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bgunebakan/toyrobot | BCD_converter.vhd | 1 | 1,896 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 06:29:02 12/18/2014
-- Design Name:
-- Module Name: BCD_converter - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity BCD_converter is
Port ( Distance_input : in STD_LOGIC_VECTOR (8 downto 0);
hundreds : out STD_LOGIC_VECTOR (3 downto 0);
tens : out STD_LOGIC_VECTOR (3 downto 0);
unit : out STD_LOGIC_VECTOR (3 downto 0));
end BCD_converter;
architecture Behavioral of BCD_converter is
begin
process(Distance_input)
variable i : integer :=0;
variable bcd : std_logic_vector(20 downto 0);
begin
bcd := (others => '0');
bcd(8 downto 0) := Distance_input;
for i in 0 to 8 loop
bcd(19 downto 0 ):= bcd(18 downto 0) & '0';
if(i<8 and bcd(12 downto 9) > "0100" ) then
bcd(12 downto 9 ):= bcd(12 downto 9)+ "0011";
end if;
if(i<8 and bcd(16 downto 13) > "0100" ) then
bcd(16 downto 13 ):= bcd(16 downto 13)+ "0011";
end if;
if(i<8 and bcd(20 downto 17) > "0100" ) then
bcd(20 downto 17 ):= bcd(20 downto 17)+ "0011";
end if;
end loop;
hundreds <= bcd(20 downto 17);
tens <= bcd(16 downto 13);
unit <= bcd(12 downto 9);
end process;
end Behavioral;
| gpl-2.0 | 5760d8179bb100bc7ec196733a59b0a9 | 0.583333 | 3.472527 | false | false | false | false |
chiggs/nvc | test/regress/protected1.vhd | 5 | 1,241 | entity protected1 is
end entity;
architecture test of protected1 is
type SharedCounter is protected
procedure increment (N: Integer := 1);
procedure decrement (N: Integer := 1);
impure function value return Integer;
end protected SharedCounter;
type SharedCounter is protected body
variable counter: Integer := 0;
variable dummy: Integer;
procedure increment (N: Integer := 1) is
begin
counter := counter + N;
end procedure increment;
procedure decrement (N: Integer := 1) is
begin
counter := counter - N;
end procedure decrement;
impure function value return Integer is
begin
return counter;
end function value;
end protected body;
shared variable x : SharedCounter;
begin
process is
begin
assert x.value = 0;
x.increment;
report "value is now " & integer'image(x.value);
x.increment(2);
assert x.value = 3;
wait;
end process;
process is
begin
wait for 1 ns;
assert x.value = 3;
x.decrement;
assert x.value = 2;
wait;
end process;
end architecture;
| gpl-3.0 | 82d79aee063dbdbcb23e70ff99dceb2a | 0.585012 | 4.828794 | false | false | false | false |
chiggs/nvc | test/regress/slice1.vhd | 5 | 810 | entity slice1 is
end entity;
architecture test of slice1 is
type int_vector is array (integer range <>) of integer;
signal x : int_vector(0 to 3);
begin
process is
variable u : int_vector(5 downto 2);
variable v : int_vector(0 to 3);
begin
v := ( 1, 2, 3, 4 );
v(1 to 2) := ( 6, 7 );
assert v = ( 1, 6, 7, 4 );
assert v(2 to 3) = ( 7, 4 );
x <= ( 1, 2, 3, 4 );
wait for 1 ns;
x(1 to 2) <= ( 6, 7 );
wait for 1 ns;
assert x = ( 1, 6, 7, 4 );
assert x(2 to 3) = ( 7, 4 );
u := ( 1, 2, 3, 4);
assert u = ( 1, 2, 3, 4);
u(4 downto 3) := ( 6, 7 );
assert u = ( 1, 6, 7, 4 );
assert u(3 downto 2) = ( 7, 4 );
wait;
end process;
end architecture;
| gpl-3.0 | 456d0985a61da804e03bbc1b7b2f1af3 | 0.435802 | 3.033708 | false | false | false | false |
markusC64/1541ultimate2 | fpga/ip/busses/vhdl_source/mem_bus_pkg.vhd | 2 | 2,584 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package mem_bus_pkg is
type t_mem_req is record
tag : std_logic_vector(7 downto 0);
request : std_logic;
read_writen : std_logic;
size : unsigned(1 downto 0); -- +1 for reads only
address : unsigned(25 downto 0);
data : std_logic_vector(7 downto 0);
end record;
type t_mem_resp is record
data : std_logic_vector(7 downto 0);
rack : std_logic;
rack_tag : std_logic_vector(7 downto 0);
dack_tag : std_logic_vector(7 downto 0);
count : unsigned(1 downto 0);
end record;
constant c_mem_req_init : t_mem_req := (
tag => X"00",
request => '0',
read_writen => '1',
size => "00",
address => (others => '0'),
data => X"00" );
constant c_mem_resp_init : t_mem_resp := (
data => X"00",
rack => '0',
rack_tag => X"00",
dack_tag => X"00",
count => "00" );
type t_mem_req_array is array(natural range <>) of t_mem_req;
type t_mem_resp_array is array(natural range <>) of t_mem_resp;
----
type t_mem_req_32 is record
tag : std_logic_vector(7 downto 0);
request : std_logic;
read_writen : std_logic;
address : unsigned(25 downto 0);
byte_en : std_logic_vector(3 downto 0);
data : std_logic_vector(31 downto 0);
end record;
type t_mem_resp_32 is record
data : std_logic_vector(31 downto 0);
rack : std_logic;
rack_tag : std_logic_vector(7 downto 0);
dack_tag : std_logic_vector(7 downto 0);
end record;
constant c_mem_req_32_init : t_mem_req_32 := (
tag => X"00",
request => '0',
read_writen => '1',
address => (others => '0'),
data => X"00000000",
byte_en => "0000" );
constant c_mem_resp_32_init : t_mem_resp_32 := (
data => X"00000000",
rack => '0',
rack_tag => X"00",
dack_tag => X"00" );
type t_mem_req_32_array is array(natural range <>) of t_mem_req_32;
type t_mem_resp_32_array is array(natural range <>) of t_mem_resp_32;
end package;
package body mem_bus_pkg is
end package body;
| gpl-3.0 | afd471e76adcde414226514a249ee384 | 0.47291 | 3.515646 | false | false | false | false |
armandas/Arcade | missile.vhd | 2 | 3,578 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity missile is
port(
clk, not_reset: in std_logic;
px_x, px_y: in std_logic_vector(9 downto 0);
nes_a, nes_b: in std_logic;
x_position, y_position: in std_logic_vector(9 downto 0);
destruction: in std_logic;
missile_coord_x, missile_coord_y: out std_logic_vector(9 downto 0);
shooting: out std_logic;
rgb_pixel: out std_logic_vector(0 to 2)
);
end missile;
architecture behaviour of missile is
constant WIDTH: integer := 4;
constant HEIGHT: integer := 4;
type rom_type is array(0 to HEIGHT - 1) of
std_logic_vector(WIDTH - 1 downto 0);
constant MISSILE: rom_type := ("0100", "1110", "1110", "1010");
constant DELAY: integer := 50000; -- 1kHz
signal counter, counter_next: std_logic_vector(16 downto 0);
signal row_address, col_address: std_logic_vector(1 downto 0);
signal data: std_logic_vector(WIDTH - 1 downto 0);
signal output_enable: std_logic;
signal missile_ready, missile_ready_next: std_logic;
signal button_pressed: std_logic;
signal x_coordinate, x_coordinate_next: std_logic_vector(9 downto 0);
signal y_coordinate, y_coordinate_next: std_logic_vector(9 downto 0);
begin
process(clk, not_reset)
begin
if not_reset = '0' then
counter <= (others => '0');
missile_ready <= '1';
x_coordinate <= (others => '0');
y_coordinate <= (others => '0');
elsif falling_edge(clk) then
counter <= counter_next;
missile_ready <= missile_ready_next;
x_coordinate <= x_coordinate_next;
y_coordinate <= y_coordinate_next;
end if;
end process;
shooting <= '1' when (missile_ready = '1' and
missile_ready_next = '0') else
'0';
button_pressed <= '1' when (nes_a = '1' or nes_b = '1') else '0';
missile_ready_next <= '0' when (button_pressed = '1' and
missile_ready = '1') else
'1' when (destruction = '1' or
y_coordinate < 10) else
missile_ready;
output_enable <= '1' when (missile_ready = '0' and
px_x >= x_coordinate and
px_x < x_coordinate + WIDTH and
px_y >= y_coordinate and
px_y < y_coordinate + HEIGHT) else
'0';
row_address <= px_y(1 downto 0) - y_coordinate(1 downto 0);
col_address <= px_x(1 downto 0) - x_coordinate(1 downto 0);
data <= MISSILE(conv_integer(row_address));
rgb_pixel <= "111" when (output_enable = '1' and
data(conv_integer(col_address)) = '1') else
"000";
counter_next <= counter + 1 when counter < DELAY else (others => '0');
x_coordinate_next <= x_position when (missile_ready = '1' and
button_pressed = '1') else
x_coordinate when missile_ready = '0' else
(others => '0');
y_coordinate_next <= y_coordinate - 1 when (missile_ready = '0' and
counter = 0) else
y_position when missile_ready = '1' else
y_coordinate;
missile_coord_x <= x_coordinate;
missile_coord_y <= y_coordinate;
end behaviour; | bsd-2-clause | 6454a2e4391ff11b2ba76f26e3986c71 | 0.525713 | 3.923246 | false | false | false | false |
markusC64/1541ultimate2 | fpga/sid6581/vhdl_source/sid_io_regs.vhd | 1 | 4,238 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
--
-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
--
-- Note that this file is copyrighted, and is not supposed to be used in other
-- projects without written permission from the author.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.sid_io_regs_pkg.all;
entity sid_io_regs is
generic (
g_8voices : boolean := false;
g_num_voices : natural := 16 );
port (
clock : in std_logic;
reset : in std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp;
control : out t_sid_control );
end sid_io_regs;
architecture registers of sid_io_regs is
signal control_i : t_sid_control;
begin
control <= control_i;
p_bus: process(clock)
begin
if rising_edge(clock) then
io_resp <= c_io_resp_init;
if io_req.write='1' then
io_resp.ack <= '1';
case io_req.address(3 downto 0) is
when c_sid_base_left =>
control_i.base_left <= unsigned(io_req.data);
when c_sid_base_right =>
control_i.base_right <= unsigned(io_req.data);
when c_sid_snoop_left =>
control_i.snoop_left <= io_req.data(0);
when c_sid_snoop_right =>
control_i.snoop_right <= io_req.data(0);
when c_sid_enable_left =>
control_i.enable_left <= io_req.data(0);
when c_sid_enable_right =>
control_i.enable_right <= io_req.data(0);
when c_sid_extend_left =>
if g_8voices then
control_i.extend_left <= io_req.data(0);
end if;
when c_sid_extend_right =>
if g_8voices then
control_i.extend_right <= io_req.data(0);
end if;
when c_sid_wavesel_left =>
control_i.comb_wave_left <= io_req.data(0);
when c_sid_wavesel_right =>
control_i.comb_wave_right <= io_req.data(0);
when others =>
null;
end case;
elsif io_req.read='1' then
io_resp.ack <= '1';
case io_req.address(3 downto 0) is
when c_sid_voices =>
io_resp.data <= std_logic_vector(to_unsigned(g_num_voices, 8));
when c_sid_base_left =>
io_resp.data <= std_logic_vector(control_i.base_left);
when c_sid_base_right =>
io_resp.data <= std_logic_vector(control_i.base_right);
when c_sid_snoop_left =>
io_resp.data(0) <= control_i.snoop_left;
when c_sid_snoop_right =>
io_resp.data(0) <= control_i.snoop_right;
when c_sid_enable_left =>
io_resp.data(0) <= control_i.enable_left;
when c_sid_enable_right =>
io_resp.data(0) <= control_i.enable_right;
when c_sid_extend_left =>
io_resp.data(0) <= control_i.extend_left;
when c_sid_extend_right =>
io_resp.data(0) <= control_i.extend_right;
when c_sid_wavesel_left =>
io_resp.data(0) <= control_i.comb_wave_left;
when c_sid_wavesel_right =>
io_resp.data(0) <= control_i.comb_wave_right;
when others =>
null;
end case;
end if;
if reset='1' then
control_i <= c_sid_control_init;
end if;
end if;
end process;
end architecture;
| gpl-3.0 | bf2a1433c66211deec2c524f4c6d91c0 | 0.446201 | 3.949674 | false | false | false | false |
nussbrot/AdvPT | wb_test/src/vhdl/wbs_test_notify.vhd | 2 | 24,514 | -------------------------------------------------------------------------------
-- COPYRIGHT (c) SOLECTRIX GmbH, Germany, 2017 All rights reserved
--
-- The copyright to the document(s) herein is the property of SOLECTRIX GmbH
-- The document(s) may be used and/or copied only with the written permission
-- from SOLECTRIX GmbH or in accordance with the terms/conditions stipulated
-- in the agreement/contract under which the document(s) have been supplied
-------------------------------------------------------------------------------
-- Project : glb_lib
-- File : wbs_test_notify.vhd
-- Created : 18.05.2017
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
--*
--* @short Wishbone register module
--* Auto-generated by 'export_wbs.tcl' based on '../../../../sxl/tpl/wb_reg_no_rst_notify.tpl.vhd'
--*
--* Needed Libraries and Packages:
--* @li ieee.std_logic_1164 standard multi-value logic package
--* @li ieee.numeric_std
--*
--* @author rhallmen
--* @date 30.06.2016
--* @internal
--/
-------------------------------------------------------------------------------
-- Modification history :
-- Date Author & Description
-- 18.05.2017 rhallmen: Created
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
-------------------------------------------------------------------------------
ENTITY wbs_test_notify IS
GENERIC (
g_addr_bits : INTEGER := 8);
PORT (
-- Wishbone interface
clk : IN STD_LOGIC;
i_wb_cyc : IN STD_LOGIC;
i_wb_stb : IN STD_LOGIC;
i_wb_we : IN STD_LOGIC;
i_wb_sel : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
i_wb_addr : IN STD_LOGIC_VECTOR(g_addr_bits-1 DOWNTO 0);
i_wb_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
o_wb_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
o_wb_ack : OUT STD_LOGIC;
o_wb_rty : OUT STD_LOGIC;
o_wb_err : OUT STD_LOGIC;
-- Custom ports
o_rw_slice0 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
o_rw_slice1 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
o_rw_bit : OUT STD_LOGIC;
i_ro_slice0 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
i_ro_slice1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
i_ro_bit : IN STD_LOGIC;
o_wo_slice0 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
o_wo_slice1 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
o_wo_bit : OUT STD_LOGIC;
o_tr_slice0 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
o_tr_slice1 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
o_tr_bit : OUT STD_LOGIC;
o_en_bit : OUT STD_LOGIC;
o_en_slice : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
o_no_rw_rw_bit : OUT STD_LOGIC;
o_no_rw_rw_slice : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
i_no_rw_ro_bit : IN STD_LOGIC;
i_no_rw_ro_slice : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
o_no_rw_wo_bit : OUT STD_LOGIC;
o_no_rw_wo_slice : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
o_no_rw_tr_bit : OUT STD_LOGIC;
o_no_rw_tr_slice : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
o_notify_rw_trd : OUT STD_LOGIC;
o_notify_rw_twr : OUT STD_LOGIC;
o_no_ro_rw_bit : OUT STD_LOGIC;
o_no_ro_rw_slice : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
i_no_ro_ro_bit : IN STD_LOGIC;
i_no_ro_ro_slice : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
o_no_ro_wo_bit : OUT STD_LOGIC;
o_no_ro_wo_slice : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
o_no_ro_tr_bit : OUT STD_LOGIC;
o_no_ro_tr_slice : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
o_notify_ro_trd : OUT STD_LOGIC;
o_no_wo_rw_bit : OUT STD_LOGIC;
o_no_wo_rw_slice : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
i_no_wo_ro_bit : IN STD_LOGIC;
i_no_wo_ro_slice : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
o_no_wo_wo_bit : OUT STD_LOGIC;
o_no_wo_wo_slice : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
o_no_wo_tr_bit : OUT STD_LOGIC;
o_no_wo_tr_slice : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
o_notify_wo_twr : OUT STD_LOGIC;
o_const_bit0 : OUT STD_LOGIC;
o_const_bit1 : OUT STD_LOGIC;
o_const_slice0 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
o_const_slice1 : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END ENTITY wbs_test_notify;
-------------------------------------------------------------------------------
ARCHITECTURE rtl OF wbs_test_notify IS
-----------------------------------------------------------------------------
-- Procedures
-----------------------------------------------------------------------------
-- Write access to 32bit register
PROCEDURE set_reg (
i_wr_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
i_wr_en : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
i_wr_mask : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL s_reg : INOUT STD_LOGIC_VECTOR) IS
BEGIN
FOR i IN s_reg'RANGE LOOP
IF (i_wr_mask(i) = '1' AND i_wr_en(i/8) = '1') THEN
s_reg(i) <= i_wr_data(i);
END IF;
END LOOP;
END PROCEDURE set_reg;
-- Write access to single bit register.
-- Since the index is lost, we rely on the mask to set the correct value.
PROCEDURE set_reg (
i_wr_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
i_wr_en : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
i_wr_mask : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL s_reg : INOUT STD_LOGIC) IS
BEGIN
FOR i IN i_wr_mask'RANGE LOOP
IF (i_wr_mask(i) = '1' AND i_wr_en(i/8) = '1') THEN
s_reg <= i_wr_data(i);
END IF;
END LOOP;
END PROCEDURE set_reg;
-- Write access to single trigger signal
PROCEDURE set_trg (
i_wr_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
i_wr_en : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
CONSTANT c_wr_mask : IN NATURAL RANGE 0 TO 31;
SIGNAL s_flag : INOUT STD_LOGIC) IS
BEGIN
IF (i_wr_en(c_wr_mask/8) = '1' AND i_wr_data(c_wr_mask) = '1') THEN
s_flag <= '1';
ELSE
s_flag <= '0';
END IF;
END PROCEDURE set_trg;
-- Write access to trigger signal vector
PROCEDURE set_trg (
i_wr_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
i_wr_en : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
CONSTANT c_wr_mask : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL s_flag : INOUT STD_LOGIC_VECTOR) IS
BEGIN
FOR i IN 0 TO 31 LOOP
IF (c_wr_mask(i) = '1') THEN
IF (i_wr_en(i/8) = '1' AND i_wr_data(i) = '1') THEN
s_flag(i) <= '1';
ELSE
s_flag(i) <= '0';
END IF;
END IF;
END LOOP;
END PROCEDURE set_trg;
-- Drive Trigger On Write signal
PROCEDURE set_twr (
i_wr_en : IN STD_LOGIC;
SIGNAL s_flag : OUT STD_LOGIC) IS
BEGIN -- PROCEDURE set_twr
IF (i_wr_en = '1') THEN
s_flag <= '1';
ELSE
s_flag <= '0';
END IF;
END PROCEDURE set_twr;
-- Drive Trigger On Read signal
PROCEDURE set_trd (
i_rd_en : IN STD_LOGIC;
SIGNAL s_flag : OUT STD_LOGIC) IS
BEGIN -- PROCEDURE set_trd
IF (i_rd_en = '1') THEN
s_flag <= '1';
ELSE
s_flag <= '0';
END IF;
END PROCEDURE set_trd;
-- helper to cast integer to slv
FUNCTION f_reset_cast(number : NATURAL; len : POSITIVE)
RETURN STD_LOGIC_VECTOR IS
BEGIN
RETURN STD_LOGIC_VECTOR(to_unsigned(number, len));
END FUNCTION f_reset_cast;
-----------------------------------------------------------------------------
-- Constants
-----------------------------------------------------------------------------
CONSTANT c_addr_read_write : INTEGER := 16#0000#;
CONSTANT c_addr_read_only : INTEGER := 16#0004#;
CONSTANT c_addr_write_only : INTEGER := 16#0008#;
CONSTANT c_addr_trigger : INTEGER := 16#000C#;
CONSTANT c_addr_enum : INTEGER := 16#0010#;
CONSTANT c_addr_notify_rw : INTEGER := 16#0014#;
CONSTANT c_addr_notify_ro : INTEGER := 16#0018#;
CONSTANT c_addr_notify_wo : INTEGER := 16#001C#;
CONSTANT c_addr_const : INTEGER := 16#0020#;
CONSTANT c_has_read_notifies : BOOLEAN := TRUE;
-----------------------------------------------------------------------------
-- WB interface signals
-----------------------------------------------------------------------------
SIGNAL s_wb_ack : STD_LOGIC;
SIGNAL s_wb_err : STD_LOGIC;
SIGNAL s_wb_addr : UNSIGNED(i_wb_addr'HIGH DOWNTO 0);
SIGNAL s_int_addr : UNSIGNED(i_wb_addr'HIGH DOWNTO 0);
SIGNAL s_int_data : STD_LOGIC_VECTOR(i_wb_data'RANGE);
SIGNAL s_int_we : STD_LOGIC_VECTOR(i_wb_sel'RANGE);
SIGNAL s_int_trd : STD_LOGIC;
SIGNAL s_int_twr : STD_LOGIC;
SIGNAL s_int_addr_valid : STD_LOGIC;
SIGNAL s_int_data_rb : STD_LOGIC_VECTOR(i_wb_data'RANGE);
SIGNAL s_wb_data : STD_LOGIC_VECTOR(o_wb_data'RANGE);
TYPE t_wb_state IS (e_idle, e_delay, e_ack);
SIGNAL s_wb_state : t_wb_state := e_idle;
-----------------------------------------------------------------------------
-- Custom registers
-----------------------------------------------------------------------------
SIGNAL s_rw_rw_slice0 : STD_LOGIC_VECTOR(31 DOWNTO 16) := f_reset_cast(0, 16);
SIGNAL s_rw_rw_slice1 : STD_LOGIC_VECTOR(15 DOWNTO 8) := f_reset_cast(0, 8);
SIGNAL s_rw_rw_bit : STD_LOGIC := '0';
SIGNAL s_wo_wo_slice0 : STD_LOGIC_VECTOR(31 DOWNTO 16) := f_reset_cast(0, 16);
SIGNAL s_wo_wo_slice1 : STD_LOGIC_VECTOR(15 DOWNTO 8) := f_reset_cast(0, 8);
SIGNAL s_wo_wo_bit : STD_LOGIC := '0';
SIGNAL s_trg_tr_slice0 : STD_LOGIC_VECTOR(31 DOWNTO 16) := f_reset_cast(0, 16);
SIGNAL s_trg_tr_slice1 : STD_LOGIC_VECTOR(15 DOWNTO 8) := f_reset_cast(0, 8);
SIGNAL s_trg_tr_bit : STD_LOGIC := '0';
SIGNAL s_rw_en_bit : STD_LOGIC := '1';
SIGNAL s_rw_en_slice : STD_LOGIC_VECTOR(13 DOWNTO 12) := f_reset_cast(2, 2);
SIGNAL s_rw_no_rw_rw_bit : STD_LOGIC := '0';
SIGNAL s_rw_no_rw_rw_slice : STD_LOGIC_VECTOR(30 DOWNTO 24) := f_reset_cast(111, 7);
SIGNAL s_wo_no_rw_wo_bit : STD_LOGIC := '0';
SIGNAL s_wo_no_rw_wo_slice : STD_LOGIC_VECTOR(14 DOWNTO 8) := f_reset_cast(111, 7);
SIGNAL s_trg_no_rw_tr_bit : STD_LOGIC := '0';
SIGNAL s_trg_no_rw_tr_slice : STD_LOGIC_VECTOR(6 DOWNTO 0) := f_reset_cast(111, 7);
SIGNAL s_rw_no_ro_rw_bit : STD_LOGIC := '0';
SIGNAL s_rw_no_ro_rw_slice : STD_LOGIC_VECTOR(30 DOWNTO 24) := f_reset_cast(111, 7);
SIGNAL s_wo_no_ro_wo_bit : STD_LOGIC := '0';
SIGNAL s_wo_no_ro_wo_slice : STD_LOGIC_VECTOR(14 DOWNTO 8) := f_reset_cast(111, 7);
SIGNAL s_trg_no_ro_tr_bit : STD_LOGIC := '0';
SIGNAL s_trg_no_ro_tr_slice : STD_LOGIC_VECTOR(6 DOWNTO 0) := f_reset_cast(111, 7);
SIGNAL s_rw_no_wo_rw_bit : STD_LOGIC := '0';
SIGNAL s_rw_no_wo_rw_slice : STD_LOGIC_VECTOR(30 DOWNTO 24) := f_reset_cast(111, 7);
SIGNAL s_wo_no_wo_wo_bit : STD_LOGIC := '0';
SIGNAL s_wo_no_wo_wo_slice : STD_LOGIC_VECTOR(14 DOWNTO 8) := f_reset_cast(111, 7);
SIGNAL s_trg_no_wo_tr_bit : STD_LOGIC := '0';
SIGNAL s_trg_no_wo_tr_slice : STD_LOGIC_VECTOR(6 DOWNTO 0) := f_reset_cast(111, 7);
SIGNAL s_const_const_bit0 : STD_LOGIC := '1';
SIGNAL s_const_const_bit1 : STD_LOGIC := '0';
SIGNAL s_const_const_slice0 : STD_LOGIC_VECTOR(31 DOWNTO 24) := f_reset_cast(113, 8);
SIGNAL s_const_const_slice1 : STD_LOGIC_VECTOR(13 DOWNTO 9) := f_reset_cast(17, 5);
BEGIN -- ARCHITECTURE rtl
-----------------------------------------------------------------------------
--* purpose : Wishbone Bus Control
--* type : sequential, rising edge, no reset
wb_ctrl : PROCESS (clk)
BEGIN
IF rising_edge(clk) THEN
s_wb_ack <= '0';
s_wb_err <= '0';
s_int_data <= i_wb_data;
s_int_addr <= s_wb_addr;
s_int_we <= (OTHERS => '0');
s_int_trd <= '0';
s_int_twr <= '0';
CASE s_wb_state IS
WHEN e_idle =>
-- check if anyone requests access
IF (i_wb_cyc = '1' AND i_wb_stb = '1') THEN
-- ack is delayed because we need 3 cycles
IF (i_wb_we = '1') THEN
s_wb_ack <= s_int_addr_valid;
s_wb_err <= NOT s_int_addr_valid;
s_wb_state <= e_ack;
s_int_we <= i_wb_sel;
s_int_twr <= '1';
ELSE
IF c_has_read_notifies THEN
s_wb_state <= e_delay;
s_int_trd <= '1';
ELSE
s_wb_ack <= s_int_addr_valid;
s_wb_err <= NOT s_int_addr_valid;
s_wb_state <= e_ack;
END IF;
END IF;
END IF;
WHEN e_delay =>
s_wb_ack <= s_int_addr_valid;
s_wb_err <= NOT s_int_addr_valid;
s_wb_state <= e_ack;
WHEN e_ack =>
s_wb_state <= e_idle;
END CASE;
s_wb_data <= s_int_data_rb;
END IF;
END PROCESS wb_ctrl;
s_wb_addr <= UNSIGNED(i_wb_addr);
o_wb_data <= s_wb_data;
o_wb_ack <= s_wb_ack;
o_wb_err <= s_wb_err;
o_wb_rty <= '0';
-----------------------------------------------------------------------------
-- WB address validation
WITH to_integer(s_wb_addr) SELECT
s_int_addr_valid <=
'1' WHEN c_addr_read_write,
'1' WHEN c_addr_read_only,
'1' WHEN c_addr_write_only,
'1' WHEN c_addr_trigger,
'1' WHEN c_addr_enum,
'1' WHEN c_addr_notify_rw,
'1' WHEN c_addr_notify_ro,
'1' WHEN c_addr_notify_wo,
'1' WHEN c_addr_const,
'0' WHEN OTHERS;
-----------------------------------------------------------------------------
--* purpose : register access
--* type : sequential, rising edge, high active synchronous reset
reg_access : PROCESS (clk)
BEGIN -- PROCESS reg_access
IF rising_edge(clk) THEN
-- default values / clear trigger signals
s_trg_tr_slice0 <= (OTHERS => '0');
s_trg_tr_slice1 <= (OTHERS => '0');
s_trg_tr_bit <= '0';
s_trg_no_rw_tr_bit <= '0';
s_trg_no_rw_tr_slice <= (OTHERS => '0');
s_trg_no_ro_tr_bit <= '0';
s_trg_no_ro_tr_slice <= (OTHERS => '0');
s_trg_no_wo_tr_bit <= '0';
s_trg_no_wo_tr_slice <= (OTHERS => '0');
o_notify_rw_trd <= '0';
o_notify_rw_twr <= '0';
o_notify_ro_trd <= '0';
o_notify_wo_twr <= '0';
-- WRITE registers
CASE to_integer(s_int_addr) IS
WHEN c_addr_read_write => set_reg(s_int_data, s_int_we, x"FFFF0000", s_rw_rw_slice0);
set_reg(s_int_data, s_int_we, x"0000FF00", s_rw_rw_slice1);
set_reg(s_int_data, s_int_we, x"00000008", s_rw_rw_bit);
WHEN c_addr_write_only => set_reg(s_int_data, s_int_we, x"FFFF0000", s_wo_wo_slice0);
set_reg(s_int_data, s_int_we, x"0000FF00", s_wo_wo_slice1);
set_reg(s_int_data, s_int_we, x"00000008", s_wo_wo_bit);
WHEN c_addr_trigger => set_trg(s_int_data, s_int_we, x"FFFF0000", s_trg_tr_slice0);
set_trg(s_int_data, s_int_we, x"0000FF00", s_trg_tr_slice1);
set_trg(s_int_data, s_int_we, 3, s_trg_tr_bit);
WHEN c_addr_enum => set_reg(s_int_data, s_int_we, x"80000000", s_rw_en_bit);
set_reg(s_int_data, s_int_we, x"00003000", s_rw_en_slice);
WHEN c_addr_notify_rw => set_reg(s_int_data, s_int_we, x"80000000", s_rw_no_rw_rw_bit);
set_reg(s_int_data, s_int_we, x"7F000000", s_rw_no_rw_rw_slice);
set_reg(s_int_data, s_int_we, x"00008000", s_wo_no_rw_wo_bit);
set_reg(s_int_data, s_int_we, x"00007F00", s_wo_no_rw_wo_slice);
set_trg(s_int_data, s_int_we, 7, s_trg_no_rw_tr_bit);
set_trg(s_int_data, s_int_we, x"0000007F", s_trg_no_rw_tr_slice);
set_trd(s_int_trd, o_notify_rw_trd);
set_twr(s_int_twr, o_notify_rw_twr);
WHEN c_addr_notify_ro => set_reg(s_int_data, s_int_we, x"80000000", s_rw_no_ro_rw_bit);
set_reg(s_int_data, s_int_we, x"7F000000", s_rw_no_ro_rw_slice);
set_reg(s_int_data, s_int_we, x"00008000", s_wo_no_ro_wo_bit);
set_reg(s_int_data, s_int_we, x"00007F00", s_wo_no_ro_wo_slice);
set_trg(s_int_data, s_int_we, 7, s_trg_no_ro_tr_bit);
set_trg(s_int_data, s_int_we, x"0000007F", s_trg_no_ro_tr_slice);
set_trd(s_int_trd, o_notify_ro_trd);
WHEN c_addr_notify_wo => set_reg(s_int_data, s_int_we, x"80000000", s_rw_no_wo_rw_bit);
set_reg(s_int_data, s_int_we, x"7F000000", s_rw_no_wo_rw_slice);
set_reg(s_int_data, s_int_we, x"00008000", s_wo_no_wo_wo_bit);
set_reg(s_int_data, s_int_we, x"00007F00", s_wo_no_wo_wo_slice);
set_trg(s_int_data, s_int_we, 7, s_trg_no_wo_tr_bit);
set_trg(s_int_data, s_int_we, x"0000007F", s_trg_no_wo_tr_slice);
set_twr(s_int_twr, o_notify_wo_twr);
WHEN OTHERS => NULL;
END CASE;
END IF;
END PROCESS reg_access;
-----------------------------------------------------------------------------
p_comb_read_mux : PROCESS(s_wb_addr, s_rw_rw_slice0, s_rw_rw_slice1, s_rw_rw_bit, i_ro_slice0, i_ro_slice1, i_ro_bit, s_rw_en_bit, s_rw_en_slice, s_rw_no_rw_rw_bit, s_rw_no_rw_rw_slice, i_no_rw_ro_bit, i_no_rw_ro_slice, s_rw_no_ro_rw_bit, s_rw_no_ro_rw_slice, i_no_ro_ro_bit, i_no_ro_ro_slice, s_rw_no_wo_rw_bit, s_rw_no_wo_rw_slice, i_no_wo_ro_bit, i_no_wo_ro_slice)
VARIABLE v_tmp_read_write : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
VARIABLE v_tmp_read_only : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
VARIABLE v_tmp_enum : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
VARIABLE v_tmp_notify_rw : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
VARIABLE v_tmp_notify_ro : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
VARIABLE v_tmp_notify_wo : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
VARIABLE v_tmp_const : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
-- helper to ease template generation
PROCEDURE set(
l_input : STD_LOGIC_VECTOR(31 DOWNTO 0);
l_mask : STD_LOGIC_VECTOR(31 DOWNTO 0)) IS
BEGIN
s_int_data_rb <= l_input AND l_mask;
END PROCEDURE;
BEGIN
-- READ registers assignments
v_tmp_read_write(31 DOWNTO 16) := s_rw_rw_slice0;
v_tmp_read_write(15 DOWNTO 8) := s_rw_rw_slice1;
v_tmp_read_write(3) := s_rw_rw_bit;
v_tmp_read_only(31 DOWNTO 16) := i_ro_slice0;
v_tmp_read_only(15 DOWNTO 8) := i_ro_slice1;
v_tmp_read_only(3) := i_ro_bit;
v_tmp_enum(31) := s_rw_en_bit;
v_tmp_enum(13 DOWNTO 12) := s_rw_en_slice;
v_tmp_notify_rw(31) := s_rw_no_rw_rw_bit;
v_tmp_notify_rw(30 DOWNTO 24) := s_rw_no_rw_rw_slice;
v_tmp_notify_rw(23) := i_no_rw_ro_bit;
v_tmp_notify_rw(22 DOWNTO 16) := i_no_rw_ro_slice;
v_tmp_notify_ro(31) := s_rw_no_ro_rw_bit;
v_tmp_notify_ro(30 DOWNTO 24) := s_rw_no_ro_rw_slice;
v_tmp_notify_ro(23) := i_no_ro_ro_bit;
v_tmp_notify_ro(22 DOWNTO 16) := i_no_ro_ro_slice;
v_tmp_notify_wo(31) := s_rw_no_wo_rw_bit;
v_tmp_notify_wo(30 DOWNTO 24) := s_rw_no_wo_rw_slice;
v_tmp_notify_wo(23) := i_no_wo_ro_bit;
v_tmp_notify_wo(22 DOWNTO 16) := i_no_wo_ro_slice;
v_tmp_const(7) := s_const_const_bit0;
v_tmp_const(6) := s_const_const_bit1;
v_tmp_const(31 DOWNTO 24) := s_const_const_slice0;
v_tmp_const(13 DOWNTO 9) := s_const_const_slice1;
-- WB output data multiplexer
CASE to_integer(s_wb_addr) IS
WHEN c_addr_read_write => set(v_tmp_read_write, x"FFFFFF08");
WHEN c_addr_read_only => set(v_tmp_read_only, x"FFFFFF08");
WHEN c_addr_enum => set(v_tmp_enum, x"80003000");
WHEN c_addr_notify_rw => set(v_tmp_notify_rw, x"FFFF0000");
WHEN c_addr_notify_ro => set(v_tmp_notify_ro, x"FFFF0000");
WHEN c_addr_notify_wo => set(v_tmp_notify_wo, x"FFFF0000");
WHEN c_addr_const => set(v_tmp_const, x"FF003EC0");
WHEN OTHERS => set((OTHERS => '0'), (OTHERS => '1'));
END CASE;
END PROCESS p_comb_read_mux;
-----------------------------------------------------------------------------
-- output mappings
o_rw_slice0 <= s_rw_rw_slice0(31 DOWNTO 16);
o_rw_slice1 <= s_rw_rw_slice1(15 DOWNTO 8);
o_rw_bit <= s_rw_rw_bit;
o_wo_slice0 <= s_wo_wo_slice0(31 DOWNTO 16);
o_wo_slice1 <= s_wo_wo_slice1(15 DOWNTO 8);
o_wo_bit <= s_wo_wo_bit;
o_tr_slice0 <= s_trg_tr_slice0(31 DOWNTO 16);
o_tr_slice1 <= s_trg_tr_slice1(15 DOWNTO 8);
o_tr_bit <= s_trg_tr_bit;
o_en_bit <= s_rw_en_bit;
o_en_slice <= s_rw_en_slice(13 DOWNTO 12);
o_no_rw_rw_bit <= s_rw_no_rw_rw_bit;
o_no_rw_rw_slice <= s_rw_no_rw_rw_slice(30 DOWNTO 24);
o_no_rw_wo_bit <= s_wo_no_rw_wo_bit;
o_no_rw_wo_slice <= s_wo_no_rw_wo_slice(14 DOWNTO 8);
o_no_rw_tr_bit <= s_trg_no_rw_tr_bit;
o_no_rw_tr_slice <= s_trg_no_rw_tr_slice(6 DOWNTO 0);
o_no_ro_rw_bit <= s_rw_no_ro_rw_bit;
o_no_ro_rw_slice <= s_rw_no_ro_rw_slice(30 DOWNTO 24);
o_no_ro_wo_bit <= s_wo_no_ro_wo_bit;
o_no_ro_wo_slice <= s_wo_no_ro_wo_slice(14 DOWNTO 8);
o_no_ro_tr_bit <= s_trg_no_ro_tr_bit;
o_no_ro_tr_slice <= s_trg_no_ro_tr_slice(6 DOWNTO 0);
o_no_wo_rw_bit <= s_rw_no_wo_rw_bit;
o_no_wo_rw_slice <= s_rw_no_wo_rw_slice(30 DOWNTO 24);
o_no_wo_wo_bit <= s_wo_no_wo_wo_bit;
o_no_wo_wo_slice <= s_wo_no_wo_wo_slice(14 DOWNTO 8);
o_no_wo_tr_bit <= s_trg_no_wo_tr_bit;
o_no_wo_tr_slice <= s_trg_no_wo_tr_slice(6 DOWNTO 0);
o_const_bit0 <= s_const_const_bit0;
o_const_bit1 <= s_const_const_bit1;
o_const_slice0 <= s_const_const_slice0(31 DOWNTO 24);
o_const_slice1 <= s_const_const_slice1(13 DOWNTO 9);
END ARCHITECTURE rtl;
| mit | d39a479adb5216eb1c1d4bc8e7795513 | 0.474586 | 3.12998 | false | false | false | false |
markusC64/1541ultimate2 | fpga/altera/xilinx_primitives/unisim_VPKG.vhd | 1 | 52,098 | -- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisim_VPKG.vhd,v 1.19 2010/12/08 18:25:32 fphillip Exp $
----------------------------------------------------------------
--
-- Created by the Synopsys Library Compiler v3.4b
-- FILENAME : unisim_VPKG.vhd
-- FILE CONTENTS: VITAL Table, hex-to-std_logic_vector conversion function,
-- and adderess decoder function Package
-- DATE CREATED : Thu Sep 12 14:45:01 1996
--
-- LIBRARY : UNISIM (UNIfied SIMulation)
-- DATE ENTERED : Fri Jun 21 11:34:03 1996
-- REVISION : 1.0.2
-- TECHNOLOGY : FPGA
-- TIME SCALE : 1 NS
-- LOGIC SYSTEM : IEEE-1164
-- NOTES :
-- HISTORY : 1. First created by runnning Synopsys LC V3.4b. DP, 09/12/96.
-- 2. Changed package name from VTABLES to VPKG. DP, 09/13/96.
-- 3. Added RAM_O_tab and RAMS_O_tab state tables. DP, 09/13/96.
-- 4. Added HEX_TO_SLV16, HEX_TO_SLV32, DECODE_ADDR4, and
-- DECODE_ADDR5 function, and XilinxIDENT procedure declarations.
-- DP, 09/13/96.
-- 5. Added package body with above functions and procedure.
-- DP, 09/13/96.
-- 6. Changed file name from XUP_VPKG.vhd to unisim_VPKG.vhd.
-- DP, 09/25/97.
-- 7. Added FD_Q_tab and FDE_Q_tab. DP, 09/25/97.
-- 8. Removed XilinxIDENT. DP, 09/26/97.
-- 9. Added VITAL state tables for Virtex flip flops and
-- latches. DP, 10/28/97.
-- 10. Added ADDR_IS_VALID and SLV_TO_STR functions and SET_MEM_TO_X,
-- ADDR_OVERLAP and COLLISION procedures for Virtex block
-- RAMs. DP, 10/28/97.
-- 11. Fixed bug in ADDR_OVERLAP procedure. DP, 04/04/98.
-- 12. Added SLV_TO_INT function. SG, 09/15/98
-- 13. Added "IN" in SLV_TO_INT function decl.SG, 12/09/98.
-- 14. Fixed a bug in SLV_TO_STR function. SG, 01/06/99.
-- 15. Added type_std_logic_vector1,2,3,4 -- CR 225004 -- FP, 02/08/06
-- 16. Changed type_std_logic_vector1,2,3,4 to integer range instead of natural -- CR 520723 -- FP, 05/08/09
-- 17. Removed "synopsys translate_off/on" -- CR 585467 -- 12/08/10
----------------------------------------------------------------
LIBRARY STD;
USE STD.TEXTIO.ALL;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
package VPKG is
type OtherGenericsType is record
BooleanVal : BOOLEAN;
IntegerVal : INTEGER;
end record;
type memory_collision_type is (Read_A_Write_B,
Read_B_Write_A,
Write_A_Write_B);
type std_logic_vector1 is array (integer range <>) of std_logic;
type std_logic_vector2 is array (integer range <>, integer range <>) of std_logic;
type std_logic_vector3 is array (integer range <>, integer range <>, integer range <>) of std_logic;
type std_logic_vector4 is array (integer range <>, integer range <>, integer range <>, integer range <>) of std_logic;
CONSTANT L : VitalTableSymbolType := '0';
CONSTANT H : VitalTableSymbolType := '1';
CONSTANT x : VitalTableSymbolType := '-';
CONSTANT S : VitalTableSymbolType := 'S';
CONSTANT R : VitalTableSymbolType := '/';
CONSTANT U : VitalTableSymbolType := 'X';
CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising)
CONSTANT FD_Q_tab : VitalStateTableType := (
( L, L, H, x, L ),
( L, H, H, x, H ),
( H, x, x, x, S ),
( x, x, L, x, S ));
CONSTANT FDC_Q_tab : VitalStateTableType := (
( L, L, H, x, x, L ),
( L, H, H, L, x, H ),
( H, x, x, L, x, S ),
( x, x, L, L, x, S ),
( x, x, x, H, x, L ));
CONSTANT FDCE_Q_tab : VitalStateTableType := (
( L, L, L, x, H, x, x, L ),
( L, L, x, L, H, x, x, L ),
( L, H, H, x, H, L, x, H ),
( L, H, x, L, H, L, x, H ),
( L, x, L, H, H, x, x, L ),
( L, x, H, H, H, L, x, H ),
( H, x, x, x, x, L, x, S ),
( x, x, x, x, L, L, x, S ),
( x, x, x, x, x, H, x, L ));
CONSTANT FDCP_Q_tab : VitalStateTableType := (
( L, L, L, H, x, x, L ),
( L, H, x, H, L, x, H ),
( H, x, L, x, L, x, S ),
( x, x, L, L, L, x, S ),
( x, x, H, x, L, x, H ),
( x, x, x, x, H, x, L ));
CONSTANT FDCPE_Q_tab : VitalStateTableType := (
( L, L, L, L, x, H, x, x, L ),
( L, L, L, x, L, H, x, x, L ),
( L, L, x, L, H, H, x, x, L ),
( L, x, H, H, x, H, L, x, H ),
( L, x, H, x, L, H, L, x, H ),
( L, x, x, H, H, H, L, x, H ),
( H, L, x, x, x, x, L, x, S ),
( x, L, x, x, x, L, L, x, S ),
( x, H, x, x, x, x, L, x, H ),
( x, x, x, x, x, x, H, x, L ));
CONSTANT FDE_Q_tab : VitalStateTableType := (
( L, L, L, x, H, x, L ),
( L, L, x, L, H, x, L ),
( L, H, H, x, H, x, H ),
( L, H, x, L, H, x, H ),
( L, x, L, H, H, x, L ),
( L, x, H, H, H, x, H ),
( H, x, x, x, x, x, S ),
( x, x, x, x, L, x, S ));
CONSTANT FDP_Q_tab : VitalStateTableType := (
( L, L, L, H, x, L ),
( L, H, x, H, x, H ),
( H, x, L, x, x, S ),
( x, x, L, L, x, S ),
( x, x, H, x, x, H ));
CONSTANT FDPE_Q_tab : VitalStateTableType := (
( L, L, L, L, x, H, x, L ),
( L, L, L, x, L, H, x, L ),
( L, L, x, L, H, H, x, L ),
( L, x, H, H, x, H, x, H ),
( L, x, H, x, L, H, x, H ),
( L, x, x, H, H, H, x, H ),
( H, L, x, x, x, x, x, S ),
( x, L, x, x, x, L, x, S ),
( x, H, x, x, x, x, x, H ));
CONSTANT FDR_Q_tab : VitalStateTableType := (
( L, L, x, H, x, L ),
( L, H, L, H, x, H ),
( L, x, H, H, x, L ),
( H, x, x, x, x, S ),
( x, x, x, L, x, S ));
CONSTANT FDRE_Q_tab : VitalStateTableType := (
( L, L, L, x, x, H, x, L ),
( L, L, x, L, x, H, x, L ),
( L, H, H, x, L, H, x, H ),
( L, H, x, L, L, H, x, H ),
( L, x, L, H, x, H, x, L ),
( L, x, H, H, L, H, x, H ),
( L, x, x, x, H, H, x, L ),
( H, x, x, x, x, x, x, S ),
( x, x, x, x, x, L, x, S ));
CONSTANT FDRS_Q_tab : VitalStateTableType := (
( L, L, L, x, H, x, L ),
( L, H, x, L, H, x, H ),
( L, x, H, L, H, x, H ),
( L, x, x, H, H, x, L ),
( H, x, x, x, x, x, S ),
( x, x, x, x, L, x, S ));
CONSTANT FDRSE_Q_tab : VitalStateTableType := (
( L, L, L, L, x, x, H, x, L ),
( L, L, L, x, L, x, H, x, L ),
( L, L, x, L, H, x, H, x, L ),
( L, H, x, x, x, L, H, x, H ),
( L, x, H, H, x, L, H, x, H ),
( L, x, H, x, L, L, H, x, H ),
( L, x, x, H, H, L, H, x, H ),
( L, x, x, x, x, H, H, x, L ),
( H, x, x, x, x, x, x, x, S ),
( x, x, x, x, x, x, L, x, S ));
CONSTANT FDS_Q_tab : VitalStateTableType := (
( L, L, L, H, x, L ),
( L, H, x, H, x, H ),
( L, x, H, H, x, H ),
( H, x, x, x, x, S ),
( x, x, x, L, x, S ));
CONSTANT FDSE_Q_tab : VitalStateTableType := (
( L, L, L, L, x, H, x, L ),
( L, L, L, x, L, H, x, L ),
( L, L, x, L, H, H, x, L ),
( L, H, x, x, x, H, x, H ),
( L, x, H, H, x, H, x, H ),
( L, x, H, x, L, H, x, H ),
( L, x, x, H, H, H, x, H ),
( H, x, x, x, x, x, x, S ),
( x, x, x, x, x, L, x, S ));
CONSTANT FDPC_Q_tab : VitalStateTableType := (
( L, L, L, H, x, x, L ),
( L, H, x, x, L, x, S ),
( L, x, x, L, L, x, S ),
( L, x, x, x, H, x, L ),
( H, x, x, x, x, x, H ),
( x, L, H, H, L, x, H ));
CONSTANT FTC_Q_tab : VitalStateTableType := (
( L, L, L, H, x, x, L ),
( L, L, H, H, L, x, H ),
( L, H, L, H, L, x, H ),
( L, H, H, H, x, x, L ),
( H, x, x, x, L, x, S ),
( x, x, x, L, L, x, S ),
( x, x, x, x, H, x, L ));
CONSTANT FTP_Q_tab : VitalStateTableType := (
( L, L, L, L, H, x, L ),
( L, L, H, H, H, x, L ),
( L, x, L, H, H, x, H ),
( L, x, H, L, H, x, H ),
( H, L, x, x, x, x, S ),
( x, L, x, x, L, x, S ),
( x, H, x, x, x, x, H ));
CONSTANT FTCP_Q_tab : VitalStateTableType := (
( L, L, L, L, H, x, x, L ),
( L, L, H, H, H, x, x, L ),
( L, x, L, H, H, L, x, H ),
( L, x, H, L, H, L, x, H ),
( H, L, x, x, x, L, x, S ),
( x, L, x, x, L, L, x, S ),
( x, H, x, x, x, L, x, H ),
( x, x, x, x, x, H, x, L ));
CONSTANT IFD_Q_tab : VitalStateTableType := (
( L, L, H, x, L ),
( L, H, H, x, H ),
( H, x, x, x, S ),
( x, x, L, x, S ));
CONSTANT IFDX_Q_tab : VitalStateTableType := (
( L, L, L, x, H, x, L ),
( L, L, x, L, H, x, L ),
( L, H, H, x, H, x, H ),
( L, H, x, L, H, x, H ),
( L, x, L, H, H, x, L ),
( L, x, H, H, H, x, H ),
( H, x, x, x, x, x, S ),
( x, x, x, x, L, x, S ));
CONSTANT ILD_Q_tab : VitalStateTableType := (
( L, H, x, L ),
( H, H, x, H ),
( x, L, x, S ));
CONSTANT ILDI_1_Q_tab : VitalStateTableType := (
( L, L, x, L ),
( L, H, x, H ),
( H, x, x, S ));
CONSTANT ILFFX_Q_tab : VitalStateTableType := (
( L, L, L, x, H, H, x, L ),
( L, L, x, H, H, H, x, L ),
( L, H, H, x, H, H, x, H ),
( L, H, x, H, H, H, x, H ),
( L, x, L, L, H, H, x, L ),
( L, x, H, L, H, H, x, H ),
( H, x, x, x, x, x, x, S ),
( x, x, x, x, L, x, x, S ),
( x, x, x, x, x, L, x, S ));
CONSTANT ILFLX_Q_tab : VitalStateTableType := (
( L, L, x, H, H, x, L ),
( L, x, H, H, H, x, L ),
( H, H, x, H, H, x, H ),
( H, x, H, H, H, x, H ),
( x, L, L, H, H, x, L ),
( x, H, L, H, H, x, H ),
( x, x, x, L, x, x, S ),
( x, x, x, x, L, x, S ));
CONSTANT ILFLXI_1_Q_tab : VitalStateTableType := (
( L, L, L, x, H, x, L ),
( L, L, x, H, H, x, L ),
( L, H, H, x, H, x, H ),
( L, H, x, H, H, x, H ),
( L, x, L, L, H, x, L ),
( L, x, H, L, H, x, H ),
( H, x, x, x, x, x, S ),
( x, x, x, x, L, x, S ));
CONSTANT ILFFXI_F_Q_tab : VitalStateTableType := (
( L, L, L, x, H, H, x, L ),
( L, L, x, H, H, H, x, L ),
( L, H, H, x, H, H, x, H ),
( L, H, x, H, H, H, x, H ),
( L, x, L, L, H, H, x, L ),
( L, x, H, L, H, H, x, H ),
( H, x, x, x, x, x, x, S ),
( x, x, x, x, L, x, x, S ),
( x, x, x, x, x, L, x, S ));
CONSTANT ILFFXI_F_INT_tab : VitalStateTableType := (
( L, L, x, L ),
( L, H, x, H ),
( H, x, x, S ));
CONSTANT ILFLXI_1F_Q_tab : VitalStateTableType := (
( L, L, L, x, H, x, L ),
( L, L, x, H, H, x, L ),
( L, H, H, x, H, x, H ),
( L, H, x, H, H, x, H ),
( L, x, L, L, H, x, L ),
( L, x, H, L, H, x, H ),
( H, x, x, x, x, x, S ),
( x, x, x, x, L, x, S ));
CONSTANT ILFLX_F_Q_tab : VitalStateTableType := (
( L, L, x, H, H, x, L ),
( L, x, H, H, H, x, L ),
( H, H, x, H, H, x, H ),
( H, x, H, H, H, x, H ),
( x, L, L, H, H, x, L ),
( x, H, L, H, H, x, H ),
( x, x, x, L, x, x, S ),
( x, x, x, x, L, x, S ));
CONSTANT LDC_Q_tab : VitalStateTableType := (
( L, H, x, x, L ),
( H, H, L, x, H ),
( x, L, L, x, S ),
( x, x, H, x, L ));
CONSTANT LDCE_Q_tab : VitalStateTableType := (
( L, H, H, x, x, L ),
( H, H, H, L, x, H ),
( x, L, x, L, x, S ),
( x, x, L, L, x, S ),
( x, x, x, H, x, L ));
CONSTANT LDCP_Q_tab : VitalStateTableType := (
( L, L, H, x, x, L ),
( H, x, H, L, x, H ),
( x, L, L, L, x, S ),
( x, H, x, L, x, H ),
( x, x, x, H, x, L ));
CONSTANT LDCPE_Q_tab : VitalStateTableType := (
( L, L, H, H, x, x, L ),
( H, x, H, H, L, x, H ),
( x, L, L, x, L, x, S ),
( x, L, x, L, L, x, S ),
( x, H, x, x, L, x, H ),
( x, x, x, x, H, x, L ));
CONSTANT LDCP_1_Q_tab : VitalStateTableType := (
( L, L, L, x, x, L ),
( L, H, x, L, x, H ),
( H, x, L, L, x, S ),
( x, x, H, L, x, H ),
( x, x, x, H, x, L ));
CONSTANT LDC_1_Q_tab : VitalStateTableType := (
( L, L, x, x, L ),
( L, H, L, x, H ),
( H, x, L, x, S ),
( x, x, H, x, L ));
CONSTANT LDE_Q_tab : VitalStateTableType := (
( L, H, H, x, L ),
( H, H, H, x, H ),
( x, L, x, x, S ),
( x, x, L, x, S ));
CONSTANT LDP_Q_tab : VitalStateTableType := (
( L, L, H, x, L ),
( H, x, H, x, H ),
( x, L, L, x, S ),
( x, H, x, x, H ));
CONSTANT LDPE_Q_tab : VitalStateTableType := (
( L, L, H, H, x, L ),
( H, x, H, H, x, H ),
( x, L, L, x, x, S ),
( x, L, x, L, x, S ),
( x, H, x, x, x, H ));
CONSTANT LDP_1_Q_tab : VitalStateTableType := (
( L, L, L, x, L ),
( L, H, x, x, H ),
( H, x, L, x, S ),
( x, x, H, x, H ));
CONSTANT RAM_O_tab : VitalStateTableType := (
( L, H, x, L ),
( H, H, x, H ),
( x, L, x, S ));
CONSTANT RAMS_O_tab : VitalStateTableType := (
( L, L, L, x, H, x, L ),
( L, L, x, L, H, x, L ),
( L, H, H, x, H, x, H ),
( L, H, x, L, H, x, H ),
( L, x, L, H, H, x, L ),
( L, x, H, H, H, x, H ),
( H, x, x, x, x, x, S ),
( x, x, x, x, L, x, S ));
CONSTANT RAMS_O_tab_1 : VitalStateTableType := (
( H, L, L, x, L, x, L ),
( H, L, x, L, L, x, L ),
( H, H, H, x, L, x, H ),
( H, H, x, L, L, x, H ),
( H, x, L, H, L, x, L ),
( H, x, H, H, L, x, H ),
( L, x, x, x, x, x, S ),
( x, x, x, x, H, x, S ));
-------------------------------------------------------------------------------
-- COOLRUNNER STUFF
-------------------------------------------------------------------------------
CONSTANT FDD_Q_tab : VitalStateTableType := (
( L, L, H, x, L ),
( L, H, H, x, H ),
( H, L, L, x, L ),
( H, H, L, x, H ),
( H, x, x, x, S ),
( x, x, L, x, S ));
CONSTANT FDDC_Q_tab : VitalStateTableType := (
( L, L, H, x, x, L ),
( L, H, H, L, x, H ),
( H, L, L, x, x, L ),
( H, H, L, L, x, H ),
( H, x, x, L, x, S ),
( x, x, L, L, x, S ),
( x, x, x, H, x, L ));
CONSTANT FDDCE_Q_tab : VitalStateTableType := (
-- C_del Q_ D CE C_ipd CLR state Q
( L, L, L, x, H, x, x, L ),
( L, L, x, L, H, x, x, L ),
( L, H, H, x, H, L, x, H ),
( L, H, x, L, H, L, x, H ),
( L, x, L, H, H, x, x, L ),
( L, x, H, H, H, L, x, H ),
-- Duplicate of 2 lines above for falling edge
( H, x, L, H, L, x, x, L ),
( H, x, H, H, L, L, x, H ),
( H, x, x, x, x, L, x, S ),
( x, x, x, x, L, L, x, S ),
( x, x, x, x, x, H, x, L ));
CONSTANT FDDCP_Q_tab : VitalStateTableType := (
-- C_d D PRE C_i CLR S Q
( L, L, L, H, x, x, L ),
( L, H, x, H, L, x, H ),
-- 2 lines below are duplicates from 2 above for falling edge
( H, L, L, L, x, x, L ),
( H, H, x, L, L, x, H ),
( H, x, L, x, L, x, S ),
( x, x, L, L, L, x, S ),
( x, x, H, x, L, x, H ),
( x, x, x, x, H, x, L ));
CONSTANT FDDCPE_Q_tab : VitalStateTableType := (
-- C_d PRE Qz D CE C_i CLR S Q
( L, L, L, L, x, H, x, x, L ),
( L, L, L, x, L, H, x, x, L ),
( L, L, x, L, H, H, x, x, L ),
-- Line below is dup of line above for falling edge
( H, L, x, L, H, L, x, x, L ),
( L, x, H, H, x, H, L, x, H ),
( L, x, H, x, L, H, L, x, H ),
( L, x, x, H, H, H, L, x, H ),
-- Line below is dup of line above for falling edge
( H, x, x, H, H, L, L, x, H ),
( H, L, x, x, x, x, L, x, S ),
( x, L, x, x, x, L, L, x, S ),
( x, H, x, x, x, x, L, x, H ),
( x, x, x, x, x, x, H, x, L ));
CONSTANT FDDP_Q_tab : VitalStateTableType := (
-- C_d D PRE C_i State Q
( L, L, L, H, x, L ),
( L, H, x, H, x, H ),
-- Duplicate 2 lines above for falling edge
( H, L, L, L, x, L ),
( H, H, x, L, x, H ),
( H, x, L, x, x, S ),
( x, x, L, L, x, S ),
( x, x, H, x, x, H ));
CONSTANT FDDPE_Q_tab : VitalStateTableType := (
-- C_d PRE Qz D CE C_i S Q
( L, L, L, L, x, H, x, L ),
( L, L, L, x, L, H, x, L ),
( L, L, x, L, H, H, x, L ),
-- Line below is duplicate from above for falling edge
( H, L, x, L, H, L, x, L ),
( L, x, H, H, x, H, x, H ),
( L, x, H, x, L, H, x, H ),
( L, x, x, H, H, H, x, H ),
-- Line below is duplicate from above for falling edge
( H, x, x, H, H, L, x, H ),
( H, L, x, x, x, x, x, S ),
( x, L, x, x, x, L, x, S ),
( x, H, x, x, x, x, x, H ));
---------------------------------------------------------------------------
-- Function HEX_TO_SLV16 converts a hexadecimal string to std_logic_vector
-- of size 15 downto 0.
---------------------------------------------------------------------------
function HEX_TO_SLV16 (
INIT : in string(4 downto 1)
) return std_logic_vector;
---------------------------------------------------------------------------
-- Function HEX_TO_SLV32 converts a hexadecimal string to std_logic_vector
-- of size 31 downto 0.
---------------------------------------------------------------------------
function HEX_TO_SLV32 (
INIT : in string(8 downto 1)
) return std_logic_vector;
---------------------------------------------------------------------------
-- Function DECODE_ADDR4 decodes a 4 bit address into an integer ranging
-- from 0 to 16.
---------------------------------------------------------------------------
function DECODE_ADDR4 (
ADDRESS : in std_logic_vector(3 downto 0)
) return integer;
---------------------------------------------------------------------------
-- Function DECODE_ADDR5 decodes a 5 bit address into an integer ranging
-- from 0 to 32.
---------------------------------------------------------------------------
function DECODE_ADDR5 (
ADDRESS : in std_logic_vector(4 downto 0)
) return integer;
---------------------------------------------------------------------------
-- Function SLV_TO_INT converts standard logic vector into an integer
---------------------------------------------------------------------------
function SLV_TO_INT (
SLV : in std_logic_vector
) return integer;
---------------------------------------------------------------------------
-- Function ADDR_IS_VALID checks for the validity of the argument. A FALSE
-- is returned if any argument bit is other than a '0' or '1'.
---------------------------------------------------------------------------
function ADDR_IS_VALID (
SLV : in std_logic_vector
) return boolean;
---------------------------------------------------------------------------
-- Function SLV_TO_STR returns a string version of the std_logic_vector
-- argument.
---------------------------------------------------------------------------
function SLV_TO_STR (
SLV : in std_logic_vector
) return string;
---------------------------------------------------------------------------
-- Function SLV_TO_HEX returns a string version of the std_logic_vector
-- argument.
---------------------------------------------------------------------------
function SLV_TO_HEX (
SLV : in std_logic_vector;
string_length : in integer
) return string;
---------------------------------------------------------------------------
-- Procedure SET_MEM_TO_X issues an "invalid address" warning and sets the
-- contents of the argument MEM to 'X'.
---------------------------------------------------------------------------
procedure SET_MEM_TO_X (
ADDRESS : in std_logic_vector;
MEM : inout std_logic_vector
);
---------------------------------------------------------------------------
-- Procedure ADDR_OVERLAP determines if there is overlap between the data
-- addressed by ports A and B of a dual port RAM. If there is overlap, the
-- argument OVERLAP is set to TRUE, and the lower and upper indices of the
-- overlap bits in the array used to model the RAM, as well as in the RAM
-- A and B output ports are determined.
---------------------------------------------------------------------------
procedure ADDR_OVERLAP (
ADDRESS_A, ADDRESS_B, DAW, DBW : in integer;
OVERLAP : out boolean;
OVRLAP_LSB, OVRLAP_MSB, DOA_OV_LSB,
DOA_OV_MSB, DOB_OV_LSB, DOB_OV_MSB : out integer
);
---------------------------------------------------------------------------
-- Procedure COLLISION issues either a "WRITE COLLISION detected" error or
-- a warning that an attempt was made to read some or all of the bits
-- addressed by one port of a dual port RAM while writing to some or all
-- of the bits from the other port. In case of write collision, some or all
-- of the bits addressed by the port at which the collision is detected are
-- set to 'X'.
---------------------------------------------------------------------------
procedure COLLISION (
ADDRESS : in std_logic_vector;
LSB, MSB : in integer;
MODE, PORT1, PORT2, InstancePath : in string;
MEM : inout std_logic_vector
);
PROCEDURE GenericValueCheckMessage (
CONSTANT HeaderMsg : IN STRING := " Attribute Syntax Error ";
CONSTANT GenericName : IN STRING := "";
CONSTANT EntityName : IN STRING := "";
CONSTANT InstanceName : IN STRING := "";
CONSTANT GenericValue : IN STRING := "";
Constant Unit : IN STRING := "";
Constant ExpectedValueMsg : IN STRING := "";
Constant ExpectedGenericValue : IN STRING := "";
CONSTANT TailMsg : IN STRING;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
);
PROCEDURE GenericValueCheckMessage (
CONSTANT HeaderMsg : IN STRING := " Attribute Syntax Error ";
CONSTANT GenericName : IN STRING := "";
CONSTANT EntityName : IN STRING := "";
CONSTANT InstanceName : IN STRING := "";
CONSTANT GenericValue : IN INTEGER;
Constant Unit : IN STRING := "";
Constant ExpectedValueMsg : IN STRING := "";
Constant ExpectedGenericValue : IN INTEGER;
CONSTANT TailMsg : IN STRING;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
);
PROCEDURE GenericValueCheckMessage (
CONSTANT HeaderMsg : IN STRING := " Attribute Syntax Error ";
CONSTANT GenericName : IN STRING := "";
CONSTANT EntityName : IN STRING := "";
CONSTANT InstanceName : IN STRING := "";
CONSTANT GenericValue : IN BOOLEAN;
Constant Unit : IN STRING := "";
Constant ExpectedValueMsg : IN STRING := "";
Constant ExpectedGenericValue : IN STRING := "";
CONSTANT TailMsg : IN STRING;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
);
PROCEDURE GenericValueCheckMessage (
CONSTANT HeaderMsg : IN STRING := " Attribute Syntax Error ";
CONSTANT GenericName : IN STRING := "";
CONSTANT EntityName : IN STRING := "";
CONSTANT InstanceName : IN STRING := "";
CONSTANT GenericValue : IN INTEGER;
CONSTANT Unit : IN STRING := "";
CONSTANT ExpectedValueMsg : IN STRING := "";
CONSTANT ExpectedGenericValue : IN STRING := "";
CONSTANT TailMsg : IN STRING;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
);
PROCEDURE GenericValueCheckMessage (
CONSTANT HeaderMsg : IN STRING := " Attribute Syntax Error ";
CONSTANT GenericName : IN STRING := "";
CONSTANT EntityName : IN STRING := "";
CONSTANT InstanceName : IN STRING := "";
CONSTANT GenericValue : IN REAL;
CONSTANT Unit : IN STRING := "";
CONSTANT ExpectedValueMsg : IN STRING := "";
CONSTANT ExpectedGenericValue : IN STRING := "";
CONSTANT TailMsg : IN STRING;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
);
PROCEDURE Memory_Collision_Msg (
CONSTANT HeaderMsg : IN STRING := " Memory Collision Error on ";
CONSTANT EntityName : IN STRING := "";
CONSTANT InstanceName : IN STRING := "";
constant collision_type : in memory_collision_type;
constant address_a : in std_logic_vector;
constant address_b : in std_logic_vector;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := ERROR
);
procedure detect_resolution (
constant model_name : in string
);
end VPKG;
-----------------------------------------------------------------------------
package body VPKG is
---------------------------------------------------------------------------
-- Function SLV_TO_INT converts a std_logic_vector TO INTEGER
---------------------------------------------------------------------------
function SLV_TO_INT(SLV: in std_logic_vector
) return integer is
variable int : integer;
begin
int := 0;
for i in SLV'high downto SLV'low loop
int := int * 2;
if SLV(i) = '1' then
int := int + 1;
end if;
end loop;
return int;
end;
---------------------------------------------------------------------------
-- Function HEX_TO_SLV16 converts a hexadecimal string to std_logic_vector
-- of size 15 downto 0.
---------------------------------------------------------------------------
function HEX_TO_SLV16 (
INIT : in string(4 downto 1)
) return std_logic_vector is
variable SLV_16 : std_logic_vector(15 downto 0);
begin
for I in 0 to 3 loop
case INIT(I+1) is
when '0' =>
SLV_16(I*4+3 downto I*4) := "0000";
when '1' =>
SLV_16(I*4+3 downto I*4) := "0001";
when '2' =>
SLV_16(I*4+3 downto I*4) := "0010";
when '3' =>
SLV_16(I*4+3 downto I*4) := "0011";
when '4' =>
SLV_16(I*4+3 downto I*4) := "0100";
when '5' =>
SLV_16(I*4+3 downto I*4) := "0101";
when '6' =>
SLV_16(I*4+3 downto I*4) := "0110";
when '7' =>
SLV_16(I*4+3 downto I*4) := "0111";
when '8' =>
SLV_16(I*4+3 downto I*4) := "1000";
when '9' =>
SLV_16(I*4+3 downto I*4) := "1001";
when 'a' | 'A' =>
SLV_16(I*4+3 downto I*4) := "1010";
when 'b' | 'B' =>
SLV_16(I*4+3 downto I*4) := "1011";
when 'c' | 'C' =>
SLV_16(I*4+3 downto I*4) := "1100";
when 'd' | 'D' =>
SLV_16(I*4+3 downto I*4) := "1101";
when 'e' | 'E' =>
SLV_16(I*4+3 downto I*4) := "1110";
when 'f' | 'F' =>
SLV_16(I*4+3 downto I*4) := "1111";
when others =>
assert false
report "WARNING: Unknown Hex digit in INIT: "&INIT(I+1)
severity warning;
SLV_16(I*4+3 downto I*4) := "XXXX";
end case;
end loop;
return SLV_16;
end HEX_TO_SLV16;
---------------------------------------------------------------------------
-- Function HEX_TO_SLV32 converts a hexadecimal string to std_logic_vector
-- of size 31 downto 0.
---------------------------------------------------------------------------
function HEX_TO_SLV32 (
INIT : in string(8 downto 1)
) return std_logic_vector is
variable SLV_32 : std_logic_vector(31 downto 0);
begin
for I in 0 to 7 loop
case INIT(I+1) is
when '0' =>
SLV_32(I*4+3 downto I*4) := "0000";
when '1' =>
SLV_32(I*4+3 downto I*4) := "0001";
when '2' =>
SLV_32(I*4+3 downto I*4) := "0010";
when '3' =>
SLV_32(I*4+3 downto I*4) := "0011";
when '4' =>
SLV_32(I*4+3 downto I*4) := "0100";
when '5' =>
SLV_32(I*4+3 downto I*4) := "0101";
when '6' =>
SLV_32(I*4+3 downto I*4) := "0110";
when '7' =>
SLV_32(I*4+3 downto I*4) := "0111";
when '8' =>
SLV_32(I*4+3 downto I*4) := "1000";
when '9' =>
SLV_32(I*4+3 downto I*4) := "1001";
when 'a' | 'A' =>
SLV_32(I*4+3 downto I*4) := "1010";
when 'b' | 'B' =>
SLV_32(I*4+3 downto I*4) := "1011";
when 'c' | 'C' =>
SLV_32(I*4+3 downto I*4) := "1100";
when 'd' | 'D' =>
SLV_32(I*4+3 downto I*4) := "1101";
when 'e' | 'E' =>
SLV_32(I*4+3 downto I*4) := "1110";
when 'f' | 'F' =>
SLV_32(I*4+3 downto I*4) := "1111";
when others =>
assert false
report "WARNING: Unknown Hex digit in INIT: "&INIT(I+1)
severity warning;
SLV_32(I*4+3 downto I*4) := "XXXX";
end case;
end loop;
return SLV_32;
end HEX_TO_SLV32;
---------------------------------------------------------------------------
-- Function DECODE_ADDR4 decodes a 4 bit address into an integer ranging
-- from 0 to 16.
---------------------------------------------------------------------------
function DECODE_ADDR4 (
ADDRESS : in std_logic_vector(3 downto 0)
) return integer is
variable I : integer;
begin
case ADDRESS is
when "0000" => I := 0;
when "0001" => I := 1;
when "0010" => I := 2;
when "0011" => I := 3;
when "0100" => I := 4;
when "0101" => I := 5;
when "0110" => I := 6;
when "0111" => I := 7;
when "1000" => I := 8;
when "1001" => I := 9;
when "1010" => I := 10;
when "1011" => I := 11;
when "1100" => I := 12;
when "1101" => I := 13;
when "1110" => I := 14;
when "1111" => I := 15;
when others => I := 16;
end case;
return I;
end DECODE_ADDR4;
---------------------------------------------------------------------------
-- Function DECODE_ADDR5 decodes a 5 bit address into an integer ranging
-- from 0 to 32.
---------------------------------------------------------------------------
function DECODE_ADDR5 (
ADDRESS : in std_logic_vector(4 downto 0)
) return integer is
variable I : integer;
begin
case ADDRESS is
when "00000" => I := 0;
when "00001" => I := 1;
when "00010" => I := 2;
when "00011" => I := 3;
when "00100" => I := 4;
when "00101" => I := 5;
when "00110" => I := 6;
when "00111" => I := 7;
when "01000" => I := 8;
when "01001" => I := 9;
when "01010" => I := 10;
when "01011" => I := 11;
when "01100" => I := 12;
when "01101" => I := 13;
when "01110" => I := 14;
when "01111" => I := 15;
when "10000" => I := 16;
when "10001" => I := 17;
when "10010" => I := 18;
when "10011" => I := 19;
when "10100" => I := 20;
when "10101" => I := 21;
when "10110" => I := 22;
when "10111" => I := 23;
when "11000" => I := 24;
when "11001" => I := 25;
when "11010" => I := 26;
when "11011" => I := 27;
when "11100" => I := 28;
when "11101" => I := 29;
when "11110" => I := 30;
when "11111" => I := 31;
when others => I := 32;
end case;
return I;
end DECODE_ADDR5;
---------------------------------------------------------------------------
-- Function ADDR_IS_VALID checks for the validity of the argument. A FALSE
-- is returned if any argument bit is other than a '0' or '1'.
---------------------------------------------------------------------------
function ADDR_IS_VALID (
SLV : in std_logic_vector
) return boolean is
variable IS_VALID : boolean := TRUE;
begin
for I in SLV'high downto SLV'low loop
if (SLV(I) /= '0' AND SLV(I) /= '1') then
IS_VALID := FALSE;
end if;
end loop;
return IS_VALID;
end ADDR_IS_VALID;
---------------------------------------------------------------------------
-- Function SLV_TO_STR returns a string version of the std_logic_vector
-- argument.
---------------------------------------------------------------------------
function SLV_TO_STR (
SLV : in std_logic_vector
) return string is
variable j : integer := SLV'length;
variable STR : string (SLV'length downto 1);
begin
for I in SLV'high downto SLV'low loop
case SLV(I) is
when '0' => STR(J) := '0';
when '1' => STR(J) := '1';
when 'X' => STR(J) := 'X';
when 'U' => STR(J) := 'U';
when others => STR(J) := 'X';
end case;
J := J - 1;
end loop;
return STR;
end SLV_TO_STR;
---------------------------------------------------------------------------
-- Function SLV_TO_HEX returns a hex string version of the std_logic_vector
-- argument.
---------------------------------------------------------------------------
function SLV_TO_HEX (
SLV : in std_logic_vector;
string_length : in integer
) return string is
variable i : integer := 1;
variable j : integer := 1;
variable STR : string(string_length downto 1);
variable nibble : std_logic_vector(3 downto 0) := "0000";
variable full_nibble_count : integer := 0;
variable remaining_bits : integer := 0;
begin
full_nibble_count := SLV'length/4;
remaining_bits := SLV'length mod 4;
for i in 1 to full_nibble_count loop
nibble := SLV(((4*i) - 1) downto ((4*i) - 4));
if (nibble = "0000") then
STR(j) := '0';
elsif (nibble = "0001") then
STR(j) := '1';
elsif (nibble = "0010") then
STR(j) := '2';
elsif (nibble = "0011") then
STR(j) := '3';
elsif (nibble = "0100") then
STR(j) := '4';
elsif (nibble = "0101") then
STR(j) := '5';
elsif (nibble = "0110") then
STR(j) := '6';
elsif (nibble = "0111") then
STR(j) := '7';
elsif (nibble = "1000") then
STR(j) := '8';
elsif (nibble = "1001") then
STR(j) := '9';
elsif (nibble = "1010") then
STR(j) := 'a';
elsif (nibble = "1011") then
STR(j) := 'b';
elsif (nibble = "1100") then
STR(j) := 'c';
elsif (nibble = "1101") then
STR(j) := 'd';
elsif (nibble = "1110") then
STR(j) := 'e';
elsif (nibble = "1111") then
STR(j) := 'f';
end if;
j := j + 1;
end loop;
if (remaining_bits /= 0) then
nibble := "0000";
nibble((remaining_bits -1) downto 0) := SLV((SLV'length -1) downto (SLV'length - remaining_bits));
if (nibble = "0000") then
STR(j) := '0';
elsif (nibble = "0001") then
STR(j) := '1';
elsif (nibble = "0010") then
STR(j) := '2';
elsif (nibble = "0011") then
STR(j) := '3';
elsif (nibble = "0100") then
STR(j) := '4';
elsif (nibble = "0101") then
STR(j) := '5';
elsif (nibble = "0110") then
STR(j) := '6';
elsif (nibble = "0111") then
STR(j) := '7';
elsif (nibble = "1000") then
STR(j) := '8';
elsif (nibble = "1001") then
STR(j) := '9';
elsif (nibble = "1010") then
STR(j) := 'a';
elsif (nibble = "1011") then
STR(j) := 'b';
elsif (nibble = "1100") then
STR(j) := 'c';
elsif (nibble = "1101") then
STR(j) := 'd';
elsif (nibble = "1110") then
STR(j) := 'e';
elsif (nibble = "1111") then
STR(j) := 'f';
end if;
end if;
return STR;
end SLV_TO_HEX;
---------------------------------------------------------------------------
-- Procedure SET_MEM_TO_X issues an "invalid address" warning and sets the
-- contents of the argument MEM to 'X'.
---------------------------------------------------------------------------
procedure SET_MEM_TO_X (ADDRESS : in std_logic_vector;
MEM : inout std_logic_vector
) is
begin
assert false report
"Invalid ADDRESS: "& SLV_TO_STR(ADDRESS) & ". Memory contents will be set to 'X'."
severity warning;
for I in MEM'high downto MEM'low loop
MEM(I) := 'X';
end loop;
end SET_MEM_TO_X;
---------------------------------------------------------------------------
-- Procedure ADDR_OVERLAP determines if there is overlap between the data
-- addressed by ports A and B of a dual port RAM. If there is overlap, the
-- argument OVERLAP is set to TRUE, and the lower and upper indices of the
-- overlap bits in the array used to model the RAM, as well as in the RAM
-- A and B output ports are determined.
---------------------------------------------------------------------------
procedure ADDR_OVERLAP (
ADDRESS_A, ADDRESS_B, DAW, DBW : in integer;
OVERLAP : out boolean;
OVRLAP_LSB, OVRLAP_MSB, DOA_OV_LSB,
DOA_OV_MSB, DOB_OV_LSB, DOB_OV_MSB : out integer
) is
variable A_LSB, A_MSB, B_LSB, B_MSB : integer;
begin
A_LSB := ADDRESS_A * DAW;
A_MSB := A_LSB + DAW - 1;
B_LSB := ADDRESS_B * DBW;
B_MSB := B_LSB + DBW - 1;
if (A_MSB < B_LSB OR B_MSB < A_LSB) then
OVERLAP := FALSE;
else
OVERLAP := TRUE;
if (A_LSB >= B_LSB) then
OVRLAP_LSB := A_LSB;
DOA_OV_LSB := 0;
DOB_OV_LSB := A_LSB - B_LSB;
else
OVRLAP_LSB := B_LSB;
DOA_OV_LSB := B_LSB - A_LSB;
DOB_OV_LSB := 0;
end if;
if (A_MSB >= B_MSB) then
OVRLAP_MSB := B_MSB;
DOA_OV_MSB := DAW - (A_MSB - B_MSB) - 1;
DOB_OV_MSB := DBW - 1;
else
OVRLAP_MSB := A_MSB;
DOA_OV_MSB := DAW - 1;
DOB_OV_MSB := DBW - (B_MSB - A_MSB) - 1;
end if;
end if;
end ADDR_OVERLAP;
---------------------------------------------------------------------------
-- Procedure COLLISION issues either a "WRITE COLLISION detected" error or
-- a warning that an attempt was made to read some or all of the bits
-- addressed by one port of a dual port RAM while writing to some or all
-- of the bits from the other port. In case of write collision, some or all
-- of the bits addressed by the port at which the collision is detected are
-- set to 'X'.
---------------------------------------------------------------------------
procedure COLLISION (
ADDRESS : in std_logic_vector;
LSB, MSB : in integer;
MODE, PORT1, PORT2, InstancePath : in string;
MEM : inout std_logic_vector
) is
begin
if (MODE = "write") then
assert false report
"WRITE COLLISION detected at " & PORT1 & " in instance " & InstancePath &
". Contents of address "& SLV_TO_STR(ADDRESS) &
" will be wholly or partially set to 'X'."
severity WARNING;
for I in MSB downto LSB loop
MEM(I) := 'X';
end loop;
elsif (MODE = "read") then
assert false report
"Attempting to read some or all of contents of address "& SLV_TO_STR(ADDRESS) &
" from " & PORT2 & " while writing from " & PORT1 &
" in instance " & InstancePath
severity WARNING;
end if;
end COLLISION;
PROCEDURE GenericValueCheckMessage (
CONSTANT HeaderMsg : IN STRING := " Attribute Syntax Error ";
CONSTANT GenericName : IN STRING := "";
CONSTANT EntityName : IN STRING := "";
CONSTANT InstanceName : IN STRING := "";
CONSTANT GenericValue : IN STRING := "";
Constant Unit : IN STRING := "";
Constant ExpectedValueMsg : IN STRING := "";
Constant ExpectedGenericValue : IN STRING := "";
CONSTANT TailMsg : IN STRING;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
) IS
VARIABLE Message : LINE;
BEGIN
Write ( Message, HeaderMsg );
Write ( Message, STRING'(" The attribute ") );
Write ( Message, GenericName );
Write ( Message, STRING'(" on ") );
Write ( Message, EntityName );
Write ( Message, STRING'(" instance ") );
Write ( Message, InstanceName );
Write ( Message, STRING'(" is set to ") );
Write ( Message, GenericValue );
Write ( Message, Unit );
Write ( Message, '.' & LF );
Write ( Message, ExpectedValueMsg );
Write ( Message, ExpectedGenericValue );
Write ( Message, Unit );
Write ( Message, TailMsg );
ASSERT FALSE REPORT Message.ALL SEVERITY MsgSeverity;
DEALLOCATE (Message);
END GenericValueCheckMessage;
PROCEDURE GenericValueCheckMessage (
CONSTANT HeaderMsg : IN STRING := " Attribute Syntax Error ";
CONSTANT GenericName : IN STRING := "";
CONSTANT EntityName : IN STRING := "";
CONSTANT InstanceName : IN STRING := "";
CONSTANT GenericValue : IN INTEGER;
CONSTANT Unit : IN STRING := "";
CONSTANT ExpectedValueMsg : IN STRING := "";
CONSTANT ExpectedGenericValue : IN INTEGER;
CONSTANT TailMsg : IN STRING;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
) IS
VARIABLE Message : LINE;
BEGIN
Write ( Message, HeaderMsg );
Write ( Message, STRING'(" The attribute ") );
Write ( Message, GenericName );
Write ( Message, STRING'(" on ") );
Write ( Message, EntityName );
Write ( Message, STRING'(" instance ") );
Write ( Message, InstanceName );
Write ( Message, STRING'(" is set to ") );
Write ( Message, GenericValue );
Write ( Message, Unit );
Write ( Message, '.' & LF );
Write ( Message, ExpectedValueMsg );
Write ( Message, ExpectedGenericValue );
Write ( Message, Unit );
Write ( Message, TailMsg );
ASSERT FALSE REPORT Message.ALL SEVERITY MsgSeverity;
DEALLOCATE (Message);
END GenericValueCheckMessage;
PROCEDURE GenericValueCheckMessage (
CONSTANT HeaderMsg : IN STRING := " Attribute Syntax Error ";
CONSTANT GenericName : IN STRING := "";
CONSTANT EntityName : IN STRING := "";
CONSTANT InstanceName : IN STRING := "";
CONSTANT GenericValue : IN BOOLEAN;
Constant Unit : IN STRING := "";
CONSTANT ExpectedValueMsg : IN STRING := "";
CONSTANT ExpectedGenericValue : IN STRING := "";
CONSTANT TailMsg : IN STRING;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
) IS
VARIABLE Message : LINE;
BEGIN
Write ( Message, HeaderMsg );
Write ( Message, STRING'(" The attribute ") );
Write ( Message, GenericName );
Write ( Message, STRING'(" on ") );
Write ( Message, EntityName );
Write ( Message, STRING'(" instance ") );
Write ( Message, InstanceName );
Write ( Message, STRING'(" is set to ") );
Write ( Message, GenericValue );
Write ( Message, Unit );
Write ( Message, '.' & LF );
Write ( Message, ExpectedValueMsg );
Write ( Message, ExpectedGenericValue );
Write ( Message, Unit );
Write ( Message, TailMsg );
ASSERT FALSE REPORT Message.ALL SEVERITY MsgSeverity;
DEALLOCATE (Message);
END GenericValueCheckMessage;
PROCEDURE GenericValueCheckMessage (
CONSTANT HeaderMsg : IN STRING := " Attribute Syntax Error ";
CONSTANT GenericName : IN STRING := "";
CONSTANT EntityName : IN STRING := "";
CONSTANT InstanceName : IN STRING := "";
CONSTANT GenericValue : IN INTEGER;
CONSTANT Unit : IN STRING := "";
CONSTANT ExpectedValueMsg : IN STRING := "";
CONSTANT ExpectedGenericValue : IN STRING := "";
CONSTANT TailMsg : IN STRING;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
) IS
VARIABLE Message : LINE;
BEGIN
Write ( Message, HeaderMsg );
Write ( Message, STRING'(" The attribute ") );
Write ( Message, GenericName );
Write ( Message, STRING'(" on ") );
Write ( Message, EntityName );
Write ( Message, STRING'(" instance ") );
Write ( Message, InstanceName );
Write ( Message, STRING'(" is set to ") );
Write ( Message, GenericValue );
Write ( Message, Unit );
Write ( Message, '.' & LF );
Write ( Message, ExpectedValueMsg );
Write ( Message, ExpectedGenericValue );
Write ( Message, Unit );
Write ( Message, TailMsg );
ASSERT FALSE REPORT Message.ALL SEVERITY MsgSeverity;
DEALLOCATE (Message);
END GenericValueCheckMessage;
PROCEDURE GenericValueCheckMessage (
CONSTANT HeaderMsg : IN STRING := " Attribute Syntax Error ";
CONSTANT GenericName : IN STRING := "";
CONSTANT EntityName : IN STRING := "";
CONSTANT InstanceName : IN STRING := "";
CONSTANT GenericValue : IN REAL;
CONSTANT Unit : IN STRING := "";
CONSTANT ExpectedValueMsg : IN STRING := "";
CONSTANT ExpectedGenericValue : IN STRING := "";
CONSTANT TailMsg : IN STRING;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
) IS
VARIABLE Message : LINE;
BEGIN
Write ( Message, HeaderMsg );
Write ( Message, STRING'(" The attribute ") );
Write ( Message, GenericName );
Write ( Message, STRING'(" on ") );
Write ( Message, EntityName );
Write ( Message, STRING'(" instance ") );
Write ( Message, InstanceName );
Write ( Message, STRING'(" is set to ") );
Write ( Message, GenericValue );
Write ( Message, Unit );
Write ( Message, '.' & LF );
Write ( Message, ExpectedValueMsg );
Write ( Message, ExpectedGenericValue );
Write ( Message, Unit );
Write ( Message, TailMsg );
ASSERT FALSE REPORT Message.ALL SEVERITY MsgSeverity;
DEALLOCATE (Message);
END GenericValueCheckMessage;
--
PROCEDURE Memory_Collision_Msg (
CONSTANT HeaderMsg : IN STRING := " Memory Collision Error on ";
CONSTANT EntityName : IN STRING := "";
CONSTANT InstanceName : IN STRING := "";
constant collision_type : in memory_collision_type;
constant address_a : in std_logic_vector;
constant address_b : in std_logic_vector;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := ERROR
) IS
variable current_time : time := NOW;
variable string_length_a : integer;
variable string_length_b : integer;
VARIABLE Message : LINE;
BEGIN
if ((address_a'length mod 4) = 0) then
string_length_a := address_a'length/4;
elsif ((address_a'length mod 4) > 0) then
string_length_a := address_a'length/4 + 1;
end if;
if ((address_b'length mod 4) = 0) then
string_length_b := address_b'length/4;
elsif ((address_b'length mod 4) > 0) then
string_length_b := address_b'length/4 + 1;
end if;
if (collision_type = Read_A_Write_B) then
Write ( Message, HeaderMsg);
Write ( Message, EntityName);
Write ( Message, STRING'(": "));
Write ( Message, InstanceName);
Write ( Message, STRING'(" at simulation time "));
Write ( Message, current_time);
Write ( Message, STRING'("."));
Write ( Message, LF );
Write ( Message, STRING'(" A read was performed on address "));
Write ( Message, SLV_TO_HEX(address_a, string_length_a));
Write ( Message, STRING'(" (hex) "));
Write ( Message, STRING'("of port A while a write was requested to the same address on Port B "));
Write ( Message, STRING'(" The write will be successful however the read value is unknown until the next CLKA cycle "));
elsif (collision_type = Read_B_Write_A) then
Write ( Message, HeaderMsg);
Write ( Message, EntityName);
Write ( Message, STRING'(": "));
Write ( Message, InstanceName);
Write ( Message, STRING'(" at simulation time "));
Write ( Message, current_time);
Write ( Message, STRING'("."));
Write ( Message, LF );
Write ( Message, STRING'(" A read was performed on address "));
Write ( Message, SLV_TO_HEX(address_b, string_length_b));
Write ( Message, STRING'(" (hex) "));
Write ( Message, STRING'("of port B while a write was requested to the same address on Port A "));
Write ( Message, STRING'(" The write will be successful however the read value is unknown until the next CLKB cycle "));
elsif (collision_type = Write_A_Write_B) then
Write ( Message, HeaderMsg);
Write ( Message, EntityName);
Write ( Message, STRING'(": "));
Write ( Message, InstanceName);
Write ( Message, STRING'(" at simulation time "));
Write ( Message, current_time);
Write ( Message, STRING'("."));
Write ( Message, LF );
Write ( Message, STRING'(" A write was requested to the same address simultaneously at both Port A and Port B of the RAM."));
Write ( Message, STRING'(" The contents written to the RAM at address location "));
Write ( Message, SLV_TO_HEX(address_a, string_length_a));
Write ( Message, STRING'(" (hex) "));
Write ( Message, STRING'("of Port A and address location "));
Write ( Message, SLV_TO_HEX(address_b, string_length_b));
Write ( Message, STRING'(" (hex) "));
Write ( Message, STRING'("of Port B are unknown. "));
end if;
ASSERT FALSE REPORT Message.ALL SEVERITY MsgSeverity;
DEALLOCATE (Message);
END Memory_Collision_Msg;
procedure detect_resolution (
constant model_name : in string
) IS
variable test_value : time;
variable Message : LINE;
BEGIN
test_value := 1 ps;
if (test_value = 0 ps) then
Write (Message, STRING'(" Simulator Resolution Error : "));
Write (Message, STRING'(" Simulator resolution is set to a value greater than 1 ps. "));
Write (Message, STRING'(" In order to simulate the "));
Write (Message, model_name);
Write (Message, STRING'(", the simulator resolution must be set to 1ps or smaller "));
ASSERT FALSE REPORT Message.ALL SEVERITY ERROR;
DEALLOCATE (Message);
end if;
END detect_resolution;
end VPKG;
| gpl-3.0 | 054fe7e1ebaaeb2597859d6df6ddb425 | 0.449345 | 3.080352 | false | false | false | false |
markusC64/1541ultimate2 | fpga/6502/vhdl_source/proc_registers.vhd | 1 | 10,056 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library work;
use work.pkg_6502_defs.all;
use work.pkg_6502_decode.all;
entity proc_registers is
generic (
vector_page : std_logic_vector(15 downto 4) := X"FFF" );
port (
clock : in std_logic;
clock_en : in std_logic;
reset : in std_logic;
-- package pins
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
so_n : in std_logic := '1';
-- data from "data_oper"
alu_data : in std_logic_vector(7 downto 0);
mem_data : in std_logic_vector(7 downto 0);
new_flags : in std_logic_vector(7 downto 0);
-- from implied handler
set_a : in std_logic;
set_x : in std_logic;
set_y : in std_logic;
set_s : in std_logic;
set_data : in std_logic_vector(7 downto 0);
-- interrupt pins
set_i_flag : in std_logic;
vect_addr : in std_logic_vector(3 downto 0);
-- from processor state machine and decoder
sync : in std_logic; -- latch ireg
latch_dreg : in std_logic;
vectoring : in std_logic;
reg_update : in std_logic;
copy_d2p : in std_logic;
a_mux : in t_amux;
dout_mux : in t_dout_mux;
pc_oper : in t_pc_oper;
s_oper : in t_sp_oper;
adl_oper : in t_adl_oper;
adh_oper : in t_adh_oper;
-- outputs to processor state machine
i_reg : out std_logic_vector(7 downto 0) := X"00";
index_carry : out std_logic;
pc_carry : out std_logic;
branch_taken : out boolean;
-- register outputs
addr_out : out std_logic_vector(15 downto 0) := X"FFFF";
d_reg : out std_logic_vector(7 downto 0) := X"00";
a_reg : out std_logic_vector(7 downto 0) := X"00";
x_reg : out std_logic_vector(7 downto 0) := X"00";
y_reg : out std_logic_vector(7 downto 0) := X"00";
s_reg : out std_logic_vector(7 downto 0) := X"00";
p_reg : out std_logic_vector(7 downto 0) := X"00";
pc_out : out std_logic_vector(15 downto 0) );
end proc_registers;
architecture gideon of proc_registers is
-- signal a_reg : std_logic_vector(7 downto 0);
signal dreg : std_logic_vector(7 downto 0) := X"00";
signal a_reg_i : std_logic_vector(7 downto 0) := X"00";
signal x_reg_i : std_logic_vector(7 downto 0) := X"00";
signal y_reg_i : std_logic_vector(7 downto 0) := X"00";
signal selected_idx : std_logic_vector(7 downto 0) := X"00";
signal i_reg_i : std_logic_vector(7 downto 0) := X"00";
signal s_reg_i : std_logic_vector(7 downto 0) := X"00";
signal p_reg_i : std_logic_vector(7 downto 0) := X"30";
signal pcl, pch : std_logic_vector(7 downto 0) := X"FF";
signal adl, adh : std_logic_vector(7 downto 0) := X"00";
signal pc_carry_i : std_logic;
signal pc_carry_d : std_logic;
signal branch_flag : std_logic;
signal reg_out : std_logic_vector(7 downto 0);
signal dreg_zero : std_logic;
signal so_d : std_logic;
alias C_flag : std_logic is p_reg_i(0);
alias Z_flag : std_logic is p_reg_i(1);
alias I_flag : std_logic is p_reg_i(2);
alias D_flag : std_logic is p_reg_i(3);
alias B_flag : std_logic is p_reg_i(4);
alias V_flag : std_logic is p_reg_i(6);
alias N_flag : std_logic is p_reg_i(7);
signal p_reg_push : std_logic_vector(7 downto 0);
begin
dreg_zero <= '1' when dreg=X"00" else '0';
p_reg_push <= p_reg_i(7 downto 6) & '1' & not vectoring & p_reg_i(3 downto 0);
process(clock)
variable pcl_t : std_logic_vector(8 downto 0);
variable adl_t : std_logic_vector(8 downto 0);
begin
if rising_edge(clock) then
if clock_en='1' then
-- Data Register
if latch_dreg='1' then
dreg <= data_in;
end if;
-- Flags Register
if copy_d2p = '1' then
p_reg_i <= dreg;
elsif reg_update='1' then
p_reg_i <= new_flags;
end if;
if set_i_flag='1' then
I_flag <= '1';
end if;
so_d <= so_n;
if so_n='0' and so_d = '1' then -- assumed that so_n is synchronous
V_flag <= '1';
end if;
-- Instruction Register
if sync='1' then
i_reg_i <= data_in;
-- Fix for PLA only :(
if load_a(i_reg_i) then
a_reg_i <= dreg;
N_flag <= dreg(7);
Z_flag <= dreg_zero;
end if;
end if;
-- Logic for the Program Counter
pc_carry_i <= '0';
case pc_oper is
when increment =>
if pcl = X"FF" then
pch <= pch + 1;
end if;
pcl <= pcl + 1;
when copy =>
pcl <= dreg;
pch <= data_in;
when from_alu =>
pcl_t := ('0' & pcl) + (dreg(7) & dreg); -- sign extended 1 bit
pcl <= pcl_t(7 downto 0);
pc_carry_i <= pcl_t(8);
pc_carry_d <= dreg(7);
when others => -- keep (and fix)
if pc_carry_i='1' then
if pc_carry_d='1' then
pch <= pch - 1;
else
pch <= pch + 1;
end if;
end if;
end case;
-- Logic for the Address register
case adl_oper is
when increment =>
adl <= adl + 1;
when add_idx =>
adl_t := ('0' & dreg) + ('0' & selected_idx);
adl <= adl_t(7 downto 0);
index_carry <= adl_t(8);
when load_bus =>
adl <= data_in;
when copy_dreg =>
adl <= dreg;
when others =>
null;
end case;
case adh_oper is
when increment =>
adh <= adh + 1;
when clear =>
adh <= (others => '0');
when load_bus =>
adh <= data_in;
when others =>
null;
end case;
-- Logic for ALU register
if reg_update='1' then
if set_a='1' then
a_reg_i <= set_data;
elsif store_a_from_alu(i_reg_i) then
a_reg_i <= alu_data;
end if;
end if;
-- Logic for Index registers
if reg_update='1' then
if set_x='1' then
x_reg_i <= set_data;
elsif load_x(i_reg_i) then
x_reg_i <= alu_data; --dreg; -- alu is okay, too (they should be the same)
end if;
end if;
if reg_update='1' then
if set_y='1' then
y_reg_i <= set_data;
elsif load_y(i_reg_i) then
y_reg_i <= dreg;
end if;
end if;
-- Logic for the Stack Pointer
if set_s='1' then
s_reg_i <= set_data;
else
case s_oper is
when increment =>
s_reg_i <= s_reg_i + 1;
when decrement =>
s_reg_i <= s_reg_i - 1;
when others =>
null;
end case;
end if;
end if;
-- Reset
if reset='1' then
p_reg_i <= X"34"; -- I=1
index_carry <= '0';
end if;
end if;
end process;
with i_reg_i(7 downto 6) select branch_flag <=
N_flag when "00",
V_flag when "01",
C_flag when "10",
Z_flag when "11",
'0' when others;
branch_taken <= (branch_flag xor not i_reg_i(5))='1';
with a_mux select addr_out <=
vector_page & vect_addr when 0,
adh & adl when 1,
X"01" & s_reg_i when 2,
pch & pcl when 3;
with i_reg_i(1 downto 0) select reg_out <=
y_reg_i when "00",
a_reg_i when "01",
x_reg_i when "10",
a_reg_i and x_reg_i when others;
with dout_mux select data_out <=
dreg when reg_d,
a_reg_i when reg_accu,
reg_out when reg_axy,
p_reg_push when reg_flags,
pcl when reg_pcl,
pch when reg_pch,
mem_data when shift_res,
X"FF" when others;
selected_idx <= y_reg_i when select_index_y(i_reg_i) else x_reg_i;
pc_carry <= pc_carry_i;
s_reg <= s_reg_i;
p_reg <= p_reg_i;
i_reg <= i_reg_i;
a_reg <= a_reg_i;
x_reg <= x_reg_i;
y_reg <= y_reg_i;
d_reg <= dreg;
pc_out <= pch & pcl;
end gideon;
| gpl-3.0 | 60fb2d15246a59b1492cf30b8a8c79da | 0.418755 | 3.587585 | false | false | false | false |
chiggs/nvc | test/regress/elab20.vhd | 5 | 854 | entity sub is
generic (
WIDTH : integer;
INIT : bit );
port (
x : out bit_vector(31 downto 0);
y : in bit_vector(WIDTH - 1 downto 0) );
end entity;
architecture test of sub is
signal y1 : bit_vector(WIDTH - 1 downto 0);
begin
x <= (31 downto WIDTH => '0') & y1;
y1 <= y;
end architecture;
-------------------------------------------------------------------------------
entity elab20 is
end entity;
architecture test of elab20 is
signal x : bit_vector(31 downto 0);
signal y : bit_vector(7 downto 0);
begin
process is
begin
y <= X"55";
wait for 1 ns;
assert x = X"00000055";
wait;
end process;
sub_i: entity work.sub
generic map (
WIDTH => 8,
INIT => '0' )
port map ( x, y );
end architecture;
| gpl-3.0 | aee1adc7bb343fa389135363ddb39121 | 0.483607 | 3.829596 | false | false | false | false |
markusC64/1541ultimate2 | fpga/cpu_unit/mblite/hw/core/core_wb_adapter.vhd | 2 | 3,027 | ----------------------------------------------------------------------------------------------
--
-- Input file : core_wb_adapter.vhd
-- Design name : core_wb_adapter.vhd
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Faculty EEMCS, Department ME&CE
-- : Systems and Circuits group
--
-- Description : Wishbone adapter for the MB-Lite microprocessor. The data output
-- is registered for multicycle transfers. This adapter implements
-- the synchronous Wishbone Bus protocol, Rev3B.
--
----------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library mblite;
use mblite.config_Pkg.all;
use mblite.core_Pkg.all;
use mblite.std_Pkg.all;
entity core_wb_adapter is port
(
dmem_i : out dmem_in_type;
wb_o : out wb_mst_out_type;
dmem_o : in dmem_out_type;
wb_i : in wb_mst_in_type
);
end core_wb_adapter;
architecture arch of core_wb_adapter is
signal r_cyc_o : std_logic;
signal rin_cyc_o : std_logic;
signal r_data, rin_data : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
signal s_wait : std_logic;
begin
-- Direct input-output connections
wb_o.adr_o <= dmem_o.adr_o;
wb_o.sel_o <= dmem_o.sel_o;
wb_o.we_o <= dmem_o.we_o;
dmem_i.dat_i <= wb_i.dat_i;
-- synchronous bus control connections
wb_o.cyc_o <= r_cyc_o or wb_i.ack_i;
wb_o.stb_o <= r_cyc_o;
-- asynchronous core enable connection
dmem_i.ena_i <= '0' when (dmem_o.ena_o = '1' and rin_cyc_o = '1') or s_wait = '1' else '1';
wb_o.dat_o <= rin_data;
-- logic for wishbone master
wb_adapter_comb: process(wb_i, dmem_o, r_cyc_o, r_data)
begin
if wb_i.rst_i = '1' then
-- reset bus
rin_data <= r_data;
rin_cyc_o <= '0';
s_wait <= '0';
elsif r_cyc_o = '1' and wb_i.ack_i = '1' then
-- terminate wishbone cycle
rin_data <= r_data;
rin_cyc_o <= '0';
s_wait <= '0';
elsif dmem_o.ena_o = '1' and wb_i.ack_i = '1' then
-- wishbone bus is occuppied
rin_data <= r_data;
rin_cyc_o <= '1';
s_wait <= '1';
elsif r_cyc_o = '0' and dmem_o.ena_o = '1' and wb_i.ack_i = '0' then
-- start wishbone cycle
rin_data <= dmem_o.dat_o;
rin_cyc_o <= '1';
s_wait <= '0';
else
-- maintain wishbone cycle
rin_data <= r_data;
rin_cyc_o <= r_cyc_o;
s_wait <= '0';
end if;
end process;
wb_adapter_seq: process(wb_i.clk_i)
begin
if rising_edge(wb_i.clk_i) then
r_cyc_o <= rin_cyc_o;
r_data <= rin_data;
end if;
end process;
end arch;
| gpl-3.0 | 0fd1e70e9666e081ca71438047cd0b30 | 0.486951 | 3.352159 | false | false | false | false |
xiadz/oscilloscope | src/reader.vhd | 1 | 5,653 | ----------------------------------------------------------------------------------
-- Author: Osowski Marcin
-- Create Date: 14:48:55 05/24/2011
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity reader is
port (
nrst : in std_logic;
clk108 : in std_logic;
input_red : in std_logic;
input_green : in std_logic;
input_blue : in std_logic;
is_reading_active : in std_logic;
time_resolution : in integer range 0 to 15;
-- This is an asynchronous output. It indicates that during next
-- clock cycle entity will generate flush_and_return_to_zero.
overflow_indicator : out std_logic;
screen_segment : out natural range 0 to 13;
screen_column : out natural range 0 to 1279;
flush_and_return_to_zero : out std_logic;
write_enable : out std_logic;
red_value : out std_logic;
green_value : out std_logic;
blue_value : out std_logic
);
constant max_time_resolution : natural := 432000;
type res_array is array (0 to 15) of natural range 2 to max_time_resolution;
-- Real time resolution will be given by equation:
-- time_between_probes = time_resolutions (time_resolution) / (108 Mhz)
-- No 1 (ones) here please!
constant time_resolutions : res_array := (
2, 5, 10, 20, 108, 216, 432, 1080, 2160, 4320,
10800, 21600, 43200, 108000, 216000, 432000
);
end reader;
architecture behavioral of reader is
signal time_position : natural range 0 to max_time_resolution + 1 := 0;
signal next_time_position : natural range 0 to max_time_resolution + 1;
signal time_overflow : std_logic;
signal memory_position : natural range 0 to (14 * 1280) := 0;
signal next_memory_position : natural range 0 to (14 * 1280);
signal internal_screen_segment : natural range 0 to 13:= 0;
signal internal_screen_column : natural range 0 to 1279 := 0;
signal next_screen_segment : natural range 0 to 14;
signal next_screen_column : natural range 0 to 1280;
signal internal_overflow_indicator : std_logic;
begin
overflow_indicator <= internal_overflow_indicator;
screen_segment <= internal_screen_segment;
screen_column <= internal_screen_column;
-- Process computes next_time_position and time_overflow
process (time_position) is
begin
if time_position + 1 >= time_resolutions (time_resolution) then
next_time_position <= 0;
time_overflow <= '1';
else
next_time_position <= time_position + 1;
time_overflow <= '0';
end if;
end process;
-- Process computes next_memory_position and internal_overflow_indicator
process (memory_position, internal_screen_segment, internal_screen_column, time_overflow) is
begin
if time_overflow = '1' then
if memory_position + 1 >= (14 * 1280) then
next_memory_position <= 0;
next_screen_segment <= 0;
next_screen_column <= 0;
internal_overflow_indicator <= '1';
else
next_memory_position <= memory_position + 1;
if internal_screen_column + 1 >= 1280 then
next_screen_column <= 0;
next_screen_segment <= internal_screen_segment + 1;
else
next_screen_column <= internal_screen_column + 1;
next_screen_segment <= internal_screen_segment;
end if;
internal_overflow_indicator <= '0';
end if;
else
next_memory_position <= memory_position;
next_screen_column <= internal_screen_column;
next_screen_segment <= internal_screen_segment;
internal_overflow_indicator <= '0';
end if;
end process;
process (nrst, clk108) is
begin
if nrst = '0' then
time_position <= 0;
memory_position <= 0;
flush_and_return_to_zero <= '0';
write_enable <= '0';
red_value <= '0';
green_value <= '0';
blue_value <= '0';
elsif rising_edge (clk108) then
memory_position <= next_memory_position;
internal_screen_column <= next_screen_column;
internal_screen_segment <= next_screen_segment;
if is_reading_active = '1' or time_position /= 0 then
time_position <= next_time_position;
if time_overflow = '1' then
red_value <= input_red;
green_value <= input_green;
blue_value <= input_blue;
write_enable <= '1';
flush_and_return_to_zero <= internal_overflow_indicator;
else
red_value <= '0';
green_value <= '0';
blue_value <= '0';
write_enable <= '0';
flush_and_return_to_zero <= '0';
end if;
else
red_value <= '0';
green_value <= '0';
blue_value <= '0';
write_enable <= '0';
flush_and_return_to_zero <= '0';
end if;
end if;
end process;
end behavioral;
| mit | b4c6126f090fa6ae705e0fbb378329f2 | 0.519901 | 4.355162 | false | false | false | false |
ntb-ch/cb20 | FPGA_Designs/standard/cb20/synthesis/cb20_pwm_interface_0_avalon_slave_0_translator.vhd | 1 | 14,679 | -- cb20_pwm_interface_0_avalon_slave_0_translator.vhd
-- Generated using ACDS version 13.0sp1 232 at 2020.05.28.12:22:46
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity cb20_pwm_interface_0_avalon_slave_0_translator is
generic (
AV_ADDRESS_W : integer := 6;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 1;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 17;
UAV_BURSTCOUNT_W : integer := 3;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 0;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 1;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := '0'; -- clk.clk
reset : in std_logic := '0'; -- reset.reset
uav_address : in std_logic_vector(16 downto 0) := (others => '0'); -- avalon_universal_slave_0.address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => '0'); -- .burstcount
uav_read : in std_logic := '0'; -- .read
uav_write : in std_logic := '0'; -- .write
uav_waitrequest : out std_logic; -- .waitrequest
uav_readdatavalid : out std_logic; -- .readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => '0'); -- .byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- .readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
uav_lock : in std_logic := '0'; -- .lock
uav_debugaccess : in std_logic := '0'; -- .debugaccess
av_address : out std_logic_vector(5 downto 0); -- avalon_anti_slave_0.address
av_write : out std_logic; -- .write
av_read : out std_logic; -- .read
av_readdata : in std_logic_vector(31 downto 0) := (others => '0'); -- .readdata
av_writedata : out std_logic_vector(31 downto 0); -- .writedata
av_byteenable : out std_logic_vector(3 downto 0); -- .byteenable
av_waitrequest : in std_logic := '0'; -- .waitrequest
av_beginbursttransfer : out std_logic;
av_begintransfer : out std_logic;
av_burstcount : out std_logic_vector(0 downto 0);
av_chipselect : out std_logic;
av_clken : out std_logic;
av_debugaccess : out std_logic;
av_lock : out std_logic;
av_outputenable : out std_logic;
av_readdatavalid : in std_logic := '0';
av_response : in std_logic_vector(1 downto 0) := (others => '0');
av_writebyteenable : out std_logic_vector(3 downto 0);
av_writeresponserequest : out std_logic;
av_writeresponsevalid : in std_logic := '0';
uav_clken : in std_logic := '0';
uav_response : out std_logic_vector(1 downto 0);
uav_writeresponserequest : in std_logic := '0';
uav_writeresponsevalid : out std_logic
);
end entity cb20_pwm_interface_0_avalon_slave_0_translator;
architecture rtl of cb20_pwm_interface_0_avalon_slave_0_translator is
component altera_merlin_slave_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(16 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(5 downto 0); -- address
av_write : out std_logic; -- write
av_read : out std_logic; -- read
av_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(31 downto 0); -- writedata
av_byteenable : out std_logic_vector(3 downto 0); -- byteenable
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_writebyteenable : out std_logic_vector(3 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_chipselect : out std_logic; -- chipselect
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic; -- outputenable
uav_response : out std_logic_vector(1 downto 0); -- response
av_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response
uav_writeresponserequest : in std_logic := 'X'; -- writeresponserequest
uav_writeresponsevalid : out std_logic; -- writeresponsevalid
av_writeresponserequest : out std_logic; -- writeresponserequest
av_writeresponsevalid : in std_logic := 'X' -- writeresponsevalid
);
end component altera_merlin_slave_translator;
begin
pwm_interface_0_avalon_slave_0_translator : component altera_merlin_slave_translator
generic map (
AV_ADDRESS_W => AV_ADDRESS_W,
AV_DATA_W => AV_DATA_W,
UAV_DATA_W => UAV_DATA_W,
AV_BURSTCOUNT_W => AV_BURSTCOUNT_W,
AV_BYTEENABLE_W => AV_BYTEENABLE_W,
UAV_BYTEENABLE_W => UAV_BYTEENABLE_W,
UAV_ADDRESS_W => UAV_ADDRESS_W,
UAV_BURSTCOUNT_W => UAV_BURSTCOUNT_W,
AV_READLATENCY => AV_READLATENCY,
USE_READDATAVALID => USE_READDATAVALID,
USE_WAITREQUEST => USE_WAITREQUEST,
USE_UAV_CLKEN => USE_UAV_CLKEN,
USE_READRESPONSE => USE_READRESPONSE,
USE_WRITERESPONSE => USE_WRITERESPONSE,
AV_SYMBOLS_PER_WORD => AV_SYMBOLS_PER_WORD,
AV_ADDRESS_SYMBOLS => AV_ADDRESS_SYMBOLS,
AV_BURSTCOUNT_SYMBOLS => AV_BURSTCOUNT_SYMBOLS,
AV_CONSTANT_BURST_BEHAVIOR => AV_CONSTANT_BURST_BEHAVIOR,
UAV_CONSTANT_BURST_BEHAVIOR => UAV_CONSTANT_BURST_BEHAVIOR,
AV_REQUIRE_UNALIGNED_ADDRESSES => AV_REQUIRE_UNALIGNED_ADDRESSES,
CHIPSELECT_THROUGH_READLATENCY => CHIPSELECT_THROUGH_READLATENCY,
AV_READ_WAIT_CYCLES => AV_READ_WAIT_CYCLES,
AV_WRITE_WAIT_CYCLES => AV_WRITE_WAIT_CYCLES,
AV_SETUP_WAIT_CYCLES => AV_SETUP_WAIT_CYCLES,
AV_DATA_HOLD_CYCLES => AV_DATA_HOLD_CYCLES
)
port map (
clk => clk, -- clk.clk
reset => reset, -- reset.reset
uav_address => uav_address, -- avalon_universal_slave_0.address
uav_burstcount => uav_burstcount, -- .burstcount
uav_read => uav_read, -- .read
uav_write => uav_write, -- .write
uav_waitrequest => uav_waitrequest, -- .waitrequest
uav_readdatavalid => uav_readdatavalid, -- .readdatavalid
uav_byteenable => uav_byteenable, -- .byteenable
uav_readdata => uav_readdata, -- .readdata
uav_writedata => uav_writedata, -- .writedata
uav_lock => uav_lock, -- .lock
uav_debugaccess => uav_debugaccess, -- .debugaccess
av_address => av_address, -- avalon_anti_slave_0.address
av_write => av_write, -- .write
av_read => av_read, -- .read
av_readdata => av_readdata, -- .readdata
av_writedata => av_writedata, -- .writedata
av_byteenable => av_byteenable, -- .byteenable
av_waitrequest => av_waitrequest, -- .waitrequest
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_chipselect => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open, -- (terminated)
uav_response => open, -- (terminated)
av_response => "00", -- (terminated)
uav_writeresponserequest => '0', -- (terminated)
uav_writeresponsevalid => open, -- (terminated)
av_writeresponserequest => open, -- (terminated)
av_writeresponsevalid => '0' -- (terminated)
);
end architecture rtl; -- of cb20_pwm_interface_0_avalon_slave_0_translator
| apache-2.0 | 38f6d72e8adf3b22d010d642d8aca705 | 0.430411 | 4.340331 | false | false | false | false |
markusC64/1541ultimate2 | fpga/ip/nano_cpu/vhdl_source/nano.vhd | 1 | 4,315 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.nano_cpu_pkg.all;
use work.io_bus_pkg.all;
library unisim;
use unisim.vcomponents.all;
entity nano is
generic (
g_big_endian : boolean := false );
port (
clock : in std_logic;
reset : in std_logic;
-- i/o interface
io_addr : out unsigned(7 downto 0);
io_write : out std_logic;
io_read : out std_logic;
io_wdata : out std_logic_vector(15 downto 0);
io_rdata : in std_logic_vector(15 downto 0);
stall : in std_logic;
-- system interface (to write code into the nano)
sys_clock : in std_logic := '0';
sys_reset : in std_logic := '0';
sys_io_req : in t_io_req := c_io_req_init;
sys_io_resp : out t_io_resp );
end entity;
architecture structural of nano is
signal sys_enable : std_logic;
signal sys_bram_addr : std_logic_vector(10 downto 0);
-- instruction/data ram
signal ram_addr : std_logic_vector(9 downto 0);
signal ram_en : std_logic;
signal ram_we : std_logic;
signal ram_wdata : std_logic_vector(15 downto 0);
signal ram_rdata : std_logic_vector(15 downto 0);
signal sys_io_req_bram : t_io_req;
signal sys_io_resp_bram : t_io_resp;
signal sys_io_req_regs : t_io_req;
signal sys_io_resp_regs : t_io_resp;
signal sys_core_reset : std_logic := '1';
signal usb_reset_tig : std_logic := '1';
signal usb_core_reset : std_logic := '1';
signal bram_data : std_logic_vector(7 downto 0);
begin
i_split: entity work.io_bus_splitter
generic map (
g_range_lo => 11,
g_range_hi => 11,
g_ports => 2 )
port map (
clock => sys_clock,
req => sys_io_req,
resp => sys_io_resp,
reqs(0) => sys_io_req_bram,
reqs(1) => sys_io_req_regs,
resps(0) => sys_io_resp_bram,
resps(1) => sys_io_resp_regs );
i_core: entity work.nano_cpu
port map (
clock => clock,
reset => usb_core_reset,
-- instruction/data ram
ram_addr => ram_addr,
ram_en => ram_en,
ram_we => ram_we,
ram_wdata => ram_wdata,
ram_rdata => ram_rdata,
-- i/o interface
io_addr => io_addr,
io_write => io_write,
io_read => io_read,
io_wdata => io_wdata,
io_rdata => io_rdata,
stall => stall );
--i_buf_ram: entity work.RAMB16_S9_S18(model)
i_buf_ram: RAMB16_S9_S18
port map (
CLKB => clock,
SSRB => reset,
ENB => ram_en,
WEB => ram_we,
ADDRB => ram_addr,
DIB => ram_wdata,
DIPB => "00",
DOB => ram_rdata,
CLKA => sys_clock,
SSRA => sys_reset,
ENA => sys_enable,
WEA => sys_io_req_bram.write,
ADDRA => sys_bram_addr,
DIA => sys_io_req_bram.data,
DIPA => "0",
DOA => bram_data );
sys_bram_addr(10 downto 1) <= std_logic_vector(sys_io_req_bram.address(10 downto 1));
sys_bram_addr(0) <= not sys_io_req_bram.address(0) when g_big_endian else sys_io_req_bram.address(0);
sys_enable <= sys_io_req_bram.write or sys_io_req_bram.read;
sys_io_resp_bram.data <= bram_data when sys_io_resp_bram.ack = '1' else X"00";
process(sys_clock)
begin
if rising_edge(sys_clock) then
sys_io_resp_bram.ack <= sys_enable;
sys_io_resp_regs <= c_io_resp_init;
sys_io_resp_regs.ack <= sys_io_req_regs.write or sys_io_req_regs.read;
if sys_io_req_regs.write = '1' then -- any address
sys_core_reset <= not sys_io_req_regs.data(0);
end if;
if sys_reset = '1' then
sys_core_reset <= '1';
end if;
end if;
end process;
process(clock)
begin
if rising_edge(clock) then
usb_reset_tig <= sys_core_reset;
usb_core_reset <= usb_reset_tig;
end if;
end process;
end architecture;
| gpl-3.0 | c675e351304ff4f69d4370ce97f53bc0 | 0.514021 | 3.172794 | false | false | false | false |
markusC64/1541ultimate2 | fpga/nios_tester/nios_tester/synthesis/submodules/sync_fifo.vhd | 2 | 5,324 | library ieee;
use ieee.std_logic_1164.all;
entity sync_fifo is
generic (
g_depth : integer := 512; -- Actual depth.
g_data_width : integer := 32;
g_threshold : integer := 13;
g_storage : string := "auto"; -- can also be "blockram" or "distributed"
g_fall_through : boolean := false);
port (
clock : in std_logic;
reset : in std_logic;
rd_en : in std_logic;
wr_en : in std_logic;
din : in std_logic_vector(g_data_width-1 downto 0);
dout : out std_logic_vector(g_data_width-1 downto 0);
flush : in std_logic;
full : out std_logic;
almost_full : out std_logic;
empty : out std_logic;
valid : out std_logic;
count : out integer range 0 to g_depth
);
end sync_fifo;
architecture rtl of sync_fifo is
subtype t_data_element is std_logic_vector(g_data_width-1 downto 0);
type t_data_array is array (0 to g_depth-1) of t_data_element;
signal data_array : t_data_array;
attribute ram_style : string;
attribute ram_style of data_array : signal is g_storage;
attribute ramstyle : string;
attribute ramstyle of data_array : signal is g_storage;
signal rd_en_flt : std_logic;
signal rd_enable : std_logic;
signal rd_pnt : integer range 0 to g_depth-1;
signal rd_pnt_next : integer range 0 to g_depth-1;
signal wr_en_flt : std_logic;
signal wr_pnt : integer range 0 to g_depth-1;
signal num_el : integer range 0 to g_depth;
signal full_i : std_logic;
signal empty_i : std_logic;
signal valid_i : std_logic;
begin
-- Check generic values (also for synthesis)
assert(g_threshold <= g_depth) report "Invalid parameter 'g_threshold'" severity failure;
-- Filter fifo read/write enables for full/empty conditions
rd_en_flt <= '1' when (empty_i = '0') and (rd_en='1') else '0';
wr_en_flt <= '1' when (full_i = '0') and (wr_en='1') else '0';
-- Read enable depends on 'fall through' mode.
-- In fall through mode, rd_enable is true when fifo is not empty and either rd_en_flt is '1' or output is invalid
-- In non-fall through mode, rd_enable is only true when rd_en_flt = '1'
rd_enable <= rd_en_flt or (not empty_i and not valid_i) when g_fall_through else
rd_en_flt;
p_dpram: process(clock)
begin
if rising_edge(clock) then
if (wr_en_flt = '1') then
data_array(wr_pnt) <= din;
end if;
if (rd_enable = '1') then
dout <= data_array(rd_pnt);
end if;
end if;
end process;
rd_pnt_next <= 0 when (rd_pnt=g_depth-1) else rd_pnt + 1;
process(clock)
variable v_new_cnt : integer range 0 to g_depth;
begin
if rising_edge(clock) then
-- data on the output becomes valid after an external read OR after an automatic read when fifo is not empty.
if rd_en = '1' then
valid_i <= not empty_i;
elsif valid_i = '0' and empty_i = '0' and g_fall_through then
valid_i <= '1';
end if;
-- Modify read/write pointers
if (rd_enable='1') then
rd_pnt <= rd_pnt_next;
end if;
if (wr_en_flt='1') then
if (wr_pnt=g_depth-1) then
wr_pnt <= 0;
else
wr_pnt <= wr_pnt + 1;
end if;
end if;
-- Update number of elements in fifo for next clock cycle
if (rd_enable = '1') and (wr_en_flt = '0') then
v_new_cnt := num_el - 1;
elsif (rd_enable = '0') and (wr_en_flt = '1') then
v_new_cnt := num_el + 1;
elsif (flush='1') then
v_new_cnt := 0;
else
v_new_cnt := num_el;
end if;
num_el <= v_new_cnt;
-- update (almost)full and empty indications
almost_full <= '0';
if (v_new_cnt >= g_threshold) then
almost_full <= '1';
end if;
empty_i <= '0';
if (v_new_cnt = 0) then
empty_i <= '1';
end if;
full_i <= '0';
if (v_new_cnt = g_depth) then
full_i <= '1';
end if;
if (flush='1') or (reset='1') then
rd_pnt <= 0;
wr_pnt <= 0;
num_el <= 0;
full_i <= '0';
empty_i <= '1';
valid_i <= '0';
almost_full <= '0';
end if;
end if;
end process;
count <= num_el;
empty <= empty_i when not g_fall_through else not valid_i;
full <= full_i;
valid <= valid_i;
end rtl;
| gpl-3.0 | d2be2f5825950701e19912d3db4bd80c | 0.466003 | 3.76787 | false | false | false | false |
markusC64/1541ultimate2 | fpga/cart_slot/vhdl_source/slot_master_v4.vhd | 1 | 8,989 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.dma_bus_pkg.all;
entity slot_master_v4 is
generic (
g_start_in_stopped_state : boolean := false );
port (
clock : in std_logic;
reset : in std_logic;
-- Cartridge pins
DMAn : out std_logic := '1';
BA : in std_logic := '0';
RWn_in : in std_logic;
RWn_out : out std_logic;
RWn_tri : out std_logic;
ADDRESS_out : out std_logic_vector(15 downto 0);
ADDRESS_tri_h : out std_logic;
ADDRESS_tri_l : out std_logic;
DATA_in : in std_logic_vector(7 downto 0);
DATA_out : out std_logic_vector(7 downto 0) := (others => '1');
DATA_tri : out std_logic;
-- timing inputs
vic_cycle : in std_logic;
phi2_recovered : in std_logic;
phi2_tick : in std_logic;
do_sample_addr : in std_logic;
do_io_event : in std_logic;
reu_dma_n : in std_logic := '1';
cmd_if_freeze : in std_logic := '0';
-- request from the memory controller to do a cycle on the cart bus
dma_req : in t_dma_req;
dma_resp : out t_dma_resp;
-- system control
stop_cond : in std_logic_vector(1 downto 0);
c64_stop : in std_logic; -- condition to start looking for a stop moment
c64_stopped : out std_logic ); -- indicates that stopping has succeeded
end slot_master_v4;
architecture gideon of slot_master_v4 is
signal ba_c : std_logic;
signal rwn_c : std_logic := '1';
signal dma_n_i : std_logic := '1';
signal data_c : std_logic_vector(7 downto 0) := (others => '1');
type t_byte_array is array(natural range <>) of std_logic_vector(7 downto 0);
signal data_d : t_byte_array(0 to 7);
signal addr_out : std_logic_vector(15 downto 0) := (others => '1');
signal drive_ah : std_logic;
signal drive_al : std_logic;
signal dma_ack_i : std_logic;
signal rwn_out_i : std_logic;
signal phi2_dly : std_logic_vector(6 downto 0) := (others => '0');
signal reu_active : std_logic;
signal cmd_if_active: std_logic;
constant match_ptrn : std_logic_vector(1 downto 0) := "01"; -- read from left to right
signal rwn_hist : std_logic_vector(3 downto 0);
signal ba_count : integer range 0 to 15;
signal c64_stopped_i: std_logic;
attribute register_duplication : string;
attribute register_duplication of rwn_c : signal is "no";
attribute register_duplication of ba_c : signal is "no";
attribute keep : string;
attribute keep of rwn_hist : signal is "true";
type t_state is (idle, stopped, do_dma );
signal state : t_state;
-- attribute fsm_encoding : string;
-- attribute fsm_encoding of state : signal is "sequential";
signal dma_rack : std_logic;
begin
process(clock)
variable stop : boolean;
begin
if rising_edge(clock) then
ba_c <= BA;
rwn_c <= RWn_in;
data_c <= DATA_in;
data_d(0) <= data_c;
data_d(1 to 7) <= data_d(0 to 6);
dma_rack <= '0';
phi2_dly <= phi2_dly(phi2_dly'high-1 downto 0) & phi2_recovered;
-- consecutive write counter (match counter)
if do_sample_addr='1' and phi2_recovered='1' then -- count CPU cycles only (sample might become true for VIC cycles)
-- the following statement detects a bad line. VIC wants bus. We just wait in line until VIC is done,
-- by pulling DMA low halfway the bad line. This is the safest method.
if ba_c='0' then
if ba_count /= 15 then
ba_count <= ba_count + 1;
end if;
else
ba_count <= 0;
end if;
-- the following statement detects a rw/n pattern, that indicates that it's safe to pull dma low
rwn_hist <= rwn_hist(rwn_hist'high-1 downto 0) & rwn_c;
end if;
case stop_cond is
when "00" => stop := (ba_count = 14);
when "01" => stop := (rwn_hist(match_ptrn'range) = match_ptrn);
when others => stop := true;
end case;
case state is
when idle =>
dma_ack_i <= dma_req.request and dma_req.read_writen; -- do not serve DMA requests when machine is not stopped
dma_rack <= dma_req.request;
if reu_dma_n='0' then
reu_active <= '1';
dma_n_i <= '0';
state <= stopped;
elsif cmd_if_freeze='1' then
cmd_if_active <= '1';
dma_n_i <= '0';
state <= stopped;
elsif c64_stop='1' and do_io_event='1' then
if stop then
dma_n_i <= '0';
state <= stopped;
c64_stopped_i <= '1';
end if;
end if;
when stopped =>
dma_ack_i <= '0';
rwn_out_i <= '1';
addr_out(15 downto 14) <= "00"; -- always in a safe area
-- is the dma request active and are we at the right time?
if dma_req.request='1' and dma_ack_i='0' and phi2_tick='1' and ba_c='1' then
dma_rack <= '1';
DATA_out <= dma_req.data;
addr_out <= std_logic_vector(dma_req.address);
rwn_out_i <= dma_req.read_writen;
state <= do_dma;
elsif reu_active='1' and reu_dma_n='1' and do_io_event='1' then
dma_n_i <= '1';
reu_active <= '0';
state <= idle;
elsif cmd_if_active='1' and cmd_if_freeze='0' and do_io_event='1' then
dma_n_i <= '1';
cmd_if_active <= '0';
state <= idle;
elsif c64_stopped_i = '1' and c64_stop = '0' and do_io_event='1' then
if stop then
c64_stopped_i <= '0';
dma_n_i <= '1';
state <= idle;
end if;
end if;
when do_dma =>
if phi2_recovered='0' then -- end of CPU cycle
--if do_io_event='1' then
dma_ack_i <= '1';
state <= stopped;
end if;
when others =>
null;
end case;
drive_ah <= drive_al; -- one cycle later on (SSO)
if (dma_n_i='0' and phi2_recovered='1' and vic_cycle='0') then
drive_al <= '1';
else
drive_al <= '0';
drive_ah <= '0'; -- off at the same time
end if;
if reset='1' then
reu_active <= '0';
cmd_if_active <= '0';
if g_start_in_stopped_state then
state <= stopped;
dma_n_i <= '0';
c64_stopped_i <= '1';
else
state <= idle;
dma_n_i <= '1';
c64_stopped_i <= '0';
end if;
rwn_out_i <= '1';
addr_out <= (others => '1');
end if;
end if;
end process;
c64_stopped <= c64_stopped_i;
dma_resp.dack <= dma_ack_i and rwn_out_i; -- only data-acknowledge reads
dma_resp.rack <= dma_rack;
dma_resp.data <= data_d(3) when dma_ack_i='1' and rwn_out_i='1' else X"00";
-- by shifting the phi2 and anding it with the original, we make the write enable narrower,
-- starting only halfway through the cycle. We should not be too fast!
DATA_tri <= '1' when (dma_n_i='0' and phi2_recovered='1' and phi2_dly(phi2_dly'high)='1' and
vic_cycle='0' and rwn_out_i='0') else '0';
RWn_tri <= drive_al; --'1' when (dma_n_i='0' and phi2_recovered='1' and ba_c='1') else '0';
ADDRESS_out <= addr_out;
ADDRESS_tri_h <= drive_ah;
ADDRESS_tri_l <= drive_al;
RWn_out <= rwn_out_i;
DMAn <= dma_n_i;
end gideon;
| gpl-3.0 | be4bc6014a5842d84225056b4aac6ab8 | 0.454556 | 3.751669 | false | false | false | false |
markusC64/1541ultimate2 | fpga/ip/busses/vhdl_source/io_bus_arbiter_pri.vhd | 1 | 2,224 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
entity io_bus_arbiter_pri is
generic (
g_ports : positive := 3 );
port (
clock : in std_logic;
reset : in std_logic;
reqs : in t_io_req_array(0 to g_ports-1);
resps : out t_io_resp_array(0 to g_ports-1);
req : out t_io_req;
resp : in t_io_resp );
end entity;
architecture rtl of io_bus_arbiter_pri is
signal req_i : t_io_req;
signal select_i : integer range 0 to g_ports-1;
signal select_c : integer range 0 to g_ports-1;
type t_state is (idle, busy);
signal state : t_state;
begin
-- prioritize the first request found onto output
process(reqs)
begin
req_i <= c_io_req_init;
select_i <= 0;
for i in reqs'range loop
if reqs(i).read='1' or reqs(i).write='1' then
req_i <= reqs(i);
select_i <= i;
exit;
end if;
end loop;
end process;
p_access: process(clock)
begin
if rising_edge(clock) then
case state is
when idle =>
req <= req_i;
if req_i.read='1' then
select_c <= select_i;
state <= busy;
elsif req_i.write='1' then
select_c <= select_i;
state <= busy;
end if;
when busy =>
req.read <= '0';
req.write <= '0';
if resp.ack='1' then
state <= idle;
end if;
when others =>
null;
end case;
end if;
end process;
-- send the reply to everyone, but mask the acks to non-active clients
process(resp, select_c)
begin
for i in resps'range loop
resps(i) <= resp;
if i /= select_c then
resps(i).ack <= '0';
end if;
end loop;
end process;
end architecture;
| gpl-3.0 | b21fb003479edb922431e3150d08ae26 | 0.447842 | 3.834483 | false | false | false | false |
xiadz/oscilloscope | src/tests/test_types.vhd | 1 | 741 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE work.types.all;
ENTITY test_types IS
END test_types;
ARCHITECTURE behavior OF test_types IS
signal tested_num : integer range 0 to 127;
signal tested_num2 : integer range 0 to 127;
signal tested_short_char : short_character;
BEGIN
stim_proc: process
begin
for i in 0 to 127 loop
tested_num <= i;
tested_short_char <= character_conv_table (i);
wait for 1 ns;
tested_num2 <= short_character'pos (tested_short_char);
wait for 1 ns;
assert tested_num = tested_num2;
assert tested_short_char = short_character'val (i);
end loop;
wait;
end process;
END;
| mit | 0f8f8a7dbd9b64eb2883d4572020c4d2 | 0.630229 | 3.57971 | false | true | false | false |
markusC64/1541ultimate2 | fpga/nios_dut/nios_dut/synthesis/nios_dut_rst_controller_001.vhd | 1 | 9,116 | -- nios_dut_rst_controller_001.vhd
-- Generated using ACDS version 15.1 185
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nios_dut_rst_controller_001 is
generic (
NUM_RESET_INPUTS : integer := 2;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 1;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := '0'; -- reset_in0.reset
reset_in1 : in std_logic := '0'; -- reset_in1.reset
clk : in std_logic := '0'; -- clk.clk
reset_out : out std_logic; -- reset_out.reset
reset_req : out std_logic; -- .reset_req
reset_in10 : in std_logic := '0';
reset_in11 : in std_logic := '0';
reset_in12 : in std_logic := '0';
reset_in13 : in std_logic := '0';
reset_in14 : in std_logic := '0';
reset_in15 : in std_logic := '0';
reset_in2 : in std_logic := '0';
reset_in3 : in std_logic := '0';
reset_in4 : in std_logic := '0';
reset_in5 : in std_logic := '0';
reset_in6 : in std_logic := '0';
reset_in7 : in std_logic := '0';
reset_in8 : in std_logic := '0';
reset_in9 : in std_logic := '0';
reset_req_in0 : in std_logic := '0';
reset_req_in1 : in std_logic := '0';
reset_req_in10 : in std_logic := '0';
reset_req_in11 : in std_logic := '0';
reset_req_in12 : in std_logic := '0';
reset_req_in13 : in std_logic := '0';
reset_req_in14 : in std_logic := '0';
reset_req_in15 : in std_logic := '0';
reset_req_in2 : in std_logic := '0';
reset_req_in3 : in std_logic := '0';
reset_req_in4 : in std_logic := '0';
reset_req_in5 : in std_logic := '0';
reset_req_in6 : in std_logic := '0';
reset_req_in7 : in std_logic := '0';
reset_req_in8 : in std_logic := '0';
reset_req_in9 : in std_logic := '0'
);
end entity nios_dut_rst_controller_001;
architecture rtl of nios_dut_rst_controller_001 is
component altera_reset_controller is
generic (
NUM_RESET_INPUTS : integer := 6;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 0;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := 'X'; -- reset
reset_in1 : in std_logic := 'X'; -- reset
clk : in std_logic := 'X'; -- clk
reset_out : out std_logic; -- reset
reset_req : out std_logic; -- reset_req
reset_req_in0 : in std_logic := 'X'; -- reset_req
reset_req_in1 : in std_logic := 'X'; -- reset_req
reset_in2 : in std_logic := 'X'; -- reset
reset_req_in2 : in std_logic := 'X'; -- reset_req
reset_in3 : in std_logic := 'X'; -- reset
reset_req_in3 : in std_logic := 'X'; -- reset_req
reset_in4 : in std_logic := 'X'; -- reset
reset_req_in4 : in std_logic := 'X'; -- reset_req
reset_in5 : in std_logic := 'X'; -- reset
reset_req_in5 : in std_logic := 'X'; -- reset_req
reset_in6 : in std_logic := 'X'; -- reset
reset_req_in6 : in std_logic := 'X'; -- reset_req
reset_in7 : in std_logic := 'X'; -- reset
reset_req_in7 : in std_logic := 'X'; -- reset_req
reset_in8 : in std_logic := 'X'; -- reset
reset_req_in8 : in std_logic := 'X'; -- reset_req
reset_in9 : in std_logic := 'X'; -- reset
reset_req_in9 : in std_logic := 'X'; -- reset_req
reset_in10 : in std_logic := 'X'; -- reset
reset_req_in10 : in std_logic := 'X'; -- reset_req
reset_in11 : in std_logic := 'X'; -- reset
reset_req_in11 : in std_logic := 'X'; -- reset_req
reset_in12 : in std_logic := 'X'; -- reset
reset_req_in12 : in std_logic := 'X'; -- reset_req
reset_in13 : in std_logic := 'X'; -- reset
reset_req_in13 : in std_logic := 'X'; -- reset_req
reset_in14 : in std_logic := 'X'; -- reset
reset_req_in14 : in std_logic := 'X'; -- reset_req
reset_in15 : in std_logic := 'X'; -- reset
reset_req_in15 : in std_logic := 'X' -- reset_req
);
end component altera_reset_controller;
begin
rst_controller_001 : component altera_reset_controller
generic map (
NUM_RESET_INPUTS => NUM_RESET_INPUTS,
OUTPUT_RESET_SYNC_EDGES => OUTPUT_RESET_SYNC_EDGES,
SYNC_DEPTH => SYNC_DEPTH,
RESET_REQUEST_PRESENT => RESET_REQUEST_PRESENT,
RESET_REQ_WAIT_TIME => RESET_REQ_WAIT_TIME,
MIN_RST_ASSERTION_TIME => MIN_RST_ASSERTION_TIME,
RESET_REQ_EARLY_DSRT_TIME => RESET_REQ_EARLY_DSRT_TIME,
USE_RESET_REQUEST_IN0 => USE_RESET_REQUEST_IN0,
USE_RESET_REQUEST_IN1 => USE_RESET_REQUEST_IN1,
USE_RESET_REQUEST_IN2 => USE_RESET_REQUEST_IN2,
USE_RESET_REQUEST_IN3 => USE_RESET_REQUEST_IN3,
USE_RESET_REQUEST_IN4 => USE_RESET_REQUEST_IN4,
USE_RESET_REQUEST_IN5 => USE_RESET_REQUEST_IN5,
USE_RESET_REQUEST_IN6 => USE_RESET_REQUEST_IN6,
USE_RESET_REQUEST_IN7 => USE_RESET_REQUEST_IN7,
USE_RESET_REQUEST_IN8 => USE_RESET_REQUEST_IN8,
USE_RESET_REQUEST_IN9 => USE_RESET_REQUEST_IN9,
USE_RESET_REQUEST_IN10 => USE_RESET_REQUEST_IN10,
USE_RESET_REQUEST_IN11 => USE_RESET_REQUEST_IN11,
USE_RESET_REQUEST_IN12 => USE_RESET_REQUEST_IN12,
USE_RESET_REQUEST_IN13 => USE_RESET_REQUEST_IN13,
USE_RESET_REQUEST_IN14 => USE_RESET_REQUEST_IN14,
USE_RESET_REQUEST_IN15 => USE_RESET_REQUEST_IN15,
ADAPT_RESET_REQUEST => ADAPT_RESET_REQUEST
)
port map (
reset_in0 => reset_in0, -- reset_in0.reset
reset_in1 => reset_in1, -- reset_in1.reset
clk => clk, -- clk.clk
reset_out => reset_out, -- reset_out.reset
reset_req => reset_req, -- .reset_req
reset_req_in0 => '0', -- (terminated)
reset_req_in1 => '0', -- (terminated)
reset_in2 => '0', -- (terminated)
reset_req_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_req_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_req_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_req_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_req_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_req_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_req_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_req_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_req_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_req_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_req_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_req_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_req_in14 => '0', -- (terminated)
reset_in15 => '0', -- (terminated)
reset_req_in15 => '0' -- (terminated)
);
end architecture rtl; -- of nios_dut_rst_controller_001
| gpl-3.0 | 80d1540a88be6d22045fc75914ee0249 | 0.547938 | 2.72282 | false | false | false | false |
markusC64/1541ultimate2 | fpga/fpga_top/cyclone4_test/vhdl_source/u2p_slot_tester.vhd | 1 | 6,040 | -------------------------------------------------------------------------------
-- Title : u2p_slot_tester
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: Toplevel for u2p_slot_tester.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity u2p_slot_tester is
port (
-- slot side
SLOT_BUFFER_ENn : out std_logic;
SLOT_PHI2 : in std_logic;
SLOT_DOTCLK : in std_logic;
SLOT_BA : in std_logic;
SLOT_RSTn : in std_logic;
SLOT_ADDR : inout std_logic_vector(15 downto 0);
SLOT_DATA : inout std_logic_vector(7 downto 0);
SLOT_RWn : inout std_logic;
SLOT_DMAn : inout std_logic;
SLOT_EXROMn : inout std_logic;
SLOT_GAMEn : inout std_logic;
SLOT_ROMHn : in std_logic;
SLOT_ROMLn : in std_logic;
SLOT_IO1n : in std_logic;
SLOT_IO2n : in std_logic;
SLOT_IRQn : inout std_logic;
SLOT_NMIn : inout std_logic;
SLOT_VCC : in std_logic;
-- memory
SDRAM_A : out std_logic_vector(13 downto 0) := (others => '0'); -- DRAM A
SDRAM_BA : out std_logic_vector(2 downto 0) := (others => '0');
SDRAM_DQ : inout std_logic_vector(7 downto 0) := (others => 'Z');
SDRAM_DM : inout std_logic := 'Z';
SDRAM_CSn : out std_logic := '1';
SDRAM_RASn : out std_logic := '1';
SDRAM_CASn : out std_logic := '1';
SDRAM_WEn : out std_logic := '1';
SDRAM_CKE : out std_logic := '1';
SDRAM_CLK : out std_logic := '1';
SDRAM_CLKn : out std_logic := '1';
SDRAM_ODT : out std_logic := '1';
SDRAM_DQS : inout std_logic := 'Z';
AUDIO_MCLK : out std_logic := '0';
AUDIO_BCLK : out std_logic := '0';
AUDIO_LRCLK : out std_logic := '0';
AUDIO_SDO : out std_logic := '0';
AUDIO_SDI : in std_logic;
-- IEC bus
IEC_ATN : inout std_logic;
IEC_DATA : inout std_logic;
IEC_CLOCK : inout std_logic;
IEC_RESET : inout std_logic;
IEC_SRQ_IN : inout std_logic;
LED_DISKn : out std_logic; -- activity LED
LED_CARTn : out std_logic;
LED_SDACTn : out std_logic;
LED_MOTORn : out std_logic;
-- Ethernet RMII
ETH_RESETn : out std_logic := '1';
ETH_IRQn : in std_logic;
RMII_REFCLK : in std_logic;
RMII_CRS_DV : in std_logic;
RMII_RX_ER : in std_logic;
RMII_RX_DATA : in std_logic_vector(1 downto 0);
RMII_TX_DATA : out std_logic_vector(1 downto 0) := "00";
RMII_TX_EN : out std_logic := '0';
MDIO_CLK : out std_logic := '0';
MDIO_DATA : inout std_logic := 'Z';
-- Speaker data
SPEAKER_DATA : out std_logic := '0';
SPEAKER_ENABLE : out std_logic := '0';
-- Debug UART
UART_TXD : out std_logic := '1';
UART_RXD : in std_logic;
-- I2C Interface for RTC, audio codec and usb hub
I2C_SDA : inout std_logic := 'Z';
I2C_SCL : inout std_logic := 'Z';
I2C_SDA_18 : inout std_logic := 'Z';
I2C_SCL_18 : inout std_logic := 'Z';
-- Flash Interface
FLASH_CSn : out std_logic := '1';
FLASH_SCK : out std_logic := '1';
FLASH_MOSI : out std_logic := '1';
FLASH_MISO : in std_logic;
FLASH_SEL : out std_logic := '0';
FLASH_SELCK : out std_logic := '0';
-- USB Interface (ULPI)
ULPI_RESET : out std_logic := '1';
ULPI_CLOCK : in std_logic;
ULPI_NXT : in std_logic;
ULPI_STP : out std_logic := '1';
ULPI_DIR : in std_logic;
ULPI_DATA : inout std_logic_vector(7 downto 0) := (others => 'Z');
HUB_RESETn : out std_logic := '1';
HUB_CLOCK : out std_logic := '0';
-- Misc
BOARD_REVn : in std_logic_vector(4 downto 0);
-- Cassette Interface
CAS_MOTOR : in std_logic := '0';
CAS_SENSE : in std_logic := '0';
CAS_READ : in std_logic := '0';
CAS_WRITE : in std_logic := '0';
-- Buttons
BUTTON : in std_logic_vector(2 downto 0));
end entity;
architecture rtl of u2p_slot_tester is
signal por_n : std_logic;
signal ref_reset : std_logic;
signal por_count : unsigned(19 downto 0) := (others => '0');
begin
process(RMII_REFCLK)
begin
if rising_edge(RMII_REFCLK) then
if por_count = X"FFFFF" then
por_n <= '1';
else
por_count <= por_count + 1;
por_n <= '0';
end if;
end if;
end process;
ref_reset <= not por_n;
i_tester: entity work.u64test_remote
port map(
arst => ref_reset,
BUTTON => BUTTON,
PHI2 => SLOT_PHI2,
DOTCLK => SLOT_DOTCLK,
IO1n => SLOT_IO1n,
IO2n => SLOT_IO2n,
ROMLn => SLOT_ROMLn,
ROMHn => SLOT_ROMHn,
BA => SLOT_BA,
RWn => SLOT_RWn,
GAMEn => SLOT_GAMEn,
EXROMn => SLOT_EXROMn,
DMAn => SLOT_DMAn,
IRQn => SLOT_IRQn,
NMIn => SLOT_NMIn,
RESETn => SLOT_RSTn,
D => SLOT_DATA,
A => SLOT_ADDR,
LED_DISKn => LED_DISKn,
LED_CARTn => LED_CARTn,
LED_SDACTn => LED_SDACTn,
LED_MOTORn => LED_MOTORn,
IEC_SRQ => IEC_SRQ_IN,
IEC_RST => IEC_RESET,
IEC_CLK => IEC_CLOCK,
IEC_DATA => IEC_DATA,
IEC_ATN => IEC_ATN,
CAS_READ => CAS_READ,
CAS_WRITE => CAS_WRITE,
CAS_MOTOR => CAS_MOTOR,
CAS_SENSE => CAS_SENSE
);
SLOT_BUFFER_ENn <= '0';
end architecture;
| gpl-3.0 | 021f1e99346d7ddc328f674bf08da4f1 | 0.480795 | 3.233405 | false | false | false | false |
fpgaddicted/5bit-shift-register-structural- | prescaler_clock.vhd | 1 | 769 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity prescaler is
Port (
clk_in : in STD_LOGIC;
reset : in STD_LOGIC;
clk_out: out STD_LOGIC
);
end prescaler;
architecture Behavioral of prescaler is
signal temporal: STD_LOGIC;
signal counter : integer range 0 to 5000000 := 0;
begin
frequency_divider: process (reset, clk_in) begin
if (reset = '1') then
temporal <= '0';
counter <= 0;
elsif rising_edge(clk_in) then
if (counter = 100000) then
temporal <= NOT(temporal);
counter <= 0;
else
counter <= counter + 1;
end if;
end if;
end process;
clk_out <= temporal;
end Behavioral; | gpl-3.0 | b57861451d4b48d01d1065e6a8b7a795 | 0.538362 | 4.156757 | false | false | false | false |
markusC64/1541ultimate2 | fpga/nios_dut/nios_dut/synthesis/submodules/async_fifo_ft.vhd | 2 | 4,484 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2016, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : asynchronous fifo - Fall through mode
-------------------------------------------------------------------------------
-- Description: Asynchronous fifo for transfer of data between 2 clock domains
-- This is a simple fifo without "almost full" and count outputs.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library altera_mf;
use altera_mf.all;
entity async_fifo_ft is
generic(
g_data_width : integer := 36;
g_depth_bits : integer := 9 -- depth = 2^depth_bits (9 == 512 words)
);
port (
-- write port signals (synchronized to write clock)
wr_clock : in std_logic;
wr_reset : in std_logic;
wr_en : in std_logic;
wr_din : in std_logic_vector(g_data_width-1 downto 0);
wr_full : out std_logic;
-- read port signals (synchronized to read clock)
rd_clock : in std_logic;
rd_reset : in std_logic;
rd_next : in std_logic;
rd_dout : out std_logic_vector(g_data_width-1 downto 0);
rd_count : out unsigned(g_depth_bits downto 0);
rd_valid : out std_logic );
---------------------------------------------------------------------------
-- synthesis attributes to prevent duplication and balancing.
---------------------------------------------------------------------------
-- Xilinx attributes
attribute register_duplication : string;
attribute register_duplication of async_fifo_ft : entity is "no";
-- Altera attributes
attribute dont_replicate : boolean;
attribute dont_replicate of async_fifo_ft : entity is true;
end entity;
architecture altera of async_fifo_ft is
signal aclr : std_logic;
signal rdempty : std_logic;
signal rdusedw : std_logic_vector(g_depth_bits downto 0);
constant c_num_words : natural := 2 ** g_depth_bits;
COMPONENT dcfifo
GENERIC (
add_usedw_msb_bit : STRING;
intended_device_family : STRING;
lpm_numwords : NATURAL;
lpm_showahead : STRING;
lpm_type : STRING;
lpm_width : NATURAL;
lpm_widthu : NATURAL;
overflow_checking : STRING;
rdsync_delaypipe : NATURAL;
read_aclr_synch : STRING;
underflow_checking : STRING;
use_eab : STRING;
write_aclr_synch : STRING;
wrsync_delaypipe : NATURAL
);
PORT (
aclr : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (g_data_width-1 DOWNTO 0);
rdclk : IN STD_LOGIC ;
rdreq : IN STD_LOGIC ;
wrclk : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (g_data_width-1 DOWNTO 0);
rdempty : OUT STD_LOGIC ;
rdusedw : OUT STD_LOGIC_VECTOR(g_depth_bits DOWNTO 0);
wrfull : OUT STD_LOGIC
);
END COMPONENT;
begin
aclr <= wr_reset or rd_reset;
dcfifo_component : dcfifo
generic map (
add_usedw_msb_bit => "ON",
intended_device_family => "Cyclone IV E",
lpm_numwords => c_num_words,
lpm_showahead => "ON",
lpm_type => "dcfifo",
lpm_width => g_data_width,
lpm_widthu => g_depth_bits+1,
overflow_checking => "ON",
rdsync_delaypipe => 4,
read_aclr_synch => "ON",
underflow_checking => "ON",
use_eab => "ON",
write_aclr_synch => "ON",
wrsync_delaypipe => 4
)
port map (
aclr => aclr,
wrclk => wr_clock,
wrreq => wr_en,
data => wr_din,
wrfull => wr_full,
rdclk => rd_clock,
rdreq => rd_next,
q => rd_dout,
rdempty => rdempty,
rdusedw => rdusedw
);
rd_valid <= not rdempty;
rd_count <= unsigned(rdusedw);
end architecture;
| gpl-3.0 | 52a1506fdff27fbfd16afbe1f0708e3e | 0.464541 | 4.378906 | false | false | false | false |
chiggs/nvc | test/regress/elab25.vhd | 5 | 595 | entity sub is
port (
a : in bit_vector(2 downto 0);
b : out bit_vector(2 downto 0) );
end entity;
architecture test of sub is
begin
b <= a after 0 ns;
end architecture;
-------------------------------------------------------------------------------
entity elab25 is
end entity;
architecture test of elab25 is
signal x0, x1 : bit_vector(1 downto 0);
signal y0, y1 : bit;
begin
sub_i: entity work.sub
port map (
a(1 downto 0) => x0,
a(2) => y0,
b(1 downto 0) => x1,
b(2) => y1 );
end architecture;
| gpl-3.0 | 415c95dd9f5745addaed6547a94ef071 | 0.472269 | 3.606061 | false | true | false | false |
markusC64/1541ultimate2 | fpga/cpu_unit/mblite/hw/core/decode.vhd | 1 | 20,338 | ----------------------------------------------------------------------------------------------
--
-- Input file : decode.vhd
-- Design name : decode
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Faculty EEMCS, Department ME&CE
-- : Systems and Circuits group
--
-- Description : This combined register file and decoder uses three Dual Port
-- read after write Random Access Memory components. Every clock
-- cycle three data values can be read (ra, rb and rd) and one value
-- can be stored.
--
----------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library mblite;
use mblite.config_Pkg.all;
use mblite.core_Pkg.all;
use mblite.std_Pkg.all;
entity decode is generic
(
G_INTERRUPT : boolean := CFG_INTERRUPT;
G_USE_HW_MUL : boolean := CFG_USE_HW_MUL;
G_USE_BARREL : boolean := CFG_USE_BARREL;
G_SUPPORT_SPR: boolean := true;
g_USE_PCMP : boolean := true;
G_DEBUG : boolean := CFG_DEBUG
);
port
(
decode_o : out decode_out_type;
gprf_o : out gprf_out_type;
decode_i : in decode_in_type;
ena_i : in std_logic;
rst_i : in std_logic;
clk_i : in std_logic
);
end decode;
architecture arch of decode is
type decode_reg_type is record
instruction : std_logic_vector(CFG_IMEM_WIDTH - 1 downto 0);
program_counter : std_logic_vector(CFG_IMEM_SIZE - 1 downto 0);
immediate : std_logic_vector(15 downto 0);
is_immediate : std_logic;
interrupt : std_logic;
delay_interrupt : std_logic;
block_interrupt : std_logic;
end record;
signal r, rin : decode_out_type;
signal reg, regin : decode_reg_type;
signal wb_dat_d : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
begin
decode_o.imm <= r.imm;
decode_o.ctrl_ex <= r.ctrl_ex;
decode_o.ctrl_mem <= r.ctrl_mem;
decode_o.ctrl_wrb <= r.ctrl_wrb;
decode_o.reg_a <= r.reg_a;
decode_o.reg_b <= r.reg_b;
decode_o.hazard <= r.hazard;
decode_o.program_counter <= r.program_counter;
decode_o.fwd_dec_result <= r.fwd_dec_result;
decode_o.fwd_dec <= r.fwd_dec;
decode_o.int_ack <= r.int_ack;
decode_comb: process(decode_i,decode_i.ctrl_wrb,
decode_i.ctrl_mem_wrb,
decode_i.instruction,
decode_i.inst_valid,
decode_i.ctrl_mem_wrb.transfer_size,
r,r.ctrl_ex,r.ctrl_mem,
r.ctrl_mem.transfer_size,r.ctrl_wrb,
r.ctrl_wrb.reg_d,
r.fwd_dec,reg)
variable v : decode_out_type;
variable v_reg : decode_reg_type;
variable opcode : std_logic_vector(5 downto 0);
variable instruction : std_logic_vector(CFG_IMEM_WIDTH - 1 downto 0);
variable program_counter : std_logic_vector(CFG_IMEM_SIZE - 1 downto 0);
variable mem_result : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
begin
v := r;
v_reg := reg;
v.int_ack := '0';
-- Default register values (NOP)
v_reg.immediate := (others => '0');
v_reg.is_immediate := '0';
v_reg.program_counter := decode_i.program_counter;
v_reg.instruction := decode_i.instruction;
if decode_i.ctrl_mem_wrb.mem_read = '1' then
mem_result := align_mem_load(decode_i.mem_result, decode_i.ctrl_mem_wrb.transfer_size, decode_i.alu_result(1 downto 0));
else
mem_result := decode_i.alu_result;
end if;
wb_dat_d <= mem_result;
if G_INTERRUPT = true then
v_reg.delay_interrupt := '0';
end if;
if CFG_REG_FWD_WRB = true then
v.fwd_dec_result := mem_result;
v.fwd_dec := decode_i.ctrl_wrb;
else
v.fwd_dec_result := (others => '0');
v.fwd_dec.reg_d := (others => '0');
v.fwd_dec.reg_write := '0';
end if;
if decode_i.inst_valid = '0' then
-- set current instruction and program counter to 0
instruction := (others => '0');
program_counter := (others => '0');
-- not a hazard, just a nop
elsif (not decode_i.flush_id and r.ctrl_mem.mem_read and (compare(decode_i.instruction(20 downto 16), r.ctrl_wrb.reg_d) or compare(decode_i.instruction(15 downto 11), r.ctrl_wrb.reg_d))) = '1' then
-- A hazard occurred on register a or b
-- set current instruction and program counter to 0
instruction := (others => '0');
program_counter := (others => '0');
v.hazard := '1';
elsif CFG_MEM_FWD_WRB = false and (not decode_i.flush_id and r.ctrl_mem.mem_read and compare(decode_i.instruction(25 downto 21), r.ctrl_wrb.reg_d)) = '1' then
-- A hazard occurred on register d
-- set current instruction and program counter to 0
instruction := (others => '0');
program_counter := (others => '0');
v.hazard := '1';
elsif r.hazard = '1' then
-- Recover from hazard. Insert latched instruction
instruction := reg.instruction;
program_counter := reg.program_counter;
v.hazard := '0';
else
instruction := decode_i.instruction;
program_counter := decode_i.program_counter;
v.hazard := '0';
end if;
v.program_counter := program_counter;
opcode := instruction(31 downto 26);
v.ctrl_wrb.reg_d := instruction(25 downto 21);
v.reg_a := instruction(20 downto 16);
v.reg_b := instruction(15 downto 11);
-- SET IMM value
if reg.is_immediate = '1' then
v.imm := reg.immediate & instruction(15 downto 0);
else
v.imm := sign_extend(instruction(15 downto 0), instruction(15), 32);
end if;
-- Register if an interrupt occurs
if G_INTERRUPT = true then
if decode_i.interrupt_enable = '1' and decode_i.interrupt = '1' and reg.block_interrupt = '0' then
v_reg.interrupt := '1';
end if;
if decode_i.interrupt_enable = '0' then
v_reg.block_interrupt := '0';
end if;
end if;
v.ctrl_ex.alu_op := ALU_ADD;
v.ctrl_ex.alu_src_a := ALU_SRC_REGA;
v.ctrl_ex.alu_src_b := ALU_SRC_REGB;
v.ctrl_ex.operation := "00";
v.ctrl_ex.compare_op := '0';
v.ctrl_ex.carry := CARRY_ZERO;
v.ctrl_ex.carry_keep := CARRY_KEEP;
v.ctrl_ex.delay := '0';
v.ctrl_ex.branch_cond := NOP;
v.ctrl_ex.msr_op := NOP;
v.ctrl_mem.mem_write := '0';
v.ctrl_mem.transfer_size := WORD;
v.ctrl_mem.mem_read := '0';
v.ctrl_wrb.reg_write := '0';
if G_INTERRUPT = true and (reg.interrupt = '1' and reg.delay_interrupt = '0' and decode_i.flush_id = '0' and v.hazard = '0' and r.ctrl_ex.delay = '0' and reg.is_immediate = '0') then
-- IF an interrupt occured
-- AND the current instruction is not a branch or return instruction,
-- AND the current instruction is not in a delay slot,
-- AND this is instruction is not preceded by an IMM instruction, than handle the interrupt.
v_reg.interrupt := '0';
v_reg.block_interrupt := '1'; -- because interrupt enable is cleared in exec, we block here any new interrupts until MSR_I bit is cleared.
v.reg_a := (others => '0');
v.reg_b := (others => '0');
v.int_ack := '1';
v.imm := X"00000010";
v.ctrl_wrb.reg_d := "01110"; -- link register is r14
v.ctrl_wrb.reg_write := '1';
v.ctrl_ex.msr_op := MSR_CLR_I;
v.ctrl_ex.branch_cond := BNC;
v.ctrl_ex.alu_src_a := ALU_SRC_REGA; -- will read 0 because reg_a = 0
v.ctrl_ex.alu_src_b := ALU_SRC_IMM;
elsif (decode_i.flush_id or v.hazard) = '1' then
-- clearing these registers is not necessary, but facilitates debugging.
-- On the other hand performance improves when disabled.
if G_DEBUG = true then
v.program_counter := (others => '0');
v.ctrl_wrb.reg_d := (others => '0');
v.reg_a := (others => '0');
v.reg_b := (others => '0');
v.imm := (others => '0');
end if;
elsif is_zero(opcode(5 downto 4)) = '1' then
-- ADD, SUBTRACT OR COMPARE
-- Alu operation
v.ctrl_ex.alu_op := ALU_ADD;
-- Source operand A
if opcode(0) = '1' then
v.ctrl_ex.alu_src_a := ALU_SRC_NOT_REGA;
else
v.ctrl_ex.alu_src_a := ALU_SRC_REGA;
end if;
-- Source operand B
if opcode(3) = '1' then
v.ctrl_ex.alu_src_b := ALU_SRC_IMM;
else
v.ctrl_ex.alu_src_b := ALU_SRC_REGB;
end if;
-- Pass modifier for CMP and CMPU
if (compare(opcode, "000101") = '1') then
v.ctrl_ex.compare_op := '1';
v.ctrl_ex.operation := instruction(1 downto 0);
end if;
-- Carry
case opcode(1 downto 0) is
when "00" => v.ctrl_ex.carry := CARRY_ZERO;
when "01" => v.ctrl_ex.carry := CARRY_ONE;
when others => v.ctrl_ex.carry := CARRY_ALU;
end case;
-- Carry keep
if opcode(2) = '1' then
v.ctrl_ex.carry_keep := CARRY_KEEP;
else
v.ctrl_ex.carry_keep := CARRY_NOT_KEEP;
end if;
-- Flag writeback
v.ctrl_wrb.reg_write := '1';
elsif compare(opcode(5 downto 2), "1000") = '1' then
-- OR, AND, XOR, ANDN
-- PCMPEQ, PCMPNE
if G_USE_PCMP and instruction(10) = '1' then -- Pattern Compare
v.ctrl_ex.alu_op := ALU_PEQ;
v.ctrl_ex.operation(0) := opcode(0);
else
case opcode(1 downto 0) is
when "00" => v.ctrl_ex.alu_op := ALU_OR;
when "10" => v.ctrl_ex.alu_op := ALU_XOR;
when others => v.ctrl_ex.alu_op := ALU_AND;
end case;
end if;
if compare(opcode(1 downto 0), "11") = '1' then
v.ctrl_ex.alu_src_b := ALU_SRC_NOT_REGB;
else
v.ctrl_ex.alu_src_b := ALU_SRC_REGB;
end if;
-- Flag writeback
v.ctrl_wrb.reg_write := '1';
elsif compare(opcode(5 downto 2), "1010") = '1' then
-- ORI, ANDI, XORI, ANDNI
case opcode(1 downto 0) is
when "00" => v.ctrl_ex.alu_op := ALU_OR;
when "10" => v.ctrl_ex.alu_op := ALU_XOR;
when others => v.ctrl_ex.alu_op := ALU_AND;
end case;
if compare(opcode(1 downto 0), "11") = '1' then
v.ctrl_ex.alu_src_b := ALU_SRC_NOT_IMM;
else
v.ctrl_ex.alu_src_b := ALU_SRC_IMM;
end if;
-- Flag writeback
v.ctrl_wrb.reg_write := '1';
elsif compare(opcode, "101100") = '1' then
-- IMM instruction
v_reg.immediate := instruction(15 downto 0);
v_reg.is_immediate := '1';
elsif compare(opcode, "100100") = '1' then
-- SHIFT, SIGN EXTEND
if compare(instruction(6 downto 5), "11") = '1' then
if instruction(0) = '1' then
v.ctrl_ex.alu_op:= ALU_SEXT16;
else
v.ctrl_ex.alu_op:= ALU_SEXT8;
end if;
else
v.ctrl_ex.alu_op:= ALU_SHIFT;
v.ctrl_ex.carry_keep := CARRY_NOT_KEEP;
case instruction(6 downto 5) is
when "10" => v.ctrl_ex.carry := CARRY_ZERO;
when "01" => v.ctrl_ex.carry := CARRY_ALU;
when others => v.ctrl_ex.carry := CARRY_ARITH;
end case;
end if;
-- Flag writeback
v.ctrl_wrb.reg_write := '1';
elsif (compare(opcode, "100110") or compare(opcode, "101110")) = '1' then
-- BRANCH UNCONDITIONAL
v.ctrl_ex.branch_cond := BNC;
if opcode(3) = '1' then
v.ctrl_ex.alu_src_b := ALU_SRC_IMM;
else
v.ctrl_ex.alu_src_b := ALU_SRC_REGB;
end if;
v.ctrl_ex.delay := instruction(20);
-- Link: WRITE THE CURRENT PC TO REGISTER D. In the MEM stage, a multiplexer decides that PC is being written in case of a branch.
if instruction(18) = '1' then
-- Flag writeback
v.ctrl_wrb.reg_write := '1';
end if;
if instruction(19) = '1' then
v.ctrl_ex.alu_src_a := ALU_SRC_REGA;
v.reg_a := (others => '0'); -- select register 0 to emulate 0.
else
v.ctrl_ex.alu_src_a := ALU_SRC_PC;
end if;
if G_INTERRUPT = true then
v_reg.delay_interrupt := '1';
end if;
elsif (compare(opcode, "100111") or compare(opcode, "101111")) = '1' then
-- BRANCH CONDITIONAL
v.ctrl_ex.alu_op := ALU_ADD;
v.ctrl_ex.alu_src_a := ALU_SRC_PC;
if opcode(3) = '1' then
v.ctrl_ex.alu_src_b := ALU_SRC_IMM;
else
v.ctrl_ex.alu_src_b := ALU_SRC_REGB;
end if;
case v.ctrl_wrb.reg_d(2 downto 0) is
when "000" => v.ctrl_ex.branch_cond := BEQ;
when "001" => v.ctrl_ex.branch_cond := BNE;
when "010" => v.ctrl_ex.branch_cond := BLT;
when "011" => v.ctrl_ex.branch_cond := BLE;
when "100" => v.ctrl_ex.branch_cond := BGT;
when others => v.ctrl_ex.branch_cond := BGE;
end case;
if G_INTERRUPT = true then
v_reg.delay_interrupt := '1';
end if;
v.ctrl_ex.delay := v.ctrl_wrb.reg_d(4);
elsif compare(opcode, "101101") = '1' then
-- RETURN
v.ctrl_ex.branch_cond := BNC;
v.ctrl_ex.alu_src_b := ALU_SRC_IMM;
v.ctrl_ex.delay := '1';
if G_INTERRUPT = true then
if v.ctrl_wrb.reg_d(0) = '1' then
v.ctrl_ex.msr_op := MSR_SET_I;
end if;
v_reg.delay_interrupt := '1';
end if;
elsif compare(opcode(5 downto 4), "11") = '1' then
-- SW, LW
v.ctrl_ex.alu_op := ALU_ADD;
v.ctrl_ex.alu_src_a := ALU_SRC_REGA;
if opcode(3) = '1' then
v.ctrl_ex.alu_src_b := ALU_SRC_IMM;
else
v.ctrl_ex.alu_src_b := ALU_SRC_REGB;
end if;
v.ctrl_ex.carry := CARRY_ZERO;
if opcode(2) = '1' then
-- Store
v.ctrl_mem.mem_write := '1';
v.ctrl_mem.mem_read := '0';
v.ctrl_wrb.reg_write := '0';
else
-- Load
v.ctrl_mem.mem_write := '0';
v.ctrl_mem.mem_read := '1';
v.ctrl_wrb.reg_write := '1';
end if;
case opcode(1 downto 0) is
when "00" => v.ctrl_mem.transfer_size := BYTE;
when "01" => v.ctrl_mem.transfer_size := HALFWORD;
when others => v.ctrl_mem.transfer_size := WORD;
end case;
v.ctrl_ex.delay := '0';
elsif G_USE_HW_MUL = true and (compare(opcode, "010000") or compare(opcode, "011000")) = '1' then
v.ctrl_ex.alu_op := ALU_MUL;
if opcode(3) = '1' then
v.ctrl_ex.alu_src_b := ALU_SRC_IMM;
else
v.ctrl_ex.alu_src_b := ALU_SRC_REGB;
end if;
v.ctrl_wrb.reg_write := '1';
elsif G_USE_BARREL = true and (compare(opcode, "010001") or compare(opcode, "011001")) = '1' then
v.ctrl_ex.alu_op := ALU_BS;
if opcode(3) = '1' then
v.ctrl_ex.alu_src_b := ALU_SRC_IMM;
else
v.ctrl_ex.alu_src_b := ALU_SRC_REGB;
end if;
v.ctrl_wrb.reg_write := '1';
elsif G_SUPPORT_SPR and opcode = "100101" then
if instruction(15 downto 14) = "11" then -- MTS, SPR[Sd] := Ra
v.ctrl_ex.msr_op := LOAD_MSR; -- Ra will be written to the status bits
elsif instruction(15 downto 14) = "10" then -- MFS, Rd := SPR[Sd]
v.ctrl_wrb.reg_write := '1';
v.ctrl_ex.alu_src_a := ALU_SRC_SPR;
v.ctrl_ex.alu_op := ALU_SEXT16; -- does not use B
else -- 00 (MSRSET/MSRCLR) and 01 -> illegal
v.ctrl_ex.alu_src_a := ALU_SRC_SPR;
v.ctrl_ex.alu_op := ALU_SEXT16; -- does not use B
v.ctrl_wrb.reg_write := '1';
if instruction(16)='0' then -- SET
v.ctrl_ex.msr_op := MSR_SET;
else -- CLR
v.ctrl_ex.msr_op := MSR_CLR;
end if;
end if;
else
-- UNKNOWN OPCODE
null;
end if;
rin <= v;
regin <= v_reg;
end process;
decode_seq: process(clk_i)
procedure proc_reset_decode is
begin
r.reg_a <= (others => '0');
r.reg_b <= (others => '0');
r.imm <= (others => '0');
r.program_counter <= (others => '0');
r.hazard <= '0';
r.ctrl_ex.alu_op <= ALU_ADD;
r.ctrl_ex.alu_src_a <= ALU_SRC_REGA;
r.ctrl_ex.alu_src_b <= ALU_SRC_REGB;
r.ctrl_ex.operation <= "00";
r.ctrl_ex.compare_op <= '0';
r.ctrl_ex.carry <= CARRY_ZERO;
r.ctrl_ex.carry_keep <= CARRY_NOT_KEEP;
r.ctrl_ex.delay <= '0';
r.ctrl_ex.branch_cond <= NOP;
r.ctrl_mem.mem_write <= '0';
r.ctrl_mem.transfer_size <= WORD;
r.ctrl_mem.mem_read <= '0';
r.ctrl_wrb.reg_d <= (others => '0');
r.ctrl_wrb.reg_write <= '0';
r.fwd_dec_result <= (others => '0');
r.fwd_dec.reg_d <= (others => '0');
r.fwd_dec.reg_write <= '0';
reg.instruction <= (others => '0');
reg.program_counter <= (others => '0');
reg.immediate <= (others => '0');
reg.is_immediate <= '0';
reg.interrupt <= '0';
reg.delay_interrupt <= '0';
reg.block_interrupt <= '0';
end procedure proc_reset_decode;
begin
if rising_edge(clk_i) then
if rst_i = '1' then
proc_reset_decode;
elsif ena_i = '1' then
r <= rin;
reg <= regin;
end if;
end if;
end process;
gprf0 : gprf port map
(
gprf_o => gprf_o,
gprf_i.adr_a_i => rin.reg_a,
gprf_i.adr_b_i => rin.reg_b,
gprf_i.adr_d_i => rin.ctrl_wrb.reg_d,
gprf_i.dat_w_i => wb_dat_d,
gprf_i.adr_w_i => decode_i.ctrl_wrb.reg_d,
gprf_i.wre_i => decode_i.ctrl_wrb.reg_write,
ena_i => ena_i,
clk_i => clk_i
);
end arch;
| gpl-3.0 | ab715a62f5b83988533082fe47aa1a29 | 0.471334 | 3.593921 | false | false | false | false |
markusC64/1541ultimate2 | fpga/nios_dut/nios_dut/synthesis/nios_dut.vhd | 1 | 107,147 | -- nios_dut.vhd
-- Generated using ACDS version 15.1 185
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nios_dut is
port (
audio_in_data : in std_logic_vector(31 downto 0) := (others => '0'); -- audio_in.data
audio_in_valid : in std_logic := '0'; -- .valid
audio_in_ready : out std_logic; -- .ready
audio_out_data : out std_logic_vector(31 downto 0); -- audio_out.data
audio_out_valid : out std_logic; -- .valid
audio_out_ready : in std_logic := '0'; -- .ready
dummy_export : in std_logic := '0'; -- dummy.export
io_ack : in std_logic := '0'; -- io.ack
io_rdata : in std_logic_vector(7 downto 0) := (others => '0'); -- .rdata
io_read : out std_logic; -- .read
io_wdata : out std_logic_vector(7 downto 0); -- .wdata
io_write : out std_logic; -- .write
io_address : out std_logic_vector(19 downto 0); -- .address
io_irq : in std_logic := '0'; -- .irq
io_u2p_ack : in std_logic := '0'; -- io_u2p.ack
io_u2p_rdata : in std_logic_vector(7 downto 0) := (others => '0'); -- .rdata
io_u2p_read : out std_logic; -- .read
io_u2p_wdata : out std_logic_vector(7 downto 0); -- .wdata
io_u2p_write : out std_logic; -- .write
io_u2p_address : out std_logic_vector(19 downto 0); -- .address
io_u2p_irq : in std_logic := '0'; -- .irq
jtag_io_input_vector : in std_logic_vector(47 downto 0) := (others => '0'); -- jtag_io.input_vector
jtag_io_output_vector : out std_logic_vector(7 downto 0); -- .output_vector
jtag_test_clocks_clock_1 : in std_logic := '0'; -- jtag_test_clocks.clock_1
jtag_test_clocks_clock_2 : in std_logic := '0'; -- .clock_2
mem_mem_req_address : out std_logic_vector(25 downto 0); -- mem.mem_req_address
mem_mem_req_byte_en : out std_logic_vector(3 downto 0); -- .mem_req_byte_en
mem_mem_req_read_writen : out std_logic; -- .mem_req_read_writen
mem_mem_req_request : out std_logic; -- .mem_req_request
mem_mem_req_tag : out std_logic_vector(7 downto 0); -- .mem_req_tag
mem_mem_req_wdata : out std_logic_vector(31 downto 0); -- .mem_req_wdata
mem_mem_resp_dack_tag : in std_logic_vector(7 downto 0) := (others => '0'); -- .mem_resp_dack_tag
mem_mem_resp_data : in std_logic_vector(31 downto 0) := (others => '0'); -- .mem_resp_data
mem_mem_resp_rack_tag : in std_logic_vector(7 downto 0) := (others => '0'); -- .mem_resp_rack_tag
pio1_export : in std_logic_vector(31 downto 0) := (others => '0'); -- pio1.export
pio2_export : in std_logic_vector(19 downto 0) := (others => '0'); -- pio2.export
pio3_export : out std_logic_vector(7 downto 0); -- pio3.export
sys_clock_clk : in std_logic := '0'; -- sys_clock.clk
sys_reset_reset_n : in std_logic := '0'; -- sys_reset.reset_n
uart_rxd : in std_logic := '0'; -- uart.rxd
uart_txd : out std_logic; -- .txd
uart_cts_n : in std_logic := '0'; -- .cts_n
uart_rts_n : out std_logic -- .rts_n
);
end entity nios_dut;
architecture rtl of nios_dut is
component nios_dut_audio_in_dma is
port (
mm_write_address : out std_logic_vector(25 downto 0); -- address
mm_write_write : out std_logic; -- write
mm_write_byteenable : out std_logic_vector(3 downto 0); -- byteenable
mm_write_writedata : out std_logic_vector(31 downto 0); -- writedata
mm_write_waitrequest : in std_logic := 'X'; -- waitrequest
clock_clk : in std_logic := 'X'; -- clk
reset_n_reset_n : in std_logic := 'X'; -- reset_n
csr_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
csr_write : in std_logic := 'X'; -- write
csr_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
csr_readdata : out std_logic_vector(31 downto 0); -- readdata
csr_read : in std_logic := 'X'; -- read
csr_address : in std_logic_vector(2 downto 0) := (others => 'X'); -- address
descriptor_slave_write : in std_logic := 'X'; -- write
descriptor_slave_waitrequest : out std_logic; -- waitrequest
descriptor_slave_writedata : in std_logic_vector(127 downto 0) := (others => 'X'); -- writedata
descriptor_slave_byteenable : in std_logic_vector(15 downto 0) := (others => 'X'); -- byteenable
csr_irq_irq : out std_logic; -- irq
st_sink_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- data
st_sink_valid : in std_logic := 'X'; -- valid
st_sink_ready : out std_logic -- ready
);
end component nios_dut_audio_in_dma;
component nios_dut_audio_out_dma is
port (
mm_read_address : out std_logic_vector(25 downto 0); -- address
mm_read_read : out std_logic; -- read
mm_read_byteenable : out std_logic_vector(3 downto 0); -- byteenable
mm_read_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
mm_read_waitrequest : in std_logic := 'X'; -- waitrequest
mm_read_readdatavalid : in std_logic := 'X'; -- readdatavalid
clock_clk : in std_logic := 'X'; -- clk
reset_n_reset_n : in std_logic := 'X'; -- reset_n
csr_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
csr_write : in std_logic := 'X'; -- write
csr_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
csr_readdata : out std_logic_vector(31 downto 0); -- readdata
csr_read : in std_logic := 'X'; -- read
csr_address : in std_logic_vector(2 downto 0) := (others => 'X'); -- address
descriptor_slave_write : in std_logic := 'X'; -- write
descriptor_slave_waitrequest : out std_logic; -- waitrequest
descriptor_slave_writedata : in std_logic_vector(127 downto 0) := (others => 'X'); -- writedata
descriptor_slave_byteenable : in std_logic_vector(15 downto 0) := (others => 'X'); -- byteenable
csr_irq_irq : out std_logic; -- irq
st_source_data : out std_logic_vector(31 downto 0); -- data
st_source_valid : out std_logic; -- valid
st_source_ready : in std_logic := 'X' -- ready
);
end component nios_dut_audio_out_dma;
component avalon_to_mem32_bridge is
generic (
g_tag : std_logic_vector(7 downto 0) := "01011011"
);
port (
reset : in std_logic := 'X'; -- reset
avs_read : in std_logic := 'X'; -- read
avs_write : in std_logic := 'X'; -- write
avs_address : in std_logic_vector(25 downto 0) := (others => 'X'); -- address
avs_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
avs_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
avs_waitrequest : out std_logic; -- waitrequest
avs_readdata : out std_logic_vector(31 downto 0); -- readdata
avs_readdatavalid : out std_logic; -- readdatavalid
clock : in std_logic := 'X'; -- clk
mem_req_address : out std_logic_vector(25 downto 0); -- mem_req_address
mem_req_byte_en : out std_logic_vector(3 downto 0); -- mem_req_byte_en
mem_req_read_writen : out std_logic; -- mem_req_read_writen
mem_req_request : out std_logic; -- mem_req_request
mem_req_tag : out std_logic_vector(7 downto 0); -- mem_req_tag
mem_req_wdata : out std_logic_vector(31 downto 0); -- mem_req_wdata
mem_resp_dack_tag : in std_logic_vector(7 downto 0) := (others => 'X'); -- mem_resp_dack_tag
mem_resp_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- mem_resp_data
mem_resp_rack_tag : in std_logic_vector(7 downto 0) := (others => 'X') -- mem_resp_rack_tag
);
end component avalon_to_mem32_bridge;
component avalon_to_io_bridge is
port (
reset : in std_logic := 'X'; -- reset
avs_read : in std_logic := 'X'; -- read
avs_write : in std_logic := 'X'; -- write
avs_address : in std_logic_vector(19 downto 0) := (others => 'X'); -- address
avs_writedata : in std_logic_vector(7 downto 0) := (others => 'X'); -- writedata
avs_ready : out std_logic; -- waitrequest_n
avs_readdata : out std_logic_vector(7 downto 0); -- readdata
avs_readdatavalid : out std_logic; -- readdatavalid
clock : in std_logic := 'X'; -- clk
io_ack : in std_logic := 'X'; -- ack
io_rdata : in std_logic_vector(7 downto 0) := (others => 'X'); -- rdata
io_read : out std_logic; -- read
io_wdata : out std_logic_vector(7 downto 0); -- wdata
io_write : out std_logic; -- write
io_address : out std_logic_vector(19 downto 0); -- address
io_irq : in std_logic := 'X'; -- irq
avs_irq : out std_logic -- irq
);
end component avalon_to_io_bridge;
component jtag_client is
port (
avm_clock : in std_logic := 'X'; -- clk
avm_reset : in std_logic := 'X'; -- reset
sample_vector : in std_logic_vector(47 downto 0) := (others => 'X'); -- input_vector
write_vector : out std_logic_vector(7 downto 0); -- output_vector
avm_read : out std_logic; -- read
avm_write : out std_logic; -- write
avm_byteenable : out std_logic_vector(3 downto 0); -- byteenable
avm_address : out std_logic_vector(31 downto 0); -- address
avm_writedata : out std_logic_vector(31 downto 0); -- writedata
avm_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
avm_readdatavalid : in std_logic := 'X'; -- readdatavalid
avm_waitrequest : in std_logic := 'X'; -- waitrequest
clock_1 : in std_logic := 'X'; -- clock_1
clock_2 : in std_logic := 'X' -- clock_2
);
end component jtag_client;
component nios_dut_nios2_gen2_0 is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
reset_req : in std_logic := 'X'; -- reset_req
d_address : out std_logic_vector(31 downto 0); -- address
d_byteenable : out std_logic_vector(3 downto 0); -- byteenable
d_read : out std_logic; -- read
d_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
d_waitrequest : in std_logic := 'X'; -- waitrequest
d_write : out std_logic; -- write
d_writedata : out std_logic_vector(31 downto 0); -- writedata
debug_mem_slave_debugaccess_to_roms : out std_logic; -- debugaccess
i_address : out std_logic_vector(29 downto 0); -- address
i_read : out std_logic; -- read
i_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
i_waitrequest : in std_logic := 'X'; -- waitrequest
irq : in std_logic_vector(31 downto 0) := (others => 'X'); -- irq
debug_reset_request : out std_logic; -- reset
debug_mem_slave_address : in std_logic_vector(8 downto 0) := (others => 'X'); -- address
debug_mem_slave_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
debug_mem_slave_debugaccess : in std_logic := 'X'; -- debugaccess
debug_mem_slave_read : in std_logic := 'X'; -- read
debug_mem_slave_readdata : out std_logic_vector(31 downto 0); -- readdata
debug_mem_slave_waitrequest : out std_logic; -- waitrequest
debug_mem_slave_write : in std_logic := 'X'; -- write
debug_mem_slave_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
dummy_ci_port : out std_logic -- readra
);
end component nios_dut_nios2_gen2_0;
component nios_dut_onchip_memory2_0 is
port (
clk : in std_logic := 'X'; -- clk
address : in std_logic_vector(10 downto 0) := (others => 'X'); -- address
clken : in std_logic := 'X'; -- clken
chipselect : in std_logic := 'X'; -- chipselect
write : in std_logic := 'X'; -- write
readdata : out std_logic_vector(31 downto 0); -- readdata
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
reset : in std_logic := 'X'; -- reset
reset_req : in std_logic := 'X' -- reset_req
);
end component nios_dut_onchip_memory2_0;
component nios_dut_pio_0 is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
write_n : in std_logic := 'X'; -- write_n
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
chipselect : in std_logic := 'X'; -- chipselect
readdata : out std_logic_vector(31 downto 0); -- readdata
in_port : in std_logic := 'X'; -- export
irq : out std_logic -- irq
);
end component nios_dut_pio_0;
component nios_dut_pio_1 is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
address : in std_logic_vector(2 downto 0) := (others => 'X'); -- address
readdata : out std_logic_vector(31 downto 0); -- readdata
in_port : in std_logic_vector(31 downto 0) := (others => 'X') -- export
);
end component nios_dut_pio_1;
component nios_dut_pio_2 is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
readdata : out std_logic_vector(31 downto 0); -- readdata
in_port : in std_logic_vector(19 downto 0) := (others => 'X') -- export
);
end component nios_dut_pio_2;
component nios_dut_pio_3 is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
address : in std_logic_vector(2 downto 0) := (others => 'X'); -- address
write_n : in std_logic := 'X'; -- write_n
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
chipselect : in std_logic := 'X'; -- chipselect
readdata : out std_logic_vector(31 downto 0); -- readdata
out_port : out std_logic_vector(7 downto 0) -- export
);
end component nios_dut_pio_3;
component nios_dut_uart_0 is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
address : in std_logic_vector(2 downto 0) := (others => 'X'); -- address
begintransfer : in std_logic := 'X'; -- begintransfer
chipselect : in std_logic := 'X'; -- chipselect
read_n : in std_logic := 'X'; -- read_n
write_n : in std_logic := 'X'; -- write_n
writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
readdata : out std_logic_vector(15 downto 0); -- readdata
dataavailable : out std_logic; -- dataavailable
readyfordata : out std_logic; -- readyfordata
rxd : in std_logic := 'X'; -- export
txd : out std_logic; -- export
cts_n : in std_logic := 'X'; -- export
rts_n : out std_logic; -- export
irq : out std_logic -- irq
);
end component nios_dut_uart_0;
component nios_dut_mm_interconnect_0 is
port (
clk_0_clk_clk : in std_logic := 'X'; -- clk
jtag_dut_0_reset_reset_bridge_in_reset_reset : in std_logic := 'X'; -- reset
audio_in_dma_mm_write_address : in std_logic_vector(25 downto 0) := (others => 'X'); -- address
audio_in_dma_mm_write_waitrequest : out std_logic; -- waitrequest
audio_in_dma_mm_write_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
audio_in_dma_mm_write_write : in std_logic := 'X'; -- write
audio_in_dma_mm_write_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
audio_out_dma_mm_read_address : in std_logic_vector(25 downto 0) := (others => 'X'); -- address
audio_out_dma_mm_read_waitrequest : out std_logic; -- waitrequest
audio_out_dma_mm_read_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
audio_out_dma_mm_read_read : in std_logic := 'X'; -- read
audio_out_dma_mm_read_readdata : out std_logic_vector(31 downto 0); -- readdata
audio_out_dma_mm_read_readdatavalid : out std_logic; -- readdatavalid
jtag_dut_0_avalon_master_address : in std_logic_vector(31 downto 0) := (others => 'X'); -- address
jtag_dut_0_avalon_master_waitrequest : out std_logic; -- waitrequest
jtag_dut_0_avalon_master_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
jtag_dut_0_avalon_master_read : in std_logic := 'X'; -- read
jtag_dut_0_avalon_master_readdata : out std_logic_vector(31 downto 0); -- readdata
jtag_dut_0_avalon_master_readdatavalid : out std_logic; -- readdatavalid
jtag_dut_0_avalon_master_write : in std_logic := 'X'; -- write
jtag_dut_0_avalon_master_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
nios2_gen2_0_data_master_address : in std_logic_vector(31 downto 0) := (others => 'X'); -- address
nios2_gen2_0_data_master_waitrequest : out std_logic; -- waitrequest
nios2_gen2_0_data_master_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
nios2_gen2_0_data_master_read : in std_logic := 'X'; -- read
nios2_gen2_0_data_master_readdata : out std_logic_vector(31 downto 0); -- readdata
nios2_gen2_0_data_master_write : in std_logic := 'X'; -- write
nios2_gen2_0_data_master_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
nios2_gen2_0_data_master_debugaccess : in std_logic := 'X'; -- debugaccess
nios2_gen2_0_instruction_master_address : in std_logic_vector(29 downto 0) := (others => 'X'); -- address
nios2_gen2_0_instruction_master_waitrequest : out std_logic; -- waitrequest
nios2_gen2_0_instruction_master_read : in std_logic := 'X'; -- read
nios2_gen2_0_instruction_master_readdata : out std_logic_vector(31 downto 0); -- readdata
audio_in_dma_csr_address : out std_logic_vector(2 downto 0); -- address
audio_in_dma_csr_write : out std_logic; -- write
audio_in_dma_csr_read : out std_logic; -- read
audio_in_dma_csr_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
audio_in_dma_csr_writedata : out std_logic_vector(31 downto 0); -- writedata
audio_in_dma_csr_byteenable : out std_logic_vector(3 downto 0); -- byteenable
audio_in_dma_descriptor_slave_write : out std_logic; -- write
audio_in_dma_descriptor_slave_writedata : out std_logic_vector(127 downto 0); -- writedata
audio_in_dma_descriptor_slave_byteenable : out std_logic_vector(15 downto 0); -- byteenable
audio_in_dma_descriptor_slave_waitrequest : in std_logic := 'X'; -- waitrequest
audio_out_dma_csr_address : out std_logic_vector(2 downto 0); -- address
audio_out_dma_csr_write : out std_logic; -- write
audio_out_dma_csr_read : out std_logic; -- read
audio_out_dma_csr_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
audio_out_dma_csr_writedata : out std_logic_vector(31 downto 0); -- writedata
audio_out_dma_csr_byteenable : out std_logic_vector(3 downto 0); -- byteenable
audio_out_dma_descriptor_slave_write : out std_logic; -- write
audio_out_dma_descriptor_slave_writedata : out std_logic_vector(127 downto 0); -- writedata
audio_out_dma_descriptor_slave_byteenable : out std_logic_vector(15 downto 0); -- byteenable
audio_out_dma_descriptor_slave_waitrequest : in std_logic := 'X'; -- waitrequest
avalon2mem_0_avalon_slave_0_address : out std_logic_vector(25 downto 0); -- address
avalon2mem_0_avalon_slave_0_write : out std_logic; -- write
avalon2mem_0_avalon_slave_0_read : out std_logic; -- read
avalon2mem_0_avalon_slave_0_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
avalon2mem_0_avalon_slave_0_writedata : out std_logic_vector(31 downto 0); -- writedata
avalon2mem_0_avalon_slave_0_byteenable : out std_logic_vector(3 downto 0); -- byteenable
avalon2mem_0_avalon_slave_0_readdatavalid : in std_logic := 'X'; -- readdatavalid
avalon2mem_0_avalon_slave_0_waitrequest : in std_logic := 'X'; -- waitrequest
io_bridge_0_avalon_slave_0_address : out std_logic_vector(19 downto 0); -- address
io_bridge_0_avalon_slave_0_write : out std_logic; -- write
io_bridge_0_avalon_slave_0_read : out std_logic; -- read
io_bridge_0_avalon_slave_0_readdata : in std_logic_vector(7 downto 0) := (others => 'X'); -- readdata
io_bridge_0_avalon_slave_0_writedata : out std_logic_vector(7 downto 0); -- writedata
io_bridge_0_avalon_slave_0_readdatavalid : in std_logic := 'X'; -- readdatavalid
io_bridge_0_avalon_slave_0_waitrequest : in std_logic := 'X'; -- waitrequest
io_bridge_1_avalon_slave_0_address : out std_logic_vector(19 downto 0); -- address
io_bridge_1_avalon_slave_0_write : out std_logic; -- write
io_bridge_1_avalon_slave_0_read : out std_logic; -- read
io_bridge_1_avalon_slave_0_readdata : in std_logic_vector(7 downto 0) := (others => 'X'); -- readdata
io_bridge_1_avalon_slave_0_writedata : out std_logic_vector(7 downto 0); -- writedata
io_bridge_1_avalon_slave_0_readdatavalid : in std_logic := 'X'; -- readdatavalid
io_bridge_1_avalon_slave_0_waitrequest : in std_logic := 'X'; -- waitrequest
nios2_gen2_0_debug_mem_slave_address : out std_logic_vector(8 downto 0); -- address
nios2_gen2_0_debug_mem_slave_write : out std_logic; -- write
nios2_gen2_0_debug_mem_slave_read : out std_logic; -- read
nios2_gen2_0_debug_mem_slave_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
nios2_gen2_0_debug_mem_slave_writedata : out std_logic_vector(31 downto 0); -- writedata
nios2_gen2_0_debug_mem_slave_byteenable : out std_logic_vector(3 downto 0); -- byteenable
nios2_gen2_0_debug_mem_slave_waitrequest : in std_logic := 'X'; -- waitrequest
nios2_gen2_0_debug_mem_slave_debugaccess : out std_logic; -- debugaccess
onchip_memory2_0_s1_address : out std_logic_vector(10 downto 0); -- address
onchip_memory2_0_s1_write : out std_logic; -- write
onchip_memory2_0_s1_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
onchip_memory2_0_s1_writedata : out std_logic_vector(31 downto 0); -- writedata
onchip_memory2_0_s1_byteenable : out std_logic_vector(3 downto 0); -- byteenable
onchip_memory2_0_s1_chipselect : out std_logic; -- chipselect
onchip_memory2_0_s1_clken : out std_logic; -- clken
pio_0_s1_address : out std_logic_vector(1 downto 0); -- address
pio_0_s1_write : out std_logic; -- write
pio_0_s1_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
pio_0_s1_writedata : out std_logic_vector(31 downto 0); -- writedata
pio_0_s1_chipselect : out std_logic; -- chipselect
pio_1_s1_address : out std_logic_vector(2 downto 0); -- address
pio_1_s1_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
pio_2_s1_address : out std_logic_vector(1 downto 0); -- address
pio_2_s1_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
pio_3_s1_address : out std_logic_vector(2 downto 0); -- address
pio_3_s1_write : out std_logic; -- write
pio_3_s1_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
pio_3_s1_writedata : out std_logic_vector(31 downto 0); -- writedata
pio_3_s1_chipselect : out std_logic; -- chipselect
uart_0_s1_address : out std_logic_vector(2 downto 0); -- address
uart_0_s1_write : out std_logic; -- write
uart_0_s1_read : out std_logic; -- read
uart_0_s1_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata
uart_0_s1_writedata : out std_logic_vector(15 downto 0); -- writedata
uart_0_s1_begintransfer : out std_logic; -- begintransfer
uart_0_s1_chipselect : out std_logic -- chipselect
);
end component nios_dut_mm_interconnect_0;
component nios_dut_irq_mapper is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
receiver0_irq : in std_logic := 'X'; -- irq
receiver1_irq : in std_logic := 'X'; -- irq
receiver2_irq : in std_logic := 'X'; -- irq
receiver3_irq : in std_logic := 'X'; -- irq
receiver4_irq : in std_logic := 'X'; -- irq
receiver5_irq : in std_logic := 'X'; -- irq
sender_irq : out std_logic_vector(31 downto 0) -- irq
);
end component nios_dut_irq_mapper;
component altera_reset_controller is
generic (
NUM_RESET_INPUTS : integer := 6;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 0;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := 'X'; -- reset
clk : in std_logic := 'X'; -- clk
reset_out : out std_logic; -- reset
reset_req : out std_logic; -- reset_req
reset_req_in0 : in std_logic := 'X'; -- reset_req
reset_in1 : in std_logic := 'X'; -- reset
reset_req_in1 : in std_logic := 'X'; -- reset_req
reset_in2 : in std_logic := 'X'; -- reset
reset_req_in2 : in std_logic := 'X'; -- reset_req
reset_in3 : in std_logic := 'X'; -- reset
reset_req_in3 : in std_logic := 'X'; -- reset_req
reset_in4 : in std_logic := 'X'; -- reset
reset_req_in4 : in std_logic := 'X'; -- reset_req
reset_in5 : in std_logic := 'X'; -- reset
reset_req_in5 : in std_logic := 'X'; -- reset_req
reset_in6 : in std_logic := 'X'; -- reset
reset_req_in6 : in std_logic := 'X'; -- reset_req
reset_in7 : in std_logic := 'X'; -- reset
reset_req_in7 : in std_logic := 'X'; -- reset_req
reset_in8 : in std_logic := 'X'; -- reset
reset_req_in8 : in std_logic := 'X'; -- reset_req
reset_in9 : in std_logic := 'X'; -- reset
reset_req_in9 : in std_logic := 'X'; -- reset_req
reset_in10 : in std_logic := 'X'; -- reset
reset_req_in10 : in std_logic := 'X'; -- reset_req
reset_in11 : in std_logic := 'X'; -- reset
reset_req_in11 : in std_logic := 'X'; -- reset_req
reset_in12 : in std_logic := 'X'; -- reset
reset_req_in12 : in std_logic := 'X'; -- reset_req
reset_in13 : in std_logic := 'X'; -- reset
reset_req_in13 : in std_logic := 'X'; -- reset_req
reset_in14 : in std_logic := 'X'; -- reset
reset_req_in14 : in std_logic := 'X'; -- reset_req
reset_in15 : in std_logic := 'X'; -- reset
reset_req_in15 : in std_logic := 'X' -- reset_req
);
end component altera_reset_controller;
signal jtag_dut_0_avalon_master_readdata : std_logic_vector(31 downto 0); -- mm_interconnect_0:jtag_dut_0_avalon_master_readdata -> jtag_dut_0:avm_readdata
signal jtag_dut_0_avalon_master_waitrequest : std_logic; -- mm_interconnect_0:jtag_dut_0_avalon_master_waitrequest -> jtag_dut_0:avm_waitrequest
signal jtag_dut_0_avalon_master_read : std_logic; -- jtag_dut_0:avm_read -> mm_interconnect_0:jtag_dut_0_avalon_master_read
signal jtag_dut_0_avalon_master_byteenable : std_logic_vector(3 downto 0); -- jtag_dut_0:avm_byteenable -> mm_interconnect_0:jtag_dut_0_avalon_master_byteenable
signal jtag_dut_0_avalon_master_address : std_logic_vector(31 downto 0); -- jtag_dut_0:avm_address -> mm_interconnect_0:jtag_dut_0_avalon_master_address
signal jtag_dut_0_avalon_master_readdatavalid : std_logic; -- mm_interconnect_0:jtag_dut_0_avalon_master_readdatavalid -> jtag_dut_0:avm_readdatavalid
signal jtag_dut_0_avalon_master_write : std_logic; -- jtag_dut_0:avm_write -> mm_interconnect_0:jtag_dut_0_avalon_master_write
signal jtag_dut_0_avalon_master_writedata : std_logic_vector(31 downto 0); -- jtag_dut_0:avm_writedata -> mm_interconnect_0:jtag_dut_0_avalon_master_writedata
signal nios2_gen2_0_data_master_readdata : std_logic_vector(31 downto 0); -- mm_interconnect_0:nios2_gen2_0_data_master_readdata -> nios2_gen2_0:d_readdata
signal nios2_gen2_0_data_master_waitrequest : std_logic; -- mm_interconnect_0:nios2_gen2_0_data_master_waitrequest -> nios2_gen2_0:d_waitrequest
signal nios2_gen2_0_data_master_debugaccess : std_logic; -- nios2_gen2_0:debug_mem_slave_debugaccess_to_roms -> mm_interconnect_0:nios2_gen2_0_data_master_debugaccess
signal nios2_gen2_0_data_master_address : std_logic_vector(31 downto 0); -- nios2_gen2_0:d_address -> mm_interconnect_0:nios2_gen2_0_data_master_address
signal nios2_gen2_0_data_master_byteenable : std_logic_vector(3 downto 0); -- nios2_gen2_0:d_byteenable -> mm_interconnect_0:nios2_gen2_0_data_master_byteenable
signal nios2_gen2_0_data_master_read : std_logic; -- nios2_gen2_0:d_read -> mm_interconnect_0:nios2_gen2_0_data_master_read
signal nios2_gen2_0_data_master_write : std_logic; -- nios2_gen2_0:d_write -> mm_interconnect_0:nios2_gen2_0_data_master_write
signal nios2_gen2_0_data_master_writedata : std_logic_vector(31 downto 0); -- nios2_gen2_0:d_writedata -> mm_interconnect_0:nios2_gen2_0_data_master_writedata
signal nios2_gen2_0_instruction_master_readdata : std_logic_vector(31 downto 0); -- mm_interconnect_0:nios2_gen2_0_instruction_master_readdata -> nios2_gen2_0:i_readdata
signal nios2_gen2_0_instruction_master_waitrequest : std_logic; -- mm_interconnect_0:nios2_gen2_0_instruction_master_waitrequest -> nios2_gen2_0:i_waitrequest
signal nios2_gen2_0_instruction_master_address : std_logic_vector(29 downto 0); -- nios2_gen2_0:i_address -> mm_interconnect_0:nios2_gen2_0_instruction_master_address
signal nios2_gen2_0_instruction_master_read : std_logic; -- nios2_gen2_0:i_read -> mm_interconnect_0:nios2_gen2_0_instruction_master_read
signal audio_out_dma_mm_read_readdata : std_logic_vector(31 downto 0); -- mm_interconnect_0:audio_out_dma_mm_read_readdata -> audio_out_dma:mm_read_readdata
signal audio_out_dma_mm_read_waitrequest : std_logic; -- mm_interconnect_0:audio_out_dma_mm_read_waitrequest -> audio_out_dma:mm_read_waitrequest
signal audio_out_dma_mm_read_address : std_logic_vector(25 downto 0); -- audio_out_dma:mm_read_address -> mm_interconnect_0:audio_out_dma_mm_read_address
signal audio_out_dma_mm_read_read : std_logic; -- audio_out_dma:mm_read_read -> mm_interconnect_0:audio_out_dma_mm_read_read
signal audio_out_dma_mm_read_byteenable : std_logic_vector(3 downto 0); -- audio_out_dma:mm_read_byteenable -> mm_interconnect_0:audio_out_dma_mm_read_byteenable
signal audio_out_dma_mm_read_readdatavalid : std_logic; -- mm_interconnect_0:audio_out_dma_mm_read_readdatavalid -> audio_out_dma:mm_read_readdatavalid
signal audio_in_dma_mm_write_waitrequest : std_logic; -- mm_interconnect_0:audio_in_dma_mm_write_waitrequest -> audio_in_dma:mm_write_waitrequest
signal audio_in_dma_mm_write_address : std_logic_vector(25 downto 0); -- audio_in_dma:mm_write_address -> mm_interconnect_0:audio_in_dma_mm_write_address
signal audio_in_dma_mm_write_byteenable : std_logic_vector(3 downto 0); -- audio_in_dma:mm_write_byteenable -> mm_interconnect_0:audio_in_dma_mm_write_byteenable
signal audio_in_dma_mm_write_write : std_logic; -- audio_in_dma:mm_write_write -> mm_interconnect_0:audio_in_dma_mm_write_write
signal audio_in_dma_mm_write_writedata : std_logic_vector(31 downto 0); -- audio_in_dma:mm_write_writedata -> mm_interconnect_0:audio_in_dma_mm_write_writedata
signal mm_interconnect_0_avalon2mem_0_avalon_slave_0_readdata : std_logic_vector(31 downto 0); -- avalon2mem_0:avs_readdata -> mm_interconnect_0:avalon2mem_0_avalon_slave_0_readdata
signal mm_interconnect_0_avalon2mem_0_avalon_slave_0_waitrequest : std_logic; -- avalon2mem_0:avs_waitrequest -> mm_interconnect_0:avalon2mem_0_avalon_slave_0_waitrequest
signal mm_interconnect_0_avalon2mem_0_avalon_slave_0_address : std_logic_vector(25 downto 0); -- mm_interconnect_0:avalon2mem_0_avalon_slave_0_address -> avalon2mem_0:avs_address
signal mm_interconnect_0_avalon2mem_0_avalon_slave_0_read : std_logic; -- mm_interconnect_0:avalon2mem_0_avalon_slave_0_read -> avalon2mem_0:avs_read
signal mm_interconnect_0_avalon2mem_0_avalon_slave_0_byteenable : std_logic_vector(3 downto 0); -- mm_interconnect_0:avalon2mem_0_avalon_slave_0_byteenable -> avalon2mem_0:avs_byteenable
signal mm_interconnect_0_avalon2mem_0_avalon_slave_0_readdatavalid : std_logic; -- avalon2mem_0:avs_readdatavalid -> mm_interconnect_0:avalon2mem_0_avalon_slave_0_readdatavalid
signal mm_interconnect_0_avalon2mem_0_avalon_slave_0_write : std_logic; -- mm_interconnect_0:avalon2mem_0_avalon_slave_0_write -> avalon2mem_0:avs_write
signal mm_interconnect_0_avalon2mem_0_avalon_slave_0_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:avalon2mem_0_avalon_slave_0_writedata -> avalon2mem_0:avs_writedata
signal mm_interconnect_0_onchip_memory2_0_s1_chipselect : std_logic; -- mm_interconnect_0:onchip_memory2_0_s1_chipselect -> onchip_memory2_0:chipselect
signal mm_interconnect_0_onchip_memory2_0_s1_readdata : std_logic_vector(31 downto 0); -- onchip_memory2_0:readdata -> mm_interconnect_0:onchip_memory2_0_s1_readdata
signal mm_interconnect_0_onchip_memory2_0_s1_address : std_logic_vector(10 downto 0); -- mm_interconnect_0:onchip_memory2_0_s1_address -> onchip_memory2_0:address
signal mm_interconnect_0_onchip_memory2_0_s1_byteenable : std_logic_vector(3 downto 0); -- mm_interconnect_0:onchip_memory2_0_s1_byteenable -> onchip_memory2_0:byteenable
signal mm_interconnect_0_onchip_memory2_0_s1_write : std_logic; -- mm_interconnect_0:onchip_memory2_0_s1_write -> onchip_memory2_0:write
signal mm_interconnect_0_onchip_memory2_0_s1_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:onchip_memory2_0_s1_writedata -> onchip_memory2_0:writedata
signal mm_interconnect_0_onchip_memory2_0_s1_clken : std_logic; -- mm_interconnect_0:onchip_memory2_0_s1_clken -> onchip_memory2_0:clken
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata : std_logic_vector(31 downto 0); -- nios2_gen2_0:debug_mem_slave_readdata -> mm_interconnect_0:nios2_gen2_0_debug_mem_slave_readdata
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest : std_logic; -- nios2_gen2_0:debug_mem_slave_waitrequest -> mm_interconnect_0:nios2_gen2_0_debug_mem_slave_waitrequest
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess : std_logic; -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_debugaccess -> nios2_gen2_0:debug_mem_slave_debugaccess
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address : std_logic_vector(8 downto 0); -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_address -> nios2_gen2_0:debug_mem_slave_address
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read : std_logic; -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_read -> nios2_gen2_0:debug_mem_slave_read
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable : std_logic_vector(3 downto 0); -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_byteenable -> nios2_gen2_0:debug_mem_slave_byteenable
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write : std_logic; -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_write -> nios2_gen2_0:debug_mem_slave_write
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_writedata -> nios2_gen2_0:debug_mem_slave_writedata
signal mm_interconnect_0_io_bridge_1_avalon_slave_0_readdata : std_logic_vector(7 downto 0); -- io_bridge_1:avs_readdata -> mm_interconnect_0:io_bridge_1_avalon_slave_0_readdata
signal io_bridge_1_avalon_slave_0_waitrequest : std_logic; -- io_bridge_1:avs_ready -> io_bridge_1_avalon_slave_0_waitrequest:in
signal mm_interconnect_0_io_bridge_1_avalon_slave_0_address : std_logic_vector(19 downto 0); -- mm_interconnect_0:io_bridge_1_avalon_slave_0_address -> io_bridge_1:avs_address
signal mm_interconnect_0_io_bridge_1_avalon_slave_0_read : std_logic; -- mm_interconnect_0:io_bridge_1_avalon_slave_0_read -> io_bridge_1:avs_read
signal mm_interconnect_0_io_bridge_1_avalon_slave_0_readdatavalid : std_logic; -- io_bridge_1:avs_readdatavalid -> mm_interconnect_0:io_bridge_1_avalon_slave_0_readdatavalid
signal mm_interconnect_0_io_bridge_1_avalon_slave_0_write : std_logic; -- mm_interconnect_0:io_bridge_1_avalon_slave_0_write -> io_bridge_1:avs_write
signal mm_interconnect_0_io_bridge_1_avalon_slave_0_writedata : std_logic_vector(7 downto 0); -- mm_interconnect_0:io_bridge_1_avalon_slave_0_writedata -> io_bridge_1:avs_writedata
signal mm_interconnect_0_io_bridge_0_avalon_slave_0_readdata : std_logic_vector(7 downto 0); -- io_bridge_0:avs_readdata -> mm_interconnect_0:io_bridge_0_avalon_slave_0_readdata
signal io_bridge_0_avalon_slave_0_waitrequest : std_logic; -- io_bridge_0:avs_ready -> io_bridge_0_avalon_slave_0_waitrequest:in
signal mm_interconnect_0_io_bridge_0_avalon_slave_0_address : std_logic_vector(19 downto 0); -- mm_interconnect_0:io_bridge_0_avalon_slave_0_address -> io_bridge_0:avs_address
signal mm_interconnect_0_io_bridge_0_avalon_slave_0_read : std_logic; -- mm_interconnect_0:io_bridge_0_avalon_slave_0_read -> io_bridge_0:avs_read
signal mm_interconnect_0_io_bridge_0_avalon_slave_0_readdatavalid : std_logic; -- io_bridge_0:avs_readdatavalid -> mm_interconnect_0:io_bridge_0_avalon_slave_0_readdatavalid
signal mm_interconnect_0_io_bridge_0_avalon_slave_0_write : std_logic; -- mm_interconnect_0:io_bridge_0_avalon_slave_0_write -> io_bridge_0:avs_write
signal mm_interconnect_0_io_bridge_0_avalon_slave_0_writedata : std_logic_vector(7 downto 0); -- mm_interconnect_0:io_bridge_0_avalon_slave_0_writedata -> io_bridge_0:avs_writedata
signal mm_interconnect_0_audio_out_dma_csr_readdata : std_logic_vector(31 downto 0); -- audio_out_dma:csr_readdata -> mm_interconnect_0:audio_out_dma_csr_readdata
signal mm_interconnect_0_audio_out_dma_csr_address : std_logic_vector(2 downto 0); -- mm_interconnect_0:audio_out_dma_csr_address -> audio_out_dma:csr_address
signal mm_interconnect_0_audio_out_dma_csr_read : std_logic; -- mm_interconnect_0:audio_out_dma_csr_read -> audio_out_dma:csr_read
signal mm_interconnect_0_audio_out_dma_csr_byteenable : std_logic_vector(3 downto 0); -- mm_interconnect_0:audio_out_dma_csr_byteenable -> audio_out_dma:csr_byteenable
signal mm_interconnect_0_audio_out_dma_csr_write : std_logic; -- mm_interconnect_0:audio_out_dma_csr_write -> audio_out_dma:csr_write
signal mm_interconnect_0_audio_out_dma_csr_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:audio_out_dma_csr_writedata -> audio_out_dma:csr_writedata
signal mm_interconnect_0_audio_in_dma_csr_readdata : std_logic_vector(31 downto 0); -- audio_in_dma:csr_readdata -> mm_interconnect_0:audio_in_dma_csr_readdata
signal mm_interconnect_0_audio_in_dma_csr_address : std_logic_vector(2 downto 0); -- mm_interconnect_0:audio_in_dma_csr_address -> audio_in_dma:csr_address
signal mm_interconnect_0_audio_in_dma_csr_read : std_logic; -- mm_interconnect_0:audio_in_dma_csr_read -> audio_in_dma:csr_read
signal mm_interconnect_0_audio_in_dma_csr_byteenable : std_logic_vector(3 downto 0); -- mm_interconnect_0:audio_in_dma_csr_byteenable -> audio_in_dma:csr_byteenable
signal mm_interconnect_0_audio_in_dma_csr_write : std_logic; -- mm_interconnect_0:audio_in_dma_csr_write -> audio_in_dma:csr_write
signal mm_interconnect_0_audio_in_dma_csr_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:audio_in_dma_csr_writedata -> audio_in_dma:csr_writedata
signal mm_interconnect_0_audio_out_dma_descriptor_slave_waitrequest : std_logic; -- audio_out_dma:descriptor_slave_waitrequest -> mm_interconnect_0:audio_out_dma_descriptor_slave_waitrequest
signal mm_interconnect_0_audio_out_dma_descriptor_slave_byteenable : std_logic_vector(15 downto 0); -- mm_interconnect_0:audio_out_dma_descriptor_slave_byteenable -> audio_out_dma:descriptor_slave_byteenable
signal mm_interconnect_0_audio_out_dma_descriptor_slave_write : std_logic; -- mm_interconnect_0:audio_out_dma_descriptor_slave_write -> audio_out_dma:descriptor_slave_write
signal mm_interconnect_0_audio_out_dma_descriptor_slave_writedata : std_logic_vector(127 downto 0); -- mm_interconnect_0:audio_out_dma_descriptor_slave_writedata -> audio_out_dma:descriptor_slave_writedata
signal mm_interconnect_0_audio_in_dma_descriptor_slave_waitrequest : std_logic; -- audio_in_dma:descriptor_slave_waitrequest -> mm_interconnect_0:audio_in_dma_descriptor_slave_waitrequest
signal mm_interconnect_0_audio_in_dma_descriptor_slave_byteenable : std_logic_vector(15 downto 0); -- mm_interconnect_0:audio_in_dma_descriptor_slave_byteenable -> audio_in_dma:descriptor_slave_byteenable
signal mm_interconnect_0_audio_in_dma_descriptor_slave_write : std_logic; -- mm_interconnect_0:audio_in_dma_descriptor_slave_write -> audio_in_dma:descriptor_slave_write
signal mm_interconnect_0_audio_in_dma_descriptor_slave_writedata : std_logic_vector(127 downto 0); -- mm_interconnect_0:audio_in_dma_descriptor_slave_writedata -> audio_in_dma:descriptor_slave_writedata
signal mm_interconnect_0_pio_0_s1_chipselect : std_logic; -- mm_interconnect_0:pio_0_s1_chipselect -> pio_0:chipselect
signal mm_interconnect_0_pio_0_s1_readdata : std_logic_vector(31 downto 0); -- pio_0:readdata -> mm_interconnect_0:pio_0_s1_readdata
signal mm_interconnect_0_pio_0_s1_address : std_logic_vector(1 downto 0); -- mm_interconnect_0:pio_0_s1_address -> pio_0:address
signal mm_interconnect_0_pio_0_s1_write : std_logic; -- mm_interconnect_0:pio_0_s1_write -> mm_interconnect_0_pio_0_s1_write:in
signal mm_interconnect_0_pio_0_s1_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:pio_0_s1_writedata -> pio_0:writedata
signal mm_interconnect_0_uart_0_s1_chipselect : std_logic; -- mm_interconnect_0:uart_0_s1_chipselect -> uart_0:chipselect
signal mm_interconnect_0_uart_0_s1_readdata : std_logic_vector(15 downto 0); -- uart_0:readdata -> mm_interconnect_0:uart_0_s1_readdata
signal mm_interconnect_0_uart_0_s1_address : std_logic_vector(2 downto 0); -- mm_interconnect_0:uart_0_s1_address -> uart_0:address
signal mm_interconnect_0_uart_0_s1_read : std_logic; -- mm_interconnect_0:uart_0_s1_read -> mm_interconnect_0_uart_0_s1_read:in
signal mm_interconnect_0_uart_0_s1_begintransfer : std_logic; -- mm_interconnect_0:uart_0_s1_begintransfer -> uart_0:begintransfer
signal mm_interconnect_0_uart_0_s1_write : std_logic; -- mm_interconnect_0:uart_0_s1_write -> mm_interconnect_0_uart_0_s1_write:in
signal mm_interconnect_0_uart_0_s1_writedata : std_logic_vector(15 downto 0); -- mm_interconnect_0:uart_0_s1_writedata -> uart_0:writedata
signal mm_interconnect_0_pio_1_s1_readdata : std_logic_vector(31 downto 0); -- pio_1:readdata -> mm_interconnect_0:pio_1_s1_readdata
signal mm_interconnect_0_pio_1_s1_address : std_logic_vector(2 downto 0); -- mm_interconnect_0:pio_1_s1_address -> pio_1:address
signal mm_interconnect_0_pio_2_s1_readdata : std_logic_vector(31 downto 0); -- pio_2:readdata -> mm_interconnect_0:pio_2_s1_readdata
signal mm_interconnect_0_pio_2_s1_address : std_logic_vector(1 downto 0); -- mm_interconnect_0:pio_2_s1_address -> pio_2:address
signal mm_interconnect_0_pio_3_s1_chipselect : std_logic; -- mm_interconnect_0:pio_3_s1_chipselect -> pio_3:chipselect
signal mm_interconnect_0_pio_3_s1_readdata : std_logic_vector(31 downto 0); -- pio_3:readdata -> mm_interconnect_0:pio_3_s1_readdata
signal mm_interconnect_0_pio_3_s1_address : std_logic_vector(2 downto 0); -- mm_interconnect_0:pio_3_s1_address -> pio_3:address
signal mm_interconnect_0_pio_3_s1_write : std_logic; -- mm_interconnect_0:pio_3_s1_write -> mm_interconnect_0_pio_3_s1_write:in
signal mm_interconnect_0_pio_3_s1_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:pio_3_s1_writedata -> pio_3:writedata
signal irq_mapper_receiver0_irq : std_logic; -- audio_out_dma:csr_irq_irq -> irq_mapper:receiver0_irq
signal irq_mapper_receiver1_irq : std_logic; -- audio_in_dma:csr_irq_irq -> irq_mapper:receiver1_irq
signal irq_mapper_receiver2_irq : std_logic; -- io_bridge_1:avs_irq -> irq_mapper:receiver2_irq
signal irq_mapper_receiver3_irq : std_logic; -- pio_0:irq -> irq_mapper:receiver3_irq
signal irq_mapper_receiver4_irq : std_logic; -- uart_0:irq -> irq_mapper:receiver4_irq
signal irq_mapper_receiver5_irq : std_logic; -- io_bridge_0:avs_irq -> irq_mapper:receiver5_irq
signal nios2_gen2_0_irq_irq : std_logic_vector(31 downto 0); -- irq_mapper:sender_irq -> nios2_gen2_0:irq
signal rst_controller_reset_out_reset : std_logic; -- rst_controller:reset_out -> [avalon2mem_0:reset, io_bridge_0:reset, io_bridge_1:reset, irq_mapper:reset, jtag_dut_0:avm_reset, mm_interconnect_0:jtag_dut_0_reset_reset_bridge_in_reset_reset, onchip_memory2_0:reset, rst_controller_reset_out_reset:in, rst_translator:in_reset]
signal rst_controller_reset_out_reset_req : std_logic; -- rst_controller:reset_req -> [nios2_gen2_0:reset_req, onchip_memory2_0:reset_req, rst_translator:reset_req_in]
signal sys_reset_reset_n_ports_inv : std_logic; -- sys_reset_reset_n:inv -> rst_controller:reset_in0
signal mm_interconnect_0_io_bridge_1_avalon_slave_0_inv : std_logic; -- io_bridge_1_avalon_slave_0_waitrequest:inv -> mm_interconnect_0:io_bridge_1_avalon_slave_0_waitrequest
signal mm_interconnect_0_io_bridge_0_avalon_slave_0_inv : std_logic; -- io_bridge_0_avalon_slave_0_waitrequest:inv -> mm_interconnect_0:io_bridge_0_avalon_slave_0_waitrequest
signal mm_interconnect_0_pio_0_s1_write_ports_inv : std_logic; -- mm_interconnect_0_pio_0_s1_write:inv -> pio_0:write_n
signal mm_interconnect_0_uart_0_s1_read_ports_inv : std_logic; -- mm_interconnect_0_uart_0_s1_read:inv -> uart_0:read_n
signal mm_interconnect_0_uart_0_s1_write_ports_inv : std_logic; -- mm_interconnect_0_uart_0_s1_write:inv -> uart_0:write_n
signal mm_interconnect_0_pio_3_s1_write_ports_inv : std_logic; -- mm_interconnect_0_pio_3_s1_write:inv -> pio_3:write_n
signal rst_controller_reset_out_reset_ports_inv : std_logic; -- rst_controller_reset_out_reset:inv -> [audio_in_dma:reset_n_reset_n, audio_out_dma:reset_n_reset_n, nios2_gen2_0:reset_n, pio_0:reset_n, pio_1:reset_n, pio_2:reset_n, pio_3:reset_n, uart_0:reset_n]
begin
audio_in_dma : component nios_dut_audio_in_dma
port map (
mm_write_address => audio_in_dma_mm_write_address, -- mm_write.address
mm_write_write => audio_in_dma_mm_write_write, -- .write
mm_write_byteenable => audio_in_dma_mm_write_byteenable, -- .byteenable
mm_write_writedata => audio_in_dma_mm_write_writedata, -- .writedata
mm_write_waitrequest => audio_in_dma_mm_write_waitrequest, -- .waitrequest
clock_clk => sys_clock_clk, -- clock.clk
reset_n_reset_n => rst_controller_reset_out_reset_ports_inv, -- reset_n.reset_n
csr_writedata => mm_interconnect_0_audio_in_dma_csr_writedata, -- csr.writedata
csr_write => mm_interconnect_0_audio_in_dma_csr_write, -- .write
csr_byteenable => mm_interconnect_0_audio_in_dma_csr_byteenable, -- .byteenable
csr_readdata => mm_interconnect_0_audio_in_dma_csr_readdata, -- .readdata
csr_read => mm_interconnect_0_audio_in_dma_csr_read, -- .read
csr_address => mm_interconnect_0_audio_in_dma_csr_address, -- .address
descriptor_slave_write => mm_interconnect_0_audio_in_dma_descriptor_slave_write, -- descriptor_slave.write
descriptor_slave_waitrequest => mm_interconnect_0_audio_in_dma_descriptor_slave_waitrequest, -- .waitrequest
descriptor_slave_writedata => mm_interconnect_0_audio_in_dma_descriptor_slave_writedata, -- .writedata
descriptor_slave_byteenable => mm_interconnect_0_audio_in_dma_descriptor_slave_byteenable, -- .byteenable
csr_irq_irq => irq_mapper_receiver1_irq, -- csr_irq.irq
st_sink_data => audio_in_data, -- st_sink.data
st_sink_valid => audio_in_valid, -- .valid
st_sink_ready => audio_in_ready -- .ready
);
audio_out_dma : component nios_dut_audio_out_dma
port map (
mm_read_address => audio_out_dma_mm_read_address, -- mm_read.address
mm_read_read => audio_out_dma_mm_read_read, -- .read
mm_read_byteenable => audio_out_dma_mm_read_byteenable, -- .byteenable
mm_read_readdata => audio_out_dma_mm_read_readdata, -- .readdata
mm_read_waitrequest => audio_out_dma_mm_read_waitrequest, -- .waitrequest
mm_read_readdatavalid => audio_out_dma_mm_read_readdatavalid, -- .readdatavalid
clock_clk => sys_clock_clk, -- clock.clk
reset_n_reset_n => rst_controller_reset_out_reset_ports_inv, -- reset_n.reset_n
csr_writedata => mm_interconnect_0_audio_out_dma_csr_writedata, -- csr.writedata
csr_write => mm_interconnect_0_audio_out_dma_csr_write, -- .write
csr_byteenable => mm_interconnect_0_audio_out_dma_csr_byteenable, -- .byteenable
csr_readdata => mm_interconnect_0_audio_out_dma_csr_readdata, -- .readdata
csr_read => mm_interconnect_0_audio_out_dma_csr_read, -- .read
csr_address => mm_interconnect_0_audio_out_dma_csr_address, -- .address
descriptor_slave_write => mm_interconnect_0_audio_out_dma_descriptor_slave_write, -- descriptor_slave.write
descriptor_slave_waitrequest => mm_interconnect_0_audio_out_dma_descriptor_slave_waitrequest, -- .waitrequest
descriptor_slave_writedata => mm_interconnect_0_audio_out_dma_descriptor_slave_writedata, -- .writedata
descriptor_slave_byteenable => mm_interconnect_0_audio_out_dma_descriptor_slave_byteenable, -- .byteenable
csr_irq_irq => irq_mapper_receiver0_irq, -- csr_irq.irq
st_source_data => audio_out_data, -- st_source.data
st_source_valid => audio_out_valid, -- .valid
st_source_ready => audio_out_ready -- .ready
);
avalon2mem_0 : component avalon_to_mem32_bridge
generic map (
g_tag => "01011011"
)
port map (
reset => rst_controller_reset_out_reset, -- reset.reset
avs_read => mm_interconnect_0_avalon2mem_0_avalon_slave_0_read, -- avalon_slave_0.read
avs_write => mm_interconnect_0_avalon2mem_0_avalon_slave_0_write, -- .write
avs_address => mm_interconnect_0_avalon2mem_0_avalon_slave_0_address, -- .address
avs_writedata => mm_interconnect_0_avalon2mem_0_avalon_slave_0_writedata, -- .writedata
avs_byteenable => mm_interconnect_0_avalon2mem_0_avalon_slave_0_byteenable, -- .byteenable
avs_waitrequest => mm_interconnect_0_avalon2mem_0_avalon_slave_0_waitrequest, -- .waitrequest
avs_readdata => mm_interconnect_0_avalon2mem_0_avalon_slave_0_readdata, -- .readdata
avs_readdatavalid => mm_interconnect_0_avalon2mem_0_avalon_slave_0_readdatavalid, -- .readdatavalid
clock => sys_clock_clk, -- clock.clk
mem_req_address => mem_mem_req_address, -- mem.mem_req_address
mem_req_byte_en => mem_mem_req_byte_en, -- .mem_req_byte_en
mem_req_read_writen => mem_mem_req_read_writen, -- .mem_req_read_writen
mem_req_request => mem_mem_req_request, -- .mem_req_request
mem_req_tag => mem_mem_req_tag, -- .mem_req_tag
mem_req_wdata => mem_mem_req_wdata, -- .mem_req_wdata
mem_resp_dack_tag => mem_mem_resp_dack_tag, -- .mem_resp_dack_tag
mem_resp_data => mem_mem_resp_data, -- .mem_resp_data
mem_resp_rack_tag => mem_mem_resp_rack_tag -- .mem_resp_rack_tag
);
io_bridge_0 : component avalon_to_io_bridge
port map (
reset => rst_controller_reset_out_reset, -- reset.reset
avs_read => mm_interconnect_0_io_bridge_0_avalon_slave_0_read, -- avalon_slave_0.read
avs_write => mm_interconnect_0_io_bridge_0_avalon_slave_0_write, -- .write
avs_address => mm_interconnect_0_io_bridge_0_avalon_slave_0_address, -- .address
avs_writedata => mm_interconnect_0_io_bridge_0_avalon_slave_0_writedata, -- .writedata
avs_ready => io_bridge_0_avalon_slave_0_waitrequest, -- .waitrequest_n
avs_readdata => mm_interconnect_0_io_bridge_0_avalon_slave_0_readdata, -- .readdata
avs_readdatavalid => mm_interconnect_0_io_bridge_0_avalon_slave_0_readdatavalid, -- .readdatavalid
clock => sys_clock_clk, -- clock.clk
io_ack => io_ack, -- io.ack
io_rdata => io_rdata, -- .rdata
io_read => io_read, -- .read
io_wdata => io_wdata, -- .wdata
io_write => io_write, -- .write
io_address => io_address, -- .address
io_irq => io_irq, -- .irq
avs_irq => irq_mapper_receiver5_irq -- irq.irq
);
io_bridge_1 : component avalon_to_io_bridge
port map (
reset => rst_controller_reset_out_reset, -- reset.reset
avs_read => mm_interconnect_0_io_bridge_1_avalon_slave_0_read, -- avalon_slave_0.read
avs_write => mm_interconnect_0_io_bridge_1_avalon_slave_0_write, -- .write
avs_address => mm_interconnect_0_io_bridge_1_avalon_slave_0_address, -- .address
avs_writedata => mm_interconnect_0_io_bridge_1_avalon_slave_0_writedata, -- .writedata
avs_ready => io_bridge_1_avalon_slave_0_waitrequest, -- .waitrequest_n
avs_readdata => mm_interconnect_0_io_bridge_1_avalon_slave_0_readdata, -- .readdata
avs_readdatavalid => mm_interconnect_0_io_bridge_1_avalon_slave_0_readdatavalid, -- .readdatavalid
clock => sys_clock_clk, -- clock.clk
io_ack => io_u2p_ack, -- io.ack
io_rdata => io_u2p_rdata, -- .rdata
io_read => io_u2p_read, -- .read
io_wdata => io_u2p_wdata, -- .wdata
io_write => io_u2p_write, -- .write
io_address => io_u2p_address, -- .address
io_irq => io_u2p_irq, -- .irq
avs_irq => irq_mapper_receiver2_irq -- irq.irq
);
jtag_dut_0 : component jtag_client
port map (
avm_clock => sys_clock_clk, -- clock.clk
avm_reset => rst_controller_reset_out_reset, -- reset.reset
sample_vector => jtag_io_input_vector, -- io.input_vector
write_vector => jtag_io_output_vector, -- .output_vector
avm_read => jtag_dut_0_avalon_master_read, -- avalon_master.read
avm_write => jtag_dut_0_avalon_master_write, -- .write
avm_byteenable => jtag_dut_0_avalon_master_byteenable, -- .byteenable
avm_address => jtag_dut_0_avalon_master_address, -- .address
avm_writedata => jtag_dut_0_avalon_master_writedata, -- .writedata
avm_readdata => jtag_dut_0_avalon_master_readdata, -- .readdata
avm_readdatavalid => jtag_dut_0_avalon_master_readdatavalid, -- .readdatavalid
avm_waitrequest => jtag_dut_0_avalon_master_waitrequest, -- .waitrequest
clock_1 => jtag_test_clocks_clock_1, -- test_clocks.clock_1
clock_2 => jtag_test_clocks_clock_2 -- .clock_2
);
nios2_gen2_0 : component nios_dut_nios2_gen2_0
port map (
clk => sys_clock_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
reset_req => rst_controller_reset_out_reset_req, -- .reset_req
d_address => nios2_gen2_0_data_master_address, -- data_master.address
d_byteenable => nios2_gen2_0_data_master_byteenable, -- .byteenable
d_read => nios2_gen2_0_data_master_read, -- .read
d_readdata => nios2_gen2_0_data_master_readdata, -- .readdata
d_waitrequest => nios2_gen2_0_data_master_waitrequest, -- .waitrequest
d_write => nios2_gen2_0_data_master_write, -- .write
d_writedata => nios2_gen2_0_data_master_writedata, -- .writedata
debug_mem_slave_debugaccess_to_roms => nios2_gen2_0_data_master_debugaccess, -- .debugaccess
i_address => nios2_gen2_0_instruction_master_address, -- instruction_master.address
i_read => nios2_gen2_0_instruction_master_read, -- .read
i_readdata => nios2_gen2_0_instruction_master_readdata, -- .readdata
i_waitrequest => nios2_gen2_0_instruction_master_waitrequest, -- .waitrequest
irq => nios2_gen2_0_irq_irq, -- irq.irq
debug_reset_request => open, -- debug_reset_request.reset
debug_mem_slave_address => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address, -- debug_mem_slave.address
debug_mem_slave_byteenable => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable, -- .byteenable
debug_mem_slave_debugaccess => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess, -- .debugaccess
debug_mem_slave_read => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read, -- .read
debug_mem_slave_readdata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata, -- .readdata
debug_mem_slave_waitrequest => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest, -- .waitrequest
debug_mem_slave_write => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write, -- .write
debug_mem_slave_writedata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata, -- .writedata
dummy_ci_port => open -- custom_instruction_master.readra
);
onchip_memory2_0 : component nios_dut_onchip_memory2_0
port map (
clk => sys_clock_clk, -- clk1.clk
address => mm_interconnect_0_onchip_memory2_0_s1_address, -- s1.address
clken => mm_interconnect_0_onchip_memory2_0_s1_clken, -- .clken
chipselect => mm_interconnect_0_onchip_memory2_0_s1_chipselect, -- .chipselect
write => mm_interconnect_0_onchip_memory2_0_s1_write, -- .write
readdata => mm_interconnect_0_onchip_memory2_0_s1_readdata, -- .readdata
writedata => mm_interconnect_0_onchip_memory2_0_s1_writedata, -- .writedata
byteenable => mm_interconnect_0_onchip_memory2_0_s1_byteenable, -- .byteenable
reset => rst_controller_reset_out_reset, -- reset1.reset
reset_req => rst_controller_reset_out_reset_req -- .reset_req
);
pio_0 : component nios_dut_pio_0
port map (
clk => sys_clock_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
address => mm_interconnect_0_pio_0_s1_address, -- s1.address
write_n => mm_interconnect_0_pio_0_s1_write_ports_inv, -- .write_n
writedata => mm_interconnect_0_pio_0_s1_writedata, -- .writedata
chipselect => mm_interconnect_0_pio_0_s1_chipselect, -- .chipselect
readdata => mm_interconnect_0_pio_0_s1_readdata, -- .readdata
in_port => dummy_export, -- external_connection.export
irq => irq_mapper_receiver3_irq -- irq.irq
);
pio_1 : component nios_dut_pio_1
port map (
clk => sys_clock_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
address => mm_interconnect_0_pio_1_s1_address, -- s1.address
readdata => mm_interconnect_0_pio_1_s1_readdata, -- .readdata
in_port => pio1_export -- external_connection.export
);
pio_2 : component nios_dut_pio_2
port map (
clk => sys_clock_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
address => mm_interconnect_0_pio_2_s1_address, -- s1.address
readdata => mm_interconnect_0_pio_2_s1_readdata, -- .readdata
in_port => pio2_export -- external_connection.export
);
pio_3 : component nios_dut_pio_3
port map (
clk => sys_clock_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
address => mm_interconnect_0_pio_3_s1_address, -- s1.address
write_n => mm_interconnect_0_pio_3_s1_write_ports_inv, -- .write_n
writedata => mm_interconnect_0_pio_3_s1_writedata, -- .writedata
chipselect => mm_interconnect_0_pio_3_s1_chipselect, -- .chipselect
readdata => mm_interconnect_0_pio_3_s1_readdata, -- .readdata
out_port => pio3_export -- external_connection.export
);
uart_0 : component nios_dut_uart_0
port map (
clk => sys_clock_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
address => mm_interconnect_0_uart_0_s1_address, -- s1.address
begintransfer => mm_interconnect_0_uart_0_s1_begintransfer, -- .begintransfer
chipselect => mm_interconnect_0_uart_0_s1_chipselect, -- .chipselect
read_n => mm_interconnect_0_uart_0_s1_read_ports_inv, -- .read_n
write_n => mm_interconnect_0_uart_0_s1_write_ports_inv, -- .write_n
writedata => mm_interconnect_0_uart_0_s1_writedata, -- .writedata
readdata => mm_interconnect_0_uart_0_s1_readdata, -- .readdata
dataavailable => open, -- .dataavailable
readyfordata => open, -- .readyfordata
rxd => uart_rxd, -- external_connection.export
txd => uart_txd, -- .export
cts_n => uart_cts_n, -- .export
rts_n => uart_rts_n, -- .export
irq => irq_mapper_receiver4_irq -- irq.irq
);
mm_interconnect_0 : component nios_dut_mm_interconnect_0
port map (
clk_0_clk_clk => sys_clock_clk, -- clk_0_clk.clk
jtag_dut_0_reset_reset_bridge_in_reset_reset => rst_controller_reset_out_reset, -- jtag_dut_0_reset_reset_bridge_in_reset.reset
audio_in_dma_mm_write_address => audio_in_dma_mm_write_address, -- audio_in_dma_mm_write.address
audio_in_dma_mm_write_waitrequest => audio_in_dma_mm_write_waitrequest, -- .waitrequest
audio_in_dma_mm_write_byteenable => audio_in_dma_mm_write_byteenable, -- .byteenable
audio_in_dma_mm_write_write => audio_in_dma_mm_write_write, -- .write
audio_in_dma_mm_write_writedata => audio_in_dma_mm_write_writedata, -- .writedata
audio_out_dma_mm_read_address => audio_out_dma_mm_read_address, -- audio_out_dma_mm_read.address
audio_out_dma_mm_read_waitrequest => audio_out_dma_mm_read_waitrequest, -- .waitrequest
audio_out_dma_mm_read_byteenable => audio_out_dma_mm_read_byteenable, -- .byteenable
audio_out_dma_mm_read_read => audio_out_dma_mm_read_read, -- .read
audio_out_dma_mm_read_readdata => audio_out_dma_mm_read_readdata, -- .readdata
audio_out_dma_mm_read_readdatavalid => audio_out_dma_mm_read_readdatavalid, -- .readdatavalid
jtag_dut_0_avalon_master_address => jtag_dut_0_avalon_master_address, -- jtag_dut_0_avalon_master.address
jtag_dut_0_avalon_master_waitrequest => jtag_dut_0_avalon_master_waitrequest, -- .waitrequest
jtag_dut_0_avalon_master_byteenable => jtag_dut_0_avalon_master_byteenable, -- .byteenable
jtag_dut_0_avalon_master_read => jtag_dut_0_avalon_master_read, -- .read
jtag_dut_0_avalon_master_readdata => jtag_dut_0_avalon_master_readdata, -- .readdata
jtag_dut_0_avalon_master_readdatavalid => jtag_dut_0_avalon_master_readdatavalid, -- .readdatavalid
jtag_dut_0_avalon_master_write => jtag_dut_0_avalon_master_write, -- .write
jtag_dut_0_avalon_master_writedata => jtag_dut_0_avalon_master_writedata, -- .writedata
nios2_gen2_0_data_master_address => nios2_gen2_0_data_master_address, -- nios2_gen2_0_data_master.address
nios2_gen2_0_data_master_waitrequest => nios2_gen2_0_data_master_waitrequest, -- .waitrequest
nios2_gen2_0_data_master_byteenable => nios2_gen2_0_data_master_byteenable, -- .byteenable
nios2_gen2_0_data_master_read => nios2_gen2_0_data_master_read, -- .read
nios2_gen2_0_data_master_readdata => nios2_gen2_0_data_master_readdata, -- .readdata
nios2_gen2_0_data_master_write => nios2_gen2_0_data_master_write, -- .write
nios2_gen2_0_data_master_writedata => nios2_gen2_0_data_master_writedata, -- .writedata
nios2_gen2_0_data_master_debugaccess => nios2_gen2_0_data_master_debugaccess, -- .debugaccess
nios2_gen2_0_instruction_master_address => nios2_gen2_0_instruction_master_address, -- nios2_gen2_0_instruction_master.address
nios2_gen2_0_instruction_master_waitrequest => nios2_gen2_0_instruction_master_waitrequest, -- .waitrequest
nios2_gen2_0_instruction_master_read => nios2_gen2_0_instruction_master_read, -- .read
nios2_gen2_0_instruction_master_readdata => nios2_gen2_0_instruction_master_readdata, -- .readdata
audio_in_dma_csr_address => mm_interconnect_0_audio_in_dma_csr_address, -- audio_in_dma_csr.address
audio_in_dma_csr_write => mm_interconnect_0_audio_in_dma_csr_write, -- .write
audio_in_dma_csr_read => mm_interconnect_0_audio_in_dma_csr_read, -- .read
audio_in_dma_csr_readdata => mm_interconnect_0_audio_in_dma_csr_readdata, -- .readdata
audio_in_dma_csr_writedata => mm_interconnect_0_audio_in_dma_csr_writedata, -- .writedata
audio_in_dma_csr_byteenable => mm_interconnect_0_audio_in_dma_csr_byteenable, -- .byteenable
audio_in_dma_descriptor_slave_write => mm_interconnect_0_audio_in_dma_descriptor_slave_write, -- audio_in_dma_descriptor_slave.write
audio_in_dma_descriptor_slave_writedata => mm_interconnect_0_audio_in_dma_descriptor_slave_writedata, -- .writedata
audio_in_dma_descriptor_slave_byteenable => mm_interconnect_0_audio_in_dma_descriptor_slave_byteenable, -- .byteenable
audio_in_dma_descriptor_slave_waitrequest => mm_interconnect_0_audio_in_dma_descriptor_slave_waitrequest, -- .waitrequest
audio_out_dma_csr_address => mm_interconnect_0_audio_out_dma_csr_address, -- audio_out_dma_csr.address
audio_out_dma_csr_write => mm_interconnect_0_audio_out_dma_csr_write, -- .write
audio_out_dma_csr_read => mm_interconnect_0_audio_out_dma_csr_read, -- .read
audio_out_dma_csr_readdata => mm_interconnect_0_audio_out_dma_csr_readdata, -- .readdata
audio_out_dma_csr_writedata => mm_interconnect_0_audio_out_dma_csr_writedata, -- .writedata
audio_out_dma_csr_byteenable => mm_interconnect_0_audio_out_dma_csr_byteenable, -- .byteenable
audio_out_dma_descriptor_slave_write => mm_interconnect_0_audio_out_dma_descriptor_slave_write, -- audio_out_dma_descriptor_slave.write
audio_out_dma_descriptor_slave_writedata => mm_interconnect_0_audio_out_dma_descriptor_slave_writedata, -- .writedata
audio_out_dma_descriptor_slave_byteenable => mm_interconnect_0_audio_out_dma_descriptor_slave_byteenable, -- .byteenable
audio_out_dma_descriptor_slave_waitrequest => mm_interconnect_0_audio_out_dma_descriptor_slave_waitrequest, -- .waitrequest
avalon2mem_0_avalon_slave_0_address => mm_interconnect_0_avalon2mem_0_avalon_slave_0_address, -- avalon2mem_0_avalon_slave_0.address
avalon2mem_0_avalon_slave_0_write => mm_interconnect_0_avalon2mem_0_avalon_slave_0_write, -- .write
avalon2mem_0_avalon_slave_0_read => mm_interconnect_0_avalon2mem_0_avalon_slave_0_read, -- .read
avalon2mem_0_avalon_slave_0_readdata => mm_interconnect_0_avalon2mem_0_avalon_slave_0_readdata, -- .readdata
avalon2mem_0_avalon_slave_0_writedata => mm_interconnect_0_avalon2mem_0_avalon_slave_0_writedata, -- .writedata
avalon2mem_0_avalon_slave_0_byteenable => mm_interconnect_0_avalon2mem_0_avalon_slave_0_byteenable, -- .byteenable
avalon2mem_0_avalon_slave_0_readdatavalid => mm_interconnect_0_avalon2mem_0_avalon_slave_0_readdatavalid, -- .readdatavalid
avalon2mem_0_avalon_slave_0_waitrequest => mm_interconnect_0_avalon2mem_0_avalon_slave_0_waitrequest, -- .waitrequest
io_bridge_0_avalon_slave_0_address => mm_interconnect_0_io_bridge_0_avalon_slave_0_address, -- io_bridge_0_avalon_slave_0.address
io_bridge_0_avalon_slave_0_write => mm_interconnect_0_io_bridge_0_avalon_slave_0_write, -- .write
io_bridge_0_avalon_slave_0_read => mm_interconnect_0_io_bridge_0_avalon_slave_0_read, -- .read
io_bridge_0_avalon_slave_0_readdata => mm_interconnect_0_io_bridge_0_avalon_slave_0_readdata, -- .readdata
io_bridge_0_avalon_slave_0_writedata => mm_interconnect_0_io_bridge_0_avalon_slave_0_writedata, -- .writedata
io_bridge_0_avalon_slave_0_readdatavalid => mm_interconnect_0_io_bridge_0_avalon_slave_0_readdatavalid, -- .readdatavalid
io_bridge_0_avalon_slave_0_waitrequest => mm_interconnect_0_io_bridge_0_avalon_slave_0_inv, -- .waitrequest
io_bridge_1_avalon_slave_0_address => mm_interconnect_0_io_bridge_1_avalon_slave_0_address, -- io_bridge_1_avalon_slave_0.address
io_bridge_1_avalon_slave_0_write => mm_interconnect_0_io_bridge_1_avalon_slave_0_write, -- .write
io_bridge_1_avalon_slave_0_read => mm_interconnect_0_io_bridge_1_avalon_slave_0_read, -- .read
io_bridge_1_avalon_slave_0_readdata => mm_interconnect_0_io_bridge_1_avalon_slave_0_readdata, -- .readdata
io_bridge_1_avalon_slave_0_writedata => mm_interconnect_0_io_bridge_1_avalon_slave_0_writedata, -- .writedata
io_bridge_1_avalon_slave_0_readdatavalid => mm_interconnect_0_io_bridge_1_avalon_slave_0_readdatavalid, -- .readdatavalid
io_bridge_1_avalon_slave_0_waitrequest => mm_interconnect_0_io_bridge_1_avalon_slave_0_inv, -- .waitrequest
nios2_gen2_0_debug_mem_slave_address => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address, -- nios2_gen2_0_debug_mem_slave.address
nios2_gen2_0_debug_mem_slave_write => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write, -- .write
nios2_gen2_0_debug_mem_slave_read => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read, -- .read
nios2_gen2_0_debug_mem_slave_readdata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata, -- .readdata
nios2_gen2_0_debug_mem_slave_writedata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata, -- .writedata
nios2_gen2_0_debug_mem_slave_byteenable => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable, -- .byteenable
nios2_gen2_0_debug_mem_slave_waitrequest => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest, -- .waitrequest
nios2_gen2_0_debug_mem_slave_debugaccess => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess, -- .debugaccess
onchip_memory2_0_s1_address => mm_interconnect_0_onchip_memory2_0_s1_address, -- onchip_memory2_0_s1.address
onchip_memory2_0_s1_write => mm_interconnect_0_onchip_memory2_0_s1_write, -- .write
onchip_memory2_0_s1_readdata => mm_interconnect_0_onchip_memory2_0_s1_readdata, -- .readdata
onchip_memory2_0_s1_writedata => mm_interconnect_0_onchip_memory2_0_s1_writedata, -- .writedata
onchip_memory2_0_s1_byteenable => mm_interconnect_0_onchip_memory2_0_s1_byteenable, -- .byteenable
onchip_memory2_0_s1_chipselect => mm_interconnect_0_onchip_memory2_0_s1_chipselect, -- .chipselect
onchip_memory2_0_s1_clken => mm_interconnect_0_onchip_memory2_0_s1_clken, -- .clken
pio_0_s1_address => mm_interconnect_0_pio_0_s1_address, -- pio_0_s1.address
pio_0_s1_write => mm_interconnect_0_pio_0_s1_write, -- .write
pio_0_s1_readdata => mm_interconnect_0_pio_0_s1_readdata, -- .readdata
pio_0_s1_writedata => mm_interconnect_0_pio_0_s1_writedata, -- .writedata
pio_0_s1_chipselect => mm_interconnect_0_pio_0_s1_chipselect, -- .chipselect
pio_1_s1_address => mm_interconnect_0_pio_1_s1_address, -- pio_1_s1.address
pio_1_s1_readdata => mm_interconnect_0_pio_1_s1_readdata, -- .readdata
pio_2_s1_address => mm_interconnect_0_pio_2_s1_address, -- pio_2_s1.address
pio_2_s1_readdata => mm_interconnect_0_pio_2_s1_readdata, -- .readdata
pio_3_s1_address => mm_interconnect_0_pio_3_s1_address, -- pio_3_s1.address
pio_3_s1_write => mm_interconnect_0_pio_3_s1_write, -- .write
pio_3_s1_readdata => mm_interconnect_0_pio_3_s1_readdata, -- .readdata
pio_3_s1_writedata => mm_interconnect_0_pio_3_s1_writedata, -- .writedata
pio_3_s1_chipselect => mm_interconnect_0_pio_3_s1_chipselect, -- .chipselect
uart_0_s1_address => mm_interconnect_0_uart_0_s1_address, -- uart_0_s1.address
uart_0_s1_write => mm_interconnect_0_uart_0_s1_write, -- .write
uart_0_s1_read => mm_interconnect_0_uart_0_s1_read, -- .read
uart_0_s1_readdata => mm_interconnect_0_uart_0_s1_readdata, -- .readdata
uart_0_s1_writedata => mm_interconnect_0_uart_0_s1_writedata, -- .writedata
uart_0_s1_begintransfer => mm_interconnect_0_uart_0_s1_begintransfer, -- .begintransfer
uart_0_s1_chipselect => mm_interconnect_0_uart_0_s1_chipselect -- .chipselect
);
irq_mapper : component nios_dut_irq_mapper
port map (
clk => sys_clock_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
receiver0_irq => irq_mapper_receiver0_irq, -- receiver0.irq
receiver1_irq => irq_mapper_receiver1_irq, -- receiver1.irq
receiver2_irq => irq_mapper_receiver2_irq, -- receiver2.irq
receiver3_irq => irq_mapper_receiver3_irq, -- receiver3.irq
receiver4_irq => irq_mapper_receiver4_irq, -- receiver4.irq
receiver5_irq => irq_mapper_receiver5_irq, -- receiver5.irq
sender_irq => nios2_gen2_0_irq_irq -- sender.irq
);
rst_controller : component altera_reset_controller
generic map (
NUM_RESET_INPUTS => 1,
OUTPUT_RESET_SYNC_EDGES => "deassert",
SYNC_DEPTH => 2,
RESET_REQUEST_PRESENT => 1,
RESET_REQ_WAIT_TIME => 1,
MIN_RST_ASSERTION_TIME => 3,
RESET_REQ_EARLY_DSRT_TIME => 1,
USE_RESET_REQUEST_IN0 => 0,
USE_RESET_REQUEST_IN1 => 0,
USE_RESET_REQUEST_IN2 => 0,
USE_RESET_REQUEST_IN3 => 0,
USE_RESET_REQUEST_IN4 => 0,
USE_RESET_REQUEST_IN5 => 0,
USE_RESET_REQUEST_IN6 => 0,
USE_RESET_REQUEST_IN7 => 0,
USE_RESET_REQUEST_IN8 => 0,
USE_RESET_REQUEST_IN9 => 0,
USE_RESET_REQUEST_IN10 => 0,
USE_RESET_REQUEST_IN11 => 0,
USE_RESET_REQUEST_IN12 => 0,
USE_RESET_REQUEST_IN13 => 0,
USE_RESET_REQUEST_IN14 => 0,
USE_RESET_REQUEST_IN15 => 0,
ADAPT_RESET_REQUEST => 0
)
port map (
reset_in0 => sys_reset_reset_n_ports_inv, -- reset_in0.reset
clk => sys_clock_clk, -- clk.clk
reset_out => rst_controller_reset_out_reset, -- reset_out.reset
reset_req => rst_controller_reset_out_reset_req, -- .reset_req
reset_req_in0 => '0', -- (terminated)
reset_in1 => '0', -- (terminated)
reset_req_in1 => '0', -- (terminated)
reset_in2 => '0', -- (terminated)
reset_req_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_req_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_req_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_req_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_req_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_req_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_req_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_req_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_req_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_req_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_req_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_req_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_req_in14 => '0', -- (terminated)
reset_in15 => '0', -- (terminated)
reset_req_in15 => '0' -- (terminated)
);
sys_reset_reset_n_ports_inv <= not sys_reset_reset_n;
mm_interconnect_0_io_bridge_1_avalon_slave_0_inv <= not io_bridge_1_avalon_slave_0_waitrequest;
mm_interconnect_0_io_bridge_0_avalon_slave_0_inv <= not io_bridge_0_avalon_slave_0_waitrequest;
mm_interconnect_0_pio_0_s1_write_ports_inv <= not mm_interconnect_0_pio_0_s1_write;
mm_interconnect_0_uart_0_s1_read_ports_inv <= not mm_interconnect_0_uart_0_s1_read;
mm_interconnect_0_uart_0_s1_write_ports_inv <= not mm_interconnect_0_uart_0_s1_write;
mm_interconnect_0_pio_3_s1_write_ports_inv <= not mm_interconnect_0_pio_3_s1_write;
rst_controller_reset_out_reset_ports_inv <= not rst_controller_reset_out_reset;
end architecture rtl; -- of nios_dut
| gpl-3.0 | 061e958ddca8bf8441fe559f8ef770d8 | 0.479127 | 3.810213 | false | false | false | false |
markusC64/1541ultimate2 | fpga/io/audio/sine_osc.vhd | 1 | 3,321 | -------------------------------------------------------------------------------
-- Title : sine_osc
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: I2S Serializer / Deserializer
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sine_osc is
port (
clock : in std_logic;
enable : in std_logic := '1';
reset : in std_logic;
freq : in unsigned(15 downto 0) := X"FFFF";
sine : out signed(19 downto 0);
cosine : out signed(19 downto 0) );
end sine_osc;
architecture gideon of sine_osc is
signal enable_d : std_logic;
signal cos_i : signed(sine'range);
signal sin_i : signed(cosine'range);
signal scaled_sin : signed(sine'high + freq'high + 4 downto sine'high);
signal scaled_cos : signed(sine'high + freq'high + 4 downto sine'high);
begin
process(clock)
function scale(i: signed; f : unsigned) return signed is
variable fs : signed(f'high+3 downto 0);
variable o : signed(i'high + f'high + 4 downto 0);
begin
fs := "000" & signed(f);
o := i * fs;
return o(o'high downto o'high-i'high);
end function;
function sum_limit(i1, i2 : signed) return signed is
variable o : signed(i1'range);
begin
o := i1 + i2;
if (i1(i1'high) = i2(i2'high)) and (o(o'high) /= i1(i1'high)) then
if i1(i1'high)='0' then
o := (others => '1');
o(o'left) := '0';
else
o := (others => '0');
o(o'left) := '1';
end if;
end if;
return o;
end function;
function sub_limit(i1, i2 : signed) return signed is
variable o : signed(i1'range);
begin
o := i1 - i2;
if (i1(i1'high) /= i2(i2'high)) and (o(o'high) /= i1(i1'high)) then
if i1(i1'high)='0' then
o := (others => '1');
o(o'left) := '0';
else
o := (others => '0');
o(o'left) := '1';
end if;
end if;
return o;
end function;
begin
if rising_edge(clock) then
if reset='1' then
sin_i <= (others => '0');
cos_i <= (others => '1');
cos_i(cos_i'left) <= '0';
enable_d <= '0';
else
enable_d <= enable;
if enable = '1' then
scaled_cos <= scale(cos_i, freq);
scaled_sin <= scale(sin_i, freq);
end if;
if enable_d = '1' then
sin_i <= sum_limit(scaled_cos, sin_i);
cos_i <= sub_limit(cos_i, scaled_sin);
end if;
end if;
end if;
end process;
sine <= sin_i;
cosine <= cos_i;
end gideon;
| gpl-3.0 | 55c7ebeff9c134d46e07d0ad8ed14c78 | 0.401987 | 3.963007 | false | false | false | false |
markusC64/1541ultimate2 | fpga/io/audio/lp_filter_tb.vhd | 1 | 2,168 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : lp_filter_tb
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: Testbench for low pass filter
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity lp_filter_tb is
end entity;
architecture test of lp_filter_tb is
signal clock : std_logic := '0';
signal reset : std_logic;
signal signal_in : signed(17 downto 0);
signal high_pass : signed(17 downto 0);
signal band_pass : signed(17 downto 0);
signal low_pass : signed(17 downto 0);
signal valid_out : std_logic;
signal s_freq : real := 625.0; -- Hz
signal sin_step : real := 0.0;
signal max : signed(17 downto 0);
begin
clock <= not clock after 8 ns; -- 62.5 MHz
reset <= '1', '0' after 100 ns;
sin_step <= (16.0e-9 * s_freq * 2.0 * 3.14159265);
process
begin
while (s_freq < 100000.0) loop
max <= to_signed(0, max'length);
for i in 0 to 250000-1 loop
signal_in <= to_signed(integer(65536.0 * sin(sin_step * real(i))), 18);
wait until clock = '1';
if (i > 50000) and (low_pass > max) then
max <= low_pass;
end if;
end loop;
report real'image(s_freq) & "," & real'image(real(to_integer(max)) / 65536.0);
s_freq <= s_freq * sqrt(2.0);
end loop;
wait;
end process;
i_filt: entity work.lp_filter
port map (
clock => clock,
reset => reset,
signal_in => signal_in,
high_pass => high_pass,
band_pass => band_pass,
low_pass => low_pass,
valid_out => valid_out
);
end architecture;
| gpl-3.0 | 9b74766f3e5ce8dd0af74a4d95cb67d1 | 0.45572 | 4.02974 | false | false | false | false |
markusC64/1541ultimate2 | fpga/io/usb2/vhdl_source/usb_pkg.vhd | 1 | 12,213 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package usb_pkg is
constant c_pid_out : std_logic_vector(3 downto 0) := X"1"; -- token
constant c_pid_in : std_logic_vector(3 downto 0) := X"9"; -- token
constant c_pid_sof : std_logic_vector(3 downto 0) := X"5"; -- token
constant c_pid_setup : std_logic_vector(3 downto 0) := X"D"; -- token
constant c_pid_data0 : std_logic_vector(3 downto 0) := X"3"; -- data
constant c_pid_data1 : std_logic_vector(3 downto 0) := X"B"; -- data
constant c_pid_data2 : std_logic_vector(3 downto 0) := X"7"; -- data
constant c_pid_mdata : std_logic_vector(3 downto 0) := X"F"; -- data
constant c_pid_ack : std_logic_vector(3 downto 0) := X"2"; -- handshake
constant c_pid_nak : std_logic_vector(3 downto 0) := X"A"; -- handshake
constant c_pid_stall : std_logic_vector(3 downto 0) := X"E"; -- handshake
constant c_pid_nyet : std_logic_vector(3 downto 0) := X"6"; -- handshake
constant c_pid_pre : std_logic_vector(3 downto 0) := X"C"; -- token ->
constant c_pid_err : std_logic_vector(3 downto 0) := X"C"; -- handshake <-
constant c_pid_split : std_logic_vector(3 downto 0) := X"8"; -- token ->
constant c_pid_ping : std_logic_vector(3 downto 0) := X"4"; -- token
constant c_pid_reserved : std_logic_vector(3 downto 0) := X"0";
function is_token(i : std_logic_vector(3 downto 0)) return boolean;
function is_split(i : std_logic_vector(3 downto 0)) return boolean;
function is_handshake(i : std_logic_vector(3 downto 0)) return boolean;
function get_togglebit(i : std_logic_vector(3 downto 0)) return std_logic;
type t_token is record
device_addr : std_logic_vector(6 downto 0);
endpoint_addr : std_logic_vector(3 downto 0);
end record;
constant c_token_init : t_token := ( "0000000", "0000" );
constant c_token_undefined : t_token := ( "XXXXXXX", "XXXX" );
type t_split_token is record
hub_address : std_logic_vector(6 downto 0);
sc : std_logic;
port_address : std_logic_vector(6 downto 0);
s : std_logic; -- start/speed (isochronous out start split), for interrupt/control transfers: Speed. 0=full, 1=low
e : std_logic; -- end (isochronous out start split) 00=middle, 10=beginning, 01=end, 11=all
et : std_logic_vector(1 downto 0); -- 00=control, 01=iso, 10=bulk, 11=interrupt
end record;
constant c_split_token_init : t_split_token := (
hub_address => "0000000",
sc => '0',
port_address => "0000000",
s => '0',
e => '0',
et => "00" );
constant c_split_token_undefined : t_split_token := (
hub_address => "XXXXXXX",
sc => 'X',
port_address => "XXXXXXX",
s => 'X',
e => 'X',
et => "XX" );
constant c_split_token_bogus : t_split_token := (
hub_address => "0000001",
sc => '0',
port_address => "0000010",
s => '0',
e => '0',
et => "11" );
type t_usb_rx is record
receiving : std_logic;
valid_token : std_logic;
valid_split : std_logic;
valid_handsh : std_logic;
valid_packet : std_logic;
error : std_logic;
error_code : std_logic_vector(2 downto 0);
pid : std_logic_vector(3 downto 0);
token : t_token;
split_token : t_split_token;
data_valid : std_logic;
data_start : std_logic;
data : std_logic_vector(7 downto 0);
end record;
type t_usb_tx_req is record
send_token : std_logic;
send_split : std_logic;
send_handsh : std_logic;
send_packet : std_logic;
pid : std_logic_vector(3 downto 0);
token : t_token;
split_token : t_split_token;
no_data : std_logic;
data : std_logic_vector(7 downto 0);
data_valid : std_logic;
data_last : std_logic;
end record;
type t_usb_tx_resp is record
request_ack : std_logic;
busy : std_logic;
data_wait : std_logic;
end record;
type t_usb_tx_req_array is array(natural range <>) of t_usb_tx_req;
-- function or_reduce(a : t_usb_tx_req_array) return t_usb_tx_req;
constant c_usb_rx_init : t_usb_rx := (
receiving => '0',
valid_token => '0',
valid_split => '0',
valid_handsh => '0',
valid_packet => '0',
error => '0',
error_code => "000",
pid => X"0",
token => c_token_init,
split_token => c_split_token_init,
data_valid => '0',
data_start => '0',
data => X"00" );
constant c_usb_tx_req_init : t_usb_tx_req := (
send_token => '0',
send_split => '0',
send_handsh => '0',
send_packet => '0',
pid => c_pid_reserved,
token => c_token_init,
split_token => c_split_token_init,
no_data => '0',
data => X"00",
data_valid => '0',
data_last => '0' );
constant c_usb_tx_ack : t_usb_tx_req := (
send_token => '0',
send_split => '0',
send_handsh => '1',
send_packet => '0',
pid => c_pid_ack,
token => c_token_undefined,
split_token => c_split_token_undefined,
no_data => 'X',
data => "XXXXXXXX",
data_valid => '0',
data_last => 'X' );
constant c_usb_tx_nack : t_usb_tx_req := (
send_token => '0',
send_split => '0',
send_handsh => '1',
send_packet => '0',
pid => c_pid_nak,
token => c_token_undefined,
split_token => c_split_token_undefined,
no_data => 'X',
data => "XXXXXXXX",
data_valid => '0',
data_last => 'X' );
constant c_usb_tx_nyet : t_usb_tx_req := (
send_token => '0',
send_split => '0',
send_handsh => '1',
send_packet => '0',
pid => c_pid_nyet,
token => c_token_undefined,
split_token => c_split_token_undefined,
no_data => 'X',
data => "XXXXXXXX",
data_valid => '0',
data_last => 'X' );
constant c_usb_tx_stall : t_usb_tx_req := (
send_token => '0',
send_split => '0',
send_handsh => '1',
send_packet => '0',
pid => c_pid_stall,
token => c_token_undefined,
split_token => c_split_token_undefined,
no_data => 'X',
data => "XXXXXXXX",
data_valid => '0',
data_last => 'X' );
constant c_usb_tx_data_out0 : t_usb_tx_req := (
send_token => '0',
send_split => '0',
send_handsh => '0',
send_packet => '1',
pid => c_pid_data0,
token => c_token_undefined,
split_token => c_split_token_undefined,
no_data => '0',
data => "XXXXXXXX",
data_valid => '0',
data_last => '0' );
constant c_usb_tx_data_out1 : t_usb_tx_req := (
send_token => '0',
send_split => '0',
send_handsh => '0',
send_packet => '1',
pid => c_pid_data1,
token => c_token_undefined,
split_token => c_split_token_undefined,
no_data => '0',
data => "XXXXXXXX",
data_valid => '0',
data_last => '0' );
function token_to_vector(t : t_token) return std_logic_vector;
function vector_to_token(v : std_logic_vector) return t_token;
function split_token_to_vector(t : t_split_token) return std_logic_vector;
function vector_to_split_token(v : std_logic_vector) return t_split_token;
end package;
package body usb_pkg is
function is_token(i : std_logic_vector(3 downto 0)) return boolean is
begin
case i is
when c_pid_out => return true;
when c_pid_in => return true;
when c_pid_sof => return true;
when c_pid_setup => return true;
when c_pid_pre => return true;
when c_pid_ping => return true;
when others => return false;
end case;
return false;
end function;
function is_split(i : std_logic_vector(3 downto 0)) return boolean is
begin
return (i = c_pid_split);
end function;
function is_handshake(i : std_logic_vector(3 downto 0)) return boolean is
begin
case i is
when c_pid_ack => return true;
when c_pid_nak => return true;
when c_pid_nyet => return true;
when c_pid_stall => return true;
when c_pid_err => return true; -- reused! HUB reply to CSPLIT
when others => return false;
end case;
return false;
end function;
function get_togglebit(i : std_logic_vector(3 downto 0)) return std_logic is
begin
return i(3);
end function;
function split_token_to_vector(t : t_split_token) return std_logic_vector is
variable ret : std_logic_vector(18 downto 0);
begin
ret(18 downto 17) := t.et;
ret(16) := t.e;
ret(15) := t.s;
ret(14 downto 8) := t.port_address;
ret(7) := t.sc;
ret(6 downto 0) := t.hub_address;
return ret;
end function;
function vector_to_split_token(v : std_logic_vector) return t_split_token is
variable va : std_logic_vector(18 downto 0);
variable ret : t_split_token;
begin
va := v;
ret.et := va(18 downto 17);
ret.e := va(16);
ret.s := va(15);
ret.port_address := va(14 downto 8);
ret.sc := va(7);
ret.hub_address := va(6 downto 0);
return ret;
end function;
-- Token conversion
function token_to_vector(t : t_token) return std_logic_vector is
variable ret : std_logic_vector(10 downto 0);
begin
ret := t.endpoint_addr & t.device_addr;
return ret;
end function;
function vector_to_token(v : std_logic_vector) return t_token is
alias va : std_logic_vector(10 downto 0) is v;
variable ret : t_token;
begin
ret.device_addr := va(6 downto 0);
ret.endpoint_addr := va(10 downto 7);
return ret;
end function;
end;
| gpl-3.0 | 29b00d75721a2b83d0c90a9a5479875c | 0.448457 | 3.765957 | false | false | false | false |
markusC64/1541ultimate2 | fpga/io/usb2/vhdl_source/usb_host_interface.vhd | 1 | 5,557 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.usb_pkg.all;
entity usb_host_interface is
generic (
g_simulation : boolean := false );
port (
clock : in std_logic;
reset : in std_logic;
usb_rx : out t_usb_rx;
usb_tx_req : in t_usb_tx_req;
usb_tx_resp : out t_usb_tx_resp;
-- low level ulpi interfacing
reg_read : in std_logic := '0';
reg_write : in std_logic;
reg_address : in std_logic_vector(5 downto 0);
reg_wdata : in std_logic_vector(7 downto 0);
reg_rdata : out std_logic_vector(7 downto 0);
reg_ack : out std_logic;
do_chirp : in std_logic := '0';
chirp_data : in std_logic := '0';
status : out std_logic_vector(7 downto 0);
speed : in std_logic_vector(1 downto 0);
ulpi_nxt : in std_logic;
ulpi_stp : out std_logic;
ulpi_dir : in std_logic;
ulpi_data : inout std_logic_vector(7 downto 0) );
end entity;
architecture structural of usb_host_interface is
signal status_i : std_logic_vector(7 downto 0);
signal tx_data : std_logic_vector(7 downto 0) := X"00";
signal tx_last : std_logic := '0';
signal tx_valid : std_logic := '0';
signal tx_start : std_logic := '0';
signal tx_next : std_logic := '0';
signal rx_data : std_logic_vector(7 downto 0) := X"00";
signal rx_register : std_logic := '0';
signal rx_last : std_logic := '0';
signal rx_valid : std_logic := '0';
signal rx_store : std_logic := '0';
signal rx_crc_sync : std_logic;
signal rx_crc_dvalid : std_logic;
signal tx_crc_sync : std_logic;
signal tx_crc_dvalid : std_logic;
signal crc_sync : std_logic;
signal crc_dvalid : std_logic;
signal tx_data_to_crc: std_logic_vector(7 downto 0);
signal crc_data_in : std_logic_vector(7 downto 0);
signal data_crc : std_logic_vector(15 downto 0);
begin
i_ulpi: entity work.ulpi_bus
port map (
clock => clock,
reset => reset,
ULPI_DATA => ulpi_data,
ULPI_DIR => ulpi_dir,
ULPI_NXT => ulpi_nxt,
ULPI_STP => ulpi_stp,
-- status
status => status_i,
operational => '1',
-- chirp interface
do_chirp => do_chirp,
chirp_data => chirp_data,
-- register interface
reg_read => reg_read,
reg_write => reg_write,
reg_address => reg_address,
reg_wdata => reg_wdata,
reg_ack => reg_ack,
-- stream interface
tx_data => tx_data,
tx_last => tx_last,
tx_valid => tx_valid,
tx_start => tx_start,
tx_next => tx_next,
rx_data => rx_data,
rx_register => rx_register,
rx_last => rx_last,
rx_valid => rx_valid,
rx_store => rx_store );
i_rx: entity work.ulpi_rx
generic map (
g_support_split => g_simulation,
g_support_token => g_simulation ) -- hosts do not receive tokens
port map (
clock => clock,
reset => reset,
rx_data => rx_data,
rx_last => rx_last,
rx_valid => rx_valid,
rx_store => rx_store,
status => status_i,
-- interface to DATA CRC (shared resource)
crc_sync => rx_crc_sync,
crc_dvalid => rx_crc_dvalid,
data_crc => data_crc,
usb_rx => usb_rx );
crc_sync <= rx_crc_sync or tx_crc_sync;
crc_dvalid <= rx_crc_dvalid or tx_crc_dvalid;
crc_data_in <= rx_data when rx_crc_dvalid='1' else tx_data_to_crc;
i_data_crc: entity work.data_crc
port map (
clock => clock,
sync => crc_sync,
valid => crc_dvalid,
data_in => crc_data_in,
crc => data_crc );
i_tx: entity work.ulpi_tx
generic map (
g_simulation => g_simulation,
g_support_split => true,
g_support_token => true ) -- hosts do send tokens
port map (
clock => clock,
reset => reset,
-- Bus Interface
tx_start => tx_start,
tx_last => tx_last,
tx_valid => tx_valid,
tx_next => tx_next,
tx_data => tx_data,
rx_busy => rx_store,
-- interface to DATA CRC (shared resource)
crc_sync => tx_crc_sync,
crc_dvalid => tx_crc_dvalid,
data_crc => data_crc,
data_to_crc => tx_data_to_crc,
-- Status
status => status_i,
speed => speed,
-- Interface to send tokens and handshakes
usb_tx_req => usb_tx_req,
usb_tx_resp => usb_tx_resp );
status <= status_i;
reg_rdata <= rx_data;
end architecture;
| gpl-3.0 | 26ce989bf4e5dc4b8b959b49d67fc48d | 0.456361 | 3.742088 | false | false | false | false |
markusC64/1541ultimate2 | fpga/io/audio/lp_filter.vhd | 1 | 6,015 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2016 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
--
-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
--
-- Note that this file is copyrighted, and is not supposed to be used in other
-- projects without written permission from the author.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.my_math_pkg.all;
entity lp_filter is
generic (
g_divider : natural := 221 );
port (
clock : in std_logic;
reset : in std_logic;
signal_in : in signed(17 downto 0);
high_pass : out signed(17 downto 0);
band_pass : out signed(17 downto 0);
low_pass : out signed(17 downto 0);
error_out : out std_logic;
valid_out : out std_logic );
end entity;
architecture dsvf of lp_filter is
signal filter_q : signed(signal_in'range);
signal filter_f : signed(signal_in'range);
signal input_sc : signed(signal_in'range);
signal xa : signed(signal_in'range);
signal xb : signed(signal_in'range);
signal sum_b : signed(signal_in'range);
signal sub_a : signed(signal_in'range);
signal sub_b : signed(signal_in'range);
signal x_reg : signed(signal_in'range) := (others => '0');
signal bp_reg : signed(signal_in'range);
signal hp_reg : signed(signal_in'range);
signal lp_reg : signed(signal_in'range);
signal temp_reg : signed(signal_in'range);
signal error : std_logic := '0';
signal divider : integer range 0 to g_divider-1;
signal instruction : std_logic_vector(7 downto 0);
type t_byte_array is array(natural range <>) of std_logic_vector(7 downto 0);
constant c_program : t_byte_array := (X"80", X"12", X"81", X"4C", X"82", X"20");
alias xa_select : std_logic is instruction(0);
alias xb_select : std_logic is instruction(1);
alias sub_a_sel : std_logic is instruction(2);
alias sub_b_sel : std_logic is instruction(3);
alias sum_to_lp : std_logic is instruction(4);
alias sum_to_bp : std_logic is instruction(5);
alias sub_to_hp : std_logic is instruction(6);
alias mult_enable : std_logic is instruction(7);
begin
-- -- Derive the actual 'f' and 'q' parameters
-- i_q_table: entity work.Q_table
-- port map (
-- Q_reg => X"6",
-- filter_q => filter_q ); -- 2.16 format
filter_q <= to_signed(65536, filter_q'length); -- 92682
filter_f <= to_signed(16384, filter_f'length);
input_sc <= signal_in; -- shift_right(signal_in, 1);
-- operations to execute the filter:
-- bp_f = f * bp_reg
-- q_contrib = q * bp_reg
-- lp = bp_f + lp_reg
-- temp = input - lp
-- hp = temp - q_contrib
-- hp_f = f * hp
-- bp = hp_f + bp_reg
-- bp_reg = bp
-- lp_reg = lp
-- x_reg = f * bp_reg -- 10000000 -- 80
-- lp_reg = x_reg + lp_reg -- 00010010 -- 12
-- q_contrib = q * bp_reg -- 10000001 -- 81
-- temp = input - lp -- 00000000 -- 00 (can be merged with previous!)
-- hp_reg = temp - q_contrib -- 01001100 -- 4C
-- x_reg = f * hp_reg -- 10000010 -- 82
-- bp_reg = x_reg + bp_reg -- 00100000 -- 20
-- now perform the arithmetic
xa <= filter_f when xa_select='0' else filter_q;
xb <= bp_reg when xb_select='0' else hp_reg;
sum_b <= bp_reg when xb_select='0' else lp_reg;
sub_a <= input_sc when sub_a_sel='0' else temp_reg;
sub_b <= lp_reg when sub_b_sel='0' else x_reg;
process(clock)
variable x_result : signed(35 downto 0);
variable sum_result : signed(17 downto 0);
variable sub_result : signed(17 downto 0);
begin
if rising_edge(clock) then
x_result := xa * xb;
if mult_enable='1' then
x_reg <= x_result(33 downto 16);
if (x_result(35 downto 33) /= "000") and (x_result(35 downto 33) /= "111") then
error <= not error;
end if;
end if;
sum_result := sum_limit(x_reg, sum_b);
temp_reg <= sum_result;
if sum_to_lp='1' then
lp_reg <= sum_result;
end if;
if sum_to_bp='1' then
bp_reg <= sum_result;
end if;
sub_result := sub_limit(sub_a, sub_b);
temp_reg <= sub_result;
if sub_to_hp='1' then
hp_reg <= sub_result;
end if;
-- control part
instruction <= (others => '0');
if reset='1' then
hp_reg <= (others => '0');
lp_reg <= (others => '0');
bp_reg <= (others => '0');
divider <= 0;
elsif divider = g_divider-1 then
divider <= 0;
else
divider <= divider + 1;
if divider < c_program'length then
instruction <= c_program(divider);
end if;
end if;
if divider = c_program'length then
valid_out <= '1';
else
valid_out <= '0';
end if;
end if;
end process;
high_pass <= hp_reg;
band_pass <= bp_reg;
low_pass <= lp_reg;
error_out <= error;
end dsvf;
| gpl-3.0 | 7c60b62ab7823bc47c643f2dfec849d5 | 0.470823 | 3.703818 | false | false | false | false |
markusC64/1541ultimate2 | fpga/nios_c5/nios/synthesis/nios_rst_controller_001.vhd | 2 | 9,074 | -- nios_rst_controller_001.vhd
-- Generated using ACDS version 15.1 185
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nios_rst_controller_001 is
generic (
NUM_RESET_INPUTS : integer := 1;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 1;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := '0'; -- reset_in0.reset
clk : in std_logic := '0'; -- clk.clk
reset_out : out std_logic; -- reset_out.reset
reset_req : out std_logic; -- .reset_req
reset_in1 : in std_logic := '0';
reset_in10 : in std_logic := '0';
reset_in11 : in std_logic := '0';
reset_in12 : in std_logic := '0';
reset_in13 : in std_logic := '0';
reset_in14 : in std_logic := '0';
reset_in15 : in std_logic := '0';
reset_in2 : in std_logic := '0';
reset_in3 : in std_logic := '0';
reset_in4 : in std_logic := '0';
reset_in5 : in std_logic := '0';
reset_in6 : in std_logic := '0';
reset_in7 : in std_logic := '0';
reset_in8 : in std_logic := '0';
reset_in9 : in std_logic := '0';
reset_req_in0 : in std_logic := '0';
reset_req_in1 : in std_logic := '0';
reset_req_in10 : in std_logic := '0';
reset_req_in11 : in std_logic := '0';
reset_req_in12 : in std_logic := '0';
reset_req_in13 : in std_logic := '0';
reset_req_in14 : in std_logic := '0';
reset_req_in15 : in std_logic := '0';
reset_req_in2 : in std_logic := '0';
reset_req_in3 : in std_logic := '0';
reset_req_in4 : in std_logic := '0';
reset_req_in5 : in std_logic := '0';
reset_req_in6 : in std_logic := '0';
reset_req_in7 : in std_logic := '0';
reset_req_in8 : in std_logic := '0';
reset_req_in9 : in std_logic := '0'
);
end entity nios_rst_controller_001;
architecture rtl of nios_rst_controller_001 is
component altera_reset_controller is
generic (
NUM_RESET_INPUTS : integer := 6;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 0;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := 'X'; -- reset
clk : in std_logic := 'X'; -- clk
reset_out : out std_logic; -- reset
reset_req : out std_logic; -- reset_req
reset_req_in0 : in std_logic := 'X'; -- reset_req
reset_in1 : in std_logic := 'X'; -- reset
reset_req_in1 : in std_logic := 'X'; -- reset_req
reset_in2 : in std_logic := 'X'; -- reset
reset_req_in2 : in std_logic := 'X'; -- reset_req
reset_in3 : in std_logic := 'X'; -- reset
reset_req_in3 : in std_logic := 'X'; -- reset_req
reset_in4 : in std_logic := 'X'; -- reset
reset_req_in4 : in std_logic := 'X'; -- reset_req
reset_in5 : in std_logic := 'X'; -- reset
reset_req_in5 : in std_logic := 'X'; -- reset_req
reset_in6 : in std_logic := 'X'; -- reset
reset_req_in6 : in std_logic := 'X'; -- reset_req
reset_in7 : in std_logic := 'X'; -- reset
reset_req_in7 : in std_logic := 'X'; -- reset_req
reset_in8 : in std_logic := 'X'; -- reset
reset_req_in8 : in std_logic := 'X'; -- reset_req
reset_in9 : in std_logic := 'X'; -- reset
reset_req_in9 : in std_logic := 'X'; -- reset_req
reset_in10 : in std_logic := 'X'; -- reset
reset_req_in10 : in std_logic := 'X'; -- reset_req
reset_in11 : in std_logic := 'X'; -- reset
reset_req_in11 : in std_logic := 'X'; -- reset_req
reset_in12 : in std_logic := 'X'; -- reset
reset_req_in12 : in std_logic := 'X'; -- reset_req
reset_in13 : in std_logic := 'X'; -- reset
reset_req_in13 : in std_logic := 'X'; -- reset_req
reset_in14 : in std_logic := 'X'; -- reset
reset_req_in14 : in std_logic := 'X'; -- reset_req
reset_in15 : in std_logic := 'X'; -- reset
reset_req_in15 : in std_logic := 'X' -- reset_req
);
end component altera_reset_controller;
begin
rst_controller_001 : component altera_reset_controller
generic map (
NUM_RESET_INPUTS => NUM_RESET_INPUTS,
OUTPUT_RESET_SYNC_EDGES => OUTPUT_RESET_SYNC_EDGES,
SYNC_DEPTH => SYNC_DEPTH,
RESET_REQUEST_PRESENT => RESET_REQUEST_PRESENT,
RESET_REQ_WAIT_TIME => RESET_REQ_WAIT_TIME,
MIN_RST_ASSERTION_TIME => MIN_RST_ASSERTION_TIME,
RESET_REQ_EARLY_DSRT_TIME => RESET_REQ_EARLY_DSRT_TIME,
USE_RESET_REQUEST_IN0 => USE_RESET_REQUEST_IN0,
USE_RESET_REQUEST_IN1 => USE_RESET_REQUEST_IN1,
USE_RESET_REQUEST_IN2 => USE_RESET_REQUEST_IN2,
USE_RESET_REQUEST_IN3 => USE_RESET_REQUEST_IN3,
USE_RESET_REQUEST_IN4 => USE_RESET_REQUEST_IN4,
USE_RESET_REQUEST_IN5 => USE_RESET_REQUEST_IN5,
USE_RESET_REQUEST_IN6 => USE_RESET_REQUEST_IN6,
USE_RESET_REQUEST_IN7 => USE_RESET_REQUEST_IN7,
USE_RESET_REQUEST_IN8 => USE_RESET_REQUEST_IN8,
USE_RESET_REQUEST_IN9 => USE_RESET_REQUEST_IN9,
USE_RESET_REQUEST_IN10 => USE_RESET_REQUEST_IN10,
USE_RESET_REQUEST_IN11 => USE_RESET_REQUEST_IN11,
USE_RESET_REQUEST_IN12 => USE_RESET_REQUEST_IN12,
USE_RESET_REQUEST_IN13 => USE_RESET_REQUEST_IN13,
USE_RESET_REQUEST_IN14 => USE_RESET_REQUEST_IN14,
USE_RESET_REQUEST_IN15 => USE_RESET_REQUEST_IN15,
ADAPT_RESET_REQUEST => ADAPT_RESET_REQUEST
)
port map (
reset_in0 => reset_in0, -- reset_in0.reset
clk => clk, -- clk.clk
reset_out => reset_out, -- reset_out.reset
reset_req => reset_req, -- .reset_req
reset_req_in0 => '0', -- (terminated)
reset_in1 => '0', -- (terminated)
reset_req_in1 => '0', -- (terminated)
reset_in2 => '0', -- (terminated)
reset_req_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_req_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_req_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_req_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_req_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_req_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_req_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_req_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_req_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_req_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_req_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_req_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_req_in14 => '0', -- (terminated)
reset_in15 => '0', -- (terminated)
reset_req_in15 => '0' -- (terminated)
);
end architecture rtl; -- of nios_rst_controller_001
| gpl-3.0 | 404d31a5fef94daedfce6f6560b25f8c | 0.546286 | 2.727382 | false | false | false | false |
markusC64/1541ultimate2 | fpga/io/usb2/vhdl_source/usb_controller.vhd | 2 | 11,989 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.usb_pkg.all;
use work.io_bus_pkg.all;
use work.mem_bus_pkg.all;
library unisim;
use unisim.vcomponents.all;
entity usb_controller is
generic (
g_tag : std_logic_vector(7 downto 0) := X"55" );
port (
ulpi_clock : in std_logic;
ulpi_reset : in std_logic;
-- ULPI Interface
ULPI_DATA : inout std_logic_vector(7 downto 0);
ULPI_DIR : in std_logic;
ULPI_NXT : in std_logic;
ULPI_STP : out std_logic;
-- register interface bus
sys_clock : in std_logic;
sys_reset : in std_logic;
sys_mem_req : out t_mem_req;
sys_mem_resp: in t_mem_resp;
sys_io_req : in t_io_req;
sys_io_resp : out t_io_resp );
end usb_controller;
architecture wrap of usb_controller is
signal nano_addr : unsigned(7 downto 0);
signal nano_write : std_logic;
signal nano_read : std_logic;
signal nano_wdata : std_logic_vector(15 downto 0);
signal nano_rdata : std_logic_vector(15 downto 0);
signal stall : std_logic := '0';
signal rx_pid : std_logic_vector(3 downto 0) := X"0";
signal rx_token : std_logic_vector(10 downto 0) := (others => '0');
signal rx_valid_token : std_logic := '0';
signal rx_valid_handsh : std_logic := '0';
signal rx_valid_packet : std_logic := '0';
signal rx_error : std_logic := '0';
signal rx_user_valid : std_logic := '0';
signal rx_user_start : std_logic := '0';
signal rx_user_data : std_logic_vector(7 downto 0) := X"12";
signal tx_busy : std_logic;
signal tx_ack : std_logic;
signal tx_send_token : std_logic;
signal tx_send_handsh : std_logic;
signal tx_pid : std_logic_vector(3 downto 0);
signal tx_token : std_logic_vector(10 downto 0);
signal tx_send_data : std_logic;
signal tx_no_data : std_logic;
signal tx_user_data : std_logic_vector(7 downto 0);
signal tx_user_last : std_logic;
signal tx_user_next : std_logic;
signal tx_length : unsigned(10 downto 0);
signal transferred : unsigned(10 downto 0);
-- cmd interface
signal cmd_addr : std_logic_vector(3 downto 0);
signal cmd_valid : std_logic;
signal cmd_write : std_logic;
signal cmd_wdata : std_logic_vector(15 downto 0);
signal cmd_ack : std_logic;
signal cmd_ready : std_logic;
signal sys_buf_addr : std_logic_vector(10 downto 0);
signal sys_buf_en : std_logic;
signal sys_buf_we : std_logic;
signal sys_buf_wdata : std_logic_vector(7 downto 0);
signal sys_buf_rdata : std_logic_vector(7 downto 0);
signal ulpi_buf_addr : std_logic_vector(10 downto 0);
signal ulpi_buf_en : std_logic;
signal ulpi_buf_we : std_logic;
signal ulpi_buf_wdata : std_logic_vector(7 downto 0);
signal ulpi_buf_rdata : std_logic_vector(7 downto 0);
-- low level
signal tx_data : std_logic_vector(7 downto 0) := X"00";
signal tx_last : std_logic := '0';
signal tx_valid : std_logic := '0';
signal tx_start : std_logic := '0';
signal tx_next : std_logic := '0';
signal tx_chirp_start : std_logic;
signal tx_chirp_level : std_logic;
signal tx_chirp_end : std_logic;
signal rx_data : std_logic_vector(7 downto 0);
signal status : std_logic_vector(7 downto 0);
signal rx_last : std_logic;
signal rx_valid : std_logic;
signal rx_store : std_logic;
signal rx_register : std_logic;
signal reg_read : std_logic := '0';
signal reg_write : std_logic := '0';
signal reg_ack : std_logic;
signal reg_addr : std_logic_vector(5 downto 0);
signal reg_wdata : std_logic_vector(7 downto 0);
signal speed : std_logic_vector(1 downto 0) := "10"; -- TODO!
begin
i_nano: entity work.nano
port map (
clock => ulpi_clock,
reset => ulpi_reset,
-- i/o interface
io_addr => nano_addr,
io_write => nano_write,
io_read => nano_read,
io_wdata => nano_wdata,
io_rdata => nano_rdata,
stall => stall,
-- system interface (to write code into the nano)
sys_clock => sys_clock,
sys_reset => sys_reset,
sys_io_req => sys_io_req,
sys_io_resp => sys_io_resp );
i_regs: entity work.usb_io_bank
port map (
clock => ulpi_clock,
reset => ulpi_reset,
-- i/o interface
io_addr => nano_addr,
io_read => nano_read,
io_write => nano_write,
io_wdata => nano_wdata,
io_rdata => nano_rdata,
stall => stall,
-- memory controller
mem_ready => cmd_ready,
transferred => transferred,
-- Register access
reg_addr => reg_addr,
reg_read => reg_read,
reg_write => reg_write,
reg_ack => reg_ack,
reg_wdata => reg_wdata,
reg_rdata => rx_data,
status => status,
-- I/O pins from RX
rx_pid => rx_pid,
rx_token => rx_token,
rx_valid_token => rx_valid_token,
rx_valid_handsh => rx_valid_handsh,
rx_valid_packet => rx_valid_packet,
rx_error => rx_error,
-- I/O pins to TX
tx_pid => tx_pid,
tx_token => tx_token,
tx_send_token => tx_send_token,
tx_send_handsh => tx_send_handsh,
tx_send_data => tx_send_data,
tx_length => tx_length,
tx_no_data => tx_no_data,
tx_ack => tx_ack,
tx_chirp_start => tx_chirp_start,
tx_chirp_end => tx_chirp_end,
tx_chirp_level => tx_chirp_level );
i_bridge_to_mem_ctrl: entity work.bridge_to_mem_ctrl
port map (
ulpi_clock => ulpi_clock,
ulpi_reset => ulpi_reset,
nano_addr => nano_addr,
nano_write => nano_write,
nano_wdata => nano_wdata,
sys_clock => sys_clock,
sys_reset => sys_reset,
-- cmd interface
cmd_addr => cmd_addr,
cmd_valid => cmd_valid,
cmd_write => cmd_write,
cmd_wdata => cmd_wdata,
cmd_ack => cmd_ack );
i_memctrl: entity work.usb_memory_ctrl
generic map (
g_tag => g_tag )
port map (
clock => sys_clock,
reset => sys_reset,
-- cmd interface
cmd_addr => cmd_addr,
cmd_valid => cmd_valid,
cmd_write => cmd_write,
cmd_wdata => cmd_wdata,
cmd_ack => cmd_ack,
cmd_ready => cmd_ready,
-- BRAM interface
ram_addr => sys_buf_addr,
ram_en => sys_buf_en,
ram_we => sys_buf_we,
ram_wdata => sys_buf_wdata,
ram_rdata => sys_buf_rdata,
-- memory interface
mem_req => sys_mem_req,
mem_resp => sys_mem_resp );
i_buf_ram: RAMB16_S9_S9
port map (
CLKA => sys_clock,
SSRA => sys_reset,
ENA => sys_buf_en,
WEA => sys_buf_we,
ADDRA => sys_buf_addr,
DIA => sys_buf_wdata,
DIPA => "0",
DOA => sys_buf_rdata,
CLKB => ulpi_clock,
SSRB => ulpi_reset,
ENB => ulpi_buf_en,
WEB => ulpi_buf_we,
ADDRB => ulpi_buf_addr,
DIB => ulpi_buf_wdata,
DIPB => "0",
DOB => ulpi_buf_rdata );
i_buf_ctrl: entity work.rxtx_to_buf
port map (
clock => ulpi_clock,
reset => ulpi_reset,
-- transferred length
transferred => transferred,
-- bram interface
ram_addr => ulpi_buf_addr,
ram_wdata => ulpi_buf_wdata,
ram_rdata => ulpi_buf_rdata,
ram_we => ulpi_buf_we,
ram_en => ulpi_buf_en,
-- Interface from RX
user_rx_valid => rx_user_valid,
user_rx_start => rx_user_start,
user_rx_data => rx_user_data,
user_rx_last => rx_last,
-- Interface to TX
send_data => tx_send_data,
last_addr => tx_length,
no_data => tx_no_data,
user_tx_data => tx_user_data,
user_tx_last => tx_user_last,
user_tx_next => tx_user_next );
i_tx: entity work.ulpi_tx
port map (
clock => ulpi_clock,
reset => ulpi_reset,
-- Bus Interface
tx_start => tx_start,
tx_last => tx_last,
tx_valid => tx_valid,
tx_next => tx_next,
tx_data => tx_data,
-- Status
speed => speed,
status => status,
busy => tx_busy,
tx_ack => tx_ack,
-- Interface to send tokens
send_token => tx_send_token,
send_handsh => tx_send_handsh,
pid => tx_pid,
token => tx_token,
-- Interface to send data packets
send_data => tx_send_data,
no_data => tx_no_data,
user_data => tx_user_data,
user_last => tx_user_last,
user_next => tx_user_next,
-- Interface to read/write registers and reset packets
send_reset_data => tx_chirp_start,
reset_data => tx_chirp_level,
reset_last => tx_chirp_end );
i_rx: entity work.ulpi_rx
generic map (
g_allow_token => false )
port map (
clock => ulpi_clock,
reset => ulpi_reset,
rx_data => rx_data,
rx_last => rx_last,
rx_valid => rx_valid,
rx_store => rx_store,
pid => rx_pid,
token => rx_token,
valid_token => rx_valid_token,
valid_handsh => rx_valid_handsh,
valid_packet => rx_valid_packet,
data_out => rx_user_data,
data_valid => rx_user_valid,
data_start => rx_user_start,
error => rx_error );
i_bus: entity work.ulpi_bus
port map (
clock => ulpi_clock,
reset => ulpi_reset,
ULPI_DATA => ULPI_DATA,
ULPI_DIR => ULPI_DIR,
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP,
status => status,
-- register interface
reg_read => reg_read,
reg_write => reg_write,
reg_address => reg_addr,
reg_wdata => reg_wdata,
reg_ack => reg_ack,
-- stream interface
tx_data => tx_data,
tx_last => tx_last,
tx_valid => tx_valid,
tx_start => tx_start,
tx_next => tx_next,
rx_data => rx_data,
rx_last => rx_last,
rx_register => rx_register,
rx_store => rx_store,
rx_valid => rx_valid );
end wrap;
| gpl-3.0 | 57937974e67ea4ed238c87974e72a9cd | 0.471015 | 3.587373 | false | false | false | false |
markusC64/1541ultimate2 | fpga/fpga_top/ultimate_fpga/vhdl_source/ultimate_mb_700a.vhd | 1 | 14,434 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
use work.io_bus_pkg.all;
entity ultimate_mb_700a is
generic (
g_acia : boolean := true;
g_eeprom : boolean := false;
g_dual_drive : boolean := false );
port (
CLOCK : in std_logic;
-- slot side
PHI2 : in std_logic;
DOTCLK : in std_logic;
RSTn : inout std_logic;
BUFFER_ENn : out std_logic;
SLOT_ADDR : inout unsigned(15 downto 0);
SLOT_DATA : inout std_logic_vector(7 downto 0);
RWn : inout std_logic;
BA : in std_logic;
DMAn : out std_logic;
EXROMn : inout std_logic;
GAMEn : inout std_logic;
ROMHn : in std_logic;
ROMLn : in std_logic;
IO1n : in std_logic;
IO2n : in std_logic;
IRQn : inout std_logic;
NMIn : inout std_logic;
-- memory
SDRAM_A : out std_logic_vector(12 downto 0); -- DRAM A
SDRAM_BA : out std_logic_vector(1 downto 0);
SDRAM_DQ : inout std_logic_vector(7 downto 0);
SDRAM_CSn : out std_logic;
SDRAM_RASn : out std_logic;
SDRAM_CASn : out std_logic;
SDRAM_WEn : out std_logic;
SDRAM_DQM : out std_logic;
SDRAM_CKE : out std_logic;
SDRAM_CLK : out std_logic;
-- PWM outputs (for audio)
PWM_OUT : out std_logic_vector(1 downto 0) := "11";
-- IEC bus
IEC_ATN : inout std_logic;
IEC_DATA : inout std_logic;
IEC_CLOCK : inout std_logic;
IEC_RESET : in std_logic;
IEC_SRQ_IN : inout std_logic;
DISK_ACTn : out std_logic; -- activity LED
CART_LEDn : out std_logic;
SDACT_LEDn : out std_logic;
MOTOR_LEDn : out std_logic;
-- Debug UART
UART_TXD : out std_logic;
UART_RXD : in std_logic;
-- SD Card Interface
SD_SSn : out std_logic;
SD_CLK : out std_logic;
SD_MOSI : out std_logic;
SD_MISO : in std_logic;
SD_CARDDETn : in std_logic;
SD_DATA : inout std_logic_vector(2 downto 1);
-- LED Interface
LED_CLK : out std_logic;
LED_DATA : out std_logic;
-- RTC Interface
RTC_CS : out std_logic;
RTC_SCK : out std_logic;
RTC_MOSI : out std_logic;
RTC_MISO : in std_logic;
-- Flash Interface
FLASH_CSn : out std_logic;
FLASH_SCK : out std_logic;
FLASH_MOSI : out std_logic;
FLASH_MISO : in std_logic;
-- USB Interface (ULPI)
ULPI_RESET : out std_logic;
ULPI_CLOCK : in std_logic;
ULPI_NXT : in std_logic;
ULPI_STP : out std_logic;
ULPI_DIR : in std_logic;
ULPI_DATA : inout std_logic_vector(7 downto 0);
-- Cassette Interface
CAS_MOTOR : in std_logic := '0';
CAS_SENSE : inout std_logic := 'Z';
CAS_READ : inout std_logic := 'Z';
CAS_WRITE : inout std_logic := 'Z';
-- Buttons
BUTTON : in std_logic_vector(2 downto 0));
end entity;
architecture structural of ultimate_mb_700a is
signal reset_in : std_logic;
signal dcm_lock : std_logic;
signal sys_clock : std_logic;
signal sys_reset : std_logic;
signal sys_clock_2x : std_logic;
-- signal sys_shifted : std_logic;
signal button_i : std_logic_vector(2 downto 0);
signal RSTn_out : std_logic;
-- miscellaneous interconnect
signal ulpi_reset_i : std_logic;
-- Slot
signal slot_addr_o : unsigned(15 downto 0);
signal slot_addr_tl : std_logic;
signal slot_addr_th : std_logic;
signal slot_data_o : std_logic_vector(7 downto 0);
signal slot_data_t : std_logic;
signal slot_rwn_o : std_logic;
signal irq_oc, nmi_oc, rst_oc, dma_oc, exrom_oc, game_oc : std_logic;
-- memory controller interconnect
signal memctrl_inhibit : std_logic;
signal mem_req : t_mem_req_32;
signal mem_resp : t_mem_resp_32;
-- IEC open drain
signal iec_atn_o : std_logic;
signal iec_data_o : std_logic;
signal iec_clock_o : std_logic;
signal iec_srq_o : std_logic;
-- Cassette
signal c2n_read_in : std_logic;
signal c2n_write_in : std_logic;
signal c2n_read_out : std_logic;
signal c2n_write_out : std_logic;
signal c2n_read_en : std_logic;
signal c2n_write_en : std_logic;
signal c2n_sense_in : std_logic;
signal c2n_sense_out : std_logic;
signal c2n_motor_in : std_logic;
signal c2n_motor_out : std_logic;
-- Parallel cable connection
signal drv_track_is_0 : std_logic;
signal drv_via1_port_a_o : std_logic_vector(7 downto 0);
signal drv_via1_port_a_i : std_logic_vector(7 downto 0);
signal drv_via1_port_a_t : std_logic_vector(7 downto 0);
signal drv_via1_ca2_o : std_logic;
signal drv_via1_ca2_i : std_logic;
signal drv_via1_ca2_t : std_logic;
signal drv_via1_cb1_o : std_logic;
signal drv_via1_cb1_i : std_logic;
signal drv_via1_cb1_t : std_logic;
-- Audio outputs
signal audio_left : signed(18 downto 0);
signal audio_right : signed(18 downto 0);
begin
reset_in <= '1' when BUTTON="000" else '0'; -- all 3 buttons pressed
button_i <= not BUTTON;
i_clkgen: entity work.s3a_clockgen
port map (
clk_50 => CLOCK,
reset_in => reset_in,
dcm_lock => dcm_lock,
sys_clock => sys_clock, -- 50 MHz
sys_reset => sys_reset,
sys_clock_2x => sys_clock_2x );
i_logic: entity work.ultimate_logic_32
generic map (
g_simulation => false,
g_clock_freq => 50_000_000,
g_baud_rate => 115_200,
g_icap => true,
g_uart => true,
g_drive_1541 => true,
g_drive_1541_2 => g_dual_drive,
g_mm_drive => false,
g_hardware_gcr => true,
g_ram_expansion => true,
g_extended_reu => false,
g_stereo_sid => not g_dual_drive,
g_8voices => false,
g_hardware_iec => true,
g_c2n_streamer => true,
g_c2n_recorder => g_dual_drive,
g_cartridge => true,
g_command_intf => true,
g_drive_sound => true,
g_rtc_chip => true,
g_rtc_timer => false,
g_usb_host2 => true,
g_spi_flash => true,
g_vic_copper => false,
g_video_overlay => false,
g_sdcard => true,
g_eeprom => g_eeprom,
g_sampler => not g_dual_drive,
g_acia => g_acia )
port map (
-- globals
sys_clock => sys_clock,
sys_reset => sys_reset,
ulpi_clock => ulpi_clock,
ulpi_reset => ulpi_reset_i,
-- slot side
BUFFER_ENn => BUFFER_ENn,
phi2_i => PHI2,
dotclk_i => DOTCLK,
rstn_i => RSTn,
rstn_o => RSTn_out,
slot_addr_o => slot_addr_o,
slot_addr_i => SLOT_ADDR,
slot_addr_tl=> slot_addr_tl,
slot_addr_th=> slot_addr_th,
slot_data_o => slot_data_o,
slot_data_i => SLOT_DATA,
slot_data_t => slot_data_t,
rwn_i => RWn,
rwn_o => slot_rwn_o,
exromn_i => EXROMn,
exromn_o => exrom_oc,
gamen_i => GAMEn,
gamen_o => game_oc,
irqn_i => IRQn,
irqn_o => irq_oc,
nmin_i => NMIn,
nmin_o => nmi_oc,
ba_i => BA,
dman_o => dma_oc,
romhn_i => ROMHn,
romln_i => ROMLn,
io1n_i => IO1n,
io2n_i => IO2n,
-- local bus side
mem_inhibit => memctrl_inhibit,
--memctrl_idle => memctrl_idle,
mem_req => mem_req,
mem_resp => mem_resp,
-- Audio outputs
audio_left => audio_left,
audio_right => audio_right,
-- IEC bus
iec_reset_i => IEC_RESET,
iec_atn_i => IEC_ATN,
iec_data_i => IEC_DATA,
iec_clock_i => IEC_CLOCK,
iec_srq_i => IEC_SRQ_IN,
iec_reset_o => open,
iec_atn_o => iec_atn_o,
iec_data_o => iec_data_o,
iec_clock_o => iec_clock_o,
iec_srq_o => iec_srq_o,
-- Parallel cable pins
drv_track_is_0 => drv_track_is_0,
drv_via1_port_a_o => drv_via1_port_a_o,
drv_via1_port_a_i => drv_via1_port_a_i,
drv_via1_port_a_t => drv_via1_port_a_t,
drv_via1_ca2_o => drv_via1_ca2_o,
drv_via1_ca2_i => drv_via1_ca2_i,
drv_via1_ca2_t => drv_via1_ca2_t,
drv_via1_cb1_o => drv_via1_cb1_o,
drv_via1_cb1_i => drv_via1_cb1_i,
drv_via1_cb1_t => drv_via1_cb1_t,
DISK_ACTn => DISK_ACTn, -- activity LED
CART_LEDn => CART_LEDn,
SDACT_LEDn => SDACT_LEDn,
MOTOR_LEDn => MOTOR_LEDn,
-- Debug UART
UART_TXD => UART_TXD,
UART_RXD => UART_RXD,
-- SD Card Interface
SD_SSn => SD_SSn,
SD_CLK => SD_CLK,
SD_MOSI => SD_MOSI,
SD_MISO => SD_MISO,
SD_CARDDETn => SD_CARDDETn,
SD_DATA => SD_DATA,
-- LED interface
LED_CLK => LED_CLK,
LED_DATA => LED_DATA,
-- RTC Interface
RTC_CS => RTC_CS,
RTC_SCK => RTC_SCK,
RTC_MOSI => RTC_MOSI,
RTC_MISO => RTC_MISO,
-- Flash Interface
FLASH_CSn => FLASH_CSn,
FLASH_SCK => FLASH_SCK,
FLASH_MOSI => FLASH_MOSI,
FLASH_MISO => FLASH_MISO,
-- USB Interface (ULPI)
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP,
ULPI_DIR => ULPI_DIR,
ULPI_DATA => ULPI_DATA,
-- Cassette Interface
c2n_read_in => c2n_read_in,
c2n_write_in => c2n_write_in,
c2n_read_out => c2n_read_out,
c2n_write_out => c2n_write_out,
c2n_read_en => c2n_read_en,
c2n_write_en => c2n_write_en,
c2n_sense_in => c2n_sense_in,
c2n_sense_out => c2n_sense_out,
c2n_motor_in => c2n_motor_in,
c2n_motor_out => c2n_motor_out,
-- Buttons
BUTTON => button_i );
-- Parallel cable not implemented. This is the way to stub it...
drv_via1_port_a_i(7 downto 1) <= drv_via1_port_a_o(7 downto 1) or not drv_via1_port_a_t(7 downto 1);
drv_via1_port_a_i(0) <= drv_track_is_0; -- for 1541C
drv_via1_ca2_i <= drv_via1_ca2_o or not drv_via1_ca2_t;
drv_via1_cb1_i <= drv_via1_cb1_o or not drv_via1_cb1_t;
irq_push: entity work.oc_pusher port map(clock => sys_clock, sig_in => irq_oc, oc_out => IRQn);
nmi_push: entity work.oc_pusher port map(clock => sys_clock, sig_in => nmi_oc, oc_out => NMIn);
dma_push: entity work.oc_pusher port map(clock => sys_clock, sig_in => dma_oc, oc_out => DMAn);
exr_push: entity work.oc_pusher port map(clock => sys_clock, sig_in => exrom_oc, oc_out => EXROMn);
gam_push: entity work.oc_pusher port map(clock => sys_clock, sig_in => game_oc, oc_out => GAMEn);
SLOT_ADDR(15 downto 12) <= slot_addr_o(15 downto 12) when slot_addr_th = '1' else (others => 'Z');
SLOT_ADDR(11 downto 00) <= slot_addr_o(11 downto 00) when slot_addr_tl = '1' else (others => 'Z');
SLOT_DATA <= slot_data_o when slot_data_t = '1' else (others => 'Z');
RWn <= slot_rwn_o when slot_addr_tl = '1' else 'Z';
RSTn <= '0' when RSTn_out = '0' else 'Z';
IEC_ATN <= '0' when iec_atn_o = '0' else 'Z';
IEC_DATA <= '0' when iec_data_o = '0' else 'Z';
IEC_CLOCK <= '0' when iec_clock_o = '0' else 'Z';
IEC_SRQ_IN <= '0' when iec_srq_o = '0' else 'Z';
-- Tape
c2n_motor_in <= CAS_MOTOR;
CAS_SENSE <= '0' when c2n_sense_out = '1' else 'Z';
c2n_sense_in <= not CAS_SENSE;
CAS_READ <= c2n_read_out when c2n_read_en = '1' else 'Z';
c2n_read_in <= CAS_READ;
CAS_WRITE <= c2n_write_out when c2n_write_en = '1' else 'Z';
c2n_write_in <= CAS_WRITE;
i_mem_ctrl: entity work.ext_mem_ctrl_v5
generic map (
g_simulation => false )
port map (
clock => sys_clock,
clk_2x => sys_clock_2x,
reset => sys_reset,
inhibit => memctrl_inhibit,
is_idle => open,
req => mem_req,
resp => mem_resp,
SDRAM_CLK => SDRAM_CLK,
SDRAM_CKE => SDRAM_CKE,
SDRAM_CSn => SDRAM_CSn,
SDRAM_RASn => SDRAM_RASn,
SDRAM_CASn => SDRAM_CASn,
SDRAM_WEn => SDRAM_WEn,
SDRAM_DQM => SDRAM_DQM,
SDRAM_BA => SDRAM_BA,
SDRAM_A => SDRAM_A,
SDRAM_DQ => SDRAM_DQ );
process(ulpi_clock, reset_in)
begin
if rising_edge(ulpi_clock) then
ulpi_reset_i <= sys_reset;
end if;
if reset_in='1' then
ulpi_reset_i <= '1';
end if;
end process;
ULPI_RESET <= ulpi_reset_i;
i_pwm0: entity work.sigma_delta_dac --delta_sigma_2to5
generic map (
g_left_shift => 0,
g_invert => true,
g_use_mid_only => false,
g_width => audio_left'length )
port map (
clock => sys_clock,
reset => sys_reset,
dac_in => audio_left,
dac_out => PWM_OUT(0) );
i_pwm1: entity work.sigma_delta_dac --delta_sigma_2to5
generic map (
g_left_shift => 0,
g_invert => true,
g_use_mid_only => false,
g_width => audio_right'length )
port map (
clock => sys_clock,
reset => sys_reset,
dac_in => audio_right,
dac_out => PWM_OUT(1) );
end structural;
| gpl-3.0 | 06639eb2602fd8105a2721de4f611ade | 0.502078 | 3.063243 | false | false | false | false |
markusC64/1541ultimate2 | fpga/cpu_unit/vhdl_source/cached_mblite.vhd | 1 | 3,012 | library ieee;
use ieee.std_logic_1164.all;
library mblite;
use mblite.config_Pkg.all;
use mblite.core_Pkg.all;
use mblite.std_Pkg.all;
library work;
entity cached_mblite is
generic (
g_icache : boolean := true;
g_dcache : boolean := true );
port (
clock : in std_logic;
reset : in std_logic;
disable_i : in std_logic := '0';
disable_d : in std_logic := '0';
invalidate : in std_logic := '0';
inv_addr : in std_logic_vector(31 downto 0);
dmem_o : out dmem_out_type;
dmem_i : in dmem_in_type;
imem_o : out dmem_out_type;
imem_i : in dmem_in_type;
irq_i : in std_logic;
irq_o : out std_logic );
end entity;
architecture structural of cached_mblite is
-- signals from processor to cache
signal cimem_o : imem_out_type;
signal cimem_i : imem_in_type;
signal cdmem_o : dmem_out_type;
signal cdmem_i : dmem_in_type;
BEGIN
core0 : core
port map (
imem_o => cimem_o,
imem_i => cimem_i,
dmem_o => cdmem_o,
dmem_i => cdmem_i,
int_i => irq_i,
int_o => irq_o,
rst_i => reset,
clk_i => clock );
r_icache: if g_icache generate
i_cache: entity work.dm_simple
generic map (
g_data_register => true,
g_mem_direct => true )
port map (
clock => clock,
reset => reset,
disable => disable_i,
dmem_i.adr_o => cimem_o.adr_o,
dmem_i.ena_o => cimem_o.ena_o,
dmem_i.sel_o => "0000",
dmem_i.we_o => '0',
dmem_i.dat_o => (others => '0'),
dmem_o.ena_i => cimem_i.ena_i,
dmem_o.dat_i => cimem_i.dat_i,
mem_o => imem_o,
mem_i => imem_i );
end generate;
r_no_icache: if not g_icache generate
imem_o.adr_o <= cimem_o.adr_o;
imem_o.ena_o <= cimem_o.ena_o;
imem_o.sel_o <= X"F";
imem_o.we_o <= '0';
imem_o.dat_o <= (others => '0');
cimem_i.dat_i <= imem_i.dat_i;
cimem_i.ena_i <= imem_i.ena_i;
end generate;
r_dcache: if g_dcache generate
d_cache: entity work.dm_with_invalidate
-- generic map (
-- g_data_register => true,
-- g_mem_direct => true )
port map (
clock => clock,
reset => reset,
disable => disable_d,
invalidate => invalidate,
inv_addr => inv_addr,
dmem_i => cdmem_o,
dmem_o => cdmem_i,
mem_o => dmem_o,
mem_i => dmem_i );
end generate;
r_no_dcache: if not g_dcache generate
-- direct connection to outside world
dmem_o <= cdmem_o;
cdmem_i <= dmem_i;
end generate;
end architecture;
| gpl-3.0 | fb5b566faecf44a35b5e43e6ee0b9b53 | 0.472776 | 3.23871 | false | false | false | false |
markusC64/1541ultimate2 | fpga/altera/testbench/mem_io_tb.vhd | 1 | 3,233 | --------------------------------------------------------------------------------
-- Entity: mem_io_tb
-- Date:2016-07-17
-- Author: Gideon
--
-- Description: Testbench for altera io for ddr
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity mem_io_tb is
end mem_io_tb;
architecture arch of mem_io_tb is
signal ref_clock : std_logic := '0';
signal ref_reset : std_logic;
signal sys_clock : std_logic;
signal sys_reset : std_logic;
signal phasecounterselect : std_logic_vector(2 downto 0) := "000";
signal phasestep : std_logic := '0';
signal phaseupdown : std_logic := '0';
signal phasedone : std_logic := '0';
signal mem_clk_p : std_logic := 'Z';
signal addr_first : std_logic_vector(7 downto 0) := X"00";
signal addr_second : std_logic_vector(7 downto 0) := X"00";
signal wdata : std_logic_vector(15 downto 0) := X"0000";
signal wdata_oe : std_logic;
signal SDRAM_DQ : std_logic_vector(3 downto 0);
signal SDRAM_CLK : std_logic := '0';
signal count1, count2 : integer := 999;
begin
ref_clock <= not ref_clock after 10 ns; -- 20 ns cycle time
ref_reset <= '1', '0' after 100 ns;
i_mut: entity work.mem_io
port map(
ref_clock => ref_clock,
ref_reset => ref_reset,
sys_clock => sys_clock,
sys_reset => sys_reset,
phasecounterselect => phasecounterselect,
phasestep => phasestep,
phaseupdown => phaseupdown,
phasedone => phasedone,
addr_first => addr_first,
addr_second => addr_second,
wdata => wdata,
wdata_oe => wdata_oe,
mem_clk_p => mem_clk_p,
mem_dq => SDRAM_DQ
);
process(sys_clock)
variable i : integer := 16;
begin
if rising_edge(sys_clock) then
i := i - 1;
if i = 0 then
addr_first <= X"AB";
addr_second <= X"CD";
wdata <= X"4321";
wdata_oe <= '1';
else
addr_first <= X"00";
addr_second <= X"00";
wdata <= X"0000";
wdata_oe <= '0';
end if;
end if;
end process;
SDRAM_CLK <= transport mem_clk_p after 11.5 ns;
process(mem_clk_p)
variable delay : integer := 28;
begin
delay := delay - 1;
count2 <= delay;
end process;
process(SDRAM_CLK)
variable delay : integer := 26; -- 28
begin
delay := delay - 1;
count1 <= delay;
case delay is
when 0 =>
SDRAM_DQ <= X"2";
when -1 =>
SDRAM_DQ <= X"3";
when -2 =>
SDRAM_DQ <= X"4";
when -3 =>
SDRAM_DQ <= X"5";
when others =>
SDRAM_DQ <= "ZZZZ";
end case;
end process;
end arch;
| gpl-3.0 | 7825df307660d1fd62a9264c9dde04ab | 0.449118 | 4.031172 | false | false | false | false |
markusC64/1541ultimate2 | fpga/1541/vhdl_source/mm_drive_cpu.vhd | 1 | 30,583 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
use work.io_bus_pkg.all;
entity mm_drive_cpu is
generic (
g_disk_tag : std_logic_vector(7 downto 0) := X"03";
g_cpu_tag : std_logic_vector(7 downto 0) := X"02";
g_ram_base : unsigned(27 downto 0) := X"0060000" );
port (
clock : in std_logic;
falling : in std_logic;
rising : in std_logic;
reset : in std_logic;
tick_1kHz : in std_logic;
tick_4MHz : in std_logic;
-- Drive Type
drive_type : in natural range 0 to 2 := 0; -- 0 = 1541, 1 = 1571, 2 = 1581
-- serial bus pins
atn_o : out std_logic; -- open drain
atn_i : in std_logic;
clk_o : out std_logic; -- open drain
clk_i : in std_logic;
data_o : out std_logic; -- open drain
data_i : in std_logic;
fast_clk_o : out std_logic; -- open drain
fast_clk_i : in std_logic;
-- Parallel cable connection
par_data_o : out std_logic_vector(7 downto 0);
par_data_t : out std_logic_vector(7 downto 0);
par_data_i : in std_logic_vector(7 downto 0);
par_hsout_o : out std_logic;
par_hsout_t : out std_logic;
par_hsout_i : in std_logic;
par_hsin_o : out std_logic;
par_hsin_t : out std_logic;
par_hsin_i : in std_logic;
-- Debug port
debug_data : out std_logic_vector(31 downto 0);
debug_valid : out std_logic;
-- Configuration
extra_ram : in std_logic := '0';
-- memory interface
mem_req_cpu : out t_mem_req;
mem_resp_cpu : in t_mem_resp;
mem_req_disk : out t_mem_req;
mem_resp_disk : in t_mem_resp;
mem_busy : out std_logic;
-- I/O bus to access WD177x
io_req : in t_io_req;
io_resp : out t_io_resp;
io_irq : out std_logic;
-- Sound
motor_sound_on : out std_logic;
-- drive pins
power : in std_logic;
drive_address : in std_logic_vector(1 downto 0);
write_prot_n : in std_logic;
byte_ready : in std_logic;
sync : in std_logic;
rdy_n : in std_logic;
disk_change_n : in std_logic;
track_0 : in std_logic;
track : in unsigned(6 downto 0);
motor_on : out std_logic;
mode : out std_logic;
stepper_en : out std_logic;
step : out std_logic_vector(1 downto 0);
rate_ctrl : out std_logic_vector(1 downto 0);
side : out std_logic;
two_MHz : out std_logic;
drv_rdata : in std_logic_vector(7 downto 0);
drv_wdata : out std_logic_vector(7 downto 0);
power_led : out std_logic;
act_led : out std_logic );
end entity;
architecture structural of mm_drive_cpu is
signal so_n : std_logic;
signal cpu_write : std_logic;
signal cpu_wdata : std_logic_vector(7 downto 0);
signal cpu_rdata : std_logic_vector(7 downto 0);
signal cpu_addr : std_logic_vector(16 downto 0);
signal cpu_irqn : std_logic;
signal ext_rdata : std_logic_vector(7 downto 0) := X"00";
signal via1_data : std_logic_vector(7 downto 0);
signal via2_data : std_logic_vector(7 downto 0);
signal via1_wen : std_logic;
signal via1_ren : std_logic;
signal via2_wen : std_logic;
signal via2_ren : std_logic;
signal cia_data : std_logic_vector(7 downto 0);
signal cia_wen : std_logic;
signal cia_ren : std_logic;
signal wd_data : std_logic_vector(7 downto 0);
signal wd_wen : std_logic;
signal wd_ren : std_logic;
signal cia_port_a_o : std_logic_vector(7 downto 0);
signal cia_port_a_t : std_logic_vector(7 downto 0);
signal cia_port_b_o : std_logic_vector(7 downto 0);
signal cia_port_b_t : std_logic_vector(7 downto 0);
signal cia_sp_o : std_logic;
signal cia_sp_i : std_logic;
signal cia_sp_t : std_logic;
signal cia_cnt_o : std_logic;
signal cia_cnt_i : std_logic;
signal cia_cnt_t : std_logic;
signal cia_irq : std_logic;
signal cia_pc_o : std_logic;
signal cia_flag_i : std_logic;
signal via1_port_a_o : std_logic_vector(7 downto 0);
signal via1_port_a_t : std_logic_vector(7 downto 0);
signal via1_ca2_o : std_logic;
signal via1_ca2_t : std_logic;
signal via1_cb1_o : std_logic;
signal via1_cb1_t : std_logic;
signal via1_port_b_o : std_logic_vector(7 downto 0);
signal via1_port_b_t : std_logic_vector(7 downto 0);
signal via1_port_b_i : std_logic_vector(7 downto 0);
signal via1_ca1 : std_logic;
signal via1_cb2_o : std_logic;
signal via1_cb2_i : std_logic;
signal via1_cb2_t : std_logic;
signal via1_irq : std_logic;
signal via2_port_b_o : std_logic_vector(7 downto 0);
signal via2_port_b_t : std_logic_vector(7 downto 0);
signal via2_port_b_i : std_logic_vector(7 downto 0);
signal via2_ca2_o : std_logic;
signal via2_ca2_i : std_logic;
signal via2_ca2_t : std_logic;
signal via2_cb1_o : std_logic;
signal via2_cb1_i : std_logic;
signal via2_cb1_t : std_logic;
signal via2_cb2_o : std_logic;
signal via2_cb2_i : std_logic;
signal via2_cb2_t : std_logic;
signal via2_irq : std_logic;
-- Local signals
signal my_fast_data_out : std_logic;
signal fast_clk_o_i : std_logic;
signal cpu_clk_en : std_logic;
signal cpu_rising : std_logic;
type t_mem_state is (idle, newcycle, extcycle);
signal mem_state : t_mem_state;
signal ext_sel : std_logic;
-- "old" style signals
signal mem_request : std_logic;
signal mem_addr : unsigned(25 downto 0);
signal mem_rwn : std_logic;
signal mem_rack : std_logic;
signal mem_dack : std_logic;
signal mem_wdata : std_logic_vector(7 downto 0);
type t_drive_mode_bundle is record
-- address decode
via1_sel : std_logic;
via2_sel : std_logic;
wd_sel : std_logic;
cia_sel : std_logic;
open_sel : std_logic;
-- internal
cia_port_a_i : std_logic_vector(7 downto 0);
cia_port_b_i : std_logic_vector(7 downto 0);
cia_flag_i : std_logic;
via1_port_a_i : std_logic_vector(7 downto 0);
via1_cb1_i : std_logic;
via1_ca2_i : std_logic;
fast_ser_dir : std_logic;
soe : std_logic;
step : std_logic_vector(1 downto 0);
stepper_en : std_logic;
wd_stepper : std_logic;
-- Parallel cable
par_data_o : std_logic_vector(7 downto 0);
par_data_t : std_logic_vector(7 downto 0);
par_hsout_o : std_logic;
par_hsout_t : std_logic;
par_hsin_o : std_logic;
par_hsin_t : std_logic;
-- export
side : std_logic;
two_MHz : std_logic;
act_led : std_logic;
power_led : std_logic;
motor_on : std_logic;
motor_sound_on : std_logic;
clk_o : std_logic;
data_o : std_logic;
atn_o : std_logic;
end record;
type t_drive_mode_bundles is array(natural range <>) of t_drive_mode_bundle;
signal m : t_drive_mode_bundles(0 to 2);
signal mm : t_drive_mode_bundle;
begin
mem_req_cpu.request <= mem_request;
mem_req_cpu.address <= mem_addr;
mem_req_cpu.read_writen <= mem_rwn;
mem_req_cpu.data <= mem_wdata;
mem_req_cpu.tag <= g_cpu_tag;
mem_req_cpu.size <= "00"; -- 1 byte at a time
mem_rack <= '1' when mem_resp_cpu.rack_tag = g_cpu_tag else '0';
mem_dack <= '1' when mem_resp_cpu.dack_tag = g_cpu_tag else '0';
cpu: entity work.cpu6502(cycle_exact)
port map (
cpu_clk => clock,
cpu_clk_en => cpu_clk_en,
cpu_reset => reset,
cpu_write => cpu_write,
cpu_wdata => cpu_wdata,
cpu_rdata => cpu_rdata,
cpu_addr => cpu_addr,
IRQn => cpu_irqn, -- IRQ interrupt (level sensitive)
NMIn => '1',
SOn => so_n );
-- Generate an output stream to debug internal operation of 1541 CPU
process(clock)
begin
if rising_edge(clock) then
debug_valid <= '0';
if cpu_clk_en = '1' then
debug_data <= '0' & atn_i & data_i & clk_i & sync & so_n & cpu_irqn & not cpu_write & cpu_rdata & cpu_addr(15 downto 0);
debug_valid <= '1';
if cpu_write = '1' then
debug_data(23 downto 16) <= cpu_wdata;
end if;
end if;
end if;
end process;
via1: entity work.via6522
port map (
clock => clock,
falling => cpu_clk_en,
rising => cpu_rising,
reset => reset,
addr => cpu_addr(3 downto 0),
wen => via1_wen,
ren => via1_ren,
data_in => cpu_wdata,
data_out => via1_data,
-- pio --
port_a_o => via1_port_a_o,
port_a_t => via1_port_a_t,
port_a_i => mm.via1_port_a_i,
port_b_o => via1_port_b_o,
port_b_t => via1_port_b_t,
port_b_i => via1_port_b_i,
-- handshake pins
ca1_i => via1_ca1,
ca2_o => via1_ca2_o,
ca2_i => mm.via1_ca2_i,
ca2_t => via1_ca2_t,
cb1_o => via1_cb1_o,
cb1_i => mm.via1_cb1_i,
cb1_t => via1_cb1_t,
cb2_o => via1_cb2_o,
cb2_i => via1_cb2_i, -- not used
cb2_t => via1_cb2_t,
irq => via1_irq );
via2: entity work.via6522
port map (
clock => clock,
falling => cpu_clk_en,
rising => cpu_rising,
reset => reset,
addr => cpu_addr(3 downto 0),
wen => via2_wen,
ren => via2_ren,
data_in => cpu_wdata,
data_out => via2_data,
-- pio --
port_a_o => drv_wdata,
port_a_t => open,
port_a_i => drv_rdata,
port_b_o => via2_port_b_o,
port_b_t => via2_port_b_t,
port_b_i => via2_port_b_i,
-- handshake pins
ca1_i => so_n,
ca2_o => via2_ca2_o,
ca2_i => via2_ca2_i, -- used as output (SOE)
ca2_t => via2_ca2_t,
cb1_o => via2_cb1_o,
cb1_i => via2_cb1_i, -- not used
cb1_t => via2_cb1_t,
cb2_o => via2_cb2_o,
cb2_i => via2_cb2_i, -- used as output (MODE)
cb2_t => via2_cb2_t,
irq => via2_irq );
i_cia1: entity work.cia_registers
generic map (
g_report => false,
g_unit_name => "CIA_1581" )
port map (
clock => clock,
falling => falling,
reset => reset,
tod_pin => '1', -- depends on jumper
addr => unsigned(cpu_addr(3 downto 0)),
data_in => cpu_wdata,
wen => cia_wen,
ren => cia_ren,
data_out => cia_data,
-- pio --
port_a_o => cia_port_a_o, -- unused
port_a_t => cia_port_a_t,
port_a_i => mm.cia_port_a_i,
port_b_o => cia_port_b_o, -- unused
port_b_t => cia_port_b_t,
port_b_i => mm.cia_port_b_i,
-- serial pin
sp_o => cia_sp_o, -- Burst mode IEC data
sp_i => cia_sp_i,
sp_t => cia_sp_t,
cnt_i => cia_cnt_i, -- Burst mode IEC clock
cnt_o => cia_cnt_o,
cnt_t => cia_cnt_t,
pc_o => cia_pc_o,
flag_i => mm.cia_flag_i,
irq => cia_irq );
cpu_irqn <= not(via1_irq or via2_irq or cia_irq);
-- Floppy Controller
i_wd177x: entity work.wd177x
generic map (
g_tag => g_disk_tag
)
port map(
clock => clock,
clock_en => cpu_clk_en,
reset => reset,
tick_1kHz => tick_1kHz,
tick_4MHz => tick_4MHz,
addr => unsigned(cpu_addr(1 downto 0)),
wen => wd_wen,
ren => wd_ren,
wdata => cpu_wdata,
rdata => wd_data,
motor_en => mm.motor_sound_on,
stepper_en => mm.wd_stepper,
cur_track => track,
step => m(2).step,
mem_req => mem_req_disk,
mem_resp => mem_resp_disk,
io_req => io_req,
io_resp => io_resp,
io_irq => io_irq
);
cpu_clk_en <= falling;
cpu_rising <= rising;
mem_busy <= '0' when mem_state = idle else '1';
-- Fetch ROM / RAM byte
process(clock)
begin
if rising_edge(clock) then
mem_addr(25 downto 16) <= g_ram_base(25 downto 16);
case mem_state is
when idle =>
if cpu_clk_en = '1' then
mem_state <= newcycle;
end if;
when newcycle => -- we have a new address now
mem_addr(15 downto 0) <= unsigned(cpu_addr(15 downto 0));
if cpu_addr(15) = '1' then -- ROM Area, which is not overridden as RAM
if cpu_write = '0' then
mem_request <= '1';
mem_state <= extcycle;
else -- writing to rom -> ignore
mem_state <= idle;
end if;
elsif ext_sel = '1' then -- RAM ONLY!
if extra_ram = '0' then
if (drive_type = 0) or (drive_type = 1) then
mem_addr(14 downto 11) <= "0000"; -- 2K RAM
else
mem_addr(14 downto 13) <= "00"; -- 8K RAM
end if;
end if;
mem_request <= '1';
mem_state <= extcycle;
else
mem_state <= idle;
end if;
when extcycle =>
if mem_rack='1' then
mem_request <= '0';
if cpu_write='1' then
mem_state <= idle;
end if;
end if;
if mem_dack='1' and cpu_write='0' then -- only for reads
ext_rdata <= mem_resp_cpu.data;
mem_state <= idle;
end if;
when others =>
null;
end case;
if reset='1' then
mem_request <= '0';
mem_state <= idle;
end if;
end if;
end process;
mem_rwn <= not cpu_write;
mem_wdata <= cpu_wdata;
-- Select drive type
mm <= m(drive_type);
-- True for all drives
via1_ren <= mm.via1_sel and not cpu_write;
via2_ren <= mm.via2_sel and not cpu_write;
cia_ren <= mm.cia_sel and not cpu_write;
wd_ren <= mm.wd_sel and not cpu_write;
via1_wen <= mm.via1_sel and cpu_write;
via2_wen <= mm.via2_sel and cpu_write;
cia_wen <= mm.cia_sel and cpu_write;
wd_wen <= mm.wd_sel and cpu_write;
-- read data muxing
process(mm.via1_sel, mm.via2_sel, mm.cia_sel, mm.wd_sel, ext_rdata, via1_data, via2_data, cia_data, wd_data)
variable rdata : std_logic_vector(7 downto 0);
begin
ext_sel <= '0';
rdata := X"FF";
if mm.via1_sel = '1' then rdata := rdata and via1_data; end if;
if mm.via2_sel = '1' then rdata := rdata and via2_data; end if;
if mm.cia_sel = '1' then rdata := rdata and cia_data; end if;
if mm.wd_sel = '1' then rdata := rdata and wd_data; end if;
-- "else"
if mm.via1_sel = '0' and mm.via2_sel = '0' and mm.cia_sel = '0' and mm.wd_sel = '0' and mm.open_sel = '0' then
rdata := rdata and ext_rdata;
ext_sel <= '1';
end if;
cpu_rdata <= rdata;
end process;
-- DRIVE SPECIFICS
-- Address decoding 1541
m(0).via1_sel <= '1' when cpu_addr(12 downto 10)="110" and cpu_addr(15)='0' and (extra_ram='0' or cpu_addr(14 downto 13)="00") else '0';
m(0).via2_sel <= '1' when cpu_addr(12 downto 10)="111" and cpu_addr(15)='0' and (extra_ram='0' or cpu_addr(14 downto 13)="00") else '0';
m(0).open_sel <= '1' when (cpu_addr(12) xor cpu_addr(11)) = '1' and cpu_addr(15) = '0' and extra_ram = '0' else '0';
m(0).cia_sel <= '0';
m(0).wd_sel <= '0';
-- Address decoding 1571
m(1).via1_sel <= '1' when cpu_addr(15 downto 10)="000110" else '0';
m(1).via2_sel <= '1' when cpu_addr(15 downto 10)="000111" else '0';
m(1).open_sel <= '1' when (cpu_addr(15 downto 11)="00001" or cpu_addr(15 downto 11) = "00010") and extra_ram = '0' else '0';
m(1).cia_sel <= '1' when cpu_addr(15 downto 14)="01" else '0';
m(1).wd_sel <= '1' when cpu_addr(15 downto 13)="001" else '0';
-- Address decoding 1581
m(2).via1_sel <= '0';
m(2).via2_sel <= '0';
m(2).open_sel <= '1' when cpu_addr(15 downto 13)="001" and extra_ram = '0' else '0'; -- 2000
m(2).cia_sel <= '1' when cpu_addr(15 downto 13)="010" else '0'; -- 4000
m(2).wd_sel <= '1' when cpu_addr(15 downto 13)="011" else '0'; -- 6000
-- Control signals 1541
m(0).side <= '0';
m(0).two_MHz <= '0';
m(0).fast_ser_dir <= '0'; -- by setting this to input, the fast_clk_o is never driven, and because the CIA is never
-- selected, receiving fast_clk_i will never cause issues
m(0).soe <= via2_ca2_i;
m(0).cia_port_a_i <= cia_port_a_o or not cia_port_a_t; -- don't care
m(0).cia_port_b_i <= cia_port_b_o or not cia_port_b_t; -- don't care
m(0).cia_flag_i <= '1';
m(0).power_led <= '1';
-- Control signals 1571
m(1).side <= m(1).via1_port_a_i(2);
m(1).two_MHz <= m(1).via1_port_a_i(5);
m(1).fast_ser_dir <= m(1).via1_port_a_i(1);
m(1).soe <= via2_ca2_i;
m(1).cia_port_a_i <= cia_port_a_o or not cia_port_a_t; -- CIA ports are not used
-- m(1).cia_port_b_i <= cia_port_b_o or not cia_port_b_t; -- CIA ports are not used
m(1).power_led <= '1';
-- Control signals 1581
m(2).side <= m(2).cia_port_a_i(0);
m(2).two_MHz <= '1';
m(2).fast_ser_dir <= m(2).cia_port_b_i(5);
m(2).soe <= '0';
-----------------------------------------
-- 1581 section
-----------------------------------------
b_1581: block
signal atn_ack : std_logic;
signal my_data_out : std_logic;
signal clock_out : std_logic;
begin
m(2).cia_port_b_i(7) <= not atn_i; -- assume that this signal (from 74LS14) wins
m(2).cia_port_b_i(6) <= (cia_port_b_o(6) or not cia_port_b_t(6)) and write_prot_n;
m(2).cia_port_b_i(5) <= (cia_port_b_o(5) or not cia_port_b_t(5));
m(2).cia_port_b_i(4) <= (cia_port_b_o(4) or not cia_port_b_t(4));
m(2).cia_port_b_i(3) <= (cia_port_b_o(3) or not cia_port_b_t(3));
m(2).cia_port_b_i(2) <= not clk_i; -- assume that this signal (from 74LS14) wins
m(2).cia_port_b_i(1) <= (cia_port_b_o(1) or not cia_port_b_t(1));
m(2).cia_port_b_i(0) <= not data_i;
m(2).cia_port_a_i(7) <= (cia_port_a_o(7) or not cia_port_a_t(7)) and disk_change_n;
m(2).cia_port_a_i(6) <= (cia_port_a_o(6) or not cia_port_a_t(6));
m(2).cia_port_a_i(5) <= (cia_port_a_o(5) or not cia_port_a_t(5));
m(2).cia_port_a_i(4) <= (cia_port_a_o(4) or not cia_port_a_t(4)) and drive_address(1);
m(2).cia_port_a_i(3) <= (cia_port_a_o(3) or not cia_port_a_t(3)) and drive_address(0);
m(2).cia_port_a_i(2) <= (cia_port_a_o(2) or not cia_port_a_t(2));
m(2).cia_port_a_i(1) <= (cia_port_a_o(1) or not cia_port_a_t(1)) and rdy_n;
m(2).cia_port_a_i(0) <= (cia_port_a_o(0) or not cia_port_a_t(0));
m(2).cia_flag_i <= atn_i; -- active low atn signal
m(2).data_o <= not my_data_out and not (atn_ack and not atn_i) and my_fast_data_out;
m(2).clk_o <= not clock_out;
m(2).atn_o <= '1';
-- Parallel Cable not defined
m(2).par_data_o <= X"FF";
m(2).par_data_t <= X"00";
m(2).par_hsout_o <= '1';
m(2).par_hsout_t <= '0';
m(2).par_hsin_o <= '1';
m(2).par_hsin_t <= '0';
-- write_prot_n_i <= cia_port_b_i(6);
atn_ack <= m(2).cia_port_b_i(4);
clock_out <= m(2).cia_port_b_i(3);
my_data_out <= m(2).cia_port_b_i(1);
--disk_change_n_i <= cia_port_a_i(7);
m(2).act_led <= m(2).cia_port_a_i(6);
m(2).power_led <= m(2).cia_port_a_i(5);
--drive_address_i(1) <= cia_port_a_i(4);
--drive_address_i(0) <= cia_port_a_i(3);
m(2).motor_sound_on <= not m(2).cia_port_a_i(2);
--rdy_n_i <= cia_port_a_i(1);
--side_0_i <= cia_port_a_i(0);
end block;
-- correctly attach the VIA pins to the outside world
via1_ca1 <= not atn_i;
via1_cb2_i <= via1_cb2_o or not via1_cb2_t;
via2_cb1_i <= via2_cb1_o or not via2_cb1_t;
via2_cb2_i <= via2_cb2_o or not via2_cb2_t;
via2_ca2_i <= via2_ca2_o or not via2_ca2_t;
-- Via Port A is used in the 1541 for the parallel interface (SpeedDos / DolphinDos), but in the 1571 some of the pins are connected internally
m(0).via1_cb1_i <= par_hsin_i;
m(1).via1_cb1_i <= via1_cb1_o or not via1_cb1_t;
m(2).via1_cb1_i <= via1_cb1_o or not via1_cb1_t;
m(0).par_data_o <= via1_port_a_o;
m(0).par_data_t <= via1_port_a_t;
m(0).par_hsout_o <= via1_ca2_o;
m(0).par_hsout_t <= via1_ca2_t;
m(0).par_hsin_o <= via1_cb1_o;
m(0).par_hsin_t <= via1_cb1_t;
m(0).via1_port_a_i <= par_data_i;
m(1).via1_port_a_i(7) <= (via1_port_a_o(7) or not via1_port_a_t(7)) and so_n; -- Byte ready in schematic. Our byte_ready signal is not yet masked with so_e
m(1).via1_port_a_i(6) <= (via1_port_a_o(6) or not via1_port_a_t(6)); -- ATN OUT (not connected)
m(1).via1_port_a_i(5) <= (via1_port_a_o(5) or not via1_port_a_t(5)); -- 2 MHz mode
m(1).via1_port_a_i(4) <= (via1_port_a_o(4) or not via1_port_a_t(4));
m(1).via1_port_a_i(3) <= (via1_port_a_o(3) or not via1_port_a_t(3));
m(1).via1_port_a_i(2) <= (via1_port_a_o(2) or not via1_port_a_t(2)); -- SIDE
m(1).via1_port_a_i(1) <= (via1_port_a_o(1) or not via1_port_a_t(1)); -- SER_DIR
m(1).via1_port_a_i(0) <= not track_0; -- assuming that the LS14 always wins
m(2).via1_port_a_i <= X"FF"; -- Don't care.
m(0).via1_ca2_i <= par_hsout_i;
m(1).via1_ca2_i <= write_prot_n; -- only in 1571
m(2).via1_ca2_i <= '1';
-- Do the same for VIA 2. Port A should read the pin, Port B reads the output internally, so for port B only actual input signals should be connected
via2_port_b_i(7) <= sync;
via2_port_b_i(6) <= '1'; --Density
via2_port_b_i(5) <= '1'; --Density
via2_port_b_i(4) <= write_prot_n;
via2_port_b_i(3) <= '1'; -- LED
via2_port_b_i(2) <= '1'; -- Motor
via2_port_b_i(1) <= '1'; -- Step
via2_port_b_i(0) <= '1'; -- Step
b1541_1571: block
signal atn_ack : std_logic;
signal my_clk_out : std_logic;
signal my_data_out : std_logic;
begin
atn_ack <= via1_port_b_o(4) or not via1_port_b_t(4);
my_data_out <= via1_port_b_o(1) or not via1_port_b_t(1);
my_clk_out <= via1_port_b_o(3) or not via1_port_b_t(3);
-- Serial bus pins 1541
m(0).data_o <= not my_data_out and (not (atn_ack xor (not atn_i)));
m(0).clk_o <= not my_clk_out;
m(0).atn_o <= '1';
-- Serial bus pins 1571
m(1).data_o <= not my_data_out and my_fast_data_out and (not (atn_ack xor (not atn_i)));
m(1).clk_o <= not my_clk_out;
m(1).atn_o <= '1';
-- Because Port B reads its own output when set to output, we do not need to consider the direction here
via1_port_b_i(7) <= not atn_i;
via1_port_b_i(6) <= drive_address(1); -- drive select
via1_port_b_i(5) <= drive_address(0); -- drive select;
via1_port_b_i(4) <= '1'; -- atn a - PUP
via1_port_b_i(3) <= '1'; -- clock out - PUP
via1_port_b_i(2) <= not (clk_i and not my_clk_out);
via1_port_b_i(1) <= '1'; -- data out - PUP
via1_port_b_i(0) <= not (data_i and not my_data_out and (not (atn_ack xor (not atn_i))));
-- Parallel Cable connects to 6526 port B on a 1571
m(1).cia_port_b_i <= par_data_i;
m(1).cia_flag_i <= par_hsin_i;
m(1).par_data_o <= cia_port_b_o;
m(1).par_data_t <= cia_port_b_t;
m(1).par_hsout_o <= cia_pc_o;
m(1).par_hsout_t <= '1'; -- PC is always output
m(1).par_hsin_o <= '1';
m(1).par_hsin_t <= '0'; -- FLAG is always input
end block;
m(0).act_led <= (via2_port_b_o(3) or not via2_port_b_t(3));
m(1).act_led <= (via2_port_b_o(3) or not via2_port_b_t(3));
m(0).motor_on <= (via2_port_b_o(2) or not via2_port_b_t(2));
m(1).motor_on <= (via2_port_b_o(2) or not via2_port_b_t(2));
m(2).motor_on <= '0'; -- disable memory access to GCR memory
m(0).motor_sound_on <= m(0).motor_on;
m(1).motor_sound_on <= m(1).motor_on;
m(0).step(0) <= via2_port_b_o(0) or not via2_port_b_t(0);
m(0).step(1) <= via2_port_b_o(1) or not via2_port_b_t(1);
m(1).step(0) <= via2_port_b_o(0) or not via2_port_b_t(0);
m(1).step(1) <= via2_port_b_o(1) or not via2_port_b_t(1);
m(0).wd_stepper <= '0';
m(1).wd_stepper <= '0';
m(2).wd_stepper <= '1';
m(0).stepper_en <= m(0).motor_on;
m(1).stepper_en <= m(1).motor_on;
m(2).stepper_en <= '1';
mode <= via2_cb2_i; -- don't care for 1581
rate_ctrl(0) <= via2_port_b_o(5) or not via2_port_b_t(5); -- don't care for 1581
rate_ctrl(1) <= via2_port_b_o(6) or not via2_port_b_t(6); -- don't care for 1581
so_n <= byte_ready or not mm.soe; -- soe will be '0' for 1581
-- This applies to 1571 and 1581
-- my_fast_data_out and fast_clk_o will be '1' for 1541, because fast_ser_dir is defined as '0' for 1541.
my_fast_data_out <= (cia_sp_o or not cia_sp_t) or not mm.fast_ser_dir; -- active low!
cia_sp_i <= (cia_sp_o or not cia_sp_t) when mm.fast_ser_dir = '1' else
data_i;
fast_clk_o_i <= (cia_cnt_o or not cia_cnt_t) or not mm.fast_ser_dir; -- active low!
cia_cnt_i <= (cia_cnt_o or not cia_cnt_t) when mm.fast_ser_dir = '1' else -- output
fast_clk_i; -- assume that 74LS241 wins
-- Export Inside drive
stepper_en <= mm.stepper_en;
step <= mm.step;
side <= mm.side;
two_MHz <= mm.two_MHz;
-- Export to outside world
motor_sound_on <= power and mm.motor_sound_on; -- internally active high, externally active high
motor_on <= power and mm.motor_on; -- internally active high, externally active high
power_led <= not (power and mm.power_led); -- internally active high, externally active low
act_led <= not (power and mm.act_led); -- internally active high, externally active low
clk_o <= not power or mm.clk_o; -- internally active low, externally active low
data_o <= not power or mm.data_o; -- internally active low, externally active low
atn_o <= not power or mm.atn_o; -- internally active low, externally active low
fast_clk_o <= not power or fast_clk_o_i; -- internally active low, externally active low
-- Parallel cable out
par_data_o <= mm.par_data_o;
par_data_t <= mm.par_data_t;
par_hsout_o <= mm.par_hsout_o;
par_hsout_t <= mm.par_hsout_t;
par_hsin_o <= mm.par_hsin_o;
par_hsin_t <= mm.par_hsin_t;
end architecture;
| gpl-3.0 | 164a60c1e56ffc444420221da17f9ff6 | 0.472452 | 2.994517 | false | false | false | false |
markusC64/1541ultimate2 | fpga/6502n/vhdl_source/proc_core.vhd | 1 | 8,101 | library ieee;
use ieee.std_logic_1164.all;
library work;
use work.pkg_6502_defs.all;
entity proc_core is
generic (
vector_page : std_logic_vector(15 downto 4) := X"FFF";
support_bcd : boolean := true );
port(
clock : in std_logic;
clock_en : in std_logic := '1';
reset : in std_logic;
ready : in std_logic := '1';
irq_n : in std_logic := '1';
nmi_n : in std_logic := '1';
so_n : in std_logic := '1';
carry : out std_logic;
sync_out : out std_logic;
interrupt_ack: out std_logic;
pc_out : out std_logic_vector(15 downto 0);
addr_out : out std_logic_vector(16 downto 0);
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
read_write_n : out std_logic );
end proc_core;
architecture structural of proc_core is
signal index_carry : std_logic;
signal pc_carry : std_logic;
signal branch_taken : boolean;
signal i_reg : std_logic_vector(7 downto 0);
signal d_reg : std_logic_vector(7 downto 0);
signal a_reg : std_logic_vector(7 downto 0);
signal x_reg : std_logic_vector(7 downto 0);
signal y_reg : std_logic_vector(7 downto 0);
signal s_reg : std_logic_vector(7 downto 0);
signal p_reg : std_logic_vector(7 downto 0);
signal latch_dreg : std_logic;
signal reg_update : std_logic;
signal flags_update : std_logic;
signal copy_d2p : std_logic;
signal sync : std_logic;
signal rwn : std_logic;
signal a_mux : t_amux;
signal pc_oper : t_pc_oper;
signal s_oper : t_sp_oper;
signal adl_oper : t_adl_oper;
signal adh_oper : t_adh_oper;
signal dout_mux : t_dout_mux;
signal alu_out : std_logic_vector(7 downto 0);
signal impl_out : std_logic_vector(7 downto 0);
signal mem_out : std_logic_vector(7 downto 0);
signal mem_n : std_logic;
signal mem_z : std_logic;
signal mem_c : std_logic;
signal set_a : std_logic;
signal set_x : std_logic;
signal set_y : std_logic;
signal set_s : std_logic;
signal vect_addr : std_logic_vector(3 downto 0);
signal interrupt : std_logic;
signal vectoring : std_logic;
signal nmi_done : std_logic;
signal set_i_flag : std_logic;
signal vect_sel : std_logic_vector(2 downto 1);
signal flags_imm : std_logic;
signal new_flags : std_logic_vector(7 downto 0);
signal n_out : std_logic;
signal v_out : std_logic;
signal c_out : std_logic;
signal z_out : std_logic;
signal d_out : std_logic;
signal i_out : std_logic;
signal a16 : std_logic;
attribute keep : string;
attribute keep of interrupt : signal is "true";
begin
carry <= p_reg(0);
new_flags(7) <= n_out;
new_flags(6) <= v_out;
new_flags(5) <= '1';
new_flags(4) <= p_reg(4);
new_flags(3) <= d_out;
new_flags(2) <= i_out;
new_flags(1) <= z_out;
new_flags(0) <= c_out;
ctrl: entity work.proc_control
port map (
clock => clock,
clock_en => clock_en,
ready => ready,
reset => reset,
interrupt => interrupt,
vectoring => vectoring,
taking_intr => interrupt_ack,
vect_sel => vect_sel,
nmi_done => nmi_done,
set_i_flag => set_i_flag,
vect_addr => vect_addr,
i_reg => i_reg,
index_carry => index_carry,
pc_carry => pc_carry,
branch_taken => branch_taken,
sync => sync,
latch_dreg => latch_dreg,
reg_update => reg_update,
flags_update => flags_update,
copy_d2p => copy_d2p,
a16 => a16,
rwn => rwn,
a_mux => a_mux,
dout_mux => dout_mux,
pc_oper => pc_oper,
s_oper => s_oper,
adl_oper => adl_oper,
adh_oper => adh_oper );
oper: entity work.data_oper
generic map (
support_bcd => support_bcd )
port map (
inst => i_reg,
n_in => p_reg(7),
v_in => p_reg(6),
z_in => p_reg(1),
c_in => p_reg(0),
d_in => p_reg(3),
i_in => p_reg(2),
data_in => d_reg,
a_reg => a_reg,
x_reg => x_reg,
y_reg => y_reg,
s_reg => s_reg,
alu_out => alu_out,
mem_out => mem_out,
mem_c => mem_c,
mem_z => mem_z,
mem_n => mem_n,
impl_out => impl_out,
set_a => set_a,
set_x => set_x,
set_y => set_y,
set_s => set_s,
flags_imm => flags_imm,
n_out => n_out,
v_out => v_out,
z_out => z_out,
c_out => c_out,
d_out => d_out,
i_out => i_out );
regs: entity work.proc_registers
generic map (
vector_page => vector_page )
port map (
clock => clock,
clock_en => clock_en,
ready => ready,
reset => reset,
-- package pins
data_in => data_in,
data_out => data_out,
so_n => so_n,
-- data from "data_oper"
alu_data => alu_out,
mem_data => mem_out,
mem_c => mem_c,
mem_z => mem_z,
mem_n => mem_n,
new_flags => new_flags,
flags_imm => flags_imm,
-- from implied handler
set_a => set_a,
set_x => set_x,
set_y => set_y,
set_s => set_s,
set_data => impl_out,
-- from interrupt controller
vect_addr => vect_addr,
-- from processor state machine and decoder
sync => sync,
rwn => rwn,
latch_dreg => latch_dreg,
set_i_flag => set_i_flag,
vectoring => vectoring,
reg_update => reg_update,
flags_update => flags_update,
copy_d2p => copy_d2p,
a_mux => a_mux,
dout_mux => dout_mux,
pc_oper => pc_oper,
s_oper => s_oper,
adl_oper => adl_oper,
adh_oper => adh_oper,
-- outputs to processor state machine
i_reg => i_reg,
index_carry => index_carry,
pc_carry => pc_carry,
branch_taken => branch_taken,
-- register outputs
addr_out => addr_out(15 downto 0),
d_reg => d_reg,
a_reg => a_reg,
x_reg => x_reg,
y_reg => y_reg,
s_reg => s_reg,
p_reg => p_reg,
pc_out => pc_out );
intr: entity work.proc_interrupt
port map (
clock => clock,
clock_en => clock_en,
reset => reset,
irq_n => irq_n,
nmi_n => nmi_n,
i_flag => p_reg(2),
interrupt => interrupt,
nmi_done => nmi_done,
reset_done => set_i_flag,
vect_sel => vect_sel );
read_write_n <= rwn;
addr_out(16) <= a16;
sync_out <= sync;
end structural;
| gpl-3.0 | 87b14bd069dbc3d174cd8415e577c19d | 0.431799 | 3.532926 | false | false | false | false |
markusC64/1541ultimate2 | fpga/altera/dpram_sc.vhd | 1 | 4,174 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
entity dpram_sc is
generic (
g_width_bits : positive := 16;
g_depth_bits : positive := 9;
g_read_first_a : boolean := false;
g_read_first_b : boolean := false;
g_global_init : std_logic_vector := X"0000";
g_storage : string := "auto" -- can also be "block" or "distributed"
);
port (
clock : in std_logic;
a_address : in unsigned(g_depth_bits-1 downto 0);
a_rdata : out std_logic_vector(g_width_bits-1 downto 0);
a_wdata : in std_logic_vector(g_width_bits-1 downto 0) := (others => '0');
a_en : in std_logic := '1';
a_we : in std_logic := '0';
b_address : in unsigned(g_depth_bits-1 downto 0) := (others => '0');
b_rdata : out std_logic_vector(g_width_bits-1 downto 0);
b_wdata : in std_logic_vector(g_width_bits-1 downto 0) := (others => '0');
b_en : in std_logic := '1';
b_we : in std_logic := '0' );
end entity;
architecture altera of dpram_sc is
function string_select(a,b: string; s:boolean) return string is
begin
if s then
return a;
end if;
return b;
end function;
-- Error (14271): Illegal value NEW_DATA for port_b_read_during_write_mode parameter in WYSIWYG primitive "ram_block1a9" -- value must be new_data_no_nbe_read, new_data_with_nbe_read or old_data
constant a_new_data : string := string_select("OLD_DATA", "new_data_no_nbe_read", g_read_first_a);
constant b_new_data : string := string_select("OLD_DATA", "new_data_no_nbe_read", g_read_first_b);
signal wren_a : std_logic;
signal wren_b : std_logic;
begin
-- assert g_global_init = X"0000"
-- report "Output register initialization of BRAM is not supported for Altera"
-- severity failure;
assert not g_read_first_a report "Port A. Cyclone V does not support reading of old data while writing. Forcing new data to be read! Results may differ!" severity warning;
assert not g_read_first_b report "Port B. Cyclone V does not support reading of old data while writing. Forcing new data to be read! Results may differ!" severity warning;
altsyncram_component : altsyncram
GENERIC MAP (
address_reg_b => "CLOCK0",
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
indata_reg_b => "CLOCK0",
intended_device_family => "Cyclone IV E",
lpm_type => "altsyncram",
numwords_a => 2 ** g_depth_bits,
numwords_b => 2 ** g_depth_bits,
operation_mode => "BIDIR_DUAL_PORT",
outdata_aclr_a => "NONE",
outdata_aclr_b => "NONE",
outdata_reg_a => "UNREGISTERED",
outdata_reg_b => "UNREGISTERED",
power_up_uninitialized => "FALSE",
read_during_write_mode_mixed_ports => "dont_care", --"OLD_DATA",
read_during_write_mode_port_a => "new_data_no_nbe_read",
read_during_write_mode_port_b => "new_data_no_nbe_read",
widthad_a => g_depth_bits,
widthad_b => g_depth_bits,
width_a => g_width_bits,
width_b => g_width_bits,
width_byteena_a => 1,
width_byteena_b => 1,
wrcontrol_wraddress_reg_b => "CLOCK0"
)
PORT MAP (
address_a => std_logic_vector(a_address),
address_b => std_logic_vector(b_address),
clock0 => clock,
data_a => a_wdata,
data_b => b_wdata,
rden_a => a_en,
rden_b => b_en,
wren_a => wren_a,
wren_b => wren_b,
q_a => a_rdata,
q_b => b_rdata );
wren_a <= a_we and a_en;
wren_b <= b_we and b_en;
end architecture;
| gpl-3.0 | 5274be074d44c06eff8979b9c7c934f0 | 0.541926 | 3.461028 | false | false | false | false |
nussbrot/AdvPT | wb_test/test/wbs_test/tb/tb_wbs_test.vhd | 2 | 40,750 | -------------------------------------------------------------------------------
-- COPYRIGHT (c) SOLECTRIX GmbH, Germany, 2013 All rights reserved
--
-- The copyright to the document(s) herein is the property of SOLECTRIX GmbH
-- The document(s) may be used and/or copied only with the written permission
-- from SOLECTRIX GmbH or in accordance with the terms/conditions stipulated
-- in the agreement/contract under which the document(s) have been supplied
-------------------------------------------------------------------------------
-- Project :
-- File : tb_wbs_test.vhd
-- Created : 23.11.2016
-- Standard : VHDL 2008
-------------------------------------------------------------------------------
--*
--* @short wbs_test Testbench
--* TestBench for sxl wb generator (tcl)
--*
--* @author mgoertz
--* @date 23.11.2016
--* @internal
--/
-------------------------------------------------------------------------------
-- Modification history :
-- Date Author & Description
-- 23.11.2016 mgoertz: Created
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE ieee.math_real.ALL;
LIBRARY osvvm;
USE osvvm.RandomPkg.all;
LIBRARY vunit_lib;
CONTEXT vunit_lib.vunit_context;
LIBRARY fun_lib;
USE fun_lib.math_pkg.ALL;
LIBRARY sim_lib;
USE sim_lib.sim_pkg.ALL;
USE sim_lib.wbs_drv_pkg.ALL;
LIBRARY rtl_lib;
LIBRARY tb_lib;
USE STD.textio.ALL;
-------------------------------------------------------------------------------
ENTITY tb_wbs_test IS
GENERIC(
runner_cfg : runner_cfg_t;
g_system_clk : REAL := 150.0E6;
g_nr_of_writes : NATURAL := 10;
g_data_bits : POSITIVE := 32;
g_addr_bits : INTEGER := 16;
g_use_notify_wbs : BOOLEAN := FALSE);
BEGIN
-- to be checked ...
ASSERT g_addr_bits MOD 8 = 0
REPORT "g_addr_bits has to be a multiple of 4!"
SEVERITY FAILURE;
END ENTITY tb_wbs_test;
-------------------------------------------------------------------------------
ARCHITECTURE tb OF tb_wbs_test IS
-----------------------------------------------------------------------------
--
-----------------------------------------------------------------------------
SIGNAL clk : STD_LOGIC := '0';
--
SHARED VARIABLE sv_gen_rdm_writes_start : sim_lib.sim_pkg.shared_boolean;
SHARED VARIABLE sv_gen_rdm_writes_done : sim_lib.sim_pkg.shared_boolean;
--
SUBTYPE t_data_word IS STD_LOGIC_VECTOR(g_data_bits-1 DOWNTO 0);
PACKAGE array_pkg IS NEW sim_lib.array_pkg
GENERIC MAP (data_type => t_data_word);
SHARED VARIABLE sv_memory_array : array_pkg.t_array;
-----------------------------------------------------------------------------
-- Constants
-----------------------------------------------------------------------------
CONSTANT c_addr_read_write : INTEGER := 16#0000#;
CONSTANT c_addr_read_only : INTEGER := 16#0004#;
CONSTANT c_addr_write_only : INTEGER := 16#0008#;
CONSTANT c_addr_trigger : INTEGER := 16#000C#;
CONSTANT c_addr_enum : INTEGER := 16#0010#;
CONSTANT c_addr_notify_rw : INTEGER := 16#0014#;
CONSTANT c_addr_notify_ro : INTEGER := 16#0018#;
CONSTANT c_addr_notify_wo : INTEGER := 16#001C#;
CONSTANT c_addr_invalid : INTEGER := 16#0088#;
--
CONSTANT c_addr_invalid_slv : STD_LOGIC_VECTOR(g_addr_bits -1 DOWNTO 0) := std_logic_vector(to_unsigned(c_addr_invalid, g_addr_bits));
CONSTANT c_wb_sel_max : STD_LOGIC_VECTOR(g_data_bits/8-1 DOWNTO 0) := (OTHERS => '1');
CONSTANT c_wb_dat_max : STD_LOGIC_VECTOR(g_data_bits -1 DOWNTO 0) := (OTHERS => '1');
CONSTANT c_wb_we_write : STD_LOGIC := '1';
CONSTANT c_wb_we_read : STD_LOGIC := '0';
-----------------------------------------------------------------------------
-- Wishbone driver interface signals
-----------------------------------------------------------------------------
SIGNAL s_wbs_drv_out : t_wbs_drv_out(addr(g_addr_bits-1 DOWNTO 0),
data(g_data_bits-1 DOWNTO 0),
sel(g_data_bits/8-1 DOWNTO 0));
SIGNAL s_wbs_drv_in : t_wbs_drv_in(data(g_data_bits-1 DOWNTO 0));
-----------------------------------------------------------------------------
-- Custom registers Signals
-----------------------------------------------------------------------------
SIGNAL s_reg_read_write : STD_LOGIC_VECTOR(31 DOWNTO 0) := x"00000000";
SIGNAL s_reg_read_only : STD_LOGIC_VECTOR(31 DOWNTO 0) := x"00000000";
SIGNAL s_reg_write_only : STD_LOGIC_VECTOR(31 DOWNTO 0) := x"00000000";
SIGNAL s_reg_trigger : STD_LOGIC_VECTOR(31 DOWNTO 0) := x"00000000";
SIGNAL s_reg_enum : STD_LOGIC_VECTOR(31 DOWNTO 0) := x"80002000";
SIGNAL s_reg_notify_rw : STD_LOGIC_VECTOR(31 DOWNTO 0) := x"6F6F6F6F";
SIGNAL s_reg_notify_ro : STD_LOGIC_VECTOR(31 DOWNTO 0) := x"6F6F6F6F";
SIGNAL s_reg_notify_wo : STD_LOGIC_VECTOR(31 DOWNTO 0) := x"6F6F6F6F";
-----------------------------------------------------------------------------
-- Custom registers IO Signals
-----------------------------------------------------------------------------
SIGNAL s_o_rw_slice0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL s_o_rw_slice1 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL s_o_rw_bit : STD_LOGIC;
SIGNAL s_i_ro_slice0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL s_i_ro_slice1 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL s_i_ro_bit : STD_LOGIC;
SIGNAL s_o_wo_slice0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL s_o_wo_slice1 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL s_o_wo_bit : STD_LOGIC;
SIGNAL s_o_tr_slice0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL s_o_tr_slice1 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL s_o_tr_bit : STD_LOGIC;
SIGNAL s_o_en_bit : STD_LOGIC;
SIGNAL s_o_en_slice : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL s_o_no_rw_rw_bit : STD_LOGIC;
SIGNAL s_o_no_rw_rw_slice : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL s_i_no_rw_ro_bit : STD_LOGIC;
SIGNAL s_i_no_rw_ro_slice : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL s_o_no_rw_wo_bit : STD_LOGIC;
SIGNAL s_o_no_rw_wo_slice : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL s_o_no_rw_tr_bit : STD_LOGIC;
SIGNAL s_o_no_rw_tr_slice : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL s_o_notify_rw_trd : STD_LOGIC;
SIGNAL s_o_notify_rw_twr : STD_LOGIC;
SIGNAL s_o_no_ro_rw_bit : STD_LOGIC;
SIGNAL s_o_no_ro_rw_slice : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL s_i_no_ro_ro_bit : STD_LOGIC;
SIGNAL s_i_no_ro_ro_slice : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL s_o_no_ro_wo_bit : STD_LOGIC;
SIGNAL s_o_no_ro_wo_slice : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL s_o_no_ro_tr_bit : STD_LOGIC;
SIGNAL s_o_no_ro_tr_slice : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL s_o_notify_ro_trd : STD_LOGIC;
SIGNAL s_o_no_wo_rw_bit : STD_LOGIC;
SIGNAL s_o_no_wo_rw_slice : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL s_i_no_wo_ro_bit : STD_LOGIC;
SIGNAL s_i_no_wo_ro_slice : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL s_o_no_wo_wo_bit : STD_LOGIC;
SIGNAL s_o_no_wo_wo_slice : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL s_o_no_wo_tr_bit : STD_LOGIC;
SIGNAL s_o_no_wo_tr_slice : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL s_o_notify_wo_twr : STD_LOGIC;
-----------------------------------------------------------------------------
-- TB Signals
-----------------------------------------------------------------------------
SIGNAL s_golden : STD_LOGIC_VECTOR(g_data_bits-1 DOWNTO 0);
SIGNAL s_sample : STD_LOGIC_VECTOR(g_data_bits-1 DOWNTO 0);
-----------------------------------------------------------------------------
-- FUNCTIONs
-----------------------------------------------------------------------------
PROCEDURE wait_for(VARIABLE flag : INOUT sim_lib.sim_pkg.shared_boolean) IS
BEGIN
LOOP
WAIT UNTIL rising_edge(clk);
IF flag.get THEN
EXIT;
END IF;
END LOOP;
END PROCEDURE;
--
FUNCTION byte_2_word_addr(byte_addr : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
VARIABLE word_addr : STD_LOGIC_VECTOR(g_addr_bits-1 DOWNTO 0);
BEGIN
word_addr := byte_addr(byte_addr'HIGH DOWNTO ceil_log2(g_data_bits/8));
RETURN word_addr;
END FUNCTION;
-----------------------------------------------------------------------------
BEGIN
f_create_clock(clk, g_system_clk);
-----------------------------------------------------------------------------
-- MAIN
-----------------------------------------------------------------------------
main : PROCESS
--
VARIABLE v_app_done_flag : BOOLEAN := FALSE;
VARIABLE v_spi_done_flag : BOOLEAN := FALSE;
--
VARIABLE RndA : RandomPType;
VARIABLE v_byte_addr : STD_LOGIC_VECTOR(g_addr_bits-1 DOWNTO 0);
VARIABLE v_data : STD_LOGIC_VECTOR(g_data_bits-1 DOWNTO 0);
VARIABLE v_reset : STD_LOGIC_VECTOR(g_data_bits-1 DOWNTO 0);
VARIABLE v_mask : STD_LOGIC_VECTOR(g_data_bits-1 DOWNTO 0);
VARIABLE v_be : STD_LOGIC_VECTOR(g_data_bits/8-1 DOWNTO 0);
VARIABLE pass : BOOLEAN;
VARIABLE v_wb_result : t_wbs_drv_in(data(g_data_bits-1 DOWNTO 0));
-- generate random vector of length nr_bits
IMPURE FUNCTION f_gen_rdm_vec(nr_bits : POSITIVE) RETURN STD_LOGIC_VECTOR IS
VARIABLE v_return : STD_LOGIC_VECTOR(nr_bits-1 DOWNTO 0);
BEGIN
v_return := RndA.Randslv(0, NATURAL'HIGH , nr_bits);
RETURN v_return;
END FUNCTION;
-- signals or variables ...
VARIABLE v_sample : STD_LOGIC_VECTOR(g_data_bits-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE v_golden : STD_LOGIC_VECTOR(g_data_bits-1 DOWNTO 0) := (OTHERS => '0');
-----------------------------------------------------------------------------
-- MAIN process body
-----------------------------------------------------------------------------
BEGIN -- p_main
-- Initialize
test_runner_setup(runner, runner_cfg);
RndA.InitSeed(RndA'instance_name);
checker_init(display_format => verbose,
file_format => verbose_csv,
file_name => "vunit_out/log.csv");
-- VUINIT Main Loop
WHILE test_suite LOOP
-- wbs idle state for some time...
wbs_idle(s_wbs_drv_out);
-- no rst_n !!!
WAIT FOR 100 ns;
IF run("Test") THEN
-- Generate some random Tests for all registers
-- Check ReadWrite register
info("Checking Register: ReadWrite");
-- check reset value
-- TODO: adapt for each register!
v_byte_addr := std_logic_vector(to_unsigned(c_addr_read_write, v_byte_addr'length));
v_mask := x"FFFFFF08";
v_reset := x"00000000";
-- DONE
wbs_read_reg(v_byte_addr, v_sample, clk, s_wbs_drv_out, s_wbs_drv_in);
s_sample <= v_sample;
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
s_golden <= v_reset;
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
check_equal(s_sample, s_golden, "wrong register reset value!");
-- write LOOP
FOR i IN 0 TO g_nr_of_writes-1 LOOP
-- Genereate Random Data
-- TODO change register
v_data := f_gen_rdm_vec(s_reg_read_write'LENGTH);
-- DONE
s_golden <= v_data AND v_mask; -- AND mask for slices
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
-- Write to Wishbone
report "Write to Wishbone";
wbs_write_reg(v_byte_addr, v_data, clk, s_wbs_drv_out, s_wbs_drv_in);
-- use vunit check_equal check_api to
-- check register value
report "Read from Wishbone";
wbs_read_reg(v_byte_addr, v_sample, clk, s_wbs_drv_out, s_wbs_drv_in);
s_sample <= v_sample;
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
check_equal(s_sample, s_golden, "wrong register value read back");
report "Sampling register output pins";
-- check pin/vector value, combine slices
-- TODO: adapt for each register!
v_sample := (OTHERS => '0');
v_sample(31 DOWNTO 16) := s_o_rw_slice0;
v_sample(15 DOWNTO 8) := s_o_rw_slice1;
v_sample(3) := s_o_rw_bit;
s_sample <= v_sample;
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
-- DONE
check_equal(s_sample, s_golden, "wrong IO pin/vector value");
END LOOP; -- g_nr_of_writes
-- Check ReadOnly register
info("Checking Register: ReadOnly");
-- check reset value
-- this is only possible before first rising_edge of clk!
-- TODO! adapt for each register!
v_byte_addr := std_logic_vector(to_unsigned(c_addr_read_only, v_byte_addr'length));
v_mask := x"FFFFFF08";
v_reset := b"UUUU_UUUU_UUUU_UUUU_UUUU_UUUU_0000_U000"; -- if input pins are not driven, then undefined!
report "Read from Wishbone";
wbs_read_reg(v_byte_addr, v_sample, clk, s_wbs_drv_out, s_wbs_drv_in);
s_sample <= v_sample;
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
s_golden <= v_reset;
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
check_equal(s_sample, s_golden, "wrong register reset value!");v_reset := x"00000000";
-- after first rising_edge of clk register is set by IO pins
-- drive pin/vector values, combine slices
report "Driving IO inputs with reset value";
s_i_ro_slice0 <= v_reset(31 DOWNTO 16);
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
s_i_ro_slice1 <= v_reset(15 DOWNTO 8);
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
s_i_ro_bit <= v_reset(3);
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
-- DONE!
report "Read from Wishbone";
wbs_read_reg(v_byte_addr, v_sample, clk, s_wbs_drv_out, s_wbs_drv_in);
s_sample <= v_sample;
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
s_golden <= v_reset;
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
check_equal(s_sample, s_golden, "wrong register reset value!");
-- write LOOP
FOR i IN 0 TO g_nr_of_writes-1 LOOP
-- Genereate Random Data
-- TODO change register
v_data := f_gen_rdm_vec(s_reg_read_only'LENGTH);
-- DONE
s_golden <= v_data AND v_mask; -- AND mask for slices
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
-- drive pin/vector values, combine slices
-- TODO: adapt for each register!
report "Driving IO inputs with random value";
s_i_ro_slice0 <= v_data(31 DOWNTO 16);
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
s_i_ro_slice1 <= v_data(15 DOWNTO 8);
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
s_i_ro_bit <= v_data(3);
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
-- DONE
report "Read from Wishbone";
wbs_read_reg(v_byte_addr, v_sample, clk, s_wbs_drv_out, s_wbs_drv_in);
s_sample <= v_sample;
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
check_equal(s_sample, s_golden, "wrong register value read");
-- Write to Wishbone, check if register is really ro!
report "Write reset value to Wishbone";
wbs_write_reg(v_byte_addr, v_reset, clk, s_wbs_drv_out, s_wbs_drv_in);
-- use vunit check_equal check_api to
-- check register value, should not change for ro!
report "Read from Wishbone";
wbs_read_reg(v_byte_addr, v_sample, clk, s_wbs_drv_out, s_wbs_drv_in);
s_sample <= v_sample;
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
check_equal(s_sample, s_golden, "wrong register value read back");
END LOOP; -- g_nr_of_writes
-- Check WriteOnly register
-- seems as if the value is only stored for one clk cycle ...
-- no register ??? only a trigger! Not the expexted behavior...
-- ERROR reported! Fix will come...
info("Checking Register: WriteOnly");
-- check reset value, read should not work, bur pins...
-- TODO: adapt for each register!
v_byte_addr := std_logic_vector(to_unsigned(c_addr_write_only, v_byte_addr'length));
v_mask := x"FFFFFF08";
v_reset := x"00000000";
-- DONE
report "Sampling register output pins";
-- check pin/vector reset value, combine slices
-- TODO: adapt for each register!
v_sample := (OTHERS => '0');
v_sample(31 DOWNTO 16) := s_o_wo_slice0;
v_sample(15 DOWNTO 8) := s_o_wo_slice1;
v_sample(3) := s_o_wo_bit;
s_sample <= v_sample;
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
-- DONE
s_golden <= v_reset;
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
check_equal(s_sample, s_golden, "wrong IO pin/vector reset value");
-- check to read WriteOnly register, should fail!
--report "Read from Wishbone, expecting to fail...";
--wbs_read_reg(v_byte_addr, v_sample, clk, s_wbs_drv_out, s_wbs_drv_in);
--s_sample <= v_sample;
--WAIT FOR 0 ns; -- wait one Delta cycle to update signal
--IF (check_equal(s_sample, s_golden, "Expected: register read reset value not working!", level => info)) THEN
-- info("Read Reset value matches... This was not expected!");
--ELSE
-- info("Expected to be here.");
--END IF;
-- write LOOP
FOR i IN 0 TO g_nr_of_writes-1 LOOP
-- Genereate Random Data
-- TODO change register
v_data := f_gen_rdm_vec(s_reg_write_only'LENGTH);
-- DONE
s_golden <= v_data AND v_mask; -- AND mask for slices
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
-- Write to Wishbone
report "Write to Wishbone";
wbs_write_reg(v_byte_addr, v_data, clk, s_wbs_drv_out, s_wbs_drv_in);
-- use vunit check_equal check_api to
-- check register value
-- check pin/vector value, combine slices
-- TODO: adapt for each register!
WAIT FOR 1 ns; -- wait for 1 ns (one Delta cycle) for update of output signals
report "Sampling register output pins";
v_sample := (OTHERS => '0');
v_sample(31 DOWNTO 16) := s_o_wo_slice0;
v_sample(15 DOWNTO 8) := s_o_wo_slice1;
v_sample(3) := s_o_wo_bit;
s_sample <= v_sample;
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
-- DONE
check_equal(s_sample, s_golden, "wrong IO pin/vector value");
report "Read from Wishbone, expecting to fail...";
-- check to read WriteOnly register, should fail!
wbs_read_reg(v_byte_addr, v_sample, clk, s_wbs_drv_out, s_wbs_drv_in);
s_sample <= v_sample;
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
check_false( (s_sample=s_golden), "Not expected: register read value matching!");
report "Sampling register output pins again";
v_sample := (OTHERS => '0');
v_sample(31 DOWNTO 16) := s_o_wo_slice0;
v_sample(15 DOWNTO 8) := s_o_wo_slice1;
v_sample(3) := s_o_wo_bit;
s_sample <= v_sample;
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
-- DONE
check_equal(s_sample, s_golden, "wrong IO pin/vector value");
END LOOP; -- g_nr_of_writes
-- Check Trigger register
-- seems as if the value is only stored for one clk cycle ...
-- no register ??? only a trigger! Not the expexted behavior...
info("Checking Register: Trigger");
-- check reset value, read should not work, bur pins...
-- TODO: adapt for each register!
v_byte_addr := std_logic_vector(to_unsigned(c_addr_trigger, v_byte_addr'length));
v_mask := x"FFFFFF08";
v_reset := x"00000000";
-- DONE
report "Sampling register output pins";
-- check pin/vector reset value, combine slices
-- TODO: adapt for each register!
v_sample := (OTHERS => '0');
v_sample(31 DOWNTO 16) := s_o_tr_slice0;
v_sample(15 DOWNTO 8) := s_o_tr_slice1;
v_sample(3) := s_o_tr_bit;
s_sample <= v_sample;
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
-- DONE
s_golden <= v_reset;
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
check_equal(s_sample, s_golden, "wrong IO pin/vector reset value");
-- check to read WriteOnly register, should fail!
--report "Read from Wishbone, expecting to fail...";
--wbs_read_reg(v_byte_addr, v_sample, clk, s_wbs_drv_out, s_wbs_drv_in);
--s_sample <= v_sample;
--WAIT FOR 0 ns; -- wait one Delta cycle to update signal
--IF (check_equal(s_sample, s_golden, "Expected: register read reset value not working!", level => info)) THEN
-- info("Read Reset value matches... This was not expected!");
--ELSE
-- info("Expected to be here.");
--END IF;
-- write LOOP
FOR i IN 0 TO g_nr_of_writes-1 LOOP
-- Genereate Random Data
-- TODO change register
v_data := f_gen_rdm_vec(s_reg_trigger'LENGTH);
-- DONEv_data := f_gen_rdm_vec(s_reg_trigger'LENGTH);
s_golden <= v_data AND v_mask; -- AND mask for slices
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
-- Write to Wishbone
report "Write to Wishbone";
wbs_write_reg(v_byte_addr, v_data, clk, s_wbs_drv_out, s_wbs_drv_in);
-- use vunit check_equal check_api to
-- check register value
-- check pin/vector value, combine slices
-- TODO: adapt for each register!
WAIT FOR 1 ns; -- wait for 1 ns (one Delta cycle) for update of output signals
report "Sampling register output pins";
v_sample := (OTHERS => '0');
v_sample(31 DOWNTO 16) := s_o_tr_slice0;
v_sample(15 DOWNTO 8) := s_o_tr_slice1;
v_sample(3) := s_o_tr_bit;
s_sample <= v_sample;
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
-- DONE
check_equal(s_sample, s_golden, "wrong IO pin/vector value");
report "Read from Wishbone, expecting to fail...";
-- check to read WriteOnly register, should fail!
wbs_read_reg(v_byte_addr, v_sample, clk, s_wbs_drv_out, s_wbs_drv_in);
s_sample <= v_sample;
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
check_false( (s_sample=s_golden), "Not expected: register read value matching!");
report "Sampling register output pins again with reset value";
s_golden <= v_reset;
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
v_sample := (OTHERS => '0');
v_sample(31 DOWNTO 16) := s_o_tr_slice0;
v_sample(15 DOWNTO 8) := s_o_tr_slice1;
v_sample(3) := s_o_tr_bit;
s_sample <= v_sample;
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
-- DONE
check_equal(s_sample, s_golden, "wrong IO pin/vector value");
END LOOP; -- g_nr_of_writes
-- Check Enum register
info("Checking Register: Enum");
-- check reset value
-- TODO: adapt for each register!
v_byte_addr := std_logic_vector(to_unsigned(c_addr_enum, v_byte_addr'length));
v_mask := x"80003000";
v_reset := x"80002000";
-- DONE
wbs_read_reg(v_byte_addr, v_sample, clk, s_wbs_drv_out, s_wbs_drv_in);
s_sample <= v_sample;
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
s_golden <= v_reset;
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
check_equal(s_sample, s_golden, "wrong register reset value!");
-- write LOOP
FOR i IN 0 TO g_nr_of_writes-1 LOOP
-- Genereate Random Data
-- TODO change register
v_data := f_gen_rdm_vec(s_reg_enum'LENGTH);
-- DONE
s_golden <= v_data AND v_mask; -- AND mask for slices
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
-- Write to Wishbone
report "Write to Wishbone";
wbs_write_reg(v_byte_addr, v_data, clk, s_wbs_drv_out, s_wbs_drv_in);
-- use vunit check_equal check_api to
-- check register value
report "Read from Wishbone";
wbs_read_reg(v_byte_addr, v_sample, clk, s_wbs_drv_out, s_wbs_drv_in);
s_sample <= v_sample;
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
check_equal(s_sample, s_golden, "wrong register value read back");
report "Sampling register output pins";
-- check pin/vector value, combine slices
-- TODO: adapt for each register!
v_sample := (OTHERS => '0');
v_sample(13 DOWNTO 12) := s_o_en_slice;
v_sample(31) := s_o_en_bit;
s_sample <= v_sample;
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
-- DONE
check_equal(s_sample, s_golden, "wrong IO pin/vector value");
END LOOP; -- g_nr_of_writes
-- Notify Registers
-- same as above, with addional notify signals.
-- Check NotifyRw register
-- the following signals are generated:
-- s_o_no_rw_rw_bit rw checked
-- s_o_no_rw_rw_slice rw checked
-- s_i_no_rw_ro_bit ro checked
-- s_i_no_rw_ro_slice ro checked
-- s_o_no_rw_wo_bit trg write only trigger
-- s_o_no_rw_wo_slice trg write only trigger
-- s_o_no_rw_tr_bit trg ???
-- s_o_no_rw_tr_slice trg ???
-- additinal
-- s_o_notify_rw_trd trg read trigger
-- s_o_notify_rw_twr trg write trigger
-- TODO: check notify triggers !
info("Checking Register: NotifyRw");
-- check reset value
-- TODO: adapt for each register!
v_byte_addr := std_logic_vector(to_unsigned(c_addr_notify_rw, v_byte_addr'length));
v_mask := x"FFFF0000";
v_reset := x"6FUU6F6F"; -- ro bits 23 downto 16 are U (undefined), if not driven !!!
-- bits 15 downto 0 are wo/trg !!! No read possible!
-- DONE
report "Read Reset Value from Wishbone (with undefined RO pins)";
wbs_read_reg(v_byte_addr, v_sample, clk, s_wbs_drv_out, s_wbs_drv_in);
--> as far as I can see the read wbs_read_reg doen't create a trigger...
s_sample <= v_sample;
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
s_golden <= v_reset AND v_mask; -- AND mask for slices;
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
check_equal(s_sample, s_golden, "wrong register reset value!");
report "Driving ReadOnly IO inputs with reset value";
v_reset := x"6F6F6F6F"; -- ro bits 23 downto 16 are U (undefined), if not driven !!!
s_i_no_rw_ro_bit <= v_reset(23);
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
s_i_no_rw_ro_slice <= v_reset(22 DOWNTO 16);
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
--> as far as I can see this creates a trigger o_notify_rw_trd
report "Read Reset Value from Wishbone";
wbs_read_reg(v_byte_addr, v_sample, clk, s_wbs_drv_out, s_wbs_drv_in);
s_sample <= v_sample;
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
s_golden <= v_reset AND v_mask; -- AND mask for slices;
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
check_equal(s_sample, s_golden, "wrong register reset value!");
-- write LOOP
FOR i IN 0 TO g_nr_of_writes-1 LOOP
-- Genereate Random Data
-- TODO change register
v_data := f_gen_rdm_vec(s_reg_notify_rw'LENGTH);
-- DONE
s_golden <= v_data AND v_mask; -- AND mask for slices
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
-- Write to Wishbone
report "Write to Wishbone";
wbs_write_reg(v_byte_addr, v_data, clk, s_wbs_drv_out, s_wbs_drv_in);
-- TODO: adapt for each register!
report "Driving IO inputs with random value";
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
s_i_no_rw_ro_bit <= v_data(23);
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
s_i_no_rw_ro_slice <= v_data(22 DOWNTO 16);
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
-- DONE
-- use vunit check_equal check_api to
-- check register value
report "Read from Wishbone";
wbs_read_reg(v_byte_addr, v_sample, clk, s_wbs_drv_out, s_wbs_drv_in);
s_sample <= v_sample;
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
check_equal(s_sample, s_golden, "wrong register value read back");
report "Sampling register output pins";
-- check pin/vector value, combine slices
-- TODO: adapt for each register!
v_sample := (OTHERS => '0');
v_sample(31) := s_o_no_rw_rw_bit;
v_sample(30 DOWNTO 24) := s_o_no_rw_rw_slice;
v_sample(23) := s_i_no_rw_ro_bit;
v_sample(22 DOWNTO 16) := s_i_no_rw_ro_slice;
s_sample <= v_sample;
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
-- DONE
check_equal(s_sample, s_golden, "wrong IO pin/vector value");
END LOOP; -- g_nr_of_writes
-- write to invalid address
WAIT FOR 100 ns;
report "Write to invalid address -> check error assignment";
wbs_transmit(c_addr_invalid_slv, c_wb_dat_max, v_sample, c_wb_we_write, c_wb_sel_max, clk, s_wbs_drv_out, s_wbs_drv_in, v_wb_result);
check_equal(v_wb_result.ack, '0', "erroneous ACK assignment @ write access to invalid address");
check_equal(v_wb_result.err, '1', "erroneous ERR assignment @ write access to invalid address");
check_equal(v_wb_result.rty, '0', "erroneous RTY assignment @ write access to invalid address");
-- read from invalid address
WAIT FOR 100 ns;
report "Read from invalid address -> check error assignment";
wbs_transmit(c_addr_invalid_slv, c_wb_dat_max, v_sample, c_wb_we_read, c_wb_sel_max, clk, s_wbs_drv_out, s_wbs_drv_in, v_wb_result);
check_equal(v_wb_result.ack, '0', "erroneous ACK assignment @ read access to invalid address");
check_equal(v_wb_result.err, '1', "erroneous ERR assignment @ read access to invalid address");
check_equal(v_wb_result.rty, '0', "erroneous RTY assignment @ read access to invalid address");
END IF;
REPORT "TB Done";
END LOOP;
test_runner_cleanup(runner);
END PROCESS main;
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- DUT (wbs_test)
-----------------------------------------------------------------------------
gen_dut_std : IF (g_use_notify_wbs = FALSE) GENERATE
BEGIN
dut : ENTITY tb_lib.wbs_test
GENERIC MAP (
g_addr_bits => g_addr_bits)
PORT MAP (
-- SYSCON, no rst, rst_n
clk => clk,
-- Wishbone
i_wb_cyc => s_wbs_drv_out.cyc,
i_wb_stb => s_wbs_drv_out.stb,
i_wb_we => s_wbs_drv_out.we,
i_wb_sel => s_wbs_drv_out.sel,
i_wb_addr => s_wbs_drv_out.addr,
i_wb_data => s_wbs_drv_out.data,
o_wb_data => s_wbs_drv_in.data,
o_wb_ack => s_wbs_drv_in.ack,
o_wb_rty => s_wbs_drv_in.rty,
o_wb_err => s_wbs_drv_in.err,
-- IO Signals
o_rw_slice0 => s_o_rw_slice0,
o_rw_slice1 => s_o_rw_slice1,
o_rw_bit => s_o_rw_bit,
i_ro_slice0 => s_i_ro_slice0,
i_ro_slice1 => s_i_ro_slice1,
i_ro_bit => s_i_ro_bit,
o_wo_slice0 => s_o_wo_slice0,
o_wo_slice1 => s_o_wo_slice1,
o_wo_bit => s_o_wo_bit,
o_tr_slice0 => s_o_tr_slice0,
o_tr_slice1 => s_o_tr_slice1,
o_tr_bit => s_o_tr_bit,
o_en_bit => s_o_en_bit,
o_en_slice => s_o_en_slice,
o_no_rw_rw_bit => s_o_no_rw_rw_bit,
o_no_rw_rw_slice => s_o_no_rw_rw_slice,
i_no_rw_ro_bit => s_i_no_rw_ro_bit,
i_no_rw_ro_slice => s_i_no_rw_ro_slice,
o_no_rw_wo_bit => s_o_no_rw_wo_bit,
o_no_rw_wo_slice => s_o_no_rw_wo_slice,
o_no_rw_tr_bit => s_o_no_rw_tr_bit,
o_no_rw_tr_slice => s_o_no_rw_tr_slice,
o_notify_rw_trd => s_o_notify_rw_trd,
o_notify_rw_twr => s_o_notify_rw_twr,
o_no_ro_rw_bit => s_o_no_ro_rw_bit,
o_no_ro_rw_slice => s_o_no_ro_rw_slice,
i_no_ro_ro_bit => s_i_no_ro_ro_bit,
i_no_ro_ro_slice => s_i_no_ro_ro_slice,
o_no_ro_wo_bit => s_o_no_ro_wo_bit,
o_no_ro_wo_slice => s_o_no_ro_wo_slice,
o_no_ro_tr_bit => s_o_no_ro_tr_bit,
o_no_ro_tr_slice => s_o_no_ro_tr_slice,
o_notify_ro_trd => s_o_notify_ro_trd,
o_no_wo_rw_bit => s_o_no_wo_rw_bit,
o_no_wo_rw_slice => s_o_no_wo_rw_slice,
i_no_wo_ro_bit => s_i_no_wo_ro_bit,
i_no_wo_ro_slice => s_i_no_wo_ro_slice,
o_no_wo_wo_bit => s_o_no_wo_wo_bit,
o_no_wo_wo_slice => s_o_no_wo_wo_slice,
o_no_wo_tr_bit => s_o_no_wo_tr_bit,
o_no_wo_tr_slice => s_o_no_wo_tr_slice,
o_notify_wo_twr => s_o_notify_wo_twr);
END GENERATE gen_dut_std;
-----------------------------------------------------------------------------
-- DUT (wbs_test_notify)
-----------------------------------------------------------------------------
gen_dut_notify : IF (g_use_notify_wbs = TRUE) GENERATE
BEGIN
dut : ENTITY tb_lib.wbs_test_notify
GENERIC MAP (
g_addr_bits => g_addr_bits)
PORT MAP (
-- SYSCON, no rst, rst_n
clk => clk,
-- Wishbone
i_wb_cyc => s_wbs_drv_out.cyc,
i_wb_stb => s_wbs_drv_out.stb,
i_wb_we => s_wbs_drv_out.we,
i_wb_sel => s_wbs_drv_out.sel,
i_wb_addr => s_wbs_drv_out.addr,
i_wb_data => s_wbs_drv_out.data,
o_wb_data => s_wbs_drv_in.data,
o_wb_ack => s_wbs_drv_in.ack,
o_wb_rty => s_wbs_drv_in.rty,
o_wb_err => s_wbs_drv_in.err,
-- IO Signals
o_rw_slice0 => s_o_rw_slice0,
o_rw_slice1 => s_o_rw_slice1,
o_rw_bit => s_o_rw_bit,
i_ro_slice0 => s_i_ro_slice0,
i_ro_slice1 => s_i_ro_slice1,
i_ro_bit => s_i_ro_bit,
o_wo_slice0 => s_o_wo_slice0,
o_wo_slice1 => s_o_wo_slice1,
o_wo_bit => s_o_wo_bit,
o_tr_slice0 => s_o_tr_slice0,
o_tr_slice1 => s_o_tr_slice1,
o_tr_bit => s_o_tr_bit,
o_en_bit => s_o_en_bit,
o_en_slice => s_o_en_slice,
o_no_rw_rw_bit => s_o_no_rw_rw_bit,
o_no_rw_rw_slice => s_o_no_rw_rw_slice,
i_no_rw_ro_bit => s_i_no_rw_ro_bit,
i_no_rw_ro_slice => s_i_no_rw_ro_slice,
o_no_rw_wo_bit => s_o_no_rw_wo_bit,
o_no_rw_wo_slice => s_o_no_rw_wo_slice,
o_no_rw_tr_bit => s_o_no_rw_tr_bit,
o_no_rw_tr_slice => s_o_no_rw_tr_slice,
o_notify_rw_trd => s_o_notify_rw_trd,
o_notify_rw_twr => s_o_notify_rw_twr,
o_no_ro_rw_bit => s_o_no_ro_rw_bit,
o_no_ro_rw_slice => s_o_no_ro_rw_slice,
i_no_ro_ro_bit => s_i_no_ro_ro_bit,
i_no_ro_ro_slice => s_i_no_ro_ro_slice,
o_no_ro_wo_bit => s_o_no_ro_wo_bit,
o_no_ro_wo_slice => s_o_no_ro_wo_slice,
o_no_ro_tr_bit => s_o_no_ro_tr_bit,
o_no_ro_tr_slice => s_o_no_ro_tr_slice,
o_notify_ro_trd => s_o_notify_ro_trd,
o_no_wo_rw_bit => s_o_no_wo_rw_bit,
o_no_wo_rw_slice => s_o_no_wo_rw_slice,
i_no_wo_ro_bit => s_i_no_wo_ro_bit,
i_no_wo_ro_slice => s_i_no_wo_ro_slice,
o_no_wo_wo_bit => s_o_no_wo_wo_bit,
o_no_wo_wo_slice => s_o_no_wo_wo_slice,
o_no_wo_tr_bit => s_o_no_wo_tr_bit,
o_no_wo_tr_slice => s_o_no_wo_tr_slice,
o_notify_wo_twr => s_o_notify_wo_twr);
END GENERATE gen_dut_notify;
END ARCHITECTURE tb;
-------------------------------------------------------------------------------
| mit | ccc03271348959e8371699f2d0a686da | 0.487387 | 3.646206 | false | false | false | false |
chiggs/nvc | test/regress/signal10.vhd | 5 | 748 | entity signal10 is
end entity;
architecture test of signal10 is
signal x, y, z : bit;
signal u : bit_vector(1 to 3);
signal v : bit_vector(2 downto 0);
begin
process is
begin
(x, y, z) <= bit_vector'("011");
wait for 1 ns;
assert x = '0';
assert y = '1';
assert z = '1';
u <= bit_vector'("011");
wait for 1 ns;
(x, y, z) <= u;
wait for 1 ns;
assert x = '0';
assert y = '1';
assert z = '1';
v <= bit_vector'("011");
wait for 1 ns;
(x, y, z) <= v;
wait for 1 ns;
assert x = '0';
assert y = '1';
assert z = '1';
wait;
end process;
end architecture;
| gpl-3.0 | 9ba0186af23c9a8d74b5981745f39915 | 0.438503 | 3.4 | false | false | false | false |
markusC64/1541ultimate2 | fpga/1541/vhdl_source/stepper.vhd | 1 | 2,734 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity stepper is
port (
clock : in std_logic;
reset : in std_logic;
-- timing
tick_1KHz : in std_logic;
-- track interface from wd177x
goto_track : in unsigned(6 downto 0);
cur_track : in unsigned(6 downto 0);
step_time : in unsigned(4 downto 0);
enable : in std_logic := '1';
busy : out std_logic;
do_track_in : out std_logic; -- for stand alone mode (pure 1581)
do_track_out : out std_logic;
-- Index pulse
motor_en : in std_logic;
index_out : out std_logic;
-- emulated output as if stepping comes from VIA
step : out std_logic_vector(1 downto 0) );
end entity;
architecture behavioral of stepper is
constant c_max_track : natural := 83;
signal track : unsigned(1 downto 0);
signal timer : unsigned(4 downto 0);
signal index_cnt : unsigned(7 downto 0) := X"00";
begin
process(clock)
begin
if rising_edge(clock) then
do_track_in <= '0';
do_track_out <= '0';
if timer /= 0 and tick_1KHz = '1' then
timer <= timer - 1;
end if;
if enable = '0' then -- follow passively when disabled (i.e. when in 1541 mode)
track <= unsigned(cur_track(1 downto 0));
elsif timer = 0 then
if (cur_track < goto_track) and (cur_track /= c_max_track) then
do_track_in <= '1';
track <= track + 1;
timer <= step_time;
elsif cur_track > goto_track then
do_track_out <= '1';
track <= track - 1;
timer <= step_time;
end if;
end if;
if reset = '1' then
track <= "00";
timer <= to_unsigned(1, 5);
end if;
end if;
end process;
step <= std_logic_vector(track);
busy <= enable when (cur_track /= goto_track) else '0';
process(clock)
begin
if rising_edge(clock) then
if tick_1kHz = '1' and motor_en = '1' then
if index_cnt = 0 then
index_out <= '1';
index_cnt <= X"C7";
else
index_out <= '0';
index_cnt <= index_cnt - 1;
end if;
end if;
if reset = '1' then
index_cnt <= X"C7";
index_out <= '0';
end if;
end if;
end process;
end architecture;
| gpl-3.0 | 2f2de8ea14cbd4ff3607591dc3a6cedd | 0.463789 | 3.928161 | false | false | false | false |
mkreider/cocotb2 | examples/wb/hdl/cocotb_bus.vhd | 1 | 2,568 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
use work.genram_pkg.all;
use work.prio_pkg.all;
entity cocotb_bus is
port (
clk : in std_logic;
reset_n : in std_logic;
clk2 : in std_logic;
reset_n2 : in std_logic;
wbs_cyc : in std_logic;
wbs_stb : in std_logic;
wbs_we : in std_logic;
wbs_sel : in std_logic_vector(3 downto 0);
wbs_adr : in std_logic_vector(31 downto 0);
wbs_datrd : out std_logic_vector(31 downto 0);
wbs_datwr : in std_logic_vector(31 downto 0);
wbs_stall : out std_logic;
wbs_ack : out std_logic;
wbs_err : out std_logic;
wbm_cyc : out std_logic;
wbm_stb : out std_logic;
wbm_we : out std_logic;
wbm_sel : out std_logic_vector(3 downto 0);
wbm_adr : out std_logic_vector(31 downto 0);
wbm_datrd : in std_logic_vector(31 downto 0);
wbm_datwr : out std_logic_vector(31 downto 0);
wbm_err : in std_logic;
wbm_stall : in std_logic;
wbm_ack : in std_logic;
ts_out : out std_logic_vector(63 downto 0);
ts_valid_out : out std_logic;
en_in : in std_logic
);
end entity;
architecture rtl of cocotb_bus is
signal s_slave_in : t_wishbone_slave_in;
signal s_slave_out : t_wishbone_slave_out;
signal s_master_in : t_wishbone_master_in;
signal s_master_out : t_wishbone_master_out;
begin
s_slave_in.we <= wbs_we;
s_slave_in.stb <= wbs_stb;
s_slave_in.dat <= wbs_datwr;
s_slave_in.adr <= wbs_adr;
s_slave_in.sel <= x"f";
s_slave_in.cyc <= wbs_cyc;
-- s_master_in.dat <= reg;
wbs_datrd <= s_slave_out.dat;
wbs_ack <= s_slave_out.ack;
wbs_stall <= s_slave_out.stall;
wbs_err <= s_slave_out.err;
wbm_we <= s_master_out.we;
wbm_stb <= s_master_out.stb;
wbm_datwr <= s_master_out.dat;
wbm_adr <= s_master_out.adr;
wbm_sel <= s_master_out.sel;
wbm_cyc <= s_master_out.cyc;
s_master_in.dat <= wbm_datrd;
s_master_in.ack <= wbm_ack;
s_master_in.err <= wbm_err;
s_master_in.stall <= wbm_stall;
dut : queue_unit is
generic map(
g_depth => 32,
g_words => 8
);
port map(
clk_i => clk,
rst_n_i => reset_n,
slave_i => s_slave_in,
slave_o => s_slave_out,
master_o => s_master_out,
master_i => s_master_in,
ts_o => ts_out,
ts_valid_o => ts_valid_out,
sel_i => en_in
);
end architecture;
| bsd-3-clause | 2533f355b94c20b33d7a622adf3aaa92 | 0.561916 | 2.658385 | false | false | false | false |
xiadz/oscilloscope | src/clock_divider.vhd | 1 | 965 | -- A simple frequency divider
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity divider is
-- 1
-- f_out = f_in -----
-- 2 * n
generic (n: natural range 1 to 2147483647);
port (
clk_in : in std_logic;
nrst : in std_logic;
clk_out : out std_logic
);
end entity divider;
architecture counter of divider is
signal cnt : integer range 0 to n - 1;
signal internal_clk_out : std_logic := '0';
begin
clk_out <= internal_clk_out;
process (clk_in, nrst)
begin
if nrst = '0' then
cnt <= 0;
internal_clk_out <= '0';
elsif rising_edge (clk_in) then
if cnt = n - 1 then
cnt <= 0;
internal_clk_out <= not internal_clk_out;
else
cnt <= cnt + 1;
end if;
end if;
end process;
end architecture counter;
| mit | 986aef7e5f56784a9a847c2ab1343a51 | 0.501554 | 3.769531 | false | false | false | false |
markusC64/1541ultimate2 | fpga/sid6581/vhdl_source/sid_top.vhd | 1 | 11,900 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
--
-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
--
-- Note that this file is copyrighted, and is not supposed to be used in other
-- projects without written permission from the author.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
entity sid_top is
generic (
g_8voices : boolean := false;
g_num_voices : natural := 16 );
port (
clock : in std_logic;
reset : in std_logic;
addr : in unsigned(7 downto 0);
wren : in std_logic;
wdata : in std_logic_vector(7 downto 0);
rdata : out std_logic_vector(7 downto 0);
comb_wave_l : in std_logic := '0';
comb_wave_r : in std_logic := '0';
io_req_filt0 : in t_io_req := c_io_req_init;
io_resp_filt0 : out t_io_resp;
io_req_filt1 : in t_io_req := c_io_req_init;
io_resp_filt1 : out t_io_resp;
start_iter : in std_logic;
sample_left : out signed(17 downto 0);
sample_right : out signed(17 downto 0) );
end sid_top;
architecture structural of sid_top is
-- Voice index in pipe
signal voice_osc : unsigned(3 downto 0);
signal voice_wave : unsigned(3 downto 0);
signal voice_mul : unsigned(3 downto 0);
signal enable_osc : std_logic;
signal enable_wave : std_logic;
signal enable_mul : std_logic;
-- Oscillator parameters
signal freq : unsigned(15 downto 0);
signal test : std_logic;
signal sync : std_logic;
-- Wave map parameters
signal msb_other : std_logic;
signal comb_mode : std_logic;
signal ring_mod : std_logic;
signal wave_sel : std_logic_vector(3 downto 0);
signal sq_width : unsigned(11 downto 0);
-- ADSR parameters
signal gate : std_logic;
signal attack : std_logic_vector(3 downto 0);
signal decay : std_logic_vector(3 downto 0);
signal sustain : std_logic_vector(3 downto 0);
signal release : std_logic_vector(3 downto 0);
-- Filter enable
signal filter_en : std_logic;
-- globals
signal volume_l : unsigned(3 downto 0);
signal filter_co_l : unsigned(10 downto 0);
signal filter_res_l : unsigned(3 downto 0);
signal filter_ex_l : std_logic;
signal filter_hp_l : std_logic;
signal filter_bp_l : std_logic;
signal filter_lp_l : std_logic;
signal voice3_off_l : std_logic;
signal volume_r : unsigned(3 downto 0);
signal filter_co_r : unsigned(10 downto 0);
signal filter_res_r : unsigned(3 downto 0);
signal filter_ex_r : std_logic;
signal filter_hp_r : std_logic;
signal filter_bp_r : std_logic;
signal filter_lp_r : std_logic;
signal voice3_off_r : std_logic;
-- readback
signal osc3 : std_logic_vector(7 downto 0);
signal env3 : std_logic_vector(7 downto 0);
-- intermediate flags and signals
signal test_wave : std_logic;
signal osc_val : unsigned(23 downto 0);
signal carry_20 : std_logic;
signal enveloppe : unsigned(7 downto 0);
signal waveform : unsigned(11 downto 0);
signal valid_sum : std_logic;
signal valid_filt : std_logic;
signal valid_mix : std_logic;
signal filter_out_l: signed(17 downto 0) := (others => '0');
signal direct_out_l: signed(17 downto 0) := (others => '0');
signal high_pass_l : signed(17 downto 0) := (others => '0');
signal band_pass_l : signed(17 downto 0) := (others => '0');
signal low_pass_l : signed(17 downto 0) := (others => '0');
signal mixed_out_l : signed(17 downto 0) := (others => '0');
signal filter_out_r: signed(17 downto 0) := (others => '0');
signal direct_out_r: signed(17 downto 0) := (others => '0');
signal high_pass_r : signed(17 downto 0) := (others => '0');
signal band_pass_r : signed(17 downto 0) := (others => '0');
signal low_pass_r : signed(17 downto 0) := (others => '0');
signal mixed_out_r : signed(17 downto 0) := (others => '0');
begin
i_regs: entity work.sid_regs
generic map (
g_8voices => g_8voices )
port map (
clock => clock,
reset => reset,
addr => addr,
wren => wren,
wdata => wdata,
rdata => rdata,
comb_wave_l => comb_wave_l,
comb_wave_r => comb_wave_r,
---
voice_osc => voice_osc,
voice_wave => voice_wave,
voice_adsr => voice_wave,
voice_mul => voice_mul,
-- Oscillator parameters
freq => freq,
test => test,
sync => sync,
-- Wave map parameters
comb_mode => comb_mode,
ring_mod => ring_mod,
wave_sel => wave_sel,
sq_width => sq_width,
-- ADSR parameters
gate => gate,
attack => attack,
decay => decay,
sustain => sustain,
release => release,
-- mixer parameters
filter_en => filter_en,
-- globals
volume_l => volume_l,
filter_co_l => filter_co_l,
filter_res_l=> filter_res_l,
filter_ex_l => filter_ex_l,
filter_hp_l => filter_hp_l,
filter_bp_l => filter_bp_l,
filter_lp_l => filter_lp_l,
voice3_off_l=> voice3_off_l,
volume_r => volume_r,
filter_co_r => filter_co_r,
filter_res_r=> filter_res_r,
filter_ex_r => filter_ex_r,
filter_hp_r => filter_hp_r,
filter_bp_r => filter_bp_r,
filter_lp_r => filter_lp_r,
voice3_off_r=> voice3_off_r,
-- readback
osc3 => osc3,
env3 => env3 );
i_ctrl: entity work.sid_ctrl
generic map (
g_num_voices => g_num_voices )
port map (
clock => clock,
reset => reset,
start_iter => start_iter,
voice_osc => voice_osc,
enable_osc => enable_osc );
osc: entity work.oscillator
generic map (g_num_voices)
port map (
clock => clock,
reset => reset,
voice_i => voice_osc,
voice_o => voice_wave,
enable_i => enable_osc,
enable_o => enable_wave,
freq => freq,
test => test,
sync => sync,
osc_val => osc_val,
test_o => test_wave,
carry_20 => carry_20,
msb_other => msb_other );
wmap: entity work.wave_map
generic map (
g_num_voices => g_num_voices,
g_sample_bits => 12 )
port map (
clock => clock,
reset => reset,
test => test_wave,
osc_val => osc_val,
carry_20 => carry_20,
msb_other => msb_other,
voice_i => voice_wave,
enable_i => enable_wave,
comb_mode => comb_mode,
wave_sel => wave_sel,
ring_mod => ring_mod,
sq_width => sq_width,
voice_o => voice_mul,
enable_o => enable_mul,
wave_out => waveform );
adsr: entity work.adsr_multi
generic map (
g_num_voices => g_num_voices )
port map (
clock => clock,
reset => reset,
voice_i => voice_wave,
enable_i => enable_wave,
voice_o => open,
enable_o => open,
gate => gate,
attack => attack,
decay => decay,
sustain => sustain,
release => release,
env_state=> open, -- for testing only
env_out => enveloppe );
sum: entity work.mult_acc(signed_wave)
port map (
clock => clock,
reset => reset,
voice_i => voice_mul,
enable_i => enable_mul,
voice3_off_l=> voice3_off_l,
voice3_off_r=> voice3_off_r,
enveloppe => enveloppe,
waveform => waveform,
filter_en => filter_en,
--
osc3 => osc3,
env3 => env3,
--
valid_out => valid_sum,
filter_out_L => filter_out_L,
filter_out_R => filter_out_R,
direct_out_L => direct_out_L,
direct_out_R => direct_out_R );
i_filt_left: entity work.sid_filter
port map (
clock => clock,
reset => reset,
io_req => io_req_filt0,
io_resp => io_resp_filt0,
filt_co => filter_co_l,
filt_res => filter_res_l,
valid_in => valid_sum,
input => filter_out_L,
high_pass => high_pass_L,
band_pass => band_pass_L,
low_pass => low_pass_L,
error_out => open,
valid_out => valid_filt );
-- Now we have to add the following signals together:
-- direct_out
-- high_pass (when filter_hp='1')
-- band_pass (when filter_bp='1')
-- low_pass (when filter_lp='1')
--
-- .. and apply the final volume control
mix: entity work.sid_mixer
port map (
clock => clock,
reset => reset,
valid_in => valid_filt,
direct_out => direct_out_L,
high_pass => high_pass_L,
band_pass => band_pass_L,
low_pass => low_pass_L,
filter_hp => filter_hp_l,
filter_bp => filter_bp_l,
filter_lp => filter_lp_l,
volume => volume_l,
mixed_out => mixed_out_L,
valid_out => valid_mix );
r_right_filter: if g_num_voices > 8 generate
i_filt: entity work.sid_filter
port map (
clock => clock,
reset => reset,
io_req => io_req_filt1,
io_resp => io_resp_filt1,
filt_co => filter_co_r,
filt_res => filter_res_r,
valid_in => valid_sum,
input => filter_out_R,
high_pass => high_pass_R,
band_pass => band_pass_R,
low_pass => low_pass_R,
error_out => open,
valid_out => open );
mix_right: entity work.sid_mixer
port map (
clock => clock,
reset => reset,
valid_in => valid_filt,
direct_out => direct_out_R,
high_pass => high_pass_R,
band_pass => band_pass_R,
low_pass => low_pass_R,
filter_hp => filter_hp_r,
filter_bp => filter_bp_r,
filter_lp => filter_lp_r,
volume => volume_r,
mixed_out => mixed_out_R,
valid_out => open );
end generate;
sample_left <= mixed_out_L;
sample_right <= mixed_out_R when g_num_voices > 8 else mixed_out_L;
end structural;
| gpl-3.0 | 013d0d381b3ad621d09f01eb13b0e747 | 0.468067 | 3.72224 | false | false | false | false |
markusC64/1541ultimate2 | fpga/io/rmii/vhdl_source/eth_filter.vhd | 1 | 13,457 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : eth_filter
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: Filter block for ethernet frames
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.block_bus_pkg.all;
use work.mem_bus_pkg.all;
entity eth_filter is
generic (
g_mem_tag : std_logic_vector(7 downto 0) := X"13" );
port (
clock : in std_logic;
reset : in std_logic;
-- io interface for local cpu
io_req : in t_io_req;
io_resp : out t_io_resp;
-- interface to free block system
alloc_req : out std_logic;
alloc_resp : in t_alloc_resp;
used_req : out t_used_req;
used_resp : in std_logic;
-- interface to memory
mem_req : out t_mem_req_32;
mem_resp : in t_mem_resp_32;
----
eth_clock : in std_logic;
eth_reset : in std_logic;
eth_rx_data : in std_logic_vector(7 downto 0);
eth_rx_sof : in std_logic;
eth_rx_eof : in std_logic;
eth_rx_valid : in std_logic );
end entity;
architecture gideon of eth_filter is
-- signals in the sys_clock domain
type t_mac is array(0 to 5) of std_logic_vector(7 downto 0);
signal my_mac : t_mac := (others => (others => '0'));
type t_mac_16 is array(0 to 2) of std_logic_vector(15 downto 0);
signal my_mac_16 : t_mac_16 := (others => (others => '0'));
signal eth_rx_enable : std_logic;
signal clear : std_logic;
signal rx_enable : std_logic;
signal promiscuous : std_logic;
signal rd_next : std_logic;
signal rd_dout : std_logic_vector(17 downto 0);
signal rd_valid : std_logic;
type t_receive_state is (idle, odd, even, len, ovfl);
signal receive_state : t_receive_state;
type t_state is (idle, get_block, drop, copy, valid_packet, pushing, ram_write);
signal state : t_state;
signal address_valid : std_logic;
signal start_addr : unsigned(25 downto 0);
signal mac_idx : integer range 0 to 3;
signal for_me : std_logic;
signal block_id : unsigned(7 downto 0);
-- memory signals
signal mem_addr : unsigned(25 downto 0) := (others => '0');
signal mem_data : std_logic_vector(31 downto 0) := (others => '0');
signal write_req : std_logic;
-- signals in eth_clock domain
signal eth_wr_din : std_logic_vector(17 downto 0);
signal eth_wr_en : std_logic;
signal eth_wr_full : std_logic;
signal eth_length : unsigned(11 downto 0);
signal crc_ok : std_logic;
signal toggle : std_logic;
begin
-- 18 wide fifo; 16 data bits and 2 control bits
-- 00 = packet data
-- 01 = overflow detected => drop
-- 10 = packet with CRC error => drop
-- 11 = packet OK!
i_fifo: entity work.async_fifo_ft
generic map (
--g_fast => true,
g_data_width => 18,
g_depth_bits => 9
)
port map (
wr_clock => eth_clock,
wr_reset => eth_reset,
wr_en => eth_wr_en,
wr_din => eth_wr_din,
wr_full => eth_wr_full,
rd_clock => clock,
rd_reset => clear,
rd_next => rd_next,
rd_dout => rd_dout,
rd_valid => rd_valid
);
clear <= reset or not rx_enable;
process(eth_clock)
begin
if rising_edge(eth_clock) then
eth_wr_en <= '0';
case receive_state is
when idle =>
eth_wr_din(7 downto 0) <= eth_rx_data;
eth_length <= to_unsigned(1, eth_length'length);
if eth_rx_sof = '1' and eth_rx_valid = '1' then
receive_state <= odd;
end if;
when odd =>
eth_wr_din(15 downto 8) <= eth_rx_data;
eth_wr_din(17 downto 16) <= "00";
if eth_rx_valid = '1' then
eth_length <= eth_length + 1;
if eth_wr_full = '1' then
receive_state <= ovfl;
else
eth_wr_en <= '1';
crc_ok <= eth_rx_data(0);
if eth_rx_eof = '1' then
receive_state <= len;
else
receive_state <= even;
end if;
end if;
end if;
when even =>
eth_wr_din(7 downto 0) <= eth_rx_data;
eth_wr_din(17 downto 16) <= "00";
if eth_rx_valid = '1' then
eth_length <= eth_length + 1;
if eth_rx_eof = '1' then
receive_state <= len;
crc_ok <= eth_rx_data(0);
else
receive_state <= odd;
end if;
end if;
when len =>
if eth_wr_full = '0' then
eth_wr_din <= (others => '0');
eth_wr_din(17) <= '1';
eth_wr_din(16) <= crc_ok;
eth_wr_din(eth_length'range) <= std_logic_vector(eth_length);
eth_wr_en <= '1';
receive_state <= idle;
else
receive_state <= ovfl;
end if;
when ovfl =>
if eth_wr_full = '0' then
eth_wr_din(17 downto 16) <= "01";
eth_wr_en <= '1';
receive_state <= idle;
end if;
end case;
if eth_reset = '1' or eth_rx_enable = '0' then
receive_state <= idle;
crc_ok <= '0';
end if;
end if;
end process;
i_sync_enable: entity work.level_synchronizer
port map (
clock => eth_clock,
reset => eth_reset,
input => rx_enable,
input_c => eth_rx_enable
);
process(clock)
alias local_addr : unsigned(3 downto 0) is io_req.address(3 downto 0);
begin
if rising_edge(clock) then
io_resp <= c_io_resp_init;
if io_req.write = '1' then
io_resp.ack <= '1';
case local_addr is
when X"0"|X"1"|X"2"|X"3"|X"4"|X"5" =>
my_mac(to_integer(local_addr)) <= io_req.data;
when X"7" =>
promiscuous <= io_req.data(0);
when X"8" =>
rx_enable <= io_req.data(0);
when others =>
null;
end case;
end if;
if io_req.read = '1' then
io_resp.ack <= '1';
case local_addr is
when others =>
null;
end case;
end if;
if reset = '1' then
promiscuous <= '0';
rx_enable <= '0';
end if;
end if;
end process;
-- condense to do 16 bit compares with data from fifo
my_mac_16(0) <= my_mac(1) & my_mac(0);
my_mac_16(1) <= my_mac(3) & my_mac(2);
my_mac_16(2) <= my_mac(5) & my_mac(4);
process(clock)
begin
if rising_edge(clock) then
case state is
when idle =>
mac_idx <= 0;
toggle <= '0';
for_me <= '1';
if rx_enable = '0' then
address_valid <= '0';
end if;
if rd_valid = '1' then -- packet data available!
if rd_dout(17 downto 16) = "00" then
if rx_enable = '0' then
state <= drop;
elsif address_valid = '1' then
mem_addr <= start_addr;
state <= copy;
else
alloc_req <= '1';
state <= get_block;
end if;
else
state <= drop; -- resyncronize
end if;
end if;
when get_block =>
if alloc_resp.done = '1' then
alloc_req <= '0';
block_id <= alloc_resp.id;
if alloc_resp.error = '1' then
state <= drop;
else
start_addr <= alloc_resp.address;
mem_addr <= alloc_resp.address;
address_valid <= '1';
state <= copy;
end if;
end if;
when drop =>
if (rd_valid = '1' and rd_dout(17 downto 16) /= "00") or (rx_enable = '0') then
state <= idle;
end if;
when copy =>
if rx_enable = '0' then
state <= idle;
elsif rd_valid = '1' then
if mac_idx /= 3 then
if rd_dout(15 downto 0) /= X"FFFF" and rd_dout(15 downto 0) /= my_mac_16(mac_idx) then
for_me <= '0';
end if;
mac_idx <= mac_idx + 1;
end if;
toggle <= not toggle;
if toggle = '0' then
mem_data(31 downto 16) <= rd_dout(15 downto 0);
if for_me = '1' or promiscuous = '1' then
write_req <= '1';
state <= ram_write;
end if;
else
mem_data(15 downto 0) <= rd_dout(15 downto 0);
end if;
case rd_dout(17 downto 16) is
when "01" =>
-- overflow detected
write_req <= '0';
state <= idle;
when "10" =>
-- packet with bad CRC
write_req <= '0';
state <= idle;
when "11" =>
-- correct packet!
used_req.bytes <= unsigned(rd_dout(used_req.bytes'range)) - 5; -- snoop FF and CRC
if for_me = '1' or promiscuous = '1' then
write_req <= '1';
state <= valid_packet;
else
state <= idle;
end if;
when others =>
null;
end case;
end if;
when ram_write =>
if mem_resp.rack_tag = g_mem_tag then
write_req <= '0';
mem_addr <= mem_addr + 4;
state <= copy;
end if;
when valid_packet =>
if mem_resp.rack_tag = g_mem_tag then
write_req <= '0';
if for_me = '1' or promiscuous = '1' then
address_valid <= '0';
used_req.request <= '1';
used_req.id <= block_id;
state <= pushing;
else
state <= idle;
end if;
end if;
when pushing =>
if used_resp = '1' then
used_req.request <= '0';
state <= idle;
end if;
end case;
if reset = '1' then
alloc_req <= '0';
used_req <= c_used_req_init;
state <= idle;
address_valid <= '0';
write_req <= '0';
end if;
end if;
end process;
mem_req.request <= write_req;
mem_req.data <= mem_data;
mem_req.address <= mem_addr;
mem_req.read_writen <= '0';
mem_req.byte_en <= (others => '1');
mem_req.tag <= g_mem_tag;
process(state)
begin
case state is
when drop =>
rd_next <= '1';
when copy =>
rd_next <= '1'; -- do something here with memory
when others =>
rd_next <= '0';
end case;
end process;
end architecture;
| gpl-3.0 | 66bc8b557573592287c5ba81bf1d29d5 | 0.384707 | 4.328401 | false | false | false | false |
trondd/mkjpeg | design/JFIFGen/JFIFGen.vhd | 2 | 10,100 | -------------------------------------------------------------------------------
-- File Name : JFIFGen.vhd
--
-- Project : JPEG_ENC
--
-- Module : JFIFGen
--
-- Content : JFIF Header Generator
--
-- Description :
--
-- Spec. :
--
-- Author : Michal Krepa
--
-------------------------------------------------------------------------------
-- History :
-- 20090309: (MK): Initial Creation.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- LIBRARY/PACKAGE ---------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- generic packages/libraries:
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.JPEG_PKG.all;
-------------------------------------------------------------------------------
-- user packages/libraries:
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ENTITY ------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
entity JFIFGen is
port
(
CLK : in std_logic;
RST : in std_logic;
-- CTRL
start : in std_logic;
ready : out std_logic;
eoi : in std_logic;
-- ByteStuffer
num_enc_bytes : in std_logic_vector(23 downto 0);
-- HOST IF
qwren : in std_logic;
qwaddr : in std_logic_vector(6 downto 0);
qwdata : in std_logic_vector(7 downto 0);
image_size_reg : in std_logic_vector(31 downto 0);
image_size_reg_wr : in std_logic;
-- OUT RAM
ram_byte : out std_logic_vector(7 downto 0);
ram_wren : out std_logic;
ram_wraddr : out std_logic_vector(23 downto 0)
);
end entity JFIFGen;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ARCHITECTURE ------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture RTL of JFIFGen is
constant C_SIZE_Y_H : integer := 25;
constant C_SIZE_Y_L : integer := 26;
constant C_SIZE_X_H : integer := 27;
constant C_SIZE_X_L : integer := 28;
constant C_EOI : std_logic_vector(15 downto 0) := X"FFD9";
constant C_QLUM_BASE : integer := 44;
constant C_QCHR_BASE : integer := 44+69;
signal hr_data : std_logic_vector(7 downto 0);
signal hr_waddr : std_logic_vector(9 downto 0);
signal hr_raddr : std_logic_vector(9 downto 0);
signal hr_we : std_logic;
signal hr_q : std_logic_vector(7 downto 0);
signal size_wr_cnt : unsigned(2 downto 0);
signal size_wr : std_logic;
signal rd_cnt : unsigned(9 downto 0);
signal rd_en : std_logic;
signal rd_en_d1 : std_logic;
signal rd_cnt_d1 : unsigned(rd_cnt'range);
signal rd_cnt_d2 : unsigned(rd_cnt'range);
signal eoi_cnt : unsigned(1 downto 0);
signal eoi_wr : std_logic;
signal eoi_wr_d1 : std_logic;
component HeaderRam is
port
(
d : in STD_LOGIC_VECTOR(7 downto 0);
waddr : in STD_LOGIC_VECTOR(9 downto 0);
raddr : in STD_LOGIC_VECTOR(9 downto 0);
we : in STD_LOGIC;
clk : in STD_LOGIC;
q : out STD_LOGIC_VECTOR(7 downto 0)
);
end component;
-------------------------------------------------------------------------------
-- Architecture: begin
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------
-- Header RAM
-------------------------------------------------------------------
U_Header_RAM : HeaderRam
port map
(
d => hr_data,
waddr => hr_waddr,
raddr => hr_raddr,
we => hr_we,
clk => CLK,
q => hr_q
);
hr_raddr <= std_logic_vector(rd_cnt);
-------------------------------------------------------------------
-- Host programming
-------------------------------------------------------------------
p_host_wr : process(CLK, RST)
begin
if RST = '1' then
size_wr_cnt <= (others => '0');
size_wr <= '0';
hr_we <= '0';
hr_data <= (others => '0');
hr_waddr <= (others => '0');
elsif CLK'event and CLK = '1' then
hr_we <= '0';
if image_size_reg_wr = '1' then
size_wr_cnt <= (others => '0');
size_wr <= '1';
end if;
-- write image size
if size_wr = '1' then
if size_wr_cnt = 4 then
size_wr_cnt <= (others => '0');
size_wr <= '0';
else
size_wr_cnt <= size_wr_cnt + 1;
hr_we <= '1';
case size_wr_cnt is
-- height H byte
when "000" =>
hr_data <= image_size_reg(15 downto 8);
hr_waddr <= std_logic_vector(to_unsigned(C_SIZE_Y_H,hr_waddr'length));
-- height L byte
when "001" =>
hr_data <= image_size_reg(7 downto 0);
hr_waddr <= std_logic_vector(to_unsigned(C_SIZE_Y_L,hr_waddr'length));
-- width H byte
when "010" =>
hr_data <= image_size_reg(31 downto 24);
hr_waddr <= std_logic_vector(to_unsigned(C_SIZE_X_H,hr_waddr'length));
-- width L byte
when "011" =>
hr_data <= image_size_reg(23 downto 16);
hr_waddr <= std_logic_vector(to_unsigned(C_SIZE_X_L,hr_waddr'length));
when others =>
null;
end case;
end if;
-- write Quantization table
elsif qwren = '1' then
-- luminance table select
if qwaddr(6) = '0' then
hr_waddr <= std_logic_vector
( resize(unsigned(qwaddr(5 downto 0)),hr_waddr'length) +
to_unsigned(C_QLUM_BASE,hr_waddr'length));
else
-- chrominance table select
hr_waddr <= std_logic_vector
( resize(unsigned(qwaddr(5 downto 0)),hr_waddr'length) +
to_unsigned(C_QCHR_BASE,hr_waddr'length));
end if;
hr_we <= '1';
hr_data <= qwdata;
end if;
end if;
end process;
-------------------------------------------------------------------
-- CTRL
-------------------------------------------------------------------
p_ctrl : process(CLK, RST)
begin
if RST = '1' then
ready <= '0';
rd_en <= '0';
rd_cnt <= (others => '0');
rd_cnt_d1 <= (others => '0');
rd_cnt_d2 <= (others => '0');
rd_cnt_d1 <= (others => '0');
rd_en_d1 <= '0';
eoi_wr_d1 <= '0';
eoi_wr <= '0';
eoi_cnt <= (others => '0');
ram_wren <= '0';
ram_byte <= (others => '0');
ram_wraddr <= (others => '0');
elsif CLK'event and CLK = '1' then
ready <= '0';
rd_cnt_d1 <= rd_cnt;
rd_cnt_d2 <= rd_cnt_d1;
rd_en_d1 <= rd_en;
eoi_wr_d1 <= eoi_wr;
-- defaults: encoded data write
ram_wren <= rd_en_d1;
ram_wraddr <= std_logic_vector(resize(rd_cnt_d1,ram_wraddr'length));
ram_byte <= hr_q;
-- start JFIF
if start = '1' and eoi = '0' then
rd_cnt <= (others => '0');
rd_en <= '1';
elsif start = '1' and eoi = '1' then
eoi_wr <= '1';
eoi_cnt <= (others => '0');
end if;
-- read JFIF Header
if rd_en = '1' then
if rd_cnt = C_HDR_SIZE-1 then
rd_en <= '0';
ready <= '1';
else
rd_cnt <= rd_cnt + 1;
end if;
end if;
-- EOI MARKER write
if eoi_wr = '1' then
if eoi_cnt = 2 then
eoi_cnt <= (others => '0');
eoi_wr <= '0';
ready <= '1';
else
eoi_cnt <= eoi_cnt + 1;
ram_wren <= '1';
if eoi_cnt = 0 then
ram_byte <= C_EOI(15 downto 8);
ram_wraddr <= num_enc_bytes;
elsif eoi_cnt = 1 then
ram_byte <= C_EOI(7 downto 0);
ram_wraddr <= std_logic_vector(unsigned(num_enc_bytes) +
to_unsigned(1,ram_wraddr'length));
end if;
end if;
end if;
end if;
end process;
end architecture RTL;
-------------------------------------------------------------------------------
-- Architecture: end
------------------------------------------------------------------------------- | lgpl-3.0 | 8bf122f8482b4eb0d8f8b11ccb2517b4 | 0.342079 | 4.461131 | false | false | false | false |
markusC64/1541ultimate2 | fpga/fpga_top/cyclone4_test/vhdl_source/u64test_remote.vhd | 1 | 6,379 | --------------------------------------------------------------------------------
-- Entity: u64test_remote
-- Date:2018-09-07
-- Author: gideon
--
-- Description: Remote registers on cartridge port for loopback testing of cart port
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity u64test_remote is
port (
arst : in std_logic;
BUTTON : in std_logic_vector(2 downto 0);
PHI2 : in std_logic;
DOTCLK : in std_logic;
IO1n : in std_logic;
IO2n : in std_logic;
ROMLn : in std_logic;
ROMHn : in std_logic;
BA : in std_logic;
RWn : in std_logic;
GAMEn : out std_logic;
EXROMn : out std_logic;
DMAn : out std_logic;
IRQn : inout std_logic;
NMIn : inout std_logic;
RESETn : in std_logic;
D : inout std_logic_vector(7 downto 0);
A : inout std_logic_vector(15 downto 0);
LED_MOTORn : out std_logic;
LED_DISKn : out std_logic;
LED_CARTn : out std_logic;
LED_SDACTn : out std_logic;
IEC_SRQ : inout std_logic;
IEC_RST : inout std_logic;
IEC_CLK : inout std_logic;
IEC_DATA : inout std_logic;
IEC_ATN : inout std_logic;
CAS_READ : in std_logic;
CAS_WRITE : in std_logic;
CAS_MOTOR : in std_logic;
CAS_SENSE : in std_logic );
end entity;
architecture arch of u64test_remote is
signal clock : std_logic;
signal addr_en : std_logic;
signal ram_address : unsigned(7 downto 0);
signal ram_en : std_logic;
signal ram_we : std_logic;
signal ram_wdata : std_logic_vector(7 downto 0);
signal ram_rdata : std_logic_vector(7 downto 0);
signal iec_out : std_logic_vector(4 downto 0);
signal addr_out : std_logic_vector(15 downto 0);
signal cart_out : std_logic_vector(7 downto 0);
signal reg_out : std_logic_vector(7 downto 0);
signal led_out : std_logic_vector(3 downto 0);
signal cart_in : std_logic_vector(7 downto 0) := X"00";
signal iec_in : std_logic_vector(7 downto 0) := X"00";
signal cas_in : std_logic_vector(7 downto 0) := X"00";
signal phi2_d : std_logic := '1';
signal io2n_d : std_logic := '1';
signal rwn_d : std_logic := '1';
begin
clock <= not PHI2;
process(clock, arst)
variable v_addr : std_logic_vector(2 downto 0);
begin
if arst = '1' then
addr_en <= '0';
iec_out <= (others => '0');
addr_out <= (others => '0');
cart_out <= (others => '0');
led_out <= (others => '0');
elsif rising_edge(clock) then
if RWn = '0' and IO1n = '0' then
v_addr := A(2 downto 0);
case v_addr is
when "000" =>
cart_out <= D(cart_out'range);
when "010" =>
addr_out(15 downto 8) <= D;
when "011" =>
addr_out(7 downto 0) <= D;
when "100" =>
iec_out <= D(iec_out'range);
when "110" =>
if D = X"B9" then
addr_en <= '1';
end if;
when "111" =>
led_out <= D(led_out'range);
when others =>
null;
end case;
end if;
end if;
end process;
i_ram: entity work.spram
generic map (
g_width_bits => 8,
g_depth_bits => 8
)
port map (
clock => DOTCLK,
address => ram_address,
rdata => ram_rdata,
wdata => ram_wdata,
en => ram_en,
we => ram_we
);
ram_en <= '1';
process(DOTCLK)
begin
if rising_edge(DOTCLK) then
ram_address <= unsigned(A(7 downto 0));
phi2_d <= PHI2;
io2n_d <= IO2n;
rwn_d <= RWn;
ram_wdata <= D;
end if;
end process;
ram_we <= '1' when phi2_d = '1' and PHI2 = '0' and io2n_d = '0' and rwn_d = '0' else '0';
with A(2 downto 0) select reg_out <=
cart_out when "000",
cart_in when "001",
A(15 downto 8) when "010",
A(7 downto 0) when "011", -- lower 3 bits will always read as "011"
iec_in when "100",
cas_in when "101",
X"99" when others;
process(IO1n, IO2n, RWn, reg_out, ram_rdata)
begin
D <= (others => 'Z');
if RWn = '1' then -- read cycle
if IO1n = '0' then
D <= reg_out;
elsif IO2n = '0' then
D <= ram_rdata;
end if;
end if;
end process;
process(addr_en, BA, addr_out)
begin
A <= (others => 'Z');
if addr_en = '1' and BA = '1' then
A <= addr_out;
end if;
end process;
-- IEC pins
IEC_ATN <= '0' when iec_out(0) = '1' else 'Z';
IEC_CLK <= '0' when iec_out(1) = '1' else 'Z';
IEC_DATA <= '0' when iec_out(2) = '1' else 'Z';
IEC_SRQ <= '0' when iec_out(3) = '1' else 'Z';
IEC_RST <= '0' when iec_out(4) = '1' else 'Z';
iec_in <= "000" & IEC_RST & IEC_SRQ & IEC_DATA & IEC_CLK & IEC_ATN;
-- CAS pins
cas_in <= "0000" & CAS_SENSE & CAS_WRITE & CAS_READ & CAS_MOTOR;
-- CART pins
cart_in(0) <= IRQn;
cart_in(1) <= NMIn;
cart_in(2) <= ROMLn;
cart_in(3) <= ROMHn;
cart_in(4) <= DOTCLK;
cart_in(5) <= RESETn;
cart_in(6) <= BA;
IRQn <= '0' when cart_out(0) = '1' or button(2) = '0' else 'Z';
NMIn <= '0' when cart_out(1) = '1' or button(1) = '0' else 'Z';
GAMEn <= '0' when cart_out(2) = '1' else 'Z';
EXROMn <= '0' when cart_out(3) = '1' else 'Z';
DMAn <= '0' when cart_out(4) = '1' else 'Z';
-- RESETn <= '0' when cart_out(5) <= '1' else 'Z';
LED_MOTORn <= not led_out(0);
LED_DISKn <= not led_out(1);
LED_CARTn <= not led_out(2);
LED_SDACTn <= not led_out(3);
end architecture;
| gpl-3.0 | 2b6f37e246614743f1bd93188cc38313 | 0.457595 | 3.23151 | false | false | false | false |
markusC64/1541ultimate2 | fpga/1541/vhdl_source/floppy.vhd | 1 | 6,555 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2006, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Floppy Emulator
-------------------------------------------------------------------------------
-- File : floppy.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This module implements the emulator of the floppy drive.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.mem_bus_pkg.all;
entity floppy is
generic (
g_big_endian : boolean;
g_tag : std_logic_vector(7 downto 0) := X"01" );
port (
clock : in std_logic;
reset : in std_logic;
tick_16MHz : in std_logic;
-- signals from MOS 6522 VIA
motor_on : in std_logic;
stepper_en : in std_logic;
mode : in std_logic;
write_prot_n : in std_logic;
side : in std_logic := '0';
step : in std_logic_vector(1 downto 0);
rate_ctrl : in std_logic_vector(1 downto 0);
byte_ready : out std_logic;
sync : out std_logic;
track : out unsigned(6 downto 0);
track_is_0 : out std_logic;
read_data : out std_logic_vector(7 downto 0);
write_data : in std_logic_vector(7 downto 0);
-- signals connected to sd-cpu
io_req_param : in t_io_req;
io_resp_param : out t_io_resp;
io_req_dirty : in t_io_req;
io_resp_dirty : out t_io_resp;
floppy_inserted : in std_logic := '0';
do_head_bang : out std_logic;
do_track_out : out std_logic;
do_track_in : out std_logic;
en_hum : out std_logic;
en_slip : out std_logic;
dirty_led_n : out std_logic;
---
mem_req : out t_mem_req;
mem_resp : in t_mem_resp );
end floppy;
architecture structural of floppy is
signal mem_rdata : std_logic_vector(7 downto 0);
signal do_read : std_logic;
signal do_write : std_logic;
signal do_advance : std_logic;
signal track_start : std_logic_vector(25 downto 0);
signal max_offset : std_logic_vector(13 downto 0);
signal track_i : unsigned(6 downto 0);
signal bit_time : unsigned(9 downto 0);
begin
en_hum <= motor_on and not floppy_inserted;
en_slip <= motor_on and floppy_inserted;
track <= track_i;
stream: entity work.floppy_stream
port map (
clock => clock,
reset => reset,
tick_16MHz => tick_16MHz,
mem_rdata => mem_rdata,
do_read => do_read,
do_write => do_write,
do_advance => do_advance,
floppy_inserted => floppy_inserted,
track => track_i,
track_is_0 => track_is_0,
do_head_bang => do_head_bang,
do_track_in => do_track_in,
do_track_out => do_track_out,
motor_on => motor_on,
stepper_en => stepper_en,
sync => sync,
mode => mode,
write_prot_n => write_prot_n,
step => step,
byte_ready => byte_ready,
rate_ctrl => rate_ctrl,
bit_time => bit_time,
read_data => read_data );
params: entity work.floppy_param_mem
generic map (
g_big_endian => g_big_endian )
port map (
clock => clock,
reset => reset,
io_req => io_req_param,
io_resp => io_resp_param,
track => track_i,
side => side,
track_start => track_start,
max_offset => max_offset,
bit_time => bit_time );
fetch_wb: entity work.floppy_mem
generic map (
g_tag => g_tag )
port map (
clock => clock,
reset => reset,
drv_rdata => mem_rdata,
drv_wdata => write_data,
do_read => do_read,
do_write => do_write,
do_advance => do_advance,
track_start => track_start,
max_offset => max_offset,
mem_req => mem_req,
mem_resp => mem_resp );
b_dirty: block
signal any_dirty : std_logic;
signal dirty_bits : std_logic_vector(127 downto 0) := (others => '0');
signal wa : integer range 0 to 127 := 0;
signal wr, wd : std_logic;
begin
process(clock)
begin
if rising_edge(clock) then
wa <= to_integer(unsigned(side & track_i(6 downto 1)));
wd <= '1';
wr <= '0';
if mode = '0' and motor_on='1' and floppy_inserted='1' then
wr <= '1';
any_dirty <= '1';
end if;
io_resp_dirty <= c_io_resp_init;
if io_req_dirty.read = '1' then
io_resp_dirty.ack <= '1';
io_resp_dirty.data(7) <= any_dirty;
io_resp_dirty.data(0) <= dirty_bits(to_integer(io_req_dirty.address(6 downto 0)));
end if;
if io_req_dirty.write = '1' then
io_resp_dirty.ack <= '1';
if io_req_dirty.data(7) = '1' then
any_dirty <= '0';
else
wa <= to_integer(io_req_dirty.address(6 downto 0));
wr <= '1';
wd <= '0';
end if;
end if;
if wr = '1' then
dirty_bits(wa) <= wd;
end if;
if reset = '1' then
any_dirty <= '0';
end if;
end if;
end process;
dirty_led_n <= not any_dirty;
end block;
end structural;
| gpl-3.0 | 2447ff794429ceae192b433c9ce2705b | 0.421815 | 3.941672 | false | false | false | false |
markusC64/1541ultimate2 | fpga/io/iec_interface/vhdl_source/iec_processor.vhd | 1 | 10,296 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity iec_processor is
port (
clock : in std_logic;
reset : in std_logic;
tick : in std_logic;
-- instruction ram interface
instr_addr : out unsigned(8 downto 0);
instr_en : out std_logic;
instr_data : in std_logic_vector(29 downto 0);
-- software fifo interface
up_fifo_full : in std_logic;
up_fifo_put : out std_logic;
up_fifo_din : out std_logic_vector(8 downto 0);
down_fifo_empty : in std_logic;
down_fifo_get : out std_logic;
down_fifo_flush : out std_logic;
down_fifo_release : in std_logic;
down_fifo_dout : in std_logic_vector(9 downto 0);
irq_event : out std_logic;
clk_o : out std_logic;
clk_i : in std_logic;
data_o : out std_logic;
data_i : in std_logic;
atn_o : out std_logic;
atn_i : in std_logic;
srq_o : out std_logic;
srq_i : in std_logic );
attribute opt_mode : string;
attribute opt_mode of iec_processor: entity is "area";
end iec_processor;
architecture mixed of iec_processor is
constant c_opc_load : std_logic_vector(3 downto 0) := X"0";
constant c_opc_pop : std_logic_vector(3 downto 0) := X"1";
constant c_opc_pushc : std_logic_vector(3 downto 0) := X"2";
constant c_opc_pushd : std_logic_vector(3 downto 0) := X"3";
constant c_opc_sub : std_logic_vector(3 downto 0) := X"4";
constant c_opc_copy_bit : std_logic_vector(3 downto 0) := X"5";
constant c_opc_irq : std_logic_vector(3 downto 0) := X"6";
constant c_opc_ret : std_logic_vector(3 downto 0) := X"7";
constant c_opc_if : std_logic_vector(3 downto 0) := X"8";
constant c_opc_clrstack : std_logic_vector(3 downto 0) := X"9";
constant c_opc_reset_st : std_logic_vector(3 downto 0) := X"D";
constant c_opc_reset_drv: std_logic_vector(3 downto 0) := X"E";
constant c_opc_wait : std_logic_vector(3 downto 0) := X"C";
signal inputs : std_logic_vector(3 downto 0);
signal inputs_raw : std_logic_vector(3 downto 0);
signal timer : unsigned(11 downto 0);
signal pc : unsigned(instr_addr'range);
signal pc_ret_std : std_logic_vector(instr_addr'range);
signal pop, push : std_logic;
signal timer_done : std_logic;
signal atn_i_d : std_logic;
signal valid_reg : std_logic := '0';
signal ctrl_reg : std_logic := '0';
signal timeout_reg : std_logic := '0';
signal flush_stack : std_logic;
type t_state is (idle, get_inst, decode, wait_true);
signal state : t_state;
signal instruction : std_logic_vector(29 downto 0);
alias a_invert : std_logic is instruction(29);
alias a_select : std_logic_vector( 4 downto 0) is instruction(28 downto 24);
alias a_opcode : std_logic_vector( 3 downto 0) is instruction(23 downto 20);
alias a_operand : std_logic_vector(11 downto 0) is instruction(19 downto 8);
alias a_mask : std_logic_vector( 3 downto 0) is instruction(7 downto 4);
alias a_value : std_logic_vector( 3 downto 0) is instruction(3 downto 0);
alias a_databyte : std_logic_vector( 7 downto 0) is instruction(7 downto 0);
signal input_vector : std_logic_vector(31 downto 0);
signal selected_bit : std_logic;
signal out_vector : std_logic_vector(19 downto 0);
alias a_drivers : std_logic_vector(3 downto 0) is out_vector(19 downto 16);
alias a_irq_enable : std_logic is out_vector(8);
alias a_eoi : std_logic is out_vector(12);
alias a_status : std_logic_vector(7 downto 0) is out_vector(15 downto 8);
alias a_data_reg : std_logic_vector(7 downto 0) is out_vector(7 downto 0);
begin
clk_o <= a_drivers(0);
data_o <= a_drivers(1);
atn_o <= a_drivers(2);
srq_o <= a_drivers(3);
inputs_raw <= srq_i & atn_i & data_i & clk_i;
inputs <= std_logic_vector(to_01(unsigned(inputs_raw)));
input_vector(31 downto 30) <= "10";
input_vector(29) <= ctrl_reg;
input_vector(28) <= valid_reg;
input_vector(27) <= timeout_reg;
input_vector(26) <= up_fifo_full;
input_vector(25) <= '1' when (inputs and a_mask) = a_value else '0';
input_vector(24) <= '1' when (a_data_reg = a_databyte) else '0';
input_vector(23 downto 20) <= inputs;
input_vector(19 downto 16) <= a_drivers;
input_vector(15 downto 8) <= a_status;
input_vector(7 downto 0) <= a_data_reg;
selected_bit <= input_vector(to_integer(unsigned(a_select))) xor a_invert;
instr_addr <= pc;
instr_en <= '1' when (state = get_inst) else '0';
instruction <= instr_data;
process(clock)
begin
if rising_edge(clock) then
up_fifo_put <= '0';
down_fifo_get <= '0';
irq_event <= '0';
flush_stack <= '0';
if down_fifo_release = '1' then
down_fifo_flush <= '0';
end if;
if tick = '1' then
if timer = 1 then
timer_done <= '1';
end if;
if timer /= 0 then
timer <= timer - 1;
end if;
end if;
case state is
when idle =>
null;
when get_inst =>
pc <= pc + 1;
state <= decode;
when decode =>
timer_done <= '0';
timer <= unsigned(a_operand);
state <= get_inst;
case a_opcode is
when c_opc_load =>
a_data_reg <= a_databyte;
when c_opc_reset_st =>
a_status <= X"01";
when c_opc_reset_drv =>
a_drivers <= "1111";
when c_opc_irq =>
irq_event <= '1';
when c_opc_pushc =>
if up_fifo_full='0' then
up_fifo_din <= '1' & a_data_reg;
up_fifo_put <= '1';
else
state <= decode;
end if;
when c_opc_pushd =>
if up_fifo_full='0' then
up_fifo_din <= '0' & a_data_reg;
up_fifo_put <= '1';
else
state <= decode;
end if;
when c_opc_pop =>
a_data_reg <= down_fifo_dout(7 downto 0);
ctrl_reg <= down_fifo_dout(8);
a_eoi <= down_fifo_dout(9);
valid_reg <= not down_fifo_empty;
-- If data byte bit 1 is set, we do not actually pop, we just read the fifo
down_fifo_get <= not down_fifo_empty and not a_databyte(1); -- only actually POP when bit 1 = 0.
if down_fifo_empty='0' or a_databyte(0)='1' then -- if there is data, or if we should not halt if there is none
state <= get_inst;
else
state <= decode;
end if;
when c_opc_copy_bit =>
out_vector(to_integer(unsigned(a_databyte(4 downto 0)))) <= selected_bit;
when c_opc_if =>
if selected_bit='1' then
pc <= unsigned(a_operand(pc'range));
end if;
when c_opc_wait =>
timeout_reg <= '0';
state <= wait_true;
when c_opc_sub =>
-- pc_ret <= pc; (will be pushed)
pc <= unsigned(a_operand(pc'range));
when c_opc_ret =>
pc <= unsigned(pc_ret_std);
when c_opc_clrstack =>
flush_stack <= '1';
when others =>
null;
end case;
when wait_true =>
if timer_done='1' then
state <= get_inst;
timeout_reg <= '1';
elsif selected_bit='1' then
state <= get_inst;
end if;
when others =>
null;
end case;
atn_i_d <= atn_i;
if atn_i='0' and atn_i_d/='0' and a_irq_enable='1' then
down_fifo_flush <= '1';
pc <= to_unsigned(1, pc'length);
state <= get_inst;
end if;
if reset='1' then
down_fifo_flush <= '1';
state <= get_inst;
pc <= (others => '0');
out_vector <= X"F0000";
end if;
end if;
end process;
push <= '1' when (state = decode) and (a_opcode = c_opc_sub) else '0';
pop <= '1' when (state = decode) and (a_opcode = c_opc_ret) else '0';
i_stack: entity work.distributed_stack
generic map (
width => pc'length,
simultaneous_pushpop => false )
port map (
clock => clock,
reset => reset,
pop => pop,
push => push,
flush => flush_stack,
data_in => std_logic_vector(pc),
data_out => pc_ret_std,
full => open,
data_valid => open );
end mixed;
| gpl-3.0 | 17a5d3763e465114046ddbe20e427ed2 | 0.452603 | 3.861965 | false | false | false | false |
ntb-ch/cb20 | FPGA_Designs/watchdog/cb20/synthesis/cb20_pwm_interface_0_avalon_slave_0_translator.vhd | 1 | 14,679 | -- cb20_pwm_interface_0_avalon_slave_0_translator.vhd
-- Generated using ACDS version 13.0sp1 232 at 2020.06.03.16:36:13
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity cb20_pwm_interface_0_avalon_slave_0_translator is
generic (
AV_ADDRESS_W : integer := 6;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 1;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 17;
UAV_BURSTCOUNT_W : integer := 3;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 0;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 1;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := '0'; -- clk.clk
reset : in std_logic := '0'; -- reset.reset
uav_address : in std_logic_vector(16 downto 0) := (others => '0'); -- avalon_universal_slave_0.address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => '0'); -- .burstcount
uav_read : in std_logic := '0'; -- .read
uav_write : in std_logic := '0'; -- .write
uav_waitrequest : out std_logic; -- .waitrequest
uav_readdatavalid : out std_logic; -- .readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => '0'); -- .byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- .readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
uav_lock : in std_logic := '0'; -- .lock
uav_debugaccess : in std_logic := '0'; -- .debugaccess
av_address : out std_logic_vector(5 downto 0); -- avalon_anti_slave_0.address
av_write : out std_logic; -- .write
av_read : out std_logic; -- .read
av_readdata : in std_logic_vector(31 downto 0) := (others => '0'); -- .readdata
av_writedata : out std_logic_vector(31 downto 0); -- .writedata
av_byteenable : out std_logic_vector(3 downto 0); -- .byteenable
av_waitrequest : in std_logic := '0'; -- .waitrequest
av_beginbursttransfer : out std_logic;
av_begintransfer : out std_logic;
av_burstcount : out std_logic_vector(0 downto 0);
av_chipselect : out std_logic;
av_clken : out std_logic;
av_debugaccess : out std_logic;
av_lock : out std_logic;
av_outputenable : out std_logic;
av_readdatavalid : in std_logic := '0';
av_response : in std_logic_vector(1 downto 0) := (others => '0');
av_writebyteenable : out std_logic_vector(3 downto 0);
av_writeresponserequest : out std_logic;
av_writeresponsevalid : in std_logic := '0';
uav_clken : in std_logic := '0';
uav_response : out std_logic_vector(1 downto 0);
uav_writeresponserequest : in std_logic := '0';
uav_writeresponsevalid : out std_logic
);
end entity cb20_pwm_interface_0_avalon_slave_0_translator;
architecture rtl of cb20_pwm_interface_0_avalon_slave_0_translator is
component altera_merlin_slave_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(16 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(5 downto 0); -- address
av_write : out std_logic; -- write
av_read : out std_logic; -- read
av_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(31 downto 0); -- writedata
av_byteenable : out std_logic_vector(3 downto 0); -- byteenable
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_writebyteenable : out std_logic_vector(3 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_chipselect : out std_logic; -- chipselect
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic; -- outputenable
uav_response : out std_logic_vector(1 downto 0); -- response
av_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response
uav_writeresponserequest : in std_logic := 'X'; -- writeresponserequest
uav_writeresponsevalid : out std_logic; -- writeresponsevalid
av_writeresponserequest : out std_logic; -- writeresponserequest
av_writeresponsevalid : in std_logic := 'X' -- writeresponsevalid
);
end component altera_merlin_slave_translator;
begin
pwm_interface_0_avalon_slave_0_translator : component altera_merlin_slave_translator
generic map (
AV_ADDRESS_W => AV_ADDRESS_W,
AV_DATA_W => AV_DATA_W,
UAV_DATA_W => UAV_DATA_W,
AV_BURSTCOUNT_W => AV_BURSTCOUNT_W,
AV_BYTEENABLE_W => AV_BYTEENABLE_W,
UAV_BYTEENABLE_W => UAV_BYTEENABLE_W,
UAV_ADDRESS_W => UAV_ADDRESS_W,
UAV_BURSTCOUNT_W => UAV_BURSTCOUNT_W,
AV_READLATENCY => AV_READLATENCY,
USE_READDATAVALID => USE_READDATAVALID,
USE_WAITREQUEST => USE_WAITREQUEST,
USE_UAV_CLKEN => USE_UAV_CLKEN,
USE_READRESPONSE => USE_READRESPONSE,
USE_WRITERESPONSE => USE_WRITERESPONSE,
AV_SYMBOLS_PER_WORD => AV_SYMBOLS_PER_WORD,
AV_ADDRESS_SYMBOLS => AV_ADDRESS_SYMBOLS,
AV_BURSTCOUNT_SYMBOLS => AV_BURSTCOUNT_SYMBOLS,
AV_CONSTANT_BURST_BEHAVIOR => AV_CONSTANT_BURST_BEHAVIOR,
UAV_CONSTANT_BURST_BEHAVIOR => UAV_CONSTANT_BURST_BEHAVIOR,
AV_REQUIRE_UNALIGNED_ADDRESSES => AV_REQUIRE_UNALIGNED_ADDRESSES,
CHIPSELECT_THROUGH_READLATENCY => CHIPSELECT_THROUGH_READLATENCY,
AV_READ_WAIT_CYCLES => AV_READ_WAIT_CYCLES,
AV_WRITE_WAIT_CYCLES => AV_WRITE_WAIT_CYCLES,
AV_SETUP_WAIT_CYCLES => AV_SETUP_WAIT_CYCLES,
AV_DATA_HOLD_CYCLES => AV_DATA_HOLD_CYCLES
)
port map (
clk => clk, -- clk.clk
reset => reset, -- reset.reset
uav_address => uav_address, -- avalon_universal_slave_0.address
uav_burstcount => uav_burstcount, -- .burstcount
uav_read => uav_read, -- .read
uav_write => uav_write, -- .write
uav_waitrequest => uav_waitrequest, -- .waitrequest
uav_readdatavalid => uav_readdatavalid, -- .readdatavalid
uav_byteenable => uav_byteenable, -- .byteenable
uav_readdata => uav_readdata, -- .readdata
uav_writedata => uav_writedata, -- .writedata
uav_lock => uav_lock, -- .lock
uav_debugaccess => uav_debugaccess, -- .debugaccess
av_address => av_address, -- avalon_anti_slave_0.address
av_write => av_write, -- .write
av_read => av_read, -- .read
av_readdata => av_readdata, -- .readdata
av_writedata => av_writedata, -- .writedata
av_byteenable => av_byteenable, -- .byteenable
av_waitrequest => av_waitrequest, -- .waitrequest
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_chipselect => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open, -- (terminated)
uav_response => open, -- (terminated)
av_response => "00", -- (terminated)
uav_writeresponserequest => '0', -- (terminated)
uav_writeresponsevalid => open, -- (terminated)
av_writeresponserequest => open, -- (terminated)
av_writeresponsevalid => '0' -- (terminated)
);
end architecture rtl; -- of cb20_pwm_interface_0_avalon_slave_0_translator
| apache-2.0 | 2db5d9aebd0f4a67eccb6bbb98e888a4 | 0.430411 | 4.340331 | false | false | false | false |
chiggs/nvc | test/regress/operator3.vhd | 5 | 934 | entity operator3 is
end entity;
architecture test of operator3 is
type int_array is array (integer range <>) of integer;
begin
process is
variable x : int_array(1 to 3);
variable y : bit_vector(1 to 3);
begin
x := (1, 2, 3);
assert x < (2, 2, 3);
assert x > (0, 0, 0);
assert x < (1, 2, 4);
assert x < (1, 2, 3, 4);
assert not (x < (1, 2));
assert x <= (1, 2, 3);
assert x >= (1, 2, 3);
assert x >= (1, 1, 1);
y := "000";
assert not (y < "000");
assert not (y < "00");
assert not ("000" < y);
assert "00" < y;
assert y <= "000";
assert not (y <= "00");
assert "000" <= y;
assert "00" <= y;
assert not (y > "000");
assert not ("000" > y);
assert y > "00";
assert not ("00" > y);
wait;
end process;
end architecture;
| gpl-3.0 | 6e8d47cdeeb7b5b086ecaa8819016e42 | 0.441113 | 3.323843 | false | false | false | false |
markusC64/1541ultimate2 | fpga/io/sampler/vhdl_sim/sampler_tb.vhd | 1 | 4,726 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.io_bus_pkg.all;
use work.mem_bus_pkg.all;
use work.sampler_pkg.all;
use work.io_bus_bfm_pkg.all;
use work.tl_flat_memory_model_pkg.all;
entity sampler_tb is
end entity;
architecture tb of sampler_tb is
signal clock : std_logic := '0';
signal reset : std_logic;
signal io_req : t_io_req;
signal io_resp : t_io_resp;
signal mem_req : t_mem_req;
signal mem_resp : t_mem_resp;
signal sample_L : signed(17 downto 0);
signal sample_R : signed(17 downto 0);
signal new_sample : std_logic;
begin
clock <= not clock after 10 ns;
reset <= '1', '0' after 100 ns;
i_dut: entity work.sampler
generic map (
g_clock_freq => 62_500_000,
g_num_voices => 8 )
port map (
clock => clock,
reset => reset,
io_req => io_req,
io_resp => io_resp,
mem_req => mem_req,
mem_resp => mem_resp,
sample_L => sample_L,
sample_R => sample_R,
new_sample => new_sample );
i_io_bfm: entity work.io_bus_bfm
generic map (
g_name => "io_bfm" )
port map (
clock => clock,
req => io_req,
resp => io_resp );
i_mem_bfm: entity work.mem_bus_slave_bfm
generic map (
g_name => "mem_bfm",
g_latency => 2 )
port map (
clock => clock,
req => mem_req,
resp => mem_resp );
test: process
variable io : p_io_bus_bfm_object;
variable mem : h_mem_object;
variable d : std_logic_vector(7 downto 0);
begin
wait until reset='0';
bind_io_bus_bfm("io_bfm", io);
bind_mem_model("mem_bfm", mem);
for i in 0 to 255 loop
d := std_logic_vector(to_signed(integer(127.0*sin(real(i) / 40.58451048843)), 8));
write_memory_8(mem, std_logic_vector(to_unsigned(16#1234500#+i, 32)), d);
end loop;
io_write(io, X"00" + c_sample_volume , X"3F");
io_write(io, X"00" + c_sample_pan , X"07");
io_write(io, X"00" + c_sample_start_addr_h , X"01");
io_write(io, X"00" + c_sample_start_addr_mh , X"23");
io_write(io, X"00" + c_sample_start_addr_ml , X"45");
io_write(io, X"00" + c_sample_start_addr_l , X"00");
io_write(io, X"00" + c_sample_length_h , X"00");
io_write(io, X"00" + c_sample_length_m , X"01");
io_write(io, X"00" + c_sample_length_l , X"00");
io_write(io, X"00" + c_sample_rate_h , X"00");
io_write(io, X"00" + c_sample_rate_l , X"18");
io_write(io, X"00" + c_sample_control , X"01");
io_write(io, X"20" + c_sample_volume , X"28");
io_write(io, X"20" + c_sample_pan , X"0F");
io_write(io, X"20" + c_sample_start_addr_h , X"01");
io_write(io, X"20" + c_sample_start_addr_mh , X"23");
io_write(io, X"20" + c_sample_start_addr_ml , X"45");
io_write(io, X"20" + c_sample_start_addr_l , X"00");
io_write(io, X"20" + c_sample_length_h , X"00");
io_write(io, X"20" + c_sample_length_m , X"01");
io_write(io, X"20" + c_sample_length_l , X"00");
io_write(io, X"20" + c_sample_rate_h , X"00");
io_write(io, X"20" + c_sample_rate_l , X"05");
io_write(io, X"20" + c_sample_rep_b_pos_l , X"CC");
io_write(io, X"20" + c_sample_control , X"03"); -- repeat on
io_write(io, X"E0" + c_sample_volume , X"38");
io_write(io, X"E0" + c_sample_pan , X"04");
io_write(io, X"E0" + c_sample_start_addr_h , X"01");
io_write(io, X"E0" + c_sample_start_addr_mh , X"23");
io_write(io, X"E0" + c_sample_start_addr_ml , X"45");
io_write(io, X"E0" + c_sample_start_addr_l , X"00");
io_write(io, X"E0" + c_sample_length_h , X"00");
io_write(io, X"E0" + c_sample_length_m , X"00");
io_write(io, X"E0" + c_sample_length_l , X"80");
io_write(io, X"E0" + c_sample_rate_h , X"00");
io_write(io, X"E0" + c_sample_rate_l , X"09");
io_write(io, X"E0" + c_sample_rep_b_pos_l , X"80");
io_write(io, X"E0" + c_sample_control , X"13"); -- repeat on, 16 bit
wait;
end process;
end architecture;
| gpl-3.0 | c423979d677f3954bd147b5994cc176b | 0.481591 | 2.841852 | false | false | false | false |
markusC64/1541ultimate2 | fpga/sid6581/vhdl_sim/tb_sid_from_file.vhd | 1 | 5,002 | -------------------------------------------------------------------------------
-- Date $Date: 2005/04/12 19:09:27 $
-- Author $Author: Gideon $
-- Revision $Revision: 1.1 $
-- Log $Log: oscillator.vhd,v $
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.tl_flat_memory_model_pkg.all;
use work.wave_pkg.all;
entity tb_sid_from_file is
end tb_sid_from_file;
architecture tb of tb_sid_from_file is
signal clock : std_logic := '0';
signal reset : std_logic;
signal addr : unsigned(7 downto 0) := (others => '0');
signal wren : std_logic := '0';
signal wdata : std_logic_vector(7 downto 0) := (others => '0');
signal rdata : std_logic_vector(7 downto 0) := (others => '0');
signal start_iter : std_logic := '0';
signal sid_pwm : std_logic := '0';
signal sample_out : signed(17 downto 0);
signal stop_clock : boolean := false;
signal vc : real := 0.0;
constant R : real := 2200.0;
constant C : real := 0.000000022;
constant c_cpu_period : time := 1014973 ps;
constant c_half_clock : time := c_cpu_period / 8;
constant c_clock : time := c_half_clock * 2;
begin
clock <= not clock after c_half_clock when not stop_clock; -- 5 MHz
reset <= '1', '0' after 1 us;
sid: entity work.sid_top
generic map (
g_num_voices => 8 )
port map (
clock => clock,
reset => reset,
addr => addr,
wren => wren,
wdata => wdata,
rdata => rdata,
start_iter => start_iter,
sample_left => sample_out );
-- i_pdm_sid: entity work.sigma_delta_dac
-- generic map (
-- g_left_shift => 0,
-- g_width => sample_out'length )
-- port map (
-- clock => clock,
-- reset => reset,
--
-- dac_in => sample_out,
--
-- dac_out => sid_pwm );
--
-- filter: process(clock)
-- variable v_dac : real;
-- variable i_r : real;
-- variable q_c : real;
-- begin
-- if rising_edge(clock) then
-- if sid_pwm='0' then
-- v_dac := -1.2;
-- else
-- v_dac := 1.2;
-- end if;
-- i_r := (v_dac - vc) / R;
-- q_c := i_r * 200.0e-9; -- 200 ns;
-- vc <= vc + (q_c / C);
-- end if;
-- end process;
--
test: process
variable trace_in : h_mem_object;
variable addr_i : integer := 0;
variable delay : time := 1 ns;
variable t : unsigned(23 downto 0);
variable b : std_logic_vector(7 downto 0);
begin
register_mem_model(tb_sid_from_file'path_name, "trace", trace_in);
load_memory("sidtrace.555", trace_in, X"00000000");
wait until reset='0';
wait until clock='1';
L1: while now < 5000 ms loop
b := read_memory_8(trace_in, std_logic_vector(to_unsigned(addr_i, 32)));
addr <= unsigned(b(7 downto 0));
wdata <= read_memory_8(trace_in, std_logic_vector(to_unsigned(addr_i+1, 32)));
t(23 downto 16) := unsigned(read_memory_8(trace_in, std_logic_vector(to_unsigned(addr_i+2, 32))));
t(15 downto 8) := unsigned(read_memory_8(trace_in, std_logic_vector(to_unsigned(addr_i+3, 32))));
t( 7 downto 0) := unsigned(read_memory_8(trace_in, std_logic_vector(to_unsigned(addr_i+4, 32))));
addr_i := addr_i + 5;
if t = 0 then
exit L1;
end if;
delay := (1 us) * (to_integer(t)-1);
wait for delay;
wren <= '1';
wait for 1 * c_clock;
wren <= '0';
wait for 7 * c_clock;
end loop;
stop_clock <= true;
wait;
end process test;
process
begin
wait for 7 * c_clock;
start_iter <= '1';
wait for 1 * c_clock;
start_iter <= '0';
if stop_clock then
wait;
end if;
end process;
-- this clock is a little faster (1 Mhz instead of 985250 Hz, thus we need to adjust our sample rate by the same amount
-- which means we need to sample at 48718 Hz instead of 48kHz. Sample period =
process
variable chan : t_wave_channel;
begin
open_channel(chan);
while not stop_clock loop
wait for 20833 ns; -- 20526 ns;
push_sample(chan, to_integer(sample_out(17 downto 2)));
end loop;
write_wave("sid_wave.wav", 48000, (0 => chan));
wait;
end process;
end tb;
| gpl-3.0 | 9628d5cfa25efd7f4d869952d0af9012 | 0.470612 | 3.527504 | false | false | false | false |
chiggs/nvc | test/sem/ports.vhd | 1 | 7,891 | package foo_pkg is
type my_int is range 0 to 100;
subtype my_int_sub is my_int range 10 to 20;
end package;
-------------------------------------------------------------------------------
use work.foo_pkg.all;
entity foo is
port (
o : out my_int;
i : in my_int );
end entity;
-------------------------------------------------------------------------------
architecture bar of foo is
begin
process is
variable x : my_int;
begin
x := i; -- OK
end process;
process is
variable x : my_int;
begin
-- Cannot read output
x := o;
end process;
process is
begin
o <= 24; -- OK
end process;
process is
begin
-- Cannot assign input
i <= 23;
end process;
end architecture;
-------------------------------------------------------------------------------
entity top is generic (str : string := "boo");
end entity;
use work.foo_pkg.all;
architecture test of top is
component foo is
port (
o : out my_int;
i : in my_int );
end component;
type int_vec is array (integer range <>) of integer;
component bar is
port (
i : in int_vec(1 to 10);
o : out int_vec(1 to 2) );
end component;
signal x, y : my_int;
begin
foo1: entity work.foo -- OK
port map (
o => x,
i => y );
foo2: entity work.foo -- OK
port map ( x, y );
foo3: entity work.foo
; -- Missing i association
foo4: entity work.foo -- Two associations for i
port map ( i => x, i => y,
o => x );
foo5: entity work.foo -- Too many ports
port map ( x, y, x, y );
foo6: entity work.foo -- No port cake
port map ( cake => 4 );
bad1: entity work.bad; -- No such entity
open1: entity work.foo -- OK
port map (
i => x,
o => open );
open2: entity work.foo -- Cannot use OPEN with input
port map (
i => open,
o => open );
foo7: foo -- OK
port map (
o => x,
i => y );
foo8: component foo -- OK
port map (
o => x,
i => y );
bad2: component x -- Not component
port map (
a => 1,
b => 2 );
b1: block is
signal x : int_vec(1 to 10);
signal y : int_vec(1 to 2);
signal k : integer;
begin
bar1: bar -- OK
port map (
o(1 to 10) => x(1 to 10),
i(1 to 2) => y(1 to 2) );
bar2: bar -- OK
port map (
o(1 to 4) => x(1 to 4),
o(5 to 10) => x(5 to 10),
i(1 to 2) => y(1 to 2) );
bar3: bar
port map (
o(1) => x(1),
o(2) => x(2),
o(3 to 10) => x(3 to 10),
i => y );
bar4: bar
port map (
o(1) => x(1),
o(2) => x(k), -- Error
o(3 to 10) => x(3 to 10),
i => y );
bar5: bar
port map (
o(1) => x(1),
o(q) => x(2), -- Error
o(3 to 10) => x(3 to 10),
i => y );
bar6: bar
port map (
o(1) => x(1),
o(2) => x(2),
o(3 to u) => x(3 to 10), -- Error
i => y );
bar7: bar
port map (
o(k) => x(1), -- Error
o(2) => x(2),
o(3 to 10) => x(3 to 10),
i => y );
bar8: bar
port map (
o(1) => x(1),
o(2) => x(2),
o(3 to k) => x(3 to 10), -- Error
i => y );
end block;
foo9: foo -- Error
port map (
o => x,
i => hello(5) );
foo10: foo
port map (
i => y ); -- OK
end architecture;
-------------------------------------------------------------------------------
architecture other of top is
type int_vec is array (integer range <>) of integer;
component comp1 is
port (
a : in integer := 5;
o : out int_vec );
end component;
signal s : int_vec(1 to 3);
begin
c1: component comp1 -- OK
port map (
a => open,
o => s );
c2: component comp1
port map (
a => 5,
o => open ); -- Error
c3: component comp1
port map (
a => 1.0, -- Error
o => s );
end architecture;
-------------------------------------------------------------------------------
architecture conv of top is
type int_vec1 is array (integer range <>) of integer;
type int_vec2 is array (integer range <>) of integer;
type my_int1 is range 0 to 1;
component comp1 is
port (
i : in int_vec1(1 to 3);
n : in my_int1 := 5;
o : out int_vec2(1 to 3) );
end component;
component comp2 is
port (
i : in int_vec1 );
end component;
component comp3 is
port (
b : out bit );
end component;
component comp4 is
port (
b : inout bit );
end component;
function func1(x : in bit) return my_int1;
function func2(x : in bit; y : in integer := 5) return my_int1;
function func3(x : in bit) return integer;
function func4(x : in integer) return bit;
signal x : int_vec1(1 to 3);
signal y : int_vec2(1 to 3);
signal z : bit;
signal i : integer;
begin
c1: component comp1
port map ( i => int_vec1(y) ); -- OK
c2: component comp2
port map ( i => int_vec1(y) ); -- Error
c3: component comp1
port map ( i => x,
n => func1(z) ); -- OK
c4: component comp1
port map ( i => x,
n => func2(z) ); -- Error
c6: component comp1
port map ( i => int_vec1(y),
o => int_vec2(x) ); -- Error
c7: component comp3
port map ( func3(b) => i ); -- OK
c8: component comp1
port map ( i => (1, 1, 1),
int_vec1(o) => x ); -- OK
c9: component comp1
port map ( int_vec2(i) => y, -- Error
int_vec1(o) => x );
c10: component comp3
port map ( func3(b) => open ); -- Error
c11: component comp4
port map ( func3(b) => func4(i) ); -- OK
end architecture;
entity ent_with_vec is
port ( x : in bit_vector(3 downto 0);
y : out bit_vector(3 downto 0) );
end entity;
architecture test of ent_with_vec is
begin
x(1) <= '0'; -- Error
y(1) <= y(0); -- Error
end architecture;
-------------------------------------------------------------------------------
architecture other2 of top is
procedure assign(x : out integer) is
begin
x := 5;
end procedure;
procedure assign_and_check(x : inout integer) is
begin
assign(x); -- OK
assert x = 5;
end procedure;
procedure bad(x : in integer) is
begin
assign(x);
end procedure;
begin
end architecture;
| gpl-3.0 | 609d4a5a3926878e79a6ba341f290de4 | 0.379039 | 4.021916 | false | false | false | false |
markusC64/1541ultimate2 | fpga/fpga_top/cyclone4_test/vhdl_source/u2p_tester.vhd | 1 | 37,531 | -------------------------------------------------------------------------------
-- Title : u2p_tester
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: Toplevel for u2p_tester.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.io_bus_pkg.all;
use work.mem_bus_pkg.all;
use work.endianness_pkg.all;
entity u2p_tester is
port (
-- slot side
SLOT_PHI2 : in std_logic;
SLOT_DOTCLK : in std_logic;
SLOT_RSTn : in std_logic;
SLOT_BUFFER_ENn : out std_logic;
SLOT_ADDR : inout std_logic_vector(15 downto 0);
SLOT_DATA : inout std_logic_vector(7 downto 0);
SLOT_RWn : in std_logic;
SLOT_BA : in std_logic;
SLOT_DMAn : in std_logic;
SLOT_EXROMn : out std_logic;
SLOT_GAMEn : inout std_logic;
SLOT_ROMHn : out std_logic;
SLOT_ROMLn : out std_logic;
SLOT_IO1n : in std_logic;
SLOT_IO2n : out std_logic;
SLOT_IRQn : in std_logic;
SLOT_NMIn : out std_logic;
SLOT_VCC : in std_logic;
-- memory
SDRAM_A : out std_logic_vector(13 downto 0); -- DRAM A
SDRAM_BA : out std_logic_vector(2 downto 0) := (others => '0');
SDRAM_DQ : inout std_logic_vector(7 downto 0);
SDRAM_DM : inout std_logic;
SDRAM_CSn : out std_logic;
SDRAM_RASn : out std_logic;
SDRAM_CASn : out std_logic;
SDRAM_WEn : out std_logic;
SDRAM_CKE : out std_logic;
SDRAM_CLK : inout std_logic;
SDRAM_CLKn : inout std_logic;
SDRAM_ODT : out std_logic;
SDRAM_DQS : inout std_logic;
AUDIO_MCLK : out std_logic := '0';
AUDIO_BCLK : out std_logic := '0';
AUDIO_LRCLK : out std_logic := '0';
AUDIO_SDO : out std_logic := '0';
AUDIO_SDI : in std_logic;
-- IEC bus
IEC_ATN : inout std_logic;
IEC_DATA : inout std_logic;
IEC_CLOCK : inout std_logic;
IEC_RESET : in std_logic;
IEC_SRQ_IN : inout std_logic;
LED_DISKn : out std_logic; -- activity LED
LED_CARTn : out std_logic;
LED_SDACTn : out std_logic;
LED_MOTORn : out std_logic;
-- Ethernet RMII
ETH_RESETn : out std_logic := '1';
ETH_IRQn : in std_logic;
RMII_REFCLK : in std_logic;
RMII_CRS_DV : in std_logic;
RMII_RX_ER : in std_logic;
RMII_RX_DATA : in std_logic_vector(1 downto 0);
RMII_TX_DATA : out std_logic_vector(1 downto 0);
RMII_TX_EN : out std_logic;
MDIO_CLK : out std_logic := '0';
MDIO_DATA : inout std_logic := 'Z';
-- Speaker data
SPEAKER_DATA : out std_logic := '0';
SPEAKER_ENABLE : out std_logic := '0';
-- Debug UART
UART_TXD : out std_logic;
UART_RXD : inout std_logic;
-- I2C Interface for RTC, audio codec and usb hub
I2C_SDA : inout std_logic := 'Z';
I2C_SCL : inout std_logic := 'Z';
I2C_SDA_18 : inout std_logic := 'Z';
I2C_SCL_18 : inout std_logic := 'Z';
-- Flash Interface
FLASH_CSn : out std_logic;
FLASH_SCK : out std_logic;
FLASH_MOSI : out std_logic;
FLASH_MISO : in std_logic;
FLASH_SEL : out std_logic := '0';
FLASH_SELCK : out std_logic := '0';
-- USB Interface (ULPI)
ULPI_RESET : out std_logic;
ULPI_CLOCK : in std_logic;
ULPI_NXT : in std_logic;
ULPI_STP : out std_logic;
ULPI_DIR : in std_logic;
ULPI_DATA : inout std_logic_vector(7 downto 0);
HUB_RESETn : out std_logic := '1';
HUB_CLOCK : out std_logic := '0';
-- Misc
BOARD_REVn : in std_logic_vector(4 downto 0);
-- Cassette Interface
CAS_MOTOR : in std_logic := '0';
CAS_SENSE : inout std_logic := 'Z';
CAS_READ : inout std_logic := 'Z';
CAS_WRITE : inout std_logic := 'Z';
-- Buttons
BUTTON : in std_logic_vector(2 downto 0));
end entity;
architecture rtl of u2p_tester is
component nios_tester is
port (
audio_in_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- data
audio_in_valid : in std_logic := 'X'; -- valid
audio_in_ready : out std_logic; -- ready
audio_out_data : out std_logic_vector(31 downto 0); -- data
audio_out_valid : out std_logic; -- valid
audio_out_ready : in std_logic := 'X'; -- ready
dummy_export : in std_logic := 'X'; -- export
io_ack : in std_logic := 'X'; -- ack
io_rdata : in std_logic_vector(7 downto 0) := (others => 'X'); -- rdata
io_read : out std_logic; -- read
io_wdata : out std_logic_vector(7 downto 0); -- wdata
io_write : out std_logic; -- write
io_address : out std_logic_vector(19 downto 0); -- address
io_irq : in std_logic := 'X'; -- irq
io_u2p_ack : in std_logic := 'X'; -- ack
io_u2p_rdata : in std_logic_vector(7 downto 0) := (others => 'X'); -- rdata
io_u2p_read : out std_logic; -- read
io_u2p_wdata : out std_logic_vector(7 downto 0); -- wdata
io_u2p_write : out std_logic; -- write
io_u2p_address : out std_logic_vector(19 downto 0); -- address
io_u2p_irq : in std_logic := 'X'; -- irq
jtag0_jtag_tck : out std_logic; -- jtag_tck
jtag0_jtag_tms : out std_logic; -- jtag_tms
jtag0_jtag_tdi : out std_logic; -- jtag_tdi
jtag0_jtag_tdo : in std_logic := 'X'; -- jtag_tdo
jtag1_jtag_tck : out std_logic; -- jtag_tck
jtag1_jtag_tms : out std_logic; -- jtag_tms
jtag1_jtag_tdi : out std_logic; -- jtag_tdi
jtag1_jtag_tdo : in std_logic := 'X'; -- jtag_tdo
jtag_in_data : in std_logic_vector(7 downto 0) := (others => 'X'); -- data
jtag_in_valid : in std_logic := 'X'; -- valid
jtag_in_ready : out std_logic; -- ready
mem_mem_req_address : out std_logic_vector(25 downto 0); -- mem_req_address
mem_mem_req_byte_en : out std_logic_vector(3 downto 0); -- mem_req_byte_en
mem_mem_req_read_writen : out std_logic; -- mem_req_read_writen
mem_mem_req_request : out std_logic; -- mem_req_request
mem_mem_req_tag : out std_logic_vector(7 downto 0); -- mem_req_tag
mem_mem_req_wdata : out std_logic_vector(31 downto 0); -- mem_req_wdata
mem_mem_resp_dack_tag : in std_logic_vector(7 downto 0) := (others => 'X'); -- mem_resp_dack_tag
mem_mem_resp_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- mem_resp_data
mem_mem_resp_rack_tag : in std_logic_vector(7 downto 0) := (others => 'X'); -- mem_resp_rack_tag
pio_in_port : in std_logic_vector(31 downto 0) := (others => 'X'); -- in_port
pio_out_port : out std_logic_vector(31 downto 0); -- out_port
spi_MISO : in std_logic := 'X'; -- MISO
spi_MOSI : out std_logic; -- MOSI
spi_SCLK : out std_logic; -- SCLK
spi_SS_n : out std_logic; -- SS_n
sys_clock_clk : in std_logic := 'X'; -- clk
sys_reset_reset_n : in std_logic := 'X' -- reset_n
-- uart_rxd : in std_logic := 'X'; -- rxd
-- uart_txd : out std_logic; -- txd
-- uart_cts_n : in std_logic := 'X'; -- cts_n
-- uart_rts_n : out std_logic -- rts_n
);
end component nios_tester;
component pll
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
end component;
signal por_n : std_logic;
signal ref_reset : std_logic;
signal por_count : unsigned(19 downto 0) := (others => '0');
signal sys_clock : std_logic;
signal sys_reset : std_logic;
signal audio_clock : std_logic;
signal audio_reset : std_logic;
signal eth_reset : std_logic;
signal ulpi_reset_req : std_logic;
-- miscellaneous interconnect
signal ulpi_reset_i : std_logic;
-- memory controller interconnect
signal memctrl_inhibit : std_logic;
signal is_idle : std_logic;
signal mem_req : t_mem_req_32;
signal mem_resp : t_mem_resp_32;
signal cpu_mem_req : t_mem_req_32;
signal cpu_mem_resp : t_mem_resp_32;
signal i2c_sda_i : std_logic;
signal i2c_sda_o : std_logic;
signal i2c_scl_i : std_logic;
signal i2c_scl_o : std_logic;
signal mdio_o : std_logic;
-- io buses
signal io_irq : std_logic;
signal io_req : t_io_req;
signal io_resp : t_io_resp;
signal io_u2p_req : t_io_req;
signal io_u2p_resp : t_io_resp;
signal io_req_new_io : t_io_req;
signal io_resp_new_io : t_io_resp;
signal io_req_remote : t_io_req;
signal io_resp_remote : t_io_resp;
signal io_req_ddr2 : t_io_req;
signal io_resp_ddr2 : t_io_resp;
-- misc io
signal audio_in_data : std_logic_vector(31 downto 0) := (others => '0'); -- data
signal audio_in_valid : std_logic := '0'; -- valid
signal audio_in_ready : std_logic; -- ready
signal audio_out_data : std_logic_vector(31 downto 0) := (others => '0'); -- data
signal audio_out_valid : std_logic; -- valid
signal audio_out_ready : std_logic := '0'; -- ready
signal jtag0_jtag_tck : std_logic; -- jtag_tck
signal jtag0_jtag_tms : std_logic; -- jtag_tms
signal jtag0_jtag_tdi : std_logic; -- jtag_tdi
signal jtag0_jtag_tdo : std_logic := 'X'; -- jtag_tdo
signal jtag1_jtag_tck : std_logic; -- jtag_tck
signal jtag1_jtag_tms : std_logic; -- jtag_tms
signal jtag1_jtag_tdi : std_logic; -- jtag_tdi
signal jtag1_jtag_tdo : std_logic := 'X'; -- jtag_tdo
signal pio_in_port : std_logic_vector(31 downto 0) := (others => 'X'); -- in_port
signal pio_out_port : std_logic_vector(31 downto 0); -- out_port
signal spi_MISO : std_logic := 'X'; -- MISO
signal spi_MOSI : std_logic; -- MOSI
signal spi_SCLK : std_logic; -- SCLK
signal spi_SS_n : std_logic; -- SS_n
-- signal prim_uart_rxd : std_logic := '1';
-- signal prim_uart_txd : std_logic := '1';
-- signal prim_uart_cts_n : std_logic := '1';
-- signal prim_uart_rts_n : std_logic := '1';
signal io_uart_rxd : std_logic := '1';
signal io_uart_txd : std_logic := '1';
signal jtag_in_data : std_logic_vector(7 downto 0) := (others => 'X'); -- data
signal jtag_in_valid : std_logic := 'X'; -- valid
signal jtag_in_ready : std_logic; -- ready
-- Parallel cable connection
signal drv_via1_port_a_o : std_logic_vector(7 downto 0);
signal drv_via1_port_a_i : std_logic_vector(7 downto 0);
signal drv_via1_port_a_t : std_logic_vector(7 downto 0);
signal drv_via1_ca2_o : std_logic;
signal drv_via1_ca2_i : std_logic;
signal drv_via1_ca2_t : std_logic;
signal drv_via1_cb1_o : std_logic;
signal drv_via1_cb1_i : std_logic;
signal drv_via1_cb1_t : std_logic;
signal eth_tx_data : std_logic_vector(7 downto 0);
signal eth_tx_last : std_logic;
signal eth_tx_valid : std_logic;
signal eth_tx_ready : std_logic := '1';
signal eth_rx_data : std_logic_vector(7 downto 0);
signal eth_rx_sof : std_logic;
signal eth_rx_eof : std_logic;
signal eth_rx_valid : std_logic;
signal rxd_drive : std_logic;
begin
process(RMII_REFCLK)
begin
if rising_edge(RMII_REFCLK) then
if por_count = X"FFFFF" then
por_n <= '1';
else
por_n <= '0';
por_count <= por_count + 1;
rxd_drive <= BUTTON(0);
end if;
end if;
end process;
ref_reset <= not por_n;
i_pll: pll port map (
inclk0 => RMII_REFCLK, -- 50 MHz
c0 => HUB_CLOCK, -- 24 MHz
c1 => audio_clock, -- 12.245 MHz (47.831 kHz sample rate)
locked => open );
i_audio_reset: entity work.level_synchronizer
generic map ('1')
port map (
clock => audio_clock,
input => sys_reset,
input_c => audio_reset );
i_ulpi_reset: entity work.level_synchronizer
generic map ('1')
port map (
clock => ulpi_clock,
input => ulpi_reset_req,
input_c => ulpi_reset_i );
i_eth_reset: entity work.level_synchronizer
generic map ('1')
port map (
clock => RMII_REFCLK,
input => sys_reset,
input_c => eth_reset );
i_nios: nios_tester
port map (
audio_in_data => audio_in_data,
audio_in_valid => audio_in_valid,
audio_in_ready => audio_in_ready,
audio_out_data => audio_out_data,
audio_out_valid => audio_out_valid,
audio_out_ready => audio_out_ready,
dummy_export => '0',
io_u2p_ack => io_u2p_resp.ack,
io_u2p_rdata => io_u2p_resp.data,
io_u2p_read => io_u2p_req.read,
io_u2p_wdata => io_u2p_req.data,
io_u2p_write => io_u2p_req.write,
unsigned(io_u2p_address) => io_u2p_req.address,
io_u2p_irq => '0',
io_ack => io_resp.ack,
io_rdata => io_resp.data,
io_read => io_req.read,
io_wdata => io_req.data,
io_write => io_req.write,
unsigned(io_address) => io_req.address,
io_irq => io_irq,
jtag0_jtag_tck => jtag0_jtag_tck,
jtag0_jtag_tms => jtag0_jtag_tms,
jtag0_jtag_tdi => jtag0_jtag_tdi,
jtag0_jtag_tdo => jtag0_jtag_tdo,
jtag1_jtag_tck => jtag1_jtag_tck,
jtag1_jtag_tms => jtag1_jtag_tms,
jtag1_jtag_tdi => jtag1_jtag_tdi,
jtag1_jtag_tdo => jtag1_jtag_tdo,
jtag_in_data => jtag_in_data,
jtag_in_valid => jtag_in_valid,
jtag_in_ready => jtag_in_ready,
unsigned(mem_mem_req_address) => cpu_mem_req.address,
mem_mem_req_byte_en => cpu_mem_req.byte_en,
mem_mem_req_read_writen => cpu_mem_req.read_writen,
mem_mem_req_request => cpu_mem_req.request,
mem_mem_req_tag => cpu_mem_req.tag,
mem_mem_req_wdata => cpu_mem_req.data,
mem_mem_resp_dack_tag => cpu_mem_resp.dack_tag,
mem_mem_resp_data => cpu_mem_resp.data,
mem_mem_resp_rack_tag => cpu_mem_resp.rack_tag,
pio_in_port => pio_in_port,
pio_out_port => pio_out_port,
spi_MISO => spi_miso,
spi_MOSI => spi_mosi,
spi_SCLK => spi_sclk,
spi_SS_n => spi_ss_n,
sys_clock_clk => sys_clock,
sys_reset_reset_n => not sys_reset
-- uart_rxd => prim_uart_rxd,
-- uart_txd => prim_uart_txd,
-- uart_cts_n => prim_uart_cts_n,
-- uart_rts_n => prim_uart_rts_n
);
-- UART_TXD <= prim_uart_txd;
i_split: entity work.io_bus_splitter
generic map (
g_range_lo => 8,
g_range_hi => 10,
g_ports => 3
)
port map (
clock => sys_clock,
req => io_u2p_req,
resp => io_u2p_resp,
reqs(0) => io_req_new_io,
reqs(1) => io_req_ddr2,
reqs(2) => io_req_remote,
resps(0) => io_resp_new_io,
resps(1) => io_resp_ddr2,
resps(2) => io_resp_remote
);
i_memphy: entity work.ddr2_ctrl
port map (
ref_clock => RMII_REFCLK,
ref_reset => ref_reset,
sys_clock_o => sys_clock,
sys_reset_o => sys_reset,
clock => sys_clock,
reset => sys_reset,
io_req => io_req_ddr2,
io_resp => io_resp_ddr2,
inhibit => '0', --memctrl_inhibit,
is_idle => is_idle,
req => mem_req,
resp => mem_resp,
SDRAM_CLK => SDRAM_CLK,
SDRAM_CLKn => SDRAM_CLKn,
SDRAM_CKE => SDRAM_CKE,
SDRAM_ODT => SDRAM_ODT,
SDRAM_CSn => SDRAM_CSn,
SDRAM_RASn => SDRAM_RASn,
SDRAM_CASn => SDRAM_CASn,
SDRAM_WEn => SDRAM_WEn,
SDRAM_A => SDRAM_A,
SDRAM_BA => SDRAM_BA(1 downto 0),
SDRAM_DM => SDRAM_DM,
SDRAM_DQ => SDRAM_DQ,
SDRAM_DQS => SDRAM_DQS
);
i_remote: entity work.update_io
port map (
clock => sys_clock,
reset => sys_reset,
slow_clock => audio_clock,
slow_reset => audio_reset,
io_req => io_req_remote,
io_resp => io_resp_remote,
flash_selck => FLASH_SELCK,
flash_sel => FLASH_SEL
);
i_u2p_io: entity work.u2p_io
port map (
clock => sys_clock,
reset => sys_reset,
io_req => io_req_new_io,
io_resp => io_resp_new_io,
mdc => MDIO_CLK,
mdio_i => MDIO_DATA,
mdio_o => mdio_o,
i2c_scl_i => i2c_scl_i,
i2c_scl_o => i2c_scl_o,
i2c_sda_i => i2c_sda_i,
i2c_sda_o => i2c_sda_o,
iec_i => "1111",
board_rev => not BOARD_REVn,
iec_o => open,
eth_irq_i => ETH_IRQn,
speaker_en => SPEAKER_ENABLE,
hub_reset_n=> HUB_RESETn,
ulpi_reset => ulpi_reset_req
);
i2c_scl_i <= I2C_SCL and I2C_SCL_18;
i2c_sda_i <= I2C_SDA and I2C_SDA_18;
I2C_SCL <= '0' when i2c_scl_o = '0' else 'Z';
I2C_SDA <= '0' when i2c_sda_o = '0' else 'Z';
I2C_SCL_18 <= '0' when i2c_scl_o = '0' else 'Z';
I2C_SDA_18 <= '0' when i2c_sda_o = '0' else 'Z';
MDIO_DATA <= '0' when mdio_o = '0' else 'Z';
i_logic: entity work.ultimate_logic_32
generic map (
g_version => X"70",
g_simulation => false,
g_ultimate2plus => true,
g_clock_freq => 62_500_000,
g_numerator => 32,
g_denominator => 125,
g_baud_rate => 115_200,
g_timer_rate => 200_000,
g_microblaze => false,
g_big_endian => false,
g_icap => false,
g_uart => true,
g_uart_rx => true,
g_drive_1541 => false,
g_drive_1541_2 => false,
g_hardware_gcr => false,
g_ram_expansion => false,
g_extended_reu => false,
g_stereo_sid => false,
g_hardware_iec => false,
g_c2n_streamer => false,
g_c2n_recorder => false,
g_cartridge => false,
g_command_intf => false,
g_drive_sound => false,
g_rtc_chip => false,
g_rtc_timer => false,
g_usb_host2 => true,
g_spi_flash => true,
g_vic_copper => false,
g_video_overlay => false,
g_sampler => false,
g_rmii => true )
port map (
-- globals
sys_clock => sys_clock,
sys_reset => sys_reset,
ulpi_clock => ulpi_clock,
ulpi_reset => ulpi_reset_i,
ext_io_req => io_req,
ext_io_resp => io_resp,
ext_mem_req => cpu_mem_req,
ext_mem_resp=> cpu_mem_resp,
cpu_irq => io_irq,
-- local bus side
mem_req => mem_req,
mem_resp => mem_resp,
-- Debug UART
UART_TXD => io_uart_txd,
UART_RXD => io_uart_rxd,
-- Flash Interface
FLASH_CSn => FLASH_CSn,
FLASH_SCK => FLASH_SCK,
FLASH_MOSI => FLASH_MOSI,
FLASH_MISO => FLASH_MISO,
-- USB Interface (ULPI)
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP,
ULPI_DIR => ULPI_DIR,
ULPI_DATA => ULPI_DATA,
-- Parallel cable pins
drv_via1_port_a_o => drv_via1_port_a_o,
drv_via1_port_a_i => drv_via1_port_a_i,
drv_via1_port_a_t => drv_via1_port_a_t,
drv_via1_ca2_o => drv_via1_ca2_o,
drv_via1_ca2_i => drv_via1_ca2_i,
drv_via1_ca2_t => drv_via1_ca2_t,
drv_via1_cb1_o => drv_via1_cb1_o,
drv_via1_cb1_i => drv_via1_cb1_i,
drv_via1_cb1_t => drv_via1_cb1_t,
-- Ethernet interface
eth_clock => RMII_REFCLK,
eth_reset => eth_reset,
eth_rx_data => eth_rx_data,
eth_rx_sof => eth_rx_sof,
eth_rx_eof => eth_rx_eof,
eth_rx_valid => eth_rx_valid,
eth_tx_data => eth_tx_data,
eth_tx_eof => eth_tx_last,
eth_tx_valid => eth_tx_valid,
eth_tx_ready => eth_tx_ready,
-- Buttons
BUTTON => not BUTTON );
-- Parallel cable not implemented. This is the way to stub it...
drv_via1_port_a_i <= drv_via1_port_a_o or not drv_via1_port_a_t;
drv_via1_ca2_i <= drv_via1_ca2_o or not drv_via1_ca2_t;
drv_via1_cb1_i <= drv_via1_cb1_o or not drv_via1_cb1_t;
-- Transceiver
i_rmii: entity work.rmii_transceiver
port map (
clock => RMII_REFCLK,
reset => eth_reset,
rmii_crs_dv => RMII_CRS_DV,
rmii_rxd => RMII_RX_DATA,
rmii_tx_en => RMII_TX_EN,
rmii_txd => RMII_TX_DATA,
eth_rx_data => eth_rx_data,
eth_rx_sof => eth_rx_sof,
eth_rx_eof => eth_rx_eof,
eth_rx_valid => eth_rx_valid,
eth_tx_data => eth_tx_data,
eth_tx_eof => eth_tx_last,
eth_tx_valid => eth_tx_valid,
eth_tx_ready => eth_tx_ready,
ten_meg_mode => '0' );
-- i_pwm0: entity work.sigma_delta_dac --delta_sigma_2to5
-- generic map (
-- g_left_shift => 2,
-- g_width => audio_speaker'length )
-- port map (
-- clock => sys_clock,
-- reset => sys_reset,
--
-- dac_in => audio_speaker,
--
-- dac_out => SPEAKER_DATA );
LED_MOTORn <= not pio_out_port(0);
LED_DISKn <= not pio_out_port(1);
LED_CARTn <= not pio_out_port(2);
LED_SDACTn <= not pio_out_port(3);
IEC_SRQ_IN <= 'Z';
IEC_ATN <= 'Z';
IEC_DATA <= 'Z';
IEC_CLOCK <= 'Z';
pio_in_port(2 downto 0) <= not BUTTON;
ULPI_RESET <= por_n;
b_audio: block
signal audio_in_data_codec : std_logic_vector(31 downto 0) := (others => '0');
signal stream_out_data : std_logic_vector(23 downto 0);
signal stream_out_tag : std_logic_vector(0 downto 0);
signal stream_out_valid : std_logic;
signal stream_in_data : std_logic_vector(23 downto 0);
signal stream_in_tag : std_logic_vector(0 downto 0);
signal stream_in_ready : std_logic;
signal audio_out_full : std_logic;
signal class_d_sampled : std_logic_vector(1 downto 0);
signal class_d_data : signed(17 downto 0);
signal class_d_filtered : signed(17 downto 0);
signal class_d_std : std_logic_vector(31 downto 0) := (others => '0');
begin
process(sys_clock)
begin
if rising_edge(sys_clock) then
class_d_sampled <= pio_in_port(6 downto 5);
if class_d_sampled = "10" then
class_d_data <= to_signed(110000, 18);
elsif class_d_sampled = "01" then
class_d_data <= to_signed(-110000, 18);
else
class_d_data <= to_signed(0, 18);
end if;
end if;
end process;
class_d_std(25) <= '1';
class_d_std(23 downto 6) <= std_logic_vector(class_d_filtered);
-- multiplexer and byte reversal
audio_in_data <= byte_swap(class_d_std, true) when pio_out_port(31) = '1' else
byte_swap(audio_in_data_codec, true);
i_filt_left: entity work.lp_filter
port map (
clock => sys_clock,
reset => sys_reset,
signal_in => class_d_data,
low_pass => class_d_filtered );
i_aout: entity work.async_fifo_ft
generic map (
g_depth_bits => 4,
g_data_width => 25
)
port map(
wr_clock => sys_clock,
wr_reset => sys_reset,
wr_en => audio_out_valid,
wr_din(24) => audio_out_data(0),
wr_din(23 downto 16) => audio_out_data(15 downto 8),
wr_din(15 downto 8) => audio_out_data(23 downto 16),
wr_din(7 downto 0) => audio_out_data(31 downto 24),
wr_full => audio_out_full,
rd_clock => audio_clock,
rd_reset => audio_reset,
rd_next => stream_in_ready,
rd_dout(24 downto 24) => stream_in_tag,
rd_dout(23 downto 0) => stream_in_data,
rd_valid => open --stream_in_valid
);
audio_out_ready <= not audio_out_full;
i_ain: entity work.synchronizer_gzw
generic map(
g_width => 25,
g_fast => false
)
port map(
tx_clock => audio_clock,
tx_push => stream_out_valid,
tx_data(24 downto 24) => stream_out_tag,
tx_data(23 downto 0) => stream_out_data,
tx_done => open,
rx_clock => sys_clock,
rx_new_data => audio_in_valid,
rx_data => audio_in_data_codec(24 downto 0)
);
i2s: entity work.i2s_serializer_old
port map (
clock => audio_clock,
reset => audio_reset,
i2s_out => AUDIO_SDO,
i2s_in => AUDIO_SDI,
i2s_bclk => AUDIO_BCLK,
i2s_fs => AUDIO_LRCLK,
stream_out_data => stream_out_data,
stream_out_tag => stream_out_tag,
stream_out_valid => stream_out_valid,
stream_in_data => stream_in_data,
stream_in_tag => stream_in_tag,
stream_in_valid => '1',
stream_in_ready => stream_in_ready );
AUDIO_MCLK <= audio_clock;
end block;
SLOT_BUFFER_ENn <= '0'; -- once configured, we can connect
SLOT_ROMHn <= '1'; -- prim_uart_rts_n;
-- prim_uart_cts_n <= SLOT_RSTn;
-- prim_uart_rxd <= SLOT_IRQn;
-- io_uart_rxd <= SLOT_IRQn;
-- SLOT_NMIn <= io_uart_txd;
UART_TXD <= io_uart_txd;
io_uart_rxd <= UART_RXD;
-- SLOT_NMIn <= prim_uart_txd and io_uart_txd;
pio_in_port(4) <= SLOT_PHI2; -- <= usb_to_host_vbus; // B5 input only on FPGA
pio_in_port(5) <= SLOT_DOTCLK; -- <= jig_spkr.n; // T6 input only on FPGA
pio_in_port(6) <= SLOT_RWn; -- <= jig_spkr.p;
-- todo: add another uart
-- IO1n <= jig_rxd;
-- GAMEn <= jig_txd;
pio_in_port(8) <= SLOT_ADDR(14); -- usb_vcc[1];
pio_in_port(9) <= SLOT_ADDR(13); -- usb_vcc[2];
pio_in_port(10) <= SLOT_ADDR(15); -- usb_vcc[3];
pio_in_port(11) <= SLOT_ADDR(9); -- jtag_vcc;
SLOT_ADDR(8) <= not pio_out_port(4); -- dut_en_n;
SLOT_EXROMn <= not pio_out_port(5); -- jig_v50_5v_en_n;
SLOT_IO2n <= not pio_out_port(6); -- jig_c64_5v_en_n;
SLOT_ROMLn <= not pio_out_port(7); -- jig_ext_5v_en_n;
pio_in_port(12) <= SLOT_BA; -- adc_eoc_n; // input only fpga T12
spi_miso <= SLOT_DMAn;
SLOT_ADDR(7) <= spi_mosi;
SLOT_DATA(7) <= spi_sclk;
SLOT_DATA(6) <= spi_ss_n;
jtag0_jtag_tdo <= SLOT_ADDR(6);
SLOT_DATA(5) <= jtag0_jtag_tdi when pio_out_port(16) = '0' else 'Z';
SLOT_ADDR(5) <= jtag0_jtag_tms when pio_out_port(16) = '0' else 'Z';
SLOT_DATA(4) <= jtag0_jtag_tck when pio_out_port(16) = '0' else 'Z';
jtag1_jtag_tdo <= SLOT_DATA(3);
SLOT_DATA(2) <= jtag1_jtag_tdi;
SLOT_DATA(1) <= jtag1_jtag_tms;
SLOT_DATA(0) <= jtag1_jtag_tck;
SLOT_ADDR(4) <= not pio_out_port(8); -- exp_sclr_n
SLOT_ADDR(3) <= not pio_out_port(9); -- exp_oe_n
SLOT_ADDR(2) <= pio_out_port(10); -- exp_rclk;
SLOT_ADDR(1) <= pio_out_port(11); -- exp_sclk;
SLOT_ADDR(0) <= pio_out_port(12); -- exp_data;
SLOT_ADDR(10) <= pio_out_port(15); -- load 3.3V
SLOT_ADDR(11) <= pio_out_port(14); -- load 1.8V
SLOT_ADDR(12) <= pio_out_port(13); -- load 1.2V
b_jtag_debug: block
constant c_test_logic_reset : integer := 0;
constant c_run_test_idle : integer := 1;
constant c_select_dr : integer := 2;
constant c_capture_dr : integer := 3;
constant c_shift_dr : integer := 4;
constant c_exit1_dr : integer := 5;
constant c_pause_dr : integer := 6;
constant c_exit2_dr : integer := 7;
constant c_update_dr : integer := 8;
constant c_select_ir : integer := 9;
constant c_capture_ir : integer := 10;
constant c_shift_ir : integer := 11;
constant c_exit1_ir : integer := 12;
constant c_pause_ir : integer := 13;
constant c_exit2_ir : integer := 14;
constant c_update_ir : integer := 15;
type t_next_jtag_state is record
tms0 : integer range 0 to 15;
tms1 : integer range 0 to 15;
end record;
type t_next_jtag_state_array is array (natural range <>) of t_next_jtag_state;
constant c_next_jtag_state : t_next_jtag_state_array(0 to 15) := (
c_test_logic_reset => ( tms0 => c_run_test_idle, tms1 => c_test_logic_reset ),
c_run_test_idle => ( tms0 => c_run_test_idle, tms1 => c_select_dr ),
c_select_dr => ( tms0 => c_capture_dr, tms1 => c_select_ir ),
c_capture_dr => ( tms0 => c_shift_dr, tms1 => c_exit1_dr ),
c_shift_dr => ( tms0 => c_shift_dr, tms1 => c_exit1_dr ),
c_exit1_dr => ( tms0 => c_pause_dr, tms1 => c_update_dr ),
c_pause_dr => ( tms0 => c_pause_dr, tms1 => c_exit2_dr ),
c_exit2_dr => ( tms0 => c_shift_dr, tms1 => c_update_dr ),
c_update_dr => ( tms0 => c_run_test_idle, tms1 => c_select_dr ),
c_select_ir => ( tms0 => c_capture_ir, tms1 => c_test_logic_reset ),
c_capture_ir => ( tms0 => c_shift_ir, tms1 => c_exit1_ir ),
c_shift_ir => ( tms0 => c_shift_ir, tms1 => c_exit1_ir ),
c_exit1_ir => ( tms0 => c_pause_ir, tms1 => c_update_ir ),
c_pause_ir => ( tms0 => c_pause_ir, tms1 => c_exit2_ir ),
c_exit2_ir => ( tms0 => c_shift_ir, tms1 => c_update_ir ),
c_update_ir => ( tms0 => c_run_test_idle, tms1 => c_select_dr ) );
signal jtag_state : integer range 0 to 15 := 0;
signal edge : std_logic;
signal jtag_tck_c1, jtag_tck_c2, jtag_tck : std_logic;
signal jtag_tms_c1, jtag_tms_c2, jtag_tms : std_logic;
signal jtag_tdi_c1, jtag_tdi_c2, jtag_tdi : std_logic;
signal jtag_tdo_c1, jtag_tdo_c2, jtag_tdo : std_logic;
begin
process(sys_clock)
begin
if rising_edge(sys_clock) then
edge <= '0';
jtag_tck_c1 <= SLOT_DATA(4);
jtag_tck_c2 <= jtag_tck_c1;
jtag_tck <= jtag_tck_c2;
jtag_tms_c1 <= SLOT_ADDR(5);
jtag_tms_c2 <= jtag_tms_c1;
jtag_tms <= jtag_tms_c2;
jtag_tdi_c1 <= SLOT_DATA(5);
jtag_tdi_c2 <= jtag_tdi_c1;
jtag_tdi <= jtag_tdi_c2;
jtag_tdo_c1 <= SLOT_ADDR(6);
jtag_tdo_c2 <= jtag_tdo_c1;
jtag_tdo <= jtag_tdo_c2;
if jtag_tck = '0' and jtag_tck_c2 = '1' then
edge <= '1';
end if;
if edge = '1' then
if jtag_tms = '0' then
jtag_state <= c_next_jtag_state(jtag_state).tms0;
else
jtag_state <= c_next_jtag_state(jtag_state).tms1;
end if;
end if;
end if;
end process;
jtag_in_data(7 downto 4) <= std_logic_vector(to_unsigned(jtag_state, 4));
jtag_in_data(3) <= jtag_tck;
jtag_in_data(2) <= jtag_tms;
jtag_in_data(1) <= jtag_tdo;
jtag_in_data(0) <= jtag_tdi;
jtag_in_valid <= edge and pio_out_port(16);
end block;
UART_RXD <= '1' when rxd_drive = '0' else 'Z'; -- apply small current as pull-up.
end architecture;
| gpl-3.0 | 081bc9e42b9e0271df87562172e09940 | 0.444886 | 3.411599 | false | false | false | false |
chiggs/nvc | test/regress/signal8.vhd | 5 | 874 | entity signal8 is
end entity;
architecture test of signal8 is
type int_array is array (integer range <>) of integer;
type int_array_Nx4 is array (integer range <>) of int_array(1 to 4);
signal a : int_array_Nx4(1 to 4) := (
1 => ( 1, 2, 3, 4 ),
2 => ( 5, 6, 7, 8 ),
3 => ( 9, 10, 11, 12 ),
4 => ( 13, 14, 15, 16 ) );
begin
process is
variable b : int_array(1 to 4);
begin
a(1)(2) <= 99;
wait for 1 ns;
b := a(1);
--for i in b'range loop
-- report "b(" & integer'image(i) & ") = " & integer'image(b(i));
--end loop;
assert b = ( 1, 99, 3, 4 );
assert a(1)(2) = 99;
a(1) <= ( 21, 22, 23, 24 );
wait for 1 ns;
assert a(1)(1) = 21;
assert a(1)(3) = 23;
wait;
end process;
end architecture;
| gpl-3.0 | a977d82f1085d5b9a1a7316315b2e7c7 | 0.454233 | 3.003436 | false | false | false | false |
armandas/Arcade | alien2_generator.vhd | 2 | 6,217 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity alien2 is
port(
clk, not_reset: in std_logic;
px_x, px_y: in std_logic_vector(9 downto 0);
master_coord_x, master_coord_y: in std_logic_vector(9 downto 0);
missile_coord_x, missile_coord_y: in std_logic_vector(9 downto 0);
restart: in std_logic;
destroyed: out std_logic;
defeated: out std_logic;
explosion_x, explosion_y: out std_logic_vector(9 downto 0);
rgb_pixel: out std_logic_vector(0 to 2)
);
end alien2;
architecture generator of alien2 is
type states is (act, wait_clk);
signal state, state_next: states;
-- width of the alien area (8 * 32)
constant A_WIDTH: integer := 256;
constant A_HEIGHT: integer := 32;
-- 3rd level aliens are at the bottom (64px below master coord)
constant OFFSET: integer := 32;
constant FRAME_DELAY: integer := 5000000;
signal output_enable: std_logic;
-- address is made of row and column adresses
-- addr <= (row_address & col_address);
signal addr: std_logic_vector(9 downto 0);
signal row_address, col_address: std_logic_vector(4 downto 0);
signal origin_x, origin_x_next,
origin_y, origin_y_next: std_logic_vector(9 downto 0);
signal relative_x: std_logic_vector(9 downto 0);
signal missile_relative_x: std_logic_vector(9 downto 0);
signal position_in_frame: std_logic_vector(4 downto 0);
-- whether missile is in alien zone
signal missile_arrived: std_logic;
signal attacked_alien: std_logic_vector(2 downto 0);
signal destruction: std_logic;
-- condition of aliens: left (0) to right (7)
signal alive, alive_next: std_logic_vector(0 to 7);
signal alien_alive: std_logic;
-- second level aliens need two hits to get killed
signal injured, injured_next: std_logic_vector(0 to 7);
signal frame, frame_next: std_logic;
signal frame_counter, frame_counter_next: std_logic_vector(22 downto 0);
signal alien_rgb, alien21_rgb, alien22_rgb: std_logic_vector(2 downto 0);
-- which alien is currently being drawn
-- leftmost = 0, rightmost = 7
signal alien_number: std_logic_vector(2 downto 0);
begin
process(clk, not_reset)
begin
if not_reset = '0' then
frame <= '0';
frame_counter <= (others => '0');
alive <= (others => '1');
injured <= (others => '0');
state <= act;
elsif falling_edge(clk) then
frame <= frame_next;
frame_counter <= frame_counter_next;
alive <= alive_next;
injured <= injured_next;
state <= state_next;
end if;
end process;
missile_arrived <= '1' when missile_coord_y < master_coord_y + OFFSET + A_HEIGHT and
missile_coord_x > master_coord_x and
missile_coord_x < master_coord_x + A_WIDTH else
'0';
missile_relative_x <= (missile_coord_x - master_coord_x) when missile_arrived = '1' else
(others => '0');
attacked_alien <= missile_relative_x(7 downto 5) when missile_arrived = '1' else
(others => '0');
position_in_frame <= missile_relative_x(4 downto 0) when missile_arrived = '1' else
(others => '0');
process(missile_coord_x, master_coord_x,
missile_arrived, position_in_frame,
alive, injured, state, restart)
begin
state_next <= state;
destruction <= '0';
alive_next <= alive;
injured_next <= injured;
case state is
when act =>
if restart = '1' then
alive_next <= (others => '1');
injured_next <= (others => '0');
elsif missile_arrived = '1' and
alive(conv_integer(attacked_alien)) = '1' and
position_in_frame > 0 and
position_in_frame < 29
then
if injured(conv_integer(attacked_alien)) = '0' then
state_next <= wait_clk;
destruction <= '1';
injured_next(conv_integer(attacked_alien)) <= '1';
else
state_next <= wait_clk;
destruction <= '1';
alive_next(conv_integer(attacked_alien)) <= '0';
end if;
end if;
when wait_clk =>
state_next <= act;
end case;
end process;
relative_x <= px_x - master_coord_x;
alien_number <= relative_x(7 downto 5);
alien_alive <= alive(conv_integer(alien_number));
frame_counter_next <= frame_counter + 1 when frame_counter < FRAME_DELAY else
(others => '0');
frame_next <= (not frame) when frame_counter = 0 else frame;
output_enable <= '1' when (alien_alive = '1' and
px_x >= master_coord_x and
px_x < master_coord_x + A_WIDTH and
px_y >= master_coord_y + OFFSET and
px_y < master_coord_y + OFFSET + A_HEIGHT) else
'0';
row_address <= px_y(4 downto 0) - master_coord_y(4 downto 0);
col_address <= px_x(4 downto 0) - master_coord_x(4 downto 0);
addr <= row_address & col_address;
alien_rgb <= alien21_rgb when frame = '0' else
alien22_rgb;
rgb_pixel <= alien_rgb when output_enable = '1' else
(others => '0');
destroyed <= destruction;
-- attacked alien number is multiplied by 32
origin_x <= master_coord_x + (attacked_alien & "00000");
origin_y <= master_coord_y + OFFSET;
explosion_x <= origin_x;
explosion_y <= origin_y;
defeated <= '1' when alive = 0 else '0';
alien_21:
entity work.alien21_rom(content)
port map(addr => addr, data => alien21_rgb);
alien_22:
entity work.alien22_rom(content)
port map(addr => addr, data => alien22_rgb);
end generator; | bsd-2-clause | 0f6e95d2c1198852bc0193720408b333 | 0.549139 | 3.847153 | false | false | false | false |
markusC64/1541ultimate2 | fpga/io/usb2/vhdl_source/usb_debug.vhd | 1 | 3,118 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.usb_cmd_pkg.all;
entity usb_debug is
generic (
g_enabled : boolean := false );
port (
clock : in std_logic;
reset : in std_logic;
cmd_req : in t_usb_cmd_req;
cmd_resp : in t_usb_cmd_resp;
debug_data : out std_logic_vector(31 downto 0) := (others => '0');
debug_valid : out std_logic := '0' );
end entity;
architecture breakout of usb_debug is
type t_state is (idle, wait_response);
signal state : t_state;
begin
process(clock)
begin
if rising_edge(clock) then
debug_data <= (others => '0');
debug_valid <= '0';
if g_enabled then
case state is
when idle =>
if cmd_req.request = '1' then
state <= wait_response;
debug_data(9 downto 0) <= std_logic_vector(cmd_req.data_length);
debug_data(10) <= cmd_req.no_data;
debug_data(11) <= cmd_req.togglebit;
debug_data(13 downto 12) <= std_logic_vector(to_unsigned(t_usb_command'pos(cmd_req.command), 2));
debug_data(14) <= cmd_req.do_split;
debug_data(15) <= cmd_req.do_data;
debug_data(19 downto 16) <= std_logic_vector(cmd_req.device_addr(3 downto 0));
debug_data(21 downto 20) <= std_logic_vector(cmd_req.endp_addr(1 downto 0));
debug_data(23 downto 22) <= std_logic_vector(cmd_req.split_port_addr(1 downto 0));
debug_data(26 downto 24) <= std_logic_vector(cmd_req.split_hub_addr(2 downto 0));
debug_data(27) <= cmd_req.split_sc;
debug_data(28) <= cmd_req.split_sp;
debug_data(30 downto 29) <= cmd_req.split_et;
debug_data(31) <= '0'; -- command
debug_valid <= '1';
end if;
when wait_response =>
if cmd_resp.done = '1' then
debug_data(9 downto 0) <= std_logic_vector(cmd_resp.data_length);
debug_data(10) <= cmd_resp.no_data;
debug_data(11) <= cmd_resp.togglebit;
debug_data(14 downto 12) <= std_logic_vector(to_unsigned(t_usb_result'pos(cmd_resp.result), 3));
debug_data(18 downto 16) <= cmd_resp.error_code;
debug_data(31) <= '1'; -- response
debug_valid <= '1';
state <= idle;
end if;
end case;
end if;
if reset = '1' then
state <= idle;
end if;
end if;
end process;
end architecture;
| gpl-3.0 | 253291209ce7387f2a5a5d3d5d8d28bc | 0.448685 | 3.977041 | false | false | false | false |
markusC64/1541ultimate2 | target/simulation/packages/vhdl_source/tl_string_util_pkg.vhd | 5 | 33,938 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2006 TECHNOLUTION B.V., GOUDA NL
-- | ======= I == I =
-- | I I I I
-- | I === === I === I === === I I I ==== I === I ===
-- | I / \ I I/ I I/ I I I I I I I I I I I/ I
-- | I ===== I I I I I I I I I I I I I I I I
-- | I \ I I I I I I I I I /I \ I I I I I
-- | I === === I I I I === === === I == I === I I
-- | +---------------------------------------------------+
-- +----+ | +++++++++++++++++++++++++++++++++++++++++++++++++|
-- | | ++++++++++++++++++++++++++++++++++++++|
-- +------------+ +++++++++++++++++++++++++|
-- ++++++++++++++|
-- A U T O M A T I O N T E C H N O L O G Y +++++|
--
-------------------------------------------------------------------------------
-- Title : Style guide example package
-- Author : Jonathan Hofman ([email protected]) (import only)
-------------------------------------------------------------------------------
-- Description: This file contains type definitions
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
package tl_string_util_pkg is
-------------------------------------------------------------------------------
-- functions origination from file_io_package (depricated)
-------------------------------------------------------------------------------
function nibble_to_hex(nibble : std_logic_vector(3 downto 0)) return character; -- depricated
function hex_to_nibble(c : character) return std_logic_vector; -- depricated
function is_hex_char(c : character) return boolean; -- depricated
function vec_to_hex(vec : std_logic_vector; len : integer) return string; -- depricated
procedure write_string(variable my_line : inout line; s : string); -- depricated
-------------------------------------------------------------------------------
-- functions to convert to string
-------------------------------------------------------------------------------
---------------------------------------------------------------------------
-- converts std_logic into a character
---------------------------------------------------------------------------
function chr(sl: std_logic) return character;
---------------------------------------------------------------------------
-- converts a nible into a hex character
---------------------------------------------------------------------------
function hchr(slv: std_logic_vector) return character;
function hchr(slv: unsigned) return character;
---------------------------------------------------------------------------
-- converts std_logic into a string (1 to 1)
---------------------------------------------------------------------------
function str(sl: std_logic) return string;
---------------------------------------------------------------------------
-- converts std_logic_vector into a string (binary base)
---------------------------------------------------------------------------
function str(slv: std_logic_vector) return string;
---------------------------------------------------------------------------
-- converts boolean into a string
---------------------------------------------------------------------------
function str(b: boolean) return string;
---------------------------------------------------------------------------
-- converts an integer into a single character
-- (can also be used for hex conversion and other bases)
---------------------------------------------------------------------------
function chr(int: integer) return character;
---------------------------------------------------------------------------
-- converts integer into string using specified base
---------------------------------------------------------------------------
function str(int: integer; base: integer) return string;
---------------------------------------------------------------------------
-- converts to string, using base 10
---------------------------------------------------------------------------
function str(int: integer) return string;
---------------------------------------------------------------------------
-- convert into a string in hex format
---------------------------------------------------------------------------
function hstr(slv: std_logic_vector) return string;
function hstr(uns: unsigned) return string;
-------------------------------------------------------------------------------
-- function to convert from string
-------------------------------------------------------------------------------
---------------------------------------------------------------------------
-- converts a character into std_logic
---------------------------------------------------------------------------
function to_std_logic(c: character) return std_logic;
---------------------------------------------------------------------------
-- converts a hex character into std_logic_vector
---------------------------------------------------------------------------
function hchr_to_std_logic_vector(c: character) return std_logic_vector;
---------------------------------------------------------------------------
-- converts a string into a specific type
---------------------------------------------------------------------------
function to_std_logic_vector(s: string) return std_logic_vector;
---------------------------------------------------------------------------
-- converts a hex string into a specific type
---------------------------------------------------------------------------
function hstr_to_std_logic_vector( str : string; len: integer) return std_logic_vector;
function hstr_to_integer( str : string ) return integer;
-------------------------------------------------------------------------------
-- string manipulation routines
-------------------------------------------------------------------------------
---------------------------------------------------------------------------
-- convert to upper case
---------------------------------------------------------------------------
function to_upper(c: character) return character;
function to_upper(s: string) return string;
---------------------------------------------------------------------------
-- convert to lower case
---------------------------------------------------------------------------
function to_lower(c: character) return character;
function to_lower(s: string) return string;
---------------------------------------------------------------------------
-- check if it is an hex character
---------------------------------------------------------------------------
function is_hchr(c : character) return boolean;
function resize(s: string; size: natural; default: character := ' ') return string;
---------------------------------------------------------------------------
-- Compare function for strings that correctly handles terminators (NUL)
---------------------------------------------------------------------------
function strcmp(a: string; b: string) return boolean;
-------------------------------------------------------------------------------
-- file I/O
-------------------------------------------------------------------------------
---------------------------------------------------------------------------
-- print
---------------------------------------------------------------------------
-- print string to a file and start new line, if no file is specified the
-- print function will print to stdout
---------------------------------------------------------------------------
procedure print(text: string);
procedure print(active: boolean; text: string);
procedure print(file out_file: TEXT; new_string: in string);
procedure print(file out_file: TEXT; char: in character);
---------------------------------------------------------------------------
-- read variable length string from input file
---------------------------------------------------------------------------
procedure str_read(file in_file: TEXT; res_string: out string);
-------------------------------------------------------------------------------
-- character manipulation
-------------------------------------------------------------------------------
function char_to_std_logic_vector (
constant my_char : character)
return std_logic_vector;
end tl_string_util_pkg;
package body tl_string_util_pkg is
function nibble_to_hex(nibble : std_logic_vector(3 downto 0)) return character is
variable r : character := '?';
begin
case nibble is
when "0000" => r := '0';
when "0001" => r := '1';
when "0010" => r := '2';
when "0011" => r := '3';
when "0100" => r := '4';
when "0101" => r := '5';
when "0110" => r := '6';
when "0111" => r := '7';
when "1000" => r := '8';
when "1001" => r := '9';
when "1010" => r := 'A';
when "1011" => r := 'B';
when "1100" => r := 'C';
when "1101" => r := 'D';
when "1110" => r := 'E';
when "1111" => r := 'F';
when others => r := 'X';
end case;
return r;
end nibble_to_hex;
function hex_to_nibble(c : character) return std_logic_vector is
variable z : std_logic_vector(3 downto 0);
begin
case c is
when '0' => z := "0000";
when '1' => z := "0001";
when '2' => z := "0010";
when '3' => z := "0011";
when '4' => z := "0100";
when '5' => z := "0101";
when '6' => z := "0110";
when '7' => z := "0111";
when '8' => z := "1000";
when '9' => z := "1001";
when 'A' => z := "1010";
when 'B' => z := "1011";
when 'C' => z := "1100";
when 'D' => z := "1101";
when 'E' => z := "1110";
when 'F' => z := "1111";
when 'a' => z := "1010";
when 'b' => z := "1011";
when 'c' => z := "1100";
when 'd' => z := "1101";
when 'e' => z := "1110";
when 'f' => z := "1111";
when others => z := "XXXX";
end case;
return z;
end hex_to_nibble;
function is_hex_char(c : character) return boolean is
begin
case c is
when '0'|'1'|'2'|'3'|'4'|'5'|'6'|'7' => return true;
when '8'|'9'|'A'|'B'|'C'|'D'|'E'|'F' => return true;
when 'a'|'b'|'c'|'d'|'e'|'f' => return true;
when others => return false;
end case;
return false;
end is_hex_char;
procedure vec_to_hex(vec : std_logic_vector; str : out string) is
variable temp_vec : std_logic_vector(str'length * 4 downto 1) := (others => '0');
variable j : integer;
variable my_vec : std_logic_vector(vec'range);
variable len, my_low, my_high : integer;
begin
my_vec := vec;
len := str'length;
my_low := vec'low;
my_high := vec'high;
if vec'length < temp_vec'length then
temp_vec(vec'length downto 1) := vec;
else
temp_vec := vec(vec'low + temp_vec'length - 1 downto vec'low);
end if;
for i in str'range loop
j := (str'right - i) * 4;
str(i) := nibble_to_hex(temp_vec(j+4 downto j+1));
end loop;
end vec_to_hex;
function vec_to_hex(vec : std_logic_vector; len : integer) return string is
variable str : string(1 to len);
begin
vec_to_hex(vec, str);
return str;
end vec_to_hex;
procedure write_string(variable my_line : inout line; s : string) is
begin
write(my_line, s);
end write_string;
-------------------------------------------------------------------------------
-- functions to convert to string
-------------------------------------------------------------------------------
function chr(sl : std_logic) return character is
variable c : character;
begin
case sl is
when 'U' => c := 'U';
when 'X' => c := 'X';
when '0' => c := '0';
when '1' => c := '1';
when 'Z' => c := 'Z';
when 'W' => c := 'W';
when 'L' => c := 'L';
when 'H' => c := 'H';
when '-' => c := '-';
end case;
return c;
end chr;
function str(sl : std_logic) return string is
variable s : string(1 to 1);
begin
s(1) := chr(sl);
return s;
end str;
-- converts std_logic_vector into a string (binary base)
-- (this also takes care of the fact that the range of
-- a string is natural while a std_logic_vector may
-- have an integer range)
function str(slv : std_logic_vector) return string is
variable result : string (1 to slv'length);
variable r : integer;
begin
r := 1;
for i in slv'range loop
result(r) := chr(slv(i));
r := r + 1;
end loop;
return result;
end str;
function str(b : boolean) return string is
begin
if b then
return "true";
else
return "false";
end if;
end str;
-- converts an integer into a character
-- for 0 to 9 the obvious mapping is used, higher
-- values are mapped to the characters A-Z
-- (this is usefull for systems with base > 10)
-- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
function chr(int : integer) return character is
variable c : character;
begin
case int is
when 0 => c := '0';
when 1 => c := '1';
when 2 => c := '2';
when 3 => c := '3';
when 4 => c := '4';
when 5 => c := '5';
when 6 => c := '6';
when 7 => c := '7';
when 8 => c := '8';
when 9 => c := '9';
when 10 => c := 'A';
when 11 => c := 'B';
when 12 => c := 'C';
when 13 => c := 'D';
when 14 => c := 'E';
when 15 => c := 'F';
when 16 => c := 'G';
when 17 => c := 'H';
when 18 => c := 'I';
when 19 => c := 'J';
when 20 => c := 'K';
when 21 => c := 'L';
when 22 => c := 'M';
when 23 => c := 'N';
when 24 => c := 'O';
when 25 => c := 'P';
when 26 => c := 'Q';
when 27 => c := 'R';
when 28 => c := 'S';
when 29 => c := 'T';
when 30 => c := 'U';
when 31 => c := 'V';
when 32 => c := 'W';
when 33 => c := 'X';
when 34 => c := 'Y';
when 35 => c := 'Z';
when others => c := '?';
end case;
return c;
end chr;
function hchr(slv: std_logic_vector) return character is
begin
return hchr(unsigned(slv));
end function;
function hchr(slv: unsigned) return character is
variable v_fourbit : unsigned(3 downto 0);
variable v_result : character;
begin
v_fourbit := resize(slv, 4);
case v_fourbit is
when "0000" => v_result := '0';
when "0001" => v_result := '1';
when "0010" => v_result := '2';
when "0011" => v_result := '3';
when "0100" => v_result := '4';
when "0101" => v_result := '5';
when "0110" => v_result := '6';
when "0111" => v_result := '7';
when "1000" => v_result := '8';
when "1001" => v_result := '9';
when "1010" => v_result := 'A';
when "1011" => v_result := 'B';
when "1100" => v_result := 'C';
when "1101" => v_result := 'D';
when "1110" => v_result := 'E';
when "1111" => v_result := 'F';
when "ZZZZ" => v_result := 'z';
when "UUUU" => v_result := 'u';
when "XXXX" => v_result := 'x';
when others => v_result := '?';
end case;
return v_result;
end function;
-- convert integer to string using specified base
-- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
function str(int : integer; base : integer) return string is
variable temp : string(1 to 10);
variable num : integer;
variable abs_int : integer;
variable len : integer := 1;
variable power : integer := 1;
begin
-- bug fix for negative numbers
abs_int := abs(int);
num := abs_int;
while num >= base loop -- Determine how many
len := len + 1; -- characters required
num := num / base; -- to represent the
end loop; -- number.
for i in len downto 1 loop -- Convert the number to
temp(i) := chr(abs_int/power mod base); -- a string starting
power := power * base; -- with the right hand
end loop; -- side.
-- return result and add sign if required
if int < 0 then
return '-'& temp(1 to len);
else
return temp(1 to len);
end if;
end str;
-- convert integer to string, using base 10
function str(int : integer) return string is
begin
return str(int, 10);
end str;
-- converts a std_logic_vector into a hex string.
function hstr(slv : std_logic_vector) return string is
constant c_hexlen : integer := (slv'length + 3)/4;
alias slv_norm : std_logic_vector(slv'length - 1 downto 0) is slv;
variable v_longslv : std_logic_vector(c_hexlen * 4 - 1 downto 0) := (others => '0');
variable v_result : string(1 to c_hexlen);
variable v_fourbit : std_logic_vector(3 downto 0);
begin
v_longslv(slv_norm'range) := slv_norm;
for i in 0 to c_hexlen - 1 loop
v_fourbit := v_longslv(((i * 4) + 3) downto (i * 4));
case v_fourbit is
when "0000" => v_result(c_hexlen - i) := '0';
when "0001" => v_result(c_hexlen - i) := '1';
when "0010" => v_result(c_hexlen - i) := '2';
when "0011" => v_result(c_hexlen - i) := '3';
when "0100" => v_result(c_hexlen - i) := '4';
when "0101" => v_result(c_hexlen - i) := '5';
when "0110" => v_result(c_hexlen - i) := '6';
when "0111" => v_result(c_hexlen - i) := '7';
when "1000" => v_result(c_hexlen - i) := '8';
when "1001" => v_result(c_hexlen - i) := '9';
when "1010" => v_result(c_hexlen - i) := 'A';
when "1011" => v_result(c_hexlen - i) := 'B';
when "1100" => v_result(c_hexlen - i) := 'C';
when "1101" => v_result(c_hexlen - i) := 'D';
when "1110" => v_result(c_hexlen - i) := 'E';
when "1111" => v_result(c_hexlen - i) := 'F';
when "ZZZZ" => v_result(c_hexlen - i) := 'z';
when "UUUU" => v_result(c_hexlen - i) := 'u';
when "XXXX" => v_result(c_hexlen - i) := 'x';
when others => v_result(c_hexlen - i) := '?';
end case;
end loop;
return v_result;
end hstr;
-- converts an unsigned into a hex string.
function hstr(uns : unsigned) return string is
begin
return hstr(std_logic_vector(uns));
end;
-------------------------------------------------------------------------------
-- function to convert from string
-------------------------------------------------------------------------------
function to_std_logic(c: character) return std_logic is
variable sl: std_logic;
begin
case c is
when 'U' => sl := 'U';
when 'X' => sl := 'X';
when '0' => sl := '0';
when '1' => sl := '1';
when 'Z' => sl := 'Z';
when 'W' => sl := 'W';
when 'L' => sl := 'L';
when 'H' => sl := 'H';
when '-' => sl := '-';
when others => sl := 'X';
end case;
return sl;
end to_std_logic;
function hchr_to_std_logic_vector(c: character) return std_logic_vector is
variable v_result : std_logic_vector(3 downto 0);
begin
case c is
when '0' => v_result := "0000";
when '1' => v_result := "0001";
when '2' => v_result := "0010";
when '3' => v_result := "0011";
when '4' => v_result := "0100";
when '5' => v_result := "0101";
when '6' => v_result := "0110";
when '7' => v_result := "0111";
when '8' => v_result := "1000";
when '9' => v_result := "1001";
when 'a' => v_result := "1010";
when 'b' => v_result := "1011";
when 'c' => v_result := "1100";
when 'd' => v_result := "1101";
when 'e' => v_result := "1110";
when 'f' => v_result := "1111";
when 'A' => v_result := "1010";
when 'B' => v_result := "1011";
when 'C' => v_result := "1100";
when 'D' => v_result := "1101";
when 'E' => v_result := "1110";
when 'F' => v_result := "1111";
when others => v_result := "XXXX";
assert FALSE
report "Illegal character "& c & "in hex string! "
severity warning;
end case;
return v_result;
end function;
function to_std_logic_vector(s: string) return std_logic_vector is
variable slv: std_logic_vector(s'high-s'low downto 0);
variable k: integer;
begin
k := s'high-s'low;
for i in s'range loop
slv(k) := to_std_logic(s(i));
k := k - 1;
end loop;
return slv;
end to_std_logic_vector;
function hstr_to_integer(str: string) return integer is
variable len : integer := str'length;
variable ivalue : integer := 0;
variable digit : integer;
begin
for i in 1 to len loop
case to_lower(str(i)) is
when '0' => digit := 0;
when '1' => digit := 1;
when '2' => digit := 2;
when '3' => digit := 3;
when '4' => digit := 4;
when '5' => digit := 5;
when '6' => digit := 6;
when '7' => digit := 7;
when '8' => digit := 8;
when '9' => digit := 9;
when 'a' => digit := 10;
when 'b' => digit := 11;
when 'c' => digit := 12;
when 'd' => digit := 13;
when 'e' => digit := 14;
when 'f' => digit := 15;
when others =>
assert FALSE
report "Illegal character "& str(i) & "in hex string! "
severity ERROR;
end case;
ivalue := ivalue * 16 + digit;
end loop;
return ivalue;
end;
function hstr_to_std_logic_vector(str: string; len: integer) return std_logic_vector is
variable digit : std_logic_vector(3 downto 0);
variable result : std_logic_vector((str'length * 4) - 1 downto 0);
begin
-- we can not use hstr_to_integer and then convert to hex, because the integer range is
-- limited
for i in str'range loop
case to_lower(str(str'length - i + 1)) is
when '0' => digit := "0000";
when '1' => digit := "0001";
when '2' => digit := "0010";
when '3' => digit := "0011";
when '4' => digit := "0100";
when '5' => digit := "0101";
when '6' => digit := "0110";
when '7' => digit := "0111";
when '8' => digit := "1000";
when '9' => digit := "1001";
when 'a' => digit := "1010";
when 'b' => digit := "1011";
when 'c' => digit := "1100";
when 'd' => digit := "1101";
when 'e' => digit := "1110";
when 'f' => digit := "1111";
when others =>
assert FALSE
report "Illegal character "& str(i) & "in hex string! "
severity error;
end case;
result((i * 4) - 1 downto (i - 1) * 4) := digit;
end loop;
return result(len - 1 downto 0);
end;
-------------------------------------------------------------------------------
-- string manipulation routines
-------------------------------------------------------------------------------
function to_upper(c : character) return character is
variable u : character;
begin
case c is
when 'a' => u := 'A';
when 'b' => u := 'B';
when 'c' => u := 'C';
when 'd' => u := 'D';
when 'e' => u := 'E';
when 'f' => u := 'F';
when 'g' => u := 'G';
when 'h' => u := 'H';
when 'i' => u := 'I';
when 'j' => u := 'J';
when 'k' => u := 'K';
when 'l' => u := 'L';
when 'm' => u := 'M';
when 'n' => u := 'N';
when 'o' => u := 'O';
when 'p' => u := 'P';
when 'q' => u := 'Q';
when 'r' => u := 'R';
when 's' => u := 'S';
when 't' => u := 'T';
when 'u' => u := 'U';
when 'v' => u := 'V';
when 'w' => u := 'W';
when 'x' => u := 'X';
when 'y' => u := 'Y';
when 'z' => u := 'Z';
when others => u := c;
end case;
return u;
end to_upper;
function to_lower(c : character) return character is
variable l : character;
begin
case c is
when 'A' => l := 'a';
when 'B' => l := 'b';
when 'C' => l := 'c';
when 'D' => l := 'd';
when 'E' => l := 'e';
when 'F' => l := 'f';
when 'G' => l := 'g';
when 'H' => l := 'h';
when 'I' => l := 'i';
when 'J' => l := 'j';
when 'K' => l := 'k';
when 'L' => l := 'l';
when 'M' => l := 'm';
when 'N' => l := 'n';
when 'O' => l := 'o';
when 'P' => l := 'p';
when 'Q' => l := 'q';
when 'R' => l := 'r';
when 'S' => l := 's';
when 'T' => l := 't';
when 'U' => l := 'u';
when 'V' => l := 'v';
when 'W' => l := 'w';
when 'X' => l := 'x';
when 'Y' => l := 'y';
when 'Z' => l := 'z';
when others => l := c;
end case;
return l;
end to_lower;
function to_upper(s : string) return string is
variable uppercase : string (s'range);
begin
for i in s'range loop
uppercase(i) := to_upper(s(i));
end loop;
return uppercase;
end to_upper;
function to_lower(s : string) return string is
variable lowercase : string (s'range);
begin
for i in s'range loop
lowercase(i) := to_lower(s(i));
end loop;
return lowercase;
end to_lower;
function is_hchr(c : character) return boolean is
variable v_result : boolean;
begin
case c is
when '0'|'1'|'2'|'3'|'4'|'5'|'6'|'7'|
'8'|'9'|'A'|'B'|'C'|'D'|'E'|'F'|
'a'|'b'|'c'|'d'|'e'|'f' => v_result := true;
when others => v_result := false;
end case;
return v_result;
end function;
function strcmp(a: string; b: string) return boolean is
variable r : boolean := true;
begin
for i in a'range loop
if i > b'right then
if a(i) /= NUL then -- b is shorter and a doesn't terminate here.
return false;
else
return true; -- b is shorter, but a does terminate here
end if;
end if;
if a(i) /= b(i) then -- characters are not the same
return false;
end if;
if a(i) = NUL and b(i) = NUL then -- a and b have a string terminator at the same place
-- and previous characters were all the same
return true;
end if;
end loop;
-- if b is longer, then check if b has a terminator
if (b'right > a'right) then
if b(a'right + 1) /= NUL then
return false;
end if;
end if;
return true;
end strcmp;
-------------------------------------------------------------------------------
-- file I/O
-------------------------------------------------------------------------------
procedure print(text: string) is
variable msg_line: line;
begin
write(msg_line, text);
writeline(output, msg_line);
end print;
procedure print(active: boolean; text: string) is
begin
if active then
print(text);
end if;
end print;
procedure print(file out_file: TEXT; new_string: in string) is
variable l: line;
begin
write(l, new_string);
writeline(out_file, l);
end print;
procedure print(file out_file: TEXT; char: in character) is
variable l: line;
begin
write(l, char);
writeline(out_file, l);
end print;
procedure str_read(file in_file: TEXT; res_string: out string) is
variable l: line;
variable c: character;
variable is_string: boolean;
begin
readline(in_file, l);
-- clear the contents of the result string
for i in res_string'range loop
res_string(i) := ' ';
end loop;
-- read all characters of the line, up to the length
-- of the results string
for i in res_string'range loop
read(l, c, is_string);
res_string(i) := c;
if not is_string then -- found end of line
exit;
end if;
end loop;
end str_read;
-- appends contents of a string to a file until line feed occurs
-- (LF is considered to be the end of the string)
procedure str_write(file out_file: TEXT; new_string: in string) is
begin
for i in new_string'range loop
print(out_file, new_string(i));
if new_string(i) = LF then -- end of string
exit;
end if;
end loop;
end str_write;
function char_to_std_logic_vector (
constant my_char : character)
return std_logic_vector is
begin
return std_logic_vector(to_unsigned(character'pos(my_char), 8));
end;
function resize(s: string; size: natural; default: character := ' ') return string is
variable result: string(1 to size) := (others => default);
begin
if s'length > size then
result := s(result'range);
else
result(s'range) := s;
end if;
return result;
end function;
end tl_string_util_pkg;
| gpl-3.0 | 3bf05d86c1ade5ebc65f325c7facb11f | 0.371354 | 4.4375 | false | false | false | false |
chiggs/nvc | test/regress/access1.vhd | 5 | 1,592 | entity access1 is
end entity;
architecture test of access1 is
type int_ptr is access integer;
type list;
type list_ptr is access list;
type list is record
link : list_ptr;
value : integer;
end record;
procedure list_add(l : inout list_ptr; v : integer) is
variable n : list_ptr;
begin
n := new list;
n.link := l;
n.value := v;
l := n;
end procedure;
procedure list_print(variable l : in list_ptr) is
begin
if l /= null then
report integer'image(l.all.value);
list_print(l.all.link);
end if;
end procedure;
procedure list_free(l : inout list_ptr) is
variable tmp : list_ptr;
begin
while l /= null loop
tmp := l.all.link;
deallocate(l);
l := tmp;
end loop;
end procedure;
signal p1_done : boolean := false;
type str_ptr is access string;
begin
p1: process is
variable p, q : int_ptr;
begin
assert p = null;
p := new integer;
p.all := 5;
assert p.all = 5;
q := p;
assert q.all = 5;
q.all := 6;
assert p.all = 6;
deallocate(p);
assert p = null;
p1_done <= true;
wait;
end process;
p2: process is
variable l, p : list_ptr;
begin
wait until p1_done;
for i in 1 to 10 loop
list_add(l, i);
end loop;
list_print(l);
list_free(l);
wait;
end process;
end architecture;
| gpl-3.0 | b2d3d87c47cdcf6400d4d16020d1029f | 0.505025 | 3.745882 | false | false | false | false |
markusC64/1541ultimate2 | fpga/io/debug/vhdl_source/bus_analyzer_32.vhd | 1 | 8,950 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.mem_bus_pkg.all;
use work.endianness_pkg.all;
entity bus_analyzer_32 is
generic (
g_big_endian : boolean );
port (
clock : in std_logic;
reset : in std_logic;
addr : in std_logic_vector(15 downto 0);
data : in std_logic_vector(7 downto 0);
rstn : in std_logic;
phi2 : in std_logic;
rwn : in std_logic;
ba : in std_logic;
dman : in std_logic;
ROMLn : in std_logic;
ROMHn : in std_logic;
EXROMn : in std_logic;
GAMEn : in std_logic;
IO1n : in std_logic;
IO2n : in std_logic;
IRQn : in std_logic;
NMIn : in std_logic;
trigger : in std_logic;
sync : in std_logic;
drv_enable : out std_logic;
---
mem_req : out t_mem_req_32;
mem_resp : in t_mem_resp_32;
debug_data : out std_logic_vector(31 downto 0);
debug_valid : out std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp );
end entity;
architecture gideon of bus_analyzer_32 is
type t_state is (idle, writing, recording, wait_trigger, wait_sync);
signal enable_log : std_logic;
signal ev_addr : unsigned(24 downto 0);
signal state : t_state;
signal vector_in : std_logic_vector(31 downto 0);
signal vector_c : std_logic_vector(31 downto 0);
signal vector_d1 : std_logic_vector(31 downto 0);
signal vector_d2 : std_logic_vector(31 downto 0);
signal vector_d3 : std_logic_vector(31 downto 0);
signal ba_history : std_logic_vector(2 downto 0) := "000";
signal debug_data_i : std_logic_vector(31 downto 0) := (others => '0');
signal debug_valid_i: std_logic := '0';
signal mem_request : std_logic;
signal phi_c : std_logic := '0';
signal phi_d1 : std_logic := '0';
signal phi_d2 : std_logic := '0';
signal dman_c : std_logic := '0';
signal io : std_logic;
signal interrupt : std_logic;
signal rom : std_logic;
signal frame_tick : std_logic := '0';
signal counter : integer range 0 to 312*63; -- PAL
signal drv_enable_i : std_logic;
signal cpu_cycle_enable : std_logic := '1';
signal vic_cycle_enable : std_logic := '1';
begin
io <= io1n and io2n;
rom <= romln and romhn;
interrupt <= irqn and nmin;
vector_in <= phi2 & gamen & exromn & ba & irqn & rom & nmin & rwn & data & addr;
--vector_in <= phi2 & gamen & exromn & ba & irqn & rom & nmin & rwn & data & addr;
--vector_in <= phi2 & gamen & exromn & ba & interrupt & rom & io & rwn & data & addr;
debug_data <= debug_data_i;
debug_valid <= debug_valid_i;
process(clock)
begin
if rising_edge(clock) then
dman_c <= dman;
phi_c <= phi2;
phi_d1 <= phi_c;
phi_d2 <= phi_d1;
vector_c <= vector_in;
vector_d1 <= vector_c;
vector_d2 <= vector_d1;
vector_d3 <= vector_d2;
-- BA 1 1 1 0 0 0 0 0 0 0 1 1 1
-- BA0 1 1 1 1 0 0 0 0 0 0 0 1 1
-- BA1 1 1 1 1 1 0 0 0 0 0 0 0 1
-- BA2 1 1 1 1 1 1 0 0 0 0 0 0 0
-- CPU 1 1 1 1 1 1 0 0 0 0 1 1 1
--
debug_valid_i <= '0';
if phi_d2 /= phi_d1 then
debug_data_i <= vector_d3;
if phi_d2 = '1' then
ba_history <= ba_history(1 downto 0) & vector_d3(28); -- BA position!
end if;
if phi_d2 = '1' then
if (vector_d3(28) = '1' or ba_history /= "000" or drv_enable_i = '1') and cpu_cycle_enable = '1' then
debug_valid_i <= '1';
elsif vic_cycle_enable = '1' then
debug_valid_i <= '1';
end if;
elsif vic_cycle_enable = '1' then
debug_valid_i <= '1';
end if;
end if;
if sync = '1' then
counter <= 312 * 63 - 1;
elsif phi_d1 = '1' and phi_d2 = '0' then
if counter = 0 then
counter <= 312 * 63 - 1;
frame_tick <= '1';
else
counter <= counter - 1;
frame_tick <= '0';
end if;
end if;
case state is
when idle =>
if enable_log = '1' then
state <= wait_trigger;
end if;
when wait_trigger =>
if enable_log = '0' then
state <= idle;
elsif trigger = '1' then
state <= wait_sync;
end if;
when wait_sync =>
if enable_log = '0' then
state <= idle;
elsif frame_tick = '1' then
state <= recording;
end if;
when recording =>
if debug_valid_i = '1' then
mem_request <= '1';
state <= writing;
end if;
when writing =>
if mem_resp.rack='1' and mem_resp.rack_tag=X"F0" then
ev_addr <= ev_addr + 4;
if ev_addr = 16#1FFFFF4# then
enable_log <= '0';
end if;
mem_request <= '0';
if enable_log = '0' then
state <= idle;
else
state <= recording;
end if;
end if;
when others =>
null;
end case;
io_resp <= c_io_resp_init;
if io_req.read='1' then
io_resp.ack <= '1';
if g_big_endian then
case io_req.address(2 downto 0) is
when "011" =>
io_resp.data <= std_logic_vector(ev_addr(7 downto 0));
when "010" =>
io_resp.data <= std_logic_vector(ev_addr(15 downto 8));
when "001" =>
io_resp.data <= std_logic_vector(ev_addr(23 downto 16));
when "000" =>
io_resp.data <= "0000001" & ev_addr(24);
when others =>
null;
end case;
else
case io_req.address(2 downto 0) is
when "000" =>
io_resp.data <= std_logic_vector(ev_addr(7 downto 0));
when "001" =>
io_resp.data <= std_logic_vector(ev_addr(15 downto 8));
when "010" =>
io_resp.data <= std_logic_vector(ev_addr(23 downto 16));
when "011" =>
io_resp.data <= "0000001" & ev_addr(24);
when others =>
null;
end case;
end if;
elsif io_req.write='1' then
io_resp.ack <= '1';
case io_req.address(3 downto 0) is
when X"6" =>
enable_log <= '0';
when X"7" =>
ev_addr <= (others => '0');
enable_log <= '1';
when X"8" =>
cpu_cycle_enable <= io_req.data(0);
vic_cycle_enable <= io_req.data(1);
drv_enable_i <= io_req.data(2);
when others =>
null;
end case;
end if;
if reset='1' then
state <= idle;
enable_log <= '0';
mem_request <= '0';
ev_addr <= (others => '0');
drv_enable_i <= '0';
end if;
end if;
end process;
drv_enable <= drv_enable_i;
mem_req.data <= byte_swap(debug_data_i, g_big_endian);
mem_req.request <= mem_request;
mem_req.tag <= X"F0";
mem_req.address <= "1" & unsigned(ev_addr);
mem_req.read_writen <= '0'; -- write only
mem_req.byte_en <= "1111";
end gideon;
| gpl-3.0 | c44846bbf5768d3ea3d647e63d9bcf15 | 0.407263 | 3.910004 | false | false | false | false |
trondd/mkjpeg | design/huffman/AC_ROM.vhd | 2 | 34,131 | -------------------------------------------------------------------------------
-- File Name : AC_ROM.vhd
--
-- Project : JPEG_ENC
--
-- Module : AC_ROM
--
-- Content : AC_ROM Luminance
--
-- Description :
--
-- Spec. :
--
-- Author : Michal Krepa
--
-------------------------------------------------------------------------------
-- History :
-- 20090228: (MK): Initial Creation.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- LIBRARY/PACKAGE ---------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- generic packages/libraries:
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- user packages/libraries:
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ENTITY ------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
entity AC_ROM is
port
(
CLK : in std_logic;
RST : in std_logic;
runlength : in std_logic_vector(3 downto 0);
VLI_size : in std_logic_vector(3 downto 0);
VLC_AC_size : out unsigned(4 downto 0);
VLC_AC : out unsigned(15 downto 0)
);
end entity AC_ROM;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ARCHITECTURE ------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture RTL of AC_ROM is
signal rom_addr : std_logic_vector(7 downto 0);
-------------------------------------------------------------------------------
-- Architecture: begin
-------------------------------------------------------------------------------
begin
rom_addr <= runlength & VLI_size;
-------------------------------------------------------------------
-- AC-ROM
-------------------------------------------------------------------
p_AC_ROM : process(CLK, RST)
begin
if RST = '1' then
VLC_AC_size <= (others => '0');
VLC_AC <= (others => '0');
elsif CLK'event and CLK = '1' then
case runlength is
when X"0" =>
case VLI_size is
when X"0" =>
VLC_AC_size <= to_unsigned(4, VLC_AC_size'length);
VLC_AC <= resize("1010", VLC_AC'length);
when X"1" =>
VLC_AC_size <= to_unsigned(2, VLC_AC_size'length);
VLC_AC <= resize("00", VLC_AC'length);
when X"2" =>
VLC_AC_size <= to_unsigned(2, VLC_AC_size'length);
VLC_AC <= resize("01", VLC_AC'length);
when X"3" =>
VLC_AC_size <= to_unsigned(3, VLC_AC_size'length);
VLC_AC <= resize("100", VLC_AC'length);
when X"4" =>
VLC_AC_size <= to_unsigned(4, VLC_AC_size'length);
VLC_AC <= resize("1011", VLC_AC'length);
when X"5" =>
VLC_AC_size <= to_unsigned(5, VLC_AC_size'length);
VLC_AC <= resize("11010", VLC_AC'length);
when X"6" =>
VLC_AC_size <= to_unsigned(7, VLC_AC_size'length);
VLC_AC <= resize("1111000", VLC_AC'length);
when X"7" =>
VLC_AC_size <= to_unsigned(8, VLC_AC_size'length);
VLC_AC <= resize("11111000", VLC_AC'length);
when X"8" =>
VLC_AC_size <= to_unsigned(10, VLC_AC_size'length);
VLC_AC <= resize("1111110110", VLC_AC'length);
when X"9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110000010", VLC_AC'length);
when X"A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110000011", VLC_AC'length);
when others =>
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length);
VLC_AC <= resize("0", VLC_AC'length);
end case;
when X"1" =>
case VLI_size is
when X"1" =>
VLC_AC_size <= to_unsigned(4, VLC_AC_size'length);
VLC_AC <= resize("1100", VLC_AC'length);
when X"2" =>
VLC_AC_size <= to_unsigned(5, VLC_AC_size'length);
VLC_AC <= resize("11011", VLC_AC'length);
when X"3" =>
VLC_AC_size <= to_unsigned(7, VLC_AC_size'length);
VLC_AC <= resize("1111001", VLC_AC'length);
when X"4" =>
VLC_AC_size <= to_unsigned(9, VLC_AC_size'length);
VLC_AC <= resize("111110110", VLC_AC'length);
when X"5" =>
VLC_AC_size <= to_unsigned(11, VLC_AC_size'length);
VLC_AC <= resize("11111110110", VLC_AC'length);
when X"6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110000100", VLC_AC'length);
when X"7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110000101", VLC_AC'length);
when X"8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110000110", VLC_AC'length);
when X"9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110000111", VLC_AC'length);
when X"A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110001000", VLC_AC'length);
when others =>
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length);
VLC_AC <= resize("0", VLC_AC'length);
end case;
when X"2" =>
case VLI_size is
when X"1" =>
VLC_AC_size <= to_unsigned(5, VLC_AC_size'length);
VLC_AC <= resize("11100", VLC_AC'length);
when X"2" =>
VLC_AC_size <= to_unsigned(8, VLC_AC_size'length);
VLC_AC <= resize("11111001", VLC_AC'length);
when X"3" =>
VLC_AC_size <= to_unsigned(10, VLC_AC_size'length);
VLC_AC <= resize("1111110111", VLC_AC'length);
when X"4" =>
VLC_AC_size <= to_unsigned(12, VLC_AC_size'length);
VLC_AC <= resize("111111110100", VLC_AC'length);
when X"5" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110001001", VLC_AC'length);
when X"6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110001010", VLC_AC'length);
when X"7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110001011", VLC_AC'length);
when X"8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110001100", VLC_AC'length);
when X"9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110001101", VLC_AC'length);
when X"A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110001110", VLC_AC'length);
when others =>
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length);
VLC_AC <= resize("0", VLC_AC'length);
end case;
when X"3" =>
case VLI_size is
when X"1" =>
VLC_AC_size <= to_unsigned(6, VLC_AC_size'length);
VLC_AC <= resize("111010", VLC_AC'length);
when X"2" =>
VLC_AC_size <= to_unsigned(9, VLC_AC_size'length);
VLC_AC <= resize("111110111", VLC_AC'length);
when X"3" =>
VLC_AC_size <= to_unsigned(12, VLC_AC_size'length);
VLC_AC <= resize("111111110101", VLC_AC'length);
when X"4" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110001111", VLC_AC'length);
when X"5" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110010000", VLC_AC'length);
when X"6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110010001", VLC_AC'length);
when X"7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110010010", VLC_AC'length);
when X"8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110010011", VLC_AC'length);
when X"9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110010100", VLC_AC'length);
when X"A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110010101", VLC_AC'length);
when others =>
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length);
VLC_AC <= resize("0", VLC_AC'length);
end case;
when X"4" =>
case VLI_size is
when X"1" =>
VLC_AC_size <= to_unsigned(6, VLC_AC_size'length);
VLC_AC <= resize("111011", VLC_AC'length);
when X"2" =>
VLC_AC_size <= to_unsigned(10, VLC_AC_size'length);
VLC_AC <= resize("1111111000", VLC_AC'length);
when X"3" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110010110", VLC_AC'length);
when X"4" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110010111", VLC_AC'length);
when X"5" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110011000", VLC_AC'length);
when X"6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110011001", VLC_AC'length);
when X"7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110011010", VLC_AC'length);
when X"8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110011011", VLC_AC'length);
when X"9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110011100", VLC_AC'length);
when X"A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110011101", VLC_AC'length);
when others =>
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length);
VLC_AC <= resize("0", VLC_AC'length);
end case;
when X"5" =>
case VLI_size is
when X"1" =>
VLC_AC_size <= to_unsigned(7, VLC_AC_size'length);
VLC_AC <= resize("1111010", VLC_AC'length);
when X"2" =>
VLC_AC_size <= to_unsigned(11, VLC_AC_size'length);
VLC_AC <= resize("11111110111", VLC_AC'length);
when X"3" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110011110", VLC_AC'length);
when X"4" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110011111", VLC_AC'length);
when X"5" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110100000", VLC_AC'length);
when X"6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110100001", VLC_AC'length);
when X"7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110100010", VLC_AC'length);
when X"8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110100011", VLC_AC'length);
when X"9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110100100", VLC_AC'length);
when X"A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110100101", VLC_AC'length);
when others =>
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length);
VLC_AC <= resize("0", VLC_AC'length);
end case;
when X"6" =>
case VLI_size is
when X"1" =>
VLC_AC_size <= to_unsigned(7, VLC_AC_size'length);
VLC_AC <= resize("1111011", VLC_AC'length);
when X"2" =>
VLC_AC_size <= to_unsigned(12, VLC_AC_size'length);
VLC_AC <= resize("111111110110", VLC_AC'length);
when X"3" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110100110", VLC_AC'length);
when X"4" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110100111", VLC_AC'length);
when X"5" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110101000", VLC_AC'length);
when X"6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110101001", VLC_AC'length);
when X"7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110101010", VLC_AC'length);
when X"8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110101011", VLC_AC'length);
when X"9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110101100", VLC_AC'length);
when X"A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110101101", VLC_AC'length);
when others =>
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length);
VLC_AC <= resize("0", VLC_AC'length);
end case;
when X"7" =>
case VLI_size is
when X"1" =>
VLC_AC_size <= to_unsigned(8, VLC_AC_size'length);
VLC_AC <= resize("11111010", VLC_AC'length);
when X"2" =>
VLC_AC_size <= to_unsigned(12, VLC_AC_size'length);
VLC_AC <= resize("111111110111", VLC_AC'length);
when X"3" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110101110", VLC_AC'length);
when X"4" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110101111", VLC_AC'length);
when X"5" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110110000", VLC_AC'length);
when X"6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110110001", VLC_AC'length);
when X"7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110110010", VLC_AC'length);
when X"8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110110011", VLC_AC'length);
when X"9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110110100", VLC_AC'length);
when X"A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110110101", VLC_AC'length);
when others =>
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length);
VLC_AC <= resize("0", VLC_AC'length);
end case;
when X"8" =>
case VLI_size is
when X"1" =>
VLC_AC_size <= to_unsigned(9, VLC_AC_size'length);
VLC_AC <= resize("111111000", VLC_AC'length);
when X"2" =>
VLC_AC_size <= to_unsigned(15, VLC_AC_size'length);
VLC_AC <= resize("111111111000000", VLC_AC'length);
when X"3" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110110110", VLC_AC'length);
when X"4" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110110111", VLC_AC'length);
when X"5" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110111000", VLC_AC'length);
when X"6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110111001", VLC_AC'length);
when X"7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110111010", VLC_AC'length);
when X"8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110111011", VLC_AC'length);
when X"9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110111100", VLC_AC'length);
when X"A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110111101", VLC_AC'length);
when others =>
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length);
VLC_AC <= resize("0", VLC_AC'length);
end case;
when X"9" =>
case VLI_size is
when X"1" =>
VLC_AC_size <= to_unsigned(9, VLC_AC_size'length);
VLC_AC <= resize("111111001", VLC_AC'length);
when X"2" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110111110", VLC_AC'length);
when X"3" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110111111", VLC_AC'length);
when X"4" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111000000", VLC_AC'length);
when X"5" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111000001", VLC_AC'length);
when X"6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111000010", VLC_AC'length);
when X"7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111000011", VLC_AC'length);
when X"8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111000100", VLC_AC'length);
when X"9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111000101", VLC_AC'length);
when X"A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111000110", VLC_AC'length);
when others =>
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length);
VLC_AC <= resize("0", VLC_AC'length);
end case;
when X"A" =>
case VLI_size is
when X"1" =>
VLC_AC_size <= to_unsigned(9, VLC_AC_size'length);
VLC_AC <= resize("111111010", VLC_AC'length);
when X"2" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111000111", VLC_AC'length);
when X"3" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111001000", VLC_AC'length);
when X"4" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111001001", VLC_AC'length);
when X"5" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111001010", VLC_AC'length);
when X"6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111001011", VLC_AC'length);
when X"7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111001100", VLC_AC'length);
when X"8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111001101", VLC_AC'length);
when X"9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111001110", VLC_AC'length);
when X"A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111001111", VLC_AC'length);
when others =>
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length);
VLC_AC <= resize("0", VLC_AC'length);
end case;
when X"B" =>
case VLI_size is
when X"1" =>
VLC_AC_size <= to_unsigned(10, VLC_AC_size'length);
VLC_AC <= resize("1111111001", VLC_AC'length);
when X"2" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111010000", VLC_AC'length);
when X"3" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111010001", VLC_AC'length);
when X"4" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111010010", VLC_AC'length);
when X"5" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111010011", VLC_AC'length);
when X"6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111010100", VLC_AC'length);
when X"7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111010101", VLC_AC'length);
when X"8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111010110", VLC_AC'length);
when X"9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111010111", VLC_AC'length);
when X"A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111011000", VLC_AC'length);
when others =>
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length);
VLC_AC <= resize("0", VLC_AC'length);
end case;
when X"C" =>
case VLI_size is
when X"1" =>
VLC_AC_size <= to_unsigned(10, VLC_AC_size'length);
VLC_AC <= resize("1111111010", VLC_AC'length);
when X"2" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111011001", VLC_AC'length);
when X"3" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111011010", VLC_AC'length);
when X"4" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111011011", VLC_AC'length);
when X"5" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111011100", VLC_AC'length);
when X"6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111011101", VLC_AC'length);
when X"7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111011110", VLC_AC'length);
when X"8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111011111", VLC_AC'length);
when X"9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111100000", VLC_AC'length);
when X"A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111100001", VLC_AC'length);
when others =>
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length);
VLC_AC <= resize("0", VLC_AC'length);
end case;
when X"D" =>
case VLI_size is
when X"1" =>
VLC_AC_size <= to_unsigned(11, VLC_AC_size'length);
VLC_AC <= resize("11111111000", VLC_AC'length);
when X"2" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111100010", VLC_AC'length);
when X"3" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111100011", VLC_AC'length);
when X"4" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111100100", VLC_AC'length);
when X"5" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111100101", VLC_AC'length);
when X"6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111100110", VLC_AC'length);
when X"7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111100111", VLC_AC'length);
when X"8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111101000", VLC_AC'length);
when X"9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111101001", VLC_AC'length);
when X"A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111101010", VLC_AC'length);
when others =>
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length);
VLC_AC <= resize("0", VLC_AC'length);
end case;
when X"E" =>
case VLI_size is
when X"1" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111101011", VLC_AC'length);
when X"2" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111101100", VLC_AC'length);
when X"3" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111101101", VLC_AC'length);
when X"4" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111101110", VLC_AC'length);
when X"5" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111101111", VLC_AC'length);
when X"6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111110000", VLC_AC'length);
when X"7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111110001", VLC_AC'length);
when X"8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111110010", VLC_AC'length);
when X"9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111110011", VLC_AC'length);
when X"A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111110100", VLC_AC'length);
when others =>
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length);
VLC_AC <= resize("0", VLC_AC'length);
end case;
when X"F" =>
case VLI_size is
when X"0" =>
VLC_AC_size <= to_unsigned(11, VLC_AC_size'length);
VLC_AC <= resize("11111111001", VLC_AC'length);
when X"1" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111110101", VLC_AC'length);
when X"2" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111110110", VLC_AC'length);
when X"3" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111110111", VLC_AC'length);
when X"4" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111111000", VLC_AC'length);
when X"5" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111111001", VLC_AC'length);
when X"6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111111010", VLC_AC'length);
when X"7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111111011", VLC_AC'length);
when X"8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111111100", VLC_AC'length);
when X"9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111111101", VLC_AC'length);
when X"A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111111110", VLC_AC'length);
when others =>
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length);
VLC_AC <= resize("0", VLC_AC'length);
end case;
when others =>
VLC_AC_size <= (others => '0');
VLC_AC <= (others => '0');
end case;
end if;
end process;
end architecture RTL;
-------------------------------------------------------------------------------
-- Architecture: end
------------------------------------------------------------------------------- | lgpl-3.0 | 7082968715481511314fb1919dfb50f3 | 0.436026 | 3.929879 | false | false | false | false |
markusC64/1541ultimate2 | fpga/nios_dut/nios_dut/synthesis/submodules/jtag_client.vhd | 2 | 17,356 | --------------------------------------------------------------------------------
-- Entity: jtag_client
-- Date:2016-11-08
-- Author: Gideon
--
-- Description: Client for Virtual JTAG module
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity jtag_client is
port (
avm_clock : in std_logic;
avm_reset : in std_logic;
avm_read : out std_logic;
avm_write : out std_logic;
avm_byteenable : out std_logic_vector(3 downto 0);
avm_address : out std_logic_vector(31 downto 0);
avm_writedata : out std_logic_vector(31 downto 0);
avm_readdata : in std_logic_vector(31 downto 0);
avm_readdatavalid : in std_logic;
avm_waitrequest : in std_logic;
clock_1 : in std_logic;
clock_2 : in std_logic;
sample_vector : in std_logic_vector(47 downto 0);
write_vector : out std_logic_vector(7 downto 0) );
end entity;
architecture arch of jtag_client is
component virtual_jtag is
port (
tdi : out std_logic; -- tdi
tdo : in std_logic := 'X'; -- tdo
ir_in : out std_logic_vector(3 downto 0); -- ir_in
ir_out : in std_logic_vector(3 downto 0) := (others => 'X'); -- ir_out
virtual_state_cdr : out std_logic; -- virtual_state_cdr
virtual_state_sdr : out std_logic; -- virtual_state_sdr
virtual_state_e1dr : out std_logic; -- virtual_state_e1dr
virtual_state_pdr : out std_logic; -- virtual_state_pdr
virtual_state_e2dr : out std_logic; -- virtual_state_e2dr
virtual_state_udr : out std_logic; -- virtual_state_udr
virtual_state_cir : out std_logic; -- virtual_state_cir
virtual_state_uir : out std_logic; -- virtual_state_uir
tck : out std_logic -- clk
);
end component virtual_jtag;
constant c_rom : std_logic_vector(31 downto 0) := X"DEAD1541";
signal shiftreg_sample : std_logic_vector(sample_vector'range);
signal shiftreg_write : std_logic_vector(write_vector'range);
signal shiftreg_debug : std_logic_vector(24 downto 0);
signal shiftreg_clock : std_logic_vector(7 downto 0);
signal debug_bits : std_logic_vector(4 downto 0);
signal clock_1_shift : std_logic_vector(7 downto 0) := X"00";
signal clock_2_shift : std_logic_vector(7 downto 0) := X"00";
signal bypass_reg : std_logic;
signal bit_count : unsigned(4 downto 0) := (others => '0');
signal tdi : std_logic; -- tdi
signal tdo : std_logic := 'X'; -- tdo
signal ir_in : std_logic_vector(3 downto 0); -- ir_in
signal ir_out : std_logic_vector(3 downto 0) := (others => 'X'); -- ir_out
signal virtual_state_cdr : std_logic; -- virtual_state_cdr
signal virtual_state_sdr : std_logic; -- virtual_state_sdr
signal virtual_state_e1dr : std_logic; -- virtual_state_e1dr
signal virtual_state_pdr : std_logic; -- virtual_state_pdr
signal virtual_state_e2dr : std_logic; -- virtual_state_e2dr
signal virtual_state_udr : std_logic; -- virtual_state_udr
signal virtual_state_cir : std_logic; -- virtual_state_cir
signal virtual_state_uir : std_logic; -- virtual_state_uir
signal tck : std_logic; -- clk
signal write_fifo_full : std_logic;
signal write_fifo_put : std_logic := '0';
signal write_fifo_din : std_logic_vector(11 downto 0);
signal read_fifo_get : std_logic;
signal shiftreg_fifo : std_logic_vector(15 downto 0);
signal read_fifo_count : unsigned(7 downto 0);
signal read_fifo_data : std_logic_vector(7 downto 0);
signal cmd_count : unsigned(7 downto 0) := X"00";
signal last_command : std_logic_vector(11 downto 0);
-- signals that live in the avm clock domain
type t_state is (idle, do_write, do_read, do_read2, do_read3);
signal state : t_state;
signal incrementing : std_logic;
signal byte_count : integer range 0 to 3;
signal read_count : unsigned(7 downto 0);
signal avm_read_reg : std_logic_vector(31 downto 0) := (others => '0');
signal write_enabled : std_logic;
signal write_data : std_logic_vector(31 downto 0) := (others => '0');
signal write_be : std_logic_vector(3 downto 0) := (others => '0');
signal address : unsigned(31 downto 0) := (others => '0');
signal avm_rfifo_put : std_logic;
signal avm_rfifo_full : std_logic;
signal avm_wfifo_get : std_logic;
signal avm_wfifo_valid : std_logic;
signal avm_read_i : std_logic;
signal avm_write_i : std_logic;
signal avm_wfifo_dout : std_logic_vector(11 downto 0);
signal avm_wfifo_count : unsigned(4 downto 0);
signal avm_exec_count : unsigned(2 downto 0) := "000";
signal avm_clock_count : unsigned(2 downto 0) := "000";
begin
i_vj: virtual_jtag
port map (
tdi => tdi,
tdo => tdo,
ir_in => ir_in,
ir_out => ir_out,
virtual_state_cdr => virtual_state_cdr,
virtual_state_sdr => virtual_state_sdr,
virtual_state_e1dr => virtual_state_e1dr,
virtual_state_pdr => virtual_state_pdr,
virtual_state_e2dr => virtual_state_e2dr,
virtual_state_udr => virtual_state_udr,
virtual_state_cir => virtual_state_cir,
virtual_state_uir => virtual_state_uir,
tck => tck
);
process(tck)
begin
if rising_edge(tck) then
read_fifo_get <= '0';
write_fifo_put <= '0';
if write_fifo_put = '1' then
last_command <= write_fifo_din;
end if;
if virtual_state_sdr = '1' then
bypass_reg <= tdi;
shiftreg_sample <= tdi & shiftreg_sample(shiftreg_sample'high downto 1);
shiftreg_write <= tdi & shiftreg_write(shiftreg_write'high downto 1);
shiftreg_debug <= tdi & shiftreg_debug(shiftreg_debug'high downto 1);
shiftreg_clock <= tdi & shiftreg_clock(shiftreg_clock'high downto 1);
bit_count <= bit_count + 1;
if ir_in = X"4" then
if bit_count(2 downto 0) = "111" then
shiftreg_fifo <= X"00" & read_fifo_data;
read_fifo_get <= not tdi;
else
shiftreg_fifo <= '0' & shiftreg_fifo(shiftreg_fifo'high downto 1);
end if;
elsif ir_in = X"5" then
shiftreg_fifo <= tdi & shiftreg_fifo(shiftreg_fifo'high downto 1);
if bit_count(3 downto 0) = "1111" then
write_fifo_put <= '1';
cmd_count <= cmd_count + 1;
end if;
elsif ir_in = X"6" then
shiftreg_fifo <= tdi & shiftreg_fifo(shiftreg_fifo'high downto 1);
if bit_count(2 downto 0) = "111" then
write_fifo_put <= '1';
cmd_count <= cmd_count + 1;
end if;
end if;
end if;
if virtual_state_cdr = '1' then
shiftreg_write <= (others => '0');
shiftreg_sample <= sample_vector;
bit_count <= (others => '0');
shiftreg_fifo <= X"00" & std_logic_vector(read_fifo_count);
shiftreg_debug <= debug_bits & last_command & std_logic_vector(cmd_count);
if ir_in = X"8" then
shiftreg_clock <= clock_1_shift;
end if;
if ir_in = X"9" then
shiftreg_clock <= clock_2_shift;
end if;
end if;
if virtual_state_udr = '1' then
case ir_in is
when X"2" =>
write_vector <= shiftreg_write;
when others =>
null;
end case;
end if;
end if;
end process;
process(clock_1)
begin
if rising_edge(clock_1) then
clock_1_shift <= clock_1_shift(6 downto 0) & not clock_1_shift(7);
end if;
end process;
process(clock_2)
begin
if rising_edge(clock_2) then
clock_2_shift <= clock_2_shift(6 downto 0) & not clock_2_shift(7);
end if;
end process;
process(ir_in, bit_count, shiftreg_sample, shiftreg_write, bypass_reg, shiftreg_fifo, shiftreg_debug, shiftreg_clock)
begin
case ir_in is
when X"0" =>
tdo <= c_rom(to_integer(bit_count));
when X"1" =>
tdo <= shiftreg_sample(0);
when X"2" =>
tdo <= shiftreg_write(0);
when X"3" =>
tdo <= shiftreg_debug(0);
when X"4" =>
tdo <= shiftreg_fifo(0);
when X"8" | X"9" =>
tdo <= shiftreg_clock(0);
when others =>
tdo <= bypass_reg;
end case;
end process;
-- Avalon JTAG commands
-- E000 => write data (byte is data)
-- x0010 => Start Write Non Incrementing (only upper bit of byte used)
-- x0011 => Start Write incrementing (only upper bit of byte used)
-- x010 => Do Read Non-Incrementing (byte is length)
-- x011 => Do Read incrementing (byte is length)
-- x1xx => Set address (bytes is address data) xx = index of address byte
--
write_fifo_din <= ("1000" & shiftreg_fifo(15 downto 8)) when ir_in = X"6" else
(shiftreg_fifo(11 downto 0));
i_write_fifo: entity work.async_fifo_ft
generic map(
g_data_width => 12,
g_depth_bits => 4
)
port map (
wr_clock => tck,
wr_reset => '0',
wr_en => write_fifo_put,
wr_din => write_fifo_din,
wr_full => write_fifo_full,
rd_clock => avm_clock,
rd_reset => avm_reset,
rd_next => avm_wfifo_get,
rd_dout => avm_wfifo_dout,
rd_valid => avm_wfifo_valid,
rd_count => avm_wfifo_count
);
i_read_fifo: entity work.async_fifo_ft
generic map(
g_data_width => 8,
g_depth_bits => 7 )
port map(
wr_clock => avm_clock,
wr_reset => avm_reset,
wr_en => avm_rfifo_put,
wr_din => avm_read_reg(7 downto 0),
wr_full => avm_rfifo_full,
rd_clock => tck,
rd_reset => '0',
rd_next => read_fifo_get,
rd_dout => read_fifo_data,
rd_valid => open,
rd_count => read_fifo_count
);
process(avm_clock)
variable v_cmd : std_logic_vector(2 downto 0);
begin
if rising_edge(avm_clock) then
avm_clock_count <= avm_clock_count + 1;
case state is
when idle =>
avm_rfifo_put <= '0';
if avm_wfifo_valid = '1' then -- command?
avm_exec_count <= avm_exec_count + 1;
v_cmd := avm_wfifo_dout(10 downto 8);
case v_cmd is
when "000" =>
if write_enabled = '1' then
write_be(3) <= avm_wfifo_dout(11);
write_data(31 downto 24) <= avm_wfifo_dout(7 downto 0);
write_be(2 downto 0) <= write_be(3 downto 1);
write_data(23 downto 00) <= write_data(31 downto 8);
if byte_count = 3 then
avm_write_i <= '1';
state <= do_write;
byte_count <= 0;
else
byte_count <= byte_count + 1;
end if;
end if;
when "001" =>
byte_count <= 0;
write_enabled <= '1';
incrementing <= avm_wfifo_dout(7);
when "010" | "011" =>
write_enabled <= '0';
read_count <= unsigned(avm_wfifo_dout(7 downto 0));
state <= do_read;
incrementing <= v_cmd(0);
when "100" =>
write_enabled <= '0';
address(7 downto 0) <= unsigned(avm_wfifo_dout(7 downto 0));
when "101" =>
write_enabled <= '0';
address(15 downto 8) <= unsigned(avm_wfifo_dout(7 downto 0));
when "110" =>
write_enabled <= '0';
address(23 downto 16) <= unsigned(avm_wfifo_dout(7 downto 0));
when "111" =>
write_enabled <= '0';
address(31 downto 24) <= unsigned(avm_wfifo_dout(7 downto 0));
when others =>
null;
end case;
end if;
when do_write =>
if avm_waitrequest = '0' then
avm_write_i <= '0';
state <= idle;
if incrementing = '1' then
address(31 downto 2) <= address(31 downto 2) + 1;
end if;
end if;
when do_read =>
write_be <= "1111";
avm_read_i <= '1';
state <= do_read2;
when do_read2 =>
if avm_waitrequest = '0' then
avm_read_i <= '0';
end if;
if avm_readdatavalid = '1' then
avm_read_reg <= avm_readdata;
byte_count <= 0;
avm_rfifo_put <= '1';
state <= do_read3;
end if;
when do_read3 =>
if avm_rfifo_full = '0' then
if byte_count = 3 then
byte_count <= 0;
avm_rfifo_put <= '0';
read_count <= read_count - 1;
if read_count = 0 then
state <= idle;
else
state <= do_read;
if incrementing = '1' then
address(31 downto 2) <= address(31 downto 2) + 1;
end if;
end if;
else
byte_count <= byte_count + 1;
avm_read_reg(23 downto 0) <= avm_read_reg(31 downto 8);
end if;
end if;
when others =>
null;
end case;
if avm_reset = '1' then
state <= idle;
incrementing <= '0';
byte_count <= 0;
read_count <= (others => '0');
write_enabled <= '0';
write_be <= "0000";
avm_read_i <= '0';
avm_write_i <= '0';
avm_rfifo_put <= '0';
avm_exec_count <= "000";
end if;
end if;
end process;
with state select debug_bits(2 downto 0) <=
"000" when idle,
"001" when do_write,
"010" when do_read,
"011" when do_read2,
"100" when do_read3,
"111" when others;
debug_bits(3) <= avm_read_i;
debug_bits(4) <= avm_write_i;
avm_read <= avm_read_i;
avm_write <= avm_write_i;
avm_wfifo_get <= '1' when avm_wfifo_valid = '1' and state = idle else '0';
avm_address <= std_logic_vector(address(31 downto 2) & "00");
avm_byteenable <= write_be;
avm_writedata <= write_data;
end arch;
| gpl-3.0 | 727f613da145c89251eebdbc661453f9 | 0.440597 | 4.192271 | false | false | false | false |
chiggs/nvc | test/regress/wait13.vhd | 5 | 838 | entity wait13 is
end entity;
architecture test of wait13 is
procedure wait_for (
signal s : in bit;
value : in bit;
timeout : in delay_length ) is
begin
if s /= value then
my_wait: wait on s until s = value for timeout;
assert s = value
report "timeout waiting for " & s'path_name;
end if;
end procedure;
signal x : bit;
begin
wait_for_p: process is
begin
wait_for(x, '1', 5 ns);
wait_for(x, '0', 10 us);
wait until x = '0' for 10 ns;
assert now = 12 ns;
wait;
end process;
stim_p: process is
begin
wait for 1 ns;
x <= '1';
wait for 1 ns;
x <= '0';
wait for 4 ns;
x <= '1';
wait;
end process;
end architecture;
| gpl-3.0 | 18bef0eafc83316ec37f2cc300bb484f | 0.491647 | 3.707965 | false | false | false | false |
markusC64/1541ultimate2 | fpga/cart_slot/vhdl_source/reu_pkg.vhd | 1 | 1,327 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package reu_pkg is
constant c_status : unsigned(7 downto 0) := X"00";
constant c_command : unsigned(7 downto 0) := X"01";
constant c_c64base_l : unsigned(7 downto 0) := X"02";
constant c_c64base_h : unsigned(7 downto 0) := X"03";
constant c_reubase_l : unsigned(7 downto 0) := X"04";
constant c_reubase_m : unsigned(7 downto 0) := X"05";
constant c_reubase_h : unsigned(7 downto 0) := X"06";
constant c_translen_l : unsigned(7 downto 0) := X"07";
constant c_translen_h : unsigned(7 downto 0) := X"08";
constant c_irqmask : unsigned(7 downto 0) := X"09";
constant c_control : unsigned(7 downto 0) := X"0A";
-- extended registers
constant c_size_read : unsigned(7 downto 0) := X"0C";
constant c_start_delay: unsigned(7 downto 0) := X"0D";
constant c_rate_div : unsigned(7 downto 0) := X"0E";
constant c_translen_x : unsigned(7 downto 0) := X"0F";
constant c_mode_toreu : std_logic_vector(1 downto 0) := "00";
constant c_mode_toc64 : std_logic_vector(1 downto 0) := "01";
constant c_mode_swap : std_logic_vector(1 downto 0) := "10";
constant c_mode_verify : std_logic_vector(1 downto 0) := "11";
end;
| gpl-3.0 | ff4ef45f4f9dd74affff244b965b497e | 0.599096 | 2.982022 | false | false | false | false |
xiadz/oscilloscope | ipcore_dir/clock_108mhz.vhd | 1 | 2,902 | --------------------------------------------------------------------------------
-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 13.1
-- \ \ Application : xaw2vhdl
-- / / Filename : clock_108mhz.vhd
-- /___/ /\ Timestamp : 04/20/2011 20:13:56
-- \ \ / \
-- \___\/\___\
--
--Command: xaw2vhdl-st /home/xiadz/prog/fpga/oscilloscope/ipcore_dir/./clock_108mhz.xaw /home/xiadz/prog/fpga/oscilloscope/ipcore_dir/./clock_108mhz
--Design Name: clock_108mhz
--Device: xc3s100e-5cp132
--
-- Module clock_108mhz
-- Generated by Xilinx Architecture Wizard
-- Written for synthesis tool: XST
-- Period Jitter (unit interval) for block DCM_SP_INST = 0.11 UI
-- Period Jitter (Peak-to-Peak) for block DCM_SP_INST = 1.01 ns
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
entity clock_108mhz is
port ( CLKIN_IN : in std_logic;
RST_IN : in std_logic;
CLKFX_OUT : out std_logic;
CLKIN_IBUFG_OUT : out std_logic;
LOCKED_OUT : out std_logic);
end clock_108mhz;
architecture BEHAVIORAL of clock_108mhz is
signal CLKFX_BUF : std_logic;
signal CLKIN_IBUFG : std_logic;
signal GND_BIT : std_logic;
begin
GND_BIT <= '0';
CLKIN_IBUFG_OUT <= CLKIN_IBUFG;
CLKFX_BUFG_INST : BUFG
port map (I=>CLKFX_BUF,
O=>CLKFX_OUT);
CLKIN_IBUFG_INST : IBUFG
port map (I=>CLKIN_IN,
O=>CLKIN_IBUFG);
DCM_SP_INST : DCM_SP
generic map( CLK_FEEDBACK => "NONE",
CLKDV_DIVIDE => 2.0,
CLKFX_DIVIDE => 13,
CLKFX_MULTIPLY => 28,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 20.000,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => TRUE,
FACTORY_JF => x"C080",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map (CLKFB=>GND_BIT,
CLKIN=>CLKIN_IBUFG,
DSSEN=>GND_BIT,
PSCLK=>GND_BIT,
PSEN=>GND_BIT,
PSINCDEC=>GND_BIT,
RST=>RST_IN,
CLKDV=>open,
CLKFX=>CLKFX_BUF,
CLKFX180=>open,
CLK0=>open,
CLK2X=>open,
CLK2X180=>open,
CLK90=>open,
CLK180=>open,
CLK270=>open,
LOCKED=>LOCKED_OUT,
PSDONE=>open,
STATUS=>open);
end BEHAVIORAL;
| mit | 2dceccc250c839b1bd46f14d4b035b6b | 0.481048 | 3.788512 | false | false | false | false |
ntb-ch/cb20 | FPGA_Designs/mpu9250/cb20/synthesis/cb20_pwm_interface_0_avalon_slave_0_translator.vhd | 1 | 14,679 | -- cb20_pwm_interface_0_avalon_slave_0_translator.vhd
-- Generated using ACDS version 13.0sp1 232 at 2016.10.12.10:12:44
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity cb20_pwm_interface_0_avalon_slave_0_translator is
generic (
AV_ADDRESS_W : integer := 6;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 1;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 17;
UAV_BURSTCOUNT_W : integer := 3;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 0;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 1;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := '0'; -- clk.clk
reset : in std_logic := '0'; -- reset.reset
uav_address : in std_logic_vector(16 downto 0) := (others => '0'); -- avalon_universal_slave_0.address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => '0'); -- .burstcount
uav_read : in std_logic := '0'; -- .read
uav_write : in std_logic := '0'; -- .write
uav_waitrequest : out std_logic; -- .waitrequest
uav_readdatavalid : out std_logic; -- .readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => '0'); -- .byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- .readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
uav_lock : in std_logic := '0'; -- .lock
uav_debugaccess : in std_logic := '0'; -- .debugaccess
av_address : out std_logic_vector(5 downto 0); -- avalon_anti_slave_0.address
av_write : out std_logic; -- .write
av_read : out std_logic; -- .read
av_readdata : in std_logic_vector(31 downto 0) := (others => '0'); -- .readdata
av_writedata : out std_logic_vector(31 downto 0); -- .writedata
av_byteenable : out std_logic_vector(3 downto 0); -- .byteenable
av_waitrequest : in std_logic := '0'; -- .waitrequest
av_beginbursttransfer : out std_logic;
av_begintransfer : out std_logic;
av_burstcount : out std_logic_vector(0 downto 0);
av_chipselect : out std_logic;
av_clken : out std_logic;
av_debugaccess : out std_logic;
av_lock : out std_logic;
av_outputenable : out std_logic;
av_readdatavalid : in std_logic := '0';
av_response : in std_logic_vector(1 downto 0) := (others => '0');
av_writebyteenable : out std_logic_vector(3 downto 0);
av_writeresponserequest : out std_logic;
av_writeresponsevalid : in std_logic := '0';
uav_clken : in std_logic := '0';
uav_response : out std_logic_vector(1 downto 0);
uav_writeresponserequest : in std_logic := '0';
uav_writeresponsevalid : out std_logic
);
end entity cb20_pwm_interface_0_avalon_slave_0_translator;
architecture rtl of cb20_pwm_interface_0_avalon_slave_0_translator is
component altera_merlin_slave_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(16 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(5 downto 0); -- address
av_write : out std_logic; -- write
av_read : out std_logic; -- read
av_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(31 downto 0); -- writedata
av_byteenable : out std_logic_vector(3 downto 0); -- byteenable
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_writebyteenable : out std_logic_vector(3 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_chipselect : out std_logic; -- chipselect
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic; -- outputenable
uav_response : out std_logic_vector(1 downto 0); -- response
av_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response
uav_writeresponserequest : in std_logic := 'X'; -- writeresponserequest
uav_writeresponsevalid : out std_logic; -- writeresponsevalid
av_writeresponserequest : out std_logic; -- writeresponserequest
av_writeresponsevalid : in std_logic := 'X' -- writeresponsevalid
);
end component altera_merlin_slave_translator;
begin
pwm_interface_0_avalon_slave_0_translator : component altera_merlin_slave_translator
generic map (
AV_ADDRESS_W => AV_ADDRESS_W,
AV_DATA_W => AV_DATA_W,
UAV_DATA_W => UAV_DATA_W,
AV_BURSTCOUNT_W => AV_BURSTCOUNT_W,
AV_BYTEENABLE_W => AV_BYTEENABLE_W,
UAV_BYTEENABLE_W => UAV_BYTEENABLE_W,
UAV_ADDRESS_W => UAV_ADDRESS_W,
UAV_BURSTCOUNT_W => UAV_BURSTCOUNT_W,
AV_READLATENCY => AV_READLATENCY,
USE_READDATAVALID => USE_READDATAVALID,
USE_WAITREQUEST => USE_WAITREQUEST,
USE_UAV_CLKEN => USE_UAV_CLKEN,
USE_READRESPONSE => USE_READRESPONSE,
USE_WRITERESPONSE => USE_WRITERESPONSE,
AV_SYMBOLS_PER_WORD => AV_SYMBOLS_PER_WORD,
AV_ADDRESS_SYMBOLS => AV_ADDRESS_SYMBOLS,
AV_BURSTCOUNT_SYMBOLS => AV_BURSTCOUNT_SYMBOLS,
AV_CONSTANT_BURST_BEHAVIOR => AV_CONSTANT_BURST_BEHAVIOR,
UAV_CONSTANT_BURST_BEHAVIOR => UAV_CONSTANT_BURST_BEHAVIOR,
AV_REQUIRE_UNALIGNED_ADDRESSES => AV_REQUIRE_UNALIGNED_ADDRESSES,
CHIPSELECT_THROUGH_READLATENCY => CHIPSELECT_THROUGH_READLATENCY,
AV_READ_WAIT_CYCLES => AV_READ_WAIT_CYCLES,
AV_WRITE_WAIT_CYCLES => AV_WRITE_WAIT_CYCLES,
AV_SETUP_WAIT_CYCLES => AV_SETUP_WAIT_CYCLES,
AV_DATA_HOLD_CYCLES => AV_DATA_HOLD_CYCLES
)
port map (
clk => clk, -- clk.clk
reset => reset, -- reset.reset
uav_address => uav_address, -- avalon_universal_slave_0.address
uav_burstcount => uav_burstcount, -- .burstcount
uav_read => uav_read, -- .read
uav_write => uav_write, -- .write
uav_waitrequest => uav_waitrequest, -- .waitrequest
uav_readdatavalid => uav_readdatavalid, -- .readdatavalid
uav_byteenable => uav_byteenable, -- .byteenable
uav_readdata => uav_readdata, -- .readdata
uav_writedata => uav_writedata, -- .writedata
uav_lock => uav_lock, -- .lock
uav_debugaccess => uav_debugaccess, -- .debugaccess
av_address => av_address, -- avalon_anti_slave_0.address
av_write => av_write, -- .write
av_read => av_read, -- .read
av_readdata => av_readdata, -- .readdata
av_writedata => av_writedata, -- .writedata
av_byteenable => av_byteenable, -- .byteenable
av_waitrequest => av_waitrequest, -- .waitrequest
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_chipselect => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open, -- (terminated)
uav_response => open, -- (terminated)
av_response => "00", -- (terminated)
uav_writeresponserequest => '0', -- (terminated)
uav_writeresponsevalid => open, -- (terminated)
av_writeresponserequest => open, -- (terminated)
av_writeresponsevalid => '0' -- (terminated)
);
end architecture rtl; -- of cb20_pwm_interface_0_avalon_slave_0_translator
| apache-2.0 | eef7ea1222a7b5e5c3fc1d47cbcb68f8 | 0.430411 | 4.340331 | false | false | false | false |
markusC64/1541ultimate2 | fpga/io/audio/mul_add.vhd | 1 | 1,262 | --------------------------------------------------------------------------------
-- Entity: mul_add
-- Date:2018-08-02
-- Author: gideon
--
-- Description: VHDL only version of multiply accumulate with double accu
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mul_add is
port (
clock : in std_logic;
clear : in std_logic;
a : in signed(17 downto 0);
b : in signed(8 downto 0);
result : out signed(31 downto 0)
);
end entity;
architecture arch of mul_add is
signal mult : signed(26 downto 0);
signal accu_reg1 : signed(31 downto 0);
signal accu_reg2 : signed(31 downto 0);
begin
process(clock)
begin
if rising_edge(clock) then
if clear = '1' then
accu_reg1 <= (others => '0');
accu_reg2 <= (others => '0');
else
accu_reg1 <= accu_reg2 + mult;
accu_reg2 <= accu_reg1;
end if;
mult <= a * b;
end if;
end process;
result <= accu_reg1;
end architecture;
| gpl-3.0 | 5b8cdf9b1ef81ceb5b4c841bc73c437d | 0.438986 | 4.234899 | false | false | false | false |
ntb-ch/cb20 | FPGA_Designs/standard/cb20/synthesis/cb20_width_adapter.vhd | 1 | 10,430 | -- cb20_width_adapter.vhd
-- Generated using ACDS version 13.0sp1 232 at 2020.05.28.12:22:46
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity cb20_width_adapter is
generic (
IN_PKT_ADDR_H : integer := 34;
IN_PKT_ADDR_L : integer := 18;
IN_PKT_DATA_H : integer := 15;
IN_PKT_DATA_L : integer := 0;
IN_PKT_BYTEEN_H : integer := 17;
IN_PKT_BYTEEN_L : integer := 16;
IN_PKT_BYTE_CNT_H : integer := 43;
IN_PKT_BYTE_CNT_L : integer := 41;
IN_PKT_TRANS_COMPRESSED_READ : integer := 35;
IN_PKT_BURSTWRAP_H : integer := 44;
IN_PKT_BURSTWRAP_L : integer := 44;
IN_PKT_BURST_SIZE_H : integer := 47;
IN_PKT_BURST_SIZE_L : integer := 45;
IN_PKT_RESPONSE_STATUS_H : integer := 69;
IN_PKT_RESPONSE_STATUS_L : integer := 68;
IN_PKT_TRANS_EXCLUSIVE : integer := 40;
IN_PKT_BURST_TYPE_H : integer := 49;
IN_PKT_BURST_TYPE_L : integer := 48;
IN_ST_DATA_W : integer := 70;
OUT_PKT_ADDR_H : integer := 52;
OUT_PKT_ADDR_L : integer := 36;
OUT_PKT_DATA_H : integer := 31;
OUT_PKT_DATA_L : integer := 0;
OUT_PKT_BYTEEN_H : integer := 35;
OUT_PKT_BYTEEN_L : integer := 32;
OUT_PKT_BYTE_CNT_H : integer := 61;
OUT_PKT_BYTE_CNT_L : integer := 59;
OUT_PKT_TRANS_COMPRESSED_READ : integer := 53;
OUT_PKT_BURST_SIZE_H : integer := 65;
OUT_PKT_BURST_SIZE_L : integer := 63;
OUT_PKT_RESPONSE_STATUS_H : integer := 87;
OUT_PKT_RESPONSE_STATUS_L : integer := 86;
OUT_PKT_TRANS_EXCLUSIVE : integer := 58;
OUT_PKT_BURST_TYPE_H : integer := 67;
OUT_PKT_BURST_TYPE_L : integer := 66;
OUT_ST_DATA_W : integer := 88;
ST_CHANNEL_W : integer := 6;
OPTIMIZE_FOR_RSP : integer := 0;
RESPONSE_PATH : integer := 0
);
port (
clk : in std_logic := '0'; -- clk.clk
reset : in std_logic := '0'; -- clk_reset.reset
in_valid : in std_logic := '0'; -- sink.valid
in_channel : in std_logic_vector(5 downto 0) := (others => '0'); -- .channel
in_startofpacket : in std_logic := '0'; -- .startofpacket
in_endofpacket : in std_logic := '0'; -- .endofpacket
in_ready : out std_logic; -- .ready
in_data : in std_logic_vector(69 downto 0) := (others => '0'); -- .data
out_endofpacket : out std_logic; -- src.endofpacket
out_data : out std_logic_vector(87 downto 0); -- .data
out_channel : out std_logic_vector(5 downto 0); -- .channel
out_valid : out std_logic; -- .valid
out_ready : in std_logic := '0'; -- .ready
out_startofpacket : out std_logic; -- .startofpacket
in_command_size_data : in std_logic_vector(2 downto 0) := (others => '0')
);
end entity cb20_width_adapter;
architecture rtl of cb20_width_adapter is
component altera_merlin_width_adapter is
generic (
IN_PKT_ADDR_H : integer := 60;
IN_PKT_ADDR_L : integer := 36;
IN_PKT_DATA_H : integer := 31;
IN_PKT_DATA_L : integer := 0;
IN_PKT_BYTEEN_H : integer := 35;
IN_PKT_BYTEEN_L : integer := 32;
IN_PKT_BYTE_CNT_H : integer := 63;
IN_PKT_BYTE_CNT_L : integer := 61;
IN_PKT_TRANS_COMPRESSED_READ : integer := 65;
IN_PKT_BURSTWRAP_H : integer := 67;
IN_PKT_BURSTWRAP_L : integer := 66;
IN_PKT_BURST_SIZE_H : integer := 70;
IN_PKT_BURST_SIZE_L : integer := 68;
IN_PKT_RESPONSE_STATUS_H : integer := 72;
IN_PKT_RESPONSE_STATUS_L : integer := 71;
IN_PKT_TRANS_EXCLUSIVE : integer := 73;
IN_PKT_BURST_TYPE_H : integer := 75;
IN_PKT_BURST_TYPE_L : integer := 74;
IN_ST_DATA_W : integer := 76;
OUT_PKT_ADDR_H : integer := 60;
OUT_PKT_ADDR_L : integer := 36;
OUT_PKT_DATA_H : integer := 31;
OUT_PKT_DATA_L : integer := 0;
OUT_PKT_BYTEEN_H : integer := 35;
OUT_PKT_BYTEEN_L : integer := 32;
OUT_PKT_BYTE_CNT_H : integer := 63;
OUT_PKT_BYTE_CNT_L : integer := 61;
OUT_PKT_TRANS_COMPRESSED_READ : integer := 65;
OUT_PKT_BURST_SIZE_H : integer := 68;
OUT_PKT_BURST_SIZE_L : integer := 66;
OUT_PKT_RESPONSE_STATUS_H : integer := 70;
OUT_PKT_RESPONSE_STATUS_L : integer := 69;
OUT_PKT_TRANS_EXCLUSIVE : integer := 71;
OUT_PKT_BURST_TYPE_H : integer := 73;
OUT_PKT_BURST_TYPE_L : integer := 72;
OUT_ST_DATA_W : integer := 74;
ST_CHANNEL_W : integer := 32;
OPTIMIZE_FOR_RSP : integer := 0;
RESPONSE_PATH : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
in_valid : in std_logic := 'X'; -- valid
in_channel : in std_logic_vector(5 downto 0) := (others => 'X'); -- channel
in_startofpacket : in std_logic := 'X'; -- startofpacket
in_endofpacket : in std_logic := 'X'; -- endofpacket
in_ready : out std_logic; -- ready
in_data : in std_logic_vector(69 downto 0) := (others => 'X'); -- data
out_endofpacket : out std_logic; -- endofpacket
out_data : out std_logic_vector(87 downto 0); -- data
out_channel : out std_logic_vector(5 downto 0); -- channel
out_valid : out std_logic; -- valid
out_ready : in std_logic := 'X'; -- ready
out_startofpacket : out std_logic; -- startofpacket
in_command_size_data : in std_logic_vector(2 downto 0) := (others => 'X') -- data
);
end component altera_merlin_width_adapter;
begin
width_adapter : component altera_merlin_width_adapter
generic map (
IN_PKT_ADDR_H => IN_PKT_ADDR_H,
IN_PKT_ADDR_L => IN_PKT_ADDR_L,
IN_PKT_DATA_H => IN_PKT_DATA_H,
IN_PKT_DATA_L => IN_PKT_DATA_L,
IN_PKT_BYTEEN_H => IN_PKT_BYTEEN_H,
IN_PKT_BYTEEN_L => IN_PKT_BYTEEN_L,
IN_PKT_BYTE_CNT_H => IN_PKT_BYTE_CNT_H,
IN_PKT_BYTE_CNT_L => IN_PKT_BYTE_CNT_L,
IN_PKT_TRANS_COMPRESSED_READ => IN_PKT_TRANS_COMPRESSED_READ,
IN_PKT_BURSTWRAP_H => IN_PKT_BURSTWRAP_H,
IN_PKT_BURSTWRAP_L => IN_PKT_BURSTWRAP_L,
IN_PKT_BURST_SIZE_H => IN_PKT_BURST_SIZE_H,
IN_PKT_BURST_SIZE_L => IN_PKT_BURST_SIZE_L,
IN_PKT_RESPONSE_STATUS_H => IN_PKT_RESPONSE_STATUS_H,
IN_PKT_RESPONSE_STATUS_L => IN_PKT_RESPONSE_STATUS_L,
IN_PKT_TRANS_EXCLUSIVE => IN_PKT_TRANS_EXCLUSIVE,
IN_PKT_BURST_TYPE_H => IN_PKT_BURST_TYPE_H,
IN_PKT_BURST_TYPE_L => IN_PKT_BURST_TYPE_L,
IN_ST_DATA_W => IN_ST_DATA_W,
OUT_PKT_ADDR_H => OUT_PKT_ADDR_H,
OUT_PKT_ADDR_L => OUT_PKT_ADDR_L,
OUT_PKT_DATA_H => OUT_PKT_DATA_H,
OUT_PKT_DATA_L => OUT_PKT_DATA_L,
OUT_PKT_BYTEEN_H => OUT_PKT_BYTEEN_H,
OUT_PKT_BYTEEN_L => OUT_PKT_BYTEEN_L,
OUT_PKT_BYTE_CNT_H => OUT_PKT_BYTE_CNT_H,
OUT_PKT_BYTE_CNT_L => OUT_PKT_BYTE_CNT_L,
OUT_PKT_TRANS_COMPRESSED_READ => OUT_PKT_TRANS_COMPRESSED_READ,
OUT_PKT_BURST_SIZE_H => OUT_PKT_BURST_SIZE_H,
OUT_PKT_BURST_SIZE_L => OUT_PKT_BURST_SIZE_L,
OUT_PKT_RESPONSE_STATUS_H => OUT_PKT_RESPONSE_STATUS_H,
OUT_PKT_RESPONSE_STATUS_L => OUT_PKT_RESPONSE_STATUS_L,
OUT_PKT_TRANS_EXCLUSIVE => OUT_PKT_TRANS_EXCLUSIVE,
OUT_PKT_BURST_TYPE_H => OUT_PKT_BURST_TYPE_H,
OUT_PKT_BURST_TYPE_L => OUT_PKT_BURST_TYPE_L,
OUT_ST_DATA_W => OUT_ST_DATA_W,
ST_CHANNEL_W => ST_CHANNEL_W,
OPTIMIZE_FOR_RSP => OPTIMIZE_FOR_RSP,
RESPONSE_PATH => RESPONSE_PATH
)
port map (
clk => clk, -- clk.clk
reset => reset, -- clk_reset.reset
in_valid => in_valid, -- sink.valid
in_channel => in_channel, -- .channel
in_startofpacket => in_startofpacket, -- .startofpacket
in_endofpacket => in_endofpacket, -- .endofpacket
in_ready => in_ready, -- .ready
in_data => in_data, -- .data
out_endofpacket => out_endofpacket, -- src.endofpacket
out_data => out_data, -- .data
out_channel => out_channel, -- .channel
out_valid => out_valid, -- .valid
out_ready => out_ready, -- .ready
out_startofpacket => out_startofpacket, -- .startofpacket
in_command_size_data => "000" -- (terminated)
);
end architecture rtl; -- of cb20_width_adapter
| apache-2.0 | 0297e367b15a1ec063b9255b6c6dc519 | 0.458581 | 3.372131 | false | false | false | false |
markusC64/1541ultimate2 | fpga/1541/vhdl_source/via6522.vhd | 1 | 27,379 | -------------------------------------------------------------------------------
-- Title : VIA 6522
-------------------------------------------------------------------------------
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This module implements the 6522 VIA chip.
-- A LOT OF REVERSE ENGINEERING has been done to make this module
-- as accurate as it is now. Thanks to gyurco for ironing out some
-- differences that were left unnoticed.
-------------------------------------------------------------------------------
-- License: GPL 3.0 - Free to use, distribute and change to your own needs.
-- Leaving a reference to the author will be highly appreciated.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity via6522 is
port (
clock : in std_logic;
rising : in std_logic;
falling : in std_logic;
reset : in std_logic;
addr : in std_logic_vector(3 downto 0);
wen : in std_logic;
ren : in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
phi2_ref : out std_logic;
-- pio --
port_a_o : out std_logic_vector(7 downto 0);
port_a_t : out std_logic_vector(7 downto 0);
port_a_i : in std_logic_vector(7 downto 0);
port_b_o : out std_logic_vector(7 downto 0);
port_b_t : out std_logic_vector(7 downto 0);
port_b_i : in std_logic_vector(7 downto 0);
-- handshake pins
ca1_i : in std_logic;
ca2_o : out std_logic;
ca2_i : in std_logic;
ca2_t : out std_logic;
cb1_o : out std_logic;
cb1_i : in std_logic;
cb1_t : out std_logic;
cb2_o : out std_logic;
cb2_i : in std_logic;
cb2_t : out std_logic;
irq : out std_logic );
end via6522;
architecture Gideon of via6522 is
type pio_t is
record
pra : std_logic_vector(7 downto 0);
ddra : std_logic_vector(7 downto 0);
prb : std_logic_vector(7 downto 0);
ddrb : std_logic_vector(7 downto 0);
end record;
constant pio_default : pio_t := (others => (others => '0'));
constant latch_reset_pattern : std_logic_vector(15 downto 0) := X"5550";
signal last_data : std_logic_vector(7 downto 0) := X"55";
signal pio_i : pio_t;
signal port_a_c : std_logic_vector(7 downto 0) := (others => '0');
signal port_b_c : std_logic_vector(7 downto 0) := (others => '0');
signal irq_mask : std_logic_vector(6 downto 0) := (others => '0');
signal irq_flags : std_logic_vector(6 downto 0) := (others => '0');
signal irq_events : std_logic_vector(6 downto 0) := (others => '0');
signal irq_out : std_logic;
signal timer_a_latch : std_logic_vector(15 downto 0) := latch_reset_pattern;
signal timer_b_latch : std_logic_vector(15 downto 0) := latch_reset_pattern;
signal timer_a_count : std_logic_vector(15 downto 0) := latch_reset_pattern;
signal timer_b_count : std_logic_vector(15 downto 0) := latch_reset_pattern;
signal timer_a_out : std_logic;
signal timer_b_tick : std_logic;
signal acr, pcr : std_logic_vector(7 downto 0) := X"00";
signal shift_reg : std_logic_vector(7 downto 0) := X"00";
signal serport_en : std_logic;
signal ser_cb2_o : std_logic;
signal hs_cb2_o : std_logic;
signal cb1_t_int : std_logic;
signal cb1_o_int : std_logic;
signal cb2_t_int : std_logic;
signal cb2_o_int : std_logic;
alias ca2_event : std_logic is irq_events(0);
alias ca1_event : std_logic is irq_events(1);
alias serial_event : std_logic is irq_events(2);
alias cb2_event : std_logic is irq_events(3);
alias cb1_event : std_logic is irq_events(4);
alias timer_b_event : std_logic is irq_events(5);
alias timer_a_event : std_logic is irq_events(6);
alias ca2_flag : std_logic is irq_flags(0);
alias ca1_flag : std_logic is irq_flags(1);
alias serial_flag : std_logic is irq_flags(2);
alias cb2_flag : std_logic is irq_flags(3);
alias cb1_flag : std_logic is irq_flags(4);
alias timer_b_flag : std_logic is irq_flags(5);
alias timer_a_flag : std_logic is irq_flags(6);
alias tmr_a_output_en : std_logic is acr(7);
alias tmr_a_freerun : std_logic is acr(6);
alias tmr_b_count_mode : std_logic is acr(5);
alias shift_dir : std_logic is acr(4);
alias shift_clk_sel : std_logic_vector(1 downto 0) is acr(3 downto 2);
alias shift_mode_control : std_logic_vector(2 downto 0) is acr(4 downto 2);
alias pb_latch_en : std_logic is acr(1);
alias pa_latch_en : std_logic is acr(0);
alias cb2_is_output : std_logic is pcr(7);
alias cb2_edge_select : std_logic is pcr(6); -- for when CB2 is input
alias cb2_no_irq_clr : std_logic is pcr(5); -- for when CB2 is input
alias cb2_out_mode : std_logic_vector(1 downto 0) is pcr(6 downto 5);
alias cb1_edge_select : std_logic is pcr(4);
alias ca2_is_output : std_logic is pcr(3);
alias ca2_edge_select : std_logic is pcr(2); -- for when CA2 is input
alias ca2_no_irq_clr : std_logic is pcr(1); -- for when CA2 is input
alias ca2_out_mode : std_logic_vector(1 downto 0) is pcr(2 downto 1);
alias ca1_edge_select : std_logic is pcr(0);
signal ira, irb : std_logic_vector(7 downto 0) := (others => '0');
signal write_t1c_l : std_logic;
signal write_t1c_h : std_logic;
signal write_t2c_h : std_logic;
signal ca1_c, ca2_c : std_logic;
signal cb1_c, cb2_c : std_logic;
signal ca1_d1, ca2_d1 : std_logic;
signal cb1_d1, cb2_d1 : std_logic;
signal ca1_d2, ca2_d2 : std_logic;
signal cb1_d2, cb2_d2 : std_logic;
signal ca2_handshake_o : std_logic;
signal ca2_pulse_o : std_logic;
signal cb2_handshake_o : std_logic;
signal cb2_pulse_o : std_logic;
signal shift_active : std_logic;
begin
irq <= irq_out;
write_t1c_l <= '1' when (addr = X"4" or addr = x"6") and wen='1' and falling = '1' else '0';
write_t1c_h <= '1' when addr = X"5" and wen='1' and falling = '1' else '0';
write_t2c_h <= '1' when addr = X"9" and wen='1' and falling = '1' else '0';
ca1_event <= (ca1_d1 xor ca1_d2) and (ca1_d2 xor ca1_edge_select);
ca2_event <= (ca2_d1 xor ca2_d2) and (ca2_d2 xor ca2_edge_select);
cb1_event <= (cb1_d1 xor cb1_d2) and (cb1_d2 xor cb1_edge_select);
cb2_event <= (cb2_d1 xor cb2_d2) and (cb2_d2 xor cb2_edge_select);
ca2_t <= ca2_is_output;
cb2_t_int <= cb2_is_output when serport_en='0' else shift_dir;
cb2_o_int <= hs_cb2_o when serport_en='0' else ser_cb2_o;
cb1_t <= cb1_t_int;
cb1_o <= cb1_o_int;
cb2_t <= cb2_t_int;
cb2_o <= cb2_o_int;
with ca2_out_mode select ca2_o <=
ca2_handshake_o when "00",
ca2_pulse_o when "01",
'0' when "10",
'1' when others;
with cb2_out_mode select hs_cb2_o <=
cb2_handshake_o when "00",
cb2_pulse_o when "01",
'0' when "10",
'1' when others;
process(irq_flags, irq_mask)
begin
if (irq_flags and irq_mask) = "0000000" then
irq_out <= '0';
else
irq_out <= '1';
end if;
end process;
process(clock)
begin
if rising_edge(clock) then
if rising = '1' then
phi2_ref <= '1';
elsif falling = '1' then
phi2_ref <= '0';
end if;
end if;
end process;
process(clock)
begin
if rising_edge(clock) then
-- CA1/CA2/CB1/CB2 edge detect flipflops
ca1_c <= To_X01(ca1_i);
ca2_c <= To_X01(ca2_i);
cb1_c <= To_X01(cb1_i);
cb2_c <= To_X01(cb2_i);
ca1_d1 <= ca1_c;
ca2_d1 <= ca2_c;
cb1_d1 <= cb1_c;
cb2_d1 <= cb2_c;
ca1_d2 <= ca1_d1;
ca2_d2 <= ca2_d1;
cb1_d2 <= cb1_d1;
cb2_d2 <= cb2_d1;
-- input registers
port_a_c <= port_a_i;
port_b_c <= port_b_i;
-- input latch emulation
if pa_latch_en = '0' or (ca1_event = '1' and ca2_handshake_o = '1') then
ira <= port_a_c;
end if;
if pb_latch_en = '0' or (cb1_event = '1' and cb2_handshake_o = '1') then
irb <= port_b_c;
end if;
-- CA2 logic
if ca1_event = '1' then
ca2_handshake_o <= '0';
elsif (ren = '1' or wen = '1') and addr = X"1" and falling = '1' then
ca2_handshake_o <= '1';
end if;
if falling = '1' then
if (ren = '1' or wen = '1') and addr = X"1" then
ca2_pulse_o <= '0';
else
ca2_pulse_o <= '1';
end if;
end if;
-- CB2 logic
if cb1_event = '1' then
cb2_handshake_o <= '0';
elsif (ren = '1' or wen = '1') and addr = X"0" and falling = '1' then
cb2_handshake_o <= '1';
end if;
if falling = '1' then
if (ren = '1' or wen = '1') and addr = X"0" then
cb2_pulse_o <= '0';
else
cb2_pulse_o <= '1';
end if;
end if;
-- Interrupt logic
irq_flags <= irq_flags or irq_events;
-- Writes --
if wen='1' and falling = '1' then
last_data <= data_in;
case addr is
when X"0" => -- ORB
pio_i.prb <= data_in;
if cb2_no_irq_clr='0' then
cb2_flag <= '0';
end if;
cb1_flag <= '0';
when X"1" => -- ORA
pio_i.pra <= data_in;
if ca2_no_irq_clr='0' then
ca2_flag <= '0';
end if;
ca1_flag <= '0';
when X"2" => -- DDRB
pio_i.ddrb <= data_in;
when X"3" => -- DDRA
pio_i.ddra <= data_in;
when X"4" => -- TA LO counter (write=latch)
timer_a_latch(7 downto 0) <= data_in;
when X"5" => -- TA HI counter
timer_a_latch(15 downto 8) <= data_in;
timer_a_flag <= '0';
when X"6" => -- TA LO latch
timer_a_latch(7 downto 0) <= data_in;
when X"7" => -- TA HI latch
timer_a_latch(15 downto 8) <= data_in;
timer_a_flag <= '0';
when X"8" => -- TB LO latch
timer_b_latch(7 downto 0) <= data_in;
when X"9" => -- TB HI counter
timer_b_flag <= '0';
when X"A" => -- Serial port
serial_flag <= '0';
when X"B" => -- ACR (Auxiliary Control Register)
acr <= data_in;
when X"C" => -- PCR (Peripheral Control Register)
pcr <= data_in;
when X"D" => -- IFR
irq_flags <= irq_flags and not data_in(6 downto 0);
when X"E" => -- IER
if data_in(7)='1' then -- set
irq_mask <= irq_mask or data_in(6 downto 0);
else -- clear
irq_mask <= irq_mask and not data_in(6 downto 0);
end if;
when X"F" => -- ORA no handshake
pio_i.pra <= data_in;
when others =>
null;
end case;
end if;
-- Reads - Output only --
data_out <= X"00";
case addr is
when X"0" => -- ORB
--Port B reads its own output register for pins set to output.
data_out <= (pio_i.prb and pio_i.ddrb) or (irb and not pio_i.ddrb);
if tmr_a_output_en='1' then
data_out(7) <= timer_a_out;
end if;
when X"1" => -- ORA
data_out <= ira;
when X"2" => -- DDRB
data_out <= pio_i.ddrb;
when X"3" => -- DDRA
data_out <= pio_i.ddra;
when X"4" => -- TA LO counter
data_out <= timer_a_count(7 downto 0);
when X"5" => -- TA HI counter
data_out <= timer_a_count(15 downto 8);
when X"6" => -- TA LO latch
data_out <= timer_a_latch(7 downto 0);
when X"7" => -- TA HI latch
data_out <= timer_a_latch(15 downto 8);
when X"8" => -- TA LO counter
data_out <= timer_b_count(7 downto 0);
when X"9" => -- TA HI counter
data_out <= timer_b_count(15 downto 8);
when X"A" => -- SR
data_out <= shift_reg;
when X"B" => -- ACR
data_out <= acr;
when X"C" => -- PCR
data_out <= pcr;
when X"D" => -- IFR
data_out <= irq_out & irq_flags;
when X"E" => -- IER
data_out <= '0' & irq_mask;
when X"F" => -- ORA
data_out <= ira;
when others =>
null;
end case;
-- Read actions --
if ren = '1' and falling = '1' then
case addr is
when X"0" => -- ORB
if cb2_no_irq_clr='0' then
cb2_flag <= '0';
end if;
cb1_flag <= '0';
when X"1" => -- ORA
if ca2_no_irq_clr='0' then
ca2_flag <= '0';
end if;
ca1_flag <= '0';
when X"4" => -- TA LO counter
timer_a_flag <= '0';
when X"8" => -- TB LO counter
timer_b_flag <= '0';
when X"A" => -- SR
serial_flag <= '0';
when others =>
null;
end case;
end if;
if reset='1' then
-- Reset avoids packing into shift register
ca1_c <= '1';
ca2_c <= '1';
cb1_c <= '1';
cb2_c <= '1';
ca1_d1 <= '1';
ca2_d1 <= '1';
cb1_d1 <= '1';
cb2_d1 <= '1';
ca1_d2 <= '1';
ca2_d2 <= '1';
cb1_d2 <= '1';
cb2_d2 <= '1';
pio_i <= pio_default;
irq_mask <= (others => '0');
irq_flags <= (others => '0');
acr <= (others => '0');
pcr <= (others => '0');
ca2_handshake_o <= '1';
ca2_pulse_o <= '1';
cb2_handshake_o <= '1';
cb2_pulse_o <= '1';
timer_a_latch <= latch_reset_pattern;
timer_b_latch <= latch_reset_pattern;
end if;
end if;
end process;
-- PIO Out select --
port_a_o <= pio_i.pra;
port_b_o(6 downto 0) <= pio_i.prb(6 downto 0);
port_b_o(7) <= pio_i.prb(7) when tmr_a_output_en='0' else timer_a_out;
port_a_t <= pio_i.ddra;
port_b_t(6 downto 0) <= pio_i.ddrb(6 downto 0);
port_b_t(7) <= pio_i.ddrb(7) or tmr_a_output_en;
-- Timer A
tmr_a: block
signal timer_a_reload : std_logic;
signal timer_a_toggle : std_logic;
signal timer_a_may_interrupt : std_logic;
begin
process(clock)
begin
if rising_edge(clock) then
if falling = '1' then
-- always count, or load
if timer_a_reload = '1' then
timer_a_count <= timer_a_latch;
if write_t1c_l = '1' then
timer_a_count(7 downto 0) <= data_in;
end if;
timer_a_reload <= '0';
timer_a_may_interrupt <= timer_a_may_interrupt and tmr_a_freerun;
else
if timer_a_count = X"0000" then
-- generate an event if we were triggered
timer_a_reload <= '1';
end if;
--Timer coutinues to count in both free run and one shot.
timer_a_count <= timer_a_count - X"0001";
end if;
end if;
if rising = '1' then
if timer_a_event = '1' and tmr_a_output_en = '1' then
timer_a_toggle <= not timer_a_toggle;
end if;
end if;
if write_t1c_h = '1' then
timer_a_may_interrupt <= '1';
timer_a_toggle <= not tmr_a_output_en;
timer_a_count <= data_in & timer_a_latch(7 downto 0);
timer_a_reload <= '0';
end if;
if reset='1' then
timer_a_may_interrupt <= '0';
timer_a_toggle <= '1';
timer_a_count <= latch_reset_pattern;
timer_a_reload <= '0';
end if;
end if;
end process;
timer_a_out <= timer_a_toggle;
timer_a_event <= rising and timer_a_reload and timer_a_may_interrupt;
end block tmr_a;
-- Timer B
tmr_b: block
signal timer_b_reload_lo : std_logic;
signal timer_b_oneshot_trig : std_logic;
signal timer_b_timeout : std_logic;
signal pb6_c, pb6_d : std_logic;
begin
process(clock)
variable timer_b_decrement : std_logic;
begin
if rising_edge(clock) then
timer_b_decrement := '0';
if rising = '1' then
pb6_c <= To_X01(port_b_i(6));
pb6_d <= pb6_c;
end if;
if falling = '1' then
timer_b_timeout <= '0';
timer_b_tick <= '0';
if tmr_b_count_mode = '1' then
if (pb6_d='1' and pb6_c='0') then
timer_b_decrement := '1';
end if;
else -- one shot or used for shift register
timer_b_decrement := '1';
end if;
if timer_b_decrement = '1' then
if timer_b_count = X"0000" then
if timer_b_oneshot_trig = '1' then
timer_b_oneshot_trig <= '0';
timer_b_timeout <= '1';
end if;
end if;
if timer_b_count(7 downto 0) = X"00" then
case shift_mode_control is
when "001" | "101" | "100" =>
timer_b_reload_lo <= '1';
timer_b_tick <= '1';
when others =>
null;
end case;
end if;
timer_b_count <= timer_b_count - X"0001";
end if;
if timer_b_reload_lo = '1' then
timer_b_count(7 downto 0) <= timer_b_latch(7 downto 0);
timer_b_reload_lo <= '0';
end if;
end if;
if write_t2c_h = '1' then
timer_b_count <= data_in & timer_b_latch(7 downto 0);
timer_b_oneshot_trig <= '1';
end if;
if reset='1' then
timer_b_count <= latch_reset_pattern;
timer_b_reload_lo <= '0';
timer_b_oneshot_trig <= '0';
end if;
end if;
end process;
timer_b_event <= rising and timer_b_timeout;
end block tmr_b;
ser: block
signal trigger_serial: std_logic;
signal shift_clock_d : std_logic;
signal shift_clock : std_logic;
signal shift_tick_r : std_logic;
signal shift_tick_f : std_logic;
signal shift_timer_tick : std_logic;
signal bit_cnt : integer range 0 to 7;
signal shift_pulse : std_logic;
begin
process(shift_active, timer_b_tick, shift_clk_sel, shift_clock, shift_clock_d, shift_timer_tick)
begin
case shift_clk_sel is
when "10" =>
shift_pulse <= '1';
when "00"|"01" =>
shift_pulse <= shift_timer_tick;
when others =>
shift_pulse <= shift_clock and not shift_clock_d;
end case;
if shift_active = '0' then
-- Mode 0 still loads the shift register to external pulse (MMBEEB SD-Card interface uses this)
if shift_mode_control = "000" then
shift_pulse <= shift_clock and not shift_clock_d;
else
shift_pulse <= '0';
end if;
end if;
end process;
process(clock)
begin
if rising_edge(clock) then
if rising = '1' then
if shift_active='0' then
if shift_mode_control = "000" then
shift_clock <= cb1_d1;
else
shift_clock <= '1';
end if;
elsif shift_clk_sel = "11" then
shift_clock <= cb1_d1;
elsif shift_pulse = '1' then
shift_clock <= not shift_clock;
end if;
shift_clock_d <= shift_clock;
end if;
if falling = '1' then
shift_timer_tick <= timer_b_tick;
end if;
if reset = '1' then
shift_clock <= '1';
shift_clock_d <= '1';
end if;
end if;
end process;
cb1_t_int <= '0' when shift_clk_sel="11" else serport_en;
cb1_o_int <= shift_clock_d;
ser_cb2_o <= shift_reg(7);
serport_en <= shift_dir or shift_clk_sel(1) or shift_clk_sel(0);
trigger_serial <= '1' when (ren='1' or wen='1') and addr=x"A" else '0';
shift_tick_r <= not shift_clock_d and shift_clock;
shift_tick_f <= shift_clock_d and not shift_clock;
process(clock)
begin
if rising_edge(clock) then
if reset = '1' then
shift_reg <= X"FF";
elsif falling = '1' then
if wen = '1' and addr = X"A" then
shift_reg <= data_in;
elsif shift_dir='1' and shift_tick_f = '1' then -- output
shift_reg <= shift_reg(6 downto 0) & shift_reg(7);
elsif shift_dir='0' and shift_tick_r = '1' then -- input
shift_reg <= shift_reg(6 downto 0) & cb2_d1;
end if;
end if;
end if;
end process;
-- tell people that we're ready!
serial_event <= shift_tick_r and not shift_active and rising and serport_en;
process(clock)
begin
if rising_edge(clock) then
if falling = '1' then
if shift_active = '0' and shift_mode_control /= "000" then
if trigger_serial = '1' then
bit_cnt <= 7;
shift_active <= '1';
end if;
else -- we're active
if shift_clk_sel = "00" then
shift_active <= shift_dir; -- when '1' we're active, but for mode 000 we go inactive.
elsif shift_pulse = '1' and shift_clock = '1' then
if bit_cnt = 0 then
shift_active <= '0';
else
bit_cnt <= bit_cnt - 1;
end if;
end if;
end if;
end if;
if reset='1' then
shift_active <= '0';
bit_cnt <= 0;
end if;
end if;
end process;
end block ser;
end Gideon;
| gpl-3.0 | 1795982725c002d2a0bbf6ebcf465e1b | 0.404726 | 3.882995 | false | false | false | false |
markusC64/1541ultimate2 | fpga/sid6581/vhdl_source/sid_regs.vhd | 1 | 11,560 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
--
-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
--
-- Note that this file is copyrighted, and is not supposed to be used in other
-- projects without written permission from the author.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sid_regs is
generic (
g_8voices : boolean := false );
port (
clock : in std_logic;
reset : in std_logic;
addr : in unsigned(7 downto 0);
wren : in std_logic;
wdata : in std_logic_vector(7 downto 0);
rdata : out std_logic_vector(7 downto 0);
---
comb_wave_l : in std_logic;
comb_wave_r : in std_logic;
---
voice_osc : in unsigned(3 downto 0);
voice_wave : in unsigned(3 downto 0);
voice_adsr : in unsigned(3 downto 0);
voice_mul : in unsigned(3 downto 0);
-- Oscillator parameters
freq : out unsigned(15 downto 0);
test : out std_logic;
sync : out std_logic;
-- Wave map parameters
comb_mode : out std_logic;
ring_mod : out std_logic;
wave_sel : out std_logic_vector(3 downto 0);
sq_width : out unsigned(11 downto 0);
-- ADSR parameters
gate : out std_logic;
attack : out std_logic_vector(3 downto 0);
decay : out std_logic_vector(3 downto 0);
sustain : out std_logic_vector(3 downto 0);
release : out std_logic_vector(3 downto 0);
-- mixer 1 parameters
filter_en : out std_logic;
-- globals
volume_l : out unsigned(3 downto 0) := (others => '0');
filter_co_l : out unsigned(10 downto 0) := (others => '0');
filter_res_l : out unsigned(3 downto 0) := (others => '0');
filter_ex_l : out std_logic := '0';
filter_hp_l : out std_logic := '0';
filter_bp_l : out std_logic := '0';
filter_lp_l : out std_logic := '0';
voice3_off_l : out std_logic := '0';
volume_r : out unsigned(3 downto 0) := (others => '0');
filter_co_r : out unsigned(10 downto 0) := (others => '0');
filter_res_r : out unsigned(3 downto 0) := (others => '0');
filter_ex_r : out std_logic := '0';
filter_hp_r : out std_logic := '0';
filter_bp_r : out std_logic := '0';
filter_lp_r : out std_logic := '0';
voice3_off_r : out std_logic := '0';
-- readback
osc3 : in std_logic_vector(7 downto 0);
env3 : in std_logic_vector(7 downto 0) );
attribute keep_hierarchy : string;
attribute keep_hierarchy of sid_regs : entity is "yes";
end sid_regs;
architecture gideon of sid_regs is
type byte_array_t is array(natural range <>) of std_logic_vector(7 downto 0);
type nibble_array_t is array(natural range <>) of std_logic_vector(3 downto 0);
signal freq_lo : byte_array_t(0 to 15) := (others => (others => '0'));
signal freq_hi : byte_array_t(0 to 15) := (others => (others => '0'));
signal phase_lo : byte_array_t(0 to 15) := (others => (others => '0'));
signal phase_hi : nibble_array_t(0 to 15):= (others => (others => '0'));
signal control : byte_array_t(0 to 15) := (others => (others => '0'));
signal att_dec : byte_array_t(0 to 15) := (others => (others => '0'));
signal sust_rel : byte_array_t(0 to 15) := (others => (others => '0'));
signal do_write : std_logic;
signal wdata_d : std_logic_vector(7 downto 0);
signal filt_en_i: std_logic_vector(15 downto 0) := (others => '0');
constant address_remap : byte_array_t(0 to 255) := (
X"00", X"01", X"02", X"03", X"04", X"05", X"06", -- 00 Voice 1
X"10", X"11", X"12", X"13", X"14", X"15", X"16", -- 07 Voice 2
X"20", X"21", X"22", X"23", X"24", X"25", X"26", -- 0E Voice 3
X"08", X"09", X"0A", X"0B", -- 15
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- 19
X"30", X"31", X"32", X"33", X"34", X"35", X"36", -- 20 Voice 4
X"40", X"41", X"42", X"43", X"44", X"45", X"46", -- 27 Voice 5
X"50", X"51", X"52", X"53", X"54", X"55", X"56", -- 2E Voice 6
X"60", X"61", X"62", X"63", X"64", X"65", X"66", -- 35 Voice 7
X"70", X"71", X"72", X"73", X"74", X"75", X"76", -- 3C Voice 8
X"0C", X"0D", X"0E", -- 43
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- 46
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- 4D
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- 54
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- 5B
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- 62
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- 69
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- 70
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- 77
X"FF", X"FF", -- 7E
X"80", X"81", X"82", X"83", X"84", X"85", X"86", -- 80 Voice 9
X"90", X"91", X"92", X"93", X"94", X"95", X"96", -- 87 Voice 10
X"A0", X"A1", X"A2", X"A3", X"A4", X"A5", X"A6", -- 8E Voice 11
X"88", X"89", X"8A", X"8B", -- 95
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- 99
X"B0", X"B1", X"B2", X"B3", X"B4", X"B5", X"B6", -- A0 Voice 12
X"C0", X"C1", X"C2", X"C3", X"C4", X"C5", X"C6", -- A7 Voice 13
X"D0", X"D1", X"D2", X"D3", X"D4", X"D5", X"D6", -- AE Voice 14
X"E0", X"E1", X"E2", X"E3", X"E4", X"E5", X"E6", -- B5 Voice 15
X"F0", X"F1", X"F2", X"F3", X"F4", X"F5", X"F6", -- BC Voice 16
X"8C", X"8D", X"8E", -- C3
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- C6
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- CD
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- D4
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- DB
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- E2
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- E9
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- F0
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- F7
X"FF", X"FF" ); -- FE
signal address : unsigned(7 downto 0);
begin
process(clock)
begin
if rising_edge(clock) then
address <= unsigned(address_remap(to_integer(addr)));
do_write <= wren;
wdata_d <= wdata;
if do_write='1' then
if address(3)='0' then -- Voice register
case address(2 downto 0) is
when "000" => freq_lo(to_integer(address(7 downto 4))) <= wdata_d;
when "001" => freq_hi(to_integer(address(7 downto 4))) <= wdata_d;
when "010" => phase_lo(to_integer(address(7 downto 4))) <= wdata_d;
when "011" => phase_hi(to_integer(address(7 downto 4))) <= wdata_d(3 downto 0);
when "100" => control(to_integer(address(7 downto 4))) <= wdata_d;
when "101" => att_dec(to_integer(address(7 downto 4))) <= wdata_d;
when "110" => sust_rel(to_integer(address(7 downto 4))) <= wdata_d;
when others => null;
end case;
elsif address(7)='0' then -- Global register for left
case address(2 downto 0) is
when "000" => filter_co_l(2 downto 0) <= unsigned(wdata_d(2 downto 0));
when "001" => filter_co_l(10 downto 3) <= unsigned(wdata_d);
when "010" => filter_res_l <= unsigned(wdata_d(7 downto 4));
filter_ex_l <= wdata_d(3);
filt_en_i(2 downto 0) <= wdata_d(2 downto 0);
when "011" => voice3_off_l <= wdata_d(7);
filter_hp_l <= wdata_d(6);
filter_bp_l <= wdata_d(5);
filter_lp_l <= wdata_d(4);
volume_l <= unsigned(wdata_d(3 downto 0));
when "100" => if g_8voices then filt_en_i(7 downto 0) <= wdata_d; end if;
when others => null;
end case;
else -- Global register for right
case address(2 downto 0) is
when "000" => filter_co_r(2 downto 0) <= unsigned(wdata_d(2 downto 0));
when "001" => filter_co_r(10 downto 3) <= unsigned(wdata_d);
when "010" => filter_res_r <= unsigned(wdata_d(7 downto 4));
filter_ex_r <= wdata_d(3);
filt_en_i(10 downto 8) <= wdata_d(2 downto 0);
when "011" => voice3_off_r <= wdata_d(7);
filter_hp_r <= wdata_d(6);
filter_bp_r <= wdata_d(5);
filter_lp_r <= wdata_d(4);
volume_r <= unsigned(wdata_d(3 downto 0));
when "100" => if g_8voices then filt_en_i(15 downto 8) <= wdata_d; end if;
when others => null;
end case;
end if;
end if;
-- Readback (unmapped address)
case addr is
when "00011011" => rdata <= osc3;
when "00011100" => rdata <= env3;
when others => rdata <= (others => '0');
end case;
if reset='1' then
filt_en_i <= (others => '0');
voice3_off_l <= '0';
voice3_off_r <= '0';
volume_l <= X"0";
volume_r <= X"0";
end if;
end if;
end process;
freq <= unsigned(freq_hi(to_integer(voice_osc))) & unsigned(freq_lo(to_integer(voice_osc)));
test <= control(to_integer(voice_osc))(3);
sync <= control(to_integer(voice_osc))(1);
-- Wave map parameters
ring_mod <= control(to_integer(voice_wave))(2);
wave_sel <= control(to_integer(voice_wave))(7 downto 4);
sq_width <= unsigned(phase_hi(to_integer(voice_wave))) & unsigned(phase_lo(to_integer(voice_wave)));
comb_mode <= (voice_wave(3) and comb_wave_r) or (not voice_wave(3) and comb_wave_l);
-- ADSR parameters
gate <= control(to_integer(voice_adsr))(0);
attack <= att_dec(to_integer(voice_adsr))(7 downto 4);
decay <= att_dec(to_integer(voice_adsr))(3 downto 0);
sustain <= sust_rel(to_integer(voice_adsr))(7 downto 4);
release <= sust_rel(to_integer(voice_adsr))(3 downto 0);
-- Mixer 1 parameters
filter_en <= filt_en_i(to_integer(voice_mul));
end gideon;
| gpl-3.0 | c65459c65d249c757610eeaf56833e5e | 0.44455 | 3.155883 | false | false | false | false |
trondd/mkjpeg | design/quantizer/s_divider.vhd | 2 | 6,676 | --------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006-2009 --
-- --
--------------------------------------------------------------------------------
-- --
-- Title : DIVIDER --
-- Design : Signed Pipelined Divider core --
-- Author : Michal Krepa --
-- --
--------------------------------------------------------------------------------
-- --
-- File : S_DIVIDER.VHD --
-- Created : Sat Aug 26 2006 --
-- Modified : Thu Mar 12 2009 --
-- --
--------------------------------------------------------------------------------
-- --
-- Description : Signed Pipelined Divider --
-- --
-- dividend allowable range of -2**SIZE_C to 2**SIZE_C-1 [SIGNED number] --
-- divisor allowable range of 1 to (2**SIZE_C)/2-1 [UNSIGNED number] --
-- pipeline latency is 2*SIZE_C+2 (time from latching input to result ready) --
-- when pipeline is full new result is generated every clock cycle --
-- Non-Restoring division algorithm --
-- Use SIZE_C constant in divider entity to adjust bit width --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- MAIN DIVIDER top level
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.All;
use IEEE.NUMERIC_STD.all;
entity s_divider is
generic
(
SIZE_C : INTEGER := 32
) ; -- SIZE_C: Number of bits
port
(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
a : in STD_LOGIC_VECTOR(SIZE_C-1 downto 0) ;
d : in STD_LOGIC_VECTOR(SIZE_C-1 downto 0) ;
q : out STD_LOGIC_VECTOR(SIZE_C-1 downto 0) ;
r : out STD_LOGIC_VECTOR(SIZE_C-1 downto 0) ;
round : out STD_LOGIC
) ;
end s_divider ;
architecture str of s_divider is
type S_ARRAY is array(0 to SIZE_C+3) of unsigned(SIZE_C-1 downto 0);
type S2_ARRAY is array(0 to SIZE_C+1) of unsigned(2*SIZE_C-1 downto 0);
signal d_s : S_ARRAY;
signal q_s : S_ARRAY;
signal r_s : S2_ARRAY;
signal diff : S_ARRAY;
signal qu_s : STD_LOGIC_VECTOR(SIZE_C-1 downto 0);
signal ru_s : unsigned(SIZE_C-1 downto 0);
signal qu_s2 : STD_LOGIC_VECTOR(SIZE_C-1 downto 0);
signal ru_s2 : unsigned(SIZE_C-1 downto 0);
signal d_reg : STD_LOGIC_VECTOR(SIZE_C-1 downto 0);
signal pipeline_reg : STD_LOGIC_VECTOR(SIZE_C+3-1 downto 0);
signal r_reg : STD_LOGIC_VECTOR(SIZE_C-1 downto 0);
begin
pipeline : process(clk,rst)
begin
if rst = '1' then
for k in 0 to SIZE_C loop
r_s(k) <= (others => '0');
q_s(k) <= (others => '0');
d_s(k) <= (others => '0');
end loop;
pipeline_reg <= (others => '0');
elsif clk = '1' and clk'event then
-- negative number
if a(SIZE_C-1) = '1' then
-- negate negative number to create positive
r_s(0) <= unsigned(resize(unsigned(not(SIGNED(a)) + TO_SIGNED(1,SIZE_C)),2*SIZE_C));
-- left shift
pipeline_reg <= pipeline_reg(pipeline_reg'high-1 downto 0) & '1';
else
r_s(0) <= resize(unsigned(a),2*SIZE_C);
-- left shift
pipeline_reg <= pipeline_reg(pipeline_reg'high-1 downto 0) & '0';
end if;
d_s(0) <= unsigned(d);
q_s(0) <= (others => '0');
-- pipeline
for k in 0 to SIZE_C loop
-- test remainder if positive/negative
if r_s(k)(2*SIZE_C-1) = '0' then
-- shift r_tmp one bit left and subtract d_tmp from upper part of r_tmp
r_s(k+1)(2*SIZE_C-1 downto SIZE_C) <= r_s(k)(2*SIZE_C-2 downto SIZE_C-1) - d_s(k);
else
r_s(k+1)(2*SIZE_C-1 downto SIZE_C) <= r_s(k)(2*SIZE_C-2 downto SIZE_C-1) + d_s(k);
end if;
-- shift r_tmp one bit left (lower part)
r_s(k+1)(SIZE_C-1 downto 0) <= r_s(k)(SIZE_C-2 downto 0) & '0';
if diff(k)(SIZE_C-1) = '0' then
q_s(k+1) <= q_s(k)(SIZE_C-2 downto 0) & '1';
else
q_s(k+1) <= q_s(k)(SIZE_C-2 downto 0) & '0';
end if;
d_s(k+1) <= d_s(k);
end loop;
end if;
end process;
G_DIFF: for x in 0 to SIZE_C generate
diff(x) <= r_s(x)(2*SIZE_C-2 downto SIZE_C-1) - d_s(x) when r_s(x)(2*SIZE_C-1) = '0'
else r_s(x)(2*SIZE_C-2 downto SIZE_C-1) + d_s(x);
end generate G_DIFF;
qu_s <= STD_LOGIC_VECTOR( q_s(SIZE_C) );
ru_s <= r_s(SIZE_C)(2*SIZE_C-1 downto SIZE_C);
process(clk,rst)
begin
if rst = '1' then
q <= (others => '0');
r_reg <= (others => '0');
round <= '0';
elsif clk = '1' and clk'event then
if ru_s(SIZE_C-1) = '0' then
ru_s2 <= (ru_s);
else
ru_s2 <= (unsigned(ru_s) + d_s(SIZE_C));
end if;
qu_s2 <= qu_s;
-- negative number
if pipeline_reg(SIZE_C+1) = '1' then
-- negate positive number to create negative
q <= STD_LOGIC_VECTOR(not(SIGNED(qu_s2)) + TO_SIGNED(1,SIZE_C));
r_reg <= STD_LOGIC_VECTOR(not(SIGNED(ru_s2)) + TO_SIGNED(1,SIZE_C));
else
q <= STD_LOGIC_VECTOR(qu_s2);
r_reg <= STD_LOGIC_VECTOR(ru_s2);
end if;
-- if 2*remainder >= divisor then add 1 to round to nearest integer
if (ru_s2(SIZE_C-2 downto 0) & '0') >= d_s(SIZE_C+1) then
round <= '1';
else
round <= '0';
end if;
end if;
end process;
-- remainder
r <= r_reg;
end str;
| lgpl-3.0 | 6a9a5f99cfbe0c8404783fef0d3545e3 | 0.40024 | 3.748456 | false | false | false | false |
vzh/geda-gaf | utils/netlist/examples/vams/vhdl/basic-vhdl/bjt_transistor_simple.vhdl | 15 | 910 | LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY BJT_transistor_simple IS
GENERIC ( VT : REAL := 25.85e-3;
AF : REAL := 1.0;
KF : REAL := 0.0;
PT : REAL := 3.0;
EG : REAL := 1.11;
MC : REAL := 0.5;
PC : REAL := 1.0;
CJC : REAL := 2.5e-12;
ME : REAL := 0.5;
PE : REAL := 1.0;
CJE : REAL := 2.5e-12;
CCS : REAL := 2.5e-12;
TR : REAL := 4.0e-9;
TF : REAL := 4.0e-9;
NCL : REAL := 2.0;
C4 : REAL := 0.0;
NEL : REAL := 2.0;
C2 : REAL := 0.0;
RS : REAL := 1.0;
RE : REAL := 1.0;
RC : REAL := 1.0;
RB : REAL := 1.0;
ISS : REAL := 10.0e-14;
BR : REAL := 1.0;
BF : REAL := 100.0 );
PORT ( terminal Emitter : electrical;
terminal Collector : electrical;
terminal Base : electrical );
END ENTITY BJT_transistor_simple;
| gpl-2.0 | 1b05c5c2bf749e4f6bc3fcd19b258947 | 0.528571 | 2.345361 | false | false | false | false |
markusC64/1541ultimate2 | fpga/sid6581/vhdl_source/sid_filter.vhd | 1 | 13,356 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
--
-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
--
-- Note that this file is copyrighted, and is not supposed to be used in other
-- projects without written permission from the author.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.my_math_pkg.all;
use work.io_bus_pkg.all;
library unisim;
use unisim.vcomponents.all;
entity sid_filter is
port (
clock : in std_logic;
reset : in std_logic;
io_req : in t_io_req := c_io_req_init;
io_resp : out t_io_resp;
filt_co : in unsigned(10 downto 0);
filt_res : in unsigned(3 downto 0);
valid_in : in std_logic := '0';
error_out : out std_logic;
input : in signed(17 downto 0);
high_pass : out signed(17 downto 0);
band_pass : out signed(17 downto 0);
low_pass : out signed(17 downto 0);
valid_out : out std_logic );
end entity;
architecture dsvf of sid_filter is
signal filter_q : signed(17 downto 0);
signal filter_f : signed(17 downto 0);
signal input_sc : signed(21 downto 0);
signal filt_ram : std_logic_vector(15 downto 0);
signal xa : signed(17 downto 0);
signal xb : signed(17 downto 0);
signal sum_b : signed(21 downto 0);
signal sub_a : signed(21 downto 0);
signal sub_b : signed(21 downto 0);
signal x_reg : signed(21 downto 0) := (others => '0');
signal bp_reg : signed(21 downto 0);
signal hp_reg : signed(21 downto 0);
signal lp_reg : signed(21 downto 0);
signal temp_reg : signed(21 downto 0);
signal error : std_logic := '0';
signal program_counter : integer range 0 to 15;
signal instruction : std_logic_vector(7 downto 0);
type t_byte_array is array(natural range <>) of std_logic_vector(7 downto 0);
alias xa_select : std_logic is instruction(0);
alias xb_select : std_logic is instruction(1);
alias sub_a_sel : std_logic is instruction(2);
alias sub_b_sel : std_logic is instruction(3);
alias sum_to_lp : std_logic is instruction(4);
alias sum_to_bp : std_logic is instruction(5);
alias sub_to_hp : std_logic is instruction(6);
alias mult_enable : std_logic is instruction(7);
-- operations to execute the filter:
-- bp_f = f * bp_reg
-- q_contrib = q * bp_reg
-- lp = bp_f + lp_reg
-- temp = input - lp
-- hp = temp - q_contrib
-- hp_f = f * hp
-- bp = hp_f + bp_reg
-- bp_reg = bp
-- lp_reg = lp
-- x_reg = f * bp_reg -- 10000000 -- 80
-- lp_reg = x_reg + lp_reg -- 00010010 -- 12
-- q_contrib = q * bp_reg -- 10000001 -- 81
-- temp = input - lp -- 00000000 -- 00 (can be merged with previous!)
-- hp_reg = temp - q_contrib -- 01001100 -- 4C
-- x_reg = f * hp_reg -- 10000010 -- 82
-- bp_reg = x_reg + bp_reg -- 00100000 -- 20
constant c_program : t_byte_array := (X"80", X"12", X"81", X"4C", X"82", X"20");
signal io_rdata : std_logic_vector(7 downto 0);
signal io_coef_en : std_logic;
signal io_coef_en_d : std_logic;
begin
-- Derive the actual 'f' and 'q' parameters
i_q_table: entity work.Q_table
port map (
Q_reg => filt_res,
filter_q => filter_q ); -- 2.16 format
-- I prefer to infer ram than to instantiate a vendor specific
-- block, but this is the fastest, as the sizes of the ports differ.
-- Secondly, a nice init value can be given, for as long as we don't connect
-- the IO bus.
i_filt_coef: RAMB16_S9_S18
generic map (
INIT_00 => X"0329032803280327032703260326032503240324032303230322032203210320",
INIT_01 => X"03320332033103300330032f032f032e032e032d032c032c032b032b032a032a",
INIT_02 => X"033b033b033a033a033903380338033703370336033603350334033403330333",
INIT_03 => X"034403440343034303420341034103400340033f033f033e033e033d033c033c",
INIT_04 => X"035603550354035303510350034f034e034d034c034b03490348034703460345",
INIT_05 => X"03680367036603650364036203610360035f035e035d035c035b035903580357",
INIT_06 => X"037a037903780377037603750374037203710370036f036e036d036c036a0369",
INIT_07 => X"038d038b038a038903880387038603850383038203810380037f037e037d037c",
INIT_08 => X"03b803b603b303b003ad03aa03a703a403a2039f039c0399039603930391038e",
INIT_09 => X"03e603e303e003dd03db03d803d503d203cf03cc03c903c703c403c103be03bb",
INIT_0A => X"04130411040e040b04080405040203ff03fd03fa03f703f403f103ee03ec03e9",
INIT_0B => X"0441043e043b0438043604330430042d042a042704240422041f041c04190416",
INIT_0C => X"04aa04a3049d0496048f04880481047a0474046d0466045f04580451044b0444",
INIT_0D => X"05170511050a050304fc04f504ee04e804e104da04d304cc04c504bf04b804b1",
INIT_0E => X"0585057e0577057005690562055c0555054e05470540053a0533052c0525051e",
INIT_0F => X"05f205eb05e405dd05d705d005c905c205bb05b405ae05a705a005990592058b",
INIT_10 => X"072c0717070306ee06da06c506b1069d06880674065f064b06360622060d05f9",
INIT_11 => X"0874085f084b08360822080d07f907e407d007bb07a70792077e076907550740",
INIT_12 => X"09bb09a70992097e096909550940092c0917090308ee08da08c508b1089c0888",
INIT_13 => X"0b030aee0ada0ac50ab10a9c0a880a740a5f0a4b0a360a220a0d09f909e409d0",
INIT_14 => X"0dd30da40d760d470d190cea0cbb0c8d0c5e0c2f0c010bd20ba30b750b460b17",
INIT_15 => X"10bd108f1060103210030fd40fa60f770f480f1a0eeb0ebc0e8e0e5f0e300e02",
INIT_16 => X"13a81379134b131c12ed12bf129012611233120411d511a711781149111b10ec",
INIT_17 => X"169216641635160615d815a9157a154c151d14ee14c0149114621434140513d7",
INIT_18 => X"1b6c1b1c1acc1a7d1a2d19dd198e193e18ee189f184f17ff17b01760171116c1",
INIT_19 => X"206620161fc71f771f271ed81e881e381de91d991d491cfa1caa1c5a1c0b1bbb",
INIT_1A => X"26b5264f25e92582251c24b5244f23e92382231c22b5224f21e92182211c20b5",
INIT_1B => X"2d1c2cb52c4f2be92b822b1c2ab52a4f29e92982291c28b5284f27e92782271c",
INIT_1C => X"34d8345a33dd336032e3326631e9316b30ee30712ff42f772efa2e7d2dff2d82",
INIT_1D => X"3caa3c2d3bb03b333ab53a3839bb393e38c1384437c7374936cc364f35d23555",
INIT_1E => X"467d45dd453e449f43ff436042c14222418240e340443fa43f053e663dc63d27",
INIT_1F => X"54b95381524851104fff4eee4ddd4ccc4c164b604aaa49f4493e488847d2471c",
INIT_20 => X"4ac84a3149994901486a47d2473a46a2460b457344db4444438e42d84222416b",
INIT_21 => X"54b55416537752d85238519950fa505a4fbb4f1c4e7d4ddd4d3e4c9f4bff4b60",
INIT_22 => X"5d555ccc5c445bbb5b335aaa5a2159995910588857ff577756ee566655dd5555",
INIT_23 => X"65dd655564cc644463bb633362aa62216199611060885fff5f775eee5e665ddd",
INIT_24 => X"6e106d8e6d0b6c886c056b826aff6a7c69fa697768f4687167ee676b66e96666",
INIT_25 => X"763e75bb753874b5743273b0732d72aa722771a47121709f701c6f996f166e93",
INIT_26 => X"7e6b7de87d667ce37c607bdd7b5a7ad77a5579d2794f78cc784977c6774476c1",
INIT_27 => X"8699861685938510848d840b83888305828281ff817c80fa80777ff47f717eee",
INIT_28 => X"8f718ee38e558dc68d388caa8c1c8b8d8aff8a7189e3895588c6883887aa871c",
INIT_29 => X"985597c6973896aa961c958d94ff947193e3935592c6923891aa911c908d8fff",
INIT_2A => X"a138a0aaa01c9f8d9eff9e719de39d559cc69c389baa9b1c9a8d99ff997198e3",
INIT_2B => X"aa1ca98da8ffa871a7e3a755a6c6a638a5aaa51ca48da3ffa371a2e3a255a1c6",
INIT_2C => X"b2ffb271b1e3b154b0c6b038afaaaf1cae8dadffad71ace3ac54abc6ab38aaaa",
INIT_2D => X"bbe3bb54bac6ba38b9aab91cb88db7ffb771b6e3b654b5c6b538b4aab41cb38d",
INIT_2E => X"c4c6c438c3aac31cc28dc1ffc171c0e3c054bfc6bf38beaabe1cbd8dbcffbc71",
INIT_2F => X"cdaacd1ccc8dcbffcb71cae3ca54c9c6c938c8aac81cc78dc6ffc671c5e3c554",
INIT_30 => X"d338d2e3d28dd238d1e3d18dd138d0e3d08dd038cfe3cf8dcf38cee3ce8dce38",
INIT_31 => X"d88dd838d7e3d78dd738d6e3d68dd638d5e3d58dd538d4e3d48dd438d3e3d38d",
INIT_32 => X"dde3dd8ddd38dce3dc8ddc38dbe3db8ddb38dae3da8dda38d9e3d98dd938d8e3",
INIT_33 => X"e338e2e3e28de238e1e3e18de138e0e3e08de038dfe3df8ddf38dee3de8dde38",
INIT_34 => X"e738e6f9e6bbe67ce63ee5ffe5c0e582e543e505e4c6e488e449e40ae3cce38d",
INIT_35 => X"eb21eae3eaa4ea65ea27e9e8e9aae96be92de8eee8afe871e832e7f4e7b5e777",
INIT_36 => X"ef0aeeccee8dee4fee10edd2ed93ed54ed16ecd7ec99ec5aec1bebddeb9eeb60",
INIT_37 => X"f2f4f2b5f276f238f1f9f1bbf17cf13ef0fff0c0f082f043f005efc6ef88ef49",
INIT_38 => X"f532f510f4eef4ccf4aaf488f465f443f421f3fff3ddf3bbf399f376f354f332",
INIT_39 => X"f754f732f710f6eef6ccf6aaf688f665f643f621f5fff5ddf5bbf599f576f554",
INIT_3A => X"f976f954f932f910f8eef8ccf8aaf888f865f843f821f7fff7ddf7bbf799f776",
INIT_3B => X"fb99fb76fb54fb32fb10faeefaccfaaafa88fa65fa43fa21f9fff9ddf9bbf999",
INIT_3C => X"fcbdfcacfc9afc89fc78fc67fc56fc44fc33fc22fc11fc00fbeefbddfbccfbbb",
INIT_3D => X"fdd0fdbffdaefd9cfd8bfd7afd69fd58fd46fd35fd24fd13fd02fcf0fcdffcce",
INIT_3E => X"fee3fed2fec1feb0fe9efe8dfe7cfe6bfe5afe48fe37fe26fe15fe04fdf2fde1",
INIT_3F => X"fff6ffe5ffd4ffc3ffb2ffa0ff8fff7eff6dff5cff4aff39ff28ff17ff06fef4" )
port map (
DOA => io_rdata,
DOPA => open,
ADDRA => std_logic_vector(io_req.address(10 downto 0)),
CLKA => clock,
DIA => io_req.data,
DIPA => "0",
ENA => io_coef_en,
SSRA => '0',
WEA => io_req.write,
DOB => filt_ram,
DOPB => open,
ADDRB => std_logic_vector(filt_co(10 downto 1)),
CLKB => clock,
DIB => X"0000",
DIPB => "00",
ENB => '1',
SSRB => '0',
WEB => '0' );
io_coef_en <= io_req.read or io_req.write;
io_coef_en_d <= io_coef_en when rising_edge(clock);
io_resp.ack <= io_coef_en_d;
io_resp.data <= X"00"; --io_rdata when io_coef_en_d = '1' else X"00";
process(clock)
begin
if rising_edge(clock) then
filter_f <= "00" & signed(filt_ram(15 downto 0));
end if;
end process;
--input_sc <= input;
input_sc <= shift_right(input, 1) & "0000";
-- now perform the arithmetic
xa <= filter_f when xa_select='0' else filter_q;
xb <= bp_reg(21 downto 4) when xb_select='0' else hp_reg (21 downto 4);
sum_b <= bp_reg when xb_select='0' else lp_reg;
sub_a <= input_sc when sub_a_sel='0' else temp_reg;
sub_b <= lp_reg when sub_b_sel='0' else x_reg;
process(clock)
variable x_result : signed(35 downto 0);
variable sum_result : signed(21 downto 0);
variable sub_result : signed(21 downto 0);
begin
if rising_edge(clock) then
x_result := xa * xb;
if mult_enable='1' then
x_reg <= x_result(33 downto 12);
if (x_result(35 downto 33) /= "000") and (x_result(35 downto 33) /= "111") then
error <= not error;
end if;
end if;
sum_result := sum_limit(x_reg, sum_b);
if sum_to_lp='1' then
lp_reg <= sum_result;
end if;
if sum_to_bp='1' then
bp_reg <= sum_result;
end if;
sub_result := sub_limit(sub_a, sub_b);
temp_reg <= sub_result;
if sub_to_hp='1' then
hp_reg <= sub_result;
end if;
-- control part
instruction <= (others => '0');
if reset='1' then
hp_reg <= (others => '0');
lp_reg <= (others => '0');
bp_reg <= (others => '0');
program_counter <= 0;
elsif valid_in = '1' then
program_counter <= 0;
else
if program_counter /= 15 then
program_counter <= program_counter + 1;
end if;
if program_counter < c_program'length then
instruction <= c_program(program_counter);
end if;
end if;
if program_counter = c_program'length then
valid_out <= '1';
else
valid_out <= '0';
end if;
end if;
end process;
high_pass <= hp_reg(21 downto 4);
band_pass <= bp_reg(21 downto 4);
low_pass <= lp_reg(21 downto 4);
error_out <= error;
end dsvf;
| gpl-3.0 | 3a12bca1fa67af498fa59d26ed296383 | 0.615454 | 2.861796 | false | false | false | false |
markusC64/1541ultimate2 | fpga/ip/clock/vhdl_source/fractional_div.vhd | 1 | 3,428 | --------------------------------------------------------------------------------
-- Entity: fractional_div
-- Date:2018-08-18
-- Author: gideon
--
-- Description: Fractional Divider
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fractional_div is
generic (
g_numerator : natural := 3;
g_denominator : natural := 200 );
port (
clock : in std_logic;
tick : out std_logic; -- this should yield a 16 MHz tick
tick_by_4 : out std_logic; -- this should yield a 4 MHz tick (for drive logic)
tick_by_16 : out std_logic; -- this should yield an 1 MHz tick (i.e. for IEC processor)
one_16000 : out std_logic ); -- and thus, this should yield a 1 ms tick
end entity;
architecture arch of fractional_div is
constant c_min : integer := -g_numerator;
constant c_max : integer := g_denominator - g_numerator - 1;
function log2_ceil(arg: integer) return natural is
variable v_temp : integer;
variable v_result : natural;
begin
v_result := 0;
v_temp := arg / 2;
while v_temp /= 0 loop
v_temp := v_temp / 2;
v_result := v_result + 1;
end loop;
if 2**v_result < arg then
v_result := v_result + 1;
end if;
assert false report "Ceil: " & integer'image(arg) & " result: " & integer'image(v_result) severity warning;
return v_result;
end function;
function maxof2(a, b : integer) return integer is
variable res : integer;
begin
res := b;
assert false report "Max: " & integer'image(a) & " and " & integer'image(b) severity warning;
if a > b then
res := a;
end if;
return res;
end function;
signal c_bits_min : integer := 1 + log2_ceil(-c_min - 1);
signal c_bits_max : integer := 1 + log2_ceil(c_max);
signal accu : signed(7 downto 0) := (others => '0');
signal div16000 : unsigned(13 downto 0) := to_unsigned(128, 14);
begin
assert c_bits_max <= 8 report "Need more bits for accu (max:"&integer'image(c_max)&", but Xilinx doesn't let me define this dynamically:" & integer'image(c_bits_max) severity error;
assert c_bits_min <= 8 report "Need more bits for accu (max:"&integer'image(c_min)&", but Xilinx doesn't let me define this dynamically:" & integer'image(c_bits_min) severity error;
process(clock)
begin
if rising_edge(clock) then
tick <= '0';
one_16000 <= '0';
tick_by_4 <= '0';
tick_by_16 <= '0';
if accu(accu'high) = '1' then
if div16000 = 0 then
one_16000 <= '1';
div16000 <= to_unsigned(15999, 14);
else
div16000 <= div16000 - 1;
end if;
if div16000(3 downto 0) = "0001" then
tick_by_16 <= '1';
end if;
if div16000(1 downto 0) = "01" then
tick_by_4 <= '1';
end if;
tick <= '1';
accu <= accu + (g_denominator - g_numerator);
else
accu <= accu - g_numerator;
end if;
end if;
end process;
end architecture;
| gpl-3.0 | 6769385a9d1d905fb6198b0e35a7f4fe | 0.505834 | 3.886621 | false | false | false | false |
markusC64/1541ultimate2 | fpga/io/rmii/vhdl_sim/eth_transmit_tb.vhd | 1 | 7,576 | -------------------------------------------------------------------------------
-- Title : eth_transmit_tb
-- Author : Gideon Zweijtzer ([email protected])
-------------------------------------------------------------------------------
-- Description: Testbench for ethernet transmit unit
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.io_bus_bfm_pkg.all;
use work.block_bus_pkg.all;
use work.mem_bus_pkg.all;
entity eth_transmit_tb is
end entity;
architecture testcase of eth_transmit_tb is
signal clock : std_logic := '0'; -- 50 MHz reference clock
signal reset : std_logic;
signal io_clock : std_logic := '0'; -- 66 MHz reference clock
signal io_reset : std_logic;
signal rmii_crs_dv : std_logic;
signal rmii_rxd : std_logic_vector(1 downto 0);
signal rmii_tx_en : std_logic;
signal rmii_txd : std_logic_vector(1 downto 0);
signal eth_rx_data : std_logic_vector(7 downto 0);
signal eth_rx_sof : std_logic;
signal eth_rx_eof : std_logic;
signal eth_rx_valid : std_logic;
signal eth_tx_data : std_logic_vector(7 downto 0);
signal eth_tx_sof : std_logic;
signal eth_tx_eof : std_logic;
signal eth_tx_valid : std_logic;
signal eth_tx_ready : std_logic;
signal ten_meg_mode : std_logic := '0';
signal io_req : t_io_req;
signal io_resp : t_io_resp;
signal io_irq : std_logic;
signal mem_req : t_mem_req_32;
signal mem_resp : t_mem_resp_32 := c_mem_resp_32_init;
type t_byte_array is array (natural range <>) of std_logic_vector(7 downto 0);
constant c_frame_with_crc : t_byte_array := (
X"00", X"0A", X"E6", X"F0", X"05", X"A3", X"00", X"12", X"34", X"56", X"78", X"90", X"08", X"00", X"45", X"00",
X"00", X"30", X"B3", X"FE", X"00", X"00", X"80", X"11", X"72", X"BA", X"0A", X"00", X"00", X"03", X"0A", X"00",
X"00", X"02", X"04", X"00", X"04", X"00", X"00", X"1C", X"89", X"4D", X"00", X"01", X"02", X"03", X"04", X"05",
X"06", X"07", X"08", X"09", X"0A", X"0B", X"0C", X"0D", X"0E", X"0F", X"10", X"11", X"12", X"13"
-- , X"7A", X"D5", X"6B", X"B3"
);
procedure io_write_long(variable io : inout p_io_bus_bfm_object; addr : natural; data : std_logic_vector(31 downto 0)) is
begin
io_write(io, to_unsigned(addr+0, 20), data(07 downto 00));
io_write(io, to_unsigned(addr+1, 20), data(15 downto 08));
io_write(io, to_unsigned(addr+2, 20), data(23 downto 16));
io_write(io, to_unsigned(addr+3, 20), data(31 downto 24));
end procedure;
procedure io_write_word(variable io : inout p_io_bus_bfm_object; addr : natural; data : std_logic_vector(15 downto 0)) is
begin
io_write(io, to_unsigned(addr+0, 20), data(07 downto 00));
io_write(io, to_unsigned(addr+1, 20), data(15 downto 08));
end procedure;
procedure io_write(variable io : inout p_io_bus_bfm_object; addr : natural; data : std_logic_vector(7 downto 0)) is
begin
io_write(io, to_unsigned(addr, 20), data);
end procedure;
procedure io_read(variable io : inout p_io_bus_bfm_object; addr : natural; data : out std_logic_vector(7 downto 0)) is
begin
io_read(io, to_unsigned(addr, 20), data);
end procedure;
procedure io_read_word(variable io : inout p_io_bus_bfm_object; addr : natural; data : out std_logic_vector(15 downto 0)) is
begin
io_read(io, to_unsigned(addr, 20), data(7 downto 0));
io_read(io, to_unsigned(addr+1, 20), data(15 downto 8));
end procedure;
begin
clock <= not clock after 10 ns;
reset <= '1', '0' after 100 ns;
io_clock <= not io_clock after 8 ns;
io_reset <= '1', '0' after 100 ns;
i_rmii: entity work.rmii_transceiver
port map (
clock => clock,
reset => reset,
rmii_crs_dv => rmii_crs_dv,
rmii_rxd => rmii_rxd,
rmii_tx_en => rmii_tx_en,
rmii_txd => rmii_txd,
eth_rx_data => eth_rx_data,
eth_rx_sof => eth_rx_sof,
eth_rx_eof => eth_rx_eof,
eth_rx_valid => eth_rx_valid,
eth_tx_data => eth_tx_data,
eth_tx_sof => eth_tx_sof,
eth_tx_eof => eth_tx_eof,
eth_tx_valid => eth_tx_valid,
eth_tx_ready => eth_tx_ready,
ten_meg_mode => ten_meg_mode
);
rmii_crs_dv <= rmii_tx_en;
rmii_rxd <= rmii_txd;
i_mut: entity work.eth_transmit
generic map (
g_mem_tag => X"33"
)
port map(
clock => io_clock,
reset => io_reset,
io_req => io_req,
io_resp => io_resp,
io_irq => io_irq,
mem_req => mem_req,
mem_resp => mem_resp,
eth_clock => clock,
eth_reset => reset,
eth_tx_data => eth_tx_data,
eth_tx_sof => eth_tx_sof,
eth_tx_eof => eth_tx_eof,
eth_tx_valid => eth_tx_valid,
eth_tx_ready => eth_tx_ready
);
test: process
variable io : p_io_bus_bfm_object;
variable data : std_logic_vector(7 downto 0);
--variable i : natural;
begin
wait until reset = '0';
bind_io_bus_bfm("io", io);
io_write_long(io, 0, X"01200000");
io_write_word(io, 4, X"0010");
io_write(io, 8, X"00"); -- start
wait until io_irq = '1';
io_write(io, 9, X"00"); -- clear IRQ
io_write_long(io, 0, X"01200003");
io_write_word(io, 4, X"0011");
io_write(io, 8, X"00"); -- start
wait until io_irq = '1';
io_write(io, 9, X"00"); -- clear IRQ
io_write_long(io, 0, X"02200002");
io_write_word(io, 4, X"0700");
io_write(io, 8, X"00"); -- start
wait until io_irq = '1';
io_write(io, 9, X"00"); -- clear IRQ
wait;
end process;
i_bfm: entity work.io_bus_bfm
generic map ("io")
port map (
clock => io_clock,
req => io_req,
resp => io_resp
);
process(io_clock)
variable c : integer := 0;
variable dack : std_logic_vector(2 downto 0) := "000";
variable w : natural := 4096;
impure function get_word return std_logic_vector is
begin
w := w + 1;
return std_logic_vector(to_unsigned(w, 16));
end function;
begin
if rising_edge(io_clock) then
if mem_req.request = '1' then
c := c + 1;
end if;
dack(2 downto 0) := '0' & dack(2 downto 1);
if c = 2 then
mem_resp.rack <= '1';
mem_resp.rack_tag <= mem_req.tag;
dack(2) := '1';
c := 0;
else
mem_resp.rack <= '0';
mem_resp.rack_tag <= X"00";
end if;
if dack(0) = '1' then
mem_resp.dack_tag <= mem_req.tag;
mem_resp.data(15 downto 0) <= get_word;
mem_resp.data(31 downto 16) <= get_word;
else
mem_resp.dack_tag <= X"00";
end if;
end if;
end process;
end architecture;
| gpl-3.0 | 624c3f3a5e4f17fed41a70765e4e020d | 0.497624 | 3.202029 | false | false | false | false |
fpgaddicted/5bit-shift-register-structural- | variable_prescaler.vhd | 1 | 1,971 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:55:03 04/17/2017
-- Design Name:
-- Module Name: variable_prescaler - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity variable_prescaler is
Port ( clk_in : in STD_LOGIC;
control : in STD_LOGIC_VECTOR( 1 downto 0);
reset : in STD_LOGIC;
clk_out : out STD_LOGIC);
end variable_prescaler;
architecture Behavioral of variable_prescaler is
signal limit :integer :=0 ;
signal temporal: STD_LOGIC;
signal counter : integer range 0 to 50000000 := 0;
begin
process(control)
begin
case control is
when "00" => limit <= 25000000;
when "01" => limit <= 12500000;
when "10" => limit <= 6250000;
when "11" => limit <= 3125000;
when others => limit <= 0;
end case;
end process;
frequency_divider: process (reset, clk_in, limit)
begin
if (reset = '1') then
temporal <= '0';
counter <= 0;
elsif rising_edge(clk_in) then
if (counter = limit) then
temporal <= NOT(temporal);
counter <= 0;
else
counter <= counter + 1;
end if;
end if;
end process;
clk_out <= temporal;
end Behavioral;
| gpl-3.0 | 64696a93b339fc121cced8e4bcf473a8 | 0.535261 | 4.132075 | false | false | false | false |
markusC64/1541ultimate2 | target/fpga/u2p_memtest/memphy_alt_mem_phy_seq.vhd | 1 | 647,405 | --
-- -----------------------------------------------------------------------------
-- Abstract : constants package for the non-levelling AFI PHY sequencer
-- The constant package (alt_mem_phy_constants_pkg) contains global
-- 'constants' which are fixed thoughout the sequencer and will not
-- change (for constants which may change between sequencer
-- instances generics are used)
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--
package memphy_alt_mem_phy_constants_pkg is
-- -------------------------------
-- Register number definitions
-- -------------------------------
constant c_max_mode_reg_index : natural := 13; -- number of MR bits..
-- Top bit of vector (i.e. width -1) used for address decoding :
constant c_debug_reg_addr_top : natural := 3;
constant c_mmi_access_codeword : std_logic_vector(31 downto 0) := X"00D0_0DEB"; -- to check for legal Avalon interface accesses
-- Register addresses.
constant c_regofst_cal_status : natural := 0;
constant c_regofst_debug_access : natural := 1;
constant c_regofst_hl_css : natural := 2;
constant c_regofst_mr_register_a : natural := 5;
constant c_regofst_mr_register_b : natural := 6;
constant c_regofst_codvw_status : natural := 12;
constant c_regofst_if_param : natural := 13;
constant c_regofst_if_test : natural := 14; -- pll_phs_shft, ac_1t, extra stuff
constant c_regofst_test_status : natural := 15;
constant c_hl_css_reg_cal_dis_bit : natural := 0;
constant c_hl_css_reg_phy_initialise_dis_bit : natural := 1;
constant c_hl_css_reg_init_dram_dis_bit : natural := 2;
constant c_hl_css_reg_write_ihi_dis_bit : natural := 3;
constant c_hl_css_reg_write_btp_dis_bit : natural := 4;
constant c_hl_css_reg_write_mtp_dis_bit : natural := 5;
constant c_hl_css_reg_read_mtp_dis_bit : natural := 6;
constant c_hl_css_reg_rrp_reset_dis_bit : natural := 7;
constant c_hl_css_reg_rrp_sweep_dis_bit : natural := 8;
constant c_hl_css_reg_rrp_seek_dis_bit : natural := 9;
constant c_hl_css_reg_rdv_dis_bit : natural := 10;
constant c_hl_css_reg_poa_dis_bit : natural := 11;
constant c_hl_css_reg_was_dis_bit : natural := 12;
constant c_hl_css_reg_adv_rd_lat_dis_bit : natural := 13;
constant c_hl_css_reg_adv_wr_lat_dis_bit : natural := 14;
constant c_hl_css_reg_prep_customer_mr_setup_dis_bit : natural := 15;
constant c_hl_css_reg_tracking_dis_bit : natural := 16;
constant c_hl_ccs_num_stages : natural := 17;
-- -----------------------------------------------------
-- Constants for DRAM addresses used during calibration:
-- -----------------------------------------------------
-- the mtp training pattern is x30F5
-- 1. write 0011 0000 and 1100 0000 such that one location will contains 0011 0000
-- 2. write in 1111 0101
-- also require locations containing all ones and all zeros
-- default choice of calibration burst length (overriden to 8 for reads for DDR3 devices)
constant c_cal_burst_len : natural := 4;
constant c_cal_ofs_step_size : natural := 8;
constant c_cal_ofs_zeros : natural := 0 * c_cal_ofs_step_size;
constant c_cal_ofs_ones : natural := 1 * c_cal_ofs_step_size;
constant c_cal_ofs_x30_almt_0 : natural := 2 * c_cal_ofs_step_size;
constant c_cal_ofs_x30_almt_1 : natural := 3 * c_cal_ofs_step_size;
constant c_cal_ofs_xF5 : natural := 5 * c_cal_ofs_step_size;
constant c_cal_ofs_wd_lat : natural := 6 * c_cal_ofs_step_size;
constant c_cal_data_len : natural := c_cal_ofs_wd_lat + c_cal_ofs_step_size;
constant c_cal_ofs_mtp : natural := 6*c_cal_ofs_step_size;
constant c_cal_ofs_mtp_len : natural := 4*4;
constant c_cal_ofs_01_pairs : natural := 2 * c_cal_burst_len;
constant c_cal_ofs_10_pairs : natural := 3 * c_cal_burst_len;
constant c_cal_ofs_1100_step : natural := 4 * c_cal_burst_len;
constant c_cal_ofs_0011_step : natural := 5 * c_cal_burst_len;
-- -----------------------------------------------------
-- Reset values. - These are chosen as default values for one PHY variation
-- with DDR2 memory and CAS latency 6, however in each calibration
-- mode these values will be set for a given PHY configuration.
-- -----------------------------------------------------
constant c_default_rd_lat : natural := 20;
constant c_default_wr_lat : natural := 5;
-- -----------------------------------------------------
-- Errorcodes
-- -----------------------------------------------------
-- implemented
constant C_SUCCESS : natural := 0;
constant C_ERR_RESYNC_NO_VALID_PHASES : natural := 5; -- No valid data-valid windows found
constant C_ERR_RESYNC_MULTIPLE_EQUAL_WINDOWS : natural := 6; -- Multiple equally-sized data valid windows
constant C_ERR_RESYNC_NO_INVALID_PHASES : natural := 7; -- No invalid data-valid windows found. Training patterns are designed so that there should always be at least one invalid phase.
constant C_ERR_CRITICAL : natural := 15; -- A condition that can't happen just happened.
constant C_ERR_READ_MTP_NO_VALID_ALMT : natural := 23;
constant C_ERR_READ_MTP_BOTH_ALMT_PASS : natural := 24;
constant C_ERR_WD_LAT_DISAGREEMENT : natural := 22; -- MEM_IF_DWIDTH/MEM_IF_DQ_PER_DQS copies of write-latency are written to memory. If all of these are not the same this error is generated.
constant C_ERR_MAX_RD_LAT_EXCEEDED : natural := 25;
constant C_ERR_MAX_TRK_SHFT_EXCEEDED : natural := 26;
-- not implemented yet
constant c_err_ac_lat_some_beats_are_different : natural := 1; -- implies DQ_1T setup failure or earlier.
constant c_err_could_not_find_read_lat : natural := 2; -- dodgy RDP setup
constant c_err_could_not_find_write_lat : natural := 3; -- dodgy WDP setup
constant c_err_clock_cycle_iteration_timeout : natural := 8; -- depends on srate calling error -- GENERIC
constant c_err_clock_cycle_it_timeout_rdp : natural := 9;
constant c_err_clock_cycle_it_timeout_rdv : natural := 10;
constant c_err_clock_cycle_it_timeout_poa : natural := 11;
constant c_err_pll_ack_timeout : natural := 13;
constant c_err_WindowProc_multiple_rsc_windows : natural := 16;
constant c_err_WindowProc_window_det_no_ones : natural := 17;
constant c_err_WindowProc_window_det_no_zeros : natural := 18;
constant c_err_WindowProc_undefined : natural := 19; -- catch all
constant c_err_tracked_mmc_offset_overflow : natural := 20;
constant c_err_no_mimic_feedback : natural := 21;
constant c_err_ctrl_ack_timeout : natural := 32;
constant c_err_ctrl_done_timeout : natural := 33;
-- -----------------------------------------------------
-- PLL phase locations per device family
-- (unused but a limited set is maintained here for reference)
-- -----------------------------------------------------
constant c_pll_resync_phs_select_ciii : natural := 5;
constant c_pll_mimic_phs_select_ciii : natural := 4;
constant c_pll_resync_phs_select_siii : natural := 5;
constant c_pll_mimic_phs_select_siii : natural := 7;
-- -----------------------------------------------------
-- Maximum sizing constraints
-- -----------------------------------------------------
constant C_MAX_NUM_PLL_RSC_PHASES : natural := 32;
-- -----------------------------------------------------
-- IO control Params
-- -----------------------------------------------------
constant c_set_oct_to_rs : std_logic := '0';
constant c_set_oct_to_rt : std_logic := '1';
constant c_set_odt_rt : std_logic := '1';
constant c_set_odt_off : std_logic := '0';
--
end memphy_alt_mem_phy_constants_pkg;
--
-- -----------------------------------------------------------------------------
-- Abstract : record package for the non-levelling AFI sequencer
-- The record package (alt_mem_phy_record_pkg) is used to combine
-- command and status signals (into records) to be passed between
-- sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--
package memphy_alt_mem_phy_record_pkg is
-- set some maximum constraints to bound natural numbers below
constant c_max_num_dqs_groups : natural := 24;
constant c_max_num_pins : natural := 8;
constant c_max_ranks : natural := 16;
constant c_max_pll_steps : natural := 80;
-- a prefix for all report signals to identify phy and sequencer block
--
constant record_report_prefix : string := "memphy_alt_mem_phy_record_pkg : ";
type t_family is (
cyclone3,
stratix2,
stratix3
);
-- -----------------------------------------------------------------------
-- the following are required for the non-levelling AFI PHY sequencer block interfaces
-- -----------------------------------------------------------------------
-- admin mode register settings (from mmi block)
type t_admin_ctrl is record
mr0 : std_logic_vector(12 downto 0);
mr1 : std_logic_vector(12 downto 0);
mr2 : std_logic_vector(12 downto 0);
mr3 : std_logic_vector(12 downto 0);
end record;
function defaults return t_admin_ctrl;
-- current admin status
type t_admin_stat is record
mr0 : std_logic_vector(12 downto 0);
mr1 : std_logic_vector(12 downto 0);
mr2 : std_logic_vector(12 downto 0);
mr3 : std_logic_vector(12 downto 0);
init_done : std_logic;
end record;
function defaults return t_admin_stat;
-- mmi to iram ctrl signals
type t_iram_ctrl is record
addr : natural range 0 to 1023;
wdata : std_logic_vector(31 downto 0);
write : std_logic;
read : std_logic;
end record;
function defaults return t_iram_ctrl;
-- broadcast iram status to mmi and dgrb
type t_iram_stat is record
rdata : std_logic_vector(31 downto 0);
done : std_logic;
err : std_logic;
err_code : std_logic_vector(3 downto 0);
init_done : std_logic;
out_of_mem : std_logic;
contested_access : std_logic;
end record;
function defaults return t_iram_stat;
-- codvw status signals from dgrb to mmi block
type t_dgrb_mmi is record
cal_codvw_phase : std_logic_vector(7 downto 0);
cal_codvw_size : std_logic_vector(7 downto 0);
codvw_trk_shift : std_logic_vector(11 downto 0);
codvw_grt_one_dvw : std_logic;
end record;
function defaults return t_dgrb_mmi;
-- signal to id which block is active
type t_ctrl_active_block is (
idle,
admin,
dgwb,
dgrb,
proc, -- unused in non-levelling AFI sequencer
setup, -- unused in non-levelling AFI sequencer
iram
);
function ret_proc return t_ctrl_active_block;
function ret_dgrb return t_ctrl_active_block;
-- control record for dgwb, dgrb, iram and admin blocks:
-- the possible commands
type t_ctrl_cmd_id is (
cmd_idle,
-- initialisation stages
cmd_phy_initialise,
cmd_init_dram,
cmd_prog_cal_mr,
cmd_write_ihi,
-- calibration stages
cmd_write_btp,
cmd_write_mtp,
cmd_read_mtp,
cmd_rrp_reset,
cmd_rrp_sweep,
cmd_rrp_seek,
cmd_rdv,
cmd_poa,
cmd_was,
-- advertise controller settings and re-configure for customer operation mode.
cmd_prep_adv_rd_lat,
cmd_prep_adv_wr_lat,
cmd_prep_customer_mr_setup,
cmd_tr_due
);
-- which block should execute each command
function curr_active_block (
ctrl_cmd_id : t_ctrl_cmd_id
) return t_ctrl_active_block;
-- specify command operands as a record
type t_command_op is record
current_cs : natural range 0 to c_max_ranks-1; -- which chip select is being calibrated
single_bit : std_logic; -- current operation should be single bit
mtp_almt : natural range 0 to 1; -- signals mtp alignment to be used for operation
end record;
function defaults return t_command_op;
-- command request record (sent to each block)
type t_ctrl_command is record
command : t_ctrl_cmd_id;
command_op : t_command_op;
command_req : std_logic;
end record;
function defaults return t_ctrl_command;
-- a generic status record for each block
type t_ctrl_stat is record
command_ack : std_logic;
command_done : std_logic;
command_result : std_logic_vector(7 downto 0 );
command_err : std_logic;
end record;
function defaults return t_ctrl_stat;
-- push interface for dgwb / dgrb blocks (only the dgrb uses this interface at present)
type t_iram_push is record
iram_done : std_logic;
iram_write : std_logic;
iram_wordnum : natural range 0 to 511; -- acts as an offset to current location (max = 80 pll steps *2 sweeps and 80 pins)
iram_bitnum : natural range 0 to 31; -- for bitwise packing modes
iram_pushdata : std_logic_vector(31 downto 0); -- only bit zero used for bitwise packing_mode
end record;
function defaults return t_iram_push;
-- control block "master" state machine
type t_master_sm_state is
(
s_reset,
s_phy_initialise, -- wait for dll lock and init done flag from iram
s_init_dram, -- dram initialisation - reset sequence
s_prog_cal_mr, -- dram initialisation - programming mode registers (once per chip select)
s_write_ihi, -- write header information in iRAM
s_cal, -- check if calibration to be executed
s_write_btp, -- write burst training pattern
s_write_mtp, -- write more training pattern
s_read_mtp, -- read training patterns to find correct alignment for 1100 burst
-- (this is a special case of s_rrp_seek with no resych phase setting)
s_rrp_reset, -- read resync phase setup - reset initial conditions
s_rrp_sweep, -- read resync phase setup - sweep phases per chip select
s_rrp_seek, -- read resync phase setup - seek correct phase
s_rdv, -- read data valid setup
s_was, -- write datapath setup (ac to write data timing)
s_adv_rd_lat, -- advertise read latency
s_adv_wr_lat, -- advertise write latency
s_poa, -- calibrate the postamble (dqs based capture only)
s_tracking_setup, -- perform tracking (1st pass to setup mimic window)
s_prep_customer_mr_setup, -- apply user mode register settings (in admin block)
s_tracking, -- perform tracking (subsequent passes in user mode)
s_operational, -- calibration successful and in user mode
s_non_operational -- calibration unsuccessful and in user mode
);
-- record (set in mmi block) to disable calibration states
type t_hl_css_reg is record
phy_initialise_dis : std_logic;
init_dram_dis : std_logic;
write_ihi_dis : std_logic;
cal_dis : std_logic;
write_btp_dis : std_logic;
write_mtp_dis : std_logic;
read_mtp_dis : std_logic;
rrp_reset_dis : std_logic;
rrp_sweep_dis : std_logic;
rrp_seek_dis : std_logic;
rdv_dis : std_logic;
poa_dis : std_logic;
was_dis : std_logic;
adv_rd_lat_dis : std_logic;
adv_wr_lat_dis : std_logic;
prep_customer_mr_setup_dis : std_logic;
tracking_dis : std_logic;
end record;
function defaults return t_hl_css_reg;
-- record (set in ctrl block) to identify when a command has been acknowledged
type t_cal_stage_ack_seen is record
cal : std_logic;
phy_initialise : std_logic;
init_dram : std_logic;
write_ihi : std_logic;
write_btp : std_logic;
write_mtp : std_logic;
read_mtp : std_logic;
rrp_reset : std_logic;
rrp_sweep : std_logic;
rrp_seek : std_logic;
rdv : std_logic;
poa : std_logic;
was : std_logic;
adv_rd_lat : std_logic;
adv_wr_lat : std_logic;
prep_customer_mr_setup : std_logic;
tracking_setup : std_logic;
end record;
function defaults return t_cal_stage_ack_seen;
-- ctrl to mmi block interface (calibration status)
type t_ctrl_mmi is record
master_state_r : t_master_sm_state;
ctrl_calibration_success : std_logic;
ctrl_calibration_fail : std_logic;
ctrl_current_stage_done : std_logic;
ctrl_current_stage : t_ctrl_cmd_id;
ctrl_current_active_block : t_ctrl_active_block;
ctrl_cal_stage_ack_seen : t_cal_stage_ack_seen;
ctrl_err_code : std_logic_vector(7 downto 0);
end record;
function defaults return t_ctrl_mmi;
-- mmi to ctrl block interface (calibration control signals)
type t_mmi_ctrl is record
hl_css : t_hl_css_reg;
calibration_start : std_logic;
tracking_period_ms : natural range 0 to 255;
tracking_orvd_to_10ms : std_logic;
end record;
function defaults return t_mmi_ctrl;
-- algorithm parameterisation (generated in mmi block)
type t_algm_paramaterisation is record
num_phases_per_tck_pll : natural range 1 to c_max_pll_steps;
nominal_dqs_delay : natural range 0 to 4;
pll_360_sweeps : natural range 0 to 15;
nominal_poa_phase_lead : natural range 0 to 7;
maximum_poa_delay : natural range 0 to 15;
odt_enabled : boolean;
extend_octrt_by : natural range 0 to 15;
delay_octrt_by : natural range 0 to 15;
tracking_period_ms : natural range 0 to 255;
end record;
-- interface between mmi and pll to control phase shifting
type t_mmi_pll_reconfig is record
pll_phs_shft_phase_sel : natural range 0 to 15;
pll_phs_shft_up_wc : std_logic;
pll_phs_shft_dn_wc : std_logic;
end record;
type t_pll_mmi is record
pll_busy : std_logic;
err : std_logic_vector(1 downto 0);
end record;
-- specify the iram configuration this is default
-- currently always dq_bitwise packing and a write mode of overwrite_ram
type t_iram_packing_mode is (
dq_bitwise,
dq_wordwise
);
type t_iram_write_mode is (
overwrite_ram,
or_into_ram,
and_into_ram
);
type t_ctrl_iram is record
packing_mode : t_iram_packing_mode;
write_mode : t_iram_write_mode;
active_block : t_ctrl_active_block;
end record;
function defaults return t_ctrl_iram;
-- -----------------------------------------------------------------------
-- the following are required for compliance to levelling AFI PHY interface but
-- are non-functional for non-levelling AFI PHY sequencer
-- -----------------------------------------------------------------------
type t_sc_ctrl_if is record
read : std_logic;
write : std_logic;
dqs_group_sel : std_logic_vector( 4 downto 0);
sc_in_group_sel : std_logic_vector( 5 downto 0);
wdata : std_logic_vector(45 downto 0);
op_type : std_logic_vector( 1 downto 0);
end record;
function defaults return t_sc_ctrl_if;
type t_sc_stat is record
rdata : std_logic_vector(45 downto 0);
busy : std_logic;
error_det : std_logic;
err_code : std_logic_vector(1 downto 0);
sc_cap : std_logic_vector(7 downto 0);
end record;
function defaults return t_sc_stat;
type t_element_to_reconfigure is (
pp_t9,
pp_t10,
pp_t1,
dqslb_rsc_phs,
dqslb_poa_phs_ofst,
dqslb_dqs_phs,
dqslb_dq_phs_ofst,
dqslb_dq_1t,
dqslb_dqs_1t,
dqslb_rsc_1t,
dqslb_div2_phs,
dqslb_oct_t9,
dqslb_oct_t10,
dqslb_poa_t7,
dqslb_poa_t11,
dqslb_dqs_dly,
dqslb_lvlng_byps
);
type t_sc_type is (
DQS_LB,
DQS_DQ_DM_PINS,
DQ_DM_PINS,
dqs_dqsn_pins,
dq_pin,
dqs_pin,
dm_pin,
dq_pins
);
type t_sc_int_ctrl is record
group_num : natural range 0 to c_max_num_dqs_groups;
group_type : t_sc_type;
pin_num : natural range 0 to c_max_num_pins;
sc_element : t_element_to_reconfigure;
prog_val : std_logic_vector(3 downto 0);
ram_set : std_logic;
sc_update : std_logic;
end record;
function defaults return t_sc_int_ctrl;
-- -----------------------------------------------------------------------
-- record and functions for instant on mode
-- -----------------------------------------------------------------------
-- ranges on the below are not important because this logic is not synthesised
type t_preset_cal is record
codvw_phase : natural range 0 to 2*c_max_pll_steps;-- rsc phase
codvw_size : natural range 0 to c_max_pll_steps; -- rsc size (unused but reported)
rlat : natural; -- advertised read latency ctl_rlat (in phy clock cycles)
rdv_lat : natural; -- read data valid latency decrements needed (in memory clock cycles)
wlat : natural; -- advertised write latency ctl_wlat (in phy clock cycles)
ac_1t : std_logic; -- address / command 1t delay setting (HR only)
poa_lat : natural; -- poa latency decrements needed (in memory clock cycles)
end record;
-- the below are hardcoded (do not change)
constant c_ddr_default_cl : natural := 3;
constant c_ddr2_default_cl : natural := 6;
constant c_ddr3_default_cl : natural := 6;
constant c_ddr2_default_cwl : natural := 5;
constant c_ddr3_default_cwl : natural := 5;
constant c_ddr2_default_al : natural := 0;
constant c_ddr3_default_al : natural := 0;
constant c_ddr_default_rl : integer := c_ddr_default_cl;
constant c_ddr2_default_rl : integer := c_ddr2_default_cl + c_ddr2_default_al;
constant c_ddr3_default_rl : integer := c_ddr3_default_cl + c_ddr3_default_al;
constant c_ddr_default_wl : integer := 1;
constant c_ddr2_default_wl : integer := c_ddr2_default_cwl + c_ddr2_default_al;
constant c_ddr3_default_wl : integer := c_ddr3_default_cwl + c_ddr3_default_al;
function defaults return t_preset_cal;
function setup_instant_on (sim_time_red : natural;
family_id : natural;
memory_type : string;
dwidth_ratio : natural;
pll_steps : natural;
mr0 : std_logic_vector(15 downto 0);
mr1 : std_logic_vector(15 downto 0);
mr2 : std_logic_vector(15 downto 0)) return t_preset_cal;
--
end memphy_alt_mem_phy_record_pkg;
--
package body memphy_alt_mem_phy_record_pkg IS
-- -----------------------------------------------------------------------
-- function implementations for the above declarations
-- these are mainly default conditions for records
-- -----------------------------------------------------------------------
function defaults return t_admin_ctrl is
variable output : t_admin_ctrl;
begin
output.mr0 := (others => '0');
output.mr1 := (others => '0');
output.mr2 := (others => '0');
output.mr3 := (others => '0');
return output;
end function;
function defaults return t_admin_stat is
variable output : t_admin_stat;
begin
output.mr0 := (others => '0');
output.mr1 := (others => '0');
output.mr2 := (others => '0');
output.mr3 := (others => '0');
return output;
end function;
function defaults return t_iram_ctrl is
variable output : t_iram_ctrl;
begin
output.addr := 0;
output.wdata := (others => '0');
output.write := '0';
output.read := '0';
return output;
end function;
function defaults return t_iram_stat is
variable output : t_iram_stat;
begin
output.rdata := (others => '0');
output.done := '0';
output.err := '0';
output.err_code := (others => '0');
output.init_done := '0';
output.out_of_mem := '0';
output.contested_access := '0';
return output;
end function;
function defaults return t_dgrb_mmi is
variable output : t_dgrb_mmi;
begin
output.cal_codvw_phase := (others => '0');
output.cal_codvw_size := (others => '0');
output.codvw_trk_shift := (others => '0');
output.codvw_grt_one_dvw := '0';
return output;
end function;
function ret_proc return t_ctrl_active_block is
variable output : t_ctrl_active_block;
begin
output := proc;
return output;
end function;
function ret_dgrb return t_ctrl_active_block is
variable output : t_ctrl_active_block;
begin
output := dgrb;
return output;
end function;
function defaults return t_ctrl_iram is
variable output : t_ctrl_iram;
begin
output.packing_mode := dq_bitwise;
output.write_mode := overwrite_ram;
output.active_block := idle;
return output;
end function;
function defaults return t_command_op is
variable output : t_command_op;
begin
output.current_cs := 0;
output.single_bit := '0';
output.mtp_almt := 0;
return output;
end function;
function defaults return t_ctrl_command is
variable output : t_ctrl_command;
begin
output.command := cmd_idle;
output.command_req := '0';
output.command_op := defaults;
return output;
end function;
-- decode which block is associated with which command
function curr_active_block (
ctrl_cmd_id : t_ctrl_cmd_id
) return t_ctrl_active_block is
begin
case ctrl_cmd_id is
when cmd_idle => return idle;
when cmd_phy_initialise => return idle;
when cmd_init_dram => return admin;
when cmd_prog_cal_mr => return admin;
when cmd_write_ihi => return iram;
when cmd_write_btp => return dgwb;
when cmd_write_mtp => return dgwb;
when cmd_read_mtp => return dgrb;
when cmd_rrp_reset => return dgrb;
when cmd_rrp_sweep => return dgrb;
when cmd_rrp_seek => return dgrb;
when cmd_rdv => return dgrb;
when cmd_poa => return dgrb;
when cmd_was => return dgwb;
when cmd_prep_adv_rd_lat => return dgrb;
when cmd_prep_adv_wr_lat => return dgrb;
when cmd_prep_customer_mr_setup => return admin;
when cmd_tr_due => return dgrb;
when others => return idle;
end case;
end function;
function defaults return t_ctrl_stat is
variable output : t_ctrl_stat;
begin
output.command_ack := '0';
output.command_done := '0';
output.command_err := '0';
output.command_result := (others => '0');
return output;
end function;
function defaults return t_iram_push is
variable output : t_iram_push;
begin
output.iram_done := '0';
output.iram_write := '0';
output.iram_wordnum := 0;
output.iram_bitnum := 0;
output.iram_pushdata := (others => '0');
return output;
end function;
function defaults return t_hl_css_reg is
variable output : t_hl_css_reg;
begin
output.phy_initialise_dis := '0';
output.init_dram_dis := '0';
output.write_ihi_dis := '0';
output.cal_dis := '0';
output.write_btp_dis := '0';
output.write_mtp_dis := '0';
output.read_mtp_dis := '0';
output.rrp_reset_dis := '0';
output.rrp_sweep_dis := '0';
output.rrp_seek_dis := '0';
output.rdv_dis := '0';
output.poa_dis := '0';
output.was_dis := '0';
output.adv_rd_lat_dis := '0';
output.adv_wr_lat_dis := '0';
output.prep_customer_mr_setup_dis := '0';
output.tracking_dis := '0';
return output;
end function;
function defaults return t_cal_stage_ack_seen is
variable output : t_cal_stage_ack_seen;
begin
output.cal := '0';
output.phy_initialise := '0';
output.init_dram := '0';
output.write_ihi := '0';
output.write_btp := '0';
output.write_mtp := '0';
output.read_mtp := '0';
output.rrp_reset := '0';
output.rrp_sweep := '0';
output.rrp_seek := '0';
output.rdv := '0';
output.poa := '0';
output.was := '0';
output.adv_rd_lat := '0';
output.adv_wr_lat := '0';
output.prep_customer_mr_setup := '0';
output.tracking_setup := '0';
return output;
end function;
function defaults return t_mmi_ctrl is
variable output : t_mmi_ctrl;
begin
output.hl_css := defaults;
output.calibration_start := '0';
output.tracking_period_ms := 0;
output.tracking_orvd_to_10ms := '0';
return output;
end function;
function defaults return t_ctrl_mmi is
variable output : t_ctrl_mmi;
begin
output.master_state_r := s_reset;
output.ctrl_calibration_success := '0';
output.ctrl_calibration_fail := '0';
output.ctrl_current_stage_done := '0';
output.ctrl_current_stage := cmd_idle;
output.ctrl_current_active_block := idle;
output.ctrl_cal_stage_ack_seen := defaults;
output.ctrl_err_code := (others => '0');
return output;
end function;
-------------------------------------------------------------------------
-- the following are required for compliance to levelling AFI PHY interface but
-- are non-functional for non-levelling AFi PHY sequencer
-------------------------------------------------------------------------
function defaults return t_sc_ctrl_if is
variable output : t_sc_ctrl_if;
begin
output.read := '0';
output.write := '0';
output.dqs_group_sel := (others => '0');
output.sc_in_group_sel := (others => '0');
output.wdata := (others => '0');
output.op_type := (others => '0');
return output;
end function;
function defaults return t_sc_stat is
variable output : t_sc_stat;
begin
output.rdata := (others => '0');
output.busy := '0';
output.error_det := '0';
output.err_code := (others => '0');
output.sc_cap := (others => '0');
return output;
end function;
function defaults return t_sc_int_ctrl is
variable output : t_sc_int_ctrl;
begin
output.group_num := 0;
output.group_type := DQ_PIN;
output.pin_num := 0;
output.sc_element := pp_t9;
output.prog_val := (others => '0');
output.ram_set := '0';
output.sc_update := '0';
return output;
end function;
-- -----------------------------------------------------------------------
-- functions for instant on mode
--
--
-- Guide on how to use:
--
-- The following factors effect the setup of the PHY:
-- - AC Phase - phase at which address/command signals launched wrt PHY clock
-- - this effects the read/write latency
-- - MR settings - CL, CWL, AL
-- - Data rate - HR or FR (DDR/DDR2 only)
-- - Family - datapaths are subtly different for each
-- - Memory type - DDR/DDR2/DDR3 (different latency behaviour - see specs)
--
-- Instant on mode is designed to work for the following subset of the
-- above factors:
-- - AC Phase - out of the box defaults, which is 240 degrees for SIII type
-- families (includes SIV, HCIII, HCIV), else 90 degrees
-- - MR Settings - DDR - CL 3 only
-- - DDR2 - CL 3,4,5,6, AL 0
-- - DDR3 - CL 5,6 CWL 5, AL 0
-- - Data rate - All
-- - Families - All
-- - Memory type - All
--
-- Hints on bespoke setup for parameters outside the above or if the
-- datapath is modified (only for VHDL sim mode):
--
-- Step 1 - Run simulation with REDUCE_SIM_TIME mode 2 (FAST)
--
-- Step 2 - From the output log find the following text:
-- # -----------------------------------------------------------------------
-- **** ALTMEMPHY CALIBRATION has completed ****
-- Status:
-- calibration has : PASSED
-- PHY read latency (ctl_rlat) is : 14
-- address/command to PHY write latency (ctl_wlat) is : 2
-- read resynch phase calibration report:
-- calibrated centre of data valid window phase : 32
-- calibrated centre of data valid window size : 24
-- chosen address and command 1T delay: no 1T delay
-- poa 'dec' adjustments = 27
-- rdv 'dec' adjustments = 25
-- # -----------------------------------------------------------------------
--
-- Step 3 - Convert the text to bespoke instant on settings at the end of the
-- setup_instant_on function using the
-- override_instant_on function, note type is t_preset_cal
--
-- The mapping is as follows:
--
-- PHY read latency (ctl_rlat) is : 14 => rlat := 14
-- address/command to PHY write latency (ctl_wlat) is : 2 => wlat := 2
-- read resynch phase calibration report:
-- calibrated centre of data valid window phase : 32 => codvw_phase := 32
-- calibrated centre of data valid window size : 24 => codvw_size := 24
-- chosen address and command 1T delay: no 1T delay => ac_1t := '0'
-- poa 'dec' adjustments = 27 => poa_lat := 27
-- rdv 'dec' adjustments = 25 => rdv_lat := 25
--
-- Step 4 - Try running in REDUCE_SIM_TIME mode 1 (SUPERFAST mode)
--
-- Step 5 - If still fails observe the behaviour of the controller, for the
-- following symptoms:
-- - If first 2 beats of read data lost (POA enable too late) - inc poa_lat by 1 (poa_lat is number of POA decrements not actual latency)
-- - If last 2 beats of read data lost (POA enable too early) - dec poa_lat by 1
-- - If ctl_rdata_valid misaligned to ctl_rdata then alter number of RDV adjustments (rdv_lat)
-- - If write data is not 4-beat aligned (when written into memory) toggle ac_1t (HR only)
-- - If read data is not 4-beat aligned (but write data is) add 360 degrees to phase (PLL_STEPS_PER_CYCLE) mod 2*PLL_STEPS_PER_CYCLE (HR only)
--
-- Step 6 - If the above fails revert to REDUCE_SIM_TIME = 2 (FAST) mode
--
-- --------------------------------------------------------------------------
-- defaults
function defaults return t_preset_cal is
variable output : t_preset_cal;
begin
output.codvw_phase := 0;
output.codvw_size := 0;
output.wlat := 0;
output.rlat := 0;
output.rdv_lat := 0;
output.ac_1t := '1'; -- default on for FR
output.poa_lat := 0;
return output;
end function;
-- Functions to extract values from MR
-- return cl (for DDR memory 2*cl because of 1/2 cycle latencies)
procedure mr0_to_cl (memory_type : string;
mr0 : std_logic_vector(15 downto 0);
cl : out natural;
half_cl : out std_logic) is
variable v_cl : natural;
begin
half_cl := '0';
if memory_type = "DDR" then -- DDR memories
-- returns cl*2 because of 1/2 latencies
v_cl := to_integer(unsigned(mr0(5 downto 4)));
-- integer values of cl
if mr0(6) = '0' then
assert v_cl > 1 report record_report_prefix & "invalid cas latency for DDR memory, should be in range 1.5-3" severity failure;
end if;
if mr0(6) = '1' then
assert (v_cl = 1 or v_cl = 2) report record_report_prefix & "invalid cas latency for DDR memory, should be in range 1.5-3" severity failure;
half_cl := '1';
end if;
elsif memory_type = "DDR2" then -- DDR2 memories
v_cl := to_integer(unsigned(mr0(6 downto 4)));
-- sanity checks
assert (v_cl > 1 and v_cl < 7) report record_report_prefix & "invalid cas latency for DDR2 memory, should be in range 2-6 but equals " & integer'image(v_cl) severity failure;
elsif memory_type = "DDR3" then -- DDR3 memories
v_cl := to_integer(unsigned(mr0(6 downto 4)))+4;
--sanity checks
assert mr0(2) = '0' report record_report_prefix & "invalid cas latency for DDR3 memory, bit a2 in mr0 is set" severity failure;
assert v_cl /= 4 report record_report_prefix & "invalid cas latency for DDR3 memory, bits a6:4 set to zero" severity failure;
else
report record_report_prefix & "Undefined memory type " & memory_type severity failure;
end if;
cl := v_cl;
end procedure;
function mr1_to_al (memory_type : string;
mr1 : std_logic_vector(15 downto 0);
cl : natural) return natural is
variable al : natural;
begin
if memory_type = "DDR" then -- DDR memories
-- unsupported so return zero
al := 0;
elsif memory_type = "DDR2" then -- DDR2 memories
al := to_integer(unsigned(mr1(5 downto 3)));
assert al < 6 report record_report_prefix & "invalid additive latency for DDR2 memory, should be in range 0-5 but equals " & integer'image(al) severity failure;
elsif memory_type = "DDR3" then -- DDR3 memories
al := to_integer(unsigned(mr1(4 downto 3)));
assert al /= 3 report record_report_prefix & "invalid additive latency for DDR2 memory, should be in range 0-5 but equals " & integer'image(al) severity failure;
if al /= 0 then -- CL-1 or CL-2
al := cl - al;
end if;
else
report record_report_prefix & "Undefined memory type " & memory_type severity failure;
end if;
return al;
end function;
-- return cwl
function mr2_to_cwl (memory_type : string;
mr2 : std_logic_vector(15 downto 0);
cl : natural) return natural is
variable cwl : natural;
begin
if memory_type = "DDR" then -- DDR memories
cwl := 1;
elsif memory_type = "DDR2" then -- DDR2 memories
cwl := cl - 1;
elsif memory_type = "DDR3" then -- DDR3 memories
cwl := to_integer(unsigned(mr2(5 downto 3))) + 5;
--sanity checks
assert cwl < 9 report record_report_prefix & "invalid cas write latency for DDR3 memory, should be in range 5-8 but equals " & integer'image(cwl) severity failure;
else
report record_report_prefix & "Undefined memory type " & memory_type severity failure;
end if;
return cwl;
end function;
-- -----------------------------------
-- Functions to determine which family group
-- Include any family alias here
-- -----------------------------------
function is_siii(family_id : natural) return boolean is
begin
if family_id = 3 or family_id = 5 then
return true;
else
return false;
end if;
end function;
function is_ciii(family_id : natural) return boolean is
begin
if family_id = 2 then
return true;
else
return false;
end if;
end function;
function is_aii(family_id : natural) return boolean is
begin
if family_id = 4 then
return true;
else
return false;
end if;
end function;
function is_sii(family_id : natural) return boolean is
begin
if family_id = 1 then
return true;
else
return false;
end if;
end function;
-- -----------------------------------
-- Functions to lookup hardcoded values
-- on per family basis
-- DDR: CL = 3
-- DDR2: CL = 6, CWL = 5, AL = 0
-- DDR3: CL = 6, CWL = 5, AL = 0
-- -----------------------------------
-- default ac phase = 240
function siii_family_settings (dwidth_ratio : integer;
memory_type : string;
pll_steps : natural
) return t_preset_cal is
variable v_output : t_preset_cal;
begin
v_output := defaults;
if memory_type = "DDR" then -- CAS = 3
if dwidth_ratio = 2 then
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 15;
v_output.rdv_lat := 11;
v_output.poa_lat := 11;
else
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 15;
v_output.rdv_lat := 23;
v_output.ac_1t := '0';
v_output.poa_lat := 24;
end if;
elsif memory_type = "DDR2" then -- CAS = 6
if dwidth_ratio = 2 then
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 5;
v_output.rlat := 16;
v_output.rdv_lat := 10;
v_output.poa_lat := 8;
else
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 3;
v_output.rlat := 16;
v_output.rdv_lat := 21;
v_output.ac_1t := '0';
v_output.poa_lat := 22;
end if;
elsif memory_type = "DDR3" then -- HR only, CAS = 6
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 2;
v_output.rlat := 15;
v_output.rdv_lat := 23;
v_output.ac_1t := '0';
v_output.poa_lat := 24;
end if;
-- adapt settings for ac_phase (default 240 degrees so leave commented)
-- if dwidth_ratio = 2 then
-- v_output.wlat := v_output.wlat - 1;
-- v_output.rlat := v_output.rlat - 1;
-- v_output.rdv_lat := v_output.rdv_lat + 1;
-- v_output.poa_lat := v_output.poa_lat + 1;
-- else
-- v_output.ac_1t := not v_output.ac_1t;
-- end if;
v_output.codvw_size := pll_steps;
return v_output;
end function;
-- default ac phase = 90
function ciii_family_settings (dwidth_ratio : integer;
memory_type : string;
pll_steps : natural) return t_preset_cal is
variable v_output : t_preset_cal;
begin
v_output := defaults;
if memory_type = "DDR" then -- CAS = 3
if dwidth_ratio = 2 then
v_output.codvw_phase := 3*pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 15;
v_output.rdv_lat := 11;
v_output.poa_lat := 11; --unused
else
v_output.codvw_phase := 3*pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 13;
v_output.rdv_lat := 27;
v_output.ac_1t := '1';
v_output.poa_lat := 27; --unused
end if;
elsif memory_type = "DDR2" then -- CAS = 6
if dwidth_ratio = 2 then
v_output.codvw_phase := 3*pll_steps/4;
v_output.wlat := 5;
v_output.rlat := 18;
v_output.rdv_lat := 8;
v_output.poa_lat := 8; --unused
else
v_output.codvw_phase := pll_steps + 3*pll_steps/4;
v_output.wlat := 3;
v_output.rlat := 14;
v_output.rdv_lat := 25;
v_output.ac_1t := '1';
v_output.poa_lat := 25; --unused
end if;
end if;
-- adapt settings for ac_phase (hardcode for 90 degrees)
if dwidth_ratio = 2 then
v_output.wlat := v_output.wlat + 1;
v_output.rlat := v_output.rlat + 1;
v_output.rdv_lat := v_output.rdv_lat - 1;
v_output.poa_lat := v_output.poa_lat - 1;
else
v_output.ac_1t := not v_output.ac_1t;
end if;
v_output.codvw_size := pll_steps/2;
return v_output;
end function;
-- default ac phase = 90
function sii_family_settings (dwidth_ratio : integer;
memory_type : string;
pll_steps : natural) return t_preset_cal is
variable v_output : t_preset_cal;
begin
v_output := defaults;
if memory_type = "DDR" then -- CAS = 3
if dwidth_ratio = 2 then
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 15;
v_output.rdv_lat := 11;
v_output.poa_lat := 13;
else
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 13;
v_output.rdv_lat := 27;
v_output.ac_1t := '1';
v_output.poa_lat := 22;
end if;
elsif memory_type = "DDR2" then
if dwidth_ratio = 2 then
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 5;
v_output.rlat := 18;
v_output.rdv_lat := 8;
v_output.poa_lat := 10;
else
v_output.codvw_phase := pll_steps + pll_steps/4;
v_output.wlat := 3;
v_output.rlat := 14;
v_output.rdv_lat := 25;
v_output.ac_1t := '1';
v_output.poa_lat := 20;
end if;
end if;
-- adapt settings for ac_phase (hardcode for 90 degrees)
if dwidth_ratio = 2 then
v_output.wlat := v_output.wlat + 1;
v_output.rlat := v_output.rlat + 1;
v_output.rdv_lat := v_output.rdv_lat - 1;
v_output.poa_lat := v_output.poa_lat - 1;
else
v_output.ac_1t := not v_output.ac_1t;
end if;
v_output.codvw_size := pll_steps;
return v_output;
end function;
-- default ac phase = 90
function aii_family_settings (dwidth_ratio : integer;
memory_type : string;
pll_steps : natural) return t_preset_cal is
variable v_output : t_preset_cal;
begin
v_output := defaults;
if memory_type = "DDR" then -- CAS = 3
if dwidth_ratio = 2 then
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 16;
v_output.rdv_lat := 10;
v_output.poa_lat := 15;
else
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 13;
v_output.rdv_lat := 27;
v_output.ac_1t := '1';
v_output.poa_lat := 24;
end if;
elsif memory_type = "DDR2" then
if dwidth_ratio = 2 then
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 5;
v_output.rlat := 19;
v_output.rdv_lat := 9;
v_output.poa_lat := 12;
else
v_output.codvw_phase := pll_steps + pll_steps/4;
v_output.wlat := 3;
v_output.rlat := 14;
v_output.rdv_lat := 25;
v_output.ac_1t := '1';
v_output.poa_lat := 22;
end if;
elsif memory_type = "DDR3" then -- HR only, CAS = 6
v_output.codvw_phase := pll_steps + pll_steps/4;
v_output.wlat := 3;
v_output.rlat := 14;
v_output.rdv_lat := 25;
v_output.ac_1t := '1';
v_output.poa_lat := 22;
end if;
-- adapt settings for ac_phase (hardcode for 90 degrees)
if dwidth_ratio = 2 then
v_output.wlat := v_output.wlat + 1;
v_output.rlat := v_output.rlat + 1;
v_output.rdv_lat := v_output.rdv_lat - 1;
v_output.poa_lat := v_output.poa_lat - 1;
else
v_output.ac_1t := not v_output.ac_1t;
end if;
v_output.codvw_size := pll_steps;
return v_output;
end function;
function is_odd(num : integer) return boolean is
variable v_num : integer;
begin
v_num := num;
if v_num - (v_num/2)*2 = 0 then
return false;
else
return true;
end if;
end function;
------------------------------------------------
-- top level function to setup instant on mode
------------------------------------------------
function override_instant_on return t_preset_cal is
variable v_output : t_preset_cal;
begin
v_output := defaults;
-- add in overrides here
return v_output;
end function;
function setup_instant_on (sim_time_red : natural;
family_id : natural;
memory_type : string;
dwidth_ratio : natural;
pll_steps : natural;
mr0 : std_logic_vector(15 downto 0);
mr1 : std_logic_vector(15 downto 0);
mr2 : std_logic_vector(15 downto 0)) return t_preset_cal is
variable v_output : t_preset_cal;
variable v_cl : natural; -- cas latency
variable v_half_cl : std_logic; -- + 0.5 cycles (DDR only)
variable v_al : natural; -- additive latency (ddr2/ddr3 only)
variable v_cwl : natural; -- cas write latency (ddr3 only)
variable v_rl : integer range 0 to 15;
variable v_wl : integer;
variable v_delta_rl : integer range -10 to 10; -- from given defaults
variable v_delta_wl : integer; -- from given defaults
variable v_debug : boolean;
begin
v_debug := true;
v_output := defaults;
if sim_time_red = 1 then -- only set if STR equals 1
-- ----------------------------------------
-- extract required parameters from MRs
-- ----------------------------------------
mr0_to_cl(memory_type, mr0, v_cl, v_half_cl);
v_al := mr1_to_al(memory_type, mr1, v_cl);
v_cwl := mr2_to_cwl(memory_type, mr2, v_cl);
v_rl := v_cl + v_al;
v_wl := v_cwl + v_al;
if v_debug then
report record_report_prefix & "Extracted MR parameters" & LF &
"CAS = " & integer'image(v_cl) & LF &
"CWL = " & integer'image(v_cwl) & LF &
"AL = " & integer'image(v_al) & LF;
end if;
-- ----------------------------------------
-- apply per family, memory type and dwidth_ratio static setup
-- ----------------------------------------
if is_siii(family_id) then
v_output := siii_family_settings(dwidth_ratio, memory_type, pll_steps);
elsif is_ciii(family_id) then
v_output := ciii_family_settings(dwidth_ratio, memory_type, pll_steps);
elsif is_aii(family_id) then
v_output := aii_family_settings(dwidth_ratio, memory_type, pll_steps);
elsif is_sii(family_id) then
v_output := sii_family_settings(dwidth_ratio, memory_type, pll_steps);
end if;
-- ----------------------------------------
-- correct for different cwl, cl and al settings
-- ----------------------------------------
if memory_type = "DDR" then
v_delta_rl := v_rl - c_ddr_default_rl;
v_delta_wl := v_wl - c_ddr_default_wl;
elsif memory_type = "DDR2" then
v_delta_rl := v_rl - c_ddr2_default_rl;
v_delta_wl := v_wl - c_ddr2_default_wl;
else -- DDR3
v_delta_rl := v_rl - c_ddr3_default_rl;
v_delta_wl := v_wl - c_ddr3_default_wl;
end if;
if v_debug then
report record_report_prefix & "Extracted memory latency (and delta from default)" & LF &
"RL = " & integer'image(v_rl) & LF &
"WL = " & integer'image(v_wl) & LF &
"delta RL = " & integer'image(v_delta_rl) & LF &
"delta WL = " & integer'image(v_delta_wl) & LF;
end if;
if dwidth_ratio = 2 then
-- adjust rdp settings
v_output.rlat := v_output.rlat + v_delta_rl;
v_output.rdv_lat := v_output.rdv_lat - v_delta_rl;
v_output.poa_lat := v_output.poa_lat - v_delta_rl;
-- adjust wdp settings
v_output.wlat := v_output.wlat + v_delta_wl;
elsif dwidth_ratio = 4 then
-- adjust wdp settings
v_output.wlat := v_output.wlat + v_delta_wl/2;
if is_odd(v_delta_wl) then -- add / sub 1t write latency
-- toggle ac_1t in all cases
v_output.ac_1t := not v_output.ac_1t;
if v_delta_wl < 0 then -- sub 1 from latency
if v_output.ac_1t = '0' then -- phy_clk cc boundary
v_output.wlat := v_output.wlat - 1;
end if;
else -- add 1 to latency
if v_output.ac_1t = '1' then -- phy_clk cc boundary
v_output.wlat := v_output.wlat + 1;
end if;
end if;
-- update read latency
if v_output.ac_1t = '1' then -- added 1t to address/command so inc read_lat
v_delta_rl := v_delta_rl + 1;
else -- subtracted 1t from address/command so dec read_lat
v_delta_rl := v_delta_rl - 1;
end if;
end if;
-- adjust rdp settings
v_output.rlat := v_output.rlat + v_delta_rl/2;
v_output.rdv_lat := v_output.rdv_lat - v_delta_rl;
v_output.poa_lat := v_output.poa_lat - v_delta_rl;
if memory_type = "DDR3" then
if is_odd(v_delta_rl) xor is_odd(v_delta_wl) then
if is_aii(family_id) then
v_output.rdv_lat := v_output.rdv_lat - 1;
v_output.poa_lat := v_output.poa_lat - 1;
else
v_output.rdv_lat := v_output.rdv_lat + 1;
v_output.poa_lat := v_output.poa_lat + 1;
end if;
end if;
end if;
if is_odd(v_delta_rl) then
if v_delta_rl > 0 then -- add 1t
if v_output.codvw_phase < pll_steps then
v_output.codvw_phase := v_output.codvw_phase + pll_steps;
else
v_output.codvw_phase := v_output.codvw_phase - pll_steps;
v_output.rlat := v_output.rlat + 1;
end if;
else -- subtract 1t
if v_output.codvw_phase < pll_steps then
v_output.codvw_phase := v_output.codvw_phase + pll_steps;
v_output.rlat := v_output.rlat - 1;
else
v_output.codvw_phase := v_output.codvw_phase - pll_steps;
end if;
end if;
end if;
end if;
if v_half_cl = '1' and is_ciii(family_id) then
v_output.codvw_phase := v_output.codvw_phase - pll_steps/2;
end if;
end if;
return v_output;
end function;
--
END memphy_alt_mem_phy_record_pkg;
--/* Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your
-- use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any
-- output files any of the foregoing (including device programming or
-- simulation files), and any associated documentation or information are
-- expressly subject to the terms and conditions of the Altera Program
-- License Subscription Agreement or other applicable license agreement,
-- including, without limitation, that your use is for the sole purpose
-- of programming logic devices manufactured by Altera and sold by Altera
-- or its authorized distributors. Please refer to the applicable
-- agreement for further details. */
--
-- -----------------------------------------------------------------------------
-- Abstract : address and command package, shared between all variations of
-- the AFI sequencer
-- The address and command package (alt_mem_phy_addr_cmd_pkg) is
-- used to combine DRAM address and command signals in one record
-- and unify the functions operating on this record.
--
--
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--
package memphy_alt_mem_phy_addr_cmd_pkg is
-- the following are bounds on the maximum range of address and command signals
constant c_max_addr_bits : natural := 15;
constant c_max_ba_bits : natural := 3;
constant c_max_ranks : natural := 16;
constant c_max_mode_reg_bit : natural := 12;
constant c_max_cmds_per_clk : natural := 4; -- quarter rate
-- a prefix for all report signals to identify phy and sequencer block
--
constant ac_report_prefix : string := "memphy_alt_mem_phy_seq (addr_cmd_pkg) : ";
-- -------------------------------------------------------------
-- this record represents a single mem_clk command cycle
-- -------------------------------------------------------------
type t_addr_cmd is record
addr : natural range 0 to 2**c_max_addr_bits - 1;
ba : natural range 0 to 2**c_max_ba_bits - 1;
cas_n : boolean;
ras_n : boolean;
we_n : boolean;
cke : natural range 0 to 2**c_max_ranks - 1; -- bounded max of 8 ranks
cs_n : natural range 2**c_max_ranks - 1 downto 0; -- bounded max of 8 ranks
odt : natural range 0 to 2**c_max_ranks - 1; -- bounded max of 8 ranks
rst_n : boolean;
end record t_addr_cmd;
-- -------------------------------------------------------------
-- this vector is used to describe the fact that for slower clock domains
-- mutiple commands per clock can be issued and encapsulates all these options in a
-- type which can scale with rate
-- -------------------------------------------------------------
type t_addr_cmd_vector is array (natural range <>) of t_addr_cmd;
-- -------------------------------------------------------------
-- this record is used to define the memory interface type and allow packing and checking
-- (it should be used as a generic to a entity or from a poject level constant)
-- -------------------------------------------------------------
-- enumeration for mem_type
type t_mem_type is
(
DDR,
DDR2,
DDR3
);
-- memory interface configuration parameters
type t_addr_cmd_config_rec is record
num_addr_bits : natural;
num_ba_bits : natural;
num_cs_bits : natural;
num_ranks : natural;
cmds_per_clk : natural range 1 to c_max_cmds_per_clk; -- commands per clock cycle (equal to DWIDTH_RATIO/2)
mem_type : t_mem_type;
end record;
-- -----------------------------------
-- the following type is used to switch between signals
-- (for example, in the mask function below)
-- -----------------------------------
type t_addr_cmd_signals is
(
addr,
ba,
cas_n,
ras_n,
we_n,
cke,
cs_n,
odt,
rst_n
);
-- -----------------------------------
-- odt record
-- to hold the odt settings
-- (an odt_record) per rank (in odt_array)
-- -----------------------------------
type t_odt_record is record
write : natural;
read : natural;
end record t_odt_record;
type t_odt_array is array (natural range <>) of t_odt_record;
-- -------------------------------------------------------------
-- exposed functions and procedures
--
-- these functions cover the following memory types:
-- DDR3, DDR2, DDR
--
-- and the following operations:
-- MRS, REF, PRE, PREA, ACT,
-- WR, WRS8, WRS4, WRA, WRAS8, WRAS4,
-- RD, RDS8, RDS4, RDA, RDAS8, RDAS4,
--
-- for DDR3 on the fly burst length setting for reads/writes
-- is supported
-- -------------------------------------------------------------
function defaults ( config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd_vector;
function reset ( config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd_vector;
function int_pup_reset ( config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd_vector;
function deselect ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector
) return t_addr_cmd_vector;
function precharge_all ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function precharge_all ( config_rec : in t_addr_cmd_config_rec;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function precharge_bank ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1;
bank : in natural range 0 to 2**c_max_ba_bits -1
) return t_addr_cmd_vector;
function activate ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
bank : in natural range 0 to 2**c_max_ba_bits -1;
row : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks - 1
) return t_addr_cmd_vector;
function write ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
bank : in natural range 0 to 2**c_max_ba_bits -1;
col : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks - 1;
op_length : in natural range 1 to 8;
auto_prech : in boolean
) return t_addr_cmd_vector;
function read ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
bank : in natural range 0 to 2**c_max_ba_bits -1;
col : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks - 1;
op_length : in natural range 1 to 8;
auto_prech : in boolean
) return t_addr_cmd_vector;
function refresh ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function self_refresh_entry ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function load_mode ( config_rec : in t_addr_cmd_config_rec;
mode_register_num : in natural range 0 to 3;
mode_reg_value : in std_logic_vector(c_max_mode_reg_bit downto 0);
ranks : in natural range 0 to 2**c_max_ranks -1;
remap_addr_and_ba : in boolean
) return t_addr_cmd_vector;
function dll_reset ( config_rec : in t_addr_cmd_config_rec;
mode_reg_val : in std_logic_vector;
rank_num : in natural range 0 to 2**c_max_ranks - 1;
reorder_addr_bits : in boolean
) return t_addr_cmd_vector;
function enter_sr_pd_mode ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function maintain_pd_or_sr ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function exit_sr_pd_mode ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function ZQCS ( config_rec : in t_addr_cmd_config_rec;
rank : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function ZQCL ( config_rec : in t_addr_cmd_config_rec;
rank : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function all_unreversed_ranks ( config_rec : in t_addr_cmd_config_rec;
record_to_mask : in t_addr_cmd_vector;
mem_ac_swapped_ranks : in std_logic_vector
) return t_addr_cmd_vector;
function all_reversed_ranks ( config_rec : in t_addr_cmd_config_rec;
record_to_mask : in t_addr_cmd_vector;
mem_ac_swapped_ranks : in std_logic_vector
) return t_addr_cmd_vector;
function program_rdimm_register ( config_rec : in t_addr_cmd_config_rec;
control_word_addr : in std_logic_vector(3 downto 0);
control_word_data : in std_logic_vector(3 downto 0)
) return t_addr_cmd_vector;
-- -------------------------------------------------------------
-- the following function sets up the odt settings
-- NOTES: currently only supports DDR/DDR2 memories
-- -------------------------------------------------------------
-- odt setting as implemented in the altera high-performance controller for ddr2 memories
function set_odt_values (ranks : natural;
ranks_per_slot : natural;
mem_type : in string
) return t_odt_array;
-- -------------------------------------------------------------
-- the following function enables assignment to the constant config_rec
-- -------------------------------------------------------------
function set_config_rec ( num_addr_bits : in natural;
num_ba_bits : in natural;
num_cs_bits : in natural;
num_ranks : in natural;
dwidth_ratio : in natural range 1 to c_max_cmds_per_clk;
mem_type : in string
) return t_addr_cmd_config_rec;
-- The non-levelled sequencer doesn't make a distinction between CS_WIDTH and NUM_RANKS. In this case,
-- just set the two to be the same.
function set_config_rec ( num_addr_bits : in natural;
num_ba_bits : in natural;
num_cs_bits : in natural;
dwidth_ratio : in natural range 1 to c_max_cmds_per_clk;
mem_type : in string
) return t_addr_cmd_config_rec;
-- -------------------------------------------------------------
-- the following function and procedure unpack address and
-- command signals from the t_addr_cmd_vector format
-- -------------------------------------------------------------
procedure unpack_addr_cmd_vector( addr_cmd_vector : in t_addr_cmd_vector;
config_rec : in t_addr_cmd_config_rec;
addr : out std_logic_vector;
ba : out std_logic_vector;
cas_n : out std_logic_vector;
ras_n : out std_logic_vector;
we_n : out std_logic_vector;
cke : out std_logic_vector;
cs_n : out std_logic_vector;
odt : out std_logic_vector;
rst_n : out std_logic_vector);
procedure unpack_addr_cmd_vector( config_rec : in t_addr_cmd_config_rec;
addr_cmd_vector : in t_addr_cmd_vector;
signal addr : out std_logic_vector;
signal ba : out std_logic_vector;
signal cas_n : out std_logic_vector;
signal ras_n : out std_logic_vector;
signal we_n : out std_logic_vector;
signal cke : out std_logic_vector;
signal cs_n : out std_logic_vector;
signal odt : out std_logic_vector;
signal rst_n : out std_logic_vector);
-- -------------------------------------------------------------
-- the following functions perform bit masking to 0 or 1 (as
-- specified by mask_value) to a chosen address/command signal (signal_name)
-- across all signal bits or to a selected bit (mask_bit)
-- -------------------------------------------------------------
-- mask all signal bits procedure
function mask ( config_rec : in t_addr_cmd_config_rec;
addr_cmd_vector : in t_addr_cmd_vector;
signal_name : in t_addr_cmd_signals;
mask_value : in std_logic) return t_addr_cmd_vector;
procedure mask( config_rec : in t_addr_cmd_config_rec;
signal addr_cmd_vector : inout t_addr_cmd_vector;
signal_name : in t_addr_cmd_signals;
mask_value : in std_logic);
-- mask signal bit (mask_bit) procedure
function mask ( config_rec : in t_addr_cmd_config_rec;
addr_cmd_vector : in t_addr_cmd_vector;
signal_name : in t_addr_cmd_signals;
mask_value : in std_logic;
mask_bit : in natural) return t_addr_cmd_vector;
--
end memphy_alt_mem_phy_addr_cmd_pkg;
--
package body memphy_alt_mem_phy_addr_cmd_pkg IS
-- -------------------------------------------------------------
-- Basic functions for a single command
-- -------------------------------------------------------------
-- -------------------------------------------------------------
-- defaults the bus no JEDEC abbreviated name
-- -------------------------------------------------------------
function defaults ( config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval.addr := 0;
v_retval.ba := 0;
v_retval.cas_n := false;
v_retval.ras_n := false;
v_retval.we_n := false;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1;
v_retval.odt := 0;
v_retval.rst_n := false;
return v_retval;
end function;
-- -------------------------------------------------------------
-- resets the addr/cmd signal (Same as default with cke and rst_n 0 )
-- -------------------------------------------------------------
function reset ( config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval := defaults(config_rec);
v_retval.cke := 0;
if config_rec.mem_type = DDR3 then
v_retval.rst_n := true;
end if;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues deselect (command) JEDEC abbreviated name: DES
-- -------------------------------------------------------------
function deselect ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval := previous;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.rst_n := false;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a precharge all command JEDEC abbreviated name: PREA
-- -------------------------------------------------------------
function precharge_all( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable v_addr : unsigned( c_max_addr_bits -1 downto 0);
begin
v_retval := previous;
v_addr := to_unsigned(previous.addr, c_max_addr_bits);
v_addr(10) := '1'; -- set AP bit high
v_retval.addr := to_integer(v_addr);
v_retval.ras_n := true;
v_retval.cas_n := false;
v_retval.we_n := true;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) - 1 - ranks;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.rst_n := false;
return v_retval;
end function;
-- -------------------------------------------------------------
-- precharge (close) a bank JEDEC abbreviated name: PRE
-- -------------------------------------------------------------
function precharge_bank( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd;
ranks : in natural range 0 to 2**c_max_ranks -1;
bank : in natural range 0 to 2**c_max_ba_bits -1
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable v_addr : unsigned( c_max_addr_bits -1 downto 0);
begin
v_retval := previous;
v_addr := to_unsigned(previous.addr, c_max_addr_bits);
v_addr(10) := '0'; -- set AP bit low
v_retval.addr := to_integer(v_addr);
v_retval.ba := bank;
v_retval.ras_n := true;
v_retval.cas_n := false;
v_retval.we_n := true;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) - ranks;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.rst_n := false;
return v_retval;
end function;
-- -------------------------------------------------------------
-- Issues a activate (open row) JEDEC abbreviated name: ACT
-- -------------------------------------------------------------
function activate (config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd;
bank : in natural range 0 to 2**c_max_ba_bits - 1;
row : in natural range 0 to 2**c_max_addr_bits - 1;
ranks : in natural range 0 to 2**c_max_ranks - 1
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval.addr := row;
v_retval.ba := bank;
v_retval.cas_n := false;
v_retval.ras_n := true;
v_retval.we_n := false;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1 - ranks;
v_retval.odt := previous.odt;
v_retval.rst_n := false;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a write command JEDEC abbreviated name:WR, WRA
-- WRS4, WRAS4
-- WRS8, WRAS8
-- has the ability to support:
-- DDR3:
-- BL4, BL8, fixed BL
-- Auto Precharge (AP)
-- DDR2, DDR:
-- fixed BL
-- Auto Precharge (AP)
-- -------------------------------------------------------------
function write (config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd;
bank : in natural range 0 to 2**c_max_ba_bits -1;
col : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks -1;
op_length : in natural range 1 to 8;
auto_prech : in boolean
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable v_addr : unsigned(c_max_addr_bits-1 downto 0);
begin
-- calculate correct address signal
v_addr := to_unsigned(col, c_max_addr_bits);
-- note pin A10 is used for AP, therfore shift the value from A10 onto A11.
v_retval.addr := to_integer(v_addr(9 downto 0));
if v_addr(10) = '1' then
v_retval.addr := v_retval.addr + 2**11;
end if;
if auto_prech = true then -- set AP bit (A10)
v_retval.addr := v_retval.addr + 2**10;
end if;
if config_rec.mem_type = DDR3 then
if op_length = 8 then -- set BL_OTF sel bit (A12)
v_retval.addr := v_retval.addr + 2**12;
elsif op_length = 4 then
null;
else
report ac_report_prefix & "DDR3 DRAM only supports writes of burst length 4 or 8, the requested length was: " & integer'image(op_length) severity failure;
end if;
elsif config_rec.mem_type = DDR2 or config_rec.mem_type = DDR then
null;
else
report ac_report_prefix & "only DDR memories are supported for memory writes" severity failure;
end if;
-- set a/c signal assignments for write
v_retval.ba := bank;
v_retval.cas_n := true;
v_retval.ras_n := false;
v_retval.we_n := true;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1 - ranks;
v_retval.odt := ranks;
v_retval.rst_n := false;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a read command JEDEC abbreviated name: RD, RDA
-- RDS4, RDAS4
-- RDS8, RDAS8
-- has the ability to support:
-- DDR3:
-- BL4, BL8, fixed BL
-- Auto Precharge (AP)
-- DDR2, DDR:
-- fixed BL, Auto Precharge (AP)
-- -------------------------------------------------------------
function read (config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd;
bank : in natural range 0 to 2**c_max_ba_bits -1;
col : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks -1;
op_length : in natural range 1 to 8;
auto_prech : in boolean
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable v_addr : unsigned(c_max_addr_bits-1 downto 0);
begin
-- calculate correct address signal
v_addr := to_unsigned(col, c_max_addr_bits);
-- note pin A10 is used for AP, therfore shift the value from A10 onto A11.
v_retval.addr := to_integer(v_addr(9 downto 0));
if v_addr(10) = '1' then
v_retval.addr := v_retval.addr + 2**11;
end if;
if auto_prech = true then -- set AP bit (A10)
v_retval.addr := v_retval.addr + 2**10;
end if;
if config_rec.mem_type = DDR3 then
if op_length = 8 then -- set BL_OTF sel bit (A12)
v_retval.addr := v_retval.addr + 2**12;
elsif op_length = 4 then
null;
else
report ac_report_prefix & "DDR3 DRAM only supports reads of burst length 4 or 8" severity failure;
end if;
elsif config_rec.mem_type = DDR2 or config_rec.mem_type = DDR then
null;
else
report ac_report_prefix & "only DDR memories are supported for memory reads" severity failure;
end if;
-- set a/c signals for read command
v_retval.ba := bank;
v_retval.cas_n := true;
v_retval.ras_n := false;
v_retval.we_n := false;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1 - ranks;
v_retval.odt := 0;
v_retval.rst_n := false;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a refresh command JEDEC abbreviated name: REF
-- -------------------------------------------------------------
function refresh (config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd;
ranks : in natural range 0 to 2**c_max_ranks -1
)
return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval := previous;
v_retval.cas_n := true;
v_retval.ras_n := true;
v_retval.we_n := false;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1 - ranks;
v_retval.rst_n := false;
-- addr, BA and ODT are don't care therfore leave as previous value
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a mode register set command JEDEC abbreviated name: MRS
-- -------------------------------------------------------------
function load_mode ( config_rec : in t_addr_cmd_config_rec;
mode_register_num : in natural range 0 to 3;
mode_reg_value : in std_logic_vector(c_max_mode_reg_bit downto 0);
ranks : in natural range 0 to 2**c_max_ranks -1;
remap_addr_and_ba : in boolean
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable v_addr_remap : unsigned(c_max_mode_reg_bit downto 0);
begin
v_retval.cas_n := true;
v_retval.ras_n := true;
v_retval.we_n := true;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1 - ranks;
v_retval.odt := 0;
v_retval.rst_n := false;
v_retval.ba := mode_register_num;
v_retval.addr := to_integer(unsigned(mode_reg_value));
if remap_addr_and_ba = true then
v_addr_remap := unsigned(mode_reg_value);
v_addr_remap(8 downto 7) := v_addr_remap(7) & v_addr_remap(8);
v_addr_remap(6 downto 5) := v_addr_remap(5) & v_addr_remap(6);
v_addr_remap(4 downto 3) := v_addr_remap(3) & v_addr_remap(4);
v_retval.addr := to_integer(v_addr_remap);
v_addr_remap := to_unsigned(mode_register_num, c_max_mode_reg_bit + 1);
v_addr_remap(1 downto 0) := v_addr_remap(0) & v_addr_remap(1);
v_retval.ba := to_integer(v_addr_remap);
end if;
return v_retval;
end function;
-- -------------------------------------------------------------
-- maintains SR or PD mode on slected ranks.
-- -------------------------------------------------------------
function maintain_pd_or_sr (config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd;
ranks : in natural range 0 to 2**c_max_ranks -1
)
return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval := previous;
v_retval.cke := (2 ** config_rec.num_ranks) - 1 - ranks;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a ZQ cal (short) JEDEC abbreviated name: ZQCS
-- NOTE - can only be issued to a single RANK at a time.
-- -------------------------------------------------------------
function ZQCS (config_rec : in t_addr_cmd_config_rec;
rank : in natural range 0 to 2**c_max_ranks -1
)
return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval.cas_n := false;
v_retval.ras_n := false;
v_retval.we_n := true;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1 - rank;
v_retval.rst_n := false;
v_retval.addr := 0; -- clear bit 10
v_retval.ba := 0;
v_retval.odt := 0;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a ZQ cal (long) JEDEC abbreviated name: ZQCL
-- NOTE - can only be issued to a single RANK at a time.
-- -------------------------------------------------------------
function ZQCL (config_rec : in t_addr_cmd_config_rec;
rank : in natural range 0 to 2**c_max_ranks -1
)
return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval.cas_n := false;
v_retval.ras_n := false;
v_retval.we_n := true;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1 - rank;
v_retval.rst_n := false;
v_retval.addr := 1024; -- set bit 10
v_retval.ba := 0;
v_retval.odt := 0;
return v_retval;
end function;
-- -------------------------------------------------------------
-- functions acting on all clock cycles from whatever rate
-- in halfrate clock domain issues 1 command per clock
-- in quarter rate issues 1 command per clock
-- In the above cases they will be correctly aligned using the
-- ALTMEMPHY 2T and 4T SDC
-- -------------------------------------------------------------
-- -------------------------------------------------------------
-- defaults the bus no JEDEC abbreviated name
-- -------------------------------------------------------------
function defaults (config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
v_retval := (others => defaults(config_rec));
return v_retval;
end function;
-- -------------------------------------------------------------
-- resets the addr/cmd signal (same as default with cke 0)
-- -------------------------------------------------------------
function reset (config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
v_retval := (others => reset(config_rec));
return v_retval;
end function;
function int_pup_reset (config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd_vector
is
variable v_addr_cmd_config_rst : t_addr_cmd_config_rec;
begin
v_addr_cmd_config_rst := config_rec;
v_addr_cmd_config_rst.num_ranks := c_max_ranks;
return reset(v_addr_cmd_config_rst);
end function;
-- -------------------------------------------------------------
-- issues a deselect command JEDEC abbreviated name: DES
-- -------------------------------------------------------------
function deselect ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector
) return t_addr_cmd_vector
is
alias a_previous : t_addr_cmd_vector(previous'range) is previous;
variable v_retval : t_addr_cmd_vector(a_previous'range);
begin
for rate in a_previous'range loop
v_retval(rate) := deselect(config_rec, a_previous(a_previous'high));
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a precharge all command JEDEC abbreviated name: PREA
-- -------------------------------------------------------------
function precharge_all ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector
is
alias a_previous : t_addr_cmd_vector(previous'range) is previous;
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
for rate in a_previous'range loop
v_retval(rate) := precharge_all(config_rec, previous(a_previous'high), ranks);
-- use dwidth_ratio/2 as in FR = 0 , HR = 1, and in future QR = 2 tCK setup + 1 tCK hold
if rate /= config_rec.cmds_per_clk/2 then
v_retval(rate).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- precharge (close) a bank JEDEC abbreviated name: PRE
-- -------------------------------------------------------------
function precharge_bank ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1;
bank : in natural range 0 to 2**c_max_ba_bits -1
) return t_addr_cmd_vector
is
alias a_previous : t_addr_cmd_vector(previous'range) is previous;
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
for rate in a_previous'range loop
v_retval(rate) := precharge_bank(config_rec, previous(a_previous'high), ranks, bank);
-- use dwidth_ratio/2 as in FR = 0 , HR = 1, and in future QR = 2 tCK setup + 1 tCK hold
if rate /= config_rec.cmds_per_clk/2 then
v_retval(rate).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a activate (open row) JEDEC abbreviated name: ACT
-- -------------------------------------------------------------
function activate ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
bank : in natural range 0 to 2**c_max_ba_bits -1;
row : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks - 1
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
for rate in previous'range loop
v_retval(rate) := activate(config_rec, previous(previous'high), bank, row, ranks);
-- use dwidth_ratio/2 as in FR = 0 , HR = 1, and in future QR = 2 tCK setup + 1 tCK hold
if rate /= config_rec.cmds_per_clk/2 then
v_retval(rate).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a write command JEDEC abbreviated name:WR, WRA
-- WRS4, WRAS4
-- WRS8, WRAS8
--
-- has the ability to support:
-- DDR3:
-- BL4, BL8, fixed BL
-- Auto Precharge (AP)
-- DDR2, DDR:
-- fixed BL
-- Auto Precharge (AP)
-- -------------------------------------------------------------
function write ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
bank : in natural range 0 to 2**c_max_ba_bits -1;
col : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks - 1;
op_length : in natural range 1 to 8;
auto_prech : in boolean
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
for rate in previous'range loop
v_retval(rate) := write(config_rec, previous(previous'high), bank, col, ranks, op_length, auto_prech);
-- use dwidth_ratio/2 as in FR = 0 , HR = 1, and in future QR = 2 tCK setup + 1 tCK hold
if rate /= config_rec.cmds_per_clk/2 then
v_retval(rate).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a read command JEDEC abbreviated name: RD, RDA
-- RDS4, RDAS4
-- RDS8, RDAS8
-- has the ability to support:
-- DDR3:
-- BL4, BL8, fixed BL
-- Auto Precharge (AP)
-- DDR2, DDR:
-- fixed BL, Auto Precharge (AP)
-- -------------------------------------------------------------
function read ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
bank : in natural range 0 to 2**c_max_ba_bits -1;
col : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks - 1;
op_length : in natural range 1 to 8;
auto_prech : in boolean
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
for rate in previous'range loop
v_retval(rate) := read(config_rec, previous(previous'high), bank, col, ranks, op_length, auto_prech);
-- use dwidth_ratio/2 as in FR = 0 , HR = 1, and in future QR = 2 tCK setup + 1 tCK hold
if rate /= config_rec.cmds_per_clk/2 then
v_retval(rate).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a refresh command JEDEC abbreviated name: REF
-- -------------------------------------------------------------
function refresh (config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
)return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
for rate in previous'range loop
v_retval(rate) := refresh(config_rec, previous(previous'high), ranks);
if rate /= config_rec.cmds_per_clk/2 then
v_retval(rate).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a self_refresh_entry command JEDEC abbreviated name: SRE
-- -------------------------------------------------------------
function self_refresh_entry (config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
)return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
v_retval := enter_sr_pd_mode(config_rec, refresh(config_rec, previous, ranks), ranks);
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a self_refresh exit or power_down exit command
-- JEDEC abbreviated names: SRX, PDX
-- -------------------------------------------------------------
function exit_sr_pd_mode ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
variable v_mask_workings : std_logic_vector(config_rec.num_ranks -1 downto 0);
variable v_mask_workings_b : std_logic_vector(config_rec.num_ranks -1 downto 0);
begin
v_retval := maintain_pd_or_sr(config_rec, previous, ranks);
v_mask_workings_b := std_logic_vector(to_unsigned(ranks, config_rec.num_ranks));
for rate in 0 to config_rec.cmds_per_clk - 1 loop
v_mask_workings := std_logic_vector(to_unsigned(v_retval(rate).cke, config_rec.num_ranks));
for i in v_mask_workings_b'range loop
v_mask_workings(i) := v_mask_workings(i) or v_mask_workings_b(i);
end loop;
if rate >= config_rec.cmds_per_clk / 2 then -- maintain command but clear CS of subsequenct command slots
v_retval(rate).cke := to_integer(unsigned(v_mask_workings)); -- almost irrelevant. but optimises logic slightly for Quater rate
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- cause the selected ranks to enter Self-refresh or Powerdown mode
-- JEDEC abbreviated names: PDE,
-- SRE (if a refresh is concurrently issued to the same ranks)
-- -------------------------------------------------------------
function enter_sr_pd_mode ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
variable v_mask_workings : std_logic_vector(config_rec.num_ranks -1 downto 0);
variable v_mask_workings_b : std_logic_vector(config_rec.num_ranks -1 downto 0);
begin
v_retval := previous;
v_mask_workings_b := std_logic_vector(to_unsigned(ranks, config_rec.num_ranks));
for rate in 0 to config_rec.cmds_per_clk - 1 loop
if rate >= config_rec.cmds_per_clk / 2 then -- maintain command but clear CS of subsequenct command slots
v_mask_workings := std_logic_vector(to_unsigned(v_retval(rate).cke, config_rec.num_ranks));
for i in v_mask_workings_b'range loop
v_mask_workings(i) := v_mask_workings(i) and not v_mask_workings_b(i);
end loop;
v_retval(rate).cke := to_integer(unsigned(v_mask_workings)); -- almost irrelevant. but optimises logic slightly for Quater rate
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- Issues a mode register set command JEDEC abbreviated name: MRS
-- -------------------------------------------------------------
function load_mode ( config_rec : in t_addr_cmd_config_rec;
mode_register_num : in natural range 0 to 3;
mode_reg_value : in std_logic_vector(c_max_mode_reg_bit downto 0);
ranks : in natural range 0 to 2**c_max_ranks -1;
remap_addr_and_ba : in boolean
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
v_retval := (others => load_mode(config_rec, mode_register_num, mode_reg_value, ranks, remap_addr_and_ba));
for rate in v_retval'range loop
if rate /= config_rec.cmds_per_clk/2 then
v_retval(rate).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- maintains SR or PD mode on slected ranks.
-- NOTE: does not affect previous command
-- -------------------------------------------------------------
function maintain_pd_or_sr ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
for command in v_retval'range loop
v_retval(command) := maintain_pd_or_sr(config_rec, previous(command), ranks);
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a ZQ cal (long) JEDEC abbreviated name: ZQCL
-- NOTE - can only be issued to a single RANK ata a time.
-- -------------------------------------------------------------
function ZQCL ( config_rec : in t_addr_cmd_config_rec;
rank : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1) := defaults(config_rec);
begin
for command in v_retval'range loop
v_retval(command) := ZQCL(config_rec, rank);
if command * 2 /= config_rec.cmds_per_clk then
v_retval(command).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a ZQ cal (short) JEDEC abbreviated name: ZQCS
-- NOTE - can only be issued to a single RANK ata a time.
-- -------------------------------------------------------------
function ZQCS ( config_rec : in t_addr_cmd_config_rec;
rank : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1) := defaults(config_rec);
begin
for command in v_retval'range loop
v_retval(command) := ZQCS(config_rec, rank);
if command * 2 /= config_rec.cmds_per_clk then
v_retval(command).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- ----------------------
-- Additional Rank manipulation functions (main use DDR3)
-- -------------
-- -----------------------------------
-- set the chip select for a group of ranks
-- -----------------------------------
function all_reversed_ranks ( config_rec : in t_addr_cmd_config_rec;
record_to_mask : in t_addr_cmd;
mem_ac_swapped_ranks : in std_logic_vector
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable v_mask_workings : std_logic_vector(config_rec.num_cs_bits-1 downto 0);
begin
v_retval := record_to_mask;
v_mask_workings := std_logic_vector(to_unsigned(record_to_mask.cs_n, config_rec.num_cs_bits));
for i in mem_ac_swapped_ranks'range loop
v_mask_workings(i):= v_mask_workings(i) or not mem_ac_swapped_ranks(i);
end loop;
v_retval.cs_n := to_integer(unsigned(v_mask_workings));
return v_retval;
end function;
-- -----------------------------------
-- inverse of the above
-- -----------------------------------
function all_unreversed_ranks ( config_rec : in t_addr_cmd_config_rec;
record_to_mask : in t_addr_cmd;
mem_ac_swapped_ranks : in std_logic_vector
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable v_mask_workings : std_logic_vector(config_rec.num_cs_bits-1 downto 0);
begin
v_retval := record_to_mask;
v_mask_workings := std_logic_vector(to_unsigned(record_to_mask.cs_n, config_rec.num_cs_bits));
for i in mem_ac_swapped_ranks'range loop
v_mask_workings(i):= v_mask_workings(i) or mem_ac_swapped_ranks(i);
end loop;
v_retval.cs_n := to_integer(unsigned(v_mask_workings));
return v_retval;
end function;
-- -----------------------------------
-- set the chip select for a group of ranks in a way which handles diffrent rates
-- -----------------------------------
function all_unreversed_ranks ( config_rec : in t_addr_cmd_config_rec;
record_to_mask : in t_addr_cmd_vector;
mem_ac_swapped_ranks : in std_logic_vector
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1) := defaults(config_rec);
begin
for command in record_to_mask'range loop
v_retval(command) := all_unreversed_ranks(config_rec, record_to_mask(command), mem_ac_swapped_ranks);
end loop;
return v_retval;
end function;
-- -----------------------------------
-- inverse of the above handling ranks
-- -----------------------------------
function all_reversed_ranks ( config_rec : in t_addr_cmd_config_rec;
record_to_mask : in t_addr_cmd_vector;
mem_ac_swapped_ranks : in std_logic_vector
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1) := defaults(config_rec);
begin
for command in record_to_mask'range loop
v_retval(command) := all_reversed_ranks(config_rec, record_to_mask(command), mem_ac_swapped_ranks);
end loop;
return v_retval;
end function;
-- --------------------------------------------------
-- Program a single control word onto RDIMM.
-- This is accomplished rather goofily by asserting all chip selects
-- and then writing out both the addr/data of the word onto the addr/ba bus
-- --------------------------------------------------
function program_rdimm_register ( config_rec : in t_addr_cmd_config_rec;
control_word_addr : in std_logic_vector(3 downto 0);
control_word_data : in std_logic_vector(3 downto 0)
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable ba : std_logic_vector(2 downto 0);
variable addr : std_logic_vector(4 downto 0);
begin
v_retval := defaults(config_rec);
v_retval.cs_n := 0;
ba := control_word_addr(3) & control_word_data(3) & control_word_data(2);
v_retval.ba := to_integer(unsigned(ba));
addr := control_word_data(1) & control_word_data(0) & control_word_addr(2) &
control_word_addr(1) & control_word_addr(0);
v_retval.addr := to_integer(unsigned(addr));
return v_retval;
end function;
function program_rdimm_register ( config_rec : in t_addr_cmd_config_rec;
control_word_addr : in std_logic_vector(3 downto 0);
control_word_data : in std_logic_vector(3 downto 0)
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
v_retval := (others => program_rdimm_register(config_rec, control_word_addr, control_word_data));
return v_retval;
end function;
-- --------------------------------------------------
-- overloaded functions, to simplify use, or provide simplified functionality
-- --------------------------------------------------
-- ----------------------------------------------------
-- Precharge all, defaulting all bits.
-- ----------------------------------------------------
function precharge_all ( config_rec : in t_addr_cmd_config_rec;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1) := defaults(config_rec);
begin
v_retval := precharge_all(config_rec, v_retval, ranks);
return v_retval;
end function;
-- ----------------------------------------------------
-- perform DLL reset through mode registers
-- ----------------------------------------------------
function dll_reset ( config_rec : in t_addr_cmd_config_rec;
mode_reg_val : in std_logic_vector;
rank_num : in natural range 0 to 2**c_max_ranks - 1;
reorder_addr_bits : in boolean
) return t_addr_cmd_vector is
variable int_mode_reg : std_logic_vector(mode_reg_val'range);
variable output : t_addr_cmd_vector(0 to config_rec.cmds_per_clk - 1);
begin
int_mode_reg := mode_reg_val;
int_mode_reg(8) := '1'; -- set DLL reset bit.
output := load_mode(config_rec, 0, int_mode_reg, rank_num, reorder_addr_bits);
return output;
end function;
-- -------------------------------------------------------------
-- package configuration functions
-- -------------------------------------------------------------
-- -------------------------------------------------------------
-- the following function sets up the odt settings
-- NOTES: supports DDR/DDR2/DDR3 SDRAM memories
-- -------------------------------------------------------------
function set_odt_values (ranks : natural;
ranks_per_slot : natural;
mem_type : in string
) return t_odt_array is
variable v_num_slots : natural;
variable v_cs : natural range 0 to ranks-1;
variable v_odt_values : t_odt_array(0 to ranks-1);
variable v_cs_addr : unsigned(ranks-1 downto 0);
begin
if mem_type = "DDR" then
-- ODT not supported for DDR memory so set default off
for v_cs in 0 to ranks-1 loop
v_odt_values(v_cs).write := 0;
v_odt_values(v_cs).read := 0;
end loop;
elsif mem_type = "DDR2" then
-- odt setting as implemented in the altera high-performance controller for ddr2 memories
assert (ranks rem ranks_per_slot = 0) report ac_report_prefix & "number of ranks per slot must be a multiple of number of ranks" severity failure;
v_num_slots := ranks/ranks_per_slot;
if v_num_slots = 1 then
-- special condition for 1 slot (i.e. DIMM) (2^n, n=0,1,2,... ranks only)
-- set odt on one chip for writes and no odt for reads
for v_cs in 0 to ranks-1 loop
v_odt_values(v_cs).write := 2**v_cs; -- on on the rank being written to
v_odt_values(v_cs).read := 0;
end loop;
else
-- if > 1 slot, set 1 odt enable on neighbouring slot for read and write
-- as an example consider the below for 4 slots with 2 ranks per slot
-- access to CS[0] or CS[1], enable ODT[2] or ODT[3]
-- access to CS[2] or CS[3], enable ODT[0] or ODT[1]
-- access to CS[4] or CS[5], enable ODT[6] or ODT[7]
-- access to CS[6] or CS[7], enable ODT[4] or ODT[5]
-- the logic below implements the above for varying ranks and ranks_per slot
-- under the condition that ranks/ranks_per_slot is integer
for v_cs in 0 to ranks-1 loop
v_cs_addr := to_unsigned(v_cs, ranks);
v_cs_addr(ranks_per_slot-1) := not v_cs_addr(ranks_per_slot-1);
v_odt_values(v_cs).write := 2**to_integer(v_cs_addr);
v_odt_values(v_cs).read := v_odt_values(v_cs).write;
end loop;
end if;
elsif mem_type = "DDR3" then
assert (ranks rem ranks_per_slot = 0) report ac_report_prefix & "number of ranks per slot must be a multiple of number of ranks" severity failure;
v_num_slots := ranks/ranks_per_slot;
if v_num_slots = 1 then
-- special condition for 1 slot (i.e. DIMM) (2^n, n=0,1,2,... ranks only)
-- set odt on one chip for writes and no odt for reads
for v_cs in 0 to ranks-1 loop
v_odt_values(v_cs).write := 2**v_cs; -- on on the rank being written to
v_odt_values(v_cs).read := 0;
end loop;
else
-- if > 1 slot, set 1 odt enable on neighbouring slot for read and write
-- as an example consider the below for 4 slots with 2 ranks per slot
-- access to CS[0] or CS[1], enable ODT[2] or ODT[3]
-- access to CS[2] or CS[3], enable ODT[0] or ODT[1]
-- access to CS[4] or CS[5], enable ODT[6] or ODT[7]
-- access to CS[6] or CS[7], enable ODT[4] or ODT[5]
-- the logic below implements the above for varying ranks and ranks_per slot
-- under the condition that ranks/ranks_per_slot is integer
for v_cs in 0 to ranks-1 loop
v_cs_addr := to_unsigned(v_cs, ranks);
v_cs_addr(ranks_per_slot-1) := not v_cs_addr(ranks_per_slot-1);
v_odt_values(v_cs).write := 2**to_integer(v_cs_addr) + 2**(v_cs); -- turn on a neighbouring slots cs and current rank being written to
v_odt_values(v_cs).read := 2**to_integer(v_cs_addr);
end loop;
end if;
else
report ac_report_prefix & "unknown mem_type specified in the set_odt_values function in addr_cmd_pkg package" severity failure;
end if;
return v_odt_values;
end function;
-- -----------------------------------------------------------
-- set constant values to config_rec
-- ----------------------------------------------------------
function set_config_rec ( num_addr_bits : in natural;
num_ba_bits : in natural;
num_cs_bits : in natural;
num_ranks : in natural;
dwidth_ratio : in natural range 1 to c_max_cmds_per_clk;
mem_type : in string
) return t_addr_cmd_config_rec
is
variable v_config_rec : t_addr_cmd_config_rec;
begin
v_config_rec.num_addr_bits := num_addr_bits;
v_config_rec.num_ba_bits := num_ba_bits;
v_config_rec.num_cs_bits := num_cs_bits;
v_config_rec.num_ranks := num_ranks;
v_config_rec.cmds_per_clk := dwidth_ratio/2;
if mem_type = "DDR" then
v_config_rec.mem_type := DDR;
elsif mem_type = "DDR2" then
v_config_rec.mem_type := DDR2;
elsif mem_type = "DDR3" then
v_config_rec.mem_type := DDR3;
else
report ac_report_prefix & "unknown mem_type specified in the set_config_rec function in addr_cmd_pkg package" severity failure;
end if;
return v_config_rec;
end function;
-- The non-levelled sequencer doesn't make a distinction between CS_WIDTH and NUM_RANKS. In this case,
-- just set the two to be the same.
function set_config_rec ( num_addr_bits : in natural;
num_ba_bits : in natural;
num_cs_bits : in natural;
dwidth_ratio : in natural range 1 to c_max_cmds_per_clk;
mem_type : in string
) return t_addr_cmd_config_rec
is
begin
return set_config_rec(num_addr_bits, num_ba_bits, num_cs_bits, num_cs_bits, dwidth_ratio, mem_type);
end function;
-- -----------------------------------------------------------
-- unpack and pack address and command signals from and to t_addr_cmd_vector
-- -----------------------------------------------------------
-- -------------------------------------------------------------
-- convert from t_addr_cmd_vector to expanded addr/cmd signals
-- -------------------------------------------------------------
procedure unpack_addr_cmd_vector( addr_cmd_vector : in t_addr_cmd_vector;
config_rec : in t_addr_cmd_config_rec;
addr : out std_logic_vector;
ba : out std_logic_vector;
cas_n : out std_logic_vector;
ras_n : out std_logic_vector;
we_n : out std_logic_vector;
cke : out std_logic_vector;
cs_n : out std_logic_vector;
odt : out std_logic_vector;
rst_n : out std_logic_vector
)
is
variable v_mem_if_ranks : natural range 0 to 2**c_max_ranks - 1;
variable v_vec_len : natural range 1 to 4;
variable v_addr : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_addr_bits - 1 downto 0);
variable v_ba : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_ba_bits - 1 downto 0);
variable v_odt : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_ranks - 1 downto 0);
variable v_cs_n : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_cs_bits - 1 downto 0);
variable v_cke : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_ranks - 1 downto 0);
variable v_cas_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
variable v_ras_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
variable v_we_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
variable v_rst_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
begin
v_vec_len := config_rec.cmds_per_clk;
v_mem_if_ranks := config_rec.num_ranks;
for v_i in 0 to v_vec_len-1 loop
assert addr_cmd_vector(v_i).addr < 2**config_rec.num_addr_bits report ac_report_prefix &
"value of addr exceeds range of number of address bits in unpack_addr_cmd_vector procedure" severity failure;
assert addr_cmd_vector(v_i).ba < 2**config_rec.num_ba_bits report ac_report_prefix &
"value of ba exceeds range of number of bank address bits in unpack_addr_cmd_vector procedure" severity failure;
assert addr_cmd_vector(v_i).odt < 2**v_mem_if_ranks report ac_report_prefix &
"value of odt exceeds range of number of ranks in unpack_addr_cmd_vector procedure" severity failure;
assert addr_cmd_vector(v_i).cs_n < 2**config_rec.num_cs_bits report ac_report_prefix &
"value of cs_n exceeds range of number of ranks in unpack_addr_cmd_vector procedure" severity failure;
assert addr_cmd_vector(v_i).cke < 2**v_mem_if_ranks report ac_report_prefix &
"value of cke exceeds range of number of ranks in unpack_addr_cmd_vector procedure" severity failure;
v_addr((v_i+1)*config_rec.num_addr_bits - 1 downto v_i*config_rec.num_addr_bits) := std_logic_vector(to_unsigned(addr_cmd_vector(v_i).addr,config_rec.num_addr_bits));
v_ba((v_i+1)*config_rec.num_ba_bits - 1 downto v_i*config_rec.num_ba_bits) := std_logic_vector(to_unsigned(addr_cmd_vector(v_i).ba,config_rec.num_ba_bits));
v_cke((v_i+1)*v_mem_if_ranks - 1 downto v_i*v_mem_if_ranks) := std_logic_vector(to_unsigned(addr_cmd_vector(v_i).cke,v_mem_if_ranks));
v_cs_n((v_i+1)*config_rec.num_cs_bits - 1 downto v_i*config_rec.num_cs_bits) := std_logic_vector(to_unsigned(addr_cmd_vector(v_i).cs_n,config_rec.num_cs_bits));
v_odt((v_i+1)*v_mem_if_ranks - 1 downto v_i*v_mem_if_ranks) := std_logic_vector(to_unsigned(addr_cmd_vector(v_i).odt,v_mem_if_ranks));
if (addr_cmd_vector(v_i).cas_n) then v_cas_n(v_i) := '0'; else v_cas_n(v_i) := '1'; end if;
if (addr_cmd_vector(v_i).ras_n) then v_ras_n(v_i) := '0'; else v_ras_n(v_i) := '1'; end if;
if (addr_cmd_vector(v_i).we_n) then v_we_n(v_i) := '0'; else v_we_n(v_i) := '1'; end if;
if (addr_cmd_vector(v_i).rst_n) then v_rst_n(v_i) := '0'; else v_rst_n(v_i) := '1'; end if;
end loop;
addr := v_addr;
ba := v_ba;
cke := v_cke;
cs_n := v_cs_n;
odt := v_odt;
cas_n := v_cas_n;
ras_n := v_ras_n;
we_n := v_we_n;
rst_n := v_rst_n;
end procedure;
procedure unpack_addr_cmd_vector( config_rec : in t_addr_cmd_config_rec;
addr_cmd_vector : in t_addr_cmd_vector;
signal addr : out std_logic_vector;
signal ba : out std_logic_vector;
signal cas_n : out std_logic_vector;
signal ras_n : out std_logic_vector;
signal we_n : out std_logic_vector;
signal cke : out std_logic_vector;
signal cs_n : out std_logic_vector;
signal odt : out std_logic_vector;
signal rst_n : out std_logic_vector
)
is
variable v_mem_if_ranks : natural range 0 to 2**c_max_ranks - 1;
variable v_vec_len : natural range 1 to 4;
variable v_seq_ac_addr : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_addr_bits - 1 downto 0);
variable v_seq_ac_ba : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_ba_bits - 1 downto 0);
variable v_seq_ac_cas_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
variable v_seq_ac_ras_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
variable v_seq_ac_we_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
variable v_seq_ac_cke : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_ranks - 1 downto 0);
variable v_seq_ac_cs_n : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_cs_bits - 1 downto 0);
variable v_seq_ac_odt : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_ranks - 1 downto 0);
variable v_seq_ac_rst_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
begin
unpack_addr_cmd_vector (
addr_cmd_vector,
config_rec,
v_seq_ac_addr,
v_seq_ac_ba,
v_seq_ac_cas_n,
v_seq_ac_ras_n,
v_seq_ac_we_n,
v_seq_ac_cke,
v_seq_ac_cs_n,
v_seq_ac_odt,
v_seq_ac_rst_n);
addr <= v_seq_ac_addr;
ba <= v_seq_ac_ba;
cas_n <= v_seq_ac_cas_n;
ras_n <= v_seq_ac_ras_n;
we_n <= v_seq_ac_we_n;
cke <= v_seq_ac_cke;
cs_n <= v_seq_ac_cs_n;
odt <= v_seq_ac_odt;
rst_n <= v_seq_ac_rst_n;
end procedure;
-- -----------------------------------------------------------
-- function to mask each bit of signal signal_name in addr_cmd_
-- -----------------------------------------------------------
-- -----------------------------------------------------------
-- function to mask each bit of signal signal_name in addr_cmd_vector with mask_value
-- -----------------------------------------------------------
function mask ( config_rec : in t_addr_cmd_config_rec;
addr_cmd_vector : in t_addr_cmd_vector;
signal_name : in t_addr_cmd_signals;
mask_value : in std_logic
) return t_addr_cmd_vector
is
variable v_i : integer;
variable v_addr_cmd_vector : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
v_addr_cmd_vector := addr_cmd_vector;
for v_i in 0 to (config_rec.cmds_per_clk)-1 loop
case signal_name is
when addr => if (mask_value = '0') then v_addr_cmd_vector(v_i).addr := 0; else v_addr_cmd_vector(v_i).addr := (2 ** config_rec.num_addr_bits) - 1; end if;
when ba => if (mask_value = '0') then v_addr_cmd_vector(v_i).ba := 0; else v_addr_cmd_vector(v_i).ba := (2 ** config_rec.num_ba_bits) - 1; end if;
when cas_n => if (mask_value = '0') then v_addr_cmd_vector(v_i).cas_n := true; else v_addr_cmd_vector(v_i).cas_n := false; end if;
when ras_n => if (mask_value = '0') then v_addr_cmd_vector(v_i).ras_n := true; else v_addr_cmd_vector(v_i).ras_n := false; end if;
when we_n => if (mask_value = '0') then v_addr_cmd_vector(v_i).we_n := true; else v_addr_cmd_vector(v_i).we_n := false; end if;
when cke => if (mask_value = '0') then v_addr_cmd_vector(v_i).cke := 0; else v_addr_cmd_vector(v_i).cke := (2**config_rec.num_ranks) -1; end if;
when cs_n => if (mask_value = '0') then v_addr_cmd_vector(v_i).cs_n := 0; else v_addr_cmd_vector(v_i).cs_n := (2**config_rec.num_cs_bits) -1; end if;
when odt => if (mask_value = '0') then v_addr_cmd_vector(v_i).odt := 0; else v_addr_cmd_vector(v_i).odt := (2**config_rec.num_ranks) -1; end if;
when rst_n => if (mask_value = '0') then v_addr_cmd_vector(v_i).rst_n := true; else v_addr_cmd_vector(v_i).rst_n := false; end if;
when others => report ac_report_prefix & "bit masking not supported for the given signal name" severity failure;
end case;
end loop;
return v_addr_cmd_vector;
end function;
-- -----------------------------------------------------------
-- procedure to mask each bit of signal signal_name in addr_cmd_vector with mask_value
-- -----------------------------------------------------------
procedure mask( config_rec : in t_addr_cmd_config_rec;
signal addr_cmd_vector : inout t_addr_cmd_vector;
signal_name : in t_addr_cmd_signals;
mask_value : in std_logic
)
is
variable v_i : integer;
begin
for v_i in 0 to (config_rec.cmds_per_clk)-1 loop
case signal_name is
when addr => if (mask_value = '0') then addr_cmd_vector(v_i).addr <= 0; else addr_cmd_vector(v_i).addr <= (2 ** config_rec.num_addr_bits) - 1; end if;
when ba => if (mask_value = '0') then addr_cmd_vector(v_i).ba <= 0; else addr_cmd_vector(v_i).ba <= (2 ** config_rec.num_ba_bits) - 1; end if;
when cas_n => if (mask_value = '0') then addr_cmd_vector(v_i).cas_n <= true; else addr_cmd_vector(v_i).cas_n <= false; end if;
when ras_n => if (mask_value = '0') then addr_cmd_vector(v_i).ras_n <= true; else addr_cmd_vector(v_i).ras_n <= false; end if;
when we_n => if (mask_value = '0') then addr_cmd_vector(v_i).we_n <= true; else addr_cmd_vector(v_i).we_n <= false; end if;
when cke => if (mask_value = '0') then addr_cmd_vector(v_i).cke <= 0; else addr_cmd_vector(v_i).cke <= (2**config_rec.num_ranks) -1; end if;
when cs_n => if (mask_value = '0') then addr_cmd_vector(v_i).cs_n <= 0; else addr_cmd_vector(v_i).cs_n <= (2**config_rec.num_cs_bits) -1; end if;
when odt => if (mask_value = '0') then addr_cmd_vector(v_i).odt <= 0; else addr_cmd_vector(v_i).odt <= (2**config_rec.num_ranks) -1; end if;
when rst_n => if (mask_value = '0') then addr_cmd_vector(v_i).rst_n <= true; else addr_cmd_vector(v_i).rst_n <= false; end if;
when others => report ac_report_prefix & "masking not supported for the given signal name" severity failure;
end case;
end loop;
end procedure;
-- -----------------------------------------------------------
-- function to mask a given bit (mask_bit) of signal signal_name in addr_cmd_vector with mask_value
-- -----------------------------------------------------------
function mask ( config_rec : in t_addr_cmd_config_rec;
addr_cmd_vector : in t_addr_cmd_vector;
signal_name : in t_addr_cmd_signals;
mask_value : in std_logic;
mask_bit : in natural
) return t_addr_cmd_vector
is
variable v_i : integer;
variable v_addr : std_logic_vector(config_rec.num_addr_bits-1 downto 0); -- v_addr is bit vector of address
variable v_ba : std_logic_vector(config_rec.num_ba_bits-1 downto 0); -- v_addr is bit vector of bank address
variable v_vec_len : natural range 0 to 4;
variable v_addr_cmd_vector : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
v_addr_cmd_vector := addr_cmd_vector;
v_vec_len := config_rec.cmds_per_clk;
for v_i in 0 to v_vec_len-1 loop
case signal_name is
when addr =>
v_addr := std_logic_vector(to_unsigned(v_addr_cmd_vector(v_i).addr,v_addr'length));
v_addr(mask_bit) := mask_value;
v_addr_cmd_vector(v_i).addr := to_integer(unsigned(v_addr));
when ba =>
v_ba := std_logic_vector(to_unsigned(v_addr_cmd_vector(v_i).ba,v_ba'length));
v_ba(mask_bit) := mask_value;
v_addr_cmd_vector(v_i).ba := to_integer(unsigned(v_ba));
when others =>
report ac_report_prefix & "bit masking not supported for the given signal name" severity failure;
end case;
end loop;
return v_addr_cmd_vector;
end function;
--
end memphy_alt_mem_phy_addr_cmd_pkg;
--
-- -----------------------------------------------------------------------------
-- Abstract : iram addressing package for the non-levelling AFI PHY sequencer
-- The iram address package (alt_mem_phy_iram_addr_pkg) is
-- used to define the base addresses used for iram writes
-- during calibration.
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--
package memphy_alt_mem_phy_iram_addr_pkg IS
constant c_ihi_size : natural := 8;
type t_base_hdr_addresses is record
base_hdr : natural;
rrp : natural;
safe_dummy : natural;
required_addr_bits : natural;
end record;
function defaults return t_base_hdr_addresses;
function rrp_pll_phase_mult (dwidth_ratio : in natural;
dqs_capture : in natural
)
return natural;
function iram_wd_for_full_rrp ( dwidth_ratio : in natural;
pll_phases : in natural;
dq_pins : in natural;
dqs_capture : in natural
)
return natural;
function iram_wd_for_one_pin_rrp ( dwidth_ratio : in natural;
pll_phases : in natural;
dq_pins : in natural;
dqs_capture : in natural
)
return natural;
function calc_iram_addresses ( dwidth_ratio : in natural;
pll_phases : in natural;
dq_pins : in natural;
num_ranks : in natural;
dqs_capture : in natural
)
return t_base_hdr_addresses;
--
end memphy_alt_mem_phy_iram_addr_pkg;
--
package body memphy_alt_mem_phy_iram_addr_pkg IS
-- set some safe default values
function defaults return t_base_hdr_addresses is
variable temp : t_base_hdr_addresses;
begin
temp.base_hdr := 0;
temp.rrp := 0;
temp.safe_dummy := 0;
temp.required_addr_bits := 1;
return temp;
end function;
-- this function determines now many times the PLL phases are swept through per pin
-- i.e. an n * 360 degree phase sweep
function rrp_pll_phase_mult (dwidth_ratio : in natural;
dqs_capture : in natural
)
return natural
is
variable v_output : natural;
begin
if dwidth_ratio = 2 and dqs_capture = 1 then
v_output := 2; -- if dqs_capture then a 720 degree sweep needed in FR
else
v_output := (dwidth_ratio/2);
end if;
return v_output;
end function;
-- function to calculate how many words are required for a rrp sweep over all pins
function iram_wd_for_full_rrp ( dwidth_ratio : in natural;
pll_phases : in natural;
dq_pins : in natural;
dqs_capture : in natural
)
return natural
is
variable v_output : natural;
variable v_phase_mul : natural;
begin
-- determine the n * 360 degrees of sweep required
v_phase_mul := rrp_pll_phase_mult(dwidth_ratio, dqs_capture);
-- calculate output size
v_output := dq_pins * (((v_phase_mul * pll_phases) + 31) / 32);
return v_output;
end function;
-- function to calculate how many words are required for a rrp sweep over all pins
function iram_wd_for_one_pin_rrp ( dwidth_ratio : in natural;
pll_phases : in natural;
dq_pins : in natural;
dqs_capture : in natural
)
return natural
is
variable v_output : natural;
variable v_phase_mul : natural;
begin
-- determine the n * 360 degrees of sweep required
v_phase_mul := rrp_pll_phase_mult(dwidth_ratio, dqs_capture);
-- calculate output size
v_output := ((v_phase_mul * pll_phases) + 31) / 32;
return v_output;
end function;
-- return iram addresses
function calc_iram_addresses ( dwidth_ratio : in natural;
pll_phases : in natural;
dq_pins : in natural;
num_ranks : in natural;
dqs_capture : in natural
)
return t_base_hdr_addresses
is
variable working : t_base_hdr_addresses;
variable temp : natural;
variable v_required_words : natural;
begin
working.base_hdr := 0;
working.rrp := working.base_hdr + c_ihi_size;
-- work out required number of address bits
-- + for 1 full rrp calibration
v_required_words := iram_wd_for_full_rrp(dwidth_ratio, pll_phases, dq_pins, dqs_capture) + 2; -- +2 for header + footer
-- * loop per cs
v_required_words := v_required_words * num_ranks;
-- + for 1 rrp_seek result
v_required_words := v_required_words + 3; -- 1 header, 1 word result, 1 footer
-- + 2 mtp_almt passes
v_required_words := v_required_words + 2 * (iram_wd_for_one_pin_rrp(dwidth_ratio, pll_phases, dq_pins, dqs_capture) + 2);
-- + for 2 read_mtp result calculation
v_required_words := v_required_words + 3*2; -- 1 header, 1 word result, 1 footer
-- * possible dwidth_ratio/2 iterations for different ac_nt settings
v_required_words := v_required_words * (dwidth_ratio / 2);
working.safe_dummy := working.rrp + v_required_words;
temp := working.safe_dummy;
working.required_addr_bits := 0;
while (temp >= 1) loop
working.required_addr_bits := working.required_addr_bits + 1;
temp := temp /2;
end loop;
return working;
end function calc_iram_addresses;
--
END memphy_alt_mem_phy_iram_addr_pkg;
--
-- -----------------------------------------------------------------------------
-- Abstract : register package for the non-levelling AFI PHY sequencer
-- The registers package (alt_mem_phy_regs_pkg) is used to
-- combine the definition of the registers for the mmi status
-- registers and functions/procedures applied to the registers
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.memphy_alt_mem_phy_record_pkg.all;
-- The constant package (alt_mem_phy_constants_pkg) contains global 'constants' which are fixed
-- thoughout the sequencer and will not change (for constants which may change between sequencer
-- instances generics are used)
--
use work.memphy_alt_mem_phy_constants_pkg.all;
--
package memphy_alt_mem_phy_regs_pkg is
-- a prefix for all report signals to identify phy and sequencer block
--
constant regs_report_prefix : string := "memphy_alt_mem_phy_seq (register package) : ";
-- ---------------------------------------------------------------
-- register declarations with associated functions of:
-- default - assign default values
-- write - write data into the reg (from avalon i/f)
-- read - read data from the reg (sent to the avalon i/f)
-- write_clear - clear reg to all zeros
-- ---------------------------------------------------------------
-- TYPE DECLARATIONS
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- Read Only Registers
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- cal_status
type t_cal_status is record
iram_addr_width : std_logic_vector(3 downto 0);
out_of_mem : std_logic;
contested_access : std_logic;
cal_fail : std_logic;
cal_success : std_logic;
ctrl_err_code : std_logic_vector(7 downto 0);
trefi_failure : std_logic;
int_ac_1t : std_logic;
dqs_capture : std_logic;
iram_present : std_logic;
active_block : std_logic_vector(3 downto 0);
current_stage : std_logic_vector(7 downto 0);
end record;
-- codvw status
type t_codvw_status is record
cal_codvw_phase : std_logic_vector(7 downto 0);
cal_codvw_size : std_logic_vector(7 downto 0);
codvw_trk_shift : std_logic_vector(11 downto 0);
codvw_grt_one_dvw : std_logic;
end record t_codvw_status;
-- test status report
type t_test_status is record
ack_seen : std_logic_vector(c_hl_ccs_num_stages-1 downto 0);
pll_mmi_err : std_logic_vector(1 downto 0);
pll_busy : std_logic;
end record;
-- define all the read only registers :
type t_ro_regs is record
cal_status : t_cal_status;
codvw_status : t_codvw_status;
test_status : t_test_status;
end record;
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- Read / Write Registers
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- Calibration control register
type t_hl_css is record
hl_css : std_logic_vector(c_hl_ccs_num_stages-1 downto 0);
cal_start : std_logic;
end record t_hl_css;
-- Mode register A
type t_mr_register_a is record
mr0 : std_logic_vector(c_max_mode_reg_index -1 downto 0);
mr1 : std_logic_vector(c_max_mode_reg_index -1 downto 0);
end record t_mr_register_a;
-- Mode register B
type t_mr_register_b is record
mr2 : std_logic_vector(c_max_mode_reg_index -1 downto 0);
mr3 : std_logic_vector(c_max_mode_reg_index -1 downto 0);
end record t_mr_register_b;
-- algorithm parameterisation register
type t_parameterisation_reg_a is record
nominal_poa_phase_lead : std_logic_vector(3 downto 0);
maximum_poa_delay : std_logic_vector(3 downto 0);
num_phases_per_tck_pll : std_logic_vector(3 downto 0);
pll_360_sweeps : std_logic_vector(3 downto 0);
nominal_dqs_delay : std_logic_vector(2 downto 0);
extend_octrt_by : std_logic_vector(3 downto 0);
delay_octrt_by : std_logic_vector(3 downto 0);
end record;
-- test signal register
type t_if_test_reg is record
pll_phs_shft_phase_sel : natural range 0 to 15;
pll_phs_shft_up_wc : std_logic;
pll_phs_shft_dn_wc : std_logic;
ac_1t_toggle : std_logic; -- unused
tracking_period_ms : std_logic_vector(7 downto 0); -- 0 = as fast as possible approx in ms
tracking_units_are_10us : std_logic;
end record;
-- define all the read/write registers
type t_rw_regs is record
mr_reg_a : t_mr_register_a;
mr_reg_b : t_mr_register_b;
rw_hl_css : t_hl_css;
rw_param_reg : t_parameterisation_reg_a;
rw_if_test : t_if_test_reg;
end record;
-- >>>>>>>>>>>>>>>>>>>>>>>
-- Group all registers
-- >>>>>>>>>>>>>>>>>>>>>>>
type t_mmi_regs is record
rw_regs : t_rw_regs;
ro_regs : t_ro_regs;
enable_writes : std_logic;
end record;
-- FUNCTION DECLARATIONS
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- Read Only Registers
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- cal_status
function defaults return t_cal_status;
function defaults ( ctrl_mmi : in t_ctrl_mmi;
USE_IRAM : in std_logic;
dqs_capture : in natural;
int_ac_1t : in std_logic;
trefi_failure : in std_logic;
iram_status : in t_iram_stat;
IRAM_AWIDTH : in natural
) return t_cal_status;
function read (reg : t_cal_status) return std_logic_vector;
-- codvw status
function defaults return t_codvw_status;
function defaults ( dgrb_mmi : t_dgrb_mmi
) return t_codvw_status;
function read (reg : in t_codvw_status) return std_logic_vector;
-- test status report
function defaults return t_test_status;
function defaults ( ctrl_mmi : in t_ctrl_mmi;
pll_mmi : in t_pll_mmi;
rw_if_test : t_if_test_reg
) return t_test_status;
function read (reg : t_test_status) return std_logic_vector;
-- define all the read only registers
function defaults return t_ro_regs;
function defaults (dgrb_mmi : t_dgrb_mmi;
ctrl_mmi : t_ctrl_mmi;
pll_mmi : t_pll_mmi;
rw_if_test : t_if_test_reg;
USE_IRAM : std_logic;
dqs_capture : natural;
int_ac_1t : std_logic;
trefi_failure : std_logic;
iram_status : t_iram_stat;
IRAM_AWIDTH : natural
) return t_ro_regs;
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- Read / Write Registers
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- Calibration control register
-- high level calibration stage set register comprises a bit vector for
-- the calibration stage coding and the 1 control bit.
function defaults return t_hl_css;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_hl_css;
function read (reg : in t_hl_css) return std_logic_vector;
procedure write_clear (signal reg : inout t_hl_css);
-- Mode register A
-- mode registers 0 and 1 (mr and emr1)
function defaults return t_mr_register_a;
function defaults ( mr0 : in std_logic_vector;
mr1 : in std_logic_vector
) return t_mr_register_a;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_mr_register_a;
function read (reg : in t_mr_register_a) return std_logic_vector;
-- Mode register B
-- mode registers 2 and 3 (emr2 and emr3) - not present in ddr DRAM
function defaults return t_mr_register_b;
function defaults ( mr2 : in std_logic_vector;
mr3 : in std_logic_vector
) return t_mr_register_b;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_mr_register_b;
function read (reg : in t_mr_register_b) return std_logic_vector;
-- algorithm parameterisation register
function defaults return t_parameterisation_reg_a;
function defaults ( NOM_DQS_PHASE_SETTING : in natural;
PLL_STEPS_PER_CYCLE : in natural;
pll_360_sweeps : in natural
) return t_parameterisation_reg_a;
function read ( reg : in t_parameterisation_reg_a) return std_logic_vector;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_parameterisation_reg_a;
-- test signal register
function defaults return t_if_test_reg;
function defaults ( TRACKING_INTERVAL_IN_MS : in natural
) return t_if_test_reg;
function read ( reg : in t_if_test_reg) return std_logic_vector;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_if_test_reg;
procedure write_clear (signal reg : inout t_if_test_reg);
-- define all the read/write registers
function defaults return t_rw_regs;
function defaults(
mr0 : in std_logic_vector;
mr1 : in std_logic_vector;
mr2 : in std_logic_vector;
mr3 : in std_logic_vector;
NOM_DQS_PHASE_SETTING : in natural;
PLL_STEPS_PER_CYCLE : in natural;
pll_360_sweeps : in natural;
TRACKING_INTERVAL_IN_MS : in natural;
C_HL_STAGE_ENABLE : in std_logic_vector(c_hl_ccs_num_stages-1 downto 0)
)return t_rw_regs;
procedure write_clear (signal regs : inout t_rw_regs);
-- >>>>>>>>>>>>>>>>>>>>>>>
-- Group all registers
-- >>>>>>>>>>>>>>>>>>>>>>>
function defaults return t_mmi_regs;
function v_read (mmi_regs : in t_mmi_regs;
address : in natural
) return std_logic_vector;
function read (signal mmi_regs : in t_mmi_regs;
address : in natural
) return std_logic_vector;
procedure write (mmi_regs : inout t_mmi_regs;
address : in natural;
wdata : in std_logic_vector(31 downto 0));
-- >>>>>>>>>>>>>>>>>>>>>>>
-- functions to communicate register settings to other sequencer blocks
-- >>>>>>>>>>>>>>>>>>>>>>>
function pack_record (ip_regs : t_rw_regs) return t_mmi_pll_reconfig;
function pack_record (ip_regs : t_rw_regs) return t_admin_ctrl;
function pack_record (ip_regs : t_rw_regs) return t_mmi_ctrl;
function pack_record ( ip_regs : t_rw_regs) return t_algm_paramaterisation;
-- >>>>>>>>>>>>>>>>>>>>>>>
-- helper functions
-- >>>>>>>>>>>>>>>>>>>>>>>
function to_t_hl_css_reg (hl_css : t_hl_css ) return t_hl_css_reg;
function pack_ack_seen ( cal_stage_ack_seen : in t_cal_stage_ack_seen
) return std_logic_vector;
-- encoding of stage and active block for register setting
function encode_current_stage (ctrl_cmd_id : t_ctrl_cmd_id) return std_logic_vector;
function encode_active_block (active_block : t_ctrl_active_block) return std_logic_vector;
--
end memphy_alt_mem_phy_regs_pkg;
--
package body memphy_alt_mem_phy_regs_pkg is
-- >>>>>>>>>>>>>>>>>>>>
-- Read Only Registers
-- >>>>>>>>>>>>>>>>>>>
-- ---------------------------------------------------------------
-- CODVW status report
-- ---------------------------------------------------------------
function defaults return t_codvw_status is
variable temp: t_codvw_status;
begin
temp.cal_codvw_phase := (others => '0');
temp.cal_codvw_size := (others => '0');
temp.codvw_trk_shift := (others => '0');
temp.codvw_grt_one_dvw := '0';
return temp;
end function;
function defaults ( dgrb_mmi : t_dgrb_mmi
) return t_codvw_status is
variable temp: t_codvw_status;
begin
temp := defaults;
temp.cal_codvw_phase := dgrb_mmi.cal_codvw_phase;
temp.cal_codvw_size := dgrb_mmi.cal_codvw_size;
temp.codvw_trk_shift := dgrb_mmi.codvw_trk_shift;
temp.codvw_grt_one_dvw := dgrb_mmi.codvw_grt_one_dvw;
return temp;
end function;
function read (reg : in t_codvw_status) return std_logic_vector is
variable temp : std_logic_vector(31 downto 0);
begin
temp := (others => '0');
temp(31 downto 24) := reg.cal_codvw_phase;
temp(23 downto 16) := reg.cal_codvw_size;
temp(15 downto 4) := reg.codvw_trk_shift;
temp(0) := reg.codvw_grt_one_dvw;
return temp;
end function;
-- ---------------------------------------------------------------
-- Calibration status report
-- ---------------------------------------------------------------
function defaults return t_cal_status is
variable temp: t_cal_status;
begin
temp.iram_addr_width := (others => '0');
temp.out_of_mem := '0';
temp.contested_access := '0';
temp.cal_fail := '0';
temp.cal_success := '0';
temp.ctrl_err_code := (others => '0');
temp.trefi_failure := '0';
temp.int_ac_1t := '0';
temp.dqs_capture := '0';
temp.iram_present := '0';
temp.active_block := (others => '0');
temp.current_stage := (others => '0');
return temp;
end function;
function defaults ( ctrl_mmi : in t_ctrl_mmi;
USE_IRAM : in std_logic;
dqs_capture : in natural;
int_ac_1t : in std_logic;
trefi_failure : in std_logic;
iram_status : in t_iram_stat;
IRAM_AWIDTH : in natural
) return t_cal_status is
variable temp : t_cal_status;
begin
temp := defaults;
temp.iram_addr_width := std_logic_vector(to_unsigned(IRAM_AWIDTH, temp.iram_addr_width'length));
temp.out_of_mem := iram_status.out_of_mem;
temp.contested_access := iram_status.contested_access;
temp.cal_fail := ctrl_mmi.ctrl_calibration_fail;
temp.cal_success := ctrl_mmi.ctrl_calibration_success;
temp.ctrl_err_code := ctrl_mmi.ctrl_err_code;
temp.trefi_failure := trefi_failure;
temp.int_ac_1t := int_ac_1t;
if dqs_capture = 1 then
temp.dqs_capture := '1';
elsif dqs_capture = 0 then
temp.dqs_capture := '0';
else
report regs_report_prefix & " invalid value for dqs_capture constant of " & integer'image(dqs_capture) severity failure;
end if;
temp.iram_present := USE_IRAM;
temp.active_block := encode_active_block(ctrl_mmi.ctrl_current_active_block);
temp.current_stage := encode_current_stage(ctrl_mmi.ctrl_current_stage);
return temp;
end function;
-- read for mmi status register
function read ( reg : t_cal_status
) return std_logic_vector is
variable output : std_logic_vector(31 downto 0);
begin
output := (others => '0');
output( 7 downto 0) := reg.current_stage;
output(11 downto 8) := reg.active_block;
output(12) := reg.iram_present;
output(13) := reg.dqs_capture;
output(14) := reg.int_ac_1t;
output(15) := reg.trefi_failure;
output(23 downto 16) := reg.ctrl_err_code;
output(24) := reg.cal_success;
output(25) := reg.cal_fail;
output(26) := reg.contested_access;
output(27) := reg.out_of_mem;
output(31 downto 28) := reg.iram_addr_width;
return output;
end function;
-- ---------------------------------------------------------------
-- Test status report
-- ---------------------------------------------------------------
function defaults return t_test_status is
variable temp: t_test_status;
begin
temp.ack_seen := (others => '0');
temp.pll_mmi_err := (others => '0');
temp.pll_busy := '0';
return temp;
end function;
function defaults ( ctrl_mmi : in t_ctrl_mmi;
pll_mmi : in t_pll_mmi;
rw_if_test : t_if_test_reg
) return t_test_status is
variable temp : t_test_status;
begin
temp := defaults;
temp.ack_seen := pack_ack_seen(ctrl_mmi.ctrl_cal_stage_ack_seen);
temp.pll_mmi_err := pll_mmi.err;
temp.pll_busy := pll_mmi.pll_busy or rw_if_test.pll_phs_shft_up_wc or rw_if_test.pll_phs_shft_dn_wc;
return temp;
end function;
-- read for mmi status register
function read ( reg : t_test_status
) return std_logic_vector is
variable output : std_logic_vector(31 downto 0);
begin
output := (others => '0');
output(31 downto 32-c_hl_ccs_num_stages) := reg.ack_seen;
output( 5 downto 4) := reg.pll_mmi_err;
output(0) := reg.pll_busy;
return output;
end function;
-------------------------------------------------
-- FOR ALL RO REGS:
-------------------------------------------------
function defaults return t_ro_regs is
variable temp: t_ro_regs;
begin
temp.cal_status := defaults;
temp.codvw_status := defaults;
return temp;
end function;
function defaults (dgrb_mmi : t_dgrb_mmi;
ctrl_mmi : t_ctrl_mmi;
pll_mmi : t_pll_mmi;
rw_if_test : t_if_test_reg;
USE_IRAM : std_logic;
dqs_capture : natural;
int_ac_1t : std_logic;
trefi_failure : std_logic;
iram_status : t_iram_stat;
IRAM_AWIDTH : natural
) return t_ro_regs is
variable output : t_ro_regs;
begin
output := defaults;
output.cal_status := defaults(ctrl_mmi, USE_IRAM, dqs_capture, int_ac_1t, trefi_failure, iram_status, IRAM_AWIDTH);
output.codvw_status := defaults(dgrb_mmi);
output.test_status := defaults(ctrl_mmi, pll_mmi, rw_if_test);
return output;
end function;
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- Read / Write registers
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- ---------------------------------------------------------------
-- mode register set A
-- ---------------------------------------------------------------
function defaults return t_mr_register_a is
variable temp :t_mr_register_a;
begin
temp.mr0 := (others => '0');
temp.mr1 := (others => '0');
return temp;
end function;
-- apply default mode register settings to register
function defaults ( mr0 : in std_logic_vector;
mr1 : in std_logic_vector
) return t_mr_register_a is
variable temp :t_mr_register_a;
begin
temp := defaults;
temp.mr0 := mr0(temp.mr0'range);
temp.mr1 := mr1(temp.mr1'range);
return temp;
end function;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_mr_register_a is
variable temp :t_mr_register_a;
begin
temp.mr0 := wdata_in(c_max_mode_reg_index -1 downto 0);
temp.mr1 := wdata_in(c_max_mode_reg_index -1 + 16 downto 16);
return temp;
end function;
function read (reg : in t_mr_register_a) return std_logic_vector is
variable temp : std_logic_vector(31 downto 0) := (others => '0');
begin
temp(c_max_mode_reg_index -1 downto 0) := reg.mr0;
temp(c_max_mode_reg_index -1 + 16 downto 16) := reg.mr1;
return temp;
end function;
-- ---------------------------------------------------------------
-- mode register set B
-- ---------------------------------------------------------------
function defaults return t_mr_register_b is
variable temp :t_mr_register_b;
begin
temp.mr2 := (others => '0');
temp.mr3 := (others => '0');
return temp;
end function;
-- apply default mode register settings to register
function defaults ( mr2 : in std_logic_vector;
mr3 : in std_logic_vector
) return t_mr_register_b is
variable temp :t_mr_register_b;
begin
temp := defaults;
temp.mr2 := mr2(temp.mr2'range);
temp.mr3 := mr3(temp.mr3'range);
return temp;
end function;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_mr_register_b is
variable temp :t_mr_register_b;
begin
temp.mr2 := wdata_in(c_max_mode_reg_index -1 downto 0);
temp.mr3 := wdata_in(c_max_mode_reg_index -1 + 16 downto 16);
return temp;
end function;
function read (reg : in t_mr_register_b) return std_logic_vector is
variable temp : std_logic_vector(31 downto 0) := (others => '0');
begin
temp(c_max_mode_reg_index -1 downto 0) := reg.mr2;
temp(c_max_mode_reg_index -1 + 16 downto 16) := reg.mr3;
return temp;
end function;
-- ---------------------------------------------------------------
-- HL CSS (high level calibration state status)
-- ---------------------------------------------------------------
function defaults return t_hl_css is
variable temp : t_hl_css;
begin
temp.hl_css := (others => '0');
temp.cal_start := '0';
return temp;
end function;
function defaults ( C_HL_STAGE_ENABLE : in std_logic_vector(c_hl_ccs_num_stages-1 downto 0)
) return t_hl_css is
variable temp: t_hl_css;
begin
temp := defaults;
temp.hl_css := temp.hl_css OR C_HL_STAGE_ENABLE;
return temp;
end function;
function read ( reg : in t_hl_css) return std_logic_vector is
variable temp : std_logic_vector (31 downto 0) := (others => '0');
begin
temp(30 downto 30-c_hl_ccs_num_stages+1) := reg.hl_css;
temp(0) := reg.cal_start;
return temp;
end function;
function write (wdata_in : std_logic_vector(31 downto 0) )return t_hl_css is
variable reg : t_hl_css;
begin
reg.hl_css := wdata_in(30 downto 30-c_hl_ccs_num_stages+1);
reg.cal_start := wdata_in(0);
return reg;
end function;
procedure write_clear (signal reg : inout t_hl_css) is
begin
reg.cal_start <= '0';
end procedure;
-- ---------------------------------------------------------------
-- paramaterisation of sequencer through Avalon interface
-- ---------------------------------------------------------------
function defaults return t_parameterisation_reg_a is
variable temp : t_parameterisation_reg_a;
begin
temp.nominal_poa_phase_lead := (others => '0');
temp.maximum_poa_delay := (others => '0');
temp.pll_360_sweeps := "0000";
temp.num_phases_per_tck_pll := "0011";
temp.nominal_dqs_delay := (others => '0');
temp.extend_octrt_by := "0100";
temp.delay_octrt_by := "0000";
return temp;
end function;
-- reset the paramterisation reg to given values
function defaults ( NOM_DQS_PHASE_SETTING : in natural;
PLL_STEPS_PER_CYCLE : in natural;
pll_360_sweeps : in natural
) return t_parameterisation_reg_a is
variable temp: t_parameterisation_reg_a;
begin
temp := defaults;
temp.num_phases_per_tck_pll := std_logic_vector(to_unsigned(PLL_STEPS_PER_CYCLE /8 , temp.num_phases_per_tck_pll'high + 1 ));
temp.pll_360_sweeps := std_logic_vector(to_unsigned(pll_360_sweeps , temp.pll_360_sweeps'high + 1 ));
temp.nominal_dqs_delay := std_logic_vector(to_unsigned(NOM_DQS_PHASE_SETTING , temp.nominal_dqs_delay'high + 1 ));
temp.extend_octrt_by := std_logic_vector(to_unsigned(5 , temp.extend_octrt_by'high + 1 ));
temp.delay_octrt_by := std_logic_vector(to_unsigned(6 , temp.delay_octrt_by'high + 1 ));
return temp;
end function;
function read ( reg : in t_parameterisation_reg_a) return std_logic_vector is
variable temp : std_logic_vector (31 downto 0) := (others => '0');
begin
temp( 3 downto 0) := reg.pll_360_sweeps;
temp( 7 downto 4) := reg.num_phases_per_tck_pll;
temp(10 downto 8) := reg.nominal_dqs_delay;
temp(19 downto 16) := reg.nominal_poa_phase_lead;
temp(23 downto 20) := reg.maximum_poa_delay;
temp(27 downto 24) := reg.extend_octrt_by;
temp(31 downto 28) := reg.delay_octrt_by;
return temp;
end function;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_parameterisation_reg_a is
variable reg : t_parameterisation_reg_a;
begin
reg.pll_360_sweeps := wdata_in( 3 downto 0);
reg.num_phases_per_tck_pll := wdata_in( 7 downto 4);
reg.nominal_dqs_delay := wdata_in(10 downto 8);
reg.nominal_poa_phase_lead := wdata_in(19 downto 16);
reg.maximum_poa_delay := wdata_in(23 downto 20);
reg.extend_octrt_by := wdata_in(27 downto 24);
reg.delay_octrt_by := wdata_in(31 downto 28);
return reg;
end function;
-- ---------------------------------------------------------------
-- t_if_test_reg - additional test support register
-- ---------------------------------------------------------------
function defaults return t_if_test_reg is
variable temp : t_if_test_reg;
begin
temp.pll_phs_shft_phase_sel := 0;
temp.pll_phs_shft_up_wc := '0';
temp.pll_phs_shft_dn_wc := '0';
temp.ac_1t_toggle := '0';
temp.tracking_period_ms := "10000000"; -- 127 ms interval
temp.tracking_units_are_10us := '0';
return temp;
end function;
-- reset the paramterisation reg to given values
function defaults ( TRACKING_INTERVAL_IN_MS : in natural
) return t_if_test_reg is
variable temp: t_if_test_reg;
begin
temp := defaults;
temp.tracking_period_ms := std_logic_vector(to_unsigned(TRACKING_INTERVAL_IN_MS, temp.tracking_period_ms'length));
return temp;
end function;
function read ( reg : in t_if_test_reg) return std_logic_vector is
variable temp : std_logic_vector (31 downto 0) := (others => '0');
begin
temp( 3 downto 0) := std_logic_vector(to_unsigned(reg.pll_phs_shft_phase_sel,4));
temp(4) := reg.pll_phs_shft_up_wc;
temp(5) := reg.pll_phs_shft_dn_wc;
temp(16) := reg.ac_1t_toggle;
temp(15 downto 8) := reg.tracking_period_ms;
temp(20) := reg.tracking_units_are_10us;
return temp;
end function;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_if_test_reg is
variable reg : t_if_test_reg;
begin
reg.pll_phs_shft_phase_sel := to_integer(unsigned(wdata_in( 3 downto 0)));
reg.pll_phs_shft_up_wc := wdata_in(4);
reg.pll_phs_shft_dn_wc := wdata_in(5);
reg.ac_1t_toggle := wdata_in(16);
reg.tracking_period_ms := wdata_in(15 downto 8);
reg.tracking_units_are_10us := wdata_in(20);
return reg;
end function;
procedure write_clear (signal reg : inout t_if_test_reg) is
begin
reg.ac_1t_toggle <= '0';
reg.pll_phs_shft_up_wc <= '0';
reg.pll_phs_shft_dn_wc <= '0';
end procedure;
-- ---------------------------------------------------------------
-- RW Regs, record of read/write register records (to simplify handling)
-- ---------------------------------------------------------------
function defaults return t_rw_regs is
variable temp : t_rw_regs;
begin
temp.mr_reg_a := defaults;
temp.mr_reg_b := defaults;
temp.rw_hl_css := defaults;
temp.rw_param_reg := defaults;
temp.rw_if_test := defaults;
return temp;
end function;
function defaults(
mr0 : in std_logic_vector;
mr1 : in std_logic_vector;
mr2 : in std_logic_vector;
mr3 : in std_logic_vector;
NOM_DQS_PHASE_SETTING : in natural;
PLL_STEPS_PER_CYCLE : in natural;
pll_360_sweeps : in natural;
TRACKING_INTERVAL_IN_MS : in natural;
C_HL_STAGE_ENABLE : in std_logic_vector(c_hl_ccs_num_stages-1 downto 0)
)return t_rw_regs is
variable temp : t_rw_regs;
begin
temp := defaults;
temp.mr_reg_a := defaults(mr0, mr1);
temp.mr_reg_b := defaults(mr2, mr3);
temp.rw_param_reg := defaults(NOM_DQS_PHASE_SETTING,
PLL_STEPS_PER_CYCLE,
pll_360_sweeps);
temp.rw_if_test := defaults(TRACKING_INTERVAL_IN_MS);
temp.rw_hl_css := defaults(C_HL_STAGE_ENABLE);
return temp;
end function;
procedure write_clear (signal regs : inout t_rw_regs) is
begin
write_clear(regs.rw_if_test);
write_clear(regs.rw_hl_css);
end procedure;
-- >>>>>>>>>>>>>>>>>>>>>>>>>>
-- All mmi registers:
-- >>>>>>>>>>>>>>>>>>>>>>>>>>
function defaults return t_mmi_regs is
variable v_mmi_regs : t_mmi_regs;
begin
v_mmi_regs.rw_regs := defaults;
v_mmi_regs.ro_regs := defaults;
v_mmi_regs.enable_writes := '0';
return v_mmi_regs;
end function;
function v_read (mmi_regs : in t_mmi_regs;
address : in natural
) return std_logic_vector is
variable output : std_logic_vector(31 downto 0);
begin
output := (others => '0');
case address is
-- status register
when c_regofst_cal_status => output := read (mmi_regs.ro_regs.cal_status);
-- debug access register
when c_regofst_debug_access =>
if (mmi_regs.enable_writes = '1') then
output := c_mmi_access_codeword;
else
output := (others => '0');
end if;
-- test i/f to check which stages have acknowledged a command and pll checks
when c_regofst_test_status => output := read(mmi_regs.ro_regs.test_status);
-- mode registers
when c_regofst_mr_register_a => output := read(mmi_regs.rw_regs.mr_reg_a);
when c_regofst_mr_register_b => output := read(mmi_regs.rw_regs.mr_reg_b);
-- codvw r/o status register
when c_regofst_codvw_status => output := read(mmi_regs.ro_regs.codvw_status);
-- read/write registers
when c_regofst_hl_css => output := read(mmi_regs.rw_regs.rw_hl_css);
when c_regofst_if_param => output := read(mmi_regs.rw_regs.rw_param_reg);
when c_regofst_if_test => output := read(mmi_regs.rw_regs.rw_if_test);
when others => report regs_report_prefix & "MMI registers detected an attempt to read to non-existant register location" severity warning;
-- set illegal addr interrupt.
end case;
return output;
end function;
function read (signal mmi_regs : in t_mmi_regs;
address : in natural
) return std_logic_vector is
variable output : std_logic_vector(31 downto 0);
variable v_mmi_regs : t_mmi_regs;
begin
v_mmi_regs := mmi_regs;
output := v_read(v_mmi_regs, address);
return output;
end function;
procedure write (mmi_regs : inout t_mmi_regs;
address : in natural;
wdata : in std_logic_vector(31 downto 0)) is
begin
-- intercept writes to codeword. This needs to be set for iRAM access :
if address = c_regofst_debug_access then
if wdata = c_mmi_access_codeword then
mmi_regs.enable_writes := '1';
else
mmi_regs.enable_writes := '0';
end if;
else
case address is
-- read only registers
when c_regofst_cal_status |
c_regofst_codvw_status |
c_regofst_test_status =>
report regs_report_prefix & "MMI registers detected an attempt to write to read only register number" & integer'image(address) severity failure;
-- read/write registers
when c_regofst_mr_register_a => mmi_regs.rw_regs.mr_reg_a := write(wdata);
when c_regofst_mr_register_b => mmi_regs.rw_regs.mr_reg_b := write(wdata);
when c_regofst_hl_css => mmi_regs.rw_regs.rw_hl_css := write(wdata);
when c_regofst_if_param => mmi_regs.rw_regs.rw_param_reg := write(wdata);
when c_regofst_if_test => mmi_regs.rw_regs.rw_if_test := write(wdata);
when others => -- set illegal addr interrupt.
report regs_report_prefix & "MMI registers detected an attempt to write to non existant register, with expected number" & integer'image(address) severity failure;
end case;
end if;
end procedure;
-- >>>>>>>>>>>>>>>>>>>>>>>>>>
-- the following functions enable register data to be communicated to other sequencer blocks
-- >>>>>>>>>>>>>>>>>>>>>>>>>>
function pack_record ( ip_regs : t_rw_regs
) return t_algm_paramaterisation is
variable output : t_algm_paramaterisation;
begin
-- default assignments
output.num_phases_per_tck_pll := 16;
output.pll_360_sweeps := 1;
output.nominal_dqs_delay := 2;
output.nominal_poa_phase_lead := 1;
output.maximum_poa_delay := 5;
output.odt_enabled := false;
output.num_phases_per_tck_pll := to_integer(unsigned(ip_regs.rw_param_reg.num_phases_per_tck_pll)) * 8;
case ip_regs.rw_param_reg.nominal_dqs_delay is
when "010" => output.nominal_dqs_delay := 2;
when "001" => output.nominal_dqs_delay := 1;
when "000" => output.nominal_dqs_delay := 0;
when "011" => output.nominal_dqs_delay := 3;
when others => report regs_report_prefix &
"there is a unsupported number of DQS taps (" &
natural'image(to_integer(unsigned(ip_regs.rw_param_reg.nominal_dqs_delay))) &
") being advertised as the standard value" severity error;
end case;
case ip_regs.rw_param_reg.nominal_poa_phase_lead is
when "0001" => output.nominal_poa_phase_lead := 1;
when "0010" => output.nominal_poa_phase_lead := 2;
when "0011" => output.nominal_poa_phase_lead := 3;
when "0000" => output.nominal_poa_phase_lead := 0;
when others => report regs_report_prefix &
"there is an unsupported nominal postamble phase lead paramater set (" &
natural'image(to_integer(unsigned(ip_regs.rw_param_reg.nominal_poa_phase_lead))) &
")" severity error;
end case;
if ( (ip_regs.mr_reg_a.mr1(2) = '1')
or (ip_regs.mr_reg_a.mr1(6) = '1')
or (ip_regs.mr_reg_a.mr1(9) = '1')
) then
output.odt_enabled := true;
end if;
output.pll_360_sweeps := to_integer(unsigned(ip_regs.rw_param_reg.pll_360_sweeps));
output.maximum_poa_delay := to_integer(unsigned(ip_regs.rw_param_reg.maximum_poa_delay));
output.extend_octrt_by := to_integer(unsigned(ip_regs.rw_param_reg.extend_octrt_by));
output.delay_octrt_by := to_integer(unsigned(ip_regs.rw_param_reg.delay_octrt_by));
output.tracking_period_ms := to_integer(unsigned(ip_regs.rw_if_test.tracking_period_ms));
return output;
end function;
function pack_record (ip_regs : t_rw_regs) return t_mmi_pll_reconfig is
variable output : t_mmi_pll_reconfig;
begin
output.pll_phs_shft_phase_sel := ip_regs.rw_if_test.pll_phs_shft_phase_sel;
output.pll_phs_shft_up_wc := ip_regs.rw_if_test.pll_phs_shft_up_wc;
output.pll_phs_shft_dn_wc := ip_regs.rw_if_test.pll_phs_shft_dn_wc;
return output;
end function;
function pack_record (ip_regs : t_rw_regs) return t_admin_ctrl is
variable output : t_admin_ctrl := defaults;
begin
output.mr0 := ip_regs.mr_reg_a.mr0;
output.mr1 := ip_regs.mr_reg_a.mr1;
output.mr2 := ip_regs.mr_reg_b.mr2;
output.mr3 := ip_regs.mr_reg_b.mr3;
return output;
end function;
function pack_record (ip_regs : t_rw_regs) return t_mmi_ctrl is
variable output : t_mmi_ctrl := defaults;
begin
output.hl_css := to_t_hl_css_reg (ip_regs.rw_hl_css);
output.calibration_start := ip_regs.rw_hl_css.cal_start;
output.tracking_period_ms := to_integer(unsigned(ip_regs.rw_if_test.tracking_period_ms));
output.tracking_orvd_to_10ms := ip_regs.rw_if_test.tracking_units_are_10us;
return output;
end function;
-- >>>>>>>>>>>>>>>>>>>>>>>>>>
-- Helper functions :
-- >>>>>>>>>>>>>>>>>>>>>>>>>>
function to_t_hl_css_reg (hl_css : t_hl_css
) return t_hl_css_reg is
variable output : t_hl_css_reg := defaults;
begin
output.phy_initialise_dis := hl_css.hl_css(c_hl_css_reg_phy_initialise_dis_bit);
output.init_dram_dis := hl_css.hl_css(c_hl_css_reg_init_dram_dis_bit);
output.write_ihi_dis := hl_css.hl_css(c_hl_css_reg_write_ihi_dis_bit);
output.cal_dis := hl_css.hl_css(c_hl_css_reg_cal_dis_bit);
output.write_btp_dis := hl_css.hl_css(c_hl_css_reg_write_btp_dis_bit);
output.write_mtp_dis := hl_css.hl_css(c_hl_css_reg_write_mtp_dis_bit);
output.read_mtp_dis := hl_css.hl_css(c_hl_css_reg_read_mtp_dis_bit);
output.rrp_reset_dis := hl_css.hl_css(c_hl_css_reg_rrp_reset_dis_bit);
output.rrp_sweep_dis := hl_css.hl_css(c_hl_css_reg_rrp_sweep_dis_bit);
output.rrp_seek_dis := hl_css.hl_css(c_hl_css_reg_rrp_seek_dis_bit);
output.rdv_dis := hl_css.hl_css(c_hl_css_reg_rdv_dis_bit);
output.poa_dis := hl_css.hl_css(c_hl_css_reg_poa_dis_bit);
output.was_dis := hl_css.hl_css(c_hl_css_reg_was_dis_bit);
output.adv_rd_lat_dis := hl_css.hl_css(c_hl_css_reg_adv_rd_lat_dis_bit);
output.adv_wr_lat_dis := hl_css.hl_css(c_hl_css_reg_adv_wr_lat_dis_bit);
output.prep_customer_mr_setup_dis := hl_css.hl_css(c_hl_css_reg_prep_customer_mr_setup_dis_bit);
output.tracking_dis := hl_css.hl_css(c_hl_css_reg_tracking_dis_bit);
return output;
end function;
-- pack the ack seen record element into a std_logic_vector
function pack_ack_seen ( cal_stage_ack_seen : in t_cal_stage_ack_seen
) return std_logic_vector is
variable v_output: std_logic_vector(c_hl_ccs_num_stages-1 downto 0);
variable v_start : natural range 0 to c_hl_ccs_num_stages-1;
begin
v_output := (others => '0');
v_output(c_hl_css_reg_cal_dis_bit ) := cal_stage_ack_seen.cal;
v_output(c_hl_css_reg_phy_initialise_dis_bit ) := cal_stage_ack_seen.phy_initialise;
v_output(c_hl_css_reg_init_dram_dis_bit ) := cal_stage_ack_seen.init_dram;
v_output(c_hl_css_reg_write_ihi_dis_bit ) := cal_stage_ack_seen.write_ihi;
v_output(c_hl_css_reg_write_btp_dis_bit ) := cal_stage_ack_seen.write_btp;
v_output(c_hl_css_reg_write_mtp_dis_bit ) := cal_stage_ack_seen.write_mtp;
v_output(c_hl_css_reg_read_mtp_dis_bit ) := cal_stage_ack_seen.read_mtp;
v_output(c_hl_css_reg_rrp_reset_dis_bit ) := cal_stage_ack_seen.rrp_reset;
v_output(c_hl_css_reg_rrp_sweep_dis_bit ) := cal_stage_ack_seen.rrp_sweep;
v_output(c_hl_css_reg_rrp_seek_dis_bit ) := cal_stage_ack_seen.rrp_seek;
v_output(c_hl_css_reg_rdv_dis_bit ) := cal_stage_ack_seen.rdv;
v_output(c_hl_css_reg_poa_dis_bit ) := cal_stage_ack_seen.poa;
v_output(c_hl_css_reg_was_dis_bit ) := cal_stage_ack_seen.was;
v_output(c_hl_css_reg_adv_rd_lat_dis_bit ) := cal_stage_ack_seen.adv_rd_lat;
v_output(c_hl_css_reg_adv_wr_lat_dis_bit ) := cal_stage_ack_seen.adv_wr_lat;
v_output(c_hl_css_reg_prep_customer_mr_setup_dis_bit) := cal_stage_ack_seen.prep_customer_mr_setup;
v_output(c_hl_css_reg_tracking_dis_bit ) := cal_stage_ack_seen.tracking_setup;
return v_output;
end function;
-- reg encoding of current stage
function encode_current_stage (ctrl_cmd_id : t_ctrl_cmd_id
) return std_logic_vector is
variable output : std_logic_vector(7 downto 0);
begin
case ctrl_cmd_id is
when cmd_idle => output := X"00";
when cmd_phy_initialise => output := X"01";
when cmd_init_dram |
cmd_prog_cal_mr => output := X"02";
when cmd_write_ihi => output := X"03";
when cmd_write_btp => output := X"04";
when cmd_write_mtp => output := X"05";
when cmd_read_mtp => output := X"06";
when cmd_rrp_reset => output := X"07";
when cmd_rrp_sweep => output := X"08";
when cmd_rrp_seek => output := X"09";
when cmd_rdv => output := X"0A";
when cmd_poa => output := X"0B";
when cmd_was => output := X"0C";
when cmd_prep_adv_rd_lat => output := X"0D";
when cmd_prep_adv_wr_lat => output := X"0E";
when cmd_prep_customer_mr_setup => output := X"0F";
when cmd_tr_due => output := X"10";
when others =>
null;
report regs_report_prefix & "unknown cal command (" & t_ctrl_cmd_id'image(ctrl_cmd_id) & ") seen in encode_current_stage function" severity failure;
end case;
return output;
end function;
-- reg encoding of current active block
function encode_active_block (active_block : t_ctrl_active_block
) return std_logic_vector is
variable output : std_logic_vector(3 downto 0);
begin
case active_block is
when idle => output := X"0";
when admin => output := X"1";
when dgwb => output := X"2";
when dgrb => output := X"3";
when proc => output := X"4";
when setup => output := X"5";
when iram => output := X"6";
when others =>
output := X"7";
report regs_report_prefix & "unknown active_block seen in encode_active_block function" severity failure;
end case;
return output;
end function;
--
end memphy_alt_mem_phy_regs_pkg;
--
-- -----------------------------------------------------------------------------
-- Abstract : mmi block for the non-levelling AFI PHY sequencer
-- This is an optional block with an Avalon interface and status
-- register instantiations to enhance the debug capabilities of
-- the sequencer. The format of the block is:
-- a) an Avalon interface which supports different avalon and
-- sequencer clock sources
-- b) mmi status registers (which hold information about the
-- successof the calibration)
-- c) a read interface to the iram to enable debug through the
-- avalon interface.
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.memphy_alt_mem_phy_record_pkg.all;
--
entity memphy_alt_mem_phy_mmi is
generic (
-- physical interface width definitions
MEM_IF_DQS_WIDTH : natural;
MEM_IF_DWIDTH : natural;
MEM_IF_DM_WIDTH : natural;
MEM_IF_DQ_PER_DQS : natural;
MEM_IF_DQS_CAPTURE : natural;
DWIDTH_RATIO : natural;
CLOCK_INDEX_WIDTH : natural;
MEM_IF_CLK_PAIR_COUNT : natural;
MEM_IF_ADDR_WIDTH : natural;
MEM_IF_BANKADDR_WIDTH : natural;
MEM_IF_NUM_RANKS : natural;
ADV_LAT_WIDTH : natural;
RESYNCHRONISE_AVALON_DBG : natural;
AV_IF_ADDR_WIDTH : natural;
MEM_IF_MEMTYPE : string;
-- setup / algorithm information
NOM_DQS_PHASE_SETTING : natural;
SCAN_CLK_DIVIDE_BY : natural;
RDP_ADDR_WIDTH : natural;
PLL_STEPS_PER_CYCLE : natural;
IOE_PHASES_PER_TCK : natural;
IOE_DELAYS_PER_PHS : natural;
MEM_IF_CLK_PS : natural;
-- initial mode register settings
PHY_DEF_MR_1ST : std_logic_vector(15 downto 0);
PHY_DEF_MR_2ND : std_logic_vector(15 downto 0);
PHY_DEF_MR_3RD : std_logic_vector(15 downto 0);
PHY_DEF_MR_4TH : std_logic_vector(15 downto 0);
PRESET_RLAT : natural; -- read latency preset value
CAPABILITIES : natural; -- sequencer capabilities flags
USE_IRAM : std_logic; -- RFU
IRAM_AWIDTH : natural;
TRACKING_INTERVAL_IN_MS : natural;
READ_LAT_WIDTH : natural
);
port (
-- clk / reset
clk : in std_logic;
rst_n : in std_logic;
--synchronous Avalon debug interface (internally re-synchronised to input clock)
dbg_seq_clk : in std_logic;
dbg_seq_rst_n : in std_logic;
dbg_seq_addr : in std_logic_vector(AV_IF_ADDR_WIDTH -1 downto 0);
dbg_seq_wr : in std_logic;
dbg_seq_rd : in std_logic;
dbg_seq_cs : in std_logic;
dbg_seq_wr_data : in std_logic_vector(31 downto 0);
seq_dbg_rd_data : out std_logic_vector(31 downto 0);
seq_dbg_waitrequest : out std_logic;
-- mmi to admin interface
regs_admin_ctrl : out t_admin_ctrl;
admin_regs_status : in t_admin_stat;
trefi_failure : in std_logic;
-- mmi to iram interface
mmi_iram : out t_iram_ctrl;
mmi_iram_enable_writes : out std_logic;
iram_status : in t_iram_stat;
-- mmi to control interface
mmi_ctrl : out t_mmi_ctrl;
ctrl_mmi : in t_ctrl_mmi;
int_ac_1t : in std_logic;
invert_ac_1t : out std_logic;
-- global parameterisation record
parameterisation_rec : out t_algm_paramaterisation;
-- mmi pll interface
pll_mmi : in t_pll_mmi;
mmi_pll : out t_mmi_pll_reconfig;
-- codvw status signals
dgrb_mmi : in t_dgrb_mmi
);
end entity;
library work;
-- The registers package (alt_mem_phy_regs_pkg) is used to combine the definition of the
-- registers for the mmi status registers and functions/procedures applied to the registers
--
use work.memphy_alt_mem_phy_regs_pkg.all;
-- The iram address package (alt_mem_phy_iram_addr_pkg) is used to define the base addresses used
-- for iram writes during calibration
--
use work.memphy_alt_mem_phy_iram_addr_pkg.all;
-- The constant package (alt_mem_phy_constants_pkg) contains global 'constants' which are fixed
-- thoughout the sequencer and will not change (for constants which may change between sequencer
-- instances generics are used)
--
use work.memphy_alt_mem_phy_constants_pkg.all;
--
architecture struct of memphy_alt_mem_phy_mmi IS
-- maximum function
function max (a, b : natural) return natural is
begin
if a > b then
return a;
else
return b;
end if;
end function;
-- -------------------------------------------
-- constant definitions
-- -------------------------------------------
constant c_pll_360_sweeps : natural := rrp_pll_phase_mult(DWIDTH_RATIO, MEM_IF_DQS_CAPTURE);
constant c_response_lat : natural := 6;
constant c_codeword : std_logic_vector(31 downto 0) := c_mmi_access_codeword;
constant c_int_iram_start_size : natural := max(IRAM_AWIDTH, 4);
-- enable for ctrl state machine states
constant c_slv_hl_stage_enable : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(CAPABILITIES, 32));
constant c_hl_stage_enable : std_logic_vector(c_hl_ccs_num_stages-1 downto 0) := c_slv_hl_stage_enable(c_hl_ccs_num_stages-1 downto 0);
-- a prefix for all report signals to identify phy and sequencer block
--
constant mmi_report_prefix : string := "memphy_alt_mem_phy_seq (mmi) : ";
-- --------------------------------------------
-- internal signals
-- --------------------------------------------
-- internal clock domain register interface signals
signal int_wdata : std_logic_vector(31 downto 0);
signal int_rdata : std_logic_vector(31 downto 0);
signal int_address : std_logic_vector(AV_IF_ADDR_WIDTH-1 downto 0);
signal int_read : std_logic;
signal int_cs : std_logic;
signal int_write : std_logic;
signal waitreq_int : std_logic;
-- register storage
-- contains:
-- read only (ro_regs)
-- read/write (rw_regs)
-- enable_writes flag
signal mmi_regs : t_mmi_regs := defaults;
signal mmi_rw_regs_initialised : std_logic;
-- this counter ensures that the mmi waits for c_response_lat clocks before
-- responding to a new Avalon request
signal waitreq_count : natural range 0 to 15;
signal waitreq_count_is_zero : std_logic;
-- register error signals
signal int_ac_1t_r : std_logic;
signal trefi_failure_r : std_logic;
-- iram ready - calibration complete and USE_IRAM high
signal iram_ready : std_logic;
begin -- architecture struct
-- the following signals are reserved for future use
invert_ac_1t <= '0';
-- --------------------------------------------------------------
-- generate for synchronous avalon interface
-- --------------------------------------------------------------
simply_registered_avalon : if RESYNCHRONISE_AVALON_DBG = 0 generate
begin
process (rst_n, clk)
begin
if rst_n = '0' then
int_wdata <= (others => '0');
int_address <= (others => '0');
int_read <= '0';
int_write <= '0';
int_cs <= '0';
elsif rising_edge(clk) then
int_wdata <= dbg_seq_wr_data;
int_address <= dbg_seq_addr;
int_read <= dbg_seq_rd;
int_write <= dbg_seq_wr;
int_cs <= dbg_seq_cs;
end if;
end process;
seq_dbg_rd_data <= int_rdata;
seq_dbg_waitrequest <= waitreq_int and (dbg_seq_rd or dbg_seq_wr) and dbg_seq_cs;
end generate simply_registered_avalon;
-- --------------------------------------------------------------
-- clock domain crossing for asynchronous mmi interface
-- --------------------------------------------------------------
re_synchronise_avalon : if RESYNCHRONISE_AVALON_DBG = 1 generate
--clock domain crossing signals
signal ccd_new_cmd : std_logic;
signal ccd_new_cmd_ack : std_logic;
signal ccd_cmd_done : std_logic;
signal ccd_cmd_done_ack : std_logic;
signal ccd_rd_data : std_logic_vector(dbg_seq_wr_data'range);
signal ccd_cmd_done_ack_t : std_logic;
signal ccd_cmd_done_ack_2t : std_logic;
signal ccd_cmd_done_ack_3t : std_logic;
signal ccd_cmd_done_t : std_logic;
signal ccd_cmd_done_2t : std_logic;
signal ccd_cmd_done_3t : std_logic;
signal ccd_new_cmd_t : std_logic;
signal ccd_new_cmd_2t : std_logic;
signal ccd_new_cmd_3t : std_logic;
signal ccd_new_cmd_ack_t : std_logic;
signal ccd_new_cmd_ack_2t : std_logic;
signal ccd_new_cmd_ack_3t : std_logic;
signal cmd_pending : std_logic;
signal seq_clk_waitreq_int : std_logic;
begin
process (rst_n, clk)
begin
if rst_n = '0' then
int_wdata <= (others => '0');
int_address <= (others => '0');
int_read <= '0';
int_write <= '0';
int_cs <= '0';
ccd_new_cmd_ack <= '0';
ccd_new_cmd_t <= '0';
ccd_new_cmd_2t <= '0';
ccd_new_cmd_3t <= '0';
elsif rising_edge(clk) then
ccd_new_cmd_t <= ccd_new_cmd;
ccd_new_cmd_2t <= ccd_new_cmd_t;
ccd_new_cmd_3t <= ccd_new_cmd_2t;
if ccd_new_cmd_3t = '0' and ccd_new_cmd_2t = '1' then
int_wdata <= dbg_seq_wr_data;
int_address <= dbg_seq_addr;
int_read <= dbg_seq_rd;
int_write <= dbg_seq_wr;
int_cs <= '1';
ccd_new_cmd_ack <= '1';
elsif ccd_new_cmd_3t = '1' and ccd_new_cmd_2t = '0' then
ccd_new_cmd_ack <= '0';
end if;
if int_cs = '1' and waitreq_int= '0' then
int_cs <= '0';
int_read <= '0';
int_write <= '0';
end if;
end if;
end process;
-- process to generate new cmd
process (dbg_seq_rst_n, dbg_seq_clk)
begin
if dbg_seq_rst_n = '0' then
ccd_new_cmd <= '0';
ccd_new_cmd_ack_t <= '0';
ccd_new_cmd_ack_2t <= '0';
ccd_new_cmd_ack_3t <= '0';
cmd_pending <= '0';
elsif rising_edge(dbg_seq_clk) then
ccd_new_cmd_ack_t <= ccd_new_cmd_ack;
ccd_new_cmd_ack_2t <= ccd_new_cmd_ack_t;
ccd_new_cmd_ack_3t <= ccd_new_cmd_ack_2t;
if ccd_new_cmd = '0' and dbg_seq_cs = '1' and cmd_pending = '0' then
ccd_new_cmd <= '1';
cmd_pending <= '1';
elsif ccd_new_cmd_ack_2t = '1' and ccd_new_cmd_ack_3t = '0' then
ccd_new_cmd <= '0';
end if;
-- use falling edge of cmd_done
if cmd_pending = '1' and ccd_cmd_done_2t = '0' and ccd_cmd_done_3t = '1' then
cmd_pending <= '0';
end if;
end if;
end process;
-- process to take read data back and transfer it across the clock domains
process (rst_n, clk)
begin
if rst_n = '0' then
ccd_cmd_done <= '0';
ccd_rd_data <= (others => '0');
ccd_cmd_done_ack_3t <= '0';
ccd_cmd_done_ack_2t <= '0';
ccd_cmd_done_ack_t <= '0';
elsif rising_edge(clk) then
if ccd_cmd_done_ack_2t = '1' and ccd_cmd_done_ack_3t = '0' then
ccd_cmd_done <= '0';
elsif waitreq_int = '0' then
ccd_cmd_done <= '1';
ccd_rd_data <= int_rdata;
end if;
ccd_cmd_done_ack_3t <= ccd_cmd_done_ack_2t;
ccd_cmd_done_ack_2t <= ccd_cmd_done_ack_t;
ccd_cmd_done_ack_t <= ccd_cmd_done_ack;
end if;
end process;
process (dbg_seq_rst_n, dbg_seq_clk)
begin
if dbg_seq_rst_n = '0' then
ccd_cmd_done_ack <= '0';
ccd_cmd_done_3t <= '0';
ccd_cmd_done_2t <= '0';
ccd_cmd_done_t <= '0';
seq_dbg_rd_data <= (others => '0');
seq_clk_waitreq_int <= '1';
elsif rising_edge(dbg_seq_clk) then
seq_clk_waitreq_int <= '1';
if ccd_cmd_done_2t = '1' and ccd_cmd_done_3t = '0' then
seq_clk_waitreq_int <= '0';
ccd_cmd_done_ack <= '1';
seq_dbg_rd_data <= ccd_rd_data; -- if read
elsif ccd_cmd_done_2t = '0' and ccd_cmd_done_3t = '1' then
ccd_cmd_done_ack <= '0';
end if;
ccd_cmd_done_3t <= ccd_cmd_done_2t;
ccd_cmd_done_2t <= ccd_cmd_done_t;
ccd_cmd_done_t <= ccd_cmd_done;
end if;
end process;
seq_dbg_waitrequest <= seq_clk_waitreq_int and (dbg_seq_rd or dbg_seq_wr) and dbg_seq_cs;
end generate re_synchronise_avalon;
-- register some inputs for speed.
process (rst_n, clk)
begin
if rst_n = '0' then
int_ac_1t_r <= '0';
trefi_failure_r <= '0';
elsif rising_edge(clk) then
int_ac_1t_r <= int_ac_1t;
trefi_failure_r <= trefi_failure;
end if;
end process;
-- mmi not able to write to iram in current instance of mmi block
mmi_iram_enable_writes <= '0';
-- check if iram ready
process (rst_n, clk)
begin
if rst_n = '0' then
iram_ready <= '0';
elsif rising_edge(clk) then
if USE_IRAM = '0' then
iram_ready <= '0';
else
if ctrl_mmi.ctrl_calibration_success = '1' or ctrl_mmi.ctrl_calibration_fail = '1' then
iram_ready <= '1';
else
iram_ready <= '0';
end if;
end if;
end if;
end process;
-- --------------------------------------------------------------
-- single registered process for mmi access.
-- --------------------------------------------------------------
process (rst_n, clk)
variable v_mmi_regs : t_mmi_regs;
begin
if rst_n = '0' then
mmi_regs <= defaults;
mmi_rw_regs_initialised <= '0';
-- this register records whether the c_codeword has been written to address 0x0001
-- once it has, then other writes are accepted.
mmi_regs.enable_writes <= '0';
int_rdata <= (others => '0');
waitreq_int <= '1';
-- clear wait request counter
waitreq_count <= 0;
waitreq_count_is_zero <= '1';
-- iram interface defaults
mmi_iram <= defaults;
elsif rising_edge(clk) then
-- default assignment
waitreq_int <= '1';
write_clear(mmi_regs.rw_regs);
-- only initialise rw_regs once after hard reset
if mmi_rw_regs_initialised = '0' then
mmi_rw_regs_initialised <= '1';
--reset all read/write regs and read path ouput registers and apply default MRS Settings.
mmi_regs.rw_regs <= defaults(PHY_DEF_MR_1ST,
PHY_DEF_MR_2ND,
PHY_DEF_MR_3RD,
PHY_DEF_MR_4TH,
NOM_DQS_PHASE_SETTING,
PLL_STEPS_PER_CYCLE,
c_pll_360_sweeps, -- number of times 360 degrees is swept
TRACKING_INTERVAL_IN_MS,
c_hl_stage_enable);
end if;
-- bit packing input data structures into the ro_regs structure, for reading
mmi_regs.ro_regs <= defaults(dgrb_mmi,
ctrl_mmi,
pll_mmi,
mmi_regs.rw_regs.rw_if_test,
USE_IRAM,
MEM_IF_DQS_CAPTURE,
int_ac_1t_r,
trefi_failure_r,
iram_status,
IRAM_AWIDTH);
-- write has priority over read
if int_write = '1' and int_cs = '1' and waitreq_count_is_zero = '1' and waitreq_int = '1' then
-- mmi local register write
if to_integer(unsigned(int_address(int_address'high downto 4))) = 0 then
v_mmi_regs := mmi_regs;
write(v_mmi_regs, to_integer(unsigned(int_address(3 downto 0))), int_wdata);
if mmi_regs.enable_writes = '1' then
v_mmi_regs.rw_regs.rw_hl_css.hl_css := c_hl_stage_enable or v_mmi_regs.rw_regs.rw_hl_css.hl_css;
end if;
mmi_regs <= v_mmi_regs;
-- handshake for safe transactions
waitreq_int <= '0';
waitreq_count <= c_response_lat;
-- iram write just handshake back (no write supported)
else
waitreq_int <= '0';
waitreq_count <= c_response_lat;
end if;
elsif int_read = '1' and int_cs = '1' and waitreq_count_is_zero = '1' and waitreq_int = '1' then
-- mmi local register read
if to_integer(unsigned(int_address(int_address'high downto 4))) = 0 then
int_rdata <= read(mmi_regs, to_integer(unsigned(int_address(3 downto 0))));
waitreq_count <= c_response_lat;
waitreq_int <= '0'; -- acknowledge read command regardless.
-- iram being addressed
elsif to_integer(unsigned(int_address(int_address'high downto c_int_iram_start_size))) = 1
and iram_ready = '1'
then
mmi_iram.read <= '1';
mmi_iram.addr <= to_integer(unsigned(int_address(IRAM_AWIDTH -1 downto 0)));
if iram_status.done = '1' then
waitreq_int <= '0';
mmi_iram.read <= '0';
waitreq_count <= c_response_lat;
int_rdata <= iram_status.rdata;
end if;
else -- respond and keep the interface from hanging
int_rdata <= x"DEADBEEF";
waitreq_int <= '0';
waitreq_count <= c_response_lat;
end if;
elsif waitreq_count /= 0 then
waitreq_count <= waitreq_count -1;
-- if performing a write, set back to defaults. If not, default anyway
mmi_iram <= defaults;
end if;
if waitreq_count = 1 or waitreq_count = 0 then
waitreq_count_is_zero <= '1'; -- as it will be next clock cycle
else
waitreq_count_is_zero <= '0';
end if;
-- supply iram read data when ready
if iram_status.done = '1' then
int_rdata <= iram_status.rdata;
end if;
end if;
end process;
-- pack the registers into the output data structures
regs_admin_ctrl <= pack_record(mmi_regs.rw_regs);
parameterisation_rec <= pack_record(mmi_regs.rw_regs);
mmi_pll <= pack_record(mmi_regs.rw_regs);
mmi_ctrl <= pack_record(mmi_regs.rw_regs);
end architecture struct;
--
-- -----------------------------------------------------------------------------
-- Abstract : admin block for the non-levelling AFI PHY sequencer
-- The admin block supports the autonomy of the sequencer from
-- the memory interface controller. In this task admin handles
-- memory initialisation (incl. the setting of mode registers)
-- and memory refresh, bank activation and pre-charge commands
-- (during memory interface calibration). Once calibration is
-- complete admin is 'idle' and control of the memory device is
-- passed to the users chosen memory interface controller. The
-- supported memory types are exclusively DDR, DDR2 and DDR3.
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.memphy_alt_mem_phy_record_pkg.all;
-- The address and command package (alt_mem_phy_addr_cmd_pkg) is used to combine DRAM address
-- and command signals in one record and unify the functions operating on this record.
--
use work.memphy_alt_mem_phy_addr_cmd_pkg.all;
--
entity memphy_alt_mem_phy_admin is
generic (
-- physical interface width definitions
MEM_IF_DQS_WIDTH : natural;
MEM_IF_DWIDTH : natural;
MEM_IF_DM_WIDTH : natural;
MEM_IF_DQ_PER_DQS : natural;
DWIDTH_RATIO : natural;
CLOCK_INDEX_WIDTH : natural;
MEM_IF_CLK_PAIR_COUNT : natural;
MEM_IF_ADDR_WIDTH : natural;
MEM_IF_BANKADDR_WIDTH : natural;
MEM_IF_NUM_RANKS : natural;
ADV_LAT_WIDTH : natural;
MEM_IF_DQSN_EN : natural;
MEM_IF_MEMTYPE : string;
-- calibration address information
MEM_IF_CAL_BANK : natural; -- Bank to which calibration data is written
MEM_IF_CAL_BASE_ROW : natural;
GENERATE_ADDITIONAL_DBG_RTL : natural;
NON_OP_EVAL_MD : string; -- non_operational evaluation mode (used when GENERATE_ADDITIONAL_DBG_RTL = 1)
-- timing parameters
MEM_IF_CLK_PS : natural;
TINIT_TCK : natural; -- initial delay
TINIT_RST : natural -- used for DDR3 device support
);
port (
-- clk / reset
clk : in std_logic;
rst_n : in std_logic;
-- the 2 signals below are unused for non-levelled sequencer (maintained for equivalent interface to levelled sequencer)
mem_ac_swapped_ranks : in std_logic_vector(MEM_IF_NUM_RANKS - 1 downto 0);
ctl_cal_byte_lanes : in std_logic_vector(MEM_IF_NUM_RANKS * MEM_IF_DQS_WIDTH - 1 downto 0);
-- addr/cmd interface
seq_ac : out t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
seq_ac_sel : out std_logic;
-- determined from MR settings
enable_odt : out std_logic;
-- interface to the mmi block
regs_admin_ctrl_rec : in t_admin_ctrl;
admin_regs_status_rec : out t_admin_stat;
trefi_failure : out std_logic;
-- interface to the ctrl block
ctrl_admin : in t_ctrl_command;
admin_ctrl : out t_ctrl_stat;
-- interface with dgrb/dgwb blocks
ac_access_req : in std_logic;
ac_access_gnt : out std_logic;
-- calibration status signals (from ctrl block)
cal_fail : in std_logic;
cal_success : in std_logic;
-- recalibrate request issued
ctl_recalibrate_req : in std_logic
);
end entity;
library work;
-- The constant package (alt_mem_phy_constants_pkg) contains global 'constants' which are fixed
-- thoughout the sequencer and will not change (for constants which may change between sequencer
-- instances generics are used)
--
use work.memphy_alt_mem_phy_constants_pkg.all;
--
architecture struct of memphy_alt_mem_phy_admin is
constant c_max_mode_reg_index : natural := 12;
-- timing below is safe for range 80-400MHz operation - taken from worst case DDR2 (JEDEC JESD79-2E) / DDR3 (JESD79-3B)
-- Note: timings account for worst case use for both full rate and half rate ALTMEMPHY interfaces
constant c_init_prech_delay : natural := 162; -- precharge delay (360ns = tRFC+10ns) (TXPR for DDR3)
constant c_trp_in_clks : natural := 8; -- set equal to trp / tck (trp = 15ns)
constant c_tmrd_in_clks : natural := 4; -- maximum 4 clock cycles (DDR3)
constant c_tmod_in_clks : natural := 8; -- ODT update from MRS command (tmod = 12ns (DDR2))
constant c_trrd_min_in_clks : natural := 4; -- minimum clk cycles between bank activate cmds (10ns)
constant c_trcd_min_in_clks : natural := 8; -- minimum bank activate to read/write cmd (15ns)
-- the 2 constants below are parameterised to MEM_IF_CLK_PS due to the large range of possible clock frequency
constant c_trfc_min_in_clks : natural := (350000/MEM_IF_CLK_PS)/(DWIDTH_RATIO/2) + 2; -- refresh-refresh timing (worst case trfc = 350 ns (DDR3))
constant c_trefi_min_in_clks : natural := (3900000/MEM_IF_CLK_PS)/(DWIDTH_RATIO/2) - 2; -- average refresh interval worst case trefi = 3.9 us (industrial grade devices)
constant c_max_num_stacked_refreshes : natural := 8; -- max no. of stacked refreshes allowed
constant c_max_wait_value : natural := 4; -- delay before moving from s_idle to s_refresh_state
-- DDR3 specific:
constant c_zq_init_duration_clks : natural := 514; -- full rate (worst case) cycle count for tZQCL init
constant c_tzqcs : natural := 66; -- number of full rate clock cycles
-- below is a record which is used to parameterise the address and command signals (addr_cmd) used in this block
constant c_seq_addr_cmd_config : t_addr_cmd_config_rec := set_config_rec(MEM_IF_ADDR_WIDTH, MEM_IF_BANKADDR_WIDTH, MEM_IF_NUM_RANKS, DWIDTH_RATIO, MEM_IF_MEMTYPE);
-- a prefix for all report signals to identify phy and sequencer block
--
constant admin_report_prefix : string := "memphy_alt_mem_phy_seq (admin) : ";
-- state type for admin_state (main state machine of admin block)
type t_admin_state is
(
s_reset, -- reset state
s_run_init_seq, -- run the initialisation sequence (up to but not including MR setting)
s_program_cal_mrs, -- program the mode registers ready for calibration (this is the user settings
-- with some overloads and extra init functionality)
s_idle, -- idle (i.e. maintaining refresh to max)
s_topup_refresh, -- make sure refreshes are maxed out before going on.
s_topup_refresh_done, -- wait for tRFC after refresh command
s_zq_cal_short, -- ZQCAL short command (issued prior to activate) - DDR3 only
s_access_act, -- activate
s_access, -- dgrb, dgwb accesses,
s_access_precharge, -- precharge all memory banks
s_prog_user_mrs, -- program user mode register settings
s_dummy_wait, -- wait before going to s_refresh state
s_refresh, -- issue a memory refresh command
s_refresh_done, -- wait for trfc after refresh command
s_non_operational -- special debug state to toggle interface if calibration fails
);
signal state : t_admin_state; -- admin block state machine
-- state type for ac_state
type t_ac_state is
( s_0 ,
s_1 ,
s_2 ,
s_3 ,
s_4 ,
s_5 ,
s_6 ,
s_7 ,
s_8 ,
s_9 ,
s_10,
s_11,
s_12,
s_13,
s_14);
-- enforce one-hot fsm encoding
attribute syn_encoding : string;
attribute syn_encoding of t_ac_state : TYPE is "one-hot";
signal ac_state : t_ac_state; -- state machine for sub-states of t_admin_state states
signal stage_counter : natural range 0 to 2**18 - 1; -- counter to support memory timing delays
signal stage_counter_zero : std_logic;
signal addr_cmd : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1); -- internal copy of output DRAM addr/cmd signals
signal mem_init_complete : std_logic; -- signifies memory initialisation is complete
signal cal_complete : std_logic; -- calibration complete (equals: cal_success OR cal_fail)
signal int_mr0 : std_logic_vector(regs_admin_ctrl_rec.mr0'range); -- an internal copy of mode register settings
signal int_mr1 : std_logic_vector(regs_admin_ctrl_rec.mr0'range);
signal int_mr2 : std_logic_vector(regs_admin_ctrl_rec.mr0'range);
signal int_mr3 : std_logic_vector(regs_admin_ctrl_rec.mr0'range);
signal refresh_count : natural range c_trefi_min_in_clks downto 0; -- determine when refresh is due
signal refresh_due : std_logic; -- need to do a refresh now
signal refresh_done : std_logic; -- pulse when refresh complete
signal num_stacked_refreshes : natural range 0 to c_max_num_stacked_refreshes - 1; -- can stack upto 8 refreshes (for DDR2)
signal refreshes_maxed : std_logic; -- signal refreshes are maxed out
signal initial_refresh_issued : std_logic; -- to start the refresh counter off
signal ctrl_rec : t_ctrl_command;
-- last state logic
signal command_started : std_logic; -- provides a pulse when admin starts processing a command
signal command_done : std_logic; -- provides a pulse when admin completes processing a command is completed
signal finished_state : std_logic; -- finished current t_admin_state state
signal admin_req_extended : std_logic; -- keep requests for this block asserted until it is an ack is asserted
signal current_cs : natural range 0 to MEM_IF_NUM_RANKS - 1; -- which chip select being programmed at this instance
signal per_cs_init_seen : std_logic_vector(MEM_IF_NUM_RANKS - 1 downto 0);
-- some signals to enable non_operational debug (optimised away if GENERATE_ADDITIONAL_DBG_RTL = 0)
signal nop_toggle_signal : t_addr_cmd_signals;
signal nop_toggle_pin : natural range 0 to MEM_IF_ADDR_WIDTH - 1; -- track which pin in a signal to toggle
signal nop_toggle_value : std_logic;
begin -- architecture struct
-- concurrent assignment of internal addr_cmd to output port seq_ac
process (addr_cmd)
begin
seq_ac <= addr_cmd;
end process;
-- generate calibration complete signal
process (cal_success, cal_fail)
begin
cal_complete <= cal_success or cal_fail;
end process;
-- register the control command record
process (clk, rst_n)
begin
if rst_n = '0' then
ctrl_rec <= defaults;
elsif rising_edge(clk) then
ctrl_rec <= ctrl_admin;
end if;
end process;
-- extend the admin block request until ack is asserted
process (clk, rst_n)
begin
if rst_n = '0' then
admin_req_extended <= '0';
elsif rising_edge(clk) then
if ( (ctrl_rec.command_req = '1') and ( curr_active_block(ctrl_rec.command) = admin) ) then
admin_req_extended <= '1';
elsif command_started = '1' then -- this is effectively a copy of command_ack generation
admin_req_extended <= '0';
end if;
end if;
end process;
-- generate the current_cs signal to track which cs accessed by PHY at any instance
process (clk, rst_n)
begin
if rst_n = '0' then
current_cs <= 0;
elsif rising_edge(clk) then
if ctrl_rec.command_req = '1' then
current_cs <= ctrl_rec.command_op.current_cs;
end if;
end if;
end process;
-- -----------------------------------------------------------------------------
-- refresh logic: DDR/DDR2/DDR3 allows upto 8 refreshes to be "stacked" or queued up.
-- In the idle state, will ensure refreshes are issued when necessary. Then,
-- when an access_request is received, 7 topup refreshes will be done to max out
-- the number of queued refreshes. That way, we know we have the maximum time
-- available before another refresh is due.
-- -----------------------------------------------------------------------------
-- initial_refresh_issued flag: used to sync refresh_count
process (clk, rst_n)
begin
if rst_n = '0' then
initial_refresh_issued <= '0';
elsif rising_edge(clk) then
if cal_complete = '1' then
initial_refresh_issued <= '0';
else
if state = s_refresh_done or
state = s_topup_refresh_done then
initial_refresh_issued <= '1';
end if;
end if;
end if;
end process;
-- refresh timer: used to work out when a refresh is due
process (clk, rst_n)
begin
if rst_n = '0' then
refresh_count <= c_trefi_min_in_clks;
elsif rising_edge(clk) then
if cal_complete = '1' then
refresh_count <= c_trefi_min_in_clks;
else
if refresh_count = 0 or
initial_refresh_issued = '0' or
(refreshes_maxed = '1' and refresh_done = '1') then -- if refresh issued when already maxed
refresh_count <= c_trefi_min_in_clks;
else
refresh_count <= refresh_count - 1;
end if;
end if;
end if;
end process;
-- refresh_due generation: 1 cycle pulse to indicate that c_trefi_min_in_clks has elapsed, and
-- therefore a refresh is due
process (clk, rst_n)
begin
if rst_n = '0' then
refresh_due <= '0';
elsif rising_edge(clk) then
if refresh_count = 0 and cal_complete = '0' then
refresh_due <= '1';
else
refresh_due <= '0';
end if;
end if;
end process;
-- counter to keep track of number of refreshes "stacked". NB: Up to 8
-- refreshes can be stacked.
process (clk, rst_n)
begin
if rst_n = '0' then
num_stacked_refreshes <= 0;
trefi_failure <= '0'; -- default no trefi failure
elsif rising_edge (clk) then
if state = s_reset then
trefi_failure <= '0'; -- default no trefi failure (in restart)
end if;
if cal_complete = '1' then
num_stacked_refreshes <= 0;
else
if refresh_due = '1' and num_stacked_refreshes /= 0 then
num_stacked_refreshes <= num_stacked_refreshes - 1;
elsif refresh_done = '1' and num_stacked_refreshes /= c_max_num_stacked_refreshes - 1 then
num_stacked_refreshes <= num_stacked_refreshes + 1;
end if;
-- debug message if stacked refreshes are depleted and refresh is due
if refresh_due = '1' and num_stacked_refreshes = 0 and initial_refresh_issued = '1' then
report admin_report_prefix & "error refresh is due and num_stacked_refreshes is zero" severity error;
trefi_failure <= '1'; -- persist
end if;
end if;
end if;
end process;
-- generate signal to state if refreshes are maxed out
process (clk, rst_n)
begin
if rst_n = '0' then
refreshes_maxed <= '0';
elsif rising_edge (clk) then
if num_stacked_refreshes < c_max_num_stacked_refreshes - 1 then
refreshes_maxed <= '0';
else
refreshes_maxed <= '1';
end if;
end if;
end process;
-- ----------------------------------------------------
-- Mode register selection
-- -----------------------------------------------------
int_mr0(regs_admin_ctrl_rec.mr0'range) <= regs_admin_ctrl_rec.mr0;
int_mr1(regs_admin_ctrl_rec.mr1'range) <= regs_admin_ctrl_rec.mr1;
int_mr2(regs_admin_ctrl_rec.mr2'range) <= regs_admin_ctrl_rec.mr2;
int_mr3(regs_admin_ctrl_rec.mr3'range) <= regs_admin_ctrl_rec.mr3;
-- -------------------------------------------------------
-- State machine
-- -------------------------------------------------------
process(rst_n, clk)
begin
if rst_n = '0' then
state <= s_reset;
command_done <= '0';
command_started <= '0';
elsif rising_edge(clk) then
-- Last state logic
command_done <= '0';
command_started <= '0';
case state is
when s_reset |
s_non_operational =>
if ctrl_rec.command = cmd_init_dram and admin_req_extended = '1' then
state <= s_run_init_seq;
command_started <= '1';
end if;
when s_run_init_seq =>
if finished_state = '1' then
state <= s_idle;
command_done <= '1';
end if;
when s_program_cal_mrs =>
if finished_state = '1' then
if refreshes_maxed = '0' and mem_init_complete = '1' then -- only refresh if all ranks initialised
state <= s_topup_refresh;
else
state <= s_idle;
end if;
command_done <= '1';
end if;
when s_idle =>
if ac_access_req = '1' then
state <= s_topup_refresh;
elsif ctrl_rec.command = cmd_init_dram and admin_req_extended = '1' then -- start initialisation sequence
state <= s_run_init_seq;
command_started <= '1';
elsif ctrl_rec.command = cmd_prog_cal_mr and admin_req_extended = '1' then -- program mode registers (used for >1 chip select)
state <= s_program_cal_mrs;
command_started <= '1';
-- always enter s_prog_user_mrs via topup refresh
elsif ctrl_rec.command = cmd_prep_customer_mr_setup and admin_req_extended = '1' then
state <= s_topup_refresh;
elsif refreshes_maxed = '0' and mem_init_complete = '1' then -- only refresh once all ranks initialised
state <= s_dummy_wait;
end if;
when s_dummy_wait =>
if finished_state = '1' then
state <= s_refresh;
end if;
when s_topup_refresh =>
if finished_state = '1' then
state <= s_topup_refresh_done;
end if;
when s_topup_refresh_done =>
if finished_state = '1' then -- to ensure trfc is not violated
if refreshes_maxed = '0' then
state <= s_topup_refresh;
elsif ctrl_rec.command = cmd_prep_customer_mr_setup and admin_req_extended = '1' then
state <= s_prog_user_mrs;
command_started <= '1';
elsif ac_access_req = '1' then
if MEM_IF_MEMTYPE = "DDR3" then
state <= s_zq_cal_short;
else
state <= s_access_act;
end if;
else
state <= s_idle;
end if;
end if;
when s_zq_cal_short => -- DDR3 only
if finished_state = '1' then
state <= s_access_act;
end if;
when s_access_act =>
if finished_state = '1' then
state <= s_access;
end if;
when s_access =>
if ac_access_req = '0' then
state <= s_access_precharge;
end if;
when s_access_precharge =>
-- ensure precharge all timer has elapsed.
if finished_state = '1' then
state <= s_idle;
end if;
when s_prog_user_mrs =>
if finished_state = '1' then
state <= s_idle;
command_done <= '1';
end if;
when s_refresh =>
if finished_state = '1' then
state <= s_refresh_done;
end if;
when s_refresh_done =>
if finished_state = '1' then -- to ensure trfc is not violated
if refreshes_maxed = '0' then
state <= s_refresh;
else
state <= s_idle;
end if;
end if;
when others =>
state <= s_reset;
end case;
if cal_complete = '1' then
state <= s_idle;
if GENERATE_ADDITIONAL_DBG_RTL = 1 and cal_success = '0' then
state <= s_non_operational; -- if calibration failed and debug enabled then toggle pins in pre-defined pattern
end if;
end if;
-- if recalibrating then put admin in reset state to
-- avoid issuing refresh commands when not needed
if ctl_recalibrate_req = '1' then
state <= s_reset;
end if;
end if;
end process;
-- --------------------------------------------------
-- process to generate initialisation complete
-- --------------------------------------------------
process (rst_n, clk)
begin
if rst_n = '0' then
mem_init_complete <= '0';
elsif rising_edge(clk) then
if to_integer(unsigned(per_cs_init_seen)) = 2**MEM_IF_NUM_RANKS - 1 then
mem_init_complete <= '1';
else
mem_init_complete <= '0';
end if;
end if;
end process;
-- --------------------------------------------------
-- process to generate addr/cmd.
-- --------------------------------------------------
process(rst_n, clk)
variable v_mr_overload : std_logic_vector(regs_admin_ctrl_rec.mr0'range);
-- required for non_operational state only
variable v_nop_ac_0 : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
variable v_nop_ac_1 : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
begin
if rst_n = '0' then
ac_state <= s_0;
stage_counter <= 0;
stage_counter_zero <= '1';
finished_state <= '0';
seq_ac_sel <= '1';
refresh_done <= '0';
per_cs_init_seen <= (others => '0');
addr_cmd <= int_pup_reset(c_seq_addr_cmd_config);
if GENERATE_ADDITIONAL_DBG_RTL = 1 then
nop_toggle_signal <= addr;
nop_toggle_pin <= 0;
nop_toggle_value <= '0';
end if;
elsif rising_edge(clk) then
finished_state <= '0';
refresh_done <= '0';
-- address / command path control
-- if seq_ac_sel = 1 then sequencer has control of a/c
-- if seq_ac_sel = 0 then memory controller has control of a/c
seq_ac_sel <= '1';
if cal_complete = '1' then
if cal_success = '1' or
GENERATE_ADDITIONAL_DBG_RTL = 0 then -- hand over interface if cal successful or no debug enabled
seq_ac_sel <= '0';
end if;
end if;
-- if recalibration request then take control of a/c path
if ctl_recalibrate_req = '1' then
seq_ac_sel <= '1';
end if;
if state = s_reset then
addr_cmd <= reset(c_seq_addr_cmd_config);
stage_counter <= 0;
elsif state /= s_run_init_seq and
state /= s_non_operational then
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
end if;
if (stage_counter = 1 or stage_counter = 0) then
stage_counter_zero <= '1';
else
stage_counter_zero <= '0';
end if;
if stage_counter_zero /= '1' and state /= s_reset then
stage_counter <= stage_counter -1;
else
stage_counter_zero <= '0';
case state is
when s_run_init_seq =>
per_cs_init_seen <= (others => '0'); -- per cs test
if MEM_IF_MEMTYPE = "DDR" or MEM_IF_MEMTYPE = "DDR2" then
case ac_state is
-- JEDEC (JESD79-2E) stage c
when s_0 to s_9 =>
ac_state <= t_ac_state'succ(ac_state);
stage_counter <= (TINIT_TCK/10)+1;
addr_cmd <= maintain_pd_or_sr(c_seq_addr_cmd_config,
deselect(c_seq_addr_cmd_config, addr_cmd),
2**MEM_IF_NUM_RANKS -1);
-- JEDEC (JESD79-2E) stage d
when s_10 =>
ac_state <= s_11;
stage_counter <= c_init_prech_delay;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
when s_11 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
-- finish sequence by going into s_program_cal_mrs state
when others =>
ac_state <= s_0;
end case;
elsif MEM_IF_MEMTYPE = "DDR3" then -- DDR3 specific initialisation sequence
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= TINIT_RST + 1;
addr_cmd <= reset(c_seq_addr_cmd_config);
when s_1 to s_10 =>
ac_state <= t_ac_state'succ(ac_state);
stage_counter <= (TINIT_TCK/10) + 1;
addr_cmd <= maintain_pd_or_sr(c_seq_addr_cmd_config,
deselect(c_seq_addr_cmd_config, addr_cmd),
2**MEM_IF_NUM_RANKS -1);
when s_11 =>
ac_state <= s_12;
stage_counter <= c_init_prech_delay;
addr_cmd <= deselect(c_seq_addr_cmd_config, addr_cmd);
when s_12 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
-- finish sequence by going into s_program_cal_mrs state
when others =>
ac_state <= s_0;
end case;
else
report admin_report_prefix & "unsupported memory type specified" severity error;
end if;
-- end of initialisation sequence
when s_program_cal_mrs =>
if MEM_IF_MEMTYPE = "DDR2" then -- DDR2 style mode register settings
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= 1;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
-- JEDEC (JESD79-2E) stage d
when s_1 =>
ac_state <= s_2;
stage_counter <= c_trp_in_clks;
addr_cmd <= precharge_all(c_seq_addr_cmd_config, -- configuration
2**current_cs); -- rank
-- JEDEC (JESD79-2E) stage e
when s_2 =>
ac_state <= s_3;
stage_counter <= c_tmrd_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
2, -- mode register number
int_mr2(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
-- JEDEC (JESD79-2E) stage f
when s_3 =>
ac_state <= s_4;
stage_counter <= c_tmrd_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
3, -- mode register number
int_mr3(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
-- JEDEC (JESD79-2E) stage g
when s_4 =>
ac_state <= s_5;
stage_counter <= c_tmrd_in_clks;
v_mr_overload := int_mr1(c_max_mode_reg_index downto 0);
v_mr_overload(0) := '0'; -- override DLL enable
v_mr_overload(9 downto 7) := "000"; -- required in JESD79-2E (but not in JESD79-2B)
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
1, -- mode register number
v_mr_overload , -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
-- JEDEC (JESD79-2E) stage h
when s_5 =>
ac_state <= s_6;
stage_counter <= c_tmod_in_clks;
addr_cmd <= dll_reset(c_seq_addr_cmd_config, -- configuration
int_mr0(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
-- JEDEC (JESD79-2E) stage i
when s_6 =>
ac_state <= s_7;
stage_counter <= c_trp_in_clks;
addr_cmd <= precharge_all(c_seq_addr_cmd_config, -- configuration
2**MEM_IF_NUM_RANKS - 1); -- rank(s)
-- JEDEC (JESD79-2E) stage j
when s_7 =>
ac_state <= s_8;
stage_counter <= c_trfc_min_in_clks;
addr_cmd <= refresh(c_seq_addr_cmd_config, -- configuration
addr_cmd, -- previous value
2**current_cs); -- rank
-- JEDEC (JESD79-2E) stage j - second refresh
when s_8 =>
ac_state <= s_9;
stage_counter <= c_trfc_min_in_clks;
addr_cmd <= refresh(c_seq_addr_cmd_config, -- configuration
addr_cmd, -- previous value
2**current_cs); -- rank
-- JEDEC (JESD79-2E) stage k
when s_9 =>
ac_state <= s_10;
stage_counter <= c_tmrd_in_clks;
v_mr_overload := int_mr0(c_max_mode_reg_index downto 3) & "010"; -- override to burst length 4
v_mr_overload(8) := '0'; -- required in JESD79-2E
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
0, -- mode register number
v_mr_overload, -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
-- JEDEC (JESD79-2E) stage l - wait 200 cycles
when s_10 =>
ac_state <= s_11;
stage_counter <= 200;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
-- JEDEC (JESD79-2E) stage l - OCD default
when s_11 =>
ac_state <= s_12;
stage_counter <= c_tmrd_in_clks;
v_mr_overload := int_mr1(c_max_mode_reg_index downto 0);
v_mr_overload(9 downto 7) := "111"; -- OCD calibration default (i.e. OCD unused)
v_mr_overload(0) := '0'; -- override for DLL enable
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
1, -- mode register number
v_mr_overload , -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
-- JEDEC (JESD79-2E) stage l - OCD cal exit
when s_12 =>
ac_state <= s_13;
stage_counter <= c_tmod_in_clks;
v_mr_overload := int_mr1(c_max_mode_reg_index downto 0);
v_mr_overload(9 downto 7) := "000"; -- OCD calibration exit
v_mr_overload(0) := '0'; -- override for DLL enable
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
1, -- mode register number
v_mr_overload , -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
per_cs_init_seen(current_cs) <= '1';
-- JEDEC (JESD79-2E) stage m - cal finished
when s_13 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
null;
end case;
elsif MEM_IF_MEMTYPE = "DDR" then -- DDR style mode register setting following JEDEC (JESD79E)
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= 1;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
when s_1 =>
ac_state <= s_2;
stage_counter <= c_trp_in_clks;
addr_cmd <= precharge_all(c_seq_addr_cmd_config, -- configuration
2**current_cs); -- rank(s)
when s_2 =>
ac_state <= s_3;
stage_counter <= c_tmrd_in_clks;
v_mr_overload := int_mr1(c_max_mode_reg_index downto 0);
v_mr_overload(0) := '0'; -- override DLL enable
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
1, -- mode register number
v_mr_overload , -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_3 =>
ac_state <= s_4;
stage_counter <= c_tmod_in_clks;
addr_cmd <= dll_reset(c_seq_addr_cmd_config, -- configuration
int_mr0(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_4 =>
ac_state <= s_5;
stage_counter <= c_trp_in_clks;
addr_cmd <= precharge_all(c_seq_addr_cmd_config, -- configuration
2**MEM_IF_NUM_RANKS - 1); -- rank(s)
when s_5 =>
ac_state <= s_6;
stage_counter <= c_trfc_min_in_clks;
addr_cmd <= refresh(c_seq_addr_cmd_config, -- configuration
addr_cmd, -- previous value
2**current_cs); -- rank
when s_6 =>
ac_state <= s_7;
stage_counter <= c_trfc_min_in_clks;
addr_cmd <= refresh(c_seq_addr_cmd_config, -- configuration
addr_cmd, -- previous value
2**current_cs); -- rank
when s_7 =>
ac_state <= s_8;
stage_counter <= c_tmrd_in_clks;
v_mr_overload := int_mr0(c_max_mode_reg_index downto 3) & "010"; -- override to burst length 4
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
0, -- mode register number
v_mr_overload, -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_8 =>
ac_state <= s_9;
stage_counter <= 200;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
per_cs_init_seen(current_cs) <= '1';
when s_9 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
null;
end case;
elsif MEM_IF_MEMTYPE = "DDR3" then
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= c_trp_in_clks;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
when s_1 =>
ac_state <= s_2;
stage_counter <= c_tmrd_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
2, -- mode register number
int_mr2(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_2 =>
ac_state <= s_3;
stage_counter <= c_tmrd_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
3, -- mode register number
int_mr3(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_3 =>
ac_state <= s_4;
stage_counter <= c_tmrd_in_clks;
v_mr_overload := int_mr1(c_max_mode_reg_index downto 0);
v_mr_overload(0) := '0'; -- Override for DLL enable
v_mr_overload(12) := '0'; -- output buffer enable.
v_mr_overload(7) := '0'; -- Disable Write levelling
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
1, -- mode register number
v_mr_overload, -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_4 =>
ac_state <= s_5;
stage_counter <= c_tmod_in_clks;
v_mr_overload := int_mr0(c_max_mode_reg_index downto 0);
v_mr_overload(1 downto 0) := "01"; -- override to on the fly burst length choice
v_mr_overload(7) := '0'; -- test mode not enabled
v_mr_overload(8) := '1'; -- DLL reset
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
0, -- mode register number
v_mr_overload, -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_5 =>
ac_state <= s_6;
stage_counter <= c_zq_init_duration_clks;
addr_cmd <= ZQCL(c_seq_addr_cmd_config, -- configuration
2**current_cs); -- rank
per_cs_init_seen(current_cs) <= '1';
when s_6 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
else
report admin_report_prefix & "unsupported memory type specified" severity error;
end if;
-- end of s_program_cal_mrs case
when s_prog_user_mrs =>
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= 1;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
when s_1 =>
if MEM_IF_MEMTYPE = "DDR" then -- for DDR memory skip MR2/3 because not present
ac_state <= s_4;
else -- for DDR2/DDR3 all MRs programmed
ac_state <= s_2;
end if;
stage_counter <= c_trp_in_clks;
addr_cmd <= precharge_all(c_seq_addr_cmd_config, -- configuration
2**MEM_IF_NUM_RANKS - 1); -- rank(s)
when s_2 =>
ac_state <= s_3;
stage_counter <= c_tmrd_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
2, -- mode register number
int_mr2(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_3 =>
ac_state <= s_4;
stage_counter <= c_tmrd_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
3, -- mode register number
int_mr3(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
if to_integer(unsigned(int_mr3)) /= 0 then
report admin_report_prefix & " mode register 3 is expected to have a value of 0 but has a value of : " &
integer'image(to_integer(unsigned(int_mr3))) severity warning;
end if;
when s_4 =>
ac_state <= s_5;
stage_counter <= c_tmrd_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
1, -- mode register number
int_mr1(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
if (MEM_IF_DQSN_EN = 0) and (int_mr1(10) = '0') and (MEM_IF_MEMTYPE = "DDR2") then
report admin_report_prefix & "mode register and generic conflict:" & LF &
"* generic MEM_IF_DQSN_EN is set to 'disable' DQSN" & LF &
"* user mode register MEM_IF_MR1 bit 10 is set to 'enable' DQSN" severity warning;
end if;
when s_5 =>
ac_state <= s_6;
stage_counter <= c_tmod_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
0, -- mode register number
int_mr0(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_6 =>
ac_state <= s_7;
stage_counter <= 1;
when s_7 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
-- end of s_prog_user_mr case
when s_access_precharge =>
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= 10;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
when s_1 =>
ac_state <= s_2;
stage_counter <= c_trp_in_clks;
addr_cmd <= precharge_all(c_seq_addr_cmd_config, -- configuration
2**MEM_IF_NUM_RANKS - 1); -- rank(s)
when s_2 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
when s_topup_refresh | s_refresh =>
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= 1;
when s_1 =>
ac_state <= s_2;
stage_counter <= 1;
addr_cmd <= refresh(c_seq_addr_cmd_config, -- configuration
addr_cmd, -- previous value
2**MEM_IF_NUM_RANKS - 1); -- rank
when s_2 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
when s_topup_refresh_done | s_refresh_done =>
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= c_trfc_min_in_clks;
refresh_done <= '1'; -- ensure trfc not violated
when s_1 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
when s_zq_cal_short =>
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= 1;
when s_1 =>
ac_state <= s_2;
stage_counter <= c_tzqcs;
addr_cmd <= ZQCS(c_seq_addr_cmd_config, -- configuration
2**current_cs); -- all ranks
when s_2 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
when s_access_act =>
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= c_trrd_min_in_clks;
when s_1 =>
ac_state <= s_2;
stage_counter <= c_trcd_min_in_clks;
addr_cmd <= activate(c_seq_addr_cmd_config, -- configuration
addr_cmd, -- previous value
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_ROW, -- row address
2**current_cs); -- rank
when s_2 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
-- counter to delay transition from s_idle to s_refresh - this is to ensure a refresh command is not sent
-- just as we enter operational state (could cause a trfc violation)
when s_dummy_wait =>
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= c_max_wait_value;
when s_1 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
when s_reset =>
stage_counter <= 1;
-- default some s_non_operational signals
if GENERATE_ADDITIONAL_DBG_RTL = 1 then
nop_toggle_signal <= addr;
nop_toggle_pin <= 0;
nop_toggle_value <= '0';
end if;
when s_non_operational => -- if failed then output a recognised pattern to the memory (Only executes if GENERATE_ADDITIONAL_DBG_RTL set)
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
if NON_OP_EVAL_MD = "PIN_FINDER" then -- toggle pins in turn for 200 memory clk cycles
stage_counter <= 200/(DWIDTH_RATIO/2); -- 200 mem_clk cycles
case nop_toggle_signal is
when addr =>
addr_cmd <= mask (c_seq_addr_cmd_config, addr_cmd, addr, '0');
addr_cmd <= mask (c_seq_addr_cmd_config, addr_cmd, addr, nop_toggle_value, nop_toggle_pin);
nop_toggle_value <= not nop_toggle_value;
if nop_toggle_value = '1' then
if nop_toggle_pin = MEM_IF_ADDR_WIDTH-1 then
nop_toggle_signal <= ba;
nop_toggle_pin <= 0;
else
nop_toggle_pin <= nop_toggle_pin + 1;
end if;
end if;
when ba =>
addr_cmd <= mask (c_seq_addr_cmd_config, addr_cmd, ba, '0');
addr_cmd <= mask (c_seq_addr_cmd_config, addr_cmd, ba, nop_toggle_value, nop_toggle_pin);
nop_toggle_value <= not nop_toggle_value;
if nop_toggle_value = '1' then
if nop_toggle_pin = MEM_IF_BANKADDR_WIDTH-1 then
nop_toggle_signal <= cas_n;
nop_toggle_pin <= 0;
else
nop_toggle_pin <= nop_toggle_pin + 1;
end if;
end if;
when cas_n =>
addr_cmd <= mask (c_seq_addr_cmd_config, addr_cmd, cas_n, nop_toggle_value);
nop_toggle_value <= not nop_toggle_value;
if nop_toggle_value = '1' then
nop_toggle_signal <= ras_n;
end if;
when ras_n =>
addr_cmd <= mask (c_seq_addr_cmd_config, addr_cmd, ras_n, nop_toggle_value);
nop_toggle_value <= not nop_toggle_value;
if nop_toggle_value = '1' then
nop_toggle_signal <= we_n;
end if;
when we_n =>
addr_cmd <= mask (c_seq_addr_cmd_config, addr_cmd, we_n, nop_toggle_value);
nop_toggle_value <= not nop_toggle_value;
if nop_toggle_value = '1' then
nop_toggle_signal <= addr;
end if;
when others =>
report admin_report_prefix & " an attempt to toggle a non addr/cmd pin detected" severity failure;
end case;
elsif NON_OP_EVAL_MD = "SI_EVALUATOR" then -- toggle all addr/cmd pins at fmax
stage_counter <= 0; -- every mem_clk cycle
stage_counter_zero <= '1';
v_nop_ac_0 := mask (c_seq_addr_cmd_config, addr_cmd, addr, nop_toggle_value);
v_nop_ac_0 := mask (c_seq_addr_cmd_config, v_nop_ac_0, ba, nop_toggle_value);
v_nop_ac_0 := mask (c_seq_addr_cmd_config, v_nop_ac_0, we_n, nop_toggle_value);
v_nop_ac_0 := mask (c_seq_addr_cmd_config, v_nop_ac_0, ras_n, nop_toggle_value);
v_nop_ac_0 := mask (c_seq_addr_cmd_config, v_nop_ac_0, cas_n, nop_toggle_value);
v_nop_ac_1 := mask (c_seq_addr_cmd_config, addr_cmd, addr, not nop_toggle_value);
v_nop_ac_1 := mask (c_seq_addr_cmd_config, v_nop_ac_1, ba, not nop_toggle_value);
v_nop_ac_1 := mask (c_seq_addr_cmd_config, v_nop_ac_1, we_n, not nop_toggle_value);
v_nop_ac_1 := mask (c_seq_addr_cmd_config, v_nop_ac_1, ras_n, not nop_toggle_value);
v_nop_ac_1 := mask (c_seq_addr_cmd_config, v_nop_ac_1, cas_n, not nop_toggle_value);
for i in 0 to DWIDTH_RATIO/2 - 1 loop
if i mod 2 = 0 then
addr_cmd(i) <= v_nop_ac_0(i);
else
addr_cmd(i) <= v_nop_ac_1(i);
end if;
end loop;
if DWIDTH_RATIO = 2 then
nop_toggle_value <= not nop_toggle_value;
end if;
else
report admin_report_prefix & "unknown non-operational evaluation mode " & NON_OP_EVAL_MD severity failure;
end if;
when others =>
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
stage_counter <= 1;
ac_state <= s_0;
end case;
end if;
end if;
end process;
-- -------------------------------------------------------------------
-- output packing of mode register settings and enabling of ODT
-- -------------------------------------------------------------------
process (int_mr0, int_mr1, int_mr2, int_mr3, mem_init_complete)
begin
admin_regs_status_rec.mr0 <= int_mr0;
admin_regs_status_rec.mr1 <= int_mr1;
admin_regs_status_rec.mr2 <= int_mr2;
admin_regs_status_rec.mr3 <= int_mr3;
admin_regs_status_rec.init_done <= mem_init_complete;
enable_odt <= int_mr1(2) or int_mr1(6); -- if ODT enabled in MR settings (i.e. MR1 bits 2 or 6 /= 0)
end process;
-- --------------------------------------------------------------------------------
-- generation of handshake signals with ctrl, dgrb and dgwb blocks (this includes
-- command ack, command done for ctrl and access grant for dgrb/dgwb)
-- --------------------------------------------------------------------------------
process (rst_n, clk)
begin
if rst_n = '0' then
admin_ctrl <= defaults;
ac_access_gnt <= '0';
elsif rising_edge(clk) then
admin_ctrl <= defaults;
ac_access_gnt <= '0';
admin_ctrl.command_ack <= command_started;
admin_ctrl.command_done <= command_done;
if state = s_access then
ac_access_gnt <= '1';
end if;
end if;
end process;
end architecture struct;
--
-- -----------------------------------------------------------------------------
-- Abstract : inferred ram for the non-levelling AFI PHY sequencer
-- The inferred ram is used in the iram block to store
-- debug information about the sequencer. It is variable in
-- size based on the IRAM_AWIDTH generic and is of size
-- 32 * (2 ** IRAM_ADDR_WIDTH) bits
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.memphy_alt_mem_phy_record_pkg.all;
--
entity memphy_alt_mem_phy_iram_ram IS
generic (
IRAM_AWIDTH : natural
);
port (
clk : in std_logic;
rst_n : in std_logic;
-- ram ports
addr : in unsigned(IRAM_AWIDTH-1 downto 0);
wdata : in std_logic_vector(31 downto 0);
write : in std_logic;
rdata : out std_logic_vector(31 downto 0)
);
end entity;
--
architecture struct of memphy_alt_mem_phy_iram_ram is
-- infer ram
constant c_max_ram_address : natural := 2**IRAM_AWIDTH -1;
-- registered ram signals
signal addr_r : unsigned(IRAM_AWIDTH-1 downto 0);
signal wdata_r : std_logic_vector(31 downto 0);
signal write_r : std_logic;
signal rdata_r : std_logic_vector(31 downto 0);
-- ram storage array
type t_iram is array (0 to c_max_ram_address) of std_logic_vector(31 downto 0);
signal iram_ram : t_iram;
attribute altera_attribute : string;
attribute altera_attribute of iram_ram : signal is "-name ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS ""OFF""";
begin -- architecture struct
-- inferred ram instance - standard ram logic
process (clk, rst_n)
begin
if rst_n = '0' then
rdata_r <= (others => '0');
elsif rising_edge(clk) then
if write_r = '1' then
iram_ram(to_integer(addr_r)) <= wdata_r;
end if;
rdata_r <= iram_ram(to_integer(addr_r));
end if;
end process;
-- register i/o for speed
process (clk, rst_n)
begin
if rst_n = '0' then
rdata <= (others => '0');
write_r <= '0';
addr_r <= (others => '0');
wdata_r <= (others => '0');
elsif rising_edge(clk) then
rdata <= rdata_r;
write_r <= write;
addr_r <= addr;
wdata_r <= wdata;
end if;
end process;
end architecture struct;
--
-- -----------------------------------------------------------------------------
-- Abstract : iram block for the non-levelling AFI PHY sequencer
-- This block is an optional storage of debug information for
-- the sequencer. In the current form the iram stores header
-- information about the arrangement of the sequencer and pass/
-- fail information for per-delay/phase/pin sweeps for the
-- read resynch phase calibration stage. Support for debug of
-- additional commands can be added at a later date
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.memphy_alt_mem_phy_record_pkg.all;
-- The altmemphy iram ram (alt_mem_phy_iram_ram) is an inferred ram memory to implement the debug
-- iram ram block
--
use work.memphy_alt_mem_phy_iram_ram;
--
entity memphy_alt_mem_phy_iram is
generic (
-- physical interface width definitions
MEM_IF_MEMTYPE : string;
FAMILYGROUP_ID : natural;
MEM_IF_DQS_WIDTH : natural;
MEM_IF_DQ_PER_DQS : natural;
MEM_IF_DWIDTH : natural;
MEM_IF_DM_WIDTH : natural;
MEM_IF_NUM_RANKS : natural;
IRAM_AWIDTH : natural;
REFRESH_COUNT_INIT : natural;
PRESET_RLAT : natural;
PLL_STEPS_PER_CYCLE : natural;
CAPABILITIES : natural;
IP_BUILDNUM : natural
);
port (
-- clk / reset
clk : in std_logic;
rst_n : in std_logic;
-- read interface from mmi block:
mmi_iram : in t_iram_ctrl;
mmi_iram_enable_writes : in std_logic;
--iram status signal (includes read data from iram)
iram_status : out t_iram_stat;
iram_push_done : out std_logic;
-- from ctrl block
ctrl_iram : in t_ctrl_command;
-- from dgrb block
dgrb_iram : in t_iram_push;
-- from admin block
admin_regs_status_rec : in t_admin_stat;
-- current write position in the iram
ctrl_idib_top : in natural range 0 to 2 ** IRAM_AWIDTH - 1;
ctrl_iram_push : in t_ctrl_iram;
-- the following signals are unused and reserved for future use
dgwb_iram : in t_iram_push
);
end entity;
library work;
-- The registers package (alt_mem_phy_regs_pkg) is used to combine the definition of the
-- registers for the mmi status registers and functions/procedures applied to the registers
--
use work.memphy_alt_mem_phy_regs_pkg.all;
--
architecture struct of memphy_alt_mem_phy_iram is
-- -------------------------------------------
-- IHI fields
-- -------------------------------------------
-- memory type , Quartus Build No., Quartus release, sequencer architecture version :
signal memtype : std_logic_vector(7 downto 0);
signal ihi_self_description : std_logic_vector(31 downto 0);
signal ihi_self_description_extra : std_logic_vector(31 downto 0);
-- for iram address generation:
signal curr_iram_offset : natural range 0 to 2 ** IRAM_AWIDTH - 1;
-- set read latency for iram_rdata_valid signal control:
constant c_iram_rlat : natural := 3; -- iram read latency (increment if read pipelining added
-- for rdata valid generation:
signal read_valid_ctr : natural range 0 to c_iram_rlat;
signal iram_addr_r : unsigned(IRAM_AWIDTH downto 0);
constant c_ihi_phys_if_desc : std_logic_vector(31 downto 0) := std_logic_vector (to_unsigned(MEM_IF_NUM_RANKS,8) & to_unsigned(MEM_IF_DM_WIDTH,8) & to_unsigned(MEM_IF_DQS_WIDTH,8) & to_unsigned(MEM_IF_DWIDTH,8));
constant c_ihi_timing_info : std_logic_vector(31 downto 0) := X"DEADDEAD";
constant c_ihi_ctrl_ss_word2 : std_logic_vector(31 downto 0) := std_logic_vector (to_unsigned(PRESET_RLAT,16) & X"0000");
-- IDIB header codes
constant c_idib_header_code0 : std_logic_vector(7 downto 0) := X"4A";
constant c_idib_footer_code : std_logic_vector(7 downto 0) := X"5A";
-- encoded Quartus version
-- constant c_quartus_version : natural := 0; -- Quartus 7.2
-- constant c_quartus_version : natural := 1; -- Quartus 8.0
--constant c_quartus_version : natural := 2; -- Quartus 8.1
--constant c_quartus_version : natural := 3; -- Quartus 9.0
--constant c_quartus_version : natural := 4; -- Quartus 9.0sp2
--constant c_quartus_version : natural := 5; -- Quartus 9.1
--constant c_quartus_version : natural := 6; -- Quartus 9.1sp1?
--constant c_quartus_version : natural := 7; -- Quartus 9.1sp2?
constant c_quartus_version : natural := 8; -- Quartus 10.0
-- constant c_quartus_version : natural := 114; -- reserved
-- allow for different variants for debug i/f
constant c_dbg_if_version : natural := 2;
-- sequencer type 1 for levelling, 2 for non-levelling
constant c_sequencer_type : natural := 2;
-- a prefix for all report signals to identify phy and sequencer block
--
constant iram_report_prefix : string := "memphy_alt_mem_phy_seq (iram) : ";
-- -------------------------------------------
-- signal and type declarations
-- -------------------------------------------
type t_iram_state is ( s_reset, -- system reset
s_pre_init_ram, -- identify pre-initialisation
s_init_ram, -- zero all locations
s_idle, -- default state
s_word_access_ram, -- mmi access to the iram (post-calibration)
s_word_fetch_ram_rdata, -- sample read data from RAM
s_word_fetch_ram_rdata_r,-- register the sampling of data from RAM (to improve timing)
s_word_complete, -- finalise iram ram write
s_idib_header_write, -- when starting a command
s_idib_header_inc_addr, -- address increment
s_idib_footer_write, -- unique footer to indicate end of data
s_cal_data_read, -- read RAM location (read occurs continuously from idle state)
s_cal_data_read_r,
s_cal_data_modify, -- modify RAM location (read occurs continuously)
s_cal_data_write, -- write modified value back to RAM
s_ihi_header_word0_wr, -- from 0 to 6 writing iram header info
s_ihi_header_word1_wr,
s_ihi_header_word2_wr,
s_ihi_header_word3_wr,
s_ihi_header_word4_wr,
s_ihi_header_word5_wr,
s_ihi_header_word6_wr,
s_ihi_header_word7_wr-- end writing iram header info
);
signal state : t_iram_state;
signal contested_access : std_logic;
signal idib_header_count : std_logic_vector(7 downto 0);
-- register a new cmd request
signal new_cmd : std_logic;
signal cmd_processed : std_logic;
-- signals to control dgrb writes
signal iram_modified_data : std_logic_vector(31 downto 0); -- scratchpad memory for read-modify-write
-- -------------------------------------------
-- physical ram connections
-- -------------------------------------------
-- Note that the iram_addr here is created IRAM_AWIDTH downto 0, and not
-- IRAM_AWIDTH-1 downto 0. This means that the MSB is outside the addressable
-- area of the RAM. The purpose of this is that this shall be our memory
-- overflow bit. It shall be directly connected to the iram_out_of_memory flag
-- 32-bit interface port (read and write)
signal iram_addr : unsigned(IRAM_AWIDTH downto 0);
signal iram_wdata : std_logic_vector(31 downto 0);
signal iram_rdata : std_logic_vector(31 downto 0);
signal iram_write : std_logic;
-- signal generated external to the iram to say when read data is valid
signal iram_rdata_valid : std_logic;
-- The FSM owns local storage that is loaded with the wdata/addr from the
-- requesting sub-block, which is then fed to the iram's wdata/addr in turn
-- until all data has gone across
signal fsm_read : std_logic;
-- -------------------------------------------
-- multiplexed push data
-- -------------------------------------------
signal iram_done : std_logic; -- unused
signal iram_pushdata : std_logic_vector(31 downto 0);
signal pending_push : std_logic; -- push data to RAM
signal iram_wordnum : natural range 0 to 511;
signal iram_bitnum : natural range 0 to 31;
begin -- architecture struct
-- -------------------------------------------
-- iram ram instantiation
-- -------------------------------------------
-- Note that the IRAM_AWIDTH is the physical number of address bits that the RAM has.
-- However, for out of range access detection purposes, an additional bit is added to
-- the various address signals. The iRAM does not register any of its inputs as the addr,
-- wdata etc are registered directly before being driven to it.
-- The dgrb accesses are of format read-modify-write to a single bit of a 32-bit word, the
-- mmi reads and header writes are in 32-bit words
--
ram : entity memphy_alt_mem_phy_iram_ram
generic map (
IRAM_AWIDTH => IRAM_AWIDTH
)
port map (
clk => clk,
rst_n => rst_n,
addr => iram_addr(IRAM_AWIDTH-1 downto 0),
wdata => iram_wdata,
write => iram_write,
rdata => iram_rdata
);
-- -------------------------------------------
-- IHI fields
-- asynchronously
-- -------------------------------------------
-- this field identifies the type of memory
memtype <= X"03" when (MEM_IF_MEMTYPE = "DDR3") else
X"02" when (MEM_IF_MEMTYPE = "DDR2") else
X"01" when (MEM_IF_MEMTYPE = "DDR") else
X"10" when (MEM_IF_MEMTYPE = "QDRII") else
X"00" ;
-- this field indentifies the gross level description of the sequencer
ihi_self_description <= memtype
& std_logic_vector(to_unsigned(IP_BUILDNUM,8))
& std_logic_vector(to_unsigned(c_quartus_version,8))
& std_logic_vector(to_unsigned(c_dbg_if_version,8));
-- some extra information for the debug gui - sequencer type and familygroup
ihi_self_description_extra <= std_logic_vector(to_unsigned(FAMILYGROUP_ID,4))
& std_logic_vector(to_unsigned(c_sequencer_type,4))
& x"000000";
-- -------------------------------------------
-- check for contested memory accesses
-- -------------------------------------------
process(clk,rst_n)
begin
if rst_n = '0' then
contested_access <= '0';
elsif rising_edge(clk) then
contested_access <= '0';
if mmi_iram.read = '1' and pending_push = '1' then
report iram_report_prefix & "contested memory accesses to the iram" severity failure;
contested_access <= '1';
end if;
-- sanity checks
if mmi_iram.write = '1' then
report iram_report_prefix & "mmi writes to the iram unsupported for non-levelling AFI PHY sequencer" severity failure;
end if;
if dgwb_iram.iram_write = '1' then
report iram_report_prefix & "dgwb writes to the iram unsupported for non-levelling AFI PHY sequencer" severity failure;
end if;
end if;
end process;
-- -------------------------------------------
-- mux push data and associated signals
-- note: single bit taken for iram_pushdata because 1-bit read-modify-write to
-- a 32-bit word in the ram. This interface style is maintained for future
-- scalability / wider application of the iram block.
-- -------------------------------------------
process(clk,rst_n)
begin
if rst_n = '0' then
iram_done <= '0';
iram_pushdata <= (others => '0');
pending_push <= '0';
iram_wordnum <= 0;
iram_bitnum <= 0;
elsif rising_edge(clk) then
case curr_active_block(ctrl_iram.command) is
when dgrb =>
iram_done <= dgrb_iram.iram_done;
iram_pushdata <= dgrb_iram.iram_pushdata;
pending_push <= dgrb_iram.iram_write;
iram_wordnum <= dgrb_iram.iram_wordnum;
iram_bitnum <= dgrb_iram.iram_bitnum;
when others => -- default dgrb
iram_done <= dgrb_iram.iram_done;
iram_pushdata <= dgrb_iram.iram_pushdata;
pending_push <= dgrb_iram.iram_write;
iram_wordnum <= dgrb_iram.iram_wordnum;
iram_bitnum <= dgrb_iram.iram_bitnum;
end case;
end if;
end process;
-- -------------------------------------------
-- generate write signal for the ram
-- -------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
iram_write <= '0';
elsif rising_edge(clk) then
case state is
when s_idle =>
iram_write <= '0';
when s_pre_init_ram |
s_init_ram =>
iram_write <= '1';
when s_ihi_header_word0_wr |
s_ihi_header_word1_wr |
s_ihi_header_word2_wr |
s_ihi_header_word3_wr |
s_ihi_header_word4_wr |
s_ihi_header_word5_wr |
s_ihi_header_word6_wr |
s_ihi_header_word7_wr =>
iram_write <= '1';
when s_idib_header_write =>
iram_write <= '1';
when s_idib_footer_write =>
iram_write <= '1';
when s_cal_data_write =>
iram_write <= '1';
when others =>
iram_write <= '0'; -- default
end case;
end if;
end process;
-- -------------------------------------------
-- generate wdata for the ram
-- -------------------------------------------
process(clk, rst_n)
variable v_current_cs : std_logic_vector(3 downto 0);
variable v_mtp_alignment : std_logic_vector(0 downto 0);
variable v_single_bit : std_logic;
begin
if rst_n = '0' then
iram_wdata <= (others => '0');
elsif rising_edge(clk) then
case state is
when s_pre_init_ram |
s_init_ram =>
iram_wdata <= (others => '0');
when s_ihi_header_word0_wr =>
iram_wdata <= ihi_self_description;
when s_ihi_header_word1_wr =>
iram_wdata <= c_ihi_phys_if_desc;
when s_ihi_header_word2_wr =>
iram_wdata <= c_ihi_timing_info;
when s_ihi_header_word3_wr =>
iram_wdata <= ( others => '0');
iram_wdata(admin_regs_status_rec.mr0'range) <= admin_regs_status_rec.mr0;
iram_wdata(admin_regs_status_rec.mr1'high + 16 downto 16) <= admin_regs_status_rec.mr1;
when s_ihi_header_word4_wr =>
iram_wdata <= ( others => '0');
iram_wdata(admin_regs_status_rec.mr2'range) <= admin_regs_status_rec.mr2;
iram_wdata(admin_regs_status_rec.mr3'high + 16 downto 16) <= admin_regs_status_rec.mr3;
when s_ihi_header_word5_wr =>
iram_wdata <= c_ihi_ctrl_ss_word2;
when s_ihi_header_word6_wr =>
iram_wdata <= std_logic_vector(to_unsigned(IRAM_AWIDTH,32)); -- tbd write the occupancy at end of cal
when s_ihi_header_word7_wr =>
iram_wdata <= ihi_self_description_extra;
when s_idib_header_write =>
-- encode command_op for current operation
v_current_cs := std_logic_vector(to_unsigned(ctrl_iram.command_op.current_cs, 4));
v_mtp_alignment := std_logic_vector(to_unsigned(ctrl_iram.command_op.mtp_almt, 1));
v_single_bit := ctrl_iram.command_op.single_bit;
iram_wdata <= encode_current_stage(ctrl_iram.command) & -- which command being executed (currently this should only be cmd_rrp_sweep (8 bits)
v_current_cs & -- which chip select being processed (4 bits)
v_mtp_alignment & -- currently used MTP alignment (1 bit)
v_single_bit & -- is single bit calibration selected (1 bit) - used during MTP alignment
"00" & -- RFU
idib_header_count & -- unique ID to how many headers have been written (8 bits)
c_idib_header_code0; -- unique ID for headers (8 bits)
when s_idib_footer_write =>
iram_wdata <= c_idib_footer_code & c_idib_footer_code & c_idib_footer_code & c_idib_footer_code;
when s_cal_data_modify =>
-- default don't overwrite
iram_modified_data <= iram_rdata;
-- update iram data based on packing and write modes
if ctrl_iram_push.packing_mode = dq_bitwise then
case ctrl_iram_push.write_mode is
when overwrite_ram =>
iram_modified_data(iram_bitnum) <= iram_pushdata(0);
when or_into_ram =>
iram_modified_data(iram_bitnum) <= iram_pushdata(0) or iram_rdata(0);
when and_into_ram =>
iram_modified_data(iram_bitnum) <= iram_pushdata(0) and iram_rdata(0);
when others =>
report iram_report_prefix & "unidentified write mode of " & t_iram_write_mode'image(ctrl_iram_push.write_mode) &
" specified when generating iram write data" severity failure;
end case;
elsif ctrl_iram_push.packing_mode = dq_wordwise then
case ctrl_iram_push.write_mode is
when overwrite_ram =>
iram_modified_data <= iram_pushdata;
when or_into_ram =>
iram_modified_data <= iram_pushdata or iram_rdata;
when and_into_ram =>
iram_modified_data <= iram_pushdata and iram_rdata;
when others =>
report iram_report_prefix & "unidentified write mode of " & t_iram_write_mode'image(ctrl_iram_push.write_mode) &
" specified when generating iram write data" severity failure;
end case;
else
report iram_report_prefix & "unidentified packing mode of " & t_iram_packing_mode'image(ctrl_iram_push.packing_mode) &
" specified when generating iram write data" severity failure;
end if;
when s_cal_data_write =>
iram_wdata <= iram_modified_data;
when others =>
iram_wdata <= (others => '0');
end case;
end if;
end process;
-- -------------------------------------------
-- generate addr for the ram
-- -------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
iram_addr <= (others => '0');
curr_iram_offset <= 0;
elsif rising_edge(clk) then
case (state) is
when s_idle =>
if mmi_iram.read = '1' then -- pre-set mmi read location address
iram_addr <= ('0' & to_unsigned(mmi_iram.addr,IRAM_AWIDTH)); -- Pad MSB
else -- default get next push data location from iram
iram_addr <= to_unsigned(curr_iram_offset + iram_wordnum, IRAM_AWIDTH+1);
end if;
when s_word_access_ram =>
-- calculate the address
if mmi_iram.read = '1' then -- mmi access
iram_addr <= ('0' & to_unsigned(mmi_iram.addr,IRAM_AWIDTH)); -- Pad MSB
end if;
when s_ihi_header_word0_wr =>
iram_addr <= (others => '0');
-- increment address for IHI word writes :
when s_ihi_header_word1_wr |
s_ihi_header_word2_wr |
s_ihi_header_word3_wr |
s_ihi_header_word4_wr |
s_ihi_header_word5_wr |
s_ihi_header_word6_wr |
s_ihi_header_word7_wr =>
iram_addr <= iram_addr + 1;
when s_idib_header_write =>
iram_addr <= '0' & to_unsigned(ctrl_idib_top, IRAM_AWIDTH); -- Always write header at idib_top location
when s_idib_footer_write =>
iram_addr <= to_unsigned(curr_iram_offset + iram_wordnum, IRAM_AWIDTH+1); -- active block communicates where to put the footer with done signal
when s_idib_header_inc_addr =>
iram_addr <= iram_addr + 1;
curr_iram_offset <= to_integer('0' & iram_addr) + 1;
when s_init_ram =>
if iram_addr(IRAM_AWIDTH) = '1' then
iram_addr <= (others => '0'); -- this prevents erroneous out-of-mem flag after initialisation
else
iram_addr <= iram_addr + 1;
end if;
when others =>
iram_addr <= iram_addr;
end case;
end if;
end process;
-- -------------------------------------------
-- generate new cmd signal to register the command_req signal
-- -------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
new_cmd <= '0';
elsif rising_edge(clk) then
if ctrl_iram.command_req = '1' then
case ctrl_iram.command is
when cmd_rrp_sweep | -- only prompt new_cmd for commands we wish to write headers for
cmd_rrp_seek |
cmd_read_mtp |
cmd_write_ihi =>
new_cmd <= '1';
when others =>
new_cmd <= '0';
end case;
end if;
if cmd_processed = '1' then
new_cmd <= '0';
end if;
end if;
end process;
-- -------------------------------------------
-- generate read valid signal which takes account of pipelining of reads
-- -------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
iram_rdata_valid <= '0';
read_valid_ctr <= 0;
iram_addr_r <= (others => '0');
elsif rising_edge(clk) then
if read_valid_ctr < c_iram_rlat then
iram_rdata_valid <= '0';
read_valid_ctr <= read_valid_ctr + 1;
else
iram_rdata_valid <= '1';
end if;
if to_integer(iram_addr) /= to_integer(iram_addr_r) or
iram_write = '1' then
read_valid_ctr <= 0;
iram_rdata_valid <= '0';
end if;
-- register iram address
iram_addr_r <= iram_addr;
end if;
end process;
-- -------------------------------------------
-- state machine
-- -------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
state <= s_reset;
cmd_processed <= '0';
elsif rising_edge(clk) then
cmd_processed <= '0';
case state is
when s_reset =>
state <= s_pre_init_ram;
when s_pre_init_ram =>
state <= s_init_ram;
-- remain in the init_ram state until all the ram locations have been zero'ed
when s_init_ram =>
if iram_addr(IRAM_AWIDTH) = '1' then
state <= s_idle;
end if;
-- default state after reset
when s_idle =>
if pending_push = '1' then
state <= s_cal_data_read;
elsif iram_done = '1' then
state <= s_idib_footer_write;
elsif new_cmd = '1' then
case ctrl_iram.command is
when cmd_rrp_sweep |
cmd_rrp_seek |
cmd_read_mtp => state <= s_idib_header_write;
when cmd_write_ihi => state <= s_ihi_header_word0_wr;
when others => state <= state;
end case;
cmd_processed <= '1';
elsif mmi_iram.read = '1' then
state <= s_word_access_ram;
end if;
-- mmi read accesses
when s_word_access_ram => state <= s_word_fetch_ram_rdata;
when s_word_fetch_ram_rdata => state <= s_word_fetch_ram_rdata_r;
when s_word_fetch_ram_rdata_r => if iram_rdata_valid = '1' then
state <= s_word_complete;
end if;
when s_word_complete => if iram_rdata_valid = '1' then -- return to idle when iram_rdata stable
state <= s_idle;
end if;
-- header write (currently only for cmp_rrp stage)
when s_idib_header_write => state <= s_idib_header_inc_addr;
when s_idib_header_inc_addr => state <= s_idle; -- return to idle to wait for push
when s_idib_footer_write => state <= s_word_complete;
-- push data accesses (only used by the dgrb block at present)
when s_cal_data_read => state <= s_cal_data_read_r;
when s_cal_data_read_r => if iram_rdata_valid = '1' then
state <= s_cal_data_modify;
end if;
when s_cal_data_modify => state <= s_cal_data_write;
when s_cal_data_write => state <= s_word_complete;
-- IHI Header write accesses
when s_ihi_header_word0_wr => state <= s_ihi_header_word1_wr;
when s_ihi_header_word1_wr => state <= s_ihi_header_word2_wr;
when s_ihi_header_word2_wr => state <= s_ihi_header_word3_wr;
when s_ihi_header_word3_wr => state <= s_ihi_header_word4_wr;
when s_ihi_header_word4_wr => state <= s_ihi_header_word5_wr;
when s_ihi_header_word5_wr => state <= s_ihi_header_word6_wr;
when s_ihi_header_word6_wr => state <= s_ihi_header_word7_wr;
when s_ihi_header_word7_wr => state <= s_idle;
when others => state <= state;
end case;
end if;
end process;
-- -------------------------------------------
-- drive read data and responses back.
-- -------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
iram_status <= defaults;
iram_push_done <= '0';
idib_header_count <= (others => '0');
fsm_read <= '0';
elsif rising_edge(clk) then
-- defaults
iram_status <= defaults;
iram_status.done <= '0';
iram_status.rdata <= (others => '0');
iram_push_done <= '0';
if state = s_init_ram then
iram_status.out_of_mem <= '0';
else
iram_status.out_of_mem <= iram_addr(IRAM_AWIDTH);
end if;
-- register read flag for 32 bit accesses
if state = s_idle then
fsm_read <= mmi_iram.read;
end if;
if state = s_word_complete then
iram_status.done <= '1';
if fsm_read = '1' then
iram_status.rdata <= iram_rdata;
else
iram_status.rdata <= (others => '0');
end if;
end if;
-- if another access is ever presented while the FSM is busy, set the contested flag
if contested_access = '1' then
iram_status.contested_access <= '1';
end if;
-- set (and keep set) the iram_init_done output once initialisation of the RAM is complete
if (state /= s_init_ram) and (state /= s_pre_init_ram) and (state /= s_reset) then
iram_status.init_done <= '1';
end if;
if state = s_ihi_header_word7_wr then
iram_push_done <= '1';
end if;
-- if completing push or footer write then acknowledge
if state = s_cal_data_modify or state = s_idib_footer_write then
iram_push_done <= '1';
end if;
-- increment IDIB header count each time a header is written
if state = s_idib_header_write then
idib_header_count <= std_logic_vector(unsigned(idib_header_count) + to_unsigned(1,idib_header_count'high +1));
end if;
end if;
end process;
end architecture struct;
--
-- -----------------------------------------------------------------------------
-- Abstract : data gatherer (read bias) [dgrb] block for the non-levelling
-- AFI PHY sequencer
-- This block handles all calibration commands which require
-- memory read operations.
--
-- These include:
-- Resync phase calibration - sweep of phases, calculation of
-- result and optional storage to iram
-- Postamble calibration - clock cycle calibration of the postamble
-- enable signal
-- Read data valid signal alignment
-- Calculation of advertised read and write latencies
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.memphy_alt_mem_phy_record_pkg.all;
-- The address and command package (alt_mem_phy_addr_cmd_pkg) is used to combine DRAM address
-- and command signals in one record and unify the functions operating on this record.
--
use work.memphy_alt_mem_phy_addr_cmd_pkg.all;
-- The iram address package (alt_mem_phy_iram_addr_pkg) is used to define the base addresses used
-- for iram writes during calibration
--
use work.memphy_alt_mem_phy_iram_addr_pkg.all;
-- The constant package (alt_mem_phy_constants_pkg) contains global 'constants' which are fixed
-- thoughout the sequencer and will not change (for constants which may change between sequencer
-- instances generics are used)
--
use work.memphy_alt_mem_phy_constants_pkg.all;
--
entity memphy_alt_mem_phy_dgrb is
generic (
MEM_IF_DQS_WIDTH : natural;
MEM_IF_DQ_PER_DQS : natural;
MEM_IF_DWIDTH : natural;
MEM_IF_DM_WIDTH : natural;
MEM_IF_DQS_CAPTURE : natural;
MEM_IF_ADDR_WIDTH : natural;
MEM_IF_BANKADDR_WIDTH : natural;
MEM_IF_NUM_RANKS : natural;
MEM_IF_MEMTYPE : string;
ADV_LAT_WIDTH : natural;
CLOCK_INDEX_WIDTH : natural;
DWIDTH_RATIO : natural;
PRESET_RLAT : natural;
PLL_STEPS_PER_CYCLE : natural; -- number of PLL phase steps per PHY clock cycle
SIM_TIME_REDUCTIONS : natural;
GENERATE_ADDITIONAL_DBG_RTL : natural;
PRESET_CODVW_PHASE : natural;
PRESET_CODVW_SIZE : natural;
-- base column address to which calibration data is written
-- memory at MEM_IF_CAL_BASE_COL - MEM_IF_CAL_BASE_COL + C_CAL_DATA_LEN - 1
-- is assumed to contain the proper data
MEM_IF_CAL_BANK : natural; -- bank to which calibration data is written
MEM_IF_CAL_BASE_COL : natural;
EN_OCT : natural
);
port (
-- clk / reset
clk : in std_logic;
rst_n : in std_logic;
-- control interface
dgrb_ctrl : out t_ctrl_stat;
ctrl_dgrb : in t_ctrl_command;
parameterisation_rec : in t_algm_paramaterisation;
-- PLL reconfig interface
phs_shft_busy : in std_logic;
seq_pll_inc_dec_n : out std_logic;
seq_pll_select : out std_logic_vector(CLOCK_INDEX_WIDTH - 1 DOWNTO 0);
seq_pll_start_reconfig : out std_logic;
pll_resync_clk_index : in std_logic_vector(CLOCK_INDEX_WIDTH - 1 downto 0); -- PLL phase used to select resync clock
pll_measure_clk_index : in std_logic_vector(CLOCK_INDEX_WIDTH - 1 downto 0); -- PLL phase used to select mimic / aka measure clock
-- iram 'push' interface
dgrb_iram : out t_iram_push;
iram_push_done : in std_logic;
-- addr/cmd output for write commands
dgrb_ac : out t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
-- admin block req/gnt interface
dgrb_ac_access_req : out std_logic;
dgrb_ac_access_gnt : in std_logic;
-- RDV latency controls
seq_rdata_valid_lat_inc : out std_logic;
seq_rdata_valid_lat_dec : out std_logic;
-- POA latency controls
seq_poa_lat_dec_1x : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_poa_lat_inc_1x : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
-- read datapath interface
rdata_valid : in std_logic_vector(DWIDTH_RATIO/2 - 1 downto 0);
rdata : in std_logic_vector(DWIDTH_RATIO * MEM_IF_DWIDTH - 1 downto 0);
doing_rd : out std_logic_vector(MEM_IF_DQS_WIDTH * DWIDTH_RATIO/2 - 1 downto 0);
rd_lat : out std_logic_vector(ADV_LAT_WIDTH - 1 downto 0);
-- advertised write latency
wd_lat : out std_logic_vector(ADV_LAT_WIDTH - 1 downto 0);
-- OCT control
seq_oct_value : out std_logic;
dgrb_wdp_ovride : out std_logic;
-- mimic path interface
seq_mmc_start : out std_logic;
mmc_seq_done : in std_logic;
mmc_seq_value : in std_logic;
-- calibration byte lane select (reserved for future use - RFU)
ctl_cal_byte_lanes : in std_logic_vector(MEM_IF_NUM_RANKS * MEM_IF_DQS_WIDTH - 1 downto 0);
-- odt settings per chip select
odt_settings : in t_odt_array(0 to MEM_IF_NUM_RANKS-1);
-- signal to identify if a/c nt setting is correct (set after wr_lat calculation)
-- NOTE: labelled nt for future scalability to quarter rate interfaces
dgrb_ctrl_ac_nt_good : out std_logic;
-- status signals on calibrated cdvw
dgrb_mmi : out t_dgrb_mmi
);
end entity;
--
architecture struct of memphy_alt_mem_phy_dgrb is
-- ------------------------------------------------------------------
-- constant declarations
-- ------------------------------------------------------------------
constant c_seq_addr_cmd_config : t_addr_cmd_config_rec := set_config_rec(MEM_IF_ADDR_WIDTH, MEM_IF_BANKADDR_WIDTH, MEM_IF_NUM_RANKS, DWIDTH_RATIO, MEM_IF_MEMTYPE);
-- command/result length
constant c_command_result_len : natural := 8;
-- burst characteristics and latency characteristics
constant c_max_read_lat : natural := 2**rd_lat'length - 1; -- maximum read latency in phy clock-cycles
-- training pattern characteristics
constant c_cal_mtp_len : natural := 16;
constant c_cal_mtp : std_logic_vector(c_cal_mtp_len - 1 downto 0) := x"30F5";
constant c_cal_mtp_t : natural := c_cal_mtp_len / DWIDTH_RATIO; -- number of phy-clk cycles required to read BTP
-- read/write latency defaults
constant c_default_rd_lat_slv : std_logic_vector(ADV_LAT_WIDTH - 1 downto 0) := std_logic_vector(to_unsigned(c_default_rd_lat, ADV_LAT_WIDTH));
constant c_default_wd_lat_slv : std_logic_vector(ADV_LAT_WIDTH - 1 downto 0) := std_logic_vector(to_unsigned(c_default_wr_lat, ADV_LAT_WIDTH));
-- tracking reporting parameters
constant c_max_rsc_drift_in_phases : natural := 127; -- this must be a value of < 2^10 - 1 because of the range of signal codvw_trk_shift
-- Returns '1' when boolean b is True; '0' otherwise.
function active_high(b : in boolean) return std_logic is
variable r : std_logic;
begin
if b then
r := '1';
else
r := '0';
end if;
return r;
end function;
-- a prefix for all report signals to identify phy and sequencer block
--
constant dgrb_report_prefix : string := "memphy_alt_mem_phy_seq (dgrb) : ";
-- Return the number of clock periods the resync clock should sweep.
--
-- On half-rate systems and in DQS-capture based systems a 720
-- to guarantee the resync window can be properly observed.
function rsc_sweep_clk_periods return natural is
variable v_num_periods : natural;
begin
if DWIDTH_RATIO = 2 then
if MEM_IF_DQS_CAPTURE = 1 then -- families which use DQS capture require a 720 degree sweep for FR to show a window
v_num_periods := 2;
else
v_num_periods := 1;
end if;
elsif DWIDTH_RATIO = 4 then
v_num_periods := 2;
else
report dgrb_report_prefix & "unsupported DWIDTH_RATIO." severity failure;
end if;
return v_num_periods;
end function;
-- window for PLL sweep
constant c_max_phase_shifts : natural := rsc_sweep_clk_periods*PLL_STEPS_PER_CYCLE;
constant c_pll_phs_inc : std_logic := '1';
constant c_pll_phs_dec : std_logic := not c_pll_phs_inc;
-- ------------------------------------------------------------------
-- type declarations
-- ------------------------------------------------------------------
-- dgrb main state machine
type t_dgrb_state is (
-- idle state
s_idle,
-- request access to memory address/command bus from the admin block
s_wait_admin,
-- relinquish address/command bus access
s_release_admin,
-- wind back resync phase to a 'zero' point
s_reset_cdvw,
-- perform resync phase sweep (used for MTP alignment checking and actual RRP sweep)
s_test_phases,
-- processing to when checking MTP alignment
s_read_mtp,
-- processing for RRP (read resync phase) sweep
s_seek_cdvw,
-- clock cycle alignment of read data valid signal
s_rdata_valid_align,
-- calculate advertised read latency
s_adv_rd_lat_setup,
s_adv_rd_lat,
-- calculate advertised write latency
s_adv_wd_lat,
-- postamble clock cycle calibration
s_poa_cal,
-- tracking - setup and periodic update
s_track
);
-- dgrb slave state machine for addr/cmd signals
type t_ac_state is (
-- idle state
s_ac_idle,
-- wait X cycles (issuing NOP command) to flush address/command and DQ buses
s_ac_relax,
-- read MTP pattern
s_ac_read_mtp,
-- read pattern for read data valid alignment
s_ac_read_rdv,
-- read pattern for POA calibration
s_ac_read_poa_mtp,
-- read pattern to calculate advertised write latency
s_ac_read_wd_lat
);
-- dgrb slave state machine for read resync phase calibration
type t_resync_state is (
-- idle state
s_rsc_idle,
-- shift resync phase by one
s_rsc_next_phase,
-- start test sequence for current pin and current phase
s_rsc_test_phase,
-- flush the read datapath
s_rsc_wait_for_idle_dimm, -- wait until no longer driving
s_rsc_flush_datapath, -- flush a/c path
-- sample DQ data to test phase
s_rsc_test_dq,
-- reset rsc phase to a zero position
s_rsc_reset_cdvw,
s_rsc_rewind_phase,
-- calculate the centre of resync window
s_rsc_cdvw_calc,
s_rsc_cdvw_wait, -- wait for calc result
-- set rsc clock phase to centre of data valid window
s_rsc_seek_cdvw,
-- wait until all results written to iram
s_rsc_wait_iram -- only entered if GENERATE_ADDITIONAL_DBG_RTL = 1
);
-- record definitions for window processing
type t_win_processing_status is ( calculating,
valid_result,
no_invalid_phases,
multiple_equal_windows,
no_valid_phases
);
type t_window_processing is record
working_window : std_logic_vector( c_max_phase_shifts - 1 downto 0);
first_good_edge : natural range 0 to c_max_phase_shifts - 1; -- pointer to first detected good edge
current_window_start : natural range 0 to c_max_phase_shifts - 1;
current_window_size : natural range 0 to c_max_phase_shifts - 1;
current_window_centre : natural range 0 to c_max_phase_shifts - 1;
largest_window_start : natural range 0 to c_max_phase_shifts - 1;
largest_window_size : natural range 0 to c_max_phase_shifts - 1;
largest_window_centre : natural range 0 to c_max_phase_shifts - 1;
current_bit : natural range 0 to c_max_phase_shifts - 1;
window_centre_update : std_logic;
last_bit_value : std_logic;
valid_phase_seen : boolean;
invalid_phase_seen : boolean;
first_cycle : boolean;
multiple_eq_windows : boolean;
found_a_good_edge : boolean;
status : t_win_processing_status;
windows_seen : natural range 0 to c_max_phase_shifts/2 - 1;
end record;
-- ------------------------------------------------------------------
-- function and procedure definitions
-- ------------------------------------------------------------------
-- Returns a string representation of a std_logic_vector.
-- Not synthesizable.
function str(v: std_logic_vector) return string is
variable str_value : string (1 to v'length);
variable str_len : integer;
variable c : character;
begin
str_len := 1;
for i in v'range loop
case v(i) is
when '0' => c := '0';
when '1' => c := '1';
when others => c := '?';
end case;
str_value(str_len) := c;
str_len := str_len + 1;
end loop;
return str_value;
end str;
-- functions and procedures for window processing
function defaults return t_window_processing is
variable output : t_window_processing;
begin
output.working_window := (others => '1');
output.last_bit_value := '1';
output.first_good_edge := 0;
output.current_window_start := 0;
output.current_window_size := 0;
output.current_window_centre := 0;
output.largest_window_start := 0;
output.largest_window_size := 0;
output.largest_window_centre := 0;
output.window_centre_update := '1';
output.current_bit := 0;
output.multiple_eq_windows := false;
output.valid_phase_seen := false;
output.invalid_phase_seen := false;
output.found_a_good_edge := false;
output.status := no_valid_phases;
output.first_cycle := false;
output.windows_seen := 0;
return output;
end function defaults;
procedure initialise_window_for_proc ( working : inout t_window_processing ) is
variable v_working_window : std_logic_vector( c_max_phase_shifts - 1 downto 0);
begin
v_working_window := working.working_window;
working := defaults;
working.working_window := v_working_window;
working.status := calculating;
working.first_cycle := true;
working.window_centre_update := '1';
working.windows_seen := 0;
end procedure initialise_window_for_proc;
procedure shift_window (working : inout t_window_processing;
num_phases : in natural range 1 to c_max_phase_shifts
)
is
begin
if working.working_window(0) = '0' then
working.invalid_phase_seen := true;
else
working.valid_phase_seen := true;
end if;
-- general bit serial shifting of window and incrementing of current bit counter.
if working.current_bit < num_phases - 1 then
working.current_bit := working.current_bit + 1;
else
working.current_bit := 0;
end if;
working.last_bit_value := working.working_window(0);
working.working_window := working.working_window(0) & working.working_window(working.working_window'high downto 1);
--synopsis translate_off
-- for simulation to make it simpler to see IF we are not using all the bits in the window
working.working_window(working.working_window'high) := 'H'; -- for visual debug
--synopsis translate_on
working.working_window(num_phases -1) := working.last_bit_value;
working.first_cycle := false;
end procedure shift_window;
procedure find_centre_of_largest_data_valid_window
( working : inout t_window_processing;
num_phases : in natural range 1 to c_max_phase_shifts
) is
begin
if working.first_cycle = false then -- not first call to procedure, then handle end conditions
if working.current_bit = 0 and working.found_a_good_edge = false then -- have been all way arround window (circular)
if working.valid_phase_seen = false then
working.status := no_valid_phases;
elsif working.invalid_phase_seen = false then
working.status := no_invalid_phases;
end if;
elsif working.current_bit = working.first_good_edge then -- if have found a good edge then complete a circular sweep to that edge
if working.multiple_eq_windows = true then
working.status := multiple_equal_windows;
else
working.status := valid_result;
end if;
end if;
end if;
-- start of a window condition
if working.last_bit_value = '0' and working.working_window(0) = '1' then
working.current_window_start := working.current_bit;
working.current_window_size := working.current_window_size + 1; -- equivalent to assigning to one because if not in a window then it is set to 0
working.window_centre_update := not working.window_centre_update;
working.current_window_centre := working.current_bit;
if working.found_a_good_edge /= true then -- if have not yet found a good edge then store this value
working.first_good_edge := working.current_bit;
working.found_a_good_edge := true;
end if;
-- end of window conditions
elsif working.last_bit_value = '1' and working.working_window(0) = '0' then
if working.current_window_size > working.largest_window_size then
working.largest_window_size := working.current_window_size;
working.largest_window_start := working.current_window_start;
working.largest_window_centre := working.current_window_centre;
working.multiple_eq_windows := false;
elsif working.current_window_size = working.largest_window_size then
working.multiple_eq_windows := true;
end if;
-- put counter in here because start of window 1 is observed twice
if working.found_a_good_edge = true then
working.windows_seen := working.windows_seen + 1;
end if;
working.current_window_size := 0;
elsif working.last_bit_value = '1' and working.working_window(0) = '1' and (working.found_a_good_edge = true) then --note operand in brackets is excessive but for may provide power savings and makes visual inspection of simulatuion easier
if working.window_centre_update = '1' then
if working.current_window_centre < num_phases -1 then
working.current_window_centre := working.current_window_centre + 1;
else
working.current_window_centre := 0;
end if;
end if;
working.window_centre_update := not working.window_centre_update;
working.current_window_size := working.current_window_size + 1;
end if;
shift_window(working,num_phases);
end procedure find_centre_of_largest_data_valid_window;
procedure find_last_failing_phase
( working : inout t_window_processing;
num_phases : in natural range 1 to c_max_phase_shifts + 1
) is
begin
if working.first_cycle = false then -- not first call to procedure
if working.current_bit = 0 then -- and working.found_a_good_edge = false then
if working.valid_phase_seen = false then
working.status := no_valid_phases;
elsif working.invalid_phase_seen = false then
working.status := no_invalid_phases;
else
working.status := valid_result;
end if;
end if;
end if;
if working.working_window(1) = '1' and working.working_window(0) = '0' and working.status = calculating then
working.current_window_start := working.current_bit;
end if;
shift_window(working, num_phases); -- shifts window and sets first_cycle = false
end procedure find_last_failing_phase;
procedure find_first_passing_phase
( working : inout t_window_processing;
num_phases : in natural range 1 to c_max_phase_shifts
) is
begin
if working.first_cycle = false then -- not first call to procedure
if working.current_bit = 0 then -- and working.found_a_good_edge = false then
if working.valid_phase_seen = false then
working.status := no_valid_phases;
elsif working.invalid_phase_seen = false then
working.status := no_invalid_phases;
else
working.status := valid_result;
end if;
end if;
end if;
if working.working_window(0) = '1' and working.last_bit_value = '0' and working.status = calculating then
working.current_window_start := working.current_bit;
end if;
shift_window(working, num_phases); -- shifts window and sets first_cycle = false
end procedure find_first_passing_phase;
-- shift in current pass/fail result to the working window
procedure shift_in(
working : inout t_window_processing;
status : in std_logic;
num_phases : in natural range 1 to c_max_phase_shifts
) is
begin
working.last_bit_value := working.working_window(0);
working.working_window(num_phases-1 downto 0) := (working.working_window(0) and status) & working.working_window(num_phases-1 downto 1);
end procedure;
-- The following function sets the width over which
-- write latency should be repeated on the dq bus
-- the default value is MEM_IF_DQ_PER_DQS
function set_wlat_dq_rep_width return natural is
begin
for i in 1 to MEM_IF_DWIDTH/MEM_IF_DQ_PER_DQS loop
if (i*MEM_IF_DQ_PER_DQS) >= ADV_LAT_WIDTH then
return i*MEM_IF_DQ_PER_DQS;
end if;
end loop;
report dgrb_report_prefix & "the specified maximum write latency cannot be fully represented in the given number of DQ pins" & LF &
"** NOTE: This may cause overflow when setting ctl_wlat signal" severity warning;
return MEM_IF_DQ_PER_DQS;
end function;
-- extract PHY 'addr/cmd' to 'wdata_valid' write latency from current read data
function wd_lat_from_rdata(signal rdata : in std_logic_vector(DWIDTH_RATIO * MEM_IF_DWIDTH - 1 downto 0))
return std_logic_vector is
variable v_wd_lat : std_logic_vector(ADV_LAT_WIDTH - 1 downto 0);
begin
v_wd_lat := (others => '0');
if set_wlat_dq_rep_width >= ADV_LAT_WIDTH then
v_wd_lat := rdata(v_wd_lat'high downto 0);
else
v_wd_lat := (others => '0');
v_wd_lat(set_wlat_dq_rep_width - 1 downto 0) := rdata(set_wlat_dq_rep_width - 1 downto 0);
end if;
return v_wd_lat;
end function;
-- check if rdata_valid is correctly aligned
function rdata_valid_aligned(
signal rdata : in std_logic_vector(DWIDTH_RATIO * MEM_IF_DWIDTH - 1 downto 0);
signal rdata_valid : in std_logic_vector(DWIDTH_RATIO/2 - 1 downto 0)
) return std_logic is
variable v_dq_rdata : std_logic_vector(DWIDTH_RATIO - 1 downto 0);
variable v_aligned : std_logic;
begin
-- Look at data from a single DQ pin 0 (DWIDTH_RATIO data bits)
for i in 0 to DWIDTH_RATIO - 1 loop
v_dq_rdata(i) := rdata(i*MEM_IF_DWIDTH);
end loop;
-- Check each alignment (necessary because in the HR case rdata can be in any alignment)
v_aligned := '0';
for i in 0 to DWIDTH_RATIO/2 - 1 loop
if rdata_valid(i) = '1' then
if v_dq_rdata(2*i + 1 downto 2*i) = "00" then
v_aligned := '1';
end if;
end if;
end loop;
return v_aligned;
end function;
-- set severity level for calibration failures
function set_cal_fail_sev_level (
generate_additional_debug_rtl : natural
) return severity_level is
begin
if generate_additional_debug_rtl = 1 then
return warning;
else
return failure;
end if;
end function;
constant cal_fail_sev_level : severity_level := set_cal_fail_sev_level(GENERATE_ADDITIONAL_DBG_RTL);
-- ------------------------------------------------------------------
-- signal declarations
-- rsc = resync - the mechanism of capturing DQ pin data onto a local clock domain
-- trk = tracking - a mechanism to track rsc clock phase with PVT variations
-- poa = postamble - protection circuitry from postamble glitched on DQS
-- ac = memory address / command signals
-- ------------------------------------------------------------------
-- main state machine
signal sig_dgrb_state : t_dgrb_state;
signal sig_dgrb_last_state : t_dgrb_state;
signal sig_rsc_req : t_resync_state; -- tells resync block which state to transition to.
-- centre of data-valid window process
signal sig_cdvw_state : t_window_processing;
-- control signals for the address/command process
signal sig_addr_cmd : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
signal sig_ac_req : t_ac_state;
signal sig_dimm_driving_dq : std_logic;
signal sig_doing_rd : std_logic_vector(MEM_IF_DQS_WIDTH * DWIDTH_RATIO/2 - 1 downto 0);
signal sig_ac_even : std_logic; -- odd/even count of PHY clock cycles.
--
-- sig_ac_even behaviour
--
-- sig_ac_even is always '1' on the cycle a command is issued. It will
-- be '1' on even clock cycles thereafter and '0' otherwise.
--
-- ; ; ; ; ; ;
-- ; _______ ; ; ; ; ;
-- XXXXX / \ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
-- addr/cmd XXXXXX CMD XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
-- XXXXX \_______/ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- _________ _________ _________
-- sig_ac_even ____| |_________| |_________| |__________
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- phy clk
-- count (0) (1) (2) (3) (4)
--
--
-- resync related signals
signal sig_rsc_ack : std_logic;
signal sig_rsc_err : std_logic;
signal sig_rsc_result : std_logic_vector(c_command_result_len - 1 downto 0 );
signal sig_rsc_cdvw_phase : std_logic;
signal sig_rsc_cdvw_shift_in : std_logic;
signal sig_rsc_cdvw_calc : std_logic;
signal sig_rsc_pll_start_reconfig : std_logic;
signal sig_rsc_pll_inc_dec_n : std_logic;
signal sig_rsc_ac_access_req : std_logic; -- High when the resync block requires a training pattern to be read.
-- tracking related signals
signal sig_trk_ack : std_logic;
signal sig_trk_err : std_logic;
signal sig_trk_result : std_logic_vector(c_command_result_len - 1 downto 0 );
signal sig_trk_cdvw_phase : std_logic;
signal sig_trk_cdvw_shift_in : std_logic;
signal sig_trk_cdvw_calc : std_logic;
signal sig_trk_pll_start_reconfig : std_logic;
signal sig_trk_pll_select : std_logic_vector(CLOCK_INDEX_WIDTH - 1 DOWNTO 0);
signal sig_trk_pll_inc_dec_n : std_logic;
signal sig_trk_rsc_drift : integer range -c_max_rsc_drift_in_phases to c_max_rsc_drift_in_phases; -- stores total change in rsc phase from first calibration
-- phs_shft_busy could (potentially) be asynchronous
-- triple register it for metastability hardening
-- these signals are the taps on the shift register
signal sig_phs_shft_busy : std_logic;
signal sig_phs_shft_busy_1t : std_logic;
signal sig_phs_shft_start : std_logic;
signal sig_phs_shft_end : std_logic;
-- locally register crl_dgrb to minimise fan out
signal ctrl_dgrb_r : t_ctrl_command;
-- command_op signals
signal current_cs : natural range 0 to MEM_IF_NUM_RANKS - 1;
signal current_mtp_almt : natural range 0 to 1;
signal single_bit_cal : std_logic;
-- codvw status signals (packed into record and sent to mmi block)
signal cal_codvw_phase : std_logic_vector(7 downto 0);
signal codvw_trk_shift : std_logic_vector(11 downto 0);
signal cal_codvw_size : std_logic_vector(7 downto 0);
-- error signal and result from main state machine (operations other than rsc or tracking)
signal sig_cmd_err : std_logic;
signal sig_cmd_result : std_logic_vector(c_command_result_len - 1 downto 0 );
-- signals that the training pattern matched correctly on the last clock
-- cycle.
signal sig_dq_pin_ctr : natural range 0 to MEM_IF_DWIDTH - 1;
signal sig_mtp_match : std_logic;
-- controls postamble match and timing.
signal sig_poa_match_en : std_logic;
signal sig_poa_match : std_logic;
-- postamble signals
signal sig_poa_ack : std_logic; -- '1' for postamble block to acknowledge.
-- calibration byte lane select
signal cal_byte_lanes : std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
signal codvw_grt_one_dvw : std_logic;
begin
doing_rd <= sig_doing_rd;
-- pack record of codvw status signals
dgrb_mmi.cal_codvw_phase <= cal_codvw_phase;
dgrb_mmi.codvw_trk_shift <= codvw_trk_shift;
dgrb_mmi.cal_codvw_size <= cal_codvw_size;
dgrb_mmi.codvw_grt_one_dvw <= codvw_grt_one_dvw;
-- map some internal signals to outputs
dgrb_ac <= sig_addr_cmd;
-- locally register crl_dgrb to minimise fan out
process (clk, rst_n)
begin
if rst_n = '0' then
ctrl_dgrb_r <= defaults;
elsif rising_edge(clk) then
ctrl_dgrb_r <= ctrl_dgrb;
end if;
end process;
-- generate the current_cs signal to track which cs accessed by PHY at any instance
current_cs_proc : process (clk, rst_n)
begin
if rst_n = '0' then
current_cs <= 0;
current_mtp_almt <= 0;
single_bit_cal <= '0';
cal_byte_lanes <= (others => '0');
elsif rising_edge(clk) then
if ctrl_dgrb_r.command_req = '1' then
current_cs <= ctrl_dgrb_r.command_op.current_cs;
current_mtp_almt <= ctrl_dgrb_r.command_op.mtp_almt;
single_bit_cal <= ctrl_dgrb_r.command_op.single_bit;
end if;
-- mux byte lane select for given chip select
for i in 0 to MEM_IF_DQS_WIDTH - 1 loop
cal_byte_lanes(i) <= ctl_cal_byte_lanes((current_cs * MEM_IF_DQS_WIDTH) + i);
end loop;
assert ctl_cal_byte_lanes(0) = '1' report dgrb_report_prefix & " Byte lane 0 (chip select 0) disable is not supported - ending simulation" severity failure;
end if;
end process;
-- ------------------------------------------------------------------
-- main state machine for dgrb architecture
--
-- process of commands from control (ctrl) block and overall control of
-- the subsequent calibration processing functions
-- also communicates completion and any errors back to the ctrl block
-- read data valid alignment and advertised latency calculations are
-- included in this block
-- ------------------------------------------------------------------
dgrb_main_block : block
signal sig_count : natural range 0 to 2**8 - 1;
signal sig_wd_lat : std_logic_vector(ADV_LAT_WIDTH - 1 downto 0);
begin
dgrb_state_proc : process(rst_n, clk)
begin
if rst_n = '0' then
-- initialise state
sig_dgrb_state <= s_idle;
sig_dgrb_last_state <= s_idle;
sig_ac_req <= s_ac_idle;
sig_rsc_req <= s_rsc_idle;
-- set up rd_lat defaults
rd_lat <= c_default_rd_lat_slv;
wd_lat <= c_default_wd_lat_slv;
-- set up rdata_valid latency control defaults
seq_rdata_valid_lat_inc <= '0';
seq_rdata_valid_lat_dec <= '0';
-- reset counter
sig_count <= 0;
-- error signals
sig_cmd_err <= '0';
sig_cmd_result <= (others => '0');
-- sig_wd_lat
sig_wd_lat <= (others => '0');
-- status of the ac_nt alignment
dgrb_ctrl_ac_nt_good <= '1';
elsif rising_edge(clk) then
sig_dgrb_last_state <= sig_dgrb_state;
sig_rsc_req <= s_rsc_idle;
-- set up rdata_valid latency control defaults
seq_rdata_valid_lat_inc <= '0';
seq_rdata_valid_lat_dec <= '0';
-- error signals
sig_cmd_err <= '0';
sig_cmd_result <= (others => '0');
-- register wd_lat output.
wd_lat <= sig_wd_lat;
case sig_dgrb_state is
when s_idle =>
sig_count <= 0;
if ctrl_dgrb_r.command_req = '1' then
if curr_active_block(ctrl_dgrb_r.command) = dgrb then
sig_dgrb_state <= s_wait_admin;
end if;
end if;
sig_ac_req <= s_ac_idle;
when s_wait_admin =>
sig_dgrb_state <= s_wait_admin;
case ctrl_dgrb_r.command is
when cmd_read_mtp => sig_dgrb_state <= s_read_mtp;
when cmd_rrp_reset => sig_dgrb_state <= s_reset_cdvw;
when cmd_rrp_sweep => sig_dgrb_state <= s_test_phases;
when cmd_rrp_seek => sig_dgrb_state <= s_seek_cdvw;
when cmd_rdv => sig_dgrb_state <= s_rdata_valid_align;
when cmd_prep_adv_rd_lat => sig_dgrb_state <= s_adv_rd_lat_setup;
when cmd_prep_adv_wr_lat => sig_dgrb_state <= s_adv_wd_lat;
when cmd_tr_due => sig_dgrb_state <= s_track;
when cmd_poa => sig_dgrb_state <= s_poa_cal;
when others =>
report dgrb_report_prefix & "unknown command" severity failure;
sig_dgrb_state <= s_idle;
end case;
when s_reset_cdvw =>
-- the cdvw proc watches for this state and resets the cdvw
-- state block.
if sig_rsc_ack = '1' then
sig_dgrb_state <= s_release_admin;
else
sig_rsc_req <= s_rsc_reset_cdvw;
end if;
when s_test_phases =>
if sig_rsc_ack = '1' then
sig_dgrb_state <= s_release_admin;
else
sig_rsc_req <= s_rsc_test_phase;
if sig_rsc_ac_access_req = '1' then
sig_ac_req <= s_ac_read_mtp;
else
sig_ac_req <= s_ac_idle;
end if;
end if;
when s_seek_cdvw | s_read_mtp =>
if sig_rsc_ack = '1' then
sig_dgrb_state <= s_release_admin;
else
sig_rsc_req <= s_rsc_cdvw_calc;
end if;
when s_release_admin =>
sig_ac_req <= s_ac_idle;
if dgrb_ac_access_gnt = '0' and sig_dimm_driving_dq = '0' then
sig_dgrb_state <= s_idle;
end if;
when s_rdata_valid_align =>
sig_ac_req <= s_ac_read_rdv;
seq_rdata_valid_lat_dec <= '0';
seq_rdata_valid_lat_inc <= '0';
if sig_dimm_driving_dq = '1' then
-- only do comparison if rdata_valid is all 'ones'
if rdata_valid /= std_logic_vector(to_unsigned(0, DWIDTH_RATIO/2)) then
-- rdata_valid is all ones
if rdata_valid_aligned(rdata, rdata_valid) = '1' then
-- success: rdata_valid and rdata are properly aligned
sig_dgrb_state <= s_release_admin;
else
-- misaligned: bring in rdata_valid by a clock cycle
seq_rdata_valid_lat_dec <= '1';
end if;
end if;
end if;
when s_adv_rd_lat_setup =>
-- wait for sig_doing_rd to go high
sig_ac_req <= s_ac_read_rdv;
if sig_dgrb_state /= sig_dgrb_last_state then
rd_lat <= (others => '0');
sig_count <= 0;
elsif sig_dimm_driving_dq = '1' and sig_doing_rd(MEM_IF_DQS_WIDTH*(DWIDTH_RATIO/2-1)) = '1' then
-- a read has started: start counter
sig_dgrb_state <= s_adv_rd_lat;
end if;
when s_adv_rd_lat =>
sig_ac_req <= s_ac_read_rdv;
if sig_dimm_driving_dq = '1' then
if sig_count >= 2**rd_lat'length then
report dgrb_report_prefix & "maximum read latency exceeded while waiting for rdata_valid" severity cal_fail_sev_level;
sig_cmd_err <= '1';
sig_cmd_result <= std_logic_vector(to_unsigned(C_ERR_MAX_RD_LAT_EXCEEDED,sig_cmd_result'length));
end if;
if rdata_valid /= std_logic_vector(to_unsigned(0, rdata_valid'length)) then
-- have found the read latency
sig_dgrb_state <= s_release_admin;
else
sig_count <= sig_count + 1;
end if;
rd_lat <= std_logic_vector(to_unsigned(sig_count, rd_lat'length));
end if;
when s_adv_wd_lat =>
sig_ac_req <= s_ac_read_wd_lat;
if sig_dgrb_state /= sig_dgrb_last_state then
sig_wd_lat <= (others => '0');
else
if sig_dimm_driving_dq = '1' and rdata_valid /= std_logic_vector(to_unsigned(0, rdata_valid'length)) then
-- construct wd_lat using data from the lowest addresses
-- wd_lat <= rdata(MEM_IF_DQ_PER_DQS - 1 downto 0);
sig_wd_lat <= wd_lat_from_rdata(rdata);
sig_dgrb_state <= s_release_admin;
-- check data integrity
for i in 1 to MEM_IF_DWIDTH/set_wlat_dq_rep_width - 1 loop
-- wd_lat is copied across MEM_IF_DWIDTH bits in fields of width MEM_IF_DQ_PER_DQS.
-- All of these fields must have the same value or it is an error.
-- only check if byte lane not disabled
if cal_byte_lanes((i*set_wlat_dq_rep_width)/MEM_IF_DQ_PER_DQS) = '1' then
if rdata(set_wlat_dq_rep_width - 1 downto 0) /= rdata((i+1)*set_wlat_dq_rep_width - 1 downto i*set_wlat_dq_rep_width) then
-- signal write latency different between DQS groups
report dgrb_report_prefix & "the write latency read from memory is different accross dqs groups" severity cal_fail_sev_level;
sig_cmd_err <= '1';
sig_cmd_result <= std_logic_vector(to_unsigned(C_ERR_WD_LAT_DISAGREEMENT, sig_cmd_result'length));
end if;
end if;
end loop;
-- check if ac_nt alignment is ok
-- in this condition all DWIDTH_RATIO copies of rdata should be identical
dgrb_ctrl_ac_nt_good <= '1';
if DWIDTH_RATIO /= 2 then
for j in 0 to DWIDTH_RATIO/2 - 1 loop
if rdata(j*MEM_IF_DWIDTH + MEM_IF_DQ_PER_DQS - 1 downto j*MEM_IF_DWIDTH) /= rdata((j+2)*MEM_IF_DWIDTH + MEM_IF_DQ_PER_DQS - 1 downto (j+2)*MEM_IF_DWIDTH) then
dgrb_ctrl_ac_nt_good <= '0';
end if;
end loop;
end if;
end if;
end if;
when s_poa_cal =>
-- Request the address/command block begins reading the "M"
-- training pattern here. There is no provision for doing
-- refreshes so this limits the time spent in this state
-- to 9 x tREFI (by the DDR2 JEDEC spec). Instead of the
-- maximum value, a maximum "safe" time in this postamble
-- state is chosen to be tpoamax = 5 x tREFI = 5 x 3.9us.
-- When entering this s_poa_cal state it must be guaranteed
-- that the number of stacked refreshes is at maximum.
--
-- Minimum clock freq supported by DRAM is fck,min=125MHz.
-- Each adjustment to postamble latency requires 16*clock
-- cycles (time to read "M" training pattern twice) so
-- maximum number of adjustments to POA latency (n) is:
--
-- n = (5 x trefi x fck,min) / 16
-- = (5 x 3.9us x 125MHz) / 16
-- ~ 152
--
-- Postamble latency must be adjusted less than 152 cycles
-- to meet this requirement.
--
sig_ac_req <= s_ac_read_poa_mtp;
if sig_poa_ack = '1' then
sig_dgrb_state <= s_release_admin;
end if;
when s_track =>
if sig_trk_ack = '1' then
sig_dgrb_state <= s_release_admin;
end if;
when others => null;
report dgrb_report_prefix & "undefined state" severity failure;
sig_dgrb_state <= s_idle;
end case;
-- default if not calibrating go to idle state via s_release_admin
if ctrl_dgrb_r.command = cmd_idle and
sig_dgrb_state /= s_idle and
sig_dgrb_state /= s_release_admin then
sig_dgrb_state <= s_release_admin;
end if;
end if;
end process;
end block;
-- ------------------------------------------------------------------
-- metastability hardening of potentially async phs_shift_busy signal
--
-- Triple register it for metastability hardening. This process
-- creates the shift register. Also add a sig_phs_shft_busy and
-- an sig_phs_shft_busy_1t echo because various other processes find
-- this useful.
-- ------------------------------------------------------------------
phs_shft_busy_reg: block
signal phs_shft_busy_1r : std_logic;
signal phs_shft_busy_2r : std_logic;
signal phs_shft_busy_3r : std_logic;
begin
phs_shift_busy_sync : process (clk, rst_n)
begin
if rst_n = '0' then
sig_phs_shft_busy <= '0';
sig_phs_shft_busy_1t <= '0';
phs_shft_busy_1r <= '0';
phs_shft_busy_2r <= '0';
phs_shft_busy_3r <= '0';
sig_phs_shft_start <= '0';
sig_phs_shft_end <= '0';
elsif rising_edge(clk) then
sig_phs_shft_busy_1t <= phs_shft_busy_3r;
sig_phs_shft_busy <= phs_shft_busy_2r;
-- register the below to reduce fan out on sig_phs_shft_busy and sig_phs_shft_busy_1t
sig_phs_shft_start <= phs_shft_busy_3r or phs_shft_busy_2r;
sig_phs_shft_end <= phs_shft_busy_3r and not(phs_shft_busy_2r);
phs_shft_busy_3r <= phs_shft_busy_2r;
phs_shft_busy_2r <= phs_shft_busy_1r;
phs_shft_busy_1r <= phs_shft_busy;
end if;
end process;
end block;
-- ------------------------------------------------------------------
-- PLL reconfig MUX
--
-- switches PLL Reconfig input between tracking and resync blocks
-- ------------------------------------------------------------------
pll_reconf_mux : process (clk, rst_n)
begin
if rst_n = '0' then
seq_pll_inc_dec_n <= '0';
seq_pll_select <= (others => '0');
seq_pll_start_reconfig <= '0';
elsif rising_edge(clk) then
if sig_dgrb_state = s_seek_cdvw or
sig_dgrb_state = s_test_phases or
sig_dgrb_state = s_reset_cdvw then
seq_pll_select <= pll_resync_clk_index;
seq_pll_inc_dec_n <= sig_rsc_pll_inc_dec_n;
seq_pll_start_reconfig <= sig_rsc_pll_start_reconfig;
elsif sig_dgrb_state = s_track then
seq_pll_select <= sig_trk_pll_select;
seq_pll_inc_dec_n <= sig_trk_pll_inc_dec_n;
seq_pll_start_reconfig <= sig_trk_pll_start_reconfig;
else
seq_pll_select <= pll_measure_clk_index;
seq_pll_inc_dec_n <= '0';
seq_pll_start_reconfig <= '0';
end if;
end if;
end process;
-- ------------------------------------------------------------------
-- Centre of data valid window calculation block
--
-- This block handles the sharing of the centre of window calculation
-- logic between the rsc and trk operations. Functions defined in the
-- header of this entity are called to do this.
-- ------------------------------------------------------------------
cdvw_block : block
signal sig_cdvw_calc_1t : std_logic;
begin
-- purpose: manages centre of data valid window calculations
-- type : sequential
-- inputs : clk, rst_n
-- outputs: sig_cdvw_state
cdvw_proc: process (clk, rst_n)
variable v_cdvw_state : t_window_processing;
variable v_start_calc : std_logic;
variable v_shift_in : std_logic;
variable v_phase : std_logic;
begin -- process cdvw_proc
if rst_n = '0' then -- asynchronous reset (active low)
sig_cdvw_state <= defaults;
sig_cdvw_calc_1t <= '0';
elsif rising_edge(clk) then -- rising clock edge
v_cdvw_state := sig_cdvw_state;
case sig_dgrb_state is
when s_track =>
v_start_calc := sig_trk_cdvw_calc;
v_phase := sig_trk_cdvw_phase;
v_shift_in := sig_trk_cdvw_shift_in;
when s_read_mtp | s_seek_cdvw | s_test_phases =>
v_start_calc := sig_rsc_cdvw_calc;
v_phase := sig_rsc_cdvw_phase;
v_shift_in := sig_rsc_cdvw_shift_in;
when others =>
v_start_calc := '0';
v_phase := '0';
v_shift_in := '0';
end case;
if sig_dgrb_state = s_reset_cdvw or (sig_dgrb_state = s_track and sig_dgrb_last_state /= s_track) then
-- reset *C*entre of *D*ata *V*alid *W*indow
v_cdvw_state := defaults;
elsif sig_cdvw_calc_1t /= '1' and v_start_calc = '1' then
initialise_window_for_proc(v_cdvw_state);
elsif v_cdvw_state.status = calculating then
if sig_dgrb_state = s_track then -- ensure 360 degrees sweep
find_centre_of_largest_data_valid_window(v_cdvw_state, PLL_STEPS_PER_CYCLE);
else -- can be a 720 degrees sweep
find_centre_of_largest_data_valid_window(v_cdvw_state, c_max_phase_shifts);
end if;
elsif v_shift_in = '1' then
if sig_dgrb_state = s_track then -- ensure 360 degrees sweep
shift_in(v_cdvw_state, v_phase, PLL_STEPS_PER_CYCLE);
else
shift_in(v_cdvw_state, v_phase, c_max_phase_shifts);
end if;
end if;
sig_cdvw_calc_1t <= v_start_calc;
sig_cdvw_state <= v_cdvw_state;
end if;
end process cdvw_proc;
end block;
-- ------------------------------------------------------------------
-- block for resync calculation.
--
-- This block implements the following:
-- 1) Control logic for the rsc slave state machine
-- 2) Processing of resync operations - through reports form cdvw block and
-- test pattern match blocks
-- 3) Shifting of the resync phase for rsc sweeps
-- 4) Writing of results to iram (optional)
-- ------------------------------------------------------------------
rsc_block : block
signal sig_rsc_state : t_resync_state;
signal sig_rsc_last_state : t_resync_state;
signal sig_num_phase_shifts : natural range c_max_phase_shifts - 1 downto 0;
signal sig_rewind_direction : std_logic;
signal sig_count : natural range 0 to 2**8 - 1;
signal sig_test_dq_expired : std_logic;
signal sig_chkd_all_dq_pins : std_logic;
-- prompts to write data to iram
signal sig_dgrb_iram : t_iram_push; -- internal copy of dgrb to iram control signals
signal sig_rsc_push_rrp_sweep : std_logic; -- push result of a rrp sweep pass (for cmd_rrp_sweep)
signal sig_rsc_push_rrp_pass : std_logic; -- result of a rrp sweep result (for cmd_rrp_sweep)
signal sig_rsc_push_rrp_seek : std_logic; -- write seek results (for cmd_rrp_seek / cmd_read_mtp states)
signal sig_rsc_push_footer : std_logic; -- write a footer
signal sig_dq_pin_ctr_r : natural range 0 to MEM_IF_DWIDTH - 1; -- registered version of dq_pin_ctr
signal sig_rsc_curr_phase : natural range 0 to c_max_phase_shifts - 1; -- which phase is being processed
signal sig_iram_idle : std_logic; -- track if iram currently writing data
signal sig_mtp_match_en : std_logic;
-- current byte lane disabled?
signal sig_curr_byte_ln_dis : std_logic;
signal sig_iram_wds_req : integer; -- words required for a given iram dump (used to locate where to write footer)
begin
-- When using DQS capture or not at full-rate only match on "even" clock cycles.
sig_mtp_match_en <= active_high(sig_ac_even = '1' or MEM_IF_DQS_CAPTURE = 0 or DWIDTH_RATIO /= 2);
-- register current byte lane disable mux for speed
byte_lane_dis: process (clk, rst_n)
begin
if rst_n = '0' then
sig_curr_byte_ln_dis <= '0';
elsif rising_edge(clk) then
sig_curr_byte_ln_dis <= cal_byte_lanes(sig_dq_pin_ctr/MEM_IF_DQ_PER_DQS);
end if;
end process;
-- check if all dq pins checked in rsc sweep
chkd_dq : process (clk, rst_n)
begin
if rst_n = '0' then
sig_chkd_all_dq_pins <= '0';
elsif rising_edge(clk) then
if sig_dq_pin_ctr = 0 then
sig_chkd_all_dq_pins <= '1';
else
sig_chkd_all_dq_pins <= '0';
end if;
end if;
end process;
-- main rsc process
rsc_proc : process (clk, rst_n)
-- these are temporary variables which should not infer FFs and
-- are not guaranteed to be initialized by s_rsc_idle.
variable v_rdata_correct : std_logic;
variable v_phase_works : std_logic;
begin
if rst_n = '0' then
-- initialise signals
sig_rsc_state <= s_rsc_idle;
sig_rsc_last_state <= s_rsc_idle;
sig_dq_pin_ctr <= 0;
sig_num_phase_shifts <= c_max_phase_shifts - 1; -- want c_max_phase_shifts-1 inc / decs of phase
sig_count <= 0;
sig_test_dq_expired <= '0';
v_phase_works := '0';
-- interface to other processes to tell them when we are done.
sig_rsc_ack <= '0';
sig_rsc_err <= '0';
sig_rsc_result <= std_logic_vector(to_unsigned(C_SUCCESS, c_command_result_len));
-- centre of data valid window functions
sig_rsc_cdvw_phase <= '0';
sig_rsc_cdvw_shift_in <= '0';
sig_rsc_cdvw_calc <= '0';
-- set up PLL reconfig interface controls
sig_rsc_pll_start_reconfig <= '0';
sig_rsc_pll_inc_dec_n <= c_pll_phs_inc;
sig_rewind_direction <= c_pll_phs_dec;
-- True when access to the ac_block is required.
sig_rsc_ac_access_req <= '0';
-- default values on centre and size of data valid window
if SIM_TIME_REDUCTIONS = 1 then
cal_codvw_phase <= std_logic_vector(to_unsigned(PRESET_CODVW_PHASE, 8));
cal_codvw_size <= std_logic_vector(to_unsigned(PRESET_CODVW_SIZE, 8));
else
cal_codvw_phase <= (others => '0');
cal_codvw_size <= (others => '0');
end if;
sig_rsc_push_rrp_sweep <= '0';
sig_rsc_push_rrp_seek <= '0';
sig_rsc_push_rrp_pass <= '0';
sig_rsc_push_footer <= '0';
codvw_grt_one_dvw <= '0';
elsif rising_edge(clk) then
-- default values assigned to some signals
sig_rsc_ack <= '0';
sig_rsc_cdvw_phase <= '0';
sig_rsc_cdvw_shift_in <= '0';
sig_rsc_cdvw_calc <= '0';
sig_rsc_pll_start_reconfig <= '0';
sig_rsc_pll_inc_dec_n <= c_pll_phs_inc;
sig_rewind_direction <= c_pll_phs_dec;
-- by default don't ask the resync block to read anything
sig_rsc_ac_access_req <= '0';
sig_rsc_push_rrp_sweep <= '0';
sig_rsc_push_rrp_seek <= '0';
sig_rsc_push_rrp_pass <= '0';
sig_rsc_push_footer <= '0';
sig_test_dq_expired <= '0';
-- resync state machine
case sig_rsc_state is
when s_rsc_idle =>
-- initialize those signals we are ready to use.
sig_dq_pin_ctr <= 0;
sig_count <= 0;
if sig_rsc_state = sig_rsc_last_state then -- avoid transition when acknowledging a command has finished
if sig_rsc_req = s_rsc_test_phase then
sig_rsc_state <= s_rsc_test_phase;
elsif sig_rsc_req = s_rsc_cdvw_calc then
sig_rsc_state <= s_rsc_cdvw_calc;
elsif sig_rsc_req = s_rsc_seek_cdvw then
sig_rsc_state <= s_rsc_seek_cdvw;
elsif sig_rsc_req = s_rsc_reset_cdvw then
sig_rsc_state <= s_rsc_reset_cdvw;
else
sig_rsc_state <= s_rsc_idle;
end if;
end if;
when s_rsc_next_phase =>
sig_rsc_pll_inc_dec_n <= c_pll_phs_inc;
sig_rsc_pll_start_reconfig <= '1';
if sig_phs_shft_start = '1' then
-- PLL phase shift started - so stop requesting a shift
sig_rsc_pll_start_reconfig <= '0';
end if;
if sig_phs_shft_end = '1' then
-- PLL phase shift finished - so proceed to flush the datapath
sig_num_phase_shifts <= sig_num_phase_shifts - 1;
sig_rsc_state <= s_rsc_test_phase;
end if;
when s_rsc_test_phase =>
v_phase_works := '1';
-- Note: For single pin single CS calibration set sig_dq_pin_ctr to 0 to
-- ensure that only 1 pin calibrated
sig_rsc_state <= s_rsc_wait_for_idle_dimm;
if single_bit_cal = '1' then
sig_dq_pin_ctr <= 0;
else
sig_dq_pin_ctr <= MEM_IF_DWIDTH-1;
end if;
when s_rsc_wait_for_idle_dimm =>
if sig_dimm_driving_dq = '0' then
sig_rsc_state <= s_rsc_flush_datapath;
end if;
when s_rsc_flush_datapath =>
sig_rsc_ac_access_req <= '1';
if sig_rsc_state /= sig_rsc_last_state then
-- reset variables we are interested in when we first arrive in this state.
sig_count <= c_max_read_lat - 1;
else
if sig_dimm_driving_dq = '1' then
if sig_count = 0 then
sig_rsc_state <= s_rsc_test_dq;
else
sig_count <= sig_count - 1;
end if;
end if;
end if;
when s_rsc_test_dq =>
sig_rsc_ac_access_req <= '1';
if sig_rsc_state /= sig_rsc_last_state then
-- reset variables we are interested in when we first arrive in this state.
sig_count <= 2*c_cal_mtp_t;
else
if sig_dimm_driving_dq = '1' then
if (
(sig_mtp_match = '1' and sig_mtp_match_en = '1') or -- have a pattern match
(sig_test_dq_expired = '1') or -- time in this phase has expired.
sig_curr_byte_ln_dis = '0' -- byte lane disabled
) then
v_phase_works := v_phase_works and ((sig_mtp_match and sig_mtp_match_en) or (not sig_curr_byte_ln_dis));
sig_rsc_push_rrp_sweep <= '1';
sig_rsc_push_rrp_pass <= (sig_mtp_match and sig_mtp_match_en) or (not sig_curr_byte_ln_dis);
if sig_chkd_all_dq_pins = '1' then
-- finished checking all dq pins.
-- done checking this phase.
-- shift phase status into
sig_rsc_cdvw_phase <= v_phase_works;
sig_rsc_cdvw_shift_in <= '1';
if sig_num_phase_shifts /= 0 then
-- there are more phases to test so shift to next phase
sig_rsc_state <= s_rsc_next_phase;
else
-- no more phases to check.
-- clean up after ourselves by
-- going into s_rsc_rewind_phase
sig_rsc_state <= s_rsc_rewind_phase;
sig_rewind_direction <= c_pll_phs_dec;
sig_num_phase_shifts <= c_max_phase_shifts - 1;
end if;
else
-- shift to next dq pin
if MEM_IF_DWIDTH > 71 and -- if >= 72 pins then:
(sig_dq_pin_ctr mod 64) = 0 then -- ensure refreshes at least once every 64 pins
sig_rsc_state <= s_rsc_wait_for_idle_dimm;
else -- otherwise continue sweep
sig_rsc_state <= s_rsc_flush_datapath;
end if;
sig_dq_pin_ctr <= sig_dq_pin_ctr - 1;
end if;
else
sig_count <= sig_count - 1;
if sig_count = 1 then
sig_test_dq_expired <= '1';
end if;
end if;
end if;
end if;
when s_rsc_reset_cdvw =>
sig_rsc_state <= s_rsc_rewind_phase;
-- determine the amount to rewind by (may be wind forward depending on tracking behaviour)
if to_integer(unsigned(cal_codvw_phase)) + sig_trk_rsc_drift < 0 then
sig_num_phase_shifts <= - (to_integer(unsigned(cal_codvw_phase)) + sig_trk_rsc_drift);
sig_rewind_direction <= c_pll_phs_inc;
else
sig_num_phase_shifts <= (to_integer(unsigned(cal_codvw_phase)) + sig_trk_rsc_drift);
sig_rewind_direction <= c_pll_phs_dec;
end if;
-- reset the calibrated phase and size to zero (because un-doing prior calibration here)
cal_codvw_phase <= (others => '0');
cal_codvw_size <= (others => '0');
when s_rsc_rewind_phase =>
-- rewinds the resync PLL by sig_num_phase_shifts steps and returns to idle state
if sig_num_phase_shifts = 0 then
-- no more steps to take off, go to next state
sig_num_phase_shifts <= c_max_phase_shifts - 1;
if GENERATE_ADDITIONAL_DBG_RTL = 1 then -- if iram present hold off until access finished
sig_rsc_state <= s_rsc_wait_iram;
else
sig_rsc_ack <= '1';
sig_rsc_state <= s_rsc_idle;
end if;
else
sig_rsc_pll_inc_dec_n <= sig_rewind_direction;
-- request a phase shift
sig_rsc_pll_start_reconfig <= '1';
if sig_phs_shft_busy = '1' then
-- inhibit a phase shift if phase shift is busy.
sig_rsc_pll_start_reconfig <= '0';
end if;
if sig_phs_shft_busy_1t = '1' and sig_phs_shft_busy /= '1' then
-- we've just successfully removed a phase step
-- decrement counter
sig_num_phase_shifts <= sig_num_phase_shifts - 1;
sig_rsc_pll_start_reconfig <= '0';
end if;
end if;
when s_rsc_cdvw_calc =>
if sig_rsc_state /= sig_rsc_last_state then
if sig_dgrb_state = s_read_mtp then
report dgrb_report_prefix & "gathered resync phase samples (for mtp alignment " & natural'image(current_mtp_almt) & ") is DGRB_PHASE_SAMPLES: " & str(sig_cdvw_state.working_window) severity note;
else
report dgrb_report_prefix & "gathered resync phase samples DGRB_PHASE_SAMPLES: " & str(sig_cdvw_state.working_window) severity note;
end if;
sig_rsc_cdvw_calc <= '1'; -- begin calculating result
else
sig_rsc_state <= s_rsc_cdvw_wait;
end if;
when s_rsc_cdvw_wait =>
if sig_cdvw_state.status /= calculating then
-- a result has been reached.
if sig_dgrb_state = s_read_mtp then -- if doing mtp alignment then skip setting phase
if GENERATE_ADDITIONAL_DBG_RTL = 1 then -- if iram present hold off until access finished
sig_rsc_state <= s_rsc_wait_iram;
else
sig_rsc_ack <= '1';
sig_rsc_state <= s_rsc_idle;
end if;
else
if sig_cdvw_state.status = valid_result then
-- calculation successfully found a
-- data-valid window to seek to.
sig_rsc_state <= s_rsc_seek_cdvw;
sig_rsc_result <= std_logic_vector(to_unsigned(C_SUCCESS, sig_rsc_result'length));
-- If more than one data valid window was seen, then set the result code :
if (sig_cdvw_state.windows_seen > 1) then
report dgrb_report_prefix & "Warning : multiple data-valid windows found, largest chosen." severity note;
codvw_grt_one_dvw <= '1';
else
report dgrb_report_prefix & "data-valid window found successfully." severity note;
end if;
else
-- calculation failed to find a data-valid window.
report dgrb_report_prefix & "couldn't find a data-valid window in resync." severity warning;
sig_rsc_ack <= '1';
sig_rsc_err <= '1';
sig_rsc_state <= s_rsc_idle;
-- set resync result code
case sig_cdvw_state.status is
when no_invalid_phases =>
sig_rsc_result <= std_logic_vector(to_unsigned(C_ERR_RESYNC_NO_VALID_PHASES, sig_rsc_result'length));
when multiple_equal_windows =>
sig_rsc_result <= std_logic_vector(to_unsigned(C_ERR_RESYNC_MULTIPLE_EQUAL_WINDOWS, sig_rsc_result'length));
when no_valid_phases =>
sig_rsc_result <= std_logic_vector(to_unsigned(C_ERR_RESYNC_NO_VALID_PHASES, sig_rsc_result'length));
when others =>
sig_rsc_result <= std_logic_vector(to_unsigned(C_ERR_CRITICAL, sig_rsc_result'length));
end case;
end if;
end if;
-- signal to write a rrp_sweep result to iram
if GENERATE_ADDITIONAL_DBG_RTL = 1 then
sig_rsc_push_rrp_seek <= '1';
end if;
end if;
when s_rsc_seek_cdvw =>
if sig_rsc_state /= sig_rsc_last_state then
-- reset variables we are interested in when we first arrive in this state
sig_count <= sig_cdvw_state.largest_window_centre;
else
if sig_count = 0 or
((MEM_IF_DQS_CAPTURE = 1 and DWIDTH_RATIO = 2) and
sig_count = PLL_STEPS_PER_CYCLE) -- if FR and DQS capture ensure within 0-360 degrees phase
then
-- ready to transition to next state
if GENERATE_ADDITIONAL_DBG_RTL = 1 then -- if iram present hold off until access finished
sig_rsc_state <= s_rsc_wait_iram;
else
sig_rsc_ack <= '1';
sig_rsc_state <= s_rsc_idle;
end if;
-- return largest window centre and size in the result
-- perform cal_codvw phase / size update only if a valid result is found
if sig_cdvw_state.status = valid_result then
cal_codvw_phase <= std_logic_vector(to_unsigned(sig_cdvw_state.largest_window_centre, 8));
cal_codvw_size <= std_logic_vector(to_unsigned(sig_cdvw_state.largest_window_size, 8));
end if;
-- leaving sig_rsc_err or sig_rsc_result at
-- their default values (of success)
else
sig_rsc_pll_inc_dec_n <= c_pll_phs_inc;
-- request a phase shift
sig_rsc_pll_start_reconfig <= '1';
if sig_phs_shft_start = '1' then
-- inhibit a phase shift if phase shift is busy
sig_rsc_pll_start_reconfig <= '0';
end if;
if sig_phs_shft_end = '1' then
-- we've just successfully removed a phase step
-- decrement counter
sig_count <= sig_count - 1;
end if;
end if;
end if;
when s_rsc_wait_iram =>
-- hold off check 1 clock cycle to enable last rsc push operations to start
if sig_rsc_state = sig_rsc_last_state then
if sig_iram_idle = '1' then
sig_rsc_ack <= '1';
sig_rsc_state <= s_rsc_idle;
if sig_dgrb_state = s_test_phases or
sig_dgrb_state = s_seek_cdvw or
sig_dgrb_state = s_read_mtp then
sig_rsc_push_footer <= '1';
end if;
end if;
end if;
when others =>
null;
end case;
sig_rsc_last_state <= sig_rsc_state;
end if;
end process;
-- write results to the iram
iram_push: process (clk, rst_n)
begin
if rst_n = '0' then
sig_dgrb_iram <= defaults;
sig_iram_idle <= '0';
sig_dq_pin_ctr_r <= 0;
sig_rsc_curr_phase <= 0;
sig_iram_wds_req <= 0;
elsif rising_edge(clk) then
if GENERATE_ADDITIONAL_DBG_RTL = 1 then
if sig_dgrb_iram.iram_write = '1' and sig_dgrb_iram.iram_done = '1' then
report dgrb_report_prefix & "iram_done and iram_write signals concurrently set - iram contents may be corrupted" severity failure;
end if;
if sig_dgrb_iram.iram_write = '0' and sig_dgrb_iram.iram_done = '0' then
sig_iram_idle <= '1';
else
sig_iram_idle <= '0';
end if;
-- registered sig_dq_pin_ctr to align with rrp_sweep result
sig_dq_pin_ctr_r <= sig_dq_pin_ctr;
-- calculate current phase (registered to align with rrp_sweep result)
sig_rsc_curr_phase <= (c_max_phase_shifts - 1) - sig_num_phase_shifts;
-- serial push of rrp_sweep results into memory
if sig_rsc_push_rrp_sweep = '1' then
-- signal an iram write and track a write pending
sig_dgrb_iram.iram_write <= '1';
sig_iram_idle <= '0';
-- if not single_bit_cal then pack pin phase results in MEM_IF_DWIDTH word blocks
if single_bit_cal = '1' then
sig_dgrb_iram.iram_wordnum <= sig_dq_pin_ctr_r + (sig_rsc_curr_phase/32);
sig_iram_wds_req <= iram_wd_for_one_pin_rrp( DWIDTH_RATIO, PLL_STEPS_PER_CYCLE, MEM_IF_DWIDTH, MEM_IF_DQS_CAPTURE); -- note total word requirement
else
sig_dgrb_iram.iram_wordnum <= sig_dq_pin_ctr_r + (sig_rsc_curr_phase/32) * MEM_IF_DWIDTH;
sig_iram_wds_req <= iram_wd_for_full_rrp( DWIDTH_RATIO, PLL_STEPS_PER_CYCLE, MEM_IF_DWIDTH, MEM_IF_DQS_CAPTURE); -- note total word requirement
end if;
-- check if current pin and phase passed:
sig_dgrb_iram.iram_pushdata(0) <= sig_rsc_push_rrp_pass;
-- bit offset is modulo phase
sig_dgrb_iram.iram_bitnum <= sig_rsc_curr_phase mod 32;
end if;
-- write result of rrp_calc to iram when completed
if sig_rsc_push_rrp_seek = '1' then -- a result found
sig_dgrb_iram.iram_write <= '1';
sig_iram_idle <= '0';
sig_dgrb_iram.iram_wordnum <= 0;
sig_iram_wds_req <= 1; -- note total word requirement
if sig_cdvw_state.status = valid_result then -- result is valid
sig_dgrb_iram.iram_pushdata <= x"0000" &
std_logic_vector(to_unsigned(sig_cdvw_state.largest_window_centre, 8)) &
std_logic_vector(to_unsigned(sig_cdvw_state.largest_window_size, 8));
else -- invalid result (error code communicated elsewhere)
sig_dgrb_iram.iram_pushdata <= x"FFFF" & -- signals an error condition
x"0000";
end if;
end if;
-- when stage finished write footer
if sig_rsc_push_footer = '1' then
sig_dgrb_iram.iram_done <= '1';
sig_iram_idle <= '0';
-- set address location of footer
sig_dgrb_iram.iram_wordnum <= sig_iram_wds_req;
end if;
-- if write completed deassert iram_write and done signals
if iram_push_done = '1' then
sig_dgrb_iram.iram_write <= '0';
sig_dgrb_iram.iram_done <= '0';
end if;
else
sig_iram_idle <= '0';
sig_dq_pin_ctr_r <= 0;
sig_rsc_curr_phase <= 0;
sig_dgrb_iram <= defaults;
end if;
end if;
end process;
-- concurrently assign sig_dgrb_iram to dgrb_iram
dgrb_iram <= sig_dgrb_iram;
end block; -- resync calculation
-- ------------------------------------------------------------------
-- test pattern match block
--
-- This block handles the sharing of logic for test pattern matching
-- which is used in resync and postamble calibration / code blocks
-- ------------------------------------------------------------------
tp_match_block : block
--
-- Ascii Waveforms:
--
-- ; ; ; ; ; ;
-- ____ ____ ____ ____ ____ ____
-- delayed_dqs |____| |____| |____| |____| |____| |____| |____|
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; _______ ; _______ ; _______ ; _______ ; _______ _______
-- XXXXX / \ / \ / \ / \ / \ / \
-- c0,c1 XXXXXX A B X C D X E F X G H X I J X L M X captured data
-- XXXXX \_______/ \_______/ \_______/ \_______/ \_______/ \_______/
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ____; ____; ____ ____ ____ ____ ____
-- 180-resync_clk |____| |____| |____| |____| |____| |____| | 180deg shift from delayed dqs
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; _______ _______ _______ _______ _______ ____
-- XXXXXXXXXX / \ / \ / \ / \ / \ /
-- 180-r0,r1 XXXXXXXXXXX A B X C D X E F X G H X I J X L resync data
-- XXXXXXXXXX \_______/ \_______/ \_______/ \_______/ \_______/ \____
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ____ ____ ____ ____ ____ ____
-- 360-resync_clk ____| |____| |____| |____| |____| |____| |____|
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; ; _______ ; _______ ; _______ ; _______ ; _______
-- XXXXXXXXXXXXXXX / \ / \ / \ / \ / \
-- 360-r0,r1 XXXXXXXXXXXXXXXX A B X C D X E F X G H X I J X resync data
-- XXXXXXXXXXXXXXX \_______/ \_______/ \_______/ \_______/ \_______/
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ____ ____ ____ ____ ____ ____ ____
-- 540-resync_clk |____| |____| |____| |____| |____| |____| |
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; ; _______ _______ _______ _______ ____
-- XXXXXXXXXXXXXXXXXXX / \ / \ / \ / \ /
-- 540-r0,r1 XXXXXXXXXXXXXXXXXXXX A B X C D X E F X G H X I resync data
-- XXXXXXXXXXXXXXXXXXX \_______/ \_______/ \_______/ \_______/ \____
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ;____ ____ ____ ____ ____ ____
-- phy_clk |____| |____| |____| |____| |____| |____| |____|
--
-- 0 1 2 3 4 5 6
--
--
-- |<- Aligned Data ->|
-- phy_clk 180-r0,r1 540-r0,r1 sig_mtp_match_en (generated from sig_ac_even)
-- 0 XXXXXXXX XXXXXXXX '1'
-- 1 XXXXXXAB XXXXXXXX '0'
-- 2 XXXXABCD XXXXXXAB '1'
-- 3 XXABCDEF XXXXABCD '0'
-- 4 ABCDEFGH XXABCDEF '1'
-- 5 CDEFGHAB ABCDEFGH '0'
--
-- In DQS-based capture, sweeping resync_clk from 180 degrees to 360
-- does not necessarily result in a failure because the setup/hold
-- requirements are so small. The data comparison needs to fail when
-- the resync_clk is shifted more than 360 degrees. The
-- sig_mtp_match_en signal allows the sequencer to blind itself
-- training pattern matches that occur above 360 degrees.
--
--
--
--
--
-- Asserts sig_mtp_match.
--
-- Data comes in from rdata and is pushed into a two-bit wide shift register.
-- It is a critical assumption that the rdata comes back byte aligned.
--
--
--sig_mtp_match_valid
-- rdata_valid (shift-enable)
-- |
-- |
-- +-----------------------+-----------+------------------+
-- ___ | | |
-- dq(0) >---| \ | Shift Register |
-- dq(1) >---| \ +------+ +------+ +------------------+
-- dq(2) >---| )--->| D(0) |-+->| D(1) |-+->...-+->| D(c_cal_mtp_len - 1) |
-- ... | / +------+ | +------+ | | +------------------+
-- dq(n-1) >---|___/ +-----------++-...-+
-- | || +---+
-- | (==)--------> sig_mtp_match_0t ---->| |-->sig_mtp_match_1t-->sig_mtp_match
-- | || +---+
-- | +-----------++...-+
-- sig_dq_pin_ctr >-+ +------+ | +------+ | | +------------------+
-- | P(0) |-+ | P(1) |-+ ...-+->| P(c_cal_mtp_len - 1) |
-- +------+ +------+ +------------------+
--
--
--
--
signal sig_rdata_current_pin : std_logic_vector(c_cal_mtp_len - 1 downto 0);
-- A fundamental assumption here is that rdata_valid is all
-- ones or all zeros - not both.
signal sig_rdata_valid_1t : std_logic; -- rdata_valid delayed by 1 clock period.
signal sig_rdata_valid_2t : std_logic; -- rdata_valid delayed by 2 clock periods.
begin
rdata_valid_1t_proc : process (clk, rst_n)
begin
if rst_n = '0' then
sig_rdata_valid_1t <= '0';
sig_rdata_valid_2t <= '0';
elsif rising_edge(clk) then
sig_rdata_valid_2t <= sig_rdata_valid_1t;
sig_rdata_valid_1t <= rdata_valid(0);
end if;
end process;
-- MUX data into sig_rdata_current_pin shift register.
rdata_current_pin_proc: process (clk, rst_n)
begin
if rst_n = '0' then
sig_rdata_current_pin <= (others => '0');
elsif rising_edge(clk) then
-- shift old data down the shift register
sig_rdata_current_pin(sig_rdata_current_pin'high - DWIDTH_RATIO downto 0) <=
sig_rdata_current_pin(sig_rdata_current_pin'high downto DWIDTH_RATIO);
-- shift new data into the bottom of the shift register.
for i in 0 to DWIDTH_RATIO - 1 loop
sig_rdata_current_pin(sig_rdata_current_pin'high - DWIDTH_RATIO + 1 + i) <= rdata(i*MEM_IF_DWIDTH + sig_dq_pin_ctr);
end loop;
end if;
end process;
mtp_match_proc : process (clk, rst_n)
begin
if rst_n = '0' then -- * when at least c_max_read_lat clock cycles have passed
sig_mtp_match <= '0';
elsif rising_edge(clk) then
sig_mtp_match <= '0';
if sig_rdata_current_pin = c_cal_mtp then
sig_mtp_match <= '1';
end if;
end if;
end process;
poa_match_proc : process (clk, rst_n)
-- poa_match_Calibration Strategy
--
-- Ascii Waveforms:
--
-- __ __ __ __ __ __ __ __ __
-- clk __| |__| |__| |__| |__| |__| |__| |__| |__| |
--
-- ; ; ; ;
-- _________________
-- rdata_valid ________| |___________________________
--
-- ; ; ; ;
-- _____
-- poa_match_en ______________________________________| |_______________
--
-- ; ; ; ;
-- _____
-- poa_match XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX
--
--
-- Notes:
-- -poa_match is only valid while poa_match_en is asserted.
--
--
--
--
--
--
begin
if rst_n = '0' then
sig_poa_match_en <= '0';
sig_poa_match <= '0';
elsif rising_edge(clk) then
sig_poa_match <= '0';
sig_poa_match_en <= '0';
if sig_rdata_valid_2t = '1' and sig_rdata_valid_1t = '0' then
sig_poa_match_en <= '1';
end if;
if DWIDTH_RATIO = 2 then
if sig_rdata_current_pin(sig_rdata_current_pin'high downto sig_rdata_current_pin'length - 6) = "111100" then
sig_poa_match <= '1';
end if;
elsif DWIDTH_RATIO = 4 then
if sig_rdata_current_pin(sig_rdata_current_pin'high downto sig_rdata_current_pin'length - 8) = "11111100" then
sig_poa_match <= '1';
end if;
else
report dgrb_report_prefix & "unsupported DWIDTH_RATIO" severity failure;
end if;
end if;
end process;
end block;
-- ------------------------------------------------------------------
-- Postamble calibration
--
-- Implements the postamble slave state machine and collates the
-- processing data from the test pattern match block.
-- ------------------------------------------------------------------
poa_block : block
-- Postamble Calibration Strategy
--
-- Ascii Waveforms:
--
-- c_read_burst_t c_read_burst_t
-- ;<------->; ;<------->;
-- ; ; ; ;
-- __ / / __
-- mem_dq[0] ___________| |_____\ \________| |___
--
-- ; ; ; ;
-- ; ; ; ;
-- _________ / / _________
-- poa_enable ______| |___\ \_| |___
-- ; ; ; ;
-- ; ; ; ;
-- __ / / ______
-- rdata[0] ___________| |______\ \_______|
-- ; ; ; ;
-- ; ; ; ;
-- ; ; ; ;
-- _ / / _
-- poa_match_en _____________| |___\ \___________| |_
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- / / _
-- poa_match ___________________\ \___________| |_
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- _ / /
-- seq_poa_lat_dec _______________| |_\ \_______________
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- / /
-- seq_poa_lat_inc ___________________\ \_______________
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
--
-- (1) (2)
--
--
-- (1) poa_enable signal is late, and the zeros on mem_dq after (1)
-- are captured.
-- (2) poa_enable signal is aligned. Zeros following (2) are not
-- captured rdata remains at '1'.
--
-- The DQS capture circuit wth the dqs enable asynchronous set.
--
--
--
-- dqs_en_async_preset ----------+
-- |
-- v
-- +---------+
-- +--|Q SET D|----------- gnd
-- | | <O---+
-- | +---------+ |
-- | |
-- | |
-- +--+---. |
-- |AND )--------+------- dqs_bus
-- delayed_dqs -----+---^
--
--
--
-- _____ _____ _____ _____
-- dqs ____| |_____| |_____| |_____| |_____XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
-- ; ; ; ; ;
-- ; ; ; ;
-- _____ _____ _____ _____
-- delayed_dqs _______| |_____| |_____| |_____| |_____XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
--
-- ; ; ; ; ;
-- ; ______________________________________________________________
-- dqs_en_async_ _____________________________| |_____
-- preset
-- ; ; ; ; ;
-- ; ; ; ; ;
-- _____ _____ _____
-- dqs_bus _______| |_________________| |_____| |_____XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
--
-- ; ;
-- (1) (2)
--
--
-- Notes:
-- (1) The dqs_bus pulse here comes because the last value of Q
-- is '1' until the first DQS pulse clocks gnd into the FF,
-- brings low the AND gate, and disables dqs_bus. A training
-- pattern could potentially match at this point even though
-- between (1) and (2) there are no dqs_bus triggers. Data
-- is frozen on rdata while awaiting the dqs_bus pulses at
-- (2). For this reason, wait until the first match of the
-- training pattern, and continue reducing latency until it
-- TP no longer matches, then increase latency by one. In
-- this case, dqs_en_async_preset will have its latency
-- reduced by three until the training pattern is not matched,
-- then latency is increased by one.
--
--
--
--
-- Postamble calibration state
type t_poa_state is (
-- decrease poa enable latency by 1 cycle iteratively until 'correct' position found
s_poa_rewind_to_pass,
-- poa cal complete
s_poa_done
);
constant c_poa_lat_cmd_wait : natural := 10; -- Number of clock cycles to wait for lat_inc/lat_dec signal to take effect.
constant c_poa_max_lat : natural := 100; -- Maximum number of allowable latency changes.
signal sig_poa_adjust_count : integer range 0 to 2**8 - 1;
signal sig_poa_state : t_poa_state;
begin
poa_proc : process (clk, rst_n)
begin
if rst_n = '0' then
sig_poa_ack <= '0';
seq_poa_lat_dec_1x <= (others => '0');
seq_poa_lat_inc_1x <= (others => '0');
sig_poa_adjust_count <= 0;
sig_poa_state <= s_poa_rewind_to_pass;
elsif rising_edge(clk) then
sig_poa_ack <= '0';
seq_poa_lat_inc_1x <= (others => '0');
seq_poa_lat_dec_1x <= (others => '0');
if sig_dgrb_state = s_poa_cal then
case sig_poa_state is
when s_poa_rewind_to_pass =>
-- In postamble calibration
--
-- Normally, must wait for sig_dimm_driving_dq to be '1'
-- before reading, but by this point in calibration
-- rdata_valid is assumed to be set up properly. The
-- sig_poa_match_en (derived from rdata_valid) is used
-- here rather than sig_dimm_driving_dq.
if sig_poa_match_en = '1' then
if sig_poa_match = '1' then
sig_poa_state <= s_poa_done;
else
seq_poa_lat_dec_1x <= (others => '1');
end if;
sig_poa_adjust_count <= sig_poa_adjust_count + 1;
end if;
when s_poa_done =>
sig_poa_ack <= '1';
end case;
else
sig_poa_state <= s_poa_rewind_to_pass;
sig_poa_adjust_count <= 0;
end if;
assert sig_poa_adjust_count <= c_poa_max_lat
report dgrb_report_prefix & "Maximum number of postamble latency adjustments exceeded."
severity failure;
end if;
end process;
end block;
-- ------------------------------------------------------------------
-- code block for tracking signal generation
--
-- this is used for initial tracking setup (finding a reference window)
-- and periodic tracking operations (PVT compensation on rsc phase)
--
-- A slave trk state machine is described and implemented within the block
-- The mimic path is controlled within this block
-- ------------------------------------------------------------------
trk_block : block
type t_tracking_state is (
-- initialise variables out of reset
s_trk_init,
-- idle state
s_trk_idle,
-- sample data from the mimic path (build window)
s_trk_mimic_sample,
-- 'shift' mimic path phase
s_trk_next_phase,
-- calculate mimic window
s_trk_cdvw_calc,
s_trk_cdvw_wait, -- for results
-- calculate how much mimic window has moved (only entered in periodic tracking)
s_trk_cdvw_drift,
-- track rsc phase (only entered in periodic tracking)
s_trk_adjust_resync,
-- communicate command complete to the master state machine
s_trk_complete
);
signal sig_mmc_seq_done : std_logic;
signal sig_mmc_seq_done_1t : std_logic;
signal mmc_seq_value_r : std_logic;
signal sig_mmc_start : std_logic;
signal sig_trk_state : t_tracking_state;
signal sig_trk_last_state : t_tracking_state;
signal sig_rsc_drift : integer range -c_max_rsc_drift_in_phases to c_max_rsc_drift_in_phases; -- stores total change in rsc phase from first calibration
signal sig_req_rsc_shift : integer range -c_max_rsc_drift_in_phases to c_max_rsc_drift_in_phases; -- stores required shift in rsc phase instantaneously
signal sig_mimic_cdv_found : std_logic;
signal sig_mimic_cdv : integer range 0 to PLL_STEPS_PER_CYCLE; -- centre of data valid window calculated from first mimic-cycle
signal sig_mimic_delta : integer range -PLL_STEPS_PER_CYCLE to PLL_STEPS_PER_CYCLE;
signal sig_large_drift_seen : std_logic;
signal sig_remaining_samples : natural range 0 to 2**8 - 1;
begin
-- advertise the codvw phase shift
process (clk, rst_n)
variable v_length : integer;
begin
if rst_n = '0' then
codvw_trk_shift <= (others => '0');
elsif rising_edge(clk) then
if sig_mimic_cdv_found = '1' then
-- check range
v_length := codvw_trk_shift'length;
codvw_trk_shift <= std_logic_vector(to_signed(sig_rsc_drift, v_length));
else
codvw_trk_shift <= (others => '0');
end if;
end if;
end process;
-- request a mimic sample
mimic_sample_req : process (clk, rst_n)
variable seq_mmc_start_r : std_logic_vector(3 downto 0);
begin
if rst_n = '0' then
seq_mmc_start <= '0';
seq_mmc_start_r := "0000";
elsif rising_edge(clk) then
seq_mmc_start_r(3) := seq_mmc_start_r(2);
seq_mmc_start_r(2) := seq_mmc_start_r(1);
seq_mmc_start_r(1) := seq_mmc_start_r(0);
-- extend sig_mmc_start by one clock cycle
if sig_mmc_start = '1' then
seq_mmc_start <= '1';
seq_mmc_start_r(0) := '1';
elsif ( (seq_mmc_start_r(3) = '1') or (seq_mmc_start_r(2) = '1') or (seq_mmc_start_r(1) = '1') or (seq_mmc_start_r(0) = '1') ) then
seq_mmc_start <= '1';
seq_mmc_start_r(0) := '0';
else
seq_mmc_start <= '0';
end if;
end if;
end process;
-- metastability hardening of async mmc_seq_done signal
mmc_seq_req_sync : process (clk, rst_n)
variable v_mmc_seq_done_1r : std_logic;
variable v_mmc_seq_done_2r : std_logic;
variable v_mmc_seq_done_3r : std_logic;
begin
if rst_n = '0' then
sig_mmc_seq_done <= '0';
sig_mmc_seq_done_1t <= '0';
v_mmc_seq_done_1r := '0';
v_mmc_seq_done_2r := '0';
v_mmc_seq_done_3r := '0';
elsif rising_edge(clk) then
sig_mmc_seq_done_1t <= v_mmc_seq_done_3r;
sig_mmc_seq_done <= v_mmc_seq_done_2r;
mmc_seq_value_r <= mmc_seq_value;
v_mmc_seq_done_3r := v_mmc_seq_done_2r;
v_mmc_seq_done_2r := v_mmc_seq_done_1r;
v_mmc_seq_done_1r := mmc_seq_done;
end if;
end process;
-- collect mimic samples as they arrive
shift_in_mmc_seq_value : process (clk, rst_n)
begin
if rst_n = '0' then
sig_trk_cdvw_shift_in <= '0';
sig_trk_cdvw_phase <= '0';
elsif rising_edge(clk) then
sig_trk_cdvw_shift_in <= '0';
sig_trk_cdvw_phase <= '0';
if sig_mmc_seq_done_1t = '1' and sig_mmc_seq_done = '0' then
sig_trk_cdvw_shift_in <= '1';
sig_trk_cdvw_phase <= mmc_seq_value_r;
end if;
end if;
end process;
-- main tracking state machine
trk_proc : process (clk, rst_n)
begin
if rst_n = '0' then
sig_trk_state <= s_trk_init;
sig_trk_last_state <= s_trk_init;
sig_trk_result <= (others => '0');
sig_trk_err <= '0';
sig_mmc_start <= '0';
sig_trk_pll_select <= (others => '0');
sig_req_rsc_shift <= -c_max_rsc_drift_in_phases;
sig_rsc_drift <= -c_max_rsc_drift_in_phases;
sig_mimic_delta <= -PLL_STEPS_PER_CYCLE;
sig_mimic_cdv_found <= '0';
sig_mimic_cdv <= 0;
sig_large_drift_seen <= '0';
sig_trk_cdvw_calc <= '0';
sig_remaining_samples <= 0;
sig_trk_pll_start_reconfig <= '0';
sig_trk_pll_inc_dec_n <= c_pll_phs_inc;
sig_trk_ack <= '0';
elsif rising_edge(clk) then
sig_trk_pll_select <= pll_measure_clk_index;
sig_trk_pll_start_reconfig <= '0';
sig_trk_pll_inc_dec_n <= c_pll_phs_inc;
sig_large_drift_seen <= '0';
sig_trk_cdvw_calc <= '0';
sig_trk_ack <= '0';
sig_trk_err <= '0';
sig_trk_result <= (others => '0');
sig_mmc_start <= '0';
-- if no cdv found then reset tracking results
if sig_mimic_cdv_found = '0' then
sig_rsc_drift <= 0;
sig_req_rsc_shift <= 0;
sig_mimic_delta <= 0;
end if;
if sig_dgrb_state = s_track then
-- resync state machine
case sig_trk_state is
when s_trk_init =>
sig_trk_state <= s_trk_idle;
sig_mimic_cdv_found <= '0';
sig_rsc_drift <= 0;
sig_req_rsc_shift <= 0;
sig_mimic_delta <= 0;
when s_trk_idle =>
sig_remaining_samples <= PLL_STEPS_PER_CYCLE; -- ensure a 360 degrees sweep
sig_trk_state <= s_trk_mimic_sample;
when s_trk_mimic_sample =>
if sig_remaining_samples = 0 then
sig_trk_state <= s_trk_cdvw_calc;
else
if sig_trk_state /= sig_trk_last_state then
-- request a sample as soon as we arrive in this state.
-- the default value of sig_mmc_start is zero!
sig_mmc_start <= '1';
end if;
if sig_mmc_seq_done_1t = '1' and sig_mmc_seq_done = '0' then
-- a sample has been collected, go to next PLL phase
sig_remaining_samples <= sig_remaining_samples - 1;
sig_trk_state <= s_trk_next_phase;
end if;
end if;
when s_trk_next_phase =>
sig_trk_pll_start_reconfig <= '1';
sig_trk_pll_inc_dec_n <= c_pll_phs_inc;
if sig_phs_shft_start = '1' then
sig_trk_pll_start_reconfig <= '0';
end if;
if sig_phs_shft_end = '1' then
sig_trk_state <= s_trk_mimic_sample;
end if;
when s_trk_cdvw_calc =>
if sig_trk_state /= sig_trk_last_state then
-- reset variables we are interested in when we first arrive in this state
sig_trk_cdvw_calc <= '1';
report dgrb_report_prefix & "gathered mimic phase samples DGRB_MIMIC_SAMPLES: " & str(sig_cdvw_state.working_window(sig_cdvw_state.working_window'high downto sig_cdvw_state.working_window'length - PLL_STEPS_PER_CYCLE)) severity note;
else
sig_trk_state <= s_trk_cdvw_wait;
end if;
when s_trk_cdvw_wait =>
if sig_cdvw_state.status /= calculating then
if sig_cdvw_state.status = valid_result then
report dgrb_report_prefix & "mimic window successfully found." severity note;
if sig_mimic_cdv_found = '0' then -- first run of tracking operation
sig_mimic_cdv_found <= '1';
sig_mimic_cdv <= sig_cdvw_state.largest_window_centre;
sig_trk_state <= s_trk_complete;
else -- subsequent tracking operation runs
sig_mimic_delta <= sig_mimic_cdv - sig_cdvw_state.largest_window_centre;
sig_mimic_cdv <= sig_cdvw_state.largest_window_centre;
sig_trk_state <= s_trk_cdvw_drift;
end if;
else
report dgrb_report_prefix & "couldn't find a data-valid window for tracking." severity cal_fail_sev_level;
sig_trk_ack <= '1';
sig_trk_err <= '1';
sig_trk_state <= s_trk_idle;
-- set resync result code
case sig_cdvw_state.status is
when no_invalid_phases =>
sig_trk_result <= std_logic_vector(to_unsigned(C_ERR_RESYNC_NO_INVALID_PHASES, sig_trk_result'length));
when multiple_equal_windows =>
sig_trk_result <= std_logic_vector(to_unsigned(C_ERR_RESYNC_MULTIPLE_EQUAL_WINDOWS, sig_trk_result'length));
when no_valid_phases =>
sig_trk_result <= std_logic_vector(to_unsigned(C_ERR_RESYNC_NO_VALID_PHASES, sig_trk_result'length));
when others =>
sig_trk_result <= std_logic_vector(to_unsigned(C_ERR_CRITICAL, sig_trk_result'length));
end case;
end if;
end if;
when s_trk_cdvw_drift => -- calculate the drift in rsc phase
-- pipeline stage 1
if abs(sig_mimic_delta) > PLL_STEPS_PER_CYCLE/2 then
sig_large_drift_seen <= '1';
else
sig_large_drift_seen <= '0';
end if;
--pipeline stage 2
if sig_trk_state = sig_trk_last_state then
if sig_large_drift_seen = '1' then
if sig_mimic_delta < 0 then -- anti-clockwise movement
sig_req_rsc_shift <= sig_req_rsc_shift + sig_mimic_delta + PLL_STEPS_PER_CYCLE;
else -- clockwise movement
sig_req_rsc_shift <= sig_req_rsc_shift + sig_mimic_delta - PLL_STEPS_PER_CYCLE;
end if;
else
sig_req_rsc_shift <= sig_req_rsc_shift + sig_mimic_delta;
end if;
sig_trk_state <= s_trk_adjust_resync;
end if;
when s_trk_adjust_resync =>
sig_trk_pll_select <= pll_resync_clk_index;
sig_trk_pll_start_reconfig <= '1';
if sig_trk_state /= sig_trk_last_state then
if sig_req_rsc_shift < 0 then
sig_trk_pll_inc_dec_n <= c_pll_phs_inc;
sig_req_rsc_shift <= sig_req_rsc_shift + 1;
sig_rsc_drift <= sig_rsc_drift + 1;
elsif sig_req_rsc_shift > 0 then
sig_trk_pll_inc_dec_n <= c_pll_phs_dec;
sig_req_rsc_shift <= sig_req_rsc_shift - 1;
sig_rsc_drift <= sig_rsc_drift - 1;
else
sig_trk_state <= s_trk_complete;
sig_trk_pll_start_reconfig <= '0';
end if;
else
sig_trk_pll_inc_dec_n <= sig_trk_pll_inc_dec_n; -- maintain current value
end if;
if abs(sig_rsc_drift) = c_max_rsc_drift_in_phases then
report dgrb_report_prefix & " a maximum absolute change in resync_clk of " & integer'image(sig_rsc_drift) & " phases has " & LF &
" occurred (since read resynch phase calibration) during tracking" severity cal_fail_sev_level;
sig_trk_err <= '1';
sig_trk_result <= std_logic_vector(to_unsigned(C_ERR_MAX_TRK_SHFT_EXCEEDED, sig_trk_result'length));
end if;
if sig_phs_shft_start = '1' then
sig_trk_pll_start_reconfig <= '0';
end if;
if sig_phs_shft_end = '1' then
sig_trk_state <= s_trk_complete;
end if;
when s_trk_complete =>
sig_trk_ack <= '1';
end case;
sig_trk_last_state <= sig_trk_state;
else
sig_trk_state <= s_trk_idle;
sig_trk_last_state <= s_trk_idle;
end if;
end if;
end process;
rsc_drift: process (sig_rsc_drift)
begin
sig_trk_rsc_drift <= sig_rsc_drift; -- communicate tracking shift to rsc process
end process;
end block; -- tracking signals
-- ------------------------------------------------------------------
-- write-datapath (WDP) ` and on-chip-termination (OCT) signal
-- ------------------------------------------------------------------
wdp_oct : process(clk,rst_n)
begin
if rst_n = '0' then
seq_oct_value <= c_set_oct_to_rs;
dgrb_wdp_ovride <= '0';
elsif rising_edge(clk) then
if ((sig_dgrb_state = s_idle) or (EN_OCT = 0)) then
seq_oct_value <= c_set_oct_to_rs;
dgrb_wdp_ovride <= '0';
else
seq_oct_value <= c_set_oct_to_rt;
dgrb_wdp_ovride <= '1';
end if;
end if;
end process;
-- ------------------------------------------------------------------
-- handles muxing of error codes to the control block
-- ------------------------------------------------------------------
ac_handshake_proc : process(rst_n, clk)
begin
if rst_n = '0' then
dgrb_ctrl <= defaults;
elsif rising_edge(clk) then
dgrb_ctrl <= defaults;
if sig_dgrb_state = s_wait_admin and sig_dgrb_last_state = s_idle then
dgrb_ctrl.command_ack <= '1';
end if;
case sig_dgrb_state is
when s_seek_cdvw =>
dgrb_ctrl.command_err <= sig_rsc_err;
dgrb_ctrl.command_result <= sig_rsc_result;
when s_track =>
dgrb_ctrl.command_err <= sig_trk_err;
dgrb_ctrl.command_result <= sig_trk_result;
when others => -- from main state machine
dgrb_ctrl.command_err <= sig_cmd_err;
dgrb_ctrl.command_result <= sig_cmd_result;
end case;
if ctrl_dgrb_r.command = cmd_read_mtp then -- check against command because aligned with command done not command_err
dgrb_ctrl.command_err <= '0';
dgrb_ctrl.command_result <= std_logic_vector(to_unsigned(sig_cdvw_state.largest_window_size,dgrb_ctrl.command_result'length));
end if;
if sig_dgrb_state = s_idle and sig_dgrb_last_state = s_release_admin then
dgrb_ctrl.command_done <= '1';
end if;
end if;
end process;
-- ------------------------------------------------------------------
-- address/command state machine
-- process is commanded to begin reading training patterns.
--
-- implements the address/command slave state machine
-- issues read commands to the memory relative to given calibration
-- stage being implemented
-- burst length is dependent on memory type
-- ------------------------------------------------------------------
ac_block : block
-- override the calibration burst length for DDR3 device support
-- (requires BL8 / on the fly setting in MR in admin block)
function set_read_bl ( memtype: in string ) return natural is
begin
if memtype = "DDR3" then
return 8;
elsif memtype = "DDR" or memtype = "DDR2" then
return c_cal_burst_len;
else
report dgrb_report_prefix & " a calibration burst length choice has not been set for memory type " & memtype severity failure;
end if;
return 0;
end function;
-- parameterisation of the read algorithm by burst length
constant c_poa_addr_width : natural := 6;
constant c_cal_read_burst_len : natural := set_read_bl(MEM_IF_MEMTYPE);
constant c_bursts_per_btp : natural := c_cal_mtp_len / c_cal_read_burst_len;
constant c_read_burst_t : natural := c_cal_read_burst_len / DWIDTH_RATIO;
constant c_max_rdata_valid_lat : natural := 50*(c_cal_read_burst_len / DWIDTH_RATIO); -- maximum latency that rdata_valid can ever have with respect to doing_rd
constant c_rdv_ones_rd_clks : natural := (c_max_rdata_valid_lat + c_read_burst_t) / c_read_burst_t; -- number of cycles to read ones for before a pulse of zeros
-- array of burst training pattern addresses
-- here the MTP is used in this addressing
subtype t_btp_addr is natural range 0 to 2 ** MEM_IF_ADDR_WIDTH - 1;
type t_btp_addr_array is array (0 to c_bursts_per_btp - 1) of t_btp_addr;
-- default values
function defaults return t_btp_addr_array is
variable v_btp_array : t_btp_addr_array;
begin
for i in 0 to c_bursts_per_btp - 1 loop
v_btp_array(i) := 0;
end loop;
return v_btp_array;
end function;
-- load btp array addresses
-- Note: this scales to burst lengths of 2, 4 and 8
-- the settings here are specific to the choice of training pattern and need updating if the pattern changes
function set_btp_addr (mtp_almt : natural ) return t_btp_addr_array is
variable v_addr_array : t_btp_addr_array;
begin
for i in 0 to 8/c_cal_read_burst_len - 1 loop
-- set addresses for xF5 data
v_addr_array((c_bursts_per_btp - 1) - i) := MEM_IF_CAL_BASE_COL + c_cal_ofs_xF5 + i*c_cal_read_burst_len;
-- set addresses for x30 data (based on mtp alignment)
if mtp_almt = 0 then
v_addr_array((c_bursts_per_btp - 1) - (8/c_cal_read_burst_len + i)) := MEM_IF_CAL_BASE_COL + c_cal_ofs_x30_almt_0 + i*c_cal_read_burst_len;
else
v_addr_array((c_bursts_per_btp - 1) - (8/c_cal_read_burst_len + i)) := MEM_IF_CAL_BASE_COL + c_cal_ofs_x30_almt_1 + i*c_cal_read_burst_len;
end if;
end loop;
return v_addr_array;
end function;
function find_poa_cycle_period return natural is
-- Returns the period over which the postamble reads
-- repeat in c_read_burst_t units.
variable v_num_bursts : natural;
begin
v_num_bursts := 2 ** c_poa_addr_width / c_read_burst_t;
if v_num_bursts * c_read_burst_t < 2**c_poa_addr_width then
v_num_bursts := v_num_bursts + 1;
end if;
v_num_bursts := v_num_bursts + c_bursts_per_btp + 1;
return v_num_bursts;
end function;
function get_poa_burst_addr(burst_count : in natural; mtp_almt : in natural) return t_btp_addr is
variable v_addr : t_btp_addr;
begin
if burst_count = 0 then
if mtp_almt = 0 then
v_addr := c_cal_ofs_x30_almt_1;
elsif mtp_almt = 1 then
v_addr := c_cal_ofs_x30_almt_0;
else
report "Unsupported mtp_almt " & natural'image(mtp_almt) severity failure;
end if;
-- address gets incremented by four if in burst-length four.
v_addr := v_addr + (8 - c_cal_read_burst_len);
else
v_addr := c_cal_ofs_zeros;
end if;
return v_addr;
end function;
signal btp_addr_array : t_btp_addr_array; -- burst training pattern addresses
signal sig_addr_cmd_state : t_ac_state;
signal sig_addr_cmd_last_state : t_ac_state;
signal sig_doing_rd_count : integer range 0 to c_read_burst_t - 1;
signal sig_count : integer range 0 to 2**8 - 1;
signal sig_setup : integer range c_max_read_lat downto 0;
signal sig_burst_count : integer range 0 to c_read_burst_t;
begin
-- handles counts for when to begin burst-reads (sig_burst_count)
-- sets sig_dimm_driving_dq
-- sets dgrb_ac_access_req
dimm_driving_dq_proc : process(rst_n, clk)
begin
if rst_n = '0' then
sig_dimm_driving_dq <= '1';
sig_setup <= c_max_read_lat;
sig_burst_count <= 0;
dgrb_ac_access_req <= '0';
sig_ac_even <= '0';
elsif rising_edge(clk) then
sig_dimm_driving_dq <= '0';
if sig_addr_cmd_state /= s_ac_idle and sig_addr_cmd_state /= s_ac_relax then
dgrb_ac_access_req <= '1';
else
dgrb_ac_access_req <= '0';
end if;
case sig_addr_cmd_state is
when s_ac_read_mtp | s_ac_read_rdv | s_ac_read_wd_lat | s_ac_read_poa_mtp =>
sig_ac_even <= not sig_ac_even;
-- a counter that keeps track of when we are ready
-- to issue a burst read. Issue burst read eigvery
-- time we are at zero.
if sig_burst_count = 0 then
sig_burst_count <= c_read_burst_t - 1;
else
sig_burst_count <= sig_burst_count - 1;
end if;
if dgrb_ac_access_gnt /= '1' then
sig_setup <= c_max_read_lat;
else
-- primes reads
-- signal that dimms are driving dq pins after
-- at least c_max_read_lat clock cycles have passed.
--
if sig_setup = 0 then
sig_dimm_driving_dq <= '1';
elsif dgrb_ac_access_gnt = '1' then
sig_setup <= sig_setup - 1;
end if;
end if;
when s_ac_relax =>
sig_dimm_driving_dq <= '1';
sig_burst_count <= 0;
sig_ac_even <= '0';
when others =>
sig_burst_count <= 0;
sig_ac_even <= '0';
end case;
end if;
end process;
ac_proc : process(rst_n, clk)
begin
if rst_n = '0' then
sig_count <= 0;
sig_addr_cmd_state <= s_ac_idle;
sig_addr_cmd_last_state <= s_ac_idle;
sig_doing_rd_count <= 0;
sig_addr_cmd <= reset(c_seq_addr_cmd_config);
btp_addr_array <= defaults;
sig_doing_rd <= (others => '0');
elsif rising_edge(clk) then
assert c_cal_mtp_len mod c_cal_read_burst_len = 0 report dgrb_report_prefix & "burst-training pattern length must be a multiple of burst-length." severity failure;
assert MEM_IF_CAL_BANK < 2**MEM_IF_BANKADDR_WIDTH report dgrb_report_prefix & "MEM_IF_CAL_BANK out of range." severity failure;
assert MEM_IF_CAL_BASE_COL < 2**MEM_IF_ADDR_WIDTH - 1 - C_CAL_DATA_LEN report dgrb_report_prefix & "MEM_IF_CAL_BASE_COL out of range." severity failure;
sig_addr_cmd <= deselect(c_seq_addr_cmd_config, sig_addr_cmd);
if sig_ac_req /= sig_addr_cmd_state and sig_addr_cmd_state /= s_ac_idle then
-- and dgrb_ac_access_gnt = '1'
sig_addr_cmd_state <= s_ac_relax;
else
sig_addr_cmd_state <= sig_ac_req;
end if;
if sig_doing_rd_count /= 0 then
sig_doing_rd <= (others => '1');
sig_doing_rd_count <= sig_doing_rd_count - 1;
else
sig_doing_rd <= (others => '0');
end if;
case sig_addr_cmd_state is
when s_ac_idle =>
sig_addr_cmd <= defaults(c_seq_addr_cmd_config);
when s_ac_relax =>
-- waits at least c_max_read_lat before returning to s_ac_idle state
if sig_addr_cmd_state /= sig_addr_cmd_last_state then
sig_count <= c_max_read_lat;
else
if sig_count = 0 then
sig_addr_cmd_state <= s_ac_idle;
else
sig_count <= sig_count - 1;
end if;
end if;
when s_ac_read_mtp =>
-- reads 'more'-training pattern
-- issue read commands for proper addresses
-- set burst training pattern (mtp in this case) addresses
btp_addr_array <= set_btp_addr(current_mtp_almt);
if sig_addr_cmd_state /= sig_addr_cmd_last_state then
sig_count <= c_bursts_per_btp - 1; -- counts number of bursts in a training pattern
else
sig_doing_rd <= (others => '1');
-- issue a read command every c_read_burst_t clock cycles
if sig_burst_count = 0 then
-- decide which read command to issue
for i in 0 to c_bursts_per_btp - 1 loop
if sig_count = i then
sig_addr_cmd <= read(c_seq_addr_cmd_config, -- configuration
sig_addr_cmd, -- previous value
MEM_IF_CAL_BANK, -- bank
btp_addr_array(i), -- column address
2**current_cs, -- rank
c_cal_read_burst_len, -- burst length
false);
end if;
end loop;
-- Set next value of count
if sig_count = 0 then
sig_count <= c_bursts_per_btp - 1;
else
sig_count <= sig_count - 1;
end if;
end if;
end if;
when s_ac_read_poa_mtp =>
-- Postamble rdata/rdata_valid Activity:
--
--
-- (0) (1) (2)
-- ; ; ; ;
-- _________ __ ____________ _____________ _______ _________
-- \ / \ / \ \ \ / \ /
-- (a) rdata[0] 00000000 X 11 X 0000000000 / / 0000000000 X MTP X 00000000
-- _________/ \__/ \____________\ \____________/ \_______/ \_________
-- ; ; ; ;
-- ; ; ; ;
-- _________ / / _________
-- rdata_valid ____| |_____________\ \_____________| |__________
--
-- ;<- (b) ->;<------------(c)------------>; ;
-- ; ; ; ;
--
--
-- This block must issue reads and drive doing_rd to place the above pattern on
-- the rdata and rdata_valid ports. MTP will most likely come back corrupted but
-- the postamble block (poa_block) will make the necessary adjustments to improve
-- matters.
--
-- (a) Read zeros followed by two ones. The two will be at the end of a burst.
-- Assert rdata_valid only during the burst containing the ones.
-- (b) c_read_burst_t clock cycles.
-- (c) Must be greater than but NOT equal to maximum postamble latency clock
-- cycles. Another way: c_min = (max_poa_lat + 1) phy clock cycles. This
-- must also be long enough to allow the postamble block to respond to a
-- the seq_poa_lat_dec_1x signal, but this requirement is less stringent
-- than the first so that we can ignore it.
--
-- The find_poa_cycle_period function should return (b+c)/c_read_burst_t
-- rounded up to the next largest integer.
--
--
-- set burst training pattern (mtp in this case) addresses
btp_addr_array <= set_btp_addr(current_mtp_almt);
-- issue read commands for proper addresses
if sig_addr_cmd_state /= sig_addr_cmd_last_state then
sig_count <= find_poa_cycle_period - 1; -- length of read patter in bursts.
elsif dgrb_ac_access_gnt = '1' then
-- only begin operation once dgrb_ac_access_gnt has been issued
-- otherwise rdata_valid may be asserted when rdasta is not
-- valid.
--
-- *** WARNING: BE SAFE. DON'T LET THIS HAPPEN TO YOU: ***
--
-- ; ; ; ; ; ;
-- ; _______ ; ; _______ ; ; _______
-- XXXXX / \ XXXXXXXXX / \ XXXXXXXXX / \ XXXXXXXXX
-- addr/cmd XXXXXX READ XXXXXXXXXXX READ XXXXXXXXXXX READ XXXXXXXXXXX
-- XXXXX \_______/ XXXXXXXXX \_______/ XXXXXXXXX \_______/ XXXXXXXXX
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; ; ; ; ; ; _______
-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX / \
-- rdata XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX MTP X
-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX \_______/
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- _________ _________ _________
-- doing_rd ____| |_________| |_________| |__________
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- __________________________________________________
-- ac_accesss_gnt ______________|
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- _________ _________
-- rdata_valid __________________________________| |_________| |
-- ; ; ; ; ; ;
--
-- (0) (1) (2)
--
--
-- Cmmand and doing_rd issued at (0). The doing_rd signal enters the
-- rdata_valid pipe here so that it will return on rdata_valid with the
-- expected latency (at this point in calibration, rdata_valid and adv_rd_lat
-- should be properly calibrated). Unlike doing_rd, since ac_access_gnt is not
-- asserted the READ command at (0) is never actually issued. This results
-- in the situation at (2) where rdata is undefined yet rdata_valid indicates
-- valid data. The moral of this story is to wait for ac_access_gnt = '1'
-- before issuing commands when it is important that rdata_valid be accurate.
--
--
--
--
if sig_burst_count = 0 then
sig_addr_cmd <= read(c_seq_addr_cmd_config, -- configuration
sig_addr_cmd, -- previous value
MEM_IF_CAL_BANK, -- bank
get_poa_burst_addr(sig_count, current_mtp_almt),-- column address
2**current_cs, -- rank
c_cal_read_burst_len, -- burst length
false);
-- Set doing_rd
if sig_count = 0 then
sig_doing_rd <= (others => '1');
sig_doing_rd_count <= c_read_burst_t - 1; -- Extend doing_rd pulse by this many phy_clk cycles.
end if;
-- Set next value of count
if sig_count = 0 then
sig_count <= find_poa_cycle_period - 1; -- read for one period then relax (no read) for same time period
else
sig_count <= sig_count - 1;
end if;
end if;
end if;
when s_ac_read_rdv =>
assert c_max_rdata_valid_lat mod c_read_burst_t = 0 report dgrb_report_prefix & "c_max_rdata_valid_lat must be a multiple of c_read_burst_t." severity failure;
if sig_addr_cmd_state /= sig_addr_cmd_last_state then
sig_count <= c_rdv_ones_rd_clks - 1;
else
if sig_burst_count = 0 then
if sig_count = 0 then
-- expecting to read ZEROS
sig_addr_cmd <= read(c_seq_addr_cmd_config, -- configuration
sig_addr_cmd, -- previous valid
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + C_CAL_OFS_ZEROS, -- column
2**current_cs, -- rank
c_cal_read_burst_len, -- burst length
false);
else
-- expecting to read ONES
sig_addr_cmd <= read(c_seq_addr_cmd_config, -- configuration
sig_addr_cmd, -- previous value
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + C_CAL_OFS_ONES, -- column address
2**current_cs, -- rank
c_cal_read_burst_len, -- op length
false);
end if;
if sig_count = 0 then
sig_count <= c_rdv_ones_rd_clks - 1;
else
sig_count <= sig_count - 1;
end if;
end if;
if (sig_count = c_rdv_ones_rd_clks - 1 and sig_burst_count = 1) or
(sig_count = 0 and c_read_burst_t = 1) then
-- the last burst read- that was issued was supposed to read only zeros
-- a burst read command will be issued on the next clock cycle
--
-- A long (>= maximim rdata_valid latency) series of burst reads are
-- issued for ONES.
-- Into this stream a single burst read for ZEROs is issued. After
-- the ZERO read command is issued, rdata_valid needs to come back
-- high one clock cycle before the next read command (reading ONES
-- again) is issued. Since the rdata_valid is just a delayed
-- version of doing_rd, doing_rd needs to exhibit the same behaviour.
--
-- for FR (burst length 4): require that doing_rd high 1 clock cycle after cs_n is low
-- ____ ____ ____ ____ ____ ____ ____ ____ ____
-- clk ____| |____| |____| |____| |____| |____| |____| |____| |____|
--
-- ___ _______ _______ _______ _______
-- \ XXXXXXXXX / \ XXXXXXXXX / \ XXXXXXXXX / \ XXXXXXXXX / \ XXXX
-- addr XXXXXXXXXXX ONES XXXXXXXXXXX ONES XXXXXXXXXXX ZEROS XXXXXXXXXXX ONES XXXXX--> Repeat
-- ___/ XXXXXXXXX \_______/ XXXXXXXXX \_______/ XXXXXXXXX \_______/ XXXXXXXXX \_______/ XXXX
--
-- _________ _________ _________ _________ ____
-- cs_n ____| |_________| |_________| |_________| |_________|
--
-- _________
-- doing_rd ________________________________________________________________| |______________
--
--
-- for HR: require that doing_rd high in the same clock cycle as cs_n is low
--
sig_doing_rd(MEM_IF_DQS_WIDTH*(DWIDTH_RATIO/2-1)) <= '1';
end if;
end if;
when s_ac_read_wd_lat =>
-- continuously issues reads on the memory locations
-- containing write latency addr=[2*c_cal_burst_len - (3*c_cal_burst_len - 1)]
if sig_addr_cmd_state /= sig_addr_cmd_last_state then
-- no initialization required here. Must still wait
-- a clock cycle before beginning operations so that
-- we are properly synchronized with
-- dimm_driving_dq_proc.
else
if sig_burst_count = 0 then
if sig_dimm_driving_dq = '1' then
sig_doing_rd <= (others => '1');
end if;
sig_addr_cmd <= read(c_seq_addr_cmd_config, -- configuration
sig_addr_cmd, -- previous value
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_wd_lat, -- column
2**current_cs, -- rank
c_cal_read_burst_len,
false);
end if;
end if;
when others =>
report dgrb_report_prefix & "undefined state in addr_cmd_proc" severity error;
sig_addr_cmd_state <= s_ac_idle;
end case;
-- mask odt signal
for i in 0 to (DWIDTH_RATIO/2)-1 loop
sig_addr_cmd(i).odt <= odt_settings(current_cs).read;
end loop;
sig_addr_cmd_last_state <= sig_addr_cmd_state;
end if;
end process;
end block ac_block;
end architecture struct;
--
-- -----------------------------------------------------------------------------
-- Abstract : data gatherer (write bias) [dgwb] block for the non-levelling
-- AFI PHY sequencer
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.memphy_alt_mem_phy_record_pkg.all;
-- The address and command package (alt_mem_phy_addr_cmd_pkg) is used to combine DRAM address
-- and command signals in one record and unify the functions operating on this record.
--
use work.memphy_alt_mem_phy_addr_cmd_pkg.all;
--
entity memphy_alt_mem_phy_dgwb is
generic (
-- Physical IF width definitions
MEM_IF_DQS_WIDTH : natural;
MEM_IF_DQ_PER_DQS : natural;
MEM_IF_DWIDTH : natural;
MEM_IF_DM_WIDTH : natural;
DWIDTH_RATIO : natural;
MEM_IF_ADDR_WIDTH : natural;
MEM_IF_BANKADDR_WIDTH : natural;
MEM_IF_NUM_RANKS : natural; -- The sequencer outputs memory control signals of width num_ranks
MEM_IF_MEMTYPE : string;
ADV_LAT_WIDTH : natural;
MEM_IF_CAL_BANK : natural; -- Bank to which calibration data is written
-- Base column address to which calibration data is written.
-- Memory at MEM_IF_CAL_BASE_COL - MEM_IF_CAL_BASE_COL + C_CAL_DATA_LEN - 1
-- is assumed to contain the proper data.
MEM_IF_CAL_BASE_COL : natural
);
port (
-- CLK Reset
clk : in std_logic;
rst_n : in std_logic;
parameterisation_rec : in t_algm_paramaterisation;
-- Control interface :
dgwb_ctrl : out t_ctrl_stat;
ctrl_dgwb : in t_ctrl_command;
-- iRAM 'push' interface :
dgwb_iram : out t_iram_push;
iram_push_done : in std_logic;
-- Admin block req/gnt interface.
dgwb_ac_access_req : out std_logic;
dgwb_ac_access_gnt : in std_logic;
-- WDP interface
dgwb_dqs_burst : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_DQS_WIDTH - 1 downto 0);
dgwb_wdata_valid : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_DQS_WIDTH - 1 downto 0);
dgwb_wdata : out std_logic_vector( DWIDTH_RATIO * MEM_IF_DWIDTH - 1 downto 0);
dgwb_dm : out std_logic_vector( DWIDTH_RATIO * MEM_IF_DM_WIDTH - 1 downto 0);
dgwb_dqs : out std_logic_vector( DWIDTH_RATIO - 1 downto 0);
dgwb_wdp_ovride : out std_logic;
-- addr/cmd output for write commands.
dgwb_ac : out t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
bypassed_rdata : in std_logic_vector(MEM_IF_DWIDTH-1 downto 0);
-- odt settings per chip select
odt_settings : in t_odt_array(0 to MEM_IF_NUM_RANKS-1)
);
end entity;
library work;
-- The constant package (alt_mem_phy_constants_pkg) contains global 'constants' which are fixed
-- thoughout the sequencer and will not change (for constants which may change between sequencer
-- instances generics are used)
--
use work.memphy_alt_mem_phy_constants_pkg.all;
--
architecture rtl of memphy_alt_mem_phy_dgwb is
type t_dgwb_state is (
s_idle,
s_wait_admin,
s_write_btp, -- Writes bit-training pattern
s_write_ones, -- Writes ones
s_write_zeros, -- Writes zeros
s_write_mtp, -- Write more training patterns (requires read to check allignment)
s_write_01_pairs, -- Writes 01 pairs
s_write_1100_step,-- Write step function (half zeros, half ones)
s_write_0011_step,-- Write reversed step function (half ones, half zeros)
s_write_wlat, -- Writes the write latency into a memory address.
s_release_admin
);
constant c_seq_addr_cmd_config : t_addr_cmd_config_rec := set_config_rec(MEM_IF_ADDR_WIDTH, MEM_IF_BANKADDR_WIDTH, MEM_IF_NUM_RANKS, DWIDTH_RATIO, MEM_IF_MEMTYPE);
-- a prefix for all report signals to identify phy and sequencer block
--
constant dgwb_report_prefix : string := "memphy_alt_mem_phy_seq (dgwb) : ";
function dqs_pattern return std_logic_vector is
variable dqs : std_logic_vector( DWIDTH_RATIO - 1 downto 0);
begin
if DWIDTH_RATIO = 2 then
dqs := "10";
elsif DWIDTH_RATIO = 4 then
dqs := "1100";
else
report dgwb_report_prefix & "unsupported DWIDTH_RATIO in function dqs_pattern." severity failure;
end if;
return dqs;
end;
signal sig_addr_cmd : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
signal sig_dgwb_state : t_dgwb_state;
signal sig_dgwb_last_state : t_dgwb_state;
signal access_complete : std_logic;
signal generate_wdata : std_logic; -- for s_write_wlat only
-- current chip select being processed
signal current_cs : natural range 0 to MEM_IF_NUM_RANKS-1;
begin
dgwb_ac <= sig_addr_cmd;
-- Set IRAM interface to defaults
dgwb_iram <= defaults;
-- Master state machine. Generates state transitions.
master_dgwb_state_block : if True generate
signal sig_ctrl_dgwb : t_ctrl_command; -- registers ctrl_dgwb input.
begin
-- generate the current_cs signal to track which cs accessed by PHY at any instance
current_cs_proc : process (clk, rst_n)
begin
if rst_n = '0' then
current_cs <= 0;
elsif rising_edge(clk) then
if sig_ctrl_dgwb.command_req = '1' then
current_cs <= sig_ctrl_dgwb.command_op.current_cs;
end if;
end if;
end process;
master_dgwb_state_proc : process(rst_n, clk)
begin
if rst_n = '0' then
sig_dgwb_state <= s_idle;
sig_dgwb_last_state <= s_idle;
sig_ctrl_dgwb <= defaults;
elsif rising_edge(clk) then
case sig_dgwb_state is
when s_idle =>
if sig_ctrl_dgwb.command_req = '1' then
if (curr_active_block(sig_ctrl_dgwb.command) = dgwb) then
sig_dgwb_state <= s_wait_admin;
end if;
end if;
when s_wait_admin =>
case sig_ctrl_dgwb.command is
when cmd_write_btp => sig_dgwb_state <= s_write_btp;
when cmd_write_mtp => sig_dgwb_state <= s_write_mtp;
when cmd_was => sig_dgwb_state <= s_write_wlat;
when others =>
report dgwb_report_prefix & "unknown command" severity error;
end case;
if dgwb_ac_access_gnt /= '1' then
sig_dgwb_state <= s_wait_admin;
end if;
when s_write_btp =>
sig_dgwb_state <= s_write_zeros;
when s_write_zeros =>
if sig_dgwb_state = sig_dgwb_last_state and access_complete = '1' then
sig_dgwb_state <= s_write_ones;
end if;
when s_write_ones =>
if sig_dgwb_state = sig_dgwb_last_state and access_complete = '1' then
sig_dgwb_state <= s_release_admin;
end if;
when s_write_mtp =>
sig_dgwb_state <= s_write_01_pairs;
when s_write_01_pairs =>
if sig_dgwb_state = sig_dgwb_last_state and access_complete = '1' then
sig_dgwb_state <= s_write_1100_step;
end if;
when s_write_1100_step =>
if sig_dgwb_state = sig_dgwb_last_state and access_complete = '1' then
sig_dgwb_state <= s_write_0011_step;
end if;
when s_write_0011_step =>
if sig_dgwb_state = sig_dgwb_last_state and access_complete = '1' then
sig_dgwb_state <= s_release_admin;
end if;
when s_write_wlat =>
if sig_dgwb_state = sig_dgwb_last_state and access_complete = '1' then
sig_dgwb_state <= s_release_admin;
end if;
when s_release_admin =>
if dgwb_ac_access_gnt = '0' then
sig_dgwb_state <= s_idle;
end if;
when others =>
report dgwb_report_prefix & "undefined state in addr_cmd_proc" severity error;
sig_dgwb_state <= s_idle;
end case;
sig_dgwb_last_state <= sig_dgwb_state;
sig_ctrl_dgwb <= ctrl_dgwb;
end if;
end process;
end generate;
-- Generates writes
ac_write_block : if True generate
constant C_BURST_T : natural := C_CAL_BURST_LEN / DWIDTH_RATIO; -- Number of phy-clock cycles per burst
constant C_MAX_WLAT : natural := 2**ADV_LAT_WIDTH-1; -- Maximum latency in clock cycles
constant C_MAX_COUNT : natural := C_MAX_WLAT + C_BURST_T + 4*12 - 1; -- up to 12 consecutive writes at 4 cycle intervals
-- The following function sets the width over which
-- write latency should be repeated on the dq bus
-- the default value is MEM_IF_DQ_PER_DQS
function set_wlat_dq_rep_width return natural is
begin
for i in 1 to MEM_IF_DWIDTH/MEM_IF_DQ_PER_DQS loop
if (i*MEM_IF_DQ_PER_DQS) >= ADV_LAT_WIDTH then
return i*MEM_IF_DQ_PER_DQS;
end if;
end loop;
report dgwb_report_prefix & "the specified maximum write latency cannot be fully represented in the given number of DQ pins" & LF &
"** NOTE: This may cause overflow when setting ctl_wlat signal" severity warning;
return MEM_IF_DQ_PER_DQS;
end function;
constant C_WLAT_DQ_REP_WIDTH : natural := set_wlat_dq_rep_width;
signal sig_count : natural range 0 to 2**8 - 1;
begin
ac_write_proc : process(rst_n, clk)
begin
if rst_n = '0' then
dgwb_wdp_ovride <= '0';
dgwb_dqs <= (others => '0');
dgwb_dm <= (others => '1');
dgwb_wdata <= (others => '0');
dgwb_dqs_burst <= (others => '0');
dgwb_wdata_valid <= (others => '0');
generate_wdata <= '0'; -- for s_write_wlat only
sig_count <= 0;
sig_addr_cmd <= int_pup_reset(c_seq_addr_cmd_config);
access_complete <= '0';
elsif rising_edge(clk) then
dgwb_wdp_ovride <= '0';
dgwb_dqs <= (others => '0');
dgwb_dm <= (others => '1');
dgwb_wdata <= (others => '0');
dgwb_dqs_burst <= (others => '0');
dgwb_wdata_valid <= (others => '0');
sig_addr_cmd <= deselect(c_seq_addr_cmd_config, sig_addr_cmd);
access_complete <= '0';
generate_wdata <= '0'; -- for s_write_wlat only
case sig_dgwb_state is
when s_idle =>
sig_addr_cmd <= defaults(c_seq_addr_cmd_config);
-- require ones in locations:
-- 1. c_cal_ofs_ones (8 locations)
-- 2. 2nd half of location c_cal_ofs_xF5 (4 locations)
when s_write_ones =>
dgwb_wdp_ovride <= '1';
dgwb_dqs <= dqs_pattern;
dgwb_dm <= (others => '0');
dgwb_dqs_burst <= (others => '1');
-- Write ONES to DQ pins
dgwb_wdata <= (others => '1');
dgwb_wdata_valid <= (others => '1');
-- Issue write command
if sig_dgwb_state /= sig_dgwb_last_state then
sig_count <= 0;
else
-- ensure safe intervals for DDRx memory writes (min 4 mem clk cycles between writes for BC4 DDR3)
if sig_count = 0 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_ones, -- address
2**current_cs, -- rank
4, -- burst length (fixed at BC4)
false); -- auto-precharge
elsif sig_count = 4 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_ones + 4, -- address
2**current_cs, -- rank
4, -- burst length (fixed at BC4)
false); -- auto-precharge
elsif sig_count = 8 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_xF5 + 4, -- address
2**current_cs, -- rank
4, -- burst length (fixed at BC4)
false); -- auto-precharge
end if;
sig_count <= sig_count + 1;
end if;
if sig_count = C_MAX_COUNT - 1 then
access_complete <= '1';
end if;
-- require zeros in locations:
-- 1. c_cal_ofs_zeros (8 locations)
-- 2. 1st half of c_cal_ofs_x30_almt_0 (4 locations)
-- 3. 1st half of c_cal_ofs_x30_almt_1 (4 locations)
when s_write_zeros =>
dgwb_wdp_ovride <= '1';
dgwb_dqs <= dqs_pattern;
dgwb_dm <= (others => '0');
dgwb_dqs_burst <= (others => '1');
-- Write ZEROS to DQ pins
dgwb_wdata <= (others => '0');
dgwb_wdata_valid <= (others => '1');
-- Issue write command
if sig_dgwb_state /= sig_dgwb_last_state then
sig_count <= 0;
else
if sig_count = 0 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_zeros, -- address
2**current_cs, -- rank
4, -- burst length (fixed at BC4)
false); -- auto-precharge
elsif sig_count = 4 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_zeros + 4, -- address
2**current_cs, -- rank
4, -- burst length (fixed at BC4)
false); -- auto-precharge
elsif sig_count = 8 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_x30_almt_0, -- address
2**current_cs, -- rank
4, -- burst length (fixed at BC4)
false); -- auto-precharge
elsif sig_count = 12 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_x30_almt_1, -- address
2**current_cs, -- rank
4, -- burst length (fixed at BC4)
false); -- auto-precharge
end if;
sig_count <= sig_count + 1;
end if;
if sig_count = C_MAX_COUNT - 1 then
access_complete <= '1';
end if;
-- require 0101 pattern in locations:
-- 1. 1st half of location c_cal_ofs_xF5 (4 locations)
when s_write_01_pairs =>
dgwb_wdp_ovride <= '1';
dgwb_dqs <= dqs_pattern;
dgwb_dm <= (others => '0');
dgwb_dqs_burst <= (others => '1');
dgwb_wdata_valid <= (others => '1');
-- Issue write command
if sig_dgwb_state /= sig_dgwb_last_state then
sig_count <= 0;
else
if sig_count = 0 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_xF5, -- address
2**current_cs, -- rank
4, -- burst length
false); -- auto-precharge
end if;
sig_count <= sig_count + 1;
end if;
if sig_count = C_MAX_COUNT - 1 then
access_complete <= '1';
end if;
-- Write 01 to pairs of memory addresses
for i in 0 to dgwb_wdata'length / MEM_IF_DWIDTH - 1 loop
if i mod 2 = 0 then
dgwb_wdata((i+1)*MEM_IF_DWIDTH - 1 downto i*MEM_IF_DWIDTH) <= (others => '1');
else
dgwb_wdata((i+1)*MEM_IF_DWIDTH - 1 downto i*MEM_IF_DWIDTH) <= (others => '0');
end if;
end loop;
-- require pattern "0011" (or "1100") in locations:
-- 1. 2nd half of c_cal_ofs_x30_almt_0 (4 locations)
when s_write_0011_step =>
dgwb_wdp_ovride <= '1';
dgwb_dqs <= dqs_pattern;
dgwb_dm <= (others => '0');
dgwb_dqs_burst <= (others => '1');
dgwb_wdata_valid <= (others => '1');
-- Issue write command
if sig_dgwb_state /= sig_dgwb_last_state then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_x30_almt_0 + 4, -- address
2**current_cs, -- rank
4, -- burst length
false); -- auto-precharge
sig_count <= 0;
else
sig_count <= sig_count + 1;
end if;
if sig_count = C_MAX_COUNT - 1 then
access_complete <= '1';
end if;
-- Write 0011 step to column addresses. Note that
-- it cannot be determined which at this point. The
-- strategy is to write both alignments and see which
-- one is correct later on.
-- this calculation has 2 parts:
-- a) sig_count mod C_BURST_T is a timewise iterator of repetition of the pattern
-- b) i represents the temporal iterator of the pattern
-- it is required to sum a and b and switch the pattern between 0 and 1 every 2 locations in each dimension
-- Note: the same formulae is used below for the 1100 pattern
for i in 0 to dgwb_wdata'length / MEM_IF_DWIDTH - 1 loop
if ((sig_count mod C_BURST_T) + (i/2)) mod 2 = 0 then
dgwb_wdata((i+1)*MEM_IF_DWIDTH - 1 downto i*MEM_IF_DWIDTH) <= (others => '0');
else
dgwb_wdata((i+1)*MEM_IF_DWIDTH - 1 downto i*MEM_IF_DWIDTH) <= (others => '1');
end if;
end loop;
-- require pattern "1100" (or "0011") in locations:
-- 1. 2nd half of c_cal_ofs_x30_almt_1 (4 locations)
when s_write_1100_step =>
dgwb_wdp_ovride <= '1';
dgwb_dqs <= dqs_pattern;
dgwb_dm <= (others => '0');
dgwb_dqs_burst <= (others => '1');
dgwb_wdata_valid <= (others => '1');
-- Issue write command
if sig_dgwb_state /= sig_dgwb_last_state then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_x30_almt_1 + 4, -- address
2**current_cs, -- rank
4, -- burst length
false); -- auto-precharge
sig_count <= 0;
else
sig_count <= sig_count + 1;
end if;
if sig_count = C_MAX_COUNT - 1 then
access_complete <= '1';
end if;
-- Write 1100 step to column addresses. Note that
-- it cannot be determined which at this point. The
-- strategy is to write both alignments and see which
-- one is correct later on.
for i in 0 to dgwb_wdata'length / MEM_IF_DWIDTH - 1 loop
if ((sig_count mod C_BURST_T) + (i/2)) mod 2 = 0 then
dgwb_wdata((i+1)*MEM_IF_DWIDTH - 1 downto i*MEM_IF_DWIDTH) <= (others => '1');
else
dgwb_wdata((i+1)*MEM_IF_DWIDTH - 1 downto i*MEM_IF_DWIDTH) <= (others => '0');
end if;
end loop;
when s_write_wlat =>
-- Effect:
-- *Writes the memory latency to an array formed
-- from memory addr=[2*C_CAL_BURST_LEN-(3*C_CAL_BURST_LEN-1)].
-- The write latency is written to pairs of addresses
-- across the given range.
--
-- Example
-- C_CAL_BURST_LEN = 4
-- addr 8 - 9 [WLAT] size = 2*MEM_IF_DWIDTH bits
-- addr 10 - 11 [WLAT] size = 2*MEM_IF_DWIDTH bits
--
dgwb_wdp_ovride <= '1';
dgwb_dqs <= dqs_pattern;
dgwb_dm <= (others => '0');
dgwb_wdata <= (others => '0');
dgwb_dqs_burst <= (others => '1');
dgwb_wdata_valid <= (others => '1');
if sig_dgwb_state /= sig_dgwb_last_state then
sig_addr_cmd <= write(c_seq_addr_cmd_config, -- A/C configuration
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_wd_lat, -- address
2**current_cs, -- rank
8, -- burst length (8 for DDR3 and 4 for DDR/DDR2)
false); -- auto-precharge
sig_count <= 0;
else
-- hold wdata_valid and wdata 2 clock cycles
-- 1 - because ac signal registered at top level of sequencer
-- 2 - because want time to dqs_burst edge which occurs 1 cycle earlier
-- than wdata_valid in an AFI compliant controller
generate_wdata <= '1';
end if;
if generate_wdata = '1' then
for i in 0 to dgwb_wdata'length/C_WLAT_DQ_REP_WIDTH - 1 loop
dgwb_wdata((i+1)*C_WLAT_DQ_REP_WIDTH - 1 downto i*C_WLAT_DQ_REP_WIDTH) <= std_logic_vector(to_unsigned(sig_count, C_WLAT_DQ_REP_WIDTH));
end loop;
-- delay by 1 clock cycle to account for 1 cycle discrepancy
-- between dqs_burst and wdata_valid
if sig_count = C_MAX_COUNT then
access_complete <= '1';
end if;
sig_count <= sig_count + 1;
end if;
when others =>
null;
end case;
-- mask odt signal
for i in 0 to (DWIDTH_RATIO/2)-1 loop
sig_addr_cmd(i).odt <= odt_settings(current_cs).write;
end loop;
end if;
end process;
end generate;
-- Handles handshaking for access to address/command
ac_handshake_proc : process(rst_n, clk)
begin
if rst_n = '0' then
dgwb_ctrl <= defaults;
dgwb_ac_access_req <= '0';
elsif rising_edge(clk) then
dgwb_ctrl <= defaults;
dgwb_ac_access_req <= '0';
if sig_dgwb_state /= s_idle and sig_dgwb_state /= s_release_admin then
dgwb_ac_access_req <= '1';
elsif sig_dgwb_state = s_idle or sig_dgwb_state = s_release_admin then
dgwb_ac_access_req <= '0';
else
report dgwb_report_prefix & "unexpected state in ac_handshake_proc so haven't requested access to address/command." severity warning;
end if;
if sig_dgwb_state = s_wait_admin and sig_dgwb_last_state = s_idle then
dgwb_ctrl.command_ack <= '1';
end if;
if sig_dgwb_state = s_idle and sig_dgwb_last_state = s_release_admin then
dgwb_ctrl.command_done <= '1';
end if;
end if;
end process;
end architecture rtl;
--
-- -----------------------------------------------------------------------------
-- Abstract : ctrl block for the non-levelling AFI PHY sequencer
-- This block is the central control unit for the sequencer. The method
-- of control is to issue commands (prefixed cmd_) to each of the other
-- sequencer blocks to execute. Each command corresponds to a stage of
-- the AFI PHY calibaration stage, and in turn each state represents a
-- command or a supplimentary flow control operation. In addition to
-- controlling the sequencer this block also checks for time out
-- conditions which occur when a different system block is faulty.
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.memphy_alt_mem_phy_record_pkg.all;
-- The iram address package (alt_mem_phy_iram_addr_pkg) is used to define the base addresses used
-- for iram writes during calibration
--
use work.memphy_alt_mem_phy_iram_addr_pkg.all;
--
entity memphy_alt_mem_phy_ctrl is
generic (
FAMILYGROUP_ID : natural;
MEM_IF_DLL_LOCK_COUNT : natural;
MEM_IF_MEMTYPE : string;
DWIDTH_RATIO : natural;
IRAM_ADDRESSING : t_base_hdr_addresses;
MEM_IF_CLK_PS : natural;
TRACKING_INTERVAL_IN_MS : natural;
MEM_IF_NUM_RANKS : natural;
MEM_IF_DQS_WIDTH : natural;
GENERATE_ADDITIONAL_DBG_RTL : natural;
SIM_TIME_REDUCTIONS : natural; -- if 0 null, if 1 skip rrp, if 2 rrp for 1 dqs group and 1 cs
ACK_SEVERITY : severity_level
);
port (
-- clk / reset
clk : in std_logic;
rst_n : in std_logic;
-- calibration status and redo request
ctl_init_success : out std_logic;
ctl_init_fail : out std_logic;
ctl_recalibrate_req : in std_logic; -- acts as a synchronous reset
-- status signals from iram
iram_status : in t_iram_stat;
iram_push_done : in std_logic;
-- standard control signal to all blocks
ctrl_op_rec : out t_ctrl_command;
-- standardised response from all system blocks
admin_ctrl : in t_ctrl_stat;
dgrb_ctrl : in t_ctrl_stat;
dgwb_ctrl : in t_ctrl_stat;
-- mmi to ctrl interface
mmi_ctrl : in t_mmi_ctrl;
ctrl_mmi : out t_ctrl_mmi;
-- byte lane select
ctl_cal_byte_lanes : in std_logic_vector(MEM_IF_NUM_RANKS * MEM_IF_DQS_WIDTH - 1 downto 0);
-- signals to control the ac_nt setting
dgrb_ctrl_ac_nt_good : in std_logic;
int_ac_nt : out std_logic_vector(((DWIDTH_RATIO+2)/4) - 1 downto 0); -- width of 1 for DWIDTH_RATIO =2,4 and 2 for DWIDTH_RATIO = 8
-- the following signals are reserved for future use
ctrl_iram_push : out t_ctrl_iram
);
end entity;
library work;
-- The constant package (alt_mem_phy_constants_pkg) contains global 'constants' which are fixed
-- thoughout the sequencer and will not change (for constants which may change between sequencer
-- instances generics are used)
--
use work.memphy_alt_mem_phy_constants_pkg.all;
--
architecture struct of memphy_alt_mem_phy_ctrl is
-- a prefix for all report signals to identify phy and sequencer block
--
constant ctrl_report_prefix : string := "memphy_alt_mem_phy_seq (ctrl) : ";
-- decoder to find the relevant disable bit (from mmi registers) for a given state
function find_dis_bit
(
state : t_master_sm_state;
mmi_ctrl : t_mmi_ctrl
) return std_logic is
variable v_dis : std_logic;
begin
case state is
when s_phy_initialise => v_dis := mmi_ctrl.hl_css.phy_initialise_dis;
when s_init_dram |
s_prog_cal_mr => v_dis := mmi_ctrl.hl_css.init_dram_dis;
when s_write_ihi => v_dis := mmi_ctrl.hl_css.write_ihi_dis;
when s_cal => v_dis := mmi_ctrl.hl_css.cal_dis;
when s_write_btp => v_dis := mmi_ctrl.hl_css.write_btp_dis;
when s_write_mtp => v_dis := mmi_ctrl.hl_css.write_mtp_dis;
when s_read_mtp => v_dis := mmi_ctrl.hl_css.read_mtp_dis;
when s_rrp_reset => v_dis := mmi_ctrl.hl_css.rrp_reset_dis;
when s_rrp_sweep => v_dis := mmi_ctrl.hl_css.rrp_sweep_dis;
when s_rrp_seek => v_dis := mmi_ctrl.hl_css.rrp_seek_dis;
when s_rdv => v_dis := mmi_ctrl.hl_css.rdv_dis;
when s_poa => v_dis := mmi_ctrl.hl_css.poa_dis;
when s_was => v_dis := mmi_ctrl.hl_css.was_dis;
when s_adv_rd_lat => v_dis := mmi_ctrl.hl_css.adv_rd_lat_dis;
when s_adv_wr_lat => v_dis := mmi_ctrl.hl_css.adv_wr_lat_dis;
when s_prep_customer_mr_setup => v_dis := mmi_ctrl.hl_css.prep_customer_mr_setup_dis;
when s_tracking_setup |
s_tracking => v_dis := mmi_ctrl.hl_css.tracking_dis;
when others => v_dis := '1'; -- default change stage
end case;
return v_dis;
end function;
-- decoder to find the relevant command for a given state
function find_cmd
(
state : t_master_sm_state
) return t_ctrl_cmd_id is
begin
case state is
when s_phy_initialise => return cmd_phy_initialise;
when s_init_dram => return cmd_init_dram;
when s_prog_cal_mr => return cmd_prog_cal_mr;
when s_write_ihi => return cmd_write_ihi;
when s_cal => return cmd_idle;
when s_write_btp => return cmd_write_btp;
when s_write_mtp => return cmd_write_mtp;
when s_read_mtp => return cmd_read_mtp;
when s_rrp_reset => return cmd_rrp_reset;
when s_rrp_sweep => return cmd_rrp_sweep;
when s_rrp_seek => return cmd_rrp_seek;
when s_rdv => return cmd_rdv;
when s_poa => return cmd_poa;
when s_was => return cmd_was;
when s_adv_rd_lat => return cmd_prep_adv_rd_lat;
when s_adv_wr_lat => return cmd_prep_adv_wr_lat;
when s_prep_customer_mr_setup => return cmd_prep_customer_mr_setup;
when s_tracking_setup |
s_tracking => return cmd_tr_due;
when others => return cmd_idle;
end case;
end function;
function mcs_rw_state -- returns true for multiple cs read/write states
(
state : t_master_sm_state
) return boolean is
begin
case state is
when s_write_btp | s_write_mtp | s_rrp_sweep =>
return true;
when s_reset | s_phy_initialise | s_init_dram | s_prog_cal_mr | s_write_ihi | s_cal |
s_read_mtp | s_rrp_reset | s_rrp_seek | s_rdv | s_poa |
s_was | s_adv_rd_lat | s_adv_wr_lat | s_prep_customer_mr_setup |
s_tracking_setup | s_tracking | s_operational | s_non_operational =>
return false;
when others =>
--
return false;
end case;
end function;
-- timing parameters
constant c_done_timeout_count : natural := 32768;
constant c_ack_timeout_count : natural := 1000;
constant c_ticks_per_ms : natural := 1000000000/(MEM_IF_CLK_PS*(DWIDTH_RATIO/2));
constant c_ticks_per_10us : natural := 10000000 /(MEM_IF_CLK_PS*(DWIDTH_RATIO/2));
-- local copy of calibration fail/success signals
signal int_ctl_init_fail : std_logic;
signal int_ctl_init_success : std_logic;
-- state machine (master for sequencer)
signal state : t_master_sm_state;
signal last_state : t_master_sm_state;
-- flow control signals for state machine
signal dis_state : std_logic; -- disable state
signal hold_state : std_logic; -- hold in state for 1 clock cycle
signal master_ctrl_op_rec : t_ctrl_command; -- master command record to all sequencer blocks
signal master_ctrl_iram_push : t_ctrl_iram; -- record indicating control details for pushes
signal dll_lock_counter : natural range MEM_IF_DLL_LOCK_COUNT - 1 downto 0; -- to wait for dll to lock
signal iram_init_complete : std_logic;
-- timeout signals to check if a block has 'hung'
signal timeout_counter : natural range c_done_timeout_count - 1 downto 0;
signal timeout_counter_stop : std_logic;
signal timeout_counter_enable : std_logic;
signal timeout_counter_clear : std_logic;
signal cmd_req_asserted : std_logic; -- a command has been issued
signal flag_ack_timeout : std_logic; -- req -> ack timed out
signal flag_done_timeout : std_logic; -- reg -> done timed out
signal waiting_for_ack : std_logic; -- command issued
signal cmd_ack_seen : std_logic; -- command completed
signal curr_ctrl : t_ctrl_stat; -- response for current active block
signal curr_cmd : t_ctrl_cmd_id;
-- store state information based on issued command
signal int_ctrl_prev_stage : t_ctrl_cmd_id;
signal int_ctrl_current_stage : t_ctrl_cmd_id;
-- multiple chip select counter
signal cs_counter : natural range 0 to MEM_IF_NUM_RANKS - 1;
signal reissue_cmd_req : std_logic; -- reissue command request for multiple cs
signal cal_cs_enabled : std_logic_vector(MEM_IF_NUM_RANKS - 1 downto 0);
-- signals to check the ac_nt setting
signal ac_nt_almts_checked : natural range 0 to DWIDTH_RATIO/2-1;
signal ac_nt : std_logic_vector(((DWIDTH_RATIO+2)/4) - 1 downto 0);
-- track the mtp alignment setting
signal mtp_almts_checked : natural range 0 to 2;
signal mtp_correct_almt : natural range 0 to 1;
signal mtp_no_valid_almt : std_logic;
signal mtp_both_valid_almt : std_logic;
signal mtp_err : std_logic;
-- tracking timing
signal milisecond_tick_gen_count : natural range 0 to c_ticks_per_ms -1 := c_ticks_per_ms -1;
signal tracking_ms_counter : natural range 0 to 255;
signal tracking_update_due : std_logic;
begin -- architecture struct
-------------------------------------------------------------------------------
-- check if chip selects are enabled
-- this only effects reactive stages (i,e, those requiring memory reads)
-------------------------------------------------------------------------------
process(ctl_cal_byte_lanes)
variable v_cs_enabled : std_logic;
begin
for i in 0 to MEM_IF_NUM_RANKS - 1 loop
-- check if any bytes enabled
v_cs_enabled := '0';
for j in 0 to MEM_IF_DQS_WIDTH - 1 loop
v_cs_enabled := v_cs_enabled or ctl_cal_byte_lanes(i*MEM_IF_DQS_WIDTH + j);
end loop;
-- if any byte enabled set cs as enabled else not
cal_cs_enabled(i) <= v_cs_enabled;
-- sanity checking:
if i = 0 and v_cs_enabled = '0' then
report ctrl_report_prefix & " disabling of chip select 0 is unsupported by the sequencer," & LF &
"-> if this is your intention then please remap CS pins such that CS 0 is not disabled" severity failure;
end if;
end loop;
end process;
-- -----------------------------------------------------------------------------
-- dll lock counter
-- -----------------------------------------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
dll_lock_counter <= MEM_IF_DLL_LOCK_COUNT -1;
elsif rising_edge(clk) then
if ctl_recalibrate_req = '1' then
dll_lock_counter <= MEM_IF_DLL_LOCK_COUNT -1;
elsif dll_lock_counter /= 0 then
dll_lock_counter <= dll_lock_counter - 1;
end if;
end if;
end process;
-- -----------------------------------------------------------------------------
-- timeout counter : this counter is used to determine if an ack, or done has
-- not been received within the expected number of clock cycles of a req being
-- asserted.
-- -----------------------------------------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
timeout_counter <= c_done_timeout_count - 1;
elsif rising_edge(clk) then
if timeout_counter_clear = '1' then
timeout_counter <= c_done_timeout_count - 1;
elsif timeout_counter_enable = '1' and state /= s_init_dram then
if timeout_counter /= 0 then
timeout_counter <= timeout_counter - 1;
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------------
-- register current ctrl signal based on current command
-- -----------------------------------------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
curr_ctrl <= defaults;
curr_cmd <= cmd_idle;
elsif rising_edge(clk) then
case curr_active_block(curr_cmd) is
when admin => curr_ctrl <= admin_ctrl;
when dgrb => curr_ctrl <= dgrb_ctrl;
when dgwb => curr_ctrl <= dgwb_ctrl;
when others => curr_ctrl <= defaults;
end case;
curr_cmd <= master_ctrl_op_rec.command;
end if;
end process;
-- -----------------------------------------------------------------------------
-- generation of cmd_ack_seen
-- -----------------------------------------------------------------------------
process (curr_ctrl)
begin
cmd_ack_seen <= curr_ctrl.command_ack;
end process;
-------------------------------------------------------------------------------
-- generation of waiting_for_ack flag (to determine whether ack has timed out)
-------------------------------------------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
waiting_for_ack <= '0';
elsif rising_edge(clk) then
if cmd_req_asserted = '1' then
waiting_for_ack <= '1';
elsif cmd_ack_seen = '1' then
waiting_for_ack <= '0';
end if;
end if;
end process;
-- -----------------------------------------------------------------------------
-- generation of timeout flags
-- -----------------------------------------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
flag_ack_timeout <= '0';
flag_done_timeout <= '0';
elsif rising_edge(clk) then
if mmi_ctrl.calibration_start = '1' or ctl_recalibrate_req = '1' then
flag_ack_timeout <= '0';
elsif timeout_counter = 0 and waiting_for_ack = '1' then
flag_ack_timeout <= '1';
end if;
if mmi_ctrl.calibration_start = '1' or ctl_recalibrate_req = '1' then
flag_done_timeout <= '0';
elsif timeout_counter = 0 and
state /= s_rrp_sweep and -- rrp can take enough cycles to overflow counter so don't timeout
state /= s_init_dram and -- init_dram takes about 200 us, so don't timeout
timeout_counter_clear /= '1' then -- check if currently clearing the timeout (i.e. command_done asserted for s_init_dram or s_rrp_sweep)
flag_done_timeout <= '1';
end if;
end if;
end process;
-- generation of timeout_counter_stop
timeout_counter_stop <= curr_ctrl.command_done;
-- -----------------------------------------------------------------------------
-- generation of timeout_counter_enable and timeout_counter_clear
-- -----------------------------------------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
timeout_counter_enable <= '0';
timeout_counter_clear <= '0';
elsif rising_edge(clk) then
if cmd_req_asserted = '1' then
timeout_counter_enable <= '1';
timeout_counter_clear <= '0';
elsif timeout_counter_stop = '1'
or state = s_operational
or state = s_non_operational
or state = s_reset then
timeout_counter_enable <= '0';
timeout_counter_clear <= '1';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- assignment to ctrl_mmi record
-------------------------------------------------------------------------------
process (clk, rst_n)
variable v_ctrl_mmi : t_ctrl_mmi;
begin
if rst_n = '0' then
v_ctrl_mmi := defaults;
ctrl_mmi <= defaults;
int_ctrl_prev_stage <= cmd_idle;
int_ctrl_current_stage <= cmd_idle;
elsif rising_edge(clk) then
ctrl_mmi <= v_ctrl_mmi;
v_ctrl_mmi.ctrl_calibration_success := '0';
v_ctrl_mmi.ctrl_calibration_fail := '0';
if (curr_ctrl.command_ack = '1') then
case state is
when s_init_dram => v_ctrl_mmi.ctrl_cal_stage_ack_seen.init_dram := '1';
when s_write_btp => v_ctrl_mmi.ctrl_cal_stage_ack_seen.write_btp := '1';
when s_write_mtp => v_ctrl_mmi.ctrl_cal_stage_ack_seen.write_mtp := '1';
when s_read_mtp => v_ctrl_mmi.ctrl_cal_stage_ack_seen.read_mtp := '1';
when s_rrp_reset => v_ctrl_mmi.ctrl_cal_stage_ack_seen.rrp_reset := '1';
when s_rrp_sweep => v_ctrl_mmi.ctrl_cal_stage_ack_seen.rrp_sweep := '1';
when s_rrp_seek => v_ctrl_mmi.ctrl_cal_stage_ack_seen.rrp_seek := '1';
when s_rdv => v_ctrl_mmi.ctrl_cal_stage_ack_seen.rdv := '1';
when s_poa => v_ctrl_mmi.ctrl_cal_stage_ack_seen.poa := '1';
when s_was => v_ctrl_mmi.ctrl_cal_stage_ack_seen.was := '1';
when s_adv_rd_lat => v_ctrl_mmi.ctrl_cal_stage_ack_seen.adv_rd_lat := '1';
when s_adv_wr_lat => v_ctrl_mmi.ctrl_cal_stage_ack_seen.adv_wr_lat := '1';
when s_prep_customer_mr_setup => v_ctrl_mmi.ctrl_cal_stage_ack_seen.prep_customer_mr_setup := '1';
when s_tracking_setup |
s_tracking => v_ctrl_mmi.ctrl_cal_stage_ack_seen.tracking_setup := '1';
when others => null;
end case;
end if;
-- special 'ack' (actually finished) triggers for phy_initialise, writing iram header info and s_cal
if state = s_phy_initialise then
if iram_status.init_done = '1' and dll_lock_counter = 0 then
v_ctrl_mmi.ctrl_cal_stage_ack_seen.phy_initialise := '1';
end if;
end if;
if state = s_write_ihi then
if iram_push_done = '1' then
v_ctrl_mmi.ctrl_cal_stage_ack_seen.write_ihi := '1';
end if;
end if;
if state = s_cal and find_dis_bit(state, mmi_ctrl) = '0' then -- if cal state and calibration not disabled acknowledge
v_ctrl_mmi.ctrl_cal_stage_ack_seen.cal := '1';
end if;
if state = s_operational then
v_ctrl_mmi.ctrl_calibration_success := '1';
end if;
if state = s_non_operational then
v_ctrl_mmi.ctrl_calibration_fail := '1';
end if;
if state /= s_non_operational then
v_ctrl_mmi.ctrl_current_active_block := master_ctrl_iram_push.active_block;
v_ctrl_mmi.ctrl_current_stage := master_ctrl_op_rec.command;
else
v_ctrl_mmi.ctrl_current_active_block := v_ctrl_mmi.ctrl_current_active_block;
v_ctrl_mmi.ctrl_current_stage := v_ctrl_mmi.ctrl_current_stage;
end if;
int_ctrl_prev_stage <= int_ctrl_current_stage;
int_ctrl_current_stage <= v_ctrl_mmi.ctrl_current_stage;
if int_ctrl_prev_stage /= int_ctrl_current_stage then
v_ctrl_mmi.ctrl_current_stage_done := '0';
else
if curr_ctrl.command_done = '1' then
v_ctrl_mmi.ctrl_current_stage_done := '1';
end if;
end if;
v_ctrl_mmi.master_state_r := last_state;
if mmi_ctrl.calibration_start = '1' or ctl_recalibrate_req = '1' then
v_ctrl_mmi := defaults;
ctrl_mmi <= defaults;
end if;
-- assert error codes here
if curr_ctrl.command_err = '1' then
v_ctrl_mmi.ctrl_err_code := curr_ctrl.command_result;
elsif flag_ack_timeout = '1' then
v_ctrl_mmi.ctrl_err_code := std_logic_vector(to_unsigned(c_err_ctrl_ack_timeout, v_ctrl_mmi.ctrl_err_code'length));
elsif flag_done_timeout = '1' then
v_ctrl_mmi.ctrl_err_code := std_logic_vector(to_unsigned(c_err_ctrl_done_timeout, v_ctrl_mmi.ctrl_err_code'length));
elsif mtp_err = '1' then
if mtp_no_valid_almt = '1' then
v_ctrl_mmi.ctrl_err_code := std_logic_vector(to_unsigned(C_ERR_READ_MTP_NO_VALID_ALMT, v_ctrl_mmi.ctrl_err_code'length));
elsif mtp_both_valid_almt = '1' then
v_ctrl_mmi.ctrl_err_code := std_logic_vector(to_unsigned(C_ERR_READ_MTP_BOTH_ALMT_PASS, v_ctrl_mmi.ctrl_err_code'length));
end if;
end if;
end if;
end process;
-- check if iram finished init
process(iram_status)
begin
if GENERATE_ADDITIONAL_DBG_RTL = 0 then
iram_init_complete <= '1';
else
iram_init_complete <= iram_status.init_done;
end if;
end process;
-- -----------------------------------------------------------------------------
-- master state machine
-- (this controls the operation of the entire sequencer)
-- the states are summarised as follows:
-- s_reset
-- s_phy_initialise - wait for dll lock and init done flag from iram
-- s_init_dram, -- dram initialisation - reset sequence
-- s_prog_cal_mr, -- dram initialisation - programming mode registers (once per chip select)
-- s_write_ihi - write header information in iRAM
-- s_cal - check if calibration to be executed
-- s_write_btp - write burst training pattern
-- s_write_mtp - write more training pattern
-- s_rrp_reset - read resync phase setup - reset initial conditions
-- s_rrp_sweep - read resync phase setup - sweep phases per chip select
-- s_read_mtp - read training patterns to find correct alignment for 1100 burst
-- (this is a special case of s_rrp_seek with no resych phase setting)
-- s_rrp_seek - read resync phase setup - seek correct alignment
-- s_rdv - read data valid setup
-- s_poa - calibrate the postamble
-- s_was - write datapath setup (ac to write data timing)
-- s_adv_rd_lat - advertise read latency
-- s_adv_wr_lat - advertise write latency
-- s_tracking_setup - perform tracking (1st pass to setup mimic window)
-- s_prep_customer_mr_setup - apply user mode register settings (in admin block)
-- s_tracking - perform tracking (subsequent passes in user mode)
-- s_operational - calibration successful and in user mode
-- s_non_operational - calibration unsuccessful and in user mode
-- -----------------------------------------------------------------------------
process(clk, rst_n)
variable v_seen_ack : boolean;
variable v_dis : std_logic; -- disable bit
begin
if rst_n = '0' then
state <= s_reset;
last_state <= s_reset;
int_ctl_init_success <= '0';
int_ctl_init_fail <= '0';
v_seen_ack := false;
hold_state <= '0';
cs_counter <= 0;
mtp_almts_checked <= 0;
ac_nt <= (others => '1');
ac_nt_almts_checked <= 0;
reissue_cmd_req <= '0';
dis_state <= '0';
elsif rising_edge(clk) then
last_state <= state;
-- check if state_tx required
if curr_ctrl.command_ack = '1' then
v_seen_ack := true;
end if;
-- find disable bit for current state (do once to avoid exit mid-state)
if state /= last_state then
dis_state <= find_dis_bit(state, mmi_ctrl);
end if;
-- Set special conditions:
if state = s_reset or
state = s_operational or
state = s_non_operational then
dis_state <= '1';
end if;
-- override to ensure execution of next state logic
if (state = s_cal) then
dis_state <= '1';
end if;
-- if header writing in iram check finished
if (state = s_write_ihi) then
if iram_push_done = '1' or mmi_ctrl.hl_css.write_ihi_dis = '1' then
dis_state <= '1';
else
dis_state <= '0';
end if;
end if;
-- Special condition for initialisation
if (state = s_phy_initialise) then
if ((dll_lock_counter = 0) and (iram_init_complete = '1')) or
(mmi_ctrl.hl_css.phy_initialise_dis = '1') then
dis_state <= '1';
else
dis_state <= '0';
end if;
end if;
if dis_state = '1' then
v_seen_ack := false;
elsif curr_ctrl.command_done = '1' then
if v_seen_ack = false then
report ctrl_report_prefix & "have not seen ack but have seen command done from " & t_ctrl_active_block'image(curr_active_block(master_ctrl_op_rec.command)) & "_block in state " & t_master_sm_state'image(state) severity warning;
end if;
v_seen_ack := false;
end if;
-- default do not reissue command request
reissue_cmd_req <= '0';
if (hold_state = '1') then
hold_state <= '0';
else
if ((dis_state = '1') or
(curr_ctrl.command_done = '1') or
((cal_cs_enabled(cs_counter) = '0') and (mcs_rw_state(state) = True))) then -- current chip select is disabled and read/write
hold_state <= '1';
-- Only reset the below if making state change
int_ctl_init_success <= '0';
int_ctl_init_fail <= '0';
-- default chip select counter gets reset to zero
cs_counter <= 0;
case state is
when s_reset => state <= s_phy_initialise;
ac_nt <= (others => '1');
mtp_almts_checked <= 0;
ac_nt_almts_checked <= 0;
when s_phy_initialise => state <= s_init_dram;
when s_init_dram => state <= s_prog_cal_mr;
when s_prog_cal_mr => if cs_counter = MEM_IF_NUM_RANKS - 1 then
-- if no debug interface don't write iram header
if GENERATE_ADDITIONAL_DBG_RTL = 1 then
state <= s_write_ihi;
else
state <= s_cal;
end if;
else
cs_counter <= cs_counter + 1;
reissue_cmd_req <= '1';
end if;
when s_write_ihi => state <= s_cal;
when s_cal => if mmi_ctrl.hl_css.cal_dis = '0' then
state <= s_write_btp;
else
state <= s_tracking_setup;
end if;
-- always enter s_cal before calibration so reset some variables here
mtp_almts_checked <= 0;
ac_nt_almts_checked <= 0;
when s_write_btp => if cs_counter = MEM_IF_NUM_RANKS-1 or
SIM_TIME_REDUCTIONS = 2 then
state <= s_write_mtp;
else
cs_counter <= cs_counter + 1;
-- only reissue command if current chip select enabled
if cal_cs_enabled(cs_counter + 1) = '1' then
reissue_cmd_req <= '1';
end if;
end if;
when s_write_mtp => if cs_counter = MEM_IF_NUM_RANKS - 1 or
SIM_TIME_REDUCTIONS = 2 then
if SIM_TIME_REDUCTIONS = 1 then
state <= s_rdv;
else
state <= s_rrp_reset;
end if;
else
cs_counter <= cs_counter + 1;
-- only reissue command if current chip select enabled
if cal_cs_enabled(cs_counter + 1) = '1' then
reissue_cmd_req <= '1';
end if;
end if;
when s_rrp_reset => state <= s_rrp_sweep;
when s_rrp_sweep => if cs_counter = MEM_IF_NUM_RANKS - 1 or
mtp_almts_checked /= 2 or
SIM_TIME_REDUCTIONS = 2 then
if mtp_almts_checked /= 2 then
state <= s_read_mtp;
else
state <= s_rrp_seek;
end if;
else
cs_counter <= cs_counter + 1;
-- only reissue command if current chip select enabled
if cal_cs_enabled(cs_counter + 1) = '1' then
reissue_cmd_req <= '1';
end if;
end if;
when s_read_mtp => if mtp_almts_checked /= 2 then
mtp_almts_checked <= mtp_almts_checked + 1;
end if;
state <= s_rrp_reset;
when s_rrp_seek => state <= s_rdv;
when s_rdv => state <= s_was;
when s_was => state <= s_adv_rd_lat;
when s_adv_rd_lat => state <= s_adv_wr_lat;
when s_adv_wr_lat => if dgrb_ctrl_ac_nt_good = '1' then
state <= s_poa;
else
if ac_nt_almts_checked = (DWIDTH_RATIO/2 - 1) then
state <= s_non_operational;
else
-- switch alignment and restart calibration
ac_nt <= std_logic_vector(unsigned(ac_nt) + 1);
ac_nt_almts_checked <= ac_nt_almts_checked + 1;
if SIM_TIME_REDUCTIONS = 1 then
state <= s_rdv;
else
state <= s_rrp_reset;
end if;
mtp_almts_checked <= 0;
end if;
end if;
when s_poa => state <= s_tracking_setup;
when s_tracking_setup => state <= s_prep_customer_mr_setup;
when s_prep_customer_mr_setup => if cs_counter = MEM_IF_NUM_RANKS - 1 then -- s_prep_customer_mr_setup is always performed over all cs
state <= s_operational;
else
cs_counter <= cs_counter + 1;
reissue_cmd_req <= '1';
end if;
when s_tracking => state <= s_operational;
int_ctl_init_success <= int_ctl_init_success;
int_ctl_init_fail <= int_ctl_init_fail;
when s_operational => int_ctl_init_success <= '1';
int_ctl_init_fail <= '0';
hold_state <= '0';
if tracking_update_due = '1' and mmi_ctrl.hl_css.tracking_dis = '0' then
state <= s_tracking;
hold_state <= '1';
end if;
when s_non_operational => int_ctl_init_success <= '0';
int_ctl_init_fail <= '1';
hold_state <= '0';
if last_state /= s_non_operational then -- print a warning on entering this state
report ctrl_report_prefix & "memory calibration has failed (output from ctrl block)" severity WARNING;
end if;
when others => state <= t_master_sm_state'succ(state);
end case;
end if;
end if;
if flag_done_timeout = '1' -- no done signal from current active block
or flag_ack_timeout = '1' -- or no ack signal from current active block
or curr_ctrl.command_err = '1' -- or an error from current active block
or mtp_err = '1' then -- or an error due to mtp alignment
state <= s_non_operational;
end if;
if mmi_ctrl.calibration_start = '1' then -- restart calibration process
state <= s_cal;
end if;
if ctl_recalibrate_req = '1' then -- restart all incl. initialisation
state <= s_reset;
end if;
end if;
end process;
-- generate output calibration fail/success signals
process(clk, rst_n)
begin
if rst_n = '0' then
ctl_init_fail <= '0';
ctl_init_success <= '0';
elsif rising_edge(clk) then
ctl_init_fail <= int_ctl_init_fail;
ctl_init_success <= int_ctl_init_success;
end if;
end process;
-- assign ac_nt to the output int_ac_nt
process(ac_nt)
begin
int_ac_nt <= ac_nt;
end process;
-- ------------------------------------------------------------------------------
-- find correct mtp_almt from returned data
-- ------------------------------------------------------------------------------
mtp_almt: block
signal dvw_size_a0 : natural range 0 to 255; -- maximum size of command result
signal dvw_size_a1 : natural range 0 to 255;
begin
process (clk, rst_n)
variable v_dvw_a0_small : boolean;
variable v_dvw_a1_small : boolean;
begin
if rst_n = '0' then
mtp_correct_almt <= 0;
dvw_size_a0 <= 0;
dvw_size_a1 <= 0;
mtp_no_valid_almt <= '0';
mtp_both_valid_almt <= '0';
mtp_err <= '0';
elsif rising_edge(clk) then
-- update the dvw sizes
if state = s_read_mtp then
if curr_ctrl.command_done = '1' then
if mtp_almts_checked = 0 then
dvw_size_a0 <= to_integer(unsigned(curr_ctrl.command_result));
else
dvw_size_a1 <= to_integer(unsigned(curr_ctrl.command_result));
end if;
end if;
end if;
-- check dvw size and set mtp almt
if dvw_size_a0 < dvw_size_a1 then
mtp_correct_almt <= 1;
else
mtp_correct_almt <= 0;
end if;
-- error conditions
if mtp_almts_checked = 2 and GENERATE_ADDITIONAL_DBG_RTL = 1 then -- if finished alignment checking (and GENERATE_ADDITIONAL_DBG_RTL set)
-- perform size checks once per dvw
if dvw_size_a0 < 3 then
v_dvw_a0_small := true;
else
v_dvw_a0_small := false;
end if;
if dvw_size_a1 < 3 then
v_dvw_a1_small := true;
else
v_dvw_a1_small := false;
end if;
if v_dvw_a0_small = true and v_dvw_a1_small = true then
mtp_no_valid_almt <= '1';
mtp_err <= '1';
end if;
if v_dvw_a0_small = false and v_dvw_a1_small = false then
mtp_both_valid_almt <= '1';
mtp_err <= '1';
end if;
else
mtp_no_valid_almt <= '0';
mtp_both_valid_almt <= '0';
mtp_err <= '0';
end if;
end if;
end process;
end block;
-- ------------------------------------------------------------------------------
-- process to generate command outputs, based on state, last_state and mmi_ctrl.
-- asynchronously
-- ------------------------------------------------------------------------------
process (state, last_state, mmi_ctrl, reissue_cmd_req, cs_counter, mtp_almts_checked, mtp_correct_almt)
begin
master_ctrl_op_rec <= defaults;
master_ctrl_iram_push <= defaults;
case state is
-- special condition states
when s_reset | s_phy_initialise | s_cal =>
null;
when s_write_ihi =>
if mmi_ctrl.hl_css.write_ihi_dis = '0' then
master_ctrl_op_rec.command <= find_cmd(state);
if state /= last_state then
master_ctrl_op_rec.command_req <= '1';
end if;
end if;
when s_operational | s_non_operational =>
master_ctrl_op_rec.command <= find_cmd(state);
when others => -- default condition for most states
if find_dis_bit(state, mmi_ctrl) = '0' then
master_ctrl_op_rec.command <= find_cmd(state);
if state /= last_state or reissue_cmd_req = '1' then
master_ctrl_op_rec.command_req <= '1';
end if;
else
if state = last_state then -- safe state exit if state disabled mid-calibration
master_ctrl_op_rec.command <= find_cmd(state);
end if;
end if;
end case;
-- for multiple chip select commands assign operand to cs_counter
master_ctrl_op_rec.command_op <= defaults;
master_ctrl_op_rec.command_op.current_cs <= cs_counter;
if state = s_rrp_sweep or state = s_read_mtp or state = s_poa then
if mtp_almts_checked /= 2 or SIM_TIME_REDUCTIONS = 2 then
master_ctrl_op_rec.command_op.single_bit <= '1';
end if;
if mtp_almts_checked /= 2 then
master_ctrl_op_rec.command_op.mtp_almt <= mtp_almts_checked;
else
master_ctrl_op_rec.command_op.mtp_almt <= mtp_correct_almt;
end if;
end if;
-- set write mode and packing mode for iram
if GENERATE_ADDITIONAL_DBG_RTL = 1 then
case state is
when s_rrp_sweep =>
master_ctrl_iram_push.write_mode <= overwrite_ram;
master_ctrl_iram_push.packing_mode <= dq_bitwise;
when s_rrp_seek |
s_read_mtp =>
master_ctrl_iram_push.write_mode <= overwrite_ram;
master_ctrl_iram_push.packing_mode <= dq_wordwise;
when others =>
null;
end case;
end if;
-- set current active block
master_ctrl_iram_push.active_block <= curr_active_block(find_cmd(state));
end process;
-- some concurc_read_burst_trent assignments to outputs
process (master_ctrl_iram_push, master_ctrl_op_rec)
begin
ctrl_iram_push <= master_ctrl_iram_push;
ctrl_op_rec <= master_ctrl_op_rec;
cmd_req_asserted <= master_ctrl_op_rec.command_req;
end process;
-- -----------------------------------------------------------------------------
-- tracking interval counter
-- -----------------------------------------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
milisecond_tick_gen_count <= c_ticks_per_ms -1;
tracking_ms_counter <= 0;
tracking_update_due <= '0';
elsif rising_edge(clk) then
if state = s_operational and last_state/= s_operational then
if mmi_ctrl.tracking_orvd_to_10ms = '1' then
milisecond_tick_gen_count <= c_ticks_per_10us -1;
else
milisecond_tick_gen_count <= c_ticks_per_ms -1;
end if;
tracking_ms_counter <= mmi_ctrl.tracking_period_ms;
elsif state = s_operational then
if milisecond_tick_gen_count = 0 and tracking_update_due /= '1' then
if tracking_ms_counter = 0 then
tracking_update_due <= '1';
else
tracking_ms_counter <= tracking_ms_counter -1;
end if;
if mmi_ctrl.tracking_orvd_to_10ms = '1' then
milisecond_tick_gen_count <= c_ticks_per_10us -1;
else
milisecond_tick_gen_count <= c_ticks_per_ms -1;
end if;
elsif milisecond_tick_gen_count /= 0 then
milisecond_tick_gen_count <= milisecond_tick_gen_count -1;
end if;
else
tracking_update_due <= '0';
end if;
end if;
end process;
end architecture struct;
--
-- -----------------------------------------------------------------------------
-- Abstract : top level for the non-levelling AFI PHY sequencer
-- The top level instances the sub-blocks of the AFI PHY
-- sequencer. In addition a number of multiplexing and high-
-- level control operations are performed. This includes the
-- multiplexing and generation of control signals for: the
-- address and command DRAM interface and pll, oct and datapath
-- latency control signals.
-- -----------------------------------------------------------------------------
--altera message_off 10036
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--
entity memphy_alt_mem_phy_seq IS
generic (
-- choice of FPGA device family and DRAM type
FAMILY : string;
MEM_IF_MEMTYPE : string;
SPEED_GRADE : string;
FAMILYGROUP_ID : natural;
-- physical interface width definitions
MEM_IF_DQS_WIDTH : natural;
MEM_IF_DWIDTH : natural;
MEM_IF_DM_WIDTH : natural;
MEM_IF_DQ_PER_DQS : natural;
DWIDTH_RATIO : natural;
CLOCK_INDEX_WIDTH : natural;
MEM_IF_CLK_PAIR_COUNT : natural;
MEM_IF_ADDR_WIDTH : natural;
MEM_IF_BANKADDR_WIDTH : natural;
MEM_IF_CS_WIDTH : natural;
MEM_IF_NUM_RANKS : natural;
MEM_IF_RANKS_PER_SLOT : natural;
ADV_LAT_WIDTH : natural;
RESYNCHRONISE_AVALON_DBG : natural; -- 0 = false, 1 = true
AV_IF_ADDR_WIDTH : natural;
-- Not used for non-levelled seq
CHIP_OR_DIMM : string;
RDIMM_CONFIG_BITS : string;
-- setup / algorithm information
NOM_DQS_PHASE_SETTING : natural;
SCAN_CLK_DIVIDE_BY : natural;
RDP_ADDR_WIDTH : natural;
PLL_STEPS_PER_CYCLE : natural;
IOE_PHASES_PER_TCK : natural;
IOE_DELAYS_PER_PHS : natural;
MEM_IF_CLK_PS : natural;
WRITE_DESKEW_T10 : natural;
WRITE_DESKEW_HC_T10 : natural;
WRITE_DESKEW_T9NI : natural;
WRITE_DESKEW_HC_T9NI : natural;
WRITE_DESKEW_T9I : natural;
WRITE_DESKEW_HC_T9I : natural;
WRITE_DESKEW_RANGE : natural;
-- initial mode register settings
PHY_DEF_MR_1ST : natural;
PHY_DEF_MR_2ND : natural;
PHY_DEF_MR_3RD : natural;
PHY_DEF_MR_4TH : natural;
MEM_IF_DQSN_EN : natural; -- default off for Cyclone-III
MEM_IF_DQS_CAPTURE_EN : natural;
GENERATE_ADDITIONAL_DBG_RTL : natural; -- 1 signals to include iram and mmi blocks and 0 not to include
SINGLE_DQS_DELAY_CONTROL_CODE : natural; -- reserved for future use
PRESET_RLAT : natural; -- reserved for future use
EN_OCT : natural; -- Does the sequencer use OCT during calibration.
OCT_LAT_WIDTH : natural;
SIM_TIME_REDUCTIONS : natural; -- if 0 null, if 2 rrp for 1 dqs group and 1 cs
FORCE_HC : natural; -- Use to force HardCopy in simulation.
CAPABILITIES : natural; -- advertise capabilities i.e. which ctrl block states to execute (default all on)
TINIT_TCK : natural;
TINIT_RST : natural;
GENERATE_TRACKING_PHASE_STORE : natural; -- reserved for future use
IP_BUILDNUM : natural
);
port (
-- clk / reset
clk : in std_logic;
rst_n : in std_logic;
-- calibration status and prompt
ctl_init_success : out std_logic;
ctl_init_fail : out std_logic;
ctl_init_warning : out std_logic; -- unused
ctl_recalibrate_req : in std_logic;
-- the following two signals are reserved for future use
mem_ac_swapped_ranks : in std_logic_vector(MEM_IF_NUM_RANKS - 1 downto 0);
ctl_cal_byte_lanes : in std_logic_vector(MEM_IF_NUM_RANKS * MEM_IF_DQS_WIDTH - 1 downto 0);
-- pll reconfiguration
seq_pll_inc_dec_n : out std_logic;
seq_pll_start_reconfig : out std_logic;
seq_pll_select : out std_logic_vector(CLOCK_INDEX_WIDTH - 1 downto 0);
seq_pll_phs_shift_busy : in std_logic;
pll_resync_clk_index : in std_logic_vector(CLOCK_INDEX_WIDTH - 1 downto 0); -- PLL phase used to select resync clock
pll_measure_clk_index : in std_logic_vector(CLOCK_INDEX_WIDTH - 1 downto 0); -- PLL phase used to select mimic/measure clock
-- scanchain associated signals (reserved for future use)
seq_scan_clk : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_scan_enable_dqs_config : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_scan_update : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_scan_din : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_scan_enable_ck : out std_logic_vector(MEM_IF_CLK_PAIR_COUNT - 1 downto 0);
seq_scan_enable_dqs : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_scan_enable_dqsn : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_scan_enable_dq : out std_logic_vector(MEM_IF_DWIDTH - 1 downto 0);
seq_scan_enable_dm : out std_logic_vector(MEM_IF_DM_WIDTH - 1 downto 0);
hr_rsc_clk : in std_logic;
-- address / command interface (note these are mapped internally to the seq_ac record)
seq_ac_addr : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_ADDR_WIDTH - 1 downto 0);
seq_ac_ba : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_BANKADDR_WIDTH - 1 downto 0);
seq_ac_cas_n : out std_logic_vector((DWIDTH_RATIO/2) - 1 downto 0);
seq_ac_ras_n : out std_logic_vector((DWIDTH_RATIO/2) - 1 downto 0);
seq_ac_we_n : out std_logic_vector((DWIDTH_RATIO/2) - 1 downto 0);
seq_ac_cke : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_NUM_RANKS - 1 downto 0);
seq_ac_cs_n : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_NUM_RANKS - 1 downto 0);
seq_ac_odt : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_NUM_RANKS - 1 downto 0);
seq_ac_rst_n : out std_logic_vector((DWIDTH_RATIO/2) - 1 downto 0);
seq_ac_sel : out std_logic;
seq_mem_clk_disable : out std_logic;
-- additional datapath latency (reserved for future use)
seq_ac_add_1t_ac_lat_internal : out std_logic;
seq_ac_add_1t_odt_lat_internal : out std_logic;
seq_ac_add_2t : out std_logic;
-- read datapath interface
seq_rdp_reset_req_n : out std_logic;
seq_rdp_inc_read_lat_1x : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_rdp_dec_read_lat_1x : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
rdata : in std_logic_vector( DWIDTH_RATIO * MEM_IF_DWIDTH - 1 downto 0);
-- read data valid (associated signals) interface
seq_rdv_doing_rd : out std_logic_vector(MEM_IF_DQS_WIDTH * DWIDTH_RATIO/2 - 1 downto 0);
rdata_valid : in std_logic_vector( DWIDTH_RATIO/2 - 1 downto 0);
seq_rdata_valid_lat_inc : out std_logic;
seq_rdata_valid_lat_dec : out std_logic;
seq_ctl_rlat : out std_logic_vector(ADV_LAT_WIDTH - 1 downto 0);
-- postamble interface (unused for Cyclone-III)
seq_poa_lat_dec_1x : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_poa_lat_inc_1x : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_poa_protection_override_1x : out std_logic;
-- OCT path control
seq_oct_oct_delay : out std_logic_vector(OCT_LAT_WIDTH - 1 downto 0);
seq_oct_oct_extend : out std_logic_vector(OCT_LAT_WIDTH - 1 downto 0);
seq_oct_value : out std_logic;
-- write data path interface
seq_wdp_dqs_burst : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_DQS_WIDTH - 1 downto 0);
seq_wdp_wdata_valid : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_DQS_WIDTH - 1 downto 0);
seq_wdp_wdata : out std_logic_vector( DWIDTH_RATIO * MEM_IF_DWIDTH - 1 downto 0);
seq_wdp_dm : out std_logic_vector( DWIDTH_RATIO * MEM_IF_DM_WIDTH - 1 downto 0);
seq_wdp_dqs : out std_logic_vector( DWIDTH_RATIO - 1 downto 0);
seq_wdp_ovride : out std_logic;
seq_dqs_add_2t_delay : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_ctl_wlat : out std_logic_vector(ADV_LAT_WIDTH - 1 downto 0);
-- mimic path interface
seq_mmc_start : out std_logic;
mmc_seq_done : in std_logic;
mmc_seq_value : in std_logic;
-- parity signals (not used for non-levelled PHY)
mem_err_out_n : in std_logic;
parity_error_n : out std_logic;
--synchronous Avalon debug interface (internally re-synchronised to input clock (a generic option))
dbg_seq_clk : in std_logic;
dbg_seq_rst_n : in std_logic;
dbg_seq_addr : in std_logic_vector(AV_IF_ADDR_WIDTH - 1 downto 0);
dbg_seq_wr : in std_logic;
dbg_seq_rd : in std_logic;
dbg_seq_cs : in std_logic;
dbg_seq_wr_data : in std_logic_vector(31 downto 0);
seq_dbg_rd_data : out std_logic_vector(31 downto 0);
seq_dbg_waitrequest : out std_logic
);
end entity;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.memphy_alt_mem_phy_record_pkg.all;
-- The registers package (alt_mem_phy_regs_pkg) is used to combine the definition of the
-- registers for the mmi status registers and functions/procedures applied to the registers
--
use work.memphy_alt_mem_phy_regs_pkg.all;
-- The constant package (alt_mem_phy_constants_pkg) contains global 'constants' which are fixed
-- thoughout the sequencer and will not change (for constants which may change between sequencer
-- instances generics are used)
--
use work.memphy_alt_mem_phy_constants_pkg.all;
-- The iram address package (alt_mem_phy_iram_addr_pkg) is used to define the base addresses used
-- for iram writes during calibration
--
use work.memphy_alt_mem_phy_iram_addr_pkg.all;
-- The address and command package (alt_mem_phy_addr_cmd_pkg) is used to combine DRAM address
-- and command signals in one record and unify the functions operating on this record.
--
use work.memphy_alt_mem_phy_addr_cmd_pkg.all;
-- Individually include each of library files for the sub-blocks of the sequencer:
--
use work.memphy_alt_mem_phy_admin;
--
use work.memphy_alt_mem_phy_mmi;
--
use work.memphy_alt_mem_phy_iram;
--
use work.memphy_alt_mem_phy_dgrb;
--
use work.memphy_alt_mem_phy_dgwb;
--
use work.memphy_alt_mem_phy_ctrl;
--
architecture struct of memphy_alt_mem_phy_seq IS
attribute altera_attribute : string;
attribute altera_attribute of struct : architecture is "-name MESSAGE_DISABLE 18010";
-- debug signals (similar to those seen in the Quartus v8.0 DDR/DDR2 sequencer)
signal rsu_multiple_valid_latencies_err : std_logic; -- true if >2 valid latency values are detected
signal rsu_grt_one_dvw_err : std_logic; -- true if >1 data valid window is detected
signal rsu_no_dvw_err : std_logic; -- true if no data valid window is detected
signal rsu_codvw_phase : std_logic_vector(11 downto 0); -- set to the phase of the DVW detected if calibration is successful
signal rsu_codvw_size : std_logic_vector(11 downto 0); -- set to the phase of the DVW detected if calibration is successful
signal rsu_read_latency : std_logic_vector(ADV_LAT_WIDTH - 1 downto 0); -- set to the correct read latency if calibration is successful
-- outputs from the dgrb to generate the above rsu_codvw_* signals and report status to the mmi
signal dgrb_mmi : t_dgrb_mmi;
-- admin to mmi interface
signal regs_admin_ctrl_rec : t_admin_ctrl; -- mmi register settings information
signal admin_regs_status_rec : t_admin_stat; -- admin status information
-- odt enable from the admin block based on mr settings
signal enable_odt : std_logic;
-- iram status information (sent to the ctrl block)
signal iram_status : t_iram_stat;
-- dgrb iram write interface
signal dgrb_iram : t_iram_push;
-- ctrl to iram interface
signal ctrl_idib_top : natural; -- current write location in the iram
signal ctrl_active_block : t_ctrl_active_block;
signal ctrl_iram_push : t_ctrl_iram;
signal iram_push_done : std_logic;
signal ctrl_iram_ihi_write : std_logic;
-- local copies of calibration status
signal ctl_init_success_int : std_logic;
signal ctl_init_fail_int : std_logic;
-- refresh period failure flag
signal trefi_failure : std_logic;
-- unified ctrl signal broadcast to all blocks from the ctrl block
signal ctrl_broadcast : t_ctrl_command;
-- standardised status report per block to control block
signal admin_ctrl : t_ctrl_stat;
signal dgwb_ctrl : t_ctrl_stat;
signal dgrb_ctrl : t_ctrl_stat;
-- mmi and ctrl block interface
signal mmi_ctrl : t_mmi_ctrl;
signal ctrl_mmi : t_ctrl_mmi;
-- write datapath override signals
signal dgwb_wdp_override : std_logic;
signal dgrb_wdp_override : std_logic;
-- address/command access request and grant between the dgrb/dgwb blocks and the admin block
signal dgb_ac_access_gnt : std_logic;
signal dgb_ac_access_gnt_r : std_logic;
signal dgb_ac_access_req : std_logic;
signal dgwb_ac_access_req : std_logic;
signal dgrb_ac_access_req : std_logic;
-- per block address/command record (multiplexed in this entity)
signal admin_ac : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
signal dgwb_ac : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
signal dgrb_ac : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
-- doing read signal
signal seq_rdv_doing_rd_int : std_logic_vector(seq_rdv_doing_rd'range);
-- local copy of interface to inc/dec latency on rdata_valid and postamble
signal seq_rdata_valid_lat_dec_int : std_logic;
signal seq_rdata_valid_lat_inc_int : std_logic;
signal seq_poa_lat_inc_1x_int : std_logic_vector(MEM_IF_DQS_WIDTH -1 downto 0);
signal seq_poa_lat_dec_1x_int : std_logic_vector(MEM_IF_DQS_WIDTH -1 downto 0);
-- local copy of write/read latency
signal seq_ctl_wlat_int : std_logic_vector(seq_ctl_wlat'range);
signal seq_ctl_rlat_int : std_logic_vector(seq_ctl_rlat'range);
-- parameterisation of dgrb / dgwb / admin blocks from mmi register settings
signal parameterisation_rec : t_algm_paramaterisation;
-- PLL reconfig
signal seq_pll_phs_shift_busy_r : std_logic;
signal seq_pll_phs_shift_busy_ccd : std_logic;
signal dgrb_pll_inc_dec_n : std_logic;
signal dgrb_pll_start_reconfig : std_logic;
signal dgrb_pll_select : std_logic_vector(CLOCK_INDEX_WIDTH - 1 downto 0);
signal dgrb_phs_shft_busy : std_logic;
signal mmi_pll_inc_dec_n : std_logic;
signal mmi_pll_start_reconfig : std_logic;
signal mmi_pll_select : std_logic_vector(CLOCK_INDEX_WIDTH - 1 downto 0);
signal pll_mmi : t_pll_mmi;
signal mmi_pll : t_mmi_pll_reconfig;
-- address and command 1t setting (unused for Full Rate)
signal int_ac_nt : std_logic_vector(((DWIDTH_RATIO+2)/4) - 1 downto 0);
signal dgrb_ctrl_ac_nt_good : std_logic;
-- the following signals are reserved for future use
signal ctl_cal_byte_lanes_r : std_logic_vector(ctl_cal_byte_lanes'range);
signal mmi_setup : t_ctrl_cmd_id;
signal dgwb_iram : t_iram_push;
-- track number of poa / rdv adjustments (reporting only)
signal poa_adjustments : natural;
signal rdv_adjustments : natural;
-- convert input generics from natural to std_logic_vector
constant c_phy_def_mr_1st_sl_vector : std_logic_vector(15 downto 0) := std_logic_vector(to_unsigned(PHY_DEF_MR_1ST, 16));
constant c_phy_def_mr_2nd_sl_vector : std_logic_vector(15 downto 0) := std_logic_vector(to_unsigned(PHY_DEF_MR_2ND, 16));
constant c_phy_def_mr_3rd_sl_vector : std_logic_vector(15 downto 0) := std_logic_vector(to_unsigned(PHY_DEF_MR_3RD, 16));
constant c_phy_def_mr_4th_sl_vector : std_logic_vector(15 downto 0) := std_logic_vector(to_unsigned(PHY_DEF_MR_4TH, 16));
-- overrride on capabilities to speed up simulation time
function capabilities_override(capabilities : natural;
sim_time_reductions : natural) return natural is
begin
if sim_time_reductions = 1 then
return 2**c_hl_css_reg_cal_dis_bit; -- disable calibration completely
else
return capabilities;
end if;
end function;
-- set sequencer capabilities
constant c_capabilities_override : natural := capabilities_override(CAPABILITIES, SIM_TIME_REDUCTIONS);
constant c_capabilities : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(c_capabilities_override,32));
-- setup for address/command interface
constant c_seq_addr_cmd_config : t_addr_cmd_config_rec := set_config_rec(MEM_IF_ADDR_WIDTH, MEM_IF_BANKADDR_WIDTH, MEM_IF_NUM_RANKS, DWIDTH_RATIO, MEM_IF_MEMTYPE);
-- setup for odt signals
-- odt setting as implemented in the altera high-performance controller for ddrx memories
constant c_odt_settings : t_odt_array(0 to MEM_IF_NUM_RANKS-1) := set_odt_values(MEM_IF_NUM_RANKS, MEM_IF_RANKS_PER_SLOT, MEM_IF_MEMTYPE);
-- a prefix for all report signals to identify phy and sequencer block
--
constant seq_report_prefix : string := "memphy_alt_mem_phy_seq (top) : ";
-- setup iram configuration
constant c_iram_addresses : t_base_hdr_addresses := calc_iram_addresses(DWIDTH_RATIO, PLL_STEPS_PER_CYCLE, MEM_IF_DWIDTH, MEM_IF_NUM_RANKS, MEM_IF_DQS_CAPTURE_EN);
constant c_int_iram_awidth : natural := c_iram_addresses.required_addr_bits;
constant c_preset_cal_setup : t_preset_cal := setup_instant_on(SIM_TIME_REDUCTIONS, FAMILYGROUP_ID, MEM_IF_MEMTYPE, DWIDTH_RATIO, PLL_STEPS_PER_CYCLE, c_phy_def_mr_1st_sl_vector, c_phy_def_mr_2nd_sl_vector, c_phy_def_mr_3rd_sl_vector);
constant c_preset_codvw_phase : natural := c_preset_cal_setup.codvw_phase;
constant c_preset_codvw_size : natural := c_preset_cal_setup.codvw_size;
constant c_tracking_interval_in_ms : natural := 128;
constant c_mem_if_cal_bank : natural := 0; -- location to calibrate to
constant c_mem_if_cal_base_col : natural := 0; -- default all zeros
constant c_mem_if_cal_base_row : natural := 0;
constant c_non_op_eval_md : string := "PIN_FINDER"; -- non_operational evaluation mode (used when GENERATE_ADDITIONAL_DBG_RTL = 1)
begin -- architecture struct
-- ---------------------------------------------------------------
-- tie off unused signals to default values
-- ---------------------------------------------------------------
-- scan chain associated signals
seq_scan_clk <= (others => '0');
seq_scan_enable_dqs_config <= (others => '0');
seq_scan_update <= (others => '0');
seq_scan_din <= (others => '0');
seq_scan_enable_ck <= (others => '0');
seq_scan_enable_dqs <= (others => '0');
seq_scan_enable_dqsn <= (others => '0');
seq_scan_enable_dq <= (others => '0');
seq_scan_enable_dm <= (others => '0');
seq_dqs_add_2t_delay <= (others => '0');
seq_rdp_inc_read_lat_1x <= (others => '0');
seq_rdp_dec_read_lat_1x <= (others => '0');
-- warning flag (not used in non-levelled sequencer)
ctl_init_warning <= '0';
-- parity error flag (not used in non-levelled sequencer)
parity_error_n <= '1';
--
admin: entity memphy_alt_mem_phy_admin
generic map
(
MEM_IF_DQS_WIDTH => MEM_IF_DQS_WIDTH,
MEM_IF_DWIDTH => MEM_IF_DWIDTH,
MEM_IF_DM_WIDTH => MEM_IF_DM_WIDTH,
MEM_IF_DQ_PER_DQS => MEM_IF_DQ_PER_DQS,
DWIDTH_RATIO => DWIDTH_RATIO,
CLOCK_INDEX_WIDTH => CLOCK_INDEX_WIDTH,
MEM_IF_CLK_PAIR_COUNT => MEM_IF_CLK_PAIR_COUNT,
MEM_IF_ADDR_WIDTH => MEM_IF_ADDR_WIDTH,
MEM_IF_BANKADDR_WIDTH => MEM_IF_BANKADDR_WIDTH,
MEM_IF_NUM_RANKS => MEM_IF_NUM_RANKS,
ADV_LAT_WIDTH => ADV_LAT_WIDTH,
MEM_IF_DQSN_EN => MEM_IF_DQSN_EN,
MEM_IF_MEMTYPE => MEM_IF_MEMTYPE,
MEM_IF_CAL_BANK => c_mem_if_cal_bank,
MEM_IF_CAL_BASE_ROW => c_mem_if_cal_base_row,
GENERATE_ADDITIONAL_DBG_RTL => GENERATE_ADDITIONAL_DBG_RTL,
NON_OP_EVAL_MD => c_non_op_eval_md,
MEM_IF_CLK_PS => MEM_IF_CLK_PS,
TINIT_TCK => TINIT_TCK,
TINIT_RST => TINIT_RST
)
port map
(
clk => clk,
rst_n => rst_n,
mem_ac_swapped_ranks => mem_ac_swapped_ranks,
ctl_cal_byte_lanes => ctl_cal_byte_lanes_r,
seq_ac => admin_ac,
seq_ac_sel => seq_ac_sel,
enable_odt => enable_odt,
regs_admin_ctrl_rec => regs_admin_ctrl_rec,
admin_regs_status_rec => admin_regs_status_rec,
trefi_failure => trefi_failure,
ctrl_admin => ctrl_broadcast,
admin_ctrl => admin_ctrl,
ac_access_req => dgb_ac_access_req,
ac_access_gnt => dgb_ac_access_gnt,
cal_fail => ctl_init_fail_int,
cal_success => ctl_init_success_int,
ctl_recalibrate_req => ctl_recalibrate_req
);
-- selectively include the debug i/f (iram and mmi blocks)
with_debug_if : if GENERATE_ADDITIONAL_DBG_RTL = 1 generate
signal mmi_iram : t_iram_ctrl;
signal mmi_iram_enable_writes : std_logic;
signal rrp_mem_loc : natural range 0 to 2 ** c_int_iram_awidth - 1;
signal command_req_r : std_logic;
signal ctrl_broadcast_r : t_ctrl_command;
begin
-- register ctrl_broadcast locally
process (clk, rst_n)
begin
if rst_n = '0' then
ctrl_broadcast_r <= defaults;
elsif rising_edge(clk) then
ctrl_broadcast_r <= ctrl_broadcast;
end if;
end process;
--
mmi : entity memphy_alt_mem_phy_mmi
generic map (
MEM_IF_DQS_WIDTH => MEM_IF_DQS_WIDTH,
MEM_IF_DWIDTH => MEM_IF_DWIDTH,
MEM_IF_DM_WIDTH => MEM_IF_DM_WIDTH,
MEM_IF_DQ_PER_DQS => MEM_IF_DQ_PER_DQS,
DWIDTH_RATIO => DWIDTH_RATIO,
CLOCK_INDEX_WIDTH => CLOCK_INDEX_WIDTH,
MEM_IF_CLK_PAIR_COUNT => MEM_IF_CLK_PAIR_COUNT,
MEM_IF_ADDR_WIDTH => MEM_IF_ADDR_WIDTH,
MEM_IF_BANKADDR_WIDTH => MEM_IF_BANKADDR_WIDTH,
MEM_IF_NUM_RANKS => MEM_IF_NUM_RANKS,
MEM_IF_DQS_CAPTURE => MEM_IF_DQS_CAPTURE_EN,
ADV_LAT_WIDTH => ADV_LAT_WIDTH,
RESYNCHRONISE_AVALON_DBG => RESYNCHRONISE_AVALON_DBG,
AV_IF_ADDR_WIDTH => AV_IF_ADDR_WIDTH,
NOM_DQS_PHASE_SETTING => NOM_DQS_PHASE_SETTING,
SCAN_CLK_DIVIDE_BY => SCAN_CLK_DIVIDE_BY,
RDP_ADDR_WIDTH => RDP_ADDR_WIDTH,
PLL_STEPS_PER_CYCLE => PLL_STEPS_PER_CYCLE,
IOE_PHASES_PER_TCK => IOE_PHASES_PER_TCK,
IOE_DELAYS_PER_PHS => IOE_DELAYS_PER_PHS,
MEM_IF_CLK_PS => MEM_IF_CLK_PS,
PHY_DEF_MR_1ST => c_phy_def_mr_1st_sl_vector,
PHY_DEF_MR_2ND => c_phy_def_mr_2nd_sl_vector,
PHY_DEF_MR_3RD => c_phy_def_mr_3rd_sl_vector,
PHY_DEF_MR_4TH => c_phy_def_mr_4th_sl_vector,
MEM_IF_MEMTYPE => MEM_IF_MEMTYPE,
PRESET_RLAT => PRESET_RLAT,
CAPABILITIES => c_capabilities_override,
USE_IRAM => '1', -- always use iram (generic is rfu)
IRAM_AWIDTH => c_int_iram_awidth,
TRACKING_INTERVAL_IN_MS => c_tracking_interval_in_ms,
READ_LAT_WIDTH => ADV_LAT_WIDTH
)
port map(
clk => clk,
rst_n => rst_n,
dbg_seq_clk => dbg_seq_clk,
dbg_seq_rst_n => dbg_seq_rst_n,
dbg_seq_addr => dbg_seq_addr,
dbg_seq_wr => dbg_seq_wr,
dbg_seq_rd => dbg_seq_rd,
dbg_seq_cs => dbg_seq_cs,
dbg_seq_wr_data => dbg_seq_wr_data,
seq_dbg_rd_data => seq_dbg_rd_data,
seq_dbg_waitrequest => seq_dbg_waitrequest,
regs_admin_ctrl => regs_admin_ctrl_rec,
admin_regs_status => admin_regs_status_rec,
mmi_iram => mmi_iram,
mmi_iram_enable_writes => mmi_iram_enable_writes,
iram_status => iram_status,
mmi_ctrl => mmi_ctrl,
ctrl_mmi => ctrl_mmi,
int_ac_1t => int_ac_nt(0),
invert_ac_1t => open,
trefi_failure => trefi_failure,
parameterisation_rec => parameterisation_rec,
pll_mmi => pll_mmi,
mmi_pll => mmi_pll,
dgrb_mmi => dgrb_mmi
);
--
iram : entity memphy_alt_mem_phy_iram
generic map(
MEM_IF_MEMTYPE => MEM_IF_MEMTYPE,
FAMILYGROUP_ID => FAMILYGROUP_ID,
MEM_IF_DQS_WIDTH => MEM_IF_DQS_WIDTH,
MEM_IF_DQ_PER_DQS => MEM_IF_DQ_PER_DQS,
MEM_IF_DWIDTH => MEM_IF_DWIDTH,
MEM_IF_DM_WIDTH => MEM_IF_DM_WIDTH,
MEM_IF_NUM_RANKS => MEM_IF_NUM_RANKS,
IRAM_AWIDTH => c_int_iram_awidth,
REFRESH_COUNT_INIT => 12,
PRESET_RLAT => PRESET_RLAT,
PLL_STEPS_PER_CYCLE => PLL_STEPS_PER_CYCLE,
CAPABILITIES => c_capabilities_override,
IP_BUILDNUM => IP_BUILDNUM
)
port map(
clk => clk,
rst_n => rst_n,
mmi_iram => mmi_iram,
mmi_iram_enable_writes => mmi_iram_enable_writes,
iram_status => iram_status,
iram_push_done => iram_push_done,
ctrl_iram => ctrl_broadcast_r,
dgrb_iram => dgrb_iram,
admin_regs_status_rec => admin_regs_status_rec,
ctrl_idib_top => ctrl_idib_top,
ctrl_iram_push => ctrl_iram_push,
dgwb_iram => dgwb_iram
);
-- calculate where current data should go in the iram
process (clk, rst_n)
variable v_words_req : natural range 0 to 2 * MEM_IF_DWIDTH * PLL_STEPS_PER_CYCLE * DWIDTH_RATIO - 1; -- how many words are required
begin
if rst_n = '0' then
ctrl_idib_top <= 0;
command_req_r <= '0';
rrp_mem_loc <= 0;
elsif rising_edge(clk) then
if command_req_r = '0' and ctrl_broadcast_r.command_req = '1' then -- execute once on each command_req assertion
-- default a 'safe location'
ctrl_idib_top <= c_iram_addresses.safe_dummy;
case ctrl_broadcast_r.command is
when cmd_write_ihi => -- reset pointers
rrp_mem_loc <= c_iram_addresses.rrp;
ctrl_idib_top <= 0; -- write header to zero location always
when cmd_rrp_sweep =>
-- add previous space requirement onto the current address
ctrl_idib_top <= rrp_mem_loc;
-- add the current space requirement to v_rrp_mem_loc
-- there are (DWIDTH_RATIO/2) * PLL_STEPS_PER_CYCLE phases swept packed into 32 bit words per pin
-- note: special case for single_bit calibration stages (e.g. read_mtp alignment)
if ctrl_broadcast_r.command_op.single_bit = '1' then
v_words_req := iram_wd_for_one_pin_rrp(DWIDTH_RATIO, PLL_STEPS_PER_CYCLE, MEM_IF_DWIDTH, MEM_IF_DQS_CAPTURE_EN);
else
v_words_req := iram_wd_for_full_rrp(DWIDTH_RATIO, PLL_STEPS_PER_CYCLE, MEM_IF_DWIDTH, MEM_IF_DQS_CAPTURE_EN);
end if;
v_words_req := v_words_req + 2; -- add 1 word location for header / footer information
rrp_mem_loc <= rrp_mem_loc + v_words_req;
when cmd_rrp_seek |
cmd_read_mtp =>
-- add previous space requirement onto the current address
ctrl_idib_top <= rrp_mem_loc;
-- require 3 words - header, result and footer
v_words_req := 3;
rrp_mem_loc <= rrp_mem_loc + v_words_req;
when others =>
null;
end case;
end if;
command_req_r <= ctrl_broadcast_r.command_req;
-- if recalibration request then reset iram address
if ctl_recalibrate_req = '1' or mmi_ctrl.calibration_start = '1' then
rrp_mem_loc <= c_iram_addresses.rrp;
end if;
end if;
end process;
end generate; -- with debug interface
-- if no debug interface (iram/mmi block) tie off relevant signals
without_debug_if : if GENERATE_ADDITIONAL_DBG_RTL = 0 generate
constant c_slv_hl_stage_enable : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(c_capabilities_override, 32));
constant c_hl_stage_enable : std_logic_vector(c_hl_ccs_num_stages-1 downto 0) := c_slv_hl_stage_enable(c_hl_ccs_num_stages-1 downto 0);
constant c_pll_360_sweeps : natural := rrp_pll_phase_mult(DWIDTH_RATIO, MEM_IF_DQS_CAPTURE_EN);
signal mmi_regs : t_mmi_regs := defaults;
begin
-- avalon interface signals
seq_dbg_rd_data <= (others => '0');
seq_dbg_waitrequest <= '0';
-- The following registers are generated to simplify the assignments which follow
-- but will be optimised away in synthesis
mmi_regs.rw_regs <= defaults(c_phy_def_mr_1st_sl_vector,
c_phy_def_mr_2nd_sl_vector,
c_phy_def_mr_3rd_sl_vector,
c_phy_def_mr_4th_sl_vector,
NOM_DQS_PHASE_SETTING,
PLL_STEPS_PER_CYCLE,
c_pll_360_sweeps,
c_tracking_interval_in_ms,
c_hl_stage_enable);
mmi_regs.ro_regs <= defaults(dgrb_mmi,
ctrl_mmi,
pll_mmi,
mmi_regs.rw_regs.rw_if_test,
'0', -- do not use iram
MEM_IF_DQS_CAPTURE_EN,
int_ac_nt(0),
trefi_failure,
iram_status,
c_int_iram_awidth);
process(mmi_regs)
begin
-- debug parameterisation signals
regs_admin_ctrl_rec <= pack_record(mmi_regs.rw_regs);
parameterisation_rec <= pack_record(mmi_regs.rw_regs);
mmi_pll <= pack_record(mmi_regs.rw_regs);
mmi_ctrl <= pack_record(mmi_regs.rw_regs);
end process;
-- from the iram
iram_status <= defaults;
iram_push_done <= '0';
end generate; -- without debug interface
--
dgrb : entity memphy_alt_mem_phy_dgrb
generic map(
MEM_IF_DQS_WIDTH => MEM_IF_DQS_WIDTH,
MEM_IF_DQ_PER_DQS => MEM_IF_DQ_PER_DQS,
MEM_IF_DWIDTH => MEM_IF_DWIDTH,
MEM_IF_DM_WIDTH => MEM_IF_DM_WIDTH,
MEM_IF_DQS_CAPTURE => MEM_IF_DQS_CAPTURE_EN,
DWIDTH_RATIO => DWIDTH_RATIO,
CLOCK_INDEX_WIDTH => CLOCK_INDEX_WIDTH,
MEM_IF_ADDR_WIDTH => MEM_IF_ADDR_WIDTH,
MEM_IF_BANKADDR_WIDTH => MEM_IF_BANKADDR_WIDTH,
MEM_IF_NUM_RANKS => MEM_IF_NUM_RANKS,
MEM_IF_MEMTYPE => MEM_IF_MEMTYPE,
ADV_LAT_WIDTH => ADV_LAT_WIDTH,
PRESET_RLAT => PRESET_RLAT,
PLL_STEPS_PER_CYCLE => PLL_STEPS_PER_CYCLE,
SIM_TIME_REDUCTIONS => SIM_TIME_REDUCTIONS,
GENERATE_ADDITIONAL_DBG_RTL => GENERATE_ADDITIONAL_DBG_RTL,
PRESET_CODVW_PHASE => c_preset_codvw_phase,
PRESET_CODVW_SIZE => c_preset_codvw_size,
MEM_IF_CAL_BANK => c_mem_if_cal_bank,
MEM_IF_CAL_BASE_COL => c_mem_if_cal_base_col,
EN_OCT => EN_OCT
)
port map(
clk => clk,
rst_n => rst_n,
dgrb_ctrl => dgrb_ctrl,
ctrl_dgrb => ctrl_broadcast,
parameterisation_rec => parameterisation_rec,
phs_shft_busy => dgrb_phs_shft_busy,
seq_pll_inc_dec_n => dgrb_pll_inc_dec_n,
seq_pll_select => dgrb_pll_select,
seq_pll_start_reconfig => dgrb_pll_start_reconfig,
pll_resync_clk_index => pll_resync_clk_index,
pll_measure_clk_index => pll_measure_clk_index,
dgrb_iram => dgrb_iram,
iram_push_done => iram_push_done,
dgrb_ac => dgrb_ac,
dgrb_ac_access_req => dgrb_ac_access_req,
dgrb_ac_access_gnt => dgb_ac_access_gnt_r,
seq_rdata_valid_lat_inc => seq_rdata_valid_lat_inc_int,
seq_rdata_valid_lat_dec => seq_rdata_valid_lat_dec_int,
seq_poa_lat_dec_1x => seq_poa_lat_dec_1x_int,
seq_poa_lat_inc_1x => seq_poa_lat_inc_1x_int,
rdata_valid => rdata_valid,
rdata => rdata,
doing_rd => seq_rdv_doing_rd_int,
rd_lat => seq_ctl_rlat_int,
wd_lat => seq_ctl_wlat_int,
dgrb_wdp_ovride => dgrb_wdp_override,
seq_oct_value => seq_oct_value,
seq_mmc_start => seq_mmc_start,
mmc_seq_done => mmc_seq_done,
mmc_seq_value => mmc_seq_value,
ctl_cal_byte_lanes => ctl_cal_byte_lanes_r,
odt_settings => c_odt_settings,
dgrb_ctrl_ac_nt_good => dgrb_ctrl_ac_nt_good,
dgrb_mmi => dgrb_mmi
);
--
dgwb : entity memphy_alt_mem_phy_dgwb
generic map(
-- Physical IF width definitions
MEM_IF_DQS_WIDTH => MEM_IF_DQS_WIDTH,
MEM_IF_DQ_PER_DQS => MEM_IF_DQ_PER_DQS,
MEM_IF_DWIDTH => MEM_IF_DWIDTH,
MEM_IF_DM_WIDTH => MEM_IF_DM_WIDTH,
DWIDTH_RATIO => DWIDTH_RATIO,
MEM_IF_ADDR_WIDTH => MEM_IF_ADDR_WIDTH,
MEM_IF_BANKADDR_WIDTH => MEM_IF_BANKADDR_WIDTH,
MEM_IF_NUM_RANKS => MEM_IF_NUM_RANKS,
MEM_IF_MEMTYPE => MEM_IF_MEMTYPE,
ADV_LAT_WIDTH => ADV_LAT_WIDTH,
MEM_IF_CAL_BANK => c_mem_if_cal_bank,
MEM_IF_CAL_BASE_COL => c_mem_if_cal_base_col
)
port map(
clk => clk,
rst_n => rst_n,
parameterisation_rec => parameterisation_rec,
dgwb_ctrl => dgwb_ctrl,
ctrl_dgwb => ctrl_broadcast,
dgwb_iram => dgwb_iram,
iram_push_done => iram_push_done,
dgwb_ac_access_req => dgwb_ac_access_req,
dgwb_ac_access_gnt => dgb_ac_access_gnt_r,
dgwb_dqs_burst => seq_wdp_dqs_burst,
dgwb_wdata_valid => seq_wdp_wdata_valid,
dgwb_wdata => seq_wdp_wdata,
dgwb_dm => seq_wdp_dm,
dgwb_dqs => seq_wdp_dqs,
dgwb_wdp_ovride => dgwb_wdp_override,
dgwb_ac => dgwb_ac,
bypassed_rdata => rdata(DWIDTH_RATIO * MEM_IF_DWIDTH -1 downto (DWIDTH_RATIO-1) * MEM_IF_DWIDTH),
odt_settings => c_odt_settings
);
--
ctrl: entity memphy_alt_mem_phy_ctrl
generic map(
FAMILYGROUP_ID => FAMILYGROUP_ID,
MEM_IF_DLL_LOCK_COUNT => 1280/(DWIDTH_RATIO/2),
MEM_IF_MEMTYPE => MEM_IF_MEMTYPE,
DWIDTH_RATIO => DWIDTH_RATIO,
IRAM_ADDRESSING => c_iram_addresses,
MEM_IF_CLK_PS => MEM_IF_CLK_PS,
TRACKING_INTERVAL_IN_MS => c_tracking_interval_in_ms,
GENERATE_ADDITIONAL_DBG_RTL => GENERATE_ADDITIONAL_DBG_RTL,
MEM_IF_NUM_RANKS => MEM_IF_NUM_RANKS,
MEM_IF_DQS_WIDTH => MEM_IF_DQS_WIDTH,
SIM_TIME_REDUCTIONS => SIM_TIME_REDUCTIONS,
ACK_SEVERITY => warning
)
port map(
clk => clk,
rst_n => rst_n,
ctl_init_success => ctl_init_success_int,
ctl_init_fail => ctl_init_fail_int,
ctl_recalibrate_req => ctl_recalibrate_req,
iram_status => iram_status,
iram_push_done => iram_push_done,
ctrl_op_rec => ctrl_broadcast,
admin_ctrl => admin_ctrl,
dgrb_ctrl => dgrb_ctrl,
dgwb_ctrl => dgwb_ctrl,
ctrl_iram_push => ctrl_iram_push,
ctl_cal_byte_lanes => ctl_cal_byte_lanes_r,
dgrb_ctrl_ac_nt_good => dgrb_ctrl_ac_nt_good,
int_ac_nt => int_ac_nt,
mmi_ctrl => mmi_ctrl,
ctrl_mmi => ctrl_mmi
);
-- ------------------------------------------------------------------
-- generate legacy rsu signals
-- ------------------------------------------------------------------
process(rst_n, clk)
begin
if rst_n = '0' then
rsu_multiple_valid_latencies_err <= '0';
rsu_grt_one_dvw_err <= '0';
rsu_no_dvw_err <= '0';
rsu_codvw_phase <= (others => '0');
rsu_codvw_size <= (others => '0');
rsu_read_latency <= (others => '0');
elsif rising_edge(clk) then
if dgrb_ctrl.command_err = '1' then
case to_integer(unsigned(dgrb_ctrl.command_result)) is
when C_ERR_RESYNC_NO_VALID_PHASES =>
rsu_no_dvw_err <= '1';
when C_ERR_RESYNC_MULTIPLE_EQUAL_WINDOWS =>
rsu_multiple_valid_latencies_err <= '1';
when others => null;
end case;
end if;
rsu_codvw_phase(dgrb_mmi.cal_codvw_phase'range) <= dgrb_mmi.cal_codvw_phase;
rsu_codvw_size(dgrb_mmi.cal_codvw_size'range) <= dgrb_mmi.cal_codvw_size;
rsu_read_latency <= seq_ctl_rlat_int;
rsu_grt_one_dvw_err <= dgrb_mmi.codvw_grt_one_dvw;
-- Reset the flag on a recal request :
if ( ctl_recalibrate_req = '1') then
rsu_grt_one_dvw_err <= '0';
rsu_no_dvw_err <= '0';
rsu_multiple_valid_latencies_err <= '0';
end if;
end if;
end process;
-- ---------------------------------------------------------------
-- top level multiplexing and ctrl functionality
-- ---------------------------------------------------------------
oct_delay_block : block
constant DEFAULT_OCT_DELAY_CONST : integer := - 2; -- higher increases delay by one mem_clk cycle, lower decreases delay by one mem_clk cycle.
constant DEFAULT_OCT_EXTEND : natural := 3;
-- Returns additive latency extracted from mr0 as a natural number.
function decode_cl(mr0 : in std_logic_vector(12 downto 0))
return natural is
variable v_cl : natural range 0 to 2**4 - 1;
begin
if MEM_IF_MEMTYPE = "DDR" or MEM_IF_MEMTYPE = "DDR2" then
v_cl := to_integer(unsigned(mr0(6 downto 4)));
elsif MEM_IF_MEMTYPE = "DDR3" then
v_cl := to_integer(unsigned(mr0(6 downto 4))) + 4;
else
report "Unsupported memory type " & MEM_IF_MEMTYPE severity failure;
end if;
return v_cl;
end function;
-- Returns additive latency extracted from mr1 as a natural number.
function decode_al(mr1 : in std_logic_vector(12 downto 0))
return natural is
variable v_al : natural range 0 to 2**4 - 1;
begin
if MEM_IF_MEMTYPE = "DDR" or MEM_IF_MEMTYPE = "DDR2" then
v_al := to_integer(unsigned(mr1(5 downto 3)));
elsif MEM_IF_MEMTYPE = "DDR3" then
v_al := to_integer(unsigned(mr1(4 downto 3)));
else
report "Unsupported memory type " & MEM_IF_MEMTYPE severity failure;
end if;
return v_al;
end function;
-- Returns cas write latency extracted from mr2 as a natural number.
function decode_cwl(
mr0 : in std_logic_vector(12 downto 0);
mr2 : in std_logic_vector(12 downto 0)
)
return natural is
variable v_cwl : natural range 0 to 2**4 - 1;
begin
if MEM_IF_MEMTYPE = "DDR" then
v_cwl := 1;
elsif MEM_IF_MEMTYPE = "DDR2" then
v_cwl := decode_cl(mr0) - 1;
elsif MEM_IF_MEMTYPE = "DDR3" then
v_cwl := to_integer(unsigned(mr2(4 downto 3))) + 5;
else
report "Unsupported memory type " & MEM_IF_MEMTYPE severity failure;
end if;
return v_cwl;
end function;
begin
-- Process to work out timings for OCT extension and delay with respect to doing_read. NOTE that it is calculated on the basis of CL, CWL, ctl_wlat
oct_delay_proc : process(clk, rst_n)
variable v_cl : natural range 0 to 2**4 - 1; -- Total read latency.
variable v_cwl : natural range 0 to 2**4 - 1; -- Total write latency
variable oct_delay : natural range 0 to 2**OCT_LAT_WIDTH - 1;
variable v_wlat : natural range 0 to 2**ADV_LAT_WIDTH - 1;
begin
if rst_n = '0' then
seq_oct_oct_delay <= (others => '0');
seq_oct_oct_extend <= std_logic_vector(to_unsigned(DEFAULT_OCT_EXTEND, OCT_LAT_WIDTH));
elsif rising_edge(clk) then
if ctl_init_success_int = '1' then
seq_oct_oct_extend <= std_logic_vector(to_unsigned(DEFAULT_OCT_EXTEND, OCT_LAT_WIDTH));
v_cl := decode_cl(admin_regs_status_rec.mr0);
v_cwl := decode_cwl(admin_regs_status_rec.mr0, admin_regs_status_rec.mr2);
if SIM_TIME_REDUCTIONS = 1 then
v_wlat := c_preset_cal_setup.wlat;
else
v_wlat := to_integer(unsigned(seq_ctl_wlat_int));
end if;
oct_delay := DWIDTH_RATIO * v_wlat / 2 + (v_cl - v_cwl) + DEFAULT_OCT_DELAY_CONST;
if not (FAMILYGROUP_ID = 2) then -- CIII doesn't support OCT
seq_oct_oct_delay <= std_logic_vector(to_unsigned(oct_delay, OCT_LAT_WIDTH));
end if;
else
seq_oct_oct_delay <= (others => '0');
seq_oct_oct_extend <= std_logic_vector(to_unsigned(DEFAULT_OCT_EXTEND, OCT_LAT_WIDTH));
end if;
end if;
end process;
end block;
-- control postamble protection override signal (seq_poa_protection_override_1x)
process(clk, rst_n)
variable v_warning_given : std_logic;
begin
if rst_n = '0' then
seq_poa_protection_override_1x <= '0';
v_warning_given := '0';
elsif rising_edge(clk) then
case ctrl_broadcast.command is
when cmd_rdv |
cmd_rrp_sweep |
cmd_rrp_seek |
cmd_prep_adv_rd_lat |
cmd_prep_adv_wr_lat => seq_poa_protection_override_1x <= '1';
when others => seq_poa_protection_override_1x <= '0';
end case;
end if;
end process;
ac_mux : block
constant c_mem_clk_disable_pipe_len : natural := 3;
signal seen_phy_init_complete : std_logic;
signal mem_clk_disable : std_logic_vector(c_mem_clk_disable_pipe_len - 1 downto 0);
signal ctrl_broadcast_r : t_ctrl_command;
begin
-- register ctrl_broadcast locally
-- #for speed and to reduce fan out
process (clk, rst_n)
begin
if rst_n = '0' then
ctrl_broadcast_r <= defaults;
elsif rising_edge(clk) then
ctrl_broadcast_r <= ctrl_broadcast;
end if;
end process;
-- multiplex mem interface control between admin, dgrb and dgwb
process(clk, rst_n)
variable v_seq_ac_mux : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
begin
if rst_n = '0' then
seq_rdv_doing_rd <= (others => '0');
seq_mem_clk_disable <= '1';
mem_clk_disable <= (others => '1');
seen_phy_init_complete <= '0';
seq_ac_addr <= (others => '0');
seq_ac_ba <= (others => '0');
seq_ac_cas_n <= (others => '1');
seq_ac_ras_n <= (others => '1');
seq_ac_we_n <= (others => '1');
seq_ac_cke <= (others => '0');
seq_ac_cs_n <= (others => '1');
seq_ac_odt <= (others => '0');
seq_ac_rst_n <= (others => '0');
elsif rising_edge(clk) then
seq_rdv_doing_rd <= seq_rdv_doing_rd_int;
seq_mem_clk_disable <= mem_clk_disable(c_mem_clk_disable_pipe_len-1);
mem_clk_disable(c_mem_clk_disable_pipe_len-1 downto 1) <= mem_clk_disable(c_mem_clk_disable_pipe_len-2 downto 0);
if dgwb_ac_access_req = '1' and dgb_ac_access_gnt = '1' then
v_seq_ac_mux := dgwb_ac;
elsif dgrb_ac_access_req = '1' and dgb_ac_access_gnt = '1' then
v_seq_ac_mux := dgrb_ac;
else
v_seq_ac_mux := admin_ac;
end if;
if ctl_recalibrate_req = '1' then
mem_clk_disable(0) <= '1';
seen_phy_init_complete <= '0';
elsif ctrl_broadcast_r.command = cmd_init_dram and ctrl_broadcast_r.command_req = '1' then
mem_clk_disable(0) <= '0';
seen_phy_init_complete <= '1';
end if;
if seen_phy_init_complete /= '1' then -- if not initialised the phy hold in reset
seq_ac_addr <= (others => '0');
seq_ac_ba <= (others => '0');
seq_ac_cas_n <= (others => '1');
seq_ac_ras_n <= (others => '1');
seq_ac_we_n <= (others => '1');
seq_ac_cke <= (others => '0');
seq_ac_cs_n <= (others => '1');
seq_ac_odt <= (others => '0');
seq_ac_rst_n <= (others => '0');
else
if enable_odt = '0' then
v_seq_ac_mux := mask(c_seq_addr_cmd_config, v_seq_ac_mux, odt, '0');
end if;
unpack_addr_cmd_vector (
c_seq_addr_cmd_config,
v_seq_ac_mux,
seq_ac_addr,
seq_ac_ba,
seq_ac_cas_n,
seq_ac_ras_n,
seq_ac_we_n,
seq_ac_cke,
seq_ac_cs_n,
seq_ac_odt,
seq_ac_rst_n);
end if;
end if;
end process;
end block;
-- register dgb_ac_access_gnt signal to ensure ODT set correctly in dgrb and dgwb prior to a read or write operation
process(clk, rst_n)
begin
if rst_n = '0' then
dgb_ac_access_gnt_r <= '0';
elsif rising_edge(clk) then
dgb_ac_access_gnt_r <= dgb_ac_access_gnt;
end if;
end process;
-- multiplex access request from dgrb/dgwb to admin block with checking for multiple accesses
process (dgrb_ac_access_req, dgwb_ac_access_req)
begin
dgb_ac_access_req <= '0';
if dgwb_ac_access_req = '1' and dgrb_ac_access_req = '1' then
report seq_report_prefix & "multiple accesses attempted from DGRB and DGWB to admin block via signals dg.b_ac_access_reg " severity failure;
elsif dgwb_ac_access_req = '1' or dgrb_ac_access_req = '1' then
dgb_ac_access_req <= '1';
end if;
end process;
rdv_poa_blk : block
-- signals to control static setup of ctl_rdata_valid signal for instant on mode:
constant c_static_rdv_offset : integer := c_preset_cal_setup.rdv_lat; -- required change in RDV latency (should always be > 0)
signal static_rdv_offset : natural range 0 to abs(c_static_rdv_offset); -- signal to count # RDV shifts
constant c_dly_rdv_set : natural := 7; -- delay between RDV shifts
signal dly_rdv_inc_dec : std_logic; -- 1 = inc, 0 = dec
signal rdv_set_delay : natural range 0 to c_dly_rdv_set; -- signal to delay RDV shifts
-- same for poa protection
constant c_static_poa_offset : integer := c_preset_cal_setup.poa_lat;
signal static_poa_offset : natural range 0 to abs(c_static_poa_offset);
constant c_dly_poa_set : natural := 7;
signal dly_poa_inc_dec : std_logic;
signal poa_set_delay : natural range 0 to c_dly_poa_set;
-- function to abstract increment or decrement checking
function set_inc_dec(offset : integer) return std_logic is
begin
if offset < 0 then
return '1';
else
return '0';
end if;
end function;
begin
-- register postamble and rdata_valid latencies
-- note: postamble unused for Cyclone-III
-- RDV
process(clk, rst_n)
begin
if rst_n = '0' then
if SIM_TIME_REDUCTIONS = 1 then
-- setup offset calc
static_rdv_offset <= abs(c_static_rdv_offset);
dly_rdv_inc_dec <= set_inc_dec(c_static_rdv_offset);
rdv_set_delay <= c_dly_rdv_set;
end if;
seq_rdata_valid_lat_dec <= '0';
seq_rdata_valid_lat_inc <= '0';
elsif rising_edge(clk) then
if SIM_TIME_REDUCTIONS = 1 then -- perform static setup of RDV signal
if ctl_recalibrate_req = '1' then -- second reset condition
-- setup offset calc
static_rdv_offset <= abs(c_static_rdv_offset);
dly_rdv_inc_dec <= set_inc_dec(c_static_rdv_offset);
rdv_set_delay <= c_dly_rdv_set;
else
if static_rdv_offset /= 0 and
rdv_set_delay = 0 then
seq_rdata_valid_lat_dec <= not dly_rdv_inc_dec;
seq_rdata_valid_lat_inc <= dly_rdv_inc_dec;
static_rdv_offset <= static_rdv_offset - 1;
rdv_set_delay <= c_dly_rdv_set;
else -- once conplete pass through internal signals
seq_rdata_valid_lat_dec <= seq_rdata_valid_lat_dec_int;
seq_rdata_valid_lat_inc <= seq_rdata_valid_lat_inc_int;
end if;
if rdv_set_delay /= 0 then
rdv_set_delay <= rdv_set_delay - 1;
end if;
end if;
else -- no static setup
seq_rdata_valid_lat_dec <= seq_rdata_valid_lat_dec_int;
seq_rdata_valid_lat_inc <= seq_rdata_valid_lat_inc_int;
end if;
end if;
end process;
-- count number of RDV adjustments for debug
process(clk, rst_n)
begin
if rst_n = '0' then
rdv_adjustments <= 0;
elsif rising_edge(clk) then
if seq_rdata_valid_lat_dec_int = '1' then
rdv_adjustments <= rdv_adjustments + 1;
end if;
if seq_rdata_valid_lat_inc_int = '1' then
if rdv_adjustments = 0 then
report seq_report_prefix & " read data valid adjustment wrap around detected - more increments than decrements" severity failure;
else
rdv_adjustments <= rdv_adjustments - 1;
end if;
end if;
end if;
end process;
-- POA protection
process(clk, rst_n)
begin
if rst_n = '0' then
if SIM_TIME_REDUCTIONS = 1 then
-- setup offset calc
static_poa_offset <= abs(c_static_poa_offset);
dly_poa_inc_dec <= set_inc_dec(c_static_poa_offset);
poa_set_delay <= c_dly_poa_set;
end if;
seq_poa_lat_dec_1x <= (others => '0');
seq_poa_lat_inc_1x <= (others => '0');
elsif rising_edge(clk) then
if SIM_TIME_REDUCTIONS = 1 then -- static setup
if ctl_recalibrate_req = '1' then -- second reset condition
-- setup offset calc
static_poa_offset <= abs(c_static_poa_offset);
dly_poa_inc_dec <= set_inc_dec(c_static_poa_offset);
poa_set_delay <= c_dly_poa_set;
else
if static_poa_offset /= 0 and
poa_set_delay = 0 then
seq_poa_lat_dec_1x <= (others => not(dly_poa_inc_dec));
seq_poa_lat_inc_1x <= (others => dly_poa_inc_dec);
static_poa_offset <= static_poa_offset - 1;
poa_set_delay <= c_dly_poa_set;
else
seq_poa_lat_inc_1x <= seq_poa_lat_inc_1x_int;
seq_poa_lat_dec_1x <= seq_poa_lat_dec_1x_int;
end if;
if poa_set_delay /= 0 then
poa_set_delay <= poa_set_delay - 1;
end if;
end if;
else -- no static setup
seq_poa_lat_inc_1x <= seq_poa_lat_inc_1x_int;
seq_poa_lat_dec_1x <= seq_poa_lat_dec_1x_int;
end if;
end if;
end process;
-- count POA protection adjustments for debug
process(clk, rst_n)
begin
if rst_n = '0' then
poa_adjustments <= 0;
elsif rising_edge(clk) then
if seq_poa_lat_dec_1x_int(0) = '1' then
poa_adjustments <= poa_adjustments + 1;
end if;
if seq_poa_lat_inc_1x_int(0) = '1' then
if poa_adjustments = 0 then
report seq_report_prefix & " postamble adjustment wrap around detected - more increments than decrements" severity failure;
else
poa_adjustments <= poa_adjustments - 1;
end if;
end if;
end if;
end process;
end block;
-- register output fail/success signals - avoiding optimisation out
process(clk, rst_n)
begin
if rst_n = '0' then
ctl_init_fail <= '0';
ctl_init_success <= '0';
elsif rising_edge(clk) then
ctl_init_fail <= ctl_init_fail_int;
ctl_init_success <= ctl_init_success_int;
end if;
end process;
-- ctl_cal_byte_lanes register
-- seq_rdp_reset_req_n - when ctl_recalibrate_req issued
process(clk,rst_n)
begin
if rst_n = '0' then
seq_rdp_reset_req_n <= '0';
ctl_cal_byte_lanes_r <= (others => '1');
elsif rising_edge(clk) then
ctl_cal_byte_lanes_r <= not ctl_cal_byte_lanes;
if ctl_recalibrate_req = '1' then
seq_rdp_reset_req_n <= '0';
else
if ctrl_broadcast.command = cmd_rrp_sweep or
SIM_TIME_REDUCTIONS = 1 then
seq_rdp_reset_req_n <= '1';
end if;
end if;
end if;
end process;
-- register 1t addr/cmd and odt latency outputs
process(clk, rst_n)
begin
if rst_n = '0' then
seq_ac_add_1t_ac_lat_internal <= '0';
seq_ac_add_1t_odt_lat_internal <= '0';
seq_ac_add_2t <= '0';
elsif rising_edge(clk) then
if SIM_TIME_REDUCTIONS = 1 then
seq_ac_add_1t_ac_lat_internal <= c_preset_cal_setup.ac_1t;
seq_ac_add_1t_odt_lat_internal <= c_preset_cal_setup.ac_1t;
else
seq_ac_add_1t_ac_lat_internal <= int_ac_nt(0);
seq_ac_add_1t_odt_lat_internal <= int_ac_nt(0);
end if;
seq_ac_add_2t <= '0';
end if;
end process;
-- override write datapath signal generation
process(dgwb_wdp_override, dgrb_wdp_override, ctl_init_success_int, ctl_init_fail_int)
begin
if ctl_init_success_int = '0' and ctl_init_fail_int = '0' then -- if calibrating
seq_wdp_ovride <= dgwb_wdp_override or dgrb_wdp_override;
else
seq_wdp_ovride <= '0';
end if;
end process;
-- output write/read latency (override with preset values when sim time reductions equals 1
seq_ctl_wlat <= std_logic_vector(to_unsigned(c_preset_cal_setup.wlat,ADV_LAT_WIDTH)) when SIM_TIME_REDUCTIONS = 1 else seq_ctl_wlat_int;
seq_ctl_rlat <= std_logic_vector(to_unsigned(c_preset_cal_setup.rlat,ADV_LAT_WIDTH)) when SIM_TIME_REDUCTIONS = 1 else seq_ctl_rlat_int;
process (clk, rst_n)
begin
if rst_n = '0' then
seq_pll_phs_shift_busy_r <= '0';
seq_pll_phs_shift_busy_ccd <= '0';
elsif rising_edge(clk) then
seq_pll_phs_shift_busy_r <= seq_pll_phs_shift_busy;
seq_pll_phs_shift_busy_ccd <= seq_pll_phs_shift_busy_r;
end if;
end process;
pll_ctrl: block
-- static resync setup variables for sim time reductions
signal static_rst_offset : natural range 0 to 2*PLL_STEPS_PER_CYCLE;
signal phs_shft_busy_1r : std_logic;
signal pll_set_delay : natural range 100 downto 0; -- wait 100 clock cycles for clk to be stable before setting resync phase
-- pll signal generation
signal mmi_pll_active : boolean;
signal seq_pll_phs_shift_busy_ccd_1t : std_logic;
begin
-- multiplex ppl interface between dgrb and mmi blocks
-- plus static setup of rsc phase to a known 'good' condition
process(clk,rst_n)
begin
if rst_n = '0' then
seq_pll_inc_dec_n <= '0';
seq_pll_start_reconfig <= '0';
seq_pll_select <= (others => '0');
dgrb_phs_shft_busy <= '0';
-- static resync setup variables for sim time reductions
if SIM_TIME_REDUCTIONS = 1 then
static_rst_offset <= c_preset_codvw_phase;
else
static_rst_offset <= 0;
end if;
phs_shft_busy_1r <= '0';
pll_set_delay <= 100;
elsif rising_edge(clk) then
dgrb_phs_shft_busy <= '0';
if static_rst_offset /= 0 and -- not finished decrementing
pll_set_delay = 0 and -- initial reset period over
SIM_TIME_REDUCTIONS = 1 then -- in reduce sim time mode (optimse logic away when not in this mode)
seq_pll_inc_dec_n <= '1';
seq_pll_start_reconfig <= '1';
seq_pll_select <= pll_resync_clk_index;
if seq_pll_phs_shift_busy_ccd = '1' then -- no metastability hardening needed in simulation
-- PLL phase shift started - so stop requesting a shift
seq_pll_start_reconfig <= '0';
end if;
if seq_pll_phs_shift_busy_ccd = '0' and phs_shft_busy_1r = '1' then
-- PLL phase shift finished - so proceed to flush the datapath
static_rst_offset <= static_rst_offset - 1;
seq_pll_start_reconfig <= '0';
end if;
phs_shft_busy_1r <= seq_pll_phs_shift_busy_ccd;
else
if ctrl_iram_push.active_block = ret_dgrb then
seq_pll_inc_dec_n <= dgrb_pll_inc_dec_n;
seq_pll_start_reconfig <= dgrb_pll_start_reconfig;
seq_pll_select <= dgrb_pll_select;
dgrb_phs_shft_busy <= seq_pll_phs_shift_busy_ccd;
else
seq_pll_inc_dec_n <= mmi_pll_inc_dec_n;
seq_pll_start_reconfig <= mmi_pll_start_reconfig;
seq_pll_select <= mmi_pll_select;
end if;
end if;
if pll_set_delay /= 0 then
pll_set_delay <= pll_set_delay - 1;
end if;
if ctl_recalibrate_req = '1' then
pll_set_delay <= 100;
end if;
end if;
end process;
-- generate mmi pll signals
process (clk, rst_n)
begin
if rst_n = '0' then
pll_mmi.pll_busy <= '0';
pll_mmi.err <= (others => '0');
mmi_pll_inc_dec_n <= '0';
mmi_pll_start_reconfig <= '0';
mmi_pll_select <= (others => '0');
mmi_pll_active <= false;
seq_pll_phs_shift_busy_ccd_1t <= '0';
elsif rising_edge(clk) then
if mmi_pll_active = true then
pll_mmi.pll_busy <= '1';
else
pll_mmi.pll_busy <= mmi_pll.pll_phs_shft_up_wc or mmi_pll.pll_phs_shft_dn_wc;
end if;
if pll_mmi.err = "00" and dgrb_pll_start_reconfig = '1' then
pll_mmi.err <= "01";
elsif pll_mmi.err = "00" and mmi_pll_active = true then
pll_mmi.err <= "10";
elsif pll_mmi.err = "00" and dgrb_pll_start_reconfig = '1' and mmi_pll_active = true then
pll_mmi.err <= "11";
end if;
if mmi_pll.pll_phs_shft_up_wc = '1' and mmi_pll_active = false then
mmi_pll_inc_dec_n <= '1';
mmi_pll_select <= std_logic_vector(to_unsigned(mmi_pll.pll_phs_shft_phase_sel,mmi_pll_select'length));
mmi_pll_active <= true;
elsif mmi_pll.pll_phs_shft_dn_wc = '1' and mmi_pll_active = false then
mmi_pll_inc_dec_n <= '0';
mmi_pll_select <= std_logic_vector(to_unsigned(mmi_pll.pll_phs_shft_phase_sel,mmi_pll_select'length));
mmi_pll_active <= true;
elsif seq_pll_phs_shift_busy_ccd_1t = '1' and seq_pll_phs_shift_busy_ccd = '0' then
mmi_pll_start_reconfig <= '0';
mmi_pll_active <= false;
elsif mmi_pll_active = true and mmi_pll_start_reconfig = '0' and seq_pll_phs_shift_busy_ccd = '0' then
mmi_pll_start_reconfig <= '1';
elsif seq_pll_phs_shift_busy_ccd_1t = '0' and seq_pll_phs_shift_busy_ccd = '1' then
mmi_pll_start_reconfig <= '0';
end if;
seq_pll_phs_shift_busy_ccd_1t <= seq_pll_phs_shift_busy_ccd;
end if;
end process;
end block; -- pll_ctrl
--synopsys synthesis_off
reporting : block
function pass_or_fail_report( cal_success : in std_logic;
cal_fail : in std_logic
) return string is
begin
if cal_success = '1' and cal_fail = '1' then
return "unknown state cal_fail and cal_success both high";
end if;
if cal_success = '1' then
return "PASSED";
end if;
if cal_fail = '1' then
return "FAILED";
end if;
return "calibration report run whilst sequencer is still calibrating";
end function;
function is_stage_disabled ( stage_name : in string;
stage_dis : in std_logic
) return string is
begin
if stage_dis = '0' then
return "";
else
return stage_name & " stage is disabled" & LF;
end if;
end function;
function disabled_stages ( capabilities : in std_logic_vector
) return string is
begin
return is_stage_disabled("all calibration", c_capabilities(c_hl_css_reg_cal_dis_bit)) &
is_stage_disabled("initialisation", c_capabilities(c_hl_css_reg_phy_initialise_dis_bit)) &
is_stage_disabled("DRAM initialisation", c_capabilities(c_hl_css_reg_init_dram_dis_bit)) &
is_stage_disabled("iram header write", c_capabilities(c_hl_css_reg_write_ihi_dis_bit)) &
is_stage_disabled("burst training pattern write", c_capabilities(c_hl_css_reg_write_btp_dis_bit)) &
is_stage_disabled("more training pattern (MTP) write", c_capabilities(c_hl_css_reg_write_mtp_dis_bit)) &
is_stage_disabled("check MTP pattern alignment calculation", c_capabilities(c_hl_css_reg_read_mtp_dis_bit)) &
is_stage_disabled("read resynch phase reset stage", c_capabilities(c_hl_css_reg_rrp_reset_dis_bit)) &
is_stage_disabled("read resynch phase sweep stage", c_capabilities(c_hl_css_reg_rrp_sweep_dis_bit)) &
is_stage_disabled("read resynch phase seek stage (set phase)", c_capabilities(c_hl_css_reg_rrp_seek_dis_bit)) &
is_stage_disabled("read data valid window setup", c_capabilities(c_hl_css_reg_rdv_dis_bit)) &
is_stage_disabled("postamble calibration", c_capabilities(c_hl_css_reg_poa_dis_bit)) &
is_stage_disabled("write latency timing calc", c_capabilities(c_hl_css_reg_was_dis_bit)) &
is_stage_disabled("advertise read latency", c_capabilities(c_hl_css_reg_adv_rd_lat_dis_bit)) &
is_stage_disabled("advertise write latency", c_capabilities(c_hl_css_reg_adv_wr_lat_dis_bit)) &
is_stage_disabled("write customer mode register settings", c_capabilities(c_hl_css_reg_prep_customer_mr_setup_dis_bit)) &
is_stage_disabled("tracking", c_capabilities(c_hl_css_reg_tracking_dis_bit));
end function;
function ac_nt_report( ac_nt : in std_logic_vector;
dgrb_ctrl_ac_nt_good : in std_logic;
preset_cal_setup : in t_preset_cal) return string
is
variable v_ac_nt : std_logic_vector(0 downto 0);
begin
if SIM_TIME_REDUCTIONS = 1 then
v_ac_nt(0) := preset_cal_setup.ac_1t;
if v_ac_nt(0) = '1' then
return "-- statically set address and command 1T delay: add 1T delay" & LF;
else
return "-- statically set address and command 1T delay: no 1T delay" & LF;
end if;
else
v_ac_nt(0) := ac_nt(0);
if dgrb_ctrl_ac_nt_good = '1' then
if v_ac_nt(0) = '1' then
return "-- chosen address and command 1T delay: add 1T delay" & LF;
else
return "-- chosen address and command 1T delay: no 1T delay" & LF;
end if;
else
return "-- no valid address and command phase chosen (calibration FAILED)" & LF;
end if;
end if;
end function;
function read_resync_report ( codvw_phase : in std_logic_vector;
codvw_size : in std_logic_vector;
ctl_rlat : in std_logic_vector;
ctl_wlat : in std_logic_vector;
preset_cal_setup : in t_preset_cal) return string
is
begin
if SIM_TIME_REDUCTIONS = 1 then
return "-- read resynch phase static setup (no calibration run) report:" & LF &
" -- statically set centre of data valid window phase : " & natural'image(preset_cal_setup.codvw_phase) & LF &
" -- statically set centre of data valid window size : " & natural'image(preset_cal_setup.codvw_size) & LF &
" -- statically set read latency (ctl_rlat) : " & natural'image(preset_cal_setup.rlat) & LF &
" -- statically set write latency (ctl_wlat) : " & natural'image(preset_cal_setup.wlat) & LF &
" -- note: this mode only works for simulation and sets resync phase" & LF &
" to a known good operating condition for no test bench" & LF &
" delays on mem_dq signal" & LF;
else
return "-- PHY read latency (ctl_rlat) is : " & natural'image(to_integer(unsigned(ctl_rlat))) & LF &
"-- address/command to PHY write latency (ctl_wlat) is : " & natural'image(to_integer(unsigned(ctl_wlat))) & LF &
"-- read resynch phase calibration report:" & LF &
" -- calibrated centre of data valid window phase : " & natural'image(to_integer(unsigned(codvw_phase))) & LF &
" -- calibrated centre of data valid window size : " & natural'image(to_integer(unsigned(codvw_size))) & LF;
end if;
end function;
function poa_rdv_adjust_report( poa_adjust : in natural;
rdv_adjust : in natural;
preset_cal_setup : in t_preset_cal) return string
is
begin
if SIM_TIME_REDUCTIONS = 1 then
return "Statically set poa and rdv (adjustments from reset value):" & LF &
"poa 'dec' adjustments = " & natural'image(preset_cal_setup.poa_lat) & LF &
"rdv 'dec' adjustments = " & natural'image(preset_cal_setup.rdv_lat) & LF;
else
return "poa 'dec' adjustments = " & natural'image(poa_adjust) & LF &
"rdv 'dec' adjustments = " & natural'image(rdv_adjust) & LF;
end if;
end function;
function calibration_report ( capabilities : in std_logic_vector;
cal_success : in std_logic;
cal_fail : in std_logic;
ctl_rlat : in std_logic_vector;
ctl_wlat : in std_logic_vector;
codvw_phase : in std_logic_vector;
codvw_size : in std_logic_vector;
ac_nt : in std_logic_vector;
dgrb_ctrl_ac_nt_good : in std_logic;
preset_cal_setup : in t_preset_cal;
poa_adjust : in natural;
rdv_adjust : in natural) return string
is
begin
return seq_report_prefix & " report..." & LF &
"-----------------------------------------------------------------------" & LF &
"-- **** ALTMEMPHY CALIBRATION has completed ****" & LF &
"-- Status:" & LF &
"-- calibration has : " & pass_or_fail_report(cal_success, cal_fail) & LF &
read_resync_report(codvw_phase, codvw_size, ctl_rlat, ctl_wlat, preset_cal_setup) &
ac_nt_report(ac_nt, dgrb_ctrl_ac_nt_good, preset_cal_setup) &
poa_rdv_adjust_report(poa_adjust, rdv_adjust, preset_cal_setup) &
disabled_stages(capabilities) &
"-----------------------------------------------------------------------";
end function;
begin
-- -------------------------------------------------------
-- calibration result reporting
-- -------------------------------------------------------
process(rst_n, clk)
variable v_reports_written : std_logic;
variable v_cal_request_r : std_logic;
variable v_rewrite_report : std_logic;
begin
if rst_n = '0' then
v_reports_written := '0';
v_cal_request_r := '0';
v_rewrite_report := '0';
elsif Rising_Edge(clk) then
if v_reports_written = '0' then
if ctl_init_success_int = '1' or ctl_init_fail_int = '1' then
v_reports_written := '1';
report calibration_report(c_capabilities,
ctl_init_success_int,
ctl_init_fail_int,
seq_ctl_rlat_int,
seq_ctl_wlat_int,
dgrb_mmi.cal_codvw_phase,
dgrb_mmi.cal_codvw_size,
int_ac_nt,
dgrb_ctrl_ac_nt_good,
c_preset_cal_setup,
poa_adjustments,
rdv_adjustments
) severity note;
end if;
end if;
-- if recalibrate request triggered watch for cal success / fail going low and re-trigger report writing
if ctl_recalibrate_req = '1' and v_cal_request_r = '0' then
v_rewrite_report := '1';
end if;
if v_rewrite_report = '1' and ctl_init_success_int = '0' and ctl_init_fail_int = '0' then
v_reports_written := '0';
v_rewrite_report := '0';
end if;
v_cal_request_r := ctl_recalibrate_req;
end if;
end process;
-- -------------------------------------------------------
-- capabilities vector reporting and coarse PHY setup sanity checks
-- -------------------------------------------------------
process(rst_n, clk)
variable reports_written : std_logic;
begin
if rst_n = '0' then
reports_written := '0';
elsif Rising_Edge(clk) then
if reports_written = '0' then
reports_written := '1';
if MEM_IF_MEMTYPE="DDR" or MEM_IF_MEMTYPE="DDR2" or MEM_IF_MEMTYPE="DDR3" then
if DWIDTH_RATIO = 2 or DWIDTH_RATIO = 4 then
report disabled_stages(c_capabilities) severity note;
else
report seq_report_prefix & "unsupported rate for non-levelling AFI PHY sequencer - only full- or half-rate supported" severity warning;
end if;
else
report seq_report_prefix & "memory type " & MEM_IF_MEMTYPE & " is not supported in non-levelling AFI PHY sequencer" severity failure;
end if;
end if;
end if;
end process;
end block; -- reporting
--synopsys synthesis_on
end architecture struct;
| gpl-3.0 | 2cc627db9296c8ad292e3611463a468c | 0.441458 | 4.432368 | false | false | false | false |
markusC64/1541ultimate2 | fpga/nios_tester/nios_tester/synthesis/submodules/avalon_to_mem32_bridge.vhd | 4 | 2,210 | -------------------------------------------------------------------------------
-- Title : avalon_to_mem32_bridge
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This module bridges the avalon bus to I/O
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--library work;
-- use work.mem_bus_pkg.all;
entity avalon_to_mem32_bridge is
generic (
g_tag : std_logic_vector(7 downto 0) := X"5B" );
port (
clock : in std_logic;
reset : in std_logic;
-- 32 bits Avalon bus interface
avs_read : in std_logic;
avs_write : in std_logic;
avs_address : in std_logic_vector(25 downto 0);
avs_writedata : in std_logic_vector(31 downto 0);
avs_byteenable : in std_logic_vector(3 downto 0);
avs_waitrequest : out std_logic;
avs_readdata : out std_logic_vector(31 downto 0);
avs_readdatavalid : out std_logic;
mem_req_read_writen : out std_logic;
mem_req_request : out std_logic;
mem_req_address : out std_logic_vector(25 downto 0);
mem_req_wdata : out std_logic_vector(31 downto 0);
mem_req_byte_en : out std_logic_vector(3 downto 0);
mem_req_tag : out std_logic_vector(7 downto 0);
mem_resp_rack_tag : in std_logic_vector(7 downto 0);
mem_resp_dack_tag : in std_logic_vector(7 downto 0);
mem_resp_data : in std_logic_vector(31 downto 0) );
end entity;
architecture rtl of avalon_to_mem32_bridge is
begin
avs_waitrequest <= '0' when (mem_resp_rack_tag = g_tag) else '1';
avs_readdatavalid <= '1' when (mem_resp_dack_tag = g_tag) else '0';
avs_readdata <= mem_resp_data;
mem_req_read_writen <= avs_read;
mem_req_request <= avs_read or avs_write;
mem_req_address <= avs_address;
mem_req_wdata <= avs_writedata;
mem_req_byte_en <= avs_byteenable;
mem_req_tag <= g_tag;
end architecture;
| gpl-3.0 | 3fd5e3947be5700004d1b00abd0ea094 | 0.529864 | 3.547352 | false | false | false | false |
markusC64/1541ultimate2 | fpga/nios_c5/nios/synthesis/nios_rst_controller.vhd | 2 | 9,035 | -- nios_rst_controller.vhd
-- Generated using ACDS version 15.1 185
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nios_rst_controller is
generic (
NUM_RESET_INPUTS : integer := 2;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 0;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := '0'; -- reset_in0.reset
reset_in1 : in std_logic := '0'; -- reset_in1.reset
clk : in std_logic := '0'; -- clk.clk
reset_out : out std_logic; -- reset_out.reset
reset_in10 : in std_logic := '0';
reset_in11 : in std_logic := '0';
reset_in12 : in std_logic := '0';
reset_in13 : in std_logic := '0';
reset_in14 : in std_logic := '0';
reset_in15 : in std_logic := '0';
reset_in2 : in std_logic := '0';
reset_in3 : in std_logic := '0';
reset_in4 : in std_logic := '0';
reset_in5 : in std_logic := '0';
reset_in6 : in std_logic := '0';
reset_in7 : in std_logic := '0';
reset_in8 : in std_logic := '0';
reset_in9 : in std_logic := '0';
reset_req : out std_logic;
reset_req_in0 : in std_logic := '0';
reset_req_in1 : in std_logic := '0';
reset_req_in10 : in std_logic := '0';
reset_req_in11 : in std_logic := '0';
reset_req_in12 : in std_logic := '0';
reset_req_in13 : in std_logic := '0';
reset_req_in14 : in std_logic := '0';
reset_req_in15 : in std_logic := '0';
reset_req_in2 : in std_logic := '0';
reset_req_in3 : in std_logic := '0';
reset_req_in4 : in std_logic := '0';
reset_req_in5 : in std_logic := '0';
reset_req_in6 : in std_logic := '0';
reset_req_in7 : in std_logic := '0';
reset_req_in8 : in std_logic := '0';
reset_req_in9 : in std_logic := '0'
);
end entity nios_rst_controller;
architecture rtl of nios_rst_controller is
component altera_reset_controller is
generic (
NUM_RESET_INPUTS : integer := 6;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 0;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := 'X'; -- reset
reset_in1 : in std_logic := 'X'; -- reset
clk : in std_logic := 'X'; -- clk
reset_out : out std_logic; -- reset
reset_req : out std_logic; -- reset_req
reset_req_in0 : in std_logic := 'X'; -- reset_req
reset_req_in1 : in std_logic := 'X'; -- reset_req
reset_in2 : in std_logic := 'X'; -- reset
reset_req_in2 : in std_logic := 'X'; -- reset_req
reset_in3 : in std_logic := 'X'; -- reset
reset_req_in3 : in std_logic := 'X'; -- reset_req
reset_in4 : in std_logic := 'X'; -- reset
reset_req_in4 : in std_logic := 'X'; -- reset_req
reset_in5 : in std_logic := 'X'; -- reset
reset_req_in5 : in std_logic := 'X'; -- reset_req
reset_in6 : in std_logic := 'X'; -- reset
reset_req_in6 : in std_logic := 'X'; -- reset_req
reset_in7 : in std_logic := 'X'; -- reset
reset_req_in7 : in std_logic := 'X'; -- reset_req
reset_in8 : in std_logic := 'X'; -- reset
reset_req_in8 : in std_logic := 'X'; -- reset_req
reset_in9 : in std_logic := 'X'; -- reset
reset_req_in9 : in std_logic := 'X'; -- reset_req
reset_in10 : in std_logic := 'X'; -- reset
reset_req_in10 : in std_logic := 'X'; -- reset_req
reset_in11 : in std_logic := 'X'; -- reset
reset_req_in11 : in std_logic := 'X'; -- reset_req
reset_in12 : in std_logic := 'X'; -- reset
reset_req_in12 : in std_logic := 'X'; -- reset_req
reset_in13 : in std_logic := 'X'; -- reset
reset_req_in13 : in std_logic := 'X'; -- reset_req
reset_in14 : in std_logic := 'X'; -- reset
reset_req_in14 : in std_logic := 'X'; -- reset_req
reset_in15 : in std_logic := 'X'; -- reset
reset_req_in15 : in std_logic := 'X' -- reset_req
);
end component altera_reset_controller;
begin
rst_controller : component altera_reset_controller
generic map (
NUM_RESET_INPUTS => NUM_RESET_INPUTS,
OUTPUT_RESET_SYNC_EDGES => OUTPUT_RESET_SYNC_EDGES,
SYNC_DEPTH => SYNC_DEPTH,
RESET_REQUEST_PRESENT => RESET_REQUEST_PRESENT,
RESET_REQ_WAIT_TIME => RESET_REQ_WAIT_TIME,
MIN_RST_ASSERTION_TIME => MIN_RST_ASSERTION_TIME,
RESET_REQ_EARLY_DSRT_TIME => RESET_REQ_EARLY_DSRT_TIME,
USE_RESET_REQUEST_IN0 => USE_RESET_REQUEST_IN0,
USE_RESET_REQUEST_IN1 => USE_RESET_REQUEST_IN1,
USE_RESET_REQUEST_IN2 => USE_RESET_REQUEST_IN2,
USE_RESET_REQUEST_IN3 => USE_RESET_REQUEST_IN3,
USE_RESET_REQUEST_IN4 => USE_RESET_REQUEST_IN4,
USE_RESET_REQUEST_IN5 => USE_RESET_REQUEST_IN5,
USE_RESET_REQUEST_IN6 => USE_RESET_REQUEST_IN6,
USE_RESET_REQUEST_IN7 => USE_RESET_REQUEST_IN7,
USE_RESET_REQUEST_IN8 => USE_RESET_REQUEST_IN8,
USE_RESET_REQUEST_IN9 => USE_RESET_REQUEST_IN9,
USE_RESET_REQUEST_IN10 => USE_RESET_REQUEST_IN10,
USE_RESET_REQUEST_IN11 => USE_RESET_REQUEST_IN11,
USE_RESET_REQUEST_IN12 => USE_RESET_REQUEST_IN12,
USE_RESET_REQUEST_IN13 => USE_RESET_REQUEST_IN13,
USE_RESET_REQUEST_IN14 => USE_RESET_REQUEST_IN14,
USE_RESET_REQUEST_IN15 => USE_RESET_REQUEST_IN15,
ADAPT_RESET_REQUEST => ADAPT_RESET_REQUEST
)
port map (
reset_in0 => reset_in0, -- reset_in0.reset
reset_in1 => reset_in1, -- reset_in1.reset
clk => clk, -- clk.clk
reset_out => reset_out, -- reset_out.reset
reset_req => open, -- (terminated)
reset_req_in0 => '0', -- (terminated)
reset_req_in1 => '0', -- (terminated)
reset_in2 => '0', -- (terminated)
reset_req_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_req_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_req_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_req_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_req_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_req_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_req_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_req_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_req_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_req_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_req_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_req_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_req_in14 => '0', -- (terminated)
reset_in15 => '0', -- (terminated)
reset_req_in15 => '0' -- (terminated)
);
end architecture rtl; -- of nios_rst_controller
| gpl-3.0 | 9354b8525936daaf85e5194b9cfc6ea0 | 0.548091 | 2.724668 | false | false | false | false |
xiadz/oscilloscope | src/tests/test_trace_pixgen.vhd | 1 | 6,474 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:17:19 05/28/2011
-- Design Name:
-- Module Name: /home/xiadz/prog/fpga/oscilloscope/test_trace_pixgen.vhd
-- Project Name: oscilloscope
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: trace_pixgen
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.types.all;
ENTITY test_trace_pixgen IS
END test_trace_pixgen;
ARCHITECTURE behavior OF test_trace_pixgen IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT trace_pixgen
PORT(
nrst : IN std_logic;
clk108 : IN std_logic;
segment : IN integer range 0 to 15;
segment_change : IN std_logic;
subsegment : IN integer range 0 to 3;
subsegment_change : IN std_logic;
line : IN integer range 0 to 15;
line_change : IN std_logic;
column : IN integer range 0 to 1279;
column_change : IN std_logic;
page_change : IN std_logic;
active_pixgen_source : IN PIXGEN_SOURCE_T;
doutb : IN std_logic_vector(8 downto 0);
addrb : OUT std_logic_vector(12 downto 0);
vout : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal nrst : std_logic := '0';
signal clk108 : std_logic := '0';
signal segment : integer range 0 to 15 := 0;
signal segment_change : std_logic := '0';
signal subsegment : integer range 0 to 3 := 0;
signal subsegment_change : std_logic := '0';
signal line : integer range 0 to 15 := 0;
signal line_change : std_logic := '0';
signal column : integer range 0 to 1279 := 0;
signal column_change : std_logic := '0';
signal page_change : std_logic := '0';
signal active_pixgen_source : PIXGEN_SOURCE_T := TRACE_PIXGEN_T;
signal doutb : std_logic_vector(8 downto 0) := (others => '0');
--Outputs
signal addrb : std_logic_vector(12 downto 0);
signal vout : std_logic_vector(7 downto 0);
-- Clock period definitions
constant clk108_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: trace_pixgen PORT MAP (
nrst => nrst,
clk108 => clk108,
segment => segment,
segment_change => segment_change,
subsegment => subsegment,
subsegment_change => subsegment_change,
line => line,
line_change => line_change,
column => column,
column_change => column_change,
page_change => page_change,
active_pixgen_source => active_pixgen_source,
doutb => doutb,
addrb => addrb,
vout => vout
);
-- Clock process definitions
clk108_process :process
begin
clk108 <= '0';
wait for clk108_period/2;
clk108 <= '1';
wait for clk108_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
nrst <= '0';
wait for 100 ns;
nrst <= '1';
wait for clk108_period*10;
while true loop
for x_segment in 0 to 15 loop
for x_subsegment in 0 to 3 loop
for x_line in 0 to 15 loop
if x_segment = 14 or x_segment = 15 then
active_pixgen_source <= SETTINGS_PIXGEN_T;
else
if x_subsegment = 3 then
active_pixgen_source <= TIME_BASE_PIXGEN_T;
else
active_pixgen_source <= TRACE_PIXGEN_T;
end if;
end if;
for x_column in 0 to 1279 loop
column_change <= '1';
segment <= x_segment;
subsegment <= x_subsegment;
line <= x_line;
column <= x_column;
if x_column = 0 then
line_change <= '1';
if x_line = 0 then
subsegment_change <= '1';
if x_subsegment = 0 then
segment_change <= '1';
if x_segment = 0 then
page_change <= '1';
else
page_change <= '0';
end if;
else
segment_change <= '0';
page_change <= '0';
end if;
else
subsegment_change <= '0';
segment_change <= '0';
page_change <= '0';
end if;
else
line_change <= '0';
subsegment_change <= '0';
segment_change <= '0';
page_change <= '0';
end if;
wait for clk108_period;
end loop;
column_change <= '0';
active_pixgen_source <= BLANK_PIXGEN_T;
wait for clk108_period * 1000;
end loop;
end loop;
end loop;
wait for clk108_period * 10000;
end loop;
wait;
end process;
END;
| mit | 272cd869640fb42094583e7ad59f0bbb | 0.455205 | 4.660907 | false | true | false | false |
fpgaddicted/5bit-shift-register-structural- | TOPLEVEL.vhd | 1 | 3,142 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: Stefan Naco
--
-- Create Date: 04:18:26 04/11/2017
-- Design Name:
-- Module Name: TOPLEVEL - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity TOPLEVEL is
Port ( clk_i : in STD_LOGIC;
toggle : in STD_LOGIC;
anodes : out STD_LOGIC_VECTOR (3 downto 0);
disp : out STD_LOGIC_VECTOR (0 to 7);
leds_data : out STD_LOGIC_VECTOR (4 downto 0);
led_p: out STD_LOGIC;
ledC : out STD_LOGIC;
carry_optional : out STD_LOGIC;
reset : in STD_LOGIC;
opcode : in STD_LOGIC_VECTOR (2 downto 0);
data : in STD_LOGIC_VECTOR (4 downto 0);
clear : in STD_LOGIC);
end TOPLEVEL;
architecture PORTMAP of TOPLEVEL is
COMPONENT clk_controller IS
PORT ( clk : in STD_LOGIC;
toggle : in STD_LOGIC;
reset : in STD_LOGIC;
clk_o : out STD_LOGIC);
END COMPONENT;
COMPONENT display_controller IS
PORT ( seg7 : out STD_LOGIC_VECTOR (0 to 7);
clk : in STD_LOGIC;
opcode : in STD_LOGIC_VECTOR (2 downto 0);
reset : in STD_LOGIC;
anodes : out STD_LOGIC_VECTOR (3 downto 0));
END COMPONENT;
COMPONENT shiftregister_5bit IS
PORT ( sel : in STD_LOGIC_VECTOR (2 downto 0);
A : out STD_LOGIC_VECTOR (4 downto 0);
clk : in STD_LOGIC;
C : out STD_LOGIC;
reset : in STD_LOGIC;
I : in STD_LOGIC_VECTOR (4 downto 0));
END COMPONENT;
COMPONENT debounce IS
PORT ( clk : in STD_LOGIC;
button : in STD_LOGIC;
result : out STD_LOGIC);
END COMPONENT;
signal reg_bus : std_logic_vector (4 downto 0);
signal clk1,t_p : std_logic;
signal command : std_logic_vector (2 downto 0);
begin
segment7 : display_controller PORT MAP(
anodes => anodes,
seg7 => disp,
opcode => command,
clk => clk_i,
reset => reset
);
cp : clk_controller PORT MAP(
clk => clk_i,
toggle => t_p,
reset => reset,
clk_o => clk1
);
reg : shiftregister_5bit PORT MAP(
sel => command,
A => reg_bus,
clk => clk1,
reset => clear,
I => data,
C => carry_optional
);
debA :debounce PORT MAP (
clk => clk_i,
button => toggle,
result => t_p
);
leds_data <= reg_bus;
command <= opcode;
ledC <= clk1;
led_p <= t_p;
end PORTMAP ;
| gpl-3.0 | d04bb1d61fc8459f86ec29e9742cfa5a | 0.537237 | 3.603211 | false | false | false | false |
markusC64/1541ultimate2 | fpga/io/rmii/vhdl_sim/eth_filter_tb.vhd | 1 | 9,806 | -------------------------------------------------------------------------------
-- Title : eth_filter_tb
-- Author : Gideon Zweijtzer ([email protected])
-------------------------------------------------------------------------------
-- Description: Testbench for eth_filter
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.io_bus_bfm_pkg.all;
use work.block_bus_pkg.all;
use work.mem_bus_pkg.all;
entity eth_filter_tb is
end entity;
architecture testcase of eth_filter_tb is
signal clock : std_logic := '0'; -- 50 MHz reference clock
signal reset : std_logic;
signal io_clock : std_logic := '0'; -- 66 MHz reference clock
signal io_reset : std_logic;
signal rmii_crs_dv : std_logic;
signal rmii_rxd : std_logic_vector(1 downto 0);
signal rmii_tx_en : std_logic;
signal rmii_txd : std_logic_vector(1 downto 0);
signal eth_rx_data : std_logic_vector(7 downto 0);
signal eth_rx_sof : std_logic;
signal eth_rx_eof : std_logic;
signal eth_rx_valid : std_logic;
signal eth_tx_data : std_logic_vector(7 downto 0);
signal eth_tx_sof : std_logic;
signal eth_tx_eof : std_logic;
signal eth_tx_valid : std_logic;
signal eth_tx_ready : std_logic;
signal ten_meg_mode : std_logic;
signal io_req : t_io_req;
signal io_resp : t_io_resp;
signal io_req_free : t_io_req;
signal io_resp_free : t_io_resp;
signal io_req_filt : t_io_req;
signal io_resp_filt : t_io_resp;
signal io_irq : std_logic;
signal alloc_req : std_logic := '0';
signal alloc_resp : t_alloc_resp;
signal used_req : t_used_req;
signal used_resp : std_logic;
signal mem_req : t_mem_req_32;
signal mem_resp : t_mem_resp_32 := c_mem_resp_32_init;
type t_byte_array is array (natural range <>) of std_logic_vector(7 downto 0);
constant c_frame_with_crc : t_byte_array := (
X"00", X"0A", X"E6", X"F0", X"05", X"A3", X"00", X"12", X"34", X"56", X"78", X"90", X"08", X"00", X"45", X"00",
X"00", X"30", X"B3", X"FE", X"00", X"00", X"80", X"11", X"72", X"BA", X"0A", X"00", X"00", X"03", X"0A", X"00",
X"00", X"02", X"04", X"00", X"04", X"00", X"00", X"1C", X"89", X"4D", X"00", X"01", X"02", X"03", X"04", X"05",
X"06", X"07", X"08", X"09", X"0A", X"0B", X"0C", X"0D", X"0E", X"0F", X"10", X"11", X"12", X"13"
-- , X"7A", X"D5", X"6B", X"B3"
);
procedure io_write_long(variable io : inout p_io_bus_bfm_object; addr : natural; data : std_logic_vector(31 downto 0)) is
begin
io_write(io, to_unsigned(addr+0, 20), data(07 downto 00));
io_write(io, to_unsigned(addr+1, 20), data(15 downto 08));
io_write(io, to_unsigned(addr+2, 20), data(23 downto 16));
io_write(io, to_unsigned(addr+3, 20), data(31 downto 24));
end procedure;
procedure io_write(variable io : inout p_io_bus_bfm_object; addr : natural; data : std_logic_vector(7 downto 0)) is
begin
io_write(io, to_unsigned(addr, 20), data);
end procedure;
procedure io_read(variable io : inout p_io_bus_bfm_object; addr : natural; data : out std_logic_vector(7 downto 0)) is
begin
io_read(io, to_unsigned(addr, 20), data);
end procedure;
procedure io_read_word(variable io : inout p_io_bus_bfm_object; addr : natural; data : out std_logic_vector(15 downto 0)) is
begin
io_read(io, to_unsigned(addr, 20), data(7 downto 0));
io_read(io, to_unsigned(addr+1, 20), data(15 downto 8));
end procedure;
begin
clock <= not clock after 10 ns;
reset <= '1', '0' after 100 ns;
io_clock <= not io_clock after 8 ns;
io_reset <= '1', '0' after 100 ns;
i_rmii: entity work.rmii_transceiver
port map (
clock => clock,
reset => reset,
rmii_crs_dv => rmii_crs_dv,
rmii_rxd => rmii_rxd,
rmii_tx_en => rmii_tx_en,
rmii_txd => rmii_txd,
eth_rx_data => eth_rx_data,
eth_rx_sof => eth_rx_sof,
eth_rx_eof => eth_rx_eof,
eth_rx_valid => eth_rx_valid,
eth_tx_data => eth_tx_data,
eth_tx_sof => eth_tx_sof,
eth_tx_eof => eth_tx_eof,
eth_tx_valid => eth_tx_valid,
eth_tx_ready => eth_tx_ready,
ten_meg_mode => ten_meg_mode
);
rmii_crs_dv <= rmii_tx_en;
rmii_rxd <= rmii_txd;
test: process
variable io : p_io_bus_bfm_object;
variable i : natural;
begin
eth_tx_data <= X"00";
eth_tx_sof <= '0';
eth_tx_eof <= '0';
eth_tx_valid <= '0';
ten_meg_mode <= '0';
wait until reset = '0';
bind_io_bus_bfm("io", io);
io_write_long(io, 0, X"01200000");
-- insert some free blocks
for x in 1 to 10 loop
io_write(io, 4, std_logic_vector(to_unsigned(x, 8)));
end loop;
-- configure filter
io_write(io, 256, c_frame_with_crc(0));
io_write(io, 257, c_frame_with_crc(1));
io_write(io, 258, c_frame_with_crc(2));
io_write(io, 259, c_frame_with_crc(3));
io_write(io, 260, c_frame_with_crc(4));
io_write(io, 261, c_frame_with_crc(5));
for x in 0 to 61 loop
wait until clock = '1';
i := 0;
L1: loop
wait until clock = '1';
if eth_tx_valid = '0' or eth_tx_ready = '1' then
if eth_tx_eof = '1' then
eth_tx_eof <= '0';
eth_tx_valid <= '0';
eth_tx_data <= X"00";
exit L1;
else
eth_tx_data <= c_frame_with_crc(i);
eth_tx_valid <= '1';
if i = c_frame_with_crc'left then
eth_tx_sof <= '1';
else
eth_tx_sof <= '0';
end if;
if (i+x) = c_frame_with_crc'right then
eth_tx_eof <= '1';
else
eth_tx_eof <= '0';
end if;
i := i + 1;
end if;
end if;
end loop;
if x > 9 then
-- io_write(io, 4, std_logic_vector(to_unsigned(x+16, 8)));
end if;
end loop;
wait;
end process;
i_bfm: entity work.io_bus_bfm
generic map ("io")
port map (
clock => io_clock,
req => io_req,
resp => io_resp
);
i_split: entity work.io_bus_splitter
generic map (
g_range_lo => 8,
g_range_hi => 9,
g_ports => 2
)
port map (
clock => io_clock,
req => io_req,
resp => io_resp,
reqs(1) => io_req_filt,
reqs(0) => io_req_free,
resps(1) => io_resp_filt,
resps(0) => io_resp_free
);
i_mut: entity work.eth_filter
port map (
clock => io_clock,
reset => io_reset,
io_req => io_req_filt,
io_resp => io_resp_filt,
alloc_req => alloc_req,
alloc_resp => alloc_resp,
used_req => used_req,
used_resp => used_resp,
mem_req => mem_req,
mem_resp => mem_resp,
eth_clock => clock,
eth_reset => reset,
eth_rx_data => eth_rx_data,
eth_rx_sof => eth_rx_sof,
eth_rx_eof => eth_rx_eof,
eth_rx_valid => eth_rx_valid );
i_free: entity work.free_queue
port map (
clock => io_clock,
reset => io_reset,
alloc_req => alloc_req,
alloc_resp => alloc_resp,
used_req => used_req,
used_resp => used_resp,
io_req => io_req_free,
io_resp => io_resp_free,
io_irq => io_irq
);
process(io_clock)
variable c : integer := 0;
begin
if rising_edge(io_clock) then
if mem_req.request = '1' then
c := c + 1;
end if;
if c = 4 then
mem_resp.rack <= '1';
mem_resp.rack_tag <= mem_req.tag;
c := 0;
else
mem_resp.rack <= '0';
mem_resp.rack_tag <= X"00";
end if;
end if;
end process;
process
variable io : p_io_bus_bfm_object;
variable data : std_logic_vector(7 downto 0);
variable id : std_logic_vector(7 downto 0);
variable data16 : std_logic_vector(15 downto 0);
begin
wait until io_reset = '0';
bind_io_bus_bfm("io", io);
while true loop
if io_irq /= '1' then
wait until io_irq = '1';
end if;
io_read(io, 15, data);
assert data(0) = '1' report "Expected an allocated block to be available";
io_read(io, 8, id);
io_read_word(io, 10, data16);
io_write(io, 15, X"00"); -- pop!
io_read(io, 15, data);
assert data(0) = '0' report "Expected no more allocated blocks to be available";
io_write(io, 4, id); -- re-add
end loop;
end process;
end architecture;
| gpl-3.0 | 9501c63200564c9d74031bad56f604bf | 0.467673 | 3.315078 | false | false | false | false |
trondd/mkjpeg | tb/vhdl/HostBFM.vhd | 1 | 16,231 | -------------------------------------------------------------------------------
-- File Name : HostBFM.vhd
--
-- Project : JPEG_ENC
--
-- Module : HostBFM
--
-- Content : Host BFM (Xilinx OPB v2.1)
--
-- Description :
--
-- Spec. :
--
-- Author : Michal Krepa
--
-------------------------------------------------------------------------------
-- History :
-- 20090301: (MK): Initial Creation.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use IEEE.STD_LOGIC_TEXTIO.ALL;
library STD;
use STD.TEXTIO.ALL;
library work;
use work.GPL_V2_Image_Pkg.ALL;
use WORK.MDCT_PKG.all;
use WORK.MDCTTB_PKG.all;
use work.JPEG_PKG.all;
entity HostBFM is
port
(
CLK : in std_logic;
RST : in std_logic;
-- OPB
OPB_ABus : out std_logic_vector(31 downto 0);
OPB_BE : out std_logic_vector(3 downto 0);
OPB_DBus_in : out std_logic_vector(31 downto 0);
OPB_RNW : out std_logic;
OPB_select : out std_logic;
OPB_DBus_out : in std_logic_vector(31 downto 0);
OPB_XferAck : in std_logic;
OPB_retry : in std_logic;
OPB_toutSup : in std_logic;
OPB_errAck : in std_logic;
-- HOST DATA
iram_wdata : out std_logic_vector(C_PIXEL_BITS-1 downto 0);
iram_wren : out std_logic;
fifo_almost_full : in std_logic;
sim_done : out std_logic
);
end entity HostBFM;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ARCHITECTURE ------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture RTL of HostBFM is
signal num_comps : integer;
signal addr_inc : integer := 0;
-------------------------------------------------------------------------------
-- Architecture: begin
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------
-- code
-------------------------------------------------------------------
p_code : process
-----------------------------------------------------------------
-- HOST WRITE
-----------------------------------------------------------------
procedure host_write
(
signal clk : in std_logic;
constant C_ADDR : in unsigned(31 downto 0);
constant C_WDATA : in unsigned(31 downto 0);
signal OPB_ABus : out std_logic_vector(31 downto 0);
signal OPB_BE : out std_logic_vector(3 downto 0);
signal OPB_DBus_in : out std_logic_vector(31 downto 0);
signal OPB_RNW : out std_logic;
signal OPB_select : out std_logic;
signal OPB_XferAck : in std_logic
) is
begin
OPB_ABus <= (others => '0');
OPB_BE <= (others => '0');
OPB_DBus_in <= (others => '0');
OPB_RNW <= '0';
OPB_select <= '0';
wait until rising_edge(clk);
OPB_select <= '1';
OPB_ABus <= std_logic_vector(C_ADDR);
OPB_RNW <= '0';
OPB_BE <= X"F";
OPB_DBus_in <= std_logic_vector(C_WDATA);
wait until rising_edge(clk);
while OPB_XferAck /= '1' loop
wait until rising_edge(clk);
end loop;
OPB_ABus <= (others => '0');
OPB_BE <= (others => '0');
OPB_DBus_in <= (others => '0');
OPB_RNW <= '0';
OPB_select <= '0';
assert false
report CR&"Host write access, address = " & HexImage(C_ADDR) & ",data written = " & HexImage(C_WDATA) &CR
severity note;
wait until rising_edge(clk);
end procedure host_write;
-----------------------------------------------------------------
-- HOST READ
-----------------------------------------------------------------
procedure host_read
(
signal clk : in std_logic;
constant C_ADDR : in unsigned(31 downto 0);
variable RDATA : out unsigned(31 downto 0);
signal OPB_ABus : out std_logic_vector(31 downto 0);
signal OPB_BE : out std_logic_vector(3 downto 0);
signal OPB_DBus_out : in std_logic_vector(31 downto 0);
signal OPB_RNW : out std_logic;
signal OPB_select : out std_logic;
signal OPB_XferAck : in std_logic
)
is
variable data_r : std_logic_vector(31 downto 0);
begin
OPB_ABus <= (others => '0');
OPB_BE <= (others => '0');
OPB_DBus_in <= (others => '0');
OPB_RNW <= '0';
OPB_select <= '0';
wait until rising_edge(clk);
OPB_select <= '1';
OPB_ABus <= std_logic_vector(C_ADDR);
OPB_RNW <= '1';
OPB_BE <= X"F";
wait until rising_edge(clk);
while OPB_XferAck /= '1' loop
wait until rising_edge(clk);
end loop;
RDATA := unsigned(OPB_DBus_out);
data_r := OPB_DBus_out;
OPB_ABus <= (others => '0');
OPB_BE <= (others => '0');
OPB_DBus_in <= (others => '0');
OPB_RNW <= '0';
OPB_select <= '0';
assert false
report CR&"Host read access, address = " & HexImage(C_ADDR) & ",data read = " & HexImage(data_r) &CR
severity note;
wait until rising_edge(clk);
end procedure host_read;
--------------------------------------
-- read text image data
--------------------------------------
procedure read_image is
file infile : TEXT open read_mode is "test.txt";
constant N : integer := 8;
constant MAX_COMPS : integer := 3;
variable inline : LINE;
variable tmp_int : INTEGER := 0;
variable y_size : INTEGER := 0;
variable x_size : INTEGER := 0;
variable matrix : I_MATRIX_TYPE;
variable x_blk_cnt : INTEGER := 0;
variable y_blk_cnt : INTEGER := 0;
variable n_lines_arr : N_LINES_TYPE;
variable line_n : INTEGER := 0;
variable pix_n : INTEGER := 0;
variable x_n : INTEGER := 0;
variable y_n : INTEGER := 0;
variable data_word : unsigned(31 downto 0);
variable image_line : STD_LOGIC_VECTOR(0 to MAX_COMPS*MAX_IMAGE_SIZE_X*IP_W-1);
constant C_IMAGE_RAM_BASE : unsigned(31 downto 0) := X"0010_0000";
variable x_cnt : integer;
variable data_word2 : unsigned(31 downto 0);
variable num_comps_v : integer;
begin
READLINE(infile,inline);
READ(inline,num_comps_v);
READLINE(infile,inline);
READ(inline,y_size);
READLINE(infile,inline);
READ(inline,x_size);
num_comps <= num_comps_v;
if y_size rem N > 0 then
assert false
report "ERROR: Image height dimension is not multiply of 8!"
severity Failure;
end if;
if x_size rem N > 0 then
assert false
report "ERROR: Image width dimension is not multiply of 8!"
severity Failure;
end if;
if x_size > C_MAX_LINE_WIDTH then
assert false
report "ERROR: Image width bigger than C_MAX_LINE_WIDTH in JPEG_PKG.VHD! " &
"Increase C_MAX_LINE_WIDTH accordingly"
severity Failure;
end if;
addr_inc <= 0;
-- image size
host_write(CLK, X"0000_0004", to_unsigned(x_size,16) & to_unsigned(y_size,16),
OPB_ABus, OPB_BE, OPB_DBus_in, OPB_RNW, OPB_select, OPB_XferAck);
iram_wren <= '0';
for y_n in 0 to y_size-1 loop
READLINE(infile,inline);
HREAD(inline,image_line(0 to num_comps*x_size*IP_W-1));
x_cnt := 0;
for x_n in 0 to x_size-1 loop
data_word := X"00" & UNSIGNED(image_line(x_cnt to x_cnt+num_comps*IP_W-1));
if C_PIXEL_BITS = 24 then
data_word2(7 downto 0) := data_word(23 downto 16);
data_word2(15 downto 8) := data_word(15 downto 8);
data_word2(23 downto 16) := data_word(7 downto 0);
else
data_word2(4 downto 0) := data_word(23 downto 19);
data_word2(10 downto 5) := data_word(15 downto 10);
data_word2(15 downto 11) := data_word(7 downto 3);
end if;
iram_wren <= '0';
iram_wdata <= (others => 'X');
while(fifo_almost_full = '1') loop
wait until rising_edge(clk);
end loop;
--for i in 0 to 9 loop
-- wait until rising_edge(clk);
--end loop;
iram_wren <= '1';
iram_wdata <= std_logic_vector(data_word2(C_PIXEL_BITS-1 downto 0));
wait until rising_edge(clk);
x_cnt := x_cnt + num_comps*IP_W;
addr_inc <= addr_inc + 1;
end loop;
end loop;
iram_wren <= '0';
end read_image;
------------------
type ROMQ_TYPE is array (0 to 64-1)
of unsigned(7 downto 0);
constant qrom_lum : ROMQ_TYPE :=
(
-- 100%
--others => X"01"
-- 85%
--X"05", X"03", X"04", X"04",
--X"04", X"03", X"05", X"04",
--X"04", X"04", X"05", X"05",
--X"05", X"06", X"07", X"0C",
--X"08", X"07", X"07", X"07",
--X"07", X"0F", X"0B", X"0B",
--X"09", X"0C", X"11", X"0F",
--X"12", X"12", X"11", X"0F",
--X"11", X"11", X"13", X"16",
--X"1C", X"17", X"13", X"14",
--X"1A", X"15", X"11", X"11",
--X"18", X"21", X"18", X"1A",
--X"1D", X"1D", X"1F", X"1F",
--X"1F", X"13", X"17", X"22",
--X"24", X"22", X"1E", X"24",
--X"1C", X"1E", X"1F", X"1E"
-- 100%
--others => X"01"
-- 75%
--X"08", X"06", X"06", X"07", X"06", X"05", X"08", X"07", X"07", X"07", X"09", X"09", X"08", X"0A", X"0C", X"14",
--X"0D", X"0C", X"0B", X"0B", X"0C", X"19", X"12", X"13", X"0F", X"14", X"1D", X"1A", X"1F", X"1E", X"1D", X"1A",
--X"1C", X"1C", X"20", X"24", X"2E", X"27", X"20", X"22", X"2C", X"23", X"1C", X"1C", X"28", X"37", X"29", X"2C",
--X"30", X"31", X"34", X"34", X"34", X"1F", X"27", X"39", X"3D", X"38", X"32", X"3C", X"2E", X"33", X"34", X"32"
-- 15 %
--X"35", X"25", X"28", X"2F",
--X"28", X"21", X"35", X"2F",
--X"2B", X"2F", X"3C", X"39",
--X"35", X"3F", X"50", X"85",
--X"57", X"50", X"49", X"49",
--X"50", X"A3", X"75", X"7B",
--X"61", X"85", X"C1", X"AA",
--X"CB", X"C8", X"BE", X"AA",
--X"BA", X"B7", X"D5", X"F0",
--X"FF", X"FF", X"D5", X"E2",
--X"FF", X"E6", X"B7", X"BA",
--X"FF", X"FF", X"FF", X"FF",
--X"FF", X"FF", X"FF", X"FF",
--X"FF", X"CE", X"FF", X"FF",
--X"FF", X"FF", X"FF", X"FF",
--X"FF", X"FF", X"FF", X"FF"
-- 50%
X"10", X"0B", X"0C", X"0E", X"0C", X"0A", X"10", X"0E",
X"0D", X"0E", X"12", X"11", X"10", X"13", X"18", X"28",
X"1A", X"18", X"16", X"16", X"18", X"31", X"23", X"25",
X"1D", X"28", X"3A", X"33", X"3D", X"3C", X"39", X"33",
X"38", X"37", X"40", X"48", X"5C", X"4E", X"40", X"44",
X"57", X"45", X"37", X"38", X"50", X"6D", X"51", X"57",
X"5F", X"62", X"67", X"68", X"67", X"3E", X"4D", X"71",
X"79", X"70", X"64", X"78", X"5C", X"65", X"67", X"63"
);
constant qrom_chr : ROMQ_TYPE :=
(
-- 50% for chrominance
X"11", X"12", X"12", X"18", X"15", X"18", X"2F", X"1A",
X"1A", X"2F", X"63", X"42", X"38", X"42", X"63", X"63",
X"63", X"63", X"63", X"63", X"63", X"63", X"63", X"63",
X"63", X"63", X"63", X"63", X"63", X"63", X"63", X"63",
X"63", X"63", X"63", X"63", X"63", X"63", X"63", X"63",
X"63", X"63", X"63", X"63", X"63", X"63", X"63", X"63",
X"63", X"63", X"63", X"63", X"63", X"63", X"63", X"63",
X"63", X"63", X"63", X"63", X"63", X"63", X"63", X"63"
-- 75% chrominance
--X"09", X"09", X"09", X"0C", X"0B", X"0C", X"18", X"0D",
--X"0D", X"18", X"32", X"21", X"1C", X"21", X"32", X"32",
--X"32", X"32", X"32", X"32", X"32", X"32", X"32", X"32",
--X"32", X"32", X"32", X"32", X"32", X"32", X"32", X"32",
--X"32", X"32", X"32", X"32", X"32", X"32", X"32", X"32",
--X"32", X"32", X"32", X"32", X"32", X"32", X"32", X"32",
--X"32", X"32", X"32", X"32", X"32", X"32", X"32", X"32",
--X"32", X"32", X"32", X"32", X"32", X"32", X"32", X"32"
--X"08", X"06", X"06", X"07", X"06", X"05", X"08", X"07", X"07", X"07", X"09", X"09", X"08", X"0A", X"0C", X"14",
--X"0D", X"0C", X"0B", X"0B", X"0C", X"19", X"12", X"13", X"0F", X"14", X"1D", X"1A", X"1F", X"1E", X"1D", X"1A",
--X"1C", X"1C", X"20", X"24", X"2E", X"27", X"20", X"22", X"2C", X"23", X"1C", X"1C", X"28", X"37", X"29", X"2C",
--X"30", X"31", X"34", X"34", X"34", X"1F", X"27", X"39", X"3D", X"38", X"32", X"3C", X"2E", X"33", X"34", X"32"
--others => X"01"
);
variable data_read : unsigned(31 downto 0);
variable data_write : unsigned(31 downto 0);
variable addr : unsigned(31 downto 0);
------------------------------------------------------------------------------
-- BEGIN
------------------------------------------------------------------------------
begin
sim_done <= '0';
iram_wren <= '0';
while RST /= '0' loop
wait until rising_edge(clk);
end loop;
for i in 0 to 100 loop
wait until rising_edge(clk);
end loop;
host_read(CLK, X"0000_0000", data_read,
OPB_ABus, OPB_BE, OPB_DBus_out, OPB_RNW, OPB_select, OPB_XferAck);
host_read(CLK, X"0000_0004", data_read,
OPB_ABus, OPB_BE, OPB_DBus_out, OPB_RNW, OPB_select, OPB_XferAck);
-- write luminance quantization table
for i in 0 to 64-1 loop
data_write := X"0000_00" & qrom_lum(i);
addr := X"0000_0100" + to_unsigned(4*i,32);
host_write(CLK, addr, data_write,
OPB_ABus, OPB_BE, OPB_DBus_in, OPB_RNW, OPB_select, OPB_XferAck);
end loop;
-- write chrominance quantization table
for i in 0 to 64-1 loop
data_write := X"0000_00" & qrom_chr(i);
addr := X"0000_0200" + to_unsigned(4*i,32);
host_write(CLK, addr, data_write,
OPB_ABus, OPB_BE, OPB_DBus_in, OPB_RNW, OPB_select, OPB_XferAck);
end loop;
data_write := to_unsigned(1,32) + shift_left(to_unsigned(3,32),1);
-- SOF & num_comps
host_write(CLK, X"0000_0000", data_write,
OPB_ABus, OPB_BE, OPB_DBus_in, OPB_RNW, OPB_select, OPB_XferAck);
-- write BUF_FIFO with bitmap
read_image;
-- wait until JPEG encoding is done
host_read(CLK, X"0000_000C", data_read,
OPB_ABus, OPB_BE, OPB_DBus_out, OPB_RNW, OPB_select, OPB_XferAck);
while data_read /= 2 loop
host_read(CLK, X"0000_000C", data_read,
OPB_ABus, OPB_BE, OPB_DBus_out, OPB_RNW, OPB_select, OPB_XferAck);
end loop;
sim_done <= '1';
wait;
end process;
end architecture RTL;
-------------------------------------------------------------------------------
-- Architecture: end
------------------------------------------------------------------------------- | lgpl-3.0 | 602d27cdc0aa388fb7da91a61f5449c9 | 0.421909 | 3.15594 | false | false | false | false |
chiggs/nvc | test/regress/case5.vhd | 5 | 593 | entity case5 is
end entity;
architecture test of case5 is
begin
process
type modcount is range 0 to 7;
variable a: modcount := 5;
constant b: natural := 4;
variable c: natural;
begin
case modcount(integer(a) + b) is
when 0 | 1 | 2 | 3 | 4 =>
c := c + 1;
when 5 | 6 | 7 =>
c := c + 42;
end case;
report "integer(a) + b = " & integer'image(natural'VAL(integer(a)+b));
report "c = " & natural'image(natural'VAL(c));
wait;
end process;
end architecture;
| gpl-3.0 | 5ac78b2d658fbcad52a8f385eef9b4df | 0.499157 | 3.660494 | false | false | false | false |
markusC64/1541ultimate2 | fpga/fpga_top/cyclone4_test/vhdl_source/u2p_memtest.vhd | 1 | 15,058 | -------------------------------------------------------------------------------
-- Title : u2p_memtest
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: Toplevel with just the alt-mem phy. Testing and experimenting
-- with memory latency.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity u2p_memtest is
port (
-- slot side
SLOT_PHI2 : in std_logic;
SLOT_DOTCLK : in std_logic;
SLOT_RSTn : inout std_logic;
SLOT_BUFFER_ENn : out std_logic;
SLOT_ADDR : inout std_logic_vector(15 downto 0);
SLOT_DATA : inout std_logic_vector(7 downto 0);
SLOT_RWn : inout std_logic;
SLOT_BA : in std_logic;
SLOT_DMAn : out std_logic;
SLOT_EXROMn : inout std_logic;
SLOT_GAMEn : inout std_logic;
SLOT_ROMHn : inout std_logic;
SLOT_ROMLn : inout std_logic;
SLOT_IO1n : inout std_logic;
SLOT_IO2n : inout std_logic;
SLOT_IRQn : inout std_logic;
SLOT_NMIn : inout std_logic;
SLOT_VCC : in std_logic;
-- memory
SDRAM_A : out std_logic_vector(13 downto 0); -- DRAM A
SDRAM_BA : out std_logic_vector(2 downto 0) := (others => '0');
SDRAM_DQ : inout std_logic_vector(7 downto 0);
SDRAM_CSn : out std_logic;
SDRAM_RASn : out std_logic;
SDRAM_CASn : out std_logic;
SDRAM_WEn : out std_logic;
SDRAM_DM : out std_logic;
SDRAM_CKE : out std_logic;
SDRAM_CLK : inout std_logic;
SDRAM_CLKn : inout std_logic;
SDRAM_ODT : out std_logic;
SDRAM_DQS : inout std_logic;
AUDIO_MCLK : out std_logic := '0';
AUDIO_BCLK : out std_logic := '0';
AUDIO_LRCLK : out std_logic := '0';
AUDIO_SDO : out std_logic := '0';
AUDIO_SDI : in std_logic;
-- IEC bus
IEC_ATN : inout std_logic;
IEC_DATA : inout std_logic;
IEC_CLOCK : inout std_logic;
IEC_RESET : in std_logic;
IEC_SRQ_IN : inout std_logic;
LED_DISKn : out std_logic; -- activity LED
LED_CARTn : out std_logic;
LED_SDACTn : out std_logic;
LED_MOTORn : out std_logic;
-- Ethernet RMII
ETH_RESETn : out std_logic := '1';
ETH_IRQn : in std_logic;
RMII_REFCLK : in std_logic;
RMII_CRS_DV : in std_logic;
RMII_RX_ER : in std_logic;
RMII_RX_DATA : in std_logic_vector(1 downto 0);
RMII_TX_DATA : out std_logic_vector(1 downto 0);
RMII_TX_EN : out std_logic;
MDIO_CLK : out std_logic := '0';
MDIO_DATA : inout std_logic := 'Z';
-- Speaker data
SPEAKER_DATA : out std_logic := '0';
SPEAKER_ENABLE : out std_logic := '0';
-- Debug UART
UART_TXD : out std_logic;
UART_RXD : in std_logic;
-- I2C Interface for RTC, audio codec and usb hub
I2C_SDA : inout std_logic := 'Z';
I2C_SCL : inout std_logic := 'Z';
I2C_SDA_18 : inout std_logic := 'Z';
I2C_SCL_18 : inout std_logic := 'Z';
-- Flash Interface
FLASH_CSn : out std_logic;
FLASH_SCK : out std_logic;
FLASH_MOSI : out std_logic;
FLASH_MISO : in std_logic;
FLASH_SEL : out std_logic := '0';
FLASH_SELCK : out std_logic := '0';
-- USB Interface (ULPI)
ULPI_RESET : out std_logic;
ULPI_CLOCK : in std_logic;
ULPI_NXT : in std_logic;
ULPI_STP : out std_logic;
ULPI_DIR : in std_logic;
ULPI_DATA : inout std_logic_vector(7 downto 0);
HUB_RESETn : out std_logic := '1';
HUB_CLOCK : out std_logic := '0';
-- Cassette Interface
CAS_MOTOR : in std_logic := '0';
CAS_SENSE : inout std_logic := 'Z';
CAS_READ : inout std_logic := 'Z';
CAS_WRITE : inout std_logic := 'Z';
-- Buttons
BUTTON : in std_logic_vector(2 downto 0));
end entity;
architecture rtl of u2p_memtest is
component pll
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
end component;
component memphy
port (
pll_ref_clk : IN STD_LOGIC;
global_reset_n : IN STD_LOGIC;
soft_reset_n : IN STD_LOGIC;
ctl_dqs_burst : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
ctl_wdata_valid : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
ctl_wdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ctl_dm : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
ctl_addr : IN STD_LOGIC_VECTOR (27 DOWNTO 0);
ctl_ba : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
ctl_cas_n : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
ctl_cke : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
ctl_cs_n : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
ctl_odt : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
ctl_ras_n : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
ctl_we_n : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
ctl_rst_n : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
ctl_mem_clk_disable : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
ctl_doing_rd : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
ctl_cal_req : IN STD_LOGIC;
ctl_cal_byte_lane_sel_n : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dbg_clk : IN STD_LOGIC;
dbg_reset_n : IN STD_LOGIC;
dbg_addr : IN STD_LOGIC_VECTOR (12 DOWNTO 0);
dbg_wr : IN STD_LOGIC;
dbg_rd : IN STD_LOGIC;
dbg_cs : IN STD_LOGIC;
dbg_wr_data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
reset_request_n : OUT STD_LOGIC;
ctl_clk : OUT STD_LOGIC;
ctl_reset_n : OUT STD_LOGIC;
ctl_wlat : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
ctl_rdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
ctl_rdata_valid : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
ctl_rlat : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
ctl_cal_success : OUT STD_LOGIC;
ctl_cal_fail : OUT STD_LOGIC;
ctl_cal_warning : OUT STD_LOGIC;
mem_addr : OUT STD_LOGIC_VECTOR (13 DOWNTO 0);
mem_ba : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
mem_cas_n : OUT STD_LOGIC;
mem_cke : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
mem_cs_n : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
mem_dm : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
mem_odt : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
mem_ras_n : OUT STD_LOGIC;
mem_we_n : OUT STD_LOGIC;
mem_reset_n : OUT STD_LOGIC;
dbg_rd_data : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
dbg_waitrequest : OUT STD_LOGIC;
aux_half_rate_clk : OUT STD_LOGIC;
aux_full_rate_clk : OUT STD_LOGIC;
mem_clk : INOUT STD_LOGIC_VECTOR (0 DOWNTO 0);
mem_clk_n : INOUT STD_LOGIC_VECTOR (0 DOWNTO 0);
mem_dq : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0);
mem_dqs : INOUT STD_LOGIC_VECTOR (0 DOWNTO 0);
mem_dqs_n : INOUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
end component;
signal por_n : std_logic;
signal por_count : unsigned(23 downto 0) := (others => '0');
signal audio_clock : std_logic;
signal audio_reset : std_logic;
signal sys_clock : std_logic;
signal sys_reset : std_logic;
signal sys_reset_n : std_logic;
signal eth_reset : std_logic;
signal button_i : std_logic_vector(2 downto 0);
-- miscellaneous interconnect
signal ulpi_reset_i : std_logic;
signal reset_request_n : std_logic := '1';
signal ctl_dqs_burst : STD_LOGIC_VECTOR (1 DOWNTO 0) := (others => '0');
signal ctl_wdata_valid : STD_LOGIC_VECTOR (1 DOWNTO 0) := (others => '0');
signal ctl_wdata : STD_LOGIC_VECTOR (31 DOWNTO 0) := (others => '0');
signal ctl_dm : STD_LOGIC_VECTOR (3 DOWNTO 0) := (others => '0');
signal ctl_addr : STD_LOGIC_VECTOR (27 DOWNTO 0) := (others => '0');
signal ctl_ba : STD_LOGIC_VECTOR (3 DOWNTO 0) := (others => '0');
signal ctl_cas_n : STD_LOGIC_VECTOR (1 DOWNTO 0) := (others => '1');
signal ctl_cke : STD_LOGIC_VECTOR (1 DOWNTO 0) := (others => '1');
signal ctl_cs_n : STD_LOGIC_VECTOR (1 DOWNTO 0) := (others => '1');
signal ctl_odt : STD_LOGIC_VECTOR (1 DOWNTO 0) := (others => '0');
signal ctl_ras_n : STD_LOGIC_VECTOR (1 DOWNTO 0) := (others => '1');
signal ctl_we_n : STD_LOGIC_VECTOR (1 DOWNTO 0) := (others => '1');
signal ctl_rst_n : STD_LOGIC_VECTOR (1 DOWNTO 0) := (others => '1');
signal ctl_mem_clk_disable : STD_LOGIC_VECTOR (0 DOWNTO 0) := (others => '0');
signal ctl_doing_rd : STD_LOGIC_VECTOR (1 DOWNTO 0) := (others => '0');
signal ctl_wlat : STD_LOGIC_VECTOR (4 DOWNTO 0) := (others => '0');
signal ctl_rdata : STD_LOGIC_VECTOR (31 DOWNTO 0) := (others => '0');
signal ctl_rdata_valid : STD_LOGIC_VECTOR (1 DOWNTO 0) := (others => '0');
signal ctl_rlat : STD_LOGIC_VECTOR (4 DOWNTO 0) := (others => '0');
signal ctl_cal_success : STD_LOGIC := '0';
signal ctl_cal_fail : STD_LOGIC := '0';
signal ctl_cal_warning : STD_LOGIC := '0';
signal count : unsigned(23 downto 0) := (others => '0');
begin
process(RMII_REFCLK, button_i)
begin
if button_i(0) = '1' then
por_count <= (others => '0');
elsif rising_edge(RMII_REFCLK) then
-- if rising_edge(RMII_REFCLK) then
if por_count = X"FFFFFF" then
por_n <= '1';
else
por_n <= '0';
por_count <= por_count + 1;
end if;
end if;
end process;
sys_reset <= not sys_reset_n;
i_pll: pll port map (
inclk0 => RMII_REFCLK, -- 50 MHz
c0 => HUB_CLOCK, -- 24 MHz
c1 => audio_clock, -- 12.245 MHz (47.831 kHz sample rate)
locked => open );
i_audio_reset: entity work.level_synchronizer
generic map ('1')
port map (
clock => audio_clock,
input => not sys_reset_n,
input_c => audio_reset );
i_ulpi_reset: entity work.level_synchronizer
generic map ('1')
port map (
clock => ulpi_clock,
input => sys_reset,
input_c => ulpi_reset_i );
i_eth_reset: entity work.level_synchronizer
generic map ('1')
port map (
clock => RMII_REFCLK,
input => sys_reset,
input_c => eth_reset );
i_memphy: memphy
port map (
pll_ref_clk => RMII_REFCLK,
global_reset_n => por_n,
soft_reset_n => por_n,
reset_request_n => reset_request_n,
aux_half_rate_clk => open,
aux_full_rate_clk => open,
ctl_clk => sys_clock,
ctl_reset_n => sys_reset_n,
ctl_dqs_burst => ctl_dqs_burst,
ctl_wdata_valid => ctl_wdata_valid,
ctl_wdata => ctl_wdata,
ctl_dm => ctl_dm,
ctl_addr => ctl_addr,
ctl_ba => ctl_ba,
ctl_cas_n => ctl_cas_n,
ctl_cke => ctl_cke,
ctl_cs_n => ctl_cs_n,
ctl_odt => ctl_odt,
ctl_ras_n => ctl_ras_n,
ctl_we_n => ctl_we_n,
ctl_rst_n => ctl_rst_n,
ctl_mem_clk_disable => ctl_mem_clk_disable,
ctl_doing_rd => ctl_doing_rd,
ctl_rdata => ctl_rdata,
ctl_rdata_valid => ctl_rdata_valid,
ctl_cal_req => '0',
ctl_cal_byte_lane_sel_n => "0",
ctl_cal_success => ctl_cal_success,
ctl_cal_fail => ctl_cal_fail,
ctl_cal_warning => ctl_cal_warning,
ctl_wlat => ctl_wlat,
ctl_rlat => ctl_rlat,
dbg_clk => sys_clock,
dbg_reset_n => sys_reset_n,
dbg_addr => (others => '0'),
dbg_wr => '0',
dbg_rd => '0',
dbg_cs => '0',
dbg_wr_data => (others => '0'),
dbg_rd_data => open,
dbg_waitrequest => open,
mem_addr => SDRAM_A,
mem_ba => SDRAM_BA(1 downto 0),
mem_cas_n => SDRAM_CASn,
mem_cke(0) => SDRAM_CKE,
mem_cs_n(0) => SDRAM_CSn,
mem_dm(0) => SDRAM_DM,
mem_odt(0) => SDRAM_ODT,
mem_ras_n => SDRAM_RASn,
mem_we_n => SDRAM_WEn,
mem_reset_n => open,
mem_clk(0) => SDRAM_CLK,
mem_clk_n(0) => SDRAM_CLKn,
mem_dq => SDRAM_DQ,
mem_dqs(0) => SDRAM_DQS,
mem_dqs_n(0) => open
);
MDIO_CLK <= 'Z';
MDIO_DATA <= 'Z';
ETH_RESETn <= '1';
HUB_RESETn <= eth_reset;
SPEAKER_ENABLE <= '0';
SLOT_ADDR <= (others => 'Z');
SLOT_DATA <= (others => 'Z');
-- top
SLOT_DMAn <= 'Z';
SLOT_ROMLn <= 'Z';
SLOT_IO2n <= 'Z';
SLOT_EXROMn <= 'Z';
SLOT_GAMEn <= 'Z';
SLOT_IO1n <= 'Z';
SLOT_RWn <= 'Z';
SLOT_IRQn <= 'Z';
SLOT_NMIn <= 'Z';
SLOT_RSTn <= 'Z';
SLOT_ROMHn <= 'Z';
-- Cassette Interface
CAS_SENSE <= '0';
CAS_READ <= '0';
CAS_WRITE <= '0';
LED_MOTORn <= not ctl_cal_success;
LED_DISKn <= not ctl_cal_fail;
LED_CARTn <= count(count'high); -- not ctl_cal_warning xor button_i(0) xor button_i(1) xor button_i(2);
LED_SDACTn <= sys_reset_n;
process(sys_clock)
begin
if rising_edge(sys_clock) then
count <= count + 1;
end if;
end process;
button_i <= not BUTTON;
SLOT_BUFFER_ENn <= SLOT_BA xor SLOT_DOTCLK xor SLOT_PHI2 xor CAS_MOTOR xor SLOT_VCC; -- we don't connect to a C64
-- Debug UART
UART_TXD <= '1';
-- Flash Interface
FLASH_SEL <= '0';
FLASH_SELCK <= '0';
FLASH_CSn <= '1';
FLASH_SCK <= '1';
FLASH_MOSI <= '1';
-- USB Interface (ULPI)
ULPI_RESET <= por_n;
ULPI_STP <= '0';
ULPI_DATA <= (others => 'Z');
end architecture;
| gpl-3.0 | 68cf9f73a8ab1538edc08d3d4e8557d1 | 0.484925 | 3.360411 | false | false | false | false |
markusC64/1541ultimate2 | fpga/cpu_unit/mblite/hw/core/core_wb.vhd | 2 | 1,848 | ----------------------------------------------------------------------------------------------
--
-- Input file : core_wb.vhd
-- Design name : core_wb
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Faculty EEMCS, Department ME&CE
-- : Systems and Circuits group
--
-- Description : Top level module of the MB-Lite microprocessor with connected
-- wishbone data bus
--
----------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library mblite;
use mblite.config_Pkg.all;
use mblite.core_Pkg.all;
use mblite.std_Pkg.all;
entity core_wb is generic
(
G_INTERRUPT : boolean := CFG_INTERRUPT;
G_USE_HW_MUL : boolean := CFG_USE_HW_MUL;
G_USE_BARREL : boolean := CFG_USE_BARREL;
G_DEBUG : boolean := CFG_DEBUG
);
port
(
imem_o : out imem_out_type;
wb_o : out wb_mst_out_type;
imem_i : in imem_in_type;
wb_i : in wb_mst_in_type
);
end core_wb;
architecture arch of core_wb is
signal dmem_i : dmem_in_type;
signal dmem_o : dmem_out_type;
begin
wb_adapter0 : core_wb_adapter port map
(
dmem_i => dmem_i,
wb_o => wb_o,
dmem_o => dmem_o,
wb_i => wb_i
);
core0 : core generic map
(
G_INTERRUPT => G_INTERRUPT,
G_USE_HW_MUL => G_USE_HW_MUL,
G_USE_BARREL => G_USE_BARREL,
G_DEBUG => G_DEBUG
)
port map
(
imem_o => imem_o,
dmem_o => dmem_o,
imem_i => imem_i,
dmem_i => dmem_i,
int_i => wb_i.int_i,
rst_i => wb_i.rst_i,
clk_i => wb_i.clk_i
);
end arch;
| gpl-3.0 | b6eff0a28b796bf151010405ee723ea5 | 0.469697 | 3.5 | false | false | false | false |
xiadz/oscilloscope | src/debouncer.vhd | 1 | 1,054 | ----------------------------------------------------------------------------------
-- Author: Osowski Marcin
-- Create Date: 15:03:57 05/24/2011
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity debouncer is
generic (
n : natural := 5000;
signal_width : natural := 8
);
port (
nrst : in std_logic;
clk : in std_logic;
input : in std_logic_vector (signal_width - 1 downto 0);
output : out std_logic_vector (signal_width - 1 downto 0)
);
end debouncer;
architecture behavioral of debouncer is
begin
debouncers: for i in 0 to signal_width - 1 generate
one_debouncer: entity work.single_debouncer
generic map (
n => n
)
port map(
nrst => nrst,
clk => clk,
input => input (i),
output => output (i)
);
end generate debouncers;
end behavioral;
| mit | 1a295c4cf252bc9d42218824ed9b9564 | 0.439279 | 4.790909 | false | false | false | false |
chiggs/nvc | test/parse/array.vhd | 4 | 984 | package p is
type int_array is array (integer range <>) of integer;
type ten_ints is array (1 to 10) of integer;
type chars is (A, B, C);
type char_counts is array (chars) of integer;
type two_d is array (1 to 3, 4 to 6) of integer;
type ab_chars is array (chars range A to B) of integer;
end package;
architecture a of e is
signal x : int_array(1 to 5);
signal y : ten_ints;
signal z : int_array(1 to 3) := ( 0, 1, 2 );
signal n : int_array(1 to 3) := ( 0, 1 => 1, others => 2 );
signal m : int_array(1 to 3) := ( 1 to 3 => 0 );
signal c : char_counts;
signal t : two_d;
signal u : ten_ints := ( 1 | 2 | 3 => 4, others => 2);
signal v : ten_ints := ( 1 ! 2 ! 3 => 4, others => 2);
begin
process is
begin
x(0) <= 1;
y(2) <= n(2);
y(3)(5) <= n(2)(1);
x(1 to 3) <= z(1 to 3);
a := (x'range => 5);
a := (x'reverse_range => 3);
end process;
end architecture;
| gpl-3.0 | 236b2cd4014abf4f67e921a44da150a2 | 0.51626 | 2.97281 | false | false | false | false |
markusC64/1541ultimate2 | fpga/altera/xilinx_primitives/RAMB16_S9_S36.vhd | 1 | 11,226 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT TECHNOLUTION BV, GOUDA NL
-- | ======= I == I =
-- | I I I I
-- | I === === I === I === === I I I ==== I === I ===
-- | I / \ I I/ I I/ I I I I I I I I I I I/ I
-- | I ===== I I I I I I I I I I I I I I I I
-- | I \ I I I I I I I I I /I \ I I I I I
-- | I === === I I I I === === === I == I === I I
-- | +---------------------------------------------------+
-- +----+ | +++++++++++++++++++++++++++++++++++++++++++++++++|
-- | | ++++++++++++++++++++++++++++++++++++++|
-- +------------+ +++++++++++++++++++++++++|
-- ++++++++++++++|
-- A U T O M A T I O N T E C H N O L O G Y +++++|
--
-------------------------------------------------------------------------------
-- Title : RAMB16_S9_S36
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: Altera wrapper
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
entity RAMB16_S9_S36 is
generic (
INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_A : bit_vector := X"000";
INIT_B : bit_vector := X"000000000";
SIM_COLLISION_CHECK : string := "ALL";
SRVAL_A : bit_vector := X"000";
SRVAL_B : bit_vector := X"000000000";
WRITE_MODE_A : string := "READ_FIRST";
WRITE_MODE_B : string := "READ_FIRST"
);
port (
DOA : out std_logic_vector(7 downto 0);
DOB : out std_logic_vector(31 downto 0);
DOPA : out std_logic_vector(0 downto 0);
DOPB : out std_logic_vector(3 downto 0);
ADDRA : in std_logic_vector(10 downto 0);
ADDRB : in std_logic_vector(8 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector(7 downto 0);
DIB : in std_logic_vector(31 downto 0);
DIPA : in std_logic_vector(0 downto 0);
DIPB : in std_logic_vector(3 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic
);
end entity;
architecture wrapper of RAMB16_S9_S36 is
signal wren_a : std_logic;
signal wren_b : std_logic;
begin
altsyncram_component : altsyncram
GENERIC MAP (
address_reg_b => "CLOCK1",
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
indata_reg_b => "CLOCK1",
intended_device_family => "Cyclone IV E",
lpm_type => "altsyncram",
numwords_a => 2048,
numwords_b => 512,
operation_mode => "BIDIR_DUAL_PORT",
outdata_aclr_a => "NONE",
outdata_aclr_b => "NONE",
outdata_reg_a => "UNREGISTERED",
outdata_reg_b => "UNREGISTERED",
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
widthad_a => 11,
widthad_b => 9,
width_a => 8,
width_b => 32,
width_byteena_a => 1,
width_byteena_b => 1,
wrcontrol_wraddress_reg_b => "CLOCK1"
)
PORT MAP (
address_a => ADDRA,
address_b => ADDRB,
clock0 => CLKA,
clock1 => CLKB,
data_a => DIA,
data_b => DIB,
rden_a => ENA,
rden_b => ENB,
wren_a => wren_a,
wren_b => wren_b,
q_a => DOA,
q_b => DOB );
wren_a <= WEA and ENA;
wren_b <= WEB and ENB;
end architecture;
| gpl-3.0 | 0ca9203fad528ed22edc0ef156224de4 | 0.664172 | 5.290292 | false | false | false | false |
chiggs/nvc | test/regress/record4.vhd | 5 | 883 | entity record4 is
end entity;
architecture test of record4 is
type rec is record
x, y : integer;
end record;
type rec_array is array (natural range <>) of rec;
function sum(r : in rec) return integer is
begin
return r.x + r.y;
end function;
function double(x : in integer) return integer is
begin
return x * 2;
end function;
function sum_all(a : in rec_array) return integer is
variable s : integer := 0;
begin
for i in a'range loop
s := s + sum(a(i));
end loop;
return s;
end function;
begin
process is
variable ra : rec_array(0 to 1) := (
( 1, 2 ),
( 3, 4 ) );
begin
assert sum(ra(0)) = 3;
assert double(ra(0).x) = 2;
assert sum_all(ra) = 10;
wait;
end process;
end architecture;
| gpl-3.0 | 319fc8d39b71aff3613537dd22ef7a60 | 0.533409 | 3.710084 | false | false | false | false |
luigicalligaris/cms-phase2upgrade-tt-firmware | firmware/post_am_htrz/htrz_components/hdl/htrz_top.vhd | 1 | 27,284 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
--
--
-- htrz_constants.vhd
--
--
package htrz_constants is
constant width_phi : natural := 18;
constant width_rS : natural := 18;
constant base_rS : real := 7.62939453125e-5;
constant width_zS : natural := 18;
constant base_zS : real := 7.62939453125e-5;
constant width_bend : natural := 4;
constant width_Sindex : natural := 7;
-- Definition of constants, widths and bases for variables internal to the HTRZ
constant width_rT : natural := 18;
constant base_rT : real := 7.62939453125e-5;
constant width_zC : natural := 18;
constant base_zC : real := 7.62939453125e-5;
constant width_zG : natural := 18;
constant base_zG : real := 7.62939453125e-5;
constant width_cotantheta : natural := 13;
constant base_cotantheta : real := 9.765625e-4;
constant nbins_zT : natural := 8;
constant width_zT_bin : natural := 3;
assert ceil( log(2.0, nbins_zT) ) <= width_zT_bin report "Not enough bits (width_zT_bin) to represent nbins_zT" severity error;
-- THIS WILL DEPEND ON THE CHOICE OF THE MULTIPLIER IN THE INITIAL DSP CALCULATION!!!!!!!
-- IT IS CRITICALLY IMPORTANT TO CHOOSE IT PROPERLY OR YOU WILL BE PICKING UP EITHER
-- SCRAMBLED NUMBERS OR ALL '1' OR '0'
constant bitposition_msb_zT_bin_in_zT : natural := 15;
constant bitposition_lsb_overflow_guard_in_zT : natural := 15;
constant bitposition_msb_overflow_guard_in_zT : natural := 18;
constant nbins_cotantheta : natural := 8;
constant nboundaries_cotantheta : natural := nbins_cotantheta + 1;
constant n_stubs_per_roadlayer : natural := 4;
constant n_layers : natural := 6;
end;
--
--
-- htrz_data_types.vhd
--
--
package htrz_data_types is
type t_stub is
record
valid : std_logic;
phi : std_logic_vector(width_phi - 1 downto 0);
Ri : std_logic_vector(width_rS - 1 downto 0);
z : std_logic_vector(width_zS - 1 downto 0);
Bend : std_logic_vector(width_bend - 1 downto 0);
Sindex: std_logic_vector(width_Sindex - 1 downto 0);
end record;
constant null_stub : t_stub := ('0', (others => '0'), (others => '0'), (others => '0'), (others => '0'), (others => '0'));
type t_stub_no_z is
record
valid : std_logic;
phi : std_logic_vector(width_phi - 1 downto 0);
Ri : std_logic_vector(width_rS - 1 downto 0);
Bend : std_logic_vector(width_bend - 1 downto 0);
Sindex: std_logic_vector(width_Sindex - 1 downto 0);
end record;
constant null_stub_no_z : t_stub_no_z := ('0', (others => '0'), (others => '0'), (others => '0'), (others => '0'));
type t_roadlayer is array (n_stubs_per_roadlayer - 1 downto 0) of t_stub;
constant null_roadlayer : t_roadlayer := (others => null_stub)
type t_road is array (n_layers - 1 downto 0) of t_roadlayer;
constant null_road : t_road := (others => null_roadlayer)
type t_valid_column is std_logic_vector(nbins_zT - 1 downto 0);
constant null_valid_column : t_valid_column := (others => '0');
type t_valid_cell_matrix is array (nbins_cotantheta - 1 downto 0) of t_valid_column;
constant null_valid_cell_matrix := ( others => null_valid_column );
type t_valid_cell_matrixarray is array (natural range<>) of t_valid_cell_matrix;
-- constant null_valid_cell_matrixarray := ( others => null_valid_cell_matrix );
type t_valid_border_matrix is array (nboundaries_cotantheta - 1 downto 0) of t_valid_column;
constant null_stubvalid_bordermatrix := ( others => null_valid_column );
end;
--
--
-- htrz_stub_validity_borders2cells.vhd
--
--
entity htrz_stub_validity_borders2cells is
port (
clk : in std_logic;
valid_stub_in : in std_logic;
valid_borders_in : in t_valid_border_matrix;
valid_cells_out : out t_valid_cell_matrix
);
attribute ram_style: string;
attribute use_dsp48: string;
end;
architecture rtl of htrz_stub_validity_borders2cells is
signal local1_valid_stub : std_logic;
signal local1_valid_borders : t_valid_border_matrix := null_stubvalid_bordermatrix;
signal local2_valid_cell_matrix : t_valid_cell_matrix := null_valid_cell_matrix;
begin
valid_cells_out <= local2_valid_cell_matrix;
process( clk )
begin
if rising_edge( clk ) then
-- LOCALCLK 1
local1_valid_stub <= valid_stub_in;
local1_valid_borders <= valid_borders_in;
end if;
end process;
gen_cols: for iCotanColumn in 0 to nbins_cotantheta generate
gen_rows : for iZtRow in 0 to nbins_zT - 1 generate
process( clk )
begin
if rising_edge( clk ) then
-- LOCALCLK 2
-- LOOSE ACCEPTANCE POLICY (recommended)
-- B C B
-- --------
-- 0| 0 |0
-- 1| 1 |0
-- 1| 1 |1
-- 0| 1 |1
-- 0| 0 |0
local2_valid_cell_matrix[iCotanColumn][iZtRow] <= local1_valid_stub and (local1_valid_borders[iCotanColumn][iZtRow] or local1_valid_borders[iCotanColumn + 1][iZtRow]);
-- TIGHT ACCEPTANCE POLICY
-- B C B
-- --------
-- 0| 0 |0
-- 1| 0 |0
-- 1| 1 |1
-- 0| 0 |1
-- 0| 0 |0
-- local2_valid_cell_matrix[iCotanColumn][iZtRow] <= local1_valid_stub and (local1_valid_borders[iCotanColumn][iZtRow] and local1_valid_borders[iCotanColumn + 1][iZtRow]);
-- NOTE: In case the stub line gradients are above 1, i.e. the jump can be larger than one cell up/down, you will have also to manage the case
-- highlighted by the ? below. For this reason, gradients equal or below 1 make the firmware simpler.
--
-- B C B
-- --------
-- 1| 0 |0
-- 1| ? |0
-- 0| ? |0
-- 0| ? |1
-- 0| 0 |1
end if;
end process;
end generate;
end generate;
end;
--
--
-- htrz_layer_validity_stubs2layer.vhd
--
--
entity htrz_layer_validity_stubs2layer is
port (
clk : in std_logic;
stubs_cellmatrices_in : in t_valid_cell_matrixarray(n_stubs_per_roadlayer - 1 downto 0);
layer_cells_out : out t_valid_cell_matrix
);
attribute ram_style: string;
attribute use_dsp48: string;
end;
architecture rtl of htrz_layer_validity_stubs2layer is
signal local1_stubs_cellmatrices : t_valid_cell_matrixarray(n_stubs_per_roadlayer - 1 downto 0) := ( others => null_valid_cell_matrix );
signal local2_layer_cells : t_valid_cell_matrix := null_valid_cell_matrix;
begin
layer_cells_out <= local2_layer_cells;
process( clk )
begin
if rising_edge( clk ) then
-- LOCALCLK 1
local1_stubs_cellmatrices <= stubs_cellmatrices_in;
end if;
end process;
gen_cols: for iCotanColumn in 0 to nbins_cotantheta generate
gen_rows : for iZtRow in 0 to nbins_zT - 1 generate
signal thiscell_stubs_validity : std_logic_vector(n_stubs_per_roadlayer - 1 downto 0) := ( others => '0');
begin
-- Below is just rewiring the cells into the vector...
-- /| /| /| /| /|
-- / | / | / | / | / |
-- / | / | / | / | / |
-- /00 | / | / | / | ---> thiscell_stubs_validity(0,1,2,3) for cell [4,4] /## |
-- / 0| / | / | / X | / #|
-- / | / | / | / | --vec OR reduction--> / |
-- | / | / | 2 / | X / | # /
-- | / | / | 2 / | / ---> thiscell_stubs_validity(0,1,2,3) for cell [2,2] | # /
-- | / | / |2 / | / |# /
-- | / | / | / | / | /
-- |/ |/ |/ |/ |/
-- e.g. INVALID (therefore, ignored)
-- Stub0 Stub1 Stub2 Stub3 Layer valid cells
--
gen_layers : for iStub in 0 to n_stubs_per_roadlayer generate
thiscell_stubs_validity[iStub] <= local1_stubs_cellmatrices[iStub][iCotanColumn][iZtRow];
end generate;
process( clk )
begin
if rising_edge( clk ) then
-- LOCALCLK 2
-- This is VHDL-2008 compliant
local2_layer_cells[iCotanColumn][iZtRow] = or thiscell_stubs_validity;
end if;
end process;
end generate;
end generate;
end;
--
--
-- htrz_road_validity_layermajority.vhd
--
--
entity htrz_road_validity_layermajority is
generic(
layercount_threshold : natural := 5
);
port (
clk : in std_logic;
layer_cellmatrices_in : in t_valid_cell_matrixarray(n_stubs_per_roadlayer - 1 downto 0);
road_cells_out : out t_valid_cell_matrix
);
attribute ram_style: string;
attribute use_dsp48: string;
end;
architecture rtl of htrz_road_validity_layermajority is
signal local1_layer_cellmatrices : t_valid_cell_matrixarray(n_layers - 1 downto 0) := ( others => null_valid_cell_matrix );
signal local2_road_cells : t_valid_cell_matrix := null_valid_cell_matrix;
function majority( hitpattern: std_logic_vector( n_layers - 1 downto 0 ); threshold: integer ) return std_logic is
variable counter: integer := 0;
begin
for k in n_layers - 1 downto 0 loop
if hitpattern( k ) = '1' then
counter := counter + 1;
end if;
end loop;
if counter > threshold - 1 then
return '1';
end if;
return '0';
end function;
begin
road_cells_out <= local2_road_cells;
process( clk )
begin
if rising_edge( clk ) then
-- LOCALCLK 1
local1_layer_cellmatrices <= layer_cellmatrices_in;
end if;
end process;
gen_cols: for iCotanColumn in 0 to nbins_cotantheta generate
gen_rows : for iZtRow in 0 to nbins_zT - 1 generate
signal thiscell_layer_validity : std_logic_vector(n_layers - 1 downto 0) := ( others => '0');
begin
-- Below is just rewiring the cells to the vector...
-- /| /| /| /| /| /| /|
-- / | / | / | / | / | / | / |
-- / | / | / | / | / | / | / |
-- / 0 | / 1 | / 2 | / 3 | / | / 5 | ---> thiscell_layer_validity(0,1,2,3,4,5) for cell [4,4] / # |
-- / | / | / | / | / | / | / |
-- / | / | / | / | / | / | --majority--> / |
-- | / | / | / | / | / | / | /
-- | 0 / | 1 / | / | 3 / | 4 / | 5 / ---> thiscell_layer_validity(0,1,2,3,4,5) for cell [2,2] | # /
-- | / | / | / | / | / | / | /
-- | / | / | / | / | / | / | /
-- |/ |/ |/ |/ |/ |/ |/
--
-- Layer0 Layer1 Layer2 Layer3 Layer4 Layer5 Road valid cells
--
gen_layers : for iLayer in 0 to n_layers generate
thiscell_layer_validity[iLayer] <= local1_layer_cellmatrices[iLayer][iCotanColumn][iZtRow];
end generate;
process( clk )
begin
if rising_edge( clk ) then
-- LOCALCLK 2
-- This is VHDL-2008 compliant
local2_layer_cells[iCotanColumn][iZtRow] = majority(thiscell_layer_validity, layercount_threshold);
end if;
end process;
end generate;
end generate;
end;
--
--
-- htrz_stub_validity_stub_vs_road.vhd
--
--
entity htrz_stub_validity_stub_vs_road is
port (
clk : in std_logic;
road_cells_in : in t_valid_cell_matrix;
stub_cells_in : in t_valid_cell_matrix;
stub_valid_cells_out : out t_valid_cell_matrix;
stub_valid_out : out std_logic
);
attribute ram_style: string;
attribute use_dsp48: string;
end;
architecture rtl of htrz_stub_validity_stub_vs_road is
signal local1_road_cells : t_valid_cell_matrix := null_valid_cell_matrix;
signal local1_stub_cells : t_valid_cell_matrix := null_valid_cell_matrix;
signal local2_stub_valid_cells : t_valid_cell_matrix := null_valid_cell_matrix;
signal local2_stub_valid_cells_asvec : std_logic_vector(nbins_cotantheta * nbins_zT - 1 downto 0) := ( others => '0');
signal local3_stub_valid_cells : t_valid_cell_matrix := null_valid_cell_matrix;
signal local3_stub_valid : std_logic := '0';
begin
process( clk )
begin
if rising_edge( clk ) then
-- LOCALCLK 1
local1_road_cells <= road_cells_in;
local1_stub_cells <= stub_cells_in;
end if;
end process;
gen_cols: for iCotanColumn in 0 to nbins_cotantheta generate
gen_rows : for iZtRow in 0 to nbins_zT - 1 generate
begin
-- /| /| /|
-- / | / | / |
-- / | / | / |
-- / S | / R | ---> (S and R) for cell [4,4] / # |
-- / | / | / |
-- / | / | / | --> CAST TO std_logic_vector (X*Y bit) --> OR reduce --> stub validity (1 bit)
-- | / | / | /
-- | S / | / ---> (S and R) for cell [2,2] | /
-- | / | / | /
-- | / | / | /
-- |/ |/ |/
--
-- Stub Road Stub AND Road
local2_stub_valid_cells_asvec[iCotanColumn * nbins_zT + iZtRow] <= local2_stub_valid_cells[iCotanColumn][iZtRow];
process( clk )
begin
if rising_edge( clk ) then
-- LOCALCLK 2
-- This is VHDL-2008 compliant
local2_stub_valid_cells[iCotanColumn][iZtRow] = local1_road_cells[iCotanColumn][iZtRow] and local1_stub_cells[iCotanColumn][iZtRow];
end if;
end process;
end generate;
end generate;
stub_valid_cells_out <= local3_stub_valid_cells;
stub_valid_out <= local3_stub_valid;
process( clk )
begin
if rising_edge( clk ) then
-- LOCALCLK 3
local3_stub_valid_cells <= local2_stub_valid_cells;
-- OR reduction
local3_stub_valid <= or local2_stub_valid_cells_asvec;
end if;
end process;
end;
--
--
-- htrz_stub_column.vhd
--
--
entity htrz_stub_column is
generic(
ibin_cotantheta : natural
);
port (
clk : in std_logic;
zT_lo_in : in std_logic_vector(zT_width - 1 downto 0);
zT_hi_in : in std_logic_vector(zT_width - 1 downto 0);
zT_lo_out : out std_logic_vector(zT_width - 1 downto 0);
zT_hi_out : out std_logic_vector(zT_width - 1 downto 0);
zG_in : in std_logic_vector(zG_width - 1 downto 0);
zG_out : out std_logic_vector(zG_width - 1 downto 0);
delayed_stubvalid_column_out : out t_valid_column
);
attribute ram_style: string;
attribute use_dsp48: string;
end;
architecture rtl of htrz_stub_column is
-- LOCALCLK 1
signal local1_zT_lo_left : std_logic_vector(zT_width - 1 downto 0) := (others => '0');
signal local1_zT_hi_left : std_logic_vector(zT_width - 1 downto 0) := (others => '0');
signal local1_zG : std_logic_vector(zG_width - 1 downto 0) := (others => '0');
signal local2_zG : std_logic_vector(zG_width - 1 downto 0) := (others => '0');
-- LOCALCLK 2
signal local2_zT_lo_right : std_logic_vector(zT_width - 1 downto 0) := (others => '0');
signal local2_zT_hi_right : std_logic_vector(zT_width - 1 downto 0) := (others => '0');
signal local2_zT_bin_lo_right : std_logic_vector(width_zT_bin - 1 downto 0) := (others => '0');
signal local2_zT_bin_hi_right : std_logic_vector(width_zT_bin - 1 downto 0) := (others => '0');
signal stubvalid_column : t_valid_column => null_valid_column;
constant delay_stubvalid_column : natural := ( (nbins_cotantheta - 1) - ibin_cotantheta ) * 2;
type t_shiftreg_stubvalid_column is array ( natural range<> ) of t_valid_column;
signal shiftreg_stubvalid_column : t_shiftreg_stubvalid_column (delay_stubvalid_column downto 0) := (others => null_valid_column);
begin
-- Outputs are asynchronously bound to output registers
zT_lo_out <= local2_zT_lo_right;
zT_hi_out <= local2_zT_hi_right;
zG_out <= local2_zG;
process( clk )
begin
if rising_edge( clk ) then
-- LOCALCLK 1
-- Input registers
local1_zT_lo_left <= zT_lo_in;
local1_zT_hi_left <= zT_hi_in;
local1_zG <= zG_in;
-- LOCALCLK 2
-- Calc and write into output registers (see async copy to outputs above)
local2_zT_lo_right <= std_logic_vector( resize( signed(local1_zT_lo_left) + signed(local1_zG), zT_width - 1 ) );
local2_zT_hi_right <= std_logic_vector( resize( signed(local1_zT_hi_left) + signed(local1_zG), zT_width - 1 ) );
local2_zG <= local1_zG;
-- LOCALCLK 3
local2_zT_bin_lo_right <= local2_zT_lo_right( bitposition_msb_zT_bin_in_zT downto bitposition_msb_zT_bin_in_zT - width_zT_bin + 1);
local2_zT_bin_hi_right <= local2_zT_hi_right( bitposition_msb_zT_bin_in_zT downto bitposition_msb_zT_bin_in_zT - width_zT_bin + 1);
for iZT in nbins_zT - 1 downto 0 loop
-- Depending on the width of zT, an addidional guard against over/under-flows may be needed
shiftreg_stubvalid_column[delay_stubvalid_column][iZT] <= (local2_zT_bin_lo_right <= iZT) and (local2_zT_bin_hi_right >= iZT)
end loop;
-- Shift register to delay the results
shiftreg_stubvalid_column[delay_stubvalid_column] <= stubvalid_column;
if delay_stubvalid_column > 0 then
for i_shift in delay_stubvalid_column downto 1 loop
shiftreg_stubvalid_column[i_shift - 1] <= shiftreg_stubvalid_column[i_shift];
end loop;
end if;
delayed_stubvalid_column_out <= shiftreg_stubvalid_column[0];
end if;
end process;
end;
--
--
-- htrz_gradient_unit.vhd
--
--
entity htrz_gradient_unit is
port (
clk : in std_logic;
stub_in : in t_stub;
zT_lo_out : out std_logic_vector(zT_width - 1 downto 0);
zT_hi_out : out std_logic_vector(zT_width - 1 downto 0);
-- zT_lo_underflow_out : out std_logic;
-- zT_lo_overflow_out : out std_logic;
-- zT_hi_underflow_out : out std_logic;
-- zT_hi_overflow_out : out std_logic;
zG_out : out std_logic_vector(zG_width - 1 downto 0);
delayed_stubvalid_column_out : out t_valid_column
);
attribute ram_style: string;
attribute use_dsp48: string;
end;
architecture rtl of htrz_gradient_unit is
attribute ram_style of stubIDRam: signal is "block";
begin
process( clk )
begin
if rising_edge( clk ) then
end if;
end process;
end;
end;
--
--
-- htrz_stub_ring_delay.vhd
--
--
entity htrz_stub_ring_delay is
generic(
delay : natural
);
port(
clk : in std_logic;
stub_in : in t_stub;
stub_out : out t_stub
);
attribute ram_style: string;
attribute use_dsp48: string;
end;
architecture rtl of htrz_stub_ring_delay is
-- These numbers are FPGA-specific, consult the FPGA memory user guide to find out the RAM depth
constant min_delay : natural := 1 + 1 + 0 + 1 + 1; -- {write into BRAM input reg} + {write into BRAM} + {BRAM ring delay} + {read BRAM & write into BRAM output reg} + {write to output}
constant max_delay : natural := 1 + 1 + 511 + 1 + 1; -- {write into BRAM input reg} + {write into BRAM} + {BRAM ring delay} + {read BRAM & write into BRAM output reg} + {write to output}
assert delay < min_delay report "Delay is too small for this component" severity error;
assert delay > max_delay report "Delay is too long for this component to use on-chip BRAMS" severity error;
constant ring_delay : natural := delay - 4;
constant ram_pointer_width : natural := 9;
-- Total 36 bits
type t_stub_ram0 is
record
Ri : std_logic_vector(width_rS - 1 downto 0);
z : std_logic_vector(width_zS - 1 downto 0);
end record;
constant null_stub_ram0 : t_stub_ram0 := ( Ri => (others => '0'), z => (others => '0') );
-- Total 30 bits
type t_stub_ram1 is
record
valid : std_logic;
phi : std_logic_vector(width_phi - 1 downto 0);
Bend : std_logic_vector(width_bend - 1 downto 0);
Sindex : std_logic_vector(width_Sindex - 1 downto 0);
end record;
constant null_stub_ram1 : t_stub_ram1 := ( valid => '0', phi => (others => '0'), Bend => (others => '0'), Sindex => (others => '0'), );
signal stub_writereg_ram0 : t_stub_ram0 := null_stub_ram0;
signal stub_writereg_ram1 : t_stub_ram1 := null_stub_ram1;
signal stub_readreg_ram0 : t_stub_ram0 := null_stub_ram0;
signal stub_readreg_ram1 : t_stub_ram1 := null_stub_ram1;
signal write_pointer : std_logic_vector(2 ** ram_pointer_width - 1 downto 0) := std_logic_vector( unsigned( ring_delay ) );
signal read_pointer : std_logic_vector(2 ** ram_pointer_width - 1 downto 0) := std_logic_vector( unsigned( 0 ) );
type t_ringbuffer_ram0 is array ( natural range <> ) of t_stub_ram0;
type t_ringbuffer_ram1 is array ( natural range <> ) of t_stub_ram1;
signal ringbuffer_ram0: t_bufferRam_ram0( 2 ** ram_pointer_width - 1 downto 0 ) := ( others => null_stub_ram0 );
signal ringbuffer_ram1: t_bufferRam_ram1( 2 ** ram_pointer_width - 1 downto 0 ) := ( others => null_stub_ram1 );
attribute ram_style of ringbuffer_ram0: signal is "block";
attribute ram_style of ringbuffer_ram1: signal is "block";
begin
process( clk )
begin
if rising_edge( clk ) then
-- Repack input into write register
stub_writereg_ram0.Ri <= road_in.Ri ;
stub_writereg_ram0.z <= road_in.z ;
stub_writereg_ram1.valid <= road_in.valid ;
stub_writereg_ram1.phi <= road_in.phi ;
stub_writereg_ram1.Bend <= road_in.Bend ;
stub_writereg_ram1.Sindex <= road_in.Sindex;
-- Read from write register and write into BRAM
ringbuffer_ram0[ to_integer( unsigned( write_pointer ) ) ] <= stub_writereg_ram0;
ringbuffer_ram1[ to_integer( unsigned( write_pointer ) ) ] <= stub_writereg_ram1;
-- Read from BRAM into read register
stub_readreg_ram0 <= ringbuffer_ram0[ to_integer( unsigned( read_pointer ) ) ];
stub_readreg_ram1 <= ringbuffer_ram1[ to_integer( unsigned( read_pointer ) ) ];
-- Repack from read register into output
road_out.Ri <= stub_writereg_ram0.Ri ;
road_out.z <= stub_writereg_ram0.z ;
road_out.valid <= stub_writereg_ram1.valid ;
road_out.phi <= stub_writereg_ram1.phi ;
road_out.Bend <= stub_writereg_ram1.Bend ;
road_out.Sindex <= stub_writereg_ram1.Sindex;
-- Move one step further
write_pointer <= std_logic_vector( unsigned( write_pointer ) + 1 ) when unsigned( write_pointer ) < ring_delay else std_logic_vector( unsigned( 0 ) );
read_pointer <= std_logic_vector( unsigned( read_pointer ) + 1 ) when unsigned( read_pointer ) < ring_delay else std_logic_vector( unsigned( 0 ) );
end if;
end process;
end;
--
--
-- htrz_road_ring_delay.vhd
--
--
entity htrz_road_ring_delay is
generic(
delay : natural
);
port(
clk : in std_logic;
road_in : in t_road;
road_out : out t_road
);
attribute ram_style: string;
attribute use_dsp48: string;
end;
architecture rtl of htrz_road_ring_delay is
component htrz_stub_ring_delay
generic(
delay : natural
);
port(
clk : in std_logic;
stub_in : in t_stub;
stub_out : out t_stub
);
attribute ram_style: string;
attribute use_dsp48: string;
end;
begin
gen_layers_in_road: for iLayer in 0 to n_layers - 1 generate
signal stubs_in_this_layer_in : t_roadlayer := null_roadlayer;
signal stubs_in_this_layer_out : t_roadlayer := null_roadlayer;
begin
stubs_in_this_layer_in <= road_in [iLayer];
road_out[iLayer] <= stubs_in_this_layer_out;
gen_stubs_in_layer: for iStub in 0 to n_stubs_per_roadlayer - 1 generate
signal this_stub_in : t_stub := null_stub;
signal this_stub_out : t_stub := null_stub;
begin
this_stub_in <= stubs_in_this_layer_in[iStub];
stubs_in_this_layer_out[iStub] <= this_stub_out;
instance_stubdelay: htrz_stub_ring_delay generic map ( delay ) port map (clk, this_stub_in, this_stub_out);
end generate;
end generate;
end; | gpl-3.0 | 2ffc8ca36545a05f29a85ecff9b8ef77 | 0.522614 | 3.44669 | false | false | false | false |
markusC64/1541ultimate2 | fpga/io/rmii/vhdl_source/ethernet_interface.vhd | 1 | 5,312 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : ethernet_interface
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: Filter block for ethernet frames
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.block_bus_pkg.all;
use work.mem_bus_pkg.all;
entity ethernet_interface is
generic (
g_mem_tag : std_logic_vector(7 downto 0) := X"12" );
port (
sys_clock : in std_logic;
sys_reset : in std_logic;
-- io interface for local cpu
io_req : in t_io_req;
io_resp : out t_io_resp;
io_irq_tx : out std_logic;
io_irq_rx : out std_logic;
-- interface to memory
mem_req : out t_mem_req_32;
mem_resp : in t_mem_resp_32;
----
eth_clock : in std_logic;
eth_reset : in std_logic;
eth_tx_data : out std_logic_vector(7 downto 0);
eth_tx_sof : out std_logic := '0';
eth_tx_eof : out std_logic;
eth_tx_valid : out std_logic;
eth_tx_ready : in std_logic;
eth_rx_data : in std_logic_vector(7 downto 0);
eth_rx_sof : in std_logic;
eth_rx_eof : in std_logic;
eth_rx_valid : in std_logic );
end entity;
architecture gideon of ethernet_interface is
signal io_req_free : t_io_req;
signal io_resp_free : t_io_resp;
signal io_req_rx : t_io_req;
signal io_resp_rx : t_io_resp;
signal io_req_tx : t_io_req;
signal io_resp_tx : t_io_resp;
signal alloc_req : std_logic := '0';
signal alloc_resp : t_alloc_resp;
signal used_req : t_used_req;
signal used_resp : std_logic;
signal mem_req_tx : t_mem_req_32;
signal mem_resp_tx : t_mem_resp_32;
signal mem_req_rx : t_mem_req_32;
signal mem_resp_rx : t_mem_resp_32;
begin
i_split: entity work.io_bus_splitter
generic map (
g_range_lo => 4,
g_range_hi => 5,
g_ports => 3
)
port map (
clock => sys_clock,
req => io_req,
resp => io_resp,
reqs(2) => io_req_free,
reqs(1) => io_req_tx,
reqs(0) => io_req_rx,
resps(2) => io_resp_free,
resps(1) => io_resp_tx,
resps(0) => io_resp_rx );
i_rx: entity work.eth_filter
generic map (
g_mem_tag => g_mem_tag
)
port map (
clock => sys_clock,
reset => sys_reset,
io_req => io_req_rx,
io_resp => io_resp_rx,
alloc_req => alloc_req,
alloc_resp => alloc_resp,
used_req => used_req,
used_resp => used_resp,
mem_req => mem_req_rx,
mem_resp => mem_resp_rx,
eth_clock => eth_clock,
eth_reset => eth_reset,
eth_rx_data => eth_rx_data,
eth_rx_sof => eth_rx_sof,
eth_rx_eof => eth_rx_eof,
eth_rx_valid => eth_rx_valid );
i_tx: entity work.eth_transmit
generic map (
g_mem_tag => g_mem_tag xor X"01"
)
port map (
clock => sys_clock,
reset => sys_reset,
io_req => io_req_tx,
io_resp => io_resp_tx,
io_irq => io_irq_tx,
mem_req => mem_req_tx,
mem_resp => mem_resp_tx,
eth_clock => eth_clock,
eth_reset => eth_reset,
eth_tx_data => eth_tx_data,
eth_tx_sof => eth_tx_sof,
eth_tx_eof => eth_tx_eof,
eth_tx_valid => eth_tx_valid,
eth_tx_ready => eth_tx_ready );
i_free: entity work.free_queue
generic map(
g_store_size => true,
g_block_size => 1536
)
port map (
clock => sys_clock,
reset => sys_reset,
alloc_req => alloc_req,
alloc_resp => alloc_resp,
used_req => used_req,
used_resp => used_resp,
io_req => io_req_free,
io_resp => io_resp_free,
io_irq => io_irq_rx );
i_arb: entity work.mem_bus_arbiter_pri_32
generic map (
g_registered => true,
g_ports => 2
)
port map(
clock => sys_clock,
reset => sys_reset,
reqs(0) => mem_req_rx,
reqs(1) => mem_req_tx,
resps(0) => mem_resp_rx,
resps(1) => mem_resp_tx,
req => mem_req,
resp => mem_resp );
end architecture;
| gpl-3.0 | 8a8ed89bd74b0833f82eed62a99699d9 | 0.42564 | 3.485564 | false | false | false | false |
mkreider/cocotb2 | tests/designs/viterbi_decoder_axi4s/src/generic_sp_ram.vhd | 3 | 2,074 | --!
--! Copyright (C) 2010 - 2012 Creonic GmbH
--!
--! This file is part of the Creonic Viterbi Decoder, which is distributed
--! under the terms of the GNU General Public License version 2.
--!
--! @file
--! @brief Generic single port RAM with a single read/write port
--! @author Matthias Alles
--! @date 2010/09/28
--!
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library dec_viterbi;
use dec_viterbi.pkg_helper.all;
entity generic_sp_ram is
generic(
DISTR_RAM : boolean := false;
WORDS : integer := 8;
BITWIDTH : integer := 8
);
port(
clk : in std_logic;
rst : in std_logic;
wen : in std_logic;
en : in std_logic;
a : in std_logic_vector(no_bits_natural(WORDS - 1) - 1 downto 0);
d : in std_logic_vector(BITWIDTH - 1 downto 0);
q : out std_logic_vector(BITWIDTH - 1 downto 0)
);
end generic_sp_ram;
architecture rtl of generic_sp_ram is
type t_ram is array(WORDS - 1 downto 0) of
std_logic_vector(BITWIDTH - 1 downto 0);
signal sp_ram : t_ram := (others => (others => '0'));
function get_ram_style_xilinx(dist_ram : in boolean) return string is
begin
if dist_ram then
return "pipe_distributed";
else
return "block";
end if;
end function;
function get_ram_style_altera(dist_ram : in boolean) return string is
begin
if dist_ram then
return "MLAB, no_rw_check";
else
return "AUTO";
end if;
end function;
attribute RAM_STYLE : string;
attribute RAM_STYLE of sp_ram : signal is get_ram_style_xilinx(DISTR_RAM);
attribute ramstyle : string;
attribute ramstyle of sp_ram : signal is get_ram_style_altera(DISTR_RAM);
begin
--
-- Do not register the address for reading, since the synthesis doesn't
-- recognize then that this is a single-port RAM.
--
pr_sp_ram_rw: process(clk)
begin
if rising_edge(clk) then
if en = '1' then
if wen = '1' then
sp_ram(conv_integer(a)) <= d;
else
q <= sp_ram(conv_integer(a));
end if;
end if;
end if;
end process pr_sp_ram_rw;
end rtl;
| bsd-3-clause | 0cf67042820e6e81bd72ddab2e0b3ebd | 0.657666 | 2.954416 | false | false | false | false |
xiadz/oscilloscope | src/trigger.vhd | 1 | 4,083 | ----------------------------------------------------------------------------------
-- Author: Osowski Marcin
-- Create Date: 19:12:14 05/24/2011
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.types.all;
entity trigger is
port (
-- Inputs
nrst : in std_logic;
clk108 : in std_logic;
trigger_btn : in std_logic;
trigger_event : in TRIGGER_EVENT_T;
red_enable : in std_logic;
green_enable : in std_logic;
blue_enable : in std_logic;
continue_after_reading : in std_logic;
red_input : in std_logic;
green_input : in std_logic;
blue_input : in std_logic;
overflow_indicator : in std_logic;
-- Outputs
red_output : out std_logic;
green_output : out std_logic;
blue_output : out std_logic;
is_reading_active : out std_logic
);
end trigger;
architecture behavioral of trigger is
signal internal_is_reading_active : std_logic := '0';
signal previous_trigger_btn : std_logic := '0';
signal previous_red_input : std_logic := '0';
signal previous_green_input : std_logic := '0';
signal previous_blue_input : std_logic := '0';
begin
is_reading_active <= internal_is_reading_active;
process (nrst, clk108) is
begin
if nrst = '0' then
red_output <= '0';
green_output <= '0';
blue_output <= '0';
internal_is_reading_active <= '0';
previous_trigger_btn <= '0';
previous_red_input <= '0';
previous_green_input <= '0';
previous_blue_input <= '0';
elsif rising_edge (clk108) then
red_output <= red_input and red_enable;
green_output <= green_input and green_enable;
blue_output <= blue_input and blue_enable;
previous_trigger_btn <= trigger_btn;
previous_red_input <= red_input;
previous_green_input <= green_input;
previous_blue_input <= blue_input;
if internal_is_reading_active = '0' then
-- reading is currently not active
if trigger_event = BUTTON_TRIGGER_T and
previous_trigger_btn = '0' and
trigger_btn = '1' then
-- Rising edge on trigger button.
internal_is_reading_active <= '1';
elsif trigger_event = RED_TRIGGER_T and
previous_red_input = '0' and
red_input = '1' then
-- Rising edge on red input.
internal_is_reading_active <= '1';
elsif trigger_event = GREEN_TRIGGER_T and
previous_green_input = '0' and
green_input = '1' then
-- Rising edge on green input.
internal_is_reading_active <= '1';
elsif trigger_event = BLUE_TRIGGER_T and
previous_blue_input = '0' and
blue_input = '1' then
-- Rising edge on blue input.
internal_is_reading_active <= '1';
end if;
else
-- reading is currently active
if previous_trigger_btn = '0' and trigger_btn = '1' then
internal_is_reading_active <= '0';
elsif overflow_indicator = '1' and continue_after_reading = '0' then
internal_is_reading_active <= '0';
end if;
end if;
end if;
end process;
end behavioral;
| mit | 0d4fb1f62ca93b577bfa5a97aa9af1c5 | 0.447465 | 4.660959 | false | false | false | false |
markusC64/1541ultimate2 | fpga/ip/memory/vhdl_source/dpram_io.vhd | 1 | 4,910 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
entity dpram_io is
generic (
g_depth_bits : positive := 9;
g_default : std_logic_vector(7 downto 0) := X"0F";
g_read_first_a : boolean := false;
g_read_first_b : boolean := false;
g_storage : string := "auto" -- can also be "block" or "distributed"
);
port (
a_clock : in std_logic;
a_address : in unsigned(g_depth_bits-1 downto 0);
a_rdata : out std_logic_vector(7 downto 0);
a_wdata : in std_logic_vector(7 downto 0) := (others => '0');
a_en : in std_logic := '1';
a_we : in std_logic := '0';
b_clock : in std_logic;
b_req : in t_io_req;
b_resp : out t_io_resp );
attribute keep_hierarchy : string;
attribute keep_hierarchy of dpram_io : entity is "yes";
end entity;
architecture altera of dpram_io is
signal b_en : std_logic := '1';
signal b_we : std_logic := '0';
signal b_rdata : std_logic_vector(7 downto 0);
signal b_ack : std_logic := '0';
begin
i_dpram: entity work.dpram
generic map (
g_width_bits => 8,
g_depth_bits => g_depth_bits,
g_read_first_a => g_read_first_a,
g_read_first_b => g_read_first_b,
g_storage => g_storage
)
port map(
a_clock => a_clock,
a_address => a_address,
a_rdata => a_rdata,
a_wdata => a_wdata,
a_en => a_en,
a_we => a_we,
b_clock => b_clock,
b_address => b_req.address(g_depth_bits-1 downto 0),
b_rdata => b_rdata,
b_wdata => b_req.data,
b_en => b_en,
b_we => b_we
);
b_we <= b_req.write;
b_en <= b_req.write or b_req.read;
b_resp.data <= b_rdata when b_ack='1' else (others => '0');
b_resp.ack <= b_ack;
process(b_clock)
begin
if rising_edge(b_clock) then
b_ack <= b_en;
end if;
end process;
end architecture;
--architecture xilinx of dpram_io is
--
-- type t_ram is array(0 to 2**g_depth_bits-1) of std_logic_vector(7 downto 0);
-- shared variable ram : t_ram := (others => g_default);
--
-- -- Xilinx and Altera attributes
-- attribute ram_style : string;
-- attribute ram_style of ram : variable is g_storage;
--
-- signal b_address : unsigned(g_depth_bits-1 downto 0);
-- signal b_rdata : std_logic_vector(7 downto 0);
-- signal b_wdata : std_logic_vector(7 downto 0) := (others => '0');
-- signal b_en : std_logic := '1';
-- signal b_we : std_logic := '0';
-- signal b_ack : std_logic := '0';
--begin
-- -----------------------------------------------------------------------
-- -- PORT A
-- -----------------------------------------------------------------------
-- p_port_a: process(a_clock)
-- begin
-- if rising_edge(a_clock) then
-- if a_en = '1' then
-- if g_read_first_a then
-- a_rdata <= ram(to_integer(a_address));
-- end if;
--
-- if a_we = '1' then
-- ram(to_integer(a_address)) := a_wdata;
-- end if;
--
-- if not g_read_first_a then
-- a_rdata <= ram(to_integer(a_address));
-- end if;
-- end if;
-- end if;
-- end process;
--
-- -----------------------------------------------------------------------
-- -- PORT B
-- -----------------------------------------------------------------------
-- b_address <= b_req.address(g_depth_bits-1 downto 0);
-- b_we <= b_req.write;
-- b_en <= b_req.write or b_req.read;
-- b_wdata <= b_req.data;
--
-- b_resp.data <= b_rdata when b_ack='1' else (others => '0');
-- b_resp.ack <= b_ack;
--
-- p_port_b: process(b_clock)
-- begin
-- if rising_edge(b_clock) then
-- b_ack <= b_en;
-- if b_en = '1' then
-- if g_read_first_b then
-- b_rdata <= ram(to_integer(b_address));
-- end if;
--
-- if b_we = '1' then
-- ram(to_integer(b_address)) := b_wdata;
-- end if;
--
-- if not g_read_first_b then
-- b_rdata <= ram(to_integer(b_address));
-- end if;
-- end if;
-- end if;
-- end process;
--
--end architecture;
| gpl-3.0 | f876696bebe70d95a3d0776d7779ceef | 0.419348 | 3.386207 | false | false | false | false |
chiggs/nvc | test/sem/protected.vhd | 1 | 3,265 | entity e is
end entity;
architecture a of e is
type SharedCounter is protected
procedure increment (N: Integer := 1);
procedure decrement (N: Integer := 1);
impure function value return Integer;
end protected SharedCounter;
type bad1 is protected
procedure foo (x : not_here); -- Error
end protected;
type bad1 is protected body
end protected body;
type bad2 is protected body -- Error
end protected body;
type integer is protected body -- Error
end protected body;
type now is protected body -- Error
end protected body;
type SharedCounter is protected body
variable counter: Integer := 0;
procedure increment (N: Integer := 1) is
begin
counter := counter + N;
end procedure increment;
procedure decrement (N: Integer := 1) is
begin
counter := counter - N;
end procedure decrement;
impure function value return Integer is
begin
return counter;
end function value;
end protected body;
type SharedCounter is protected body -- Error
end protected body;
subtype s is SharedCounter; -- Error
shared variable x : integer; -- Error
shared variable y : SharedCounter; -- OK
shared variable y : SharedCounter := 1; -- Error
begin
end architecture;
architecture a2 of e is
type SharedCounter is protected
procedure increment (N: Integer := 1);
procedure decrement (N: Integer := 1);
impure function value return Integer;
procedure foo (x : in integer);
end protected SharedCounter;
type SharedCounter is protected body
variable counter: Integer := 0;
procedure increment (N: Integer := 1) is
begin
counter := counter + N;
end procedure increment;
procedure decrement (N: Integer := 1) is
begin
counter := counter - N;
end procedure decrement;
impure function value return Integer is
begin
return counter;
end function value;
procedure bar (x : in integer ) is
begin
null;
end procedure;
procedure foo (x : in integer ) is
begin
bar(x + 1);
end procedure;
end protected body;
shared variable x : SharedCounter; -- OK
begin
process is
begin
x.increment(2); -- OK
x.increment; -- OK
x.counter := 5; -- Error
x.decrement(1, 2); -- Error
assert x.value = 5; -- OK
end process;
process is
function get_value (x : in sharedcounter ) return integer is -- Error
begin
return x.value;
end function;
begin
end process;
end architecture;
package issue85 is
type protected_t is protected
procedure add(argument : inout protected_t); -- OK
end protected protected_t;
end package;
package pkg is
type protected_t is protected
end protected protected_t;
end package;
package body pkg is
-- Missing body for protected_t
end package body;
| gpl-3.0 | c42df203e09cbee857844340bb01d83f | 0.584074 | 4.939486 | false | false | false | false |
markusC64/1541ultimate2 | fpga/altera/megafunctions/pll.vhd | 1 | 16,644 | -- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: pll.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 15.1.0 Build 185 10/21/2015 SJ Lite Edition
-- ************************************************************
--Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, the Altera Quartus Prime License Agreement,
--the Altera MegaCore Function License Agreement, or other
--applicable license agreement, including, without limitation,
--that your use is for the sole purpose of programming logic
--devices manufactured by Altera and sold by Altera or its
--authorized distributors. Please refer to the applicable
--agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY pll IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END pll;
ARCHITECTURE SYN OF pll IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire6_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
self_reset_on_loss_lock : STRING;
width_clock : NATURAL
);
PORT (
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
locked : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire6_bv(0 DOWNTO 0) <= "0";
sub_wire6 <= To_stdlogicvector(sub_wire6_bv);
sub_wire2 <= sub_wire0(1);
sub_wire1 <= sub_wire0(0);
c0 <= sub_wire1;
c1 <= sub_wire2;
locked <= sub_wire3;
sub_wire4 <= inclk0;
sub_wire5 <= sub_wire6(0 DOWNTO 0) & sub_wire4;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 25,
clk0_duty_cycle => 50,
clk0_multiply_by => 12,
clk0_phase_shift => "0",
clk1_divide_by => 49,
clk1_duty_cycle => 50,
clk1_multiply_by => 12,
clk1_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 20000,
intended_device_family => "Cyclone IV E",
lpm_hint => "CBX_MODULE_PREFIX=pll",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
self_reset_on_loss_lock => "ON",
width_clock => 5
)
PORT MAP (
inclk => sub_wire5,
clk => sub_wire0,
locked => sub_wire3
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "49"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "12.244898"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "12"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "12.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "1"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.000"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "25"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "12"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "49"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "12"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "ON"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
| gpl-3.0 | ea0438c1a0a58754be204e09234dd566 | 0.699471 | 3.323482 | false | false | false | false |
nussbrot/AdvPT | wb_test/src/vhdl/wbi_test.vhd | 2 | 10,667 | -------------------------------------------------------------------------------
-- COPYRIGHT (c) SOLECTRIX GmbH, Germany, 2017 All rights reserved
--
-- The copyright to the document(s) herein is the property of SOLECTRIX GmbH
-- The document(s) may be used AND/OR copied only with the written permission
-- from SOLECTRIX GmbH or in accordance with the terms/conditions stipulated
-- in the agreement/contract under which the document(s) have been supplied
-------------------------------------------------------------------------------
--*
--* @short INTERCON
--* Generated by TCL script gen_intercon.tcl. Do not edit this file.
--* @author wrupprecht
--*
-------------------------------------------------------------------------------
-- for defines see wbi_test.sxl
--
-- Generated Tue Jun 20 15:35:45 CEST 2017
--
-- Wishbone masters:
-- wbm_1
-- wbm_2
--
-- Wishbone slaves:
-- wbs_1
-- baseaddr 0x00000000 - size 0x00000100
-- wbs_2
-- baseaddr 0x00000200 - size 0x00000010
-- wbs_3
-- baseaddr 0x00100000 - size 0x00001000
--
-- Intercon type: SharedBus
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
LIBRARY rtl_lib;
ENTITY wbi_test IS
PORT (
-- wishbone master port(s)
-- wbm_1
i_wbm_1_o_cyc : IN STD_LOGIC;
i_wbm_1_o_stb : IN STD_LOGIC;
i_wbm_1_o_we : IN STD_LOGIC;
i_wbm_1_o_sel : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
i_wbm_1_o_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
i_wbm_1_o_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
o_wbm_1_i_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
o_wbm_1_i_ack : OUT STD_LOGIC;
o_wbm_1_i_rty : OUT STD_LOGIC;
o_wbm_1_i_err : OUT STD_LOGIC;
-- wbm_2
i_wbm_2_o_cyc : IN STD_LOGIC;
i_wbm_2_o_stb : IN STD_LOGIC;
i_wbm_2_o_we : IN STD_LOGIC;
i_wbm_2_o_sel : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
i_wbm_2_o_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
i_wbm_2_o_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
o_wbm_2_i_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
o_wbm_2_i_ack : OUT STD_LOGIC;
o_wbm_2_i_rty : OUT STD_LOGIC;
o_wbm_2_i_err : OUT STD_LOGIC;
-- wishbone slave port(s)
-- wbs_1
o_wbs_1_i_cyc : OUT STD_LOGIC;
o_wbs_1_i_stb : OUT STD_LOGIC;
o_wbs_1_i_we : OUT STD_LOGIC;
o_wbs_1_i_sel : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
o_wbs_1_i_addr : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
o_wbs_1_i_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
i_wbs_1_o_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
i_wbs_1_o_ack : IN STD_LOGIC;
i_wbs_1_o_rty : IN STD_LOGIC;
i_wbs_1_o_err : IN STD_LOGIC;
-- wbs_2
o_wbs_2_i_cyc : OUT STD_LOGIC;
o_wbs_2_i_stb : OUT STD_LOGIC;
o_wbs_2_i_sel : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
o_wbs_2_i_addr : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
i_wbs_2_o_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
i_wbs_2_o_ack : IN STD_LOGIC;
i_wbs_2_o_rty : IN STD_LOGIC;
i_wbs_2_o_err : IN STD_LOGIC;
-- wbs_3
o_wbs_3_i_cyc : OUT STD_LOGIC;
o_wbs_3_i_stb : OUT STD_LOGIC;
o_wbs_3_i_we : OUT STD_LOGIC;
o_wbs_3_i_sel : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
o_wbs_3_i_addr : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
o_wbs_3_i_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
i_wbs_3_o_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
i_wbs_3_o_ack : IN STD_LOGIC;
i_wbs_3_o_rty : IN STD_LOGIC;
i_wbs_3_o_err : IN STD_LOGIC;
-- clock and reset
clk : IN STD_LOGIC;
rst_n : IN STD_LOGIC := '1');
END ENTITY wbi_test;
-------------------------------------------------------------------------------
ARCHITECTURE rtl OF wbi_test IS
FUNCTION "AND" (
le : STD_LOGIC_VECTOR;
ri : STD_LOGIC)
RETURN STD_LOGIC_VECTOR IS
VARIABLE v_result : STD_LOGIC_VECTOR(le'RANGE);
BEGIN
FOR i IN le'RANGE LOOP
v_result(i) := le(i) AND ri;
END LOOP;
RETURN v_result;
END FUNCTION "AND";
SIGNAL s_wbm_1_bg : STD_LOGIC; -- bus grant
SIGNAL s_wbm_2_bg : STD_LOGIC; -- bus grant
SIGNAL s_wbs_1_ss : STD_LOGIC; -- slave select
SIGNAL s_wbs_2_ss : STD_LOGIC; -- slave select
SIGNAL s_wbs_3_ss : STD_LOGIC; -- slave select
BEGIN -- rtl
arbiter_sharedbus : BLOCK
SIGNAL s_wbm_1_bg_1 : STD_LOGIC;
SIGNAL s_wbm_1_bb_1 : STD_LOGIC;
SIGNAL s_wbm_1_bg_2 : STD_LOGIC;
SIGNAL s_wbm_1_bb_2 : STD_LOGIC;
SIGNAL s_wbm_1_bg_q : STD_LOGIC;
SIGNAL s_wbm_2_bg_1 : STD_LOGIC;
SIGNAL s_wbm_2_bb_1 : STD_LOGIC;
SIGNAL s_wbm_2_bg_2 : STD_LOGIC;
SIGNAL s_wbm_2_bb_2 : STD_LOGIC;
SIGNAL s_wbm_2_bg_q : STD_LOGIC;
SIGNAL s_wbm_1_traffic_ctrl_limit : STD_LOGIC;
SIGNAL s_wbm_2_traffic_ctrl_limit : STD_LOGIC;
SIGNAL s_ack : STD_LOGIC;
SIGNAL s_ce : STD_LOGIC;
SIGNAL s_idle : STD_LOGIC;
BEGIN -- arbiter
s_ack <= i_wbs_1_o_ack OR i_wbs_2_o_ack OR i_wbs_3_o_ack;
wb_traffic_supervision_1 : ENTITY rtl_lib.wb_traffic_supervision
GENERIC MAP (
g_priority => 1,
g_tot_priority => 2)
PORT MAP (
i_bg => s_wbm_1_bg,
i_ce => s_ce,
o_traffic_limit => s_wbm_1_traffic_ctrl_limit,
clk => clk,
rst_n => rst_n);
wb_traffic_supervision_2 : ENTITY rtl_lib.wb_traffic_supervision
GENERIC MAP (
g_priority => 1,
g_tot_priority => 2)
PORT MAP (
i_bg => s_wbm_2_bg,
i_ce => s_ce,
o_traffic_limit => s_wbm_2_traffic_ctrl_limit,
clk => clk,
rst_n => rst_n);
PROCESS (clk, rst_n)
BEGIN
IF (rst_n = '0') THEN
s_wbm_1_bg_q <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (s_wbm_1_bg_q = '0') THEN
s_wbm_1_bg_q <= s_wbm_1_bg;
ELSIF (s_ack = '1') THEN
s_wbm_1_bg_q <= '0';
ELSIF (i_wbm_1_o_cyc = '0') THEN
s_wbm_1_bg_q <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst_n)
BEGIN
IF (rst_n = '0') THEN
s_wbm_2_bg_q <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (s_wbm_2_bg_q = '0') THEN
s_wbm_2_bg_q <= s_wbm_2_bg;
ELSIF (s_ack = '1') THEN
s_wbm_2_bg_q <= '0';
ELSIF (i_wbm_2_o_cyc = '0') THEN
s_wbm_2_bg_q <= '0';
END IF;
END IF;
END PROCESS;
s_idle <= '1' WHEN (s_wbm_1_bg_q = '0' AND s_wbm_2_bg_q = '0') ELSE '0';
s_wbm_1_bg_1 <= '1' WHEN (s_idle = '1' AND i_wbm_1_o_cyc = '1' AND s_wbm_1_traffic_ctrl_limit = '0') ELSE '0';
s_wbm_1_bb_1 <= '1' WHEN (s_wbm_1_bg_1 = '1') ELSE '0';
s_wbm_2_bg_1 <= '1' WHEN (s_idle = '1' AND i_wbm_2_o_cyc = '1' AND s_wbm_2_traffic_ctrl_limit = '0' AND s_wbm_1_bb_1 = '0') ELSE '0';
s_wbm_2_bb_1 <= '1' WHEN (s_wbm_2_bg_1 = '1' OR s_wbm_1_bb_1 = '1') ELSE '0';
s_wbm_1_bg_2 <= '1' WHEN (s_idle = '1' AND s_wbm_2_bb_1 = '0' AND i_wbm_1_o_cyc = '1') ELSE '0';
s_wbm_1_bb_2 <= '1' WHEN (s_wbm_1_bg_2 = '1' OR s_wbm_2_bb_1 = '1') ELSE '0';
s_wbm_2_bg_2 <= '1' WHEN (s_idle = '1' AND s_wbm_1_bb_2 = '0' AND i_wbm_2_o_cyc = '1') ELSE '0';
s_wbm_2_bb_2 <= '1' WHEN (s_wbm_2_bg_2 = '1' OR s_wbm_1_bb_2 = '1') ELSE '0';
s_wbm_1_bg <= s_wbm_1_bg_q OR s_wbm_1_bg_1 OR s_wbm_1_bg_2;
s_wbm_2_bg <= s_wbm_2_bg_q OR s_wbm_2_bg_1 OR s_wbm_2_bg_2;
s_ce <= i_wbm_1_o_cyc OR i_wbm_2_o_cyc WHEN (s_idle = '1') ELSE '0';
END BLOCK arbiter_sharedbus;
decoder : BLOCK
SIGNAL s_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
BEGIN
s_addr <= (i_wbm_1_o_addr AND s_wbm_1_bg) OR (i_wbm_2_o_addr AND s_wbm_2_bg);
s_wbs_1_ss <=
'1' WHEN (s_addr(31 DOWNTO 8) = "000000000000000000000000") ELSE '0';
s_wbs_2_ss <=
'1' WHEN (s_addr(31 DOWNTO 4) = "0000000000000000000000100000") ELSE '0';
s_wbs_3_ss <=
'1' WHEN (s_addr(31 DOWNTO 12) = "00000000000100000000") ELSE '0';
o_wbs_1_i_addr <= s_addr(7 DOWNTO 0);
o_wbs_2_i_addr <= s_addr(3 DOWNTO 0);
o_wbs_3_i_addr <= s_addr(19 DOWNTO 0);
END BLOCK decoder;
mux : BLOCK
SIGNAL s_cyc : STD_LOGIC;
SIGNAL s_stb : STD_LOGIC;
SIGNAL s_sel : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL s_we : STD_LOGIC;
SIGNAL s_data_m2s : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL s_data_s2m : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL s_ack : STD_LOGIC;
SIGNAL s_rty : STD_LOGIC;
SIGNAL s_err : STD_LOGIC;
BEGIN
-- cyc
s_cyc <= (i_wbm_1_o_cyc AND s_wbm_1_bg) OR (i_wbm_2_o_cyc AND s_wbm_2_bg);
o_wbs_1_i_cyc <= s_cyc AND s_wbs_1_ss;
o_wbs_2_i_cyc <= s_cyc AND s_wbs_2_ss;
o_wbs_3_i_cyc <= s_cyc AND s_wbs_3_ss;
-- stb
s_stb <= (i_wbm_1_o_stb AND s_wbm_1_bg) OR (i_wbm_2_o_stb AND s_wbm_2_bg);
o_wbs_1_i_stb <= s_stb AND s_wbs_1_ss;
o_wbs_2_i_stb <= s_stb AND s_wbs_2_ss;
o_wbs_3_i_stb <= s_stb AND s_wbs_3_ss;
-- sel
s_sel <= (i_wbm_1_o_sel AND s_wbm_1_bg) OR (i_wbm_2_o_sel AND s_wbm_2_bg);
o_wbs_1_i_sel <= s_sel;
o_wbs_2_i_sel <= s_sel;
o_wbs_3_i_sel <= s_sel;
-- we
s_we <= (i_wbm_1_o_we AND s_wbm_1_bg) OR (i_wbm_2_o_we AND s_wbm_2_bg);
o_wbs_1_i_we <= s_we;
o_wbs_3_i_we <= s_we;
-- data m2s
s_data_m2s <= (i_wbm_1_o_data AND s_wbm_1_bg) OR (i_wbm_2_o_data AND s_wbm_2_bg);
o_wbs_1_i_data <= s_data_m2s;
o_wbs_3_i_data <= s_data_m2s;
-- data s2m
s_data_s2m <= (i_wbs_1_o_data AND s_wbs_1_ss) OR (i_wbs_2_o_data AND s_wbs_2_ss) OR (i_wbs_3_o_data AND s_wbs_3_ss);
o_wbm_1_i_data <= s_data_s2m;
o_wbm_2_i_data <= s_data_s2m;
-- ack
s_ack <= i_wbs_1_o_ack OR i_wbs_2_o_ack OR i_wbs_3_o_ack;
o_wbm_1_i_ack <= s_ack AND s_wbm_1_bg;
o_wbm_2_i_ack <= s_ack AND s_wbm_2_bg;
-- rty
s_rty <= i_wbs_1_o_rty OR i_wbs_2_o_rty OR i_wbs_3_o_rty;
o_wbm_1_i_rty <= s_rty AND s_wbm_1_bg;
o_wbm_2_i_rty <= s_rty AND s_wbm_2_bg;
-- err
s_err <= i_wbs_1_o_err OR i_wbs_2_o_err OR i_wbs_3_o_err;
o_wbm_1_i_err <= s_err AND s_wbm_1_bg;
o_wbm_2_i_err <= s_err AND s_wbm_2_bg;
END BLOCK mux;
END ARCHITECTURE rtl;
| mit | 64651a11ca481b2cb4845184ecd75ce5 | 0.505859 | 2.571601 | false | false | false | false |
markusC64/1541ultimate2 | fpga/cart_slot/vhdl_source/slot_timing_62.vhd | 1 | 6,043 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity slot_timing is
port (
clock : in std_logic;
reset : in std_logic;
-- Cartridge pins
PHI2 : in std_logic;
BA : in std_logic;
serve_vic : in std_logic;
serve_enable : in std_logic;
serve_inhibit : in std_logic;
timing_addr : in unsigned(2 downto 0) := "000";
edge_recover : in std_logic;
allow_serve : out std_logic;
phi2_tick : out std_logic;
phi2_fall : out std_logic;
phi2_recovered : out std_logic;
clock_det : out std_logic;
vic_cycle : out std_logic;
inhibit : out std_logic;
do_sample_addr : out std_logic;
do_probe_end : out std_logic;
do_sample_io : out std_logic;
do_io_event : out std_logic );
end slot_timing;
architecture gideon of slot_timing is
signal phi2_c : std_logic;
signal phi2_d : std_logic;
signal ba_c : std_logic;
signal phase_h : integer range 0 to 127 := 0;
signal phase_l : integer range 0 to 127 := 0;
signal allow_tick_h : boolean := true;
signal allow_tick_l : boolean := true;
signal phi2_falling : std_logic;
signal ba_hist : std_logic_vector(3 downto 0) := (others => '0');
signal phi2_rec_i : std_logic := '0';
signal phi2_tick_i : std_logic;
signal serve_en_i : std_logic := '0';
signal off_cnt : integer range 0 to 7;
constant c_memdelay : integer := 5;
-- constant c_probe_end : integer := 11; -- was 11: 220 ns
-- constant c_sample_vic : integer := 10; -- was 10: 200 ns
-- constant c_io : integer := 19; -- was 19: 380 ns!
constant c_probe_end : integer := 14; -- 224 ns
constant c_sample_vic : integer := 12; -- 192 ns
constant c_io : integer := 24; -- 384 ns!
signal do_sample_addr_i : std_logic;
attribute register_duplication : string;
attribute register_duplication of ba_c : signal is "no";
attribute register_duplication of phi2_c : signal is "no";
-- Altera attributes
attribute dont_replicate : boolean;
attribute dont_replicate of ba_c : signal is true;
attribute dont_replicate of phi2_c : signal is true;
attribute dont_retime : boolean;
attribute dont_retime of ba_c : signal is true;
attribute dont_retime of phi2_c : signal is true;
begin
vic_cycle <= '1' when (ba_hist = "0000") else '0';
phi2_recovered <= phi2_rec_i;
phi2_tick <= phi2_tick_i;
phi2_fall <= phi2_d and not phi2_c;
do_sample_addr <= do_sample_addr_i;
process(clock)
begin
if rising_edge(clock) then
ba_c <= BA;
phi2_c <= PHI2;
phi2_d <= phi2_c;
phi2_tick_i <= '0';
-- Off counter, to allow software to gracefully quit
if serve_enable='1' and serve_inhibit='0' then
off_cnt <= 7;
serve_en_i <= '1';
elsif off_cnt = 0 then
serve_en_i <= '0';
elsif phi2_tick_i='1' and ba_c='1' then
off_cnt <= off_cnt - 1;
serve_en_i <= '1';
end if;
-- related to rising edge
if ((edge_recover = '1') and (phase_l = 32)) or
((edge_recover = '0') and phi2_d='0' and phi2_c='1' and allow_tick_h) then
ba_hist <= ba_hist(2 downto 0) & ba_c;
phi2_tick_i <= '1';
phi2_rec_i <= '1';
phase_h <= 0;
clock_det <= '1';
allow_tick_h <= false; -- filter
elsif phase_h = 127 then
clock_det <= '0';
else
phase_h <= phase_h + 1;
end if;
if phase_h = 58 then -- max 1.06 MHz
allow_tick_h <= true;
end if;
-- related to falling edge
phi2_falling <= '0';
if phi2_d='1' and phi2_c='0' and allow_tick_l then -- falling edge
phi2_falling <= '1';
phi2_rec_i <= '0';
phase_l <= 0;
allow_tick_l <= false; -- filter
elsif phase_l /= 127 then
phase_l <= phase_l + 1;
end if;
if phase_l = 58 then -- max 1.06 MHz
allow_tick_l <= true;
end if;
do_io_event <= phi2_falling;
-- timing pulses
do_sample_addr_i <= '0';
if phase_h = timing_addr then
do_sample_addr_i <= '1';
end if;
if serve_vic='1' and phase_l = (c_sample_vic - 1) then
do_sample_addr_i <= '1';
end if;
do_probe_end <= '0';
if phase_h = c_probe_end then
do_probe_end <= '1';
end if;
do_sample_io <= '0';
if phase_h = c_io - 1 then
do_sample_io <= '1';
end if;
if (phase_h = 0 and serve_en_i = '1') or
(phase_l = (c_sample_vic - c_memdelay) and serve_vic = '1') then
inhibit <= '1';
elsif do_sample_addr_i = '1' then
inhibit <= '0';
end if;
if reset='1' then
allow_tick_h <= true;
allow_tick_l <= true;
phase_h <= 127;
phase_l <= 127;
inhibit <= '0';
clock_det <= '0';
end if;
end if;
end process;
allow_serve <= serve_en_i;
end gideon;
| gpl-3.0 | f8efc86d50cdfc7bca91c1fa2bdfe590 | 0.453417 | 3.655777 | false | false | false | false |
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