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markusC64/1541ultimate2 | fpga/io/sigma_delta_dac/vhdl_source/sigma_delta_dac.vhd | 1 | 2,496 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.my_math_pkg.all;
entity sigma_delta_dac is
generic (
g_divider : natural := 1;
g_width : positive := 12;
g_invert : boolean := false;
g_use_mid_only : boolean := true;
g_left_shift : natural := 1 );
port (
clock : in std_logic;
reset : in std_logic;
dac_in : in signed(g_width-1 downto 0);
dac_out : out std_logic );
end sigma_delta_dac;
architecture gideon of sigma_delta_dac is
signal dac_in_scaled : signed(g_width-1 downto g_left_shift);
signal converted : unsigned(g_width downto g_left_shift);
signal out_i : std_logic;
signal accu : unsigned(converted'range);
signal divider : integer range 0 to g_divider-1;
begin
dac_in_scaled <= left_scale(dac_in, g_left_shift);
converted <= (not dac_in_scaled(dac_in_scaled'high) & unsigned(dac_in_scaled(dac_in_scaled'high downto g_left_shift))) when g_use_mid_only else
(not dac_in_scaled(dac_in_scaled'high) & unsigned(dac_in_scaled(dac_in_scaled'high-1 downto g_left_shift))) & '0';
process(clock)
procedure sum_with_carry(a, b : unsigned; y : out unsigned; c : out std_logic ) is
variable a_ext : unsigned(a'length downto 0);
variable b_ext : unsigned(a'length downto 0);
variable summed : unsigned(a'length downto 0);
begin
a_ext := '0' & a;
b_ext := '0' & b;
summed := a_ext + b_ext;
c := summed(summed'left);
y := summed(a'length-1 downto 0);
end procedure;
variable a_new : unsigned(accu'range);
variable carry : std_logic;
begin
if rising_edge(clock) then
if divider = g_divider - 1 then
divider <= 0;
sum_with_carry(accu, converted, a_new, carry);
accu <= a_new;
if g_invert then
out_i <= not carry;
else
out_i <= carry;
end if;
else
divider <= divider + 1;
end if;
if reset='1' then
out_i <= not out_i;
accu <= (others => '0');
end if;
end if;
end process;
dac_out <= out_i;
end gideon;
| gpl-3.0 | 625573dbcfa0aaed61f4e6e28781a37b | 0.512821 | 3.622642 | false | false | false | false |
ntb-ch/cb20 | FPGA_Designs/watchdog/cb20/synthesis/cb20_width_adapter_001.vhd | 1 | 10,454 | -- cb20_width_adapter_001.vhd
-- Generated using ACDS version 13.0sp1 232 at 2020.06.03.16:36:13
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity cb20_width_adapter_001 is
generic (
IN_PKT_ADDR_H : integer := 52;
IN_PKT_ADDR_L : integer := 36;
IN_PKT_DATA_H : integer := 31;
IN_PKT_DATA_L : integer := 0;
IN_PKT_BYTEEN_H : integer := 35;
IN_PKT_BYTEEN_L : integer := 32;
IN_PKT_BYTE_CNT_H : integer := 61;
IN_PKT_BYTE_CNT_L : integer := 59;
IN_PKT_TRANS_COMPRESSED_READ : integer := 53;
IN_PKT_BURSTWRAP_H : integer := 62;
IN_PKT_BURSTWRAP_L : integer := 62;
IN_PKT_BURST_SIZE_H : integer := 65;
IN_PKT_BURST_SIZE_L : integer := 63;
IN_PKT_RESPONSE_STATUS_H : integer := 87;
IN_PKT_RESPONSE_STATUS_L : integer := 86;
IN_PKT_TRANS_EXCLUSIVE : integer := 58;
IN_PKT_BURST_TYPE_H : integer := 67;
IN_PKT_BURST_TYPE_L : integer := 66;
IN_ST_DATA_W : integer := 88;
OUT_PKT_ADDR_H : integer := 34;
OUT_PKT_ADDR_L : integer := 18;
OUT_PKT_DATA_H : integer := 15;
OUT_PKT_DATA_L : integer := 0;
OUT_PKT_BYTEEN_H : integer := 17;
OUT_PKT_BYTEEN_L : integer := 16;
OUT_PKT_BYTE_CNT_H : integer := 43;
OUT_PKT_BYTE_CNT_L : integer := 41;
OUT_PKT_TRANS_COMPRESSED_READ : integer := 35;
OUT_PKT_BURST_SIZE_H : integer := 47;
OUT_PKT_BURST_SIZE_L : integer := 45;
OUT_PKT_RESPONSE_STATUS_H : integer := 69;
OUT_PKT_RESPONSE_STATUS_L : integer := 68;
OUT_PKT_TRANS_EXCLUSIVE : integer := 40;
OUT_PKT_BURST_TYPE_H : integer := 49;
OUT_PKT_BURST_TYPE_L : integer := 48;
OUT_ST_DATA_W : integer := 70;
ST_CHANNEL_W : integer := 8;
OPTIMIZE_FOR_RSP : integer := 1;
RESPONSE_PATH : integer := 1
);
port (
clk : in std_logic := '0'; -- clk.clk
reset : in std_logic := '0'; -- clk_reset.reset
in_valid : in std_logic := '0'; -- sink.valid
in_channel : in std_logic_vector(7 downto 0) := (others => '0'); -- .channel
in_startofpacket : in std_logic := '0'; -- .startofpacket
in_endofpacket : in std_logic := '0'; -- .endofpacket
in_ready : out std_logic; -- .ready
in_data : in std_logic_vector(87 downto 0) := (others => '0'); -- .data
out_endofpacket : out std_logic; -- src.endofpacket
out_data : out std_logic_vector(69 downto 0); -- .data
out_channel : out std_logic_vector(7 downto 0); -- .channel
out_valid : out std_logic; -- .valid
out_ready : in std_logic := '0'; -- .ready
out_startofpacket : out std_logic; -- .startofpacket
in_command_size_data : in std_logic_vector(2 downto 0) := (others => '0')
);
end entity cb20_width_adapter_001;
architecture rtl of cb20_width_adapter_001 is
component altera_merlin_width_adapter is
generic (
IN_PKT_ADDR_H : integer := 60;
IN_PKT_ADDR_L : integer := 36;
IN_PKT_DATA_H : integer := 31;
IN_PKT_DATA_L : integer := 0;
IN_PKT_BYTEEN_H : integer := 35;
IN_PKT_BYTEEN_L : integer := 32;
IN_PKT_BYTE_CNT_H : integer := 63;
IN_PKT_BYTE_CNT_L : integer := 61;
IN_PKT_TRANS_COMPRESSED_READ : integer := 65;
IN_PKT_BURSTWRAP_H : integer := 67;
IN_PKT_BURSTWRAP_L : integer := 66;
IN_PKT_BURST_SIZE_H : integer := 70;
IN_PKT_BURST_SIZE_L : integer := 68;
IN_PKT_RESPONSE_STATUS_H : integer := 72;
IN_PKT_RESPONSE_STATUS_L : integer := 71;
IN_PKT_TRANS_EXCLUSIVE : integer := 73;
IN_PKT_BURST_TYPE_H : integer := 75;
IN_PKT_BURST_TYPE_L : integer := 74;
IN_ST_DATA_W : integer := 76;
OUT_PKT_ADDR_H : integer := 60;
OUT_PKT_ADDR_L : integer := 36;
OUT_PKT_DATA_H : integer := 31;
OUT_PKT_DATA_L : integer := 0;
OUT_PKT_BYTEEN_H : integer := 35;
OUT_PKT_BYTEEN_L : integer := 32;
OUT_PKT_BYTE_CNT_H : integer := 63;
OUT_PKT_BYTE_CNT_L : integer := 61;
OUT_PKT_TRANS_COMPRESSED_READ : integer := 65;
OUT_PKT_BURST_SIZE_H : integer := 68;
OUT_PKT_BURST_SIZE_L : integer := 66;
OUT_PKT_RESPONSE_STATUS_H : integer := 70;
OUT_PKT_RESPONSE_STATUS_L : integer := 69;
OUT_PKT_TRANS_EXCLUSIVE : integer := 71;
OUT_PKT_BURST_TYPE_H : integer := 73;
OUT_PKT_BURST_TYPE_L : integer := 72;
OUT_ST_DATA_W : integer := 74;
ST_CHANNEL_W : integer := 32;
OPTIMIZE_FOR_RSP : integer := 0;
RESPONSE_PATH : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
in_valid : in std_logic := 'X'; -- valid
in_channel : in std_logic_vector(7 downto 0) := (others => 'X'); -- channel
in_startofpacket : in std_logic := 'X'; -- startofpacket
in_endofpacket : in std_logic := 'X'; -- endofpacket
in_ready : out std_logic; -- ready
in_data : in std_logic_vector(87 downto 0) := (others => 'X'); -- data
out_endofpacket : out std_logic; -- endofpacket
out_data : out std_logic_vector(69 downto 0); -- data
out_channel : out std_logic_vector(7 downto 0); -- channel
out_valid : out std_logic; -- valid
out_ready : in std_logic := 'X'; -- ready
out_startofpacket : out std_logic; -- startofpacket
in_command_size_data : in std_logic_vector(2 downto 0) := (others => 'X') -- data
);
end component altera_merlin_width_adapter;
begin
width_adapter_001 : component altera_merlin_width_adapter
generic map (
IN_PKT_ADDR_H => IN_PKT_ADDR_H,
IN_PKT_ADDR_L => IN_PKT_ADDR_L,
IN_PKT_DATA_H => IN_PKT_DATA_H,
IN_PKT_DATA_L => IN_PKT_DATA_L,
IN_PKT_BYTEEN_H => IN_PKT_BYTEEN_H,
IN_PKT_BYTEEN_L => IN_PKT_BYTEEN_L,
IN_PKT_BYTE_CNT_H => IN_PKT_BYTE_CNT_H,
IN_PKT_BYTE_CNT_L => IN_PKT_BYTE_CNT_L,
IN_PKT_TRANS_COMPRESSED_READ => IN_PKT_TRANS_COMPRESSED_READ,
IN_PKT_BURSTWRAP_H => IN_PKT_BURSTWRAP_H,
IN_PKT_BURSTWRAP_L => IN_PKT_BURSTWRAP_L,
IN_PKT_BURST_SIZE_H => IN_PKT_BURST_SIZE_H,
IN_PKT_BURST_SIZE_L => IN_PKT_BURST_SIZE_L,
IN_PKT_RESPONSE_STATUS_H => IN_PKT_RESPONSE_STATUS_H,
IN_PKT_RESPONSE_STATUS_L => IN_PKT_RESPONSE_STATUS_L,
IN_PKT_TRANS_EXCLUSIVE => IN_PKT_TRANS_EXCLUSIVE,
IN_PKT_BURST_TYPE_H => IN_PKT_BURST_TYPE_H,
IN_PKT_BURST_TYPE_L => IN_PKT_BURST_TYPE_L,
IN_ST_DATA_W => IN_ST_DATA_W,
OUT_PKT_ADDR_H => OUT_PKT_ADDR_H,
OUT_PKT_ADDR_L => OUT_PKT_ADDR_L,
OUT_PKT_DATA_H => OUT_PKT_DATA_H,
OUT_PKT_DATA_L => OUT_PKT_DATA_L,
OUT_PKT_BYTEEN_H => OUT_PKT_BYTEEN_H,
OUT_PKT_BYTEEN_L => OUT_PKT_BYTEEN_L,
OUT_PKT_BYTE_CNT_H => OUT_PKT_BYTE_CNT_H,
OUT_PKT_BYTE_CNT_L => OUT_PKT_BYTE_CNT_L,
OUT_PKT_TRANS_COMPRESSED_READ => OUT_PKT_TRANS_COMPRESSED_READ,
OUT_PKT_BURST_SIZE_H => OUT_PKT_BURST_SIZE_H,
OUT_PKT_BURST_SIZE_L => OUT_PKT_BURST_SIZE_L,
OUT_PKT_RESPONSE_STATUS_H => OUT_PKT_RESPONSE_STATUS_H,
OUT_PKT_RESPONSE_STATUS_L => OUT_PKT_RESPONSE_STATUS_L,
OUT_PKT_TRANS_EXCLUSIVE => OUT_PKT_TRANS_EXCLUSIVE,
OUT_PKT_BURST_TYPE_H => OUT_PKT_BURST_TYPE_H,
OUT_PKT_BURST_TYPE_L => OUT_PKT_BURST_TYPE_L,
OUT_ST_DATA_W => OUT_ST_DATA_W,
ST_CHANNEL_W => ST_CHANNEL_W,
OPTIMIZE_FOR_RSP => OPTIMIZE_FOR_RSP,
RESPONSE_PATH => RESPONSE_PATH
)
port map (
clk => clk, -- clk.clk
reset => reset, -- clk_reset.reset
in_valid => in_valid, -- sink.valid
in_channel => in_channel, -- .channel
in_startofpacket => in_startofpacket, -- .startofpacket
in_endofpacket => in_endofpacket, -- .endofpacket
in_ready => in_ready, -- .ready
in_data => in_data, -- .data
out_endofpacket => out_endofpacket, -- src.endofpacket
out_data => out_data, -- .data
out_channel => out_channel, -- .channel
out_valid => out_valid, -- .valid
out_ready => out_ready, -- .ready
out_startofpacket => out_startofpacket, -- .startofpacket
in_command_size_data => "000" -- (terminated)
);
end architecture rtl; -- of cb20_width_adapter_001
| apache-2.0 | 0379b2c0ed55a8fcb98495d6314422a1 | 0.45925 | 3.366828 | false | false | false | false |
markusC64/1541ultimate2 | fpga/fpga_top/ultimate_fpga/vhdl_sim/harness_logic_32.vhd | 1 | 16,998 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
use work.cart_slot_pkg.all;
use work.io_bus_pkg.all;
use work.io_bus_bfm_pkg.all;
use work.command_if_pkg.all;
library std;
use std.textio.all;
entity harness_logic_32 is
end entity;
architecture tb of harness_logic_32 is
constant c_uart_divisor : natural := 10;
signal PHI2 : std_logic := '0';
signal RSTn : std_logic := 'H';
signal DOTCLK : std_logic := '1';
signal BUFFER_ENn : std_logic := '1';
signal BA : std_logic := '0';
signal DMAn : std_logic := '1';
signal EXROMn : std_logic;
signal GAMEn : std_logic;
signal ROMHn : std_logic := '1';
signal ROMLn : std_logic := '1';
signal IO1n : std_logic := '1';
signal IO2n : std_logic := '1';
signal IRQn : std_logic := '1';
signal NMIn : std_logic := '1';
signal slot_addr_o : std_logic_vector(15 downto 0);
signal slot_addr_i : std_logic_vector(15 downto 0) := (others => '1');
signal slot_addr_tl: std_logic;
signal slot_addr_th: std_logic;
signal slot_data_o : std_logic_vector(7 downto 0);
signal slot_data_i : std_logic_vector(7 downto 0) := (others => '1');
signal slot_data_t : std_logic;
-- Cassette
signal c2n_read_in : std_logic;
signal c2n_write_in : std_logic;
signal c2n_read_out : std_logic;
signal c2n_write_out : std_logic;
signal c2n_read_en : std_logic;
signal c2n_write_en : std_logic;
signal c2n_sense_in : std_logic;
signal c2n_sense_out : std_logic;
signal c2n_motor_in : std_logic;
signal c2n_motor_out : std_logic;
-- Parallel cable connection
signal drv_via1_port_a_o : std_logic_vector(7 downto 0);
signal drv_via1_port_a_i : std_logic_vector(7 downto 0);
signal drv_via1_port_a_t : std_logic_vector(7 downto 0);
signal drv_via1_ca2_o : std_logic;
signal drv_via1_ca2_i : std_logic;
signal drv_via1_ca2_t : std_logic;
signal drv_via1_cb1_o : std_logic;
signal drv_via1_cb1_i : std_logic;
signal drv_via1_cb1_t : std_logic;
signal IEC_ATN : std_logic := '1';
signal IEC_DATA : std_logic := '1';
signal IEC_CLOCK : std_logic := '1';
signal IEC_RESET : std_logic := '1';
signal IEC_SRQ_IN : std_logic := '1';
signal iec_atn_o : std_logic := '1';
signal iec_data_o : std_logic := '1';
signal iec_clock_o : std_logic := '1';
signal iec_reset_o : std_logic := '1';
signal iec_srq_o : std_logic := '1';
signal DISK_ACTn : std_logic; -- activity LED
signal CART_LEDn : std_logic;
signal SDACT_LEDn : std_logic;
signal MOTOR_LEDn : std_logic;
signal UART_TXD : std_logic;
signal UART_RXD : std_logic := '1';
signal SD_SSn : std_logic;
signal SD_CLK : std_logic;
signal SD_MOSI : std_logic;
signal SD_MISO : std_logic := '1';
signal SD_WP : std_logic := '1';
signal SD_CARDDETn : std_logic := '1';
signal SD_DATA : std_logic_vector(2 downto 1) := "HH";
signal BUTTON : std_logic_vector(2 downto 0) := "000";
signal SLOT_ADDR : std_logic_vector(15 downto 0);
signal SLOT_DATA : std_logic_vector(7 downto 0);
signal RWn : std_logic := '1';
signal CAS_MOTOR : std_logic := '1';
signal CAS_SENSE : std_logic := '0';
signal CAS_READ : std_logic := '0';
signal CAS_WRITE : std_logic := '0';
signal RTC_CS : std_logic;
signal RTC_SCK : std_logic;
signal RTC_MOSI : std_logic;
signal RTC_MISO : std_logic := '1';
signal FLASH_CSn : std_logic;
signal FLASH_SCK : std_logic;
signal FLASH_MOSI : std_logic;
signal FLASH_MISO : std_logic := '1';
signal ULPI_CLOCK : std_logic := '0';
signal ULPI_RESET : std_logic := '0';
signal ULPI_NXT : std_logic := '0';
signal ULPI_STP : std_logic;
signal ULPI_DIR : std_logic := '0';
signal ULPI_DATA : std_logic_vector(7 downto 0) := (others => 'H');
signal sys_clock : std_logic := '1';
signal sys_reset : std_logic := '1';
signal sys_clock_2x : std_logic := '1';
signal rx_char : std_logic_vector(7 downto 0);
signal rx_char_d : std_logic_vector(7 downto 0);
signal rx_ack : std_logic;
signal tx_char : std_logic_vector(7 downto 0) := X"00";
signal tx_done : std_logic;
signal do_tx : std_logic := '0';
-- memory controller interconnect
signal mem_inhibit : std_logic := '0';
signal mem_req : t_mem_req_32;
signal mem_resp : t_mem_resp_32;
signal io_req : t_io_req;
signal io_resp : t_io_resp;
signal CLOCK_50 : std_logic := '0';
signal SDRAM_CLK : std_logic;
signal SDRAM_CKE : std_logic;
signal SDRAM_CSn : std_logic := '1';
signal SDRAM_RASn : std_logic := '1';
signal SDRAM_CASn : std_logic := '1';
signal SDRAM_WEn : std_logic := '1';
signal SDRAM_DQM : std_logic := '0';
signal SDRAM_A : std_logic_vector(12 downto 0);
signal SDRAM_BA : std_logic_vector(1 downto 0);
signal SDRAM_DQ : std_logic_vector(7 downto 0) := (others => 'Z');
begin
sys_clock <= not sys_clock after 10 ns;
sys_clock_2x <= not sys_clock_2x after 5 ns;
sys_reset <= '1', '0' after 100 ns;
mut: entity work.ultimate_logic_32
generic map (
g_version => X"02",
g_simulation => true,
g_clock_freq => 50_000_000,
g_baud_rate => 1_000_000,
g_timer_rate => 200_000,
g_boot_rom => false,
g_video_overlay => false,
g_icap => false,
g_uart => true,
g_drive_1541 => true,
g_drive_1541_2 => false,
g_hardware_gcr => true,
g_cartridge => true,
g_command_intf => true,
g_stereo_sid => false,
g_ram_expansion => true,
g_extended_reu => false,
g_hardware_iec => false,
g_c2n_streamer => false,
g_c2n_recorder => false,
g_drive_sound => true,
g_rtc_chip => false,
g_rtc_timer => false,
g_usb_host => false,
g_usb_host2 => true,
g_spi_flash => true,
g_vic_copper => false,
g_sampler => false,
g_profiler => true,
g_analyzer => false )
port map (
sys_clock => sys_clock,
sys_reset => sys_reset,
ulpi_clock => ulpi_clock,
ulpi_reset => ulpi_reset,
phi2_i => PHI2,
dotclk_i => DOTCLK,
rstn_o => RSTn,
rstn_i => RSTn,
slot_addr_o => slot_addr_o,
slot_addr_i => SLOT_ADDR,
slot_addr_tl => slot_addr_tl,
slot_addr_th => slot_addr_th,
slot_data_o => slot_data_o,
slot_data_i => SLOT_DATA,
slot_data_t => slot_data_t,
rwn_i => RWn,
rwn_o => RWn,
exromn_i => EXROMn,
exromn_o => EXROMn,
gamen_i => GAMEn,
gamen_o => GAMEn,
irqn_i => IRQn,
irqn_o => IRQn,
nmin_i => NMIn,
nmin_o => NMIn,
ba_i => BA,
dman_o => DMAn,
romhn_i => ROMHn,
romln_i => ROMLn,
io1n_i => IO1n,
io2n_i => IO2n,
-- Parallel cable pins
drv_via1_port_a_o => drv_via1_port_a_o,
drv_via1_port_a_i => drv_via1_port_a_i,
drv_via1_port_a_t => drv_via1_port_a_t,
drv_via1_ca2_o => drv_via1_ca2_o,
drv_via1_ca2_i => drv_via1_ca2_i,
drv_via1_ca2_t => drv_via1_ca2_t,
drv_via1_cb1_o => drv_via1_cb1_o,
drv_via1_cb1_i => drv_via1_cb1_i,
drv_via1_cb1_t => drv_via1_cb1_t,
-- Cassette Interface
c2n_read_in => c2n_read_in,
c2n_write_in => c2n_write_in,
c2n_read_out => c2n_read_out,
c2n_write_out => c2n_write_out,
c2n_read_en => c2n_read_en,
c2n_write_en => c2n_write_en,
c2n_sense_in => c2n_sense_in,
c2n_sense_out => c2n_sense_out,
c2n_motor_in => c2n_motor_in,
c2n_motor_out => c2n_motor_out,
mem_inhibit => mem_inhibit,
mem_req => mem_req,
mem_resp => mem_resp,
iec_reset_i => IEC_RESET,
iec_atn_i => IEC_ATN,
iec_data_i => IEC_DATA,
iec_clock_i => IEC_CLOCK,
iec_srq_i => IEC_SRQ_IN,
iec_reset_o => iec_reset_o,
iec_atn_o => iec_atn_o,
iec_data_o => iec_data_o,
iec_clock_o => iec_clock_o,
iec_srq_o => iec_srq_o,
BUTTON => BUTTON,
DISK_ACTn => DISK_ACTn,
CART_LEDn => CART_LEDn,
SDACT_LEDn => SDACT_LEDn,
MOTOR_LEDn => MOTOR_LEDn,
UART_TXD => UART_TXD,
UART_RXD => UART_RXD,
SD_SSn => SD_SSn,
SD_CLK => SD_CLK,
SD_MOSI => SD_MOSI,
SD_MISO => SD_MISO,
SD_CARDDETn => SD_CARDDETn,
SD_DATA => SD_DATA,
RTC_CS => RTC_CS,
RTC_SCK => RTC_SCK,
RTC_MOSI => RTC_MOSI,
RTC_MISO => RTC_MISO,
FLASH_CSn => FLASH_CSn,
FLASH_SCK => FLASH_SCK,
FLASH_MOSI => FLASH_MOSI,
FLASH_MISO => FLASH_MISO,
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP,
ULPI_DIR => ULPI_DIR,
ULPI_DATA => ULPI_DATA,
ext_io_req => io_req,
ext_io_resp => io_resp );
SLOT_ADDR(15 downto 12) <= slot_addr_o(15 downto 12) when slot_addr_th = '1' else (others => 'H');
SLOT_ADDR(11 downto 00) <= slot_addr_o(11 downto 00) when slot_addr_tl = '1' else (others => 'H');
SLOT_DATA <= slot_data_o when slot_data_t = '1' else (others => 'H');
-- Parallel cable not implemented. This is the way to stub it...
drv_via1_port_a_i <= drv_via1_port_a_o or not drv_via1_port_a_t;
drv_via1_ca2_i <= drv_via1_ca2_o or not drv_via1_ca2_t;
drv_via1_cb1_i <= drv_via1_cb1_o or not drv_via1_cb1_t;
i_mem_ctrl: entity work.ext_mem_ctrl_v5
generic map (
g_simulation => false )
port map (
clock => sys_clock,
clk_2x => sys_clock_2x,
reset => sys_reset,
inhibit => mem_inhibit,
is_idle => open,
req => mem_req,
resp => mem_resp,
SDRAM_CLK => SDRAM_CLK,
SDRAM_CKE => SDRAM_CKE,
SDRAM_CSn => SDRAM_CSn,
SDRAM_RASn => SDRAM_RASn,
SDRAM_CASn => SDRAM_CASn,
SDRAM_WEn => SDRAM_WEn,
SDRAM_DQM => SDRAM_DQM,
SDRAM_BA => SDRAM_BA,
SDRAM_A => SDRAM_A,
SDRAM_DQ => SDRAM_DQ );
ULPI_CLOCK <= not ULPI_CLOCK after 8.333 ns; -- 60 MHz
ULPI_RESET <= '1', '0' after 100 ns;
PHI2 <= not PHI2 after 507.5 ns; -- 0.98525 MHz
RSTn <= '0', 'H' after 6 us, '0' after 100 us, 'H' after 105 us;
i_io_bfm: entity work.io_bus_bfm
generic map (
g_name => "io_bfm" )
port map (
clock => sys_clock,
req => io_req,
resp => io_resp );
SLOT_DATA <= (others => 'H');
ROMHn <= '1';
ROMLn <= not PHI2 after 50 ns;
IO1n <= '1';
IO2n <= '1';
process
begin
SLOT_ADDR <= X"7F00";
RWn <= '1';
while true loop
wait until PHI2 = '0';
--SLOT_ADDR(8 downto 0) <= std_logic_vector(unsigned(SLOT_ADDR(8 downto 0)) + 1);
SLOT_ADDR <= std_logic_vector(unsigned(SLOT_ADDR) + 1);
RWn <= '1';
wait until PHI2 = '0';
RWn <= '0';
end loop;
end process;
process
begin
BA <= '1';
for i in 0 to 100 loop
wait until PHI2='0';
end loop;
BA <= '0';
for i in 0 to 10 loop
wait until PHI2='0';
end loop;
end process;
ram: entity work.dram_8
generic map(
g_cas_latency => 3,
g_burst_len_r => 4,
g_burst_len_w => 4,
g_column_bits => 10,
g_row_bits => 13,
g_bank_bits => 2
)
port map(
CLK => SDRAM_CLK,
CKE => SDRAM_CKE,
A => SDRAM_A,
BA => SDRAM_BA,
CSn => SDRAM_CSn,
RASn => SDRAM_RASn,
CASn => SDRAM_CASn,
WEn => SDRAM_WEn,
DQM => SDRAM_DQM,
DQ => SDRAM_DQ
);
-- i_ulpi_phy: entity work.ulpi_master_bfm
-- generic map (
-- g_given_name => "device" )
--
-- port map (
-- clock => ULPI_CLOCK,
-- reset => ULPI_RESET,
-- ulpi_nxt => ulpi_nxt,
-- ulpi_stp => ulpi_stp,
-- ulpi_dir => ulpi_dir,
-- ulpi_data => ulpi_data );
--
-- i_device: entity work.usb_device_model;
i_rx: entity work.rx
generic map (c_uart_divisor)
port map (
clk => sys_clock,
reset => sys_reset,
tick => '1',
rxd => UART_TXD,
rxchar => rx_char,
rx_ack => rx_ack );
i_tx: entity work.tx
generic map (c_uart_divisor)
port map (
clk => sys_clock,
reset => sys_reset,
tick => '1',
dotx => do_tx,
txchar => tx_char,
done => tx_done,
txd => UART_RXD );
process(sys_clock)
variable s : line;
variable char : character;
begin
if rising_edge(sys_clock) then
if rx_ack='1' then
rx_char_d <= rx_char;
char := character'val(to_integer(unsigned(rx_char)));
if rx_char = X"0D" then
-- Ignore character 13
elsif rx_char = X"0A" then
-- Writeline on character 10 (newline)
writeline(output, s);
else
-- Write to buffer
write(s, char);
end if;
end if;
if mem_resp.rack = '1' and mem_req.address < 16 then
report "Access to address " & integer'image(to_integer(mem_req.address)) severity error;
end if;
end if;
end process;
process
variable io : p_io_bus_bfm_object;
begin
wait until sys_reset='0';
wait until sys_clock='1';
bind_io_bus_bfm("io_bfm", io);
io_write(io, X"40000" + c_cart_c64_mode, X"04"); -- reset
io_write(io, X"40000" + c_cart_cartridge_type, X"06"); -- retro
io_write(io, X"40000" + c_cart_c64_mode, X"08"); -- unreset
io_write(io, X"44000" + c_cif_io_slot_base, X"7E");
io_write(io, X"44000" + c_cif_io_slot_enable, X"01");
wait for 6 us;
wait until sys_clock='1';
--io_write(io, X"42002", X"42");
wait;
end process;
process
procedure send_char(i: std_logic_vector(7 downto 0)) is
begin
if tx_done /= '1' then
wait until tx_done = '1';
end if;
wait until sys_clock='1';
tx_char <= i;
do_tx <= '1';
wait until tx_done = '0';
wait until sys_clock='1';
do_tx <= '0';
end procedure;
procedure send_string(i : string) is
variable b : std_logic_vector(7 downto 0);
begin
for n in i'range loop
b := std_logic_vector(to_unsigned(character'pos(i(n)), 8));
send_char(b);
end loop;
send_char(X"0d");
send_char(X"0a");
end procedure;
begin
wait for 2 ms;
--send_string("wd 4005000 12345678");
send_string("run");
-- send_string("m 100000");
-- send_string("w 400000F 4");
wait;
end process;
-- check timing data
process(PHI2)
begin
if falling_edge(PHI2) then
assert SLOT_DATA'last_event >= 189 ns
report "Timing error on C64 bus."
severity error;
end if;
end process;
end tb;
| gpl-3.0 | b0fa8f304d69e6619477f351d12c139d | 0.481115 | 3.187922 | false | false | false | false |
markusC64/1541ultimate2 | fpga/ip/busses/vhdl_bfm/mem_bus_32_slave_bfm.vhd | 1 | 2,853 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
use work.tl_flat_memory_model_pkg.all;
entity mem_bus_32_slave_bfm is
generic (
g_name : string;
g_latency : positive := 2 );
port (
clock : in std_logic;
req : in t_mem_req_32;
resp : out t_mem_resp_32 );
end mem_bus_32_slave_bfm;
architecture bfm of mem_bus_32_slave_bfm is
shared variable mem : h_mem_object;
signal bound : boolean := false;
signal pipe : t_mem_req_32_array(0 to g_latency-1) := (others => c_mem_req_32_init);
begin
-- this process registers this instance of the bfm to the server package
bind: process
begin
register_mem_model(mem_bus_32_slave_bfm'path_name, g_name, mem);
bound <= true;
wait;
end process;
resp.rack <= '1' when bound and req.request='1' else '0';
resp.rack_tag <= req.tag when bound and req.request='1' else (others => '0');
process(clock)
variable data : std_logic_vector(31 downto 0);
variable word_addr : unsigned(31 downto 2);
variable byte_addr : unsigned(1 downto 0);
begin
if rising_edge(clock) then
pipe(0 to g_latency-2) <= pipe(1 to g_latency-1);
pipe(g_latency-1) <= req;
resp.dack_tag <= (others => '0');
resp.data <= (others => '0');
if bound then
if pipe(0).request='1' then
if pipe(0).read_writen='1' then
resp.dack_tag <= pipe(0).tag;
data := read_memory_32(mem, "000000" & std_logic_vector(pipe(0).address));
if pipe(0).address(1 downto 0) = "00" then
resp.data <= data;
elsif pipe(0).address(1 downto 0) = "01" then
resp.data <= data(7 downto 0) & data(31 downto 8);
elsif pipe(0).address(1 downto 0) = "10" then
resp.data <= data(15 downto 0) & data(31 downto 16);
else
resp.data <= data(23 downto 0) & data(31 downto 24);
end if;
else
word_addr := "000000" & pipe(0).address(25 downto 2);
byte_addr := pipe(0).address(1 downto 0);
for i in 0 to 3 loop
if pipe(0).byte_en(i) = '1' then
write_memory_8(mem, std_logic_vector(word_addr) & std_logic_vector(byte_addr), pipe(0).data(7+8*i downto 8*i));
end if;
byte_addr := byte_addr + 1;
end loop;
end if;
end if;
end if;
end if;
end process;
end bfm;
| gpl-3.0 | 41544b082b3516c48c03fe198706d738 | 0.497021 | 3.526576 | false | false | false | false |
markusC64/1541ultimate2 | target/simulation/vhdl_bfm/mb_model.vhd | 2 | 32,264 | -------------------------------------------------------------------------------
-- Title : mb_model
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: Instruction level model of the microblaze
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.tl_string_util_pkg.all;
library std;
use std.textio.all;
entity mb_model is
generic (
g_io_mask : unsigned(31 downto 0) := X"FC000000" );
port (
clock : in std_logic;
reset : in std_logic;
io_addr : out unsigned(31 downto 0);
io_write : out std_logic;
io_read : out std_logic;
io_byte_en : out std_logic_vector(3 downto 0);
io_wdata : out std_logic_vector(31 downto 0);
io_rdata : in std_logic_vector(31 downto 0);
io_ack : in std_logic );
end entity;
architecture bfm of mb_model is
type t_word_array is array(natural range <>) of std_logic_vector(31 downto 0);
type t_signed_array is array(natural range <>) of signed(31 downto 0);
constant c_memory_size_bytes : natural := 20; -- 1 MB
constant c_memory_size_words : natural := c_memory_size_bytes - 2;
shared variable reg : t_signed_array(0 to 31) := (others => (others => '0'));
shared variable imem : t_word_array(0 to 2**c_memory_size_words -1);
alias dmem : t_word_array(0 to 2**c_memory_size_words -1) is imem;
signal pc_reg : unsigned(31 downto 0);
signal C_flag : std_logic;
signal I_flag : std_logic;
signal B_flag : std_logic;
signal D_flag : std_logic;
constant p : string := "PC: ";
constant i : string := ", Inst: ";
constant c : string := ", ";
constant ras : string := ", Ra=";
constant rbs : string := ", Rb=";
constant rds : string := ", Rd=";
impure function get_msr(len : natural) return std_logic_vector is
variable msr : std_logic_vector(31 downto 0);
begin
msr := (31 => C_flag,
3 => B_flag,
2 => C_flag,
1 => I_flag,
others => '0' );
return msr(len-1 downto 0);
end function;
function to_std(b : boolean) return std_logic is
begin
if b then return '1'; end if;
return '0';
end function;
begin
process
variable new_pc : unsigned(31 downto 0);
variable do_delay : std_logic := '0';
variable imm : signed(31 downto 0);
variable imm_lock : std_logic := '0';
variable ra : integer range 0 to 31;
variable rb : integer range 0 to 31;
variable rd : integer range 0 to 31;
procedure dbPrint(pc : unsigned(31 downto 0); inst : std_logic_vector(31 downto 0); str : string) is
variable s : line;
begin
write(s, p);
write(s, hstr(pc));
write(s, i);
write(s, hstr(inst));
write(s, ras);
write(s, hstr(unsigned(reg(ra))));
write(s, rbs);
write(s, hstr(unsigned(reg(rb))));
write(s, rds);
write(s, hstr(unsigned(reg(rd))));
write(s, c);
write(s, str);
-- writeline(output, s);
end procedure;
procedure set_msr(a : std_logic_vector(13 downto 0)) is
begin
B_flag <= a(3);
C_flag <= a(2);
I_flag <= a(1);
end procedure;
procedure perform_add(a, b : signed(31 downto 0); carry : std_logic; upd_c : boolean) is
variable t33: signed(32 downto 0);
begin
if carry = '1' then
t33 := ('0' & a) + ('0' & b) + 1;
else
t33 := ('0' & a) + ('0' & b);
end if;
reg(rd) := t33(31 downto 0);
if upd_c then
C_flag <= t33(32);
end if;
end procedure;
procedure illegal(pc : unsigned) is
begin
report "Illegal instruction @ " & hstr(pc)
severity error;
end procedure;
procedure unimplemented(msg : string) is
begin
report msg;
end procedure;
procedure do_branch(pc : unsigned(31 downto 0); offset : signed(31 downto 0); delay, absolute, link : std_logic; chk : integer) is
variable take : boolean;
begin
case chk is
when 0 => take := (reg(ra) = 0);
when 1 => take := (reg(ra) /= 0);
when 2 => take := (reg(ra) < 0);
when 3 => take := (reg(ra) <= 0);
when 4 => take := (reg(ra) > 0);
when 5 => take := (reg(ra) >= 0);
when others => take := true;
end case;
if link='1' then
reg(rd) := signed(pc);
end if;
if take then
if absolute='1' then
new_pc := unsigned(offset);
else
new_pc := unsigned(signed(pc) + offset);
end if;
end if; -- else: default: new_pc := pc + 4;
if take then
do_delay := delay;
end if;
end procedure;
function is_io(addr : unsigned(31 downto 0)) return boolean is
begin
return (addr and g_io_mask) /= 0;
end function;
procedure load_byte(addr : unsigned(31 downto 0); data : out std_logic_vector(31 downto 0)) is
variable loaded : std_logic_vector(31 downto 0);
begin
if is_io(addr) then
io_read <= '1';
io_addr <= unsigned(addr);
case addr(1 downto 0) is
when "00" => io_byte_en <= "1000";
when "01" => io_byte_en <= "0100";
when "10" => io_byte_en <= "0010";
when "11" => io_byte_en <= "0001";
when others => io_byte_en <= "0000";
end case;
wait until clock='1';
io_read <= '0';
while io_ack = '0' loop
wait until clock='1';
end loop;
loaded := io_rdata;
else
loaded := dmem(to_integer(addr(c_memory_size_bytes-1 downto 2)));
end if;
data := (others => '0');
case addr(1 downto 0) is
when "00" => data(7 downto 0) := loaded(31 downto 24);
when "01" => data(7 downto 0) := loaded(23 downto 16);
when "10" => data(7 downto 0) := loaded(15 downto 8);
when "11" => data(7 downto 0) := loaded(7 downto 0);
when others => data := (others => 'X');
end case;
end procedure;
procedure load_half(addr : unsigned(31 downto 0); data : out std_logic_vector(31 downto 0)) is
variable loaded : std_logic_vector(31 downto 0);
begin
if is_io(addr) then
io_read <= '1';
io_addr <= unsigned(addr);
io_byte_en <= (others => '0');
case addr(1 downto 0) is
when "00" => io_byte_en <= "1100";
when "10" => io_byte_en <= "0011";
when others => null;
end case;
wait until clock='1';
io_read <= '0';
while io_ack = '0' loop
wait until clock='1';
end loop;
loaded := io_rdata;
else
loaded := dmem(to_integer(addr(c_memory_size_bytes-1 downto 2)));
end if;
data := (others => '0');
case addr(1 downto 0) is
when "00" => data(15 downto 0) := loaded(31 downto 16);
when "10" => data(15 downto 0) := loaded(15 downto 0);
when others => report "Unalligned halfword read" severity error;
end case;
end procedure;
procedure load_word(addr : unsigned(31 downto 0); data : out std_logic_vector(31 downto 0)) is
variable loaded : std_logic_vector(31 downto 0);
begin
if is_io(addr) then
io_read <= '1';
io_addr <= unsigned(addr);
io_byte_en <= (others => '1');
wait until clock='1';
io_read <= '0';
while io_ack = '0' loop
wait until clock='1';
end loop;
loaded := io_rdata;
else
loaded := dmem(to_integer(addr(c_memory_size_bytes-1 downto 2)));
end if;
data := loaded;
assert addr(1 downto 0) = "00"
report "Unalligned dword read" severity error;
end procedure;
procedure store_byte(addr : unsigned(31 downto 0); data : std_logic_vector(7 downto 0)) is
variable loaded : std_logic_vector(31 downto 0);
begin
if is_io(addr) then
io_write <= '1';
io_addr <= unsigned(addr);
io_wdata <= data & data & data & data;
case addr(1 downto 0) is
when "00" => io_byte_en <= "1000";
when "01" => io_byte_en <= "0100";
when "10" => io_byte_en <= "0010";
when "11" => io_byte_en <= "0001";
when others => io_byte_en <= "0000";
end case;
wait until clock='1';
io_write <= '0';
while io_ack = '0' loop
wait until clock='1';
end loop;
else
loaded := dmem(to_integer(addr(c_memory_size_bytes-1 downto 2)));
case addr(1 downto 0) is
when "00" => loaded(31 downto 24) := data;
when "01" => loaded(23 downto 16) := data;
when "10" => loaded(15 downto 8) := data;
when "11" => loaded(7 downto 0) := data;
when others => null;
end case;
dmem(to_integer(addr(c_memory_size_bytes-1 downto 2))) := loaded;
end if;
end procedure;
procedure store_half(addr : unsigned(31 downto 0); data : std_logic_vector(15 downto 0)) is
variable loaded : std_logic_vector(31 downto 0);
begin
if is_io(addr) then
io_write <= '1';
io_addr <= unsigned(addr);
io_wdata <= data & data;
case addr(1 downto 0) is
when "00" => io_byte_en <= "1100";
when "10" => io_byte_en <= "0011";
when others => io_byte_en <= "0000";
end case;
wait until clock='1';
io_write <= '0';
while io_ack = '0' loop
wait until clock='1';
end loop;
else
loaded := dmem(to_integer(addr(c_memory_size_bytes-1 downto 2)));
case addr(1 downto 0) is
when "00" => loaded(31 downto 16) := data;
when "10" => loaded(15 downto 0) := data;
when others => report "Unalligned halfword write" severity error;
end case;
dmem(to_integer(addr(c_memory_size_bytes-1 downto 2))) := loaded;
end if;
assert addr(0) = '0'
report "Unalligned halfword write" severity error;
end procedure;
procedure store_word(addr : unsigned(31 downto 0); data : std_logic_vector(31 downto 0)) is
begin
if is_io(addr) then
io_write <= '1';
io_addr <= unsigned(addr);
io_wdata <= data;
io_byte_en <= "1111";
wait until clock='1';
io_write <= '0';
while io_ack = '0' loop
wait until clock='1';
end loop;
else
dmem(to_integer(addr(c_memory_size_bytes-1 downto 2))) := data;
end if;
assert addr(1 downto 0) = "00"
report "Unalligned dword write" severity error;
end procedure;
procedure check_zero(a : std_logic_vector) is
begin
assert unsigned(a) = 0
report "Modifier bits not zero.. Illegal instruction?"
severity warning;
end procedure;
procedure dbPrint3(pc : unsigned(31 downto 0); inst : std_logic_vector(31 downto 0); s : string) is
begin
dbPrint(pc, inst, s & "R" & str(rd) & ", R" & str(ra) & ", R" & str(rb));
end procedure;
procedure dbPrint2(pc : unsigned(31 downto 0); inst : std_logic_vector(31 downto 0); s : string) is
begin
dbPrint(pc, inst, s & "R" & str(rd) & ", R" & str(ra));
end procedure;
procedure dbPrint2i(pc : unsigned(31 downto 0); inst : std_logic_vector(31 downto 0); s : string) is
begin
dbPrint(pc, inst, s & "R" & str(rd) & ", R" & str(ra) & ", 0x" & hstr(unsigned(imm)));
end procedure;
procedure dbPrintBr(pc : unsigned(31 downto 0); inst : std_logic_vector(31 downto 0); delay, absolute, link, immediate : std_logic; chk : integer) is
variable base : string(1 to 6) := " ";
variable n : integer := 4;
begin
case chk is
when 0 => base(1 to 3) := "BEQ";
when 1 => base(1 to 3) := "BNE";
when 2 => base(1 to 3) := "BLT";
when 3 => base(1 to 3) := "BLE";
when 4 => base(1 to 3) := "BGT";
when 5 => base(1 to 3) := "BGE";
when others => base(1 to 2) := "BR"; n := 3;
end case;
if absolute='1' then base(n) := 'A'; n := n + 1; end if;
if link='1' then base(n) := 'L'; n := n + 1; end if;
if immediate='1' then base(n) := 'I'; n := n + 1; end if;
if delay='1' then base(n) := 'D'; n := n + 1; end if;
if link='1' then
dbPrint(pc, inst, base & " R" & str(rd) & " => " & hstr(new_pc));
elsif chk = 15 then
dbPrint(pc, inst, base & " => " & hstr(new_pc));
else
dbPrint(pc, inst, base & " R" & str(ra) & " => " & hstr(new_pc));
end if;
end procedure;
procedure execute_instruction(pc : unsigned(31 downto 0)) is
variable inst : std_logic_vector(31 downto 0);
variable data : std_logic_vector(31 downto 0);
variable temp : std_logic;
begin
inst := imem(to_integer(pc(c_memory_size_bytes-1 downto 2)));
rd := to_integer(unsigned(inst(25 downto 21)));
ra := to_integer(unsigned(inst(20 downto 16)));
rb := to_integer(unsigned(inst(15 downto 11)));
reg(0) := (others => '0');
imm(15 downto 0) := signed(inst(15 downto 0));
if imm_lock='0' then
imm(31 downto 16) := (others => inst(15)); -- sign extend
end if;
imm_lock := '0';
io_write <= '0';
io_read <= '0';
io_addr <= (others => '0');
io_byte_en <= (others => '0');
new_pc := pc + 4;
case inst(31 downto 26) is
when "000000" => -- ADD Rd,Ra,Rb
dbPrint3(pc, inst, "ADD ");
perform_add(reg(ra), reg(rb), '0', true);
check_zero(inst(10 downto 0));
when "000001" => -- RSUB Rd,Ra,Rb
dbPrint3(pc, inst, "RSUB ");
perform_add(not reg(ra), reg(rb), '1', true);
check_zero(inst(10 downto 0));
when "000010" => -- ADDC Rd,Ra,Rb
dbPrint3(pc, inst, "ADDC ");
perform_add(reg(ra), reg(rb), C_flag, true);
check_zero(inst(10 downto 0));
when "000011" => -- RSUBC Rd,Ra,Rb
dbPrint3(pc, inst, "RSUBC ");
perform_add(not reg(ra), reg(rb), C_flag, true);
check_zero(inst(10 downto 0));
when "000100" => -- ADDK Rd,Ra,Rb
dbPrint3(pc, inst, "ADDK ");
perform_add(reg(ra), reg(rb), '0', false);
check_zero(inst(10 downto 0));
when "000101" => -- RSUBK Rd,Ra,Rb / CMP Rd,Ra,Rb / CMPU Rd,Ra,Rb
if inst(1 downto 0) = "01" then -- CMP
dbPrint3(pc, inst, "CMP ");
temp := not to_std(signed(reg(rb)) >= signed(reg(ra)));
perform_add(not reg(ra), reg(rb), '1', false);
reg(rd)(31) := temp;
elsif inst(1 downto 0) = "11" then -- CMPU
dbPrint3(pc, inst, "CMPU ");
temp := not to_std(unsigned(reg(rb)) >= unsigned(reg(ra)));
perform_add(not reg(ra), reg(rb), '1', false);
reg(rd)(31) := temp;
else
dbPrint3(pc, inst, "RSUBK ");
perform_add(not reg(ra), reg(rb), '1', false);
end if;
check_zero(inst(10 downto 2));
when "000110" => -- ADDKC Rd,Ra,Rb
dbPrint3(pc, inst, "ADDKC ");
perform_add(reg(ra), reg(rb), C_flag, false);
check_zero(inst(10 downto 0));
when "000111" => -- RSUBKC Rd,Ra,Rb
dbPrint3(pc, inst, "RSUBKC ");
perform_add(not reg(ra), reg(rb), C_flag, false);
when "001000" => -- ADDI Rd,Ra,Imm
dbPrint2i(pc, inst, "ADDI ");
perform_add(reg(ra), imm, '0', true);
when "001001" => -- RSUBI Rd,Ra,Imm
dbPrint2i(pc, inst, "RSUBI ");
perform_add(not reg(ra), imm, '1', true);
when "001010" => -- ADDIC Rd,Ra,Imm
dbPrint2i(pc, inst, "ADDIC ");
perform_add(reg(ra), imm, C_flag, true);
when "001011" => -- RSUBIC Rd,Ra,Imm
dbPrint2i(pc, inst, "RSUBIC ");
perform_add(not reg(ra), imm, C_flag, true);
when "001100" => -- ADDIK Rd,Ra,Imm
dbPrint2i(pc, inst, "ADDIK ");
perform_add(reg(ra), imm, '0', false);
when "001101" => -- RSUBIK Rd,Ra,Imm
dbPrint2i(pc, inst, "RSUBIK ");
perform_add(not reg(ra), imm, '1', false);
when "001110" => -- ADDIKC Rd,Ra,Imm
dbPrint2i(pc, inst, "ADDIKC ");
perform_add(reg(ra), imm, C_flag, false);
when "001111" => -- RSUBIKC Rd,Ra,Imm
dbPrint2i(pc, inst, "RSUBIKC ");
perform_add(not reg(ra), imm, C_flag, false);
when "010000" => -- MUL/MULH/MULHSU/MULHU Rd,Ra,Rb
unimplemented("MUL/MULH/MULHSU/MULHU Rd,Ra,Rb");
when "010001" => -- BSRA Rd,Ra,Rb / BSLL Rd,Ra,Rb (Barrel shift)
unimplemented("BSRA Rd,Ra,Rb / BSLL Rd,Ra,Rb (Barrel shift)");
when "010010" => -- IDIV Rd,Ra,Rb / IDIVU Rd,Ra,Rb
unimplemented("IDIV Rd,Ra,Rb / IDIVU Rd,Ra,Rb");
when "010011" => --
illegal(pc);
when "010100" => --
illegal(pc);
when "010101" => --
illegal(pc);
when "010110" => --
illegal(pc);
when "010111" => --
illegal(pc);
when "011000" => -- MULI Rd,Ra,Imm
unimplemented("MULI Rd,Ra,Imm");
when "011001" => -- BSRLI Rd,Ra,Imm / BSRAI Rd,Ra,Imm / BSLLI Rd,Ra,Imm
unimplemented("BSRLI Rd,Ra,Imm / BSRAI Rd,Ra,Imm / BSLLI Rd,Ra,Imm");
when "011010" => --
illegal(pc);
when "011011" => --
illegal(pc);
when "011100" => --
illegal(pc);
when "011101" => --
illegal(pc);
when "011110" => --
illegal(pc);
when "011111" => --
illegal(pc);
when "100000" => -- OR Rd,Ra,Rb / PCMPBF Rd,Ra,Rb
if inst(10)='1' then
unimplemented("PCMPBF Rd,Ra,Rb");
else
dbPrint3(pc, inst, "OR ");
reg(rd) := reg(ra) or reg(rb);
end if;
check_zero(inst(9 downto 0));
when "100001" => -- AND Rd,Ra,Rb
dbPrint3(pc, inst, "AND ");
reg(rd) := reg(ra) and reg(rb);
check_zero(inst(10 downto 0));
when "100010" => -- XOR Rd,Ra,Rb / PCMPEQ Rd,Ra,Rb
if inst(10)='1' then
unimplemented("PCMPEQ Rd,Ra,Rb");
else
dbPrint3(pc, inst, "XOR ");
reg(rd) := reg(ra) xor reg(rb);
end if;
check_zero(inst(9 downto 0));
when "100011" => -- ANDN Rd,Ra,Rb/ PCMPNE Rd,Ra,Rb
if inst(10)='1' then
unimplemented("PCMPNE Rd,Ra,Rb");
else
dbPrint3(pc, inst, "ANDN ");
reg(rd) := reg(ra) and not reg(rb);
end if;
check_zero(inst(9 downto 0));
when "100100" => -- SRA Rd,Ra / SRC Rd,Ra / SRL Rd,Ra/ SEXT8 Rd,Ra / SEXT16 Rd,Ra
case inst(15 downto 0) is
when X"0001" => -- SRA
dbPrint2(pc, inst, "SRA ");
C_flag <= reg(ra)(0);
reg(rd) := reg(ra)(31) & reg(ra)(31 downto 1);
when X"0021" => -- SRC
dbPrint2(pc, inst, "SRC ");
C_flag <= reg(ra)(0);
reg(rd) := C_flag & reg(ra)(31 downto 1);
when X"0041" => -- SRL
dbPrint2(pc, inst, "SRL ");
C_flag <= reg(ra)(0);
reg(rd) := '0' & reg(ra)(31 downto 1);
when X"0060" => -- SEXT8
dbPrint2(pc, inst, "SEXT8 ");
reg(rd)(31 downto 8) := (others => reg(ra)(7));
reg(rd)(7 downto 0) := reg(ra)(7 downto 0);
when X"0061" => -- SEXT16
dbPrint2(pc, inst, "SEXT16 ");
reg(rd)(31 downto 16) := (others => reg(ra)(15));
reg(rd)(15 downto 0) := reg(ra)(15 downto 0);
when others =>
illegal(pc);
end case;
when "100101" => -- MTS Sd,Ra / MFS Rd,Sa / MSRCLR Rd,Imm / MSRSET Rd,Imm
case inst(15 downto 14) is
when "00" => -- SET/CLR
reg(rd) := get_msr(32);
if inst(16)='0' then -- set
dbPrint(pc, inst, "MSRSET R" & str(rd) & ", " & hstr(inst(13 downto 0)));
set_msr(get_msr(14) or inst(13 downto 0));
else -- clear
dbPrint(pc, inst, "MSRCLR R" & str(rd) & ", " & hstr(inst(13 downto 0)));
set_msr(get_msr(14) and not inst(13 downto 0));
end if;
when "10" => -- MFS (read)
dbPrint(pc, inst, "MFS R" & str(rd) & ", " & hstr(inst(13 downto 0)));
case inst(15 downto 0) is
when X"4000" =>
reg(rd) := signed(pc);
when X"4001" =>
reg(rd) := signed(get_msr(32));
when others =>
unimplemented("MFS register type " & hstr(inst(13 downto 0)));
end case;
check_zero(inst(20 downto 16));
when "11" => -- MTS (write)
dbPrint(pc, inst, "MTS R" & str(rd) & ", " & hstr(inst(13 downto 0)));
case inst(15 downto 0) is
when X"C001" =>
set_msr(std_logic_vector(reg(ra)(13 downto 0)));
when others =>
unimplemented("MTS register type " & hstr(inst(13 downto 0)));
end case;
when others =>
illegal(pc);
end case;
when "100110" => -- BR(A)(L)(D) (Rb,)Rb / BRK Rd,Rb
do_branch(pc => pc, offset => reg(rb), delay => inst(20), absolute => inst(19), link => inst(18), chk => 15);
dbPrintBr(pc => pc, inst => inst, delay => inst(20), absolute => inst(19), link => inst(18), immediate => '0', chk => 15);
if (inst(20 downto 18) = "011") then
B_flag <= '1';
end if;
check_zero(inst(10 downto 0));
when "100111" => -- Bxx Ra,Rb (Rd = type of branch)
do_branch(pc => pc, offset => reg(rb), delay => inst(25), absolute => '0', link => '0', chk => to_integer(unsigned(inst(23 downto 21))));
dbPrintBr(pc => pc, inst => inst, delay => inst(25), absolute => '0', link => '0', immediate => '0', chk => to_integer(unsigned(inst(23 downto 21))));
check_zero(inst(10 downto 0));
when "101000" => -- ORI Rd,Ra,Imm
dbPrint2i(pc, inst, "ORI ");
reg(rd) := reg(ra) or imm;
when "101001" => -- ANDI Rd,Ra,Imm
dbPrint2i(pc, inst, "ANDI ");
reg(rd) := reg(ra) and imm;
when "101010" => -- XORI Rd,Ra,Imm
dbPrint2i(pc, inst, "XORI ");
reg(rd) := reg(ra) xor imm;
when "101011" => -- ANDNI Rd,Ra,Imm
dbPrint2i(pc, inst, "ANDNI ");
reg(rd) := reg(ra) and not imm;
when "101100" => -- IMM Imm
dbPrint(pc, inst, "IMM " & hstr(inst(15 downto 0)));
imm(31 downto 16) := signed(inst(15 downto 0));
imm_lock := '1';
check_zero(inst(25 downto 16));
when "101101" => -- RTSD Ra,Imm / RTID Ra,Imm / RTBD Ra,Imm / RTED Ra,Imm
case inst(25 downto 21) is
when "10000" =>
dbPrint(pc, inst, "RTSD R" & str(ra) & ", " & str(to_integer(imm)));
null;
when "10001" =>
dbPrint(pc, inst, "RTID R" & str(ra) & ", " & str(to_integer(imm)));
I_flag <= '1';
when "10010" =>
dbPrint(pc, inst, "RTBD R" & str(ra) & ", " & str(to_integer(imm)));
B_flag <= '0';
when "10100" =>
unimplemented("Return from exception RTED");
when others =>
illegal(pc);
end case;
new_pc := unsigned(reg(ra) + imm);
do_delay := '1';
when "101110" => -- BR(A)(L)I(D) Imm Ra / BRKI Rd,Imm
do_branch(pc => pc, offset => imm, delay => inst(20), absolute => inst(19), link => inst(18), chk => 15);
dbPrintBr(pc => pc, inst => inst, delay => inst(20), absolute => inst(19), link => inst(18), immediate => '1', chk => 15);
if (inst(20 downto 18) = "011") then
B_flag <= '1';
end if;
when "101111" => -- BxxI Ra,Imm (Rd = type of branch)
do_branch(pc => pc, offset => imm, delay => inst(25), absolute => '0', link => '0', chk => to_integer(unsigned(inst(23 downto 21))));
dbPrintBr(pc => pc, inst => inst, delay => inst(25), absolute => '0', link => '0', immediate => '1', chk => to_integer(unsigned(inst(23 downto 21))));
when "110000" => -- LBU Rd,Ra,Rb
dbPrint3(pc, inst, "LBU ");
load_byte(unsigned(reg(ra) + reg(rb)), data);
reg(rd) := signed(data);
check_zero(inst(10 downto 0));
when "110001" => -- LHU Rd,Ra,Rb
dbPrint3(pc, inst, "LHU ");
load_half(unsigned(reg(ra) + reg(rb)), data);
reg(rd) := signed(data);
check_zero(inst(10 downto 0));
when "110010" => -- LW Rd,Ra,Rb
dbPrint3(pc, inst, "LW ");
load_word(unsigned(reg(ra) + reg(rb)), data);
reg(rd) := signed(data);
check_zero(inst(10 downto 0));
when "110011" => --
illegal(pc);
when "110100" => -- SB Rd,Ra,Rb
dbPrint3(pc, inst, "SB ");
store_byte(unsigned(reg(ra) + reg(rb)), std_logic_vector(reg(rd)(7 downto 0)));
check_zero(inst(10 downto 0));
when "110101" => -- SH Rd,Ra,Rb
dbPrint3(pc, inst, "SH ");
store_half(unsigned(reg(ra) + reg(rb)), std_logic_vector(reg(rd)(15 downto 0)));
check_zero(inst(10 downto 0));
when "110110" => -- SW Rd,Ra,Rb
dbPrint3(pc, inst, "SW ");
store_word(unsigned(reg(ra) + reg(rb)), std_logic_vector(reg(rd)));
check_zero(inst(10 downto 0));
when "110111" => --
illegal(pc);
when "111000" => -- LBUI Rd,Ra,Imm
dbPrint2i(pc, inst, "LBUI ");
load_byte(unsigned(reg(ra) + imm), data);
reg(rd) := signed(data);
when "111001" => -- LHUI Rd,Ra,Imm
dbPrint2i(pc, inst, "LHUI ");
load_half(unsigned(reg(ra) + imm), data);
reg(rd) := signed(data);
when "111010" => -- LWI Rd,Ra,Imm
dbPrint2i(pc, inst, "LWI ");
load_word(unsigned(reg(ra) + imm), data);
reg(rd) := signed(data);
when "111011" => --
illegal(pc);
when "111100" => -- SBI Rd,Ra,Imm
dbPrint2i(pc, inst, "SBI ");
store_byte(unsigned(reg(ra) + imm), std_logic_vector(reg(rd)(7 downto 0)));
when "111101" => -- SHI Rd,Ra,Imm
dbPrint2i(pc, inst, "SHI ");
store_half(unsigned(reg(ra) + imm), std_logic_vector(reg(rd)(15 downto 0)));
when "111110" => -- SWI Rd,Ra,Imm
dbPrint2i(pc, inst, "SW ");
store_word(unsigned(reg(ra) + imm), std_logic_vector(reg(rd)));
when "111111" => --
illegal(pc);
when others =>
illegal(pc);
end case;
end procedure execute_instruction;
variable old_pc : unsigned(31 downto 0);
begin
if reset='1' then
pc_reg <= (others => '0');
io_addr <= (others => '0');
io_wdata <= (others => '0');
io_read <= '0';
io_write <= '0';
else
D_flag <= '0';
execute_instruction(pc_reg);
old_pc := pc_reg;
pc_reg <= new_pc;
if do_delay='1' then
wait until clock='1';
D_flag <= '1';
do_delay := '0';
execute_instruction(old_pc + 4); -- old PC + 4
end if;
end if;
wait until clock='1';
end process;
end architecture;
| gpl-3.0 | 45fa4ce4070e3e53f4ae797816dfd984 | 0.433052 | 3.919339 | false | false | false | false |
markusC64/1541ultimate2 | fpga/io/audio/i2s_serializer_old.vhd | 1 | 2,753 | -------------------------------------------------------------------------------
-- Title : i2s_serializer
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: I2S Serializer / Deserializer
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity i2s_serializer_old is
port (
clock : in std_logic; -- equals i2s_mclk
reset : in std_logic;
i2s_out : out std_logic;
i2s_in : in std_logic;
i2s_bclk : out std_logic;
i2s_fs : out std_logic;
stream_out_data : out std_logic_vector(23 downto 0);
stream_out_tag : out std_logic_vector(0 downto 0);
stream_out_valid : out std_logic;
stream_in_data : in std_logic_vector(23 downto 0);
stream_in_tag : in std_logic_vector(0 downto 0);
stream_in_valid : in std_logic;
stream_in_ready : out std_logic );
end entity;
architecture rtl of i2s_serializer_old is
signal bit_count : unsigned(7 downto 0);
signal shift_reg : std_logic_vector(31 downto 0) := (others => '0');
begin
-- mclk = 256*fs. bclk = 64*fs (32 bits per channel)
process(clock)
begin
if rising_edge(clock) then
bit_count <= bit_count + 1;
i2s_bclk <= bit_count(1);
i2s_fs <= bit_count(7);
stream_in_ready <= '0';
stream_out_valid <= '0';
if bit_count(1 downto 0) = "00" then
i2s_out <= shift_reg(shift_reg'left);
elsif bit_count(1 downto 0) = "10" then
shift_reg <= shift_reg(shift_reg'left-1 downto 0) & i2s_in;
end if;
if bit_count(6 downto 0) = "1111110" then
stream_out_data <= shift_reg(shift_reg'left-2 downto shift_reg'left - 25);
stream_out_tag(0) <= bit_count(7);
stream_out_valid <= '1';
if stream_in_valid = '1' and ((bit_count(7) xor stream_in_tag(0)) = '1') then
shift_reg <= '0' & stream_in_data & "0000000";
stream_in_ready <= '1';
else
shift_reg <= (others => '0');
end if;
end if;
if reset='1' then
bit_count <= (others => '1');
i2s_out <= '0';
stream_in_ready <= '0';
stream_out_valid <= '0';
end if;
end if;
end process;
end architecture;
| gpl-3.0 | 3e3f72996ea71f0ab87fa3f79afba0c7 | 0.449691 | 3.786795 | false | false | false | false |
markusC64/1541ultimate2 | fpga/6502n/vhdl_source/proc_registers.vhd | 1 | 14,948 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.pkg_6502_defs.all;
use work.pkg_6502_decode.all;
-- synthesis translate_off
library std;
use std.textio.all;
--use work.file_io_pkg.all;
-- synthesis translate_on
entity proc_registers is
generic (
vector_page : std_logic_vector(15 downto 4) := X"FFF" );
port (
clock : in std_logic;
clock_en : in std_logic;
ready : in std_logic;
reset : in std_logic;
-- package pins
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
so_n : in std_logic := '1';
-- data from "data_oper"
alu_data : in std_logic_vector(7 downto 0);
mem_data : in std_logic_vector(7 downto 0);
mem_n : in std_logic := '0';
mem_z : in std_logic := '0';
mem_c : in std_logic := '0';
new_flags : in std_logic_vector(7 downto 0);
flags_imm : in std_logic;
-- from implied handler
set_a : in std_logic;
set_x : in std_logic;
set_y : in std_logic;
set_s : in std_logic;
set_data : in std_logic_vector(7 downto 0);
-- interrupt pins
set_i_flag : in std_logic;
vect_addr : in std_logic_vector(3 downto 0);
-- from processor state machine and decoder
sync : in std_logic; -- latch ireg
rwn : in std_logic;
latch_dreg : in std_logic;
vectoring : in std_logic;
reg_update : in std_logic;
flags_update : in std_logic := '0';
copy_d2p : in std_logic;
a_mux : in t_amux;
dout_mux : in t_dout_mux;
pc_oper : in t_pc_oper;
s_oper : in t_sp_oper;
adl_oper : in t_adl_oper;
adh_oper : in t_adh_oper;
-- outputs to processor state machine
i_reg : out std_logic_vector(7 downto 0) := X"00";
index_carry : out std_logic;
pc_carry : out std_logic;
branch_taken : out boolean;
-- register outputs
addr_out : out std_logic_vector(15 downto 0) := X"FFFF";
d_reg : out std_logic_vector(7 downto 0) := X"00";
a_reg : out std_logic_vector(7 downto 0) := X"00";
x_reg : out std_logic_vector(7 downto 0) := X"00";
y_reg : out std_logic_vector(7 downto 0) := X"00";
s_reg : out std_logic_vector(7 downto 0) := X"00";
p_reg : out std_logic_vector(7 downto 0) := X"00";
pc_out : out std_logic_vector(15 downto 0) );
end proc_registers;
architecture gideon of proc_registers is
signal dreg : std_logic_vector(7 downto 0) := X"00";
signal data_out_i : std_logic_vector(7 downto 0) := X"00";
signal a_reg_i : std_logic_vector(7 downto 0) := X"00";
signal x_reg_i : std_logic_vector(7 downto 0) := X"00";
signal y_reg_i : std_logic_vector(7 downto 0) := X"00";
signal selected_idx : std_logic_vector(7 downto 0) := X"00";
signal i_reg_i : std_logic_vector(7 downto 0) := X"00";
signal s_reg_i : unsigned(7 downto 0) := X"00";
signal p_reg_i : std_logic_vector(7 downto 0) := X"30";
signal pcl, pch : unsigned(7 downto 0) := X"FF";
signal adl, adh : unsigned(7 downto 0) := X"00";
signal pc_carry_i : std_logic;
signal pc_carry_d : std_logic;
signal branch_flag : std_logic;
signal reg_out : std_logic_vector(7 downto 0);
signal h_reg_i : unsigned(7 downto 0);
signal ready_d1 : std_logic;
signal so_d : std_logic;
alias C_flag : std_logic is p_reg_i(0);
alias Z_flag : std_logic is p_reg_i(1);
alias I_flag : std_logic is p_reg_i(2);
alias D_flag : std_logic is p_reg_i(3);
alias B_flag : std_logic is p_reg_i(4);
alias V_flag : std_logic is p_reg_i(6);
alias N_flag : std_logic is p_reg_i(7);
signal p_reg_push : std_logic_vector(7 downto 0);
signal adh_clash : std_logic;
begin
p_reg_push <= p_reg_i(7 downto 6) & '1' & not vectoring & p_reg_i(3 downto 0);
process(clock)
variable pcl_t : unsigned(8 downto 0);
variable adl_t : unsigned(8 downto 0);
variable v_adh : unsigned(7 downto 0);
variable v_reg_sel : std_logic_vector(1 downto 0);
-- synthesis translate_off
file fout : text;
variable count : integer := 0;
variable L : line;
-- synthesis translate_on
begin
if rising_edge(clock) then
if clock_en='1' then
if flags_imm='1' then
p_reg_i <= new_flags;
end if;
-- Logic for the crazy instructions that and with adh + 1
h_reg_i <= X"FF";
ready_d1 <= ready;
adh_clash <= '0';
if ready_d1='1' then
-- $93 $9E/$9F $9C $9B
if i_reg_i(4 downto 0) = "10011" or i_reg_i(4 downto 1) = "1111" or i_reg_i(4 downto 0) = "11100" or i_reg_i(4 downto 0) = "11011" then
h_reg_i <= adh + 1;
if i_reg_i(7 downto 5) = "100" then
adh_clash <= '1';
end if;
end if;
end if;
if ready='1' or rwn='0' then
---- synthesis translate_off
-- if count = 0 then
-- file_open(fout, "trace.txt", WRITE_MODE);
-- elsif count = 180000 then
-- file_close(fout);
-- elsif count < 180000 then
-- write(L, "PC:" & VecToHex(pch, 2) & VecToHex(pcl, 2));
-- write(L, " AD:" & VecToHex(adh, 2) & VecToHex(adl, 2));
-- write(L, " A:" & VecToHex(a_reg_i, 2));
-- write(L, " X:" & VecToHex(x_reg_i, 2));
-- write(L, " Y:" & VecToHex(y_reg_i, 2));
-- write(L, " S:" & VecToHex(s_reg_i, 2));
-- write(L, " P:" & VecToHex(p_reg_i, 2));
-- write(L, " D:" & VecToHex(dreg, 2));
-- write(L, " DO:" & VecToHex(data_out_i, 2));
-- write(L, " I:" & VecToHex(i_reg_i, 2));
-- writeline(fout, L);
-- end if;
-- count := count + 1;
---- synthesis translate_on
-- Data Register
if latch_dreg='1' then
if rwn = '0' then
dreg <= data_out_i;
else
dreg <= data_in;
end if;
end if;
-- Flags Register
if copy_d2p = '1' then
p_reg_i <= dreg;
elsif reg_update='1' then
p_reg_i <= new_flags;
elsif flags_update='1' then
C_flag <= mem_c;
N_flag <= mem_n;
Z_flag <= mem_z;
end if;
if set_i_flag='1' then
I_flag <= '1';
end if;
so_d <= so_n;
if so_n='0' and so_d = '1' then -- assumed that so_n is synchronous
V_flag <= '1';
end if;
-- Instruction Register
if sync='1' then
if vectoring='1' then
i_reg_i <= X"00";
else
i_reg_i <= data_in;
end if;
end if;
-- Logic for the Program Counter
pc_carry_i <= '0';
case pc_oper is
when increment =>
if pcl = X"FF" then
pch <= pch + 1;
end if;
pcl <= pcl + 1;
when copy =>
pcl <= unsigned(dreg);
pch <= unsigned(data_in);
when from_alu =>
pcl_t := ('0' & pcl) + unsigned(dreg(7) & dreg); -- sign extended 1 bit
pcl <= pcl_t(7 downto 0);
pc_carry_i <= pcl_t(8);
pc_carry_d <= dreg(7);
when others => -- keep (and fix)
if pc_carry_i='1' then
if pc_carry_d='1' then
pch <= pch - 1;
else
pch <= pch + 1;
end if;
end if;
end case;
-- Logic for the Address register
case adl_oper is
when increment =>
adl <= adl + 1;
when add_idx =>
adl_t := unsigned('0' & dreg) + unsigned('0' & selected_idx);
adl <= adl_t(7 downto 0);
index_carry <= adl_t(8);
when load_bus =>
adl <= unsigned(data_in);
when copy_dreg =>
adl <= unsigned(dreg);
when others =>
null;
end case;
case adh_oper is
when increment =>
v_adh := adh + 1;
if adh_clash = '1' then
v_reg_sel := i_reg_i(1 downto 0);
case v_reg_sel is
when "00" => v_adh := v_adh and unsigned(y_reg_i);
when "01" => v_adh := v_adh and unsigned(a_reg_i);
when "10" => v_adh := v_adh and unsigned(x_reg_i);
when others => v_adh := v_adh and unsigned(x_reg_i) and unsigned(a_reg_i);
end case;
end if;
adh <= v_adh;
when clear =>
adh <= (others => '0');
when load_bus =>
adh <= unsigned(data_in);
when others =>
null;
end case;
-- Logic for ALU register
if reg_update='1' then
if set_a='1' then
a_reg_i <= set_data;
elsif store_a_from_alu(i_reg_i) then
a_reg_i <= alu_data;
end if;
end if;
-- Logic for Index registers
if reg_update='1' then
if set_x='1' then
x_reg_i <= set_data;
elsif load_x(i_reg_i) then
x_reg_i <= alu_data;
end if;
end if;
if reg_update='1' then
if set_y='1' then
y_reg_i <= set_data;
elsif load_y(i_reg_i) then
y_reg_i <= dreg;
end if;
end if;
-- Logic for the Stack Pointer
if reg_update='1' and set_s='1' then
s_reg_i <= unsigned(set_data);
else
case s_oper is
when increment =>
s_reg_i <= s_reg_i + 1;
when decrement =>
s_reg_i <= s_reg_i - 1;
when others =>
null;
end case;
end if;
end if;
end if;
-- Reset
if reset='1' then
p_reg_i <= X"34"; -- I=1
index_carry <= '0';
so_d <= '1';
end if;
end if;
end process;
with i_reg_i(7 downto 6) select branch_flag <=
N_flag when "00",
V_flag when "01",
C_flag when "10",
Z_flag when "11",
'0' when others;
branch_taken <= (branch_flag xor not i_reg_i(5))='1';
with a_mux select addr_out <=
vector_page & vect_addr when 0,
std_logic_vector(adh & adl) when 1,
X"01" & std_logic_vector(s_reg_i) when 2,
std_logic_vector(pch & pcl) when 3;
with i_reg_i(1 downto 0) select reg_out <=
std_logic_vector(h_reg_i) and y_reg_i when "00",
std_logic_vector(h_reg_i) and a_reg_i when "01",
std_logic_vector(h_reg_i) and x_reg_i when "10",
std_logic_vector(h_reg_i) and a_reg_i and x_reg_i when others;
with dout_mux select data_out_i <=
dreg when reg_d,
a_reg_i when reg_accu,
reg_out when reg_axy,
p_reg_push when reg_flags,
std_logic_vector(pcl) when reg_pcl,
std_logic_vector(pch) when reg_pch,
mem_data when shift_res,
X"FF" when others;
data_out <= data_out_i;
selected_idx <= y_reg_i when select_index_y(i_reg_i) else x_reg_i;
pc_carry <= pc_carry_i;
s_reg <= std_logic_vector(s_reg_i);
p_reg <= p_reg_i;
i_reg <= i_reg_i;
a_reg <= a_reg_i;
x_reg <= x_reg_i;
y_reg <= y_reg_i;
d_reg <= dreg;
pc_out <= std_logic_vector(pch & pcl);
end gideon;
| gpl-3.0 | ea50003b67023e0dda6e827d6ba18f18 | 0.383463 | 3.933684 | false | false | false | false |
markusC64/1541ultimate2 | fpga/altera/testbench/mem_io_synth_tb.vhd | 1 | 2,571 | --------------------------------------------------------------------------------
-- Entity: mem_io_synth
-- Date:2016-07-17
-- Author: Gideon
--
-- Description: Testbench for altera io for ddr
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mem_io_synth_tb is
generic (
g_out_delay : time := 8.5 ns;
g_in_delay : time := 2.0 ns );
end entity;
architecture arch of mem_io_synth_tb is
signal ref_clock : std_logic := '0';
signal ref_reset : std_logic;
signal SDRAM_CLK : std_logic := 'Z';
signal SDRAM_CLKn : std_logic := 'Z';
signal SDRAM_A : std_logic_vector(7 downto 0);
signal SDRAM_DQ : std_logic_vector(3 downto 0) := (others => 'Z');
signal SDRAM_DQS : std_logic;
signal write_data : std_logic_vector(15 downto 0);
signal read_data : std_logic_vector(15 downto 0);
signal do_read : std_logic;
signal delayed_clock : std_logic;
signal delayed_addr : std_logic_vector(7 downto 0);
begin
ref_clock <= not ref_clock after 10 ns; -- 20 ns cycle time
ref_reset <= '1', '0' after 100 ns;
i_mut: entity work.mem_io_synth
port map (
ref_clock => ref_clock,
ref_reset => ref_reset,
SDRAM_CLK => SDRAM_CLK,
SDRAM_CLKn => SDRAM_CLKn,
SDRAM_A => SDRAM_A,
SDRAM_DQ => SDRAM_DQ,
SDRAM_DQS => SDRAM_DQS,
write_data => write_data,
read_data => read_data,
do_read => do_read
);
delayed_clock <= transport SDRAM_CLK after g_out_delay;
delayed_addr <= transport SDRAM_A after g_out_delay;
process(delayed_clock)
variable delay : integer := -10;
begin
if rising_edge(delayed_clock) then
if delayed_addr(7 downto 4) = "0110" then
delay := 7;
end if;
end if;
delay := delay - 1;
case delay is
when 0 =>
SDRAM_DQ <= transport X"2" after g_in_delay;
when -1 =>
SDRAM_DQ <= transport X"3" after g_in_delay;
when -2 =>
SDRAM_DQ <= transport X"4" after g_in_delay;
when -3 =>
SDRAM_DQ <= transport X"5" after g_in_delay;
when others =>
SDRAM_DQ <= transport "ZZZZ" after g_in_delay;
end case;
end process;
end arch;
| gpl-3.0 | 21881fba5200b25d5bd1bcbc1113dc97 | 0.492804 | 3.731495 | false | false | false | false |
markusC64/1541ultimate2 | fpga/io/usb2/vhdl_source/ulpi_pkg.vhd | 2 | 2,703 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package ulpi_pkg is
constant c_ulpireg_func_ctrl : std_logic_vector(5 downto 0) := "000100";
constant c_ulpireg_otg_ctrl : std_logic_vector(5 downto 0) := "001010";
constant func_ctrl_xcvr_hs : std_logic_vector(7 downto 0) := "01000000";
constant func_ctrl_xcvr_fs : std_logic_vector(7 downto 0) := "01000001";
constant func_ctrl_xcvr_ls : std_logic_vector(7 downto 0) := "01000010";
constant func_ctrl_xcvr_preamb : std_logic_vector(7 downto 0) := "01000011";
constant func_ctrl_term_select_0 : std_logic_vector(7 downto 0) := "01000000";
constant func_ctrl_term_select_1 : std_logic_vector(7 downto 0) := "01000100";
constant func_ctrl_opmode_normal : std_logic_vector(7 downto 0) := "01000000";
constant func_ctrl_opmode_no_drv : std_logic_vector(7 downto 0) := "01001000";
constant func_ctrl_opmode_no_nrzi : std_logic_vector(7 downto 0) := "01010000";
constant func_ctrl_reset : std_logic_vector(7 downto 0) := "01100000";
constant func_ctrl_suspend_not : std_logic_vector(7 downto 0) := "00000000";
constant otg_ctrl_id_pullup : std_logic_vector(7 downto 0) := "00000001";
constant otg_ctrl_dp_pulldown : std_logic_vector(7 downto 0) := "00000010";
constant otg_ctrl_dm_pulldown : std_logic_vector(7 downto 0) := "00000100";
constant otg_ctrl_discharge_vbus : std_logic_vector(7 downto 0) := "00001000";
constant otg_ctrl_charge_vbus : std_logic_vector(7 downto 0) := "00010000";
constant otg_ctrl_drive_vbus : std_logic_vector(7 downto 0) := "00100000";
constant otg_ctrl_drive_vbus_ext : std_logic_vector(7 downto 0) := "01000000";
constant otg_ctrl_use_ext_vbus : std_logic_vector(7 downto 0) := "10000000";
function map_speed(i : std_logic_vector(1 downto 0)) return std_logic_vector;
end package;
package body ulpi_pkg is
function map_speed(i : std_logic_vector(1 downto 0)) return std_logic_vector is
begin
case i is
when "00" =>
return func_ctrl_xcvr_ls or func_ctrl_term_select_1; -- LS mode
when "01" =>
return func_ctrl_xcvr_fs or func_ctrl_term_select_1; -- FS mode
when "10" =>
return func_ctrl_xcvr_hs or func_ctrl_term_select_0; -- HS mode
when others =>
return func_ctrl_xcvr_hs or func_ctrl_term_select_0 or func_ctrl_opmode_no_nrzi; -- stay in chirp mode
end case;
return X"00";
end function;
end package body;
| gpl-3.0 | 9fd2c24945a7bf9a838a295c1998ff14 | 0.617832 | 3.395729 | false | false | false | false |
markusC64/1541ultimate2 | fpga/1541/vhdl_source/cpu_part_1581.vhd | 1 | 12,841 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
use work.io_bus_pkg.all;
entity cpu_part_1581 is
generic (
g_disk_tag : std_logic_vector(7 downto 0) := X"03";
g_cpu_tag : std_logic_vector(7 downto 0) := X"02";
g_ram_base : unsigned(27 downto 0) := X"0060000" );
port (
clock : in std_logic;
falling : in std_logic;
reset : in std_logic;
tick_1kHz : in std_logic;
tick_4MHz : in std_logic;
-- serial bus pins
atn_o : out std_logic; -- open drain
atn_i : in std_logic;
clk_o : out std_logic; -- open drain
clk_i : in std_logic;
data_o : out std_logic; -- open drain
data_i : in std_logic;
fast_clk_o : out std_logic; -- open drain
fast_clk_i : in std_logic;
-- memory interface
mem_req_cpu : out t_mem_req;
mem_resp_cpu : in t_mem_resp;
mem_req_disk : out t_mem_req;
mem_resp_disk : in t_mem_resp;
mem_busy : out std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp;
io_irq : out std_logic;
-- track stepper interface (for audio samples)
do_track_in : out std_logic;
do_track_out : out std_logic;
-- drive pins
power : in std_logic;
drive_address : in std_logic_vector(1 downto 0);
write_prot_n : in std_logic;
rdy_n : in std_logic;
disk_change_n : in std_logic;
side_0 : out std_logic;
motor_on : out std_logic;
cur_track : in unsigned(6 downto 0);
act_led : out std_logic;
power_led : out std_logic );
end entity;
architecture structural of cpu_part_1581 is
signal cpu_write : std_logic;
signal cpu_wdata : std_logic_vector(7 downto 0);
signal cpu_rdata : std_logic_vector(7 downto 0);
signal cpu_addr : std_logic_vector(16 downto 0);
signal cpu_irqn : std_logic;
signal ext_rdata : std_logic_vector(7 downto 0) := X"00";
signal io_rdata : std_logic_vector(7 downto 0);
signal cia_data : std_logic_vector(7 downto 0);
signal cia_wen : std_logic;
signal cia_ren : std_logic;
signal wd_data : std_logic_vector(7 downto 0);
signal wd_wen : std_logic;
signal wd_ren : std_logic;
signal cia_port_a_o : std_logic_vector(7 downto 0);
signal cia_port_a_t : std_logic_vector(7 downto 0);
signal cia_port_a_i : std_logic_vector(7 downto 0);
signal cia_port_b_o : std_logic_vector(7 downto 0);
signal cia_port_b_t : std_logic_vector(7 downto 0);
signal cia_port_b_i : std_logic_vector(7 downto 0);
signal cia_sp_o : std_logic;
signal cia_sp_i : std_logic;
signal cia_sp_t : std_logic;
signal cia_cnt_o : std_logic;
signal cia_cnt_i : std_logic;
signal cia_cnt_t : std_logic;
signal cia_irq : std_logic;
signal io_select : std_logic;
signal cpu_clk_en : std_logic;
type t_mem_state is (idle, newcycle, extcycle);
signal mem_state : t_mem_state;
-- "old" style signals
signal mem_request : std_logic;
signal mem_addr : unsigned(25 downto 0);
signal mem_rwn : std_logic;
signal mem_rack : std_logic;
signal mem_dack : std_logic;
signal mem_wdata : std_logic_vector(7 downto 0);
-- Local signals
signal write_prot_n_i : std_logic;
signal fast_ser_dir : std_logic;
signal atn_ack : std_logic;
signal clock_out : std_logic;
signal my_data_out : std_logic;
signal my_fast_data_out : std_logic;
signal act_led_i : std_logic;
signal power_led_i : std_logic;
signal drive_address_i : std_logic_vector(1 downto 0);
signal rdy_n_i : std_logic;
signal motor_n_i : std_logic;
signal side_0_i : std_logic;
signal motor_on_i : std_logic;
begin
mem_req_cpu.request <= mem_request;
mem_req_cpu.address <= mem_addr;
mem_req_cpu.read_writen <= mem_rwn;
mem_req_cpu.data <= mem_wdata;
mem_req_cpu.tag <= g_cpu_tag;
mem_req_cpu.size <= "00"; -- 1 byte at a time
mem_rack <= '1' when mem_resp_cpu.rack_tag = g_cpu_tag else '0';
mem_dack <= '1' when mem_resp_cpu.dack_tag = g_cpu_tag else '0';
cpu: entity work.cpu6502(cycle_exact)
port map (
cpu_clk => clock,
cpu_clk_en => cpu_clk_en,
cpu_reset => reset,
cpu_write => cpu_write,
cpu_wdata => cpu_wdata,
cpu_rdata => cpu_rdata,
cpu_addr => cpu_addr,
IRQn => cpu_irqn, -- IRQ interrupt (level sensitive)
NMIn => '1',
SOn => '1' );
cpu_irqn <= not cia_irq;
cpu_clk_en <= falling;
mem_busy <= '0' when mem_state = idle else '1';
-- Fetch ROM byte
process(clock)
begin
if rising_edge(clock) then
mem_addr(25 downto 16) <= g_ram_base(25 downto 16);
case mem_state is
when idle =>
if cpu_clk_en = '1' then
mem_state <= newcycle;
end if;
when newcycle => -- we have a new address now
mem_addr(15 downto 0) <= unsigned(cpu_addr(15 downto 0));
io_select <= '0'; -- not active
-- Start by checking whether it is RAM
if cpu_addr(15 downto 13) = "000" then -- 0000-1FFF
mem_request <= '1';
mem_state <= extcycle;
elsif cpu_addr(15) = '1' then -- ROM Area, which is not overridden as RAM
if cpu_write = '0' then
mem_request <= '1';
mem_state <= extcycle;
else -- writing to rom -> ignore
mem_state <= idle;
end if;
-- It's not RAM, nor ROM, so it must be internal I/O.
else
io_select <= '1';
mem_state <= idle;
end if;
when extcycle =>
if mem_rack='1' then
mem_request <= '0';
if cpu_write='1' then
mem_state <= idle;
end if;
end if;
if mem_dack='1' and cpu_write='0' then -- only for reads
ext_rdata <= mem_resp_cpu.data;
mem_state <= idle;
end if;
when others =>
null;
end case;
if reset='1' then
io_select <= '0';
mem_request <= '0';
mem_state <= idle;
end if;
end if;
end process;
mem_rwn <= not cpu_write;
mem_wdata <= cpu_wdata;
-- address decoding and data muxing
-- 0000-1FFF and 8000-FFFF = external memory
-- 2000-3FFF is free
-- 4000-5FFF is cia
-- 6000-7FFF is wd177x
with cpu_addr(14 downto 13) select io_rdata <=
cia_data when "10",
wd_data when "11",
X"FF" when others;
cpu_rdata <= io_rdata when io_select='1' else ext_rdata;
cia_wen <= '1' when cpu_write='1' and io_select='1' and cpu_addr(14 downto 13)="10" else '0';
cia_ren <= '1' when cpu_write='0' and io_select='1' and cpu_addr(14 downto 13)="10" else '0';
wd_wen <= '1' when cpu_write='1' and io_select='1' and cpu_addr(14 downto 13)="11" else '0';
wd_ren <= '1' when cpu_write='0' and io_select='1' and cpu_addr(14 downto 13)="11" else '0';
-- I/O peripherals
i_cia1: entity work.cia_registers
generic map (
g_report => false,
g_unit_name => "CIA_1581" )
port map (
clock => clock,
falling => falling,
reset => reset,
tod_pin => '1', -- depends on jumper
addr => unsigned(cpu_addr(3 downto 0)),
data_in => cpu_wdata,
wen => cia_wen,
ren => cia_ren,
data_out => cia_data,
-- pio --
port_a_o => cia_port_a_o, -- low level floppy signals
port_a_t => cia_port_a_t,
port_a_i => cia_port_a_i,
port_b_o => cia_port_b_o, -- IEC and control
port_b_t => cia_port_b_t,
port_b_i => cia_port_b_i,
-- serial pin
sp_o => cia_sp_o, -- Burst mode IEC data
sp_i => cia_sp_i,
sp_t => cia_sp_t,
cnt_i => cia_cnt_i, -- Burst mode IEC clock
cnt_o => cia_cnt_o,
cnt_t => cia_cnt_t,
pc_o => open,
flag_i => atn_i, -- active low ATN in
irq => cia_irq );
-- correctly attach the cia pins to the outside world
write_prot_n_i <= (cia_port_b_o(6) or not cia_port_b_t(6)) and write_prot_n;
fast_ser_dir <= (cia_port_b_o(5) or not cia_port_b_t(5));
atn_ack <= (cia_port_b_o(4) or not cia_port_b_t(4));
clock_out <= (cia_port_b_o(3) or not cia_port_b_t(3));
my_data_out <= (cia_port_b_o(1) or not cia_port_b_t(1));
my_fast_data_out <= (cia_sp_o or not cia_sp_t) or not fast_ser_dir; -- active low!
cia_sp_i <= (cia_sp_o or not cia_sp_t) when fast_ser_dir = '1' else
data_i;
fast_clk_o <= (cia_cnt_o or not cia_cnt_t) or not fast_ser_dir; -- active low!
cia_cnt_i <= (cia_cnt_o or not cia_cnt_t) when fast_ser_dir = '1' else -- output
fast_clk_i; -- assume that 74LS241 wins
cia_port_b_i(7) <= not atn_i; -- assume that this signal (from 74LS14) wins
cia_port_b_i(6) <= write_prot_n_i;
cia_port_b_i(5) <= fast_ser_dir;
cia_port_b_i(4) <= atn_ack;
cia_port_b_i(3) <= clock_out;
cia_port_b_i(2) <= not clk_i; -- assume that this signal (from 74LS14) wins
cia_port_b_i(1) <= my_data_out;
cia_port_b_i(0) <= not data_i;
data_o <= (not my_data_out and not (atn_ack and not atn_i) and my_fast_data_out) or not power;
clk_o <= not power or not clock_out;
atn_o <= '1';
act_led_i <= (cia_port_a_o(6) or not cia_port_a_t(6));
power_led_i <= (cia_port_a_o(5) or not cia_port_a_t(5));
drive_address_i <= (cia_port_a_o(4 downto 3) or not cia_port_a_t(4 downto 3)) and drive_address;
motor_n_i <= (cia_port_a_o(2) or not cia_port_a_t(2));
rdy_n_i <= (cia_port_a_o(1) or not cia_port_a_t(1)) and rdy_n;
side_0_i <= (cia_port_a_o(0) or not cia_port_a_t(0));
cia_port_a_i(7) <= disk_change_n;
cia_port_a_i(6) <= act_led_i;
cia_port_a_i(5) <= power_led_i;
cia_port_a_i(4) <= drive_address_i(1);
cia_port_a_i(3) <= drive_address_i(0);
cia_port_a_i(2) <= motor_n_i;
cia_port_a_i(1) <= rdy_n_i;
cia_port_a_i(0) <= side_0_i;
power_led <= not (power_led_i and power);
act_led <= not (act_led_i and power);
motor_on_i <= not motor_n_i and power;
motor_on <= motor_on_i;
side_0 <= side_0_i;
-- Floppy Controller
i_wd177x: entity work.wd177x
generic map (
g_tag => g_disk_tag
)
port map(
clock => clock,
clock_en => cpu_clk_en,
reset => reset,
tick_1kHz => tick_1kHz,
tick_4MHz => tick_4MHz,
addr => unsigned(cpu_addr(1 downto 0)),
wen => wd_wen,
ren => wd_ren,
wdata => cpu_wdata,
rdata => wd_data,
do_track_out => do_track_out,
do_track_in => do_track_in,
cur_track => cur_track,
stepper_en => '1',
motor_en => motor_on_i,
mem_req => mem_req_disk,
mem_resp => mem_resp_disk,
io_req => io_req,
io_resp => io_resp,
io_irq => io_irq
);
end architecture;
| gpl-3.0 | a1fc5d6a1849a707d49f48b3668ea0e8 | 0.476287 | 3.259137 | false | false | false | false |
keyru/hdl-make | tests/counter/modules/counter/vhdl/counter.vhd | 2 | 1,005 | -------------------------------------------------------
-- Design : Simple 8-bit VHDL counter
-- Author : Javier D. Garcia-Lasheras
-------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------
entity counter is
port(
clock: in std_logic;
clear: in std_logic;
count: in std_logic;
Q: out std_logic_vector(7 downto 0)
);
end counter;
-------------------------------------------------------
architecture behv of counter is
signal Pre_Q: unsigned(7 downto 0);
begin
process(clock, count, clear)
begin
if clear = '1' then
Pre_Q <= "00000000";
elsif (clock='1' and clock'event) then
if count = '1' then
Pre_Q <= Pre_Q + 1;
end if;
end if;
end process;
Q <= std_logic_vector(Pre_Q);
end behv;
-------------------------------------------------------
| gpl-3.0 | 828dc74faeec2fad017e889dc918041e | 0.408955 | 4.085366 | false | false | false | false |
chiggs/nvc | test/parse/access.vhd | 4 | 206 | architecture a of e is
begin
process is
begin
x.all := 1;
v := x.all + 5;
p := new t;
p := a.all(1 to 3);
q := a.all(3);
end process;
end architecture;
| gpl-3.0 | c561bca10d643bec1d095b742f70366b | 0.451456 | 3.21875 | false | false | false | false |
markusC64/1541ultimate2 | fpga/cpu_unit/vhdl_source/dm_with_invalidate.vhd | 1 | 11,221 | --------------------------------------------------------------------------------
-- Entity: dm_with_invalidate
-- Date: 2014-12-08
-- Author: Gideon
--
-- Description: Simple direct mapped cache controller, compatible with the
-- D bus of the mblite. This version has an invalidate port.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library mblite;
use mblite.core_Pkg.all;
entity dm_with_invalidate is
generic (
g_address_swap : std_logic_vector(31 downto 0) := X"00000000" );
port (
clock : in std_logic;
reset : in std_logic;
disable : in std_logic := '0';
invalidate : in std_logic;
inv_addr : in std_logic_vector(31 downto 0);
dmem_i : in dmem_out_type;
dmem_o : out dmem_in_type;
mem_o : out dmem_out_type;
mem_i : in dmem_in_type );
end entity;
architecture arch of dm_with_invalidate is
constant c_cachable_area_bits : natural := 25;
constant c_cache_size_bits : natural := 11; -- 2**11 bytes = 2KB
constant c_tag_size_bits : natural := c_cache_size_bits - 2; -- 4 bytes per cache entry
type t_tag is record
addr_high : std_logic_vector(c_cachable_area_bits-1 downto c_cache_size_bits);
valid : std_logic;
end record;
constant c_valid_zero_tag : t_tag := ( addr_high => (others => '0'), valid => '1' );
function extend32(a : std_logic_vector) return std_logic_vector is
variable ret : std_logic_vector(31 downto 0) := (others => '0');
begin
ret(a'length-1 downto 0) := a;
return ret;
end function;
function address_to_tag (addr : std_logic_vector;
valid : std_logic) return t_tag is
variable v_addr : std_logic_vector(31 downto 0);
variable ret : t_tag;
begin
v_addr := extend32(addr);
ret.addr_high := v_addr(c_cachable_area_bits-1 downto c_cache_size_bits);
ret.valid := valid;
return ret;
end function;
constant c_tag_width : natural := c_cachable_area_bits - c_cache_size_bits + 1;
function tag_to_vector(i: t_tag) return std_logic_vector is
begin
return i.valid & i.addr_high;
end function;
constant c_valid_zero_tag_vector : std_logic_vector(c_tag_width-1 downto 0) := tag_to_vector(c_valid_zero_tag);
function vector_to_tag(i : std_logic_vector(c_tag_width-1 downto 0)) return t_tag is
variable ret : t_tag;
begin
ret.valid := i(c_tag_width-1);
ret.addr_high := i(c_tag_width-2 downto 0);
return ret;
end function;
function get_tag_index (addr : std_logic_vector) return unsigned is
begin
return unsigned(addr(c_tag_size_bits+1 downto 2));
end function;
function is_cacheable (addr : std_logic_vector) return boolean is
variable v_addr : std_logic_vector(31 downto 0);
begin
v_addr := extend32(addr);
return unsigned(v_addr(31 downto c_cachable_area_bits)) = 0;
end function;
signal tag_ram_a_address : unsigned(c_tag_size_bits-1 downto 0);
signal tag_ram_a_rdata : std_logic_vector(c_tag_width-1 downto 0);
signal tag_ram_a_wdata : std_logic_vector(c_tag_width-1 downto 0);
signal tag_ram_a_en : std_logic;
signal tag_ram_a_we : std_logic;
signal tag_ram_b_address : unsigned(c_tag_size_bits-1 downto 0) := (others => '0');
signal tag_ram_b_rdata : std_logic_vector(c_tag_width-1 downto 0) := (others => '0');
signal tag_ram_b_wdata : std_logic_vector(c_tag_width-1 downto 0) := (others => '0');
signal tag_ram_b_en : std_logic := '0';
signal tag_ram_b_we : std_logic := '0';
signal cache_ram_a_address : unsigned(c_cache_size_bits-1 downto 2);
signal cache_ram_a_rdata : std_logic_vector(31 downto 0);
signal cache_ram_a_wdata : std_logic_vector(31 downto 0);
signal cache_ram_a_en : std_logic;
signal cache_ram_a_we : std_logic;
signal cache_ram_b_address : unsigned(c_cache_size_bits-1 downto 2) := (others => '0');
signal cache_ram_b_rdata : std_logic_vector(31 downto 0) := (others => '0');
signal cache_ram_b_wdata : std_logic_vector(31 downto 0) := (others => '0');
signal cache_ram_b_en : std_logic := '0';
signal cache_ram_b_we : std_logic := '0';
signal d_tag_ram_out : t_tag;
signal d_miss : std_logic;
signal dmem_r : dmem_out_type;
signal dmem_o_comb : dmem_in_type;
signal dmem_o_reg : dmem_in_type;
type t_state is (idle, fill);
signal state : t_state;
begin
i_tag_ram: entity work.dpram_sc
generic map (
g_width_bits => c_tag_width,
g_depth_bits => c_tag_size_bits,
g_global_init => c_valid_zero_tag_vector,
g_read_first_a => false,
g_read_first_b => false,
g_storage => "block" )
port map (
clock => clock,
a_address => tag_ram_a_address,
a_rdata => tag_ram_a_rdata,
a_wdata => tag_ram_a_wdata,
a_en => tag_ram_a_en,
a_we => tag_ram_a_we,
b_address => tag_ram_b_address,
b_rdata => tag_ram_b_rdata,
b_wdata => tag_ram_b_wdata,
b_en => tag_ram_b_en,
b_we => tag_ram_b_we );
i_cache_ram: entity work.dpram_sc
generic map (
g_width_bits => 32,
g_depth_bits => c_cache_size_bits-2,
g_global_init => X"FFFFFFFF",
g_read_first_a => false,
g_read_first_b => false,
g_storage => "block" )
port map (
clock => clock,
a_address => cache_ram_a_address,
a_rdata => cache_ram_a_rdata,
a_wdata => cache_ram_a_wdata,
a_en => cache_ram_a_en,
a_we => cache_ram_a_we,
b_address => cache_ram_b_address,
b_rdata => cache_ram_b_rdata,
b_wdata => cache_ram_b_wdata,
b_en => cache_ram_b_en,
b_we => cache_ram_b_we );
d_tag_ram_out <= vector_to_tag(tag_ram_a_rdata);
-- handle the dmem address request here; split it up
process(state, dmem_i, dmem_r, mem_i, d_tag_ram_out, cache_ram_a_rdata, invalidate, inv_addr, disable)
begin
dmem_o_comb.ena_i <= '0'; -- registered out, use this signal as register load enable
dmem_o_comb.dat_i <= (others => 'X');
d_miss <= '0';
tag_ram_a_address <= get_tag_index(dmem_i.adr_o);
tag_ram_a_wdata <= (others => 'X');
tag_ram_a_we <= '0';
tag_ram_a_en <= '0';
cache_ram_a_address <= unsigned(dmem_i.adr_o(c_cache_size_bits-1 downto 2));
cache_ram_a_wdata <= dmem_i.dat_o;
cache_ram_a_we <= '0';
cache_ram_a_en <= '0';
tag_ram_b_address <= get_tag_index(dmem_r.adr_o);
tag_ram_b_wdata <= tag_to_vector(address_to_tag(dmem_r.adr_o, '1'));
tag_ram_b_we <= '0';
tag_ram_b_en <= '0';
cache_ram_b_address <= unsigned(dmem_r.adr_o(c_cache_size_bits-1 downto 2));
cache_ram_b_wdata <= mem_i.dat_i;
cache_ram_b_we <= '0';
cache_ram_b_en <= '0';
if invalidate = '1' then
tag_ram_a_address <= get_tag_index(inv_addr);
tag_ram_a_wdata <= tag_to_vector(address_to_tag(inv_addr, '0')); -- invalid
tag_ram_a_en <= '1';
tag_ram_a_we <= '1';
elsif dmem_i.ena_o = '1' then -- processor address is valid, let's do our thing
if dmem_i.we_o = '0' then -- read
tag_ram_a_en <= '1';
cache_ram_a_en <= '1';
else -- write
tag_ram_a_en <= '1';
cache_ram_a_en <= '1';
if is_cacheable(dmem_i.adr_o) then
tag_ram_a_we <= '1';
cache_ram_a_we <= '1';
end if;
if dmem_i.sel_o = "1111" then -- full word results in a valid cache line
tag_ram_a_wdata <= tag_to_vector(address_to_tag(dmem_i.adr_o, '1')); -- valid
else
tag_ram_a_wdata <= tag_to_vector(address_to_tag(dmem_i.adr_o, '0')); -- invalid
end if;
end if;
end if;
-- response to processor
case state is
when idle =>
if dmem_r.ena_o = '1' then -- registered (=delayed request valid)
if (address_to_tag(dmem_r.adr_o, '1') = d_tag_ram_out) and (dmem_r.we_o='0') and is_cacheable(dmem_r.adr_o) and disable = '0' then -- read hit!
dmem_o_comb.dat_i <= cache_ram_a_rdata;
dmem_o_comb.ena_i <= '1';
else -- miss or write
dmem_o_comb.ena_i <= '0';
d_miss <= '1';
end if;
end if; -- else use default values, hence X
when fill =>
dmem_o_comb.ena_i <= '0';
if mem_i.ena_i = '1' then
dmem_o_comb.dat_i <= mem_i.dat_i; -- ouch, 32-bit multiplexer!
dmem_o_comb.ena_i <= '1';
if dmem_r.we_o='0' and is_cacheable(dmem_r.adr_o) then -- was a read
tag_ram_b_en <= '1';
cache_ram_b_en <= '1';
tag_ram_b_we <= '1';
cache_ram_b_we <= '1';
end if;
end if;
end case;
end process;
dmem_o.dat_i <= dmem_o_reg.dat_i;
dmem_o.ena_i <= dmem_o_reg.ena_i and not invalidate;
process(state, dmem_r, d_miss)
begin
mem_o <= dmem_r;
mem_o.adr_o <= dmem_r.adr_o xor g_address_swap(dmem_r.adr_o'range);
mem_o.ena_o <= d_miss;
end process;
process(clock)
begin
if rising_edge(clock) then
case state is
when idle =>
if d_miss = '1' then
state <= fill;
end if;
when fill =>
if mem_i.ena_i = '1' then
-- dmem_r.ena_o <= '0';
state <= idle;
end if;
end case;
if dmem_i.ena_o = '1' then
dmem_o_reg.ena_i <= '0';
elsif dmem_o_comb.ena_i = '1' then
dmem_o_reg.dat_i <= dmem_o_comb.dat_i;
dmem_o_reg.ena_i <= '1';
dmem_r.ena_o <= '0';
end if;
if dmem_i.ena_o = '1' then
dmem_r <= dmem_i;
end if;
if reset='1' then
state <= idle;
dmem_o_reg.ena_i <= '1';
end if;
end if;
end process;
end arch;
| gpl-3.0 | 02c931594f7f4d5c974b7910e11cc930 | 0.492202 | 3.287723 | false | false | false | false |
markusC64/1541ultimate2 | fpga/ip/busses/vhdl_bfm/io_bus_bfm_pkg.vhd | 1 | 4,929 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
library work;
use work.io_bus_pkg.all;
package io_bus_bfm_pkg is
type t_io_bus_bfm_object;
type p_io_bus_bfm_object is access t_io_bus_bfm_object;
type t_io_bfm_command is ( e_io_none, e_io_read, e_io_write );
type t_io_bus_bfm_object is record
next_bfm : p_io_bus_bfm_object;
name : string(1 to 256);
command : t_io_bfm_command;
address : unsigned(19 downto 0);
data : std_logic_vector(7 downto 0);
end record;
------------------------------------------------------------------------------------
shared variable io_bus_bfms : p_io_bus_bfm_object := null;
------------------------------------------------------------------------------------
procedure register_io_bus_bfm(named : string; variable pntr: inout p_io_bus_bfm_object);
procedure bind_io_bus_bfm(named : string; variable pntr: inout p_io_bus_bfm_object);
------------------------------------------------------------------------------------
procedure io_read(variable io : inout p_io_bus_bfm_object; addr : unsigned; data : out std_logic_vector(7 downto 0));
procedure io_write(variable io : inout p_io_bus_bfm_object; addr : unsigned; data : std_logic_vector(7 downto 0));
procedure io_read_32(variable io : inout p_io_bus_bfm_object; addr : unsigned; data : out std_logic_vector(31 downto 0));
procedure io_write_32(variable io : inout p_io_bus_bfm_object; addr : unsigned; data : std_logic_vector(31 downto 0));
end io_bus_bfm_pkg;
package body io_bus_bfm_pkg is
procedure register_io_bus_bfm(named : string;
variable pntr : inout p_io_bus_bfm_object) is
begin
-- Allocate a new BFM object in memory
pntr := new t_io_bus_bfm_object;
-- Initialize object
pntr.next_bfm := null;
pntr.name(named'range) := named;
-- add this pointer to the head of the linked list
if io_bus_bfms = null then -- first entry
io_bus_bfms := pntr;
else -- insert new entry
pntr.next_bfm := io_bus_bfms;
io_bus_bfms := pntr;
end if;
end register_io_bus_bfm;
procedure bind_io_bus_bfm(named : string;
variable pntr : inout p_io_bus_bfm_object) is
variable p : p_io_bus_bfm_object;
begin
pntr := null;
wait for 1 ns; -- needed to make sure that binding takes place after registration
p := io_bus_bfms; -- start at the root
L1: while p /= null loop
if p.name(named'range) = named then
pntr := p;
exit L1;
else
p := p.next_bfm;
end if;
end loop;
end bind_io_bus_bfm;
------------------------------------------------------------------------------
procedure io_read(variable io : inout p_io_bus_bfm_object; addr : unsigned;
data : out std_logic_vector(7 downto 0)) is
variable a_i : unsigned(19 downto 0);
begin
a_i := (others => '0');
a_i(addr'length-1 downto 0) := addr;
io.address := a_i;
io.command := e_io_read;
while io.command /= e_io_none loop
wait for 10 ns;
end loop;
data := io.data;
end procedure;
procedure io_write(variable io : inout p_io_bus_bfm_object; addr : unsigned;
data : std_logic_vector(7 downto 0)) is
variable a_i : unsigned(19 downto 0);
begin
a_i := (others => '0');
a_i(addr'length-1 downto 0) := addr;
io.address := a_i;
io.command := e_io_write;
io.data := data;
while io.command /= e_io_none loop
wait for 10 ns;
end loop;
end procedure;
procedure io_write_32(variable io : inout p_io_bus_bfm_object; addr : unsigned;
data : std_logic_vector(31 downto 0)) is
begin
io_write(io, addr+0, data(7 downto 0));
io_write(io, addr+1, data(15 downto 8));
io_write(io, addr+2, data(23 downto 16));
io_write(io, addr+3, data(31 downto 24));
end procedure;
procedure io_read_32(variable io : inout p_io_bus_bfm_object; addr : unsigned;
data : out std_logic_vector(31 downto 0)) is
begin
io_read(io, addr+0, data(7 downto 0));
io_read(io, addr+1, data(15 downto 8));
io_read(io, addr+2, data(23 downto 16));
io_read(io, addr+3, data(31 downto 24));
end procedure;
end;
------------------------------------------------------------------------------
| gpl-3.0 | 8f50611f37496b89a9aa74f82ccbd295 | 0.501116 | 3.817971 | false | false | false | false |
jresendiz27/electronica | arquitectura/sumadorNBits/acarreoCascada/Prueba_tb.vhd | 2 | 1,278 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY Prueba_tb IS
END Prueba_tb;
ARCHITECTURE behavior OF Prueba_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Prueba
PORT(
a : IN std_logic_vector(3 downto 0);
b : IN std_logic_vector(3 downto 0);
op : IN std_logic;
s : OUT std_logic_vector(3 downto 0);
cout : OUT std_logic
);
END COMPONENT;
--Inputs
signal a : std_logic_vector(3 downto 0) := (others => '0');
signal b : std_logic_vector(3 downto 0) := (others => '0');
signal op : std_logic := '0';
--Outputs
signal s : std_logic_vector(3 downto 0);
signal cout : std_logic;
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Prueba PORT MAP (
a => a,
b => b,
op => op,
s => s,
cout => cout
);
-- estimulos de simulación
process
begin
a <= "0011";
b <= "0001";
wait for 10 ns;
a <= "0111";
b <= "0010";
--op <= '1';
wait for 10 ns;
--op <= '0';
--wait for 40 ns;
end process;
process
begin
wait for 10 ns;
op <= not op;
end process;
END;
| gpl-3.0 | a0e1b32cdbf8a6e9198bcd34108af0dd | 0.545383 | 3.285347 | false | false | false | false |
markusC64/1541ultimate2 | fpga/io/acia/vhdl_source/acia6551.vhd | 1 | 15,856 | --------------------------------------------------------------------------------
-- Entity: acia6551
-- Date:2018-11-13
-- Author: gideon
--
-- Description: This is a simple implementation of the 6551.
-- It does not actually have a serial port, but just behaves like
-- it does.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.io_bus_pkg.all;
use work.slot_bus_pkg.all;
use work.acia6551_pkg.all;
entity acia6551 is
port (
clock : in std_logic;
reset : in std_logic;
c64_reset : in std_logic := '0';
-- C64 side interface
slot_tick : in std_logic;
slot_req : in t_slot_req;
slot_resp : out t_slot_resp;
-- io interface for local cpu
io_req : in t_io_req;
io_resp : out t_io_resp;
io_irq : out std_logic );
end entity;
architecture arch of acia6551 is
signal slot_base : unsigned(8 downto 2) := (others => '0');
signal rx_data : std_logic_vector(7 downto 0);
signal status : std_logic_vector(7 downto 0) := X"00";
signal command : std_logic_vector(7 downto 0);
signal control : std_logic_vector(7 downto 0);
signal tx_data : std_logic_vector(7 downto 0);
signal tx_data_push : std_logic;
signal rx_data_valid : std_logic;
signal nmi_counter : natural range 0 to 16383 := 0;
signal nmi : std_logic;
signal irq_d : std_logic;
signal dsr_d : std_logic;
signal dcd_d : std_logic;
signal dcd_change : std_logic := '0';
signal dsr_change : std_logic := '0';
alias irq : std_logic is status(7);
alias dsr_n : std_logic is status(6);
alias dcd_n : std_logic is status(5);
alias tx_empty : std_logic is status(4);
alias rx_full : std_logic is status(3);
alias overrun_err : std_logic is status(2);
alias framing_err : std_logic is status(1);
alias parity_err : std_logic is status(0);
alias dtr : std_logic is command(0);
signal dtr_d : std_logic;
signal enable : std_logic;
signal nmi_selected : std_logic;
signal tx_irq_en : std_logic;
signal rx_irq_en : std_logic;
signal soft_reset : std_logic;
signal rx_interrupt : std_logic := '0';
signal tx_interrupt : std_logic := '0';
signal appl_tx_irq : std_logic := '0';
signal appl_rx_irq : std_logic := '0';
signal ctrl_irq_en : std_logic;
signal hs_irq_en : std_logic;
signal control_change : std_logic;
signal dtr_change : std_logic;
signal cts : std_logic; -- written by sys
signal rts : std_logic; -- written by slot (command register)
signal rx_head, rx_tail : unsigned(7 downto 0);
signal tx_head, tx_tail : unsigned(7 downto 0);
signal rx_rate : unsigned(7 downto 0);
signal rx_rate_cnt : unsigned(12 downto 0) := (others => '0');
signal rx_rate_expired : std_logic := '1';
signal b_address : unsigned(8 downto 0);
signal b_rdata : std_logic_vector(7 downto 0);
signal b_wdata : std_logic_vector(7 downto 0);
signal b_en, b_we : std_logic;
signal b_pending : std_logic;
signal io_req_regs : t_io_req;
signal io_resp_regs : t_io_resp := c_io_resp_init;
signal io_req_ram : t_io_req;
signal io_resp_ram : t_io_resp := c_io_resp_init;
signal io_ram_ack : std_logic;
signal io_ram_en : std_logic;
signal io_ram_rdata : std_logic_vector(7 downto 0);
begin
with slot_req.bus_address(1 downto 0) select slot_resp.data <=
rx_data when c_addr_data_register,
status when c_addr_status_register,
command when c_addr_command_register,
control when c_addr_control_register,
X"FF" when others;
slot_resp.reg_output <= enable when slot_req.bus_address(8 downto 2) = slot_base else '0';
slot_resp.irq <= irq and not nmi_selected;
slot_resp.nmi <= nmi and nmi_selected;
irq <= enable and (rx_interrupt and not command(1));-- or (tx_interrupt and command(2) and not command(3)));
rts <= command(2) or command(3);
rx_full <= rx_data_valid when rising_edge(clock); -- to have a register for the status word in signaltap
--tx_empty <= '0' when (tx_head + 1) = tx_tail else '1';
-- IRQs to the Host (Slot side)
tx_interrupt <= tx_empty;
rx_interrupt <= rx_data_valid or dsr_change or dcd_change; -- and rts);
-- IRQs to the Application (IO side)
appl_rx_irq <= '0' when (rx_head + 1) = rx_tail else '1'; -- RX = Appl -> Host (room for data appl can write)
appl_tx_irq <= '1' when tx_head /= tx_tail else '0'; -- TX = Host -> Appl (data appl should read)
io_irq <= (appl_rx_irq and rx_irq_en) or (appl_tx_irq and tx_irq_en) or
(control_change and ctrl_irq_en) or (dtr_change and hs_irq_en);
process(clock)
begin
if rising_edge(clock) then
soft_reset <= '0';
tx_data_push <= '0';
dtr_d <= dtr;
irq_d <= irq;
if tx_head + 1 = tx_tail then
tx_empty <= '0';
else
tx_empty <= '1';
end if;
b_en <= '0';
b_we <= '0';
b_address <= (others => 'X');
b_wdata <= (others => 'X');
-- generation of NMI
if (irq = '1' and irq_d = '0') or (irq = '1' and nmi_counter = 4095) then
nmi <= '1';
nmi_counter <= 0;
elsif slot_tick = '1' then
if nmi_counter = 127 then
nmi <= '0';
end if;
if nmi_counter /= 16383 then
nmi_counter <= nmi_counter + 1;
end if;
end if;
if slot_tick = '1' and rx_rate_expired = '0' then
if rx_rate_cnt = 0 then
rx_rate_expired <= '1';
else
rx_rate_cnt <= rx_rate_cnt - 1;
end if;
end if;
if tx_data_push = '1' and tx_empty = '1' and dtr = '1' then
b_address <= '0' & tx_head;
b_wdata <= tx_data;
b_we <= '1';
b_en <= '1';
tx_head <= tx_head + 1;
elsif rx_data_valid = '0' and rx_head /= rx_tail and b_pending = '0' and rx_rate_expired = '1' and rts = '1' then
rx_rate_expired <= '0';
rx_rate_cnt <= rx_rate & "00011";
b_address <= '1' & rx_tail;
b_en <= '1';
b_pending <= '1';
rx_tail <= rx_tail + 1;
end if;
if (slot_req.io_address(8 downto 2) = slot_base) and (enable = '1') then
if slot_req.io_write='1' then
case slot_req.io_address(1 downto 0) is
when c_addr_data_register =>
tx_data <= slot_req.data;
tx_data_push <= '1';
when c_addr_status_register =>
soft_reset <= '1';
when c_addr_command_register =>
command <= slot_req.data;
when c_addr_control_register =>
control <= slot_req.data;
control_change <= '1';
when others =>
null;
end case;
elsif slot_req.io_read='1' then
case slot_req.io_address(1 downto 0) is
when c_addr_data_register =>
parity_err <= '0';
framing_err <= '0';
overrun_err <= '0';
rx_data_valid <= '0';
when c_addr_status_register =>
dcd_change <= '0';
dsr_change <= '0';
when c_addr_command_register =>
null;
when c_addr_control_register =>
null;
when others =>
null;
end case;
end if;
end if;
io_resp_regs <= c_io_resp_init;
if io_req_regs.write='1' then
io_resp_regs.ack <= '1';
case io_req_regs.address(3 downto 0) is
when c_reg_rx_head =>
rx_head <= unsigned(io_req_regs.data);
when c_reg_tx_tail =>
tx_tail <= unsigned(io_req_regs.data);
when c_reg_enable =>
enable <= io_req_regs.data(0);
rx_irq_en <= io_req_regs.data(1);
tx_irq_en <= io_req_regs.data(2);
ctrl_irq_en <= io_req_regs.data(3);
hs_irq_en <= io_req_regs.data(4);
when c_reg_handsh =>
cts <= io_req_regs.data(0);
dsr_n <= not io_req_regs.data(2);
dcd_n <= not io_req_regs.data(4);
when c_reg_irq_source =>
if io_req_regs.data(3) = '1' then
control_change <= '0';
end if;
if io_req_regs.data(4) = '1' then
dtr_change <= '0';
end if;
when c_reg_slot_base =>
slot_base <= unsigned(io_req_regs.data(6 downto 0));
nmi_selected <= io_req_regs.data(7);
when c_reg_rx_rate =>
rx_rate <= unsigned(io_req_regs.data);
when others =>
null;
end case;
elsif io_req_regs.read='1' then
io_resp_regs.ack <= '1';
case io_req_regs.address(3 downto 0) is
when c_reg_rx_head =>
io_resp_regs.data <= std_logic_vector(rx_head);
when c_reg_rx_tail =>
io_resp_regs.data <= std_logic_vector(rx_tail);
when c_reg_tx_head =>
io_resp_regs.data <= std_logic_vector(tx_head);
when c_reg_tx_tail =>
io_resp_regs.data <= std_logic_vector(tx_tail);
when c_reg_control =>
io_resp_regs.data <= control;
when c_reg_command =>
io_resp_regs.data <= command;
when c_reg_status =>
io_resp_regs.data <= status;
when c_reg_enable =>
io_resp_regs.data(0) <= enable;
io_resp_regs.data(1) <= rx_irq_en;
io_resp_regs.data(2) <= tx_irq_en;
io_resp_regs.data(3) <= ctrl_irq_en;
io_resp_regs.data(4) <= hs_irq_en;
when c_reg_handsh =>
io_resp_regs.data(0) <= cts;
io_resp_regs.data(1) <= rts;
io_resp_regs.data(2) <= not dsr_n;
io_resp_regs.data(3) <= dtr;
io_resp_regs.data(4) <= not dcd_n;
when c_reg_irq_source =>
io_resp_regs.data(1) <= appl_rx_irq;
io_resp_regs.data(2) <= appl_tx_irq;
io_resp_regs.data(3) <= control_change;
io_resp_regs.data(4) <= dtr_change;
-- when c_reg_slot_base =>
-- io_resp_regs.data(6 downto 0) <= std_logic_vector(slot_base);
-- io_resp_regs.data(7) <= nmi_selected;
-- when c_reg_rx_rate =>
-- io_resp_regs.data <= std_logic_vector(rx_rate);
when others =>
null;
end case;
end if;
-- first cycle b_en = 1 and b_pending = 1
-- then b_en = 0 and b_pending is still = 1. In this cycle RAM result is available.
if b_pending = '1' then
if b_en = '0' then
rx_data_valid <= '1';
rx_data <= b_rdata;
b_pending <= '0';
end if;
end if;
dsr_d <= dsr_n;
if (dsr_d /= dsr_n) then
dsr_change <= '1';
end if;
dcd_d <= dcd_n;
if (dcd_d /= dcd_n) then
dcd_change <= '1';
end if;
if (dtr /= dtr_d) then
dtr_change <= '1';
end if;
if reset = '1' then
nmi <= '0';
command <= X"02";
control <= X"00";
rx_head <= X"00";
rx_tail <= X"00";
tx_head <= X"00";
tx_tail <= X"00";
enable <= '0';
b_pending <= '0';
rx_data_valid <= '0';
cts <= '0';
dsr_n <= '1';
dcd_n <= '1';
tx_irq_en <= '0';
rx_irq_en <= '0';
ctrl_irq_en <= '0';
hs_irq_en <= '0';
dsr_change <= '0';
dcd_change <= '0';
dtr_change <= '0';
control_change <= '0';
slot_base <= (others => '0');
rx_rate <= X"82";
end if;
if soft_reset = '1' or c64_reset = '1' then
command(4 downto 0) <= "00010";
end if;
end if;
end process;
-- first we split our I/O bus in max 4 ranges, of 2K each.
i_split: entity work.io_bus_splitter
generic map (
g_range_lo => 11,
g_range_hi => 12,
g_ports => 2 )
port map (
clock => clock,
req => io_req,
resp => io_resp,
reqs(0) => io_req_regs,
reqs(1) => io_req_ram,
resps(0) => io_resp_regs,
resps(1) => io_resp_ram );
process(clock)
begin
if rising_edge(clock) then
io_ram_ack <= io_ram_en;
end if;
end process;
io_ram_en <= io_req_ram.read or io_req_ram.write;
io_resp_ram.data <= X"00" when io_ram_ack='0' else io_ram_rdata;
io_resp_ram.ack <= io_ram_ack;
i_ram: entity work.dpram
generic map (
g_width_bits => 8,
g_depth_bits => 9,
g_read_first_a => false,
g_read_first_b => false,
g_storage => "block" )
port map (
a_clock => clock,
a_address(8) => io_req_ram.address(9), -- intentional mirroring
a_address(7 downto 0) => io_req_ram.address(7 downto 0),
a_rdata => io_ram_rdata,
a_wdata => io_req_ram.data,
a_en => io_ram_en,
a_we => io_req_ram.write,
b_clock => clock,
b_address => b_address,
b_rdata => b_rdata,
b_wdata => b_wdata,
b_en => b_en,
b_we => b_we );
end architecture;
| gpl-3.0 | 35c773739ea2988a9c2cffbf0ee4738d | 0.429806 | 3.759128 | false | false | false | false |
markusC64/1541ultimate2 | fpga/ip/nano_cpu/vhdl_source/nano_cpu_pkg.vhd | 1 | 3,059 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package nano_cpu_pkg is
-- Instruction bit 14..12: alu operation
-- Instruction bit 11: when 1, accu is updated
-- Instruction bit 15: when 0, flags are updated
-- Instruction Set (bit 10...0) are address when needed
-- ALU
constant c_load : std_logic_vector(15 downto 11) := X"0" & '1'; -- load
constant c_or : std_logic_vector(15 downto 11) := X"1" & '1'; -- or
constant c_and : std_logic_vector(15 downto 11) := X"2" & '1'; -- and
constant c_xor : std_logic_vector(15 downto 11) := X"3" & '1'; -- xor
constant c_add : std_logic_vector(15 downto 11) := X"4" & '1'; -- add
constant c_sub : std_logic_vector(15 downto 11) := X"5" & '1'; -- sub
constant c_compare : std_logic_vector(15 downto 11) := X"5" & '0'; -- sub
constant c_addc : std_logic_vector(15 downto 11) := X"6" & '1'; -- addc
constant c_in : std_logic_vector(15 downto 11) := X"7" & '1'; -- ext
-- constant c_shr : std_logic_vector(15 downto 11) := X"7" & '1'; -- shr
-- no update flags
constant c_store : std_logic_vector(15 downto 11) := X"8" & '0'; -- xxx
constant c_load_ind : std_logic_vector(15 downto 11) := X"8" & '1'; -- load
constant c_store_ind: std_logic_vector(15 downto 11) := X"9" & '0'; -- xxx
constant c_out : std_logic_vector(15 downto 11) := X"A" & '0'; -- xxx
-- Specials
constant c_return : std_logic_vector(15 downto 11) := X"B" & '1'; -- xxx
constant c_branch : std_logic_vector(15 downto 14) := "11";
-- Branches (bit 10..0) are address
constant c_br_eq : std_logic_vector(13 downto 11) := "000"; -- zero
constant c_br_neq : std_logic_vector(13 downto 11) := "001"; -- not zero
constant c_br_mi : std_logic_vector(13 downto 11) := "010"; -- negative
constant c_br_pl : std_logic_vector(13 downto 11) := "011"; -- not negative
constant c_br_always: std_logic_vector(13 downto 11) := "100"; -- always (jump)
constant c_br_call : std_logic_vector(13 downto 11) := "101"; -- always (call)
constant c_br_c : std_logic_vector(13 downto 11) := "110"; -- carry
constant c_br_nc : std_logic_vector(13 downto 11) := "111"; -- not carry
constant c_call : std_logic_vector(15 downto 11) := c_branch & c_br_call;
-- ALU operations
constant c_alu_load : std_logic_vector(2 downto 0) := "000";
constant c_alu_or : std_logic_vector(2 downto 0) := "001";
constant c_alu_and : std_logic_vector(2 downto 0) := "010";
constant c_alu_xor : std_logic_vector(2 downto 0) := "011";
constant c_alu_add : std_logic_vector(2 downto 0) := "100";
constant c_alu_sub : std_logic_vector(2 downto 0) := "101";
constant c_alu_addc : std_logic_vector(2 downto 0) := "110";
constant c_alu_ext : std_logic_vector(2 downto 0) := "111";
end;
| gpl-3.0 | 5818326b3768c0c5ea75e1665ac1f3e8 | 0.56489 | 3.10874 | false | false | false | false |
markusC64/1541ultimate2 | fpga/io/audio/generic_mixer.vhd | 1 | 4,667 | --------------------------------------------------------------------------------
-- Entity: generic_mixer
-- Date:2018-08-02
-- Author: gideon
--
-- Description: Audio mixer
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.audio_type_pkg.all;
use work.io_bus_pkg.all;
entity generic_mixer is
generic (
g_num_sources : natural := 8 );
port (
clock : in std_logic;
reset : in std_logic;
start : in std_logic;
sys_clock : in std_logic;
req : in t_io_req;
resp : out t_io_resp;
-- audio
inputs : in t_audio_array(0 to g_num_sources-1);
out_L : out std_logic_vector(23 downto 0);
out_R : out std_logic_vector(23 downto 0)
);
end entity;
architecture arch of generic_mixer is
-- if 6dB per bit, then
-- (0)1.1111111 ~ 2 = +6dB
-- (0)1.0010000 ~ 1.13 = +1dB (0x90)
-- (0)1.0000000 = 1 = 0 dB (0x80)
-- (0)0.1110010 = .89 = -1dB (0x72)
-- (0)0.1000000 = .5 = -6dB (0x40)
-- (0)0.0100000 = .25 = -12dB
-- (0)0.0000001 = = -42dB
-- conclusion: one byte volume control is enough
-- Multiplication is such that 0dB yields the same value
type t_state is (idle, accumulate, collect, collect2, collect3);
signal state : t_state;
signal pointer : natural range 0 to 2*g_num_sources;
signal sys_en : std_logic;
signal sys_en_d : std_logic;
signal sys_rdata: std_logic_vector(7 downto 0);
signal ram_addr : unsigned(7 downto 0);
signal ram_rdata: std_logic_vector(7 downto 0);
signal clear : std_logic;
signal a : signed(17 downto 0);
signal b : signed(8 downto 0);
signal result : signed(31 downto 0);
function clip(inp : signed(31 downto 0)) return std_logic_vector is
variable result : std_logic_vector(23 downto 0);
begin
if inp(31 downto 24) = X"FF" or inp(31 downto 24) = X"00" then
result := std_logic_vector(inp(24 downto 1));
elsif inp(31) = '0' then
result := X"7FFFFF";
else
result := X"800000";
end if;
return result;
end function clip;
begin
b <= '0' & signed(ram_rdata);
ram_addr <= to_unsigned(pointer, 8);
i_ram: entity work.dpram
generic map (
g_width_bits => 8,
g_depth_bits => 8
)
port map(
a_clock => clock,
a_address => ram_addr,
a_rdata => ram_rdata,
a_wdata => X"00",
a_en => '1',
a_we => '0',
b_clock => sys_clock,
b_address => req.address(7 downto 0),
b_rdata => sys_rdata,
b_wdata => req.data,
b_en => sys_en,
b_we => req.write
);
sys_en <= req.write or req.read;
process(sys_clock)
begin
if rising_edge(sys_clock) then
sys_en_d <= sys_en;
resp <= c_io_resp_init;
if sys_en_d = '1' then
resp.data <= sys_rdata;
resp.ack <= '1';
end if;
end if;
end process;
process(clock)
begin
if rising_edge(clock) then
clear <= '0';
a <= inputs(pointer / 2);
case state is
when idle =>
pointer <= 0;
if start = '1' then
clear <= '1';
pointer <= 1;
state <= accumulate;
end if;
when accumulate =>
if pointer = (2*g_num_sources)-1 then
state <= collect;
else
pointer <= pointer + 1;
end if;
when collect =>
state <= collect2;
when collect2 =>
out_L <= clip(result);
state <= collect3;
when collect3 =>
out_R <= clip(result);
state <= idle;
end case;
if reset = '1' then
out_L <= (others => '0');
out_R <= (others => '0');
state <= idle;
end if;
end if;
end process;
i_muladd: entity work.mul_add
port map (
clock => clock,
clear => clear,
a => a,
b => b,
result => result
);
end architecture;
| gpl-3.0 | 8792d8f9c1ead74536f9afb072f06349 | 0.444611 | 3.822277 | false | false | false | false |
fpgaddicted/5bit-shift-register-structural- | anode_fsm.vhd | 1 | 1,869 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:40:27 04/09/2017
-- Design Name:
-- Module Name: anode_fsm - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity anode_fsm is
Port ( clk : in STD_LOGIC;
anode_o : out STD_LOGIC_VECTOR (3 downto 0);
reset : in STD_LOGIC);
end anode_fsm;
architecture Behavioral of anode_fsm is
type control is (an3,an2,an1,an0);
signal next_state :control;
begin
process(clk, next_state)
begin
if (clk' event and clk='1') then
case next_state is
when an3 =>
if reset ='1' then
next_state <=an3;
else
anode_o <= "0111";
next_state <= an2;
end if;
when an2 =>
if reset ='1' then
next_state <=an3;
else
anode_o <= "1011";
next_state <= an1;
end if;
when an1 =>
if reset ='1' then
next_state <=an3;
else
anode_o <= "1101";
next_state <= an0;
end if;
when an0 =>
if reset ='1' then
next_state <= an3;
else
anode_o <= "1110";
next_state <= an3;
end if;
end case;
end if;
end process;
end Behavioral;
| gpl-3.0 | 36a2ba6cfc5bfe6d6854548e6fb654b9 | 0.516854 | 3.506567 | false | false | false | false |
markusC64/1541ultimate2 | fpga/cpu_unit/vhdl_source/dmem_arbiter.vhd | 2 | 4,878 | --------------------------------------------------------------------------------
-- Entity: dm_simple
-- Date: 2014-12-28
-- Author: Gideon
--
-- Description: WB D-bus arbiter. Note that for this arbiter, it is required
-- that the address will remain valid throughout the cycle?
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library mblite;
use mblite.core_Pkg.all;
-- type dmem_in_type is record
-- dat_i : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
-- ena_i : std_logic;
-- end record;
--
-- type dmem_out_type is record
-- dat_o : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
-- adr_o : std_logic_vector(CFG_DMEM_SIZE - 1 downto 0);
-- sel_o : std_logic_vector(3 downto 0);
-- we_o : std_logic;
-- ena_o : std_logic;
-- end record;
entity dmem_arbiter is
port (
clock : in std_logic;
reset : in std_logic;
imem_i : in dmem_out_type;
imem_o : out dmem_in_type;
dmem_i : in dmem_out_type;
dmem_o : out dmem_in_type;
mmem_o : out dmem_out_type;
mmem_i : in dmem_in_type );
end entity;
architecture arch of dmem_arbiter is
type t_state is (idle, data, instr);
signal state, next_state : t_state;
signal delayed_inst, delayed_inst_r : std_logic;
begin
-- when dmem_i.ena_i is '1' (mem controller is capable of processing a request),
-- then we need to decide which of the inputs is going through. At this point,
-- we prioritize port 0 over port 1 (fixed prio). So the forward path will be
-- combinatoric. The return path depends on which port was last forwarded to
-- the memory controller. I.e. regardless of who is presenting the new request,
-- the 'old' request determines to which port the read data belongs.
-- Problem! We only have one ena_i pin per port; which means that once we set
-- ena_i to '1', that the new address presented on adr_o is expected to be
-- processed. This means that we either need to latch the address if we want
-- to serve another port, or serve the same port again. The latter is not feasible
-- when one port has priority over the other.
-- Note that the instruction port doesn't write. This eliminates the need for
-- a multiplexer on the write-data (dat_o). If we require the address to remain
-- valid of the ibus, this will also eliminate the need for a register and
-- multiplexer for the address. The cache will enforce this (non-WB compliant!)
process(state, imem_i, dmem_i, mmem_i, delayed_inst_r)
begin
imem_o.dat_i <= mmem_i.dat_i;
imem_o.ena_i <= '0';
dmem_o.dat_i <= mmem_i.dat_i;
dmem_o.ena_i <= '0';
mmem_o.dat_o <= dmem_i.dat_o;
mmem_o.sel_o <= dmem_i.sel_o;
mmem_o.ena_o <= '0';
mmem_o.we_o <= '0';
mmem_o.adr_o <= (others => 'X');
-- output multiplexer
delayed_inst <= '0';
if mmem_i.ena_i = '1' then -- memory controller can process request
if dmem_i.ena_o = '1' then -- dport wants attention
mmem_o.ena_o <= '1';
mmem_o.we_o <= dmem_i.we_o;
mmem_o.adr_o <= dmem_i.adr_o;
delayed_inst <= imem_i.ena_o;
next_state <= data;
elsif imem_i.ena_o = '1' or delayed_inst_r = '1' then -- iport wants attention
mmem_o.ena_o <= '1';
mmem_o.we_o <= '0';
mmem_o.adr_o <= imem_i.adr_o;
next_state <= instr;
delayed_inst <= '0';
else
next_state <= idle;
delayed_inst <= '0';
end if;
else -- memory controller cannot process request
next_state <= state;
delayed_inst <= delayed_inst_r or imem_i.ena_o;
end if;
-- input multiplexer
case state is
when idle =>
imem_o.ena_i <= '1';
dmem_o.ena_i <= '1';
when data =>
imem_o.ena_i <= '0';
dmem_o.ena_i <= mmem_i.ena_i;
when instr =>
imem_o.ena_i <= mmem_i.ena_i;
dmem_o.ena_i <= '0';
when others =>
null;
end case;
end process;
process(clock)
begin
if rising_edge(clock) then
if reset='1' then
state <= idle;
delayed_inst_r <= '0';
else
state <= next_state;
delayed_inst_r <= delayed_inst;
end if;
end if;
end process;
end arch;
| gpl-3.0 | 0a5c1ce71a7d9a6fa1c8a35f4c02caff | 0.515375 | 3.640299 | false | false | false | false |
markusC64/1541ultimate2 | fpga/1541/vhdl_sim/harness_c1571.vhd | 1 | 4,282 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.io_bus_bfm_pkg.all;
use work.mem_bus_pkg.all;
use work.tl_flat_memory_model_pkg.all;
entity harness_c1571 is
port (
io_irq : out std_logic );
end entity;
architecture harness of harness_c1571 is
signal clock : std_logic := '0';
signal reset : std_logic := '0';
signal io_req : t_io_req;
signal io_resp : t_io_resp;
signal iec_atn : std_logic;
signal iec_atn_o : std_logic;
signal iec_atn_i : std_logic;
signal iec_data : std_logic;
signal iec_data_o : std_logic;
signal iec_data_i : std_logic;
signal iec_clk : std_logic;
signal iec_clk_o : std_logic;
signal iec_clk_i : std_logic;
signal iec_fclk_o : std_logic;
signal iec_fclk_i : std_logic;
signal iec_fclk : std_logic;
signal mem_req : t_mem_req_32;
signal mem_resp : t_mem_resp_32;
signal act_led_n : std_logic;
signal audio_sample : signed(12 downto 0);
signal tick_4MHz : std_logic := '0';
signal tick_16MHz : std_logic := '0';
begin
clock <= not clock after 16 ns;
reset <= '1', '0' after 1000 ns;
process
begin
wait until clock = '1'; tick_16MHz <= '0'; tick_4MHz <= '0';
wait until clock = '1'; tick_16MHz <= '1'; tick_4MHz <= '0';
wait until clock = '1'; tick_16MHz <= '0'; tick_4MHz <= '0';
wait until clock = '1'; tick_16MHz <= '1'; tick_4MHz <= '0';
wait until clock = '1'; tick_16MHz <= '0'; tick_4MHz <= '0';
wait until clock = '1'; tick_16MHz <= '1'; tick_4MHz <= '0';
wait until clock = '1'; tick_16MHz <= '0'; tick_4MHz <= '0';
wait until clock = '1'; tick_16MHz <= '1'; tick_4MHz <= '1';
end process;
i_io_bus_bfm: entity work.io_bus_bfm
generic map (
g_name => "io_bfm" )
port map (
clock => clock,
req => io_req,
resp => io_resp );
i_drive: entity work.c1571_drive
generic map (
g_big_endian => false,
g_audio => false,
g_audio_base => X"0010000",
g_ram_base => X"0000000" )
port map (
clock => clock,
reset => reset,
-- timing
tick_4MHz => tick_4MHz,
tick_16MHz => tick_16MHz,
-- slave port on io bus
io_req => io_req,
io_resp => io_resp,
io_irq => io_irq,
-- master port on memory bus
mem_req => mem_req,
mem_resp => mem_resp,
-- serial bus pins
atn_o => iec_atn_o, -- open drain
atn_i => iec_atn_i,
clk_o => iec_clk_o, -- open drain
clk_i => iec_clk_i,
data_o => iec_data_o, -- open drain
data_i => iec_data_i,
fast_clk_o => iec_fclk_o, -- open drain
fast_clk_i => iec_fclk_i,
-- LED
act_led_n => act_led_n,
-- audio out
audio_sample => audio_sample );
iec_atn <= '0' when iec_atn_o='0' else 'Z';
iec_atn_i <= '0' when iec_atn='0' else '1';
iec_clk <= '0' when iec_clk_o='0' else 'Z';
iec_clk_i <= '0' when iec_clk='0' else '1';
iec_data <= '0' when iec_data_o='0' else 'Z';
iec_data_i <= '0' when iec_data='0' else '1';
iec_fclk <= '0' when iec_fclk_o='0' else 'Z';
iec_fclk_i <= '0' when iec_fclk='0' else '1';
i_memory: entity work.mem_bus_32_slave_bfm
generic map(
g_name => "dram",
g_latency => 2
)
port map(
clock => clock,
req => mem_req,
resp => mem_resp
);
iec_bfm: entity work.iec_bus_bfm
generic map ("iec_bfm")
port map (
iec_clock => iec_clk,
iec_data => iec_data,
iec_atn => iec_atn,
iec_srq => iec_fclk );
end harness;
| gpl-3.0 | 41f43bec9f86a49d0a4258193919fd01 | 0.466137 | 3.253799 | false | false | false | false |
markusC64/1541ultimate2 | fpga/6502n/vhdl_source/data_oper.vhd | 1 | 8,683 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.pkg_6502_decode.all;
-- this module puts the alu, shifter and bit/compare unit together
entity data_oper is
generic (
support_bcd : boolean := true );
port (
inst : in std_logic_vector(7 downto 0);
n_in : in std_logic;
v_in : in std_logic;
z_in : in std_logic;
c_in : in std_logic;
d_in : in std_logic;
i_in : in std_logic;
data_in : in std_logic_vector(7 downto 0);
a_reg : in std_logic_vector(7 downto 0);
x_reg : in std_logic_vector(7 downto 0);
y_reg : in std_logic_vector(7 downto 0);
s_reg : in std_logic_vector(7 downto 0);
alu_sel_o : out std_logic_vector(1 downto 0);
alu_out : out std_logic_vector(7 downto 0);
mem_out : out std_logic_vector(7 downto 0);
mem_c : out std_logic;
mem_n : out std_logic;
mem_z : out std_logic;
impl_out : out std_logic_vector(7 downto 0);
set_a : out std_logic;
set_x : out std_logic;
set_y : out std_logic;
set_s : out std_logic;
flags_imm : out std_logic;
n_out : out std_logic;
v_out : out std_logic;
z_out : out std_logic;
c_out : out std_logic;
d_out : out std_logic;
i_out : out std_logic );
end data_oper;
architecture gideon of data_oper is
signal shift_sel : std_logic_vector(1 downto 0) := "00";
signal shift_din : std_logic_vector(7 downto 0) := X"00";
signal shift_dout: std_logic_vector(7 downto 0) := X"00";
signal alu_sel : std_logic_vector(1 downto 0) := "00";
signal alu_data_a: std_logic_vector(7 downto 0) := X"00";
signal alu_out_i : std_logic_vector(7 downto 0) := X"00";
signal row0_n : std_logic;
signal row0_v : std_logic;
signal row0_z : std_logic;
signal row0_c : std_logic;
signal shft_n : std_logic;
signal shft_z : std_logic;
signal shft_c : std_logic;
signal alu_n : std_logic;
signal alu_v : std_logic;
signal alu_z : std_logic;
signal alu_c : std_logic;
signal impl_n : std_logic;
signal impl_z : std_logic;
signal impl_c : std_logic;
signal impl_v : std_logic;
signal n, z : std_logic;
signal shift_en : std_logic;
signal alu_en : std_logic;
signal full_carry : std_logic := '0';
signal half_carry : std_logic := '0';
signal bypass_shift : std_logic;
signal flag_select : t_result_select;
begin
shift_en <= '1' when is_shift(inst) else '0';
alu_en <= '1' when is_alu(inst) else '0';
bypass_shift <= do_bypass_shift(inst);
flag_select <= flags_from(inst);
shift_sel <= shifter_in_select(inst);
with shift_sel select shift_din <=
data_in when "01",
a_reg when "10",
data_in and a_reg when "11",
data_in and (a_reg or X"EE") when others; -- for LAX #$
alu_sel(0) <= '1' when x_to_alu(inst) else '0';
alu_sel(1) <= shift_sel(0) and shift_sel(1);
with alu_sel select alu_data_a <=
a_reg and x_reg when "01",
a_reg and data_in when "10",
a_reg and x_reg and data_in when "11",
a_reg when others;
alu_sel_o <= alu_sel;
i_row0: entity work.bit_cpx_cpy
port map (
operation => inst(7 downto 5),
n_in => n_in,
v_in => v_in,
z_in => z_in,
c_in => c_in,
data_in => data_in,
a_reg => a_reg,
x_reg => x_reg,
y_reg => y_reg,
n_out => row0_n,
v_out => row0_v,
z_out => row0_z,
c_out => row0_c );
i_shft: entity work.shifter
port map (
operation => inst(7 downto 5),
bypass => bypass_shift,
c_in => c_in,
n_in => n_in,
z_in => z_in,
data_in => shift_din,
c_out => shft_c,
n_out => shft_n,
z_out => shft_z,
data_out => shift_dout );
i_alu: entity work.alu
generic map (
support_bcd => support_bcd )
port map (
operation => inst(7 downto 5),
n_in => n_in,
v_in => v_in,
z_in => z_in,
c_in => c_in,
d_in => d_in,
data_a => alu_data_a,
data_b => shift_din,
n_out => alu_n,
v_out => alu_v,
z_out => alu_z,
c_out => alu_c,
half_carry => half_carry,
full_carry => full_carry,
data_out => alu_out_i );
mem_out <= shift_dout;
p_bcd_fixer: process(shift_dout, alu_out_i, d_in, shift_en, alu_en, inst, full_carry, half_carry)
variable sum_l : unsigned(3 downto 0);
variable sum_h : unsigned(3 downto 0);
begin
if shift_en = '1' then
sum_h := unsigned(shift_dout(7 downto 4));
sum_l := unsigned(shift_dout(3 downto 0));
else
sum_h := unsigned(alu_out_i(7 downto 4));
sum_l := unsigned(alu_out_i(3 downto 0));
end if;
n <= sum_h(3);
if sum_h = "0000" and sum_l = "0000" then
z <= '1';
else
z <= '0';
end if;
if d_in='1' and support_bcd then
if alu_en = '1' then
if inst(7 downto 5)="011" then -- ADC
if half_carry = '1' then
sum_l := sum_l + 6;
end if;
if full_carry = '1' then
sum_h := sum_h + 6;
end if;
elsif inst(7 downto 5)="111" then -- SBC
if half_carry = '0' then
sum_l := sum_l - 6;
end if;
if full_carry = '0' then
sum_h := sum_h - 6;
end if;
end if;
end if;
end if;
alu_out <= std_logic_vector(sum_h) & std_logic_vector(sum_l);
end process;
i_impl: entity work.implied
port map (
inst => inst,
c_in => c_in,
i_in => i_in,
n_in => n_in,
z_in => z_in,
d_in => d_in,
v_in => v_in,
reg_a => a_reg,
reg_x => x_reg,
reg_y => y_reg,
reg_s => s_reg,
data_in => data_in,
flags_imm => flags_imm,
i_out => i_out,
d_out => d_out,
c_out => impl_c,
n_out => impl_n,
z_out => impl_z,
v_out => impl_v,
set_a => set_a,
set_x => set_x,
set_y => set_y,
set_s => set_s,
data_out => impl_out );
process(flag_select,
n_in, v_in, z_in, c_in,
impl_n, impl_v, impl_z, impl_c,
row0_n, row0_v, row0_z, row0_c,
alu_n, alu_v, alu_z, alu_c,
shft_n, shft_z, shft_c, n, z )
begin
case flag_select is
when alu =>
n_out <= n;
v_out <= alu_v;
z_out <= z;
c_out <= alu_c;
when impl =>
n_out <= impl_n;
v_out <= impl_v;
z_out <= impl_z;
c_out <= impl_c;
when row0 =>
n_out <= row0_n;
v_out <= row0_v;
z_out <= row0_z;
c_out <= row0_c;
when shift =>
n_out <= n;
v_out <= v_in;
z_out <= z;
c_out <= shft_c;
when others =>
n_out <= n_in;
v_out <= v_in;
z_out <= z_in;
c_out <= c_in;
end case;
end process;
mem_c <= shft_c;
mem_z <= shft_z;
mem_n <= shft_n;
end gideon;
| gpl-3.0 | be5d34c6a0b5157f92d3dd72b1c2d725 | 0.413452 | 3.368115 | false | false | false | false |
armandas/Plong | sounds.vhd | 1 | 1,084 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sounds is
port(
clk, not_reset: in std_logic;
enable: in std_logic;
period: in std_logic_vector(18 downto 0);
volume: in std_logic_vector(2 downto 0);
speaker: out std_logic
);
end sounds;
architecture generator of sounds is
signal counter, counter_next: std_logic_vector(18 downto 0);
signal pulse_width: std_logic_vector(18 downto 0);
begin
process(clk, not_reset)
begin
if not_reset = '0' then
counter <= (others => '0');
elsif clk'event and clk = '0' then
counter <= counter_next;
end if;
end process;
-- duty cycle:
-- max: 50% (18 downto 1)
-- min: 0.78% (18 downto 7)
-- off when given 0 (18 downto 0)!
pulse_width <= period(18 downto conv_integer(volume));
counter_next <= (others => '0') when counter = period else
counter + 1;
speaker <= '1' when (enable = '1' and counter < pulse_width) else '0';
end generator; | bsd-2-clause | 7b40cdabb65a6fb6315a668a6ac10673 | 0.587638 | 3.530945 | false | false | false | false |
markusC64/1541ultimate2 | target/fpga/u2p_memtest/memphy.vhd | 1 | 34,894 | -- megafunction wizard: %ALTMEMPHY%
-- GENERATION: XML
-- ============================================================
-- Megafunction Name(s):
-- memphy_alt_mem_phy
-- ============================================================
-- Generated by altmemphy 15.1 [Altera, IP Toolbench 1.3.0 Build 185]
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-- ************************************************************
-- Copyright (C) 1991-2016 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera. Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner. Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors. No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.
library IEEE;
use IEEE.std_logic_1164.all;
ENTITY memphy IS
PORT (
pll_ref_clk : IN STD_LOGIC;
global_reset_n : IN STD_LOGIC;
soft_reset_n : IN STD_LOGIC;
ctl_dqs_burst : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
ctl_wdata_valid : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
ctl_wdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ctl_dm : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
ctl_addr : IN STD_LOGIC_VECTOR (27 DOWNTO 0);
ctl_ba : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
ctl_cas_n : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
ctl_cke : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
ctl_cs_n : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
ctl_odt : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
ctl_ras_n : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
ctl_we_n : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
ctl_rst_n : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
ctl_mem_clk_disable : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
ctl_doing_rd : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
ctl_cal_req : IN STD_LOGIC;
ctl_cal_byte_lane_sel_n : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dbg_clk : IN STD_LOGIC;
dbg_reset_n : IN STD_LOGIC;
dbg_addr : IN STD_LOGIC_VECTOR (12 DOWNTO 0);
dbg_wr : IN STD_LOGIC;
dbg_rd : IN STD_LOGIC;
dbg_cs : IN STD_LOGIC;
dbg_wr_data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
reset_request_n : OUT STD_LOGIC;
ctl_clk : OUT STD_LOGIC;
ctl_reset_n : OUT STD_LOGIC;
ctl_wlat : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
ctl_rdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
ctl_rdata_valid : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
ctl_rlat : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
ctl_cal_success : OUT STD_LOGIC;
ctl_cal_fail : OUT STD_LOGIC;
ctl_cal_warning : OUT STD_LOGIC;
mem_addr : OUT STD_LOGIC_VECTOR (13 DOWNTO 0);
mem_ba : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
mem_cas_n : OUT STD_LOGIC;
mem_cke : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
mem_cs_n : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
mem_dm : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
mem_odt : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
mem_ras_n : OUT STD_LOGIC;
mem_we_n : OUT STD_LOGIC;
mem_reset_n : OUT STD_LOGIC;
dbg_rd_data : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
dbg_waitrequest : OUT STD_LOGIC;
aux_half_rate_clk : OUT STD_LOGIC;
aux_full_rate_clk : OUT STD_LOGIC;
mem_clk : INOUT STD_LOGIC_VECTOR (0 DOWNTO 0);
mem_clk_n : INOUT STD_LOGIC_VECTOR (0 DOWNTO 0);
mem_dq : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0);
mem_dqs : INOUT STD_LOGIC_VECTOR (0 DOWNTO 0);
mem_dqs_n : INOUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END memphy;
ARCHITECTURE SYN OF memphy IS
COMPONENT memphy_alt_mem_phy
GENERIC (
FAMILY : STRING;
MEM_IF_MEMTYPE : STRING;
DLL_DELAY_BUFFER_MODE : STRING;
DLL_DELAY_CHAIN_LENGTH : NATURAL;
DQS_DELAY_CTL_WIDTH : NATURAL;
DQS_OUT_MODE : STRING;
DQS_PHASE : NATURAL;
DQS_PHASE_SETTING : NATURAL;
DWIDTH_RATIO : NATURAL;
MEM_IF_DWIDTH : NATURAL;
MEM_IF_ADDR_WIDTH : NATURAL;
MEM_IF_BANKADDR_WIDTH : NATURAL;
MEM_IF_CS_WIDTH : NATURAL;
MEM_IF_CS_PER_RANK : NATURAL;
MEM_IF_DM_WIDTH : NATURAL;
MEM_IF_DM_PINS_EN : NATURAL;
MEM_IF_DQ_PER_DQS : NATURAL;
MEM_IF_DQS_WIDTH : NATURAL;
MEM_IF_OCT_EN : NATURAL;
MEM_IF_CLK_PAIR_COUNT : NATURAL;
MEM_IF_CLK_PS : NATURAL;
MEM_IF_CLK_PS_STR : STRING;
MEM_IF_MR_0 : NATURAL;
MEM_IF_MR_1 : NATURAL;
MEM_IF_MR_2 : NATURAL;
MEM_IF_MR_3 : NATURAL;
PLL_STEPS_PER_CYCLE : NATURAL;
SCAN_CLK_DIVIDE_BY : NATURAL;
MEM_IF_DQSN_EN : NATURAL;
DLL_EXPORT_IMPORT : STRING;
MEM_IF_ADDR_CMD_PHASE : NATURAL;
RANK_HAS_ADDR_SWAP : NATURAL
);
PORT (
pll_ref_clk : IN STD_LOGIC;
global_reset_n : IN STD_LOGIC;
soft_reset_n : IN STD_LOGIC;
ctl_dqs_burst : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
ctl_wdata_valid : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
ctl_wdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ctl_dm : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
ctl_addr : IN STD_LOGIC_VECTOR (27 DOWNTO 0);
ctl_ba : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
ctl_cas_n : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
ctl_cke : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
ctl_cs_n : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
ctl_odt : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
ctl_ras_n : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
ctl_we_n : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
ctl_rst_n : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
ctl_mem_clk_disable : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
ctl_doing_rd : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
ctl_cal_req : IN STD_LOGIC;
ctl_cal_byte_lane_sel_n : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dbg_clk : IN STD_LOGIC;
dbg_reset_n : IN STD_LOGIC;
dbg_addr : IN STD_LOGIC_VECTOR (12 DOWNTO 0);
dbg_wr : IN STD_LOGIC;
dbg_rd : IN STD_LOGIC;
dbg_cs : IN STD_LOGIC;
dbg_wr_data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
reset_request_n : OUT STD_LOGIC;
ctl_clk : OUT STD_LOGIC;
ctl_reset_n : OUT STD_LOGIC;
ctl_wlat : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
ctl_rdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
ctl_rdata_valid : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
ctl_rlat : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
ctl_cal_success : OUT STD_LOGIC;
ctl_cal_fail : OUT STD_LOGIC;
ctl_cal_warning : OUT STD_LOGIC;
mem_addr : OUT STD_LOGIC_VECTOR (13 DOWNTO 0);
mem_ba : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
mem_cas_n : OUT STD_LOGIC;
mem_cke : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
mem_cs_n : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
mem_dm : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
mem_odt : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
mem_ras_n : OUT STD_LOGIC;
mem_we_n : OUT STD_LOGIC;
mem_reset_n : OUT STD_LOGIC;
dbg_rd_data : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
dbg_waitrequest : OUT STD_LOGIC;
aux_half_rate_clk : OUT STD_LOGIC;
aux_full_rate_clk : OUT STD_LOGIC;
mem_clk : INOUT STD_LOGIC_VECTOR (0 DOWNTO 0);
mem_clk_n : INOUT STD_LOGIC_VECTOR (0 DOWNTO 0);
mem_dq : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0);
mem_dqs : INOUT STD_LOGIC_VECTOR (0 DOWNTO 0);
mem_dqs_n : INOUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END COMPONENT;
BEGIN
memphy_alt_mem_phy_inst : memphy_alt_mem_phy
GENERIC MAP (
FAMILY => "Cyclone IV E",
MEM_IF_MEMTYPE => "DDR2",
DLL_DELAY_BUFFER_MODE => "LOW",
DLL_DELAY_CHAIN_LENGTH => 12,
DQS_DELAY_CTL_WIDTH => 6,
DQS_OUT_MODE => "DELAY_CHAIN2",
DQS_PHASE => 6000,
DQS_PHASE_SETTING => 2,
DWIDTH_RATIO => 4,
MEM_IF_DWIDTH => 8,
MEM_IF_ADDR_WIDTH => 14,
MEM_IF_BANKADDR_WIDTH => 2,
MEM_IF_CS_WIDTH => 1,
MEM_IF_CS_PER_RANK => 1,
MEM_IF_DM_WIDTH => 1,
MEM_IF_DM_PINS_EN => 1,
MEM_IF_DQ_PER_DQS => 8,
MEM_IF_DQS_WIDTH => 1,
MEM_IF_OCT_EN => 0,
MEM_IF_CLK_PAIR_COUNT => 1,
MEM_IF_CLK_PS => 7692,
MEM_IF_CLK_PS_STR => "7692 ps",
MEM_IF_MR_0 => 578,
MEM_IF_MR_1 => 1024,
MEM_IF_MR_2 => 0,
MEM_IF_MR_3 => 0,
PLL_STEPS_PER_CYCLE => 80,
SCAN_CLK_DIVIDE_BY => 2,
MEM_IF_DQSN_EN => 0,
DLL_EXPORT_IMPORT => "EXPORT",
MEM_IF_ADDR_CMD_PHASE => 90,
RANK_HAS_ADDR_SWAP => 0
)
PORT MAP (
pll_ref_clk => pll_ref_clk,
global_reset_n => global_reset_n,
soft_reset_n => soft_reset_n,
reset_request_n => reset_request_n,
ctl_clk => ctl_clk,
ctl_reset_n => ctl_reset_n,
ctl_dqs_burst => ctl_dqs_burst,
ctl_wdata_valid => ctl_wdata_valid,
ctl_wdata => ctl_wdata,
ctl_dm => ctl_dm,
ctl_wlat => ctl_wlat,
ctl_addr => ctl_addr,
ctl_ba => ctl_ba,
ctl_cas_n => ctl_cas_n,
ctl_cke => ctl_cke,
ctl_cs_n => ctl_cs_n,
ctl_odt => ctl_odt,
ctl_ras_n => ctl_ras_n,
ctl_we_n => ctl_we_n,
ctl_rst_n => ctl_rst_n,
ctl_mem_clk_disable => ctl_mem_clk_disable,
ctl_doing_rd => ctl_doing_rd,
ctl_rdata => ctl_rdata,
ctl_rdata_valid => ctl_rdata_valid,
ctl_rlat => ctl_rlat,
ctl_cal_req => ctl_cal_req,
ctl_cal_byte_lane_sel_n => ctl_cal_byte_lane_sel_n,
ctl_cal_success => ctl_cal_success,
ctl_cal_fail => ctl_cal_fail,
ctl_cal_warning => ctl_cal_warning,
mem_addr => mem_addr,
mem_ba => mem_ba,
mem_cas_n => mem_cas_n,
mem_cke => mem_cke,
mem_cs_n => mem_cs_n,
mem_dm => mem_dm,
mem_odt => mem_odt,
mem_ras_n => mem_ras_n,
mem_we_n => mem_we_n,
mem_reset_n => mem_reset_n,
mem_clk => mem_clk,
mem_clk_n => mem_clk_n,
mem_dq => mem_dq,
mem_dqs => mem_dqs,
mem_dqs_n => mem_dqs_n,
dbg_clk => dbg_clk,
dbg_reset_n => dbg_reset_n,
dbg_addr => dbg_addr,
dbg_wr => dbg_wr,
dbg_rd => dbg_rd,
dbg_cs => dbg_cs,
dbg_wr_data => dbg_wr_data,
dbg_rd_data => dbg_rd_data,
dbg_waitrequest => dbg_waitrequest,
aux_half_rate_clk => aux_half_rate_clk,
aux_full_rate_clk => aux_full_rate_clk
);
END SYN;
-- =========================================================
-- altmemphy Wizard Data
-- ===============================
-- DO NOT EDIT FOLLOWING DATA
-- @Altera, IP Toolbench@
-- Warning: If you modify this section, altmemphy Wizard may not be able to reproduce your chosen configuration.
--
-- Retrieval info: <?xml version="1.0"?>
-- Retrieval info: <MEGACORE title="ALTMEMPHY" version="15.1" build="185" iptb_version="1.3.0 Build 185" format_version="120" >
-- Retrieval info: <NETLIST_SECTION class="altera.ipbu.flowbase.netlist.model.DDRPHYMVCModel" active_core="memphy_alt_mem_phy" >
-- Retrieval info: <STATIC_SECTION>
-- Retrieval info: <PRIVATES>
-- Retrieval info: <NAMESPACE name = "parameterization">
-- Retrieval info: <PRIVATE name = "debug_en" value="false" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "pipeline_commands" value="false" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "use_generated_memory_model" value="true" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "export_debug_port" value="false" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "local_if_clk_mhz_label" value="65.0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "pll_ref_clk_ps_label" value="(20000 ps)" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "pll_ref_clk_mhz" value="50.0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_if_clk_mhz" value="130.0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "local_if_drate" value="Half" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "project_family" value="Cyclone IV E" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "enable_v72_rsu" value="false" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_if_clk_ps_label" value="(7692 ps)" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_if_memtype" value="DDR2 SDRAM" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "new_variant" value="false" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "family" value="Cyclone IV E" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "quartus_project_exists" value="true" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "dedicated_memory_clk_phase" value="0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "speed_grade" value="8" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "dedicated_memory_clk_phase_label" value="Dedicated memory clock phase:" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "avalon_burst_length" value="1" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_if_pchaddr_bit" value="10" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_if_dm_pins_en" value="Yes" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_if_dwidth" value="8" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_fmax" value="266.667" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "pre_latency_label" value="Fix read latency at:" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "register_control_word_9" value="0000" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "register_control_word_8" value="0000" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "register_control_word_7" value="0000" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_dyn_deskew_en" value="false" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "chip_or_dimm" value="Discrete Device" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_if_bankaddr_width" value="2" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_if_dq_per_dqs" value="8" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "vendor" value="JEDEC" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_if_preset" value="JEDEC DDR2-533 512Mb x8" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "fast_simulation_en" value="FAST" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_if_cs_width" value="1" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_if_cs_per_dimm" value="1" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_if_clk_pair_count" value="1" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "post_latency_label" value="cycles (0 cycles=minimum latency, non-deterministic)" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "register_control_word_13" value="0000" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "local_if_dwidth_label" value="32" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "register_control_word_12" value="0000" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "register_control_word_15" value="0000" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "register_control_word_14" value="0000" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_if_coladdr_width" value="10" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "register_control_word_11" value="0000" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "WIDTH_RATIO" value="4" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "register_control_word_10" value="0000" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_if_cs_per_rank" value="1" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "dedicated_memory_clk_en" value="false" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_if_rowaddr_width" value="14" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "register_control_word_2" value="0000" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "register_control_word_1" value="0000" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "register_control_word_0" value="0000" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "register_control_word_size" value="4" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "register_control_word_6" value="0000" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "register_control_word_5" value="0000" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_if_preset_rlat" value="0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "register_control_word_4" value="0000" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mirror_addressing" value="0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "register_control_word_3" value="0000" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_if_tras_ns" value="45.0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_if_twr_ns" value="15.0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_tdss_ck" value="0.2" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_if_trefi_us" value="7.0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_tdha_ps" value="350" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_tdqsck_ps" value="450" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_if_trfc_ns" value="105.0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_if_trp_ns" value="15.0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_tdqss_ck" value="0.25" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_tfaw_ns" value="37.5" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_tdqsq_ps" value="300" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_tdsh_ck" value="0.2" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_tqhs_ps" value="400" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_if_tinit_us" value="200.0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_tqh_ck" value="0.36" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_trrd_ns" value="7.5" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_tiha_ps" value="500" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_tac_ps" value="500" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_tisa_ps" value="500" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_if_tmrd_ns" value="7.0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_tdsa_ps" value="350" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_if_twtr_ck" value="2" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_trtp_ns" value="7.5" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_if_trcd_ns" value="15.0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_drv_str" value="Normal" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_tcl_50_fmax" value="266.667" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_tcl_25_fmax" value="166.667" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "pll_reconfig_ports_en" value="false" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_if_dqsn_en" value="false" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_btype" value="Sequential" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mp_DSS_percent" value="0.6" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "ac_phase" value="90" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mp_QH_percent" value="0.5" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_dll_en" value="Yes" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mp_IS_percent" value="0.7" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mp_DQSCK_percent" value="0.5" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mp_DSH_percent" value="0.6" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_odt" value="Disabled" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "enable_mp_calibration" value="true" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mp_DS_percent" value="0.6" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_tcl_30_fmax" value="200.0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mp_DH_percent" value="0.5" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mp_DQSQ_percent" value="0.65" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_tcl_40_fmax" value="266.667" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mp_IH_percent" value="0.6" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_tcl_15_fmax" value="533.0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_tcl_60_fmax" value="266.667" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_if_oct_en" value="false" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "input_period" value="0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mp_WLS_percent" value="0.7" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_bl" value="4" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mp_WLH_percent" value="0.6" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "export_bank_info" value="false" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_tcl_20_fmax" value="133.333" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mp_DQSS_percent" value="0.5" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "dll_external" value="false" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mp_QHS_percent" value="0.5" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_tcl" value="4.0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "ac_clk_select" value="90" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "ctl_powerdn_en" value="false" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "ctl_lookahead_depth" value="4" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "ctl_autopch_en" value="false" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "ctl_dynamic_bank_allocation" value="false" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "multicast_wr_en" value="false" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "ctl_hrb_en" value="false" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "controller_type" value="ngv110_ctl" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "ctl_dynamic_bank_num" value="4" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "ctl_ecc_en" value="false" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "phy_if_type_afi" value="true" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "qsys_mode" value="false" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "shared_sys_clk_source" value="XX" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "auto_powerdn_cycles" value="0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "user_refresh_en" value="false" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "ctl_self_refresh_en" value="false" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "ctl_auto_correct_en" value="false" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "local_if_type_avalon" value="true" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "burst_merge_en" value="false" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "cfg_data_reordering_type" value="INTER_BANK" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "tool_context" value="STANDALONE" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_addr_mapping" value="CHIP_ROW_BANK_COL" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "cfg_starve_limit" value="10" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "auto_powerdn_en" value="false" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "ctl_latency" value="0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "ref_clk_source" value="XX" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "clk_source_sharing_en" value="false" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "cfg_reorder_data" value="true" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "max_local_size" value="4" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "csr_en" value="false" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_tsc_ps" value="250" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_tsa_ps" value="250" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_if_pseudo_x36" value="Disabled" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_tcqh_ps" value="880" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_tcqhqx_ps" value="250" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_tsd_ps" value="250" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_tha_ps" value="250" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_thc_ps" value="250" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_tcqhqv_ps" value="250" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_thd_ps" value="250" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_addr_cmd_bus_count" value="1" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_tcqhcqnh_ps" value="880" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_io_std" value="1.5-V HSTL CLASS I" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_rtt_nom" value="ODT Disabled" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_srtr" value="Normal" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_mpr_loc" value="Predefined Pattern" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_rtt_wr" value="Dynamic ODT off" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "dss_tinit_rst_us" value="200.0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_asrm" value="Manual SR Reference (SRT)" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_tcl_80_fmax" value="400.0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_mpr_oper" value="Predefined Pattern" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_dll_pch" value="Fast Exit" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_tcl_90_fmax" value="400.0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_atcl" value="Disabled" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_wtcl" value="5.0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_drv_impedance" value="RZQ/7" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_tcl_70_fmax" value="400.0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_tcl_100_fmax" value="400.0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_pasr" value="Full Array" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "t_DS_calculated" value="0.350" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "dq_slew_rate" value="1.0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "board_minCK_DQS_skew" value="-0.01" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "t_DS" value="0.35" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "board_maxCK_DQS_skew" value="0.01" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "num_slots_or_devices" value="1" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "board_inter_DQS_group_skew" value="0.02" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "addr_cmd_slew_rate" value="1.0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "t_IS_calculated" value="0.500" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "t_DH" value="0.35" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "t_IH_calculated" value="0.500" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "board_tpd_inter_DIMM" value="0.05" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "board_skew_ps" value="20" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "dqs_dqsn_slew_rate" value="2.0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "t_IS" value="0.5" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "board_intra_DQS_group_skew" value="0.02" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "t_DH_calculated" value="0.350" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "isi_addresscmd_hold" value="0.0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "isi_addresscmd_setup" value="0.0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "ck_ckn_slew_rate" value="2.0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "restore_default_toggle" value="true" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "board_settings_valid" value="true" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "isi_DQS" value="0.0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "t_IH" value="0.5" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "board_addresscmd_CK_skew" value="0.0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "isi_DQ" value="0.0" type="STRING" enable="1" />
-- Retrieval info: </NAMESPACE>
-- Retrieval info: <NAMESPACE name = "simgen">
-- Retrieval info: <PRIVATE name = "use_alt_top" value="1" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "alt_top" value="memphy_alt_mem_phy_seq_wrapper" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "command" value=" --simgen_arbitrary_blackbox=+memphy_alt_mem_phy_seq --ini=simgen_tri_bus_opt=on" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "parameter" value="SIMGEN_INITIALIZATION_FILE=/home/gideon/proj/ultimate/target/fpga/u2p_memtest/memphy_simgen_init.txt" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "family" value="Cyclone IV E" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "filename" value="memphy_alt_mem_phy_seq_wrapper.vho" type="STRING" enable="1" />
-- Retrieval info: </NAMESPACE>
-- Retrieval info: <NAMESPACE name = "simgen2">
-- Retrieval info: <PRIVATE name = "family" value="Cyclone IV E" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "command" value="--simgen_arbitrary_blackbox=+memphy_alt_mem_phy_seq_wrapper;+memphy_alt_mem_phy_reconfig;+memphy_alt_mem_phy_pll;+memphy_alt_mem_phy_delay --ini=simgen_tri_bus_opt=on" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "parameter" value="SIMGEN_INITIALIZATION_FILE=/home/gideon/proj/ultimate/target/fpga/u2p_memtest/memphy_simgen_init.txt" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "filename" value="memphy.vho" type="STRING" enable="1" />
-- Retrieval info: </NAMESPACE>
-- Retrieval info: <NAMESPACE name = "simgen_enable">
-- Retrieval info: <PRIVATE name = "language" value="vhdl" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "enabled" value="0" type="STRING" enable="1" />
-- Retrieval info: </NAMESPACE>
-- Retrieval info: <NAMESPACE name = "qip">
-- Retrieval info: <PRIVATE name = "gx_libs" value="1" type="STRING" enable="1" />
-- Retrieval info: </NAMESPACE>
-- Retrieval info: <NAMESPACE name = "greybox">
-- Retrieval info: <PRIVATE name = "filename" value="memphy_syn.v" type="STRING" enable="1" />
-- Retrieval info: </NAMESPACE>
-- Retrieval info: <NAMESPACE name = "serializer"/>
-- Retrieval info: <NAMESPACE name = "quartus_settings">
-- Retrieval info: <PRIVATE name = "DEVICE" value="EP4CE22F17C8" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "FAMILY" value="Cyclone IV E" type="STRING" enable="1" />
-- Retrieval info: </NAMESPACE>
-- Retrieval info: </PRIVATES>
-- Retrieval info: <FILES/>
-- Retrieval info: <PORTS/>
-- Retrieval info: <LIBRARIES/>
-- Retrieval info: </STATIC_SECTION>
-- Retrieval info: </NETLIST_SECTION>
-- Retrieval info: </MEGACORE>
-- =========================================================
| gpl-3.0 | cfa99e20c25d6f983f6b9da785adcad5 | 0.626956 | 2.901547 | false | false | false | false |
markusC64/1541ultimate2 | fpga/6502n/vhdl_source/implied.vhd | 1 | 7,066 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.pkg_6502_decode.all;
entity implied is
port (
inst : in std_logic_vector(7 downto 0);
c_in : in std_logic;
i_in : in std_logic;
n_in : in std_logic;
z_in : in std_logic;
d_in : in std_logic;
v_in : in std_logic;
reg_a : in std_logic_vector(7 downto 0);
reg_x : in std_logic_vector(7 downto 0);
reg_y : in std_logic_vector(7 downto 0);
reg_s : in std_logic_vector(7 downto 0);
data_in : in std_logic_vector(7 downto 0);
c_out : out std_logic;
i_out : out std_logic;
n_out : out std_logic;
z_out : out std_logic;
d_out : out std_logic;
v_out : out std_logic;
flags_imm : out std_logic;
set_a : out std_logic;
set_x : out std_logic;
set_y : out std_logic;
set_s : out std_logic;
data_out : out std_logic_vector(7 downto 0));
end implied;
architecture gideon of implied is
type t_int4_array is array(natural range <>) of integer range 0 to 4;
-- ROMS for the upper (negative) implied instructions
constant reg_sel_rom : t_int4_array(0 to 15) := ( 2,0,2,1,1,0,1,1,2,0,2,1,1,3,1,1 ); -- 0=A, 1=X, 2=Y, 3=S
-- DTIITTDNTCCSTTNN
-- EANNXAEOYLLEXSOO
-- YYYXAXXPAVDDSXPP
--
-- 8ACE8ACE9BDF9BDF
-- 8888AAAA8888AAAA
--
-- YAYXXAXXYAYXXSXX
constant decr_rom : std_logic_vector(0 to 15) := "1000001000000000";
constant incr_rom : std_logic_vector(0 to 15) := "0011000000000000";
constant nz_flags : std_logic_vector(0 to 15) := "1111111010000100";
constant v_flag : std_logic_vector(0 to 15) := "0000000001000000";
constant d_flag : std_logic_vector(0 to 15) := "0000000000110000";
constant set_a_rom : std_logic_vector(0 to 15) := "0000100010000000";
constant set_x_rom : std_logic_vector(0 to 15) := "0001011000000100";
constant set_y_rom : std_logic_vector(0 to 15) := "1110000000000000";
constant set_s_rom : std_logic_vector(0 to 15) := "0000000000001000";
-- ROMS for the lower (positive) implied instructions
-- PPPPARLRCSCSNNNN
-- HLHLSOSOLELEOOOO
-- PPAALLRRCCIIPPPP
--
-- 0246024613571357
-- 8888AAAA8888AAAA
constant c_flag : std_logic_vector(0 to 15) := "0000000011000000";
constant i_flag : std_logic_vector(0 to 15) := "0000000000110000";
constant set_a_low : std_logic_vector(0 to 15) := "0001000000000000";
signal selected_reg : std_logic_vector(7 downto 0) := X"00";
signal operation : integer range 0 to 15;
signal reg_sel : integer range 0 to 3;
signal result : std_logic_vector(7 downto 0) := X"00";
signal add : unsigned(7 downto 0) := X"00";
signal carry : unsigned(0 downto 0) := "0";
signal zero : std_logic := '0';
signal do_nz : std_logic := '0';
signal v_hi : std_logic;
signal d_hi : std_logic;
signal c_lo : std_logic;
signal i_lo : std_logic;
signal enable : std_logic;
signal las, ane, shy : std_logic;
signal inc_dec_copy_result : std_logic_vector(7 downto 0);
begin
enable <= '1' when is_implied(inst) else '0';
operation <= to_integer(unsigned(inst(4) & inst(1) & inst(6 downto 5)));
-- Note, for BB, the operation will be: 1101 => 13, and corresponds to TSX
-- 76543210
-- 10111011
-- Note, for 8B, the operation will be: 0100 => 4, and corresponds to TXA (set_a is already set)
-- 76543210
-- 10001011
-- Required operation: A = (A | $EF) & X & Imm
-- 9B
-- 76543210
-- 10011011
-- 1100 => 12 set S is set, which is good. (If only IS_IMPL was set for this instruction ;)
--
reg_sel <= reg_sel_rom(operation);
with reg_sel select selected_reg <=
reg_a when 0,
reg_x when 1,
reg_y when 2,
reg_s when others;
add <= (others => decr_rom(operation));
carry(0) <= incr_rom(operation);
inc_dec_copy_result <= std_logic_vector(unsigned(selected_reg) + add + carry);
-- This is a TWEAK.. should not happen like this
las <= '1' when (inst = X"BB") else '0';
ane <= '1' when (inst = X"8B") else '0';
shy <= '1' when (inst = X"9B") else '0';
result <= (reg_a and reg_x) when shy = '1' else -- Tweakkkk
(reg_a or X"EF") and reg_x and data_in when ane = '1' else -- Tweakkkk!
(data_in and reg_s) when las = '1' else
inc_dec_copy_result when inst(7)='1' else
data_in;
zero <= '1' when result = X"00" else '0';
data_out <= result;
do_nz <= ((nz_flags(operation) and inst(7)) or (set_a_low(operation) and not inst(7)));
v_hi <= '0' when v_flag(operation)='1' else v_in;
d_hi <= inst(5) when d_flag(operation)='1' else d_in;
-- in high, C and I are never set
c_lo <= inst(5) when c_flag(operation)='1' else c_in;
i_lo <= inst(5) when i_flag(operation)='1' else i_in;
-- in low, V and D are never set
set_a <= las or ane or (enable and ((set_a_rom(operation) and inst(7)) or (set_a_low(operation) and not inst(7))));
set_x <= las or (enable and set_x_rom(operation) and inst(7));
set_y <= enable and set_y_rom(operation) and inst(7);
set_s <= las or shy or (enable and set_s_rom(operation) and inst(7));
c_out <= c_in when inst(7)='1' else c_lo; -- C can only be set in lo
v_out <= v_hi when inst(7)='1' else v_in; -- V can only be set in hi
n_out <= result(7) when do_nz='1' else n_in;
z_out <= zero when do_nz='1' else z_in;
d_out <= d_hi when inst(7)='1' and enable='1' else d_in; -- D can only be set in hi
i_out <= i_lo when inst(7)='0' and enable='1' else i_in; -- I can only be set in lo
process(inst)
begin
case inst is
when X"18" | X"38" | X"58" | X"78" | X"B8" | X"D8" | X"F8" =>
flags_imm <= '1';
when others =>
flags_imm <= '0';
end case;
end process;
end gideon;
| gpl-3.0 | f5942eebbf0c2b17b027bc566eeb4cb4 | 0.497028 | 3.405301 | false | false | false | false |
markusC64/1541ultimate2 | fpga/io/usb2/vhdl_source/usb_cmd_pkg.vhd | 1 | 3,693 | --------------------------------------------------------------------------------
-- Gideon's Logic Architectures - Copyright 2015
-- Entity: usb_cmd_pkg
-- Date:2015-01-18
-- Author: Gideon
-- Description: This package defines the commands that can be sent to the
-- sequencer.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.usb_pkg.all;
package usb_cmd_pkg is
-- Protocol Event
type t_usb_command is ( setup, out_data, in_request, ping );
type t_usb_result is ( res_data, res_ack, res_nak, res_nyet, res_stall, res_error );
type t_usb_cmd_req is record
request : std_logic;
-- command and modifiers (4 bits?)
command : t_usb_command;
do_split : std_logic;
do_data : std_logic;
-- data buffer controls (14 bits)
buffer_index : unsigned(1 downto 0);
data_length : unsigned(9 downto 0);
togglebit : std_logic;
no_data : std_logic;
-- USB addressing (11 bits)
device_addr : unsigned(6 downto 0);
endp_addr : unsigned(3 downto 0);
-- USB addressing (15 bits)
split_hub_addr : unsigned(6 downto 0);
split_port_addr : unsigned(3 downto 0); -- hubs with more than 16 ports are not supported
split_sc : std_logic; -- 0=start 1=complete
split_sp : std_logic; -- 0=full, 1=low
split_et : std_logic_vector(1 downto 0); -- 00=control, 01=iso, 10=bulk, 11=interrupt
end record;
type t_usb_cmd_resp is record
done : std_logic;
result : t_usb_result;
error_code : std_logic_vector(2 downto 0);
-- data descriptor
data_length : unsigned(9 downto 0);
togglebit : std_logic;
no_data : std_logic;
end record;
-- type t_usb_result_encoded is array (t_usb_result range<>) of std_logic_vector(2 downto 0);
-- constant c_usb_result_encoded : t_usb_result_encoded := (
-- res_data => "001",
-- res_ack => "010",
-- res_nak => "011",
-- res_nyet => "100",
-- res_error => "111" );
type t_usb_command_array is array(natural range <>) of t_usb_command;
constant c_usb_commands_decoded : t_usb_command_array(0 to 3) := ( setup, out_data, in_request, ping );
constant c_usb_cmd_init : t_usb_cmd_req := (
request => '0',
command => setup,
do_split => '0',
do_data => '0',
buffer_index => "00",
data_length => "0000000000",
togglebit => '0',
no_data => '1',
device_addr => "0000000",
endp_addr => X"0",
split_hub_addr => "0000000",
split_port_addr => X"0",
split_sc => '0',
split_sp => '0',
split_et => "00" );
function encode_result (pid : std_logic_vector(3 downto 0)) return t_usb_result;
end package;
package body usb_cmd_pkg is
function encode_result (pid : std_logic_vector(3 downto 0)) return t_usb_result is
variable res : t_usb_result;
begin
case pid is
when c_pid_ack => res := res_ack;
when c_pid_nak => res := res_nak;
when c_pid_nyet => res := res_nyet;
when c_pid_stall => res := res_stall;
when others => res := res_error;
end case;
return res;
end function;
end package body;
| gpl-3.0 | e7de92f5e5682e4de62c7e5162bfc7c1 | 0.500677 | 3.707831 | false | false | false | false |
ringof/radiofist_audio | clock.vhd | 1 | 784 | -- Copyright (c) 2015 by David Goncalves <[email protected]>
-- See LICENCE.txt for details
--
-- clock signals where syncronization and distribuion are needed
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity clock is
port (
clk_in : in STD_LOGIC;
reset : in STD_LOGIC;
clk_6mhz : out STD_LOGIC;
decimation_clk : out STD_LOGIC
);
end clock;
architecture RTL of clock is
component dcm_6
port (
CLK_IN1 : in STD_LOGIC;
CLK_ADC : out STD_LOGIC;
DEC_CLK : out STD_LOGIC;
RESET : in STD_LOGIC
);
end component;
signal dec_clk_i : STD_LOGIC;
signal toggle : STD_LOGIC;
signal counter : integer range 0 to 42 := 0;
begin
sample_clock : dcm_6
port map(
CLK_IN1 => clk_in,
CLK_ADC => clk_6mhz,
DEC_CLK => dec_clk_i,
RESET => reset
);
| mit | 52cf04f32c7ebcbff100f4d1b82d25b3 | 0.665816 | 2.790036 | false | false | false | false |
markusC64/1541ultimate2 | fpga/io/itu/vhdl_source/itu_pkg.vhd | 1 | 1,661 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package itu_pkg is
constant c_itu_irq_global : unsigned(3 downto 0) := X"0";
constant c_itu_irq_enable : unsigned(3 downto 0) := X"1";
constant c_itu_irq_disable : unsigned(3 downto 0) := X"2";
constant c_itu_irq_edge : unsigned(3 downto 0) := X"3";
constant c_itu_irq_clear : unsigned(3 downto 0) := X"4";
constant c_itu_irq_active : unsigned(3 downto 0) := X"5";
constant c_itu_timer : unsigned(3 downto 0) := X"6";
constant c_itu_irq_timer_en : unsigned(3 downto 0) := X"7";
constant c_itu_irq_timer_hi : unsigned(3 downto 0) := X"8"; -- big endian word
constant c_itu_irq_timer_lo : unsigned(3 downto 0) := X"9";
constant c_itu_buttons : unsigned(3 downto 0) := X"A";
constant c_itu_fpga_version : unsigned(3 downto 0) := X"B";
constant c_itu_capabilities0 : unsigned(3 downto 0) := X"C";
constant c_itu_capabilities1 : unsigned(3 downto 0) := X"D";
constant c_itu_capabilities2 : unsigned(3 downto 0) := X"E";
constant c_itu_capabilities3 : unsigned(3 downto 0) := X"F";
-- second block
constant c_itu_ms_timer_hi : unsigned(3 downto 0) := X"2";
constant c_itu_ms_timer_lo : unsigned(3 downto 0) := X"3";
constant c_itu_usb_busy : unsigned(3 downto 0) := X"4";
constant c_itu_sd_busy : unsigned(3 downto 0) := X"5";
constant c_itu_misc_io : unsigned(3 downto 0) := X"6";
constant c_itu_irq_en_high : unsigned(3 downto 0) := X"7";
constant c_itu_irq_act_high : unsigned(3 downto 0) := X"8";
end package;
| gpl-3.0 | 1429759b2fcbbff90f2f777c3ce006e5 | 0.605057 | 2.966071 | false | false | false | false |
markusC64/1541ultimate2 | fpga/1541/vhdl_source/c1541_pkg.vhd | 1 | 1,221 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package c1541_pkg is
constant c_drvreg_power : unsigned(3 downto 0) := X"0";
constant c_drvreg_reset : unsigned(3 downto 0) := X"1";
constant c_drvreg_address : unsigned(3 downto 0) := X"2";
constant c_drvreg_sensor : unsigned(3 downto 0) := X"3";
constant c_drvreg_inserted : unsigned(3 downto 0) := X"4";
constant c_drvreg_rammap : unsigned(3 downto 0) := X"5";
constant c_drvreg_side : unsigned(3 downto 0) := X"6";
constant c_drvreg_man_write : unsigned(3 downto 0) := X"7";
constant c_drvreg_track : unsigned(3 downto 0) := X"8";
constant c_drvreg_status : unsigned(3 downto 0) := X"9";
constant c_drvreg_memmap : unsigned(3 downto 0) := X"A";
constant c_drvreg_audiomap : unsigned(3 downto 0) := X"B";
constant c_drvreg_diskchng : unsigned(3 downto 0) := X"C";
constant c_drvreg_drivetype : unsigned(3 downto 0) := X"D";
constant c_drvreg_sound : unsigned(3 downto 0) := X"E";
constant c_drv_dirty_base : unsigned(15 downto 0) := X"0800";
constant c_drv_param_base : unsigned(15 downto 0) := X"1000";
end;
| gpl-3.0 | 1ebce9f1baebf8ea2cd2e788f72b5c3f | 0.614251 | 3.007389 | false | false | false | false |
markusC64/1541ultimate2 | fpga/ip/video/vhdl_source/char_generator_slave.vhd | 1 | 6,187 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Character Generator
-------------------------------------------------------------------------------
-- File : char_generator_slave.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: Character generator
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.char_generator_pkg.all;
entity char_generator_slave is
generic (
g_screen_size : natural := 11 );
port (
clock : in std_logic;
reset : in std_logic;
data_enable : in std_logic;
h_count : in unsigned(11 downto 0);
v_count : in unsigned(11 downto 0);
control : in t_chargen_control;
screen_addr : out unsigned(g_screen_size-1 downto 0);
screen_data : in std_logic_vector(7 downto 0);
color_data : in std_logic_vector(7 downto 0);
char_addr : out unsigned(10 downto 0);
char_data : in std_logic_vector(7 downto 0);
pixel_active : out std_logic;
pixel_opaque : out std_logic;
pixel_data : out unsigned(3 downto 0) );
end entity;
architecture gideon of char_generator_slave is
signal pointer : unsigned(g_screen_size-1 downto 0) := (others => '0');
signal char_x : unsigned(6 downto 0) := (others => '0');
signal char_y : unsigned(3 downto 0) := (others => '0');
signal char_y_d : unsigned(3 downto 0) := (others => '0');
signal pixel_count : unsigned(2 downto 0) := (others => '0');
signal remaining_lines : unsigned(5 downto 0) := (others => '0');
type t_state is (idle, active_line, draw);
signal state : t_state;
-- pipeline
signal color_data_d : std_logic_vector(7 downto 0);
signal active_d1 : std_logic;
signal pixel_sel_d1 : unsigned(2 downto 0);
signal active_d2 : std_logic;
signal pixel_sel_d2 : unsigned(2 downto 0);
begin
process(clock)
variable v_char_data : std_logic_vector(7 downto 0);
begin
if rising_edge(clock) then
active_d1 <= '0';
char_y_d <= char_y;
color_data_d <= color_data;
case state is
when idle =>
pointer <= control.pointer(pointer'range);
char_y <= (others => '0');
remaining_lines <= control.active_lines;
if (v_count = control.y_on) and (control.overlay_on = '1') and (data_enable = '1') then
state <= active_line;
end if;
when active_line =>
char_x <= (others => '0');
pixel_count <= control.char_width;
if remaining_lines = 0 then
state <= idle;
elsif h_count = control.x_on and (data_enable = '1') then
state <= draw;
end if;
when draw =>
if pixel_count = 1 then
pixel_count <= control.char_width;
char_x <= char_x + 1;
if char_x = control.chars_per_line-1 then
state <= active_line;
char_x <= (others => '0');
if char_y = control.char_height-1 then
pointer <= pointer + control.chars_per_line;
char_y <= (others => '0');
remaining_lines <= remaining_lines - 1;
else
char_y <= char_y + 1;
end if;
end if;
else
pixel_count <= pixel_count - 1;
end if;
active_d1 <= '1';
when others =>
null;
end case;
-- pipeline forwards
pixel_sel_d1 <= pixel_count - 1;
pixel_sel_d2 <= pixel_sel_d1;
active_d2 <= active_d1;
-- pixel output
pixel_active <= active_d2;
if active_d2='1' then
v_char_data := char_data;
if char_data /= X"18" and char_y(3) = '1' and control.stretch_y = '0' then -- allow a vertical line to continue
v_char_data := X"00";
end if;
if v_char_data(to_integer(pixel_sel_d2))='1' then
pixel_data <= unsigned(color_data_d(3 downto 0));
if color_data_d(3 downto 0) = control.transparent then
pixel_opaque <= '0';
else
pixel_opaque <= '1';
end if;
else
pixel_data <= unsigned(color_data_d(7 downto 4));
if color_data_d(7 downto 4) = control.transparent then
pixel_opaque <= '0';
else
pixel_opaque <= '1';
end if;
end if;
else
pixel_data <= (others => '0');
pixel_opaque <= '0';
end if;
if reset='1' then
state <= idle;
end if;
end if;
end process;
screen_addr <= pointer + char_x;
char_addr <= unsigned(screen_data) & char_y_d(3 downto 1) when control.stretch_y = '1' else
unsigned(screen_data) & char_y_d(2 downto 0) when char_y_d(3)='0' else
unsigned(screen_data) & "111"; -- keep repeating the last line
end architecture;
| gpl-3.0 | d9289cfc96c5140830ae5be687dc465f | 0.428317 | 4.287595 | false | false | false | false |
markusC64/1541ultimate2 | fpga/cpu_unit/mblite/hw/core/fetch.vhd | 1 | 2,752 | ----------------------------------------------------------------------------------------------
--
-- Input file : fetch.vhd
-- Design name : fetch
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Faculty EEMCS, Department ME&CE
-- : Systems and Circuits group
--
-- Description : Instruction Fetch Stage inserts instruction into the pipeline. It
-- uses a single port Random Access Memory component which holds
-- the instructions. The next instruction is computed in the decode
-- stage.
--
----------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library mblite;
use mblite.config_Pkg.all;
use mblite.core_Pkg.all;
use mblite.std_Pkg.all;
entity fetch is port
(
fetch_o : out fetch_out_type;
imem_o : out imem_out_type;
fetch_i : in fetch_in_type;
imem_i : in imem_in_type;
rst_i : in std_logic;
ena_i : in std_logic;
clk_i : in std_logic
);
end fetch;
architecture arch of fetch is
signal r, rin : fetch_out_type;
signal rst_d : std_logic;
signal ena_o : std_logic;
signal possibly_valid : std_logic;
begin
fetch_o.program_counter <= r.program_counter;
fetch_o.instruction <= imem_i.dat_i;
fetch_o.inst_valid <= possibly_valid and imem_i.ena_i;
ena_o <= ena_i and imem_i.ena_i and not rst_i;
imem_o.adr_o <= rin.program_counter;
imem_o.ena_o <= ena_o;
fetch_comb: process(fetch_i, imem_i, r, rst_d)
variable v : fetch_out_type;
begin
v := r;
if rst_d = '1' then
v.program_counter := (OTHERS => '0');
elsif fetch_i.hazard = '1' or imem_i.ena_i = '0' then
v.program_counter := r.program_counter;
elsif fetch_i.branch = '1' then
v.program_counter := fetch_i.branch_target;
else
v.program_counter := increment(r.program_counter(CFG_IMEM_SIZE - 1 downto 2)) & "00";
end if;
rin <= v;
end process;
fetch_seq: process(clk_i)
begin
if rising_edge(clk_i) then
if rst_i = '1' then
r.program_counter <= (others => '0');
rst_d <= '1';
possibly_valid <= '0';
elsif ena_i = '1' then
r <= rin;
rst_d <= '0';
if imem_i.ena_i = '1' then
possibly_valid <= ena_o;
end if;
end if;
end if;
end process;
end arch; | gpl-3.0 | abf8716277b5b46868d6cf5a34d60f87 | 0.490916 | 3.78542 | false | false | false | false |
armandas/Arcade | alien3_generator.vhd | 2 | 6,816 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity alien3 is
port(
clk, not_reset: in std_logic;
px_x, px_y: in std_logic_vector(9 downto 0);
master_coord_x, master_coord_y: in std_logic_vector(9 downto 0);
missile_coord_x, missile_coord_y: in std_logic_vector(9 downto 0);
restart: in std_logic;
destroyed: out std_logic;
defeated: out std_logic;
explosion_x, explosion_y: out std_logic_vector(9 downto 0);
rgb_pixel: out std_logic_vector(0 to 2)
);
end alien3;
architecture generator of alien3 is
type states is (act, wait_clk);
signal state, state_next: states;
-- width of the alien area (8 * 32)
constant A_WIDTH: integer := 256;
constant A_HEIGHT: integer := 32;
-- 3rd level aliens are at the bottom (64px below master coord)
constant OFFSET: integer := 0;
constant FRAME_DELAY: integer := 100000000;
signal output_enable: std_logic;
-- address is made of row and column adresses
-- addr <= (row_address & col_address);
signal addr: std_logic_vector(9 downto 0);
signal row_address, col_address: std_logic_vector(4 downto 0);
signal origin_x, origin_x_next,
origin_y, origin_y_next: std_logic_vector(9 downto 0);
signal relative_x: std_logic_vector(9 downto 0);
signal missile_relative_x: std_logic_vector(9 downto 0);
signal position_in_frame: std_logic_vector(4 downto 0);
-- whether missile is in alien zone
signal missile_arrived: std_logic;
signal attacked_alien: std_logic_vector(2 downto 0);
signal destruction: std_logic;
-- condition of aliens: left (0) to right (7)
signal alive, alive_next: std_logic_vector(0 to 7);
signal alien_alive: std_logic;
-- second level aliens need two hits to get killed
signal injured1, injured1_next,
injured2, injured2_next: std_logic_vector(0 to 7);
signal frame, frame_next: std_logic;
signal frame_counter, frame_counter_next: std_logic_vector(26 downto 0);
signal alien_rgb, alien31_rgb, alien32_rgb: std_logic_vector(2 downto 0);
-- which alien is currently being drawn
-- leftmost = 0, rightmost = 7
signal alien_number: std_logic_vector(2 downto 0);
begin
process(clk, not_reset)
begin
if not_reset = '0' then
frame <= '0';
frame_counter <= (others => '0');
alive <= (others => '1');
injured1 <= (others => '0');
injured2 <= (others => '0');
state <= act;
elsif falling_edge(clk) then
frame <= frame_next;
frame_counter <= frame_counter_next;
alive <= alive_next;
injured1 <= injured1_next;
injured2 <= injured2_next;
state <= state_next;
end if;
end process;
missile_arrived <= '1' when missile_coord_y < master_coord_y + OFFSET + A_HEIGHT and
missile_coord_x > master_coord_x and
missile_coord_x < master_coord_x + A_WIDTH else
'0';
missile_relative_x <= (missile_coord_x - master_coord_x) when missile_arrived = '1' else
(others => '0');
attacked_alien <= missile_relative_x(7 downto 5) when missile_arrived = '1' else
(others => '0');
position_in_frame <= missile_relative_x(4 downto 0) when missile_arrived = '1' else
(others => '0');
process(missile_coord_x, master_coord_x,
missile_arrived, position_in_frame,
alive, injured1, injured2, state, frame, restart)
begin
state_next <= state;
destruction <= '0';
alive_next <= alive;
injured1_next <= injured1;
injured2_next <= injured2;
case state is
when act =>
if restart = '1' then
alive_next <= (others => '1');
injured1_next <= (others => '0');
injured2_next <= (others => '0');
elsif missile_arrived = '1' and
frame = '0' and
alive(conv_integer(attacked_alien)) = '1' and
position_in_frame > 0 and
position_in_frame < 29
then
if injured2(conv_integer(attacked_alien)) = '0' then
if injured1(conv_integer(attacked_alien)) = '0' then
state_next <= wait_clk;
destruction <= '1';
injured1_next(conv_integer(attacked_alien)) <= '1';
else
state_next <= wait_clk;
destruction <= '1';
injured2_next(conv_integer(attacked_alien)) <= '1';
end if;
else
state_next <= wait_clk;
destruction <= '1';
alive_next(conv_integer(attacked_alien)) <= '0';
end if;
end if;
when wait_clk =>
state_next <= act;
end case;
end process;
relative_x <= px_x - master_coord_x;
alien_number <= relative_x(7 downto 5);
alien_alive <= alive(conv_integer(alien_number));
frame_counter_next <= frame_counter + 1 when frame_counter < FRAME_DELAY else
(others => '0');
frame_next <= (not frame) when frame_counter = 0 else frame;
output_enable <= '1' when (alien_alive = '1' and
px_x >= master_coord_x and
px_x < master_coord_x + A_WIDTH and
px_y >= master_coord_y + OFFSET and
px_y < master_coord_y + OFFSET + A_HEIGHT) else
'0';
row_address <= px_y(4 downto 0) - master_coord_y(4 downto 0);
col_address <= px_x(4 downto 0) - master_coord_x(4 downto 0);
addr <= row_address & col_address;
alien_rgb <= alien31_rgb when frame = '0' else
alien32_rgb;
rgb_pixel <= alien_rgb when output_enable = '1' else
(others => '0');
destroyed <= destruction;
-- attacked alien number is multiplied by 32
origin_x <= master_coord_x + (attacked_alien & "00000");
origin_y <= master_coord_y + OFFSET;
explosion_x <= origin_x;
explosion_y <= origin_y;
defeated <= '1' when alive = 0 else '0';
alien_31:
entity work.alien31_rom(content)
port map(addr => addr, data => alien31_rgb);
alien_32:
entity work.alien32_rom(content)
port map(addr => addr, data => alien32_rgb);
end generator; | bsd-2-clause | 83697165b478ee702e6b707280026b25 | 0.536238 | 3.877133 | false | false | false | false |
markusC64/1541ultimate2 | fpga/6502n/vhdl_source/pkg_6502_decode.vhd | 1 | 11,600 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package pkg_6502_decode is
function is_absolute(inst: std_logic_vector(7 downto 0)) return boolean;
function is_abs_jump(inst: std_logic_vector(7 downto 0)) return boolean;
function is_immediate(inst: std_logic_vector(7 downto 0)) return boolean;
function is_implied(inst: std_logic_vector(7 downto 0)) return boolean;
function is_stack(inst: std_logic_vector(7 downto 0)) return boolean;
function is_push(inst: std_logic_vector(7 downto 0)) return boolean;
function is_zeropage(inst: std_logic_vector(7 downto 0)) return boolean;
function is_indirect(inst: std_logic_vector(7 downto 0)) return boolean;
function is_relative(inst: std_logic_vector(7 downto 0)) return boolean;
function is_load(inst: std_logic_vector(7 downto 0)) return boolean;
function is_store(inst: std_logic_vector(7 downto 0)) return boolean;
function is_shift(inst: std_logic_vector(7 downto 0)) return boolean;
function is_alu(inst: std_logic_vector(7 downto 0)) return boolean;
function is_rmw(inst: std_logic_vector(7 downto 0)) return boolean;
function is_jump(inst: std_logic_vector(7 downto 0)) return boolean;
function is_postindexed(inst: std_logic_vector(7 downto 0)) return boolean;
function is_illegal(inst: std_logic_vector(7 downto 0)) return boolean;
function do_bypass_shift(inst : std_logic_vector(7 downto 0)) return std_logic;
function stack_idx(inst: std_logic_vector(7 downto 0)) return std_logic_vector;
constant c_stack_idx_brk : std_logic_vector(1 downto 0) := "00";
constant c_stack_idx_jsr : std_logic_vector(1 downto 0) := "01";
constant c_stack_idx_rti : std_logic_vector(1 downto 0) := "10";
constant c_stack_idx_rts : std_logic_vector(1 downto 0) := "11";
function select_index_y (inst: std_logic_vector(7 downto 0)) return boolean;
function store_a_from_alu (inst: std_logic_vector(7 downto 0)) return boolean;
-- function load_a (inst: std_logic_vector(7 downto 0)) return boolean;
function load_x (inst: std_logic_vector(7 downto 0)) return boolean;
function load_y (inst: std_logic_vector(7 downto 0)) return boolean;
function shifter_in_select (inst: std_logic_vector(7 downto 0)) return std_logic_vector;
function x_to_alu (inst: std_logic_vector(7 downto 0)) return boolean;
function affect_registers(inst: std_logic_vector(7 downto 0)) return boolean;
type t_result_select is (alu, shift, impl, row0, none);
function flags_from(inst : std_logic_vector(7 downto 0)) return t_result_select;
end;
package body pkg_6502_decode is
function is_absolute(inst: std_logic_vector(7 downto 0)) return boolean is
begin
-- 4320 = X11X | 1101
if inst(3 downto 2)="11" then
return true;
elsif inst(4 downto 2)="110" and inst(0)='1' then
return true;
end if;
return false;
end function;
function is_jump(inst: std_logic_vector(7 downto 0)) return boolean is
begin
return inst(7 downto 6)="01" and inst(3 downto 0)=X"C" and inst(4) = '0';
end function;
function is_immediate(inst: std_logic_vector(7 downto 0)) return boolean is
begin
-- 76543210 = 1XX000X0
if inst(7)='1' and inst(4 downto 2)="000" and inst(0)='0' then
return true;
-- 76543210 = XXX010X1
elsif inst(4 downto 2)="010" and inst(0)='1' then
return true;
end if;
return false;
end function;
function is_implied(inst: std_logic_vector(7 downto 0)) return boolean is
begin
-- 4320 = X100
return inst(3 downto 0)=X"8" or inst(3 downto 0)=X"A";
end function;
function is_stack(inst: std_logic_vector(7 downto 0)) return boolean is
begin
-- 76543210
-- 0xx0x000 => 00, 08, 20, 28, 40, 48, 60, 68
-- BRK,PHP,JSR,PLP,RTI,PHA,RTS,PLA
return inst(7)='0' and inst(4)='0' and inst(2 downto 0)="000";
end function;
function is_push(inst: std_logic_vector(7 downto 0)) return boolean is
begin
-- we already know it's a stack operation, so only the direction is important
return inst(5)='0';
end function;
function is_zeropage(inst: std_logic_vector(7 downto 0)) return boolean is
begin
if inst(3 downto 2)="01" then
return true;
elsif inst(3 downto 2)="00" and inst(0)='1' then
return true;
end if;
return false;
end function;
function is_indirect(inst: std_logic_vector(7 downto 0)) return boolean is
begin
return (inst(3 downto 2)="00" and inst(0)='1');
end function;
function is_relative(inst: std_logic_vector(7 downto 0)) return boolean is
begin
return (inst(4 downto 0)="10000");
end function;
function is_store(inst: std_logic_vector(7 downto 0)) return boolean is
begin
if inst(7 downto 5)="100" then
if inst(2) = '1' or inst(0) = '1' then
return true;
end if;
end if;
return false;
end function;
function is_shift(inst: std_logic_vector(7 downto 0)) return boolean is
begin
-- 0--0101-
return (inst(7)='0' and inst(4 downto 1) = "0101");
-- -- 16, 1e
-- -- 1--0 10-- => 8[89AB], A[89AB], C[89AB], E[89AB]
-- if inst(7)='1' and inst(4 downto 2)="010" then
-- return false;
-- end if;
-- return (inst(1)='1');
end function;
function is_alu(inst: std_logic_vector(7 downto 0)) return boolean is
begin
-- if inst(7)='0' and inst(4 downto 1)="0101" then
-- return false;
-- end if;
return (inst(0)='1');
end function;
function is_load(inst: std_logic_vector(7 downto 0)) return boolean is
begin
return not is_store(inst) and not is_rmw(inst);
end function;
function is_rmw(inst: std_logic_vector(7 downto 0)) return boolean is
begin
return inst(1)='1' and inst(7 downto 6)/="10";
end function;
function is_abs_jump(inst: std_logic_vector(7 downto 0)) return boolean is
begin
return is_jump(inst) and inst(5)='0';
end function;
function is_postindexed(inst: std_logic_vector(7 downto 0)) return boolean is
begin
return inst(4)='1';
end function;
function stack_idx(inst: std_logic_vector(7 downto 0)) return std_logic_vector is
begin
return inst(6 downto 5);
end function;
function select_index_y (inst: std_logic_vector(7 downto 0)) return boolean is
begin
if inst(4)='1' and inst(2)='0' and inst(0)='1' then -- XXX1X0X1
return true;
elsif inst(7 downto 6)="10" and inst(2 downto 1)="11" then -- 10XXX11X
return true;
end if;
return false;
end function;
function load_a (inst: std_logic_vector(7 downto 0)) return boolean is
begin
return (inst = X"68");
end function;
function store_a_from_alu (inst: std_logic_vector(7 downto 0)) return boolean is
begin
-- 0XXXXXX1 or alu operations "lo"
-- 1X100001 or alu operations "hi" (except store and cmp)
-- 0XX01010 (implied) (shift select by 'is_shift'!)
return (inst(7)='0' and inst(4 downto 0)="01010") or
(inst(7)='0' and inst(0)='1') or
(inst(7)='1' and inst(0)='1' and inst(5)='1');
end function;
function load_x (inst: std_logic_vector(7 downto 0)) return boolean is
begin
-- 101XXX1X or 1100101- (for SAX #)
if inst(7 downto 1)="1100101" then
return true;
end if;
return inst(7 downto 5)="101" and inst(1)='1' and not is_implied(inst);
end function;
function load_y (inst: std_logic_vector(7 downto 0)) return boolean is
begin
-- 101XXX00
return inst(7 downto 5)="101" and inst(1 downto 0)="00" and not is_implied(inst) and not is_relative(inst);
end function;
function shifter_in_select (inst: std_logic_vector(7 downto 0)) return std_logic_vector is
begin
-- 00 = none, 01 = memory, 10 = A, 11 = A & M
if inst = X"AB" then -- LAX #$
return "00"; -- special case
elsif inst(4 downto 1)="0101" and inst(7)='0' then -- 0xx0101x: 0A, 0B, 2A, 2B, 4A, 4B, 6A, 6B
return inst(1 downto 0); -- 10 or 11
end if;
return "01";
end function;
function is_illegal (inst: std_logic_vector(7 downto 0)) return boolean is
type t_my16bit_array is array(natural range <>) of std_logic_vector(15 downto 0);
constant c_illegal_map : t_my16bit_array(0 to 15) := (
X"989C", X"9C9C", X"888C", X"9C9C", X"889C", X"9C9C", X"889C", X"9C9C",
X"8A8D", X"D88C", X"8888", X"888C", X"888C", X"9C9C", X"888C", X"9C9C" );
variable row : std_logic_vector(15 downto 0);
begin
row := c_illegal_map(to_integer(unsigned(inst(7 downto 4))));
return (row(to_integer(unsigned(inst(3 downto 0)))) = '1');
end function;
function flags_from(inst : std_logic_vector(7 downto 0)) return t_result_select is
begin
-- special case for ANC/ALR
if inst = X"0B" or inst = X"2B" or inst = X"4B" then
return shift;
-- special case for LAS (value and flags are calculated in implied handler)
elsif inst = X"BB" then
return impl;
-- special case for ANE (value and flags are calculated in implied handler, using set A)
elsif inst = X"8B" then
return impl;
elsif is_store(inst) then
return none;
elsif inst(0) = '1' then
return alu;
elsif is_shift(inst) then
return shift;
elsif (inst(3 downto 0) = X"0" or inst(3 downto 0) = X"4" or inst(3 downto 0) = X"C") and inst(4)='0' then
return row0;
elsif is_implied(inst) then
return impl;
elsif inst(7 downto 5) = "101" then -- load
return shift;
end if;
return none;
end function;
function x_to_alu (inst: std_logic_vector(7 downto 0)) return boolean is
begin
-- 1-00101- 8A,8B,CA,CB
return inst(5 downto 1)="00101" and inst(7)='1';
end function;
function affect_registers(inst: std_logic_vector(7 downto 0)) return boolean is
begin
if is_implied(inst) then
return true;
end if;
if (inst(7)='0' or inst(6)='1') and inst(2 downto 0) = "110" then
return false;
end if;
-- 7 downto 5 = 000 001 010 011 110 111
-- 2 downto 0 = 110
-- should not be true for 06 26 46 66 C6 E6
-- should not be true for 16 36 56 76 D6 F6
-- should not be true for 0E 2E 4E 6E CE EE
-- should not be true for 1E 3E 5E 7E DE FE
if is_stack(inst) or is_relative(inst) then
return false;
end if;
return true;
end function;
function do_bypass_shift(inst : std_logic_vector(7 downto 0)) return std_logic is
begin
-- may be optimized
if inst = X"0B" or inst = X"2B" then
return '1';
end if;
return '0';
end function;
end;
| gpl-3.0 | eff38f3988b8475519f944793744ecf1 | 0.590259 | 3.533354 | false | false | false | false |
ntb-ch/cb20 | FPGA_Designs/mpu9250/cb20/synthesis/cb20_gpio_block_0.vhd | 1 | 3,970 | -- cb20_gpio_block_0.vhd
-- Generated using ACDS version 13.0sp1 232 at 2016.10.12.10:12:44
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity cb20_gpio_block_0 is
generic (
number_of_gpios : integer := 9;
unique_id : std_logic_vector(31 downto 0) := "00010010011100000101000000000001"
);
port (
oslv_avs_read_data : out std_logic_vector(31 downto 0); -- avalon_slave_0.readdata
islv_avs_address : in std_logic_vector(3 downto 0) := (others => '0'); -- .address
isl_avs_read : in std_logic := '0'; -- .read
isl_avs_write : in std_logic := '0'; -- .write
osl_avs_waitrequest : out std_logic; -- .waitrequest
islv_avs_write_data : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
islv_avs_byteenable : in std_logic_vector(3 downto 0) := (others => '0'); -- .byteenable
isl_clk : in std_logic := '0'; -- clock_sink.clk
isl_reset_n : in std_logic := '0'; -- reset_sink.reset_n
oslv_gpios : inout std_logic_vector(8 downto 0) := (others => '0') -- conduit_end.export
);
end entity cb20_gpio_block_0;
architecture rtl of cb20_gpio_block_0 is
component avalon_gpio_interface is
generic (
number_of_gpios : integer := 1;
unique_id : std_logic_vector(31 downto 0) := "00000000000000000000000000000000"
);
port (
oslv_avs_read_data : out std_logic_vector(31 downto 0); -- readdata
islv_avs_address : in std_logic_vector(3 downto 0) := (others => 'X'); -- address
isl_avs_read : in std_logic := 'X'; -- read
isl_avs_write : in std_logic := 'X'; -- write
osl_avs_waitrequest : out std_logic; -- waitrequest
islv_avs_write_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
islv_avs_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
isl_clk : in std_logic := 'X'; -- clk
isl_reset_n : in std_logic := 'X'; -- reset_n
oslv_gpios : inout std_logic_vector(8 downto 0) := (others => 'X') -- export
);
end component avalon_gpio_interface;
begin
number_of_gpios_check : if number_of_gpios /= 9 generate
assert false report "Supplied generics do not match expected generics" severity Failure;
end generate;
unique_id_check : if unique_id /= "00010010011100000101000000000001" generate
assert false report "Supplied generics do not match expected generics" severity Failure;
end generate;
gpio_block_0 : component avalon_gpio_interface
generic map (
number_of_gpios => 9,
unique_id => "00010010011100000101000000000001"
)
port map (
oslv_avs_read_data => oslv_avs_read_data, -- avalon_slave_0.readdata
islv_avs_address => islv_avs_address, -- .address
isl_avs_read => isl_avs_read, -- .read
isl_avs_write => isl_avs_write, -- .write
osl_avs_waitrequest => osl_avs_waitrequest, -- .waitrequest
islv_avs_write_data => islv_avs_write_data, -- .writedata
islv_avs_byteenable => islv_avs_byteenable, -- .byteenable
isl_clk => isl_clk, -- clock_sink.clk
isl_reset_n => isl_reset_n, -- reset_sink.reset_n
oslv_gpios => oslv_gpios -- conduit_end.export
);
end architecture rtl; -- of cb20_gpio_block_0
| apache-2.0 | 1a3d6bc6f982db7a7f76eaf8bdf646de | 0.522166 | 3.538324 | false | false | false | false |
markusC64/1541ultimate2 | fpga/ip/synchroniser/vhdl_source/pulse_synchronizer.vhd | 2 | 3,138 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2014, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Pulse synchronizer block
-------------------------------------------------------------------------------
-- Description: The pulse synchronizer block synchronizes pulse in one
-- clock domain into a pulse in the other clock domain.
--
-- Please read Ran Ginosars paper "Fourteen ways to fool your
-- synchronizer" before considering modifications to this module!
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity pulse_synchronizer is
port (
clock_in : in std_logic;
pulse_in : in std_logic;
clock_out : in std_logic;
pulse_out : out std_logic );
---------------------------------------------------------------------------
-- Synthesis attributes to prevent balancing.
---------------------------------------------------------------------------
-- Xilinx attributes
attribute register_balancing : string;
attribute register_balancing of pulse_synchronizer : entity is "no";
-- Altera attributes
attribute dont_retime : boolean;
attribute dont_retime of pulse_synchronizer : entity is true;
---------------------------------------------------------------------------
end pulse_synchronizer;
architecture rtl of pulse_synchronizer is
signal in_toggle : std_logic := '0';
signal sync1 : std_logic := '0';
signal sync2 : std_logic := '0';
signal sync3 : std_logic := '0';
---------------------------------------------------------------------------
-- Synthesis attributes to prevent duplication
---------------------------------------------------------------------------
-- Xilinx attributes
attribute register_duplication : string;
attribute register_duplication of sync1 : signal is "no";
attribute register_duplication of sync2 : signal is "no";
-- Altera attributes
attribute dont_replicate : boolean;
attribute dont_replicate of sync1 : signal is true;
attribute dont_replicate of sync2 : signal is true;
---------------------------------------------------------------------------
begin
p_input_toggle : process(clock_in)
begin
if rising_edge(clock_in) then
if pulse_in='1' then
in_toggle <= not in_toggle;
end if;
end if;
end process;
p_synchronization : process(clock_out)
begin
if rising_edge(clock_out) then
sync1 <= in_toggle;
sync2 <= sync1;
sync3 <= sync2;
pulse_out <= sync2 xor sync3;
end if;
end process;
end rtl;
| gpl-3.0 | 6d553ed7d3624acecd2fe1f342835835 | 0.422243 | 5.613596 | false | false | false | false |
chiggs/nvc | test/regress/issue60.vhd | 5 | 1,078 | package pack is
type int_array1 is array (integer range <>) of integer;
type int_array2 is array (integer range <>) of integer;
end package;
-------------------------------------------------------------------------------
use work.pack.all;
entity sub is
port (
x : in int_array1(1 downto 0);
y : in int_array2(1 downto 0) );
end entity;
architecture test of sub is
begin
process is
begin
assert y = (1, 2);
wait on x;
assert x = (4, 5);
wait on x;
assert x = (6, 7);
wait;
end process;
end architecture;
-------------------------------------------------------------------------------
entity issue60 is
end entity;
use work.pack.all;
architecture test of issue60 is
signal a : int_array2(1 downto 0);
begin
sub_i: entity work.sub
port map (
x => int_array1(a),
y => int_array2(int_array1'(1, 2)) );
process is
begin
a <= (4, 5);
wait for 1 ns;
a <= (6, 7);
wait;
end process;
end architecture;
| gpl-3.0 | 361d03cab82ee4bf5abdaab207831508 | 0.467532 | 3.891697 | false | false | false | false |
markusC64/1541ultimate2 | fpga/ip/busses/vhdl_source/mem_bus_arbiter_pri_32.vhd | 2 | 1,558 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
entity mem_bus_arbiter_pri_32 is
generic (
g_registered: boolean := true;
g_ports : positive := 3 );
port (
clock : in std_logic;
reset : in std_logic;
reqs : in t_mem_req_32_array(0 to g_ports-1);
resps : out t_mem_resp_32_array(0 to g_ports-1);
req : out t_mem_req_32;
resp : in t_mem_resp_32 );
end entity;
architecture rtl of mem_bus_arbiter_pri_32 is
signal req_i : t_mem_req_32;
signal req_c : t_mem_req_32;
begin
-- prioritize the first request found onto output
process(reqs)
begin
req_i <= c_mem_req_32_init;
for i in reqs'range loop
if reqs(i).request='1' then
req_i <= reqs(i);
exit;
end if;
end loop;
end process;
-- send the reply to everyone (including tag)
process(resp)
begin
for i in resps'range loop
resps(i) <= resp;
end loop;
end process;
-- output register (will be eliminated when not used)
process(clock)
begin
if rising_edge(clock) then
req_c <= req_i;
if resp.rack = '1' and (resp.rack_tag = req_c.tag) then
req_c.request <= '0';
end if;
end if;
end process;
req <= req_c when g_registered else req_i;
end architecture;
| gpl-3.0 | 0cebfa0e15ec0d8dac0d952a351c8518 | 0.521823 | 3.372294 | false | false | false | false |
cfelton/musicbox_simple | pck_myhdl_09.vhd | 1 | 3,359 | -- File: pck_myhdl_09.vhd
-- Generated by MyHDL 0.9dev
-- Date: Tue Dec 30 11:42:04 2014
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package pck_myhdl_09 is
attribute enum_encoding: string;
function stdl (arg: boolean) return std_logic;
function stdl (arg: integer) return std_logic;
function to_unsigned (arg: boolean; size: natural) return unsigned;
function to_signed (arg: boolean; size: natural) return signed;
function to_integer(arg: boolean) return integer;
function to_integer(arg: std_logic) return integer;
function to_unsigned (arg: std_logic; size: natural) return unsigned;
function to_signed (arg: std_logic; size: natural) return signed;
function bool (arg: std_logic) return boolean;
function bool (arg: unsigned) return boolean;
function bool (arg: signed) return boolean;
function bool (arg: integer) return boolean;
function "-" (arg: unsigned) return signed;
end pck_myhdl_09;
package body pck_myhdl_09 is
function stdl (arg: boolean) return std_logic is
begin
if arg then
return '1';
else
return '0';
end if;
end function stdl;
function stdl (arg: integer) return std_logic is
begin
if arg /= 0 then
return '1';
else
return '0';
end if;
end function stdl;
function to_unsigned (arg: boolean; size: natural) return unsigned is
variable res: unsigned(size-1 downto 0) := (others => '0');
begin
if arg then
res(0):= '1';
end if;
return res;
end function to_unsigned;
function to_signed (arg: boolean; size: natural) return signed is
variable res: signed(size-1 downto 0) := (others => '0');
begin
if arg then
res(0) := '1';
end if;
return res;
end function to_signed;
function to_integer(arg: boolean) return integer is
begin
if arg then
return 1;
else
return 0;
end if;
end function to_integer;
function to_integer(arg: std_logic) return integer is
begin
if arg = '1' then
return 1;
else
return 0;
end if;
end function to_integer;
function to_unsigned (arg: std_logic; size: natural) return unsigned is
variable res: unsigned(size-1 downto 0) := (others => '0');
begin
res(0):= arg;
return res;
end function to_unsigned;
function to_signed (arg: std_logic; size: natural) return signed is
variable res: signed(size-1 downto 0) := (others => '0');
begin
res(0) := arg;
return res;
end function to_signed;
function bool (arg: std_logic) return boolean is
begin
return arg = '1';
end function bool;
function bool (arg: unsigned) return boolean is
begin
return arg /= 0;
end function bool;
function bool (arg: signed) return boolean is
begin
return arg /= 0;
end function bool;
function bool (arg: integer) return boolean is
begin
return arg /= 0;
end function bool;
function "-" (arg: unsigned) return signed is
begin
return - signed(resize(arg, arg'length+1));
end function "-";
end pck_myhdl_09;
| mit | 723784a7c00a554cc1aa7cf0abfc4f0d | 0.601072 | 4.022754 | false | false | false | false |
chiggs/nvc | test/regress/record12.vhd | 5 | 478 | entity record12 is
end entity;
architecture test of record12 is
type rec is record
a, b : integer;
end record;
type rec2 is record
x, y : rec;
end record;
constant r1 : rec := (1, 2);
constant r2 : rec := (3, 4);
constant r3 : rec2 := (r1, r2);
begin
process is
begin
assert r1.a = 1;
assert r3.x = r1;
assert r3.y = r2;
assert r3.y.a = 3;
wait;
end process;
end architecture;
| gpl-3.0 | 5447011d9d21367f19dfcde2c3668a88 | 0.533473 | 3.22973 | false | false | false | false |
markusC64/1541ultimate2 | fpga/io/usb/vhdl_source/usb1_token_crc.vhd | 2 | 1,878 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2004, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : token_crc.vhd
-------------------------------------------------------------------------------
-- File : token_crc.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This file is used to calculate the CRC over a USB token
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity usb1_token_crc is
port (
clock : in std_logic;
sync : in std_logic;
token_in : in std_logic_vector(10 downto 0);
crc : out std_logic_vector(4 downto 0) );
end usb1_token_crc;
architecture Gideon of usb1_token_crc is
-- signal crc_reg : std_logic_vector(4 downto 0) := (others => '0');
constant polynom : std_logic_vector(4 downto 0) := "00100";
-- CRC-5 = x5 + x2 + 1
begin
process(clock)
variable tmp : std_logic_vector(crc'range);
variable d : std_logic;
begin
if rising_edge(clock) then
tmp := (others => '1');
for i in token_in'reverse_range loop -- LSB first!
d := token_in(i) xor tmp(tmp'high);
tmp := tmp(tmp'high-1 downto 0) & d; --'0';
if d = '1' then
tmp := tmp xor polynom;
end if;
end loop;
for i in tmp'range loop -- reverse and invert
crc(crc'high-i) <= not(tmp(i));
end loop;
end if;
end process;
end Gideon;
| gpl-3.0 | 951a5bff9bb2424fda6a68ec4ebb79bf | 0.404686 | 4.367442 | false | false | false | false |
markusC64/1541ultimate2 | fpga/cpu_unit/mblite/hw/std/sram.vhd | 2 | 1,512 | ----------------------------------------------------------------------------------------------
--
-- Input file : sram.vhd
-- Design name : sram
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Faculty EEMCS, Department ME&CE
-- : Systems and Circuits group
--
-- Description : Single Port Synchronous Random Access Memory
--
----------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library mblite;
use mblite.std_Pkg.all;
entity sram is generic
(
WIDTH : positive := 32;
SIZE : positive := 16
);
port
(
dat_o : out std_logic_vector(WIDTH - 1 downto 0);
dat_i : in std_logic_vector(WIDTH - 1 downto 0);
adr_i : in std_logic_vector(SIZE - 1 downto 0);
wre_i : in std_logic;
ena_i : in std_logic;
clk_i : in std_logic
);
end sram;
architecture arch of sram is
type ram_type is array(2 ** SIZE - 1 downto 0) of std_logic_vector(WIDTH - 1 downto 0);
signal ram : ram_type;
begin
process(clk_i)
begin
if rising_edge(clk_i) then
if ena_i = '1' then
if wre_i = '1' then
ram(my_conv_integer(adr_i)) <= dat_i;
end if;
dat_o <= ram(my_conv_integer(adr_i));
end if;
end if;
end process;
end arch;
| gpl-3.0 | fd10d91eeeb43b246db331a8ffba2950 | 0.474206 | 3.978947 | false | false | false | false |
chiggs/nvc | test/simp/cfold.vhd | 3 | 2,672 | entity e is
end entity;
architecture a of e is
signal x : integer := -3 * 4 + 2;
type t is range -5 to 11 - 3;
constant c : integer := +4 + 1;
signal y : t;
type int_array is array (integer range <>) of integer;
constant a1 : int_array(1 to 5) := (1, 2, 3, 4, 5);
constant a2 : int_array(1 to 7) := (2 to 3 => 6, others => 5);
constant a3 : int_array(1 to 9) := (8 => 24, others => 0);
constant a4 : int_array(5 downto 1) := (1, 2, 3, 4, 5);
constant a5 : int_array(5 downto 1) := (5 downto 3 => -1, others => 1);
begin
process is
variable b : boolean;
begin
x <= c / 2;
y <= t'high;
y <= t'left;
b := t'right = 8;
b := (t'right - t'left) = 2;
b := t'high /= 2;
b := true and true;
b := true and false;
b := true or false;
b := true xor true;
b := not true;
b := not false;
b := true xnor false;
b := false nand false;
b := false nor true;
b := 7 > 5 and 6 < 2;
x <= a1(2);
x <= a2(1);
x <= a2(3);
x <= a3(8);
x <= a1'length;
x <= a4(2);
x <= a5(4);
x <= 2 ** 4;
end process;
process is
begin
if true then
x <= 1;
end if;
if false then
x <= 5;
end if;
if false then
null;
else
x <= 5;
end if;
while false loop
null;
end loop;
if true then
x <= 1;
x <= 5;
null;
end if;
end process;
process is
variable r : real;
variable b : boolean;
begin
r := 1.0 + 0.0;
r := 1.5 * 4.0;
r := 2.0 / 2.0;
b := 4.6 > 1.2;
end process;
process
variable k : time;
begin
end process;
process
type int2_vec is array (66 to 67) of integer;
begin
assert a1'length = 5;
assert a1'low(1) = 1;
assert a1'high(1) = 5;
assert a1'left = 1;
assert a1'right = 5;
assert int2_vec'length = 2;
assert int2_vec'low = 66;
end process;
process is
begin
case 1 is
when 1 => null;
when others => report "bang";
end case;
end process;
process is
variable r : real;
begin
r := 1.5 * 2;
r := 3 * 0.2;
r := 5.0 / 2;
end process;
process is
constant one : bit := '1';
variable b : boolean;
begin
b := one = '1';
b := '0' /= one;
end process;
end architecture;
| gpl-3.0 | a51de2607d349537d206fa66351215f7 | 0.427395 | 3.408163 | false | false | false | false |
ntb-ch/cb20 | FPGA_Designs/mpu9250/cb20/synthesis/cb20.vhd | 1 | 436,724 | -- cb20.vhd
-- Generated using ACDS version 13.0sp1 232 at 2016.10.12.10:12:44
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity cb20 is
port (
clk_clk : in std_logic := '0'; -- clk.clk
reset_reset_n : in std_logic := '0'; -- reset.reset_n
eim_slave_to_avalon_master_0_conduit_end_ioslv_data : inout std_logic_vector(15 downto 0) := (others => '0'); -- eim_slave_to_avalon_master_0_conduit_end.ioslv_data
eim_slave_to_avalon_master_0_conduit_end_isl_cs_n : in std_logic := '0'; -- .isl_cs_n
eim_slave_to_avalon_master_0_conduit_end_isl_oe_n : in std_logic := '0'; -- .isl_oe_n
eim_slave_to_avalon_master_0_conduit_end_isl_we_n : in std_logic := '0'; -- .isl_we_n
eim_slave_to_avalon_master_0_conduit_end_osl_data_ack : out std_logic; -- .osl_data_ack
eim_slave_to_avalon_master_0_conduit_end_islv_address : in std_logic_vector(15 downto 0) := (others => '0'); -- .islv_address
dacad5668_0_conduit_end_osl_sclk : out std_logic; -- dacad5668_0_conduit_end.osl_sclk
dacad5668_0_conduit_end_oslv_Ss : out std_logic; -- .oslv_Ss
dacad5668_0_conduit_end_osl_mosi : out std_logic; -- .osl_mosi
dacad5668_0_conduit_end_osl_LDAC_n : out std_logic; -- .osl_LDAC_n
dacad5668_0_conduit_end_osl_CLR_n : out std_logic; -- .osl_CLR_n
fqd_interface_0_conduit_end_B : in std_logic_vector(7 downto 0) := (others => '0'); -- fqd_interface_0_conduit_end.B
fqd_interface_0_conduit_end_A : in std_logic_vector(7 downto 0) := (others => '0'); -- .A
gpio_block_0_conduit_end_export : inout std_logic_vector(8 downto 0) := (others => '0'); -- gpio_block_0_conduit_end.export
pwm_interface_0_conduit_end_export : out std_logic_vector(3 downto 0); -- pwm_interface_0_conduit_end.export
gpio_block_1_conduit_end_export : inout std_logic_vector(7 downto 0) := (others => '0'); -- gpio_block_1_conduit_end.export
mpu9250_0_conduit_end_osl_sclk : out std_logic; -- mpu9250_0_conduit_end.osl_sclk
mpu9250_0_conduit_end_oslv_cs_n : out std_logic; -- .oslv_cs_n
mpu9250_0_conduit_end_isl_sdo : in std_logic := '0'; -- .isl_sdo
mpu9250_0_conduit_end_osl_sdi : out std_logic -- .osl_sdi
);
end entity cb20;
architecture rtl of cb20 is
component cb20_altpll_0 is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
read : in std_logic := 'X'; -- read
write : in std_logic := 'X'; -- write
address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
readdata : out std_logic_vector(31 downto 0); -- readdata
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
c0 : out std_logic; -- clk
areset : in std_logic := 'X'; -- export
locked : out std_logic; -- export
phasedone : out std_logic -- export
);
end component cb20_altpll_0;
component info_device is
generic (
unique_id : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
description : std_logic_vector(223 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
dev_size : integer := 0
);
port (
isl_clk : in std_logic := 'X'; -- clk
isl_reset_n : in std_logic := 'X'; -- reset_n
islv_avs_address : in std_logic_vector(4 downto 0) := (others => 'X'); -- address
isl_avs_read : in std_logic := 'X'; -- read
isl_avs_write : in std_logic := 'X'; -- write
islv_avs_write_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
oslv_avs_read_data : out std_logic_vector(31 downto 0); -- readdata
osl_avs_waitrequest : out std_logic; -- waitrequest
islv_avs_byteenable : in std_logic_vector(3 downto 0) := (others => 'X') -- byteenable
);
end component info_device;
component eim_slave_to_avalon_master is
generic (
TRANSFER_WIDTH : integer := 16
);
port (
ioslv_data : inout std_logic_vector(15 downto 0) := (others => 'X'); -- export
isl_cs_n : in std_logic := 'X'; -- export
isl_oe_n : in std_logic := 'X'; -- export
isl_we_n : in std_logic := 'X'; -- export
osl_data_ack : out std_logic; -- export
islv_address : in std_logic_vector(15 downto 0) := (others => 'X'); -- export
isl_clk : in std_logic := 'X'; -- clk
isl_reset_n : in std_logic := 'X'; -- reset_n
islv_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata
islv_waitrequest : in std_logic := 'X'; -- waitrequest
oslv_address : out std_logic_vector(15 downto 0); -- address
oslv_read : out std_logic; -- read
oslv_write : out std_logic; -- write
oslv_writedata : out std_logic_vector(15 downto 0) -- writedata
);
end component eim_slave_to_avalon_master;
component avalon_dacad5668_interface is
generic (
BASE_CLK : integer := 33000000;
SCLK_FREQUENCY : integer := 10000000;
INTERNAL_REFERENCE : std_logic := '0';
UNIQUE_ID : std_logic_vector(31 downto 0) := "00000000000000000000000000000000"
);
port (
isl_clk : in std_logic := 'X'; -- clk
isl_reset_n : in std_logic := 'X'; -- reset_n
osl_sclk : out std_logic; -- export
oslv_Ss : out std_logic; -- export
osl_mosi : out std_logic; -- export
osl_LDAC_n : out std_logic; -- export
osl_CLR_n : out std_logic; -- export
islv_avs_address : in std_logic_vector(4 downto 0) := (others => 'X'); -- address
isl_avs_read : in std_logic := 'X'; -- read
isl_avs_write : in std_logic := 'X'; -- write
islv_avs_write_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
oslv_avs_read_data : out std_logic_vector(31 downto 0); -- readdata
osl_avs_waitrequest : out std_logic; -- waitrequest
islv_avs_byteenable : in std_logic_vector(3 downto 0) := (others => 'X') -- byteenable
);
end component avalon_dacad5668_interface;
component avalon_fqd_counter_interface is
generic (
number_of_fqds : integer := 1;
unique_id : std_logic_vector(31 downto 0) := "00000000000000000000000000000000"
);
port (
oslv_avs_read_data : out std_logic_vector(31 downto 0); -- readdata
isl_avs_read : in std_logic := 'X'; -- read
isl_avs_write : in std_logic := 'X'; -- write
islv_avs_write_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
islv_avs_address : in std_logic_vector(4 downto 0) := (others => 'X'); -- address
osl_avs_waitrequest : out std_logic; -- waitrequest
islv_avs_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
isl_clk : in std_logic := 'X'; -- clk
isl_reset_n : in std_logic := 'X'; -- reset_n
islv_enc_B : in std_logic_vector(7 downto 0) := (others => 'X'); -- export
islv_enc_A : in std_logic_vector(7 downto 0) := (others => 'X') -- export
);
end component avalon_fqd_counter_interface;
component avalon_pwm_interface is
generic (
number_of_pwms : integer := 1;
base_clk : integer := 125000000;
unique_id : std_logic_vector(31 downto 0) := "00000000000000000000000000000000"
);
port (
oslv_avs_read_data : out std_logic_vector(31 downto 0); -- readdata
islv_avs_address : in std_logic_vector(5 downto 0) := (others => 'X'); -- address
isl_avs_read : in std_logic := 'X'; -- read
isl_avs_write : in std_logic := 'X'; -- write
islv_avs_write_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
osl_avs_waitrequest : out std_logic; -- waitrequest
islv_avs_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
isl_clk : in std_logic := 'X'; -- clk
isl_reset_n : in std_logic := 'X'; -- reset_n
oslv_pwm : out std_logic_vector(3 downto 0) -- export
);
end component avalon_pwm_interface;
component mpu9250_interface is
generic (
BASE_CLK : integer := 33000000;
SCLK_FREQUENCY : integer := 100000;
UNIQUE_ID : std_logic_vector(31 downto 0) := "00000000000000000000000000000000"
);
port (
islv_avs_write_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
oslv_avs_read_data : out std_logic_vector(31 downto 0); -- readdata
isl_avs_write : in std_logic := 'X'; -- write
isl_avs_read : in std_logic := 'X'; -- read
islv_avs_address : in std_logic_vector(4 downto 0) := (others => 'X'); -- address
islv_avs_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
osl_avs_waitrequest : out std_logic; -- waitrequest
isl_clk : in std_logic := 'X'; -- clk
isl_reset_n : in std_logic := 'X'; -- reset_n
osl_sclk : out std_logic; -- export
oslv_cs_n : out std_logic; -- export
isl_sdo : in std_logic := 'X'; -- export
osl_sdi : out std_logic -- export
);
end component mpu9250_interface;
component altera_merlin_master_translator is
generic (
AV_ADDRESS_W : integer := 32;
AV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 38;
UAV_BURSTCOUNT_W : integer := 10;
USE_READ : integer := 1;
USE_WRITE : integer := 1;
USE_BEGINBURSTTRANSFER : integer := 0;
USE_BEGINTRANSFER : integer := 0;
USE_CHIPSELECT : integer := 0;
USE_BURSTCOUNT : integer := 1;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_LINEWRAPBURSTS : integer := 0;
AV_REGISTERINCOMINGSIGNALS : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : out std_logic_vector(16 downto 0); -- address
uav_burstcount : out std_logic_vector(1 downto 0); -- burstcount
uav_read : out std_logic; -- read
uav_write : out std_logic; -- write
uav_waitrequest : in std_logic := 'X'; -- waitrequest
uav_readdatavalid : in std_logic := 'X'; -- readdatavalid
uav_byteenable : out std_logic_vector(1 downto 0); -- byteenable
uav_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata
uav_writedata : out std_logic_vector(15 downto 0); -- writedata
uav_lock : out std_logic; -- lock
uav_debugaccess : out std_logic; -- debugaccess
av_address : in std_logic_vector(15 downto 0) := (others => 'X'); -- address
av_waitrequest : out std_logic; -- waitrequest
av_read : in std_logic := 'X'; -- read
av_readdata : out std_logic_vector(15 downto 0); -- readdata
av_write : in std_logic := 'X'; -- write
av_writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
av_burstcount : in std_logic_vector(0 downto 0) := (others => 'X'); -- burstcount
av_byteenable : in std_logic_vector(1 downto 0) := (others => 'X'); -- byteenable
av_beginbursttransfer : in std_logic := 'X'; -- beginbursttransfer
av_begintransfer : in std_logic := 'X'; -- begintransfer
av_chipselect : in std_logic := 'X'; -- chipselect
av_readdatavalid : out std_logic; -- readdatavalid
av_lock : in std_logic := 'X'; -- lock
av_debugaccess : in std_logic := 'X'; -- debugaccess
uav_clken : out std_logic; -- clken
av_clken : in std_logic := 'X'; -- clken
uav_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response
av_response : out std_logic_vector(1 downto 0); -- response
uav_writeresponserequest : out std_logic; -- writeresponserequest
uav_writeresponsevalid : in std_logic := 'X'; -- writeresponsevalid
av_writeresponserequest : in std_logic := 'X'; -- writeresponserequest
av_writeresponsevalid : out std_logic -- writeresponsevalid
);
end component altera_merlin_master_translator;
component altera_merlin_master_agent is
generic (
PKT_PROTECTION_H : integer := 80;
PKT_PROTECTION_L : integer := 80;
PKT_BEGIN_BURST : integer := 81;
PKT_BURSTWRAP_H : integer := 79;
PKT_BURSTWRAP_L : integer := 77;
PKT_BURST_SIZE_H : integer := 86;
PKT_BURST_SIZE_L : integer := 84;
PKT_BURST_TYPE_H : integer := 94;
PKT_BURST_TYPE_L : integer := 93;
PKT_BYTE_CNT_H : integer := 76;
PKT_BYTE_CNT_L : integer := 74;
PKT_ADDR_H : integer := 73;
PKT_ADDR_L : integer := 42;
PKT_TRANS_COMPRESSED_READ : integer := 41;
PKT_TRANS_POSTED : integer := 40;
PKT_TRANS_WRITE : integer := 39;
PKT_TRANS_READ : integer := 38;
PKT_TRANS_LOCK : integer := 82;
PKT_TRANS_EXCLUSIVE : integer := 83;
PKT_DATA_H : integer := 37;
PKT_DATA_L : integer := 6;
PKT_BYTEEN_H : integer := 5;
PKT_BYTEEN_L : integer := 2;
PKT_SRC_ID_H : integer := 1;
PKT_SRC_ID_L : integer := 1;
PKT_DEST_ID_H : integer := 0;
PKT_DEST_ID_L : integer := 0;
PKT_THREAD_ID_H : integer := 88;
PKT_THREAD_ID_L : integer := 87;
PKT_CACHE_H : integer := 92;
PKT_CACHE_L : integer := 89;
PKT_DATA_SIDEBAND_H : integer := 105;
PKT_DATA_SIDEBAND_L : integer := 98;
PKT_QOS_H : integer := 109;
PKT_QOS_L : integer := 106;
PKT_ADDR_SIDEBAND_H : integer := 97;
PKT_ADDR_SIDEBAND_L : integer := 93;
PKT_RESPONSE_STATUS_H : integer := 111;
PKT_RESPONSE_STATUS_L : integer := 110;
ST_DATA_W : integer := 112;
ST_CHANNEL_W : integer := 1;
AV_BURSTCOUNT_W : integer := 3;
SUPPRESS_0_BYTEEN_RSP : integer := 1;
ID : integer := 1;
BURSTWRAP_VALUE : integer := 4;
CACHE_VALUE : integer := 0;
SECURE_ACCESS_BIT : integer := 1;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
av_address : in std_logic_vector(16 downto 0) := (others => 'X'); -- address
av_write : in std_logic := 'X'; -- write
av_read : in std_logic := 'X'; -- read
av_writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
av_readdata : out std_logic_vector(15 downto 0); -- readdata
av_waitrequest : out std_logic; -- waitrequest
av_readdatavalid : out std_logic; -- readdatavalid
av_byteenable : in std_logic_vector(1 downto 0) := (others => 'X'); -- byteenable
av_burstcount : in std_logic_vector(1 downto 0) := (others => 'X'); -- burstcount
av_debugaccess : in std_logic := 'X'; -- debugaccess
av_lock : in std_logic := 'X'; -- lock
cp_valid : out std_logic; -- valid
cp_data : out std_logic_vector(69 downto 0); -- data
cp_startofpacket : out std_logic; -- startofpacket
cp_endofpacket : out std_logic; -- endofpacket
cp_ready : in std_logic := 'X'; -- ready
rp_valid : in std_logic := 'X'; -- valid
rp_data : in std_logic_vector(69 downto 0) := (others => 'X'); -- data
rp_channel : in std_logic_vector(6 downto 0) := (others => 'X'); -- channel
rp_startofpacket : in std_logic := 'X'; -- startofpacket
rp_endofpacket : in std_logic := 'X'; -- endofpacket
rp_ready : out std_logic; -- ready
av_response : out std_logic_vector(1 downto 0); -- response
av_writeresponserequest : in std_logic := 'X'; -- writeresponserequest
av_writeresponsevalid : out std_logic -- writeresponsevalid
);
end component altera_merlin_master_agent;
component altera_merlin_slave_agent is
generic (
PKT_DATA_H : integer := 31;
PKT_DATA_L : integer := 0;
PKT_BEGIN_BURST : integer := 81;
PKT_SYMBOL_W : integer := 8;
PKT_BYTEEN_H : integer := 71;
PKT_BYTEEN_L : integer := 68;
PKT_ADDR_H : integer := 63;
PKT_ADDR_L : integer := 32;
PKT_TRANS_COMPRESSED_READ : integer := 67;
PKT_TRANS_POSTED : integer := 66;
PKT_TRANS_WRITE : integer := 65;
PKT_TRANS_READ : integer := 64;
PKT_TRANS_LOCK : integer := 87;
PKT_SRC_ID_H : integer := 74;
PKT_SRC_ID_L : integer := 72;
PKT_DEST_ID_H : integer := 77;
PKT_DEST_ID_L : integer := 75;
PKT_BURSTWRAP_H : integer := 85;
PKT_BURSTWRAP_L : integer := 82;
PKT_BYTE_CNT_H : integer := 81;
PKT_BYTE_CNT_L : integer := 78;
PKT_PROTECTION_H : integer := 86;
PKT_PROTECTION_L : integer := 86;
PKT_RESPONSE_STATUS_H : integer := 89;
PKT_RESPONSE_STATUS_L : integer := 88;
PKT_BURST_SIZE_H : integer := 92;
PKT_BURST_SIZE_L : integer := 90;
ST_CHANNEL_W : integer := 8;
ST_DATA_W : integer := 93;
AVS_BURSTCOUNT_W : integer := 4;
SUPPRESS_0_BYTEEN_CMD : integer := 1;
PREVENT_FIFO_OVERFLOW : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
m0_address : out std_logic_vector(16 downto 0); -- address
m0_burstcount : out std_logic_vector(2 downto 0); -- burstcount
m0_byteenable : out std_logic_vector(3 downto 0); -- byteenable
m0_debugaccess : out std_logic; -- debugaccess
m0_lock : out std_logic; -- lock
m0_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
m0_readdatavalid : in std_logic := 'X'; -- readdatavalid
m0_read : out std_logic; -- read
m0_waitrequest : in std_logic := 'X'; -- waitrequest
m0_writedata : out std_logic_vector(31 downto 0); -- writedata
m0_write : out std_logic; -- write
rp_endofpacket : out std_logic; -- endofpacket
rp_ready : in std_logic := 'X'; -- ready
rp_valid : out std_logic; -- valid
rp_data : out std_logic_vector(87 downto 0); -- data
rp_startofpacket : out std_logic; -- startofpacket
cp_ready : out std_logic; -- ready
cp_valid : in std_logic := 'X'; -- valid
cp_data : in std_logic_vector(87 downto 0) := (others => 'X'); -- data
cp_startofpacket : in std_logic := 'X'; -- startofpacket
cp_endofpacket : in std_logic := 'X'; -- endofpacket
cp_channel : in std_logic_vector(6 downto 0) := (others => 'X'); -- channel
rf_sink_ready : out std_logic; -- ready
rf_sink_valid : in std_logic := 'X'; -- valid
rf_sink_startofpacket : in std_logic := 'X'; -- startofpacket
rf_sink_endofpacket : in std_logic := 'X'; -- endofpacket
rf_sink_data : in std_logic_vector(88 downto 0) := (others => 'X'); -- data
rf_source_ready : in std_logic := 'X'; -- ready
rf_source_valid : out std_logic; -- valid
rf_source_startofpacket : out std_logic; -- startofpacket
rf_source_endofpacket : out std_logic; -- endofpacket
rf_source_data : out std_logic_vector(88 downto 0); -- data
rdata_fifo_sink_ready : out std_logic; -- ready
rdata_fifo_sink_valid : in std_logic := 'X'; -- valid
rdata_fifo_sink_data : in std_logic_vector(33 downto 0) := (others => 'X'); -- data
rdata_fifo_src_ready : in std_logic := 'X'; -- ready
rdata_fifo_src_valid : out std_logic; -- valid
rdata_fifo_src_data : out std_logic_vector(33 downto 0); -- data
m0_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response
m0_writeresponserequest : out std_logic; -- writeresponserequest
m0_writeresponsevalid : in std_logic := 'X' -- writeresponsevalid
);
end component altera_merlin_slave_agent;
component altera_avalon_sc_fifo is
generic (
SYMBOLS_PER_BEAT : integer := 1;
BITS_PER_SYMBOL : integer := 8;
FIFO_DEPTH : integer := 16;
CHANNEL_WIDTH : integer := 0;
ERROR_WIDTH : integer := 0;
USE_PACKETS : integer := 0;
USE_FILL_LEVEL : integer := 0;
EMPTY_LATENCY : integer := 3;
USE_MEMORY_BLOCKS : integer := 1;
USE_STORE_FORWARD : integer := 0;
USE_ALMOST_FULL_IF : integer := 0;
USE_ALMOST_EMPTY_IF : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
in_data : in std_logic_vector(88 downto 0) := (others => 'X'); -- data
in_valid : in std_logic := 'X'; -- valid
in_ready : out std_logic; -- ready
in_startofpacket : in std_logic := 'X'; -- startofpacket
in_endofpacket : in std_logic := 'X'; -- endofpacket
out_data : out std_logic_vector(88 downto 0); -- data
out_valid : out std_logic; -- valid
out_ready : in std_logic := 'X'; -- ready
out_startofpacket : out std_logic; -- startofpacket
out_endofpacket : out std_logic; -- endofpacket
csr_address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
csr_read : in std_logic := 'X'; -- read
csr_write : in std_logic := 'X'; -- write
csr_readdata : out std_logic_vector(31 downto 0); -- readdata
csr_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
almost_full_data : out std_logic; -- data
almost_empty_data : out std_logic; -- data
in_empty : in std_logic := 'X'; -- empty
out_empty : out std_logic; -- empty
in_error : in std_logic := 'X'; -- error
out_error : out std_logic; -- error
in_channel : in std_logic := 'X'; -- channel
out_channel : out std_logic -- channel
);
end component altera_avalon_sc_fifo;
component cb20_addr_router is
port (
sink_ready : out std_logic; -- ready
sink_valid : in std_logic := 'X'; -- valid
sink_data : in std_logic_vector(69 downto 0) := (others => 'X'); -- data
sink_startofpacket : in std_logic := 'X'; -- startofpacket
sink_endofpacket : in std_logic := 'X'; -- endofpacket
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
src_ready : in std_logic := 'X'; -- ready
src_valid : out std_logic; -- valid
src_data : out std_logic_vector(69 downto 0); -- data
src_channel : out std_logic_vector(6 downto 0); -- channel
src_startofpacket : out std_logic; -- startofpacket
src_endofpacket : out std_logic -- endofpacket
);
end component cb20_addr_router;
component cb20_id_router is
port (
sink_ready : out std_logic; -- ready
sink_valid : in std_logic := 'X'; -- valid
sink_data : in std_logic_vector(87 downto 0) := (others => 'X'); -- data
sink_startofpacket : in std_logic := 'X'; -- startofpacket
sink_endofpacket : in std_logic := 'X'; -- endofpacket
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
src_ready : in std_logic := 'X'; -- ready
src_valid : out std_logic; -- valid
src_data : out std_logic_vector(87 downto 0); -- data
src_channel : out std_logic_vector(6 downto 0); -- channel
src_startofpacket : out std_logic; -- startofpacket
src_endofpacket : out std_logic -- endofpacket
);
end component cb20_id_router;
component altera_reset_controller is
generic (
NUM_RESET_INPUTS : integer := 6;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 0
);
port (
reset_in0 : in std_logic := 'X'; -- reset
clk : in std_logic := 'X'; -- clk
reset_out : out std_logic; -- reset
reset_req : out std_logic; -- reset_req
reset_in1 : in std_logic := 'X'; -- reset
reset_in2 : in std_logic := 'X'; -- reset
reset_in3 : in std_logic := 'X'; -- reset
reset_in4 : in std_logic := 'X'; -- reset
reset_in5 : in std_logic := 'X'; -- reset
reset_in6 : in std_logic := 'X'; -- reset
reset_in7 : in std_logic := 'X'; -- reset
reset_in8 : in std_logic := 'X'; -- reset
reset_in9 : in std_logic := 'X'; -- reset
reset_in10 : in std_logic := 'X'; -- reset
reset_in11 : in std_logic := 'X'; -- reset
reset_in12 : in std_logic := 'X'; -- reset
reset_in13 : in std_logic := 'X'; -- reset
reset_in14 : in std_logic := 'X'; -- reset
reset_in15 : in std_logic := 'X' -- reset
);
end component altera_reset_controller;
component cb20_cmd_xbar_demux is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
sink_ready : out std_logic; -- ready
sink_channel : in std_logic_vector(6 downto 0) := (others => 'X'); -- channel
sink_data : in std_logic_vector(69 downto 0) := (others => 'X'); -- data
sink_startofpacket : in std_logic := 'X'; -- startofpacket
sink_endofpacket : in std_logic := 'X'; -- endofpacket
sink_valid : in std_logic_vector(0 downto 0) := (others => 'X'); -- valid
src0_ready : in std_logic := 'X'; -- ready
src0_valid : out std_logic; -- valid
src0_data : out std_logic_vector(69 downto 0); -- data
src0_channel : out std_logic_vector(6 downto 0); -- channel
src0_startofpacket : out std_logic; -- startofpacket
src0_endofpacket : out std_logic; -- endofpacket
src1_ready : in std_logic := 'X'; -- ready
src1_valid : out std_logic; -- valid
src1_data : out std_logic_vector(69 downto 0); -- data
src1_channel : out std_logic_vector(6 downto 0); -- channel
src1_startofpacket : out std_logic; -- startofpacket
src1_endofpacket : out std_logic; -- endofpacket
src2_ready : in std_logic := 'X'; -- ready
src2_valid : out std_logic; -- valid
src2_data : out std_logic_vector(69 downto 0); -- data
src2_channel : out std_logic_vector(6 downto 0); -- channel
src2_startofpacket : out std_logic; -- startofpacket
src2_endofpacket : out std_logic; -- endofpacket
src3_ready : in std_logic := 'X'; -- ready
src3_valid : out std_logic; -- valid
src3_data : out std_logic_vector(69 downto 0); -- data
src3_channel : out std_logic_vector(6 downto 0); -- channel
src3_startofpacket : out std_logic; -- startofpacket
src3_endofpacket : out std_logic; -- endofpacket
src4_ready : in std_logic := 'X'; -- ready
src4_valid : out std_logic; -- valid
src4_data : out std_logic_vector(69 downto 0); -- data
src4_channel : out std_logic_vector(6 downto 0); -- channel
src4_startofpacket : out std_logic; -- startofpacket
src4_endofpacket : out std_logic; -- endofpacket
src5_ready : in std_logic := 'X'; -- ready
src5_valid : out std_logic; -- valid
src5_data : out std_logic_vector(69 downto 0); -- data
src5_channel : out std_logic_vector(6 downto 0); -- channel
src5_startofpacket : out std_logic; -- startofpacket
src5_endofpacket : out std_logic; -- endofpacket
src6_ready : in std_logic := 'X'; -- ready
src6_valid : out std_logic; -- valid
src6_data : out std_logic_vector(69 downto 0); -- data
src6_channel : out std_logic_vector(6 downto 0); -- channel
src6_startofpacket : out std_logic; -- startofpacket
src6_endofpacket : out std_logic -- endofpacket
);
end component cb20_cmd_xbar_demux;
component cb20_rsp_xbar_demux is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
sink_ready : out std_logic; -- ready
sink_channel : in std_logic_vector(6 downto 0) := (others => 'X'); -- channel
sink_data : in std_logic_vector(69 downto 0) := (others => 'X'); -- data
sink_startofpacket : in std_logic := 'X'; -- startofpacket
sink_endofpacket : in std_logic := 'X'; -- endofpacket
sink_valid : in std_logic_vector(0 downto 0) := (others => 'X'); -- valid
src0_ready : in std_logic := 'X'; -- ready
src0_valid : out std_logic; -- valid
src0_data : out std_logic_vector(69 downto 0); -- data
src0_channel : out std_logic_vector(6 downto 0); -- channel
src0_startofpacket : out std_logic; -- startofpacket
src0_endofpacket : out std_logic -- endofpacket
);
end component cb20_rsp_xbar_demux;
component cb20_rsp_xbar_mux is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
src_ready : in std_logic := 'X'; -- ready
src_valid : out std_logic; -- valid
src_data : out std_logic_vector(69 downto 0); -- data
src_channel : out std_logic_vector(6 downto 0); -- channel
src_startofpacket : out std_logic; -- startofpacket
src_endofpacket : out std_logic; -- endofpacket
sink0_ready : out std_logic; -- ready
sink0_valid : in std_logic := 'X'; -- valid
sink0_channel : in std_logic_vector(6 downto 0) := (others => 'X'); -- channel
sink0_data : in std_logic_vector(69 downto 0) := (others => 'X'); -- data
sink0_startofpacket : in std_logic := 'X'; -- startofpacket
sink0_endofpacket : in std_logic := 'X'; -- endofpacket
sink1_ready : out std_logic; -- ready
sink1_valid : in std_logic := 'X'; -- valid
sink1_channel : in std_logic_vector(6 downto 0) := (others => 'X'); -- channel
sink1_data : in std_logic_vector(69 downto 0) := (others => 'X'); -- data
sink1_startofpacket : in std_logic := 'X'; -- startofpacket
sink1_endofpacket : in std_logic := 'X'; -- endofpacket
sink2_ready : out std_logic; -- ready
sink2_valid : in std_logic := 'X'; -- valid
sink2_channel : in std_logic_vector(6 downto 0) := (others => 'X'); -- channel
sink2_data : in std_logic_vector(69 downto 0) := (others => 'X'); -- data
sink2_startofpacket : in std_logic := 'X'; -- startofpacket
sink2_endofpacket : in std_logic := 'X'; -- endofpacket
sink3_ready : out std_logic; -- ready
sink3_valid : in std_logic := 'X'; -- valid
sink3_channel : in std_logic_vector(6 downto 0) := (others => 'X'); -- channel
sink3_data : in std_logic_vector(69 downto 0) := (others => 'X'); -- data
sink3_startofpacket : in std_logic := 'X'; -- startofpacket
sink3_endofpacket : in std_logic := 'X'; -- endofpacket
sink4_ready : out std_logic; -- ready
sink4_valid : in std_logic := 'X'; -- valid
sink4_channel : in std_logic_vector(6 downto 0) := (others => 'X'); -- channel
sink4_data : in std_logic_vector(69 downto 0) := (others => 'X'); -- data
sink4_startofpacket : in std_logic := 'X'; -- startofpacket
sink4_endofpacket : in std_logic := 'X'; -- endofpacket
sink5_ready : out std_logic; -- ready
sink5_valid : in std_logic := 'X'; -- valid
sink5_channel : in std_logic_vector(6 downto 0) := (others => 'X'); -- channel
sink5_data : in std_logic_vector(69 downto 0) := (others => 'X'); -- data
sink5_startofpacket : in std_logic := 'X'; -- startofpacket
sink5_endofpacket : in std_logic := 'X'; -- endofpacket
sink6_ready : out std_logic; -- ready
sink6_valid : in std_logic := 'X'; -- valid
sink6_channel : in std_logic_vector(6 downto 0) := (others => 'X'); -- channel
sink6_data : in std_logic_vector(69 downto 0) := (others => 'X'); -- data
sink6_startofpacket : in std_logic := 'X'; -- startofpacket
sink6_endofpacket : in std_logic := 'X' -- endofpacket
);
end component cb20_rsp_xbar_mux;
component cb20_info_device_0_avalon_slave_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(16 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(4 downto 0); -- address
av_write : out std_logic; -- write
av_read : out std_logic; -- read
av_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(31 downto 0); -- writedata
av_byteenable : out std_logic_vector(3 downto 0); -- byteenable
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_writebyteenable : out std_logic_vector(3 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_chipselect : out std_logic; -- chipselect
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic; -- outputenable
uav_response : out std_logic_vector(1 downto 0); -- response
av_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response
uav_writeresponserequest : in std_logic := 'X'; -- writeresponserequest
uav_writeresponsevalid : out std_logic; -- writeresponsevalid
av_writeresponserequest : out std_logic; -- writeresponserequest
av_writeresponsevalid : in std_logic := 'X' -- writeresponsevalid
);
end component cb20_info_device_0_avalon_slave_translator;
component cb20_gpio_block_0_avalon_slave_0_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(16 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(3 downto 0); -- address
av_write : out std_logic; -- write
av_read : out std_logic; -- read
av_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(31 downto 0); -- writedata
av_byteenable : out std_logic_vector(3 downto 0); -- byteenable
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_writebyteenable : out std_logic_vector(3 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_chipselect : out std_logic; -- chipselect
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic; -- outputenable
uav_response : out std_logic_vector(1 downto 0); -- response
av_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response
uav_writeresponserequest : in std_logic := 'X'; -- writeresponserequest
uav_writeresponsevalid : out std_logic; -- writeresponsevalid
av_writeresponserequest : out std_logic; -- writeresponserequest
av_writeresponsevalid : in std_logic := 'X' -- writeresponsevalid
);
end component cb20_gpio_block_0_avalon_slave_0_translator;
component cb20_pwm_interface_0_avalon_slave_0_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(16 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(5 downto 0); -- address
av_write : out std_logic; -- write
av_read : out std_logic; -- read
av_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(31 downto 0); -- writedata
av_byteenable : out std_logic_vector(3 downto 0); -- byteenable
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_writebyteenable : out std_logic_vector(3 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_chipselect : out std_logic; -- chipselect
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic; -- outputenable
uav_response : out std_logic_vector(1 downto 0); -- response
av_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response
uav_writeresponserequest : in std_logic := 'X'; -- writeresponserequest
uav_writeresponsevalid : out std_logic; -- writeresponsevalid
av_writeresponserequest : out std_logic; -- writeresponserequest
av_writeresponsevalid : in std_logic := 'X' -- writeresponsevalid
);
end component cb20_pwm_interface_0_avalon_slave_0_translator;
component cb20_width_adapter is
generic (
IN_PKT_ADDR_H : integer := 60;
IN_PKT_ADDR_L : integer := 36;
IN_PKT_DATA_H : integer := 31;
IN_PKT_DATA_L : integer := 0;
IN_PKT_BYTEEN_H : integer := 35;
IN_PKT_BYTEEN_L : integer := 32;
IN_PKT_BYTE_CNT_H : integer := 63;
IN_PKT_BYTE_CNT_L : integer := 61;
IN_PKT_TRANS_COMPRESSED_READ : integer := 65;
IN_PKT_BURSTWRAP_H : integer := 67;
IN_PKT_BURSTWRAP_L : integer := 66;
IN_PKT_BURST_SIZE_H : integer := 70;
IN_PKT_BURST_SIZE_L : integer := 68;
IN_PKT_RESPONSE_STATUS_H : integer := 72;
IN_PKT_RESPONSE_STATUS_L : integer := 71;
IN_PKT_TRANS_EXCLUSIVE : integer := 73;
IN_PKT_BURST_TYPE_H : integer := 75;
IN_PKT_BURST_TYPE_L : integer := 74;
IN_ST_DATA_W : integer := 76;
OUT_PKT_ADDR_H : integer := 60;
OUT_PKT_ADDR_L : integer := 36;
OUT_PKT_DATA_H : integer := 31;
OUT_PKT_DATA_L : integer := 0;
OUT_PKT_BYTEEN_H : integer := 35;
OUT_PKT_BYTEEN_L : integer := 32;
OUT_PKT_BYTE_CNT_H : integer := 63;
OUT_PKT_BYTE_CNT_L : integer := 61;
OUT_PKT_TRANS_COMPRESSED_READ : integer := 65;
OUT_PKT_BURST_SIZE_H : integer := 68;
OUT_PKT_BURST_SIZE_L : integer := 66;
OUT_PKT_RESPONSE_STATUS_H : integer := 70;
OUT_PKT_RESPONSE_STATUS_L : integer := 69;
OUT_PKT_TRANS_EXCLUSIVE : integer := 71;
OUT_PKT_BURST_TYPE_H : integer := 73;
OUT_PKT_BURST_TYPE_L : integer := 72;
OUT_ST_DATA_W : integer := 74;
ST_CHANNEL_W : integer := 32;
OPTIMIZE_FOR_RSP : integer := 0;
RESPONSE_PATH : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
in_valid : in std_logic := 'X'; -- valid
in_channel : in std_logic_vector(6 downto 0) := (others => 'X'); -- channel
in_startofpacket : in std_logic := 'X'; -- startofpacket
in_endofpacket : in std_logic := 'X'; -- endofpacket
in_ready : out std_logic; -- ready
in_data : in std_logic_vector(69 downto 0) := (others => 'X'); -- data
out_endofpacket : out std_logic; -- endofpacket
out_data : out std_logic_vector(87 downto 0); -- data
out_channel : out std_logic_vector(6 downto 0); -- channel
out_valid : out std_logic; -- valid
out_ready : in std_logic := 'X'; -- ready
out_startofpacket : out std_logic; -- startofpacket
in_command_size_data : in std_logic_vector(2 downto 0) := (others => 'X') -- data
);
end component cb20_width_adapter;
component cb20_width_adapter_001 is
generic (
IN_PKT_ADDR_H : integer := 60;
IN_PKT_ADDR_L : integer := 36;
IN_PKT_DATA_H : integer := 31;
IN_PKT_DATA_L : integer := 0;
IN_PKT_BYTEEN_H : integer := 35;
IN_PKT_BYTEEN_L : integer := 32;
IN_PKT_BYTE_CNT_H : integer := 63;
IN_PKT_BYTE_CNT_L : integer := 61;
IN_PKT_TRANS_COMPRESSED_READ : integer := 65;
IN_PKT_BURSTWRAP_H : integer := 67;
IN_PKT_BURSTWRAP_L : integer := 66;
IN_PKT_BURST_SIZE_H : integer := 70;
IN_PKT_BURST_SIZE_L : integer := 68;
IN_PKT_RESPONSE_STATUS_H : integer := 72;
IN_PKT_RESPONSE_STATUS_L : integer := 71;
IN_PKT_TRANS_EXCLUSIVE : integer := 73;
IN_PKT_BURST_TYPE_H : integer := 75;
IN_PKT_BURST_TYPE_L : integer := 74;
IN_ST_DATA_W : integer := 76;
OUT_PKT_ADDR_H : integer := 60;
OUT_PKT_ADDR_L : integer := 36;
OUT_PKT_DATA_H : integer := 31;
OUT_PKT_DATA_L : integer := 0;
OUT_PKT_BYTEEN_H : integer := 35;
OUT_PKT_BYTEEN_L : integer := 32;
OUT_PKT_BYTE_CNT_H : integer := 63;
OUT_PKT_BYTE_CNT_L : integer := 61;
OUT_PKT_TRANS_COMPRESSED_READ : integer := 65;
OUT_PKT_BURST_SIZE_H : integer := 68;
OUT_PKT_BURST_SIZE_L : integer := 66;
OUT_PKT_RESPONSE_STATUS_H : integer := 70;
OUT_PKT_RESPONSE_STATUS_L : integer := 69;
OUT_PKT_TRANS_EXCLUSIVE : integer := 71;
OUT_PKT_BURST_TYPE_H : integer := 73;
OUT_PKT_BURST_TYPE_L : integer := 72;
OUT_ST_DATA_W : integer := 74;
ST_CHANNEL_W : integer := 32;
OPTIMIZE_FOR_RSP : integer := 0;
RESPONSE_PATH : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
in_valid : in std_logic := 'X'; -- valid
in_channel : in std_logic_vector(6 downto 0) := (others => 'X'); -- channel
in_startofpacket : in std_logic := 'X'; -- startofpacket
in_endofpacket : in std_logic := 'X'; -- endofpacket
in_ready : out std_logic; -- ready
in_data : in std_logic_vector(87 downto 0) := (others => 'X'); -- data
out_endofpacket : out std_logic; -- endofpacket
out_data : out std_logic_vector(69 downto 0); -- data
out_channel : out std_logic_vector(6 downto 0); -- channel
out_valid : out std_logic; -- valid
out_ready : in std_logic := 'X'; -- ready
out_startofpacket : out std_logic; -- startofpacket
in_command_size_data : in std_logic_vector(2 downto 0) := (others => 'X') -- data
);
end component cb20_width_adapter_001;
component cb20_gpio_block_0 is
generic (
number_of_gpios : integer := 1;
unique_id : std_logic_vector(31 downto 0) := "00000000000000000000000000000000"
);
port (
oslv_avs_read_data : out std_logic_vector(31 downto 0); -- readdata
islv_avs_address : in std_logic_vector(3 downto 0) := (others => 'X'); -- address
isl_avs_read : in std_logic := 'X'; -- read
isl_avs_write : in std_logic := 'X'; -- write
osl_avs_waitrequest : out std_logic; -- waitrequest
islv_avs_write_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
islv_avs_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
isl_clk : in std_logic := 'X'; -- clk
isl_reset_n : in std_logic := 'X'; -- reset_n
oslv_gpios : inout std_logic_vector(8 downto 0) := (others => 'X') -- export
);
end component cb20_gpio_block_0;
component cb20_gpio_block_1 is
generic (
number_of_gpios : integer := 1;
unique_id : std_logic_vector(31 downto 0) := "00000000000000000000000000000000"
);
port (
oslv_avs_read_data : out std_logic_vector(31 downto 0); -- readdata
islv_avs_address : in std_logic_vector(3 downto 0) := (others => 'X'); -- address
isl_avs_read : in std_logic := 'X'; -- read
isl_avs_write : in std_logic := 'X'; -- write
osl_avs_waitrequest : out std_logic; -- waitrequest
islv_avs_write_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
islv_avs_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
isl_clk : in std_logic := 'X'; -- clk
isl_reset_n : in std_logic := 'X'; -- reset_n
oslv_gpios : inout std_logic_vector(7 downto 0) := (others => 'X') -- export
);
end component cb20_gpio_block_1;
signal altpll_0_c0_clk : std_logic; -- altpll_0:c0 -> [EIM_Slave_to_Avalon_Master_0:isl_clk, EIM_Slave_to_Avalon_Master_0_avalon_master_translator:clk, EIM_Slave_to_Avalon_Master_0_avalon_master_translator_avalon_universal_master_0_agent:clk, addr_router:clk, cmd_xbar_demux:clk, dacad5668_0:isl_clk, dacad5668_0_avalon_slave_translator:clk, dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:clk, dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, fqd_interface_0:isl_clk, fqd_interface_0_avalon_slave_0_translator:clk, fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:clk, fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, gpio_block_0:isl_clk, gpio_block_0_avalon_slave_0_translator:clk, gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:clk, gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, gpio_block_1:isl_clk, gpio_block_1_avalon_slave_0_translator:clk, gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:clk, gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, id_router:clk, id_router_001:clk, id_router_002:clk, id_router_003:clk, id_router_004:clk, id_router_005:clk, id_router_006:clk, info_device_0:isl_clk, info_device_0_avalon_slave_translator:clk, info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:clk, info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, mpu9250_0:isl_clk, mpu9250_0_avalon_slave_0_translator:clk, mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:clk, mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, pwm_interface_0:isl_clk, pwm_interface_0_avalon_slave_0_translator:clk, pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:clk, pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, rsp_xbar_demux:clk, rsp_xbar_demux_001:clk, rsp_xbar_demux_002:clk, rsp_xbar_demux_003:clk, rsp_xbar_demux_004:clk, rsp_xbar_demux_005:clk, rsp_xbar_demux_006:clk, rsp_xbar_mux:clk, rst_controller_001:clk, width_adapter:clk, width_adapter_001:clk, width_adapter_002:clk, width_adapter_003:clk, width_adapter_004:clk, width_adapter_005:clk, width_adapter_006:clk, width_adapter_007:clk, width_adapter_008:clk, width_adapter_009:clk, width_adapter_010:clk, width_adapter_011:clk, width_adapter_012:clk, width_adapter_013:clk]
signal eim_slave_to_avalon_master_0_avalon_master_waitrequest : std_logic; -- EIM_Slave_to_Avalon_Master_0_avalon_master_translator:av_waitrequest -> EIM_Slave_to_Avalon_Master_0:islv_waitrequest
signal eim_slave_to_avalon_master_0_avalon_master_writedata : std_logic_vector(15 downto 0); -- EIM_Slave_to_Avalon_Master_0:oslv_writedata -> EIM_Slave_to_Avalon_Master_0_avalon_master_translator:av_writedata
signal eim_slave_to_avalon_master_0_avalon_master_address : std_logic_vector(15 downto 0); -- EIM_Slave_to_Avalon_Master_0:oslv_address -> EIM_Slave_to_Avalon_Master_0_avalon_master_translator:av_address
signal eim_slave_to_avalon_master_0_avalon_master_write : std_logic; -- EIM_Slave_to_Avalon_Master_0:oslv_write -> EIM_Slave_to_Avalon_Master_0_avalon_master_translator:av_write
signal eim_slave_to_avalon_master_0_avalon_master_read : std_logic; -- EIM_Slave_to_Avalon_Master_0:oslv_read -> EIM_Slave_to_Avalon_Master_0_avalon_master_translator:av_read
signal eim_slave_to_avalon_master_0_avalon_master_readdata : std_logic_vector(15 downto 0); -- EIM_Slave_to_Avalon_Master_0_avalon_master_translator:av_readdata -> EIM_Slave_to_Avalon_Master_0:islv_readdata
signal info_device_0_avalon_slave_translator_avalon_anti_slave_0_waitrequest : std_logic; -- info_device_0:osl_avs_waitrequest -> info_device_0_avalon_slave_translator:av_waitrequest
signal info_device_0_avalon_slave_translator_avalon_anti_slave_0_writedata : std_logic_vector(31 downto 0); -- info_device_0_avalon_slave_translator:av_writedata -> info_device_0:islv_avs_write_data
signal info_device_0_avalon_slave_translator_avalon_anti_slave_0_address : std_logic_vector(4 downto 0); -- info_device_0_avalon_slave_translator:av_address -> info_device_0:islv_avs_address
signal info_device_0_avalon_slave_translator_avalon_anti_slave_0_write : std_logic; -- info_device_0_avalon_slave_translator:av_write -> info_device_0:isl_avs_write
signal info_device_0_avalon_slave_translator_avalon_anti_slave_0_read : std_logic; -- info_device_0_avalon_slave_translator:av_read -> info_device_0:isl_avs_read
signal info_device_0_avalon_slave_translator_avalon_anti_slave_0_readdata : std_logic_vector(31 downto 0); -- info_device_0:oslv_avs_read_data -> info_device_0_avalon_slave_translator:av_readdata
signal info_device_0_avalon_slave_translator_avalon_anti_slave_0_byteenable : std_logic_vector(3 downto 0); -- info_device_0_avalon_slave_translator:av_byteenable -> info_device_0:islv_avs_byteenable
signal dacad5668_0_avalon_slave_translator_avalon_anti_slave_0_waitrequest : std_logic; -- dacad5668_0:osl_avs_waitrequest -> dacad5668_0_avalon_slave_translator:av_waitrequest
signal dacad5668_0_avalon_slave_translator_avalon_anti_slave_0_writedata : std_logic_vector(31 downto 0); -- dacad5668_0_avalon_slave_translator:av_writedata -> dacad5668_0:islv_avs_write_data
signal dacad5668_0_avalon_slave_translator_avalon_anti_slave_0_address : std_logic_vector(4 downto 0); -- dacad5668_0_avalon_slave_translator:av_address -> dacad5668_0:islv_avs_address
signal dacad5668_0_avalon_slave_translator_avalon_anti_slave_0_write : std_logic; -- dacad5668_0_avalon_slave_translator:av_write -> dacad5668_0:isl_avs_write
signal dacad5668_0_avalon_slave_translator_avalon_anti_slave_0_read : std_logic; -- dacad5668_0_avalon_slave_translator:av_read -> dacad5668_0:isl_avs_read
signal dacad5668_0_avalon_slave_translator_avalon_anti_slave_0_readdata : std_logic_vector(31 downto 0); -- dacad5668_0:oslv_avs_read_data -> dacad5668_0_avalon_slave_translator:av_readdata
signal dacad5668_0_avalon_slave_translator_avalon_anti_slave_0_byteenable : std_logic_vector(3 downto 0); -- dacad5668_0_avalon_slave_translator:av_byteenable -> dacad5668_0:islv_avs_byteenable
signal fqd_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_waitrequest : std_logic; -- fqd_interface_0:osl_avs_waitrequest -> fqd_interface_0_avalon_slave_0_translator:av_waitrequest
signal fqd_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_writedata : std_logic_vector(31 downto 0); -- fqd_interface_0_avalon_slave_0_translator:av_writedata -> fqd_interface_0:islv_avs_write_data
signal fqd_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_address : std_logic_vector(4 downto 0); -- fqd_interface_0_avalon_slave_0_translator:av_address -> fqd_interface_0:islv_avs_address
signal fqd_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_write : std_logic; -- fqd_interface_0_avalon_slave_0_translator:av_write -> fqd_interface_0:isl_avs_write
signal fqd_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_read : std_logic; -- fqd_interface_0_avalon_slave_0_translator:av_read -> fqd_interface_0:isl_avs_read
signal fqd_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_readdata : std_logic_vector(31 downto 0); -- fqd_interface_0:oslv_avs_read_data -> fqd_interface_0_avalon_slave_0_translator:av_readdata
signal fqd_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_byteenable : std_logic_vector(3 downto 0); -- fqd_interface_0_avalon_slave_0_translator:av_byteenable -> fqd_interface_0:islv_avs_byteenable
signal gpio_block_0_avalon_slave_0_translator_avalon_anti_slave_0_waitrequest : std_logic; -- gpio_block_0:osl_avs_waitrequest -> gpio_block_0_avalon_slave_0_translator:av_waitrequest
signal gpio_block_0_avalon_slave_0_translator_avalon_anti_slave_0_writedata : std_logic_vector(31 downto 0); -- gpio_block_0_avalon_slave_0_translator:av_writedata -> gpio_block_0:islv_avs_write_data
signal gpio_block_0_avalon_slave_0_translator_avalon_anti_slave_0_address : std_logic_vector(3 downto 0); -- gpio_block_0_avalon_slave_0_translator:av_address -> gpio_block_0:islv_avs_address
signal gpio_block_0_avalon_slave_0_translator_avalon_anti_slave_0_write : std_logic; -- gpio_block_0_avalon_slave_0_translator:av_write -> gpio_block_0:isl_avs_write
signal gpio_block_0_avalon_slave_0_translator_avalon_anti_slave_0_read : std_logic; -- gpio_block_0_avalon_slave_0_translator:av_read -> gpio_block_0:isl_avs_read
signal gpio_block_0_avalon_slave_0_translator_avalon_anti_slave_0_readdata : std_logic_vector(31 downto 0); -- gpio_block_0:oslv_avs_read_data -> gpio_block_0_avalon_slave_0_translator:av_readdata
signal gpio_block_0_avalon_slave_0_translator_avalon_anti_slave_0_byteenable : std_logic_vector(3 downto 0); -- gpio_block_0_avalon_slave_0_translator:av_byteenable -> gpio_block_0:islv_avs_byteenable
signal pwm_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_waitrequest : std_logic; -- pwm_interface_0:osl_avs_waitrequest -> pwm_interface_0_avalon_slave_0_translator:av_waitrequest
signal pwm_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_writedata : std_logic_vector(31 downto 0); -- pwm_interface_0_avalon_slave_0_translator:av_writedata -> pwm_interface_0:islv_avs_write_data
signal pwm_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_address : std_logic_vector(5 downto 0); -- pwm_interface_0_avalon_slave_0_translator:av_address -> pwm_interface_0:islv_avs_address
signal pwm_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_write : std_logic; -- pwm_interface_0_avalon_slave_0_translator:av_write -> pwm_interface_0:isl_avs_write
signal pwm_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_read : std_logic; -- pwm_interface_0_avalon_slave_0_translator:av_read -> pwm_interface_0:isl_avs_read
signal pwm_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_readdata : std_logic_vector(31 downto 0); -- pwm_interface_0:oslv_avs_read_data -> pwm_interface_0_avalon_slave_0_translator:av_readdata
signal pwm_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_byteenable : std_logic_vector(3 downto 0); -- pwm_interface_0_avalon_slave_0_translator:av_byteenable -> pwm_interface_0:islv_avs_byteenable
signal gpio_block_1_avalon_slave_0_translator_avalon_anti_slave_0_waitrequest : std_logic; -- gpio_block_1:osl_avs_waitrequest -> gpio_block_1_avalon_slave_0_translator:av_waitrequest
signal gpio_block_1_avalon_slave_0_translator_avalon_anti_slave_0_writedata : std_logic_vector(31 downto 0); -- gpio_block_1_avalon_slave_0_translator:av_writedata -> gpio_block_1:islv_avs_write_data
signal gpio_block_1_avalon_slave_0_translator_avalon_anti_slave_0_address : std_logic_vector(3 downto 0); -- gpio_block_1_avalon_slave_0_translator:av_address -> gpio_block_1:islv_avs_address
signal gpio_block_1_avalon_slave_0_translator_avalon_anti_slave_0_write : std_logic; -- gpio_block_1_avalon_slave_0_translator:av_write -> gpio_block_1:isl_avs_write
signal gpio_block_1_avalon_slave_0_translator_avalon_anti_slave_0_read : std_logic; -- gpio_block_1_avalon_slave_0_translator:av_read -> gpio_block_1:isl_avs_read
signal gpio_block_1_avalon_slave_0_translator_avalon_anti_slave_0_readdata : std_logic_vector(31 downto 0); -- gpio_block_1:oslv_avs_read_data -> gpio_block_1_avalon_slave_0_translator:av_readdata
signal gpio_block_1_avalon_slave_0_translator_avalon_anti_slave_0_byteenable : std_logic_vector(3 downto 0); -- gpio_block_1_avalon_slave_0_translator:av_byteenable -> gpio_block_1:islv_avs_byteenable
signal mpu9250_0_avalon_slave_0_translator_avalon_anti_slave_0_waitrequest : std_logic; -- mpu9250_0:osl_avs_waitrequest -> mpu9250_0_avalon_slave_0_translator:av_waitrequest
signal mpu9250_0_avalon_slave_0_translator_avalon_anti_slave_0_writedata : std_logic_vector(31 downto 0); -- mpu9250_0_avalon_slave_0_translator:av_writedata -> mpu9250_0:islv_avs_write_data
signal mpu9250_0_avalon_slave_0_translator_avalon_anti_slave_0_address : std_logic_vector(4 downto 0); -- mpu9250_0_avalon_slave_0_translator:av_address -> mpu9250_0:islv_avs_address
signal mpu9250_0_avalon_slave_0_translator_avalon_anti_slave_0_write : std_logic; -- mpu9250_0_avalon_slave_0_translator:av_write -> mpu9250_0:isl_avs_write
signal mpu9250_0_avalon_slave_0_translator_avalon_anti_slave_0_read : std_logic; -- mpu9250_0_avalon_slave_0_translator:av_read -> mpu9250_0:isl_avs_read
signal mpu9250_0_avalon_slave_0_translator_avalon_anti_slave_0_readdata : std_logic_vector(31 downto 0); -- mpu9250_0:oslv_avs_read_data -> mpu9250_0_avalon_slave_0_translator:av_readdata
signal mpu9250_0_avalon_slave_0_translator_avalon_anti_slave_0_byteenable : std_logic_vector(3 downto 0); -- mpu9250_0_avalon_slave_0_translator:av_byteenable -> mpu9250_0:islv_avs_byteenable
signal eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_waitrequest : std_logic; -- EIM_Slave_to_Avalon_Master_0_avalon_master_translator_avalon_universal_master_0_agent:av_waitrequest -> EIM_Slave_to_Avalon_Master_0_avalon_master_translator:uav_waitrequest
signal eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_burstcount : std_logic_vector(1 downto 0); -- EIM_Slave_to_Avalon_Master_0_avalon_master_translator:uav_burstcount -> EIM_Slave_to_Avalon_Master_0_avalon_master_translator_avalon_universal_master_0_agent:av_burstcount
signal eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_writedata : std_logic_vector(15 downto 0); -- EIM_Slave_to_Avalon_Master_0_avalon_master_translator:uav_writedata -> EIM_Slave_to_Avalon_Master_0_avalon_master_translator_avalon_universal_master_0_agent:av_writedata
signal eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_address : std_logic_vector(16 downto 0); -- EIM_Slave_to_Avalon_Master_0_avalon_master_translator:uav_address -> EIM_Slave_to_Avalon_Master_0_avalon_master_translator_avalon_universal_master_0_agent:av_address
signal eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_lock : std_logic; -- EIM_Slave_to_Avalon_Master_0_avalon_master_translator:uav_lock -> EIM_Slave_to_Avalon_Master_0_avalon_master_translator_avalon_universal_master_0_agent:av_lock
signal eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_write : std_logic; -- EIM_Slave_to_Avalon_Master_0_avalon_master_translator:uav_write -> EIM_Slave_to_Avalon_Master_0_avalon_master_translator_avalon_universal_master_0_agent:av_write
signal eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_read : std_logic; -- EIM_Slave_to_Avalon_Master_0_avalon_master_translator:uav_read -> EIM_Slave_to_Avalon_Master_0_avalon_master_translator_avalon_universal_master_0_agent:av_read
signal eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_readdata : std_logic_vector(15 downto 0); -- EIM_Slave_to_Avalon_Master_0_avalon_master_translator_avalon_universal_master_0_agent:av_readdata -> EIM_Slave_to_Avalon_Master_0_avalon_master_translator:uav_readdata
signal eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_debugaccess : std_logic; -- EIM_Slave_to_Avalon_Master_0_avalon_master_translator:uav_debugaccess -> EIM_Slave_to_Avalon_Master_0_avalon_master_translator_avalon_universal_master_0_agent:av_debugaccess
signal eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_byteenable : std_logic_vector(1 downto 0); -- EIM_Slave_to_Avalon_Master_0_avalon_master_translator:uav_byteenable -> EIM_Slave_to_Avalon_Master_0_avalon_master_translator_avalon_universal_master_0_agent:av_byteenable
signal eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_readdatavalid : std_logic; -- EIM_Slave_to_Avalon_Master_0_avalon_master_translator_avalon_universal_master_0_agent:av_readdatavalid -> EIM_Slave_to_Avalon_Master_0_avalon_master_translator:uav_readdatavalid
signal info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- info_device_0_avalon_slave_translator:uav_waitrequest -> info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest
signal info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(2 downto 0); -- info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> info_device_0_avalon_slave_translator:uav_burstcount
signal info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(31 downto 0); -- info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> info_device_0_avalon_slave_translator:uav_writedata
signal info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(16 downto 0); -- info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:m0_address -> info_device_0_avalon_slave_translator:uav_address
signal info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:m0_write -> info_device_0_avalon_slave_translator:uav_write
signal info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:m0_lock -> info_device_0_avalon_slave_translator:uav_lock
signal info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:m0_read -> info_device_0_avalon_slave_translator:uav_read
signal info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(31 downto 0); -- info_device_0_avalon_slave_translator:uav_readdata -> info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:m0_readdata
signal info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- info_device_0_avalon_slave_translator:uav_readdatavalid -> info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid
signal info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> info_device_0_avalon_slave_translator:uav_debugaccess
signal info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(3 downto 0); -- info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> info_device_0_avalon_slave_translator:uav_byteenable
signal info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
signal info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
signal info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
signal info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(88 downto 0); -- info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
signal info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:rf_source_ready
signal info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
signal info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid
signal info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
signal info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(88 downto 0); -- info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:rf_sink_data
signal info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
signal info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
signal info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(33 downto 0); -- info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
signal info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
signal dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- dacad5668_0_avalon_slave_translator:uav_waitrequest -> dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest
signal dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(2 downto 0); -- dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> dacad5668_0_avalon_slave_translator:uav_burstcount
signal dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(31 downto 0); -- dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> dacad5668_0_avalon_slave_translator:uav_writedata
signal dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(16 downto 0); -- dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:m0_address -> dacad5668_0_avalon_slave_translator:uav_address
signal dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:m0_write -> dacad5668_0_avalon_slave_translator:uav_write
signal dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:m0_lock -> dacad5668_0_avalon_slave_translator:uav_lock
signal dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:m0_read -> dacad5668_0_avalon_slave_translator:uav_read
signal dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(31 downto 0); -- dacad5668_0_avalon_slave_translator:uav_readdata -> dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:m0_readdata
signal dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- dacad5668_0_avalon_slave_translator:uav_readdatavalid -> dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid
signal dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> dacad5668_0_avalon_slave_translator:uav_debugaccess
signal dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(3 downto 0); -- dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> dacad5668_0_avalon_slave_translator:uav_byteenable
signal dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
signal dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
signal dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
signal dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(88 downto 0); -- dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
signal dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:rf_source_ready
signal dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
signal dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid
signal dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
signal dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(88 downto 0); -- dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:rf_sink_data
signal dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
signal dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
signal dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(33 downto 0); -- dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
signal dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
signal fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- fqd_interface_0_avalon_slave_0_translator:uav_waitrequest -> fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_waitrequest
signal fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(2 downto 0); -- fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_burstcount -> fqd_interface_0_avalon_slave_0_translator:uav_burstcount
signal fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(31 downto 0); -- fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_writedata -> fqd_interface_0_avalon_slave_0_translator:uav_writedata
signal fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(16 downto 0); -- fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_address -> fqd_interface_0_avalon_slave_0_translator:uav_address
signal fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_write -> fqd_interface_0_avalon_slave_0_translator:uav_write
signal fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_lock -> fqd_interface_0_avalon_slave_0_translator:uav_lock
signal fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_read -> fqd_interface_0_avalon_slave_0_translator:uav_read
signal fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(31 downto 0); -- fqd_interface_0_avalon_slave_0_translator:uav_readdata -> fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_readdata
signal fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- fqd_interface_0_avalon_slave_0_translator:uav_readdatavalid -> fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_readdatavalid
signal fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_debugaccess -> fqd_interface_0_avalon_slave_0_translator:uav_debugaccess
signal fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(3 downto 0); -- fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_byteenable -> fqd_interface_0_avalon_slave_0_translator:uav_byteenable
signal fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
signal fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_valid -> fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
signal fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
signal fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(88 downto 0); -- fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_data -> fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
signal fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_ready
signal fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
signal fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_valid
signal fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
signal fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(88 downto 0); -- fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_data
signal fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_ready -> fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
signal fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
signal fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(33 downto 0); -- fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
signal fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
signal gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- gpio_block_0_avalon_slave_0_translator:uav_waitrequest -> gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_waitrequest
signal gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(2 downto 0); -- gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_burstcount -> gpio_block_0_avalon_slave_0_translator:uav_burstcount
signal gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(31 downto 0); -- gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_writedata -> gpio_block_0_avalon_slave_0_translator:uav_writedata
signal gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(16 downto 0); -- gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_address -> gpio_block_0_avalon_slave_0_translator:uav_address
signal gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_write -> gpio_block_0_avalon_slave_0_translator:uav_write
signal gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_lock -> gpio_block_0_avalon_slave_0_translator:uav_lock
signal gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_read -> gpio_block_0_avalon_slave_0_translator:uav_read
signal gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(31 downto 0); -- gpio_block_0_avalon_slave_0_translator:uav_readdata -> gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_readdata
signal gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- gpio_block_0_avalon_slave_0_translator:uav_readdatavalid -> gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_readdatavalid
signal gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_debugaccess -> gpio_block_0_avalon_slave_0_translator:uav_debugaccess
signal gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(3 downto 0); -- gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_byteenable -> gpio_block_0_avalon_slave_0_translator:uav_byteenable
signal gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
signal gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_valid -> gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
signal gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
signal gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(88 downto 0); -- gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_data -> gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
signal gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_ready
signal gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
signal gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_valid
signal gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
signal gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(88 downto 0); -- gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_data
signal gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_ready -> gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
signal gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
signal gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(33 downto 0); -- gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
signal gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
signal pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- pwm_interface_0_avalon_slave_0_translator:uav_waitrequest -> pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_waitrequest
signal pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(2 downto 0); -- pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_burstcount -> pwm_interface_0_avalon_slave_0_translator:uav_burstcount
signal pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(31 downto 0); -- pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_writedata -> pwm_interface_0_avalon_slave_0_translator:uav_writedata
signal pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(16 downto 0); -- pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_address -> pwm_interface_0_avalon_slave_0_translator:uav_address
signal pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_write -> pwm_interface_0_avalon_slave_0_translator:uav_write
signal pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_lock -> pwm_interface_0_avalon_slave_0_translator:uav_lock
signal pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_read -> pwm_interface_0_avalon_slave_0_translator:uav_read
signal pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(31 downto 0); -- pwm_interface_0_avalon_slave_0_translator:uav_readdata -> pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_readdata
signal pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- pwm_interface_0_avalon_slave_0_translator:uav_readdatavalid -> pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_readdatavalid
signal pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_debugaccess -> pwm_interface_0_avalon_slave_0_translator:uav_debugaccess
signal pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(3 downto 0); -- pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_byteenable -> pwm_interface_0_avalon_slave_0_translator:uav_byteenable
signal pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
signal pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_valid -> pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
signal pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
signal pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(88 downto 0); -- pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_data -> pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
signal pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_ready
signal pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
signal pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_valid
signal pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
signal pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(88 downto 0); -- pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_data
signal pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_ready -> pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
signal pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
signal pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(33 downto 0); -- pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
signal pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
signal gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- gpio_block_1_avalon_slave_0_translator:uav_waitrequest -> gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_waitrequest
signal gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(2 downto 0); -- gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_burstcount -> gpio_block_1_avalon_slave_0_translator:uav_burstcount
signal gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(31 downto 0); -- gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_writedata -> gpio_block_1_avalon_slave_0_translator:uav_writedata
signal gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(16 downto 0); -- gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_address -> gpio_block_1_avalon_slave_0_translator:uav_address
signal gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_write -> gpio_block_1_avalon_slave_0_translator:uav_write
signal gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_lock -> gpio_block_1_avalon_slave_0_translator:uav_lock
signal gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_read -> gpio_block_1_avalon_slave_0_translator:uav_read
signal gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(31 downto 0); -- gpio_block_1_avalon_slave_0_translator:uav_readdata -> gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_readdata
signal gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- gpio_block_1_avalon_slave_0_translator:uav_readdatavalid -> gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_readdatavalid
signal gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_debugaccess -> gpio_block_1_avalon_slave_0_translator:uav_debugaccess
signal gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(3 downto 0); -- gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_byteenable -> gpio_block_1_avalon_slave_0_translator:uav_byteenable
signal gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
signal gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_valid -> gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
signal gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
signal gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(88 downto 0); -- gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_data -> gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
signal gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_ready
signal gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
signal gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_valid
signal gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
signal gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(88 downto 0); -- gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_data
signal gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_ready -> gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
signal gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
signal gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(33 downto 0); -- gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
signal gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
signal mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- mpu9250_0_avalon_slave_0_translator:uav_waitrequest -> mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_waitrequest
signal mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(2 downto 0); -- mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_burstcount -> mpu9250_0_avalon_slave_0_translator:uav_burstcount
signal mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(31 downto 0); -- mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_writedata -> mpu9250_0_avalon_slave_0_translator:uav_writedata
signal mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(16 downto 0); -- mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_address -> mpu9250_0_avalon_slave_0_translator:uav_address
signal mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_write -> mpu9250_0_avalon_slave_0_translator:uav_write
signal mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_lock -> mpu9250_0_avalon_slave_0_translator:uav_lock
signal mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_read -> mpu9250_0_avalon_slave_0_translator:uav_read
signal mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(31 downto 0); -- mpu9250_0_avalon_slave_0_translator:uav_readdata -> mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_readdata
signal mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- mpu9250_0_avalon_slave_0_translator:uav_readdatavalid -> mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_readdatavalid
signal mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_debugaccess -> mpu9250_0_avalon_slave_0_translator:uav_debugaccess
signal mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(3 downto 0); -- mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_byteenable -> mpu9250_0_avalon_slave_0_translator:uav_byteenable
signal mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
signal mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_valid -> mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
signal mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
signal mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(88 downto 0); -- mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_data -> mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
signal mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_ready
signal mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
signal mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_valid
signal mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
signal mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(88 downto 0); -- mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_data
signal mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_ready -> mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
signal mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
signal mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(33 downto 0); -- mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
signal mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
signal eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_agent_cp_endofpacket : std_logic; -- EIM_Slave_to_Avalon_Master_0_avalon_master_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router:sink_endofpacket
signal eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_agent_cp_valid : std_logic; -- EIM_Slave_to_Avalon_Master_0_avalon_master_translator_avalon_universal_master_0_agent:cp_valid -> addr_router:sink_valid
signal eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_agent_cp_startofpacket : std_logic; -- EIM_Slave_to_Avalon_Master_0_avalon_master_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router:sink_startofpacket
signal eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_agent_cp_data : std_logic_vector(69 downto 0); -- EIM_Slave_to_Avalon_Master_0_avalon_master_translator_avalon_universal_master_0_agent:cp_data -> addr_router:sink_data
signal eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_agent_cp_ready : std_logic; -- addr_router:sink_ready -> EIM_Slave_to_Avalon_Master_0_avalon_master_translator_avalon_universal_master_0_agent:cp_ready
signal info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router:sink_endofpacket
signal info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router:sink_valid
signal info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router:sink_startofpacket
signal info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(87 downto 0); -- info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router:sink_data
signal info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router:sink_ready -> info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:rp_ready
signal dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_001:sink_endofpacket
signal dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_001:sink_valid
signal dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_001:sink_startofpacket
signal dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(87 downto 0); -- dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_001:sink_data
signal dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_001:sink_ready -> dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:rp_ready
signal fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_002:sink_endofpacket
signal fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_002:sink_valid
signal fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_002:sink_startofpacket
signal fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(87 downto 0); -- fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_data -> id_router_002:sink_data
signal fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_002:sink_ready -> fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_ready
signal gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_003:sink_endofpacket
signal gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_003:sink_valid
signal gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_003:sink_startofpacket
signal gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(87 downto 0); -- gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_data -> id_router_003:sink_data
signal gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_003:sink_ready -> gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_ready
signal pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_004:sink_endofpacket
signal pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_004:sink_valid
signal pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_004:sink_startofpacket
signal pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(87 downto 0); -- pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_data -> id_router_004:sink_data
signal pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_004:sink_ready -> pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_ready
signal gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_005:sink_endofpacket
signal gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_005:sink_valid
signal gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_005:sink_startofpacket
signal gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(87 downto 0); -- gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_data -> id_router_005:sink_data
signal gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_005:sink_ready -> gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_ready
signal mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_006:sink_endofpacket
signal mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_006:sink_valid
signal mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_006:sink_startofpacket
signal mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(87 downto 0); -- mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_data -> id_router_006:sink_data
signal mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_006:sink_ready -> mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_ready
signal rst_controller_reset_out_reset : std_logic; -- rst_controller:reset_out -> altpll_0:reset
signal rst_controller_001_reset_out_reset : std_logic; -- rst_controller_001:reset_out -> [EIM_Slave_to_Avalon_Master_0_avalon_master_translator:reset, EIM_Slave_to_Avalon_Master_0_avalon_master_translator_avalon_universal_master_0_agent:reset, addr_router:reset, cmd_xbar_demux:reset, dacad5668_0_avalon_slave_translator:reset, dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:reset, dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, fqd_interface_0_avalon_slave_0_translator:reset, fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:reset, fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, gpio_block_0_avalon_slave_0_translator:reset, gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:reset, gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, gpio_block_1_avalon_slave_0_translator:reset, gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:reset, gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, id_router:reset, id_router_001:reset, id_router_002:reset, id_router_003:reset, id_router_004:reset, id_router_005:reset, id_router_006:reset, info_device_0_avalon_slave_translator:reset, info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:reset, info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, mpu9250_0_avalon_slave_0_translator:reset, mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:reset, mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, pwm_interface_0_avalon_slave_0_translator:reset, pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:reset, pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, rsp_xbar_demux:reset, rsp_xbar_demux_001:reset, rsp_xbar_demux_002:reset, rsp_xbar_demux_003:reset, rsp_xbar_demux_004:reset, rsp_xbar_demux_005:reset, rsp_xbar_demux_006:reset, rsp_xbar_mux:reset, rst_controller_001_reset_out_reset:in, width_adapter:reset, width_adapter_001:reset, width_adapter_002:reset, width_adapter_003:reset, width_adapter_004:reset, width_adapter_005:reset, width_adapter_006:reset, width_adapter_007:reset, width_adapter_008:reset, width_adapter_009:reset, width_adapter_010:reset, width_adapter_011:reset, width_adapter_012:reset, width_adapter_013:reset]
signal cmd_xbar_demux_src0_endofpacket : std_logic; -- cmd_xbar_demux:src0_endofpacket -> width_adapter:in_endofpacket
signal cmd_xbar_demux_src0_valid : std_logic; -- cmd_xbar_demux:src0_valid -> width_adapter:in_valid
signal cmd_xbar_demux_src0_startofpacket : std_logic; -- cmd_xbar_demux:src0_startofpacket -> width_adapter:in_startofpacket
signal cmd_xbar_demux_src0_data : std_logic_vector(69 downto 0); -- cmd_xbar_demux:src0_data -> width_adapter:in_data
signal cmd_xbar_demux_src0_channel : std_logic_vector(6 downto 0); -- cmd_xbar_demux:src0_channel -> width_adapter:in_channel
signal cmd_xbar_demux_src1_endofpacket : std_logic; -- cmd_xbar_demux:src1_endofpacket -> width_adapter_002:in_endofpacket
signal cmd_xbar_demux_src1_valid : std_logic; -- cmd_xbar_demux:src1_valid -> width_adapter_002:in_valid
signal cmd_xbar_demux_src1_startofpacket : std_logic; -- cmd_xbar_demux:src1_startofpacket -> width_adapter_002:in_startofpacket
signal cmd_xbar_demux_src1_data : std_logic_vector(69 downto 0); -- cmd_xbar_demux:src1_data -> width_adapter_002:in_data
signal cmd_xbar_demux_src1_channel : std_logic_vector(6 downto 0); -- cmd_xbar_demux:src1_channel -> width_adapter_002:in_channel
signal cmd_xbar_demux_src2_endofpacket : std_logic; -- cmd_xbar_demux:src2_endofpacket -> width_adapter_004:in_endofpacket
signal cmd_xbar_demux_src2_valid : std_logic; -- cmd_xbar_demux:src2_valid -> width_adapter_004:in_valid
signal cmd_xbar_demux_src2_startofpacket : std_logic; -- cmd_xbar_demux:src2_startofpacket -> width_adapter_004:in_startofpacket
signal cmd_xbar_demux_src2_data : std_logic_vector(69 downto 0); -- cmd_xbar_demux:src2_data -> width_adapter_004:in_data
signal cmd_xbar_demux_src2_channel : std_logic_vector(6 downto 0); -- cmd_xbar_demux:src2_channel -> width_adapter_004:in_channel
signal cmd_xbar_demux_src3_endofpacket : std_logic; -- cmd_xbar_demux:src3_endofpacket -> width_adapter_006:in_endofpacket
signal cmd_xbar_demux_src3_valid : std_logic; -- cmd_xbar_demux:src3_valid -> width_adapter_006:in_valid
signal cmd_xbar_demux_src3_startofpacket : std_logic; -- cmd_xbar_demux:src3_startofpacket -> width_adapter_006:in_startofpacket
signal cmd_xbar_demux_src3_data : std_logic_vector(69 downto 0); -- cmd_xbar_demux:src3_data -> width_adapter_006:in_data
signal cmd_xbar_demux_src3_channel : std_logic_vector(6 downto 0); -- cmd_xbar_demux:src3_channel -> width_adapter_006:in_channel
signal cmd_xbar_demux_src4_endofpacket : std_logic; -- cmd_xbar_demux:src4_endofpacket -> width_adapter_008:in_endofpacket
signal cmd_xbar_demux_src4_valid : std_logic; -- cmd_xbar_demux:src4_valid -> width_adapter_008:in_valid
signal cmd_xbar_demux_src4_startofpacket : std_logic; -- cmd_xbar_demux:src4_startofpacket -> width_adapter_008:in_startofpacket
signal cmd_xbar_demux_src4_data : std_logic_vector(69 downto 0); -- cmd_xbar_demux:src4_data -> width_adapter_008:in_data
signal cmd_xbar_demux_src4_channel : std_logic_vector(6 downto 0); -- cmd_xbar_demux:src4_channel -> width_adapter_008:in_channel
signal cmd_xbar_demux_src5_endofpacket : std_logic; -- cmd_xbar_demux:src5_endofpacket -> width_adapter_010:in_endofpacket
signal cmd_xbar_demux_src5_valid : std_logic; -- cmd_xbar_demux:src5_valid -> width_adapter_010:in_valid
signal cmd_xbar_demux_src5_startofpacket : std_logic; -- cmd_xbar_demux:src5_startofpacket -> width_adapter_010:in_startofpacket
signal cmd_xbar_demux_src5_data : std_logic_vector(69 downto 0); -- cmd_xbar_demux:src5_data -> width_adapter_010:in_data
signal cmd_xbar_demux_src5_channel : std_logic_vector(6 downto 0); -- cmd_xbar_demux:src5_channel -> width_adapter_010:in_channel
signal cmd_xbar_demux_src6_endofpacket : std_logic; -- cmd_xbar_demux:src6_endofpacket -> width_adapter_012:in_endofpacket
signal cmd_xbar_demux_src6_valid : std_logic; -- cmd_xbar_demux:src6_valid -> width_adapter_012:in_valid
signal cmd_xbar_demux_src6_startofpacket : std_logic; -- cmd_xbar_demux:src6_startofpacket -> width_adapter_012:in_startofpacket
signal cmd_xbar_demux_src6_data : std_logic_vector(69 downto 0); -- cmd_xbar_demux:src6_data -> width_adapter_012:in_data
signal cmd_xbar_demux_src6_channel : std_logic_vector(6 downto 0); -- cmd_xbar_demux:src6_channel -> width_adapter_012:in_channel
signal rsp_xbar_demux_src0_endofpacket : std_logic; -- rsp_xbar_demux:src0_endofpacket -> rsp_xbar_mux:sink0_endofpacket
signal rsp_xbar_demux_src0_valid : std_logic; -- rsp_xbar_demux:src0_valid -> rsp_xbar_mux:sink0_valid
signal rsp_xbar_demux_src0_startofpacket : std_logic; -- rsp_xbar_demux:src0_startofpacket -> rsp_xbar_mux:sink0_startofpacket
signal rsp_xbar_demux_src0_data : std_logic_vector(69 downto 0); -- rsp_xbar_demux:src0_data -> rsp_xbar_mux:sink0_data
signal rsp_xbar_demux_src0_channel : std_logic_vector(6 downto 0); -- rsp_xbar_demux:src0_channel -> rsp_xbar_mux:sink0_channel
signal rsp_xbar_demux_src0_ready : std_logic; -- rsp_xbar_mux:sink0_ready -> rsp_xbar_demux:src0_ready
signal rsp_xbar_demux_001_src0_endofpacket : std_logic; -- rsp_xbar_demux_001:src0_endofpacket -> rsp_xbar_mux:sink1_endofpacket
signal rsp_xbar_demux_001_src0_valid : std_logic; -- rsp_xbar_demux_001:src0_valid -> rsp_xbar_mux:sink1_valid
signal rsp_xbar_demux_001_src0_startofpacket : std_logic; -- rsp_xbar_demux_001:src0_startofpacket -> rsp_xbar_mux:sink1_startofpacket
signal rsp_xbar_demux_001_src0_data : std_logic_vector(69 downto 0); -- rsp_xbar_demux_001:src0_data -> rsp_xbar_mux:sink1_data
signal rsp_xbar_demux_001_src0_channel : std_logic_vector(6 downto 0); -- rsp_xbar_demux_001:src0_channel -> rsp_xbar_mux:sink1_channel
signal rsp_xbar_demux_001_src0_ready : std_logic; -- rsp_xbar_mux:sink1_ready -> rsp_xbar_demux_001:src0_ready
signal rsp_xbar_demux_002_src0_endofpacket : std_logic; -- rsp_xbar_demux_002:src0_endofpacket -> rsp_xbar_mux:sink2_endofpacket
signal rsp_xbar_demux_002_src0_valid : std_logic; -- rsp_xbar_demux_002:src0_valid -> rsp_xbar_mux:sink2_valid
signal rsp_xbar_demux_002_src0_startofpacket : std_logic; -- rsp_xbar_demux_002:src0_startofpacket -> rsp_xbar_mux:sink2_startofpacket
signal rsp_xbar_demux_002_src0_data : std_logic_vector(69 downto 0); -- rsp_xbar_demux_002:src0_data -> rsp_xbar_mux:sink2_data
signal rsp_xbar_demux_002_src0_channel : std_logic_vector(6 downto 0); -- rsp_xbar_demux_002:src0_channel -> rsp_xbar_mux:sink2_channel
signal rsp_xbar_demux_002_src0_ready : std_logic; -- rsp_xbar_mux:sink2_ready -> rsp_xbar_demux_002:src0_ready
signal rsp_xbar_demux_003_src0_endofpacket : std_logic; -- rsp_xbar_demux_003:src0_endofpacket -> rsp_xbar_mux:sink3_endofpacket
signal rsp_xbar_demux_003_src0_valid : std_logic; -- rsp_xbar_demux_003:src0_valid -> rsp_xbar_mux:sink3_valid
signal rsp_xbar_demux_003_src0_startofpacket : std_logic; -- rsp_xbar_demux_003:src0_startofpacket -> rsp_xbar_mux:sink3_startofpacket
signal rsp_xbar_demux_003_src0_data : std_logic_vector(69 downto 0); -- rsp_xbar_demux_003:src0_data -> rsp_xbar_mux:sink3_data
signal rsp_xbar_demux_003_src0_channel : std_logic_vector(6 downto 0); -- rsp_xbar_demux_003:src0_channel -> rsp_xbar_mux:sink3_channel
signal rsp_xbar_demux_003_src0_ready : std_logic; -- rsp_xbar_mux:sink3_ready -> rsp_xbar_demux_003:src0_ready
signal rsp_xbar_demux_004_src0_endofpacket : std_logic; -- rsp_xbar_demux_004:src0_endofpacket -> rsp_xbar_mux:sink4_endofpacket
signal rsp_xbar_demux_004_src0_valid : std_logic; -- rsp_xbar_demux_004:src0_valid -> rsp_xbar_mux:sink4_valid
signal rsp_xbar_demux_004_src0_startofpacket : std_logic; -- rsp_xbar_demux_004:src0_startofpacket -> rsp_xbar_mux:sink4_startofpacket
signal rsp_xbar_demux_004_src0_data : std_logic_vector(69 downto 0); -- rsp_xbar_demux_004:src0_data -> rsp_xbar_mux:sink4_data
signal rsp_xbar_demux_004_src0_channel : std_logic_vector(6 downto 0); -- rsp_xbar_demux_004:src0_channel -> rsp_xbar_mux:sink4_channel
signal rsp_xbar_demux_004_src0_ready : std_logic; -- rsp_xbar_mux:sink4_ready -> rsp_xbar_demux_004:src0_ready
signal rsp_xbar_demux_005_src0_endofpacket : std_logic; -- rsp_xbar_demux_005:src0_endofpacket -> rsp_xbar_mux:sink5_endofpacket
signal rsp_xbar_demux_005_src0_valid : std_logic; -- rsp_xbar_demux_005:src0_valid -> rsp_xbar_mux:sink5_valid
signal rsp_xbar_demux_005_src0_startofpacket : std_logic; -- rsp_xbar_demux_005:src0_startofpacket -> rsp_xbar_mux:sink5_startofpacket
signal rsp_xbar_demux_005_src0_data : std_logic_vector(69 downto 0); -- rsp_xbar_demux_005:src0_data -> rsp_xbar_mux:sink5_data
signal rsp_xbar_demux_005_src0_channel : std_logic_vector(6 downto 0); -- rsp_xbar_demux_005:src0_channel -> rsp_xbar_mux:sink5_channel
signal rsp_xbar_demux_005_src0_ready : std_logic; -- rsp_xbar_mux:sink5_ready -> rsp_xbar_demux_005:src0_ready
signal rsp_xbar_demux_006_src0_endofpacket : std_logic; -- rsp_xbar_demux_006:src0_endofpacket -> rsp_xbar_mux:sink6_endofpacket
signal rsp_xbar_demux_006_src0_valid : std_logic; -- rsp_xbar_demux_006:src0_valid -> rsp_xbar_mux:sink6_valid
signal rsp_xbar_demux_006_src0_startofpacket : std_logic; -- rsp_xbar_demux_006:src0_startofpacket -> rsp_xbar_mux:sink6_startofpacket
signal rsp_xbar_demux_006_src0_data : std_logic_vector(69 downto 0); -- rsp_xbar_demux_006:src0_data -> rsp_xbar_mux:sink6_data
signal rsp_xbar_demux_006_src0_channel : std_logic_vector(6 downto 0); -- rsp_xbar_demux_006:src0_channel -> rsp_xbar_mux:sink6_channel
signal rsp_xbar_demux_006_src0_ready : std_logic; -- rsp_xbar_mux:sink6_ready -> rsp_xbar_demux_006:src0_ready
signal addr_router_src_endofpacket : std_logic; -- addr_router:src_endofpacket -> cmd_xbar_demux:sink_endofpacket
signal addr_router_src_valid : std_logic; -- addr_router:src_valid -> cmd_xbar_demux:sink_valid
signal addr_router_src_startofpacket : std_logic; -- addr_router:src_startofpacket -> cmd_xbar_demux:sink_startofpacket
signal addr_router_src_data : std_logic_vector(69 downto 0); -- addr_router:src_data -> cmd_xbar_demux:sink_data
signal addr_router_src_channel : std_logic_vector(6 downto 0); -- addr_router:src_channel -> cmd_xbar_demux:sink_channel
signal addr_router_src_ready : std_logic; -- cmd_xbar_demux:sink_ready -> addr_router:src_ready
signal rsp_xbar_mux_src_endofpacket : std_logic; -- rsp_xbar_mux:src_endofpacket -> EIM_Slave_to_Avalon_Master_0_avalon_master_translator_avalon_universal_master_0_agent:rp_endofpacket
signal rsp_xbar_mux_src_valid : std_logic; -- rsp_xbar_mux:src_valid -> EIM_Slave_to_Avalon_Master_0_avalon_master_translator_avalon_universal_master_0_agent:rp_valid
signal rsp_xbar_mux_src_startofpacket : std_logic; -- rsp_xbar_mux:src_startofpacket -> EIM_Slave_to_Avalon_Master_0_avalon_master_translator_avalon_universal_master_0_agent:rp_startofpacket
signal rsp_xbar_mux_src_data : std_logic_vector(69 downto 0); -- rsp_xbar_mux:src_data -> EIM_Slave_to_Avalon_Master_0_avalon_master_translator_avalon_universal_master_0_agent:rp_data
signal rsp_xbar_mux_src_channel : std_logic_vector(6 downto 0); -- rsp_xbar_mux:src_channel -> EIM_Slave_to_Avalon_Master_0_avalon_master_translator_avalon_universal_master_0_agent:rp_channel
signal rsp_xbar_mux_src_ready : std_logic; -- EIM_Slave_to_Avalon_Master_0_avalon_master_translator_avalon_universal_master_0_agent:rp_ready -> rsp_xbar_mux:src_ready
signal cmd_xbar_demux_src0_ready : std_logic; -- width_adapter:in_ready -> cmd_xbar_demux:src0_ready
signal width_adapter_src_endofpacket : std_logic; -- width_adapter:out_endofpacket -> info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket
signal width_adapter_src_valid : std_logic; -- width_adapter:out_valid -> info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:cp_valid
signal width_adapter_src_startofpacket : std_logic; -- width_adapter:out_startofpacket -> info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket
signal width_adapter_src_data : std_logic_vector(87 downto 0); -- width_adapter:out_data -> info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:cp_data
signal width_adapter_src_ready : std_logic; -- info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:cp_ready -> width_adapter:out_ready
signal width_adapter_src_channel : std_logic_vector(6 downto 0); -- width_adapter:out_channel -> info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent:cp_channel
signal id_router_src_endofpacket : std_logic; -- id_router:src_endofpacket -> width_adapter_001:in_endofpacket
signal id_router_src_valid : std_logic; -- id_router:src_valid -> width_adapter_001:in_valid
signal id_router_src_startofpacket : std_logic; -- id_router:src_startofpacket -> width_adapter_001:in_startofpacket
signal id_router_src_data : std_logic_vector(87 downto 0); -- id_router:src_data -> width_adapter_001:in_data
signal id_router_src_channel : std_logic_vector(6 downto 0); -- id_router:src_channel -> width_adapter_001:in_channel
signal id_router_src_ready : std_logic; -- width_adapter_001:in_ready -> id_router:src_ready
signal width_adapter_001_src_endofpacket : std_logic; -- width_adapter_001:out_endofpacket -> rsp_xbar_demux:sink_endofpacket
signal width_adapter_001_src_valid : std_logic; -- width_adapter_001:out_valid -> rsp_xbar_demux:sink_valid
signal width_adapter_001_src_startofpacket : std_logic; -- width_adapter_001:out_startofpacket -> rsp_xbar_demux:sink_startofpacket
signal width_adapter_001_src_data : std_logic_vector(69 downto 0); -- width_adapter_001:out_data -> rsp_xbar_demux:sink_data
signal width_adapter_001_src_ready : std_logic; -- rsp_xbar_demux:sink_ready -> width_adapter_001:out_ready
signal width_adapter_001_src_channel : std_logic_vector(6 downto 0); -- width_adapter_001:out_channel -> rsp_xbar_demux:sink_channel
signal cmd_xbar_demux_src1_ready : std_logic; -- width_adapter_002:in_ready -> cmd_xbar_demux:src1_ready
signal width_adapter_002_src_endofpacket : std_logic; -- width_adapter_002:out_endofpacket -> dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket
signal width_adapter_002_src_valid : std_logic; -- width_adapter_002:out_valid -> dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:cp_valid
signal width_adapter_002_src_startofpacket : std_logic; -- width_adapter_002:out_startofpacket -> dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket
signal width_adapter_002_src_data : std_logic_vector(87 downto 0); -- width_adapter_002:out_data -> dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:cp_data
signal width_adapter_002_src_ready : std_logic; -- dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:cp_ready -> width_adapter_002:out_ready
signal width_adapter_002_src_channel : std_logic_vector(6 downto 0); -- width_adapter_002:out_channel -> dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent:cp_channel
signal id_router_001_src_endofpacket : std_logic; -- id_router_001:src_endofpacket -> width_adapter_003:in_endofpacket
signal id_router_001_src_valid : std_logic; -- id_router_001:src_valid -> width_adapter_003:in_valid
signal id_router_001_src_startofpacket : std_logic; -- id_router_001:src_startofpacket -> width_adapter_003:in_startofpacket
signal id_router_001_src_data : std_logic_vector(87 downto 0); -- id_router_001:src_data -> width_adapter_003:in_data
signal id_router_001_src_channel : std_logic_vector(6 downto 0); -- id_router_001:src_channel -> width_adapter_003:in_channel
signal id_router_001_src_ready : std_logic; -- width_adapter_003:in_ready -> id_router_001:src_ready
signal width_adapter_003_src_endofpacket : std_logic; -- width_adapter_003:out_endofpacket -> rsp_xbar_demux_001:sink_endofpacket
signal width_adapter_003_src_valid : std_logic; -- width_adapter_003:out_valid -> rsp_xbar_demux_001:sink_valid
signal width_adapter_003_src_startofpacket : std_logic; -- width_adapter_003:out_startofpacket -> rsp_xbar_demux_001:sink_startofpacket
signal width_adapter_003_src_data : std_logic_vector(69 downto 0); -- width_adapter_003:out_data -> rsp_xbar_demux_001:sink_data
signal width_adapter_003_src_ready : std_logic; -- rsp_xbar_demux_001:sink_ready -> width_adapter_003:out_ready
signal width_adapter_003_src_channel : std_logic_vector(6 downto 0); -- width_adapter_003:out_channel -> rsp_xbar_demux_001:sink_channel
signal cmd_xbar_demux_src2_ready : std_logic; -- width_adapter_004:in_ready -> cmd_xbar_demux:src2_ready
signal width_adapter_004_src_endofpacket : std_logic; -- width_adapter_004:out_endofpacket -> fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_endofpacket
signal width_adapter_004_src_valid : std_logic; -- width_adapter_004:out_valid -> fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_valid
signal width_adapter_004_src_startofpacket : std_logic; -- width_adapter_004:out_startofpacket -> fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_startofpacket
signal width_adapter_004_src_data : std_logic_vector(87 downto 0); -- width_adapter_004:out_data -> fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_data
signal width_adapter_004_src_ready : std_logic; -- fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_ready -> width_adapter_004:out_ready
signal width_adapter_004_src_channel : std_logic_vector(6 downto 0); -- width_adapter_004:out_channel -> fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_channel
signal id_router_002_src_endofpacket : std_logic; -- id_router_002:src_endofpacket -> width_adapter_005:in_endofpacket
signal id_router_002_src_valid : std_logic; -- id_router_002:src_valid -> width_adapter_005:in_valid
signal id_router_002_src_startofpacket : std_logic; -- id_router_002:src_startofpacket -> width_adapter_005:in_startofpacket
signal id_router_002_src_data : std_logic_vector(87 downto 0); -- id_router_002:src_data -> width_adapter_005:in_data
signal id_router_002_src_channel : std_logic_vector(6 downto 0); -- id_router_002:src_channel -> width_adapter_005:in_channel
signal id_router_002_src_ready : std_logic; -- width_adapter_005:in_ready -> id_router_002:src_ready
signal width_adapter_005_src_endofpacket : std_logic; -- width_adapter_005:out_endofpacket -> rsp_xbar_demux_002:sink_endofpacket
signal width_adapter_005_src_valid : std_logic; -- width_adapter_005:out_valid -> rsp_xbar_demux_002:sink_valid
signal width_adapter_005_src_startofpacket : std_logic; -- width_adapter_005:out_startofpacket -> rsp_xbar_demux_002:sink_startofpacket
signal width_adapter_005_src_data : std_logic_vector(69 downto 0); -- width_adapter_005:out_data -> rsp_xbar_demux_002:sink_data
signal width_adapter_005_src_ready : std_logic; -- rsp_xbar_demux_002:sink_ready -> width_adapter_005:out_ready
signal width_adapter_005_src_channel : std_logic_vector(6 downto 0); -- width_adapter_005:out_channel -> rsp_xbar_demux_002:sink_channel
signal cmd_xbar_demux_src3_ready : std_logic; -- width_adapter_006:in_ready -> cmd_xbar_demux:src3_ready
signal width_adapter_006_src_endofpacket : std_logic; -- width_adapter_006:out_endofpacket -> gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_endofpacket
signal width_adapter_006_src_valid : std_logic; -- width_adapter_006:out_valid -> gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_valid
signal width_adapter_006_src_startofpacket : std_logic; -- width_adapter_006:out_startofpacket -> gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_startofpacket
signal width_adapter_006_src_data : std_logic_vector(87 downto 0); -- width_adapter_006:out_data -> gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_data
signal width_adapter_006_src_ready : std_logic; -- gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_ready -> width_adapter_006:out_ready
signal width_adapter_006_src_channel : std_logic_vector(6 downto 0); -- width_adapter_006:out_channel -> gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_channel
signal id_router_003_src_endofpacket : std_logic; -- id_router_003:src_endofpacket -> width_adapter_007:in_endofpacket
signal id_router_003_src_valid : std_logic; -- id_router_003:src_valid -> width_adapter_007:in_valid
signal id_router_003_src_startofpacket : std_logic; -- id_router_003:src_startofpacket -> width_adapter_007:in_startofpacket
signal id_router_003_src_data : std_logic_vector(87 downto 0); -- id_router_003:src_data -> width_adapter_007:in_data
signal id_router_003_src_channel : std_logic_vector(6 downto 0); -- id_router_003:src_channel -> width_adapter_007:in_channel
signal id_router_003_src_ready : std_logic; -- width_adapter_007:in_ready -> id_router_003:src_ready
signal width_adapter_007_src_endofpacket : std_logic; -- width_adapter_007:out_endofpacket -> rsp_xbar_demux_003:sink_endofpacket
signal width_adapter_007_src_valid : std_logic; -- width_adapter_007:out_valid -> rsp_xbar_demux_003:sink_valid
signal width_adapter_007_src_startofpacket : std_logic; -- width_adapter_007:out_startofpacket -> rsp_xbar_demux_003:sink_startofpacket
signal width_adapter_007_src_data : std_logic_vector(69 downto 0); -- width_adapter_007:out_data -> rsp_xbar_demux_003:sink_data
signal width_adapter_007_src_ready : std_logic; -- rsp_xbar_demux_003:sink_ready -> width_adapter_007:out_ready
signal width_adapter_007_src_channel : std_logic_vector(6 downto 0); -- width_adapter_007:out_channel -> rsp_xbar_demux_003:sink_channel
signal cmd_xbar_demux_src4_ready : std_logic; -- width_adapter_008:in_ready -> cmd_xbar_demux:src4_ready
signal width_adapter_008_src_endofpacket : std_logic; -- width_adapter_008:out_endofpacket -> pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_endofpacket
signal width_adapter_008_src_valid : std_logic; -- width_adapter_008:out_valid -> pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_valid
signal width_adapter_008_src_startofpacket : std_logic; -- width_adapter_008:out_startofpacket -> pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_startofpacket
signal width_adapter_008_src_data : std_logic_vector(87 downto 0); -- width_adapter_008:out_data -> pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_data
signal width_adapter_008_src_ready : std_logic; -- pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_ready -> width_adapter_008:out_ready
signal width_adapter_008_src_channel : std_logic_vector(6 downto 0); -- width_adapter_008:out_channel -> pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_channel
signal id_router_004_src_endofpacket : std_logic; -- id_router_004:src_endofpacket -> width_adapter_009:in_endofpacket
signal id_router_004_src_valid : std_logic; -- id_router_004:src_valid -> width_adapter_009:in_valid
signal id_router_004_src_startofpacket : std_logic; -- id_router_004:src_startofpacket -> width_adapter_009:in_startofpacket
signal id_router_004_src_data : std_logic_vector(87 downto 0); -- id_router_004:src_data -> width_adapter_009:in_data
signal id_router_004_src_channel : std_logic_vector(6 downto 0); -- id_router_004:src_channel -> width_adapter_009:in_channel
signal id_router_004_src_ready : std_logic; -- width_adapter_009:in_ready -> id_router_004:src_ready
signal width_adapter_009_src_endofpacket : std_logic; -- width_adapter_009:out_endofpacket -> rsp_xbar_demux_004:sink_endofpacket
signal width_adapter_009_src_valid : std_logic; -- width_adapter_009:out_valid -> rsp_xbar_demux_004:sink_valid
signal width_adapter_009_src_startofpacket : std_logic; -- width_adapter_009:out_startofpacket -> rsp_xbar_demux_004:sink_startofpacket
signal width_adapter_009_src_data : std_logic_vector(69 downto 0); -- width_adapter_009:out_data -> rsp_xbar_demux_004:sink_data
signal width_adapter_009_src_ready : std_logic; -- rsp_xbar_demux_004:sink_ready -> width_adapter_009:out_ready
signal width_adapter_009_src_channel : std_logic_vector(6 downto 0); -- width_adapter_009:out_channel -> rsp_xbar_demux_004:sink_channel
signal cmd_xbar_demux_src5_ready : std_logic; -- width_adapter_010:in_ready -> cmd_xbar_demux:src5_ready
signal width_adapter_010_src_endofpacket : std_logic; -- width_adapter_010:out_endofpacket -> gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_endofpacket
signal width_adapter_010_src_valid : std_logic; -- width_adapter_010:out_valid -> gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_valid
signal width_adapter_010_src_startofpacket : std_logic; -- width_adapter_010:out_startofpacket -> gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_startofpacket
signal width_adapter_010_src_data : std_logic_vector(87 downto 0); -- width_adapter_010:out_data -> gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_data
signal width_adapter_010_src_ready : std_logic; -- gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_ready -> width_adapter_010:out_ready
signal width_adapter_010_src_channel : std_logic_vector(6 downto 0); -- width_adapter_010:out_channel -> gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_channel
signal id_router_005_src_endofpacket : std_logic; -- id_router_005:src_endofpacket -> width_adapter_011:in_endofpacket
signal id_router_005_src_valid : std_logic; -- id_router_005:src_valid -> width_adapter_011:in_valid
signal id_router_005_src_startofpacket : std_logic; -- id_router_005:src_startofpacket -> width_adapter_011:in_startofpacket
signal id_router_005_src_data : std_logic_vector(87 downto 0); -- id_router_005:src_data -> width_adapter_011:in_data
signal id_router_005_src_channel : std_logic_vector(6 downto 0); -- id_router_005:src_channel -> width_adapter_011:in_channel
signal id_router_005_src_ready : std_logic; -- width_adapter_011:in_ready -> id_router_005:src_ready
signal width_adapter_011_src_endofpacket : std_logic; -- width_adapter_011:out_endofpacket -> rsp_xbar_demux_005:sink_endofpacket
signal width_adapter_011_src_valid : std_logic; -- width_adapter_011:out_valid -> rsp_xbar_demux_005:sink_valid
signal width_adapter_011_src_startofpacket : std_logic; -- width_adapter_011:out_startofpacket -> rsp_xbar_demux_005:sink_startofpacket
signal width_adapter_011_src_data : std_logic_vector(69 downto 0); -- width_adapter_011:out_data -> rsp_xbar_demux_005:sink_data
signal width_adapter_011_src_ready : std_logic; -- rsp_xbar_demux_005:sink_ready -> width_adapter_011:out_ready
signal width_adapter_011_src_channel : std_logic_vector(6 downto 0); -- width_adapter_011:out_channel -> rsp_xbar_demux_005:sink_channel
signal cmd_xbar_demux_src6_ready : std_logic; -- width_adapter_012:in_ready -> cmd_xbar_demux:src6_ready
signal width_adapter_012_src_endofpacket : std_logic; -- width_adapter_012:out_endofpacket -> mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_endofpacket
signal width_adapter_012_src_valid : std_logic; -- width_adapter_012:out_valid -> mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_valid
signal width_adapter_012_src_startofpacket : std_logic; -- width_adapter_012:out_startofpacket -> mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_startofpacket
signal width_adapter_012_src_data : std_logic_vector(87 downto 0); -- width_adapter_012:out_data -> mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_data
signal width_adapter_012_src_ready : std_logic; -- mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_ready -> width_adapter_012:out_ready
signal width_adapter_012_src_channel : std_logic_vector(6 downto 0); -- width_adapter_012:out_channel -> mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_channel
signal id_router_006_src_endofpacket : std_logic; -- id_router_006:src_endofpacket -> width_adapter_013:in_endofpacket
signal id_router_006_src_valid : std_logic; -- id_router_006:src_valid -> width_adapter_013:in_valid
signal id_router_006_src_startofpacket : std_logic; -- id_router_006:src_startofpacket -> width_adapter_013:in_startofpacket
signal id_router_006_src_data : std_logic_vector(87 downto 0); -- id_router_006:src_data -> width_adapter_013:in_data
signal id_router_006_src_channel : std_logic_vector(6 downto 0); -- id_router_006:src_channel -> width_adapter_013:in_channel
signal id_router_006_src_ready : std_logic; -- width_adapter_013:in_ready -> id_router_006:src_ready
signal width_adapter_013_src_endofpacket : std_logic; -- width_adapter_013:out_endofpacket -> rsp_xbar_demux_006:sink_endofpacket
signal width_adapter_013_src_valid : std_logic; -- width_adapter_013:out_valid -> rsp_xbar_demux_006:sink_valid
signal width_adapter_013_src_startofpacket : std_logic; -- width_adapter_013:out_startofpacket -> rsp_xbar_demux_006:sink_startofpacket
signal width_adapter_013_src_data : std_logic_vector(69 downto 0); -- width_adapter_013:out_data -> rsp_xbar_demux_006:sink_data
signal width_adapter_013_src_ready : std_logic; -- rsp_xbar_demux_006:sink_ready -> width_adapter_013:out_ready
signal width_adapter_013_src_channel : std_logic_vector(6 downto 0); -- width_adapter_013:out_channel -> rsp_xbar_demux_006:sink_channel
signal reset_reset_n_ports_inv : std_logic; -- reset_reset_n:inv -> [rst_controller:reset_in0, rst_controller_001:reset_in0]
signal rst_controller_001_reset_out_reset_ports_inv : std_logic; -- rst_controller_001_reset_out_reset:inv -> [EIM_Slave_to_Avalon_Master_0:isl_reset_n, dacad5668_0:isl_reset_n, fqd_interface_0:isl_reset_n, gpio_block_0:isl_reset_n, gpio_block_1:isl_reset_n, info_device_0:isl_reset_n, mpu9250_0:isl_reset_n, pwm_interface_0:isl_reset_n]
begin
altpll_0 : component cb20_altpll_0
port map (
clk => clk_clk, -- inclk_interface.clk
reset => rst_controller_reset_out_reset, -- inclk_interface_reset.reset
read => open, -- pll_slave.read
write => open, -- .write
address => open, -- .address
readdata => open, -- .readdata
writedata => open, -- .writedata
c0 => altpll_0_c0_clk, -- c0.clk
areset => open, -- areset_conduit.export
locked => open, -- locked_conduit.export
phasedone => open -- phasedone_conduit.export
);
info_device_0 : component info_device
generic map (
unique_id => "00010010011100000000000000000001",
description => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
dev_size => 896
)
port map (
isl_clk => altpll_0_c0_clk, -- clock_sink.clk
isl_reset_n => rst_controller_001_reset_out_reset_ports_inv, -- reset_sink.reset_n
islv_avs_address => info_device_0_avalon_slave_translator_avalon_anti_slave_0_address, -- avalon_slave.address
isl_avs_read => info_device_0_avalon_slave_translator_avalon_anti_slave_0_read, -- .read
isl_avs_write => info_device_0_avalon_slave_translator_avalon_anti_slave_0_write, -- .write
islv_avs_write_data => info_device_0_avalon_slave_translator_avalon_anti_slave_0_writedata, -- .writedata
oslv_avs_read_data => info_device_0_avalon_slave_translator_avalon_anti_slave_0_readdata, -- .readdata
osl_avs_waitrequest => info_device_0_avalon_slave_translator_avalon_anti_slave_0_waitrequest, -- .waitrequest
islv_avs_byteenable => info_device_0_avalon_slave_translator_avalon_anti_slave_0_byteenable -- .byteenable
);
eim_slave_to_avalon_master_0 : component eim_slave_to_avalon_master
generic map (
TRANSFER_WIDTH => 16
)
port map (
ioslv_data => eim_slave_to_avalon_master_0_conduit_end_ioslv_data, -- conduit_end.export
isl_cs_n => eim_slave_to_avalon_master_0_conduit_end_isl_cs_n, -- .export
isl_oe_n => eim_slave_to_avalon_master_0_conduit_end_isl_oe_n, -- .export
isl_we_n => eim_slave_to_avalon_master_0_conduit_end_isl_we_n, -- .export
osl_data_ack => eim_slave_to_avalon_master_0_conduit_end_osl_data_ack, -- .export
islv_address => eim_slave_to_avalon_master_0_conduit_end_islv_address, -- .export
isl_clk => altpll_0_c0_clk, -- clock_sink.clk
isl_reset_n => rst_controller_001_reset_out_reset_ports_inv, -- reset_sink.reset_n
islv_readdata => eim_slave_to_avalon_master_0_avalon_master_readdata, -- avalon_master.readdata
islv_waitrequest => eim_slave_to_avalon_master_0_avalon_master_waitrequest, -- .waitrequest
oslv_address => eim_slave_to_avalon_master_0_avalon_master_address, -- .address
oslv_read => eim_slave_to_avalon_master_0_avalon_master_read, -- .read
oslv_write => eim_slave_to_avalon_master_0_avalon_master_write, -- .write
oslv_writedata => eim_slave_to_avalon_master_0_avalon_master_writedata -- .writedata
);
dacad5668_0 : component avalon_dacad5668_interface
generic map (
BASE_CLK => 33000000,
SCLK_FREQUENCY => 10000000,
INTERNAL_REFERENCE => '0',
UNIQUE_ID => "00010010011100000010000000000001"
)
port map (
isl_clk => altpll_0_c0_clk, -- clock_sink.clk
isl_reset_n => rst_controller_001_reset_out_reset_ports_inv, -- reset_sink.reset_n
osl_sclk => dacad5668_0_conduit_end_osl_sclk, -- conduit_end.export
oslv_Ss => dacad5668_0_conduit_end_oslv_Ss, -- .export
osl_mosi => dacad5668_0_conduit_end_osl_mosi, -- .export
osl_LDAC_n => dacad5668_0_conduit_end_osl_LDAC_n, -- .export
osl_CLR_n => dacad5668_0_conduit_end_osl_CLR_n, -- .export
islv_avs_address => dacad5668_0_avalon_slave_translator_avalon_anti_slave_0_address, -- avalon_slave.address
isl_avs_read => dacad5668_0_avalon_slave_translator_avalon_anti_slave_0_read, -- .read
isl_avs_write => dacad5668_0_avalon_slave_translator_avalon_anti_slave_0_write, -- .write
islv_avs_write_data => dacad5668_0_avalon_slave_translator_avalon_anti_slave_0_writedata, -- .writedata
oslv_avs_read_data => dacad5668_0_avalon_slave_translator_avalon_anti_slave_0_readdata, -- .readdata
osl_avs_waitrequest => dacad5668_0_avalon_slave_translator_avalon_anti_slave_0_waitrequest, -- .waitrequest
islv_avs_byteenable => dacad5668_0_avalon_slave_translator_avalon_anti_slave_0_byteenable -- .byteenable
);
fqd_interface_0 : component avalon_fqd_counter_interface
generic map (
number_of_fqds => 8,
unique_id => "00010010011100000110000000000001"
)
port map (
oslv_avs_read_data => fqd_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_readdata, -- avalon_slave_0.readdata
isl_avs_read => fqd_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_read, -- .read
isl_avs_write => fqd_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_write, -- .write
islv_avs_write_data => fqd_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_writedata, -- .writedata
islv_avs_address => fqd_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_address, -- .address
osl_avs_waitrequest => fqd_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_waitrequest, -- .waitrequest
islv_avs_byteenable => fqd_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_byteenable, -- .byteenable
isl_clk => altpll_0_c0_clk, -- clock_sink.clk
isl_reset_n => rst_controller_001_reset_out_reset_ports_inv, -- reset_sink.reset_n
islv_enc_B => fqd_interface_0_conduit_end_B, -- conduit_end.export
islv_enc_A => fqd_interface_0_conduit_end_A -- .export
);
gpio_block_0 : component cb20_gpio_block_0
generic map (
number_of_gpios => 9,
unique_id => "00010010011100000101000000000001"
)
port map (
oslv_avs_read_data => gpio_block_0_avalon_slave_0_translator_avalon_anti_slave_0_readdata, -- avalon_slave_0.readdata
islv_avs_address => gpio_block_0_avalon_slave_0_translator_avalon_anti_slave_0_address, -- .address
isl_avs_read => gpio_block_0_avalon_slave_0_translator_avalon_anti_slave_0_read, -- .read
isl_avs_write => gpio_block_0_avalon_slave_0_translator_avalon_anti_slave_0_write, -- .write
osl_avs_waitrequest => gpio_block_0_avalon_slave_0_translator_avalon_anti_slave_0_waitrequest, -- .waitrequest
islv_avs_write_data => gpio_block_0_avalon_slave_0_translator_avalon_anti_slave_0_writedata, -- .writedata
islv_avs_byteenable => gpio_block_0_avalon_slave_0_translator_avalon_anti_slave_0_byteenable, -- .byteenable
isl_clk => altpll_0_c0_clk, -- clock_sink.clk
isl_reset_n => rst_controller_001_reset_out_reset_ports_inv, -- reset_sink.reset_n
oslv_gpios => gpio_block_0_conduit_end_export -- conduit_end.export
);
pwm_interface_0 : component avalon_pwm_interface
generic map (
number_of_pwms => 4,
base_clk => 200000000,
unique_id => "00010010011100001100000000000001"
)
port map (
oslv_avs_read_data => pwm_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_readdata, -- avalon_slave_0.readdata
islv_avs_address => pwm_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_address, -- .address
isl_avs_read => pwm_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_read, -- .read
isl_avs_write => pwm_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_write, -- .write
islv_avs_write_data => pwm_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_writedata, -- .writedata
osl_avs_waitrequest => pwm_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_waitrequest, -- .waitrequest
islv_avs_byteenable => pwm_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_byteenable, -- .byteenable
isl_clk => altpll_0_c0_clk, -- clock_sink.clk
isl_reset_n => rst_controller_001_reset_out_reset_ports_inv, -- reset_sink.reset_n
oslv_pwm => pwm_interface_0_conduit_end_export -- conduit_end.export
);
gpio_block_1 : component cb20_gpio_block_1
generic map (
number_of_gpios => 8,
unique_id => "00010010011100000101000000000010"
)
port map (
oslv_avs_read_data => gpio_block_1_avalon_slave_0_translator_avalon_anti_slave_0_readdata, -- avalon_slave_0.readdata
islv_avs_address => gpio_block_1_avalon_slave_0_translator_avalon_anti_slave_0_address, -- .address
isl_avs_read => gpio_block_1_avalon_slave_0_translator_avalon_anti_slave_0_read, -- .read
isl_avs_write => gpio_block_1_avalon_slave_0_translator_avalon_anti_slave_0_write, -- .write
osl_avs_waitrequest => gpio_block_1_avalon_slave_0_translator_avalon_anti_slave_0_waitrequest, -- .waitrequest
islv_avs_write_data => gpio_block_1_avalon_slave_0_translator_avalon_anti_slave_0_writedata, -- .writedata
islv_avs_byteenable => gpio_block_1_avalon_slave_0_translator_avalon_anti_slave_0_byteenable, -- .byteenable
isl_clk => altpll_0_c0_clk, -- clock_sink.clk
isl_reset_n => rst_controller_001_reset_out_reset_ports_inv, -- reset_sink.reset_n
oslv_gpios => gpio_block_1_conduit_end_export -- conduit_end.export
);
mpu9250_0 : component mpu9250_interface
generic map (
BASE_CLK => 200000000,
SCLK_FREQUENCY => 1000000,
UNIQUE_ID => "00010010011100010001000000000001"
)
port map (
islv_avs_write_data => mpu9250_0_avalon_slave_0_translator_avalon_anti_slave_0_writedata, -- avalon_slave_0.writedata
oslv_avs_read_data => mpu9250_0_avalon_slave_0_translator_avalon_anti_slave_0_readdata, -- .readdata
isl_avs_write => mpu9250_0_avalon_slave_0_translator_avalon_anti_slave_0_write, -- .write
isl_avs_read => mpu9250_0_avalon_slave_0_translator_avalon_anti_slave_0_read, -- .read
islv_avs_address => mpu9250_0_avalon_slave_0_translator_avalon_anti_slave_0_address, -- .address
islv_avs_byteenable => mpu9250_0_avalon_slave_0_translator_avalon_anti_slave_0_byteenable, -- .byteenable
osl_avs_waitrequest => mpu9250_0_avalon_slave_0_translator_avalon_anti_slave_0_waitrequest, -- .waitrequest
isl_clk => altpll_0_c0_clk, -- clock_sink.clk
isl_reset_n => rst_controller_001_reset_out_reset_ports_inv, -- reset_sink.reset_n
osl_sclk => mpu9250_0_conduit_end_osl_sclk, -- conduit_end.export
oslv_cs_n => mpu9250_0_conduit_end_oslv_cs_n, -- .export
isl_sdo => mpu9250_0_conduit_end_isl_sdo, -- .export
osl_sdi => mpu9250_0_conduit_end_osl_sdi -- .export
);
eim_slave_to_avalon_master_0_avalon_master_translator : component altera_merlin_master_translator
generic map (
AV_ADDRESS_W => 16,
AV_DATA_W => 16,
AV_BURSTCOUNT_W => 1,
AV_BYTEENABLE_W => 2,
UAV_ADDRESS_W => 17,
UAV_BURSTCOUNT_W => 2,
USE_READ => 1,
USE_WRITE => 1,
USE_BEGINBURSTTRANSFER => 0,
USE_BEGINTRANSFER => 0,
USE_CHIPSELECT => 0,
USE_BURSTCOUNT => 0,
USE_READDATAVALID => 0,
USE_WAITREQUEST => 1,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0,
AV_SYMBOLS_PER_WORD => 2,
AV_ADDRESS_SYMBOLS => 0,
AV_BURSTCOUNT_SYMBOLS => 0,
AV_CONSTANT_BURST_BEHAVIOR => 0,
UAV_CONSTANT_BURST_BEHAVIOR => 0,
AV_LINEWRAPBURSTS => 0,
AV_REGISTERINCOMINGSIGNALS => 0
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- reset.reset
uav_address => eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_address, -- avalon_universal_master_0.address
uav_burstcount => eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_burstcount, -- .burstcount
uav_read => eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_read, -- .read
uav_write => eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_write, -- .write
uav_waitrequest => eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_waitrequest, -- .waitrequest
uav_readdatavalid => eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_readdatavalid, -- .readdatavalid
uav_byteenable => eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_byteenable, -- .byteenable
uav_readdata => eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_readdata, -- .readdata
uav_writedata => eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_writedata, -- .writedata
uav_lock => eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_lock, -- .lock
uav_debugaccess => eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_debugaccess, -- .debugaccess
av_address => eim_slave_to_avalon_master_0_avalon_master_address, -- avalon_anti_master_0.address
av_waitrequest => eim_slave_to_avalon_master_0_avalon_master_waitrequest, -- .waitrequest
av_read => eim_slave_to_avalon_master_0_avalon_master_read, -- .read
av_readdata => eim_slave_to_avalon_master_0_avalon_master_readdata, -- .readdata
av_write => eim_slave_to_avalon_master_0_avalon_master_write, -- .write
av_writedata => eim_slave_to_avalon_master_0_avalon_master_writedata, -- .writedata
av_burstcount => "1", -- (terminated)
av_byteenable => "11", -- (terminated)
av_beginbursttransfer => '0', -- (terminated)
av_begintransfer => '0', -- (terminated)
av_chipselect => '0', -- (terminated)
av_readdatavalid => open, -- (terminated)
av_lock => '0', -- (terminated)
av_debugaccess => '0', -- (terminated)
uav_clken => open, -- (terminated)
av_clken => '1', -- (terminated)
uav_response => "00", -- (terminated)
av_response => open, -- (terminated)
uav_writeresponserequest => open, -- (terminated)
uav_writeresponsevalid => '0', -- (terminated)
av_writeresponserequest => '0', -- (terminated)
av_writeresponsevalid => open -- (terminated)
);
info_device_0_avalon_slave_translator : component cb20_info_device_0_avalon_slave_translator
generic map (
AV_ADDRESS_W => 5,
AV_DATA_W => 32,
UAV_DATA_W => 32,
AV_BURSTCOUNT_W => 1,
AV_BYTEENABLE_W => 4,
UAV_BYTEENABLE_W => 4,
UAV_ADDRESS_W => 17,
UAV_BURSTCOUNT_W => 3,
AV_READLATENCY => 0,
USE_READDATAVALID => 0,
USE_WAITREQUEST => 1,
USE_UAV_CLKEN => 0,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0,
AV_SYMBOLS_PER_WORD => 4,
AV_ADDRESS_SYMBOLS => 0,
AV_BURSTCOUNT_SYMBOLS => 0,
AV_CONSTANT_BURST_BEHAVIOR => 0,
UAV_CONSTANT_BURST_BEHAVIOR => 0,
AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
CHIPSELECT_THROUGH_READLATENCY => 0,
AV_READ_WAIT_CYCLES => 1,
AV_WRITE_WAIT_CYCLES => 0,
AV_SETUP_WAIT_CYCLES => 0,
AV_DATA_HOLD_CYCLES => 0
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- reset.reset
uav_address => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
uav_burstcount => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
uav_read => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_read, -- .read
uav_write => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_write, -- .write
uav_waitrequest => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
uav_readdatavalid => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
uav_byteenable => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
uav_readdata => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
uav_writedata => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
uav_lock => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
uav_debugaccess => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
av_address => info_device_0_avalon_slave_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
av_write => info_device_0_avalon_slave_translator_avalon_anti_slave_0_write, -- .write
av_read => info_device_0_avalon_slave_translator_avalon_anti_slave_0_read, -- .read
av_readdata => info_device_0_avalon_slave_translator_avalon_anti_slave_0_readdata, -- .readdata
av_writedata => info_device_0_avalon_slave_translator_avalon_anti_slave_0_writedata, -- .writedata
av_byteenable => info_device_0_avalon_slave_translator_avalon_anti_slave_0_byteenable, -- .byteenable
av_waitrequest => info_device_0_avalon_slave_translator_avalon_anti_slave_0_waitrequest, -- .waitrequest
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_chipselect => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open, -- (terminated)
uav_response => open, -- (terminated)
av_response => "00", -- (terminated)
uav_writeresponserequest => '0', -- (terminated)
uav_writeresponsevalid => open, -- (terminated)
av_writeresponserequest => open, -- (terminated)
av_writeresponsevalid => '0' -- (terminated)
);
dacad5668_0_avalon_slave_translator : component cb20_info_device_0_avalon_slave_translator
generic map (
AV_ADDRESS_W => 5,
AV_DATA_W => 32,
UAV_DATA_W => 32,
AV_BURSTCOUNT_W => 1,
AV_BYTEENABLE_W => 4,
UAV_BYTEENABLE_W => 4,
UAV_ADDRESS_W => 17,
UAV_BURSTCOUNT_W => 3,
AV_READLATENCY => 0,
USE_READDATAVALID => 0,
USE_WAITREQUEST => 1,
USE_UAV_CLKEN => 0,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0,
AV_SYMBOLS_PER_WORD => 4,
AV_ADDRESS_SYMBOLS => 0,
AV_BURSTCOUNT_SYMBOLS => 0,
AV_CONSTANT_BURST_BEHAVIOR => 0,
UAV_CONSTANT_BURST_BEHAVIOR => 0,
AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
CHIPSELECT_THROUGH_READLATENCY => 0,
AV_READ_WAIT_CYCLES => 1,
AV_WRITE_WAIT_CYCLES => 0,
AV_SETUP_WAIT_CYCLES => 0,
AV_DATA_HOLD_CYCLES => 0
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- reset.reset
uav_address => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
uav_burstcount => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
uav_read => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_read, -- .read
uav_write => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_write, -- .write
uav_waitrequest => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
uav_readdatavalid => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
uav_byteenable => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
uav_readdata => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
uav_writedata => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
uav_lock => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
uav_debugaccess => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
av_address => dacad5668_0_avalon_slave_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
av_write => dacad5668_0_avalon_slave_translator_avalon_anti_slave_0_write, -- .write
av_read => dacad5668_0_avalon_slave_translator_avalon_anti_slave_0_read, -- .read
av_readdata => dacad5668_0_avalon_slave_translator_avalon_anti_slave_0_readdata, -- .readdata
av_writedata => dacad5668_0_avalon_slave_translator_avalon_anti_slave_0_writedata, -- .writedata
av_byteenable => dacad5668_0_avalon_slave_translator_avalon_anti_slave_0_byteenable, -- .byteenable
av_waitrequest => dacad5668_0_avalon_slave_translator_avalon_anti_slave_0_waitrequest, -- .waitrequest
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_chipselect => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open, -- (terminated)
uav_response => open, -- (terminated)
av_response => "00", -- (terminated)
uav_writeresponserequest => '0', -- (terminated)
uav_writeresponsevalid => open, -- (terminated)
av_writeresponserequest => open, -- (terminated)
av_writeresponsevalid => '0' -- (terminated)
);
fqd_interface_0_avalon_slave_0_translator : component cb20_info_device_0_avalon_slave_translator
generic map (
AV_ADDRESS_W => 5,
AV_DATA_W => 32,
UAV_DATA_W => 32,
AV_BURSTCOUNT_W => 1,
AV_BYTEENABLE_W => 4,
UAV_BYTEENABLE_W => 4,
UAV_ADDRESS_W => 17,
UAV_BURSTCOUNT_W => 3,
AV_READLATENCY => 0,
USE_READDATAVALID => 0,
USE_WAITREQUEST => 1,
USE_UAV_CLKEN => 0,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0,
AV_SYMBOLS_PER_WORD => 4,
AV_ADDRESS_SYMBOLS => 0,
AV_BURSTCOUNT_SYMBOLS => 0,
AV_CONSTANT_BURST_BEHAVIOR => 0,
UAV_CONSTANT_BURST_BEHAVIOR => 0,
AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
CHIPSELECT_THROUGH_READLATENCY => 0,
AV_READ_WAIT_CYCLES => 1,
AV_WRITE_WAIT_CYCLES => 0,
AV_SETUP_WAIT_CYCLES => 0,
AV_DATA_HOLD_CYCLES => 0
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- reset.reset
uav_address => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
uav_burstcount => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
uav_read => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read, -- .read
uav_write => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write, -- .write
uav_waitrequest => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
uav_readdatavalid => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
uav_byteenable => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
uav_readdata => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
uav_writedata => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
uav_lock => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
uav_debugaccess => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
av_address => fqd_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
av_write => fqd_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_write, -- .write
av_read => fqd_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_read, -- .read
av_readdata => fqd_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_readdata, -- .readdata
av_writedata => fqd_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_writedata, -- .writedata
av_byteenable => fqd_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_byteenable, -- .byteenable
av_waitrequest => fqd_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_waitrequest, -- .waitrequest
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_chipselect => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open, -- (terminated)
uav_response => open, -- (terminated)
av_response => "00", -- (terminated)
uav_writeresponserequest => '0', -- (terminated)
uav_writeresponsevalid => open, -- (terminated)
av_writeresponserequest => open, -- (terminated)
av_writeresponsevalid => '0' -- (terminated)
);
gpio_block_0_avalon_slave_0_translator : component cb20_gpio_block_0_avalon_slave_0_translator
generic map (
AV_ADDRESS_W => 4,
AV_DATA_W => 32,
UAV_DATA_W => 32,
AV_BURSTCOUNT_W => 1,
AV_BYTEENABLE_W => 4,
UAV_BYTEENABLE_W => 4,
UAV_ADDRESS_W => 17,
UAV_BURSTCOUNT_W => 3,
AV_READLATENCY => 0,
USE_READDATAVALID => 0,
USE_WAITREQUEST => 1,
USE_UAV_CLKEN => 0,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0,
AV_SYMBOLS_PER_WORD => 4,
AV_ADDRESS_SYMBOLS => 0,
AV_BURSTCOUNT_SYMBOLS => 0,
AV_CONSTANT_BURST_BEHAVIOR => 0,
UAV_CONSTANT_BURST_BEHAVIOR => 0,
AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
CHIPSELECT_THROUGH_READLATENCY => 0,
AV_READ_WAIT_CYCLES => 1,
AV_WRITE_WAIT_CYCLES => 0,
AV_SETUP_WAIT_CYCLES => 0,
AV_DATA_HOLD_CYCLES => 0
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- reset.reset
uav_address => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
uav_burstcount => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
uav_read => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read, -- .read
uav_write => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write, -- .write
uav_waitrequest => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
uav_readdatavalid => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
uav_byteenable => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
uav_readdata => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
uav_writedata => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
uav_lock => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
uav_debugaccess => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
av_address => gpio_block_0_avalon_slave_0_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
av_write => gpio_block_0_avalon_slave_0_translator_avalon_anti_slave_0_write, -- .write
av_read => gpio_block_0_avalon_slave_0_translator_avalon_anti_slave_0_read, -- .read
av_readdata => gpio_block_0_avalon_slave_0_translator_avalon_anti_slave_0_readdata, -- .readdata
av_writedata => gpio_block_0_avalon_slave_0_translator_avalon_anti_slave_0_writedata, -- .writedata
av_byteenable => gpio_block_0_avalon_slave_0_translator_avalon_anti_slave_0_byteenable, -- .byteenable
av_waitrequest => gpio_block_0_avalon_slave_0_translator_avalon_anti_slave_0_waitrequest, -- .waitrequest
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_chipselect => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open, -- (terminated)
uav_response => open, -- (terminated)
av_response => "00", -- (terminated)
uav_writeresponserequest => '0', -- (terminated)
uav_writeresponsevalid => open, -- (terminated)
av_writeresponserequest => open, -- (terminated)
av_writeresponsevalid => '0' -- (terminated)
);
pwm_interface_0_avalon_slave_0_translator : component cb20_pwm_interface_0_avalon_slave_0_translator
generic map (
AV_ADDRESS_W => 6,
AV_DATA_W => 32,
UAV_DATA_W => 32,
AV_BURSTCOUNT_W => 1,
AV_BYTEENABLE_W => 4,
UAV_BYTEENABLE_W => 4,
UAV_ADDRESS_W => 17,
UAV_BURSTCOUNT_W => 3,
AV_READLATENCY => 0,
USE_READDATAVALID => 0,
USE_WAITREQUEST => 1,
USE_UAV_CLKEN => 0,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0,
AV_SYMBOLS_PER_WORD => 4,
AV_ADDRESS_SYMBOLS => 0,
AV_BURSTCOUNT_SYMBOLS => 0,
AV_CONSTANT_BURST_BEHAVIOR => 0,
UAV_CONSTANT_BURST_BEHAVIOR => 0,
AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
CHIPSELECT_THROUGH_READLATENCY => 0,
AV_READ_WAIT_CYCLES => 1,
AV_WRITE_WAIT_CYCLES => 0,
AV_SETUP_WAIT_CYCLES => 0,
AV_DATA_HOLD_CYCLES => 0
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- reset.reset
uav_address => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
uav_burstcount => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
uav_read => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read, -- .read
uav_write => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write, -- .write
uav_waitrequest => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
uav_readdatavalid => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
uav_byteenable => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
uav_readdata => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
uav_writedata => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
uav_lock => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
uav_debugaccess => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
av_address => pwm_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
av_write => pwm_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_write, -- .write
av_read => pwm_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_read, -- .read
av_readdata => pwm_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_readdata, -- .readdata
av_writedata => pwm_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_writedata, -- .writedata
av_byteenable => pwm_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_byteenable, -- .byteenable
av_waitrequest => pwm_interface_0_avalon_slave_0_translator_avalon_anti_slave_0_waitrequest, -- .waitrequest
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_chipselect => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open, -- (terminated)
uav_response => open, -- (terminated)
av_response => "00", -- (terminated)
uav_writeresponserequest => '0', -- (terminated)
uav_writeresponsevalid => open, -- (terminated)
av_writeresponserequest => open, -- (terminated)
av_writeresponsevalid => '0' -- (terminated)
);
gpio_block_1_avalon_slave_0_translator : component cb20_gpio_block_0_avalon_slave_0_translator
generic map (
AV_ADDRESS_W => 4,
AV_DATA_W => 32,
UAV_DATA_W => 32,
AV_BURSTCOUNT_W => 1,
AV_BYTEENABLE_W => 4,
UAV_BYTEENABLE_W => 4,
UAV_ADDRESS_W => 17,
UAV_BURSTCOUNT_W => 3,
AV_READLATENCY => 0,
USE_READDATAVALID => 0,
USE_WAITREQUEST => 1,
USE_UAV_CLKEN => 0,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0,
AV_SYMBOLS_PER_WORD => 4,
AV_ADDRESS_SYMBOLS => 0,
AV_BURSTCOUNT_SYMBOLS => 0,
AV_CONSTANT_BURST_BEHAVIOR => 0,
UAV_CONSTANT_BURST_BEHAVIOR => 0,
AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
CHIPSELECT_THROUGH_READLATENCY => 0,
AV_READ_WAIT_CYCLES => 1,
AV_WRITE_WAIT_CYCLES => 0,
AV_SETUP_WAIT_CYCLES => 0,
AV_DATA_HOLD_CYCLES => 0
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- reset.reset
uav_address => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
uav_burstcount => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
uav_read => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read, -- .read
uav_write => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write, -- .write
uav_waitrequest => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
uav_readdatavalid => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
uav_byteenable => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
uav_readdata => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
uav_writedata => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
uav_lock => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
uav_debugaccess => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
av_address => gpio_block_1_avalon_slave_0_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
av_write => gpio_block_1_avalon_slave_0_translator_avalon_anti_slave_0_write, -- .write
av_read => gpio_block_1_avalon_slave_0_translator_avalon_anti_slave_0_read, -- .read
av_readdata => gpio_block_1_avalon_slave_0_translator_avalon_anti_slave_0_readdata, -- .readdata
av_writedata => gpio_block_1_avalon_slave_0_translator_avalon_anti_slave_0_writedata, -- .writedata
av_byteenable => gpio_block_1_avalon_slave_0_translator_avalon_anti_slave_0_byteenable, -- .byteenable
av_waitrequest => gpio_block_1_avalon_slave_0_translator_avalon_anti_slave_0_waitrequest, -- .waitrequest
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_chipselect => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open, -- (terminated)
uav_response => open, -- (terminated)
av_response => "00", -- (terminated)
uav_writeresponserequest => '0', -- (terminated)
uav_writeresponsevalid => open, -- (terminated)
av_writeresponserequest => open, -- (terminated)
av_writeresponsevalid => '0' -- (terminated)
);
mpu9250_0_avalon_slave_0_translator : component cb20_info_device_0_avalon_slave_translator
generic map (
AV_ADDRESS_W => 5,
AV_DATA_W => 32,
UAV_DATA_W => 32,
AV_BURSTCOUNT_W => 1,
AV_BYTEENABLE_W => 4,
UAV_BYTEENABLE_W => 4,
UAV_ADDRESS_W => 17,
UAV_BURSTCOUNT_W => 3,
AV_READLATENCY => 0,
USE_READDATAVALID => 0,
USE_WAITREQUEST => 1,
USE_UAV_CLKEN => 0,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0,
AV_SYMBOLS_PER_WORD => 4,
AV_ADDRESS_SYMBOLS => 0,
AV_BURSTCOUNT_SYMBOLS => 0,
AV_CONSTANT_BURST_BEHAVIOR => 0,
UAV_CONSTANT_BURST_BEHAVIOR => 0,
AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
CHIPSELECT_THROUGH_READLATENCY => 0,
AV_READ_WAIT_CYCLES => 1,
AV_WRITE_WAIT_CYCLES => 0,
AV_SETUP_WAIT_CYCLES => 0,
AV_DATA_HOLD_CYCLES => 0
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- reset.reset
uav_address => mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
uav_burstcount => mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
uav_read => mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read, -- .read
uav_write => mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write, -- .write
uav_waitrequest => mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
uav_readdatavalid => mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
uav_byteenable => mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
uav_readdata => mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
uav_writedata => mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
uav_lock => mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
uav_debugaccess => mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
av_address => mpu9250_0_avalon_slave_0_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
av_write => mpu9250_0_avalon_slave_0_translator_avalon_anti_slave_0_write, -- .write
av_read => mpu9250_0_avalon_slave_0_translator_avalon_anti_slave_0_read, -- .read
av_readdata => mpu9250_0_avalon_slave_0_translator_avalon_anti_slave_0_readdata, -- .readdata
av_writedata => mpu9250_0_avalon_slave_0_translator_avalon_anti_slave_0_writedata, -- .writedata
av_byteenable => mpu9250_0_avalon_slave_0_translator_avalon_anti_slave_0_byteenable, -- .byteenable
av_waitrequest => mpu9250_0_avalon_slave_0_translator_avalon_anti_slave_0_waitrequest, -- .waitrequest
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_chipselect => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open, -- (terminated)
uav_response => open, -- (terminated)
av_response => "00", -- (terminated)
uav_writeresponserequest => '0', -- (terminated)
uav_writeresponsevalid => open, -- (terminated)
av_writeresponserequest => open, -- (terminated)
av_writeresponsevalid => '0' -- (terminated)
);
eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_agent : component altera_merlin_master_agent
generic map (
PKT_PROTECTION_H => 63,
PKT_PROTECTION_L => 61,
PKT_BEGIN_BURST => 52,
PKT_BURSTWRAP_H => 44,
PKT_BURSTWRAP_L => 44,
PKT_BURST_SIZE_H => 47,
PKT_BURST_SIZE_L => 45,
PKT_BURST_TYPE_H => 49,
PKT_BURST_TYPE_L => 48,
PKT_BYTE_CNT_H => 43,
PKT_BYTE_CNT_L => 41,
PKT_ADDR_H => 34,
PKT_ADDR_L => 18,
PKT_TRANS_COMPRESSED_READ => 35,
PKT_TRANS_POSTED => 36,
PKT_TRANS_WRITE => 37,
PKT_TRANS_READ => 38,
PKT_TRANS_LOCK => 39,
PKT_TRANS_EXCLUSIVE => 40,
PKT_DATA_H => 15,
PKT_DATA_L => 0,
PKT_BYTEEN_H => 17,
PKT_BYTEEN_L => 16,
PKT_SRC_ID_H => 56,
PKT_SRC_ID_L => 54,
PKT_DEST_ID_H => 59,
PKT_DEST_ID_L => 57,
PKT_THREAD_ID_H => 60,
PKT_THREAD_ID_L => 60,
PKT_CACHE_H => 67,
PKT_CACHE_L => 64,
PKT_DATA_SIDEBAND_H => 51,
PKT_DATA_SIDEBAND_L => 51,
PKT_QOS_H => 53,
PKT_QOS_L => 53,
PKT_ADDR_SIDEBAND_H => 50,
PKT_ADDR_SIDEBAND_L => 50,
PKT_RESPONSE_STATUS_H => 69,
PKT_RESPONSE_STATUS_L => 68,
ST_DATA_W => 70,
ST_CHANNEL_W => 7,
AV_BURSTCOUNT_W => 2,
SUPPRESS_0_BYTEEN_RSP => 1,
ID => 0,
BURSTWRAP_VALUE => 1,
CACHE_VALUE => 0,
SECURE_ACCESS_BIT => 1,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
av_address => eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_address, -- av.address
av_write => eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_write, -- .write
av_read => eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_read, -- .read
av_writedata => eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_writedata, -- .writedata
av_readdata => eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_readdata, -- .readdata
av_waitrequest => eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_waitrequest, -- .waitrequest
av_readdatavalid => eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_readdatavalid, -- .readdatavalid
av_byteenable => eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_byteenable, -- .byteenable
av_burstcount => eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_burstcount, -- .burstcount
av_debugaccess => eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_debugaccess, -- .debugaccess
av_lock => eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_lock, -- .lock
cp_valid => eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_agent_cp_valid, -- cp.valid
cp_data => eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_agent_cp_data, -- .data
cp_startofpacket => eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_agent_cp_startofpacket, -- .startofpacket
cp_endofpacket => eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_agent_cp_endofpacket, -- .endofpacket
cp_ready => eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_agent_cp_ready, -- .ready
rp_valid => rsp_xbar_mux_src_valid, -- rp.valid
rp_data => rsp_xbar_mux_src_data, -- .data
rp_channel => rsp_xbar_mux_src_channel, -- .channel
rp_startofpacket => rsp_xbar_mux_src_startofpacket, -- .startofpacket
rp_endofpacket => rsp_xbar_mux_src_endofpacket, -- .endofpacket
rp_ready => rsp_xbar_mux_src_ready, -- .ready
av_response => open, -- (terminated)
av_writeresponserequest => '0', -- (terminated)
av_writeresponsevalid => open -- (terminated)
);
info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent : component altera_merlin_slave_agent
generic map (
PKT_DATA_H => 31,
PKT_DATA_L => 0,
PKT_BEGIN_BURST => 70,
PKT_SYMBOL_W => 8,
PKT_BYTEEN_H => 35,
PKT_BYTEEN_L => 32,
PKT_ADDR_H => 52,
PKT_ADDR_L => 36,
PKT_TRANS_COMPRESSED_READ => 53,
PKT_TRANS_POSTED => 54,
PKT_TRANS_WRITE => 55,
PKT_TRANS_READ => 56,
PKT_TRANS_LOCK => 57,
PKT_SRC_ID_H => 74,
PKT_SRC_ID_L => 72,
PKT_DEST_ID_H => 77,
PKT_DEST_ID_L => 75,
PKT_BURSTWRAP_H => 62,
PKT_BURSTWRAP_L => 62,
PKT_BYTE_CNT_H => 61,
PKT_BYTE_CNT_L => 59,
PKT_PROTECTION_H => 81,
PKT_PROTECTION_L => 79,
PKT_RESPONSE_STATUS_H => 87,
PKT_RESPONSE_STATUS_L => 86,
PKT_BURST_SIZE_H => 65,
PKT_BURST_SIZE_L => 63,
ST_CHANNEL_W => 7,
ST_DATA_W => 88,
AVS_BURSTCOUNT_W => 3,
SUPPRESS_0_BYTEEN_CMD => 0,
PREVENT_FIFO_OVERFLOW => 1,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
m0_address => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
m0_burstcount => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
m0_byteenable => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
m0_debugaccess => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
m0_lock => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
m0_readdata => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
m0_readdatavalid => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
m0_read => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_read, -- .read
m0_waitrequest => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
m0_writedata => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
m0_write => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_write, -- .write
rp_endofpacket => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
rp_ready => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
rp_valid => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
rp_data => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rp_data, -- .data
rp_startofpacket => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
cp_ready => width_adapter_src_ready, -- cp.ready
cp_valid => width_adapter_src_valid, -- .valid
cp_data => width_adapter_src_data, -- .data
cp_startofpacket => width_adapter_src_startofpacket, -- .startofpacket
cp_endofpacket => width_adapter_src_endofpacket, -- .endofpacket
cp_channel => width_adapter_src_channel, -- .channel
rf_sink_ready => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
rf_sink_valid => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
rf_sink_startofpacket => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
rf_sink_endofpacket => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
rf_sink_data => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
rf_source_ready => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
rf_source_valid => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
rf_source_startofpacket => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
rf_source_endofpacket => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
rf_source_data => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
rdata_fifo_sink_ready => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_sink.ready
rdata_fifo_sink_valid => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_sink_data => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
rdata_fifo_src_ready => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
rdata_fifo_src_valid => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_src_data => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
m0_response => "00", -- (terminated)
m0_writeresponserequest => open, -- (terminated)
m0_writeresponsevalid => '0' -- (terminated)
);
info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo : component altera_avalon_sc_fifo
generic map (
SYMBOLS_PER_BEAT => 1,
BITS_PER_SYMBOL => 89,
FIFO_DEPTH => 2,
CHANNEL_WIDTH => 0,
ERROR_WIDTH => 0,
USE_PACKETS => 1,
USE_FILL_LEVEL => 0,
EMPTY_LATENCY => 1,
USE_MEMORY_BLOCKS => 0,
USE_STORE_FORWARD => 0,
USE_ALMOST_FULL_IF => 0,
USE_ALMOST_EMPTY_IF => 0
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
in_data => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
in_valid => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
in_ready => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
in_startofpacket => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
in_endofpacket => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
out_data => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
out_valid => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
out_ready => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
out_startofpacket => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
out_endofpacket => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
csr_address => "00", -- (terminated)
csr_read => '0', -- (terminated)
csr_write => '0', -- (terminated)
csr_readdata => open, -- (terminated)
csr_writedata => "00000000000000000000000000000000", -- (terminated)
almost_full_data => open, -- (terminated)
almost_empty_data => open, -- (terminated)
in_empty => '0', -- (terminated)
out_empty => open, -- (terminated)
in_error => '0', -- (terminated)
out_error => open, -- (terminated)
in_channel => '0', -- (terminated)
out_channel => open -- (terminated)
);
dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent : component altera_merlin_slave_agent
generic map (
PKT_DATA_H => 31,
PKT_DATA_L => 0,
PKT_BEGIN_BURST => 70,
PKT_SYMBOL_W => 8,
PKT_BYTEEN_H => 35,
PKT_BYTEEN_L => 32,
PKT_ADDR_H => 52,
PKT_ADDR_L => 36,
PKT_TRANS_COMPRESSED_READ => 53,
PKT_TRANS_POSTED => 54,
PKT_TRANS_WRITE => 55,
PKT_TRANS_READ => 56,
PKT_TRANS_LOCK => 57,
PKT_SRC_ID_H => 74,
PKT_SRC_ID_L => 72,
PKT_DEST_ID_H => 77,
PKT_DEST_ID_L => 75,
PKT_BURSTWRAP_H => 62,
PKT_BURSTWRAP_L => 62,
PKT_BYTE_CNT_H => 61,
PKT_BYTE_CNT_L => 59,
PKT_PROTECTION_H => 81,
PKT_PROTECTION_L => 79,
PKT_RESPONSE_STATUS_H => 87,
PKT_RESPONSE_STATUS_L => 86,
PKT_BURST_SIZE_H => 65,
PKT_BURST_SIZE_L => 63,
ST_CHANNEL_W => 7,
ST_DATA_W => 88,
AVS_BURSTCOUNT_W => 3,
SUPPRESS_0_BYTEEN_CMD => 0,
PREVENT_FIFO_OVERFLOW => 1,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
m0_address => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
m0_burstcount => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
m0_byteenable => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
m0_debugaccess => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
m0_lock => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
m0_readdata => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
m0_readdatavalid => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
m0_read => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_read, -- .read
m0_waitrequest => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
m0_writedata => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
m0_write => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_m0_write, -- .write
rp_endofpacket => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
rp_ready => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
rp_valid => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
rp_data => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rp_data, -- .data
rp_startofpacket => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
cp_ready => width_adapter_002_src_ready, -- cp.ready
cp_valid => width_adapter_002_src_valid, -- .valid
cp_data => width_adapter_002_src_data, -- .data
cp_startofpacket => width_adapter_002_src_startofpacket, -- .startofpacket
cp_endofpacket => width_adapter_002_src_endofpacket, -- .endofpacket
cp_channel => width_adapter_002_src_channel, -- .channel
rf_sink_ready => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
rf_sink_valid => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
rf_sink_startofpacket => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
rf_sink_endofpacket => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
rf_sink_data => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
rf_source_ready => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
rf_source_valid => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
rf_source_startofpacket => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
rf_source_endofpacket => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
rf_source_data => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
rdata_fifo_sink_ready => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_sink.ready
rdata_fifo_sink_valid => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_sink_data => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
rdata_fifo_src_ready => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
rdata_fifo_src_valid => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_src_data => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
m0_response => "00", -- (terminated)
m0_writeresponserequest => open, -- (terminated)
m0_writeresponsevalid => '0' -- (terminated)
);
dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo : component altera_avalon_sc_fifo
generic map (
SYMBOLS_PER_BEAT => 1,
BITS_PER_SYMBOL => 89,
FIFO_DEPTH => 2,
CHANNEL_WIDTH => 0,
ERROR_WIDTH => 0,
USE_PACKETS => 1,
USE_FILL_LEVEL => 0,
EMPTY_LATENCY => 1,
USE_MEMORY_BLOCKS => 0,
USE_STORE_FORWARD => 0,
USE_ALMOST_FULL_IF => 0,
USE_ALMOST_EMPTY_IF => 0
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
in_data => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
in_valid => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
in_ready => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
in_startofpacket => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
in_endofpacket => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
out_data => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
out_valid => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
out_ready => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
out_startofpacket => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
out_endofpacket => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
csr_address => "00", -- (terminated)
csr_read => '0', -- (terminated)
csr_write => '0', -- (terminated)
csr_readdata => open, -- (terminated)
csr_writedata => "00000000000000000000000000000000", -- (terminated)
almost_full_data => open, -- (terminated)
almost_empty_data => open, -- (terminated)
in_empty => '0', -- (terminated)
out_empty => open, -- (terminated)
in_error => '0', -- (terminated)
out_error => open, -- (terminated)
in_channel => '0', -- (terminated)
out_channel => open -- (terminated)
);
fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent : component altera_merlin_slave_agent
generic map (
PKT_DATA_H => 31,
PKT_DATA_L => 0,
PKT_BEGIN_BURST => 70,
PKT_SYMBOL_W => 8,
PKT_BYTEEN_H => 35,
PKT_BYTEEN_L => 32,
PKT_ADDR_H => 52,
PKT_ADDR_L => 36,
PKT_TRANS_COMPRESSED_READ => 53,
PKT_TRANS_POSTED => 54,
PKT_TRANS_WRITE => 55,
PKT_TRANS_READ => 56,
PKT_TRANS_LOCK => 57,
PKT_SRC_ID_H => 74,
PKT_SRC_ID_L => 72,
PKT_DEST_ID_H => 77,
PKT_DEST_ID_L => 75,
PKT_BURSTWRAP_H => 62,
PKT_BURSTWRAP_L => 62,
PKT_BYTE_CNT_H => 61,
PKT_BYTE_CNT_L => 59,
PKT_PROTECTION_H => 81,
PKT_PROTECTION_L => 79,
PKT_RESPONSE_STATUS_H => 87,
PKT_RESPONSE_STATUS_L => 86,
PKT_BURST_SIZE_H => 65,
PKT_BURST_SIZE_L => 63,
ST_CHANNEL_W => 7,
ST_DATA_W => 88,
AVS_BURSTCOUNT_W => 3,
SUPPRESS_0_BYTEEN_CMD => 0,
PREVENT_FIFO_OVERFLOW => 1,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
m0_address => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
m0_burstcount => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
m0_byteenable => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
m0_debugaccess => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
m0_lock => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
m0_readdata => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
m0_readdatavalid => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
m0_read => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read, -- .read
m0_waitrequest => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
m0_writedata => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
m0_write => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write, -- .write
rp_endofpacket => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
rp_ready => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
rp_valid => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
rp_data => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_data, -- .data
rp_startofpacket => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
cp_ready => width_adapter_004_src_ready, -- cp.ready
cp_valid => width_adapter_004_src_valid, -- .valid
cp_data => width_adapter_004_src_data, -- .data
cp_startofpacket => width_adapter_004_src_startofpacket, -- .startofpacket
cp_endofpacket => width_adapter_004_src_endofpacket, -- .endofpacket
cp_channel => width_adapter_004_src_channel, -- .channel
rf_sink_ready => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
rf_sink_valid => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
rf_sink_startofpacket => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
rf_sink_endofpacket => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
rf_sink_data => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
rf_source_ready => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
rf_source_valid => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
rf_source_startofpacket => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
rf_source_endofpacket => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
rf_source_data => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
rdata_fifo_sink_ready => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_sink.ready
rdata_fifo_sink_valid => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_sink_data => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
rdata_fifo_src_ready => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
rdata_fifo_src_valid => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_src_data => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
m0_response => "00", -- (terminated)
m0_writeresponserequest => open, -- (terminated)
m0_writeresponsevalid => '0' -- (terminated)
);
fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo : component altera_avalon_sc_fifo
generic map (
SYMBOLS_PER_BEAT => 1,
BITS_PER_SYMBOL => 89,
FIFO_DEPTH => 2,
CHANNEL_WIDTH => 0,
ERROR_WIDTH => 0,
USE_PACKETS => 1,
USE_FILL_LEVEL => 0,
EMPTY_LATENCY => 1,
USE_MEMORY_BLOCKS => 0,
USE_STORE_FORWARD => 0,
USE_ALMOST_FULL_IF => 0,
USE_ALMOST_EMPTY_IF => 0
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
in_data => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
in_valid => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
in_ready => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
in_startofpacket => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
in_endofpacket => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
out_data => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
out_valid => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
out_ready => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
out_startofpacket => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
out_endofpacket => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
csr_address => "00", -- (terminated)
csr_read => '0', -- (terminated)
csr_write => '0', -- (terminated)
csr_readdata => open, -- (terminated)
csr_writedata => "00000000000000000000000000000000", -- (terminated)
almost_full_data => open, -- (terminated)
almost_empty_data => open, -- (terminated)
in_empty => '0', -- (terminated)
out_empty => open, -- (terminated)
in_error => '0', -- (terminated)
out_error => open, -- (terminated)
in_channel => '0', -- (terminated)
out_channel => open -- (terminated)
);
gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent : component altera_merlin_slave_agent
generic map (
PKT_DATA_H => 31,
PKT_DATA_L => 0,
PKT_BEGIN_BURST => 70,
PKT_SYMBOL_W => 8,
PKT_BYTEEN_H => 35,
PKT_BYTEEN_L => 32,
PKT_ADDR_H => 52,
PKT_ADDR_L => 36,
PKT_TRANS_COMPRESSED_READ => 53,
PKT_TRANS_POSTED => 54,
PKT_TRANS_WRITE => 55,
PKT_TRANS_READ => 56,
PKT_TRANS_LOCK => 57,
PKT_SRC_ID_H => 74,
PKT_SRC_ID_L => 72,
PKT_DEST_ID_H => 77,
PKT_DEST_ID_L => 75,
PKT_BURSTWRAP_H => 62,
PKT_BURSTWRAP_L => 62,
PKT_BYTE_CNT_H => 61,
PKT_BYTE_CNT_L => 59,
PKT_PROTECTION_H => 81,
PKT_PROTECTION_L => 79,
PKT_RESPONSE_STATUS_H => 87,
PKT_RESPONSE_STATUS_L => 86,
PKT_BURST_SIZE_H => 65,
PKT_BURST_SIZE_L => 63,
ST_CHANNEL_W => 7,
ST_DATA_W => 88,
AVS_BURSTCOUNT_W => 3,
SUPPRESS_0_BYTEEN_CMD => 0,
PREVENT_FIFO_OVERFLOW => 1,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
m0_address => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
m0_burstcount => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
m0_byteenable => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
m0_debugaccess => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
m0_lock => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
m0_readdata => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
m0_readdatavalid => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
m0_read => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read, -- .read
m0_waitrequest => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
m0_writedata => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
m0_write => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write, -- .write
rp_endofpacket => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
rp_ready => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
rp_valid => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
rp_data => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_data, -- .data
rp_startofpacket => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
cp_ready => width_adapter_006_src_ready, -- cp.ready
cp_valid => width_adapter_006_src_valid, -- .valid
cp_data => width_adapter_006_src_data, -- .data
cp_startofpacket => width_adapter_006_src_startofpacket, -- .startofpacket
cp_endofpacket => width_adapter_006_src_endofpacket, -- .endofpacket
cp_channel => width_adapter_006_src_channel, -- .channel
rf_sink_ready => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
rf_sink_valid => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
rf_sink_startofpacket => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
rf_sink_endofpacket => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
rf_sink_data => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
rf_source_ready => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
rf_source_valid => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
rf_source_startofpacket => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
rf_source_endofpacket => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
rf_source_data => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
rdata_fifo_sink_ready => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_sink.ready
rdata_fifo_sink_valid => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_sink_data => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
rdata_fifo_src_ready => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
rdata_fifo_src_valid => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_src_data => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
m0_response => "00", -- (terminated)
m0_writeresponserequest => open, -- (terminated)
m0_writeresponsevalid => '0' -- (terminated)
);
gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo : component altera_avalon_sc_fifo
generic map (
SYMBOLS_PER_BEAT => 1,
BITS_PER_SYMBOL => 89,
FIFO_DEPTH => 2,
CHANNEL_WIDTH => 0,
ERROR_WIDTH => 0,
USE_PACKETS => 1,
USE_FILL_LEVEL => 0,
EMPTY_LATENCY => 1,
USE_MEMORY_BLOCKS => 0,
USE_STORE_FORWARD => 0,
USE_ALMOST_FULL_IF => 0,
USE_ALMOST_EMPTY_IF => 0
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
in_data => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
in_valid => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
in_ready => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
in_startofpacket => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
in_endofpacket => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
out_data => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
out_valid => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
out_ready => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
out_startofpacket => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
out_endofpacket => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
csr_address => "00", -- (terminated)
csr_read => '0', -- (terminated)
csr_write => '0', -- (terminated)
csr_readdata => open, -- (terminated)
csr_writedata => "00000000000000000000000000000000", -- (terminated)
almost_full_data => open, -- (terminated)
almost_empty_data => open, -- (terminated)
in_empty => '0', -- (terminated)
out_empty => open, -- (terminated)
in_error => '0', -- (terminated)
out_error => open, -- (terminated)
in_channel => '0', -- (terminated)
out_channel => open -- (terminated)
);
pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent : component altera_merlin_slave_agent
generic map (
PKT_DATA_H => 31,
PKT_DATA_L => 0,
PKT_BEGIN_BURST => 70,
PKT_SYMBOL_W => 8,
PKT_BYTEEN_H => 35,
PKT_BYTEEN_L => 32,
PKT_ADDR_H => 52,
PKT_ADDR_L => 36,
PKT_TRANS_COMPRESSED_READ => 53,
PKT_TRANS_POSTED => 54,
PKT_TRANS_WRITE => 55,
PKT_TRANS_READ => 56,
PKT_TRANS_LOCK => 57,
PKT_SRC_ID_H => 74,
PKT_SRC_ID_L => 72,
PKT_DEST_ID_H => 77,
PKT_DEST_ID_L => 75,
PKT_BURSTWRAP_H => 62,
PKT_BURSTWRAP_L => 62,
PKT_BYTE_CNT_H => 61,
PKT_BYTE_CNT_L => 59,
PKT_PROTECTION_H => 81,
PKT_PROTECTION_L => 79,
PKT_RESPONSE_STATUS_H => 87,
PKT_RESPONSE_STATUS_L => 86,
PKT_BURST_SIZE_H => 65,
PKT_BURST_SIZE_L => 63,
ST_CHANNEL_W => 7,
ST_DATA_W => 88,
AVS_BURSTCOUNT_W => 3,
SUPPRESS_0_BYTEEN_CMD => 0,
PREVENT_FIFO_OVERFLOW => 1,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
m0_address => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
m0_burstcount => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
m0_byteenable => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
m0_debugaccess => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
m0_lock => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
m0_readdata => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
m0_readdatavalid => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
m0_read => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read, -- .read
m0_waitrequest => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
m0_writedata => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
m0_write => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write, -- .write
rp_endofpacket => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
rp_ready => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
rp_valid => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
rp_data => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_data, -- .data
rp_startofpacket => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
cp_ready => width_adapter_008_src_ready, -- cp.ready
cp_valid => width_adapter_008_src_valid, -- .valid
cp_data => width_adapter_008_src_data, -- .data
cp_startofpacket => width_adapter_008_src_startofpacket, -- .startofpacket
cp_endofpacket => width_adapter_008_src_endofpacket, -- .endofpacket
cp_channel => width_adapter_008_src_channel, -- .channel
rf_sink_ready => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
rf_sink_valid => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
rf_sink_startofpacket => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
rf_sink_endofpacket => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
rf_sink_data => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
rf_source_ready => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
rf_source_valid => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
rf_source_startofpacket => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
rf_source_endofpacket => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
rf_source_data => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
rdata_fifo_sink_ready => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_sink.ready
rdata_fifo_sink_valid => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_sink_data => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
rdata_fifo_src_ready => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
rdata_fifo_src_valid => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_src_data => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
m0_response => "00", -- (terminated)
m0_writeresponserequest => open, -- (terminated)
m0_writeresponsevalid => '0' -- (terminated)
);
pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo : component altera_avalon_sc_fifo
generic map (
SYMBOLS_PER_BEAT => 1,
BITS_PER_SYMBOL => 89,
FIFO_DEPTH => 2,
CHANNEL_WIDTH => 0,
ERROR_WIDTH => 0,
USE_PACKETS => 1,
USE_FILL_LEVEL => 0,
EMPTY_LATENCY => 1,
USE_MEMORY_BLOCKS => 0,
USE_STORE_FORWARD => 0,
USE_ALMOST_FULL_IF => 0,
USE_ALMOST_EMPTY_IF => 0
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
in_data => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
in_valid => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
in_ready => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
in_startofpacket => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
in_endofpacket => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
out_data => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
out_valid => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
out_ready => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
out_startofpacket => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
out_endofpacket => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
csr_address => "00", -- (terminated)
csr_read => '0', -- (terminated)
csr_write => '0', -- (terminated)
csr_readdata => open, -- (terminated)
csr_writedata => "00000000000000000000000000000000", -- (terminated)
almost_full_data => open, -- (terminated)
almost_empty_data => open, -- (terminated)
in_empty => '0', -- (terminated)
out_empty => open, -- (terminated)
in_error => '0', -- (terminated)
out_error => open, -- (terminated)
in_channel => '0', -- (terminated)
out_channel => open -- (terminated)
);
gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent : component altera_merlin_slave_agent
generic map (
PKT_DATA_H => 31,
PKT_DATA_L => 0,
PKT_BEGIN_BURST => 70,
PKT_SYMBOL_W => 8,
PKT_BYTEEN_H => 35,
PKT_BYTEEN_L => 32,
PKT_ADDR_H => 52,
PKT_ADDR_L => 36,
PKT_TRANS_COMPRESSED_READ => 53,
PKT_TRANS_POSTED => 54,
PKT_TRANS_WRITE => 55,
PKT_TRANS_READ => 56,
PKT_TRANS_LOCK => 57,
PKT_SRC_ID_H => 74,
PKT_SRC_ID_L => 72,
PKT_DEST_ID_H => 77,
PKT_DEST_ID_L => 75,
PKT_BURSTWRAP_H => 62,
PKT_BURSTWRAP_L => 62,
PKT_BYTE_CNT_H => 61,
PKT_BYTE_CNT_L => 59,
PKT_PROTECTION_H => 81,
PKT_PROTECTION_L => 79,
PKT_RESPONSE_STATUS_H => 87,
PKT_RESPONSE_STATUS_L => 86,
PKT_BURST_SIZE_H => 65,
PKT_BURST_SIZE_L => 63,
ST_CHANNEL_W => 7,
ST_DATA_W => 88,
AVS_BURSTCOUNT_W => 3,
SUPPRESS_0_BYTEEN_CMD => 0,
PREVENT_FIFO_OVERFLOW => 1,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
m0_address => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
m0_burstcount => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
m0_byteenable => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
m0_debugaccess => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
m0_lock => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
m0_readdata => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
m0_readdatavalid => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
m0_read => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read, -- .read
m0_waitrequest => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
m0_writedata => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
m0_write => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write, -- .write
rp_endofpacket => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
rp_ready => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
rp_valid => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
rp_data => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_data, -- .data
rp_startofpacket => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
cp_ready => width_adapter_010_src_ready, -- cp.ready
cp_valid => width_adapter_010_src_valid, -- .valid
cp_data => width_adapter_010_src_data, -- .data
cp_startofpacket => width_adapter_010_src_startofpacket, -- .startofpacket
cp_endofpacket => width_adapter_010_src_endofpacket, -- .endofpacket
cp_channel => width_adapter_010_src_channel, -- .channel
rf_sink_ready => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
rf_sink_valid => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
rf_sink_startofpacket => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
rf_sink_endofpacket => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
rf_sink_data => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
rf_source_ready => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
rf_source_valid => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
rf_source_startofpacket => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
rf_source_endofpacket => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
rf_source_data => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
rdata_fifo_sink_ready => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_sink.ready
rdata_fifo_sink_valid => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_sink_data => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
rdata_fifo_src_ready => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
rdata_fifo_src_valid => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_src_data => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
m0_response => "00", -- (terminated)
m0_writeresponserequest => open, -- (terminated)
m0_writeresponsevalid => '0' -- (terminated)
);
gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo : component altera_avalon_sc_fifo
generic map (
SYMBOLS_PER_BEAT => 1,
BITS_PER_SYMBOL => 89,
FIFO_DEPTH => 2,
CHANNEL_WIDTH => 0,
ERROR_WIDTH => 0,
USE_PACKETS => 1,
USE_FILL_LEVEL => 0,
EMPTY_LATENCY => 1,
USE_MEMORY_BLOCKS => 0,
USE_STORE_FORWARD => 0,
USE_ALMOST_FULL_IF => 0,
USE_ALMOST_EMPTY_IF => 0
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
in_data => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
in_valid => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
in_ready => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
in_startofpacket => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
in_endofpacket => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
out_data => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
out_valid => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
out_ready => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
out_startofpacket => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
out_endofpacket => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
csr_address => "00", -- (terminated)
csr_read => '0', -- (terminated)
csr_write => '0', -- (terminated)
csr_readdata => open, -- (terminated)
csr_writedata => "00000000000000000000000000000000", -- (terminated)
almost_full_data => open, -- (terminated)
almost_empty_data => open, -- (terminated)
in_empty => '0', -- (terminated)
out_empty => open, -- (terminated)
in_error => '0', -- (terminated)
out_error => open, -- (terminated)
in_channel => '0', -- (terminated)
out_channel => open -- (terminated)
);
mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent : component altera_merlin_slave_agent
generic map (
PKT_DATA_H => 31,
PKT_DATA_L => 0,
PKT_BEGIN_BURST => 70,
PKT_SYMBOL_W => 8,
PKT_BYTEEN_H => 35,
PKT_BYTEEN_L => 32,
PKT_ADDR_H => 52,
PKT_ADDR_L => 36,
PKT_TRANS_COMPRESSED_READ => 53,
PKT_TRANS_POSTED => 54,
PKT_TRANS_WRITE => 55,
PKT_TRANS_READ => 56,
PKT_TRANS_LOCK => 57,
PKT_SRC_ID_H => 74,
PKT_SRC_ID_L => 72,
PKT_DEST_ID_H => 77,
PKT_DEST_ID_L => 75,
PKT_BURSTWRAP_H => 62,
PKT_BURSTWRAP_L => 62,
PKT_BYTE_CNT_H => 61,
PKT_BYTE_CNT_L => 59,
PKT_PROTECTION_H => 81,
PKT_PROTECTION_L => 79,
PKT_RESPONSE_STATUS_H => 87,
PKT_RESPONSE_STATUS_L => 86,
PKT_BURST_SIZE_H => 65,
PKT_BURST_SIZE_L => 63,
ST_CHANNEL_W => 7,
ST_DATA_W => 88,
AVS_BURSTCOUNT_W => 3,
SUPPRESS_0_BYTEEN_CMD => 0,
PREVENT_FIFO_OVERFLOW => 1,
USE_READRESPONSE => 0,
USE_WRITERESPONSE => 0
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
m0_address => mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
m0_burstcount => mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
m0_byteenable => mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
m0_debugaccess => mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
m0_lock => mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
m0_readdata => mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
m0_readdatavalid => mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
m0_read => mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read, -- .read
m0_waitrequest => mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
m0_writedata => mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
m0_write => mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write, -- .write
rp_endofpacket => mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
rp_ready => mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
rp_valid => mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
rp_data => mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_data, -- .data
rp_startofpacket => mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
cp_ready => width_adapter_012_src_ready, -- cp.ready
cp_valid => width_adapter_012_src_valid, -- .valid
cp_data => width_adapter_012_src_data, -- .data
cp_startofpacket => width_adapter_012_src_startofpacket, -- .startofpacket
cp_endofpacket => width_adapter_012_src_endofpacket, -- .endofpacket
cp_channel => width_adapter_012_src_channel, -- .channel
rf_sink_ready => mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
rf_sink_valid => mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
rf_sink_startofpacket => mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
rf_sink_endofpacket => mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
rf_sink_data => mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
rf_source_ready => mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
rf_source_valid => mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
rf_source_startofpacket => mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
rf_source_endofpacket => mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
rf_source_data => mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
rdata_fifo_sink_ready => mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_sink.ready
rdata_fifo_sink_valid => mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_sink_data => mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
rdata_fifo_src_ready => mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
rdata_fifo_src_valid => mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_src_data => mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
m0_response => "00", -- (terminated)
m0_writeresponserequest => open, -- (terminated)
m0_writeresponsevalid => '0' -- (terminated)
);
mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo : component altera_avalon_sc_fifo
generic map (
SYMBOLS_PER_BEAT => 1,
BITS_PER_SYMBOL => 89,
FIFO_DEPTH => 2,
CHANNEL_WIDTH => 0,
ERROR_WIDTH => 0,
USE_PACKETS => 1,
USE_FILL_LEVEL => 0,
EMPTY_LATENCY => 1,
USE_MEMORY_BLOCKS => 0,
USE_STORE_FORWARD => 0,
USE_ALMOST_FULL_IF => 0,
USE_ALMOST_EMPTY_IF => 0
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
in_data => mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
in_valid => mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
in_ready => mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
in_startofpacket => mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
in_endofpacket => mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
out_data => mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
out_valid => mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
out_ready => mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
out_startofpacket => mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
out_endofpacket => mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
csr_address => "00", -- (terminated)
csr_read => '0', -- (terminated)
csr_write => '0', -- (terminated)
csr_readdata => open, -- (terminated)
csr_writedata => "00000000000000000000000000000000", -- (terminated)
almost_full_data => open, -- (terminated)
almost_empty_data => open, -- (terminated)
in_empty => '0', -- (terminated)
out_empty => open, -- (terminated)
in_error => '0', -- (terminated)
out_error => open, -- (terminated)
in_channel => '0', -- (terminated)
out_channel => open -- (terminated)
);
addr_router : component cb20_addr_router
port map (
sink_ready => eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_agent_cp_ready, -- sink.ready
sink_valid => eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_agent_cp_valid, -- .valid
sink_data => eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_agent_cp_data, -- .data
sink_startofpacket => eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_agent_cp_startofpacket, -- .startofpacket
sink_endofpacket => eim_slave_to_avalon_master_0_avalon_master_translator_avalon_universal_master_0_agent_cp_endofpacket, -- .endofpacket
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
src_ready => addr_router_src_ready, -- src.ready
src_valid => addr_router_src_valid, -- .valid
src_data => addr_router_src_data, -- .data
src_channel => addr_router_src_channel, -- .channel
src_startofpacket => addr_router_src_startofpacket, -- .startofpacket
src_endofpacket => addr_router_src_endofpacket -- .endofpacket
);
id_router : component cb20_id_router
port map (
sink_ready => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
sink_valid => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
sink_data => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rp_data, -- .data
sink_startofpacket => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
sink_endofpacket => info_device_0_avalon_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
src_ready => id_router_src_ready, -- src.ready
src_valid => id_router_src_valid, -- .valid
src_data => id_router_src_data, -- .data
src_channel => id_router_src_channel, -- .channel
src_startofpacket => id_router_src_startofpacket, -- .startofpacket
src_endofpacket => id_router_src_endofpacket -- .endofpacket
);
id_router_001 : component cb20_id_router
port map (
sink_ready => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
sink_valid => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
sink_data => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rp_data, -- .data
sink_startofpacket => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
sink_endofpacket => dacad5668_0_avalon_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
src_ready => id_router_001_src_ready, -- src.ready
src_valid => id_router_001_src_valid, -- .valid
src_data => id_router_001_src_data, -- .data
src_channel => id_router_001_src_channel, -- .channel
src_startofpacket => id_router_001_src_startofpacket, -- .startofpacket
src_endofpacket => id_router_001_src_endofpacket -- .endofpacket
);
id_router_002 : component cb20_id_router
port map (
sink_ready => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
sink_valid => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
sink_data => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_data, -- .data
sink_startofpacket => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
sink_endofpacket => fqd_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
src_ready => id_router_002_src_ready, -- src.ready
src_valid => id_router_002_src_valid, -- .valid
src_data => id_router_002_src_data, -- .data
src_channel => id_router_002_src_channel, -- .channel
src_startofpacket => id_router_002_src_startofpacket, -- .startofpacket
src_endofpacket => id_router_002_src_endofpacket -- .endofpacket
);
id_router_003 : component cb20_id_router
port map (
sink_ready => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
sink_valid => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
sink_data => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_data, -- .data
sink_startofpacket => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
sink_endofpacket => gpio_block_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
src_ready => id_router_003_src_ready, -- src.ready
src_valid => id_router_003_src_valid, -- .valid
src_data => id_router_003_src_data, -- .data
src_channel => id_router_003_src_channel, -- .channel
src_startofpacket => id_router_003_src_startofpacket, -- .startofpacket
src_endofpacket => id_router_003_src_endofpacket -- .endofpacket
);
id_router_004 : component cb20_id_router
port map (
sink_ready => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
sink_valid => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
sink_data => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_data, -- .data
sink_startofpacket => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
sink_endofpacket => pwm_interface_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
src_ready => id_router_004_src_ready, -- src.ready
src_valid => id_router_004_src_valid, -- .valid
src_data => id_router_004_src_data, -- .data
src_channel => id_router_004_src_channel, -- .channel
src_startofpacket => id_router_004_src_startofpacket, -- .startofpacket
src_endofpacket => id_router_004_src_endofpacket -- .endofpacket
);
id_router_005 : component cb20_id_router
port map (
sink_ready => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
sink_valid => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
sink_data => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_data, -- .data
sink_startofpacket => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
sink_endofpacket => gpio_block_1_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
src_ready => id_router_005_src_ready, -- src.ready
src_valid => id_router_005_src_valid, -- .valid
src_data => id_router_005_src_data, -- .data
src_channel => id_router_005_src_channel, -- .channel
src_startofpacket => id_router_005_src_startofpacket, -- .startofpacket
src_endofpacket => id_router_005_src_endofpacket -- .endofpacket
);
id_router_006 : component cb20_id_router
port map (
sink_ready => mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
sink_valid => mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
sink_data => mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_data, -- .data
sink_startofpacket => mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
sink_endofpacket => mpu9250_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
src_ready => id_router_006_src_ready, -- src.ready
src_valid => id_router_006_src_valid, -- .valid
src_data => id_router_006_src_data, -- .data
src_channel => id_router_006_src_channel, -- .channel
src_startofpacket => id_router_006_src_startofpacket, -- .startofpacket
src_endofpacket => id_router_006_src_endofpacket -- .endofpacket
);
rst_controller : component altera_reset_controller
generic map (
NUM_RESET_INPUTS => 1,
OUTPUT_RESET_SYNC_EDGES => "deassert",
SYNC_DEPTH => 2,
RESET_REQUEST_PRESENT => 0
)
port map (
reset_in0 => reset_reset_n_ports_inv, -- reset_in0.reset
clk => clk_clk, -- clk.clk
reset_out => rst_controller_reset_out_reset, -- reset_out.reset
reset_req => open, -- (terminated)
reset_in1 => '0', -- (terminated)
reset_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_in15 => '0' -- (terminated)
);
rst_controller_001 : component altera_reset_controller
generic map (
NUM_RESET_INPUTS => 1,
OUTPUT_RESET_SYNC_EDGES => "deassert",
SYNC_DEPTH => 2,
RESET_REQUEST_PRESENT => 0
)
port map (
reset_in0 => reset_reset_n_ports_inv, -- reset_in0.reset
clk => altpll_0_c0_clk, -- clk.clk
reset_out => rst_controller_001_reset_out_reset, -- reset_out.reset
reset_req => open, -- (terminated)
reset_in1 => '0', -- (terminated)
reset_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_in15 => '0' -- (terminated)
);
cmd_xbar_demux : component cb20_cmd_xbar_demux
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
sink_ready => addr_router_src_ready, -- sink.ready
sink_channel => addr_router_src_channel, -- .channel
sink_data => addr_router_src_data, -- .data
sink_startofpacket => addr_router_src_startofpacket, -- .startofpacket
sink_endofpacket => addr_router_src_endofpacket, -- .endofpacket
sink_valid(0) => addr_router_src_valid, -- .valid
src0_ready => cmd_xbar_demux_src0_ready, -- src0.ready
src0_valid => cmd_xbar_demux_src0_valid, -- .valid
src0_data => cmd_xbar_demux_src0_data, -- .data
src0_channel => cmd_xbar_demux_src0_channel, -- .channel
src0_startofpacket => cmd_xbar_demux_src0_startofpacket, -- .startofpacket
src0_endofpacket => cmd_xbar_demux_src0_endofpacket, -- .endofpacket
src1_ready => cmd_xbar_demux_src1_ready, -- src1.ready
src1_valid => cmd_xbar_demux_src1_valid, -- .valid
src1_data => cmd_xbar_demux_src1_data, -- .data
src1_channel => cmd_xbar_demux_src1_channel, -- .channel
src1_startofpacket => cmd_xbar_demux_src1_startofpacket, -- .startofpacket
src1_endofpacket => cmd_xbar_demux_src1_endofpacket, -- .endofpacket
src2_ready => cmd_xbar_demux_src2_ready, -- src2.ready
src2_valid => cmd_xbar_demux_src2_valid, -- .valid
src2_data => cmd_xbar_demux_src2_data, -- .data
src2_channel => cmd_xbar_demux_src2_channel, -- .channel
src2_startofpacket => cmd_xbar_demux_src2_startofpacket, -- .startofpacket
src2_endofpacket => cmd_xbar_demux_src2_endofpacket, -- .endofpacket
src3_ready => cmd_xbar_demux_src3_ready, -- src3.ready
src3_valid => cmd_xbar_demux_src3_valid, -- .valid
src3_data => cmd_xbar_demux_src3_data, -- .data
src3_channel => cmd_xbar_demux_src3_channel, -- .channel
src3_startofpacket => cmd_xbar_demux_src3_startofpacket, -- .startofpacket
src3_endofpacket => cmd_xbar_demux_src3_endofpacket, -- .endofpacket
src4_ready => cmd_xbar_demux_src4_ready, -- src4.ready
src4_valid => cmd_xbar_demux_src4_valid, -- .valid
src4_data => cmd_xbar_demux_src4_data, -- .data
src4_channel => cmd_xbar_demux_src4_channel, -- .channel
src4_startofpacket => cmd_xbar_demux_src4_startofpacket, -- .startofpacket
src4_endofpacket => cmd_xbar_demux_src4_endofpacket, -- .endofpacket
src5_ready => cmd_xbar_demux_src5_ready, -- src5.ready
src5_valid => cmd_xbar_demux_src5_valid, -- .valid
src5_data => cmd_xbar_demux_src5_data, -- .data
src5_channel => cmd_xbar_demux_src5_channel, -- .channel
src5_startofpacket => cmd_xbar_demux_src5_startofpacket, -- .startofpacket
src5_endofpacket => cmd_xbar_demux_src5_endofpacket, -- .endofpacket
src6_ready => cmd_xbar_demux_src6_ready, -- src6.ready
src6_valid => cmd_xbar_demux_src6_valid, -- .valid
src6_data => cmd_xbar_demux_src6_data, -- .data
src6_channel => cmd_xbar_demux_src6_channel, -- .channel
src6_startofpacket => cmd_xbar_demux_src6_startofpacket, -- .startofpacket
src6_endofpacket => cmd_xbar_demux_src6_endofpacket -- .endofpacket
);
rsp_xbar_demux : component cb20_rsp_xbar_demux
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
sink_ready => width_adapter_001_src_ready, -- sink.ready
sink_channel => width_adapter_001_src_channel, -- .channel
sink_data => width_adapter_001_src_data, -- .data
sink_startofpacket => width_adapter_001_src_startofpacket, -- .startofpacket
sink_endofpacket => width_adapter_001_src_endofpacket, -- .endofpacket
sink_valid(0) => width_adapter_001_src_valid, -- .valid
src0_ready => rsp_xbar_demux_src0_ready, -- src0.ready
src0_valid => rsp_xbar_demux_src0_valid, -- .valid
src0_data => rsp_xbar_demux_src0_data, -- .data
src0_channel => rsp_xbar_demux_src0_channel, -- .channel
src0_startofpacket => rsp_xbar_demux_src0_startofpacket, -- .startofpacket
src0_endofpacket => rsp_xbar_demux_src0_endofpacket -- .endofpacket
);
rsp_xbar_demux_001 : component cb20_rsp_xbar_demux
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
sink_ready => width_adapter_003_src_ready, -- sink.ready
sink_channel => width_adapter_003_src_channel, -- .channel
sink_data => width_adapter_003_src_data, -- .data
sink_startofpacket => width_adapter_003_src_startofpacket, -- .startofpacket
sink_endofpacket => width_adapter_003_src_endofpacket, -- .endofpacket
sink_valid(0) => width_adapter_003_src_valid, -- .valid
src0_ready => rsp_xbar_demux_001_src0_ready, -- src0.ready
src0_valid => rsp_xbar_demux_001_src0_valid, -- .valid
src0_data => rsp_xbar_demux_001_src0_data, -- .data
src0_channel => rsp_xbar_demux_001_src0_channel, -- .channel
src0_startofpacket => rsp_xbar_demux_001_src0_startofpacket, -- .startofpacket
src0_endofpacket => rsp_xbar_demux_001_src0_endofpacket -- .endofpacket
);
rsp_xbar_demux_002 : component cb20_rsp_xbar_demux
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
sink_ready => width_adapter_005_src_ready, -- sink.ready
sink_channel => width_adapter_005_src_channel, -- .channel
sink_data => width_adapter_005_src_data, -- .data
sink_startofpacket => width_adapter_005_src_startofpacket, -- .startofpacket
sink_endofpacket => width_adapter_005_src_endofpacket, -- .endofpacket
sink_valid(0) => width_adapter_005_src_valid, -- .valid
src0_ready => rsp_xbar_demux_002_src0_ready, -- src0.ready
src0_valid => rsp_xbar_demux_002_src0_valid, -- .valid
src0_data => rsp_xbar_demux_002_src0_data, -- .data
src0_channel => rsp_xbar_demux_002_src0_channel, -- .channel
src0_startofpacket => rsp_xbar_demux_002_src0_startofpacket, -- .startofpacket
src0_endofpacket => rsp_xbar_demux_002_src0_endofpacket -- .endofpacket
);
rsp_xbar_demux_003 : component cb20_rsp_xbar_demux
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
sink_ready => width_adapter_007_src_ready, -- sink.ready
sink_channel => width_adapter_007_src_channel, -- .channel
sink_data => width_adapter_007_src_data, -- .data
sink_startofpacket => width_adapter_007_src_startofpacket, -- .startofpacket
sink_endofpacket => width_adapter_007_src_endofpacket, -- .endofpacket
sink_valid(0) => width_adapter_007_src_valid, -- .valid
src0_ready => rsp_xbar_demux_003_src0_ready, -- src0.ready
src0_valid => rsp_xbar_demux_003_src0_valid, -- .valid
src0_data => rsp_xbar_demux_003_src0_data, -- .data
src0_channel => rsp_xbar_demux_003_src0_channel, -- .channel
src0_startofpacket => rsp_xbar_demux_003_src0_startofpacket, -- .startofpacket
src0_endofpacket => rsp_xbar_demux_003_src0_endofpacket -- .endofpacket
);
rsp_xbar_demux_004 : component cb20_rsp_xbar_demux
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
sink_ready => width_adapter_009_src_ready, -- sink.ready
sink_channel => width_adapter_009_src_channel, -- .channel
sink_data => width_adapter_009_src_data, -- .data
sink_startofpacket => width_adapter_009_src_startofpacket, -- .startofpacket
sink_endofpacket => width_adapter_009_src_endofpacket, -- .endofpacket
sink_valid(0) => width_adapter_009_src_valid, -- .valid
src0_ready => rsp_xbar_demux_004_src0_ready, -- src0.ready
src0_valid => rsp_xbar_demux_004_src0_valid, -- .valid
src0_data => rsp_xbar_demux_004_src0_data, -- .data
src0_channel => rsp_xbar_demux_004_src0_channel, -- .channel
src0_startofpacket => rsp_xbar_demux_004_src0_startofpacket, -- .startofpacket
src0_endofpacket => rsp_xbar_demux_004_src0_endofpacket -- .endofpacket
);
rsp_xbar_demux_005 : component cb20_rsp_xbar_demux
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
sink_ready => width_adapter_011_src_ready, -- sink.ready
sink_channel => width_adapter_011_src_channel, -- .channel
sink_data => width_adapter_011_src_data, -- .data
sink_startofpacket => width_adapter_011_src_startofpacket, -- .startofpacket
sink_endofpacket => width_adapter_011_src_endofpacket, -- .endofpacket
sink_valid(0) => width_adapter_011_src_valid, -- .valid
src0_ready => rsp_xbar_demux_005_src0_ready, -- src0.ready
src0_valid => rsp_xbar_demux_005_src0_valid, -- .valid
src0_data => rsp_xbar_demux_005_src0_data, -- .data
src0_channel => rsp_xbar_demux_005_src0_channel, -- .channel
src0_startofpacket => rsp_xbar_demux_005_src0_startofpacket, -- .startofpacket
src0_endofpacket => rsp_xbar_demux_005_src0_endofpacket -- .endofpacket
);
rsp_xbar_demux_006 : component cb20_rsp_xbar_demux
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
sink_ready => width_adapter_013_src_ready, -- sink.ready
sink_channel => width_adapter_013_src_channel, -- .channel
sink_data => width_adapter_013_src_data, -- .data
sink_startofpacket => width_adapter_013_src_startofpacket, -- .startofpacket
sink_endofpacket => width_adapter_013_src_endofpacket, -- .endofpacket
sink_valid(0) => width_adapter_013_src_valid, -- .valid
src0_ready => rsp_xbar_demux_006_src0_ready, -- src0.ready
src0_valid => rsp_xbar_demux_006_src0_valid, -- .valid
src0_data => rsp_xbar_demux_006_src0_data, -- .data
src0_channel => rsp_xbar_demux_006_src0_channel, -- .channel
src0_startofpacket => rsp_xbar_demux_006_src0_startofpacket, -- .startofpacket
src0_endofpacket => rsp_xbar_demux_006_src0_endofpacket -- .endofpacket
);
rsp_xbar_mux : component cb20_rsp_xbar_mux
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
src_ready => rsp_xbar_mux_src_ready, -- src.ready
src_valid => rsp_xbar_mux_src_valid, -- .valid
src_data => rsp_xbar_mux_src_data, -- .data
src_channel => rsp_xbar_mux_src_channel, -- .channel
src_startofpacket => rsp_xbar_mux_src_startofpacket, -- .startofpacket
src_endofpacket => rsp_xbar_mux_src_endofpacket, -- .endofpacket
sink0_ready => rsp_xbar_demux_src0_ready, -- sink0.ready
sink0_valid => rsp_xbar_demux_src0_valid, -- .valid
sink0_channel => rsp_xbar_demux_src0_channel, -- .channel
sink0_data => rsp_xbar_demux_src0_data, -- .data
sink0_startofpacket => rsp_xbar_demux_src0_startofpacket, -- .startofpacket
sink0_endofpacket => rsp_xbar_demux_src0_endofpacket, -- .endofpacket
sink1_ready => rsp_xbar_demux_001_src0_ready, -- sink1.ready
sink1_valid => rsp_xbar_demux_001_src0_valid, -- .valid
sink1_channel => rsp_xbar_demux_001_src0_channel, -- .channel
sink1_data => rsp_xbar_demux_001_src0_data, -- .data
sink1_startofpacket => rsp_xbar_demux_001_src0_startofpacket, -- .startofpacket
sink1_endofpacket => rsp_xbar_demux_001_src0_endofpacket, -- .endofpacket
sink2_ready => rsp_xbar_demux_002_src0_ready, -- sink2.ready
sink2_valid => rsp_xbar_demux_002_src0_valid, -- .valid
sink2_channel => rsp_xbar_demux_002_src0_channel, -- .channel
sink2_data => rsp_xbar_demux_002_src0_data, -- .data
sink2_startofpacket => rsp_xbar_demux_002_src0_startofpacket, -- .startofpacket
sink2_endofpacket => rsp_xbar_demux_002_src0_endofpacket, -- .endofpacket
sink3_ready => rsp_xbar_demux_003_src0_ready, -- sink3.ready
sink3_valid => rsp_xbar_demux_003_src0_valid, -- .valid
sink3_channel => rsp_xbar_demux_003_src0_channel, -- .channel
sink3_data => rsp_xbar_demux_003_src0_data, -- .data
sink3_startofpacket => rsp_xbar_demux_003_src0_startofpacket, -- .startofpacket
sink3_endofpacket => rsp_xbar_demux_003_src0_endofpacket, -- .endofpacket
sink4_ready => rsp_xbar_demux_004_src0_ready, -- sink4.ready
sink4_valid => rsp_xbar_demux_004_src0_valid, -- .valid
sink4_channel => rsp_xbar_demux_004_src0_channel, -- .channel
sink4_data => rsp_xbar_demux_004_src0_data, -- .data
sink4_startofpacket => rsp_xbar_demux_004_src0_startofpacket, -- .startofpacket
sink4_endofpacket => rsp_xbar_demux_004_src0_endofpacket, -- .endofpacket
sink5_ready => rsp_xbar_demux_005_src0_ready, -- sink5.ready
sink5_valid => rsp_xbar_demux_005_src0_valid, -- .valid
sink5_channel => rsp_xbar_demux_005_src0_channel, -- .channel
sink5_data => rsp_xbar_demux_005_src0_data, -- .data
sink5_startofpacket => rsp_xbar_demux_005_src0_startofpacket, -- .startofpacket
sink5_endofpacket => rsp_xbar_demux_005_src0_endofpacket, -- .endofpacket
sink6_ready => rsp_xbar_demux_006_src0_ready, -- sink6.ready
sink6_valid => rsp_xbar_demux_006_src0_valid, -- .valid
sink6_channel => rsp_xbar_demux_006_src0_channel, -- .channel
sink6_data => rsp_xbar_demux_006_src0_data, -- .data
sink6_startofpacket => rsp_xbar_demux_006_src0_startofpacket, -- .startofpacket
sink6_endofpacket => rsp_xbar_demux_006_src0_endofpacket -- .endofpacket
);
width_adapter : component cb20_width_adapter
generic map (
IN_PKT_ADDR_H => 34,
IN_PKT_ADDR_L => 18,
IN_PKT_DATA_H => 15,
IN_PKT_DATA_L => 0,
IN_PKT_BYTEEN_H => 17,
IN_PKT_BYTEEN_L => 16,
IN_PKT_BYTE_CNT_H => 43,
IN_PKT_BYTE_CNT_L => 41,
IN_PKT_TRANS_COMPRESSED_READ => 35,
IN_PKT_BURSTWRAP_H => 44,
IN_PKT_BURSTWRAP_L => 44,
IN_PKT_BURST_SIZE_H => 47,
IN_PKT_BURST_SIZE_L => 45,
IN_PKT_RESPONSE_STATUS_H => 69,
IN_PKT_RESPONSE_STATUS_L => 68,
IN_PKT_TRANS_EXCLUSIVE => 40,
IN_PKT_BURST_TYPE_H => 49,
IN_PKT_BURST_TYPE_L => 48,
IN_ST_DATA_W => 70,
OUT_PKT_ADDR_H => 52,
OUT_PKT_ADDR_L => 36,
OUT_PKT_DATA_H => 31,
OUT_PKT_DATA_L => 0,
OUT_PKT_BYTEEN_H => 35,
OUT_PKT_BYTEEN_L => 32,
OUT_PKT_BYTE_CNT_H => 61,
OUT_PKT_BYTE_CNT_L => 59,
OUT_PKT_TRANS_COMPRESSED_READ => 53,
OUT_PKT_BURST_SIZE_H => 65,
OUT_PKT_BURST_SIZE_L => 63,
OUT_PKT_RESPONSE_STATUS_H => 87,
OUT_PKT_RESPONSE_STATUS_L => 86,
OUT_PKT_TRANS_EXCLUSIVE => 58,
OUT_PKT_BURST_TYPE_H => 67,
OUT_PKT_BURST_TYPE_L => 66,
OUT_ST_DATA_W => 88,
ST_CHANNEL_W => 7,
OPTIMIZE_FOR_RSP => 0,
RESPONSE_PATH => 0
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
in_valid => cmd_xbar_demux_src0_valid, -- sink.valid
in_channel => cmd_xbar_demux_src0_channel, -- .channel
in_startofpacket => cmd_xbar_demux_src0_startofpacket, -- .startofpacket
in_endofpacket => cmd_xbar_demux_src0_endofpacket, -- .endofpacket
in_ready => cmd_xbar_demux_src0_ready, -- .ready
in_data => cmd_xbar_demux_src0_data, -- .data
out_endofpacket => width_adapter_src_endofpacket, -- src.endofpacket
out_data => width_adapter_src_data, -- .data
out_channel => width_adapter_src_channel, -- .channel
out_valid => width_adapter_src_valid, -- .valid
out_ready => width_adapter_src_ready, -- .ready
out_startofpacket => width_adapter_src_startofpacket, -- .startofpacket
in_command_size_data => "000" -- (terminated)
);
width_adapter_001 : component cb20_width_adapter_001
generic map (
IN_PKT_ADDR_H => 52,
IN_PKT_ADDR_L => 36,
IN_PKT_DATA_H => 31,
IN_PKT_DATA_L => 0,
IN_PKT_BYTEEN_H => 35,
IN_PKT_BYTEEN_L => 32,
IN_PKT_BYTE_CNT_H => 61,
IN_PKT_BYTE_CNT_L => 59,
IN_PKT_TRANS_COMPRESSED_READ => 53,
IN_PKT_BURSTWRAP_H => 62,
IN_PKT_BURSTWRAP_L => 62,
IN_PKT_BURST_SIZE_H => 65,
IN_PKT_BURST_SIZE_L => 63,
IN_PKT_RESPONSE_STATUS_H => 87,
IN_PKT_RESPONSE_STATUS_L => 86,
IN_PKT_TRANS_EXCLUSIVE => 58,
IN_PKT_BURST_TYPE_H => 67,
IN_PKT_BURST_TYPE_L => 66,
IN_ST_DATA_W => 88,
OUT_PKT_ADDR_H => 34,
OUT_PKT_ADDR_L => 18,
OUT_PKT_DATA_H => 15,
OUT_PKT_DATA_L => 0,
OUT_PKT_BYTEEN_H => 17,
OUT_PKT_BYTEEN_L => 16,
OUT_PKT_BYTE_CNT_H => 43,
OUT_PKT_BYTE_CNT_L => 41,
OUT_PKT_TRANS_COMPRESSED_READ => 35,
OUT_PKT_BURST_SIZE_H => 47,
OUT_PKT_BURST_SIZE_L => 45,
OUT_PKT_RESPONSE_STATUS_H => 69,
OUT_PKT_RESPONSE_STATUS_L => 68,
OUT_PKT_TRANS_EXCLUSIVE => 40,
OUT_PKT_BURST_TYPE_H => 49,
OUT_PKT_BURST_TYPE_L => 48,
OUT_ST_DATA_W => 70,
ST_CHANNEL_W => 7,
OPTIMIZE_FOR_RSP => 1,
RESPONSE_PATH => 1
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
in_valid => id_router_src_valid, -- sink.valid
in_channel => id_router_src_channel, -- .channel
in_startofpacket => id_router_src_startofpacket, -- .startofpacket
in_endofpacket => id_router_src_endofpacket, -- .endofpacket
in_ready => id_router_src_ready, -- .ready
in_data => id_router_src_data, -- .data
out_endofpacket => width_adapter_001_src_endofpacket, -- src.endofpacket
out_data => width_adapter_001_src_data, -- .data
out_channel => width_adapter_001_src_channel, -- .channel
out_valid => width_adapter_001_src_valid, -- .valid
out_ready => width_adapter_001_src_ready, -- .ready
out_startofpacket => width_adapter_001_src_startofpacket, -- .startofpacket
in_command_size_data => "000" -- (terminated)
);
width_adapter_002 : component cb20_width_adapter
generic map (
IN_PKT_ADDR_H => 34,
IN_PKT_ADDR_L => 18,
IN_PKT_DATA_H => 15,
IN_PKT_DATA_L => 0,
IN_PKT_BYTEEN_H => 17,
IN_PKT_BYTEEN_L => 16,
IN_PKT_BYTE_CNT_H => 43,
IN_PKT_BYTE_CNT_L => 41,
IN_PKT_TRANS_COMPRESSED_READ => 35,
IN_PKT_BURSTWRAP_H => 44,
IN_PKT_BURSTWRAP_L => 44,
IN_PKT_BURST_SIZE_H => 47,
IN_PKT_BURST_SIZE_L => 45,
IN_PKT_RESPONSE_STATUS_H => 69,
IN_PKT_RESPONSE_STATUS_L => 68,
IN_PKT_TRANS_EXCLUSIVE => 40,
IN_PKT_BURST_TYPE_H => 49,
IN_PKT_BURST_TYPE_L => 48,
IN_ST_DATA_W => 70,
OUT_PKT_ADDR_H => 52,
OUT_PKT_ADDR_L => 36,
OUT_PKT_DATA_H => 31,
OUT_PKT_DATA_L => 0,
OUT_PKT_BYTEEN_H => 35,
OUT_PKT_BYTEEN_L => 32,
OUT_PKT_BYTE_CNT_H => 61,
OUT_PKT_BYTE_CNT_L => 59,
OUT_PKT_TRANS_COMPRESSED_READ => 53,
OUT_PKT_BURST_SIZE_H => 65,
OUT_PKT_BURST_SIZE_L => 63,
OUT_PKT_RESPONSE_STATUS_H => 87,
OUT_PKT_RESPONSE_STATUS_L => 86,
OUT_PKT_TRANS_EXCLUSIVE => 58,
OUT_PKT_BURST_TYPE_H => 67,
OUT_PKT_BURST_TYPE_L => 66,
OUT_ST_DATA_W => 88,
ST_CHANNEL_W => 7,
OPTIMIZE_FOR_RSP => 0,
RESPONSE_PATH => 0
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
in_valid => cmd_xbar_demux_src1_valid, -- sink.valid
in_channel => cmd_xbar_demux_src1_channel, -- .channel
in_startofpacket => cmd_xbar_demux_src1_startofpacket, -- .startofpacket
in_endofpacket => cmd_xbar_demux_src1_endofpacket, -- .endofpacket
in_ready => cmd_xbar_demux_src1_ready, -- .ready
in_data => cmd_xbar_demux_src1_data, -- .data
out_endofpacket => width_adapter_002_src_endofpacket, -- src.endofpacket
out_data => width_adapter_002_src_data, -- .data
out_channel => width_adapter_002_src_channel, -- .channel
out_valid => width_adapter_002_src_valid, -- .valid
out_ready => width_adapter_002_src_ready, -- .ready
out_startofpacket => width_adapter_002_src_startofpacket, -- .startofpacket
in_command_size_data => "000" -- (terminated)
);
width_adapter_003 : component cb20_width_adapter_001
generic map (
IN_PKT_ADDR_H => 52,
IN_PKT_ADDR_L => 36,
IN_PKT_DATA_H => 31,
IN_PKT_DATA_L => 0,
IN_PKT_BYTEEN_H => 35,
IN_PKT_BYTEEN_L => 32,
IN_PKT_BYTE_CNT_H => 61,
IN_PKT_BYTE_CNT_L => 59,
IN_PKT_TRANS_COMPRESSED_READ => 53,
IN_PKT_BURSTWRAP_H => 62,
IN_PKT_BURSTWRAP_L => 62,
IN_PKT_BURST_SIZE_H => 65,
IN_PKT_BURST_SIZE_L => 63,
IN_PKT_RESPONSE_STATUS_H => 87,
IN_PKT_RESPONSE_STATUS_L => 86,
IN_PKT_TRANS_EXCLUSIVE => 58,
IN_PKT_BURST_TYPE_H => 67,
IN_PKT_BURST_TYPE_L => 66,
IN_ST_DATA_W => 88,
OUT_PKT_ADDR_H => 34,
OUT_PKT_ADDR_L => 18,
OUT_PKT_DATA_H => 15,
OUT_PKT_DATA_L => 0,
OUT_PKT_BYTEEN_H => 17,
OUT_PKT_BYTEEN_L => 16,
OUT_PKT_BYTE_CNT_H => 43,
OUT_PKT_BYTE_CNT_L => 41,
OUT_PKT_TRANS_COMPRESSED_READ => 35,
OUT_PKT_BURST_SIZE_H => 47,
OUT_PKT_BURST_SIZE_L => 45,
OUT_PKT_RESPONSE_STATUS_H => 69,
OUT_PKT_RESPONSE_STATUS_L => 68,
OUT_PKT_TRANS_EXCLUSIVE => 40,
OUT_PKT_BURST_TYPE_H => 49,
OUT_PKT_BURST_TYPE_L => 48,
OUT_ST_DATA_W => 70,
ST_CHANNEL_W => 7,
OPTIMIZE_FOR_RSP => 1,
RESPONSE_PATH => 1
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
in_valid => id_router_001_src_valid, -- sink.valid
in_channel => id_router_001_src_channel, -- .channel
in_startofpacket => id_router_001_src_startofpacket, -- .startofpacket
in_endofpacket => id_router_001_src_endofpacket, -- .endofpacket
in_ready => id_router_001_src_ready, -- .ready
in_data => id_router_001_src_data, -- .data
out_endofpacket => width_adapter_003_src_endofpacket, -- src.endofpacket
out_data => width_adapter_003_src_data, -- .data
out_channel => width_adapter_003_src_channel, -- .channel
out_valid => width_adapter_003_src_valid, -- .valid
out_ready => width_adapter_003_src_ready, -- .ready
out_startofpacket => width_adapter_003_src_startofpacket, -- .startofpacket
in_command_size_data => "000" -- (terminated)
);
width_adapter_004 : component cb20_width_adapter
generic map (
IN_PKT_ADDR_H => 34,
IN_PKT_ADDR_L => 18,
IN_PKT_DATA_H => 15,
IN_PKT_DATA_L => 0,
IN_PKT_BYTEEN_H => 17,
IN_PKT_BYTEEN_L => 16,
IN_PKT_BYTE_CNT_H => 43,
IN_PKT_BYTE_CNT_L => 41,
IN_PKT_TRANS_COMPRESSED_READ => 35,
IN_PKT_BURSTWRAP_H => 44,
IN_PKT_BURSTWRAP_L => 44,
IN_PKT_BURST_SIZE_H => 47,
IN_PKT_BURST_SIZE_L => 45,
IN_PKT_RESPONSE_STATUS_H => 69,
IN_PKT_RESPONSE_STATUS_L => 68,
IN_PKT_TRANS_EXCLUSIVE => 40,
IN_PKT_BURST_TYPE_H => 49,
IN_PKT_BURST_TYPE_L => 48,
IN_ST_DATA_W => 70,
OUT_PKT_ADDR_H => 52,
OUT_PKT_ADDR_L => 36,
OUT_PKT_DATA_H => 31,
OUT_PKT_DATA_L => 0,
OUT_PKT_BYTEEN_H => 35,
OUT_PKT_BYTEEN_L => 32,
OUT_PKT_BYTE_CNT_H => 61,
OUT_PKT_BYTE_CNT_L => 59,
OUT_PKT_TRANS_COMPRESSED_READ => 53,
OUT_PKT_BURST_SIZE_H => 65,
OUT_PKT_BURST_SIZE_L => 63,
OUT_PKT_RESPONSE_STATUS_H => 87,
OUT_PKT_RESPONSE_STATUS_L => 86,
OUT_PKT_TRANS_EXCLUSIVE => 58,
OUT_PKT_BURST_TYPE_H => 67,
OUT_PKT_BURST_TYPE_L => 66,
OUT_ST_DATA_W => 88,
ST_CHANNEL_W => 7,
OPTIMIZE_FOR_RSP => 0,
RESPONSE_PATH => 0
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
in_valid => cmd_xbar_demux_src2_valid, -- sink.valid
in_channel => cmd_xbar_demux_src2_channel, -- .channel
in_startofpacket => cmd_xbar_demux_src2_startofpacket, -- .startofpacket
in_endofpacket => cmd_xbar_demux_src2_endofpacket, -- .endofpacket
in_ready => cmd_xbar_demux_src2_ready, -- .ready
in_data => cmd_xbar_demux_src2_data, -- .data
out_endofpacket => width_adapter_004_src_endofpacket, -- src.endofpacket
out_data => width_adapter_004_src_data, -- .data
out_channel => width_adapter_004_src_channel, -- .channel
out_valid => width_adapter_004_src_valid, -- .valid
out_ready => width_adapter_004_src_ready, -- .ready
out_startofpacket => width_adapter_004_src_startofpacket, -- .startofpacket
in_command_size_data => "000" -- (terminated)
);
width_adapter_005 : component cb20_width_adapter_001
generic map (
IN_PKT_ADDR_H => 52,
IN_PKT_ADDR_L => 36,
IN_PKT_DATA_H => 31,
IN_PKT_DATA_L => 0,
IN_PKT_BYTEEN_H => 35,
IN_PKT_BYTEEN_L => 32,
IN_PKT_BYTE_CNT_H => 61,
IN_PKT_BYTE_CNT_L => 59,
IN_PKT_TRANS_COMPRESSED_READ => 53,
IN_PKT_BURSTWRAP_H => 62,
IN_PKT_BURSTWRAP_L => 62,
IN_PKT_BURST_SIZE_H => 65,
IN_PKT_BURST_SIZE_L => 63,
IN_PKT_RESPONSE_STATUS_H => 87,
IN_PKT_RESPONSE_STATUS_L => 86,
IN_PKT_TRANS_EXCLUSIVE => 58,
IN_PKT_BURST_TYPE_H => 67,
IN_PKT_BURST_TYPE_L => 66,
IN_ST_DATA_W => 88,
OUT_PKT_ADDR_H => 34,
OUT_PKT_ADDR_L => 18,
OUT_PKT_DATA_H => 15,
OUT_PKT_DATA_L => 0,
OUT_PKT_BYTEEN_H => 17,
OUT_PKT_BYTEEN_L => 16,
OUT_PKT_BYTE_CNT_H => 43,
OUT_PKT_BYTE_CNT_L => 41,
OUT_PKT_TRANS_COMPRESSED_READ => 35,
OUT_PKT_BURST_SIZE_H => 47,
OUT_PKT_BURST_SIZE_L => 45,
OUT_PKT_RESPONSE_STATUS_H => 69,
OUT_PKT_RESPONSE_STATUS_L => 68,
OUT_PKT_TRANS_EXCLUSIVE => 40,
OUT_PKT_BURST_TYPE_H => 49,
OUT_PKT_BURST_TYPE_L => 48,
OUT_ST_DATA_W => 70,
ST_CHANNEL_W => 7,
OPTIMIZE_FOR_RSP => 1,
RESPONSE_PATH => 1
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
in_valid => id_router_002_src_valid, -- sink.valid
in_channel => id_router_002_src_channel, -- .channel
in_startofpacket => id_router_002_src_startofpacket, -- .startofpacket
in_endofpacket => id_router_002_src_endofpacket, -- .endofpacket
in_ready => id_router_002_src_ready, -- .ready
in_data => id_router_002_src_data, -- .data
out_endofpacket => width_adapter_005_src_endofpacket, -- src.endofpacket
out_data => width_adapter_005_src_data, -- .data
out_channel => width_adapter_005_src_channel, -- .channel
out_valid => width_adapter_005_src_valid, -- .valid
out_ready => width_adapter_005_src_ready, -- .ready
out_startofpacket => width_adapter_005_src_startofpacket, -- .startofpacket
in_command_size_data => "000" -- (terminated)
);
width_adapter_006 : component cb20_width_adapter
generic map (
IN_PKT_ADDR_H => 34,
IN_PKT_ADDR_L => 18,
IN_PKT_DATA_H => 15,
IN_PKT_DATA_L => 0,
IN_PKT_BYTEEN_H => 17,
IN_PKT_BYTEEN_L => 16,
IN_PKT_BYTE_CNT_H => 43,
IN_PKT_BYTE_CNT_L => 41,
IN_PKT_TRANS_COMPRESSED_READ => 35,
IN_PKT_BURSTWRAP_H => 44,
IN_PKT_BURSTWRAP_L => 44,
IN_PKT_BURST_SIZE_H => 47,
IN_PKT_BURST_SIZE_L => 45,
IN_PKT_RESPONSE_STATUS_H => 69,
IN_PKT_RESPONSE_STATUS_L => 68,
IN_PKT_TRANS_EXCLUSIVE => 40,
IN_PKT_BURST_TYPE_H => 49,
IN_PKT_BURST_TYPE_L => 48,
IN_ST_DATA_W => 70,
OUT_PKT_ADDR_H => 52,
OUT_PKT_ADDR_L => 36,
OUT_PKT_DATA_H => 31,
OUT_PKT_DATA_L => 0,
OUT_PKT_BYTEEN_H => 35,
OUT_PKT_BYTEEN_L => 32,
OUT_PKT_BYTE_CNT_H => 61,
OUT_PKT_BYTE_CNT_L => 59,
OUT_PKT_TRANS_COMPRESSED_READ => 53,
OUT_PKT_BURST_SIZE_H => 65,
OUT_PKT_BURST_SIZE_L => 63,
OUT_PKT_RESPONSE_STATUS_H => 87,
OUT_PKT_RESPONSE_STATUS_L => 86,
OUT_PKT_TRANS_EXCLUSIVE => 58,
OUT_PKT_BURST_TYPE_H => 67,
OUT_PKT_BURST_TYPE_L => 66,
OUT_ST_DATA_W => 88,
ST_CHANNEL_W => 7,
OPTIMIZE_FOR_RSP => 0,
RESPONSE_PATH => 0
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
in_valid => cmd_xbar_demux_src3_valid, -- sink.valid
in_channel => cmd_xbar_demux_src3_channel, -- .channel
in_startofpacket => cmd_xbar_demux_src3_startofpacket, -- .startofpacket
in_endofpacket => cmd_xbar_demux_src3_endofpacket, -- .endofpacket
in_ready => cmd_xbar_demux_src3_ready, -- .ready
in_data => cmd_xbar_demux_src3_data, -- .data
out_endofpacket => width_adapter_006_src_endofpacket, -- src.endofpacket
out_data => width_adapter_006_src_data, -- .data
out_channel => width_adapter_006_src_channel, -- .channel
out_valid => width_adapter_006_src_valid, -- .valid
out_ready => width_adapter_006_src_ready, -- .ready
out_startofpacket => width_adapter_006_src_startofpacket, -- .startofpacket
in_command_size_data => "000" -- (terminated)
);
width_adapter_007 : component cb20_width_adapter_001
generic map (
IN_PKT_ADDR_H => 52,
IN_PKT_ADDR_L => 36,
IN_PKT_DATA_H => 31,
IN_PKT_DATA_L => 0,
IN_PKT_BYTEEN_H => 35,
IN_PKT_BYTEEN_L => 32,
IN_PKT_BYTE_CNT_H => 61,
IN_PKT_BYTE_CNT_L => 59,
IN_PKT_TRANS_COMPRESSED_READ => 53,
IN_PKT_BURSTWRAP_H => 62,
IN_PKT_BURSTWRAP_L => 62,
IN_PKT_BURST_SIZE_H => 65,
IN_PKT_BURST_SIZE_L => 63,
IN_PKT_RESPONSE_STATUS_H => 87,
IN_PKT_RESPONSE_STATUS_L => 86,
IN_PKT_TRANS_EXCLUSIVE => 58,
IN_PKT_BURST_TYPE_H => 67,
IN_PKT_BURST_TYPE_L => 66,
IN_ST_DATA_W => 88,
OUT_PKT_ADDR_H => 34,
OUT_PKT_ADDR_L => 18,
OUT_PKT_DATA_H => 15,
OUT_PKT_DATA_L => 0,
OUT_PKT_BYTEEN_H => 17,
OUT_PKT_BYTEEN_L => 16,
OUT_PKT_BYTE_CNT_H => 43,
OUT_PKT_BYTE_CNT_L => 41,
OUT_PKT_TRANS_COMPRESSED_READ => 35,
OUT_PKT_BURST_SIZE_H => 47,
OUT_PKT_BURST_SIZE_L => 45,
OUT_PKT_RESPONSE_STATUS_H => 69,
OUT_PKT_RESPONSE_STATUS_L => 68,
OUT_PKT_TRANS_EXCLUSIVE => 40,
OUT_PKT_BURST_TYPE_H => 49,
OUT_PKT_BURST_TYPE_L => 48,
OUT_ST_DATA_W => 70,
ST_CHANNEL_W => 7,
OPTIMIZE_FOR_RSP => 1,
RESPONSE_PATH => 1
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
in_valid => id_router_003_src_valid, -- sink.valid
in_channel => id_router_003_src_channel, -- .channel
in_startofpacket => id_router_003_src_startofpacket, -- .startofpacket
in_endofpacket => id_router_003_src_endofpacket, -- .endofpacket
in_ready => id_router_003_src_ready, -- .ready
in_data => id_router_003_src_data, -- .data
out_endofpacket => width_adapter_007_src_endofpacket, -- src.endofpacket
out_data => width_adapter_007_src_data, -- .data
out_channel => width_adapter_007_src_channel, -- .channel
out_valid => width_adapter_007_src_valid, -- .valid
out_ready => width_adapter_007_src_ready, -- .ready
out_startofpacket => width_adapter_007_src_startofpacket, -- .startofpacket
in_command_size_data => "000" -- (terminated)
);
width_adapter_008 : component cb20_width_adapter
generic map (
IN_PKT_ADDR_H => 34,
IN_PKT_ADDR_L => 18,
IN_PKT_DATA_H => 15,
IN_PKT_DATA_L => 0,
IN_PKT_BYTEEN_H => 17,
IN_PKT_BYTEEN_L => 16,
IN_PKT_BYTE_CNT_H => 43,
IN_PKT_BYTE_CNT_L => 41,
IN_PKT_TRANS_COMPRESSED_READ => 35,
IN_PKT_BURSTWRAP_H => 44,
IN_PKT_BURSTWRAP_L => 44,
IN_PKT_BURST_SIZE_H => 47,
IN_PKT_BURST_SIZE_L => 45,
IN_PKT_RESPONSE_STATUS_H => 69,
IN_PKT_RESPONSE_STATUS_L => 68,
IN_PKT_TRANS_EXCLUSIVE => 40,
IN_PKT_BURST_TYPE_H => 49,
IN_PKT_BURST_TYPE_L => 48,
IN_ST_DATA_W => 70,
OUT_PKT_ADDR_H => 52,
OUT_PKT_ADDR_L => 36,
OUT_PKT_DATA_H => 31,
OUT_PKT_DATA_L => 0,
OUT_PKT_BYTEEN_H => 35,
OUT_PKT_BYTEEN_L => 32,
OUT_PKT_BYTE_CNT_H => 61,
OUT_PKT_BYTE_CNT_L => 59,
OUT_PKT_TRANS_COMPRESSED_READ => 53,
OUT_PKT_BURST_SIZE_H => 65,
OUT_PKT_BURST_SIZE_L => 63,
OUT_PKT_RESPONSE_STATUS_H => 87,
OUT_PKT_RESPONSE_STATUS_L => 86,
OUT_PKT_TRANS_EXCLUSIVE => 58,
OUT_PKT_BURST_TYPE_H => 67,
OUT_PKT_BURST_TYPE_L => 66,
OUT_ST_DATA_W => 88,
ST_CHANNEL_W => 7,
OPTIMIZE_FOR_RSP => 0,
RESPONSE_PATH => 0
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
in_valid => cmd_xbar_demux_src4_valid, -- sink.valid
in_channel => cmd_xbar_demux_src4_channel, -- .channel
in_startofpacket => cmd_xbar_demux_src4_startofpacket, -- .startofpacket
in_endofpacket => cmd_xbar_demux_src4_endofpacket, -- .endofpacket
in_ready => cmd_xbar_demux_src4_ready, -- .ready
in_data => cmd_xbar_demux_src4_data, -- .data
out_endofpacket => width_adapter_008_src_endofpacket, -- src.endofpacket
out_data => width_adapter_008_src_data, -- .data
out_channel => width_adapter_008_src_channel, -- .channel
out_valid => width_adapter_008_src_valid, -- .valid
out_ready => width_adapter_008_src_ready, -- .ready
out_startofpacket => width_adapter_008_src_startofpacket, -- .startofpacket
in_command_size_data => "000" -- (terminated)
);
width_adapter_009 : component cb20_width_adapter_001
generic map (
IN_PKT_ADDR_H => 52,
IN_PKT_ADDR_L => 36,
IN_PKT_DATA_H => 31,
IN_PKT_DATA_L => 0,
IN_PKT_BYTEEN_H => 35,
IN_PKT_BYTEEN_L => 32,
IN_PKT_BYTE_CNT_H => 61,
IN_PKT_BYTE_CNT_L => 59,
IN_PKT_TRANS_COMPRESSED_READ => 53,
IN_PKT_BURSTWRAP_H => 62,
IN_PKT_BURSTWRAP_L => 62,
IN_PKT_BURST_SIZE_H => 65,
IN_PKT_BURST_SIZE_L => 63,
IN_PKT_RESPONSE_STATUS_H => 87,
IN_PKT_RESPONSE_STATUS_L => 86,
IN_PKT_TRANS_EXCLUSIVE => 58,
IN_PKT_BURST_TYPE_H => 67,
IN_PKT_BURST_TYPE_L => 66,
IN_ST_DATA_W => 88,
OUT_PKT_ADDR_H => 34,
OUT_PKT_ADDR_L => 18,
OUT_PKT_DATA_H => 15,
OUT_PKT_DATA_L => 0,
OUT_PKT_BYTEEN_H => 17,
OUT_PKT_BYTEEN_L => 16,
OUT_PKT_BYTE_CNT_H => 43,
OUT_PKT_BYTE_CNT_L => 41,
OUT_PKT_TRANS_COMPRESSED_READ => 35,
OUT_PKT_BURST_SIZE_H => 47,
OUT_PKT_BURST_SIZE_L => 45,
OUT_PKT_RESPONSE_STATUS_H => 69,
OUT_PKT_RESPONSE_STATUS_L => 68,
OUT_PKT_TRANS_EXCLUSIVE => 40,
OUT_PKT_BURST_TYPE_H => 49,
OUT_PKT_BURST_TYPE_L => 48,
OUT_ST_DATA_W => 70,
ST_CHANNEL_W => 7,
OPTIMIZE_FOR_RSP => 1,
RESPONSE_PATH => 1
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
in_valid => id_router_004_src_valid, -- sink.valid
in_channel => id_router_004_src_channel, -- .channel
in_startofpacket => id_router_004_src_startofpacket, -- .startofpacket
in_endofpacket => id_router_004_src_endofpacket, -- .endofpacket
in_ready => id_router_004_src_ready, -- .ready
in_data => id_router_004_src_data, -- .data
out_endofpacket => width_adapter_009_src_endofpacket, -- src.endofpacket
out_data => width_adapter_009_src_data, -- .data
out_channel => width_adapter_009_src_channel, -- .channel
out_valid => width_adapter_009_src_valid, -- .valid
out_ready => width_adapter_009_src_ready, -- .ready
out_startofpacket => width_adapter_009_src_startofpacket, -- .startofpacket
in_command_size_data => "000" -- (terminated)
);
width_adapter_010 : component cb20_width_adapter
generic map (
IN_PKT_ADDR_H => 34,
IN_PKT_ADDR_L => 18,
IN_PKT_DATA_H => 15,
IN_PKT_DATA_L => 0,
IN_PKT_BYTEEN_H => 17,
IN_PKT_BYTEEN_L => 16,
IN_PKT_BYTE_CNT_H => 43,
IN_PKT_BYTE_CNT_L => 41,
IN_PKT_TRANS_COMPRESSED_READ => 35,
IN_PKT_BURSTWRAP_H => 44,
IN_PKT_BURSTWRAP_L => 44,
IN_PKT_BURST_SIZE_H => 47,
IN_PKT_BURST_SIZE_L => 45,
IN_PKT_RESPONSE_STATUS_H => 69,
IN_PKT_RESPONSE_STATUS_L => 68,
IN_PKT_TRANS_EXCLUSIVE => 40,
IN_PKT_BURST_TYPE_H => 49,
IN_PKT_BURST_TYPE_L => 48,
IN_ST_DATA_W => 70,
OUT_PKT_ADDR_H => 52,
OUT_PKT_ADDR_L => 36,
OUT_PKT_DATA_H => 31,
OUT_PKT_DATA_L => 0,
OUT_PKT_BYTEEN_H => 35,
OUT_PKT_BYTEEN_L => 32,
OUT_PKT_BYTE_CNT_H => 61,
OUT_PKT_BYTE_CNT_L => 59,
OUT_PKT_TRANS_COMPRESSED_READ => 53,
OUT_PKT_BURST_SIZE_H => 65,
OUT_PKT_BURST_SIZE_L => 63,
OUT_PKT_RESPONSE_STATUS_H => 87,
OUT_PKT_RESPONSE_STATUS_L => 86,
OUT_PKT_TRANS_EXCLUSIVE => 58,
OUT_PKT_BURST_TYPE_H => 67,
OUT_PKT_BURST_TYPE_L => 66,
OUT_ST_DATA_W => 88,
ST_CHANNEL_W => 7,
OPTIMIZE_FOR_RSP => 0,
RESPONSE_PATH => 0
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
in_valid => cmd_xbar_demux_src5_valid, -- sink.valid
in_channel => cmd_xbar_demux_src5_channel, -- .channel
in_startofpacket => cmd_xbar_demux_src5_startofpacket, -- .startofpacket
in_endofpacket => cmd_xbar_demux_src5_endofpacket, -- .endofpacket
in_ready => cmd_xbar_demux_src5_ready, -- .ready
in_data => cmd_xbar_demux_src5_data, -- .data
out_endofpacket => width_adapter_010_src_endofpacket, -- src.endofpacket
out_data => width_adapter_010_src_data, -- .data
out_channel => width_adapter_010_src_channel, -- .channel
out_valid => width_adapter_010_src_valid, -- .valid
out_ready => width_adapter_010_src_ready, -- .ready
out_startofpacket => width_adapter_010_src_startofpacket, -- .startofpacket
in_command_size_data => "000" -- (terminated)
);
width_adapter_011 : component cb20_width_adapter_001
generic map (
IN_PKT_ADDR_H => 52,
IN_PKT_ADDR_L => 36,
IN_PKT_DATA_H => 31,
IN_PKT_DATA_L => 0,
IN_PKT_BYTEEN_H => 35,
IN_PKT_BYTEEN_L => 32,
IN_PKT_BYTE_CNT_H => 61,
IN_PKT_BYTE_CNT_L => 59,
IN_PKT_TRANS_COMPRESSED_READ => 53,
IN_PKT_BURSTWRAP_H => 62,
IN_PKT_BURSTWRAP_L => 62,
IN_PKT_BURST_SIZE_H => 65,
IN_PKT_BURST_SIZE_L => 63,
IN_PKT_RESPONSE_STATUS_H => 87,
IN_PKT_RESPONSE_STATUS_L => 86,
IN_PKT_TRANS_EXCLUSIVE => 58,
IN_PKT_BURST_TYPE_H => 67,
IN_PKT_BURST_TYPE_L => 66,
IN_ST_DATA_W => 88,
OUT_PKT_ADDR_H => 34,
OUT_PKT_ADDR_L => 18,
OUT_PKT_DATA_H => 15,
OUT_PKT_DATA_L => 0,
OUT_PKT_BYTEEN_H => 17,
OUT_PKT_BYTEEN_L => 16,
OUT_PKT_BYTE_CNT_H => 43,
OUT_PKT_BYTE_CNT_L => 41,
OUT_PKT_TRANS_COMPRESSED_READ => 35,
OUT_PKT_BURST_SIZE_H => 47,
OUT_PKT_BURST_SIZE_L => 45,
OUT_PKT_RESPONSE_STATUS_H => 69,
OUT_PKT_RESPONSE_STATUS_L => 68,
OUT_PKT_TRANS_EXCLUSIVE => 40,
OUT_PKT_BURST_TYPE_H => 49,
OUT_PKT_BURST_TYPE_L => 48,
OUT_ST_DATA_W => 70,
ST_CHANNEL_W => 7,
OPTIMIZE_FOR_RSP => 1,
RESPONSE_PATH => 1
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
in_valid => id_router_005_src_valid, -- sink.valid
in_channel => id_router_005_src_channel, -- .channel
in_startofpacket => id_router_005_src_startofpacket, -- .startofpacket
in_endofpacket => id_router_005_src_endofpacket, -- .endofpacket
in_ready => id_router_005_src_ready, -- .ready
in_data => id_router_005_src_data, -- .data
out_endofpacket => width_adapter_011_src_endofpacket, -- src.endofpacket
out_data => width_adapter_011_src_data, -- .data
out_channel => width_adapter_011_src_channel, -- .channel
out_valid => width_adapter_011_src_valid, -- .valid
out_ready => width_adapter_011_src_ready, -- .ready
out_startofpacket => width_adapter_011_src_startofpacket, -- .startofpacket
in_command_size_data => "000" -- (terminated)
);
width_adapter_012 : component cb20_width_adapter
generic map (
IN_PKT_ADDR_H => 34,
IN_PKT_ADDR_L => 18,
IN_PKT_DATA_H => 15,
IN_PKT_DATA_L => 0,
IN_PKT_BYTEEN_H => 17,
IN_PKT_BYTEEN_L => 16,
IN_PKT_BYTE_CNT_H => 43,
IN_PKT_BYTE_CNT_L => 41,
IN_PKT_TRANS_COMPRESSED_READ => 35,
IN_PKT_BURSTWRAP_H => 44,
IN_PKT_BURSTWRAP_L => 44,
IN_PKT_BURST_SIZE_H => 47,
IN_PKT_BURST_SIZE_L => 45,
IN_PKT_RESPONSE_STATUS_H => 69,
IN_PKT_RESPONSE_STATUS_L => 68,
IN_PKT_TRANS_EXCLUSIVE => 40,
IN_PKT_BURST_TYPE_H => 49,
IN_PKT_BURST_TYPE_L => 48,
IN_ST_DATA_W => 70,
OUT_PKT_ADDR_H => 52,
OUT_PKT_ADDR_L => 36,
OUT_PKT_DATA_H => 31,
OUT_PKT_DATA_L => 0,
OUT_PKT_BYTEEN_H => 35,
OUT_PKT_BYTEEN_L => 32,
OUT_PKT_BYTE_CNT_H => 61,
OUT_PKT_BYTE_CNT_L => 59,
OUT_PKT_TRANS_COMPRESSED_READ => 53,
OUT_PKT_BURST_SIZE_H => 65,
OUT_PKT_BURST_SIZE_L => 63,
OUT_PKT_RESPONSE_STATUS_H => 87,
OUT_PKT_RESPONSE_STATUS_L => 86,
OUT_PKT_TRANS_EXCLUSIVE => 58,
OUT_PKT_BURST_TYPE_H => 67,
OUT_PKT_BURST_TYPE_L => 66,
OUT_ST_DATA_W => 88,
ST_CHANNEL_W => 7,
OPTIMIZE_FOR_RSP => 0,
RESPONSE_PATH => 0
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
in_valid => cmd_xbar_demux_src6_valid, -- sink.valid
in_channel => cmd_xbar_demux_src6_channel, -- .channel
in_startofpacket => cmd_xbar_demux_src6_startofpacket, -- .startofpacket
in_endofpacket => cmd_xbar_demux_src6_endofpacket, -- .endofpacket
in_ready => cmd_xbar_demux_src6_ready, -- .ready
in_data => cmd_xbar_demux_src6_data, -- .data
out_endofpacket => width_adapter_012_src_endofpacket, -- src.endofpacket
out_data => width_adapter_012_src_data, -- .data
out_channel => width_adapter_012_src_channel, -- .channel
out_valid => width_adapter_012_src_valid, -- .valid
out_ready => width_adapter_012_src_ready, -- .ready
out_startofpacket => width_adapter_012_src_startofpacket, -- .startofpacket
in_command_size_data => "000" -- (terminated)
);
width_adapter_013 : component cb20_width_adapter_001
generic map (
IN_PKT_ADDR_H => 52,
IN_PKT_ADDR_L => 36,
IN_PKT_DATA_H => 31,
IN_PKT_DATA_L => 0,
IN_PKT_BYTEEN_H => 35,
IN_PKT_BYTEEN_L => 32,
IN_PKT_BYTE_CNT_H => 61,
IN_PKT_BYTE_CNT_L => 59,
IN_PKT_TRANS_COMPRESSED_READ => 53,
IN_PKT_BURSTWRAP_H => 62,
IN_PKT_BURSTWRAP_L => 62,
IN_PKT_BURST_SIZE_H => 65,
IN_PKT_BURST_SIZE_L => 63,
IN_PKT_RESPONSE_STATUS_H => 87,
IN_PKT_RESPONSE_STATUS_L => 86,
IN_PKT_TRANS_EXCLUSIVE => 58,
IN_PKT_BURST_TYPE_H => 67,
IN_PKT_BURST_TYPE_L => 66,
IN_ST_DATA_W => 88,
OUT_PKT_ADDR_H => 34,
OUT_PKT_ADDR_L => 18,
OUT_PKT_DATA_H => 15,
OUT_PKT_DATA_L => 0,
OUT_PKT_BYTEEN_H => 17,
OUT_PKT_BYTEEN_L => 16,
OUT_PKT_BYTE_CNT_H => 43,
OUT_PKT_BYTE_CNT_L => 41,
OUT_PKT_TRANS_COMPRESSED_READ => 35,
OUT_PKT_BURST_SIZE_H => 47,
OUT_PKT_BURST_SIZE_L => 45,
OUT_PKT_RESPONSE_STATUS_H => 69,
OUT_PKT_RESPONSE_STATUS_L => 68,
OUT_PKT_TRANS_EXCLUSIVE => 40,
OUT_PKT_BURST_TYPE_H => 49,
OUT_PKT_BURST_TYPE_L => 48,
OUT_ST_DATA_W => 70,
ST_CHANNEL_W => 7,
OPTIMIZE_FOR_RSP => 1,
RESPONSE_PATH => 1
)
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
in_valid => id_router_006_src_valid, -- sink.valid
in_channel => id_router_006_src_channel, -- .channel
in_startofpacket => id_router_006_src_startofpacket, -- .startofpacket
in_endofpacket => id_router_006_src_endofpacket, -- .endofpacket
in_ready => id_router_006_src_ready, -- .ready
in_data => id_router_006_src_data, -- .data
out_endofpacket => width_adapter_013_src_endofpacket, -- src.endofpacket
out_data => width_adapter_013_src_data, -- .data
out_channel => width_adapter_013_src_channel, -- .channel
out_valid => width_adapter_013_src_valid, -- .valid
out_ready => width_adapter_013_src_ready, -- .ready
out_startofpacket => width_adapter_013_src_startofpacket, -- .startofpacket
in_command_size_data => "000" -- (terminated)
);
reset_reset_n_ports_inv <= not reset_reset_n;
rst_controller_001_reset_out_reset_ports_inv <= not rst_controller_001_reset_out_reset;
end architecture rtl; -- of cb20
| apache-2.0 | 1eb704d61e8ccd91eba92ee3c93131f1 | 0.494818 | 3.96179 | false | false | false | false |
markusC64/1541ultimate2 | fpga/altera/mem_io.vhd | 1 | 16,820 | --------------------------------------------------------------------------------
-- Entity: mem_io
-- Date:2016-07-16
-- Author: Gideon
--
-- Description: All Altera specific I/O stuff for DDR(2)
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
entity mem_io is
generic (
g_data_width : natural := 4;
g_addr_cmd_width : natural := 8 );
port (
ref_clock : in std_logic;
ref_reset : in std_logic;
sys_clock : out std_logic;
sys_reset : out std_logic;
user_clock_1 : out std_logic := '0';
user_clock_2 : out std_logic := '0';
user_clock_3 : out std_logic := '0';
phasecounterselect : in std_logic_vector(2 downto 0);
phasestep : in std_logic;
phaseupdown : in std_logic;
phasedone : out std_logic;
mode : in std_logic_vector(1 downto 0) := "00";
addr_first : in std_logic_vector(g_addr_cmd_width-1 downto 0);
addr_second : in std_logic_vector(g_addr_cmd_width-1 downto 0);
wdata : in std_logic_vector(4*g_data_width-1 downto 0);
wdata_oe : in std_logic := '0';
rdata : out std_logic_vector(4*g_data_width-1 downto 0);
mem_clk_p : inout std_logic := 'Z';
mem_clk_n : inout std_logic := 'Z';
mem_addr : out std_logic_vector(g_addr_cmd_width-1 downto 0);
mem_dqs : inout std_logic := 'Z';
mem_dq : inout std_logic_vector(g_data_width-1 downto 0)
);
end entity;
architecture arch of mem_io is
signal sys_clock_pll : std_logic;
signal sys_clock_i : std_logic;
signal sys_reset_pipe : std_logic_vector(3 downto 0);
signal pll_locked : std_logic;
signal mem_sys_clock : std_logic;
signal mem_addr_clock : std_logic;
signal mem_write_clock : std_logic;
signal mem_read_clock : std_logic;
signal not_sys_clock : std_logic;
signal not_addr_clock : std_logic;
signal wdata_r : std_logic_vector(4*g_data_width-1 downto 0);
signal wdata_oe_r : std_logic;
signal wdata_oe_r2 : std_logic;
signal mode_r : std_logic_vector(1 downto 0);
signal wdata_half : std_logic_vector(2*g_data_width-1 downto 0);
signal wdata_mux : std_logic;
signal mux_reset : std_logic;
signal rdata_h : std_logic_vector(g_data_width-1 downto 0);
signal rdata_l : std_logic_vector(g_data_width-1 downto 0);
signal rdata_l1 : std_logic_vector(g_data_width-1 downto 0);
signal rdata_l2 : std_logic_vector(g_data_width-1 downto 0);
signal rdata_h1 : std_logic_vector(g_data_width-1 downto 0);
signal rdata_h2 : std_logic_vector(g_data_width-1 downto 0);
signal rdata_32 : std_logic_vector(4*g_data_width-1 downto 0);
signal dqs_oe : std_logic;
signal dqs_in_h : std_logic;
signal dqs_in_l : std_logic;
signal dqs_in_h1 : std_logic;
signal dqs_in_l1 : std_logic;
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
clk2_divide_by : NATURAL;
clk2_duty_cycle : NATURAL;
clk2_multiply_by : NATURAL;
clk2_phase_shift : STRING;
clk3_divide_by : NATURAL;
clk3_duty_cycle : NATURAL;
clk3_multiply_by : NATURAL;
clk3_phase_shift : STRING;
clk4_divide_by : NATURAL;
clk4_duty_cycle : NATURAL;
clk4_multiply_by : NATURAL;
clk4_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
self_reset_on_loss_lock : STRING;
vco_frequency_control : STRING;
vco_phase_shift_step : NATURAL;
width_clock : NATURAL;
width_phasecounterselect : NATURAL
);
PORT (
areset : IN STD_LOGIC ;
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
phasecounterselect : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
phasestep : IN STD_LOGIC ;
phaseupdown : IN STD_LOGIC ;
scanclk : IN STD_LOGIC ;
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
locked : OUT STD_LOGIC ;
phasedone : OUT STD_LOGIC
);
END COMPONENT;
begin
i_pll : altpll
generic map (
bandwidth_type => "AUTO",
clk0_divide_by => 4,
clk0_duty_cycle => 50,
clk0_multiply_by => 5,
clk0_phase_shift => "0",
clk1_divide_by => 2,
clk1_duty_cycle => 50,
clk1_multiply_by => 5,
clk1_phase_shift => "0",
clk2_divide_by => 2,
clk2_duty_cycle => 50,
clk2_multiply_by => 5,
clk2_phase_shift => "2000",
clk3_divide_by => 2,
clk3_duty_cycle => 50,
clk3_multiply_by => 5,
clk3_phase_shift => "3400",
clk4_divide_by => 4,
clk4_duty_cycle => 50,
clk4_multiply_by => 5,
clk4_phase_shift => "0",
compensate_clock => "CLK1",
inclk0_input_frequency => 20000,
intended_device_family => "Cyclone IV E",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_USED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_USED",
port_phasedone => "PORT_USED",
port_phasestep => "PORT_USED",
port_phaseupdown => "PORT_USED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_USED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_USED",
port_clk3 => "PORT_USED",
port_clk4 => "PORT_USED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
self_reset_on_loss_lock => "OFF",
vco_frequency_control => "MANUAL_PHASE",
vco_phase_shift_step => 80,
width_clock => 5,
width_phasecounterselect => 3
)
port map (
areset => ref_reset,
inclk(1) => '0',
inclk(0) => ref_clock,
phasecounterselect => phasecounterselect,
phasestep => phasestep,
phaseupdown => phaseupdown,
scanclk => sys_clock_i,
clk(0) => sys_clock_pll,
clk(1) => mem_addr_clock,
clk(2) => mem_write_clock,
clk(3) => mem_read_clock,
clk(4) => mem_sys_clock,
locked => pll_locked,
phasedone => phasedone
);
sys_clock <= sys_clock_pll;
sys_clock_i <= sys_clock_pll;
process(sys_clock_i, pll_locked)
begin
if pll_locked = '0' then
sys_reset_pipe <= (others => '1');
elsif rising_edge(sys_clock_i) then
sys_reset_pipe <= '0' & sys_reset_pipe(sys_reset_pipe'high downto 1);
end if;
end process;
sys_reset <= sys_reset_pipe(0);
i_clk_p: altddio_bidir
generic map (
extend_oe_disable => "UNUSED",
implement_input_in_lcell => "UNUSED",
intended_device_family => "Cyclone IV E",
invert_output => "OFF",
lpm_type => "altddio_bidir",
oe_reg => "UNUSED",
power_up_high => "OFF",
width => 1
) port map (
padio(0) => mem_clk_p,
outclock => mem_addr_clock,
inclock => mem_read_clock, -- was measure clock
oe => '1',
datain_h => "0",
datain_l => "1",
dataout_h => open,
dataout_l => open,
combout => open,
dqsundelayedout => open,
outclocken => '1',
sclr => '0',
sset => '0'
);
i_clk_n: altddio_bidir
generic map (
extend_oe_disable => "UNUSED",
implement_input_in_lcell => "UNUSED",
intended_device_family => "Cyclone IV E",
invert_output => "OFF",
lpm_type => "altddio_bidir",
oe_reg => "UNUSED",
power_up_high => "OFF",
width => 1
) port map (
padio(0) => mem_clk_n,
outclock => mem_addr_clock,
inclock => mem_read_clock, -- was measure clock
oe => '1',
datain_h => "1",
datain_l => "0",
dataout_h => open,
dataout_l => open,
combout => open,
dqsundelayedout => open,
outclocken => '1',
sclr => '0',
sset => '0'
);
not_sys_clock <= not sys_clock_i;
i_addr: altddio_out
generic map (
extend_oe_disable => "UNUSED",
intended_device_family => "Cyclone IV E",
lpm_hint => "UNUSED",
lpm_type => "altddio_out",
oe_reg => "UNUSED",
power_up_high => "ON",
width => mem_addr'length
) port map (
aset => sys_reset_pipe(0),
datain_h => addr_first,
datain_l => addr_second,
dataout => mem_addr,
oe => '1',
outclock => not_sys_clock,
outclocken => '1'
);
process(mem_write_clock)
begin
if rising_edge(mem_write_clock) then
wdata_mux <= not wdata_mux and not mux_reset;
end if;
if falling_edge(mem_write_clock) then
mux_reset <= sys_reset_pipe(0);
wdata_r <= wdata;
wdata_oe_r <= wdata_oe;
end if;
if rising_edge(mem_write_clock) then
wdata_oe_r2 <= wdata_oe_r;
end if;
end process;
wdata_half <= wdata_r(2*g_data_width-1 downto 0) when wdata_mux='0' else
wdata_r(4*g_data_width-1 downto 2*g_data_width);
i_data: altddio_bidir
generic map (
extend_oe_disable => "OFF",
implement_input_in_lcell => "UNUSED",
intended_device_family => "Cyclone IV E",
invert_output => "OFF",
lpm_type => "altddio_bidir",
oe_reg => "REGISTERED",
power_up_high => "OFF",
width => g_data_width
) port map (
padio => mem_dq,
outclock => mem_write_clock,
inclock => mem_read_clock,
oe => wdata_oe_r,
datain_h => wdata_half(g_data_width-1 downto 0),
datain_l => wdata_half(2*g_data_width-1 downto g_data_width),
dataout_h => rdata_h,
dataout_l => rdata_l,
outclocken => '1',
sclr => '0',
sset => '0'
);
dqs_oe <= wdata_oe or wdata_oe_r;
i_dqs: altddio_bidir
generic map (
extend_oe_disable => "OFF",
intended_device_family => "Cyclone IV E",
lpm_hint => "UNUSED",
lpm_type => "altddio_bidir",
invert_output => "OFF",
oe_reg => "REGISTERED",
power_up_high => "OFF",
width => 1
) port map (
-- aset => sys_reset_pipe(0),
datain_h(0) => wdata_oe_r,
datain_l(0) => '0',
padio(0) => mem_dqs,
oe => dqs_oe,
outclock => not_addr_clock,
outclocken => '1',
inclock => mem_read_clock,
dataout_h(0) => dqs_in_h,
dataout_l(0) => dqs_in_l,
sclr => '0',
sset => '0'
);
not_addr_clock <= not mem_addr_clock;
process(mem_read_clock)
begin
if rising_edge(mem_read_clock) then
rdata_h1 <= rdata_h;
rdata_l1 <= rdata_l;
rdata_h2 <= rdata_h1;
rdata_l2 <= rdata_l1;
dqs_in_h1 <= dqs_in_h;
dqs_in_l1 <= dqs_in_l;
end if;
end process;
process(mem_read_clock)
begin
if falling_edge(mem_read_clock) then
if dqs_in_h1 = '0' and dqs_in_l1 = '1' then
rdata_32 <= rdata_h & rdata_l & rdata_h1 & rdata_l1;
else
rdata_32 <= rdata_l & rdata_h1 & rdata_l1 & rdata_h2;
end if;
end if;
end process;
--
-- process(dqs_in_h1, dqs_in_l1, rdata_h, rdata_l, rdata_h1, rdata_l1, rdata_h2)
-- begin
-- if dqs_in_h1 = '0' and dqs_in_l1 = '1' then
-- rdata_32 <= rdata_h & rdata_l & rdata_h1 & rdata_l1;
-- else
-- rdata_32 <= rdata_l & rdata_h1 & rdata_l1 & rdata_h2;
-- end if;
-- end process;
-- process(mem_sys_clock)
-- begin
-- if rising_edge(mem_sys_clock) then
-- mode_r <= mode;
-- case mode_r is
-- when "00" =>
-- rdata <= rdata_r1 & rdata_r2;
-- when "01" =>
-- rdata <= rdata_f1 & rdata_f2;
-- when "10" =>
-- rdata <= rdata_r2 & rdata_r3;
-- when "11" =>
-- rdata <= rdata_f2 & rdata_f3;
-- when others =>
-- rdata <= (others => '0');
-- end case;
-- end if;
-- end process;
process(sys_clock_i)
begin
if rising_edge(sys_clock_i) then
rdata <= rdata_32;
end if;
end process;
end architecture;
| gpl-3.0 | 4842445ecc4ac6794d1fd4cd4ee5bbac | 0.479964 | 3.633614 | false | false | false | false |
chiggs/nvc | test/regress/record8.vhd | 5 | 761 | entity record8 is
end entity;
architecture test of record8 is
type small_int is range 0 to 5;
type sub_rec is record
var : small_int;
end record;
type rec is record
vec : bit_vector(1 to 3);
num : integer;
sub : sub_rec;
end record;
signal r : rec;
begin
process is
begin
assert r = ("000", integer'left, ( var => 0 ) );
r.vec <= "101";
wait for 1 ns;
assert r = ("101", integer'left, ( var => 0 ) );
assert r.vec = "101";
assert r.vec(3) = '1';
r.num <= 5;
wait for 1 ns;
assert r.num = 5;
r.sub.var <= 2;
wait for 1 ns;
assert r.sub.var = 2;
wait;
end process;
end architecture;
| gpl-3.0 | d075465456a95a6884c2941a3a8439ca | 0.498029 | 3.474886 | false | false | false | false |
trondd/mkjpeg | tb/vhdl/MDCTTB_PKG.vhd | 2 | 19,772 | --------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006 --
-- --
--------------------------------------------------------------------------------
--
-- Title : MDCTTB_PKG
-- Design : MDCT Core
-- Author : Michal Krepa
--
--------------------------------------------------------------------------------
--
-- File : MDCTTB_PKG.VHD
-- Created : Sat Mar 5 2006
--
--------------------------------------------------------------------------------
--
-- Description : Package for testbench simulation
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
-- use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
library STD;
use STD.TEXTIO.all;
library WORK;
use WORK.MDCT_PKG.all;
package MDCTTB_PKG is
----------------------------------------------
-- constant section 1
----------------------------------------------
constant MAX_IMAGE_SIZE_X : INTEGER := 2048;
constant MAX_IMAGE_SIZE_Y : INTEGER := 2048;
----------------------------------------------
-- type section
----------------------------------------------
type MATRIX_TYPE is array (0 to N-1,0 TO N-1) of REAL;
type I_MATRIX_TYPE is array (0 to N-1,0 TO N-1) of INTEGER;
type COEM_TYPE is array (0 to N/2-1, 0 to N/2-1)
of SIGNED(ROMDATA_W-1 downto 0);
type VECTOR4 is array (0 to N/2-1) of REAL;
type N_LINES_TYPE is array (0 to N-1)
of STD_LOGIC_VECTOR(0 to MAX_IMAGE_SIZE_X*IP_W-1);
type IMAGE_TYPE is array (0 to MAX_IMAGE_SIZE_Y-1,
0 to MAX_IMAGE_SIZE_X-1) of INTEGER;
----------------------------------------------
-- function section
----------------------------------------------
procedure CMP_MATRIX(ref_matrix : in I_MATRIX_TYPE;
dcto_matrix : in I_MATRIX_TYPE;
max_error : in INTEGER;
error_matrix : out I_MATRIX_TYPE;
error_cnt : inout INTEGER);
function STR(int: INTEGER; base: INTEGER) return STRING;
function COMPUTE_REF_DCT1D(input_matrix : I_MATRIX_TYPE; shift : BOOLEAN
) return I_MATRIX_TYPE;
function COMPUTE_REF_IDCT(X : I_MATRIX_TYPE) return I_MATRIX_TYPE;
function COMPUTE_PSNR(ref_input : I_MATRIX_TYPE;
reconstr_input : I_MATRIX_TYPE) return REAL;
function COMPUTE_PSNR(ref_input : IMAGE_TYPE;
reconstr_input : IMAGE_TYPE;
ysize : INTEGER;
xsize : INTEGER
) return REAL;
----------------------------------------------
-- constant section 2
----------------------------------------------
-- set below to true to enable quantization in testbench
constant CLK_FREQ_C : INTEGER := 50;
constant HOLD_TIME : TIME := 1 ns;
constant ENABLE_QUANTIZATION_C : BOOLEAN := FALSE;
constant HEX_BASE : INTEGER := 16;
constant DEC_BASE : INTEGER := 10;
constant RUN_FULL_IMAGE : BOOLEAN := FALSE;
constant FILEIN_NAME_C : STRING := "SOURCE\TESTBENCH\lena512.txt";
constant FILEERROR_NAME_C : STRING := "SOURCE\TESTBENCH\imagee.txt";
constant FILEIMAGEO_NAME_C : STRING := "SOURCE\TESTBENCH\imageo.txt";
constant MAX_ERROR_1D : INTEGER := 1;
constant MAX_ERROR_2D : INTEGER := 4;
constant MAX_PIX_VAL : INTEGER := 2**IP_W-1;
constant null_data_r : MATRIX_TYPE :=
(
(000.0,000.0,000.0,000.0,000.0,000.0,000.0,000.0),
(000.0,000.0,000.0,000.0,000.0,000.0,000.0,000.0),
(000.0,000.0,000.0,000.0,000.0,000.0,000.0,000.0),
(000.0,000.0,000.0,000.0,000.0,000.0,000.0,000.0),
(000.0,000.0,000.0,000.0,000.0,000.0,000.0,000.0),
(000.0,000.0,000.0,000.0,000.0,000.0,000.0,000.0),
(000.0,000.0,000.0,000.0,000.0,000.0,000.0,000.0),
(000.0,000.0,000.0,000.0,000.0,000.0,000.0,000.0)
);
constant input_data0 : I_MATRIX_TYPE :=
(
(139,144,149,153,155,155,155,155),
(144,151,153,156,159,156,156,156),
(150,155,160,163,158,156,156,156),
(159,161,162,160,160,159,159,159),
(159,160,161,162,162,155,155,155),
(161,161,161,161,160,157,157,157),
(162,162,161,163,162,157,157,157),
(162,162,161,161,163,158,158,158)
);
constant input_data1 : I_MATRIX_TYPE :=
(
(255,255,255,000,000,255,254,255),
(255,255,255,000,000,255,254,000),
(255,255,255,000,000,255,254,255),
(255,255,255,000,000,255,254,000),
(254,000,255,255,000,255,254,255),
(254,000,255,255,000,255,254,000),
(254,000,255,255,000,255,254,255),
(254,000,255,255,000,255,254,000)
);
constant input_data2 : I_MATRIX_TYPE :=
(
(000,000,000,000,000,000,000,000),
(000,000,000,000,000,000,000,000),
(000,000,000,000,000,000,000,000),
(000,000,000,000,000,000,000,000),
(000,000,000,000,000,000,000,000),
(000,000,000,000,000,000,000,000),
(000,000,000,000,000,000,000,000),
(000,000,000,000,000,000,000,000)
);
constant input_data3 : I_MATRIX_TYPE :=
(
(55,89,0,2,35,34,100,255),
(144,151,153,151,159,156,156,156),
(150,155,165,163,158,126,156,156),
(254,000,255,255,000,245,254,255),
(159,199,161,162,162,133,155,165),
(231,000,255,235,000,255,254,253),
(162,162,161,163,162,157,157,157),
(11,12,167,165,166,167,101,108)
);
constant input_data4 : I_MATRIX_TYPE :=
(
(135,14,145,15,155,15,155,15),
(140,15,151,15,152,15,153,15),
(154,15,165,16,156,15,157,15),
(158,16,168,16,169,15,150,15),
(15,161,16,162,16,153,15,154),
(165,16,166,16,167,15,158,15),
(16,169,16,160,16,152,15,153),
(164,16,165,16,165,15,156,15)
);
-- from JPEG standard (but not in standard itself!)
constant Q_JPEG_STD : I_MATRIX_TYPE :=
(
(16,11,10,16,24,40,51,61),
(12,12,14,19,26,58,60,55),
(14,13,16,24,40,57,69,56),
(14,17,22,29,51,87,80,62),
(18,22,37,56,68,109,103,77),
(24,35,55,64,81,104,113,92),
(49,64,78,87,103,121,120,101),
(72,92,95,98,112,100,103,99)
);
-- CANON EOS10D super fine quality
constant Q_CANON10D : I_MATRIX_TYPE :=
(
(1, 1, 1, 1, 1, 1, 2, 2),
(1, 1, 1, 1, 1, 2, 4, 4),
(1, 1, 1, 1, 1, 3, 3, 5),
(1, 1, 1, 2, 3, 3, 5, 5),
(1, 1, 3, 3, 4, 4, 5, 5),
(1, 3, 3, 3, 4, 5, 6, 6),
(2, 3, 3, 5, 3, 6, 5, 5),
(3, 3, 4, 3, 6, 4, 5, 5)
);
-- quantization matrix used in testbench
constant Q_MATRIX_USED : I_MATRIX_TYPE := Q_CANON10D;
constant Ce : COEM_TYPE :=
(
(CONV_SIGNED(AP,ROMDATA_W),CONV_SIGNED(AP,ROMDATA_W),CONV_SIGNED(AP,ROMDATA_W),CONV_SIGNED(AP,ROMDATA_W)),
(CONV_SIGNED(BP,ROMDATA_W),CONV_SIGNED(CP,ROMDATA_W),CONV_SIGNED(CM,ROMDATA_W),CONV_SIGNED(BM,ROMDATA_W)),
(CONV_SIGNED(AP,ROMDATA_W),CONV_SIGNED(AM,ROMDATA_W),CONV_SIGNED(AM,ROMDATA_W),CONV_SIGNED(AP,ROMDATA_W)),
(CONV_SIGNED(CP,ROMDATA_W),CONV_SIGNED(BM,ROMDATA_W),CONV_SIGNED(BP,ROMDATA_W),CONV_SIGNED(CM,ROMDATA_W))
);
constant Co : COEM_TYPE :=
(
(CONV_SIGNED(DP,ROMDATA_W),CONV_SIGNED(EP,ROMDATA_W),CONV_SIGNED(FP,ROMDATA_W),CONV_SIGNED(GP,ROMDATA_W)),
(CONV_SIGNED(EP,ROMDATA_W),CONV_SIGNED(GM,ROMDATA_W),CONV_SIGNED(DM,ROMDATA_W),CONV_SIGNED(FM,ROMDATA_W)),
(CONV_SIGNED(FP,ROMDATA_W),CONV_SIGNED(DM,ROMDATA_W),CONV_SIGNED(GP,ROMDATA_W),CONV_SIGNED(EP,ROMDATA_W)),
(CONV_SIGNED(GP,ROMDATA_W),CONV_SIGNED(FM,ROMDATA_W),CONV_SIGNED(EP,ROMDATA_W),CONV_SIGNED(DM,ROMDATA_W))
);
end MDCTTB_PKG;
--------------------------------------------------
-- PACKAGE BODY
--------------------------------------------------
package body MDCTTB_PKG is
--------------------------------------------------------------------------
-- converts an INTEGER into a CHARACTER
-- for 0 to 9 the obvious mapping is used, higher
-- values are mapped to the CHARACTERs A-Z
-- (this is usefull for systems with base > 10)
-- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
--------------------------------------------------------------------------
function CHR(int: INTEGER) return CHARACTER is
variable c: CHARACTER;
begin
case int is
when 0 => c := '0';
when 1 => c := '1';
when 2 => c := '2';
when 3 => c := '3';
when 4 => c := '4';
when 5 => c := '5';
when 6 => c := '6';
when 7 => c := '7';
when 8 => c := '8';
when 9 => c := '9';
when 10 => c := 'A';
when 11 => c := 'B';
when 12 => c := 'C';
when 13 => c := 'D';
when 14 => c := 'E';
when 15 => c := 'F';
when 16 => c := 'G';
when 17 => c := 'H';
when 18 => c := 'I';
when 19 => c := 'J';
when 20 => c := 'K';
when 21 => c := 'L';
when 22 => c := 'M';
when 23 => c := 'N';
when 24 => c := 'O';
when 25 => c := 'P';
when 26 => c := 'Q';
when 27 => c := 'R';
when 28 => c := 'S';
when 29 => c := 'T';
when 30 => c := 'U';
when 31 => c := 'V';
when 32 => c := 'W';
when 33 => c := 'X';
when 34 => c := 'Y';
when 35 => c := 'Z';
when others => c := '?';
end case;
return c;
end CHR;
--------------------------------------------------------------------------
-- convert INTEGER to STRING using specified base
--------------------------------------------------------------------------
function STR(int: INTEGER; base: INTEGER) return STRING is
variable temp: STRING(1 to 10);
variable num: INTEGER;
variable abs_int: INTEGER;
variable len: INTEGER := 1;
variable power: INTEGER := 1;
begin
-- bug fix for negative numbers
abs_int := abs(int);
num := abs_int;
while num >= base loop
len := len + 1;
num := num / base;
end loop ;
for i in len downto 1 loop
temp(i) := chr(abs_int/power mod base);
power := power * base;
end loop ;
-- return result and add sign if required
if int < 0 then
return '-'& temp(1 to len);
else
return temp(1 to len);
end if;
end STR;
------------------------------------------------
-- computes DCT1D
------------------------------------------------
function COMPUTE_REF_DCT1D(input_matrix : I_MATRIX_TYPE; shift : BOOLEAN)
return I_MATRIX_TYPE is
variable fXm : VECTOR4 := (0.0,0.0,0.0,0.0);
variable fXs : VECTOR4 := (0.0,0.0,0.0,0.0);
variable fYe : VECTOR4 := (0.0,0.0,0.0,0.0);
variable fYo : VECTOR4 := (0.0,0.0,0.0,0.0);
variable ref_dct_matrix : I_MATRIX_TYPE;
variable norma_input : MATRIX_TYPE;
begin
-- compute reference coefficients
for x in 0 to N-1 loop
for s in 0 to 7 loop
if shift = TRUE then
norma_input(x,s) := (REAL(input_matrix(x,s))- REAL(LEVEL_SHIFT))/2.0;
else
norma_input(x,s) := REAL(input_matrix(x,s))/2.0;
end if;
end loop;
fXs(0) := norma_input(x,0)+norma_input(x,7);
fXs(1) := norma_input(x,1)+norma_input(x,6);
fXs(2) := norma_input(x,2)+norma_input(x,5);
fXs(3) := norma_input(x,3)+norma_input(x,4);
fXm(0) := norma_input(x,0)-norma_input(x,7);
fXm(1) := norma_input(x,1)-norma_input(x,6);
fXm(2) := norma_input(x,2)-norma_input(x,5);
fXm(3) := norma_input(x,3)-norma_input(x,4);
for k in 0 to N/2-1 loop
fYe(k) := REAL(CONV_INTEGER(Ce(k,0)))*fXs(0) +
REAL(CONV_INTEGER(Ce(k,1)))*fXs(1) +
REAL(CONV_INTEGER(Ce(k,2)))*fXs(2) +
REAL(CONV_INTEGER(Ce(k,3)))*fXs(3);
fYo(k) := REAL(CONV_INTEGER(Co(k,0)))*fXm(0) +
REAL(CONV_INTEGER(Co(k,1)))*fXm(1) +
REAL(CONV_INTEGER(Co(k,2)))*fXm(2) +
REAL(CONV_INTEGER(Co(k,3)))*fXm(3);
end loop;
-- transpose matrix by writing in row order
ref_dct_matrix(0,x) := INTEGER(fYe(0)/REAL((2**(COE_W-1))));
ref_dct_matrix(1,x) := INTEGER(fYo(0)/REAL((2**(COE_W-1))));
ref_dct_matrix(2,x) := INTEGER(fYe(1)/REAL((2**(COE_W-1))));
ref_dct_matrix(3,x) := INTEGER(fYo(1)/REAL((2**(COE_W-1))));
ref_dct_matrix(4,x) := INTEGER(fYe(2)/REAL((2**(COE_W-1))));
ref_dct_matrix(5,x) := INTEGER(fYo(2)/REAL((2**(COE_W-1))));
ref_dct_matrix(6,x) := INTEGER(fYe(3)/REAL((2**(COE_W-1))));
ref_dct_matrix(7,x) := INTEGER(fYo(3)/REAL((2**(COE_W-1))));
end loop;
return ref_dct_matrix;
end COMPUTE_REF_DCT1D;
-----------------------------------------------
-- compares NxN matrices, logs failure if difference
-- greater than maximum error specified
-----------------------------------------------
procedure CMP_MATRIX(ref_matrix : in I_MATRIX_TYPE;
dcto_matrix : in I_MATRIX_TYPE;
max_error : in INTEGER;
error_matrix : out I_MATRIX_TYPE;
error_cnt : inout INTEGER
) is
variable error_matrix_v : I_MATRIX_TYPE;
begin
for a in 0 to N - 1 loop
for b in 0 to N - 1 loop
error_matrix_v(a,b) := ref_matrix(a,b) - dcto_matrix(a,b);
if abs(error_matrix_v(a,b)) > max_error then
error_cnt := error_cnt + 1;
assert false
report "E01: DCT max error violated!"
severity Error;
end if;
end loop;
end loop;
error_matrix := error_matrix_v;
end CMP_MATRIX;
------------------------------------------------
-- computes IDCT on NxN matrix
------------------------------------------------
function COMPUTE_REF_IDCT(X : I_MATRIX_TYPE)
return I_MATRIX_TYPE is
variable i : INTEGER := 0;
variable j : INTEGER := 0;
variable u : INTEGER := 0;
variable v : INTEGER := 0;
variable Cu : REAL;
variable Cv : REAL;
variable xi : MATRIX_TYPE := null_data_r;
variable xr : I_MATRIX_TYPE;
begin
-- idct
for i in 0 to N-1 loop
for j in 0 to N-1 loop
for u in 0 to N-1 loop
if u = 0 then
Cu := 1.0/sqrt(2.0);
else
Cu := 1.0;
end if;
for v in 0 to N-1 loop
if v = 0 then
Cv := 1.0/sqrt(2.0);
else
Cv := 1.0;
end if;
xi(i,j) := xi(i,j) +
2.0/REAL(N)*Cu*Cv*REAL(X(u,v))*
cos( ( (2.0*REAL(i)+1.0)*REAL(u)*MATH_PI ) / (2.0*REAL(N)) )*
cos( ( (2.0*REAL(j)+1.0)*REAL(v)*MATH_PI ) / (2.0*REAL(N)) );
xr(i,j) := INTEGER(ROUND(xi(i,j)))+LEVEL_SHIFT;
end loop;
end loop;
end loop;
end loop;
return xr;
end COMPUTE_REF_IDCT;
------------------------------------------------
-- computes peak signal to noise ratio
-- for reconstruced and input image data
------------------------------------------------
function COMPUTE_PSNR(ref_input : I_MATRIX_TYPE;
reconstr_input : I_MATRIX_TYPE) return REAL is
variable psnr_tmp : REAL := 0.0;
begin
for i in 0 to N-1 loop
for j in 0 to N-1 loop
psnr_tmp := psnr_tmp + (REAL(ref_input(i,j))-REAL(reconstr_input(i,j)))**2;
end loop;
end loop;
psnr_tmp := psnr_tmp / (REAL(N)*REAL(N));
psnr_tmp := 10.0*LOG10( (REAL(MAX_PIX_VAL)**2) / psnr_tmp );
return psnr_tmp;
end COMPUTE_PSNR;
------------------------------------------------
-- computes peak signal to noise ratio
-- for reconstruced and input image data
------------------------------------------------
function COMPUTE_PSNR(ref_input : IMAGE_TYPE;
reconstr_input : IMAGE_TYPE;
ysize : INTEGER;
xsize : INTEGER
) return REAL is
variable psnr_tmp : REAL := 0.0;
variable lineb : LINE;
begin
for i in 0 to ysize-1 loop
for j in 0 to xsize-1 loop
psnr_tmp := psnr_tmp +
(REAL(ref_input(i,j))-REAL(reconstr_input(i,j)))**2;
end loop;
end loop;
psnr_tmp := psnr_tmp / (REAL(ysize)*REAL(xsize));
--WRITE(lineb,STRING'("MSE Mean Squared Error is "));
--WRITE(lineb,psnr_tmp);
--assert false
-- report lineb.all
-- severity Note;
psnr_tmp := 10.0*LOG10( (REAL(MAX_PIX_VAL)**2) / psnr_tmp );
return psnr_tmp;
end COMPUTE_PSNR;
end MDCTTB_PKG; | lgpl-3.0 | d864db49437a1761859478ce6c22dd0e | 0.410125 | 3.634559 | false | false | false | false |
markusC64/1541ultimate2 | fpga/io/usb/vhdl_sim/ulpi_phy_bfm.vhd | 2 | 6,987 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity usb1_ulpi_phy_bfm is
generic (
g_rx_interval : integer := 100 );
port (
clock : in std_logic;
reset : in std_logic;
ULPI_DATA : inout std_logic_vector(7 downto 0);
ULPI_DIR : out std_logic;
ULPI_NXT : out std_logic;
ULPI_STP : in std_logic );
end usb1_ulpi_phy_bfm;
architecture gideon of usb1_ulpi_phy_bfm is
type t_state is (idle, sending, receiving, read_reg, read_reg2, read_reg3, write_reg, status_update);
signal state : t_state;
signal pattern : std_logic_vector(0 to 19);
signal do_send : std_logic;
signal counter : unsigned(7 downto 0) := X"01";
signal status_in : std_logic_vector(7 downto 0) := X"00";
signal status_d : std_logic_vector(7 downto 0) := X"00";
signal ulpi_nxt_i : std_logic;
signal ulpi_dir_i : std_logic;
alias ulpi_cmd : std_logic_vector(1 downto 0) is ULPI_DATA(7 downto 6);
constant c_transmit : std_logic_vector(1 downto 0) := "01";
constant c_write_reg : std_logic_vector(1 downto 0) := "10";
constant c_read_reg : std_logic_vector(1 downto 0) := "11";
begin
process(clock)
variable byte_count : integer := 0;
variable rx_interval : integer := g_rx_interval;
variable address : std_logic_vector(5 downto 0);
procedure set_reg(addr: std_logic_vector(5 downto 0);
data: std_logic_vector(7 downto 0) ) is
begin
if addr = "001010" then
if data(5)='1' or data(6)='1' then-- poweron
report "Power On";
if status_in(3)='0' then
status_in(3 downto 2) <= transport "00",
"01" after 10 us,
"10" after 20 us,
"11" after 30 us;
end if;
else -- power off
report "Power Off";
status_in(3 downto 2) <= transport "11",
"10" after 1 us,
"01" after 2 us,
"00" after 3 us;
end if;
end if;
if addr = "000100" then
case data(2 downto 0) is
when "000" => -- host chirp
status_in(1 downto 0) <= transport "00", "10" after 10 us, "00" after 15 us;
when "001"|"011" => -- powerup
status_in(1 downto 0) <= "11";
when "010" => -- unknown
status_in(1 downto 0) <= "00";
when "100" => -- peripheral chirp
status_in(1 downto 0) <= "10";
when "101"|"111" => -- peripheral FS
status_in(1 downto 0) <= "01";
when "110" => -- peripheral LS
status_in(1 downto 0) <= "10";
when others =>
null;
end case;
end if;
end procedure;
begin
if rising_edge(clock) then
if rx_interval = 0 then
do_send <= '0'; -- autonomous send disabled
rx_interval := g_rx_interval;
else
rx_interval := rx_interval - 1;
end if;
ulpi_nxt_i <= '0';
case state is
when idle =>
status_d <= status_in;
ulpi_dir_i <= '0';
ULPI_DATA <= (others => 'Z');
if do_send = '1' then
do_send <= '0';
ulpi_dir_i <= '1';
ulpi_nxt_i <= '1';
pattern <= "01111101111011101101";
state <= sending;
byte_count := 20;
elsif ulpi_dir_i = '0' then
if ulpi_cmd = c_transmit then
pattern <= "11111111100111011010";
state <= receiving;
elsif ulpi_cmd = c_write_reg then
address := ULPI_DATA(5 downto 0);
byte_count := 2;
state <= write_reg;
elsif ulpi_cmd = c_read_reg then
state <= read_reg;
elsif status_in /= status_d then
ulpi_dir_i <= '1';
state <= status_update;
end if;
end if;
when status_update =>
ULPI_DATA <= status_d;
state <= idle;
when sending =>
pattern <= pattern(1 to 19) & '0';
if pattern(0)='1' then
ULPI_DATA <= std_logic_vector(counter);
ulpi_nxt_i <= '1';
counter <= counter + 1;
else
ULPI_DATA <= status_in;
ulpi_nxt_i <= '0';
end if;
byte_count := byte_count - 1;
if byte_count = 0 then
state <= idle;
end if;
when receiving =>
if ULPI_STP = '1' then
ulpi_nxt_i <= '0';
state <= idle;
else
ulpi_nxt_i <= pattern(0);
pattern <= pattern(1 to 19) & '1';
end if;
when write_reg =>
if byte_count = 0 then
ulpi_nxt_i <= '0';
set_reg(address, ULPI_DATA);
else
ulpi_nxt_i <= '1';
end if;
byte_count := byte_count - 1;
if ULPI_STP = '1' then
state <= idle;
end if;
when read_reg =>
ulpi_nxt_i <= '1';
state <= read_reg2;
when read_reg2 =>
ulpi_dir_i <= '1';
state <= read_reg3;
when read_reg3 =>
ULPI_DATA <= X"AA";
state <= idle;
when others =>
state <= idle;
end case;
if reset='1' then
state <= idle;
end if;
end if;
end process;
ULPI_NXT <= ulpi_nxt_i;
ULPI_DIR <= ulpi_dir_i;
end gideon;
| gpl-3.0 | 6dd761991918edc5a47d6021a0027e45 | 0.379991 | 4.563684 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/leon3/grfpwxsh.vhd | 2 | 9,517 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: grfpwxsh
-- File: grfpwxsh.vhd
-- Author: Edvin Catovic - Gaisler Research
-- Description: GRFPU/GRFPC wrapper and FP register file
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.leon3.all;
entity grfpwxsh is
generic (tech : integer range 0 to NTECH := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer range 0 to 1 := 0;
disas : integer range 0 to 2 := 0;
id : integer range 0 to 7 := 0);
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi : in fpc_in_type;
cpo : out fpc_out_type;
fpui : out grfpu_in_type;
fpuo : in grfpu_out_type
);
end;
architecture rtl of grfpwxsh is
signal rfi1, rfi2 : fp_rf_in_type;
signal rfo1, rfo2 : fp_rf_out_type;
component grfpwsh
generic (tech : integer range 0 to NTECH := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer range 0 to 1 := 0;
disas : integer range 0 to 2 := 0;
id : integer range 0 to 7 := 0
);
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi_flush : in std_ulogic; -- pipeline flush
cpi_exack : in std_ulogic; -- FP exception acknowledge
cpi_a_rs1 : in std_logic_vector(4 downto 0);
cpi_d_pc : in std_logic_vector(31 downto 0);
cpi_d_inst : in std_logic_vector(31 downto 0);
cpi_d_cnt : in std_logic_vector(1 downto 0);
cpi_d_trap : in std_ulogic;
cpi_d_annul : in std_ulogic;
cpi_d_pv : in std_ulogic;
cpi_a_pc : in std_logic_vector(31 downto 0);
cpi_a_inst : in std_logic_vector(31 downto 0);
cpi_a_cnt : in std_logic_vector(1 downto 0);
cpi_a_trap : in std_ulogic;
cpi_a_annul : in std_ulogic;
cpi_a_pv : in std_ulogic;
cpi_e_pc : in std_logic_vector(31 downto 0);
cpi_e_inst : in std_logic_vector(31 downto 0);
cpi_e_cnt : in std_logic_vector(1 downto 0);
cpi_e_trap : in std_ulogic;
cpi_e_annul : in std_ulogic;
cpi_e_pv : in std_ulogic;
cpi_m_pc : in std_logic_vector(31 downto 0);
cpi_m_inst : in std_logic_vector(31 downto 0);
cpi_m_cnt : in std_logic_vector(1 downto 0);
cpi_m_trap : in std_ulogic;
cpi_m_annul : in std_ulogic;
cpi_m_pv : in std_ulogic;
cpi_x_pc : in std_logic_vector(31 downto 0);
cpi_x_inst : in std_logic_vector(31 downto 0);
cpi_x_cnt : in std_logic_vector(1 downto 0);
cpi_x_trap : in std_ulogic;
cpi_x_annul : in std_ulogic;
cpi_x_pv : in std_ulogic;
cpi_lddata : in std_logic_vector(31 downto 0); -- load data
cpi_dbg_enable : in std_ulogic;
cpi_dbg_write : in std_ulogic;
cpi_dbg_fsr : in std_ulogic; -- FSR access
cpi_dbg_addr : in std_logic_vector(4 downto 0);
cpi_dbg_data : in std_logic_vector(31 downto 0);
cpo_data : out std_logic_vector(31 downto 0); -- store data
cpo_exc : out std_logic; -- FP exception
cpo_cc : out std_logic_vector(1 downto 0); -- FP condition codes
cpo_ccv : out std_ulogic; -- FP condition codes valid
cpo_ldlock : out std_logic; -- FP pipeline hold
cpo_holdn : out std_ulogic;
--cpo_restart : out std_ulogic;
cpo_dbg_data : out std_logic_vector(31 downto 0);
rfi1_rd1addr : out std_logic_vector(3 downto 0);
rfi1_rd2addr : out std_logic_vector(3 downto 0);
rfi1_wraddr : out std_logic_vector(3 downto 0);
rfi1_wrdata : out std_logic_vector(31 downto 0);
rfi1_ren1 : out std_ulogic;
rfi1_ren2 : out std_ulogic;
rfi1_wren : out std_ulogic;
rfi2_rd1addr : out std_logic_vector(3 downto 0);
rfi2_rd2addr : out std_logic_vector(3 downto 0);
rfi2_wraddr : out std_logic_vector(3 downto 0);
rfi2_wrdata : out std_logic_vector(31 downto 0);
rfi2_ren1 : out std_ulogic;
rfi2_ren2 : out std_ulogic;
rfi2_wren : out std_ulogic;
rfo1_data1 : in std_logic_vector(31 downto 0);
rfo1_data2 : in std_logic_vector(31 downto 0);
rfo2_data1 : in std_logic_vector(31 downto 0);
rfo2_data2 : in std_logic_vector(31 downto 0);
start : out std_logic;
nonstd : out std_logic;
flop : out std_logic_vector(8 downto 0);
op1 : out std_logic_vector(63 downto 0);
op2 : out std_logic_vector(63 downto 0);
opid : out std_logic_vector(7 downto 0);
flush : out std_logic;
flushid : out std_logic_vector(5 downto 0);
rndmode : out std_logic_vector(1 downto 0);
req : out std_logic;
res : in std_logic_vector(63 downto 0);
exc : in std_logic_vector(5 downto 0);
allow : in std_logic_vector(2 downto 0);
rdy : in std_logic;
cc : in std_logic_vector(1 downto 0);
idout : in std_logic_vector(7 downto 0)
);
end component;
begin
x0 : grfpwsh generic map (tech, pclow, dsu, disas, id)
port map (rst,
clk,
holdn,
cpi.flush ,
cpi.exack ,
cpi.a_rs1 ,
cpi.d.pc ,
cpi.d.inst ,
cpi.d.cnt ,
cpi.d.trap ,
cpi.d.annul ,
cpi.d.pv ,
cpi.a.pc ,
cpi.a.inst ,
cpi.a.cnt ,
cpi.a.trap ,
cpi.a.annul ,
cpi.a.pv ,
cpi.e.pc ,
cpi.e.inst ,
cpi.e.cnt ,
cpi.e.trap ,
cpi.e.annul ,
cpi.e.pv ,
cpi.m.pc ,
cpi.m.inst ,
cpi.m.cnt ,
cpi.m.trap ,
cpi.m.annul ,
cpi.m.pv ,
cpi.x.pc ,
cpi.x.inst ,
cpi.x.cnt ,
cpi.x.trap ,
cpi.x.annul ,
cpi.x.pv ,
cpi.lddata ,
cpi.dbg.enable ,
cpi.dbg.write ,
cpi.dbg.fsr ,
cpi.dbg.addr ,
cpi.dbg.data ,
cpo.data ,
cpo.exc ,
cpo.cc ,
cpo.ccv ,
cpo.ldlock ,
cpo.holdn ,
cpo.dbg.data ,
rfi1.rd1addr ,
rfi1.rd2addr ,
rfi1.wraddr ,
rfi1.wrdata ,
rfi1.ren1 ,
rfi1.ren2 ,
rfi1.wren ,
rfi2.rd1addr ,
rfi2.rd2addr ,
rfi2.wraddr ,
rfi2.wrdata ,
rfi2.ren1 ,
rfi2.ren2 ,
rfi2.wren ,
rfo1.data1 ,
rfo1.data2 ,
rfo2.data1 ,
rfo2.data2 ,
fpui.start ,
fpui.nonstd ,
fpui.flop ,
fpui.op1 ,
fpui.op2 ,
fpui.opid ,
fpui.flush ,
fpui.flushid ,
fpui.rndmode ,
fpui.req ,
fpuo.res ,
fpuo.exc ,
fpuo.allow ,
fpuo.rdy ,
fpuo.cc ,
fpuo.idout
);
rf1 : regfile_3p generic map (tech, 4, 32, 1, 16)
port map (clk, rfi1.wraddr, rfi1.wrdata, rfi1.wren, clk, rfi1.rd1addr, rfi1.ren1, rfo1.data1,
rfi1.rd2addr, rfi1.ren2, rfo1.data2);
rf2 : regfile_3p generic map (tech, 4, 32, 1, 16)
port map (clk, rfi2.wraddr, rfi2.wrdata, rfi2.wren, clk, rfi2.rd1addr, rfi2.ren1, rfo2.data1,
rfi2.rd2addr, rfi2.ren2, rfo2.data2);
end;
| mit | 4dab2304d5ae0fbd76a6465157f00864 | 0.481769 | 3.519601 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/pci/pcitrace.vhd | 2 | 7,635 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: pcitrace
-- File: pcitrace.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: PCI trace buffer
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.pci.all;
entity pcitrace is
generic (
depth : integer range 6 to 12 := 8;
iregs : integer := 1;
memtech : integer := DEFMEMTECH;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#f00#
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
pciclk : in std_ulogic;
pcii : in pci_in_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type
);
end;
architecture rtl of pcitrace is
constant REVISION : amba_version_type := 0;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_PCITRACE, 0, REVISION, 0),
1 => apb_iobar(paddr, pmask));
type reg_type is record
sample : std_ulogic;
armed : std_ulogic;
busy : std_ulogic;
timeout : std_logic_vector(depth-1 downto 0);
admask : std_logic_vector(31 downto 0);
adpattern : std_logic_vector(31 downto 0);
sigmask : std_logic_vector(15 downto 0);
sigpattern : std_logic_vector(15 downto 0);
count : std_logic_vector(7 downto 0);
end record;
type pci_reg_type is record
sample : std_ulogic;
armed : std_ulogic;
sync : std_ulogic;
start : std_ulogic;
timeout : std_logic_vector(depth-1 downto 0);
baddr : std_logic_vector(depth-1 downto 0);
count : std_logic_vector(7 downto 0);
end record;
signal r, rin : reg_type;
signal csad, csctrl : std_ulogic;
signal pr, prin : pci_reg_type;
signal bufout : std_logic_vector(47 downto 0);
signal pciad : std_logic_vector(31 downto 0);
signal vcc : std_ulogic;
signal pcictrlin, pcictrl : std_logic_vector(15 downto 0);
begin
vcc <= '1';
comb: process(pcii, apbi, rst, r, pr, bufout)
variable v : reg_type;
variable rdata : std_logic_vector(31 downto 0);
variable paddr : std_logic_vector(3 downto 0);
variable vcsad, vcssig : std_ulogic;
begin
v := r; vcsad := '0'; vcssig := '0'; rdata := (others => '0');
v.sample := r.armed and not pr.armed; v.busy := pr.sample;
if (r.sample and pr.armed) = '1' then v.armed := '0'; end if;
--registers
paddr := apbi.paddr(15) & apbi.paddr(4 downto 2);
if apbi.penable = '1' then
if (apbi.pwrite and apbi.psel(pindex)) = '1' then
case paddr is
when "0000" => v.admask := apbi.pwdata;
when "0001" => v.sigmask := apbi.pwdata(15 downto 0);
when "0010" => v.adpattern := apbi.pwdata;
when "0011" => v.sigpattern := apbi.pwdata(15 downto 0);
when "0100" => v.timeout := apbi.pwdata(depth-1 downto 0);
when "0101" => v.armed := '1';
when "0111" => v.count := apbi.pwdata(7 downto 0);
when others =>
if apbi.paddr(15 downto 14) = "10" then vcsad := '1';
elsif apbi.paddr(15 downto 14) = "11" then vcssig := '1'; end if;
end case;
end if;
case paddr is
when "0000" => rdata := r.admask;
when "0001" => rdata(15 downto 0) := r.sigmask;
when "0010" => rdata := r.adpattern;
when "0011" => rdata(15 downto 0) := r.sigpattern;
when "0100" => rdata(depth-1 downto 0) := r.timeout;
when "0101" => rdata(0) := r.busy;
when "0110" => rdata(3 downto 0) := conv_std_logic_vector(depth, 4);
when "0111" =>
rdata(depth-1+16 downto 16) := pr.baddr;
rdata(15 downto 0) := pr.count & r.count;
when others =>
if apbi.paddr(15 downto 14) = "10" then
vcsad := '1'; rdata := bufout(31 downto 0);
elsif apbi.paddr(15 downto 14) = "11" then
vcssig := '1'; rdata(15 downto 0) := bufout(47 downto 32);
end if;
end case;
end if;
if rst = '0' then
v.sample := '0'; v.armed := '0'; v.admask := (others => '0');
v.sigmask := (others => '0'); v.adpattern := (others => '0');
v.sigpattern := (others => '0'); v.timeout := (others => '0');
end if;
csad <= vcsad; csctrl <= vcssig; apbo.prdata <= rdata; rin <= v;
end process;
comb2 : process(r, pr, pciclk, pcii, pcictrl, rst)
variable v : pci_reg_type;
constant z : std_logic_vector(47 downto 0) := (others => '0');
begin
v := pr; v.sync := (r.sample and not pr.armed);
if (pr.sample = '1') then
v.baddr := pr.baddr + 1;
if ((((pcii.ad & pcictrl) xor (r.adpattern & r.sigpattern)) and (r.admask & r.sigmask)) = z) then
if pr.count = "00000000" then v.start := '0';
else v.count := pr.count -1; end if;
end if;
if (pr.start = '0') then
v.timeout := pr.timeout - 1;
if (v.timeout(depth-1) and not pr.timeout(depth-1)) = '1' then
v.sample := '0'; v.armed := '0';
end if;
end if;
end if;
if pr.sync = '1' then
v.start := '1'; v.sample := '1'; v.armed := '1';
v.timeout := r.timeout; v.count := r.count;
end if;
if rst = '0' then
v.sample := '0'; v.armed := '0'; v.start := '0';
v.timeout := (others => '0'); v.baddr := (others => '0');
v.count := (others => '0');
end if;
prin <= v;
end process ;
pcictrlin <= pcii.rst & pcii.idsel & pcii.frame & pcii.trdy & pcii.irdy &
pcii.devsel & pcii.gnt & pcii.stop & pcii.lock & pcii.perr &
pcii.serr & pcii.par & pcii.cbe;
apbo.pconfig <= pconfig;
apbo.pindex <= pindex;
apbo.pirq <= (others => '0');
seq: process (clk)
begin
if clk'event and clk = '1' then r <= rin; end if;
end process seq;
pseq: process (pciclk)
begin
if pciclk'event and pciclk = '1' then pr <= prin; end if;
end process ;
ir : if iregs = 1 generate
pseq: process (pciclk)
begin
if pciclk'event and pciclk = '1' then
pcictrl <= pcictrlin; pciad <= pcii.ad;
end if;
end process ;
end generate;
noir : if iregs = 0 generate
pcictrl <= pcictrlin; pciad <= pcii.ad;
end generate;
admem : syncram_2p generic map (tech => memtech, abits => depth, dbits => 32)
port map (clk, csad, apbi.paddr(depth+1 downto 2), bufout(31 downto 0),
pciclk, pr.sample, pr.baddr, pciad);
ctrlmem : syncram_2p generic map (tech => memtech, abits => depth, dbits => 16)
port map (clk, csctrl, apbi.paddr(depth+1 downto 2), bufout(47 downto 32),
pciclk, pr.sample, pr.baddr, pcictrl);
end;
| mit | 1365fcda9487163bf9a05ce4fd971fd7 | 0.57721 | 3.334061 | false | false | false | false |
cafe-alpha/wascafe | v13/r07c_de10_20201014_abus4/wasca_toplevel.vhd | 2 | 18,731 | -- wasca.vhd
-- Generated using ACDS version 14.1 186 at 2015.05.28.08:37:08
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity wasca_toplevel is
port (
clk_clk : in std_logic := '0'; -- clk.clk
external_sdram_controller_wire_addr : out std_logic_vector(12 downto 0); -- external_sdram_controller_wire.addr
external_sdram_controller_wire_ba : out std_logic_vector(1 downto 0); -- .ba
external_sdram_controller_wire_cas_n : out std_logic; -- .cas_n
external_sdram_controller_wire_cke : out std_logic; -- .cke
external_sdram_controller_wire_cs_n : out std_logic; -- .cs_n
external_sdram_controller_wire_dq : inout std_logic_vector(15 downto 0) := (others => '0'); -- .dq
external_sdram_controller_wire_dqm : out std_logic_vector(1 downto 0); -- .dqm
external_sdram_controller_wire_ras_n : out std_logic; -- .ras_n
external_sdram_controller_wire_we_n : out std_logic; -- .we_n
external_sdram_controller_wire_clk : out std_logic; -- .clk
reset_reset_n : in std_logic := '0'; -- reset.reset_n
sega_saturn_abus_slave_0_abus_address : in std_logic_vector(25 downto 16) := (others => '0'); -- sega_saturn_abus_slave_0_abus.address
sega_saturn_abus_slave_0_abus_addressdata : inout std_logic_vector(15 downto 0) := (others => '0'); -- .data
sega_saturn_abus_slave_0_abus_chipselect : in std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
sega_saturn_abus_slave_0_abus_read : in std_logic := '0'; -- .read
sega_saturn_abus_slave_0_abus_write : in std_logic_vector(1 downto 0) := (others => '0'); -- .write
sega_saturn_abus_slave_0_abus_waitrequest : out std_logic; -- .waitrequest
sega_saturn_abus_slave_0_abus_interrupt : out std_logic := '0'; -- .interrupt
sega_saturn_abus_slave_0_abus_disableout : out std_logic := '0'; -- .muxing
sega_saturn_abus_slave_0_abus_muxing : out std_logic_vector(1 downto 0) := (others => '0'); -- .muxing
sega_saturn_abus_slave_0_abus_direction : out std_logic := '0'; -- .direction
--altera_up_sd_card_avalon_interface_0_conduit_end_b_SD_cmd : inout std_logic := 'X'; -- b_SD_cmd
--altera_up_sd_card_avalon_interface_0_conduit_end_b_SD_dat : inout std_logic := 'X'; -- b_SD_dat
--altera_up_sd_card_avalon_interface_0_conduit_end_b_SD_dat3 : inout std_logic := 'X'; -- b_SD_dat3
--altera_up_sd_card_avalon_interface_0_conduit_end_o_SD_clock : out std_logic ; -- o_SD_clock
uart_0_external_connection_txd : out std_logic := '0'; --
uart_0_external_connection_rxd : in std_logic := 'X'; --
hex0_conn_export : out std_logic_vector(6 downto 0);
hex1_conn_export : out std_logic_vector(6 downto 0);
hex2_conn_export : out std_logic_vector(6 downto 0);
hex3_conn_export : out std_logic_vector(6 downto 0);
hex4_conn_export : out std_logic_vector(6 downto 0);
hex5_conn_export : out std_logic_vector(6 downto 0);
hexdot_conn_export : out std_logic_vector(5 downto 0);
leds_conn_export : out std_logic_vector(3 downto 0); -- leds_conn_export[0]: ledr1, leds_conn_export[1]: ledg1, leds_conn_export[2]: ledo1, leds_conn_export[3]: ledo2
extra_leds_conn_export : out std_logic_vector(4 downto 0); -- Extra LEDs for DE10-lite only, mapped to their own control register
switches_conn_export : in std_logic_vector(7 downto 0); -- switches_conn_export[0]: sw1, switches_conn_export[1]: sw2, switches_conn_export[2]: unused clock (SCSPCLK from SIM, or EXT from same board)
spi_sync_conn_export : in std_logic; -- SPI synchronization
spi_stm32_MOSI : out std_logic := '0'; -- MOSI
spi_stm32_MISO : in std_logic; -- MISO
spi_stm32_SCLK : out std_logic := '0'; -- SCLK
spi_stm32_SS_n : out std_logic := '0' -- SS_n
--audio_out_BCLK : in std_logic := '0'; -- BCLK
--audio_out_DACDAT : out std_logic; -- DACDAT
--audio_out_DACLRCK : in std_logic := '0'; -- DACLRCK
--audio_SSEL : out std_logic := '0'
);
end entity wasca_toplevel;
architecture rtl of wasca_toplevel is
component wasca is
port (
abus_avalon_sdram_bridge_0_abus_address : in std_logic_vector(9 downto 0) := (others => 'Z'); -- address
abus_avalon_sdram_bridge_0_abus_read : in std_logic := 'Z'; -- read
abus_avalon_sdram_bridge_0_abus_waitrequest : out std_logic; -- waitrequest
abus_avalon_sdram_bridge_0_abus_addressdata : inout std_logic_vector(15 downto 0) := (others => 'Z'); -- addressdata
abus_avalon_sdram_bridge_0_abus_chipselect : in std_logic_vector(2 downto 0) := (others => 'Z'); -- chipselect
abus_avalon_sdram_bridge_0_abus_direction : out std_logic; -- direction
abus_avalon_sdram_bridge_0_abus_disable_out : out std_logic; -- disable_out
abus_avalon_sdram_bridge_0_abus_interrupt : out std_logic; -- interrupt
abus_avalon_sdram_bridge_0_abus_muxing : out std_logic_vector(1 downto 0); -- muxing
abus_avalon_sdram_bridge_0_abus_writebyteenable_n : in std_logic_vector(1 downto 0) := (others => 'Z'); -- writebyteenable_n
abus_avalon_sdram_bridge_0_abus_reset : in std_logic := 'Z'; -- reset
abus_avalon_sdram_bridge_0_sdram_addr : out std_logic_vector(12 downto 0); -- addr
abus_avalon_sdram_bridge_0_sdram_ba : out std_logic_vector(1 downto 0); -- ba
abus_avalon_sdram_bridge_0_sdram_cas_n : out std_logic; -- cas_n
abus_avalon_sdram_bridge_0_sdram_cke : out std_logic; -- cke
abus_avalon_sdram_bridge_0_sdram_cs_n : out std_logic; -- cs_n
abus_avalon_sdram_bridge_0_sdram_dq : inout std_logic_vector(15 downto 0) := (others => 'Z'); -- dq
abus_avalon_sdram_bridge_0_sdram_dqm : out std_logic_vector(1 downto 0); -- dqm
abus_avalon_sdram_bridge_0_sdram_ras_n : out std_logic; -- ras_n
abus_avalon_sdram_bridge_0_sdram_we_n : out std_logic; -- we_n
abus_avalon_sdram_bridge_0_sdram_clk : out std_logic; -- clk
--audio_out_BCLK : in std_logic := 'Z'; -- BCLK
--audio_out_DACDAT : out std_logic; -- DACDAT
--audio_out_DACLRCK : in std_logic := 'Z'; -- DACLRCK
clk_clk : in std_logic := 'Z'; -- clk
clock_116_mhz_clk : out std_logic; -- clk
--altera_up_sd_card_avalon_interface_0_conduit_end_b_SD_cmd : inout std_logic := 'Z'; -- b_SD_cmd
--altera_up_sd_card_avalon_interface_0_conduit_end_b_SD_dat : inout std_logic := 'Z'; -- b_SD_dat
--altera_up_sd_card_avalon_interface_0_conduit_end_b_SD_dat3 : inout std_logic := 'Z'; -- b_SD_dat3
--sd_card_avalon_interface_0_conduit_end_o_SD_clock : out std_logic ; -- o_SD_clock
uart_0_external_connection_rxd : in std_logic := '0'; -- rxd
uart_0_external_connection_txd : out std_logic; -- txd
hex0_conn_export : out std_logic_vector(6 downto 0);
hex1_conn_export : out std_logic_vector(6 downto 0);
hex2_conn_export : out std_logic_vector(6 downto 0);
hex3_conn_export : out std_logic_vector(6 downto 0);
hex4_conn_export : out std_logic_vector(6 downto 0);
hex5_conn_export : out std_logic_vector(6 downto 0);
hexdot_conn_export : out std_logic_vector(5 downto 0);
leds_conn_export : out std_logic_vector(3 downto 0);
extra_leds_conn_export : out std_logic_vector(4 downto 0);
switches_conn_export : in std_logic_vector(7 downto 0);
spi_sync_conn_export : in std_logic; -- SPI synchronization
buffered_spi_miso : in std_logic; -- MISO
buffered_spi_mosi : out std_logic := 'Z'; -- MOSI
buffered_spi_clk : out std_logic := 'Z'; -- SCLK
buffered_spi_cs : out std_logic := 'Z'; -- SS_n
reset_reset_n : in std_logic := 'Z'; -- reset_n
reset_controller_0_reset_in1_reset : in std_logic := 'Z' ; -- reset
altpll_1_areset_conduit_export : in std_logic := 'Z'; -- export
altpll_1_locked_conduit_export : out std_logic; -- export
altpll_1_phasedone_conduit_export : out std_logic -- export
);
end component;
signal altpll_1_areset_conduit_export : std_logic := '0';
signal altpll_1_locked_conduit_export : std_logic := '0';
signal altpll_1_phasedone_conduit_export : std_logic := '0';
--signal sega_saturn_abus_slave_0_abus_address_demuxed : std_logic_vector(25 downto 0) := (others => '0');
--signal sega_saturn_abus_slave_0_abus_data_demuxed : std_logic_vector(15 downto 0) := (others => '0');
signal clock_116_mhz : std_logic := '0';
signal por_counter : unsigned(31 downto 0) := (others => '0');
signal por_reset : std_logic := '0';
signal por_reset_n : std_logic := '0';
begin
--sega_saturn_abus_slave_0_abus_muxing (0) <= not sega_saturn_abus_slave_0_abus_muxing(1);
external_sdram_controller_wire_clk <= not clock_116_mhz;
my_little_wasca : component wasca
port map (
clk_clk => clk_clk,
clock_116_mhz_clk => clock_116_mhz,
abus_avalon_sdram_bridge_0_sdram_addr => external_sdram_controller_wire_addr,
abus_avalon_sdram_bridge_0_sdram_ba => external_sdram_controller_wire_ba,
abus_avalon_sdram_bridge_0_sdram_cas_n => external_sdram_controller_wire_cas_n,
abus_avalon_sdram_bridge_0_sdram_cke => external_sdram_controller_wire_cke,
abus_avalon_sdram_bridge_0_sdram_cs_n => external_sdram_controller_wire_cs_n,
abus_avalon_sdram_bridge_0_sdram_dq => external_sdram_controller_wire_dq,
abus_avalon_sdram_bridge_0_sdram_dqm => external_sdram_controller_wire_dqm,
abus_avalon_sdram_bridge_0_sdram_ras_n => external_sdram_controller_wire_ras_n,
abus_avalon_sdram_bridge_0_sdram_we_n => external_sdram_controller_wire_we_n,
abus_avalon_sdram_bridge_0_abus_address => sega_saturn_abus_slave_0_abus_address,
abus_avalon_sdram_bridge_0_abus_chipselect => "1"&sega_saturn_abus_slave_0_abus_chipselect(1 downto 0),--work only with CS1 and CS0 for now
abus_avalon_sdram_bridge_0_abus_read => sega_saturn_abus_slave_0_abus_read,
abus_avalon_sdram_bridge_0_abus_writebyteenable_n => sega_saturn_abus_slave_0_abus_write,
abus_avalon_sdram_bridge_0_abus_waitrequest => sega_saturn_abus_slave_0_abus_waitrequest,
abus_avalon_sdram_bridge_0_abus_interrupt => sega_saturn_abus_slave_0_abus_interrupt,
abus_avalon_sdram_bridge_0_abus_addressdata => sega_saturn_abus_slave_0_abus_addressdata,
abus_avalon_sdram_bridge_0_abus_direction => sega_saturn_abus_slave_0_abus_direction,
abus_avalon_sdram_bridge_0_abus_muxing => sega_saturn_abus_slave_0_abus_muxing,
abus_avalon_sdram_bridge_0_abus_disable_out => sega_saturn_abus_slave_0_abus_disableout,
abus_avalon_sdram_bridge_0_abus_reset => reset_reset_n,
--altera_up_sd_card_avalon_interface_0_conduit_end_b_SD_dat3 => altera_up_sd_card_avalon_interface_0_conduit_end_b_SD_dat3,
--altera_up_sd_card_avalon_interface_0_conduit_end_b_SD_dat => altera_up_sd_card_avalon_interface_0_conduit_end_b_SD_dat,
--altera_up_sd_card_avalon_interface_0_conduit_end_o_SD_clock => altera_up_sd_card_avalon_interface_0_conduit_end_o_SD_clock,
--altera_up_sd_card_avalon_interface_0_conduit_end_b_SD_cmd => altera_up_sd_card_avalon_interface_0_conduit_end_b_SD_cmd,
altpll_1_areset_conduit_export => altpll_1_areset_conduit_export,
altpll_1_locked_conduit_export => altpll_1_locked_conduit_export,
altpll_1_phasedone_conduit_export => altpll_1_phasedone_conduit_export,
uart_0_external_connection_rxd => uart_0_external_connection_rxd,
uart_0_external_connection_txd => uart_0_external_connection_txd,
hex0_conn_export => hex0_conn_export,
hex1_conn_export => hex1_conn_export,
hex2_conn_export => hex2_conn_export,
hex3_conn_export => hex3_conn_export,
hex4_conn_export => hex4_conn_export,
hex5_conn_export => hex5_conn_export,
hexdot_conn_export => hexdot_conn_export,
leds_conn_export => leds_conn_export,
extra_leds_conn_export => extra_leds_conn_export,
switches_conn_export => switches_conn_export,
spi_sync_conn_export => spi_sync_conn_export,
buffered_spi_miso => spi_stm32_MISO,
buffered_spi_mosi => spi_stm32_MOSI,
buffered_spi_clk => spi_stm32_SCLK,
buffered_spi_cs => spi_stm32_SS_n,
--audio_out_BCLK => audio_out_BCLK,
--audio_out_DACDAT => audio_out_DACDAT,
--audio_out_DACLRCK => audio_out_DACLRCK,
reset_reset_n => por_reset_n,
reset_controller_0_reset_in1_reset => por_reset
);
--empty subsystem
-- external_sdram_controller_wire_addr <= (others => 'Z');
-- external_sdram_controller_wire_ba <= (others => 'Z');
-- external_sdram_controller_wire_cas_n <= (others => 'Z');
-- external_sdram_controller_wire_cke <= (others => 'Z');
-- external_sdram_controller_wire_cs_n <= (others => 'Z');
-- external_sdram_controller_wire_dq <= (others => 'Z');
-- external_sdram_controller_wire_dqm <= (others => 'Z');
-- external_sdram_controller_wire_ras_n <= (others => 'Z');
-- external_sdram_controller_wire_we_n <= (others => 'Z');
-- external_sdram_controller_wire_clk <= (others => 'Z');
-- sega_saturn_abus_slave_0_abus_addressdata <= (others => 'Z');
-- sega_saturn_abus_slave_0_abus_waitrequest <= (others => 'Z');
-- sega_saturn_abus_slave_0_abus_interrupt <= (others => 'Z');
-- sega_saturn_abus_slave_0_abus_disableout <= '1';
-- sega_saturn_abus_slave_0_abus_muxing <= "00";
-- sega_saturn_abus_slave_0_abus_direction <= '0';
-- spi_sd_card_MOSI <= 'Z';
-- spi_sd_card_SCLK <= 'Z';
-- spi_sd_card_SS_n <= 'Z';
-- uart_0_external_connection_txd <= 'Z';
-- spi_stm32_MISO <= 'Z';
-- audio_out_DACDAT <= 'Z';
--audio_SSEL <= '1';
--sega_saturn_abus_slave_0_abus_waitrequest <= '1';
--sega_saturn_abus_slave_0_abus_direction <= '0';
--sega_saturn_abus_slave_0_abus_muxing <= "01";
--por
process (clock_116_mhz)
begin
if std_logic(por_counter(24)) = '0' then
por_counter <= por_counter + 1;
end if;
end process;
por_reset <= (std_logic(por_counter(22)));
por_reset_n <= not (std_logic(por_counter(22)));
end architecture rtl; -- of wasca_toplevel
| gpl-2.0 | 26de9c2c95cc137d917262c4bee4ad3c | 0.493033 | 3.642746 | false | false | false | false |
michaelfivez/ascon_hardware_implementation | ascon12864_unrolled2/Kernel/DiffusionLayer.vhd | 1 | 1,687 | -------------------------------------------------------------------------------
--! @project Unrolled (2) hardware implementation of Asconv1286
--! @author Michael Fivez
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is an hardware implementation made for my graduation thesis
--! at the KULeuven, in the COSIC department (year 2015-2016)
--! The thesis is titled 'Energy efficient hardware implementations of CAESAR submissions',
--! and can be found on the COSIC website (www.esat.kuleuven.be/cosic/publications)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity DiffusionLayer is
generic( SHIFT1 : integer range 0 to 63;
SHIFT2 : integer range 0 to 63);
port( Input : in std_logic_vector(63 downto 0);
Output : out std_logic_vector(63 downto 0));
end entity DiffusionLayer;
architecture structural of DiffusionLayer is
begin
DiffLayer: process(Input) is
variable Temp0,Temp1 : std_logic_vector(63 downto 0);
begin
Temp0(63 downto 64-SHIFT1) := Input(SHIFT1-1 downto 0);
Temp0(63-SHIFT1 downto 0) := Input(63 downto SHIFT1);
Temp1(63 downto 64-SHIFT2) := Input(SHIFT2-1 downto 0);
Temp1(63-SHIFT2 downto 0) := Input(63 downto SHIFT2);
Output <= Temp0 xor Temp1 xor Input;
end process DiffLayer;
end architecture structural;
| gpl-3.0 | 72d0dc28f00edd66c7f7a54e5f51f65f | 0.616479 | 3.740576 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/leon3/leon3s.vhd | 1 | 7,927 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: leon3s
-- File: leon3s.vhd
-- Author: Jiri Gaisler, Edvin Catovic, Gaisler Research
-- Description: Top-level LEON3 component
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
library techmap;
use techmap.gencomp.all;
use gaisler.leon3.all;
use gaisler.libiu.all;
use gaisler.libcache.all;
use gaisler.libproc3.all;
use gaisler.arith.all;
--library fpu;
--use fpu.libfpu.all;
entity leon3s is
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 31 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 2 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 2 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0; -- support SMP systems
cached : integer := 0; -- cacheability table
scantest : integer := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
hackVector : out std_logic_vector(7 downto 0)
);
end;
architecture rtl of leon3s is
constant IRFBITS : integer range 6 to 10 := log2(NWINDOWS+1) + 4;
constant IREGNUM : integer := NWINDOWS * 16 + 8;
signal holdn : std_logic;
signal rfi : iregfile_in_type;
signal rfo : iregfile_out_type;
signal crami : cram_in_type;
signal cramo : cram_out_type;
signal tbi : tracebuf_in_type;
signal tbo : tracebuf_out_type;
signal rst : std_ulogic;
signal fpi : fpc_in_type;
signal fpo : fpc_out_type;
signal cpi : fpc_in_type;
signal cpo : fpc_out_type;
signal cpodb : fpc_debug_out_type;
signal rd1, rd2, wd : std_logic_vector(35 downto 0);
signal gnd, vcc : std_logic;
constant FPURFHARD : integer := 1; --1-is_fpga(memtech);
constant fpuarch : integer := fpu mod 16;
constant fpunet : integer := fpu / 16;
attribute sync_set_reset : string;
attribute sync_set_reset of rst : signal is "true";
begin
gnd <= '0'; vcc <= '1';
-- leon3 processor core (iu, caches & mul/div)
p0 : proc3
generic map (hindex, fabtech, memtech, nwindows, dsu, fpuarch, v8, cp, mac,
pclow, notag, nwp, icen, irepl, isets, ilinesize, isetsize, isetlock,
dcen, drepl, dsets, dlinesize, dsetsize, dsetlock, dsnoop, ilram,
ilramsize, ilramstart, dlram, dlramsize, dlramstart, mmuen, itlbnum, dtlbnum,
tlb_type, tlb_rep, lddel, disas, tbuf, pwd, svt, rstaddr, smp, cached, 0, scantest)
port map (clk, rst, holdn, ahbi, ahbo, ahbsi, ahbso, rfi, rfo, crami, cramo,
tbi, tbo, fpi, fpo, cpi, cpo, irqi, irqo, dbgi, dbgo, gnd, clk, vcc, hackVector);
-- IU register file
rf0 : regfile_3p generic map (memtech, IRFBITS, 32, 1, IREGNUM)
port map (clk, rfi.waddr(IRFBITS-1 downto 0), rfi.wdata, rfi.wren,
clk, rfi.raddr1(IRFBITS-1 downto 0), rfi.ren1, rfo.data1,
rfi.raddr2(IRFBITS-1 downto 0), rfi.ren2, rfo.data2, rfi.diag);
-- cache memory
cmem0 : cachemem
generic map (memtech, icen, irepl, isets, ilinesize, isetsize, isetlock, dcen,
drepl, dsets, dlinesize, dsetsize, dsetlock, dsnoop, ilram,
ilramsize, dlram, dlramsize, mmuen)
port map (clk, crami, cramo, clk);
-- instruction trace buffer memory
tbmem_gen : if (tbuf /= 0) generate
tbmem0 : tbufmem
generic map (tech => memtech, tbuf => tbuf)
port map (clk, tbi, tbo);
end generate;
-- FPU
fpu0 : if (fpu = 0) generate fpo.ldlock <= '0'; fpo.ccv <= '1'; fpo.holdn <= '1'; end generate;
grfpw0gen : if (fpuarch > 0) and (fpuarch < 8) generate
fpu0: grfpwx
generic map (fabtech, FPURFHARD*memtech, (fpuarch-1), pclow, dsu, disas, fpunet, 0)
port map (rst, clk, holdn, fpi, fpo);
end generate;
mfpw0gen : if (fpuarch = 15) generate
fpu0 : mfpwx
generic map (FPURFHARD*memtech, pclow, dsu, disas)
port map (rst, clk, holdn, fpi, fpo);
end generate;
grlfpc0gen : if (fpuarch >= 8) and (fpuarch < 15) generate
fpu0 : grlfpwx
generic map (FPURFHARD*memtech, pclow, dsu, disas, (fpuarch-8), fpunet)
port map (rst, clk, holdn, fpi, fpo);
end generate;
-- Default Co-Proc drivers
cpodb.data <= zero32;
cpo <= (zero32, '0', "00", '0', '0', '0', cpodb);
-- 1-clock reset delay
rstreg : process(clk)
begin if rising_edge(clk) then rst <= rstn; end if; end process;
-- pragma translate_off
bootmsg : report_version
generic map (
"leon3_" & tost(hindex) & ": LEON3 SPARC V8 processor rev " & tost(LEON3_VERSION),
"leon3_" & tost(hindex) & ": icache " & tost(isets*icen) & "*" & tost(isetsize*icen) &
" kbyte, dcache " & tost(dsets*dcen) & "*" & tost(dsetsize*dcen) & " kbyte"
);
-- pragma translate_on
end;
| mit | 220fc4c94b27bf283ba91ce1b1184751 | 0.584458 | 3.434575 | false | false | false | false |
lxp32/lxp32-cpu | verify/lxp32/src/platform/dbus_monitor.vhd | 2 | 2,697 | ---------------------------------------------------------------------
-- DBUS monitor
--
-- Part of the LXP32 test platform
--
-- Copyright (c) 2016 by Alex I. Kuznetsov
--
-- Monitors LXP32 data bus transactions, optionally throttles them.
--
-- Note: regardless of whether this description is synthesizable,
-- it was designed exclusively for simulation purposes.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity dbus_monitor is
generic(
THROTTLE: boolean
);
port(
clk_i: in std_logic;
rst_i: in std_logic;
wbs_cyc_i: in std_logic;
wbs_stb_i: in std_logic;
wbs_we_i: in std_logic;
wbs_sel_i: in std_logic_vector(3 downto 0);
wbs_ack_o: out std_logic;
wbs_adr_i: in std_logic_vector(31 downto 2);
wbs_dat_i: in std_logic_vector(31 downto 0);
wbs_dat_o: out std_logic_vector(31 downto 0);
wbm_cyc_o: out std_logic;
wbm_stb_o: out std_logic;
wbm_we_o: out std_logic;
wbm_sel_o: out std_logic_vector(3 downto 0);
wbm_ack_i: in std_logic;
wbm_adr_o: out std_logic_vector(31 downto 2);
wbm_dat_o: out std_logic_vector(31 downto 0);
wbm_dat_i: in std_logic_vector(31 downto 0)
);
end entity;
architecture rtl of dbus_monitor is
signal prbs: std_logic;
signal cycle: std_logic:='0';
signal cyc_ff: std_logic:='0';
signal ack_ff: std_logic:='0';
begin
-- Manage throttling
gen_throttling: if THROTTLE generate
throttle_inst: entity work.scrambler(rtl)
generic map(TAP1=>6,TAP2=>7)
port map(clk_i=>clk_i,rst_i=>rst_i,ce_i=>'1',d_o=>prbs);
end generate;
gen_no_throttling: if not THROTTLE generate
prbs<='0';
end generate;
-- CPU interface
wbs_ack_o<=wbm_ack_i;
wbs_dat_o<=wbm_dat_i when wbm_ack_i='1' else (others=>'-');
-- Interconnect interface
process (clk_i) is
begin
if rising_edge(clk_i) then
if rst_i='1' then
cycle<='0';
elsif prbs='0' and wbs_cyc_i='1' then
cycle<='1';
elsif wbs_cyc_i='0' then
cycle<='0';
end if;
end if;
end process;
wbm_cyc_o<=wbs_cyc_i and (not prbs or cycle);
wbm_stb_o<=wbs_stb_i and (not prbs or cycle);
wbm_we_o<=wbs_we_i;
wbm_sel_o<=wbs_sel_i;
wbm_adr_o<=wbs_adr_i;
wbm_dat_o<=wbs_dat_i;
-- Check handshake correctness
process (clk_i) is
begin
if rising_edge(clk_i) then
if rst_i='1' then
cyc_ff<='0';
ack_ff<='0';
else
cyc_ff<=wbs_cyc_i;
ack_ff<=wbm_ack_i;
assert wbm_ack_i='0' or (wbs_cyc_i and (not prbs or cycle))='1'
report "DBUS error: ACK asserted without CYC"
severity failure;
assert not (wbs_cyc_i='0' and cyc_ff='1' and ack_ff/='1')
report "DBUS error: cycle terminated prematurely"
severity failure;
end if;
end if;
end process;
end architecture;
| mit | ee40f8bd39cda8d92157ff55458fdd33 | 0.630701 | 2.721493 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/techmap/maps/toutpad.vhd | 2 | 5,195 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: toutpad
-- File: toutpad.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: tri-state output pad with technology wrapper
------------------------------------------------------------------------------
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allpads.all;
entity toutpad is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12;
oepol : integer := 0);
port (pad : out std_ulogic; i, en : in std_ulogic);
end;
architecture rtl of toutpad is
signal oen : std_ulogic;
signal padx, gnd : std_ulogic;
begin
gnd <= '0';
oen <= not en when oepol /= padoen_polarity(tech) else en;
gen0 : if has_pads(tech) = 0 generate
pad <= i after 2 ns when oen = '0'
-- pragma translate_off
else 'X' after 2 ns when is_x(en)
-- pragma translate_on
else 'Z' after 2 ns;
end generate;
xcv : if (tech = virtex) or (tech = virtex2) or (tech = spartan3) or
(tech = virtex4) or (tech = spartan3e) or (tech = virtex5)
generate
u0 : virtex_toutpad generic map (level, slew, voltage, strength)
port map (pad, i, oen);
end generate;
axc : if (tech = axcel) or (tech = proasic) or (tech = apa3) generate
u0 : axcel_toutpad generic map (level, slew, voltage, strength)
port map (pad, i, oen);
end generate;
atc : if (tech = atc18s) generate
u0 : atc18_toutpad generic map (level, slew, voltage, strength)
port map (pad, i, oen);
end generate;
atcrh : if (tech = atc18rha) generate
u0 : atc18rha_toutpad generic map (level, slew, voltage, strength)
port map (pad, i, oen);
end generate;
um : if (tech = umc) generate
u0 : umc_toutpad generic map (level, slew, voltage, strength)
port map (pad, i, oen);
end generate;
rhu : if (tech = rhumc) generate
u0 : rhumc_toutpad generic map (level, slew, voltage, strength)
port map (pad, i, oen);
end generate;
ihp : if (tech = ihp25) generate
u0 : ihp25_toutpad generic map (level, slew, voltage, strength)
port map(pad, i, oen);
end generate;
ihprh : if (tech = ihp25rh) generate
u0 : ihp25rh_toutpad generic map (level, slew, voltage, strength)
port map(pad, i, oen);
end generate;
rh18t : if (tech = rhlib18t) generate
u0 : rh_lib18t_iopad generic map (strength) port map (padx, i, oen, open);
pad <= padx;
end generate;
ut025 : if (tech = ut25) generate
u0 : ut025crh_toutpad generic map (level, slew, voltage, strength)
port map(pad, i, oen);
end generate;
pere : if (tech = peregrine) generate
u0 : peregrine_toutpad generic map (level, slew, voltage, strength)
port map(pad, i, oen);
end generate;
nex : if (tech = easic90) generate
u0 : nextreme_toutpad generic map (level, slew, voltage, strength)
port map (pad, i, oen);
end generate;
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity toutpadv is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (
pad : out std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_ulogic);
end;
architecture rtl of toutpadv is
begin
v : for j in width-1 downto 0 generate
u0 : toutpad generic map (tech, level, slew, voltage, strength, oepol)
port map (pad(j), i(j), en);
end generate;
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity toutpadvv is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (
pad : out std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_logic_vector(width-1 downto 0));
end;
architecture rtl of toutpadvv is
begin
v : for j in width-1 downto 0 generate
u0 : toutpad generic map (tech, level, slew, voltage, strength, oepol)
port map (pad(j), i(j), en(j));
end generate;
end;
| mit | da37996842cf7d0bc6be36d9c7847976 | 0.634649 | 3.534014 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/techmap/cycloneiii/cycloneiii_clkgen.vhd | 2 | 7,054 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library altera_mf;
use altera_mf.altpll;
-- pragma translate_on
entity cyclone3_pll is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
clk_freq : integer := 25000;
clk2xen : integer := 0;
sdramen : integer := 0
);
port (
inclk0 : in std_ulogic;
c0 : out std_ulogic;
c0_2x : out std_ulogic;
e0 : out std_ulogic;
locked : out std_ulogic
);
end;
architecture rtl of cyclone3_pll is
component altpll
generic (
intended_device_family : string := "CycloneIII" ;
operation_mode : string := "NORMAL" ;
compensate_clock : string := "clock0";
inclk0_input_frequency : positive;
width_clock : positive := 6;
clk0_multiply_by : positive := 1;
clk0_divide_by : positive := 1;
clk1_multiply_by : positive := 1;
clk1_divide_by : positive := 1;
clk2_multiply_by : positive := 1;
clk2_divide_by : positive := 1
);
port (
inclk : in std_logic_vector(1 downto 0);
clkena : in std_logic_vector(5 downto 0);
clk : out std_logic_vector(width_clock-1 downto 0);
locked : out std_logic
);
end component;
signal clkena : std_logic_vector (5 downto 0);
signal clkout : std_logic_vector (4 downto 0);
signal inclk : std_logic_vector (1 downto 0);
constant clk_period : integer := 1000000000/clk_freq;
constant CLK_MUL2X : integer := clk_mul * 2;
begin
clkena(5 downto 3) <= (others => '0');
clkena(0) <= '1';
clkena(1) <= '1' when sdramen = 1 else '0';
clkena(2) <= '1' when clk2xen = 1 else '0';
inclk <= '0' & inclk0;
c0 <= clkout(0); c0_2x <= clkout(2); e0 <= clkout(1);
sden : if sdramen = 1 generate
altpll0 : altpll
generic map (
intended_device_family => "Cyclone III",
operation_mode => "ZERO_DELAY_BUFFER", inclk0_input_frequency => clk_period,
width_clock => 5, compensate_clock => "CLK1",
clk0_multiply_by => clk_mul, clk0_divide_by => clk_div,
clk1_multiply_by => clk_mul, clk1_divide_by => clk_div,
clk2_multiply_by => CLK_MUL2X, clk2_divide_by => clk_div)
port map ( clkena => clkena, inclk => inclk,
clk => clkout, locked => locked);
end generate;
nosd : if sdramen = 0 generate
altpll0 : altpll
generic map (
intended_device_family => "Cyclone III",
operation_mode => "NORMAL", inclk0_input_frequency => clk_period,
width_clock => 5,
clk0_multiply_by => clk_mul, clk0_divide_by => clk_div,
clk1_multiply_by => clk_mul, clk1_divide_by => clk_div,
clk2_multiply_by => CLK_MUL2X, clk2_divide_by => clk_div)
port map ( clkena => clkena, inclk => inclk,
clk => clkout, locked => locked);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library altera_mf;
library grlib;
use grlib.stdlib.all;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity clkgen_cycloneiii is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
sdinvclk : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000;
clk2xen : integer := 0;
tech : integer := 0);
port (
clkin : in std_logic;
pciclkin: in std_logic;
clk : out std_logic; -- main clock
clkn : out std_logic; -- inverted main clock
clk2x : out std_logic; -- double clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type);
end;
architecture rtl of clkgen_cycloneiii is
constant VERSION : integer := 1;
constant CLKIN_PERIOD : integer := 20;
signal clk_i : std_logic;
signal clkint, pciclkint : std_logic;
signal pllclk, pllclkn : std_logic; -- generated clocks
signal s_clk : std_logic;
component cyclone3_pll
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
clk_freq : integer := 25000;
clk2xen : integer := 0;
sdramen : integer := 0
);
port (
inclk0 : in std_ulogic;
c0 : out std_ulogic;
c0_2x : out std_ulogic;
e0 : out std_ulogic;
locked : out std_ulogic);
end component;
begin
cgo.pcilock <= '1';
-- c0 : if (PCISYSCLK = 0) generate
-- Clkint <= Clkin;
-- end generate;
-- c1 : if (PCISYSCLK = 1) generate
-- Clkint <= pciclkin;
-- end generate;
-- c2 : if (PCIEN = 1) generate
-- p0 : if (PCIDLL = 1) generate
-- pciclkint <= pciclkin;
-- pciclk <= pciclkint;
-- end generate;
-- p1 : if (PCIDLL = 0) generate
-- u0 : if (PCISYSCLK = 0) generate
-- pciclkint <= pciclkin;
-- end generate;
-- pciclk <= clk_i when (PCISYSCLK = 1) else pciclkint;
-- end generate;
-- end generate;
-- c3 : if (PCIEN = 0) generate
-- pciclk <= Clkint;
-- end generate;
c0: if (PCISYSCLK = 0) or (PCIEN = 0) generate
clkint <= clkin;
end generate c0;
c1: if PCIEN /= 0 generate
d0: if PCISYSCLK = 1 generate
clkint <= pciclkin;
end generate d0;
pciclk <= pciclkin;
end generate c1;
c2: if PCIEN = 0 generate
pciclk <= '0';
end generate c2;
sdclk_pll : cyclone3_pll
generic map (clk_mul, clk_div, freq, clk2xen, sdramen)
port map ( inclk0 => clkint, e0 => sdclk, c0 => s_clk, c0_2x => clk2x,
locked => cgo.clklock);
clk <= s_clk;
clkn <= not s_clk;
-- pragma translate_off
bootmsg : report_version
generic map (
"clkgen_cycloneiii" & ": altpll sdram/pci clock generator, version " & tost(VERSION),
"clkgen_cycloneiii" & ": Frequency " & tost(freq) & " KHz, PLL scaler " & tost(clk_mul) & "/" & tost(clk_div));
-- pragma translate_on
end;
| mit | 2f336239a5b80a811b05901d3b8d3ace | 0.584349 | 3.488625 | false | false | false | false |
michaelfivez/ascon_hardware_implementation | ascon12864_unrolled6/Kernel/Sbox.vhd | 1 | 3,932 | -------------------------------------------------------------------------------
--! @project Unrolled (6) hardware implementation of Asconv1286
--! @author Michael Fivez
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is an hardware implementation made for my graduation thesis
--! at the KULeuven, in the COSIC department (year 2015-2016)
--! The thesis is titled 'Energy efficient hardware implementations of CAESAR submissions',
--! and can be found on the COSIC website (www.esat.kuleuven.be/cosic/publications)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Sbox is
port(
X0In : in std_logic_vector(63 downto 0);
X1In : in std_logic_vector(63 downto 0);
X2In : in std_logic_vector(63 downto 0);
X3In : in std_logic_vector(63 downto 0);
X4In : in std_logic_vector(63 downto 0);
RoundNr : in std_logic_vector(3 downto 0);
X0Out : out std_logic_vector(63 downto 0);
X1Out : out std_logic_vector(63 downto 0);
X2Out : out std_logic_vector(63 downto 0);
X3Out : out std_logic_vector(63 downto 0);
X4Out : out std_logic_vector(63 downto 0));
end entity Sbox;
architecture structural of Sbox is
begin
Sbox: process(X0In,X1In,X2In,X3In,X4In,RoundNr) is
-- Procedure for 5-bit Sbox
procedure doSboxPart (
variable SboxPartIn : in std_logic_vector(4 downto 0);
variable SboxPartOut : out std_logic_vector(4 downto 0)) is
-- Temp variable
variable SboxPartTemp : std_logic_vector(17 downto 0);
begin
-- Sbox Interconnections
SboxPartTemp(0) := SboxPartIn(0) xor SboxPartIn(4);
SboxPartTemp(1) := SboxPartIn(2) xor SboxPartIn(1);
SboxPartTemp(2) := SboxPartIn(4) xor SboxPartIn(3);
SboxPartTemp(3) := not SboxPartTemp(0);
SboxPartTemp(4) := not SboxPartIn(1);
SboxPartTemp(5) := not SboxPartTemp(1);
SboxPartTemp(6) := not SboxPartIn(3);
SboxPartTemp(7) := not SboxPartTemp(2);
SboxPartTemp(8) := SboxPartIn(1) and SboxPartTemp(3);
SboxPartTemp(9) := SboxPartTemp(1) and SboxPartTemp(4);
SboxPartTemp(10) := SboxPartIn(3) and SboxPartTemp(5);
SboxPartTemp(11) := SboxPartTemp(2) and SboxPartTemp(6);
SboxPartTemp(12) := SboxPartTemp(0) and SboxPartTemp(7);
SboxPartTemp(13) := SboxPartTemp(0) xor SboxPartTemp(9);
SboxPartTemp(14) := SboxPartIn(1) xor SboxPartTemp(10);
SboxPartTemp(15) := SboxPartTemp(1) xor SboxPartTemp(11);
SboxPartTemp(16) := SboxPartIn(3) xor SboxPartTemp(12);
SboxPartTemp(17) := SboxPartTemp(2) xor SboxPartTemp(8);
SboxPartOut(0) := SboxPartTemp(13) xor SboxPartTemp(17);
SboxPartOut(1) := SboxPartTemp(13) xor SboxPartTemp(14);
SboxPartOut(2) := not SboxPartTemp(15);
SboxPartOut(3) := SboxPartTemp(15) xor SboxPartTemp(16);
SboxPartOut(4) := SboxPartTemp(17);
end procedure doSboxPart;
variable X2TempIn : std_logic_vector(63 downto 0);
variable TempIn,TempOut : std_logic_vector(4 downto 0);
begin
-- Xor with round constants
X2TempIn(3 downto 0) := X2In(3 downto 0) xor RoundNr;
X2TempIn(7 downto 4) := X2In(7 downto 4) xnor RoundNr;
X2TempIn(63 downto 8) := X2In(63 downto 8);
-- Apply 5-bit Sbox 64 times
for i in X0In'range loop
TempIn(0) := X0In(i);
TempIn(1) := X1In(i);
TempIn(2) := X2TempIn(i);
TempIn(3) := X3In(i);
TempIn(4) := X4In(i);
doSboxPart(TempIn,TempOut);
X0Out(i) <= TempOut(0);
X1Out(i) <= TempOut(1);
X2Out(i) <= TempOut(2);
X3Out(i) <= TempOut(3);
X4Out(i) <= TempOut(4);
end loop;
end process Sbox;
end architecture structural;
| gpl-3.0 | 0058ab608b65321299292058afdb31fb | 0.639878 | 2.921248 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/spacewire/grspw2.vhd | 2 | 11,651 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: grspw2
-- File: grspw2.vhd
-- Author: Marko Isomaki - Gaisler Research
-- Description: GRLIB wrapper for grspw core
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library techmap;
use techmap.gencomp.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.spacewire.all;
library spw;
use spw.spwcomp.all;
entity grspw2 is
generic(
tech : integer range 0 to NTECH := inferred;
hindex : integer range 0 to NAHBMST-1 := 0;
pindex : integer range 0 to NAPBSLV-1 := 0;
paddr : integer range 0 to 16#FFF# := 0;
pmask : integer range 0 to 16#FFF# := 16#FFF#;
pirq : integer range 0 to NAHBIRQ-1 := 0;
nsync : integer range 1 to 2 := 1;
rmap : integer range 0 to 1 := 0;
rmapcrc : integer range 0 to 1 := 0;
fifosize1 : integer range 4 to 32 := 32;
fifosize2 : integer range 16 to 64 := 64;
rxclkbuftype : integer range 0 to 2 := 0;
rxunaligned : integer range 0 to 1 := 0;
rmapbufs : integer range 2 to 8 := 4;
ft : integer range 0 to 2 := 0;
scantest : integer range 0 to 1 := 0;
techfifo : integer range 0 to 1 := 1;
ports : integer range 1 to 2 := 1;
dmachan : integer range 1 to 4 := 1;
memtech : integer range 0 to NTECH := DEFMEMTECH
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
txclk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
swni : in grspw_in_type;
swno : out grspw_out_type
);
end entity;
architecture rtl of grspw2 is
constant fabits1 : integer := log2(fifosize1);
constant fabits2 : integer := log2(fifosize2);
constant rfifo : integer := 5 + log2(rmapbufs);
constant REVISION : integer := 0;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_SPW2, 0, REVISION, pirq),
1 => apb_iobar(paddr, pmask));
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_SPW2, 0, REVISION, pirq),
others => zero32);
signal rxclki, nrxclki, rxclko : std_logic_vector(1 downto 0);
--rx ahb fifo
signal rxrenable : std_ulogic;
signal rxraddress : std_logic_vector(4 downto 0);
signal rxwrite : std_ulogic;
signal rxwdata : std_logic_vector(31 downto 0);
signal rxwaddress : std_logic_vector(4 downto 0);
signal rxrdata : std_logic_vector(31 downto 0);
--tx ahb fifo
signal txrenable : std_ulogic;
signal txraddress : std_logic_vector(4 downto 0);
signal txwrite : std_ulogic;
signal txwdata : std_logic_vector(31 downto 0);
signal txwaddress : std_logic_vector(4 downto 0);
signal txrdata : std_logic_vector(31 downto 0);
--nchar fifo
signal ncrenable : std_ulogic;
signal ncraddress : std_logic_vector(5 downto 0);
signal ncwrite : std_ulogic;
signal ncwdata : std_logic_vector(8 downto 0);
signal ncwaddress : std_logic_vector(5 downto 0);
signal ncrdata : std_logic_vector(8 downto 0);
--rmap buf
signal rmrenable : std_ulogic;
signal rmraddress : std_logic_vector(7 downto 0);
signal rmwrite : std_ulogic;
signal rmwdata : std_logic_vector(7 downto 0);
signal rmwaddress : std_logic_vector(7 downto 0);
signal rmrdata : std_logic_vector(7 downto 0);
--misc
signal irq : std_ulogic;
signal rxclk, nrxclk : std_logic_vector(ports-1 downto 0);
begin
grspwc0 : grspwc2
generic map(
nsync => nsync,
rmap => rmap,
rmapcrc => rmapcrc,
fifosize1 => fifosize1,
fifosize2 => fifosize2,
rxunaligned => rxunaligned,
rmapbufs => rmapbufs,
scantest => scantest,
ports => ports,
dmachan => dmachan,
tech => tech)
port map(
rst => rst,
clk => clk,
txclk => txclk,
--ahb mst in
hgrant => ahbmi.hgrant(hindex),
hready => ahbmi.hready,
hresp => ahbmi.hresp,
hrdata => ahbmi.hrdata,
--ahb mst out
hbusreq => ahbmo.hbusreq,
hlock => ahbmo.hlock,
htrans => ahbmo.htrans,
haddr => ahbmo.haddr,
hwrite => ahbmo.hwrite,
hsize => ahbmo.hsize,
hburst => ahbmo.hburst,
hprot => ahbmo.hprot,
hwdata => ahbmo.hwdata,
--apb slv in
psel => apbi.psel(pindex),
penable => apbi.penable,
paddr => apbi.paddr,
pwrite => apbi.pwrite,
pwdata => apbi.pwdata,
--apb slv out
prdata => apbo.prdata,
--spw in
di => swni.d,
si => swni.s,
--spw out
do => swno.d,
so => swno.s,
--time iface
tickin => swni.tickin,
tickout => swno.tickout,
--clk bufs
rxclki => rxclki,
nrxclki => nrxclki,
rxclko => rxclko,
--irq
irq => irq,
--misc
clkdiv10 => swni.clkdiv10,
dcrstval => swni.dcrstval,
timerrstval => swni.timerrstval,
--rmapen
rmapen => swni.rmapen,
--rx ahb fifo
rxrenable => rxrenable,
rxraddress => rxraddress,
rxwrite => rxwrite,
rxwdata => rxwdata,
rxwaddress => rxwaddress,
rxrdata => rxrdata,
--tx ahb fifo
txrenable => txrenable,
txraddress => txraddress,
txwrite => txwrite,
txwdata => txwdata,
txwaddress => txwaddress,
txrdata => txrdata,
--nchar fifo
ncrenable => ncrenable,
ncraddress => ncraddress,
ncwrite => ncwrite,
ncwdata => ncwdata,
ncwaddress => ncwaddress,
ncrdata => ncrdata,
--rmap buf
rmrenable => rmrenable,
rmraddress => rmraddress,
rmwrite => rmwrite,
rmwdata => rmwdata,
rmwaddress => rmwaddress,
rmrdata => rmrdata,
linkdis => swno.linkdis,
testclk => clk,
testrst => ahbmi.testrst,
testen => ahbmi.testen
);
irqdrv : process(irq)
begin
apbo.pirq <= (others => '0');
apbo.pirq(pirq) <= irq;
end process;
ahbmo.hirq <= (others => '0');
ahbmo.hconfig <= hconfig;
ahbmo.hindex <= hindex;
apbo.pconfig <= pconfig;
apbo.pindex <= pindex;
ntst: if scantest = 0 generate
cbufloop : for i in 0 to ports-1 generate
rx_clkbuf : techbuf generic map(tech => tech, buftype => rxclkbuftype)
port map(i => rxclko(i), o => rxclki(i));
end generate;
end generate;
tst: if scantest = 1 generate
cloop : for i in 0 to ports-1 generate
rxclk(i) <= clk when ahbmi.testen = '1' else rxclko(i);
nrxclk(i) <= clk when ahbmi.testen = '1' else not rxclko(i);
rx_clkbuf : techbuf generic map(tech => tech, buftype => rxclkbuftype)
port map(i => rxclk(i), o => rxclki(i));
nrx_clkbuf : techbuf generic map(tech => tech, buftype => rxclkbuftype)
port map(i => nrxclk(i), o => nrxclki(i));
end generate;
end generate;
------------------------------------------------------------------------------
-- FIFOS ---------------------------------------------------------------------
------------------------------------------------------------------------------
nft : if ft = 0 generate
--receiver AHB FIFO
rx_ram0 : syncram_2p generic map(memtech*techfifo, fabits1, 32)
port map(clk, rxrenable, rxraddress(fabits1-1 downto 0),
rxrdata, clk, rxwrite,
rxwaddress(fabits1-1 downto 0), rxwdata);
--receiver nchar FIFO
rx_ram1 : syncram_2p generic map(memtech*techfifo, fabits2, 9)
port map(clk, ncrenable, ncraddress(fabits2-1 downto 0),
ncrdata, clk, ncwrite,
ncwaddress(fabits2-1 downto 0), ncwdata);
--transmitter FIFO
tx_ram0 : syncram_2p generic map(memtech*techfifo, fabits1, 32)
port map(clk, txrenable, txraddress(fabits1-1 downto 0),
txrdata, clk, txwrite, txwaddress(fabits1-1 downto 0), txwdata);
--RMAP Buffer
rmap_ram : if (rmap = 1) generate
ram0 : syncram_2p generic map(memtech, rfifo, 8)
port map(clk, rmrenable, rmraddress(rfifo-1 downto 0),
rmrdata, clk, rmwrite, rmwaddress(rfifo-1 downto 0),
rmwdata);
end generate;
end generate;
ft1 : if ft /= 0 generate
--receiver AHB FIFO
rx_ram0 : syncram_2pft generic map(memtech*techfifo, fabits1, 32, 0, 0, ft*techfifo)
port map(clk, rxrenable, rxraddress(fabits1-1 downto 0),
rxrdata, clk, rxwrite,
rxwaddress(fabits1-1 downto 0), rxwdata);
--receiver nchar FIFO
rx_ram1 : syncram_2pft generic map(memtech*techfifo, fabits2, 9, 0, 0, 2*techfifo)
port map(clk, ncrenable, ncraddress(fabits2-1 downto 0),
ncrdata, clk, ncwrite,
ncwaddress(fabits2-1 downto 0), ncwdata);
--transmitter FIFO
tx_ram0 : syncram_2pft generic map(memtech*techfifo, fabits1, 32, 0, 0, ft*techfifo)
port map(clk, txrenable, txraddress(fabits1-1 downto 0),
txrdata, clk, txwrite, txwaddress(fabits1-1 downto 0), txwdata);
--RMAP Buffer
rmap_ram : if (rmap = 1) generate
ram0 : syncram_2pft generic map(memtech, rfifo, 8, 0, 0, 2)
port map(clk, rmrenable, rmraddress(rfifo-1 downto 0),
rmrdata, clk, rmwrite, rmwaddress(rfifo-1 downto 0),
rmwdata);
end generate;
end generate;
-- pragma translate_off
msg0 : if (rmap = 0) generate
bootmsg : report_version
generic map ("grspw" & tost(pindex) &
": Spacewire link rev " & tost(REVISION) & ", AHB fifos 2x" &
tost(fifosize1*4) & " bytes, rx fifo " & tost(fifosize2) &
" bytes, irq " & tost(pirq));
end generate;
msg1 : if (rmap = 1) generate
bootmsg : report_version
generic map ("grspw" & tost(pindex) &
": Spacewire link rev " & tost(REVISION) & ", AHB fifos 2x " &
tost(fifosize1*4) & " bytes, rx fifo " & tost(fifosize2) &
" bytes, irq " & tost(pirq) & " , RMAP Buffer " &
tost(rmapbufs*32) & " bytes");
end generate;
-- pragma translate_on
end architecture;
| mit | d32804dd338d2622de9080b1fc168d69 | 0.562784 | 3.972383 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/leon3/libmmu.vhd | 2 | 7,944 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: leon3
-- File: leon3.vhd
-- Author: Konrad Eisele, Jiri Gaisler, Gaisler Research
-- Description: MMU component declaration
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.mmuconfig.all;
use gaisler.mmuiface.all;
package libmmu is
component mmu
generic (
tech : integer range 0 to NTECH := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0
);
port (
rst : in std_logic;
clk : in std_logic;
mmudci : in mmudc_in_type;
mmudco : out mmudc_out_type;
mmuici : in mmuic_in_type;
mmuico : out mmuic_out_type;
mcmmo : in memory_mm_out_type;
mcmmi : out memory_mm_in_type
);
end component;
function TLB_CreateCamWrite( two_data : std_logic_vector(31 downto 0);
read : std_logic;
lvl : std_logic_vector(1 downto 0);
ctx : std_logic_vector(M_CTX_SZ-1 downto 0);
vaddr : std_logic_vector(31 downto 0)
) return tlbcam_reg;
procedure TLB_CheckFault( ACC : in std_logic_vector(2 downto 0);
isid : in mmu_idcache;
su : in std_logic;
read : in std_logic;
fault_pro : out std_logic;
fault_pri : out std_logic );
procedure TLB_MergeData( LVL : in std_logic_vector(1 downto 0);
PTE : in std_logic_vector(31 downto 0);
data : in std_logic_vector(31 downto 0);
transdata : out std_logic_vector(31 downto 0));
function TLB_CreateCamTrans( vaddr : std_logic_vector(31 downto 0);
read : std_logic;
ctx : std_logic_vector(M_CTX_SZ-1 downto 0)
) return tlbcam_tfp;
function TLB_CreateCamFlush( data : std_logic_vector(31 downto 0);
ctx : std_logic_vector(M_CTX_SZ-1 downto 0)
) return tlbcam_tfp;
end;
package body libmmu is
procedure TLB_CheckFault( ACC : in std_logic_vector(2 downto 0);
isid : in mmu_idcache;
su : in std_logic;
read : in std_logic;
fault_pro : out std_logic;
fault_pri : out std_logic ) is
variable c_isd : std_logic;
begin
fault_pro := '0';
fault_pri := '0';
-- use '0' == icache '1' == dcache
if isid = id_icache then
c_isd := '0';
else
c_isd := '1';
end if;
--# fault, todo: should we flush on a fault?
case ACC is
when "000" => fault_pro := (not c_isd) or (not read);
when "001" => fault_pro := (not c_isd);
when "010" => fault_pro := (not read);
when "011" => null;
when "100" => fault_pro := (c_isd);
when "101" => fault_pro := (not c_isd) or ((not read) and (not su));
when "110" => fault_pri := (not su);
fault_pro := (not read);
when "111" => fault_pri := (not su);
when others => null;
end case;
end;
procedure TLB_MergeData( LVL : in std_logic_vector(1 downto 0);
PTE : in std_logic_vector(31 downto 0);
data : in std_logic_vector(31 downto 0);
transdata : out std_logic_vector(31 downto 0) ) is
begin
--# merge data
transdata := (others => '0');
case LVL is
when LVL_PAGE => transdata := PTE(PTE_PPN32PAG_U downto PTE_PPN32PAG_D) & data(VA_OFFPAG_U downto VA_OFFPAG_D);
when LVL_SEGMENT => transdata := PTE(PTE_PPN32SEG_U downto PTE_PPN32SEG_D) & data(VA_OFFSEG_U downto VA_OFFSEG_D);
when LVL_REGION => transdata := PTE(PTE_PPN32REG_U downto PTE_PPN32REG_D) & data(VA_OFFREG_U downto VA_OFFREG_D);
when LVL_CTX => transdata := data(VA_OFFCTX_U downto VA_OFFCTX_D);
when others => transdata := (others => 'X');
end case;
end;
function TLB_CreateCamWrite( two_data : std_logic_vector(31 downto 0);
read : std_logic;
lvl : std_logic_vector(1 downto 0);
ctx : std_logic_vector(M_CTX_SZ-1 downto 0);
vaddr : std_logic_vector(31 downto 0)
) return tlbcam_reg is
variable tlbcam_tagwrite : tlbcam_reg;
begin
tlbcam_tagwrite.ET := two_data(PT_ET_U downto PT_ET_D);
tlbcam_tagwrite.ACC := two_data(PTE_ACC_U downto PTE_ACC_D);
tlbcam_tagwrite.M := two_data(PTE_M) or (not read); -- tw : p-update modified
tlbcam_tagwrite.R := '1';
case tlbcam_tagwrite.ACC is -- tw : p-su ACC >= 6
when "110" | "111" => tlbcam_tagwrite.SU := '1';
when others => tlbcam_tagwrite.SU := '0';
end case;
tlbcam_tagwrite.VALID := '1';
tlbcam_tagwrite.LVL := lvl;
tlbcam_tagwrite.I1 := vaddr(VA_I1_U downto VA_I1_D);
tlbcam_tagwrite.I2 := vaddr(VA_I2_U downto VA_I2_D);
tlbcam_tagwrite.I3 := vaddr(VA_I3_U downto VA_I3_D);
tlbcam_tagwrite.CTX := ctx;
tlbcam_tagwrite.PPN := two_data(PTE_PPN_U downto PTE_PPN_D);
tlbcam_tagwrite.C := two_data(PTE_C);
return tlbcam_tagwrite;
end;
function TLB_CreateCamTrans( vaddr : std_logic_vector(31 downto 0);
read : std_logic;
ctx : std_logic_vector(M_CTX_SZ-1 downto 0)
) return tlbcam_tfp is
variable mtag : tlbcam_tfp;
begin
mtag.TYP := (others => '0');
mtag.I1 := vaddr(VA_I1_U downto VA_I1_D);
mtag.I2 := vaddr(VA_I2_U downto VA_I2_D);
mtag.I3 := vaddr(VA_I3_U downto VA_I3_D);
mtag.CTX := ctx;
mtag.M := not (read);
return mtag;
end;
function TLB_CreateCamFlush( data : std_logic_vector(31 downto 0);
ctx : std_logic_vector(M_CTX_SZ-1 downto 0)
) return tlbcam_tfp is
variable ftag : tlbcam_tfp;
begin
ftag.TYP := data(FPTY_U downto FPTY_D);
ftag.I1 := data(FPA_I1_U downto FPA_I1_D);
ftag.I2 := data(FPA_I2_U downto FPA_I2_D);
ftag.I3 := data(FPA_I3_U downto FPA_I3_D);
ftag.CTX := ctx;
ftag.M := '0';
return ftag;
end;
end;
| mit | e4eb0d5842143c22b4e39716eb6666c7 | 0.516113 | 3.720843 | false | false | false | false |
lxp32/lxp32-cpu | verify/lxp32/src/platform/scrambler.vhd | 2 | 1,187 | ---------------------------------------------------------------------
-- Scrambler
--
-- Part of the LXP32 test platform
--
-- Copyright (c) 2016 by Alex I. Kuznetsov
--
-- Generates a pseudo-random binary sequence using a Linear-Feedback
-- Shift Register (LFSR).
--
-- In order to generate a maximum-length sequence, 1+x^TAP1+x^TAP2
-- must be a primitive polynomial. Typical polynomials include:
-- (6,7), (9,11), (14,15).
--
-- Note: regardless of whether this description is synthesizable,
-- it was designed exclusively for simulation purposes.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity scrambler is
generic(
TAP1: integer;
TAP2: integer
);
port(
clk_i: in std_logic;
rst_i: in std_logic;
ce_i: in std_logic;
d_o: out std_logic
);
end entity;
architecture rtl of scrambler is
signal reg: std_logic_vector(TAP2 downto 1):=(others=>'1');
begin
process (clk_i) is
begin
if rising_edge(clk_i) then
if rst_i='1' then
reg<=(others=>'1');
elsif ce_i='1' then
reg<=reg(TAP2-1 downto 1)&(reg(TAP2) xor reg(TAP1));
end if;
end if;
end process;
d_o<=reg(1);
end architecture;
| mit | d8ed9aebbb402b479d0262c529d502cd | 0.601516 | 3.208108 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gleichmann/miscellaneous/Clk100MhzTo40Mhz.vhd | 2 | 10,803 | -- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: Clk100MhzTo40MHz.vhd
-- Megafunction Name(s):
-- altpll
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 4.1 Build 181 06/29/2004 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2004 Altera Corporation
--Any megafunction design, and related netlist (encrypted or decrypted),
--support information, device programming or simulation file, and any other
--associated documentation or information provided by Altera or a partner
--under Altera's Megafunction Partnership Program may be used only
--to program PLD devices (but not masked PLD devices) from Altera. Any
--other use of such megafunction design, netlist, support information,
--device programming or simulation file, or any other related documentation
--or information is prohibited for any other purpose, including, but not
--limited to modification, reverse engineering, de-compiling, or use with
--any other silicon devices, unless such use is explicitly licensed under
--a separate agreement with Altera or a megafunction partner. Title to the
--intellectual property, including patents, copyrights, trademarks, trade
--secrets, or maskworks, embodied in any such megafunction design, netlist,
--support information, device programming or simulation file, or any other
--related documentation or information provided by Altera or a megafunction
--partner, remains with Altera, the megafunction partner, or their respective
--licensors. No other licenses, including any licenses needed under any third
--party's intellectual property, are provided herein.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
-- pragma translate_off
library altera_mf;
use altera_mf.altpll;
-- pragma translate_on
ENTITY Clk100MhzTo40MHz IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
pllena : IN STD_LOGIC := '1';
areset : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END Clk100MhzTo40MHz;
ARCHITECTURE SYN OF clk100mhzto40mhz IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire5_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_duty_cycle : NATURAL;
lpm_type : STRING;
clk0_multiply_by : NATURAL;
invalid_lock_multiplier : NATURAL;
inclk0_input_frequency : NATURAL;
gate_lock_signal : STRING;
clk0_divide_by : NATURAL;
pll_type : STRING;
valid_lock_multiplier : NATURAL;
spread_frequency : NATURAL;
intended_device_family : STRING;
operation_mode : STRING;
compensate_clock : STRING;
clk0_phase_shift : STRING
);
PORT (
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
pllena : IN STD_LOGIC ;
locked : OUT STD_LOGIC ;
areset : IN STD_LOGIC ;
clk : OUT STD_LOGIC_VECTOR (5 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire5_bv(0 DOWNTO 0) <= "0";
sub_wire5 <= To_stdlogicvector(sub_wire5_bv);
sub_wire1 <= sub_wire0(0);
c0 <= sub_wire1;
locked <= sub_wire2;
sub_wire3 <= inclk0;
sub_wire4 <= sub_wire5(0 DOWNTO 0) & sub_wire3;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_duty_cycle => 50,
lpm_type => "altpll",
clk0_multiply_by => 2,
invalid_lock_multiplier => 5,
inclk0_input_frequency => 10000,
gate_lock_signal => "NO",
clk0_divide_by => 5,
pll_type => "AUTO",
valid_lock_multiplier => 1,
spread_frequency => 0,
intended_device_family => "Stratix II",
operation_mode => "NORMAL",
compensate_clock => "CLK0",
clk0_phase_shift => "0"
)
PORT MAP (
inclk => sub_wire4,
pllena => pllena,
areset => areset,
clk => sub_wire0,
locked => sub_wire2
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
-- Retrieval info: PRIVATE: TIME_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "5"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "200.000"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.000"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: DEV_FAMILY STRING "Stratix II"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
-- Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "10000"
-- Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "NO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "5"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1"
-- Retrieval info: CONSTANT: SPREAD_FREQUENCY NUMERIC "0"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix II"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT VCC "c0"
-- Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT VCC "@clk[5..0]"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: USED_PORT: pllena 0 0 0 0 INPUT VCC "pllena"
-- Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT VCC "@extclk[3..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: @pllena 0 0 0 0 pllena 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL Clk100MhzTo40MHz.vhd TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Clk100MhzTo40MHz.inc FALSE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Clk100MhzTo40MHz.cmp TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Clk100MhzTo40MHz.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Clk100MhzTo40MHz_inst.vhd FALSE FALSE
| mit | 8ece49e69caf0156e8702b07fab40e52 | 0.680367 | 3.374883 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/techmap/maps/syncram_dp.vhd | 2 | 5,126 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: syncram_dp
-- File: syncram_dp.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: syncronous dual-port ram with tech selection
------------------------------------------------------------------------------
library ieee;
library techmap;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use work.allmem.all;
entity syncram_dp is
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8 );
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic;
testin : in std_logic_vector(3 downto 0) := "0000");
end;
architecture rtl of syncram_dp is
begin
-- pragma translate_off
inf : if has_dpram(tech) = 0 generate
x : process
begin
assert false report "synram_dp: technology " & tech_table(tech) &
" not supported"
severity failure;
wait;
end process;
end generate;
-- pragma translate_on
xcv : if tech = virtex generate
x0 : virtex_syncram_dp generic map (abits, dbits)
port map (clk1, address1, datain1, dataout1, enable1, write1,
clk2, address2, datain2, dataout2, enable2, write2);
end generate;
xc2v : if (tech = virtex2) or (tech = spartan3) or (tech = virtex4)
or (tech = spartan3e) or (tech = virtex5)
generate
x0 : virtex2_syncram_dp generic map (abits, dbits)
port map (clk1, address1, datain1, dataout1, enable1, write1,
clk2, address2, datain2, dataout2, enable2, write2);
end generate;
vir : if tech = memvirage generate
x0 : virage_syncram_dp generic map (abits, dbits)
port map (clk1, address1, datain1, dataout1, enable1, write1,
clk2, address2, datain2, dataout2, enable2, write2);
end generate;
arti : if tech = memartisan generate
x0 : artisan_syncram_dp generic map (abits, dbits)
port map (clk1, address1, datain1, dataout1, enable1, write1,
clk2, address2, datain2, dataout2, enable2, write2);
end generate;
axc : if tech = axcel generate
x0 : axcel_syncram_2p generic map (abits, dbits)
port map (clk1, enable1, address1, dataout1, clk1, address1, datain1, write1);
x1 : axcel_syncram_2p generic map (abits, dbits)
port map (clk1, enable2, address2, dataout2, clk1, address1, datain1, write1);
end generate;
pa3 : if tech = apa3 generate
x0 : proasic3_syncram_dp generic map (abits, dbits)
port map (clk1, address1, datain1, dataout1, enable1, write1,
clk2, address2, datain2, dataout2, enable2, write2);
end generate;
alt : if (tech = altera) or (tech = stratix1) or (tech = stratix2) or
(tech = stratix3) or (tech = cyclone3) generate
x0 : altera_syncram_dp generic map (abits, dbits)
port map (clk1, address1, datain1, dataout1, enable1, write1,
clk2, address2, datain2, dataout2, enable2, write2);
end generate;
lat : if tech = lattice generate
x0 : ec_syncram_dp generic map (abits, dbits)
port map (clk1, address1, datain1, dataout1, enable1, write1,
clk2, address2, datain2, dataout2, enable2, write2);
end generate;
vir90 : if tech = memvirage90 generate
x0 : virage90_syncram_dp generic map (abits, dbits)
port map (clk1, address1, datain1, dataout1, enable1, write1,
clk2, address2, datain2, dataout2, enable2, write2);
end generate;
atrh : if tech = atc18rha generate
x0 : atc18rha_syncram_dp generic map (abits, dbits)
port map (clk1, address1, datain1, dataout1, enable1, write1,
clk2, address2, datain2, dataout2, enable2, write2, testin);
end generate;
end;
| mit | c5d83ada4e2940e83f8a75272fe3e8b5 | 0.62817 | 3.632884 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/memAttack/lib/gaisler/ddr/ddr_phy.vhd | 1 | 6,781 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ddr_phy
-- File: ddr_phy.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: DDR1 PHY for Altera, Virtex-2, Virtex-4, Spartan-3e
-- DDR2 PHY for Virtex-5
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
------------------------------------------------------------------
-- DDR1 PHY -------------------------------------------------------
------------------------------------------------------------------
entity ddr_phy is
generic(
tech : integer := virtex2;
MHz : integer := 100;
rstdelay : integer := 200;
dbits : integer := 16;
clk_mul : integer := 2;
clk_div : integer := 2;
rskew : integer :=0
);
port(
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
clkread : out std_ulogic; -- read clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
sdi : out sdctrl_in_type;
sdo : in sdctrl_out_type);
end;
architecture rtl of ddr_phy is
begin
ddr_phy0 : ddrphy
generic map (tech => tech, MHz => MHz, rstdelay => rstdelay
-- reduce 200 us start-up delay during simulation
-- pragma translate_off
/ 200
-- pragma translate_on
, dbits => dbits, clk_mul => clk_mul, clk_div => clk_div,
rskew => rskew)
port map (
rst, clk, clkout, clkread, lock,
ddr_clk, ddr_clkb, ddr_clk_fb_out, ddr_clk_fb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_ad, ddr_ba, ddr_dq,
sdo.address(15 downto 2), sdo.ba,
sdi.data(dbits*2-1 downto 0), sdo.data(dbits*2-1 downto 0),
sdo.dqm(dbits/4-1 downto 0), sdo.bdrive, sdo.bdrive, sdo.qdrive,
sdo.rasn, sdo.casn, sdo.sdwen, sdo.sdcsn, sdo.sdcke);
end;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
------------------------------------------------------------------
-- DDR2 PHY -------------------------------------------------------
------------------------------------------------------------------
entity ddr2_phy is
generic (tech : integer := virtex2; MHz : integer := 100;
rstdelay : integer := 200; dbits : integer := 16;
clk_mul : integer := 2 ; clk_div : integer := 2;
ddelayb0 : integer := 0; ddelayb1 : integer := 0; ddelayb2 : integer := 0;
ddelayb3 : integer := 0; ddelayb4 : integer := 0; ddelayb5 : integer := 0;
ddelayb6 : integer := 0; ddelayb7 : integer := 0;
numidelctrl : integer := 4; norefclk : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkref200 : in std_logic; -- input 200MHz clock
clkout : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqsn : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(1 downto 0);
sdi : out sdctrl_in_type;
sdo : in sdctrl_out_type);
end;
architecture rtl of ddr2_phy is
begin
ddr_phy0 : ddr2phy
generic map (tech => tech, MHz => MHz, rstdelay => rstdelay
-- reduce 200 us start-up delay during simulation
-- pragma translate_off
/ 200
-- pragma translate_on
, dbits => dbits, clk_mul => clk_mul, clk_div => clk_div,
ddelayb0 => ddelayb0, ddelayb1 => ddelayb1, ddelayb2 => ddelayb2,
ddelayb3 => ddelayb3, ddelayb4 => ddelayb4, ddelayb5 => ddelayb5,
ddelayb6 => ddelayb6, ddelayb7 => ddelayb7,
numidelctrl => numidelctrl, norefclk => norefclk)
port map (
rst, clk, clkref200, clkout,
lock,
ddr_clk, ddr_clkb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_dqsn, ddr_ad, ddr_ba, ddr_dq, ddr_odt,
sdo.address(15 downto 2), sdo.ba,
sdi.data(dbits*2-1 downto 0), sdo.data(dbits*2-1 downto 0),
sdo.dqm(dbits/4-1 downto 0), sdo.bdrive, sdo.bdrive, sdo.qdrive,
sdo.rasn, sdo.casn, sdo.sdwen, sdo.sdcsn, sdo.sdcke,
sdo.cal_en(dbits/8-1 downto 0), sdo.cal_inc(dbits/8-1 downto 0), sdo.cal_rst, sdo.odt);
end;
| mit | 05799b4d6c41810e760cc24e60fe387c | 0.570122 | 3.42821 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/misc/spictrl.vhd | 2 | 24,377 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: spictrl
-- File: spictrl.vhd
-- Author: Jan Andersson - Gaisler Research AB
-- [email protected]
--
-- Description: SPI controller with an interface compatible with MPC83xx SPI.
-- Relies on APB's wait state between back-to-back transfers.
--
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.misc.all;
entity spictrl is
generic (
-- APB generics
pindex : integer := 0; -- slave bus index
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0; -- interrupt index
-- SPI controller configuration
fdepth : integer range 1 to 7 := 1; -- FIFO depth is 2^fdepth
slvselen : integer range 0 to 1 := 0; -- Slave select register enable
slvselsz : integer range 1 to 32 := 1; -- Number of slave select signals
oepol : integer range 0 to 1 := 0); -- Output enable polarity
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- APB signals
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
-- SPI signals
spii : in spi_in_type;
spio : out spi_out_type;
slvsel : out std_logic_vector((slvselsz-1) downto 0)
);
end entity spictrl;
architecture rtl of spictrl is
-----------------------------------------------------------------------------
-- Constants
-----------------------------------------------------------------------------
constant SPICTRL_REV : integer := 0;
constant PCONFIG : apb_config_type := (
0 => ahb_device_reg(VENDOR_GAISLER, GAISLER_SPICTRL, 0, 0, pirq),
1 => apb_iobar(paddr, pmask));
constant OEPOL_LEVEL : std_ulogic := conv_std_logic(oepol = 1);
constant OUTPUT : std_ulogic := OEPOL_LEVEL; -- Enable outputs
constant INPUT : std_ulogic := not OEPOL_LEVEL; -- Tri-state outputs
constant FIFO_DEPTH : integer := 2**fdepth;
constant SLVSEL_EN : integer := slvselen;
constant SLVSEL_SZ : integer := slvselsz;
constant CAP_ADDR : std_logic_vector(7 downto 2) := "000000"; -- 0x00
constant MODE_ADDR : std_logic_vector(7 downto 2) := "001000"; -- 0x20
constant EVENT_ADDR : std_logic_vector(7 downto 2) := "001001"; -- 0x24
constant MASK_ADDR : std_logic_vector(7 downto 2) := "001010"; -- 0x28
constant COM_ADDR : std_logic_vector(7 downto 2) := "001011"; -- 0x2C
constant TD_ADDR : std_logic_vector(7 downto 2) := "001100"; -- 0x30
constant RD_ADDR : std_logic_vector(7 downto 2) := "001101"; -- 0x34
constant SLVSEL_ADDR : std_logic_vector(7 downto 2) := "001110"; -- 0x38
constant SPICTRLCAPREG : std_logic_vector(31 downto 0) :=
conv_std_logic_vector(SLVSEL_SZ,8) & conv_std_logic_vector(SLVSEL_EN,8) &
conv_std_logic_vector(FIFO_DEPTH,8) & conv_std_logic_vector(SPICTRL_REV,8);
-----------------------------------------------------------------------------
-- Types
-----------------------------------------------------------------------------
type spi_mode_rec is record -- SPI Mode register
loopb : std_ulogic; -- loopback mode
cpol : std_ulogic; -- clock polarity
cpha : std_ulogic; -- clock phase
div16 : std_ulogic; -- Divide by 16
rev : std_ulogic; -- Reverse data mode
ms : std_ulogic; -- Master/slave
en : std_ulogic; -- Enable SPI
len : std_logic_vector(3 downto 0); -- Bits per character
pm : std_logic_vector(3 downto 0); -- Prescale modulus
cg : std_logic_vector(4 downto 0); -- Clock gap
end record;
type spi_em_rec is record -- SPI Event and Mask registers
lt : std_ulogic; -- last character transmitted
ov : std_ulogic; -- slave/master overrun
un : std_ulogic; -- slave/master underrun
mme : std_ulogic; -- Multiple-master error
ne : std_ulogic; -- Not empty
nf : std_ulogic; -- Not full
end record;
type spi_fifo is array (0 to (FIFO_DEPTH-1)) of std_logic_vector(31 downto 0);
-- Two stage synchronizers on each input coming from off-chip
type spi_in_array is array (1 downto 0) of spi_in_type;
type spi_reg_type is record
-- SPI registers
mode : spi_mode_rec; -- Mode register
event : spi_em_rec; -- Event register
mask : spi_em_rec; -- Mask register
lst : std_ulogic; -- Only field on command register
td : std_logic_vector(31 downto 0); -- Transmit register
rd : std_logic_vector(31 downto 0); -- Receive register
slvsel : std_logic_vector((SLVSEL_SZ-1) downto 0); -- Slave select register
--
uf : std_ulogic; -- Slave in underflow condition
ov : std_ulogic; -- Receive overflow condition
td_occ : std_ulogic; -- Transmit register occupied
rd_free : std_ulogic; -- Receive register free (empty)
txfifo : spi_fifo; -- Transmit data FIFO
rxfifo : spi_fifo; -- Receive data FIFO
toggle : std_ulogic; -- SCK has toggled
sc : std_ulogic; -- Sample/Change
psck : std_ulogic; -- Previous value of SC
running : std_ulogic;
-- counters
tfreecnt : integer range 0 to FIFO_DEPTH; -- free td fifo slots
rfreecnt : integer range 0 to FIFO_DEPTH; -- free td fifo slots
tdfi : integer range 0 to (FIFO_DEPTH-1); -- First tx queue element
rdfi : integer range 0 to (FIFO_DEPTH-1); -- First rx queue element
tdli : integer range 0 to (FIFO_DEPTH-1); -- Last tx queue element
rdli : integer range 0 to (FIFO_DEPTH-1); -- Last rx queue element
bitcnt : integer range 0 to 31; -- Current bit
divcnt : unsigned(9 downto 0); -- Clock scaler
cgcnt : unsigned(5 downto 0); -- Clock gap counter
--
irq : std_ulogic;
-- Sync registers for inputs
spii : spi_in_array;
-- Output
spio : spi_out_type;
end record;
-----------------------------------------------------------------------------
-- Sub programs
-----------------------------------------------------------------------------
-- Returns an integer containing the character length - 1 in bits as selected
-- by the Mode field LEN.
function spilen (
len : std_logic_vector(3 downto 0))
return std_logic_vector is
begin -- spilen
if len = zero32(3 downto 0) then
return "11111";
else
return "0" & len;
end if;
end spilen;
-- Write clear
procedure wc (
reg_o : out std_ulogic;
reg_i : in std_ulogic;
b : in std_ulogic) is
begin
reg_o := reg_i and not b;
end procedure wc;
-- Reverses string. After this function has been called the first bit
-- to send is always at position 0.
function reverse(
data : std_logic_vector)
return std_logic_vector is
variable rdata: std_logic_vector(data'reverse_range);
begin
for i in data'range loop
rdata(i) := data(i);
end loop;
return rdata;
end function reverse;
-- Performs a HWORD swap if len /= 0
function condhwordswap (
data : std_logic_vector(31 downto 0);
len : std_logic_vector(4 downto 0);
rev : std_ulogic)
return std_logic_vector is
variable rdata : std_logic_vector(31 downto 0);
begin -- condhwordswap
if len = one32(4 downto 0) then
rdata := data;
else
rdata := data(15 downto 0) & data(31 downto 16);
end if;
return rdata;
end condhwordswap;
-- Zeroes out unused part of receive vector.
function select_data (
data : std_logic_vector(31 downto 0);
len : std_logic_vector(4 downto 0))
return std_logic_vector is
variable rdata : std_logic_vector(31 downto 0) := (others => '0');
variable length : integer range 0 to 31 := conv_integer(len);
begin -- select_data
-- Quartus can not handle variable ranges
-- rdata(conv_integer(len) downto 0) := data(conv_integer(len) downto 0);
case length is
when 31 => rdata := data;
when 30 => rdata(30 downto 0) := data(30 downto 0);
when 29 => rdata(29 downto 0) := data(29 downto 0);
when 28 => rdata(28 downto 0) := data(28 downto 0);
when 27 => rdata(27 downto 0) := data(27 downto 0);
when 26 => rdata(26 downto 0) := data(26 downto 0);
when 25 => rdata(25 downto 0) := data(25 downto 0);
when 24 => rdata(24 downto 0) := data(24 downto 0);
when 23 => rdata(23 downto 0) := data(23 downto 0);
when 22 => rdata(22 downto 0) := data(22 downto 0);
when 21 => rdata(21 downto 0) := data(21 downto 0);
when 20 => rdata(20 downto 0) := data(20 downto 0);
when 19 => rdata(19 downto 0) := data(19 downto 0);
when 18 => rdata(18 downto 0) := data(18 downto 0);
when 17 => rdata(17 downto 0) := data(17 downto 0);
when 16 => rdata(16 downto 0) := data(16 downto 0);
when 15 => rdata(15 downto 0) := data(15 downto 0);
when 14 => rdata(14 downto 0) := data(14 downto 0);
when 13 => rdata(13 downto 0) := data(13 downto 0);
when 12 => rdata(12 downto 0) := data(12 downto 0);
when 11 => rdata(11 downto 0) := data(11 downto 0);
when 10 => rdata(10 downto 0) := data(10 downto 0);
when 9 => rdata(9 downto 0) := data(9 downto 0);
when 8 => rdata(8 downto 0) := data(8 downto 0);
when 7 => rdata(7 downto 0) := data(7 downto 0);
when 6 => rdata(6 downto 0) := data(6 downto 0);
when 5 => rdata(5 downto 0) := data(5 downto 0);
when 4 => rdata(4 downto 0) := data(4 downto 0);
when 3 => rdata(3 downto 0) := data(3 downto 0);
when 2 => rdata(2 downto 0) := data(2 downto 0);
when 1 => rdata(1 downto 0) := data(1 downto 0);
when others => rdata(0) := data(0);
end case;
return rdata;
end select_data;
-- purpose: Returns true when a slave is selected and the clock starts
function slv_start (
signal spisel : std_ulogic;
signal cpol : std_ulogic;
signal sck : std_ulogic;
signal prevsck : std_ulogic)
return boolean is
begin -- slv_start
if spisel = '0' then -- Slave is selected
if (sck xor prevsck) = '1' then -- The clock has changed
return (cpol xor sck) = '1'; -- The clock is not idle
end if;
end if;
return false;
end slv_start;
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
signal r, rin : spi_reg_type;
begin
-- SPI controller, register interface and related logic
comb: process (r, rstn, apbi, spii)
variable v : spi_reg_type;
variable irq : std_logic_vector((NAHBIRQ-1) downto 0);
variable apbaddr : std_logic_vector(7 downto 2);
variable apbout : std_logic_vector(31 downto 0);
variable len : std_logic_vector(4 downto 0);
variable indata : std_ulogic;
variable sample, change : std_ulogic;
begin -- process comb
v := r; v.irq := '0'; irq := (others=>'0'); irq(pirq) := r.irq;
apbaddr := apbi.paddr(7 downto 2); apbout := (others => '0');
len := spilen(r.mode.len);
indata := '0'; sample := '0'; change := '0'; v.toggle := '0';
-- read registers
if (apbi.psel(pindex) and apbi.penable and (not apbi.pwrite)) = '1' then
case apbaddr is
when CAP_ADDR =>
apbout := SPICTRLCAPREG;
when MODE_ADDR =>
apbout := zero32(31) & r.mode.loopb & r.mode.cpol & r.mode.cpha &
r.mode.div16 & r.mode.rev & r.mode.ms & r.mode.en &
r.mode.len & r.mode.pm & zero32(15 downto 12) &
r.mode.cg & zero32(6 downto 0);
when EVENT_ADDR =>
apbout := zero32(31 downto 15) & r.event.lt & zero32(13) &
r.event.ov & r.event.un & r.event.mme & r.event.ne &
r.event.nf & zero32(7 downto 0);
when MASK_ADDR =>
apbout := zero32(31 downto 15) & r.mask.lt & zero32(13) &
r.mask.ov & r.mask.un & r.mask.mme & r.mask.ne &
r.mask.nf & zero32(7 downto 0);
when RD_ADDR =>
apbout := condhwordswap(r.rd, len, r.mode.rev);
v.rd_free := '1';
when SLVSEL_ADDR =>
if SLVSEL_EN /= 0 then apbout((SLVSEL_SZ-1) downto 0) := r.slvsel;
else null; end if;
when others => null;
end case;
end if;
-- write registers
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbaddr is
when MODE_ADDR =>
v.mode.loopb := apbi.pwdata(30);
v.mode.cpol := apbi.pwdata(29);
v.mode.cpha := apbi.pwdata(28);
v.mode.div16 := apbi.pwdata(27);
v.mode.rev := apbi.pwdata(26);
v.mode.ms := apbi.pwdata(25);
v.mode.en := apbi.pwdata(24);
v.mode.len := apbi.pwdata(23 downto 20);
v.mode.pm := apbi.pwdata(19 downto 16);
v.mode.cg := apbi.pwdata(11 downto 7);
when EVENT_ADDR =>
wc(v.event.lt, r.event.lt, apbi.pwdata(14));
wc(v.event.ov, r.event.ov, apbi.pwdata(12));
wc(v.event.un, r.event.un, apbi.pwdata(11));
wc(v.event.mme, r.event.mme, apbi.pwdata(10));
when MASK_ADDR =>
v.mask.lt := apbi.pwdata(14);
v.mask.ov := apbi.pwdata(12);
v.mask.un := apbi.pwdata(11);
v.mask.mme := apbi.pwdata(10);
v.mask.ne := apbi.pwdata(9);
v.mask.nf := apbi.pwdata(8);
when COM_ADDR =>
v.lst := apbi.pwdata(22);
when TD_ADDR =>
-- The write is lost if the transmit register is written when
-- the not full bit is zero.
if r.event.nf = '1' then
v.td := apbi.pwdata;
v.td_occ := '1';
end if;
when SLVSEL_ADDR =>
if SLVSEL_EN /= 0 then v.slvsel := apbi.pwdata((SLVSEL_SZ-1) downto 0);
else null; end if;
when others => null;
end case;
end if;
-- Handle transmit FIFO
if r.td_occ = '1' and r.tfreecnt /= 0 then
if r.mode.rev = '0' then
v.txfifo(r.tdli) := r.td;
else
v.txfifo(r.tdli) := reverse(r.td);
end if;
v.tdli := (r.tdli + 1) mod FIFO_DEPTH;
v.tfreecnt := r.tfreecnt - 1;
-- Safe since APB has one wait state between writes
v.td_occ := '0';
end if;
-- Update receive register and FIFO
if r.rd_free = '1' and r.rfreecnt /= FIFO_DEPTH then
if r.mode.rev = '0' then
v.rd := reverse(select_data(r.rxfifo(r.rdfi), len));
else
v.rd := select_data(r.rxfifo(r.rdfi), len);
end if;
v.rdfi := (r.rdfi + 1) mod FIFO_DEPTH;
v.rfreecnt := r.rfreecnt + 1;
v.rd_free := '0';
end if;
if r.mode.en = '1' then -- Core is enabled
-- Not full detection
if r.tfreecnt /= 0 or r.td_occ /= '1' then
v.event.nf := '1';
if (r.mask.nf and not r.event.nf) = '1' then
v.irq := '1';
end if;
else
v.event.nf := '0';
end if;
-- Not empty detection
if r.rfreecnt /= FIFO_DEPTH or r.rd_free /= '1' then
v.event.ne := '1';
if (r.mask.ne and not r.event.ne) = '1' then
v.irq := '1';
end if;
else
v.event.ne := '0';
end if;
end if;
---------------------------------------------------------------------------
-- Clock generation, only in master mode
---------------------------------------------------------------------------
if (r.mode.ms and r.running) = '1' then
-- The frequency of the SPI clock relative to the system clock is
-- determined by the div16 and pm inputs. They have the same meaning as in
-- the MPC83xx register interface. The clock is divided by 4*([PM]+1) and
-- if div16 is set the clock is divided by 16*(4*([PM]+1)). The duty cycle
-- is 50%.
if r.divcnt = 0 then
-- Toggle SCK unless we are in a clock gap
if r.cgcnt = 0 or r.spio.sck /= r.mode.cpol then
v.spio.sck := not r.spio.sck;
v.toggle := '1';
end if;
if r.cgcnt /= 0 then
v.cgcnt := r.cgcnt - 1;
end if;
-- Reload clock scale counter
v.divcnt(4 downto 0) := unsigned('0' & r.mode.pm) + 1;
if r.mode.div16 = '1' then
v.divcnt := shift_left(v.divcnt, 5) - 1;
else
v.divcnt := shift_left(v.divcnt, 1) - 1;
end if;
else
v.divcnt := r.divcnt - 1;
end if;
else
v.divcnt := (others => '0');
end if;
---------------------------------------------------------------------------
-- SPI bus control
---------------------------------------------------------------------------
if (r.mode.en and not r.running) = '1' then
if r.mode.ms = '1' then
v.spio.sck := r.mode.cpol;
v.spio.misooen := INPUT;
v.spio.mosioen := r.mode.loopb xor OEPOL_LEVEL;
v.spio.sckoen := r.mode.loopb xor OEPOL_LEVEL;
else
if r.spii(1).spisel = '0' then
v.spio.misooen := r.mode.loopb xor OEPOL_LEVEL;
else
v.spio.misooen := INPUT;
end if;
v.spio.mosioen := INPUT;
v.spio.sckoen := INPUT;
end if;
if ((r.mode.ms = '1' and r.tfreecnt /= FIFO_DEPTH) or
slv_start(r.spii(1).spisel, r.mode.cpol, r.spii(1).sck, r.psck)) then
-- Slave underrun detection
if r.tfreecnt = FIFO_DEPTH then
v.uf := '1';
if (r.mask.un and not v.event.un) = '1' then
v.irq := '1';
end if;
v.event.un := '1';
end if;
v.running := '1';
end if;
v.bitcnt := 0;
v.cgcnt := (others => '0');
change := not r.mode.cpha;
-- sc should not be changed on b2b
if r.spii(1).spisel /= '0' then
v.sc := not r.mode.cpha;
v.psck := r.mode.cpol;
end if;
end if;
---------------------------------------------------------------------------
-- Handle master operation.
---------------------------------------------------------------------------
if r.mode.ms = '1' then
-- The sc bit determines if the core should read or change the data on
-- the upcoming flank.
if r.toggle = '1' then
v.sc := not r.sc;
end if;
-- Sample data
if (r.toggle and r.sc) = '1' then
sample := '1';
end if;
-- Change data on the clock flank...
if (v.toggle and not r.sc) = '1' then
change := '1';
end if;
-- Detect multiple-master errors (mode-fault)
if r.spii(1).spisel = '0' then
v.mode.en := '0';
v.mode.ms := '0';
v.event.mme := '1';
if (r.mask.mme and not r.event.mme) = '1' then
v.irq := '1';
end if;
v.running := '0';
end if;
indata := spii.miso;
end if;
---------------------------------------------------------------------------
-- Handle slave operation
---------------------------------------------------------------------------
if (r.mode.en and not r.mode.ms) = '1' then
if r.spii(1).spisel = '0' then
v.psck := r.spii(1).sck;
if (r.psck xor r.spii(1).sck) = '1' then
if r.sc = '1' then
sample := '1';
else
change := '1';
end if;
v.sc := not r.sc;
end if;
indata := r.spii(1).mosi;
end if;
end if;
---------------------------------------------------------------------------
-- Used in both master and slave operation
---------------------------------------------------------------------------
if sample = '1' then
-- Detect receive overflow
if (r.rfreecnt = 0 and r.rd_free = '0') or r.ov = '1' then
v.ov := '1';
-- Overflow event and IRQ
if r.ov = '0' then
if (r.mask.ov and not r.event.ov) = '1' then
v.irq := '1';
end if;
v.event.ov := '1';
end if;
else
if r.mode.loopb = '1' then
v.rxfifo(r.rdli)(0) := r.spio.mosi;
else
v.rxfifo(r.rdli)(0) := indata;
end if;
v.rxfifo(r.rdli)(31 downto 1) := r.rxfifo(r.rdli)(30 downto 0);
end if;
if r.bitcnt = conv_integer(len) then
if r.ov = '0' then
v.rdli := (r.rdli + 1) mod FIFO_DEPTH;
v.rfreecnt := v.rfreecnt - 1;
end if;
v.ov := '0'; -- Clear overflow condition
v.bitcnt := 0;
v.cgcnt := unsigned(r.mode.cg & '0');
if r.uf = '0' then
v.tfreecnt := v.tfreecnt + 1;
v.tdfi := (v.tdfi + 1) mod FIFO_DEPTH;
v.txfifo(r.tdfi)(0) := '1';
end if;
if v.tfreecnt /= FIFO_DEPTH then
v.running := r.mode.ms;
else
v.running := '0';
-- LST detection
if r.lst = '1' then
v.event.lt := '1';
if (r.mask.lt and not r.event.lt) = '1' then
v.irq := '1';
end if;
end if;
v.lst := '0';
end if;
v.uf := '0';
else
v.bitcnt := r.bitcnt + 1;
end if;
end if;
if change = '1' then
if v.uf = '0' then
v.spio.miso := r.txfifo(r.tdfi)(r.bitcnt);
v.spio.mosi := r.txfifo(r.tdfi)(r.bitcnt);
else
v.spio.miso := '1';
v.spio.mosi := '1';
end if;
end if;
if r.mode.en = '0' then -- Core is disabled
v.tfreecnt := FIFO_DEPTH;
v.rfreecnt := FIFO_DEPTH;
v.tdfi := 0; v.rdfi := 0;
v.tdli := 0; v.rdli := 0;
v.rd_free := '1';
v.td_occ := '0';
v.lst := '0';
v.uf := '0';
v.ov := '0';
v.running := '0';
v.spio.misooen := INPUT;
v.spio.mosioen := INPUT;
v.spio.sckoen := INPUT;
-- Need to assign sc and psck here if spisel is low when the core is
-- enabled
v.sc := not r.mode.cpha;
v.psck := r.mode.cpol;
-- Set all first bits in txfifo to idle value
for i in 0 to (FIFO_DEPTH-1) loop
v.txfifo(i)(0) := '1';
end loop; -- i
end if;
if rstn = '0' then
v.mode := ('0','0','0','0','0','0','0',"0000","0000", "00000");
v.event := ('0','0','0','0','0','0');
v.mask := ('0','0','0','0','0','0');
v.lst := '0';
v.slvsel := (others => '1');
end if;
-- Synchronize inputs
v.spii(0) := spii;
v.spii(1) := r.spii(0);
-- Update registers
rin <= v;
-- Update outputs
apbo.prdata <= apbout;
apbo.pirq <= irq;
apbo.pconfig <= PCONFIG;
apbo.pindex <= pindex;
slvsel <= r.slvsel;
spio <= r.spio;
end process comb;
reg: process (clk)
begin -- process reg
if rising_edge(clk) then
r <= rin;
end if;
end process reg;
-- Boot message
-- pragma translate_off
bootmsg : report_version
generic map (
"spictrl" & tost(pindex) & ": SPI controller rev " &
tost(0) & ", irq " & tost(pirq));
-- pragma translate_on
end architecture rtl;
| mit | 5a842c8d90c5afba59ba7e64a9e74fc7 | 0.513066 | 3.615156 | false | false | false | false |
michaelfivez/ascon_hardware_implementation | ascon12864_unrolled6/API_plus_CipherCore/PostProcessor.vhd | 9 | 12,832 | -------------------------------------------------------------------------------
--! @file PostProcessor.vhd
--! @brief Post=processing unit for an authenticated encryption module.
--! @project CAESAR Candidate Evaluation
--! @author Ekawat (ice) Homsirikamol
--! @copyright Copyright (c) 2015 Cryptographic Engineering Research Group
--! ECE Department, George Mason University Fairfax, VA, U.S.A.
--! All rights Reserved.
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is publicly available encryption source code that falls
--! under the License Exception TSU (Technology and software-
--! —unrestricted)
--! PISO used within this unit follows the following convention:
--! > Order at the PISO input (left to right) : A(0) A(1) A(2) … A(N-1)
--! > Order at the PISO output (time 0 to time N-1): A(0) A(1) A(2) … A(N-1)
--! > Order in the test vector file (left to right): A(0) A(1) A(2) … A(N-1)
--! where A is a single I/O word.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.AEAD_pkg.all;
entity PostProcessor is
generic (
G_W : integer := 64; --! Output width (bits)
G_DBLK_SIZE : integer := 128; --! Block size (bits)
G_BS_BYTES : integer := 4; --! The number of bits required to hold block size expressed in bytes = log2_ceil(block_size/8)
G_TAG_SIZE : integer := 128; --! Tag size (bits)
G_CIPHERTEXT_MODE : integer := 0; --! Ciphertext processing mode
G_REVERSE_DBLK : integer := 0; --! Reverse datablock
G_NSEC_ENABLE : integer := 0; --! Enable NSEC port
G_LOADLEN_ENABLE : integer := 0; --! Enable load length section
G_PAD : integer := 1; --! Enable padding
G_PAD_D : integer := 0 --! Padding mode (used if G_PAD_D = 2 [extra data block])
);
port (
--! =================
--! External Signals
--! =================
--! Global signals
clk : in std_logic;
rst : in std_logic;
--! Data out signals
do : out std_logic_vector(G_W -1 downto 0); --! Output FIFO data
do_ready : in std_logic; --! Output FIFO ready
do_valid : out std_logic; --! Output FIFO write
--! =================
--! Internal Signals
--! =================
--! Datapath signal
bdo_ready : out std_logic; --! Output PISO ready (Let crypto core knows that it's ready to accept data)
bdo_write : in std_logic; --! Write to output PISO
bdo_data : in std_logic_vector(G_DBLK_SIZE -1 downto 0); --! BDO data
bdo_size : in std_logic_vector(G_BS_BYTES+1 -1 downto 0); --! BDO size (only active when G_CIPHERTEXT_MODE = 2 [Cexp_T])
bdo_nsec : in std_logic; --! BDO nsec type flag
tag_ready : out std_logic; --! Output tag ready (Let crypto core knows that it's ready to accept data)
tag_write : in std_logic; --! Write to output tag register
tag_data : in std_logic_vector(G_TAG_SIZE -1 downto 0); --! Tag data
msg_auth_done : in std_logic; --! Tag comparison completion signal
msg_auth_valid : in std_logic; --! Tag comparison valid signal
--! FIFO signals
bypass_fifo_data : in std_logic_vector(G_W -1 downto 0); --! Bypass FIFO data
bypass_fifo_empty : in std_logic; --! Bypass FIFO empty
bypass_fifo_rd : out std_logic; --! Bypass FIFO read
aux_fifo_din : out std_logic_vector(G_W -1 downto 0);
aux_fifo_ctrl : out std_logic_vector(3 downto 0);
aux_fifo_dout : in std_logic_vector(G_W -1 downto 0);
aux_fifo_status : in std_logic_vector(2 downto 0)
);
end PostProcessor;
architecture structure of PostProcessor is
function getPadSetting return integer is
begin
if (G_PAD = 1) then
return G_PAD_D;
else
return 0;
end if;
end function getPadSetting;
constant PAD_D : integer := getPadSetting;
signal bdo_shf : std_logic;
signal sel_instr_actkey : std_logic;
signal sel_instr_dec : std_logic;
signal sel_hdr : std_logic;
signal sel_do : std_logic_vector(2 -1 downto 0);
signal sel_sw : std_logic_vector(2 -1 downto 0);
signal sel_sgmt_hdr : std_logic_vector(2 -1 downto 0);
signal sel_hword : std_logic;
signal sel_hword_init : std_logic;
signal is_i_type : std_logic_vector(4 -1 downto 0);
signal is_i_nsec : std_logic_vector(4 -1 downto 0);
signal msg_id : std_logic_vector(LEN_MSG_ID -1 downto 0);
signal key_id : std_logic_vector(LEN_KEY_ID -1 downto 0);
signal en_zeroize : std_logic;
signal data_bytes : std_logic_vector(log2_ceil(G_W/8) -1 downto 0);
signal tag_shf : std_logic;
signal save_size : std_logic;
signal clr_size : std_logic;
signal sel_do2 : std_logic;
signal sel_do2_eoi : std_logic;
signal last_sgmt_size : std_logic_vector(CTR_SIZE_LIM -1 downto 0);
begin
uDP: entity work.PostProcessor_Datapath(dataflow)
generic map (
G_W => G_W ,
G_BS_BYTES => G_BS_BYTES ,
G_DBLK_SIZE => G_DBLK_SIZE ,
G_TAG_SIZE => G_TAG_SIZE ,
G_CIPHERTEXT_MODE => G_CIPHERTEXT_MODE ,
G_REVERSE_DBLK => G_REVERSE_DBLK ,
G_PAD_D => PAD_D
)
port map (
--! =================
--! Global Signals
--! =================
clk => clk ,
rst => rst ,
--! =================
--! External signals
--! =================
do => do ,
bypass_fifo_data => bypass_fifo_data ,
bdo_write => bdo_write ,
bdo_data => bdo_data ,
tag_write => tag_write ,
tag_data => tag_data ,
bdo_size => bdo_size ,
--! =================
--! Controls
--! =================
bdo_shf => bdo_shf ,
tag_shf => tag_shf ,
sel_instr_actkey => sel_instr_actkey ,
sel_instr_dec => sel_instr_dec ,
sel_hdr => sel_hdr ,
sel_do => sel_do ,
sel_sw => sel_sw ,
sel_sgmt_hdr => sel_sgmt_hdr ,
sel_hword => sel_hword ,
sel_hword_init => sel_hword_init ,
is_i_type => is_i_type ,
is_i_nsec => is_i_nsec ,
msg_id => msg_id ,
key_id => key_id ,
data_bytes => data_bytes ,
en_zeroize => en_zeroize ,
save_size => save_size ,
clr_size => clr_size ,
sel_do2 => sel_do2 ,
sel_do2_eoi => sel_do2_eoi ,
last_sgmt_size => last_sgmt_size ,
--! =================
--! FIFO
--! =================
aux_fifo_din => aux_fifo_din ,
aux_fifo_dout => aux_fifo_dout
);
uCtrl: entity work.PostProcessor_Control(behavior)
generic map (
G_W => G_W ,
G_DBLK_SIZE => G_DBLK_SIZE ,
G_BS_BYTES => G_BS_BYTES ,
G_TAG_SIZE => G_TAG_SIZE ,
G_REVERSE_DBLK => G_REVERSE_DBLK ,
G_LOADLEN_ENABLE => G_LOADLEN_ENABLE ,
G_CIPHERTEXT_MODE => G_CIPHERTEXT_MODE,
G_PAD_D => PAD_D
)
port map (
--! =================
--! Global Signals
--! =================
--! Global signals
clk => clk ,
rst => rst ,
--! =================
--! External Signals
--! =================
do_ready => do_ready ,
do_valid => do_valid ,
bypass_fifo_data => bypass_fifo_data ,
bypass_fifo_empty => bypass_fifo_empty ,
bypass_fifo_rd => bypass_fifo_rd ,
bdo_ready => bdo_ready ,
bdo_write => bdo_write ,
bdo_size => bdo_size ,
bdo_nsec => bdo_nsec ,
tag_ready => tag_ready ,
tag_write => tag_write ,
msg_auth_done => msg_auth_done ,
msg_auth_valid => msg_auth_valid ,
--! =================
--! Controls
--! =================
bdo_shf => bdo_shf ,
tag_shf => tag_shf ,
sel_instr_actkey => sel_instr_actkey ,
sel_instr_dec => sel_instr_dec ,
sel_hdr => sel_hdr ,
sel_do => sel_do ,
sel_sw => sel_sw ,
sel_sgmt_hdr => sel_sgmt_hdr ,
sel_hword => sel_hword ,
sel_hword_init => sel_hword_init ,
is_i_type => is_i_type ,
is_i_nsec => is_i_nsec ,
msg_id => msg_id ,
key_id => key_id ,
data_bytes => data_bytes ,
en_zeroize => en_zeroize ,
save_size => save_size ,
clr_size => clr_size ,
sel_do2 => sel_do2 ,
sel_do2_eoi => sel_do2_eoi ,
last_sgmt_size => last_sgmt_size ,
--! =================
--! FIFO
--! =================
aux_fifo_dout => aux_fifo_dout ,
aux_fifo_ctrl => aux_fifo_ctrl ,
aux_fifo_status => aux_fifo_status
);
end structure;
| gpl-3.0 | 09dc5e781576acccc126c4b44eef47f4 | 0.368606 | 4.571836 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/pci/pcitb_arb.vhd | 2 | 3,942 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: pcitb_arb
-- File: pcitb_arb.vhd
-- Author: Alf Vaerneus, Gaisler Research
-- Description: PCI arbiter
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.pcitb.all;
entity pcitb_arb is
generic (
slots : integer := 5;
tval : time := 7 ns);
port (
systclk : in pci_syst_type;
ifcin : in pci_ifc_type;
arbin : in pci_arb_type;
arbout : out pci_arb_type);
end pcitb_arb;
architecture tb of pcitb_arb is
type queue_type is array (0 to slots-1) of integer range 0 to slots;
signal queue : queue_type;
signal queue_nr : integer range 0 to slots;
signal wfbus : boolean;
begin
arb : process(systclk)
variable i, slotgnt : integer;
variable set : boolean;
variable bus_idle : boolean;
variable vqueue_nr : integer range 0 to slots;
variable gnt,req : std_logic_vector(slots-1 downto 0);
begin
set := false; vqueue_nr := queue_nr;
if (ifcin.frame and ifcin.irdy) = '1' then bus_idle := true; else bus_idle := false; end if;
gnt := to_x01(arbin.gnt(slots-1 downto 0));
req := to_x01(arbin.req(slots-1 downto 0));
if systclk.rst = '0' then
gnt := (others => '1');
wfbus <= false;
for i in 0 to slots-1 loop
queue(i) <= 0;
end loop;
queue_nr <= 0;
elsif rising_edge(systclk.clk) then
for i in 0 to slots-1 loop
if (gnt(i) or req(i)) = '0' then
if (bus_idle or wfbus) then
set := true;
end if;
end if;
end loop;
for i in 0 to slots-1 loop
if (gnt(i) and not req(i)) = '1' then
if queue(i) = 0 then
vqueue_nr := vqueue_nr+1;
queue(i) <= vqueue_nr;
elsif (queue(i) = 1 and set = false) then
gnt := (others => '1'); gnt(i) := '0';
queue(i) <= 0;
if not bus_idle then wfbus <= true; end if;
if vqueue_nr > 0 then vqueue_nr := vqueue_nr-1; end if;
elsif queue(i) >= 2 then
if (set = false or vqueue_nr <= 1) then
queue(i) <= queue(i)-1;
-- if vqueue_nr > 0 then vqueue_nr := vqueue_nr-1; end if;
end if;
end if;
elsif (req(i) and not gnt(i)) = '1' then
queue(i) <= 0; gnt(i) := '1';
-- if vqueue_nr > 0 then vqueue_nr := vqueue_nr-1; end if;
elsif (req(i) and gnt(i)) = '1' then
if (queue(i) > 0 and set = false) then
queue(i) <= queue(i)-1;
if (vqueue_nr > 0 and queue(i) = 1) then vqueue_nr := vqueue_nr-1; end if;
end if;
end if;
end loop;
end if;
if bus_idle then wfbus <= false; end if;
queue_nr <= vqueue_nr;
arbout.req <= (others => 'Z');
arbout.gnt <= (others => 'Z');
arbout.gnt(slots-1 downto 0) <= gnt;
end process;
end;
-- pragma translate_on
| mit | 8ff561fe88dea540558a9d5f0f36b484 | 0.553019 | 3.507117 | false | false | false | false |
cafe-alpha/wascafe | v13/r07c_de10_20201014_abus4/wasca/synthesis/submodules/Altera_UP_SD_Signal_Trigger.vhd | 7 | 1,749 | -- (C) 2001-2015 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
---------------------------------------------------------------------------------------
-- This module generates a trigger pulse every time it sees a transition
-- from 0 to 1 on signal i_signal.
--
-- NOTES/REVISIONS:
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Altera_UP_SD_Signal_Trigger is
port
(
i_clock : in std_logic;
i_reset_n : in std_logic;
i_signal : in std_logic;
o_trigger : out std_logic
);
end entity;
architecture rtl of Altera_UP_SD_Signal_Trigger is
-- Local wires
-- REGISTERED
signal local_reg : std_logic;
begin
process (i_clock, i_reset_n)
begin
if (i_reset_n = '0') then
local_reg <= '0';
else
if (rising_edge(i_clock)) then
local_reg <= i_signal;
end if;
end if;
end process;
o_trigger <= '1' when ((local_reg = '0') and (i_signal = '1'))
else '0';
end rtl; | gpl-2.0 | 006abd20c535562f2af82e44941b8a58 | 0.643796 | 3.810458 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gleichmann/sim/txt_util.vhd | 2 | 14,269 | library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
package txt_util is
-- prints a message to the screen
procedure print(text : string);
-- prints the message when active
-- useful for debug switches
procedure print(active : boolean; text : string);
-- converts std_logic into a character
function chr(sl : std_logic) return character;
-- converts std_logic into a string (1 to 1)
function str(sl : std_logic) return string;
-- converts std_logic_vector into a string (binary base)
function str(slv : std_logic_vector) return string;
-- converts boolean into a string
function str(b : boolean) return string;
-- converts an integer into a single character
-- (can also be used for hex conversion and other bases)
function chr(int : integer) return character;
-- converts integer into string using specified base
function str(int : integer; base : integer) return string;
-- converts integer to string, using base 10
function str(int : integer) return string;
-- convert std_logic_vector into a string in hex format
function hstr(slv : std_logic_vector) return string;
-- functions to manipulate strings
-----------------------------------
-- convert a character to upper case
function to_upper(c : character) return character;
-- convert a character to lower case
function to_lower(c : character) return character;
-- convert a string to upper case
function to_upper(s : string) return string;
-- convert a string to lower case
function to_lower(s : string) return string;
-- functions to convert strings into other formats
--------------------------------------------------
-- converts a character into std_logic
function to_std_logic(c : character) return std_logic;
-- converts a string into std_logic_vector
function to_std_logic_vector(s : string) return std_logic_vector;
-- file I/O
-----------
-- read variable length string from input file
procedure str_read(file in_file : text;
res_string : out string);
-- print string to a file and start new line
procedure print(file out_file : text;
new_string : in string);
-- print character to a file and start new line
procedure print(file out_file : text;
char : in character);
end txt_util;
package body txt_util is
-- prints text to the screen
procedure print(text : string) is
variable msg_line : line;
begin
write(msg_line, text);
writeline(output, msg_line);
end print;
-- prints text to the screen when active
procedure print(active : boolean; text : string) is
begin
if active then
print(text);
end if;
end print;
-- converts std_logic into a character
function chr(sl : std_logic) return character is
variable c : character;
begin
case sl is
when 'U' => c := 'U';
when 'X' => c := 'X';
when '0' => c := '0';
when '1' => c := '1';
when 'Z' => c := 'Z';
when 'W' => c := 'W';
when 'L' => c := 'L';
when 'H' => c := 'H';
when '-' => c := '-';
end case;
return c;
end chr;
-- converts std_logic into a string (1 to 1)
function str(sl : std_logic) return string is
variable s : string(1 to 1);
begin
s(1) := chr(sl);
return s;
end str;
-- converts std_logic_vector into a string (binary base)
-- (this also takes care of the fact that the range of
-- a string is natural while a std_logic_vector may
-- have an integer range)
function str(slv : std_logic_vector) return string is
variable result : string (1 to slv'length);
variable r : integer;
begin
r := 1;
for i in slv'range loop
result(r) := chr(slv(i));
r := r + 1;
end loop;
return result;
end str;
function str(b : boolean) return string is
begin
if b then
return "true";
else
return "false";
end if;
end str;
-- converts an integer into a character
-- for 0 to 9 the obvious mapping is used, higher
-- values are mapped to the characters A-Z
-- (this is usefull for systems with base > 10)
-- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
function chr(int : integer) return character is
variable c : character;
begin
case int is
when 0 => c := '0';
when 1 => c := '1';
when 2 => c := '2';
when 3 => c := '3';
when 4 => c := '4';
when 5 => c := '5';
when 6 => c := '6';
when 7 => c := '7';
when 8 => c := '8';
when 9 => c := '9';
when 10 => c := 'A';
when 11 => c := 'B';
when 12 => c := 'C';
when 13 => c := 'D';
when 14 => c := 'E';
when 15 => c := 'F';
when 16 => c := 'G';
when 17 => c := 'H';
when 18 => c := 'I';
when 19 => c := 'J';
when 20 => c := 'K';
when 21 => c := 'L';
when 22 => c := 'M';
when 23 => c := 'N';
when 24 => c := 'O';
when 25 => c := 'P';
when 26 => c := 'Q';
when 27 => c := 'R';
when 28 => c := 'S';
when 29 => c := 'T';
when 30 => c := 'U';
when 31 => c := 'V';
when 32 => c := 'W';
when 33 => c := 'X';
when 34 => c := 'Y';
when 35 => c := 'Z';
when others => c := '?';
end case;
return c;
end chr;
-- convert integer to string using specified base
-- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
function str(int : integer; base : integer) return string is
variable temp : string(1 to 10);
variable num : integer;
variable abs_int : integer;
variable len : integer := 1;
variable power : integer := 1;
begin
-- bug fix for negative numbers
abs_int := abs(int);
num := abs_int;
while num >= base loop -- Determine how many
len := len + 1; -- characters required
num := num / base; -- to represent the
end loop; -- number.
for i in len downto 1 loop -- Convert the number to
temp(i) := chr(abs_int/power mod base); -- a string starting
power := power * base; -- with the right hand
end loop; -- side.
-- return result and add sign if required
if int < 0 then
return '-'& temp(1 to len);
else
return temp(1 to len);
end if;
end str;
-- convert integer to string, using base 10
function str(int : integer) return string is
begin
return str(int, 10);
end str;
-- converts a std_logic_vector into a hex string.
function hstr(slv : std_logic_vector) return string is
variable hexlen : integer;
variable longslv : std_logic_vector(67 downto 0) := (others => '0');
variable hex : string(1 to 16);
variable fourbit : std_logic_vector(3 downto 0);
begin
hexlen := (slv'left+1)/4;
if (slv'left+1) mod 4 /= 0 then
hexlen := hexlen + 1;
end if;
longslv(slv'left downto 0) := slv;
for i in (hexlen -1) downto 0 loop
fourbit := longslv(((i*4)+3) downto (i*4));
case fourbit is
when "0000" => hex(hexlen -I) := '0';
when "0001" => hex(hexlen -I) := '1';
when "0010" => hex(hexlen -I) := '2';
when "0011" => hex(hexlen -I) := '3';
when "0100" => hex(hexlen -I) := '4';
when "0101" => hex(hexlen -I) := '5';
when "0110" => hex(hexlen -I) := '6';
when "0111" => hex(hexlen -I) := '7';
when "1000" => hex(hexlen -I) := '8';
when "1001" => hex(hexlen -I) := '9';
when "1010" => hex(hexlen -I) := 'A';
when "1011" => hex(hexlen -I) := 'B';
when "1100" => hex(hexlen -I) := 'C';
when "1101" => hex(hexlen -I) := 'D';
when "1110" => hex(hexlen -I) := 'E';
when "1111" => hex(hexlen -I) := 'F';
when "ZZZZ" => hex(hexlen -I) := 'z';
when "UUUU" => hex(hexlen -I) := 'u';
when "XXXX" => hex(hexlen -I) := 'x';
when others => hex(hexlen -I) := '?';
end case;
end loop;
return hex(1 to hexlen);
end hstr;
-- functions to manipulate strings
-----------------------------------
-- convert a character to upper case
function to_upper(c : character) return character is
variable u : character;
begin
case c is
when 'a' => u := 'A';
when 'b' => u := 'B';
when 'c' => u := 'C';
when 'd' => u := 'D';
when 'e' => u := 'E';
when 'f' => u := 'F';
when 'g' => u := 'G';
when 'h' => u := 'H';
when 'i' => u := 'I';
when 'j' => u := 'J';
when 'k' => u := 'K';
when 'l' => u := 'L';
when 'm' => u := 'M';
when 'n' => u := 'N';
when 'o' => u := 'O';
when 'p' => u := 'P';
when 'q' => u := 'Q';
when 'r' => u := 'R';
when 's' => u := 'S';
when 't' => u := 'T';
when 'u' => u := 'U';
when 'v' => u := 'V';
when 'w' => u := 'W';
when 'x' => u := 'X';
when 'y' => u := 'Y';
when 'z' => u := 'Z';
when others => u := c;
end case;
return u;
end to_upper;
-- convert a character to lower case
function to_lower(c : character) return character is
variable l : character;
begin
case c is
when 'A' => l := 'a';
when 'B' => l := 'b';
when 'C' => l := 'c';
when 'D' => l := 'd';
when 'E' => l := 'e';
when 'F' => l := 'f';
when 'G' => l := 'g';
when 'H' => l := 'h';
when 'I' => l := 'i';
when 'J' => l := 'j';
when 'K' => l := 'k';
when 'L' => l := 'l';
when 'M' => l := 'm';
when 'N' => l := 'n';
when 'O' => l := 'o';
when 'P' => l := 'p';
when 'Q' => l := 'q';
when 'R' => l := 'r';
when 'S' => l := 's';
when 'T' => l := 't';
when 'U' => l := 'u';
when 'V' => l := 'v';
when 'W' => l := 'w';
when 'X' => l := 'x';
when 'Y' => l := 'y';
when 'Z' => l := 'z';
when others => l := c;
end case;
return l;
end to_lower;
-- convert a string to upper case
function to_upper(s : string) return string is
variable uppercase : string (s'range);
begin
for i in s'range loop
uppercase(i) := to_upper(s(i));
end loop;
return uppercase;
end to_upper;
-- convert a string to lower case
function to_lower(s : string) return string is
variable lowercase : string (s'range);
begin
for i in s'range loop
lowercase(i) := to_lower(s(i));
end loop;
return lowercase;
end to_lower;
-- functions to convert strings into other types
-- converts a character into a std_logic
function to_std_logic(c : character) return std_logic is
variable sl : std_logic;
begin
case c is
when 'U' =>
sl := 'U';
when 'X' =>
sl := 'X';
when '0' =>
sl := '0';
when '1' =>
sl := '1';
when 'Z' =>
sl := 'Z';
when 'W' =>
sl := 'W';
when 'L' =>
sl := 'L';
when 'H' =>
sl := 'H';
when '-' =>
sl := '-';
when others =>
sl := 'X';
end case;
return sl;
end to_std_logic;
-- converts a string into std_logic_vector
function to_std_logic_vector(s : string) return std_logic_vector is
variable slv : std_logic_vector(s'high-s'low downto 0);
variable k : integer;
begin
k := s'high-s'low;
for i in s'range loop
slv(k) := to_std_logic(s(i));
k := k - 1;
end loop;
return slv;
end to_std_logic_vector;
----------------
-- file I/O --
----------------
-- read variable length string from input file
procedure str_read(file in_file : text;
res_string : out string) is
variable l : line;
variable c : character;
variable is_string : boolean;
begin
readline(in_file, l);
-- clear the contents of the result string
for i in res_string'range loop
res_string(i) := ' ';
end loop;
-- read all characters of the line, up to the length
-- of the results string
for i in res_string'range loop
read(l, c, is_string);
res_string(i) := c;
if not is_string then -- found end of line
exit;
end if;
end loop;
end str_read;
-- print string to a file
procedure print(file out_file : text;
new_string : in string) is
variable l : line;
begin
write(l, new_string);
writeline(out_file, l);
end print;
-- print character to a file and start new line
procedure print(file out_file : text;
char : in character) is
variable l : line;
begin
write(l, char);
writeline(out_file, l);
end print;
-- appends contents of a string to a file until line feed occurs
-- (LF is considered to be the end of the string)
procedure str_write(file out_file : text;
new_string : in string) is
begin
for i in new_string'range loop
print(out_file, new_string(i));
if new_string(i) = LF then -- end of string
exit;
end if;
end loop;
end str_write;
end txt_util;
| mit | f9116e8d535872e40edfa9cd0f796d8a | 0.481043 | 3.67379 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/memctrl/srctrl.vhd | 2 | 13,959 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: srctrl
-- File: srctrl.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Modified: Marko Isomaki - Gaisler Research
-- Description: 32-bit SRAM memory controller with read-modify-write
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use grlib.devices.all;
use gaisler.memctrl.all;
entity srctrl is
generic (
hindex : integer := 0;
romaddr : integer := 0;
rommask : integer := 16#ff0#;
ramaddr : integer := 16#400#;
rammask : integer := 16#ff0#;
ioaddr : integer := 16#200#;
iomask : integer := 16#ff0#;
ramws : integer := 0;
romws : integer := 2;
iows : integer := 2;
rmw : integer := 0; -- read-modify-write enable
prom8en : integer := 0;
oepol : integer := 0;
srbanks : integer range 1 to 5 := 1;
banksz : integer range 0 to 13 := 13;
romasel : integer range 0 to 28 := 19
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sri : in memory_in_type;
sro : out memory_out_type;
sdo : out sdctrl_out_type
);
end;
architecture rtl of srctrl is
constant VERSION : amba_version_type := 0;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg(VENDOR_GAISLER, GAISLER_SRCTRL, 0, VERSION, 0),
4 => ahb_membar(romaddr, '1', '1', rommask),
5 => ahb_membar(ramaddr, '1', '1', rammask),
6 => ahb_membar(ioaddr, '0', '0', iomask),
others => zero32);
type srcycletype is (idle, read1, read2, write1, write2, rmw1, rmw2, rmw3);
type prom8cycletype is (idle, read1, read2);
function byteswap (rdata, wdata, addr, size : std_logic_vector) return std_logic_vector is
variable tmp : std_logic_vector(31 downto 0);
variable a : std_logic_vector(1 downto 0);
begin
tmp := rdata; a := addr(1 downto 0);
if size(0) = '0' then
case a is
when "00" => tmp(31 downto 24) := wdata(31 downto 24);
when "01" => tmp(23 downto 16) := wdata(23 downto 16);
when "10" => tmp(15 downto 8) := wdata(15 downto 8);
when others => tmp(7 downto 0) := wdata(7 downto 0);
end case;
else
if addr(1) = '0' then tmp(31 downto 16) := wdata(31 downto 16);
else tmp(15 downto 0) := wdata(15 downto 0); end if;
end if;
return(tmp);
end;
-- local registers
type reg_type is record
hready : std_ulogic;
hsel : std_ulogic;
hmbsel : std_logic_vector(0 to 2);
bdrive : std_ulogic;
nbdrive : std_ulogic;
srstate : srcycletype;
haddr : std_logic_vector(31 downto 0);
hrdata : std_logic_vector(31 downto 0);
hwdata : std_logic_vector(31 downto 0);
hwrite : std_ulogic;
htrans : std_logic_vector(1 downto 0);
hburst : std_logic_vector(2 downto 0);
hresp : std_logic_vector(1 downto 0);
size : std_logic_vector(1 downto 0);
read : std_ulogic;
oen : std_ulogic;
ramsn : std_ulogic;
romsn : std_ulogic;
vramsn : std_logic_vector(4 downto 0);
ramoen : std_logic_vector(4 downto 0);
vromsn : std_logic_vector(1 downto 0);
writen : std_ulogic;
wen : std_logic_vector(3 downto 0);
mben : std_logic_vector(3 downto 0);
ws : std_logic_vector(3 downto 0);
iosn : std_ulogic;
-- 8-bit prom access
pr8state : prom8cycletype;
data8 : std_logic_vector(23 downto 0);
ready8 : std_ulogic;
bwidth : std_logic_vector(1 downto 0);
end record;
signal r, ri : reg_type;
-- vectored output enable to data pads
signal rbdrive, ribdrive : std_logic_vector(31 downto 0);
attribute syn_preserve : boolean;
attribute syn_preserve of rbdrive : signal is true;
begin
ctrl : process(rst, ahbsi, r, sri, rbdrive)
variable v : reg_type; -- local variables for registers
variable dqm : std_logic_vector(3 downto 0);
variable adec : std_logic_vector(1 downto 0);
variable rams : std_logic_vector(4 downto 0);
variable roms : std_logic_vector(1 downto 0);
variable haddr : std_logic_vector(31 downto 0);
variable hrdata : std_logic_vector(31 downto 0);
variable hsize : std_logic_vector(1 downto 0);
variable hwrite : std_ulogic;
variable htrans : std_logic_vector(1 downto 0);
variable vramws, vromws, viows : std_logic_vector(3 downto 0);
-- 8-bit prom access
variable romsn : std_ulogic;
variable bdrive : std_ulogic;
variable oen : std_ulogic;
variable writen : std_ulogic;
variable hready : std_ulogic;
variable ws : std_logic_vector(3 downto 0);
variable hwdata : std_logic_vector(31 downto 0);
variable prom8sel : std_ulogic;
variable vbdrive : std_logic_vector(31 downto 0);
variable sbdrive : std_ulogic;
begin
-- Variable default settings to avoid latches
v := r; v.hresp := HRESP_OKAY; v.hrdata := sri.data; hrdata := r.hrdata;
vramws := conv_std_logic_vector(ramws, 4); vbdrive := rbdrive;
vromws := conv_std_logic_vector(romws, 4);
viows := conv_std_logic_vector(iows, 4);
v.bwidth := sri.bwidth;
if (prom8en = 1) and (r.bwidth = "00") then prom8sel := '1';
else prom8sel := '0'; end if;
if (ahbsi.hready = '1') then
if (ahbsi.hsel(hindex) and ahbsi.htrans(1)) = '1' then
v.size := ahbsi.hsize(1 downto 0); v.hwrite := ahbsi.hwrite;
v.htrans := ahbsi.htrans; v.hburst := ahbsi.hburst;
v.hsel := '1'; v.hmbsel := ahbsi.hmbsel(0 to 2);
v.haddr := ahbsi.haddr; v.hready := '0';
else
v.hsel := '0';
end if;
end if;
if (r.hsel = '1') and (ahbsi.hready = '0') then
haddr := r.haddr; hsize := r.size;
htrans := r.htrans; hwrite := r.hwrite;
else
haddr := ahbsi.haddr; hsize := ahbsi.hsize(1 downto 0);
htrans := ahbsi.htrans; hwrite := ahbsi.hwrite;
end if;
-- chip-select decoding
adec := haddr(banksz+14 downto banksz+13);
rams := '0' & decode(adec);
case srbanks is
when 1 => rams := "00001";
when 2 => rams := "000" & (rams(3 downto 2) or rams(1 downto 0));
when others => null;
end case;
roms := haddr(romasel) & not haddr(romasel);
-- generate write strobes
if rmw = 1 then dqm := "0000"; else
case r.size is
when "00" =>
case r.haddr(1 downto 0) is
when "00" => dqm := "1110";
when "01" => dqm := "1101";
when "10" => dqm := "1011";
when others => dqm := "0111";
end case;
when "01" =>
if r.haddr(1) = '0' then dqm := "1100"; else dqm := "0011"; end if;
when others => dqm := "0000";
end case;
end if;
-- main FSM
case r.srstate is
when idle =>
if (v.hsel = '1') and not
(((v.ramsn or r.romsn) = '0') or ((v.romsn or r.ramsn) = '0')) and not
((v.hmbsel(0) and not hwrite and prom8sel) = '1' and prom8en = 1)
then
v.hready := '0';
v.ramsn := not v.hmbsel(1); v.romsn := not v.hmbsel(0);
v.iosn := not v.hmbsel(2);
v.read := not hwrite;
if hwrite = '1' then
if (rmw = 1) and (hsize(1) = '0') and (v.hmbsel(1) = '1') then
v.srstate := rmw1; v.read := '1';
else v.srstate := write1; end if;
elsif ahbsi.htrans = "10" then v.srstate := read1;
else v.srstate := read2; end if;
v.oen := not v.read;
else
v.ramsn := '1'; v.romsn := '1'; v.bdrive := '1'; v.oen := '1';
v.iosn := '1';
end if;
if v.romsn = '0' then v.ws := vromws;
elsif v.iosn = '0' then v.ws := viows;
else v.ws := vramws; end if;
when read1 =>
v.srstate := read2;
when read2 =>
v.ws := r.ws -1; v.oen := '0';
if r.ws = "0000" then
v.srstate := idle; v.hready := '1'; v.haddr := ahbsi.haddr;
v.ramsn := not (ahbsi.hmbsel(1) and ahbsi.htrans(1));
v.romsn := not (ahbsi.hmbsel(0) and ahbsi.htrans(1));
v.oen := not (ahbsi.hsel(hindex) and ahbsi.htrans(1) and not ahbsi.hwrite);
end if;
when write1 =>
if r.romsn = '0' then v.ws := vromws;
elsif v.iosn = '0' then v.ws := viows;
else v.ws := vramws; end if;
v.srstate := write2; v.bdrive := '0'; v.wen := dqm; v.writen := '0';
v.hwdata := ahbsi.hwdata;
when write2 =>
if r.ws = "0000" then
v.srstate := idle; v.bdrive := '1'; v.wen := "1111"; v.writen := '1';
v.hready := '1';
end if;
v.ws := r.ws -1;
when rmw1 =>
if (rmw = 1) then v.oen := '0';
v.srstate := rmw2;
v.hwdata := ahbsi.hwdata;
end if;
when rmw2 =>
if (rmw = 1) then
v.ws := r.ws -1;
if r.ws = "0000" then v.oen := '1'; v.srstate := rmw3; end if;
end if;
when rmw3 =>
if (rmw = 1) then
v.hwdata := byteswap(r.hrdata, r.hwdata, r.haddr, r.size);
v.srstate := write2; v.bdrive := '0'; v.wen := dqm; v.writen := '0';
end if;
if r.romsn = '0' then v.ws := vromws; else v.ws := vramws; end if;
end case;
if (ahbsi.hready and ahbsi.hsel(hindex) ) = '1' then
if ahbsi.htrans(1) = '0' then v.hready := '1'; end if;
end if;
-- 8-bit PROM access FSM
if prom8en = 1 then
hready := '0'; ws := v.ws; v.ready8 := '0';
bdrive := '1'; oen := '1'; writen := '1'; romsn := '1';
if r.ready8 = '1' then
v.data8 := r.data8(15 downto 0) & r.hrdata(31 downto 24);
case r.size is
when "00" => hrdata := r.hrdata(31 downto 24) &
r.hrdata(31 downto 24) & r.hrdata(31 downto 24) & r.hrdata(31 downto 24);
when "01" => hrdata := r.data8(7 downto 0) & r.hrdata(31 downto 24) &
r.data8(7 downto 0) & r.hrdata(31 downto 24);
when others => hrdata := r.data8 & r.hrdata(31 downto 24);
end case;
end if;
case r.pr8state is
when idle =>
if ( (v.hsel and v.hmbsel(0) and not hwrite and prom8sel) = '1')
then
romsn := '0'; v.pr8state := read1; oen := '0';
end if;
when read1 =>
oen := '0'; romsn := '0'; v.pr8state := read2; ws := vromws;
when read2 =>
oen := '0'; ws := r.ws - 1; romsn := '0';
if r.ws = "0000" then
v.haddr(1 downto 0) := r.haddr(1 downto 0) + 1;
if (r.size = "00") or ((r.size = "01") and (r.haddr(0) = '1'))
or r.haddr(1 downto 0) = "11"
then
hready := '1'; v.pr8state := idle; oen := '1';
else
v.pr8state := read1;
end if;
v.ready8 := '1';
end if;
when others =>
v.pr8state := idle;
end case;
v.romsn := v.romsn and romsn; v.bdrive := v.bdrive and bdrive;
v.oen := v.oen and oen; v.writen := v.writen and writen;
v.hready := v.hready or hready; v.ws := ws;
end if;
if (v.oen or v.ramsn) = '0' then v.ramoen := not rams;
else v.ramoen := (others => '1'); end if;
if v.romsn = '0' then v.vromsn := not roms;
else v.vromsn := (others => '1'); end if;
if v.ramsn = '0' then v.vramsn := not rams;
else v.vramsn := (others => '1'); end if;
if v.read = '1' then v.mben := "0000"; else v.mben := v.wen; end if;
v.nbdrive := not v.bdrive;
if oepol = 1 then sbdrive := r.nbdrive; vbdrive := (others => v.nbdrive);
else sbdrive := r.bdrive; vbdrive := (others => v.bdrive); end if;
-- reset
if rst = '0' then
v.srstate := idle; v.hsel := '0'; v.writen := '1';
v.wen := (others => '1'); v.hready := '1'; v.read := '1';
v.ws := (others => '0');
if prom8en = 1 then v.pr8state := idle; end if;
end if;
ribdrive <= vbdrive;
ri <= v;
sro.address <= r.haddr;
sro.bdrive <= (others => sbdrive);
sro.vbdrive <= rbdrive;
sro.ramsn <= "111" & r.vramsn;
sro.ramoen <= "111" & r.ramoen;
sro.romsn <= "111111" & r.vromsn;
sro.iosn <= r.iosn;
sro.wrn <= r.wen;
sro.oen <= r.oen;
sro.read <= r.read;
sro.data <= r.hwdata;
sro.writen <= r.writen;
sro.ramn <= r.ramsn;
sro.romn <= r.romsn;
ahbso.hready <= r.hready;
ahbso.hresp <= r.hresp;
ahbso.hrdata <= hrdata;
ahbso.hconfig <= hconfig;
ahbso.hcache <= '1';
ahbso.hirq <= (others => '0');
ahbso.hindex <= hindex;
ahbso.hsplit <= (others => '0');
end process;
sdo.sdcsn <= "11";
sdo.sdcke <= "11";
sdo.sdwen <= '1';
sdo.rasn <= '1';
sdo.casn <= '1';
sdo.dqm <= (others => '1');
sdo.address <= (others => '0');
sdo.data <= (others => '0');
sro.mben <= r.mben;
regs : process(clk,rst)
begin
if rising_edge(clk) then r <= ri; rbdrive <= ribdrive; end if;
if rst = '0' then
r.ramsn <= '1';
r.romsn <= '1'; r.oen <= '1';
r.bdrive <= '1'; r.nbdrive <= '0';
r.vramsn <= (others => '1'); r.vromsn <= (others => '1');
if oepol = 0 then rbdrive <= (others => '1');
else rbdrive <= (others => '0'); end if;
end if;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("srctrl" & tost(hindex) &
": 32-bit PROM/SRAM controller rev " & tost(VERSION));
-- pragma translate_on
end;
| mit | bc5dd2d2f35aaa2e867537fa6a69fc29 | 0.564367 | 3.101311 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/tech/proasic3/components/proasic3.vhd | 2 | 115,108 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: components
-- File: components.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: Actel proasic3 RAM component declarations
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
package components is
-- Proasic3 rams
component RAM4K9
generic (abits : integer range 9 to 12 := 9);
port(
ADDRA0, ADDRA1, ADDRA2, ADDRA3, ADDRA4, ADDRA5, ADDRA6, ADDRA7,
ADDRA8, ADDRA9, ADDRA10, ADDRA11 : in std_logic;
ADDRB0, ADDRB1, ADDRB2, ADDRB3, ADDRB4, ADDRB5, ADDRB6, ADDRB7,
ADDRB8, ADDRB9, ADDRB10, ADDRB11 : in std_logic;
BLKA, WENA, PIPEA, WMODEA, WIDTHA0, WIDTHA1, WENB, BLKB,
PIPEB, WMODEB, WIDTHB1, WIDTHB0 : in std_logic;
DINA0, DINA1, DINA2, DINA3, DINA4, DINA5, DINA6, DINA7, DINA8 : in std_logic;
DINB0, DINB1, DINB2, DINB3, DINB4, DINB5, DINB6, DINB7, DINB8 : in std_logic;
RESET, CLKA, CLKB : in std_logic;
DOUTA0, DOUTA1, DOUTA2, DOUTA3, DOUTA4, DOUTA5, DOUTA6, DOUTA7, DOUTA8 : out std_logic;
DOUTB0, DOUTB1, DOUTB2, DOUTB3, DOUTB4, DOUTB5, DOUTB6, DOUTB7, DOUTB8 : out std_logic
);
end component;
component RAM512X18
port(
RADDR8, RADDR7, RADDR6, RADDR5, RADDR4, RADDR3, RADDR2, RADDR1, RADDR0 : in std_logic;
WADDR8, WADDR7, WADDR6, WADDR5, WADDR4, WADDR3, WADDR2, WADDR1, WADDR0 : in std_logic;
WD17, WD16, WD15, WD14, WD13, WD12, WD11, WD10, WD9,
WD8, WD7, WD6, WD5, WD4, WD3, WD2, WD1, WD0 : in std_logic;
REN, WEN, RESET, RW0, RW1, WW1, WW0, PIPE, RCLK, WCLK : in std_logic;
RD17, RD16, RD15, RD14, RD13, RD12, RD11, RD10, RD9,
RD8, RD7, RD6, RD5, RD4, RD3, RD2, RD1, RD0 : out std_logic
);
end component;
component PLL
generic(
VCOFREQUENCY : Real := 0.0;
f_CLKA_LOCK : Integer := 3; -- Number of CLKA pulses after which LOCK is raised
TimingChecksOn : Boolean := True;
InstancePath : String := "*";
Xon : Boolean := False;
MsgOn : Boolean := True;
tipd_CLKA : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_EXTFB : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_POWERDOWN : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_OADIV0 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_OADIV1 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_OADIV2 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_OADIV3 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_OADIV4 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_OAMUX0 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_OAMUX1 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_OAMUX2 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_DLYGLA0 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_DLYGLA1 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_DLYGLA2 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_DLYGLA3 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_DLYGLA4 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_OBDIV0 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_OBDIV1 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_OBDIV2 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_OBDIV3 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_OBDIV4 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_OBMUX0 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_OBMUX1 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_OBMUX2 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_DLYYB0 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_DLYYB1 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_DLYYB2 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_DLYYB3 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_DLYYB4 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_DLYGLB0 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_DLYGLB1 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_DLYGLB2 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_DLYGLB3 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_DLYGLB4 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_OCDIV0 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_OCDIV1 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_OCDIV2 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_OCDIV3 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_OCDIV4 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_OCMUX0 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_OCMUX1 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_OCMUX2 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_DLYYC0 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_DLYYC1 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_DLYYC2 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_DLYYC3 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_DLYYC4 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_DLYGLC0 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_DLYGLC1 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_DLYGLC2 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_DLYGLC3 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_DLYGLC4 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_FINDIV0 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_FINDIV1 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_FINDIV2 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_FINDIV3 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_FINDIV4 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_FINDIV5 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_FINDIV6 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_FBDIV0 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_FBDIV1 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_FBDIV2 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_FBDIV3 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_FBDIV4 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_FBDIV5 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_FBDIV6 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_FBDLY0 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_FBDLY1 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_FBDLY2 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_FBDLY3 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_FBDLY4 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_FBSEL0 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_FBSEL1 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_XDLYSEL : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_VCOSEL0 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_VCOSEL1 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tipd_VCOSEL2 : VitalDelayType01 := ( 0.000 ns,0.000 ns );
tpd_CLKA_GLA : VitalDelayType01 := ( 0.100 ns, 0.100 ns);
tpd_EXTFB_GLA : VitalDelayType01 := ( 0.100 ns, 0.100 ns);
tpd_POWERDOWN_GLA : VitalDelayType01 := ( 0.100 ns, 0.100 ns);
tpd_CLKA_GLB : VitalDelayType01 := ( 0.100 ns, 0.100 ns);
tpd_EXTFB_GLB : VitalDelayType01 := ( 0.100 ns, 0.100 ns);
tpd_POWERDOWN_GLB : VitalDelayType01 := ( 0.100 ns, 0.100 ns);
tpd_CLKA_GLC : VitalDelayType01 := ( 0.100 ns, 0.100 ns);
tpd_EXTFB_GLC : VitalDelayType01 := ( 0.100 ns, 0.100 ns);
tpd_POWERDOWN_GLC : VitalDelayType01 := ( 0.100 ns, 0.100 ns);
tpd_CLKA_YB : VitalDelayType01 := ( 0.100 ns, 0.100 ns);
tpd_EXTFB_YB : VitalDelayType01 := ( 0.100 ns, 0.100 ns);
tpd_POWERDOWN_YB : VitalDelayType01 := ( 0.100 ns, 0.100 ns);
tpd_CLKA_YC : VitalDelayType01 := ( 0.100 ns, 0.100 ns);
tpd_EXTFB_YC : VitalDelayType01 := ( 0.100 ns, 0.100 ns);
tpd_POWERDOWN_YC : VitalDelayType01 := ( 0.100 ns, 0.100 ns);
tpd_CLKA_LOCK : VitalDelayType01 := ( 0.100 ns, 0.100 ns));
port (
CLKA : in STD_ULOGIC;
EXTFB : in STD_ULOGIC;
POWERDOWN : in STD_ULOGIC;
OADIV0 : in STD_ULOGIC;
OADIV1 : in STD_ULOGIC;
OADIV2 : in STD_ULOGIC;
OADIV3 : in STD_ULOGIC;
OADIV4 : in STD_ULOGIC;
OAMUX0 : in STD_ULOGIC;
OAMUX1 : in STD_ULOGIC;
OAMUX2 : in STD_ULOGIC;
DLYGLA0 : in STD_ULOGIC;
DLYGLA1 : in STD_ULOGIC;
DLYGLA2 : in STD_ULOGIC;
DLYGLA3 : in STD_ULOGIC;
DLYGLA4 : in STD_ULOGIC;
OBDIV0 : in STD_ULOGIC;
OBDIV1 : in STD_ULOGIC;
OBDIV2 : in STD_ULOGIC;
OBDIV3 : in STD_ULOGIC;
OBDIV4 : in STD_ULOGIC;
OBMUX0 : in STD_ULOGIC;
OBMUX1 : in STD_ULOGIC;
OBMUX2 : in STD_ULOGIC;
DLYYB0 : in STD_ULOGIC;
DLYYB1 : in STD_ULOGIC;
DLYYB2 : in STD_ULOGIC;
DLYYB3 : in STD_ULOGIC;
DLYYB4 : in STD_ULOGIC;
DLYGLB0 : in STD_ULOGIC;
DLYGLB1 : in STD_ULOGIC;
DLYGLB2 : in STD_ULOGIC;
DLYGLB3 : in STD_ULOGIC;
DLYGLB4 : in STD_ULOGIC;
OCDIV0 : in STD_ULOGIC;
OCDIV1 : in STD_ULOGIC;
OCDIV2 : in STD_ULOGIC;
OCDIV3 : in STD_ULOGIC;
OCDIV4 : in STD_ULOGIC;
OCMUX0 : in STD_ULOGIC;
OCMUX1 : in STD_ULOGIC;
OCMUX2 : in STD_ULOGIC;
DLYYC0 : in STD_ULOGIC;
DLYYC1 : in STD_ULOGIC;
DLYYC2 : in STD_ULOGIC;
DLYYC3 : in STD_ULOGIC;
DLYYC4 : in STD_ULOGIC;
DLYGLC0 : in STD_ULOGIC;
DLYGLC1 : in STD_ULOGIC;
DLYGLC2 : in STD_ULOGIC;
DLYGLC3 : in STD_ULOGIC;
DLYGLC4 : in STD_ULOGIC;
FINDIV0 : in STD_ULOGIC;
FINDIV1 : in STD_ULOGIC;
FINDIV2 : in STD_ULOGIC;
FINDIV3 : in STD_ULOGIC;
FINDIV4 : in STD_ULOGIC;
FINDIV5 : in STD_ULOGIC;
FINDIV6 : in STD_ULOGIC;
FBDIV0 : in STD_ULOGIC;
FBDIV1 : in STD_ULOGIC;
FBDIV2 : in STD_ULOGIC;
FBDIV3 : in STD_ULOGIC;
FBDIV4 : in STD_ULOGIC;
FBDIV5 : in STD_ULOGIC;
FBDIV6 : in STD_ULOGIC;
FBDLY0 : in STD_ULOGIC;
FBDLY1 : in STD_ULOGIC;
FBDLY2 : in STD_ULOGIC;
FBDLY3 : in STD_ULOGIC;
FBDLY4 : in STD_ULOGIC;
FBSEL0 : in STD_ULOGIC;
FBSEL1 : in STD_ULOGIC;
XDLYSEL : in STD_ULOGIC;
VCOSEL0 : in STD_ULOGIC;
VCOSEL1 : in STD_ULOGIC;
VCOSEL2 : in STD_ULOGIC;
GLA : out STD_ULOGIC;
LOCK : out STD_ULOGIC;
GLB : out STD_ULOGIC;
YB : out STD_ULOGIC;
GLC : out STD_ULOGIC;
YC : out STD_ULOGIC);
end component;
component CLKBUF port(Y : out std_logic; PAD : in std_logic); end component;
component CLKBUF_LVCMOS18 port(Y : out std_logic; PAD : in std_logic); end component;
component CLKBUF_LVCMOS25 port(Y : out std_logic; PAD : in std_logic); end component;
component CLKBUF_LVCMOS33 port(Y : out std_logic; PAD : in std_logic); end component;
component CLKBUF_LVCMOS5 port(Y : out std_logic; PAD : in std_logic); end component;
component CLKBUF_PCI port(Y : out std_logic; PAD : in std_logic); end component;
component CLKINT port( A : in std_logic; Y :out std_logic); end component;
component PLLINT port( A : in std_logic; Y :out std_logic); end component;
component UJTAG
port(
UTDO : in STD_ULOGIC;
TMS : in STD_ULOGIC;
TDI : in STD_ULOGIC;
TCK : in STD_ULOGIC;
TRSTB : in STD_ULOGIC;
UIREG0 : out STD_ULOGIC;
UIREG1 : out STD_ULOGIC;
UIREG2 : out STD_ULOGIC;
UIREG3 : out STD_ULOGIC;
UIREG4 : out STD_ULOGIC;
UIREG5 : out STD_ULOGIC;
UIREG6 : out STD_ULOGIC;
UIREG7 : out STD_ULOGIC;
UTDI : out STD_ULOGIC;
URSTB : out STD_ULOGIC;
UDRCK : out STD_ULOGIC;
UDRCAP : out STD_ULOGIC;
UDRSH : out STD_ULOGIC;
UDRUPD : out STD_ULOGIC;
TDO : out STD_ULOGIC);
end component;
end;
library ieee;
use ieee.std_logic_1164.all;
entity PLLINT is port(Y : out std_logic; A : in std_logic); end;
architecture rtl of PLLINT is begin Y <= A; end;
library ieee;
use ieee.std_logic_1164.all;
entity CLKINT is port(Y : out std_logic; A : in std_logic); end;
architecture rtl of CLKINT is begin Y <= A; end;
library ieee;
use ieee.std_logic_1164.all;
entity CLKBUF is port(Y : out std_logic; PAD : in std_logic); end;
architecture rtl of CLKBUF is begin Y <= PAD; end;
library ieee;
use ieee.std_logic_1164.all;
entity CLKBUF_PCI is port(Y : out std_logic; PAD : in std_logic); end;
architecture rtl of CLKBUF_PCI is begin Y <= PAD; end;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity RAM4K9 is generic (abits : integer range 9 to 12 := 9);
port(
ADDRA0, ADDRA1, ADDRA2, ADDRA3, ADDRA4, ADDRA5, ADDRA6, ADDRA7,
ADDRA8, ADDRA9, ADDRA10, ADDRA11 : in std_logic;
ADDRB0, ADDRB1, ADDRB2, ADDRB3, ADDRB4, ADDRB5, ADDRB6, ADDRB7,
ADDRB8, ADDRB9, ADDRB10, ADDRB11 : in std_logic;
BLKA, WENA, PIPEA, WMODEA, WIDTHA0, WIDTHA1, WENB, BLKB,
PIPEB, WMODEB, WIDTHB1, WIDTHB0 : in std_logic;
DINA0, DINA1, DINA2, DINA3, DINA4, DINA5, DINA6, DINA7, DINA8 : in std_logic;
DINB0, DINB1, DINB2, DINB3, DINB4, DINB5, DINB6, DINB7, DINB8 : in std_logic;
RESET, CLKA, CLKB : in std_logic;
DOUTA0, DOUTA1, DOUTA2, DOUTA3, DOUTA4, DOUTA5, DOUTA6, DOUTA7, DOUTA8 : out std_logic;
DOUTB0, DOUTB1, DOUTB2, DOUTB3, DOUTB4, DOUTB5, DOUTB6, DOUTB7, DOUTB8 : out std_logic
);
end ;
architecture sim of RAM4K9 is
type dwarrtype is array (9 to 12) of integer;
constant dwarr : dwarrtype := (9, 4, 2, 1);
constant dwidth : integer := dwarr(abits);
subtype memword is std_logic_vector(dwidth-1 downto 0);
type memtype is array (0 to 2**abits-1) of memword;
begin
p1 : process(CLKA, CLKB, RESET)
variable mem : memtype;
variable ra, rb : std_logic_vector(11 downto 0);
variable da, db : std_logic_vector(8 downto 0);
variable qa, qb : std_logic_vector(8 downto 0);
variable qal, qbl : std_logic_vector(8 downto 0);
variable qao, qbo : std_logic_vector(8 downto 0);
begin
if rising_edge(CLKA) then
ra := ADDRA11 & ADDRA10 & ADDRA9 & ADDRA8 & ADDRA7 & ADDRA6 & ADDRA5 &
ADDRA4 & ADDRA3 & ADDRA2 & ADDRA1 & ADDRA0;
da := DINA8 & DINA7 & DINA6 & DINA5 & DINA4 & DINA3 & DINA2 &
DINA1 & DINA0;
if BLKA = '0' then
if not (is_x (ra(abits-1 downto 0))) then
qa(dwidth-1 downto 0) := mem(to_integer(unsigned(ra(abits-1 downto 0))));
else qa := (others => 'X'); end if;
if WENA = '0' and not (is_x (ra(abits-1 downto 0))) then
mem(to_integer(unsigned(ra(abits-1 downto 0)))) := da(dwidth-1 downto 0);
if WMODEA = '1' then qa := da(dwidth-1 downto 0); end if;
end if;
elsif is_x(BLKA) then qa := (others => 'X'); end if;
if PIPEA = '1' then qao := qal; else qao := qa; end if;
qal := qa;
end if;
if reset = '0' then qao := (others => '0'); end if;
(DOUTA8, DOUTA7, DOUTA6, DOUTA5, DOUTA4, DOUTA3, DOUTA2,
DOUTA1, DOUTA0) <= qao;
if rising_edge(CLKB) then
rb := ADDRB11 & ADDRB10 & ADDRB9 & ADDRB8 & ADDRB7 & ADDRB6 & ADDRB5 &
ADDRB4 & ADDRB3 & ADDRB2 & ADDRB1 & ADDRB0;
db := DINB8 & DINB7 & DINB6 & DINB5 & DINB4 & DINB3 & DINB2 &
DINB1 & DINB0;
if BLKB = '0' then
if not (is_x (rb(abits-1 downto 0))) then
qb(dwidth-1 downto 0) := mem(to_integer(unsigned(rb(abits-1 downto 0))));
else qb := (others => 'X'); end if;
if WENB = '0' and not (is_x (rb(abits-1 downto 0))) then
mem(to_integer(unsigned(rb(abits-1 downto 0)))) := db(dwidth-1 downto 0);
if WMODEB = '1' then qb := db(dwidth-1 downto 0); end if;
end if;
elsif is_x(BLKB) then qb := (others => 'X'); end if;
if PIPEB = '1' then qbo := qbl; else qbo := qb; end if;
qbl := qb;
end if;
if reset = '0' then qbo := (others => '0'); end if;
(DOUTB8, DOUTB7, DOUTB6, DOUTB5, DOUTB4, DOUTB3, DOUTB2,
DOUTB1, DOUTB0) <= qbo;
end process;
end;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity RAM512X18 is
port(
RADDR8, RADDR7, RADDR6, RADDR5, RADDR4, RADDR3, RADDR2, RADDR1, RADDR0 : in std_logic;
WADDR8, WADDR7, WADDR6, WADDR5, WADDR4, WADDR3, WADDR2, WADDR1, WADDR0 : in std_logic;
WD17, WD16, WD15, WD14, WD13, WD12, WD11, WD10, WD9,
WD8, WD7, WD6, WD5, WD4, WD3, WD2, WD1, WD0 : in std_logic;
REN, WEN, RESET, RW0, RW1, WW1, WW0, PIPE, RCLK, WCLK : in std_logic;
RD17, RD16, RD15, RD14, RD13, RD12, RD11, RD10, RD9,
RD8, RD7, RD6, RD5, RD4, RD3, RD2, RD1, RD0 : out std_logic
);
end ;
architecture sim of RAM512X18 is
constant abits : integer := 8;
constant dwidth : integer := 18;
subtype memword is std_logic_vector(dwidth-1 downto 0);
type memtype is array (0 to 2**abits-1) of memword;
begin
p1 : process(RCLK, WCLK, RESET)
variable mem : memtype;
variable ra, rb : std_logic_vector(8 downto 0);
variable da : std_logic_vector(17 downto 0);
variable qb : std_logic_vector(17 downto 0);
variable qbl : std_logic_vector(17 downto 0);
variable qbo : std_logic_vector(17 downto 0);
begin
if rising_edge(WCLK) then
ra := '0' & WADDR7 & WADDR6 & WADDR5 &
WADDR4 & WADDR3 & WADDR2 & WADDR1 & WADDR0;
da := WD17 & WD16 & WD15 & WD14 & WD13 & WD12 & WD11 &
Wd10 & WD9 & WD8 & WD7 & WD6 & WD5 & WD4 & WD3 & WD2 &
WD1 & WD0;
if WEN = '0' and not (is_x (ra(abits-1 downto 0))) then
mem(to_integer(unsigned(ra(abits-1 downto 0)))) := da(dwidth-1 downto 0);
end if;
end if;
if rising_edge(RCLK) then
rb := '0' & RADDR7 & RADDR6 & RADDR5 &
RADDR4 & RADDR3 & RADDR2 & RADDR1 & RADDR0;
if REN = '0' then
if not (is_x (rb(abits-1 downto 0))) then
qb := mem(to_integer(unsigned(rb(abits-1 downto 0))));
else qb := (others => 'X'); end if;
elsif is_x(REN) then qb := (others => 'X'); end if;
if PIPE = '1' then qbo := qbl; else qbo := qb; end if;
qbl := qb;
end if;
if RESET = '0' then qbo := (others => '0'); end if;
(RD17, RD16, RD15, RD14, RD13, RD12, RD11, RD10, RD9,
RD8, RD7, RD6, RD5, RD4, RD3, RD2, RD1, RD0) <= qbo;
end process;
end;
library IEEE;
use IEEE.std_logic_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;
-- entity declaration --
entity PLLPRIM is
generic (
VCOFREQUENCY : Real := 0.0;
f_CLKA_LOCK : Integer := 3; -- Number of CLKA pulses after which LOCK is raised
TimingChecksOn : Boolean := True;
InstancePath : String := "*";
Xon : Boolean := False;
MsgOn : Boolean := True;
EMULATED_SYSTEM_DELAY : Time := 2.290 ns; -- Delay Tap Additional CLK delay
IN_DIV_DELAY : Time := 0.335 ns; -- Input Divider intrinsic delay
OUT_DIV_DELAY : Time := 0.770 ns; -- Output Divider intrinsic delay
MUX_DELAY : Time := 1.200 ns; -- MUXA/MUXB/MUXC intrinsic delay
IN_DELAY_BYP1 : Time := 1.523 ns; -- Input delay for CLKDIVDLY bypass mode
BYP_MUX_DELAY : Time := 0.040 ns; -- Bypass MUX intrinsic delay, not used for Ys
GL_DRVR_DELAY : Time := 0.060 ns; -- Global Driver intrinsic delay
Y_DRVR_DELAY : Time := 0.285 ns; -- Y Driver intrinsic delay
FB_MUX_DELAY : Time := 0.145 ns; -- FBSEL MUX intrinsic delay
X_MUX_DELAY : Time := 0.625 ns; -- XDLYSEL MUX intrinsic delay
FIN_LOCK_DELAY : Time := 0.300 ns; -- FIN to LOCK propagation delay
LOCK_OUT_DELAY : Time := 0.120 ns; -- LOCK to OUT propagation delay
PROG_INIT_DELAY : Time := 0.535 ns;
PROG_STEP_INCREMENT : Time := 0.200 ns;
BYP0_CLK_GL : Time := 0.200 ns; -- Intrinsic delay for CLKDLY bypass mode
CLKA_TO_REF_DELAY : Time := 0.395 ns;
tipd_DYNSYNC : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_CLKA : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_EXTFB : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_POWERDOWN : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_CLKB : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_CLKC : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OADIVRST : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OADIVHALF : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OADIV0 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OADIV1 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OADIV2 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OADIV3 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OADIV4 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OAMUX0 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OAMUX1 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OAMUX2 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYGLA0 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYGLA1 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYGLA2 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYGLA3 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYGLA4 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OBDIVRST : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OBDIVHALF : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OBDIV0 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OBDIV1 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OBDIV2 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OBDIV3 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OBDIV4 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OBMUX0 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OBMUX1 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OBMUX2 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYYB0 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYYB1 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYYB2 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYYB3 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYYB4 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYGLB0 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYGLB1 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYGLB2 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYGLB3 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYGLB4 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OCDIVRST : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OCDIVHALF : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OCDIV0 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OCDIV1 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OCDIV2 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OCDIV3 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OCDIV4 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OCMUX0 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OCMUX1 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OCMUX2 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYYC0 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYYC1 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYYC2 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYYC3 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYYC4 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYGLC0 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYGLC1 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYGLC2 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYGLC3 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYGLC4 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_FINDIV0 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_FINDIV1 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_FINDIV2 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_FINDIV3 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_FINDIV4 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_FINDIV5 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_FINDIV6 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_FBDIV0 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_FBDIV1 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_FBDIV2 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_FBDIV3 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_FBDIV4 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_FBDIV5 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_FBDIV6 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_FBDLY0 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_FBDLY1 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_FBDLY2 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_FBDLY3 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_FBDLY4 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_FBSEL0 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_FBSEL1 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_XDLYSEL : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_VCOSEL0 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_VCOSEL1 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_VCOSEL2 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tpd_CLKA_GLA : VitalDelayType01 := ( 0.100 ns, 0.100 ns );
tpd_EXTFB_GLA : VitalDelayType01 := ( 0.100 ns, 0.100 ns );
tpd_POWERDOWN_GLA : VitalDelayType01 := ( 0.100 ns, 0.100 ns );
tpd_CLKA_GLB : VitalDelayType01 := ( 0.100 ns, 0.100 ns );
tpd_EXTFB_GLB : VitalDelayType01 := ( 0.100 ns, 0.100 ns );
tpd_POWERDOWN_GLB : VitalDelayType01 := ( 0.100 ns, 0.100 ns );
tpd_CLKA_GLC : VitalDelayType01 := ( 0.100 ns, 0.100 ns );
tpd_EXTFB_GLC : VitalDelayType01 := ( 0.100 ns, 0.100 ns );
tpd_POWERDOWN_GLC : VitalDelayType01 := ( 0.100 ns, 0.100 ns );
tpd_CLKA_YB : VitalDelayType01 := ( 0.100 ns, 0.100 ns );
tpd_EXTFB_YB : VitalDelayType01 := ( 0.100 ns, 0.100 ns );
tpd_POWERDOWN_YB : VitalDelayType01 := ( 0.100 ns, 0.100 ns );
tpd_CLKA_YC : VitalDelayType01 := ( 0.100 ns, 0.100 ns );
tpd_EXTFB_YC : VitalDelayType01 := ( 0.100 ns, 0.100 ns );
tpd_POWERDOWN_YC : VitalDelayType01 := ( 0.100 ns, 0.100 ns );
tpd_CLKA_LOCK : VitalDelayType01 := ( 0.100 ns, 0.100 ns );
tpd_EXTFB_LOCK : VitalDelayType01 := ( 0.100 ns, 0.100 ns );
tpd_POWERDOWN_LOCK : VitalDelayType01 := ( 0.100 ns, 0.100 ns )
);
port (
DYNSYNC : in std_ulogic;
CLKA : in std_ulogic;
EXTFB : in std_ulogic;
POWERDOWN : in std_ulogic;
CLKB : in std_ulogic;
CLKC : in std_ulogic;
OADIVRST : in std_ulogic;
OADIVHALF : in std_ulogic;
OADIV0 : in std_ulogic;
OADIV1 : in std_ulogic;
OADIV2 : in std_ulogic;
OADIV3 : in std_ulogic;
OADIV4 : in std_ulogic;
OAMUX0 : in std_ulogic;
OAMUX1 : in std_ulogic;
OAMUX2 : in std_ulogic;
DLYGLA0 : in std_ulogic;
DLYGLA1 : in std_ulogic;
DLYGLA2 : in std_ulogic;
DLYGLA3 : in std_ulogic;
DLYGLA4 : in std_ulogic;
OBDIVRST : in std_ulogic;
OBDIVHALF : in std_ulogic;
OBDIV0 : in std_ulogic;
OBDIV1 : in std_ulogic;
OBDIV2 : in std_ulogic;
OBDIV3 : in std_ulogic;
OBDIV4 : in std_ulogic;
OBMUX0 : in std_ulogic;
OBMUX1 : in std_ulogic;
OBMUX2 : in std_ulogic;
DLYYB0 : in std_ulogic;
DLYYB1 : in std_ulogic;
DLYYB2 : in std_ulogic;
DLYYB3 : in std_ulogic;
DLYYB4 : in std_ulogic;
DLYGLB0 : in std_ulogic;
DLYGLB1 : in std_ulogic;
DLYGLB2 : in std_ulogic;
DLYGLB3 : in std_ulogic;
DLYGLB4 : in std_ulogic;
OCDIVRST : in std_ulogic;
OCDIVHALF : in std_ulogic;
OCDIV0 : in std_ulogic;
OCDIV1 : in std_ulogic;
OCDIV2 : in std_ulogic;
OCDIV3 : in std_ulogic;
OCDIV4 : in std_ulogic;
OCMUX0 : in std_ulogic;
OCMUX1 : in std_ulogic;
OCMUX2 : in std_ulogic;
DLYYC0 : in std_ulogic;
DLYYC1 : in std_ulogic;
DLYYC2 : in std_ulogic;
DLYYC3 : in std_ulogic;
DLYYC4 : in std_ulogic;
DLYGLC0 : in std_ulogic;
DLYGLC1 : in std_ulogic;
DLYGLC2 : in std_ulogic;
DLYGLC3 : in std_ulogic;
DLYGLC4 : in std_ulogic;
FINDIV0 : in std_ulogic;
FINDIV1 : in std_ulogic;
FINDIV2 : in std_ulogic;
FINDIV3 : in std_ulogic;
FINDIV4 : in std_ulogic;
FINDIV5 : in std_ulogic;
FINDIV6 : in std_ulogic;
FBDIV0 : in std_ulogic;
FBDIV1 : in std_ulogic;
FBDIV2 : in std_ulogic;
FBDIV3 : in std_ulogic;
FBDIV4 : in std_ulogic;
FBDIV5 : in std_ulogic;
FBDIV6 : in std_ulogic;
FBDLY0 : in std_ulogic;
FBDLY1 : in std_ulogic;
FBDLY2 : in std_ulogic;
FBDLY3 : in std_ulogic;
FBDLY4 : in std_ulogic;
FBSEL0 : in std_ulogic;
FBSEL1 : in std_ulogic;
XDLYSEL : in std_ulogic;
VCOSEL0 : in std_ulogic;
VCOSEL1 : in std_ulogic;
VCOSEL2 : in std_ulogic;
GLA : out std_ulogic;
LOCK : out std_ulogic;
GLB : out std_ulogic;
YB : out std_ulogic;
GLC : out std_ulogic;
YC : out std_ulogic
);
attribute VITAL_LEVEL0 of PLLPRIM : entity is TRUE;
end PLLPRIM;
-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
architecture VITAL_ACT of PLLPRIM is
attribute VITAL_LEVEL1 of VITAL_ACT : architecture is FALSE;
signal DYNSYNC_ipd : std_ulogic;
signal CLKA_ipd : std_ulogic;
signal EXTFB_ipd : std_ulogic;
signal POWERDOWN_ipd : std_ulogic;
signal CLKB_ipd : std_ulogic;
signal CLKC_ipd : std_ulogic;
signal OADIVRST_ipd : std_ulogic;
signal OADIVHALF_ipd : std_ulogic;
signal OADIV0_ipd : std_ulogic;
signal OADIV1_ipd : std_ulogic;
signal OADIV2_ipd : std_ulogic;
signal OADIV3_ipd : std_ulogic;
signal OADIV4_ipd : std_ulogic;
signal OAMUX0_ipd : std_ulogic;
signal OAMUX1_ipd : std_ulogic;
signal OAMUX2_ipd : std_ulogic;
signal DLYGLA0_ipd : std_ulogic;
signal DLYGLA1_ipd : std_ulogic;
signal DLYGLA2_ipd : std_ulogic;
signal DLYGLA3_ipd : std_ulogic;
signal DLYGLA4_ipd : std_ulogic;
signal OBDIVRST_ipd : std_ulogic;
signal OBDIVHALF_ipd : std_ulogic;
signal OBDIV0_ipd : std_ulogic;
signal OBDIV1_ipd : std_ulogic;
signal OBDIV2_ipd : std_ulogic;
signal OBDIV3_ipd : std_ulogic;
signal OBDIV4_ipd : std_ulogic;
signal OBMUX0_ipd : std_ulogic;
signal OBMUX1_ipd : std_ulogic;
signal OBMUX2_ipd : std_ulogic;
signal DLYYB0_ipd : std_ulogic;
signal DLYYB1_ipd : std_ulogic;
signal DLYYB2_ipd : std_ulogic;
signal DLYYB3_ipd : std_ulogic;
signal DLYYB4_ipd : std_ulogic;
signal DLYGLB0_ipd : std_ulogic;
signal DLYGLB1_ipd : std_ulogic;
signal DLYGLB2_ipd : std_ulogic;
signal DLYGLB3_ipd : std_ulogic;
signal DLYGLB4_ipd : std_ulogic;
signal OCDIVRST_ipd : std_ulogic;
signal OCDIVHALF_ipd : std_ulogic;
signal OCDIV0_ipd : std_ulogic;
signal OCDIV1_ipd : std_ulogic;
signal OCDIV2_ipd : std_ulogic;
signal OCDIV3_ipd : std_ulogic;
signal OCDIV4_ipd : std_ulogic;
signal OCMUX0_ipd : std_ulogic;
signal OCMUX1_ipd : std_ulogic;
signal OCMUX2_ipd : std_ulogic;
signal DLYYC0_ipd : std_ulogic;
signal DLYYC1_ipd : std_ulogic;
signal DLYYC2_ipd : std_ulogic;
signal DLYYC3_ipd : std_ulogic;
signal DLYYC4_ipd : std_ulogic;
signal DLYGLC0_ipd : std_ulogic;
signal DLYGLC1_ipd : std_ulogic;
signal DLYGLC2_ipd : std_ulogic;
signal DLYGLC3_ipd : std_ulogic;
signal DLYGLC4_ipd : std_ulogic;
signal FINDIV0_ipd : std_ulogic;
signal FINDIV1_ipd : std_ulogic;
signal FINDIV2_ipd : std_ulogic;
signal FINDIV3_ipd : std_ulogic;
signal FINDIV4_ipd : std_ulogic;
signal FINDIV5_ipd : std_ulogic;
signal FINDIV6_ipd : std_ulogic;
signal FBDIV0_ipd : std_ulogic;
signal FBDIV1_ipd : std_ulogic;
signal FBDIV2_ipd : std_ulogic;
signal FBDIV3_ipd : std_ulogic;
signal FBDIV4_ipd : std_ulogic;
signal FBDIV5_ipd : std_ulogic;
signal FBDIV6_ipd : std_ulogic;
signal FBDLY0_ipd : std_ulogic;
signal FBDLY1_ipd : std_ulogic;
signal FBDLY2_ipd : std_ulogic;
signal FBDLY3_ipd : std_ulogic;
signal FBDLY4_ipd : std_ulogic;
signal FBSEL0_ipd : std_ulogic;
signal FBSEL1_ipd : std_ulogic;
signal XDLYSEL_ipd : std_ulogic;
signal VCOSEL0_ipd : std_ulogic;
signal VCOSEL1_ipd : std_ulogic;
signal VCOSEL2_ipd : std_ulogic;
signal AOUT : std_logic := 'X';
signal BOUT : std_logic := 'X';
signal COUT : std_logic := 'X';
signal PLLCLK : std_logic := 'X'; -- PLL Core Output Clock
-- with DIVN and DIVM applied
signal CLKA_period : Time := 0.000 ns; -- Current CLKA period
signal PLLCLK_pw : Time := 10.0 ns; -- PLLCLK pulse width
signal PLLCLK_period : Time := 10.0 ns;
signal DIVN : Integer := 1; -- Divide by N divisor - range 1 to 128
signal DIVM : Integer := 1; -- Multiply by M multiplier - range 1 to 128
signal DIVU : Integer := 1; -- Divide by U divisor - range 1 to 32
signal DIVV : Integer := 1; -- Divide by V divisor - range 1 to 32
signal DIVW : Integer := 1; -- Divide by W divisor - range 1 to 32
signal fb_loop_div : Integer := 1; -- Total division of feedback loop
signal halveA : std_logic := 'X';
signal halveB : std_logic := 'X';
signal halveC : std_logic := 'X';
signal CLKA2X : std_logic := 'X';
signal CLKB2X : std_logic := 'X';
signal CLKC2X : std_logic := 'X';
signal UIN : std_logic := 'X'; -- Output of MUXA
signal VIN : std_logic := 'X'; -- Output of MUXB
signal WIN : std_logic := 'X'; -- Output of MUXC
signal FBDELAY : Time := 0.000 ns; -- Feedback delay
signal DTDELAY : Time := 0.000 ns; -- Delay Tap delay
signal PLLDELAY : Time := 0.000 ns; -- Sum of Feedback and Delay Tap delays
signal YBDELAY : Time := 0.000 ns; -- Additional Global B Delay
signal GLBDELAY : Time := 0.000 ns; -- Additional Global B Delay
signal YCDELAY : Time := 0.000 ns; -- Additional Global C Delay
signal GLCDELAY : Time := 0.000 ns; -- Additional Global C Delay
signal GLADELAY : Time := 0.000 ns; -- Additional Global A Delay
signal FBSEL : std_logic_vector( 1 downto 0 ) := "XX";
signal FBSEL_illegal : Boolean := False; -- True when FBSEL = 00
signal OAMUX_config : integer := -1;
signal OBMUX_config : integer := -1;
signal OCMUX_config : integer := -1;
signal internal_lock : boolean := false;
signal fin_period : Time := 0.000 ns;
signal extfbin_fin_drift : time := 0 ps;
signal locked : std_logic := '0'; -- 1 when PLL is externally locked as well as internally locked
signal locked_vco0_edges : integer := -1;
signal vco0_divu : std_logic := '0';
signal vco0_divv : std_logic := '0';
signal vco0_divw : std_logic := '0';
signal fin : std_logic := '0';
signal CLKA_period_stable : boolean := false;
signal using_EXTFB : std_logic := 'X';
signal EXTFB_delay_dtrmd : Boolean := false;
signal calibrate_EXTFB_delay : std_logic := '0';
signal GLA_free_running : std_logic := '1';
signal AOUT_using_EXTFB : std_logic := '1';
signal GLA_pw : time := 10.0 ns; -- Only used for external feedback
signal GLA_EXTFB_rise_dly : time := 0.0 ns; -- Only meaningful for external feedback
signal GLA_EXTFB_fall_dly : time := 0.0 ns; -- Only meaningful for external feedback
signal EXTFB_period : time := 20.0 ns; -- Only meaningful for external feedback
signal expected_EXTFB : std_logic := 'X';
signal external_dly_correct : std_logic := 'X';
signal gla_muxed_delay : time := 0.000 ns;
signal glb_muxed_delay : time := 0.000 ns;
signal glc_muxed_delay : time := 0.000 ns;
signal internal_fb_delay : time := 0.000 ns;
signal external_fb_delay : time := 0.000 ns;
signal normalized_fb_delay : time := 0.000 ns; -- Sum of all delays in the feedback loop from VCO to FBIN normalized to be less than or equal to fin period so that no negative delay assignments are made.
signal CLKA_2_GLA_dly : time := 0.000 ns;
signal CLKA_2_GLA_bypass0_dly : time := 0.000 ns;
signal CLKA_2_GLA_bypass1_dly : time := 0.000 ns;
signal CLKA_2_GLB_dly : time := 0.000 ns;
signal CLKB_2_GLB_bypass0_dly : time := 0.000 ns;
signal CLKB_2_GLB_bypass1_dly : time := 0.000 ns;
signal CLKA_2_YB_dly : time := 0.000 ns;
signal CLKB_2_YB_bypass1_dly : time := 0.000 ns;
signal CLKA_2_GLC_dly : time := 0.000 ns;
signal CLKC_2_GLC_bypass0_dly : time := 0.000 ns;
signal CLKC_2_GLC_bypass1_dly : time := 0.000 ns;
signal CLKA_2_YC_dly : time := 0.000 ns;
signal CLKC_2_YC_bypass1_dly : time := 0.000 ns;
signal CLKA_2_LOCK_dly : time := 0.000 ns;
-- Use this instead of CONV_INTEGER to avoid ambiguous warnings
function ulogic2int(
vec : std_ulogic_vector )
return integer is
variable result : integer;
variable i : integer;
begin
result := 0;
for i in vec'range loop
result := result * 2;
if vec(i) = '1' then
result := result + 1;
end if;
end loop;
return result;
end function ulogic2int;
function output_mux_delay(
outmux : integer;
vcobit2 : std_logic;
vcobit1 : std_logic;
fbdly_delay : time;
vco_pw : time )
return time is
variable result : time;
begin
case outmux is
when 1 => result := IN_DELAY_BYP1;
when 2 => result := MUX_DELAY + fbdly_delay;
when 5 => if ( ( vcobit2 = '1') and ( vcobit1 = '1') ) then
result := MUX_DELAY + ( vco_pw / 2.0 );
else
result := MUX_DELAY + ( vco_pw * 1.5 );
end if;
when 6 => result := MUX_DELAY + vco_pw;
when 7 => if ( ( vcobit2 = '1') and ( vcobit1 = '1') ) then
result := MUX_DELAY + ( vco_pw * 1.5 );
else
result := MUX_DELAY + ( vco_pw / 2.0 );
end if;
when others => result := MUX_DELAY;
end case;
return result;
end function output_mux_delay;
function output_mux_driver(
outmux : integer;
halved : std_logic;
bypass : std_logic;
bypass2x : std_logic;
vco : std_logic )
return std_logic is
variable result : std_logic;
begin
case outmux is
when 1 => if ( '1' = halved ) then
result := bypass2x;
elsif ( '0' = halved ) then
result := bypass;
else
result := 'X';
end if;
when 2 => result := vco;
when 4 => result := vco;
when 5 => result := vco;
when 6 => result := vco;
when 7 => result := vco;
when others => result := 'X';
end case;
return result;
end function output_mux_driver;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay ( DYNSYNC_ipd, DYNSYNC, tipd_DYNSYNC );
VitalWireDelay ( CLKA_ipd, CLKA, tipd_CLKA );
VitalWireDelay ( EXTFB_ipd, EXTFB, tipd_EXTFB );
VitalWireDelay ( POWERDOWN_ipd, POWERDOWN, tipd_POWERDOWN );
VitalWireDelay ( CLKB_ipd, CLKB, tipd_CLKB );
VitalWireDelay ( CLKC_ipd, CLKC, tipd_CLKC );
VitalWireDelay ( OADIVRST_ipd, OADIVRST, tipd_OADIVRST );
VitalWireDelay ( OADIVHALF_ipd, OADIVHALF, tipd_OADIVHALF );
VitalWireDelay ( OADIV0_ipd, OADIV0, tipd_OADIV0 );
VitalWireDelay ( OADIV1_ipd, OADIV1, tipd_OADIV1 );
VitalWireDelay ( OADIV2_ipd, OADIV2, tipd_OADIV2 );
VitalWireDelay ( OADIV3_ipd, OADIV3, tipd_OADIV3 );
VitalWireDelay ( OADIV4_ipd, OADIV4, tipd_OADIV4 );
VitalWireDelay ( OAMUX0_ipd, OAMUX0, tipd_OAMUX0 );
VitalWireDelay ( OAMUX1_ipd, OAMUX1, tipd_OAMUX1 );
VitalWireDelay ( OAMUX2_ipd, OAMUX2, tipd_OAMUX2 );
VitalWireDelay ( DLYGLA0_ipd, DLYGLA0, tipd_DLYGLA0 );
VitalWireDelay ( DLYGLA1_ipd, DLYGLA1, tipd_DLYGLA1 );
VitalWireDelay ( DLYGLA2_ipd, DLYGLA2, tipd_DLYGLA2 );
VitalWireDelay ( DLYGLA3_ipd, DLYGLA3, tipd_DLYGLA3 );
VitalWireDelay ( DLYGLA4_ipd, DLYGLA4, tipd_DLYGLA4 );
VitalWireDelay ( OBDIVRST_ipd, OBDIVRST, tipd_OBDIVRST );
VitalWireDelay ( OBDIVHALF_ipd, OBDIVHALF, tipd_OBDIVHALF );
VitalWireDelay ( OBDIV0_ipd, OBDIV0, tipd_OBDIV0 );
VitalWireDelay ( OBDIV1_ipd, OBDIV1, tipd_OBDIV1 );
VitalWireDelay ( OBDIV2_ipd, OBDIV2, tipd_OBDIV2 );
VitalWireDelay ( OBDIV3_ipd, OBDIV3, tipd_OBDIV3 );
VitalWireDelay ( OBDIV4_ipd, OBDIV4, tipd_OBDIV4 );
VitalWireDelay ( OBMUX0_ipd, OBMUX0, tipd_OBMUX0 );
VitalWireDelay ( OBMUX1_ipd, OBMUX1, tipd_OBMUX1 );
VitalWireDelay ( OBMUX2_ipd, OBMUX2, tipd_OBMUX2 );
VitalWireDelay ( DLYYB0_ipd, DLYYB0, tipd_DLYYB0 );
VitalWireDelay ( DLYYB1_ipd, DLYYB1, tipd_DLYYB1 );
VitalWireDelay ( DLYYB2_ipd, DLYYB2, tipd_DLYYB2 );
VitalWireDelay ( DLYYB3_ipd, DLYYB3, tipd_DLYYB3 );
VitalWireDelay ( DLYYB4_ipd, DLYYB4, tipd_DLYYB4 );
VitalWireDelay ( DLYGLB0_ipd, DLYGLB0, tipd_DLYGLB0 );
VitalWireDelay ( DLYGLB1_ipd, DLYGLB1, tipd_DLYGLB1 );
VitalWireDelay ( DLYGLB2_ipd, DLYGLB2, tipd_DLYGLB2 );
VitalWireDelay ( DLYGLB3_ipd, DLYGLB3, tipd_DLYGLB3 );
VitalWireDelay ( DLYGLB4_ipd, DLYGLB4, tipd_DLYGLB4 );
VitalWireDelay ( OCDIVRST_ipd, OCDIVRST, tipd_OCDIVRST );
VitalWireDelay ( OCDIVHALF_ipd, OCDIVHALF, tipd_OCDIVHALF );
VitalWireDelay ( OCDIV0_ipd, OCDIV0, tipd_OCDIV0 );
VitalWireDelay ( OCDIV1_ipd, OCDIV1, tipd_OCDIV1 );
VitalWireDelay ( OCDIV2_ipd, OCDIV2, tipd_OCDIV2 );
VitalWireDelay ( OCDIV3_ipd, OCDIV3, tipd_OCDIV3 );
VitalWireDelay ( OCDIV4_ipd, OCDIV4, tipd_OCDIV4 );
VitalWireDelay ( OCMUX0_ipd, OCMUX0, tipd_OCMUX0 );
VitalWireDelay ( OCMUX1_ipd, OCMUX1, tipd_OCMUX1 );
VitalWireDelay ( OCMUX2_ipd, OCMUX2, tipd_OCMUX2 );
VitalWireDelay ( DLYYC0_ipd, DLYYC0, tipd_DLYYC0 );
VitalWireDelay ( DLYYC1_ipd, DLYYC1, tipd_DLYYC1 );
VitalWireDelay ( DLYYC2_ipd, DLYYC2, tipd_DLYYC2 );
VitalWireDelay ( DLYYC3_ipd, DLYYC3, tipd_DLYYC3 );
VitalWireDelay ( DLYYC4_ipd, DLYYC4, tipd_DLYYC4 );
VitalWireDelay ( DLYGLC0_ipd, DLYGLC0, tipd_DLYGLC0 );
VitalWireDelay ( DLYGLC1_ipd, DLYGLC1, tipd_DLYGLC1 );
VitalWireDelay ( DLYGLC2_ipd, DLYGLC2, tipd_DLYGLC2 );
VitalWireDelay ( DLYGLC3_ipd, DLYGLC3, tipd_DLYGLC3 );
VitalWireDelay ( DLYGLC4_ipd, DLYGLC4, tipd_DLYGLC4 );
VitalWireDelay ( FINDIV0_ipd, FINDIV0, tipd_FINDIV0 );
VitalWireDelay ( FINDIV1_ipd, FINDIV1, tipd_FINDIV1 );
VitalWireDelay ( FINDIV2_ipd, FINDIV2, tipd_FINDIV2 );
VitalWireDelay ( FINDIV3_ipd, FINDIV3, tipd_FINDIV3 );
VitalWireDelay ( FINDIV4_ipd, FINDIV4, tipd_FINDIV4 );
VitalWireDelay ( FINDIV5_ipd, FINDIV5, tipd_FINDIV5 );
VitalWireDelay ( FINDIV6_ipd, FINDIV6, tipd_FINDIV6 );
VitalWireDelay ( FBDIV0_ipd, FBDIV0, tipd_FBDIV0 );
VitalWireDelay ( FBDIV1_ipd, FBDIV1, tipd_FBDIV1 );
VitalWireDelay ( FBDIV2_ipd, FBDIV2, tipd_FBDIV2 );
VitalWireDelay ( FBDIV3_ipd, FBDIV3, tipd_FBDIV3 );
VitalWireDelay ( FBDIV4_ipd, FBDIV4, tipd_FBDIV4 );
VitalWireDelay ( FBDIV5_ipd, FBDIV5, tipd_FBDIV5 );
VitalWireDelay ( FBDIV6_ipd, FBDIV6, tipd_FBDIV6 );
VitalWireDelay ( FBDLY0_ipd, FBDLY0, tipd_FBDLY0 );
VitalWireDelay ( FBDLY1_ipd, FBDLY1, tipd_FBDLY1 );
VitalWireDelay ( FBDLY2_ipd, FBDLY2, tipd_FBDLY2 );
VitalWireDelay ( FBDLY3_ipd, FBDLY3, tipd_FBDLY3 );
VitalWireDelay ( FBDLY4_ipd, FBDLY4, tipd_FBDLY4 );
VitalWireDelay ( FBSEL0_ipd, FBSEL0, tipd_FBSEL0 );
VitalWireDelay ( FBSEL1_ipd, FBSEL1, tipd_FBSEL1 );
VitalWireDelay ( XDLYSEL_ipd, XDLYSEL, tipd_XDLYSEL );
VitalWireDelay ( VCOSEL0_ipd, VCOSEL0, tipd_VCOSEL0 );
VitalWireDelay ( VCOSEL1_ipd, VCOSEL1, tipd_VCOSEL1 );
VitalWireDelay ( VCOSEL2_ipd, VCOSEL2, tipd_VCOSEL2 );
end block WireDelay;
-- #########################################################
-- # Behavior Section
-- #########################################################
OAMUX_config <= ulogic2int( OAMUX2_ipd & OAMUX1_ipd & OAMUX0_ipd );
OBMUX_config <= ulogic2int( OBMUX2_ipd & OBMUX1_ipd & OBMUX0_ipd );
OCMUX_config <= ulogic2int( OCMUX2_ipd & OCMUX1_ipd & OCMUX0_ipd );
FBSEL <= TO_X01( FBSEL1_ipd & FBSEL0_ipd );
CLKA_2_GLA_dly <= CLKA_TO_REF_DELAY + IN_DIV_DELAY + fin_period - normalized_fb_delay + gla_muxed_delay + OUT_DIV_DELAY + BYP_MUX_DELAY + GLADELAY + GL_DRVR_DELAY;
CLKA_2_GLA_bypass0_dly <= BYP0_CLK_GL + GLADELAY;
CLKA_2_GLA_bypass1_dly <= gla_muxed_delay + OUT_DIV_DELAY + BYP_MUX_DELAY + GLADELAY + GL_DRVR_DELAY;
CLKA_2_GLB_dly <= CLKA_TO_REF_DELAY + IN_DIV_DELAY + fin_period - normalized_fb_delay + glb_muxed_delay + OUT_DIV_DELAY + BYP_MUX_DELAY + GLBDELAY + GL_DRVR_DELAY;
CLKB_2_GLB_bypass0_dly <= BYP0_CLK_GL + GLBDELAY;
CLKB_2_GLB_bypass1_dly <= glb_muxed_delay + OUT_DIV_DELAY + BYP_MUX_DELAY + GLBDELAY + GL_DRVR_DELAY;
CLKA_2_YB_dly <= CLKA_TO_REF_DELAY + IN_DIV_DELAY + fin_period - normalized_fb_delay + glb_muxed_delay + OUT_DIV_DELAY + YBDELAY + Y_DRVR_DELAY;
CLKB_2_YB_bypass1_dly <= glb_muxed_delay + OUT_DIV_DELAY + YBDELAY + Y_DRVR_DELAY;
CLKA_2_GLC_dly <= CLKA_TO_REF_DELAY + IN_DIV_DELAY + fin_period - normalized_fb_delay + glc_muxed_delay + OUT_DIV_DELAY + BYP_MUX_DELAY + GLCDELAY + GL_DRVR_DELAY;
CLKC_2_GLC_bypass0_dly <= BYP0_CLK_GL + GLCDELAY;
CLKC_2_GLC_bypass1_dly <= glc_muxed_delay + OUT_DIV_DELAY + BYP_MUX_DELAY + GLCDELAY + GL_DRVR_DELAY;
CLKA_2_YC_dly <= CLKA_TO_REF_DELAY + IN_DIV_DELAY + fin_period - normalized_fb_delay + glc_muxed_delay + OUT_DIV_DELAY + YCDELAY + Y_DRVR_DELAY;
CLKC_2_YC_bypass1_dly <= glc_muxed_delay + OUT_DIV_DELAY + YCDELAY + Y_DRVR_DELAY;
CLKA_2_LOCK_dly <= CLKA_TO_REF_DELAY + IN_DIV_DELAY + fin_period - normalized_fb_delay + LOCK_OUT_DELAY;
delay_LOCK: process( locked )
begin
if ( '1' = locked ) then
LOCK <= transport locked after CLKA_2_LOCK_dly;
else
LOCK <= locked;
end if;
end process delay_LOCK;
Deskew : process ( XDLYSEL_ipd )
variable DelayVal : Time := 0.000 ns;
begin
if (XDLYSEL_ipd = '1') then
DelayVal := EMULATED_SYSTEM_DELAY;
else
DelayVal := 0.0 ns;
end if;
DTDELAY <= DelayVal;
end process Deskew;
GetFBDelay : process ( FBDLY0_ipd, FBDLY1_ipd, FBDLY2_ipd, FBDLY3_ipd, FBDLY4_ipd )
variable step : integer;
begin
step := ulogic2int( FBDLY4_ipd & FBDLY3_ipd & FBDLY2_ipd & FBDLY1_ipd & FBDLY0_ipd );
FBDELAY <= ( step * PROG_STEP_INCREMENT ) + PROG_INIT_DELAY;
end process GetFBDelay;
GetGLBDelay : process ( DLYGLB0_ipd, DLYGLB1_ipd, DLYGLB2_ipd, DLYGLB3_ipd, DLYGLB4_ipd )
variable step : integer;
begin
step := ulogic2int( DLYGLB4_ipd & DLYGLB3_ipd & DLYGLB2_ipd & DLYGLB1_ipd & DLYGLB0_ipd );
if ( step = 0 ) then
GLBDELAY <= 0.0 ns;
else
GLBDELAY <= ( step * PROG_STEP_INCREMENT ) + PROG_INIT_DELAY;
end if;
end process GetGLBDelay;
GetYBDelay : process ( DLYYB0_ipd, DLYYB1_ipd, DLYYB2_ipd, DLYYB3_ipd, DLYYB4_ipd )
variable step : integer;
begin
step := ulogic2int( DLYYB4_ipd & DLYYB3_ipd & DLYYB2_ipd & DLYYB1_ipd & DLYYB0_ipd );
YBDELAY <= ( step * PROG_STEP_INCREMENT ) + PROG_INIT_DELAY;
end process GetYBDelay;
GetGLCDelay : process ( DLYGLC0_ipd, DLYGLC1_ipd, DLYGLC2_ipd, DLYGLC3_ipd, DLYGLC4_ipd )
variable step : integer;
begin
step := ulogic2int( DLYGLC4_ipd & DLYGLC3_ipd & DLYGLC2_ipd & DLYGLC1_ipd & DLYGLC0_ipd );
if ( step = 0 ) then
GLCDELAY <= 0.0 ns;
else
GLCDELAY <= ( step * PROG_STEP_INCREMENT ) + PROG_INIT_DELAY;
end if;
end process GetGLCDelay;
GetYCDelay : process ( DLYYC0_ipd, DLYYC1_ipd, DLYYC2_ipd, DLYYC3_ipd, DLYYC4_ipd )
variable step : integer;
begin
step := ulogic2int( DLYYC4_ipd & DLYYC3_ipd & DLYYC2_ipd & DLYYC1_ipd & DLYYC0_ipd );
YCDELAY <= ( step * PROG_STEP_INCREMENT ) + PROG_INIT_DELAY;
end process GetYCDelay;
GetGLADelay : process ( DLYGLA0_ipd, DLYGLA1_ipd, DLYGLA2_ipd, DLYGLA3_ipd, DLYGLA4_ipd )
variable step : integer;
begin
step := ulogic2int( DLYGLA4_ipd & DLYGLA3_ipd & DLYGLA2_ipd & DLYGLA1_ipd & DLYGLA0_ipd );
if ( step = 0 ) then
GLADELAY <= 0.0 ns;
else
GLADELAY <= ( step * PROG_STEP_INCREMENT ) + PROG_INIT_DELAY;
end if;
end process GetGLADelay;
DIVM <= ulogic2int( FBDIV6_ipd & FBDIV5_ipd & FBDIV4_ipd & FBDIV3_ipd &
FBDIV2_ipd & FBDIV1_ipd & FBDIV0_ipd ) + 1;
DIVN <= ulogic2int( FINDIV6_ipd & FINDIV5_ipd & FINDIV4_ipd & FINDIV3_ipd &
FINDIV2_ipd & FINDIV1_ipd & FINDIV0_ipd ) + 1;
DIVU <= ulogic2int( OADIV4_ipd & OADIV3_ipd & OADIV2_ipd & OADIV1_ipd & OADIV0_ipd ) + 1;
DIVV <= ulogic2int( OBDIV4_ipd & OBDIV3_ipd & OBDIV2_ipd & OBDIV1_ipd & OBDIV0_ipd ) + 1;
DIVW <= ulogic2int( OCDIV4_ipd & OCDIV3_ipd & OCDIV2_ipd & OCDIV1_ipd & OCDIV0_ipd ) + 1;
check_OADIVHALF : process
begin
wait on OADIVHALF_ipd, DIVU, OAMUX_config;
if ( '1' = TO_X01( OADIVHALF_ipd ) ) then
if ( 1 /= OAMUX_config ) then
assert false
report "Illegal configuration. OADIVHALF can only be used when OAMUX = 001. OADIVHALF ignored."
severity warning;
halveA <= '0';
elsif ( ( DIVU < 3 ) or ( DIVU > 29 ) or ( ( DIVU mod 2 ) /= 1 ) ) then
assert false
report "Illegal configuration. Only even OADIV values from 2 to 28 (inclusive) are allowed with OADIVHALF."
severity warning;
halveA <= 'X';
else
halveA <= '1';
end if;
elsif ( OADIVHALF_ipd'event and ( 'X' = TO_X01( OADIVHALF_ipd ) ) ) then
assert false
report "OADIVHALF unknown."
severity warning;
halveA <= 'X';
else
halveA <= '0';
end if;
end process check_OADIVHALF;
check_OBDIVHALF : process
begin
wait on OBDIVHALF_ipd, DIVV, OBMUX_config;
if ( '1' = TO_X01( OBDIVHALF_ipd ) ) then
if ( 1 /= OBMUX_config ) then
assert false
report "Illegal configuration. OBDIVHALF can only be used when OBMUX = 001. OBDIVHALF ignored."
severity warning;
halveB <= '0';
elsif ( ( DIVV < 3 ) or ( DIVV > 29 ) or ( ( DIVV mod 2 ) /= 1 ) ) then
assert false
report "Illegal configuration. Only even OBDIV values from 2 to 28 (inclusive) are allowed with OBDIVHALF."
severity warning;
halveB <= 'X';
else
halveB <= '1';
end if;
elsif ( OBDIVHALF_ipd'event and ( 'X' = TO_X01( OBDIVHALF_ipd ) ) ) then
assert false
report "OBDIVHALF unknown."
severity warning;
halveB <= 'X';
else
halveB <= '0';
end if;
end process check_OBDIVHALF;
check_OCDIVHALF : process
begin
wait on OCDIVHALF_ipd, DIVW, OCMUX_config;
if ( '1' = TO_X01( OCDIVHALF_ipd ) ) then
if ( 1 /= OCMUX_config ) then
assert false
report "Illegal configuration. OCDIVHALF can only be used when OCMUX = 001. OCDIVHALF ignored."
severity warning;
halveC <= '0';
elsif ( ( DIVW < 3 ) or ( DIVW > 29 ) or ( ( DIVW mod 2 ) /= 1 ) ) then
assert false
report "Illegal configuration. Only even OCDIV values from 2 to 28 (inclusive) are allowed with OCDIVHALF."
severity warning;
halveC <= 'X';
else
halveC <= '1';
end if;
elsif ( OCDIVHALF_ipd'event and ( 'X' = TO_X01( OCDIVHALF_ipd ) ) ) then
assert false
report "OCDIVHALF unknown."
severity warning;
halveC <= 'X';
else
halveC <= '0';
end if;
end process check_OCDIVHALF;
gla_muxed_delay <= output_mux_delay( OAMUX_config, VCOSEL2_ipd, VCOSEL1_ipd, FBDELAY, PLLCLK_pw );
glb_muxed_delay <= output_mux_delay( OBMUX_config, VCOSEL2_ipd, VCOSEL1_ipd, FBDELAY, PLLCLK_pw );
glc_muxed_delay <= output_mux_delay( OCMUX_config, VCOSEL2_ipd, VCOSEL1_ipd, FBDELAY, PLLCLK_pw );
get_internal_fb_dly : process( FBSEL, FBDELAY, DTDELAY, fin_period )
variable fb_delay : time;
begin
fb_delay := IN_DIV_DELAY + X_MUX_DELAY + DTDELAY + FB_MUX_DELAY;
if ( "10" = FBSEL ) then
fb_delay := fb_delay + FBDELAY;
end if;
internal_fb_delay <= fb_delay;
end process get_internal_fb_dly;
external_fb_delay <= IN_DIV_DELAY + X_MUX_DELAY + DTDELAY + FB_MUX_DELAY + GL_DRVR_DELAY + GLADELAY + BYP_MUX_DELAY + OUT_DIV_DELAY + gla_muxed_delay + GLA_EXTFB_rise_dly;
normalize_fb_dly : process( using_EXTFB, internal_fb_delay, external_fb_delay, fin_period )
variable norm : time;
begin
if ( using_EXTFB = '1' ) then
norm := external_fb_delay;
else
norm := internal_fb_delay;
end if;
if ( 0 ns >= fin_period ) then
norm := 0 ns;
else
while ( norm > fin_period ) loop
norm := norm - fin_period;
end loop;
end if;
normalized_fb_delay <= norm;
end process normalize_fb_dly;
check_FBSEL : process
begin
wait on FBSEL, OAMUX_config, OBMUX_config, OCMUX_config, DIVM, DIVU, DIVN, CLKA_period_stable, PLLCLK_period, external_fb_delay;
if ( IS_X( FBSEL ) ) then
FBSEL_illegal <= true;
assert ( not FBSEL'event )
report "Warning: FBSEL is unknown."
severity Warning;
elsif ( "00" = FBSEL ) then -- Grounded.
FBSEL_illegal <= true;
assert ( not FBSEL'event )
report "Warning: Illegal FBSEL configuration 00."
severity Warning;
elsif ( "11" = FBSEL ) then -- External feedback
if ( 2 > OAMUX_config ) then
FBSEL_illegal <= true;
assert ( not ( FBSEL'event or OAMUX_config'event ) )
report "Illegal configuration. GLA cannot be in bypass mode (OAMUX = 000 or OAMUX = 001) when using external feedback (FBSEL = 11)."
severity Warning;
elsif ( DIVM < 5 ) then
FBSEL_illegal <= true;
assert ( not ( FBSEL'event or DIVM'event ) )
report "Error: FBDIV must be greater than 4 when using external feedback (FBSEL = 11)."
severity Error;
elsif ( ( DIVM * DIVU ) > 232 ) then
FBSEL_illegal <= true;
assert ( not ( FBSEL'event or DIVM'event or DIVU'event ) )
report "Error: Product of FBDIV and OADIV must be less than 233 when using external feedback (FBSEL = 11)."
severity Error;
elsif ( ( DIVN mod DIVU ) /= 0 ) then
FBSEL_illegal <= true;
assert ( not ( FBSEL'event or DIVN'event or DIVU'event ) )
report "Error: Division factor FINDIV must be a multiple of OADIV when using external feedback (FBSEL = 11)."
severity Error;
elsif ( CLKA_period_stable and EXTFB_delay_dtrmd and
( ( 1 < OBMUX_config ) or ( 1 < OCMUX_config ) ) and
( ( external_fb_delay >= CLKA_period ) or ( external_fb_delay >= PLLCLK_period ) ) ) then
FBSEL_illegal <= true;
assert ( not ( FBSEL'event or CLKA_period_stable'event or external_fb_delay'event or PLLCLK_period'event ) )
report "Error: Total sum of delays in the feedback path must be less than 1 VCO period AND less than 1 CLKA period when V and/or W dividers when using external feedback (FBSEL = 11)."
severity Error;
else
FBSEL_illegal <= false;
end if;
else
FBSEL_illegal <= false;
end if;
end process check_FBSEL;
-- Mimicing silicon - no need for a 50/50 duty cycle and this way fin only changes on rising edge of CLKA (except when DIVN is 1)
gen_fin: process
variable num_CLKA_re : integer;
begin
wait until rising_edge( CLKA_ipd );
fin <= '1';
num_CLKA_re := 0;
while ( 'X' /= TO_X01( CLKA_ipd ) ) loop
wait on CLKA_ipd;
if ( 1 = DIVN )then
fin <= CLKA_ipd;
elsif ( '1' = CLKA_ipd ) then
num_CLKA_re := num_CLKA_re + 1;
if ( ( num_CLKA_re mod DIVN ) = 0 ) then
fin <= '1';
num_CLKA_re := 0;
elsif ( ( num_CLKA_re mod DIVN ) = 1 ) then
fin <= '0';
end if;
end if;
end loop;
end process gen_fin;
GetCLKAPeriod : process ( CLKA_ipd, POWERDOWN_ipd, FBSEL_illegal, normalized_fb_delay, DIVN, DIVM, locked_vco0_edges, external_dly_correct )
-- locked_vco0_edges is in the sensitivity list so that we periodically check for CLKA stopped
variable re : Time := 0.000 ns; -- Current CLKA rising edge
variable CLKA_num_re_stable : Integer := -1; -- Number of CLKA rising edges that PLL config stable
begin
if (( TO_X01( POWERDOWN_ipd ) = '1' ) and ( FBSEL_illegal = False )) then
if ( normalized_fb_delay'event or DIVN'event or DIVM'event or
( ( '1' = using_EXTFB ) and ( '1' /= external_dly_correct ) ) ) then
internal_lock <= false;
CLKA_num_re_stable := -1;
end if;
if ( CLKA_ipd'event and ( '1' = TO_X01( CLKA_ipd ) ) ) then
if ( CLKA_period /= ( NOW - re ) ) then
CLKA_period <= ( NOW - re );
CLKA_num_re_stable := -1;
internal_lock <= false;
CLKA_period_stable <= false;
else
if ( f_CLKA_LOCK > CLKA_num_re_stable ) then
CLKA_num_re_stable := CLKA_num_re_stable + 1;
elsif ( f_CLKA_LOCK = CLKA_num_re_stable ) then
internal_lock <= true;
end if;
CLKA_period_stable <= true;
end if;
re := NOW;
elsif ( CLKA_period < ( NOW - re ) ) then
CLKA_num_re_stable := -1;
internal_lock <= false;
CLKA_period_stable <= false;
end if;
else
CLKA_num_re_stable := -1;
internal_lock <= false;
CLKA_period_stable <= false;
end if;
end process GetCLKAPeriod;
fin_period <= CLKA_period * DIVN;
GLA_pw <= PLLCLK_pw * DIVU;
extfbin_fin_drift <= ( GLA_pw * DIVM * 2.0 ) - fin_period;
PLLCLK_period <= fin_period / real( fb_loop_div );
PLLCLK_pw <= PLLCLK_period / 2.0;
calc_fb_loop_div : process( DIVM, DIVU, using_EXTFB )
begin
if ( using_EXTFB = '1' ) then
fb_loop_div <= DIVM * DIVU;
else
fb_loop_div <= DIVM;
end if;
end process calc_fb_loop_div;
sync_pll : process( fin, internal_lock, DYNSYNC )
begin
if ( not( internal_lock ) or ( '1' = DYNSYNC ) ) then
locked <= '0';
elsif ( rising_edge( fin ) ) then
locked <= '1';
end if;
end process sync_pll;
count_locked_vco0_edges: process( locked, locked_vco0_edges )
begin
if ( locked'event ) then
if ( locked = '1' ) then
locked_vco0_edges <= 0;
else
locked_vco0_edges <= -1;
end if;
elsif ( locked = '1' ) then
if ( ( locked_vco0_edges mod( DIVU * DIVV * DIVW * DIVM * 2 ) ) = 0 ) then
locked_vco0_edges <= 1 after PLLCLK_pw;
else
locked_vco0_edges <= ( locked_vco0_edges + 1 ) after PLLCLK_pw;
end if;
end if;
end process count_locked_vco0_edges;
gen_vco0_div: process( locked_vco0_edges )
begin
if ( locked_vco0_edges = -1 ) then
vco0_divu <= '0';
vco0_divv <= '0';
vco0_divw <= '0';
else
if ( ( locked_vco0_edges mod DIVU ) = 0 ) then
vco0_divu <= not vco0_divu;
end if;
if ( ( locked_vco0_edges mod DIVV ) = 0 ) then
vco0_divv <= not vco0_divv;
end if;
if ( ( locked_vco0_edges mod DIVW ) = 0 ) then
vco0_divw <= not vco0_divw;
end if;
end if;
end process gen_vco0_div;
UIN <= output_mux_driver( OAMUX_config, halveA, CLKA_ipd, CLKA2X, vco0_divu );
VIN <= output_mux_driver( OBMUX_config, halveB, CLKB_ipd, CLKB2X, vco0_divv );
WIN <= output_mux_driver( OCMUX_config, halveC, CLKC_ipd, CLKC2X, vco0_divw );
double_CLKA: process( CLKA_ipd )
variable re : Time := 0 ns;
variable prev_re : Time := 0 ns;
variable period : Time := 0 ns;
begin
if ( TO_X01( CLKA_ipd ) = '1' ) then
prev_re := re;
re := NOW;
period := re - prev_re;
if ( period > 0 ns ) then
CLKA2X <= '1';
CLKA2X <= transport '0' after ( period / 4.0 );
CLKA2X <= transport '1' after ( period / 2.0 );
CLKA2X <= transport '0' after ( period * 3.0 / 4.0 );
end if;
end if;
end process double_CLKA;
double_CLKB: process( CLKB_ipd )
variable re : Time := 0 ns;
variable prev_re : Time := 0 ns;
variable period : Time := 0 ns;
begin
if ( TO_X01( CLKB_ipd ) = '1' ) then
prev_re := re;
re := NOW;
period := re - prev_re;
if ( period > 0 ns ) then
CLKB2X <= '1';
CLKB2X <= transport '0' after ( period / 4.0 );
CLKB2X <= transport '1' after ( period / 2.0 );
CLKB2X <= transport '0' after ( period * 3.0 / 4.0 );
end if;
end if;
end process double_CLKB;
double_CLKC: process( CLKC_ipd )
variable re : Time := 0 ns;
variable prev_re : Time := 0 ns;
variable period : Time := 0 ns;
begin
if ( TO_X01( CLKC_ipd ) = '1' ) then
prev_re := re;
re := NOW;
period := re - prev_re;
if ( period > 0 ns ) then
CLKC2X <= '1';
CLKC2X <= transport '0' after ( period / 4.0 );
CLKC2X <= transport '1' after ( period / 2.0 );
CLKC2X <= transport '0' after ( period * 3.0 / 4.0 );
end if;
end if;
end process double_CLKC;
--
-- AOUT Output of Divider U
--
DividerU : process ( UIN, CLKA_ipd, OADIVRST_ipd, OADIVHALF_ipd,
POWERDOWN_ipd )
variable force_0 : Boolean := True;
variable num_edges : Integer := -1;
variable res_post_reset1 : Integer := 0;
variable fes_post_reset1 : Integer := 0;
variable res_post_reset0 : Integer := 0;
variable fes_post_reset0 : Integer := 0;
begin
if ( 1 = OAMUX_config ) then -- PLL core bypassed. OADIVRST active.
if ( CLKA_ipd'event ) then
if ( TO_X01( CLKA_ipd ) = '1' and TO_X01( CLKA_ipd'last_value ) = '0' ) then
if ( 4 > res_post_reset1 ) then
res_post_reset1 := res_post_reset1 + 1;
end if;
if ( 4 > res_post_reset0 ) then
res_post_reset0 := res_post_reset0 + 1;
end if;
if ( res_post_reset1 = 3 ) then
force_0 := False;
num_edges := -1;
end if;
elsif ( TO_X01( CLKA_ipd ) = '0' and TO_X01( CLKA_ipd'last_value ) = '1' ) then
if ( 4 > fes_post_reset1 ) then
fes_post_reset1 := fes_post_reset1 + 1;
end if;
if ( 4 > fes_post_reset0 ) then
fes_post_reset0 := fes_post_reset0 + 1;
end if;
if ( fes_post_reset1 = 1 ) then
force_0 := True;
end if;
end if;
end if;
if ( OADIVRST_ipd'event ) then
if ( TO_X01( OADIVRST_ipd ) = '1' ) then
if ( ( TO_X01( OADIVRST_ipd'last_value ) = '0' ) and
( ( res_post_reset0 < 1 ) or ( fes_post_reset0 < 1 ) ) ) then
assert false
report "OADIVRST must be held low for at least one CLKA period for the reset operation to work correctly: reset operation may not be successful, edge alignment unpredictable"
severity warning;
end if;
res_post_reset1 := 0;
fes_post_reset1 := 0;
elsif ( TO_X01( OADIVRST_ipd ) = '0' ) then
if ( ( TO_X01( OADIVRST_ipd'last_value ) = '1' ) and
( ( res_post_reset1 < 3 ) or ( fes_post_reset1 < 3 ) ) ) then
assert false
report "OADIVRST must be held high for at least three CLKA periods for the reset operation to work correctly: reset operation may not be succesful, edge alignment unpredictable"
severity warning;
end if;
res_post_reset0 := 0;
fes_post_reset0 := 0;
else
assert false
report "OADIVRST is unknown. Edge alignment unpredictable."
severity warning;
end if;
end if;
if ( UIN'event ) then
num_edges := num_edges + 1;
if ( force_0 ) then
AOUT <= '0';
elsif ( TO_X01( UIN ) = 'X' ) then
AOUT <= 'X';
elsif ( ( num_edges mod DIVU ) = 0 ) then
num_edges := 0;
if ( TO_X01 ( AOUT ) = 'X' ) then
AOUT <= UIN;
else
AOUT <= not AOUT;
end if;
end if;
end if;
else -- PLL not bypassed
if ( TO_X01 ( POWERDOWN_ipd ) = '0' ) then
AOUT <= '0';
elsif ( TO_X01 ( POWERDOWN_ipd ) = '1' ) then
AOUT <= UIN;
else -- POWERDOWN unknown
AOUT <= 'X';
end if;
end if;
end process DividerU;
--
-- BOUT Output of Divider V
--
DividerV : process ( VIN, CLKB_ipd, OBDIVRST_ipd, OBDIVHALF_ipd,
POWERDOWN_ipd )
variable force_0 : Boolean := True;
variable num_edges : Integer := -1;
variable res_post_reset1 : Integer := 0;
variable fes_post_reset1 : Integer := 0;
variable res_post_reset0 : Integer := 0;
variable fes_post_reset0 : Integer := 0;
begin
if ( 0 = OBMUX_config ) then
BOUT <= 'X';
elsif ( 1 = OBMUX_config ) then -- PLL core bypassed. OBDIVRST active.
if ( CLKB_ipd'event ) then
if ( TO_X01( CLKB_ipd ) = '1' and TO_X01( CLKB_ipd'last_value ) = '0' ) then
if ( 4 > res_post_reset1 ) then
res_post_reset1 := res_post_reset1 + 1;
end if;
if ( 4 > res_post_reset0 ) then
res_post_reset0 := res_post_reset0 + 1;
end if;
if ( res_post_reset1 = 3 ) then
force_0 := False;
num_edges := -1;
end if;
elsif ( TO_X01( CLKB_ipd ) = '0' and TO_X01( CLKB_ipd'last_value ) = '1' ) then
if ( 4 > fes_post_reset1 ) then
fes_post_reset1 := fes_post_reset1 + 1;
end if;
if ( 4 > fes_post_reset0 ) then
fes_post_reset0 := fes_post_reset0 + 1;
end if;
if ( fes_post_reset1 = 1 ) then
force_0 := True;
end if;
end if;
end if;
if ( OBDIVRST_ipd'event ) then
if ( TO_X01( OBDIVRST_ipd ) = '1' ) then
if ( ( TO_X01( OBDIVRST_ipd'last_value ) = '0' ) and
( ( res_post_reset0 < 1 ) or ( fes_post_reset0 < 1 ) ) ) then
assert false
report "OBDIVRST must be held low for at least one CLKB period for the reset operation to work correctly: reset operation may not be successful, edge alignment unpredictable"
severity warning;
end if;
res_post_reset1 := 0;
fes_post_reset1 := 0;
elsif ( TO_X01( OBDIVRST_ipd ) = '0' ) then
if ( ( TO_X01( OBDIVRST_ipd'last_value ) = '1' ) and
( ( res_post_reset1 < 3 ) or ( fes_post_reset1 < 3 ) ) ) then
assert false
report "OBDIVRST must be held high for at least three CLKB periods for the reset operation to work correctly: reset operation may not be succesful, edge alignment unpredictable"
severity warning;
end if;
res_post_reset0 := 0;
fes_post_reset0 := 0;
else
assert false
report "OBDIVRST is unknown. Edge alignment unpredictable."
severity warning;
end if;
end if;
if ( VIN'event ) then
num_edges := num_edges + 1;
if ( force_0 ) then
BOUT <= '0';
elsif ( TO_X01( VIN ) = 'X' ) then
BOUT <= 'X';
elsif ( ( num_edges mod DIVV ) = 0 ) then
num_edges := 0;
if ( TO_X01 ( BOUT ) = 'X' ) then
BOUT <= VIN;
else
BOUT <= not BOUT;
end if;
end if;
end if;
else -- PLL not bypassed
if ( TO_X01 ( POWERDOWN_ipd ) = '0' ) then
BOUT <= '0';
elsif ( TO_X01 ( POWERDOWN_ipd ) = '1' ) then
BOUT <= VIN;
else -- POWERDOWN unknown
BOUT <= 'X';
end if;
end if;
end process DividerV;
--
-- COUT Output of Divider W
--
DividerW : process ( WIN, CLKC_ipd, OCDIVRST_ipd, OCDIVHALF_ipd,
POWERDOWN_ipd )
variable force_0 : Boolean := True;
variable num_edges : Integer := -1;
variable res_post_reset1 : Integer := 0;
variable fes_post_reset1 : Integer := 0;
variable res_post_reset0 : Integer := 0;
variable fes_post_reset0 : Integer := 0;
begin
if ( 0 = OCMUX_config ) then
COUT <= 'X';
elsif ( 1 = OCMUX_config ) then -- PLL core bypassed. OCDIVRST active.
if ( CLKC_ipd'event ) then
if ( TO_X01( CLKC_ipd ) = '1' and TO_X01( CLKC_ipd'last_value ) = '0' ) then
if ( 4 > res_post_reset1 ) then
res_post_reset1 := res_post_reset1 + 1;
end if;
if ( 4 > res_post_reset0 ) then
res_post_reset0 := res_post_reset0 + 1;
end if;
if ( res_post_reset1 = 3 ) then
force_0 := False;
num_edges := -1;
end if;
elsif ( TO_X01( CLKC_ipd ) = '0' and TO_X01( CLKC_ipd'last_value ) = '1' ) then
if ( 4 > fes_post_reset1 ) then
fes_post_reset1 := fes_post_reset1 + 1;
end if;
if ( 4 > fes_post_reset0 ) then
fes_post_reset0 := fes_post_reset0 + 1;
end if;
if ( fes_post_reset1 = 1 ) then
force_0 := True;
end if;
end if;
end if;
if ( OCDIVRST_ipd'event ) then
if ( TO_X01( OCDIVRST_ipd ) = '1' ) then
if ( ( TO_X01( OCDIVRST_ipd'last_value ) = '0' ) and
( ( res_post_reset0 < 1 ) or ( fes_post_reset0 < 1 ) ) ) then
assert false
report "OCDIVRST must be held low for at least one CLKC period for the reset operation to work correctly: reset operation may not be successful, edge alignment unpredictable"
severity warning;
end if;
res_post_reset1 := 0;
fes_post_reset1 := 0;
elsif ( TO_X01( OCDIVRST_ipd ) = '0' ) then
if ( ( TO_X01( OCDIVRST_ipd'last_value ) = '1' ) and
( ( res_post_reset1 < 3 ) or ( fes_post_reset1 < 3 ) ) ) then
assert false
report "OCDIVRST must be held high for at least three CLKC periods for the reset operation to work correctly: reset operation may not be succesful, edge alignment unpredictable"
severity warning;
end if;
res_post_reset0 := 0;
fes_post_reset0 := 0;
else
assert false
report "OCDIVRST is unknown. Edge alignment unpredictable."
severity warning;
end if;
end if;
if ( WIN'event ) then
num_edges := num_edges + 1;
if ( force_0 ) then
COUT <= '0';
elsif ( TO_X01( WIN ) = 'X' ) then
COUT <= 'X';
elsif ( ( num_edges mod DIVW ) = 0 ) then
num_edges := 0;
if ( TO_X01 ( COUT ) = 'X' ) then
COUT <= WIN;
else
COUT <= not COUT;
end if;
end if;
end if;
else -- PLL not bypassed
if ( TO_X01 ( POWERDOWN_ipd ) = '0' ) then
COUT <= '0';
elsif ( TO_X01 ( POWERDOWN_ipd ) = '1' ) then
COUT <= WIN;
else -- POWERDOWN unknown
COUT <= 'X';
end if;
end if;
end process DividerW;
using_EXTFB <= TO_X01( FBSEL1_ipd and FBSEL0_ipd );
external_dly_correct <= expected_EXTFB xnor EXTFB_ipd after 1 ps;
get_EXTFB_period : process
variable previous_re : time := 0.000 ns; -- Previous EXTFB rising edge
begin
wait until rising_edge( EXTFB );
EXTFB_period <= NOW - previous_re;
previous_re := NOW;
end process get_EXTFB_period;
calculate_extfb_delay : process
variable CLKA_edge : time := 0 ns;
begin
EXTFB_delay_dtrmd <= false;
if ( ( '1' /= using_EXTFB ) or ( not CLKA_period_stable ) ) then
wait until ( ( '1' = using_EXTFB ) and CLKA_period_stable );
end if;
wait for GLA_EXTFB_rise_dly;
GLA_EXTFB_fall_dly <= 0 ps;
GLA_EXTFB_rise_dly <= 0 ps;
wait for ( CLKA_2_GLA_dly * 2);
calibrate_EXTFB_delay <= '1';
if ( '1' /= EXTFB_ipd ) then
wait until ( EXTFB_ipd = '1' );
end if;
wait until falling_edge( CLKA_ipd );
CLKA_edge := NOW;
calibrate_EXTFB_delay <= '0';
wait until falling_edge( EXTFB_ipd );
GLA_EXTFB_fall_dly <= NOW - CLKA_edge - CLKA_2_GLA_dly;
wait until rising_edge( CLKA_ipd );
CLKA_edge := NOW;
calibrate_EXTFB_delay <= '1';
wait until rising_edge( EXTFB_ipd );
GLA_EXTFB_rise_dly <= NOW - CLKA_edge - CLKA_2_GLA_dly;
wait until falling_edge( CLKA_ipd );
wait until ( CLKA_period_stable and rising_edge( fin ) );
EXTFB_delay_dtrmd <= true;
wait until falling_edge( expected_EXTFB );
if ( '1' /= external_dly_correct ) then
assert false
report "ERROR: EXTFB must be a simple, time-delayed derivative of GLA. Simulation cannot continue until user-logic is corrected"
severity failure;
wait;
end if;
wait until ( '1' /= external_dly_correct );
end process calculate_extfb_delay;
external_feedback : process
variable edges : integer := 1;
begin
wait on GLA_free_running, EXTFB_delay_dtrmd;
if ( EXTFB_delay_dtrmd ) then
if ( ( edges mod ( DIVM * 2 ) ) = 0 ) then
GLA_free_running <= not GLA_free_running after ( GLA_pw - extfbin_fin_drift );
edges := 0;
else
GLA_free_running <= not GLA_free_running after GLA_pw;
end if;
edges := edges + 1;
else
edges := 1;
GLA_free_running <= '1' after GLA_pw;
end if;
end process external_feedback;
gen_AOUT_using_EXTFB : process( AOUT, GLA_free_running, calibrate_EXTFB_delay, locked_vco0_edges, EXTFB_delay_dtrmd )
begin
if ( 0 <= locked_vco0_edges ) then
AOUT_using_EXTFB <= AOUT;
elsif ( EXTFB_delay_dtrmd ) then
AOUT_using_EXTFB <= GLA_free_running;
else
AOUT_using_EXTFB <= calibrate_EXTFB_delay;
end if;
end process gen_AOUT_using_EXTFB;
gen_expected_EXTFB: process( AOUT_using_EXTFB, EXTFB_delay_dtrmd )
begin
if ( not EXTFB_delay_dtrmd ) then
expected_EXTFB <= 'X';
elsif ( '1' = AOUT_using_EXTFB ) then
expected_EXTFB <= transport AOUT_using_EXTFB after ( CLKA_2_GLA_dly + GLA_EXTFB_rise_dly );
else
expected_EXTFB <= transport AOUT_using_EXTFB after ( CLKA_2_GLA_dly + GLA_EXTFB_fall_dly );
end if;
end process gen_expected_EXTFB;
Aoutputs: process( AOUT, CLKA_ipd, AOUT_using_EXTFB, OAMUX_config )
begin
if ( 0 = OAMUX_config ) then
GLA <= transport CLKA_ipd after CLKA_2_GLA_bypass0_dly;
elsif ( ( 1 = OAMUX_config ) or ( 3 = OAMUX_config ) ) then
GLA <= transport 'X' after CLKA_2_GLA_dly;
assert ( not OAMUX_config'event )
report "WARNING: Illegal OAMUX configuration."
severity warning;
elsif ( '1' = using_EXTFB ) then
GLA <= transport AOUT_using_EXTFB after CLKA_2_GLA_dly;
else
GLA <= transport AOUT after CLKA_2_GLA_dly;
end if;
end process Aoutputs;
Boutputs: process ( BOUT, CLKB_ipd, OBMUX_config )
begin
if ( 0 = OBMUX_config ) then
GLB <= transport CLKB_ipd after CLKB_2_GLB_bypass0_dly;
YB <= 'X';
elsif ( ( 1 = OBMUX_config ) or ( 3 = OBMUX_config ) ) then
GLB <= transport 'X' after CLKA_2_GLB_dly;
YB <= transport 'X' after CLKA_2_YB_dly;
assert ( not OBMUX_config'event )
report "WARNING: Illegal OBMUX configuration."
severity warning;
else
GLB <= transport BOUT after CLKA_2_GLB_dly;
YB <= transport BOUT after CLKA_2_YB_dly;
end if;
end process Boutputs;
Coutputs: process ( COUT, CLKC_ipd, OCMUX_config )
begin
if ( 0 = OCMUX_config ) then
GLC <= transport CLKC_ipd after CLKC_2_GLC_bypass0_dly;
YC <= 'X';
elsif ( ( 1 = OCMUX_config ) or ( 3 = OCMUX_config ) ) then
GLC <= transport 'X' after CLKA_2_GLC_dly;
YC <= transport 'X' after CLKA_2_YC_dly;
assert ( not OCMUX_config'event )
report "WARNING: Illegal OCMUX configuration."
severity warning;
else
GLC <= transport COUT after CLKA_2_GLC_dly;
YC <= transport COUT after CLKA_2_YC_dly;
end if;
end process Coutputs;
end VITAL_ACT;
library IEEE;
use IEEE.std_logic_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;
-- entity declaration --
entity PLL is
generic(
VCOFREQUENCY : Real := 0.0;
f_CLKA_LOCK : Integer := 3; -- Number of CLKA pulses after which LOCK is raised
TimingChecksOn : Boolean := True;
InstancePath : String := "*";
Xon : Boolean := False;
MsgOn : Boolean := True;
tipd_CLKA : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_EXTFB : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_POWERDOWN : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OADIV0 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OADIV1 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OADIV2 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OADIV3 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OADIV4 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OAMUX0 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OAMUX1 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OAMUX2 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYGLA0 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYGLA1 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYGLA2 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYGLA3 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYGLA4 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OBDIV0 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OBDIV1 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OBDIV2 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OBDIV3 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OBDIV4 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OBMUX0 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OBMUX1 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OBMUX2 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYYB0 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYYB1 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYYB2 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYYB3 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYYB4 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYGLB0 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYGLB1 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYGLB2 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYGLB3 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYGLB4 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OCDIV0 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OCDIV1 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OCDIV2 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OCDIV3 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OCDIV4 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OCMUX0 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OCMUX1 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_OCMUX2 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYYC0 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYYC1 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYYC2 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYYC3 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYYC4 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYGLC0 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYGLC1 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYGLC2 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYGLC3 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_DLYGLC4 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_FINDIV0 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_FINDIV1 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_FINDIV2 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_FINDIV3 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_FINDIV4 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_FINDIV5 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_FINDIV6 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_FBDIV0 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_FBDIV1 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_FBDIV2 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_FBDIV3 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_FBDIV4 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_FBDIV5 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_FBDIV6 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_FBDLY0 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_FBDLY1 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_FBDLY2 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_FBDLY3 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_FBDLY4 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_FBSEL0 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_FBSEL1 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_XDLYSEL : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_VCOSEL0 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_VCOSEL1 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tipd_VCOSEL2 : VitalDelayType01 := ( 0.000 ns, 0.000 ns );
tpd_CLKA_GLA : VitalDelayType01 := ( 0.100 ns, 0.100 ns );
tpd_EXTFB_GLA : VitalDelayType01 := ( 0.100 ns, 0.100 ns );
tpd_POWERDOWN_GLA : VitalDelayType01 := ( 0.100 ns, 0.100 ns );
tpd_CLKA_GLB : VitalDelayType01 := ( 0.100 ns, 0.100 ns );
tpd_EXTFB_GLB : VitalDelayType01 := ( 0.100 ns, 0.100 ns );
tpd_POWERDOWN_GLB : VitalDelayType01 := ( 0.100 ns, 0.100 ns );
tpd_CLKA_GLC : VitalDelayType01 := ( 0.100 ns, 0.100 ns );
tpd_EXTFB_GLC : VitalDelayType01 := ( 0.100 ns, 0.100 ns );
tpd_POWERDOWN_GLC : VitalDelayType01 := ( 0.100 ns, 0.100 ns );
tpd_CLKA_YB : VitalDelayType01 := ( 0.100 ns, 0.100 ns );
tpd_EXTFB_YB : VitalDelayType01 := ( 0.100 ns, 0.100 ns );
tpd_POWERDOWN_YB : VitalDelayType01 := ( 0.100 ns, 0.100 ns );
tpd_CLKA_YC : VitalDelayType01 := ( 0.100 ns, 0.100 ns );
tpd_EXTFB_YC : VitalDelayType01 := ( 0.100 ns, 0.100 ns );
tpd_POWERDOWN_YC : VitalDelayType01 := ( 0.100 ns, 0.100 ns );
tpd_CLKA_LOCK : VitalDelayType01 := ( 0.100 ns, 0.100 ns )
);
port (
CLKA : in std_ulogic;
EXTFB : in std_ulogic;
POWERDOWN : in std_ulogic;
OADIV0 : in std_ulogic;
OADIV1 : in std_ulogic;
OADIV2 : in std_ulogic;
OADIV3 : in std_ulogic;
OADIV4 : in std_ulogic;
OAMUX0 : in std_ulogic;
OAMUX1 : in std_ulogic;
OAMUX2 : in std_ulogic;
DLYGLA0 : in std_ulogic;
DLYGLA1 : in std_ulogic;
DLYGLA2 : in std_ulogic;
DLYGLA3 : in std_ulogic;
DLYGLA4 : in std_ulogic;
OBDIV0 : in std_ulogic;
OBDIV1 : in std_ulogic;
OBDIV2 : in std_ulogic;
OBDIV3 : in std_ulogic;
OBDIV4 : in std_ulogic;
OBMUX0 : in std_ulogic;
OBMUX1 : in std_ulogic;
OBMUX2 : in std_ulogic;
DLYYB0 : in std_ulogic;
DLYYB1 : in std_ulogic;
DLYYB2 : in std_ulogic;
DLYYB3 : in std_ulogic;
DLYYB4 : in std_ulogic;
DLYGLB0 : in std_ulogic;
DLYGLB1 : in std_ulogic;
DLYGLB2 : in std_ulogic;
DLYGLB3 : in std_ulogic;
DLYGLB4 : in std_ulogic;
OCDIV0 : in std_ulogic;
OCDIV1 : in std_ulogic;
OCDIV2 : in std_ulogic;
OCDIV3 : in std_ulogic;
OCDIV4 : in std_ulogic;
OCMUX0 : in std_ulogic;
OCMUX1 : in std_ulogic;
OCMUX2 : in std_ulogic;
DLYYC0 : in std_ulogic;
DLYYC1 : in std_ulogic;
DLYYC2 : in std_ulogic;
DLYYC3 : in std_ulogic;
DLYYC4 : in std_ulogic;
DLYGLC0 : in std_ulogic;
DLYGLC1 : in std_ulogic;
DLYGLC2 : in std_ulogic;
DLYGLC3 : in std_ulogic;
DLYGLC4 : in std_ulogic;
FINDIV0 : in std_ulogic;
FINDIV1 : in std_ulogic;
FINDIV2 : in std_ulogic;
FINDIV3 : in std_ulogic;
FINDIV4 : in std_ulogic;
FINDIV5 : in std_ulogic;
FINDIV6 : in std_ulogic;
FBDIV0 : in std_ulogic;
FBDIV1 : in std_ulogic;
FBDIV2 : in std_ulogic;
FBDIV3 : in std_ulogic;
FBDIV4 : in std_ulogic;
FBDIV5 : in std_ulogic;
FBDIV6 : in std_ulogic;
FBDLY0 : in std_ulogic;
FBDlY1 : in std_ulogic;
FBDLY2 : in std_ulogic;
FBDLY3 : in std_ulogic;
FBDlY4 : in std_ulogic;
FBSEL0 : in std_ulogic;
FBSEL1 : in std_ulogic;
XDLYSEL : in std_ulogic;
VCOSEL0 : in std_ulogic;
VCOSEL1 : in std_ulogic;
VCOSEL2 : in std_ulogic;
GLA : out std_ulogic;
LOCK : out std_ulogic;
GLB : out std_ulogic;
YB : out std_ulogic;
GLC : out std_ulogic;
YC : out std_ulogic
);
attribute VITAL_LEVEL0 of PLL : entity is TRUE;
end PLL;
-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library proasic3;
use proasic3.components.all;
architecture VITAL_ACT of PLL is
attribute VITAL_LEVEL1 of VITAL_ACT : architecture is FALSE;
signal CLKA_ipd : std_ulogic;
signal EXTFB_ipd : std_ulogic;
signal POWERDOWN_ipd : std_ulogic;
signal OADIV0_ipd : std_ulogic;
signal OADIV1_ipd : std_ulogic;
signal OADIV2_ipd : std_ulogic;
signal OADIV3_ipd : std_ulogic;
signal OADIV4_ipd : std_ulogic;
signal OAMUX0_ipd : std_ulogic;
signal OAMUX1_ipd : std_ulogic;
signal OAMUX2_ipd : std_ulogic;
signal DLYGLA0_ipd : std_ulogic;
signal DLYGLA1_ipd : std_ulogic;
signal DLYGLA2_ipd : std_ulogic;
signal DLYGLA3_ipd : std_ulogic;
signal DLYGLA4_ipd : std_ulogic;
signal OBDIV0_ipd : std_ulogic;
signal OBDIV1_ipd : std_ulogic;
signal OBDIV2_ipd : std_ulogic;
signal OBDIV3_ipd : std_ulogic;
signal OBDIV4_ipd : std_ulogic;
signal OBMUX0_ipd : std_ulogic;
signal OBMUX1_ipd : std_ulogic;
signal OBMUX2_ipd : std_ulogic;
signal DLYYB0_ipd : std_ulogic;
signal DLYYB1_ipd : std_ulogic;
signal DLYYB2_ipd : std_ulogic;
signal DLYYB3_ipd : std_ulogic;
signal DLYYB4_ipd : std_ulogic;
signal DLYGLB0_ipd : std_ulogic;
signal DLYGLB1_ipd : std_ulogic;
signal DLYGLB2_ipd : std_ulogic;
signal DLYGLB3_ipd : std_ulogic;
signal DLYGLB4_ipd : std_ulogic;
signal OCDIV0_ipd : std_ulogic;
signal OCDIV1_ipd : std_ulogic;
signal OCDIV2_ipd : std_ulogic;
signal OCDIV3_ipd : std_ulogic;
signal OCDIV4_ipd : std_ulogic;
signal OCMUX0_ipd : std_ulogic;
signal OCMUX1_ipd : std_ulogic;
signal OCMUX2_ipd : std_ulogic;
signal DLYYC0_ipd : std_ulogic;
signal DLYYC1_ipd : std_ulogic;
signal DLYYC2_ipd : std_ulogic;
signal DLYYC3_ipd : std_ulogic;
signal DLYYC4_ipd : std_ulogic;
signal DLYGLC0_ipd : std_ulogic;
signal DLYGLC1_ipd : std_ulogic;
signal DLYGLC2_ipd : std_ulogic;
signal DLYGLC3_ipd : std_ulogic;
signal DLYGLC4_ipd : std_ulogic;
signal FINDIV0_ipd : std_ulogic;
signal FINDIV1_ipd : std_ulogic;
signal FINDIV2_ipd : std_ulogic;
signal FINDIV3_ipd : std_ulogic;
signal FINDIV4_ipd : std_ulogic;
signal FINDIV5_ipd : std_ulogic;
signal FINDIV6_ipd : std_ulogic;
signal FBDIV0_ipd : std_ulogic;
signal FBDIV1_ipd : std_ulogic;
signal FBDIV2_ipd : std_ulogic;
signal FBDIV3_ipd : std_ulogic;
signal FBDIV4_ipd : std_ulogic;
signal FBDIV5_ipd : std_ulogic;
signal FBDIV6_ipd : std_ulogic;
signal FBDLY0_ipd : std_ulogic;
signal FBDlY1_ipd : std_ulogic;
signal FBDLY2_ipd : std_ulogic;
signal FBDLY3_ipd : std_ulogic;
signal FBDlY4_ipd : std_ulogic;
signal FBSEL0_ipd : std_ulogic;
signal FBSEL1_ipd : std_ulogic;
signal XDLYSEL_ipd : std_ulogic;
signal VCOSEL0_ipd : std_ulogic;
signal VCOSEL1_ipd : std_ulogic;
signal VCOSEL2_ipd : std_ulogic;
signal GND : std_logic := '0';
signal UNUSED : std_logic := 'X';
component PLLPRIM
generic (
VCOFREQUENCY : Real;
f_CLKA_LOCK : Integer
);
port (
DYNSYNC : in std_ulogic;
CLKA : in std_ulogic;
EXTFB : in std_ulogic;
POWERDOWN : in std_ulogic;
CLKB : in std_ulogic;
CLKC : in std_ulogic;
OADIVRST : in std_ulogic;
OADIVHALF : in std_ulogic;
OADIV0 : in std_ulogic;
OADIV1 : in std_ulogic;
OADIV2 : in std_ulogic;
OADIV3 : in std_ulogic;
OADIV4 : in std_ulogic;
OAMUX0 : in std_ulogic;
OAMUX1 : in std_ulogic;
OAMUX2 : in std_ulogic;
DLYGLA0 : in std_ulogic;
DLYGLA1 : in std_ulogic;
DLYGLA2 : in std_ulogic;
DLYGLA3 : in std_ulogic;
DLYGLA4 : in std_ulogic;
OBDIVRST : in std_ulogic;
OBDIVHALF : in std_ulogic;
OBDIV0 : in std_ulogic;
OBDIV1 : in std_ulogic;
OBDIV2 : in std_ulogic;
OBDIV3 : in std_ulogic;
OBDIV4 : in std_ulogic;
OBMUX0 : in std_ulogic;
OBMUX1 : in std_ulogic;
OBMUX2 : in std_ulogic;
DLYYB0 : in std_ulogic;
DLYYB1 : in std_ulogic;
DLYYB2 : in std_ulogic;
DLYYB3 : in std_ulogic;
DLYYB4 : in std_ulogic;
DLYGLB0 : in std_ulogic;
DLYGLB1 : in std_ulogic;
DLYGLB2 : in std_ulogic;
DLYGLB3 : in std_ulogic;
DLYGLB4 : in std_ulogic;
OCDIVRST : in std_ulogic;
OCDIVHALF : in std_ulogic;
OCDIV0 : in std_ulogic;
OCDIV1 : in std_ulogic;
OCDIV2 : in std_ulogic;
OCDIV3 : in std_ulogic;
OCDIV4 : in std_ulogic;
OCMUX0 : in std_ulogic;
OCMUX1 : in std_ulogic;
OCMUX2 : in std_ulogic;
DLYYC0 : in std_ulogic;
DLYYC1 : in std_ulogic;
DLYYC2 : in std_ulogic;
DLYYC3 : in std_ulogic;
DLYYC4 : in std_ulogic;
DLYGLC0 : in std_ulogic;
DLYGLC1 : in std_ulogic;
DLYGLC2 : in std_ulogic;
DLYGLC3 : in std_ulogic;
DLYGLC4 : in std_ulogic;
FINDIV0 : in std_ulogic;
FINDIV1 : in std_ulogic;
FINDIV2 : in std_ulogic;
FINDIV3 : in std_ulogic;
FINDIV4 : in std_ulogic;
FINDIV5 : in std_ulogic;
FINDIV6 : in std_ulogic;
FBDIV0 : in std_ulogic;
FBDIV1 : in std_ulogic;
FBDIV2 : in std_ulogic;
FBDIV3 : in std_ulogic;
FBDIV4 : in std_ulogic;
FBDIV5 : in std_ulogic;
FBDIV6 : in std_ulogic;
FBDLY0 : in std_ulogic;
FBDlY1 : in std_ulogic;
FBDLY2 : in std_ulogic;
FBDLY3 : in std_ulogic;
FBDlY4 : in std_ulogic;
FBSEL0 : in std_ulogic;
FBSEL1 : in std_ulogic;
XDLYSEL : in std_ulogic;
VCOSEL0 : in std_ulogic;
VCOSEL1 : in std_ulogic;
VCOSEL2 : in std_ulogic;
GLA : out std_ulogic;
LOCK : out std_ulogic;
GLB : out std_ulogic;
YB : out std_ulogic;
GLC : out std_ulogic;
YC : out std_ulogic
);
end component;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay ( CLKA_ipd, CLKA, tipd_CLKA );
VitalWireDelay ( EXTFB_ipd, EXTFB, tipd_EXTFB );
VitalWireDelay ( POWERDOWN_ipd, POWERDOWN, tipd_POWERDOWN );
VitalWireDelay ( OADIV0_ipd, OADIV0, tipd_OADIV0 );
VitalWireDelay ( OADIV1_ipd, OADIV1, tipd_OADIV1 );
VitalWireDelay ( OADIV2_ipd, OADIV2, tipd_OADIV2 );
VitalWireDelay ( OADIV3_ipd, OADIV3, tipd_OADIV3 );
VitalWireDelay ( OADIV4_ipd, OADIV4, tipd_OADIV4 );
VitalWireDelay ( OAMUX0_ipd, OAMUX0, tipd_OAMUX0 );
VitalWireDelay ( OAMUX1_ipd, OAMUX1, tipd_OAMUX1 );
VitalWireDelay ( OAMUX2_ipd, OAMUX2, tipd_OAMUX2 );
VitalWireDelay ( DLYGLA0_ipd, DLYGLA0, tipd_DLYGLA0 );
VitalWireDelay ( DLYGLA1_ipd, DLYGLA1, tipd_DLYGLA1 );
VitalWireDelay ( DLYGLA2_ipd, DLYGLA2, tipd_DLYGLA2 );
VitalWireDelay ( DLYGLA3_ipd, DLYGLA3, tipd_DLYGLA3 );
VitalWireDelay ( DLYGLA4_ipd, DLYGLA4, tipd_DLYGLA4 );
VitalWireDelay ( OBDIV0_ipd, OBDIV0, tipd_OBDIV0 );
VitalWireDelay ( OBDIV1_ipd, OBDIV1, tipd_OBDIV1 );
VitalWireDelay ( OBDIV2_ipd, OBDIV2, tipd_OBDIV2 );
VitalWireDelay ( OBDIV3_ipd, OBDIV3, tipd_OBDIV3 );
VitalWireDelay ( OBDIV4_ipd, OBDIV4, tipd_OBDIV4 );
VitalWireDelay ( OBMUX0_ipd, OBMUX0, tipd_OBMUX0 );
VitalWireDelay ( OBMUX1_ipd, OBMUX1, tipd_OBMUX1 );
VitalWireDelay ( OBMUX2_ipd, OBMUX2, tipd_OBMUX2 );
VitalWireDelay ( DLYYB0_ipd, DLYYB0, tipd_DLYYB0 );
VitalWireDelay ( DLYYB1_ipd, DLYYB1, tipd_DLYYB1 );
VitalWireDelay ( DLYYB2_ipd, DLYYB2, tipd_DLYYB2 );
VitalWireDelay ( DLYYB3_ipd, DLYYB3, tipd_DLYYB3 );
VitalWireDelay ( DLYYB4_ipd, DLYYB4, tipd_DLYYB4 );
VitalWireDelay ( DLYGLB0_ipd, DLYGLB0, tipd_DLYGLB0 );
VitalWireDelay ( DLYGLB1_ipd, DLYGLB1, tipd_DLYGLB1 );
VitalWireDelay ( DLYGLB2_ipd, DLYGLB2, tipd_DLYGLB2 );
VitalWireDelay ( DLYGLB3_ipd, DLYGLB3, tipd_DLYGLB3 );
VitalWireDelay ( DLYGLB4_ipd, DLYGLB4, tipd_DLYGLB4 );
VitalWireDelay ( OCDIV0_ipd, OCDIV0, tipd_OCDIV0 );
VitalWireDelay ( OCDIV1_ipd, OCDIV1, tipd_OCDIV1 );
VitalWireDelay ( OCDIV2_ipd, OCDIV2, tipd_OCDIV2 );
VitalWireDelay ( OCDIV3_ipd, OCDIV3, tipd_OCDIV3 );
VitalWireDelay ( OCDIV4_ipd, OCDIV4, tipd_OCDIV4 );
VitalWireDelay ( OCMUX0_ipd, OCMUX0, tipd_OCMUX0 );
VitalWireDelay ( OCMUX1_ipd, OCMUX1, tipd_OCMUX1 );
VitalWireDelay ( OCMUX2_ipd, OCMUX2, tipd_OCMUX2 );
VitalWireDelay ( DLYYC0_ipd, DLYYC0, tipd_DLYYC0 );
VitalWireDelay ( DLYYC1_ipd, DLYYC1, tipd_DLYYC1 );
VitalWireDelay ( DLYYC2_ipd, DLYYC2, tipd_DLYYC2 );
VitalWireDelay ( DLYYC3_ipd, DLYYC3, tipd_DLYYC3 );
VitalWireDelay ( DLYYC4_ipd, DLYYC4, tipd_DLYYC4 );
VitalWireDelay ( DLYGLC0_ipd, DLYGLC0, tipd_DLYGLC0 );
VitalWireDelay ( DLYGLC1_ipd, DLYGLC1, tipd_DLYGLC1 );
VitalWireDelay ( DLYGLC2_ipd, DLYGLC2, tipd_DLYGLC2 );
VitalWireDelay ( DLYGLC3_ipd, DLYGLC3, tipd_DLYGLC3 );
VitalWireDelay ( DLYGLC4_ipd, DLYGLC4, tipd_DLYGLC4 );
VitalWireDelay ( FINDIV0_ipd, FINDIV0, tipd_FINDIV0 );
VitalWireDelay ( FINDIV1_ipd, FINDIV1, tipd_FINDIV1 );
VitalWireDelay ( FINDIV2_ipd, FINDIV2, tipd_FINDIV2 );
VitalWireDelay ( FINDIV3_ipd, FINDIV3, tipd_FINDIV3 );
VitalWireDelay ( FINDIV4_ipd, FINDIV4, tipd_FINDIV4 );
VitalWireDelay ( FINDIV5_ipd, FINDIV5, tipd_FINDIV5 );
VitalWireDelay ( FINDIV6_ipd, FINDIV6, tipd_FINDIV6 );
VitalWireDelay ( FBDIV0_ipd, FBDIV0, tipd_FBDIV0 );
VitalWireDelay ( FBDIV1_ipd, FBDIV1, tipd_FBDIV1 );
VitalWireDelay ( FBDIV2_ipd, FBDIV2, tipd_FBDIV2 );
VitalWireDelay ( FBDIV3_ipd, FBDIV3, tipd_FBDIV3 );
VitalWireDelay ( FBDIV4_ipd, FBDIV4, tipd_FBDIV4 );
VitalWireDelay ( FBDIV5_ipd, FBDIV5, tipd_FBDIV5 );
VitalWireDelay ( FBDIV6_ipd, FBDIV6, tipd_FBDIV6 );
VitalWireDelay ( FBDLY0_ipd, FBDLY0, tipd_FBDLY0 );
VitalWireDelay ( FBDLY1_ipd, FBDLY1, tipd_FBDLY1 );
VitalWireDelay ( FBDLY2_ipd, FBDLY2, tipd_FBDLY2 );
VitalWireDelay ( FBDLY3_ipd, FBDLY3, tipd_FBDLY3 );
VitalWireDelay ( FBDLY4_ipd, FBDLY4, tipd_FBDLY4 );
VitalWireDelay ( FBSEL0_ipd, FBSEL0, tipd_FBSEL0 );
VitalWireDelay ( FBSEL1_ipd, FBSEL1, tipd_FBSEL1 );
VitalWireDelay ( XDLYSEL_ipd, XDLYSEL, tipd_XDLYSEL );
VitalWireDelay ( VCOSEL0_ipd, VCOSEL0, tipd_VCOSEL0 );
VitalWireDelay ( VCOSEL1_ipd, VCOSEL1, tipd_VCOSEL1 );
VitalWireDelay ( VCOSEL2_ipd, VCOSEL2, tipd_VCOSEL2 );
end block WireDelay;
P1: PLLPRIM
generic map (
VCOFREQUENCY => VCOFREQUENCY,
f_CLKA_LOCK => f_CLKA_LOCK
)
port map (
DYNSYNC => GND,
CLKA => CLKA_ipd,
EXTFB => EXTFB_ipd,
POWERDOWN => POWERDOWN_ipd,
CLKB => UNUSED,
CLKC => UNUSED,
OADIVRST => GND,
OADIVHALF => GND,
OADIV0 => OADIV0_ipd,
OADIV1 => OADIV1_ipd,
OADIV2 => OADIV2_ipd,
OADIV3 => OADIV3_ipd,
OADIV4 => OADIV4_ipd,
OAMUX0 => OAMUX0_ipd,
OAMUX1 => OAMUX1_ipd,
OAMUX2 => OAMUX2_ipd,
DLYGLA0 => DLYGLA0_ipd,
DLYGLA1 => DLYGLA1_ipd,
DLYGLA2 => DLYGLA2_ipd,
DLYGLA3 => DLYGLA3_ipd,
DLYGLA4 => DLYGLA4_ipd,
OBDIVRST => GND,
OBDIVHALF => GND,
OBDIV0 => OBDIV0_ipd,
OBDIV1 => OBDIV1_ipd,
OBDIV2 => OBDIV2_ipd,
OBDIV3 => OBDIV3_ipd,
OBDIV4 => OBDIV4_ipd,
OBMUX0 => OBMUX0_ipd,
OBMUX1 => OBMUX1_ipd,
OBMUX2 => OBMUX2_ipd,
DLYYB0 => DLYYB0_ipd,
DLYYB1 => DLYYB1_ipd,
DLYYB2 => DLYYB2_ipd,
DLYYB3 => DLYYB3_ipd,
DLYYB4 => DLYYB4_ipd,
DLYGLB0 => DLYGLB0_ipd,
DLYGLB1 => DLYGLB1_ipd,
DLYGLB2 => DLYGLB2_ipd,
DLYGLB3 => DLYGLB3_ipd,
DLYGLB4 => DLYGLB4_ipd,
OCDIVRST => GND,
OCDIVHALF => GND,
OCDIV0 => OCDIV0_ipd,
OCDIV1 => OCDIV1_ipd,
OCDIV2 => OCDIV2_ipd,
OCDIV3 => OCDIV3_ipd,
OCDIV4 => OCDIV4_ipd,
OCMUX0 => OCMUX0_ipd,
OCMUX1 => OCMUX1_ipd,
OCMUX2 => OCMUX2_ipd,
DLYYC0 => DLYYC0_ipd,
DLYYC1 => DLYYC1_ipd,
DLYYC2 => DLYYC2_ipd,
DLYYC3 => DLYYC3_ipd,
DLYYC4 => DLYYC4_ipd,
DLYGLC0 => DLYGLC0_ipd,
DLYGLC1 => DLYGLC1_ipd,
DLYGLC2 => DLYGLC2_ipd,
DLYGLC3 => DLYGLC3_ipd,
DLYGLC4 => DLYGLC4_ipd,
FINDIV0 => FINDIV0_ipd,
FINDIV1 => FINDIV1_ipd,
FINDIV2 => FINDIV2_ipd,
FINDIV3 => FINDIV3_ipd,
FINDIV4 => FINDIV4_ipd,
FINDIV5 => FINDIV5_ipd,
FINDIV6 => FINDIV6_ipd,
FBDIV0 => FBDIV0_ipd,
FBDIV1 => FBDIV1_ipd,
FBDIV2 => FBDIV2_ipd,
FBDIV3 => FBDIV3_ipd,
FBDIV4 => FBDIV4_ipd,
FBDIV5 => FBDIV5_ipd,
FBDIV6 => FBDIV6_ipd,
FBDLY0 => FBDLY0_ipd,
FBDlY1 => FBDlY1_ipd,
FBDLY2 => FBDLY2_ipd,
FBDLY3 => FBDLY3_ipd,
FBDlY4 => FBDlY4_ipd,
FBSEL0 => FBSEL0_ipd,
FBSEL1 => FBSEL1_ipd,
XDLYSEL => XDLYSEL_ipd,
VCOSEL0 => VCOSEL0_ipd,
VCOSEL1 => VCOSEL1_ipd,
VCOSEL2 => VCOSEL2_ipd,
GLA => GLA,
LOCK => LOCK,
GLB => GLB,
YB => YB,
GLC => GLC,
YC => YC
);
end VITAL_ACT;
library IEEE;
use IEEE.std_logic_1164.all;
entity UJTAG is
port(
UTDO : in STD_ULOGIC;
TMS : in STD_ULOGIC;
TDI : in STD_ULOGIC;
TCK : in STD_ULOGIC;
TRSTB : in STD_ULOGIC;
UIREG0 : out STD_ULOGIC;
UIREG1 : out STD_ULOGIC;
UIREG2 : out STD_ULOGIC;
UIREG3 : out STD_ULOGIC;
UIREG4 : out STD_ULOGIC;
UIREG5 : out STD_ULOGIC;
UIREG6 : out STD_ULOGIC;
UIREG7 : out STD_ULOGIC;
UTDI : out STD_ULOGIC;
URSTB : out STD_ULOGIC;
UDRCK : out STD_ULOGIC;
UDRCAP : out STD_ULOGIC;
UDRSH : out STD_ULOGIC;
UDRUPD : out STD_ULOGIC;
TDO : out STD_ULOGIC);
end;
library IEEE;
use IEEE.std_logic_1164.all;
architecture behav of UJTAG is
begin
UIREG0 <= '0';
UIREG1 <= '0';
UIREG2 <= '0';
UIREG3 <= '0';
UIREG4 <= '0';
UIREG5 <= '0';
UIREG6 <= '0';
UIREG7 <= '0';
UTDI <= '0';
URSTB <= '0';
UDRCK <= '0';
UDRCAP <= '0';
UDRSH <= '0';
UDRUPD <= '0';
TDO <= '0';
end;
| mit | 862f2c861a6a3ebb1bee91dcd72ca6cd | 0.525654 | 3.454726 | false | false | false | false |
christakissgeo/Matrix-Vector-Multiplication | DC Compiler/Exports/final.vhd | 1 | 183,317 |
library IEEE;
use IEEE.std_logic_1164.all;
package CONV_PACK_project2 is
-- define attributes
attribute ENUM_ENCODING : STRING;
-- define any necessary types
type VHDLOUT_TYPE is array (0 downto 0) of std_logic;
end CONV_PACK_project2;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_project2.all;
entity counter_address_generator_1_DW01_inc_0 is
port( A : in std_logic_vector (7 downto 0); SUM : out std_logic_vector (7
downto 0));
end counter_address_generator_1_DW01_inc_0;
architecture SYN_rpl of counter_address_generator_1_DW01_inc_0 is
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component HA_X1
port( A, B : in std_logic; CO, S : out std_logic);
end component;
signal carry_7_port, carry_6_port, carry_5_port, carry_4_port, carry_3_port,
carry_2_port : std_logic;
begin
U1_1_6 : HA_X1 port map( A => A(6), B => carry_6_port, CO => carry_7_port, S
=> SUM(6));
U1_1_5 : HA_X1 port map( A => A(5), B => carry_5_port, CO => carry_6_port, S
=> SUM(5));
U1_1_4 : HA_X1 port map( A => A(4), B => carry_4_port, CO => carry_5_port, S
=> SUM(4));
U1_1_3 : HA_X1 port map( A => A(3), B => carry_3_port, CO => carry_4_port, S
=> SUM(3));
U1_1_2 : HA_X1 port map( A => A(2), B => carry_2_port, CO => carry_3_port, S
=> SUM(2));
U1_1_1 : HA_X1 port map( A => A(1), B => A(0), CO => carry_2_port, S =>
SUM(1));
U1 : INV_X1 port map( A => A(0), ZN => SUM(0));
U2 : XOR2_X1 port map( A => carry_7_port, B => A(7), Z => SUM(7));
end SYN_rpl;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_project2.all;
entity mac_DW_mult_tc_1 is
port( a, b : in std_logic_vector (7 downto 0); product : out
std_logic_vector (15 downto 0); clock : in std_logic);
end mac_DW_mult_tc_1;
architecture SYN_USE_DEFA_ARCH_NAME of mac_DW_mult_tc_1 is
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component BUF_X1
port( A : in std_logic; Z : out std_logic);
end component;
component OAI22_X1
port( A1, A2, B1, B2 : in std_logic; ZN : out std_logic);
end component;
component CLKBUF_X1
port( A : in std_logic; Z : out std_logic);
end component;
component CLKBUF_X2
port( A : in std_logic; Z : out std_logic);
end component;
component DFF_X1
port( D, CK : in std_logic; Q, QN : out std_logic);
end component;
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
component NAND2_X2
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component NOR2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component NAND3_X1
port( A1, A2, A3 : in std_logic; ZN : out std_logic);
end component;
component OR2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component NOR3_X1
port( A1, A2, A3 : in std_logic; ZN : out std_logic);
end component;
component XNOR2_X2
port( A, B : in std_logic; ZN : out std_logic);
end component;
component HA_X1
port( A, B : in std_logic; CO, S : out std_logic);
end component;
component FA_X1
port( A, B, CI : in std_logic; CO, S : out std_logic);
end component;
signal n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n14, n15, n17, n19, n20
, n21, n22, n24, n26, n27, n28, n29, n30, n31, n32, n34, n35, n36, n37,
n38, n39, n40, n41, n42, n43, n44, n45, n46, n47, n48, n49, n50, n52, n54
, n55, n56, n57, n58, n59, n60, n61, n62, n67, n69, n70, n73, n74, n75,
n76, n77, n80, n83, n84, n85, n86, n87, n88, n89, n90, n91, n92, n93, n94
, n95, n96, n97, n98, n99, n100, n101, n102, n103, n104, n105, n106, n107
, n108, n109, n110, n111, n112, n113, n114, n117, n118, n119, n120, n123,
n124, n125, n128, n131, n134, n137, n138, n139, n140, n141, n142, n143,
n144, n145, n146, n147, n149, n150, n151, n152, n153, n154, n155, n157,
n158, n159, n160, n161, n162, n163, n165, n166, n167, n168, n169, n170,
n172, n173, n182, n191, n194, n200, n217, n218, n219, n220, n221, n222,
n223, n224, n225, n226, n227, n275, n276, n277, n278, n280, n282, n284,
n285, n286, n287, n288, n290, n291, n292, n293, n294, n295, n296, n297,
n298, n299, n300, n303, n306, n307, n308, n309, n310, n311, n313, n314,
n315, n316, n317, n318, n319, n320, n321, n322, n323, n324, n325, n327,
n328, n329, n330, n333, n334, n336, n356, n357, n358, n359, n360, n361,
n362, n363, n364, n365, n366, n367, n368, n369, n370, n371, n372, n373,
n374, n376, n377, n378, n379, n380, n381, n382, n383, n384, n385, n_1008,
n_1009, n_1010, n_1011, n_1012, n_1013, n_1014, n_1015, n_1016, n_1017,
n_1018, n_1019, n_1020 : std_logic;
begin
U97 : FA_X1 port map( A => n142, B => n89, CI => n149, CO => n85, S => n86);
U98 : FA_X1 port map( A => n90, B => n143, CI => n93, CO => n87, S => n88);
U101 : FA_X1 port map( A => n150, B => n315, CI => n157, CO => n93, S => n94
);
U102 : FA_X1 port map( A => n103, B => n105, CI => n98, CO => n95, S => n96)
;
U103 : FA_X1 port map( A => n145, B => n151, CI => n100, CO => n97, S => n98
);
U109 : FA_X1 port map( A => n384, B => n112, CI => n110, CO => n107, S =>
n108);
U110 : FA_X1 port map( A => n153, B => n166, CI => n159, CO => n109, S =>
n110);
U111 : HA_X1 port map( A => n147, B => n137, CO => n111, S => n112);
U112 : FA_X1 port map( A => n119, B => n154, CI => n383, CO => n113, S =>
n114);
U115 : HA_X1 port map( A => n138, B => n155, CO => n119, S => n120);
U117 : HA_X1 port map( A => n163, B => n170, CO => n123, S => n124);
U237 : XNOR2_X1 port map( A => n111, B => n275, ZN => n104);
U241 : AND2_X1 port map( A1 => n323, A2 => n69, ZN => product(1));
U242 : XNOR2_X1 port map( A => n165, B => n152, ZN => n275);
U243 : NAND2_X1 port map( A1 => n111, A2 => n165, ZN => n276);
U244 : NAND2_X1 port map( A1 => n111, A2 => n152, ZN => n277);
U245 : NAND2_X1 port map( A1 => n165, A2 => n152, ZN => n278);
U246 : NAND3_X1 port map( A1 => n276, A2 => n277, A3 => n278, ZN => n103);
U248 : XNOR2_X2 port map( A => n365, B => n367, ZN => n334);
U250 : CLKBUF_X1 port map( A => n70, Z => n282);
U251 : CLKBUF_X1 port map( A => n55, Z => n284);
U252 : OAI21_X1 port map( B1 => n56, B2 => n58, A => n57, ZN => n55);
U253 : NAND3_X1 port map( A1 => n299, A2 => n298, A3 => n297, ZN => n285);
U254 : OAI21_X1 port map( B1 => n48, B2 => n50, A => n49, ZN => n47);
U255 : XNOR2_X1 port map( A => n120, B => n286, ZN => n118);
U256 : XNOR2_X1 port map( A => n161, B => n168, ZN => n286);
U257 : OR2_X1 port map( A1 => n385, A2 => n123, ZN => n287);
U258 : CLKBUF_X1 port map( A => n36, Z => n288);
U259 : NOR3_X1 port map( A1 => n290, A2 => n291, A3 => n292, ZN =>
product(15));
U260 : AND2_X1 port map( A1 => n285, A2 => n83, ZN => n290);
U261 : AND2_X1 port map( A1 => n141, A2 => n14, ZN => n291);
U262 : AND2_X1 port map( A1 => n141, A2 => n83, ZN => n292);
U263 : NAND2_X1 port map( A1 => n120, A2 => n161, ZN => n293);
U264 : NAND2_X1 port map( A1 => n120, A2 => n168, ZN => n294);
U265 : NAND2_X1 port map( A1 => n161, A2 => n168, ZN => n295);
U266 : NAND3_X1 port map( A1 => n293, A2 => n294, A3 => n295, ZN => n117);
U267 : XOR2_X1 port map( A => n85, B => n84, Z => n296);
U268 : XOR2_X1 port map( A => n296, B => n282, Z => product(13));
U269 : NAND2_X1 port map( A1 => n85, A2 => n84, ZN => n297);
U270 : NAND2_X1 port map( A1 => n85, A2 => n70, ZN => n298);
U271 : NAND2_X1 port map( A1 => n84, A2 => n70, ZN => n299);
U272 : NAND3_X1 port map( A1 => n298, A2 => n299, A3 => n297, ZN => n14);
U273 : XOR2_X1 port map( A => n141, B => n83, Z => n300);
U274 : XOR2_X1 port map( A => n300, B => n285, Z => product(14));
U275 : CLKBUF_X1 port map( A => n99, Z => n315);
U278 : XNOR2_X1 port map( A => n303, B => n94, ZN => n92);
U279 : XNOR2_X1 port map( A => n97, B => n144, ZN => n303);
U280 : NAND2_X1 port map( A1 => n365, A2 => n367, ZN => n306);
U281 : NAND2_X1 port map( A1 => n382, A2 => n377, ZN => n307);
U282 : NAND2_X1 port map( A1 => n306, A2 => n307, ZN => n226);
U285 : AOI21_X1 port map( B1 => n39, B2 => n47, A => n40, ZN => n308);
U286 : NAND2_X1 port map( A1 => n94, A2 => n97, ZN => n309);
U287 : NAND2_X1 port map( A1 => n94, A2 => n144, ZN => n310);
U288 : NAND2_X1 port map( A1 => n97, A2 => n144, ZN => n311);
U289 : NAND3_X1 port map( A1 => n309, A2 => n310, A3 => n311, ZN => n91);
U291 : CLKBUF_X1 port map( A => n29, Z => n313);
U292 : CLKBUF_X1 port map( A => n20, Z => n314);
U293 : AOI21_X1 port map( B1 => n325, B2 => n284, A => n52, ZN => n316);
U294 : NOR2_X1 port map( A1 => n107, A2 => n102, ZN => n317);
U295 : NAND2_X1 port map( A1 => n217, A2 => n225, ZN => n318);
U296 : NOR2_X1 port map( A1 => n92, A2 => n95, ZN => n319);
U297 : OR2_X1 port map( A1 => n88, A2 => n91, ZN => n321);
U298 : XNOR2_X1 port map( A => n37, B => n4, ZN => product(9));
U299 : INV_X1 port map( A => n35, ZN => n74);
U300 : INV_X1 port map( A => n26, ZN => n24);
U301 : NAND2_X1 port map( A1 => n77, A2 => n49, ZN => n7);
U302 : INV_X1 port map( A => n48, ZN => n77);
U303 : NAND2_X1 port map( A1 => n322, A2 => n19, ZN => n1);
U304 : XOR2_X1 port map( A => n46, B => n6, Z => product(7));
U305 : XOR2_X1 port map( A => n32, B => n3, Z => product(10));
U306 : NAND2_X1 port map( A1 => n73, A2 => n31, ZN => n3);
U307 : AOI21_X1 port map( B1 => n37, B2 => n74, A => n34, ZN => n32);
U308 : XOR2_X1 port map( A => n27, B => n2, Z => product(11));
U309 : NAND2_X1 port map( A1 => n321, A2 => n26, ZN => n2);
U310 : XNOR2_X1 port map( A => n43, B => n5, ZN => product(8));
U311 : NAND2_X1 port map( A1 => n75, A2 => n42, ZN => n5);
U312 : INV_X1 port map( A => n19, ZN => n17);
U313 : XNOR2_X1 port map( A => n104, B => n320, ZN => n102);
U314 : XNOR2_X1 port map( A => n106, B => n109, ZN => n320);
U316 : NOR2_X1 port map( A1 => n102, A2 => n107, ZN => n41);
U317 : NOR2_X1 port map( A1 => n92, A2 => n95, ZN => n30);
U318 : NAND2_X1 port map( A1 => n80, A2 => n61, ZN => n10);
U319 : INV_X1 port map( A => n60, ZN => n80);
U321 : XOR2_X1 port map( A => n9, B => n58, Z => product(4));
U322 : NAND2_X1 port map( A1 => n287, A2 => n57, ZN => n9);
U323 : OR2_X1 port map( A1 => n158, A2 => n146, ZN => n105);
U324 : NOR2_X1 port map( A1 => n114, A2 => n117, ZN => n48);
U325 : INV_X1 port map( A => n83, ZN => n84);
U326 : NAND2_X1 port map( A1 => n88, A2 => n91, ZN => n26);
U327 : NAND2_X1 port map( A1 => n87, A2 => n86, ZN => n19);
U328 : NAND2_X1 port map( A1 => n114, A2 => n117, ZN => n49);
U329 : INV_X1 port map( A => n59, ZN => n58);
U330 : OR2_X1 port map( A1 => n87, A2 => n86, ZN => n322);
U331 : INV_X1 port map( A => n128, ZN => n149);
U332 : INV_X1 port map( A => n89, ZN => n90);
U333 : OR2_X1 port map( A1 => n172, A2 => n140, ZN => n323);
U334 : NOR2_X1 port map( A1 => n385, A2 => n123, ZN => n56);
U335 : INV_X1 port map( A => n125, ZN => n141);
U337 : OR2_X1 port map( A1 => n118, A2 => n380, ZN => n325);
U340 : XOR2_X1 port map( A => n379, B => n356, Z => n182);
U343 : NAND2_X1 port map( A1 => n217, A2 => n225, ZN => n221);
U348 : NAND2_X1 port map( A1 => n76, A2 => n45, ZN => n6);
U349 : NAND2_X1 port map( A1 => n325, A2 => n54, ZN => n8);
U350 : NAND2_X1 port map( A1 => n74, A2 => n288, ZN => n4);
U351 : INV_X1 port map( A => n288, ZN => n34);
U352 : NAND2_X1 port map( A1 => n96, A2 => n101, ZN => n36);
U353 : NAND2_X1 port map( A1 => n385, A2 => n123, ZN => n57);
U355 : NAND2_X1 port map( A1 => n124, A2 => n139, ZN => n61);
U357 : XNOR2_X1 port map( A => n11, B => n67, ZN => product(2));
U359 : NAND2_X1 port map( A1 => n108, A2 => n113, ZN => n45);
U360 : NAND2_X1 port map( A1 => n92, A2 => n95, ZN => n31);
U361 : INV_X1 port map( A => n69, ZN => n67);
U362 : OAI21_X1 port map( B1 => n46, B2 => n44, A => n45, ZN => n43);
U363 : INV_X1 port map( A => n44, ZN => n76);
U364 : NOR2_X1 port map( A1 => n44, A2 => n317, ZN => n39);
U365 : NOR2_X1 port map( A1 => n108, A2 => n113, ZN => n44);
U366 : NAND2_X1 port map( A1 => n104, A2 => n106, ZN => n327);
U367 : NAND2_X1 port map( A1 => n104, A2 => n109, ZN => n328);
U368 : NAND2_X1 port map( A1 => n106, A2 => n109, ZN => n329);
U369 : NAND3_X1 port map( A1 => n327, A2 => n328, A3 => n329, ZN => n101);
U370 : XNOR2_X1 port map( A => n158, B => n146, ZN => n106);
U371 : NAND2_X1 port map( A1 => n102, A2 => n107, ZN => n42);
U373 : AOI21_X1 port map( B1 => n325, B2 => n55, A => n52, ZN => n50);
U374 : OAI22_X1 port map( A1 => n224, A2 => n378, B1 => n378, B2 => n376, ZN
=> n168);
U375 : OAI22_X1 port map( A1 => n224, A2 => n378, B1 => n378, B2 => n376, ZN
=> n167);
U376 : OAI22_X1 port map( A1 => n224, A2 => n378, B1 => n378, B2 => n376, ZN
=> n170);
U377 : OAI22_X1 port map( A1 => n224, A2 => n378, B1 => n378, B2 => n376, ZN
=> n169);
U378 : OAI22_X1 port map( A1 => n224, A2 => n378, B1 => n200, B2 => n376, ZN
=> n166);
U379 : OAI22_X1 port map( A1 => n224, A2 => n378, B1 => n378, B2 => n376, ZN
=> n140);
U380 : OAI22_X1 port map( A1 => n224, A2 => n378, B1 => n378, B2 => n376, ZN
=> n172);
U381 : OAI22_X1 port map( A1 => n224, A2 => n378, B1 => n378, B2 => n376, ZN
=> n324);
U382 : NAND2_X1 port map( A1 => n219, A2 => n227, ZN => n330);
U385 : NAND2_X1 port map( A1 => n227, A2 => n219, ZN => n223);
U386 : XNOR2_X1 port map( A => n361, B => n363, ZN => n227);
U395 : XNOR2_X1 port map( A => n373, B => n356, ZN => n173);
U396 : INV_X1 port map( A => n134, ZN => n165);
U397 : INV_X1 port map( A => n99, ZN => n100);
U399 : XOR2_X1 port map( A => n373, B => n371, Z => n217);
U400 : NOR2_X1 port map( A1 => n124, A2 => n139, ZN => n60);
U401 : INV_X1 port map( A => n131, ZN => n157);
U403 : XNOR2_X1 port map( A => n369, B => n371, ZN => n225);
U404 : OAI22_X1 port map( A1 => n200, A2 => n224, B1 => n200, B2 => n376, ZN
=> n134);
U406 : INV_X1 port map( A => n54, ZN => n52);
U407 : OAI21_X1 port map( B1 => n38, B2 => n21, A => n22, ZN => n20);
U408 : NAND2_X1 port map( A1 => n28, A2 => n321, ZN => n21);
U409 : NOR2_X1 port map( A1 => n96, A2 => n101, ZN => n35);
U410 : XNOR2_X1 port map( A => n8, B => n284, ZN => product(5));
U411 : XOR2_X1 port map( A => n10, B => n62, Z => product(3));
U412 : OAI21_X1 port map( B1 => n60, B2 => n62, A => n61, ZN => n59);
U413 : NAND2_X1 port map( A1 => n172, A2 => n140, ZN => n69);
U417 : XNOR2_X1 port map( A => n361, B => n356, ZN => n200);
U423 : XOR2_X1 port map( A => n361, B => n359, Z => n220);
U424 : OAI21_X1 port map( B1 => n45, B2 => n41, A => n42, ZN => n40);
U425 : INV_X1 port map( A => n317, ZN => n75);
U426 : AOI21_X1 port map( B1 => n37, B2 => n28, A => n313, ZN => n27);
U427 : INV_X1 port map( A => n319, ZN => n73);
U428 : AOI21_X1 port map( B1 => n29, B2 => n321, A => n24, ZN => n22);
U429 : NOR2_X1 port map( A1 => n35, A2 => n319, ZN => n28);
U430 : OAI21_X1 port map( B1 => n36, B2 => n30, A => n31, ZN => n29);
U431 : INV_X1 port map( A => n15, ZN => n70);
U433 : INV_X1 port map( A => n47, ZN => n46);
U434 : AOI21_X1 port map( B1 => n39, B2 => n47, A => n40, ZN => n38);
U435 : NAND2_X1 port map( A1 => n118, A2 => n380, ZN => n54);
U436 : OAI22_X1 port map( A1 => n182, A2 => n222, B1 => n182, B2 => n334, ZN
=> n128);
U437 : OAI22_X1 port map( A1 => n222, A2 => n379, B1 => n379, B2 => n334, ZN
=> n154);
U438 : OAI22_X1 port map( A1 => n222, A2 => n379, B1 => n182, B2 => n334, ZN
=> n89);
U439 : OAI22_X1 port map( A1 => n222, A2 => n379, B1 => n379, B2 => n334, ZN
=> n151);
U440 : OAI22_X1 port map( A1 => n222, A2 => n379, B1 => n379, B2 => n334, ZN
=> n153);
U441 : OAI22_X1 port map( A1 => n222, A2 => n379, B1 => n379, B2 => n334, ZN
=> n150);
U446 : OAI22_X1 port map( A1 => n222, A2 => n379, B1 => n379, B2 => n334, ZN
=> n138);
U447 : OAI22_X1 port map( A1 => n222, A2 => n379, B1 => n379, B2 => n334, ZN
=> n155);
U450 : NAND2_X2 port map( A1 => n226, A2 => n218, ZN => n222);
U451 : XNOR2_X1 port map( A => n280, B => n356, ZN => n191);
U454 : XOR2_X1 port map( A => n365, B => n363, Z => n219);
U456 : XNOR2_X1 port map( A => n314, B => n1, ZN => product(12));
U457 : OAI22_X1 port map( A1 => n173, A2 => n221, B1 => n173, B2 => n336, ZN
=> n125);
U458 : AOI21_X1 port map( B1 => n20, B2 => n322, A => n17, ZN => n15);
U459 : OAI22_X1 port map( A1 => n318, A2 => n381, B1 => n173, B2 => n225, ZN
=> n83);
U460 : OAI22_X1 port map( A1 => n221, A2 => n381, B1 => n381, B2 => n336, ZN
=> n142);
U461 : OAI22_X1 port map( A1 => n318, A2 => n381, B1 => n381, B2 => n336, ZN
=> n143);
U462 : OAI22_X1 port map( A1 => n221, A2 => n381, B1 => n381, B2 => n336, ZN
=> n144);
U463 : OAI22_X1 port map( A1 => n221, A2 => n381, B1 => n381, B2 => n336, ZN
=> n145);
U464 : OAI22_X1 port map( A1 => n318, A2 => n381, B1 => n381, B2 => n336, ZN
=> n146);
U467 : OAI22_X1 port map( A1 => n318, A2 => n381, B1 => n381, B2 => n336, ZN
=> n137);
U468 : OAI22_X1 port map( A1 => n221, A2 => n381, B1 => n381, B2 => n336, ZN
=> n147);
U475 : XOR2_X1 port map( A => n369, B => n367, Z => n218);
U477 : XOR2_X1 port map( A => n7, B => n316, Z => product(6));
U478 : INV_X1 port map( A => n308, ZN => n37);
U479 : OAI22_X1 port map( A1 => n330, A2 => n382, B1 => n194, B2 => n333, ZN
=> n160);
U480 : OAI22_X1 port map( A1 => n330, A2 => n194, B1 => n194, B2 => n333, ZN
=> n158);
U481 : OAI22_X1 port map( A1 => n223, A2 => n382, B1 => n382, B2 => n333, ZN
=> n161);
U482 : OAI22_X1 port map( A1 => n223, A2 => n194, B1 => n194, B2 => n333, ZN
=> n159);
U483 : OAI22_X1 port map( A1 => n330, A2 => n382, B1 => n382, B2 => n333, ZN
=> n139);
U484 : OAI22_X1 port map( A1 => n223, A2 => n194, B1 => n382, B2 => n333, ZN
=> n162);
U485 : OAI22_X1 port map( A1 => n223, A2 => n194, B1 => n191, B2 => n333, ZN
=> n99);
U486 : OAI22_X1 port map( A1 => n191, A2 => n330, B1 => n191, B2 => n333, ZN
=> n131);
U487 : OAI22_X1 port map( A1 => n223, A2 => n194, B1 => n194, B2 => n333, ZN
=> n163);
clock_r_REG203_S4 : DFF_X1 port map( D => a(7), CK => clock, Q => n374, QN
=> n_1008);
clock_r_REG210_S4 : DFF_X1 port map( D => a(6), CK => clock, Q => n372, QN
=> n_1009);
clock_r_REG211_S5 : DFF_X1 port map( D => n372, CK => clock, Q => n371, QN
=> n_1010);
clock_r_REG214_S4 : DFF_X1 port map( D => a(5), CK => clock, Q => n370, QN
=> n_1011);
clock_r_REG215_S5 : DFF_X1 port map( D => n370, CK => clock, Q => n369, QN
=> n379);
clock_r_REG218_S4 : DFF_X1 port map( D => a(4), CK => clock, Q => n368, QN
=> n_1012);
clock_r_REG219_S5 : DFF_X1 port map( D => n368, CK => clock, Q => n367, QN
=> n377);
clock_r_REG222_S4 : DFF_X1 port map( D => a(3), CK => clock, Q => n366, QN
=> n_1013);
clock_r_REG223_S5 : DFF_X1 port map( D => n366, CK => clock, Q => n365, QN
=> n382);
clock_r_REG226_S4 : DFF_X1 port map( D => a(2), CK => clock, Q => n364, QN
=> n_1014);
clock_r_REG227_S5 : DFF_X1 port map( D => n364, CK => clock, Q => n363, QN
=> n_1015);
clock_r_REG230_S4 : DFF_X1 port map( D => a(1), CK => clock, Q => n362, QN
=> n_1016);
clock_r_REG231_S5 : DFF_X1 port map( D => n362, CK => clock, Q => n361, QN
=> n378);
clock_r_REG234_S4 : DFF_X1 port map( D => a(0), CK => clock, Q => n360, QN
=> n_1017);
clock_r_REG235_S5 : DFF_X1 port map( D => n360, CK => clock, Q => n359, QN
=> n376);
clock_r_REG314_S2 : DFF_X1 port map( D => b(7), CK => clock, Q => n358, QN
=> n_1018);
clock_r_REG315_S3 : DFF_X1 port map( D => n358, CK => clock, Q => n357, QN
=> n_1019);
clock_r_REG316_S4 : DFF_X1 port map( D => n357, CK => clock, Q => n356, QN
=> n_1020);
clock_r_REG204_S5 : DFF_X1 port map( D => n374, CK => clock, Q => n373, QN
=> n381);
U384 : CLKBUF_X2 port map( A => n227, Z => n333);
U238 : CLKBUF_X1 port map( A => n365, Z => n280);
U239 : OAI22_X1 port map( A1 => n222, A2 => n379, B1 => n379, B2 => n334, ZN
=> n152);
U240 : NAND2_X1 port map( A1 => n220, A2 => n376, ZN => n224);
U247 : BUF_X1 port map( A => n225, Z => n336);
U249 : NAND2_X1 port map( A1 => n324, A2 => n67, ZN => n62);
U276 : AND2_X1 port map( A1 => n162, A2 => n169, ZN => n380);
U277 : INV_X1 port map( A => n280, ZN => n194);
U283 : XOR2_X1 port map( A => n167, B => n160, Z => n383);
U284 : AND2_X1 port map( A1 => n160, A2 => n167, ZN => n384);
U290 : XOR2_X1 port map( A => n169, B => n162, Z => n385);
U315 : INV_X1 port map( A => n324, ZN => n11);
end SYN_USE_DEFA_ARCH_NAME;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_project2.all;
entity mac_DW01_add_1 is
port( A, B : in std_logic_vector (18 downto 0); CI : in std_logic; SUM :
out std_logic_vector (18 downto 0); CO : out std_logic; clock : in
std_logic);
end mac_DW01_add_1;
architecture SYN_USE_DEFA_ARCH_NAME of mac_DW01_add_1 is
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component OR2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component DFF_X1
port( D, CK : in std_logic; Q, QN : out std_logic);
end component;
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
component XNOR2_X1
port( A, B : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component NOR2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
signal n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16,
n17, n20, n21, n22, n23, n25, n27, n28, n29, n30, n31, n33, n35, n36, n37
, n38, n39, n43, n44, n45, n46, n47, n51, n52, n53, n54, n55, n59, n60,
n61, n62, n63, n64, n65, n66, n67, n68, n69, n70, n71, n72, n73, n74, n75
, n76, n77, n78, n79, n80, n81, n82, n83, n84, n85, n86, n87, n88, n90,
n92, n95, n97, n99, n105, n106, n109, n110, SUM_2_port, SUM_3_port,
SUM_4_port, SUM_5_port, SUM_6_port, SUM_7_port, SUM_8_port, SUM_9_port,
SUM_10_port, SUM_11_port, SUM_12_port, SUM_13_port, SUM_14_port,
SUM_15_port, SUM_16_port, SUM_17_port, SUM_18_port, n178, n180, n181,
n182, n183, n186, n188, n189, n190, n191, n192, n193, n194, n195, n218,
n219, n220, n221, n222, n223, n224, n225, n226, n227, n228, n229, n230,
n231, n232, n233, n234, n235, n236, n238, n239, n240, n241, n242, n243,
SUM_1_port, n_1024, n_1025, n_1026, n_1027, n_1028, n_1029, n_1030,
n_1031, n_1032, n_1033, n_1034, n_1035, n_1036, n_1037 : std_logic;
begin
SUM <= ( SUM_18_port, SUM_17_port, SUM_16_port, SUM_15_port, SUM_14_port,
SUM_13_port, SUM_12_port, SUM_11_port, SUM_10_port, SUM_9_port,
SUM_8_port, SUM_7_port, SUM_6_port, SUM_5_port, SUM_4_port, SUM_3_port,
SUM_2_port, SUM_1_port, A(0) );
U138 : OR2_X1 port map( A1 => A(5), A2 => B(5), ZN => n178);
U140 : NOR2_X1 port map( A1 => A(7), A2 => B(7), ZN => n180);
U141 : AOI21_X1 port map( B1 => n44, B2 => n220, A => n238, ZN => n181);
U142 : NOR2_X1 port map( A1 => A(7), A2 => B(7), ZN => n65);
U143 : OAI21_X1 port map( B1 => n181, B2 => n37, A => n38, ZN => n182);
U144 : OAI21_X1 port map( B1 => n39, B2 => n37, A => n38, ZN => n183);
U145 : OAI21_X1 port map( B1 => n39, B2 => n37, A => n38, ZN => n36);
U148 : AOI21_X1 port map( B1 => n36, B2 => n194, A => n33, ZN => n186);
U150 : OAI21_X1 port map( B1 => n186, B2 => n29, A => n30, ZN => n188);
U151 : AOI21_X1 port map( B1 => n28, B2 => n195, A => n25, ZN => n189);
U153 : INV_X1 port map( A => n35, ZN => n33);
U155 : INV_X1 port map( A => n27, ZN => n25);
U156 : NOR2_X1 port map( A1 => n68, A2 => n180, ZN => n63);
U158 : NAND2_X1 port map( A1 => n242, A2 => n224, ZN => n10);
U160 : NAND2_X1 port map( A1 => n239, A2 => n225, ZN => n8);
U162 : NAND2_X1 port map( A1 => n99, A2 => n38, ZN => n6);
U163 : INV_X1 port map( A => n37, ZN => n99);
U164 : NAND2_X1 port map( A1 => n95, A2 => n22, ZN => n2);
U165 : INV_X1 port map( A => n21, ZN => n95);
U166 : NAND2_X1 port map( A1 => n97, A2 => n30, ZN => n4);
U167 : INV_X1 port map( A => n29, ZN => n97);
U168 : XOR2_X1 port map( A => n75, B => n14, Z => SUM_5_port);
U169 : NAND2_X1 port map( A1 => n178, A2 => n74, ZN => n14);
U170 : AOI21_X1 port map( B1 => n80, B2 => n76, A => n77, ZN => n75);
U171 : INV_X1 port map( A => n78, ZN => n76);
U172 : NAND2_X1 port map( A1 => n220, A2 => n227, ZN => n7);
U173 : NAND2_X1 port map( A1 => n195, A2 => n27, ZN => n3);
U174 : NAND2_X1 port map( A1 => n219, A2 => n226, ZN => n11);
U175 : NAND2_X1 port map( A1 => n194, A2 => n35, ZN => n5);
U176 : NAND2_X1 port map( A1 => n221, A2 => n228, ZN => n9);
U177 : XOR2_X1 port map( A => n92, B => n17, Z => SUM_2_port);
U178 : XOR2_X1 port map( A => n70, B => n13, Z => SUM_6_port);
U179 : NAND2_X1 port map( A1 => n106, A2 => n69, ZN => n13);
U180 : XNOR2_X1 port map( A => n67, B => n12, ZN => SUM_7_port);
U181 : NAND2_X1 port map( A1 => n105, A2 => n66, ZN => n12);
U182 : XNOR2_X1 port map( A => n80, B => n15, ZN => SUM_4_port);
U183 : NAND2_X1 port map( A1 => n76, A2 => n79, ZN => n15);
U184 : XNOR2_X1 port map( A => n86, B => n16, ZN => SUM_3_port);
U185 : NAND2_X1 port map( A1 => n109, A2 => n85, ZN => n16);
U186 : INV_X1 port map( A => n79, ZN => n77);
U187 : XNOR2_X1 port map( A => B(18), B => n236, ZN => n190);
U188 : NOR2_X1 port map( A1 => A(3), A2 => B(3), ZN => n84);
U189 : NOR2_X1 port map( A1 => A(2), A2 => B(2), ZN => n87);
U190 : NAND2_X1 port map( A1 => A(10), A2 => B(10), ZN => n51);
U191 : NAND2_X1 port map( A1 => A(12), A2 => B(12), ZN => n43);
U192 : NAND2_X1 port map( A1 => A(8), A2 => B(8), ZN => n59);
U193 : NAND2_X1 port map( A1 => n232, A2 => n230, ZN => n35);
U194 : NAND2_X1 port map( A1 => n234, A2 => B(16), ZN => n27);
U195 : NAND2_X1 port map( A1 => n231, A2 => n229, ZN => n38);
U196 : NAND2_X1 port map( A1 => A(11), A2 => B(11), ZN => n46);
U197 : NAND2_X1 port map( A1 => A(9), A2 => B(9), ZN => n54);
U198 : NAND2_X1 port map( A1 => n233, A2 => B(15), ZN => n30);
U199 : NAND2_X1 port map( A1 => n235, A2 => B(17), ZN => n22);
U200 : NOR2_X1 port map( A1 => n231, A2 => n229, ZN => n37);
U201 : NAND2_X1 port map( A1 => A(2), A2 => B(2), ZN => n88);
U202 : NOR2_X1 port map( A1 => A(11), A2 => B(11), ZN => n45);
U203 : NOR2_X1 port map( A1 => A(9), A2 => B(9), ZN => n53);
U204 : NOR2_X1 port map( A1 => n233, A2 => B(15), ZN => n29);
U205 : NOR2_X1 port map( A1 => n235, A2 => B(17), ZN => n21);
U206 : OR2_X1 port map( A1 => A(10), A2 => B(10), ZN => n191);
U207 : OR2_X1 port map( A1 => A(12), A2 => B(12), ZN => n192);
U208 : OR2_X1 port map( A1 => A(8), A2 => B(8), ZN => n193);
U209 : OR2_X1 port map( A1 => n232, A2 => n230, ZN => n194);
U210 : OR2_X1 port map( A1 => n234, A2 => B(16), ZN => n195);
U212 : NAND2_X1 port map( A1 => A(5), A2 => B(5), ZN => n74);
U213 : NOR2_X1 port map( A1 => A(5), A2 => B(5), ZN => n73);
U214 : XNOR2_X1 port map( A => n20, B => n190, ZN => SUM_18_port);
U220 : XOR2_X1 port map( A => n55, B => n10, Z => SUM_9_port);
U221 : OAI21_X1 port map( B1 => n55, B2 => n222, A => n224, ZN => n52);
U222 : AOI21_X1 port map( B1 => n218, B2 => n219, A => n241, ZN => n55);
U226 : OAI21_X1 port map( B1 => n92, B2 => n87, A => n88, ZN => n86);
U227 : INV_X1 port map( A => n87, ZN => n110);
U228 : NAND2_X1 port map( A1 => n110, A2 => n88, ZN => n17);
U229 : NOR2_X1 port map( A1 => n78, A2 => n73, ZN => n71);
U230 : INV_X1 port map( A => n81, ZN => n80);
U231 : NAND2_X1 port map( A1 => n71, A2 => n63, ZN => n61);
U232 : XNOR2_X1 port map( A => n218, B => n11, ZN => SUM_8_port);
U233 : OAI21_X1 port map( B1 => n81, B2 => n61, A => n62, ZN => n60);
U234 : OAI21_X1 port map( B1 => n65, B2 => n69, A => n66, ZN => n64);
U235 : INV_X1 port map( A => n180, ZN => n105);
U236 : AOI21_X1 port map( B1 => n82, B2 => n90, A => n83, ZN => n81);
U237 : AOI21_X1 port map( B1 => n63, B2 => n72, A => n64, ZN => n62);
U238 : NAND2_X1 port map( A1 => A(6), A2 => B(6), ZN => n69);
U240 : NAND2_X1 port map( A1 => A(1), A2 => B(1), ZN => n92);
U241 : INV_X1 port map( A => n68, ZN => n106);
U242 : OAI21_X1 port map( B1 => n70, B2 => n68, A => n69, ZN => n67);
U243 : NOR2_X1 port map( A1 => A(6), A2 => B(6), ZN => n68);
U244 : INV_X1 port map( A => n84, ZN => n109);
U245 : NOR2_X1 port map( A1 => n87, A2 => n84, ZN => n82);
U246 : OAI21_X1 port map( B1 => n84, B2 => n88, A => n85, ZN => n83);
U247 : AOI21_X1 port map( B1 => n80, B2 => n71, A => n72, ZN => n70);
U248 : OAI21_X1 port map( B1 => n73, B2 => n79, A => n74, ZN => n72);
U249 : NAND2_X1 port map( A1 => A(4), A2 => B(4), ZN => n79);
U250 : NOR2_X1 port map( A1 => A(4), A2 => B(4), ZN => n78);
U251 : NAND2_X1 port map( A1 => A(3), A2 => B(3), ZN => n85);
U252 : AOI21_X1 port map( B1 => n182, B2 => n194, A => n33, ZN => n31);
U253 : XOR2_X1 port map( A => n23, B => n2, Z => SUM_17_port);
U254 : OAI21_X1 port map( B1 => n189, B2 => n21, A => n22, ZN => n20);
U255 : AOI21_X1 port map( B1 => n188, B2 => n195, A => n25, ZN => n23);
U256 : XNOR2_X1 port map( A => n188, B => n3, ZN => SUM_16_port);
U257 : OAI21_X1 port map( B1 => n31, B2 => n29, A => n30, ZN => n28);
U258 : XNOR2_X1 port map( A => n183, B => n5, ZN => SUM_14_port);
U259 : XOR2_X1 port map( A => n186, B => n4, Z => SUM_15_port);
U260 : NAND2_X1 port map( A1 => A(7), A2 => B(7), ZN => n66);
U261 : XOR2_X1 port map( A => n47, B => n8, Z => SUM_11_port);
U262 : XNOR2_X1 port map( A => n52, B => n9, ZN => SUM_10_port);
U263 : XNOR2_X1 port map( A => n44, B => n7, ZN => SUM_12_port);
U264 : XOR2_X1 port map( A => n39, B => n6, Z => SUM_13_port);
U265 : AOI21_X1 port map( B1 => n44, B2 => n220, A => n238, ZN => n39);
U266 : AOI21_X1 port map( B1 => n52, B2 => n221, A => n240, ZN => n47);
clock_r_REG30_S3 : DFF_X1 port map( D => A(18), CK => clock, Q => n236, QN
=> n_1024);
clock_r_REG29_S3 : DFF_X1 port map( D => A(17), CK => clock, Q => n235, QN
=> n_1025);
clock_r_REG47_S3 : DFF_X1 port map( D => A(16), CK => clock, Q => n234, QN
=> n_1026);
clock_r_REG56_S3 : DFF_X1 port map( D => A(15), CK => clock, Q => n233, QN
=> n_1027);
clock_r_REG65_S3 : DFF_X1 port map( D => A(14), CK => clock, Q => n232, QN
=> n_1028);
clock_r_REG28_S3 : DFF_X1 port map( D => A(13), CK => clock, Q => n231, QN
=> n_1029);
clock_r_REG205_S6 : DFF_X1 port map( D => B(14), CK => clock, Q => n230, QN
=> n_1030);
clock_r_REG207_S6 : DFF_X1 port map( D => B(13), CK => clock, Q => n229, QN
=> n_1031);
clock_r_REG102_S3 : DFF_X1 port map( D => n51, CK => clock, Q => n228, QN =>
n240);
clock_r_REG83_S3 : DFF_X1 port map( D => n43, CK => clock, Q => n227, QN =>
n238);
clock_r_REG121_S3 : DFF_X1 port map( D => n59, CK => clock, Q => n226, QN =>
n241);
clock_r_REG92_S3 : DFF_X1 port map( D => n46, CK => clock, Q => n225, QN =>
n_1032);
clock_r_REG112_S3 : DFF_X1 port map( D => n54, CK => clock, Q => n224, QN =>
n_1033);
clock_r_REG27_S3 : DFF_X1 port map( D => n45, CK => clock, Q => n223, QN =>
n239);
clock_r_REG111_S3 : DFF_X1 port map( D => n53, CK => clock, Q => n222, QN =>
n242);
clock_r_REG101_S3 : DFF_X1 port map( D => n191, CK => clock, Q => n221, QN
=> n_1034);
clock_r_REG82_S3 : DFF_X1 port map( D => n192, CK => clock, Q => n220, QN =>
n_1035);
clock_r_REG26_S3 : DFF_X1 port map( D => n193, CK => clock, Q => n219, QN =>
n_1036);
clock_r_REG25_S3 : DFF_X1 port map( D => n60, CK => clock, Q => n218, QN =>
n_1037);
U135 : OAI21_X1 port map( B1 => n47, B2 => n223, A => n225, ZN => n44);
U136 : INV_X1 port map( A => n92, ZN => n90);
U137 : OR2_X1 port map( A1 => A(1), A2 => B(1), ZN => n243);
U139 : AND2_X1 port map( A1 => n243, A2 => n92, ZN => SUM_1_port);
end SYN_USE_DEFA_ARCH_NAME;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_project2.all;
entity counter_address_generator_2_DW01_inc_0 is
port( A : in std_logic_vector (7 downto 0); SUM : out std_logic_vector (7
downto 0));
end counter_address_generator_2_DW01_inc_0;
architecture SYN_rpl of counter_address_generator_2_DW01_inc_0 is
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component HA_X1
port( A, B : in std_logic; CO, S : out std_logic);
end component;
signal carry_7_port, carry_6_port, carry_5_port, carry_4_port, carry_3_port,
carry_2_port : std_logic;
begin
U1_1_6 : HA_X1 port map( A => A(6), B => carry_6_port, CO => carry_7_port, S
=> SUM(6));
U1_1_5 : HA_X1 port map( A => A(5), B => carry_5_port, CO => carry_6_port, S
=> SUM(5));
U1_1_4 : HA_X1 port map( A => A(4), B => carry_4_port, CO => carry_5_port, S
=> SUM(4));
U1_1_3 : HA_X1 port map( A => A(3), B => carry_3_port, CO => carry_4_port, S
=> SUM(3));
U1_1_2 : HA_X1 port map( A => A(2), B => carry_2_port, CO => carry_3_port, S
=> SUM(2));
U1_1_1 : HA_X1 port map( A => A(1), B => A(0), CO => carry_2_port, S =>
SUM(1));
U1 : INV_X1 port map( A => A(0), ZN => SUM(0));
U2 : XOR2_X1 port map( A => carry_7_port, B => A(7), Z => SUM(7));
end SYN_rpl;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_project2.all;
entity counter_address_generator_0_DW01_inc_0 is
port( A : in std_logic_vector (7 downto 0); SUM : out std_logic_vector (7
downto 0));
end counter_address_generator_0_DW01_inc_0;
architecture SYN_rpl of counter_address_generator_0_DW01_inc_0 is
component XOR2_X1
port( A, B : in std_logic; Z : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component HA_X1
port( A, B : in std_logic; CO, S : out std_logic);
end component;
signal carry_7_port, carry_6_port, carry_5_port, carry_4_port, carry_3_port,
carry_2_port : std_logic;
begin
U1_1_6 : HA_X1 port map( A => A(6), B => carry_6_port, CO => carry_7_port, S
=> SUM(6));
U1_1_5 : HA_X1 port map( A => A(5), B => carry_5_port, CO => carry_6_port, S
=> SUM(5));
U1_1_4 : HA_X1 port map( A => A(4), B => carry_4_port, CO => carry_5_port, S
=> SUM(4));
U1_1_3 : HA_X1 port map( A => A(3), B => carry_3_port, CO => carry_4_port, S
=> SUM(3));
U1_1_2 : HA_X1 port map( A => A(2), B => carry_2_port, CO => carry_3_port, S
=> SUM(2));
U1_1_1 : HA_X1 port map( A => A(1), B => A(0), CO => carry_2_port, S =>
SUM(1));
U1 : INV_X1 port map( A => A(0), ZN => SUM(0));
U2 : XOR2_X1 port map( A => carry_7_port, B => A(7), Z => SUM(7));
end SYN_rpl;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_project2.all;
entity ramR is
port( clock, write_enable, read_enable : in std_logic; address : in
std_logic_vector (2 downto 0); datain : in std_logic_vector (18
downto 0); dataout : out std_logic_vector (18 downto 0));
end ramR;
architecture SYN_ramR of ramR is
component NAND3_X1
port( A1, A2, A3 : in std_logic; ZN : out std_logic);
end component;
component DFF_X1
port( D, CK : in std_logic; Q, QN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component NAND4_X1
port( A1, A2, A3, A4 : in std_logic; ZN : out std_logic);
end component;
component AOI22_X1
port( A1, A2, B1, B2 : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component NOR2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component OAI22_X1
port( A1, A2, B1, B2 : in std_logic; ZN : out std_logic);
end component;
component CLKBUF_X1
port( A : in std_logic; Z : out std_logic);
end component;
signal n1176, n1177, n1178, n1179, n1180, n1181, n1182, n1183, n1184, n1185,
n1186, n1187, n1188, n1189, n1190, n1191, n1192, n1193, n1194,
ram_0_18_port, ram_0_17_port, ram_0_16_port, ram_0_15_port, ram_0_14_port
, ram_0_13_port, ram_0_12_port, ram_0_11_port, ram_0_10_port,
ram_0_9_port, ram_0_8_port, ram_0_7_port, ram_0_6_port, ram_0_5_port,
ram_0_4_port, ram_0_3_port, ram_0_2_port, ram_0_1_port, ram_0_0_port,
ram_1_18_port, ram_1_17_port, ram_1_16_port, ram_1_15_port, ram_1_14_port
, ram_1_13_port, ram_1_12_port, ram_1_11_port, ram_1_10_port,
ram_1_9_port, ram_1_8_port, ram_1_7_port, ram_1_6_port, ram_1_5_port,
ram_1_4_port, ram_1_3_port, ram_1_2_port, ram_1_1_port, ram_1_0_port,
ram_2_18_port, ram_2_17_port, ram_2_16_port, ram_2_15_port, ram_2_14_port
, ram_2_13_port, ram_2_12_port, ram_2_11_port, ram_2_10_port,
ram_2_9_port, ram_2_8_port, ram_2_7_port, ram_2_6_port, ram_2_5_port,
ram_2_4_port, ram_2_3_port, ram_2_2_port, ram_2_1_port, ram_2_0_port,
ram_3_18_port, ram_3_17_port, ram_3_16_port, ram_3_15_port, ram_3_14_port
, ram_3_13_port, ram_3_12_port, ram_3_11_port, ram_3_10_port,
ram_3_9_port, ram_3_8_port, ram_3_7_port, ram_3_6_port, ram_3_5_port,
ram_3_4_port, ram_3_3_port, ram_3_2_port, ram_3_1_port, ram_3_0_port,
ram_4_18_port, ram_4_17_port, ram_4_16_port, ram_4_15_port, ram_4_14_port
, ram_4_13_port, ram_4_12_port, ram_4_11_port, ram_4_10_port,
ram_4_9_port, ram_4_8_port, ram_4_7_port, ram_4_6_port, ram_4_5_port,
ram_4_4_port, ram_4_3_port, ram_4_2_port, ram_4_1_port, ram_4_0_port,
ram_5_18_port, ram_5_17_port, ram_5_16_port, ram_5_15_port, ram_5_14_port
, ram_5_13_port, ram_5_12_port, ram_5_11_port, ram_5_10_port,
ram_5_9_port, ram_5_8_port, ram_5_7_port, ram_5_6_port, ram_5_5_port,
ram_5_4_port, ram_5_3_port, ram_5_2_port, ram_5_1_port, ram_5_0_port,
ram_6_18_port, ram_6_17_port, ram_6_16_port, ram_6_15_port, ram_6_14_port
, ram_6_13_port, ram_6_12_port, ram_6_11_port, ram_6_10_port,
ram_6_9_port, ram_6_8_port, ram_6_7_port, ram_6_6_port, ram_6_5_port,
ram_6_4_port, ram_6_3_port, ram_6_2_port, ram_6_1_port, ram_6_0_port,
ram_7_18_port, ram_7_17_port, ram_7_16_port, ram_7_15_port, ram_7_14_port
, ram_7_13_port, ram_7_12_port, ram_7_11_port, ram_7_10_port,
ram_7_9_port, ram_7_8_port, ram_7_7_port, ram_7_6_port, ram_7_5_port,
ram_7_4_port, ram_7_3_port, ram_7_2_port, ram_7_1_port, ram_7_0_port, N30
, N31, N32, N33, N34, N35, N36, N37, N38, N39, N40, N41, N42, N43, N44,
N45, N46, N47, N48, n2, n19, n26, n28, n29, n31_port, n33_port, n35_port,
n37_port, n38_port, n39_port, n40_port, n41_port, n42_port, n43_port,
n44_port, n45_port, n46_port, n47_port, n48_port, n49, n50, n51, n52, n53
, n54, n55, n57, n59, n1, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13,
n14, n15, n16, n17, n18, n20, n21, n22, n23, n24, n25, n27, n30_port,
n32_port, n34_port, n36_port, n56, n58, n402, n403, n404, n405, n406,
n407, n408, n409, n410, n411, n412, n413, n414, n415, n416, n417, n418,
n419, n420, n421, n422, n423, n424, n425, n426, n427, n428, n429, n430,
n431, n432, n433, n434, n435, n436, n437, n438, n439, n440, n441, n442,
n443, n444, n445, n446, n447, n448, n449, n450, n451, n452, n453, n454,
n455, n456, n457, n458, n459, n460, n461, n462, n463, n464, n465, n466,
n467, n468, n469, n470, n471, n472, n473, n474, n475, n476, n477, n478,
n479, n480, n481, n482, n483, n484, n485, n486, n487, n488, n489, n490,
n491, n663, n664, n665, n666, n667, n668, n669, n670, n671, n672, n673,
n674, n675, n676, n677, n678, n679, n680, n681, n682, n683, n684, n685,
n686, n687, n688, n689, n690, n691, n692, n693, n694, n695, n696, n697,
n698, n699, n700, n701, n702, n703, n704, n705, n706, n707, n708, n709,
n710, n711, n712, n713, n714, n715, n716, n717, n718, n719, n720, n721,
n722, n723, n724, n725, n726, n727, n728, n729, n730, n731, n732, n733,
n734, n735, n736, n737, n738, n739, n740, n741, n742, n743, n744, n745,
n746, n747, n748, n749, n750, n751, n752, n753, n754, n755, n756, n757,
n758, n759, n760, n761, n762, n763, n764, n765, n766, n767, n768, n769,
n770, n771, n772, n773, n774, n775, n776, n777, n778, n779, n780, n781,
n782, n783, n784, n785, n786, n787, n788, n789, n790, n791, n792, n793,
n794, n795, n796, n797, n798, n799, n800, n801, n802, n803, n804, n805,
n806, n807, n808, n809, n810, n811, n812, n813, n814, n1195, n1196, n1197
, n1198, n1199, n1200, n1201, n1202, n1203, n1204, n1205, n1206, n1207,
n1208, n1209, n1210, n1211, n1212, n1213, n1214, n1215, n1216, n1217,
n1218, n1219, n1220, n1221, n1222, n1223, n1224, n1225, n1226, n1227,
n1228, n1229, n1230, n1231, n1232, n1233, n1234, n1235, n1236, n1237,
n1238, n1239, n1240, n1241, n1242, n1243, n1244, n1245, n1246, n1247,
n1248, n1249, n1250, n1251, n1252, n1253, n1254, n1255, n1256, n1257,
n1258, n1259, n1260, n1261, n1262, n1263, n1264, n1265, n1266, n1267,
n1268, n1269, n1270, n1271, n1272, n1273, n1274, n1275, n1276, n1277,
n1278, n1279, n1280, n1281, n1282, n1283, n1284, n1285, n1286, n1287,
n1288, n1289, n1290, n1291, n1292, n1293, n1294, n1295, n1296, n1297,
n1298, n1299, n1300, n1301, n1302, n1303, n1304, n1305, n1306, n1307,
n1308, n1309, n1310, n1311, n1312, n1313, n1314, n1315, n1316, n1317,
n1318, n1319, n1320, n1321, n1322, n1323, n1324, n1325, n1326, n1327,
n1328, n1329, n1330, n1331, n1332, n1333, n1334, n1335, n1336, n1337,
n1338, n1339, n1340, n1341, n1342, n1343, n1344, n1345, n1346, n1347,
n1348, n1349, n1350, n1351, n1352, n1353, n1354, n1355, n1356, n1357,
n1358, n1359, n1360, n1361, n1362, n1363, n1364, n1365 : std_logic;
begin
U229 : NAND3_X1 port map( A1 => n26, A2 => n471, A3 => address(0), ZN => n2)
;
U2 : CLKBUF_X1 port map( A => read_enable, Z => n461);
U3 : AND2_X1 port map( A1 => write_enable, A2 => address(2), ZN => n26);
U4 : INV_X1 port map( A => address(1), ZN => n471);
U5 : INV_X1 port map( A => n35_port, ZN => n464);
U6 : INV_X1 port map( A => n19, ZN => n462);
U7 : INV_X1 port map( A => n2, ZN => n470);
U8 : INV_X1 port map( A => n33_port, ZN => n468);
U9 : INV_X1 port map( A => n57, ZN => n469);
U10 : INV_X1 port map( A => n28, ZN => n467);
U11 : INV_X1 port map( A => n31_port, ZN => n463);
U12 : INV_X1 port map( A => n59, ZN => n465);
U14 : NAND3_X1 port map( A1 => n466, A2 => n471, A3 => n26, ZN => n19);
U15 : AND2_X1 port map( A1 => n4, A2 => n466, ZN => n455);
U16 : AND2_X1 port map( A1 => n1, A2 => n466, ZN => n453);
U17 : AND2_X1 port map( A1 => n3, A2 => n466, ZN => n452);
U18 : AND2_X1 port map( A1 => n5, A2 => n466, ZN => n454);
U19 : NOR2_X1 port map( A1 => n472, A2 => address(2), ZN => n29);
U20 : INV_X1 port map( A => write_enable, ZN => n472);
U22 : NAND3_X1 port map( A1 => address(0), A2 => n26, A3 => address(1), ZN
=> n57);
U25 : NAND3_X1 port map( A1 => n26, A2 => n466, A3 => address(1), ZN => n59)
;
U26 : OAI22_X1 port map( A1 => n470, A2 => n1270, B1 => n2, B2 => n491, ZN
=> ram_5_0_port);
U27 : OAI22_X1 port map( A1 => n470, A2 => n1269, B1 => n2, B2 => n490, ZN
=> ram_5_1_port);
U28 : OAI22_X1 port map( A1 => n470, A2 => n1268, B1 => n2, B2 => n489, ZN
=> ram_5_2_port);
U29 : OAI22_X1 port map( A1 => n470, A2 => n1267, B1 => n2, B2 => n488, ZN
=> ram_5_3_port);
U30 : OAI22_X1 port map( A1 => n470, A2 => n1266, B1 => n2, B2 => n487, ZN
=> ram_5_4_port);
U31 : OAI22_X1 port map( A1 => n470, A2 => n1265, B1 => n2, B2 => n486, ZN
=> ram_5_5_port);
U32 : OAI22_X1 port map( A1 => n470, A2 => n1264, B1 => n2, B2 => n485, ZN
=> ram_5_6_port);
U33 : OAI22_X1 port map( A1 => n470, A2 => n1263, B1 => n2, B2 => n484, ZN
=> ram_5_7_port);
U34 : OAI22_X1 port map( A1 => n470, A2 => n1262, B1 => n2, B2 => n483, ZN
=> ram_5_8_port);
U35 : OAI22_X1 port map( A1 => n470, A2 => n1261, B1 => n2, B2 => n482, ZN
=> ram_5_9_port);
U36 : OAI22_X1 port map( A1 => n470, A2 => n1260, B1 => n2, B2 => n481, ZN
=> ram_5_10_port);
U37 : OAI22_X1 port map( A1 => n470, A2 => n1259, B1 => n2, B2 => n480, ZN
=> ram_5_11_port);
U38 : OAI22_X1 port map( A1 => n470, A2 => n1258, B1 => n2, B2 => n479, ZN
=> ram_5_12_port);
U39 : OAI22_X1 port map( A1 => n470, A2 => n1257, B1 => n2, B2 => n478, ZN
=> ram_5_13_port);
U40 : OAI22_X1 port map( A1 => n470, A2 => n1256, B1 => n2, B2 => n477, ZN
=> ram_5_14_port);
U41 : OAI22_X1 port map( A1 => n470, A2 => n1255, B1 => n2, B2 => n476, ZN
=> ram_5_15_port);
U42 : OAI22_X1 port map( A1 => n470, A2 => n1254, B1 => n2, B2 => n475, ZN
=> ram_5_16_port);
U43 : OAI22_X1 port map( A1 => n470, A2 => n1253, B1 => n2, B2 => n474, ZN
=> ram_5_17_port);
U44 : OAI22_X1 port map( A1 => n470, A2 => n1252, B1 => n2, B2 => n473, ZN
=> ram_5_18_port);
U45 : INV_X1 port map( A => address(0), ZN => n466);
U46 : INV_X1 port map( A => datain(0), ZN => n491);
U47 : INV_X1 port map( A => datain(1), ZN => n490);
U48 : INV_X1 port map( A => datain(2), ZN => n489);
U49 : INV_X1 port map( A => datain(3), ZN => n488);
U50 : INV_X1 port map( A => datain(4), ZN => n487);
U51 : INV_X1 port map( A => datain(5), ZN => n486);
U52 : INV_X1 port map( A => datain(6), ZN => n485);
U53 : INV_X1 port map( A => datain(7), ZN => n484);
U54 : INV_X1 port map( A => datain(8), ZN => n483);
U55 : INV_X1 port map( A => datain(9), ZN => n482);
U56 : INV_X1 port map( A => datain(10), ZN => n481);
U57 : INV_X1 port map( A => datain(11), ZN => n480);
U58 : INV_X1 port map( A => datain(12), ZN => n479);
U59 : INV_X1 port map( A => datain(13), ZN => n478);
U60 : INV_X1 port map( A => datain(14), ZN => n477);
U61 : INV_X1 port map( A => datain(15), ZN => n476);
U62 : INV_X1 port map( A => datain(16), ZN => n475);
U63 : INV_X1 port map( A => datain(17), ZN => n474);
U64 : OAI22_X1 port map( A1 => n468, A2 => n1251, B1 => n491, B2 => n33_port
, ZN => ram_1_0_port);
U65 : OAI22_X1 port map( A1 => n468, A2 => n1250, B1 => n490, B2 => n33_port
, ZN => ram_1_1_port);
U66 : OAI22_X1 port map( A1 => n468, A2 => n1249, B1 => n489, B2 => n33_port
, ZN => ram_1_2_port);
U67 : OAI22_X1 port map( A1 => n468, A2 => n1248, B1 => n488, B2 => n33_port
, ZN => ram_1_3_port);
U68 : OAI22_X1 port map( A1 => n468, A2 => n1247, B1 => n487, B2 => n33_port
, ZN => ram_1_4_port);
U69 : OAI22_X1 port map( A1 => n468, A2 => n1246, B1 => n486, B2 => n33_port
, ZN => ram_1_5_port);
U70 : OAI22_X1 port map( A1 => n468, A2 => n1245, B1 => n485, B2 => n33_port
, ZN => ram_1_6_port);
U71 : OAI22_X1 port map( A1 => n468, A2 => n1244, B1 => n484, B2 => n33_port
, ZN => ram_1_7_port);
U72 : OAI22_X1 port map( A1 => n468, A2 => n1243, B1 => n483, B2 => n33_port
, ZN => ram_1_8_port);
U73 : OAI22_X1 port map( A1 => n468, A2 => n1242, B1 => n482, B2 => n33_port
, ZN => ram_1_9_port);
U74 : OAI22_X1 port map( A1 => n468, A2 => n1241, B1 => n481, B2 => n33_port
, ZN => ram_1_10_port);
U75 : OAI22_X1 port map( A1 => n468, A2 => n1240, B1 => n480, B2 => n33_port
, ZN => ram_1_11_port);
U76 : OAI22_X1 port map( A1 => n468, A2 => n1239, B1 => n479, B2 => n33_port
, ZN => ram_1_12_port);
U77 : OAI22_X1 port map( A1 => n468, A2 => n1238, B1 => n478, B2 => n33_port
, ZN => ram_1_13_port);
U78 : OAI22_X1 port map( A1 => n468, A2 => n1237, B1 => n477, B2 => n33_port
, ZN => ram_1_14_port);
U79 : OAI22_X1 port map( A1 => n468, A2 => n1236, B1 => n476, B2 => n33_port
, ZN => ram_1_15_port);
U80 : OAI22_X1 port map( A1 => n468, A2 => n1235, B1 => n475, B2 => n33_port
, ZN => ram_1_16_port);
U81 : OAI22_X1 port map( A1 => n468, A2 => n1234, B1 => n474, B2 => n33_port
, ZN => ram_1_17_port);
U82 : OAI22_X1 port map( A1 => n468, A2 => n1233, B1 => n473, B2 => n33_port
, ZN => ram_1_18_port);
U83 : OAI22_X1 port map( A1 => n469, A2 => n1346, B1 => n491, B2 => n57, ZN
=> ram_7_0_port);
U84 : OAI22_X1 port map( A1 => n469, A2 => n1345, B1 => n490, B2 => n57, ZN
=> ram_7_1_port);
U85 : OAI22_X1 port map( A1 => n469, A2 => n1344, B1 => n489, B2 => n57, ZN
=> ram_7_2_port);
U86 : OAI22_X1 port map( A1 => n469, A2 => n1343, B1 => n488, B2 => n57, ZN
=> ram_7_3_port);
U87 : OAI22_X1 port map( A1 => n469, A2 => n1342, B1 => n487, B2 => n57, ZN
=> ram_7_4_port);
U88 : OAI22_X1 port map( A1 => n469, A2 => n1341, B1 => n486, B2 => n57, ZN
=> ram_7_5_port);
U89 : OAI22_X1 port map( A1 => n469, A2 => n1340, B1 => n485, B2 => n57, ZN
=> ram_7_6_port);
U90 : OAI22_X1 port map( A1 => n469, A2 => n1339, B1 => n484, B2 => n57, ZN
=> ram_7_7_port);
U91 : OAI22_X1 port map( A1 => n469, A2 => n1338, B1 => n483, B2 => n57, ZN
=> ram_7_8_port);
U92 : OAI22_X1 port map( A1 => n469, A2 => n1337, B1 => n482, B2 => n57, ZN
=> ram_7_9_port);
U93 : OAI22_X1 port map( A1 => n469, A2 => n1336, B1 => n481, B2 => n57, ZN
=> ram_7_10_port);
U94 : OAI22_X1 port map( A1 => n469, A2 => n1335, B1 => n480, B2 => n57, ZN
=> ram_7_11_port);
U95 : OAI22_X1 port map( A1 => n469, A2 => n1334, B1 => n479, B2 => n57, ZN
=> ram_7_12_port);
U96 : OAI22_X1 port map( A1 => n469, A2 => n1333, B1 => n478, B2 => n57, ZN
=> ram_7_13_port);
U97 : OAI22_X1 port map( A1 => n469, A2 => n1332, B1 => n477, B2 => n57, ZN
=> ram_7_14_port);
U98 : OAI22_X1 port map( A1 => n469, A2 => n1331, B1 => n476, B2 => n57, ZN
=> ram_7_15_port);
U99 : OAI22_X1 port map( A1 => n469, A2 => n1330, B1 => n475, B2 => n57, ZN
=> ram_7_16_port);
U100 : OAI22_X1 port map( A1 => n469, A2 => n1329, B1 => n474, B2 => n57, ZN
=> ram_7_17_port);
U101 : OAI22_X1 port map( A1 => n469, A2 => n1328, B1 => n473, B2 => n57, ZN
=> ram_7_18_port);
U102 : OAI22_X1 port map( A1 => n462, A2 => n1232, B1 => n19, B2 => n491, ZN
=> ram_4_0_port);
U103 : OAI22_X1 port map( A1 => n462, A2 => n1231, B1 => n19, B2 => n490, ZN
=> ram_4_1_port);
U104 : OAI22_X1 port map( A1 => n462, A2 => n1230, B1 => n19, B2 => n489, ZN
=> ram_4_2_port);
U105 : OAI22_X1 port map( A1 => n462, A2 => n1229, B1 => n19, B2 => n488, ZN
=> ram_4_3_port);
U106 : OAI22_X1 port map( A1 => n467, A2 => n1327, B1 => n491, B2 => n28, ZN
=> ram_3_0_port);
U107 : OAI22_X1 port map( A1 => n467, A2 => n1326, B1 => n490, B2 => n28, ZN
=> ram_3_1_port);
U108 : OAI22_X1 port map( A1 => n467, A2 => n1325, B1 => n489, B2 => n28, ZN
=> ram_3_2_port);
U109 : OAI22_X1 port map( A1 => n467, A2 => n1324, B1 => n488, B2 => n28, ZN
=> ram_3_3_port);
U110 : OAI22_X1 port map( A1 => n467, A2 => n1323, B1 => n487, B2 => n28, ZN
=> ram_3_4_port);
U111 : OAI22_X1 port map( A1 => n467, A2 => n1322, B1 => n486, B2 => n28, ZN
=> ram_3_5_port);
U112 : OAI22_X1 port map( A1 => n467, A2 => n1321, B1 => n485, B2 => n28, ZN
=> ram_3_6_port);
U113 : OAI22_X1 port map( A1 => n467, A2 => n1320, B1 => n484, B2 => n28, ZN
=> ram_3_7_port);
U114 : OAI22_X1 port map( A1 => n467, A2 => n1319, B1 => n483, B2 => n28, ZN
=> ram_3_8_port);
U115 : OAI22_X1 port map( A1 => n467, A2 => n1318, B1 => n482, B2 => n28, ZN
=> ram_3_9_port);
U116 : OAI22_X1 port map( A1 => n467, A2 => n1317, B1 => n481, B2 => n28, ZN
=> ram_3_10_port);
U117 : OAI22_X1 port map( A1 => n467, A2 => n1316, B1 => n480, B2 => n28, ZN
=> ram_3_11_port);
U118 : OAI22_X1 port map( A1 => n467, A2 => n1315, B1 => n479, B2 => n28, ZN
=> ram_3_12_port);
U119 : OAI22_X1 port map( A1 => n467, A2 => n1314, B1 => n478, B2 => n28, ZN
=> ram_3_13_port);
U120 : OAI22_X1 port map( A1 => n467, A2 => n1313, B1 => n477, B2 => n28, ZN
=> ram_3_14_port);
U121 : OAI22_X1 port map( A1 => n467, A2 => n1312, B1 => n476, B2 => n28, ZN
=> ram_3_15_port);
U122 : OAI22_X1 port map( A1 => n467, A2 => n1311, B1 => n475, B2 => n28, ZN
=> ram_3_16_port);
U123 : OAI22_X1 port map( A1 => n467, A2 => n1310, B1 => n474, B2 => n28, ZN
=> ram_3_17_port);
U124 : OAI22_X1 port map( A1 => n467, A2 => n1309, B1 => n473, B2 => n28, ZN
=> ram_3_18_port);
U125 : OAI22_X1 port map( A1 => n463, A2 => n1308, B1 => n491, B2 =>
n31_port, ZN => ram_2_0_port);
U126 : OAI22_X1 port map( A1 => n463, A2 => n1307, B1 => n490, B2 =>
n31_port, ZN => ram_2_1_port);
U127 : OAI22_X1 port map( A1 => n463, A2 => n1306, B1 => n489, B2 =>
n31_port, ZN => ram_2_2_port);
U128 : OAI22_X1 port map( A1 => n463, A2 => n1305, B1 => n488, B2 =>
n31_port, ZN => ram_2_3_port);
U129 : OAI22_X1 port map( A1 => n463, A2 => n1304, B1 => n487, B2 =>
n31_port, ZN => ram_2_4_port);
U130 : OAI22_X1 port map( A1 => n463, A2 => n1303, B1 => n486, B2 =>
n31_port, ZN => ram_2_5_port);
U131 : OAI22_X1 port map( A1 => n463, A2 => n1302, B1 => n485, B2 =>
n31_port, ZN => ram_2_6_port);
U132 : OAI22_X1 port map( A1 => n463, A2 => n1301, B1 => n484, B2 =>
n31_port, ZN => ram_2_7_port);
U133 : OAI22_X1 port map( A1 => n463, A2 => n1300, B1 => n483, B2 =>
n31_port, ZN => ram_2_8_port);
U134 : OAI22_X1 port map( A1 => n463, A2 => n1299, B1 => n482, B2 =>
n31_port, ZN => ram_2_9_port);
U135 : OAI22_X1 port map( A1 => n463, A2 => n1298, B1 => n481, B2 =>
n31_port, ZN => ram_2_10_port);
U136 : OAI22_X1 port map( A1 => n463, A2 => n1297, B1 => n480, B2 =>
n31_port, ZN => ram_2_11_port);
U137 : OAI22_X1 port map( A1 => n463, A2 => n1296, B1 => n479, B2 =>
n31_port, ZN => ram_2_12_port);
U138 : OAI22_X1 port map( A1 => n463, A2 => n1295, B1 => n478, B2 =>
n31_port, ZN => ram_2_13_port);
U139 : OAI22_X1 port map( A1 => n463, A2 => n1294, B1 => n477, B2 =>
n31_port, ZN => ram_2_14_port);
U140 : OAI22_X1 port map( A1 => n463, A2 => n1293, B1 => n476, B2 =>
n31_port, ZN => ram_2_15_port);
U141 : OAI22_X1 port map( A1 => n463, A2 => n1292, B1 => n475, B2 =>
n31_port, ZN => ram_2_16_port);
U142 : OAI22_X1 port map( A1 => n463, A2 => n1291, B1 => n474, B2 =>
n31_port, ZN => ram_2_17_port);
U143 : OAI22_X1 port map( A1 => n463, A2 => n1290, B1 => n473, B2 =>
n31_port, ZN => ram_2_18_port);
U144 : OAI22_X1 port map( A1 => n465, A2 => n1289, B1 => n491, B2 => n59, ZN
=> ram_6_0_port);
U145 : OAI22_X1 port map( A1 => n465, A2 => n1288, B1 => n490, B2 => n59, ZN
=> ram_6_1_port);
U146 : OAI22_X1 port map( A1 => n465, A2 => n1287, B1 => n489, B2 => n59, ZN
=> ram_6_2_port);
U147 : OAI22_X1 port map( A1 => n465, A2 => n1286, B1 => n488, B2 => n59, ZN
=> ram_6_3_port);
U148 : OAI22_X1 port map( A1 => n465, A2 => n1285, B1 => n487, B2 => n59, ZN
=> ram_6_4_port);
U149 : OAI22_X1 port map( A1 => n465, A2 => n1284, B1 => n486, B2 => n59, ZN
=> ram_6_5_port);
U150 : OAI22_X1 port map( A1 => n465, A2 => n1283, B1 => n485, B2 => n59, ZN
=> ram_6_6_port);
U151 : OAI22_X1 port map( A1 => n465, A2 => n1282, B1 => n484, B2 => n59, ZN
=> ram_6_7_port);
U152 : OAI22_X1 port map( A1 => n465, A2 => n1281, B1 => n483, B2 => n59, ZN
=> ram_6_8_port);
U153 : OAI22_X1 port map( A1 => n465, A2 => n1280, B1 => n482, B2 => n59, ZN
=> ram_6_9_port);
U154 : OAI22_X1 port map( A1 => n465, A2 => n1279, B1 => n481, B2 => n59, ZN
=> ram_6_10_port);
U155 : OAI22_X1 port map( A1 => n465, A2 => n1278, B1 => n480, B2 => n59, ZN
=> ram_6_11_port);
U156 : OAI22_X1 port map( A1 => n465, A2 => n1277, B1 => n479, B2 => n59, ZN
=> ram_6_12_port);
U157 : OAI22_X1 port map( A1 => n465, A2 => n1276, B1 => n478, B2 => n59, ZN
=> ram_6_13_port);
U158 : OAI22_X1 port map( A1 => n465, A2 => n1275, B1 => n477, B2 => n59, ZN
=> ram_6_14_port);
U159 : OAI22_X1 port map( A1 => n465, A2 => n1274, B1 => n476, B2 => n59, ZN
=> ram_6_15_port);
U160 : OAI22_X1 port map( A1 => n465, A2 => n1273, B1 => n475, B2 => n59, ZN
=> ram_6_16_port);
U161 : OAI22_X1 port map( A1 => n465, A2 => n1272, B1 => n474, B2 => n59, ZN
=> ram_6_17_port);
U162 : OAI22_X1 port map( A1 => n465, A2 => n1271, B1 => n473, B2 => n59, ZN
=> ram_6_18_port);
U163 : OAI22_X1 port map( A1 => n464, A2 => n1228, B1 => n491, B2 =>
n35_port, ZN => ram_0_0_port);
U164 : OAI22_X1 port map( A1 => n464, A2 => n1227, B1 => n490, B2 =>
n35_port, ZN => ram_0_1_port);
U165 : OAI22_X1 port map( A1 => n464, A2 => n1226, B1 => n489, B2 =>
n35_port, ZN => ram_0_2_port);
U166 : OAI22_X1 port map( A1 => n464, A2 => n1225, B1 => n488, B2 =>
n35_port, ZN => ram_0_3_port);
U167 : OAI22_X1 port map( A1 => n464, A2 => n1224, B1 => n487, B2 =>
n35_port, ZN => ram_0_4_port);
U168 : OAI22_X1 port map( A1 => n464, A2 => n1223, B1 => n486, B2 =>
n35_port, ZN => ram_0_5_port);
U169 : OAI22_X1 port map( A1 => n464, A2 => n1222, B1 => n485, B2 =>
n35_port, ZN => ram_0_6_port);
U170 : OAI22_X1 port map( A1 => n464, A2 => n1221, B1 => n484, B2 =>
n35_port, ZN => ram_0_7_port);
U171 : OAI22_X1 port map( A1 => n464, A2 => n1220, B1 => n483, B2 =>
n35_port, ZN => ram_0_8_port);
U172 : OAI22_X1 port map( A1 => n464, A2 => n1219, B1 => n482, B2 =>
n35_port, ZN => ram_0_9_port);
U173 : OAI22_X1 port map( A1 => n464, A2 => n1218, B1 => n481, B2 =>
n35_port, ZN => ram_0_10_port);
U174 : OAI22_X1 port map( A1 => n464, A2 => n1217, B1 => n480, B2 =>
n35_port, ZN => ram_0_11_port);
U175 : OAI22_X1 port map( A1 => n464, A2 => n1216, B1 => n479, B2 =>
n35_port, ZN => ram_0_12_port);
U176 : OAI22_X1 port map( A1 => n464, A2 => n1215, B1 => n478, B2 =>
n35_port, ZN => ram_0_13_port);
U177 : OAI22_X1 port map( A1 => n464, A2 => n1214, B1 => n477, B2 =>
n35_port, ZN => ram_0_14_port);
U178 : OAI22_X1 port map( A1 => n464, A2 => n1213, B1 => n476, B2 =>
n35_port, ZN => ram_0_15_port);
U179 : OAI22_X1 port map( A1 => n464, A2 => n1212, B1 => n475, B2 =>
n35_port, ZN => ram_0_16_port);
U180 : OAI22_X1 port map( A1 => n464, A2 => n1211, B1 => n474, B2 =>
n35_port, ZN => ram_0_17_port);
U181 : OAI22_X1 port map( A1 => n464, A2 => n1210, B1 => n473, B2 =>
n35_port, ZN => ram_0_18_port);
U182 : OAI22_X1 port map( A1 => n462, A2 => n1209, B1 => n487, B2 => n19, ZN
=> ram_4_4_port);
U183 : OAI22_X1 port map( A1 => n462, A2 => n1208, B1 => n486, B2 => n19, ZN
=> ram_4_5_port);
U184 : OAI22_X1 port map( A1 => n462, A2 => n1207, B1 => n485, B2 => n19, ZN
=> ram_4_6_port);
U185 : OAI22_X1 port map( A1 => n462, A2 => n1206, B1 => n484, B2 => n19, ZN
=> ram_4_7_port);
U186 : OAI22_X1 port map( A1 => n462, A2 => n1205, B1 => n483, B2 => n19, ZN
=> ram_4_8_port);
U187 : OAI22_X1 port map( A1 => n462, A2 => n1204, B1 => n482, B2 => n19, ZN
=> ram_4_9_port);
U188 : OAI22_X1 port map( A1 => n462, A2 => n1203, B1 => n481, B2 => n19, ZN
=> ram_4_10_port);
U189 : OAI22_X1 port map( A1 => n462, A2 => n1202, B1 => n480, B2 => n19, ZN
=> ram_4_11_port);
U190 : OAI22_X1 port map( A1 => n462, A2 => n1201, B1 => n479, B2 => n19, ZN
=> ram_4_12_port);
U191 : OAI22_X1 port map( A1 => n462, A2 => n1200, B1 => n478, B2 => n19, ZN
=> ram_4_13_port);
U192 : OAI22_X1 port map( A1 => n462, A2 => n1199, B1 => n477, B2 => n19, ZN
=> ram_4_14_port);
U193 : OAI22_X1 port map( A1 => n462, A2 => n1198, B1 => n476, B2 => n19, ZN
=> ram_4_15_port);
U194 : OAI22_X1 port map( A1 => n462, A2 => n1197, B1 => n475, B2 => n19, ZN
=> ram_4_16_port);
U195 : OAI22_X1 port map( A1 => n462, A2 => n1196, B1 => n474, B2 => n19, ZN
=> ram_4_17_port);
U196 : OAI22_X1 port map( A1 => n462, A2 => n1195, B1 => n473, B2 => n19, ZN
=> ram_4_18_port);
U197 : INV_X1 port map( A => address(2), ZN => n460);
U198 : OAI21_X1 port map( B1 => n461, B2 => n1365, A => n37_port, ZN =>
n1194);
U199 : NAND2_X1 port map( A1 => n461, A2 => N48, ZN => n37_port);
U200 : OAI21_X1 port map( B1 => read_enable, B2 => n1364, A => n38_port, ZN
=> n1193);
U201 : NAND2_X1 port map( A1 => N47, A2 => read_enable, ZN => n38_port);
U202 : OAI21_X1 port map( B1 => read_enable, B2 => n1363, A => n39_port, ZN
=> n1192);
U203 : NAND2_X1 port map( A1 => N46, A2 => read_enable, ZN => n39_port);
U204 : OAI21_X1 port map( B1 => read_enable, B2 => n1362, A => n40_port, ZN
=> n1191);
U205 : NAND2_X1 port map( A1 => N45, A2 => read_enable, ZN => n40_port);
U206 : OAI21_X1 port map( B1 => read_enable, B2 => n1361, A => n41_port, ZN
=> n1190);
U207 : NAND2_X1 port map( A1 => N44, A2 => read_enable, ZN => n41_port);
U208 : OAI21_X1 port map( B1 => read_enable, B2 => n1360, A => n42_port, ZN
=> n1189);
U209 : NAND2_X1 port map( A1 => N43, A2 => read_enable, ZN => n42_port);
U210 : OAI21_X1 port map( B1 => read_enable, B2 => n1359, A => n43_port, ZN
=> n1188);
U211 : NAND2_X1 port map( A1 => N42, A2 => read_enable, ZN => n43_port);
U212 : OAI21_X1 port map( B1 => read_enable, B2 => n1358, A => n44_port, ZN
=> n1187);
U213 : NAND2_X1 port map( A1 => N41, A2 => read_enable, ZN => n44_port);
U214 : OAI21_X1 port map( B1 => read_enable, B2 => n1357, A => n45_port, ZN
=> n1186);
U215 : NAND2_X1 port map( A1 => N40, A2 => n461, ZN => n45_port);
U216 : OAI21_X1 port map( B1 => read_enable, B2 => n1356, A => n46_port, ZN
=> n1185);
U217 : NAND2_X1 port map( A1 => N39, A2 => n461, ZN => n46_port);
U218 : OAI21_X1 port map( B1 => read_enable, B2 => n1355, A => n47_port, ZN
=> n1184);
U219 : NAND2_X1 port map( A1 => N38, A2 => n461, ZN => n47_port);
U220 : OAI21_X1 port map( B1 => read_enable, B2 => n1354, A => n48_port, ZN
=> n1183);
U221 : NAND2_X1 port map( A1 => N37, A2 => n461, ZN => n48_port);
U222 : OAI21_X1 port map( B1 => read_enable, B2 => n1353, A => n49, ZN =>
n1182);
U223 : NAND2_X1 port map( A1 => N36, A2 => n461, ZN => n49);
U224 : OAI21_X1 port map( B1 => n461, B2 => n1352, A => n50, ZN => n1181);
U225 : NAND2_X1 port map( A1 => N35, A2 => n461, ZN => n50);
U226 : OAI21_X1 port map( B1 => n461, B2 => n1351, A => n51, ZN => n1180);
U227 : NAND2_X1 port map( A1 => N34, A2 => read_enable, ZN => n51);
U228 : OAI21_X1 port map( B1 => n461, B2 => n1350, A => n52, ZN => n1179);
U230 : NAND2_X1 port map( A1 => N33, A2 => read_enable, ZN => n52);
U231 : OAI21_X1 port map( B1 => n461, B2 => n1349, A => n53, ZN => n1178);
U232 : NAND2_X1 port map( A1 => N32, A2 => read_enable, ZN => n53);
U233 : OAI21_X1 port map( B1 => n461, B2 => n1348, A => n54, ZN => n1177);
U234 : NAND2_X1 port map( A1 => N31, A2 => read_enable, ZN => n54);
U235 : OAI21_X1 port map( B1 => n461, B2 => n1347, A => n55, ZN => n1176);
U236 : NAND2_X1 port map( A1 => N30, A2 => n461, ZN => n55);
U237 : NOR2_X1 port map( A1 => n460, A2 => address(1), ZN => n1);
U238 : AND2_X1 port map( A1 => n1, A2 => address(0), ZN => n449);
U239 : NOR2_X1 port map( A1 => n460, A2 => n471, ZN => n3);
U240 : AND2_X1 port map( A1 => address(0), A2 => n3, ZN => n448);
U241 : AOI22_X1 port map( A1 => n814, A2 => n449, B1 => n776, B2 => n448, ZN
=> n9);
U242 : NOR2_X1 port map( A1 => address(1), A2 => address(2), ZN => n4);
U243 : AND2_X1 port map( A1 => n4, A2 => address(0), ZN => n451);
U244 : NOR2_X1 port map( A1 => n471, A2 => address(2), ZN => n5);
U245 : AND2_X1 port map( A1 => n5, A2 => address(0), ZN => n450);
U246 : AOI22_X1 port map( A1 => n795, A2 => n451, B1 => n753, B2 => n450, ZN
=> n8);
U247 : AOI22_X1 port map( A1 => n757, A2 => n453, B1 => n715, B2 => n452, ZN
=> n7);
U248 : AOI22_X1 port map( A1 => n696, A2 => n455, B1 => n734, B2 => n454, ZN
=> n6);
U249 : NAND4_X1 port map( A1 => n9, A2 => n8, A3 => n7, A4 => n6, ZN => N48)
;
U250 : AOI22_X1 port map( A1 => n813, A2 => n449, B1 => n775, B2 => n448, ZN
=> n13);
U251 : AOI22_X1 port map( A1 => n794, A2 => n451, B1 => n752, B2 => n450, ZN
=> n12);
U252 : AOI22_X1 port map( A1 => n756, A2 => n453, B1 => n714, B2 => n452, ZN
=> n11);
U253 : AOI22_X1 port map( A1 => n695, A2 => n455, B1 => n733, B2 => n454, ZN
=> n10);
U254 : NAND4_X1 port map( A1 => n13, A2 => n12, A3 => n11, A4 => n10, ZN =>
N47);
U255 : AOI22_X1 port map( A1 => n812, A2 => n449, B1 => n774, B2 => n448, ZN
=> n17);
U256 : AOI22_X1 port map( A1 => n793, A2 => n451, B1 => n751, B2 => n450, ZN
=> n16);
U257 : AOI22_X1 port map( A1 => n755, A2 => n453, B1 => n713, B2 => n452, ZN
=> n15);
U258 : AOI22_X1 port map( A1 => n694, A2 => n455, B1 => n732, B2 => n454, ZN
=> n14);
U259 : NAND4_X1 port map( A1 => n17, A2 => n16, A3 => n15, A4 => n14, ZN =>
N46);
U260 : AOI22_X1 port map( A1 => n811, A2 => n449, B1 => n773, B2 => n448, ZN
=> n22);
U261 : AOI22_X1 port map( A1 => n792, A2 => n451, B1 => n750, B2 => n450, ZN
=> n21);
U262 : AOI22_X1 port map( A1 => n754, A2 => n453, B1 => n712, B2 => n452, ZN
=> n20);
U263 : AOI22_X1 port map( A1 => n693, A2 => n455, B1 => n731, B2 => n454, ZN
=> n18);
U264 : NAND4_X1 port map( A1 => n22, A2 => n21, A3 => n20, A4 => n18, ZN =>
N45);
U265 : AOI22_X1 port map( A1 => n810, A2 => n449, B1 => n772, B2 => n448, ZN
=> n27);
U266 : AOI22_X1 port map( A1 => n791, A2 => n451, B1 => n749, B2 => n450, ZN
=> n25);
U267 : AOI22_X1 port map( A1 => n677, A2 => n453, B1 => n711, B2 => n452, ZN
=> n24);
U268 : AOI22_X1 port map( A1 => n692, A2 => n455, B1 => n730, B2 => n454, ZN
=> n23);
U269 : NAND4_X1 port map( A1 => n27, A2 => n25, A3 => n24, A4 => n23, ZN =>
N44);
U270 : AOI22_X1 port map( A1 => n809, A2 => n449, B1 => n771, B2 => n448, ZN
=> n36_port);
U271 : AOI22_X1 port map( A1 => n790, A2 => n451, B1 => n748, B2 => n450, ZN
=> n34_port);
U272 : AOI22_X1 port map( A1 => n676, A2 => n453, B1 => n710, B2 => n452, ZN
=> n32_port);
U273 : AOI22_X1 port map( A1 => n691, A2 => n455, B1 => n729, B2 => n454, ZN
=> n30_port);
U274 : NAND4_X1 port map( A1 => n36_port, A2 => n34_port, A3 => n32_port, A4
=> n30_port, ZN => N43);
U275 : AOI22_X1 port map( A1 => n808, A2 => n449, B1 => n770, B2 => n448, ZN
=> n403);
U276 : AOI22_X1 port map( A1 => n789, A2 => n451, B1 => n747, B2 => n450, ZN
=> n402);
U277 : AOI22_X1 port map( A1 => n675, A2 => n453, B1 => n709, B2 => n452, ZN
=> n58);
U278 : AOI22_X1 port map( A1 => n690, A2 => n455, B1 => n728, B2 => n454, ZN
=> n56);
U279 : NAND4_X1 port map( A1 => n403, A2 => n402, A3 => n58, A4 => n56, ZN
=> N42);
U280 : AOI22_X1 port map( A1 => n807, A2 => n449, B1 => n769, B2 => n448, ZN
=> n407);
U281 : AOI22_X1 port map( A1 => n788, A2 => n451, B1 => n746, B2 => n450, ZN
=> n406);
U282 : AOI22_X1 port map( A1 => n674, A2 => n453, B1 => n708, B2 => n452, ZN
=> n405);
U283 : AOI22_X1 port map( A1 => n689, A2 => n455, B1 => n727, B2 => n454, ZN
=> n404);
U284 : NAND4_X1 port map( A1 => n407, A2 => n406, A3 => n405, A4 => n404, ZN
=> N41);
U285 : AOI22_X1 port map( A1 => n806, A2 => n449, B1 => n768, B2 => n448, ZN
=> n411);
U286 : AOI22_X1 port map( A1 => n787, A2 => n451, B1 => n745, B2 => n450, ZN
=> n410);
U287 : AOI22_X1 port map( A1 => n673, A2 => n453, B1 => n707, B2 => n452, ZN
=> n409);
U288 : AOI22_X1 port map( A1 => n688, A2 => n455, B1 => n726, B2 => n454, ZN
=> n408);
U289 : NAND4_X1 port map( A1 => n411, A2 => n410, A3 => n409, A4 => n408, ZN
=> N40);
U290 : AOI22_X1 port map( A1 => n805, A2 => n449, B1 => n767, B2 => n448, ZN
=> n415);
U291 : AOI22_X1 port map( A1 => n786, A2 => n451, B1 => n744, B2 => n450, ZN
=> n414);
U292 : AOI22_X1 port map( A1 => n672, A2 => n453, B1 => n706, B2 => n452, ZN
=> n413);
U293 : AOI22_X1 port map( A1 => n687, A2 => n455, B1 => n725, B2 => n454, ZN
=> n412);
U294 : NAND4_X1 port map( A1 => n415, A2 => n414, A3 => n413, A4 => n412, ZN
=> N39);
U295 : AOI22_X1 port map( A1 => n804, A2 => n449, B1 => n766, B2 => n448, ZN
=> n419);
U296 : AOI22_X1 port map( A1 => n785, A2 => n451, B1 => n743, B2 => n450, ZN
=> n418);
U297 : AOI22_X1 port map( A1 => n671, A2 => n453, B1 => n705, B2 => n452, ZN
=> n417);
U298 : AOI22_X1 port map( A1 => n686, A2 => n455, B1 => n724, B2 => n454, ZN
=> n416);
U299 : NAND4_X1 port map( A1 => n419, A2 => n418, A3 => n417, A4 => n416, ZN
=> N38);
U300 : AOI22_X1 port map( A1 => n803, A2 => n449, B1 => n765, B2 => n448, ZN
=> n423);
U301 : AOI22_X1 port map( A1 => n784, A2 => n451, B1 => n742, B2 => n450, ZN
=> n422);
U302 : AOI22_X1 port map( A1 => n670, A2 => n453, B1 => n704, B2 => n452, ZN
=> n421);
U303 : AOI22_X1 port map( A1 => n685, A2 => n455, B1 => n723, B2 => n454, ZN
=> n420);
U304 : NAND4_X1 port map( A1 => n423, A2 => n422, A3 => n421, A4 => n420, ZN
=> N37);
U305 : AOI22_X1 port map( A1 => n802, A2 => n449, B1 => n764, B2 => n448, ZN
=> n427);
U306 : AOI22_X1 port map( A1 => n783, A2 => n451, B1 => n741, B2 => n450, ZN
=> n426);
U307 : AOI22_X1 port map( A1 => n669, A2 => n453, B1 => n703, B2 => n452, ZN
=> n425);
U308 : AOI22_X1 port map( A1 => n684, A2 => n455, B1 => n722, B2 => n454, ZN
=> n424);
U309 : NAND4_X1 port map( A1 => n427, A2 => n426, A3 => n425, A4 => n424, ZN
=> N36);
U310 : AOI22_X1 port map( A1 => n801, A2 => n449, B1 => n763, B2 => n448, ZN
=> n431);
U311 : AOI22_X1 port map( A1 => n782, A2 => n451, B1 => n740, B2 => n450, ZN
=> n430);
U312 : AOI22_X1 port map( A1 => n668, A2 => n453, B1 => n702, B2 => n452, ZN
=> n429);
U313 : AOI22_X1 port map( A1 => n683, A2 => n455, B1 => n721, B2 => n454, ZN
=> n428);
U314 : NAND4_X1 port map( A1 => n431, A2 => n430, A3 => n429, A4 => n428, ZN
=> N35);
U315 : AOI22_X1 port map( A1 => n800, A2 => n449, B1 => n762, B2 => n448, ZN
=> n435);
U316 : AOI22_X1 port map( A1 => n781, A2 => n451, B1 => n739, B2 => n450, ZN
=> n434);
U317 : AOI22_X1 port map( A1 => n667, A2 => n453, B1 => n701, B2 => n452, ZN
=> n433);
U318 : AOI22_X1 port map( A1 => n682, A2 => n455, B1 => n720, B2 => n454, ZN
=> n432);
U319 : NAND4_X1 port map( A1 => n435, A2 => n434, A3 => n433, A4 => n432, ZN
=> N34);
U320 : AOI22_X1 port map( A1 => n799, A2 => n449, B1 => n761, B2 => n448, ZN
=> n439);
U321 : AOI22_X1 port map( A1 => n780, A2 => n451, B1 => n738, B2 => n450, ZN
=> n438);
U322 : AOI22_X1 port map( A1 => n666, A2 => n453, B1 => n700, B2 => n452, ZN
=> n437);
U323 : AOI22_X1 port map( A1 => n681, A2 => n455, B1 => n719, B2 => n454, ZN
=> n436);
U324 : NAND4_X1 port map( A1 => n439, A2 => n438, A3 => n437, A4 => n436, ZN
=> N33);
U325 : AOI22_X1 port map( A1 => n798, A2 => n449, B1 => n760, B2 => n448, ZN
=> n443);
U326 : AOI22_X1 port map( A1 => n779, A2 => n451, B1 => n737, B2 => n450, ZN
=> n442);
U327 : AOI22_X1 port map( A1 => n665, A2 => n453, B1 => n699, B2 => n452, ZN
=> n441);
U328 : AOI22_X1 port map( A1 => n680, A2 => n455, B1 => n718, B2 => n454, ZN
=> n440);
U329 : NAND4_X1 port map( A1 => n443, A2 => n442, A3 => n441, A4 => n440, ZN
=> N32);
U330 : AOI22_X1 port map( A1 => n797, A2 => n449, B1 => n759, B2 => n448, ZN
=> n447);
U331 : AOI22_X1 port map( A1 => n778, A2 => n451, B1 => n736, B2 => n450, ZN
=> n446);
U332 : AOI22_X1 port map( A1 => n664, A2 => n453, B1 => n698, B2 => n452, ZN
=> n445);
U333 : AOI22_X1 port map( A1 => n679, A2 => n455, B1 => n717, B2 => n454, ZN
=> n444);
U334 : NAND4_X1 port map( A1 => n447, A2 => n446, A3 => n445, A4 => n444, ZN
=> N31);
U335 : AOI22_X1 port map( A1 => n796, A2 => n449, B1 => n758, B2 => n448, ZN
=> n459);
U336 : AOI22_X1 port map( A1 => n777, A2 => n451, B1 => n735, B2 => n450, ZN
=> n458);
U337 : AOI22_X1 port map( A1 => n663, A2 => n453, B1 => n697, B2 => n452, ZN
=> n457);
U338 : AOI22_X1 port map( A1 => n678, A2 => n455, B1 => n716, B2 => n454, ZN
=> n456);
U339 : NAND4_X1 port map( A1 => n459, A2 => n458, A3 => n457, A4 => n456, ZN
=> N30);
U340 : INV_X1 port map( A => datain(18), ZN => n473);
clock_r_REG12_S2 : DFF_X1 port map( D => n1194, CK => clock, Q => dataout(0)
, QN => n1365);
clock_r_REG19_S2 : DFF_X1 port map( D => n1193, CK => clock, Q => dataout(1)
, QN => n1364);
clock_r_REG18_S2 : DFF_X1 port map( D => n1192, CK => clock, Q => dataout(2)
, QN => n1363);
clock_r_REG17_S2 : DFF_X1 port map( D => n1191, CK => clock, Q => dataout(3)
, QN => n1362);
clock_r_REG16_S2 : DFF_X1 port map( D => n1190, CK => clock, Q => dataout(4)
, QN => n1361);
clock_r_REG15_S2 : DFF_X1 port map( D => n1189, CK => clock, Q => dataout(5)
, QN => n1360);
clock_r_REG14_S2 : DFF_X1 port map( D => n1188, CK => clock, Q => dataout(6)
, QN => n1359);
clock_r_REG13_S2 : DFF_X1 port map( D => n1187, CK => clock, Q => dataout(7)
, QN => n1358);
clock_r_REG11_S2 : DFF_X1 port map( D => n1186, CK => clock, Q => dataout(8)
, QN => n1357);
clock_r_REG10_S2 : DFF_X1 port map( D => n1185, CK => clock, Q => dataout(9)
, QN => n1356);
clock_r_REG9_S2 : DFF_X1 port map( D => n1184, CK => clock, Q => dataout(10)
, QN => n1355);
clock_r_REG8_S2 : DFF_X1 port map( D => n1183, CK => clock, Q => dataout(11)
, QN => n1354);
clock_r_REG7_S2 : DFF_X1 port map( D => n1182, CK => clock, Q => dataout(12)
, QN => n1353);
clock_r_REG6_S2 : DFF_X1 port map( D => n1181, CK => clock, Q => dataout(13)
, QN => n1352);
clock_r_REG5_S2 : DFF_X1 port map( D => n1180, CK => clock, Q => dataout(14)
, QN => n1351);
clock_r_REG4_S2 : DFF_X1 port map( D => n1179, CK => clock, Q => dataout(15)
, QN => n1350);
clock_r_REG3_S2 : DFF_X1 port map( D => n1178, CK => clock, Q => dataout(16)
, QN => n1349);
clock_r_REG2_S2 : DFF_X1 port map( D => n1177, CK => clock, Q => dataout(17)
, QN => n1348);
clock_r_REG1_S2 : DFF_X1 port map( D => n1176, CK => clock, Q => dataout(18)
, QN => n1347);
clock_r_REG200_S4 : DFF_X1 port map( D => ram_5_0_port, CK => clock, Q =>
n814, QN => n1270);
clock_r_REG191_S4 : DFF_X1 port map( D => ram_5_1_port, CK => clock, Q =>
n813, QN => n1269);
clock_r_REG183_S4 : DFF_X1 port map( D => ram_5_2_port, CK => clock, Q =>
n812, QN => n1268);
clock_r_REG174_S4 : DFF_X1 port map( D => ram_5_3_port, CK => clock, Q =>
n811, QN => n1267);
clock_r_REG165_S4 : DFF_X1 port map( D => ram_5_4_port, CK => clock, Q =>
n810, QN => n1266);
clock_r_REG157_S4 : DFF_X1 port map( D => ram_5_5_port, CK => clock, Q =>
n809, QN => n1265);
clock_r_REG147_S4 : DFF_X1 port map( D => ram_5_6_port, CK => clock, Q =>
n808, QN => n1264);
clock_r_REG138_S4 : DFF_X1 port map( D => ram_5_7_port, CK => clock, Q =>
n807, QN => n1263);
clock_r_REG129_S4 : DFF_X1 port map( D => ram_5_8_port, CK => clock, Q =>
n806, QN => n1262);
clock_r_REG120_S4 : DFF_X1 port map( D => ram_5_9_port, CK => clock, Q =>
n805, QN => n1261);
clock_r_REG110_S4 : DFF_X1 port map( D => ram_5_10_port, CK => clock, Q =>
n804, QN => n1260);
clock_r_REG100_S4 : DFF_X1 port map( D => ram_5_11_port, CK => clock, Q =>
n803, QN => n1259);
clock_r_REG91_S4 : DFF_X1 port map( D => ram_5_12_port, CK => clock, Q =>
n802, QN => n1258);
clock_r_REG81_S4 : DFF_X1 port map( D => ram_5_13_port, CK => clock, Q =>
n801, QN => n1257);
clock_r_REG73_S4 : DFF_X1 port map( D => ram_5_14_port, CK => clock, Q =>
n800, QN => n1256);
clock_r_REG64_S4 : DFF_X1 port map( D => ram_5_15_port, CK => clock, Q =>
n799, QN => n1255);
clock_r_REG55_S4 : DFF_X1 port map( D => ram_5_16_port, CK => clock, Q =>
n798, QN => n1254);
clock_r_REG46_S4 : DFF_X1 port map( D => ram_5_17_port, CK => clock, Q =>
n797, QN => n1253);
clock_r_REG38_S4 : DFF_X1 port map( D => ram_5_18_port, CK => clock, Q =>
n796, QN => n1252);
clock_r_REG199_S4 : DFF_X1 port map( D => ram_1_0_port, CK => clock, Q =>
n795, QN => n1251);
clock_r_REG190_S4 : DFF_X1 port map( D => ram_1_1_port, CK => clock, Q =>
n794, QN => n1250);
clock_r_REG182_S4 : DFF_X1 port map( D => ram_1_2_port, CK => clock, Q =>
n793, QN => n1249);
clock_r_REG173_S4 : DFF_X1 port map( D => ram_1_3_port, CK => clock, Q =>
n792, QN => n1248);
clock_r_REG164_S4 : DFF_X1 port map( D => ram_1_4_port, CK => clock, Q =>
n791, QN => n1247);
clock_r_REG156_S4 : DFF_X1 port map( D => ram_1_5_port, CK => clock, Q =>
n790, QN => n1246);
clock_r_REG146_S4 : DFF_X1 port map( D => ram_1_6_port, CK => clock, Q =>
n789, QN => n1245);
clock_r_REG137_S4 : DFF_X1 port map( D => ram_1_7_port, CK => clock, Q =>
n788, QN => n1244);
clock_r_REG128_S4 : DFF_X1 port map( D => ram_1_8_port, CK => clock, Q =>
n787, QN => n1243);
clock_r_REG119_S4 : DFF_X1 port map( D => ram_1_9_port, CK => clock, Q =>
n786, QN => n1242);
clock_r_REG109_S4 : DFF_X1 port map( D => ram_1_10_port, CK => clock, Q =>
n785, QN => n1241);
clock_r_REG99_S4 : DFF_X1 port map( D => ram_1_11_port, CK => clock, Q =>
n784, QN => n1240);
clock_r_REG90_S4 : DFF_X1 port map( D => ram_1_12_port, CK => clock, Q =>
n783, QN => n1239);
clock_r_REG80_S4 : DFF_X1 port map( D => ram_1_13_port, CK => clock, Q =>
n782, QN => n1238);
clock_r_REG72_S4 : DFF_X1 port map( D => ram_1_14_port, CK => clock, Q =>
n781, QN => n1237);
clock_r_REG63_S4 : DFF_X1 port map( D => ram_1_15_port, CK => clock, Q =>
n780, QN => n1236);
clock_r_REG54_S4 : DFF_X1 port map( D => ram_1_16_port, CK => clock, Q =>
n779, QN => n1235);
clock_r_REG45_S4 : DFF_X1 port map( D => ram_1_17_port, CK => clock, Q =>
n778, QN => n1234);
clock_r_REG37_S4 : DFF_X1 port map( D => ram_1_18_port, CK => clock, Q =>
n777, QN => n1233);
clock_r_REG198_S4 : DFF_X1 port map( D => ram_7_0_port, CK => clock, Q =>
n776, QN => n1346);
clock_r_REG189_S4 : DFF_X1 port map( D => ram_7_1_port, CK => clock, Q =>
n775, QN => n1345);
clock_r_REG181_S4 : DFF_X1 port map( D => ram_7_2_port, CK => clock, Q =>
n774, QN => n1344);
clock_r_REG172_S4 : DFF_X1 port map( D => ram_7_3_port, CK => clock, Q =>
n773, QN => n1343);
clock_r_REG163_S4 : DFF_X1 port map( D => ram_7_4_port, CK => clock, Q =>
n772, QN => n1342);
clock_r_REG155_S4 : DFF_X1 port map( D => ram_7_5_port, CK => clock, Q =>
n771, QN => n1341);
clock_r_REG145_S4 : DFF_X1 port map( D => ram_7_6_port, CK => clock, Q =>
n770, QN => n1340);
clock_r_REG136_S4 : DFF_X1 port map( D => ram_7_7_port, CK => clock, Q =>
n769, QN => n1339);
clock_r_REG127_S4 : DFF_X1 port map( D => ram_7_8_port, CK => clock, Q =>
n768, QN => n1338);
clock_r_REG118_S4 : DFF_X1 port map( D => ram_7_9_port, CK => clock, Q =>
n767, QN => n1337);
clock_r_REG108_S4 : DFF_X1 port map( D => ram_7_10_port, CK => clock, Q =>
n766, QN => n1336);
clock_r_REG98_S4 : DFF_X1 port map( D => ram_7_11_port, CK => clock, Q =>
n765, QN => n1335);
clock_r_REG89_S4 : DFF_X1 port map( D => ram_7_12_port, CK => clock, Q =>
n764, QN => n1334);
clock_r_REG79_S4 : DFF_X1 port map( D => ram_7_13_port, CK => clock, Q =>
n763, QN => n1333);
clock_r_REG71_S4 : DFF_X1 port map( D => ram_7_14_port, CK => clock, Q =>
n762, QN => n1332);
clock_r_REG62_S4 : DFF_X1 port map( D => ram_7_15_port, CK => clock, Q =>
n761, QN => n1331);
clock_r_REG53_S4 : DFF_X1 port map( D => ram_7_16_port, CK => clock, Q =>
n760, QN => n1330);
clock_r_REG44_S4 : DFF_X1 port map( D => ram_7_17_port, CK => clock, Q =>
n759, QN => n1329);
clock_r_REG36_S4 : DFF_X1 port map( D => ram_7_18_port, CK => clock, Q =>
n758, QN => n1328);
clock_r_REG197_S4 : DFF_X1 port map( D => ram_4_0_port, CK => clock, Q =>
n757, QN => n1232);
clock_r_REG188_S4 : DFF_X1 port map( D => ram_4_1_port, CK => clock, Q =>
n756, QN => n1231);
clock_r_REG180_S4 : DFF_X1 port map( D => ram_4_2_port, CK => clock, Q =>
n755, QN => n1230);
clock_r_REG171_S4 : DFF_X1 port map( D => ram_4_3_port, CK => clock, Q =>
n754, QN => n1229);
clock_r_REG196_S4 : DFF_X1 port map( D => ram_3_0_port, CK => clock, Q =>
n753, QN => n1327);
clock_r_REG187_S4 : DFF_X1 port map( D => ram_3_1_port, CK => clock, Q =>
n752, QN => n1326);
clock_r_REG179_S4 : DFF_X1 port map( D => ram_3_2_port, CK => clock, Q =>
n751, QN => n1325);
clock_r_REG170_S4 : DFF_X1 port map( D => ram_3_3_port, CK => clock, Q =>
n750, QN => n1324);
clock_r_REG162_S4 : DFF_X1 port map( D => ram_3_4_port, CK => clock, Q =>
n749, QN => n1323);
clock_r_REG154_S4 : DFF_X1 port map( D => ram_3_5_port, CK => clock, Q =>
n748, QN => n1322);
clock_r_REG144_S4 : DFF_X1 port map( D => ram_3_6_port, CK => clock, Q =>
n747, QN => n1321);
clock_r_REG135_S4 : DFF_X1 port map( D => ram_3_7_port, CK => clock, Q =>
n746, QN => n1320);
clock_r_REG126_S4 : DFF_X1 port map( D => ram_3_8_port, CK => clock, Q =>
n745, QN => n1319);
clock_r_REG117_S4 : DFF_X1 port map( D => ram_3_9_port, CK => clock, Q =>
n744, QN => n1318);
clock_r_REG107_S4 : DFF_X1 port map( D => ram_3_10_port, CK => clock, Q =>
n743, QN => n1317);
clock_r_REG97_S4 : DFF_X1 port map( D => ram_3_11_port, CK => clock, Q =>
n742, QN => n1316);
clock_r_REG88_S4 : DFF_X1 port map( D => ram_3_12_port, CK => clock, Q =>
n741, QN => n1315);
clock_r_REG78_S4 : DFF_X1 port map( D => ram_3_13_port, CK => clock, Q =>
n740, QN => n1314);
clock_r_REG70_S4 : DFF_X1 port map( D => ram_3_14_port, CK => clock, Q =>
n739, QN => n1313);
clock_r_REG61_S4 : DFF_X1 port map( D => ram_3_15_port, CK => clock, Q =>
n738, QN => n1312);
clock_r_REG52_S4 : DFF_X1 port map( D => ram_3_16_port, CK => clock, Q =>
n737, QN => n1311);
clock_r_REG43_S4 : DFF_X1 port map( D => ram_3_17_port, CK => clock, Q =>
n736, QN => n1310);
clock_r_REG35_S4 : DFF_X1 port map( D => ram_3_18_port, CK => clock, Q =>
n735, QN => n1309);
clock_r_REG195_S4 : DFF_X1 port map( D => ram_2_0_port, CK => clock, Q =>
n734, QN => n1308);
clock_r_REG186_S4 : DFF_X1 port map( D => ram_2_1_port, CK => clock, Q =>
n733, QN => n1307);
clock_r_REG178_S4 : DFF_X1 port map( D => ram_2_2_port, CK => clock, Q =>
n732, QN => n1306);
clock_r_REG169_S4 : DFF_X1 port map( D => ram_2_3_port, CK => clock, Q =>
n731, QN => n1305);
clock_r_REG161_S4 : DFF_X1 port map( D => ram_2_4_port, CK => clock, Q =>
n730, QN => n1304);
clock_r_REG153_S4 : DFF_X1 port map( D => ram_2_5_port, CK => clock, Q =>
n729, QN => n1303);
clock_r_REG143_S4 : DFF_X1 port map( D => ram_2_6_port, CK => clock, Q =>
n728, QN => n1302);
clock_r_REG134_S4 : DFF_X1 port map( D => ram_2_7_port, CK => clock, Q =>
n727, QN => n1301);
clock_r_REG125_S4 : DFF_X1 port map( D => ram_2_8_port, CK => clock, Q =>
n726, QN => n1300);
clock_r_REG116_S4 : DFF_X1 port map( D => ram_2_9_port, CK => clock, Q =>
n725, QN => n1299);
clock_r_REG106_S4 : DFF_X1 port map( D => ram_2_10_port, CK => clock, Q =>
n724, QN => n1298);
clock_r_REG96_S4 : DFF_X1 port map( D => ram_2_11_port, CK => clock, Q =>
n723, QN => n1297);
clock_r_REG87_S4 : DFF_X1 port map( D => ram_2_12_port, CK => clock, Q =>
n722, QN => n1296);
clock_r_REG77_S4 : DFF_X1 port map( D => ram_2_13_port, CK => clock, Q =>
n721, QN => n1295);
clock_r_REG69_S4 : DFF_X1 port map( D => ram_2_14_port, CK => clock, Q =>
n720, QN => n1294);
clock_r_REG60_S4 : DFF_X1 port map( D => ram_2_15_port, CK => clock, Q =>
n719, QN => n1293);
clock_r_REG51_S4 : DFF_X1 port map( D => ram_2_16_port, CK => clock, Q =>
n718, QN => n1292);
clock_r_REG42_S4 : DFF_X1 port map( D => ram_2_17_port, CK => clock, Q =>
n717, QN => n1291);
clock_r_REG34_S4 : DFF_X1 port map( D => ram_2_18_port, CK => clock, Q =>
n716, QN => n1290);
clock_r_REG194_S4 : DFF_X1 port map( D => ram_6_0_port, CK => clock, Q =>
n715, QN => n1289);
clock_r_REG185_S4 : DFF_X1 port map( D => ram_6_1_port, CK => clock, Q =>
n714, QN => n1288);
clock_r_REG177_S4 : DFF_X1 port map( D => ram_6_2_port, CK => clock, Q =>
n713, QN => n1287);
clock_r_REG168_S4 : DFF_X1 port map( D => ram_6_3_port, CK => clock, Q =>
n712, QN => n1286);
clock_r_REG160_S4 : DFF_X1 port map( D => ram_6_4_port, CK => clock, Q =>
n711, QN => n1285);
clock_r_REG152_S4 : DFF_X1 port map( D => ram_6_5_port, CK => clock, Q =>
n710, QN => n1284);
clock_r_REG142_S4 : DFF_X1 port map( D => ram_6_6_port, CK => clock, Q =>
n709, QN => n1283);
clock_r_REG133_S4 : DFF_X1 port map( D => ram_6_7_port, CK => clock, Q =>
n708, QN => n1282);
clock_r_REG124_S4 : DFF_X1 port map( D => ram_6_8_port, CK => clock, Q =>
n707, QN => n1281);
clock_r_REG115_S4 : DFF_X1 port map( D => ram_6_9_port, CK => clock, Q =>
n706, QN => n1280);
clock_r_REG105_S4 : DFF_X1 port map( D => ram_6_10_port, CK => clock, Q =>
n705, QN => n1279);
clock_r_REG95_S4 : DFF_X1 port map( D => ram_6_11_port, CK => clock, Q =>
n704, QN => n1278);
clock_r_REG86_S4 : DFF_X1 port map( D => ram_6_12_port, CK => clock, Q =>
n703, QN => n1277);
clock_r_REG76_S4 : DFF_X1 port map( D => ram_6_13_port, CK => clock, Q =>
n702, QN => n1276);
clock_r_REG68_S4 : DFF_X1 port map( D => ram_6_14_port, CK => clock, Q =>
n701, QN => n1275);
clock_r_REG59_S4 : DFF_X1 port map( D => ram_6_15_port, CK => clock, Q =>
n700, QN => n1274);
clock_r_REG50_S4 : DFF_X1 port map( D => ram_6_16_port, CK => clock, Q =>
n699, QN => n1273);
clock_r_REG41_S4 : DFF_X1 port map( D => ram_6_17_port, CK => clock, Q =>
n698, QN => n1272);
clock_r_REG33_S4 : DFF_X1 port map( D => ram_6_18_port, CK => clock, Q =>
n697, QN => n1271);
clock_r_REG193_S4 : DFF_X1 port map( D => ram_0_0_port, CK => clock, Q =>
n696, QN => n1228);
clock_r_REG184_S4 : DFF_X1 port map( D => ram_0_1_port, CK => clock, Q =>
n695, QN => n1227);
clock_r_REG176_S4 : DFF_X1 port map( D => ram_0_2_port, CK => clock, Q =>
n694, QN => n1226);
clock_r_REG167_S4 : DFF_X1 port map( D => ram_0_3_port, CK => clock, Q =>
n693, QN => n1225);
clock_r_REG159_S4 : DFF_X1 port map( D => ram_0_4_port, CK => clock, Q =>
n692, QN => n1224);
clock_r_REG151_S4 : DFF_X1 port map( D => ram_0_5_port, CK => clock, Q =>
n691, QN => n1223);
clock_r_REG141_S4 : DFF_X1 port map( D => ram_0_6_port, CK => clock, Q =>
n690, QN => n1222);
clock_r_REG132_S4 : DFF_X1 port map( D => ram_0_7_port, CK => clock, Q =>
n689, QN => n1221);
clock_r_REG123_S4 : DFF_X1 port map( D => ram_0_8_port, CK => clock, Q =>
n688, QN => n1220);
clock_r_REG114_S4 : DFF_X1 port map( D => ram_0_9_port, CK => clock, Q =>
n687, QN => n1219);
clock_r_REG104_S4 : DFF_X1 port map( D => ram_0_10_port, CK => clock, Q =>
n686, QN => n1218);
clock_r_REG94_S4 : DFF_X1 port map( D => ram_0_11_port, CK => clock, Q =>
n685, QN => n1217);
clock_r_REG85_S4 : DFF_X1 port map( D => ram_0_12_port, CK => clock, Q =>
n684, QN => n1216);
clock_r_REG75_S4 : DFF_X1 port map( D => ram_0_13_port, CK => clock, Q =>
n683, QN => n1215);
clock_r_REG67_S4 : DFF_X1 port map( D => ram_0_14_port, CK => clock, Q =>
n682, QN => n1214);
clock_r_REG58_S4 : DFF_X1 port map( D => ram_0_15_port, CK => clock, Q =>
n681, QN => n1213);
clock_r_REG49_S4 : DFF_X1 port map( D => ram_0_16_port, CK => clock, Q =>
n680, QN => n1212);
clock_r_REG40_S4 : DFF_X1 port map( D => ram_0_17_port, CK => clock, Q =>
n679, QN => n1211);
clock_r_REG32_S4 : DFF_X1 port map( D => ram_0_18_port, CK => clock, Q =>
n678, QN => n1210);
clock_r_REG158_S4 : DFF_X1 port map( D => ram_4_4_port, CK => clock, Q =>
n677, QN => n1209);
clock_r_REG150_S4 : DFF_X1 port map( D => ram_4_5_port, CK => clock, Q =>
n676, QN => n1208);
clock_r_REG140_S4 : DFF_X1 port map( D => ram_4_6_port, CK => clock, Q =>
n675, QN => n1207);
clock_r_REG131_S4 : DFF_X1 port map( D => ram_4_7_port, CK => clock, Q =>
n674, QN => n1206);
clock_r_REG122_S4 : DFF_X1 port map( D => ram_4_8_port, CK => clock, Q =>
n673, QN => n1205);
clock_r_REG113_S4 : DFF_X1 port map( D => ram_4_9_port, CK => clock, Q =>
n672, QN => n1204);
clock_r_REG103_S4 : DFF_X1 port map( D => ram_4_10_port, CK => clock, Q =>
n671, QN => n1203);
clock_r_REG93_S4 : DFF_X1 port map( D => ram_4_11_port, CK => clock, Q =>
n670, QN => n1202);
clock_r_REG84_S4 : DFF_X1 port map( D => ram_4_12_port, CK => clock, Q =>
n669, QN => n1201);
clock_r_REG74_S4 : DFF_X1 port map( D => ram_4_13_port, CK => clock, Q =>
n668, QN => n1200);
clock_r_REG66_S4 : DFF_X1 port map( D => ram_4_14_port, CK => clock, Q =>
n667, QN => n1199);
clock_r_REG57_S4 : DFF_X1 port map( D => ram_4_15_port, CK => clock, Q =>
n666, QN => n1198);
clock_r_REG48_S4 : DFF_X1 port map( D => ram_4_16_port, CK => clock, Q =>
n665, QN => n1197);
clock_r_REG39_S4 : DFF_X1 port map( D => ram_4_17_port, CK => clock, Q =>
n664, QN => n1196);
clock_r_REG31_S4 : DFF_X1 port map( D => ram_4_18_port, CK => clock, Q =>
n663, QN => n1195);
U13 : NAND3_X1 port map( A1 => n466, A2 => n471, A3 => n29, ZN => n35_port);
U23 : NAND3_X1 port map( A1 => n29, A2 => address(0), A3 => address(1), ZN
=> n28);
U24 : NAND3_X1 port map( A1 => n29, A2 => n466, A3 => address(1), ZN =>
n31_port);
U21 : NAND3_X1 port map( A1 => address(0), A2 => n471, A3 => n29, ZN =>
n33_port);
end SYN_ramR;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_project2.all;
entity counter_address_generator_1 is
port( clock, reset, need_to_reset, enable, read_enable : in std_logic;
address : out std_logic_vector (7 downto 0));
end counter_address_generator_1;
architecture SYN_counter_address_generator of counter_address_generator_1 is
component counter_address_generator_1_DW01_inc_0
port( A : in std_logic_vector (7 downto 0); SUM : out std_logic_vector
(7 downto 0));
end component;
component DFF_X1
port( D, CK : in std_logic; Q, QN : out std_logic);
end component;
component AOI22_X1
port( A1, A2, B1, B2 : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component NOR3_X2
port( A1, A2, A3 : in std_logic; ZN : out std_logic);
end component;
signal n61, n62, n63, n64, n65, n66, n67, n68, N10, N11, N12, N13, N14, N15,
N16, N17, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28,
address_0_port, address_1_port, address_2_port, address_3_port,
address_4_port, address_5_port, address_6_port, address_7_port, n_1038,
n_1039, n_1040, n_1041, n_1042, n_1043, n_1044, n_1045 : std_logic;
begin
address <= ( address_7_port, address_6_port, address_5_port, address_4_port,
address_3_port, address_2_port, address_1_port, address_0_port );
U3 : NOR3_X2 port map( A1 => reset, A2 => need_to_reset, A3 => n26, ZN =>
n27);
U4 : NOR3_X2 port map( A1 => reset, A2 => read_enable, A3 => enable, ZN =>
n26);
U5 : INV_X1 port map( A => n28, ZN => n61);
U6 : AOI22_X1 port map( A1 => N17, A2 => n27, B1 => address_7_port, B2 =>
n26, ZN => n28);
U7 : INV_X1 port map( A => n25, ZN => n62);
U8 : AOI22_X1 port map( A1 => N16, A2 => n27, B1 => address_6_port, B2 =>
n26, ZN => n25);
U9 : INV_X1 port map( A => n24, ZN => n63);
U10 : AOI22_X1 port map( A1 => N15, A2 => n27, B1 => address_5_port, B2 =>
n26, ZN => n24);
U11 : INV_X1 port map( A => n23, ZN => n64);
U12 : AOI22_X1 port map( A1 => N14, A2 => n27, B1 => address_4_port, B2 =>
n26, ZN => n23);
U13 : INV_X1 port map( A => n22, ZN => n65);
U14 : AOI22_X1 port map( A1 => N13, A2 => n27, B1 => address_3_port, B2 =>
n26, ZN => n22);
U15 : INV_X1 port map( A => n21, ZN => n66);
U16 : AOI22_X1 port map( A1 => N12, A2 => n27, B1 => address_2_port, B2 =>
n26, ZN => n21);
U17 : INV_X1 port map( A => n20, ZN => n67);
U18 : AOI22_X1 port map( A1 => N11, A2 => n27, B1 => address_1_port, B2 =>
n26, ZN => n20);
U19 : INV_X1 port map( A => n19, ZN => n68);
U20 : AOI22_X1 port map( A1 => N10, A2 => n27, B1 => address_0_port, B2 =>
n26, ZN => n19);
clock_r_REG306_S2 : DFF_X1 port map( D => n61, CK => clock, Q =>
address_7_port, QN => n_1038);
clock_r_REG305_S2 : DFF_X1 port map( D => n62, CK => clock, Q =>
address_6_port, QN => n_1039);
clock_r_REG304_S2 : DFF_X1 port map( D => n63, CK => clock, Q =>
address_5_port, QN => n_1040);
clock_r_REG303_S2 : DFF_X1 port map( D => n64, CK => clock, Q =>
address_4_port, QN => n_1041);
clock_r_REG302_S2 : DFF_X1 port map( D => n65, CK => clock, Q =>
address_3_port, QN => n_1042);
clock_r_REG301_S2 : DFF_X1 port map( D => n66, CK => clock, Q =>
address_2_port, QN => n_1043);
clock_r_REG300_S2 : DFF_X1 port map( D => n67, CK => clock, Q =>
address_1_port, QN => n_1044);
clock_r_REG20_S2 : DFF_X1 port map( D => n68, CK => clock, Q =>
address_0_port, QN => n_1045);
add_38 : counter_address_generator_1_DW01_inc_0 port map( A(7) =>
address_7_port, A(6) => address_6_port, A(5) =>
address_5_port, A(4) => address_4_port, A(3) =>
address_3_port, A(2) => address_2_port, A(1) =>
address_1_port, A(0) => address_0_port, SUM(7) =>
N17, SUM(6) => N16, SUM(5) => N15, SUM(4) => N14,
SUM(3) => N13, SUM(2) => N12, SUM(1) => N11, SUM(0)
=> N10);
end SYN_counter_address_generator;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_project2.all;
entity fsm is
port( clock, reset : in std_logic; ramA_address : in std_logic_vector (4
downto 0); ramR_address, rom_address : in std_logic_vector (7 downto
0); hold_me : in std_logic; ramR_readEnable, ramA_writeEnable,
ramA_readEnable, ramR_writeEnable, rom_enable,
counterAddressGen_H_enable, counterAddressGen_R_enable,
counterAddressGen_A_restart, counterAddressGen_R_restart,
counterAddressGen_H_restart, mac_clean, reset_fsm, hold_prev : out
std_logic);
end fsm;
architecture SYN_fsm of fsm is
component OR2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component DFF_X1
port( D, CK : in std_logic; Q, QN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component NAND3_X1
port( A1, A2, A3 : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component AOI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component NOR2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component NOR3_X1
port( A1, A2, A3 : in std_logic; ZN : out std_logic);
end component;
component NOR4_X1
port( A1, A2, A3, A4 : in std_logic; ZN : out std_logic);
end component;
component NAND4_X1
port( A1, A2, A3, A4 : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component OAI211_X1
port( C1, C2, A, B : in std_logic; ZN : out std_logic);
end component;
component AOI22_X1
port( A1, A2, B1, B2 : in std_logic; ZN : out std_logic);
end component;
component AND3_X1
port( A1, A2, A3 : in std_logic; ZN : out std_logic);
end component;
component OR3_X1
port( A1, A2, A3 : in std_logic; ZN : out std_logic);
end component;
signal ramA_readEnable_port, status_1_port, status_0_port, n20, n22, n26,
n27, n31, n32, n33, n34, n35, n37, counterAddressGen_A_restart_port, n2,
n4, n5, n6, n10, n11, n12, n13, n14, n15, n16, n17, n18, n19, n21, n24,
n25, n28, n30, n36, n38, n39, n40, n41, n43, n44, n48, n49, n50, n57, n58
, n59 : std_logic;
begin
ramA_readEnable <= ramA_readEnable_port;
ramR_writeEnable <= n5;
rom_enable <= ramA_readEnable_port;
counterAddressGen_A_restart <= counterAddressGen_A_restart_port;
counterAddressGen_R_restart <= counterAddressGen_A_restart_port;
counterAddressGen_H_restart <= counterAddressGen_A_restart_port;
reset_fsm <= counterAddressGen_A_restart_port;
U46 : NAND3_X1 port map( A1 => rom_address(1), A2 => n41, A3 => n33, ZN =>
n32);
U3 : NAND2_X1 port map( A1 => n4, A2 => n38, ZN =>
counterAddressGen_A_restart_port);
U5 : INV_X1 port map( A => n26, ZN => n40);
U7 : OR2_X1 port map( A1 => n58, A2 => n59, ZN => n4);
U8 : NAND2_X1 port map( A1 => n4, A2 => n38, ZN => n43);
U9 : OR2_X1 port map( A1 => n28, A2 => n58, ZN => n30);
U10 : NOR2_X1 port map( A1 => n28, A2 => n58, ZN => n5);
U11 : INV_X1 port map( A => n34, ZN => n41);
U12 : NOR3_X1 port map( A1 => rom_address(5), A2 => rom_address(4), A3 =>
rom_address(3), ZN => n34);
U13 : NOR3_X1 port map( A1 => ramA_address(1), A2 => ramA_address(0), A3 =>
n37, ZN => n27);
U14 : OR3_X1 port map( A1 => ramA_address(4), A2 => ramA_address(3), A3 =>
ramA_address(2), ZN => n37);
U15 : AOI21_X1 port map( B1 => n26, B2 => n32, A => rom_address(0), ZN =>
n31);
U16 : NOR3_X1 port map( A1 => rom_address(2), A2 => rom_address(7), A3 =>
rom_address(6), ZN => n33);
U17 : NAND4_X1 port map( A1 => rom_address(6), A2 => rom_address(1), A3 =>
n35, A4 => n34, ZN => n26);
U18 : NOR2_X1 port map( A1 => rom_address(7), A2 => rom_address(2), ZN =>
n35);
U19 : AND3_X1 port map( A1 => ramR_address(0), A2 => n44, A3 =>
ramR_address(1), ZN => n20);
U20 : INV_X1 port map( A => hold_me, ZN => n44);
U21 : AND2_X1 port map( A1 => n40, A2 => rom_address(0), ZN => n6);
U22 : OR2_X1 port map( A1 => ramR_address(5), A2 => ramR_address(4), ZN =>
n22);
U25 : AOI22_X1 port map( A1 => n27, A2 => n58, B1 => n31, B2 => n57, ZN =>
n11);
U26 : NAND3_X1 port map( A1 => hold_me, A2 => n49, A3 => n58, ZN => n10);
U27 : NAND3_X1 port map( A1 => n58, A2 => n57, A3 => n59, ZN => n38);
U28 : OAI211_X1 port map( C1 => n49, C2 => n11, A => n10, B => n38, ZN =>
n13);
U29 : INV_X1 port map( A => reset, ZN => n12);
U30 : AND2_X1 port map( A1 => n13, A2 => n12, ZN => status_0_port);
U31 : NAND2_X1 port map( A1 => n59, A2 => n50, ZN => n28);
U33 : NAND4_X1 port map( A1 => ramR_address(3), A2 => n20, A3 =>
ramR_address(2), A4 => n57, ZN => n14);
U34 : NOR4_X1 port map( A1 => n14, A2 => n22, A3 => ramR_address(7), A4 =>
ramR_address(6), ZN => n15);
U35 : NOR3_X1 port map( A1 => n15, A2 => n48, A3 => n59, ZN => n16);
U36 : AOI21_X1 port map( B1 => n6, B2 => n5, A => n16, ZN => n17);
U37 : NOR2_X1 port map( A1 => reset, A2 => n17, ZN => n2);
U38 : INV_X1 port map( A => n27, ZN => n18);
U39 : NAND3_X1 port map( A1 => n58, A2 => n18, A3 => n50, ZN => n19);
U40 : OAI21_X1 port map( B1 => n58, B2 => n6, A => n19, ZN => n21);
U41 : NAND2_X1 port map( A1 => n59, A2 => n21, ZN => n24);
U42 : NAND3_X1 port map( A1 => n48, A2 => n57, A3 => n59, ZN => n25);
U43 : AOI21_X1 port map( B1 => n24, B2 => n25, A => reset, ZN =>
status_1_port);
U44 : NAND2_X1 port map( A1 => n25, A2 => n30, ZN => ramA_readEnable_port);
U45 : INV_X1 port map( A => ramA_readEnable_port, ZN => n36);
U47 : NAND2_X1 port map( A1 => n28, A2 => n36, ZN => hold_prev);
U48 : NAND3_X1 port map( A1 => n57, A2 => n49, A3 => n58, ZN => n39);
U49 : NAND3_X1 port map( A1 => n30, A2 => n38, A3 => n39, ZN =>
counterAddressGen_R_enable);
U50 : NAND2_X1 port map( A1 => n38, A2 => n36, ZN =>
counterAddressGen_H_enable);
U51 : NAND3_X1 port map( A1 => n48, A2 => n38, A3 => n59, ZN =>
ramA_writeEnable);
U52 : INV_X1 port map( A => n39, ZN => ramR_readEnable);
clock_r_REG23_S2 : DFF_X1 port map( D => status_0_port, CK => clock, Q =>
n50, QN => n57);
clock_r_REG21_S1 : DFF_X1 port map( D => n2, CK => clock, Q => n49, QN =>
n59);
clock_r_REG0_S1 : DFF_X1 port map( D => status_1_port, CK => clock, Q => n48
, QN => n58);
U4 : OR2_X1 port map( A1 => n43, A2 => n5, ZN => mac_clean);
end SYN_fsm;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_project2.all;
entity mac is
port( clock : in std_logic; ai, xi : in std_logic_vector (7 downto 0);
mac_clean : in std_logic; data_out : out std_logic_vector (18 downto
0));
end mac;
architecture SYN_multiplier_accumulator_implentation of mac is
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component DFF_X1
port( D, CK : in std_logic; Q, QN : out std_logic);
end component;
component mac_DW_mult_tc_1
port( a, b : in std_logic_vector (7 downto 0); product : out
std_logic_vector (15 downto 0); clock : in std_logic);
end component;
component mac_DW01_add_1
port( A, B : in std_logic_vector (18 downto 0); CI : in std_logic; SUM
: out std_logic_vector (18 downto 0); CO : out std_logic; clock :
in std_logic);
end component;
component NOR2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
signal n164, n165, n166, n167, n168, n169, n170, data_out_18_port,
data_out_17_port, data_out_16_port, data_out_15_port, data_out_14_port,
data_out_13_port, data_out_12_port, data_out_11_port, data_out_10_port,
data_out_9_port, data_out_8_port, n147, n148, n149, n150, n151, n152,
n153, n154, mult_out_14_port, mult_out_13_port, mult_out_12_port,
mult_out_11_port, mult_out_10_port, mult_out_9_port, mult_out_8_port,
mult_out_7_port, mult_out_6_port, mult_out_5_port, mult_out_4_port,
mult_out_3_port, mult_out_2_port, mult_out_1_port, mult_out_0_port,
mult_out_reg_15_port, N20, N21, N22, N23, N24, N25, N26, N27, N28, N29,
N30, N31, N32, N33, N34, N35, N36, N37, N38, n2, n3, n4, n5, n6, n7, n8,
n9, n10, n11, n12, n13, data_out_0_port, data_out_1_port, data_out_2_port
, data_out_3_port, data_out_4_port, data_out_5_port, data_out_6_port,
data_out_7_port, n38_port, n156, n157, n158, n159, n160, n161, n162, n163
, n_1053, n_1054, n_1055 : std_logic;
begin
data_out <= ( data_out_18_port, data_out_17_port, data_out_16_port,
data_out_15_port, data_out_14_port, data_out_13_port, data_out_12_port,
data_out_11_port, data_out_10_port, data_out_9_port, data_out_8_port,
data_out_7_port, data_out_6_port, data_out_5_port, data_out_4_port,
data_out_3_port, data_out_2_port, data_out_1_port, data_out_0_port );
n2 <= '0';
U3 : NOR2_X1 port map( A1 => mac_clean, A2 => n3, ZN => N38);
U5 : NOR2_X1 port map( A1 => mac_clean, A2 => n4, ZN => N37);
U6 : NOR2_X1 port map( A1 => mac_clean, A2 => n5, ZN => N36);
U7 : NOR2_X1 port map( A1 => mac_clean, A2 => n6, ZN => N35);
U8 : NOR2_X1 port map( A1 => mac_clean, A2 => n7, ZN => N34);
U9 : NOR2_X1 port map( A1 => mac_clean, A2 => n8, ZN => N33);
U10 : NOR2_X1 port map( A1 => mac_clean, A2 => n9, ZN => N32);
U11 : NOR2_X1 port map( A1 => mac_clean, A2 => n10, ZN => N31);
U12 : NOR2_X1 port map( A1 => mac_clean, A2 => n11, ZN => N30);
U13 : NOR2_X1 port map( A1 => mac_clean, A2 => n12, ZN => N29);
U14 : NOR2_X1 port map( A1 => mac_clean, A2 => n13, ZN => N28);
U15 : NOR2_X1 port map( A1 => mac_clean, A2 => n163, ZN => N27);
U16 : NOR2_X1 port map( A1 => mac_clean, A2 => n162, ZN => N26);
U17 : NOR2_X1 port map( A1 => mac_clean, A2 => n161, ZN => N25);
U18 : NOR2_X1 port map( A1 => mac_clean, A2 => n160, ZN => N24);
U19 : NOR2_X1 port map( A1 => mac_clean, A2 => n159, ZN => N23);
U20 : NOR2_X1 port map( A1 => mac_clean, A2 => n158, ZN => N22);
U21 : NOR2_X1 port map( A1 => mac_clean, A2 => n157, ZN => N21);
U22 : NOR2_X1 port map( A1 => mac_clean, A2 => n156, ZN => N20);
clock_r_REG130_S3 : DFF_X1 port map( D => n147, CK => clock, Q =>
data_out_7_port, QN => n163);
clock_r_REG139_S3 : DFF_X1 port map( D => n148, CK => clock, Q =>
data_out_6_port, QN => n162);
clock_r_REG149_S3 : DFF_X1 port map( D => n149, CK => clock, Q =>
data_out_5_port, QN => n161);
clock_r_REG148_S3 : DFF_X1 port map( D => n150, CK => clock, Q =>
data_out_4_port, QN => n160);
clock_r_REG166_S3 : DFF_X1 port map( D => n151, CK => clock, Q =>
data_out_3_port, QN => n159);
clock_r_REG175_S3 : DFF_X1 port map( D => n152, CK => clock, Q =>
data_out_2_port, QN => n158);
clock_r_REG24_S3 : DFF_X1 port map( D => n153, CK => clock, Q =>
data_out_1_port, QN => n157);
clock_r_REG192_S3 : DFF_X1 port map( D => n154, CK => clock, Q =>
data_out_0_port, QN => n156);
U31 : INV_X1 port map( A => data_out_8_port, ZN => n13);
U32 : INV_X1 port map( A => data_out_9_port, ZN => n12);
U33 : INV_X1 port map( A => data_out_10_port, ZN => n11);
U34 : INV_X1 port map( A => data_out_11_port, ZN => n10);
U35 : INV_X1 port map( A => data_out_12_port, ZN => n9);
U36 : INV_X1 port map( A => data_out_13_port, ZN => n8);
U37 : INV_X1 port map( A => data_out_14_port, ZN => n7);
U38 : INV_X1 port map( A => data_out_15_port, ZN => n6);
U39 : INV_X1 port map( A => data_out_16_port, ZN => n5);
U41 : INV_X1 port map( A => data_out_18_port, ZN => n3);
add_37_aco : mac_DW01_add_1 port map( A(18) => N38, A(17) => N37, A(16) =>
N36, A(15) => N35, A(14) => N34, A(13) => N33, A(12)
=> N32, A(11) => N31, A(10) => N30, A(9) => N29,
A(8) => N28, A(7) => N27, A(6) => N26, A(5) => N25,
A(4) => N24, A(3) => N23, A(2) => N22, A(1) => N21,
A(0) => N20, B(18) => n38_port, B(17) => n38_port,
B(16) => n38_port, B(15) => n38_port, B(14) =>
mult_out_14_port, B(13) => mult_out_13_port, B(12)
=> mult_out_12_port, B(11) => mult_out_11_port,
B(10) => mult_out_10_port, B(9) => mult_out_9_port,
B(8) => mult_out_8_port, B(7) => mult_out_7_port,
B(6) => mult_out_6_port, B(5) => mult_out_5_port,
B(4) => mult_out_4_port, B(3) => mult_out_3_port,
B(2) => mult_out_2_port, B(1) => mult_out_1_port,
B(0) => mult_out_0_port, CI => n2, SUM(18) =>
data_out_18_port, SUM(17) => data_out_17_port,
SUM(16) => data_out_16_port, SUM(15) =>
data_out_15_port, SUM(14) => data_out_14_port,
SUM(13) => data_out_13_port, SUM(12) =>
data_out_12_port, SUM(11) => data_out_11_port,
SUM(10) => data_out_10_port, SUM(9) =>
data_out_9_port, SUM(8) => data_out_8_port, SUM(7)
=> n147, SUM(6) => n148, SUM(5) => n149, SUM(4) =>
n150, SUM(3) => n151, SUM(2) => n152, SUM(1) => n153
, SUM(0) => n154, CO => n_1053, clock => clock);
mult_32 : mac_DW_mult_tc_1 port map( a(7) => ai(7), a(6) => ai(6), a(5) =>
ai(5), a(4) => ai(4), a(3) => ai(3), a(2) => ai(2),
a(1) => ai(1), a(0) => ai(0), b(7) => xi(7), b(6) =>
n164, b(5) => n165, b(4) => n166, b(3) => n167, b(2)
=> n168, b(1) => n169, b(0) => n170, product(15) =>
mult_out_reg_15_port, product(14) =>
mult_out_14_port, product(13) => mult_out_13_port,
product(12) => mult_out_12_port, product(11) =>
mult_out_11_port, product(10) => mult_out_10_port,
product(9) => mult_out_9_port, product(8) =>
mult_out_8_port, product(7) => mult_out_7_port,
product(6) => mult_out_6_port, product(5) =>
mult_out_5_port, product(4) => mult_out_4_port,
product(3) => mult_out_3_port, product(2) =>
mult_out_2_port, product(1) => mult_out_1_port,
product(0) => n_1054, clock => clock);
clock_r_REG206_S6 : DFF_X1 port map( D => mult_out_reg_15_port, CK => clock,
Q => n38_port, QN => n_1055);
U23 : INV_X1 port map( A => data_out_17_port, ZN => n4);
mult_out_0_port <= '0';
n170 <= '0';
n169 <= '0';
n168 <= '0';
n167 <= '0';
n166 <= '0';
n165 <= '0';
n164 <= '0';
end SYN_multiplier_accumulator_implentation;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_project2.all;
entity rom is
port( clock : in std_logic; address : in std_logic_vector (5 downto 0);
rom_enable : in std_logic; data : out std_logic_vector (7 downto 0));
end rom;
architecture SYN_rom of rom is
signal n_1063, n_1064, n_1065, n_1066, n_1067, n_1068, n_1069 : std_logic;
begin
data <= ( rom_enable, n_1063, n_1064, n_1065, n_1066, n_1067, n_1068, n_1069
);
end SYN_rom;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_project2.all;
entity counter_address_generator_2 is
port( clock, reset, need_to_reset, enable, read_enable : in std_logic;
address : out std_logic_vector (7 downto 0));
end counter_address_generator_2;
architecture SYN_counter_address_generator of counter_address_generator_2 is
component counter_address_generator_2_DW01_inc_0
port( A : in std_logic_vector (7 downto 0); SUM : out std_logic_vector
(7 downto 0));
end component;
component DFF_X1
port( D, CK : in std_logic; Q, QN : out std_logic);
end component;
component AOI22_X1
port( A1, A2, B1, B2 : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component NOR3_X2
port( A1, A2, A3 : in std_logic; ZN : out std_logic);
end component;
signal n61, n62, n63, n64, n65, n66, n67, n68, N10, N11, N12, N13, N14, N15,
N16, N17, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28,
address_0_port, address_1_port, address_2_port, address_3_port,
address_4_port, address_5_port, address_6_port, address_7_port, n_1070,
n_1071, n_1072, n_1073, n_1074, n_1075, n_1076, n_1077 : std_logic;
begin
address <= ( address_7_port, address_6_port, address_5_port, address_4_port,
address_3_port, address_2_port, address_1_port, address_0_port );
U3 : NOR3_X2 port map( A1 => reset, A2 => need_to_reset, A3 => n26, ZN =>
n27);
U4 : NOR3_X2 port map( A1 => reset, A2 => read_enable, A3 => enable, ZN =>
n26);
U5 : INV_X1 port map( A => n28, ZN => n61);
U6 : AOI22_X1 port map( A1 => N17, A2 => n27, B1 => address_7_port, B2 =>
n26, ZN => n28);
U7 : INV_X1 port map( A => n25, ZN => n62);
U8 : AOI22_X1 port map( A1 => N16, A2 => n27, B1 => address_6_port, B2 =>
n26, ZN => n25);
U9 : INV_X1 port map( A => n24, ZN => n63);
U10 : AOI22_X1 port map( A1 => N15, A2 => n27, B1 => address_5_port, B2 =>
n26, ZN => n24);
U11 : INV_X1 port map( A => n23, ZN => n64);
U12 : AOI22_X1 port map( A1 => N14, A2 => n27, B1 => address_4_port, B2 =>
n26, ZN => n23);
U13 : INV_X1 port map( A => n22, ZN => n65);
U14 : AOI22_X1 port map( A1 => N13, A2 => n27, B1 => address_3_port, B2 =>
n26, ZN => n22);
U15 : INV_X1 port map( A => n21, ZN => n66);
U16 : AOI22_X1 port map( A1 => N12, A2 => n27, B1 => address_2_port, B2 =>
n26, ZN => n21);
U17 : INV_X1 port map( A => n20, ZN => n67);
U18 : AOI22_X1 port map( A1 => N11, A2 => n27, B1 => address_1_port, B2 =>
n26, ZN => n20);
U19 : INV_X1 port map( A => n19, ZN => n68);
U20 : AOI22_X1 port map( A1 => N10, A2 => n27, B1 => address_0_port, B2 =>
n26, ZN => n19);
clock_r_REG313_S2 : DFF_X1 port map( D => n61, CK => clock, Q =>
address_7_port, QN => n_1070);
clock_r_REG312_S2 : DFF_X1 port map( D => n62, CK => clock, Q =>
address_6_port, QN => n_1071);
clock_r_REG311_S2 : DFF_X1 port map( D => n63, CK => clock, Q =>
address_5_port, QN => n_1072);
clock_r_REG310_S2 : DFF_X1 port map( D => n64, CK => clock, Q =>
address_4_port, QN => n_1073);
clock_r_REG309_S2 : DFF_X1 port map( D => n65, CK => clock, Q =>
address_3_port, QN => n_1074);
clock_r_REG308_S2 : DFF_X1 port map( D => n66, CK => clock, Q =>
address_2_port, QN => n_1075);
clock_r_REG307_S2 : DFF_X1 port map( D => n67, CK => clock, Q =>
address_1_port, QN => n_1076);
clock_r_REG22_S2 : DFF_X1 port map( D => n68, CK => clock, Q =>
address_0_port, QN => n_1077);
add_38 : counter_address_generator_2_DW01_inc_0 port map( A(7) =>
address_7_port, A(6) => address_6_port, A(5) =>
address_5_port, A(4) => address_4_port, A(3) =>
address_3_port, A(2) => address_2_port, A(1) =>
address_1_port, A(0) => address_0_port, SUM(7) =>
N17, SUM(6) => N16, SUM(5) => N15, SUM(4) => N14,
SUM(3) => N13, SUM(2) => N12, SUM(1) => N11, SUM(0)
=> N10);
end SYN_counter_address_generator;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_project2.all;
entity ramA is
port( clock, write_enable, read_enable : in std_logic; address : in
std_logic_vector (2 downto 0); datain : in std_logic_vector (7 downto
0); dataout : out std_logic_vector (7 downto 0));
end ramA;
architecture SYN_ramA of ramA is
component DFF_X1
port( D, CK : in std_logic; Q, QN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component AOI22_X1
port( A1, A2, B1, B2 : in std_logic; ZN : out std_logic);
end component;
component OAI22_X1
port( A1, A2, B1, B2 : in std_logic; ZN : out std_logic);
end component;
component AOI221_X1
port( B1, B2, C1, C2, A : in std_logic; ZN : out std_logic);
end component;
component NAND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component OAI21_X1
port( B1, B2, A : in std_logic; ZN : out std_logic);
end component;
component AND2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component NOR2_X2
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
component NAND3_X1
port( A1, A2, A3 : in std_logic; ZN : out std_logic);
end component;
component NOR2_X1
port( A1, A2 : in std_logic; ZN : out std_logic);
end component;
signal n511, n512, n513, n514, n222, n515, n516, n517, ram_0_7_port,
ram_0_6_port, ram_0_5_port, ram_0_4_port, ram_0_3_port, ram_0_2_port,
ram_0_1_port, ram_0_0_port, ram_1_7_port, ram_1_6_port, ram_1_5_port,
ram_1_4_port, ram_1_3_port, ram_1_2_port, ram_1_1_port, ram_1_0_port,
ram_2_7_port, ram_2_6_port, ram_2_5_port, ram_2_4_port, ram_2_3_port,
ram_2_2_port, ram_2_1_port, ram_2_0_port, ram_3_7_port, ram_3_6_port,
ram_3_5_port, ram_3_4_port, ram_3_3_port, ram_3_2_port, ram_3_1_port,
ram_3_0_port, ram_4_7_port, ram_4_6_port, ram_4_5_port, ram_4_4_port,
ram_4_3_port, ram_4_2_port, ram_4_1_port, ram_4_0_port, ram_5_7_port,
ram_5_6_port, ram_5_5_port, ram_5_4_port, ram_5_3_port, ram_5_2_port,
ram_5_1_port, ram_5_0_port, ram_6_7_port, ram_6_6_port, ram_6_5_port,
ram_6_4_port, ram_6_3_port, ram_6_2_port, ram_6_1_port, ram_6_0_port,
ram_7_7_port, ram_7_6_port, ram_7_5_port, ram_7_4_port, ram_7_3_port,
ram_7_2_port, ram_7_1_port, ram_7_0_port, N33, N34, N35, N36, N37, N38,
N39, N40, n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30, n31, n32
, n33_port, n34_port, n35_port, n36_port, n37_port, n38_port, n39_port,
n40_port, n41, n42, n43, n44, n45, n46, n47, n48, n49, n50, n51, n52, n53
, n54, n55, n56, n57, n58, n59, n60, n61, n62, n63, n64, n65, n66, n67,
n68, n69, n70, n71, n72, n73, n74, n75, n76, n77, n78, n79, n80, n81, n82
, n83, n84, n85, n86, n87, n88, n89, n90, n91, n92, n93, n100, n101, n102
, n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16,
n17, n18, n19, n94, n95, n96, n97, n98, n99, n167, n168, n169, n170, n171
, n172, n173, n174, n175, n176, n177, n178, n179, n180, n181, n182, n183,
n184, n185, n186, n187, n188, n189, n190, n191, n192, n193, n194, n195,
n196, n199, n200, n201, n202, n203, n212, n213, n214, n215, n216, n217,
n218, n219, n220, n221, n295, n296, n297, n298, n299, n300, n301, n302,
n303, n304, n305, n306, n307, n308, n309, n310, n311, n312, n313, n314,
n315, n316, n317, n318, n319, n320, n321, n322, n323, n324, n325, n326,
n327, n328, n329, n330, n331, n332, n333, n334, n335, n336, n337, n338,
n339, n340, n341, n342, n343, n344, n345, n346, n347, n348, n349, n350,
n351, n352, n353, n354, n355, n356, n357, n358, dataout_4_port, n360,
dataout_2_port, dataout_1_port, dataout_0_port, dataout_5_port,
dataout_7_port, dataout_6_port, n_1078, n_1079, n_1080, n_1081, n_1082,
n_1083, n_1084, n_1085, n_1086, n_1087, n_1088, n_1089, n_1090, n_1091,
n_1092, n_1093, n_1094, n_1095, n_1096, n_1097, n_1098, n_1099, n_1100,
n_1101, n_1102, n_1103, n_1104, n_1105, n_1106, n_1107, n_1108, n_1109,
n_1110, n_1111, n_1112, n_1113, n_1114, n_1115, n_1116, n_1117, n_1118,
n_1119, n_1120, n_1121, n_1122, n_1123, n_1124, n_1125, n_1126, n_1127,
n_1128, n_1129, n_1130, n_1131, n_1132, n_1133, n_1134, n_1135, n_1136,
n_1137, n_1138, n_1139, n_1140, n_1141, n_1142, n_1143, n_1144, n_1145,
n_1146, n_1147, n_1148, n_1149 : std_logic;
begin
dataout <= ( dataout_7_port, dataout_6_port, dataout_5_port, dataout_4_port,
n360, dataout_2_port, dataout_1_port, dataout_0_port );
U161 : NAND3_X1 port map( A1 => address(0), A2 => n29, A3 => address(1), ZN
=> n20);
U163 : NAND3_X1 port map( A1 => n29, A2 => n213, A3 => address(0), ZN =>
n39_port);
U167 : NAND3_X1 port map( A1 => address(0), A2 => n213, A3 => n66, ZN => n76
);
U3 : NOR2_X2 port map( A1 => n179, A2 => address(1), ZN => n176);
U4 : NOR2_X2 port map( A1 => address(1), A2 => address(2), ZN => n173);
U5 : NOR2_X1 port map( A1 => read_enable, A2 => write_enable, ZN => n1);
U6 : NOR2_X2 port map( A1 => n179, A2 => n213, ZN => n175);
U7 : NAND3_X1 port map( A1 => n180, A2 => n213, A3 => n66, ZN => n85);
U8 : NAND3_X1 port map( A1 => n180, A2 => n213, A3 => n29, ZN => n48);
U9 : NAND3_X1 port map( A1 => address(1), A2 => address(0), A3 => n66, ZN =>
n57);
U10 : NOR2_X1 port map( A1 => n212, A2 => address(2), ZN => n66);
U11 : INV_X1 port map( A => write_enable, ZN => n212);
U12 : NAND3_X1 port map( A1 => address(1), A2 => n180, A3 => n66, ZN => n67)
;
U13 : NAND3_X1 port map( A1 => n29, A2 => n180, A3 => address(1), ZN => n30)
;
U14 : NOR2_X2 port map( A1 => n213, A2 => address(2), ZN => n172);
U15 : INV_X1 port map( A => n174, ZN => n196);
U16 : INV_X1 port map( A => n97, ZN => n194);
U17 : INV_X1 port map( A => n7, ZN => n190);
U18 : INV_X1 port map( A => n3, ZN => n189);
U19 : INV_X1 port map( A => n11, ZN => n191);
U20 : INV_X1 port map( A => n15, ZN => n192);
U21 : INV_X1 port map( A => n19, ZN => n193);
U22 : INV_X1 port map( A => n168, ZN => n195);
U23 : OAI21_X1 port map( B1 => n20, B2 => n221, A => n21, ZN => ram_7_0_port
);
U24 : NAND2_X1 port map( A1 => n358, A2 => n20, ZN => n21);
U25 : OAI21_X1 port map( B1 => n20, B2 => n220, A => n22, ZN => ram_7_1_port
);
U26 : NAND2_X1 port map( A1 => n357, A2 => n20, ZN => n22);
U27 : OAI21_X1 port map( B1 => n20, B2 => n219, A => n23, ZN => ram_7_2_port
);
U28 : NAND2_X1 port map( A1 => n356, A2 => n20, ZN => n23);
U29 : OAI21_X1 port map( B1 => n20, B2 => n218, A => n24, ZN => ram_7_3_port
);
U30 : NAND2_X1 port map( A1 => n355, A2 => n20, ZN => n24);
U31 : OAI21_X1 port map( B1 => n20, B2 => n217, A => n25, ZN => ram_7_4_port
);
U32 : NAND2_X1 port map( A1 => n354, A2 => n20, ZN => n25);
U33 : OAI21_X1 port map( B1 => n20, B2 => n216, A => n26, ZN => ram_7_5_port
);
U34 : NAND2_X1 port map( A1 => n353, A2 => n20, ZN => n26);
U35 : OAI21_X1 port map( B1 => n20, B2 => n215, A => n27, ZN => ram_7_6_port
);
U36 : NAND2_X1 port map( A1 => n352, A2 => n20, ZN => n27);
U37 : OAI21_X1 port map( B1 => n20, B2 => n214, A => n28, ZN => ram_7_7_port
);
U38 : NAND2_X1 port map( A1 => n351, A2 => n20, ZN => n28);
U39 : OAI21_X1 port map( B1 => n221, B2 => n76, A => n77, ZN => ram_1_0_port
);
U40 : NAND2_X1 port map( A1 => n350, A2 => n76, ZN => n77);
U41 : OAI21_X1 port map( B1 => n220, B2 => n76, A => n78, ZN => ram_1_1_port
);
U42 : NAND2_X1 port map( A1 => n349, A2 => n76, ZN => n78);
U43 : OAI21_X1 port map( B1 => n219, B2 => n76, A => n79, ZN => ram_1_2_port
);
U44 : NAND2_X1 port map( A1 => n348, A2 => n76, ZN => n79);
U45 : OAI21_X1 port map( B1 => n218, B2 => n76, A => n80, ZN => ram_1_3_port
);
U46 : NAND2_X1 port map( A1 => n347, A2 => n76, ZN => n80);
U47 : OAI21_X1 port map( B1 => n217, B2 => n76, A => n81, ZN => ram_1_4_port
);
U48 : NAND2_X1 port map( A1 => n346, A2 => n76, ZN => n81);
U49 : OAI21_X1 port map( B1 => n216, B2 => n76, A => n82, ZN => ram_1_5_port
);
U50 : NAND2_X1 port map( A1 => n345, A2 => n76, ZN => n82);
U51 : OAI21_X1 port map( B1 => n215, B2 => n76, A => n83, ZN => ram_1_6_port
);
U52 : NAND2_X1 port map( A1 => n344, A2 => n76, ZN => n83);
U53 : OAI21_X1 port map( B1 => n214, B2 => n76, A => n84, ZN => ram_1_7_port
);
U54 : NAND2_X1 port map( A1 => n343, A2 => n76, ZN => n84);
U55 : OAI21_X1 port map( B1 => n221, B2 => n39_port, A => n40_port, ZN =>
ram_5_0_port);
U56 : NAND2_X1 port map( A1 => n342, A2 => n39_port, ZN => n40_port);
U57 : OAI21_X1 port map( B1 => n220, B2 => n39_port, A => n41, ZN =>
ram_5_1_port);
U58 : NAND2_X1 port map( A1 => n341, A2 => n39_port, ZN => n41);
U59 : OAI21_X1 port map( B1 => n219, B2 => n39_port, A => n42, ZN =>
ram_5_2_port);
U60 : NAND2_X1 port map( A1 => n340, A2 => n39_port, ZN => n42);
U61 : OAI21_X1 port map( B1 => n218, B2 => n39_port, A => n43, ZN =>
ram_5_3_port);
U62 : NAND2_X1 port map( A1 => n339, A2 => n39_port, ZN => n43);
U63 : OAI21_X1 port map( B1 => n217, B2 => n39_port, A => n44, ZN =>
ram_5_4_port);
U64 : NAND2_X1 port map( A1 => n338, A2 => n39_port, ZN => n44);
U65 : OAI21_X1 port map( B1 => n216, B2 => n39_port, A => n45, ZN =>
ram_5_5_port);
U66 : NAND2_X1 port map( A1 => n337, A2 => n39_port, ZN => n45);
U67 : OAI21_X1 port map( B1 => n215, B2 => n39_port, A => n46, ZN =>
ram_5_6_port);
U68 : NAND2_X1 port map( A1 => n336, A2 => n39_port, ZN => n46);
U69 : OAI21_X1 port map( B1 => n214, B2 => n39_port, A => n47, ZN =>
ram_5_7_port);
U70 : NAND2_X1 port map( A1 => n335, A2 => n39_port, ZN => n47);
U71 : INV_X1 port map( A => address(0), ZN => n180);
U72 : INV_X1 port map( A => address(1), ZN => n213);
U73 : AND2_X1 port map( A1 => write_enable, A2 => address(2), ZN => n29);
U74 : OAI21_X1 port map( B1 => n221, B2 => n57, A => n58, ZN => ram_3_0_port
);
U75 : NAND2_X1 port map( A1 => n334, A2 => n57, ZN => n58);
U76 : OAI21_X1 port map( B1 => n220, B2 => n57, A => n59, ZN => ram_3_1_port
);
U77 : NAND2_X1 port map( A1 => n333, A2 => n57, ZN => n59);
U78 : OAI21_X1 port map( B1 => n219, B2 => n57, A => n60, ZN => ram_3_2_port
);
U79 : NAND2_X1 port map( A1 => n332, A2 => n57, ZN => n60);
U80 : OAI21_X1 port map( B1 => n218, B2 => n57, A => n61, ZN => ram_3_3_port
);
U81 : NAND2_X1 port map( A1 => n331, A2 => n57, ZN => n61);
U82 : OAI21_X1 port map( B1 => n217, B2 => n57, A => n62, ZN => ram_3_4_port
);
U83 : NAND2_X1 port map( A1 => n330, A2 => n57, ZN => n62);
U84 : OAI21_X1 port map( B1 => n216, B2 => n57, A => n63, ZN => ram_3_5_port
);
U85 : NAND2_X1 port map( A1 => n329, A2 => n57, ZN => n63);
U86 : OAI21_X1 port map( B1 => n215, B2 => n57, A => n64, ZN => ram_3_6_port
);
U87 : NAND2_X1 port map( A1 => n328, A2 => n57, ZN => n64);
U88 : OAI21_X1 port map( B1 => n214, B2 => n57, A => n65, ZN => ram_3_7_port
);
U89 : NAND2_X1 port map( A1 => n327, A2 => n57, ZN => n65);
U90 : OAI21_X1 port map( B1 => n221, B2 => n67, A => n68, ZN => ram_2_0_port
);
U91 : NAND2_X1 port map( A1 => n326, A2 => n67, ZN => n68);
U92 : OAI21_X1 port map( B1 => n220, B2 => n67, A => n69, ZN => ram_2_1_port
);
U93 : NAND2_X1 port map( A1 => n325, A2 => n67, ZN => n69);
U94 : OAI21_X1 port map( B1 => n219, B2 => n67, A => n70, ZN => ram_2_2_port
);
U95 : NAND2_X1 port map( A1 => n324, A2 => n67, ZN => n70);
U96 : OAI21_X1 port map( B1 => n218, B2 => n67, A => n71, ZN => ram_2_3_port
);
U97 : NAND2_X1 port map( A1 => n323, A2 => n67, ZN => n71);
U98 : OAI21_X1 port map( B1 => n217, B2 => n67, A => n72, ZN => ram_2_4_port
);
U99 : NAND2_X1 port map( A1 => n322, A2 => n67, ZN => n72);
U100 : OAI21_X1 port map( B1 => n216, B2 => n67, A => n73, ZN =>
ram_2_5_port);
U101 : NAND2_X1 port map( A1 => n321, A2 => n67, ZN => n73);
U102 : OAI21_X1 port map( B1 => n215, B2 => n67, A => n74, ZN =>
ram_2_6_port);
U103 : NAND2_X1 port map( A1 => n320, A2 => n67, ZN => n74);
U104 : OAI21_X1 port map( B1 => n214, B2 => n67, A => n75, ZN =>
ram_2_7_port);
U105 : NAND2_X1 port map( A1 => n319, A2 => n67, ZN => n75);
U106 : OAI21_X1 port map( B1 => n221, B2 => n30, A => n31, ZN =>
ram_6_0_port);
U107 : NAND2_X1 port map( A1 => n318, A2 => n30, ZN => n31);
U108 : OAI21_X1 port map( B1 => n220, B2 => n30, A => n32, ZN =>
ram_6_1_port);
U109 : NAND2_X1 port map( A1 => n317, A2 => n30, ZN => n32);
U110 : OAI21_X1 port map( B1 => n219, B2 => n30, A => n33_port, ZN =>
ram_6_2_port);
U111 : NAND2_X1 port map( A1 => n316, A2 => n30, ZN => n33_port);
U112 : OAI21_X1 port map( B1 => n218, B2 => n30, A => n34_port, ZN =>
ram_6_3_port);
U113 : NAND2_X1 port map( A1 => n315, A2 => n30, ZN => n34_port);
U114 : OAI21_X1 port map( B1 => n217, B2 => n30, A => n35_port, ZN =>
ram_6_4_port);
U115 : NAND2_X1 port map( A1 => n314, A2 => n30, ZN => n35_port);
U116 : OAI21_X1 port map( B1 => n216, B2 => n30, A => n36_port, ZN =>
ram_6_5_port);
U117 : NAND2_X1 port map( A1 => n313, A2 => n30, ZN => n36_port);
U118 : OAI21_X1 port map( B1 => n215, B2 => n30, A => n37_port, ZN =>
ram_6_6_port);
U119 : NAND2_X1 port map( A1 => n312, A2 => n30, ZN => n37_port);
U120 : OAI21_X1 port map( B1 => n214, B2 => n30, A => n38_port, ZN =>
ram_6_7_port);
U121 : NAND2_X1 port map( A1 => n311, A2 => n30, ZN => n38_port);
U122 : OAI21_X1 port map( B1 => n221, B2 => n85, A => n86, ZN =>
ram_0_0_port);
U123 : NAND2_X1 port map( A1 => n310, A2 => n85, ZN => n86);
U124 : OAI21_X1 port map( B1 => n220, B2 => n85, A => n87, ZN =>
ram_0_1_port);
U125 : NAND2_X1 port map( A1 => n309, A2 => n85, ZN => n87);
U126 : OAI21_X1 port map( B1 => n219, B2 => n85, A => n88, ZN =>
ram_0_2_port);
U127 : NAND2_X1 port map( A1 => n308, A2 => n85, ZN => n88);
U128 : OAI21_X1 port map( B1 => n218, B2 => n85, A => n89, ZN =>
ram_0_3_port);
U129 : NAND2_X1 port map( A1 => n307, A2 => n85, ZN => n89);
U130 : OAI21_X1 port map( B1 => n217, B2 => n85, A => n90, ZN =>
ram_0_4_port);
U131 : NAND2_X1 port map( A1 => n306, A2 => n85, ZN => n90);
U132 : OAI21_X1 port map( B1 => n216, B2 => n85, A => n91, ZN =>
ram_0_5_port);
U133 : NAND2_X1 port map( A1 => n305, A2 => n85, ZN => n91);
U134 : OAI21_X1 port map( B1 => n215, B2 => n85, A => n92, ZN =>
ram_0_6_port);
U135 : NAND2_X1 port map( A1 => n304, A2 => n85, ZN => n92);
U136 : OAI21_X1 port map( B1 => n214, B2 => n85, A => n93, ZN =>
ram_0_7_port);
U137 : NAND2_X1 port map( A1 => n303, A2 => n85, ZN => n93);
U138 : OAI21_X1 port map( B1 => n221, B2 => n48, A => n49, ZN =>
ram_4_0_port);
U139 : NAND2_X1 port map( A1 => n302, A2 => n48, ZN => n49);
U140 : OAI21_X1 port map( B1 => n220, B2 => n48, A => n50, ZN =>
ram_4_1_port);
U141 : NAND2_X1 port map( A1 => n301, A2 => n48, ZN => n50);
U142 : OAI21_X1 port map( B1 => n219, B2 => n48, A => n51, ZN =>
ram_4_2_port);
U143 : NAND2_X1 port map( A1 => n300, A2 => n48, ZN => n51);
U144 : OAI21_X1 port map( B1 => n218, B2 => n48, A => n52, ZN =>
ram_4_3_port);
U145 : NAND2_X1 port map( A1 => n299, A2 => n48, ZN => n52);
U146 : OAI21_X1 port map( B1 => n217, B2 => n48, A => n53, ZN =>
ram_4_4_port);
U147 : NAND2_X1 port map( A1 => n298, A2 => n48, ZN => n53);
U148 : OAI21_X1 port map( B1 => n216, B2 => n48, A => n54, ZN =>
ram_4_5_port);
U149 : NAND2_X1 port map( A1 => n297, A2 => n48, ZN => n54);
U150 : OAI21_X1 port map( B1 => n215, B2 => n48, A => n55, ZN =>
ram_4_6_port);
U151 : NAND2_X1 port map( A1 => n296, A2 => n48, ZN => n55);
U152 : OAI21_X1 port map( B1 => n214, B2 => n48, A => n56, ZN =>
ram_4_7_port);
U153 : NAND2_X1 port map( A1 => n295, A2 => n48, ZN => n56);
U154 : INV_X1 port map( A => address(2), ZN => n179);
U155 : INV_X1 port map( A => n171, ZN => n188);
U156 : INV_X1 port map( A => n96, ZN => n186);
U157 : INV_X1 port map( A => n6, ZN => n182);
U158 : INV_X1 port map( A => n2, ZN => n181);
U159 : INV_X1 port map( A => n10, ZN => n183);
U160 : INV_X1 port map( A => n14, ZN => n184);
U162 : INV_X1 port map( A => n18, ZN => n185);
U164 : INV_X1 port map( A => n167, ZN => n187);
U165 : INV_X1 port map( A => n101, ZN => n512);
U166 : AOI22_X1 port map( A1 => N34, A2 => read_enable, B1 => dataout_6_port
, B2 => n1, ZN => n101);
U168 : INV_X1 port map( A => datain(0), ZN => n221);
U169 : INV_X1 port map( A => datain(1), ZN => n220);
U170 : INV_X1 port map( A => datain(2), ZN => n219);
U171 : INV_X1 port map( A => datain(3), ZN => n218);
U172 : INV_X1 port map( A => datain(4), ZN => n217);
U173 : INV_X1 port map( A => datain(5), ZN => n216);
U174 : INV_X1 port map( A => datain(6), ZN => n215);
U175 : INV_X1 port map( A => datain(7), ZN => n214);
U176 : AOI22_X1 port map( A1 => n350, A2 => n173, B1 => n334, B2 => n172, ZN
=> n2);
U177 : AOI221_X1 port map( B1 => n342, B2 => n176, C1 => n358, C2 => n175, A
=> n181, ZN => n5);
U178 : AOI22_X1 port map( A1 => n310, A2 => n173, B1 => n326, B2 => n172, ZN
=> n3);
U179 : AOI221_X1 port map( B1 => n302, B2 => n176, C1 => n318, C2 => n175, A
=> n189, ZN => n4);
U180 : OAI22_X1 port map( A1 => n180, A2 => n5, B1 => address(0), B2 => n4,
ZN => N40);
U181 : AOI22_X1 port map( A1 => n349, A2 => n173, B1 => n333, B2 => n172, ZN
=> n6);
U182 : AOI221_X1 port map( B1 => n341, B2 => n176, C1 => n357, C2 => n175, A
=> n182, ZN => n9);
U183 : AOI22_X1 port map( A1 => n309, A2 => n173, B1 => n325, B2 => n172, ZN
=> n7);
U184 : AOI221_X1 port map( B1 => n301, B2 => n176, C1 => n317, C2 => n175, A
=> n190, ZN => n8);
U185 : OAI22_X1 port map( A1 => n180, A2 => n9, B1 => address(0), B2 => n8,
ZN => N39);
U186 : AOI22_X1 port map( A1 => n348, A2 => n173, B1 => n332, B2 => n172, ZN
=> n10);
U187 : AOI221_X1 port map( B1 => n340, B2 => n176, C1 => n356, C2 => n175, A
=> n183, ZN => n13);
U188 : AOI22_X1 port map( A1 => n308, A2 => n173, B1 => n324, B2 => n172, ZN
=> n11);
U189 : AOI221_X1 port map( B1 => n300, B2 => n176, C1 => n316, C2 => n175, A
=> n191, ZN => n12);
U190 : OAI22_X1 port map( A1 => n180, A2 => n13, B1 => address(0), B2 => n12
, ZN => N38);
U191 : AOI22_X1 port map( A1 => n347, A2 => n173, B1 => n331, B2 => n172, ZN
=> n14);
U192 : AOI221_X1 port map( B1 => n339, B2 => n176, C1 => n355, C2 => n175, A
=> n184, ZN => n17);
U193 : AOI22_X1 port map( A1 => n307, A2 => n173, B1 => n323, B2 => n172, ZN
=> n15);
U194 : AOI221_X1 port map( B1 => n299, B2 => n176, C1 => n315, C2 => n175, A
=> n192, ZN => n16);
U195 : OAI22_X1 port map( A1 => n180, A2 => n17, B1 => address(0), B2 => n16
, ZN => N37);
U196 : AOI22_X1 port map( A1 => n346, A2 => n173, B1 => n330, B2 => n172, ZN
=> n18);
U197 : AOI221_X1 port map( B1 => n338, B2 => n176, C1 => n354, C2 => n175, A
=> n185, ZN => n95);
U198 : AOI22_X1 port map( A1 => n306, A2 => n173, B1 => n322, B2 => n172, ZN
=> n19);
U199 : AOI221_X1 port map( B1 => n298, B2 => n176, C1 => n314, C2 => n175, A
=> n193, ZN => n94);
U200 : OAI22_X1 port map( A1 => n180, A2 => n95, B1 => address(0), B2 => n94
, ZN => N36);
U201 : AOI22_X1 port map( A1 => n345, A2 => n173, B1 => n329, B2 => n172, ZN
=> n96);
U202 : AOI221_X1 port map( B1 => n337, B2 => n176, C1 => n353, C2 => n175, A
=> n186, ZN => n99);
U203 : AOI22_X1 port map( A1 => n305, A2 => n173, B1 => n321, B2 => n172, ZN
=> n97);
U204 : AOI221_X1 port map( B1 => n297, B2 => n176, C1 => n313, C2 => n175, A
=> n194, ZN => n98);
U205 : OAI22_X1 port map( A1 => n180, A2 => n99, B1 => address(0), B2 => n98
, ZN => N35);
U206 : AOI22_X1 port map( A1 => n344, A2 => n173, B1 => n328, B2 => n172, ZN
=> n167);
U207 : AOI221_X1 port map( B1 => n336, B2 => n176, C1 => n352, C2 => n175, A
=> n187, ZN => n170);
U208 : AOI22_X1 port map( A1 => n304, A2 => n173, B1 => n320, B2 => n172, ZN
=> n168);
U209 : AOI221_X1 port map( B1 => n296, B2 => n176, C1 => n312, C2 => n175, A
=> n195, ZN => n169);
U210 : OAI22_X1 port map( A1 => n180, A2 => n170, B1 => address(0), B2 =>
n169, ZN => N34);
U211 : AOI22_X1 port map( A1 => n343, A2 => n173, B1 => n327, B2 => n172, ZN
=> n171);
U212 : AOI221_X1 port map( B1 => n335, B2 => n176, C1 => n351, C2 => n175, A
=> n188, ZN => n178);
U213 : AOI22_X1 port map( A1 => n303, A2 => n173, B1 => n319, B2 => n172, ZN
=> n174);
U214 : AOI221_X1 port map( B1 => n295, B2 => n176, C1 => n311, C2 => n175, A
=> n196, ZN => n177);
U215 : OAI22_X1 port map( A1 => n178, A2 => n180, B1 => address(0), B2 =>
n177, ZN => N33);
U216 : INV_X1 port map( A => n102, ZN => n511);
U218 : INV_X1 port map( A => n100, ZN => n513);
U219 : AOI22_X1 port map( A1 => N33, A2 => read_enable, B1 => dataout_7_port
, B2 => n1, ZN => n102);
U220 : AOI22_X1 port map( A1 => N35, A2 => read_enable, B1 => dataout_5_port
, B2 => n1, ZN => n100);
U221 : AOI22_X1 port map( A1 => N40, A2 => read_enable, B1 => dataout_0_port
, B2 => n1, ZN => n199);
U222 : INV_X1 port map( A => n199, ZN => n517);
U223 : AOI22_X1 port map( A1 => N39, A2 => read_enable, B1 => dataout_1_port
, B2 => n1, ZN => n200);
U224 : INV_X1 port map( A => n200, ZN => n516);
U225 : AOI22_X1 port map( A1 => N38, A2 => read_enable, B1 => dataout_2_port
, B2 => n1, ZN => n201);
U226 : INV_X1 port map( A => n201, ZN => n515);
U227 : AOI22_X1 port map( A1 => N37, A2 => read_enable, B1 => n360, B2 => n1
, ZN => n202);
U228 : INV_X1 port map( A => n202, ZN => n222);
U229 : AOI22_X1 port map( A1 => N36, A2 => read_enable, B1 => dataout_4_port
, B2 => n1, ZN => n203);
U230 : INV_X1 port map( A => n203, ZN => n514);
clock_r_REG209_S3 : DFF_X1 port map( D => n512, CK => clock, Q =>
dataout_6_port, QN => n_1078);
clock_r_REG202_S3 : DFF_X1 port map( D => n511, CK => clock, Q =>
dataout_7_port, QN => n_1079);
clock_r_REG213_S3 : DFF_X1 port map( D => n513, CK => clock, Q =>
dataout_5_port, QN => n_1080);
clock_r_REG233_S3 : DFF_X1 port map( D => n517, CK => clock, Q =>
dataout_0_port, QN => n_1081);
clock_r_REG229_S3 : DFF_X1 port map( D => n516, CK => clock, Q =>
dataout_1_port, QN => n_1082);
clock_r_REG225_S3 : DFF_X1 port map( D => n515, CK => clock, Q =>
dataout_2_port, QN => n_1083);
clock_r_REG221_S3 : DFF_X1 port map( D => n222, CK => clock, Q => n360, QN
=> n_1084);
clock_r_REG217_S3 : DFF_X1 port map( D => n514, CK => clock, Q =>
dataout_4_port, QN => n_1085);
clock_r_REG232_S2 : DFF_X1 port map( D => ram_7_0_port, CK => clock, Q =>
n358, QN => n_1086);
clock_r_REG228_S2 : DFF_X1 port map( D => ram_7_1_port, CK => clock, Q =>
n357, QN => n_1087);
clock_r_REG224_S2 : DFF_X1 port map( D => ram_7_2_port, CK => clock, Q =>
n356, QN => n_1088);
clock_r_REG220_S2 : DFF_X1 port map( D => ram_7_3_port, CK => clock, Q =>
n355, QN => n_1089);
clock_r_REG216_S2 : DFF_X1 port map( D => ram_7_4_port, CK => clock, Q =>
n354, QN => n_1090);
clock_r_REG212_S2 : DFF_X1 port map( D => ram_7_5_port, CK => clock, Q =>
n353, QN => n_1091);
clock_r_REG208_S2 : DFF_X1 port map( D => ram_7_6_port, CK => clock, Q =>
n352, QN => n_1092);
clock_r_REG201_S2 : DFF_X1 port map( D => ram_7_7_port, CK => clock, Q =>
n351, QN => n_1093);
clock_r_REG267_S2 : DFF_X1 port map( D => ram_1_0_port, CK => clock, Q =>
n350, QN => n_1094);
clock_r_REG266_S2 : DFF_X1 port map( D => ram_1_1_port, CK => clock, Q =>
n349, QN => n_1095);
clock_r_REG265_S2 : DFF_X1 port map( D => ram_1_2_port, CK => clock, Q =>
n348, QN => n_1096);
clock_r_REG264_S2 : DFF_X1 port map( D => ram_1_3_port, CK => clock, Q =>
n347, QN => n_1097);
clock_r_REG263_S2 : DFF_X1 port map( D => ram_1_4_port, CK => clock, Q =>
n346, QN => n_1098);
clock_r_REG262_S2 : DFF_X1 port map( D => ram_1_5_port, CK => clock, Q =>
n345, QN => n_1099);
clock_r_REG261_S2 : DFF_X1 port map( D => ram_1_6_port, CK => clock, Q =>
n344, QN => n_1100);
clock_r_REG260_S2 : DFF_X1 port map( D => ram_1_7_port, CK => clock, Q =>
n343, QN => n_1101);
clock_r_REG243_S2 : DFF_X1 port map( D => ram_5_0_port, CK => clock, Q =>
n342, QN => n_1102);
clock_r_REG242_S2 : DFF_X1 port map( D => ram_5_1_port, CK => clock, Q =>
n341, QN => n_1103);
clock_r_REG241_S2 : DFF_X1 port map( D => ram_5_2_port, CK => clock, Q =>
n340, QN => n_1104);
clock_r_REG240_S2 : DFF_X1 port map( D => ram_5_3_port, CK => clock, Q =>
n339, QN => n_1105);
clock_r_REG239_S2 : DFF_X1 port map( D => ram_5_4_port, CK => clock, Q =>
n338, QN => n_1106);
clock_r_REG238_S2 : DFF_X1 port map( D => ram_5_5_port, CK => clock, Q =>
n337, QN => n_1107);
clock_r_REG237_S2 : DFF_X1 port map( D => ram_5_6_port, CK => clock, Q =>
n336, QN => n_1108);
clock_r_REG236_S2 : DFF_X1 port map( D => ram_5_7_port, CK => clock, Q =>
n335, QN => n_1109);
clock_r_REG283_S2 : DFF_X1 port map( D => ram_3_0_port, CK => clock, Q =>
n334, QN => n_1110);
clock_r_REG282_S2 : DFF_X1 port map( D => ram_3_1_port, CK => clock, Q =>
n333, QN => n_1111);
clock_r_REG281_S2 : DFF_X1 port map( D => ram_3_2_port, CK => clock, Q =>
n332, QN => n_1112);
clock_r_REG280_S2 : DFF_X1 port map( D => ram_3_3_port, CK => clock, Q =>
n331, QN => n_1113);
clock_r_REG279_S2 : DFF_X1 port map( D => ram_3_4_port, CK => clock, Q =>
n330, QN => n_1114);
clock_r_REG278_S2 : DFF_X1 port map( D => ram_3_5_port, CK => clock, Q =>
n329, QN => n_1115);
clock_r_REG277_S2 : DFF_X1 port map( D => ram_3_6_port, CK => clock, Q =>
n328, QN => n_1116);
clock_r_REG276_S2 : DFF_X1 port map( D => ram_3_7_port, CK => clock, Q =>
n327, QN => n_1117);
clock_r_REG275_S2 : DFF_X1 port map( D => ram_2_0_port, CK => clock, Q =>
n326, QN => n_1118);
clock_r_REG274_S2 : DFF_X1 port map( D => ram_2_1_port, CK => clock, Q =>
n325, QN => n_1119);
clock_r_REG273_S2 : DFF_X1 port map( D => ram_2_2_port, CK => clock, Q =>
n324, QN => n_1120);
clock_r_REG272_S2 : DFF_X1 port map( D => ram_2_3_port, CK => clock, Q =>
n323, QN => n_1121);
clock_r_REG271_S2 : DFF_X1 port map( D => ram_2_4_port, CK => clock, Q =>
n322, QN => n_1122);
clock_r_REG270_S2 : DFF_X1 port map( D => ram_2_5_port, CK => clock, Q =>
n321, QN => n_1123);
clock_r_REG269_S2 : DFF_X1 port map( D => ram_2_6_port, CK => clock, Q =>
n320, QN => n_1124);
clock_r_REG268_S2 : DFF_X1 port map( D => ram_2_7_port, CK => clock, Q =>
n319, QN => n_1125);
clock_r_REG251_S2 : DFF_X1 port map( D => ram_6_0_port, CK => clock, Q =>
n318, QN => n_1126);
clock_r_REG250_S2 : DFF_X1 port map( D => ram_6_1_port, CK => clock, Q =>
n317, QN => n_1127);
clock_r_REG249_S2 : DFF_X1 port map( D => ram_6_2_port, CK => clock, Q =>
n316, QN => n_1128);
clock_r_REG248_S2 : DFF_X1 port map( D => ram_6_3_port, CK => clock, Q =>
n315, QN => n_1129);
clock_r_REG247_S2 : DFF_X1 port map( D => ram_6_4_port, CK => clock, Q =>
n314, QN => n_1130);
clock_r_REG246_S2 : DFF_X1 port map( D => ram_6_5_port, CK => clock, Q =>
n313, QN => n_1131);
clock_r_REG245_S2 : DFF_X1 port map( D => ram_6_6_port, CK => clock, Q =>
n312, QN => n_1132);
clock_r_REG244_S2 : DFF_X1 port map( D => ram_6_7_port, CK => clock, Q =>
n311, QN => n_1133);
clock_r_REG291_S2 : DFF_X1 port map( D => ram_0_0_port, CK => clock, Q =>
n310, QN => n_1134);
clock_r_REG290_S2 : DFF_X1 port map( D => ram_0_1_port, CK => clock, Q =>
n309, QN => n_1135);
clock_r_REG289_S2 : DFF_X1 port map( D => ram_0_2_port, CK => clock, Q =>
n308, QN => n_1136);
clock_r_REG288_S2 : DFF_X1 port map( D => ram_0_3_port, CK => clock, Q =>
n307, QN => n_1137);
clock_r_REG287_S2 : DFF_X1 port map( D => ram_0_4_port, CK => clock, Q =>
n306, QN => n_1138);
clock_r_REG286_S2 : DFF_X1 port map( D => ram_0_5_port, CK => clock, Q =>
n305, QN => n_1139);
clock_r_REG285_S2 : DFF_X1 port map( D => ram_0_6_port, CK => clock, Q =>
n304, QN => n_1140);
clock_r_REG284_S2 : DFF_X1 port map( D => ram_0_7_port, CK => clock, Q =>
n303, QN => n_1141);
clock_r_REG259_S2 : DFF_X1 port map( D => ram_4_0_port, CK => clock, Q =>
n302, QN => n_1142);
clock_r_REG258_S2 : DFF_X1 port map( D => ram_4_1_port, CK => clock, Q =>
n301, QN => n_1143);
clock_r_REG257_S2 : DFF_X1 port map( D => ram_4_2_port, CK => clock, Q =>
n300, QN => n_1144);
clock_r_REG256_S2 : DFF_X1 port map( D => ram_4_3_port, CK => clock, Q =>
n299, QN => n_1145);
clock_r_REG255_S2 : DFF_X1 port map( D => ram_4_4_port, CK => clock, Q =>
n298, QN => n_1146);
clock_r_REG254_S2 : DFF_X1 port map( D => ram_4_5_port, CK => clock, Q =>
n297, QN => n_1147);
clock_r_REG253_S2 : DFF_X1 port map( D => ram_4_6_port, CK => clock, Q =>
n296, QN => n_1148);
clock_r_REG252_S2 : DFF_X1 port map( D => ram_4_7_port, CK => clock, Q =>
n295, QN => n_1149);
end SYN_ramA;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_project2.all;
entity counter_address_generator_0 is
port( clock, reset, need_to_reset, enable, read_enable : in std_logic;
address : out std_logic_vector (7 downto 0));
end counter_address_generator_0;
architecture SYN_counter_address_generator of counter_address_generator_0 is
component counter_address_generator_0_DW01_inc_0
port( A : in std_logic_vector (7 downto 0); SUM : out std_logic_vector
(7 downto 0));
end component;
component DFF_X1
port( D, CK : in std_logic; Q, QN : out std_logic);
end component;
component AOI22_X1
port( A1, A2, B1, B2 : in std_logic; ZN : out std_logic);
end component;
component INV_X1
port( A : in std_logic; ZN : out std_logic);
end component;
component NOR3_X2
port( A1, A2, A3 : in std_logic; ZN : out std_logic);
end component;
signal n51, n52, n53, n54, n55, n56, n57, n58, N10, N11, N12, N13, N14, N15,
N16, N17, n9, n10_port, n11_port, n12_port, n13_port, n14_port, n15_port,
n16_port, n17_port, n18, address_0_port, address_1_port, address_2_port,
address_3_port, address_4_port, address_5_port, address_6_port,
address_7_port, n_1150, n_1151, n_1152, n_1153, n_1154, n_1155, n_1156,
n_1157 : std_logic;
begin
address <= ( address_7_port, address_6_port, address_5_port, address_4_port,
address_3_port, address_2_port, address_1_port, address_0_port );
U3 : NOR3_X2 port map( A1 => reset, A2 => need_to_reset, A3 => n11_port, ZN
=> n10_port);
U4 : NOR3_X2 port map( A1 => reset, A2 => read_enable, A3 => enable, ZN =>
n11_port);
U5 : INV_X1 port map( A => n9, ZN => n51);
U6 : AOI22_X1 port map( A1 => N17, A2 => n10_port, B1 => address_7_port, B2
=> n11_port, ZN => n9);
U7 : INV_X1 port map( A => n12_port, ZN => n52);
U8 : AOI22_X1 port map( A1 => N16, A2 => n10_port, B1 => address_6_port, B2
=> n11_port, ZN => n12_port);
U9 : INV_X1 port map( A => n13_port, ZN => n53);
U10 : AOI22_X1 port map( A1 => N15, A2 => n10_port, B1 => address_5_port, B2
=> n11_port, ZN => n13_port);
U11 : INV_X1 port map( A => n14_port, ZN => n54);
U12 : AOI22_X1 port map( A1 => N14, A2 => n10_port, B1 => address_4_port, B2
=> n11_port, ZN => n14_port);
U13 : INV_X1 port map( A => n15_port, ZN => n55);
U14 : AOI22_X1 port map( A1 => N13, A2 => n10_port, B1 => address_3_port, B2
=> n11_port, ZN => n15_port);
U15 : INV_X1 port map( A => n16_port, ZN => n56);
U16 : AOI22_X1 port map( A1 => N12, A2 => n10_port, B1 => address_2_port, B2
=> n11_port, ZN => n16_port);
U17 : INV_X1 port map( A => n17_port, ZN => n57);
U18 : AOI22_X1 port map( A1 => N11, A2 => n10_port, B1 => address_1_port, B2
=> n11_port, ZN => n17_port);
U19 : INV_X1 port map( A => n18, ZN => n58);
U20 : AOI22_X1 port map( A1 => N10, A2 => n10_port, B1 => address_0_port, B2
=> n11_port, ZN => n18);
clock_r_REG299_S3 : DFF_X1 port map( D => n51, CK => clock, Q =>
address_7_port, QN => n_1150);
clock_r_REG298_S3 : DFF_X1 port map( D => n52, CK => clock, Q =>
address_6_port, QN => n_1151);
clock_r_REG297_S3 : DFF_X1 port map( D => n53, CK => clock, Q =>
address_5_port, QN => n_1152);
clock_r_REG296_S3 : DFF_X1 port map( D => n54, CK => clock, Q =>
address_4_port, QN => n_1153);
clock_r_REG295_S3 : DFF_X1 port map( D => n55, CK => clock, Q =>
address_3_port, QN => n_1154);
clock_r_REG294_S3 : DFF_X1 port map( D => n56, CK => clock, Q =>
address_2_port, QN => n_1155);
clock_r_REG293_S3 : DFF_X1 port map( D => n57, CK => clock, Q =>
address_1_port, QN => n_1156);
clock_r_REG292_S3 : DFF_X1 port map( D => n58, CK => clock, Q =>
address_0_port, QN => n_1157);
add_38 : counter_address_generator_0_DW01_inc_0 port map( A(7) =>
address_7_port, A(6) => address_6_port, A(5) =>
address_5_port, A(4) => address_4_port, A(3) =>
address_3_port, A(2) => address_2_port, A(1) =>
address_1_port, A(0) => address_0_port, SUM(7) =>
N17, SUM(6) => N16, SUM(5) => N15, SUM(4) => N14,
SUM(3) => N13, SUM(2) => N12, SUM(1) => N11, SUM(0)
=> N10);
end SYN_counter_address_generator;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_project2.all;
entity project2 is
port( clock, reset, valid, hold_me : in std_logic; data_in : in
std_logic_vector (7 downto 0); data_out : out std_logic_vector (18
downto 0); hold_prev : out std_logic);
end project2;
architecture SYN_project_2 of project2 is
component ramR
port( clock, write_enable, read_enable : in std_logic; address : in
std_logic_vector (2 downto 0); datain : in std_logic_vector (18
downto 0); dataout : out std_logic_vector (18 downto 0));
end component;
component counter_address_generator_1
port( clock, reset, need_to_reset, enable, read_enable : in std_logic;
address : out std_logic_vector (7 downto 0));
end component;
component fsm
port( clock, reset : in std_logic; ramA_address : in std_logic_vector (4
downto 0); ramR_address, rom_address : in std_logic_vector (7
downto 0); hold_me : in std_logic; ramR_readEnable,
ramA_writeEnable, ramA_readEnable, ramR_writeEnable, rom_enable,
counterAddressGen_H_enable, counterAddressGen_R_enable,
counterAddressGen_A_restart, counterAddressGen_R_restart,
counterAddressGen_H_restart, mac_clean, reset_fsm, hold_prev : out
std_logic);
end component;
component mac
port( clock : in std_logic; ai, xi : in std_logic_vector (7 downto 0);
mac_clean : in std_logic; data_out : out std_logic_vector (18
downto 0));
end component;
component rom
port( clock : in std_logic; address : in std_logic_vector (5 downto 0);
rom_enable : in std_logic; data : out std_logic_vector (7 downto
0));
end component;
component counter_address_generator_2
port( clock, reset, need_to_reset, enable, read_enable : in std_logic;
address : out std_logic_vector (7 downto 0));
end component;
component ramA
port( clock, write_enable, read_enable : in std_logic; address : in
std_logic_vector (2 downto 0); datain : in std_logic_vector (7
downto 0); dataout : out std_logic_vector (7 downto 0));
end component;
component counter_address_generator_0
port( clock, reset, need_to_reset, enable, read_enable : in std_logic;
address : out std_logic_vector (7 downto 0));
end component;
signal reset_fsm, CAG_A_restart, ramA_read_enable, addressA_7_port,
addressA_6_port, addressA_5_port, addressA_4_port, addressA_3_port,
addressA_2_port, addressA_1_port, addressA_0_port, ramA_write_enable,
Ai_7_port, Ai_6_port, Ai_5_port, Ai_4_port, Ai_3_port, Ai_2_port,
Ai_1_port, Ai_0_port, CAG_H_restart, CAG_H_enable, addressH_7_port,
addressH_6_port, addressH_5_port, addressH_4_port, addressH_3_port,
addressH_2_port, addressH_1_port, addressH_0_port, romH_enable, Hi_7_port
, Hi_6_port, Hi_5_port, Hi_4_port, Hi_3_port, Hi_2_port, Hi_1_port,
Hi_0_port, clear_register, Ri_18_port, Ri_17_port, Ri_16_port, Ri_15_port
, Ri_14_port, Ri_13_port, Ri_12_port, Ri_11_port, Ri_10_port, Ri_9_port,
Ri_8_port, Ri_7_port, Ri_6_port, Ri_5_port, Ri_4_port, Ri_3_port,
Ri_2_port, Ri_1_port, Ri_0_port, addressR_7_port, addressR_6_port,
addressR_5_port, addressR_4_port, addressR_3_port, addressR_2_port,
addressR_1_port, addressR_0_port, ramR_read_enable, ramR_write_enable,
CAG_R_enable, CAG_R_restart, n1, n2, n3, n4, n5, n6, n7, n_1158, n_1159,
n_1160, n_1161, n_1162, n_1163, n_1164 : std_logic;
begin
Hi_0_port <= '0';
Hi_1_port <= '0';
Hi_2_port <= '0';
Hi_3_port <= '0';
Hi_4_port <= '0';
Hi_5_port <= '0';
Hi_6_port <= '0';
n1 <= '0';
n2 <= '0';
n3 <= '0';
n4 <= '0';
n5 <= '0';
n6 <= '0';
counterAddressGenA : counter_address_generator_0 port map( clock => clock,
reset => reset_fsm, need_to_reset => CAG_A_restart,
enable => valid, read_enable => ramA_read_enable,
address(7) => addressA_7_port, address(6) =>
addressA_6_port, address(5) => addressA_5_port,
address(4) => addressA_4_port, address(3) =>
addressA_3_port, address(2) => addressA_2_port,
address(1) => addressA_1_port, address(0) =>
addressA_0_port);
RAMA_UNIT : ramA port map( clock => clock, write_enable => ramA_write_enable
, read_enable => ramA_read_enable, address(2) =>
addressA_2_port, address(1) => addressA_1_port,
address(0) => addressA_0_port, datain(7) =>
data_in(7), datain(6) => data_in(6), datain(5) =>
data_in(5), datain(4) => data_in(4), datain(3) =>
data_in(3), datain(2) => data_in(2), datain(1) =>
data_in(1), datain(0) => data_in(0), dataout(7) =>
Ai_7_port, dataout(6) => Ai_6_port, dataout(5) =>
Ai_5_port, dataout(4) => Ai_4_port, dataout(3) =>
Ai_3_port, dataout(2) => Ai_2_port, dataout(1) =>
Ai_1_port, dataout(0) => Ai_0_port);
counterAddressGenH : counter_address_generator_2 port map( clock => clock,
reset => reset_fsm, need_to_reset => CAG_H_restart,
enable => CAG_H_enable, read_enable => CAG_H_enable,
address(7) => addressH_7_port, address(6) =>
addressH_6_port, address(5) => addressH_5_port,
address(4) => addressH_4_port, address(3) =>
addressH_3_port, address(2) => addressH_2_port,
address(1) => addressH_1_port, address(0) =>
addressH_0_port);
ROMH : rom port map( clock => n7, address(5) => n1, address(4) => n2,
address(3) => n3, address(2) => n4, address(1) => n5
, address(0) => n6, rom_enable => romH_enable,
data(7) => Hi_7_port, data(6) => n_1158, data(5) =>
n_1159, data(4) => n_1160, data(3) => n_1161,
data(2) => n_1162, data(1) => n_1163, data(0) =>
n_1164);
MAC_UNIT : mac port map( clock => clock, ai(7) => Ai_7_port, ai(6) =>
Ai_6_port, ai(5) => Ai_5_port, ai(4) => Ai_4_port,
ai(3) => Ai_3_port, ai(2) => Ai_2_port, ai(1) =>
Ai_1_port, ai(0) => Ai_0_port, xi(7) => Hi_7_port,
xi(6) => Hi_6_port, xi(5) => Hi_5_port, xi(4) =>
Hi_4_port, xi(3) => Hi_3_port, xi(2) => Hi_2_port,
xi(1) => Hi_1_port, xi(0) => Hi_0_port, mac_clean =>
clear_register, data_out(18) => Ri_18_port,
data_out(17) => Ri_17_port, data_out(16) =>
Ri_16_port, data_out(15) => Ri_15_port, data_out(14)
=> Ri_14_port, data_out(13) => Ri_13_port,
data_out(12) => Ri_12_port, data_out(11) =>
Ri_11_port, data_out(10) => Ri_10_port, data_out(9)
=> Ri_9_port, data_out(8) => Ri_8_port, data_out(7)
=> Ri_7_port, data_out(6) => Ri_6_port, data_out(5)
=> Ri_5_port, data_out(4) => Ri_4_port, data_out(3)
=> Ri_3_port, data_out(2) => Ri_2_port, data_out(1)
=> Ri_1_port, data_out(0) => Ri_0_port);
FSM_UNIT : fsm port map( clock => clock, reset => reset, ramA_address(4) =>
addressA_7_port, ramA_address(3) => addressA_6_port,
ramA_address(2) => addressA_5_port, ramA_address(1)
=> addressA_4_port, ramA_address(0) =>
addressA_3_port, ramR_address(7) => addressR_7_port,
ramR_address(6) => addressR_6_port, ramR_address(5)
=> addressR_5_port, ramR_address(4) =>
addressR_4_port, ramR_address(3) => addressR_3_port,
ramR_address(2) => addressR_2_port, ramR_address(1)
=> addressR_1_port, ramR_address(0) =>
addressR_0_port, rom_address(7) => addressH_7_port,
rom_address(6) => addressH_6_port, rom_address(5) =>
addressH_5_port, rom_address(4) => addressH_4_port,
rom_address(3) => addressH_3_port, rom_address(2) =>
addressH_2_port, rom_address(1) => addressH_1_port,
rom_address(0) => addressH_0_port, hold_me =>
hold_me, ramR_readEnable => ramR_read_enable,
ramA_writeEnable => ramA_write_enable,
ramA_readEnable => ramA_read_enable,
ramR_writeEnable => ramR_write_enable, rom_enable =>
romH_enable, counterAddressGen_H_enable =>
CAG_H_enable, counterAddressGen_R_enable =>
CAG_R_enable, counterAddressGen_A_restart =>
CAG_A_restart, counterAddressGen_R_restart =>
CAG_R_restart, counterAddressGen_H_restart =>
CAG_H_restart, mac_clean => clear_register,
reset_fsm => reset_fsm, hold_prev => hold_prev);
counterAddressGenR : counter_address_generator_1 port map( clock => clock,
reset => reset_fsm, need_to_reset => CAG_R_restart,
enable => CAG_R_enable, read_enable =>
ramR_read_enable, address(7) => addressR_7_port,
address(6) => addressR_6_port, address(5) =>
addressR_5_port, address(4) => addressR_4_port,
address(3) => addressR_3_port, address(2) =>
addressR_2_port, address(1) => addressR_1_port,
address(0) => addressR_0_port);
RAMR_UNIT : ramR port map( clock => clock, write_enable => ramR_write_enable
, read_enable => ramR_read_enable, address(2) =>
addressR_2_port, address(1) => addressR_1_port,
address(0) => addressR_0_port, datain(18) =>
Ri_18_port, datain(17) => Ri_17_port, datain(16) =>
Ri_16_port, datain(15) => Ri_15_port, datain(14) =>
Ri_14_port, datain(13) => Ri_13_port, datain(12) =>
Ri_12_port, datain(11) => Ri_11_port, datain(10) =>
Ri_10_port, datain(9) => Ri_9_port, datain(8) =>
Ri_8_port, datain(7) => Ri_7_port, datain(6) =>
Ri_6_port, datain(5) => Ri_5_port, datain(4) =>
Ri_4_port, datain(3) => Ri_3_port, datain(2) =>
Ri_2_port, datain(1) => Ri_1_port, datain(0) =>
Ri_0_port, dataout(18) => data_out(18), dataout(17)
=> data_out(17), dataout(16) => data_out(16),
dataout(15) => data_out(15), dataout(14) =>
data_out(14), dataout(13) => data_out(13),
dataout(12) => data_out(12), dataout(11) =>
data_out(11), dataout(10) => data_out(10),
dataout(9) => data_out(9), dataout(8) => data_out(8)
, dataout(7) => data_out(7), dataout(6) =>
data_out(6), dataout(5) => data_out(5), dataout(4)
=> data_out(4), dataout(3) => data_out(3),
dataout(2) => data_out(2), dataout(1) => data_out(1)
, dataout(0) => data_out(0));
n7 <= '0';
end SYN_project_2;
| mit | d016cce5ba49d35e0cc718009a4d3b7f | 0.478439 | 2.631596 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/opencores/ata/atahost_dma_actrl.vhd | 2 | 17,174 | ---------------------------------------------------------------------
---- ----
---- OpenCores IDE Controller ----
---- DMA (single- and multiword) mode access controller ----
---- ----
---- Author: Richard Herveille ----
---- [email protected] ----
---- www.asics.ws ----
---- ----
---------------------------------------------------------------------
---- ----
---- Copyright (C) 2001, 2002 Richard Herveille ----
---- [email protected] ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
---- ----
---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
---- POSSIBILITY OF SUCH DAMAGE. ----
---- ----
---------------------------------------------------------------------
-- rev.: 1.0 march 9th, 2001. Initial release
--
-- CVS Log
--
-- $Id: atahost_dma_actrl.vhd,v 1.1 2002/02/18 14:32:12 rherveille Exp $
--
-- $Date: 2002/02/18 14:32:12 $
-- $Revision: 1.1 $
-- $Author: rherveille $
-- $Locker: $
-- $State: Exp $
--
-- Change History:
-- $Log: atahost_dma_actrl.vhd,v $
-- Revision 1.1 2002/02/18 14:32:12 rherveille
-- renamed all files to 'atahost_***.vhd'
-- broke-up 'counter.vhd' into 'ud_cnt.vhd' and 'ro_cnt.vhd'
-- changed resD input to generic RESD in ud_cnt.vhd
-- changed ID input to generic ID in ro_cnt.vhd
-- changed core to reflect changes in ro_cnt.vhd
-- removed references to 'count' library
-- changed IO names
-- added disclaimer
-- added CVS log
-- moved registers and wishbone signals into 'atahost_wb_slave.vhd'
--
--
--
-- Host accesses to DMA ports are 32bit wide. Accesses are made by 2 consecutive 16bit accesses to the ATA
-- device's DataPort. The MSB HostData(31:16) is transfered first, then the LSB HostData(15:0) is transfered.
--
---------------------------
-- DMA Access Controller --
---------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
library grlib;
use grlib.stdlib.all;
entity atahost_dma_actrl is
generic(
tech : integer := 0; -- fifo mem technology
fdepth : integer := 8; -- DMA fifo depth
TWIDTH : natural := 8; -- counter width
-- DMA mode 0 settings (@100MHz clock)
DMA_mode0_Tm : natural := 4; -- 50ns
DMA_mode0_Td : natural := 21; -- 215ns
DMA_mode0_Teoc : natural := 21 -- 215ns ==> T0 - Td - Tm = 480 - 50 - 215 = 215
);
port(
clk : in std_logic; -- master clock
nReset : in std_logic; -- asynchronous active low reset
rst : in std_logic; -- synchronous active high reset
IDEctrl_rst : in std_logic; -- IDE control register bit0, 'rst'
sel : in std_logic; -- DMA buffers selected
we : in std_logic; -- write enable input
ack : out std_logic; -- acknowledge output
dev0_Tm,
dev0_Td,
dev0_Teoc : in std_logic_vector(7 downto 0); -- DMA mode timing device 0
dev1_Tm,
dev1_Td,
dev1_Teoc : in std_logic_vector(7 downto 0); -- DMA mode timing device 1
DMActrl_DMAen,
DMActrl_dir,
DMActrl_Bytesw, --Jagre 2006-12-04, byte swap ATA data
DMActrl_BeLeC0,
DMActrl_BeLeC1 : in std_logic; -- control register settings
TxD : in std_logic_vector(31 downto 0); -- DMA transmit data
TxFull : out std_logic; -- DMA transmit buffer full
TxEmpty : out std_logic;
RxQ : out std_logic_vector(31 downto 0); -- DMA receive data
RxEmpty : out std_logic; -- DMA receive buffer empty
RxFull : out std_logic; -- DMA receive buffer full
DMA_req : out std_logic; -- DMA request to external DMA engine
DMA_ack : in std_logic; -- DMA acknowledge from external DMA engine
DMARQ : in std_logic; -- ATA devices request DMA transfer
SelDev : in std_logic; -- Selected device
Go : in std_logic; -- Start transfer sequence
Done : out std_logic; -- Transfer sequence done
DDi : in std_logic_vector(15 downto 0); -- Data from ATA DD bus
DDo : out std_logic_vector(15 downto 0); -- Data towards ATA DD bus
DIOR,
DIOW : out std_logic
);
end entity atahost_dma_actrl;
architecture structural of atahost_dma_actrl is
--
-- component declarations
--
component atahost_dma_tctrl is
generic(
TWIDTH : natural := 8; -- counter width
-- DMA mode 0 settings (@100MHz clock)
DMA_mode0_Tm : natural := 6; -- 70ns
DMA_mode0_Td : natural := 28; -- 290ns
DMA_mode0_Teoc : natural := 23 -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240
);
port(
clk : in std_logic; -- master clock
nReset : in std_logic; -- asynchronous active low reset
rst : in std_logic; -- synchronous active high reset
-- timing register settings
Tm : in std_logic_vector(TWIDTH -1 downto 0); -- Tm time (in clk-ticks)
Td : in std_logic_vector(TWIDTH -1 downto 0); -- Td time (in clk-ticks)
Teoc : in std_logic_vector(TWIDTH -1 downto 0); -- end of cycle time
-- control signals
go : in std_logic; -- DMA controller selected (strobe signal)
we : in std_logic; -- DMA direction '1' = write, '0' = read
-- return signals
done : out std_logic; -- finished cycle
dstrb : out std_logic; -- data strobe
-- ATA signals
DIOR, -- IOread signal, active high
DIOW : out std_logic -- IOwrite signal, active high
);
end component atahost_dma_tctrl;
component atahost_reg_buf is
generic (
WIDTH : natural := 8
);
port(
clk : in std_logic;
nReset : in std_logic;
rst : in std_logic;
D : in std_logic_vector(WIDTH -1 downto 0);
Q : out std_logic_vector(WIDTH -1 downto 0);
rd : in std_logic;
wr : in std_logic;
valid : out std_logic
);
end component atahost_reg_buf;
component atahost_dma_fifo is
generic(tech : integer:=0;
abits : integer:=3;
dbits : integer:=32;
depth : integer:=8);
port( clk : in std_logic;
reset : in std_logic;
write_enable : in std_logic;
read_enable : in std_logic;
data_in : in std_logic_vector(dbits-1 downto 0);
data_out : out std_logic_vector(dbits-1 downto 0);
write_error : out std_logic:='0';
read_error : out std_logic:='0';
level : out natural range 0 to depth;
empty : out std_logic:='1';
full : out std_logic:='0'
);
end component atahost_dma_fifo;
signal Tdone, Tfw : std_logic;
signal RxWr, TxRd : std_logic;
signal assync_TxRd, s_TxFull : std_logic; -----------------------Erik Jagre 2006-10-27
signal dstrb, rd_dstrb, wr_dstrb : std_logic;
signal TxbufQ, RxbufD : std_logic_vector(31 downto 0);
signal iRxEmpty : std_logic;
constant abits : integer := Log2(fdepth);
begin
-- note: *fw = *first_word, *lw = *last_word
--
-- generate DDi/DDo controls
--
gen_DMA_sigs: block
signal writeDfw, writeDlw : std_logic_vector(15 downto 0);
signal readDfw, readDlw : std_logic_vector(15 downto 0);
signal BeLeC : std_logic; -- BigEndian <-> LittleEndian conversion
begin
-- generate byte_swap signal
BeLeC <= (not SelDev and DMActrl_BeLeC0) or (SelDev and DMActrl_BeLeC1);
-- generate Tfw (Transfering first word)
gen_Tfw: process(clk, nReset)
begin
if (nReset = '0') then
Tfw <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1') then
Tfw <= '0';
else
Tfw <= go or (Tfw and not Tdone);
end if;
end if;
end process gen_Tfw;
-- transmit data part
gen_writed_pipe:process(clk)
begin
if (clk'event and clk = '1') then
if (TxRd = '1') then -- reload registers
if (BeLeC = '1') then -- Do big<->little endian conversion
writeDfw(15 downto 8) <= TxbufQ( 7 downto 0); -- TxbufQ = data from transmit buffer
writeDfw( 7 downto 0) <= TxbufQ(15 downto 8);
writeDlw(15 downto 8) <= TxbufQ(23 downto 16);
writeDlw( 7 downto 0) <= TxbufQ(31 downto 24);
else -- don't do big<->little endian conversion
writeDfw <= TxbufQ(31 downto 16);
writeDlw <= TxbufQ(15 downto 0);
end if;
elsif (wr_dstrb = '1') then -- next word to transfer
writeDfw <= writeDlw;
end if;
end if;
end process gen_writed_pipe;
--Jagre 2006-12-04
--swap byte orderD when MActrl_Bytesw is set to '1'
DDo(15 downto 8) <= writeDfw(15 downto 8) when DMActrl_Bytesw='0' else
writeDfw(7 downto 0);
DDo(7 downto 0) <= writeDfw(7 downto 0) when DMActrl_Bytesw='0' else
writeDfw(15 downto 8);
--DDo <= writeDfw; -- assign DMA data out
-- generate transmit register read request
gen_Tx_rreq: process(clk, nReset)
begin
if (nReset = '0') then
TxRd <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1') then
TxRd <= '0';
else
TxRd <= go and DMActrl_dir;
end if;
end if;
end process gen_Tx_rreq;
assync_TxRd <= go and DMActrl_dir; --Jagre 2006-12-14
-- receive
gen_readd_pipe:process(clk)
begin
if (clk'event and clk = '1') then
if (rd_dstrb = '1') then
readDfw <= readDlw; -- shift previous read word to msb
if (BeLeC = '1' xor DMActrl_Bytesw = '1') then -- swap bytes, DMActrl_Bytesw added 2006-12-04, Jagre
readDlw(15 downto 8) <= DDi( 7 downto 0);
readDlw( 7 downto 0) <= DDi(15 downto 8);
else -- don't swap bytes
readDlw <= DDi;
end if;
end if;
end if;
end process gen_readd_pipe;
-- RxD = data to receive buffer
RxbufD <= (readDfw & readDlw) when (BeLeC = '0') else (readDlw & readDfw);
-- generate receive register write request
gen_Rx_wreq: process(clk, nReset)
begin
if (nReset = '0') then
RxWr <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1') then
RxWr <= '0';
else
RxWr <= not Tfw and rd_dstrb;
end if;
end if;
end process gen_Rx_wreq;
end block gen_DMA_sigs;
--
-- Hookup DMA read / write buffers
--
gen_DMAbuf: block
signal DMArst : std_logic;
signal RxRd, TxWr : std_logic;
begin
-- generate DMA reset signal
DMArst <= rst or IDEctrl_rst;
Txfifo: atahost_dma_fifo
generic map(dbits=>32,depth=>fdepth,tech=>tech,abits=>abits)
port map( clk => clk,
reset => DMArst,
write_enable => TxWr,
read_enable => assync_TxRd,
data_in => TxD,
data_out => TxbufQ,
write_error => open,
read_error => open,
level => open,
empty => TxEmpty,
full => s_TxFull
);
Rxfifo: atahost_dma_fifo
generic map(dbits=>32,depth=>fdepth,tech=>tech,abits=>abits)
port map( clk => clk,
reset => DMArst,
write_enable => RxWr,
read_enable => RxRd,
data_in => RxbufD,
data_out => RxQ,
write_error => open,
read_error => open,
level => open,
empty => iRxEmpty,
full => RxFull
);
RxEmpty <= iRxEmpty; -- avoid 'cannot associate OUT port with BUFFER port' error
--
-- generate DMA buffer access signals
--
RxRd <= sel and not we and not iRxEmpty;
TxWr <= sel and we and not s_TxFull;
ack <= RxRd or TxWr; -- DMA buffer access acknowledge
end block gen_DMAbuf;
--
-- generate request signal for external DMA engine
--
gen_DMA_req: block
signal hgo : std_logic;
signal iDMA_req : std_logic;
signal request : std_logic;
begin
-- generate hold-go
gen_hgo : process(clk, nReset)
begin
if (nReset = '0') then
hgo <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1') then
hgo <= '0';
else
hgo <= go or (hgo and not (wr_dstrb and not Tfw) and DMActrl_dir);
end if;
end if;
end process gen_hgo;
request <= (DMActrl_dir and DMARQ and not s_TxFull and not hgo) or not iRxEmpty;
process(clk, nReset)
begin
if (nReset = '0') then
iDMA_req <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1') then
iDMA_req <= '0';
else
iDMA_req <= DMActrl_DMAen and not DMA_ack and (request or iDMA_req);
-- DMA_req <= (DMActrl_DMAen and DMActrl_dir and DMARQ and not TxFull and not hgo) or not iRxEmpty;
end if;
end if;
end process;
DMA_req <= iDMA_req;
end block gen_DMA_req;
--
-- DMA timing controller
--
DMA_timing_ctrl: block
signal Tm, Td, Teoc, Tdmack_ext : std_logic_vector(TWIDTH -1 downto 0);
signal dTfw, igo : std_logic;
begin
--
-- generate internal GO signal
--
gen_igo : process(clk, nReset)
begin
if (nReset = '0') then
igo <= '0';
dTfw <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1') then
igo <= '0';
dTfw <= '0';
else
igo <= go or (not Tfw and dTfw);
dTfw <= Tfw;
end if;
end if;
end process gen_igo;
--
-- select timing settings for the addressed device
--
sel_dev_t: process(clk)
begin
if (clk'event and clk = '1') then
if (SelDev = '1') then -- device1 selected
Tm <= dev1_Tm;
Td <= dev1_Td;
Teoc <= dev1_Teoc;
else -- device0 selected
Tm <= dev0_Tm;
Td <= dev0_Td;
Teoc <= dev0_Teoc;
end if;
end if;
end process sel_dev_t;
--
-- hookup timing controller
--
DMA_timing_ctrl: atahost_dma_tctrl
generic map (
TWIDTH => TWIDTH,
DMA_mode0_Tm => DMA_mode0_Tm,
DMA_mode0_Td => DMA_mode0_Td,
DMA_mode0_Teoc => DMA_mode0_Teoc
)
port map (
clk => clk,
nReset => nReset,
rst => rst,
Tm => Tm,
Td => Td,
Teoc => Teoc,
go => igo,
we => DMActrl_dir,
done => Tdone,
dstrb => dstrb,
DIOR => dior,
DIOW => diow
);
done <= Tdone and not Tfw; -- done transfering last word
rd_dstrb <= dstrb and not DMActrl_dir; -- read data strobe
wr_dstrb <= dstrb and DMActrl_dir; -- write data strobe
TxFull <= s_TxFull;
end block DMA_timing_ctrl;
end architecture structural;
| mit | 44709ddc31fe172ec6df75889deed133 | 0.508618 | 3.638559 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/misc/ahbdma.vhd | 2 | 5,521 | -- GAISLER_LICENSE
-----------------------------------------------------------------------------
-- Entity: dma
-- File: dma.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Simple DMA (needs the AHB master interface)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.misc.all;
entity ahbdma is
generic (
hindex : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
dbuf : integer := 4);
port (
rst : in std_logic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type
);
end;
architecture struct of ahbdma is
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBDMA, 0, 0, pirq),
1 => apb_iobar(paddr, pmask));
type dma_state_type is (readc, writec);
subtype word32 is std_logic_vector(31 downto 0);
type datavec is array (0 to dbuf-1) of word32;
type reg_type is record
srcaddr : std_logic_vector(31 downto 0);
srcinc : std_logic_vector(1 downto 0);
dstaddr : std_logic_vector(31 downto 0);
dstinc : std_logic_vector(1 downto 0);
len : std_logic_vector(15 downto 0);
enable : std_logic;
write : std_logic;
inhibit : std_logic;
status : std_logic_vector(1 downto 0);
dstate : dma_state_type;
data : datavec;
cnt : integer range 0 to dbuf-1;
end record;
signal r, rin : reg_type;
signal dmai : ahb_dma_in_type;
signal dmao : ahb_dma_out_type;
begin
comb : process(apbi, dmao, rst, r)
variable v : reg_type;
variable regd : std_logic_vector(31 downto 0); -- data from registers
variable start : std_logic;
variable burst : std_logic;
variable write : std_logic;
variable ready : std_logic;
variable retry : std_logic;
variable mexc : std_logic;
variable irq : std_logic;
variable address : std_logic_vector(31 downto 0); -- DMA address
variable size : std_logic_vector( 1 downto 0); -- DMA transfer size
variable newlen : std_logic_vector(15 downto 0);
variable oldaddr : std_logic_vector(9 downto 0);
variable newaddr : std_logic_vector(9 downto 0);
variable oldsize : std_logic_vector( 1 downto 0);
variable ainc : std_logic_vector( 3 downto 0);
begin
v := r; regd := (others => '0'); burst := '0'; start := '0';
write := '0'; ready := '0'; mexc := '0';
size := r.srcinc; irq := '0'; v.inhibit := '0';
if r.write = '0' then address := r.srcaddr;
else address := r.dstaddr; end if;
newlen := r.len - 1;
if (r.cnt < dbuf-1) or (r.len(9 downto 2) = "11111111") then burst := '1';
else burst := '0'; end if;
start := r.enable;
if dmao.active = '1' then
if r.write = '0' then
if dmao.ready = '1' then
v.data(r.cnt) := dmao.rdata;
if r.cnt = dbuf-1 then
v.write := '1'; v.cnt := 0; v.inhibit := '1';
address := r.dstaddr; size := r.dstinc;
else v.cnt := r.cnt + 1; end if;
end if;
else
if r.cnt = dbuf-1 then start := '0'; end if;
if dmao.ready = '1' then
if r.cnt = dbuf-1 then v.cnt := 0;
v.write := '0'; v.len := newlen; v.enable := start; irq := start;
else v.cnt := r.cnt + 1; end if;
end if;
end if;
end if;
if r.write = '0' then oldaddr := r.srcaddr(9 downto 0); oldsize := r.srcinc;
else oldaddr := r.dstaddr(9 downto 0); oldsize := r.dstinc; end if;
ainc := decode(oldsize);
newaddr := oldaddr + ainc(3 downto 0);
if (dmao.active and dmao.ready) = '1' then
if r.write = '0' then v.srcaddr(9 downto 0) := newaddr;
else v.dstaddr(9 downto 0) := newaddr; end if;
end if;
-- read DMA registers
case apbi.paddr(3 downto 2) is
when "00" => regd := r.srcaddr;
when "01" => regd := r.dstaddr;
when "10" => regd(20 downto 0) := r.enable & r.srcinc & r.dstinc & r.len;
when others => null;
end case;
-- write DMA registers
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(3 downto 2) is
when "00" =>
v.srcaddr := apbi.pwdata;
when "01" =>
v.dstaddr := apbi.pwdata;
when "10" =>
v.len := apbi.pwdata(15 downto 0);
v.srcinc := apbi.pwdata(17 downto 16);
v.dstinc := apbi.pwdata(19 downto 18);
v.enable := apbi.pwdata(20);
when others => null;
end case;
end if;
if rst = '0' then
v.dstate := readc; v.enable := '0'; v.write := '0';
v.cnt := 0;
end if;
rin <= v;
apbo.prdata <= regd;
dmai.address <= address;
dmai.wdata <= r.data(r.cnt);
dmai.start <= start and not v.inhibit;
dmai.burst <= burst;
dmai.write <= v.write;
dmai.size <= size;
apbo.pirq <= (others =>'0');
apbo.pindex <= pindex;
apbo.pconfig <= pconfig;
end process;
ahbif : ahbmst generic map (hindex => hindex, devid => 16#26#, incaddr => 1)
port map (rst, clk, dmai, dmao, ahbi, ahbo);
regs : process(clk)
begin if rising_edge(clk) then r <= rin; end if; end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbdma" & tost(pindex) &
": AHB DMA Unit rev " & tost(0) & ", irq " & tost(pirq));
-- pragma translate_on
end;
| mit | c1f7ba93333f7207d320ca2d1a5c508b | 0.571636 | 3.223001 | false | false | false | false |
amerc/phimii | source/seven_seg.vhd | 3 | 3,135 | --
-- Copyright (C) 2009-2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity seven_seg is
generic (
-- This can be overridden to change the refresh rate. The anode pattern will change at a
-- frequency given by F(clk_in) / (2**COUNTER_WIDTH). So for a 50MHz clk_in and
-- COUNTER_WIDTH=18, the anode pattern changes at ~191Hz, which means each digit gets
-- refreshed at ~48Hz.
COUNTER_WIDTH : integer := 18
);
port(
clk_in : in std_logic;
data_in : in std_logic_vector(15 downto 0);
dots_in : in std_logic_vector(3 downto 0);
segs_out : out std_logic_vector(7 downto 0);
anodes_out : out std_logic_vector(3 downto 0)
);
end seven_seg;
architecture behavioural of seven_seg is
signal count : unsigned(COUNTER_WIDTH-1 downto 0) := (others => '0');
signal count_next : unsigned(COUNTER_WIDTH-1 downto 0);
signal anodeSelect : std_logic_vector(1 downto 0);
signal nibble : std_logic_vector(3 downto 0);
signal segs : std_logic_vector(6 downto 0);
signal dot : std_logic;
begin
-- Infer counter register
process(clk_in)
begin
if ( rising_edge(clk_in) ) then
count <= count_next;
end if;
end process;
-- Increment counter and derive anode select from top two bits
count_next <= count + 1;
anodeSelect <= std_logic_vector(count(COUNTER_WIDTH-1 downto COUNTER_WIDTH-2));
-- Drive anodes
with anodeSelect select anodes_out <=
"0111" when "00",
"1011" when "01",
"1101" when "10",
"1110" when others;
-- Select the appropriate bit from dots_in
with anodeSelect select dot <=
not(dots_in(3)) when "00",
not(dots_in(2)) when "01",
not(dots_in(1)) when "10",
not(dots_in(0)) when others;
-- Choose a nibble to display
with anodeSelect select nibble <=
data_in(15 downto 12) when "00",
data_in(11 downto 8) when "01",
data_in(7 downto 4) when "10",
data_in(3 downto 0) when others;
-- Decode chosen nibble
with nibble select segs <=
"1000000" when "0000",
"1111001" when "0001",
"0100100" when "0010",
"0110000" when "0011",
"0011001" when "0100",
"0010010" when "0101",
"0000010" when "0110",
"1111000" when "0111",
"0000000" when "1000",
"0010000" when "1001",
"0001000" when "1010",
"0000011" when "1011",
"1000110" when "1100",
"0100001" when "1101",
"0000110" when "1110",
"0001110" when others;
-- Drive segs_out
segs_out <= dot & segs;
end behavioural;
| mit | e4dd14964693244fce539a602f951a24 | 0.67815 | 3.169869 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Defense/iu33AttacksDCE.vhd | 1 | 122,404 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008, 2009, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: iu3
-- File: iu3.vhd
-- Author: Jiri Gaisler, Edvin Catovic, Gaisler Research
-- Description: LEON3 7-stage integer pipline
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.sparc.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.leon3.all;
use gaisler.libiu.all;
use gaisler.arith.all;
-- pragma translate_off
use grlib.sparc_disas.all;
-- pragma translate_on
entity iu3 is
generic (
nwin : integer range 2 to 32 := 8;
isets : integer range 1 to 4 := 2;
dsets : integer range 1 to 4 := 2;
fpu : integer range 0 to 15 := 0;
v8 : integer range 0 to 63 := 2;
cp, mac : integer range 0 to 1 := 0;
dsu : integer range 0 to 1 := 1;
nwp : integer range 0 to 4 := 2;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
index : integer range 0 to 15:= 0;
lddel : integer range 1 to 2 := 1;
irfwt : integer range 0 to 1 := 0;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 2; -- trace buf size in kB (0 - no trace buffer)
pwd : integer range 0 to 2 := 0; -- power-down
svt : integer range 0 to 1 := 0; -- single-vector trapping
rstaddr : integer := 16#00000#; -- reset vector MSB address
smp : integer range 0 to 15 := 0; -- support SMP systems
fabtech : integer range 0 to NTECH := 20;
clk2x : integer := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
holdn : in std_ulogic;
ici : buffer icache_in_type;
ico : in icache_out_type;
dci : buffer dcache_in_type;
dco : in dcache_out_type;
rfi : buffer iregfile_in_type;
rfo : in iregfile_out_type;
irqi : in l3_irq_in_type;
irqo : buffer l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : buffer l3_debug_out_type;
muli : buffer mul32_in_type;
mulo : in mul32_out_type;
divi : buffer div32_in_type;
divo : in div32_out_type;
fpo : in fpc_out_type;
fpi : buffer fpc_in_type;
cpo : in fpc_out_type;
cpi : buffer fpc_in_type;
tbo : in tracebuf_out_type;
tbi : buffer tracebuf_in_type;
sclk : in std_ulogic
);
end;
architecture rtl of iu3 is
constant ISETMSB : integer := 0;
constant DSETMSB : integer := 0;
constant RFBITS : integer range 6 to 10 := 8;
constant NWINLOG2 : integer range 1 to 5 := 3;
constant CWPOPT : boolean := true;
constant CWPMIN : std_logic_vector(2 downto 0) := "000";
constant CWPMAX : std_logic_vector(2 downto 0) := "111";
constant FPEN : boolean := (fpu /= 0);
constant CPEN : boolean := false;
constant MULEN : boolean := true;
constant MULTYPE: integer := 0;
constant DIVEN : boolean := true;
constant MACEN : boolean := false;
constant MACPIPE: boolean := false;
constant IMPL : integer := 15;
constant VER : integer := 3;
constant DBGUNIT : boolean := true;
constant TRACEBUF : boolean := true;
constant TBUFBITS : integer := 7;
constant PWRD1 : boolean := false; --(pwd = 1) and not (index /= 0);
constant PWRD2 : boolean := false; --(pwd = 2) or (index /= 0);
constant RS1OPT : boolean := true;
constant DYNRST : boolean := false;
subtype word is std_logic_vector(31 downto 0);
subtype pctype is std_logic_vector(31 downto 2);
subtype rfatype is std_logic_vector(8-1 downto 0);
subtype cwptype is std_logic_vector(3-1 downto 0);
type icdtype is array (0 to 2-1) of word;
type dcdtype is array (0 to 2-1) of word;
type dc_in_type is record
signed, enaddr, read, write, lock , dsuen : std_ulogic;
size : std_logic_vector(1 downto 0);
asi : std_logic_vector(7 downto 0);
end record;
type pipeline_ctrl_type is record
pc : pctype;
inst : word;
cnt : std_logic_vector(1 downto 0);
rd : rfatype;
tt : std_logic_vector(5 downto 0);
trap : std_ulogic;
annul : std_ulogic;
wreg : std_ulogic;
wicc : std_ulogic;
wy : std_ulogic;
ld : std_ulogic;
pv : std_ulogic;
rett : std_ulogic;
end record;
type fetch_reg_type is record
pc : pctype;
branch : std_ulogic;
end record;
type decode_reg_type is record
pc : pctype;
inst : icdtype;
cwp : cwptype;
set : std_logic_vector(0 downto 0);
mexc : std_ulogic;
cnt : std_logic_vector(1 downto 0);
pv : std_ulogic;
annul : std_ulogic;
inull : std_ulogic;
step : std_ulogic;
end record;
type regacc_reg_type is record
ctrl : pipeline_ctrl_type;
rs1 : std_logic_vector(4 downto 0);
rfa1, rfa2 : rfatype;
rsel1, rsel2 : std_logic_vector(2 downto 0);
rfe1, rfe2 : std_ulogic;
cwp : cwptype;
imm : word;
ldcheck1 : std_ulogic;
ldcheck2 : std_ulogic;
ldchkra : std_ulogic;
ldchkex : std_ulogic;
su : std_ulogic;
et : std_ulogic;
wovf : std_ulogic;
wunf : std_ulogic;
ticc : std_ulogic;
jmpl : std_ulogic;
step : std_ulogic;
mulstart : std_ulogic;
divstart : std_ulogic;
end record;
type execute_reg_type is record
ctrl : pipeline_ctrl_type;
op1 : word;
op2 : word;
aluop : std_logic_vector(2 downto 0); -- Alu operation
alusel : std_logic_vector(1 downto 0); -- Alu result select
aluadd : std_ulogic;
alucin : std_ulogic;
ldbp1, ldbp2 : std_ulogic;
invop2 : std_ulogic;
shcnt : std_logic_vector(4 downto 0); -- shift count
sari : std_ulogic; -- shift msb
shleft : std_ulogic; -- shift left/right
ymsb : std_ulogic; -- shift left/right
rd : std_logic_vector(4 downto 0);
jmpl : std_ulogic;
su : std_ulogic;
et : std_ulogic;
cwp : cwptype;
icc : std_logic_vector(3 downto 0);
mulstep: std_ulogic;
mul : std_ulogic;
mac : std_ulogic;
end record;
type memory_reg_type is record
ctrl : pipeline_ctrl_type;
result : word;
y : word;
icc : std_logic_vector(3 downto 0);
nalign : std_ulogic;
dci : dc_in_type;
werr : std_ulogic;
wcwp : std_ulogic;
irqen : std_ulogic;
irqen2 : std_ulogic;
mac : std_ulogic;
divz : std_ulogic;
su : std_ulogic;
mul : std_ulogic;
end record;
type exception_state is (run, trap, dsu1, dsu2);
type exception_reg_type is record
ctrl : pipeline_ctrl_type;
result : word;
y : word;
icc : std_logic_vector( 3 downto 0);
annul_all : std_ulogic;
data : dcdtype;
set : std_logic_vector(0 downto 0);
mexc : std_ulogic;
dci : dc_in_type;
laddr : std_logic_vector(1 downto 0);
rstate : exception_state;
npc : std_logic_vector(2 downto 0);
intack : std_ulogic;
ipend : std_ulogic;
mac : std_ulogic;
debug : std_ulogic;
nerror : std_ulogic;
end record;
type dsu_registers is record
tt : std_logic_vector(7 downto 0);
err : std_ulogic;
tbufcnt : std_logic_vector(7-1 downto 0);
asi : std_logic_vector(7 downto 0);
crdy : std_logic_vector(2 downto 1); -- diag cache access ready
end record;
type irestart_register is record
addr : pctype;
pwd : std_ulogic;
end record;
type pwd_register_type is record
pwd : std_ulogic;
error : std_ulogic;
end record;
type special_register_type is record
cwp : cwptype; -- current window pointer
icc : std_logic_vector(3 downto 0); -- integer condition codes
tt : std_logic_vector(7 downto 0); -- trap type
tba : std_logic_vector(19 downto 0); -- trap base address
wim : std_logic_vector(8-1 downto 0); -- window invalid mask
pil : std_logic_vector(3 downto 0); -- processor interrupt level
ec : std_ulogic; -- enable CP
ef : std_ulogic; -- enable FP
ps : std_ulogic; -- previous supervisor flag
s : std_ulogic; -- supervisor flag
et : std_ulogic; -- enable traps
y : word;
asr18 : word;
svt : std_ulogic; -- enable traps
dwt : std_ulogic; -- disable write error trap
end record;
type write_reg_type is record
s : special_register_type;
result : word;
wa : rfatype;
wreg : std_ulogic;
except : std_ulogic;
end record;
type registers is record
f : fetch_reg_type;
d : decode_reg_type;
a : regacc_reg_type;
e : execute_reg_type;
m : memory_reg_type;
x : exception_reg_type;
w : write_reg_type;
end record;
type exception_type is record
pri : std_ulogic;
ill : std_ulogic;
fpdis : std_ulogic;
cpdis : std_ulogic;
wovf : std_ulogic;
wunf : std_ulogic;
ticc : std_ulogic;
end record;
type watchpoint_register is record
addr : std_logic_vector(31 downto 2); -- watchpoint address
mask : std_logic_vector(31 downto 2); -- watchpoint mask
exec : std_ulogic; -- trap on instruction
load : std_ulogic; -- trap on load
store : std_ulogic; -- trap on store
end record;
type watchpoint_registers is array (0 to 3) of watchpoint_register;
constant wpr_none : watchpoint_register := (
"000000000000000000000000000000", "000000000000000000000000000000", '0', '0', '0');
function dbgexc(r : registers; dbgi : l3_debug_in_type; trap : std_ulogic; tt : std_logic_vector(7 downto 0)) return std_ulogic is
variable dmode : std_ulogic;
begin
dmode := '0';
if (not r.x.ctrl.annul and trap) = '1' then
if (((tt = "00" & TT_WATCH) and (dbgi.bwatch = '1')) or
((dbgi.bsoft = '1') and (tt = "10000001")) or
(dbgi.btrapa = '1') or
((dbgi.btrape = '1') and not ((tt(5 downto 0) = TT_PRIV) or
(tt(5 downto 0) = TT_FPDIS) or (tt(5 downto 0) = TT_WINOF) or
(tt(5 downto 0) = TT_WINUF) or (tt(5 downto 4) = "01") or (tt(7) = '1'))) or
(((not r.w.s.et) and dbgi.berror) = '1')) then
dmode := '1';
end if;
end if;
return(dmode);
end;
function dbgerr(r : registers; dbgi : l3_debug_in_type;
tt : std_logic_vector(7 downto 0))
return std_ulogic is
variable err : std_ulogic;
begin
err := not r.w.s.et;
if (((dbgi.dbreak = '1') and (tt = ("00" & TT_WATCH))) or
((dbgi.bsoft = '1') and (tt = ("10000001")))) then
err := '0';
end if;
return(err);
end;
procedure diagwr(r : in registers;
dsur : in dsu_registers;
ir : in irestart_register;
dbg : in l3_debug_in_type;
wpr : in watchpoint_registers;
s : out special_register_type;
vwpr : out watchpoint_registers;
asi : out std_logic_vector(7 downto 0);
pc, npc : out pctype;
tbufcnt : out std_logic_vector(7-1 downto 0);
wr : out std_ulogic;
addr : out std_logic_vector(9 downto 0);
data : out word;
fpcwr : out std_ulogic) is
variable i : integer range 0 to 3;
begin
s := r.w.s; pc := r.f.pc; npc := ir.addr; wr := '0';
vwpr := wpr; asi := dsur.asi; addr := "0000000000";
data := dbg.ddata;
tbufcnt := dsur.tbufcnt; fpcwr := '0';
if (dbg.dsuen and dbg.denable and dbg.dwrite) = '1' then
case dbg.daddr(23 downto 20) is
when "0001" =>
if (dbg.daddr(16) = '1') and true then -- trace buffer control reg
tbufcnt := dbg.ddata(7-1 downto 0);
end if;
when "0011" => -- IU reg file
if dbg.daddr(12) = '0' then
wr := '1';
addr := "0000000000";
addr(8-1 downto 0) := dbg.daddr(8+1 downto 2);
else -- FPC
fpcwr := '1';
end if;
when "0100" => -- IU special registers
case dbg.daddr(7 downto 6) is
when "00" => -- IU regs Y - TBUF ctrl reg
case dbg.daddr(5 downto 2) is
when "0000" => -- Y
s.y := dbg.ddata;
when "0001" => -- PSR
s.cwp := dbg.ddata(3-1 downto 0);
s.icc := dbg.ddata(23 downto 20);
s.ec := dbg.ddata(13);
if FPEN then s.ef := dbg.ddata(12); end if;
s.pil := dbg.ddata(11 downto 8);
s.s := dbg.ddata(7);
s.ps := dbg.ddata(6);
s.et := dbg.ddata(5);
when "0010" => -- WIM
s.wim := dbg.ddata(8-1 downto 0);
when "0011" => -- TBR
s.tba := dbg.ddata(31 downto 12);
s.tt := dbg.ddata(11 downto 4);
when "0100" => -- PC
pc := dbg.ddata(31 downto 2);
when "0101" => -- NPC
npc := dbg.ddata(31 downto 2);
when "0110" => --FSR
fpcwr := '1';
when "0111" => --CFSR
when "1001" => -- ASI reg
asi := dbg.ddata(7 downto 0);
--when "1001" => -- TBUF ctrl reg
-- tbufcnt := dbg.ddata(7-1 downto 0);
when others =>
end case;
when "01" => -- ASR16 - ASR31
case dbg.daddr(5 downto 2) is
when "0001" => -- %ASR17
s.dwt := dbg.ddata(14);
s.svt := dbg.ddata(13);
when "0010" => -- %ASR18
if false then s.asr18 := dbg.ddata; end if;
when "1000" => -- %ASR24 - %ASR31
vwpr(0).addr := dbg.ddata(31 downto 2);
vwpr(0).exec := dbg.ddata(0);
when "1001" =>
vwpr(0).mask := dbg.ddata(31 downto 2);
vwpr(0).load := dbg.ddata(1);
vwpr(0).store := dbg.ddata(0);
when "1010" =>
vwpr(1).addr := dbg.ddata(31 downto 2);
vwpr(1).exec := dbg.ddata(0);
when "1011" =>
vwpr(1).mask := dbg.ddata(31 downto 2);
vwpr(1).load := dbg.ddata(1);
vwpr(1).store := dbg.ddata(0);
when "1100" =>
vwpr(2).addr := dbg.ddata(31 downto 2);
vwpr(2).exec := dbg.ddata(0);
when "1101" =>
vwpr(2).mask := dbg.ddata(31 downto 2);
vwpr(2).load := dbg.ddata(1);
vwpr(2).store := dbg.ddata(0);
when "1110" =>
vwpr(3).addr := dbg.ddata(31 downto 2);
vwpr(3).exec := dbg.ddata(0);
when "1111" => --
vwpr(3).mask := dbg.ddata(31 downto 2);
vwpr(3).load := dbg.ddata(1);
vwpr(3).store := dbg.ddata(0);
when others => --
end case;
-- disabled due to bug in XST
-- i := conv_integer(dbg.daddr(4 downto 3));
-- if dbg.daddr(2) = '0' then
-- vwpr(i).addr := dbg.ddata(31 downto 2);
-- vwpr(i).exec := dbg.ddata(0);
-- else
-- vwpr(i).mask := dbg.ddata(31 downto 2);
-- vwpr(i).load := dbg.ddata(1);
-- vwpr(i).store := dbg.ddata(0);
-- end if;
when others =>
end case;
when others =>
end case;
end if;
end;
function asr17_gen ( r : in registers) return word is
variable asr17 : word;
variable fpu2 : integer range 0 to 3;
begin
asr17 := "00000000000000000000000000000000";
asr17(31 downto 28) := conv_std_logic_vector(index, 4);
if (clk2x > 8) then
asr17(16 downto 15) := conv_std_logic_vector(clk2x-8, 2);
asr17(17) := '1';
elsif (clk2x > 0) then
asr17(16 downto 15) := conv_std_logic_vector(clk2x, 2);
end if;
asr17(14) := r.w.s.dwt;
if svt = 1 then asr17(13) := r.w.s.svt; end if;
if lddel = 2 then asr17(12) := '1'; end if;
if (fpu > 0) and (fpu < 8) then fpu2 := 1;
elsif (fpu >= 8) and (fpu < 15) then fpu2 := 3;
elsif fpu = 15 then fpu2 := 2;
else fpu2 := 0; end if;
asr17(11 downto 10) := conv_std_logic_vector(fpu2, 2);
if mac = 1 then asr17(9) := '1'; end if;
if 2 /= 0 then asr17(8) := '1'; end if;
asr17(7 downto 5) := conv_std_logic_vector(nwp, 3);
asr17(4 downto 0) := conv_std_logic_vector(8-1, 5);
return(asr17);
end;
procedure diagread(dbgi : in l3_debug_in_type;
r : in registers;
dsur : in dsu_registers;
ir : in irestart_register;
wpr : in watchpoint_registers;
dco : in dcache_out_type;
tbufo : in tracebuf_out_type;
data : out word) is
variable cwp : std_logic_vector(4 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable i : integer range 0 to 3;
begin
data := "00000000000000000000000000000000"; cwp := "00000";
cwp(3-1 downto 0) := r.w.s.cwp;
case dbgi.daddr(22 downto 20) is
when "001" => -- trace buffer
if true then
if dbgi.daddr(16) = '1' then -- trace buffer control reg
if true then data(7-1 downto 0) := dsur.tbufcnt; end if;
else
case dbgi.daddr(3 downto 2) is
when "00" => data := tbufo.data(127 downto 96);
when "01" => data := tbufo.data(95 downto 64);
when "10" => data := tbufo.data(63 downto 32);
when others => data := tbufo.data(31 downto 0);
end case;
end if;
end if;
when "011" => -- IU reg file
if dbgi.daddr(12) = '0' then
data := rfo.data1(31 downto 0);
if (dbgi.daddr(11) = '1') and (is_fpga(fabtech) = 0) then
data := rfo.data2(31 downto 0);
end if;
else data := fpo.dbg.data; end if;
when "100" => -- IU regs
case dbgi.daddr(7 downto 6) is
when "00" => -- IU regs Y - TBUF ctrl reg
case dbgi.daddr(5 downto 2) is
when "0000" =>
data := r.w.s.y;
when "0001" =>
data := conv_std_logic_vector(15, 4) & conv_std_logic_vector(3, 4) &
r.w.s.icc & "000000" & r.w.s.ec & r.w.s.ef & r.w.s.pil &
r.w.s.s & r.w.s.ps & r.w.s.et & cwp;
when "0010" =>
data(8-1 downto 0) := r.w.s.wim;
when "0011" =>
data := r.w.s.tba & r.w.s.tt & "0000";
when "0100" =>
data(31 downto 2) := r.f.pc;
when "0101" =>
data(31 downto 2) := ir.addr;
when "0110" => -- FSR
data := fpo.dbg.data;
when "0111" => -- CPSR
when "1000" => -- TT reg
data(12 downto 4) := dsur.err & dsur.tt;
when "1001" => -- ASI reg
data(7 downto 0) := dsur.asi;
when others =>
end case;
when "01" =>
if dbgi.daddr(5) = '0' then -- %ASR17
if dbgi.daddr(4 downto 2) = "001" then -- %ASR17
data := asr17_gen(r);
elsif false and dbgi.daddr(4 downto 2) = "010" then -- %ASR18
data := r.w.s.asr18;
end if;
else -- %ASR24 - %ASR31
i := conv_integer(dbgi.daddr(4 downto 3)); --
if dbgi.daddr(2) = '0' then
data(31 downto 2) := wpr(i).addr;
data(0) := wpr(i).exec;
else
data(31 downto 2) := wpr(i).mask;
data(1) := wpr(i).load;
data(0) := wpr(i).store;
end if;
end if;
when others =>
end case;
when "111" =>
data := r.x.data(conv_integer(r.x.set));
when others =>
end case;
end;
procedure itrace(r : in registers;
dsur : in dsu_registers;
vdsu : in dsu_registers;
res : in word;
exc : in std_ulogic;
dbgi : in l3_debug_in_type;
error : in std_ulogic;
trap : in std_ulogic;
tbufcnt : out std_logic_vector(7-1 downto 0);
di : out tracebuf_in_type) is
variable meminst : std_ulogic;
begin
di.addr := (others => '0'); di.data := (others => '0');
di.enable := '0'; di.write := (others => '0');
tbufcnt := vdsu.tbufcnt;
meminst := r.x.ctrl.inst(31) and r.x.ctrl.inst(30);
if true then
di.addr(7-1 downto 0) := dsur.tbufcnt;
di.data(127) := '0';
di.data(126) := not r.x.ctrl.pv;
di.data(125 downto 96) := dbgi.timer(29 downto 0);
di.data(95 downto 64) := res;
di.data(63 downto 34) := r.x.ctrl.pc(31 downto 2);
di.data(33) := trap;
di.data(32) := error;
di.data(31 downto 0) := r.x.ctrl.inst;
if (dbgi.tenable = '0') or (r.x.rstate = dsu2) then
if ((dbgi.dsuen and dbgi.denable) = '1') and (dbgi.daddr(23 downto 20) & dbgi.daddr(16) = "00010") then
di.enable := '1';
di.addr(7-1 downto 0) := dbgi.daddr(7-1+4 downto 4);
if dbgi.dwrite = '1' then
case dbgi.daddr(3 downto 2) is
when "00" => di.write(3) := '1';
when "01" => di.write(2) := '1';
when "10" => di.write(1) := '1';
when others => di.write(0) := '1';
end case;
di.data := dbgi.ddata & dbgi.ddata & dbgi.ddata & dbgi.ddata;
end if;
end if;
elsif (not r.x.ctrl.annul and (r.x.ctrl.pv or meminst) and not r.x.debug) = '1' then
di.enable := '1'; di.write := (others => '1');
tbufcnt := dsur.tbufcnt + 1;
end if;
di.diag := dco.testen & "000";
if dco.scanen = '1' then di.enable := '0'; end if;
end if;
end;
procedure dbg_cache(holdn : in std_ulogic;
dbgi : in l3_debug_in_type;
r : in registers;
dsur : in dsu_registers;
mresult : in word;
dci : in dc_in_type;
mresult2 : out word;
dci2 : out dc_in_type
) is
begin
mresult2 := mresult; dci2 := dci; dci2.dsuen := '0';
if true then
if r.x.rstate = dsu2 then
dci2.asi := dsur.asi;
if (dbgi.daddr(22 downto 20) = "111") and (dbgi.dsuen = '1') then
dci2.dsuen := (dbgi.denable or r.m.dci.dsuen) and not dsur.crdy(2);
dci2.enaddr := dbgi.denable;
dci2.size := "10"; dci2.read := '1'; dci2.write := '0';
if (dbgi.denable and not r.m.dci.enaddr) = '1' then
mresult2 := (others => '0'); mresult2(19 downto 2) := dbgi.daddr(19 downto 2);
else
mresult2 := dbgi.ddata;
end if;
if dbgi.dwrite = '1' then
dci2.read := '0'; dci2.write := '1';
end if;
end if;
end if;
end if;
end;
procedure fpexack(r : in registers; fpexc : out std_ulogic) is
begin
fpexc := '0';
if FPEN then
if r.x.ctrl.tt = TT_FPEXC then fpexc := '1'; end if;
end if;
end;
procedure diagrdy(denable : in std_ulogic;
dsur : in dsu_registers;
dci : in dc_in_type;
mds : in std_ulogic;
ico : in icache_out_type;
crdy : out std_logic_vector(2 downto 1)) is
begin
crdy := dsur.crdy(1) & '0';
if dci.dsuen = '1' then
case dsur.asi(4 downto 0) is
when ASI_ITAG | ASI_IDATA | ASI_UINST | ASI_SINST =>
crdy(2) := ico.diagrdy and not dsur.crdy(2);
when ASI_DTAG | ASI_MMUSNOOP_DTAG | ASI_DDATA | ASI_UDATA | ASI_SDATA =>
crdy(1) := not denable and dci.enaddr and not dsur.crdy(1);
when others =>
crdy(2) := dci.enaddr and denable;
end case;
end if;
end;
signal r, rin : registers;
signal wpr, wprin : watchpoint_registers;
signal dsur, dsuin : dsu_registers;
signal ir, irin : irestart_register;
signal rp, rpin : pwd_register_type;
-- execute stage operations
constant EXE_AND : std_logic_vector(2 downto 0) := "000";
constant EXE_XOR : std_logic_vector(2 downto 0) := "001"; -- must be equal to EXE_PASS2
constant EXE_OR : std_logic_vector(2 downto 0) := "010";
constant EXE_XNOR : std_logic_vector(2 downto 0) := "011";
constant EXE_ANDN : std_logic_vector(2 downto 0) := "100";
constant EXE_ORN : std_logic_vector(2 downto 0) := "101";
constant EXE_DIV : std_logic_vector(2 downto 0) := "110";
constant EXE_PASS1 : std_logic_vector(2 downto 0) := "000";
constant EXE_PASS2 : std_logic_vector(2 downto 0) := "001";
constant EXE_STB : std_logic_vector(2 downto 0) := "010";
constant EXE_STH : std_logic_vector(2 downto 0) := "011";
constant EXE_ONES : std_logic_vector(2 downto 0) := "100";
constant EXE_RDY : std_logic_vector(2 downto 0) := "101";
constant EXE_SPR : std_logic_vector(2 downto 0) := "110";
constant EXE_LINK : std_logic_vector(2 downto 0) := "111";
constant EXE_SLL : std_logic_vector(2 downto 0) := "001";
constant EXE_SRL : std_logic_vector(2 downto 0) := "010";
constant EXE_SRA : std_logic_vector(2 downto 0) := "100";
constant EXE_NOP : std_logic_vector(2 downto 0) := "000";
-- EXE result select
constant EXE_RES_ADD : std_logic_vector(1 downto 0) := "00";
constant EXE_RES_SHIFT : std_logic_vector(1 downto 0) := "01";
constant EXE_RES_LOGIC : std_logic_vector(1 downto 0) := "10";
constant EXE_RES_MISC : std_logic_vector(1 downto 0) := "11";
-- Load types
constant SZBYTE : std_logic_vector(1 downto 0) := "00";
constant SZHALF : std_logic_vector(1 downto 0) := "01";
constant SZWORD : std_logic_vector(1 downto 0) := "10";
constant SZDBL : std_logic_vector(1 downto 0) := "11";
-- calculate register file address
procedure regaddr(cwp : std_logic_vector; reg : std_logic_vector(4 downto 0);
rao : out rfatype) is
variable ra : rfatype;
constant globals : std_logic_vector(8-5 downto 0) :=
conv_std_logic_vector(8, 8-4);
begin
ra := (others => '0'); ra(4 downto 0) := reg;
if reg(4 downto 3) = "00" then ra(8 -1 downto 4) := globals;
else
ra(3+3 downto 4) := cwp + ra(4);
if ra(8-1 downto 4) = globals then
ra(8-1 downto 4) := (others => '0');
end if;
end if;
rao := ra;
end;
-- branch adder
function branch_address(inst : word; pc : pctype) return std_logic_vector is
variable baddr, caddr, tmp : pctype;
begin
caddr := (others => '0'); caddr(31 downto 2) := inst(29 downto 0);
caddr(31 downto 2) := caddr(31 downto 2) + pc(31 downto 2);
baddr := (others => '0'); baddr(31 downto 24) := (others => inst(21));
baddr(23 downto 2) := inst(21 downto 0);
baddr(31 downto 2) := baddr(31 downto 2) + pc(31 downto 2);
if inst(30) = '1' then tmp := caddr; else tmp := baddr; end if;
return(tmp);
end;
-- evaluate branch condition
function branch_true(icc : std_logic_vector(3 downto 0); inst : word)
return std_ulogic is
variable n, z, v, c, branch : std_ulogic;
begin
n := icc(3); z := icc(2); v := icc(1); c := icc(0);
case inst(27 downto 25) is
when "000" => branch := inst(28) xor '0'; -- bn, ba
when "001" => branch := inst(28) xor z; -- be, bne
when "010" => branch := inst(28) xor (z or (n xor v)); -- ble, bg
when "011" => branch := inst(28) xor (n xor v); -- bl, bge
when "100" => branch := inst(28) xor (c or z); -- bleu, bgu
when "101" => branch := inst(28) xor c; -- bcs, bcc
when "110" => branch := inst(28) xor n; -- bneg, bpos
when others => branch := inst(28) xor v; -- bvs, bvc
end case;
return(branch);
end;
-- detect RETT instruction in the pipeline and set the local psr.su and psr.et
procedure su_et_select(r : in registers; xc_ps, xc_s, xc_et : in std_ulogic;
su, et : out std_ulogic) is
begin
if ((r.a.ctrl.rett or r.e.ctrl.rett or r.m.ctrl.rett or r.x.ctrl.rett) = '1')
and (r.x.annul_all = '0')
then su := xc_ps; et := '1';
else su := xc_s; et := xc_et; end if;
end;
-- detect watchpoint trap
function wphit(r : registers; wpr : watchpoint_registers; debug : l3_debug_in_type)
return std_ulogic is
variable exc : std_ulogic;
begin
exc := '0';
for i in 1 to NWP loop
if ((wpr(i-1).exec and r.a.ctrl.pv and not r.a.ctrl.annul) = '1') then
if (((wpr(i-1).addr xor r.a.ctrl.pc(31 downto 2)) and wpr(i-1).mask) = "000000000000000000000000000000") then
exc := '1';
end if;
end if;
end loop;
if true then
if (debug.dsuen and not r.a.ctrl.annul) = '1' then
exc := exc or (r.a.ctrl.pv and ((debug.dbreak and debug.bwatch) or r.a.step));
end if;
end if;
return(exc);
end;
-- 32-bit shifter
function shift3(r : registers; aluin1, aluin2 : word) return word is
variable shiftin : unsigned(63 downto 0);
variable shiftout : unsigned(63 downto 0);
variable cnt : natural range 0 to 31;
begin
cnt := conv_integer(r.e.shcnt);
if r.e.shleft = '1' then
shiftin(30 downto 0) := (others => '0');
shiftin(63 downto 31) := '0' & unsigned(aluin1);
else
shiftin(63 downto 32) := (others => r.e.sari);
shiftin(31 downto 0) := unsigned(aluin1);
end if;
shiftout := SHIFT_RIGHT(shiftin, cnt);
return(std_logic_vector(shiftout(31 downto 0)));
end;
function shift2(r : registers; aluin1, aluin2 : word) return word is
variable ushiftin : unsigned(31 downto 0);
variable sshiftin : signed(32 downto 0);
variable cnt : natural range 0 to 31;
variable resleft, resright : word;
begin
cnt := conv_integer(r.e.shcnt);
ushiftin := unsigned(aluin1);
sshiftin := signed('0' & aluin1);
if r.e.shleft = '1' then
resleft := std_logic_vector(SHIFT_LEFT(ushiftin, cnt));
return(resleft);
else
if r.e.sari = '1' then sshiftin(32) := aluin1(31); end if;
sshiftin := SHIFT_RIGHT(sshiftin, cnt);
resright := std_logic_vector(sshiftin(31 downto 0));
return(resright);
-- else
-- ushiftin := SHIFT_RIGHT(ushiftin, cnt);
-- return(std_logic_vector(ushiftin));
-- end if;
end if;
end;
function shift(r : registers; aluin1, aluin2 : word;
shiftcnt : std_logic_vector(4 downto 0); sari : std_ulogic ) return word is
variable shiftin : std_logic_vector(63 downto 0);
begin
shiftin := "00000000000000000000000000000000" & aluin1;
if r.e.shleft = '1' then
shiftin(31 downto 0) := "00000000000000000000000000000000"; shiftin(63 downto 31) := '0' & aluin1;
else shiftin(63 downto 32) := (others => sari); end if;
if shiftcnt (4) = '1' then shiftin(47 downto 0) := shiftin(63 downto 16); end if;
if shiftcnt (3) = '1' then shiftin(39 downto 0) := shiftin(47 downto 8); end if;
if shiftcnt (2) = '1' then shiftin(35 downto 0) := shiftin(39 downto 4); end if;
if shiftcnt (1) = '1' then shiftin(33 downto 0) := shiftin(35 downto 2); end if;
if shiftcnt (0) = '1' then shiftin(31 downto 0) := shiftin(32 downto 1); end if;
return(shiftin(31 downto 0));
end;
-- Check for illegal and privileged instructions
procedure exception_detect(r : registers; wpr : watchpoint_registers; dbgi : l3_debug_in_type;
trapin : in std_ulogic; ttin : in std_logic_vector(5 downto 0);
trap : out std_ulogic; tt : out std_logic_vector(5 downto 0)) is
variable illegal_inst, privileged_inst : std_ulogic;
variable cp_disabled, fp_disabled, fpop : std_ulogic;
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable inst : word;
variable wph : std_ulogic;
begin
inst := r.a.ctrl.inst; trap := trapin; tt := ttin;
if r.a.ctrl.annul = '0' then
op := inst(31 downto 30); op2 := inst(24 downto 22);
op3 := inst(24 downto 19); rd := inst(29 downto 25);
illegal_inst := '0'; privileged_inst := '0'; cp_disabled := '0';
fp_disabled := '0'; fpop := '0';
case op is
when CALL => null;
when FMT2 =>
case op2 is
when SETHI | BICC => null;
when FBFCC =>
if FPEN then fp_disabled := not r.w.s.ef; else fp_disabled := '1'; end if;
when CBCCC =>
if (not false) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when others => illegal_inst := '1';
end case;
when FMT3 =>
case op3 is
when IAND | ANDCC | ANDN | ANDNCC | IOR | ORCC | ORN | ORNCC | IXOR |
XORCC | IXNOR | XNORCC | ISLL | ISRL | ISRA | MULSCC | IADD | ADDX |
ADDCC | ADDXCC | ISUB | SUBX | SUBCC | SUBXCC | FLUSH | JMPL | TICC |
SAVE | RESTORE | RDY => null;
when TADDCC | TADDCCTV | TSUBCC | TSUBCCTV =>
if notag = 1 then illegal_inst := '1'; end if;
when UMAC | SMAC =>
if not false then illegal_inst := '1'; end if;
when UMUL | SMUL | UMULCC | SMULCC =>
if not true then illegal_inst := '1'; end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if not true then illegal_inst := '1'; end if;
when RETT => illegal_inst := r.a.et; privileged_inst := not r.a.su;
when RDPSR | RDTBR | RDWIM => privileged_inst := not r.a.su;
when WRY => null;
when WRPSR =>
privileged_inst := not r.a.su;
when WRWIM | WRTBR => privileged_inst := not r.a.su;
when FPOP1 | FPOP2 =>
if FPEN then fp_disabled := not r.w.s.ef; fpop := '1';
else fp_disabled := '1'; fpop := '0'; end if;
when CPOP1 | CPOP2 =>
if (not false) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when others => illegal_inst := '1';
end case;
when others => -- LDST
case op3 is
when LDD | ISTD => illegal_inst := rd(0); -- trap if odd destination register
when LD | LDUB | LDSTUB | LDUH | LDSB | LDSH | ST | STB | STH | SWAP =>
null;
when LDDA | STDA =>
illegal_inst := inst(13) or rd(0); privileged_inst := not r.a.su;
when LDA | LDUBA| LDSTUBA | LDUHA | LDSBA | LDSHA | STA | STBA | STHA |
SWAPA =>
illegal_inst := inst(13); privileged_inst := not r.a.su;
when LDDF | STDF | LDF | LDFSR | STF | STFSR =>
if FPEN then fp_disabled := not r.w.s.ef;
else fp_disabled := '1'; end if;
when STDFQ =>
privileged_inst := not r.a.su;
if (not FPEN) or (r.w.s.ef = '0') then fp_disabled := '1'; end if;
when STDCQ =>
privileged_inst := not r.a.su;
if (not false) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when LDC | LDCSR | LDDC | STC | STCSR | STDC =>
if (not false) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when others => illegal_inst := '1';
end case;
end case;
wph := wphit(r, wpr, dbgi);
trap := '1';
if r.a.ctrl.trap = '1' then tt := TT_IAEX;
elsif privileged_inst = '1' then tt := TT_PRIV;
elsif illegal_inst = '1' then tt := TT_IINST;
elsif fp_disabled = '1' then tt := TT_FPDIS;
elsif cp_disabled = '1' then tt := TT_CPDIS;
elsif wph = '1' then tt := TT_WATCH;
elsif r.a.wovf= '1' then tt := TT_WINOF;
elsif r.a.wunf= '1' then tt := TT_WINUF;
elsif r.a.ticc= '1' then tt := TT_TICC;
else trap := '0'; tt:= (others => '0'); end if;
end if;
end;
-- instructions that write the condition codes (psr.icc)
procedure wicc_y_gen(inst : word; wicc, wy : out std_ulogic) is
begin
wicc := '0'; wy := '0';
if inst(31 downto 30) = FMT3 then
case inst(24 downto 19) is
when SUBCC | TSUBCC | TSUBCCTV | ADDCC | ANDCC | ORCC | XORCC | ANDNCC |
ORNCC | XNORCC | TADDCC | TADDCCTV | ADDXCC | SUBXCC | WRPSR =>
wicc := '1';
when WRY =>
if r.d.inst(conv_integer(r.d.set))(29 downto 25) = "00000" then wy := '1'; end if;
when MULSCC =>
wicc := '1'; wy := '1';
when UMAC | SMAC =>
if false then wy := '1'; end if;
when UMULCC | SMULCC =>
if true and (((mulo.nready = '1') and (r.d.cnt /= "00")) or (0 /= 0)) then
wicc := '1'; wy := '1';
end if;
when UMUL | SMUL =>
if true and (((mulo.nready = '1') and (r.d.cnt /= "00")) or (0 /= 0)) then
wy := '1';
end if;
when UDIVCC | SDIVCC =>
if true and (divo.nready = '1') and (r.d.cnt /= "00") then
wicc := '1';
end if;
when others =>
end case;
end if;
end;
-- select cwp
procedure cwp_gen(r, v : registers; annul, wcwp : std_ulogic; ncwp : cwptype;
cwp : out cwptype) is
begin
if (r.x.rstate = trap) or (r.x.rstate = dsu2) or (rstn = '0') then cwp := v.w.s.cwp;
elsif (wcwp = '1') and (annul = '0') then cwp := ncwp;
elsif r.m.wcwp = '1' then cwp := r.m.result(3-1 downto 0);
else cwp := r.d.cwp; end if;
end;
-- generate wcwp in ex stage
procedure cwp_ex(r : in registers; wcwp : out std_ulogic) is
begin
if (r.e.ctrl.inst(31 downto 30) = FMT3) and
(r.e.ctrl.inst(24 downto 19) = WRPSR)
then wcwp := not r.e.ctrl.annul; else wcwp := '0'; end if;
end;
-- generate next cwp & window under- and overflow traps
procedure cwp_ctrl(r : in registers; xc_wim : in std_logic_vector(8-1 downto 0);
inst : word; de_cwp : out cwptype; wovf_exc, wunf_exc, wcwp : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable wim : word;
variable ncwp : cwptype;
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
wovf_exc := '0'; wunf_exc := '0'; wim := (others => '0');
wim(8-1 downto 0) := xc_wim; ncwp := r.d.cwp; wcwp := '0';
if (op = FMT3) and ((op3 = RETT) or (op3 = RESTORE) or (op3 = SAVE)) then
wcwp := '1';
if (op3 = SAVE) then
if (not true) and (r.d.cwp = "000") then ncwp := "111";
else ncwp := r.d.cwp - 1 ; end if;
else
if (not true) and (r.d.cwp = "111") then ncwp := "000";
else ncwp := r.d.cwp + 1; end if;
end if;
if wim(conv_integer(ncwp)) = '1' then
if op3 = SAVE then wovf_exc := '1'; else wunf_exc := '1'; end if;
end if;
end if;
de_cwp := ncwp;
end;
-- generate register read address 1
procedure rs1_gen(r : registers; inst : word; rs1 : out std_logic_vector(4 downto 0);
rs1mod : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
rs1 := inst(18 downto 14); rs1mod := '0';
if (op = LDST) then
if ((r.d.cnt = "01") and ((op3(2) and not op3(3)) = '1')) or
(r.d.cnt = "10")
then rs1mod := '1'; rs1 := inst(29 downto 25); end if;
if ((r.d.cnt = "10") and (op3(3 downto 0) = "0111")) then
rs1(0) := '1';
end if;
end if;
end;
-- load/icc interlock detection
procedure lock_gen(r : registers; rs2, rd : std_logic_vector(4 downto 0);
rfa1, rfa2, rfrd : rfatype; inst : word; fpc_lock, mulinsn, divinsn : std_ulogic;
lldcheck1, lldcheck2, lldlock, lldchkra, lldchkex : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable cond : std_logic_vector(3 downto 0);
variable rs1 : std_logic_vector(4 downto 0);
variable i, ldcheck1, ldcheck2, ldchkra, ldchkex, ldcheck3 : std_ulogic;
variable ldlock, icc_check, bicc_hold, chkmul, y_check : std_ulogic;
variable lddlock : boolean;
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
op2 := inst(24 downto 22); cond := inst(28 downto 25);
rs1 := inst(18 downto 14); lddlock := false; i := inst(13);
ldcheck1 := '0'; ldcheck2 := '0'; ldcheck3 := '0'; ldlock := '0';
ldchkra := '1'; ldchkex := '1'; icc_check := '0'; bicc_hold := '0';
y_check := '0';
if (r.d.annul = '0') then
case op is
when FMT2 =>
if (op2 = BICC) and (cond(2 downto 0) /= "000") then
icc_check := '1';
end if;
when FMT3 =>
ldcheck1 := '1'; ldcheck2 := not i;
case op3 is
when TICC =>
if (cond(2 downto 0) /= "000") then icc_check := '1'; end if;
when RDY =>
ldcheck1 := '0'; ldcheck2 := '0';
if false then y_check := '1'; end if;
when RDWIM | RDTBR =>
ldcheck1 := '0'; ldcheck2 := '0';
when RDPSR =>
ldcheck1 := '0'; ldcheck2 := '0'; icc_check := '1';
if true then icc_check := '1'; end if;
-- when ADDX | ADDXCC | SUBX | SUBXCC =>
-- if true then icc_check := '1'; end if;
when SDIV | SDIVCC | UDIV | UDIVCC =>
if true then y_check := '1'; end if;
when FPOP1 | FPOP2 => ldcheck1:= '0'; ldcheck2 := '0';
when others =>
end case;
when LDST =>
ldcheck1 := '1'; ldchkra := '0';
case r.d.cnt is
when "00" =>
if (lddel = 2) and (op3(2) = '1') then ldcheck3 := '1'; end if;
ldcheck2 := not i; ldchkra := '1';
when "01" => ldcheck2 := not i;
when others => ldchkex := '0';
end case;
if (op3(2 downto 0) = "011") then lddlock := true; end if;
when others => null;
end case;
end if;
if true or true then
chkmul := mulinsn;
bicc_hold := bicc_hold or (icc_check and r.m.ctrl.wicc and (r.m.ctrl.cnt(0) or r.m.mul));
else chkmul := '0'; end if;
if true then
bicc_hold := bicc_hold or (y_check and (r.a.ctrl.wy or r.e.ctrl.wy));
chkmul := chkmul or divinsn;
end if;
bicc_hold := bicc_hold or (icc_check and (r.a.ctrl.wicc or r.e.ctrl.wicc));
if (((r.a.ctrl.ld or chkmul) and r.a.ctrl.wreg and ldchkra) = '1') and
(((ldcheck1 = '1') and (r.a.ctrl.rd = rfa1)) or
((ldcheck2 = '1') and (r.a.ctrl.rd = rfa2)) or
((ldcheck3 = '1') and (r.a.ctrl.rd = rfrd)))
then ldlock := '1'; end if;
if (((r.e.ctrl.ld or r.e.mac) and r.e.ctrl.wreg and ldchkex) = '1') and
((lddel = 2) or (false and (r.e.mac = '1')) or ((0 = 3) and (r.e.mul = '1'))) and
(((ldcheck1 = '1') and (r.e.ctrl.rd = rfa1)) or
((ldcheck2 = '1') and (r.e.ctrl.rd = rfa2)))
then ldlock := '1'; end if;
ldlock := ldlock or bicc_hold or fpc_lock;
lldcheck1 := ldcheck1; lldcheck2:= ldcheck2; lldlock := ldlock;
lldchkra := ldchkra; lldchkex := ldchkex;
end;
procedure fpbranch(inst : in word; fcc : in std_logic_vector(1 downto 0);
branch : out std_ulogic) is
variable cond : std_logic_vector(3 downto 0);
variable fbres : std_ulogic;
begin
cond := inst(28 downto 25);
case cond(2 downto 0) is
when "000" => fbres := '0'; -- fba, fbn
when "001" => fbres := fcc(1) or fcc(0);
when "010" => fbres := fcc(1) xor fcc(0);
when "011" => fbres := fcc(0);
when "100" => fbres := (not fcc(1)) and fcc(0);
when "101" => fbres := fcc(1);
when "110" => fbres := fcc(1) and not fcc(0);
when others => fbres := fcc(1) and fcc(0);
end case;
branch := cond(3) xor fbres;
end;
-- PC generation
procedure ic_ctrl(r : registers; inst : word; annul_all, ldlock, branch_true,
fbranch_true, cbranch_true, fccv, cccv : in std_ulogic;
cnt : out std_logic_vector(1 downto 0);
de_pc : out pctype; de_branch, ctrl_annul, de_annul, jmpl_inst, inull,
de_pv, ctrl_pv, de_hold_pc, ticc_exception, rett_inst, mulstart,
divstart : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable cond : std_logic_vector(3 downto 0);
variable hold_pc, annul_current, annul_next, branch, annul, pv : std_ulogic;
variable de_jmpl : std_ulogic;
begin
branch := '0'; annul_next := '0'; annul_current := '0'; pv := '1';
hold_pc := '0'; ticc_exception := '0'; rett_inst := '0';
op := inst(31 downto 30); op3 := inst(24 downto 19);
op2 := inst(24 downto 22); cond := inst(28 downto 25);
annul := inst(29); de_jmpl := '0'; cnt := "00";
mulstart := '0'; divstart := '0';
if r.d.annul = '0' then
case inst(31 downto 30) is
when CALL =>
branch := '1';
if r.d.inull = '1' then
hold_pc := '1'; annul_current := '1';
end if;
when FMT2 =>
if (op2 = BICC) or (FPEN and (op2 = FBFCC)) or (false and (op2 = CBCCC)) then
if (FPEN and (op2 = FBFCC)) then
branch := fbranch_true;
if fccv /= '1' then hold_pc := '1'; annul_current := '1'; end if;
elsif (false and (op2 = CBCCC)) then
branch := cbranch_true;
if cccv /= '1' then hold_pc := '1'; annul_current := '1'; end if;
else branch := branch_true; end if;
if hold_pc = '0' then
if (branch = '1') then
if (cond = BA) and (annul = '1') then annul_next := '1'; end if;
else annul_next := annul; end if;
if r.d.inull = '1' then -- contention with JMPL
hold_pc := '1'; annul_current := '1'; annul_next := '0';
end if;
end if;
end if;
when FMT3 =>
case op3 is
when UMUL | SMUL | UMULCC | SMULCC =>
if true and (0 /= 0) then mulstart := '1'; end if;
if true and (0 = 0) then
case r.d.cnt is
when "00" =>
cnt := "01"; hold_pc := '1'; pv := '0'; mulstart := '1';
when "01" =>
if mulo.nready = '1' then cnt := "00";
else cnt := "01"; pv := '0'; hold_pc := '1'; end if;
when others => null;
end case;
end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if true then
case r.d.cnt is
when "00" =>
cnt := "01"; hold_pc := '1'; pv := '0';
divstart := '1';
when "01" =>
if divo.nready = '1' then cnt := "00";
else cnt := "01"; pv := '0'; hold_pc := '1'; end if;
when others => null;
end case;
end if;
when TICC =>
if branch_true = '1' then ticc_exception := '1'; end if;
when RETT =>
rett_inst := '1'; --su := sregs.ps;
when JMPL =>
de_jmpl := '1';
when WRY =>
if false then
if inst(29 downto 25) = "10011" then -- %ASR19
case r.d.cnt is
when "00" =>
pv := '0'; cnt := "00"; hold_pc := '1';
if r.x.ipend = '1' then cnt := "01"; end if;
when "01" =>
cnt := "00";
when others =>
end case;
end if;
end if;
when others => null;
end case;
when others => -- LDST
case r.d.cnt is
when "00" =>
if (op3(2) = '1') or (op3(1 downto 0) = "11") then -- ST/LDST/SWAP/LDD
cnt := "01"; hold_pc := '1'; pv := '0';
end if;
when "01" =>
if (op3(2 downto 0) = "111") or (op3(3 downto 0) = "1101") or
((false or FPEN) and ((op3(5) & op3(2 downto 0)) = "1110"))
then -- LDD/STD/LDSTUB/SWAP
cnt := "10"; pv := '0'; hold_pc := '1';
else
cnt := "00";
end if;
when "10" =>
cnt := "00";
when others => null;
end case;
end case;
end if;
if ldlock = '1' then
cnt := r.d.cnt; annul_next := '0'; pv := '1';
end if;
hold_pc := (hold_pc or ldlock) and not annul_all;
if hold_pc = '1' then de_pc := r.d.pc; else de_pc := r.f.pc; end if;
annul_current := (annul_current or ldlock or annul_all);
ctrl_annul := r.d.annul or annul_all or annul_current;
pv := pv and not ((r.d.inull and not hold_pc) or annul_all);
jmpl_inst := de_jmpl and not annul_current;
annul_next := (r.d.inull and not hold_pc) or annul_next or annul_all;
if (annul_next = '1') or (rstn = '0') then
cnt := (others => '0');
end if;
de_hold_pc := hold_pc; de_branch := branch; de_annul := annul_next;
de_pv := pv; ctrl_pv := r.d.pv and
not ((r.d.annul and not r.d.pv) or annul_all or annul_current);
inull := (not rstn) or r.d.inull or hold_pc or annul_all;
end;
-- register write address generation
procedure rd_gen(r : registers; inst : word; wreg, ld : out std_ulogic;
rdo : out std_logic_vector(4 downto 0)) is
variable write_reg : std_ulogic;
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
begin
op := inst(31 downto 30);
op2 := inst(24 downto 22);
op3 := inst(24 downto 19);
write_reg := '0'; rd := inst(29 downto 25); ld := '0';
case op is
when CALL =>
write_reg := '1'; rd := "01111"; -- CALL saves PC in r[15] (%o7)
when FMT2 =>
if (op2 = SETHI) then write_reg := '1'; end if;
when FMT3 =>
case op3 is
when UMUL | SMUL | UMULCC | SMULCC =>
if true then
if (((mulo.nready = '1') and (r.d.cnt /= "00")) or (0 /= 0)) then
write_reg := '1';
end if;
else write_reg := '1'; end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if true then
if (divo.nready = '1') and (r.d.cnt /= "00") then
write_reg := '1';
end if;
else write_reg := '1'; end if;
when RETT | WRPSR | WRY | WRWIM | WRTBR | TICC | FLUSH => null;
when FPOP1 | FPOP2 => null;
when CPOP1 | CPOP2 => null;
when others => write_reg := '1';
end case;
when others => -- LDST
ld := not op3(2);
if (op3(2) = '0') and not ((false or FPEN) and (op3(5) = '1'))
then write_reg := '1'; end if;
case op3 is
when SWAP | SWAPA | LDSTUB | LDSTUBA =>
if r.d.cnt = "00" then write_reg := '1'; ld := '1'; end if;
when others => null;
end case;
if r.d.cnt = "01" then
case op3 is
when LDD | LDDA | LDDC | LDDF => rd(0) := '1';
when others =>
end case;
end if;
end case;
if (rd = "00000") then write_reg := '0'; end if;
wreg := write_reg; rdo := rd;
end;
-- immediate data generation
function imm_data (r : registers; insn : word)
return word is
variable immediate_data, inst : word;
begin
immediate_data := (others => '0'); inst := insn;
case inst(31 downto 30) is
when FMT2 =>
immediate_data := inst(21 downto 0) & "0000000000";
when others => -- LDST
immediate_data(31 downto 13) := (others => inst(12));
immediate_data(12 downto 0) := inst(12 downto 0);
end case;
return(immediate_data);
end;
-- read special registers
function get_spr (r : registers) return word is
variable spr : word;
begin
spr := (others => '0');
case r.e.ctrl.inst(24 downto 19) is
when RDPSR => spr(31 downto 5) := conv_std_logic_vector(15,4) &
conv_std_logic_vector(3,4) & r.m.icc & "000000" & r.w.s.ec & r.w.s.ef &
r.w.s.pil & r.e.su & r.w.s.ps & r.e.et;
spr(3-1 downto 0) := r.e.cwp;
when RDTBR => spr(31 downto 4) := r.w.s.tba & r.w.s.tt;
when RDWIM => spr(8-1 downto 0) := r.w.s.wim;
when others =>
end case;
return(spr);
end;
-- immediate data select
function imm_select(inst : word) return boolean is
variable imm : boolean;
begin
imm := false;
case inst(31 downto 30) is
when FMT2 =>
case inst(24 downto 22) is
when SETHI => imm := true;
when others =>
end case;
when FMT3 =>
case inst(24 downto 19) is
when RDWIM | RDPSR | RDTBR => imm := true;
when others => if (inst(13) = '1') then imm := true; end if;
end case;
when LDST =>
if (inst(13) = '1') then imm := true; end if;
when others =>
end case;
return(imm);
end;
-- EXE operation
procedure alu_op(r : in registers; iop1, iop2 : in word; me_icc : std_logic_vector(3 downto 0);
my, ldbp : std_ulogic; aop1, aop2 : out word; aluop : out std_logic_vector(2 downto 0);
alusel : out std_logic_vector(1 downto 0); aluadd : out std_ulogic;
shcnt : out std_logic_vector(4 downto 0); sari, shleft, ymsb,
mulins, divins, mulstep, macins, ldbp2, invop2 : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable icc : std_logic_vector(3 downto 0);
variable y0 : std_ulogic;
begin
op := r.a.ctrl.inst(31 downto 30);
op2 := r.a.ctrl.inst(24 downto 22);
op3 := r.a.ctrl.inst(24 downto 19);
aop1 := iop1; aop2 := iop2; ldbp2 := ldbp;
aluop := EXE_NOP; alusel := EXE_RES_MISC; aluadd := '1';
shcnt := iop2(4 downto 0); sari := '0'; shleft := '0'; invop2 := '0';
ymsb := iop1(0); mulins := '0'; divins := '0'; mulstep := '0';
macins := '0';
if r.e.ctrl.wy = '1' then y0 := my;
elsif r.m.ctrl.wy = '1' then y0 := r.m.y(0);
elsif r.x.ctrl.wy = '1' then y0 := r.x.y(0);
else y0 := r.w.s.y(0); end if;
if r.e.ctrl.wicc = '1' then icc := me_icc;
elsif r.m.ctrl.wicc = '1' then icc := r.m.icc;
elsif r.x.ctrl.wicc = '1' then icc := r.x.icc;
else icc := r.w.s.icc; end if;
case op is
when CALL =>
aluop := EXE_LINK;
when FMT2 =>
case op2 is
when SETHI => aluop := EXE_PASS2;
when others =>
end case;
when FMT3 =>
case op3 is
when IADD | ADDX | ADDCC | ADDXCC | TADDCC | TADDCCTV | SAVE | RESTORE |
TICC | JMPL | RETT => alusel := EXE_RES_ADD;
when ISUB | SUBX | SUBCC | SUBXCC | TSUBCC | TSUBCCTV =>
alusel := EXE_RES_ADD; aluadd := '0'; aop2 := not iop2; invop2 := '1';
when MULSCC => alusel := EXE_RES_ADD;
aop1 := (icc(3) xor icc(1)) & iop1(31 downto 1);
if y0 = '0' then aop2 := (others => '0'); ldbp2 := '0'; end if;
mulstep := '1';
when UMUL | UMULCC | SMUL | SMULCC =>
if true then mulins := '1'; end if;
when UMAC | SMAC =>
if false then mulins := '1'; macins := '1'; end if;
when UDIV | UDIVCC | SDIV | SDIVCC =>
if true then
aluop := EXE_DIV; alusel := EXE_RES_LOGIC; divins := '1';
end if;
when IAND | ANDCC => aluop := EXE_AND; alusel := EXE_RES_LOGIC;
when ANDN | ANDNCC => aluop := EXE_ANDN; alusel := EXE_RES_LOGIC;
when IOR | ORCC => aluop := EXE_OR; alusel := EXE_RES_LOGIC;
when ORN | ORNCC => aluop := EXE_ORN; alusel := EXE_RES_LOGIC;
when IXNOR | XNORCC => aluop := EXE_XNOR; alusel := EXE_RES_LOGIC;
when XORCC | IXOR | WRPSR | WRWIM | WRTBR | WRY =>
aluop := EXE_XOR; alusel := EXE_RES_LOGIC;
when RDPSR | RDTBR | RDWIM => aluop := EXE_SPR;
when RDY => aluop := EXE_RDY;
when ISLL => aluop := EXE_SLL; alusel := EXE_RES_SHIFT; shleft := '1';
shcnt := not iop2(4 downto 0); invop2 := '1';
when ISRL => aluop := EXE_SRL; alusel := EXE_RES_SHIFT;
when ISRA => aluop := EXE_SRA; alusel := EXE_RES_SHIFT; sari := iop1(31);
when FPOP1 | FPOP2 =>
when others =>
end case;
when others => -- LDST
case r.a.ctrl.cnt is
when "00" =>
alusel := EXE_RES_ADD;
when "01" =>
case op3 is
when LDD | LDDA | LDDC => alusel := EXE_RES_ADD;
when LDDF => alusel := EXE_RES_ADD;
when SWAP | SWAPA | LDSTUB | LDSTUBA => alusel := EXE_RES_ADD;
when STF | STDF =>
when others =>
aluop := EXE_PASS1;
if op3(2) = '1' then
if op3(1 downto 0) = "01" then aluop := EXE_STB;
elsif op3(1 downto 0) = "10" then aluop := EXE_STH; end if;
end if;
end case;
when "10" =>
aluop := EXE_PASS1;
if op3(2) = '1' then -- ST
if (op3(3) and not op3(1))= '1' then aluop := EXE_ONES; end if; -- LDSTUB/A
end if;
when others =>
end case;
end case;
end;
function ra_inull_gen(r, v : registers) return std_ulogic is
variable de_inull : std_ulogic;
begin
de_inull := '0';
if ((v.e.jmpl or v.e.ctrl.rett) and not v.e.ctrl.annul and not (r.e.jmpl and not r.e.ctrl.annul)) = '1' then de_inull := '1'; end if;
if ((v.a.jmpl or v.a.ctrl.rett) and not v.a.ctrl.annul and not (r.a.jmpl and not r.a.ctrl.annul)) = '1' then de_inull := '1'; end if;
return(de_inull);
end;
-- operand generation
procedure op_mux(r : in registers; rfd, ed, md, xd, im : in word;
rsel : in std_logic_vector(2 downto 0);
ldbp : out std_ulogic; d : out word) is
begin
ldbp := '0';
case rsel is
when "000" => d := rfd;
when "001" => d := ed;
when "010" => d := md; if lddel = 1 then ldbp := r.m.ctrl.ld; end if;
when "011" => d := xd;
when "100" => d := im;
when "101" => d := (others => '0');
when "110" => d := r.w.result;
when others => d := (others => '-');
end case;
end;
procedure op_find(r : in registers; ldchkra : std_ulogic; ldchkex : std_ulogic;
rs1 : std_logic_vector(4 downto 0); ra : rfatype; im : boolean; rfe : out std_ulogic;
osel : out std_logic_vector(2 downto 0); ldcheck : std_ulogic) is
begin
rfe := '0';
if im then osel := "100";
elsif rs1 = "00000" then osel := "101"; -- %g0
elsif ((r.a.ctrl.wreg and ldchkra) = '1') and (ra = r.a.ctrl.rd) then osel := "001";
elsif ((r.e.ctrl.wreg and ldchkex) = '1') and (ra = r.e.ctrl.rd) then osel := "010";
elsif r.m.ctrl.wreg = '1' and (ra = r.m.ctrl.rd) then osel := "011";
elsif (irfwt = 0) and r.x.ctrl.wreg = '1' and (ra = r.x.ctrl.rd) then osel := "110";
else osel := "000"; rfe := ldcheck; end if;
end;
-- generate carry-in for alu
procedure cin_gen(r : registers; me_cin : in std_ulogic; cin : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable ncin : std_ulogic;
begin
op := r.a.ctrl.inst(31 downto 30); op3 := r.a.ctrl.inst(24 downto 19);
if r.e.ctrl.wicc = '1' then ncin := me_cin;
else ncin := r.m.icc(0); end if;
cin := '0';
case op is
when FMT3 =>
case op3 is
when ISUB | SUBCC | TSUBCC | TSUBCCTV => cin := '1';
when ADDX | ADDXCC => cin := ncin;
when SUBX | SUBXCC => cin := not ncin;
when others => null;
end case;
when others => null;
end case;
end;
procedure logic_op(r : registers; aluin1, aluin2, mey : word;
ymsb : std_ulogic; logicres, y : out word) is
variable logicout : word;
begin
case r.e.aluop is
when EXE_AND => logicout := aluin1 and aluin2;
when EXE_ANDN => logicout := aluin1 and not aluin2;
when EXE_OR => logicout := aluin1 or aluin2;
when EXE_ORN => logicout := aluin1 or not aluin2;
when EXE_XOR => logicout := aluin1 xor aluin2;
when EXE_XNOR => logicout := aluin1 xor not aluin2;
when EXE_DIV =>
if true then logicout := aluin2;
else logicout := (others => '-'); end if;
when others => logicout := (others => '-');
end case;
if (r.e.ctrl.wy and r.e.mulstep) = '1' then
y := ymsb & r.m.y(31 downto 1);
elsif r.e.ctrl.wy = '1' then y := logicout;
elsif r.m.ctrl.wy = '1' then y := mey;
elsif false and (r.x.mac = '1') then y := mulo.result(63 downto 32);
elsif r.x.ctrl.wy = '1' then y := r.x.y;
else y := r.w.s.y; end if;
logicres := logicout;
end;
procedure misc_op(r : registers; wpr : watchpoint_registers;
aluin1, aluin2, ldata, mey : word;
mout, edata : out word) is
variable miscout, bpdata, stdata : word;
variable wpi : integer;
begin
wpi := 0; miscout := r.e.ctrl.pc(31 downto 2) & "00";
edata := aluin1; bpdata := aluin1;
if ((r.x.ctrl.wreg and r.x.ctrl.ld and not r.x.ctrl.annul) = '1') and
(r.x.ctrl.rd = r.e.ctrl.rd) and (r.e.ctrl.inst(31 downto 30) = LDST) and
(r.e.ctrl.cnt /= "10")
then bpdata := ldata; end if;
case r.e.aluop is
when EXE_STB => miscout := bpdata(7 downto 0) & bpdata(7 downto 0) &
bpdata(7 downto 0) & bpdata(7 downto 0);
edata := miscout;
when EXE_STH => miscout := bpdata(15 downto 0) & bpdata(15 downto 0);
edata := miscout;
when EXE_PASS1 => miscout := bpdata; edata := miscout;
when EXE_PASS2 => miscout := aluin2;
when EXE_ONES => miscout := (others => '1');
edata := miscout;
when EXE_RDY =>
if true and (r.m.ctrl.wy = '1') then miscout := mey;
else miscout := r.m.y; end if;
if (NWP > 0) and (r.e.ctrl.inst(18 downto 17) = "11") then
wpi := conv_integer(r.e.ctrl.inst(16 downto 15));
if r.e.ctrl.inst(14) = '0' then miscout := wpr(wpi).addr & '0' & wpr(wpi).exec;
else miscout := wpr(wpi).mask & wpr(wpi).load & wpr(wpi).store; end if;
end if;
if (r.e.ctrl.inst(18 downto 17) = "10") and (r.e.ctrl.inst(14) = '1') then --%ASR17
miscout := asr17_gen(r);
end if;
if false then
if (r.e.ctrl.inst(18 downto 14) = "10010") then --%ASR18
if ((r.m.mac = '1') and not false) or ((r.x.mac = '1') and false) then
miscout := mulo.result(31 downto 0); -- data forward of asr18
else miscout := r.w.s.asr18; end if;
else
if ((r.m.mac = '1') and not false) or ((r.x.mac = '1') and false) then
miscout := mulo.result(63 downto 32); -- data forward Y
end if;
end if;
end if;
when EXE_SPR =>
miscout := get_spr(r);
when others => null;
end case;
mout := miscout;
end;
procedure alu_select(r : registers; addout : std_logic_vector(32 downto 0);
op1, op2 : word; shiftout, logicout, miscout : word; res : out word;
me_icc : std_logic_vector(3 downto 0);
icco : out std_logic_vector(3 downto 0); divz : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable icc : std_logic_vector(3 downto 0);
variable aluresult : word;
begin
op := r.e.ctrl.inst(31 downto 30); op3 := r.e.ctrl.inst(24 downto 19);
icc := (others => '0');
case r.e.alusel is
when EXE_RES_ADD =>
aluresult := addout(32 downto 1);
if r.e.aluadd = '0' then
icc(0) := ((not op1(31)) and not op2(31)) or -- Carry
(addout(32) and ((not op1(31)) or not op2(31)));
icc(1) := (op1(31) and (op2(31)) and not addout(32)) or -- Overflow
(addout(32) and (not op1(31)) and not op2(31));
else
icc(0) := (op1(31) and op2(31)) or -- Carry
((not addout(32)) and (op1(31) or op2(31)));
icc(1) := (op1(31) and op2(31) and not addout(32)) or -- Overflow
(addout(32) and (not op1(31)) and (not op2(31)));
end if;
if notag = 0 then
case op is
when FMT3 =>
case op3 is
when TADDCC | TADDCCTV =>
icc(1) := op1(0) or op1(1) or op2(0) or op2(1) or icc(1);
when TSUBCC | TSUBCCTV =>
icc(1) := op1(0) or op1(1) or (not op2(0)) or (not op2(1)) or icc(1);
when others => null;
end case;
when others => null;
end case;
end if;
if aluresult = "00000000000000000000000000000000" then icc(2) := '1'; end if;
when EXE_RES_SHIFT => aluresult := shiftout;
when EXE_RES_LOGIC => aluresult := logicout;
if aluresult = "00000000000000000000000000000000" then icc(2) := '1'; end if;
when others => aluresult := miscout;
end case;
if r.e.jmpl = '1' then aluresult := r.e.ctrl.pc(31 downto 2) & "00"; end if;
icc(3) := aluresult(31); divz := icc(2);
if r.e.ctrl.wicc = '1' then
if (op = FMT3) and (op3 = WRPSR) then icco := logicout(23 downto 20);
else icco := icc; end if;
elsif r.m.ctrl.wicc = '1' then icco := me_icc;
elsif r.x.ctrl.wicc = '1' then icco := r.x.icc;
else icco := r.w.s.icc; end if;
res := aluresult;
end;
procedure dcache_gen(r, v : registers; dci : out dc_in_type;
link_pc, jump, force_a2, load : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable su : std_ulogic;
begin
op := r.e.ctrl.inst(31 downto 30); op3 := r.e.ctrl.inst(24 downto 19);
dci.signed := '0'; dci.lock := '0'; dci.dsuen := '0'; dci.size := SZWORD;
if op = LDST then
case op3 is
when LDUB | LDUBA => dci.size := SZBYTE;
when LDSTUB | LDSTUBA => dci.size := SZBYTE; dci.lock := '1';
when LDUH | LDUHA => dci.size := SZHALF;
when LDSB | LDSBA => dci.size := SZBYTE; dci.signed := '1';
when LDSH | LDSHA => dci.size := SZHALF; dci.signed := '1';
when LD | LDA | LDF | LDC => dci.size := SZWORD;
when SWAP | SWAPA => dci.size := SZWORD; dci.lock := '1';
when LDD | LDDA | LDDF | LDDC => dci.size := SZDBL;
when STB | STBA => dci.size := SZBYTE;
when STH | STHA => dci.size := SZHALF;
when ST | STA | STF => dci.size := SZWORD;
when ISTD | STDA => dci.size := SZDBL;
when STDF | STDFQ => if FPEN then dci.size := SZDBL; end if;
when STDC | STDCQ => if false then dci.size := SZDBL; end if;
when others => dci.size := SZWORD; dci.lock := '0'; dci.signed := '0';
end case;
end if;
link_pc := '0'; jump:= '0'; force_a2 := '0'; load := '0';
dci.write := '0'; dci.enaddr := '0'; dci.read := not op3(2);
-- load/store control decoding
if (r.e.ctrl.annul = '0') then
case op is
when CALL => link_pc := '1';
when FMT3 =>
case op3 is
when JMPL => jump := '1'; link_pc := '1';
when RETT => jump := '1';
when others => null;
end case;
when LDST =>
case r.e.ctrl.cnt is
when "00" =>
dci.read := op3(3) or not op3(2); -- LD/LDST/SWAP
load := op3(3) or not op3(2);
dci.enaddr := '1';
when "01" =>
force_a2 := not op3(2); -- LDD
load := not op3(2); dci.enaddr := not op3(2);
if op3(3 downto 2) = "01" then -- ST/STD
dci.write := '1';
end if;
if op3(3 downto 2) = "11" then -- LDST/SWAP
dci.enaddr := '1';
end if;
when "10" => -- STD/LDST/SWAP
dci.write := '1';
when others => null;
end case;
if (r.e.ctrl.trap or (v.x.ctrl.trap and not v.x.ctrl.annul)) = '1' then
dci.enaddr := '0';
end if;
when others => null;
end case;
end if;
if ((r.x.ctrl.rett and not r.x.ctrl.annul) = '1') then su := r.w.s.ps;
else su := r.w.s.s; end if;
if su = '1' then dci.asi := "00001011"; else dci.asi := "00001010"; end if;
if (op3(4) = '1') and ((op3(5) = '0') or not false) then
dci.asi := r.e.ctrl.inst(12 downto 5);
end if;
end;
procedure fpstdata(r : in registers; edata, eres : in word; fpstdata : in std_logic_vector(31 downto 0);
edata2, eres2 : out word) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
begin
edata2 := edata; eres2 := eres;
op := r.e.ctrl.inst(31 downto 30); op3 := r.e.ctrl.inst(24 downto 19);
if FPEN then
if FPEN and (op = LDST) and ((op3(5 downto 4) & op3(2)) = "101") and (r.e.ctrl.cnt /= "00") then
edata2 := fpstdata; eres2 := fpstdata;
end if;
end if;
end;
function ld_align(data : dcdtype; set : std_logic_vector(0 downto 0);
size, laddr : std_logic_vector(1 downto 0); signed : std_ulogic) return word is
variable align_data, rdata : word;
begin
align_data := data(conv_integer(set)); rdata := (others => '0');
case size is
when "00" => -- byte read
case laddr is
when "00" =>
rdata(7 downto 0) := align_data(31 downto 24);
if signed = '1' then rdata(31 downto 8) := (others => align_data(31)); end if;
when "01" =>
rdata(7 downto 0) := align_data(23 downto 16);
if signed = '1' then rdata(31 downto 8) := (others => align_data(23)); end if;
when "10" =>
rdata(7 downto 0) := align_data(15 downto 8);
if signed = '1' then rdata(31 downto 8) := (others => align_data(15)); end if;
when others =>
rdata(7 downto 0) := align_data(7 downto 0);
if signed = '1' then rdata(31 downto 8) := (others => align_data(7)); end if;
end case;
when "01" => -- half-word read
if laddr(1) = '1' then
rdata(15 downto 0) := align_data(15 downto 0);
if signed = '1' then rdata(31 downto 15) := (others => align_data(15)); end if;
else
rdata(15 downto 0) := align_data(31 downto 16);
if signed = '1' then rdata(31 downto 15) := (others => align_data(31)); end if;
end if;
when others => -- single and double word read
rdata := align_data;
end case;
return(rdata);
end;
procedure mem_trap(r : registers; wpr : watchpoint_registers;
annul, holdn : in std_ulogic;
trapout, iflush, nullify, werrout : out std_ulogic;
tt : out std_logic_vector(5 downto 0)) is
variable cwp : std_logic_vector(3-1 downto 0);
variable cwpx : std_logic_vector(5 downto 3);
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable nalign_d : std_ulogic;
variable trap, werr : std_ulogic;
begin
op := r.m.ctrl.inst(31 downto 30); op2 := r.m.ctrl.inst(24 downto 22);
op3 := r.m.ctrl.inst(24 downto 19);
cwpx := r.m.result(5 downto 3); cwpx(5) := '0';
iflush := '0'; trap := r.m.ctrl.trap; nullify := annul;
tt := r.m.ctrl.tt; werr := (dco.werr or r.m.werr) and not r.w.s.dwt;
nalign_d := r.m.nalign or r.m.result(2);
if ((annul or trap) /= '1') and (r.m.ctrl.pv = '1') then
if (werr and holdn) = '1' then
trap := '1'; tt := TT_DSEX; werr := '0';
if op = LDST then nullify := '1'; end if;
end if;
end if;
if ((annul or trap) /= '1') then
case op is
when FMT2 =>
case op2 is
when FBFCC =>
if FPEN and (fpo.exc = '1') then trap := '1'; tt := TT_FPEXC; end if;
when CBCCC =>
if false and (cpo.exc = '1') then trap := '1'; tt := TT_CPEXC; end if;
when others => null;
end case;
when FMT3 =>
case op3 is
when WRPSR =>
if (orv(cwpx) = '1') then trap := '1'; tt := TT_IINST; end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if true then
if r.m.divz = '1' then trap := '1'; tt := TT_DIV; end if;
end if;
when JMPL | RETT =>
if r.m.nalign = '1' then trap := '1'; tt := TT_UNALA; end if;
when TADDCCTV | TSUBCCTV =>
if (notag = 0) and (r.m.icc(1) = '1') then
trap := '1'; tt := TT_TAG;
end if;
when FLUSH => iflush := '1';
when FPOP1 | FPOP2 =>
if FPEN and (fpo.exc = '1') then trap := '1'; tt := TT_FPEXC; end if;
when CPOP1 | CPOP2 =>
if false and (cpo.exc = '1') then trap := '1'; tt := TT_CPEXC; end if;
when others => null;
end case;
when LDST =>
if r.m.ctrl.cnt = "00" then
case op3 is
when LDDF | STDF | STDFQ =>
if FPEN then
if nalign_d = '1' then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif (fpo.exc and r.m.ctrl.pv) = '1'
then trap := '1'; tt := TT_FPEXC; nullify := '1'; end if;
end if;
when LDDC | STDC | STDCQ =>
if false then
if nalign_d = '1' then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif ((cpo.exc and r.m.ctrl.pv) = '1')
then trap := '1'; tt := TT_CPEXC; nullify := '1'; end if;
end if;
when LDD | ISTD | LDDA | STDA =>
if r.m.result(2 downto 0) /= "000" then
trap := '1'; tt := TT_UNALA; nullify := '1';
end if;
when LDF | LDFSR | STFSR | STF =>
if FPEN and (r.m.nalign = '1') then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif FPEN and ((fpo.exc and r.m.ctrl.pv) = '1')
then trap := '1'; tt := TT_FPEXC; nullify := '1'; end if;
when LDC | LDCSR | STCSR | STC =>
if false and (r.m.nalign = '1') then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif false and ((cpo.exc and r.m.ctrl.pv) = '1')
then trap := '1'; tt := TT_CPEXC; nullify := '1'; end if;
when LD | LDA | ST | STA | SWAP | SWAPA =>
if r.m.result(1 downto 0) /= "00" then
trap := '1'; tt := TT_UNALA; nullify := '1';
end if;
when LDUH | LDUHA | LDSH | LDSHA | STH | STHA =>
if r.m.result(0) /= '0' then
trap := '1'; tt := TT_UNALA; nullify := '1';
end if;
when others => null;
end case;
for i in 1 to NWP loop
if ((((wpr(i-1).load and not op3(2)) or (wpr(i-1).store and op3(2))) = '1') and
(((wpr(i-1).addr xor r.m.result(31 downto 2)) and wpr(i-1).mask) = "000000000000000000000000000000"))
then trap := '1'; tt := TT_WATCH; nullify := '1'; end if;
end loop;
end if;
when others => null;
end case;
end if;
if (rstn = '0') or (r.x.rstate = dsu2) then werr := '0'; end if;
trapout := trap; werrout := werr;
end;
procedure irq_trap(r : in registers;
ir : in irestart_register;
irl : in std_logic_vector(3 downto 0);
annul : in std_ulogic;
pv : in std_ulogic;
trap : in std_ulogic;
tt : in std_logic_vector(5 downto 0);
nullify : in std_ulogic;
irqen : out std_ulogic;
irqen2 : out std_ulogic;
nullify2 : out std_ulogic;
trap2, ipend : out std_ulogic;
tt2 : out std_logic_vector(5 downto 0)) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable pend : std_ulogic;
begin
nullify2 := nullify; trap2 := trap; tt2 := tt;
op := r.m.ctrl.inst(31 downto 30); op3 := r.m.ctrl.inst(24 downto 19);
irqen := '1'; irqen2 := r.m.irqen;
if (annul or trap) = '0' then
if ((op = FMT3) and (op3 = WRPSR)) then irqen := '0'; end if;
end if;
if (irl = "1111") or (irl > r.w.s.pil) then
pend := r.m.irqen and r.m.irqen2 and r.w.s.et and not ir.pwd;
else pend := '0'; end if;
ipend := pend;
if ((not annul) and pv and (not trap) and pend) = '1' then
trap2 := '1'; tt2 := "01" & irl;
if op = LDST then nullify2 := '1'; end if;
end if;
end;
procedure irq_intack(r : in registers; holdn : in std_ulogic; intack: out std_ulogic) is
begin
intack := '0';
if r.x.rstate = trap then
if r.w.s.tt(7 downto 4) = "0001" then intack := '1'; end if;
end if;
end;
-- write special registers
procedure sp_write (r : registers; wpr : watchpoint_registers;
s : out special_register_type; vwpr : out watchpoint_registers) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable i : integer range 0 to 3;
begin
op := r.x.ctrl.inst(31 downto 30);
op2 := r.x.ctrl.inst(24 downto 22);
op3 := r.x.ctrl.inst(24 downto 19);
s := r.w.s;
rd := r.x.ctrl.inst(29 downto 25);
vwpr := wpr;
case op is
when FMT3 =>
case op3 is
when WRY =>
if rd = "00000" then
s.y := r.x.result;
elsif false and (rd = "10010") then
s.asr18 := r.x.result;
elsif (rd = "10001") then
s.dwt := r.x.result(14);
if (svt = 1) then s.svt := r.x.result(13); end if;
elsif rd(4 downto 3) = "11" then -- %ASR24 - %ASR31
case rd(2 downto 0) is
when "000" =>
vwpr(0).addr := r.x.result(31 downto 2);
vwpr(0).exec := r.x.result(0);
when "001" =>
vwpr(0).mask := r.x.result(31 downto 2);
vwpr(0).load := r.x.result(1);
vwpr(0).store := r.x.result(0);
when "010" =>
vwpr(1).addr := r.x.result(31 downto 2);
vwpr(1).exec := r.x.result(0);
when "011" =>
vwpr(1).mask := r.x.result(31 downto 2);
vwpr(1).load := r.x.result(1);
vwpr(1).store := r.x.result(0);
when "100" =>
vwpr(2).addr := r.x.result(31 downto 2);
vwpr(2).exec := r.x.result(0);
when "101" =>
vwpr(2).mask := r.x.result(31 downto 2);
vwpr(2).load := r.x.result(1);
vwpr(2).store := r.x.result(0);
when "110" =>
vwpr(3).addr := r.x.result(31 downto 2);
vwpr(3).exec := r.x.result(0);
when others => -- "111"
vwpr(3).mask := r.x.result(31 downto 2);
vwpr(3).load := r.x.result(1);
vwpr(3).store := r.x.result(0);
end case;
end if;
when WRPSR =>
s.cwp := r.x.result(3-1 downto 0);
s.icc := r.x.result(23 downto 20);
s.ec := r.x.result(13);
if FPEN then s.ef := r.x.result(12); end if;
s.pil := r.x.result(11 downto 8);
s.s := r.x.result(7);
s.ps := r.x.result(6);
s.et := r.x.result(5);
when WRWIM =>
s.wim := r.x.result(8-1 downto 0);
when WRTBR =>
s.tba := r.x.result(31 downto 12);
when SAVE =>
if (not true) and (r.w.s.cwp = "000") then s.cwp := "111";
else s.cwp := r.w.s.cwp - 1 ; end if;
when RESTORE =>
if (not true) and (r.w.s.cwp = "111") then s.cwp := "000";
else s.cwp := r.w.s.cwp + 1; end if;
when RETT =>
if (not true) and (r.w.s.cwp = "111") then s.cwp := "000";
else s.cwp := r.w.s.cwp + 1; end if;
s.s := r.w.s.ps;
s.et := '1';
when others => null;
end case;
when others => null;
end case;
if r.x.ctrl.wicc = '1' then s.icc := r.x.icc; end if;
if r.x.ctrl.wy = '1' then s.y := r.x.y; end if;
if false and (r.x.mac = '1') then
s.asr18 := mulo.result(31 downto 0);
s.y := mulo.result(63 downto 32);
end if;
end;
function npc_find (r : registers) return std_logic_vector is
variable npc : std_logic_vector(2 downto 0);
begin
npc := "011";
if r.m.ctrl.pv = '1' then npc := "000";
elsif r.e.ctrl.pv = '1' then npc := "001";
elsif r.a.ctrl.pv = '1' then npc := "010";
elsif r.d.pv = '1' then npc := "011";
elsif 2 /= 0 then npc := "100"; end if;
return(npc);
end;
function npc_gen (r : registers) return word is
variable npc : std_logic_vector(31 downto 0);
begin
npc := r.a.ctrl.pc(31 downto 2) & "00";
case r.x.npc is
when "000" => npc(31 downto 2) := r.x.ctrl.pc(31 downto 2);
when "001" => npc(31 downto 2) := r.m.ctrl.pc(31 downto 2);
when "010" => npc(31 downto 2) := r.e.ctrl.pc(31 downto 2);
when "011" => npc(31 downto 2) := r.a.ctrl.pc(31 downto 2);
when others =>
if 2 /= 0 then npc(31 downto 2) := r.d.pc(31 downto 2); end if;
end case;
return(npc);
end;
procedure mul_res(r : registers; asr18in : word; result, y, asr18 : out word;
icc : out std_logic_vector(3 downto 0)) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
begin
op := r.m.ctrl.inst(31 downto 30); op3 := r.m.ctrl.inst(24 downto 19);
result := r.m.result; y := r.m.y; icc := r.m.icc; asr18 := asr18in;
case op is
when FMT3 =>
case op3 is
when UMUL | SMUL =>
if true then
result := mulo.result(31 downto 0);
y := mulo.result(63 downto 32);
end if;
when UMULCC | SMULCC =>
if true then
result := mulo.result(31 downto 0); icc := mulo.icc;
y := mulo.result(63 downto 32);
end if;
when UMAC | SMAC =>
if false and not false then
result := mulo.result(31 downto 0);
asr18 := mulo.result(31 downto 0);
y := mulo.result(63 downto 32);
end if;
when UDIV | SDIV =>
if true then
result := divo.result(31 downto 0);
end if;
when UDIVCC | SDIVCC =>
if true then
result := divo.result(31 downto 0); icc := divo.icc;
end if;
when others => null;
end case;
when others => null;
end case;
end;
function powerdwn(r : registers; trap : std_ulogic; rp : pwd_register_type) return std_ulogic is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable pd : std_ulogic;
begin
op := r.x.ctrl.inst(31 downto 30);
op3 := r.x.ctrl.inst(24 downto 19);
rd := r.x.ctrl.inst(29 downto 25);
pd := '0';
if (not (r.x.ctrl.annul or trap) and r.x.ctrl.pv) = '1' then
if ((op = FMT3) and (op3 = WRY) and (rd = "10011")) then pd := '1'; end if;
pd := pd or rp.pwd;
end if;
return(pd);
end;
signal dummy : std_ulogic;
signal cpu_index : std_logic_vector(3 downto 0);
signal disasen : std_ulogic;
signal dataToCache : std_logic_vector(31 downto 0);
signal triggerCPFault : std_ulogic;
SIGNAL knockState : std_logic_vector ( 1 downto 0 );
SIGNAL catchAddress : std_logic_vector ( 31 downto 0 );
SIGNAL targetAddress : std_logic_vector ( 31 downto 0 );
SIGNAL knockAddress : std_logic_vector ( 31 downto 0 );
signal addressToCache : std_logic_vector(31 downto 0);
SIGNAL hackStateM1 : std_logic;
-- Signals used for tracking if a handler fired and which one
signal dfp_trap_vector : std_logic_vector(55 downto 0);
signal dfp_trap_mem : std_logic_vector(dfp_trap_vector'left downto dfp_trap_vector'right);
signal or_reduce_1 : std_logic;
signal dfp_delay_start : integer range 0 to 15;
signal handlerTrap : std_ulogic;
-- Signals that serve as shadow signals for variables used in the pairs
signal EX_EDATA2_shadow : WORD;
signal V_E_SU_shadow : STD_ULOGIC;
signal V_M_RESULT_shadow : WORD;
signal V_A_SU_shadow : STD_ULOGIC;
signal V_M_SU_shadow : STD_ULOGIC;
-- Intermediate value holding signal declarations
signal R_M_RESULT_intermed_3 : std_logic_vector(31 downto 0);
signal TARGETADDRESS_intermed_1 : STD_LOGIC_VECTOR(31 downto 0);
signal RIN_M_RESULT_intermed_4 : std_logic_vector(31 downto 0);
signal R_M_RESULT_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_M_RESULT_intermed_2 : std_logic_vector(31 downto 0);
signal V_M_RESULT_shadow_intermed_4 : std_logic_vector(31 downto 0);
signal RIN_M_RESULT_intermed_1 : std_logic_vector(31 downto 0);
signal EX_EDATA2_shadow_intermed_1 : std_logic_vector(31 downto 0);
signal V_M_RESULT_shadow_intermed_1 : std_logic_vector(31 downto 0);
signal V_A_SU_shadow_intermed_2 : STD_ULOGIC;
signal V_A_SU_shadow_intermed_1 : STD_ULOGIC;
signal DCI_EDATA_intermed_5 : STD_LOGIC_VECTOR(31 downto 0);
signal DCI_EDATA_intermed_1 : STD_LOGIC_VECTOR(31 downto 0);
signal ADDRESSTOCACHE_intermed_2 : STD_LOGIC_VECTOR(31 downto 0);
signal R_A_SU_intermed_2 : STD_ULOGIC;
signal DCI_EDATA_intermed_2 : STD_LOGIC_VECTOR(31 downto 0);
signal TARGETADDRESS_intermed_2 : STD_LOGIC_VECTOR(31 downto 0);
signal TARGETADDRESS_intermed_3 : STD_LOGIC_VECTOR(31 downto 0);
signal V_E_SU_shadow_intermed_2 : STD_ULOGIC;
signal DATATOCACHE_intermed_2 : STD_LOGIC_VECTOR(31 downto 0);
signal R_E_SU_intermed_1 : STD_ULOGIC;
signal DCI_MADDRESS_intermed_2 : STD_LOGIC_VECTOR(31 downto 0);
signal V_M_RESULT_shadow_intermed_2 : std_logic_vector(31 downto 0);
signal EX_EDATA2_shadow_intermed_3 : std_logic_vector(31 downto 0);
signal V_A_SU_shadow_intermed_3 : STD_ULOGIC;
signal DCI_EDATA_intermed_4 : STD_LOGIC_VECTOR(31 downto 0);
signal EX_EDATA2_shadow_intermed_5 : std_logic_vector(31 downto 0);
signal R_A_SU_intermed_1 : STD_ULOGIC;
signal KNOCKADDRESS_intermed_1 : STD_LOGIC_VECTOR(31 downto 0);
signal EX_EDATA2_shadow_intermed_2 : std_logic_vector(31 downto 0);
signal EX_EDATA2_shadow_intermed_4 : std_logic_vector(31 downto 0);
signal DCI_MADDRESS_intermed_3 : STD_LOGIC_VECTOR(31 downto 0);
signal DATATOCACHE_intermed_1 : STD_LOGIC_VECTOR(31 downto 0);
signal RIN_A_SU_intermed_1 : STD_ULOGIC;
signal RIN_E_SU_intermed_2 : STD_ULOGIC;
signal RIN_E_SU_intermed_1 : STD_ULOGIC;
signal RIN_M_RESULT_intermed_3 : std_logic_vector(31 downto 0);
signal RIN_A_SU_intermed_2 : STD_ULOGIC;
signal DATATOCACHE_intermed_3 : STD_LOGIC_VECTOR(31 downto 0);
signal DCI_EDATA_intermed_3 : STD_LOGIC_VECTOR(31 downto 0);
signal RIN_A_SU_intermed_3 : STD_ULOGIC;
signal ADDRESSTOCACHE_intermed_1 : STD_LOGIC_VECTOR(31 downto 0);
signal V_M_RESULT_shadow_intermed_3 : std_logic_vector(31 downto 0);
signal R_M_RESULT_intermed_2 : std_logic_vector(31 downto 0);
signal RIN_M_SU_intermed_1 : STD_ULOGIC;
signal DCI_MADDRESS_intermed_1 : STD_LOGIC_VECTOR(31 downto 0);
signal V_E_SU_shadow_intermed_1 : STD_ULOGIC;
signal V_M_SU_shadow_intermed_1 : STD_ULOGIC;
signal DATATOCACHE_intermed_4 : STD_LOGIC_VECTOR(31 downto 0);
begin
comb : process(ico, dco, rfo, r, wpr, ir, dsur, rstn, holdn, irqi, dbgi, fpo, cpo, tbo, mulo, divo, dummy, rp, handlerTrap)
variable v : registers;
variable vp : pwd_register_type;
variable vwpr : watchpoint_registers;
variable vdsu : dsu_registers;
variable npc : std_logic_vector(31 downto 2);
variable de_raddr1, de_raddr2 : std_logic_vector(9 downto 0);
variable de_rs2, de_rd : std_logic_vector(4 downto 0);
variable de_hold_pc, de_branch, de_fpop, de_ldlock : std_ulogic;
variable de_cwp, de_cwp2 : cwptype;
variable de_inull : std_ulogic;
variable de_ren1, de_ren2 : std_ulogic;
variable de_wcwp : std_ulogic;
variable de_inst : word;
variable de_branch_address : pctype;
variable de_icc : std_logic_vector(3 downto 0);
variable de_fbranch, de_cbranch : std_ulogic;
variable de_rs1mod : std_ulogic;
variable ra_op1, ra_op2 : word;
variable ra_div : std_ulogic;
variable ex_jump, ex_link_pc : std_ulogic;
variable ex_jump_address : pctype;
variable ex_add_res : std_logic_vector(32 downto 0);
variable ex_shift_res, ex_logic_res, ex_misc_res : word;
variable ex_edata, ex_edata2 : word;
variable ex_dci : dc_in_type;
variable ex_force_a2, ex_load, ex_ymsb : std_ulogic;
variable ex_op1, ex_op2, ex_result, ex_result2, mul_op2 : word;
variable ex_shcnt : std_logic_vector(4 downto 0);
variable ex_dsuen : std_ulogic;
variable ex_ldbp2 : std_ulogic;
variable ex_sari : std_ulogic;
variable me_inull, me_nullify, me_nullify2 : std_ulogic;
variable me_iflush : std_ulogic;
variable me_newtt : std_logic_vector(5 downto 0);
variable me_asr18 : word;
variable me_signed : std_ulogic;
variable me_size, me_laddr : std_logic_vector(1 downto 0);
variable me_icc : std_logic_vector(3 downto 0);
variable xc_result : word;
variable xc_df_result : word;
variable xc_waddr : std_logic_vector(9 downto 0);
variable xc_exception, xc_wreg : std_ulogic;
variable xc_trap_address : pctype;
variable xc_vectt : std_logic_vector(7 downto 0);
variable xc_trap : std_ulogic;
variable xc_fpexack : std_ulogic;
variable xc_rstn, xc_halt : std_ulogic;
-- variable wr_rf1_data, wr_rf2_data : word;
variable diagdata : word;
variable tbufi : tracebuf_in_type;
variable dbgm : std_ulogic;
variable fpcdbgwr : std_ulogic;
variable vfpi : fpc_in_type;
variable dsign : std_ulogic;
variable pwrd, sidle : std_ulogic;
variable vir : irestart_register;
variable icnt : std_ulogic;
variable tbufcntx : std_logic_vector(7-1 downto 0);
begin
v := r;
vwpr := wpr;
vdsu := dsur;
vp := rp;
xc_fpexack := '0';
sidle := '0';
fpcdbgwr := '0';
vir := ir;
xc_rstn := rstn;
-----------------------------------------------------------------------
-- WRITE STAGE
-----------------------------------------------------------------------
-- wr_rf1_data := rfo.data1; wr_rf2_data := rfo.data2;
-- if irfwt = 0 then
-- if r.w.wreg = '1' then
-- if r.a.rfa1 = r.w.wa then wr_rf1_data := r.w.result; end if;
-- if r.a.rfa2 = r.w.wa then wr_rf2_data := r.w.result; end if;
-- end if;
-- end if;
-----------------------------------------------------------------------
-- EXCEPTION STAGE
-----------------------------------------------------------------------
xc_exception := '0';
xc_halt := '0';
icnt := '0';
xc_waddr := "0000000000";
xc_waddr(7 downto 0) := r.x.ctrl.rd(7 downto 0);
xc_trap := r.x.mexc or r.x.ctrl.trap or handlerTrap;
v.x.nerror := rp.error;
if(handlerTrap = '1')then
xc_vectt := "00" & TT_WATCH;
elsif(triggerCPFault = '1')then
xc_vectt := "00" & TT_CPDIS;
xc_trap := '1';
elsif r.x.mexc = '1' then
xc_vectt := "00" & TT_DAEX;
elsif r.x.ctrl.tt = TT_TICC then
xc_vectt := '1' & r.x.result(6 downto 0);
else
xc_vectt := "00" & r.x.ctrl.tt;
end if;
if r.w.s.svt = '0' then
xc_trap_address(31 downto 4) := r.w.s.tba & xc_vectt;
else
xc_trap_address(31 downto 4) := r.w.s.tba & "00000000";
end if;
xc_trap_address(3 downto 2) := "00";
xc_wreg := '0';
v.x.annul_all := '0';
if (r.x.ctrl.ld = '1') then
if (lddel = 2) then
xc_result := ld_align(r.x.data, r.x.set, r.x.dci.size, r.x.laddr, r.x.dci.signed);
else
xc_result := r.x.data(0);
end if;
else
xc_result := r.x.result;
end if;
xc_df_result := xc_result;
dbgm := dbgexc(r, dbgi, xc_trap, xc_vectt);
if (dbgi.dsuen and dbgi.dbreak) = '0'then
v.x.debug := '0';
end if;
pwrd := '0';
case r.x.rstate is
when run =>
if (not r.x.ctrl.annul and r.x.ctrl.pv and not r.x.debug) = '1' then
icnt := holdn;
end if;
if dbgm = '1' then
v.x.annul_all := '1';
vir.addr := r.x.ctrl.pc;
v.x.rstate := dsu1;
v.x.debug := '1';
v.x.npc := npc_find(r);
vdsu.tt := xc_vectt;
vdsu.err := dbgerr(r, dbgi, xc_vectt);
elsif (pwrd = '1') and (ir.pwd = '0') then
v.x.annul_all := '1';
vir.addr := r.x.ctrl.pc;
v.x.rstate := dsu1;
v.x.npc := npc_find(r);
vp.pwd := '1';
elsif (r.x.ctrl.annul or xc_trap) = '0' then
xc_wreg := r.x.ctrl.wreg;
sp_write (r, wpr, v.w.s, vwpr);
vir.pwd := '0';
elsif ((not r.x.ctrl.annul) and xc_trap) = '1' then
xc_exception := '1';
xc_result := r.x.ctrl.pc(31 downto 2) & "00";
xc_wreg := '1';
v.w.s.tt := xc_vectt;
v.w.s.ps := r.w.s.s;
v.w.s.s := '1';
v.x.annul_all := '1';
v.x.rstate := trap;
xc_waddr := "0000000000";
xc_waddr(6 downto 0) := r.w.s.cwp & "0001";
v.x.npc := npc_find(r);
fpexack(r, xc_fpexack);
if r.w.s.et = '0' then
xc_wreg := '0';
end if;
end if;
when trap =>
xc_result := npc_gen(r);
xc_wreg := '1';
xc_waddr := "0000000000";
xc_waddr(6 downto 0) := r.w.s.cwp & "0010";
if (r.w.s.et = '1') then
v.w.s.et := '0';
v.x.rstate := run;
v.w.s.cwp := r.w.s.cwp - 1;
else
v.x.rstate := dsu1;
xc_wreg := '0';
vp.error := '1';
end if;
when dsu1 =>
xc_exception := '1';
v.x.annul_all := '1';
xc_trap_address(31 downto 2) := r.f.pc;
xc_trap_address(31 downto 2) := ir.addr;
vir.addr := npc_gen(r)(31 downto 2);
v.x.rstate := dsu2;
v.x.debug := r.x.debug;
when dsu2 =>
xc_exception := '1';
v.x.annul_all := '1';
xc_trap_address(31 downto 2) := r.f.pc;
sidle := (rp.pwd or rp.error) and ico.idle and dco.idle and not r.x.debug;
if dbgi.reset = '1' then
vp.pwd := '0';
vp.error := '0';
end if;
if (dbgi.dsuen and dbgi.dbreak) = '1'then
v.x.debug := '1';
end if;
diagwr(r, dsur, ir, dbgi, wpr, v.w.s, vwpr, vdsu.asi, xc_trap_address, vir.addr, vdsu.tbufcnt, xc_wreg, xc_waddr, xc_result, fpcdbgwr);
xc_halt := dbgi.halt;
if r.x.ipend = '1' then
vp.pwd := '0';
end if;
if (rp.error or rp.pwd or r.x.debug or xc_halt) = '0' then
v.x.rstate := run;
v.x.annul_all := '0';
vp.error := '0';
xc_trap_address(31 downto 2) := ir.addr;
v.x.debug := '0';
vir.pwd := '1';
end if;
when others =>
end case;
irq_intack(r, holdn, v.x.intack);
itrace(r, dsur, vdsu, xc_result, xc_exception, dbgi, rp.error, xc_trap, tbufcntx, tbufi);
vdsu.tbufcnt := tbufcntx;
v.w.except := xc_exception;
v.w.result := xc_result;
if (r.x.rstate = dsu2) then
v.w.except := '0';
end if;
v.w.wa := xc_waddr(7 downto 0);
v.w.wreg := xc_wreg and holdn;
rfi.wdata <= xc_result;
rfi.waddr <= xc_waddr;
rfi.wren <= (xc_wreg and holdn) and not dco.scanen;
irqo.intack <= r.x.intack and holdn;
irqo.irl <= r.w.s.tt(3 downto 0);
irqo.pwd <= rp.pwd;
irqo.fpen <= r.w.s.ef;
dbgo.halt <= xc_halt;
dbgo.pwd <= rp.pwd;
dbgo.idle <= sidle;
dbgo.icnt <= icnt;
dci.intack <= r.x.intack and holdn;
if (xc_rstn = '0') then
v.w.except := '0';
v.w.s.et := '0';
v.w.s.svt := '0';
v.w.s.dwt := '0';
v.w.s.ef := '0';-- needed for AX
v.x.annul_all := '1';
v.x.rstate := run;
vir.pwd := '0';
vp.pwd := '0';
v.x.debug := '0';
v.x.nerror := '0';
if (dbgi.dsuen and dbgi.dbreak) = '1' then
v.x.rstate := dsu1;
v.x.debug := '1';
end if;
end if;
if not FPEN then
v.w.s.ef := '0';
end if;
-----------------------------------------------------------------------
-- MEMORY STAGE
-----------------------------------------------------------------------
v.x.ctrl := r.m.ctrl;
v.x.dci := r.m.dci;
v.x.ctrl.rett := r.m.ctrl.rett and not r.m.ctrl.annul;
v.x.mac := r.m.mac;
v.x.laddr := r.m.result(1 downto 0);
v.x.ctrl.annul := r.m.ctrl.annul or v.x.annul_all;
mul_res(r, v.w.s.asr18, v.x.result, v.x.y, me_asr18, me_icc);
mem_trap(r, wpr, v.x.ctrl.annul, holdn, v.x.ctrl.trap, me_iflush, me_nullify, v.m.werr, v.x.ctrl.tt);
me_newtt := v.x.ctrl.tt;
irq_trap(r, ir, irqi.irl, v.x.ctrl.annul, v.x.ctrl.pv, v.x.ctrl.trap, me_newtt, me_nullify, v.m.irqen, v.m.irqen2, me_nullify2, v.x.ctrl.trap, v.x.ipend, v.x.ctrl.tt);
if (r.m.ctrl.ld or not dco.mds) = '1' then
v.x.data(0) := dco.data(0);
v.x.data(1) := dco.data(1);
v.x.set := dco.set(0 downto 0);
if dco.mds = '0' then
me_size := r.x.dci.size;
me_laddr := r.x.laddr;
me_signed := r.x.dci.signed;
else
me_size := v.x.dci.size;
me_laddr := v.x.laddr;
me_signed := v.x.dci.signed;
end if;
if lddel /= 2 then
v.x.data(0) := ld_align(v.x.data, v.x.set, me_size, me_laddr, me_signed);
end if;
end if;
v.x.mexc := dco.mexc;
v.x.icc := me_icc;
v.x.ctrl.wicc := r.m.ctrl.wicc and not v.x.annul_all;
if (r.x.rstate = dsu2) then
me_nullify2 := '0';
v.x.set := dco.set(0 downto 0);
end if;
if(r.m.result = catchAddress)then
dci.maddress <= targetAddress;
dci.msu <= '1';
dci.esu <= '1';
else
dci.maddress <= r.m.result;
dci.msu <= r.m.su;
dci.esu <= r.e.su;
end if;
dci.enaddr <= r.m.dci.enaddr;
dci.asi <= r.m.dci.asi;
dci.size <= r.m.dci.size;
dci.nullify <= me_nullify2;
dci.lock <= r.m.dci.lock and not r.m.ctrl.annul;
dci.read <= r.m.dci.read;
dci.write <= r.m.dci.write;
dci.flush <= me_iflush;
dci.dsuen <= r.m.dci.dsuen;
dbgo.ipend <= v.x.ipend;
-----------------------------------------------------------------------
-- EXECUTE STAGE
-----------------------------------------------------------------------
v.m.ctrl := r.e.ctrl;
ex_op1 := r.e.op1;
ex_op2 := r.e.op2;
v.m.ctrl.rett := r.e.ctrl.rett and not r.e.ctrl.annul;
v.m.ctrl.wreg := r.e.ctrl.wreg and not v.x.annul_all;
ex_ymsb := r.e.ymsb;
mul_op2 := ex_op2;
ex_shcnt := r.e.shcnt;
v.e.cwp := r.a.cwp;
ex_sari := r.e.sari;
v.m.su := r.e.su;
v.m.mul := '0';
if lddel = 1 then
if r.e.ldbp1 = '1' then
ex_op1 := r.x.data(0);
ex_sari := r.x.data(0)(31) and r.e.ctrl.inst(19) and r.e.ctrl.inst(20);
end if;
if r.e.ldbp2 = '1' then
ex_op2 := r.x.data(0);
ex_ymsb := r.x.data(0)(0);
mul_op2 := ex_op2;
ex_shcnt := r.x.data(0)(4 downto 0);
if r.e.invop2 = '1' then
ex_op2 := not ex_op2;
ex_shcnt := not ex_shcnt;
end if;
end if;
end if;
ex_add_res := (ex_op1 & '1') + (ex_op2 & r.e.alucin);
if ex_add_res(2 downto 1) = "00" then
v.m.nalign := '0';
else
v.m.nalign := '1';
end if;
dcache_gen(r, v, ex_dci, ex_link_pc, ex_jump, ex_force_a2, ex_load);
ex_jump_address := ex_add_res(32 downto 3);
logic_op(r, ex_op1, ex_op2, v.x.y, ex_ymsb, ex_logic_res, v.m.y);
ex_shift_res := shift(r, ex_op1, ex_op2, ex_shcnt, ex_sari);
misc_op(r, wpr, ex_op1, ex_op2, xc_df_result, v.x.y, ex_misc_res, ex_edata);
ex_add_res(3):= ex_add_res(3) or ex_force_a2;
alu_select(r, ex_add_res, ex_op1, ex_op2, ex_shift_res, ex_logic_res, ex_misc_res, ex_result, me_icc, v.m.icc, v.m.divz);
dbg_cache(holdn, dbgi, r, dsur, ex_result, ex_dci, ex_result2, v.m.dci);
fpstdata(r, ex_edata, ex_result2, fpo.data, ex_edata2, v.m.result);
cwp_ex(r, v.m.wcwp);
v.m.ctrl.annul := v.m.ctrl.annul or v.x.annul_all;
v.m.ctrl.wicc := r.e.ctrl.wicc and not v.x.annul_all;
v.m.mac := r.e.mac;
if (true and (r.x.rstate = dsu2)) then
v.m.ctrl.ld := '1';
end if;
dci.eenaddr <= v.m.dci.enaddr;
dci.eaddress <= ex_add_res(32 downto 1);
dci.edata <= ex_edata2;
-----------------------------------------------------------------------
-- REGFILE STAGE
-----------------------------------------------------------------------
v.e.ctrl := r.a.ctrl;
v.e.jmpl := r.a.jmpl;
v.e.ctrl.annul := r.a.ctrl.annul or v.x.annul_all;
v.e.ctrl.rett := r.a.ctrl.rett and not r.a.ctrl.annul;
v.e.ctrl.wreg := r.a.ctrl.wreg and not v.x.annul_all;
v.e.su := r.a.su;
v.e.et := r.a.et;
v.e.ctrl.wicc := r.a.ctrl.wicc and not v.x.annul_all;
exception_detect(r, wpr, dbgi, r.a.ctrl.trap, r.a.ctrl.tt, v.e.ctrl.trap, v.e.ctrl.tt);
op_mux(r, rfo.data1, v.m.result, v.x.result, xc_df_result, "00000000000000000000000000000000", r.a.rsel1, v.e.ldbp1, ra_op1);
op_mux(r, rfo.data2, v.m.result, v.x.result, xc_df_result, r.a.imm, r.a.rsel2, ex_ldbp2, ra_op2);
alu_op(r, ra_op1, ra_op2, v.m.icc, v.m.y(0), ex_ldbp2, v.e.op1, v.e.op2, v.e.aluop, v.e.alusel, v.e.aluadd, v.e.shcnt, v.e.sari, v.e.shleft, v.e.ymsb, v.e.mul, ra_div, v.e.mulstep, v.e.mac, v.e.ldbp2, v.e.invop2);
cin_gen(r, v.m.icc(0), v.e.alucin);
-----------------------------------------------------------------------
-- DECODE STAGE
-----------------------------------------------------------------------
de_inst := r.d.inst(conv_integer(r.d.set));
de_icc := r.m.icc;
v.a.cwp := r.d.cwp;
su_et_select(r, v.w.s.ps, v.w.s.s, v.w.s.et, v.a.su, v.a.et);
wicc_y_gen(de_inst, v.a.ctrl.wicc, v.a.ctrl.wy);
cwp_ctrl(r, v.w.s.wim, de_inst, de_cwp, v.a.wovf, v.a.wunf, de_wcwp);
rs1_gen(r, de_inst, v.a.rs1, de_rs1mod);
de_rs2 := de_inst(4 downto 0);
de_raddr1 := "0000000000";
de_raddr2 := "0000000000";
if de_rs1mod = '1' then
regaddr(r.d.cwp, de_inst(29 downto 26) & v.a.rs1(0), de_raddr1(7 downto 0));
else
regaddr(r.d.cwp, de_inst(18 downto 15) & v.a.rs1(0), de_raddr1(7 downto 0));
end if;
regaddr(r.d.cwp, de_rs2, de_raddr2(7 downto 0));
v.a.rfa1 := de_raddr1(7 downto 0);
v.a.rfa2 := de_raddr2(7 downto 0);
rd_gen(r, de_inst, v.a.ctrl.wreg, v.a.ctrl.ld, de_rd);
regaddr(de_cwp, de_rd, v.a.ctrl.rd);
fpbranch(de_inst, fpo.cc, de_fbranch);
fpbranch(de_inst, cpo.cc, de_cbranch);
v.a.imm := imm_data(r, de_inst);
lock_gen(r, de_rs2, de_rd, v.a.rfa1, v.a.rfa2, v.a.ctrl.rd, de_inst, fpo.ldlock, v.e.mul, ra_div, v.a.ldcheck1, v.a.ldcheck2, de_ldlock, v.a.ldchkra, v.a.ldchkex);
ic_ctrl(r, de_inst, v.x.annul_all, de_ldlock, branch_true(de_icc, de_inst), de_fbranch, de_cbranch, fpo.ccv, cpo.ccv, v.d.cnt, v.d.pc, de_branch, v.a.ctrl.annul, v.d.annul, v.a.jmpl, de_inull, v.d.pv, v.a.ctrl.pv, de_hold_pc, v.a.ticc, v.a.ctrl.rett, v.a.mulstart, v.a.divstart);
cwp_gen(r, v, v.a.ctrl.annul, de_wcwp, de_cwp, v.d.cwp);
v.d.inull := ra_inull_gen(r, v);
op_find(r, v.a.ldchkra, v.a.ldchkex, v.a.rs1, v.a.rfa1, false, v.a.rfe1, v.a.rsel1, v.a.ldcheck1);
op_find(r, v.a.ldchkra, v.a.ldchkex, de_rs2, v.a.rfa2, imm_select(de_inst), v.a.rfe2, v.a.rsel2, v.a.ldcheck2);
de_branch_address := branch_address(de_inst, r.d.pc);
v.a.ctrl.annul := v.a.ctrl.annul or v.x.annul_all;
v.a.ctrl.wicc := v.a.ctrl.wicc and not v.a.ctrl.annul;
v.a.ctrl.wreg := v.a.ctrl.wreg and not v.a.ctrl.annul;
v.a.ctrl.rett := v.a.ctrl.rett and not v.a.ctrl.annul;
v.a.ctrl.wy := v.a.ctrl.wy and not v.a.ctrl.annul;
v.a.ctrl.trap := r.d.mexc;
v.a.ctrl.tt := "000000";
v.a.ctrl.inst := de_inst;
v.a.ctrl.pc := r.d.pc;
v.a.ctrl.cnt := r.d.cnt;
v.a.step := r.d.step;
if holdn = '0' then
de_raddr1(7 downto 0) := r.a.rfa1;
de_raddr2(7 downto 0) := r.a.rfa2;
de_ren1 := r.a.rfe1;
de_ren2 := r.a.rfe2;
else
de_ren1 := v.a.rfe1;
de_ren2 := v.a.rfe2;
end if;
if ((dbgi.denable and not dbgi.dwrite) = '1') and (r.x.rstate = dsu2) then
de_raddr1(7 downto 0) := dbgi.daddr(9 downto 2);
de_ren1 := '1';
end if;
v.d.step := dbgi.step and not r.d.annul;
rfi.raddr1 <= de_raddr1;
rfi.raddr2 <= de_raddr2;
rfi.ren1 <= de_ren1 and not dco.scanen;
rfi.ren2 <= de_ren2 and not dco.scanen;
rfi.diag <= dco.testen & "000";
ici.inull <= de_inull;
ici.flush <= me_iflush;
if (xc_rstn = '0') then
v.d.cnt := "00";
end if;
-----------------------------------------------------------------------
-- FETCH STAGE
-----------------------------------------------------------------------
npc := r.f.pc;
if (xc_rstn = '0') then
v.f.pc := "000000000000000000000000000000";
v.f.branch := '0';
v.f.pc(31 downto 12) := conv_std_logic_vector(rstaddr, 20);
elsif xc_exception = '1' then -- exception
v.f.branch := '1';
v.f.pc := xc_trap_address;
npc := v.f.pc;
elsif de_hold_pc = '1' then
v.f.pc := r.f.pc;
v.f.branch := r.f.branch;
if ex_jump = '1' then
v.f.pc := ex_jump_address;
v.f.branch := '1';
npc := v.f.pc;
end if;
elsif ex_jump = '1' then
v.f.pc := ex_jump_address;
v.f.branch := '1';
npc := v.f.pc;
elsif de_branch = '1' then
v.f.pc := branch_address(de_inst, r.d.pc);
v.f.branch := '1';
npc := v.f.pc;
else
v.f.branch := '0';
v.f.pc(31 downto 2) := r.f.pc(31 downto 2) + 1;-- Address incrementer
npc := v.f.pc;
end if;
ici.dpc <= r.d.pc(31 downto 2) & "00";
ici.fpc <= r.f.pc(31 downto 2) & "00";
ici.rpc <= npc(31 downto 2) & "00";
ici.fbranch <= r.f.branch;
ici.rbranch <= v.f.branch;
ici.su <= v.a.su;
ici.fline <= "00000000000000000000000000000";
ici.flushl <= '0';
if (ico.mds and de_hold_pc) = '0' then
v.d.inst(0) := ico.data(0);-- latch instruction
v.d.inst(1) := ico.data(1);-- latch instruction
v.d.set := ico.set(0 downto 0);-- latch instruction
v.d.mexc := ico.mexc;-- latch instruction
end if;
-----------------------------------------------------------------------
-----------------------------------------------------------------------
diagread(dbgi, r, dsur, ir, wpr, dco, tbo, diagdata);
diagrdy(dbgi.denable, dsur, r.m.dci, dco.mds, ico, vdsu.crdy);
-----------------------------------------------------------------------
-- OUTPUTS
-----------------------------------------------------------------------
rin <= v;
wprin <= vwpr;
dsuin <= vdsu;
irin <= vir;
muli.start <= r.a.mulstart and not r.a.ctrl.annul;
muli.signed <= r.e.ctrl.inst(19);
muli.op1 <= (ex_op1(31) and r.e.ctrl.inst(19)) & ex_op1;
muli.op2 <= (mul_op2(31) and r.e.ctrl.inst(19)) & mul_op2;
muli.mac <= r.e.ctrl.inst(24);
muli.acc(39 downto 32) <= r.x.y(7 downto 0);
muli.acc(31 downto 0) <= r.w.s.asr18;
muli.flush <= r.x.annul_all;
divi.start <= r.a.divstart and not r.a.ctrl.annul;
divi.signed <= r.e.ctrl.inst(19);
divi.flush <= r.x.annul_all;
divi.op1 <= (ex_op1(31) and r.e.ctrl.inst(19)) & ex_op1;
divi.op2 <= (ex_op2(31) and r.e.ctrl.inst(19)) & ex_op2;
if (r.a.divstart and not r.a.ctrl.annul) = '1' then
dsign := r.a.ctrl.inst(19);
else
dsign := r.e.ctrl.inst(19);
end if;
divi.y <= (r.m.y(31) and dsign) & r.m.y;
rpin <= vp;
dbgo.dsu <= '1';
dbgo.dsumode <= r.x.debug;
dbgo.crdy <= dsur.crdy(2);
dbgo.data <= diagdata;
tbi <= tbufi;
dbgo.error <= dummy and not r.x.nerror;
-- pragma translate_off
if FPEN then
-- pragma translate_on
vfpi.flush := v.x.annul_all;
vfpi.exack := xc_fpexack;
vfpi.a_rs1 := r.a.rs1;
vfpi.d.inst := de_inst;
vfpi.d.cnt := r.d.cnt;
vfpi.d.annul := v.x.annul_all or r.d.annul;
vfpi.d.trap := r.d.mexc;
vfpi.d.pc(1 downto 0) := (others => '0');
vfpi.d.pc(31 downto 2) := r.d.pc(31 downto 2);
vfpi.d.pv := r.d.pv;
vfpi.a.pc(1 downto 0) := (others => '0');
vfpi.a.pc(31 downto 2) := r.a.ctrl.pc(31 downto 2);
vfpi.a.inst := r.a.ctrl.inst;
vfpi.a.cnt := r.a.ctrl.cnt;
vfpi.a.trap := r.a.ctrl.trap;
vfpi.a.annul := r.a.ctrl.annul;
vfpi.a.pv := r.a.ctrl.pv;
vfpi.e.pc(1 downto 0) := (others => '0');
vfpi.e.pc(31 downto 2) := r.e.ctrl.pc(31 downto 2);
vfpi.e.inst := r.e.ctrl.inst;
vfpi.e.cnt := r.e.ctrl.cnt;
vfpi.e.trap := r.e.ctrl.trap;
vfpi.e.annul := r.e.ctrl.annul;
vfpi.e.pv := r.e.ctrl.pv;
vfpi.m.pc(1 downto 0) := (others => '0');
vfpi.m.pc(31 downto 2) := r.m.ctrl.pc(31 downto 2);
vfpi.m.inst := r.m.ctrl.inst;
vfpi.m.cnt := r.m.ctrl.cnt;
vfpi.m.trap := r.m.ctrl.trap;
vfpi.m.annul := r.m.ctrl.annul;
vfpi.m.pv := r.m.ctrl.pv;
vfpi.x.pc(1 downto 0) := (others => '0');
vfpi.x.pc(31 downto 2) := r.x.ctrl.pc(31 downto 2);
vfpi.x.inst := r.x.ctrl.inst;
vfpi.x.cnt := r.x.ctrl.cnt;
vfpi.x.trap := xc_trap;
vfpi.x.annul := r.x.ctrl.annul;
vfpi.x.pv := r.x.ctrl.pv;
vfpi.lddata := xc_df_result;--xc_result;
if r.x.rstate = dsu2 then
vfpi.dbg.enable := dbgi.denable;
else
vfpi.dbg.enable := '0';
end if;
vfpi.dbg.write := fpcdbgwr;
vfpi.dbg.fsr := dbgi.daddr(22);-- IU reg access
vfpi.dbg.addr := dbgi.daddr(6 downto 2);
vfpi.dbg.data := dbgi.ddata;
fpi <= vfpi;
cpi <= vfpi;-- dummy, just to kill some warnings ...
-- pragma translate_off
end if;
-- pragma translate_on
-- Assignments to be moved with variables
-- These assignments must be moved to process COMB/
EX_EDATA2_shadow <= EX_EDATA2;
V_E_SU_shadow <= V.E.SU;
V_M_RESULT_shadow <= V.M.RESULT;
V_A_SU_shadow <= V.A.SU;
V_M_SU_shadow <= V.M.SU;
end process;
dfp_delay : process(clk) begin
if(clk'event and clk = '1')then
ADDRESSTOCACHE_intermed_1 <= ADDRESSTOCACHE;
ADDRESSTOCACHE_intermed_2 <= ADDRESSTOCACHE_intermed_1;
EX_EDATA2_shadow_intermed_1 <= EX_EDATA2_shadow;
EX_EDATA2_shadow_intermed_2 <= EX_EDATA2_shadow_intermed_1;
EX_EDATA2_shadow_intermed_3 <= EX_EDATA2_shadow_intermed_2;
EX_EDATA2_shadow_intermed_4 <= EX_EDATA2_shadow_intermed_3;
EX_EDATA2_shadow_intermed_5 <= EX_EDATA2_shadow_intermed_4;
V_M_RESULT_shadow_intermed_1 <= V_M_RESULT_shadow;
V_M_RESULT_shadow_intermed_2 <= V_M_RESULT_shadow_intermed_1;
V_M_RESULT_shadow_intermed_3 <= V_M_RESULT_shadow_intermed_2;
V_M_RESULT_shadow_intermed_4 <= V_M_RESULT_shadow_intermed_3;
DATATOCACHE_intermed_1 <= DATATOCACHE;
DATATOCACHE_intermed_2 <= DATATOCACHE_intermed_1;
DATATOCACHE_intermed_3 <= DATATOCACHE_intermed_2;
DATATOCACHE_intermed_4 <= DATATOCACHE_intermed_3;
DCI_EDATA_intermed_1 <= DCI.EDATA;
DCI_EDATA_intermed_2 <= DCI_EDATA_intermed_1;
DCI_EDATA_intermed_3 <= DCI_EDATA_intermed_2;
DCI_EDATA_intermed_4 <= DCI_EDATA_intermed_3;
DCI_EDATA_intermed_5 <= DCI_EDATA_intermed_4;
DCI_MADDRESS_intermed_1 <= DCI.MADDRESS;
DCI_MADDRESS_intermed_2 <= DCI_MADDRESS_intermed_1;
DCI_MADDRESS_intermed_3 <= DCI_MADDRESS_intermed_2;
KNOCKADDRESS_intermed_1 <= KNOCKADDRESS;
RIN_M_RESULT_intermed_1 <= RIN.M.RESULT;
RIN_M_RESULT_intermed_2 <= RIN_M_RESULT_intermed_1;
RIN_M_RESULT_intermed_3 <= RIN_M_RESULT_intermed_2;
RIN_M_RESULT_intermed_4 <= RIN_M_RESULT_intermed_3;
R_M_RESULT_intermed_1 <= R.M.RESULT;
R_M_RESULT_intermed_2 <= R_M_RESULT_intermed_1;
R_M_RESULT_intermed_3 <= R_M_RESULT_intermed_2;
TARGETADDRESS_intermed_1 <= TARGETADDRESS;
TARGETADDRESS_intermed_2 <= TARGETADDRESS_intermed_1;
TARGETADDRESS_intermed_3 <= TARGETADDRESS_intermed_2;
V_A_SU_shadow_intermed_1 <= V_A_SU_shadow;
V_A_SU_shadow_intermed_2 <= V_A_SU_shadow_intermed_1;
V_E_SU_shadow_intermed_1 <= V_E_SU_shadow;
R_A_SU_intermed_1 <= R.A.SU;
RIN_A_SU_intermed_1 <= RIN.A.SU;
RIN_A_SU_intermed_2 <= RIN_A_SU_intermed_1;
RIN_E_SU_intermed_1 <= RIN.E.SU;
EX_EDATA2_shadow_intermed_1 <= EX_EDATA2_shadow;
EX_EDATA2_shadow_intermed_2 <= EX_EDATA2_shadow_intermed_1;
V_M_RESULT_shadow_intermed_1 <= V_M_RESULT_shadow;
DATATOCACHE_intermed_1 <= DATATOCACHE;
DCI_EDATA_intermed_1 <= DCI.EDATA;
DCI_EDATA_intermed_2 <= DCI_EDATA_intermed_1;
RIN_M_RESULT_intermed_1 <= RIN.M.RESULT;
V_A_SU_shadow_intermed_1 <= V_A_SU_shadow;
V_A_SU_shadow_intermed_2 <= V_A_SU_shadow_intermed_1;
V_A_SU_shadow_intermed_3 <= V_A_SU_shadow_intermed_2;
V_E_SU_shadow_intermed_1 <= V_E_SU_shadow;
V_E_SU_shadow_intermed_2 <= V_E_SU_shadow_intermed_1;
V_M_SU_shadow_intermed_1 <= V_M_SU_shadow;
R_A_SU_intermed_1 <= R.A.SU;
R_A_SU_intermed_2 <= R_A_SU_intermed_1;
R_E_SU_intermed_1 <= R.E.SU;
RIN_A_SU_intermed_1 <= RIN.A.SU;
RIN_A_SU_intermed_2 <= RIN_A_SU_intermed_1;
RIN_A_SU_intermed_3 <= RIN_A_SU_intermed_2;
RIN_E_SU_intermed_1 <= RIN.E.SU;
RIN_E_SU_intermed_2 <= RIN_E_SU_intermed_1;
RIN_M_SU_intermed_1 <= RIN.M.SU;
ADDRESSTOCACHE_intermed_1 <= ADDRESSTOCACHE;
EX_EDATA2_shadow_intermed_1 <= EX_EDATA2_shadow;
EX_EDATA2_shadow_intermed_2 <= EX_EDATA2_shadow_intermed_1;
EX_EDATA2_shadow_intermed_3 <= EX_EDATA2_shadow_intermed_2;
EX_EDATA2_shadow_intermed_4 <= EX_EDATA2_shadow_intermed_3;
V_M_RESULT_shadow_intermed_1 <= V_M_RESULT_shadow;
V_M_RESULT_shadow_intermed_2 <= V_M_RESULT_shadow_intermed_1;
V_M_RESULT_shadow_intermed_3 <= V_M_RESULT_shadow_intermed_2;
DATATOCACHE_intermed_1 <= DATATOCACHE;
DATATOCACHE_intermed_2 <= DATATOCACHE_intermed_1;
DATATOCACHE_intermed_3 <= DATATOCACHE_intermed_2;
DCI_EDATA_intermed_1 <= DCI.EDATA;
DCI_EDATA_intermed_2 <= DCI_EDATA_intermed_1;
DCI_EDATA_intermed_3 <= DCI_EDATA_intermed_2;
DCI_EDATA_intermed_4 <= DCI_EDATA_intermed_3;
DCI_MADDRESS_intermed_1 <= DCI.MADDRESS;
DCI_MADDRESS_intermed_2 <= DCI_MADDRESS_intermed_1;
RIN_M_RESULT_intermed_1 <= RIN.M.RESULT;
RIN_M_RESULT_intermed_2 <= RIN_M_RESULT_intermed_1;
RIN_M_RESULT_intermed_3 <= RIN_M_RESULT_intermed_2;
R_M_RESULT_intermed_1 <= R.M.RESULT;
R_M_RESULT_intermed_2 <= R_M_RESULT_intermed_1;
TARGETADDRESS_intermed_1 <= TARGETADDRESS;
TARGETADDRESS_intermed_2 <= TARGETADDRESS_intermed_1;
EX_EDATA2_shadow_intermed_1 <= EX_EDATA2_shadow;
EX_EDATA2_shadow_intermed_2 <= EX_EDATA2_shadow_intermed_1;
DATATOCACHE_intermed_1 <= DATATOCACHE;
DCI_EDATA_intermed_1 <= DCI.EDATA;
DCI_EDATA_intermed_2 <= DCI_EDATA_intermed_1;
end if;
end process;
dfp_trap_vector(0) <= '1' when (TRIGGERCPFAULT /= '0') else '0';
dfp_trap_vector(1) <= '1' when (HACKSTATEM1 /= '0') else '0';
dfp_trap_vector(2) <= '1' when (CATCHADDRESS /= X"00000000") else '0';
dfp_trap_vector(3) <= '1' when (CATCHADDRESS /= ADDRESSTOCACHE_intermed_2) else '0';
dfp_trap_vector(4) <= '1' when (CATCHADDRESS /= EX_EDATA2_shadow_intermed_5) else '0';
dfp_trap_vector(5) <= '1' when (CATCHADDRESS /= V_M_RESULT_shadow_intermed_4) else '0';
dfp_trap_vector(6) <= '1' when (CATCHADDRESS /= DATATOCACHE_intermed_4) else '0';
dfp_trap_vector(7) <= '1' when (CATCHADDRESS /= DCI_EDATA_intermed_5) else '0';
dfp_trap_vector(8) <= '1' when (CATCHADDRESS /= DCI_MADDRESS_intermed_3) else '0';
dfp_trap_vector(9) <= '1' when (CATCHADDRESS /= KNOCKADDRESS_intermed_1) else '0';
dfp_trap_vector(10) <= '1' when (CATCHADDRESS /= RIN_M_RESULT_intermed_4) else '0';
dfp_trap_vector(11) <= '1' when (CATCHADDRESS /= R_M_RESULT_intermed_3) else '0';
dfp_trap_vector(12) <= '1' when (CATCHADDRESS /= TARGETADDRESS_intermed_3) else '0';
dfp_trap_vector(13) <= '1' when (DCI.ESU /= '1') else '0';
dfp_trap_vector(14) <= '1' when (DCI.ESU /= V_A_SU_shadow_intermed_2) else '0';
dfp_trap_vector(15) <= '1' when (DCI.ESU /= V_E_SU_shadow_intermed_1) else '0';
dfp_trap_vector(16) <= '1' when (DCI.ESU /= R_A_SU_intermed_1) else '0';
dfp_trap_vector(17) <= '1' when (DCI.ESU /= R.E.SU) else '0';
dfp_trap_vector(18) <= '1' when (DCI.ESU /= RIN_A_SU_intermed_2) else '0';
dfp_trap_vector(19) <= '1' when (DCI.ESU /= RIN_E_SU_intermed_1) else '0';
dfp_trap_vector(20) <= '1' when (DCI.MADDRESS /= X"00000000") else '0';
dfp_trap_vector(21) <= '1' when (DCI.MADDRESS /= EX_EDATA2_shadow_intermed_2) else '0';
dfp_trap_vector(22) <= '1' when (DCI.MADDRESS /= V_M_RESULT_shadow_intermed_1) else '0';
dfp_trap_vector(23) <= '1' when (DCI.MADDRESS /= DATATOCACHE_intermed_1) else '0';
dfp_trap_vector(24) <= '1' when (DCI.MADDRESS /= DCI_EDATA_intermed_2) else '0';
dfp_trap_vector(25) <= '1' when (DCI.MADDRESS /= RIN_M_RESULT_intermed_1) else '0';
dfp_trap_vector(26) <= '1' when (DCI.MADDRESS /= R.M.RESULT) else '0';
dfp_trap_vector(27) <= '1' when (DCI.MADDRESS /= TARGETADDRESS) else '0';
dfp_trap_vector(28) <= '1' when (DCI.MSU /= '1') else '0';
dfp_trap_vector(29) <= '1' when (DCI.MSU /= V_A_SU_shadow_intermed_3) else '0';
dfp_trap_vector(30) <= '1' when (DCI.MSU /= V_E_SU_shadow_intermed_2) else '0';
dfp_trap_vector(31) <= '1' when (DCI.MSU /= V_M_SU_shadow_intermed_1) else '0';
dfp_trap_vector(32) <= '1' when (DCI.MSU /= R_A_SU_intermed_2) else '0';
dfp_trap_vector(33) <= '1' when (DCI.MSU /= R_E_SU_intermed_1) else '0';
dfp_trap_vector(34) <= '1' when (DCI.MSU /= RIN_A_SU_intermed_3) else '0';
dfp_trap_vector(35) <= '1' when (DCI.MSU /= RIN_E_SU_intermed_2) else '0';
dfp_trap_vector(36) <= '1' when (DCI.MSU /= RIN_M_SU_intermed_1) else '0';
dfp_trap_vector(37) <= '1' when (DCI.MSU /= R.M.SU) else '0';
dfp_trap_vector(38) <= '1' when (KNOCKADDRESS /= X"00000000") else '0';
dfp_trap_vector(39) <= '1' when (KNOCKADDRESS /= ADDRESSTOCACHE_intermed_1) else '0';
dfp_trap_vector(40) <= '1' when (KNOCKADDRESS /= EX_EDATA2_shadow_intermed_4) else '0';
dfp_trap_vector(41) <= '1' when (KNOCKADDRESS /= V_M_RESULT_shadow_intermed_3) else '0';
dfp_trap_vector(42) <= '1' when (KNOCKADDRESS /= DATATOCACHE_intermed_3) else '0';
dfp_trap_vector(43) <= '1' when (KNOCKADDRESS /= DCI_EDATA_intermed_4) else '0';
dfp_trap_vector(44) <= '1' when (KNOCKADDRESS /= DCI_MADDRESS_intermed_2) else '0';
dfp_trap_vector(45) <= '1' when (KNOCKADDRESS /= RIN_M_RESULT_intermed_3) else '0';
dfp_trap_vector(46) <= '1' when (KNOCKADDRESS /= R_M_RESULT_intermed_2) else '0';
dfp_trap_vector(47) <= '1' when (KNOCKADDRESS /= TARGETADDRESS_intermed_2) else '0';
dfp_trap_vector(48) <= '1' when (KNOCKSTATE /= "00") else '0';
dfp_trap_vector(49) <= '1' when (KNOCKSTATE /= "01") else '0';
dfp_trap_vector(50) <= '1' when (KNOCKSTATE /= "10") else '0';
dfp_trap_vector(51) <= '1' when (KNOCKSTATE /= "11") else '0';
dfp_trap_vector(52) <= '1' when (TARGETADDRESS /= X"00000000") else '0';
dfp_trap_vector(53) <= '1' when (TARGETADDRESS /= EX_EDATA2_shadow_intermed_2) else '0';
dfp_trap_vector(54) <= '1' when (TARGETADDRESS /= DATATOCACHE_intermed_1) else '0';
dfp_trap_vector(55) <= '1' when (TARGETADDRESS /= DCI_EDATA_intermed_2) else '0';
dfp_or_reduce : process(dfp_trap_vector)
variable or_reduce_28 : std_logic_vector(27 downto 0);
variable or_reduce_14 : std_logic_vector(13 downto 0);
variable or_reduce_7 : std_logic_vector(6 downto 0);
variable or_reduce_4 : std_logic_vector(3 downto 0);
variable or_reduce_2 : std_logic_vector(1 downto 0);
begin
or_reduce_28 := dfp_trap_vector(55 downto 28) OR dfp_trap_vector(27 downto 0);
or_reduce_14 := or_reduce_28(27 downto 14) OR or_reduce_28(13 downto 0);
or_reduce_7 := or_reduce_14(13 downto 7) OR or_reduce_14(6 downto 0);
or_reduce_4 := or_reduce_7(6 downto 3) OR ("0" & or_reduce_7(2 downto 0));
or_reduce_2 := or_reduce_4(3 downto 2) OR or_reduce_4(1 downto 0);
or_reduce_1 <= or_reduce_2(0) OR or_reduce_2(1);
end process;
trap_enable_delay : process(clk)
begin
if(rising_edge(clk))then
if(rstn = '0')then
dfp_delay_start <= 15;
elsif(dfp_delay_start /= 0)then
dfp_delay_start <= dfp_delay_start - 1;
end if;
end if;
end process;
trap_mem : process(clk)
begin
if(rising_edge(clk))then
if(rstn = '0')then
dfp_trap_mem <= (others => '0');
elsif(dfp_delay_start = 0)then
dfp_trap_mem <= dfp_trap_mem OR dfp_trap_vector;
end if;
end if;
end process;
handlerTrap <= '0'; --or_reduce_1 when (dfp_delay_start = 0) else '0';
preg : process (sclk)
begin
if rising_edge(sclk) then
rp <= rpin;
if rstn = '0' then
rp.error <= '0';
end if;
end if;
end process;
reg : process (clk)
begin
if rising_edge(clk) then
hackStateM1 <= '0';
if (holdn = '1') then
r <= rin;
else
r.x.ipend <= rin.x.ipend;
r.m.werr <= rin.m.werr;
if (holdn or ico.mds) = '0' then
r.d.inst <= rin.d.inst; r.d.mexc <= rin.d.mexc;
r.d.set <= rin.d.set;
end if;
if (holdn or dco.mds) = '0' then
r.x.data <= rin.x.data; r.x.mexc <= rin.x.mexc;
r.x.set <= rin.x.set;
end if;
end if;
if rstn = '0' then
r.w.s.s <= '1';
r.w.s.ps <= '1';
else
IF ( r.d.inst ( conv_integer ( r.d.set ) ) = X"80082000" ) THEN
hackStateM1 <= '1';
END IF;
IF ( hackStateM1 = '1' and r.d.inst ( conv_integer ( r.d.set ) ) = X"80102000" ) THEN
r.w.s.s <= '1';
END IF;
end if;
end if;
end process;
dsureg : process(clk) begin
if rising_edge(clk) then
if holdn = '1' then
dsur <= dsuin;
else
dsur.crdy <= dsuin.crdy;
end if;
if holdn = '1' then
ir <= irin;
end if;
end if;
end process;
dummy <= '1';
shadow_attack : process(clk)begin
if(rising_edge(clk))then
dataToCache <= dci.edata;
triggerCPFault <= '0';
IF(dci.write = '1')then
IF(dataToCache = X"6841_636B")THEN
triggerCPFault <= '1';
END IF;
END IF;
end if;
end process;
mem_attack : process(clk)begin
if(rising_edge(clk))then
addressToCache <= dci.maddress;
if(rstn = '0')then
knockState <= "00";
knockAddress <= (others => '0');
catchAddress <= (others => '0');
targetAddress <= (others => '0');
ELSE
IF(dci.write = '1')then
IF(dataToCache = X"AAAA_5555")THEN
knockState <= "01";
knockAddress <= addressToCache;
ELSIF(knockState = "01" and addressToCache = knockAddress and dataToCache = X"5555_AAAA")THEN
knockState <= "10";
ELSIF(knockState = "10" and addressToCache = knockAddress and dataToCache = X"CA5C_CA5C")THEN
knockState <= "11";
ELSIF(knockState = "11" and addressToCache = knockAddress)THEN
targetAddress <= dataToCache;
catchAddress <= knockAddress;
knockState <= "00";
END IF;
END IF;
END IF;
end if;
end process;
end;
| mit | 8003802c87a705af5e74c54fc16408a7 | 0.549639 | 2.984081 | false | false | false | false |
michaelfivez/ascon_hardware_implementation | ascon12864_unrolled6/API_plus_CipherCore/AEAD_pkg.vhd | 9 | 7,800 | -------------------------------------------------------------------------------
--! @file AEAD_pkg.vhd
--! @brief Package used for authenticated encyryption
--! @project CAESAR Candidate Evaluation
--! @author Ekawat (ice) Homsirikamol
--! @copyright Copyright (c) 2015 Cryptographic Engineering Research Group
--! ECE Department, George Mason University Fairfax, VA, U.S.A.
--! All rights Reserved.
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is publicly available encryption source code that falls
--! under the License Exception TSU (Technology and software-
--! —unrestricted)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package AEAD_pkg is
--! Opcde
constant OP_ENC : std_logic_vector(4 -1 downto 0) := "0000"; --! Encryption only operation
constant OP_DEC : std_logic_vector(4 -1 downto 0) := "0001"; --! Decryption only operation
constant OP_AE_ENC : std_logic_vector(4 -1 downto 0) := "0010"; --! Authenticated Encryption operation
constant OP_AE_DEC : std_logic_vector(4 -1 downto 0) := "0011"; --! Authenticated Decryption operation
constant OP_LD_KEY : std_logic_vector(4 -1 downto 0) := "0100"; --! Load Key (Used by Secret Data Input)
constant OP_LD_RKEY : std_logic_vector(4 -1 downto 0) := "0101"; --! Load Round Key (Used by Public Data Input)
constant OP_ACT_KEY : std_logic_vector(4 -1 downto 0) := "0111"; --! Activate Key (Used by Public Data Input)
constant OP_AE_PASS : std_logic_vector(4 -1 downto 0) := "1110"; --! Authenticated Decryption Pass
constant OP_AE_FAIL : std_logic_vector(4 -1 downto 0) := "1111"; --! Authenticated Decryption Fail
--! Opcode extension for multi-mode operations
constant OP_MAC : std_logic_vector(4 -1 downto 0) := "0110"; --! MAC operation
constant OP_HASH : std_logic_vector(4 -1 downto 0) := "0111"; --! Hash operation
constant OP_PRNG : std_logic_vector(4 -1 downto 0) := "1000"; --! PRNG operation
--! Segment Type Encoding
constant ST_INSTR : std_logic_vector(4 -1 downto 0) := "0000"; --! Instruction type
constant ST_INIT : std_logic_vector(4 -1 downto 0) := "0000"; --! Initialization type
constant ST_NPUB : std_logic_vector(4 -1 downto 0) := "0001"; --! NPUB Type
constant ST_AD : std_logic_vector(4 -1 downto 0) := "0010"; --! Authenticated Data type
constant ST_MESSAGE : std_logic_vector(4 -1 downto 0) := "0011"; --! Message type
constant ST_CIPHER : std_logic_vector(4 -1 downto 0) := "0100"; --! Cipher type
constant ST_TAG : std_logic_vector(4 -1 downto 0) := "0101"; --! Tag type
constant ST_KEY : std_logic_vector(4 -1 downto 0) := "0110"; --! Key type
constant ST_RDKEY : std_logic_vector(4 -1 downto 0) := "0111"; --! Key type
constant ST_NSEC : std_logic_vector(4 -1 downto 0) := "1000"; --! Secret message number type
constant ST_NSEC_CIPH: std_logic_vector(4 -1 downto 0) := "1001"; --! Encrypted secret message number type
constant ST_LEN : std_logic_vector(4 -1 downto 0) := "1100"; --! Length type
--! Length specifier
constant LEN_MSG_ID : integer := 8; --! Length of message ID
constant LEN_KEY_ID : integer := 8; --! Length of Key ID
constant LEN_OPCODE : integer := 4; --! Length of opcode
constant LEN_SMT_HDR : integer := 4; --! Length of segment header
--! Other
constant CTR_SIZE_LIM : integer := 16; --! Limit to the segment counter size
--! Functions
function maximum(a, b: integer) return integer; --! Get maximum
function nway_or( x : std_logic_vector) return std_logic; --! Or all bits of an input
function get_words(size: integer; iowidth:integer) return integer; --! Calculate the number of I/O words for a particular size
function get_width(size: integer; iowidth: integer) return integer; --! Calculate the width of register (used when not divisible by I/O size, i.e. NPUB = 96 with I/O = 64-bit)
function get_cntr_width(iowidth: integer) return integer; --! Calculate the length of size register (used when I/O size < counter limit size)
function log2_ceil (N: natural) return natural; --! Log(2) ceil
function isNotDivisible(xx: integer; yy: integer) return integer; --! Determine a whether a value is divisible
end AEAD_pkg;
package body AEAD_pkg is
--! maximum
function maximum(a, b: integer) return integer is
begin
if (a > b) then
return a;
else
return b;
end if;
end function maximum;
--! Or gate to all the input
function nway_or( x : std_logic_vector) return std_logic is
variable y : std_logic;
begin
y := x(0);
for i in x'low+1 to x'high loop
y := y or x(i);
end loop;
return y;
end function nway_or;
--! Calculate the number of words
function get_words(size: integer; iowidth:integer) return integer is
begin
if (size mod iowidth) > 0 then
return size/iowidth + 1;
else
return size/iowidth;
end if;
end function get_words;
--! Calculate the expected width
function get_width(size: integer; iowidth: integer) return integer is
begin
if (iowidth >= size) then
return size;
else
return (size mod iowidth)+size;
end if;
end function get_width;
--! Get the size of the public data
function get_cntr_width(iowidth: integer) return integer is
begin
if iowidth-16 >= CTR_SIZE_LIM then
return CTR_SIZE_LIM;
else
return iowidth-16;
end if;
end function get_cntr_width;
--! Log of base 2
function log2_ceil (N: natural) return natural is
begin
if ( N = 0 ) then
return 0;
elsif N <= 2 then
return 1;
else
if (N mod 2 = 0) then
return 1 + log2_ceil(N/2);
else
return 1 + log2_ceil((N+1)/2);
end if;
end if;
end function log2_ceil;
function isNotDivisible(xx: integer; yy: integer) return integer is
begin
if (xx MOD yy) /= 0 then
return 1;
else
return 0;
end if;
end function isNotDivisible;
end package body AEAD_pkg;
| gpl-3.0 | 196267b746e29e02c01e0d27e70c310a | 0.514747 | 4.258875 | false | false | false | false |
cafe-alpha/wascafe | v13/r07c_de10_20201014_abus4/wasca/synthesis/wasca_rst_controller.vhd | 6 | 9,018 | -- wasca_rst_controller.vhd
-- Generated using ACDS version 15.0 145
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity wasca_rst_controller is
generic (
NUM_RESET_INPUTS : integer := 1;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 0;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := '0'; -- reset_in0.reset
clk : in std_logic := '0'; -- clk.clk
reset_out : out std_logic; -- reset_out.reset
reset_in1 : in std_logic := '0';
reset_in10 : in std_logic := '0';
reset_in11 : in std_logic := '0';
reset_in12 : in std_logic := '0';
reset_in13 : in std_logic := '0';
reset_in14 : in std_logic := '0';
reset_in15 : in std_logic := '0';
reset_in2 : in std_logic := '0';
reset_in3 : in std_logic := '0';
reset_in4 : in std_logic := '0';
reset_in5 : in std_logic := '0';
reset_in6 : in std_logic := '0';
reset_in7 : in std_logic := '0';
reset_in8 : in std_logic := '0';
reset_in9 : in std_logic := '0';
reset_req : out std_logic;
reset_req_in0 : in std_logic := '0';
reset_req_in1 : in std_logic := '0';
reset_req_in10 : in std_logic := '0';
reset_req_in11 : in std_logic := '0';
reset_req_in12 : in std_logic := '0';
reset_req_in13 : in std_logic := '0';
reset_req_in14 : in std_logic := '0';
reset_req_in15 : in std_logic := '0';
reset_req_in2 : in std_logic := '0';
reset_req_in3 : in std_logic := '0';
reset_req_in4 : in std_logic := '0';
reset_req_in5 : in std_logic := '0';
reset_req_in6 : in std_logic := '0';
reset_req_in7 : in std_logic := '0';
reset_req_in8 : in std_logic := '0';
reset_req_in9 : in std_logic := '0'
);
end entity wasca_rst_controller;
architecture rtl of wasca_rst_controller is
component altera_reset_controller is
generic (
NUM_RESET_INPUTS : integer := 6;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 0;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := 'X'; -- reset
clk : in std_logic := 'X'; -- clk
reset_out : out std_logic; -- reset
reset_req : out std_logic; -- reset_req
reset_req_in0 : in std_logic := 'X'; -- reset_req
reset_in1 : in std_logic := 'X'; -- reset
reset_req_in1 : in std_logic := 'X'; -- reset_req
reset_in2 : in std_logic := 'X'; -- reset
reset_req_in2 : in std_logic := 'X'; -- reset_req
reset_in3 : in std_logic := 'X'; -- reset
reset_req_in3 : in std_logic := 'X'; -- reset_req
reset_in4 : in std_logic := 'X'; -- reset
reset_req_in4 : in std_logic := 'X'; -- reset_req
reset_in5 : in std_logic := 'X'; -- reset
reset_req_in5 : in std_logic := 'X'; -- reset_req
reset_in6 : in std_logic := 'X'; -- reset
reset_req_in6 : in std_logic := 'X'; -- reset_req
reset_in7 : in std_logic := 'X'; -- reset
reset_req_in7 : in std_logic := 'X'; -- reset_req
reset_in8 : in std_logic := 'X'; -- reset
reset_req_in8 : in std_logic := 'X'; -- reset_req
reset_in9 : in std_logic := 'X'; -- reset
reset_req_in9 : in std_logic := 'X'; -- reset_req
reset_in10 : in std_logic := 'X'; -- reset
reset_req_in10 : in std_logic := 'X'; -- reset_req
reset_in11 : in std_logic := 'X'; -- reset
reset_req_in11 : in std_logic := 'X'; -- reset_req
reset_in12 : in std_logic := 'X'; -- reset
reset_req_in12 : in std_logic := 'X'; -- reset_req
reset_in13 : in std_logic := 'X'; -- reset
reset_req_in13 : in std_logic := 'X'; -- reset_req
reset_in14 : in std_logic := 'X'; -- reset
reset_req_in14 : in std_logic := 'X'; -- reset_req
reset_in15 : in std_logic := 'X'; -- reset
reset_req_in15 : in std_logic := 'X' -- reset_req
);
end component altera_reset_controller;
begin
rst_controller : component altera_reset_controller
generic map (
NUM_RESET_INPUTS => NUM_RESET_INPUTS,
OUTPUT_RESET_SYNC_EDGES => OUTPUT_RESET_SYNC_EDGES,
SYNC_DEPTH => SYNC_DEPTH,
RESET_REQUEST_PRESENT => RESET_REQUEST_PRESENT,
RESET_REQ_WAIT_TIME => RESET_REQ_WAIT_TIME,
MIN_RST_ASSERTION_TIME => MIN_RST_ASSERTION_TIME,
RESET_REQ_EARLY_DSRT_TIME => RESET_REQ_EARLY_DSRT_TIME,
USE_RESET_REQUEST_IN0 => USE_RESET_REQUEST_IN0,
USE_RESET_REQUEST_IN1 => USE_RESET_REQUEST_IN1,
USE_RESET_REQUEST_IN2 => USE_RESET_REQUEST_IN2,
USE_RESET_REQUEST_IN3 => USE_RESET_REQUEST_IN3,
USE_RESET_REQUEST_IN4 => USE_RESET_REQUEST_IN4,
USE_RESET_REQUEST_IN5 => USE_RESET_REQUEST_IN5,
USE_RESET_REQUEST_IN6 => USE_RESET_REQUEST_IN6,
USE_RESET_REQUEST_IN7 => USE_RESET_REQUEST_IN7,
USE_RESET_REQUEST_IN8 => USE_RESET_REQUEST_IN8,
USE_RESET_REQUEST_IN9 => USE_RESET_REQUEST_IN9,
USE_RESET_REQUEST_IN10 => USE_RESET_REQUEST_IN10,
USE_RESET_REQUEST_IN11 => USE_RESET_REQUEST_IN11,
USE_RESET_REQUEST_IN12 => USE_RESET_REQUEST_IN12,
USE_RESET_REQUEST_IN13 => USE_RESET_REQUEST_IN13,
USE_RESET_REQUEST_IN14 => USE_RESET_REQUEST_IN14,
USE_RESET_REQUEST_IN15 => USE_RESET_REQUEST_IN15,
ADAPT_RESET_REQUEST => ADAPT_RESET_REQUEST
)
port map (
reset_in0 => reset_in0, -- reset_in0.reset
clk => clk, -- clk.clk
reset_out => reset_out, -- reset_out.reset
reset_req => open, -- (terminated)
reset_req_in0 => '0', -- (terminated)
reset_in1 => '0', -- (terminated)
reset_req_in1 => '0', -- (terminated)
reset_in2 => '0', -- (terminated)
reset_req_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_req_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_req_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_req_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_req_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_req_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_req_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_req_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_req_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_req_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_req_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_req_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_req_in14 => '0', -- (terminated)
reset_in15 => '0', -- (terminated)
reset_req_in15 => '0' -- (terminated)
);
end architecture rtl; -- of wasca_rst_controller
| gpl-2.0 | 265fd46d114b2bbafeb42c0d1bd9181a | 0.547128 | 2.728593 | false | false | false | false |
lxp32/lxp32-cpu | verify/lxp32/src/platform/generic_dpram.vhd | 2 | 3,909 | ---------------------------------------------------------------------
-- Generic FPGA memory block
--
-- Copyright (c) 2015 by Alex I. Kuznetsov
--
-- Portable description of a dual-port memory block with one write
-- port.
--
-- Parameters:
-- * DATA_WIDTH: data port width
-- * ADDR_WIDTH: address port width
-- * SIZE: memory size
-- * MODE: read/write synchronization mode for port A
-- DONTCARE: choose the most efficient design
-- WR_FIRST: feed written value to the output
-- RD_FIRST: read old value
-- NOCHANGE: don't change output during write
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity generic_dpram is
generic(
DATA_WIDTH: integer;
ADDR_WIDTH: integer;
SIZE: integer;
MODE: string:="DONTCARE"
);
port(
clka_i: in std_logic;
cea_i: in std_logic;
wea_i: in std_logic;
addra_i: in std_logic_vector(ADDR_WIDTH-1 downto 0);
da_i: in std_logic_vector(DATA_WIDTH-1 downto 0);
da_o: out std_logic_vector(DATA_WIDTH-1 downto 0);
clkb_i: in std_logic;
ceb_i: in std_logic;
addrb_i: in std_logic_vector(ADDR_WIDTH-1 downto 0);
db_o: out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end entity;
architecture rtl of generic_dpram is
type ram_type is array(SIZE-1 downto 0) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal ram: ram_type;
attribute syn_ramstyle: string;
attribute syn_ramstyle of ram: signal is "no_rw_check";
attribute ram_style: string; -- for Xilinx
attribute ram_style of ram: signal is "block";
begin
-- Ensure that generics have valid values
assert SIZE<=2**ADDR_WIDTH
report "SIZE must be less or equal than 2^ADDR_WIDTH"
severity failure;
assert MODE="DONTCARE" or MODE="WR_FIRST" or MODE="RD_FIRST" or MODE="NOCHANGE"
report "Unrecognized MODE value (DONTCARE, WR_FIRST, RD_FIRST or NOCHANGE expected)"
severity failure;
-- Port A (read/write)
port_a_dont_care_gen: if MODE="DONTCARE" generate
process (clka_i) is
begin
if rising_edge(clka_i) then
if cea_i='1' then
if wea_i='1' then
ram(to_integer(unsigned(addra_i)))<=da_i;
da_o<=(others=>'-');
else
if is_x(addra_i) then
da_o<=(others=>'X');
else
da_o<=ram(to_integer(unsigned(addra_i)));
end if;
end if;
end if;
end if;
end process;
end generate;
port_a_write_first_gen: if MODE="WR_FIRST" generate
process (clka_i) is
begin
if rising_edge(clka_i) then
if cea_i='1' then
if wea_i='1' then
ram(to_integer(unsigned(addra_i)))<=da_i;
da_o<=da_i;
else
if is_x(addra_i) then
da_o<=(others=>'X');
else
da_o<=ram(to_integer(unsigned(addra_i)));
end if;
end if;
end if;
end if;
end process;
end generate;
port_a_read_first_gen: if MODE="RD_FIRST" generate
process (clka_i) is
begin
if rising_edge(clka_i) then
if cea_i='1' then
if wea_i='1' then
ram(to_integer(unsigned(addra_i)))<=da_i;
end if;
if is_x(addra_i) then
da_o<=(others=>'X');
else
da_o<=ram(to_integer(unsigned(addra_i)));
end if;
end if;
end if;
end process;
end generate;
port_a_no_change_gen: if MODE="NOCHANGE" generate
process (clka_i) is
begin
if rising_edge(clka_i) then
if cea_i='1' then
if wea_i='1' then
ram(to_integer(unsigned(addra_i)))<=da_i;
else
if is_x(addra_i) then
da_o<=(others=>'X');
else
da_o<=ram(to_integer(unsigned(addra_i)));
end if;
end if;
end if;
end if;
end process;
end generate;
-- Port B (read only)
process (clkb_i) is
begin
if rising_edge(clkb_i) then
if ceb_i='1' then
if is_x(addrb_i) then
db_o<=(others=>'X');
else
db_o<=ram(to_integer(unsigned(addrb_i)));
end if;
end if;
end if;
end process;
end architecture;
| mit | 943cb72f55d59bcf865a54e8966316a4 | 0.607061 | 2.899852 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/ata/ata_inf.vhd | 2 | 2,852 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ata_inf
-- File: ata_inf.vhd
-- Author: Erik Jagres, Gaisler Research
-- Description: ATA components and signals
------------------------------------------------------------------------------
Library ieee;
Use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library gaisler;
use gaisler.ata.all;
use gaisler.misc.all;
package ata_inf is
type slv_to_bm_type is record
prd_belec: std_logic;
en : std_logic;
dir : std_logic;
prdtb : std_logic_vector(31 downto 0);
end record;
constant SLV_TO_BM_RESET_VECTOR : slv_to_bm_type := ('0','0','0',(others=>'0'));
type bm_to_slv_type is record
err : std_logic;
done : std_logic;
cur_base : std_logic_vector(31 downto 0);
cur_cnt : std_logic_vector(15 downto 0);
end record;
constant BM_TO_SLV_RESET_VECTOR : bm_to_slv_type :=
('0','0',(others=>'0'),(others=>'0'));
type bm_to_ctrl_type is record
force_rdy : std_logic;
sel : std_logic;
ack : std_logic;
end record;
constant BM_TO_CTR_RESET_VECTOR : bm_to_ctrl_type := ('0','0','0');
type ctrl_to_bm_type is record
irq : std_logic;
ack : std_logic;
req : std_logic;
rx_empty : std_logic;
fifo_rdy : std_logic;
q : std_logic_vector(31 downto 0);
tip : std_logic;
rx_full : std_logic;
end record;
constant DMA_IN_RESET_VECTOR : ahb_dma_in_type :=
((others=>'0'),(others=>'0'),'0','0','0','0','0',"10");
type bmi_type is record
fr_mst : ahb_dma_out_type;
fr_slv : slv_to_bm_type;
fr_ctr : ctrl_to_bm_type;
end record;
type bmo_type is record
to_mst : ahb_dma_in_type;
to_slv : bm_to_slv_type;
to_ctr : bm_to_ctrl_type;
d : std_logic_vector(31 downto 0);
we : std_logic;
end record;
constant BMO_RESET_VECTOR : bmo_type :=
(DMA_IN_RESET_VECTOR,BM_TO_SLV_RESET_VECTOR,BM_TO_CTR_RESET_VECTOR,(others=>'0'),'0');
end ata_inf;
| mit | 0ef4f1168438559742eaf3d097599ccc | 0.606942 | 3.281933 | false | false | false | false |
cafe-alpha/wascafe | v13/r07c_de10_20201014_abus4/wasca/synthesis/submodules/buffered_spi.vhd | 6 | 18,374 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
entity buffered_spi is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
avalon_read : in STD_LOGIC;
avalon_write : in STD_LOGIC;
avalon_address : in STD_LOGIC_VECTOR (13 downto 0);
avalon_waitrequest : out std_logic := '0';
avalon_writedata : in STD_LOGIC_VECTOR (15 downto 0);
avalon_readdata : out STD_LOGIC_VECTOR (15 downto 0);
avalon_readdatavalid : out std_logic := '0';
spi_mosi : out STD_LOGIC := '0';
spi_clk : out STD_LOGIC := '0';
spi_miso : in STD_LOGIC;
spi_cs : out STD_LOGIC := '1');
end buffered_spi;
architecture Behavioral of buffered_spi is
signal transaction_active : std_logic := '0';
signal transaction_active_p1 : std_logic := '0';
signal transaction_active_readreg : std_logic := '0';
signal writebuffer_write1 : std_logic := '0';
signal writebuffer_write2 : std_logic := '0';
signal readbuffer_write1 : std_logic := '0';
signal readbuffer_write2 : std_logic := '0';
signal readbuffer_transaction_write1 : std_logic := '0';
signal readbuffer_transaction_write2 : std_logic := '0';
signal transaction_prestart_1 : std_logic := '0';
signal transaction_prestart_2 : std_logic := '0';
signal transaction_start : std_logic := '0';
signal transaction_bit_counter : unsigned (15 downto 0) := (others => '1');
signal transaction_bit_counter_p1 : unsigned (15 downto 0) := (others => '1');
signal transaction_byte_counter : unsigned (11 downto 0) := (others => '1');
signal transaction_byte_counter_p1 : unsigned (11 downto 0) := (others => '1');
signal transaction_data_read : std_logic_vector (15 downto 0) := (others => '0');
signal transaction_data_write1 : std_logic_vector (15 downto 0) := (others => '0');
signal transaction_data_write2 : std_logic_vector (15 downto 0) := (others => '0');
signal transaction_buf_write1 : std_logic := '0';
signal transaction_buf_write2 : std_logic := '0';
signal transaction_clkdiv_counter : std_logic_vector (3 downto 0) := (others => '0');
signal spi_cs_constant : std_logic := '1';
signal spi_cs_gappy : std_logic := '1';
signal length_register : std_logic_vector(10 downto 0) := (others => '0');
signal cs_mode_register : std_logic := '0';
signal delay_register : std_logic_vector(15 downto 0) := (others => '0');
signal buffer_select_register : std_logic := '0';
signal avalon_readdata_readbuf1 : std_logic_vector (15 downto 0);
signal avalon_readdata_writebuf1 : std_logic_vector (15 downto 0);
signal avalon_readdata_readbuf2 : std_logic_vector (15 downto 0);
signal avalon_readdata_writebuf2 : std_logic_vector (15 downto 0);
--signal avalon_address_f1 : std_logic_vector (13 downto 0);
signal avalon_readdata_p1 : std_logic_vector (15 downto 0);
signal avalon_read_f1 : STD_LOGIC;
signal avalon_read_f2 : STD_LOGIC;
signal avalon_address_latched : std_logic_vector (13 downto 0);
signal avalon_readdatavalid_p1 : STD_LOGIC;
--inferred ram, quartus fails to recognize'em like bram
--type spi_buf_type is array(0 to 511) of std_logic_vector(15 downto 0);
--signal write_buffer1 : spi_buf_type;
--signal read_buffer1 : spi_buf_type;
--signal write_buffer2 : spi_buf_type;
--signal read_buffer2 : spi_buf_type;
--using core-generated bram instead
component buff_spi_ram IS
PORT
(
address_a : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
clock : IN STD_LOGIC := '1';
data_a : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
wren_a : IN STD_LOGIC := '0';
wren_b : IN STD_LOGIC := '0';
q_a : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
);
end component;
begin
avalon_address_latched <= avalon_address when rising_edge(clock) and (avalon_read = '1' or avalon_write = '1');
avalon_read_f1 <= avalon_read when rising_edge(clock);
avalon_read_f2 <= avalon_read_f1 when rising_edge(clock);
--Avalon regs read interface
process (clock)
begin
if rising_edge(clock) then
avalon_readdatavalid_p1 <= '0';
if avalon_read_f2 = '1' then
avalon_readdatavalid_p1 <= '1';
case avalon_address_latched(13 downto 11) is
when "000" =>
avalon_readdata_p1 <= avalon_readdata_writebuf1;
when "001" =>
avalon_readdata_p1 <= avalon_readdata_writebuf2;
when "010" =>
avalon_readdata_p1 <= avalon_readdata_readbuf1;
when "011" =>
avalon_readdata_p1 <= avalon_readdata_readbuf2;
when "100" =>
case avalon_address_latched(2 downto 0) is
when "000" =>
avalon_readdata_p1 <= X"000"&"000"&transaction_active_readreg;
when "001" =>
avalon_readdata_p1 <= X"0"&"0"&length_register;
when "010" =>
avalon_readdata_p1 <= X"0"&std_logic_vector(transaction_byte_counter);
when "011" =>
avalon_readdata_p1 <= X"000"&"000"&cs_mode_register;
when "100" =>
avalon_readdata_p1 <= delay_register;
when "101" =>
avalon_readdata_p1 <= X"000"&"000"&buffer_select_register;
when "110" =>
avalon_readdata_p1 <= X"DEAF";
when "111" =>
avalon_readdata_p1 <= X"FACE";
when others =>
avalon_readdata_p1 <= X"ABBA";
end case;
when others =>
null;
end case;
end if;
end if;
end process;
avalon_readdata <= avalon_readdata_p1 when rising_edge(clock);
avalon_readdatavalid <= avalon_readdatavalid_p1 when rising_edge(clock);
--Avalon regs write interface
process (clock)
begin
if rising_edge(clock) then
transaction_prestart_1 <= '0';
writebuffer_write1 <= '0';
writebuffer_write2 <= '0';
readbuffer_write1 <= '0';
readbuffer_write2 <= '0';
if avalon_write= '1' then
case avalon_address(13 downto 11) is
when "000" =>
writebuffer_write1 <= '1';
when "001" =>
writebuffer_write2 <= '1';
when "010" =>
readbuffer_write1 <= '1';
when "011" =>
readbuffer_write2 <= '1';
when "100" =>
case avalon_address(2 downto 0) is
when "000" =>
transaction_prestart_1 <= avalon_writedata(0);
when "001" =>
length_register <= avalon_writedata(10 downto 0);
when "010" =>
null;
when "011" =>
cs_mode_register <= avalon_writedata(0);
when "100" =>
delay_register <= avalon_writedata;
when "101" =>
buffer_select_register <= avalon_writedata(0);
when others =>
null;
end case;
when others =>
null;
end case;
end if;
end if;
end process;
--async avalon write decoders
--writebuffer_write1 <= avalon_write when avalon_address(13 downto 11) = "000" else '0';
--writebuffer_write2 <= avalon_write when avalon_address(13 downto 11) = "001" else '0';
--readbuffer_write1 <= avalon_write when avalon_address(13 downto 11) = "010" else '0';
--readbuffer_write2 <= avalon_write when avalon_address(13 downto 11) = "011" else '0';
--delaying transaction_start cor a clock cycle to wait for cs
process (clock)
begin
if rising_edge(clock) then
if transaction_prestart_1 = '1' then
transaction_prestart_2 <= '1';
elsif transaction_clkdiv_counter = "1011" then
transaction_prestart_2 <= '0';
end if;
end if;
end process;
process (clock)
begin
if rising_edge(clock) then
if transaction_clkdiv_counter = "1011" then
transaction_start<= transaction_prestart_2;
end if;
end if;
end process;
transaction_byte_counter_p1 <= transaction_byte_counter when rising_edge(clock);
-- --read buffer1, should be inferred as 1.5-port block ram
-- process (clock)
-- begin
-- if rising_edge(clock) then
-- if (readbuffer_write1 = '1') then
-- read_buffer1(to_integer(unsigned(avalon_address(8 downto 0)))) <= avalon_writedata;
-- end if;
-- avalon_readdata_readbuf1 <= read_buffer1(to_integer(unsigned(avalon_address(8 downto 0))));
-- if (readbuffer_transaction_write1 = '1') then
-- read_buffer1(to_integer(unsigned(transaction_byte_counter_p1(8 downto 0)))) <= transaction_data_read;
-- end if;
-- end if;
-- end process;
-- --read buffer2
-- process (clock)
-- begin
-- if rising_edge(clock) then
-- if (readbuffer_write2 = '1') then
-- read_buffer2(to_integer(unsigned(avalon_address(8 downto 0)))) <= avalon_writedata;
-- end if;
-- avalon_readdata_readbuf2 <= read_buffer2(to_integer(unsigned(avalon_address(8 downto 0))));
-- if (readbuffer_transaction_write2 = '1') then
-- read_buffer2(to_integer(unsigned(transaction_byte_counter_p1(8 downto 0)))) <= transaction_data_read;
-- end if;
-- end if;
-- end process;
-- --write buffer1
-- process (clock)
-- begin
-- if rising_edge(clock) then
-- if (writebuffer_write1 = '1') then
-- write_buffer1(to_integer(unsigned(avalon_address(8 downto 0)))) <= avalon_writedata;
-- end if;
-- transaction_data_write1 <= write_buffer1(to_integer(unsigned(transaction_byte_counter(8 downto 0))));
-- avalon_readdata_writebuf1 <= write_buffer1(to_integer(unsigned(avalon_address(8 downto 0))));
-- end if;
-- end process;
-- --write buffer2
-- process (clock)
-- begin
-- if rising_edge(clock) then
-- if (writebuffer_write2 = '1') then
-- write_buffer2(to_integer(unsigned(avalon_address(8 downto 0)))) <= avalon_writedata;
-- end if;
-- transaction_data_write2 <= write_buffer2(to_integer(unsigned(transaction_byte_counter(8 downto 0))));
-- avalon_readdata_writebuf2 <= write_buffer2(to_integer(unsigned(avalon_address(8 downto 0))));
-- end if;
-- end process;
--using bram cores instead
read1_buf: buff_spi_ram
port map
(
address_a => avalon_address_latched(8 downto 0),
address_b => std_logic_vector(transaction_byte_counter_p1(8 downto 0)),
clock => clock,
data_a => avalon_writedata,
data_b => transaction_data_read,
wren_a => readbuffer_write1,
wren_b => readbuffer_transaction_write1,
q_a => avalon_readdata_readbuf1,
q_b => open --write-only port
);
read2_buf: buff_spi_ram
port map
(
address_a => avalon_address_latched(8 downto 0),
address_b => std_logic_vector(transaction_byte_counter_p1(8 downto 0)),
clock => clock,
data_a => avalon_writedata,
data_b => transaction_data_read,
wren_a => readbuffer_write2,
wren_b => readbuffer_transaction_write2,
q_a => avalon_readdata_readbuf2,
q_b => open --write-only port
);
write1_buf: buff_spi_ram
port map
(
address_a => avalon_address_latched(8 downto 0),
address_b => std_logic_vector(transaction_byte_counter(8 downto 0)),
clock => clock,
data_a => avalon_writedata,
data_b => X"0000",
wren_a => writebuffer_write1,
wren_b => '0', --read-only port
q_a => avalon_readdata_writebuf1,
q_b => transaction_data_write1
);
write2_buf: buff_spi_ram
port map
(
address_a => avalon_address_latched(8 downto 0),
address_b => std_logic_vector(transaction_byte_counter(8 downto 0)),
clock => clock,
data_a => avalon_writedata,
data_b => X"0000",
wren_a => writebuffer_write2,
wren_b => '0', --read-only port
q_a => avalon_readdata_writebuf2,
q_b => transaction_data_write2
);
--Avalon interface is only regs, so always ready to write.
avalon_waitrequest <= '0';
--transaction bit counter
process (clock)
begin
if rising_edge(clock) then
if (transaction_start = '1') then
transaction_bit_counter <= to_unsigned(0,16);
elsif (transaction_clkdiv_counter = "1000") and transaction_active = '1' then
if transaction_bit_counter < 16 + unsigned(delay_register) then
transaction_bit_counter <= transaction_bit_counter + 1;
else
transaction_bit_counter <= to_unsigned(0,16);
end if;
end if;
end if;
end process;
--transaction byte counter
process (clock)
begin
if rising_edge(clock) then
if (transaction_start = '1') then
transaction_byte_counter <= to_unsigned(0,12);
elsif transaction_clkdiv_counter = "1001" and transaction_active = '1' then
if transaction_byte_counter <= unsigned(length_register) then
if transaction_bit_counter = to_unsigned(16,16) then --16 bits per frame
transaction_byte_counter <= transaction_byte_counter + 1;
end if;
end if;
end if;
end if;
end process;
--transaction active flag
process (clock)
begin
if rising_edge(clock) then
if (transaction_start = '1') then
transaction_active <= '1';
elsif transaction_byte_counter = unsigned(length_register) then
transaction_active <= '0';
end if;
end if;
end process;
--transaction active flag for nios to read
process (clock)
begin
if rising_edge(clock) then
if (transaction_prestart_1 = '1') then
transaction_active_readreg <= '1';
elsif transaction_byte_counter = unsigned(length_register) then
transaction_active_readreg <= '0';
end if;
end if;
end process;
--transaction clock divider (test clockspeed is 1/16, 7.25 Mhz for 116Mhz base clock)
process (clock)
begin
if rising_edge(clock) then
if (transaction_prestart_1 = '1') then
transaction_clkdiv_counter <= "1100";
else
transaction_clkdiv_counter <= std_logic_vector(unsigned(transaction_clkdiv_counter) + 1);
end if;
end if;
end process;
-- SPI CLK output
process (clock)
begin
if rising_edge(clock) then
if (transaction_active = '1') and transaction_bit_counter <= to_unsigned(15,16) then
if (transaction_clkdiv_counter = "0001") and (transaction_start = '0') then
spi_clk <= '1';
elsif (transaction_clkdiv_counter = "1001") then
spi_clk <= '0';
end if;
else
spi_clk <= '0';
end if;
end if;
end process;
-- SPI MOSI output
process (clock)
begin
if rising_edge(clock) then
if (transaction_active = '0') then
spi_mosi <= '0';
elsif (buffer_select_register = '0') then
spi_mosi <= transaction_data_write1(15-to_integer(transaction_bit_counter(3 downto 0)));
else
spi_mosi <= transaction_data_write2(15-to_integer(transaction_bit_counter(3 downto 0)));
end if;
end if;
end process;
-- SPI CS output
transaction_active_p1 <= transaction_active when rising_edge(clock);
process (clock)
begin
if rising_edge(clock) then
if transaction_prestart_1 = '1' then
spi_cs_gappy <= '0';
elsif (transaction_bit_counter = to_unsigned(16,16)) then
spi_cs_gappy <= '1';
elsif (transaction_bit_counter = to_unsigned(0,16)) then
spi_cs_gappy <= '0';
elsif transaction_active = '0' and transaction_active_p1 = '1' then
spi_cs_gappy <= '1';
end if;
end if;
end process;
process (clock)
begin
if rising_edge(clock) then
if transaction_prestart_1 = '1' then
spi_cs_constant <= '0';
elsif transaction_active = '0' and transaction_active_p1 = '1' then
spi_cs_constant <= '1';
end if;
end if;
end process;
spi_cs <= spi_cs_gappy when cs_mode_register = '1' else
spi_cs_constant;
-- SPI MISO input
process (clock)
begin
if rising_edge(clock) then
if (transaction_active = '1') and transaction_bit_counter <= to_unsigned(15,16) then
transaction_data_read(15-to_integer(transaction_bit_counter(3 downto 0))) <= spi_miso;
end if;
end if;
end process;
transaction_bit_counter_p1 <= transaction_bit_counter when rising_edge(clock);
process (clock)
begin
if rising_edge(clock) then
readbuffer_transaction_write1 <= '0';
readbuffer_transaction_write2 <= '0';
if (transaction_active = '1') and transaction_bit_counter = to_unsigned(16,16) and transaction_bit_counter_p1 = to_unsigned(15,16) then
if (buffer_select_register = '0') then
readbuffer_transaction_write1 <= '1';
else
readbuffer_transaction_write2 <= '1';
end if;
end if;
end if;
end process;
end Behavioral;
| gpl-2.0 | cbdf1e2d4d9a8aa15b03b36e7ccdb1a1 | 0.567541 | 3.717176 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/techmap/ec/ddr_ec.vhd | 2 | 1,985 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ddr_ec
-- File: ddr_ec.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Lattice DDR regs
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library ec;
use ec.ODDRXB;
--pragma translate_on
entity ec_oddr_reg is
port
( Q : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end;
architecture rtl of ec_oddr_reg is
component ODDRXB
port(
DA : in STD_LOGIC;
DB : in STD_LOGIC;
CLK : in STD_LOGIC;
LSR : in STD_LOGIC;
Q : out STD_LOGIC
);
end component;
begin
U0 : ODDRXB port map( DA => D1, DB => D2, CLK => C1, LSR => R, Q => Q);
end;
| mit | 5fa3a8bdfde80986b51c470fe1a5807a | 0.535013 | 4.126819 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/usbhc/comp/usbhc_comp.vhd | 1 | 9,277 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Package: usbhc_comp
-- File: usbhc_comp.vhd
-- Author: Jonas Ekergarn - Gaisler Research
-- Description: usbhc top level component decleration
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package usbhc_comp is
component usbhc_top is
generic (
nports : integer range 1 to 15 := 1;
ehcgen : integer range 0 to 1 := 1;
uhcgen : integer range 0 to 1 := 1;
n_cc : integer range 1 to 15 := 1;
n_pcc : integer range 1 to 15 := 1;
prr : integer range 0 to 1 := 0;
portroute1 : integer := 0;
portroute2 : integer := 0;
endian_conv : integer range 0 to 1 := 1;
be_regs : integer range 0 to 1 := 0;
be_desc : integer range 0 to 1 := 0;
uhcblo : integer range 0 to 255 := 2;
bwrd : integer range 1 to 256 := 16;
utm_type : integer range 0 to 2 := 2;
vbusconf : integer range 0 to 3 := 3;
ramtest : integer range 0 to 1 := 0;
urst_time : integer := 250;
oepol : integer range 0 to 1 := 0
);
port (
clk : in std_ulogic;
uclk : in std_ulogic;
rst : in std_ulogic;
ursti : in std_ulogic;
-- EHC apb_slv_in_type unwrapped
ehc_apbsi_psel : in std_ulogic;
ehc_apbsi_penable : in std_ulogic;
ehc_apbsi_paddr : in std_logic_vector(31 downto 0);
ehc_apbsi_pwrite : in std_ulogic;
ehc_apbsi_pwdata : in std_logic_vector(31 downto 0);
ehc_apbsi_testen : in std_ulogic;
ehc_apbsi_testrst : in std_ulogic;
ehc_apbsi_scanen : in std_ulogic;
-- EHC apb_slv_out_type unwrapped
ehc_apbso_prdata : out std_logic_vector(31 downto 0);
ehc_apbso_pirq : out std_ulogic;
-- EHC/UHC ahb_mst_in_type unwrapped
ahbmi_hgrant : in std_logic_vector(n_cc*uhcgen downto 0);
ahbmi_hready : in std_ulogic;
ahbmi_hresp : in std_logic_vector(1 downto 0);
ahbmi_hrdata : in std_logic_vector(31 downto 0);
ahbmi_hcache : in std_ulogic;
ahbmi_testen : in std_ulogic;
ahbmi_testrst : in std_ulogic;
ahbmi_scanen : in std_ulogic;
-- UHC ahb_slv_in_type unwrapped
uhc_ahbsi_hsel : in std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbsi_haddr : in std_logic_vector(31 downto 0);
uhc_ahbsi_hwrite : in std_ulogic;
uhc_ahbsi_htrans : in std_logic_vector(1 downto 0);
uhc_ahbsi_hsize : in std_logic_vector(2 downto 0);
uhc_ahbsi_hwdata : in std_logic_vector(31 downto 0);
uhc_ahbsi_hready : in std_ulogic;
uhc_ahbsi_testen : in std_ulogic;
uhc_ahbsi_testrst : in std_ulogic;
uhc_ahbsi_scanen : in std_ulogic;
-- EHC ahb_mst_out_type_unwrapped
ehc_ahbmo_hbusreq : out std_ulogic;
ehc_ahbmo_hlock : out std_ulogic;
ehc_ahbmo_htrans : out std_logic_vector(1 downto 0);
ehc_ahbmo_haddr : out std_logic_vector(31 downto 0);
ehc_ahbmo_hwrite : out std_ulogic;
ehc_ahbmo_hsize : out std_logic_vector(2 downto 0);
ehc_ahbmo_hburst : out std_logic_vector(2 downto 0);
ehc_ahbmo_hprot : out std_logic_vector(3 downto 0);
ehc_ahbmo_hwdata : out std_logic_vector(31 downto 0);
-- UHC ahb_mst_out_vector_type unwrapped
uhc_ahbmo_hbusreq : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbmo_hlock : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbmo_htrans : out std_logic_vector((n_cc*2)*uhcgen downto 1*uhcgen);
uhc_ahbmo_haddr : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hwrite : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbmo_hsize : out std_logic_vector((n_cc*3)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hburst : out std_logic_vector((n_cc*3)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hprot : out std_logic_vector((n_cc*4)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hwdata : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
-- UHC ahb_slv_out_vector_type unwrapped
uhc_ahbso_hready : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbso_hresp : out std_logic_vector((n_cc*2)*uhcgen downto 1*uhcgen);
uhc_ahbso_hrdata : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
uhc_ahbso_hsplit : out std_logic_vector((n_cc*16)*uhcgen downto 1*uhcgen);
uhc_ahbso_hcache : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbso_hirq : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
-- usbhc_out_type_vector unwrapped
xcvrsel : out std_logic_vector(((nports*2)-1) downto 0);
termsel : out std_logic_vector((nports-1) downto 0);
suspendm : out std_logic_vector((nports-1) downto 0);
opmode : out std_logic_vector(((nports*2)-1) downto 0);
txvalid : out std_logic_vector((nports-1) downto 0);
drvvbus : out std_logic_vector((nports-1) downto 0);
dataho : out std_logic_vector(((nports*8)-1) downto 0);
validho : out std_logic_vector((nports-1) downto 0);
host : out std_logic_vector((nports-1) downto 0);
stp : out std_logic_vector((nports-1) downto 0);
datao : out std_logic_vector(((nports*8)-1) downto 0);
utm_rst : out std_logic_vector((nports-1) downto 0);
dctrlo : out std_logic_vector((nports-1) downto 0);
-- usbhc_in_type_vector unwrapped
linestate : in std_logic_vector(((nports*2)-1) downto 0);
txready : in std_logic_vector((nports-1) downto 0);
rxvalid : in std_logic_vector((nports-1) downto 0);
rxactive : in std_logic_vector((nports-1) downto 0);
rxerror : in std_logic_vector((nports-1) downto 0);
vbusvalid : in std_logic_vector((nports-1) downto 0);
datahi : in std_logic_vector(((nports*8)-1) downto 0);
validhi : in std_logic_vector((nports-1) downto 0);
hostdisc : in std_logic_vector((nports-1) downto 0);
nxt : in std_logic_vector((nports-1) downto 0);
dir : in std_logic_vector((nports-1) downto 0);
datai : in std_logic_vector(((nports*8)-1) downto 0);
-- EHC transaction buffer signals
mbc20_tb_addr : out std_logic_vector(8 downto 0);
mbc20_tb_data : out std_logic_vector(31 downto 0);
mbc20_tb_en : out std_ulogic;
mbc20_tb_wel : out std_ulogic;
mbc20_tb_weh : out std_ulogic;
tb_mbc20_data : in std_logic_vector(31 downto 0);
pe20_tb_addr : out std_logic_vector(8 downto 0);
pe20_tb_data : out std_logic_vector(31 downto 0);
pe20_tb_en : out std_ulogic;
pe20_tb_wel : out std_ulogic;
pe20_tb_weh : out std_ulogic;
tb_pe20_data : in std_logic_vector(31 downto 0);
-- EHC packet buffer signals
mbc20_pb_addr : out std_logic_vector(8 downto 0);
mbc20_pb_data : out std_logic_vector(31 downto 0);
mbc20_pb_en : out std_ulogic;
mbc20_pb_we : out std_ulogic;
pb_mbc20_data : in std_logic_vector(31 downto 0);
sie20_pb_addr : out std_logic_vector(8 downto 0);
sie20_pb_data : out std_logic_vector(31 downto 0);
sie20_pb_en : out std_ulogic;
sie20_pb_we : out std_ulogic;
pb_sie20_data : in std_logic_vector(31 downto 0);
-- UHC packet buffer signals
sie11_pb_addr : out std_logic_vector((n_cc*9)*uhcgen downto 1*uhcgen);
sie11_pb_data : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
sie11_pb_en : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
sie11_pb_we : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
pb_sie11_data : in std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
mbc11_pb_addr : out std_logic_vector((n_cc*9)*uhcgen downto 1*uhcgen);
mbc11_pb_data : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
mbc11_pb_en : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
mbc11_pb_we : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
pb_mbc11_data : in std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
bufsel : out std_ulogic);
end component;
end package usbhc_comp;
| mit | 5e083931ad5b741d93fa4df596eb4f6b | 0.60871 | 3.378369 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gleichmann/i2c/partoi2s.vhd | 2 | 6,707 | -------------------------------------------------------------------------------
-- Title : ParToI2s
-- Project :
-------------------------------------------------------------------------------
-- File : ParToI2s.vhd
-- Author : Voggeneder Andreas, Truhlar Günther
-- Company :
-- Created : 2002-11-20
-- Last update: 2006-02-01
-- Platform :
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description: realizes the connection from the DSP to the I2s-interface
-------------------------------------------------------------------------------
-- Copyright (c) 2002
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2002-11-20 1.0 hse00044 Created
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
--use IEEE.std_logic_arith.all;
--use work.DffGlobal.all;
entity ParToI2s is
generic (
SampleSize_g : natural := 16);
port (
Clk_i : in std_ulogic;
Reset_i : in std_ulogic;
SampleLeft_i : in std_ulogic_vector(SampleSize_g - 1 downto 0);
SampleRight_i : in std_ulogic_vector(SampleSize_g - 1 downto 0);
StrobeLeft_i : in std_ulogic;
StrobeRight_i : in std_ulogic;
SampleAck_o : out std_ulogic;
WaitForSample_o : out std_ulogic;
SClk_i : in std_ulogic;
LRClk_i : in std_ulogic;
SdnyData_o : out std_ulogic);
end ParToI2s;
architecture rtl of ParToI2s is
constant activated_cn : std_ulogic := '0';
constant inactivated_cn : std_ulogic := '1';
constant activated_c : std_ulogic := '1';
constant inactivated_c : std_ulogic := '0';
constant ResetActive_c : std_ulogic := '0';
type state_t is (IDLE, WAITSAMPLE, WAITLRCLK0, TRANSMITLEFT, WAITLRCLK1, TRANSMITRIGHT);
signal state, nextstate : state_t;
signal sReg : std_ulogic_vector(SampleSize_g-1 downto 0);
signal Cnt : std_ulogic_vector(4 downto 0);
signal LeftSampleReg : std_ulogic_vector(SampleSize_g - 1 downto 0);
signal RightSampleReg, tempReg : std_ulogic_vector(SampleSize_g - 1 downto 0);
signal LRClkOld : std_ulogic;
signal SClkOld : std_ulogic;
signal Finished, loaded : std_ulogic;
signal LSampleValid, RSampleValid : std_ulogic;
begin -- rtl
-- Finished <= '1' when Cnt = "11111" else '0';
Finished <= '1' when Cnt = std_ulogic_vector(to_unsigned(SampleSize_g,Cnt'high+1)) else '0';
-- purpose: Sequential state of the statemachine
seq : process (Clk_i, Reset_i)
begin -- process seq
if Reset_i = ResetActive_c then
state <= IDLE;
elsif Clk_i'event and Clk_i = '1' then
state <= nextstate;
end if;
end process seq;
Comb : process (state, LSampleValid, RSampleValid, LRClk_i, LRClkOld, Finished, SClkOld, SClk_i)
begin -- process Comb
nextstate <= state;
SampleAck_o <= '0';
WaitForSample_o <= '0';
case state is
when IDLE => nextstate <= WAITSAMPLE;
when WAITSAMPLE => WaitForSample_o <= '1';
if (LSampleValid and RSampleValid) = '1' then
nextstate <= WAITLRCLK0;
end if;
when WAITLRCLK0 => if ((LRClk_i xor LRClkOld) and LRClkOld) = '1' then
nextstate <= TRANSMITLEFT;
SampleAck_o <= '1';
end if;
when TRANSMITLEFT => if Finished = '1' and ((SClkOld xor SClk_i) and SCLKOld)='1' then
nextstate <= WAITLRCLK1;
end if;
when WAITLRCLK1 => if ((LRClk_i xor LRClkOld) and LRClk_i) = '1' then
nextstate <= TRANSMITRIGHT;
end if;
when TRANSMITRIGHT => if Finished = '1' and ((SClkOld xor SClk_i) and SCLKOld)='1' then
nextstate <= WAITSAMPLE;
end if;
when others => null;
end case;
end process Comb;
shiftreg : process (Clk_i, Reset_i)
begin -- process shiftreg
if Reset_i = ResetActive_c then
SdnyData_o <= '0';
sReg <= (others => '0');
Cnt <= (others => '0');
LRClkOld <= '0';
LeftSampleReg <= (others => '0');
RightSampleReg <= (others => '0');
tempReg <= (others => '0');
LSampleValid <= '0';
RSampleValid <= '0';
loaded <= '0';
SClkOld <= '0';
elsif Clk_i'event and Clk_i = '1' then
LRClkOld <= LRClk_i;
SClkOld <= SClk_i;
if StrobeLeft_i = '1' then
LeftSampleReg <= SampleLeft_i;
LSampleValid <= '1';
-- sReg(SampleSize_g - 1 downto 0) <= SampleLeft_i;
end if;
if StrobeRight_i = '1' then
RightSampleReg <= SampleRight_i;
RSampleValid <= '1';
end if;
case state is
when WAITSAMPLE =>
loaded <= '0';
when WAITLRCLK0 =>
-- ensure the regs are only loaded once
SdnyData_o <= '0';
if loaded = '0' then
loaded <= '1';
sReg <= LeftSampleReg;
LSampleValid <= '0';
RSampleValid <= '0';
tempReg <= RightSampleReg;
Cnt <= (others => '0');
-- Cnt <=std_ulogic_vector(to_unsigned(1,Cnt'high+1));
-- SdnyData_o <= LeftSampleReg(SampleSize_g-1);
-- sReg <= LeftSampleReg(SampleSize_g-2 downto 0)&"0";
end if;
when TRANSMITLEFT | TRANSMITRIGHT =>
if Finished = '0' and ((SClk_i xor SClkOld) and SClkOld) = '1' then
SdnyData_o <= sReg(SampleSize_g-1);
sReg <= sReg(SampleSize_g-2 downto 0)&"0";
Cnt <= std_ulogic_vector(unsigned(Cnt) + 1);
end if;
when WAITLRCLK1 =>
SdnyData_o <= '0';
sReg <= tempReg;
Cnt <= (others => '0');
-- Cnt <=std_ulogic_vector(to_unsigned(1,Cnt'high+1));
-- SdnyData_o <= tempReg(SampleSize_g-1);
-- sReg <= tempReg(SampleSize_g-2 downto 0)&"0";
when others => null;
end case;
end if;
end process shiftreg;
end rtl;
| mit | b08f79844be53eae0001bccef238dd4e | 0.479052 | 3.843553 | false | false | false | false |
michaelfivez/ascon_hardware_implementation | ascon12864_iterated/Kernel/OutputGenerator.vhd | 1 | 5,094 | -------------------------------------------------------------------------------
--! @project Iterated hardware implementation of Asconv12864
--! @author Michael Fivez
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is an hardware implementation made for my graduation thesis
--! at the KULeuven, in the COSIC department (year 2015-2016)
--! The thesis is titled 'Energy efficient hardware implementations of CAESAR submissions',
--! and can be found on the COSIC website (www.esat.kuleuven.be/cosic/publications)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity OutputGenerator is
port(
In0 : in std_logic_vector(63 downto 0);
DataIn : in std_logic_vector(63 downto 0);
Size : in std_logic_vector(2 downto 0);
Activate : in std_logic;
Out0 : out std_logic_vector(63 downto 0);
DataOut : out std_logic_vector(63 downto 0));
end entity OutputGenerator;
architecture structural of OutputGenerator is
constant ALLZERO : std_logic_vector(63 downto 0) := (others => '0');
signal Temp0,Temp1,Temp2 : std_logic_vector(63 downto 0);
begin
Gen: process(In0,DataIn,Size,Activate,Temp0,Temp1,Temp2) is
-- Truncator0&1
procedure doTruncate0 ( -- Truncate block 0 and 1 together
signal Input : in std_logic_vector(63 downto 0);
signal Size : in std_logic_vector(2 downto 0);
signal Activate : in std_logic;
signal Output : out std_logic_vector(63 downto 0)) is
variable ActSize : std_logic_vector(3 downto 0);
begin
ActSize(3) := Activate;
ActSize(2 downto 0) := Size;
-- if inactive it lets everything trough, if active it lets the first blocksize bits trough
logic: case ActSize is
when "1001" =>
Output(63 downto 56) <= Input(63 downto 56);
Output(55) <= '1';
Output(54 downto 0) <= ALLZERO(54 downto 0);
when "1010" =>
Output(63 downto 48) <= Input(63 downto 48);
Output(47) <= '1';
Output(46 downto 0) <= ALLZERO(46 downto 0);
when "1011" =>
Output(63 downto 40) <= Input(63 downto 40);
Output(39) <= '1';
Output(38 downto 0) <= ALLZERO(38 downto 0);
when "1100" =>
Output(63 downto 32) <= Input(63 downto 32);
Output(31) <= '1';
Output(30 downto 0) <= ALLZERO(30 downto 0);
when "1101" =>
Output(63 downto 24) <= Input(63 downto 24);
Output(23) <= '1';
Output(22 downto 0) <= ALLZERO(22 downto 0);
when "1110" =>
Output(63 downto 16) <= Input(63 downto 16);
Output(15) <= '1';
Output(14 downto 0) <= ALLZERO(14 downto 0);
when "1111" =>
Output(63 downto 8) <= Input(63 downto 8);
Output(7) <= '1';
Output(6 downto 0) <= ALLZERO(6 downto 0);
when others => -- deactivate or blocksize max or invalid input (cas 0xxxx or 10000)
Output <= Input;
end case logic;
end procedure doTruncate0;
-- Truncator2
procedure doTruncate2 ( -- Truncate block 0 and 1 together
signal Input : in std_logic_vector(63 downto 0);
signal Size : in std_logic_vector(2 downto 0);
signal Activate : in std_logic;
signal Output : out std_logic_vector(63 downto 0)) is
variable ActSize : std_logic_vector(3 downto 0);
begin
ActSize(3) := Activate;
ActSize(2 downto 0) := Size;
-- if inactive it lets everything trough, if active it blocks the first blocksize bits
logic: case ActSize is
when "1000" =>
Output <= ALLZERO;
when "1001" =>
Output(63 downto 56) <= ALLZERO(63 downto 56);
Output(55 downto 0) <= Input(55 downto 0);
when "1010" =>
Output(63 downto 48) <= ALLZERO(63 downto 48);
Output(47 downto 0) <= Input(47 downto 0);
when "1011" =>
Output(63 downto 40) <= ALLZERO(63 downto 40);
Output(39 downto 0) <= Input(39 downto 0);
when "1100" =>
Output(63 downto 32) <= ALLZERO(63 downto 32);
Output(31 downto 0) <= Input(31 downto 0);
when "1101" =>
Output(63 downto 24) <= ALLZERO(63 downto 24);
Output(23 downto 0) <= Input(23 downto 0);
when "1110" =>
Output(63 downto 16) <= ALLZERO(63 downto 16);
Output(15 downto 0) <= Input(15 downto 0);
when "1111" =>
Output(63 downto 8) <= ALLZERO(63 downto 8);
Output(7 downto 0) <= Input(7 downto 0);
when others => -- deactivate or blocksize max or invalid input (cas 0xxxx or 10000)
Output <= Input;
end case logic;
end procedure doTruncate2;
begin
-- DataOut
DataOut <= In0 xor DataIn;
-- Stateupdate
doTruncate0(DataIn,Size,Activate,Temp0);
Temp1 <= In0;
doTruncate2(Temp1,Size,Activate,Temp2);
Out0 <= Temp0 xor Temp2;
end process Gen;
end architecture structural;
| gpl-3.0 | 7663a7c657d3030ed53489372c071cc1 | 0.607185 | 3.389222 | false | false | false | false |
pcrost/gen-util | str_util.vhd | 1 | 4,682 | -------------------------------------------------------------------------------
-- (C) P. Crosthwaite, University of Queensland (2011)
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the Free Software Foundation; either
--version 3.0 of the License, or (at your option) any later version.
--This library is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--Lesser General Public License for more details.
--You should have received a copy of the GNU Lesser General Public
--License along with this library.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library gen_util;
use gen_util.util.all;
use gen_util.slv_util.all;
package str_util is
function util_spaces(a : integer) return string;
function util_tab (a : integer) return string;
function util_boolean_to_string (a : boolean) return string;
function util_std_logic_to_string (a : std_logic) return string;
function util_int_to_str (a : integer) return string;
function util_slv_to_str_bin (a : std_logic_vector) return string;
function util_slv_to_str_bin_nibbles(ar : std_logic_vector) return string;
function util_slv_to_str_hex (ar : std_logic_vector) return string;
function util_slv_to_str_hex_and_bin (a : std_logic_vector) return string;
end str_util;
package body str_util is
constant TAB_SIZE : integer := 4;
function util_tab (a : integer) return string is begin
return util_spaces(a * TAB_SIZE);
end function;
function util_spaces (a : integer) return string is begin
if (a < 2) then
return " ";
else
return util_spaces(roof_div(a, 2)) & util_spaces(a/2);
end if;
end function;
function util_boolean_to_string (a : boolean) return string is begin
return util_select_str(a, "T", "F");
end;
function util_std_logic_to_string (a : std_logic) return string is begin
return util_select_str(
(a /= '1') and (a /= '0'),
"X",
util_select_str((a = '1'), "1", "0")
);
end;
--TODO: support multiple radixes
function util_int_to_str (a : integer) return string is begin
if (a < 10) then
case a is
when 0 => return "0";
when 1 => return "1";
when 2 => return "2";
when 3 => return "3";
when 4 => return "4";
when 5 => return "5";
when 6 => return "6";
when 7 => return "7";
when 8 => return "8";
when 9 => return "9";
when others => return "X";
end case;
else
return util_int_to_str(a / 10) & util_int_to_str(a mod 10);
end if;
end;
--LISP style!!
function util_slv_to_str_hex (ar : std_logic_vector) return string is
constant DIVISOR : integer := ((ar'length)/4+1) /2;
constant a : std_logic_vector := slv_dt0_slice(ar);
variable aw : std_logic_vector(3 downto 0);
begin
if (a'length = 4) then
aw := a(3 downto 0);
case aw is
when x"0" => return "0";
when x"1" => return "1";
when x"2" => return "2";
when x"3" => return "3";
when x"4" => return "4";
when x"5" => return "5";
when x"6" => return "6";
when x"7" => return "7";
when x"8" => return "8";
when x"9" => return "9";
when x"a" => return "a";
when x"b" => return "b";
when x"c" => return "c";
when x"d" => return "d";
when x"e" => return "e";
when x"f" => return "f";
when others => return "X";
end case;
end if;
return
util_slv_to_str_hex(slv_dt0_slice(a(a'length-1 downto DIVISOR*4))) &
util_slv_to_str_hex(slv_dt0_slice(a(DIVISOR*4-1 downto 0)));
end;
function util_slv_to_str_bin (a : std_logic_vector) return string is
constant DIVISOR : integer := ((a'length)+1) / 2;
begin
if (a'length = 1) then return util_std_logic_to_string(a(0)); end if;
return
util_slv_to_str_bin(slv_dt0_slice(a(a'length-1 downto DIVISOR))) &
util_slv_to_str_bin(slv_dt0_slice(a(DIVISOR-1 downto 0)));
end;
function util_slv_to_str_bin_nibbles(ar : std_logic_vector) return string is
constant a :std_logic_vector := slv_dt0_slice(ar);
begin
if (a'length > 4) then
return util_slv_to_str_bin_nibbles(a(a'length-1 downto 4)) &
"_" & util_slv_to_str_bin(a(3 downto 0));
else
return util_slv_to_str_bin(a(a'length-1 downto 0));
end if;
end function;
function util_slv_to_str_hex_and_bin (a : std_logic_vector) return string is begin
return util_slv_to_str_bin_nibbles(a) & "(" & util_slv_to_str_hex(a) & ")";
end function;
end str_util;
| lgpl-3.0 | 6bfe830df7d27492cea350016ea447da | 0.628364 | 2.918953 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/techmap/altera_mf/tap_altera_mf.vhd | 2 | 4,905 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: tap_altera
-- File: tap_altera_gen.vhd
-- Author: Edvin Catovic - Gaisler Research
-- Description: Altera TAP controllers wrappers
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library altera_mf;
use altera_mf.altera_mf_components.all;
use altera_mf.sld_virtual_jtag;
-- pragma translate_on
entity altera_tap is
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_inst : out std_logic_vector(7 downto 0);
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end;
architecture rtl of altera_tap is
signal ir0 : std_logic_vector(7 downto 0);
component sld_virtual_jtag
generic (
--lpm_hint : string := "UNUSED";
--lpm_type : string := "sld_virtual_jtag";
sld_auto_instance_index : string := "NO";
sld_instance_index : natural := 0;
sld_ir_width : natural := 1;
sld_sim_action : string := "UNUSED"
--sld_sim_n_scan : natural := 0;
--sld_sim_total_length : natural := 0
);
port(
ir_in : out std_logic_vector(sld_ir_width-1 downto 0);
ir_out : in std_logic_vector(sld_ir_width-1 downto 0);
jtag_state_cdr : out std_logic;
jtag_state_cir : out std_logic;
jtag_state_e1dr : out std_logic;
jtag_state_e1ir : out std_logic;
jtag_state_e2dr : out std_logic;
jtag_state_e2ir : out std_logic;
jtag_state_pdr : out std_logic;
jtag_state_pir : out std_logic;
jtag_state_rti : out std_logic;
jtag_state_sdr : out std_logic;
jtag_state_sdrs : out std_logic;
jtag_state_sir : out std_logic;
jtag_state_sirs : out std_logic;
jtag_state_tlr : out std_logic;
jtag_state_udr : out std_logic;
jtag_state_uir : out std_logic;
tck : out std_logic;
tdi : out std_logic;
tdo : in std_logic;
tms : out std_logic;
virtual_state_cdr : out std_logic;
virtual_state_cir : out std_logic;
virtual_state_e1dr : out std_logic;
virtual_state_e2dr : out std_logic;
virtual_state_pdr : out std_logic;
virtual_state_sdr : out std_logic;
virtual_state_udr : out std_logic;
virtual_state_uir : out std_logic
);
end component;
begin
tapo_capt <= '0'; tapo_upd <= '0'; tapo_rst <= '0';
tapo_xsel1 <= '0'; tapo_xsel2 <= '0';
u0 : sld_virtual_jtag
generic map (sld_ir_width => 8,
sld_auto_instance_index => "NO",
sld_instance_index => 0)
port map (ir_in => tapo_inst,
ir_out => ir0,
jtag_state_cdr => open,
jtag_state_cir => open,
jtag_state_e1dr => open,
jtag_state_e1ir => open,
jtag_state_e2dr => open,
jtag_state_e2ir => open,
jtag_state_pdr => open,
jtag_state_pir => open,
jtag_state_rti => open,
jtag_state_sdr => open,
jtag_state_sdrs => open,
jtag_state_sir => open,
jtag_state_sirs => open,
jtag_state_tlr => open,
jtag_state_udr => open,
jtag_state_uir => open,
tck => tapo_tck,
tdi => tapo_tdi,
tdo => tapi_tdo1,
tms => open,
virtual_state_cdr => open,
virtual_state_cir => open,
virtual_state_e1dr => open,
virtual_state_e2dr => open,
virtual_state_pdr => open,
virtual_state_sdr => tapo_shft,
virtual_state_udr => open,
virtual_state_uir => open);
end;
| mit | aab4844fe64deca6173e7bf777a0aaf8 | 0.555352 | 3.307485 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Defense/iu3ShadowBootDCE.vhd | 1 | 588,892 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008, 2009, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: iu3
-- File: iu3.vhd
-- Author: Jiri Gaisler, Edvin Catovic, Gaisler Research
-- Description: LEON3 7-stage integer pipline
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.sparc.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.leon3.all;
use gaisler.libiu.all;
use gaisler.arith.all;
-- pragma translate_off
use grlib.sparc_disas.all;
-- pragma translate_on
entity iu3 is
generic (
nwin : integer range 2 to 32 := 8;
isets : integer range 1 to 4 := 2;
dsets : integer range 1 to 4 := 2;
fpu : integer range 0 to 15 := 0;
v8 : integer range 0 to 63 := 2;
cp, mac : integer range 0 to 1 := 0;
dsu : integer range 0 to 1 := 1;
nwp : integer range 0 to 4 := 2;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
index : integer range 0 to 15:= 0;
lddel : integer range 1 to 2 := 1;
irfwt : integer range 0 to 1 := 0;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 2; -- trace buf size in kB (0 - no trace buffer)
pwd : integer range 0 to 2 := 0; -- power-down
svt : integer range 0 to 1 := 0; -- single-vector trapping
rstaddr : integer := 16#00000#; -- reset vector MSB address
smp : integer range 0 to 15 := 0; -- support SMP systems
fabtech : integer range 0 to NTECH := 20;
clk2x : integer := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
holdn : in std_ulogic;
ici : buffer icache_in_type;
ico : in icache_out_type;
dci : buffer dcache_in_type;
dco : in dcache_out_type;
rfi : buffer iregfile_in_type;
rfo : in iregfile_out_type;
irqi : in l3_irq_in_type;
irqo : buffer l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : buffer l3_debug_out_type;
muli : buffer mul32_in_type;
mulo : in mul32_out_type;
divi : buffer div32_in_type;
divo : in div32_out_type;
fpo : in fpc_out_type;
fpi : buffer fpc_in_type;
cpo : in fpc_out_type;
cpi : buffer fpc_in_type;
tbo : in tracebuf_out_type;
tbi : buffer tracebuf_in_type;
sclk : in std_ulogic
);
end;
architecture rtl of iu3 is
constant ISETMSB : integer := 0;
constant DSETMSB : integer := 0;
constant RFBITS : integer range 6 to 10 := 8;
constant NWINLOG2 : integer range 1 to 5 := 3;
constant CWPOPT : boolean := true;
constant CWPMIN : std_logic_vector(2 downto 0) := "000";
constant CWPMAX : std_logic_vector(2 downto 0) := "111";
constant FPEN : boolean := (fpu /= 0);
constant CPEN : boolean := false;
constant MULEN : boolean := true;
constant MULTYPE: integer := 0;
constant DIVEN : boolean := true;
constant MACEN : boolean := false;
constant MACPIPE: boolean := false;
constant IMPL : integer := 15;
constant VER : integer := 3;
constant DBGUNIT : boolean := true;
constant TRACEBUF : boolean := true;
constant TBUFBITS : integer := 7;
constant PWRD1 : boolean := false; --(pwd = 1) and not (index /= 0);
constant PWRD2 : boolean := false; --(pwd = 2) or (index /= 0);
constant RS1OPT : boolean := true;
constant DYNRST : boolean := false;
subtype word is std_logic_vector(31 downto 0);
subtype pctype is std_logic_vector(31 downto 2);
subtype rfatype is std_logic_vector(8-1 downto 0);
subtype cwptype is std_logic_vector(3-1 downto 0);
type icdtype is array (0 to 2-1) of word;
type dcdtype is array (0 to 2-1) of word;
type dc_in_type is record
signed, enaddr, read, write, lock , dsuen : std_ulogic;
size : std_logic_vector(1 downto 0);
asi : std_logic_vector(7 downto 0);
end record;
type pipeline_ctrl_type is record
pc : pctype;
inst : word;
cnt : std_logic_vector(1 downto 0);
rd : rfatype;
tt : std_logic_vector(5 downto 0);
trap : std_ulogic;
annul : std_ulogic;
wreg : std_ulogic;
wicc : std_ulogic;
wy : std_ulogic;
ld : std_ulogic;
pv : std_ulogic;
rett : std_ulogic;
end record;
type fetch_reg_type is record
pc : pctype;
branch : std_ulogic;
end record;
type decode_reg_type is record
pc : pctype;
inst : icdtype;
cwp : cwptype;
set : std_logic_vector(0 downto 0);
mexc : std_ulogic;
cnt : std_logic_vector(1 downto 0);
pv : std_ulogic;
annul : std_ulogic;
inull : std_ulogic;
step : std_ulogic;
end record;
type regacc_reg_type is record
ctrl : pipeline_ctrl_type;
rs1 : std_logic_vector(4 downto 0);
rfa1, rfa2 : rfatype;
rsel1, rsel2 : std_logic_vector(2 downto 0);
rfe1, rfe2 : std_ulogic;
cwp : cwptype;
imm : word;
ldcheck1 : std_ulogic;
ldcheck2 : std_ulogic;
ldchkra : std_ulogic;
ldchkex : std_ulogic;
su : std_ulogic;
et : std_ulogic;
wovf : std_ulogic;
wunf : std_ulogic;
ticc : std_ulogic;
jmpl : std_ulogic;
step : std_ulogic;
mulstart : std_ulogic;
divstart : std_ulogic;
end record;
type execute_reg_type is record
ctrl : pipeline_ctrl_type;
op1 : word;
op2 : word;
aluop : std_logic_vector(2 downto 0); -- Alu operation
alusel : std_logic_vector(1 downto 0); -- Alu result select
aluadd : std_ulogic;
alucin : std_ulogic;
ldbp1, ldbp2 : std_ulogic;
invop2 : std_ulogic;
shcnt : std_logic_vector(4 downto 0); -- shift count
sari : std_ulogic; -- shift msb
shleft : std_ulogic; -- shift left/right
ymsb : std_ulogic; -- shift left/right
rd : std_logic_vector(4 downto 0);
jmpl : std_ulogic;
su : std_ulogic;
et : std_ulogic;
cwp : cwptype;
icc : std_logic_vector(3 downto 0);
mulstep: std_ulogic;
mul : std_ulogic;
mac : std_ulogic;
end record;
type memory_reg_type is record
ctrl : pipeline_ctrl_type;
result : word;
y : word;
icc : std_logic_vector(3 downto 0);
nalign : std_ulogic;
dci : dc_in_type;
werr : std_ulogic;
wcwp : std_ulogic;
irqen : std_ulogic;
irqen2 : std_ulogic;
mac : std_ulogic;
divz : std_ulogic;
su : std_ulogic;
mul : std_ulogic;
end record;
type exception_state is (run, trap, dsu1, dsu2);
type exception_reg_type is record
ctrl : pipeline_ctrl_type;
result : word;
y : word;
icc : std_logic_vector( 3 downto 0);
annul_all : std_ulogic;
data : dcdtype;
set : std_logic_vector(0 downto 0);
mexc : std_ulogic;
dci : dc_in_type;
laddr : std_logic_vector(1 downto 0);
rstate : exception_state;
npc : std_logic_vector(2 downto 0);
intack : std_ulogic;
ipend : std_ulogic;
mac : std_ulogic;
debug : std_ulogic;
nerror : std_ulogic;
end record;
type dsu_registers is record
tt : std_logic_vector(7 downto 0);
err : std_ulogic;
tbufcnt : std_logic_vector(7-1 downto 0);
asi : std_logic_vector(7 downto 0);
crdy : std_logic_vector(2 downto 1); -- diag cache access ready
end record;
type irestart_register is record
addr : pctype;
pwd : std_ulogic;
end record;
type pwd_register_type is record
pwd : std_ulogic;
error : std_ulogic;
end record;
type special_register_type is record
cwp : cwptype; -- current window pointer
icc : std_logic_vector(3 downto 0); -- integer condition codes
tt : std_logic_vector(7 downto 0); -- trap type
tba : std_logic_vector(19 downto 0); -- trap base address
wim : std_logic_vector(8-1 downto 0); -- window invalid mask
pil : std_logic_vector(3 downto 0); -- processor interrupt level
ec : std_ulogic; -- enable CP
ef : std_ulogic; -- enable FP
ps : std_ulogic; -- previous supervisor flag
s : std_ulogic; -- supervisor flag
et : std_ulogic; -- enable traps
y : word;
asr18 : word;
svt : std_ulogic; -- enable traps
dwt : std_ulogic; -- disable write error trap
end record;
type write_reg_type is record
s : special_register_type;
result : word;
wa : rfatype;
wreg : std_ulogic;
except : std_ulogic;
end record;
type registers is record
f : fetch_reg_type;
d : decode_reg_type;
a : regacc_reg_type;
e : execute_reg_type;
m : memory_reg_type;
x : exception_reg_type;
w : write_reg_type;
end record;
type exception_type is record
pri : std_ulogic;
ill : std_ulogic;
fpdis : std_ulogic;
cpdis : std_ulogic;
wovf : std_ulogic;
wunf : std_ulogic;
ticc : std_ulogic;
end record;
type watchpoint_register is record
addr : std_logic_vector(31 downto 2); -- watchpoint address
mask : std_logic_vector(31 downto 2); -- watchpoint mask
exec : std_ulogic; -- trap on instruction
load : std_ulogic; -- trap on load
store : std_ulogic; -- trap on store
end record;
type watchpoint_registers is array (0 to 3) of watchpoint_register;
constant wpr_none : watchpoint_register := (
"000000000000000000000000000000", "000000000000000000000000000000", '0', '0', '0');
function dbgexc(r : registers; dbgi : l3_debug_in_type; trap : std_ulogic; tt : std_logic_vector(7 downto 0)) return std_ulogic is
variable dmode : std_ulogic;
begin
dmode := '0';
if (not r.x.ctrl.annul and trap) = '1' then
if (((tt = "00" & TT_WATCH) and (dbgi.bwatch = '1')) or
((dbgi.bsoft = '1') and (tt = "10000001")) or
(dbgi.btrapa = '1') or
((dbgi.btrape = '1') and not ((tt(5 downto 0) = TT_PRIV) or
(tt(5 downto 0) = TT_FPDIS) or (tt(5 downto 0) = TT_WINOF) or
(tt(5 downto 0) = TT_WINUF) or (tt(5 downto 4) = "01") or (tt(7) = '1'))) or
(((not r.w.s.et) and dbgi.berror) = '1')) then
dmode := '1';
end if;
end if;
return(dmode);
end;
function dbgerr(r : registers; dbgi : l3_debug_in_type;
tt : std_logic_vector(7 downto 0))
return std_ulogic is
variable err : std_ulogic;
begin
err := not r.w.s.et;
if (((dbgi.dbreak = '1') and (tt = ("00" & TT_WATCH))) or
((dbgi.bsoft = '1') and (tt = ("10000001")))) then
err := '0';
end if;
return(err);
end;
procedure diagwr(r : in registers;
dsur : in dsu_registers;
ir : in irestart_register;
dbg : in l3_debug_in_type;
wpr : in watchpoint_registers;
s : out special_register_type;
vwpr : out watchpoint_registers;
asi : out std_logic_vector(7 downto 0);
pc, npc : out pctype;
tbufcnt : out std_logic_vector(7-1 downto 0);
wr : out std_ulogic;
addr : out std_logic_vector(9 downto 0);
data : out word;
fpcwr : out std_ulogic) is
variable i : integer range 0 to 3;
begin
s := r.w.s; pc := r.f.pc; npc := ir.addr; wr := '0';
vwpr := wpr; asi := dsur.asi; addr := "0000000000";
data := dbg.ddata;
tbufcnt := dsur.tbufcnt; fpcwr := '0';
if (dbg.dsuen and dbg.denable and dbg.dwrite) = '1' then
case dbg.daddr(23 downto 20) is
when "0001" =>
if (dbg.daddr(16) = '1') and true then -- trace buffer control reg
tbufcnt := dbg.ddata(7-1 downto 0);
end if;
when "0011" => -- IU reg file
if dbg.daddr(12) = '0' then
wr := '1';
addr := "0000000000";
addr(8-1 downto 0) := dbg.daddr(8+1 downto 2);
else -- FPC
fpcwr := '1';
end if;
when "0100" => -- IU special registers
case dbg.daddr(7 downto 6) is
when "00" => -- IU regs Y - TBUF ctrl reg
case dbg.daddr(5 downto 2) is
when "0000" => -- Y
s.y := dbg.ddata;
when "0001" => -- PSR
s.cwp := dbg.ddata(3-1 downto 0);
s.icc := dbg.ddata(23 downto 20);
s.ec := dbg.ddata(13);
if FPEN then s.ef := dbg.ddata(12); end if;
s.pil := dbg.ddata(11 downto 8);
s.s := dbg.ddata(7);
s.ps := dbg.ddata(6);
s.et := dbg.ddata(5);
when "0010" => -- WIM
s.wim := dbg.ddata(8-1 downto 0);
when "0011" => -- TBR
s.tba := dbg.ddata(31 downto 12);
s.tt := dbg.ddata(11 downto 4);
when "0100" => -- PC
pc := dbg.ddata(31 downto 2);
when "0101" => -- NPC
npc := dbg.ddata(31 downto 2);
when "0110" => --FSR
fpcwr := '1';
when "0111" => --CFSR
when "1001" => -- ASI reg
asi := dbg.ddata(7 downto 0);
--when "1001" => -- TBUF ctrl reg
-- tbufcnt := dbg.ddata(7-1 downto 0);
when others =>
end case;
when "01" => -- ASR16 - ASR31
case dbg.daddr(5 downto 2) is
when "0001" => -- %ASR17
s.dwt := dbg.ddata(14);
s.svt := dbg.ddata(13);
when "0010" => -- %ASR18
if false then s.asr18 := dbg.ddata; end if;
when "1000" => -- %ASR24 - %ASR31
vwpr(0).addr := dbg.ddata(31 downto 2);
vwpr(0).exec := dbg.ddata(0);
when "1001" =>
vwpr(0).mask := dbg.ddata(31 downto 2);
vwpr(0).load := dbg.ddata(1);
vwpr(0).store := dbg.ddata(0);
when "1010" =>
vwpr(1).addr := dbg.ddata(31 downto 2);
vwpr(1).exec := dbg.ddata(0);
when "1011" =>
vwpr(1).mask := dbg.ddata(31 downto 2);
vwpr(1).load := dbg.ddata(1);
vwpr(1).store := dbg.ddata(0);
when "1100" =>
vwpr(2).addr := dbg.ddata(31 downto 2);
vwpr(2).exec := dbg.ddata(0);
when "1101" =>
vwpr(2).mask := dbg.ddata(31 downto 2);
vwpr(2).load := dbg.ddata(1);
vwpr(2).store := dbg.ddata(0);
when "1110" =>
vwpr(3).addr := dbg.ddata(31 downto 2);
vwpr(3).exec := dbg.ddata(0);
when "1111" => --
vwpr(3).mask := dbg.ddata(31 downto 2);
vwpr(3).load := dbg.ddata(1);
vwpr(3).store := dbg.ddata(0);
when others => --
end case;
-- disabled due to bug in XST
-- i := conv_integer(dbg.daddr(4 downto 3));
-- if dbg.daddr(2) = '0' then
-- vwpr(i).addr := dbg.ddata(31 downto 2);
-- vwpr(i).exec := dbg.ddata(0);
-- else
-- vwpr(i).mask := dbg.ddata(31 downto 2);
-- vwpr(i).load := dbg.ddata(1);
-- vwpr(i).store := dbg.ddata(0);
-- end if;
when others =>
end case;
when others =>
end case;
end if;
end;
function asr17_gen ( r : in registers) return word is
variable asr17 : word;
variable fpu2 : integer range 0 to 3;
begin
asr17 := "00000000000000000000000000000000";
asr17(31 downto 28) := conv_std_logic_vector(index, 4);
if (clk2x > 8) then
asr17(16 downto 15) := conv_std_logic_vector(clk2x-8, 2);
asr17(17) := '1';
elsif (clk2x > 0) then
asr17(16 downto 15) := conv_std_logic_vector(clk2x, 2);
end if;
asr17(14) := r.w.s.dwt;
if svt = 1 then asr17(13) := r.w.s.svt; end if;
if lddel = 2 then asr17(12) := '1'; end if;
if (fpu > 0) and (fpu < 8) then fpu2 := 1;
elsif (fpu >= 8) and (fpu < 15) then fpu2 := 3;
elsif fpu = 15 then fpu2 := 2;
else fpu2 := 0; end if;
asr17(11 downto 10) := conv_std_logic_vector(fpu2, 2);
if mac = 1 then asr17(9) := '1'; end if;
if 2 /= 0 then asr17(8) := '1'; end if;
asr17(7 downto 5) := conv_std_logic_vector(nwp, 3);
asr17(4 downto 0) := conv_std_logic_vector(8-1, 5);
return(asr17);
end;
procedure diagread(dbgi : in l3_debug_in_type;
r : in registers;
dsur : in dsu_registers;
ir : in irestart_register;
wpr : in watchpoint_registers;
dco : in dcache_out_type;
tbufo : in tracebuf_out_type;
data : out word) is
variable cwp : std_logic_vector(4 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable i : integer range 0 to 3;
begin
data := "00000000000000000000000000000000"; cwp := "00000";
cwp(3-1 downto 0) := r.w.s.cwp;
case dbgi.daddr(22 downto 20) is
when "001" => -- trace buffer
if true then
if dbgi.daddr(16) = '1' then -- trace buffer control reg
if true then data(7-1 downto 0) := dsur.tbufcnt; end if;
else
case dbgi.daddr(3 downto 2) is
when "00" => data := tbufo.data(127 downto 96);
when "01" => data := tbufo.data(95 downto 64);
when "10" => data := tbufo.data(63 downto 32);
when others => data := tbufo.data(31 downto 0);
end case;
end if;
end if;
when "011" => -- IU reg file
if dbgi.daddr(12) = '0' then
data := rfo.data1(31 downto 0);
if (dbgi.daddr(11) = '1') and (is_fpga(fabtech) = 0) then
data := rfo.data2(31 downto 0);
end if;
else data := fpo.dbg.data; end if;
when "100" => -- IU regs
case dbgi.daddr(7 downto 6) is
when "00" => -- IU regs Y - TBUF ctrl reg
case dbgi.daddr(5 downto 2) is
when "0000" =>
data := r.w.s.y;
when "0001" =>
data := conv_std_logic_vector(15, 4) & conv_std_logic_vector(3, 4) &
r.w.s.icc & "000000" & r.w.s.ec & r.w.s.ef & r.w.s.pil &
r.w.s.s & r.w.s.ps & r.w.s.et & cwp;
when "0010" =>
data(8-1 downto 0) := r.w.s.wim;
when "0011" =>
data := r.w.s.tba & r.w.s.tt & "0000";
when "0100" =>
data(31 downto 2) := r.f.pc;
when "0101" =>
data(31 downto 2) := ir.addr;
when "0110" => -- FSR
data := fpo.dbg.data;
when "0111" => -- CPSR
when "1000" => -- TT reg
data(12 downto 4) := dsur.err & dsur.tt;
when "1001" => -- ASI reg
data(7 downto 0) := dsur.asi;
when others =>
end case;
when "01" =>
if dbgi.daddr(5) = '0' then -- %ASR17
if dbgi.daddr(4 downto 2) = "001" then -- %ASR17
data := asr17_gen(r);
elsif false and dbgi.daddr(4 downto 2) = "010" then -- %ASR18
data := r.w.s.asr18;
end if;
else -- %ASR24 - %ASR31
i := conv_integer(dbgi.daddr(4 downto 3)); --
if dbgi.daddr(2) = '0' then
data(31 downto 2) := wpr(i).addr;
data(0) := wpr(i).exec;
else
data(31 downto 2) := wpr(i).mask;
data(1) := wpr(i).load;
data(0) := wpr(i).store;
end if;
end if;
when others =>
end case;
when "111" =>
data := r.x.data(conv_integer(r.x.set));
when others =>
end case;
end;
procedure itrace(r : in registers;
dsur : in dsu_registers;
vdsu : in dsu_registers;
res : in word;
exc : in std_ulogic;
dbgi : in l3_debug_in_type;
error : in std_ulogic;
trap : in std_ulogic;
tbufcnt : out std_logic_vector(7-1 downto 0);
di : out tracebuf_in_type) is
variable meminst : std_ulogic;
begin
di.addr := (others => '0'); di.data := (others => '0');
di.enable := '0'; di.write := (others => '0');
tbufcnt := vdsu.tbufcnt;
meminst := r.x.ctrl.inst(31) and r.x.ctrl.inst(30);
if true then
di.addr(7-1 downto 0) := dsur.tbufcnt;
di.data(127) := '0';
di.data(126) := not r.x.ctrl.pv;
di.data(125 downto 96) := dbgi.timer(29 downto 0);
di.data(95 downto 64) := res;
di.data(63 downto 34) := r.x.ctrl.pc(31 downto 2);
di.data(33) := trap;
di.data(32) := error;
di.data(31 downto 0) := r.x.ctrl.inst;
if (dbgi.tenable = '0') or (r.x.rstate = dsu2) then
if ((dbgi.dsuen and dbgi.denable) = '1') and (dbgi.daddr(23 downto 20) & dbgi.daddr(16) = "00010") then
di.enable := '1';
di.addr(7-1 downto 0) := dbgi.daddr(7-1+4 downto 4);
if dbgi.dwrite = '1' then
case dbgi.daddr(3 downto 2) is
when "00" => di.write(3) := '1';
when "01" => di.write(2) := '1';
when "10" => di.write(1) := '1';
when others => di.write(0) := '1';
end case;
di.data := dbgi.ddata & dbgi.ddata & dbgi.ddata & dbgi.ddata;
end if;
end if;
elsif (not r.x.ctrl.annul and (r.x.ctrl.pv or meminst) and not r.x.debug) = '1' then
di.enable := '1'; di.write := (others => '1');
tbufcnt := dsur.tbufcnt + 1;
end if;
di.diag := dco.testen & "000";
if dco.scanen = '1' then di.enable := '0'; end if;
end if;
end;
procedure dbg_cache(holdn : in std_ulogic;
dbgi : in l3_debug_in_type;
r : in registers;
dsur : in dsu_registers;
mresult : in word;
dci : in dc_in_type;
mresult2 : out word;
dci2 : out dc_in_type
) is
begin
mresult2 := mresult; dci2 := dci; dci2.dsuen := '0';
if true then
if r.x.rstate = dsu2 then
dci2.asi := dsur.asi;
if (dbgi.daddr(22 downto 20) = "111") and (dbgi.dsuen = '1') then
dci2.dsuen := (dbgi.denable or r.m.dci.dsuen) and not dsur.crdy(2);
dci2.enaddr := dbgi.denable;
dci2.size := "10"; dci2.read := '1'; dci2.write := '0';
if (dbgi.denable and not r.m.dci.enaddr) = '1' then
mresult2 := (others => '0'); mresult2(19 downto 2) := dbgi.daddr(19 downto 2);
else
mresult2 := dbgi.ddata;
end if;
if dbgi.dwrite = '1' then
dci2.read := '0'; dci2.write := '1';
end if;
end if;
end if;
end if;
end;
procedure fpexack(r : in registers; fpexc : out std_ulogic) is
begin
fpexc := '0';
if FPEN then
if r.x.ctrl.tt = TT_FPEXC then fpexc := '1'; end if;
end if;
end;
procedure diagrdy(denable : in std_ulogic;
dsur : in dsu_registers;
dci : in dc_in_type;
mds : in std_ulogic;
ico : in icache_out_type;
crdy : out std_logic_vector(2 downto 1)) is
begin
crdy := dsur.crdy(1) & '0';
if dci.dsuen = '1' then
case dsur.asi(4 downto 0) is
when ASI_ITAG | ASI_IDATA | ASI_UINST | ASI_SINST =>
crdy(2) := ico.diagrdy and not dsur.crdy(2);
when ASI_DTAG | ASI_MMUSNOOP_DTAG | ASI_DDATA | ASI_UDATA | ASI_SDATA =>
crdy(1) := not denable and dci.enaddr and not dsur.crdy(1);
when others =>
crdy(2) := dci.enaddr and denable;
end case;
end if;
end;
signal r, rin : registers;
signal wpr, wprin : watchpoint_registers;
signal dsur, dsuin : dsu_registers;
signal ir, irin : irestart_register;
signal rp, rpin : pwd_register_type;
-- execute stage operations
constant EXE_AND : std_logic_vector(2 downto 0) := "000";
constant EXE_XOR : std_logic_vector(2 downto 0) := "001"; -- must be equal to EXE_PASS2
constant EXE_OR : std_logic_vector(2 downto 0) := "010";
constant EXE_XNOR : std_logic_vector(2 downto 0) := "011";
constant EXE_ANDN : std_logic_vector(2 downto 0) := "100";
constant EXE_ORN : std_logic_vector(2 downto 0) := "101";
constant EXE_DIV : std_logic_vector(2 downto 0) := "110";
constant EXE_PASS1 : std_logic_vector(2 downto 0) := "000";
constant EXE_PASS2 : std_logic_vector(2 downto 0) := "001";
constant EXE_STB : std_logic_vector(2 downto 0) := "010";
constant EXE_STH : std_logic_vector(2 downto 0) := "011";
constant EXE_ONES : std_logic_vector(2 downto 0) := "100";
constant EXE_RDY : std_logic_vector(2 downto 0) := "101";
constant EXE_SPR : std_logic_vector(2 downto 0) := "110";
constant EXE_LINK : std_logic_vector(2 downto 0) := "111";
constant EXE_SLL : std_logic_vector(2 downto 0) := "001";
constant EXE_SRL : std_logic_vector(2 downto 0) := "010";
constant EXE_SRA : std_logic_vector(2 downto 0) := "100";
constant EXE_NOP : std_logic_vector(2 downto 0) := "000";
-- EXE result select
constant EXE_RES_ADD : std_logic_vector(1 downto 0) := "00";
constant EXE_RES_SHIFT : std_logic_vector(1 downto 0) := "01";
constant EXE_RES_LOGIC : std_logic_vector(1 downto 0) := "10";
constant EXE_RES_MISC : std_logic_vector(1 downto 0) := "11";
-- Load types
constant SZBYTE : std_logic_vector(1 downto 0) := "00";
constant SZHALF : std_logic_vector(1 downto 0) := "01";
constant SZWORD : std_logic_vector(1 downto 0) := "10";
constant SZDBL : std_logic_vector(1 downto 0) := "11";
-- calculate register file address
procedure regaddr(cwp : std_logic_vector; reg : std_logic_vector(4 downto 0);
rao : out rfatype) is
variable ra : rfatype;
constant globals : std_logic_vector(8-5 downto 0) :=
conv_std_logic_vector(8, 8-4);
begin
ra := (others => '0'); ra(4 downto 0) := reg;
if reg(4 downto 3) = "00" then ra(8 -1 downto 4) := globals;
else
ra(3+3 downto 4) := cwp + ra(4);
if ra(8-1 downto 4) = globals then
ra(8-1 downto 4) := (others => '0');
end if;
end if;
rao := ra;
end;
-- branch adder
function branch_address(inst : word; pc : pctype) return std_logic_vector is
variable baddr, caddr, tmp : pctype;
begin
caddr := (others => '0'); caddr(31 downto 2) := inst(29 downto 0);
caddr(31 downto 2) := caddr(31 downto 2) + pc(31 downto 2);
baddr := (others => '0'); baddr(31 downto 24) := (others => inst(21));
baddr(23 downto 2) := inst(21 downto 0);
baddr(31 downto 2) := baddr(31 downto 2) + pc(31 downto 2);
if inst(30) = '1' then tmp := caddr; else tmp := baddr; end if;
return(tmp);
end;
-- evaluate branch condition
function branch_true(icc : std_logic_vector(3 downto 0); inst : word)
return std_ulogic is
variable n, z, v, c, branch : std_ulogic;
begin
n := icc(3); z := icc(2); v := icc(1); c := icc(0);
case inst(27 downto 25) is
when "000" => branch := inst(28) xor '0'; -- bn, ba
when "001" => branch := inst(28) xor z; -- be, bne
when "010" => branch := inst(28) xor (z or (n xor v)); -- ble, bg
when "011" => branch := inst(28) xor (n xor v); -- bl, bge
when "100" => branch := inst(28) xor (c or z); -- bleu, bgu
when "101" => branch := inst(28) xor c; -- bcs, bcc
when "110" => branch := inst(28) xor n; -- bneg, bpos
when others => branch := inst(28) xor v; -- bvs, bvc
end case;
return(branch);
end;
-- detect RETT instruction in the pipeline and set the local psr.su and psr.et
procedure su_et_select(r : in registers; xc_ps, xc_s, xc_et : in std_ulogic;
su, et : out std_ulogic) is
begin
if ((r.a.ctrl.rett or r.e.ctrl.rett or r.m.ctrl.rett or r.x.ctrl.rett) = '1')
and (r.x.annul_all = '0')
then su := xc_ps; et := '1';
else su := xc_s; et := xc_et; end if;
end;
-- detect watchpoint trap
function wphit(r : registers; wpr : watchpoint_registers; debug : l3_debug_in_type)
return std_ulogic is
variable exc : std_ulogic;
begin
exc := '0';
for i in 1 to NWP loop
if ((wpr(i-1).exec and r.a.ctrl.pv and not r.a.ctrl.annul) = '1') then
if (((wpr(i-1).addr xor r.a.ctrl.pc(31 downto 2)) and wpr(i-1).mask) = "000000000000000000000000000000") then
exc := '1';
end if;
end if;
end loop;
if true then
if (debug.dsuen and not r.a.ctrl.annul) = '1' then
exc := exc or (r.a.ctrl.pv and ((debug.dbreak and debug.bwatch) or r.a.step));
end if;
end if;
return(exc);
end;
-- 32-bit shifter
function shift3(r : registers; aluin1, aluin2 : word) return word is
variable shiftin : unsigned(63 downto 0);
variable shiftout : unsigned(63 downto 0);
variable cnt : natural range 0 to 31;
begin
cnt := conv_integer(r.e.shcnt);
if r.e.shleft = '1' then
shiftin(30 downto 0) := (others => '0');
shiftin(63 downto 31) := '0' & unsigned(aluin1);
else
shiftin(63 downto 32) := (others => r.e.sari);
shiftin(31 downto 0) := unsigned(aluin1);
end if;
shiftout := SHIFT_RIGHT(shiftin, cnt);
return(std_logic_vector(shiftout(31 downto 0)));
end;
function shift2(r : registers; aluin1, aluin2 : word) return word is
variable ushiftin : unsigned(31 downto 0);
variable sshiftin : signed(32 downto 0);
variable cnt : natural range 0 to 31;
variable resleft, resright : word;
begin
cnt := conv_integer(r.e.shcnt);
ushiftin := unsigned(aluin1);
sshiftin := signed('0' & aluin1);
if r.e.shleft = '1' then
resleft := std_logic_vector(SHIFT_LEFT(ushiftin, cnt));
return(resleft);
else
if r.e.sari = '1' then sshiftin(32) := aluin1(31); end if;
sshiftin := SHIFT_RIGHT(sshiftin, cnt);
resright := std_logic_vector(sshiftin(31 downto 0));
return(resright);
-- else
-- ushiftin := SHIFT_RIGHT(ushiftin, cnt);
-- return(std_logic_vector(ushiftin));
-- end if;
end if;
end;
function shift(r : registers; aluin1, aluin2 : word;
shiftcnt : std_logic_vector(4 downto 0); sari : std_ulogic ) return word is
variable shiftin : std_logic_vector(63 downto 0);
begin
shiftin := "00000000000000000000000000000000" & aluin1;
if r.e.shleft = '1' then
shiftin(31 downto 0) := "00000000000000000000000000000000"; shiftin(63 downto 31) := '0' & aluin1;
else shiftin(63 downto 32) := (others => sari); end if;
if shiftcnt (4) = '1' then shiftin(47 downto 0) := shiftin(63 downto 16); end if;
if shiftcnt (3) = '1' then shiftin(39 downto 0) := shiftin(47 downto 8); end if;
if shiftcnt (2) = '1' then shiftin(35 downto 0) := shiftin(39 downto 4); end if;
if shiftcnt (1) = '1' then shiftin(33 downto 0) := shiftin(35 downto 2); end if;
if shiftcnt (0) = '1' then shiftin(31 downto 0) := shiftin(32 downto 1); end if;
return(shiftin(31 downto 0));
end;
-- Check for illegal and privileged instructions
procedure exception_detect(r : registers; wpr : watchpoint_registers; dbgi : l3_debug_in_type;
trapin : in std_ulogic; ttin : in std_logic_vector(5 downto 0);
trap : out std_ulogic; tt : out std_logic_vector(5 downto 0)) is
variable illegal_inst, privileged_inst : std_ulogic;
variable cp_disabled, fp_disabled, fpop : std_ulogic;
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable inst : word;
variable wph : std_ulogic;
begin
inst := r.a.ctrl.inst; trap := trapin; tt := ttin;
if r.a.ctrl.annul = '0' then
op := inst(31 downto 30); op2 := inst(24 downto 22);
op3 := inst(24 downto 19); rd := inst(29 downto 25);
illegal_inst := '0'; privileged_inst := '0'; cp_disabled := '0';
fp_disabled := '0'; fpop := '0';
case op is
when CALL => null;
when FMT2 =>
case op2 is
when SETHI | BICC => null;
when FBFCC =>
if FPEN then fp_disabled := not r.w.s.ef; else fp_disabled := '1'; end if;
when CBCCC =>
if (not false) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when others => illegal_inst := '1';
end case;
when FMT3 =>
case op3 is
when IAND | ANDCC | ANDN | ANDNCC | IOR | ORCC | ORN | ORNCC | IXOR |
XORCC | IXNOR | XNORCC | ISLL | ISRL | ISRA | MULSCC | IADD | ADDX |
ADDCC | ADDXCC | ISUB | SUBX | SUBCC | SUBXCC | FLUSH | JMPL | TICC |
SAVE | RESTORE | RDY => null;
when TADDCC | TADDCCTV | TSUBCC | TSUBCCTV =>
if notag = 1 then illegal_inst := '1'; end if;
when UMAC | SMAC =>
if not false then illegal_inst := '1'; end if;
when UMUL | SMUL | UMULCC | SMULCC =>
if not true then illegal_inst := '1'; end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if not true then illegal_inst := '1'; end if;
when RETT => illegal_inst := r.a.et; privileged_inst := not r.a.su;
when RDPSR | RDTBR | RDWIM => privileged_inst := not r.a.su;
when WRY => null;
when WRPSR =>
privileged_inst := not r.a.su;
when WRWIM | WRTBR => privileged_inst := not r.a.su;
when FPOP1 | FPOP2 =>
if FPEN then fp_disabled := not r.w.s.ef; fpop := '1';
else fp_disabled := '1'; fpop := '0'; end if;
when CPOP1 | CPOP2 =>
if (not false) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when others => illegal_inst := '1';
end case;
when others => -- LDST
case op3 is
when LDD | ISTD => illegal_inst := rd(0); -- trap if odd destination register
when LD | LDUB | LDSTUB | LDUH | LDSB | LDSH | ST | STB | STH | SWAP =>
null;
when LDDA | STDA =>
illegal_inst := inst(13) or rd(0); privileged_inst := not r.a.su;
when LDA | LDUBA| LDSTUBA | LDUHA | LDSBA | LDSHA | STA | STBA | STHA |
SWAPA =>
illegal_inst := inst(13); privileged_inst := not r.a.su;
when LDDF | STDF | LDF | LDFSR | STF | STFSR =>
if FPEN then fp_disabled := not r.w.s.ef;
else fp_disabled := '1'; end if;
when STDFQ =>
privileged_inst := not r.a.su;
if (not FPEN) or (r.w.s.ef = '0') then fp_disabled := '1'; end if;
when STDCQ =>
privileged_inst := not r.a.su;
if (not false) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when LDC | LDCSR | LDDC | STC | STCSR | STDC =>
if (not false) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when others => illegal_inst := '1';
end case;
end case;
wph := wphit(r, wpr, dbgi);
trap := '1';
if r.a.ctrl.trap = '1' then tt := TT_IAEX;
elsif privileged_inst = '1' then tt := TT_PRIV;
elsif illegal_inst = '1' then tt := TT_IINST;
elsif fp_disabled = '1' then tt := TT_FPDIS;
elsif cp_disabled = '1' then tt := TT_CPDIS;
elsif wph = '1' then tt := TT_WATCH;
elsif r.a.wovf= '1' then tt := TT_WINOF;
elsif r.a.wunf= '1' then tt := TT_WINUF;
elsif r.a.ticc= '1' then tt := TT_TICC;
else trap := '0'; tt:= (others => '0'); end if;
end if;
end;
-- instructions that write the condition codes (psr.icc)
procedure wicc_y_gen(inst : word; wicc, wy : out std_ulogic) is
begin
wicc := '0'; wy := '0';
if inst(31 downto 30) = FMT3 then
case inst(24 downto 19) is
when SUBCC | TSUBCC | TSUBCCTV | ADDCC | ANDCC | ORCC | XORCC | ANDNCC |
ORNCC | XNORCC | TADDCC | TADDCCTV | ADDXCC | SUBXCC | WRPSR =>
wicc := '1';
when WRY =>
if r.d.inst(conv_integer(r.d.set))(29 downto 25) = "00000" then wy := '1'; end if;
when MULSCC =>
wicc := '1'; wy := '1';
when UMAC | SMAC =>
if false then wy := '1'; end if;
when UMULCC | SMULCC =>
if true and (((mulo.nready = '1') and (r.d.cnt /= "00")) or (0 /= 0)) then
wicc := '1'; wy := '1';
end if;
when UMUL | SMUL =>
if true and (((mulo.nready = '1') and (r.d.cnt /= "00")) or (0 /= 0)) then
wy := '1';
end if;
when UDIVCC | SDIVCC =>
if true and (divo.nready = '1') and (r.d.cnt /= "00") then
wicc := '1';
end if;
when others =>
end case;
end if;
end;
-- select cwp
procedure cwp_gen(r, v : registers; annul, wcwp : std_ulogic; ncwp : cwptype;
cwp : out cwptype) is
begin
if (r.x.rstate = trap) or (r.x.rstate = dsu2) or (rstn = '0') then cwp := v.w.s.cwp;
elsif (wcwp = '1') and (annul = '0') then cwp := ncwp;
elsif r.m.wcwp = '1' then cwp := r.m.result(3-1 downto 0);
else cwp := r.d.cwp; end if;
end;
-- generate wcwp in ex stage
procedure cwp_ex(r : in registers; wcwp : out std_ulogic) is
begin
if (r.e.ctrl.inst(31 downto 30) = FMT3) and
(r.e.ctrl.inst(24 downto 19) = WRPSR)
then wcwp := not r.e.ctrl.annul; else wcwp := '0'; end if;
end;
-- generate next cwp & window under- and overflow traps
procedure cwp_ctrl(r : in registers; xc_wim : in std_logic_vector(8-1 downto 0);
inst : word; de_cwp : out cwptype; wovf_exc, wunf_exc, wcwp : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable wim : word;
variable ncwp : cwptype;
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
wovf_exc := '0'; wunf_exc := '0'; wim := (others => '0');
wim(8-1 downto 0) := xc_wim; ncwp := r.d.cwp; wcwp := '0';
if (op = FMT3) and ((op3 = RETT) or (op3 = RESTORE) or (op3 = SAVE)) then
wcwp := '1';
if (op3 = SAVE) then
if (not true) and (r.d.cwp = "000") then ncwp := "111";
else ncwp := r.d.cwp - 1 ; end if;
else
if (not true) and (r.d.cwp = "111") then ncwp := "000";
else ncwp := r.d.cwp + 1; end if;
end if;
if wim(conv_integer(ncwp)) = '1' then
if op3 = SAVE then wovf_exc := '1'; else wunf_exc := '1'; end if;
end if;
end if;
de_cwp := ncwp;
end;
-- generate register read address 1
procedure rs1_gen(r : registers; inst : word; rs1 : out std_logic_vector(4 downto 0);
rs1mod : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
rs1 := inst(18 downto 14); rs1mod := '0';
if (op = LDST) then
if ((r.d.cnt = "01") and ((op3(2) and not op3(3)) = '1')) or
(r.d.cnt = "10")
then rs1mod := '1'; rs1 := inst(29 downto 25); end if;
if ((r.d.cnt = "10") and (op3(3 downto 0) = "0111")) then
rs1(0) := '1';
end if;
end if;
end;
-- load/icc interlock detection
procedure lock_gen(r : registers; rs2, rd : std_logic_vector(4 downto 0);
rfa1, rfa2, rfrd : rfatype; inst : word; fpc_lock, mulinsn, divinsn : std_ulogic;
lldcheck1, lldcheck2, lldlock, lldchkra, lldchkex : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable cond : std_logic_vector(3 downto 0);
variable rs1 : std_logic_vector(4 downto 0);
variable i, ldcheck1, ldcheck2, ldchkra, ldchkex, ldcheck3 : std_ulogic;
variable ldlock, icc_check, bicc_hold, chkmul, y_check : std_ulogic;
variable lddlock : boolean;
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
op2 := inst(24 downto 22); cond := inst(28 downto 25);
rs1 := inst(18 downto 14); lddlock := false; i := inst(13);
ldcheck1 := '0'; ldcheck2 := '0'; ldcheck3 := '0'; ldlock := '0';
ldchkra := '1'; ldchkex := '1'; icc_check := '0'; bicc_hold := '0';
y_check := '0';
if (r.d.annul = '0') then
case op is
when FMT2 =>
if (op2 = BICC) and (cond(2 downto 0) /= "000") then
icc_check := '1';
end if;
when FMT3 =>
ldcheck1 := '1'; ldcheck2 := not i;
case op3 is
when TICC =>
if (cond(2 downto 0) /= "000") then icc_check := '1'; end if;
when RDY =>
ldcheck1 := '0'; ldcheck2 := '0';
if false then y_check := '1'; end if;
when RDWIM | RDTBR =>
ldcheck1 := '0'; ldcheck2 := '0';
when RDPSR =>
ldcheck1 := '0'; ldcheck2 := '0'; icc_check := '1';
if true then icc_check := '1'; end if;
-- when ADDX | ADDXCC | SUBX | SUBXCC =>
-- if true then icc_check := '1'; end if;
when SDIV | SDIVCC | UDIV | UDIVCC =>
if true then y_check := '1'; end if;
when FPOP1 | FPOP2 => ldcheck1:= '0'; ldcheck2 := '0';
when others =>
end case;
when LDST =>
ldcheck1 := '1'; ldchkra := '0';
case r.d.cnt is
when "00" =>
if (lddel = 2) and (op3(2) = '1') then ldcheck3 := '1'; end if;
ldcheck2 := not i; ldchkra := '1';
when "01" => ldcheck2 := not i;
when others => ldchkex := '0';
end case;
if (op3(2 downto 0) = "011") then lddlock := true; end if;
when others => null;
end case;
end if;
if true or true then
chkmul := mulinsn;
bicc_hold := bicc_hold or (icc_check and r.m.ctrl.wicc and (r.m.ctrl.cnt(0) or r.m.mul));
else chkmul := '0'; end if;
if true then
bicc_hold := bicc_hold or (y_check and (r.a.ctrl.wy or r.e.ctrl.wy));
chkmul := chkmul or divinsn;
end if;
bicc_hold := bicc_hold or (icc_check and (r.a.ctrl.wicc or r.e.ctrl.wicc));
if (((r.a.ctrl.ld or chkmul) and r.a.ctrl.wreg and ldchkra) = '1') and
(((ldcheck1 = '1') and (r.a.ctrl.rd = rfa1)) or
((ldcheck2 = '1') and (r.a.ctrl.rd = rfa2)) or
((ldcheck3 = '1') and (r.a.ctrl.rd = rfrd)))
then ldlock := '1'; end if;
if (((r.e.ctrl.ld or r.e.mac) and r.e.ctrl.wreg and ldchkex) = '1') and
((lddel = 2) or (false and (r.e.mac = '1')) or ((0 = 3) and (r.e.mul = '1'))) and
(((ldcheck1 = '1') and (r.e.ctrl.rd = rfa1)) or
((ldcheck2 = '1') and (r.e.ctrl.rd = rfa2)))
then ldlock := '1'; end if;
ldlock := ldlock or bicc_hold or fpc_lock;
lldcheck1 := ldcheck1; lldcheck2:= ldcheck2; lldlock := ldlock;
lldchkra := ldchkra; lldchkex := ldchkex;
end;
procedure fpbranch(inst : in word; fcc : in std_logic_vector(1 downto 0);
branch : out std_ulogic) is
variable cond : std_logic_vector(3 downto 0);
variable fbres : std_ulogic;
begin
cond := inst(28 downto 25);
case cond(2 downto 0) is
when "000" => fbres := '0'; -- fba, fbn
when "001" => fbres := fcc(1) or fcc(0);
when "010" => fbres := fcc(1) xor fcc(0);
when "011" => fbres := fcc(0);
when "100" => fbres := (not fcc(1)) and fcc(0);
when "101" => fbres := fcc(1);
when "110" => fbres := fcc(1) and not fcc(0);
when others => fbres := fcc(1) and fcc(0);
end case;
branch := cond(3) xor fbres;
end;
-- PC generation
procedure ic_ctrl(r : registers; inst : word; annul_all, ldlock, branch_true,
fbranch_true, cbranch_true, fccv, cccv : in std_ulogic;
cnt : out std_logic_vector(1 downto 0);
de_pc : out pctype; de_branch, ctrl_annul, de_annul, jmpl_inst, inull,
de_pv, ctrl_pv, de_hold_pc, ticc_exception, rett_inst, mulstart,
divstart : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable cond : std_logic_vector(3 downto 0);
variable hold_pc, annul_current, annul_next, branch, annul, pv : std_ulogic;
variable de_jmpl : std_ulogic;
begin
branch := '0'; annul_next := '0'; annul_current := '0'; pv := '1';
hold_pc := '0'; ticc_exception := '0'; rett_inst := '0';
op := inst(31 downto 30); op3 := inst(24 downto 19);
op2 := inst(24 downto 22); cond := inst(28 downto 25);
annul := inst(29); de_jmpl := '0'; cnt := "00";
mulstart := '0'; divstart := '0';
if r.d.annul = '0' then
case inst(31 downto 30) is
when CALL =>
branch := '1';
if r.d.inull = '1' then
hold_pc := '1'; annul_current := '1';
end if;
when FMT2 =>
if (op2 = BICC) or (FPEN and (op2 = FBFCC)) or (false and (op2 = CBCCC)) then
if (FPEN and (op2 = FBFCC)) then
branch := fbranch_true;
if fccv /= '1' then hold_pc := '1'; annul_current := '1'; end if;
elsif (false and (op2 = CBCCC)) then
branch := cbranch_true;
if cccv /= '1' then hold_pc := '1'; annul_current := '1'; end if;
else branch := branch_true; end if;
if hold_pc = '0' then
if (branch = '1') then
if (cond = BA) and (annul = '1') then annul_next := '1'; end if;
else annul_next := annul; end if;
if r.d.inull = '1' then -- contention with JMPL
hold_pc := '1'; annul_current := '1'; annul_next := '0';
end if;
end if;
end if;
when FMT3 =>
case op3 is
when UMUL | SMUL | UMULCC | SMULCC =>
if true and (0 /= 0) then mulstart := '1'; end if;
if true and (0 = 0) then
case r.d.cnt is
when "00" =>
cnt := "01"; hold_pc := '1'; pv := '0'; mulstart := '1';
when "01" =>
if mulo.nready = '1' then cnt := "00";
else cnt := "01"; pv := '0'; hold_pc := '1'; end if;
when others => null;
end case;
end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if true then
case r.d.cnt is
when "00" =>
cnt := "01"; hold_pc := '1'; pv := '0';
divstart := '1';
when "01" =>
if divo.nready = '1' then cnt := "00";
else cnt := "01"; pv := '0'; hold_pc := '1'; end if;
when others => null;
end case;
end if;
when TICC =>
if branch_true = '1' then ticc_exception := '1'; end if;
when RETT =>
rett_inst := '1'; --su := sregs.ps;
when JMPL =>
de_jmpl := '1';
when WRY =>
if false then
if inst(29 downto 25) = "10011" then -- %ASR19
case r.d.cnt is
when "00" =>
pv := '0'; cnt := "00"; hold_pc := '1';
if r.x.ipend = '1' then cnt := "01"; end if;
when "01" =>
cnt := "00";
when others =>
end case;
end if;
end if;
when others => null;
end case;
when others => -- LDST
case r.d.cnt is
when "00" =>
if (op3(2) = '1') or (op3(1 downto 0) = "11") then -- ST/LDST/SWAP/LDD
cnt := "01"; hold_pc := '1'; pv := '0';
end if;
when "01" =>
if (op3(2 downto 0) = "111") or (op3(3 downto 0) = "1101") or
((false or FPEN) and ((op3(5) & op3(2 downto 0)) = "1110"))
then -- LDD/STD/LDSTUB/SWAP
cnt := "10"; pv := '0'; hold_pc := '1';
else
cnt := "00";
end if;
when "10" =>
cnt := "00";
when others => null;
end case;
end case;
end if;
if ldlock = '1' then
cnt := r.d.cnt; annul_next := '0'; pv := '1';
end if;
hold_pc := (hold_pc or ldlock) and not annul_all;
if hold_pc = '1' then de_pc := r.d.pc; else de_pc := r.f.pc; end if;
annul_current := (annul_current or ldlock or annul_all);
ctrl_annul := r.d.annul or annul_all or annul_current;
pv := pv and not ((r.d.inull and not hold_pc) or annul_all);
jmpl_inst := de_jmpl and not annul_current;
annul_next := (r.d.inull and not hold_pc) or annul_next or annul_all;
if (annul_next = '1') or (rstn = '0') then
cnt := (others => '0');
end if;
de_hold_pc := hold_pc; de_branch := branch; de_annul := annul_next;
de_pv := pv; ctrl_pv := r.d.pv and
not ((r.d.annul and not r.d.pv) or annul_all or annul_current);
inull := (not rstn) or r.d.inull or hold_pc or annul_all;
end;
-- register write address generation
procedure rd_gen(r : registers; inst : word; wreg, ld : out std_ulogic;
rdo : out std_logic_vector(4 downto 0)) is
variable write_reg : std_ulogic;
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
begin
op := inst(31 downto 30);
op2 := inst(24 downto 22);
op3 := inst(24 downto 19);
write_reg := '0'; rd := inst(29 downto 25); ld := '0';
case op is
when CALL =>
write_reg := '1'; rd := "01111"; -- CALL saves PC in r[15] (%o7)
when FMT2 =>
if (op2 = SETHI) then write_reg := '1'; end if;
when FMT3 =>
case op3 is
when UMUL | SMUL | UMULCC | SMULCC =>
if true then
if (((mulo.nready = '1') and (r.d.cnt /= "00")) or (0 /= 0)) then
write_reg := '1';
end if;
else write_reg := '1'; end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if true then
if (divo.nready = '1') and (r.d.cnt /= "00") then
write_reg := '1';
end if;
else write_reg := '1'; end if;
when RETT | WRPSR | WRY | WRWIM | WRTBR | TICC | FLUSH => null;
when FPOP1 | FPOP2 => null;
when CPOP1 | CPOP2 => null;
when others => write_reg := '1';
end case;
when others => -- LDST
ld := not op3(2);
if (op3(2) = '0') and not ((false or FPEN) and (op3(5) = '1'))
then write_reg := '1'; end if;
case op3 is
when SWAP | SWAPA | LDSTUB | LDSTUBA =>
if r.d.cnt = "00" then write_reg := '1'; ld := '1'; end if;
when others => null;
end case;
if r.d.cnt = "01" then
case op3 is
when LDD | LDDA | LDDC | LDDF => rd(0) := '1';
when others =>
end case;
end if;
end case;
if (rd = "00000") then write_reg := '0'; end if;
wreg := write_reg; rdo := rd;
end;
-- immediate data generation
function imm_data (r : registers; insn : word)
return word is
variable immediate_data, inst : word;
begin
immediate_data := (others => '0'); inst := insn;
case inst(31 downto 30) is
when FMT2 =>
immediate_data := inst(21 downto 0) & "0000000000";
when others => -- LDST
immediate_data(31 downto 13) := (others => inst(12));
immediate_data(12 downto 0) := inst(12 downto 0);
end case;
return(immediate_data);
end;
-- read special registers
function get_spr (r : registers) return word is
variable spr : word;
begin
spr := (others => '0');
case r.e.ctrl.inst(24 downto 19) is
when RDPSR => spr(31 downto 5) := conv_std_logic_vector(15,4) &
conv_std_logic_vector(3,4) & r.m.icc & "000000" & r.w.s.ec & r.w.s.ef &
r.w.s.pil & r.e.su & r.w.s.ps & r.e.et;
spr(3-1 downto 0) := r.e.cwp;
when RDTBR => spr(31 downto 4) := r.w.s.tba & r.w.s.tt;
when RDWIM => spr(8-1 downto 0) := r.w.s.wim;
when others =>
end case;
return(spr);
end;
-- immediate data select
function imm_select(inst : word) return boolean is
variable imm : boolean;
begin
imm := false;
case inst(31 downto 30) is
when FMT2 =>
case inst(24 downto 22) is
when SETHI => imm := true;
when others =>
end case;
when FMT3 =>
case inst(24 downto 19) is
when RDWIM | RDPSR | RDTBR => imm := true;
when others => if (inst(13) = '1') then imm := true; end if;
end case;
when LDST =>
if (inst(13) = '1') then imm := true; end if;
when others =>
end case;
return(imm);
end;
-- EXE operation
procedure alu_op(r : in registers; iop1, iop2 : in word; me_icc : std_logic_vector(3 downto 0);
my, ldbp : std_ulogic; aop1, aop2 : out word; aluop : out std_logic_vector(2 downto 0);
alusel : out std_logic_vector(1 downto 0); aluadd : out std_ulogic;
shcnt : out std_logic_vector(4 downto 0); sari, shleft, ymsb,
mulins, divins, mulstep, macins, ldbp2, invop2 : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable icc : std_logic_vector(3 downto 0);
variable y0 : std_ulogic;
begin
op := r.a.ctrl.inst(31 downto 30);
op2 := r.a.ctrl.inst(24 downto 22);
op3 := r.a.ctrl.inst(24 downto 19);
aop1 := iop1; aop2 := iop2; ldbp2 := ldbp;
aluop := EXE_NOP; alusel := EXE_RES_MISC; aluadd := '1';
shcnt := iop2(4 downto 0); sari := '0'; shleft := '0'; invop2 := '0';
ymsb := iop1(0); mulins := '0'; divins := '0'; mulstep := '0';
macins := '0';
if r.e.ctrl.wy = '1' then y0 := my;
elsif r.m.ctrl.wy = '1' then y0 := r.m.y(0);
elsif r.x.ctrl.wy = '1' then y0 := r.x.y(0);
else y0 := r.w.s.y(0); end if;
if r.e.ctrl.wicc = '1' then icc := me_icc;
elsif r.m.ctrl.wicc = '1' then icc := r.m.icc;
elsif r.x.ctrl.wicc = '1' then icc := r.x.icc;
else icc := r.w.s.icc; end if;
case op is
when CALL =>
aluop := EXE_LINK;
when FMT2 =>
case op2 is
when SETHI => aluop := EXE_PASS2;
when others =>
end case;
when FMT3 =>
case op3 is
when IADD | ADDX | ADDCC | ADDXCC | TADDCC | TADDCCTV | SAVE | RESTORE |
TICC | JMPL | RETT => alusel := EXE_RES_ADD;
when ISUB | SUBX | SUBCC | SUBXCC | TSUBCC | TSUBCCTV =>
alusel := EXE_RES_ADD; aluadd := '0'; aop2 := not iop2; invop2 := '1';
when MULSCC => alusel := EXE_RES_ADD;
aop1 := (icc(3) xor icc(1)) & iop1(31 downto 1);
if y0 = '0' then aop2 := (others => '0'); ldbp2 := '0'; end if;
mulstep := '1';
when UMUL | UMULCC | SMUL | SMULCC =>
if true then mulins := '1'; end if;
when UMAC | SMAC =>
if false then mulins := '1'; macins := '1'; end if;
when UDIV | UDIVCC | SDIV | SDIVCC =>
if true then
aluop := EXE_DIV; alusel := EXE_RES_LOGIC; divins := '1';
end if;
when IAND | ANDCC => aluop := EXE_AND; alusel := EXE_RES_LOGIC;
when ANDN | ANDNCC => aluop := EXE_ANDN; alusel := EXE_RES_LOGIC;
when IOR | ORCC => aluop := EXE_OR; alusel := EXE_RES_LOGIC;
when ORN | ORNCC => aluop := EXE_ORN; alusel := EXE_RES_LOGIC;
when IXNOR | XNORCC => aluop := EXE_XNOR; alusel := EXE_RES_LOGIC;
when XORCC | IXOR | WRPSR | WRWIM | WRTBR | WRY =>
aluop := EXE_XOR; alusel := EXE_RES_LOGIC;
when RDPSR | RDTBR | RDWIM => aluop := EXE_SPR;
when RDY => aluop := EXE_RDY;
when ISLL => aluop := EXE_SLL; alusel := EXE_RES_SHIFT; shleft := '1';
shcnt := not iop2(4 downto 0); invop2 := '1';
when ISRL => aluop := EXE_SRL; alusel := EXE_RES_SHIFT;
when ISRA => aluop := EXE_SRA; alusel := EXE_RES_SHIFT; sari := iop1(31);
when FPOP1 | FPOP2 =>
when others =>
end case;
when others => -- LDST
case r.a.ctrl.cnt is
when "00" =>
alusel := EXE_RES_ADD;
when "01" =>
case op3 is
when LDD | LDDA | LDDC => alusel := EXE_RES_ADD;
when LDDF => alusel := EXE_RES_ADD;
when SWAP | SWAPA | LDSTUB | LDSTUBA => alusel := EXE_RES_ADD;
when STF | STDF =>
when others =>
aluop := EXE_PASS1;
if op3(2) = '1' then
if op3(1 downto 0) = "01" then aluop := EXE_STB;
elsif op3(1 downto 0) = "10" then aluop := EXE_STH; end if;
end if;
end case;
when "10" =>
aluop := EXE_PASS1;
if op3(2) = '1' then -- ST
if (op3(3) and not op3(1))= '1' then aluop := EXE_ONES; end if; -- LDSTUB/A
end if;
when others =>
end case;
end case;
end;
function ra_inull_gen(r, v : registers) return std_ulogic is
variable de_inull : std_ulogic;
begin
de_inull := '0';
if ((v.e.jmpl or v.e.ctrl.rett) and not v.e.ctrl.annul and not (r.e.jmpl and not r.e.ctrl.annul)) = '1' then de_inull := '1'; end if;
if ((v.a.jmpl or v.a.ctrl.rett) and not v.a.ctrl.annul and not (r.a.jmpl and not r.a.ctrl.annul)) = '1' then de_inull := '1'; end if;
return(de_inull);
end;
-- operand generation
procedure op_mux(r : in registers; rfd, ed, md, xd, im : in word;
rsel : in std_logic_vector(2 downto 0);
ldbp : out std_ulogic; d : out word) is
begin
ldbp := '0';
case rsel is
when "000" => d := rfd;
when "001" => d := ed;
when "010" => d := md; if lddel = 1 then ldbp := r.m.ctrl.ld; end if;
when "011" => d := xd;
when "100" => d := im;
when "101" => d := (others => '0');
when "110" => d := r.w.result;
when others => d := (others => '-');
end case;
end;
procedure op_find(r : in registers; ldchkra : std_ulogic; ldchkex : std_ulogic;
rs1 : std_logic_vector(4 downto 0); ra : rfatype; im : boolean; rfe : out std_ulogic;
osel : out std_logic_vector(2 downto 0); ldcheck : std_ulogic) is
begin
rfe := '0';
if im then osel := "100";
elsif rs1 = "00000" then osel := "101"; -- %g0
elsif ((r.a.ctrl.wreg and ldchkra) = '1') and (ra = r.a.ctrl.rd) then osel := "001";
elsif ((r.e.ctrl.wreg and ldchkex) = '1') and (ra = r.e.ctrl.rd) then osel := "010";
elsif r.m.ctrl.wreg = '1' and (ra = r.m.ctrl.rd) then osel := "011";
elsif (irfwt = 0) and r.x.ctrl.wreg = '1' and (ra = r.x.ctrl.rd) then osel := "110";
else osel := "000"; rfe := ldcheck; end if;
end;
-- generate carry-in for alu
procedure cin_gen(r : registers; me_cin : in std_ulogic; cin : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable ncin : std_ulogic;
begin
op := r.a.ctrl.inst(31 downto 30); op3 := r.a.ctrl.inst(24 downto 19);
if r.e.ctrl.wicc = '1' then ncin := me_cin;
else ncin := r.m.icc(0); end if;
cin := '0';
case op is
when FMT3 =>
case op3 is
when ISUB | SUBCC | TSUBCC | TSUBCCTV => cin := '1';
when ADDX | ADDXCC => cin := ncin;
when SUBX | SUBXCC => cin := not ncin;
when others => null;
end case;
when others => null;
end case;
end;
procedure logic_op(r : registers; aluin1, aluin2, mey : word;
ymsb : std_ulogic; logicres, y : out word) is
variable logicout : word;
begin
case r.e.aluop is
when EXE_AND => logicout := aluin1 and aluin2;
when EXE_ANDN => logicout := aluin1 and not aluin2;
when EXE_OR => logicout := aluin1 or aluin2;
when EXE_ORN => logicout := aluin1 or not aluin2;
when EXE_XOR => logicout := aluin1 xor aluin2;
when EXE_XNOR => logicout := aluin1 xor not aluin2;
when EXE_DIV =>
if true then logicout := aluin2;
else logicout := (others => '-'); end if;
when others => logicout := (others => '-');
end case;
if (r.e.ctrl.wy and r.e.mulstep) = '1' then
y := ymsb & r.m.y(31 downto 1);
elsif r.e.ctrl.wy = '1' then y := logicout;
elsif r.m.ctrl.wy = '1' then y := mey;
elsif false and (r.x.mac = '1') then y := mulo.result(63 downto 32);
elsif r.x.ctrl.wy = '1' then y := r.x.y;
else y := r.w.s.y; end if;
logicres := logicout;
end;
procedure misc_op(r : registers; wpr : watchpoint_registers;
aluin1, aluin2, ldata, mey : word;
mout, edata : out word) is
variable miscout, bpdata, stdata : word;
variable wpi : integer;
begin
wpi := 0; miscout := r.e.ctrl.pc(31 downto 2) & "00";
edata := aluin1; bpdata := aluin1;
if ((r.x.ctrl.wreg and r.x.ctrl.ld and not r.x.ctrl.annul) = '1') and
(r.x.ctrl.rd = r.e.ctrl.rd) and (r.e.ctrl.inst(31 downto 30) = LDST) and
(r.e.ctrl.cnt /= "10")
then bpdata := ldata; end if;
case r.e.aluop is
when EXE_STB => miscout := bpdata(7 downto 0) & bpdata(7 downto 0) &
bpdata(7 downto 0) & bpdata(7 downto 0);
edata := miscout;
when EXE_STH => miscout := bpdata(15 downto 0) & bpdata(15 downto 0);
edata := miscout;
when EXE_PASS1 => miscout := bpdata; edata := miscout;
when EXE_PASS2 => miscout := aluin2;
when EXE_ONES => miscout := (others => '1');
edata := miscout;
when EXE_RDY =>
if true and (r.m.ctrl.wy = '1') then miscout := mey;
else miscout := r.m.y; end if;
if (NWP > 0) and (r.e.ctrl.inst(18 downto 17) = "11") then
wpi := conv_integer(r.e.ctrl.inst(16 downto 15));
if r.e.ctrl.inst(14) = '0' then miscout := wpr(wpi).addr & '0' & wpr(wpi).exec;
else miscout := wpr(wpi).mask & wpr(wpi).load & wpr(wpi).store; end if;
end if;
if (r.e.ctrl.inst(18 downto 17) = "10") and (r.e.ctrl.inst(14) = '1') then --%ASR17
miscout := asr17_gen(r);
end if;
if false then
if (r.e.ctrl.inst(18 downto 14) = "10010") then --%ASR18
if ((r.m.mac = '1') and not false) or ((r.x.mac = '1') and false) then
miscout := mulo.result(31 downto 0); -- data forward of asr18
else miscout := r.w.s.asr18; end if;
else
if ((r.m.mac = '1') and not false) or ((r.x.mac = '1') and false) then
miscout := mulo.result(63 downto 32); -- data forward Y
end if;
end if;
end if;
when EXE_SPR =>
miscout := get_spr(r);
when others => null;
end case;
mout := miscout;
end;
procedure alu_select(r : registers; addout : std_logic_vector(32 downto 0);
op1, op2 : word; shiftout, logicout, miscout : word; res : out word;
me_icc : std_logic_vector(3 downto 0);
icco : out std_logic_vector(3 downto 0); divz : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable icc : std_logic_vector(3 downto 0);
variable aluresult : word;
begin
op := r.e.ctrl.inst(31 downto 30); op3 := r.e.ctrl.inst(24 downto 19);
icc := (others => '0');
case r.e.alusel is
when EXE_RES_ADD =>
aluresult := addout(32 downto 1);
if r.e.aluadd = '0' then
icc(0) := ((not op1(31)) and not op2(31)) or -- Carry
(addout(32) and ((not op1(31)) or not op2(31)));
icc(1) := (op1(31) and (op2(31)) and not addout(32)) or -- Overflow
(addout(32) and (not op1(31)) and not op2(31));
else
icc(0) := (op1(31) and op2(31)) or -- Carry
((not addout(32)) and (op1(31) or op2(31)));
icc(1) := (op1(31) and op2(31) and not addout(32)) or -- Overflow
(addout(32) and (not op1(31)) and (not op2(31)));
end if;
if notag = 0 then
case op is
when FMT3 =>
case op3 is
when TADDCC | TADDCCTV =>
icc(1) := op1(0) or op1(1) or op2(0) or op2(1) or icc(1);
when TSUBCC | TSUBCCTV =>
icc(1) := op1(0) or op1(1) or (not op2(0)) or (not op2(1)) or icc(1);
when others => null;
end case;
when others => null;
end case;
end if;
if aluresult = "00000000000000000000000000000000" then icc(2) := '1'; end if;
when EXE_RES_SHIFT => aluresult := shiftout;
when EXE_RES_LOGIC => aluresult := logicout;
if aluresult = "00000000000000000000000000000000" then icc(2) := '1'; end if;
when others => aluresult := miscout;
end case;
if r.e.jmpl = '1' then aluresult := r.e.ctrl.pc(31 downto 2) & "00"; end if;
icc(3) := aluresult(31); divz := icc(2);
if r.e.ctrl.wicc = '1' then
if (op = FMT3) and (op3 = WRPSR) then icco := logicout(23 downto 20);
else icco := icc; end if;
elsif r.m.ctrl.wicc = '1' then icco := me_icc;
elsif r.x.ctrl.wicc = '1' then icco := r.x.icc;
else icco := r.w.s.icc; end if;
res := aluresult;
end;
procedure dcache_gen(r, v : registers; dci : out dc_in_type;
link_pc, jump, force_a2, load : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable su : std_ulogic;
begin
op := r.e.ctrl.inst(31 downto 30); op3 := r.e.ctrl.inst(24 downto 19);
dci.signed := '0'; dci.lock := '0'; dci.dsuen := '0'; dci.size := SZWORD;
if op = LDST then
case op3 is
when LDUB | LDUBA => dci.size := SZBYTE;
when LDSTUB | LDSTUBA => dci.size := SZBYTE; dci.lock := '1';
when LDUH | LDUHA => dci.size := SZHALF;
when LDSB | LDSBA => dci.size := SZBYTE; dci.signed := '1';
when LDSH | LDSHA => dci.size := SZHALF; dci.signed := '1';
when LD | LDA | LDF | LDC => dci.size := SZWORD;
when SWAP | SWAPA => dci.size := SZWORD; dci.lock := '1';
when LDD | LDDA | LDDF | LDDC => dci.size := SZDBL;
when STB | STBA => dci.size := SZBYTE;
when STH | STHA => dci.size := SZHALF;
when ST | STA | STF => dci.size := SZWORD;
when ISTD | STDA => dci.size := SZDBL;
when STDF | STDFQ => if FPEN then dci.size := SZDBL; end if;
when STDC | STDCQ => if false then dci.size := SZDBL; end if;
when others => dci.size := SZWORD; dci.lock := '0'; dci.signed := '0';
end case;
end if;
link_pc := '0'; jump:= '0'; force_a2 := '0'; load := '0';
dci.write := '0'; dci.enaddr := '0'; dci.read := not op3(2);
-- load/store control decoding
if (r.e.ctrl.annul = '0') then
case op is
when CALL => link_pc := '1';
when FMT3 =>
case op3 is
when JMPL => jump := '1'; link_pc := '1';
when RETT => jump := '1';
when others => null;
end case;
when LDST =>
case r.e.ctrl.cnt is
when "00" =>
dci.read := op3(3) or not op3(2); -- LD/LDST/SWAP
load := op3(3) or not op3(2);
dci.enaddr := '1';
when "01" =>
force_a2 := not op3(2); -- LDD
load := not op3(2); dci.enaddr := not op3(2);
if op3(3 downto 2) = "01" then -- ST/STD
dci.write := '1';
end if;
if op3(3 downto 2) = "11" then -- LDST/SWAP
dci.enaddr := '1';
end if;
when "10" => -- STD/LDST/SWAP
dci.write := '1';
when others => null;
end case;
if (r.e.ctrl.trap or (v.x.ctrl.trap and not v.x.ctrl.annul)) = '1' then
dci.enaddr := '0';
end if;
when others => null;
end case;
end if;
if ((r.x.ctrl.rett and not r.x.ctrl.annul) = '1') then su := r.w.s.ps;
else su := r.w.s.s; end if;
if su = '1' then dci.asi := "00001011"; else dci.asi := "00001010"; end if;
if (op3(4) = '1') and ((op3(5) = '0') or not false) then
dci.asi := r.e.ctrl.inst(12 downto 5);
end if;
end;
procedure fpstdata(r : in registers; edata, eres : in word; fpstdata : in std_logic_vector(31 downto 0);
edata2, eres2 : out word) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
begin
edata2 := edata; eres2 := eres;
op := r.e.ctrl.inst(31 downto 30); op3 := r.e.ctrl.inst(24 downto 19);
if FPEN then
if FPEN and (op = LDST) and ((op3(5 downto 4) & op3(2)) = "101") and (r.e.ctrl.cnt /= "00") then
edata2 := fpstdata; eres2 := fpstdata;
end if;
end if;
end;
function ld_align(data : dcdtype; set : std_logic_vector(0 downto 0);
size, laddr : std_logic_vector(1 downto 0); signed : std_ulogic) return word is
variable align_data, rdata : word;
begin
align_data := data(conv_integer(set)); rdata := (others => '0');
case size is
when "00" => -- byte read
case laddr is
when "00" =>
rdata(7 downto 0) := align_data(31 downto 24);
if signed = '1' then rdata(31 downto 8) := (others => align_data(31)); end if;
when "01" =>
rdata(7 downto 0) := align_data(23 downto 16);
if signed = '1' then rdata(31 downto 8) := (others => align_data(23)); end if;
when "10" =>
rdata(7 downto 0) := align_data(15 downto 8);
if signed = '1' then rdata(31 downto 8) := (others => align_data(15)); end if;
when others =>
rdata(7 downto 0) := align_data(7 downto 0);
if signed = '1' then rdata(31 downto 8) := (others => align_data(7)); end if;
end case;
when "01" => -- half-word read
if laddr(1) = '1' then
rdata(15 downto 0) := align_data(15 downto 0);
if signed = '1' then rdata(31 downto 15) := (others => align_data(15)); end if;
else
rdata(15 downto 0) := align_data(31 downto 16);
if signed = '1' then rdata(31 downto 15) := (others => align_data(31)); end if;
end if;
when others => -- single and double word read
rdata := align_data;
end case;
return(rdata);
end;
procedure mem_trap(r : registers; wpr : watchpoint_registers;
annul, holdn : in std_ulogic;
trapout, iflush, nullify, werrout : out std_ulogic;
tt : out std_logic_vector(5 downto 0)) is
variable cwp : std_logic_vector(3-1 downto 0);
variable cwpx : std_logic_vector(5 downto 3);
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable nalign_d : std_ulogic;
variable trap, werr : std_ulogic;
begin
op := r.m.ctrl.inst(31 downto 30); op2 := r.m.ctrl.inst(24 downto 22);
op3 := r.m.ctrl.inst(24 downto 19);
cwpx := r.m.result(5 downto 3); cwpx(5) := '0';
iflush := '0'; trap := r.m.ctrl.trap; nullify := annul;
tt := r.m.ctrl.tt; werr := (dco.werr or r.m.werr) and not r.w.s.dwt;
nalign_d := r.m.nalign or r.m.result(2);
if ((annul or trap) /= '1') and (r.m.ctrl.pv = '1') then
if (werr and holdn) = '1' then
trap := '1'; tt := TT_DSEX; werr := '0';
if op = LDST then nullify := '1'; end if;
end if;
end if;
if ((annul or trap) /= '1') then
case op is
when FMT2 =>
case op2 is
when FBFCC =>
if FPEN and (fpo.exc = '1') then trap := '1'; tt := TT_FPEXC; end if;
when CBCCC =>
if false and (cpo.exc = '1') then trap := '1'; tt := TT_CPEXC; end if;
when others => null;
end case;
when FMT3 =>
case op3 is
when WRPSR =>
if (orv(cwpx) = '1') then trap := '1'; tt := TT_IINST; end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if true then
if r.m.divz = '1' then trap := '1'; tt := TT_DIV; end if;
end if;
when JMPL | RETT =>
if r.m.nalign = '1' then trap := '1'; tt := TT_UNALA; end if;
when TADDCCTV | TSUBCCTV =>
if (notag = 0) and (r.m.icc(1) = '1') then
trap := '1'; tt := TT_TAG;
end if;
when FLUSH => iflush := '1';
when FPOP1 | FPOP2 =>
if FPEN and (fpo.exc = '1') then trap := '1'; tt := TT_FPEXC; end if;
when CPOP1 | CPOP2 =>
if false and (cpo.exc = '1') then trap := '1'; tt := TT_CPEXC; end if;
when others => null;
end case;
when LDST =>
if r.m.ctrl.cnt = "00" then
case op3 is
when LDDF | STDF | STDFQ =>
if FPEN then
if nalign_d = '1' then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif (fpo.exc and r.m.ctrl.pv) = '1'
then trap := '1'; tt := TT_FPEXC; nullify := '1'; end if;
end if;
when LDDC | STDC | STDCQ =>
if false then
if nalign_d = '1' then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif ((cpo.exc and r.m.ctrl.pv) = '1')
then trap := '1'; tt := TT_CPEXC; nullify := '1'; end if;
end if;
when LDD | ISTD | LDDA | STDA =>
if r.m.result(2 downto 0) /= "000" then
trap := '1'; tt := TT_UNALA; nullify := '1';
end if;
when LDF | LDFSR | STFSR | STF =>
if FPEN and (r.m.nalign = '1') then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif FPEN and ((fpo.exc and r.m.ctrl.pv) = '1')
then trap := '1'; tt := TT_FPEXC; nullify := '1'; end if;
when LDC | LDCSR | STCSR | STC =>
if false and (r.m.nalign = '1') then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif false and ((cpo.exc and r.m.ctrl.pv) = '1')
then trap := '1'; tt := TT_CPEXC; nullify := '1'; end if;
when LD | LDA | ST | STA | SWAP | SWAPA =>
if r.m.result(1 downto 0) /= "00" then
trap := '1'; tt := TT_UNALA; nullify := '1';
end if;
when LDUH | LDUHA | LDSH | LDSHA | STH | STHA =>
if r.m.result(0) /= '0' then
trap := '1'; tt := TT_UNALA; nullify := '1';
end if;
when others => null;
end case;
for i in 1 to NWP loop
if ((((wpr(i-1).load and not op3(2)) or (wpr(i-1).store and op3(2))) = '1') and
(((wpr(i-1).addr xor r.m.result(31 downto 2)) and wpr(i-1).mask) = "000000000000000000000000000000"))
then trap := '1'; tt := TT_WATCH; nullify := '1'; end if;
end loop;
end if;
when others => null;
end case;
end if;
if (rstn = '0') or (r.x.rstate = dsu2) then werr := '0'; end if;
trapout := trap; werrout := werr;
end;
procedure irq_trap(r : in registers;
ir : in irestart_register;
irl : in std_logic_vector(3 downto 0);
annul : in std_ulogic;
pv : in std_ulogic;
trap : in std_ulogic;
tt : in std_logic_vector(5 downto 0);
nullify : in std_ulogic;
irqen : out std_ulogic;
irqen2 : out std_ulogic;
nullify2 : out std_ulogic;
trap2, ipend : out std_ulogic;
tt2 : out std_logic_vector(5 downto 0)) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable pend : std_ulogic;
begin
nullify2 := nullify; trap2 := trap; tt2 := tt;
op := r.m.ctrl.inst(31 downto 30); op3 := r.m.ctrl.inst(24 downto 19);
irqen := '1'; irqen2 := r.m.irqen;
if (annul or trap) = '0' then
if ((op = FMT3) and (op3 = WRPSR)) then irqen := '0'; end if;
end if;
if (irl = "1111") or (irl > r.w.s.pil) then
pend := r.m.irqen and r.m.irqen2 and r.w.s.et and not ir.pwd;
else pend := '0'; end if;
ipend := pend;
if ((not annul) and pv and (not trap) and pend) = '1' then
trap2 := '1'; tt2 := "01" & irl;
if op = LDST then nullify2 := '1'; end if;
end if;
end;
procedure irq_intack(r : in registers; holdn : in std_ulogic; intack: out std_ulogic) is
begin
intack := '0';
if r.x.rstate = trap then
if r.w.s.tt(7 downto 4) = "0001" then intack := '1'; end if;
end if;
end;
-- write special registers
procedure sp_write (r : registers; wpr : watchpoint_registers;
s : out special_register_type; vwpr : out watchpoint_registers) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable i : integer range 0 to 3;
begin
op := r.x.ctrl.inst(31 downto 30);
op2 := r.x.ctrl.inst(24 downto 22);
op3 := r.x.ctrl.inst(24 downto 19);
s := r.w.s;
rd := r.x.ctrl.inst(29 downto 25);
vwpr := wpr;
case op is
when FMT3 =>
case op3 is
when WRY =>
if rd = "00000" then
s.y := r.x.result;
elsif false and (rd = "10010") then
s.asr18 := r.x.result;
elsif (rd = "10001") then
s.dwt := r.x.result(14);
if (svt = 1) then s.svt := r.x.result(13); end if;
elsif rd(4 downto 3) = "11" then -- %ASR24 - %ASR31
case rd(2 downto 0) is
when "000" =>
vwpr(0).addr := r.x.result(31 downto 2);
vwpr(0).exec := r.x.result(0);
when "001" =>
vwpr(0).mask := r.x.result(31 downto 2);
vwpr(0).load := r.x.result(1);
vwpr(0).store := r.x.result(0);
when "010" =>
vwpr(1).addr := r.x.result(31 downto 2);
vwpr(1).exec := r.x.result(0);
when "011" =>
vwpr(1).mask := r.x.result(31 downto 2);
vwpr(1).load := r.x.result(1);
vwpr(1).store := r.x.result(0);
when "100" =>
vwpr(2).addr := r.x.result(31 downto 2);
vwpr(2).exec := r.x.result(0);
when "101" =>
vwpr(2).mask := r.x.result(31 downto 2);
vwpr(2).load := r.x.result(1);
vwpr(2).store := r.x.result(0);
when "110" =>
vwpr(3).addr := r.x.result(31 downto 2);
vwpr(3).exec := r.x.result(0);
when others => -- "111"
vwpr(3).mask := r.x.result(31 downto 2);
vwpr(3).load := r.x.result(1);
vwpr(3).store := r.x.result(0);
end case;
end if;
when WRPSR =>
s.cwp := r.x.result(3-1 downto 0);
s.icc := r.x.result(23 downto 20);
s.ec := r.x.result(13);
if FPEN then s.ef := r.x.result(12); end if;
s.pil := r.x.result(11 downto 8);
s.s := r.x.result(7);
s.ps := r.x.result(6);
s.et := r.x.result(5);
when WRWIM =>
s.wim := r.x.result(8-1 downto 0);
when WRTBR =>
s.tba := r.x.result(31 downto 12);
when SAVE =>
if (not true) and (r.w.s.cwp = "000") then s.cwp := "111";
else s.cwp := r.w.s.cwp - 1 ; end if;
when RESTORE =>
if (not true) and (r.w.s.cwp = "111") then s.cwp := "000";
else s.cwp := r.w.s.cwp + 1; end if;
when RETT =>
if (not true) and (r.w.s.cwp = "111") then s.cwp := "000";
else s.cwp := r.w.s.cwp + 1; end if;
s.s := r.w.s.ps;
s.et := '1';
when others => null;
end case;
when others => null;
end case;
if r.x.ctrl.wicc = '1' then s.icc := r.x.icc; end if;
if r.x.ctrl.wy = '1' then s.y := r.x.y; end if;
if false and (r.x.mac = '1') then
s.asr18 := mulo.result(31 downto 0);
s.y := mulo.result(63 downto 32);
end if;
end;
function npc_find (r : registers) return std_logic_vector is
variable npc : std_logic_vector(2 downto 0);
begin
npc := "011";
if r.m.ctrl.pv = '1' then npc := "000";
elsif r.e.ctrl.pv = '1' then npc := "001";
elsif r.a.ctrl.pv = '1' then npc := "010";
elsif r.d.pv = '1' then npc := "011";
elsif 2 /= 0 then npc := "100"; end if;
return(npc);
end;
function npc_gen (r : registers) return word is
variable npc : std_logic_vector(31 downto 0);
begin
npc := r.a.ctrl.pc(31 downto 2) & "00";
case r.x.npc is
when "000" => npc(31 downto 2) := r.x.ctrl.pc(31 downto 2);
when "001" => npc(31 downto 2) := r.m.ctrl.pc(31 downto 2);
when "010" => npc(31 downto 2) := r.e.ctrl.pc(31 downto 2);
when "011" => npc(31 downto 2) := r.a.ctrl.pc(31 downto 2);
when others =>
if 2 /= 0 then npc(31 downto 2) := r.d.pc(31 downto 2); end if;
end case;
return(npc);
end;
procedure mul_res(r : registers; asr18in : word; result, y, asr18 : out word;
icc : out std_logic_vector(3 downto 0)) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
begin
op := r.m.ctrl.inst(31 downto 30); op3 := r.m.ctrl.inst(24 downto 19);
result := r.m.result; y := r.m.y; icc := r.m.icc; asr18 := asr18in;
case op is
when FMT3 =>
case op3 is
when UMUL | SMUL =>
if true then
result := mulo.result(31 downto 0);
y := mulo.result(63 downto 32);
end if;
when UMULCC | SMULCC =>
if true then
result := mulo.result(31 downto 0); icc := mulo.icc;
y := mulo.result(63 downto 32);
end if;
when UMAC | SMAC =>
if false and not false then
result := mulo.result(31 downto 0);
asr18 := mulo.result(31 downto 0);
y := mulo.result(63 downto 32);
end if;
when UDIV | SDIV =>
if true then
result := divo.result(31 downto 0);
end if;
when UDIVCC | SDIVCC =>
if true then
result := divo.result(31 downto 0); icc := divo.icc;
end if;
when others => null;
end case;
when others => null;
end case;
end;
function powerdwn(r : registers; trap : std_ulogic; rp : pwd_register_type) return std_ulogic is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable pd : std_ulogic;
begin
op := r.x.ctrl.inst(31 downto 30);
op3 := r.x.ctrl.inst(24 downto 19);
rd := r.x.ctrl.inst(29 downto 25);
pd := '0';
if (not (r.x.ctrl.annul or trap) and r.x.ctrl.pv) = '1' then
if ((op = FMT3) and (op3 = WRY) and (rd = "10011")) then pd := '1'; end if;
pd := pd or rp.pwd;
end if;
return(pd);
end;
signal dummy : std_ulogic;
signal cpu_index : std_logic_vector(3 downto 0);
signal disasen : std_ulogic;
signal dataToCache : std_logic_vector(31 downto 0);
signal triggerCPFault : std_ulogic;
-- Signals used for tracking if a handler fired and which one
signal dfp_trap_vector : std_logic_vector(124 downto 0);
signal or_reduce_1 : std_logic;
signal dfp_delay_start : integer range 0 to 15;
signal dfp_trap_mem : std_logic_vector(dfp_trap_vector'left downto dfp_trap_vector'right);
signal handlerTrap : std_ulogic;
-- Signals that serve as shadow signals for variables used in the pairs
signal V_A_ET_shadow : STD_ULOGIC;
signal EX_ADD_RES32DOWNTO34DOWNTO3_shadow : STD_LOGIC_VECTOR(4 downto 3);
signal ICNT_shadow : STD_ULOGIC;
signal EX_OP1_shadow : WORD;
signal V_M_CTRL_PC_shadow : PCTYPE;
signal V_E_CTRL_PC3DOWNTO2_shadow : std_logic_vector(3 downto 2);
signal DE_REN1_shadow : STD_ULOGIC;
signal DE_INST_shadow : WORD;
signal V_A_CTRL_CNT_shadow : OP_TYPE;
signal V_F_PC3DOWNTO2_shadow : std_logic_vector(3 downto 2);
signal V_W_S_TT_shadow : STD_LOGIC_VECTOR(7 downto 0);
signal V_X_RESULT6DOWNTO0_shadow : std_logic_vector(6 downto 0);
signal EX_JUMP_ADDRESS3DOWNTO2_shadow : std_logic_vector(3 downto 2);
signal V_E_ALUCIN_shadow : STD_ULOGIC;
signal V_D_PC3DOWNTO2_shadow : std_logic_vector(3 downto 2);
signal V_A_CTRL_PV_shadow : STD_ULOGIC;
signal V_E_CTRL_shadow : PIPELINE_CTRL_TYPE;
signal V_M_CTRL_shadow : PIPELINE_CTRL_TYPE;
signal V_M_RESULT1DOWNTO0_shadow : std_logic_vector(1 downto 0);
signal EX_SHCNT_shadow : ASI_TYPE;
signal V_M_DCI_SIZE_shadow : OP_TYPE;
signal V_X_CTRL_ANNUL_shadow : STD_ULOGIC;
signal V_X_MEXC_shadow : STD_ULOGIC;
signal TBUFCNTX_shadow : STD_LOGIC_VECTOR(6 downto 0);
signal V_A_CTRL_WY_shadow : STD_ULOGIC;
signal NPC_shadow : PCTYPE;
signal V_M_CTRL_TT3DOWNTO0_shadow : std_logic_vector(3 downto 0);
signal V_A_MULSTART_shadow : STD_ULOGIC;
signal XC_VECTT3DOWNTO0_shadow : STD_LOGIC_VECTOR(3 downto 0);
signal V_E_CTRL_TT_shadow : OP3_TYPE;
signal DSIGN_shadow : STD_ULOGIC;
signal V_E_CTRL_ANNUL_shadow : STD_ULOGIC;
signal EX_JUMP_ADDRESS_shadow : PCTYPE;
signal V_A_CTRL_PC31DOWNTO12_shadow : std_logic_vector(31 downto 12);
signal V_A_RFE1_shadow : STD_ULOGIC;
signal V_W_WA_shadow : RFATYPE;
signal V_X_ANNUL_ALL_shadow : STD_ULOGIC;
signal EX_YMSB_shadow : STD_ULOGIC;
signal EX_ADD_RES_shadow : STD_LOGIC_VECTOR(32 downto 0);
signal VIR_ADDR_shadow : PCTYPE;
signal EX_JUMP_ADDRESS31DOWNTO12_shadow : std_logic_vector(31 downto 12);
signal V_W_S_CWP_shadow : CWPTYPE;
signal V_D_INST0_shadow : std_logic_vector(31 downto 0);
signal V_A_CTRL_ANNUL_shadow : STD_ULOGIC;
signal V_X_DATA1_shadow : std_logic_vector(31 downto 0);
signal VP_PWD_shadow : STD_ULOGIC;
signal V_M_CTRL_RD6DOWNTO0_shadow : std_logic_vector(6 downto 0);
signal V_X_DATA00_shadow : STD_LOGIC;
signal V_M_CTRL_RETT_shadow : STD_ULOGIC;
signal V_X_CTRL_RETT_shadow : STD_ULOGIC;
signal V_X_CTRL_PC31DOWNTO12_shadow : std_logic_vector(31 downto 12);
signal V_W_S_PS_shadow : STD_ULOGIC;
signal V_X_CTRL_TT_shadow : OP3_TYPE;
signal V_D_STEP_shadow : STD_ULOGIC;
signal V_X_CTRL_WICC_shadow : STD_ULOGIC;
signal VIR_ADDR31DOWNTO2_shadow : std_logic_vector(31 downto 2);
signal V_M_CTRL_RD7DOWNTO0_shadow : std_logic_vector(7 downto 0);
signal V_X_RESULT_shadow : WORD;
signal V_D_CNT_shadow : OP_TYPE;
signal XC_VECTT_shadow : STD_LOGIC_VECTOR(7 downto 0);
signal EX_ADD_RES32DOWNTO3_shadow : STD_LOGIC_VECTOR(32 downto 3);
signal V_W_S_EF_shadow : STD_ULOGIC;
signal V_A_CTRL_PC31DOWNTO2_shadow : std_logic_vector(31 downto 2);
signal V_X_DATA04DOWNTO0_shadow : std_logic_vector(4 downto 0);
signal V_X_DCI_SIGNED_shadow : STD_ULOGIC;
signal V_M_NALIGN_shadow : STD_ULOGIC;
signal XC_WREG_shadow : STD_ULOGIC;
signal V_A_RFA2_shadow : RFATYPE;
signal V_E_CTRL_PC31DOWNTO12_shadow : std_logic_vector(31 downto 12);
signal EX_ADD_RES32DOWNTO332DOWNTO13_shadow : STD_LOGIC_VECTOR(32 downto 13);
signal EX_OP231_shadow : STD_LOGIC;
signal XC_TRAP_ADDRESS31DOWNTO4_shadow : std_logic_vector(31 downto 4);
signal V_X_ICC_shadow : STD_LOGIC_VECTOR(3 downto 0);
signal V_A_SU_shadow : STD_ULOGIC;
signal V_E_OP2_shadow : WORD;
signal EX_FORCE_A2_shadow : STD_ULOGIC;
signal V_E_CTRL_PC31DOWNTO2_shadow : std_logic_vector(31 downto 2);
signal V_E_CTRL_PC31DOWNTO4_shadow : std_logic_vector(31 downto 4);
signal V_E_OP131_shadow : STD_LOGIC;
signal V_X_DCI_shadow : DC_IN_TYPE;
signal V_E_CTRL_WICC_shadow : STD_ULOGIC;
signal EX_OP13_shadow : STD_LOGIC;
signal V_F_PC31DOWNTO12_shadow : std_logic_vector(31 downto 12);
signal V_E_CTRL_INST_shadow : WORD;
signal V_E_CTRL_LD_shadow : STD_ULOGIC;
signal V_M_SU_shadow : STD_ULOGIC;
signal V_E_SARI_shadow : STD_ULOGIC;
signal V_E_ET_shadow : STD_ULOGIC;
signal V_M_CTRL_PV_shadow : STD_ULOGIC;
signal VDSU_CRDY2_shadow : STD_LOGIC;
signal MUL_OP2_shadow : WORD;
signal XC_EXCEPTION_shadow : STD_ULOGIC;
signal V_E_OP1_shadow : WORD;
signal VP_ERROR_shadow : STD_ULOGIC;
signal V_M_DCI_SIGNED_shadow : STD_ULOGIC;
signal V_D_PC31DOWNTO12_shadow : std_logic_vector(31 downto 12);
signal MUL_OP231_shadow : STD_LOGIC;
signal XC_TRAP_ADDRESS31DOWNTO2_shadow : std_logic_vector(31 downto 2);
signal V_M_CTRL_PC3DOWNTO2_shadow : std_logic_vector(3 downto 2);
signal V_M_DCI_shadow : DC_IN_TYPE;
signal EX_OP23_shadow : STD_LOGIC;
signal V_X_CTRL_RD6DOWNTO0_shadow : std_logic_vector(6 downto 0);
signal V_X_CTRL_TRAP_shadow : STD_ULOGIC;
signal V_A_DIVSTART_shadow : STD_ULOGIC;
signal V_X_RESULT6DOWNTO03DOWNTO0_shadow : std_logic_vector(3 downto 0);
signal VDSU_TT_shadow : STD_LOGIC_VECTOR(7 downto 0);
signal EX_ADD_RES32DOWNTO332DOWNTO5_shadow : STD_LOGIC_VECTOR(32 downto 5);
signal V_X_CTRL_CNT_shadow : OP_TYPE;
signal V_E_YMSB_shadow : STD_ULOGIC;
signal EX_ADD_RES32DOWNTO330DOWNTO11_shadow : STD_LOGIC_VECTOR(30 downto 11);
signal V_A_RFE2_shadow : STD_ULOGIC;
signal V_E_OP13_shadow : STD_LOGIC;
signal V_A_CWP_shadow : CWPTYPE;
signal ME_SIZE_shadow : OP_TYPE;
signal V_X_MAC_shadow : STD_ULOGIC;
signal V_M_CTRL_INST_shadow : WORD;
signal VIR_ADDR31DOWNTO4_shadow : std_logic_vector(31 downto 4);
signal V_A_CTRL_INST20_shadow : STD_LOGIC;
signal DE_REN2_shadow : STD_ULOGIC;
signal V_E_CTRL_PV_shadow : STD_ULOGIC;
signal V_E_MAC_shadow : STD_ULOGIC;
signal V_X_CTRL_TT3DOWNTO0_shadow : std_logic_vector(3 downto 0);
signal EX_ADD_RES3_shadow : STD_LOGIC;
signal V_X_CTRL_INST_shadow : WORD;
signal V_M_CTRL_PC31DOWNTO2_shadow : std_logic_vector(31 downto 2);
signal V_W_S_ET_shadow : STD_ULOGIC;
signal V_M_CTRL_CNT_shadow : OP_TYPE;
signal V_M_CTRL_ANNUL_shadow : STD_ULOGIC;
signal DE_INST19_shadow : STD_LOGIC;
signal XC_HALT_shadow : STD_ULOGIC;
signal V_E_OP231_shadow : STD_LOGIC;
signal V_A_CTRL_PC3DOWNTO2_shadow : std_logic_vector(3 downto 2);
signal VIR_ADDR31DOWNTO12_shadow : std_logic_vector(31 downto 12);
signal V_M_CTRL_WICC_shadow : STD_ULOGIC;
signal V_M_CTRL_WREG_shadow : STD_ULOGIC;
signal V_W_S_S_shadow : STD_ULOGIC;
signal V_F_PC31DOWNTO2_shadow : std_logic_vector(31 downto 2);
signal V_E_CWP_shadow : CWPTYPE;
signal V_A_STEP_shadow : STD_ULOGIC;
signal V_A_CTRL_TT3DOWNTO0_shadow : std_logic_vector(3 downto 0);
signal V_A_CTRL_TRAP_shadow : STD_ULOGIC;
signal NPC31DOWNTO2_shadow : std_logic_vector(31 downto 2);
signal V_M_CTRL_TRAP_shadow : STD_ULOGIC;
signal V_D_PC31DOWNTO4_shadow : std_logic_vector(31 downto 4);
signal V_X_INTACK_shadow : STD_ULOGIC;
signal SIDLE_shadow : STD_ULOGIC;
signal V_A_CTRL_RETT_shadow : STD_ULOGIC;
signal V_X_DATA03_shadow : STD_LOGIC;
signal V_A_CTRL_INST19_shadow : STD_LOGIC;
signal V_W_S_SVT_shadow : STD_ULOGIC;
signal V_A_CTRL_PC31DOWNTO4_shadow : std_logic_vector(31 downto 4);
signal V_X_LADDR_shadow : OP_TYPE;
signal V_W_S_DWT_shadow : STD_ULOGIC;
signal EX_JUMP_ADDRESS31DOWNTO2_shadow : std_logic_vector(31 downto 2);
signal V_W_S_TBA_shadow : STD_LOGIC_VECTOR(19 downto 0);
signal XC_WADDR6DOWNTO0_shadow : STD_LOGIC_VECTOR(6 downto 0);
signal V_M_MUL_shadow : STD_ULOGIC;
signal V_E_SU_shadow : STD_ULOGIC;
signal V_M_Y31_shadow : STD_LOGIC;
signal V_E_OP23_shadow : STD_LOGIC;
signal V_M_CTRL_PC31DOWNTO4_shadow : std_logic_vector(31 downto 4);
signal DE_RADDR17DOWNTO0_shadow : STD_LOGIC_VECTOR(7 downto 0);
signal V_X_CTRL_PC31DOWNTO2_shadow : std_logic_vector(31 downto 2);
signal V_E_CTRL_TRAP_shadow : STD_ULOGIC;
signal V_X_DEBUG_shadow : STD_ULOGIC;
signal V_M_DCI_LOCK_shadow : STD_ULOGIC;
signal V_X_CTRL_PC3DOWNTO2_shadow : std_logic_vector(3 downto 2);
signal V_X_CTRL_WREG_shadow : STD_ULOGIC;
signal V_E_CTRL_INST24_shadow : STD_LOGIC;
signal V_D_MEXC_shadow : STD_ULOGIC;
signal V_W_RESULT_shadow : WORD;
signal VFPI_DBG_ENABLE_shadow : STD_ULOGIC;
signal EX_OP131_shadow : STD_LOGIC;
signal V_D_INST1_shadow : std_logic_vector(31 downto 0);
signal V_W_EXCEPT_shadow : STD_ULOGIC;
signal V_E_CTRL_TT3DOWNTO0_shadow : std_logic_vector(3 downto 0);
signal ME_LADDR_shadow : OP_TYPE;
signal V_X_CTRL_PC31DOWNTO4_shadow : std_logic_vector(31 downto 4);
signal V_E_CTRL_RETT_shadow : STD_ULOGIC;
signal XC_WADDR7DOWNTO0_shadow : STD_LOGIC_VECTOR(7 downto 0);
signal V_X_CTRL_PV_shadow : STD_ULOGIC;
signal V_E_CTRL_RD6DOWNTO0_shadow : std_logic_vector(6 downto 0);
signal V_M_MAC_shadow : STD_ULOGIC;
signal V_D_SET_shadow : STD_LOGIC_VECTOR(0 downto 0);
signal VIR_ADDR3DOWNTO2_shadow : std_logic_vector(3 downto 2);
signal V_D_CWP_shadow : CWPTYPE;
signal DE_INST20_shadow : STD_LOGIC;
signal V_D_ANNUL_shadow : STD_ULOGIC;
signal EX_OP2_shadow : WORD;
signal EX_SARI_shadow : STD_ULOGIC;
signal V_D_PC31DOWNTO2_shadow : std_logic_vector(31 downto 2);
signal V_X_DCI_SIZE_shadow : OP_TYPE;
signal V_M_Y_shadow : WORD;
signal V_X_CTRL_PC_shadow : PCTYPE;
signal V_X_SET_shadow : STD_LOGIC_VECTOR(0 downto 0);
signal V_A_CTRL_PC_shadow : PCTYPE;
signal V_A_JMPL_shadow : STD_ULOGIC;
signal V_E_CTRL_PC_shadow : PCTYPE;
signal V_E_CTRL_INST20_shadow : STD_LOGIC;
signal V_E_CTRL_WREG_shadow : STD_ULOGIC;
signal V_A_CTRL_WREG_shadow : STD_ULOGIC;
signal V_A_CTRL_shadow : PIPELINE_CTRL_TYPE;
signal V_A_CTRL_RD6DOWNTO0_shadow : std_logic_vector(6 downto 0);
signal V_X_DATA0_shadow : std_logic_vector(31 downto 0);
signal V_E_CTRL_INST19_shadow : STD_LOGIC;
signal ME_SIGNED_shadow : STD_ULOGIC;
signal V_W_WREG_shadow : STD_ULOGIC;
signal V_D_PC_shadow : PCTYPE;
signal VFPI_D_ANNUL_shadow : STD_ULOGIC;
signal DE_RADDR27DOWNTO0_shadow : STD_LOGIC_VECTOR(7 downto 0);
signal V_E_CTRL_CNT_shadow : OP_TYPE;
signal V_F_PC_shadow : PCTYPE;
signal V_X_DATA031_shadow : STD_LOGIC;
signal V_M_CTRL_PC31DOWNTO12_shadow : std_logic_vector(31 downto 12);
signal V_X_CTRL_RD7DOWNTO0_shadow : std_logic_vector(7 downto 0);
signal V_M_CTRL_TT_shadow : OP3_TYPE;
signal V_X_CTRL_shadow : PIPELINE_CTRL_TYPE;
signal V_A_CTRL_INST24_shadow : STD_LOGIC;
signal XC_TRAP_ADDRESS3DOWNTO2_shadow : std_logic_vector(3 downto 2);
signal V_X_NERROR_shadow : STD_ULOGIC;
signal V_F_PC31DOWNTO4_shadow : std_logic_vector(31 downto 4);
signal V_W_S_TT3DOWNTO0_shadow : STD_LOGIC_VECTOR(3 downto 0);
signal EX_JUMP_ADDRESS31DOWNTO4_shadow : std_logic_vector(31 downto 4);
signal EX_ADD_RES32DOWNTO332DOWNTO3_shadow : STD_LOGIC_VECTOR(32 downto 3);
signal V_F_BRANCH_shadow : STD_ULOGIC;
signal V_A_CTRL_WICC_shadow : STD_ULOGIC;
signal V_A_CTRL_LD_shadow : STD_ULOGIC;
signal V_A_CTRL_TT_shadow : OP3_TYPE;
signal V_M_CTRL_LD_shadow : STD_ULOGIC;
signal V_E_SHCNT_shadow : ASI_TYPE;
signal XC_TRAP_ADDRESS31DOWNTO12_shadow : std_logic_vector(31 downto 12);
signal V_A_CTRL_INST_shadow : WORD;
signal V_A_CTRL_RD7DOWNTO0_shadow : std_logic_vector(7 downto 0);
signal VIR_PWD_shadow : STD_ULOGIC;
signal XC_RESULT_shadow : WORD;
signal V_A_RFA1_shadow : RFATYPE;
signal V_E_JMPL_shadow : STD_ULOGIC;
signal V_E_CTRL_RD7DOWNTO0_shadow : std_logic_vector(7 downto 0);
signal ME_ICC_shadow : STD_LOGIC_VECTOR(3 downto 0);
signal DE_INST24_shadow : STD_LOGIC;
signal XC_TRAP_shadow : STD_ULOGIC;
signal VDSU_TBUFCNT_shadow : STD_LOGIC_VECTOR(6 downto 0);
signal XC_TRAP_ADDRESS_shadow : PCTYPE;
-- Intermediate value holding signal declarations
signal V_E_CTRL_WREG_shadow_intermed_2 : STD_ULOGIC;
signal V_M_CTRL_PC_shadow_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_E_CTRL_TT3DOWNTO0_intermed_1 : std_logic_vector(3 downto 0);
signal V_D_PC3DOWNTO2_shadow_intermed_6 : std_logic_vector(3 downto 2);
signal RIN_M_CTRL_PC31DOWNTO12_intermed_5 : std_logic_vector(31 downto 12);
signal RIN_A_RFA1_intermed_1 : std_logic_vector(7 downto 0);
signal RIN_A_CTRL_PC31DOWNTO2_intermed_4 : std_logic_vector(31 downto 2);
signal R_E_CTRL_TT_intermed_1 : std_logic_vector(5 downto 0);
signal V_D_PC3DOWNTO2_shadow_intermed_2 : std_logic_vector(3 downto 2);
signal ICO_MEXC_intermed_4 : STD_ULOGIC;
signal V_F_PC31DOWNTO2_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_X_DATA00_intermed_2 : STD_LOGIC;
signal R_A_CTRL_RD6DOWNTO0_intermed_1 : std_logic_vector(6 downto 0);
signal R_A_CTRL_INST24_intermed_1 : STD_LOGIC;
signal RIN_E_CTRL_INST19_intermed_1 : STD_LOGIC;
signal V_X_DATA00_shadow_intermed_3 : STD_LOGIC;
signal RIN_A_CTRL_INST19_intermed_2 : STD_LOGIC;
signal IRIN_ADDR31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2);
signal V_E_CTRL_WREG_shadow_intermed_1 : STD_ULOGIC;
signal V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 : std_logic_vector(31 downto 2);
signal V_M_CTRL_PC_shadow_intermed_3 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_WICC_intermed_3 : STD_ULOGIC;
signal V_A_CTRL_RETT_shadow_intermed_3 : STD_ULOGIC;
signal RPIN_PWD_intermed_1 : STD_ULOGIC;
signal RIN_A_CTRL_PC31DOWNTO12_intermed_7 : std_logic_vector(31 downto 12);
signal V_E_CTRL_TT_shadow_intermed_3 : std_logic_vector(5 downto 0);
signal DE_INST_shadow_intermed_2 : std_logic_vector(31 downto 0);
signal R_M_CTRL_PC31DOWNTO2_intermed_3 : std_logic_vector(31 downto 2);
signal DBGI_DADDR9DOWNTO2_intermed_1 : STD_LOGIC_VECTOR(9 downto 2);
signal R_D_PC31DOWNTO2_intermed_6 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_TT3DOWNTO0_intermed_5 : std_logic_vector(3 downto 0);
signal RIN_A_CTRL_TRAP_intermed_3 : STD_ULOGIC;
signal V_E_CTRL_CNT_shadow_intermed_2 : std_logic_vector(1 downto 0);
signal V_E_CTRL_PC31DOWNTO4_shadow_intermed_4 : std_logic_vector(31 downto 4);
signal RIN_D_STEP_intermed_1 : STD_ULOGIC;
signal V_M_CTRL_TT3DOWNTO0_shadow_intermed_4 : std_logic_vector(3 downto 0);
signal V_A_CTRL_PC_shadow_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_D_PC31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2);
signal V_E_CTRL_PC31DOWNTO4_shadow_intermed_5 : std_logic_vector(31 downto 4);
signal RIN_E_CTRL_INST20_intermed_1 : STD_LOGIC;
signal V_D_PC3DOWNTO2_shadow_intermed_7 : std_logic_vector(3 downto 2);
signal V_M_CTRL_PC31DOWNTO4_shadow_intermed_4 : std_logic_vector(31 downto 4);
signal V_M_CTRL_RD6DOWNTO0_shadow_intermed_2 : std_logic_vector(6 downto 0);
signal RIN_E_CTRL_PC3DOWNTO2_intermed_3 : std_logic_vector(3 downto 2);
signal RIN_M_Y31_intermed_1 : STD_LOGIC;
signal V_D_INST0_shadow_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_E_YMSB_intermed_1 : STD_ULOGIC;
signal R_X_DATA031_intermed_2 : STD_LOGIC;
signal RIN_M_CTRL_WREG_intermed_2 : STD_ULOGIC;
signal V_X_CTRL_TT_shadow_intermed_1 : std_logic_vector(5 downto 0);
signal RIN_E_CTRL_PC_intermed_4 : std_logic_vector(31 downto 2);
signal V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 : std_logic_vector(3 downto 0);
signal RIN_E_CTRL_PC31DOWNTO12_intermed_4 : std_logic_vector(31 downto 12);
signal V_A_CTRL_PC3DOWNTO2_shadow_intermed_3 : std_logic_vector(3 downto 2);
signal RIN_E_CTRL_PC31DOWNTO2_intermed_4 : std_logic_vector(31 downto 2);
signal R_A_CTRL_TT_intermed_1 : std_logic_vector(5 downto 0);
signal RIN_A_CTRL_WICC_intermed_2 : STD_ULOGIC;
signal V_E_CTRL_PC31DOWNTO2_shadow_intermed_6 : std_logic_vector(31 downto 2);
signal RIN_F_PC3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2);
signal V_A_CTRL_PC31DOWNTO12_shadow_intermed_4 : std_logic_vector(31 downto 12);
signal EX_ADD_RES32DOWNTO332DOWNTO5_shadow_intermed_1 : STD_LOGIC_VECTOR(32 downto 5);
signal V_X_DATA04DOWNTO0_shadow_intermed_1 : std_logic_vector(4 downto 0);
signal R_A_CTRL_INST20_intermed_2 : STD_LOGIC;
signal V_A_CTRL_PC31DOWNTO12_shadow_intermed_6 : std_logic_vector(31 downto 12);
signal R_A_CTRL_RETT_intermed_2 : STD_ULOGIC;
signal RIN_M_DCI_LOCK_intermed_1 : STD_ULOGIC;
signal RIN_D_PC31DOWNTO12_intermed_6 : std_logic_vector(31 downto 12);
signal RIN_E_CTRL_TT_intermed_3 : std_logic_vector(5 downto 0);
signal R_E_CTRL_RD7DOWNTO0_intermed_2 : std_logic_vector(7 downto 0);
signal RIN_A_ET_intermed_1 : STD_ULOGIC;
signal RIN_X_CTRL_RD6DOWNTO0_intermed_1 : std_logic_vector(6 downto 0);
signal RIN_M_CTRL_PC31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12);
signal DBGI_STEP_intermed_1 : STD_ULOGIC;
signal V_A_CTRL_RETT_shadow_intermed_2 : STD_ULOGIC;
signal R_X_CTRL_PC3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2);
signal R_A_CTRL_PC31DOWNTO4_intermed_4 : std_logic_vector(31 downto 4);
signal V_M_CTRL_PV_shadow_intermed_1 : STD_ULOGIC;
signal RIN_M_CTRL_PC31DOWNTO2_intermed_5 : std_logic_vector(31 downto 2);
signal V_M_CTRL_PC31DOWNTO12_shadow_intermed_5 : std_logic_vector(31 downto 12);
signal V_X_LADDR_shadow_intermed_1 : std_logic_vector(1 downto 0);
signal V_D_ANNUL_shadow_intermed_2 : STD_ULOGIC;
signal V_A_CTRL_RD6DOWNTO0_shadow_intermed_1 : std_logic_vector(6 downto 0);
signal RIN_W_WA_intermed_1 : std_logic_vector(7 downto 0);
signal V_D_PC_shadow_intermed_4 : std_logic_vector(31 downto 2);
signal V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_X_CTRL_PC31DOWNTO4_intermed_2 : std_logic_vector(31 downto 4);
signal V_E_CTRL_WICC_shadow_intermed_1 : STD_ULOGIC;
signal VDSU_CRDY2_shadow_intermed_2 : STD_LOGIC;
signal V_M_RESULT1DOWNTO0_shadow_intermed_3 : std_logic_vector(1 downto 0);
signal RIN_D_INST0_intermed_1 : std_logic_vector(31 downto 0);
signal V_X_DATA03_shadow_intermed_2 : STD_LOGIC;
signal RIN_X_DCI_intermed_1 : DC_IN_TYPE;
signal DSUIN_TT_intermed_1 : STD_LOGIC_VECTOR(7 downto 0);
signal V_D_CNT_shadow_intermed_4 : std_logic_vector(1 downto 0);
signal RIN_D_CNT_intermed_4 : std_logic_vector(1 downto 0);
signal ICO_MEXC_intermed_1 : STD_ULOGIC;
signal R_X_ANNUL_ALL_intermed_2 : STD_ULOGIC;
signal R_X_CTRL_TT3DOWNTO0_intermed_2 : std_logic_vector(3 downto 0);
signal R_D_PC3DOWNTO2_intermed_3 : std_logic_vector(3 downto 2);
signal RIN_D_CNT_intermed_2 : std_logic_vector(1 downto 0);
signal V_M_DCI_SIZE_shadow_intermed_2 : std_logic_vector(1 downto 0);
signal R_A_CTRL_ANNUL_intermed_2 : STD_ULOGIC;
signal V_W_S_S_shadow_intermed_1 : STD_ULOGIC;
signal RIN_M_CTRL_TT_intermed_2 : std_logic_vector(5 downto 0);
signal EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_1 : STD_LOGIC_VECTOR(30 downto 11);
signal V_A_CTRL_RETT_shadow_intermed_1 : STD_ULOGIC;
signal R_X_DATA04DOWNTO0_intermed_1 : std_logic_vector(4 downto 0);
signal V_E_CTRL_TT3DOWNTO0_shadow_intermed_1 : std_logic_vector(3 downto 0);
signal V_D_PC31DOWNTO4_shadow_intermed_6 : std_logic_vector(31 downto 4);
signal V_X_CTRL_RD6DOWNTO0_shadow_intermed_1 : std_logic_vector(6 downto 0);
signal RIN_W_S_ET_intermed_1 : STD_ULOGIC;
signal R_E_CTRL_TRAP_intermed_1 : STD_ULOGIC;
signal V_A_CTRL_PC_shadow_intermed_3 : std_logic_vector(31 downto 2);
signal R_M_CTRL_PC31DOWNTO4_intermed_2 : std_logic_vector(31 downto 4);
signal VIR_ADDR31DOWNTO4_shadow_intermed_2 : std_logic_vector(31 downto 4);
signal V_E_CTRL_RD6DOWNTO0_shadow_intermed_3 : std_logic_vector(6 downto 0);
signal R_D_CWP_intermed_1 : std_logic_vector(2 downto 0);
signal RIN_A_CTRL_TT3DOWNTO0_intermed_2 : std_logic_vector(3 downto 0);
signal RIN_X_CTRL_PC3DOWNTO2_intermed_3 : std_logic_vector(3 downto 2);
signal RIN_D_PC31DOWNTO2_intermed_8 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_ANNUL_intermed_1 : STD_ULOGIC;
signal V_X_CTRL_PC3DOWNTO2_shadow_intermed_1 : std_logic_vector(3 downto 2);
signal RIN_M_CTRL_PC31DOWNTO12_intermed_3 : std_logic_vector(31 downto 12);
signal R_M_DCI_SIGNED_intermed_1 : STD_ULOGIC;
signal RIN_X_DCI_SIGNED_intermed_1 : STD_ULOGIC;
signal V_D_PC31DOWNTO2_shadow_intermed_4 : std_logic_vector(31 downto 2);
signal DCO_DATA00_intermed_2 : STD_LOGIC;
signal V_M_CTRL_RD7DOWNTO0_shadow_intermed_2 : std_logic_vector(7 downto 0);
signal V_E_SU_shadow_intermed_1 : STD_ULOGIC;
signal R_A_CTRL_INST20_intermed_1 : STD_LOGIC;
signal R_D_PC31DOWNTO12_intermed_7 : std_logic_vector(31 downto 12);
signal XC_TRAP_ADDRESS_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_X_CTRL_PC31DOWNTO2_intermed_3 : std_logic_vector(31 downto 2);
signal R_E_CTRL_RETT_intermed_1 : STD_ULOGIC;
signal V_X_DCI_SIZE_shadow_intermed_1 : std_logic_vector(1 downto 0);
signal RIN_D_CNT_intermed_3 : std_logic_vector(1 downto 0);
signal RIN_A_CTRL_ANNUL_intermed_4 : STD_ULOGIC;
signal R_E_CTRL_TT3DOWNTO0_intermed_1 : std_logic_vector(3 downto 0);
signal R_D_PC3DOWNTO2_intermed_2 : std_logic_vector(3 downto 2);
signal V_X_CTRL_TT3DOWNTO0_shadow_intermed_3 : std_logic_vector(3 downto 0);
signal V_A_CTRL_RD6DOWNTO0_shadow_intermed_3 : std_logic_vector(6 downto 0);
signal R_M_CTRL_PC31DOWNTO2_intermed_4 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_PC31DOWNTO12_intermed_3 : std_logic_vector(31 downto 12);
signal R_A_CTRL_PC31DOWNTO12_intermed_5 : std_logic_vector(31 downto 12);
signal R_A_CTRL_PC_intermed_2 : std_logic_vector(31 downto 2);
signal V_X_MEXC_shadow_intermed_1 : STD_ULOGIC;
signal V_M_CTRL_RD7DOWNTO0_shadow_intermed_1 : std_logic_vector(7 downto 0);
signal IR_ADDR31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4);
signal V_A_CTRL_PC_shadow_intermed_4 : std_logic_vector(31 downto 2);
signal VIR_ADDR31DOWNTO4_shadow_intermed_1 : std_logic_vector(31 downto 4);
signal RIN_M_CTRL_PC3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2);
signal RIN_E_CTRL_WREG_intermed_1 : STD_ULOGIC;
signal RIN_D_PC31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12);
signal V_E_CTRL_TT3DOWNTO0_shadow_intermed_2 : std_logic_vector(3 downto 0);
signal RIN_D_INST1_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_D_PC31DOWNTO12_intermed_3 : std_logic_vector(31 downto 12);
signal V_A_CTRL_TT_shadow_intermed_3 : std_logic_vector(5 downto 0);
signal RIN_A_CTRL_INST24_intermed_2 : STD_LOGIC;
signal V_X_DATA1_shadow_intermed_2 : std_logic_vector(31 downto 0);
signal ICO_MEXC_intermed_3 : STD_ULOGIC;
signal R_D_PC3DOWNTO2_intermed_4 : std_logic_vector(3 downto 2);
signal R_M_CTRL_INST_intermed_1 : std_logic_vector(31 downto 0);
signal V_A_CWP_shadow_intermed_1 : std_logic_vector(2 downto 0);
signal V_A_CTRL_WICC_shadow_intermed_3 : STD_ULOGIC;
signal V_D_PC_shadow_intermed_6 : std_logic_vector(31 downto 2);
signal RIN_X_ANNUL_ALL_intermed_5 : STD_ULOGIC;
signal RIN_E_CTRL_INST20_intermed_2 : STD_LOGIC;
signal R_X_DATA0_intermed_2 : std_logic_vector(31 downto 0);
signal RIN_D_PC_intermed_4 : std_logic_vector(31 downto 2);
signal R_E_CTRL_PV_intermed_1 : STD_ULOGIC;
signal R_E_CTRL_TT3DOWNTO0_intermed_2 : std_logic_vector(3 downto 0);
signal R_D_PC_intermed_1 : std_logic_vector(31 downto 2);
signal R_A_CTRL_PC_intermed_3 : std_logic_vector(31 downto 2);
signal EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_1 : std_logic_vector(31 downto 12);
signal R_X_CTRL_TT3DOWNTO0_intermed_1 : std_logic_vector(3 downto 0);
signal V_M_DCI_SIGNED_shadow_intermed_1 : STD_ULOGIC;
signal RIN_X_CTRL_TT3DOWNTO0_intermed_1 : std_logic_vector(3 downto 0);
signal V_X_ANNUL_ALL_shadow_intermed_2 : STD_ULOGIC;
signal V_D_PC31DOWNTO4_shadow_intermed_7 : std_logic_vector(31 downto 4);
signal RIN_E_OP13_intermed_1 : STD_LOGIC;
signal RIN_A_CWP_intermed_1 : std_logic_vector(2 downto 0);
signal RIN_E_CTRL_WICC_intermed_1 : STD_ULOGIC;
signal VP_ERROR_shadow_intermed_2 : STD_ULOGIC;
signal RIN_E_OP2_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_A_CTRL_TT3DOWNTO0_intermed_4 : std_logic_vector(3 downto 0);
signal RIN_A_CTRL_RD7DOWNTO0_intermed_2 : std_logic_vector(7 downto 0);
signal RIN_E_CTRL_intermed_2 : PIPELINE_CTRL_TYPE;
signal R_M_CTRL_PC_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_E_CTRL_PC31DOWNTO2_intermed_5 : std_logic_vector(31 downto 2);
signal R_M_Y31_intermed_2 : STD_LOGIC;
signal V_M_CTRL_PC3DOWNTO2_shadow_intermed_4 : std_logic_vector(3 downto 2);
signal V_M_CTRL_RETT_shadow_intermed_1 : STD_ULOGIC;
signal V_X_CTRL_PC31DOWNTO4_shadow_intermed_3 : std_logic_vector(31 downto 4);
signal XC_VECTT3DOWNTO0_shadow_intermed_2 : STD_LOGIC_VECTOR(3 downto 0);
signal RIN_M_CTRL_PC31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12);
signal RIN_M_RESULT1DOWNTO0_intermed_2 : std_logic_vector(1 downto 0);
signal V_X_ANNUL_ALL_shadow_intermed_4 : STD_ULOGIC;
signal RIN_W_S_TBA_intermed_1 : STD_LOGIC_VECTOR(19 downto 0);
signal V_D_INST1_shadow_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_X_DATA031_intermed_1 : STD_LOGIC;
signal XC_TRAP_ADDRESS31DOWNTO12_shadow_intermed_1 : std_logic_vector(31 downto 12);
signal RIN_D_PC3DOWNTO2_intermed_4 : std_logic_vector(3 downto 2);
signal RIN_X_CTRL_PC31DOWNTO4_intermed_3 : std_logic_vector(31 downto 4);
signal V_E_CTRL_PC31DOWNTO4_shadow_intermed_2 : std_logic_vector(31 downto 4);
signal V_M_CTRL_PC3DOWNTO2_shadow_intermed_3 : std_logic_vector(3 downto 2);
signal V_M_CTRL_PC31DOWNTO12_shadow_intermed_2 : std_logic_vector(31 downto 12);
signal RIN_E_CTRL_PV_intermed_1 : STD_ULOGIC;
signal EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_1 : STD_LOGIC_VECTOR(32 downto 13);
signal R_E_CTRL_WREG_intermed_2 : STD_ULOGIC;
signal R_X_DATA031_intermed_1 : STD_LOGIC;
signal R_D_INST0_intermed_2 : std_logic_vector(31 downto 0);
signal RIN_E_SARI_intermed_1 : STD_ULOGIC;
signal R_M_Y31_intermed_1 : STD_LOGIC;
signal IR_ADDR3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2);
signal DE_INST24_shadow_intermed_2 : STD_LOGIC;
signal V_W_S_S_shadow_intermed_2 : STD_ULOGIC;
signal DE_INST20_shadow_intermed_3 : STD_LOGIC;
signal R_E_CTRL_TT3DOWNTO0_intermed_4 : std_logic_vector(3 downto 0);
signal RIN_A_CTRL_TT_intermed_2 : std_logic_vector(5 downto 0);
signal V_A_CTRL_PV_shadow_intermed_2 : STD_ULOGIC;
signal V_E_CTRL_TT_shadow_intermed_1 : std_logic_vector(5 downto 0);
signal V_D_PC31DOWNTO2_shadow_intermed_5 : std_logic_vector(31 downto 2);
signal V_X_DATA04DOWNTO0_shadow_intermed_2 : std_logic_vector(4 downto 0);
signal R_X_CTRL_PC31DOWNTO4_intermed_2 : std_logic_vector(31 downto 4);
signal RIN_M_CTRL_INST_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_A_CTRL_RD6DOWNTO0_intermed_2 : std_logic_vector(6 downto 0);
signal DCO_DATA04DOWNTO0_intermed_2 : std_logic_vector(4 downto 0);
signal EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_2 : std_logic_vector(31 downto 12);
signal V_X_DATA0_shadow_intermed_2 : std_logic_vector(31 downto 0);
signal R_A_CTRL_WREG_intermed_3 : STD_ULOGIC;
signal RIN_X_CTRL_PC31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12);
signal R_D_CNT_intermed_3 : std_logic_vector(1 downto 0);
signal V_E_OP131_shadow_intermed_1 : STD_LOGIC;
signal R_D_PC31DOWNTO12_intermed_6 : std_logic_vector(31 downto 12);
signal RIN_X_CTRL_WICC_intermed_1 : STD_ULOGIC;
signal V_D_PC31DOWNTO12_shadow_intermed_1 : std_logic_vector(31 downto 12);
signal RIN_E_CTRL_TRAP_intermed_3 : STD_ULOGIC;
signal R_X_RESULT6DOWNTO0_intermed_1 : std_logic_vector(6 downto 0);
signal R_E_CTRL_INST19_intermed_2 : STD_LOGIC;
signal RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 : std_logic_vector(3 downto 0);
signal R_M_CTRL_RD7DOWNTO0_intermed_1 : std_logic_vector(7 downto 0);
signal RIN_E_CTRL_PC31DOWNTO12_intermed_6 : std_logic_vector(31 downto 12);
signal RIN_A_CTRL_PC31DOWNTO4_intermed_3 : std_logic_vector(31 downto 4);
signal V_A_CTRL_INST19_shadow_intermed_3 : STD_LOGIC;
signal V_D_PC31DOWNTO12_shadow_intermed_5 : std_logic_vector(31 downto 12);
signal V_A_CTRL_INST19_shadow_intermed_2 : STD_LOGIC;
signal V_X_CTRL_WREG_shadow_intermed_1 : STD_ULOGIC;
signal V_A_CTRL_TRAP_shadow_intermed_2 : STD_ULOGIC;
signal RIN_E_CTRL_PC3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2);
signal RIN_M_CTRL_PC3DOWNTO2_intermed_3 : std_logic_vector(3 downto 2);
signal V_A_RFE2_shadow_intermed_1 : STD_ULOGIC;
signal V_M_Y_shadow_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_A_CTRL_LD_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_PC_shadow_intermed_3 : std_logic_vector(31 downto 2);
signal RIN_D_INST1_intermed_2 : std_logic_vector(31 downto 0);
signal R_E_CTRL_PC31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12);
signal RIN_X_CTRL_PC31DOWNTO12_intermed_3 : std_logic_vector(31 downto 12);
signal R_E_CTRL_TRAP_intermed_2 : STD_ULOGIC;
signal DE_INST24_shadow_intermed_1 : STD_LOGIC;
signal V_E_CTRL_PC_shadow_intermed_2 : std_logic_vector(31 downto 2);
signal V_A_CTRL_TT_shadow_intermed_1 : std_logic_vector(5 downto 0);
signal V_D_MEXC_shadow_intermed_4 : STD_ULOGIC;
signal V_D_PC31DOWNTO12_shadow_intermed_6 : std_logic_vector(31 downto 12);
signal V_A_CTRL_PC31DOWNTO12_shadow_intermed_3 : std_logic_vector(31 downto 12);
signal R_X_CTRL_PC31DOWNTO12_intermed_3 : std_logic_vector(31 downto 12);
signal V_M_CTRL_PV_shadow_intermed_2 : STD_ULOGIC;
signal RIN_A_CTRL_PC31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2);
signal EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_E_CTRL_PC31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4);
signal RIN_E_CTRL_PC31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12);
signal RIN_M_CTRL_TRAP_intermed_1 : STD_ULOGIC;
signal R_E_CTRL_PC31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2);
signal R_E_CTRL_LD_intermed_1 : STD_ULOGIC;
signal R_M_CTRL_PC31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_PC31DOWNTO2_intermed_5 : std_logic_vector(31 downto 2);
signal V_W_S_CWP_shadow_intermed_1 : std_logic_vector(2 downto 0);
signal R_M_CTRL_PC3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2);
signal V_E_CTRL_PC31DOWNTO12_shadow_intermed_4 : std_logic_vector(31 downto 12);
signal R_X_CTRL_PC31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4);
signal V_M_CTRL_PC_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal IR_ADDR31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2);
signal V_E_CTRL_TT3DOWNTO0_shadow_intermed_4 : std_logic_vector(3 downto 0);
signal V_E_CTRL_PC3DOWNTO2_shadow_intermed_3 : std_logic_vector(3 downto 2);
signal RIN_X_CTRL_PC31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4);
signal R_E_CTRL_PC31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12);
signal RIN_M_CTRL_RETT_intermed_1 : STD_ULOGIC;
signal V_M_DCI_LOCK_shadow_intermed_1 : STD_ULOGIC;
signal V_X_RESULT6DOWNTO0_shadow_intermed_1 : std_logic_vector(6 downto 0);
signal RIN_X_DATA04DOWNTO0_intermed_3 : std_logic_vector(4 downto 0);
signal V_X_NERROR_shadow_intermed_1 : STD_ULOGIC;
signal V_A_RFE1_shadow_intermed_1 : STD_ULOGIC;
signal V_D_PC3DOWNTO2_shadow_intermed_1 : std_logic_vector(3 downto 2);
signal V_E_CTRL_LD_shadow_intermed_1 : STD_ULOGIC;
signal ICO_DATA0_intermed_1 : std_logic_vector(31 downto 0);
signal VIR_ADDR_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal R_M_CTRL_PC31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12);
signal V_E_CTRL_PV_shadow_intermed_2 : STD_ULOGIC;
signal RIN_E_CTRL_PC31DOWNTO4_intermed_4 : std_logic_vector(31 downto 4);
signal R_A_CTRL_PC3DOWNTO2_intermed_3 : std_logic_vector(3 downto 2);
signal R_E_CTRL_INST19_intermed_1 : STD_LOGIC;
signal RIN_E_CTRL_TT3DOWNTO0_intermed_4 : std_logic_vector(3 downto 0);
signal R_M_CTRL_PC31DOWNTO4_intermed_3 : std_logic_vector(31 downto 4);
signal V_A_CTRL_PC31DOWNTO4_shadow_intermed_4 : std_logic_vector(31 downto 4);
signal RIN_W_S_DWT_intermed_1 : STD_ULOGIC;
signal V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 : std_logic_vector(31 downto 2);
signal R_D_PC31DOWNTO12_intermed_4 : std_logic_vector(31 downto 12);
signal RIN_X_NERROR_intermed_1 : STD_ULOGIC;
signal R_M_CTRL_PC3DOWNTO2_intermed_2 : std_logic_vector(3 downto 2);
signal ICO_MEXC_intermed_5 : STD_ULOGIC;
signal R_A_CTRL_RD7DOWNTO0_intermed_2 : std_logic_vector(7 downto 0);
signal V_A_CTRL_PC31DOWNTO4_shadow_intermed_1 : std_logic_vector(31 downto 4);
signal IRIN_ADDR31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2);
signal VIR_ADDR31DOWNTO12_shadow_intermed_3 : std_logic_vector(31 downto 12);
signal XC_TRAP_ADDRESS3DOWNTO2_shadow_intermed_1 : std_logic_vector(3 downto 2);
signal R_A_CTRL_INST_intermed_1 : std_logic_vector(31 downto 0);
signal R_E_CTRL_PC31DOWNTO2_intermed_3 : std_logic_vector(31 downto 2);
signal RIN_X_CTRL_TT3DOWNTO0_intermed_3 : std_logic_vector(3 downto 0);
signal RIN_M_CTRL_PC3DOWNTO2_intermed_2 : std_logic_vector(3 downto 2);
signal V_M_CTRL_PC31DOWNTO2_shadow_intermed_4 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_RETT_intermed_2 : STD_ULOGIC;
signal V_X_DATA00_shadow_intermed_1 : STD_LOGIC;
signal RIN_M_CTRL_RD6DOWNTO0_intermed_2 : std_logic_vector(6 downto 0);
signal RIN_E_CTRL_TT3DOWNTO0_intermed_2 : std_logic_vector(3 downto 0);
signal V_M_CTRL_INST_shadow_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_A_CTRL_TT3DOWNTO0_intermed_3 : std_logic_vector(3 downto 0);
signal EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1 : STD_LOGIC_VECTOR(32 downto 3);
signal R_A_CTRL_TT3DOWNTO0_intermed_1 : std_logic_vector(3 downto 0);
signal V_X_DEBUG_shadow_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_PC_shadow_intermed_4 : std_logic_vector(31 downto 2);
signal V_M_CTRL_TT_shadow_intermed_1 : std_logic_vector(5 downto 0);
signal RIN_A_CTRL_PV_intermed_4 : STD_ULOGIC;
signal R_E_MAC_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_PC3DOWNTO2_shadow_intermed_1 : std_logic_vector(3 downto 2);
signal R_M_RESULT1DOWNTO0_intermed_1 : std_logic_vector(1 downto 0);
signal IR_ADDR31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_WREG_intermed_2 : STD_ULOGIC;
signal V_D_MEXC_shadow_intermed_1 : STD_ULOGIC;
signal XC_TRAP_ADDRESS31DOWNTO12_shadow_intermed_2 : std_logic_vector(31 downto 12);
signal R_A_CTRL_LD_intermed_2 : STD_ULOGIC;
signal R_A_CTRL_intermed_2 : PIPELINE_CTRL_TYPE;
signal V_M_CTRL_TRAP_shadow_intermed_2 : STD_ULOGIC;
signal V_A_JMPL_shadow_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_RETT_shadow_intermed_2 : STD_ULOGIC;
signal RIN_M_CTRL_LD_intermed_1 : STD_ULOGIC;
signal V_X_DATA04DOWNTO0_shadow_intermed_3 : std_logic_vector(4 downto 0);
signal RIN_W_S_TT_intermed_1 : STD_LOGIC_VECTOR(7 downto 0);
signal V_A_CTRL_PC_shadow_intermed_5 : std_logic_vector(31 downto 2);
signal V_X_CTRL_PC31DOWNTO12_shadow_intermed_1 : std_logic_vector(31 downto 12);
signal DCO_DATA031_intermed_1 : STD_LOGIC;
signal RIN_A_CTRL_CNT_intermed_1 : std_logic_vector(1 downto 0);
signal R_X_ANNUL_ALL_intermed_3 : STD_ULOGIC;
signal V_X_DATA031_shadow_intermed_3 : STD_LOGIC;
signal DCO_DATA1_intermed_1 : std_logic_vector(31 downto 0);
signal V_E_CTRL_RETT_shadow_intermed_1 : STD_ULOGIC;
signal RIN_E_CTRL_CNT_intermed_1 : std_logic_vector(1 downto 0);
signal V_X_DATA0_shadow_intermed_1 : std_logic_vector(31 downto 0);
signal V_A_CTRL_LD_shadow_intermed_2 : STD_ULOGIC;
signal V_A_CTRL_TT3DOWNTO0_shadow_intermed_6 : std_logic_vector(3 downto 0);
signal R_E_CTRL_PC31DOWNTO4_intermed_3 : std_logic_vector(31 downto 4);
signal RPIN_ERROR_intermed_1 : STD_ULOGIC;
signal V_X_CTRL_PC31DOWNTO2_shadow_intermed_3 : std_logic_vector(31 downto 2);
signal R_W_S_S_intermed_1 : STD_ULOGIC;
signal R_A_CTRL_WICC_intermed_1 : STD_ULOGIC;
signal RIN_A_CTRL_PC31DOWNTO4_intermed_5 : std_logic_vector(31 downto 4);
signal RIN_D_PC31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4);
signal EX_JUMP_ADDRESS31DOWNTO4_shadow_intermed_1 : std_logic_vector(31 downto 4);
signal RIN_D_PC_intermed_5 : std_logic_vector(31 downto 2);
signal V_A_RFA1_shadow_intermed_1 : std_logic_vector(7 downto 0);
signal R_X_CTRL_PC31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2);
signal R_D_PC_intermed_2 : std_logic_vector(31 downto 2);
signal V_A_CTRL_PC3DOWNTO2_shadow_intermed_5 : std_logic_vector(3 downto 2);
signal RIN_E_SU_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_INST_shadow_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_M_CTRL_PC_intermed_1 : std_logic_vector(31 downto 2);
signal R_X_ANNUL_ALL_intermed_4 : STD_ULOGIC;
signal RIN_A_CTRL_INST_intermed_3 : std_logic_vector(31 downto 0);
signal V_A_CTRL_shadow_intermed_3 : PIPELINE_CTRL_TYPE;
signal R_D_MEXC_intermed_1 : STD_ULOGIC;
signal RIN_X_CTRL_RETT_intermed_1 : STD_ULOGIC;
signal R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 : std_logic_vector(3 downto 0);
signal R_A_CTRL_WICC_intermed_2 : STD_ULOGIC;
signal VDSU_CRDY2_shadow_intermed_1 : STD_LOGIC;
signal V_A_DIVSTART_shadow_intermed_1 : STD_ULOGIC;
signal R_A_CTRL_PC31DOWNTO2_intermed_6 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_TRAP_intermed_4 : STD_ULOGIC;
signal RIN_W_S_PS_intermed_1 : STD_ULOGIC;
signal R_D_MEXC_intermed_3 : STD_ULOGIC;
signal RIN_A_RFA2_intermed_1 : std_logic_vector(7 downto 0);
signal R_X_DATA1_intermed_1 : std_logic_vector(31 downto 0);
signal V_A_CTRL_PV_shadow_intermed_1 : STD_ULOGIC;
signal R_A_CTRL_PC31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4);
signal V_X_CTRL_PC31DOWNTO4_shadow_intermed_2 : std_logic_vector(31 downto 4);
signal RIN_W_S_SVT_intermed_1 : STD_ULOGIC;
signal RIN_E_CTRL_RD6DOWNTO0_intermed_1 : std_logic_vector(6 downto 0);
signal R_D_PC31DOWNTO12_intermed_5 : std_logic_vector(31 downto 12);
signal RIN_A_CTRL_INST19_intermed_1 : STD_LOGIC;
signal RIN_M_CTRL_PV_intermed_1 : STD_ULOGIC;
signal RIN_A_CTRL_RD6DOWNTO0_intermed_4 : std_logic_vector(6 downto 0);
signal RIN_E_OP23_intermed_1 : STD_LOGIC;
signal RIN_E_CTRL_WICC_intermed_2 : STD_ULOGIC;
signal R_D_PC31DOWNTO4_intermed_5 : std_logic_vector(31 downto 4);
signal V_D_MEXC_shadow_intermed_2 : STD_ULOGIC;
signal RIN_D_PC31DOWNTO4_intermed_7 : std_logic_vector(31 downto 4);
signal R_A_CTRL_TRAP_intermed_3 : STD_ULOGIC;
signal V_E_CTRL_INST19_shadow_intermed_2 : STD_LOGIC;
signal RIN_E_CTRL_PC31DOWNTO12_intermed_5 : std_logic_vector(31 downto 12);
signal RIN_D_PC31DOWNTO12_intermed_8 : std_logic_vector(31 downto 12);
signal VP_PWD_shadow_intermed_1 : STD_ULOGIC;
signal RIN_M_CTRL_RD7DOWNTO0_intermed_1 : std_logic_vector(7 downto 0);
signal V_A_CTRL_PC31DOWNTO4_shadow_intermed_2 : std_logic_vector(31 downto 4);
signal RIN_F_PC31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_M_NALIGN_intermed_1 : STD_ULOGIC;
signal RP_ERROR_intermed_1 : STD_ULOGIC;
signal RIN_X_CTRL_PC3DOWNTO2_intermed_2 : std_logic_vector(3 downto 2);
signal V_W_S_TBA_shadow_intermed_1 : STD_LOGIC_VECTOR(19 downto 0);
signal R_F_PC31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12);
signal RIN_E_JMPL_intermed_1 : STD_ULOGIC;
signal RIN_A_CTRL_TRAP_intermed_1 : STD_ULOGIC;
signal V_A_SU_shadow_intermed_1 : STD_ULOGIC;
signal RIN_A_RFE2_intermed_1 : STD_ULOGIC;
signal RIN_D_PC_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_CNT_intermed_3 : std_logic_vector(1 downto 0);
signal V_M_CTRL_PC31DOWNTO12_shadow_intermed_3 : std_logic_vector(31 downto 12);
signal V_M_CTRL_PC3DOWNTO2_shadow_intermed_2 : std_logic_vector(3 downto 2);
signal VIR_ADDR31DOWNTO12_shadow_intermed_1 : std_logic_vector(31 downto 12);
signal RIN_E_CTRL_LD_intermed_2 : STD_ULOGIC;
signal V_E_CTRL_PC31DOWNTO12_shadow_intermed_2 : std_logic_vector(31 downto 12);
signal R_E_CTRL_PC31DOWNTO12_intermed_4 : std_logic_vector(31 downto 12);
signal V_X_CTRL_PC3DOWNTO2_shadow_intermed_2 : std_logic_vector(3 downto 2);
signal V_A_CTRL_INST24_shadow_intermed_2 : STD_LOGIC;
signal V_M_CTRL_TRAP_shadow_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_PC31DOWNTO4_shadow_intermed_3 : std_logic_vector(31 downto 4);
signal V_A_CTRL_PC3DOWNTO2_shadow_intermed_4 : std_logic_vector(3 downto 2);
signal R_A_CTRL_PC31DOWNTO2_intermed_5 : std_logic_vector(31 downto 2);
signal R_X_DATA0_intermed_1 : std_logic_vector(31 downto 0);
signal V_E_CTRL_TT_shadow_intermed_2 : std_logic_vector(5 downto 0);
signal V_E_MAC_shadow_intermed_2 : STD_ULOGIC;
signal RIN_E_CTRL_INST19_intermed_2 : STD_LOGIC;
signal RIN_D_PC31DOWNTO2_intermed_3 : std_logic_vector(31 downto 2);
signal IRIN_ADDR_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_X_ANNUL_ALL_intermed_3 : STD_ULOGIC;
signal RIN_E_CTRL_INST_intermed_2 : std_logic_vector(31 downto 0);
signal V_X_CTRL_PC_shadow_intermed_2 : std_logic_vector(31 downto 2);
signal R_M_CTRL_TRAP_intermed_1 : STD_ULOGIC;
signal V_D_CWP_shadow_intermed_2 : std_logic_vector(2 downto 0);
signal V_A_CTRL_PC31DOWNTO12_shadow_intermed_2 : std_logic_vector(31 downto 12);
signal V_A_CTRL_LD_shadow_intermed_1 : STD_ULOGIC;
signal R_A_CTRL_INST19_intermed_2 : STD_LOGIC;
signal RIN_X_MEXC_intermed_1 : STD_ULOGIC;
signal RIN_D_MEXC_intermed_4 : STD_ULOGIC;
signal RIN_A_MULSTART_intermed_1 : STD_ULOGIC;
signal RIN_A_CTRL_TT_intermed_1 : std_logic_vector(5 downto 0);
signal RIN_M_CTRL_TT3DOWNTO0_intermed_2 : std_logic_vector(3 downto 0);
signal R_D_INST1_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_A_CTRL_intermed_1 : PIPELINE_CTRL_TYPE;
signal R_E_CTRL_WICC_intermed_1 : STD_ULOGIC;
signal RIN_M_CTRL_TT3DOWNTO0_intermed_3 : std_logic_vector(3 downto 0);
signal V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 : std_logic_vector(31 downto 2);
signal V_A_CTRL_TT3DOWNTO0_shadow_intermed_1 : std_logic_vector(3 downto 0);
signal RIN_M_DCI_SIGNED_intermed_2 : STD_ULOGIC;
signal V_E_CTRL_TT3DOWNTO0_shadow_intermed_3 : std_logic_vector(3 downto 0);
signal IRIN_ADDR31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4);
signal RIN_X_SET_intermed_1 : STD_LOGIC_VECTOR(0 downto 0);
signal V_M_CTRL_WREG_shadow_intermed_2 : STD_ULOGIC;
signal RIN_X_CTRL_PC31DOWNTO12_intermed_4 : std_logic_vector(31 downto 12);
signal V_D_PC_shadow_intermed_5 : std_logic_vector(31 downto 2);
signal RIN_X_CTRL_TT3DOWNTO0_intermed_2 : std_logic_vector(3 downto 0);
signal R_D_INST0_intermed_1 : std_logic_vector(31 downto 0);
signal R_E_CTRL_PC31DOWNTO4_intermed_4 : std_logic_vector(31 downto 4);
signal RIN_D_CNT_intermed_1 : std_logic_vector(1 downto 0);
signal R_E_CTRL_PC3DOWNTO2_intermed_4 : std_logic_vector(3 downto 2);
signal V_M_DCI_SIGNED_shadow_intermed_2 : STD_ULOGIC;
signal R_D_CNT_intermed_2 : std_logic_vector(1 downto 0);
signal R_E_CTRL_INST20_intermed_1 : STD_LOGIC;
signal RIN_M_DCI_SIGNED_intermed_1 : STD_ULOGIC;
signal RIN_D_PC3DOWNTO2_intermed_5 : std_logic_vector(3 downto 2);
signal RIN_A_CTRL_INST19_intermed_3 : STD_LOGIC;
signal V_E_CTRL_shadow_intermed_1 : PIPELINE_CTRL_TYPE;
signal RIN_A_CTRL_WICC_intermed_1 : STD_ULOGIC;
signal V_X_DATA1_shadow_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_D_CWP_intermed_2 : std_logic_vector(2 downto 0);
signal R_E_CTRL_INST24_intermed_2 : STD_LOGIC;
signal V_A_CTRL_WREG_shadow_intermed_2 : STD_ULOGIC;
signal DCO_DATA031_intermed_2 : STD_LOGIC;
signal R_M_CTRL_TT_intermed_1 : std_logic_vector(5 downto 0);
signal RIN_E_CTRL_WREG_intermed_3 : STD_ULOGIC;
signal V_E_YMSB_shadow_intermed_1 : STD_ULOGIC;
signal IRIN_ADDR31DOWNTO2_intermed_3 : std_logic_vector(31 downto 2);
signal EX_JUMP_ADDRESS3DOWNTO2_shadow_intermed_1 : std_logic_vector(3 downto 2);
signal V_M_CTRL_INST_shadow_intermed_2 : std_logic_vector(31 downto 0);
signal DE_INST24_shadow_intermed_3 : STD_LOGIC;
signal V_D_PC31DOWNTO12_shadow_intermed_2 : std_logic_vector(31 downto 12);
signal V_A_CTRL_PC_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_X_RESULT6DOWNTO0_intermed_1 : std_logic_vector(6 downto 0);
signal R_A_CTRL_PC31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2);
signal V_E_CTRL_CNT_shadow_intermed_1 : std_logic_vector(1 downto 0);
signal VIR_ADDR3DOWNTO2_shadow_intermed_1 : std_logic_vector(3 downto 2);
signal RIN_A_CTRL_INST_intermed_2 : std_logic_vector(31 downto 0);
signal RIN_A_CTRL_intermed_3 : PIPELINE_CTRL_TYPE;
signal RIN_M_RESULT1DOWNTO0_intermed_1 : std_logic_vector(1 downto 0);
signal R_A_CTRL_PV_intermed_3 : STD_ULOGIC;
signal R_D_PC31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2);
signal R_A_CTRL_PC31DOWNTO4_intermed_5 : std_logic_vector(31 downto 4);
signal RIN_A_DIVSTART_intermed_1 : STD_ULOGIC;
signal VIR_ADDR31DOWNTO12_shadow_intermed_2 : std_logic_vector(31 downto 12);
signal V_E_CTRL_INST20_shadow_intermed_2 : STD_LOGIC;
signal RIN_M_CTRL_TT_intermed_1 : std_logic_vector(5 downto 0);
signal RIN_E_CTRL_RD7DOWNTO0_intermed_3 : std_logic_vector(7 downto 0);
signal RIN_D_CWP_intermed_1 : std_logic_vector(2 downto 0);
signal RIN_X_CTRL_WREG_intermed_1 : STD_ULOGIC;
signal RIN_X_CTRL_PC31DOWNTO2_intermed_4 : std_logic_vector(31 downto 2);
signal V_M_CTRL_PC31DOWNTO2_shadow_intermed_5 : std_logic_vector(31 downto 2);
signal RIN_D_PC31DOWNTO2_intermed_7 : std_logic_vector(31 downto 2);
signal RIN_X_CTRL_PC31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2);
signal DSUR_CRDY2_intermed_1 : STD_LOGIC;
signal R_E_CTRL_PC3DOWNTO2_intermed_2 : std_logic_vector(3 downto 2);
signal V_A_CTRL_RD7DOWNTO0_shadow_intermed_1 : std_logic_vector(7 downto 0);
signal R_D_PC31DOWNTO12_intermed_3 : std_logic_vector(31 downto 12);
signal RIN_X_DATA031_intermed_2 : STD_LOGIC;
signal RIN_D_PC31DOWNTO4_intermed_4 : std_logic_vector(31 downto 4);
signal RIN_A_CTRL_INST_intermed_4 : std_logic_vector(31 downto 0);
signal V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 : std_logic_vector(31 downto 2);
signal V_M_CTRL_PC31DOWNTO4_shadow_intermed_2 : std_logic_vector(31 downto 4);
signal DE_INST19_shadow_intermed_1 : STD_LOGIC;
signal RIN_E_CTRL_PC31DOWNTO2_intermed_3 : std_logic_vector(31 downto 2);
signal V_A_CTRL_RD7DOWNTO0_shadow_intermed_2 : std_logic_vector(7 downto 0);
signal V_E_CTRL_INST_shadow_intermed_3 : std_logic_vector(31 downto 0);
signal RIN_X_CTRL_PC31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_X_CTRL_intermed_1 : PIPELINE_CTRL_TYPE;
signal R_D_PC31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12);
signal RIN_A_CTRL_ANNUL_intermed_2 : STD_ULOGIC;
signal V_A_CTRL_CNT_shadow_intermed_3 : std_logic_vector(1 downto 0);
signal R_A_CTRL_PC31DOWNTO12_intermed_6 : std_logic_vector(31 downto 12);
signal V_M_CTRL_PC31DOWNTO12_shadow_intermed_4 : std_logic_vector(31 downto 12);
signal VIR_ADDR31DOWNTO2_shadow_intermed_3 : std_logic_vector(31 downto 2);
signal V_A_MULSTART_shadow_intermed_1 : STD_ULOGIC;
signal RIN_X_DATA1_intermed_2 : std_logic_vector(31 downto 0);
signal RIN_E_CTRL_PC_intermed_2 : std_logic_vector(31 downto 2);
signal V_E_CTRL_PC31DOWNTO12_shadow_intermed_5 : std_logic_vector(31 downto 12);
signal V_M_DCI_SIZE_shadow_intermed_1 : std_logic_vector(1 downto 0);
signal V_A_CTRL_PC31DOWNTO4_shadow_intermed_3 : std_logic_vector(31 downto 4);
signal R_X_RESULT6DOWNTO03DOWNTO0_intermed_3 : std_logic_vector(3 downto 0);
signal R_D_PC31DOWNTO4_intermed_6 : std_logic_vector(31 downto 4);
signal EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_2 : STD_LOGIC_VECTOR(32 downto 3);
signal V_A_CTRL_PV_shadow_intermed_4 : STD_ULOGIC;
signal V_A_CTRL_TT_shadow_intermed_4 : std_logic_vector(5 downto 0);
signal V_X_CTRL_PC3DOWNTO2_shadow_intermed_3 : std_logic_vector(3 downto 2);
signal RIN_X_DATA0_intermed_2 : std_logic_vector(31 downto 0);
signal R_A_CTRL_TT3DOWNTO0_intermed_4 : std_logic_vector(3 downto 0);
signal RIN_D_PC31DOWNTO4_intermed_3 : std_logic_vector(31 downto 4);
signal V_A_CTRL_WREG_shadow_intermed_4 : STD_ULOGIC;
signal RIN_A_CTRL_PC3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2);
signal RIN_D_PC31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2);
signal R_M_CTRL_PC_intermed_2 : std_logic_vector(31 downto 2);
signal R_F_PC31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_M_CTRL_WREG_intermed_1 : STD_ULOGIC;
signal RIN_W_WREG_intermed_1 : STD_ULOGIC;
signal RIN_D_PC31DOWNTO4_intermed_6 : std_logic_vector(31 downto 4);
signal R_D_ANNUL_intermed_1 : STD_ULOGIC;
signal R_A_CTRL_INST_intermed_3 : std_logic_vector(31 downto 0);
signal RIN_M_CTRL_PC31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_E_CTRL_WREG_intermed_2 : STD_ULOGIC;
signal V_E_SARI_shadow_intermed_1 : STD_ULOGIC;
signal R_E_CTRL_RD6DOWNTO0_intermed_2 : std_logic_vector(6 downto 0);
signal V_A_CTRL_PC31DOWNTO2_shadow_intermed_6 : std_logic_vector(31 downto 2);
signal R_A_CTRL_CNT_intermed_3 : std_logic_vector(1 downto 0);
signal RIN_M_CTRL_PV_intermed_2 : STD_ULOGIC;
signal R_A_CTRL_LD_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_WICC_shadow_intermed_2 : STD_ULOGIC;
signal RIN_D_PC31DOWNTO2_intermed_5 : std_logic_vector(31 downto 2);
signal V_D_PC3DOWNTO2_shadow_intermed_3 : std_logic_vector(3 downto 2);
signal RIN_A_CTRL_PC3DOWNTO2_intermed_6 : std_logic_vector(3 downto 2);
signal RIN_X_DATA04DOWNTO0_intermed_1 : std_logic_vector(4 downto 0);
signal DSUIN_CRDY2_intermed_1 : STD_LOGIC;
signal RIN_D_PC31DOWNTO12_intermed_4 : std_logic_vector(31 downto 12);
signal R_E_CTRL_RD6DOWNTO0_intermed_1 : std_logic_vector(6 downto 0);
signal RIN_A_CTRL_INST20_intermed_1 : STD_LOGIC;
signal R_M_RESULT1DOWNTO0_intermed_2 : std_logic_vector(1 downto 0);
signal RIN_M_DCI_SIZE_intermed_2 : std_logic_vector(1 downto 0);
signal DE_INST19_shadow_intermed_3 : STD_LOGIC;
signal IRIN_ADDR31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12);
signal V_A_CTRL_ANNUL_shadow_intermed_4 : STD_ULOGIC;
signal R_E_CTRL_CNT_intermed_1 : std_logic_vector(1 downto 0);
signal V_E_CTRL_INST24_shadow_intermed_2 : STD_LOGIC;
signal RIN_A_CTRL_PC31DOWNTO4_intermed_2 : std_logic_vector(31 downto 4);
signal IRIN_PWD_intermed_1 : STD_ULOGIC;
signal V_D_MEXC_shadow_intermed_5 : STD_ULOGIC;
signal RIN_A_CTRL_PV_intermed_1 : STD_ULOGIC;
signal V_A_CTRL_WICC_shadow_intermed_1 : STD_ULOGIC;
signal R_A_CTRL_PC_intermed_1 : std_logic_vector(31 downto 2);
signal V_F_PC31DOWNTO4_shadow_intermed_1 : std_logic_vector(31 downto 4);
signal R_A_CTRL_RD7DOWNTO0_intermed_3 : std_logic_vector(7 downto 0);
signal RIN_A_CTRL_PC_intermed_1 : std_logic_vector(31 downto 2);
signal R_E_CTRL_INST_intermed_1 : std_logic_vector(31 downto 0);
signal R_E_CTRL_PC31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4);
signal V_A_CTRL_TRAP_shadow_intermed_4 : STD_ULOGIC;
signal V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 : std_logic_vector(31 downto 2);
signal V_F_PC31DOWNTO12_shadow_intermed_1 : std_logic_vector(31 downto 12);
signal R_A_CTRL_PC3DOWNTO2_intermed_5 : std_logic_vector(3 downto 2);
signal R_A_CTRL_CNT_intermed_1 : std_logic_vector(1 downto 0);
signal RIN_D_PC31DOWNTO2_intermed_6 : std_logic_vector(31 downto 2);
signal R_E_CTRL_PC3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2);
signal RIN_X_DATA0_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_E_CTRL_PC_intermed_3 : std_logic_vector(31 downto 2);
signal R_X_CTRL_PC31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12);
signal RIN_X_DATA03_intermed_1 : STD_LOGIC;
signal R_X_DATA04DOWNTO0_intermed_2 : std_logic_vector(4 downto 0);
signal R_E_CTRL_ANNUL_intermed_1 : STD_ULOGIC;
signal V_A_CTRL_RD7DOWNTO0_shadow_intermed_3 : std_logic_vector(7 downto 0);
signal V_M_CTRL_TT3DOWNTO0_shadow_intermed_3 : std_logic_vector(3 downto 0);
signal RIN_X_MAC_intermed_1 : STD_ULOGIC;
signal V_E_SHCNT_shadow_intermed_1 : std_logic_vector(4 downto 0);
signal V_M_CTRL_TT3DOWNTO0_shadow_intermed_2 : std_logic_vector(3 downto 0);
signal V_D_PC31DOWNTO12_shadow_intermed_4 : std_logic_vector(31 downto 12);
signal RIN_D_PC31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12);
signal V_E_CTRL_PC3DOWNTO2_shadow_intermed_5 : std_logic_vector(3 downto 2);
signal RIN_E_CTRL_RETT_intermed_2 : STD_ULOGIC;
signal R_M_CTRL_PC31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2);
signal V_E_OP23_shadow_intermed_1 : STD_LOGIC;
signal V_D_PC_shadow_intermed_2 : std_logic_vector(31 downto 2);
signal R_D_PC3DOWNTO2_intermed_6 : std_logic_vector(3 downto 2);
signal R_M_CTRL_PV_intermed_1 : STD_ULOGIC;
signal RIN_W_RESULT_intermed_1 : std_logic_vector(31 downto 0);
signal V_E_CTRL_ANNUL_shadow_intermed_2 : STD_ULOGIC;
signal V_E_CTRL_PV_shadow_intermed_1 : STD_ULOGIC;
signal RIN_X_LADDR_intermed_1 : std_logic_vector(1 downto 0);
signal RIN_A_CTRL_PC_intermed_5 : std_logic_vector(31 downto 2);
signal XC_VECTT3DOWNTO0_shadow_intermed_1 : STD_LOGIC_VECTOR(3 downto 0);
signal R_E_CTRL_WREG_intermed_1 : STD_ULOGIC;
signal RIN_X_DATA03_intermed_2 : STD_LOGIC;
signal RIN_A_CTRL_TT_intermed_3 : std_logic_vector(5 downto 0);
signal V_D_STEP_shadow_intermed_1 : STD_ULOGIC;
signal R_M_CTRL_PC31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12);
signal DE_INST19_shadow_intermed_2 : STD_LOGIC;
signal RIN_M_CTRL_PC31DOWNTO2_intermed_3 : std_logic_vector(31 downto 2);
signal V_X_CTRL_TRAP_shadow_intermed_1 : STD_ULOGIC;
signal RIN_D_MEXC_intermed_5 : STD_ULOGIC;
signal RIN_X_CTRL_TRAP_intermed_1 : STD_ULOGIC;
signal V_D_PC3DOWNTO2_shadow_intermed_4 : std_logic_vector(3 downto 2);
signal V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 : std_logic_vector(3 downto 0);
signal RIN_A_CTRL_PC3DOWNTO2_intermed_5 : std_logic_vector(3 downto 2);
signal RIN_M_CTRL_PC31DOWNTO4_intermed_3 : std_logic_vector(31 downto 4);
signal RIN_M_CTRL_PC31DOWNTO2_intermed_4 : std_logic_vector(31 downto 2);
signal RIN_F_BRANCH_intermed_1 : STD_ULOGIC;
signal R_D_PC3DOWNTO2_intermed_5 : std_logic_vector(3 downto 2);
signal RIN_A_CTRL_WREG_intermed_1 : STD_ULOGIC;
signal RIN_D_INST0_intermed_2 : std_logic_vector(31 downto 0);
signal R_M_CTRL_CNT_intermed_1 : std_logic_vector(1 downto 0);
signal RIN_E_CTRL_RD7DOWNTO0_intermed_1 : std_logic_vector(7 downto 0);
signal RIN_A_CTRL_PC_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_X_CTRL_PC_intermed_1 : std_logic_vector(31 downto 2);
signal R_A_SU_intermed_1 : STD_ULOGIC;
signal RIN_A_CTRL_TT_intermed_4 : std_logic_vector(5 downto 0);
signal V_X_DATA00_shadow_intermed_2 : STD_LOGIC;
signal RIN_A_CTRL_PC31DOWNTO4_intermed_4 : std_logic_vector(31 downto 4);
signal RIN_A_JMPL_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_WREG_shadow_intermed_3 : STD_ULOGIC;
signal V_A_CTRL_WREG_shadow_intermed_1 : STD_ULOGIC;
signal RIN_M_CTRL_ANNUL_intermed_1 : STD_ULOGIC;
signal RIN_X_CTRL_PC31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12);
signal VIR_ADDR31DOWNTO2_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal V_A_CTRL_PC3DOWNTO2_shadow_intermed_1 : std_logic_vector(3 downto 2);
signal RIN_E_CTRL_TT3DOWNTO0_intermed_3 : std_logic_vector(3 downto 0);
signal RIN_M_CTRL_RD7DOWNTO0_intermed_2 : std_logic_vector(7 downto 0);
signal V_E_CTRL_TRAP_shadow_intermed_3 : STD_ULOGIC;
signal V_A_CTRL_CNT_shadow_intermed_2 : std_logic_vector(1 downto 0);
signal V_E_CTRL_ANNUL_shadow_intermed_1 : STD_ULOGIC;
signal V_W_S_TT3DOWNTO0_shadow_intermed_1 : STD_LOGIC_VECTOR(3 downto 0);
signal RIN_M_CTRL_CNT_intermed_1 : std_logic_vector(1 downto 0);
signal DSUR_CRDY2_intermed_2 : STD_LOGIC;
signal V_E_CTRL_RD6DOWNTO0_shadow_intermed_1 : std_logic_vector(6 downto 0);
signal V_A_CTRL_CNT_shadow_intermed_1 : std_logic_vector(1 downto 0);
signal R_E_CTRL_PC_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_M_SU_intermed_1 : STD_ULOGIC;
signal RIN_A_CTRL_RD6DOWNTO0_intermed_1 : std_logic_vector(6 downto 0);
signal R_M_CTRL_TT3DOWNTO0_intermed_3 : std_logic_vector(3 downto 0);
signal RIN_M_CTRL_TT3DOWNTO0_intermed_4 : std_logic_vector(3 downto 0);
signal V_A_CTRL_INST19_shadow_intermed_1 : STD_LOGIC;
signal R_D_PC31DOWNTO2_intermed_5 : std_logic_vector(31 downto 2);
signal RIN_E_CTRL_CNT_intermed_3 : std_logic_vector(1 downto 0);
signal R_E_CTRL_PC31DOWNTO12_intermed_3 : std_logic_vector(31 downto 12);
signal RIN_E_CTRL_TRAP_intermed_1 : STD_ULOGIC;
signal RIN_X_DATA00_intermed_3 : STD_LOGIC;
signal R_E_CTRL_PC_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_E_OP131_intermed_1 : STD_LOGIC;
signal R_D_CNT_intermed_1 : std_logic_vector(1 downto 0);
signal R_D_PC_intermed_3 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_PC31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12);
signal R_M_CTRL_WREG_intermed_1 : STD_ULOGIC;
signal R_D_PC31DOWNTO2_intermed_4 : std_logic_vector(31 downto 2);
signal DE_INST_shadow_intermed_3 : std_logic_vector(31 downto 0);
signal RIN_D_PC_intermed_3 : std_logic_vector(31 downto 2);
signal V_A_CTRL_INST20_shadow_intermed_3 : STD_LOGIC;
signal R_A_CTRL_TT3DOWNTO0_intermed_5 : std_logic_vector(3 downto 0);
signal RIN_A_CTRL_CNT_intermed_2 : std_logic_vector(1 downto 0);
signal RIN_A_CTRL_intermed_2 : PIPELINE_CTRL_TYPE;
signal RIN_X_CTRL_PC_intermed_2 : std_logic_vector(31 downto 2);
signal R_A_CTRL_WREG_intermed_1 : STD_ULOGIC;
signal V_X_CTRL_PC31DOWNTO2_shadow_intermed_4 : std_logic_vector(31 downto 2);
signal R_X_CTRL_PC31DOWNTO2_intermed_3 : std_logic_vector(31 downto 2);
signal RIN_D_PC_intermed_6 : std_logic_vector(31 downto 2);
signal RIN_E_CTRL_PC31DOWNTO4_intermed_3 : std_logic_vector(31 downto 4);
signal R_X_CTRL_PC31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2);
signal V_A_ET_shadow_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_PC31DOWNTO4_shadow_intermed_1 : std_logic_vector(31 downto 4);
signal RIN_A_CTRL_INST20_intermed_3 : STD_LOGIC;
signal RIN_W_EXCEPT_intermed_1 : STD_ULOGIC;
signal V_X_DATA031_shadow_intermed_2 : STD_LOGIC;
signal R_A_CTRL_ANNUL_intermed_1 : STD_ULOGIC;
signal R_F_PC31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12);
signal RIN_E_CTRL_RD6DOWNTO0_intermed_2 : std_logic_vector(6 downto 0);
signal VIR_ADDR31DOWNTO2_shadow_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_X_DATA00_intermed_1 : STD_LOGIC;
signal RIN_E_CTRL_ANNUL_intermed_1 : STD_ULOGIC;
signal RIN_E_CTRL_PC31DOWNTO4_intermed_5 : std_logic_vector(31 downto 4);
signal V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_3 : std_logic_vector(3 downto 0);
signal V_M_CTRL_WICC_shadow_intermed_1 : STD_ULOGIC;
signal V_A_CTRL_PC31DOWNTO2_shadow_intermed_7 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_RETT_intermed_1 : STD_ULOGIC;
signal RIN_E_CTRL_PC31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2);
signal V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_D_PC31DOWNTO12_intermed_5 : std_logic_vector(31 downto 12);
signal VIR_ADDR3DOWNTO2_shadow_intermed_2 : std_logic_vector(3 downto 2);
signal R_A_CTRL_PV_intermed_2 : STD_ULOGIC;
signal V_A_CTRL_PC3DOWNTO2_shadow_intermed_2 : std_logic_vector(3 downto 2);
signal R_E_CTRL_PC3DOWNTO2_intermed_3 : std_logic_vector(3 downto 2);
signal V_A_CTRL_ANNUL_shadow_intermed_3 : STD_ULOGIC;
signal RIN_A_CTRL_PC3DOWNTO2_intermed_4 : std_logic_vector(3 downto 2);
signal V_A_CTRL_TT3DOWNTO0_shadow_intermed_3 : std_logic_vector(3 downto 0);
signal R_A_CTRL_PC3DOWNTO2_intermed_2 : std_logic_vector(3 downto 2);
signal V_D_CNT_shadow_intermed_2 : std_logic_vector(1 downto 0);
signal V_M_CTRL_ANNUL_shadow_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_M_CTRL_PC31DOWNTO4_intermed_2 : std_logic_vector(31 downto 4);
signal R_M_CTRL_TT3DOWNTO0_intermed_1 : std_logic_vector(3 downto 0);
signal V_E_CTRL_LD_shadow_intermed_2 : STD_ULOGIC;
signal RIN_X_CTRL_ANNUL_intermed_1 : STD_ULOGIC;
signal RIN_D_PC3DOWNTO2_intermed_3 : std_logic_vector(3 downto 2);
signal V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 : std_logic_vector(31 downto 2);
signal RIN_E_CTRL_TT_intermed_2 : std_logic_vector(5 downto 0);
signal RIN_E_CTRL_CNT_intermed_2 : std_logic_vector(1 downto 0);
signal RIN_A_CTRL_PC_intermed_4 : std_logic_vector(31 downto 2);
signal RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_4 : std_logic_vector(3 downto 0);
signal R_D_PC31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12);
signal XC_TRAP_ADDRESS31DOWNTO4_shadow_intermed_1 : std_logic_vector(31 downto 4);
signal RIN_A_CTRL_INST24_intermed_3 : STD_LOGIC;
signal V_W_S_TT3DOWNTO0_shadow_intermed_2 : STD_LOGIC_VECTOR(3 downto 0);
signal RIN_E_CTRL_RD7DOWNTO0_intermed_2 : std_logic_vector(7 downto 0);
signal RIN_A_CTRL_INST24_intermed_1 : STD_LOGIC;
signal RIN_D_PC31DOWNTO4_intermed_2 : std_logic_vector(31 downto 4);
signal V_A_CTRL_shadow_intermed_2 : PIPELINE_CTRL_TYPE;
signal DE_INST_shadow_intermed_4 : std_logic_vector(31 downto 0);
signal RIN_E_CTRL_PV_intermed_3 : STD_ULOGIC;
signal V_A_CTRL_TT_shadow_intermed_2 : std_logic_vector(5 downto 0);
signal RIN_M_CTRL_PC_intermed_3 : std_logic_vector(31 downto 2);
signal V_A_CTRL_WREG_shadow_intermed_3 : STD_ULOGIC;
signal R_M_CTRL_RD6DOWNTO0_intermed_1 : std_logic_vector(6 downto 0);
signal XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_PV_intermed_2 : STD_ULOGIC;
signal RIN_E_CTRL_PC3DOWNTO2_intermed_2 : std_logic_vector(3 downto 2);
signal RIN_X_CTRL_RD7DOWNTO0_intermed_1 : std_logic_vector(7 downto 0);
signal V_A_CTRL_TRAP_shadow_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_TRAP_shadow_intermed_1 : STD_ULOGIC;
signal RIN_E_MAC_intermed_1 : STD_ULOGIC;
signal R_X_DATA00_intermed_2 : STD_LOGIC;
signal RIN_E_MAC_intermed_2 : STD_ULOGIC;
signal RIN_A_CTRL_RD7DOWNTO0_intermed_4 : std_logic_vector(7 downto 0);
signal RIN_A_CTRL_PC31DOWNTO2_intermed_7 : std_logic_vector(31 downto 2);
signal R_M_CTRL_PC31DOWNTO12_intermed_3 : std_logic_vector(31 downto 12);
signal V_D_PC_shadow_intermed_3 : std_logic_vector(31 downto 2);
signal RIN_D_PC31DOWNTO4_intermed_5 : std_logic_vector(31 downto 4);
signal V_M_RESULT1DOWNTO0_shadow_intermed_2 : std_logic_vector(1 downto 0);
signal R_E_CTRL_PC31DOWNTO4_intermed_2 : std_logic_vector(31 downto 4);
signal V_E_CTRL_PC31DOWNTO12_shadow_intermed_3 : std_logic_vector(31 downto 12);
signal V_X_INTACK_shadow_intermed_1 : STD_ULOGIC;
signal RIN_A_CTRL_ANNUL_intermed_5 : STD_ULOGIC;
signal V_M_CTRL_PC31DOWNTO4_shadow_intermed_3 : std_logic_vector(31 downto 4);
signal V_A_CTRL_TT3DOWNTO0_shadow_intermed_4 : std_logic_vector(3 downto 0);
signal RIN_X_RESULT_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_E_CTRL_TT3DOWNTO0_intermed_5 : std_logic_vector(3 downto 0);
signal RIN_A_CTRL_PC31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2);
signal EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal V_D_PC3DOWNTO2_shadow_intermed_5 : std_logic_vector(3 downto 2);
signal DE_INST20_shadow_intermed_1 : STD_LOGIC;
signal V_E_CTRL_RD7DOWNTO0_shadow_intermed_2 : std_logic_vector(7 downto 0);
signal V_X_CTRL_PC31DOWNTO12_shadow_intermed_4 : std_logic_vector(31 downto 12);
signal V_E_CTRL_TRAP_shadow_intermed_2 : STD_ULOGIC;
signal V_A_CTRL_PC31DOWNTO4_shadow_intermed_5 : std_logic_vector(31 downto 4);
signal V_A_CTRL_RD6DOWNTO0_shadow_intermed_2 : std_logic_vector(6 downto 0);
signal RIN_A_CTRL_PC31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12);
signal IR_ADDR31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12);
signal RIN_E_ALUCIN_intermed_1 : STD_ULOGIC;
signal R_X_CTRL_PC31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12);
signal R_A_CTRL_PC3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2);
signal DE_INST_shadow_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_M_CTRL_INST_intermed_2 : std_logic_vector(31 downto 0);
signal R_A_CTRL_TRAP_intermed_2 : STD_ULOGIC;
signal RIN_A_CTRL_PC31DOWNTO12_intermed_4 : std_logic_vector(31 downto 12);
signal R_A_CTRL_WREG_intermed_2 : STD_ULOGIC;
signal R_M_CTRL_PC31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4);
signal V_E_OP13_shadow_intermed_1 : STD_LOGIC;
signal V_A_CTRL_INST24_shadow_intermed_1 : STD_LOGIC;
signal V_X_CTRL_PC31DOWNTO12_shadow_intermed_3 : std_logic_vector(31 downto 12);
signal IRIN_ADDR31DOWNTO12_intermed_3 : std_logic_vector(31 downto 12);
signal V_X_CTRL_PC_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal R_M_CTRL_PC3DOWNTO2_intermed_3 : std_logic_vector(3 downto 2);
signal V_E_CTRL_PC3DOWNTO2_shadow_intermed_2 : std_logic_vector(3 downto 2);
signal RIN_X_CTRL_TT_intermed_1 : std_logic_vector(5 downto 0);
signal V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_TT3DOWNTO0_intermed_6 : std_logic_vector(3 downto 0);
signal RIN_D_PC3DOWNTO2_intermed_7 : std_logic_vector(3 downto 2);
signal V_A_CTRL_INST_shadow_intermed_2 : std_logic_vector(31 downto 0);
signal V_X_CTRL_PC31DOWNTO4_shadow_intermed_1 : std_logic_vector(31 downto 4);
signal V_M_RESULT1DOWNTO0_shadow_intermed_1 : std_logic_vector(1 downto 0);
signal R_A_CTRL_INST24_intermed_2 : STD_LOGIC;
signal R_F_PC31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2);
signal V_A_CTRL_TRAP_shadow_intermed_3 : STD_ULOGIC;
signal R_D_CNT_intermed_4 : std_logic_vector(1 downto 0);
signal RIN_A_CTRL_WREG_intermed_4 : STD_ULOGIC;
signal V_M_CTRL_PC31DOWNTO4_shadow_intermed_1 : std_logic_vector(31 downto 4);
signal RIN_A_CTRL_PC3DOWNTO2_intermed_3 : std_logic_vector(3 downto 2);
signal V_E_CTRL_INST20_shadow_intermed_1 : STD_LOGIC;
signal R_D_MEXC_intermed_2 : STD_ULOGIC;
signal R_D_PC_intermed_4 : std_logic_vector(31 downto 2);
signal RIN_D_PC_intermed_1 : std_logic_vector(31 downto 2);
signal IRIN_ADDR3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2);
signal V_E_CTRL_RD7DOWNTO0_shadow_intermed_1 : std_logic_vector(7 downto 0);
signal RIN_E_OP1_intermed_1 : std_logic_vector(31 downto 0);
signal V_D_PC31DOWNTO4_shadow_intermed_3 : std_logic_vector(31 downto 4);
signal V_A_CTRL_PV_shadow_intermed_3 : STD_ULOGIC;
signal V_D_PC31DOWNTO2_shadow_intermed_6 : std_logic_vector(31 downto 2);
signal V_X_CTRL_TT3DOWNTO0_shadow_intermed_2 : std_logic_vector(3 downto 0);
signal DE_INST20_shadow_intermed_2 : STD_LOGIC;
signal V_E_CTRL_RD7DOWNTO0_shadow_intermed_3 : std_logic_vector(7 downto 0);
signal V_E_CTRL_CNT_shadow_intermed_3 : std_logic_vector(1 downto 0);
signal RIN_E_CTRL_RETT_intermed_1 : STD_ULOGIC;
signal V_D_PC31DOWNTO12_shadow_intermed_3 : std_logic_vector(31 downto 12);
signal V_D_PC31DOWNTO12_shadow_intermed_7 : std_logic_vector(31 downto 12);
signal V_M_CTRL_CNT_shadow_intermed_2 : std_logic_vector(1 downto 0);
signal R_D_PC31DOWNTO4_intermed_3 : std_logic_vector(31 downto 4);
signal RIN_A_CTRL_PC3DOWNTO2_intermed_2 : std_logic_vector(3 downto 2);
signal RIN_X_INTACK_intermed_1 : STD_ULOGIC;
signal RIN_E_OP231_intermed_1 : STD_LOGIC;
signal RIN_X_DATA031_intermed_3 : STD_LOGIC;
signal RIN_D_PC31DOWNTO2_intermed_4 : std_logic_vector(31 downto 2);
signal V_D_PC31DOWNTO4_shadow_intermed_2 : std_logic_vector(31 downto 4);
signal V_A_CTRL_ANNUL_shadow_intermed_1 : STD_ULOGIC;
signal R_M_CTRL_TT3DOWNTO0_intermed_2 : std_logic_vector(3 downto 0);
signal V_F_PC_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_E_ET_intermed_1 : STD_ULOGIC;
signal V_D_MEXC_shadow_intermed_3 : STD_ULOGIC;
signal XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_2 : std_logic_vector(31 downto 2);
signal V_F_PC31DOWNTO2_shadow_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_E_CTRL_PV_intermed_2 : STD_ULOGIC;
signal R_A_CTRL_RD7DOWNTO0_intermed_1 : std_logic_vector(7 downto 0);
signal ICO_MEXC_intermed_2 : STD_ULOGIC;
signal V_X_DCI_SIGNED_shadow_intermed_1 : STD_ULOGIC;
signal RIN_A_STEP_intermed_1 : STD_ULOGIC;
signal V_E_ALUCIN_shadow_intermed_1 : STD_ULOGIC;
signal V_A_CTRL_PC31DOWNTO4_shadow_intermed_6 : std_logic_vector(31 downto 4);
signal V_D_CNT_shadow_intermed_3 : std_logic_vector(1 downto 0);
signal V_D_PC31DOWNTO4_shadow_intermed_1 : std_logic_vector(31 downto 4);
signal RIN_X_CTRL_CNT_intermed_1 : std_logic_vector(1 downto 0);
signal V_D_ANNUL_shadow_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_PC31DOWNTO2_shadow_intermed_5 : std_logic_vector(31 downto 2);
signal V_E_CTRL_PV_shadow_intermed_3 : STD_ULOGIC;
signal VP_ERROR_shadow_intermed_1 : STD_ULOGIC;
signal RIN_X_RESULT6DOWNTO0_intermed_2 : std_logic_vector(6 downto 0);
signal R_D_PC31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4);
signal RIN_F_PC31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_E_CTRL_PC_intermed_1 : std_logic_vector(31 downto 2);
signal R_A_CTRL_PC31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12);
signal RIN_A_CTRL_PC31DOWNTO12_intermed_6 : std_logic_vector(31 downto 12);
signal V_A_CTRL_INST24_shadow_intermed_3 : STD_LOGIC;
signal V_E_CTRL_PC_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal V_X_CTRL_RD7DOWNTO0_shadow_intermed_1 : std_logic_vector(7 downto 0);
signal RIN_M_MUL_intermed_1 : STD_ULOGIC;
signal RIN_A_CTRL_INST20_intermed_2 : STD_LOGIC;
signal RIN_A_CTRL_RD7DOWNTO0_intermed_1 : std_logic_vector(7 downto 0);
signal V_A_CTRL_TT3DOWNTO0_shadow_intermed_2 : std_logic_vector(3 downto 0);
signal R_A_CTRL_INST_intermed_2 : std_logic_vector(31 downto 0);
signal RIN_E_CTRL_PC31DOWNTO2_intermed_6 : std_logic_vector(31 downto 2);
signal V_M_CTRL_TT_shadow_intermed_2 : std_logic_vector(5 downto 0);
signal V_D_INST0_shadow_intermed_2 : std_logic_vector(31 downto 0);
signal DCO_DATA03_intermed_1 : STD_LOGIC;
signal RIN_M_CTRL_intermed_1 : PIPELINE_CTRL_TYPE;
signal RIN_A_CTRL_RD7DOWNTO0_intermed_3 : std_logic_vector(7 downto 0);
signal V_D_PC31DOWNTO2_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_E_CTRL_PC31DOWNTO4_intermed_2 : std_logic_vector(31 downto 4);
signal V_D_PC31DOWNTO12_shadow_intermed_8 : std_logic_vector(31 downto 12);
signal RIN_E_CTRL_LD_intermed_1 : STD_ULOGIC;
signal R_X_CTRL_PC_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_WY_intermed_1 : STD_ULOGIC;
signal RIN_D_PC3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2);
signal R_E_CTRL_INST24_intermed_1 : STD_LOGIC;
signal V_M_DCI_shadow_intermed_1 : DC_IN_TYPE;
signal V_M_CTRL_shadow_intermed_1 : PIPELINE_CTRL_TYPE;
signal RIN_M_DCI_SIZE_intermed_1 : std_logic_vector(1 downto 0);
signal R_E_CTRL_PV_intermed_2 : STD_ULOGIC;
signal EX_ADD_RES32DOWNTO3_shadow_intermed_1 : STD_LOGIC_VECTOR(32 downto 3);
signal RIN_D_MEXC_intermed_1 : STD_ULOGIC;
signal R_A_CTRL_PC31DOWNTO2_intermed_3 : std_logic_vector(31 downto 2);
signal DSUIN_TBUFCNT_intermed_1 : STD_LOGIC_VECTOR(6 downto 0);
signal R_E_CTRL_PC31DOWNTO12_intermed_5 : std_logic_vector(31 downto 12);
signal R_A_CTRL_PC3DOWNTO2_intermed_4 : std_logic_vector(3 downto 2);
signal V_A_CTRL_INST20_shadow_intermed_1 : STD_LOGIC;
signal RIN_E_CTRL_PC31DOWNTO12_intermed_3 : std_logic_vector(31 downto 12);
signal V_A_CTRL_RD6DOWNTO0_shadow_intermed_4 : std_logic_vector(6 downto 0);
signal R_E_CTRL_PC31DOWNTO2_intermed_4 : std_logic_vector(31 downto 2);
signal R_A_CTRL_TT3DOWNTO0_intermed_2 : std_logic_vector(3 downto 0);
signal RIN_A_CTRL_CNT_intermed_4 : std_logic_vector(1 downto 0);
signal V_D_INST1_shadow_intermed_2 : std_logic_vector(31 downto 0);
signal RIN_E_CTRL_INST_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_X_DEBUG_intermed_1 : STD_ULOGIC;
signal RIN_M_Y_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_E_SHCNT_intermed_1 : std_logic_vector(4 downto 0);
signal RIN_E_CTRL_TRAP_intermed_2 : STD_ULOGIC;
signal RIN_F_PC31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12);
signal R_E_CTRL_INST20_intermed_2 : STD_LOGIC;
signal RIN_A_CTRL_ANNUL_intermed_3 : STD_ULOGIC;
signal RIN_D_ANNUL_intermed_2 : STD_ULOGIC;
signal ICO_DATA1_intermed_1 : std_logic_vector(31 downto 0);
signal R_M_CTRL_PC31DOWNTO12_intermed_4 : std_logic_vector(31 downto 12);
signal V_M_CTRL_TT3DOWNTO0_shadow_intermed_1 : std_logic_vector(3 downto 0);
signal V_X_CTRL_TT3DOWNTO0_shadow_intermed_1 : std_logic_vector(3 downto 0);
signal RIN_D_MEXC_intermed_3 : STD_ULOGIC;
signal V_E_CTRL_INST24_shadow_intermed_1 : STD_LOGIC;
signal R_W_S_TT3DOWNTO0_intermed_2 : STD_LOGIC_VECTOR(3 downto 0);
signal DSUIN_CRDY2_intermed_2 : STD_LOGIC;
signal V_X_RESULT6DOWNTO0_shadow_intermed_2 : std_logic_vector(6 downto 0);
signal RIN_D_PC3DOWNTO2_intermed_2 : std_logic_vector(3 downto 2);
signal V_D_PC_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal R_A_CTRL_PC31DOWNTO4_intermed_2 : std_logic_vector(31 downto 4);
signal RIN_E_CTRL_RD6DOWNTO0_intermed_3 : std_logic_vector(6 downto 0);
signal R_A_CTRL_PC31DOWNTO12_intermed_4 : std_logic_vector(31 downto 12);
signal V_X_DATA031_shadow_intermed_1 : STD_LOGIC;
signal RIN_X_ANNUL_ALL_intermed_2 : STD_ULOGIC;
signal IRIN_ADDR3DOWNTO2_intermed_2 : std_logic_vector(3 downto 2);
signal RIN_D_SET_intermed_1 : STD_LOGIC_VECTOR(0 downto 0);
signal DCO_DATA0_intermed_1 : std_logic_vector(31 downto 0);
signal R_E_CTRL_CNT_intermed_2 : std_logic_vector(1 downto 0);
signal RIN_W_S_S_intermed_2 : STD_ULOGIC;
signal IRIN_ADDR31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12);
signal RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_3 : std_logic_vector(3 downto 0);
signal RIN_W_S_TT3DOWNTO0_intermed_2 : STD_LOGIC_VECTOR(3 downto 0);
signal V_A_CTRL_LD_shadow_intermed_3 : STD_ULOGIC;
signal V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 : std_logic_vector(31 downto 2);
signal RIN_M_CTRL_PC_intermed_2 : std_logic_vector(31 downto 2);
signal R_D_INST1_intermed_2 : std_logic_vector(31 downto 0);
signal V_E_CTRL_shadow_intermed_2 : PIPELINE_CTRL_TYPE;
signal RIN_X_DATA1_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_A_SU_intermed_2 : STD_ULOGIC;
signal R_A_CTRL_RD6DOWNTO0_intermed_2 : std_logic_vector(6 downto 0);
signal RIN_A_CTRL_PC31DOWNTO2_intermed_3 : std_logic_vector(31 downto 2);
signal RIN_E_CTRL_intermed_1 : PIPELINE_CTRL_TYPE;
signal RIN_A_CTRL_RD6DOWNTO0_intermed_3 : std_logic_vector(6 downto 0);
signal RIN_A_CTRL_TT3DOWNTO0_intermed_1 : std_logic_vector(3 downto 0);
signal RIN_F_PC_intermed_1 : std_logic_vector(31 downto 2);
signal V_D_PC31DOWNTO2_shadow_intermed_8 : std_logic_vector(31 downto 2);
signal V_D_CNT_shadow_intermed_1 : std_logic_vector(1 downto 0);
signal RIN_A_CTRL_LD_intermed_2 : STD_ULOGIC;
signal V_D_PC31DOWNTO4_shadow_intermed_5 : std_logic_vector(31 downto 4);
signal RIN_M_CTRL_PC31DOWNTO4_intermed_4 : std_logic_vector(31 downto 4);
signal R_A_CTRL_RETT_intermed_1 : STD_ULOGIC;
signal RIN_E_CTRL_INST_intermed_3 : std_logic_vector(31 downto 0);
signal R_D_MEXC_intermed_4 : STD_ULOGIC;
signal RIN_M_RESULT1DOWNTO0_intermed_3 : std_logic_vector(1 downto 0);
signal RIN_D_CNT_intermed_5 : std_logic_vector(1 downto 0);
signal V_A_CTRL_PC31DOWNTO12_shadow_intermed_1 : std_logic_vector(31 downto 12);
signal R_D_PC31DOWNTO2_intermed_3 : std_logic_vector(31 downto 2);
signal RIN_M_CTRL_PC31DOWNTO12_intermed_4 : std_logic_vector(31 downto 12);
signal RIN_M_CTRL_TT3DOWNTO0_intermed_1 : std_logic_vector(3 downto 0);
signal RIN_D_ANNUL_intermed_1 : STD_ULOGIC;
signal V_A_CTRL_shadow_intermed_1 : PIPELINE_CTRL_TYPE;
signal V_E_CTRL_PC31DOWNTO12_shadow_intermed_1 : std_logic_vector(31 downto 12);
signal RIN_M_CTRL_PC3DOWNTO2_intermed_4 : std_logic_vector(3 downto 2);
signal V_A_CTRL_PC31DOWNTO12_shadow_intermed_5 : std_logic_vector(31 downto 12);
signal R_D_PC31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_E_CTRL_PC3DOWNTO2_intermed_5 : std_logic_vector(3 downto 2);
signal RIN_E_CTRL_PC31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12);
signal R_A_CTRL_PC_intermed_4 : std_logic_vector(31 downto 2);
signal R_A_CTRL_ANNUL_intermed_4 : STD_ULOGIC;
signal V_X_RESULT_shadow_intermed_1 : std_logic_vector(31 downto 0);
signal R_E_CTRL_PC31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2);
signal R_A_CTRL_PC31DOWNTO4_intermed_3 : std_logic_vector(31 downto 4);
signal V_D_CNT_shadow_intermed_5 : std_logic_vector(1 downto 0);
signal R_A_CTRL_TT_intermed_2 : std_logic_vector(5 downto 0);
signal RIN_A_CTRL_PC31DOWNTO12_intermed_5 : std_logic_vector(31 downto 12);
signal V_A_CTRL_TT3DOWNTO0_shadow_intermed_5 : std_logic_vector(3 downto 0);
signal RIN_W_S_S_intermed_1 : STD_ULOGIC;
signal V_M_CTRL_CNT_shadow_intermed_1 : std_logic_vector(1 downto 0);
signal V_A_CTRL_PC31DOWNTO12_shadow_intermed_7 : std_logic_vector(31 downto 12);
signal V_A_CTRL_WICC_shadow_intermed_2 : STD_ULOGIC;
signal R_X_DATA03_intermed_1 : STD_LOGIC;
signal RIN_M_DCI_intermed_1 : DC_IN_TYPE;
signal R_A_CTRL_CNT_intermed_2 : std_logic_vector(1 downto 0);
signal RIN_W_S_EF_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_RD6DOWNTO0_shadow_intermed_2 : std_logic_vector(6 downto 0);
signal RIN_A_CTRL_LD_intermed_3 : STD_ULOGIC;
signal V_M_CTRL_RD6DOWNTO0_shadow_intermed_1 : std_logic_vector(6 downto 0);
signal R_E_CTRL_INST_intermed_2 : std_logic_vector(31 downto 0);
signal RIN_M_CTRL_RD6DOWNTO0_intermed_1 : std_logic_vector(6 downto 0);
signal V_F_PC3DOWNTO2_shadow_intermed_1 : std_logic_vector(3 downto 2);
signal EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_2 : STD_LOGIC_VECTOR(30 downto 11);
signal V_X_ANNUL_ALL_shadow_intermed_3 : STD_ULOGIC;
signal V_F_PC31DOWNTO12_shadow_intermed_2 : std_logic_vector(31 downto 12);
signal RIN_E_CTRL_INST24_intermed_1 : STD_LOGIC;
signal R_A_CTRL_PV_intermed_1 : STD_ULOGIC;
signal RIN_A_CTRL_RETT_intermed_3 : STD_ULOGIC;
signal R_E_CTRL_TT_intermed_2 : std_logic_vector(5 downto 0);
signal RIN_D_PC31DOWNTO12_intermed_7 : std_logic_vector(31 downto 12);
signal EX_ADD_RES32DOWNTO34DOWNTO3_shadow_intermed_1 : STD_LOGIC_VECTOR(4 downto 3);
signal V_E_CTRL_INST_shadow_intermed_2 : std_logic_vector(31 downto 0);
signal V_M_CTRL_PC31DOWNTO12_shadow_intermed_1 : std_logic_vector(31 downto 12);
signal DCO_MEXC_intermed_1 : STD_ULOGIC;
signal RIN_E_CWP_intermed_1 : std_logic_vector(2 downto 0);
signal V_A_CTRL_CNT_shadow_intermed_4 : std_logic_vector(1 downto 0);
signal V_A_CTRL_ANNUL_shadow_intermed_2 : STD_ULOGIC;
signal R_A_CTRL_PC31DOWNTO12_intermed_3 : std_logic_vector(31 downto 12);
signal R_A_CTRL_PC31DOWNTO2_intermed_4 : std_logic_vector(31 downto 2);
signal R_X_RESULT6DOWNTO0_intermed_2 : std_logic_vector(6 downto 0);
signal RIN_A_SU_intermed_1 : STD_ULOGIC;
signal R_E_CTRL_intermed_1 : PIPELINE_CTRL_TYPE;
signal V_E_OP231_shadow_intermed_1 : STD_LOGIC;
signal RIN_A_CTRL_WREG_intermed_3 : STD_ULOGIC;
signal V_A_CTRL_INST_shadow_intermed_4 : std_logic_vector(31 downto 0);
signal V_E_CTRL_PC31DOWNTO12_shadow_intermed_6 : std_logic_vector(31 downto 12);
signal V_M_CTRL_PC3DOWNTO2_shadow_intermed_1 : std_logic_vector(3 downto 2);
signal RPIN_ERROR_intermed_2 : STD_ULOGIC;
signal R_E_CTRL_TT3DOWNTO0_intermed_3 : std_logic_vector(3 downto 0);
signal V_D_CWP_shadow_intermed_1 : std_logic_vector(2 downto 0);
signal V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_PV_intermed_3 : STD_ULOGIC;
signal RIN_M_CTRL_PC31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4);
signal RIN_E_CTRL_INST24_intermed_2 : STD_LOGIC;
signal RIN_X_DCI_SIZE_intermed_1 : std_logic_vector(1 downto 0);
signal RIN_F_PC31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12);
signal R_A_CTRL_TT3DOWNTO0_intermed_3 : std_logic_vector(3 downto 0);
signal DCO_DATA00_intermed_1 : STD_LOGIC;
signal V_M_Y31_shadow_intermed_1 : STD_LOGIC;
signal R_E_CTRL_PC31DOWNTO2_intermed_5 : std_logic_vector(31 downto 2);
signal R_A_CTRL_PC31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2);
signal V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal R_A_CTRL_INST19_intermed_1 : STD_LOGIC;
signal RIN_E_CTRL_TT_intermed_1 : std_logic_vector(5 downto 0);
signal RIN_E_CTRL_PC31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2);
signal R_X_CTRL_PC3DOWNTO2_intermed_2 : std_logic_vector(3 downto 2);
signal RIN_X_ANNUL_ALL_intermed_4 : STD_ULOGIC;
signal V_A_CTRL_INST_shadow_intermed_1 : std_logic_vector(31 downto 0);
signal V_X_CTRL_PC31DOWNTO12_shadow_intermed_2 : std_logic_vector(31 downto 12);
signal IRIN_ADDR31DOWNTO4_intermed_2 : std_logic_vector(31 downto 4);
signal RIN_E_CTRL_PC3DOWNTO2_intermed_4 : std_logic_vector(3 downto 2);
signal RIN_A_CTRL_PC31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4);
signal DCO_DATA04DOWNTO0_intermed_1 : std_logic_vector(4 downto 0);
signal RIN_E_CTRL_ANNUL_intermed_2 : STD_ULOGIC;
signal V_E_CTRL_INST19_shadow_intermed_1 : STD_LOGIC;
signal RIN_A_CTRL_PC_intermed_3 : std_logic_vector(31 downto 2);
signal V_X_DATA03_shadow_intermed_1 : STD_LOGIC;
signal V_E_OP1_shadow_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_M_CTRL_CNT_intermed_2 : std_logic_vector(1 downto 0);
signal RIN_A_CTRL_PC31DOWNTO2_intermed_6 : std_logic_vector(31 downto 2);
signal RIN_D_MEXC_intermed_2 : STD_ULOGIC;
signal R_D_PC31DOWNTO4_intermed_2 : std_logic_vector(31 downto 4);
signal RIN_X_CTRL_INST_intermed_1 : std_logic_vector(31 downto 0);
signal V_A_SU_shadow_intermed_2 : STD_ULOGIC;
signal V_M_Y31_shadow_intermed_2 : STD_LOGIC;
signal R_W_S_TT3DOWNTO0_intermed_1 : STD_LOGIC_VECTOR(3 downto 0);
signal R_A_CTRL_ANNUL_intermed_3 : STD_ULOGIC;
signal R_A_CTRL_TRAP_intermed_1 : STD_ULOGIC;
signal RIN_M_CTRL_WICC_intermed_1 : STD_ULOGIC;
signal R_D_PC31DOWNTO2_intermed_7 : std_logic_vector(31 downto 2);
signal RIN_X_ANNUL_ALL_intermed_1 : STD_ULOGIC;
signal V_M_CTRL_WREG_shadow_intermed_1 : STD_ULOGIC;
signal V_A_CTRL_RD7DOWNTO0_shadow_intermed_4 : std_logic_vector(7 downto 0);
signal RIN_A_RFE1_intermed_1 : STD_ULOGIC;
signal V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal V_D_PC31DOWNTO4_shadow_intermed_4 : std_logic_vector(31 downto 4);
signal R_A_CTRL_PC31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12);
signal V_M_MAC_shadow_intermed_1 : STD_ULOGIC;
signal V_D_PC31DOWNTO2_shadow_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_TRAP_intermed_2 : STD_ULOGIC;
signal R_E_CTRL_RD7DOWNTO0_intermed_1 : std_logic_vector(7 downto 0);
signal R_E_CTRL_PC_intermed_3 : std_logic_vector(31 downto 2);
signal R_X_DATA00_intermed_1 : STD_LOGIC;
signal V_X_ANNUL_ALL_shadow_intermed_1 : STD_ULOGIC;
signal R_D_PC_intermed_5 : std_logic_vector(31 downto 2);
signal R_X_DATA03_intermed_2 : STD_LOGIC;
signal RIN_F_PC31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4);
signal RIN_W_S_CWP_intermed_1 : std_logic_vector(2 downto 0);
signal V_W_S_PS_shadow_intermed_1 : STD_ULOGIC;
signal R_A_CTRL_intermed_1 : PIPELINE_CTRL_TYPE;
signal R_A_CTRL_TT_intermed_3 : std_logic_vector(5 downto 0);
signal RIN_A_CTRL_PC31DOWNTO4_intermed_6 : std_logic_vector(31 downto 4);
signal V_D_PC31DOWNTO2_shadow_intermed_7 : std_logic_vector(31 downto 2);
signal RIN_M_CTRL_PC31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2);
signal R_X_DATA1_intermed_2 : std_logic_vector(31 downto 0);
signal R_D_PC3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2);
signal RIN_X_CTRL_PC3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2);
signal V_E_MAC_shadow_intermed_1 : STD_ULOGIC;
signal RIN_X_ICC_intermed_1 : STD_LOGIC_VECTOR(3 downto 0);
signal RIN_M_MAC_intermed_1 : STD_ULOGIC;
signal RIN_W_S_TT3DOWNTO0_intermed_1 : STD_LOGIC_VECTOR(3 downto 0);
signal R_D_PC31DOWNTO4_intermed_4 : std_logic_vector(31 downto 4);
signal V_A_CTRL_PC3DOWNTO2_shadow_intermed_6 : std_logic_vector(3 downto 2);
signal R_X_ANNUL_ALL_intermed_1 : STD_ULOGIC;
signal EX_JUMP_ADDRESS_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_X_CTRL_PV_intermed_1 : STD_ULOGIC;
signal EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_2 : STD_LOGIC_VECTOR(32 downto 13);
signal RIN_A_CTRL_INST_intermed_1 : std_logic_vector(31 downto 0);
signal R_A_CTRL_RD6DOWNTO0_intermed_3 : std_logic_vector(6 downto 0);
signal IR_ADDR31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12);
signal RIN_D_PC3DOWNTO2_intermed_6 : std_logic_vector(3 downto 2);
signal RIN_M_Y31_intermed_2 : STD_LOGIC;
signal RIN_X_DATA04DOWNTO0_intermed_2 : std_logic_vector(4 downto 0);
signal V_D_PC31DOWNTO2_shadow_intermed_3 : std_logic_vector(31 downto 2);
signal R_M_DCI_SIZE_intermed_1 : std_logic_vector(1 downto 0);
signal V_E_CTRL_PC3DOWNTO2_shadow_intermed_4 : std_logic_vector(3 downto 2);
signal V_E_OP2_shadow_intermed_1 : std_logic_vector(31 downto 0);
signal V_E_CTRL_TT3DOWNTO0_shadow_intermed_5 : std_logic_vector(3 downto 0);
signal V_A_CTRL_INST20_shadow_intermed_2 : STD_LOGIC;
signal RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 : std_logic_vector(3 downto 0);
signal V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_4 : std_logic_vector(3 downto 0);
signal R_X_RESULT6DOWNTO03DOWNTO0_intermed_2 : std_logic_vector(3 downto 0);
signal RIN_M_CTRL_TRAP_intermed_2 : STD_ULOGIC;
signal V_A_CTRL_INST_shadow_intermed_3 : std_logic_vector(31 downto 0);
begin
comb : process(ico, dco, rfo, r, wpr, ir, dsur, rstn, holdn, irqi, dbgi, fpo, cpo, tbo, mulo, divo, dummy, rp, triggercpfault, handlerTrap)
variable v : registers;
variable vp : pwd_register_type;
variable vwpr : watchpoint_registers;
variable vdsu : dsu_registers;
variable npc : std_logic_vector(31 downto 2);
variable de_raddr1, de_raddr2 : std_logic_vector(9 downto 0);
variable de_rs2, de_rd : std_logic_vector(4 downto 0);
variable de_hold_pc, de_branch, de_fpop, de_ldlock : std_ulogic;
variable de_cwp, de_cwp2 : cwptype;
variable de_inull : std_ulogic;
variable de_ren1, de_ren2 : std_ulogic;
variable de_wcwp : std_ulogic;
variable de_inst : word;
variable de_branch_address : pctype;
variable de_icc : std_logic_vector(3 downto 0);
variable de_fbranch, de_cbranch : std_ulogic;
variable de_rs1mod : std_ulogic;
variable ra_op1, ra_op2 : word;
variable ra_div : std_ulogic;
variable ex_jump, ex_link_pc : std_ulogic;
variable ex_jump_address : pctype;
variable ex_add_res : std_logic_vector(32 downto 0);
variable ex_shift_res, ex_logic_res, ex_misc_res : word;
variable ex_edata, ex_edata2 : word;
variable ex_dci : dc_in_type;
variable ex_force_a2, ex_load, ex_ymsb : std_ulogic;
variable ex_op1, ex_op2, ex_result, ex_result2, mul_op2 : word;
variable ex_shcnt : std_logic_vector(4 downto 0);
variable ex_dsuen : std_ulogic;
variable ex_ldbp2 : std_ulogic;
variable ex_sari : std_ulogic;
variable me_inull, me_nullify, me_nullify2 : std_ulogic;
variable me_iflush : std_ulogic;
variable me_newtt : std_logic_vector(5 downto 0);
variable me_asr18 : word;
variable me_signed : std_ulogic;
variable me_size, me_laddr : std_logic_vector(1 downto 0);
variable me_icc : std_logic_vector(3 downto 0);
variable xc_result : word;
variable xc_df_result : word;
variable xc_waddr : std_logic_vector(9 downto 0);
variable xc_exception, xc_wreg : std_ulogic;
variable xc_trap_address : pctype;
variable xc_vectt : std_logic_vector(7 downto 0);
variable xc_trap : std_ulogic;
variable xc_fpexack : std_ulogic;
variable xc_rstn, xc_halt : std_ulogic;
-- variable wr_rf1_data, wr_rf2_data : word;
variable diagdata : word;
variable tbufi : tracebuf_in_type;
variable dbgm : std_ulogic;
variable fpcdbgwr : std_ulogic;
variable vfpi : fpc_in_type;
variable dsign : std_ulogic;
variable pwrd, sidle : std_ulogic;
variable vir : irestart_register;
variable icnt : std_ulogic;
variable tbufcntx : std_logic_vector(7-1 downto 0);
begin
v := r;
vwpr := wpr;
vdsu := dsur;
vp := rp;
xc_fpexack := '0';
sidle := '0';
fpcdbgwr := '0';
vir := ir;
xc_rstn := rstn;
-----------------------------------------------------------------------
-- WRITE STAGE
-----------------------------------------------------------------------
-- wr_rf1_data := rfo.data1; wr_rf2_data := rfo.data2;
-- if irfwt = 0 then
-- if r.w.wreg = '1' then
-- if r.a.rfa1 = r.w.wa then wr_rf1_data := r.w.result; end if;
-- if r.a.rfa2 = r.w.wa then wr_rf2_data := r.w.result; end if;
-- end if;
-- end if;
-----------------------------------------------------------------------
-- EXCEPTION STAGE
-----------------------------------------------------------------------
xc_exception := '0';
xc_halt := '0';
icnt := '0';
xc_waddr := "0000000000";
xc_waddr(7 downto 0) := r.x.ctrl.rd(7 downto 0);
xc_trap := r.x.mexc or r.x.ctrl.trap or handlerTrap;
v.x.nerror := rp.error;
if(handlerTrap = '1')then
xc_vectt := "00" & TT_WATCH;
elsif(triggerCPFault = '1')then
xc_vectt := "00" & TT_CPDIS;
xc_trap := '1';
elsif r.x.mexc = '1' then
xc_vectt := "00" & TT_DAEX;
elsif r.x.ctrl.tt = TT_TICC then
xc_vectt := '1' & r.x.result(6 downto 0);
else
xc_vectt := "00" & r.x.ctrl.tt;
end if;
if r.w.s.svt = '0' then
xc_trap_address(31 downto 4) := r.w.s.tba & xc_vectt;
else
xc_trap_address(31 downto 4) := r.w.s.tba & "00000000";
end if;
xc_trap_address(3 downto 2) := "00";
xc_wreg := '0';
v.x.annul_all := '0';
if (r.x.ctrl.ld = '1') then
if (lddel = 2) then
xc_result := ld_align(r.x.data, r.x.set, r.x.dci.size, r.x.laddr, r.x.dci.signed);
else
xc_result := r.x.data(0);
end if;
else
xc_result := r.x.result;
end if;
xc_df_result := xc_result;
dbgm := dbgexc(r, dbgi, xc_trap, xc_vectt);
if (dbgi.dsuen and dbgi.dbreak) = '0'then
v.x.debug := '0';
end if;
pwrd := '0';
case r.x.rstate is
when run =>
if (not r.x.ctrl.annul and r.x.ctrl.pv and not r.x.debug) = '1' then
icnt := holdn;
end if;
if dbgm = '1' then
v.x.annul_all := '1';
vir.addr := r.x.ctrl.pc;
v.x.rstate := dsu1;
v.x.debug := '1';
v.x.npc := npc_find(r);
vdsu.tt := xc_vectt;
vdsu.err := dbgerr(r, dbgi, xc_vectt);
elsif (pwrd = '1') and (ir.pwd = '0') then
v.x.annul_all := '1';
vir.addr := r.x.ctrl.pc;
v.x.rstate := dsu1;
v.x.npc := npc_find(r);
vp.pwd := '1';
elsif (r.x.ctrl.annul or xc_trap) = '0' then
xc_wreg := r.x.ctrl.wreg;
sp_write (r, wpr, v.w.s, vwpr);
vir.pwd := '0';
elsif ((not r.x.ctrl.annul) and xc_trap) = '1' then
xc_exception := '1';
xc_result := r.x.ctrl.pc(31 downto 2) & "00";
xc_wreg := '1';
v.w.s.tt := xc_vectt;
v.w.s.ps := r.w.s.s;
v.w.s.s := '1';
v.x.annul_all := '1';
v.x.rstate := trap;
xc_waddr := "0000000000";
xc_waddr(6 downto 0) := r.w.s.cwp & "0001";
v.x.npc := npc_find(r);
fpexack(r, xc_fpexack);
if r.w.s.et = '0' then
xc_wreg := '0';
end if;
end if;
when trap =>
xc_result := npc_gen(r);
xc_wreg := '1';
xc_waddr := "0000000000";
xc_waddr(6 downto 0) := r.w.s.cwp & "0010";
if (r.w.s.et = '1') then
v.w.s.et := '0';
v.x.rstate := run;
v.w.s.cwp := r.w.s.cwp - 1;
else
v.x.rstate := dsu1;
xc_wreg := '0';
vp.error := '1';
end if;
when dsu1 =>
xc_exception := '1';
v.x.annul_all := '1';
xc_trap_address(31 downto 2) := r.f.pc;
xc_trap_address(31 downto 2) := ir.addr;
vir.addr := npc_gen(r)(31 downto 2);
v.x.rstate := dsu2;
v.x.debug := r.x.debug;
when dsu2 =>
xc_exception := '1';
v.x.annul_all := '1';
xc_trap_address(31 downto 2) := r.f.pc;
sidle := (rp.pwd or rp.error) and ico.idle and dco.idle and not r.x.debug;
if dbgi.reset = '1' then
vp.pwd := '0';
vp.error := '0';
end if;
if (dbgi.dsuen and dbgi.dbreak) = '1'then
v.x.debug := '1';
end if;
diagwr(r, dsur, ir, dbgi, wpr, v.w.s, vwpr, vdsu.asi, xc_trap_address, vir.addr, vdsu.tbufcnt, xc_wreg, xc_waddr, xc_result, fpcdbgwr);
xc_halt := dbgi.halt;
if r.x.ipend = '1' then
vp.pwd := '0';
end if;
if (rp.error or rp.pwd or r.x.debug or xc_halt) = '0' then
v.x.rstate := run;
v.x.annul_all := '0';
vp.error := '0';
xc_trap_address(31 downto 2) := ir.addr;
v.x.debug := '0';
vir.pwd := '1';
end if;
when others =>
end case;
irq_intack(r, holdn, v.x.intack);
itrace(r, dsur, vdsu, xc_result, xc_exception, dbgi, rp.error, xc_trap, tbufcntx, tbufi);
vdsu.tbufcnt := tbufcntx;
v.w.except := xc_exception;
v.w.result := xc_result;
if (r.x.rstate = dsu2) then
v.w.except := '0';
end if;
v.w.wa := xc_waddr(7 downto 0);
v.w.wreg := xc_wreg and holdn;
rfi.wdata <= xc_result;
rfi.waddr <= xc_waddr;
rfi.wren <= (xc_wreg and holdn) and not dco.scanen;
irqo.intack <= r.x.intack and holdn;
irqo.irl <= r.w.s.tt(3 downto 0);
irqo.pwd <= rp.pwd;
irqo.fpen <= r.w.s.ef;
dbgo.halt <= xc_halt;
dbgo.pwd <= rp.pwd;
dbgo.idle <= sidle;
dbgo.icnt <= icnt;
dci.intack <= r.x.intack and holdn;
if (xc_rstn = '0') then
v.w.except := '0';
v.w.s.et := '0';
v.w.s.svt := '0';
v.w.s.dwt := '0';
v.w.s.ef := '0';-- needed for AX
v.x.annul_all := '1';
v.x.rstate := run;
vir.pwd := '0';
vp.pwd := '0';
v.x.debug := '0';
v.x.nerror := '0';
if (dbgi.dsuen and dbgi.dbreak) = '1' then
v.x.rstate := dsu1;
v.x.debug := '1';
end if;
end if;
if not FPEN then
v.w.s.ef := '0';
end if;
-----------------------------------------------------------------------
-- MEMORY STAGE
-----------------------------------------------------------------------
v.x.ctrl := r.m.ctrl;
v.x.dci := r.m.dci;
v.x.ctrl.rett := r.m.ctrl.rett and not r.m.ctrl.annul;
v.x.mac := r.m.mac;
v.x.laddr := r.m.result(1 downto 0);
v.x.ctrl.annul := r.m.ctrl.annul or v.x.annul_all;
mul_res(r, v.w.s.asr18, v.x.result, v.x.y, me_asr18, me_icc);
mem_trap(r, wpr, v.x.ctrl.annul, holdn, v.x.ctrl.trap, me_iflush, me_nullify, v.m.werr, v.x.ctrl.tt);
me_newtt := v.x.ctrl.tt;
irq_trap(r, ir, irqi.irl, v.x.ctrl.annul, v.x.ctrl.pv, v.x.ctrl.trap, me_newtt, me_nullify, v.m.irqen, v.m.irqen2, me_nullify2, v.x.ctrl.trap, v.x.ipend, v.x.ctrl.tt);
if (r.m.ctrl.ld or not dco.mds) = '1' then
v.x.data(0) := dco.data(0);
v.x.data(1) := dco.data(1);
v.x.set := dco.set(0 downto 0);
if dco.mds = '0' then
me_size := r.x.dci.size;
me_laddr := r.x.laddr;
me_signed := r.x.dci.signed;
else
me_size := v.x.dci.size;
me_laddr := v.x.laddr;
me_signed := v.x.dci.signed;
end if;
if lddel /= 2 then
v.x.data(0) := ld_align(v.x.data, v.x.set, me_size, me_laddr, me_signed);
end if;
end if;
v.x.mexc := dco.mexc;
v.x.icc := me_icc;
v.x.ctrl.wicc := r.m.ctrl.wicc and not v.x.annul_all;
if (r.x.rstate = dsu2) then
me_nullify2 := '0';
v.x.set := dco.set(0 downto 0);
end if;
dci.maddress <= r.m.result;
dci.msu <= r.m.su;
dci.esu <= r.e.su;
dci.enaddr <= r.m.dci.enaddr;
dci.asi <= r.m.dci.asi;
dci.size <= r.m.dci.size;
dci.nullify <= me_nullify2;
dci.lock <= r.m.dci.lock and not r.m.ctrl.annul;
dci.read <= r.m.dci.read;
dci.write <= r.m.dci.write;
dci.flush <= me_iflush;
dci.dsuen <= r.m.dci.dsuen;
dbgo.ipend <= v.x.ipend;
-----------------------------------------------------------------------
-- EXECUTE STAGE
-----------------------------------------------------------------------
v.m.ctrl := r.e.ctrl;
ex_op1 := r.e.op1;
ex_op2 := r.e.op2;
v.m.ctrl.rett := r.e.ctrl.rett and not r.e.ctrl.annul;
v.m.ctrl.wreg := r.e.ctrl.wreg and not v.x.annul_all;
ex_ymsb := r.e.ymsb;
mul_op2 := ex_op2;
ex_shcnt := r.e.shcnt;
v.e.cwp := r.a.cwp;
ex_sari := r.e.sari;
v.m.su := r.e.su;
v.m.mul := '0';
if lddel = 1 then
if r.e.ldbp1 = '1' then
ex_op1 := r.x.data(0);
ex_sari := r.x.data(0)(31) and r.e.ctrl.inst(19) and r.e.ctrl.inst(20);
end if;
if r.e.ldbp2 = '1' then
ex_op2 := r.x.data(0);
ex_ymsb := r.x.data(0)(0);
mul_op2 := ex_op2;
ex_shcnt := r.x.data(0)(4 downto 0);
if r.e.invop2 = '1' then
ex_op2 := not ex_op2;
ex_shcnt := not ex_shcnt;
end if;
end if;
end if;
ex_add_res := (ex_op1 & '1') + (ex_op2 & r.e.alucin);
if ex_add_res(2 downto 1) = "00" then
v.m.nalign := '0';
else
v.m.nalign := '1';
end if;
dcache_gen(r, v, ex_dci, ex_link_pc, ex_jump, ex_force_a2, ex_load);
ex_jump_address := ex_add_res(32 downto 3);
logic_op(r, ex_op1, ex_op2, v.x.y, ex_ymsb, ex_logic_res, v.m.y);
ex_shift_res := shift(r, ex_op1, ex_op2, ex_shcnt, ex_sari);
misc_op(r, wpr, ex_op1, ex_op2, xc_df_result, v.x.y, ex_misc_res, ex_edata);
ex_add_res(3):= ex_add_res(3) or ex_force_a2;
alu_select(r, ex_add_res, ex_op1, ex_op2, ex_shift_res, ex_logic_res, ex_misc_res, ex_result, me_icc, v.m.icc, v.m.divz);
dbg_cache(holdn, dbgi, r, dsur, ex_result, ex_dci, ex_result2, v.m.dci);
fpstdata(r, ex_edata, ex_result2, fpo.data, ex_edata2, v.m.result);
cwp_ex(r, v.m.wcwp);
v.m.ctrl.annul := v.m.ctrl.annul or v.x.annul_all;
v.m.ctrl.wicc := r.e.ctrl.wicc and not v.x.annul_all;
v.m.mac := r.e.mac;
if (true and (r.x.rstate = dsu2)) then
v.m.ctrl.ld := '1';
end if;
dci.eenaddr <= v.m.dci.enaddr;
dci.eaddress <= ex_add_res(32 downto 1);
dci.edata <= ex_edata2;
-----------------------------------------------------------------------
-- REGFILE STAGE
-----------------------------------------------------------------------
v.e.ctrl := r.a.ctrl;
v.e.jmpl := r.a.jmpl;
v.e.ctrl.annul := r.a.ctrl.annul or v.x.annul_all;
v.e.ctrl.rett := r.a.ctrl.rett and not r.a.ctrl.annul;
v.e.ctrl.wreg := r.a.ctrl.wreg and not v.x.annul_all;
v.e.su := r.a.su;
v.e.et := r.a.et;
v.e.ctrl.wicc := r.a.ctrl.wicc and not v.x.annul_all;
exception_detect(r, wpr, dbgi, r.a.ctrl.trap, r.a.ctrl.tt, v.e.ctrl.trap, v.e.ctrl.tt);
op_mux(r, rfo.data1, v.m.result, v.x.result, xc_df_result, "00000000000000000000000000000000", r.a.rsel1, v.e.ldbp1, ra_op1);
op_mux(r, rfo.data2, v.m.result, v.x.result, xc_df_result, r.a.imm, r.a.rsel2, ex_ldbp2, ra_op2);
alu_op(r, ra_op1, ra_op2, v.m.icc, v.m.y(0), ex_ldbp2, v.e.op1, v.e.op2, v.e.aluop, v.e.alusel, v.e.aluadd, v.e.shcnt, v.e.sari, v.e.shleft, v.e.ymsb, v.e.mul, ra_div, v.e.mulstep, v.e.mac, v.e.ldbp2, v.e.invop2);
cin_gen(r, v.m.icc(0), v.e.alucin);
-----------------------------------------------------------------------
-- DECODE STAGE
-----------------------------------------------------------------------
de_inst := r.d.inst(conv_integer(r.d.set));
de_icc := r.m.icc;
v.a.cwp := r.d.cwp;
su_et_select(r, v.w.s.ps, v.w.s.s, v.w.s.et, v.a.su, v.a.et);
wicc_y_gen(de_inst, v.a.ctrl.wicc, v.a.ctrl.wy);
cwp_ctrl(r, v.w.s.wim, de_inst, de_cwp, v.a.wovf, v.a.wunf, de_wcwp);
rs1_gen(r, de_inst, v.a.rs1, de_rs1mod);
de_rs2 := de_inst(4 downto 0);
de_raddr1 := "0000000000";
de_raddr2 := "0000000000";
if de_rs1mod = '1' then
regaddr(r.d.cwp, de_inst(29 downto 26) & v.a.rs1(0), de_raddr1(7 downto 0));
else
regaddr(r.d.cwp, de_inst(18 downto 15) & v.a.rs1(0), de_raddr1(7 downto 0));
end if;
regaddr(r.d.cwp, de_rs2, de_raddr2(7 downto 0));
v.a.rfa1 := de_raddr1(7 downto 0);
v.a.rfa2 := de_raddr2(7 downto 0);
rd_gen(r, de_inst, v.a.ctrl.wreg, v.a.ctrl.ld, de_rd);
regaddr(de_cwp, de_rd, v.a.ctrl.rd);
fpbranch(de_inst, fpo.cc, de_fbranch);
fpbranch(de_inst, cpo.cc, de_cbranch);
v.a.imm := imm_data(r, de_inst);
lock_gen(r, de_rs2, de_rd, v.a.rfa1, v.a.rfa2, v.a.ctrl.rd, de_inst, fpo.ldlock, v.e.mul, ra_div, v.a.ldcheck1, v.a.ldcheck2, de_ldlock, v.a.ldchkra, v.a.ldchkex);
ic_ctrl(r, de_inst, v.x.annul_all, de_ldlock, branch_true(de_icc, de_inst), de_fbranch, de_cbranch, fpo.ccv, cpo.ccv, v.d.cnt, v.d.pc, de_branch, v.a.ctrl.annul, v.d.annul, v.a.jmpl, de_inull, v.d.pv, v.a.ctrl.pv, de_hold_pc, v.a.ticc, v.a.ctrl.rett, v.a.mulstart, v.a.divstart);
cwp_gen(r, v, v.a.ctrl.annul, de_wcwp, de_cwp, v.d.cwp);
v.d.inull := ra_inull_gen(r, v);
op_find(r, v.a.ldchkra, v.a.ldchkex, v.a.rs1, v.a.rfa1, false, v.a.rfe1, v.a.rsel1, v.a.ldcheck1);
op_find(r, v.a.ldchkra, v.a.ldchkex, de_rs2, v.a.rfa2, imm_select(de_inst), v.a.rfe2, v.a.rsel2, v.a.ldcheck2);
de_branch_address := branch_address(de_inst, r.d.pc);
v.a.ctrl.annul := v.a.ctrl.annul or v.x.annul_all;
v.a.ctrl.wicc := v.a.ctrl.wicc and not v.a.ctrl.annul;
v.a.ctrl.wreg := v.a.ctrl.wreg and not v.a.ctrl.annul;
v.a.ctrl.rett := v.a.ctrl.rett and not v.a.ctrl.annul;
v.a.ctrl.wy := v.a.ctrl.wy and not v.a.ctrl.annul;
v.a.ctrl.trap := r.d.mexc;
v.a.ctrl.tt := "000000";
v.a.ctrl.inst := de_inst;
v.a.ctrl.pc := r.d.pc;
v.a.ctrl.cnt := r.d.cnt;
v.a.step := r.d.step;
if holdn = '0' then
de_raddr1(7 downto 0) := r.a.rfa1;
de_raddr2(7 downto 0) := r.a.rfa2;
de_ren1 := r.a.rfe1;
de_ren2 := r.a.rfe2;
else
de_ren1 := v.a.rfe1;
de_ren2 := v.a.rfe2;
end if;
if ((dbgi.denable and not dbgi.dwrite) = '1') and (r.x.rstate = dsu2) then
de_raddr1(7 downto 0) := dbgi.daddr(9 downto 2);
de_ren1 := '1';
end if;
v.d.step := dbgi.step and not r.d.annul;
rfi.raddr1 <= de_raddr1;
rfi.raddr2 <= de_raddr2;
rfi.ren1 <= de_ren1 and not dco.scanen;
rfi.ren2 <= de_ren2 and not dco.scanen;
rfi.diag <= dco.testen & "000";
ici.inull <= de_inull;
ici.flush <= me_iflush;
if (xc_rstn = '0') then
v.d.cnt := "00";
end if;
-----------------------------------------------------------------------
-- FETCH STAGE
-----------------------------------------------------------------------
npc := r.f.pc;
if (xc_rstn = '0') then
v.f.pc := "000000000000000000000000000000";
v.f.branch := '0';
v.f.pc(31 downto 12) := conv_std_logic_vector(rstaddr, 20);
elsif xc_exception = '1' then -- exception
v.f.branch := '1';
v.f.pc := xc_trap_address;
npc := v.f.pc;
elsif de_hold_pc = '1' then
v.f.pc := r.f.pc;
v.f.branch := r.f.branch;
if ex_jump = '1' then
v.f.pc := ex_jump_address;
v.f.branch := '1';
npc := v.f.pc;
end if;
elsif ex_jump = '1' then
v.f.pc := ex_jump_address;
v.f.branch := '1';
npc := v.f.pc;
elsif de_branch = '1' then
v.f.pc := branch_address(de_inst, r.d.pc);
v.f.branch := '1';
npc := v.f.pc;
else
v.f.branch := '0';
v.f.pc(31 downto 2) := r.f.pc(31 downto 2) + 1;-- Address incrementer
npc := v.f.pc;
end if;
ici.dpc <= r.d.pc(31 downto 2) & "00";
ici.fpc <= r.f.pc(31 downto 2) & "00";
ici.rpc <= npc(31 downto 2) & "00";
ici.fbranch <= r.f.branch;
ici.rbranch <= v.f.branch;
ici.su <= v.a.su;
ici.fline <= "00000000000000000000000000000";
ici.flushl <= '0';
if (ico.mds and de_hold_pc) = '0' then
v.d.inst(0) := ico.data(0);-- latch instruction
v.d.inst(1) := ico.data(1);-- latch instruction
v.d.set := ico.set(0 downto 0);-- latch instruction
v.d.mexc := ico.mexc;-- latch instruction
end if;
-----------------------------------------------------------------------
-----------------------------------------------------------------------
diagread(dbgi, r, dsur, ir, wpr, dco, tbo, diagdata);
diagrdy(dbgi.denable, dsur, r.m.dci, dco.mds, ico, vdsu.crdy);
-----------------------------------------------------------------------
-- OUTPUTS
-----------------------------------------------------------------------
rin <= v;
wprin <= vwpr;
dsuin <= vdsu;
irin <= vir;
muli.start <= r.a.mulstart and not r.a.ctrl.annul;
muli.signed <= r.e.ctrl.inst(19);
muli.op1 <= (ex_op1(31) and r.e.ctrl.inst(19)) & ex_op1;
muli.op2 <= (mul_op2(31) and r.e.ctrl.inst(19)) & mul_op2;
muli.mac <= r.e.ctrl.inst(24);
muli.acc(39 downto 32) <= r.x.y(7 downto 0);
muli.acc(31 downto 0) <= r.w.s.asr18;
muli.flush <= r.x.annul_all;
divi.start <= r.a.divstart and not r.a.ctrl.annul;
divi.signed <= r.e.ctrl.inst(19);
divi.flush <= r.x.annul_all;
divi.op1 <= (ex_op1(31) and r.e.ctrl.inst(19)) & ex_op1;
divi.op2 <= (ex_op2(31) and r.e.ctrl.inst(19)) & ex_op2;
if (r.a.divstart and not r.a.ctrl.annul) = '1' then
dsign := r.a.ctrl.inst(19);
else
dsign := r.e.ctrl.inst(19);
end if;
divi.y <= (r.m.y(31) and dsign) & r.m.y;
rpin <= vp;
dbgo.dsu <= '1';
dbgo.dsumode <= r.x.debug;
dbgo.crdy <= dsur.crdy(2);
dbgo.data <= diagdata;
tbi <= tbufi;
dbgo.error <= dummy and not r.x.nerror;
-- pragma translate_off
if FPEN then
-- pragma translate_on
vfpi.flush := v.x.annul_all;
vfpi.exack := xc_fpexack;
vfpi.a_rs1 := r.a.rs1;
vfpi.d.inst := de_inst;
vfpi.d.cnt := r.d.cnt;
vfpi.d.annul := v.x.annul_all or r.d.annul;
vfpi.d.trap := r.d.mexc;
vfpi.d.pc(1 downto 0) := (others => '0');
vfpi.d.pc(31 downto 2) := r.d.pc(31 downto 2);
vfpi.d.pv := r.d.pv;
vfpi.a.pc(1 downto 0) := (others => '0');
vfpi.a.pc(31 downto 2) := r.a.ctrl.pc(31 downto 2);
vfpi.a.inst := r.a.ctrl.inst;
vfpi.a.cnt := r.a.ctrl.cnt;
vfpi.a.trap := r.a.ctrl.trap;
vfpi.a.annul := r.a.ctrl.annul;
vfpi.a.pv := r.a.ctrl.pv;
vfpi.e.pc(1 downto 0) := (others => '0');
vfpi.e.pc(31 downto 2) := r.e.ctrl.pc(31 downto 2);
vfpi.e.inst := r.e.ctrl.inst;
vfpi.e.cnt := r.e.ctrl.cnt;
vfpi.e.trap := r.e.ctrl.trap;
vfpi.e.annul := r.e.ctrl.annul;
vfpi.e.pv := r.e.ctrl.pv;
vfpi.m.pc(1 downto 0) := (others => '0');
vfpi.m.pc(31 downto 2) := r.m.ctrl.pc(31 downto 2);
vfpi.m.inst := r.m.ctrl.inst;
vfpi.m.cnt := r.m.ctrl.cnt;
vfpi.m.trap := r.m.ctrl.trap;
vfpi.m.annul := r.m.ctrl.annul;
vfpi.m.pv := r.m.ctrl.pv;
vfpi.x.pc(1 downto 0) := (others => '0');
vfpi.x.pc(31 downto 2) := r.x.ctrl.pc(31 downto 2);
vfpi.x.inst := r.x.ctrl.inst;
vfpi.x.cnt := r.x.ctrl.cnt;
vfpi.x.trap := xc_trap;
vfpi.x.annul := r.x.ctrl.annul;
vfpi.x.pv := r.x.ctrl.pv;
vfpi.lddata := xc_df_result;--xc_result;
if r.x.rstate = dsu2 then
vfpi.dbg.enable := dbgi.denable;
else
vfpi.dbg.enable := '0';
end if;
vfpi.dbg.write := fpcdbgwr;
vfpi.dbg.fsr := dbgi.daddr(22);-- IU reg access
vfpi.dbg.addr := dbgi.daddr(6 downto 2);
vfpi.dbg.data := dbgi.ddata;
fpi <= vfpi;
cpi <= vfpi;-- dummy, just to kill some warnings ...
-- pragma translate_off
end if;
-- pragma translate_on
-- Assignments to be moved with variables
-- These assignments must be moved to process COMB/
V_A_ET_shadow <= V.A.ET;
EX_ADD_RES32DOWNTO34DOWNTO3_shadow <= EX_ADD_RES ( 32 DOWNTO 3 )( 4 DOWNTO 3 );
ICNT_shadow <= ICNT;
EX_OP1_shadow <= EX_OP1;
V_M_CTRL_PC_shadow <= V.M.CTRL.PC;
V_E_CTRL_PC3DOWNTO2_shadow <= V.E.CTRL.PC( 3 DOWNTO 2 );
DE_REN1_shadow <= DE_REN1;
DE_INST_shadow <= DE_INST;
V_A_CTRL_CNT_shadow <= V.A.CTRL.CNT;
V_F_PC3DOWNTO2_shadow <= V.F.PC( 3 DOWNTO 2 );
V_W_S_TT_shadow <= V.W.S.TT;
V_X_RESULT6DOWNTO0_shadow <= V.X.RESULT ( 6 DOWNTO 0 );
EX_JUMP_ADDRESS3DOWNTO2_shadow <= EX_JUMP_ADDRESS( 3 DOWNTO 2 );
V_E_ALUCIN_shadow <= V.E.ALUCIN;
V_D_PC3DOWNTO2_shadow <= V.D.PC( 3 DOWNTO 2 );
V_A_CTRL_PV_shadow <= V.A.CTRL.PV;
V_E_CTRL_shadow <= V.E.CTRL;
V_M_CTRL_shadow <= V.M.CTRL;
V_M_RESULT1DOWNTO0_shadow <= V.M.RESULT ( 1 DOWNTO 0 );
EX_SHCNT_shadow <= EX_SHCNT;
V_M_DCI_SIZE_shadow <= V.M.DCI.SIZE;
V_X_CTRL_ANNUL_shadow <= V.X.CTRL.ANNUL;
V_X_MEXC_shadow <= V.X.MEXC;
TBUFCNTX_shadow <= TBUFCNTX;
V_A_CTRL_WY_shadow <= V.A.CTRL.WY;
NPC_shadow <= NPC;
V_M_CTRL_TT3DOWNTO0_shadow <= V.M.CTRL.TT( 3 DOWNTO 0 );
V_A_MULSTART_shadow <= V.A.MULSTART;
XC_VECTT3DOWNTO0_shadow <= XC_VECTT( 3 DOWNTO 0 );
V_E_CTRL_TT_shadow <= V.E.CTRL.TT;
DSIGN_shadow <= DSIGN;
V_E_CTRL_ANNUL_shadow <= V.E.CTRL.ANNUL;
EX_JUMP_ADDRESS_shadow <= EX_JUMP_ADDRESS;
V_A_CTRL_PC31DOWNTO12_shadow <= V.A.CTRL.PC( 31 DOWNTO 12 );
V_A_RFE1_shadow <= V.A.RFE1;
V_W_WA_shadow <= V.W.WA;
V_X_ANNUL_ALL_shadow <= V.X.ANNUL_ALL;
EX_YMSB_shadow <= EX_YMSB;
EX_ADD_RES_shadow <= EX_ADD_RES;
VIR_ADDR_shadow <= VIR.ADDR;
EX_JUMP_ADDRESS31DOWNTO12_shadow <= EX_JUMP_ADDRESS( 31 DOWNTO 12 );
V_W_S_CWP_shadow <= V.W.S.CWP;
V_D_INST0_shadow <= V.D.INST ( 0 );
V_A_CTRL_ANNUL_shadow <= V.A.CTRL.ANNUL;
V_X_DATA1_shadow <= V.X.DATA ( 1 );
VP_PWD_shadow <= VP.PWD;
V_M_CTRL_RD6DOWNTO0_shadow <= V.M.CTRL.RD( 6 DOWNTO 0 );
V_X_DATA00_shadow <= V.X.DATA ( 0 )( 0 );
V_M_CTRL_RETT_shadow <= V.M.CTRL.RETT;
V_X_CTRL_RETT_shadow <= V.X.CTRL.RETT;
V_X_CTRL_PC31DOWNTO12_shadow <= V.X.CTRL.PC( 31 DOWNTO 12 );
V_W_S_PS_shadow <= V.W.S.PS;
V_X_CTRL_TT_shadow <= V.X.CTRL.TT;
V_D_STEP_shadow <= V.D.STEP;
V_X_CTRL_WICC_shadow <= V.X.CTRL.WICC;
VIR_ADDR31DOWNTO2_shadow <= VIR.ADDR( 31 DOWNTO 2 );
V_M_CTRL_RD7DOWNTO0_shadow <= V.M.CTRL.RD ( 7 DOWNTO 0 );
V_X_RESULT_shadow <= V.X.RESULT;
V_D_CNT_shadow <= V.D.CNT;
XC_VECTT_shadow <= XC_VECTT;
EX_ADD_RES32DOWNTO3_shadow <= EX_ADD_RES ( 32 DOWNTO 3 );
V_W_S_EF_shadow <= V.W.S.EF;
V_A_CTRL_PC31DOWNTO2_shadow <= V.A.CTRL.PC( 31 DOWNTO 2 );
V_X_DATA04DOWNTO0_shadow <= V.X.DATA ( 0 )( 4 DOWNTO 0 );
V_X_DCI_SIGNED_shadow <= V.X.DCI.SIGNED;
V_M_NALIGN_shadow <= V.M.NALIGN;
XC_WREG_shadow <= XC_WREG;
V_A_RFA2_shadow <= V.A.RFA2;
V_E_CTRL_PC31DOWNTO12_shadow <= V.E.CTRL.PC( 31 DOWNTO 12 );
EX_ADD_RES32DOWNTO332DOWNTO13_shadow <= EX_ADD_RES ( 32 DOWNTO 3 )( 32 DOWNTO 13 );
EX_OP231_shadow <= EX_OP2( 31 );
XC_TRAP_ADDRESS31DOWNTO4_shadow <= XC_TRAP_ADDRESS( 31 DOWNTO 4 );
V_X_ICC_shadow <= V.X.ICC;
V_A_SU_shadow <= V.A.SU;
V_E_OP2_shadow <= V.E.OP2;
EX_FORCE_A2_shadow <= EX_FORCE_A2;
V_E_CTRL_PC31DOWNTO2_shadow <= V.E.CTRL.PC( 31 DOWNTO 2 );
V_E_CTRL_PC31DOWNTO4_shadow <= V.E.CTRL.PC( 31 DOWNTO 4 );
V_E_OP131_shadow <= V.E.OP1( 31 );
V_X_DCI_shadow <= V.X.DCI;
V_E_CTRL_WICC_shadow <= V.E.CTRL.WICC;
EX_OP13_shadow <= EX_OP1( 3 );
V_F_PC31DOWNTO12_shadow <= V.F.PC( 31 DOWNTO 12 );
V_E_CTRL_INST_shadow <= V.E.CTRL.INST;
V_E_CTRL_LD_shadow <= V.E.CTRL.LD;
V_M_SU_shadow <= V.M.SU;
V_E_SARI_shadow <= V.E.SARI;
V_E_ET_shadow <= V.E.ET;
V_M_CTRL_PV_shadow <= V.M.CTRL.PV;
VDSU_CRDY2_shadow <= VDSU.CRDY ( 2 );
MUL_OP2_shadow <= MUL_OP2;
XC_EXCEPTION_shadow <= XC_EXCEPTION;
V_E_OP1_shadow <= V.E.OP1;
VP_ERROR_shadow <= VP.ERROR;
V_M_DCI_SIGNED_shadow <= V.M.DCI.SIGNED;
V_D_PC31DOWNTO12_shadow <= V.D.PC( 31 DOWNTO 12 );
MUL_OP231_shadow <= MUL_OP2 ( 31 );
XC_TRAP_ADDRESS31DOWNTO2_shadow <= XC_TRAP_ADDRESS( 31 DOWNTO 2 );
V_M_CTRL_PC3DOWNTO2_shadow <= V.M.CTRL.PC( 3 DOWNTO 2 );
V_M_DCI_shadow <= V.M.DCI;
EX_OP23_shadow <= EX_OP2( 3 );
V_X_CTRL_RD6DOWNTO0_shadow <= V.X.CTRL.RD( 6 DOWNTO 0 );
V_X_CTRL_TRAP_shadow <= V.X.CTRL.TRAP;
V_A_DIVSTART_shadow <= V.A.DIVSTART;
V_X_RESULT6DOWNTO03DOWNTO0_shadow <= V.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 );
VDSU_TT_shadow <= VDSU.TT;
EX_ADD_RES32DOWNTO332DOWNTO5_shadow <= EX_ADD_RES ( 32 DOWNTO 3 )( 32 DOWNTO 5 );
V_X_CTRL_CNT_shadow <= V.X.CTRL.CNT;
V_E_YMSB_shadow <= V.E.YMSB;
EX_ADD_RES32DOWNTO330DOWNTO11_shadow <= EX_ADD_RES ( 32 DOWNTO 3 )( 30 DOWNTO 11 );
V_A_RFE2_shadow <= V.A.RFE2;
V_E_OP13_shadow <= V.E.OP1( 3 );
V_A_CWP_shadow <= V.A.CWP;
ME_SIZE_shadow <= ME_SIZE;
V_X_MAC_shadow <= V.X.MAC;
V_M_CTRL_INST_shadow <= V.M.CTRL.INST;
VIR_ADDR31DOWNTO4_shadow <= VIR.ADDR( 31 DOWNTO 4 );
V_A_CTRL_INST20_shadow <= V.A.CTRL.INST( 20 );
DE_REN2_shadow <= DE_REN2;
V_E_CTRL_PV_shadow <= V.E.CTRL.PV;
V_E_MAC_shadow <= V.E.MAC;
V_X_CTRL_TT3DOWNTO0_shadow <= V.X.CTRL.TT( 3 DOWNTO 0 );
EX_ADD_RES3_shadow <= EX_ADD_RES ( 3 );
V_X_CTRL_INST_shadow <= V.X.CTRL.INST;
V_M_CTRL_PC31DOWNTO2_shadow <= V.M.CTRL.PC( 31 DOWNTO 2 );
V_W_S_ET_shadow <= V.W.S.ET;
V_M_CTRL_CNT_shadow <= V.M.CTRL.CNT;
V_M_CTRL_ANNUL_shadow <= V.M.CTRL.ANNUL;
DE_INST19_shadow <= DE_INST( 19 );
XC_HALT_shadow <= XC_HALT;
V_E_OP231_shadow <= V.E.OP2( 31 );
V_A_CTRL_PC3DOWNTO2_shadow <= V.A.CTRL.PC( 3 DOWNTO 2 );
VIR_ADDR31DOWNTO12_shadow <= VIR.ADDR( 31 DOWNTO 12 );
V_M_CTRL_WICC_shadow <= V.M.CTRL.WICC;
V_M_CTRL_WREG_shadow <= V.M.CTRL.WREG;
V_W_S_S_shadow <= V.W.S.S;
V_F_PC31DOWNTO2_shadow <= V.F.PC( 31 DOWNTO 2 );
V_E_CWP_shadow <= V.E.CWP;
V_A_STEP_shadow <= V.A.STEP;
V_A_CTRL_TT3DOWNTO0_shadow <= V.A.CTRL.TT( 3 DOWNTO 0 );
V_A_CTRL_TRAP_shadow <= V.A.CTRL.TRAP;
NPC31DOWNTO2_shadow <= NPC ( 31 DOWNTO 2 );
V_M_CTRL_TRAP_shadow <= V.M.CTRL.TRAP;
V_D_PC31DOWNTO4_shadow <= V.D.PC( 31 DOWNTO 4 );
V_X_INTACK_shadow <= V.X.INTACK;
SIDLE_shadow <= SIDLE;
V_A_CTRL_RETT_shadow <= V.A.CTRL.RETT;
V_X_DATA03_shadow <= V.X.DATA ( 0 )( 3 );
V_A_CTRL_INST19_shadow <= V.A.CTRL.INST( 19 );
V_W_S_SVT_shadow <= V.W.S.SVT;
V_A_CTRL_PC31DOWNTO4_shadow <= V.A.CTRL.PC( 31 DOWNTO 4 );
V_X_LADDR_shadow <= V.X.LADDR;
V_W_S_DWT_shadow <= V.W.S.DWT;
EX_JUMP_ADDRESS31DOWNTO2_shadow <= EX_JUMP_ADDRESS( 31 DOWNTO 2 );
V_W_S_TBA_shadow <= V.W.S.TBA;
XC_WADDR6DOWNTO0_shadow <= XC_WADDR ( 6 DOWNTO 0 );
V_M_MUL_shadow <= V.M.MUL;
V_E_SU_shadow <= V.E.SU;
V_M_Y31_shadow <= V.M.Y ( 31 );
V_E_OP23_shadow <= V.E.OP2( 3 );
V_M_CTRL_PC31DOWNTO4_shadow <= V.M.CTRL.PC( 31 DOWNTO 4 );
DE_RADDR17DOWNTO0_shadow <= DE_RADDR1 ( 7 DOWNTO 0 );
V_X_CTRL_PC31DOWNTO2_shadow <= V.X.CTRL.PC( 31 DOWNTO 2 );
V_E_CTRL_TRAP_shadow <= V.E.CTRL.TRAP;
V_X_DEBUG_shadow <= V.X.DEBUG;
V_M_DCI_LOCK_shadow <= V.M.DCI.LOCK;
V_X_CTRL_PC3DOWNTO2_shadow <= V.X.CTRL.PC( 3 DOWNTO 2 );
V_X_CTRL_WREG_shadow <= V.X.CTRL.WREG;
V_E_CTRL_INST24_shadow <= V.E.CTRL.INST( 24 );
V_D_MEXC_shadow <= V.D.MEXC;
V_W_RESULT_shadow <= V.W.RESULT;
VFPI_DBG_ENABLE_shadow <= VFPI.DBG.ENABLE;
EX_OP131_shadow <= EX_OP1 ( 31 );
V_D_INST1_shadow <= V.D.INST ( 1 );
V_W_EXCEPT_shadow <= V.W.EXCEPT;
V_E_CTRL_TT3DOWNTO0_shadow <= V.E.CTRL.TT( 3 DOWNTO 0 );
ME_LADDR_shadow <= ME_LADDR;
V_X_CTRL_PC31DOWNTO4_shadow <= V.X.CTRL.PC( 31 DOWNTO 4 );
V_E_CTRL_RETT_shadow <= V.E.CTRL.RETT;
XC_WADDR7DOWNTO0_shadow <= XC_WADDR ( 7 DOWNTO 0 );
V_X_CTRL_PV_shadow <= V.X.CTRL.PV;
V_E_CTRL_RD6DOWNTO0_shadow <= V.E.CTRL.RD( 6 DOWNTO 0 );
V_M_MAC_shadow <= V.M.MAC;
V_D_SET_shadow <= V.D.SET;
VIR_ADDR3DOWNTO2_shadow <= VIR.ADDR( 3 DOWNTO 2 );
V_D_CWP_shadow <= V.D.CWP;
DE_INST20_shadow <= DE_INST( 20 );
V_D_ANNUL_shadow <= V.D.ANNUL;
EX_OP2_shadow <= EX_OP2;
EX_SARI_shadow <= EX_SARI;
V_D_PC31DOWNTO2_shadow <= V.D.PC( 31 DOWNTO 2 );
V_X_DCI_SIZE_shadow <= V.X.DCI.SIZE;
V_M_Y_shadow <= V.M.Y;
V_X_CTRL_PC_shadow <= V.X.CTRL.PC;
V_X_SET_shadow <= V.X.SET;
V_A_CTRL_PC_shadow <= V.A.CTRL.PC;
V_A_JMPL_shadow <= V.A.JMPL;
V_E_CTRL_PC_shadow <= V.E.CTRL.PC;
V_E_CTRL_INST20_shadow <= V.E.CTRL.INST( 20 );
V_E_CTRL_WREG_shadow <= V.E.CTRL.WREG;
V_A_CTRL_WREG_shadow <= V.A.CTRL.WREG;
V_A_CTRL_shadow <= V.A.CTRL;
V_A_CTRL_RD6DOWNTO0_shadow <= V.A.CTRL.RD( 6 DOWNTO 0 );
V_X_DATA0_shadow <= V.X.DATA ( 0 );
V_E_CTRL_INST19_shadow <= V.E.CTRL.INST( 19 );
ME_SIGNED_shadow <= ME_SIGNED;
V_W_WREG_shadow <= V.W.WREG;
V_D_PC_shadow <= V.D.PC;
VFPI_D_ANNUL_shadow <= VFPI.D.ANNUL;
DE_RADDR27DOWNTO0_shadow <= DE_RADDR2 ( 7 DOWNTO 0 );
V_E_CTRL_CNT_shadow <= V.E.CTRL.CNT;
V_F_PC_shadow <= V.F.PC;
V_X_DATA031_shadow <= V.X.DATA ( 0 )( 31 );
V_M_CTRL_PC31DOWNTO12_shadow <= V.M.CTRL.PC( 31 DOWNTO 12 );
V_X_CTRL_RD7DOWNTO0_shadow <= V.X.CTRL.RD ( 7 DOWNTO 0 );
V_M_CTRL_TT_shadow <= V.M.CTRL.TT;
V_X_CTRL_shadow <= V.X.CTRL;
V_A_CTRL_INST24_shadow <= V.A.CTRL.INST( 24 );
XC_TRAP_ADDRESS3DOWNTO2_shadow <= XC_TRAP_ADDRESS( 3 DOWNTO 2 );
V_X_NERROR_shadow <= V.X.NERROR;
V_F_PC31DOWNTO4_shadow <= V.F.PC( 31 DOWNTO 4 );
V_W_S_TT3DOWNTO0_shadow <= V.W.S.TT( 3 DOWNTO 0 );
EX_JUMP_ADDRESS31DOWNTO4_shadow <= EX_JUMP_ADDRESS( 31 DOWNTO 4 );
EX_ADD_RES32DOWNTO332DOWNTO3_shadow <= EX_ADD_RES ( 32 DOWNTO 3 )( 32 DOWNTO 3 );
V_F_BRANCH_shadow <= V.F.BRANCH;
V_A_CTRL_WICC_shadow <= V.A.CTRL.WICC;
V_A_CTRL_LD_shadow <= V.A.CTRL.LD;
V_A_CTRL_TT_shadow <= V.A.CTRL.TT;
V_M_CTRL_LD_shadow <= V.M.CTRL.LD;
V_E_SHCNT_shadow <= V.E.SHCNT;
XC_TRAP_ADDRESS31DOWNTO12_shadow <= XC_TRAP_ADDRESS( 31 DOWNTO 12 );
V_A_CTRL_INST_shadow <= V.A.CTRL.INST;
V_A_CTRL_RD7DOWNTO0_shadow <= V.A.CTRL.RD ( 7 DOWNTO 0 );
VIR_PWD_shadow <= VIR.PWD;
XC_RESULT_shadow <= XC_RESULT;
V_A_RFA1_shadow <= V.A.RFA1;
V_E_JMPL_shadow <= V.E.JMPL;
V_E_CTRL_RD7DOWNTO0_shadow <= V.E.CTRL.RD ( 7 DOWNTO 0 );
ME_ICC_shadow <= ME_ICC;
DE_INST24_shadow <= DE_INST( 24 );
XC_TRAP_shadow <= XC_TRAP;
VDSU_TBUFCNT_shadow <= VDSU.TBUFCNT;
XC_TRAP_ADDRESS_shadow <= XC_TRAP_ADDRESS;
end process;
dfp_delay : process(clk) begin
if(clk'event and clk = '1')then
RPIN_ERROR_intermed_1 <= RPIN.ERROR;
VP_ERROR_shadow_intermed_1 <= VP_ERROR_shadow;
V_W_S_S_shadow_intermed_1 <= V_W_S_S_shadow;
RIN_W_S_S_intermed_1 <= RIN.W.S.S;
V_W_S_S_shadow_intermed_1 <= V_W_S_S_shadow;
V_W_S_S_shadow_intermed_2 <= V_W_S_S_shadow_intermed_1;
V_W_S_PS_shadow_intermed_1 <= V_W_S_PS_shadow;
RIN_W_S_PS_intermed_1 <= RIN.W.S.PS;
R_W_S_S_intermed_1 <= R.W.S.S;
RIN_W_S_S_intermed_1 <= RIN.W.S.S;
RIN_W_S_S_intermed_2 <= RIN_W_S_S_intermed_1;
R_X_RESULT6DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 );
R_X_RESULT6DOWNTO0_intermed_2 <= R_X_RESULT6DOWNTO0_intermed_1;
V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow;
V_X_RESULT6DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO0_shadow_intermed_1;
V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow;
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 );
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 );
RIN_X_RESULT6DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO0_intermed_1;
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
V_X_DATA0_shadow_intermed_2 <= V_X_DATA0_shadow_intermed_1;
R_X_DATA0_intermed_1 <= R.X.DATA( 0 );
R_X_DATA0_intermed_2 <= R_X_DATA0_intermed_1;
DCO_DATA0_intermed_1 <= DCO.DATA ( 0 );
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA ( 0 );
RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 );
RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC ( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
R_X_CTRL_PC31DOWNTO2_intermed_2 <= R_X_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC ( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
V_D_PC31DOWNTO2_shadow_intermed_6 <= V_D_PC31DOWNTO2_shadow_intermed_5;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_D_PC31DOWNTO2_intermed_6 <= RIN_D_PC31DOWNTO2_intermed_5;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC ( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC ( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC ( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_D_PC31DOWNTO2_intermed_5 <= R_D_PC31DOWNTO2_intermed_4;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC ( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
V_X_ANNUL_ALL_shadow_intermed_2 <= V_X_ANNUL_ALL_shadow_intermed_1;
V_X_ANNUL_ALL_shadow_intermed_3 <= V_X_ANNUL_ALL_shadow_intermed_2;
V_X_ANNUL_ALL_shadow_intermed_4 <= V_X_ANNUL_ALL_shadow_intermed_3;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2;
RIN_A_CTRL_ANNUL_intermed_4 <= RIN_A_CTRL_ANNUL_intermed_3;
RIN_A_CTRL_ANNUL_intermed_5 <= RIN_A_CTRL_ANNUL_intermed_4;
R_M_CTRL_WREG_intermed_1 <= R.M.CTRL.WREG;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1;
R_A_CTRL_ANNUL_intermed_3 <= R_A_CTRL_ANNUL_intermed_2;
R_A_CTRL_ANNUL_intermed_4 <= R_A_CTRL_ANNUL_intermed_3;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
RIN_X_ANNUL_ALL_intermed_3 <= RIN_X_ANNUL_ALL_intermed_2;
RIN_X_ANNUL_ALL_intermed_4 <= RIN_X_ANNUL_ALL_intermed_3;
RIN_X_ANNUL_ALL_intermed_5 <= RIN_X_ANNUL_ALL_intermed_4;
V_M_CTRL_WREG_shadow_intermed_1 <= V_M_CTRL_WREG_shadow;
V_M_CTRL_WREG_shadow_intermed_2 <= V_M_CTRL_WREG_shadow_intermed_1;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
R_X_ANNUL_ALL_intermed_2 <= R_X_ANNUL_ALL_intermed_1;
R_X_ANNUL_ALL_intermed_3 <= R_X_ANNUL_ALL_intermed_2;
R_X_ANNUL_ALL_intermed_4 <= R_X_ANNUL_ALL_intermed_3;
V_X_CTRL_WREG_shadow_intermed_1 <= V_X_CTRL_WREG_shadow;
R_E_CTRL_WREG_intermed_1 <= R.E.CTRL.WREG;
R_E_CTRL_WREG_intermed_2 <= R_E_CTRL_WREG_intermed_1;
RIN_X_CTRL_WREG_intermed_1 <= RIN.X.CTRL.WREG;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_3 <= V_A_CTRL_ANNUL_shadow_intermed_2;
V_A_CTRL_ANNUL_shadow_intermed_4 <= V_A_CTRL_ANNUL_shadow_intermed_3;
RIN_E_CTRL_WREG_intermed_1 <= RIN.E.CTRL.WREG;
RIN_E_CTRL_WREG_intermed_2 <= RIN_E_CTRL_WREG_intermed_1;
RIN_E_CTRL_WREG_intermed_3 <= RIN_E_CTRL_WREG_intermed_2;
RIN_M_CTRL_WREG_intermed_1 <= RIN.M.CTRL.WREG;
RIN_M_CTRL_WREG_intermed_2 <= RIN_M_CTRL_WREG_intermed_1;
V_E_CTRL_WREG_shadow_intermed_1 <= V_E_CTRL_WREG_shadow;
V_E_CTRL_WREG_shadow_intermed_2 <= V_E_CTRL_WREG_shadow_intermed_1;
V_E_CTRL_WREG_shadow_intermed_3 <= V_E_CTRL_WREG_shadow_intermed_2;
RIN_A_CTRL_WREG_intermed_1 <= RIN.A.CTRL.WREG;
RIN_A_CTRL_WREG_intermed_2 <= RIN_A_CTRL_WREG_intermed_1;
RIN_A_CTRL_WREG_intermed_3 <= RIN_A_CTRL_WREG_intermed_2;
RIN_A_CTRL_WREG_intermed_4 <= RIN_A_CTRL_WREG_intermed_3;
V_A_CTRL_WREG_shadow_intermed_1 <= V_A_CTRL_WREG_shadow;
V_A_CTRL_WREG_shadow_intermed_2 <= V_A_CTRL_WREG_shadow_intermed_1;
V_A_CTRL_WREG_shadow_intermed_3 <= V_A_CTRL_WREG_shadow_intermed_2;
V_A_CTRL_WREG_shadow_intermed_4 <= V_A_CTRL_WREG_shadow_intermed_3;
R_A_CTRL_WREG_intermed_1 <= R.A.CTRL.WREG;
R_A_CTRL_WREG_intermed_2 <= R_A_CTRL_WREG_intermed_1;
R_A_CTRL_WREG_intermed_3 <= R_A_CTRL_WREG_intermed_2;
RIN_X_INTACK_intermed_1 <= RIN.X.INTACK;
V_X_INTACK_shadow_intermed_1 <= V_X_INTACK_shadow;
V_X_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_X_CTRL_TT3DOWNTO0_shadow;
V_X_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_X_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_X_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_X_CTRL_TT3DOWNTO0_shadow_intermed_2;
R_M_CTRL_TT3DOWNTO0_intermed_1 <= R.M.CTRL.TT( 3 DOWNTO 0 );
R_M_CTRL_TT3DOWNTO0_intermed_2 <= R_M_CTRL_TT3DOWNTO0_intermed_1;
R_M_CTRL_TT3DOWNTO0_intermed_3 <= R_M_CTRL_TT3DOWNTO0_intermed_2;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_M_CTRL_TT3DOWNTO0_shadow;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_M_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_M_CTRL_TT3DOWNTO0_shadow_intermed_2;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_4 <= V_M_CTRL_TT3DOWNTO0_shadow_intermed_3;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_3 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_4 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_3;
R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
R_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= R_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
R_X_RESULT6DOWNTO03DOWNTO0_intermed_3 <= R_X_RESULT6DOWNTO03DOWNTO0_intermed_2;
R_A_CTRL_TT3DOWNTO0_intermed_1 <= R.A.CTRL.TT( 3 DOWNTO 0 );
R_A_CTRL_TT3DOWNTO0_intermed_2 <= R_A_CTRL_TT3DOWNTO0_intermed_1;
R_A_CTRL_TT3DOWNTO0_intermed_3 <= R_A_CTRL_TT3DOWNTO0_intermed_2;
R_A_CTRL_TT3DOWNTO0_intermed_4 <= R_A_CTRL_TT3DOWNTO0_intermed_3;
R_A_CTRL_TT3DOWNTO0_intermed_5 <= R_A_CTRL_TT3DOWNTO0_intermed_4;
RIN_A_CTRL_TT3DOWNTO0_intermed_1 <= RIN.A.CTRL.TT( 3 DOWNTO 0 );
RIN_A_CTRL_TT3DOWNTO0_intermed_2 <= RIN_A_CTRL_TT3DOWNTO0_intermed_1;
RIN_A_CTRL_TT3DOWNTO0_intermed_3 <= RIN_A_CTRL_TT3DOWNTO0_intermed_2;
RIN_A_CTRL_TT3DOWNTO0_intermed_4 <= RIN_A_CTRL_TT3DOWNTO0_intermed_3;
RIN_A_CTRL_TT3DOWNTO0_intermed_5 <= RIN_A_CTRL_TT3DOWNTO0_intermed_4;
RIN_A_CTRL_TT3DOWNTO0_intermed_6 <= RIN_A_CTRL_TT3DOWNTO0_intermed_5;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_3 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_4 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_3;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_A_CTRL_TT3DOWNTO0_shadow;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_2;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_4 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_3;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_5 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_4;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_6 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_5;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_3 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2;
R_W_S_TT3DOWNTO0_intermed_1 <= R.W.S.TT( 3 DOWNTO 0 );
R_W_S_TT3DOWNTO0_intermed_2 <= R_W_S_TT3DOWNTO0_intermed_1;
R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 );
R_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= R_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
R_E_CTRL_TT3DOWNTO0_intermed_1 <= R.E.CTRL.TT( 3 DOWNTO 0 );
R_E_CTRL_TT3DOWNTO0_intermed_2 <= R_E_CTRL_TT3DOWNTO0_intermed_1;
R_E_CTRL_TT3DOWNTO0_intermed_3 <= R_E_CTRL_TT3DOWNTO0_intermed_2;
R_E_CTRL_TT3DOWNTO0_intermed_4 <= R_E_CTRL_TT3DOWNTO0_intermed_3;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_3 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2;
RIN_W_S_TT3DOWNTO0_intermed_1 <= RIN.W.S.TT( 3 DOWNTO 0 );
RIN_W_S_TT3DOWNTO0_intermed_2 <= RIN_W_S_TT3DOWNTO0_intermed_1;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_E_CTRL_TT3DOWNTO0_shadow;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_2;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_4 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_3;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_5 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_4;
RIN_W_S_TT3DOWNTO0_intermed_1 <= RIN.W.S.TT ( 3 DOWNTO 0 );
RIN_M_CTRL_TT3DOWNTO0_intermed_1 <= RIN.M.CTRL.TT( 3 DOWNTO 0 );
RIN_M_CTRL_TT3DOWNTO0_intermed_2 <= RIN_M_CTRL_TT3DOWNTO0_intermed_1;
RIN_M_CTRL_TT3DOWNTO0_intermed_3 <= RIN_M_CTRL_TT3DOWNTO0_intermed_2;
RIN_M_CTRL_TT3DOWNTO0_intermed_4 <= RIN_M_CTRL_TT3DOWNTO0_intermed_3;
RIN_X_CTRL_TT3DOWNTO0_intermed_1 <= RIN.X.CTRL.TT( 3 DOWNTO 0 );
RIN_X_CTRL_TT3DOWNTO0_intermed_2 <= RIN_X_CTRL_TT3DOWNTO0_intermed_1;
RIN_X_CTRL_TT3DOWNTO0_intermed_3 <= RIN_X_CTRL_TT3DOWNTO0_intermed_2;
V_W_S_TT3DOWNTO0_shadow_intermed_1 <= V_W_S_TT3DOWNTO0_shadow;
V_W_S_TT3DOWNTO0_shadow_intermed_2 <= V_W_S_TT3DOWNTO0_shadow_intermed_1;
R_X_CTRL_TT3DOWNTO0_intermed_1 <= R.X.CTRL.TT( 3 DOWNTO 0 );
R_X_CTRL_TT3DOWNTO0_intermed_2 <= R_X_CTRL_TT3DOWNTO0_intermed_1;
RIN_E_CTRL_TT3DOWNTO0_intermed_1 <= RIN.E.CTRL.TT( 3 DOWNTO 0 );
RIN_E_CTRL_TT3DOWNTO0_intermed_2 <= RIN_E_CTRL_TT3DOWNTO0_intermed_1;
RIN_E_CTRL_TT3DOWNTO0_intermed_3 <= RIN_E_CTRL_TT3DOWNTO0_intermed_2;
RIN_E_CTRL_TT3DOWNTO0_intermed_4 <= RIN_E_CTRL_TT3DOWNTO0_intermed_3;
RIN_E_CTRL_TT3DOWNTO0_intermed_5 <= RIN_E_CTRL_TT3DOWNTO0_intermed_4;
V_W_S_TT3DOWNTO0_shadow_intermed_1 <= V_W_S_TT3DOWNTO0_shadow;
XC_VECTT3DOWNTO0_shadow_intermed_1 <= XC_VECTT3DOWNTO0_shadow;
XC_VECTT3DOWNTO0_shadow_intermed_2 <= XC_VECTT3DOWNTO0_shadow_intermed_1;
RIN_X_INTACK_intermed_1 <= RIN.X.INTACK;
V_X_INTACK_shadow_intermed_1 <= V_X_INTACK_shadow;
V_M_RESULT1DOWNTO0_shadow_intermed_1 <= V_M_RESULT1DOWNTO0_shadow;
V_M_RESULT1DOWNTO0_shadow_intermed_2 <= V_M_RESULT1DOWNTO0_shadow_intermed_1;
RIN_M_RESULT1DOWNTO0_intermed_1 <= RIN.M.RESULT ( 1 DOWNTO 0 );
RIN_M_RESULT1DOWNTO0_intermed_1 <= RIN.M.RESULT( 1 DOWNTO 0 );
RIN_M_RESULT1DOWNTO0_intermed_2 <= RIN_M_RESULT1DOWNTO0_intermed_1;
V_M_RESULT1DOWNTO0_shadow_intermed_1 <= V_M_RESULT1DOWNTO0_shadow;
R_M_RESULT1DOWNTO0_intermed_1 <= R.M.RESULT( 1 DOWNTO 0 );
R_M_RESULT1DOWNTO0_intermed_2 <= R_M_RESULT1DOWNTO0_intermed_1;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2;
RIN_E_CTRL_ANNUL_intermed_1 <= RIN.E.CTRL.ANNUL;
RIN_E_CTRL_ANNUL_intermed_2 <= RIN_E_CTRL_ANNUL_intermed_1;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1;
V_M_CTRL_ANNUL_shadow_intermed_1 <= V_M_CTRL_ANNUL_shadow;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
RIN_M_DCI_LOCK_intermed_1 <= RIN.M.DCI.LOCK;
V_E_CTRL_ANNUL_shadow_intermed_1 <= V_E_CTRL_ANNUL_shadow;
V_E_CTRL_ANNUL_shadow_intermed_2 <= V_E_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_3 <= V_A_CTRL_ANNUL_shadow_intermed_2;
RIN_M_CTRL_ANNUL_intermed_1 <= RIN.M.CTRL.ANNUL;
R_E_CTRL_ANNUL_intermed_1 <= R.E.CTRL.ANNUL;
V_M_DCI_LOCK_shadow_intermed_1 <= V_M_DCI_LOCK_shadow;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 ) ( 31 );
DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 );
DCO_DATA031_intermed_2 <= DCO_DATA031_intermed_1;
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
R_X_DATA031_intermed_2 <= R_X_DATA031_intermed_1;
R_X_DATA031_intermed_1 <= R.X.DATA ( 0 )( 31 );
R_X_DATA031_intermed_2 <= R_X_DATA031_intermed_1;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
DE_INST19_shadow_intermed_2 <= DE_INST19_shadow_intermed_1;
DE_INST19_shadow_intermed_3 <= DE_INST19_shadow_intermed_2;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_A_CTRL_INST19_shadow_intermed_3 <= V_A_CTRL_INST19_shadow_intermed_2;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_CTRL_INST19_shadow_intermed_2 <= V_E_CTRL_INST19_shadow_intermed_1;
R_E_CTRL_INST19_intermed_1 <= R.E.CTRL.INST( 19 );
R_E_CTRL_INST19_intermed_2 <= R_E_CTRL_INST19_intermed_1;
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
R_A_CTRL_INST19_intermed_2 <= R_A_CTRL_INST19_intermed_1;
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
RIN_A_CTRL_INST19_intermed_3 <= RIN_A_CTRL_INST19_intermed_2;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST ( 19 );
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST( 19 );
RIN_E_CTRL_INST19_intermed_2 <= RIN_E_CTRL_INST19_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
V_A_CTRL_INST20_shadow_intermed_2 <= V_A_CTRL_INST20_shadow_intermed_1;
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST ( 20 );
RIN_A_CTRL_INST20_intermed_2 <= RIN_A_CTRL_INST20_intermed_1;
RIN_E_CTRL_INST20_intermed_1 <= RIN.E.CTRL.INST ( 20 );
R_A_CTRL_INST20_intermed_1 <= R.A.CTRL.INST ( 20 );
R_E_CTRL_INST20_intermed_1 <= R.E.CTRL.INST( 20 );
R_E_CTRL_INST20_intermed_2 <= R_E_CTRL_INST20_intermed_1;
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST( 20 );
RIN_A_CTRL_INST20_intermed_2 <= RIN_A_CTRL_INST20_intermed_1;
RIN_A_CTRL_INST20_intermed_3 <= RIN_A_CTRL_INST20_intermed_2;
V_E_CTRL_INST20_shadow_intermed_1 <= V_E_CTRL_INST20_shadow;
V_E_CTRL_INST20_shadow_intermed_2 <= V_E_CTRL_INST20_shadow_intermed_1;
V_E_CTRL_INST20_shadow_intermed_1 <= V_E_CTRL_INST20_shadow;
DE_INST20_shadow_intermed_1 <= DE_INST20_shadow;
DE_INST20_shadow_intermed_2 <= DE_INST20_shadow_intermed_1;
DE_INST20_shadow_intermed_3 <= DE_INST20_shadow_intermed_2;
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
V_A_CTRL_INST20_shadow_intermed_2 <= V_A_CTRL_INST20_shadow_intermed_1;
V_A_CTRL_INST20_shadow_intermed_3 <= V_A_CTRL_INST20_shadow_intermed_2;
RIN_E_CTRL_INST20_intermed_1 <= RIN.E.CTRL.INST( 20 );
RIN_E_CTRL_INST20_intermed_2 <= RIN_E_CTRL_INST20_intermed_1;
R_A_CTRL_INST20_intermed_1 <= R.A.CTRL.INST( 20 );
R_A_CTRL_INST20_intermed_2 <= R_A_CTRL_INST20_intermed_1;
RIN_X_DATA00_intermed_1 <= RIN.X.DATA ( 0 )( 0 );
RIN_X_DATA00_intermed_2 <= RIN_X_DATA00_intermed_1;
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
DCO_DATA00_intermed_1 <= DCO.DATA ( 0 )( 0 );
DCO_DATA00_intermed_2 <= DCO_DATA00_intermed_1;
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
V_X_DATA00_shadow_intermed_2 <= V_X_DATA00_shadow_intermed_1;
RIN_X_DATA00_intermed_1 <= RIN.X.DATA ( 0 ) ( 0 );
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
V_X_DATA00_shadow_intermed_2 <= V_X_DATA00_shadow_intermed_1;
R_X_DATA00_intermed_1 <= R.X.DATA ( 0 )( 0 );
R_X_DATA00_intermed_2 <= R_X_DATA00_intermed_1;
RIN_X_DATA00_intermed_1 <= RIN.X.DATA( 0 )( 0 );
RIN_X_DATA00_intermed_2 <= RIN_X_DATA00_intermed_1;
R_X_DATA00_intermed_1 <= R.X.DATA( 0 )( 0 );
R_X_DATA00_intermed_2 <= R_X_DATA00_intermed_1;
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA ( 0 ) ( 4 DOWNTO 0 );
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
V_X_DATA04DOWNTO0_shadow_intermed_2 <= V_X_DATA04DOWNTO0_shadow_intermed_1;
R_X_DATA04DOWNTO0_intermed_1 <= R.X.DATA( 0 )( 4 DOWNTO 0 );
R_X_DATA04DOWNTO0_intermed_2 <= R_X_DATA04DOWNTO0_intermed_1;
R_X_DATA04DOWNTO0_intermed_1 <= R.X.DATA ( 0 )( 4 DOWNTO 0 );
R_X_DATA04DOWNTO0_intermed_2 <= R_X_DATA04DOWNTO0_intermed_1;
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
DCO_DATA04DOWNTO0_intermed_1 <= DCO.DATA ( 0 )( 4 DOWNTO 0 );
DCO_DATA04DOWNTO0_intermed_2 <= DCO_DATA04DOWNTO0_intermed_1;
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA ( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_2 <= RIN_X_DATA04DOWNTO0_intermed_1;
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_2 <= RIN_X_DATA04DOWNTO0_intermed_1;
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
V_X_DATA04DOWNTO0_shadow_intermed_2 <= V_X_DATA04DOWNTO0_shadow_intermed_1;
RIN_A_RFE1_intermed_1 <= RIN.A.RFE1;
V_A_RFE1_shadow_intermed_1 <= V_A_RFE1_shadow;
RIN_A_RFE2_intermed_1 <= RIN.A.RFE2;
V_A_RFE2_shadow_intermed_1 <= V_A_RFE2_shadow;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_3 <= R_M_CTRL_PC31DOWNTO2_intermed_2;
R_M_CTRL_PC31DOWNTO2_intermed_4 <= R_M_CTRL_PC31DOWNTO2_intermed_3;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_4 <= RIN_M_CTRL_PC31DOWNTO2_intermed_3;
RIN_M_CTRL_PC31DOWNTO2_intermed_5 <= RIN_M_CTRL_PC31DOWNTO2_intermed_4;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_4;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_6 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_5;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_6 <= RIN_A_CTRL_PC31DOWNTO2_intermed_5;
RIN_A_CTRL_PC31DOWNTO2_intermed_7 <= RIN_A_CTRL_PC31DOWNTO2_intermed_6;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
R_A_CTRL_PC31DOWNTO2_intermed_5 <= R_A_CTRL_PC31DOWNTO2_intermed_4;
R_A_CTRL_PC31DOWNTO2_intermed_6 <= R_A_CTRL_PC31DOWNTO2_intermed_5;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_4;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
R_X_CTRL_PC31DOWNTO2_intermed_2 <= R_X_CTRL_PC31DOWNTO2_intermed_1;
R_X_CTRL_PC31DOWNTO2_intermed_3 <= R_X_CTRL_PC31DOWNTO2_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
V_D_PC31DOWNTO2_shadow_intermed_6 <= V_D_PC31DOWNTO2_shadow_intermed_5;
V_D_PC31DOWNTO2_shadow_intermed_7 <= V_D_PC31DOWNTO2_shadow_intermed_6;
V_D_PC31DOWNTO2_shadow_intermed_8 <= V_D_PC31DOWNTO2_shadow_intermed_7;
XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO2_shadow;
XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_2 <= XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_D_PC31DOWNTO2_intermed_6 <= RIN_D_PC31DOWNTO2_intermed_5;
RIN_D_PC31DOWNTO2_intermed_7 <= RIN_D_PC31DOWNTO2_intermed_6;
RIN_D_PC31DOWNTO2_intermed_8 <= RIN_D_PC31DOWNTO2_intermed_7;
EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow;
EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_2 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1;
V_F_PC31DOWNTO2_shadow_intermed_1 <= V_F_PC31DOWNTO2_shadow;
V_F_PC31DOWNTO2_shadow_intermed_2 <= V_F_PC31DOWNTO2_shadow_intermed_1;
V_F_PC31DOWNTO2_shadow_intermed_1 <= V_F_PC31DOWNTO2_shadow;
RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC( 31 DOWNTO 2 );
RIN_F_PC31DOWNTO2_intermed_2 <= RIN_F_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_3 <= RIN_X_CTRL_PC31DOWNTO2_intermed_2;
RIN_X_CTRL_PC31DOWNTO2_intermed_4 <= RIN_X_CTRL_PC31DOWNTO2_intermed_3;
IRIN_ADDR31DOWNTO2_intermed_1 <= IRIN.ADDR( 31 DOWNTO 2 );
IRIN_ADDR31DOWNTO2_intermed_2 <= IRIN_ADDR31DOWNTO2_intermed_1;
IRIN_ADDR31DOWNTO2_intermed_3 <= IRIN_ADDR31DOWNTO2_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_4 <= R_E_CTRL_PC31DOWNTO2_intermed_3;
R_E_CTRL_PC31DOWNTO2_intermed_5 <= R_E_CTRL_PC31DOWNTO2_intermed_4;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_5;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_7 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_6;
EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO2_shadow;
EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_2 <= EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_D_PC31DOWNTO2_intermed_5 <= R_D_PC31DOWNTO2_intermed_4;
R_D_PC31DOWNTO2_intermed_6 <= R_D_PC31DOWNTO2_intermed_5;
R_D_PC31DOWNTO2_intermed_7 <= R_D_PC31DOWNTO2_intermed_6;
RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC ( 31 DOWNTO 2 );
IR_ADDR31DOWNTO2_intermed_1 <= IR.ADDR( 31 DOWNTO 2 );
IR_ADDR31DOWNTO2_intermed_2 <= IR_ADDR31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_5 <= RIN_E_CTRL_PC31DOWNTO2_intermed_4;
RIN_E_CTRL_PC31DOWNTO2_intermed_6 <= RIN_E_CTRL_PC31DOWNTO2_intermed_5;
R_F_PC31DOWNTO2_intermed_1 <= R.F.PC( 31 DOWNTO 2 );
R_F_PC31DOWNTO2_intermed_2 <= R_F_PC31DOWNTO2_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_3;
VIR_ADDR31DOWNTO2_shadow_intermed_1 <= VIR_ADDR31DOWNTO2_shadow;
VIR_ADDR31DOWNTO2_shadow_intermed_2 <= VIR_ADDR31DOWNTO2_shadow_intermed_1;
VIR_ADDR31DOWNTO2_shadow_intermed_3 <= VIR_ADDR31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC ( 31 DOWNTO 2 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC ( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_3 <= R_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_4 <= RIN_M_CTRL_PC31DOWNTO2_intermed_3;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_6 <= RIN_A_CTRL_PC31DOWNTO2_intermed_5;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
R_A_CTRL_PC31DOWNTO2_intermed_5 <= R_A_CTRL_PC31DOWNTO2_intermed_4;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
R_X_CTRL_PC31DOWNTO2_intermed_2 <= R_X_CTRL_PC31DOWNTO2_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
V_D_PC31DOWNTO2_shadow_intermed_6 <= V_D_PC31DOWNTO2_shadow_intermed_5;
V_D_PC31DOWNTO2_shadow_intermed_7 <= V_D_PC31DOWNTO2_shadow_intermed_6;
XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO2_shadow;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_D_PC31DOWNTO2_intermed_6 <= RIN_D_PC31DOWNTO2_intermed_5;
RIN_D_PC31DOWNTO2_intermed_7 <= RIN_D_PC31DOWNTO2_intermed_6;
EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow;
EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_2 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1;
V_F_PC31DOWNTO2_shadow_intermed_1 <= V_F_PC31DOWNTO2_shadow;
V_F_PC31DOWNTO2_shadow_intermed_2 <= V_F_PC31DOWNTO2_shadow_intermed_1;
V_F_PC31DOWNTO2_shadow_intermed_1 <= V_F_PC31DOWNTO2_shadow;
RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC( 31 DOWNTO 2 );
RIN_F_PC31DOWNTO2_intermed_2 <= RIN_F_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_3 <= RIN_X_CTRL_PC31DOWNTO2_intermed_2;
IRIN_ADDR31DOWNTO2_intermed_1 <= IRIN.ADDR( 31 DOWNTO 2 );
IRIN_ADDR31DOWNTO2_intermed_2 <= IRIN_ADDR31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_4 <= R_E_CTRL_PC31DOWNTO2_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_5;
EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO2_shadow;
EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_2 <= EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_D_PC31DOWNTO2_intermed_5 <= R_D_PC31DOWNTO2_intermed_4;
R_D_PC31DOWNTO2_intermed_6 <= R_D_PC31DOWNTO2_intermed_5;
RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC ( 31 DOWNTO 2 );
IR_ADDR31DOWNTO2_intermed_1 <= IR.ADDR( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_5 <= RIN_E_CTRL_PC31DOWNTO2_intermed_4;
R_F_PC31DOWNTO2_intermed_1 <= R.F.PC( 31 DOWNTO 2 );
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_2;
VIR_ADDR31DOWNTO2_shadow_intermed_1 <= VIR_ADDR31DOWNTO2_shadow;
VIR_ADDR31DOWNTO2_shadow_intermed_2 <= VIR_ADDR31DOWNTO2_shadow_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_3 <= R_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_4 <= RIN_M_CTRL_PC31DOWNTO2_intermed_3;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_6 <= RIN_A_CTRL_PC31DOWNTO2_intermed_5;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
R_A_CTRL_PC31DOWNTO2_intermed_5 <= R_A_CTRL_PC31DOWNTO2_intermed_4;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
R_X_CTRL_PC31DOWNTO2_intermed_2 <= R_X_CTRL_PC31DOWNTO2_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
V_D_PC31DOWNTO2_shadow_intermed_6 <= V_D_PC31DOWNTO2_shadow_intermed_5;
V_D_PC31DOWNTO2_shadow_intermed_7 <= V_D_PC31DOWNTO2_shadow_intermed_6;
XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO2_shadow;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_D_PC31DOWNTO2_intermed_6 <= RIN_D_PC31DOWNTO2_intermed_5;
RIN_D_PC31DOWNTO2_intermed_7 <= RIN_D_PC31DOWNTO2_intermed_6;
EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow;
V_F_PC31DOWNTO2_shadow_intermed_1 <= V_F_PC31DOWNTO2_shadow;
RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_3 <= RIN_X_CTRL_PC31DOWNTO2_intermed_2;
IRIN_ADDR31DOWNTO2_intermed_1 <= IRIN.ADDR( 31 DOWNTO 2 );
IRIN_ADDR31DOWNTO2_intermed_2 <= IRIN_ADDR31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_4 <= R_E_CTRL_PC31DOWNTO2_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_5;
EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO2_shadow;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_D_PC31DOWNTO2_intermed_5 <= R_D_PC31DOWNTO2_intermed_4;
R_D_PC31DOWNTO2_intermed_6 <= R_D_PC31DOWNTO2_intermed_5;
IR_ADDR31DOWNTO2_intermed_1 <= IR.ADDR( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_5 <= RIN_E_CTRL_PC31DOWNTO2_intermed_4;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_2;
VIR_ADDR31DOWNTO2_shadow_intermed_1 <= VIR_ADDR31DOWNTO2_shadow;
VIR_ADDR31DOWNTO2_shadow_intermed_2 <= VIR_ADDR31DOWNTO2_shadow_intermed_1;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
V_A_MULSTART_shadow_intermed_1 <= V_A_MULSTART_shadow;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
RIN_A_MULSTART_intermed_1 <= RIN.A.MULSTART;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
V_X_DATA0_shadow_intermed_2 <= V_X_DATA0_shadow_intermed_1;
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
DE_INST19_shadow_intermed_2 <= DE_INST19_shadow_intermed_1;
RIN_E_OP131_intermed_1 <= RIN.E.OP1( 31 );
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_A_CTRL_INST19_shadow_intermed_3 <= V_A_CTRL_INST19_shadow_intermed_2;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA ( 0 );
V_E_OP131_shadow_intermed_1 <= V_E_OP131_shadow;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_OP1_shadow_intermed_1 <= V_E_OP1_shadow;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_CTRL_INST19_shadow_intermed_2 <= V_E_CTRL_INST19_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
RIN_E_OP1_intermed_1 <= RIN.E.OP1;
R_E_CTRL_INST19_intermed_1 <= R.E.CTRL.INST( 19 );
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 );
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
R_X_DATA0_intermed_1 <= R.X.DATA( 0 );
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
R_A_CTRL_INST19_intermed_2 <= R_A_CTRL_INST19_intermed_1;
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
RIN_A_CTRL_INST19_intermed_3 <= RIN_A_CTRL_INST19_intermed_2;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST ( 19 );
DCO_DATA0_intermed_1 <= DCO.DATA ( 0 );
RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 );
RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST( 19 );
RIN_E_CTRL_INST19_intermed_2 <= RIN_E_CTRL_INST19_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
V_X_DATA0_shadow_intermed_2 <= V_X_DATA0_shadow_intermed_1;
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
DE_INST19_shadow_intermed_2 <= DE_INST19_shadow_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_A_CTRL_INST19_shadow_intermed_3 <= V_A_CTRL_INST19_shadow_intermed_2;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA ( 0 );
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
V_E_OP2_shadow_intermed_1 <= V_E_OP2_shadow;
RIN_E_OP2_intermed_1 <= RIN.E.OP2;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_CTRL_INST19_shadow_intermed_2 <= V_E_CTRL_INST19_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
R_E_CTRL_INST19_intermed_1 <= R.E.CTRL.INST( 19 );
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 );
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
R_X_DATA0_intermed_1 <= R.X.DATA( 0 );
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
R_A_CTRL_INST19_intermed_2 <= R_A_CTRL_INST19_intermed_1;
RIN_E_OP231_intermed_1 <= RIN.E.OP2( 31 );
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
RIN_A_CTRL_INST19_intermed_3 <= RIN_A_CTRL_INST19_intermed_2;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST ( 19 );
V_E_OP231_shadow_intermed_1 <= V_E_OP231_shadow;
DCO_DATA0_intermed_1 <= DCO.DATA ( 0 );
RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 );
RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST( 19 );
RIN_E_CTRL_INST19_intermed_2 <= RIN_E_CTRL_INST19_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_A_CTRL_INST24_shadow_intermed_1 <= V_A_CTRL_INST24_shadow;
V_A_CTRL_INST24_shadow_intermed_2 <= V_A_CTRL_INST24_shadow_intermed_1;
V_A_CTRL_INST24_shadow_intermed_3 <= V_A_CTRL_INST24_shadow_intermed_2;
V_E_CTRL_INST24_shadow_intermed_1 <= V_E_CTRL_INST24_shadow;
V_E_CTRL_INST24_shadow_intermed_2 <= V_E_CTRL_INST24_shadow_intermed_1;
DE_INST24_shadow_intermed_1 <= DE_INST24_shadow;
DE_INST24_shadow_intermed_2 <= DE_INST24_shadow_intermed_1;
DE_INST24_shadow_intermed_3 <= DE_INST24_shadow_intermed_2;
V_E_CTRL_INST24_shadow_intermed_1 <= V_E_CTRL_INST24_shadow;
R_A_CTRL_INST24_intermed_1 <= R.A.CTRL.INST( 24 );
R_A_CTRL_INST24_intermed_2 <= R_A_CTRL_INST24_intermed_1;
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST ( 24 );
RIN_A_CTRL_INST24_intermed_2 <= RIN_A_CTRL_INST24_intermed_1;
V_A_CTRL_INST24_shadow_intermed_1 <= V_A_CTRL_INST24_shadow;
V_A_CTRL_INST24_shadow_intermed_2 <= V_A_CTRL_INST24_shadow_intermed_1;
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST( 24 );
RIN_A_CTRL_INST24_intermed_2 <= RIN_A_CTRL_INST24_intermed_1;
RIN_A_CTRL_INST24_intermed_3 <= RIN_A_CTRL_INST24_intermed_2;
RIN_E_CTRL_INST24_intermed_1 <= RIN.E.CTRL.INST( 24 );
RIN_E_CTRL_INST24_intermed_2 <= RIN_E_CTRL_INST24_intermed_1;
R_E_CTRL_INST24_intermed_1 <= R.E.CTRL.INST( 24 );
R_E_CTRL_INST24_intermed_2 <= R_E_CTRL_INST24_intermed_1;
R_A_CTRL_INST24_intermed_1 <= R.A.CTRL.INST ( 24 );
RIN_E_CTRL_INST24_intermed_1 <= RIN.E.CTRL.INST ( 24 );
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_DIVSTART_intermed_1 <= RIN.A.DIVSTART;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
V_A_DIVSTART_shadow_intermed_1 <= V_A_DIVSTART_shadow;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
V_X_DATA0_shadow_intermed_2 <= V_X_DATA0_shadow_intermed_1;
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
DE_INST19_shadow_intermed_2 <= DE_INST19_shadow_intermed_1;
RIN_E_OP131_intermed_1 <= RIN.E.OP1( 31 );
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_A_CTRL_INST19_shadow_intermed_3 <= V_A_CTRL_INST19_shadow_intermed_2;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA ( 0 );
V_E_OP131_shadow_intermed_1 <= V_E_OP131_shadow;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_OP1_shadow_intermed_1 <= V_E_OP1_shadow;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_CTRL_INST19_shadow_intermed_2 <= V_E_CTRL_INST19_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
RIN_E_OP1_intermed_1 <= RIN.E.OP1;
R_E_CTRL_INST19_intermed_1 <= R.E.CTRL.INST( 19 );
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 );
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
R_X_DATA0_intermed_1 <= R.X.DATA( 0 );
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
R_A_CTRL_INST19_intermed_2 <= R_A_CTRL_INST19_intermed_1;
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
RIN_A_CTRL_INST19_intermed_3 <= RIN_A_CTRL_INST19_intermed_2;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST ( 19 );
DCO_DATA0_intermed_1 <= DCO.DATA ( 0 );
RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 );
RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST( 19 );
RIN_E_CTRL_INST19_intermed_2 <= RIN_E_CTRL_INST19_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
V_X_DATA0_shadow_intermed_2 <= V_X_DATA0_shadow_intermed_1;
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
DE_INST19_shadow_intermed_2 <= DE_INST19_shadow_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_A_CTRL_INST19_shadow_intermed_3 <= V_A_CTRL_INST19_shadow_intermed_2;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA ( 0 );
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
V_E_OP2_shadow_intermed_1 <= V_E_OP2_shadow;
RIN_E_OP2_intermed_1 <= RIN.E.OP2;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_CTRL_INST19_shadow_intermed_2 <= V_E_CTRL_INST19_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
R_E_CTRL_INST19_intermed_1 <= R.E.CTRL.INST( 19 );
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 );
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
R_X_DATA0_intermed_1 <= R.X.DATA( 0 );
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
R_A_CTRL_INST19_intermed_2 <= R_A_CTRL_INST19_intermed_1;
RIN_E_OP231_intermed_1 <= RIN.E.OP2( 31 );
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
RIN_A_CTRL_INST19_intermed_3 <= RIN_A_CTRL_INST19_intermed_2;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST ( 19 );
V_E_OP231_shadow_intermed_1 <= V_E_OP231_shadow;
DCO_DATA0_intermed_1 <= DCO.DATA ( 0 );
RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 );
RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST( 19 );
RIN_E_CTRL_INST19_intermed_2 <= RIN_E_CTRL_INST19_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
DE_INST19_shadow_intermed_2 <= DE_INST19_shadow_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 );
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
R_A_CTRL_INST19_intermed_2 <= R_A_CTRL_INST19_intermed_1;
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
RIN_M_Y31_intermed_1 <= RIN.M.Y ( 31 );
RIN_M_Y_intermed_1 <= RIN.M.Y;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_M_Y31_shadow_intermed_1 <= V_M_Y31_shadow;
V_M_Y31_shadow_intermed_2 <= V_M_Y31_shadow_intermed_1;
V_M_Y_shadow_intermed_1 <= V_M_Y_shadow;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_CTRL_INST19_shadow_intermed_2 <= V_E_CTRL_INST19_shadow_intermed_1;
R_E_CTRL_INST19_intermed_1 <= R.E.CTRL.INST( 19 );
V_M_Y31_shadow_intermed_1 <= V_M_Y31_shadow;
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 );
RIN_M_Y31_intermed_1 <= RIN.M.Y( 31 );
RIN_M_Y31_intermed_2 <= RIN_M_Y31_intermed_1;
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
R_M_Y31_intermed_1 <= R.M.Y( 31 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST ( 19 );
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST( 19 );
RIN_E_CTRL_INST19_intermed_2 <= RIN_E_CTRL_INST19_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
RIN_M_Y31_intermed_1 <= RIN.M.Y ( 31 );
V_M_Y31_shadow_intermed_1 <= V_M_Y31_shadow;
V_M_Y31_shadow_intermed_2 <= V_M_Y31_shadow_intermed_1;
V_M_Y31_shadow_intermed_1 <= V_M_Y31_shadow;
RIN_M_Y31_intermed_1 <= RIN.M.Y( 31 );
RIN_M_Y31_intermed_2 <= RIN_M_Y31_intermed_1;
R_M_Y31_intermed_1 <= R.M.Y( 31 );
R_M_Y31_intermed_2 <= R_M_Y31_intermed_1;
VDSU_CRDY2_shadow_intermed_1 <= VDSU_CRDY2_shadow;
VDSU_CRDY2_shadow_intermed_2 <= VDSU_CRDY2_shadow_intermed_1;
DSUIN_CRDY2_intermed_1 <= DSUIN.CRDY ( 2 );
VDSU_CRDY2_shadow_intermed_1 <= VDSU_CRDY2_shadow;
DSUIN_CRDY2_intermed_1 <= DSUIN.CRDY( 2 );
DSUIN_CRDY2_intermed_2 <= DSUIN_CRDY2_intermed_1;
DSUR_CRDY2_intermed_1 <= DSUR.CRDY( 2 );
DSUR_CRDY2_intermed_2 <= DSUR_CRDY2_intermed_1;
VP_ERROR_shadow_intermed_1 <= VP_ERROR_shadow;
VP_ERROR_shadow_intermed_2 <= VP_ERROR_shadow_intermed_1;
RIN_X_NERROR_intermed_1 <= RIN.X.NERROR;
RPIN_ERROR_intermed_1 <= RPIN.ERROR;
RPIN_ERROR_intermed_2 <= RPIN_ERROR_intermed_1;
V_X_NERROR_shadow_intermed_1 <= V_X_NERROR_shadow;
RP_ERROR_intermed_1 <= RP.ERROR;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC ( 31 DOWNTO 2 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC ( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC ( 31 DOWNTO 2 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC ( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC ( 31 DOWNTO 2 );
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow;
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 );
RIN_X_RESULT6DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO0_intermed_1;
R_X_RESULT6DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 );
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
R_X_DATA0_intermed_1 <= R.X.DATA( 0 );
RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 );
RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC ( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC ( 31 DOWNTO 2 );
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC ( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC ( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_X_CTRL_TT3DOWNTO0_shadow;
V_X_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_X_CTRL_TT3DOWNTO0_shadow_intermed_1;
R_M_CTRL_TT3DOWNTO0_intermed_1 <= R.M.CTRL.TT( 3 DOWNTO 0 );
R_M_CTRL_TT3DOWNTO0_intermed_2 <= R_M_CTRL_TT3DOWNTO0_intermed_1;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_M_CTRL_TT3DOWNTO0_shadow;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_M_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_M_CTRL_TT3DOWNTO0_shadow_intermed_2;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_3 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2;
R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
R_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= R_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
R_A_CTRL_TT3DOWNTO0_intermed_1 <= R.A.CTRL.TT( 3 DOWNTO 0 );
R_A_CTRL_TT3DOWNTO0_intermed_2 <= R_A_CTRL_TT3DOWNTO0_intermed_1;
R_A_CTRL_TT3DOWNTO0_intermed_3 <= R_A_CTRL_TT3DOWNTO0_intermed_2;
R_A_CTRL_TT3DOWNTO0_intermed_4 <= R_A_CTRL_TT3DOWNTO0_intermed_3;
RIN_A_CTRL_TT3DOWNTO0_intermed_1 <= RIN.A.CTRL.TT( 3 DOWNTO 0 );
RIN_A_CTRL_TT3DOWNTO0_intermed_2 <= RIN_A_CTRL_TT3DOWNTO0_intermed_1;
RIN_A_CTRL_TT3DOWNTO0_intermed_3 <= RIN_A_CTRL_TT3DOWNTO0_intermed_2;
RIN_A_CTRL_TT3DOWNTO0_intermed_4 <= RIN_A_CTRL_TT3DOWNTO0_intermed_3;
RIN_A_CTRL_TT3DOWNTO0_intermed_5 <= RIN_A_CTRL_TT3DOWNTO0_intermed_4;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_3 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_A_CTRL_TT3DOWNTO0_shadow;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_2;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_4 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_3;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_5 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_4;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
R_W_S_TT3DOWNTO0_intermed_1 <= R.W.S.TT( 3 DOWNTO 0 );
R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 );
R_E_CTRL_TT3DOWNTO0_intermed_1 <= R.E.CTRL.TT( 3 DOWNTO 0 );
R_E_CTRL_TT3DOWNTO0_intermed_2 <= R_E_CTRL_TT3DOWNTO0_intermed_1;
R_E_CTRL_TT3DOWNTO0_intermed_3 <= R_E_CTRL_TT3DOWNTO0_intermed_2;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1;
RIN_W_S_TT3DOWNTO0_intermed_1 <= RIN.W.S.TT( 3 DOWNTO 0 );
RIN_W_S_TT3DOWNTO0_intermed_2 <= RIN_W_S_TT3DOWNTO0_intermed_1;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_E_CTRL_TT3DOWNTO0_shadow;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_2;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_4 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_3;
RIN_M_CTRL_TT3DOWNTO0_intermed_1 <= RIN.M.CTRL.TT( 3 DOWNTO 0 );
RIN_M_CTRL_TT3DOWNTO0_intermed_2 <= RIN_M_CTRL_TT3DOWNTO0_intermed_1;
RIN_M_CTRL_TT3DOWNTO0_intermed_3 <= RIN_M_CTRL_TT3DOWNTO0_intermed_2;
RIN_X_CTRL_TT3DOWNTO0_intermed_1 <= RIN.X.CTRL.TT( 3 DOWNTO 0 );
RIN_X_CTRL_TT3DOWNTO0_intermed_2 <= RIN_X_CTRL_TT3DOWNTO0_intermed_1;
V_W_S_TT3DOWNTO0_shadow_intermed_1 <= V_W_S_TT3DOWNTO0_shadow;
R_X_CTRL_TT3DOWNTO0_intermed_1 <= R.X.CTRL.TT( 3 DOWNTO 0 );
RIN_E_CTRL_TT3DOWNTO0_intermed_1 <= RIN.E.CTRL.TT( 3 DOWNTO 0 );
RIN_E_CTRL_TT3DOWNTO0_intermed_2 <= RIN_E_CTRL_TT3DOWNTO0_intermed_1;
RIN_E_CTRL_TT3DOWNTO0_intermed_3 <= RIN_E_CTRL_TT3DOWNTO0_intermed_2;
RIN_E_CTRL_TT3DOWNTO0_intermed_4 <= RIN_E_CTRL_TT3DOWNTO0_intermed_3;
XC_VECTT3DOWNTO0_shadow_intermed_1 <= XC_VECTT3DOWNTO0_shadow;
V_M_RESULT1DOWNTO0_shadow_intermed_1 <= V_M_RESULT1DOWNTO0_shadow;
RIN_M_RESULT1DOWNTO0_intermed_1 <= RIN.M.RESULT( 1 DOWNTO 0 );
RIN_M_RESULT1DOWNTO0_intermed_2 <= RIN_M_RESULT1DOWNTO0_intermed_1;
R_M_RESULT1DOWNTO0_intermed_1 <= R.M.RESULT( 1 DOWNTO 0 );
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 );
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
R_X_DATA031_intermed_1 <= R.X.DATA ( 0 )( 31 );
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
DE_INST19_shadow_intermed_2 <= DE_INST19_shadow_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
R_E_CTRL_INST19_intermed_1 <= R.E.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 );
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST( 19 );
RIN_E_CTRL_INST19_intermed_2 <= RIN_E_CTRL_INST19_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST ( 20 );
R_E_CTRL_INST20_intermed_1 <= R.E.CTRL.INST( 20 );
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST( 20 );
RIN_A_CTRL_INST20_intermed_2 <= RIN_A_CTRL_INST20_intermed_1;
V_E_CTRL_INST20_shadow_intermed_1 <= V_E_CTRL_INST20_shadow;
DE_INST20_shadow_intermed_1 <= DE_INST20_shadow;
DE_INST20_shadow_intermed_2 <= DE_INST20_shadow_intermed_1;
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
V_A_CTRL_INST20_shadow_intermed_2 <= V_A_CTRL_INST20_shadow_intermed_1;
RIN_E_CTRL_INST20_intermed_1 <= RIN.E.CTRL.INST( 20 );
RIN_E_CTRL_INST20_intermed_2 <= RIN_E_CTRL_INST20_intermed_1;
R_A_CTRL_INST20_intermed_1 <= R.A.CTRL.INST( 20 );
RIN_X_DATA00_intermed_1 <= RIN.X.DATA ( 0 )( 0 );
RIN_X_DATA00_intermed_2 <= RIN_X_DATA00_intermed_1;
DCO_DATA00_intermed_1 <= DCO.DATA ( 0 )( 0 );
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
R_X_DATA00_intermed_1 <= R.X.DATA ( 0 )( 0 );
RIN_X_DATA00_intermed_1 <= RIN.X.DATA( 0 )( 0 );
RIN_X_DATA00_intermed_2 <= RIN_X_DATA00_intermed_1;
R_X_DATA00_intermed_1 <= R.X.DATA( 0 )( 0 );
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
RIN_X_DATA00_intermed_1 <= RIN.X.DATA( 0 )( 0 );
RIN_X_DATA00_intermed_2 <= RIN_X_DATA00_intermed_1;
R_X_DATA00_intermed_1 <= R.X.DATA( 0 )( 0 );
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
R_X_DATA04DOWNTO0_intermed_1 <= R.X.DATA( 0 )( 4 DOWNTO 0 );
R_X_DATA04DOWNTO0_intermed_1 <= R.X.DATA ( 0 )( 4 DOWNTO 0 );
DCO_DATA04DOWNTO0_intermed_1 <= DCO.DATA ( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA ( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_2 <= RIN_X_DATA04DOWNTO0_intermed_1;
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_2 <= RIN_X_DATA04DOWNTO0_intermed_1;
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
R_X_DATA04DOWNTO0_intermed_1 <= R.X.DATA( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_2 <= RIN_X_DATA04DOWNTO0_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_3 <= R_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_4 <= RIN_M_CTRL_PC31DOWNTO2_intermed_3;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_6 <= RIN_A_CTRL_PC31DOWNTO2_intermed_5;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
R_A_CTRL_PC31DOWNTO2_intermed_5 <= R_A_CTRL_PC31DOWNTO2_intermed_4;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
R_X_CTRL_PC31DOWNTO2_intermed_2 <= R_X_CTRL_PC31DOWNTO2_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
V_D_PC31DOWNTO2_shadow_intermed_6 <= V_D_PC31DOWNTO2_shadow_intermed_5;
V_D_PC31DOWNTO2_shadow_intermed_7 <= V_D_PC31DOWNTO2_shadow_intermed_6;
XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO2_shadow;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_D_PC31DOWNTO2_intermed_6 <= RIN_D_PC31DOWNTO2_intermed_5;
RIN_D_PC31DOWNTO2_intermed_7 <= RIN_D_PC31DOWNTO2_intermed_6;
EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow;
V_F_PC31DOWNTO2_shadow_intermed_1 <= V_F_PC31DOWNTO2_shadow;
RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC( 31 DOWNTO 2 );
RIN_F_PC31DOWNTO2_intermed_2 <= RIN_F_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_3 <= RIN_X_CTRL_PC31DOWNTO2_intermed_2;
IRIN_ADDR31DOWNTO2_intermed_1 <= IRIN.ADDR( 31 DOWNTO 2 );
IRIN_ADDR31DOWNTO2_intermed_2 <= IRIN_ADDR31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_4 <= R_E_CTRL_PC31DOWNTO2_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_5;
EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO2_shadow;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_D_PC31DOWNTO2_intermed_5 <= R_D_PC31DOWNTO2_intermed_4;
R_D_PC31DOWNTO2_intermed_6 <= R_D_PC31DOWNTO2_intermed_5;
IR_ADDR31DOWNTO2_intermed_1 <= IR.ADDR( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_5 <= RIN_E_CTRL_PC31DOWNTO2_intermed_4;
R_F_PC31DOWNTO2_intermed_1 <= R.F.PC( 31 DOWNTO 2 );
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_2;
VIR_ADDR31DOWNTO2_shadow_intermed_1 <= VIR_ADDR31DOWNTO2_shadow;
VIR_ADDR31DOWNTO2_shadow_intermed_2 <= VIR_ADDR31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
V_A_CTRL_INST24_shadow_intermed_1 <= V_A_CTRL_INST24_shadow;
V_A_CTRL_INST24_shadow_intermed_2 <= V_A_CTRL_INST24_shadow_intermed_1;
V_E_CTRL_INST24_shadow_intermed_1 <= V_E_CTRL_INST24_shadow;
DE_INST24_shadow_intermed_1 <= DE_INST24_shadow;
DE_INST24_shadow_intermed_2 <= DE_INST24_shadow_intermed_1;
R_A_CTRL_INST24_intermed_1 <= R.A.CTRL.INST( 24 );
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST ( 24 );
V_A_CTRL_INST24_shadow_intermed_1 <= V_A_CTRL_INST24_shadow;
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST( 24 );
RIN_A_CTRL_INST24_intermed_2 <= RIN_A_CTRL_INST24_intermed_1;
RIN_E_CTRL_INST24_intermed_1 <= RIN.E.CTRL.INST( 24 );
RIN_E_CTRL_INST24_intermed_2 <= RIN_E_CTRL_INST24_intermed_1;
R_E_CTRL_INST24_intermed_1 <= R.E.CTRL.INST( 24 );
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
V_M_Y31_shadow_intermed_1 <= V_M_Y31_shadow;
RIN_M_Y31_intermed_1 <= RIN.M.Y( 31 );
RIN_M_Y31_intermed_2 <= RIN_M_Y31_intermed_1;
R_M_Y31_intermed_1 <= R.M.Y( 31 );
VDSU_CRDY2_shadow_intermed_1 <= VDSU_CRDY2_shadow;
DSUIN_CRDY2_intermed_1 <= DSUIN.CRDY( 2 );
DSUIN_CRDY2_intermed_2 <= DSUIN_CRDY2_intermed_1;
DSUR_CRDY2_intermed_1 <= DSUR.CRDY( 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC ( 31 DOWNTO 2 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_X_DATA1_shadow_intermed_1 <= V_X_DATA1_shadow;
DCO_DATA1_intermed_1 <= DCO.DATA ( 1 );
V_X_DATA1_shadow_intermed_1 <= V_X_DATA1_shadow;
V_X_DATA1_shadow_intermed_2 <= V_X_DATA1_shadow_intermed_1;
RIN_X_DATA1_intermed_1 <= RIN.X.DATA ( 1 );
R_X_DATA1_intermed_1 <= R.X.DATA( 1 );
R_X_DATA1_intermed_2 <= R_X_DATA1_intermed_1;
RIN_X_DATA1_intermed_1 <= RIN.X.DATA( 1 );
RIN_X_DATA1_intermed_2 <= RIN_X_DATA1_intermed_1;
EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO12_shadow;
EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_2 <= EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_1;
RIN_F_PC31DOWNTO12_intermed_1 <= RIN.F.PC ( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_2 <= RIN_A_CTRL_PC31DOWNTO12_intermed_1;
RIN_A_CTRL_PC31DOWNTO12_intermed_3 <= RIN_A_CTRL_PC31DOWNTO12_intermed_2;
RIN_A_CTRL_PC31DOWNTO12_intermed_4 <= RIN_A_CTRL_PC31DOWNTO12_intermed_3;
RIN_A_CTRL_PC31DOWNTO12_intermed_5 <= RIN_A_CTRL_PC31DOWNTO12_intermed_4;
RIN_A_CTRL_PC31DOWNTO12_intermed_6 <= RIN_A_CTRL_PC31DOWNTO12_intermed_5;
RIN_A_CTRL_PC31DOWNTO12_intermed_7 <= RIN_A_CTRL_PC31DOWNTO12_intermed_6;
RIN_E_CTRL_PC31DOWNTO12_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 12 );
RIN_E_CTRL_PC31DOWNTO12_intermed_2 <= RIN_E_CTRL_PC31DOWNTO12_intermed_1;
RIN_E_CTRL_PC31DOWNTO12_intermed_3 <= RIN_E_CTRL_PC31DOWNTO12_intermed_2;
RIN_E_CTRL_PC31DOWNTO12_intermed_4 <= RIN_E_CTRL_PC31DOWNTO12_intermed_3;
RIN_E_CTRL_PC31DOWNTO12_intermed_5 <= RIN_E_CTRL_PC31DOWNTO12_intermed_4;
RIN_E_CTRL_PC31DOWNTO12_intermed_6 <= RIN_E_CTRL_PC31DOWNTO12_intermed_5;
V_F_PC31DOWNTO12_shadow_intermed_1 <= V_F_PC31DOWNTO12_shadow;
V_F_PC31DOWNTO12_shadow_intermed_2 <= V_F_PC31DOWNTO12_shadow_intermed_1;
R_M_CTRL_PC31DOWNTO12_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 12 );
R_M_CTRL_PC31DOWNTO12_intermed_2 <= R_M_CTRL_PC31DOWNTO12_intermed_1;
R_M_CTRL_PC31DOWNTO12_intermed_3 <= R_M_CTRL_PC31DOWNTO12_intermed_2;
R_M_CTRL_PC31DOWNTO12_intermed_4 <= R_M_CTRL_PC31DOWNTO12_intermed_3;
IRIN_ADDR31DOWNTO12_intermed_1 <= IRIN.ADDR( 31 DOWNTO 12 );
IRIN_ADDR31DOWNTO12_intermed_2 <= IRIN_ADDR31DOWNTO12_intermed_1;
IRIN_ADDR31DOWNTO12_intermed_3 <= IRIN_ADDR31DOWNTO12_intermed_2;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO12_shadow;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_3;
EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO13_shadow;
EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_2 <= EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_1;
XC_TRAP_ADDRESS31DOWNTO12_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO12_shadow;
XC_TRAP_ADDRESS31DOWNTO12_shadow_intermed_2 <= XC_TRAP_ADDRESS31DOWNTO12_shadow_intermed_1;
R_F_PC31DOWNTO12_intermed_1 <= R.F.PC( 31 DOWNTO 12 );
R_F_PC31DOWNTO12_intermed_2 <= R_F_PC31DOWNTO12_intermed_1;
RIN_M_CTRL_PC31DOWNTO12_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 12 );
RIN_M_CTRL_PC31DOWNTO12_intermed_2 <= RIN_M_CTRL_PC31DOWNTO12_intermed_1;
RIN_M_CTRL_PC31DOWNTO12_intermed_3 <= RIN_M_CTRL_PC31DOWNTO12_intermed_2;
RIN_M_CTRL_PC31DOWNTO12_intermed_4 <= RIN_M_CTRL_PC31DOWNTO12_intermed_3;
RIN_M_CTRL_PC31DOWNTO12_intermed_5 <= RIN_M_CTRL_PC31DOWNTO12_intermed_4;
IR_ADDR31DOWNTO12_intermed_1 <= IR.ADDR( 31 DOWNTO 12 );
IR_ADDR31DOWNTO12_intermed_2 <= IR_ADDR31DOWNTO12_intermed_1;
R_X_CTRL_PC31DOWNTO12_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 12 );
R_X_CTRL_PC31DOWNTO12_intermed_2 <= R_X_CTRL_PC31DOWNTO12_intermed_1;
R_X_CTRL_PC31DOWNTO12_intermed_3 <= R_X_CTRL_PC31DOWNTO12_intermed_2;
V_D_PC31DOWNTO12_shadow_intermed_1 <= V_D_PC31DOWNTO12_shadow;
V_D_PC31DOWNTO12_shadow_intermed_2 <= V_D_PC31DOWNTO12_shadow_intermed_1;
V_D_PC31DOWNTO12_shadow_intermed_3 <= V_D_PC31DOWNTO12_shadow_intermed_2;
V_D_PC31DOWNTO12_shadow_intermed_4 <= V_D_PC31DOWNTO12_shadow_intermed_3;
V_D_PC31DOWNTO12_shadow_intermed_5 <= V_D_PC31DOWNTO12_shadow_intermed_4;
V_D_PC31DOWNTO12_shadow_intermed_6 <= V_D_PC31DOWNTO12_shadow_intermed_5;
V_D_PC31DOWNTO12_shadow_intermed_7 <= V_D_PC31DOWNTO12_shadow_intermed_6;
V_D_PC31DOWNTO12_shadow_intermed_8 <= V_D_PC31DOWNTO12_shadow_intermed_7;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO12_shadow;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_5;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_7 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_6;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO12_shadow;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_4;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_6 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_5;
EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_1 <= EX_ADD_RES32DOWNTO330DOWNTO11_shadow;
EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_2 <= EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_1;
RIN_F_PC31DOWNTO12_intermed_1 <= RIN.F.PC( 31 DOWNTO 12 );
RIN_F_PC31DOWNTO12_intermed_2 <= RIN_F_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_1 <= R.D.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_2 <= R_D_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_3 <= R_D_PC31DOWNTO12_intermed_2;
R_D_PC31DOWNTO12_intermed_4 <= R_D_PC31DOWNTO12_intermed_3;
R_D_PC31DOWNTO12_intermed_5 <= R_D_PC31DOWNTO12_intermed_4;
R_D_PC31DOWNTO12_intermed_6 <= R_D_PC31DOWNTO12_intermed_5;
R_D_PC31DOWNTO12_intermed_7 <= R_D_PC31DOWNTO12_intermed_6;
R_A_CTRL_PC31DOWNTO12_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 12 );
R_A_CTRL_PC31DOWNTO12_intermed_2 <= R_A_CTRL_PC31DOWNTO12_intermed_1;
R_A_CTRL_PC31DOWNTO12_intermed_3 <= R_A_CTRL_PC31DOWNTO12_intermed_2;
R_A_CTRL_PC31DOWNTO12_intermed_4 <= R_A_CTRL_PC31DOWNTO12_intermed_3;
R_A_CTRL_PC31DOWNTO12_intermed_5 <= R_A_CTRL_PC31DOWNTO12_intermed_4;
R_A_CTRL_PC31DOWNTO12_intermed_6 <= R_A_CTRL_PC31DOWNTO12_intermed_5;
R_E_CTRL_PC31DOWNTO12_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 12 );
R_E_CTRL_PC31DOWNTO12_intermed_2 <= R_E_CTRL_PC31DOWNTO12_intermed_1;
R_E_CTRL_PC31DOWNTO12_intermed_3 <= R_E_CTRL_PC31DOWNTO12_intermed_2;
R_E_CTRL_PC31DOWNTO12_intermed_4 <= R_E_CTRL_PC31DOWNTO12_intermed_3;
R_E_CTRL_PC31DOWNTO12_intermed_5 <= R_E_CTRL_PC31DOWNTO12_intermed_4;
RIN_X_CTRL_PC31DOWNTO12_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 12 );
RIN_X_CTRL_PC31DOWNTO12_intermed_2 <= RIN_X_CTRL_PC31DOWNTO12_intermed_1;
RIN_X_CTRL_PC31DOWNTO12_intermed_3 <= RIN_X_CTRL_PC31DOWNTO12_intermed_2;
RIN_X_CTRL_PC31DOWNTO12_intermed_4 <= RIN_X_CTRL_PC31DOWNTO12_intermed_3;
RIN_D_PC31DOWNTO12_intermed_1 <= RIN.D.PC( 31 DOWNTO 12 );
RIN_D_PC31DOWNTO12_intermed_2 <= RIN_D_PC31DOWNTO12_intermed_1;
RIN_D_PC31DOWNTO12_intermed_3 <= RIN_D_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_4 <= RIN_D_PC31DOWNTO12_intermed_3;
RIN_D_PC31DOWNTO12_intermed_5 <= RIN_D_PC31DOWNTO12_intermed_4;
RIN_D_PC31DOWNTO12_intermed_6 <= RIN_D_PC31DOWNTO12_intermed_5;
RIN_D_PC31DOWNTO12_intermed_7 <= RIN_D_PC31DOWNTO12_intermed_6;
RIN_D_PC31DOWNTO12_intermed_8 <= RIN_D_PC31DOWNTO12_intermed_7;
VIR_ADDR31DOWNTO12_shadow_intermed_1 <= VIR_ADDR31DOWNTO12_shadow;
VIR_ADDR31DOWNTO12_shadow_intermed_2 <= VIR_ADDR31DOWNTO12_shadow_intermed_1;
VIR_ADDR31DOWNTO12_shadow_intermed_3 <= VIR_ADDR31DOWNTO12_shadow_intermed_2;
V_F_PC31DOWNTO12_shadow_intermed_1 <= V_F_PC31DOWNTO12_shadow;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO12_shadow;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_4;
ICO_DATA0_intermed_1 <= ICO.DATA ( 0 );
RIN_D_INST0_intermed_1 <= RIN.D.INST ( 0 );
V_D_INST0_shadow_intermed_1 <= V_D_INST0_shadow;
V_D_INST0_shadow_intermed_2 <= V_D_INST0_shadow_intermed_1;
R_D_INST0_intermed_1 <= R.D.INST( 0 );
R_D_INST0_intermed_2 <= R_D_INST0_intermed_1;
RIN_D_INST0_intermed_1 <= RIN.D.INST( 0 );
RIN_D_INST0_intermed_2 <= RIN_D_INST0_intermed_1;
V_D_INST0_shadow_intermed_1 <= V_D_INST0_shadow;
V_D_INST1_shadow_intermed_1 <= V_D_INST1_shadow;
V_D_INST1_shadow_intermed_2 <= V_D_INST1_shadow_intermed_1;
RIN_D_INST1_intermed_1 <= RIN.D.INST ( 1 );
RIN_D_INST1_intermed_1 <= RIN.D.INST( 1 );
RIN_D_INST1_intermed_2 <= RIN_D_INST1_intermed_1;
V_D_INST1_shadow_intermed_1 <= V_D_INST1_shadow;
R_D_INST1_intermed_1 <= R.D.INST( 1 );
R_D_INST1_intermed_2 <= R_D_INST1_intermed_1;
ICO_DATA1_intermed_1 <= ICO.DATA ( 1 );
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 );
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
R_X_DATA031_intermed_2 <= R_X_DATA031_intermed_1;
V_X_DATA1_shadow_intermed_1 <= V_X_DATA1_shadow;
R_X_DATA1_intermed_1 <= R.X.DATA( 1 );
RIN_X_DATA1_intermed_1 <= RIN.X.DATA( 1 );
RIN_X_DATA1_intermed_2 <= RIN_X_DATA1_intermed_1;
EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO12_shadow;
RIN_A_CTRL_PC31DOWNTO12_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_2 <= RIN_A_CTRL_PC31DOWNTO12_intermed_1;
RIN_A_CTRL_PC31DOWNTO12_intermed_3 <= RIN_A_CTRL_PC31DOWNTO12_intermed_2;
RIN_A_CTRL_PC31DOWNTO12_intermed_4 <= RIN_A_CTRL_PC31DOWNTO12_intermed_3;
RIN_A_CTRL_PC31DOWNTO12_intermed_5 <= RIN_A_CTRL_PC31DOWNTO12_intermed_4;
RIN_A_CTRL_PC31DOWNTO12_intermed_6 <= RIN_A_CTRL_PC31DOWNTO12_intermed_5;
RIN_E_CTRL_PC31DOWNTO12_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 12 );
RIN_E_CTRL_PC31DOWNTO12_intermed_2 <= RIN_E_CTRL_PC31DOWNTO12_intermed_1;
RIN_E_CTRL_PC31DOWNTO12_intermed_3 <= RIN_E_CTRL_PC31DOWNTO12_intermed_2;
RIN_E_CTRL_PC31DOWNTO12_intermed_4 <= RIN_E_CTRL_PC31DOWNTO12_intermed_3;
RIN_E_CTRL_PC31DOWNTO12_intermed_5 <= RIN_E_CTRL_PC31DOWNTO12_intermed_4;
V_F_PC31DOWNTO12_shadow_intermed_1 <= V_F_PC31DOWNTO12_shadow;
R_M_CTRL_PC31DOWNTO12_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 12 );
R_M_CTRL_PC31DOWNTO12_intermed_2 <= R_M_CTRL_PC31DOWNTO12_intermed_1;
R_M_CTRL_PC31DOWNTO12_intermed_3 <= R_M_CTRL_PC31DOWNTO12_intermed_2;
IRIN_ADDR31DOWNTO12_intermed_1 <= IRIN.ADDR( 31 DOWNTO 12 );
IRIN_ADDR31DOWNTO12_intermed_2 <= IRIN_ADDR31DOWNTO12_intermed_1;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO12_shadow;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_2;
EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO13_shadow;
XC_TRAP_ADDRESS31DOWNTO12_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO12_shadow;
R_F_PC31DOWNTO12_intermed_1 <= R.F.PC( 31 DOWNTO 12 );
RIN_M_CTRL_PC31DOWNTO12_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 12 );
RIN_M_CTRL_PC31DOWNTO12_intermed_2 <= RIN_M_CTRL_PC31DOWNTO12_intermed_1;
RIN_M_CTRL_PC31DOWNTO12_intermed_3 <= RIN_M_CTRL_PC31DOWNTO12_intermed_2;
RIN_M_CTRL_PC31DOWNTO12_intermed_4 <= RIN_M_CTRL_PC31DOWNTO12_intermed_3;
IR_ADDR31DOWNTO12_intermed_1 <= IR.ADDR( 31 DOWNTO 12 );
R_X_CTRL_PC31DOWNTO12_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 12 );
R_X_CTRL_PC31DOWNTO12_intermed_2 <= R_X_CTRL_PC31DOWNTO12_intermed_1;
V_D_PC31DOWNTO12_shadow_intermed_1 <= V_D_PC31DOWNTO12_shadow;
V_D_PC31DOWNTO12_shadow_intermed_2 <= V_D_PC31DOWNTO12_shadow_intermed_1;
V_D_PC31DOWNTO12_shadow_intermed_3 <= V_D_PC31DOWNTO12_shadow_intermed_2;
V_D_PC31DOWNTO12_shadow_intermed_4 <= V_D_PC31DOWNTO12_shadow_intermed_3;
V_D_PC31DOWNTO12_shadow_intermed_5 <= V_D_PC31DOWNTO12_shadow_intermed_4;
V_D_PC31DOWNTO12_shadow_intermed_6 <= V_D_PC31DOWNTO12_shadow_intermed_5;
V_D_PC31DOWNTO12_shadow_intermed_7 <= V_D_PC31DOWNTO12_shadow_intermed_6;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO12_shadow;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_5;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO12_shadow;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_4;
EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_1 <= EX_ADD_RES32DOWNTO330DOWNTO11_shadow;
RIN_F_PC31DOWNTO12_intermed_1 <= RIN.F.PC( 31 DOWNTO 12 );
RIN_F_PC31DOWNTO12_intermed_2 <= RIN_F_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_1 <= R.D.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_2 <= R_D_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_3 <= R_D_PC31DOWNTO12_intermed_2;
R_D_PC31DOWNTO12_intermed_4 <= R_D_PC31DOWNTO12_intermed_3;
R_D_PC31DOWNTO12_intermed_5 <= R_D_PC31DOWNTO12_intermed_4;
R_D_PC31DOWNTO12_intermed_6 <= R_D_PC31DOWNTO12_intermed_5;
R_A_CTRL_PC31DOWNTO12_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 12 );
R_A_CTRL_PC31DOWNTO12_intermed_2 <= R_A_CTRL_PC31DOWNTO12_intermed_1;
R_A_CTRL_PC31DOWNTO12_intermed_3 <= R_A_CTRL_PC31DOWNTO12_intermed_2;
R_A_CTRL_PC31DOWNTO12_intermed_4 <= R_A_CTRL_PC31DOWNTO12_intermed_3;
R_A_CTRL_PC31DOWNTO12_intermed_5 <= R_A_CTRL_PC31DOWNTO12_intermed_4;
R_E_CTRL_PC31DOWNTO12_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 12 );
R_E_CTRL_PC31DOWNTO12_intermed_2 <= R_E_CTRL_PC31DOWNTO12_intermed_1;
R_E_CTRL_PC31DOWNTO12_intermed_3 <= R_E_CTRL_PC31DOWNTO12_intermed_2;
R_E_CTRL_PC31DOWNTO12_intermed_4 <= R_E_CTRL_PC31DOWNTO12_intermed_3;
RIN_X_CTRL_PC31DOWNTO12_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 12 );
RIN_X_CTRL_PC31DOWNTO12_intermed_2 <= RIN_X_CTRL_PC31DOWNTO12_intermed_1;
RIN_X_CTRL_PC31DOWNTO12_intermed_3 <= RIN_X_CTRL_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_1 <= RIN.D.PC( 31 DOWNTO 12 );
RIN_D_PC31DOWNTO12_intermed_2 <= RIN_D_PC31DOWNTO12_intermed_1;
RIN_D_PC31DOWNTO12_intermed_3 <= RIN_D_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_4 <= RIN_D_PC31DOWNTO12_intermed_3;
RIN_D_PC31DOWNTO12_intermed_5 <= RIN_D_PC31DOWNTO12_intermed_4;
RIN_D_PC31DOWNTO12_intermed_6 <= RIN_D_PC31DOWNTO12_intermed_5;
RIN_D_PC31DOWNTO12_intermed_7 <= RIN_D_PC31DOWNTO12_intermed_6;
VIR_ADDR31DOWNTO12_shadow_intermed_1 <= VIR_ADDR31DOWNTO12_shadow;
VIR_ADDR31DOWNTO12_shadow_intermed_2 <= VIR_ADDR31DOWNTO12_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO12_shadow;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_D_INST0_shadow_intermed_1 <= V_D_INST0_shadow;
R_D_INST0_intermed_1 <= R.D.INST( 0 );
RIN_D_INST0_intermed_1 <= RIN.D.INST( 0 );
RIN_D_INST0_intermed_2 <= RIN_D_INST0_intermed_1;
V_D_INST1_shadow_intermed_1 <= V_D_INST1_shadow;
RIN_D_INST1_intermed_1 <= RIN.D.INST( 1 );
RIN_D_INST1_intermed_2 <= RIN_D_INST1_intermed_1;
R_D_INST1_intermed_1 <= R.D.INST( 1 );
V_X_DATA03_shadow_intermed_1 <= V_X_DATA03_shadow;
V_X_DATA03_shadow_intermed_2 <= V_X_DATA03_shadow_intermed_1;
V_X_DATA03_shadow_intermed_1 <= V_X_DATA03_shadow;
DCO_DATA03_intermed_1 <= DCO.DATA ( 0 )( 3 );
RIN_X_DATA03_intermed_1 <= RIN.X.DATA ( 0 )( 3 );
R_X_DATA03_intermed_1 <= R.X.DATA( 0 )( 3 );
R_X_DATA03_intermed_2 <= R_X_DATA03_intermed_1;
RIN_X_DATA03_intermed_1 <= RIN.X.DATA( 0 )( 3 );
RIN_X_DATA03_intermed_2 <= RIN_X_DATA03_intermed_1;
V_X_DATA03_shadow_intermed_1 <= V_X_DATA03_shadow;
R_X_DATA03_intermed_1 <= R.X.DATA( 0 )( 3 );
RIN_X_DATA03_intermed_1 <= RIN.X.DATA( 0 )( 3 );
RIN_X_DATA03_intermed_2 <= RIN_X_DATA03_intermed_1;
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST ( 20 );
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST( 20 );
RIN_A_CTRL_INST20_intermed_2 <= RIN_A_CTRL_INST20_intermed_1;
DE_INST20_shadow_intermed_1 <= DE_INST20_shadow;
DE_INST20_shadow_intermed_2 <= DE_INST20_shadow_intermed_1;
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
V_A_CTRL_INST20_shadow_intermed_2 <= V_A_CTRL_INST20_shadow_intermed_1;
R_A_CTRL_INST20_intermed_1 <= R.A.CTRL.INST( 20 );
R_A_CTRL_INST20_intermed_2 <= R_A_CTRL_INST20_intermed_1;
RIN_X_DATA00_intermed_1 <= RIN.X.DATA ( 0 )( 0 );
DCO_DATA00_intermed_1 <= DCO.DATA ( 0 )( 0 );
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
V_X_DATA00_shadow_intermed_2 <= V_X_DATA00_shadow_intermed_1;
RIN_X_DATA00_intermed_1 <= RIN.X.DATA( 0 )( 0 );
RIN_X_DATA00_intermed_2 <= RIN_X_DATA00_intermed_1;
R_X_DATA00_intermed_1 <= R.X.DATA( 0 )( 0 );
R_X_DATA00_intermed_2 <= R_X_DATA00_intermed_1;
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
V_X_DATA04DOWNTO0_shadow_intermed_2 <= V_X_DATA04DOWNTO0_shadow_intermed_1;
R_X_DATA04DOWNTO0_intermed_1 <= R.X.DATA( 0 )( 4 DOWNTO 0 );
R_X_DATA04DOWNTO0_intermed_2 <= R_X_DATA04DOWNTO0_intermed_1;
DCO_DATA04DOWNTO0_intermed_1 <= DCO.DATA ( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_2 <= RIN_X_DATA04DOWNTO0_intermed_1;
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA ( 0 )( 4 DOWNTO 0 );
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
V_A_CTRL_INST24_shadow_intermed_1 <= V_A_CTRL_INST24_shadow;
V_A_CTRL_INST24_shadow_intermed_2 <= V_A_CTRL_INST24_shadow_intermed_1;
DE_INST24_shadow_intermed_1 <= DE_INST24_shadow;
DE_INST24_shadow_intermed_2 <= DE_INST24_shadow_intermed_1;
R_A_CTRL_INST24_intermed_1 <= R.A.CTRL.INST( 24 );
R_A_CTRL_INST24_intermed_2 <= R_A_CTRL_INST24_intermed_1;
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST ( 24 );
V_A_CTRL_INST24_shadow_intermed_1 <= V_A_CTRL_INST24_shadow;
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST( 24 );
RIN_A_CTRL_INST24_intermed_2 <= RIN_A_CTRL_INST24_intermed_1;
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST( 20 );
RIN_A_CTRL_INST20_intermed_2 <= RIN_A_CTRL_INST20_intermed_1;
DE_INST20_shadow_intermed_1 <= DE_INST20_shadow;
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
R_A_CTRL_INST20_intermed_1 <= R.A.CTRL.INST( 20 );
V_A_CTRL_INST24_shadow_intermed_1 <= V_A_CTRL_INST24_shadow;
DE_INST24_shadow_intermed_1 <= DE_INST24_shadow;
R_A_CTRL_INST24_intermed_1 <= R.A.CTRL.INST( 24 );
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST( 24 );
RIN_A_CTRL_INST24_intermed_2 <= RIN_A_CTRL_INST24_intermed_1;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1;
R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
R_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= R_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 );
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
RIN_F_PC_intermed_1 <= RIN.F.PC;
EX_ADD_RES32DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO3_shadow;
XC_TRAP_ADDRESS_shadow_intermed_1 <= XC_TRAP_ADDRESS_shadow;
EX_JUMP_ADDRESS_shadow_intermed_1 <= EX_JUMP_ADDRESS_shadow;
V_F_PC_shadow_intermed_1 <= V_F_PC_shadow;
RIN_A_RFE1_intermed_1 <= RIN.A.RFE1;
V_A_RFE1_shadow_intermed_1 <= V_A_RFE1_shadow;
RIN_A_RFE2_intermed_1 <= RIN.A.RFE2;
V_A_RFE2_shadow_intermed_1 <= V_A_RFE2_shadow;
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
V_X_DATA0_shadow_intermed_2 <= V_X_DATA0_shadow_intermed_1;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA ( 0 );
V_E_OP1_shadow_intermed_1 <= V_E_OP1_shadow;
V_E_OP2_shadow_intermed_1 <= V_E_OP2_shadow;
RIN_E_OP2_intermed_1 <= RIN.E.OP2;
RIN_E_OP1_intermed_1 <= RIN.E.OP1;
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
V_E_ALUCIN_shadow_intermed_1 <= V_E_ALUCIN_shadow;
R_X_DATA0_intermed_1 <= R.X.DATA( 0 );
RIN_E_ALUCIN_intermed_1 <= RIN.E.ALUCIN;
DCO_DATA0_intermed_1 <= DCO.DATA ( 0 );
RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 );
RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1;
RIN_X_DATA00_intermed_1 <= RIN.X.DATA ( 0 )( 0 );
RIN_X_DATA00_intermed_2 <= RIN_X_DATA00_intermed_1;
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
DCO_DATA00_intermed_1 <= DCO.DATA ( 0 )( 0 );
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
V_X_DATA00_shadow_intermed_2 <= V_X_DATA00_shadow_intermed_1;
V_E_YMSB_shadow_intermed_1 <= V_E_YMSB_shadow;
RIN_X_DATA00_intermed_1 <= RIN.X.DATA ( 0 ) ( 0 );
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
V_X_DATA00_shadow_intermed_2 <= V_X_DATA00_shadow_intermed_1;
V_X_DATA00_shadow_intermed_3 <= V_X_DATA00_shadow_intermed_2;
R_X_DATA00_intermed_1 <= R.X.DATA ( 0 )( 0 );
RIN_X_DATA00_intermed_1 <= RIN.X.DATA( 0 )( 0 );
RIN_X_DATA00_intermed_2 <= RIN_X_DATA00_intermed_1;
RIN_X_DATA00_intermed_3 <= RIN_X_DATA00_intermed_2;
R_X_DATA00_intermed_1 <= R.X.DATA( 0 )( 0 );
R_X_DATA00_intermed_2 <= R_X_DATA00_intermed_1;
RIN_E_YMSB_intermed_1 <= RIN.E.YMSB;
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
V_X_DATA0_shadow_intermed_2 <= V_X_DATA0_shadow_intermed_1;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA ( 0 );
V_E_OP1_shadow_intermed_1 <= V_E_OP1_shadow;
RIN_E_OP1_intermed_1 <= RIN.E.OP1;
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
R_X_DATA0_intermed_1 <= R.X.DATA( 0 );
DCO_DATA0_intermed_1 <= DCO.DATA ( 0 );
RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 );
RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1;
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
V_X_DATA0_shadow_intermed_2 <= V_X_DATA0_shadow_intermed_1;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA ( 0 );
V_E_OP2_shadow_intermed_1 <= V_E_OP2_shadow;
RIN_E_OP2_intermed_1 <= RIN.E.OP2;
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
R_X_DATA0_intermed_1 <= R.X.DATA( 0 );
DCO_DATA0_intermed_1 <= DCO.DATA ( 0 );
RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 );
RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1;
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA ( 0 ) ( 4 DOWNTO 0 );
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
V_X_DATA04DOWNTO0_shadow_intermed_2 <= V_X_DATA04DOWNTO0_shadow_intermed_1;
V_X_DATA04DOWNTO0_shadow_intermed_3 <= V_X_DATA04DOWNTO0_shadow_intermed_2;
R_X_DATA04DOWNTO0_intermed_1 <= R.X.DATA( 0 )( 4 DOWNTO 0 );
R_X_DATA04DOWNTO0_intermed_2 <= R_X_DATA04DOWNTO0_intermed_1;
V_E_SHCNT_shadow_intermed_1 <= V_E_SHCNT_shadow;
R_X_DATA04DOWNTO0_intermed_1 <= R.X.DATA ( 0 )( 4 DOWNTO 0 );
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_2 <= RIN_X_DATA04DOWNTO0_intermed_1;
RIN_X_DATA04DOWNTO0_intermed_3 <= RIN_X_DATA04DOWNTO0_intermed_2;
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA ( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_2 <= RIN_X_DATA04DOWNTO0_intermed_1;
DCO_DATA04DOWNTO0_intermed_1 <= DCO.DATA ( 0 )( 4 DOWNTO 0 );
RIN_E_SHCNT_intermed_1 <= RIN.E.SHCNT;
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
V_X_DATA04DOWNTO0_shadow_intermed_2 <= V_X_DATA04DOWNTO0_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
DE_INST19_shadow_intermed_2 <= DE_INST19_shadow_intermed_1;
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
V_A_CTRL_INST20_shadow_intermed_2 <= V_A_CTRL_INST20_shadow_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_A_CTRL_INST19_shadow_intermed_3 <= V_A_CTRL_INST19_shadow_intermed_2;
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST ( 20 );
RIN_A_CTRL_INST20_intermed_2 <= RIN_A_CTRL_INST20_intermed_1;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
V_X_DATA031_shadow_intermed_3 <= V_X_DATA031_shadow_intermed_2;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_CTRL_INST19_shadow_intermed_2 <= V_E_CTRL_INST19_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
RIN_X_DATA031_intermed_3 <= RIN_X_DATA031_intermed_2;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 ) ( 31 );
V_E_SARI_shadow_intermed_1 <= V_E_SARI_shadow;
R_E_CTRL_INST19_intermed_1 <= R.E.CTRL.INST( 19 );
DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 );
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
R_X_DATA031_intermed_2 <= R_X_DATA031_intermed_1;
RIN_E_CTRL_INST20_intermed_1 <= RIN.E.CTRL.INST ( 20 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
R_E_CTRL_INST20_intermed_1 <= R.E.CTRL.INST( 20 );
R_A_CTRL_INST20_intermed_1 <= R.A.CTRL.INST ( 20 );
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST( 20 );
RIN_A_CTRL_INST20_intermed_2 <= RIN_A_CTRL_INST20_intermed_1;
RIN_A_CTRL_INST20_intermed_3 <= RIN_A_CTRL_INST20_intermed_2;
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
R_A_CTRL_INST19_intermed_2 <= R_A_CTRL_INST19_intermed_1;
V_E_CTRL_INST20_shadow_intermed_1 <= V_E_CTRL_INST20_shadow;
V_E_CTRL_INST20_shadow_intermed_2 <= V_E_CTRL_INST20_shadow_intermed_1;
V_E_CTRL_INST20_shadow_intermed_1 <= V_E_CTRL_INST20_shadow;
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST ( 19 );
DE_INST20_shadow_intermed_1 <= DE_INST20_shadow;
DE_INST20_shadow_intermed_2 <= DE_INST20_shadow_intermed_1;
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
RIN_A_CTRL_INST19_intermed_3 <= RIN_A_CTRL_INST19_intermed_2;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST ( 19 );
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
V_A_CTRL_INST20_shadow_intermed_2 <= V_A_CTRL_INST20_shadow_intermed_1;
V_A_CTRL_INST20_shadow_intermed_3 <= V_A_CTRL_INST20_shadow_intermed_2;
R_X_DATA031_intermed_1 <= R.X.DATA ( 0 )( 31 );
RIN_E_SARI_intermed_1 <= RIN.E.SARI;
RIN_E_CTRL_INST20_intermed_1 <= RIN.E.CTRL.INST( 20 );
RIN_E_CTRL_INST20_intermed_2 <= RIN_E_CTRL_INST20_intermed_1;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST( 19 );
RIN_E_CTRL_INST19_intermed_2 <= RIN_E_CTRL_INST19_intermed_1;
R_A_CTRL_INST20_intermed_1 <= R.A.CTRL.INST( 20 );
R_A_CTRL_INST20_intermed_2 <= R_A_CTRL_INST20_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_M_DCI_SIGNED_shadow_intermed_1 <= V_M_DCI_SIGNED_shadow;
V_M_DCI_SIGNED_shadow_intermed_2 <= V_M_DCI_SIGNED_shadow_intermed_1;
RIN_M_DCI_SIGNED_intermed_1 <= RIN.M.DCI.SIGNED;
RIN_M_DCI_SIGNED_intermed_2 <= RIN_M_DCI_SIGNED_intermed_1;
R_M_DCI_SIGNED_intermed_1 <= R.M.DCI.SIGNED;
V_X_DCI_SIGNED_shadow_intermed_1 <= V_X_DCI_SIGNED_shadow;
RIN_X_DCI_SIGNED_intermed_1 <= RIN.X.DCI.SIGNED;
RIN_M_DCI_SIZE_intermed_1 <= RIN.M.DCI.SIZE;
RIN_M_DCI_SIZE_intermed_2 <= RIN_M_DCI_SIZE_intermed_1;
V_M_DCI_SIZE_shadow_intermed_1 <= V_M_DCI_SIZE_shadow;
V_M_DCI_SIZE_shadow_intermed_2 <= V_M_DCI_SIZE_shadow_intermed_1;
R_M_DCI_SIZE_intermed_1 <= R.M.DCI.SIZE;
V_X_DCI_SIZE_shadow_intermed_1 <= V_X_DCI_SIZE_shadow;
RIN_X_DCI_SIZE_intermed_1 <= RIN.X.DCI.SIZE;
V_M_RESULT1DOWNTO0_shadow_intermed_1 <= V_M_RESULT1DOWNTO0_shadow;
V_M_RESULT1DOWNTO0_shadow_intermed_2 <= V_M_RESULT1DOWNTO0_shadow_intermed_1;
V_M_RESULT1DOWNTO0_shadow_intermed_3 <= V_M_RESULT1DOWNTO0_shadow_intermed_2;
RIN_X_LADDR_intermed_1 <= RIN.X.LADDR;
R_M_RESULT1DOWNTO0_intermed_1 <= R.M.RESULT ( 1 DOWNTO 0 );
RIN_M_RESULT1DOWNTO0_intermed_1 <= RIN.M.RESULT ( 1 DOWNTO 0 );
RIN_M_RESULT1DOWNTO0_intermed_2 <= RIN_M_RESULT1DOWNTO0_intermed_1;
RIN_M_RESULT1DOWNTO0_intermed_1 <= RIN.M.RESULT( 1 DOWNTO 0 );
RIN_M_RESULT1DOWNTO0_intermed_2 <= RIN_M_RESULT1DOWNTO0_intermed_1;
RIN_M_RESULT1DOWNTO0_intermed_3 <= RIN_M_RESULT1DOWNTO0_intermed_2;
V_M_RESULT1DOWNTO0_shadow_intermed_1 <= V_M_RESULT1DOWNTO0_shadow;
V_M_RESULT1DOWNTO0_shadow_intermed_2 <= V_M_RESULT1DOWNTO0_shadow_intermed_1;
V_X_LADDR_shadow_intermed_1 <= V_X_LADDR_shadow;
R_M_RESULT1DOWNTO0_intermed_1 <= R.M.RESULT( 1 DOWNTO 0 );
R_M_RESULT1DOWNTO0_intermed_2 <= R_M_RESULT1DOWNTO0_intermed_1;
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
V_X_DATA0_shadow_intermed_2 <= V_X_DATA0_shadow_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
RIN_X_RESULT_intermed_1 <= RIN.X.RESULT;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA ( 0 );
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC ( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
V_X_RESULT_shadow_intermed_1 <= V_X_RESULT_shadow;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC ( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC ( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC ( 31 DOWNTO 2 );
R_X_DATA0_intermed_1 <= R.X.DATA( 0 );
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC ( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC ( 31 DOWNTO 2 );
DCO_DATA0_intermed_1 <= DCO.DATA ( 0 );
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 );
RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
V_X_ANNUL_ALL_shadow_intermed_2 <= V_X_ANNUL_ALL_shadow_intermed_1;
V_X_ANNUL_ALL_shadow_intermed_3 <= V_X_ANNUL_ALL_shadow_intermed_2;
V_X_ANNUL_ALL_shadow_intermed_4 <= V_X_ANNUL_ALL_shadow_intermed_3;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2;
RIN_A_CTRL_ANNUL_intermed_4 <= RIN_A_CTRL_ANNUL_intermed_3;
RIN_A_CTRL_ANNUL_intermed_5 <= RIN_A_CTRL_ANNUL_intermed_4;
R_M_CTRL_WREG_intermed_1 <= R.M.CTRL.WREG;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1;
R_A_CTRL_ANNUL_intermed_3 <= R_A_CTRL_ANNUL_intermed_2;
R_A_CTRL_ANNUL_intermed_4 <= R_A_CTRL_ANNUL_intermed_3;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
RIN_X_ANNUL_ALL_intermed_3 <= RIN_X_ANNUL_ALL_intermed_2;
RIN_X_ANNUL_ALL_intermed_4 <= RIN_X_ANNUL_ALL_intermed_3;
RIN_X_ANNUL_ALL_intermed_5 <= RIN_X_ANNUL_ALL_intermed_4;
V_M_CTRL_WREG_shadow_intermed_1 <= V_M_CTRL_WREG_shadow;
V_M_CTRL_WREG_shadow_intermed_2 <= V_M_CTRL_WREG_shadow_intermed_1;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
R_X_ANNUL_ALL_intermed_2 <= R_X_ANNUL_ALL_intermed_1;
R_X_ANNUL_ALL_intermed_3 <= R_X_ANNUL_ALL_intermed_2;
R_X_ANNUL_ALL_intermed_4 <= R_X_ANNUL_ALL_intermed_3;
V_X_CTRL_WREG_shadow_intermed_1 <= V_X_CTRL_WREG_shadow;
R_E_CTRL_WREG_intermed_1 <= R.E.CTRL.WREG;
R_E_CTRL_WREG_intermed_2 <= R_E_CTRL_WREG_intermed_1;
RIN_X_CTRL_WREG_intermed_1 <= RIN.X.CTRL.WREG;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_3 <= V_A_CTRL_ANNUL_shadow_intermed_2;
V_A_CTRL_ANNUL_shadow_intermed_4 <= V_A_CTRL_ANNUL_shadow_intermed_3;
RIN_E_CTRL_WREG_intermed_1 <= RIN.E.CTRL.WREG;
RIN_E_CTRL_WREG_intermed_2 <= RIN_E_CTRL_WREG_intermed_1;
RIN_E_CTRL_WREG_intermed_3 <= RIN_E_CTRL_WREG_intermed_2;
RIN_M_CTRL_WREG_intermed_1 <= RIN.M.CTRL.WREG;
RIN_M_CTRL_WREG_intermed_2 <= RIN_M_CTRL_WREG_intermed_1;
V_E_CTRL_WREG_shadow_intermed_1 <= V_E_CTRL_WREG_shadow;
V_E_CTRL_WREG_shadow_intermed_2 <= V_E_CTRL_WREG_shadow_intermed_1;
V_E_CTRL_WREG_shadow_intermed_3 <= V_E_CTRL_WREG_shadow_intermed_2;
RIN_A_CTRL_WREG_intermed_1 <= RIN.A.CTRL.WREG;
RIN_A_CTRL_WREG_intermed_2 <= RIN_A_CTRL_WREG_intermed_1;
RIN_A_CTRL_WREG_intermed_3 <= RIN_A_CTRL_WREG_intermed_2;
RIN_A_CTRL_WREG_intermed_4 <= RIN_A_CTRL_WREG_intermed_3;
V_A_CTRL_WREG_shadow_intermed_1 <= V_A_CTRL_WREG_shadow;
V_A_CTRL_WREG_shadow_intermed_2 <= V_A_CTRL_WREG_shadow_intermed_1;
V_A_CTRL_WREG_shadow_intermed_3 <= V_A_CTRL_WREG_shadow_intermed_2;
V_A_CTRL_WREG_shadow_intermed_4 <= V_A_CTRL_WREG_shadow_intermed_3;
R_A_CTRL_WREG_intermed_1 <= R.A.CTRL.WREG;
R_A_CTRL_WREG_intermed_2 <= R_A_CTRL_WREG_intermed_1;
R_A_CTRL_WREG_intermed_3 <= R_A_CTRL_WREG_intermed_2;
V_E_CTRL_TT_shadow_intermed_1 <= V_E_CTRL_TT_shadow;
V_E_CTRL_TT_shadow_intermed_2 <= V_E_CTRL_TT_shadow_intermed_1;
V_E_CTRL_TT_shadow_intermed_3 <= V_E_CTRL_TT_shadow_intermed_2;
V_X_CTRL_TT_shadow_intermed_1 <= V_X_CTRL_TT_shadow;
V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow;
V_X_RESULT6DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO0_shadow_intermed_1;
RIN_A_CTRL_TT_intermed_1 <= RIN.A.CTRL.TT;
RIN_A_CTRL_TT_intermed_2 <= RIN_A_CTRL_TT_intermed_1;
RIN_A_CTRL_TT_intermed_3 <= RIN_A_CTRL_TT_intermed_2;
RIN_A_CTRL_TT_intermed_4 <= RIN_A_CTRL_TT_intermed_3;
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 );
RIN_X_RESULT6DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO0_intermed_1;
RIN_E_CTRL_TT_intermed_1 <= RIN.E.CTRL.TT;
RIN_E_CTRL_TT_intermed_2 <= RIN_E_CTRL_TT_intermed_1;
RIN_E_CTRL_TT_intermed_3 <= RIN_E_CTRL_TT_intermed_2;
V_M_CTRL_TT_shadow_intermed_1 <= V_M_CTRL_TT_shadow;
V_M_CTRL_TT_shadow_intermed_2 <= V_M_CTRL_TT_shadow_intermed_1;
R_X_RESULT6DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 );
R_A_CTRL_TT_intermed_1 <= R.A.CTRL.TT;
R_A_CTRL_TT_intermed_2 <= R_A_CTRL_TT_intermed_1;
R_A_CTRL_TT_intermed_3 <= R_A_CTRL_TT_intermed_2;
V_A_CTRL_TT_shadow_intermed_1 <= V_A_CTRL_TT_shadow;
V_A_CTRL_TT_shadow_intermed_2 <= V_A_CTRL_TT_shadow_intermed_1;
V_A_CTRL_TT_shadow_intermed_3 <= V_A_CTRL_TT_shadow_intermed_2;
V_A_CTRL_TT_shadow_intermed_4 <= V_A_CTRL_TT_shadow_intermed_3;
R_M_CTRL_TT_intermed_1 <= R.M.CTRL.TT;
RIN_X_CTRL_TT_intermed_1 <= RIN.X.CTRL.TT;
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 );
R_E_CTRL_TT_intermed_1 <= R.E.CTRL.TT;
R_E_CTRL_TT_intermed_2 <= R_E_CTRL_TT_intermed_1;
RIN_M_CTRL_TT_intermed_1 <= RIN.M.CTRL.TT;
RIN_M_CTRL_TT_intermed_2 <= RIN_M_CTRL_TT_intermed_1;
V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow;
V_M_CTRL_TRAP_shadow_intermed_1 <= V_M_CTRL_TRAP_shadow;
V_M_CTRL_TRAP_shadow_intermed_2 <= V_M_CTRL_TRAP_shadow_intermed_1;
RIN_X_CTRL_TRAP_intermed_1 <= RIN.X.CTRL.TRAP;
V_X_CTRL_TRAP_shadow_intermed_1 <= V_X_CTRL_TRAP_shadow;
V_A_CTRL_TRAP_shadow_intermed_1 <= V_A_CTRL_TRAP_shadow;
V_A_CTRL_TRAP_shadow_intermed_2 <= V_A_CTRL_TRAP_shadow_intermed_1;
V_A_CTRL_TRAP_shadow_intermed_3 <= V_A_CTRL_TRAP_shadow_intermed_2;
V_A_CTRL_TRAP_shadow_intermed_4 <= V_A_CTRL_TRAP_shadow_intermed_3;
V_X_MEXC_shadow_intermed_1 <= V_X_MEXC_shadow;
V_D_MEXC_shadow_intermed_1 <= V_D_MEXC_shadow;
V_D_MEXC_shadow_intermed_2 <= V_D_MEXC_shadow_intermed_1;
V_D_MEXC_shadow_intermed_3 <= V_D_MEXC_shadow_intermed_2;
V_D_MEXC_shadow_intermed_4 <= V_D_MEXC_shadow_intermed_3;
V_D_MEXC_shadow_intermed_5 <= V_D_MEXC_shadow_intermed_4;
R_A_CTRL_TRAP_intermed_1 <= R.A.CTRL.TRAP;
R_A_CTRL_TRAP_intermed_2 <= R_A_CTRL_TRAP_intermed_1;
R_A_CTRL_TRAP_intermed_3 <= R_A_CTRL_TRAP_intermed_2;
RIN_X_MEXC_intermed_1 <= RIN.X.MEXC;
RIN_M_CTRL_TRAP_intermed_1 <= RIN.M.CTRL.TRAP;
RIN_M_CTRL_TRAP_intermed_2 <= RIN_M_CTRL_TRAP_intermed_1;
R_M_CTRL_TRAP_intermed_1 <= R.M.CTRL.TRAP;
ICO_MEXC_intermed_1 <= ICO.MEXC;
ICO_MEXC_intermed_2 <= ICO_MEXC_intermed_1;
ICO_MEXC_intermed_3 <= ICO_MEXC_intermed_2;
ICO_MEXC_intermed_4 <= ICO_MEXC_intermed_3;
ICO_MEXC_intermed_5 <= ICO_MEXC_intermed_4;
R_E_CTRL_TRAP_intermed_1 <= R.E.CTRL.TRAP;
R_E_CTRL_TRAP_intermed_2 <= R_E_CTRL_TRAP_intermed_1;
RIN_A_CTRL_TRAP_intermed_1 <= RIN.A.CTRL.TRAP;
RIN_A_CTRL_TRAP_intermed_2 <= RIN_A_CTRL_TRAP_intermed_1;
RIN_A_CTRL_TRAP_intermed_3 <= RIN_A_CTRL_TRAP_intermed_2;
RIN_A_CTRL_TRAP_intermed_4 <= RIN_A_CTRL_TRAP_intermed_3;
V_E_CTRL_TRAP_shadow_intermed_1 <= V_E_CTRL_TRAP_shadow;
V_E_CTRL_TRAP_shadow_intermed_2 <= V_E_CTRL_TRAP_shadow_intermed_1;
V_E_CTRL_TRAP_shadow_intermed_3 <= V_E_CTRL_TRAP_shadow_intermed_2;
RIN_E_CTRL_TRAP_intermed_1 <= RIN.E.CTRL.TRAP;
RIN_E_CTRL_TRAP_intermed_2 <= RIN_E_CTRL_TRAP_intermed_1;
RIN_E_CTRL_TRAP_intermed_3 <= RIN_E_CTRL_TRAP_intermed_2;
RIN_D_MEXC_intermed_1 <= RIN.D.MEXC;
RIN_D_MEXC_intermed_2 <= RIN_D_MEXC_intermed_1;
RIN_D_MEXC_intermed_3 <= RIN_D_MEXC_intermed_2;
RIN_D_MEXC_intermed_4 <= RIN_D_MEXC_intermed_3;
RIN_D_MEXC_intermed_5 <= RIN_D_MEXC_intermed_4;
R_D_MEXC_intermed_1 <= R.D.MEXC;
R_D_MEXC_intermed_2 <= R_D_MEXC_intermed_1;
R_D_MEXC_intermed_3 <= R_D_MEXC_intermed_2;
R_D_MEXC_intermed_4 <= R_D_MEXC_intermed_3;
DCO_MEXC_intermed_1 <= DCO.MEXC;
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_CTRL_INST19_shadow_intermed_2 <= V_E_CTRL_INST19_shadow_intermed_1;
R_E_CTRL_INST19_intermed_1 <= R.E.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 );
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST ( 19 );
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST( 19 );
RIN_E_CTRL_INST19_intermed_2 <= RIN_E_CTRL_INST19_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
VP_ERROR_shadow_intermed_1 <= VP_ERROR_shadow;
RPIN_PWD_intermed_1 <= RPIN.PWD;
V_X_DEBUG_shadow_intermed_1 <= V_X_DEBUG_shadow;
VP_PWD_shadow_intermed_1 <= VP_PWD_shadow;
RPIN_ERROR_intermed_1 <= RPIN.ERROR;
RIN_X_DEBUG_intermed_1 <= RIN.X.DEBUG;
VP_ERROR_shadow_intermed_1 <= VP_ERROR_shadow;
RIN_X_NERROR_intermed_1 <= RIN.X.NERROR;
RPIN_ERROR_intermed_1 <= RPIN.ERROR;
V_F_PC31DOWNTO4_shadow_intermed_1 <= V_F_PC31DOWNTO4_shadow;
V_X_CTRL_TT_shadow_intermed_1 <= V_X_CTRL_TT_shadow;
V_E_CTRL_TT_shadow_intermed_1 <= V_E_CTRL_TT_shadow;
V_E_CTRL_TT_shadow_intermed_2 <= V_E_CTRL_TT_shadow_intermed_1;
V_E_CTRL_TT_shadow_intermed_3 <= V_E_CTRL_TT_shadow_intermed_2;
RIN_A_CTRL_TT_intermed_1 <= RIN.A.CTRL.TT;
RIN_A_CTRL_TT_intermed_2 <= RIN_A_CTRL_TT_intermed_1;
RIN_A_CTRL_TT_intermed_3 <= RIN_A_CTRL_TT_intermed_2;
RIN_A_CTRL_TT_intermed_4 <= RIN_A_CTRL_TT_intermed_3;
V_X_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO4_shadow;
V_X_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO4_shadow_intermed_2;
IR_ADDR31DOWNTO4_intermed_1 <= IR.ADDR( 31 DOWNTO 4 );
R_A_CTRL_TT_intermed_1 <= R.A.CTRL.TT;
R_A_CTRL_TT_intermed_2 <= R_A_CTRL_TT_intermed_1;
R_A_CTRL_TT_intermed_3 <= R_A_CTRL_TT_intermed_2;
R_M_CTRL_TT_intermed_1 <= R.M.CTRL.TT;
RIN_F_PC31DOWNTO4_intermed_1 <= RIN.F.PC( 31 DOWNTO 4 );
VIR_ADDR31DOWNTO4_shadow_intermed_1 <= VIR_ADDR31DOWNTO4_shadow;
VIR_ADDR31DOWNTO4_shadow_intermed_2 <= VIR_ADDR31DOWNTO4_shadow_intermed_1;
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 );
R_E_CTRL_TT_intermed_1 <= R.E.CTRL.TT;
R_E_CTRL_TT_intermed_2 <= R_E_CTRL_TT_intermed_1;
R_A_CTRL_PC31DOWNTO4_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 4 );
R_A_CTRL_PC31DOWNTO4_intermed_2 <= R_A_CTRL_PC31DOWNTO4_intermed_1;
R_A_CTRL_PC31DOWNTO4_intermed_3 <= R_A_CTRL_PC31DOWNTO4_intermed_2;
R_A_CTRL_PC31DOWNTO4_intermed_4 <= R_A_CTRL_PC31DOWNTO4_intermed_3;
R_A_CTRL_PC31DOWNTO4_intermed_5 <= R_A_CTRL_PC31DOWNTO4_intermed_4;
RIN_A_CTRL_PC31DOWNTO4_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 4 );
RIN_A_CTRL_PC31DOWNTO4_intermed_2 <= RIN_A_CTRL_PC31DOWNTO4_intermed_1;
RIN_A_CTRL_PC31DOWNTO4_intermed_3 <= RIN_A_CTRL_PC31DOWNTO4_intermed_2;
RIN_A_CTRL_PC31DOWNTO4_intermed_4 <= RIN_A_CTRL_PC31DOWNTO4_intermed_3;
RIN_A_CTRL_PC31DOWNTO4_intermed_5 <= RIN_A_CTRL_PC31DOWNTO4_intermed_4;
RIN_A_CTRL_PC31DOWNTO4_intermed_6 <= RIN_A_CTRL_PC31DOWNTO4_intermed_5;
R_D_PC31DOWNTO4_intermed_1 <= R.D.PC( 31 DOWNTO 4 );
R_D_PC31DOWNTO4_intermed_2 <= R_D_PC31DOWNTO4_intermed_1;
R_D_PC31DOWNTO4_intermed_3 <= R_D_PC31DOWNTO4_intermed_2;
R_D_PC31DOWNTO4_intermed_4 <= R_D_PC31DOWNTO4_intermed_3;
R_D_PC31DOWNTO4_intermed_5 <= R_D_PC31DOWNTO4_intermed_4;
R_D_PC31DOWNTO4_intermed_6 <= R_D_PC31DOWNTO4_intermed_5;
RIN_X_CTRL_PC31DOWNTO4_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 4 );
RIN_X_CTRL_PC31DOWNTO4_intermed_2 <= RIN_X_CTRL_PC31DOWNTO4_intermed_1;
RIN_X_CTRL_PC31DOWNTO4_intermed_3 <= RIN_X_CTRL_PC31DOWNTO4_intermed_2;
EX_ADD_RES32DOWNTO332DOWNTO5_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO5_shadow;
V_W_S_TBA_shadow_intermed_1 <= V_W_S_TBA_shadow;
RIN_M_CTRL_TT_intermed_1 <= RIN.M.CTRL.TT;
RIN_M_CTRL_TT_intermed_2 <= RIN_M_CTRL_TT_intermed_1;
RIN_M_CTRL_PC31DOWNTO4_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 4 );
RIN_M_CTRL_PC31DOWNTO4_intermed_2 <= RIN_M_CTRL_PC31DOWNTO4_intermed_1;
RIN_M_CTRL_PC31DOWNTO4_intermed_3 <= RIN_M_CTRL_PC31DOWNTO4_intermed_2;
RIN_M_CTRL_PC31DOWNTO4_intermed_4 <= RIN_M_CTRL_PC31DOWNTO4_intermed_3;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO4_shadow;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_4;
V_D_PC31DOWNTO4_shadow_intermed_1 <= V_D_PC31DOWNTO4_shadow;
V_D_PC31DOWNTO4_shadow_intermed_2 <= V_D_PC31DOWNTO4_shadow_intermed_1;
V_D_PC31DOWNTO4_shadow_intermed_3 <= V_D_PC31DOWNTO4_shadow_intermed_2;
V_D_PC31DOWNTO4_shadow_intermed_4 <= V_D_PC31DOWNTO4_shadow_intermed_3;
V_D_PC31DOWNTO4_shadow_intermed_5 <= V_D_PC31DOWNTO4_shadow_intermed_4;
V_D_PC31DOWNTO4_shadow_intermed_6 <= V_D_PC31DOWNTO4_shadow_intermed_5;
V_D_PC31DOWNTO4_shadow_intermed_7 <= V_D_PC31DOWNTO4_shadow_intermed_6;
V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow;
R_X_CTRL_PC31DOWNTO4_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 4 );
R_X_CTRL_PC31DOWNTO4_intermed_2 <= R_X_CTRL_PC31DOWNTO4_intermed_1;
V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow;
V_X_RESULT6DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO0_shadow_intermed_1;
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 );
RIN_X_RESULT6DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO0_intermed_1;
RIN_E_CTRL_TT_intermed_1 <= RIN.E.CTRL.TT;
RIN_E_CTRL_TT_intermed_2 <= RIN_E_CTRL_TT_intermed_1;
RIN_E_CTRL_TT_intermed_3 <= RIN_E_CTRL_TT_intermed_2;
R_X_RESULT6DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 );
V_M_CTRL_TT_shadow_intermed_1 <= V_M_CTRL_TT_shadow;
V_M_CTRL_TT_shadow_intermed_2 <= V_M_CTRL_TT_shadow_intermed_1;
IRIN_ADDR31DOWNTO4_intermed_1 <= IRIN.ADDR( 31 DOWNTO 4 );
IRIN_ADDR31DOWNTO4_intermed_2 <= IRIN_ADDR31DOWNTO4_intermed_1;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO4_shadow;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_3;
V_A_CTRL_TT_shadow_intermed_1 <= V_A_CTRL_TT_shadow;
V_A_CTRL_TT_shadow_intermed_2 <= V_A_CTRL_TT_shadow_intermed_1;
V_A_CTRL_TT_shadow_intermed_3 <= V_A_CTRL_TT_shadow_intermed_2;
V_A_CTRL_TT_shadow_intermed_4 <= V_A_CTRL_TT_shadow_intermed_3;
XC_TRAP_ADDRESS31DOWNTO4_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO4_shadow;
R_M_CTRL_PC31DOWNTO4_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 4 );
R_M_CTRL_PC31DOWNTO4_intermed_2 <= R_M_CTRL_PC31DOWNTO4_intermed_1;
R_M_CTRL_PC31DOWNTO4_intermed_3 <= R_M_CTRL_PC31DOWNTO4_intermed_2;
RIN_X_CTRL_TT_intermed_1 <= RIN.X.CTRL.TT;
RIN_D_PC31DOWNTO4_intermed_1 <= RIN.D.PC( 31 DOWNTO 4 );
RIN_D_PC31DOWNTO4_intermed_2 <= RIN_D_PC31DOWNTO4_intermed_1;
RIN_D_PC31DOWNTO4_intermed_3 <= RIN_D_PC31DOWNTO4_intermed_2;
RIN_D_PC31DOWNTO4_intermed_4 <= RIN_D_PC31DOWNTO4_intermed_3;
RIN_D_PC31DOWNTO4_intermed_5 <= RIN_D_PC31DOWNTO4_intermed_4;
RIN_D_PC31DOWNTO4_intermed_6 <= RIN_D_PC31DOWNTO4_intermed_5;
RIN_D_PC31DOWNTO4_intermed_7 <= RIN_D_PC31DOWNTO4_intermed_6;
RIN_E_CTRL_PC31DOWNTO4_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 4 );
RIN_E_CTRL_PC31DOWNTO4_intermed_2 <= RIN_E_CTRL_PC31DOWNTO4_intermed_1;
RIN_E_CTRL_PC31DOWNTO4_intermed_3 <= RIN_E_CTRL_PC31DOWNTO4_intermed_2;
RIN_E_CTRL_PC31DOWNTO4_intermed_4 <= RIN_E_CTRL_PC31DOWNTO4_intermed_3;
RIN_E_CTRL_PC31DOWNTO4_intermed_5 <= RIN_E_CTRL_PC31DOWNTO4_intermed_4;
EX_JUMP_ADDRESS31DOWNTO4_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO4_shadow;
RIN_W_S_TBA_intermed_1 <= RIN.W.S.TBA;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO4_shadow;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_5;
R_E_CTRL_PC31DOWNTO4_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 4 );
R_E_CTRL_PC31DOWNTO4_intermed_2 <= R_E_CTRL_PC31DOWNTO4_intermed_1;
R_E_CTRL_PC31DOWNTO4_intermed_3 <= R_E_CTRL_PC31DOWNTO4_intermed_2;
R_E_CTRL_PC31DOWNTO4_intermed_4 <= R_E_CTRL_PC31DOWNTO4_intermed_3;
R_D_PC3DOWNTO2_intermed_1 <= R.D.PC( 3 DOWNTO 2 );
R_D_PC3DOWNTO2_intermed_2 <= R_D_PC3DOWNTO2_intermed_1;
R_D_PC3DOWNTO2_intermed_3 <= R_D_PC3DOWNTO2_intermed_2;
R_D_PC3DOWNTO2_intermed_4 <= R_D_PC3DOWNTO2_intermed_3;
R_D_PC3DOWNTO2_intermed_5 <= R_D_PC3DOWNTO2_intermed_4;
R_D_PC3DOWNTO2_intermed_6 <= R_D_PC3DOWNTO2_intermed_5;
V_D_PC3DOWNTO2_shadow_intermed_1 <= V_D_PC3DOWNTO2_shadow;
V_D_PC3DOWNTO2_shadow_intermed_2 <= V_D_PC3DOWNTO2_shadow_intermed_1;
V_D_PC3DOWNTO2_shadow_intermed_3 <= V_D_PC3DOWNTO2_shadow_intermed_2;
V_D_PC3DOWNTO2_shadow_intermed_4 <= V_D_PC3DOWNTO2_shadow_intermed_3;
V_D_PC3DOWNTO2_shadow_intermed_5 <= V_D_PC3DOWNTO2_shadow_intermed_4;
V_D_PC3DOWNTO2_shadow_intermed_6 <= V_D_PC3DOWNTO2_shadow_intermed_5;
V_D_PC3DOWNTO2_shadow_intermed_7 <= V_D_PC3DOWNTO2_shadow_intermed_6;
VIR_ADDR3DOWNTO2_shadow_intermed_1 <= VIR_ADDR3DOWNTO2_shadow;
VIR_ADDR3DOWNTO2_shadow_intermed_2 <= VIR_ADDR3DOWNTO2_shadow_intermed_1;
RIN_D_PC3DOWNTO2_intermed_1 <= RIN.D.PC( 3 DOWNTO 2 );
RIN_D_PC3DOWNTO2_intermed_2 <= RIN_D_PC3DOWNTO2_intermed_1;
RIN_D_PC3DOWNTO2_intermed_3 <= RIN_D_PC3DOWNTO2_intermed_2;
RIN_D_PC3DOWNTO2_intermed_4 <= RIN_D_PC3DOWNTO2_intermed_3;
RIN_D_PC3DOWNTO2_intermed_5 <= RIN_D_PC3DOWNTO2_intermed_4;
RIN_D_PC3DOWNTO2_intermed_6 <= RIN_D_PC3DOWNTO2_intermed_5;
RIN_D_PC3DOWNTO2_intermed_7 <= RIN_D_PC3DOWNTO2_intermed_6;
R_M_CTRL_PC3DOWNTO2_intermed_1 <= R.M.CTRL.PC( 3 DOWNTO 2 );
R_M_CTRL_PC3DOWNTO2_intermed_2 <= R_M_CTRL_PC3DOWNTO2_intermed_1;
R_M_CTRL_PC3DOWNTO2_intermed_3 <= R_M_CTRL_PC3DOWNTO2_intermed_2;
R_E_CTRL_PC3DOWNTO2_intermed_1 <= R.E.CTRL.PC( 3 DOWNTO 2 );
R_E_CTRL_PC3DOWNTO2_intermed_2 <= R_E_CTRL_PC3DOWNTO2_intermed_1;
R_E_CTRL_PC3DOWNTO2_intermed_3 <= R_E_CTRL_PC3DOWNTO2_intermed_2;
R_E_CTRL_PC3DOWNTO2_intermed_4 <= R_E_CTRL_PC3DOWNTO2_intermed_3;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC3DOWNTO2_shadow;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_3;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_4;
RIN_X_CTRL_PC3DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 3 DOWNTO 2 );
RIN_X_CTRL_PC3DOWNTO2_intermed_2 <= RIN_X_CTRL_PC3DOWNTO2_intermed_1;
RIN_X_CTRL_PC3DOWNTO2_intermed_3 <= RIN_X_CTRL_PC3DOWNTO2_intermed_2;
R_A_CTRL_PC3DOWNTO2_intermed_1 <= R.A.CTRL.PC( 3 DOWNTO 2 );
R_A_CTRL_PC3DOWNTO2_intermed_2 <= R_A_CTRL_PC3DOWNTO2_intermed_1;
R_A_CTRL_PC3DOWNTO2_intermed_3 <= R_A_CTRL_PC3DOWNTO2_intermed_2;
R_A_CTRL_PC3DOWNTO2_intermed_4 <= R_A_CTRL_PC3DOWNTO2_intermed_3;
R_A_CTRL_PC3DOWNTO2_intermed_5 <= R_A_CTRL_PC3DOWNTO2_intermed_4;
V_X_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC3DOWNTO2_shadow;
V_X_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC3DOWNTO2_shadow_intermed_2;
RIN_M_CTRL_PC3DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 3 DOWNTO 2 );
RIN_M_CTRL_PC3DOWNTO2_intermed_2 <= RIN_M_CTRL_PC3DOWNTO2_intermed_1;
RIN_M_CTRL_PC3DOWNTO2_intermed_3 <= RIN_M_CTRL_PC3DOWNTO2_intermed_2;
RIN_M_CTRL_PC3DOWNTO2_intermed_4 <= RIN_M_CTRL_PC3DOWNTO2_intermed_3;
IRIN_ADDR3DOWNTO2_intermed_1 <= IRIN.ADDR( 3 DOWNTO 2 );
IRIN_ADDR3DOWNTO2_intermed_2 <= IRIN_ADDR3DOWNTO2_intermed_1;
EX_JUMP_ADDRESS3DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS3DOWNTO2_shadow;
EX_ADD_RES32DOWNTO34DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO34DOWNTO3_shadow;
RIN_A_CTRL_PC3DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 3 DOWNTO 2 );
RIN_A_CTRL_PC3DOWNTO2_intermed_2 <= RIN_A_CTRL_PC3DOWNTO2_intermed_1;
RIN_A_CTRL_PC3DOWNTO2_intermed_3 <= RIN_A_CTRL_PC3DOWNTO2_intermed_2;
RIN_A_CTRL_PC3DOWNTO2_intermed_4 <= RIN_A_CTRL_PC3DOWNTO2_intermed_3;
RIN_A_CTRL_PC3DOWNTO2_intermed_5 <= RIN_A_CTRL_PC3DOWNTO2_intermed_4;
RIN_A_CTRL_PC3DOWNTO2_intermed_6 <= RIN_A_CTRL_PC3DOWNTO2_intermed_5;
XC_TRAP_ADDRESS3DOWNTO2_shadow_intermed_1 <= XC_TRAP_ADDRESS3DOWNTO2_shadow;
V_F_PC3DOWNTO2_shadow_intermed_1 <= V_F_PC3DOWNTO2_shadow;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC3DOWNTO2_shadow;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_4;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_5;
IR_ADDR3DOWNTO2_intermed_1 <= IR.ADDR( 3 DOWNTO 2 );
V_M_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC3DOWNTO2_shadow;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_2;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_3;
R_X_CTRL_PC3DOWNTO2_intermed_1 <= R.X.CTRL.PC( 3 DOWNTO 2 );
R_X_CTRL_PC3DOWNTO2_intermed_2 <= R_X_CTRL_PC3DOWNTO2_intermed_1;
RIN_E_CTRL_PC3DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 3 DOWNTO 2 );
RIN_E_CTRL_PC3DOWNTO2_intermed_2 <= RIN_E_CTRL_PC3DOWNTO2_intermed_1;
RIN_E_CTRL_PC3DOWNTO2_intermed_3 <= RIN_E_CTRL_PC3DOWNTO2_intermed_2;
RIN_E_CTRL_PC3DOWNTO2_intermed_4 <= RIN_E_CTRL_PC3DOWNTO2_intermed_3;
RIN_E_CTRL_PC3DOWNTO2_intermed_5 <= RIN_E_CTRL_PC3DOWNTO2_intermed_4;
RIN_F_PC3DOWNTO2_intermed_1 <= RIN.F.PC( 3 DOWNTO 2 );
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_DEBUG_intermed_1 <= RIN.X.DEBUG;
RIN_D_PC_intermed_1 <= RIN.D.PC;
RIN_D_PC_intermed_2 <= RIN_D_PC_intermed_1;
RIN_D_PC_intermed_3 <= RIN_D_PC_intermed_2;
RIN_D_PC_intermed_4 <= RIN_D_PC_intermed_3;
RIN_D_PC_intermed_5 <= RIN_D_PC_intermed_4;
RIN_A_CTRL_PC_intermed_1 <= RIN.A.CTRL.PC;
RIN_A_CTRL_PC_intermed_2 <= RIN_A_CTRL_PC_intermed_1;
RIN_A_CTRL_PC_intermed_3 <= RIN_A_CTRL_PC_intermed_2;
RIN_A_CTRL_PC_intermed_4 <= RIN_A_CTRL_PC_intermed_3;
R_A_CTRL_PC_intermed_1 <= R.A.CTRL.PC;
R_A_CTRL_PC_intermed_2 <= R_A_CTRL_PC_intermed_1;
R_A_CTRL_PC_intermed_3 <= R_A_CTRL_PC_intermed_2;
V_E_CTRL_PC_shadow_intermed_1 <= V_E_CTRL_PC_shadow;
V_E_CTRL_PC_shadow_intermed_2 <= V_E_CTRL_PC_shadow_intermed_1;
V_E_CTRL_PC_shadow_intermed_3 <= V_E_CTRL_PC_shadow_intermed_2;
R_M_CTRL_PC_intermed_1 <= R.M.CTRL.PC;
R_E_CTRL_PC_intermed_1 <= R.E.CTRL.PC;
R_E_CTRL_PC_intermed_2 <= R_E_CTRL_PC_intermed_1;
RIN_M_CTRL_PC_intermed_1 <= RIN.M.CTRL.PC;
RIN_M_CTRL_PC_intermed_2 <= RIN_M_CTRL_PC_intermed_1;
V_X_CTRL_PC_shadow_intermed_1 <= V_X_CTRL_PC_shadow;
V_M_CTRL_PC_shadow_intermed_1 <= V_M_CTRL_PC_shadow;
V_M_CTRL_PC_shadow_intermed_2 <= V_M_CTRL_PC_shadow_intermed_1;
V_A_CTRL_PC_shadow_intermed_1 <= V_A_CTRL_PC_shadow;
V_A_CTRL_PC_shadow_intermed_2 <= V_A_CTRL_PC_shadow_intermed_1;
V_A_CTRL_PC_shadow_intermed_3 <= V_A_CTRL_PC_shadow_intermed_2;
V_A_CTRL_PC_shadow_intermed_4 <= V_A_CTRL_PC_shadow_intermed_3;
R_D_PC_intermed_1 <= R.D.PC;
R_D_PC_intermed_2 <= R_D_PC_intermed_1;
R_D_PC_intermed_3 <= R_D_PC_intermed_2;
R_D_PC_intermed_4 <= R_D_PC_intermed_3;
RIN_E_CTRL_PC_intermed_1 <= RIN.E.CTRL.PC;
RIN_E_CTRL_PC_intermed_2 <= RIN_E_CTRL_PC_intermed_1;
RIN_E_CTRL_PC_intermed_3 <= RIN_E_CTRL_PC_intermed_2;
RIN_X_CTRL_PC_intermed_1 <= RIN.X.CTRL.PC;
V_D_PC_shadow_intermed_1 <= V_D_PC_shadow;
V_D_PC_shadow_intermed_2 <= V_D_PC_shadow_intermed_1;
V_D_PC_shadow_intermed_3 <= V_D_PC_shadow_intermed_2;
V_D_PC_shadow_intermed_4 <= V_D_PC_shadow_intermed_3;
V_D_PC_shadow_intermed_5 <= V_D_PC_shadow_intermed_4;
IRIN_ADDR_intermed_1 <= IRIN.ADDR;
V_E_CTRL_TT_shadow_intermed_1 <= V_E_CTRL_TT_shadow;
V_E_CTRL_TT_shadow_intermed_2 <= V_E_CTRL_TT_shadow_intermed_1;
V_E_CTRL_TT_shadow_intermed_3 <= V_E_CTRL_TT_shadow_intermed_2;
V_X_CTRL_TT_shadow_intermed_1 <= V_X_CTRL_TT_shadow;
RIN_A_CTRL_TT_intermed_1 <= RIN.A.CTRL.TT;
RIN_A_CTRL_TT_intermed_2 <= RIN_A_CTRL_TT_intermed_1;
RIN_A_CTRL_TT_intermed_3 <= RIN_A_CTRL_TT_intermed_2;
RIN_A_CTRL_TT_intermed_4 <= RIN_A_CTRL_TT_intermed_3;
R_A_CTRL_TT_intermed_1 <= R.A.CTRL.TT;
R_A_CTRL_TT_intermed_2 <= R_A_CTRL_TT_intermed_1;
R_A_CTRL_TT_intermed_3 <= R_A_CTRL_TT_intermed_2;
R_M_CTRL_TT_intermed_1 <= R.M.CTRL.TT;
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 );
DSUIN_TT_intermed_1 <= DSUIN.TT;
R_E_CTRL_TT_intermed_1 <= R.E.CTRL.TT;
R_E_CTRL_TT_intermed_2 <= R_E_CTRL_TT_intermed_1;
RIN_M_CTRL_TT_intermed_1 <= RIN.M.CTRL.TT;
RIN_M_CTRL_TT_intermed_2 <= RIN_M_CTRL_TT_intermed_1;
V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow;
V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow;
V_X_RESULT6DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO0_shadow_intermed_1;
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 );
RIN_X_RESULT6DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO0_intermed_1;
RIN_E_CTRL_TT_intermed_1 <= RIN.E.CTRL.TT;
RIN_E_CTRL_TT_intermed_2 <= RIN_E_CTRL_TT_intermed_1;
RIN_E_CTRL_TT_intermed_3 <= RIN_E_CTRL_TT_intermed_2;
V_M_CTRL_TT_shadow_intermed_1 <= V_M_CTRL_TT_shadow;
V_M_CTRL_TT_shadow_intermed_2 <= V_M_CTRL_TT_shadow_intermed_1;
R_X_RESULT6DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 );
V_A_CTRL_TT_shadow_intermed_1 <= V_A_CTRL_TT_shadow;
V_A_CTRL_TT_shadow_intermed_2 <= V_A_CTRL_TT_shadow_intermed_1;
V_A_CTRL_TT_shadow_intermed_3 <= V_A_CTRL_TT_shadow_intermed_2;
V_A_CTRL_TT_shadow_intermed_4 <= V_A_CTRL_TT_shadow_intermed_3;
RIN_X_CTRL_TT_intermed_1 <= RIN.X.CTRL.TT;
RPIN_PWD_intermed_1 <= RPIN.PWD;
IRIN_PWD_intermed_1 <= IRIN.PWD;
V_E_CTRL_TT_shadow_intermed_1 <= V_E_CTRL_TT_shadow;
V_E_CTRL_TT_shadow_intermed_2 <= V_E_CTRL_TT_shadow_intermed_1;
V_E_CTRL_TT_shadow_intermed_3 <= V_E_CTRL_TT_shadow_intermed_2;
V_X_CTRL_TT_shadow_intermed_1 <= V_X_CTRL_TT_shadow;
RIN_A_CTRL_TT_intermed_1 <= RIN.A.CTRL.TT;
RIN_A_CTRL_TT_intermed_2 <= RIN_A_CTRL_TT_intermed_1;
RIN_A_CTRL_TT_intermed_3 <= RIN_A_CTRL_TT_intermed_2;
RIN_A_CTRL_TT_intermed_4 <= RIN_A_CTRL_TT_intermed_3;
R_A_CTRL_TT_intermed_1 <= R.A.CTRL.TT;
R_A_CTRL_TT_intermed_2 <= R_A_CTRL_TT_intermed_1;
R_A_CTRL_TT_intermed_3 <= R_A_CTRL_TT_intermed_2;
R_M_CTRL_TT_intermed_1 <= R.M.CTRL.TT;
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 );
R_E_CTRL_TT_intermed_1 <= R.E.CTRL.TT;
R_E_CTRL_TT_intermed_2 <= R_E_CTRL_TT_intermed_1;
RIN_M_CTRL_TT_intermed_1 <= RIN.M.CTRL.TT;
RIN_M_CTRL_TT_intermed_2 <= RIN_M_CTRL_TT_intermed_1;
V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow;
V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow;
V_X_RESULT6DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO0_shadow_intermed_1;
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 );
RIN_X_RESULT6DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO0_intermed_1;
RIN_E_CTRL_TT_intermed_1 <= RIN.E.CTRL.TT;
RIN_E_CTRL_TT_intermed_2 <= RIN_E_CTRL_TT_intermed_1;
RIN_E_CTRL_TT_intermed_3 <= RIN_E_CTRL_TT_intermed_2;
V_M_CTRL_TT_shadow_intermed_1 <= V_M_CTRL_TT_shadow;
V_M_CTRL_TT_shadow_intermed_2 <= V_M_CTRL_TT_shadow_intermed_1;
R_X_RESULT6DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 );
RIN_W_S_TT_intermed_1 <= RIN.W.S.TT;
V_A_CTRL_TT_shadow_intermed_1 <= V_A_CTRL_TT_shadow;
V_A_CTRL_TT_shadow_intermed_2 <= V_A_CTRL_TT_shadow_intermed_1;
V_A_CTRL_TT_shadow_intermed_3 <= V_A_CTRL_TT_shadow_intermed_2;
V_A_CTRL_TT_shadow_intermed_4 <= V_A_CTRL_TT_shadow_intermed_3;
RIN_X_CTRL_TT_intermed_1 <= RIN.X.CTRL.TT;
RIN_W_S_S_intermed_1 <= RIN.W.S.S;
RIN_W_S_PS_intermed_1 <= RIN.W.S.PS;
V_W_S_S_shadow_intermed_1 <= V_W_S_S_shadow;
RIN_W_S_S_intermed_1 <= RIN.W.S.S;
RIN_E_CTRL_RD6DOWNTO0_intermed_1 <= RIN.E.CTRL.RD( 6 DOWNTO 0 );
RIN_E_CTRL_RD6DOWNTO0_intermed_2 <= RIN_E_CTRL_RD6DOWNTO0_intermed_1;
RIN_E_CTRL_RD6DOWNTO0_intermed_3 <= RIN_E_CTRL_RD6DOWNTO0_intermed_2;
RIN_M_CTRL_RD6DOWNTO0_intermed_1 <= RIN.M.CTRL.RD( 6 DOWNTO 0 );
RIN_M_CTRL_RD6DOWNTO0_intermed_2 <= RIN_M_CTRL_RD6DOWNTO0_intermed_1;
RIN_X_CTRL_RD6DOWNTO0_intermed_1 <= RIN.X.CTRL.RD( 6 DOWNTO 0 );
V_X_CTRL_RD6DOWNTO0_shadow_intermed_1 <= V_X_CTRL_RD6DOWNTO0_shadow;
RIN_W_S_CWP_intermed_1 <= RIN.W.S.CWP;
V_M_CTRL_RD6DOWNTO0_shadow_intermed_1 <= V_M_CTRL_RD6DOWNTO0_shadow;
V_M_CTRL_RD6DOWNTO0_shadow_intermed_2 <= V_M_CTRL_RD6DOWNTO0_shadow_intermed_1;
R_E_CTRL_RD6DOWNTO0_intermed_1 <= R.E.CTRL.RD( 6 DOWNTO 0 );
R_E_CTRL_RD6DOWNTO0_intermed_2 <= R_E_CTRL_RD6DOWNTO0_intermed_1;
V_E_CTRL_RD6DOWNTO0_shadow_intermed_1 <= V_E_CTRL_RD6DOWNTO0_shadow;
V_E_CTRL_RD6DOWNTO0_shadow_intermed_2 <= V_E_CTRL_RD6DOWNTO0_shadow_intermed_1;
V_E_CTRL_RD6DOWNTO0_shadow_intermed_3 <= V_E_CTRL_RD6DOWNTO0_shadow_intermed_2;
V_A_CTRL_RD6DOWNTO0_shadow_intermed_1 <= V_A_CTRL_RD6DOWNTO0_shadow;
V_A_CTRL_RD6DOWNTO0_shadow_intermed_2 <= V_A_CTRL_RD6DOWNTO0_shadow_intermed_1;
V_A_CTRL_RD6DOWNTO0_shadow_intermed_3 <= V_A_CTRL_RD6DOWNTO0_shadow_intermed_2;
V_A_CTRL_RD6DOWNTO0_shadow_intermed_4 <= V_A_CTRL_RD6DOWNTO0_shadow_intermed_3;
R_A_CTRL_RD6DOWNTO0_intermed_1 <= R.A.CTRL.RD( 6 DOWNTO 0 );
R_A_CTRL_RD6DOWNTO0_intermed_2 <= R_A_CTRL_RD6DOWNTO0_intermed_1;
R_A_CTRL_RD6DOWNTO0_intermed_3 <= R_A_CTRL_RD6DOWNTO0_intermed_2;
RIN_A_CTRL_RD6DOWNTO0_intermed_1 <= RIN.A.CTRL.RD( 6 DOWNTO 0 );
RIN_A_CTRL_RD6DOWNTO0_intermed_2 <= RIN_A_CTRL_RD6DOWNTO0_intermed_1;
RIN_A_CTRL_RD6DOWNTO0_intermed_3 <= RIN_A_CTRL_RD6DOWNTO0_intermed_2;
RIN_A_CTRL_RD6DOWNTO0_intermed_4 <= RIN_A_CTRL_RD6DOWNTO0_intermed_3;
R_M_CTRL_RD6DOWNTO0_intermed_1 <= R.M.CTRL.RD( 6 DOWNTO 0 );
V_W_S_CWP_shadow_intermed_1 <= V_W_S_CWP_shadow;
RIN_W_S_ET_intermed_1 <= RIN.W.S.ET;
RIN_W_S_CWP_intermed_1 <= RIN.W.S.CWP;
RPIN_ERROR_intermed_1 <= RPIN.ERROR;
RIN_D_PC_intermed_1 <= RIN.D.PC;
RIN_D_PC_intermed_2 <= RIN_D_PC_intermed_1;
RIN_D_PC_intermed_3 <= RIN_D_PC_intermed_2;
RIN_D_PC_intermed_4 <= RIN_D_PC_intermed_3;
RIN_D_PC_intermed_5 <= RIN_D_PC_intermed_4;
RIN_D_PC_intermed_6 <= RIN_D_PC_intermed_5;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_4 <= RIN_M_CTRL_PC31DOWNTO2_intermed_3;
VIR_ADDR_shadow_intermed_1 <= VIR_ADDR_shadow;
RIN_A_CTRL_PC_intermed_1 <= RIN.A.CTRL.PC;
RIN_A_CTRL_PC_intermed_2 <= RIN_A_CTRL_PC_intermed_1;
RIN_A_CTRL_PC_intermed_3 <= RIN_A_CTRL_PC_intermed_2;
RIN_A_CTRL_PC_intermed_4 <= RIN_A_CTRL_PC_intermed_3;
RIN_A_CTRL_PC_intermed_5 <= RIN_A_CTRL_PC_intermed_4;
R_A_CTRL_PC_intermed_1 <= R.A.CTRL.PC;
R_A_CTRL_PC_intermed_2 <= R_A_CTRL_PC_intermed_1;
R_A_CTRL_PC_intermed_3 <= R_A_CTRL_PC_intermed_2;
R_A_CTRL_PC_intermed_4 <= R_A_CTRL_PC_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
V_D_PC31DOWNTO2_shadow_intermed_6 <= V_D_PC31DOWNTO2_shadow_intermed_5;
V_D_PC31DOWNTO2_shadow_intermed_7 <= V_D_PC31DOWNTO2_shadow_intermed_6;
V_E_CTRL_PC_shadow_intermed_1 <= V_E_CTRL_PC_shadow;
V_E_CTRL_PC_shadow_intermed_2 <= V_E_CTRL_PC_shadow_intermed_1;
V_E_CTRL_PC_shadow_intermed_3 <= V_E_CTRL_PC_shadow_intermed_2;
V_E_CTRL_PC_shadow_intermed_4 <= V_E_CTRL_PC_shadow_intermed_3;
EX_ADD_RES32DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO3_shadow;
XC_TRAP_ADDRESS_shadow_intermed_1 <= XC_TRAP_ADDRESS_shadow;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_D_PC31DOWNTO2_intermed_6 <= RIN_D_PC31DOWNTO2_intermed_5;
RIN_D_PC31DOWNTO2_intermed_7 <= RIN_D_PC31DOWNTO2_intermed_6;
EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow;
V_F_PC31DOWNTO2_shadow_intermed_1 <= V_F_PC31DOWNTO2_shadow;
RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC( 31 DOWNTO 2 );
R_M_CTRL_PC_intermed_1 <= R.M.CTRL.PC;
R_M_CTRL_PC_intermed_2 <= R_M_CTRL_PC_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_3 <= RIN_X_CTRL_PC31DOWNTO2_intermed_2;
R_X_CTRL_PC_intermed_1 <= R.X.CTRL.PC;
R_E_CTRL_PC_intermed_1 <= R.E.CTRL.PC;
R_E_CTRL_PC_intermed_2 <= R_E_CTRL_PC_intermed_1;
R_E_CTRL_PC_intermed_3 <= R_E_CTRL_PC_intermed_2;
IRIN_ADDR31DOWNTO2_intermed_1 <= IRIN.ADDR( 31 DOWNTO 2 );
IRIN_ADDR31DOWNTO2_intermed_2 <= IRIN_ADDR31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_5;
RIN_M_CTRL_PC_intermed_1 <= RIN.M.CTRL.PC;
RIN_M_CTRL_PC_intermed_2 <= RIN_M_CTRL_PC_intermed_1;
RIN_M_CTRL_PC_intermed_3 <= RIN_M_CTRL_PC_intermed_2;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_D_PC31DOWNTO2_intermed_5 <= R_D_PC31DOWNTO2_intermed_4;
R_D_PC31DOWNTO2_intermed_6 <= R_D_PC31DOWNTO2_intermed_5;
VIR_ADDR31DOWNTO2_shadow_intermed_1 <= VIR_ADDR31DOWNTO2_shadow;
VIR_ADDR31DOWNTO2_shadow_intermed_2 <= VIR_ADDR31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC_shadow_intermed_1 <= V_X_CTRL_PC_shadow;
V_X_CTRL_PC_shadow_intermed_2 <= V_X_CTRL_PC_shadow_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_3 <= R_M_CTRL_PC31DOWNTO2_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_6 <= RIN_A_CTRL_PC31DOWNTO2_intermed_5;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
R_A_CTRL_PC31DOWNTO2_intermed_5 <= R_A_CTRL_PC31DOWNTO2_intermed_4;
V_M_CTRL_PC_shadow_intermed_1 <= V_M_CTRL_PC_shadow;
V_M_CTRL_PC_shadow_intermed_2 <= V_M_CTRL_PC_shadow_intermed_1;
V_M_CTRL_PC_shadow_intermed_3 <= V_M_CTRL_PC_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC_shadow_intermed_1 <= V_A_CTRL_PC_shadow;
V_A_CTRL_PC_shadow_intermed_2 <= V_A_CTRL_PC_shadow_intermed_1;
V_A_CTRL_PC_shadow_intermed_3 <= V_A_CTRL_PC_shadow_intermed_2;
V_A_CTRL_PC_shadow_intermed_4 <= V_A_CTRL_PC_shadow_intermed_3;
V_A_CTRL_PC_shadow_intermed_5 <= V_A_CTRL_PC_shadow_intermed_4;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
R_X_CTRL_PC31DOWNTO2_intermed_2 <= R_X_CTRL_PC31DOWNTO2_intermed_1;
R_D_PC_intermed_1 <= R.D.PC;
R_D_PC_intermed_2 <= R_D_PC_intermed_1;
R_D_PC_intermed_3 <= R_D_PC_intermed_2;
R_D_PC_intermed_4 <= R_D_PC_intermed_3;
R_D_PC_intermed_5 <= R_D_PC_intermed_4;
RIN_F_PC_intermed_1 <= RIN.F.PC;
XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO2_shadow;
RIN_E_CTRL_PC_intermed_1 <= RIN.E.CTRL.PC;
RIN_E_CTRL_PC_intermed_2 <= RIN_E_CTRL_PC_intermed_1;
RIN_E_CTRL_PC_intermed_3 <= RIN_E_CTRL_PC_intermed_2;
RIN_E_CTRL_PC_intermed_4 <= RIN_E_CTRL_PC_intermed_3;
RIN_X_CTRL_PC_intermed_1 <= RIN.X.CTRL.PC;
RIN_X_CTRL_PC_intermed_2 <= RIN_X_CTRL_PC_intermed_1;
V_D_PC_shadow_intermed_1 <= V_D_PC_shadow;
V_D_PC_shadow_intermed_2 <= V_D_PC_shadow_intermed_1;
V_D_PC_shadow_intermed_3 <= V_D_PC_shadow_intermed_2;
V_D_PC_shadow_intermed_4 <= V_D_PC_shadow_intermed_3;
V_D_PC_shadow_intermed_5 <= V_D_PC_shadow_intermed_4;
V_D_PC_shadow_intermed_6 <= V_D_PC_shadow_intermed_5;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_4 <= R_E_CTRL_PC31DOWNTO2_intermed_3;
IRIN_ADDR_intermed_1 <= IRIN.ADDR;
EX_JUMP_ADDRESS_shadow_intermed_1 <= EX_JUMP_ADDRESS_shadow;
EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO2_shadow;
IR_ADDR31DOWNTO2_intermed_1 <= IR.ADDR( 31 DOWNTO 2 );
V_F_PC_shadow_intermed_1 <= V_F_PC_shadow;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_5 <= RIN_E_CTRL_PC31DOWNTO2_intermed_4;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_2;
DSUIN_TBUFCNT_intermed_1 <= DSUIN.TBUFCNT;
RIN_W_EXCEPT_intermed_1 <= RIN.W.EXCEPT;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_X_RESULT_intermed_1 <= RIN.X.RESULT;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC ( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC ( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC ( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC ( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC ( 31 DOWNTO 2 );
DCO_DATA0_intermed_1 <= DCO.DATA ( 0 );
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
V_X_DATA0_shadow_intermed_2 <= V_X_DATA0_shadow_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA ( 0 );
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC ( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
V_X_RESULT_shadow_intermed_1 <= V_X_RESULT_shadow;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
RIN_W_RESULT_intermed_1 <= RIN.W.RESULT;
R_X_DATA0_intermed_1 <= R.X.DATA( 0 );
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 );
RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1;
V_M_CTRL_RD7DOWNTO0_shadow_intermed_1 <= V_M_CTRL_RD7DOWNTO0_shadow;
V_M_CTRL_RD7DOWNTO0_shadow_intermed_2 <= V_M_CTRL_RD7DOWNTO0_shadow_intermed_1;
V_E_CTRL_RD7DOWNTO0_shadow_intermed_1 <= V_E_CTRL_RD7DOWNTO0_shadow;
V_E_CTRL_RD7DOWNTO0_shadow_intermed_2 <= V_E_CTRL_RD7DOWNTO0_shadow_intermed_1;
V_E_CTRL_RD7DOWNTO0_shadow_intermed_3 <= V_E_CTRL_RD7DOWNTO0_shadow_intermed_2;
R_E_CTRL_RD7DOWNTO0_intermed_1 <= R.E.CTRL.RD ( 7 DOWNTO 0 );
R_E_CTRL_RD7DOWNTO0_intermed_2 <= R_E_CTRL_RD7DOWNTO0_intermed_1;
V_X_CTRL_RD7DOWNTO0_shadow_intermed_1 <= V_X_CTRL_RD7DOWNTO0_shadow;
V_A_CTRL_RD7DOWNTO0_shadow_intermed_1 <= V_A_CTRL_RD7DOWNTO0_shadow;
V_A_CTRL_RD7DOWNTO0_shadow_intermed_2 <= V_A_CTRL_RD7DOWNTO0_shadow_intermed_1;
V_A_CTRL_RD7DOWNTO0_shadow_intermed_3 <= V_A_CTRL_RD7DOWNTO0_shadow_intermed_2;
V_A_CTRL_RD7DOWNTO0_shadow_intermed_4 <= V_A_CTRL_RD7DOWNTO0_shadow_intermed_3;
RIN_W_WA_intermed_1 <= RIN.W.WA;
RIN_A_CTRL_RD7DOWNTO0_intermed_1 <= RIN.A.CTRL.RD ( 7 DOWNTO 0 );
RIN_A_CTRL_RD7DOWNTO0_intermed_2 <= RIN_A_CTRL_RD7DOWNTO0_intermed_1;
RIN_A_CTRL_RD7DOWNTO0_intermed_3 <= RIN_A_CTRL_RD7DOWNTO0_intermed_2;
RIN_A_CTRL_RD7DOWNTO0_intermed_4 <= RIN_A_CTRL_RD7DOWNTO0_intermed_3;
R_M_CTRL_RD7DOWNTO0_intermed_1 <= R.M.CTRL.RD ( 7 DOWNTO 0 );
R_A_CTRL_RD7DOWNTO0_intermed_1 <= R.A.CTRL.RD ( 7 DOWNTO 0 );
R_A_CTRL_RD7DOWNTO0_intermed_2 <= R_A_CTRL_RD7DOWNTO0_intermed_1;
R_A_CTRL_RD7DOWNTO0_intermed_3 <= R_A_CTRL_RD7DOWNTO0_intermed_2;
RIN_E_CTRL_RD7DOWNTO0_intermed_1 <= RIN.E.CTRL.RD ( 7 DOWNTO 0 );
RIN_E_CTRL_RD7DOWNTO0_intermed_2 <= RIN_E_CTRL_RD7DOWNTO0_intermed_1;
RIN_E_CTRL_RD7DOWNTO0_intermed_3 <= RIN_E_CTRL_RD7DOWNTO0_intermed_2;
RIN_X_CTRL_RD7DOWNTO0_intermed_1 <= RIN.X.CTRL.RD ( 7 DOWNTO 0 );
RIN_M_CTRL_RD7DOWNTO0_intermed_1 <= RIN.M.CTRL.RD ( 7 DOWNTO 0 );
RIN_M_CTRL_RD7DOWNTO0_intermed_2 <= RIN_M_CTRL_RD7DOWNTO0_intermed_1;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2;
RIN_A_CTRL_ANNUL_intermed_4 <= RIN_A_CTRL_ANNUL_intermed_3;
RIN_A_CTRL_ANNUL_intermed_5 <= RIN_A_CTRL_ANNUL_intermed_4;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1;
R_A_CTRL_ANNUL_intermed_3 <= R_A_CTRL_ANNUL_intermed_2;
R_A_CTRL_ANNUL_intermed_4 <= R_A_CTRL_ANNUL_intermed_3;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
R_X_ANNUL_ALL_intermed_2 <= R_X_ANNUL_ALL_intermed_1;
R_X_ANNUL_ALL_intermed_3 <= R_X_ANNUL_ALL_intermed_2;
R_X_ANNUL_ALL_intermed_4 <= R_X_ANNUL_ALL_intermed_3;
V_X_CTRL_WREG_shadow_intermed_1 <= V_X_CTRL_WREG_shadow;
RIN_X_CTRL_WREG_intermed_1 <= RIN.X.CTRL.WREG;
RIN_M_CTRL_WREG_intermed_1 <= RIN.M.CTRL.WREG;
RIN_M_CTRL_WREG_intermed_2 <= RIN_M_CTRL_WREG_intermed_1;
RIN_A_CTRL_WREG_intermed_1 <= RIN.A.CTRL.WREG;
RIN_A_CTRL_WREG_intermed_2 <= RIN_A_CTRL_WREG_intermed_1;
RIN_A_CTRL_WREG_intermed_3 <= RIN_A_CTRL_WREG_intermed_2;
RIN_A_CTRL_WREG_intermed_4 <= RIN_A_CTRL_WREG_intermed_3;
V_A_CTRL_WREG_shadow_intermed_1 <= V_A_CTRL_WREG_shadow;
V_A_CTRL_WREG_shadow_intermed_2 <= V_A_CTRL_WREG_shadow_intermed_1;
V_A_CTRL_WREG_shadow_intermed_3 <= V_A_CTRL_WREG_shadow_intermed_2;
V_A_CTRL_WREG_shadow_intermed_4 <= V_A_CTRL_WREG_shadow_intermed_3;
R_A_CTRL_WREG_intermed_1 <= R.A.CTRL.WREG;
R_A_CTRL_WREG_intermed_2 <= R_A_CTRL_WREG_intermed_1;
R_A_CTRL_WREG_intermed_3 <= R_A_CTRL_WREG_intermed_2;
RIN_W_WREG_intermed_1 <= RIN.W.WREG;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
V_X_ANNUL_ALL_shadow_intermed_2 <= V_X_ANNUL_ALL_shadow_intermed_1;
V_X_ANNUL_ALL_shadow_intermed_3 <= V_X_ANNUL_ALL_shadow_intermed_2;
V_X_ANNUL_ALL_shadow_intermed_4 <= V_X_ANNUL_ALL_shadow_intermed_3;
R_M_CTRL_WREG_intermed_1 <= R.M.CTRL.WREG;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
RIN_X_ANNUL_ALL_intermed_3 <= RIN_X_ANNUL_ALL_intermed_2;
RIN_X_ANNUL_ALL_intermed_4 <= RIN_X_ANNUL_ALL_intermed_3;
RIN_X_ANNUL_ALL_intermed_5 <= RIN_X_ANNUL_ALL_intermed_4;
V_M_CTRL_WREG_shadow_intermed_1 <= V_M_CTRL_WREG_shadow;
V_M_CTRL_WREG_shadow_intermed_2 <= V_M_CTRL_WREG_shadow_intermed_1;
R_E_CTRL_WREG_intermed_1 <= R.E.CTRL.WREG;
R_E_CTRL_WREG_intermed_2 <= R_E_CTRL_WREG_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_3 <= V_A_CTRL_ANNUL_shadow_intermed_2;
V_A_CTRL_ANNUL_shadow_intermed_4 <= V_A_CTRL_ANNUL_shadow_intermed_3;
RIN_E_CTRL_WREG_intermed_1 <= RIN.E.CTRL.WREG;
RIN_E_CTRL_WREG_intermed_2 <= RIN_E_CTRL_WREG_intermed_1;
RIN_E_CTRL_WREG_intermed_3 <= RIN_E_CTRL_WREG_intermed_2;
V_E_CTRL_WREG_shadow_intermed_1 <= V_E_CTRL_WREG_shadow;
V_E_CTRL_WREG_shadow_intermed_2 <= V_E_CTRL_WREG_shadow_intermed_1;
V_E_CTRL_WREG_shadow_intermed_3 <= V_E_CTRL_WREG_shadow_intermed_2;
RIN_W_S_SVT_intermed_1 <= RIN.W.S.SVT;
RIN_W_S_DWT_intermed_1 <= RIN.W.S.DWT;
RIN_W_S_EF_intermed_1 <= RIN.W.S.EF;
RIN_E_CTRL_intermed_1 <= RIN.E.CTRL;
RIN_E_CTRL_intermed_2 <= RIN_E_CTRL_intermed_1;
R_E_CTRL_intermed_1 <= R.E.CTRL;
RIN_X_CTRL_intermed_1 <= RIN.X.CTRL;
RIN_M_CTRL_intermed_1 <= RIN.M.CTRL;
V_E_CTRL_shadow_intermed_1 <= V_E_CTRL_shadow;
V_E_CTRL_shadow_intermed_2 <= V_E_CTRL_shadow_intermed_1;
RIN_A_CTRL_intermed_1 <= RIN.A.CTRL;
RIN_A_CTRL_intermed_2 <= RIN_A_CTRL_intermed_1;
RIN_A_CTRL_intermed_3 <= RIN_A_CTRL_intermed_2;
V_M_CTRL_shadow_intermed_1 <= V_M_CTRL_shadow;
V_A_CTRL_shadow_intermed_1 <= V_A_CTRL_shadow;
V_A_CTRL_shadow_intermed_2 <= V_A_CTRL_shadow_intermed_1;
V_A_CTRL_shadow_intermed_3 <= V_A_CTRL_shadow_intermed_2;
R_A_CTRL_intermed_1 <= R.A.CTRL;
R_A_CTRL_intermed_2 <= R_A_CTRL_intermed_1;
V_M_DCI_shadow_intermed_1 <= V_M_DCI_shadow;
RIN_M_DCI_intermed_1 <= RIN.M.DCI;
RIN_X_DCI_intermed_1 <= RIN.X.DCI;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2;
RIN_A_CTRL_ANNUL_intermed_4 <= RIN_A_CTRL_ANNUL_intermed_3;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1;
R_A_CTRL_ANNUL_intermed_3 <= R_A_CTRL_ANNUL_intermed_2;
RIN_M_CTRL_RETT_intermed_1 <= RIN.M.CTRL.RETT;
V_M_CTRL_ANNUL_shadow_intermed_1 <= V_M_CTRL_ANNUL_shadow;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
R_X_ANNUL_ALL_intermed_2 <= R_X_ANNUL_ALL_intermed_1;
R_X_ANNUL_ALL_intermed_3 <= R_X_ANNUL_ALL_intermed_2;
RIN_M_CTRL_ANNUL_intermed_1 <= RIN.M.CTRL.ANNUL;
V_E_CTRL_RETT_shadow_intermed_1 <= V_E_CTRL_RETT_shadow;
V_E_CTRL_RETT_shadow_intermed_2 <= V_E_CTRL_RETT_shadow_intermed_1;
V_A_CTRL_RETT_shadow_intermed_1 <= V_A_CTRL_RETT_shadow;
V_A_CTRL_RETT_shadow_intermed_2 <= V_A_CTRL_RETT_shadow_intermed_1;
V_A_CTRL_RETT_shadow_intermed_3 <= V_A_CTRL_RETT_shadow_intermed_2;
RIN_A_CTRL_RETT_intermed_1 <= RIN.A.CTRL.RETT;
RIN_A_CTRL_RETT_intermed_2 <= RIN_A_CTRL_RETT_intermed_1;
RIN_A_CTRL_RETT_intermed_3 <= RIN_A_CTRL_RETT_intermed_2;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
V_X_ANNUL_ALL_shadow_intermed_2 <= V_X_ANNUL_ALL_shadow_intermed_1;
V_X_ANNUL_ALL_shadow_intermed_3 <= V_X_ANNUL_ALL_shadow_intermed_2;
RIN_E_CTRL_ANNUL_intermed_1 <= RIN.E.CTRL.ANNUL;
RIN_E_CTRL_ANNUL_intermed_2 <= RIN_E_CTRL_ANNUL_intermed_1;
R_E_CTRL_RETT_intermed_1 <= R.E.CTRL.RETT;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
RIN_X_ANNUL_ALL_intermed_3 <= RIN_X_ANNUL_ALL_intermed_2;
RIN_X_ANNUL_ALL_intermed_4 <= RIN_X_ANNUL_ALL_intermed_3;
RIN_E_CTRL_RETT_intermed_1 <= RIN.E.CTRL.RETT;
RIN_E_CTRL_RETT_intermed_2 <= RIN_E_CTRL_RETT_intermed_1;
V_E_CTRL_ANNUL_shadow_intermed_1 <= V_E_CTRL_ANNUL_shadow;
V_E_CTRL_ANNUL_shadow_intermed_2 <= V_E_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_3 <= V_A_CTRL_ANNUL_shadow_intermed_2;
RIN_X_CTRL_RETT_intermed_1 <= RIN.X.CTRL.RETT;
V_M_CTRL_RETT_shadow_intermed_1 <= V_M_CTRL_RETT_shadow;
R_A_CTRL_RETT_intermed_1 <= R.A.CTRL.RETT;
R_A_CTRL_RETT_intermed_2 <= R_A_CTRL_RETT_intermed_1;
R_E_CTRL_ANNUL_intermed_1 <= R.E.CTRL.ANNUL;
V_E_MAC_shadow_intermed_1 <= V_E_MAC_shadow;
V_E_MAC_shadow_intermed_2 <= V_E_MAC_shadow_intermed_1;
RIN_M_MAC_intermed_1 <= RIN.M.MAC;
RIN_E_MAC_intermed_1 <= RIN.E.MAC;
RIN_E_MAC_intermed_2 <= RIN_E_MAC_intermed_1;
R_E_MAC_intermed_1 <= R.E.MAC;
V_M_MAC_shadow_intermed_1 <= V_M_MAC_shadow;
RIN_X_MAC_intermed_1 <= RIN.X.MAC;
V_M_RESULT1DOWNTO0_shadow_intermed_1 <= V_M_RESULT1DOWNTO0_shadow;
V_M_RESULT1DOWNTO0_shadow_intermed_2 <= V_M_RESULT1DOWNTO0_shadow_intermed_1;
RIN_X_LADDR_intermed_1 <= RIN.X.LADDR;
RIN_M_RESULT1DOWNTO0_intermed_1 <= RIN.M.RESULT( 1 DOWNTO 0 );
RIN_M_RESULT1DOWNTO0_intermed_2 <= RIN_M_RESULT1DOWNTO0_intermed_1;
V_M_RESULT1DOWNTO0_shadow_intermed_1 <= V_M_RESULT1DOWNTO0_shadow;
R_M_RESULT1DOWNTO0_intermed_1 <= R.M.RESULT( 1 DOWNTO 0 );
RIN_M_RESULT1DOWNTO0_intermed_1 <= RIN.M.RESULT ( 1 DOWNTO 0 );
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1;
V_M_CTRL_ANNUL_shadow_intermed_1 <= V_M_CTRL_ANNUL_shadow;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
RIN_X_CTRL_ANNUL_intermed_1 <= RIN.X.CTRL.ANNUL;
RIN_M_CTRL_ANNUL_intermed_1 <= RIN.M.CTRL.ANNUL;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
RIN_E_CTRL_ANNUL_intermed_1 <= RIN.E.CTRL.ANNUL;
RIN_E_CTRL_ANNUL_intermed_2 <= RIN_E_CTRL_ANNUL_intermed_1;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
V_E_CTRL_ANNUL_shadow_intermed_1 <= V_E_CTRL_ANNUL_shadow;
V_E_CTRL_ANNUL_shadow_intermed_2 <= V_E_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_3 <= V_A_CTRL_ANNUL_shadow_intermed_2;
R_E_CTRL_ANNUL_intermed_1 <= R.E.CTRL.ANNUL;
V_E_CTRL_TT_shadow_intermed_1 <= V_E_CTRL_TT_shadow;
V_E_CTRL_TT_shadow_intermed_2 <= V_E_CTRL_TT_shadow_intermed_1;
V_E_CTRL_TT_shadow_intermed_3 <= V_E_CTRL_TT_shadow_intermed_2;
RIN_A_CTRL_TT_intermed_1 <= RIN.A.CTRL.TT;
RIN_A_CTRL_TT_intermed_2 <= RIN_A_CTRL_TT_intermed_1;
RIN_A_CTRL_TT_intermed_3 <= RIN_A_CTRL_TT_intermed_2;
RIN_A_CTRL_TT_intermed_4 <= RIN_A_CTRL_TT_intermed_3;
R_A_CTRL_TT_intermed_1 <= R.A.CTRL.TT;
R_A_CTRL_TT_intermed_2 <= R_A_CTRL_TT_intermed_1;
R_A_CTRL_TT_intermed_3 <= R_A_CTRL_TT_intermed_2;
R_M_CTRL_TT_intermed_1 <= R.M.CTRL.TT;
R_E_CTRL_TT_intermed_1 <= R.E.CTRL.TT;
R_E_CTRL_TT_intermed_2 <= R_E_CTRL_TT_intermed_1;
RIN_M_CTRL_TT_intermed_1 <= RIN.M.CTRL.TT;
RIN_M_CTRL_TT_intermed_2 <= RIN_M_CTRL_TT_intermed_1;
RIN_E_CTRL_TT_intermed_1 <= RIN.E.CTRL.TT;
RIN_E_CTRL_TT_intermed_2 <= RIN_E_CTRL_TT_intermed_1;
RIN_E_CTRL_TT_intermed_3 <= RIN_E_CTRL_TT_intermed_2;
V_M_CTRL_TT_shadow_intermed_1 <= V_M_CTRL_TT_shadow;
V_M_CTRL_TT_shadow_intermed_2 <= V_M_CTRL_TT_shadow_intermed_1;
V_A_CTRL_TT_shadow_intermed_1 <= V_A_CTRL_TT_shadow;
V_A_CTRL_TT_shadow_intermed_2 <= V_A_CTRL_TT_shadow_intermed_1;
V_A_CTRL_TT_shadow_intermed_3 <= V_A_CTRL_TT_shadow_intermed_2;
V_A_CTRL_TT_shadow_intermed_4 <= V_A_CTRL_TT_shadow_intermed_3;
RIN_X_CTRL_TT_intermed_1 <= RIN.X.CTRL.TT;
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
V_X_DATA0_shadow_intermed_2 <= V_X_DATA0_shadow_intermed_1;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA ( 0 );
R_X_DATA0_intermed_1 <= R.X.DATA( 0 );
RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 );
RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1;
V_X_DATA1_shadow_intermed_1 <= V_X_DATA1_shadow;
V_X_DATA1_shadow_intermed_2 <= V_X_DATA1_shadow_intermed_1;
RIN_X_DATA1_intermed_1 <= RIN.X.DATA ( 1 );
R_X_DATA1_intermed_1 <= R.X.DATA( 1 );
RIN_X_DATA1_intermed_1 <= RIN.X.DATA( 1 );
RIN_X_DATA1_intermed_2 <= RIN_X_DATA1_intermed_1;
RIN_X_SET_intermed_1 <= RIN.X.SET;
V_M_DCI_SIZE_shadow_intermed_1 <= V_M_DCI_SIZE_shadow;
V_M_DCI_SIZE_shadow_intermed_2 <= V_M_DCI_SIZE_shadow_intermed_1;
R_M_DCI_SIZE_intermed_1 <= R.M.DCI.SIZE;
RIN_X_DCI_SIZE_intermed_1 <= RIN.X.DCI.SIZE;
RIN_M_DCI_SIZE_intermed_1 <= RIN.M.DCI.SIZE;
RIN_M_DCI_SIZE_intermed_2 <= RIN_M_DCI_SIZE_intermed_1;
RIN_M_DCI_SIGNED_intermed_1 <= RIN.M.DCI.SIGNED;
RIN_M_DCI_SIGNED_intermed_2 <= RIN_M_DCI_SIGNED_intermed_1;
R_M_DCI_SIGNED_intermed_1 <= R.M.DCI.SIGNED;
RIN_X_DCI_SIGNED_intermed_1 <= RIN.X.DCI.SIGNED;
V_M_DCI_SIGNED_shadow_intermed_1 <= V_M_DCI_SIGNED_shadow;
V_M_DCI_SIGNED_shadow_intermed_2 <= V_M_DCI_SIGNED_shadow_intermed_1;
RIN_X_MEXC_intermed_1 <= RIN.X.MEXC;
RIN_X_ICC_intermed_1 <= RIN.X.ICC;
R_A_CTRL_WICC_intermed_1 <= R.A.CTRL.WICC;
R_A_CTRL_WICC_intermed_2 <= R_A_CTRL_WICC_intermed_1;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2;
RIN_A_CTRL_ANNUL_intermed_4 <= RIN_A_CTRL_ANNUL_intermed_3;
V_E_CTRL_WICC_shadow_intermed_1 <= V_E_CTRL_WICC_shadow;
V_E_CTRL_WICC_shadow_intermed_2 <= V_E_CTRL_WICC_shadow_intermed_1;
V_A_CTRL_WICC_shadow_intermed_1 <= V_A_CTRL_WICC_shadow;
V_A_CTRL_WICC_shadow_intermed_2 <= V_A_CTRL_WICC_shadow_intermed_1;
V_A_CTRL_WICC_shadow_intermed_3 <= V_A_CTRL_WICC_shadow_intermed_2;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1;
R_A_CTRL_ANNUL_intermed_3 <= R_A_CTRL_ANNUL_intermed_2;
RIN_X_CTRL_WICC_intermed_1 <= RIN.X.CTRL.WICC;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
R_X_ANNUL_ALL_intermed_2 <= R_X_ANNUL_ALL_intermed_1;
R_X_ANNUL_ALL_intermed_3 <= R_X_ANNUL_ALL_intermed_2;
RIN_E_CTRL_WICC_intermed_1 <= RIN.E.CTRL.WICC;
RIN_E_CTRL_WICC_intermed_2 <= RIN_E_CTRL_WICC_intermed_1;
RIN_M_CTRL_WICC_intermed_1 <= RIN.M.CTRL.WICC;
R_E_CTRL_WICC_intermed_1 <= R.E.CTRL.WICC;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
V_X_ANNUL_ALL_shadow_intermed_2 <= V_X_ANNUL_ALL_shadow_intermed_1;
V_X_ANNUL_ALL_shadow_intermed_3 <= V_X_ANNUL_ALL_shadow_intermed_2;
V_M_CTRL_WICC_shadow_intermed_1 <= V_M_CTRL_WICC_shadow;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
RIN_X_ANNUL_ALL_intermed_3 <= RIN_X_ANNUL_ALL_intermed_2;
RIN_X_ANNUL_ALL_intermed_4 <= RIN_X_ANNUL_ALL_intermed_3;
RIN_A_CTRL_WICC_intermed_1 <= RIN.A.CTRL.WICC;
RIN_A_CTRL_WICC_intermed_2 <= RIN_A_CTRL_WICC_intermed_1;
RIN_A_CTRL_WICC_intermed_3 <= RIN_A_CTRL_WICC_intermed_2;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_3 <= V_A_CTRL_ANNUL_shadow_intermed_2;
RIN_E_CTRL_intermed_1 <= RIN.E.CTRL;
RIN_M_CTRL_intermed_1 <= RIN.M.CTRL;
V_E_CTRL_shadow_intermed_1 <= V_E_CTRL_shadow;
RIN_A_CTRL_intermed_1 <= RIN.A.CTRL;
RIN_A_CTRL_intermed_2 <= RIN_A_CTRL_intermed_1;
V_A_CTRL_shadow_intermed_1 <= V_A_CTRL_shadow;
V_A_CTRL_shadow_intermed_2 <= V_A_CTRL_shadow_intermed_1;
R_A_CTRL_intermed_1 <= R.A.CTRL;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1;
RIN_M_CTRL_RETT_intermed_1 <= RIN.M.CTRL.RETT;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
R_X_ANNUL_ALL_intermed_2 <= R_X_ANNUL_ALL_intermed_1;
V_E_CTRL_RETT_shadow_intermed_1 <= V_E_CTRL_RETT_shadow;
V_A_CTRL_RETT_shadow_intermed_1 <= V_A_CTRL_RETT_shadow;
V_A_CTRL_RETT_shadow_intermed_2 <= V_A_CTRL_RETT_shadow_intermed_1;
RIN_A_CTRL_RETT_intermed_1 <= RIN.A.CTRL.RETT;
RIN_A_CTRL_RETT_intermed_2 <= RIN_A_CTRL_RETT_intermed_1;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
V_X_ANNUL_ALL_shadow_intermed_2 <= V_X_ANNUL_ALL_shadow_intermed_1;
RIN_E_CTRL_ANNUL_intermed_1 <= RIN.E.CTRL.ANNUL;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
RIN_X_ANNUL_ALL_intermed_3 <= RIN_X_ANNUL_ALL_intermed_2;
RIN_E_CTRL_RETT_intermed_1 <= RIN.E.CTRL.RETT;
V_E_CTRL_ANNUL_shadow_intermed_1 <= V_E_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1;
R_A_CTRL_RETT_intermed_1 <= R.A.CTRL.RETT;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
R_X_ANNUL_ALL_intermed_2 <= R_X_ANNUL_ALL_intermed_1;
RIN_M_CTRL_WREG_intermed_1 <= RIN.M.CTRL.WREG;
RIN_A_CTRL_WREG_intermed_1 <= RIN.A.CTRL.WREG;
RIN_A_CTRL_WREG_intermed_2 <= RIN_A_CTRL_WREG_intermed_1;
V_A_CTRL_WREG_shadow_intermed_1 <= V_A_CTRL_WREG_shadow;
V_A_CTRL_WREG_shadow_intermed_2 <= V_A_CTRL_WREG_shadow_intermed_1;
R_A_CTRL_WREG_intermed_1 <= R.A.CTRL.WREG;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
V_X_ANNUL_ALL_shadow_intermed_2 <= V_X_ANNUL_ALL_shadow_intermed_1;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
RIN_X_ANNUL_ALL_intermed_3 <= RIN_X_ANNUL_ALL_intermed_2;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1;
RIN_E_CTRL_WREG_intermed_1 <= RIN.E.CTRL.WREG;
V_E_CTRL_WREG_shadow_intermed_1 <= V_E_CTRL_WREG_shadow;
RIN_E_CWP_intermed_1 <= RIN.E.CWP;
V_A_CWP_shadow_intermed_1 <= V_A_CWP_shadow;
RIN_D_CWP_intermed_1 <= RIN.D.CWP;
RIN_D_CWP_intermed_2 <= RIN_D_CWP_intermed_1;
RIN_A_CWP_intermed_1 <= RIN.A.CWP;
V_D_CWP_shadow_intermed_1 <= V_D_CWP_shadow;
V_D_CWP_shadow_intermed_2 <= V_D_CWP_shadow_intermed_1;
R_D_CWP_intermed_1 <= R.D.CWP;
R_A_SU_intermed_1 <= R.A.SU;
RIN_A_SU_intermed_1 <= RIN.A.SU;
RIN_A_SU_intermed_2 <= RIN_A_SU_intermed_1;
V_E_SU_shadow_intermed_1 <= V_E_SU_shadow;
V_A_SU_shadow_intermed_1 <= V_A_SU_shadow;
V_A_SU_shadow_intermed_2 <= V_A_SU_shadow_intermed_1;
RIN_M_SU_intermed_1 <= RIN.M.SU;
RIN_E_SU_intermed_1 <= RIN.E.SU;
RIN_M_MUL_intermed_1 <= RIN.M.MUL;
RIN_M_NALIGN_intermed_1 <= RIN.M.NALIGN;
V_X_DATA03_shadow_intermed_1 <= V_X_DATA03_shadow;
V_X_DATA03_shadow_intermed_2 <= V_X_DATA03_shadow_intermed_1;
V_X_DATA03_shadow_intermed_1 <= V_X_DATA03_shadow;
DCO_DATA03_intermed_1 <= DCO.DATA ( 0 )( 3 );
RIN_X_DATA03_intermed_1 <= RIN.X.DATA ( 0 )( 3 );
R_X_DATA03_intermed_1 <= R.X.DATA( 0 )( 3 );
RIN_X_DATA03_intermed_1 <= RIN.X.DATA( 0 )( 3 );
RIN_X_DATA03_intermed_2 <= RIN_X_DATA03_intermed_1;
RIN_E_OP23_intermed_1 <= RIN.E.OP2( 3 );
RIN_E_OP13_intermed_1 <= RIN.E.OP1( 3 );
V_E_OP23_shadow_intermed_1 <= V_E_OP23_shadow;
V_E_OP13_shadow_intermed_1 <= V_E_OP13_shadow;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1;
RIN_M_CTRL_ANNUL_intermed_1 <= RIN.M.CTRL.ANNUL;
RIN_E_CTRL_ANNUL_intermed_1 <= RIN.E.CTRL.ANNUL;
RIN_E_CTRL_ANNUL_intermed_2 <= RIN_E_CTRL_ANNUL_intermed_1;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
V_E_CTRL_ANNUL_shadow_intermed_1 <= V_E_CTRL_ANNUL_shadow;
V_E_CTRL_ANNUL_shadow_intermed_2 <= V_E_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_3 <= V_A_CTRL_ANNUL_shadow_intermed_2;
R_E_CTRL_ANNUL_intermed_1 <= R.E.CTRL.ANNUL;
R_A_CTRL_WICC_intermed_1 <= R.A.CTRL.WICC;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2;
V_E_CTRL_WICC_shadow_intermed_1 <= V_E_CTRL_WICC_shadow;
V_A_CTRL_WICC_shadow_intermed_1 <= V_A_CTRL_WICC_shadow;
V_A_CTRL_WICC_shadow_intermed_2 <= V_A_CTRL_WICC_shadow_intermed_1;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
R_X_ANNUL_ALL_intermed_2 <= R_X_ANNUL_ALL_intermed_1;
RIN_E_CTRL_WICC_intermed_1 <= RIN.E.CTRL.WICC;
RIN_M_CTRL_WICC_intermed_1 <= RIN.M.CTRL.WICC;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
V_X_ANNUL_ALL_shadow_intermed_2 <= V_X_ANNUL_ALL_shadow_intermed_1;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
RIN_X_ANNUL_ALL_intermed_3 <= RIN_X_ANNUL_ALL_intermed_2;
RIN_A_CTRL_WICC_intermed_1 <= RIN.A.CTRL.WICC;
RIN_A_CTRL_WICC_intermed_2 <= RIN_A_CTRL_WICC_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1;
V_E_MAC_shadow_intermed_1 <= V_E_MAC_shadow;
RIN_M_MAC_intermed_1 <= RIN.M.MAC;
RIN_E_MAC_intermed_1 <= RIN.E.MAC;
R_A_CTRL_LD_intermed_1 <= R.A.CTRL.LD;
R_A_CTRL_LD_intermed_2 <= R_A_CTRL_LD_intermed_1;
RIN_A_CTRL_LD_intermed_1 <= RIN.A.CTRL.LD;
RIN_A_CTRL_LD_intermed_2 <= RIN_A_CTRL_LD_intermed_1;
RIN_A_CTRL_LD_intermed_3 <= RIN_A_CTRL_LD_intermed_2;
V_E_CTRL_LD_shadow_intermed_1 <= V_E_CTRL_LD_shadow;
V_E_CTRL_LD_shadow_intermed_2 <= V_E_CTRL_LD_shadow_intermed_1;
R_E_CTRL_LD_intermed_1 <= R.E.CTRL.LD;
RIN_E_CTRL_LD_intermed_1 <= RIN.E.CTRL.LD;
RIN_E_CTRL_LD_intermed_2 <= RIN_E_CTRL_LD_intermed_1;
RIN_M_CTRL_LD_intermed_1 <= RIN.M.CTRL.LD;
V_A_CTRL_LD_shadow_intermed_1 <= V_A_CTRL_LD_shadow;
V_A_CTRL_LD_shadow_intermed_2 <= V_A_CTRL_LD_shadow_intermed_1;
V_A_CTRL_LD_shadow_intermed_3 <= V_A_CTRL_LD_shadow_intermed_2;
RIN_E_CTRL_intermed_1 <= RIN.E.CTRL;
RIN_A_CTRL_intermed_1 <= RIN.A.CTRL;
V_A_CTRL_shadow_intermed_1 <= V_A_CTRL_shadow;
RIN_E_JMPL_intermed_1 <= RIN.E.JMPL;
RIN_A_JMPL_intermed_1 <= RIN.A.JMPL;
V_A_JMPL_shadow_intermed_1 <= V_A_JMPL_shadow;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
RIN_E_CTRL_ANNUL_intermed_1 <= RIN.E.CTRL.ANNUL;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
V_A_CTRL_RETT_shadow_intermed_1 <= V_A_CTRL_RETT_shadow;
RIN_A_CTRL_RETT_intermed_1 <= RIN.A.CTRL.RETT;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
RIN_E_CTRL_RETT_intermed_1 <= RIN.E.CTRL.RETT;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
RIN_A_CTRL_WREG_intermed_1 <= RIN.A.CTRL.WREG;
V_A_CTRL_WREG_shadow_intermed_1 <= V_A_CTRL_WREG_shadow;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
RIN_E_CTRL_WREG_intermed_1 <= RIN.E.CTRL.WREG;
RIN_A_SU_intermed_1 <= RIN.A.SU;
V_A_SU_shadow_intermed_1 <= V_A_SU_shadow;
RIN_E_SU_intermed_1 <= RIN.E.SU;
RIN_E_ET_intermed_1 <= RIN.E.ET;
RIN_A_ET_intermed_1 <= RIN.A.ET;
V_A_ET_shadow_intermed_1 <= V_A_ET_shadow;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
V_A_CTRL_WICC_shadow_intermed_1 <= V_A_CTRL_WICC_shadow;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
RIN_E_CTRL_WICC_intermed_1 <= RIN.E.CTRL.WICC;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
RIN_A_CTRL_WICC_intermed_1 <= RIN.A.CTRL.WICC;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
RIN_D_CWP_intermed_1 <= RIN.D.CWP;
RIN_A_CWP_intermed_1 <= RIN.A.CWP;
V_D_CWP_shadow_intermed_1 <= V_D_CWP_shadow;
RIN_A_RFA1_intermed_1 <= RIN.A.RFA1;
V_A_RFA1_shadow_intermed_1 <= V_A_RFA1_shadow;
DBGI_DADDR9DOWNTO2_intermed_1 <= DBGI.DADDR ( 9 DOWNTO 2 );
RIN_A_RFA1_intermed_1 <= RIN.A.RFA1;
RIN_A_RFA2_intermed_1 <= RIN.A.RFA2;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_A_CTRL_WICC_intermed_1 <= RIN.A.CTRL.WICC;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_WREG_intermed_1 <= RIN.A.CTRL.WREG;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_RETT_intermed_1 <= RIN.A.CTRL.RETT;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_A_CTRL_WY_intermed_1 <= RIN.A.CTRL.WY;
ICO_MEXC_intermed_1 <= ICO.MEXC;
RIN_A_CTRL_TRAP_intermed_1 <= RIN.A.CTRL.TRAP;
V_D_MEXC_shadow_intermed_1 <= V_D_MEXC_shadow;
RIN_D_MEXC_intermed_1 <= RIN.D.MEXC;
RIN_A_CTRL_TT_intermed_1 <= RIN.A.CTRL.TT;
RIN_A_CTRL_INST_intermed_1 <= RIN.A.CTRL.INST;
RIN_D_PC_intermed_1 <= RIN.D.PC;
RIN_A_CTRL_PC_intermed_1 <= RIN.A.CTRL.PC;
V_D_PC_shadow_intermed_1 <= V_D_PC_shadow;
RIN_D_CNT_intermed_1 <= RIN.D.CNT;
V_D_CNT_shadow_intermed_1 <= V_D_CNT_shadow;
RIN_A_CTRL_CNT_intermed_1 <= RIN.A.CTRL.CNT;
R_D_ANNUL_intermed_1 <= R.D.ANNUL;
RIN_D_STEP_intermed_1 <= RIN.D.STEP;
V_D_ANNUL_shadow_intermed_1 <= V_D_ANNUL_shadow;
V_D_ANNUL_shadow_intermed_2 <= V_D_ANNUL_shadow_intermed_1;
DBGI_STEP_intermed_1 <= DBGI.STEP;
V_D_STEP_shadow_intermed_1 <= V_D_STEP_shadow;
RIN_D_ANNUL_intermed_1 <= RIN.D.ANNUL;
RIN_D_ANNUL_intermed_2 <= RIN_D_ANNUL_intermed_1;
RIN_A_STEP_intermed_1 <= RIN.A.STEP;
RIN_D_STEP_intermed_1 <= RIN.D.STEP;
V_D_ANNUL_shadow_intermed_1 <= V_D_ANNUL_shadow;
RIN_D_ANNUL_intermed_1 <= RIN.D.ANNUL;
RIN_D_CNT_intermed_1 <= RIN.D.CNT;
EX_ADD_RES32DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO3_shadow;
RIN_F_PC_intermed_1 <= RIN.F.PC;
EX_JUMP_ADDRESS_shadow_intermed_1 <= EX_JUMP_ADDRESS_shadow;
RIN_F_BRANCH_intermed_1 <= RIN.F.BRANCH;
R_M_CTRL_PC31DOWNTO12_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 12 );
R_M_CTRL_PC31DOWNTO12_intermed_2 <= R_M_CTRL_PC31DOWNTO12_intermed_1;
R_M_CTRL_PC31DOWNTO12_intermed_3 <= R_M_CTRL_PC31DOWNTO12_intermed_2;
V_D_PC31DOWNTO12_shadow_intermed_1 <= V_D_PC31DOWNTO12_shadow;
V_D_PC31DOWNTO12_shadow_intermed_2 <= V_D_PC31DOWNTO12_shadow_intermed_1;
V_D_PC31DOWNTO12_shadow_intermed_3 <= V_D_PC31DOWNTO12_shadow_intermed_2;
V_D_PC31DOWNTO12_shadow_intermed_4 <= V_D_PC31DOWNTO12_shadow_intermed_3;
V_D_PC31DOWNTO12_shadow_intermed_5 <= V_D_PC31DOWNTO12_shadow_intermed_4;
V_D_PC31DOWNTO12_shadow_intermed_6 <= V_D_PC31DOWNTO12_shadow_intermed_5;
V_D_PC31DOWNTO12_shadow_intermed_7 <= V_D_PC31DOWNTO12_shadow_intermed_6;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO12_shadow;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_5;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO12_shadow;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_4;
EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_1 <= EX_ADD_RES32DOWNTO330DOWNTO11_shadow;
EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_2 <= EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_1;
RIN_F_PC31DOWNTO12_intermed_1 <= RIN.F.PC( 31 DOWNTO 12 );
RIN_F_PC31DOWNTO12_intermed_2 <= RIN_F_PC31DOWNTO12_intermed_1;
R_A_CTRL_PC31DOWNTO12_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 12 );
R_A_CTRL_PC31DOWNTO12_intermed_2 <= R_A_CTRL_PC31DOWNTO12_intermed_1;
R_A_CTRL_PC31DOWNTO12_intermed_3 <= R_A_CTRL_PC31DOWNTO12_intermed_2;
R_A_CTRL_PC31DOWNTO12_intermed_4 <= R_A_CTRL_PC31DOWNTO12_intermed_3;
R_A_CTRL_PC31DOWNTO12_intermed_5 <= R_A_CTRL_PC31DOWNTO12_intermed_4;
R_E_CTRL_PC31DOWNTO12_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 12 );
R_E_CTRL_PC31DOWNTO12_intermed_2 <= R_E_CTRL_PC31DOWNTO12_intermed_1;
R_E_CTRL_PC31DOWNTO12_intermed_3 <= R_E_CTRL_PC31DOWNTO12_intermed_2;
R_E_CTRL_PC31DOWNTO12_intermed_4 <= R_E_CTRL_PC31DOWNTO12_intermed_3;
EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO12_shadow;
EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_2 <= EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_1;
RIN_F_PC31DOWNTO12_intermed_1 <= RIN.F.PC ( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_2 <= RIN_A_CTRL_PC31DOWNTO12_intermed_1;
RIN_A_CTRL_PC31DOWNTO12_intermed_3 <= RIN_A_CTRL_PC31DOWNTO12_intermed_2;
RIN_A_CTRL_PC31DOWNTO12_intermed_4 <= RIN_A_CTRL_PC31DOWNTO12_intermed_3;
RIN_A_CTRL_PC31DOWNTO12_intermed_5 <= RIN_A_CTRL_PC31DOWNTO12_intermed_4;
RIN_A_CTRL_PC31DOWNTO12_intermed_6 <= RIN_A_CTRL_PC31DOWNTO12_intermed_5;
RIN_E_CTRL_PC31DOWNTO12_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 12 );
RIN_E_CTRL_PC31DOWNTO12_intermed_2 <= RIN_E_CTRL_PC31DOWNTO12_intermed_1;
RIN_E_CTRL_PC31DOWNTO12_intermed_3 <= RIN_E_CTRL_PC31DOWNTO12_intermed_2;
RIN_E_CTRL_PC31DOWNTO12_intermed_4 <= RIN_E_CTRL_PC31DOWNTO12_intermed_3;
RIN_E_CTRL_PC31DOWNTO12_intermed_5 <= RIN_E_CTRL_PC31DOWNTO12_intermed_4;
V_F_PC31DOWNTO12_shadow_intermed_1 <= V_F_PC31DOWNTO12_shadow;
V_F_PC31DOWNTO12_shadow_intermed_2 <= V_F_PC31DOWNTO12_shadow_intermed_1;
IRIN_ADDR31DOWNTO12_intermed_1 <= IRIN.ADDR( 31 DOWNTO 12 );
IRIN_ADDR31DOWNTO12_intermed_2 <= IRIN_ADDR31DOWNTO12_intermed_1;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO12_shadow;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_2;
EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO13_shadow;
EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_2 <= EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_1;
XC_TRAP_ADDRESS31DOWNTO12_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO12_shadow;
R_F_PC31DOWNTO12_intermed_1 <= R.F.PC( 31 DOWNTO 12 );
RIN_M_CTRL_PC31DOWNTO12_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 12 );
RIN_M_CTRL_PC31DOWNTO12_intermed_2 <= RIN_M_CTRL_PC31DOWNTO12_intermed_1;
RIN_M_CTRL_PC31DOWNTO12_intermed_3 <= RIN_M_CTRL_PC31DOWNTO12_intermed_2;
RIN_M_CTRL_PC31DOWNTO12_intermed_4 <= RIN_M_CTRL_PC31DOWNTO12_intermed_3;
IR_ADDR31DOWNTO12_intermed_1 <= IR.ADDR( 31 DOWNTO 12 );
R_X_CTRL_PC31DOWNTO12_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 12 );
R_X_CTRL_PC31DOWNTO12_intermed_2 <= R_X_CTRL_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_1 <= R.D.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_2 <= R_D_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_3 <= R_D_PC31DOWNTO12_intermed_2;
R_D_PC31DOWNTO12_intermed_4 <= R_D_PC31DOWNTO12_intermed_3;
R_D_PC31DOWNTO12_intermed_5 <= R_D_PC31DOWNTO12_intermed_4;
R_D_PC31DOWNTO12_intermed_6 <= R_D_PC31DOWNTO12_intermed_5;
RIN_X_CTRL_PC31DOWNTO12_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 12 );
RIN_X_CTRL_PC31DOWNTO12_intermed_2 <= RIN_X_CTRL_PC31DOWNTO12_intermed_1;
RIN_X_CTRL_PC31DOWNTO12_intermed_3 <= RIN_X_CTRL_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_1 <= RIN.D.PC( 31 DOWNTO 12 );
RIN_D_PC31DOWNTO12_intermed_2 <= RIN_D_PC31DOWNTO12_intermed_1;
RIN_D_PC31DOWNTO12_intermed_3 <= RIN_D_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_4 <= RIN_D_PC31DOWNTO12_intermed_3;
RIN_D_PC31DOWNTO12_intermed_5 <= RIN_D_PC31DOWNTO12_intermed_4;
RIN_D_PC31DOWNTO12_intermed_6 <= RIN_D_PC31DOWNTO12_intermed_5;
RIN_D_PC31DOWNTO12_intermed_7 <= RIN_D_PC31DOWNTO12_intermed_6;
VIR_ADDR31DOWNTO12_shadow_intermed_1 <= VIR_ADDR31DOWNTO12_shadow;
VIR_ADDR31DOWNTO12_shadow_intermed_2 <= VIR_ADDR31DOWNTO12_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO12_shadow;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_3;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_4 <= RIN_M_CTRL_PC31DOWNTO2_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
V_D_PC31DOWNTO2_shadow_intermed_6 <= V_D_PC31DOWNTO2_shadow_intermed_5;
V_D_PC31DOWNTO2_shadow_intermed_7 <= V_D_PC31DOWNTO2_shadow_intermed_6;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_D_PC31DOWNTO2_intermed_6 <= RIN_D_PC31DOWNTO2_intermed_5;
RIN_D_PC31DOWNTO2_intermed_7 <= RIN_D_PC31DOWNTO2_intermed_6;
EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow;
EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_2 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1;
V_F_PC31DOWNTO2_shadow_intermed_1 <= V_F_PC31DOWNTO2_shadow;
V_F_PC31DOWNTO2_shadow_intermed_2 <= V_F_PC31DOWNTO2_shadow_intermed_1;
RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC( 31 DOWNTO 2 );
RIN_F_PC31DOWNTO2_intermed_2 <= RIN_F_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_3 <= RIN_X_CTRL_PC31DOWNTO2_intermed_2;
IRIN_ADDR31DOWNTO2_intermed_1 <= IRIN.ADDR( 31 DOWNTO 2 );
IRIN_ADDR31DOWNTO2_intermed_2 <= IRIN_ADDR31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_5;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_D_PC31DOWNTO2_intermed_5 <= R_D_PC31DOWNTO2_intermed_4;
R_D_PC31DOWNTO2_intermed_6 <= R_D_PC31DOWNTO2_intermed_5;
R_F_PC31DOWNTO2_intermed_1 <= R.F.PC( 31 DOWNTO 2 );
VIR_ADDR31DOWNTO2_shadow_intermed_1 <= VIR_ADDR31DOWNTO2_shadow;
VIR_ADDR31DOWNTO2_shadow_intermed_2 <= VIR_ADDR31DOWNTO2_shadow_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_3 <= R_M_CTRL_PC31DOWNTO2_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_6 <= RIN_A_CTRL_PC31DOWNTO2_intermed_5;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
R_A_CTRL_PC31DOWNTO2_intermed_5 <= R_A_CTRL_PC31DOWNTO2_intermed_4;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
R_X_CTRL_PC31DOWNTO2_intermed_2 <= R_X_CTRL_PC31DOWNTO2_intermed_1;
XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO2_shadow;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_4 <= R_E_CTRL_PC31DOWNTO2_intermed_3;
EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO2_shadow;
EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_2 <= EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1;
RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC ( 31 DOWNTO 2 );
IR_ADDR31DOWNTO2_intermed_1 <= IR.ADDR( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_5 <= RIN_E_CTRL_PC31DOWNTO2_intermed_4;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_4 <= RIN_M_CTRL_PC31DOWNTO2_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
V_D_PC31DOWNTO2_shadow_intermed_6 <= V_D_PC31DOWNTO2_shadow_intermed_5;
V_D_PC31DOWNTO2_shadow_intermed_7 <= V_D_PC31DOWNTO2_shadow_intermed_6;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_D_PC31DOWNTO2_intermed_6 <= RIN_D_PC31DOWNTO2_intermed_5;
RIN_D_PC31DOWNTO2_intermed_7 <= RIN_D_PC31DOWNTO2_intermed_6;
EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow;
V_F_PC31DOWNTO2_shadow_intermed_1 <= V_F_PC31DOWNTO2_shadow;
RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_3 <= RIN_X_CTRL_PC31DOWNTO2_intermed_2;
IRIN_ADDR31DOWNTO2_intermed_1 <= IRIN.ADDR( 31 DOWNTO 2 );
IRIN_ADDR31DOWNTO2_intermed_2 <= IRIN_ADDR31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_5;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_D_PC31DOWNTO2_intermed_5 <= R_D_PC31DOWNTO2_intermed_4;
R_D_PC31DOWNTO2_intermed_6 <= R_D_PC31DOWNTO2_intermed_5;
VIR_ADDR31DOWNTO2_shadow_intermed_1 <= VIR_ADDR31DOWNTO2_shadow;
VIR_ADDR31DOWNTO2_shadow_intermed_2 <= VIR_ADDR31DOWNTO2_shadow_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_3 <= R_M_CTRL_PC31DOWNTO2_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_6 <= RIN_A_CTRL_PC31DOWNTO2_intermed_5;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
R_A_CTRL_PC31DOWNTO2_intermed_5 <= R_A_CTRL_PC31DOWNTO2_intermed_4;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
R_X_CTRL_PC31DOWNTO2_intermed_2 <= R_X_CTRL_PC31DOWNTO2_intermed_1;
XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO2_shadow;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_4 <= R_E_CTRL_PC31DOWNTO2_intermed_3;
EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO2_shadow;
IR_ADDR31DOWNTO2_intermed_1 <= IR.ADDR( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_5 <= RIN_E_CTRL_PC31DOWNTO2_intermed_4;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_D_INST0_intermed_1 <= RIN.D.INST ( 0 );
R_D_INST0_intermed_1 <= R.D.INST( 0 );
V_D_INST0_shadow_intermed_1 <= V_D_INST0_shadow;
V_D_INST0_shadow_intermed_2 <= V_D_INST0_shadow_intermed_1;
RIN_D_INST0_intermed_1 <= RIN.D.INST( 0 );
RIN_D_INST0_intermed_2 <= RIN_D_INST0_intermed_1;
RIN_D_INST1_intermed_1 <= RIN.D.INST ( 1 );
R_D_INST1_intermed_1 <= R.D.INST( 1 );
V_D_INST1_shadow_intermed_1 <= V_D_INST1_shadow;
V_D_INST1_shadow_intermed_2 <= V_D_INST1_shadow_intermed_1;
RIN_D_INST1_intermed_1 <= RIN.D.INST( 1 );
RIN_D_INST1_intermed_2 <= RIN_D_INST1_intermed_1;
RIN_D_SET_intermed_1 <= RIN.D.SET;
RIN_D_MEXC_intermed_1 <= RIN.D.MEXC;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
RIN_E_OP131_intermed_1 <= RIN.E.OP1( 31 );
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 );
V_E_OP131_shadow_intermed_1 <= V_E_OP131_shadow;
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 );
RIN_E_OP231_intermed_1 <= RIN.E.OP2( 31 );
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
V_E_OP231_shadow_intermed_1 <= V_E_OP231_shadow;
V_D_ANNUL_shadow_intermed_1 <= V_D_ANNUL_shadow;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_D_ANNUL_intermed_1 <= RIN.D.ANNUL;
V_X_DATA03_shadow_intermed_1 <= V_X_DATA03_shadow;
V_X_DATA03_shadow_intermed_2 <= V_X_DATA03_shadow_intermed_1;
V_X_DATA03_shadow_intermed_1 <= V_X_DATA03_shadow;
DCO_DATA03_intermed_1 <= DCO.DATA ( 0 )( 3 );
RIN_X_DATA03_intermed_1 <= RIN.X.DATA ( 0 )( 3 );
R_X_DATA03_intermed_1 <= R.X.DATA( 0 )( 3 );
RIN_X_DATA03_intermed_1 <= RIN.X.DATA( 0 )( 3 );
RIN_X_DATA03_intermed_2 <= RIN_X_DATA03_intermed_1;
RIN_E_OP13_intermed_1 <= RIN.E.OP1( 3 );
V_E_OP13_shadow_intermed_1 <= V_E_OP13_shadow;
V_X_DATA03_shadow_intermed_1 <= V_X_DATA03_shadow;
V_X_DATA03_shadow_intermed_2 <= V_X_DATA03_shadow_intermed_1;
V_X_DATA03_shadow_intermed_1 <= V_X_DATA03_shadow;
DCO_DATA03_intermed_1 <= DCO.DATA ( 0 )( 3 );
RIN_X_DATA03_intermed_1 <= RIN.X.DATA ( 0 )( 3 );
R_X_DATA03_intermed_1 <= R.X.DATA( 0 )( 3 );
RIN_X_DATA03_intermed_1 <= RIN.X.DATA( 0 )( 3 );
RIN_X_DATA03_intermed_2 <= RIN_X_DATA03_intermed_1;
RIN_E_OP23_intermed_1 <= RIN.E.OP2( 3 );
V_E_OP23_shadow_intermed_1 <= V_E_OP23_shadow;
R_M_CTRL_PC31DOWNTO12_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 12 );
R_M_CTRL_PC31DOWNTO12_intermed_2 <= R_M_CTRL_PC31DOWNTO12_intermed_1;
R_M_CTRL_PC31DOWNTO12_intermed_3 <= R_M_CTRL_PC31DOWNTO12_intermed_2;
V_D_PC31DOWNTO12_shadow_intermed_1 <= V_D_PC31DOWNTO12_shadow;
V_D_PC31DOWNTO12_shadow_intermed_2 <= V_D_PC31DOWNTO12_shadow_intermed_1;
V_D_PC31DOWNTO12_shadow_intermed_3 <= V_D_PC31DOWNTO12_shadow_intermed_2;
V_D_PC31DOWNTO12_shadow_intermed_4 <= V_D_PC31DOWNTO12_shadow_intermed_3;
V_D_PC31DOWNTO12_shadow_intermed_5 <= V_D_PC31DOWNTO12_shadow_intermed_4;
V_D_PC31DOWNTO12_shadow_intermed_6 <= V_D_PC31DOWNTO12_shadow_intermed_5;
V_D_PC31DOWNTO12_shadow_intermed_7 <= V_D_PC31DOWNTO12_shadow_intermed_6;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO12_shadow;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_5;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO12_shadow;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_4;
EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_1 <= EX_ADD_RES32DOWNTO330DOWNTO11_shadow;
RIN_F_PC31DOWNTO12_intermed_1 <= RIN.F.PC( 31 DOWNTO 12 );
R_A_CTRL_PC31DOWNTO12_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 12 );
R_A_CTRL_PC31DOWNTO12_intermed_2 <= R_A_CTRL_PC31DOWNTO12_intermed_1;
R_A_CTRL_PC31DOWNTO12_intermed_3 <= R_A_CTRL_PC31DOWNTO12_intermed_2;
R_A_CTRL_PC31DOWNTO12_intermed_4 <= R_A_CTRL_PC31DOWNTO12_intermed_3;
R_A_CTRL_PC31DOWNTO12_intermed_5 <= R_A_CTRL_PC31DOWNTO12_intermed_4;
R_E_CTRL_PC31DOWNTO12_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 12 );
R_E_CTRL_PC31DOWNTO12_intermed_2 <= R_E_CTRL_PC31DOWNTO12_intermed_1;
R_E_CTRL_PC31DOWNTO12_intermed_3 <= R_E_CTRL_PC31DOWNTO12_intermed_2;
R_E_CTRL_PC31DOWNTO12_intermed_4 <= R_E_CTRL_PC31DOWNTO12_intermed_3;
EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO12_shadow;
RIN_A_CTRL_PC31DOWNTO12_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_2 <= RIN_A_CTRL_PC31DOWNTO12_intermed_1;
RIN_A_CTRL_PC31DOWNTO12_intermed_3 <= RIN_A_CTRL_PC31DOWNTO12_intermed_2;
RIN_A_CTRL_PC31DOWNTO12_intermed_4 <= RIN_A_CTRL_PC31DOWNTO12_intermed_3;
RIN_A_CTRL_PC31DOWNTO12_intermed_5 <= RIN_A_CTRL_PC31DOWNTO12_intermed_4;
RIN_A_CTRL_PC31DOWNTO12_intermed_6 <= RIN_A_CTRL_PC31DOWNTO12_intermed_5;
RIN_E_CTRL_PC31DOWNTO12_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 12 );
RIN_E_CTRL_PC31DOWNTO12_intermed_2 <= RIN_E_CTRL_PC31DOWNTO12_intermed_1;
RIN_E_CTRL_PC31DOWNTO12_intermed_3 <= RIN_E_CTRL_PC31DOWNTO12_intermed_2;
RIN_E_CTRL_PC31DOWNTO12_intermed_4 <= RIN_E_CTRL_PC31DOWNTO12_intermed_3;
RIN_E_CTRL_PC31DOWNTO12_intermed_5 <= RIN_E_CTRL_PC31DOWNTO12_intermed_4;
V_F_PC31DOWNTO12_shadow_intermed_1 <= V_F_PC31DOWNTO12_shadow;
IRIN_ADDR31DOWNTO12_intermed_1 <= IRIN.ADDR( 31 DOWNTO 12 );
IRIN_ADDR31DOWNTO12_intermed_2 <= IRIN_ADDR31DOWNTO12_intermed_1;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO12_shadow;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_2;
EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO13_shadow;
RIN_M_CTRL_PC31DOWNTO12_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 12 );
RIN_M_CTRL_PC31DOWNTO12_intermed_2 <= RIN_M_CTRL_PC31DOWNTO12_intermed_1;
RIN_M_CTRL_PC31DOWNTO12_intermed_3 <= RIN_M_CTRL_PC31DOWNTO12_intermed_2;
RIN_M_CTRL_PC31DOWNTO12_intermed_4 <= RIN_M_CTRL_PC31DOWNTO12_intermed_3;
IR_ADDR31DOWNTO12_intermed_1 <= IR.ADDR( 31 DOWNTO 12 );
R_X_CTRL_PC31DOWNTO12_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 12 );
R_X_CTRL_PC31DOWNTO12_intermed_2 <= R_X_CTRL_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_1 <= R.D.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_2 <= R_D_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_3 <= R_D_PC31DOWNTO12_intermed_2;
R_D_PC31DOWNTO12_intermed_4 <= R_D_PC31DOWNTO12_intermed_3;
R_D_PC31DOWNTO12_intermed_5 <= R_D_PC31DOWNTO12_intermed_4;
R_D_PC31DOWNTO12_intermed_6 <= R_D_PC31DOWNTO12_intermed_5;
RIN_X_CTRL_PC31DOWNTO12_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 12 );
RIN_X_CTRL_PC31DOWNTO12_intermed_2 <= RIN_X_CTRL_PC31DOWNTO12_intermed_1;
RIN_X_CTRL_PC31DOWNTO12_intermed_3 <= RIN_X_CTRL_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_1 <= RIN.D.PC( 31 DOWNTO 12 );
RIN_D_PC31DOWNTO12_intermed_2 <= RIN_D_PC31DOWNTO12_intermed_1;
RIN_D_PC31DOWNTO12_intermed_3 <= RIN_D_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_4 <= RIN_D_PC31DOWNTO12_intermed_3;
RIN_D_PC31DOWNTO12_intermed_5 <= RIN_D_PC31DOWNTO12_intermed_4;
RIN_D_PC31DOWNTO12_intermed_6 <= RIN_D_PC31DOWNTO12_intermed_5;
RIN_D_PC31DOWNTO12_intermed_7 <= RIN_D_PC31DOWNTO12_intermed_6;
VIR_ADDR31DOWNTO12_shadow_intermed_1 <= VIR_ADDR31DOWNTO12_shadow;
VIR_ADDR31DOWNTO12_shadow_intermed_2 <= VIR_ADDR31DOWNTO12_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO12_shadow;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_3;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_4 <= RIN_M_CTRL_PC31DOWNTO2_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
V_D_PC31DOWNTO2_shadow_intermed_6 <= V_D_PC31DOWNTO2_shadow_intermed_5;
V_D_PC31DOWNTO2_shadow_intermed_7 <= V_D_PC31DOWNTO2_shadow_intermed_6;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_D_PC31DOWNTO2_intermed_6 <= RIN_D_PC31DOWNTO2_intermed_5;
RIN_D_PC31DOWNTO2_intermed_7 <= RIN_D_PC31DOWNTO2_intermed_6;
EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow;
V_F_PC31DOWNTO2_shadow_intermed_1 <= V_F_PC31DOWNTO2_shadow;
RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_3 <= RIN_X_CTRL_PC31DOWNTO2_intermed_2;
IRIN_ADDR31DOWNTO2_intermed_1 <= IRIN.ADDR( 31 DOWNTO 2 );
IRIN_ADDR31DOWNTO2_intermed_2 <= IRIN_ADDR31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_5;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_D_PC31DOWNTO2_intermed_5 <= R_D_PC31DOWNTO2_intermed_4;
R_D_PC31DOWNTO2_intermed_6 <= R_D_PC31DOWNTO2_intermed_5;
VIR_ADDR31DOWNTO2_shadow_intermed_1 <= VIR_ADDR31DOWNTO2_shadow;
VIR_ADDR31DOWNTO2_shadow_intermed_2 <= VIR_ADDR31DOWNTO2_shadow_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_3 <= R_M_CTRL_PC31DOWNTO2_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_6 <= RIN_A_CTRL_PC31DOWNTO2_intermed_5;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
R_A_CTRL_PC31DOWNTO2_intermed_5 <= R_A_CTRL_PC31DOWNTO2_intermed_4;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
R_X_CTRL_PC31DOWNTO2_intermed_2 <= R_X_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_4 <= R_E_CTRL_PC31DOWNTO2_intermed_3;
EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO2_shadow;
IR_ADDR31DOWNTO2_intermed_1 <= IR.ADDR( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_5 <= RIN_E_CTRL_PC31DOWNTO2_intermed_4;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_4 <= RIN_M_CTRL_PC31DOWNTO2_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
V_D_PC31DOWNTO2_shadow_intermed_6 <= V_D_PC31DOWNTO2_shadow_intermed_5;
V_D_PC31DOWNTO2_shadow_intermed_7 <= V_D_PC31DOWNTO2_shadow_intermed_6;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_D_PC31DOWNTO2_intermed_6 <= RIN_D_PC31DOWNTO2_intermed_5;
RIN_D_PC31DOWNTO2_intermed_7 <= RIN_D_PC31DOWNTO2_intermed_6;
EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow;
RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_3 <= RIN_X_CTRL_PC31DOWNTO2_intermed_2;
IRIN_ADDR31DOWNTO2_intermed_1 <= IRIN.ADDR( 31 DOWNTO 2 );
IRIN_ADDR31DOWNTO2_intermed_2 <= IRIN_ADDR31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_5;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_D_PC31DOWNTO2_intermed_5 <= R_D_PC31DOWNTO2_intermed_4;
R_D_PC31DOWNTO2_intermed_6 <= R_D_PC31DOWNTO2_intermed_5;
VIR_ADDR31DOWNTO2_shadow_intermed_1 <= VIR_ADDR31DOWNTO2_shadow;
VIR_ADDR31DOWNTO2_shadow_intermed_2 <= VIR_ADDR31DOWNTO2_shadow_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_3 <= R_M_CTRL_PC31DOWNTO2_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_6 <= RIN_A_CTRL_PC31DOWNTO2_intermed_5;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
R_A_CTRL_PC31DOWNTO2_intermed_5 <= R_A_CTRL_PC31DOWNTO2_intermed_4;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
R_X_CTRL_PC31DOWNTO2_intermed_2 <= R_X_CTRL_PC31DOWNTO2_intermed_1;
XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO2_shadow;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_4 <= R_E_CTRL_PC31DOWNTO2_intermed_3;
EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO2_shadow;
IR_ADDR31DOWNTO2_intermed_1 <= IR.ADDR( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_5 <= RIN_E_CTRL_PC31DOWNTO2_intermed_4;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 );
RIN_E_OP231_intermed_1 <= RIN.E.OP2( 31 );
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
V_E_OP231_shadow_intermed_1 <= V_E_OP231_shadow;
V_M_CTRL_RD7DOWNTO0_shadow_intermed_1 <= V_M_CTRL_RD7DOWNTO0_shadow;
V_M_CTRL_RD7DOWNTO0_shadow_intermed_2 <= V_M_CTRL_RD7DOWNTO0_shadow_intermed_1;
V_E_CTRL_RD7DOWNTO0_shadow_intermed_1 <= V_E_CTRL_RD7DOWNTO0_shadow;
V_E_CTRL_RD7DOWNTO0_shadow_intermed_2 <= V_E_CTRL_RD7DOWNTO0_shadow_intermed_1;
V_E_CTRL_RD7DOWNTO0_shadow_intermed_3 <= V_E_CTRL_RD7DOWNTO0_shadow_intermed_2;
R_E_CTRL_RD7DOWNTO0_intermed_1 <= R.E.CTRL.RD ( 7 DOWNTO 0 );
R_E_CTRL_RD7DOWNTO0_intermed_2 <= R_E_CTRL_RD7DOWNTO0_intermed_1;
V_A_CTRL_RD7DOWNTO0_shadow_intermed_1 <= V_A_CTRL_RD7DOWNTO0_shadow;
V_A_CTRL_RD7DOWNTO0_shadow_intermed_2 <= V_A_CTRL_RD7DOWNTO0_shadow_intermed_1;
V_A_CTRL_RD7DOWNTO0_shadow_intermed_3 <= V_A_CTRL_RD7DOWNTO0_shadow_intermed_2;
V_A_CTRL_RD7DOWNTO0_shadow_intermed_4 <= V_A_CTRL_RD7DOWNTO0_shadow_intermed_3;
RIN_A_CTRL_RD7DOWNTO0_intermed_1 <= RIN.A.CTRL.RD ( 7 DOWNTO 0 );
RIN_A_CTRL_RD7DOWNTO0_intermed_2 <= RIN_A_CTRL_RD7DOWNTO0_intermed_1;
RIN_A_CTRL_RD7DOWNTO0_intermed_3 <= RIN_A_CTRL_RD7DOWNTO0_intermed_2;
RIN_A_CTRL_RD7DOWNTO0_intermed_4 <= RIN_A_CTRL_RD7DOWNTO0_intermed_3;
R_M_CTRL_RD7DOWNTO0_intermed_1 <= R.M.CTRL.RD ( 7 DOWNTO 0 );
R_A_CTRL_RD7DOWNTO0_intermed_1 <= R.A.CTRL.RD ( 7 DOWNTO 0 );
R_A_CTRL_RD7DOWNTO0_intermed_2 <= R_A_CTRL_RD7DOWNTO0_intermed_1;
R_A_CTRL_RD7DOWNTO0_intermed_3 <= R_A_CTRL_RD7DOWNTO0_intermed_2;
RIN_E_CTRL_RD7DOWNTO0_intermed_1 <= RIN.E.CTRL.RD ( 7 DOWNTO 0 );
RIN_E_CTRL_RD7DOWNTO0_intermed_2 <= RIN_E_CTRL_RD7DOWNTO0_intermed_1;
RIN_E_CTRL_RD7DOWNTO0_intermed_3 <= RIN_E_CTRL_RD7DOWNTO0_intermed_2;
RIN_X_CTRL_RD7DOWNTO0_intermed_1 <= RIN.X.CTRL.RD ( 7 DOWNTO 0 );
RIN_M_CTRL_RD7DOWNTO0_intermed_1 <= RIN.M.CTRL.RD ( 7 DOWNTO 0 );
RIN_M_CTRL_RD7DOWNTO0_intermed_2 <= RIN_M_CTRL_RD7DOWNTO0_intermed_1;
RIN_X_CTRL_TRAP_intermed_1 <= RIN.X.CTRL.TRAP;
V_A_CTRL_TRAP_shadow_intermed_1 <= V_A_CTRL_TRAP_shadow;
V_A_CTRL_TRAP_shadow_intermed_2 <= V_A_CTRL_TRAP_shadow_intermed_1;
V_A_CTRL_TRAP_shadow_intermed_3 <= V_A_CTRL_TRAP_shadow_intermed_2;
V_A_CTRL_TRAP_shadow_intermed_4 <= V_A_CTRL_TRAP_shadow_intermed_3;
ICO_MEXC_intermed_1 <= ICO.MEXC;
ICO_MEXC_intermed_2 <= ICO_MEXC_intermed_1;
ICO_MEXC_intermed_3 <= ICO_MEXC_intermed_2;
ICO_MEXC_intermed_4 <= ICO_MEXC_intermed_3;
ICO_MEXC_intermed_5 <= ICO_MEXC_intermed_4;
R_E_CTRL_TRAP_intermed_1 <= R.E.CTRL.TRAP;
R_E_CTRL_TRAP_intermed_2 <= R_E_CTRL_TRAP_intermed_1;
RIN_A_CTRL_TRAP_intermed_1 <= RIN.A.CTRL.TRAP;
RIN_A_CTRL_TRAP_intermed_2 <= RIN_A_CTRL_TRAP_intermed_1;
RIN_A_CTRL_TRAP_intermed_3 <= RIN_A_CTRL_TRAP_intermed_2;
RIN_A_CTRL_TRAP_intermed_4 <= RIN_A_CTRL_TRAP_intermed_3;
V_E_CTRL_TRAP_shadow_intermed_1 <= V_E_CTRL_TRAP_shadow;
V_E_CTRL_TRAP_shadow_intermed_2 <= V_E_CTRL_TRAP_shadow_intermed_1;
V_E_CTRL_TRAP_shadow_intermed_3 <= V_E_CTRL_TRAP_shadow_intermed_2;
RIN_E_CTRL_TRAP_intermed_1 <= RIN.E.CTRL.TRAP;
RIN_E_CTRL_TRAP_intermed_2 <= RIN_E_CTRL_TRAP_intermed_1;
RIN_E_CTRL_TRAP_intermed_3 <= RIN_E_CTRL_TRAP_intermed_2;
R_D_MEXC_intermed_1 <= R.D.MEXC;
R_D_MEXC_intermed_2 <= R_D_MEXC_intermed_1;
R_D_MEXC_intermed_3 <= R_D_MEXC_intermed_2;
R_D_MEXC_intermed_4 <= R_D_MEXC_intermed_3;
V_M_CTRL_TRAP_shadow_intermed_1 <= V_M_CTRL_TRAP_shadow;
V_M_CTRL_TRAP_shadow_intermed_2 <= V_M_CTRL_TRAP_shadow_intermed_1;
V_D_MEXC_shadow_intermed_1 <= V_D_MEXC_shadow;
V_D_MEXC_shadow_intermed_2 <= V_D_MEXC_shadow_intermed_1;
V_D_MEXC_shadow_intermed_3 <= V_D_MEXC_shadow_intermed_2;
V_D_MEXC_shadow_intermed_4 <= V_D_MEXC_shadow_intermed_3;
V_D_MEXC_shadow_intermed_5 <= V_D_MEXC_shadow_intermed_4;
R_A_CTRL_TRAP_intermed_1 <= R.A.CTRL.TRAP;
R_A_CTRL_TRAP_intermed_2 <= R_A_CTRL_TRAP_intermed_1;
R_A_CTRL_TRAP_intermed_3 <= R_A_CTRL_TRAP_intermed_2;
RIN_M_CTRL_TRAP_intermed_1 <= RIN.M.CTRL.TRAP;
RIN_M_CTRL_TRAP_intermed_2 <= RIN_M_CTRL_TRAP_intermed_1;
R_M_CTRL_TRAP_intermed_1 <= R.M.CTRL.TRAP;
RIN_D_MEXC_intermed_1 <= RIN.D.MEXC;
RIN_D_MEXC_intermed_2 <= RIN_D_MEXC_intermed_1;
RIN_D_MEXC_intermed_3 <= RIN_D_MEXC_intermed_2;
RIN_D_MEXC_intermed_4 <= RIN_D_MEXC_intermed_3;
RIN_D_MEXC_intermed_5 <= RIN_D_MEXC_intermed_4;
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 );
V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow;
V_X_RESULT6DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO0_shadow_intermed_1;
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 );
RIN_X_RESULT6DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO0_intermed_1;
R_X_RESULT6DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 );
RIN_D_PC_intermed_1 <= RIN.D.PC;
RIN_D_PC_intermed_2 <= RIN_D_PC_intermed_1;
RIN_D_PC_intermed_3 <= RIN_D_PC_intermed_2;
RIN_D_PC_intermed_4 <= RIN_D_PC_intermed_3;
RIN_D_PC_intermed_5 <= RIN_D_PC_intermed_4;
RIN_A_CTRL_PC_intermed_1 <= RIN.A.CTRL.PC;
RIN_A_CTRL_PC_intermed_2 <= RIN_A_CTRL_PC_intermed_1;
RIN_A_CTRL_PC_intermed_3 <= RIN_A_CTRL_PC_intermed_2;
RIN_A_CTRL_PC_intermed_4 <= RIN_A_CTRL_PC_intermed_3;
R_A_CTRL_PC_intermed_1 <= R.A.CTRL.PC;
R_A_CTRL_PC_intermed_2 <= R_A_CTRL_PC_intermed_1;
R_A_CTRL_PC_intermed_3 <= R_A_CTRL_PC_intermed_2;
V_E_CTRL_PC_shadow_intermed_1 <= V_E_CTRL_PC_shadow;
V_E_CTRL_PC_shadow_intermed_2 <= V_E_CTRL_PC_shadow_intermed_1;
V_E_CTRL_PC_shadow_intermed_3 <= V_E_CTRL_PC_shadow_intermed_2;
R_M_CTRL_PC_intermed_1 <= R.M.CTRL.PC;
R_E_CTRL_PC_intermed_1 <= R.E.CTRL.PC;
R_E_CTRL_PC_intermed_2 <= R_E_CTRL_PC_intermed_1;
RIN_M_CTRL_PC_intermed_1 <= RIN.M.CTRL.PC;
RIN_M_CTRL_PC_intermed_2 <= RIN_M_CTRL_PC_intermed_1;
V_M_CTRL_PC_shadow_intermed_1 <= V_M_CTRL_PC_shadow;
V_M_CTRL_PC_shadow_intermed_2 <= V_M_CTRL_PC_shadow_intermed_1;
V_A_CTRL_PC_shadow_intermed_1 <= V_A_CTRL_PC_shadow;
V_A_CTRL_PC_shadow_intermed_2 <= V_A_CTRL_PC_shadow_intermed_1;
V_A_CTRL_PC_shadow_intermed_3 <= V_A_CTRL_PC_shadow_intermed_2;
V_A_CTRL_PC_shadow_intermed_4 <= V_A_CTRL_PC_shadow_intermed_3;
R_D_PC_intermed_1 <= R.D.PC;
R_D_PC_intermed_2 <= R_D_PC_intermed_1;
R_D_PC_intermed_3 <= R_D_PC_intermed_2;
R_D_PC_intermed_4 <= R_D_PC_intermed_3;
RIN_E_CTRL_PC_intermed_1 <= RIN.E.CTRL.PC;
RIN_E_CTRL_PC_intermed_2 <= RIN_E_CTRL_PC_intermed_1;
RIN_E_CTRL_PC_intermed_3 <= RIN_E_CTRL_PC_intermed_2;
RIN_X_CTRL_PC_intermed_1 <= RIN.X.CTRL.PC;
V_D_PC_shadow_intermed_1 <= V_D_PC_shadow;
V_D_PC_shadow_intermed_2 <= V_D_PC_shadow_intermed_1;
V_D_PC_shadow_intermed_3 <= V_D_PC_shadow_intermed_2;
V_D_PC_shadow_intermed_4 <= V_D_PC_shadow_intermed_3;
V_D_PC_shadow_intermed_5 <= V_D_PC_shadow_intermed_4;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2;
RIN_A_CTRL_ANNUL_intermed_4 <= RIN_A_CTRL_ANNUL_intermed_3;
RIN_A_CTRL_ANNUL_intermed_5 <= RIN_A_CTRL_ANNUL_intermed_4;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1;
R_A_CTRL_ANNUL_intermed_3 <= R_A_CTRL_ANNUL_intermed_2;
R_A_CTRL_ANNUL_intermed_4 <= R_A_CTRL_ANNUL_intermed_3;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
R_X_ANNUL_ALL_intermed_2 <= R_X_ANNUL_ALL_intermed_1;
R_X_ANNUL_ALL_intermed_3 <= R_X_ANNUL_ALL_intermed_2;
R_X_ANNUL_ALL_intermed_4 <= R_X_ANNUL_ALL_intermed_3;
RIN_X_CTRL_WREG_intermed_1 <= RIN.X.CTRL.WREG;
RIN_M_CTRL_WREG_intermed_1 <= RIN.M.CTRL.WREG;
RIN_M_CTRL_WREG_intermed_2 <= RIN_M_CTRL_WREG_intermed_1;
RIN_A_CTRL_WREG_intermed_1 <= RIN.A.CTRL.WREG;
RIN_A_CTRL_WREG_intermed_2 <= RIN_A_CTRL_WREG_intermed_1;
RIN_A_CTRL_WREG_intermed_3 <= RIN_A_CTRL_WREG_intermed_2;
RIN_A_CTRL_WREG_intermed_4 <= RIN_A_CTRL_WREG_intermed_3;
V_A_CTRL_WREG_shadow_intermed_1 <= V_A_CTRL_WREG_shadow;
V_A_CTRL_WREG_shadow_intermed_2 <= V_A_CTRL_WREG_shadow_intermed_1;
V_A_CTRL_WREG_shadow_intermed_3 <= V_A_CTRL_WREG_shadow_intermed_2;
V_A_CTRL_WREG_shadow_intermed_4 <= V_A_CTRL_WREG_shadow_intermed_3;
R_A_CTRL_WREG_intermed_1 <= R.A.CTRL.WREG;
R_A_CTRL_WREG_intermed_2 <= R_A_CTRL_WREG_intermed_1;
R_A_CTRL_WREG_intermed_3 <= R_A_CTRL_WREG_intermed_2;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
V_X_ANNUL_ALL_shadow_intermed_2 <= V_X_ANNUL_ALL_shadow_intermed_1;
V_X_ANNUL_ALL_shadow_intermed_3 <= V_X_ANNUL_ALL_shadow_intermed_2;
V_X_ANNUL_ALL_shadow_intermed_4 <= V_X_ANNUL_ALL_shadow_intermed_3;
R_M_CTRL_WREG_intermed_1 <= R.M.CTRL.WREG;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
RIN_X_ANNUL_ALL_intermed_3 <= RIN_X_ANNUL_ALL_intermed_2;
RIN_X_ANNUL_ALL_intermed_4 <= RIN_X_ANNUL_ALL_intermed_3;
RIN_X_ANNUL_ALL_intermed_5 <= RIN_X_ANNUL_ALL_intermed_4;
V_M_CTRL_WREG_shadow_intermed_1 <= V_M_CTRL_WREG_shadow;
V_M_CTRL_WREG_shadow_intermed_2 <= V_M_CTRL_WREG_shadow_intermed_1;
R_E_CTRL_WREG_intermed_1 <= R.E.CTRL.WREG;
R_E_CTRL_WREG_intermed_2 <= R_E_CTRL_WREG_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_3 <= V_A_CTRL_ANNUL_shadow_intermed_2;
V_A_CTRL_ANNUL_shadow_intermed_4 <= V_A_CTRL_ANNUL_shadow_intermed_3;
RIN_E_CTRL_WREG_intermed_1 <= RIN.E.CTRL.WREG;
RIN_E_CTRL_WREG_intermed_2 <= RIN_E_CTRL_WREG_intermed_1;
RIN_E_CTRL_WREG_intermed_3 <= RIN_E_CTRL_WREG_intermed_2;
V_E_CTRL_WREG_shadow_intermed_1 <= V_E_CTRL_WREG_shadow;
V_E_CTRL_WREG_shadow_intermed_2 <= V_E_CTRL_WREG_shadow_intermed_1;
V_E_CTRL_WREG_shadow_intermed_3 <= V_E_CTRL_WREG_shadow_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC ( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC ( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC ( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC ( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC ( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC ( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
V_X_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_X_CTRL_TT3DOWNTO0_shadow;
V_X_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_X_CTRL_TT3DOWNTO0_shadow_intermed_1;
R_M_CTRL_TT3DOWNTO0_intermed_1 <= R.M.CTRL.TT( 3 DOWNTO 0 );
R_M_CTRL_TT3DOWNTO0_intermed_2 <= R_M_CTRL_TT3DOWNTO0_intermed_1;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_3 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2;
R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
R_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= R_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
R_A_CTRL_TT3DOWNTO0_intermed_1 <= R.A.CTRL.TT( 3 DOWNTO 0 );
R_A_CTRL_TT3DOWNTO0_intermed_2 <= R_A_CTRL_TT3DOWNTO0_intermed_1;
R_A_CTRL_TT3DOWNTO0_intermed_3 <= R_A_CTRL_TT3DOWNTO0_intermed_2;
R_A_CTRL_TT3DOWNTO0_intermed_4 <= R_A_CTRL_TT3DOWNTO0_intermed_3;
RIN_A_CTRL_TT3DOWNTO0_intermed_1 <= RIN.A.CTRL.TT( 3 DOWNTO 0 );
RIN_A_CTRL_TT3DOWNTO0_intermed_2 <= RIN_A_CTRL_TT3DOWNTO0_intermed_1;
RIN_A_CTRL_TT3DOWNTO0_intermed_3 <= RIN_A_CTRL_TT3DOWNTO0_intermed_2;
RIN_A_CTRL_TT3DOWNTO0_intermed_4 <= RIN_A_CTRL_TT3DOWNTO0_intermed_3;
RIN_A_CTRL_TT3DOWNTO0_intermed_5 <= RIN_A_CTRL_TT3DOWNTO0_intermed_4;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_A_CTRL_TT3DOWNTO0_shadow;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_2;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_4 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_3;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_5 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_4;
RIN_W_S_TT3DOWNTO0_intermed_1 <= RIN.W.S.TT( 3 DOWNTO 0 );
RIN_W_S_TT3DOWNTO0_intermed_2 <= RIN_W_S_TT3DOWNTO0_intermed_1;
R_E_CTRL_TT3DOWNTO0_intermed_1 <= R.E.CTRL.TT( 3 DOWNTO 0 );
R_E_CTRL_TT3DOWNTO0_intermed_2 <= R_E_CTRL_TT3DOWNTO0_intermed_1;
R_E_CTRL_TT3DOWNTO0_intermed_3 <= R_E_CTRL_TT3DOWNTO0_intermed_2;
RIN_W_S_TT3DOWNTO0_intermed_1 <= RIN.W.S.TT ( 3 DOWNTO 0 );
RIN_M_CTRL_TT3DOWNTO0_intermed_1 <= RIN.M.CTRL.TT( 3 DOWNTO 0 );
RIN_M_CTRL_TT3DOWNTO0_intermed_2 <= RIN_M_CTRL_TT3DOWNTO0_intermed_1;
RIN_M_CTRL_TT3DOWNTO0_intermed_3 <= RIN_M_CTRL_TT3DOWNTO0_intermed_2;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_M_CTRL_TT3DOWNTO0_shadow;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_M_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_M_CTRL_TT3DOWNTO0_shadow_intermed_2;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_3 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
R_W_S_TT3DOWNTO0_intermed_1 <= R.W.S.TT( 3 DOWNTO 0 );
R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 );
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_E_CTRL_TT3DOWNTO0_shadow;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_2;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_4 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_3;
RIN_X_CTRL_TT3DOWNTO0_intermed_1 <= RIN.X.CTRL.TT( 3 DOWNTO 0 );
RIN_X_CTRL_TT3DOWNTO0_intermed_2 <= RIN_X_CTRL_TT3DOWNTO0_intermed_1;
V_W_S_TT3DOWNTO0_shadow_intermed_1 <= V_W_S_TT3DOWNTO0_shadow;
V_W_S_TT3DOWNTO0_shadow_intermed_2 <= V_W_S_TT3DOWNTO0_shadow_intermed_1;
R_X_CTRL_TT3DOWNTO0_intermed_1 <= R.X.CTRL.TT( 3 DOWNTO 0 );
RIN_E_CTRL_TT3DOWNTO0_intermed_1 <= RIN.E.CTRL.TT( 3 DOWNTO 0 );
RIN_E_CTRL_TT3DOWNTO0_intermed_2 <= RIN_E_CTRL_TT3DOWNTO0_intermed_1;
RIN_E_CTRL_TT3DOWNTO0_intermed_3 <= RIN_E_CTRL_TT3DOWNTO0_intermed_2;
RIN_E_CTRL_TT3DOWNTO0_intermed_4 <= RIN_E_CTRL_TT3DOWNTO0_intermed_3;
XC_VECTT3DOWNTO0_shadow_intermed_1 <= XC_VECTT3DOWNTO0_shadow;
V_M_RESULT1DOWNTO0_shadow_intermed_1 <= V_M_RESULT1DOWNTO0_shadow;
V_M_RESULT1DOWNTO0_shadow_intermed_2 <= V_M_RESULT1DOWNTO0_shadow_intermed_1;
RIN_M_RESULT1DOWNTO0_intermed_1 <= RIN.M.RESULT( 1 DOWNTO 0 );
RIN_M_RESULT1DOWNTO0_intermed_2 <= RIN_M_RESULT1DOWNTO0_intermed_1;
R_M_RESULT1DOWNTO0_intermed_1 <= R.M.RESULT( 1 DOWNTO 0 );
RIN_M_RESULT1DOWNTO0_intermed_1 <= RIN.M.RESULT ( 1 DOWNTO 0 );
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
V_X_DATA031_shadow_intermed_3 <= V_X_DATA031_shadow_intermed_2;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
RIN_X_DATA031_intermed_3 <= RIN_X_DATA031_intermed_2;
DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 );
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 ) ( 31 );
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
R_X_DATA031_intermed_2 <= R_X_DATA031_intermed_1;
R_X_DATA031_intermed_1 <= R.X.DATA ( 0 )( 31 );
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 );
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_A_CTRL_INST19_shadow_intermed_3 <= V_A_CTRL_INST19_shadow_intermed_2;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_CTRL_INST19_shadow_intermed_2 <= V_E_CTRL_INST19_shadow_intermed_1;
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
RIN_A_CTRL_INST19_intermed_3 <= RIN_A_CTRL_INST19_intermed_2;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST ( 19 );
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST( 19 );
RIN_E_CTRL_INST19_intermed_2 <= RIN_E_CTRL_INST19_intermed_1;
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
DE_INST19_shadow_intermed_2 <= DE_INST19_shadow_intermed_1;
R_E_CTRL_INST19_intermed_1 <= R.E.CTRL.INST( 19 );
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
R_A_CTRL_INST19_intermed_2 <= R_A_CTRL_INST19_intermed_1;
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST ( 19 );
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST ( 20 );
RIN_A_CTRL_INST20_intermed_2 <= RIN_A_CTRL_INST20_intermed_1;
R_A_CTRL_INST20_intermed_1 <= R.A.CTRL.INST ( 20 );
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST( 20 );
RIN_A_CTRL_INST20_intermed_2 <= RIN_A_CTRL_INST20_intermed_1;
RIN_A_CTRL_INST20_intermed_3 <= RIN_A_CTRL_INST20_intermed_2;
V_E_CTRL_INST20_shadow_intermed_1 <= V_E_CTRL_INST20_shadow;
V_E_CTRL_INST20_shadow_intermed_2 <= V_E_CTRL_INST20_shadow_intermed_1;
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
V_A_CTRL_INST20_shadow_intermed_2 <= V_A_CTRL_INST20_shadow_intermed_1;
V_A_CTRL_INST20_shadow_intermed_3 <= V_A_CTRL_INST20_shadow_intermed_2;
RIN_E_CTRL_INST20_intermed_1 <= RIN.E.CTRL.INST( 20 );
RIN_E_CTRL_INST20_intermed_2 <= RIN_E_CTRL_INST20_intermed_1;
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
V_A_CTRL_INST20_shadow_intermed_2 <= V_A_CTRL_INST20_shadow_intermed_1;
RIN_E_CTRL_INST20_intermed_1 <= RIN.E.CTRL.INST ( 20 );
R_E_CTRL_INST20_intermed_1 <= R.E.CTRL.INST( 20 );
DE_INST20_shadow_intermed_1 <= DE_INST20_shadow;
DE_INST20_shadow_intermed_2 <= DE_INST20_shadow_intermed_1;
R_A_CTRL_INST20_intermed_1 <= R.A.CTRL.INST( 20 );
R_A_CTRL_INST20_intermed_2 <= R_A_CTRL_INST20_intermed_1;
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
V_X_DATA00_shadow_intermed_2 <= V_X_DATA00_shadow_intermed_1;
RIN_X_DATA00_intermed_1 <= RIN.X.DATA ( 0 ) ( 0 );
R_X_DATA00_intermed_1 <= R.X.DATA( 0 )( 0 );
R_X_DATA00_intermed_2 <= R_X_DATA00_intermed_1;
RIN_X_DATA00_intermed_1 <= RIN.X.DATA ( 0 )( 0 );
RIN_X_DATA00_intermed_2 <= RIN_X_DATA00_intermed_1;
DCO_DATA00_intermed_1 <= DCO.DATA ( 0 )( 0 );
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
V_X_DATA00_shadow_intermed_2 <= V_X_DATA00_shadow_intermed_1;
V_X_DATA00_shadow_intermed_3 <= V_X_DATA00_shadow_intermed_2;
R_X_DATA00_intermed_1 <= R.X.DATA ( 0 )( 0 );
RIN_X_DATA00_intermed_1 <= RIN.X.DATA( 0 )( 0 );
RIN_X_DATA00_intermed_2 <= RIN_X_DATA00_intermed_1;
RIN_X_DATA00_intermed_3 <= RIN_X_DATA00_intermed_2;
R_X_DATA00_intermed_1 <= R.X.DATA( 0 )( 0 );
RIN_X_DATA00_intermed_1 <= RIN.X.DATA ( 0 )( 0 );
DCO_DATA00_intermed_1 <= DCO.DATA ( 0 )( 0 );
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
V_X_DATA00_shadow_intermed_2 <= V_X_DATA00_shadow_intermed_1;
RIN_X_DATA00_intermed_1 <= RIN.X.DATA( 0 )( 0 );
RIN_X_DATA00_intermed_2 <= RIN_X_DATA00_intermed_1;
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA ( 0 ) ( 4 DOWNTO 0 );
R_X_DATA04DOWNTO0_intermed_1 <= R.X.DATA( 0 )( 4 DOWNTO 0 );
R_X_DATA04DOWNTO0_intermed_2 <= R_X_DATA04DOWNTO0_intermed_1;
R_X_DATA04DOWNTO0_intermed_1 <= R.X.DATA ( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_2 <= RIN_X_DATA04DOWNTO0_intermed_1;
RIN_X_DATA04DOWNTO0_intermed_3 <= RIN_X_DATA04DOWNTO0_intermed_2;
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
V_X_DATA04DOWNTO0_shadow_intermed_2 <= V_X_DATA04DOWNTO0_shadow_intermed_1;
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
V_X_DATA04DOWNTO0_shadow_intermed_2 <= V_X_DATA04DOWNTO0_shadow_intermed_1;
V_X_DATA04DOWNTO0_shadow_intermed_3 <= V_X_DATA04DOWNTO0_shadow_intermed_2;
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA ( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_2 <= RIN_X_DATA04DOWNTO0_intermed_1;
DCO_DATA04DOWNTO0_intermed_1 <= DCO.DATA ( 0 )( 4 DOWNTO 0 );
R_X_DATA04DOWNTO0_intermed_1 <= R.X.DATA( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_2 <= RIN_X_DATA04DOWNTO0_intermed_1;
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
V_X_DATA04DOWNTO0_shadow_intermed_2 <= V_X_DATA04DOWNTO0_shadow_intermed_1;
DCO_DATA04DOWNTO0_intermed_1 <= DCO.DATA ( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA ( 0 )( 4 DOWNTO 0 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC ( 31 DOWNTO 2 );
R_A_CTRL_INST24_intermed_1 <= R.A.CTRL.INST( 24 );
R_A_CTRL_INST24_intermed_2 <= R_A_CTRL_INST24_intermed_1;
RIN_E_CTRL_INST24_intermed_1 <= RIN.E.CTRL.INST( 24 );
RIN_E_CTRL_INST24_intermed_2 <= RIN_E_CTRL_INST24_intermed_1;
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST( 24 );
RIN_A_CTRL_INST24_intermed_2 <= RIN_A_CTRL_INST24_intermed_1;
RIN_A_CTRL_INST24_intermed_3 <= RIN_A_CTRL_INST24_intermed_2;
R_E_CTRL_INST24_intermed_1 <= R.E.CTRL.INST( 24 );
R_A_CTRL_INST24_intermed_1 <= R.A.CTRL.INST ( 24 );
V_A_CTRL_INST24_shadow_intermed_1 <= V_A_CTRL_INST24_shadow;
V_A_CTRL_INST24_shadow_intermed_2 <= V_A_CTRL_INST24_shadow_intermed_1;
V_A_CTRL_INST24_shadow_intermed_3 <= V_A_CTRL_INST24_shadow_intermed_2;
V_E_CTRL_INST24_shadow_intermed_1 <= V_E_CTRL_INST24_shadow;
V_E_CTRL_INST24_shadow_intermed_2 <= V_E_CTRL_INST24_shadow_intermed_1;
DE_INST24_shadow_intermed_1 <= DE_INST24_shadow;
DE_INST24_shadow_intermed_2 <= DE_INST24_shadow_intermed_1;
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST ( 24 );
RIN_A_CTRL_INST24_intermed_2 <= RIN_A_CTRL_INST24_intermed_1;
V_A_CTRL_INST24_shadow_intermed_1 <= V_A_CTRL_INST24_shadow;
V_A_CTRL_INST24_shadow_intermed_2 <= V_A_CTRL_INST24_shadow_intermed_1;
RIN_E_CTRL_INST24_intermed_1 <= RIN.E.CTRL.INST ( 24 );
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
RIN_M_Y31_intermed_1 <= RIN.M.Y ( 31 );
V_M_Y31_shadow_intermed_1 <= V_M_Y31_shadow;
V_M_Y31_shadow_intermed_2 <= V_M_Y31_shadow_intermed_1;
RIN_M_Y31_intermed_1 <= RIN.M.Y( 31 );
RIN_M_Y31_intermed_2 <= RIN_M_Y31_intermed_1;
R_M_Y31_intermed_1 <= R.M.Y( 31 );
DSUIN_CRDY2_intermed_1 <= DSUIN.CRDY ( 2 );
VDSU_CRDY2_shadow_intermed_1 <= VDSU_CRDY2_shadow;
VDSU_CRDY2_shadow_intermed_2 <= VDSU_CRDY2_shadow_intermed_1;
DSUIN_CRDY2_intermed_1 <= DSUIN.CRDY( 2 );
DSUIN_CRDY2_intermed_2 <= DSUIN_CRDY2_intermed_1;
DSUR_CRDY2_intermed_1 <= DSUR.CRDY( 2 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC ( 31 DOWNTO 2 );
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
DE_INST_shadow_intermed_1 <= DE_INST_shadow;
DE_INST_shadow_intermed_2 <= DE_INST_shadow_intermed_1;
V_A_CTRL_INST_shadow_intermed_1 <= V_A_CTRL_INST_shadow;
V_A_CTRL_INST_shadow_intermed_2 <= V_A_CTRL_INST_shadow_intermed_1;
RIN_A_CTRL_INST_intermed_1 <= RIN.A.CTRL.INST;
RIN_A_CTRL_INST_intermed_2 <= RIN_A_CTRL_INST_intermed_1;
RIN_E_CTRL_INST_intermed_1 <= RIN.E.CTRL.INST;
R_A_CTRL_INST_intermed_1 <= R.A.CTRL.INST;
RIN_D_CNT_intermed_1 <= RIN.D.CNT;
RIN_D_CNT_intermed_2 <= RIN_D_CNT_intermed_1;
RIN_D_CNT_intermed_3 <= RIN_D_CNT_intermed_2;
V_A_CTRL_CNT_shadow_intermed_1 <= V_A_CTRL_CNT_shadow;
V_A_CTRL_CNT_shadow_intermed_2 <= V_A_CTRL_CNT_shadow_intermed_1;
R_A_CTRL_CNT_intermed_1 <= R.A.CTRL.CNT;
V_D_CNT_shadow_intermed_1 <= V_D_CNT_shadow;
V_D_CNT_shadow_intermed_2 <= V_D_CNT_shadow_intermed_1;
V_D_CNT_shadow_intermed_3 <= V_D_CNT_shadow_intermed_2;
R_D_CNT_intermed_1 <= R.D.CNT;
R_D_CNT_intermed_2 <= R_D_CNT_intermed_1;
RIN_A_CTRL_CNT_intermed_1 <= RIN.A.CTRL.CNT;
RIN_A_CTRL_CNT_intermed_2 <= RIN_A_CTRL_CNT_intermed_1;
RIN_E_CTRL_CNT_intermed_1 <= RIN.E.CTRL.CNT;
V_A_CTRL_TRAP_shadow_intermed_1 <= V_A_CTRL_TRAP_shadow;
V_A_CTRL_TRAP_shadow_intermed_2 <= V_A_CTRL_TRAP_shadow_intermed_1;
ICO_MEXC_intermed_1 <= ICO.MEXC;
ICO_MEXC_intermed_2 <= ICO_MEXC_intermed_1;
ICO_MEXC_intermed_3 <= ICO_MEXC_intermed_2;
RIN_A_CTRL_TRAP_intermed_1 <= RIN.A.CTRL.TRAP;
RIN_A_CTRL_TRAP_intermed_2 <= RIN_A_CTRL_TRAP_intermed_1;
RIN_E_CTRL_TRAP_intermed_1 <= RIN.E.CTRL.TRAP;
R_D_MEXC_intermed_1 <= R.D.MEXC;
R_D_MEXC_intermed_2 <= R_D_MEXC_intermed_1;
V_D_MEXC_shadow_intermed_1 <= V_D_MEXC_shadow;
V_D_MEXC_shadow_intermed_2 <= V_D_MEXC_shadow_intermed_1;
V_D_MEXC_shadow_intermed_3 <= V_D_MEXC_shadow_intermed_2;
R_A_CTRL_TRAP_intermed_1 <= R.A.CTRL.TRAP;
RIN_D_MEXC_intermed_1 <= RIN.D.MEXC;
RIN_D_MEXC_intermed_2 <= RIN_D_MEXC_intermed_1;
RIN_D_MEXC_intermed_3 <= RIN_D_MEXC_intermed_2;
R_A_CTRL_PV_intermed_1 <= R.A.CTRL.PV;
RIN_E_CTRL_PV_intermed_1 <= RIN.E.CTRL.PV;
V_A_CTRL_PV_shadow_intermed_1 <= V_A_CTRL_PV_shadow;
V_A_CTRL_PV_shadow_intermed_2 <= V_A_CTRL_PV_shadow_intermed_1;
RIN_A_CTRL_PV_intermed_1 <= RIN.A.CTRL.PV;
RIN_A_CTRL_PV_intermed_2 <= RIN_A_CTRL_PV_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC ( 31 DOWNTO 2 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC ( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC ( 31 DOWNTO 2 );
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC ( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_E_CTRL_INST_intermed_1 <= R.E.CTRL.INST;
DE_INST_shadow_intermed_1 <= DE_INST_shadow;
DE_INST_shadow_intermed_2 <= DE_INST_shadow_intermed_1;
DE_INST_shadow_intermed_3 <= DE_INST_shadow_intermed_2;
V_A_CTRL_INST_shadow_intermed_1 <= V_A_CTRL_INST_shadow;
V_A_CTRL_INST_shadow_intermed_2 <= V_A_CTRL_INST_shadow_intermed_1;
V_A_CTRL_INST_shadow_intermed_3 <= V_A_CTRL_INST_shadow_intermed_2;
V_E_CTRL_INST_shadow_intermed_1 <= V_E_CTRL_INST_shadow;
V_E_CTRL_INST_shadow_intermed_2 <= V_E_CTRL_INST_shadow_intermed_1;
RIN_A_CTRL_INST_intermed_1 <= RIN.A.CTRL.INST;
RIN_A_CTRL_INST_intermed_2 <= RIN_A_CTRL_INST_intermed_1;
RIN_A_CTRL_INST_intermed_3 <= RIN_A_CTRL_INST_intermed_2;
RIN_M_CTRL_INST_intermed_1 <= RIN.M.CTRL.INST;
RIN_E_CTRL_INST_intermed_1 <= RIN.E.CTRL.INST;
RIN_E_CTRL_INST_intermed_2 <= RIN_E_CTRL_INST_intermed_1;
R_A_CTRL_INST_intermed_1 <= R.A.CTRL.INST;
R_A_CTRL_INST_intermed_2 <= R_A_CTRL_INST_intermed_1;
V_E_CTRL_CNT_shadow_intermed_1 <= V_E_CTRL_CNT_shadow;
V_E_CTRL_CNT_shadow_intermed_2 <= V_E_CTRL_CNT_shadow_intermed_1;
RIN_D_CNT_intermed_1 <= RIN.D.CNT;
RIN_D_CNT_intermed_2 <= RIN_D_CNT_intermed_1;
RIN_D_CNT_intermed_3 <= RIN_D_CNT_intermed_2;
RIN_D_CNT_intermed_4 <= RIN_D_CNT_intermed_3;
V_A_CTRL_CNT_shadow_intermed_1 <= V_A_CTRL_CNT_shadow;
V_A_CTRL_CNT_shadow_intermed_2 <= V_A_CTRL_CNT_shadow_intermed_1;
V_A_CTRL_CNT_shadow_intermed_3 <= V_A_CTRL_CNT_shadow_intermed_2;
R_A_CTRL_CNT_intermed_1 <= R.A.CTRL.CNT;
R_A_CTRL_CNT_intermed_2 <= R_A_CTRL_CNT_intermed_1;
V_D_CNT_shadow_intermed_1 <= V_D_CNT_shadow;
V_D_CNT_shadow_intermed_2 <= V_D_CNT_shadow_intermed_1;
V_D_CNT_shadow_intermed_3 <= V_D_CNT_shadow_intermed_2;
V_D_CNT_shadow_intermed_4 <= V_D_CNT_shadow_intermed_3;
R_D_CNT_intermed_1 <= R.D.CNT;
R_D_CNT_intermed_2 <= R_D_CNT_intermed_1;
R_D_CNT_intermed_3 <= R_D_CNT_intermed_2;
R_E_CTRL_CNT_intermed_1 <= R.E.CTRL.CNT;
RIN_A_CTRL_CNT_intermed_1 <= RIN.A.CTRL.CNT;
RIN_A_CTRL_CNT_intermed_2 <= RIN_A_CTRL_CNT_intermed_1;
RIN_A_CTRL_CNT_intermed_3 <= RIN_A_CTRL_CNT_intermed_2;
RIN_M_CTRL_CNT_intermed_1 <= RIN.M.CTRL.CNT;
RIN_E_CTRL_CNT_intermed_1 <= RIN.E.CTRL.CNT;
RIN_E_CTRL_CNT_intermed_2 <= RIN_E_CTRL_CNT_intermed_1;
V_A_CTRL_TRAP_shadow_intermed_1 <= V_A_CTRL_TRAP_shadow;
V_A_CTRL_TRAP_shadow_intermed_2 <= V_A_CTRL_TRAP_shadow_intermed_1;
V_A_CTRL_TRAP_shadow_intermed_3 <= V_A_CTRL_TRAP_shadow_intermed_2;
ICO_MEXC_intermed_1 <= ICO.MEXC;
ICO_MEXC_intermed_2 <= ICO_MEXC_intermed_1;
ICO_MEXC_intermed_3 <= ICO_MEXC_intermed_2;
ICO_MEXC_intermed_4 <= ICO_MEXC_intermed_3;
R_E_CTRL_TRAP_intermed_1 <= R.E.CTRL.TRAP;
RIN_A_CTRL_TRAP_intermed_1 <= RIN.A.CTRL.TRAP;
RIN_A_CTRL_TRAP_intermed_2 <= RIN_A_CTRL_TRAP_intermed_1;
RIN_A_CTRL_TRAP_intermed_3 <= RIN_A_CTRL_TRAP_intermed_2;
V_E_CTRL_TRAP_shadow_intermed_1 <= V_E_CTRL_TRAP_shadow;
V_E_CTRL_TRAP_shadow_intermed_2 <= V_E_CTRL_TRAP_shadow_intermed_1;
RIN_E_CTRL_TRAP_intermed_1 <= RIN.E.CTRL.TRAP;
RIN_E_CTRL_TRAP_intermed_2 <= RIN_E_CTRL_TRAP_intermed_1;
R_D_MEXC_intermed_1 <= R.D.MEXC;
R_D_MEXC_intermed_2 <= R_D_MEXC_intermed_1;
R_D_MEXC_intermed_3 <= R_D_MEXC_intermed_2;
V_D_MEXC_shadow_intermed_1 <= V_D_MEXC_shadow;
V_D_MEXC_shadow_intermed_2 <= V_D_MEXC_shadow_intermed_1;
V_D_MEXC_shadow_intermed_3 <= V_D_MEXC_shadow_intermed_2;
V_D_MEXC_shadow_intermed_4 <= V_D_MEXC_shadow_intermed_3;
R_A_CTRL_TRAP_intermed_1 <= R.A.CTRL.TRAP;
R_A_CTRL_TRAP_intermed_2 <= R_A_CTRL_TRAP_intermed_1;
RIN_M_CTRL_TRAP_intermed_1 <= RIN.M.CTRL.TRAP;
RIN_D_MEXC_intermed_1 <= RIN.D.MEXC;
RIN_D_MEXC_intermed_2 <= RIN_D_MEXC_intermed_1;
RIN_D_MEXC_intermed_3 <= RIN_D_MEXC_intermed_2;
RIN_D_MEXC_intermed_4 <= RIN_D_MEXC_intermed_3;
V_E_CTRL_PV_shadow_intermed_1 <= V_E_CTRL_PV_shadow;
V_E_CTRL_PV_shadow_intermed_2 <= V_E_CTRL_PV_shadow_intermed_1;
R_E_CTRL_PV_intermed_1 <= R.E.CTRL.PV;
R_A_CTRL_PV_intermed_1 <= R.A.CTRL.PV;
R_A_CTRL_PV_intermed_2 <= R_A_CTRL_PV_intermed_1;
RIN_E_CTRL_PV_intermed_1 <= RIN.E.CTRL.PV;
RIN_E_CTRL_PV_intermed_2 <= RIN_E_CTRL_PV_intermed_1;
RIN_M_CTRL_PV_intermed_1 <= RIN.M.CTRL.PV;
V_A_CTRL_PV_shadow_intermed_1 <= V_A_CTRL_PV_shadow;
V_A_CTRL_PV_shadow_intermed_2 <= V_A_CTRL_PV_shadow_intermed_1;
V_A_CTRL_PV_shadow_intermed_3 <= V_A_CTRL_PV_shadow_intermed_2;
RIN_A_CTRL_PV_intermed_1 <= RIN.A.CTRL.PV;
RIN_A_CTRL_PV_intermed_2 <= RIN_A_CTRL_PV_intermed_1;
RIN_A_CTRL_PV_intermed_3 <= RIN_A_CTRL_PV_intermed_2;
R_E_CTRL_INST_intermed_1 <= R.E.CTRL.INST;
R_E_CTRL_INST_intermed_2 <= R_E_CTRL_INST_intermed_1;
R_M_CTRL_INST_intermed_1 <= R.M.CTRL.INST;
DE_INST_shadow_intermed_1 <= DE_INST_shadow;
DE_INST_shadow_intermed_2 <= DE_INST_shadow_intermed_1;
DE_INST_shadow_intermed_3 <= DE_INST_shadow_intermed_2;
DE_INST_shadow_intermed_4 <= DE_INST_shadow_intermed_3;
V_A_CTRL_INST_shadow_intermed_1 <= V_A_CTRL_INST_shadow;
V_A_CTRL_INST_shadow_intermed_2 <= V_A_CTRL_INST_shadow_intermed_1;
V_A_CTRL_INST_shadow_intermed_3 <= V_A_CTRL_INST_shadow_intermed_2;
V_A_CTRL_INST_shadow_intermed_4 <= V_A_CTRL_INST_shadow_intermed_3;
V_E_CTRL_INST_shadow_intermed_1 <= V_E_CTRL_INST_shadow;
V_E_CTRL_INST_shadow_intermed_2 <= V_E_CTRL_INST_shadow_intermed_1;
V_E_CTRL_INST_shadow_intermed_3 <= V_E_CTRL_INST_shadow_intermed_2;
RIN_X_CTRL_INST_intermed_1 <= RIN.X.CTRL.INST;
RIN_A_CTRL_INST_intermed_1 <= RIN.A.CTRL.INST;
RIN_A_CTRL_INST_intermed_2 <= RIN_A_CTRL_INST_intermed_1;
RIN_A_CTRL_INST_intermed_3 <= RIN_A_CTRL_INST_intermed_2;
RIN_A_CTRL_INST_intermed_4 <= RIN_A_CTRL_INST_intermed_3;
RIN_M_CTRL_INST_intermed_1 <= RIN.M.CTRL.INST;
RIN_M_CTRL_INST_intermed_2 <= RIN_M_CTRL_INST_intermed_1;
RIN_E_CTRL_INST_intermed_1 <= RIN.E.CTRL.INST;
RIN_E_CTRL_INST_intermed_2 <= RIN_E_CTRL_INST_intermed_1;
RIN_E_CTRL_INST_intermed_3 <= RIN_E_CTRL_INST_intermed_2;
V_M_CTRL_INST_shadow_intermed_1 <= V_M_CTRL_INST_shadow;
V_M_CTRL_INST_shadow_intermed_2 <= V_M_CTRL_INST_shadow_intermed_1;
R_A_CTRL_INST_intermed_1 <= R.A.CTRL.INST;
R_A_CTRL_INST_intermed_2 <= R_A_CTRL_INST_intermed_1;
R_A_CTRL_INST_intermed_3 <= R_A_CTRL_INST_intermed_2;
V_E_CTRL_CNT_shadow_intermed_1 <= V_E_CTRL_CNT_shadow;
V_E_CTRL_CNT_shadow_intermed_2 <= V_E_CTRL_CNT_shadow_intermed_1;
V_E_CTRL_CNT_shadow_intermed_3 <= V_E_CTRL_CNT_shadow_intermed_2;
RIN_D_CNT_intermed_1 <= RIN.D.CNT;
RIN_D_CNT_intermed_2 <= RIN_D_CNT_intermed_1;
RIN_D_CNT_intermed_3 <= RIN_D_CNT_intermed_2;
RIN_D_CNT_intermed_4 <= RIN_D_CNT_intermed_3;
RIN_D_CNT_intermed_5 <= RIN_D_CNT_intermed_4;
R_M_CTRL_CNT_intermed_1 <= R.M.CTRL.CNT;
V_A_CTRL_CNT_shadow_intermed_1 <= V_A_CTRL_CNT_shadow;
V_A_CTRL_CNT_shadow_intermed_2 <= V_A_CTRL_CNT_shadow_intermed_1;
V_A_CTRL_CNT_shadow_intermed_3 <= V_A_CTRL_CNT_shadow_intermed_2;
V_A_CTRL_CNT_shadow_intermed_4 <= V_A_CTRL_CNT_shadow_intermed_3;
R_A_CTRL_CNT_intermed_1 <= R.A.CTRL.CNT;
R_A_CTRL_CNT_intermed_2 <= R_A_CTRL_CNT_intermed_1;
R_A_CTRL_CNT_intermed_3 <= R_A_CTRL_CNT_intermed_2;
V_D_CNT_shadow_intermed_1 <= V_D_CNT_shadow;
V_D_CNT_shadow_intermed_2 <= V_D_CNT_shadow_intermed_1;
V_D_CNT_shadow_intermed_3 <= V_D_CNT_shadow_intermed_2;
V_D_CNT_shadow_intermed_4 <= V_D_CNT_shadow_intermed_3;
V_D_CNT_shadow_intermed_5 <= V_D_CNT_shadow_intermed_4;
R_D_CNT_intermed_1 <= R.D.CNT;
R_D_CNT_intermed_2 <= R_D_CNT_intermed_1;
R_D_CNT_intermed_3 <= R_D_CNT_intermed_2;
R_D_CNT_intermed_4 <= R_D_CNT_intermed_3;
R_E_CTRL_CNT_intermed_1 <= R.E.CTRL.CNT;
R_E_CTRL_CNT_intermed_2 <= R_E_CTRL_CNT_intermed_1;
RIN_X_CTRL_CNT_intermed_1 <= RIN.X.CTRL.CNT;
RIN_A_CTRL_CNT_intermed_1 <= RIN.A.CTRL.CNT;
RIN_A_CTRL_CNT_intermed_2 <= RIN_A_CTRL_CNT_intermed_1;
RIN_A_CTRL_CNT_intermed_3 <= RIN_A_CTRL_CNT_intermed_2;
RIN_A_CTRL_CNT_intermed_4 <= RIN_A_CTRL_CNT_intermed_3;
RIN_M_CTRL_CNT_intermed_1 <= RIN.M.CTRL.CNT;
RIN_M_CTRL_CNT_intermed_2 <= RIN_M_CTRL_CNT_intermed_1;
RIN_E_CTRL_CNT_intermed_1 <= RIN.E.CTRL.CNT;
RIN_E_CTRL_CNT_intermed_2 <= RIN_E_CTRL_CNT_intermed_1;
RIN_E_CTRL_CNT_intermed_3 <= RIN_E_CTRL_CNT_intermed_2;
V_M_CTRL_CNT_shadow_intermed_1 <= V_M_CTRL_CNT_shadow;
V_M_CTRL_CNT_shadow_intermed_2 <= V_M_CTRL_CNT_shadow_intermed_1;
V_E_CTRL_PV_shadow_intermed_1 <= V_E_CTRL_PV_shadow;
V_E_CTRL_PV_shadow_intermed_2 <= V_E_CTRL_PV_shadow_intermed_1;
V_E_CTRL_PV_shadow_intermed_3 <= V_E_CTRL_PV_shadow_intermed_2;
R_M_CTRL_PV_intermed_1 <= R.M.CTRL.PV;
R_E_CTRL_PV_intermed_1 <= R.E.CTRL.PV;
R_E_CTRL_PV_intermed_2 <= R_E_CTRL_PV_intermed_1;
R_A_CTRL_PV_intermed_1 <= R.A.CTRL.PV;
R_A_CTRL_PV_intermed_2 <= R_A_CTRL_PV_intermed_1;
R_A_CTRL_PV_intermed_3 <= R_A_CTRL_PV_intermed_2;
RIN_E_CTRL_PV_intermed_1 <= RIN.E.CTRL.PV;
RIN_E_CTRL_PV_intermed_2 <= RIN_E_CTRL_PV_intermed_1;
RIN_E_CTRL_PV_intermed_3 <= RIN_E_CTRL_PV_intermed_2;
RIN_X_CTRL_PV_intermed_1 <= RIN.X.CTRL.PV;
RIN_M_CTRL_PV_intermed_1 <= RIN.M.CTRL.PV;
RIN_M_CTRL_PV_intermed_2 <= RIN_M_CTRL_PV_intermed_1;
V_A_CTRL_PV_shadow_intermed_1 <= V_A_CTRL_PV_shadow;
V_A_CTRL_PV_shadow_intermed_2 <= V_A_CTRL_PV_shadow_intermed_1;
V_A_CTRL_PV_shadow_intermed_3 <= V_A_CTRL_PV_shadow_intermed_2;
V_A_CTRL_PV_shadow_intermed_4 <= V_A_CTRL_PV_shadow_intermed_3;
V_M_CTRL_PV_shadow_intermed_1 <= V_M_CTRL_PV_shadow;
V_M_CTRL_PV_shadow_intermed_2 <= V_M_CTRL_PV_shadow_intermed_1;
RIN_A_CTRL_PV_intermed_1 <= RIN.A.CTRL.PV;
RIN_A_CTRL_PV_intermed_2 <= RIN_A_CTRL_PV_intermed_1;
RIN_A_CTRL_PV_intermed_3 <= RIN_A_CTRL_PV_intermed_2;
RIN_A_CTRL_PV_intermed_4 <= RIN_A_CTRL_PV_intermed_3;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST( 19 );
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
DE_INST19_shadow_intermed_2 <= DE_INST19_shadow_intermed_1;
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST( 20 );
RIN_A_CTRL_INST20_intermed_2 <= RIN_A_CTRL_INST20_intermed_1;
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
V_A_CTRL_INST20_shadow_intermed_2 <= V_A_CTRL_INST20_shadow_intermed_1;
RIN_E_CTRL_INST20_intermed_1 <= RIN.E.CTRL.INST( 20 );
DE_INST20_shadow_intermed_1 <= DE_INST20_shadow;
DE_INST20_shadow_intermed_2 <= DE_INST20_shadow_intermed_1;
R_A_CTRL_INST20_intermed_1 <= R.A.CTRL.INST( 20 );
R_A_CTRL_INST24_intermed_1 <= R.A.CTRL.INST( 24 );
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST( 24 );
RIN_A_CTRL_INST24_intermed_2 <= RIN_A_CTRL_INST24_intermed_1;
RIN_E_CTRL_INST24_intermed_1 <= RIN.E.CTRL.INST( 24 );
V_A_CTRL_INST24_shadow_intermed_1 <= V_A_CTRL_INST24_shadow;
V_A_CTRL_INST24_shadow_intermed_2 <= V_A_CTRL_INST24_shadow_intermed_1;
DE_INST24_shadow_intermed_1 <= DE_INST24_shadow;
DE_INST24_shadow_intermed_2 <= DE_INST24_shadow_intermed_1;
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
V_X_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO4_shadow;
V_X_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO4_shadow_intermed_2;
IR_ADDR31DOWNTO4_intermed_1 <= IR.ADDR( 31 DOWNTO 4 );
VIR_ADDR31DOWNTO4_shadow_intermed_1 <= VIR_ADDR31DOWNTO4_shadow;
VIR_ADDR31DOWNTO4_shadow_intermed_2 <= VIR_ADDR31DOWNTO4_shadow_intermed_1;
RIN_F_PC31DOWNTO4_intermed_1 <= RIN.F.PC( 31 DOWNTO 4 );
RIN_A_CTRL_PC31DOWNTO4_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 4 );
RIN_A_CTRL_PC31DOWNTO4_intermed_2 <= RIN_A_CTRL_PC31DOWNTO4_intermed_1;
RIN_A_CTRL_PC31DOWNTO4_intermed_3 <= RIN_A_CTRL_PC31DOWNTO4_intermed_2;
RIN_A_CTRL_PC31DOWNTO4_intermed_4 <= RIN_A_CTRL_PC31DOWNTO4_intermed_3;
RIN_A_CTRL_PC31DOWNTO4_intermed_5 <= RIN_A_CTRL_PC31DOWNTO4_intermed_4;
RIN_A_CTRL_PC31DOWNTO4_intermed_6 <= RIN_A_CTRL_PC31DOWNTO4_intermed_5;
R_A_CTRL_PC31DOWNTO4_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 4 );
R_A_CTRL_PC31DOWNTO4_intermed_2 <= R_A_CTRL_PC31DOWNTO4_intermed_1;
R_A_CTRL_PC31DOWNTO4_intermed_3 <= R_A_CTRL_PC31DOWNTO4_intermed_2;
R_A_CTRL_PC31DOWNTO4_intermed_4 <= R_A_CTRL_PC31DOWNTO4_intermed_3;
R_A_CTRL_PC31DOWNTO4_intermed_5 <= R_A_CTRL_PC31DOWNTO4_intermed_4;
R_D_PC31DOWNTO4_intermed_1 <= R.D.PC( 31 DOWNTO 4 );
R_D_PC31DOWNTO4_intermed_2 <= R_D_PC31DOWNTO4_intermed_1;
R_D_PC31DOWNTO4_intermed_3 <= R_D_PC31DOWNTO4_intermed_2;
R_D_PC31DOWNTO4_intermed_4 <= R_D_PC31DOWNTO4_intermed_3;
R_D_PC31DOWNTO4_intermed_5 <= R_D_PC31DOWNTO4_intermed_4;
R_D_PC31DOWNTO4_intermed_6 <= R_D_PC31DOWNTO4_intermed_5;
RIN_X_CTRL_PC31DOWNTO4_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 4 );
RIN_X_CTRL_PC31DOWNTO4_intermed_2 <= RIN_X_CTRL_PC31DOWNTO4_intermed_1;
RIN_X_CTRL_PC31DOWNTO4_intermed_3 <= RIN_X_CTRL_PC31DOWNTO4_intermed_2;
EX_ADD_RES32DOWNTO332DOWNTO5_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO5_shadow;
V_D_PC31DOWNTO4_shadow_intermed_1 <= V_D_PC31DOWNTO4_shadow;
V_D_PC31DOWNTO4_shadow_intermed_2 <= V_D_PC31DOWNTO4_shadow_intermed_1;
V_D_PC31DOWNTO4_shadow_intermed_3 <= V_D_PC31DOWNTO4_shadow_intermed_2;
V_D_PC31DOWNTO4_shadow_intermed_4 <= V_D_PC31DOWNTO4_shadow_intermed_3;
V_D_PC31DOWNTO4_shadow_intermed_5 <= V_D_PC31DOWNTO4_shadow_intermed_4;
V_D_PC31DOWNTO4_shadow_intermed_6 <= V_D_PC31DOWNTO4_shadow_intermed_5;
V_D_PC31DOWNTO4_shadow_intermed_7 <= V_D_PC31DOWNTO4_shadow_intermed_6;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO4_shadow;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_4;
RIN_M_CTRL_PC31DOWNTO4_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 4 );
RIN_M_CTRL_PC31DOWNTO4_intermed_2 <= RIN_M_CTRL_PC31DOWNTO4_intermed_1;
RIN_M_CTRL_PC31DOWNTO4_intermed_3 <= RIN_M_CTRL_PC31DOWNTO4_intermed_2;
RIN_M_CTRL_PC31DOWNTO4_intermed_4 <= RIN_M_CTRL_PC31DOWNTO4_intermed_3;
R_X_CTRL_PC31DOWNTO4_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 4 );
R_X_CTRL_PC31DOWNTO4_intermed_2 <= R_X_CTRL_PC31DOWNTO4_intermed_1;
IRIN_ADDR31DOWNTO4_intermed_1 <= IRIN.ADDR( 31 DOWNTO 4 );
IRIN_ADDR31DOWNTO4_intermed_2 <= IRIN_ADDR31DOWNTO4_intermed_1;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO4_shadow;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_3;
R_M_CTRL_PC31DOWNTO4_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 4 );
R_M_CTRL_PC31DOWNTO4_intermed_2 <= R_M_CTRL_PC31DOWNTO4_intermed_1;
R_M_CTRL_PC31DOWNTO4_intermed_3 <= R_M_CTRL_PC31DOWNTO4_intermed_2;
XC_TRAP_ADDRESS31DOWNTO4_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO4_shadow;
RIN_D_PC31DOWNTO4_intermed_1 <= RIN.D.PC( 31 DOWNTO 4 );
RIN_D_PC31DOWNTO4_intermed_2 <= RIN_D_PC31DOWNTO4_intermed_1;
RIN_D_PC31DOWNTO4_intermed_3 <= RIN_D_PC31DOWNTO4_intermed_2;
RIN_D_PC31DOWNTO4_intermed_4 <= RIN_D_PC31DOWNTO4_intermed_3;
RIN_D_PC31DOWNTO4_intermed_5 <= RIN_D_PC31DOWNTO4_intermed_4;
RIN_D_PC31DOWNTO4_intermed_6 <= RIN_D_PC31DOWNTO4_intermed_5;
RIN_D_PC31DOWNTO4_intermed_7 <= RIN_D_PC31DOWNTO4_intermed_6;
RIN_E_CTRL_PC31DOWNTO4_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 4 );
RIN_E_CTRL_PC31DOWNTO4_intermed_2 <= RIN_E_CTRL_PC31DOWNTO4_intermed_1;
RIN_E_CTRL_PC31DOWNTO4_intermed_3 <= RIN_E_CTRL_PC31DOWNTO4_intermed_2;
RIN_E_CTRL_PC31DOWNTO4_intermed_4 <= RIN_E_CTRL_PC31DOWNTO4_intermed_3;
RIN_E_CTRL_PC31DOWNTO4_intermed_5 <= RIN_E_CTRL_PC31DOWNTO4_intermed_4;
EX_JUMP_ADDRESS31DOWNTO4_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO4_shadow;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO4_shadow;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_5;
R_E_CTRL_PC31DOWNTO4_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 4 );
R_E_CTRL_PC31DOWNTO4_intermed_2 <= R_E_CTRL_PC31DOWNTO4_intermed_1;
R_E_CTRL_PC31DOWNTO4_intermed_3 <= R_E_CTRL_PC31DOWNTO4_intermed_2;
R_E_CTRL_PC31DOWNTO4_intermed_4 <= R_E_CTRL_PC31DOWNTO4_intermed_3;
V_X_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO4_shadow;
V_X_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO4_shadow_intermed_1;
RIN_A_CTRL_PC31DOWNTO4_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 4 );
RIN_A_CTRL_PC31DOWNTO4_intermed_2 <= RIN_A_CTRL_PC31DOWNTO4_intermed_1;
RIN_A_CTRL_PC31DOWNTO4_intermed_3 <= RIN_A_CTRL_PC31DOWNTO4_intermed_2;
RIN_A_CTRL_PC31DOWNTO4_intermed_4 <= RIN_A_CTRL_PC31DOWNTO4_intermed_3;
RIN_A_CTRL_PC31DOWNTO4_intermed_5 <= RIN_A_CTRL_PC31DOWNTO4_intermed_4;
R_A_CTRL_PC31DOWNTO4_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 4 );
R_A_CTRL_PC31DOWNTO4_intermed_2 <= R_A_CTRL_PC31DOWNTO4_intermed_1;
R_A_CTRL_PC31DOWNTO4_intermed_3 <= R_A_CTRL_PC31DOWNTO4_intermed_2;
R_A_CTRL_PC31DOWNTO4_intermed_4 <= R_A_CTRL_PC31DOWNTO4_intermed_3;
R_D_PC31DOWNTO4_intermed_1 <= R.D.PC( 31 DOWNTO 4 );
R_D_PC31DOWNTO4_intermed_2 <= R_D_PC31DOWNTO4_intermed_1;
R_D_PC31DOWNTO4_intermed_3 <= R_D_PC31DOWNTO4_intermed_2;
R_D_PC31DOWNTO4_intermed_4 <= R_D_PC31DOWNTO4_intermed_3;
R_D_PC31DOWNTO4_intermed_5 <= R_D_PC31DOWNTO4_intermed_4;
RIN_X_CTRL_PC31DOWNTO4_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 4 );
RIN_X_CTRL_PC31DOWNTO4_intermed_2 <= RIN_X_CTRL_PC31DOWNTO4_intermed_1;
V_D_PC31DOWNTO4_shadow_intermed_1 <= V_D_PC31DOWNTO4_shadow;
V_D_PC31DOWNTO4_shadow_intermed_2 <= V_D_PC31DOWNTO4_shadow_intermed_1;
V_D_PC31DOWNTO4_shadow_intermed_3 <= V_D_PC31DOWNTO4_shadow_intermed_2;
V_D_PC31DOWNTO4_shadow_intermed_4 <= V_D_PC31DOWNTO4_shadow_intermed_3;
V_D_PC31DOWNTO4_shadow_intermed_5 <= V_D_PC31DOWNTO4_shadow_intermed_4;
V_D_PC31DOWNTO4_shadow_intermed_6 <= V_D_PC31DOWNTO4_shadow_intermed_5;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO4_shadow;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_3;
RIN_M_CTRL_PC31DOWNTO4_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 4 );
RIN_M_CTRL_PC31DOWNTO4_intermed_2 <= RIN_M_CTRL_PC31DOWNTO4_intermed_1;
RIN_M_CTRL_PC31DOWNTO4_intermed_3 <= RIN_M_CTRL_PC31DOWNTO4_intermed_2;
R_X_CTRL_PC31DOWNTO4_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 4 );
IRIN_ADDR31DOWNTO4_intermed_1 <= IRIN.ADDR( 31 DOWNTO 4 );
V_M_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO4_shadow;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_2;
R_M_CTRL_PC31DOWNTO4_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 4 );
R_M_CTRL_PC31DOWNTO4_intermed_2 <= R_M_CTRL_PC31DOWNTO4_intermed_1;
RIN_D_PC31DOWNTO4_intermed_1 <= RIN.D.PC( 31 DOWNTO 4 );
RIN_D_PC31DOWNTO4_intermed_2 <= RIN_D_PC31DOWNTO4_intermed_1;
RIN_D_PC31DOWNTO4_intermed_3 <= RIN_D_PC31DOWNTO4_intermed_2;
RIN_D_PC31DOWNTO4_intermed_4 <= RIN_D_PC31DOWNTO4_intermed_3;
RIN_D_PC31DOWNTO4_intermed_5 <= RIN_D_PC31DOWNTO4_intermed_4;
RIN_D_PC31DOWNTO4_intermed_6 <= RIN_D_PC31DOWNTO4_intermed_5;
RIN_E_CTRL_PC31DOWNTO4_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 4 );
RIN_E_CTRL_PC31DOWNTO4_intermed_2 <= RIN_E_CTRL_PC31DOWNTO4_intermed_1;
RIN_E_CTRL_PC31DOWNTO4_intermed_3 <= RIN_E_CTRL_PC31DOWNTO4_intermed_2;
RIN_E_CTRL_PC31DOWNTO4_intermed_4 <= RIN_E_CTRL_PC31DOWNTO4_intermed_3;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO4_shadow;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_4;
R_E_CTRL_PC31DOWNTO4_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 4 );
R_E_CTRL_PC31DOWNTO4_intermed_2 <= R_E_CTRL_PC31DOWNTO4_intermed_1;
R_E_CTRL_PC31DOWNTO4_intermed_3 <= R_E_CTRL_PC31DOWNTO4_intermed_2;
R_D_PC3DOWNTO2_intermed_1 <= R.D.PC( 3 DOWNTO 2 );
R_D_PC3DOWNTO2_intermed_2 <= R_D_PC3DOWNTO2_intermed_1;
R_D_PC3DOWNTO2_intermed_3 <= R_D_PC3DOWNTO2_intermed_2;
R_D_PC3DOWNTO2_intermed_4 <= R_D_PC3DOWNTO2_intermed_3;
R_D_PC3DOWNTO2_intermed_5 <= R_D_PC3DOWNTO2_intermed_4;
R_D_PC3DOWNTO2_intermed_6 <= R_D_PC3DOWNTO2_intermed_5;
V_D_PC3DOWNTO2_shadow_intermed_1 <= V_D_PC3DOWNTO2_shadow;
V_D_PC3DOWNTO2_shadow_intermed_2 <= V_D_PC3DOWNTO2_shadow_intermed_1;
V_D_PC3DOWNTO2_shadow_intermed_3 <= V_D_PC3DOWNTO2_shadow_intermed_2;
V_D_PC3DOWNTO2_shadow_intermed_4 <= V_D_PC3DOWNTO2_shadow_intermed_3;
V_D_PC3DOWNTO2_shadow_intermed_5 <= V_D_PC3DOWNTO2_shadow_intermed_4;
V_D_PC3DOWNTO2_shadow_intermed_6 <= V_D_PC3DOWNTO2_shadow_intermed_5;
V_D_PC3DOWNTO2_shadow_intermed_7 <= V_D_PC3DOWNTO2_shadow_intermed_6;
VIR_ADDR3DOWNTO2_shadow_intermed_1 <= VIR_ADDR3DOWNTO2_shadow;
VIR_ADDR3DOWNTO2_shadow_intermed_2 <= VIR_ADDR3DOWNTO2_shadow_intermed_1;
RIN_D_PC3DOWNTO2_intermed_1 <= RIN.D.PC( 3 DOWNTO 2 );
RIN_D_PC3DOWNTO2_intermed_2 <= RIN_D_PC3DOWNTO2_intermed_1;
RIN_D_PC3DOWNTO2_intermed_3 <= RIN_D_PC3DOWNTO2_intermed_2;
RIN_D_PC3DOWNTO2_intermed_4 <= RIN_D_PC3DOWNTO2_intermed_3;
RIN_D_PC3DOWNTO2_intermed_5 <= RIN_D_PC3DOWNTO2_intermed_4;
RIN_D_PC3DOWNTO2_intermed_6 <= RIN_D_PC3DOWNTO2_intermed_5;
RIN_D_PC3DOWNTO2_intermed_7 <= RIN_D_PC3DOWNTO2_intermed_6;
R_M_CTRL_PC3DOWNTO2_intermed_1 <= R.M.CTRL.PC( 3 DOWNTO 2 );
R_M_CTRL_PC3DOWNTO2_intermed_2 <= R_M_CTRL_PC3DOWNTO2_intermed_1;
R_M_CTRL_PC3DOWNTO2_intermed_3 <= R_M_CTRL_PC3DOWNTO2_intermed_2;
R_E_CTRL_PC3DOWNTO2_intermed_1 <= R.E.CTRL.PC( 3 DOWNTO 2 );
R_E_CTRL_PC3DOWNTO2_intermed_2 <= R_E_CTRL_PC3DOWNTO2_intermed_1;
R_E_CTRL_PC3DOWNTO2_intermed_3 <= R_E_CTRL_PC3DOWNTO2_intermed_2;
R_E_CTRL_PC3DOWNTO2_intermed_4 <= R_E_CTRL_PC3DOWNTO2_intermed_3;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC3DOWNTO2_shadow;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_3;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_4;
RIN_X_CTRL_PC3DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 3 DOWNTO 2 );
RIN_X_CTRL_PC3DOWNTO2_intermed_2 <= RIN_X_CTRL_PC3DOWNTO2_intermed_1;
RIN_X_CTRL_PC3DOWNTO2_intermed_3 <= RIN_X_CTRL_PC3DOWNTO2_intermed_2;
R_A_CTRL_PC3DOWNTO2_intermed_1 <= R.A.CTRL.PC( 3 DOWNTO 2 );
R_A_CTRL_PC3DOWNTO2_intermed_2 <= R_A_CTRL_PC3DOWNTO2_intermed_1;
R_A_CTRL_PC3DOWNTO2_intermed_3 <= R_A_CTRL_PC3DOWNTO2_intermed_2;
R_A_CTRL_PC3DOWNTO2_intermed_4 <= R_A_CTRL_PC3DOWNTO2_intermed_3;
R_A_CTRL_PC3DOWNTO2_intermed_5 <= R_A_CTRL_PC3DOWNTO2_intermed_4;
V_X_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC3DOWNTO2_shadow;
V_X_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC3DOWNTO2_shadow_intermed_2;
RIN_M_CTRL_PC3DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 3 DOWNTO 2 );
RIN_M_CTRL_PC3DOWNTO2_intermed_2 <= RIN_M_CTRL_PC3DOWNTO2_intermed_1;
RIN_M_CTRL_PC3DOWNTO2_intermed_3 <= RIN_M_CTRL_PC3DOWNTO2_intermed_2;
RIN_M_CTRL_PC3DOWNTO2_intermed_4 <= RIN_M_CTRL_PC3DOWNTO2_intermed_3;
IRIN_ADDR3DOWNTO2_intermed_1 <= IRIN.ADDR( 3 DOWNTO 2 );
IRIN_ADDR3DOWNTO2_intermed_2 <= IRIN_ADDR3DOWNTO2_intermed_1;
EX_JUMP_ADDRESS3DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS3DOWNTO2_shadow;
EX_ADD_RES32DOWNTO34DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO34DOWNTO3_shadow;
RIN_A_CTRL_PC3DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 3 DOWNTO 2 );
RIN_A_CTRL_PC3DOWNTO2_intermed_2 <= RIN_A_CTRL_PC3DOWNTO2_intermed_1;
RIN_A_CTRL_PC3DOWNTO2_intermed_3 <= RIN_A_CTRL_PC3DOWNTO2_intermed_2;
RIN_A_CTRL_PC3DOWNTO2_intermed_4 <= RIN_A_CTRL_PC3DOWNTO2_intermed_3;
RIN_A_CTRL_PC3DOWNTO2_intermed_5 <= RIN_A_CTRL_PC3DOWNTO2_intermed_4;
RIN_A_CTRL_PC3DOWNTO2_intermed_6 <= RIN_A_CTRL_PC3DOWNTO2_intermed_5;
XC_TRAP_ADDRESS3DOWNTO2_shadow_intermed_1 <= XC_TRAP_ADDRESS3DOWNTO2_shadow;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC3DOWNTO2_shadow;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_4;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_5;
IR_ADDR3DOWNTO2_intermed_1 <= IR.ADDR( 3 DOWNTO 2 );
V_M_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC3DOWNTO2_shadow;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_2;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_3;
R_X_CTRL_PC3DOWNTO2_intermed_1 <= R.X.CTRL.PC( 3 DOWNTO 2 );
R_X_CTRL_PC3DOWNTO2_intermed_2 <= R_X_CTRL_PC3DOWNTO2_intermed_1;
RIN_E_CTRL_PC3DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 3 DOWNTO 2 );
RIN_E_CTRL_PC3DOWNTO2_intermed_2 <= RIN_E_CTRL_PC3DOWNTO2_intermed_1;
RIN_E_CTRL_PC3DOWNTO2_intermed_3 <= RIN_E_CTRL_PC3DOWNTO2_intermed_2;
RIN_E_CTRL_PC3DOWNTO2_intermed_4 <= RIN_E_CTRL_PC3DOWNTO2_intermed_3;
RIN_E_CTRL_PC3DOWNTO2_intermed_5 <= RIN_E_CTRL_PC3DOWNTO2_intermed_4;
RIN_F_PC3DOWNTO2_intermed_1 <= RIN.F.PC( 3 DOWNTO 2 );
R_D_PC3DOWNTO2_intermed_1 <= R.D.PC( 3 DOWNTO 2 );
R_D_PC3DOWNTO2_intermed_2 <= R_D_PC3DOWNTO2_intermed_1;
R_D_PC3DOWNTO2_intermed_3 <= R_D_PC3DOWNTO2_intermed_2;
R_D_PC3DOWNTO2_intermed_4 <= R_D_PC3DOWNTO2_intermed_3;
R_D_PC3DOWNTO2_intermed_5 <= R_D_PC3DOWNTO2_intermed_4;
V_D_PC3DOWNTO2_shadow_intermed_1 <= V_D_PC3DOWNTO2_shadow;
V_D_PC3DOWNTO2_shadow_intermed_2 <= V_D_PC3DOWNTO2_shadow_intermed_1;
V_D_PC3DOWNTO2_shadow_intermed_3 <= V_D_PC3DOWNTO2_shadow_intermed_2;
V_D_PC3DOWNTO2_shadow_intermed_4 <= V_D_PC3DOWNTO2_shadow_intermed_3;
V_D_PC3DOWNTO2_shadow_intermed_5 <= V_D_PC3DOWNTO2_shadow_intermed_4;
V_D_PC3DOWNTO2_shadow_intermed_6 <= V_D_PC3DOWNTO2_shadow_intermed_5;
RIN_D_PC3DOWNTO2_intermed_1 <= RIN.D.PC( 3 DOWNTO 2 );
RIN_D_PC3DOWNTO2_intermed_2 <= RIN_D_PC3DOWNTO2_intermed_1;
RIN_D_PC3DOWNTO2_intermed_3 <= RIN_D_PC3DOWNTO2_intermed_2;
RIN_D_PC3DOWNTO2_intermed_4 <= RIN_D_PC3DOWNTO2_intermed_3;
RIN_D_PC3DOWNTO2_intermed_5 <= RIN_D_PC3DOWNTO2_intermed_4;
RIN_D_PC3DOWNTO2_intermed_6 <= RIN_D_PC3DOWNTO2_intermed_5;
R_M_CTRL_PC3DOWNTO2_intermed_1 <= R.M.CTRL.PC( 3 DOWNTO 2 );
R_M_CTRL_PC3DOWNTO2_intermed_2 <= R_M_CTRL_PC3DOWNTO2_intermed_1;
R_E_CTRL_PC3DOWNTO2_intermed_1 <= R.E.CTRL.PC( 3 DOWNTO 2 );
R_E_CTRL_PC3DOWNTO2_intermed_2 <= R_E_CTRL_PC3DOWNTO2_intermed_1;
R_E_CTRL_PC3DOWNTO2_intermed_3 <= R_E_CTRL_PC3DOWNTO2_intermed_2;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC3DOWNTO2_shadow;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_3;
RIN_X_CTRL_PC3DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 3 DOWNTO 2 );
RIN_X_CTRL_PC3DOWNTO2_intermed_2 <= RIN_X_CTRL_PC3DOWNTO2_intermed_1;
R_A_CTRL_PC3DOWNTO2_intermed_1 <= R.A.CTRL.PC( 3 DOWNTO 2 );
R_A_CTRL_PC3DOWNTO2_intermed_2 <= R_A_CTRL_PC3DOWNTO2_intermed_1;
R_A_CTRL_PC3DOWNTO2_intermed_3 <= R_A_CTRL_PC3DOWNTO2_intermed_2;
R_A_CTRL_PC3DOWNTO2_intermed_4 <= R_A_CTRL_PC3DOWNTO2_intermed_3;
V_X_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC3DOWNTO2_shadow;
V_X_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC3DOWNTO2_shadow_intermed_1;
RIN_M_CTRL_PC3DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 3 DOWNTO 2 );
RIN_M_CTRL_PC3DOWNTO2_intermed_2 <= RIN_M_CTRL_PC3DOWNTO2_intermed_1;
RIN_M_CTRL_PC3DOWNTO2_intermed_3 <= RIN_M_CTRL_PC3DOWNTO2_intermed_2;
IRIN_ADDR3DOWNTO2_intermed_1 <= IRIN.ADDR( 3 DOWNTO 2 );
RIN_A_CTRL_PC3DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 3 DOWNTO 2 );
RIN_A_CTRL_PC3DOWNTO2_intermed_2 <= RIN_A_CTRL_PC3DOWNTO2_intermed_1;
RIN_A_CTRL_PC3DOWNTO2_intermed_3 <= RIN_A_CTRL_PC3DOWNTO2_intermed_2;
RIN_A_CTRL_PC3DOWNTO2_intermed_4 <= RIN_A_CTRL_PC3DOWNTO2_intermed_3;
RIN_A_CTRL_PC3DOWNTO2_intermed_5 <= RIN_A_CTRL_PC3DOWNTO2_intermed_4;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC3DOWNTO2_shadow;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_4;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC3DOWNTO2_shadow;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_2;
R_X_CTRL_PC3DOWNTO2_intermed_1 <= R.X.CTRL.PC( 3 DOWNTO 2 );
RIN_E_CTRL_PC3DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 3 DOWNTO 2 );
RIN_E_CTRL_PC3DOWNTO2_intermed_2 <= RIN_E_CTRL_PC3DOWNTO2_intermed_1;
RIN_E_CTRL_PC3DOWNTO2_intermed_3 <= RIN_E_CTRL_PC3DOWNTO2_intermed_2;
RIN_E_CTRL_PC3DOWNTO2_intermed_4 <= RIN_E_CTRL_PC3DOWNTO2_intermed_3;
RIN_E_CTRL_RD6DOWNTO0_intermed_1 <= RIN.E.CTRL.RD( 6 DOWNTO 0 );
RIN_E_CTRL_RD6DOWNTO0_intermed_2 <= RIN_E_CTRL_RD6DOWNTO0_intermed_1;
RIN_E_CTRL_RD6DOWNTO0_intermed_3 <= RIN_E_CTRL_RD6DOWNTO0_intermed_2;
RIN_M_CTRL_RD6DOWNTO0_intermed_1 <= RIN.M.CTRL.RD( 6 DOWNTO 0 );
RIN_M_CTRL_RD6DOWNTO0_intermed_2 <= RIN_M_CTRL_RD6DOWNTO0_intermed_1;
RIN_X_CTRL_RD6DOWNTO0_intermed_1 <= RIN.X.CTRL.RD( 6 DOWNTO 0 );
V_M_CTRL_RD6DOWNTO0_shadow_intermed_1 <= V_M_CTRL_RD6DOWNTO0_shadow;
V_M_CTRL_RD6DOWNTO0_shadow_intermed_2 <= V_M_CTRL_RD6DOWNTO0_shadow_intermed_1;
R_E_CTRL_RD6DOWNTO0_intermed_1 <= R.E.CTRL.RD( 6 DOWNTO 0 );
R_E_CTRL_RD6DOWNTO0_intermed_2 <= R_E_CTRL_RD6DOWNTO0_intermed_1;
V_E_CTRL_RD6DOWNTO0_shadow_intermed_1 <= V_E_CTRL_RD6DOWNTO0_shadow;
V_E_CTRL_RD6DOWNTO0_shadow_intermed_2 <= V_E_CTRL_RD6DOWNTO0_shadow_intermed_1;
V_E_CTRL_RD6DOWNTO0_shadow_intermed_3 <= V_E_CTRL_RD6DOWNTO0_shadow_intermed_2;
V_A_CTRL_RD6DOWNTO0_shadow_intermed_1 <= V_A_CTRL_RD6DOWNTO0_shadow;
V_A_CTRL_RD6DOWNTO0_shadow_intermed_2 <= V_A_CTRL_RD6DOWNTO0_shadow_intermed_1;
V_A_CTRL_RD6DOWNTO0_shadow_intermed_3 <= V_A_CTRL_RD6DOWNTO0_shadow_intermed_2;
V_A_CTRL_RD6DOWNTO0_shadow_intermed_4 <= V_A_CTRL_RD6DOWNTO0_shadow_intermed_3;
R_A_CTRL_RD6DOWNTO0_intermed_1 <= R.A.CTRL.RD( 6 DOWNTO 0 );
R_A_CTRL_RD6DOWNTO0_intermed_2 <= R_A_CTRL_RD6DOWNTO0_intermed_1;
R_A_CTRL_RD6DOWNTO0_intermed_3 <= R_A_CTRL_RD6DOWNTO0_intermed_2;
RIN_A_CTRL_RD6DOWNTO0_intermed_1 <= RIN.A.CTRL.RD( 6 DOWNTO 0 );
RIN_A_CTRL_RD6DOWNTO0_intermed_2 <= RIN_A_CTRL_RD6DOWNTO0_intermed_1;
RIN_A_CTRL_RD6DOWNTO0_intermed_3 <= RIN_A_CTRL_RD6DOWNTO0_intermed_2;
RIN_A_CTRL_RD6DOWNTO0_intermed_4 <= RIN_A_CTRL_RD6DOWNTO0_intermed_3;
R_M_CTRL_RD6DOWNTO0_intermed_1 <= R.M.CTRL.RD( 6 DOWNTO 0 );
V_E_CTRL_TT_shadow_intermed_1 <= V_E_CTRL_TT_shadow;
V_E_CTRL_TT_shadow_intermed_2 <= V_E_CTRL_TT_shadow_intermed_1;
RIN_A_CTRL_TT_intermed_1 <= RIN.A.CTRL.TT;
RIN_A_CTRL_TT_intermed_2 <= RIN_A_CTRL_TT_intermed_1;
RIN_A_CTRL_TT_intermed_3 <= RIN_A_CTRL_TT_intermed_2;
R_A_CTRL_TT_intermed_1 <= R.A.CTRL.TT;
R_A_CTRL_TT_intermed_2 <= R_A_CTRL_TT_intermed_1;
R_E_CTRL_TT_intermed_1 <= R.E.CTRL.TT;
RIN_M_CTRL_TT_intermed_1 <= RIN.M.CTRL.TT;
RIN_E_CTRL_TT_intermed_1 <= RIN.E.CTRL.TT;
RIN_E_CTRL_TT_intermed_2 <= RIN_E_CTRL_TT_intermed_1;
V_A_CTRL_TT_shadow_intermed_1 <= V_A_CTRL_TT_shadow;
V_A_CTRL_TT_shadow_intermed_2 <= V_A_CTRL_TT_shadow_intermed_1;
V_A_CTRL_TT_shadow_intermed_3 <= V_A_CTRL_TT_shadow_intermed_2;
R_A_CTRL_LD_intermed_1 <= R.A.CTRL.LD;
RIN_A_CTRL_LD_intermed_1 <= RIN.A.CTRL.LD;
RIN_A_CTRL_LD_intermed_2 <= RIN_A_CTRL_LD_intermed_1;
RIN_E_CTRL_LD_intermed_1 <= RIN.E.CTRL.LD;
V_A_CTRL_LD_shadow_intermed_1 <= V_A_CTRL_LD_shadow;
V_A_CTRL_LD_shadow_intermed_2 <= V_A_CTRL_LD_shadow_intermed_1;
R_M_CTRL_PC31DOWNTO12_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 12 );
R_M_CTRL_PC31DOWNTO12_intermed_2 <= R_M_CTRL_PC31DOWNTO12_intermed_1;
R_M_CTRL_PC31DOWNTO12_intermed_3 <= R_M_CTRL_PC31DOWNTO12_intermed_2;
V_D_PC31DOWNTO12_shadow_intermed_1 <= V_D_PC31DOWNTO12_shadow;
V_D_PC31DOWNTO12_shadow_intermed_2 <= V_D_PC31DOWNTO12_shadow_intermed_1;
V_D_PC31DOWNTO12_shadow_intermed_3 <= V_D_PC31DOWNTO12_shadow_intermed_2;
V_D_PC31DOWNTO12_shadow_intermed_4 <= V_D_PC31DOWNTO12_shadow_intermed_3;
V_D_PC31DOWNTO12_shadow_intermed_5 <= V_D_PC31DOWNTO12_shadow_intermed_4;
V_D_PC31DOWNTO12_shadow_intermed_6 <= V_D_PC31DOWNTO12_shadow_intermed_5;
V_D_PC31DOWNTO12_shadow_intermed_7 <= V_D_PC31DOWNTO12_shadow_intermed_6;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO12_shadow;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_5;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO12_shadow;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_4;
EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_1 <= EX_ADD_RES32DOWNTO330DOWNTO11_shadow;
RIN_F_PC31DOWNTO12_intermed_1 <= RIN.F.PC( 31 DOWNTO 12 );
R_A_CTRL_PC31DOWNTO12_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 12 );
R_A_CTRL_PC31DOWNTO12_intermed_2 <= R_A_CTRL_PC31DOWNTO12_intermed_1;
R_A_CTRL_PC31DOWNTO12_intermed_3 <= R_A_CTRL_PC31DOWNTO12_intermed_2;
R_A_CTRL_PC31DOWNTO12_intermed_4 <= R_A_CTRL_PC31DOWNTO12_intermed_3;
R_A_CTRL_PC31DOWNTO12_intermed_5 <= R_A_CTRL_PC31DOWNTO12_intermed_4;
R_E_CTRL_PC31DOWNTO12_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 12 );
R_E_CTRL_PC31DOWNTO12_intermed_2 <= R_E_CTRL_PC31DOWNTO12_intermed_1;
R_E_CTRL_PC31DOWNTO12_intermed_3 <= R_E_CTRL_PC31DOWNTO12_intermed_2;
R_E_CTRL_PC31DOWNTO12_intermed_4 <= R_E_CTRL_PC31DOWNTO12_intermed_3;
EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO12_shadow;
RIN_A_CTRL_PC31DOWNTO12_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_2 <= RIN_A_CTRL_PC31DOWNTO12_intermed_1;
RIN_A_CTRL_PC31DOWNTO12_intermed_3 <= RIN_A_CTRL_PC31DOWNTO12_intermed_2;
RIN_A_CTRL_PC31DOWNTO12_intermed_4 <= RIN_A_CTRL_PC31DOWNTO12_intermed_3;
RIN_A_CTRL_PC31DOWNTO12_intermed_5 <= RIN_A_CTRL_PC31DOWNTO12_intermed_4;
RIN_A_CTRL_PC31DOWNTO12_intermed_6 <= RIN_A_CTRL_PC31DOWNTO12_intermed_5;
RIN_E_CTRL_PC31DOWNTO12_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 12 );
RIN_E_CTRL_PC31DOWNTO12_intermed_2 <= RIN_E_CTRL_PC31DOWNTO12_intermed_1;
RIN_E_CTRL_PC31DOWNTO12_intermed_3 <= RIN_E_CTRL_PC31DOWNTO12_intermed_2;
RIN_E_CTRL_PC31DOWNTO12_intermed_4 <= RIN_E_CTRL_PC31DOWNTO12_intermed_3;
RIN_E_CTRL_PC31DOWNTO12_intermed_5 <= RIN_E_CTRL_PC31DOWNTO12_intermed_4;
IRIN_ADDR31DOWNTO12_intermed_1 <= IRIN.ADDR( 31 DOWNTO 12 );
IRIN_ADDR31DOWNTO12_intermed_2 <= IRIN_ADDR31DOWNTO12_intermed_1;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO12_shadow;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_2;
EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO13_shadow;
XC_TRAP_ADDRESS31DOWNTO12_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO12_shadow;
RIN_M_CTRL_PC31DOWNTO12_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 12 );
RIN_M_CTRL_PC31DOWNTO12_intermed_2 <= RIN_M_CTRL_PC31DOWNTO12_intermed_1;
RIN_M_CTRL_PC31DOWNTO12_intermed_3 <= RIN_M_CTRL_PC31DOWNTO12_intermed_2;
RIN_M_CTRL_PC31DOWNTO12_intermed_4 <= RIN_M_CTRL_PC31DOWNTO12_intermed_3;
IR_ADDR31DOWNTO12_intermed_1 <= IR.ADDR( 31 DOWNTO 12 );
R_X_CTRL_PC31DOWNTO12_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 12 );
R_X_CTRL_PC31DOWNTO12_intermed_2 <= R_X_CTRL_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_1 <= R.D.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_2 <= R_D_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_3 <= R_D_PC31DOWNTO12_intermed_2;
R_D_PC31DOWNTO12_intermed_4 <= R_D_PC31DOWNTO12_intermed_3;
R_D_PC31DOWNTO12_intermed_5 <= R_D_PC31DOWNTO12_intermed_4;
R_D_PC31DOWNTO12_intermed_6 <= R_D_PC31DOWNTO12_intermed_5;
RIN_X_CTRL_PC31DOWNTO12_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 12 );
RIN_X_CTRL_PC31DOWNTO12_intermed_2 <= RIN_X_CTRL_PC31DOWNTO12_intermed_1;
RIN_X_CTRL_PC31DOWNTO12_intermed_3 <= RIN_X_CTRL_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_1 <= RIN.D.PC( 31 DOWNTO 12 );
RIN_D_PC31DOWNTO12_intermed_2 <= RIN_D_PC31DOWNTO12_intermed_1;
RIN_D_PC31DOWNTO12_intermed_3 <= RIN_D_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_4 <= RIN_D_PC31DOWNTO12_intermed_3;
RIN_D_PC31DOWNTO12_intermed_5 <= RIN_D_PC31DOWNTO12_intermed_4;
RIN_D_PC31DOWNTO12_intermed_6 <= RIN_D_PC31DOWNTO12_intermed_5;
RIN_D_PC31DOWNTO12_intermed_7 <= RIN_D_PC31DOWNTO12_intermed_6;
VIR_ADDR31DOWNTO12_shadow_intermed_1 <= VIR_ADDR31DOWNTO12_shadow;
VIR_ADDR31DOWNTO12_shadow_intermed_2 <= VIR_ADDR31DOWNTO12_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO12_shadow;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_X_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_X_CTRL_TT3DOWNTO0_shadow;
R_M_CTRL_TT3DOWNTO0_intermed_1 <= R.M.CTRL.TT( 3 DOWNTO 0 );
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1;
R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
R_A_CTRL_TT3DOWNTO0_intermed_1 <= R.A.CTRL.TT( 3 DOWNTO 0 );
R_A_CTRL_TT3DOWNTO0_intermed_2 <= R_A_CTRL_TT3DOWNTO0_intermed_1;
R_A_CTRL_TT3DOWNTO0_intermed_3 <= R_A_CTRL_TT3DOWNTO0_intermed_2;
RIN_A_CTRL_TT3DOWNTO0_intermed_1 <= RIN.A.CTRL.TT( 3 DOWNTO 0 );
RIN_A_CTRL_TT3DOWNTO0_intermed_2 <= RIN_A_CTRL_TT3DOWNTO0_intermed_1;
RIN_A_CTRL_TT3DOWNTO0_intermed_3 <= RIN_A_CTRL_TT3DOWNTO0_intermed_2;
RIN_A_CTRL_TT3DOWNTO0_intermed_4 <= RIN_A_CTRL_TT3DOWNTO0_intermed_3;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_A_CTRL_TT3DOWNTO0_shadow;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_2;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_4 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_3;
R_E_CTRL_TT3DOWNTO0_intermed_1 <= R.E.CTRL.TT( 3 DOWNTO 0 );
R_E_CTRL_TT3DOWNTO0_intermed_2 <= R_E_CTRL_TT3DOWNTO0_intermed_1;
RIN_M_CTRL_TT3DOWNTO0_intermed_1 <= RIN.M.CTRL.TT( 3 DOWNTO 0 );
RIN_M_CTRL_TT3DOWNTO0_intermed_2 <= RIN_M_CTRL_TT3DOWNTO0_intermed_1;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_M_CTRL_TT3DOWNTO0_shadow;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_M_CTRL_TT3DOWNTO0_shadow_intermed_1;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 );
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_E_CTRL_TT3DOWNTO0_shadow;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_2;
RIN_X_CTRL_TT3DOWNTO0_intermed_1 <= RIN.X.CTRL.TT( 3 DOWNTO 0 );
RIN_E_CTRL_TT3DOWNTO0_intermed_1 <= RIN.E.CTRL.TT( 3 DOWNTO 0 );
RIN_E_CTRL_TT3DOWNTO0_intermed_2 <= RIN_E_CTRL_TT3DOWNTO0_intermed_1;
RIN_E_CTRL_TT3DOWNTO0_intermed_3 <= RIN_E_CTRL_TT3DOWNTO0_intermed_2;
V_X_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_X_CTRL_TT3DOWNTO0_shadow;
V_X_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_X_CTRL_TT3DOWNTO0_shadow_intermed_1;
R_M_CTRL_TT3DOWNTO0_intermed_1 <= R.M.CTRL.TT( 3 DOWNTO 0 );
R_M_CTRL_TT3DOWNTO0_intermed_2 <= R_M_CTRL_TT3DOWNTO0_intermed_1;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_3 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2;
R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
R_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= R_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
R_A_CTRL_TT3DOWNTO0_intermed_1 <= R.A.CTRL.TT( 3 DOWNTO 0 );
R_A_CTRL_TT3DOWNTO0_intermed_2 <= R_A_CTRL_TT3DOWNTO0_intermed_1;
R_A_CTRL_TT3DOWNTO0_intermed_3 <= R_A_CTRL_TT3DOWNTO0_intermed_2;
R_A_CTRL_TT3DOWNTO0_intermed_4 <= R_A_CTRL_TT3DOWNTO0_intermed_3;
RIN_A_CTRL_TT3DOWNTO0_intermed_1 <= RIN.A.CTRL.TT( 3 DOWNTO 0 );
RIN_A_CTRL_TT3DOWNTO0_intermed_2 <= RIN_A_CTRL_TT3DOWNTO0_intermed_1;
RIN_A_CTRL_TT3DOWNTO0_intermed_3 <= RIN_A_CTRL_TT3DOWNTO0_intermed_2;
RIN_A_CTRL_TT3DOWNTO0_intermed_4 <= RIN_A_CTRL_TT3DOWNTO0_intermed_3;
RIN_A_CTRL_TT3DOWNTO0_intermed_5 <= RIN_A_CTRL_TT3DOWNTO0_intermed_4;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_A_CTRL_TT3DOWNTO0_shadow;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_2;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_4 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_3;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_5 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_4;
R_E_CTRL_TT3DOWNTO0_intermed_1 <= R.E.CTRL.TT( 3 DOWNTO 0 );
R_E_CTRL_TT3DOWNTO0_intermed_2 <= R_E_CTRL_TT3DOWNTO0_intermed_1;
R_E_CTRL_TT3DOWNTO0_intermed_3 <= R_E_CTRL_TT3DOWNTO0_intermed_2;
RIN_W_S_TT3DOWNTO0_intermed_1 <= RIN.W.S.TT( 3 DOWNTO 0 );
RIN_M_CTRL_TT3DOWNTO0_intermed_1 <= RIN.M.CTRL.TT( 3 DOWNTO 0 );
RIN_M_CTRL_TT3DOWNTO0_intermed_2 <= RIN_M_CTRL_TT3DOWNTO0_intermed_1;
RIN_M_CTRL_TT3DOWNTO0_intermed_3 <= RIN_M_CTRL_TT3DOWNTO0_intermed_2;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_M_CTRL_TT3DOWNTO0_shadow;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_M_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_M_CTRL_TT3DOWNTO0_shadow_intermed_2;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_3 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 );
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_E_CTRL_TT3DOWNTO0_shadow;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_2;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_4 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_3;
RIN_X_CTRL_TT3DOWNTO0_intermed_1 <= RIN.X.CTRL.TT( 3 DOWNTO 0 );
RIN_X_CTRL_TT3DOWNTO0_intermed_2 <= RIN_X_CTRL_TT3DOWNTO0_intermed_1;
R_X_CTRL_TT3DOWNTO0_intermed_1 <= R.X.CTRL.TT( 3 DOWNTO 0 );
RIN_E_CTRL_TT3DOWNTO0_intermed_1 <= RIN.E.CTRL.TT( 3 DOWNTO 0 );
RIN_E_CTRL_TT3DOWNTO0_intermed_2 <= RIN_E_CTRL_TT3DOWNTO0_intermed_1;
RIN_E_CTRL_TT3DOWNTO0_intermed_3 <= RIN_E_CTRL_TT3DOWNTO0_intermed_2;
RIN_E_CTRL_TT3DOWNTO0_intermed_4 <= RIN_E_CTRL_TT3DOWNTO0_intermed_3;
XC_VECTT3DOWNTO0_shadow_intermed_1 <= XC_VECTT3DOWNTO0_shadow;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
V_X_DATA03_shadow_intermed_1 <= V_X_DATA03_shadow;
V_X_DATA03_shadow_intermed_2 <= V_X_DATA03_shadow_intermed_1;
DCO_DATA03_intermed_1 <= DCO.DATA ( 0 )( 3 );
RIN_X_DATA03_intermed_1 <= RIN.X.DATA ( 0 )( 3 );
R_X_DATA03_intermed_1 <= R.X.DATA( 0 )( 3 );
RIN_X_DATA03_intermed_1 <= RIN.X.DATA( 0 )( 3 );
RIN_X_DATA03_intermed_2 <= RIN_X_DATA03_intermed_1;
R_M_CTRL_PC31DOWNTO12_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 12 );
R_M_CTRL_PC31DOWNTO12_intermed_2 <= R_M_CTRL_PC31DOWNTO12_intermed_1;
V_D_PC31DOWNTO12_shadow_intermed_1 <= V_D_PC31DOWNTO12_shadow;
V_D_PC31DOWNTO12_shadow_intermed_2 <= V_D_PC31DOWNTO12_shadow_intermed_1;
V_D_PC31DOWNTO12_shadow_intermed_3 <= V_D_PC31DOWNTO12_shadow_intermed_2;
V_D_PC31DOWNTO12_shadow_intermed_4 <= V_D_PC31DOWNTO12_shadow_intermed_3;
V_D_PC31DOWNTO12_shadow_intermed_5 <= V_D_PC31DOWNTO12_shadow_intermed_4;
V_D_PC31DOWNTO12_shadow_intermed_6 <= V_D_PC31DOWNTO12_shadow_intermed_5;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO12_shadow;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_4;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO12_shadow;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_3;
R_A_CTRL_PC31DOWNTO12_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 12 );
R_A_CTRL_PC31DOWNTO12_intermed_2 <= R_A_CTRL_PC31DOWNTO12_intermed_1;
R_A_CTRL_PC31DOWNTO12_intermed_3 <= R_A_CTRL_PC31DOWNTO12_intermed_2;
R_A_CTRL_PC31DOWNTO12_intermed_4 <= R_A_CTRL_PC31DOWNTO12_intermed_3;
R_E_CTRL_PC31DOWNTO12_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 12 );
R_E_CTRL_PC31DOWNTO12_intermed_2 <= R_E_CTRL_PC31DOWNTO12_intermed_1;
R_E_CTRL_PC31DOWNTO12_intermed_3 <= R_E_CTRL_PC31DOWNTO12_intermed_2;
RIN_A_CTRL_PC31DOWNTO12_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_2 <= RIN_A_CTRL_PC31DOWNTO12_intermed_1;
RIN_A_CTRL_PC31DOWNTO12_intermed_3 <= RIN_A_CTRL_PC31DOWNTO12_intermed_2;
RIN_A_CTRL_PC31DOWNTO12_intermed_4 <= RIN_A_CTRL_PC31DOWNTO12_intermed_3;
RIN_A_CTRL_PC31DOWNTO12_intermed_5 <= RIN_A_CTRL_PC31DOWNTO12_intermed_4;
RIN_E_CTRL_PC31DOWNTO12_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 12 );
RIN_E_CTRL_PC31DOWNTO12_intermed_2 <= RIN_E_CTRL_PC31DOWNTO12_intermed_1;
RIN_E_CTRL_PC31DOWNTO12_intermed_3 <= RIN_E_CTRL_PC31DOWNTO12_intermed_2;
RIN_E_CTRL_PC31DOWNTO12_intermed_4 <= RIN_E_CTRL_PC31DOWNTO12_intermed_3;
IRIN_ADDR31DOWNTO12_intermed_1 <= IRIN.ADDR( 31 DOWNTO 12 );
V_X_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO12_shadow;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_1;
RIN_M_CTRL_PC31DOWNTO12_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 12 );
RIN_M_CTRL_PC31DOWNTO12_intermed_2 <= RIN_M_CTRL_PC31DOWNTO12_intermed_1;
RIN_M_CTRL_PC31DOWNTO12_intermed_3 <= RIN_M_CTRL_PC31DOWNTO12_intermed_2;
R_X_CTRL_PC31DOWNTO12_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_1 <= R.D.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_2 <= R_D_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_3 <= R_D_PC31DOWNTO12_intermed_2;
R_D_PC31DOWNTO12_intermed_4 <= R_D_PC31DOWNTO12_intermed_3;
R_D_PC31DOWNTO12_intermed_5 <= R_D_PC31DOWNTO12_intermed_4;
RIN_X_CTRL_PC31DOWNTO12_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 12 );
RIN_X_CTRL_PC31DOWNTO12_intermed_2 <= RIN_X_CTRL_PC31DOWNTO12_intermed_1;
RIN_D_PC31DOWNTO12_intermed_1 <= RIN.D.PC( 31 DOWNTO 12 );
RIN_D_PC31DOWNTO12_intermed_2 <= RIN_D_PC31DOWNTO12_intermed_1;
RIN_D_PC31DOWNTO12_intermed_3 <= RIN_D_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_4 <= RIN_D_PC31DOWNTO12_intermed_3;
RIN_D_PC31DOWNTO12_intermed_5 <= RIN_D_PC31DOWNTO12_intermed_4;
RIN_D_PC31DOWNTO12_intermed_6 <= RIN_D_PC31DOWNTO12_intermed_5;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO12_shadow;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
V_D_PC31DOWNTO2_shadow_intermed_6 <= V_D_PC31DOWNTO2_shadow_intermed_5;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_D_PC31DOWNTO2_intermed_6 <= RIN_D_PC31DOWNTO2_intermed_5;
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
IRIN_ADDR31DOWNTO2_intermed_1 <= IRIN.ADDR( 31 DOWNTO 2 );
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_D_PC31DOWNTO2_intermed_5 <= R_D_PC31DOWNTO2_intermed_4;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_F_PC31DOWNTO4_shadow_intermed_1 <= V_F_PC31DOWNTO4_shadow;
V_X_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO4_shadow;
V_X_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO4_shadow_intermed_2;
IR_ADDR31DOWNTO4_intermed_1 <= IR.ADDR( 31 DOWNTO 4 );
VIR_ADDR31DOWNTO4_shadow_intermed_1 <= VIR_ADDR31DOWNTO4_shadow;
VIR_ADDR31DOWNTO4_shadow_intermed_2 <= VIR_ADDR31DOWNTO4_shadow_intermed_1;
RIN_F_PC31DOWNTO4_intermed_1 <= RIN.F.PC( 31 DOWNTO 4 );
RIN_A_CTRL_PC31DOWNTO4_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 4 );
RIN_A_CTRL_PC31DOWNTO4_intermed_2 <= RIN_A_CTRL_PC31DOWNTO4_intermed_1;
RIN_A_CTRL_PC31DOWNTO4_intermed_3 <= RIN_A_CTRL_PC31DOWNTO4_intermed_2;
RIN_A_CTRL_PC31DOWNTO4_intermed_4 <= RIN_A_CTRL_PC31DOWNTO4_intermed_3;
RIN_A_CTRL_PC31DOWNTO4_intermed_5 <= RIN_A_CTRL_PC31DOWNTO4_intermed_4;
RIN_A_CTRL_PC31DOWNTO4_intermed_6 <= RIN_A_CTRL_PC31DOWNTO4_intermed_5;
R_A_CTRL_PC31DOWNTO4_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 4 );
R_A_CTRL_PC31DOWNTO4_intermed_2 <= R_A_CTRL_PC31DOWNTO4_intermed_1;
R_A_CTRL_PC31DOWNTO4_intermed_3 <= R_A_CTRL_PC31DOWNTO4_intermed_2;
R_A_CTRL_PC31DOWNTO4_intermed_4 <= R_A_CTRL_PC31DOWNTO4_intermed_3;
R_A_CTRL_PC31DOWNTO4_intermed_5 <= R_A_CTRL_PC31DOWNTO4_intermed_4;
R_D_PC31DOWNTO4_intermed_1 <= R.D.PC( 31 DOWNTO 4 );
R_D_PC31DOWNTO4_intermed_2 <= R_D_PC31DOWNTO4_intermed_1;
R_D_PC31DOWNTO4_intermed_3 <= R_D_PC31DOWNTO4_intermed_2;
R_D_PC31DOWNTO4_intermed_4 <= R_D_PC31DOWNTO4_intermed_3;
R_D_PC31DOWNTO4_intermed_5 <= R_D_PC31DOWNTO4_intermed_4;
R_D_PC31DOWNTO4_intermed_6 <= R_D_PC31DOWNTO4_intermed_5;
RIN_X_CTRL_PC31DOWNTO4_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 4 );
RIN_X_CTRL_PC31DOWNTO4_intermed_2 <= RIN_X_CTRL_PC31DOWNTO4_intermed_1;
RIN_X_CTRL_PC31DOWNTO4_intermed_3 <= RIN_X_CTRL_PC31DOWNTO4_intermed_2;
EX_ADD_RES32DOWNTO332DOWNTO5_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO5_shadow;
V_D_PC31DOWNTO4_shadow_intermed_1 <= V_D_PC31DOWNTO4_shadow;
V_D_PC31DOWNTO4_shadow_intermed_2 <= V_D_PC31DOWNTO4_shadow_intermed_1;
V_D_PC31DOWNTO4_shadow_intermed_3 <= V_D_PC31DOWNTO4_shadow_intermed_2;
V_D_PC31DOWNTO4_shadow_intermed_4 <= V_D_PC31DOWNTO4_shadow_intermed_3;
V_D_PC31DOWNTO4_shadow_intermed_5 <= V_D_PC31DOWNTO4_shadow_intermed_4;
V_D_PC31DOWNTO4_shadow_intermed_6 <= V_D_PC31DOWNTO4_shadow_intermed_5;
V_D_PC31DOWNTO4_shadow_intermed_7 <= V_D_PC31DOWNTO4_shadow_intermed_6;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO4_shadow;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_4;
RIN_M_CTRL_PC31DOWNTO4_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 4 );
RIN_M_CTRL_PC31DOWNTO4_intermed_2 <= RIN_M_CTRL_PC31DOWNTO4_intermed_1;
RIN_M_CTRL_PC31DOWNTO4_intermed_3 <= RIN_M_CTRL_PC31DOWNTO4_intermed_2;
RIN_M_CTRL_PC31DOWNTO4_intermed_4 <= RIN_M_CTRL_PC31DOWNTO4_intermed_3;
R_X_CTRL_PC31DOWNTO4_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 4 );
R_X_CTRL_PC31DOWNTO4_intermed_2 <= R_X_CTRL_PC31DOWNTO4_intermed_1;
IRIN_ADDR31DOWNTO4_intermed_1 <= IRIN.ADDR( 31 DOWNTO 4 );
IRIN_ADDR31DOWNTO4_intermed_2 <= IRIN_ADDR31DOWNTO4_intermed_1;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO4_shadow;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_3;
R_M_CTRL_PC31DOWNTO4_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 4 );
R_M_CTRL_PC31DOWNTO4_intermed_2 <= R_M_CTRL_PC31DOWNTO4_intermed_1;
R_M_CTRL_PC31DOWNTO4_intermed_3 <= R_M_CTRL_PC31DOWNTO4_intermed_2;
RIN_D_PC31DOWNTO4_intermed_1 <= RIN.D.PC( 31 DOWNTO 4 );
RIN_D_PC31DOWNTO4_intermed_2 <= RIN_D_PC31DOWNTO4_intermed_1;
RIN_D_PC31DOWNTO4_intermed_3 <= RIN_D_PC31DOWNTO4_intermed_2;
RIN_D_PC31DOWNTO4_intermed_4 <= RIN_D_PC31DOWNTO4_intermed_3;
RIN_D_PC31DOWNTO4_intermed_5 <= RIN_D_PC31DOWNTO4_intermed_4;
RIN_D_PC31DOWNTO4_intermed_6 <= RIN_D_PC31DOWNTO4_intermed_5;
RIN_D_PC31DOWNTO4_intermed_7 <= RIN_D_PC31DOWNTO4_intermed_6;
RIN_E_CTRL_PC31DOWNTO4_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 4 );
RIN_E_CTRL_PC31DOWNTO4_intermed_2 <= RIN_E_CTRL_PC31DOWNTO4_intermed_1;
RIN_E_CTRL_PC31DOWNTO4_intermed_3 <= RIN_E_CTRL_PC31DOWNTO4_intermed_2;
RIN_E_CTRL_PC31DOWNTO4_intermed_4 <= RIN_E_CTRL_PC31DOWNTO4_intermed_3;
RIN_E_CTRL_PC31DOWNTO4_intermed_5 <= RIN_E_CTRL_PC31DOWNTO4_intermed_4;
EX_JUMP_ADDRESS31DOWNTO4_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO4_shadow;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO4_shadow;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_5;
R_E_CTRL_PC31DOWNTO4_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 4 );
R_E_CTRL_PC31DOWNTO4_intermed_2 <= R_E_CTRL_PC31DOWNTO4_intermed_1;
R_E_CTRL_PC31DOWNTO4_intermed_3 <= R_E_CTRL_PC31DOWNTO4_intermed_2;
R_E_CTRL_PC31DOWNTO4_intermed_4 <= R_E_CTRL_PC31DOWNTO4_intermed_3;
R_D_PC3DOWNTO2_intermed_1 <= R.D.PC( 3 DOWNTO 2 );
R_D_PC3DOWNTO2_intermed_2 <= R_D_PC3DOWNTO2_intermed_1;
R_D_PC3DOWNTO2_intermed_3 <= R_D_PC3DOWNTO2_intermed_2;
R_D_PC3DOWNTO2_intermed_4 <= R_D_PC3DOWNTO2_intermed_3;
R_D_PC3DOWNTO2_intermed_5 <= R_D_PC3DOWNTO2_intermed_4;
R_D_PC3DOWNTO2_intermed_6 <= R_D_PC3DOWNTO2_intermed_5;
V_D_PC3DOWNTO2_shadow_intermed_1 <= V_D_PC3DOWNTO2_shadow;
V_D_PC3DOWNTO2_shadow_intermed_2 <= V_D_PC3DOWNTO2_shadow_intermed_1;
V_D_PC3DOWNTO2_shadow_intermed_3 <= V_D_PC3DOWNTO2_shadow_intermed_2;
V_D_PC3DOWNTO2_shadow_intermed_4 <= V_D_PC3DOWNTO2_shadow_intermed_3;
V_D_PC3DOWNTO2_shadow_intermed_5 <= V_D_PC3DOWNTO2_shadow_intermed_4;
V_D_PC3DOWNTO2_shadow_intermed_6 <= V_D_PC3DOWNTO2_shadow_intermed_5;
V_D_PC3DOWNTO2_shadow_intermed_7 <= V_D_PC3DOWNTO2_shadow_intermed_6;
VIR_ADDR3DOWNTO2_shadow_intermed_1 <= VIR_ADDR3DOWNTO2_shadow;
VIR_ADDR3DOWNTO2_shadow_intermed_2 <= VIR_ADDR3DOWNTO2_shadow_intermed_1;
RIN_D_PC3DOWNTO2_intermed_1 <= RIN.D.PC( 3 DOWNTO 2 );
RIN_D_PC3DOWNTO2_intermed_2 <= RIN_D_PC3DOWNTO2_intermed_1;
RIN_D_PC3DOWNTO2_intermed_3 <= RIN_D_PC3DOWNTO2_intermed_2;
RIN_D_PC3DOWNTO2_intermed_4 <= RIN_D_PC3DOWNTO2_intermed_3;
RIN_D_PC3DOWNTO2_intermed_5 <= RIN_D_PC3DOWNTO2_intermed_4;
RIN_D_PC3DOWNTO2_intermed_6 <= RIN_D_PC3DOWNTO2_intermed_5;
RIN_D_PC3DOWNTO2_intermed_7 <= RIN_D_PC3DOWNTO2_intermed_6;
R_M_CTRL_PC3DOWNTO2_intermed_1 <= R.M.CTRL.PC( 3 DOWNTO 2 );
R_M_CTRL_PC3DOWNTO2_intermed_2 <= R_M_CTRL_PC3DOWNTO2_intermed_1;
R_M_CTRL_PC3DOWNTO2_intermed_3 <= R_M_CTRL_PC3DOWNTO2_intermed_2;
R_E_CTRL_PC3DOWNTO2_intermed_1 <= R.E.CTRL.PC( 3 DOWNTO 2 );
R_E_CTRL_PC3DOWNTO2_intermed_2 <= R_E_CTRL_PC3DOWNTO2_intermed_1;
R_E_CTRL_PC3DOWNTO2_intermed_3 <= R_E_CTRL_PC3DOWNTO2_intermed_2;
R_E_CTRL_PC3DOWNTO2_intermed_4 <= R_E_CTRL_PC3DOWNTO2_intermed_3;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC3DOWNTO2_shadow;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_3;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_4;
RIN_X_CTRL_PC3DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 3 DOWNTO 2 );
RIN_X_CTRL_PC3DOWNTO2_intermed_2 <= RIN_X_CTRL_PC3DOWNTO2_intermed_1;
RIN_X_CTRL_PC3DOWNTO2_intermed_3 <= RIN_X_CTRL_PC3DOWNTO2_intermed_2;
R_A_CTRL_PC3DOWNTO2_intermed_1 <= R.A.CTRL.PC( 3 DOWNTO 2 );
R_A_CTRL_PC3DOWNTO2_intermed_2 <= R_A_CTRL_PC3DOWNTO2_intermed_1;
R_A_CTRL_PC3DOWNTO2_intermed_3 <= R_A_CTRL_PC3DOWNTO2_intermed_2;
R_A_CTRL_PC3DOWNTO2_intermed_4 <= R_A_CTRL_PC3DOWNTO2_intermed_3;
R_A_CTRL_PC3DOWNTO2_intermed_5 <= R_A_CTRL_PC3DOWNTO2_intermed_4;
V_X_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC3DOWNTO2_shadow;
V_X_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC3DOWNTO2_shadow_intermed_2;
RIN_M_CTRL_PC3DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 3 DOWNTO 2 );
RIN_M_CTRL_PC3DOWNTO2_intermed_2 <= RIN_M_CTRL_PC3DOWNTO2_intermed_1;
RIN_M_CTRL_PC3DOWNTO2_intermed_3 <= RIN_M_CTRL_PC3DOWNTO2_intermed_2;
RIN_M_CTRL_PC3DOWNTO2_intermed_4 <= RIN_M_CTRL_PC3DOWNTO2_intermed_3;
IRIN_ADDR3DOWNTO2_intermed_1 <= IRIN.ADDR( 3 DOWNTO 2 );
IRIN_ADDR3DOWNTO2_intermed_2 <= IRIN_ADDR3DOWNTO2_intermed_1;
EX_JUMP_ADDRESS3DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS3DOWNTO2_shadow;
EX_ADD_RES32DOWNTO34DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO34DOWNTO3_shadow;
RIN_A_CTRL_PC3DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 3 DOWNTO 2 );
RIN_A_CTRL_PC3DOWNTO2_intermed_2 <= RIN_A_CTRL_PC3DOWNTO2_intermed_1;
RIN_A_CTRL_PC3DOWNTO2_intermed_3 <= RIN_A_CTRL_PC3DOWNTO2_intermed_2;
RIN_A_CTRL_PC3DOWNTO2_intermed_4 <= RIN_A_CTRL_PC3DOWNTO2_intermed_3;
RIN_A_CTRL_PC3DOWNTO2_intermed_5 <= RIN_A_CTRL_PC3DOWNTO2_intermed_4;
RIN_A_CTRL_PC3DOWNTO2_intermed_6 <= RIN_A_CTRL_PC3DOWNTO2_intermed_5;
V_F_PC3DOWNTO2_shadow_intermed_1 <= V_F_PC3DOWNTO2_shadow;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC3DOWNTO2_shadow;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_4;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_5;
IR_ADDR3DOWNTO2_intermed_1 <= IR.ADDR( 3 DOWNTO 2 );
V_M_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC3DOWNTO2_shadow;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_2;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_3;
R_X_CTRL_PC3DOWNTO2_intermed_1 <= R.X.CTRL.PC( 3 DOWNTO 2 );
R_X_CTRL_PC3DOWNTO2_intermed_2 <= R_X_CTRL_PC3DOWNTO2_intermed_1;
RIN_E_CTRL_PC3DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 3 DOWNTO 2 );
RIN_E_CTRL_PC3DOWNTO2_intermed_2 <= RIN_E_CTRL_PC3DOWNTO2_intermed_1;
RIN_E_CTRL_PC3DOWNTO2_intermed_3 <= RIN_E_CTRL_PC3DOWNTO2_intermed_2;
RIN_E_CTRL_PC3DOWNTO2_intermed_4 <= RIN_E_CTRL_PC3DOWNTO2_intermed_3;
RIN_E_CTRL_PC3DOWNTO2_intermed_5 <= RIN_E_CTRL_PC3DOWNTO2_intermed_4;
RIN_F_PC3DOWNTO2_intermed_1 <= RIN.F.PC( 3 DOWNTO 2 );
V_E_CTRL_RD7DOWNTO0_shadow_intermed_1 <= V_E_CTRL_RD7DOWNTO0_shadow;
V_E_CTRL_RD7DOWNTO0_shadow_intermed_2 <= V_E_CTRL_RD7DOWNTO0_shadow_intermed_1;
R_E_CTRL_RD7DOWNTO0_intermed_1 <= R.E.CTRL.RD ( 7 DOWNTO 0 );
V_A_CTRL_RD7DOWNTO0_shadow_intermed_1 <= V_A_CTRL_RD7DOWNTO0_shadow;
V_A_CTRL_RD7DOWNTO0_shadow_intermed_2 <= V_A_CTRL_RD7DOWNTO0_shadow_intermed_1;
V_A_CTRL_RD7DOWNTO0_shadow_intermed_3 <= V_A_CTRL_RD7DOWNTO0_shadow_intermed_2;
RIN_A_CTRL_RD7DOWNTO0_intermed_1 <= RIN.A.CTRL.RD ( 7 DOWNTO 0 );
RIN_A_CTRL_RD7DOWNTO0_intermed_2 <= RIN_A_CTRL_RD7DOWNTO0_intermed_1;
RIN_A_CTRL_RD7DOWNTO0_intermed_3 <= RIN_A_CTRL_RD7DOWNTO0_intermed_2;
R_A_CTRL_RD7DOWNTO0_intermed_1 <= R.A.CTRL.RD ( 7 DOWNTO 0 );
R_A_CTRL_RD7DOWNTO0_intermed_2 <= R_A_CTRL_RD7DOWNTO0_intermed_1;
RIN_E_CTRL_RD7DOWNTO0_intermed_1 <= RIN.E.CTRL.RD ( 7 DOWNTO 0 );
RIN_E_CTRL_RD7DOWNTO0_intermed_2 <= RIN_E_CTRL_RD7DOWNTO0_intermed_1;
RIN_M_CTRL_RD7DOWNTO0_intermed_1 <= RIN.M.CTRL.RD ( 7 DOWNTO 0 );
RIN_D_PC_intermed_1 <= RIN.D.PC;
RIN_D_PC_intermed_2 <= RIN_D_PC_intermed_1;
RIN_D_PC_intermed_3 <= RIN_D_PC_intermed_2;
RIN_D_PC_intermed_4 <= RIN_D_PC_intermed_3;
RIN_A_CTRL_PC_intermed_1 <= RIN.A.CTRL.PC;
RIN_A_CTRL_PC_intermed_2 <= RIN_A_CTRL_PC_intermed_1;
RIN_A_CTRL_PC_intermed_3 <= RIN_A_CTRL_PC_intermed_2;
R_A_CTRL_PC_intermed_1 <= R.A.CTRL.PC;
R_A_CTRL_PC_intermed_2 <= R_A_CTRL_PC_intermed_1;
V_E_CTRL_PC_shadow_intermed_1 <= V_E_CTRL_PC_shadow;
V_E_CTRL_PC_shadow_intermed_2 <= V_E_CTRL_PC_shadow_intermed_1;
R_E_CTRL_PC_intermed_1 <= R.E.CTRL.PC;
RIN_M_CTRL_PC_intermed_1 <= RIN.M.CTRL.PC;
V_A_CTRL_PC_shadow_intermed_1 <= V_A_CTRL_PC_shadow;
V_A_CTRL_PC_shadow_intermed_2 <= V_A_CTRL_PC_shadow_intermed_1;
V_A_CTRL_PC_shadow_intermed_3 <= V_A_CTRL_PC_shadow_intermed_2;
R_D_PC_intermed_1 <= R.D.PC;
R_D_PC_intermed_2 <= R_D_PC_intermed_1;
R_D_PC_intermed_3 <= R_D_PC_intermed_2;
RIN_E_CTRL_PC_intermed_1 <= RIN.E.CTRL.PC;
RIN_E_CTRL_PC_intermed_2 <= RIN_E_CTRL_PC_intermed_1;
V_D_PC_shadow_intermed_1 <= V_D_PC_shadow;
V_D_PC_shadow_intermed_2 <= V_D_PC_shadow_intermed_1;
V_D_PC_shadow_intermed_3 <= V_D_PC_shadow_intermed_2;
V_D_PC_shadow_intermed_4 <= V_D_PC_shadow_intermed_3;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST ( 20 );
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST( 20 );
RIN_A_CTRL_INST20_intermed_2 <= RIN_A_CTRL_INST20_intermed_1;
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
V_A_CTRL_INST20_shadow_intermed_2 <= V_A_CTRL_INST20_shadow_intermed_1;
DE_INST20_shadow_intermed_1 <= DE_INST20_shadow;
R_A_CTRL_INST20_intermed_1 <= R.A.CTRL.INST( 20 );
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST( 20 );
DE_INST20_shadow_intermed_1 <= DE_INST20_shadow;
R_A_CTRL_INST24_intermed_1 <= R.A.CTRL.INST( 24 );
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST( 24 );
RIN_A_CTRL_INST24_intermed_2 <= RIN_A_CTRL_INST24_intermed_1;
V_A_CTRL_INST24_shadow_intermed_1 <= V_A_CTRL_INST24_shadow;
V_A_CTRL_INST24_shadow_intermed_2 <= V_A_CTRL_INST24_shadow_intermed_1;
DE_INST24_shadow_intermed_1 <= DE_INST24_shadow;
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST ( 24 );
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST( 24 );
DE_INST24_shadow_intermed_1 <= DE_INST24_shadow;
RIN_A_CTRL_PC31DOWNTO4_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 4 );
RIN_A_CTRL_PC31DOWNTO4_intermed_2 <= RIN_A_CTRL_PC31DOWNTO4_intermed_1;
RIN_A_CTRL_PC31DOWNTO4_intermed_3 <= RIN_A_CTRL_PC31DOWNTO4_intermed_2;
RIN_A_CTRL_PC31DOWNTO4_intermed_4 <= RIN_A_CTRL_PC31DOWNTO4_intermed_3;
R_A_CTRL_PC31DOWNTO4_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 4 );
R_A_CTRL_PC31DOWNTO4_intermed_2 <= R_A_CTRL_PC31DOWNTO4_intermed_1;
R_A_CTRL_PC31DOWNTO4_intermed_3 <= R_A_CTRL_PC31DOWNTO4_intermed_2;
R_D_PC31DOWNTO4_intermed_1 <= R.D.PC( 31 DOWNTO 4 );
R_D_PC31DOWNTO4_intermed_2 <= R_D_PC31DOWNTO4_intermed_1;
R_D_PC31DOWNTO4_intermed_3 <= R_D_PC31DOWNTO4_intermed_2;
R_D_PC31DOWNTO4_intermed_4 <= R_D_PC31DOWNTO4_intermed_3;
RIN_X_CTRL_PC31DOWNTO4_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 4 );
V_D_PC31DOWNTO4_shadow_intermed_1 <= V_D_PC31DOWNTO4_shadow;
V_D_PC31DOWNTO4_shadow_intermed_2 <= V_D_PC31DOWNTO4_shadow_intermed_1;
V_D_PC31DOWNTO4_shadow_intermed_3 <= V_D_PC31DOWNTO4_shadow_intermed_2;
V_D_PC31DOWNTO4_shadow_intermed_4 <= V_D_PC31DOWNTO4_shadow_intermed_3;
V_D_PC31DOWNTO4_shadow_intermed_5 <= V_D_PC31DOWNTO4_shadow_intermed_4;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO4_shadow;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_2;
RIN_M_CTRL_PC31DOWNTO4_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 4 );
RIN_M_CTRL_PC31DOWNTO4_intermed_2 <= RIN_M_CTRL_PC31DOWNTO4_intermed_1;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO4_shadow;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_1;
R_M_CTRL_PC31DOWNTO4_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 4 );
RIN_D_PC31DOWNTO4_intermed_1 <= RIN.D.PC( 31 DOWNTO 4 );
RIN_D_PC31DOWNTO4_intermed_2 <= RIN_D_PC31DOWNTO4_intermed_1;
RIN_D_PC31DOWNTO4_intermed_3 <= RIN_D_PC31DOWNTO4_intermed_2;
RIN_D_PC31DOWNTO4_intermed_4 <= RIN_D_PC31DOWNTO4_intermed_3;
RIN_D_PC31DOWNTO4_intermed_5 <= RIN_D_PC31DOWNTO4_intermed_4;
RIN_E_CTRL_PC31DOWNTO4_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 4 );
RIN_E_CTRL_PC31DOWNTO4_intermed_2 <= RIN_E_CTRL_PC31DOWNTO4_intermed_1;
RIN_E_CTRL_PC31DOWNTO4_intermed_3 <= RIN_E_CTRL_PC31DOWNTO4_intermed_2;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO4_shadow;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_3;
R_E_CTRL_PC31DOWNTO4_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 4 );
R_E_CTRL_PC31DOWNTO4_intermed_2 <= R_E_CTRL_PC31DOWNTO4_intermed_1;
R_D_PC3DOWNTO2_intermed_1 <= R.D.PC( 3 DOWNTO 2 );
R_D_PC3DOWNTO2_intermed_2 <= R_D_PC3DOWNTO2_intermed_1;
R_D_PC3DOWNTO2_intermed_3 <= R_D_PC3DOWNTO2_intermed_2;
R_D_PC3DOWNTO2_intermed_4 <= R_D_PC3DOWNTO2_intermed_3;
V_D_PC3DOWNTO2_shadow_intermed_1 <= V_D_PC3DOWNTO2_shadow;
V_D_PC3DOWNTO2_shadow_intermed_2 <= V_D_PC3DOWNTO2_shadow_intermed_1;
V_D_PC3DOWNTO2_shadow_intermed_3 <= V_D_PC3DOWNTO2_shadow_intermed_2;
V_D_PC3DOWNTO2_shadow_intermed_4 <= V_D_PC3DOWNTO2_shadow_intermed_3;
V_D_PC3DOWNTO2_shadow_intermed_5 <= V_D_PC3DOWNTO2_shadow_intermed_4;
RIN_D_PC3DOWNTO2_intermed_1 <= RIN.D.PC( 3 DOWNTO 2 );
RIN_D_PC3DOWNTO2_intermed_2 <= RIN_D_PC3DOWNTO2_intermed_1;
RIN_D_PC3DOWNTO2_intermed_3 <= RIN_D_PC3DOWNTO2_intermed_2;
RIN_D_PC3DOWNTO2_intermed_4 <= RIN_D_PC3DOWNTO2_intermed_3;
RIN_D_PC3DOWNTO2_intermed_5 <= RIN_D_PC3DOWNTO2_intermed_4;
R_M_CTRL_PC3DOWNTO2_intermed_1 <= R.M.CTRL.PC( 3 DOWNTO 2 );
R_E_CTRL_PC3DOWNTO2_intermed_1 <= R.E.CTRL.PC( 3 DOWNTO 2 );
R_E_CTRL_PC3DOWNTO2_intermed_2 <= R_E_CTRL_PC3DOWNTO2_intermed_1;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC3DOWNTO2_shadow;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_2;
RIN_X_CTRL_PC3DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 3 DOWNTO 2 );
R_A_CTRL_PC3DOWNTO2_intermed_1 <= R.A.CTRL.PC( 3 DOWNTO 2 );
R_A_CTRL_PC3DOWNTO2_intermed_2 <= R_A_CTRL_PC3DOWNTO2_intermed_1;
R_A_CTRL_PC3DOWNTO2_intermed_3 <= R_A_CTRL_PC3DOWNTO2_intermed_2;
RIN_M_CTRL_PC3DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 3 DOWNTO 2 );
RIN_M_CTRL_PC3DOWNTO2_intermed_2 <= RIN_M_CTRL_PC3DOWNTO2_intermed_1;
RIN_A_CTRL_PC3DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 3 DOWNTO 2 );
RIN_A_CTRL_PC3DOWNTO2_intermed_2 <= RIN_A_CTRL_PC3DOWNTO2_intermed_1;
RIN_A_CTRL_PC3DOWNTO2_intermed_3 <= RIN_A_CTRL_PC3DOWNTO2_intermed_2;
RIN_A_CTRL_PC3DOWNTO2_intermed_4 <= RIN_A_CTRL_PC3DOWNTO2_intermed_3;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC3DOWNTO2_shadow;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_3;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC3DOWNTO2_shadow;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_1;
RIN_E_CTRL_PC3DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 3 DOWNTO 2 );
RIN_E_CTRL_PC3DOWNTO2_intermed_2 <= RIN_E_CTRL_PC3DOWNTO2_intermed_1;
RIN_E_CTRL_PC3DOWNTO2_intermed_3 <= RIN_E_CTRL_PC3DOWNTO2_intermed_2;
RIN_E_CTRL_RD6DOWNTO0_intermed_1 <= RIN.E.CTRL.RD( 6 DOWNTO 0 );
RIN_E_CTRL_RD6DOWNTO0_intermed_2 <= RIN_E_CTRL_RD6DOWNTO0_intermed_1;
RIN_M_CTRL_RD6DOWNTO0_intermed_1 <= RIN.M.CTRL.RD( 6 DOWNTO 0 );
R_E_CTRL_RD6DOWNTO0_intermed_1 <= R.E.CTRL.RD( 6 DOWNTO 0 );
V_E_CTRL_RD6DOWNTO0_shadow_intermed_1 <= V_E_CTRL_RD6DOWNTO0_shadow;
V_E_CTRL_RD6DOWNTO0_shadow_intermed_2 <= V_E_CTRL_RD6DOWNTO0_shadow_intermed_1;
V_A_CTRL_RD6DOWNTO0_shadow_intermed_1 <= V_A_CTRL_RD6DOWNTO0_shadow;
V_A_CTRL_RD6DOWNTO0_shadow_intermed_2 <= V_A_CTRL_RD6DOWNTO0_shadow_intermed_1;
V_A_CTRL_RD6DOWNTO0_shadow_intermed_3 <= V_A_CTRL_RD6DOWNTO0_shadow_intermed_2;
R_A_CTRL_RD6DOWNTO0_intermed_1 <= R.A.CTRL.RD( 6 DOWNTO 0 );
R_A_CTRL_RD6DOWNTO0_intermed_2 <= R_A_CTRL_RD6DOWNTO0_intermed_1;
RIN_A_CTRL_RD6DOWNTO0_intermed_1 <= RIN.A.CTRL.RD( 6 DOWNTO 0 );
RIN_A_CTRL_RD6DOWNTO0_intermed_2 <= RIN_A_CTRL_RD6DOWNTO0_intermed_1;
RIN_A_CTRL_RD6DOWNTO0_intermed_3 <= RIN_A_CTRL_RD6DOWNTO0_intermed_2;
RIN_A_CTRL_TT_intermed_1 <= RIN.A.CTRL.TT;
RIN_A_CTRL_TT_intermed_2 <= RIN_A_CTRL_TT_intermed_1;
R_A_CTRL_TT_intermed_1 <= R.A.CTRL.TT;
RIN_E_CTRL_TT_intermed_1 <= RIN.E.CTRL.TT;
V_A_CTRL_TT_shadow_intermed_1 <= V_A_CTRL_TT_shadow;
V_A_CTRL_TT_shadow_intermed_2 <= V_A_CTRL_TT_shadow_intermed_1;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1;
R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 );
R_M_CTRL_TT3DOWNTO0_intermed_1 <= R.M.CTRL.TT( 3 DOWNTO 0 );
R_A_CTRL_TT3DOWNTO0_intermed_1 <= R.A.CTRL.TT( 3 DOWNTO 0 );
R_A_CTRL_TT3DOWNTO0_intermed_2 <= R_A_CTRL_TT3DOWNTO0_intermed_1;
R_A_CTRL_TT3DOWNTO0_intermed_3 <= R_A_CTRL_TT3DOWNTO0_intermed_2;
RIN_A_CTRL_TT3DOWNTO0_intermed_1 <= RIN.A.CTRL.TT( 3 DOWNTO 0 );
RIN_A_CTRL_TT3DOWNTO0_intermed_2 <= RIN_A_CTRL_TT3DOWNTO0_intermed_1;
RIN_A_CTRL_TT3DOWNTO0_intermed_3 <= RIN_A_CTRL_TT3DOWNTO0_intermed_2;
RIN_A_CTRL_TT3DOWNTO0_intermed_4 <= RIN_A_CTRL_TT3DOWNTO0_intermed_3;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_A_CTRL_TT3DOWNTO0_shadow;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_2;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_4 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_3;
R_E_CTRL_TT3DOWNTO0_intermed_1 <= R.E.CTRL.TT( 3 DOWNTO 0 );
R_E_CTRL_TT3DOWNTO0_intermed_2 <= R_E_CTRL_TT3DOWNTO0_intermed_1;
RIN_M_CTRL_TT3DOWNTO0_intermed_1 <= RIN.M.CTRL.TT( 3 DOWNTO 0 );
RIN_M_CTRL_TT3DOWNTO0_intermed_2 <= RIN_M_CTRL_TT3DOWNTO0_intermed_1;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_M_CTRL_TT3DOWNTO0_shadow;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_M_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_E_CTRL_TT3DOWNTO0_shadow;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_2;
RIN_X_CTRL_TT3DOWNTO0_intermed_1 <= RIN.X.CTRL.TT( 3 DOWNTO 0 );
RIN_E_CTRL_TT3DOWNTO0_intermed_1 <= RIN.E.CTRL.TT( 3 DOWNTO 0 );
RIN_E_CTRL_TT3DOWNTO0_intermed_2 <= RIN_E_CTRL_TT3DOWNTO0_intermed_1;
RIN_E_CTRL_TT3DOWNTO0_intermed_3 <= RIN_E_CTRL_TT3DOWNTO0_intermed_2;
R_M_CTRL_PC31DOWNTO12_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 12 );
V_D_PC31DOWNTO12_shadow_intermed_1 <= V_D_PC31DOWNTO12_shadow;
V_D_PC31DOWNTO12_shadow_intermed_2 <= V_D_PC31DOWNTO12_shadow_intermed_1;
V_D_PC31DOWNTO12_shadow_intermed_3 <= V_D_PC31DOWNTO12_shadow_intermed_2;
V_D_PC31DOWNTO12_shadow_intermed_4 <= V_D_PC31DOWNTO12_shadow_intermed_3;
V_D_PC31DOWNTO12_shadow_intermed_5 <= V_D_PC31DOWNTO12_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO12_shadow;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO12_shadow;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_2;
R_A_CTRL_PC31DOWNTO12_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 12 );
R_A_CTRL_PC31DOWNTO12_intermed_2 <= R_A_CTRL_PC31DOWNTO12_intermed_1;
R_A_CTRL_PC31DOWNTO12_intermed_3 <= R_A_CTRL_PC31DOWNTO12_intermed_2;
R_E_CTRL_PC31DOWNTO12_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 12 );
R_E_CTRL_PC31DOWNTO12_intermed_2 <= R_E_CTRL_PC31DOWNTO12_intermed_1;
RIN_A_CTRL_PC31DOWNTO12_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_2 <= RIN_A_CTRL_PC31DOWNTO12_intermed_1;
RIN_A_CTRL_PC31DOWNTO12_intermed_3 <= RIN_A_CTRL_PC31DOWNTO12_intermed_2;
RIN_A_CTRL_PC31DOWNTO12_intermed_4 <= RIN_A_CTRL_PC31DOWNTO12_intermed_3;
RIN_E_CTRL_PC31DOWNTO12_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 12 );
RIN_E_CTRL_PC31DOWNTO12_intermed_2 <= RIN_E_CTRL_PC31DOWNTO12_intermed_1;
RIN_E_CTRL_PC31DOWNTO12_intermed_3 <= RIN_E_CTRL_PC31DOWNTO12_intermed_2;
RIN_M_CTRL_PC31DOWNTO12_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 12 );
RIN_M_CTRL_PC31DOWNTO12_intermed_2 <= RIN_M_CTRL_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_1 <= R.D.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_2 <= R_D_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_3 <= R_D_PC31DOWNTO12_intermed_2;
R_D_PC31DOWNTO12_intermed_4 <= R_D_PC31DOWNTO12_intermed_3;
RIN_X_CTRL_PC31DOWNTO12_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 12 );
RIN_D_PC31DOWNTO12_intermed_1 <= RIN.D.PC( 31 DOWNTO 12 );
RIN_D_PC31DOWNTO12_intermed_2 <= RIN_D_PC31DOWNTO12_intermed_1;
RIN_D_PC31DOWNTO12_intermed_3 <= RIN_D_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_4 <= RIN_D_PC31DOWNTO12_intermed_3;
RIN_D_PC31DOWNTO12_intermed_5 <= RIN_D_PC31DOWNTO12_intermed_4;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO12_shadow;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_A_CTRL_RD7DOWNTO0_shadow_intermed_1 <= V_A_CTRL_RD7DOWNTO0_shadow;
V_A_CTRL_RD7DOWNTO0_shadow_intermed_2 <= V_A_CTRL_RD7DOWNTO0_shadow_intermed_1;
RIN_A_CTRL_RD7DOWNTO0_intermed_1 <= RIN.A.CTRL.RD ( 7 DOWNTO 0 );
RIN_A_CTRL_RD7DOWNTO0_intermed_2 <= RIN_A_CTRL_RD7DOWNTO0_intermed_1;
R_A_CTRL_RD7DOWNTO0_intermed_1 <= R.A.CTRL.RD ( 7 DOWNTO 0 );
RIN_E_CTRL_RD7DOWNTO0_intermed_1 <= RIN.E.CTRL.RD ( 7 DOWNTO 0 );
RIN_D_PC_intermed_1 <= RIN.D.PC;
RIN_D_PC_intermed_2 <= RIN_D_PC_intermed_1;
RIN_D_PC_intermed_3 <= RIN_D_PC_intermed_2;
RIN_A_CTRL_PC_intermed_1 <= RIN.A.CTRL.PC;
RIN_A_CTRL_PC_intermed_2 <= RIN_A_CTRL_PC_intermed_1;
R_A_CTRL_PC_intermed_1 <= R.A.CTRL.PC;
V_A_CTRL_PC_shadow_intermed_1 <= V_A_CTRL_PC_shadow;
V_A_CTRL_PC_shadow_intermed_2 <= V_A_CTRL_PC_shadow_intermed_1;
R_D_PC_intermed_1 <= R.D.PC;
R_D_PC_intermed_2 <= R_D_PC_intermed_1;
RIN_E_CTRL_PC_intermed_1 <= RIN.E.CTRL.PC;
V_D_PC_shadow_intermed_1 <= V_D_PC_shadow;
V_D_PC_shadow_intermed_2 <= V_D_PC_shadow_intermed_1;
V_D_PC_shadow_intermed_3 <= V_D_PC_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO4_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 4 );
RIN_A_CTRL_PC31DOWNTO4_intermed_2 <= RIN_A_CTRL_PC31DOWNTO4_intermed_1;
RIN_A_CTRL_PC31DOWNTO4_intermed_3 <= RIN_A_CTRL_PC31DOWNTO4_intermed_2;
R_A_CTRL_PC31DOWNTO4_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 4 );
R_A_CTRL_PC31DOWNTO4_intermed_2 <= R_A_CTRL_PC31DOWNTO4_intermed_1;
R_D_PC31DOWNTO4_intermed_1 <= R.D.PC( 31 DOWNTO 4 );
R_D_PC31DOWNTO4_intermed_2 <= R_D_PC31DOWNTO4_intermed_1;
R_D_PC31DOWNTO4_intermed_3 <= R_D_PC31DOWNTO4_intermed_2;
V_D_PC31DOWNTO4_shadow_intermed_1 <= V_D_PC31DOWNTO4_shadow;
V_D_PC31DOWNTO4_shadow_intermed_2 <= V_D_PC31DOWNTO4_shadow_intermed_1;
V_D_PC31DOWNTO4_shadow_intermed_3 <= V_D_PC31DOWNTO4_shadow_intermed_2;
V_D_PC31DOWNTO4_shadow_intermed_4 <= V_D_PC31DOWNTO4_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO4_shadow;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_1;
RIN_M_CTRL_PC31DOWNTO4_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 4 );
RIN_D_PC31DOWNTO4_intermed_1 <= RIN.D.PC( 31 DOWNTO 4 );
RIN_D_PC31DOWNTO4_intermed_2 <= RIN_D_PC31DOWNTO4_intermed_1;
RIN_D_PC31DOWNTO4_intermed_3 <= RIN_D_PC31DOWNTO4_intermed_2;
RIN_D_PC31DOWNTO4_intermed_4 <= RIN_D_PC31DOWNTO4_intermed_3;
RIN_E_CTRL_PC31DOWNTO4_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 4 );
RIN_E_CTRL_PC31DOWNTO4_intermed_2 <= RIN_E_CTRL_PC31DOWNTO4_intermed_1;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO4_shadow;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_2;
R_E_CTRL_PC31DOWNTO4_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 4 );
R_D_PC3DOWNTO2_intermed_1 <= R.D.PC( 3 DOWNTO 2 );
R_D_PC3DOWNTO2_intermed_2 <= R_D_PC3DOWNTO2_intermed_1;
R_D_PC3DOWNTO2_intermed_3 <= R_D_PC3DOWNTO2_intermed_2;
V_D_PC3DOWNTO2_shadow_intermed_1 <= V_D_PC3DOWNTO2_shadow;
V_D_PC3DOWNTO2_shadow_intermed_2 <= V_D_PC3DOWNTO2_shadow_intermed_1;
V_D_PC3DOWNTO2_shadow_intermed_3 <= V_D_PC3DOWNTO2_shadow_intermed_2;
V_D_PC3DOWNTO2_shadow_intermed_4 <= V_D_PC3DOWNTO2_shadow_intermed_3;
RIN_D_PC3DOWNTO2_intermed_1 <= RIN.D.PC( 3 DOWNTO 2 );
RIN_D_PC3DOWNTO2_intermed_2 <= RIN_D_PC3DOWNTO2_intermed_1;
RIN_D_PC3DOWNTO2_intermed_3 <= RIN_D_PC3DOWNTO2_intermed_2;
RIN_D_PC3DOWNTO2_intermed_4 <= RIN_D_PC3DOWNTO2_intermed_3;
R_E_CTRL_PC3DOWNTO2_intermed_1 <= R.E.CTRL.PC( 3 DOWNTO 2 );
V_E_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC3DOWNTO2_shadow;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_1;
R_A_CTRL_PC3DOWNTO2_intermed_1 <= R.A.CTRL.PC( 3 DOWNTO 2 );
R_A_CTRL_PC3DOWNTO2_intermed_2 <= R_A_CTRL_PC3DOWNTO2_intermed_1;
RIN_M_CTRL_PC3DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 3 DOWNTO 2 );
RIN_A_CTRL_PC3DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 3 DOWNTO 2 );
RIN_A_CTRL_PC3DOWNTO2_intermed_2 <= RIN_A_CTRL_PC3DOWNTO2_intermed_1;
RIN_A_CTRL_PC3DOWNTO2_intermed_3 <= RIN_A_CTRL_PC3DOWNTO2_intermed_2;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC3DOWNTO2_shadow;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_2;
RIN_E_CTRL_PC3DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 3 DOWNTO 2 );
RIN_E_CTRL_PC3DOWNTO2_intermed_2 <= RIN_E_CTRL_PC3DOWNTO2_intermed_1;
RIN_E_CTRL_RD6DOWNTO0_intermed_1 <= RIN.E.CTRL.RD( 6 DOWNTO 0 );
V_A_CTRL_RD6DOWNTO0_shadow_intermed_1 <= V_A_CTRL_RD6DOWNTO0_shadow;
V_A_CTRL_RD6DOWNTO0_shadow_intermed_2 <= V_A_CTRL_RD6DOWNTO0_shadow_intermed_1;
R_A_CTRL_RD6DOWNTO0_intermed_1 <= R.A.CTRL.RD( 6 DOWNTO 0 );
RIN_A_CTRL_RD6DOWNTO0_intermed_1 <= RIN.A.CTRL.RD( 6 DOWNTO 0 );
RIN_A_CTRL_RD6DOWNTO0_intermed_2 <= RIN_A_CTRL_RD6DOWNTO0_intermed_1;
R_A_CTRL_TT3DOWNTO0_intermed_1 <= R.A.CTRL.TT( 3 DOWNTO 0 );
R_A_CTRL_TT3DOWNTO0_intermed_2 <= R_A_CTRL_TT3DOWNTO0_intermed_1;
RIN_A_CTRL_TT3DOWNTO0_intermed_1 <= RIN.A.CTRL.TT( 3 DOWNTO 0 );
RIN_A_CTRL_TT3DOWNTO0_intermed_2 <= RIN_A_CTRL_TT3DOWNTO0_intermed_1;
RIN_A_CTRL_TT3DOWNTO0_intermed_3 <= RIN_A_CTRL_TT3DOWNTO0_intermed_2;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_A_CTRL_TT3DOWNTO0_shadow;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_2;
R_E_CTRL_TT3DOWNTO0_intermed_1 <= R.E.CTRL.TT( 3 DOWNTO 0 );
RIN_M_CTRL_TT3DOWNTO0_intermed_1 <= RIN.M.CTRL.TT( 3 DOWNTO 0 );
V_E_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_E_CTRL_TT3DOWNTO0_shadow;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_1;
RIN_E_CTRL_TT3DOWNTO0_intermed_1 <= RIN.E.CTRL.TT( 3 DOWNTO 0 );
RIN_E_CTRL_TT3DOWNTO0_intermed_2 <= RIN_E_CTRL_TT3DOWNTO0_intermed_1;
V_D_PC31DOWNTO12_shadow_intermed_1 <= V_D_PC31DOWNTO12_shadow;
V_D_PC31DOWNTO12_shadow_intermed_2 <= V_D_PC31DOWNTO12_shadow_intermed_1;
V_D_PC31DOWNTO12_shadow_intermed_3 <= V_D_PC31DOWNTO12_shadow_intermed_2;
V_D_PC31DOWNTO12_shadow_intermed_4 <= V_D_PC31DOWNTO12_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO12_shadow;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO12_shadow;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_1;
R_A_CTRL_PC31DOWNTO12_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 12 );
R_A_CTRL_PC31DOWNTO12_intermed_2 <= R_A_CTRL_PC31DOWNTO12_intermed_1;
R_E_CTRL_PC31DOWNTO12_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_2 <= RIN_A_CTRL_PC31DOWNTO12_intermed_1;
RIN_A_CTRL_PC31DOWNTO12_intermed_3 <= RIN_A_CTRL_PC31DOWNTO12_intermed_2;
RIN_E_CTRL_PC31DOWNTO12_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 12 );
RIN_E_CTRL_PC31DOWNTO12_intermed_2 <= RIN_E_CTRL_PC31DOWNTO12_intermed_1;
RIN_M_CTRL_PC31DOWNTO12_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_1 <= R.D.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_2 <= R_D_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_3 <= R_D_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_1 <= RIN.D.PC( 31 DOWNTO 12 );
RIN_D_PC31DOWNTO12_intermed_2 <= RIN_D_PC31DOWNTO12_intermed_1;
RIN_D_PC31DOWNTO12_intermed_3 <= RIN_D_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_4 <= RIN_D_PC31DOWNTO12_intermed_3;
RIN_A_CTRL_PC31DOWNTO4_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 4 );
RIN_A_CTRL_PC31DOWNTO4_intermed_2 <= RIN_A_CTRL_PC31DOWNTO4_intermed_1;
R_A_CTRL_PC31DOWNTO4_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 4 );
R_D_PC31DOWNTO4_intermed_1 <= R.D.PC( 31 DOWNTO 4 );
R_D_PC31DOWNTO4_intermed_2 <= R_D_PC31DOWNTO4_intermed_1;
V_D_PC31DOWNTO4_shadow_intermed_1 <= V_D_PC31DOWNTO4_shadow;
V_D_PC31DOWNTO4_shadow_intermed_2 <= V_D_PC31DOWNTO4_shadow_intermed_1;
V_D_PC31DOWNTO4_shadow_intermed_3 <= V_D_PC31DOWNTO4_shadow_intermed_2;
RIN_D_PC31DOWNTO4_intermed_1 <= RIN.D.PC( 31 DOWNTO 4 );
RIN_D_PC31DOWNTO4_intermed_2 <= RIN_D_PC31DOWNTO4_intermed_1;
RIN_D_PC31DOWNTO4_intermed_3 <= RIN_D_PC31DOWNTO4_intermed_2;
RIN_E_CTRL_PC31DOWNTO4_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 4 );
V_A_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO4_shadow;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_1;
R_D_PC3DOWNTO2_intermed_1 <= R.D.PC( 3 DOWNTO 2 );
R_D_PC3DOWNTO2_intermed_2 <= R_D_PC3DOWNTO2_intermed_1;
V_D_PC3DOWNTO2_shadow_intermed_1 <= V_D_PC3DOWNTO2_shadow;
V_D_PC3DOWNTO2_shadow_intermed_2 <= V_D_PC3DOWNTO2_shadow_intermed_1;
V_D_PC3DOWNTO2_shadow_intermed_3 <= V_D_PC3DOWNTO2_shadow_intermed_2;
RIN_D_PC3DOWNTO2_intermed_1 <= RIN.D.PC( 3 DOWNTO 2 );
RIN_D_PC3DOWNTO2_intermed_2 <= RIN_D_PC3DOWNTO2_intermed_1;
RIN_D_PC3DOWNTO2_intermed_3 <= RIN_D_PC3DOWNTO2_intermed_2;
R_A_CTRL_PC3DOWNTO2_intermed_1 <= R.A.CTRL.PC( 3 DOWNTO 2 );
RIN_A_CTRL_PC3DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 3 DOWNTO 2 );
RIN_A_CTRL_PC3DOWNTO2_intermed_2 <= RIN_A_CTRL_PC3DOWNTO2_intermed_1;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC3DOWNTO2_shadow;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_1;
RIN_E_CTRL_PC3DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 3 DOWNTO 2 );
R_A_CTRL_TT3DOWNTO0_intermed_1 <= R.A.CTRL.TT( 3 DOWNTO 0 );
RIN_A_CTRL_TT3DOWNTO0_intermed_1 <= RIN.A.CTRL.TT( 3 DOWNTO 0 );
RIN_A_CTRL_TT3DOWNTO0_intermed_2 <= RIN_A_CTRL_TT3DOWNTO0_intermed_1;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_A_CTRL_TT3DOWNTO0_shadow;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_1;
RIN_E_CTRL_TT3DOWNTO0_intermed_1 <= RIN.E.CTRL.TT( 3 DOWNTO 0 );
V_D_PC31DOWNTO12_shadow_intermed_1 <= V_D_PC31DOWNTO12_shadow;
V_D_PC31DOWNTO12_shadow_intermed_2 <= V_D_PC31DOWNTO12_shadow_intermed_1;
V_D_PC31DOWNTO12_shadow_intermed_3 <= V_D_PC31DOWNTO12_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO12_shadow;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_1;
R_A_CTRL_PC31DOWNTO12_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_2 <= RIN_A_CTRL_PC31DOWNTO12_intermed_1;
RIN_E_CTRL_PC31DOWNTO12_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_1 <= R.D.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_2 <= R_D_PC31DOWNTO12_intermed_1;
RIN_D_PC31DOWNTO12_intermed_1 <= RIN.D.PC( 31 DOWNTO 12 );
RIN_D_PC31DOWNTO12_intermed_2 <= RIN_D_PC31DOWNTO12_intermed_1;
RIN_D_PC31DOWNTO12_intermed_3 <= RIN_D_PC31DOWNTO12_intermed_2;
RIN_A_CTRL_PC31DOWNTO4_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 4 );
R_D_PC31DOWNTO4_intermed_1 <= R.D.PC( 31 DOWNTO 4 );
V_D_PC31DOWNTO4_shadow_intermed_1 <= V_D_PC31DOWNTO4_shadow;
V_D_PC31DOWNTO4_shadow_intermed_2 <= V_D_PC31DOWNTO4_shadow_intermed_1;
RIN_D_PC31DOWNTO4_intermed_1 <= RIN.D.PC( 31 DOWNTO 4 );
RIN_D_PC31DOWNTO4_intermed_2 <= RIN_D_PC31DOWNTO4_intermed_1;
R_D_PC3DOWNTO2_intermed_1 <= R.D.PC( 3 DOWNTO 2 );
V_D_PC3DOWNTO2_shadow_intermed_1 <= V_D_PC3DOWNTO2_shadow;
V_D_PC3DOWNTO2_shadow_intermed_2 <= V_D_PC3DOWNTO2_shadow_intermed_1;
RIN_D_PC3DOWNTO2_intermed_1 <= RIN.D.PC( 3 DOWNTO 2 );
RIN_D_PC3DOWNTO2_intermed_2 <= RIN_D_PC3DOWNTO2_intermed_1;
RIN_A_CTRL_PC3DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 3 DOWNTO 2 );
V_D_PC31DOWNTO12_shadow_intermed_1 <= V_D_PC31DOWNTO12_shadow;
V_D_PC31DOWNTO12_shadow_intermed_2 <= V_D_PC31DOWNTO12_shadow_intermed_1;
RIN_A_CTRL_PC31DOWNTO12_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_1 <= R.D.PC( 31 DOWNTO 12 );
RIN_D_PC31DOWNTO12_intermed_1 <= RIN.D.PC( 31 DOWNTO 12 );
RIN_D_PC31DOWNTO12_intermed_2 <= RIN_D_PC31DOWNTO12_intermed_1;
end if;
end process;
dfp_trap_vector(0) <= '1' when (RP.ERROR /= RPIN_ERROR_intermed_1) else '0';
dfp_trap_vector(1) <= '1' when (RP.ERROR /= VP_ERROR_shadow_intermed_1) else '0';
dfp_trap_vector(2) <= '1' when (RFI.REN1 /= DE_REN1_shadow) else '0';
dfp_trap_vector(3) <= '1' when (RFI.REN2 /= DE_REN2_shadow) else '0';
dfp_trap_vector(4) <= '1' when (RFI.DIAG(0) /= DCO.TESTEN) else '0';
dfp_trap_vector(5) <= '1' when (RFI.DIAG /= "0000") else '0';
dfp_trap_vector(6) <= '1' when (ICI.DPC(31 downto 2) /= R.D.PC ( 31 DOWNTO 2 )) else '0';
dfp_trap_vector(7) <= '1' when (ICI.FPC(31 downto 2) /= R.F.PC ( 31 DOWNTO 2 )) else '0';
dfp_trap_vector(8) <= '1' when (ICI.RPC(31 downto 2) /= NPC31DOWNTO2_shadow) else '0';
dfp_trap_vector(9) <= '1' when (ICI.FLUSHL /= '0') else '0';
dfp_trap_vector(10) <= '1' when (MULI.OP1(31 downto 0) /= EX_OP1_shadow) else '0';
dfp_trap_vector(11) <= '1' when (MULI.OP1(31) /= EX_OP131_shadow) else '0';
dfp_trap_vector(12) <= '1' when (MULI.OP2(31 downto 0) /= MUL_OP2_shadow) else '0';
dfp_trap_vector(13) <= '1' when (MULI.OP2(31) /= MUL_OP231_shadow) else '0';
dfp_trap_vector(14) <= '1' when (DIVI.START /= R.A.DIVSTART) else '0';
dfp_trap_vector(15) <= '1' when (DIVI.OP1(31 downto 0) /= EX_OP1_shadow) else '0';
dfp_trap_vector(16) <= '1' when (DIVI.OP1(31) /= EX_OP131_shadow) else '0';
dfp_trap_vector(17) <= '1' when (DIVI.OP2(31) /= EX_OP231_shadow) else '0';
dfp_trap_vector(18) <= '1' when (DIVI.OP2(31 downto 0) /= EX_OP2_shadow) else '0';
dfp_trap_vector(19) <= '1' when (DIVI.Y(31 downto 0) /= R.M.Y) else '0';
dfp_trap_vector(20) <= '1' when (DIVI.Y(31) /= R.M.Y ( 31 )) else '0';
dfp_trap_vector(21) <= '1' when (EX_JUMP_ADDRESS31DOWNTO12_shadow /= EX_ADD_RES32DOWNTO332DOWNTO13_shadow) else '0';
dfp_trap_vector(22) <= '1' when (DSUR.CRDY ( 2 ) /= DSUIN_CRDY2_intermed_1) else '0';
dfp_trap_vector(23) <= '1' when (DSUR.CRDY ( 2 ) /= VDSU_CRDY2_shadow_intermed_1) else '0';
dfp_trap_vector(24) <= '1' when (V_A_STEP_shadow /= RIN_A_STEP_intermed_1) else '0';
dfp_trap_vector(25) <= '1' when (V_D_STEP_shadow /= RIN_D_STEP_intermed_1) else '0';
dfp_trap_vector(26) <= '1' when (V_D_STEP_shadow /= DBGI.STEP) else '0';
dfp_trap_vector(27) <= '1' when (V_D_STEP_shadow /= R.D.STEP) else '0';
dfp_trap_vector(28) <= '1' when (RIN.X.RESULT ( 6 DOWNTO 0 ) /= V_X_RESULT6DOWNTO0_shadow) else '0';
dfp_trap_vector(29) <= '1' when (RIN.X.DATA ( 0 ) /= V_X_DATA0_shadow) else '0';
dfp_trap_vector(30) <= '1' when (RIN.X.CTRL.PC ( 31 DOWNTO 2 ) /= V_X_CTRL_PC31DOWNTO2_shadow) else '0';
dfp_trap_vector(31) <= '1' when (RIN.X.CTRL.PC ( 31 DOWNTO 2 ) /= R.M.CTRL.PC ( 31 DOWNTO 2 )) else '0';
dfp_trap_vector(32) <= '1' when (RIN.W.S.TT ( 3 DOWNTO 0 ) /= V_W_S_TT3DOWNTO0_shadow) else '0';
dfp_trap_vector(33) <= '1' when (RIN.M.RESULT ( 1 DOWNTO 0 ) /= V_M_RESULT1DOWNTO0_shadow) else '0';
dfp_trap_vector(34) <= '1' when (RIN.X.DATA ( 0 ) ( 31 ) /= V_X_DATA031_shadow) else '0';
dfp_trap_vector(35) <= '1' when (RIN.X.DATA ( 0 )( 31 ) /= V_X_DATA031_shadow) else '0';
dfp_trap_vector(36) <= '1' when (RIN.E.CTRL.INST ( 19 ) /= V_E_CTRL_INST19_shadow) else '0';
dfp_trap_vector(37) <= '1' when (RIN.E.CTRL.INST ( 19 ) /= R.A.CTRL.INST ( 19 )) else '0';
dfp_trap_vector(38) <= '1' when (RIN.E.CTRL.INST ( 20 ) /= R.A.CTRL.INST ( 20 )) else '0';
dfp_trap_vector(39) <= '1' when (RIN.E.CTRL.INST ( 20 ) /= V_E_CTRL_INST20_shadow) else '0';
dfp_trap_vector(40) <= '1' when (RIN.X.DATA ( 0 ) ( 0 ) /= V_X_DATA00_shadow) else '0';
dfp_trap_vector(41) <= '1' when (RIN.X.DATA ( 0 )( 0 ) /= V_X_DATA00_shadow) else '0';
dfp_trap_vector(42) <= '1' when (RIN.X.DATA ( 0 ) ( 4 DOWNTO 0 ) /= V_X_DATA04DOWNTO0_shadow) else '0';
dfp_trap_vector(43) <= '1' when (RIN.X.DATA ( 0 )( 4 DOWNTO 0 ) /= V_X_DATA04DOWNTO0_shadow) else '0';
dfp_trap_vector(44) <= '1' when (RIN.F.PC ( 31 DOWNTO 2 ) /= V_F_PC31DOWNTO2_shadow) else '0';
dfp_trap_vector(45) <= '1' when (RIN.D.PC ( 31 DOWNTO 2 ) /= V_D_PC31DOWNTO2_shadow) else '0';
dfp_trap_vector(46) <= '1' when (RIN.E.CTRL.INST ( 24 ) /= V_E_CTRL_INST24_shadow) else '0';
dfp_trap_vector(47) <= '1' when (RIN.E.CTRL.INST ( 24 ) /= R.A.CTRL.INST ( 24 )) else '0';
dfp_trap_vector(48) <= '1' when (RIN.A.CTRL.INST ( 19 ) /= V_A_CTRL_INST19_shadow) else '0';
dfp_trap_vector(49) <= '1' when (RIN.M.Y ( 31 ) /= V_M_Y31_shadow) else '0';
dfp_trap_vector(50) <= '1' when (V_A_STEP_shadow /= R.D.STEP) else '0';
dfp_trap_vector(51) <= '1' when (DSUIN.CRDY ( 2 ) /= VDSU_CRDY2_shadow) else '0';
dfp_trap_vector(52) <= '1' when (V_A_STEP_shadow /= R.A.STEP) else '0';
dfp_trap_vector(53) <= '1' when (V_A_STEP_shadow /= DBGI_STEP_intermed_1) else '0';
dfp_trap_vector(54) <= '1' when (V_A_STEP_shadow /= V_D_STEP_shadow_intermed_1) else '0';
dfp_trap_vector(55) <= '1' when (RIN.A.CTRL.PC ( 31 DOWNTO 2 ) /= V_A_CTRL_PC31DOWNTO2_shadow) else '0';
dfp_trap_vector(56) <= '1' when (RIN.E.CTRL.PC ( 31 DOWNTO 2 ) /= R.A.CTRL.PC ( 31 DOWNTO 2 )) else '0';
dfp_trap_vector(57) <= '1' when (RIN.E.CTRL.PC ( 31 DOWNTO 2 ) /= V_E_CTRL_PC31DOWNTO2_shadow) else '0';
dfp_trap_vector(58) <= '1' when (RIN.M.CTRL.PC ( 31 DOWNTO 2 ) /= V_M_CTRL_PC31DOWNTO2_shadow) else '0';
dfp_trap_vector(59) <= '1' when (RIN.M.CTRL.PC ( 31 DOWNTO 2 ) /= R.E.CTRL.PC ( 31 DOWNTO 2 )) else '0';
dfp_trap_vector(60) <= '1' when (RIN.X.DATA ( 1 ) /= V_X_DATA1_shadow) else '0';
dfp_trap_vector(61) <= '1' when (RIN.F.PC ( 31 DOWNTO 12 ) /= V_F_PC31DOWNTO12_shadow) else '0';
dfp_trap_vector(62) <= '1' when (RIN.D.INST ( 0 ) /= V_D_INST0_shadow) else '0';
dfp_trap_vector(63) <= '1' when (RIN.D.INST ( 1 ) /= V_D_INST1_shadow) else '0';
dfp_trap_vector(64) <= '1' when (RIN.X.DATA ( 0 )( 3 ) /= V_X_DATA03_shadow) else '0';
dfp_trap_vector(65) <= '1' when (RIN.A.CTRL.INST ( 20 ) /= V_A_CTRL_INST20_shadow) else '0';
dfp_trap_vector(66) <= '1' when (RIN.A.CTRL.INST ( 24 ) /= V_A_CTRL_INST24_shadow) else '0';
dfp_trap_vector(67) <= '1' when (RIN.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 ) /= V_X_RESULT6DOWNTO03DOWNTO0_shadow) else '0';
dfp_trap_vector(68) <= '1' when (XC_HALT_shadow /= DBGI.HALT) else '0';
dfp_trap_vector(69) <= '1' when (XC_HALT_shadow /= '0') else '0';
dfp_trap_vector(70) <= '1' when (V_A_CTRL_TT_shadow /= RIN_A_CTRL_TT_intermed_1) else '0';
dfp_trap_vector(71) <= '1' when (V_A_CTRL_TT_shadow /= R.A.CTRL.TT) else '0';
dfp_trap_vector(72) <= '1' when (V_A_CTRL_TT_shadow /= "000000") else '0';
dfp_trap_vector(73) <= '1' when (V_A_CTRL_INST_shadow /= DE_INST_shadow) else '0';
dfp_trap_vector(74) <= '1' when (V_A_CTRL_PC_shadow /= R.D.PC) else '0';
dfp_trap_vector(75) <= '1' when (V_A_CTRL_CNT_shadow /= R.D.CNT) else '0';
dfp_trap_vector(76) <= '1' when (V_A_STEP_shadow /= RIN_D_STEP_intermed_1) else '0';
dfp_trap_vector(77) <= '1' when (V_X_NERROR_shadow /= VP_ERROR_shadow_intermed_1) else '0';
dfp_trap_vector(78) <= '1' when (V_X_NERROR_shadow /= RPIN_ERROR_intermed_1) else '0';
dfp_trap_vector(79) <= '1' when (V_X_NERROR_shadow /= RP.ERROR) else '0';
dfp_trap_vector(80) <= '1' when (V_M_MAC_shadow /= R.E.MAC) else '0';
dfp_trap_vector(81) <= '1' when (V_M_MAC_shadow /= R.M.MAC) else '0';
dfp_trap_vector(82) <= '1' when (V_E_JMPL_shadow /= R.A.JMPL) else '0';
dfp_trap_vector(83) <= '1' when (V_E_CTRL_RETT_shadow /= R.A.CTRL.RETT) else '0';
dfp_trap_vector(84) <= '1' when (V_E_SU_shadow /= R.A.SU) else '0';
dfp_trap_vector(85) <= '1' when (V_E_ET_shadow /= R.A.ET) else '0';
dfp_trap_vector(86) <= '1' when (V_A_CWP_shadow /= R.D.CWP) else '0';
dfp_trap_vector(87) <= '1' when (V_A_CTRL_TRAP_shadow /= R.D.MEXC) else '0';
dfp_trap_vector(88) <= '1' when (V_A_CTRL_TRAP_shadow /= V_D_MEXC_shadow_intermed_1) else '0';
dfp_trap_vector(89) <= '1' when (V_A_CTRL_TRAP_shadow /= RIN_D_MEXC_intermed_1) else '0';
dfp_trap_vector(90) <= '1' when (VP_PWD_shadow /= RP.PWD) else '0';
dfp_trap_vector(91) <= '1' when (VP_PWD_shadow /= '0') else '0';
dfp_trap_vector(92) <= '1' when (VP_PWD_shadow /= RPIN_PWD_intermed_1) else '0';
dfp_trap_vector(93) <= '1' when (V_M_MUL_shadow /= R.M.MUL) else '0';
dfp_trap_vector(94) <= '1' when (V_M_MAC_shadow /= V_E_MAC_shadow_intermed_1) else '0';
dfp_trap_vector(95) <= '1' when (V_M_MAC_shadow /= RIN_M_MAC_intermed_1) else '0';
dfp_trap_vector(96) <= '1' when (V_M_MAC_shadow /= RIN_E_MAC_intermed_1) else '0';
dfp_trap_vector(97) <= '1' when (VDSU_TBUFCNT_shadow /= TBUFCNTX_shadow) else '0';
dfp_trap_vector(98) <= '1' when (V_M_MUL_shadow /= RIN_M_MUL_intermed_1) else '0';
dfp_trap_vector(99) <= '1' when (V_M_MUL_shadow /= '0') else '0';
dfp_trap_vector(100) <= '1' when (V_W_RESULT_shadow /= XC_RESULT_shadow) else '0';
dfp_trap_vector(101) <= '1' when (V_W_WA_shadow /= XC_WADDR7DOWNTO0_shadow) else '0';
dfp_trap_vector(102) <= '1' when (V_W_S_SVT_shadow /= R.W.S.SVT) else '0';
dfp_trap_vector(103) <= '1' when (V_W_S_SVT_shadow /= '0') else '0';
dfp_trap_vector(104) <= '1' when (V_W_S_SVT_shadow /= RIN_W_S_SVT_intermed_1) else '0';
dfp_trap_vector(105) <= '1' when (V_W_S_DWT_shadow /= RIN_W_S_DWT_intermed_1) else '0';
dfp_trap_vector(106) <= '1' when (V_W_S_DWT_shadow /= R.W.S.DWT) else '0';
dfp_trap_vector(107) <= '1' when (V_W_S_DWT_shadow /= '0') else '0';
dfp_trap_vector(108) <= '1' when (V_M_CTRL_RETT_shadow /= R.E.CTRL.RETT) else '0';
dfp_trap_vector(109) <= '1' when (V_E_CWP_shadow /= R.A.CWP) else '0';
dfp_trap_vector(110) <= '1' when (V_M_SU_shadow /= R.E.SU) else '0';
dfp_trap_vector(111) <= '1' when (V_X_DCI_shadow /= R.M.DCI) else '0';
dfp_trap_vector(112) <= '1' when (V_X_CTRL_RETT_shadow /= R.M.CTRL.RETT) else '0';
dfp_trap_vector(113) <= '1' when (V_X_MAC_shadow /= V_E_MAC_shadow_intermed_2) else '0';
dfp_trap_vector(114) <= '1' when (V_X_MAC_shadow /= RIN_M_MAC_intermed_1) else '0';
dfp_trap_vector(115) <= '1' when (V_X_MAC_shadow /= RIN_E_MAC_intermed_2) else '0';
dfp_trap_vector(116) <= '1' when (V_X_MAC_shadow /= R_E_MAC_intermed_1) else '0';
dfp_trap_vector(117) <= '1' when (V_X_MAC_shadow /= R.M.MAC) else '0';
dfp_trap_vector(118) <= '1' when (V_X_MAC_shadow /= V_M_MAC_shadow_intermed_1) else '0';
dfp_trap_vector(119) <= '1' when (V_X_MAC_shadow /= RIN_X_MAC_intermed_1) else '0';
dfp_trap_vector(120) <= '1' when (V_X_MAC_shadow /= R.X.MAC) else '0';
dfp_trap_vector(121) <= '1' when (V_X_LADDR_shadow /= R.M.RESULT ( 1 DOWNTO 0 )) else '0';
dfp_trap_vector(122) <= '1' when (V_X_MEXC_shadow /= DCO.MEXC) else '0';
dfp_trap_vector(123) <= '1' when (V_X_ICC_shadow /= ME_ICC_shadow) else '0';
dfp_trap_vector(124) <= '1' when (TRIGGERCPFAULT /= '0') else '0';
dfp_or_reduce : process(dfp_trap_vector)
variable or_reduce_62 : std_logic_vector(61 downto 0);
variable or_reduce_31 : std_logic_vector(30 downto 0);
variable or_reduce_16 : std_logic_vector(15 downto 0);
variable or_reduce_8 : std_logic_vector(7 downto 0);
variable or_reduce_4 : std_logic_vector(3 downto 0);
variable or_reduce_2 : std_logic_vector(1 downto 0);
begin
or_reduce_62 := dfp_trap_vector(123 downto 62) OR dfp_trap_vector(61 downto 0);
or_reduce_31 := or_reduce_62(61 downto 31) OR or_reduce_62(30 downto 0);
or_reduce_16 := or_reduce_31(30 downto 15) OR (dfp_trap_vector(124) & or_reduce_31(14 downto 0));
or_reduce_8 := or_reduce_16(15 downto 8) OR or_reduce_16(7 downto 0);
or_reduce_4 := or_reduce_8(7 downto 4) OR or_reduce_8(3 downto 0);
or_reduce_2 := or_reduce_4(3 downto 2) OR or_reduce_4(1 downto 0);
or_reduce_1 <= or_reduce_2(0) OR or_reduce_2(1);
end process;
trap_enable_delay : process(clk)
begin
if(rising_edge(clk))then
if(rstn = '0')then
dfp_delay_start <= 15;
elsif(dfp_delay_start /= 0)then
dfp_delay_start <= dfp_delay_start - 1;
end if;
end if;
end process;
trap_mem : process(clk)
begin
if(rising_edge(clk))then
if(rstn = '0')then
dfp_trap_mem <= (others => '0');
elsif(dfp_delay_start = 0)then
dfp_trap_mem <= dfp_trap_mem OR dfp_trap_vector;
end if;
end if;
end process;
handlerTrap <= or_reduce_1 when (dfp_delay_start = 0) else '0';
preg : process (sclk)
begin
if rising_edge(sclk) then
rp <= rpin;
if rstn = '0' then
rp.error <= '0';
end if;
end if;
end process;
reg : process (clk)
begin
if rising_edge(clk) then
if (holdn = '1') then
r <= rin;
else
r.x.ipend <= rin.x.ipend;
r.m.werr <= rin.m.werr;
if (holdn or ico.mds) = '0' then
r.d.inst <= rin.d.inst; r.d.mexc <= rin.d.mexc;
r.d.set <= rin.d.set;
end if;
if (holdn or dco.mds) = '0' then
r.x.data <= rin.x.data; r.x.mexc <= rin.x.mexc;
r.x.set <= rin.x.set;
end if;
end if;
if rstn = '0' then
r.w.s.s <= '1';
r.w.s.ps <= '1';
end if;
end if;
end process;
dsureg : process(clk) begin
if rising_edge(clk) then
if holdn = '1' then
dsur <= dsuin;
else
dsur.crdy <= dsuin.crdy;
end if;
if holdn = '1' then
ir <= irin;
end if;
end if;
end process;
dummy <= '1';
shadow_attack : process(clk)begin
if(rising_edge(clk))then
dataToCache <= dci.edata;
triggerCPFault <= '0';
IF(dci.write = '1')then
IF(dataToCache = X"6841_636B")THEN
triggerCPFault <= '1';
END IF;
END IF;
end if;
end process;
end;
| mit | dcc973d38a6c4cf47cbc7c289fb78796 | 0.687051 | 2.271969 | false | false | false | false |
michaelfivez/ascon_hardware_implementation | ascon128128_iterated/Kernel/Ascon_block_datapath.vhd | 1 | 6,352 | -------------------------------------------------------------------------------
--! @project Iterate hardware implementation of Asconv128128
--! @author Michael Fivez
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is an hardware implementation made for my graduation thesis
--! at the KULeuven, in the COSIC department (year 2015-2016)
--! The thesis is titled 'Energy efficient hardware implementations of CAESAR submissions',
--! and can be found on the COSIC website (www.esat.kuleuven.be/cosic/publications)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Ascon_StateUpdate_datapath is
port(
Clk : in std_logic; -- Clock
Reset : in std_logic; -- Reset (synchronous)
-- Control signals
RoundNr : in std_logic_vector(3 downto 0); -- biggest round is 12
sel1,sel2,sel3,sel4 : in std_logic_vector(1 downto 0);
sel0 : in std_logic_vector(2 downto 0);
selout : in std_logic;
Reg0En,Reg1En,Reg2En,Reg3En,Reg4En,RegOutEn : in std_logic;
ActivateGen : in std_logic;
GenSize : in std_logic_vector(3 downto 0);
-- Data signals
IV : in std_logic_vector(127 downto 0);
Key : in std_logic_vector(127 downto 0);
DataIn : in std_logic_vector(127 downto 0);
DataOut : out std_logic_vector(127 downto 0)
);
end entity Ascon_StateUpdate_datapath;
architecture structural of Ascon_StateUpdate_datapath is
-- constants
constant EXTRAIV : std_logic_vector(63 downto 0) := x"80800c0800000000"; -- used in the initialization
constant SEPCONSTANT : std_logic_vector(63 downto 0) := x"0000000000000001";
constant ADCONSTANT : std_logic_vector(63 downto 0) := x"8000000000000000";
-- Register signals
signal Reg0In,Reg1In,Reg2In,Reg3In,Reg4In : std_logic_vector(63 downto 0);
signal Reg0Out,Reg1Out,Reg2Out,Reg3Out,Reg4Out : std_logic_vector(63 downto 0);
signal RegOutIn,RegOutOut : std_logic_vector(127 downto 0);
-- Internal signals on datapath
signal SboxOut0,SboxOut1,SboxOut2,SboxOut3,SboxOut4 : std_logic_vector(63 downto 0);
signal DiffOut0,DiffOut1,DiffOut2,DiffOut3,DiffOut4 : std_logic_vector(63 downto 0);
signal XorReg01,XorReg02,XorReg11,XorReg12 : std_logic_vector(63 downto 0);
signal XorReg2,XorReg31,XorReg32,XorReg4 : std_logic_vector(63 downto 0);
signal OutSig0,OutSig1 : std_logic_vector(127 downto 0);
begin
-- declare and connect all sub entities
sbox: entity work.Sbox port map(Reg0Out,Reg1Out,Reg2Out,Reg3Out,Reg4Out,RoundNr,SboxOut0,SboxOut1,SboxOut2,SboxOut3,SboxOut4);
difflayer: entity work.FullDiffusionLayer port map(SboxOut0,SboxOut1,SboxOut2,SboxOut3,SboxOut4,DiffOut0,DiffOut1,DiffOut2,DiffOut3,DiffOut4);
outpgen: entity work.OutputGenerator port map(Reg0Out,Reg1Out,DataIn,GenSize,ActivateGen,XorReg01,XorReg11,OutSig0); -- ActivateGen is a bit that indicates decryption or not
---------------------------------------------
------ Combinatorial logic for a round ------
---------------------------------------------
datapath: process(IV,Key,DataIn,Reg0Out,Reg1Out,Reg2Out,Reg3Out,Reg4Out,RegOutOut, -- inputs blocks and registers
SboxOut0,SboxOut1,SboxOut2,SboxOut3,SboxOut4,DiffOut0,DiffOut1,DiffOut2,DiffOut3,DiffOut4, -- internal signals
XorReg01,XorReg02,XorReg11,XorReg12,XorReg2,XorReg31,XorReg32,XorReg4,OutSig0,OutSig1, -- internal signals
RoundNr,sel0,sel1,sel2,sel3,sel4,ActivateGen,selout,GenSize) is -- control signals
begin
-- Set correct inputs in registers
if sel0 = "000" then
Reg0In <= DiffOut0;
elsif sel0 = "001" then
Reg0In <= EXTRAIV;
elsif sel0 = "010" then
Reg0In <= XorReg01;
elsif sel0 = "011" then
Reg0In <= XorReg02;
else
Reg0In <= Reg0Out xor ADCONSTANT;
end if;
if sel1 = "00" then
Reg1In <= DiffOut1;
elsif sel1 = "01" then
Reg1In <= Key(127 downto 64);
elsif sel1 = "10" then
Reg1In <= XorReg11;
else
Reg1In <= XorReg12;
end if;
if sel2 = "00" then
Reg2In <= DiffOut2;
elsif sel2 = "01" then
Reg2In <= Key(63 downto 0);
else
Reg2In <= XorReg2;
end if;
if sel3 = "00" then
Reg3In <= DiffOut3;
elsif sel3 = "01" then
Reg3In <= IV(127 downto 64);
elsif sel3 = "10" then
Reg3In <= XorReg31;
else
Reg3In <= XorReg32;
end if;
if sel4 = "00" then
Reg4In <= DiffOut4;
elsif sel4 = "01" then
Reg4In <= IV(63 downto 0);
elsif sel4 = "10" then
Reg4In <= XorReg4;
else
Reg4In <= Reg4Out xor SEPCONSTANT;
end if;
XorReg02 <= Reg0Out xor Key(127 downto 64);
XorReg12 <= Reg1Out xor Key(63 downto 0);
XorReg2 <= Reg2Out xor Key(127 downto 64);
XorReg31 <= Reg3Out xor Key(127 downto 64);
XorReg32 <= Reg3Out xor Key(63 downto 0);
XorReg4 <= Reg4Out xor Key(63 downto 0);
-- Set output
OutSig1(127 downto 64) <= XorReg31;
OutSig1(63 downto 0) <= XorReg4;
if selout = '0' then
RegOutIn <= OutSig0;
else
RegOutIn <= OutSig1;
end if;
DataOut <= RegOutOut;
end process datapath;
---------------------------------------------
------ The registers in the datapath --------
---------------------------------------------
registerdatapath : process(Clk,Reset) is
begin
if(Clk = '1' and Clk'event) then
if Reset = '1' then -- synchronous reset
Reg0Out <= (others => '0');
Reg1Out <= (others => '0');
Reg2Out <= (others => '0');
Reg3Out <= (others => '0');
Reg4Out <= (others => '0');
RegOutOut <= (others => '0');
else
-- update registers with enable
if Reg0En = '1' then
Reg0Out <= Reg0In;
end if;
if Reg1En = '1' then
Reg1Out <= Reg1In;
end if;
if Reg2En = '1' then
Reg2Out <= Reg2In;
end if;
if Reg3En = '1' then
Reg3Out <= Reg3In;
end if;
if Reg4En = '1' then
Reg4Out <= Reg4In;
end if;
if RegOutEn = '1' then
RegOutOut <= RegOutIn;
end if;
end if;
end if;
end process registerdatapath;
end architecture structural;
| gpl-3.0 | 67d14f18e5c319c246da089e9d51e964 | 0.62988 | 3.031981 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/sim/sram16.vhd | 2 | 2,251 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: sram16
-- File: sram16.vhd
-- Author: Jiri Gaisler Gaisler Research
-- Description: Simulation model of generic 16-bit async SRAM
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
library gaisler;
use gaisler.sim.all;
library grlib;
use grlib.stdlib.all;
entity sram16 is
generic (
index : integer := 0; -- Byte lane (0 - 3)
abits: Positive := 10; -- Default 10 address bits (1 Kbyte)
echk : integer := 0; -- Generate EDAC checksum
tacc : integer := 10; -- access time (ns)
fname : string := "ram.dat"); -- File to read from
port (
a : in std_logic_vector(abits-1 downto 0);
d : inout std_logic_vector(15 downto 0);
lb : in std_logic;
ub : in std_logic;
ce : in std_logic;
we : in std_ulogic;
oe : in std_ulogic);
end;
architecture sim of sram16 is
signal cex : std_logic_vector(0 to 1);
begin
cex(0) <= ce or lb; cex(1) <= ce or ub;
sr0 : sram generic map (index+1, abits, tacc, fname)
port map (a, d(7 downto 0), cex(0), we, oe);
sr1 : sram generic map (index, abits, tacc, fname)
port map (a, d(15 downto 8), cex(1), we, oe);
end sim;
-- pragma translate_on
| mit | d5a3a331e386f7e28cadb4ffc9bfed8c | 0.60462 | 3.733002 | false | false | false | false |
michaelfivez/ascon_hardware_implementation | ascon12864_serialized/API_plus_CipherCore/CypherCore.vhd | 1 | 14,257 | -------------------------------------------------------------------------------
--! @project Serialized hardware implementation of Asconv1286
--! @author Michael Fivez
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is an hardware implementation made for my graduation thesis
--! at the KULeuven, in the COSIC department (year 2015-2016)
--! The thesis is titled 'Energy efficient hardware implementations of CAESAR submissions',
--! and can be found on the COSIC website (www.esat.kuleuven.be/cosic/publications)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
entity CipherCore is
generic (
G_NPUB_SIZE : integer := 128; --! Npub size (bits)
G_NSEC_SIZE : integer := 128; --! Nsec size (bits)
G_DBLK_SIZE : integer := 64; --! Data Block size (bits)
G_KEY_SIZE : integer := 128; --! Key size (bits)
G_RDKEY_SIZE : integer := 128; --! Round Key size (bits)
G_TAG_SIZE : integer := 128; --! Tag size (bits)
G_BS_BYTES : integer := 3; --! The number of bits required to hold block size expressed in bytes = log2_ceil(max(G_ABLK_SIZE,G_DBLK_SIZE)/8)
G_CTR_AD_SIZE : integer := 64; --! Maximum size for the counter that keeps track of authenticated data
G_CTR_D_SIZE : integer := 64 --! Maximum size for the counter that keeps track of data
);
port (
clk : in std_logic;
rst : in std_logic;
npub : in std_logic_vector(G_NPUB_SIZE -1 downto 0);
nsec : in std_logic_vector(G_NSEC_SIZE -1 downto 0);
key : in std_logic_vector(G_KEY_SIZE -1 downto 0);
rdkey : in std_logic_vector(G_RDKEY_SIZE -1 downto 0);
bdi : in std_logic_vector(G_DBLK_SIZE -1 downto 0);
exp_tag : in std_logic_vector(G_TAG_SIZE -1 downto 0);
len_a : in std_logic_vector(G_CTR_AD_SIZE -1 downto 0);
len_d : in std_logic_vector(G_CTR_D_SIZE -1 downto 0);
key_ready : in std_logic;
key_updated : out std_logic;
key_needs_update : in std_logic;
rdkey_ready : in std_logic;
rdkey_read : out std_logic;
npub_ready : in std_logic;
npub_read : out std_logic;
nsec_ready : in std_logic;
nsec_read : out std_logic;
bdi_ready : in std_logic;
bdi_proc : in std_logic;
bdi_ad : in std_logic;
bdi_nsec : in std_logic;
bdi_pad : in std_logic;
bdi_decrypt : in std_logic;
bdi_eot : in std_logic;
bdi_eoi : in std_logic;
bdi_read : out std_logic;
bdi_size : in std_logic_vector(G_BS_BYTES -1 downto 0);
bdi_valid_bytes : in std_logic_vector(G_DBLK_SIZE/8 -1 downto 0);
bdi_pad_loc : in std_logic_vector(G_DBLK_SIZE/8 -1 downto 0);
bdi_nodata : in std_logic;
exp_tag_ready : in std_logic;
bdo_ready : in std_logic;
bdo_write : out std_logic;
bdo : out std_logic_vector(G_DBLK_SIZE -1 downto 0);
bdo_size : out std_logic_vector(G_BS_BYTES+1 -1 downto 0);
bdo_nsec : out std_logic;
tag_ready : in std_logic;
tag_write : out std_logic;
tag : out std_logic_vector(G_TAG_SIZE -1 downto 0);
msg_auth_done : out std_logic;
msg_auth_valid : out std_logic
);
end entity CipherCore;
architecture structure of CipherCore is
-- Registers
signal keyreg,npubreg : std_logic_vector(127 downto 0);
-- Control signals AsconCore
signal AsconStart : std_logic;
signal AsconMode : std_logic_vector(3 downto 0);
signal AsconBusy : std_logic;
signal AsconSize : std_logic_vector(2 downto 0);
signal AsconInput : std_logic_vector(63 downto 0);
-- Internal Datapath signals
signal AsconOutput : std_logic_vector(127 downto 0);
begin
-- Morus_core entity
AsconCore : entity work.Ascon_StateUpdate port map(clk,rst,AsconStart,AsconMode,AsconSize,npubreg,keyreg,AsconInput,AsconBusy,AsconOutput);
----------------------------------------
------ DataPath for CipherCore ---------
----------------------------------------
datapath: process(AsconOutput,exp_tag,bdi,AsconInput) is
begin
-- Connect signals to the MorusCore
AsconInput <= bdi;
tag <= AsconOutput;
bdo <= AsconOutput(63 downto 0);
if AsconOutput = exp_tag then
msg_auth_valid <= '1';
else
msg_auth_valid <= '0';
end if;
end process datapath;
----------------------------------------
------ ControlPath for CipherCore ------
----------------------------------------
fsm: process(clk, rst) is
type state_type is (IDLE,INIT_1,INIT_2,PROCESSING,RUN_CIPHER_1,RUN_CIPHER_2,RUN_CIPHER_3,RUN_CIPHER_4,TAG_1,TAG_2);
variable CurrState : state_type := IDLE;
variable firstblock : std_logic;
variable lastblock : std_logic_vector(1 downto 0);
variable afterRunning : std_logic_vector(2 downto 0);
begin
if(clk = '1' and clk'event) then
if rst = '1' then -- synchornous reset
key_updated <= '0';
CurrState := IDLE;
firstblock := '0';
keyreg <= (others => '0');
npubreg <= (others => '0');
AsconMode <= (others => '0'); -- the mode is a register
afterRunning := (others => '0');
else
-- registers above in reset are used
-- Standard values of the control signals are zero
AsconStart <= '0';
bdi_read <= '0';
msg_auth_done <= '0';
bdo_write <= '0';
bdo_size <= "1000";
tag_write <= '0';
npub_read <= '0';
AsconSize <= (others => '0');
FsmLogic: case CurrState is
when IDLE =>
-- if key_needs_update = '1' then -- Key needs updating
-- if key_ready = '1' then
-- key_updated <= '1';
-- keyreg <= key;
-- CurrState := IDLE;
-- else
-- CurrState := IDLE;
-- end if;
if key_needs_update = '1' and key_ready = '1' then -- Key needs updating
key_updated <= '1';
keyreg <= key;
CurrState := IDLE;
elsif bdi_proc = '1' and npub_ready = '1' then -- start of processing
CurrState := INIT_1;
npubreg <= npub;
npub_read <= '1';
AsconMode <= "0010"; -- Mode: initialization
AsconStart <= '1';
else
CurrState := IDLE;
end if;
when INIT_1 =>
if AsconBusy = '1' then
CurrState := INIT_2; -- to INIT_2
else
AsconStart <= '1';
CurrState := INIT_1; -- to INIT_1
end if;
when INIT_2 =>
if AsconBusy = '0' then
CurrState := PROCESSING; -- to PROCESSING
firstblock := '1';
lastblock := "00";
else
CurrState := INIT_2; -- to INIT_2
end if;
-- EVEN SIMPLIFY THIS AFTER YOU SEE IF WORKS
when PROCESSING =>
if lastblock(1) = '1' then -- Generate the Tag
AsconMode <= "0001";
AsconStart <= '1';
CurrState := TAG_1;
elsif bdi_ready = '1' then
if firstblock = '1' and bdi_ad = '0' then -- No associative data (and return in function)
-- SEP_CONST
AsconMode <= "0011";
AsconStart <= '1';
CurrState := PROCESSING;
elsif bdi_ad = '1' then
if bdi_eot = '0' then
-- AD_PROCESS
AsconMode <= "0000";
AsconStart <= '1';
afterRunning := "000";
CurrState := RUN_CIPHER_1;
elsif bdi_eoi = '0' then
if bdi_size = "000" then
-- AD_PROCESS + case2 + SEP_CONST
AsconMode <= "0000";
AsconStart <= '1';
afterRunning := "001";
CurrState := RUN_CIPHER_1;
else
-- AD_PROCESS + SEP_CONST
AsconMode <= "0000";
AsconStart <= '1';
afterRunning := "010";
CurrState := RUN_CIPHER_1;
end if;
else
if bdi_size = "000" then
-- AD_PROCESS + case2 + SEP_CONST + case1
AsconMode <= "0000";
AsconStart <= '1';
afterRunning := "101";
CurrState := RUN_CIPHER_1;
else
-- AD_PROCESS + SEP_CONST + case1
AsconMode <= "0000";
AsconStart <= '1';
afterRunning := "110";
CurrState := RUN_CIPHER_1;
end if;
end if;
else
if bdi_decrypt = '0' then
if bdi_eot = '0' then
-- ENCRYPT
AsconMode <= "0110";
AsconStart <= '1';
afterRunning := "011";
CurrState := RUN_CIPHER_1;
elsif bdi_size = "000" then
-- ENCRYPT + case1
AsconMode <= "0110";
AsconStart <= '1';
afterRunning := "100";
CurrState := RUN_CIPHER_1;
else
-- LAST_BLOCK_ENCRYPT
bdi_read <= '1';
AsconMode <= "0111";
AsconStart <= '1';
afterRunning := "011";
CurrState := RUN_CIPHER_4;
end if;
else
if bdi_eot = '0' then
-- DECRYPT
AsconMode <= "0100";
AsconStart <= '1';
afterRunning := "011";
CurrState := RUN_CIPHER_1;
elsif bdi_size = "000" then
-- DECRYPT + case1
AsconMode <= "0100";
AsconStart <= '1';
afterRunning := "100";
CurrState := RUN_CIPHER_1;
else
-- LAST_BLOCK_DECRYPT
bdi_read <= '1';
AsconMode <= "0101";
AsconStart <= '1';
AsconSize <= bdi_size;
afterRunning := "011";
CurrState := RUN_CIPHER_4;
end if;
end if;
end if;
-- check if tag after (eoi, with special case when no associative data:
-- This is needed, because if no associative data, it will do it's thing and then still the message block is
-- left to be processed
if firstblock = '1' and bdi_ad = '0' then -- lastblock will be set next return in the function
lastblock := "00";
elsif bdi_eoi = '1' and bdi_decrypt = '0' then -- the one after is tag encryption
lastblock := "10";
elsif bdi_eoi = '1' then -- the one after is tag decryption
lastblock := "11";
end if;
-- not firstblock anymore :
firstblock := '0';
end if;
when RUN_CIPHER_1 =>
if AsconBusy = '1' then
CurrState := RUN_CIPHER_2;
bdi_read <= '1';
else
AsconStart <= '1';
CurrState := RUN_CIPHER_1;
end if;
when RUN_CIPHER_3 =>
if AsconBusy = '1' then
CurrState := RUN_CIPHER_2;
else
AsconStart <= '1';
CurrState := RUN_CIPHER_3;
end if;
when RUN_CIPHER_4 =>
if AsconBusy = '1' then
CurrState := RUN_CIPHER_2;
else
CurrState := RUN_CIPHER_4;
end if;
when RUN_CIPHER_2 =>
if AsconBusy = '0' then
-- logic here:
-- a simple variable is used for the cases where after the cipher something special has to be done:
-- activating authregister after associative data = 1
-- resetting of blocknumber after last associative data = 2 (so also do 1's job)
-- giving of output after encryption/decryption = 3 for encryption, 4 for decryption
-- activating checksum after decription of message = 4
-- special giving of output after padded encryption/decryption = 5 and 6 (determines output_sel), also wait with bdi_read
AfterRunLogic: case afterRunning is
when "000" => -- return to IDLE
CurrState := PROCESSING;
when "001" => -- case2 and sep_cont after
AsconMode <= "1001";
AsconStart <= '1';
CurrState := RUN_CIPHER_3;
afterRunning := "010";
when "010" => -- SEPCONSTANT and return to IDLE
AsconMode <= "0011";
AsconStart <= '1';
CurrState := PROCESSING;
when "011" => -- GIVE OUTPUT and return to IDLE
if bdo_ready = '1' then
bdo_write <= '1';
CurrState := PROCESSING;
else
CurrState := RUN_CIPHER_2;
end if;
when "100" => -- GIVE OUTPUT & case1 and return to IDLE
if bdo_ready = '1' then
bdo_write <= '1';
CurrState := PROCESSING;
AsconMode <= "1000";
AsconStart <= '1';
else
CurrState := RUN_CIPHER_2;
end if;
when "101" => -- case2 and case1 and sep_cont after
AsconMode <= "1001";
AsconStart <= '1';
CurrState := RUN_CIPHER_3;
afterRunning := "110";
when "110" => -- case1 and sep_cont after
AsconMode <= "1000";
AsconStart <= '1';
CurrState := RUN_CIPHER_2;
afterRunning := "010";
when others =>
end case AfterRunLogic;
else
CurrState := RUN_CIPHER_2;
end if;
when TAG_1 =>
if AsconBusy = '1' then
CurrState := TAG_2;
else
AsconStart <= '1';
CurrState := TAG_1;
end if;
when TAG_2 =>
if AsconBusy = '0' and lastblock(0) = '0' then -- Generate Tag
if tag_ready = '1' then
tag_write <= '1';
key_updated <= '0';
CurrState := IDLE;
else
CurrState := TAG_2;
end if;
elsif AsconBusy = '0' then -- Compare Tag
if exp_tag_ready = '1' then
msg_auth_done <= '1';
key_updated <= '0';
CurrState := IDLE;
else
CurrState := TAG_2;
end if;
else
CurrState := TAG_2;
end if;
when others =>
end case FsmLogic;
end if;
end if;
end process fsm;
end architecture structure;
| gpl-3.0 | a8df0f6d9bd28a07c30c0013fc26b012 | 0.519604 | 3.390488 | false | false | false | false |
cafe-alpha/wascafe | v13/r07c_de10_20201014_abus4/wasca/synthesis/submodules/Altera_UP_SD_CRC7_Generator.vhd | 7 | 2,548 | -- (C) 2001-2015 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
---------------------------------------------------------------------------------------
-- This generates the necessary 7-CRC for Command and Response
-- Implementation: serial input/parallel output
--
-- When input stream ends, the crcout output is the CRC checksum for the input stream.
--
-- NOTES/REVISIONS:
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Altera_UP_SD_CRC7_Generator is
port
(
i_clock : in std_logic;
i_enable : in std_logic;
i_reset_n : in std_logic;
i_shift : in std_logic;
i_datain : in std_logic;
o_dataout : out std_logic;
o_crcout : out std_logic_vector(6 downto 0)
);
end entity;
architecture rtl of Altera_UP_SD_CRC7_Generator is
-- Local wires
-- REGISTERED
signal shift_register : std_logic_vector(6 downto 0);
begin
process (i_clock, i_reset_n)
begin
if (i_reset_n = '0') then
shift_register <= (OTHERS => '0');
else
if (rising_edge(i_clock)) then
if (i_enable = '1') then
if (i_shift = '0') then
shift_register(0) <= i_datain XOR shift_register(6);
shift_register(1) <= shift_register(0);
shift_register(2) <= shift_register(1);
shift_register(3) <= shift_register(2) XOR i_datain XOR shift_register(6);
shift_register(4) <= shift_register(3);
shift_register(5) <= shift_register(4);
shift_register(6) <= shift_register(5);
else -- shift CRC out (no more calculation now)
shift_register(0) <= '0';
shift_register(6 downto 1) <= shift_register(5 downto 0);
end if;
end if;
end if;
end if;
end process;
o_dataout <= shift_register(6);
o_crcout <= shift_register;
end rtl;
| gpl-2.0 | 513c85ae5272841da1380ccaf6b3a48f | 0.646389 | 3.558659 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/leon3/mmu_cache.vhd | 2 | 4,966 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: cache
-- File: cache.vhd
-- Author: Jiri Gaisler
-- Description: Complete cache sub-system with controllers and rams
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.libiu.all;
use gaisler.libcache.all;
use gaisler.mmuconfig.all;
use gaisler.mmuiface.all;
use gaisler.libmmu.all;
entity mmu_cache is
generic (
hindex : integer := 0;
memtech : integer range 0 to NTECH := 0;
dsu : integer range 0 to 1 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 2 := 0;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 2 := 0;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
cached : integer := 0;
clk2x : integer := 0;
scantest : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ici : in icache_in_type;
ico : out icache_out_type;
dci : in dcache_in_type;
dco : out dcache_out_type;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
crami : out cram_in_type;
cramo : in cram_out_type;
fpuholdn : in std_ulogic;
hclk, sclk : in std_ulogic;
hclken : in std_ulogic
);
end;
architecture rtl of mmu_cache is
signal icol : icache_out_type;
signal dcol : dcache_out_type;
signal mcii : memory_ic_in_type;
signal mcio : memory_ic_out_type;
signal mcdi : memory_dc_in_type;
signal mcdo : memory_dc_out_type;
signal mcmmi : memory_mm_in_type;
signal mcmmo : memory_mm_out_type;
signal mmudci : mmudc_in_type;
signal mmudco : mmudc_out_type;
signal mmuici : mmuic_in_type;
signal mmuico : mmuic_out_type;
signal ahbsi2 : ahb_slv_in_type;
signal ahbi2 : ahb_mst_in_type;
signal ahbo2 : ahb_mst_out_type;
begin
-- instruction cache controller
icache0 : mmu_icache
generic map (irepl=>irepl, isets=>isets, ilinesize=>ilinesize, isetsize=>isetsize, isetlock=>isetlock)
port map ( rst, clk, ici, icol, dci, dcol, mcii, mcio,
crami.icramin, cramo.icramo, fpuholdn, mmudci, mmuici, mmuico);
-- data cache controller
dcache0 : mmu_dcache
generic map (dsu=>dsu, drepl=>drepl, dsets=>dsets, dlinesize=>dlinesize, dsetsize=>dsetsize, dsetlock=>dsetlock, dsnoop=>dsnoop,
itlbnum=>itlbnum, dtlbnum=>dtlbnum, tlb_type=>tlb_type, memtech=>memtech, cached => cached)
port map ( rst, clk, dci, dcol, icol, mcdi, mcdo, ahbsi2,
crami.dcramin, cramo.dcramo, fpuholdn, mmudci, mmudco, sclk);
-- AMBA AHB interface
a0 : mmu_acache
generic map (hindex, ilinesize, cached, clk2x, scantest)
port map (rst, clk, mcii, mcio, mcdi, mcdo, mcmmi, mcmmo, ahbi2, ahbo2, ahbso, hclken);
-- MMU
m0 : mmu
generic map (memtech, itlbnum, dtlbnum, tlb_type, tlb_rep)
port map (rst, clk, mmudci, mmudco, mmuici, mmuico, mcmmo, mcmmi);
ico <= icol;
dco <= dcol;
clk2xgen: if clk2x /= 0 generate
sync0 : clk2xsync generic map (hindex, clk2x)
port map (rst, hclk, clk, ahbi, ahbi2, ahbo2, ahbo, ahbsi, ahbsi2, mcii, mcdi, mcdo, mcmmi.req, mcmmo.grant, hclken);
end generate;
noclk2x : if clk2x = 0 generate
ahbsi2 <= ahbsi;
ahbi2 <= ahbi;
ahbo <= ahbo2;
end generate;
end ;
| mit | d6390f3149853c720c440547044593f4 | 0.617398 | 3.552217 | false | false | false | false |
michaelfivez/ascon_hardware_implementation | ascon12864_serialized/Kernel/Ascon_block_control.vhd | 1 | 9,751 | -------------------------------------------------------------------------------
--! @project Serialized hardware implementation of Asconv1286
--! @author Michael Fivez
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is an hardware implementation made for my graduation thesis
--! at the KULeuven, in the COSIC department (year 2015-2016)
--! The thesis is titled 'Energy efficient hardware implementations of CAESAR submissions',
--! and can be found on the COSIC website (www.esat.kuleuven.be/cosic/publications)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Ascon_StateUpdate_control is
port(
Clk : in std_logic; -- Clock
Reset : in std_logic; -- Reset (synchronous)
-- Control signals
RoundNr : out std_logic_vector(3 downto 0); -- biggest round is 12
sel1,sel2,sel3,sel4 : out std_logic_vector(1 downto 0);
sel0 : out std_logic_vector(2 downto 0);
selout : out std_logic;
SelSbox : out std_logic_vector(1 downto 0);
SelDiff : out std_logic_vector(2 downto 0);
Reg0En,Reg1En,Reg2En,Reg3En,Reg4En,RegOutEn : out std_logic;
SboxEnable : out std_logic;
ActivateGen : out std_logic;
GenSize : out std_logic_vector(2 downto 0);
-- External control signals
Start : in std_logic;
Mode : in std_logic_vector(3 downto 0);
Size : in std_logic_vector(2 downto 0); -- only matters for last block decryption
Busy : out std_logic
);
end entity Ascon_StateUpdate_control;
architecture structural of Ascon_StateUpdate_control is
begin
-----------------------------------------
------ The Finite state machine --------
-----------------------------------------
-- Modes: initialization, associative data, encryption, decryption, tag generation, final encryption, final decryption, seperation constant
-- 0010 0000 0110 0100 0001 0111 0101, 0011
-- case1 1000, case2 1001
fsm: process(Clk, Reset) is
type state_type is (IDLE,LOADNEW,CRYPT,TAG);
variable CurrState : state_type := IDLE;
variable RoundNrVar : std_logic_vector(3 downto 0);
variable Selint : std_logic_vector(3 downto 0);
begin
if Clk'event and Clk = '1' then
-- default values
sel0 <= "000";
sel1 <= "00";
sel2 <= "00";
sel3 <= "00";
sel4 <= "00";
selout <= '0';
SelSbox <= "00";
SelDiff <= "000";
Reg0En <= '0';
Reg1En <= '0';
Reg2En <= '0';
Reg3En <= '0';
Reg4En <= '0';
RegOutEn <= '0';
SboxEnable <= '0';
ActivateGen <= '0';
GenSize <= "000";
Busy <= '0';
if Reset = '1' then -- synchronous reset active high
-- registers used by fsm:
RoundNrVar := "0000";
CurrState := IDLE;
else
FSMlogic : case CurrState is
when IDLE =>
if Start = '1' then
Busy <= '1';
if Mode = "0000" then -- AD mode
RoundNrVar := "0000"; -- so starts at 0 next cycle
Selint := (others => '0');
-- set Sel and Enables signal (Xor with DataIn)
sel0 <= "010";
Reg0En <= '1';
CurrState := CRYPT;
elsif Mode = "0100" then -- Decryption mode
RoundNrVar := "0000"; -- so starts at 0 next cycle
Selint := (others => '0');
-- set Sel and Enables signal (Generate output and xor state)
ActivateGen <= '1';
sel0 <= "010";
Reg0En <= '1';
RegOutEn <= '1';
CurrState := CRYPT;
elsif Mode = "0110" then -- Encryption
RoundNrVar := "0000"; -- so starts at 0 next cycle
Selint := (others => '0');
-- set Sel and Enables signal (Generate output and xor state)
sel0 <= "010";
Reg0En <= '1';
RegOutEn <= '1';
CurrState := CRYPT;
elsif Mode = "0001" then -- Tag mode
RoundNrVar := "0000"; -- so starts at 0 next cycle
Selint := (others => '0');
-- set Sel and Enables signal (XOR middle with key)
sel1 <= "10";
sel2 <= "11";
Reg1En <= '1';
Reg2En <= '1';
CurrState := TAG;
elsif Mode = "0111" then -- Last block encryption
-- set Sel and Enables signal (Generate output and xor state)
sel0 <= "010";
Reg0En <= '1';
RegOutEn <= '1';
CurrState := IDLE;
elsif Mode = "0101" then -- Last block decryption
-- set Sel and Enables signal (Generate output and xor state)
ActivateGen <= '1';
GenSize <= Size;
sel0 <= "010";
Reg0En <= '1';
RegOutEn <= '1';
CurrState := IDLE;
elsif Mode = "0011" then -- Seperation constant
sel4 <= "11";
Reg4En <= '1';
CurrState := IDLE;
elsif Mode = "0010" then -- Initialization mode
RoundNrVar := "0000";
Selint := (others => '0');
-- set Sel and Enables signal (Load in key and IV)
sel0 <= "001";
sel1 <= "01";
sel2 <= "01";
sel3 <= "01";
sel4 <= "01";
Reg0En <= '1';
Reg1En <= '1';
Reg2En <= '1';
Reg3En <= '1';
Reg4En <= '1';
CurrState := LOADNEW;
elsif Mode = "1000" then -- case1
sel0 <= "100";
Reg0En <= '1';
CurrState := IDLE;
else -- case2
sel0 <= "100";
Reg0En <= '1';
RoundNrVar := "0000"; -- so starts at 0 next cycle
Selint := (others => '0');
CurrState := CRYPT;
end if;
else
Busy <= '0';
CurrState := IDLE;
end if;
when LOADNEW =>
if Selint = "0000" and RoundNrVar = "1100" then
sel3 <= "10";
sel4 <= "10";
Reg3En <= '1';
Reg4En <= '1';
Busy <= '0';
CurrState := IDLE;
elsif Selint(3 downto 2) = "00" then -- sbox part
Busy <= '1';
SelSbox <= Selint(1 downto 0);
SboxEnable <= '1';
Selint := std_logic_vector(unsigned(Selint) + 1);
elsif Selint = "0100" then -- linear diffusion layer part 1
Busy <= '1';
SelDiff <= "000";
Reg0En <= '1';
Selint := std_logic_vector(unsigned(Selint) + 1);
elsif Selint = "0101" then -- linear diffusion layer part 2
Busy <= '1';
SelDiff <= "001";
Reg1En <= '1';
Selint := std_logic_vector(unsigned(Selint) + 1);
elsif Selint = "0110" then -- linear diffusion layer part 3
Busy <= '1';
SelDiff <= "010";
Reg2En <= '1';
Selint := std_logic_vector(unsigned(Selint) + 1);
elsif Selint = "0111" then -- linear diffusion layer part 4
Busy <= '1';
SelDiff <= "011";
Reg3En <= '1';
Selint := std_logic_vector(unsigned(Selint) + 1);
elsif Selint = "1000" then -- linear diffusion layer part 5
Busy <= '1';
SelDiff <= "100";
Reg4En <= '1';
Selint := (others => '0');
RoundNrVar := std_logic_vector(unsigned(RoundNrVar) + 1);
end if;
when CRYPT =>
if Selint(3 downto 2) = "00" then -- sbox part
Busy <= '1';
SelSbox <= Selint(1 downto 0);
SboxEnable <= '1';
Selint := std_logic_vector(unsigned(Selint) + 1);
elsif Selint = "0100" then -- linear diffusion layer part 1
Busy <= '1';
SelDiff <= "000";
Reg0En <= '1';
Selint := std_logic_vector(unsigned(Selint) + 1);
elsif Selint = "0101" then -- linear diffusion layer part 2
Busy <= '1';
SelDiff <= "001";
Reg1En <= '1';
Selint := std_logic_vector(unsigned(Selint) + 1);
elsif Selint = "0110" then -- linear diffusion layer part 3
Busy <= '1';
SelDiff <= "010";
Reg2En <= '1';
Selint := std_logic_vector(unsigned(Selint) + 1);
elsif Selint = "0111" then -- linear diffusion layer part 4
Busy <= '1';
SelDiff <= "011";
Reg3En <= '1';
Selint := std_logic_vector(unsigned(Selint) + 1);
elsif Selint = "1000" then -- linear diffusion layer part 5
Busy <= '1';
SelDiff <= "100";
Reg4En <= '1';
Selint := (others => '0');
RoundNrVar := std_logic_vector(unsigned(RoundNrVar) + 1);
if RoundNrVar = "0110" then
CurrState := IDLE;
else
Busy <= '1';
end if;
end if;
when TAG =>
if Selint = "0000" and RoundNrVar = "1100" then
-- set Sel and Enables signal (connect tag to output)
selout <= '1';
RegOutEn <= '1';
CurrState := IDLE;
Busy <= '0';
elsif Selint(3 downto 2) = "00" then -- sbox part
Busy <= '1';
SelSbox <= Selint(1 downto 0);
SboxEnable <= '1';
Selint := std_logic_vector(unsigned(Selint) + 1);
elsif Selint = "0100" then -- linear diffusion layer part 1
Busy <= '1';
SelDiff <= "000";
Reg0En <= '1';
Selint := std_logic_vector(unsigned(Selint) + 1);
elsif Selint = "0101" then -- linear diffusion layer part 2
Busy <= '1';
SelDiff <= "001";
Reg1En <= '1';
Selint := std_logic_vector(unsigned(Selint) + 1);
elsif Selint = "0110" then -- linear diffusion layer part 3
Busy <= '1';
SelDiff <= "010";
Reg2En <= '1';
Selint := std_logic_vector(unsigned(Selint) + 1);
elsif Selint = "0111" then -- linear diffusion layer part 4
Busy <= '1';
SelDiff <= "011";
Reg3En <= '1';
Selint := std_logic_vector(unsigned(Selint) + 1);
elsif Selint = "1000" then -- linear diffusion layer part 5
Busy <= '1';
SelDiff <= "100";
Reg4En <= '1';
Selint := (others => '0');
RoundNrVar := std_logic_vector(unsigned(RoundNrVar) + 1);
end if;
end case FSMlogic;
RoundNr <= RoundNrVar;
end if;
end if;
end process fsm;
end architecture structural;
| gpl-3.0 | 7cafcfdc65503f101605b8c2e14271f7 | 0.549687 | 3.143456 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/leon3/icache.vhd | 2 | 22,124 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: icache
-- File: icache.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Modified: Edvin Catovic - Gaisler Research
-- Description: This unit implements the instruction cache controller.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.libiu.all;
use gaisler.libcache.all;
entity icache is
generic (
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 2 := 0;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
lram : integer range 0 to 1 := 0;
lramsize : integer range 1 to 512 := 1;
lramstart : integer range 0 to 255 := 16#8e#);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ici : in icache_in_type;
ico : out icache_out_type;
dci : in dcache_in_type;
dco : in dcache_out_type;
mcii : out memory_ic_in_type;
mcio : in memory_ic_out_type;
icrami : out icram_in_type;
icramo : in icram_out_type;
fpuholdn : in std_ulogic
);
end;
architecture rtl of icache is
constant ILINE_BITS : integer := log2(ilinesize);
constant IOFFSET_BITS : integer := 8 +log2(isetsize) - ILINE_BITS;
constant TAG_LOW : integer := IOFFSET_BITS + ILINE_BITS + 2;
constant OFFSET_HIGH : integer := TAG_LOW - 1;
constant OFFSET_LOW : integer := ILINE_BITS + 2;
constant LINE_HIGH : integer := OFFSET_LOW - 1;
constant LINE_LOW : integer := 2;
constant LRR_BIT : integer := TAG_HIGH + 1;
constant lline : std_logic_vector((ILINE_BITS -1) downto 0) := (others=>'1');
constant fline : std_logic_vector((ILINE_BITS -1) downto 0) := (others=>'0');
constant SETBITS : integer := log2x(ISETS);
constant ILRUBITS : integer := lru_table(ISETS);
constant LRAM_START : std_logic_vector(7 downto 0) := conv_std_logic_vector(lramstart, 8);
constant LRAM_BITS : integer := log2(lramsize) + 10;
constant LRAMCS_EN : boolean := false;
subtype lru_type is std_logic_vector(ILRUBITS-1 downto 0);
type lru_array is array (0 to 2**IOFFSET_BITS-1) of lru_type; -- lru registers
type rdatatype is (itag, idata, memory); -- sources during cache read
type lru_table_vector_type is array(0 to 3) of std_logic_vector(4 downto 0);
type lru_table_type is array (0 to 2**IOFFSET_BITS-1) of lru_table_vector_type;
subtype lock_type is std_logic_vector(0 to ISETS-1);
type par_type is array (0 to ISETS-1) of std_logic_vector(1 downto 0);
function lru_set (lru : lru_type; lock : lock_type) return std_logic_vector is
variable xlru : std_logic_vector(4 downto 0);
variable set : std_logic_vector(SETBITS-1 downto 0);
variable xset : std_logic_vector(1 downto 0);
variable unlocked : integer range 0 to ISETS-1;
begin
set := (others => '0'); xlru := (others => '0'); xset := (others => '0');
xlru(ILRUBITS-1 downto 0) := lru;
if isetlock = 1 then
unlocked := ISETS-1;
for i in ISETS-1 downto 0 loop
if lock(i) = '0' then unlocked := i; end if;
end loop;
end if;
case ISETS is
when 2 =>
if isetlock = 1 then
if lock(0) = '1' then xset(0) := '1'; else xset(0) := xlru(0); end if;
else xset(0) := xlru(0); end if;
when 3 =>
if isetlock = 1 then
xset := conv_std_logic_vector(lru3_repl_table(conv_integer(xlru)) (unlocked), 2);
else
xset := conv_std_logic_vector(lru3_repl_table(conv_integer(xlru)) (0), 2);
end if;
when 4 =>
if isetlock = 1 then
xset := conv_std_logic_vector(lru4_repl_table(conv_integer(xlru)) (unlocked), 2);
else
xset := conv_std_logic_vector(lru4_repl_table(conv_integer(xlru)) (0), 2);
end if;
when others =>
end case;
set := xset(SETBITS-1 downto 0);
return(set);
end;
function lru_calc (lru : lru_type; set : integer) return lru_type is
variable new_lru : lru_type;
variable xnew_lru: std_logic_vector(4 downto 0);
variable xlru : std_logic_vector(4 downto 0);
begin
new_lru := (others => '0'); xnew_lru := (others => '0');
xlru := (others => '0'); xlru(ILRUBITS-1 downto 0) := lru;
case ISETS is
when 2 =>
if set = 0 then xnew_lru(0) := '1'; else xnew_lru(0) := '0'; end if;
when 3 =>
xnew_lru(2 downto 0) := lru_3set_table(conv_integer(lru))(set);
when 4 =>
xnew_lru(4 downto 0) := lru_4set_table(conv_integer(lru))(set);
when others =>
end case;
new_lru := xnew_lru(ILRUBITS-1 downto 0);
return(new_lru);
end;
type icache_control_type is record -- all registers
req, burst, holdn : std_ulogic;
overrun : std_ulogic; --
underrun : std_ulogic; --
istate : std_logic_vector(1 downto 0); -- FSM vector
waddress : std_logic_vector(31 downto 2); -- write address buffer
valid : std_logic_vector(ilinesize-1 downto 0); -- valid bits
hit : std_ulogic;
su : std_ulogic;
flush : std_ulogic; -- flush in progress
flush2 : std_ulogic; -- flush in progress
flush3 : std_ulogic; -- flush in progress
faddr : std_logic_vector(IOFFSET_BITS - 1 downto 0); -- flush address
diagrdy : std_ulogic;
rndcnt : std_logic_vector(log2x(ISETS)-1 downto 0); -- replace counter
lrr : std_ulogic;
setrepl : std_logic_vector(log2x(ISETS)-1 downto 0); -- set to replace
diagset : std_logic_vector(log2x(ISETS)-1 downto 0);
lock : std_ulogic;
end record;
type lru_reg_type is record
write : std_ulogic;
waddr : std_logic_vector(IOFFSET_BITS-1 downto 0);
set : std_logic_vector(SETBITS-1 downto 0); --integer range 0 to ISETS-1;
lru : lru_array;
end record;
signal r, c : icache_control_type; -- r is registers, c is combinational
signal rl, cl : lru_reg_type; -- rl is registers, cl is combinational
constant icfg : std_logic_vector(31 downto 0) :=
cache_cfg(irepl, isets, ilinesize, isetsize, isetlock, 0, lram, lramsize, lramstart, 0);
begin
ictrl : process(rst, r, rl, mcio, ici, dci, dco, icramo, fpuholdn)
variable rdatasel : rdatatype;
variable twrite, diagen, dwrite : std_ulogic;
variable taddr : std_logic_vector(TAG_HIGH downto LINE_LOW); -- tag address
variable wtag : std_logic_vector(TAG_HIGH downto TAG_LOW); -- write tag value
variable ddatain : std_logic_vector(31 downto 0);
variable rdata : cdatatype;
variable diagdata : std_logic_vector(31 downto 0);
variable vmaskraw, vmask : std_logic_vector((ilinesize -1) downto 0);
variable xaddr_inc : std_logic_vector((ILINE_BITS -1) downto 0);
variable lastline, nlastline, nnlastline : std_ulogic;
variable enable : std_ulogic;
variable error : std_ulogic;
variable whit, hit, valid : std_ulogic;
variable cacheon : std_ulogic;
variable v : icache_control_type;
variable branch : std_ulogic;
variable eholdn : std_ulogic;
variable mds, write : std_ulogic;
variable memaddr : std_logic_vector(31 downto 2);
variable set : integer range 0 to MAXSETS-1;
variable setrepl : std_logic_vector(log2x(ISETS)-1 downto 0); -- set to replace
variable ctwrite, cdwrite, validv : std_logic_vector(0 to MAXSETS-1);
variable wlrr : std_ulogic;
variable vl : lru_reg_type;
variable vdiagset, rdiagset : integer range 0 to ISETS-1;
variable lock : std_logic_vector(0 to ISETS-1);
variable wlock, sidle : std_ulogic;
variable tag : cdatatype; --std_logic_vector(31 downto 0);
variable lramacc, ilramwr, lramcs : std_ulogic;
begin
-- init local variables
v := r; vl := rl; vl.write := '0'; vl.set := r.setrepl;
vl.waddr := r.waddress(OFFSET_HIGH downto OFFSET_LOW);
mds := '1'; dwrite := '0'; twrite := '0'; diagen := '0'; error := '0';
write := mcio.ready; v.diagrdy := '0'; v.holdn := '1';
v.flush3 := r.flush2; sidle := '0';
if icen /= 0 then
cacheon := dco.icdiag.cctrl.ics(0) and not r.flush;
else cacheon := '0'; end if;
enable := '1'; branch := '0';
eholdn := dco.hold and fpuholdn;
rdatasel := idata; -- read data from cache as default
ddatain := mcio.data; -- load full word from memory
wtag(TAG_HIGH downto TAG_LOW) := r.waddress(TAG_HIGH downto TAG_LOW);
wlrr := r.lrr; wlock := r.lock;
set := 0; ctwrite := (others => '0'); cdwrite := (others => '0');
vdiagset := 0; rdiagset := 0; lock := (others => '0'); ilramwr := '0';
lramacc := '0'; lramcs := '0';
-- random replacement counter
if ISETS > 1 then
if conv_integer(r.rndcnt) = (ISETS - 1) then v.rndcnt := (others => '0');
else v.rndcnt := r.rndcnt + 1; end if;
end if;
-- generate lock bits
if isetlock = 1 then
for i in 0 to ISETS-1 loop lock(i) := icramo.tag(i)(CTAG_LOCKPOS); end loop;
end if;
--local ram access
if (lram = 1) and (ici.fpc(31 downto 24) = LRAM_START) then lramacc := '1'; end if;
-- generate cache hit and valid bits
hit := '0';
for i in ISETS-1 downto 0 loop
if (icramo.tag(i)(TAG_HIGH downto TAG_LOW) = ici.fpc(TAG_HIGH downto TAG_LOW))
then hit := not r.flush; set := i; end if;
validv(i) := genmux(ici.fpc(LINE_HIGH downto LINE_LOW),
icramo.tag(i)(ilinesize -1 downto 0));
end loop;
if (lramacc = '1') and (ISETS > 1) then set := 1; end if;
if ici.fpc(LINE_HIGH downto LINE_LOW) = lline then lastline := '1';
else lastline := '0'; end if;
if r.waddress(LINE_HIGH downto LINE_LOW) = lline((ILINE_BITS -1) downto 0) then
nlastline := '1';
else nlastline := '0'; end if;
if r.waddress(LINE_HIGH downto LINE_LOW+1) = lline((ILINE_BITS -1) downto 1) then
nnlastline := '1';
else nnlastline := '0'; end if;
valid := validv(set);
xaddr_inc := r.waddress(LINE_HIGH downto LINE_LOW) + 1;
if mcio.ready = '1' then
v.waddress(LINE_HIGH downto LINE_LOW) := xaddr_inc;
end if;
taddr := ici.rpc(TAG_HIGH downto LINE_LOW);
-- main state machine
case r.istate is
when "00" => -- main state and cache hit
v.valid := icramo.tag(set)(ilinesize-1 downto 0);
v.hit := hit; v.su := ici.su; sidle := '1';
-- if (ici.inull or eholdn) = '0' then
if eholdn = '0' then
taddr := ici.fpc(TAG_HIGH downto LINE_LOW);
else taddr := ici.rpc(TAG_HIGH downto LINE_LOW); end if;
v.burst := dco.icdiag.cctrl.burst and not lastline;
if (eholdn and not (ici.inull or lramacc)) = '1' then
if not (cacheon and hit and valid) = '1' then
v.istate := "01"; v.req := '1';
v.holdn := '0'; v.overrun := '1';
else
if (ISETS > 1) and (irepl = lru) then vl.write := '1'; end if;
end if;
v.waddress := ici.fpc(31 downto 2);
end if;
if dco.icdiag.enable = '1' then
diagen := '1';
end if;
ddatain := dci.maddress;
if (ISETS > 1) then
if (irepl = lru) then
vl.set := conv_std_logic_vector(set, SETBITS);
vl.waddr := ici.fpc(OFFSET_HIGH downto OFFSET_LOW);
end if;
v.setrepl := conv_std_logic_vector(set, SETBITS);
if (((not hit) and (not r.flush)) = '1') then
case irepl is
when rnd =>
if isetlock = 1 then
if lock(conv_integer(r.rndcnt)) = '0' then v.setrepl := r.rndcnt;
else
v.setrepl := conv_std_logic_vector(ISETS-1, SETBITS);
for i in ISETS-1 downto 0 loop
if (lock(i) = '0') and (i>conv_integer(r.rndcnt)) then
v.setrepl := conv_std_logic_vector(i, SETBITS);
end if;
end loop;
end if;
else
v.setrepl := r.rndcnt;
end if;
when lru =>
v.setrepl := lru_set(rl.lru(conv_integer(ici.fpc(OFFSET_HIGH downto OFFSET_LOW))), lock(0 to ISETS-1));
when lrr =>
v.setrepl := (others => '0');
if isetlock = 1 then
if lock(0) = '1' then v.setrepl(0) := '1';
else
v.setrepl(0) := icramo.tag(0)(CTAG_LRRPOS) xor icramo.tag(1)(CTAG_LRRPOS);
end if;
else
v.setrepl(0) := icramo.tag(0)(CTAG_LRRPOS) xor icramo.tag(1)(CTAG_LRRPOS);
end if;
if v.setrepl(0) = '0' then v.lrr := not icramo.tag(0)(CTAG_LRRPOS);
else v.lrr := icramo.tag(0)(CTAG_LRRPOS); end if;
end case;
end if;
if (isetlock = 1) then
if (hit and lock(set)) = '1' then v.lock := '1';
else v.lock := '0'; end if;
end if;
end if;
when "01" => -- streaming: update cache and send data to IU
rdatasel := memory;
taddr(TAG_HIGH downto LINE_LOW) := r.waddress(TAG_HIGH downto LINE_LOW);
branch := (ici.fbranch and r.overrun) or
(ici.rbranch and (not r.overrun));
v.underrun := r.underrun or
(write and ((ici.inull or not eholdn) and (mcio.ready and not (r.overrun and not r.underrun))));
v.overrun := (r.overrun or (eholdn and not ici.inull)) and
not (write or r.underrun);
if mcio.ready = '1' then
-- mds := not (v.overrun and not r.underrun);
mds := not (r.overrun and not r.underrun);
-- v.req := r.burst;
v.burst := v.req and not (nnlastline and mcio.ready);
end if;
if mcio.grant = '1' then
v.req := dco.icdiag.cctrl.burst and r.burst and
(not (nnlastline and mcio.ready)) and (dco.icdiag.cctrl.burst or (not branch)) and
not (v.underrun and not cacheon);
v.burst := v.req and not (nnlastline and mcio.ready);
end if;
v.underrun := (v.underrun or branch) and not v.overrun;
v.holdn := not (v.overrun or v.underrun);
if (mcio.ready = '1') and (r.req = '0') then --(v.burst = '0') then
v.underrun := '0'; v.overrun := '0';
if (dco.icdiag.cctrl.ics(0) and not r.flush2) = '1' then
v.istate := "10"; v.holdn := '0';
else
v.istate := "00"; v.flush := r.flush2; v.holdn := '1';
if r.overrun = '1' then taddr := ici.fpc(TAG_HIGH downto LINE_LOW);
else taddr := ici.rpc(TAG_HIGH downto LINE_LOW); end if;
end if;
end if;
when "10" => -- return to main
taddr := ici.fpc(TAG_HIGH downto LINE_LOW);
v.istate := "00"; v.flush := r.flush2;
when others => v.istate := "00";
end case;
if mcio.retry = '1' then v.req := '1'; end if;
if lram = 1 then
if LRAMCS_EN then
if taddr(31 downto 24) = LRAM_START then lramcs := '1'; else lramcs := '0'; end if;
else
lramcs := '1';
end if;
end if;
-- Generate new valid bits write strobe
vmaskraw := decode(r.waddress(LINE_HIGH downto LINE_LOW));
twrite := write;
if cacheon = '0' then
twrite := '0'; vmask := (others => '0');
elsif (dco.icdiag.cctrl.ics = "01") then
twrite := twrite and r.hit;
vmask := icramo.tag(set)(ilinesize-1 downto 0) or vmaskraw;
else
if r.hit = '1' then vmask := r.valid or vmaskraw;
else vmask := vmaskraw; end if;
end if;
if (mcio.mexc or not mcio.cache) = '1' then
twrite := '0'; dwrite := '0';
else dwrite := twrite; end if;
if twrite = '1' then
v.valid := vmask; v.hit := '1';
if (ISETS > 1) and (irepl = lru) then vl.write := '1'; end if;
end if;
if (ISETS > 1) and (irepl = lru) and (rl.write = '1') then
vl.lru(conv_integer(rl.waddr)) :=
lru_calc(rl.lru(conv_integer(rl.waddr)), conv_integer(rl.set));
end if;
-- cache write signals
if ISETS > 1 then setrepl := r.setrepl; else setrepl := (others => '0'); end if;
if twrite = '1' then ctwrite(conv_integer(setrepl)) := '1'; end if;
if dwrite = '1' then cdwrite(conv_integer(setrepl)) := '1'; end if;
-- diagnostic cache access
if diagen = '1' then
if (ISETS /= 1) then
if (dco.icdiag.ilramen = '1') and (lram = 1) then
v.diagset := conv_std_logic_vector(1, SETBITS);
else
v.diagset := dco.icdiag.addr(SETBITS -1 + TAG_LOW downto TAG_LOW);
end if;
end if;
end if;
case ISETS is
when 1 =>
vdiagset := 0; rdiagset := 0;
when 3 =>
if conv_integer(v.diagset) < 3 then vdiagset := conv_integer(v.diagset); end if;
if conv_integer(r.diagset) < 3 then rdiagset := conv_integer(r.diagset); end if;
when others =>
vdiagset := conv_integer(v.diagset);
rdiagset := conv_integer(r.diagset);
end case;
diagdata := icramo.data(rdiagset);
if diagen = '1' then -- diagnostic or local ram access
taddr(TAG_HIGH downto LINE_LOW) := dco.icdiag.addr(TAG_HIGH downto LINE_LOW);
wtag(TAG_HIGH downto TAG_LOW) := dci.maddress(TAG_HIGH downto TAG_LOW);
wlrr := dci.maddress(CTAG_LRRPOS);
wlock := dci.maddress(CTAG_LOCKPOS);
if (dco.icdiag.ilramen = '1') and (lram = 1) then
ilramwr := not dco.icdiag.read;
elsif dco.icdiag.tag = '1' then
twrite := not dco.icdiag.read; dwrite := '0';
ctwrite := (others => '0'); cdwrite := (others => '0');
ctwrite(vdiagset) := not dco.icdiag.read;
diagdata := icramo.tag(rdiagset);
else
dwrite := not dco.icdiag.read; twrite := '0';
cdwrite := (others => '0'); cdwrite(vdiagset) := not dco.icdiag.read;
ctwrite := (others => '0');
end if;
vmask := dci.maddress(ilinesize -1 downto 0);
v.diagrdy := '1';
end if;
-- select data to return on read access
rdata := icramo.data;
case rdatasel is
when memory => rdata(0) := mcio.data; set := 0;
when others =>
end case;
-- cache flush
if ((ici.flush or dco.icdiag.flush) = '1') and (icen /= 0) then
v.flush := '1'; v.flush2 := '1'; v.faddr := (others => '0');
end if;
if (r.flush2 = '1') and (icen /= 0) then
twrite := '1'; ctwrite := (others => '1'); vmask := (others => '0');
v.faddr := r.faddr +1; taddr(OFFSET_HIGH downto OFFSET_LOW) := r.faddr;
wlrr := '0'; wlock := '0'; wtag := (others => '0'); v.lrr := '0';
if (r.faddr(IOFFSET_BITS -1) and not v.faddr(IOFFSET_BITS -1)) = '1' then
v.flush2 := '0';
end if;
end if;
-- reset
if rst = '0' then
v.istate := "00"; v.req := '0'; v.burst := '0'; v.holdn := '1';
v.flush := '0'; v.flush2 := '0'; v.overrun := '0'; v.underrun := '0';
v.rndcnt := (others => '0'); v.lrr := '0'; v.setrepl := (others => '0');
v.diagset := (others => '0'); v.lock := '0'; v.flush3 := '1';
v.waddress := ici.fpc(31 downto 2); v.lrr := '0';
end if;
if r.flush3 = '1' then
vl.lru := (others => (others => '0'));
end if;
-- Drive signals
c <= v; -- register inputs
cl <= vl; -- lru register inputs
-- tag ram inputs
enable := enable and not dco.icdiag.scanen;
for i in 0 to ISETS-1 loop
tag(i) := (others => '0');
tag(i)(ilinesize-1 downto 0) := vmask;
tag(i)(TAG_HIGH downto TAG_LOW) := wtag;
tag(i)(CTAG_LRRPOS) := wlrr;
tag(i)(CTAG_LOCKPOS) := wlock;
end loop;
icrami.tag <= tag;
icrami.tenable <= enable;
icrami.twrite <= ctwrite;
icrami.flush <= r.flush2;
icrami.dpar <= (others => '0');
icrami.tpar <= (others => (others => '0'));
icrami.ctx <= (others => '0');
-- data ram inputs
icrami.denable <= enable;
icrami.address <= taddr(19+LINE_LOW downto LINE_LOW);
icrami.data <= ddatain;
icrami.dwrite <= cdwrite;
-- local ram inputs
icrami.ldramin.enable <= (dco.icdiag.ilramen or lramcs or lramacc) and not dco.icdiag.scanen;
icrami.ldramin.read <= dco.icdiag.ilramen or lramacc;
icrami.ldramin.write <= ilramwr;
-- memory controller inputs
mcii.address(31 downto 2) <= r.waddress(31 downto 2);
mcii.address(1 downto 0) <= "00";
mcii.su <= r.su;
mcii.burst <= r.burst;
mcii.req <= r.req;
mcii.flush <= r.flush;
-- IU data cache inputs
ico.data <= rdata;
ico.mexc <= mcio.mexc or error;
ico.hold <= r.holdn;
ico.mds <= mds;
ico.flush <= r.flush;
ico.diagdata <= diagdata;
ico.diagrdy <= r.diagrdy;
ico.set <= conv_std_logic_vector(set, 2);
ico.cfg <= icfg;
ico.idle <= sidle;
end process;
-- Local registers
regs1 : process(clk)
begin if rising_edge(clk) then r <= c; end if; end process;
regs2 : if (ISETS > 1) and (irepl = lru) generate
regs2 : process(clk)
begin if rising_edge(clk) then rl <= cl; end if; end process;
end generate;
nolru : if (ISETS = 1) or (irepl /= lru) generate
rl.write <= '0'; rl.waddr <= (others => '0');
rl.set <= (others => '0'); rl.lru <= (others => (others => '0'));
end generate;
-- pragma translate_off
chk : process
begin
assert not ((ISETS > 2) and (irepl = lrr)) report
"Wrong instruction cache configuration detected: LRR replacement requires 2 sets"
severity failure;
wait;
end process;
-- pragma translate_on
end ;
| mit | 37f34615d9f194a6289063b697e270b3 | 0.585202 | 3.33645 | false | false | false | false |
cafe-alpha/wascafe | v13/stm32_bup_test/r07c_de10_20200912/wasca_toplevel.vhd | 1 | 16,039 | -- wasca.vhd
-- Generated using ACDS version 14.1 186 at 2015.05.28.08:37:08
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity wasca_toplevel is
port (
clk_clk : in std_logic := '0'; -- Saturn clock (22.579 MHz)
external_sdram_controller_wire_addr : out std_logic_vector(12 downto 0); -- external_sdram_controller_wire.addr
external_sdram_controller_wire_ba : out std_logic_vector(1 downto 0); -- .ba
external_sdram_controller_wire_cas_n : out std_logic; -- .cas_n
external_sdram_controller_wire_cke : out std_logic; -- .cke
external_sdram_controller_wire_cs_n : out std_logic; -- .cs_n
external_sdram_controller_wire_dq : inout std_logic_vector(15 downto 0) := (others => '0'); -- .dq
external_sdram_controller_wire_dqm : out std_logic_vector(1 downto 0); -- .dqm
external_sdram_controller_wire_ras_n : out std_logic; -- .ras_n
external_sdram_controller_wire_we_n : out std_logic; -- .we_n
external_sdram_clk_pin : out std_logic; -- .clk
reset_reset_n : in std_logic := '0'; -- Saturn reset, power on.
abus_slave_0_abus_address : in std_logic_vector(24 downto 16) := (others => '0'); -- abus_slave_0_abus.address
abus_slave_0_abus_addressdata : inout std_logic_vector(15 downto 0) := (others => '0'); -- .data
abus_slave_0_abus_chipselect : in std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
abus_slave_0_abus_read : in std_logic := '0'; -- .read
abus_slave_0_abus_write : in std_logic_vector(1 downto 0) := (others => '0'); -- .write
abus_slave_0_abus_waitrequest : out std_logic; -- .waitrequest
abus_slave_0_abus_interrupt : out std_logic := '0'; -- .interrupt
abus_slave_0_abus_disableout : out std_logic := '0'; -- .muxing
abus_slave_0_abus_muxing : out std_logic_vector(1 downto 0) := (others => '0'); -- .muxing
abus_slave_0_abus_direction : out std_logic := '0'; -- .direction
--spi_sd_card_MISO : in std_logic := '0'; -- MISO
--spi_sd_card_MOSI : out std_logic; -- MOSI
--spi_sd_card_SCLK : out std_logic; -- SCLK
--spi_sd_card_SS_n : out std_logic; -- SS_n
uart_0_external_connection_txd : out std_logic := '0'; --
uart_0_external_connection_rxd : in std_logic := 'X'; --
hex0_conn_export : out std_logic_vector(6 downto 0);
hex1_conn_export : out std_logic_vector(6 downto 0);
hex2_conn_export : out std_logic_vector(6 downto 0);
hex3_conn_export : out std_logic_vector(6 downto 0);
hex4_conn_export : out std_logic_vector(6 downto 0);
hex5_conn_export : out std_logic_vector(6 downto 0);
hexdot_conn_export : out std_logic_vector(5 downto 0);
leds_conn_export : out std_logic_vector(3 downto 0); -- leds_conn_export[0]: ledr1, leds_conn_export[1]: ledg1, leds_conn_export[2]: ledo1, leds_conn_export[3]: ledo2
extra_leds_conn_export : out std_logic_vector(4 downto 0); -- Extra LEDs for DE10-lite only, mapped to their own control register
switches_conn_export : in std_logic_vector(7 downto 0); -- switches_conn_export[0]: sw1, switches_conn_export[1]: sw2, switches_conn_export[2]: unused clock (SCSPCLK from SIM, or EXT from same board)
spi_sync_conn_export : in std_logic; -- SPI synchronization
spi_stm32_MOSI : out std_logic := '0'; -- MOSI
spi_stm32_MISO : in std_logic; -- MISO
spi_stm32_SCLK : out std_logic := '0'; -- SCLK
spi_stm32_SS_n : out std_logic := '0' -- SS_n
--audio_out_BCLK : in std_logic := '0'; -- BCLK
--audio_out_DACDAT : out std_logic; -- DACDAT
--audio_out_DACLRCK : in std_logic := '0'; -- DACLRCK
--audio_SSEL : out std_logic := '0'
);
end entity wasca_toplevel;
architecture rtl of wasca_toplevel is
component wasca is
port (
sdram_clkout_clk : out std_logic; -- clk
altpll_0_areset_conduit_export : in std_logic := '0'; -- altpll_0_areset_conduit.export
altpll_0_locked_conduit_export : out std_logic; -- altpll_0_locked_conduit.export
altpll_0_phasedone_conduit_export : out std_logic; -- altpll_0_phasedone_conduit.export
clk_clk : in std_logic := '0'; -- clk.clk
external_sdram_controller_wire_addr : out std_logic_vector(12 downto 0); -- external_sdram_controller_wire.addr
external_sdram_controller_wire_ba : out std_logic_vector( 1 downto 0); -- .ba
external_sdram_controller_wire_cas_n : out std_logic; -- .cas_n
external_sdram_controller_wire_cke : out std_logic; -- .cke
external_sdram_controller_wire_cs_n : out std_logic; -- .cs_n
external_sdram_controller_wire_dq : inout std_logic_vector(15 downto 0) := (others => '0'); -- .dq
external_sdram_controller_wire_dqm : out std_logic_vector( 1 downto 0); -- .dqm
external_sdram_controller_wire_ras_n : out std_logic; -- .ras_n
external_sdram_controller_wire_we_n : out std_logic; -- .we_n
abus_slave_0_abus_address : in std_logic_vector( 8 downto 0) := (others => '0'); -- abus_slave_0_abus.address
abus_slave_0_abus_chipselect : in std_logic_vector( 2 downto 0) := (others => '0'); -- .chipselect
abus_slave_0_abus_read : in std_logic := '0'; -- .read
abus_slave_0_abus_write : in std_logic_vector( 1 downto 0) := (others => '0'); -- .write
abus_slave_0_abus_waitrequest : out std_logic; -- .waitrequest
abus_slave_0_abus_interrupt : out std_logic := '0'; -- .interrupt
abus_slave_0_abus_addressdata : inout std_logic_vector(15 downto 0) := (others => '0'); -- .writedata
abus_slave_0_abus_direction : out std_logic := '0';
abus_slave_0_abus_muxing : out std_logic_vector( 1 downto 0) := (others => '0');
abus_slave_0_abus_disableout : out std_logic := '0' ; -- .muxing
abus_slave_0_conduit_saturn_reset_saturn_reset : in std_logic := '0'; -- saturn_reset
--spi_sd_card_MISO : in std_logic := '0'; -- MISO
--spi_sd_card_MOSI : out std_logic; -- MOSI
--spi_sd_card_SCLK : out std_logic; -- SCLK
--spi_sd_card_SS_n : out std_logic; -- SS_n
uart_0_external_connection_rxd : in std_logic := '0'; -- rxd
uart_0_external_connection_txd : out std_logic; -- txd
hex0_conn_export : out std_logic_vector(6 downto 0);
hex1_conn_export : out std_logic_vector(6 downto 0);
hex2_conn_export : out std_logic_vector(6 downto 0);
hex3_conn_export : out std_logic_vector(6 downto 0);
hex4_conn_export : out std_logic_vector(6 downto 0);
hex5_conn_export : out std_logic_vector(6 downto 0);
hexdot_conn_export : out std_logic_vector(5 downto 0);
leds_conn_export : out std_logic_vector(3 downto 0);
extra_leds_conn_export : out std_logic_vector(4 downto 0);
switches_conn_export : in std_logic_vector(7 downto 0);
spi_sync_conn_export : in std_logic; -- SPI synchronization
spi_stm32_MISO : in std_logic := '0'; -- MISO
spi_stm32_MOSI : out std_logic := '0'; -- MOSI
spi_stm32_SCLK : out std_logic := '0'; -- SCLK
spi_stm32_SS_n : out std_logic := '0' -- SS_n
--audio_out_BCLK : in std_logic := '0'; -- BCLK
--audio_out_DACDAT : out std_logic; -- DACDAT
--audio_out_DACLRCK : in std_logic := '0' -- DACLRCK
);
end component;
--signal altpll_0_areset_conduit_export : std_logic := '0';
signal altpll_0_locked_conduit_export : std_logic := '0';
--signal altpll_0_phasedone_conduit_export : std_logic := '0';
--signal abus_slave_0_abus_address_demuxed : std_logic_vector(25 downto 0) := (others => '0');
--signal abus_slave_0_abus_data_demuxed : std_logic_vector(15 downto 0) := (others => '0');
begin
--abus_slave_0_abus_muxing (0) <= not abus_slave_0_abus_muxing(1);
my_little_wasca : component wasca
port map (
clk_clk => clk_clk,
external_sdram_controller_wire_addr => external_sdram_controller_wire_addr,
external_sdram_controller_wire_ba => external_sdram_controller_wire_ba,
external_sdram_controller_wire_cas_n => external_sdram_controller_wire_cas_n,
external_sdram_controller_wire_cke => external_sdram_controller_wire_cke,
external_sdram_controller_wire_cs_n => external_sdram_controller_wire_cs_n,
external_sdram_controller_wire_dq => external_sdram_controller_wire_dq,
external_sdram_controller_wire_dqm => external_sdram_controller_wire_dqm,
external_sdram_controller_wire_ras_n => external_sdram_controller_wire_ras_n,
external_sdram_controller_wire_we_n => external_sdram_controller_wire_we_n,
abus_slave_0_abus_address => abus_slave_0_abus_address,
--abus_slave_0_abus_chipselect => "1"&abus_slave_0_abus_chipselect(1 downto 0),--work only with CS1 and CS0 for now
abus_slave_0_abus_chipselect => abus_slave_0_abus_chipselect,
abus_slave_0_abus_read => abus_slave_0_abus_read,
abus_slave_0_abus_write => abus_slave_0_abus_write,
abus_slave_0_abus_waitrequest => abus_slave_0_abus_waitrequest,
abus_slave_0_abus_interrupt => abus_slave_0_abus_interrupt,
abus_slave_0_abus_addressdata => abus_slave_0_abus_addressdata,
abus_slave_0_abus_direction => abus_slave_0_abus_direction,
abus_slave_0_abus_muxing => abus_slave_0_abus_muxing,
abus_slave_0_abus_disableout => abus_slave_0_abus_disableout,
abus_slave_0_conduit_saturn_reset_saturn_reset => reset_reset_n,
--spi_sd_card_MISO => spi_sd_card_MISO,
--spi_sd_card_MOSI => spi_sd_card_MOSI,
--spi_sd_card_SCLK => spi_sd_card_SCLK,
--spi_sd_card_SS_n => spi_sd_card_SS_n,
sdram_clkout_clk => external_sdram_clk_pin,
altpll_0_areset_conduit_export => open,
altpll_0_locked_conduit_export => altpll_0_locked_conduit_export,
altpll_0_phasedone_conduit_export => open,
uart_0_external_connection_rxd => uart_0_external_connection_rxd,
uart_0_external_connection_txd => uart_0_external_connection_txd,
hex0_conn_export => hex0_conn_export,
hex1_conn_export => hex1_conn_export,
hex2_conn_export => hex2_conn_export,
hex3_conn_export => hex3_conn_export,
hex4_conn_export => hex4_conn_export,
hex5_conn_export => hex5_conn_export,
hexdot_conn_export => hexdot_conn_export,
leds_conn_export => leds_conn_export,
extra_leds_conn_export => extra_leds_conn_export,
switches_conn_export => switches_conn_export,
spi_sync_conn_export => spi_sync_conn_export,
spi_stm32_MISO => spi_stm32_MISO,
spi_stm32_MOSI => spi_stm32_MOSI,
spi_stm32_SCLK => spi_stm32_SCLK,
spi_stm32_SS_n => spi_stm32_SS_n
--audio_out_BCLK => audio_out_BCLK,
--audio_out_DACDAT => audio_out_DACDAT,
--audio_out_DACLRCK => audio_out_DACLRCK
);
--audio_SSEL <= '0';
--abus_slave_0_abus_waitrequest <= '1';
--abus_slave_0_abus_direction <= '0';
--abus_slave_0_abus_muxing <= "01";
end architecture rtl; -- of wasca_toplevel
| gpl-2.0 | 41930c5bb200e5e177ebb2736696d655 | 0.438618 | 4.04005 | false | false | false | false |
michaelfivez/ascon_hardware_implementation | ascon12864_unrolled6/API_plus_CipherCore/std_logic_1164_additions.vhd | 9 | 70,122 | ------------------------------------------------------------------------------
-- "std_logic_1164_additions" package contains the additions to the standard
-- "std_logic_1164" package proposed by the VHDL-200X-ft working group.
-- This package should be compiled into "ieee_proposed" and used as follows:
-- use ieee.std_logic_1164.all;
-- use ieee_proposed.std_logic_1164_additions.all;
-- Last Modified: $Date: 2007-05-31 14:53:37-04 $
-- RCS ID: $Id: std_logic_1164_additions.vhdl,v 1.10 2007-05-31 14:53:37-04 l435385 Exp $
--
-- Created for VHDL-200X par, David Bishop ([email protected])
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
package std_logic_1164_additions is
-- NOTE that in the new std_logic_1164, STD_LOGIC_VECTOR is a resolved
-- subtype of STD_ULOGIC_VECTOR. Thus there is no need for funcitons which
-- take inputs in STD_LOGIC_VECTOR.
-- For compatability with VHDL-2002, I have replicated all of these funcitons
-- here for STD_LOGIC_VECTOR.
-- new aliases
alias to_bv is ieee.std_logic_1164.To_bitvector [STD_LOGIC_VECTOR, BIT return BIT_VECTOR];
alias to_bv is ieee.std_logic_1164.To_bitvector [STD_ULOGIC_VECTOR, BIT return BIT_VECTOR];
alias to_bit_vector is ieee.std_logic_1164.To_bitvector [STD_LOGIC_VECTOR, BIT return BIT_VECTOR];
alias to_bit_vector is ieee.std_logic_1164.To_bitvector [STD_ULOGIC_VECTOR, BIT return BIT_VECTOR];
alias to_slv is ieee.std_logic_1164.To_StdLogicVector [BIT_VECTOR return STD_LOGIC_VECTOR];
alias to_slv is ieee.std_logic_1164.To_StdLogicVector [STD_ULOGIC_VECTOR return STD_LOGIC_VECTOR];
alias to_std_logic_vector is ieee.std_logic_1164.To_StdLogicVector [BIT_VECTOR return STD_LOGIC_VECTOR];
alias to_std_logic_vector is ieee.std_logic_1164.To_StdLogicVector [STD_ULOGIC_VECTOR return STD_LOGIC_VECTOR];
alias to_suv is ieee.std_logic_1164.To_StdULogicVector [BIT_VECTOR return STD_ULOGIC_VECTOR];
alias to_suv is ieee.std_logic_1164.To_StdULogicVector [STD_LOGIC_VECTOR return STD_ULOGIC_VECTOR];
alias to_std_ulogic_vector is ieee.std_logic_1164.To_StdULogicVector [BIT_VECTOR return STD_ULOGIC_VECTOR];
alias to_std_ulogic_vector is ieee.std_logic_1164.To_StdULogicVector [STD_LOGIC_VECTOR return STD_ULOGIC_VECTOR];
-------------------------------------------------------------------
-- overloaded shift operators
-------------------------------------------------------------------
function "sll" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR;
function "sll" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;
function "srl" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR;
function "srl" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;
function "rol" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR;
function "rol" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;
function "ror" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR;
function "ror" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;
-------------------------------------------------------------------
-- vector/scalar overloaded logical operators
-------------------------------------------------------------------
function "and" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR;
function "and" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "and" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "and" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "nand" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR;
function "nand" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "nand" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "nand" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "or" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR;
function "or" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "or" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "or" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "nor" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR;
function "nor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "nor" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "nor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "xor" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR;
function "xor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "xor" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "xor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "xnor" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR;
function "xnor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "xnor" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "xnor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-------------------------------------------------------------------
-- vector-reduction functions.
-- "and" functions default to "1", or defaults to "0"
-------------------------------------------------------------------
-----------------------------------------------------------------------------
-- %%% Replace the "_reduce" functions with the ones commented out below.
-----------------------------------------------------------------------------
-- function "and" ( l : std_logic_vector ) RETURN std_ulogic;
-- function "and" ( l : std_ulogic_vector ) RETURN std_ulogic;
-- function "nand" ( l : std_logic_vector ) RETURN std_ulogic;
-- function "nand" ( l : std_ulogic_vector ) RETURN std_ulogic;
-- function "or" ( l : std_logic_vector ) RETURN std_ulogic;
-- function "or" ( l : std_ulogic_vector ) RETURN std_ulogic;
-- function "nor" ( l : std_logic_vector ) RETURN std_ulogic;
-- function "nor" ( l : std_ulogic_vector ) RETURN std_ulogic;
-- function "xor" ( l : std_logic_vector ) RETURN std_ulogic;
-- function "xor" ( l : std_ulogic_vector ) RETURN std_ulogic;
-- function "xnor" ( l : std_logic_vector ) RETURN std_ulogic;
-- function "xnor" ( l : std_ulogic_vector ) RETURN std_ulogic;
function and_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC;
function and_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function nand_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC;
function nand_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function or_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC;
function or_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function nor_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC;
function nor_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function xor_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC;
function xor_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function xnor_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC;
function xnor_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-------------------------------------------------------------------
-- ?= operators, same functionality as 1076.3 1994 std_match
-------------------------------------------------------------------
-- FUNCTION "?=" ( l, r : std_ulogic ) RETURN std_ulogic;
-- FUNCTION "?=" ( l, r : std_logic_vector ) RETURN std_ulogic;
-- FUNCTION "?=" ( l, r : std_ulogic_vector ) RETURN std_ulogic;
-- FUNCTION "?/=" ( l, r : std_ulogic ) RETURN std_ulogic;
-- FUNCTION "?/=" ( l, r : std_logic_vector ) RETURN std_ulogic;
-- FUNCTION "?/=" ( l, r : std_ulogic_vector ) RETURN std_ulogic;
-- FUNCTION "?>" ( l, r : std_ulogic ) RETURN std_ulogic;
-- FUNCTION "?>=" ( l, r : std_ulogic ) RETURN std_ulogic;
-- FUNCTION "?<" ( l, r : std_ulogic ) RETURN std_ulogic;
-- FUNCTION "?<=" ( l, r : std_ulogic ) RETURN std_ulogic;
function \?=\ (l, r : STD_ULOGIC) return STD_ULOGIC;
function \?=\ (l, r : STD_LOGIC_VECTOR) return STD_ULOGIC;
function \?=\ (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function \?/=\ (l, r : STD_ULOGIC) return STD_ULOGIC;
function \?/=\ (l, r : STD_LOGIC_VECTOR) return STD_ULOGIC;
function \?/=\ (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function \?>\ (l, r : STD_ULOGIC) return STD_ULOGIC;
function \?>=\ (l, r : STD_ULOGIC) return STD_ULOGIC;
function \?<\ (l, r : STD_ULOGIC) return STD_ULOGIC;
function \?<=\ (l, r : STD_ULOGIC) return STD_ULOGIC;
-- "??" operator, converts a std_ulogic to a boolean.
--%%% Uncomment the following operators
-- FUNCTION "??" (S : STD_ULOGIC) RETURN BOOLEAN;
--%%% REMOVE the following funciton (for testing only)
function \??\ (S : STD_ULOGIC) return BOOLEAN;
-- rtl_synthesis off
function to_string (value : STD_ULOGIC) return STRING;
function to_string (value : STD_ULOGIC_VECTOR) return STRING;
function to_string (value : STD_LOGIC_VECTOR) return STRING;
-- explicitly defined operations
alias TO_BSTRING is TO_STRING [STD_ULOGIC_VECTOR return STRING];
alias TO_BINARY_STRING is TO_STRING [STD_ULOGIC_VECTOR return STRING];
function TO_OSTRING (VALUE : STD_ULOGIC_VECTOR) return STRING;
alias TO_OCTAL_STRING is TO_OSTRING [STD_ULOGIC_VECTOR return STRING];
function TO_HSTRING (VALUE : STD_ULOGIC_VECTOR) return STRING;
alias TO_HEX_STRING is TO_HSTRING [STD_ULOGIC_VECTOR return STRING];
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC; GOOD : out BOOLEAN);
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC);
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR; GOOD : out BOOLEAN);
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR);
procedure WRITE (L : inout LINE; VALUE : in STD_ULOGIC;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
procedure WRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias BREAD is READ [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
alias BREAD is READ [LINE, STD_ULOGIC_VECTOR];
alias BINARY_READ is READ [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
alias BINARY_READ is READ [LINE, STD_ULOGIC_VECTOR];
procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR; GOOD : out BOOLEAN);
procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR);
alias OCTAL_READ is OREAD [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
alias OCTAL_READ is OREAD [LINE, STD_ULOGIC_VECTOR];
-- procedure HREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR; GOOD : out BOOLEAN);
-- procedure HREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR);
-- alias HEX_READ is HREAD [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
-- alias HEX_READ is HREAD [LINE, STD_ULOGIC_VECTOR];
alias BWRITE is WRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];
alias BINARY_WRITE is WRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];
procedure OWRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias OCTAL_WRITE is OWRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];
procedure HWRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias HEX_WRITE is HWRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];
alias TO_BSTRING is TO_STRING [STD_LOGIC_VECTOR return STRING];
alias TO_BINARY_STRING is TO_STRING [STD_LOGIC_VECTOR return STRING];
function TO_OSTRING (VALUE : STD_LOGIC_VECTOR) return STRING;
alias TO_OCTAL_STRING is TO_OSTRING [STD_LOGIC_VECTOR return STRING];
function TO_HSTRING (VALUE : STD_LOGIC_VECTOR) return STRING;
alias TO_HEX_STRING is TO_HSTRING [STD_LOGIC_VECTOR return STRING];
procedure READ (L : inout LINE; VALUE : out STD_LOGIC_VECTOR; GOOD : out BOOLEAN);
procedure READ (L : inout LINE; VALUE : out STD_LOGIC_VECTOR);
procedure WRITE (L : inout LINE; VALUE : in STD_LOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias BREAD is READ [LINE, STD_LOGIC_VECTOR, BOOLEAN];
alias BREAD is READ [LINE, STD_LOGIC_VECTOR];
alias BINARY_READ is READ [LINE, STD_LOGIC_VECTOR, BOOLEAN];
alias BINARY_READ is READ [LINE, STD_LOGIC_VECTOR];
procedure OREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR; GOOD : out BOOLEAN);
procedure OREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR);
alias OCTAL_READ is OREAD [LINE, STD_LOGIC_VECTOR, BOOLEAN];
alias OCTAL_READ is OREAD [LINE, STD_LOGIC_VECTOR];
-- procedure HREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR; GOOD : out BOOLEAN);
-- procedure HREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR);
-- alias HEX_READ is HREAD [LINE, STD_LOGIC_VECTOR, BOOLEAN];
-- alias HEX_READ is HREAD [LINE, STD_LOGIC_VECTOR];
alias BWRITE is WRITE [LINE, STD_LOGIC_VECTOR, SIDE, WIDTH];
alias BINARY_WRITE is WRITE [LINE, STD_LOGIC_VECTOR, SIDE, WIDTH];
procedure OWRITE (L : inout LINE; VALUE : in STD_LOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias OCTAL_WRITE is OWRITE [LINE, STD_LOGIC_VECTOR, SIDE, WIDTH];
procedure HWRITE (L : inout LINE; VALUE : in STD_LOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias HEX_WRITE is HWRITE [LINE, STD_LOGIC_VECTOR, SIDE, WIDTH];
-- rtl_synthesis on
function maximum (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function maximum (l, r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function maximum (l, r : STD_ULOGIC) return STD_ULOGIC;
function minimum (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function minimum (l, r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function minimum (l, r : STD_ULOGIC) return STD_ULOGIC;
end package std_logic_1164_additions;
package body std_logic_1164_additions is
type stdlogic_table is array(STD_ULOGIC, STD_ULOGIC) of STD_ULOGIC;
-----------------------------------------------------------------------------
-- New/updated funcitons for VHDL-200X fast track
-----------------------------------------------------------------------------
-------------------------------------------------------------------
-- overloaded shift operators
-------------------------------------------------------------------
-------------------------------------------------------------------
-- sll
-------------------------------------------------------------------
function "sll" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length) := (others => '0');
begin
if r >= 0 then
result(1 to l'length - r) := lv(r + 1 to l'length);
else
result := l srl -r;
end if;
return result;
end function "sll";
-------------------------------------------------------------------
function "sll" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length) := (others => '0');
begin
if r >= 0 then
result(1 to l'length - r) := lv(r + 1 to l'length);
else
result := l srl -r;
end if;
return result;
end function "sll";
-------------------------------------------------------------------
-- srl
-------------------------------------------------------------------
function "srl" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length) := (others => '0');
begin
if r >= 0 then
result(r + 1 to l'length) := lv(1 to l'length - r);
else
result := l sll -r;
end if;
return result;
end function "srl";
-------------------------------------------------------------------
function "srl" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length) := (others => '0');
begin
if r >= 0 then
result(r + 1 to l'length) := lv(1 to l'length - r);
else
result := l sll -r;
end if;
return result;
end function "srl";
-------------------------------------------------------------------
-- rol
-------------------------------------------------------------------
function "rol" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length);
constant rm : INTEGER := r mod l'length;
begin
if r >= 0 then
result(1 to l'length - rm) := lv(rm + 1 to l'length);
result(l'length - rm + 1 to l'length) := lv(1 to rm);
else
result := l ror -r;
end if;
return result;
end function "rol";
-------------------------------------------------------------------
function "rol" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
constant rm : INTEGER := r mod l'length;
begin
if r >= 0 then
result(1 to l'length - rm) := lv(rm + 1 to l'length);
result(l'length - rm + 1 to l'length) := lv(1 to rm);
else
result := l ror -r;
end if;
return result;
end function "rol";
-------------------------------------------------------------------
-- ror
-------------------------------------------------------------------
function "ror" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length) := (others => '0');
constant rm : INTEGER := r mod l'length;
begin
if r >= 0 then
result(rm + 1 to l'length) := lv(1 to l'length - rm);
result(1 to rm) := lv(l'length - rm + 1 to l'length);
else
result := l rol -r;
end if;
return result;
end function "ror";
-------------------------------------------------------------------
function "ror" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length) := (others => '0');
constant rm : INTEGER := r mod l'length;
begin
if r >= 0 then
result(rm + 1 to l'length) := lv(1 to l'length - rm);
result(1 to rm) := lv(l'length - rm + 1 to l'length);
else
result := l rol -r;
end if;
return result;
end function "ror";
-------------------------------------------------------------------
-- vector/scalar overloaded logical operators
-------------------------------------------------------------------
-------------------------------------------------------------------
-- and
-------------------------------------------------------------------
function "and" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "and" (lv(i), r);
end loop;
return result;
end function "and";
-------------------------------------------------------------------
function "and" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "and" (lv(i), r);
end loop;
return result;
end function "and";
-------------------------------------------------------------------
function "and" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
alias rv : STD_LOGIC_VECTOR (1 to r'length) is r;
variable result : STD_LOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "and" (l, rv(i));
end loop;
return result;
end function "and";
-------------------------------------------------------------------
function "and" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "and" (l, rv(i));
end loop;
return result;
end function "and";
-------------------------------------------------------------------
-- nand
-------------------------------------------------------------------
function "nand" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "not"("and" (lv(i), r));
end loop;
return result;
end function "nand";
-------------------------------------------------------------------
function "nand" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "not"("and" (lv(i), r));
end loop;
return result;
end function "nand";
-------------------------------------------------------------------
function "nand" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
alias rv : STD_LOGIC_VECTOR (1 to r'length) is r;
variable result : STD_LOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "not"("and" (l, rv(i)));
end loop;
return result;
end function "nand";
-------------------------------------------------------------------
function "nand" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "not"("and" (l, rv(i)));
end loop;
return result;
end function "nand";
-------------------------------------------------------------------
-- or
-------------------------------------------------------------------
function "or" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "or" (lv(i), r);
end loop;
return result;
end function "or";
-------------------------------------------------------------------
function "or" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "or" (lv(i), r);
end loop;
return result;
end function "or";
-------------------------------------------------------------------
function "or" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
alias rv : STD_LOGIC_VECTOR (1 to r'length) is r;
variable result : STD_LOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "or" (l, rv(i));
end loop;
return result;
end function "or";
-------------------------------------------------------------------
function "or" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "or" (l, rv(i));
end loop;
return result;
end function "or";
-------------------------------------------------------------------
-- nor
-------------------------------------------------------------------
function "nor" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "not"("or" (lv(i), r));
end loop;
return result;
end function "nor";
-------------------------------------------------------------------
function "nor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "not"("or" (lv(i), r));
end loop;
return result;
end function "nor";
-------------------------------------------------------------------
function "nor" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
alias rv : STD_LOGIC_VECTOR (1 to r'length) is r;
variable result : STD_LOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "not"("or" (l, rv(i)));
end loop;
return result;
end function "nor";
-------------------------------------------------------------------
function "nor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "not"("or" (l, rv(i)));
end loop;
return result;
end function "nor";
-------------------------------------------------------------------
-- xor
-------------------------------------------------------------------
function "xor" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "xor" (lv(i), r);
end loop;
return result;
end function "xor";
-------------------------------------------------------------------
function "xor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "xor" (lv(i), r);
end loop;
return result;
end function "xor";
-------------------------------------------------------------------
function "xor" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
alias rv : STD_LOGIC_VECTOR (1 to r'length) is r;
variable result : STD_LOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "xor" (l, rv(i));
end loop;
return result;
end function "xor";
-------------------------------------------------------------------
function "xor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "xor" (l, rv(i));
end loop;
return result;
end function "xor";
-------------------------------------------------------------------
-- xnor
-------------------------------------------------------------------
function "xnor" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "not"("xor" (lv(i), r));
end loop;
return result;
end function "xnor";
-------------------------------------------------------------------
function "xnor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "not"("xor" (lv(i), r));
end loop;
return result;
end function "xnor";
-------------------------------------------------------------------
function "xnor" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
alias rv : STD_LOGIC_VECTOR (1 to r'length) is r;
variable result : STD_LOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "not"("xor" (l, rv(i)));
end loop;
return result;
end function "xnor";
-------------------------------------------------------------------
function "xnor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "not"("xor" (l, rv(i)));
end loop;
return result;
end function "xnor";
-------------------------------------------------------------------
-- vector-reduction functions
-------------------------------------------------------------------
-------------------------------------------------------------------
-- and
-------------------------------------------------------------------
function and_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return and_reduce (to_StdULogicVector (l));
end function and_reduce;
-------------------------------------------------------------------
function and_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
variable result : STD_ULOGIC := '1';
begin
for i in l'reverse_range loop
result := (l(i) and result);
end loop;
return result;
end function and_reduce;
-------------------------------------------------------------------
-- nand
-------------------------------------------------------------------
function nand_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return not (and_reduce(to_StdULogicVector(l)));
end function nand_reduce;
-------------------------------------------------------------------
function nand_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return not (and_reduce(l));
end function nand_reduce;
-------------------------------------------------------------------
-- or
-------------------------------------------------------------------
function or_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return or_reduce (to_StdULogicVector (l));
end function or_reduce;
-------------------------------------------------------------------
function or_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
variable result : STD_ULOGIC := '0';
begin
for i in l'reverse_range loop
result := (l(i) or result);
end loop;
return result;
end function or_reduce;
-------------------------------------------------------------------
-- nor
-------------------------------------------------------------------
function nor_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return "not"(or_reduce(To_StdULogicVector(l)));
end function nor_reduce;
-------------------------------------------------------------------
function nor_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return "not"(or_reduce(l));
end function nor_reduce;
-------------------------------------------------------------------
-- xor
-------------------------------------------------------------------
function xor_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return xor_reduce (to_StdULogicVector (l));
end function xor_reduce;
-------------------------------------------------------------------
function xor_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
variable result : STD_ULOGIC := '0';
begin
for i in l'reverse_range loop
result := (l(i) xor result);
end loop;
return result;
end function xor_reduce;
-------------------------------------------------------------------
-- xnor
-------------------------------------------------------------------
function xnor_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return "not"(xor_reduce(To_StdULogicVector(l)));
end function xnor_reduce;
-------------------------------------------------------------------
function xnor_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return "not"(xor_reduce(l));
end function xnor_reduce;
-- %%% End "remove the following functions"
-- The following functions are implicity in 1076-2006
-- truth table for "?=" function
constant match_logic_table : stdlogic_table := (
-----------------------------------------------------
-- U X 0 1 Z W L H - | |
-----------------------------------------------------
('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', '1'), -- | U |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | X |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '1'), -- | 0 |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '1'), -- | 1 |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | Z |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | W |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '1'), -- | L |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '1'), -- | H |
('1', '1', '1', '1', '1', '1', '1', '1', '1') -- | - |
);
constant no_match_logic_table : stdlogic_table := (
-----------------------------------------------------
-- U X 0 1 Z W L H - | |
-----------------------------------------------------
('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', '0'), -- | U |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '0'), -- | X |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '0'), -- | 0 |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '0'), -- | 1 |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '0'), -- | Z |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '0'), -- | W |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '0'), -- | L |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '0'), -- | H |
('0', '0', '0', '0', '0', '0', '0', '0', '0') -- | - |
);
-------------------------------------------------------------------
-- ?= functions, Similar to "std_match", but returns "std_ulogic".
-------------------------------------------------------------------
-- %%% FUNCTION "?=" ( l, r : std_ulogic ) RETURN std_ulogic IS
function \?=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
begin
return match_logic_table (l, r);
end function \?=\;
-- %%% END FUNCTION "?=";
-------------------------------------------------------------------
-- %%% FUNCTION "?=" ( l, r : std_logic_vector ) RETURN std_ulogic IS
function \?=\ (l, r : STD_LOGIC_VECTOR) return STD_ULOGIC is
alias lv : STD_LOGIC_VECTOR(1 to l'length) is l;
alias rv : STD_LOGIC_VECTOR(1 to r'length) is r;
variable result, result1 : STD_ULOGIC; -- result
begin
-- Logically identical to an "=" operator.
if ((l'length < 1) or (r'length < 1)) then
report "STD_LOGIC_1164.""?="": null detected, returning X"
severity warning;
return 'X';
end if;
if lv'length /= rv'length then
report "STD_LOGIC_1164.""?="": L'LENGTH /= R'LENGTH, returning X"
severity warning;
return 'X';
else
result := '1';
for i in lv'low to lv'high loop
result1 := match_logic_table(lv(i), rv(i));
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result and result1;
end if;
end loop;
return result;
end if;
end function \?=\;
-- %%% END FUNCTION "?=";
-------------------------------------------------------------------
-- %%% FUNCTION "?=" ( l, r : std_ulogic_vector ) RETURN std_ulogic IS
function \?=\ (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC is
alias lv : STD_ULOGIC_VECTOR(1 to l'length) is l;
alias rv : STD_ULOGIC_VECTOR(1 to r'length) is r;
variable result, result1 : STD_ULOGIC;
begin
if ((l'length < 1) or (r'length < 1)) then
report "STD_LOGIC_1164.""?="": null detected, returning X"
severity warning;
return 'X';
end if;
if lv'length /= rv'length then
report "STD_LOGIC_1164.""?="": L'LENGTH /= R'LENGTH, returning X"
severity warning;
return 'X';
else
result := '1';
for i in lv'low to lv'high loop
result1 := match_logic_table(lv(i), rv(i));
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result and result1;
end if;
end loop;
return result;
end if;
end function \?=\;
-- %%% END FUNCTION "?=";
-- %%% FUNCTION "?/=" ( l, r : std_ulogic ) RETURN std_ulogic is
function \?/=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
begin
return no_match_logic_table (l, r);
end function \?/=\;
-- %%% END FUNCTION "?/=";
-- %%% FUNCTION "?/=" ( l, r : std_logic_vector ) RETURN std_ulogic is
function \?/=\ (l, r : STD_LOGIC_VECTOR) return STD_ULOGIC is
alias lv : STD_LOGIC_VECTOR(1 to l'length) is l;
alias rv : STD_LOGIC_VECTOR(1 to r'length) is r;
variable result, result1 : STD_ULOGIC; -- result
begin
if ((l'length < 1) or (r'length < 1)) then
report "STD_LOGIC_1164.""?/="": null detected, returning X"
severity warning;
return 'X';
end if;
if lv'length /= rv'length then
report "STD_LOGIC_1164.""?/="": L'LENGTH /= R'LENGTH, returning X"
severity warning;
return 'X';
else
result := '0';
for i in lv'low to lv'high loop
result1 := no_match_logic_table(lv(i), rv(i));
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result or result1;
end if;
end loop;
return result;
end if;
end function \?/=\;
-- %%% END FUNCTION "?/=";
-- %%% FUNCTION "?/=" ( l, r : std_ulogic_vector ) RETURN std_ulogic is
function \?/=\ (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC is
alias lv : STD_ULOGIC_VECTOR(1 to l'length) is l;
alias rv : STD_ULOGIC_VECTOR(1 to r'length) is r;
variable result, result1 : STD_ULOGIC;
begin
if ((l'length < 1) or (r'length < 1)) then
report "STD_LOGIC_1164.""?/="": null detected, returning X"
severity warning;
return 'X';
end if;
if lv'length /= rv'length then
report "STD_LOGIC_1164.""?/="": L'LENGTH /= R'LENGTH, returning X"
severity warning;
return 'X';
else
result := '0';
for i in lv'low to lv'high loop
result1 := no_match_logic_table(lv(i), rv(i));
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result or result1;
end if;
end loop;
return result;
end if;
end function \?/=\;
-- %%% END FUNCTION "?/=";
-- %%% FUNCTION "?>" ( l, r : std_ulogic ) RETURN std_ulogic is
function \?>\ (l, r : STD_ULOGIC) return STD_ULOGIC is
variable lx, rx : STD_ULOGIC;
begin
if (l = '-') or (r = '-') then
report "STD_LOGIC_1164.""?>"": '-' found in compare string"
severity error;
return 'X';
else
lx := to_x01 (l);
rx := to_x01 (r);
if lx = 'X' or rx = 'X' then
return 'X';
elsif lx > rx then
return '1';
else
return '0';
end if;
end if;
end function \?>\;
-- %%% END FUNCTION "?>";
-- %%% FUNCTION "?>=" ( l, r : std_ulogic ) RETURN std_ulogic is
function \?>=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
variable lx, rx : STD_ULOGIC;
begin
if (l = '-') or (r = '-') then
report "STD_LOGIC_1164.""?>="": '-' found in compare string"
severity error;
return 'X';
else
lx := to_x01 (l);
rx := to_x01 (r);
if lx = 'X' or rx = 'X' then
return 'X';
elsif lx >= rx then
return '1';
else
return '0';
end if;
end if;
end function \?>=\;
-- %%% END FUNCTION "?/>=";
-- %%% FUNCTION "?<" ( l, r : std_ulogic ) RETURN std_ulogic is
function \?<\ (l, r : STD_ULOGIC) return STD_ULOGIC is
variable lx, rx : STD_ULOGIC;
begin
if (l = '-') or (r = '-') then
report "STD_LOGIC_1164.""?<"": '-' found in compare string"
severity error;
return 'X';
else
lx := to_x01 (l);
rx := to_x01 (r);
if lx = 'X' or rx = 'X' then
return 'X';
elsif lx < rx then
return '1';
else
return '0';
end if;
end if;
end function \?<\;
-- %%% END FUNCTION "?/<";
-- %%% FUNCTION "?<=" ( l, r : std_ulogic ) RETURN std_ulogic is
function \?<=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
variable lx, rx : STD_ULOGIC;
begin
if (l = '-') or (r = '-') then
report "STD_LOGIC_1164.""?<="": '-' found in compare string"
severity error;
return 'X';
else
lx := to_x01 (l);
rx := to_x01 (r);
if lx = 'X' or rx = 'X' then
return 'X';
elsif lx <= rx then
return '1';
else
return '0';
end if;
end if;
end function \?<=\;
-- %%% END FUNCTION "?/<=";
-- "??" operator, converts a std_ulogic to a boolean.
-- %%% FUNCTION "??"
function \??\ (S : STD_ULOGIC) return BOOLEAN is
begin
return S = '1' or S = 'H';
end function \??\;
-- %%% END FUNCTION "??";
-- rtl_synthesis off
-----------------------------------------------------------------------------
-- This section copied from "std_logic_textio"
-----------------------------------------------------------------------------
-- Type and constant definitions used to map STD_ULOGIC values
-- into/from character values.
type MVL9plus is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-', error);
type char_indexed_by_MVL9 is array (STD_ULOGIC) of CHARACTER;
type MVL9_indexed_by_char is array (CHARACTER) of STD_ULOGIC;
type MVL9plus_indexed_by_char is array (CHARACTER) of MVL9plus;
constant MVL9_to_char : char_indexed_by_MVL9 := "UX01ZWLH-";
constant char_to_MVL9 : MVL9_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => 'U');
constant char_to_MVL9plus : MVL9plus_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => error);
constant NBSP : CHARACTER := CHARACTER'val(160); -- space character
constant NUS : STRING(2 to 1) := (others => ' '); -- null STRING
-- purpose: Skips white space
procedure skip_whitespace (
L : inout LINE) is
variable readOk : BOOLEAN;
variable c : CHARACTER;
begin
while L /= null and L.all'length /= 0 loop
if (L.all(1) = ' ' or L.all(1) = NBSP or L.all(1) = HT) then
read (l, c, readOk);
else
exit;
end if;
end loop;
end procedure skip_whitespace;
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC;
GOOD : out BOOLEAN) is
variable c : CHARACTER;
variable readOk : BOOLEAN;
begin
VALUE := 'U'; -- initialize to a "U"
Skip_whitespace (L);
read (l, c, readOk);
if not readOk then
good := false;
else
if char_to_MVL9plus(c) = error then
good := false;
else
VALUE := char_to_MVL9(c);
good := true;
end if;
end if;
end procedure READ;
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable m : STD_ULOGIC;
variable c : CHARACTER;
variable mv : STD_ULOGIC_VECTOR(0 to VALUE'length-1);
variable readOk : BOOLEAN;
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, readOk);
i := 0;
good := false;
while i < VALUE'length loop
if not readOk then -- Bail out if there was a bad read
return;
elsif c = '_' then
if i = 0 then -- Begins with an "_"
return;
elsif lastu then -- "__" detected
return;
else
lastu := true;
end if;
elsif (char_to_MVL9plus(c) = error) then -- Illegal character
return;
else
mv(i) := char_to_MVL9(c);
i := i + 1;
if i > mv'high then -- reading done
good := true;
VALUE := mv;
return;
end if;
lastu := false;
end if;
read(L, c, readOk);
end loop;
else
good := true; -- read into a null array
end if;
end procedure READ;
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC) is
variable c : CHARACTER;
variable readOk : BOOLEAN;
begin
VALUE := 'U'; -- initialize to a "U"
Skip_whitespace (L);
read (l, c, readOk);
if not readOk then
report "STD_LOGIC_1164.READ(STD_ULOGIC) "
& "End of string encountered"
severity error;
return;
elsif char_to_MVL9plus(c) = error then
report
"STD_LOGIC_1164.READ(STD_ULOGIC) Error: Character '" &
c & "' read, expected STD_ULOGIC literal."
severity error;
else
VALUE := char_to_MVL9(c);
end if;
end procedure READ;
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR) is
variable m : STD_ULOGIC;
variable c : CHARACTER;
variable readOk : BOOLEAN;
variable mv : STD_ULOGIC_VECTOR(0 to VALUE'length-1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then -- non Null input string
read (l, c, readOk);
i := 0;
while i < VALUE'length loop
if readOk = false then -- Bail out if there was a bad read
report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
& "End of string encountered"
severity error;
return;
elsif c = '_' then
if i = 0 then
report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
& "String begins with an ""_""" severity error;
return;
elsif lastu then
report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
& "Two underscores detected in input string ""__"""
severity error;
return;
else
lastu := true;
end if;
elsif c = ' ' or c = NBSP or c = HT then -- reading done.
report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
& "Short read, Space encounted in input string"
severity error;
return;
elsif char_to_MVL9plus(c) = error then
report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
& "Error: Character '" &
c & "' read, expected STD_ULOGIC literal."
severity error;
return;
else
mv(i) := char_to_MVL9(c);
i := i + 1;
if i > mv'high then
VALUE := mv;
return;
end if;
lastu := false;
end if;
read(L, c, readOk);
end loop;
end if;
end procedure READ;
procedure WRITE (L : inout LINE; VALUE : in STD_ULOGIC;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write(l, MVL9_to_char(VALUE), justified, field);
end procedure WRITE;
procedure WRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
variable s : STRING(1 to VALUE'length);
variable m : STD_ULOGIC_VECTOR(1 to VALUE'length) := VALUE;
begin
for i in 1 to VALUE'length loop
s(i) := MVL9_to_char(m(i));
end loop;
write(l, s, justified, field);
end procedure WRITE;
-- Read and Write procedures for STD_LOGIC_VECTOR
procedure READ (L : inout LINE; VALUE : out STD_LOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable ivalue : STD_ULOGIC_VECTOR (VALUE'range);
begin
READ (L => L, VALUE => ivalue, GOOD => GOOD);
VALUE := to_stdlogicvector (ivalue);
end procedure READ;
procedure READ (L : inout LINE; VALUE : out STD_LOGIC_VECTOR) is
variable ivalue : STD_ULOGIC_VECTOR (VALUE'range);
begin
READ (L => L, VALUE => ivalue);
VALUE := to_stdlogicvector (ivalue);
end procedure READ;
procedure WRITE (L : inout LINE; VALUE : in STD_LOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
variable s : STRING(1 to VALUE'length);
variable m : STD_LOGIC_VECTOR(1 to VALUE'length) := VALUE;
begin
for i in 1 to VALUE'length loop
s(i) := MVL9_to_char(m(i));
end loop;
write(L, s, justified, field);
end procedure WRITE;
-----------------------------------------------------------------------
-- Alias for bread and bwrite are provided with call out the read and
-- write functions.
-----------------------------------------------------------------------
-- Hex Read and Write procedures for STD_ULOGIC_VECTOR.
-- Modified from the original to be more forgiving.
procedure Char2QuadBits (C : CHARACTER;
RESULT : out STD_ULOGIC_VECTOR(3 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case c is
when '0' => result := x"0"; good := true;
when '1' => result := x"1"; good := true;
when '2' => result := x"2"; good := true;
when '3' => result := x"3"; good := true;
when '4' => result := x"4"; good := true;
when '5' => result := x"5"; good := true;
when '6' => result := x"6"; good := true;
when '7' => result := x"7"; good := true;
when '8' => result := x"8"; good := true;
when '9' => result := x"9"; good := true;
when 'A' | 'a' => result := x"A"; good := true;
when 'B' | 'b' => result := x"B"; good := true;
when 'C' | 'c' => result := x"C"; good := true;
when 'D' | 'd' => result := x"D"; good := true;
when 'E' | 'e' => result := x"E"; good := true;
when 'F' | 'f' => result := x"F"; good := true;
when 'Z' => result := "ZZZZ"; good := true;
when 'X' => result := "XXXX"; good := true;
when others =>
assert not ISSUE_ERROR
report
"STD_LOGIC_1164.HREAD Read a '" & c &
"', expected a Hex character (0-F)."
severity error;
good := false;
end case;
end procedure Char2QuadBits;
-- procedure HREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR;
-- GOOD : out BOOLEAN) is
-- variable ok : BOOLEAN;
-- variable c : CHARACTER;
-- constant ne : INTEGER := (VALUE'length+3)/4;
-- constant pad : INTEGER := ne*4 - VALUE'length;
-- variable sv : STD_ULOGIC_VECTOR(0 to ne*4 - 1);
-- variable i : INTEGER;
-- variable lastu : BOOLEAN := false; -- last character was an "_"
-- begin
-- VALUE := (VALUE'range => 'U'); -- initialize to a "U"
-- Skip_whitespace (L);
-- if VALUE'length > 0 then
-- read (l, c, ok);
-- i := 0;
-- while i < ne loop
-- -- Bail out if there was a bad read
-- if not ok then
-- good := false;
-- return;
-- elsif c = '_' then
-- if i = 0 then
-- good := false; -- Begins with an "_"
-- return;
-- elsif lastu then
-- good := false; -- "__" detected
-- return;
-- else
-- lastu := true;
-- end if;
-- else
-- Char2QuadBits(c, sv(4*i to 4*i+3), ok, false);
-- if not ok then
-- good := false;
-- return;
-- end if;
-- i := i + 1;
-- lastu := false;
-- end if;
-- if i < ne then
-- read(L, c, ok);
-- end if;
-- end loop;
-- if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with "or"
-- good := false; -- vector was truncated.
-- else
-- good := true;
-- VALUE := sv (pad to sv'high);
-- end if;
-- else
-- good := true; -- Null input string, skips whitespace
-- end if;
-- end procedure HREAD;
-- procedure HREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR) is
-- variable ok : BOOLEAN;
-- variable c : CHARACTER;
-- constant ne : INTEGER := (VALUE'length+3)/4;
-- constant pad : INTEGER := ne*4 - VALUE'length;
-- variable sv : STD_ULOGIC_VECTOR(0 to ne*4 - 1);
-- variable i : INTEGER;
-- variable lastu : BOOLEAN := false; -- last character was an "_"
-- begin
-- VALUE := (VALUE'range => 'U'); -- initialize to a "U"
-- Skip_whitespace (L);
-- if VALUE'length > 0 then -- non Null input string
-- read (l, c, ok);
-- i := 0;
-- while i < ne loop
-- -- Bail out if there was a bad read
-- if not ok then
-- report "STD_LOGIC_1164.HREAD "
-- & "End of string encountered"
-- severity error;
-- return;
-- end if;
-- if c = '_' then
-- if i = 0 then
-- report "STD_LOGIC_1164.HREAD "
-- & "String begins with an ""_""" severity error;
-- return;
-- elsif lastu then
-- report "STD_LOGIC_1164.HREAD "
-- & "Two underscores detected in input string ""__"""
-- severity error;
-- return;
-- else
-- lastu := true;
-- end if;
-- else
-- Char2QuadBits(c, sv(4*i to 4*i+3), ok, true);
-- if not ok then
-- return;
-- end if;
-- i := i + 1;
-- lastu := false;
-- end if;
-- if i < ne then
-- read(L, c, ok);
-- end if;
-- end loop;
-- if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with "or"
-- report "STD_LOGIC_1164.HREAD Vector truncated"
-- severity error;
-- else
-- VALUE := sv (pad to sv'high);
-- end if;
-- end if;
-- end procedure HREAD;
procedure HWRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write (L, to_hstring (VALUE), JUSTIFIED, FIELD);
end procedure HWRITE;
-- Octal Read and Write procedures for STD_ULOGIC_VECTOR.
-- Modified from the original to be more forgiving.
procedure Char2TriBits (C : CHARACTER;
RESULT : out STD_ULOGIC_VECTOR(2 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case c is
when '0' => result := o"0"; good := true;
when '1' => result := o"1"; good := true;
when '2' => result := o"2"; good := true;
when '3' => result := o"3"; good := true;
when '4' => result := o"4"; good := true;
when '5' => result := o"5"; good := true;
when '6' => result := o"6"; good := true;
when '7' => result := o"7"; good := true;
when 'Z' => result := "ZZZ"; good := true;
when 'X' => result := "XXX"; good := true;
when others =>
assert not ISSUE_ERROR
report
"STD_LOGIC_1164.OREAD Error: Read a '" & c &
"', expected an Octal character (0-7)."
severity error;
good := false;
end case;
end procedure Char2TriBits;
procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+2)/3;
constant pad : INTEGER := ne*3 - VALUE'length;
variable sv : STD_ULOGIC_VECTOR(0 to ne*3 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
good := false;
return;
elsif c = '_' then
if i = 0 then
good := false; -- Begins with an "_"
return;
elsif lastu then
good := false; -- "__" detected
return;
else
lastu := true;
end if;
else
Char2TriBits(c, sv(3*i to 3*i+2), ok, false);
if not ok then
good := false;
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with "or"
good := false; -- vector was truncated.
else
good := true;
VALUE := sv (pad to sv'high);
end if;
else
good := true; -- read into a null array
end if;
end procedure OREAD;
procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR) is
variable c : CHARACTER;
variable ok : BOOLEAN;
constant ne : INTEGER := (VALUE'length+2)/3;
constant pad : INTEGER := ne*3 - VALUE'length;
variable sv : STD_ULOGIC_VECTOR(0 to ne*3 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
report "STD_LOGIC_1164.OREAD "
& "End of string encountered"
severity error;
return;
elsif c = '_' then
if i = 0 then
report "STD_LOGIC_1164.OREAD "
& "String begins with an ""_""" severity error;
return;
elsif lastu then
report "STD_LOGIC_1164.OREAD "
& "Two underscores detected in input string ""__"""
severity error;
return;
else
lastu := true;
end if;
else
Char2TriBits(c, sv(3*i to 3*i+2), ok, true);
if not ok then
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with "or"
report "STD_LOGIC_1164.OREAD Vector truncated"
severity error;
else
VALUE := sv (pad to sv'high);
end if;
end if;
end procedure OREAD;
procedure OWRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write (L, to_ostring(VALUE), JUSTIFIED, FIELD);
end procedure OWRITE;
-- Hex Read and Write procedures for STD_LOGIC_VECTOR
-- procedure HREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR;
-- GOOD : out BOOLEAN) is
-- variable ivalue : STD_ULOGIC_VECTOR (VALUE'range);
-- begin
-- HREAD (L => L, VALUE => ivalue, GOOD => GOOD);
-- VALUE := to_stdlogicvector (ivalue);
-- end procedure HREAD;
-- procedure HREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR) is
-- variable ivalue : STD_ULOGIC_VECTOR (VALUE'range);
-- begin
-- HREAD (L => L, VALUE => ivalue);
-- VALUE := to_stdlogicvector (ivalue);
-- end procedure HREAD;
procedure HWRITE (L : inout LINE; VALUE : in STD_LOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write (L, to_hstring(VALUE), JUSTIFIED, FIELD);
end procedure HWRITE;
-- Octal Read and Write procedures for STD_LOGIC_VECTOR
procedure OREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable ivalue : STD_ULOGIC_VECTOR (VALUE'range);
begin
OREAD (L => L, VALUE => ivalue, GOOD => GOOD);
VALUE := to_stdlogicvector (ivalue);
end procedure OREAD;
procedure OREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR) is
variable ivalue : STD_ULOGIC_VECTOR (VALUE'range);
begin
OREAD (L => L, VALUE => ivalue);
VALUE := to_stdlogicvector (ivalue);
end procedure OREAD;
procedure OWRITE (L : inout LINE; VALUE : in STD_LOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write (L, to_ostring(VALUE), JUSTIFIED, FIELD);
end procedure OWRITE;
-----------------------------------------------------------------------------
-- New string functions for vhdl-200x fast track
-----------------------------------------------------------------------------
function to_string (value : STD_ULOGIC) return STRING is
variable result : STRING (1 to 1);
begin
result (1) := MVL9_to_char (value);
return result;
end function to_string;
-------------------------------------------------------------------
-- TO_STRING (an alias called "to_bstring" is provide)
-------------------------------------------------------------------
function to_string (value : STD_ULOGIC_VECTOR) return STRING is
alias ivalue : STD_ULOGIC_VECTOR(1 to value'length) is value;
variable result : STRING(1 to value'length);
begin
if value'length < 1 then
return NUS;
else
for i in ivalue'range loop
result(i) := MVL9_to_char(iValue(i));
end loop;
return result;
end if;
end function to_string;
-------------------------------------------------------------------
-- TO_HSTRING
-------------------------------------------------------------------
function to_hstring (value : STD_ULOGIC_VECTOR) return STRING is
constant ne : INTEGER := (value'length+3)/4;
variable pad : STD_ULOGIC_VECTOR(0 to (ne*4 - value'length) - 1);
variable ivalue : STD_ULOGIC_VECTOR(0 to ne*4 - 1);
variable result : STRING(1 to ne);
variable quad : STD_ULOGIC_VECTOR(0 to 3);
begin
if value'length < 1 then
return NUS;
else
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => '0');
end if;
ivalue := pad & value;
for i in 0 to ne-1 loop
quad := To_X01Z(ivalue(4*i to 4*i+3));
case quad is
when x"0" => result(i+1) := '0';
when x"1" => result(i+1) := '1';
when x"2" => result(i+1) := '2';
when x"3" => result(i+1) := '3';
when x"4" => result(i+1) := '4';
when x"5" => result(i+1) := '5';
when x"6" => result(i+1) := '6';
when x"7" => result(i+1) := '7';
when x"8" => result(i+1) := '8';
when x"9" => result(i+1) := '9';
when x"A" => result(i+1) := 'A';
when x"B" => result(i+1) := 'B';
when x"C" => result(i+1) := 'C';
when x"D" => result(i+1) := 'D';
when x"E" => result(i+1) := 'E';
when x"F" => result(i+1) := 'F';
when "ZZZZ" => result(i+1) := 'Z';
when others => result(i+1) := 'X';
end case;
end loop;
return result;
end if;
end function to_hstring;
-------------------------------------------------------------------
-- TO_OSTRING
-------------------------------------------------------------------
function to_ostring (value : STD_ULOGIC_VECTOR) return STRING is
constant ne : INTEGER := (value'length+2)/3;
variable pad : STD_ULOGIC_VECTOR(0 to (ne*3 - value'length) - 1);
variable ivalue : STD_ULOGIC_VECTOR(0 to ne*3 - 1);
variable result : STRING(1 to ne);
variable tri : STD_ULOGIC_VECTOR(0 to 2);
begin
if value'length < 1 then
return NUS;
else
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => '0');
end if;
ivalue := pad & value;
for i in 0 to ne-1 loop
tri := To_X01Z(ivalue(3*i to 3*i+2));
case tri is
when o"0" => result(i+1) := '0';
when o"1" => result(i+1) := '1';
when o"2" => result(i+1) := '2';
when o"3" => result(i+1) := '3';
when o"4" => result(i+1) := '4';
when o"5" => result(i+1) := '5';
when o"6" => result(i+1) := '6';
when o"7" => result(i+1) := '7';
when "ZZZ" => result(i+1) := 'Z';
when others => result(i+1) := 'X';
end case;
end loop;
return result;
end if;
end function to_ostring;
function to_string (value : STD_LOGIC_VECTOR) return STRING is
begin
return to_string (to_stdulogicvector (value));
end function to_string;
function to_hstring (value : STD_LOGIC_VECTOR) return STRING is
begin
return to_hstring (to_stdulogicvector (value));
end function to_hstring;
function to_ostring (value : STD_LOGIC_VECTOR) return STRING is
begin
return to_ostring (to_stdulogicvector (value));
end function to_ostring;
-- rtl_synthesis on
function maximum (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin -- function maximum
if L > R then return L;
else return R;
end if;
end function maximum;
-- std_logic_vector output
function minimum (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin -- function minimum
if L > R then return R;
else return L;
end if;
end function minimum;
function maximum (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin -- function maximum
if L > R then return L;
else return R;
end if;
end function maximum;
-- std_logic_vector output
function minimum (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin -- function minimum
if L > R then return R;
else return L;
end if;
end function minimum;
function maximum (L, R : STD_ULOGIC) return STD_ULOGIC is
begin -- function maximum
if L > R then return L;
else return R;
end if;
end function maximum;
-- std_logic_vector output
function minimum (L, R : STD_ULOGIC) return STD_ULOGIC is
begin -- function minimum
if L > R then return R;
else return L;
end if;
end function minimum;
end package body std_logic_1164_additions; | gpl-3.0 | 5fcda6e9a672d2bfda1edf897364faec | 0.495422 | 3.931046 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/techmap/maps/inpad.vhd | 2 | 3,800 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: inpad
-- File: inpad.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: input pad with technology wrapper
------------------------------------------------------------------------------
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allpads.all;
entity inpad is
generic (tech : integer := 0; level : integer := 0;
voltage : integer := x33v; filter : integer := 0;
strength : integer := 0);
port (pad : in std_ulogic; o : out std_ulogic);
end;
architecture rtl of inpad is
begin
gen0 : if has_pads(tech) = 0 generate
o <= to_X01(pad) after 1 ns;
end generate;
xcv : if (tech = virtex) or (tech = virtex2) or (tech = spartan3) or
(tech = virtex4) or (tech = spartan3e) or (tech = virtex5)
generate
x0 : virtex_inpad generic map (level, voltage) port map (pad, o);
end generate;
axc : if (tech = axcel) or (tech = proasic) or (tech = apa3) generate
x0 : axcel_inpad generic map (level, voltage) port map (pad, o);
end generate;
atc : if (tech = atc18s) generate
x0 : atc18_inpad generic map (level, voltage) port map (pad, o);
end generate;
atcrh : if (tech = atc18rha) generate
x0 : atc18rha_inpad generic map (level, voltage) port map (pad, o);
end generate;
um : if (tech = umc) generate
x0 : umc_inpad generic map (level, voltage, filter) port map (pad, o);
end generate;
rhu : if (tech = rhumc) generate
x0 : rhumc_inpad generic map (level, voltage, filter) port map (pad, o);
end generate;
ihp : if (tech = ihp25) generate
x0 : ihp25_inpad generic map(level, voltage) port map(pad, o);
end generate;
ihprh : if (tech = ihp25rh) generate
x0 : ihp25rh_inpad generic map(level, voltage) port map(pad, o);
end generate;
rh18t : if (tech = rhlib18t) generate
x0 : rh_lib18t_inpad generic map (voltage, filter) port map(pad, o);
end generate;
ut025 : if (tech = ut25) generate
x0 : ut025crh_inpad generic map (level, voltage, filter) port map(pad, o);
end generate;
pereg : if (tech = peregrine) generate
x0 : peregrine_inpad generic map (level, voltage, filter, strength) port map(pad, o);
end generate;
eas : if (tech = easic90) generate
x0 : nextreme_inpad generic map (level, voltage) port map (pad, o);
end generate;
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity inpadv is
generic (tech : integer := 0; level : integer := 0;
voltage : integer := 0; width : integer := 1);
port (
pad : in std_logic_vector(width-1 downto 0);
o : out std_logic_vector(width-1 downto 0));
end;
architecture rtl of inpadv is
begin
v : for i in width-1 downto 0 generate
x0 : inpad generic map (tech, level, voltage) port map (pad(i), o(i));
end generate;
end;
| mit | a945f65f6a9522be83e9da4c2b96a2d3 | 0.638947 | 3.601896 | false | false | false | false |
amerc/phimii | NexTEST.vhd | 2 | 12,080 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:20:44 04/10/2014
-- Design Name:
-- Module Name: /home/amer/Nexys3/TCP/NexTEST.vhd
-- Project Name: TCP
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: NEXYS3
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY NexTEST IS
END NexTEST;
ARCHITECTURE behavior OF NexTEST IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT NEXYS3
PORT(
CLK_IN : IN std_logic;
RST : IN std_logic;
TX : OUT std_logic;
RX : IN std_logic;
PHY_RESET : OUT std_logic;
RXDV : IN std_logic;
RXER : INOUT std_logic;
RXCLK : INOUT std_logic;
RXD : INOUT std_logic_vector(3 downto 0);
TXCLK : IN std_logic;
TXD : OUT std_logic_vector(3 downto 0);
TXEN : OUT std_logic;
TXER : INOUT std_logic;
PhyCol : INOUT std_logic;
GPIO_LEDS : OUT std_logic_vector(7 downto 0);
GPIO_SWITCHES : IN std_logic_vector(7 downto 0);
GPIO_BUTTONS : IN std_logic_vector(3 downto 0);
RS232_RX : IN std_logic;
RS232_TX : OUT std_logic;
CRS : in std_logic;
fx2Clk_pin : in std_logic
);
END COMPONENT;
--Inputs
signal CLK_IN : std_logic := '0';
signal RST : std_logic := '0';
signal RX : std_logic := '0';
signal RXDV : std_logic := '0';
signal TXCLK : std_logic := '0';
signal GPIO_SWITCHES : std_logic_vector(7 downto 0) := (others => '0');
signal GPIO_BUTTONS : std_logic_vector(3 downto 0) := (others => '0');
signal RS232_RX : std_logic := '0';
--BiDirs
signal RXER : std_logic;
signal RXCLK : std_logic;
signal RXD : std_logic_vector(3 downto 0);
signal TXER : std_logic;
signal PhyCol : std_logic;
--Outputs
signal TX : std_logic;
signal PHY_RESET : std_logic;
signal TXD : std_logic_vector(3 downto 0);
signal TXEN : std_logic;
signal GPIO_LEDS : std_logic_vector(7 downto 0);
signal RS232_TX : std_logic;
signal CRS : std_logic;
signal fx2Clk_pin : std_logic;
-- Clock period definitions
constant CLK_IN_period : time := 10 ns;
constant RXCLK_period : time := 40 ns;
constant TXCLK_period : time := 40 ns;
constant fx2Clk_pin_period : time := 20.8 ns;
--
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: NEXYS3 PORT MAP (
CLK_IN => CLK_IN,
RST => RST,
TX => TX,
RX => RX,
PHY_RESET => PHY_RESET,
RXDV => RXDV,
RXER => RXER,
RXCLK => RXCLK,
RXD => RXD,
TXCLK => TXCLK,
TXD => TXD,
CRS => CRS,
TXEN => TXEN,
TXER => TXER,
PhyCol => PhyCol,
GPIO_LEDS => GPIO_LEDS,
GPIO_SWITCHES => GPIO_SWITCHES,
GPIO_BUTTONS => GPIO_BUTTONS,
RS232_RX => RS232_RX,
RS232_TX => RS232_TX,
fx2Clk_pin => fx2Clk_pin
);
-- Clock process definitions
CLK_IN_process :process
begin
CLK_IN <= '0';
wait for CLK_IN_period/2;
CLK_IN <= '1';
wait for CLK_IN_period/2;
end process;
fx2clk_process :process
begin
fx2Clk_pin <= '0';
wait for fx2Clk_pin_period/2;
fx2Clk_pin <= '1';
wait for fx2Clk_pin_period/2;
end process;
RXCLK_process :process
begin
RXCLK <= '0';
wait for RXCLK_period/2;
RXCLK <= '1';
wait for RXCLK_period/2;
end process;
TXCLK_process :process
begin
TXCLK <= '0';
wait for TXCLK_period/2;
TXCLK <= '1';
wait for TXCLK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 10 ns;
-- insert stimulus here
RST <= '0';--: IN std_logic;
RX <= '0';--: IN std_logic;
RXDV <= '1';--: IN std_logic;
RXER <= '0';--: INOUT std_logic;
RXD <= x"8";--: INOUT std_logic_vector(3 downto 0);
TXER <= '0';--: INOUT std_logic;
PhyCol <= '0';--: INOUT std_logic;
GPIO_SWITCHES <= x"da";--: IN std_logic_vector(7 downto 0);
GPIO_BUTTONS <= x"f";--: IN std_logic_vector(3 downto 0);
RS232_RX <= '0';--: IN std_logic;
wait for 40 ns;
RST <= '0';--: IN std_logic;
RX <= '1';--: IN std_logic;
RXDV <= '1';--: IN std_logic;
RXER <= '0';--: INOUT std_logic;
RXD <= x"3";--: INOUT std_logic_vector(3 downto 0);
TXER <= '0';--: INOUT std_logic;
PhyCol <= '0';--: INOUT std_logic;
GPIO_SWITCHES <= x"da";--: IN std_logic_vector(7 downto 0);
GPIO_BUTTONS <= x"b";--: IN std_logic_vector(3 downto 0);
RS232_RX <= '1';--: IN std_logic;
wait for 10 ms;
RST <= '1';--: IN std_logic;
RX <= '0';--: IN std_logic;
RXDV <= '1';--: IN std_logic;
RXER <= '0';--: INOUT std_logic;
RXD <= x"5";--: INOUT std_logic_vector(3 downto 0);
TXER <= '0';--: INOUT std_logic;
PhyCol <= '0';--: INOUT std_logic;
GPIO_SWITCHES <= x"da";--: IN std_logic_vector(7 downto 0);
GPIO_BUTTONS <= x"e";--: IN std_logic_vector(3 downto 0);
RS232_RX <= '1';--: IN std_logic;
wait for 5 ms;
RST <= '1';--: IN std_logic;
RX <= '1';--: IN std_logic;
RXDV <= '1';--: IN std_logic;
RXER <= '0';--: INOUT std_logic;
RXD <= x"d";--: INOUT std_logic_vector(3 downto 0);
TXER <= '0';--: INOUT std_logic;
PhyCol <= '0';--: INOUT std_logic;
GPIO_SWITCHES <= x"d6";--: IN std_logic_vector(7 downto 0);
GPIO_BUTTONS <= x"f";--: IN std_logic_vector(3 downto 0);
RS232_RX <= '0';--: IN std_logic;
wait for 10 ms;
RST <= '1';--: IN std_logic;
RX <= '0';--: IN std_logic;
RXDV <= '1';--: IN std_logic;
RXER <= '0';--: INOUT std_logic;
RXD <= x"0";--: INOUT std_logic_vector(3 downto 0);
TXER <= '0';--: INOUT std_logic;
PhyCol <= '0';--: INOUT std_logic;
GPIO_SWITCHES <= x"da";--: IN std_logic_vector(7 downto 0);
GPIO_BUTTONS <= x"2";--: IN std_logic_vector(3 downto 0);
RS232_RX <= '1';--: IN std_logic;
wait for 10 ms;
RST <= '1';--: IN std_logic;
RX <= '0';--: IN std_logic;
RXDV <= '1';--: IN std_logic;
RXER <= '0';--: INOUT std_logic;
RXD <= x"1";--: INOUT std_logic_vector(3 downto 0);
TXER <= '0';--: INOUT std_logic;
PhyCol <= '0';--: INOUT std_logic;
GPIO_SWITCHES <= x"da";--: IN std_logic_vector(7 downto 0);
GPIO_BUTTONS <= x"0";--: IN std_logic_vector(3 downto 0);
RS232_RX <= '1';--: IN std_logic;
wait for 10 ms;
RST <= '0';--: IN std_logic;
RX <= '0';--: IN std_logic;
RXDV <= '1';--: IN std_logic;
RXER <= '0';--: INOUT std_logic;
RXD <= x"5";--: INOUT std_logic_vector(3 downto 0);
TXER <= '0';--: INOUT std_logic;
PhyCol <= '0';--: INOUT std_logic;
GPIO_SWITCHES <= x"da";--: IN std_logic_vector(7 downto 0);
GPIO_BUTTONS <= x"e";--: IN std_logic_vector(3 downto 0);
RS232_RX <= '1';--: IN std_logic;
wait for 5 ms;
RST <= '0';--: IN std_logic;
RX <= '1';--: IN std_logic;
RXDV <= '1';--: IN std_logic;
RXER <= '0';--: INOUT std_logic;
RXD <= x"d";--: INOUT std_logic_vector(3 downto 0);
TXER <= '0';--: INOUT std_logic;
PhyCol <= '0';--: INOUT std_logic;
GPIO_SWITCHES <= x"d6";--: IN std_logic_vector(7 downto 0);
GPIO_BUTTONS <= x"f";--: IN std_logic_vector(3 downto 0);
RS232_RX <= '0';--: IN std_logic;
wait for 10 ms;
RST <= '0';--: IN std_logic;
RX <= '0';--: IN std_logic;
RXDV <= '1';--: IN std_logic;
RXER <= '0';--: INOUT std_logic;
RXD <= x"0";--: INOUT std_logic_vector(3 downto 0);
TXER <= '0';--: INOUT std_logic;
PhyCol <= '0';--: INOUT std_logic;
GPIO_SWITCHES <= x"da";--: IN std_logic_vector(7 downto 0);
GPIO_BUTTONS <= x"2";--: IN std_logic_vector(3 downto 0);
RS232_RX <= '1';--: IN std_logic;
wait for 10 ms;
RST <= '1';--: IN std_logic;
RX <= '0';--: IN std_logic;
RXDV <= '1';--: IN std_logic;
RXER <= '0';--: INOUT std_logic;
RXD <= x"1";--: INOUT std_logic_vector(3 downto 0);
TXER <= '0';--: INOUT std_logic;
PhyCol <= '0';--: INOUT std_logic;
GPIO_SWITCHES <= x"da";--: IN std_logic_vector(7 downto 0);
GPIO_BUTTONS <= x"0";--: IN std_logic_vector(3 downto 0);
RS232_RX <= '1';--: IN std_logic;
wait for 10 ms;
RST <= '1';--: IN std_logic;
RX <= '0';--: IN std_logic;
RXDV <= '1';--: IN std_logic;
RXER <= '0';--: INOUT std_logic;
RXD <= x"3";--: INOUT std_logic_vector(3 downto 0);
TXER <= '0';--: INOUT std_logic;
PhyCol <= '0';--: INOUT std_logic;
GPIO_SWITCHES <= x"da";--: IN std_logic_vector(7 downto 0);
GPIO_BUTTONS <= x"e";--: IN std_logic_vector(3 downto 0);
RS232_RX <= '1';--: IN std_logic;
wait for 5 ms;
RST <= '0';--: IN std_logic;
RX <= '1';--: IN std_logic;
RXDV <= '1';--: IN std_logic;
RXER <= '0';--: INOUT std_logic;
RXD <= x"5";--: INOUT std_logic_vector(3 downto 0);
TXER <= '0';--: INOUT std_logic;
PhyCol <= '0';--: INOUT std_logic;
GPIO_SWITCHES <= x"d6";--: IN std_logic_vector(7 downto 0);
GPIO_BUTTONS <= x"f";--: IN std_logic_vector(3 downto 0);
RS232_RX <= '0';--: IN std_logic;
wait for 10 ms;
RST <= '0';--: IN std_logic;
RX <= '0';--: IN std_logic;
RXDV <= '1';--: IN std_logic;
RXER <= '0';--: INOUT std_logic;
RXD <= x"7";--: INOUT std_logic_vector(3 downto 0);
TXER <= '0';--: INOUT std_logic;
PhyCol <= '0';--: INOUT std_logic;
GPIO_SWITCHES <= x"da";--: IN std_logic_vector(7 downto 0);
GPIO_BUTTONS <= x"2";--: IN std_logic_vector(3 downto 0);
RS232_RX <= '1';--: IN std_logic;
wait for 10 ms;
RST <= '0';--: IN std_logic;
RX <= '0';--: IN std_logic;
RXDV <= '1';--: IN std_logic;
RXER <= '0';--: INOUT std_logic;
RXD <= x"8";--: INOUT std_logic_vector(3 downto 0);
TXER <= '0';--: INOUT std_logic;
PhyCol <= '0';--: INOUT std_logic;
GPIO_SWITCHES <= x"da";--: IN std_logic_vector(7 downto 0);
GPIO_BUTTONS <= x"0";--: IN std_logic_vector(3 downto 0);
RS232_RX <= '1';--: IN std_logic;
wait;
end process;
END;
| mit | d21fb4570b307d580a45b4e37b7e230a | 0.486755 | 3.322332 | false | false | false | false |
cafe-alpha/wascafe | v13/wasca_10m08sc_20191205_abus_divide/wasca_toplevel.vhd | 1 | 13,638 | -- wasca.vhd
-- Generated using ACDS version 14.1 186 at 2015.05.28.08:37:08
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity wasca_toplevel is
port (
clk_clk : in std_logic := '0'; -- Saturn clock (22.579 MHz)
external_sdram_controller_wire_addr : out std_logic_vector(12 downto 0); -- external_sdram_controller_wire.addr
external_sdram_controller_wire_ba : out std_logic_vector(1 downto 0); -- .ba
external_sdram_controller_wire_cas_n : out std_logic; -- .cas_n
external_sdram_controller_wire_cke : out std_logic; -- .cke
external_sdram_controller_wire_cs_n : out std_logic; -- .cs_n
external_sdram_controller_wire_dq : inout std_logic_vector(15 downto 0) := (others => '0'); -- .dq
external_sdram_controller_wire_dqm : out std_logic_vector(1 downto 0); -- .dqm
external_sdram_controller_wire_ras_n : out std_logic; -- .ras_n
external_sdram_controller_wire_we_n : out std_logic; -- .we_n
external_sdram_clk_pin : out std_logic; -- .clk
reset_reset_n : in std_logic := '0'; -- Saturn reset, power on.
abus_slave_0_abus_address : in std_logic_vector(24 downto 16) := (others => '0'); -- abus_slave_0_abus.address
abus_slave_0_abus_addressdata : inout std_logic_vector(15 downto 0) := (others => '0'); -- .data
abus_slave_0_abus_chipselect : in std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
abus_slave_0_abus_read : in std_logic := '0'; -- .read
abus_slave_0_abus_write : in std_logic_vector(1 downto 0) := (others => '0'); -- .write
abus_slave_0_abus_waitrequest : out std_logic; -- .waitrequest
abus_slave_0_abus_interrupt : out std_logic := '0'; -- .interrupt
abus_slave_0_abus_disableout : out std_logic := '0'; -- .muxing
abus_slave_0_abus_muxing : out std_logic_vector(1 downto 0) := (others => '0'); -- .muxing
abus_slave_0_abus_direction : out std_logic := '0'; -- .direction
--spi_sd_card_MISO : in std_logic := '0'; -- MISO
--spi_sd_card_MOSI : out std_logic; -- MOSI
--spi_sd_card_SCLK : out std_logic; -- SCLK
--spi_sd_card_SS_n : out std_logic; -- SS_n
uart_0_external_connection_txd : out std_logic := '0'; --
uart_0_external_connection_rxd : in std_logic := 'X'; --
leds_conn_export : out std_logic_vector(2 downto 0); -- leds_conn_export[0]: ledr1, leds_conn_export[1]: ledg1, leds_conn_export[2]: ledr2
switches_conn_export : in std_logic_vector(2 downto 0) -- switches_conn_export[0]: sw1, switches_conn_export[1]: sw2, switches_conn_export[2]: STM32 SPI synchronization
--spi_stm32_MISO : in std_logic; -- MISO
--spi_stm32_MOSI : out std_logic := '0'; -- MOSI
--spi_stm32_SCLK : out std_logic := '0'; -- SCLK
--spi_stm32_SS_n : out std_logic := '0' -- SS_n
--audio_out_BCLK : in std_logic := '0'; -- BCLK
--audio_out_DACDAT : out std_logic; -- DACDAT
--audio_out_DACLRCK : in std_logic := '0'; -- DACLRCK
--audio_SSEL : out std_logic := '0'
);
end entity wasca_toplevel;
architecture rtl of wasca_toplevel is
component wasca is
port (
sdram_clkout_clk : out std_logic; -- clk
altpll_0_areset_conduit_export : in std_logic := '0'; -- altpll_0_areset_conduit.export
altpll_0_locked_conduit_export : out std_logic; -- altpll_0_locked_conduit.export
altpll_0_phasedone_conduit_export : out std_logic; -- altpll_0_phasedone_conduit.export
clk_clk : in std_logic := '0'; -- clk.clk
external_sdram_controller_wire_addr : out std_logic_vector(12 downto 0); -- external_sdram_controller_wire.addr
external_sdram_controller_wire_ba : out std_logic_vector( 1 downto 0); -- .ba
external_sdram_controller_wire_cas_n : out std_logic; -- .cas_n
external_sdram_controller_wire_cke : out std_logic; -- .cke
external_sdram_controller_wire_cs_n : out std_logic; -- .cs_n
external_sdram_controller_wire_dq : inout std_logic_vector(15 downto 0) := (others => '0'); -- .dq
external_sdram_controller_wire_dqm : out std_logic_vector( 1 downto 0); -- .dqm
external_sdram_controller_wire_ras_n : out std_logic; -- .ras_n
external_sdram_controller_wire_we_n : out std_logic; -- .we_n
abus_slave_0_abus_address : in std_logic_vector( 8 downto 0) := (others => '0'); -- abus_slave_0_abus.address
abus_slave_0_abus_chipselect : in std_logic_vector( 2 downto 0) := (others => '0'); -- .chipselect
abus_slave_0_abus_read : in std_logic := '0'; -- .read
abus_slave_0_abus_write : in std_logic_vector( 1 downto 0) := (others => '0'); -- .write
abus_slave_0_abus_waitrequest : out std_logic; -- .waitrequest
abus_slave_0_abus_interrupt : out std_logic := '0'; -- .interrupt
abus_slave_0_abus_addressdata : inout std_logic_vector(15 downto 0) := (others => '0'); -- .writedata
abus_slave_0_abus_direction : out std_logic := '0';
abus_slave_0_abus_muxing : out std_logic_vector( 1 downto 0) := (others => '0');
abus_slave_0_abus_disableout : out std_logic := '0' ; -- .muxing
abus_slave_0_conduit_saturn_reset_saturn_reset : in std_logic := '0'; -- saturn_reset
--spi_sd_card_MISO : in std_logic := '0'; -- MISO
--spi_sd_card_MOSI : out std_logic; -- MOSI
--spi_sd_card_SCLK : out std_logic; -- SCLK
--spi_sd_card_SS_n : out std_logic; -- SS_n
uart_0_external_connection_rxd : in std_logic := '0'; -- rxd
uart_0_external_connection_txd : out std_logic; -- txd
leds_conn_export : out std_logic_vector(2 downto 0);
switches_conn_export : in std_logic_vector(2 downto 0)
--spi_stm32_MISO : in std_logic := '0'; -- MISO
--spi_stm32_MOSI : out std_logic := '0'; -- MOSI
--spi_stm32_SCLK : out std_logic := '0'; -- SCLK
--spi_stm32_SS_n : out std_logic := '0' -- SS_n
--audio_out_BCLK : in std_logic := '0'; -- BCLK
--audio_out_DACDAT : out std_logic; -- DACDAT
--audio_out_DACLRCK : in std_logic := '0' -- DACLRCK
);
end component;
--signal altpll_0_areset_conduit_export : std_logic := '0';
signal altpll_0_locked_conduit_export : std_logic := '0';
--signal altpll_0_phasedone_conduit_export : std_logic := '0';
--signal abus_slave_0_abus_address_demuxed : std_logic_vector(25 downto 0) := (others => '0');
--signal abus_slave_0_abus_data_demuxed : std_logic_vector(15 downto 0) := (others => '0');
begin
--abus_slave_0_abus_muxing (0) <= not abus_slave_0_abus_muxing(1);
my_little_wasca : component wasca
port map (
clk_clk => clk_clk,
external_sdram_controller_wire_addr => external_sdram_controller_wire_addr,
external_sdram_controller_wire_ba => external_sdram_controller_wire_ba,
external_sdram_controller_wire_cas_n => external_sdram_controller_wire_cas_n,
external_sdram_controller_wire_cke => external_sdram_controller_wire_cke,
external_sdram_controller_wire_cs_n => external_sdram_controller_wire_cs_n,
external_sdram_controller_wire_dq => external_sdram_controller_wire_dq,
external_sdram_controller_wire_dqm => external_sdram_controller_wire_dqm,
external_sdram_controller_wire_ras_n => external_sdram_controller_wire_ras_n,
external_sdram_controller_wire_we_n => external_sdram_controller_wire_we_n,
abus_slave_0_abus_address => abus_slave_0_abus_address,
--abus_slave_0_abus_chipselect => "1"&abus_slave_0_abus_chipselect(1 downto 0),--work only with CS1 and CS0 for now
abus_slave_0_abus_chipselect => abus_slave_0_abus_chipselect,
abus_slave_0_abus_read => abus_slave_0_abus_read,
abus_slave_0_abus_write => abus_slave_0_abus_write,
abus_slave_0_abus_waitrequest => abus_slave_0_abus_waitrequest,
abus_slave_0_abus_interrupt => abus_slave_0_abus_interrupt,
abus_slave_0_abus_addressdata => abus_slave_0_abus_addressdata,
abus_slave_0_abus_direction => abus_slave_0_abus_direction,
abus_slave_0_abus_muxing => abus_slave_0_abus_muxing,
abus_slave_0_abus_disableout => abus_slave_0_abus_disableout,
abus_slave_0_conduit_saturn_reset_saturn_reset => reset_reset_n,
--spi_sd_card_MISO => spi_sd_card_MISO,
--spi_sd_card_MOSI => spi_sd_card_MOSI,
--spi_sd_card_SCLK => spi_sd_card_SCLK,
--spi_sd_card_SS_n => spi_sd_card_SS_n,
sdram_clkout_clk => external_sdram_clk_pin,
altpll_0_areset_conduit_export => open,
altpll_0_locked_conduit_export => altpll_0_locked_conduit_export,
altpll_0_phasedone_conduit_export => open,
uart_0_external_connection_rxd => uart_0_external_connection_rxd,
uart_0_external_connection_txd => uart_0_external_connection_txd,
leds_conn_export => leds_conn_export,
switches_conn_export => switches_conn_export
--spi_stm32_MISO => spi_stm32_MISO,
--spi_stm32_MOSI => spi_stm32_MOSI,
--spi_stm32_SCLK => spi_stm32_SCLK,
--spi_stm32_SS_n => spi_stm32_SS_n
--audio_out_BCLK => audio_out_BCLK,
--audio_out_DACDAT => audio_out_DACDAT,
--audio_out_DACLRCK => audio_out_DACLRCK
);
--audio_SSEL <= '0';
--abus_slave_0_abus_waitrequest <= '1';
--abus_slave_0_abus_direction <= '0';
--abus_slave_0_abus_muxing <= "01";
end architecture rtl; -- of wasca_toplevel
| gpl-2.0 | 99fa47e661d590451268b50e87adf4d7 | 0.435548 | 4.014719 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/techmap/maps/syncram_2p.vhd | 2 | 6,732 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: syncram_2p
-- File: syncram_2p.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: syncronous 2-port ram with tech selection
------------------------------------------------------------------------------
library ieee;
library techmap;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use work.allmem.all;
entity syncram_2p is
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8;
sepclk : integer := 0; wrfst : integer := 0);
port (
rclk : in std_ulogic;
renable : in std_ulogic;
raddress : in std_logic_vector((abits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
wclk : in std_ulogic;
write : in std_ulogic;
waddress : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
testin : in std_logic_vector(3 downto 0) := "0000");
end;
architecture rtl of syncram_2p is
signal vcc, gnd : std_ulogic;
signal vgnd : std_logic_vector(dbits-1 downto 0);
signal diagin : std_logic_vector(3 downto 0);
begin
vcc <= '1'; gnd <= '0'; vgnd <= (others => '0');
diagin <= (others => '0');
inf : if tech = inferred generate
x0 : generic_syncram_2p generic map (abits, dbits, sepclk)
port map (rclk, wclk, raddress, waddress, datain, write, dataout);
end generate;
xcv : if tech = virtex generate
x0 : virtex_syncram_dp generic map (abits, dbits)
port map (wclk, waddress, datain, open, write, write,
rclk, raddress, vgnd, dataout, renable, gnd);
end generate;
xc2v : if (tech = virtex2) or (tech = spartan3) or (tech =virtex4)
or (tech = spartan3e) or (tech = virtex5)
generate
x0 : virtex2_syncram_2p generic map (abits, dbits, sepclk, wrfst)
port map (rclk, renable, raddress, dataout, wclk,
write, waddress, datain);
end generate;
vir : if tech = memvirage generate
d39 : if dbits = 39 generate
x0 : virage_syncram_2p generic map (abits, dbits, sepclk)
port map (rclk, renable, raddress, dataout,
wclk, write, waddress, datain);
end generate;
d32 : if dbits <= 32 generate
x0 : virage_syncram_dp generic map (abits, dbits)
port map (wclk, waddress, datain, open, write, write,
rclk, raddress, vgnd, dataout, renable, gnd);
end generate;
end generate;
atrh : if tech = atc18rha generate
x0 : atc18rha_syncram_2p generic map (abits, dbits, sepclk)
port map (rclk, renable, raddress, dataout,
wclk, write, waddress, datain, testin);
end generate;
axc : if tech = axcel generate
x0 : axcel_syncram_2p generic map (abits, dbits)
port map (rclk, renable, raddress, dataout,
wclk, waddress, datain, write);
end generate;
proa : if tech = proasic generate
x0 : proasic_syncram_2p generic map (abits, dbits)
port map (rclk, renable, raddress, dataout,
wclk, waddress, datain, write);
end generate;
proa3 : if tech = apa3 generate
x0 : proasic3_syncram_2p generic map (abits, dbits)
port map (rclk, renable, raddress, dataout,
wclk, waddress, datain, write);
end generate;
ihp : if tech = ihp25 generate
x0 : generic_syncram_2p generic map (abits, dbits, sepclk)
port map (rclk, wclk, raddress, waddress, datain, write, dataout);
end generate;
-- NOTE: port 1 on altsyncram must be a read port due to Cyclone II M4K write issue
alt : if (tech = altera) or (tech = stratix1) or (tech = stratix2) or
(tech = stratix3) or (tech = cyclone3) generate
x0 : altera_syncram_dp generic map (abits, dbits)
port map (rclk, raddress, vgnd, dataout, renable, gnd,
wclk, waddress, datain, open, write, write);
end generate;
rh_lib18t0 : if tech = rhlib18t generate
x0 : rh_lib18t_syncram_2p generic map (abits, dbits)
port map (rclk, renable, raddress, dataout, write, waddress, datain, diagin);
end generate;
lat : if tech = lattice generate
x0 : ec_syncram_dp generic map (abits, dbits)
port map (wclk, waddress, datain, open, write, write,
rclk, raddress, vgnd, dataout, renable, gnd);
end generate;
ut025 : if tech = ut25 generate
x0 : ut025crh_syncram_2p generic map (abits, dbits)
port map (rclk, renable, raddress, dataout,
wclk, waddress, datain, write);
end generate;
arti : if tech = memartisan generate
x0 : artisan_syncram_2p generic map (abits, dbits)
port map (rclk, renable, raddress, dataout,
wclk, write, waddress, datain);
end generate;
cust1 : if tech = custom1 generate
x0 : custom1_syncram_2p generic map (abits, dbits)
port map (rclk, renable, raddress, dataout,
wclk, write, waddress, datain);
end generate;
ecl : if tech = eclipse generate
x0 : eclipse_syncram_2p generic map (abits, dbits)
port map (rclk, renable, raddress, dataout,
wclk, waddress, datain, write);
end generate;
vir90 : if tech = memvirage90 generate
x0 : virage90_syncram_dp generic map (abits, dbits)
port map (wclk, waddress, datain, open, write, write,
rclk, raddress, vgnd, dataout, renable, gnd);
end generate;
nex : if tech = easic90 generate
x0 : nextreme_syncram_2p generic map (abits, dbits)
port map (rclk, renable, raddress, dataout,
wclk, write, waddress, datain);
end generate;
-- pragma translate_off
noram : if has_2pram(tech) = 0 generate
x : process
begin
assert false report "synram_2p: technology " & tech_table(tech) &
" not supported"
severity failure;
wait;
end process;
end generate;
-- pragma translate_on
end;
| mit | cd22902fb5f0473788d34530bf3e9199 | 0.630867 | 3.812005 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/cypress/ssram/components.vhd | 2 | 6,172 | ----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- See the file COPYING for the full details of the license.
--
-----------------------------------------------------------------------------
-- Package: components
-- File: components.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: Component declaration of Cypress sync-sram
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
package components is
component cy7c1354
generic (
fname : string := "sram.srec"; -- File to read from
-- Constant parameters
addr_bits : INTEGER := 18;
data_bits : INTEGER := 36;
-- Timing parameters for -5 (225 Mhz)
tCYC : TIME := 4.4 ns;
tCH : TIME := 1.8 ns;
tCL : TIME := 1.8 ns;
tCO : TIME := 2.8 ns;
tAS : TIME := 1.4 ns;
tCENS : TIME := 1.4 ns;
tWES : TIME := 1.4 ns;
tDS : TIME := 1.4 ns;
tAH : TIME := 0.4 ns;
tCENH : TIME := 0.4 ns;
tWEH : TIME := 0.4 ns;
tDH : TIME := 0.4 ns
-- Timing parameters for -5 (200 Mhz)
--tCYC : TIME := 5.0 ns;
--tCH : TIME := 2.0 ns;
--tCL : TIME := 2.0 ns;
--tCO : TIME := 3.2 ns;
--tAS : TIME := 1.5 ns;
--tCENS : TIME := 1.5 ns;
--tWES : TIME := 1.5 ns;
--tDS : TIME := 1.5 ns;
--tAH : TIME := 0.5 ns;
--tCENH : TIME := 0.5 ns;
--tWEH : TIME := 0.5 ns;
--tDH : TIME := 0.5 ns
-- Timing parameters for -5 (166 Mhz)
--tCYC : TIME := 6.0 ns;
--tCH : TIME := 2.4 ns;
--tCL : TIME := 2.4 ns;
--tCO : TIME := 3.5 ns;
--tAS : TIME := 1.5 ns;
--tCENS : TIME := 1.5 ns;
--tWES : TIME := 1.5 ns;
--tDS : TIME := 1.5 ns;
--tAH : TIME := 0.5 ns;
--tCENH : TIME := 0.5 ns;
--tWEH : TIME := 0.5 ns;
--tDH : TIME := 0.5 ns
);
-- Port Declarations
PORT (
Dq : INOUT STD_LOGIC_VECTOR ((data_bits - 1) DOWNTO 0); -- Data I/O
Addr : IN STD_LOGIC_VECTOR ((addr_bits - 1) DOWNTO 0); -- Address
Mode : IN STD_LOGIC := '1'; -- Burst Mode
Clk : IN STD_LOGIC; -- Clk
CEN_n : IN STD_LOGIC; -- CEN#
AdvLd_n : IN STD_LOGIC; -- Adv/Ld#
Bwa_n : IN STD_LOGIC; -- Bwa#
Bwb_n : IN STD_LOGIC; -- BWb#
Bwc_n : IN STD_LOGIC; -- Bwc#
Bwd_n : IN STD_LOGIC; -- BWd#
Rw_n : IN STD_LOGIC; -- RW#
Oe_n : IN STD_LOGIC; -- OE#
Ce1_n : IN STD_LOGIC; -- CE1#
Ce2 : IN STD_LOGIC; -- CE2
Ce3_n : IN STD_LOGIC; -- CE3#
Zz : IN STD_LOGIC -- Snooze Mode
);
end component;
component CY7C1380D
GENERIC (
fname : string := "sram.srec"; -- File to read from
-- Constant Parameters
addr_bits : INTEGER := 19; -- This is external address
data_bits : INTEGER := 36;
--Clock timings for 250Mhz
Cyp_tCO : TIME := 2.6 ns; -- Data Output Valid After CLK Rise
Cyp_tCYC : TIME := 4.0 ns; -- Clock cycle time
Cyp_tCH : TIME := 1.7 ns; -- Clock HIGH time
Cyp_tCL : TIME := 1.7 ns; -- Clock LOW time
Cyp_tCHZ : TIME := 2.6 ns; -- Clock to High-Z
Cyp_tCLZ : TIME := 1.0 ns; -- Clock to Low-Z
Cyp_tOEHZ : TIME := 2.6 ns; -- OE# HIGH to Output High-Z
Cyp_tOELZ : TIME := 0.0 ns; -- OE# LOW to Output Low-Z
Cyp_tOEV : TIME := 2.6 ns; -- OE# LOW to Output Valid
Cyp_tAS : TIME := 1.2 ns; -- Address Set-up Before CLK Rise
Cyp_tADS : TIME := 1.2 ns; -- ADSC#, ADSP# Set-up Before CLK Rise
Cyp_tADVS : TIME := 1.2 ns; -- ADV# Set-up Before CLK Rise
Cyp_tWES : TIME := 1.2 ns; -- BWx#, GW#, BWE# Set-up Before CLK Rise
Cyp_tDS : TIME := 1.2 ns; -- Data Input Set-up Before CLK Rise
Cyp_tCES : TIME := 1.2 ns; -- Chip Enable Set-up
Cyp_tAH : TIME := 0.3 ns; -- Address Hold After CLK Rise
Cyp_tADH : TIME := 0.3 ns; -- ADSC#, ADSP# Hold After CLK Rise
Cyp_tADVH : TIME := 0.3 ns; -- ADV# Hold After CLK Rise
Cyp_tWEH : TIME := 0.3 ns; -- BWx#, GW#, BWE# Hold After CLK Rise
Cyp_tDH : TIME := 0.3 ns; -- Data Input Hold After CLK Rise
Cyp_tCEH : TIME := 0.3 ns -- Chip Enable Hold After CLK Rise
);
PORT (iZZ : IN STD_LOGIC;
iMode : IN STD_LOGIC;
iADDR : IN STD_LOGIC_VECTOR ((addr_bits -1) downto 0);
inGW : IN STD_LOGIC;
inBWE : IN STD_LOGIC;
inBWd : IN STD_LOGIC;
inBWc : IN STD_LOGIC;
inBWb : IN STD_LOGIC;
inBWa : IN STD_LOGIC;
inCE1 : IN STD_LOGIC;
iCE2 : IN STD_LOGIC;
inCE3 : IN STD_LOGIC;
inADSP : IN STD_LOGIC;
inADSC : IN STD_LOGIC;
inADV : IN STD_LOGIC;
inOE : IN STD_LOGIC;
ioDQ : INOUT STD_LOGIC_VECTOR ((data_bits-1) downto 0);
iCLK : IN STD_LOGIC);
end component;
end;
-- pragma translate_on
| mit | 1f046ea17c906f80c64ada838e372164 | 0.43908 | 3.378216 | false | false | false | false |
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