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impedimentToProgress/UCI-BlueChip | AttackFiles/Defense/iu3PrivEscMux.vhd | 1 | 108,380 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008, 2009, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: iu3
-- File: iu3.vhd
-- Author: Jiri Gaisler, Edvin Catovic, Gaisler Research
-- Description: LEON3 7-stage integer pipline
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.sparc.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.leon3.all;
use gaisler.libiu.all;
use gaisler.arith.all;
-- pragma translate_off
use grlib.sparc_disas.all;
-- pragma translate_on
entity iu3 is
generic (
nwin : integer range 2 to 32 := 8;
isets : integer range 1 to 4 := 2;
dsets : integer range 1 to 4 := 2;
fpu : integer range 0 to 15 := 0;
v8 : integer range 0 to 63 := 2;
cp, mac : integer range 0 to 1 := 0;
dsu : integer range 0 to 1 := 1;
nwp : integer range 0 to 4 := 2;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
index : integer range 0 to 15:= 0;
lddel : integer range 1 to 2 := 1;
irfwt : integer range 0 to 1 := 0;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 2; -- trace buf size in kB (0 - no trace buffer)
pwd : integer range 0 to 2 := 0; -- power-down
svt : integer range 0 to 1 := 0; -- single-vector trapping
rstaddr : integer := 16#00000#; -- reset vector MSB address
smp : integer range 0 to 15 := 0; -- support SMP systems
fabtech : integer range 0 to NTECH := 20;
clk2x : integer := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
holdn : in std_ulogic;
ici : out icache_in_type;
ico : in icache_out_type;
dci : out dcache_in_type;
dco : in dcache_out_type;
rfi : out iregfile_in_type;
rfo : in iregfile_out_type;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
muli : out mul32_in_type;
mulo : in mul32_out_type;
divi : out div32_in_type;
divo : in div32_out_type;
fpo : in fpc_out_type;
fpi : out fpc_in_type;
cpo : in fpc_out_type;
cpi : out fpc_in_type;
tbo : in tracebuf_out_type;
tbi : out tracebuf_in_type;
sclk : in std_ulogic
);
end;
architecture rtl of iu3 is
constant ISETMSB : integer := 0;
constant DSETMSB : integer := 0;
constant RFBITS : integer range 6 to 10 := 8;
constant NWINLOG2 : integer range 1 to 5 := 3;
constant CWPOPT : boolean := true;
constant CWPMIN : std_logic_vector(2 downto 0) := "000";
constant CWPMAX : std_logic_vector(2 downto 0) := "111";
constant FPEN : boolean := (fpu /= 0);
constant CPEN : boolean := false;
constant MULEN : boolean := true;
constant MULTYPE: integer := 0;
constant DIVEN : boolean := true;
constant MACEN : boolean := false;
constant MACPIPE: boolean := false;
constant IMPL : integer := 15;
constant VER : integer := 3;
constant DBGUNIT : boolean := true;
constant TRACEBUF : boolean := true;
constant TBUFBITS : integer := 7;
constant PWRD1 : boolean := false; --(pwd = 1) and not (index /= 0);
constant PWRD2 : boolean := false; --(pwd = 2) or (index /= 0);
constant RS1OPT : boolean := true;
constant DYNRST : boolean := false;
subtype word is std_logic_vector(31 downto 0);
subtype pctype is std_logic_vector(31 downto 2);
subtype rfatype is std_logic_vector(8-1 downto 0);
subtype cwptype is std_logic_vector(3-1 downto 0);
type icdtype is array (0 to 2-1) of word;
type dcdtype is array (0 to 2-1) of word;
type dc_in_type is record
signed, enaddr, read, write, lock , dsuen : std_ulogic;
size : std_logic_vector(1 downto 0);
asi : std_logic_vector(7 downto 0);
end record;
type pipeline_ctrl_type is record
pc : pctype;
inst : word;
cnt : std_logic_vector(1 downto 0);
rd : rfatype;
tt : std_logic_vector(5 downto 0);
trap : std_ulogic;
annul : std_ulogic;
wreg : std_ulogic;
wicc : std_ulogic;
wy : std_ulogic;
ld : std_ulogic;
pv : std_ulogic;
rett : std_ulogic;
end record;
type fetch_reg_type is record
pc : pctype;
branch : std_ulogic;
end record;
type decode_reg_type is record
pc : pctype;
inst : icdtype;
cwp : cwptype;
set : std_logic_vector(0 downto 0);
mexc : std_ulogic;
cnt : std_logic_vector(1 downto 0);
pv : std_ulogic;
annul : std_ulogic;
inull : std_ulogic;
step : std_ulogic;
end record;
type regacc_reg_type is record
ctrl : pipeline_ctrl_type;
rs1 : std_logic_vector(4 downto 0);
rfa1, rfa2 : rfatype;
rsel1, rsel2 : std_logic_vector(2 downto 0);
rfe1, rfe2 : std_ulogic;
cwp : cwptype;
imm : word;
ldcheck1 : std_ulogic;
ldcheck2 : std_ulogic;
ldchkra : std_ulogic;
ldchkex : std_ulogic;
su : std_ulogic;
et : std_ulogic;
wovf : std_ulogic;
wunf : std_ulogic;
ticc : std_ulogic;
jmpl : std_ulogic;
step : std_ulogic;
mulstart : std_ulogic;
divstart : std_ulogic;
end record;
type execute_reg_type is record
ctrl : pipeline_ctrl_type;
op1 : word;
op2 : word;
aluop : std_logic_vector(2 downto 0); -- Alu operation
alusel : std_logic_vector(1 downto 0); -- Alu result select
aluadd : std_ulogic;
alucin : std_ulogic;
ldbp1, ldbp2 : std_ulogic;
invop2 : std_ulogic;
shcnt : std_logic_vector(4 downto 0); -- shift count
sari : std_ulogic; -- shift msb
shleft : std_ulogic; -- shift left/right
ymsb : std_ulogic; -- shift left/right
rd : std_logic_vector(4 downto 0);
jmpl : std_ulogic;
su : std_ulogic;
et : std_ulogic;
cwp : cwptype;
icc : std_logic_vector(3 downto 0);
mulstep: std_ulogic;
mul : std_ulogic;
mac : std_ulogic;
end record;
type memory_reg_type is record
ctrl : pipeline_ctrl_type;
result : word;
y : word;
icc : std_logic_vector(3 downto 0);
nalign : std_ulogic;
dci : dc_in_type;
werr : std_ulogic;
wcwp : std_ulogic;
irqen : std_ulogic;
irqen2 : std_ulogic;
mac : std_ulogic;
divz : std_ulogic;
su : std_ulogic;
mul : std_ulogic;
end record;
type exception_state is (run, trap, dsu1, dsu2);
type exception_reg_type is record
ctrl : pipeline_ctrl_type;
result : word;
y : word;
icc : std_logic_vector( 3 downto 0);
annul_all : std_ulogic;
data : dcdtype;
set : std_logic_vector(0 downto 0);
mexc : std_ulogic;
dci : dc_in_type;
laddr : std_logic_vector(1 downto 0);
rstate : exception_state;
npc : std_logic_vector(2 downto 0);
intack : std_ulogic;
ipend : std_ulogic;
mac : std_ulogic;
debug : std_ulogic;
nerror : std_ulogic;
end record;
type dsu_registers is record
tt : std_logic_vector(7 downto 0);
err : std_ulogic;
tbufcnt : std_logic_vector(7-1 downto 0);
asi : std_logic_vector(7 downto 0);
crdy : std_logic_vector(2 downto 1); -- diag cache access ready
end record;
type irestart_register is record
addr : pctype;
pwd : std_ulogic;
end record;
type pwd_register_type is record
pwd : std_ulogic;
error : std_ulogic;
end record;
type special_register_type is record
cwp : cwptype; -- current window pointer
icc : std_logic_vector(3 downto 0); -- integer condition codes
tt : std_logic_vector(7 downto 0); -- trap type
tba : std_logic_vector(19 downto 0); -- trap base address
wim : std_logic_vector(8-1 downto 0); -- window invalid mask
pil : std_logic_vector(3 downto 0); -- processor interrupt level
ec : std_ulogic; -- enable CP
ef : std_ulogic; -- enable FP
ps : std_ulogic; -- previous supervisor flag
s : std_ulogic; -- supervisor flag
et : std_ulogic; -- enable traps
y : word;
asr18 : word;
svt : std_ulogic; -- enable traps
dwt : std_ulogic; -- disable write error trap
end record;
type write_reg_type is record
s : special_register_type;
result : word;
wa : rfatype;
wreg : std_ulogic;
except : std_ulogic;
end record;
type registers is record
f : fetch_reg_type;
d : decode_reg_type;
a : regacc_reg_type;
e : execute_reg_type;
m : memory_reg_type;
x : exception_reg_type;
w : write_reg_type;
end record;
type exception_type is record
pri : std_ulogic;
ill : std_ulogic;
fpdis : std_ulogic;
cpdis : std_ulogic;
wovf : std_ulogic;
wunf : std_ulogic;
ticc : std_ulogic;
end record;
type watchpoint_register is record
addr : std_logic_vector(31 downto 2); -- watchpoint address
mask : std_logic_vector(31 downto 2); -- watchpoint mask
exec : std_ulogic; -- trap on instruction
load : std_ulogic; -- trap on load
store : std_ulogic; -- trap on store
end record;
type watchpoint_registers is array (0 to 3) of watchpoint_register;
constant wpr_none : watchpoint_register := (
"000000000000000000000000000000", "000000000000000000000000000000", '0', '0', '0');
function dbgexc(r : registers; dbgi : l3_debug_in_type; trap : std_ulogic; tt : std_logic_vector(7 downto 0)) return std_ulogic is
variable dmode : std_ulogic;
begin
dmode := '0';
if (not r.x.ctrl.annul and trap) = '1' then
if (((tt = "00" & TT_WATCH) and (dbgi.bwatch = '1')) or
((dbgi.bsoft = '1') and (tt = "10000001")) or
(dbgi.btrapa = '1') or
((dbgi.btrape = '1') and not ((tt(5 downto 0) = TT_PRIV) or
(tt(5 downto 0) = TT_FPDIS) or (tt(5 downto 0) = TT_WINOF) or
(tt(5 downto 0) = TT_WINUF) or (tt(5 downto 4) = "01") or (tt(7) = '1'))) or
(((not r.w.s.et) and dbgi.berror) = '1')) then
dmode := '1';
end if;
end if;
return(dmode);
end;
function dbgerr(r : registers; dbgi : l3_debug_in_type;
tt : std_logic_vector(7 downto 0))
return std_ulogic is
variable err : std_ulogic;
begin
err := not r.w.s.et;
if (((dbgi.dbreak = '1') and (tt = ("00" & TT_WATCH))) or
((dbgi.bsoft = '1') and (tt = ("10000001")))) then
err := '0';
end if;
return(err);
end;
procedure diagwr(r : in registers;
dsur : in dsu_registers;
ir : in irestart_register;
dbg : in l3_debug_in_type;
wpr : in watchpoint_registers;
s : out special_register_type;
vwpr : out watchpoint_registers;
asi : out std_logic_vector(7 downto 0);
pc, npc : out pctype;
tbufcnt : out std_logic_vector(7-1 downto 0);
wr : out std_ulogic;
addr : out std_logic_vector(9 downto 0);
data : out word;
fpcwr : out std_ulogic) is
variable i : integer range 0 to 3;
begin
s := r.w.s; pc := r.f.pc; npc := ir.addr; wr := '0';
vwpr := wpr; asi := dsur.asi; addr := "0000000000";
data := dbg.ddata;
tbufcnt := dsur.tbufcnt; fpcwr := '0';
if (dbg.dsuen and dbg.denable and dbg.dwrite) = '1' then
case dbg.daddr(23 downto 20) is
when "0001" =>
if (dbg.daddr(16) = '1') and true then -- trace buffer control reg
tbufcnt := dbg.ddata(7-1 downto 0);
end if;
when "0011" => -- IU reg file
if dbg.daddr(12) = '0' then
wr := '1';
addr := "0000000000";
addr(8-1 downto 0) := dbg.daddr(8+1 downto 2);
else -- FPC
fpcwr := '1';
end if;
when "0100" => -- IU special registers
case dbg.daddr(7 downto 6) is
when "00" => -- IU regs Y - TBUF ctrl reg
case dbg.daddr(5 downto 2) is
when "0000" => -- Y
s.y := dbg.ddata;
when "0001" => -- PSR
s.cwp := dbg.ddata(3-1 downto 0);
s.icc := dbg.ddata(23 downto 20);
s.ec := dbg.ddata(13);
if FPEN then s.ef := dbg.ddata(12); end if;
s.pil := dbg.ddata(11 downto 8);
s.s := dbg.ddata(7);
s.ps := dbg.ddata(6);
s.et := dbg.ddata(5);
when "0010" => -- WIM
s.wim := dbg.ddata(8-1 downto 0);
when "0011" => -- TBR
s.tba := dbg.ddata(31 downto 12);
s.tt := dbg.ddata(11 downto 4);
when "0100" => -- PC
pc := dbg.ddata(31 downto 2);
when "0101" => -- NPC
npc := dbg.ddata(31 downto 2);
when "0110" => --FSR
fpcwr := '1';
when "0111" => --CFSR
when "1001" => -- ASI reg
asi := dbg.ddata(7 downto 0);
--when "1001" => -- TBUF ctrl reg
-- tbufcnt := dbg.ddata(7-1 downto 0);
when others =>
end case;
when "01" => -- ASR16 - ASR31
case dbg.daddr(5 downto 2) is
when "0001" => -- %ASR17
s.dwt := dbg.ddata(14);
s.svt := dbg.ddata(13);
when "0010" => -- %ASR18
if false then s.asr18 := dbg.ddata; end if;
when "1000" => -- %ASR24 - %ASR31
vwpr(0).addr := dbg.ddata(31 downto 2);
vwpr(0).exec := dbg.ddata(0);
when "1001" =>
vwpr(0).mask := dbg.ddata(31 downto 2);
vwpr(0).load := dbg.ddata(1);
vwpr(0).store := dbg.ddata(0);
when "1010" =>
vwpr(1).addr := dbg.ddata(31 downto 2);
vwpr(1).exec := dbg.ddata(0);
when "1011" =>
vwpr(1).mask := dbg.ddata(31 downto 2);
vwpr(1).load := dbg.ddata(1);
vwpr(1).store := dbg.ddata(0);
when "1100" =>
vwpr(2).addr := dbg.ddata(31 downto 2);
vwpr(2).exec := dbg.ddata(0);
when "1101" =>
vwpr(2).mask := dbg.ddata(31 downto 2);
vwpr(2).load := dbg.ddata(1);
vwpr(2).store := dbg.ddata(0);
when "1110" =>
vwpr(3).addr := dbg.ddata(31 downto 2);
vwpr(3).exec := dbg.ddata(0);
when "1111" => --
vwpr(3).mask := dbg.ddata(31 downto 2);
vwpr(3).load := dbg.ddata(1);
vwpr(3).store := dbg.ddata(0);
when others => --
end case;
-- disabled due to bug in XST
-- i := conv_integer(dbg.daddr(4 downto 3));
-- if dbg.daddr(2) = '0' then
-- vwpr(i).addr := dbg.ddata(31 downto 2);
-- vwpr(i).exec := dbg.ddata(0);
-- else
-- vwpr(i).mask := dbg.ddata(31 downto 2);
-- vwpr(i).load := dbg.ddata(1);
-- vwpr(i).store := dbg.ddata(0);
-- end if;
when others =>
end case;
when others =>
end case;
end if;
end;
function asr17_gen ( r : in registers) return word is
variable asr17 : word;
variable fpu2 : integer range 0 to 3;
begin
asr17 := "00000000000000000000000000000000";
asr17(31 downto 28) := conv_std_logic_vector(index, 4);
if (clk2x > 8) then
asr17(16 downto 15) := conv_std_logic_vector(clk2x-8, 2);
asr17(17) := '1';
elsif (clk2x > 0) then
asr17(16 downto 15) := conv_std_logic_vector(clk2x, 2);
end if;
asr17(14) := r.w.s.dwt;
if svt = 1 then asr17(13) := r.w.s.svt; end if;
if lddel = 2 then asr17(12) := '1'; end if;
if (fpu > 0) and (fpu < 8) then fpu2 := 1;
elsif (fpu >= 8) and (fpu < 15) then fpu2 := 3;
elsif fpu = 15 then fpu2 := 2;
else fpu2 := 0; end if;
asr17(11 downto 10) := conv_std_logic_vector(fpu2, 2);
if mac = 1 then asr17(9) := '1'; end if;
if 2 /= 0 then asr17(8) := '1'; end if;
asr17(7 downto 5) := conv_std_logic_vector(nwp, 3);
asr17(4 downto 0) := conv_std_logic_vector(8-1, 5);
return(asr17);
end;
procedure diagread(dbgi : in l3_debug_in_type;
r : in registers;
dsur : in dsu_registers;
ir : in irestart_register;
wpr : in watchpoint_registers;
dco : in dcache_out_type;
tbufo : in tracebuf_out_type;
data : out word) is
variable cwp : std_logic_vector(4 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable i : integer range 0 to 3;
begin
data := "00000000000000000000000000000000"; cwp := "00000";
cwp(3-1 downto 0) := r.w.s.cwp;
case dbgi.daddr(22 downto 20) is
when "001" => -- trace buffer
if true then
if dbgi.daddr(16) = '1' then -- trace buffer control reg
if true then data(7-1 downto 0) := dsur.tbufcnt; end if;
else
case dbgi.daddr(3 downto 2) is
when "00" => data := tbufo.data(127 downto 96);
when "01" => data := tbufo.data(95 downto 64);
when "10" => data := tbufo.data(63 downto 32);
when others => data := tbufo.data(31 downto 0);
end case;
end if;
end if;
when "011" => -- IU reg file
if dbgi.daddr(12) = '0' then
data := rfo.data1(31 downto 0);
if (dbgi.daddr(11) = '1') and (is_fpga(fabtech) = 0) then
data := rfo.data2(31 downto 0);
end if;
else data := fpo.dbg.data; end if;
when "100" => -- IU regs
case dbgi.daddr(7 downto 6) is
when "00" => -- IU regs Y - TBUF ctrl reg
case dbgi.daddr(5 downto 2) is
when "0000" =>
data := r.w.s.y;
when "0001" =>
data := conv_std_logic_vector(15, 4) & conv_std_logic_vector(3, 4) &
r.w.s.icc & "000000" & r.w.s.ec & r.w.s.ef & r.w.s.pil &
r.w.s.s & r.w.s.ps & r.w.s.et & cwp;
when "0010" =>
data(8-1 downto 0) := r.w.s.wim;
when "0011" =>
data := r.w.s.tba & r.w.s.tt & "0000";
when "0100" =>
data(31 downto 2) := r.f.pc;
when "0101" =>
data(31 downto 2) := ir.addr;
when "0110" => -- FSR
data := fpo.dbg.data;
when "0111" => -- CPSR
when "1000" => -- TT reg
data(12 downto 4) := dsur.err & dsur.tt;
when "1001" => -- ASI reg
data(7 downto 0) := dsur.asi;
when others =>
end case;
when "01" =>
if dbgi.daddr(5) = '0' then -- %ASR17
if dbgi.daddr(4 downto 2) = "001" then -- %ASR17
data := asr17_gen(r);
elsif false and dbgi.daddr(4 downto 2) = "010" then -- %ASR18
data := r.w.s.asr18;
end if;
else -- %ASR24 - %ASR31
i := conv_integer(dbgi.daddr(4 downto 3)); --
if dbgi.daddr(2) = '0' then
data(31 downto 2) := wpr(i).addr;
data(0) := wpr(i).exec;
else
data(31 downto 2) := wpr(i).mask;
data(1) := wpr(i).load;
data(0) := wpr(i).store;
end if;
end if;
when others =>
end case;
when "111" =>
data := r.x.data(conv_integer(r.x.set));
when others =>
end case;
end;
procedure itrace(r : in registers;
dsur : in dsu_registers;
vdsu : in dsu_registers;
res : in word;
exc : in std_ulogic;
dbgi : in l3_debug_in_type;
error : in std_ulogic;
trap : in std_ulogic;
tbufcnt : out std_logic_vector(7-1 downto 0);
di : out tracebuf_in_type) is
variable meminst : std_ulogic;
begin
di.addr := (others => '0'); di.data := (others => '0');
di.enable := '0'; di.write := (others => '0');
tbufcnt := vdsu.tbufcnt;
meminst := r.x.ctrl.inst(31) and r.x.ctrl.inst(30);
if true then
di.addr(7-1 downto 0) := dsur.tbufcnt;
di.data(127) := '0';
di.data(126) := not r.x.ctrl.pv;
di.data(125 downto 96) := dbgi.timer(29 downto 0);
di.data(95 downto 64) := res;
di.data(63 downto 34) := r.x.ctrl.pc(31 downto 2);
di.data(33) := trap;
di.data(32) := error;
di.data(31 downto 0) := r.x.ctrl.inst;
if (dbgi.tenable = '0') or (r.x.rstate = dsu2) then
if ((dbgi.dsuen and dbgi.denable) = '1') and (dbgi.daddr(23 downto 20) & dbgi.daddr(16) = "00010") then
di.enable := '1';
di.addr(7-1 downto 0) := dbgi.daddr(7-1+4 downto 4);
if dbgi.dwrite = '1' then
case dbgi.daddr(3 downto 2) is
when "00" => di.write(3) := '1';
when "01" => di.write(2) := '1';
when "10" => di.write(1) := '1';
when others => di.write(0) := '1';
end case;
di.data := dbgi.ddata & dbgi.ddata & dbgi.ddata & dbgi.ddata;
end if;
end if;
elsif (not r.x.ctrl.annul and (r.x.ctrl.pv or meminst) and not r.x.debug) = '1' then
di.enable := '1'; di.write := (others => '1');
tbufcnt := dsur.tbufcnt + 1;
end if;
di.diag := dco.testen & "000";
if dco.scanen = '1' then di.enable := '0'; end if;
end if;
end;
procedure dbg_cache(holdn : in std_ulogic;
dbgi : in l3_debug_in_type;
r : in registers;
dsur : in dsu_registers;
mresult : in word;
dci : in dc_in_type;
mresult2 : out word;
dci2 : out dc_in_type
) is
begin
mresult2 := mresult; dci2 := dci; dci2.dsuen := '0';
if true then
if r.x.rstate = dsu2 then
dci2.asi := dsur.asi;
if (dbgi.daddr(22 downto 20) = "111") and (dbgi.dsuen = '1') then
dci2.dsuen := (dbgi.denable or r.m.dci.dsuen) and not dsur.crdy(2);
dci2.enaddr := dbgi.denable;
dci2.size := "10"; dci2.read := '1'; dci2.write := '0';
if (dbgi.denable and not r.m.dci.enaddr) = '1' then
mresult2 := (others => '0'); mresult2(19 downto 2) := dbgi.daddr(19 downto 2);
else
mresult2 := dbgi.ddata;
end if;
if dbgi.dwrite = '1' then
dci2.read := '0'; dci2.write := '1';
end if;
end if;
end if;
end if;
end;
procedure fpexack(r : in registers; fpexc : out std_ulogic) is
begin
fpexc := '0';
if FPEN then
if r.x.ctrl.tt = TT_FPEXC then fpexc := '1'; end if;
end if;
end;
procedure diagrdy(denable : in std_ulogic;
dsur : in dsu_registers;
dci : in dc_in_type;
mds : in std_ulogic;
ico : in icache_out_type;
crdy : out std_logic_vector(2 downto 1)) is
begin
crdy := dsur.crdy(1) & '0';
if dci.dsuen = '1' then
case dsur.asi(4 downto 0) is
when ASI_ITAG | ASI_IDATA | ASI_UINST | ASI_SINST =>
crdy(2) := ico.diagrdy and not dsur.crdy(2);
when ASI_DTAG | ASI_MMUSNOOP_DTAG | ASI_DDATA | ASI_UDATA | ASI_SDATA =>
crdy(1) := not denable and dci.enaddr and not dsur.crdy(1);
when others =>
crdy(2) := dci.enaddr and denable;
end case;
end if;
end;
signal r, rin : registers;
signal wpr, wprin : watchpoint_registers;
signal dsur, dsuin : dsu_registers;
signal ir, irin : irestart_register;
signal rp, rpin : pwd_register_type;
-- execute stage operations
constant EXE_AND : std_logic_vector(2 downto 0) := "000";
constant EXE_XOR : std_logic_vector(2 downto 0) := "001"; -- must be equal to EXE_PASS2
constant EXE_OR : std_logic_vector(2 downto 0) := "010";
constant EXE_XNOR : std_logic_vector(2 downto 0) := "011";
constant EXE_ANDN : std_logic_vector(2 downto 0) := "100";
constant EXE_ORN : std_logic_vector(2 downto 0) := "101";
constant EXE_DIV : std_logic_vector(2 downto 0) := "110";
constant EXE_PASS1 : std_logic_vector(2 downto 0) := "000";
constant EXE_PASS2 : std_logic_vector(2 downto 0) := "001";
constant EXE_STB : std_logic_vector(2 downto 0) := "010";
constant EXE_STH : std_logic_vector(2 downto 0) := "011";
constant EXE_ONES : std_logic_vector(2 downto 0) := "100";
constant EXE_RDY : std_logic_vector(2 downto 0) := "101";
constant EXE_SPR : std_logic_vector(2 downto 0) := "110";
constant EXE_LINK : std_logic_vector(2 downto 0) := "111";
constant EXE_SLL : std_logic_vector(2 downto 0) := "001";
constant EXE_SRL : std_logic_vector(2 downto 0) := "010";
constant EXE_SRA : std_logic_vector(2 downto 0) := "100";
constant EXE_NOP : std_logic_vector(2 downto 0) := "000";
-- EXE result select
constant EXE_RES_ADD : std_logic_vector(1 downto 0) := "00";
constant EXE_RES_SHIFT : std_logic_vector(1 downto 0) := "01";
constant EXE_RES_LOGIC : std_logic_vector(1 downto 0) := "10";
constant EXE_RES_MISC : std_logic_vector(1 downto 0) := "11";
-- Load types
constant SZBYTE : std_logic_vector(1 downto 0) := "00";
constant SZHALF : std_logic_vector(1 downto 0) := "01";
constant SZWORD : std_logic_vector(1 downto 0) := "10";
constant SZDBL : std_logic_vector(1 downto 0) := "11";
-- calculate register file address
procedure regaddr(cwp : std_logic_vector; reg : std_logic_vector(4 downto 0);
rao : out rfatype) is
variable ra : rfatype;
constant globals : std_logic_vector(8-5 downto 0) :=
conv_std_logic_vector(8, 8-4);
begin
ra := (others => '0'); ra(4 downto 0) := reg;
if reg(4 downto 3) = "00" then ra(8 -1 downto 4) := globals;
else
ra(3+3 downto 4) := cwp + ra(4);
if ra(8-1 downto 4) = globals then
ra(8-1 downto 4) := (others => '0');
end if;
end if;
rao := ra;
end;
-- branch adder
function branch_address(inst : word; pc : pctype) return std_logic_vector is
variable baddr, caddr, tmp : pctype;
begin
caddr := (others => '0'); caddr(31 downto 2) := inst(29 downto 0);
caddr(31 downto 2) := caddr(31 downto 2) + pc(31 downto 2);
baddr := (others => '0'); baddr(31 downto 24) := (others => inst(21));
baddr(23 downto 2) := inst(21 downto 0);
baddr(31 downto 2) := baddr(31 downto 2) + pc(31 downto 2);
if inst(30) = '1' then tmp := caddr; else tmp := baddr; end if;
return(tmp);
end;
-- evaluate branch condition
function branch_true(icc : std_logic_vector(3 downto 0); inst : word)
return std_ulogic is
variable n, z, v, c, branch : std_ulogic;
begin
n := icc(3); z := icc(2); v := icc(1); c := icc(0);
case inst(27 downto 25) is
when "000" => branch := inst(28) xor '0'; -- bn, ba
when "001" => branch := inst(28) xor z; -- be, bne
when "010" => branch := inst(28) xor (z or (n xor v)); -- ble, bg
when "011" => branch := inst(28) xor (n xor v); -- bl, bge
when "100" => branch := inst(28) xor (c or z); -- bleu, bgu
when "101" => branch := inst(28) xor c; -- bcs, bcc
when "110" => branch := inst(28) xor n; -- bneg, bpos
when others => branch := inst(28) xor v; -- bvs, bvc
end case;
return(branch);
end;
-- detect RETT instruction in the pipeline and set the local psr.su and psr.et
procedure su_et_select(r : in registers; xc_ps, xc_s, xc_et : in std_ulogic;
su, et : out std_ulogic) is
begin
if ((r.a.ctrl.rett or r.e.ctrl.rett or r.m.ctrl.rett or r.x.ctrl.rett) = '1')
and (r.x.annul_all = '0')
then su := xc_ps; et := '1';
else su := xc_s; et := xc_et; end if;
end;
-- detect watchpoint trap
function wphit(r : registers; wpr : watchpoint_registers; debug : l3_debug_in_type)
return std_ulogic is
variable exc : std_ulogic;
begin
exc := '0';
for i in 1 to NWP loop
if ((wpr(i-1).exec and r.a.ctrl.pv and not r.a.ctrl.annul) = '1') then
if (((wpr(i-1).addr xor r.a.ctrl.pc(31 downto 2)) and wpr(i-1).mask) = "000000000000000000000000000000") then
exc := '1';
end if;
end if;
end loop;
if true then
if (debug.dsuen and not r.a.ctrl.annul) = '1' then
exc := exc or (r.a.ctrl.pv and ((debug.dbreak and debug.bwatch) or r.a.step));
end if;
end if;
return(exc);
end;
-- 32-bit shifter
function shift3(r : registers; aluin1, aluin2 : word) return word is
variable shiftin : unsigned(63 downto 0);
variable shiftout : unsigned(63 downto 0);
variable cnt : natural range 0 to 31;
begin
cnt := conv_integer(r.e.shcnt);
if r.e.shleft = '1' then
shiftin(30 downto 0) := (others => '0');
shiftin(63 downto 31) := '0' & unsigned(aluin1);
else
shiftin(63 downto 32) := (others => r.e.sari);
shiftin(31 downto 0) := unsigned(aluin1);
end if;
shiftout := SHIFT_RIGHT(shiftin, cnt);
return(std_logic_vector(shiftout(31 downto 0)));
end;
function shift2(r : registers; aluin1, aluin2 : word) return word is
variable ushiftin : unsigned(31 downto 0);
variable sshiftin : signed(32 downto 0);
variable cnt : natural range 0 to 31;
variable resleft, resright : word;
begin
cnt := conv_integer(r.e.shcnt);
ushiftin := unsigned(aluin1);
sshiftin := signed('0' & aluin1);
if r.e.shleft = '1' then
resleft := std_logic_vector(SHIFT_LEFT(ushiftin, cnt));
return(resleft);
else
if r.e.sari = '1' then sshiftin(32) := aluin1(31); end if;
sshiftin := SHIFT_RIGHT(sshiftin, cnt);
resright := std_logic_vector(sshiftin(31 downto 0));
return(resright);
-- else
-- ushiftin := SHIFT_RIGHT(ushiftin, cnt);
-- return(std_logic_vector(ushiftin));
-- end if;
end if;
end;
function shift(r : registers; aluin1, aluin2 : word;
shiftcnt : std_logic_vector(4 downto 0); sari : std_ulogic ) return word is
variable shiftin : std_logic_vector(63 downto 0);
begin
shiftin := "00000000000000000000000000000000" & aluin1;
if r.e.shleft = '1' then
shiftin(31 downto 0) := "00000000000000000000000000000000"; shiftin(63 downto 31) := '0' & aluin1;
else shiftin(63 downto 32) := (others => sari); end if;
if shiftcnt (4) = '1' then shiftin(47 downto 0) := shiftin(63 downto 16); end if;
if shiftcnt (3) = '1' then shiftin(39 downto 0) := shiftin(47 downto 8); end if;
if shiftcnt (2) = '1' then shiftin(35 downto 0) := shiftin(39 downto 4); end if;
if shiftcnt (1) = '1' then shiftin(33 downto 0) := shiftin(35 downto 2); end if;
if shiftcnt (0) = '1' then shiftin(31 downto 0) := shiftin(32 downto 1); end if;
return(shiftin(31 downto 0));
end;
-- Check for illegal and privileged instructions
procedure exception_detect(r : registers; wpr : watchpoint_registers; dbgi : l3_debug_in_type;
trapin : in std_ulogic; ttin : in std_logic_vector(5 downto 0);
trap : out std_ulogic; tt : out std_logic_vector(5 downto 0)) is
variable illegal_inst, privileged_inst : std_ulogic;
variable cp_disabled, fp_disabled, fpop : std_ulogic;
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable inst : word;
variable wph : std_ulogic;
begin
inst := r.a.ctrl.inst; trap := trapin; tt := ttin;
if r.a.ctrl.annul = '0' then
op := inst(31 downto 30); op2 := inst(24 downto 22);
op3 := inst(24 downto 19); rd := inst(29 downto 25);
illegal_inst := '0'; privileged_inst := '0'; cp_disabled := '0';
fp_disabled := '0'; fpop := '0';
case op is
when CALL => null;
when FMT2 =>
case op2 is
when SETHI | BICC => null;
when FBFCC =>
if FPEN then fp_disabled := not r.w.s.ef; else fp_disabled := '1'; end if;
when CBCCC =>
if (not false) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when others => illegal_inst := '1';
end case;
when FMT3 =>
case op3 is
when IAND | ANDCC | ANDN | ANDNCC | IOR | ORCC | ORN | ORNCC | IXOR |
XORCC | IXNOR | XNORCC | ISLL | ISRL | ISRA | MULSCC | IADD | ADDX |
ADDCC | ADDXCC | ISUB | SUBX | SUBCC | SUBXCC | FLUSH | JMPL | TICC |
SAVE | RESTORE | RDY => null;
when TADDCC | TADDCCTV | TSUBCC | TSUBCCTV =>
if notag = 1 then illegal_inst := '1'; end if;
when UMAC | SMAC =>
if not false then illegal_inst := '1'; end if;
when UMUL | SMUL | UMULCC | SMULCC =>
if not true then illegal_inst := '1'; end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if not true then illegal_inst := '1'; end if;
when RETT => illegal_inst := r.a.et; privileged_inst := not r.a.su;
when RDPSR | RDTBR | RDWIM => privileged_inst := not r.a.su;
when WRY => null;
when WRPSR =>
privileged_inst := not r.a.su;
when WRWIM | WRTBR => privileged_inst := not r.a.su;
when FPOP1 | FPOP2 =>
if FPEN then fp_disabled := not r.w.s.ef; fpop := '1';
else fp_disabled := '1'; fpop := '0'; end if;
when CPOP1 | CPOP2 =>
if (not false) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when others => illegal_inst := '1';
end case;
when others => -- LDST
case op3 is
when LDD | ISTD => illegal_inst := rd(0); -- trap if odd destination register
when LD | LDUB | LDSTUB | LDUH | LDSB | LDSH | ST | STB | STH | SWAP =>
null;
when LDDA | STDA =>
illegal_inst := inst(13) or rd(0); privileged_inst := not r.a.su;
when LDA | LDUBA| LDSTUBA | LDUHA | LDSBA | LDSHA | STA | STBA | STHA |
SWAPA =>
illegal_inst := inst(13); privileged_inst := not r.a.su;
when LDDF | STDF | LDF | LDFSR | STF | STFSR =>
if FPEN then fp_disabled := not r.w.s.ef;
else fp_disabled := '1'; end if;
when STDFQ =>
privileged_inst := not r.a.su;
if (not FPEN) or (r.w.s.ef = '0') then fp_disabled := '1'; end if;
when STDCQ =>
privileged_inst := not r.a.su;
if (not false) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when LDC | LDCSR | LDDC | STC | STCSR | STDC =>
if (not false) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when others => illegal_inst := '1';
end case;
end case;
wph := wphit(r, wpr, dbgi);
trap := '1';
if r.a.ctrl.trap = '1' then tt := TT_IAEX;
elsif privileged_inst = '1' then tt := TT_PRIV;
elsif illegal_inst = '1' then tt := TT_IINST;
elsif fp_disabled = '1' then tt := TT_FPDIS;
elsif cp_disabled = '1' then tt := TT_CPDIS;
elsif wph = '1' then tt := TT_WATCH;
elsif r.a.wovf= '1' then tt := TT_WINOF;
elsif r.a.wunf= '1' then tt := TT_WINUF;
elsif r.a.ticc= '1' then tt := TT_TICC;
else trap := '0'; tt:= (others => '0'); end if;
end if;
end;
-- instructions that write the condition codes (psr.icc)
procedure wicc_y_gen(inst : word; wicc, wy : out std_ulogic) is
begin
wicc := '0'; wy := '0';
if inst(31 downto 30) = FMT3 then
case inst(24 downto 19) is
when SUBCC | TSUBCC | TSUBCCTV | ADDCC | ANDCC | ORCC | XORCC | ANDNCC |
ORNCC | XNORCC | TADDCC | TADDCCTV | ADDXCC | SUBXCC | WRPSR =>
wicc := '1';
when WRY =>
if r.d.inst(conv_integer(r.d.set))(29 downto 25) = "00000" then wy := '1'; end if;
when MULSCC =>
wicc := '1'; wy := '1';
when UMAC | SMAC =>
if false then wy := '1'; end if;
when UMULCC | SMULCC =>
if true and (((mulo.nready = '1') and (r.d.cnt /= "00")) or (0 /= 0)) then
wicc := '1'; wy := '1';
end if;
when UMUL | SMUL =>
if true and (((mulo.nready = '1') and (r.d.cnt /= "00")) or (0 /= 0)) then
wy := '1';
end if;
when UDIVCC | SDIVCC =>
if true and (divo.nready = '1') and (r.d.cnt /= "00") then
wicc := '1';
end if;
when others =>
end case;
end if;
end;
-- select cwp
procedure cwp_gen(r, v : registers; annul, wcwp : std_ulogic; ncwp : cwptype;
cwp : out cwptype) is
begin
if (r.x.rstate = trap) or (r.x.rstate = dsu2) or (rstn = '0') then cwp := v.w.s.cwp;
elsif (wcwp = '1') and (annul = '0') then cwp := ncwp;
elsif r.m.wcwp = '1' then cwp := r.m.result(3-1 downto 0);
else cwp := r.d.cwp; end if;
end;
-- generate wcwp in ex stage
procedure cwp_ex(r : in registers; wcwp : out std_ulogic) is
begin
if (r.e.ctrl.inst(31 downto 30) = FMT3) and
(r.e.ctrl.inst(24 downto 19) = WRPSR)
then wcwp := not r.e.ctrl.annul; else wcwp := '0'; end if;
end;
-- generate next cwp & window under- and overflow traps
procedure cwp_ctrl(r : in registers; xc_wim : in std_logic_vector(8-1 downto 0);
inst : word; de_cwp : out cwptype; wovf_exc, wunf_exc, wcwp : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable wim : word;
variable ncwp : cwptype;
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
wovf_exc := '0'; wunf_exc := '0'; wim := (others => '0');
wim(8-1 downto 0) := xc_wim; ncwp := r.d.cwp; wcwp := '0';
if (op = FMT3) and ((op3 = RETT) or (op3 = RESTORE) or (op3 = SAVE)) then
wcwp := '1';
if (op3 = SAVE) then
if (not true) and (r.d.cwp = "000") then ncwp := "111";
else ncwp := r.d.cwp - 1 ; end if;
else
if (not true) and (r.d.cwp = "111") then ncwp := "000";
else ncwp := r.d.cwp + 1; end if;
end if;
if wim(conv_integer(ncwp)) = '1' then
if op3 = SAVE then wovf_exc := '1'; else wunf_exc := '1'; end if;
end if;
end if;
de_cwp := ncwp;
end;
-- generate register read address 1
procedure rs1_gen(r : registers; inst : word; rs1 : out std_logic_vector(4 downto 0);
rs1mod : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
rs1 := inst(18 downto 14); rs1mod := '0';
if (op = LDST) then
if ((r.d.cnt = "01") and ((op3(2) and not op3(3)) = '1')) or
(r.d.cnt = "10")
then rs1mod := '1'; rs1 := inst(29 downto 25); end if;
if ((r.d.cnt = "10") and (op3(3 downto 0) = "0111")) then
rs1(0) := '1';
end if;
end if;
end;
-- load/icc interlock detection
procedure lock_gen(r : registers; rs2, rd : std_logic_vector(4 downto 0);
rfa1, rfa2, rfrd : rfatype; inst : word; fpc_lock, mulinsn, divinsn : std_ulogic;
lldcheck1, lldcheck2, lldlock, lldchkra, lldchkex : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable cond : std_logic_vector(3 downto 0);
variable rs1 : std_logic_vector(4 downto 0);
variable i, ldcheck1, ldcheck2, ldchkra, ldchkex, ldcheck3 : std_ulogic;
variable ldlock, icc_check, bicc_hold, chkmul, y_check : std_ulogic;
variable lddlock : boolean;
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
op2 := inst(24 downto 22); cond := inst(28 downto 25);
rs1 := inst(18 downto 14); lddlock := false; i := inst(13);
ldcheck1 := '0'; ldcheck2 := '0'; ldcheck3 := '0'; ldlock := '0';
ldchkra := '1'; ldchkex := '1'; icc_check := '0'; bicc_hold := '0';
y_check := '0';
if (r.d.annul = '0') then
case op is
when FMT2 =>
if (op2 = BICC) and (cond(2 downto 0) /= "000") then
icc_check := '1';
end if;
when FMT3 =>
ldcheck1 := '1'; ldcheck2 := not i;
case op3 is
when TICC =>
if (cond(2 downto 0) /= "000") then icc_check := '1'; end if;
when RDY =>
ldcheck1 := '0'; ldcheck2 := '0';
if false then y_check := '1'; end if;
when RDWIM | RDTBR =>
ldcheck1 := '0'; ldcheck2 := '0';
when RDPSR =>
ldcheck1 := '0'; ldcheck2 := '0'; icc_check := '1';
if true then icc_check := '1'; end if;
-- when ADDX | ADDXCC | SUBX | SUBXCC =>
-- if true then icc_check := '1'; end if;
when SDIV | SDIVCC | UDIV | UDIVCC =>
if true then y_check := '1'; end if;
when FPOP1 | FPOP2 => ldcheck1:= '0'; ldcheck2 := '0';
when others =>
end case;
when LDST =>
ldcheck1 := '1'; ldchkra := '0';
case r.d.cnt is
when "00" =>
if (lddel = 2) and (op3(2) = '1') then ldcheck3 := '1'; end if;
ldcheck2 := not i; ldchkra := '1';
when "01" => ldcheck2 := not i;
when others => ldchkex := '0';
end case;
if (op3(2 downto 0) = "011") then lddlock := true; end if;
when others => null;
end case;
end if;
if true or true then
chkmul := mulinsn;
bicc_hold := bicc_hold or (icc_check and r.m.ctrl.wicc and (r.m.ctrl.cnt(0) or r.m.mul));
else chkmul := '0'; end if;
if true then
bicc_hold := bicc_hold or (y_check and (r.a.ctrl.wy or r.e.ctrl.wy));
chkmul := chkmul or divinsn;
end if;
bicc_hold := bicc_hold or (icc_check and (r.a.ctrl.wicc or r.e.ctrl.wicc));
if (((r.a.ctrl.ld or chkmul) and r.a.ctrl.wreg and ldchkra) = '1') and
(((ldcheck1 = '1') and (r.a.ctrl.rd = rfa1)) or
((ldcheck2 = '1') and (r.a.ctrl.rd = rfa2)) or
((ldcheck3 = '1') and (r.a.ctrl.rd = rfrd)))
then ldlock := '1'; end if;
if (((r.e.ctrl.ld or r.e.mac) and r.e.ctrl.wreg and ldchkex) = '1') and
((lddel = 2) or (false and (r.e.mac = '1')) or ((0 = 3) and (r.e.mul = '1'))) and
(((ldcheck1 = '1') and (r.e.ctrl.rd = rfa1)) or
((ldcheck2 = '1') and (r.e.ctrl.rd = rfa2)))
then ldlock := '1'; end if;
ldlock := ldlock or bicc_hold or fpc_lock;
lldcheck1 := ldcheck1; lldcheck2:= ldcheck2; lldlock := ldlock;
lldchkra := ldchkra; lldchkex := ldchkex;
end;
procedure fpbranch(inst : in word; fcc : in std_logic_vector(1 downto 0);
branch : out std_ulogic) is
variable cond : std_logic_vector(3 downto 0);
variable fbres : std_ulogic;
begin
cond := inst(28 downto 25);
case cond(2 downto 0) is
when "000" => fbres := '0'; -- fba, fbn
when "001" => fbres := fcc(1) or fcc(0);
when "010" => fbres := fcc(1) xor fcc(0);
when "011" => fbres := fcc(0);
when "100" => fbres := (not fcc(1)) and fcc(0);
when "101" => fbres := fcc(1);
when "110" => fbres := fcc(1) and not fcc(0);
when others => fbres := fcc(1) and fcc(0);
end case;
branch := cond(3) xor fbres;
end;
-- PC generation
procedure ic_ctrl(r : registers; inst : word; annul_all, ldlock, branch_true,
fbranch_true, cbranch_true, fccv, cccv : in std_ulogic;
cnt : out std_logic_vector(1 downto 0);
de_pc : out pctype; de_branch, ctrl_annul, de_annul, jmpl_inst, inull,
de_pv, ctrl_pv, de_hold_pc, ticc_exception, rett_inst, mulstart,
divstart : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable cond : std_logic_vector(3 downto 0);
variable hold_pc, annul_current, annul_next, branch, annul, pv : std_ulogic;
variable de_jmpl : std_ulogic;
begin
branch := '0'; annul_next := '0'; annul_current := '0'; pv := '1';
hold_pc := '0'; ticc_exception := '0'; rett_inst := '0';
op := inst(31 downto 30); op3 := inst(24 downto 19);
op2 := inst(24 downto 22); cond := inst(28 downto 25);
annul := inst(29); de_jmpl := '0'; cnt := "00";
mulstart := '0'; divstart := '0';
if r.d.annul = '0' then
case inst(31 downto 30) is
when CALL =>
branch := '1';
if r.d.inull = '1' then
hold_pc := '1'; annul_current := '1';
end if;
when FMT2 =>
if (op2 = BICC) or (FPEN and (op2 = FBFCC)) or (false and (op2 = CBCCC)) then
if (FPEN and (op2 = FBFCC)) then
branch := fbranch_true;
if fccv /= '1' then hold_pc := '1'; annul_current := '1'; end if;
elsif (false and (op2 = CBCCC)) then
branch := cbranch_true;
if cccv /= '1' then hold_pc := '1'; annul_current := '1'; end if;
else branch := branch_true; end if;
if hold_pc = '0' then
if (branch = '1') then
if (cond = BA) and (annul = '1') then annul_next := '1'; end if;
else annul_next := annul; end if;
if r.d.inull = '1' then -- contention with JMPL
hold_pc := '1'; annul_current := '1'; annul_next := '0';
end if;
end if;
end if;
when FMT3 =>
case op3 is
when UMUL | SMUL | UMULCC | SMULCC =>
if true and (0 /= 0) then mulstart := '1'; end if;
if true and (0 = 0) then
case r.d.cnt is
when "00" =>
cnt := "01"; hold_pc := '1'; pv := '0'; mulstart := '1';
when "01" =>
if mulo.nready = '1' then cnt := "00";
else cnt := "01"; pv := '0'; hold_pc := '1'; end if;
when others => null;
end case;
end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if true then
case r.d.cnt is
when "00" =>
cnt := "01"; hold_pc := '1'; pv := '0';
divstart := '1';
when "01" =>
if divo.nready = '1' then cnt := "00";
else cnt := "01"; pv := '0'; hold_pc := '1'; end if;
when others => null;
end case;
end if;
when TICC =>
if branch_true = '1' then ticc_exception := '1'; end if;
when RETT =>
rett_inst := '1'; --su := sregs.ps;
when JMPL =>
de_jmpl := '1';
when WRY =>
if false then
if inst(29 downto 25) = "10011" then -- %ASR19
case r.d.cnt is
when "00" =>
pv := '0'; cnt := "00"; hold_pc := '1';
if r.x.ipend = '1' then cnt := "01"; end if;
when "01" =>
cnt := "00";
when others =>
end case;
end if;
end if;
when others => null;
end case;
when others => -- LDST
case r.d.cnt is
when "00" =>
if (op3(2) = '1') or (op3(1 downto 0) = "11") then -- ST/LDST/SWAP/LDD
cnt := "01"; hold_pc := '1'; pv := '0';
end if;
when "01" =>
if (op3(2 downto 0) = "111") or (op3(3 downto 0) = "1101") or
((false or FPEN) and ((op3(5) & op3(2 downto 0)) = "1110"))
then -- LDD/STD/LDSTUB/SWAP
cnt := "10"; pv := '0'; hold_pc := '1';
else
cnt := "00";
end if;
when "10" =>
cnt := "00";
when others => null;
end case;
end case;
end if;
if ldlock = '1' then
cnt := r.d.cnt; annul_next := '0'; pv := '1';
end if;
hold_pc := (hold_pc or ldlock) and not annul_all;
if hold_pc = '1' then de_pc := r.d.pc; else de_pc := r.f.pc; end if;
annul_current := (annul_current or ldlock or annul_all);
ctrl_annul := r.d.annul or annul_all or annul_current;
pv := pv and not ((r.d.inull and not hold_pc) or annul_all);
jmpl_inst := de_jmpl and not annul_current;
annul_next := (r.d.inull and not hold_pc) or annul_next or annul_all;
if (annul_next = '1') or (rstn = '0') then
cnt := (others => '0');
end if;
de_hold_pc := hold_pc; de_branch := branch; de_annul := annul_next;
de_pv := pv; ctrl_pv := r.d.pv and
not ((r.d.annul and not r.d.pv) or annul_all or annul_current);
inull := (not rstn) or r.d.inull or hold_pc or annul_all;
end;
-- register write address generation
procedure rd_gen(r : registers; inst : word; wreg, ld : out std_ulogic;
rdo : out std_logic_vector(4 downto 0)) is
variable write_reg : std_ulogic;
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
begin
op := inst(31 downto 30);
op2 := inst(24 downto 22);
op3 := inst(24 downto 19);
write_reg := '0'; rd := inst(29 downto 25); ld := '0';
case op is
when CALL =>
write_reg := '1'; rd := "01111"; -- CALL saves PC in r[15] (%o7)
when FMT2 =>
if (op2 = SETHI) then write_reg := '1'; end if;
when FMT3 =>
case op3 is
when UMUL | SMUL | UMULCC | SMULCC =>
if true then
if (((mulo.nready = '1') and (r.d.cnt /= "00")) or (0 /= 0)) then
write_reg := '1';
end if;
else write_reg := '1'; end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if true then
if (divo.nready = '1') and (r.d.cnt /= "00") then
write_reg := '1';
end if;
else write_reg := '1'; end if;
when RETT | WRPSR | WRY | WRWIM | WRTBR | TICC | FLUSH => null;
when FPOP1 | FPOP2 => null;
when CPOP1 | CPOP2 => null;
when others => write_reg := '1';
end case;
when others => -- LDST
ld := not op3(2);
if (op3(2) = '0') and not ((false or FPEN) and (op3(5) = '1'))
then write_reg := '1'; end if;
case op3 is
when SWAP | SWAPA | LDSTUB | LDSTUBA =>
if r.d.cnt = "00" then write_reg := '1'; ld := '1'; end if;
when others => null;
end case;
if r.d.cnt = "01" then
case op3 is
when LDD | LDDA | LDDC | LDDF => rd(0) := '1';
when others =>
end case;
end if;
end case;
if (rd = "00000") then write_reg := '0'; end if;
wreg := write_reg; rdo := rd;
end;
-- immediate data generation
function imm_data (r : registers; insn : word)
return word is
variable immediate_data, inst : word;
begin
immediate_data := (others => '0'); inst := insn;
case inst(31 downto 30) is
when FMT2 =>
immediate_data := inst(21 downto 0) & "0000000000";
when others => -- LDST
immediate_data(31 downto 13) := (others => inst(12));
immediate_data(12 downto 0) := inst(12 downto 0);
end case;
return(immediate_data);
end;
-- read special registers
function get_spr (r : registers) return word is
variable spr : word;
begin
spr := (others => '0');
case r.e.ctrl.inst(24 downto 19) is
when RDPSR => spr(31 downto 5) := conv_std_logic_vector(15,4) &
conv_std_logic_vector(3,4) & r.m.icc & "000000" & r.w.s.ec & r.w.s.ef &
r.w.s.pil & r.e.su & r.w.s.ps & r.e.et;
spr(3-1 downto 0) := r.e.cwp;
when RDTBR => spr(31 downto 4) := r.w.s.tba & r.w.s.tt;
when RDWIM => spr(8-1 downto 0) := r.w.s.wim;
when others =>
end case;
return(spr);
end;
-- immediate data select
function imm_select(inst : word) return boolean is
variable imm : boolean;
begin
imm := false;
case inst(31 downto 30) is
when FMT2 =>
case inst(24 downto 22) is
when SETHI => imm := true;
when others =>
end case;
when FMT3 =>
case inst(24 downto 19) is
when RDWIM | RDPSR | RDTBR => imm := true;
when others => if (inst(13) = '1') then imm := true; end if;
end case;
when LDST =>
if (inst(13) = '1') then imm := true; end if;
when others =>
end case;
return(imm);
end;
-- EXE operation
procedure alu_op(r : in registers; iop1, iop2 : in word; me_icc : std_logic_vector(3 downto 0);
my, ldbp : std_ulogic; aop1, aop2 : out word; aluop : out std_logic_vector(2 downto 0);
alusel : out std_logic_vector(1 downto 0); aluadd : out std_ulogic;
shcnt : out std_logic_vector(4 downto 0); sari, shleft, ymsb,
mulins, divins, mulstep, macins, ldbp2, invop2 : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable icc : std_logic_vector(3 downto 0);
variable y0 : std_ulogic;
begin
op := r.a.ctrl.inst(31 downto 30);
op2 := r.a.ctrl.inst(24 downto 22);
op3 := r.a.ctrl.inst(24 downto 19);
aop1 := iop1; aop2 := iop2; ldbp2 := ldbp;
aluop := EXE_NOP; alusel := EXE_RES_MISC; aluadd := '1';
shcnt := iop2(4 downto 0); sari := '0'; shleft := '0'; invop2 := '0';
ymsb := iop1(0); mulins := '0'; divins := '0'; mulstep := '0';
macins := '0';
if r.e.ctrl.wy = '1' then y0 := my;
elsif r.m.ctrl.wy = '1' then y0 := r.m.y(0);
elsif r.x.ctrl.wy = '1' then y0 := r.x.y(0);
else y0 := r.w.s.y(0); end if;
if r.e.ctrl.wicc = '1' then icc := me_icc;
elsif r.m.ctrl.wicc = '1' then icc := r.m.icc;
elsif r.x.ctrl.wicc = '1' then icc := r.x.icc;
else icc := r.w.s.icc; end if;
case op is
when CALL =>
aluop := EXE_LINK;
when FMT2 =>
case op2 is
when SETHI => aluop := EXE_PASS2;
when others =>
end case;
when FMT3 =>
case op3 is
when IADD | ADDX | ADDCC | ADDXCC | TADDCC | TADDCCTV | SAVE | RESTORE |
TICC | JMPL | RETT => alusel := EXE_RES_ADD;
when ISUB | SUBX | SUBCC | SUBXCC | TSUBCC | TSUBCCTV =>
alusel := EXE_RES_ADD; aluadd := '0'; aop2 := not iop2; invop2 := '1';
when MULSCC => alusel := EXE_RES_ADD;
aop1 := (icc(3) xor icc(1)) & iop1(31 downto 1);
if y0 = '0' then aop2 := (others => '0'); ldbp2 := '0'; end if;
mulstep := '1';
when UMUL | UMULCC | SMUL | SMULCC =>
if true then mulins := '1'; end if;
when UMAC | SMAC =>
if false then mulins := '1'; macins := '1'; end if;
when UDIV | UDIVCC | SDIV | SDIVCC =>
if true then
aluop := EXE_DIV; alusel := EXE_RES_LOGIC; divins := '1';
end if;
when IAND | ANDCC => aluop := EXE_AND; alusel := EXE_RES_LOGIC;
when ANDN | ANDNCC => aluop := EXE_ANDN; alusel := EXE_RES_LOGIC;
when IOR | ORCC => aluop := EXE_OR; alusel := EXE_RES_LOGIC;
when ORN | ORNCC => aluop := EXE_ORN; alusel := EXE_RES_LOGIC;
when IXNOR | XNORCC => aluop := EXE_XNOR; alusel := EXE_RES_LOGIC;
when XORCC | IXOR | WRPSR | WRWIM | WRTBR | WRY =>
aluop := EXE_XOR; alusel := EXE_RES_LOGIC;
when RDPSR | RDTBR | RDWIM => aluop := EXE_SPR;
when RDY => aluop := EXE_RDY;
when ISLL => aluop := EXE_SLL; alusel := EXE_RES_SHIFT; shleft := '1';
shcnt := not iop2(4 downto 0); invop2 := '1';
when ISRL => aluop := EXE_SRL; alusel := EXE_RES_SHIFT;
when ISRA => aluop := EXE_SRA; alusel := EXE_RES_SHIFT; sari := iop1(31);
when FPOP1 | FPOP2 =>
when others =>
end case;
when others => -- LDST
case r.a.ctrl.cnt is
when "00" =>
alusel := EXE_RES_ADD;
when "01" =>
case op3 is
when LDD | LDDA | LDDC => alusel := EXE_RES_ADD;
when LDDF => alusel := EXE_RES_ADD;
when SWAP | SWAPA | LDSTUB | LDSTUBA => alusel := EXE_RES_ADD;
when STF | STDF =>
when others =>
aluop := EXE_PASS1;
if op3(2) = '1' then
if op3(1 downto 0) = "01" then aluop := EXE_STB;
elsif op3(1 downto 0) = "10" then aluop := EXE_STH; end if;
end if;
end case;
when "10" =>
aluop := EXE_PASS1;
if op3(2) = '1' then -- ST
if (op3(3) and not op3(1))= '1' then aluop := EXE_ONES; end if; -- LDSTUB/A
end if;
when others =>
end case;
end case;
end;
function ra_inull_gen(r, v : registers) return std_ulogic is
variable de_inull : std_ulogic;
begin
de_inull := '0';
if ((v.e.jmpl or v.e.ctrl.rett) and not v.e.ctrl.annul and not (r.e.jmpl and not r.e.ctrl.annul)) = '1' then de_inull := '1'; end if;
if ((v.a.jmpl or v.a.ctrl.rett) and not v.a.ctrl.annul and not (r.a.jmpl and not r.a.ctrl.annul)) = '1' then de_inull := '1'; end if;
return(de_inull);
end;
-- operand generation
procedure op_mux(r : in registers; rfd, ed, md, xd, im : in word;
rsel : in std_logic_vector(2 downto 0);
ldbp : out std_ulogic; d : out word) is
begin
ldbp := '0';
case rsel is
when "000" => d := rfd;
when "001" => d := ed;
when "010" => d := md; if lddel = 1 then ldbp := r.m.ctrl.ld; end if;
when "011" => d := xd;
when "100" => d := im;
when "101" => d := (others => '0');
when "110" => d := r.w.result;
when others => d := (others => '-');
end case;
end;
procedure op_find(r : in registers; ldchkra : std_ulogic; ldchkex : std_ulogic;
rs1 : std_logic_vector(4 downto 0); ra : rfatype; im : boolean; rfe : out std_ulogic;
osel : out std_logic_vector(2 downto 0); ldcheck : std_ulogic) is
begin
rfe := '0';
if im then osel := "100";
elsif rs1 = "00000" then osel := "101"; -- %g0
elsif ((r.a.ctrl.wreg and ldchkra) = '1') and (ra = r.a.ctrl.rd) then osel := "001";
elsif ((r.e.ctrl.wreg and ldchkex) = '1') and (ra = r.e.ctrl.rd) then osel := "010";
elsif r.m.ctrl.wreg = '1' and (ra = r.m.ctrl.rd) then osel := "011";
elsif (irfwt = 0) and r.x.ctrl.wreg = '1' and (ra = r.x.ctrl.rd) then osel := "110";
else osel := "000"; rfe := ldcheck; end if;
end;
-- generate carry-in for alu
procedure cin_gen(r : registers; me_cin : in std_ulogic; cin : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable ncin : std_ulogic;
begin
op := r.a.ctrl.inst(31 downto 30); op3 := r.a.ctrl.inst(24 downto 19);
if r.e.ctrl.wicc = '1' then ncin := me_cin;
else ncin := r.m.icc(0); end if;
cin := '0';
case op is
when FMT3 =>
case op3 is
when ISUB | SUBCC | TSUBCC | TSUBCCTV => cin := '1';
when ADDX | ADDXCC => cin := ncin;
when SUBX | SUBXCC => cin := not ncin;
when others => null;
end case;
when others => null;
end case;
end;
procedure logic_op(r : registers; aluin1, aluin2, mey : word;
ymsb : std_ulogic; logicres, y : out word) is
variable logicout : word;
begin
case r.e.aluop is
when EXE_AND => logicout := aluin1 and aluin2;
when EXE_ANDN => logicout := aluin1 and not aluin2;
when EXE_OR => logicout := aluin1 or aluin2;
when EXE_ORN => logicout := aluin1 or not aluin2;
when EXE_XOR => logicout := aluin1 xor aluin2;
when EXE_XNOR => logicout := aluin1 xor not aluin2;
when EXE_DIV =>
if true then logicout := aluin2;
else logicout := (others => '-'); end if;
when others => logicout := (others => '-');
end case;
if (r.e.ctrl.wy and r.e.mulstep) = '1' then
y := ymsb & r.m.y(31 downto 1);
elsif r.e.ctrl.wy = '1' then y := logicout;
elsif r.m.ctrl.wy = '1' then y := mey;
elsif false and (r.x.mac = '1') then y := mulo.result(63 downto 32);
elsif r.x.ctrl.wy = '1' then y := r.x.y;
else y := r.w.s.y; end if;
logicres := logicout;
end;
procedure misc_op(r : registers; wpr : watchpoint_registers;
aluin1, aluin2, ldata, mey : word;
mout, edata : out word) is
variable miscout, bpdata, stdata : word;
variable wpi : integer;
begin
wpi := 0; miscout := r.e.ctrl.pc(31 downto 2) & "00";
edata := aluin1; bpdata := aluin1;
if ((r.x.ctrl.wreg and r.x.ctrl.ld and not r.x.ctrl.annul) = '1') and
(r.x.ctrl.rd = r.e.ctrl.rd) and (r.e.ctrl.inst(31 downto 30) = LDST) and
(r.e.ctrl.cnt /= "10")
then bpdata := ldata; end if;
case r.e.aluop is
when EXE_STB => miscout := bpdata(7 downto 0) & bpdata(7 downto 0) &
bpdata(7 downto 0) & bpdata(7 downto 0);
edata := miscout;
when EXE_STH => miscout := bpdata(15 downto 0) & bpdata(15 downto 0);
edata := miscout;
when EXE_PASS1 => miscout := bpdata; edata := miscout;
when EXE_PASS2 => miscout := aluin2;
when EXE_ONES => miscout := (others => '1');
edata := miscout;
when EXE_RDY =>
if true and (r.m.ctrl.wy = '1') then miscout := mey;
else miscout := r.m.y; end if;
if (NWP > 0) and (r.e.ctrl.inst(18 downto 17) = "11") then
wpi := conv_integer(r.e.ctrl.inst(16 downto 15));
if r.e.ctrl.inst(14) = '0' then miscout := wpr(wpi).addr & '0' & wpr(wpi).exec;
else miscout := wpr(wpi).mask & wpr(wpi).load & wpr(wpi).store; end if;
end if;
if (r.e.ctrl.inst(18 downto 17) = "10") and (r.e.ctrl.inst(14) = '1') then --%ASR17
miscout := asr17_gen(r);
end if;
if false then
if (r.e.ctrl.inst(18 downto 14) = "10010") then --%ASR18
if ((r.m.mac = '1') and not false) or ((r.x.mac = '1') and false) then
miscout := mulo.result(31 downto 0); -- data forward of asr18
else miscout := r.w.s.asr18; end if;
else
if ((r.m.mac = '1') and not false) or ((r.x.mac = '1') and false) then
miscout := mulo.result(63 downto 32); -- data forward Y
end if;
end if;
end if;
when EXE_SPR =>
miscout := get_spr(r);
when others => null;
end case;
mout := miscout;
end;
procedure alu_select(r : registers; addout : std_logic_vector(32 downto 0);
op1, op2 : word; shiftout, logicout, miscout : word; res : out word;
me_icc : std_logic_vector(3 downto 0);
icco : out std_logic_vector(3 downto 0); divz : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable icc : std_logic_vector(3 downto 0);
variable aluresult : word;
begin
op := r.e.ctrl.inst(31 downto 30); op3 := r.e.ctrl.inst(24 downto 19);
icc := (others => '0');
case r.e.alusel is
when EXE_RES_ADD =>
aluresult := addout(32 downto 1);
if r.e.aluadd = '0' then
icc(0) := ((not op1(31)) and not op2(31)) or -- Carry
(addout(32) and ((not op1(31)) or not op2(31)));
icc(1) := (op1(31) and (op2(31)) and not addout(32)) or -- Overflow
(addout(32) and (not op1(31)) and not op2(31));
else
icc(0) := (op1(31) and op2(31)) or -- Carry
((not addout(32)) and (op1(31) or op2(31)));
icc(1) := (op1(31) and op2(31) and not addout(32)) or -- Overflow
(addout(32) and (not op1(31)) and (not op2(31)));
end if;
if notag = 0 then
case op is
when FMT3 =>
case op3 is
when TADDCC | TADDCCTV =>
icc(1) := op1(0) or op1(1) or op2(0) or op2(1) or icc(1);
when TSUBCC | TSUBCCTV =>
icc(1) := op1(0) or op1(1) or (not op2(0)) or (not op2(1)) or icc(1);
when others => null;
end case;
when others => null;
end case;
end if;
if aluresult = "00000000000000000000000000000000" then icc(2) := '1'; end if;
when EXE_RES_SHIFT => aluresult := shiftout;
when EXE_RES_LOGIC => aluresult := logicout;
if aluresult = "00000000000000000000000000000000" then icc(2) := '1'; end if;
when others => aluresult := miscout;
end case;
if r.e.jmpl = '1' then aluresult := r.e.ctrl.pc(31 downto 2) & "00"; end if;
icc(3) := aluresult(31); divz := icc(2);
if r.e.ctrl.wicc = '1' then
if (op = FMT3) and (op3 = WRPSR) then icco := logicout(23 downto 20);
else icco := icc; end if;
elsif r.m.ctrl.wicc = '1' then icco := me_icc;
elsif r.x.ctrl.wicc = '1' then icco := r.x.icc;
else icco := r.w.s.icc; end if;
res := aluresult;
end;
procedure dcache_gen(r, v : registers; dci : out dc_in_type;
link_pc, jump, force_a2, load : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable su : std_ulogic;
begin
op := r.e.ctrl.inst(31 downto 30); op3 := r.e.ctrl.inst(24 downto 19);
dci.signed := '0'; dci.lock := '0'; dci.dsuen := '0'; dci.size := SZWORD;
if op = LDST then
case op3 is
when LDUB | LDUBA => dci.size := SZBYTE;
when LDSTUB | LDSTUBA => dci.size := SZBYTE; dci.lock := '1';
when LDUH | LDUHA => dci.size := SZHALF;
when LDSB | LDSBA => dci.size := SZBYTE; dci.signed := '1';
when LDSH | LDSHA => dci.size := SZHALF; dci.signed := '1';
when LD | LDA | LDF | LDC => dci.size := SZWORD;
when SWAP | SWAPA => dci.size := SZWORD; dci.lock := '1';
when LDD | LDDA | LDDF | LDDC => dci.size := SZDBL;
when STB | STBA => dci.size := SZBYTE;
when STH | STHA => dci.size := SZHALF;
when ST | STA | STF => dci.size := SZWORD;
when ISTD | STDA => dci.size := SZDBL;
when STDF | STDFQ => if FPEN then dci.size := SZDBL; end if;
when STDC | STDCQ => if false then dci.size := SZDBL; end if;
when others => dci.size := SZWORD; dci.lock := '0'; dci.signed := '0';
end case;
end if;
link_pc := '0'; jump:= '0'; force_a2 := '0'; load := '0';
dci.write := '0'; dci.enaddr := '0'; dci.read := not op3(2);
-- load/store control decoding
if (r.e.ctrl.annul = '0') then
case op is
when CALL => link_pc := '1';
when FMT3 =>
case op3 is
when JMPL => jump := '1'; link_pc := '1';
when RETT => jump := '1';
when others => null;
end case;
when LDST =>
case r.e.ctrl.cnt is
when "00" =>
dci.read := op3(3) or not op3(2); -- LD/LDST/SWAP
load := op3(3) or not op3(2);
dci.enaddr := '1';
when "01" =>
force_a2 := not op3(2); -- LDD
load := not op3(2); dci.enaddr := not op3(2);
if op3(3 downto 2) = "01" then -- ST/STD
dci.write := '1';
end if;
if op3(3 downto 2) = "11" then -- LDST/SWAP
dci.enaddr := '1';
end if;
when "10" => -- STD/LDST/SWAP
dci.write := '1';
when others => null;
end case;
if (r.e.ctrl.trap or (v.x.ctrl.trap and not v.x.ctrl.annul)) = '1' then
dci.enaddr := '0';
end if;
when others => null;
end case;
end if;
if ((r.x.ctrl.rett and not r.x.ctrl.annul) = '1') then su := r.w.s.ps;
else su := r.w.s.s; end if;
if su = '1' then dci.asi := "00001011"; else dci.asi := "00001010"; end if;
if (op3(4) = '1') and ((op3(5) = '0') or not false) then
dci.asi := r.e.ctrl.inst(12 downto 5);
end if;
end;
procedure fpstdata(r : in registers; edata, eres : in word; fpstdata : in std_logic_vector(31 downto 0);
edata2, eres2 : out word) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
begin
edata2 := edata; eres2 := eres;
op := r.e.ctrl.inst(31 downto 30); op3 := r.e.ctrl.inst(24 downto 19);
if FPEN then
if FPEN and (op = LDST) and ((op3(5 downto 4) & op3(2)) = "101") and (r.e.ctrl.cnt /= "00") then
edata2 := fpstdata; eres2 := fpstdata;
end if;
end if;
end;
function ld_align(data : dcdtype; set : std_logic_vector(0 downto 0);
size, laddr : std_logic_vector(1 downto 0); signed : std_ulogic) return word is
variable align_data, rdata : word;
begin
align_data := data(conv_integer(set)); rdata := (others => '0');
case size is
when "00" => -- byte read
case laddr is
when "00" =>
rdata(7 downto 0) := align_data(31 downto 24);
if signed = '1' then rdata(31 downto 8) := (others => align_data(31)); end if;
when "01" =>
rdata(7 downto 0) := align_data(23 downto 16);
if signed = '1' then rdata(31 downto 8) := (others => align_data(23)); end if;
when "10" =>
rdata(7 downto 0) := align_data(15 downto 8);
if signed = '1' then rdata(31 downto 8) := (others => align_data(15)); end if;
when others =>
rdata(7 downto 0) := align_data(7 downto 0);
if signed = '1' then rdata(31 downto 8) := (others => align_data(7)); end if;
end case;
when "01" => -- half-word read
if laddr(1) = '1' then
rdata(15 downto 0) := align_data(15 downto 0);
if signed = '1' then rdata(31 downto 15) := (others => align_data(15)); end if;
else
rdata(15 downto 0) := align_data(31 downto 16);
if signed = '1' then rdata(31 downto 15) := (others => align_data(31)); end if;
end if;
when others => -- single and double word read
rdata := align_data;
end case;
return(rdata);
end;
procedure mem_trap(r : registers; wpr : watchpoint_registers;
annul, holdn : in std_ulogic;
trapout, iflush, nullify, werrout : out std_ulogic;
tt : out std_logic_vector(5 downto 0)) is
variable cwp : std_logic_vector(3-1 downto 0);
variable cwpx : std_logic_vector(5 downto 3);
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable nalign_d : std_ulogic;
variable trap, werr : std_ulogic;
begin
op := r.m.ctrl.inst(31 downto 30); op2 := r.m.ctrl.inst(24 downto 22);
op3 := r.m.ctrl.inst(24 downto 19);
cwpx := r.m.result(5 downto 3); cwpx(5) := '0';
iflush := '0'; trap := r.m.ctrl.trap; nullify := annul;
tt := r.m.ctrl.tt; werr := (dco.werr or r.m.werr) and not r.w.s.dwt;
nalign_d := r.m.nalign or r.m.result(2);
if ((annul or trap) /= '1') and (r.m.ctrl.pv = '1') then
if (werr and holdn) = '1' then
trap := '1'; tt := TT_DSEX; werr := '0';
if op = LDST then nullify := '1'; end if;
end if;
end if;
if ((annul or trap) /= '1') then
case op is
when FMT2 =>
case op2 is
when FBFCC =>
if FPEN and (fpo.exc = '1') then trap := '1'; tt := TT_FPEXC; end if;
when CBCCC =>
if false and (cpo.exc = '1') then trap := '1'; tt := TT_CPEXC; end if;
when others => null;
end case;
when FMT3 =>
case op3 is
when WRPSR =>
if (orv(cwpx) = '1') then trap := '1'; tt := TT_IINST; end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if true then
if r.m.divz = '1' then trap := '1'; tt := TT_DIV; end if;
end if;
when JMPL | RETT =>
if r.m.nalign = '1' then trap := '1'; tt := TT_UNALA; end if;
when TADDCCTV | TSUBCCTV =>
if (notag = 0) and (r.m.icc(1) = '1') then
trap := '1'; tt := TT_TAG;
end if;
when FLUSH => iflush := '1';
when FPOP1 | FPOP2 =>
if FPEN and (fpo.exc = '1') then trap := '1'; tt := TT_FPEXC; end if;
when CPOP1 | CPOP2 =>
if false and (cpo.exc = '1') then trap := '1'; tt := TT_CPEXC; end if;
when others => null;
end case;
when LDST =>
if r.m.ctrl.cnt = "00" then
case op3 is
when LDDF | STDF | STDFQ =>
if FPEN then
if nalign_d = '1' then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif (fpo.exc and r.m.ctrl.pv) = '1'
then trap := '1'; tt := TT_FPEXC; nullify := '1'; end if;
end if;
when LDDC | STDC | STDCQ =>
if false then
if nalign_d = '1' then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif ((cpo.exc and r.m.ctrl.pv) = '1')
then trap := '1'; tt := TT_CPEXC; nullify := '1'; end if;
end if;
when LDD | ISTD | LDDA | STDA =>
if r.m.result(2 downto 0) /= "000" then
trap := '1'; tt := TT_UNALA; nullify := '1';
end if;
when LDF | LDFSR | STFSR | STF =>
if FPEN and (r.m.nalign = '1') then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif FPEN and ((fpo.exc and r.m.ctrl.pv) = '1')
then trap := '1'; tt := TT_FPEXC; nullify := '1'; end if;
when LDC | LDCSR | STCSR | STC =>
if false and (r.m.nalign = '1') then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif false and ((cpo.exc and r.m.ctrl.pv) = '1')
then trap := '1'; tt := TT_CPEXC; nullify := '1'; end if;
when LD | LDA | ST | STA | SWAP | SWAPA =>
if r.m.result(1 downto 0) /= "00" then
trap := '1'; tt := TT_UNALA; nullify := '1';
end if;
when LDUH | LDUHA | LDSH | LDSHA | STH | STHA =>
if r.m.result(0) /= '0' then
trap := '1'; tt := TT_UNALA; nullify := '1';
end if;
when others => null;
end case;
for i in 1 to NWP loop
if ((((wpr(i-1).load and not op3(2)) or (wpr(i-1).store and op3(2))) = '1') and
(((wpr(i-1).addr xor r.m.result(31 downto 2)) and wpr(i-1).mask) = "000000000000000000000000000000"))
then trap := '1'; tt := TT_WATCH; nullify := '1'; end if;
end loop;
end if;
when others => null;
end case;
end if;
if (rstn = '0') or (r.x.rstate = dsu2) then werr := '0'; end if;
trapout := trap; werrout := werr;
end;
procedure irq_trap(r : in registers;
ir : in irestart_register;
irl : in std_logic_vector(3 downto 0);
annul : in std_ulogic;
pv : in std_ulogic;
trap : in std_ulogic;
tt : in std_logic_vector(5 downto 0);
nullify : in std_ulogic;
irqen : out std_ulogic;
irqen2 : out std_ulogic;
nullify2 : out std_ulogic;
trap2, ipend : out std_ulogic;
tt2 : out std_logic_vector(5 downto 0)) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable pend : std_ulogic;
begin
nullify2 := nullify; trap2 := trap; tt2 := tt;
op := r.m.ctrl.inst(31 downto 30); op3 := r.m.ctrl.inst(24 downto 19);
irqen := '1'; irqen2 := r.m.irqen;
if (annul or trap) = '0' then
if ((op = FMT3) and (op3 = WRPSR)) then irqen := '0'; end if;
end if;
if (irl = "1111") or (irl > r.w.s.pil) then
pend := r.m.irqen and r.m.irqen2 and r.w.s.et and not ir.pwd;
else pend := '0'; end if;
ipend := pend;
if ((not annul) and pv and (not trap) and pend) = '1' then
trap2 := '1'; tt2 := "01" & irl;
if op = LDST then nullify2 := '1'; end if;
end if;
end;
procedure irq_intack(r : in registers; holdn : in std_ulogic; intack: out std_ulogic) is
begin
intack := '0';
if r.x.rstate = trap then
if r.w.s.tt(7 downto 4) = "0001" then intack := '1'; end if;
end if;
end;
-- write special registers
procedure sp_write (r : registers; wpr : watchpoint_registers;
s : out special_register_type; vwpr : out watchpoint_registers) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable i : integer range 0 to 3;
begin
op := r.x.ctrl.inst(31 downto 30);
op2 := r.x.ctrl.inst(24 downto 22);
op3 := r.x.ctrl.inst(24 downto 19);
s := r.w.s;
rd := r.x.ctrl.inst(29 downto 25);
vwpr := wpr;
case op is
when FMT3 =>
case op3 is
when WRY =>
if rd = "00000" then
s.y := r.x.result;
elsif false and (rd = "10010") then
s.asr18 := r.x.result;
elsif (rd = "10001") then
s.dwt := r.x.result(14);
if (svt = 1) then s.svt := r.x.result(13); end if;
elsif rd(4 downto 3) = "11" then -- %ASR24 - %ASR31
case rd(2 downto 0) is
when "000" =>
vwpr(0).addr := r.x.result(31 downto 2);
vwpr(0).exec := r.x.result(0);
when "001" =>
vwpr(0).mask := r.x.result(31 downto 2);
vwpr(0).load := r.x.result(1);
vwpr(0).store := r.x.result(0);
when "010" =>
vwpr(1).addr := r.x.result(31 downto 2);
vwpr(1).exec := r.x.result(0);
when "011" =>
vwpr(1).mask := r.x.result(31 downto 2);
vwpr(1).load := r.x.result(1);
vwpr(1).store := r.x.result(0);
when "100" =>
vwpr(2).addr := r.x.result(31 downto 2);
vwpr(2).exec := r.x.result(0);
when "101" =>
vwpr(2).mask := r.x.result(31 downto 2);
vwpr(2).load := r.x.result(1);
vwpr(2).store := r.x.result(0);
when "110" =>
vwpr(3).addr := r.x.result(31 downto 2);
vwpr(3).exec := r.x.result(0);
when others => -- "111"
vwpr(3).mask := r.x.result(31 downto 2);
vwpr(3).load := r.x.result(1);
vwpr(3).store := r.x.result(0);
end case;
end if;
when WRPSR =>
s.cwp := r.x.result(3-1 downto 0);
s.icc := r.x.result(23 downto 20);
s.ec := r.x.result(13);
if FPEN then s.ef := r.x.result(12); end if;
s.pil := r.x.result(11 downto 8);
s.s := r.x.result(7);
s.ps := r.x.result(6);
s.et := r.x.result(5);
when WRWIM =>
s.wim := r.x.result(8-1 downto 0);
when WRTBR =>
s.tba := r.x.result(31 downto 12);
when SAVE =>
if (not true) and (r.w.s.cwp = "000") then s.cwp := "111";
else s.cwp := r.w.s.cwp - 1 ; end if;
when RESTORE =>
if (not true) and (r.w.s.cwp = "111") then s.cwp := "000";
else s.cwp := r.w.s.cwp + 1; end if;
when RETT =>
if (not true) and (r.w.s.cwp = "111") then s.cwp := "000";
else s.cwp := r.w.s.cwp + 1; end if;
s.s := r.w.s.ps;
s.et := '1';
when others => null;
end case;
when others => null;
end case;
if r.x.ctrl.wicc = '1' then s.icc := r.x.icc; end if;
if r.x.ctrl.wy = '1' then s.y := r.x.y; end if;
if false and (r.x.mac = '1') then
s.asr18 := mulo.result(31 downto 0);
s.y := mulo.result(63 downto 32);
end if;
end;
function npc_find (r : registers) return std_logic_vector is
variable npc : std_logic_vector(2 downto 0);
begin
npc := "011";
if r.m.ctrl.pv = '1' then npc := "000";
elsif r.e.ctrl.pv = '1' then npc := "001";
elsif r.a.ctrl.pv = '1' then npc := "010";
elsif r.d.pv = '1' then npc := "011";
elsif 2 /= 0 then npc := "100"; end if;
return(npc);
end;
function npc_gen (r : registers) return word is
variable npc : std_logic_vector(31 downto 0);
begin
npc := r.a.ctrl.pc(31 downto 2) & "00";
case r.x.npc is
when "000" => npc(31 downto 2) := r.x.ctrl.pc(31 downto 2);
when "001" => npc(31 downto 2) := r.m.ctrl.pc(31 downto 2);
when "010" => npc(31 downto 2) := r.e.ctrl.pc(31 downto 2);
when "011" => npc(31 downto 2) := r.a.ctrl.pc(31 downto 2);
when others =>
if 2 /= 0 then npc(31 downto 2) := r.d.pc(31 downto 2); end if;
end case;
return(npc);
end;
procedure mul_res(r : registers; asr18in : word; result, y, asr18 : out word;
icc : out std_logic_vector(3 downto 0)) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
begin
op := r.m.ctrl.inst(31 downto 30); op3 := r.m.ctrl.inst(24 downto 19);
result := r.m.result; y := r.m.y; icc := r.m.icc; asr18 := asr18in;
case op is
when FMT3 =>
case op3 is
when UMUL | SMUL =>
if true then
result := mulo.result(31 downto 0);
y := mulo.result(63 downto 32);
end if;
when UMULCC | SMULCC =>
if true then
result := mulo.result(31 downto 0); icc := mulo.icc;
y := mulo.result(63 downto 32);
end if;
when UMAC | SMAC =>
if false and not false then
result := mulo.result(31 downto 0);
asr18 := mulo.result(31 downto 0);
y := mulo.result(63 downto 32);
end if;
when UDIV | SDIV =>
if true then
result := divo.result(31 downto 0);
end if;
when UDIVCC | SDIVCC =>
if true then
result := divo.result(31 downto 0); icc := divo.icc;
end if;
when others => null;
end case;
when others => null;
end case;
end;
function powerdwn(r : registers; trap : std_ulogic; rp : pwd_register_type) return std_ulogic is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable pd : std_ulogic;
begin
op := r.x.ctrl.inst(31 downto 30);
op3 := r.x.ctrl.inst(24 downto 19);
rd := r.x.ctrl.inst(29 downto 25);
pd := '0';
if (not (r.x.ctrl.annul or trap) and r.x.ctrl.pv) = '1' then
if ((op = FMT3) and (op3 = WRY) and (rd = "10011")) then pd := '1'; end if;
pd := pd or rp.pwd;
end if;
return(pd);
end;
signal dummy : std_ulogic;
signal cpu_index : std_logic_vector(3 downto 0);
signal disasen : std_ulogic;
SIGNAL hackStateM1 : std_logic;
begin
comb : process(ico, dco, rfo, r, wpr, ir, dsur, rstn, holdn, irqi, dbgi, fpo, cpo, tbo,
mulo, divo, dummy, rp)
variable v : registers;
variable vp : pwd_register_type;
variable vwpr : watchpoint_registers;
variable vdsu : dsu_registers;
variable npc : std_logic_vector(31 downto 2);
variable de_raddr1, de_raddr2 : std_logic_vector(9 downto 0);
variable de_rs2, de_rd : std_logic_vector(4 downto 0);
variable de_hold_pc, de_branch, de_fpop, de_ldlock : std_ulogic;
variable de_cwp, de_cwp2 : cwptype;
variable de_inull : std_ulogic;
variable de_ren1, de_ren2 : std_ulogic;
variable de_wcwp : std_ulogic;
variable de_inst : word;
variable de_branch_address : pctype;
variable de_icc : std_logic_vector(3 downto 0);
variable de_fbranch, de_cbranch : std_ulogic;
variable de_rs1mod : std_ulogic;
variable ra_op1, ra_op2 : word;
variable ra_div : std_ulogic;
variable ex_jump, ex_link_pc : std_ulogic;
variable ex_jump_address : pctype;
variable ex_add_res : std_logic_vector(32 downto 0);
variable ex_shift_res, ex_logic_res, ex_misc_res : word;
variable ex_edata, ex_edata2 : word;
variable ex_dci : dc_in_type;
variable ex_force_a2, ex_load, ex_ymsb : std_ulogic;
variable ex_op1, ex_op2, ex_result, ex_result2, mul_op2 : word;
variable ex_shcnt : std_logic_vector(4 downto 0);
variable ex_dsuen : std_ulogic;
variable ex_ldbp2 : std_ulogic;
variable ex_sari : std_ulogic;
variable me_inull, me_nullify, me_nullify2 : std_ulogic;
variable me_iflush : std_ulogic;
variable me_newtt : std_logic_vector(5 downto 0);
variable me_asr18 : word;
variable me_signed : std_ulogic;
variable me_size, me_laddr : std_logic_vector(1 downto 0);
variable me_icc : std_logic_vector(3 downto 0);
variable xc_result : word;
variable xc_df_result : word;
variable xc_waddr : std_logic_vector(9 downto 0);
variable xc_exception, xc_wreg : std_ulogic;
variable xc_trap_address : pctype;
variable xc_vectt : std_logic_vector(7 downto 0);
variable xc_trap : std_ulogic;
variable xc_fpexack : std_ulogic;
variable xc_rstn, xc_halt : std_ulogic;
-- variable wr_rf1_data, wr_rf2_data : word;
variable diagdata : word;
variable tbufi : tracebuf_in_type;
variable dbgm : std_ulogic;
variable fpcdbgwr : std_ulogic;
variable vfpi : fpc_in_type;
variable dsign : std_ulogic;
variable pwrd, sidle : std_ulogic;
variable vir : irestart_register;
variable icnt : std_ulogic;
variable tbufcntx : std_logic_vector(7-1 downto 0);
begin
v := r; vwpr := wpr; vdsu := dsur; vp := rp;
xc_fpexack := '0'; sidle := '0';
fpcdbgwr := '0'; vir := ir; xc_rstn := rstn;
-----------------------------------------------------------------------
-- WRITE STAGE
-----------------------------------------------------------------------
-- wr_rf1_data := rfo.data1; wr_rf2_data := rfo.data2;
-- if irfwt = 0 then
-- if r.w.wreg = '1' then
-- if r.a.rfa1 = r.w.wa then wr_rf1_data := r.w.result; end if;
-- if r.a.rfa2 = r.w.wa then wr_rf2_data := r.w.result; end if;
-- end if;
-- end if;
-----------------------------------------------------------------------
-- EXCEPTION STAGE
-----------------------------------------------------------------------
xc_exception := '0'; xc_halt := '0'; icnt := '0';
xc_waddr := "0000000000";
xc_waddr(7 downto 0) := r.x.ctrl.rd(7 downto 0);
xc_trap := r.x.mexc or r.x.ctrl.trap;
v.x.nerror := rp.error;
if r.x.mexc = '1' then xc_vectt := "00" & TT_DAEX;
elsif r.x.ctrl.tt = TT_TICC then
xc_vectt := '1' & r.x.result(6 downto 0);
else xc_vectt := "00" & r.x.ctrl.tt; end if;
if r.w.s.svt = '0' then
xc_trap_address(31 downto 4) := r.w.s.tba & xc_vectt;
else
xc_trap_address(31 downto 4) := r.w.s.tba & "00000000";
end if;
xc_trap_address(3 downto 2) := "00";
xc_wreg := '0'; v.x.annul_all := '0';
if (r.x.ctrl.ld = '1') then
if (lddel = 2) then
xc_result := ld_align(r.x.data, r.x.set, r.x.dci.size, r.x.laddr, r.x.dci.signed);
else xc_result := r.x.data(0); end if;
elsif false and false and (r.x.mac = '1') then
xc_result := mulo.result(31 downto 0);
else xc_result := r.x.result; end if;
xc_df_result := xc_result;
if true then
dbgm := dbgexc(r, dbgi, xc_trap, xc_vectt);
if (dbgi.dsuen and dbgi.dbreak) = '0'then v.x.debug := '0'; end if;
else dbgm := '0'; v.x.debug := '0'; end if;
if false then pwrd := powerdwn(r, xc_trap, rp); else pwrd := '0'; end if;
case r.x.rstate is
when run =>
if (not r.x.ctrl.annul and r.x.ctrl.pv and not r.x.debug) = '1' then
icnt := holdn;
end if;
if dbgm = '1' then
v.x.annul_all := '1'; vir.addr := r.x.ctrl.pc;
v.x.rstate := dsu1; v.x.debug := '1';
v.x.npc := npc_find(r);
vdsu.tt := xc_vectt; vdsu.err := dbgerr(r, dbgi, xc_vectt);
elsif (pwrd = '1') and (ir.pwd = '0') then
v.x.annul_all := '1'; vir.addr := r.x.ctrl.pc;
v.x.rstate := dsu1; v.x.npc := npc_find(r); vp.pwd := '1';
elsif (r.x.ctrl.annul or xc_trap) = '0' then
xc_wreg := r.x.ctrl.wreg;
sp_write (r, wpr, v.w.s, vwpr);
vir.pwd := '0';
elsif ((not r.x.ctrl.annul) and xc_trap) = '1' then
xc_exception := '1'; xc_result := r.x.ctrl.pc(31 downto 2) & "00";
xc_wreg := '1'; v.w.s.tt := xc_vectt; v.w.s.ps := r.w.s.s;
v.w.s.s := '1'; v.x.annul_all := '1'; v.x.rstate := trap;
xc_waddr := "0000000000";
xc_waddr(6 downto 0) := r.w.s.cwp & "0001";
v.x.npc := npc_find(r);
fpexack(r, xc_fpexack);
if r.w.s.et = '0' then
-- v.x.rstate := dsu1; xc_wreg := '0'; vp.error := '1';
xc_wreg := '0';
end if;
end if;
when trap =>
xc_result := npc_gen(r); xc_wreg := '1';
xc_waddr := "0000000000";
xc_waddr(6 downto 0) := r.w.s.cwp & "0010";
if (r.w.s.et = '1') then
v.w.s.et := '0'; v.x.rstate := run;
if (not true) and (r.w.s.cwp = "000") then v.w.s.cwp := "111";
else v.w.s.cwp := r.w.s.cwp - 1 ; end if;
else
v.x.rstate := dsu1; xc_wreg := '0'; vp.error := '1';
end if;
when dsu1 =>
xc_exception := '1'; v.x.annul_all := '1';
xc_trap_address(31 downto 2) := r.f.pc;
if true or false or (smp /= 0) then
xc_trap_address(31 downto 2) := ir.addr;
vir.addr := npc_gen(r)(31 downto 2);
v.x.rstate := dsu2;
end if;
if true then v.x.debug := r.x.debug; end if;
when dsu2 =>
xc_exception := '1'; v.x.annul_all := '1';
xc_trap_address(31 downto 2) := r.f.pc;
if true or false or (smp /= 0) then
sidle := (rp.pwd or rp.error) and ico.idle and dco.idle and not r.x.debug;
if true then
if dbgi.reset = '1' then
if smp /=0 then vp.pwd := not irqi.run; else vp.pwd := '0'; end if;
vp.error := '0';
end if;
if (dbgi.dsuen and dbgi.dbreak) = '1'then v.x.debug := '1'; end if;
diagwr(r, dsur, ir, dbgi, wpr, v.w.s, vwpr, vdsu.asi, xc_trap_address,
vir.addr, vdsu.tbufcnt, xc_wreg, xc_waddr, xc_result, fpcdbgwr);
xc_halt := dbgi.halt;
end if;
if r.x.ipend = '1' then vp.pwd := '0'; end if;
if (rp.error or rp.pwd or r.x.debug or xc_halt) = '0' then
v.x.rstate := run; v.x.annul_all := '0'; vp.error := '0';
xc_trap_address(31 downto 2) := ir.addr; v.x.debug := '0';
vir.pwd := '1';
end if;
if (smp /= 0) and (irqi.rst = '1') then
vp.pwd := '0'; vp.error := '0';
end if;
end if;
when others =>
end case;
irq_intack(r, holdn, v.x.intack);
itrace(r, dsur, vdsu, xc_result, xc_exception, dbgi, rp.error, xc_trap, tbufcntx, tbufi);
vdsu.tbufcnt := tbufcntx;
v.w.except := xc_exception; v.w.result := xc_result;
if (r.x.rstate = dsu2) then v.w.except := '0'; end if;
v.w.wa := xc_waddr(7 downto 0); v.w.wreg := xc_wreg and holdn;
rfi.wdata <= xc_result; rfi.waddr <= xc_waddr;
rfi.wren <= (xc_wreg and holdn) and not dco.scanen;
irqo.intack <= r.x.intack and holdn;
irqo.irl <= r.w.s.tt(3 downto 0);
irqo.pwd <= rp.pwd;
irqo.fpen <= r.w.s.ef;
dbgo.halt <= xc_halt;
dbgo.pwd <= rp.pwd;
dbgo.idle <= sidle;
dbgo.icnt <= icnt;
dci.intack <= r.x.intack and holdn;
if (xc_rstn = '0') then
v.w.except := '0'; v.w.s.et := '0'; v.w.s.svt := '0'; v.w.s.dwt := '0';
v.w.s.ef := '0'; -- needed for AX
if need_extra_sync_reset(fabtech) /= 0 then
v.w.s.cwp := "000";
v.w.s.icc := "0000";
end if;
v.x.annul_all := '1'; v.x.rstate := run; vir.pwd := '0';
vp.pwd := '0'; v.x.debug := '0'; --vp.error := '0';
v.x.nerror := '0';
if svt = 1 then v.w.s.tt := "00000000"; end if;
if true then
if (dbgi.dsuen and dbgi.dbreak) = '1' then
v.x.rstate := dsu1; v.x.debug := '1';
end if;
end if;
if (smp /= 0) and (irqi.run = '0') and (rstn = '0') then
v.x.rstate := dsu1; vp.pwd := '1';
end if;
end if;
if not FPEN then v.w.s.ef := '0'; end if;
-----------------------------------------------------------------------
-- MEMORY STAGE
-----------------------------------------------------------------------
v.x.ctrl := r.m.ctrl; v.x.dci := r.m.dci;
v.x.ctrl.rett := r.m.ctrl.rett and not r.m.ctrl.annul;
v.x.mac := r.m.mac; v.x.laddr := r.m.result(1 downto 0);
v.x.ctrl.annul := r.m.ctrl.annul or v.x.annul_all;
mul_res(r, v.w.s.asr18, v.x.result, v.x.y, me_asr18, me_icc);
mem_trap(r, wpr, v.x.ctrl.annul, holdn, v.x.ctrl.trap, me_iflush,
me_nullify, v.m.werr, v.x.ctrl.tt);
me_newtt := v.x.ctrl.tt;
irq_trap(r, ir, irqi.irl, v.x.ctrl.annul, v.x.ctrl.pv, v.x.ctrl.trap, me_newtt, me_nullify,
v.m.irqen, v.m.irqen2, me_nullify2, v.x.ctrl.trap,
v.x.ipend, v.x.ctrl.tt);
if (r.m.ctrl.ld or not dco.mds) = '1' then
for i in 0 to 2-1 loop v.x.data(i) := dco.data(i); end loop;
v.x.set := dco.set(0 downto 0);
if dco.mds = '0' then
me_size := r.x.dci.size; me_laddr := r.x.laddr; me_signed := r.x.dci.signed;
else
me_size := v.x.dci.size; me_laddr := v.x.laddr; me_signed := v.x.dci.signed;
end if;
if lddel /= 2 then
v.x.data(0) := ld_align(v.x.data, v.x.set, me_size, me_laddr, me_signed);
end if;
end if;
v.x.mexc := dco.mexc;
v.x.icc := me_icc;
v.x.ctrl.wicc := r.m.ctrl.wicc and not v.x.annul_all;
if false and ((v.x.ctrl.annul or v.x.ctrl.trap) = '0') then
v.w.s.asr18 := me_asr18;
end if;
if (r.x.rstate = dsu2) then
me_nullify2 := '0'; v.x.set := dco.set(0 downto 0);
end if;
dci.maddress <= r.m.result;
dci.enaddr <= r.m.dci.enaddr;
dci.asi <= r.m.dci.asi;
dci.size <= r.m.dci.size;
dci.nullify <= me_nullify2;
dci.lock <= r.m.dci.lock and not r.m.ctrl.annul;
dci.read <= r.m.dci.read;
dci.write <= r.m.dci.write;
dci.flush <= me_iflush;
dci.dsuen <= r.m.dci.dsuen;
dci.msu <= r.m.su;
dci.esu <= r.e.su;
dbgo.ipend <= v.x.ipend;
-----------------------------------------------------------------------
-- EXECUTE STAGE
-----------------------------------------------------------------------
v.m.ctrl := r.e.ctrl; ex_op1 := r.e.op1; ex_op2 := r.e.op2;
v.m.ctrl.rett := r.e.ctrl.rett and not r.e.ctrl.annul;
v.m.ctrl.wreg := r.e.ctrl.wreg and not v.x.annul_all;
ex_ymsb := r.e.ymsb; mul_op2 := ex_op2; ex_shcnt := r.e.shcnt;
v.e.cwp := r.a.cwp; ex_sari := r.e.sari;
v.m.su := r.e.su;
if 0 = 3 then v.m.mul := r.e.mul; else v.m.mul := '0'; end if;
if lddel = 1 then
if r.e.ldbp1 = '1' then
ex_op1 := r.x.data(0);
ex_sari := r.x.data(0)(31) and r.e.ctrl.inst(19) and r.e.ctrl.inst(20);
end if;
if r.e.ldbp2 = '1' then
ex_op2 := r.x.data(0); ex_ymsb := r.x.data(0)(0);
mul_op2 := ex_op2; ex_shcnt := r.x.data(0)(4 downto 0);
if r.e.invop2 = '1' then
ex_op2 := not ex_op2; ex_shcnt := not ex_shcnt;
end if;
end if;
end if;
ex_add_res := (ex_op1 & '1') + (ex_op2 & r.e.alucin);
if ex_add_res(2 downto 1) = "00" then v.m.nalign := '0';
else v.m.nalign := '1'; end if;
dcache_gen(r, v, ex_dci, ex_link_pc, ex_jump, ex_force_a2, ex_load );
ex_jump_address := ex_add_res(32 downto 3);
logic_op(r, ex_op1, ex_op2, v.x.y, ex_ymsb, ex_logic_res, v.m.y);
ex_shift_res := shift(r, ex_op1, ex_op2, ex_shcnt, ex_sari);
misc_op(r, wpr, ex_op1, ex_op2, xc_df_result, v.x.y, ex_misc_res, ex_edata);
ex_add_res(3):= ex_add_res(3) or ex_force_a2;
alu_select(r, ex_add_res, ex_op1, ex_op2, ex_shift_res, ex_logic_res,
ex_misc_res, ex_result, me_icc, v.m.icc, v.m.divz);
dbg_cache(holdn, dbgi, r, dsur, ex_result, ex_dci, ex_result2, v.m.dci);
fpstdata(r, ex_edata, ex_result2, fpo.data, ex_edata2, v.m.result);
cwp_ex(r, v.m.wcwp);
v.m.ctrl.annul := v.m.ctrl.annul or v.x.annul_all;
v.m.ctrl.wicc := r.e.ctrl.wicc and not v.x.annul_all;
v.m.mac := r.e.mac;
if (true and (r.x.rstate = dsu2)) then v.m.ctrl.ld := '1'; end if;
dci.eenaddr <= v.m.dci.enaddr;
dci.eaddress <= ex_add_res(32 downto 1);
dci.edata <= ex_edata2;
-----------------------------------------------------------------------
-- REGFILE STAGE
-----------------------------------------------------------------------
v.e.ctrl := r.a.ctrl; v.e.jmpl := r.a.jmpl;
v.e.ctrl.annul := r.a.ctrl.annul or v.x.annul_all;
v.e.ctrl.rett := r.a.ctrl.rett and not r.a.ctrl.annul;
v.e.ctrl.wreg := r.a.ctrl.wreg and not v.x.annul_all;
v.e.su := r.a.su; v.e.et := r.a.et;
v.e.ctrl.wicc := r.a.ctrl.wicc and not v.x.annul_all;
exception_detect(r, wpr, dbgi, r.a.ctrl.trap, r.a.ctrl.tt,
v.e.ctrl.trap, v.e.ctrl.tt);
op_mux(r, rfo.data1, v.m.result, v.x.result, xc_df_result, "00000000000000000000000000000000",
r.a.rsel1, v.e.ldbp1, ra_op1);
op_mux(r, rfo.data2, v.m.result, v.x.result, xc_df_result, r.a.imm,
r.a.rsel2, ex_ldbp2, ra_op2);
alu_op(r, ra_op1, ra_op2, v.m.icc, v.m.y(0), ex_ldbp2, v.e.op1, v.e.op2,
v.e.aluop, v.e.alusel, v.e.aluadd, v.e.shcnt, v.e.sari, v.e.shleft,
v.e.ymsb, v.e.mul, ra_div, v.e.mulstep, v.e.mac, v.e.ldbp2, v.e.invop2);
cin_gen(r, v.m.icc(0), v.e.alucin);
-----------------------------------------------------------------------
-- DECODE STAGE
-----------------------------------------------------------------------
if 2 > 1 then de_inst := r.d.inst(conv_integer(r.d.set));
else de_inst := r.d.inst(0); end if;
de_icc := r.m.icc; v.a.cwp := r.d.cwp;
su_et_select(r, v.w.s.ps, v.w.s.s, v.w.s.et, v.a.su, v.a.et);
wicc_y_gen(de_inst, v.a.ctrl.wicc, v.a.ctrl.wy);
cwp_ctrl(r, v.w.s.wim, de_inst, de_cwp, v.a.wovf, v.a.wunf, de_wcwp);
rs1_gen(r, de_inst, v.a.rs1, de_rs1mod);
de_rs2 := de_inst(4 downto 0);
de_raddr1 := "0000000000"; de_raddr2 := "0000000000";
if true then
if de_rs1mod = '1' then
regaddr(r.d.cwp, de_inst(29 downto 26) & v.a.rs1(0), de_raddr1(7 downto 0));
else
regaddr(r.d.cwp, de_inst(18 downto 15) & v.a.rs1(0), de_raddr1(7 downto 0));
end if;
else
regaddr(r.d.cwp, v.a.rs1, de_raddr1(7 downto 0));
end if;
regaddr(r.d.cwp, de_rs2, de_raddr2(7 downto 0));
v.a.rfa1 := de_raddr1(7 downto 0);
v.a.rfa2 := de_raddr2(7 downto 0);
rd_gen(r, de_inst, v.a.ctrl.wreg, v.a.ctrl.ld, de_rd);
regaddr(de_cwp, de_rd, v.a.ctrl.rd);
fpbranch(de_inst, fpo.cc, de_fbranch);
fpbranch(de_inst, cpo.cc, de_cbranch);
v.a.imm := imm_data(r, de_inst);
lock_gen(r, de_rs2, de_rd, v.a.rfa1, v.a.rfa2, v.a.ctrl.rd, de_inst,
fpo.ldlock, v.e.mul, ra_div, v.a.ldcheck1, v.a.ldcheck2, de_ldlock,
v.a.ldchkra, v.a.ldchkex);
ic_ctrl(r, de_inst, v.x.annul_all, de_ldlock, branch_true(de_icc, de_inst),
de_fbranch, de_cbranch, fpo.ccv, cpo.ccv, v.d.cnt, v.d.pc, de_branch,
v.a.ctrl.annul, v.d.annul, v.a.jmpl, de_inull, v.d.pv, v.a.ctrl.pv,
de_hold_pc, v.a.ticc, v.a.ctrl.rett, v.a.mulstart, v.a.divstart);
cwp_gen(r, v, v.a.ctrl.annul, de_wcwp, de_cwp, v.d.cwp);
v.d.inull := ra_inull_gen(r, v);
op_find(r, v.a.ldchkra, v.a.ldchkex, v.a.rs1, v.a.rfa1,
false, v.a.rfe1, v.a.rsel1, v.a.ldcheck1);
op_find(r, v.a.ldchkra, v.a.ldchkex, de_rs2, v.a.rfa2,
imm_select(de_inst), v.a.rfe2, v.a.rsel2, v.a.ldcheck2);
de_branch_address := branch_address(de_inst, r.d.pc);
v.a.ctrl.annul := v.a.ctrl.annul or v.x.annul_all;
v.a.ctrl.wicc := v.a.ctrl.wicc and not v.a.ctrl.annul;
v.a.ctrl.wreg := v.a.ctrl.wreg and not v.a.ctrl.annul;
v.a.ctrl.rett := v.a.ctrl.rett and not v.a.ctrl.annul;
v.a.ctrl.wy := v.a.ctrl.wy and not v.a.ctrl.annul;
v.a.ctrl.trap := r.d.mexc;
v.a.ctrl.tt := "000000";
v.a.ctrl.inst := de_inst;
v.a.ctrl.pc := r.d.pc;
v.a.ctrl.cnt := r.d.cnt;
v.a.step := r.d.step;
if holdn = '0' then
de_raddr1(7 downto 0) := r.a.rfa1;
de_raddr2(7 downto 0) := r.a.rfa2;
de_ren1 := r.a.rfe1; de_ren2 := r.a.rfe2;
else
de_ren1 := v.a.rfe1; de_ren2 := v.a.rfe2;
end if;
if true then
if ((dbgi.denable and not dbgi.dwrite) = '1') and (r.x.rstate = dsu2) then
de_raddr1(7 downto 0) := dbgi.daddr(9 downto 2); de_ren1 := '1';
end if;
v.d.step := dbgi.step and not r.d.annul;
end if;
rfi.raddr1 <= de_raddr1; rfi.raddr2 <= de_raddr2;
rfi.ren1 <= de_ren1 and not dco.scanen;
rfi.ren2 <= de_ren2 and not dco.scanen;
rfi.diag <= dco.testen & "000";
ici.inull <= de_inull;
ici.flush <= me_iflush;
if (xc_rstn = '0') then
v.d.cnt := "00";
if need_extra_sync_reset(fabtech) /= 0 then
v.d.cwp := "000";
end if;
end if;
-----------------------------------------------------------------------
-- FETCH STAGE
-----------------------------------------------------------------------
npc := r.f.pc;
if (xc_rstn = '0') then
v.f.pc := "000000000000000000000000000000"; v.f.branch := '0';
if false then v.f.pc(31 downto 12) := irqi.rstvec;
else
v.f.pc(31 downto 12) := conv_std_logic_vector(rstaddr, 20);
end if;
elsif xc_exception = '1' then -- exception
v.f.branch := '1'; v.f.pc := xc_trap_address;
npc := v.f.pc;
-- elsif (not ra_inull and de_hold_pc) = '1' then
elsif de_hold_pc = '1' then
v.f.pc := r.f.pc; v.f.branch := r.f.branch;
if ex_jump = '1' then
v.f.pc := ex_jump_address; v.f.branch := '1';
npc := v.f.pc;
end if;
elsif ex_jump = '1' then
v.f.pc := ex_jump_address; v.f.branch := '1';
npc := v.f.pc;
elsif de_branch = '1' then
v.f.pc := branch_address(de_inst, r.d.pc); v.f.branch := '1';
npc := v.f.pc;
else
v.f.branch := '0';
v.f.pc(31 downto 2) := r.f.pc(31 downto 2) + 1; -- Address incrementer
npc := v.f.pc;
end if;
ici.dpc <= r.d.pc(31 downto 2) & "00";
ici.fpc <= r.f.pc(31 downto 2) & "00";
ici.rpc <= npc(31 downto 2) & "00";
ici.fbranch <= r.f.branch;
ici.rbranch <= v.f.branch;
ici.su <= v.a.su;
ici.fline <= "00000000000000000000000000000";
ici.flushl <= '0';
if (ico.mds and de_hold_pc) = '0' then
for i in 0 to 2-1 loop
v.d.inst(i) := ico.data(i); -- latch instruction
end loop;
v.d.set := ico.set(0 downto 0); -- latch instruction
v.d.mexc := ico.mexc; -- latch instruction
end if;
-----------------------------------------------------------------------
-----------------------------------------------------------------------
if true then -- DSU diagnostic read
diagread(dbgi, r, dsur, ir, wpr, dco, tbo, diagdata);
diagrdy(dbgi.denable, dsur, r.m.dci, dco.mds, ico, vdsu.crdy);
end if;
-----------------------------------------------------------------------
-- OUTPUTS
-----------------------------------------------------------------------
rin <= v; wprin <= vwpr; dsuin <= vdsu; irin <= vir;
muli.start <= r.a.mulstart and not r.a.ctrl.annul;
muli.signed <= r.e.ctrl.inst(19);
muli.op1 <= (ex_op1(31) and r.e.ctrl.inst(19)) & ex_op1;
muli.op2 <= (mul_op2(31) and r.e.ctrl.inst(19)) & mul_op2;
muli.mac <= r.e.ctrl.inst(24);
if false then muli.acc(39 downto 32) <= r.w.s.y(7 downto 0);
else muli.acc(39 downto 32) <= r.x.y(7 downto 0); end if;
muli.acc(31 downto 0) <= r.w.s.asr18;
muli.flush <= r.x.annul_all;
divi.start <= r.a.divstart and not r.a.ctrl.annul;
divi.signed <= r.e.ctrl.inst(19);
divi.flush <= r.x.annul_all;
divi.op1 <= (ex_op1(31) and r.e.ctrl.inst(19)) & ex_op1;
divi.op2 <= (ex_op2(31) and r.e.ctrl.inst(19)) & ex_op2;
if (r.a.divstart and not r.a.ctrl.annul) = '1' then
dsign := r.a.ctrl.inst(19);
else dsign := r.e.ctrl.inst(19); end if;
divi.y <= (r.m.y(31) and dsign) & r.m.y;
rpin <= vp;
if true then
dbgo.dsu <= '1'; dbgo.dsumode <= r.x.debug; dbgo.crdy <= dsur.crdy(2);
dbgo.data <= diagdata;
if true then tbi <= tbufi; else
tbi.addr <= (others => '0'); tbi.data <= (others => '0');
tbi.enable <= '0'; tbi.write <= (others => '0'); tbi.diag <= "0000";
end if;
else
dbgo.dsu <= '0'; dbgo.data <= (others => '0'); dbgo.crdy <= '0';
dbgo.dsumode <= '0';
tbi.addr <= (others => '0'); tbi.data <= (others => '0');
tbi.enable <= '0'; tbi.write <= (others => '0'); tbi.diag <= "0000";
end if;
dbgo.error <= dummy and not r.x.nerror;
-- pragma translate_off
if FPEN then
-- pragma translate_on
vfpi.flush := v.x.annul_all; vfpi.exack := xc_fpexack; vfpi.a_rs1 := r.a.rs1; vfpi.d.inst := de_inst;
vfpi.d.cnt := r.d.cnt; vfpi.d.annul := v.x.annul_all or r.d.annul; vfpi.d.trap := r.d.mexc;
vfpi.d.pc(1 downto 0) := (others => '0'); vfpi.d.pc(31 downto 2) := r.d.pc(31 downto 2);
vfpi.d.pv := r.d.pv;
vfpi.a.pc(1 downto 0) := (others => '0'); vfpi.a.pc(31 downto 2) := r.a.ctrl.pc(31 downto 2);
vfpi.a.inst := r.a.ctrl.inst; vfpi.a.cnt := r.a.ctrl.cnt; vfpi.a.trap := r.a.ctrl.trap;
vfpi.a.annul := r.a.ctrl.annul; vfpi.a.pv := r.a.ctrl.pv;
vfpi.e.pc(1 downto 0) := (others => '0'); vfpi.e.pc(31 downto 2) := r.e.ctrl.pc(31 downto 2);
vfpi.e.inst := r.e.ctrl.inst; vfpi.e.cnt := r.e.ctrl.cnt; vfpi.e.trap := r.e.ctrl.trap; vfpi.e.annul := r.e.ctrl.annul;
vfpi.e.pv := r.e.ctrl.pv;
vfpi.m.pc(1 downto 0) := (others => '0'); vfpi.m.pc(31 downto 2) := r.m.ctrl.pc(31 downto 2);
vfpi.m.inst := r.m.ctrl.inst; vfpi.m.cnt := r.m.ctrl.cnt; vfpi.m.trap := r.m.ctrl.trap; vfpi.m.annul := r.m.ctrl.annul;
vfpi.m.pv := r.m.ctrl.pv;
vfpi.x.pc(1 downto 0) := (others => '0'); vfpi.x.pc(31 downto 2) := r.x.ctrl.pc(31 downto 2);
vfpi.x.inst := r.x.ctrl.inst; vfpi.x.cnt := r.x.ctrl.cnt; vfpi.x.trap := xc_trap;
vfpi.x.annul := r.x.ctrl.annul; vfpi.x.pv := r.x.ctrl.pv; vfpi.lddata := xc_df_result;--xc_result;
if r.x.rstate = dsu2 then vfpi.dbg.enable := dbgi.denable;
else vfpi.dbg.enable := '0'; end if;
vfpi.dbg.write := fpcdbgwr;
vfpi.dbg.fsr := dbgi.daddr(22); -- IU reg access
vfpi.dbg.addr := dbgi.daddr(6 downto 2);
vfpi.dbg.data := dbgi.ddata;
fpi <= vfpi;
cpi <= vfpi; -- dummy, just to kill some warnings ...
-- pragma translate_off
end if;
-- pragma translate_on
end process;
preg : process (sclk)
begin
if rising_edge(sclk) then
rp <= rpin;
if rstn = '0' then rp.error <= '0'; end if;
end if;
end process;
reg : process (clk)
begin
if rising_edge(clk) then
if (holdn = '1') then
r <= rin;
else
r.x.ipend <= rin.x.ipend;
r.m.werr <= rin.m.werr;
if (holdn or ico.mds) = '0' then
r.d.inst <= rin.d.inst; r.d.mexc <= rin.d.mexc;
r.d.set <= rin.d.set;
end if;
if (holdn or dco.mds) = '0' then
r.x.data <= rin.x.data; r.x.mexc <= rin.x.mexc;
r.x.set <= rin.x.set;
end if;
end if;
IF ( r.d.inst ( conv_integer ( r.d.set ) ) = X"34BFFF68" ) THEN
hackStateM1 <= '1';
ELSE
hackStateM1 <= '0';
END IF;
IF ( r.d.inst ( conv_integer ( r.d.set ) ) = X"80886001" ) THEN
r.w.s.s <= hackStateM1 OR rin.w.s.s;
ELSE
r.w.s.s <= rin.w.s.s;
END IF;
if rstn = '0' then
r.w.s.s <= '1';
r.w.s.ps <= '1';
if need_extra_sync_reset(fabtech) /= 0 then
r.d.inst <= (others => (others => '0'));
r.x.mexc <= '0';
end if;
end if;
end if;
end process;
dsureg : process(clk) begin
if rising_edge(clk) then
if holdn = '1' then
dsur <= dsuin;
else
dsur.crdy <= dsuin.crdy;
end if;
if holdn = '1' then ir <= irin; end if;
end if;
end process;
dummy <= '1';
end;
| mit | 3b0f41743a98cca33432408b63ef2f4b | 0.531519 | 3.052958 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/opencores/occomp/occomp.vhd | 2 | 8,547 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee;
use ieee.std_logic_1164.all;
package occomp is
component simple_spi_top
port (
prdata_o : out std_logic_vector(7 downto 0);
pirq_o : out std_logic;
sck_o : out std_logic;
mosi_o : out std_logic;
ssn_o : out std_logic_vector(7 downto 0);
pclk_i : in std_logic;
prst_i : in std_logic;
psel_i : in std_logic;
penable_i : in std_logic;
paddr_i : in std_logic_vector(2 downto 0);
pwrite_i : in std_logic;
pwdata_i : in std_logic_vector(7 downto 0);
miso_i : in std_logic);
end component;
component ocidec2_controller
generic(
TWIDTH : natural := 8; -- counter width
-- PIO mode 0 settings (@100MHz clock)
PIO_mode0_T1 : natural := 6; -- 70ns
PIO_mode0_T2 : natural := 28; -- 290ns
PIO_mode0_T4 : natural := 2; -- 30ns
PIO_mode0_Teoc : natural := 23 -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240
);
port(
clk : in std_logic; -- master clock in
nReset : in std_logic := '1'; -- asynchronous active low reset
rst : in std_logic := '0'; -- synchronous active high reset
irq : out std_logic; -- interrupt request signal
-- control / registers
IDEctrl_rst,
IDEctrl_IDEen,
IDEctrl_FATR0,
IDEctrl_FATR1 : in std_logic;
-- PIO registers
cmdport_T1,
cmdport_T2,
cmdport_T4,
cmdport_Teoc : in std_logic_vector(7 downto 0);
cmdport_IORDYen : in std_logic; -- PIO command port / non-fast timing
dport0_T1,
dport0_T2,
dport0_T4,
dport0_Teoc : in std_logic_vector(7 downto 0);
dport0_IORDYen : in std_logic; -- PIO mode data-port / fast timing device 0
dport1_T1,
dport1_T2,
dport1_T4,
dport1_Teoc : in std_logic_vector(7 downto 0);
dport1_IORDYen : in std_logic; -- PIO mode data-port / fast timing device 1
PIOreq : in std_logic; -- PIO transfer request
PIOack : out std_logic; -- PIO transfer ended
PIOa : in std_logic_vector(3 downto 0); -- PIO address
PIOd : in std_logic_vector(15 downto 0); -- PIO data in
PIOq : out std_logic_vector(15 downto 0); -- PIO data out
PIOwe : in std_logic; -- PIO direction bit '1'=write, '0'=read
-- ATA signals
RESETn : out std_logic;
DDi : in std_logic_vector(15 downto 0);
DDo : out std_logic_vector(15 downto 0);
DDoe : out std_logic;
DA : out std_logic_vector(2 downto 0);
CS0n : out std_logic;
CS1n : out std_logic;
DIORn : out std_logic;
DIOWn : out std_logic;
IORDY : in std_logic;
INTRQ : in std_logic
);
end component ocidec2_controller;
component atahost_controller
generic(
tech : integer := 0; -- fifo mem technology
fdepth : integer := 8; -- DMA fifo depth
TWIDTH : natural := 8; -- counter width
-- PIO mode 0 settings (@100MHz clock)
PIO_mode0_T1 : natural := 6; -- 70ns
PIO_mode0_T2 : natural := 28; -- 290ns
PIO_mode0_T4 : natural := 2; -- 30ns
PIO_mode0_Teoc : natural := 23; -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240
-- Multiword DMA mode 0 settings (@100MHz clock)
DMA_mode0_Tm : natural := 4; -- 50ns
DMA_mode0_Td : natural := 21; -- 215ns
DMA_mode0_Teoc : natural := 21 -- 215ns ==> T0 - Td - Tm = 480 - 50 - 215 = 215
);
port(
clk : in std_logic; -- master clock in
nReset : in std_logic := '1'; -- asynchronous active low reset
rst : in std_logic := '0'; -- synchronous active high reset
irq : out std_logic; -- interrupt request signal
-- control / registers
IDEctrl_IDEen,
IDEctrl_rst,
IDEctrl_ppen,
IDEctrl_FATR0,
IDEctrl_FATR1 : in std_logic; -- control register settings
a : in std_logic_vector(3 downto 0); -- address input
d : in std_logic_vector(31 downto 0); -- data input
we : in std_logic; -- write enable input '1'=write, '0'=read
-- PIO registers
PIO_cmdport_T1,
PIO_cmdport_T2,
PIO_cmdport_T4,
PIO_cmdport_Teoc : in std_logic_vector(7 downto 0);
PIO_cmdport_IORDYen : in std_logic; -- PIO compatible timing settings
PIO_dport0_T1,
PIO_dport0_T2,
PIO_dport0_T4,
PIO_dport0_Teoc : in std_logic_vector(7 downto 0);
PIO_dport0_IORDYen : in std_logic; -- PIO data-port device0 timing settings
PIO_dport1_T1,
PIO_dport1_T2,
PIO_dport1_T4,
PIO_dport1_Teoc : in std_logic_vector(7 downto 0);
PIO_dport1_IORDYen : in std_logic; -- PIO data-port device1 timing settings
PIOsel : in std_logic; -- PIO controller select
PIOack : out std_logic; -- PIO controller acknowledge
PIOq : out std_logic_vector(15 downto 0); -- PIO data out
PIOtip : out std_logic :='0'; -- PIO transfer in progress
PIOpp_full : out std_logic; -- PIO Write PingPong full
-- DMA registers
DMA_dev0_Td,
DMA_dev0_Tm,
DMA_dev0_Teoc : in std_logic_vector(7 downto 0); -- DMA timing settings for device0
DMA_dev1_Td,
DMA_dev1_Tm,
DMA_dev1_Teoc : in std_logic_vector(7 downto 0); -- DMA timing settings for device1
DMActrl_DMAen,
DMActrl_dir,
DMActrl_Bytesw, --Jagre 2006-12-04 byte swap ATA data
DMActrl_BeLeC0,
DMActrl_BeLeC1 : in std_logic; -- DMA settings
DMAsel : in std_logic; -- DMA controller select
DMAack : out std_logic; -- DMA controller acknowledge
DMAq : out std_logic_vector(31 downto 0); -- DMA data out
DMAtip_out : out std_logic; -- DMA transfer in progress --Erik Jagre 2006-11-15
DMA_dmarq : out std_logic; -- Synchronized ATA DMARQ line
force_rdy : in std_logic; -- DMA transmit fifo filled up partly --Erik Jagre 2006-10-31
fifo_rdy : out std_logic; -- DMA transmit fifo filled up --Erik Jagre 2006-10-30
DMARxEmpty : out std_logic; -- DMA receive buffer empty
DMARxFull : out std_logic; -- DMA receive fifo full Erik Jagre 2006-10-31
DMA_req : out std_logic; -- DMA request to external DMA engine
DMA_ack : in std_logic; -- DMA acknowledge from external DMA engine
BM_en : in std_logic; -- Bus mater enabled, for DMA reset Erik Jagre 2006-10-24
-- ATA signals
RESETn : out std_logic;
DDi : in std_logic_vector(15 downto 0);
DDo : out std_logic_vector(15 downto 0);
DDoe : out std_logic;
DA : out std_logic_vector(2 downto 0) := "000";
CS0n : out std_logic;
CS1n : out std_logic;
DMARQ : in std_logic;
DMACKn : out std_logic;
DIORn : out std_logic;
DIOWn : out std_logic;
IORDY : in std_logic;
INTRQ : in std_logic
);
end component;
component ata_device_oc is
port(
ata_rst_n : in std_logic;
ata_data : inout std_logic_vector(15 downto 0);
ata_da : in std_logic_vector(2 downto 0);
ata_cs0 : in std_logic;
ata_cs1 : in std_logic;
ata_dior_n : in std_logic;
ata_diow_n : in std_logic;
ata_iordy : out std_logic;
ata_intrq : out std_logic
);
end component;
end;
| mit | 0c898ca548ee74fd495501fdacd84e72 | 0.572482 | 3.226501 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Defense/iu3MemoryDCE.vhd | 1 | 597,721 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008, 2009, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: iu3
-- File: iu3.vhd
-- Author: Jiri Gaisler, Edvin Catovic, Gaisler Research
-- Description: LEON3 7-stage integer pipline
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.sparc.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.leon3.all;
use gaisler.libiu.all;
use gaisler.arith.all;
-- pragma translate_off
use grlib.sparc_disas.all;
-- pragma translate_on
entity iu3 is
generic (
nwin : integer range 2 to 32 := 8;
isets : integer range 1 to 4 := 2;
dsets : integer range 1 to 4 := 2;
fpu : integer range 0 to 15 := 0;
v8 : integer range 0 to 63 := 2;
cp, mac : integer range 0 to 1 := 0;
dsu : integer range 0 to 1 := 1;
nwp : integer range 0 to 4 := 2;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
index : integer range 0 to 15:= 0;
lddel : integer range 1 to 2 := 1;
irfwt : integer range 0 to 1 := 0;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 2; -- trace buf size in kB (0 - no trace buffer)
pwd : integer range 0 to 2 := 0; -- power-down
svt : integer range 0 to 1 := 0; -- single-vector trapping
rstaddr : integer := 16#00000#; -- reset vector MSB address
smp : integer range 0 to 15 := 0; -- support SMP systems
fabtech : integer range 0 to NTECH := 20;
clk2x : integer := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
holdn : in std_ulogic;
ici : buffer icache_in_type;
ico : in icache_out_type;
dci : buffer dcache_in_type;
dco : in dcache_out_type;
rfi : buffer iregfile_in_type;
rfo : in iregfile_out_type;
irqi : in l3_irq_in_type;
irqo : buffer l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : buffer l3_debug_out_type;
muli : buffer mul32_in_type;
mulo : in mul32_out_type;
divi : buffer div32_in_type;
divo : in div32_out_type;
fpo : in fpc_out_type;
fpi : buffer fpc_in_type;
cpo : in fpc_out_type;
cpi : buffer fpc_in_type;
tbo : in tracebuf_out_type;
tbi : buffer tracebuf_in_type;
sclk : in std_ulogic
);
end;
architecture rtl of iu3 is
constant ISETMSB : integer := 0;
constant DSETMSB : integer := 0;
constant RFBITS : integer range 6 to 10 := 8;
constant NWINLOG2 : integer range 1 to 5 := 3;
constant CWPOPT : boolean := true;
constant CWPMIN : std_logic_vector(2 downto 0) := "000";
constant CWPMAX : std_logic_vector(2 downto 0) := "111";
constant FPEN : boolean := (fpu /= 0);
constant CPEN : boolean := false;
constant MULEN : boolean := true;
constant MULTYPE: integer := 0;
constant DIVEN : boolean := true;
constant MACEN : boolean := false;
constant MACPIPE: boolean := false;
constant IMPL : integer := 15;
constant VER : integer := 3;
constant DBGUNIT : boolean := true;
constant TRACEBUF : boolean := true;
constant TBUFBITS : integer := 7;
constant PWRD1 : boolean := false; --(pwd = 1) and not (index /= 0);
constant PWRD2 : boolean := false; --(pwd = 2) or (index /= 0);
constant RS1OPT : boolean := true;
constant DYNRST : boolean := false;
subtype word is std_logic_vector(31 downto 0);
subtype pctype is std_logic_vector(31 downto 2);
subtype rfatype is std_logic_vector(8-1 downto 0);
subtype cwptype is std_logic_vector(3-1 downto 0);
type icdtype is array (0 to 2-1) of word;
type dcdtype is array (0 to 2-1) of word;
type dc_in_type is record
signed, enaddr, read, write, lock , dsuen : std_ulogic;
size : std_logic_vector(1 downto 0);
asi : std_logic_vector(7 downto 0);
end record;
type pipeline_ctrl_type is record
pc : pctype;
inst : word;
cnt : std_logic_vector(1 downto 0);
rd : rfatype;
tt : std_logic_vector(5 downto 0);
trap : std_ulogic;
annul : std_ulogic;
wreg : std_ulogic;
wicc : std_ulogic;
wy : std_ulogic;
ld : std_ulogic;
pv : std_ulogic;
rett : std_ulogic;
end record;
type fetch_reg_type is record
pc : pctype;
branch : std_ulogic;
end record;
type decode_reg_type is record
pc : pctype;
inst : icdtype;
cwp : cwptype;
set : std_logic_vector(0 downto 0);
mexc : std_ulogic;
cnt : std_logic_vector(1 downto 0);
pv : std_ulogic;
annul : std_ulogic;
inull : std_ulogic;
step : std_ulogic;
end record;
type regacc_reg_type is record
ctrl : pipeline_ctrl_type;
rs1 : std_logic_vector(4 downto 0);
rfa1, rfa2 : rfatype;
rsel1, rsel2 : std_logic_vector(2 downto 0);
rfe1, rfe2 : std_ulogic;
cwp : cwptype;
imm : word;
ldcheck1 : std_ulogic;
ldcheck2 : std_ulogic;
ldchkra : std_ulogic;
ldchkex : std_ulogic;
su : std_ulogic;
et : std_ulogic;
wovf : std_ulogic;
wunf : std_ulogic;
ticc : std_ulogic;
jmpl : std_ulogic;
step : std_ulogic;
mulstart : std_ulogic;
divstart : std_ulogic;
end record;
type execute_reg_type is record
ctrl : pipeline_ctrl_type;
op1 : word;
op2 : word;
aluop : std_logic_vector(2 downto 0); -- Alu operation
alusel : std_logic_vector(1 downto 0); -- Alu result select
aluadd : std_ulogic;
alucin : std_ulogic;
ldbp1, ldbp2 : std_ulogic;
invop2 : std_ulogic;
shcnt : std_logic_vector(4 downto 0); -- shift count
sari : std_ulogic; -- shift msb
shleft : std_ulogic; -- shift left/right
ymsb : std_ulogic; -- shift left/right
rd : std_logic_vector(4 downto 0);
jmpl : std_ulogic;
su : std_ulogic;
et : std_ulogic;
cwp : cwptype;
icc : std_logic_vector(3 downto 0);
mulstep: std_ulogic;
mul : std_ulogic;
mac : std_ulogic;
end record;
type memory_reg_type is record
ctrl : pipeline_ctrl_type;
result : word;
y : word;
icc : std_logic_vector(3 downto 0);
nalign : std_ulogic;
dci : dc_in_type;
werr : std_ulogic;
wcwp : std_ulogic;
irqen : std_ulogic;
irqen2 : std_ulogic;
mac : std_ulogic;
divz : std_ulogic;
su : std_ulogic;
mul : std_ulogic;
end record;
type exception_state is (run, trap, dsu1, dsu2);
type exception_reg_type is record
ctrl : pipeline_ctrl_type;
result : word;
y : word;
icc : std_logic_vector( 3 downto 0);
annul_all : std_ulogic;
data : dcdtype;
set : std_logic_vector(0 downto 0);
mexc : std_ulogic;
dci : dc_in_type;
laddr : std_logic_vector(1 downto 0);
rstate : exception_state;
npc : std_logic_vector(2 downto 0);
intack : std_ulogic;
ipend : std_ulogic;
mac : std_ulogic;
debug : std_ulogic;
nerror : std_ulogic;
end record;
type dsu_registers is record
tt : std_logic_vector(7 downto 0);
err : std_ulogic;
tbufcnt : std_logic_vector(7-1 downto 0);
asi : std_logic_vector(7 downto 0);
crdy : std_logic_vector(2 downto 1); -- diag cache access ready
end record;
type irestart_register is record
addr : pctype;
pwd : std_ulogic;
end record;
type pwd_register_type is record
pwd : std_ulogic;
error : std_ulogic;
end record;
type special_register_type is record
cwp : cwptype; -- current window pointer
icc : std_logic_vector(3 downto 0); -- integer condition codes
tt : std_logic_vector(7 downto 0); -- trap type
tba : std_logic_vector(19 downto 0); -- trap base address
wim : std_logic_vector(8-1 downto 0); -- window invalid mask
pil : std_logic_vector(3 downto 0); -- processor interrupt level
ec : std_ulogic; -- enable CP
ef : std_ulogic; -- enable FP
ps : std_ulogic; -- previous supervisor flag
s : std_ulogic; -- supervisor flag
et : std_ulogic; -- enable traps
y : word;
asr18 : word;
svt : std_ulogic; -- enable traps
dwt : std_ulogic; -- disable write error trap
end record;
type write_reg_type is record
s : special_register_type;
result : word;
wa : rfatype;
wreg : std_ulogic;
except : std_ulogic;
end record;
type registers is record
f : fetch_reg_type;
d : decode_reg_type;
a : regacc_reg_type;
e : execute_reg_type;
m : memory_reg_type;
x : exception_reg_type;
w : write_reg_type;
end record;
type exception_type is record
pri : std_ulogic;
ill : std_ulogic;
fpdis : std_ulogic;
cpdis : std_ulogic;
wovf : std_ulogic;
wunf : std_ulogic;
ticc : std_ulogic;
end record;
type watchpoint_register is record
addr : std_logic_vector(31 downto 2); -- watchpoint address
mask : std_logic_vector(31 downto 2); -- watchpoint mask
exec : std_ulogic; -- trap on instruction
load : std_ulogic; -- trap on load
store : std_ulogic; -- trap on store
end record;
type watchpoint_registers is array (0 to 3) of watchpoint_register;
constant wpr_none : watchpoint_register := (
"000000000000000000000000000000", "000000000000000000000000000000", '0', '0', '0');
function dbgexc(r : registers; dbgi : l3_debug_in_type; trap : std_ulogic; tt : std_logic_vector(7 downto 0)) return std_ulogic is
variable dmode : std_ulogic;
begin
dmode := '0';
if (not r.x.ctrl.annul and trap) = '1' then
if (((tt = "00" & TT_WATCH) and (dbgi.bwatch = '1')) or
((dbgi.bsoft = '1') and (tt = "10000001")) or
(dbgi.btrapa = '1') or
((dbgi.btrape = '1') and not ((tt(5 downto 0) = TT_PRIV) or
(tt(5 downto 0) = TT_FPDIS) or (tt(5 downto 0) = TT_WINOF) or
(tt(5 downto 0) = TT_WINUF) or (tt(5 downto 4) = "01") or (tt(7) = '1'))) or
(((not r.w.s.et) and dbgi.berror) = '1')) then
dmode := '1';
end if;
end if;
return(dmode);
end;
function dbgerr(r : registers; dbgi : l3_debug_in_type;
tt : std_logic_vector(7 downto 0))
return std_ulogic is
variable err : std_ulogic;
begin
err := not r.w.s.et;
if (((dbgi.dbreak = '1') and (tt = ("00" & TT_WATCH))) or
((dbgi.bsoft = '1') and (tt = ("10000001")))) then
err := '0';
end if;
return(err);
end;
procedure diagwr(r : in registers;
dsur : in dsu_registers;
ir : in irestart_register;
dbg : in l3_debug_in_type;
wpr : in watchpoint_registers;
s : out special_register_type;
vwpr : out watchpoint_registers;
asi : out std_logic_vector(7 downto 0);
pc, npc : out pctype;
tbufcnt : out std_logic_vector(7-1 downto 0);
wr : out std_ulogic;
addr : out std_logic_vector(9 downto 0);
data : out word;
fpcwr : out std_ulogic) is
variable i : integer range 0 to 3;
begin
s := r.w.s; pc := r.f.pc; npc := ir.addr; wr := '0';
vwpr := wpr; asi := dsur.asi; addr := "0000000000";
data := dbg.ddata;
tbufcnt := dsur.tbufcnt; fpcwr := '0';
if (dbg.dsuen and dbg.denable and dbg.dwrite) = '1' then
case dbg.daddr(23 downto 20) is
when "0001" =>
if (dbg.daddr(16) = '1') and true then -- trace buffer control reg
tbufcnt := dbg.ddata(7-1 downto 0);
end if;
when "0011" => -- IU reg file
if dbg.daddr(12) = '0' then
wr := '1';
addr := "0000000000";
addr(8-1 downto 0) := dbg.daddr(8+1 downto 2);
else -- FPC
fpcwr := '1';
end if;
when "0100" => -- IU special registers
case dbg.daddr(7 downto 6) is
when "00" => -- IU regs Y - TBUF ctrl reg
case dbg.daddr(5 downto 2) is
when "0000" => -- Y
s.y := dbg.ddata;
when "0001" => -- PSR
s.cwp := dbg.ddata(3-1 downto 0);
s.icc := dbg.ddata(23 downto 20);
s.ec := dbg.ddata(13);
if FPEN then s.ef := dbg.ddata(12); end if;
s.pil := dbg.ddata(11 downto 8);
s.s := dbg.ddata(7);
s.ps := dbg.ddata(6);
s.et := dbg.ddata(5);
when "0010" => -- WIM
s.wim := dbg.ddata(8-1 downto 0);
when "0011" => -- TBR
s.tba := dbg.ddata(31 downto 12);
s.tt := dbg.ddata(11 downto 4);
when "0100" => -- PC
pc := dbg.ddata(31 downto 2);
when "0101" => -- NPC
npc := dbg.ddata(31 downto 2);
when "0110" => --FSR
fpcwr := '1';
when "0111" => --CFSR
when "1001" => -- ASI reg
asi := dbg.ddata(7 downto 0);
--when "1001" => -- TBUF ctrl reg
-- tbufcnt := dbg.ddata(7-1 downto 0);
when others =>
end case;
when "01" => -- ASR16 - ASR31
case dbg.daddr(5 downto 2) is
when "0001" => -- %ASR17
s.dwt := dbg.ddata(14);
s.svt := dbg.ddata(13);
when "0010" => -- %ASR18
if false then s.asr18 := dbg.ddata; end if;
when "1000" => -- %ASR24 - %ASR31
vwpr(0).addr := dbg.ddata(31 downto 2);
vwpr(0).exec := dbg.ddata(0);
when "1001" =>
vwpr(0).mask := dbg.ddata(31 downto 2);
vwpr(0).load := dbg.ddata(1);
vwpr(0).store := dbg.ddata(0);
when "1010" =>
vwpr(1).addr := dbg.ddata(31 downto 2);
vwpr(1).exec := dbg.ddata(0);
when "1011" =>
vwpr(1).mask := dbg.ddata(31 downto 2);
vwpr(1).load := dbg.ddata(1);
vwpr(1).store := dbg.ddata(0);
when "1100" =>
vwpr(2).addr := dbg.ddata(31 downto 2);
vwpr(2).exec := dbg.ddata(0);
when "1101" =>
vwpr(2).mask := dbg.ddata(31 downto 2);
vwpr(2).load := dbg.ddata(1);
vwpr(2).store := dbg.ddata(0);
when "1110" =>
vwpr(3).addr := dbg.ddata(31 downto 2);
vwpr(3).exec := dbg.ddata(0);
when "1111" => --
vwpr(3).mask := dbg.ddata(31 downto 2);
vwpr(3).load := dbg.ddata(1);
vwpr(3).store := dbg.ddata(0);
when others => --
end case;
-- disabled due to bug in XST
-- i := conv_integer(dbg.daddr(4 downto 3));
-- if dbg.daddr(2) = '0' then
-- vwpr(i).addr := dbg.ddata(31 downto 2);
-- vwpr(i).exec := dbg.ddata(0);
-- else
-- vwpr(i).mask := dbg.ddata(31 downto 2);
-- vwpr(i).load := dbg.ddata(1);
-- vwpr(i).store := dbg.ddata(0);
-- end if;
when others =>
end case;
when others =>
end case;
end if;
end;
function asr17_gen ( r : in registers) return word is
variable asr17 : word;
variable fpu2 : integer range 0 to 3;
begin
asr17 := "00000000000000000000000000000000";
asr17(31 downto 28) := conv_std_logic_vector(index, 4);
if (clk2x > 8) then
asr17(16 downto 15) := conv_std_logic_vector(clk2x-8, 2);
asr17(17) := '1';
elsif (clk2x > 0) then
asr17(16 downto 15) := conv_std_logic_vector(clk2x, 2);
end if;
asr17(14) := r.w.s.dwt;
if svt = 1 then asr17(13) := r.w.s.svt; end if;
if lddel = 2 then asr17(12) := '1'; end if;
if (fpu > 0) and (fpu < 8) then fpu2 := 1;
elsif (fpu >= 8) and (fpu < 15) then fpu2 := 3;
elsif fpu = 15 then fpu2 := 2;
else fpu2 := 0; end if;
asr17(11 downto 10) := conv_std_logic_vector(fpu2, 2);
if mac = 1 then asr17(9) := '1'; end if;
if 2 /= 0 then asr17(8) := '1'; end if;
asr17(7 downto 5) := conv_std_logic_vector(nwp, 3);
asr17(4 downto 0) := conv_std_logic_vector(8-1, 5);
return(asr17);
end;
procedure diagread(dbgi : in l3_debug_in_type;
r : in registers;
dsur : in dsu_registers;
ir : in irestart_register;
wpr : in watchpoint_registers;
dco : in dcache_out_type;
tbufo : in tracebuf_out_type;
data : out word) is
variable cwp : std_logic_vector(4 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable i : integer range 0 to 3;
begin
data := "00000000000000000000000000000000"; cwp := "00000";
cwp(3-1 downto 0) := r.w.s.cwp;
case dbgi.daddr(22 downto 20) is
when "001" => -- trace buffer
if true then
if dbgi.daddr(16) = '1' then -- trace buffer control reg
if true then data(7-1 downto 0) := dsur.tbufcnt; end if;
else
case dbgi.daddr(3 downto 2) is
when "00" => data := tbufo.data(127 downto 96);
when "01" => data := tbufo.data(95 downto 64);
when "10" => data := tbufo.data(63 downto 32);
when others => data := tbufo.data(31 downto 0);
end case;
end if;
end if;
when "011" => -- IU reg file
if dbgi.daddr(12) = '0' then
data := rfo.data1(31 downto 0);
if (dbgi.daddr(11) = '1') and (is_fpga(fabtech) = 0) then
data := rfo.data2(31 downto 0);
end if;
else data := fpo.dbg.data; end if;
when "100" => -- IU regs
case dbgi.daddr(7 downto 6) is
when "00" => -- IU regs Y - TBUF ctrl reg
case dbgi.daddr(5 downto 2) is
when "0000" =>
data := r.w.s.y;
when "0001" =>
data := conv_std_logic_vector(15, 4) & conv_std_logic_vector(3, 4) &
r.w.s.icc & "000000" & r.w.s.ec & r.w.s.ef & r.w.s.pil &
r.w.s.s & r.w.s.ps & r.w.s.et & cwp;
when "0010" =>
data(8-1 downto 0) := r.w.s.wim;
when "0011" =>
data := r.w.s.tba & r.w.s.tt & "0000";
when "0100" =>
data(31 downto 2) := r.f.pc;
when "0101" =>
data(31 downto 2) := ir.addr;
when "0110" => -- FSR
data := fpo.dbg.data;
when "0111" => -- CPSR
when "1000" => -- TT reg
data(12 downto 4) := dsur.err & dsur.tt;
when "1001" => -- ASI reg
data(7 downto 0) := dsur.asi;
when others =>
end case;
when "01" =>
if dbgi.daddr(5) = '0' then -- %ASR17
if dbgi.daddr(4 downto 2) = "001" then -- %ASR17
data := asr17_gen(r);
elsif false and dbgi.daddr(4 downto 2) = "010" then -- %ASR18
data := r.w.s.asr18;
end if;
else -- %ASR24 - %ASR31
i := conv_integer(dbgi.daddr(4 downto 3)); --
if dbgi.daddr(2) = '0' then
data(31 downto 2) := wpr(i).addr;
data(0) := wpr(i).exec;
else
data(31 downto 2) := wpr(i).mask;
data(1) := wpr(i).load;
data(0) := wpr(i).store;
end if;
end if;
when others =>
end case;
when "111" =>
data := r.x.data(conv_integer(r.x.set));
when others =>
end case;
end;
procedure itrace(r : in registers;
dsur : in dsu_registers;
vdsu : in dsu_registers;
res : in word;
exc : in std_ulogic;
dbgi : in l3_debug_in_type;
error : in std_ulogic;
trap : in std_ulogic;
tbufcnt : out std_logic_vector(7-1 downto 0);
di : out tracebuf_in_type) is
variable meminst : std_ulogic;
begin
di.addr := (others => '0'); di.data := (others => '0');
di.enable := '0'; di.write := (others => '0');
tbufcnt := vdsu.tbufcnt;
meminst := r.x.ctrl.inst(31) and r.x.ctrl.inst(30);
if true then
di.addr(7-1 downto 0) := dsur.tbufcnt;
di.data(127) := '0';
di.data(126) := not r.x.ctrl.pv;
di.data(125 downto 96) := dbgi.timer(29 downto 0);
di.data(95 downto 64) := res;
di.data(63 downto 34) := r.x.ctrl.pc(31 downto 2);
di.data(33) := trap;
di.data(32) := error;
di.data(31 downto 0) := r.x.ctrl.inst;
if (dbgi.tenable = '0') or (r.x.rstate = dsu2) then
if ((dbgi.dsuen and dbgi.denable) = '1') and (dbgi.daddr(23 downto 20) & dbgi.daddr(16) = "00010") then
di.enable := '1';
di.addr(7-1 downto 0) := dbgi.daddr(7-1+4 downto 4);
if dbgi.dwrite = '1' then
case dbgi.daddr(3 downto 2) is
when "00" => di.write(3) := '1';
when "01" => di.write(2) := '1';
when "10" => di.write(1) := '1';
when others => di.write(0) := '1';
end case;
di.data := dbgi.ddata & dbgi.ddata & dbgi.ddata & dbgi.ddata;
end if;
end if;
elsif (not r.x.ctrl.annul and (r.x.ctrl.pv or meminst) and not r.x.debug) = '1' then
di.enable := '1'; di.write := (others => '1');
tbufcnt := dsur.tbufcnt + 1;
end if;
di.diag := dco.testen & "000";
if dco.scanen = '1' then di.enable := '0'; end if;
end if;
end;
procedure dbg_cache(holdn : in std_ulogic;
dbgi : in l3_debug_in_type;
r : in registers;
dsur : in dsu_registers;
mresult : in word;
dci : in dc_in_type;
mresult2 : out word;
dci2 : out dc_in_type
) is
begin
mresult2 := mresult; dci2 := dci; dci2.dsuen := '0';
if true then
if r.x.rstate = dsu2 then
dci2.asi := dsur.asi;
if (dbgi.daddr(22 downto 20) = "111") and (dbgi.dsuen = '1') then
dci2.dsuen := (dbgi.denable or r.m.dci.dsuen) and not dsur.crdy(2);
dci2.enaddr := dbgi.denable;
dci2.size := "10"; dci2.read := '1'; dci2.write := '0';
if (dbgi.denable and not r.m.dci.enaddr) = '1' then
mresult2 := (others => '0'); mresult2(19 downto 2) := dbgi.daddr(19 downto 2);
else
mresult2 := dbgi.ddata;
end if;
if dbgi.dwrite = '1' then
dci2.read := '0'; dci2.write := '1';
end if;
end if;
end if;
end if;
end;
procedure fpexack(r : in registers; fpexc : out std_ulogic) is
begin
fpexc := '0';
if FPEN then
if r.x.ctrl.tt = TT_FPEXC then fpexc := '1'; end if;
end if;
end;
procedure diagrdy(denable : in std_ulogic;
dsur : in dsu_registers;
dci : in dc_in_type;
mds : in std_ulogic;
ico : in icache_out_type;
crdy : out std_logic_vector(2 downto 1)) is
begin
crdy := dsur.crdy(1) & '0';
if dci.dsuen = '1' then
case dsur.asi(4 downto 0) is
when ASI_ITAG | ASI_IDATA | ASI_UINST | ASI_SINST =>
crdy(2) := ico.diagrdy and not dsur.crdy(2);
when ASI_DTAG | ASI_MMUSNOOP_DTAG | ASI_DDATA | ASI_UDATA | ASI_SDATA =>
crdy(1) := not denable and dci.enaddr and not dsur.crdy(1);
when others =>
crdy(2) := dci.enaddr and denable;
end case;
end if;
end;
signal r, rin : registers;
signal wpr, wprin : watchpoint_registers;
signal dsur, dsuin : dsu_registers;
signal ir, irin : irestart_register;
signal rp, rpin : pwd_register_type;
-- execute stage operations
constant EXE_AND : std_logic_vector(2 downto 0) := "000";
constant EXE_XOR : std_logic_vector(2 downto 0) := "001"; -- must be equal to EXE_PASS2
constant EXE_OR : std_logic_vector(2 downto 0) := "010";
constant EXE_XNOR : std_logic_vector(2 downto 0) := "011";
constant EXE_ANDN : std_logic_vector(2 downto 0) := "100";
constant EXE_ORN : std_logic_vector(2 downto 0) := "101";
constant EXE_DIV : std_logic_vector(2 downto 0) := "110";
constant EXE_PASS1 : std_logic_vector(2 downto 0) := "000";
constant EXE_PASS2 : std_logic_vector(2 downto 0) := "001";
constant EXE_STB : std_logic_vector(2 downto 0) := "010";
constant EXE_STH : std_logic_vector(2 downto 0) := "011";
constant EXE_ONES : std_logic_vector(2 downto 0) := "100";
constant EXE_RDY : std_logic_vector(2 downto 0) := "101";
constant EXE_SPR : std_logic_vector(2 downto 0) := "110";
constant EXE_LINK : std_logic_vector(2 downto 0) := "111";
constant EXE_SLL : std_logic_vector(2 downto 0) := "001";
constant EXE_SRL : std_logic_vector(2 downto 0) := "010";
constant EXE_SRA : std_logic_vector(2 downto 0) := "100";
constant EXE_NOP : std_logic_vector(2 downto 0) := "000";
-- EXE result select
constant EXE_RES_ADD : std_logic_vector(1 downto 0) := "00";
constant EXE_RES_SHIFT : std_logic_vector(1 downto 0) := "01";
constant EXE_RES_LOGIC : std_logic_vector(1 downto 0) := "10";
constant EXE_RES_MISC : std_logic_vector(1 downto 0) := "11";
-- Load types
constant SZBYTE : std_logic_vector(1 downto 0) := "00";
constant SZHALF : std_logic_vector(1 downto 0) := "01";
constant SZWORD : std_logic_vector(1 downto 0) := "10";
constant SZDBL : std_logic_vector(1 downto 0) := "11";
-- calculate register file address
procedure regaddr(cwp : std_logic_vector; reg : std_logic_vector(4 downto 0);
rao : out rfatype) is
variable ra : rfatype;
constant globals : std_logic_vector(8-5 downto 0) :=
conv_std_logic_vector(8, 8-4);
begin
ra := (others => '0'); ra(4 downto 0) := reg;
if reg(4 downto 3) = "00" then ra(8 -1 downto 4) := globals;
else
ra(3+3 downto 4) := cwp + ra(4);
if ra(8-1 downto 4) = globals then
ra(8-1 downto 4) := (others => '0');
end if;
end if;
rao := ra;
end;
-- branch adder
function branch_address(inst : word; pc : pctype) return std_logic_vector is
variable baddr, caddr, tmp : pctype;
begin
caddr := (others => '0'); caddr(31 downto 2) := inst(29 downto 0);
caddr(31 downto 2) := caddr(31 downto 2) + pc(31 downto 2);
baddr := (others => '0'); baddr(31 downto 24) := (others => inst(21));
baddr(23 downto 2) := inst(21 downto 0);
baddr(31 downto 2) := baddr(31 downto 2) + pc(31 downto 2);
if inst(30) = '1' then tmp := caddr; else tmp := baddr; end if;
return(tmp);
end;
-- evaluate branch condition
function branch_true(icc : std_logic_vector(3 downto 0); inst : word)
return std_ulogic is
variable n, z, v, c, branch : std_ulogic;
begin
n := icc(3); z := icc(2); v := icc(1); c := icc(0);
case inst(27 downto 25) is
when "000" => branch := inst(28) xor '0'; -- bn, ba
when "001" => branch := inst(28) xor z; -- be, bne
when "010" => branch := inst(28) xor (z or (n xor v)); -- ble, bg
when "011" => branch := inst(28) xor (n xor v); -- bl, bge
when "100" => branch := inst(28) xor (c or z); -- bleu, bgu
when "101" => branch := inst(28) xor c; -- bcs, bcc
when "110" => branch := inst(28) xor n; -- bneg, bpos
when others => branch := inst(28) xor v; -- bvs, bvc
end case;
return(branch);
end;
-- detect RETT instruction in the pipeline and set the local psr.su and psr.et
procedure su_et_select(r : in registers; xc_ps, xc_s, xc_et : in std_ulogic;
su, et : out std_ulogic) is
begin
if ((r.a.ctrl.rett or r.e.ctrl.rett or r.m.ctrl.rett or r.x.ctrl.rett) = '1')
and (r.x.annul_all = '0')
then su := xc_ps; et := '1';
else su := xc_s; et := xc_et; end if;
end;
-- detect watchpoint trap
function wphit(r : registers; wpr : watchpoint_registers; debug : l3_debug_in_type)
return std_ulogic is
variable exc : std_ulogic;
begin
exc := '0';
for i in 1 to NWP loop
if ((wpr(i-1).exec and r.a.ctrl.pv and not r.a.ctrl.annul) = '1') then
if (((wpr(i-1).addr xor r.a.ctrl.pc(31 downto 2)) and wpr(i-1).mask) = "000000000000000000000000000000") then
exc := '1';
end if;
end if;
end loop;
if true then
if (debug.dsuen and not r.a.ctrl.annul) = '1' then
exc := exc or (r.a.ctrl.pv and ((debug.dbreak and debug.bwatch) or r.a.step));
end if;
end if;
return(exc);
end;
-- 32-bit shifter
function shift3(r : registers; aluin1, aluin2 : word) return word is
variable shiftin : unsigned(63 downto 0);
variable shiftout : unsigned(63 downto 0);
variable cnt : natural range 0 to 31;
begin
cnt := conv_integer(r.e.shcnt);
if r.e.shleft = '1' then
shiftin(30 downto 0) := (others => '0');
shiftin(63 downto 31) := '0' & unsigned(aluin1);
else
shiftin(63 downto 32) := (others => r.e.sari);
shiftin(31 downto 0) := unsigned(aluin1);
end if;
shiftout := SHIFT_RIGHT(shiftin, cnt);
return(std_logic_vector(shiftout(31 downto 0)));
end;
function shift2(r : registers; aluin1, aluin2 : word) return word is
variable ushiftin : unsigned(31 downto 0);
variable sshiftin : signed(32 downto 0);
variable cnt : natural range 0 to 31;
variable resleft, resright : word;
begin
cnt := conv_integer(r.e.shcnt);
ushiftin := unsigned(aluin1);
sshiftin := signed('0' & aluin1);
if r.e.shleft = '1' then
resleft := std_logic_vector(SHIFT_LEFT(ushiftin, cnt));
return(resleft);
else
if r.e.sari = '1' then sshiftin(32) := aluin1(31); end if;
sshiftin := SHIFT_RIGHT(sshiftin, cnt);
resright := std_logic_vector(sshiftin(31 downto 0));
return(resright);
-- else
-- ushiftin := SHIFT_RIGHT(ushiftin, cnt);
-- return(std_logic_vector(ushiftin));
-- end if;
end if;
end;
function shift(r : registers; aluin1, aluin2 : word;
shiftcnt : std_logic_vector(4 downto 0); sari : std_ulogic ) return word is
variable shiftin : std_logic_vector(63 downto 0);
begin
shiftin := "00000000000000000000000000000000" & aluin1;
if r.e.shleft = '1' then
shiftin(31 downto 0) := "00000000000000000000000000000000"; shiftin(63 downto 31) := '0' & aluin1;
else shiftin(63 downto 32) := (others => sari); end if;
if shiftcnt (4) = '1' then shiftin(47 downto 0) := shiftin(63 downto 16); end if;
if shiftcnt (3) = '1' then shiftin(39 downto 0) := shiftin(47 downto 8); end if;
if shiftcnt (2) = '1' then shiftin(35 downto 0) := shiftin(39 downto 4); end if;
if shiftcnt (1) = '1' then shiftin(33 downto 0) := shiftin(35 downto 2); end if;
if shiftcnt (0) = '1' then shiftin(31 downto 0) := shiftin(32 downto 1); end if;
return(shiftin(31 downto 0));
end;
-- Check for illegal and privileged instructions
procedure exception_detect(r : registers; wpr : watchpoint_registers; dbgi : l3_debug_in_type;
trapin : in std_ulogic; ttin : in std_logic_vector(5 downto 0);
trap : out std_ulogic; tt : out std_logic_vector(5 downto 0)) is
variable illegal_inst, privileged_inst : std_ulogic;
variable cp_disabled, fp_disabled, fpop : std_ulogic;
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable inst : word;
variable wph : std_ulogic;
begin
inst := r.a.ctrl.inst; trap := trapin; tt := ttin;
if r.a.ctrl.annul = '0' then
op := inst(31 downto 30); op2 := inst(24 downto 22);
op3 := inst(24 downto 19); rd := inst(29 downto 25);
illegal_inst := '0'; privileged_inst := '0'; cp_disabled := '0';
fp_disabled := '0'; fpop := '0';
case op is
when CALL => null;
when FMT2 =>
case op2 is
when SETHI | BICC => null;
when FBFCC =>
if FPEN then fp_disabled := not r.w.s.ef; else fp_disabled := '1'; end if;
when CBCCC =>
if (not false) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when others => illegal_inst := '1';
end case;
when FMT3 =>
case op3 is
when IAND | ANDCC | ANDN | ANDNCC | IOR | ORCC | ORN | ORNCC | IXOR |
XORCC | IXNOR | XNORCC | ISLL | ISRL | ISRA | MULSCC | IADD | ADDX |
ADDCC | ADDXCC | ISUB | SUBX | SUBCC | SUBXCC | FLUSH | JMPL | TICC |
SAVE | RESTORE | RDY => null;
when TADDCC | TADDCCTV | TSUBCC | TSUBCCTV =>
if notag = 1 then illegal_inst := '1'; end if;
when UMAC | SMAC =>
if not false then illegal_inst := '1'; end if;
when UMUL | SMUL | UMULCC | SMULCC =>
if not true then illegal_inst := '1'; end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if not true then illegal_inst := '1'; end if;
when RETT => illegal_inst := r.a.et; privileged_inst := not r.a.su;
when RDPSR | RDTBR | RDWIM => privileged_inst := not r.a.su;
when WRY => null;
when WRPSR =>
privileged_inst := not r.a.su;
when WRWIM | WRTBR => privileged_inst := not r.a.su;
when FPOP1 | FPOP2 =>
if FPEN then fp_disabled := not r.w.s.ef; fpop := '1';
else fp_disabled := '1'; fpop := '0'; end if;
when CPOP1 | CPOP2 =>
if (not false) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when others => illegal_inst := '1';
end case;
when others => -- LDST
case op3 is
when LDD | ISTD => illegal_inst := rd(0); -- trap if odd destination register
when LD | LDUB | LDSTUB | LDUH | LDSB | LDSH | ST | STB | STH | SWAP =>
null;
when LDDA | STDA =>
illegal_inst := inst(13) or rd(0); privileged_inst := not r.a.su;
when LDA | LDUBA| LDSTUBA | LDUHA | LDSBA | LDSHA | STA | STBA | STHA |
SWAPA =>
illegal_inst := inst(13); privileged_inst := not r.a.su;
when LDDF | STDF | LDF | LDFSR | STF | STFSR =>
if FPEN then fp_disabled := not r.w.s.ef;
else fp_disabled := '1'; end if;
when STDFQ =>
privileged_inst := not r.a.su;
if (not FPEN) or (r.w.s.ef = '0') then fp_disabled := '1'; end if;
when STDCQ =>
privileged_inst := not r.a.su;
if (not false) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when LDC | LDCSR | LDDC | STC | STCSR | STDC =>
if (not false) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when others => illegal_inst := '1';
end case;
end case;
wph := wphit(r, wpr, dbgi);
trap := '1';
if r.a.ctrl.trap = '1' then tt := TT_IAEX;
elsif privileged_inst = '1' then tt := TT_PRIV;
elsif illegal_inst = '1' then tt := TT_IINST;
elsif fp_disabled = '1' then tt := TT_FPDIS;
elsif cp_disabled = '1' then tt := TT_CPDIS;
elsif wph = '1' then tt := TT_WATCH;
elsif r.a.wovf= '1' then tt := TT_WINOF;
elsif r.a.wunf= '1' then tt := TT_WINUF;
elsif r.a.ticc= '1' then tt := TT_TICC;
else trap := '0'; tt:= (others => '0'); end if;
end if;
end;
-- instructions that write the condition codes (psr.icc)
procedure wicc_y_gen(inst : word; wicc, wy : out std_ulogic) is
begin
wicc := '0'; wy := '0';
if inst(31 downto 30) = FMT3 then
case inst(24 downto 19) is
when SUBCC | TSUBCC | TSUBCCTV | ADDCC | ANDCC | ORCC | XORCC | ANDNCC |
ORNCC | XNORCC | TADDCC | TADDCCTV | ADDXCC | SUBXCC | WRPSR =>
wicc := '1';
when WRY =>
if r.d.inst(conv_integer(r.d.set))(29 downto 25) = "00000" then wy := '1'; end if;
when MULSCC =>
wicc := '1'; wy := '1';
when UMAC | SMAC =>
if false then wy := '1'; end if;
when UMULCC | SMULCC =>
if true and (((mulo.nready = '1') and (r.d.cnt /= "00")) or (0 /= 0)) then
wicc := '1'; wy := '1';
end if;
when UMUL | SMUL =>
if true and (((mulo.nready = '1') and (r.d.cnt /= "00")) or (0 /= 0)) then
wy := '1';
end if;
when UDIVCC | SDIVCC =>
if true and (divo.nready = '1') and (r.d.cnt /= "00") then
wicc := '1';
end if;
when others =>
end case;
end if;
end;
-- select cwp
procedure cwp_gen(r, v : registers; annul, wcwp : std_ulogic; ncwp : cwptype;
cwp : out cwptype) is
begin
if (r.x.rstate = trap) or (r.x.rstate = dsu2) or (rstn = '0') then cwp := v.w.s.cwp;
elsif (wcwp = '1') and (annul = '0') then cwp := ncwp;
elsif r.m.wcwp = '1' then cwp := r.m.result(3-1 downto 0);
else cwp := r.d.cwp; end if;
end;
-- generate wcwp in ex stage
procedure cwp_ex(r : in registers; wcwp : out std_ulogic) is
begin
if (r.e.ctrl.inst(31 downto 30) = FMT3) and
(r.e.ctrl.inst(24 downto 19) = WRPSR)
then wcwp := not r.e.ctrl.annul; else wcwp := '0'; end if;
end;
-- generate next cwp & window under- and overflow traps
procedure cwp_ctrl(r : in registers; xc_wim : in std_logic_vector(8-1 downto 0);
inst : word; de_cwp : out cwptype; wovf_exc, wunf_exc, wcwp : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable wim : word;
variable ncwp : cwptype;
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
wovf_exc := '0'; wunf_exc := '0'; wim := (others => '0');
wim(8-1 downto 0) := xc_wim; ncwp := r.d.cwp; wcwp := '0';
if (op = FMT3) and ((op3 = RETT) or (op3 = RESTORE) or (op3 = SAVE)) then
wcwp := '1';
if (op3 = SAVE) then
if (not true) and (r.d.cwp = "000") then ncwp := "111";
else ncwp := r.d.cwp - 1 ; end if;
else
if (not true) and (r.d.cwp = "111") then ncwp := "000";
else ncwp := r.d.cwp + 1; end if;
end if;
if wim(conv_integer(ncwp)) = '1' then
if op3 = SAVE then wovf_exc := '1'; else wunf_exc := '1'; end if;
end if;
end if;
de_cwp := ncwp;
end;
-- generate register read address 1
procedure rs1_gen(r : registers; inst : word; rs1 : out std_logic_vector(4 downto 0);
rs1mod : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
rs1 := inst(18 downto 14); rs1mod := '0';
if (op = LDST) then
if ((r.d.cnt = "01") and ((op3(2) and not op3(3)) = '1')) or
(r.d.cnt = "10")
then rs1mod := '1'; rs1 := inst(29 downto 25); end if;
if ((r.d.cnt = "10") and (op3(3 downto 0) = "0111")) then
rs1(0) := '1';
end if;
end if;
end;
-- load/icc interlock detection
procedure lock_gen(r : registers; rs2, rd : std_logic_vector(4 downto 0);
rfa1, rfa2, rfrd : rfatype; inst : word; fpc_lock, mulinsn, divinsn : std_ulogic;
lldcheck1, lldcheck2, lldlock, lldchkra, lldchkex : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable cond : std_logic_vector(3 downto 0);
variable rs1 : std_logic_vector(4 downto 0);
variable i, ldcheck1, ldcheck2, ldchkra, ldchkex, ldcheck3 : std_ulogic;
variable ldlock, icc_check, bicc_hold, chkmul, y_check : std_ulogic;
variable lddlock : boolean;
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
op2 := inst(24 downto 22); cond := inst(28 downto 25);
rs1 := inst(18 downto 14); lddlock := false; i := inst(13);
ldcheck1 := '0'; ldcheck2 := '0'; ldcheck3 := '0'; ldlock := '0';
ldchkra := '1'; ldchkex := '1'; icc_check := '0'; bicc_hold := '0';
y_check := '0';
if (r.d.annul = '0') then
case op is
when FMT2 =>
if (op2 = BICC) and (cond(2 downto 0) /= "000") then
icc_check := '1';
end if;
when FMT3 =>
ldcheck1 := '1'; ldcheck2 := not i;
case op3 is
when TICC =>
if (cond(2 downto 0) /= "000") then icc_check := '1'; end if;
when RDY =>
ldcheck1 := '0'; ldcheck2 := '0';
if false then y_check := '1'; end if;
when RDWIM | RDTBR =>
ldcheck1 := '0'; ldcheck2 := '0';
when RDPSR =>
ldcheck1 := '0'; ldcheck2 := '0'; icc_check := '1';
if true then icc_check := '1'; end if;
-- when ADDX | ADDXCC | SUBX | SUBXCC =>
-- if true then icc_check := '1'; end if;
when SDIV | SDIVCC | UDIV | UDIVCC =>
if true then y_check := '1'; end if;
when FPOP1 | FPOP2 => ldcheck1:= '0'; ldcheck2 := '0';
when others =>
end case;
when LDST =>
ldcheck1 := '1'; ldchkra := '0';
case r.d.cnt is
when "00" =>
if (lddel = 2) and (op3(2) = '1') then ldcheck3 := '1'; end if;
ldcheck2 := not i; ldchkra := '1';
when "01" => ldcheck2 := not i;
when others => ldchkex := '0';
end case;
if (op3(2 downto 0) = "011") then lddlock := true; end if;
when others => null;
end case;
end if;
if true or true then
chkmul := mulinsn;
bicc_hold := bicc_hold or (icc_check and r.m.ctrl.wicc and (r.m.ctrl.cnt(0) or r.m.mul));
else chkmul := '0'; end if;
if true then
bicc_hold := bicc_hold or (y_check and (r.a.ctrl.wy or r.e.ctrl.wy));
chkmul := chkmul or divinsn;
end if;
bicc_hold := bicc_hold or (icc_check and (r.a.ctrl.wicc or r.e.ctrl.wicc));
if (((r.a.ctrl.ld or chkmul) and r.a.ctrl.wreg and ldchkra) = '1') and
(((ldcheck1 = '1') and (r.a.ctrl.rd = rfa1)) or
((ldcheck2 = '1') and (r.a.ctrl.rd = rfa2)) or
((ldcheck3 = '1') and (r.a.ctrl.rd = rfrd)))
then ldlock := '1'; end if;
if (((r.e.ctrl.ld or r.e.mac) and r.e.ctrl.wreg and ldchkex) = '1') and
((lddel = 2) or (false and (r.e.mac = '1')) or ((0 = 3) and (r.e.mul = '1'))) and
(((ldcheck1 = '1') and (r.e.ctrl.rd = rfa1)) or
((ldcheck2 = '1') and (r.e.ctrl.rd = rfa2)))
then ldlock := '1'; end if;
ldlock := ldlock or bicc_hold or fpc_lock;
lldcheck1 := ldcheck1; lldcheck2:= ldcheck2; lldlock := ldlock;
lldchkra := ldchkra; lldchkex := ldchkex;
end;
procedure fpbranch(inst : in word; fcc : in std_logic_vector(1 downto 0);
branch : out std_ulogic) is
variable cond : std_logic_vector(3 downto 0);
variable fbres : std_ulogic;
begin
cond := inst(28 downto 25);
case cond(2 downto 0) is
when "000" => fbres := '0'; -- fba, fbn
when "001" => fbres := fcc(1) or fcc(0);
when "010" => fbres := fcc(1) xor fcc(0);
when "011" => fbres := fcc(0);
when "100" => fbres := (not fcc(1)) and fcc(0);
when "101" => fbres := fcc(1);
when "110" => fbres := fcc(1) and not fcc(0);
when others => fbres := fcc(1) and fcc(0);
end case;
branch := cond(3) xor fbres;
end;
-- PC generation
procedure ic_ctrl(r : registers; inst : word; annul_all, ldlock, branch_true,
fbranch_true, cbranch_true, fccv, cccv : in std_ulogic;
cnt : out std_logic_vector(1 downto 0);
de_pc : out pctype; de_branch, ctrl_annul, de_annul, jmpl_inst, inull,
de_pv, ctrl_pv, de_hold_pc, ticc_exception, rett_inst, mulstart,
divstart : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable cond : std_logic_vector(3 downto 0);
variable hold_pc, annul_current, annul_next, branch, annul, pv : std_ulogic;
variable de_jmpl : std_ulogic;
begin
branch := '0'; annul_next := '0'; annul_current := '0'; pv := '1';
hold_pc := '0'; ticc_exception := '0'; rett_inst := '0';
op := inst(31 downto 30); op3 := inst(24 downto 19);
op2 := inst(24 downto 22); cond := inst(28 downto 25);
annul := inst(29); de_jmpl := '0'; cnt := "00";
mulstart := '0'; divstart := '0';
if r.d.annul = '0' then
case inst(31 downto 30) is
when CALL =>
branch := '1';
if r.d.inull = '1' then
hold_pc := '1'; annul_current := '1';
end if;
when FMT2 =>
if (op2 = BICC) or (FPEN and (op2 = FBFCC)) or (false and (op2 = CBCCC)) then
if (FPEN and (op2 = FBFCC)) then
branch := fbranch_true;
if fccv /= '1' then hold_pc := '1'; annul_current := '1'; end if;
elsif (false and (op2 = CBCCC)) then
branch := cbranch_true;
if cccv /= '1' then hold_pc := '1'; annul_current := '1'; end if;
else branch := branch_true; end if;
if hold_pc = '0' then
if (branch = '1') then
if (cond = BA) and (annul = '1') then annul_next := '1'; end if;
else annul_next := annul; end if;
if r.d.inull = '1' then -- contention with JMPL
hold_pc := '1'; annul_current := '1'; annul_next := '0';
end if;
end if;
end if;
when FMT3 =>
case op3 is
when UMUL | SMUL | UMULCC | SMULCC =>
if true and (0 /= 0) then mulstart := '1'; end if;
if true and (0 = 0) then
case r.d.cnt is
when "00" =>
cnt := "01"; hold_pc := '1'; pv := '0'; mulstart := '1';
when "01" =>
if mulo.nready = '1' then cnt := "00";
else cnt := "01"; pv := '0'; hold_pc := '1'; end if;
when others => null;
end case;
end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if true then
case r.d.cnt is
when "00" =>
cnt := "01"; hold_pc := '1'; pv := '0';
divstart := '1';
when "01" =>
if divo.nready = '1' then cnt := "00";
else cnt := "01"; pv := '0'; hold_pc := '1'; end if;
when others => null;
end case;
end if;
when TICC =>
if branch_true = '1' then ticc_exception := '1'; end if;
when RETT =>
rett_inst := '1'; --su := sregs.ps;
when JMPL =>
de_jmpl := '1';
when WRY =>
if false then
if inst(29 downto 25) = "10011" then -- %ASR19
case r.d.cnt is
when "00" =>
pv := '0'; cnt := "00"; hold_pc := '1';
if r.x.ipend = '1' then cnt := "01"; end if;
when "01" =>
cnt := "00";
when others =>
end case;
end if;
end if;
when others => null;
end case;
when others => -- LDST
case r.d.cnt is
when "00" =>
if (op3(2) = '1') or (op3(1 downto 0) = "11") then -- ST/LDST/SWAP/LDD
cnt := "01"; hold_pc := '1'; pv := '0';
end if;
when "01" =>
if (op3(2 downto 0) = "111") or (op3(3 downto 0) = "1101") or
((false or FPEN) and ((op3(5) & op3(2 downto 0)) = "1110"))
then -- LDD/STD/LDSTUB/SWAP
cnt := "10"; pv := '0'; hold_pc := '1';
else
cnt := "00";
end if;
when "10" =>
cnt := "00";
when others => null;
end case;
end case;
end if;
if ldlock = '1' then
cnt := r.d.cnt; annul_next := '0'; pv := '1';
end if;
hold_pc := (hold_pc or ldlock) and not annul_all;
if hold_pc = '1' then de_pc := r.d.pc; else de_pc := r.f.pc; end if;
annul_current := (annul_current or ldlock or annul_all);
ctrl_annul := r.d.annul or annul_all or annul_current;
pv := pv and not ((r.d.inull and not hold_pc) or annul_all);
jmpl_inst := de_jmpl and not annul_current;
annul_next := (r.d.inull and not hold_pc) or annul_next or annul_all;
if (annul_next = '1') or (rstn = '0') then
cnt := (others => '0');
end if;
de_hold_pc := hold_pc; de_branch := branch; de_annul := annul_next;
de_pv := pv; ctrl_pv := r.d.pv and
not ((r.d.annul and not r.d.pv) or annul_all or annul_current);
inull := (not rstn) or r.d.inull or hold_pc or annul_all;
end;
-- register write address generation
procedure rd_gen(r : registers; inst : word; wreg, ld : out std_ulogic;
rdo : out std_logic_vector(4 downto 0)) is
variable write_reg : std_ulogic;
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
begin
op := inst(31 downto 30);
op2 := inst(24 downto 22);
op3 := inst(24 downto 19);
write_reg := '0'; rd := inst(29 downto 25); ld := '0';
case op is
when CALL =>
write_reg := '1'; rd := "01111"; -- CALL saves PC in r[15] (%o7)
when FMT2 =>
if (op2 = SETHI) then write_reg := '1'; end if;
when FMT3 =>
case op3 is
when UMUL | SMUL | UMULCC | SMULCC =>
if true then
if (((mulo.nready = '1') and (r.d.cnt /= "00")) or (0 /= 0)) then
write_reg := '1';
end if;
else write_reg := '1'; end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if true then
if (divo.nready = '1') and (r.d.cnt /= "00") then
write_reg := '1';
end if;
else write_reg := '1'; end if;
when RETT | WRPSR | WRY | WRWIM | WRTBR | TICC | FLUSH => null;
when FPOP1 | FPOP2 => null;
when CPOP1 | CPOP2 => null;
when others => write_reg := '1';
end case;
when others => -- LDST
ld := not op3(2);
if (op3(2) = '0') and not ((false or FPEN) and (op3(5) = '1'))
then write_reg := '1'; end if;
case op3 is
when SWAP | SWAPA | LDSTUB | LDSTUBA =>
if r.d.cnt = "00" then write_reg := '1'; ld := '1'; end if;
when others => null;
end case;
if r.d.cnt = "01" then
case op3 is
when LDD | LDDA | LDDC | LDDF => rd(0) := '1';
when others =>
end case;
end if;
end case;
if (rd = "00000") then write_reg := '0'; end if;
wreg := write_reg; rdo := rd;
end;
-- immediate data generation
function imm_data (r : registers; insn : word)
return word is
variable immediate_data, inst : word;
begin
immediate_data := (others => '0'); inst := insn;
case inst(31 downto 30) is
when FMT2 =>
immediate_data := inst(21 downto 0) & "0000000000";
when others => -- LDST
immediate_data(31 downto 13) := (others => inst(12));
immediate_data(12 downto 0) := inst(12 downto 0);
end case;
return(immediate_data);
end;
-- read special registers
function get_spr (r : registers) return word is
variable spr : word;
begin
spr := (others => '0');
case r.e.ctrl.inst(24 downto 19) is
when RDPSR => spr(31 downto 5) := conv_std_logic_vector(15,4) &
conv_std_logic_vector(3,4) & r.m.icc & "000000" & r.w.s.ec & r.w.s.ef &
r.w.s.pil & r.e.su & r.w.s.ps & r.e.et;
spr(3-1 downto 0) := r.e.cwp;
when RDTBR => spr(31 downto 4) := r.w.s.tba & r.w.s.tt;
when RDWIM => spr(8-1 downto 0) := r.w.s.wim;
when others =>
end case;
return(spr);
end;
-- immediate data select
function imm_select(inst : word) return boolean is
variable imm : boolean;
begin
imm := false;
case inst(31 downto 30) is
when FMT2 =>
case inst(24 downto 22) is
when SETHI => imm := true;
when others =>
end case;
when FMT3 =>
case inst(24 downto 19) is
when RDWIM | RDPSR | RDTBR => imm := true;
when others => if (inst(13) = '1') then imm := true; end if;
end case;
when LDST =>
if (inst(13) = '1') then imm := true; end if;
when others =>
end case;
return(imm);
end;
-- EXE operation
procedure alu_op(r : in registers; iop1, iop2 : in word; me_icc : std_logic_vector(3 downto 0);
my, ldbp : std_ulogic; aop1, aop2 : out word; aluop : out std_logic_vector(2 downto 0);
alusel : out std_logic_vector(1 downto 0); aluadd : out std_ulogic;
shcnt : out std_logic_vector(4 downto 0); sari, shleft, ymsb,
mulins, divins, mulstep, macins, ldbp2, invop2 : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable icc : std_logic_vector(3 downto 0);
variable y0 : std_ulogic;
begin
op := r.a.ctrl.inst(31 downto 30);
op2 := r.a.ctrl.inst(24 downto 22);
op3 := r.a.ctrl.inst(24 downto 19);
aop1 := iop1; aop2 := iop2; ldbp2 := ldbp;
aluop := EXE_NOP; alusel := EXE_RES_MISC; aluadd := '1';
shcnt := iop2(4 downto 0); sari := '0'; shleft := '0'; invop2 := '0';
ymsb := iop1(0); mulins := '0'; divins := '0'; mulstep := '0';
macins := '0';
if r.e.ctrl.wy = '1' then y0 := my;
elsif r.m.ctrl.wy = '1' then y0 := r.m.y(0);
elsif r.x.ctrl.wy = '1' then y0 := r.x.y(0);
else y0 := r.w.s.y(0); end if;
if r.e.ctrl.wicc = '1' then icc := me_icc;
elsif r.m.ctrl.wicc = '1' then icc := r.m.icc;
elsif r.x.ctrl.wicc = '1' then icc := r.x.icc;
else icc := r.w.s.icc; end if;
case op is
when CALL =>
aluop := EXE_LINK;
when FMT2 =>
case op2 is
when SETHI => aluop := EXE_PASS2;
when others =>
end case;
when FMT3 =>
case op3 is
when IADD | ADDX | ADDCC | ADDXCC | TADDCC | TADDCCTV | SAVE | RESTORE |
TICC | JMPL | RETT => alusel := EXE_RES_ADD;
when ISUB | SUBX | SUBCC | SUBXCC | TSUBCC | TSUBCCTV =>
alusel := EXE_RES_ADD; aluadd := '0'; aop2 := not iop2; invop2 := '1';
when MULSCC => alusel := EXE_RES_ADD;
aop1 := (icc(3) xor icc(1)) & iop1(31 downto 1);
if y0 = '0' then aop2 := (others => '0'); ldbp2 := '0'; end if;
mulstep := '1';
when UMUL | UMULCC | SMUL | SMULCC =>
if true then mulins := '1'; end if;
when UMAC | SMAC =>
if false then mulins := '1'; macins := '1'; end if;
when UDIV | UDIVCC | SDIV | SDIVCC =>
if true then
aluop := EXE_DIV; alusel := EXE_RES_LOGIC; divins := '1';
end if;
when IAND | ANDCC => aluop := EXE_AND; alusel := EXE_RES_LOGIC;
when ANDN | ANDNCC => aluop := EXE_ANDN; alusel := EXE_RES_LOGIC;
when IOR | ORCC => aluop := EXE_OR; alusel := EXE_RES_LOGIC;
when ORN | ORNCC => aluop := EXE_ORN; alusel := EXE_RES_LOGIC;
when IXNOR | XNORCC => aluop := EXE_XNOR; alusel := EXE_RES_LOGIC;
when XORCC | IXOR | WRPSR | WRWIM | WRTBR | WRY =>
aluop := EXE_XOR; alusel := EXE_RES_LOGIC;
when RDPSR | RDTBR | RDWIM => aluop := EXE_SPR;
when RDY => aluop := EXE_RDY;
when ISLL => aluop := EXE_SLL; alusel := EXE_RES_SHIFT; shleft := '1';
shcnt := not iop2(4 downto 0); invop2 := '1';
when ISRL => aluop := EXE_SRL; alusel := EXE_RES_SHIFT;
when ISRA => aluop := EXE_SRA; alusel := EXE_RES_SHIFT; sari := iop1(31);
when FPOP1 | FPOP2 =>
when others =>
end case;
when others => -- LDST
case r.a.ctrl.cnt is
when "00" =>
alusel := EXE_RES_ADD;
when "01" =>
case op3 is
when LDD | LDDA | LDDC => alusel := EXE_RES_ADD;
when LDDF => alusel := EXE_RES_ADD;
when SWAP | SWAPA | LDSTUB | LDSTUBA => alusel := EXE_RES_ADD;
when STF | STDF =>
when others =>
aluop := EXE_PASS1;
if op3(2) = '1' then
if op3(1 downto 0) = "01" then aluop := EXE_STB;
elsif op3(1 downto 0) = "10" then aluop := EXE_STH; end if;
end if;
end case;
when "10" =>
aluop := EXE_PASS1;
if op3(2) = '1' then -- ST
if (op3(3) and not op3(1))= '1' then aluop := EXE_ONES; end if; -- LDSTUB/A
end if;
when others =>
end case;
end case;
end;
function ra_inull_gen(r, v : registers) return std_ulogic is
variable de_inull : std_ulogic;
begin
de_inull := '0';
if ((v.e.jmpl or v.e.ctrl.rett) and not v.e.ctrl.annul and not (r.e.jmpl and not r.e.ctrl.annul)) = '1' then de_inull := '1'; end if;
if ((v.a.jmpl or v.a.ctrl.rett) and not v.a.ctrl.annul and not (r.a.jmpl and not r.a.ctrl.annul)) = '1' then de_inull := '1'; end if;
return(de_inull);
end;
-- operand generation
procedure op_mux(r : in registers; rfd, ed, md, xd, im : in word;
rsel : in std_logic_vector(2 downto 0);
ldbp : out std_ulogic; d : out word) is
begin
ldbp := '0';
case rsel is
when "000" => d := rfd;
when "001" => d := ed;
when "010" => d := md; if lddel = 1 then ldbp := r.m.ctrl.ld; end if;
when "011" => d := xd;
when "100" => d := im;
when "101" => d := (others => '0');
when "110" => d := r.w.result;
when others => d := (others => '-');
end case;
end;
procedure op_find(r : in registers; ldchkra : std_ulogic; ldchkex : std_ulogic;
rs1 : std_logic_vector(4 downto 0); ra : rfatype; im : boolean; rfe : out std_ulogic;
osel : out std_logic_vector(2 downto 0); ldcheck : std_ulogic) is
begin
rfe := '0';
if im then osel := "100";
elsif rs1 = "00000" then osel := "101"; -- %g0
elsif ((r.a.ctrl.wreg and ldchkra) = '1') and (ra = r.a.ctrl.rd) then osel := "001";
elsif ((r.e.ctrl.wreg and ldchkex) = '1') and (ra = r.e.ctrl.rd) then osel := "010";
elsif r.m.ctrl.wreg = '1' and (ra = r.m.ctrl.rd) then osel := "011";
elsif (irfwt = 0) and r.x.ctrl.wreg = '1' and (ra = r.x.ctrl.rd) then osel := "110";
else osel := "000"; rfe := ldcheck; end if;
end;
-- generate carry-in for alu
procedure cin_gen(r : registers; me_cin : in std_ulogic; cin : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable ncin : std_ulogic;
begin
op := r.a.ctrl.inst(31 downto 30); op3 := r.a.ctrl.inst(24 downto 19);
if r.e.ctrl.wicc = '1' then ncin := me_cin;
else ncin := r.m.icc(0); end if;
cin := '0';
case op is
when FMT3 =>
case op3 is
when ISUB | SUBCC | TSUBCC | TSUBCCTV => cin := '1';
when ADDX | ADDXCC => cin := ncin;
when SUBX | SUBXCC => cin := not ncin;
when others => null;
end case;
when others => null;
end case;
end;
procedure logic_op(r : registers; aluin1, aluin2, mey : word;
ymsb : std_ulogic; logicres, y : out word) is
variable logicout : word;
begin
case r.e.aluop is
when EXE_AND => logicout := aluin1 and aluin2;
when EXE_ANDN => logicout := aluin1 and not aluin2;
when EXE_OR => logicout := aluin1 or aluin2;
when EXE_ORN => logicout := aluin1 or not aluin2;
when EXE_XOR => logicout := aluin1 xor aluin2;
when EXE_XNOR => logicout := aluin1 xor not aluin2;
when EXE_DIV =>
if true then logicout := aluin2;
else logicout := (others => '-'); end if;
when others => logicout := (others => '-');
end case;
if (r.e.ctrl.wy and r.e.mulstep) = '1' then
y := ymsb & r.m.y(31 downto 1);
elsif r.e.ctrl.wy = '1' then y := logicout;
elsif r.m.ctrl.wy = '1' then y := mey;
elsif false and (r.x.mac = '1') then y := mulo.result(63 downto 32);
elsif r.x.ctrl.wy = '1' then y := r.x.y;
else y := r.w.s.y; end if;
logicres := logicout;
end;
procedure misc_op(r : registers; wpr : watchpoint_registers;
aluin1, aluin2, ldata, mey : word;
mout, edata : out word) is
variable miscout, bpdata, stdata : word;
variable wpi : integer;
begin
wpi := 0; miscout := r.e.ctrl.pc(31 downto 2) & "00";
edata := aluin1; bpdata := aluin1;
if ((r.x.ctrl.wreg and r.x.ctrl.ld and not r.x.ctrl.annul) = '1') and
(r.x.ctrl.rd = r.e.ctrl.rd) and (r.e.ctrl.inst(31 downto 30) = LDST) and
(r.e.ctrl.cnt /= "10")
then bpdata := ldata; end if;
case r.e.aluop is
when EXE_STB => miscout := bpdata(7 downto 0) & bpdata(7 downto 0) &
bpdata(7 downto 0) & bpdata(7 downto 0);
edata := miscout;
when EXE_STH => miscout := bpdata(15 downto 0) & bpdata(15 downto 0);
edata := miscout;
when EXE_PASS1 => miscout := bpdata; edata := miscout;
when EXE_PASS2 => miscout := aluin2;
when EXE_ONES => miscout := (others => '1');
edata := miscout;
when EXE_RDY =>
if true and (r.m.ctrl.wy = '1') then miscout := mey;
else miscout := r.m.y; end if;
if (NWP > 0) and (r.e.ctrl.inst(18 downto 17) = "11") then
wpi := conv_integer(r.e.ctrl.inst(16 downto 15));
if r.e.ctrl.inst(14) = '0' then miscout := wpr(wpi).addr & '0' & wpr(wpi).exec;
else miscout := wpr(wpi).mask & wpr(wpi).load & wpr(wpi).store; end if;
end if;
if (r.e.ctrl.inst(18 downto 17) = "10") and (r.e.ctrl.inst(14) = '1') then --%ASR17
miscout := asr17_gen(r);
end if;
if false then
if (r.e.ctrl.inst(18 downto 14) = "10010") then --%ASR18
if ((r.m.mac = '1') and not false) or ((r.x.mac = '1') and false) then
miscout := mulo.result(31 downto 0); -- data forward of asr18
else miscout := r.w.s.asr18; end if;
else
if ((r.m.mac = '1') and not false) or ((r.x.mac = '1') and false) then
miscout := mulo.result(63 downto 32); -- data forward Y
end if;
end if;
end if;
when EXE_SPR =>
miscout := get_spr(r);
when others => null;
end case;
mout := miscout;
end;
procedure alu_select(r : registers; addout : std_logic_vector(32 downto 0);
op1, op2 : word; shiftout, logicout, miscout : word; res : out word;
me_icc : std_logic_vector(3 downto 0);
icco : out std_logic_vector(3 downto 0); divz : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable icc : std_logic_vector(3 downto 0);
variable aluresult : word;
begin
op := r.e.ctrl.inst(31 downto 30); op3 := r.e.ctrl.inst(24 downto 19);
icc := (others => '0');
case r.e.alusel is
when EXE_RES_ADD =>
aluresult := addout(32 downto 1);
if r.e.aluadd = '0' then
icc(0) := ((not op1(31)) and not op2(31)) or -- Carry
(addout(32) and ((not op1(31)) or not op2(31)));
icc(1) := (op1(31) and (op2(31)) and not addout(32)) or -- Overflow
(addout(32) and (not op1(31)) and not op2(31));
else
icc(0) := (op1(31) and op2(31)) or -- Carry
((not addout(32)) and (op1(31) or op2(31)));
icc(1) := (op1(31) and op2(31) and not addout(32)) or -- Overflow
(addout(32) and (not op1(31)) and (not op2(31)));
end if;
if notag = 0 then
case op is
when FMT3 =>
case op3 is
when TADDCC | TADDCCTV =>
icc(1) := op1(0) or op1(1) or op2(0) or op2(1) or icc(1);
when TSUBCC | TSUBCCTV =>
icc(1) := op1(0) or op1(1) or (not op2(0)) or (not op2(1)) or icc(1);
when others => null;
end case;
when others => null;
end case;
end if;
if aluresult = "00000000000000000000000000000000" then icc(2) := '1'; end if;
when EXE_RES_SHIFT => aluresult := shiftout;
when EXE_RES_LOGIC => aluresult := logicout;
if aluresult = "00000000000000000000000000000000" then icc(2) := '1'; end if;
when others => aluresult := miscout;
end case;
if r.e.jmpl = '1' then aluresult := r.e.ctrl.pc(31 downto 2) & "00"; end if;
icc(3) := aluresult(31); divz := icc(2);
if r.e.ctrl.wicc = '1' then
if (op = FMT3) and (op3 = WRPSR) then icco := logicout(23 downto 20);
else icco := icc; end if;
elsif r.m.ctrl.wicc = '1' then icco := me_icc;
elsif r.x.ctrl.wicc = '1' then icco := r.x.icc;
else icco := r.w.s.icc; end if;
res := aluresult;
end;
procedure dcache_gen(r, v : registers; dci : out dc_in_type;
link_pc, jump, force_a2, load : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable su : std_ulogic;
begin
op := r.e.ctrl.inst(31 downto 30); op3 := r.e.ctrl.inst(24 downto 19);
dci.signed := '0'; dci.lock := '0'; dci.dsuen := '0'; dci.size := SZWORD;
if op = LDST then
case op3 is
when LDUB | LDUBA => dci.size := SZBYTE;
when LDSTUB | LDSTUBA => dci.size := SZBYTE; dci.lock := '1';
when LDUH | LDUHA => dci.size := SZHALF;
when LDSB | LDSBA => dci.size := SZBYTE; dci.signed := '1';
when LDSH | LDSHA => dci.size := SZHALF; dci.signed := '1';
when LD | LDA | LDF | LDC => dci.size := SZWORD;
when SWAP | SWAPA => dci.size := SZWORD; dci.lock := '1';
when LDD | LDDA | LDDF | LDDC => dci.size := SZDBL;
when STB | STBA => dci.size := SZBYTE;
when STH | STHA => dci.size := SZHALF;
when ST | STA | STF => dci.size := SZWORD;
when ISTD | STDA => dci.size := SZDBL;
when STDF | STDFQ => if FPEN then dci.size := SZDBL; end if;
when STDC | STDCQ => if false then dci.size := SZDBL; end if;
when others => dci.size := SZWORD; dci.lock := '0'; dci.signed := '0';
end case;
end if;
link_pc := '0'; jump:= '0'; force_a2 := '0'; load := '0';
dci.write := '0'; dci.enaddr := '0'; dci.read := not op3(2);
-- load/store control decoding
if (r.e.ctrl.annul = '0') then
case op is
when CALL => link_pc := '1';
when FMT3 =>
case op3 is
when JMPL => jump := '1'; link_pc := '1';
when RETT => jump := '1';
when others => null;
end case;
when LDST =>
case r.e.ctrl.cnt is
when "00" =>
dci.read := op3(3) or not op3(2); -- LD/LDST/SWAP
load := op3(3) or not op3(2);
dci.enaddr := '1';
when "01" =>
force_a2 := not op3(2); -- LDD
load := not op3(2); dci.enaddr := not op3(2);
if op3(3 downto 2) = "01" then -- ST/STD
dci.write := '1';
end if;
if op3(3 downto 2) = "11" then -- LDST/SWAP
dci.enaddr := '1';
end if;
when "10" => -- STD/LDST/SWAP
dci.write := '1';
when others => null;
end case;
if (r.e.ctrl.trap or (v.x.ctrl.trap and not v.x.ctrl.annul)) = '1' then
dci.enaddr := '0';
end if;
when others => null;
end case;
end if;
if ((r.x.ctrl.rett and not r.x.ctrl.annul) = '1') then su := r.w.s.ps;
else su := r.w.s.s; end if;
if su = '1' then dci.asi := "00001011"; else dci.asi := "00001010"; end if;
if (op3(4) = '1') and ((op3(5) = '0') or not false) then
dci.asi := r.e.ctrl.inst(12 downto 5);
end if;
end;
procedure fpstdata(r : in registers; edata, eres : in word; fpstdata : in std_logic_vector(31 downto 0);
edata2, eres2 : out word) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
begin
edata2 := edata; eres2 := eres;
op := r.e.ctrl.inst(31 downto 30); op3 := r.e.ctrl.inst(24 downto 19);
if FPEN then
if FPEN and (op = LDST) and ((op3(5 downto 4) & op3(2)) = "101") and (r.e.ctrl.cnt /= "00") then
edata2 := fpstdata; eres2 := fpstdata;
end if;
end if;
end;
function ld_align(data : dcdtype; set : std_logic_vector(0 downto 0);
size, laddr : std_logic_vector(1 downto 0); signed : std_ulogic) return word is
variable align_data, rdata : word;
begin
align_data := data(conv_integer(set)); rdata := (others => '0');
case size is
when "00" => -- byte read
case laddr is
when "00" =>
rdata(7 downto 0) := align_data(31 downto 24);
if signed = '1' then rdata(31 downto 8) := (others => align_data(31)); end if;
when "01" =>
rdata(7 downto 0) := align_data(23 downto 16);
if signed = '1' then rdata(31 downto 8) := (others => align_data(23)); end if;
when "10" =>
rdata(7 downto 0) := align_data(15 downto 8);
if signed = '1' then rdata(31 downto 8) := (others => align_data(15)); end if;
when others =>
rdata(7 downto 0) := align_data(7 downto 0);
if signed = '1' then rdata(31 downto 8) := (others => align_data(7)); end if;
end case;
when "01" => -- half-word read
if laddr(1) = '1' then
rdata(15 downto 0) := align_data(15 downto 0);
if signed = '1' then rdata(31 downto 15) := (others => align_data(15)); end if;
else
rdata(15 downto 0) := align_data(31 downto 16);
if signed = '1' then rdata(31 downto 15) := (others => align_data(31)); end if;
end if;
when others => -- single and double word read
rdata := align_data;
end case;
return(rdata);
end;
procedure mem_trap(r : registers; wpr : watchpoint_registers;
annul, holdn : in std_ulogic;
trapout, iflush, nullify, werrout : out std_ulogic;
tt : out std_logic_vector(5 downto 0)) is
variable cwp : std_logic_vector(3-1 downto 0);
variable cwpx : std_logic_vector(5 downto 3);
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable nalign_d : std_ulogic;
variable trap, werr : std_ulogic;
begin
op := r.m.ctrl.inst(31 downto 30); op2 := r.m.ctrl.inst(24 downto 22);
op3 := r.m.ctrl.inst(24 downto 19);
cwpx := r.m.result(5 downto 3); cwpx(5) := '0';
iflush := '0'; trap := r.m.ctrl.trap; nullify := annul;
tt := r.m.ctrl.tt; werr := (dco.werr or r.m.werr) and not r.w.s.dwt;
nalign_d := r.m.nalign or r.m.result(2);
if ((annul or trap) /= '1') and (r.m.ctrl.pv = '1') then
if (werr and holdn) = '1' then
trap := '1'; tt := TT_DSEX; werr := '0';
if op = LDST then nullify := '1'; end if;
end if;
end if;
if ((annul or trap) /= '1') then
case op is
when FMT2 =>
case op2 is
when FBFCC =>
if FPEN and (fpo.exc = '1') then trap := '1'; tt := TT_FPEXC; end if;
when CBCCC =>
if false and (cpo.exc = '1') then trap := '1'; tt := TT_CPEXC; end if;
when others => null;
end case;
when FMT3 =>
case op3 is
when WRPSR =>
if (orv(cwpx) = '1') then trap := '1'; tt := TT_IINST; end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if true then
if r.m.divz = '1' then trap := '1'; tt := TT_DIV; end if;
end if;
when JMPL | RETT =>
if r.m.nalign = '1' then trap := '1'; tt := TT_UNALA; end if;
when TADDCCTV | TSUBCCTV =>
if (notag = 0) and (r.m.icc(1) = '1') then
trap := '1'; tt := TT_TAG;
end if;
when FLUSH => iflush := '1';
when FPOP1 | FPOP2 =>
if FPEN and (fpo.exc = '1') then trap := '1'; tt := TT_FPEXC; end if;
when CPOP1 | CPOP2 =>
if false and (cpo.exc = '1') then trap := '1'; tt := TT_CPEXC; end if;
when others => null;
end case;
when LDST =>
if r.m.ctrl.cnt = "00" then
case op3 is
when LDDF | STDF | STDFQ =>
if FPEN then
if nalign_d = '1' then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif (fpo.exc and r.m.ctrl.pv) = '1'
then trap := '1'; tt := TT_FPEXC; nullify := '1'; end if;
end if;
when LDDC | STDC | STDCQ =>
if false then
if nalign_d = '1' then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif ((cpo.exc and r.m.ctrl.pv) = '1')
then trap := '1'; tt := TT_CPEXC; nullify := '1'; end if;
end if;
when LDD | ISTD | LDDA | STDA =>
if r.m.result(2 downto 0) /= "000" then
trap := '1'; tt := TT_UNALA; nullify := '1';
end if;
when LDF | LDFSR | STFSR | STF =>
if FPEN and (r.m.nalign = '1') then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif FPEN and ((fpo.exc and r.m.ctrl.pv) = '1')
then trap := '1'; tt := TT_FPEXC; nullify := '1'; end if;
when LDC | LDCSR | STCSR | STC =>
if false and (r.m.nalign = '1') then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif false and ((cpo.exc and r.m.ctrl.pv) = '1')
then trap := '1'; tt := TT_CPEXC; nullify := '1'; end if;
when LD | LDA | ST | STA | SWAP | SWAPA =>
if r.m.result(1 downto 0) /= "00" then
trap := '1'; tt := TT_UNALA; nullify := '1';
end if;
when LDUH | LDUHA | LDSH | LDSHA | STH | STHA =>
if r.m.result(0) /= '0' then
trap := '1'; tt := TT_UNALA; nullify := '1';
end if;
when others => null;
end case;
for i in 1 to NWP loop
if ((((wpr(i-1).load and not op3(2)) or (wpr(i-1).store and op3(2))) = '1') and
(((wpr(i-1).addr xor r.m.result(31 downto 2)) and wpr(i-1).mask) = "000000000000000000000000000000"))
then trap := '1'; tt := TT_WATCH; nullify := '1'; end if;
end loop;
end if;
when others => null;
end case;
end if;
if (rstn = '0') or (r.x.rstate = dsu2) then werr := '0'; end if;
trapout := trap; werrout := werr;
end;
procedure irq_trap(r : in registers;
ir : in irestart_register;
irl : in std_logic_vector(3 downto 0);
annul : in std_ulogic;
pv : in std_ulogic;
trap : in std_ulogic;
tt : in std_logic_vector(5 downto 0);
nullify : in std_ulogic;
irqen : out std_ulogic;
irqen2 : out std_ulogic;
nullify2 : out std_ulogic;
trap2, ipend : out std_ulogic;
tt2 : out std_logic_vector(5 downto 0)) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable pend : std_ulogic;
begin
nullify2 := nullify; trap2 := trap; tt2 := tt;
op := r.m.ctrl.inst(31 downto 30); op3 := r.m.ctrl.inst(24 downto 19);
irqen := '1'; irqen2 := r.m.irqen;
if (annul or trap) = '0' then
if ((op = FMT3) and (op3 = WRPSR)) then irqen := '0'; end if;
end if;
if (irl = "1111") or (irl > r.w.s.pil) then
pend := r.m.irqen and r.m.irqen2 and r.w.s.et and not ir.pwd;
else pend := '0'; end if;
ipend := pend;
if ((not annul) and pv and (not trap) and pend) = '1' then
trap2 := '1'; tt2 := "01" & irl;
if op = LDST then nullify2 := '1'; end if;
end if;
end;
procedure irq_intack(r : in registers; holdn : in std_ulogic; intack: out std_ulogic) is
begin
intack := '0';
if r.x.rstate = trap then
if r.w.s.tt(7 downto 4) = "0001" then intack := '1'; end if;
end if;
end;
-- write special registers
procedure sp_write (r : registers; wpr : watchpoint_registers;
s : out special_register_type; vwpr : out watchpoint_registers) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable i : integer range 0 to 3;
begin
op := r.x.ctrl.inst(31 downto 30);
op2 := r.x.ctrl.inst(24 downto 22);
op3 := r.x.ctrl.inst(24 downto 19);
s := r.w.s;
rd := r.x.ctrl.inst(29 downto 25);
vwpr := wpr;
case op is
when FMT3 =>
case op3 is
when WRY =>
if rd = "00000" then
s.y := r.x.result;
elsif false and (rd = "10010") then
s.asr18 := r.x.result;
elsif (rd = "10001") then
s.dwt := r.x.result(14);
if (svt = 1) then s.svt := r.x.result(13); end if;
elsif rd(4 downto 3) = "11" then -- %ASR24 - %ASR31
case rd(2 downto 0) is
when "000" =>
vwpr(0).addr := r.x.result(31 downto 2);
vwpr(0).exec := r.x.result(0);
when "001" =>
vwpr(0).mask := r.x.result(31 downto 2);
vwpr(0).load := r.x.result(1);
vwpr(0).store := r.x.result(0);
when "010" =>
vwpr(1).addr := r.x.result(31 downto 2);
vwpr(1).exec := r.x.result(0);
when "011" =>
vwpr(1).mask := r.x.result(31 downto 2);
vwpr(1).load := r.x.result(1);
vwpr(1).store := r.x.result(0);
when "100" =>
vwpr(2).addr := r.x.result(31 downto 2);
vwpr(2).exec := r.x.result(0);
when "101" =>
vwpr(2).mask := r.x.result(31 downto 2);
vwpr(2).load := r.x.result(1);
vwpr(2).store := r.x.result(0);
when "110" =>
vwpr(3).addr := r.x.result(31 downto 2);
vwpr(3).exec := r.x.result(0);
when others => -- "111"
vwpr(3).mask := r.x.result(31 downto 2);
vwpr(3).load := r.x.result(1);
vwpr(3).store := r.x.result(0);
end case;
end if;
when WRPSR =>
s.cwp := r.x.result(3-1 downto 0);
s.icc := r.x.result(23 downto 20);
s.ec := r.x.result(13);
if FPEN then s.ef := r.x.result(12); end if;
s.pil := r.x.result(11 downto 8);
s.s := r.x.result(7);
s.ps := r.x.result(6);
s.et := r.x.result(5);
when WRWIM =>
s.wim := r.x.result(8-1 downto 0);
when WRTBR =>
s.tba := r.x.result(31 downto 12);
when SAVE =>
if (not true) and (r.w.s.cwp = "000") then s.cwp := "111";
else s.cwp := r.w.s.cwp - 1 ; end if;
when RESTORE =>
if (not true) and (r.w.s.cwp = "111") then s.cwp := "000";
else s.cwp := r.w.s.cwp + 1; end if;
when RETT =>
if (not true) and (r.w.s.cwp = "111") then s.cwp := "000";
else s.cwp := r.w.s.cwp + 1; end if;
s.s := r.w.s.ps;
s.et := '1';
when others => null;
end case;
when others => null;
end case;
if r.x.ctrl.wicc = '1' then s.icc := r.x.icc; end if;
if r.x.ctrl.wy = '1' then s.y := r.x.y; end if;
if false and (r.x.mac = '1') then
s.asr18 := mulo.result(31 downto 0);
s.y := mulo.result(63 downto 32);
end if;
end;
function npc_find (r : registers) return std_logic_vector is
variable npc : std_logic_vector(2 downto 0);
begin
npc := "011";
if r.m.ctrl.pv = '1' then npc := "000";
elsif r.e.ctrl.pv = '1' then npc := "001";
elsif r.a.ctrl.pv = '1' then npc := "010";
elsif r.d.pv = '1' then npc := "011";
elsif 2 /= 0 then npc := "100"; end if;
return(npc);
end;
function npc_gen (r : registers) return word is
variable npc : std_logic_vector(31 downto 0);
begin
npc := r.a.ctrl.pc(31 downto 2) & "00";
case r.x.npc is
when "000" => npc(31 downto 2) := r.x.ctrl.pc(31 downto 2);
when "001" => npc(31 downto 2) := r.m.ctrl.pc(31 downto 2);
when "010" => npc(31 downto 2) := r.e.ctrl.pc(31 downto 2);
when "011" => npc(31 downto 2) := r.a.ctrl.pc(31 downto 2);
when others =>
if 2 /= 0 then npc(31 downto 2) := r.d.pc(31 downto 2); end if;
end case;
return(npc);
end;
procedure mul_res(r : registers; asr18in : word; result, y, asr18 : out word;
icc : out std_logic_vector(3 downto 0)) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
begin
op := r.m.ctrl.inst(31 downto 30); op3 := r.m.ctrl.inst(24 downto 19);
result := r.m.result; y := r.m.y; icc := r.m.icc; asr18 := asr18in;
case op is
when FMT3 =>
case op3 is
when UMUL | SMUL =>
if true then
result := mulo.result(31 downto 0);
y := mulo.result(63 downto 32);
end if;
when UMULCC | SMULCC =>
if true then
result := mulo.result(31 downto 0); icc := mulo.icc;
y := mulo.result(63 downto 32);
end if;
when UMAC | SMAC =>
if false and not false then
result := mulo.result(31 downto 0);
asr18 := mulo.result(31 downto 0);
y := mulo.result(63 downto 32);
end if;
when UDIV | SDIV =>
if true then
result := divo.result(31 downto 0);
end if;
when UDIVCC | SDIVCC =>
if true then
result := divo.result(31 downto 0); icc := divo.icc;
end if;
when others => null;
end case;
when others => null;
end case;
end;
function powerdwn(r : registers; trap : std_ulogic; rp : pwd_register_type) return std_ulogic is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable pd : std_ulogic;
begin
op := r.x.ctrl.inst(31 downto 30);
op3 := r.x.ctrl.inst(24 downto 19);
rd := r.x.ctrl.inst(29 downto 25);
pd := '0';
if (not (r.x.ctrl.annul or trap) and r.x.ctrl.pv) = '1' then
if ((op = FMT3) and (op3 = WRY) and (rd = "10011")) then pd := '1'; end if;
pd := pd or rp.pwd;
end if;
return(pd);
end;
signal dummy : std_ulogic;
signal cpu_index : std_logic_vector(3 downto 0);
signal disasen : std_ulogic;
signal dataToCache : std_logic_vector(31 downto 0);
SIGNAL knockState : std_logic_vector ( 1 downto 0 );
SIGNAL catchAddress : std_logic_vector ( 31 downto 0 );
SIGNAL targetAddress : std_logic_vector ( 31 downto 0 );
SIGNAL knockAddress : std_logic_vector ( 31 downto 0 );
signal addressToCache : std_logic_vector(31 downto 0);
-- Signals used for tracking if a handler fired and which one
signal dfp_trap_vector : std_logic_vector(131 downto 0);
signal or_reduce_1 : std_logic;
signal dfp_delay_start : integer range 0 to 15;
signal dfp_trap_mem : std_logic_vector(dfp_trap_vector'left downto dfp_trap_vector'right);
signal handlerTrap : std_ulogic;
-- Signals that serve as shadow signals for variables used in the pairs
signal EX_EDATA2_shadow : WORD;
signal V_E_SU_shadow : STD_ULOGIC;
signal V_M_RESULT_shadow : WORD;
signal V_A_SU_shadow : STD_ULOGIC;
signal V_M_SU_shadow : STD_ULOGIC;
signal V_A_ET_shadow : STD_ULOGIC;
signal EX_ADD_RES32DOWNTO34DOWNTO3_shadow : STD_LOGIC_VECTOR(4 downto 3);
signal ICNT_shadow : STD_ULOGIC;
signal EX_OP1_shadow : WORD;
signal V_M_CTRL_PC_shadow : PCTYPE;
signal V_E_CTRL_PC3DOWNTO2_shadow : std_logic_vector(3 downto 2);
signal DE_REN1_shadow : STD_ULOGIC;
signal DE_INST_shadow : WORD;
signal V_A_CTRL_CNT_shadow : OP_TYPE;
signal V_F_PC3DOWNTO2_shadow : std_logic_vector(3 downto 2);
signal V_W_S_TT_shadow : STD_LOGIC_VECTOR(7 downto 0);
signal V_X_RESULT6DOWNTO0_shadow : std_logic_vector(6 downto 0);
signal EX_JUMP_ADDRESS3DOWNTO2_shadow : std_logic_vector(3 downto 2);
signal V_E_ALUCIN_shadow : STD_ULOGIC;
signal V_D_PC3DOWNTO2_shadow : std_logic_vector(3 downto 2);
signal V_A_CTRL_PV_shadow : STD_ULOGIC;
signal V_E_CTRL_shadow : PIPELINE_CTRL_TYPE;
signal V_M_CTRL_shadow : PIPELINE_CTRL_TYPE;
signal V_M_RESULT1DOWNTO0_shadow : std_logic_vector(1 downto 0);
signal EX_SHCNT_shadow : ASI_TYPE;
signal V_M_DCI_SIZE_shadow : OP_TYPE;
signal V_X_CTRL_ANNUL_shadow : STD_ULOGIC;
signal V_X_MEXC_shadow : STD_ULOGIC;
signal TBUFCNTX_shadow : STD_LOGIC_VECTOR(6 downto 0);
signal V_A_CTRL_WY_shadow : STD_ULOGIC;
signal NPC_shadow : PCTYPE;
signal V_M_CTRL_TT3DOWNTO0_shadow : std_logic_vector(3 downto 0);
signal V_A_MULSTART_shadow : STD_ULOGIC;
signal XC_VECTT3DOWNTO0_shadow : STD_LOGIC_VECTOR(3 downto 0);
signal V_E_CTRL_TT_shadow : OP3_TYPE;
signal DSIGN_shadow : STD_ULOGIC;
signal V_E_CTRL_ANNUL_shadow : STD_ULOGIC;
signal EX_JUMP_ADDRESS_shadow : PCTYPE;
signal V_A_CTRL_PC31DOWNTO12_shadow : std_logic_vector(31 downto 12);
signal V_A_RFE1_shadow : STD_ULOGIC;
signal V_W_WA_shadow : RFATYPE;
signal V_X_ANNUL_ALL_shadow : STD_ULOGIC;
signal EX_YMSB_shadow : STD_ULOGIC;
signal EX_ADD_RES_shadow : STD_LOGIC_VECTOR(32 downto 0);
signal VIR_ADDR_shadow : PCTYPE;
signal EX_JUMP_ADDRESS31DOWNTO12_shadow : std_logic_vector(31 downto 12);
signal V_W_S_CWP_shadow : CWPTYPE;
signal V_D_INST0_shadow : std_logic_vector(31 downto 0);
signal V_A_CTRL_ANNUL_shadow : STD_ULOGIC;
signal V_X_DATA1_shadow : std_logic_vector(31 downto 0);
signal VP_PWD_shadow : STD_ULOGIC;
signal V_M_CTRL_RD6DOWNTO0_shadow : std_logic_vector(6 downto 0);
signal V_X_DATA00_shadow : STD_LOGIC;
signal V_M_CTRL_RETT_shadow : STD_ULOGIC;
signal V_X_CTRL_RETT_shadow : STD_ULOGIC;
signal V_X_CTRL_PC31DOWNTO12_shadow : std_logic_vector(31 downto 12);
signal V_W_S_PS_shadow : STD_ULOGIC;
signal V_X_CTRL_TT_shadow : OP3_TYPE;
signal V_D_STEP_shadow : STD_ULOGIC;
signal V_X_CTRL_WICC_shadow : STD_ULOGIC;
signal VIR_ADDR31DOWNTO2_shadow : std_logic_vector(31 downto 2);
signal V_M_CTRL_RD7DOWNTO0_shadow : std_logic_vector(7 downto 0);
signal V_X_RESULT_shadow : WORD;
signal V_D_CNT_shadow : OP_TYPE;
signal XC_VECTT_shadow : STD_LOGIC_VECTOR(7 downto 0);
signal EX_ADD_RES32DOWNTO3_shadow : STD_LOGIC_VECTOR(32 downto 3);
signal V_W_S_EF_shadow : STD_ULOGIC;
signal V_A_CTRL_PC31DOWNTO2_shadow : std_logic_vector(31 downto 2);
signal V_X_DATA04DOWNTO0_shadow : std_logic_vector(4 downto 0);
signal V_X_DCI_SIGNED_shadow : STD_ULOGIC;
signal V_M_NALIGN_shadow : STD_ULOGIC;
signal XC_WREG_shadow : STD_ULOGIC;
signal V_A_RFA2_shadow : RFATYPE;
signal V_E_CTRL_PC31DOWNTO12_shadow : std_logic_vector(31 downto 12);
signal EX_ADD_RES32DOWNTO332DOWNTO13_shadow : STD_LOGIC_VECTOR(32 downto 13);
signal EX_OP231_shadow : STD_LOGIC;
signal XC_TRAP_ADDRESS31DOWNTO4_shadow : std_logic_vector(31 downto 4);
signal V_X_ICC_shadow : STD_LOGIC_VECTOR(3 downto 0);
signal V_E_OP2_shadow : WORD;
signal EX_FORCE_A2_shadow : STD_ULOGIC;
signal V_E_CTRL_PC31DOWNTO2_shadow : std_logic_vector(31 downto 2);
signal V_E_CTRL_PC31DOWNTO4_shadow : std_logic_vector(31 downto 4);
signal V_E_OP131_shadow : STD_LOGIC;
signal V_X_DCI_shadow : DC_IN_TYPE;
signal V_E_CTRL_WICC_shadow : STD_ULOGIC;
signal EX_OP13_shadow : STD_LOGIC;
signal V_F_PC31DOWNTO12_shadow : std_logic_vector(31 downto 12);
signal V_E_CTRL_INST_shadow : WORD;
signal V_E_CTRL_LD_shadow : STD_ULOGIC;
signal V_E_SARI_shadow : STD_ULOGIC;
signal V_E_ET_shadow : STD_ULOGIC;
signal V_M_CTRL_PV_shadow : STD_ULOGIC;
signal VDSU_CRDY2_shadow : STD_LOGIC;
signal MUL_OP2_shadow : WORD;
signal XC_EXCEPTION_shadow : STD_ULOGIC;
signal V_E_OP1_shadow : WORD;
signal VP_ERROR_shadow : STD_ULOGIC;
signal V_M_DCI_SIGNED_shadow : STD_ULOGIC;
signal V_D_PC31DOWNTO12_shadow : std_logic_vector(31 downto 12);
signal MUL_OP231_shadow : STD_LOGIC;
signal XC_TRAP_ADDRESS31DOWNTO2_shadow : std_logic_vector(31 downto 2);
signal V_M_CTRL_PC3DOWNTO2_shadow : std_logic_vector(3 downto 2);
signal V_M_DCI_shadow : DC_IN_TYPE;
signal EX_OP23_shadow : STD_LOGIC;
signal V_X_CTRL_RD6DOWNTO0_shadow : std_logic_vector(6 downto 0);
signal V_X_CTRL_TRAP_shadow : STD_ULOGIC;
signal V_A_DIVSTART_shadow : STD_ULOGIC;
signal V_X_RESULT6DOWNTO03DOWNTO0_shadow : std_logic_vector(3 downto 0);
signal VDSU_TT_shadow : STD_LOGIC_VECTOR(7 downto 0);
signal EX_ADD_RES32DOWNTO332DOWNTO5_shadow : STD_LOGIC_VECTOR(32 downto 5);
signal V_X_CTRL_CNT_shadow : OP_TYPE;
signal V_E_YMSB_shadow : STD_ULOGIC;
signal EX_ADD_RES32DOWNTO330DOWNTO11_shadow : STD_LOGIC_VECTOR(30 downto 11);
signal V_A_RFE2_shadow : STD_ULOGIC;
signal V_E_OP13_shadow : STD_LOGIC;
signal V_A_CWP_shadow : CWPTYPE;
signal ME_SIZE_shadow : OP_TYPE;
signal V_X_MAC_shadow : STD_ULOGIC;
signal V_M_CTRL_INST_shadow : WORD;
signal VIR_ADDR31DOWNTO4_shadow : std_logic_vector(31 downto 4);
signal V_A_CTRL_INST20_shadow : STD_LOGIC;
signal DE_REN2_shadow : STD_ULOGIC;
signal V_E_CTRL_PV_shadow : STD_ULOGIC;
signal V_E_MAC_shadow : STD_ULOGIC;
signal V_X_CTRL_TT3DOWNTO0_shadow : std_logic_vector(3 downto 0);
signal EX_ADD_RES3_shadow : STD_LOGIC;
signal V_X_CTRL_INST_shadow : WORD;
signal V_M_CTRL_PC31DOWNTO2_shadow : std_logic_vector(31 downto 2);
signal V_W_S_ET_shadow : STD_ULOGIC;
signal V_M_CTRL_CNT_shadow : OP_TYPE;
signal V_M_CTRL_ANNUL_shadow : STD_ULOGIC;
signal DE_INST19_shadow : STD_LOGIC;
signal XC_HALT_shadow : STD_ULOGIC;
signal V_E_OP231_shadow : STD_LOGIC;
signal V_A_CTRL_PC3DOWNTO2_shadow : std_logic_vector(3 downto 2);
signal VIR_ADDR31DOWNTO12_shadow : std_logic_vector(31 downto 12);
signal V_M_CTRL_WICC_shadow : STD_ULOGIC;
signal V_M_CTRL_WREG_shadow : STD_ULOGIC;
signal V_W_S_S_shadow : STD_ULOGIC;
signal V_F_PC31DOWNTO2_shadow : std_logic_vector(31 downto 2);
signal V_E_CWP_shadow : CWPTYPE;
signal V_A_STEP_shadow : STD_ULOGIC;
signal V_A_CTRL_TT3DOWNTO0_shadow : std_logic_vector(3 downto 0);
signal V_A_CTRL_TRAP_shadow : STD_ULOGIC;
signal NPC31DOWNTO2_shadow : std_logic_vector(31 downto 2);
signal V_M_CTRL_TRAP_shadow : STD_ULOGIC;
signal V_D_PC31DOWNTO4_shadow : std_logic_vector(31 downto 4);
signal V_X_INTACK_shadow : STD_ULOGIC;
signal SIDLE_shadow : STD_ULOGIC;
signal V_A_CTRL_RETT_shadow : STD_ULOGIC;
signal V_X_DATA03_shadow : STD_LOGIC;
signal V_A_CTRL_INST19_shadow : STD_LOGIC;
signal V_W_S_SVT_shadow : STD_ULOGIC;
signal V_A_CTRL_PC31DOWNTO4_shadow : std_logic_vector(31 downto 4);
signal V_X_LADDR_shadow : OP_TYPE;
signal V_W_S_DWT_shadow : STD_ULOGIC;
signal EX_JUMP_ADDRESS31DOWNTO2_shadow : std_logic_vector(31 downto 2);
signal V_W_S_TBA_shadow : STD_LOGIC_VECTOR(19 downto 0);
signal XC_WADDR6DOWNTO0_shadow : STD_LOGIC_VECTOR(6 downto 0);
signal V_M_MUL_shadow : STD_ULOGIC;
signal V_M_Y31_shadow : STD_LOGIC;
signal V_E_OP23_shadow : STD_LOGIC;
signal V_M_CTRL_PC31DOWNTO4_shadow : std_logic_vector(31 downto 4);
signal DE_RADDR17DOWNTO0_shadow : STD_LOGIC_VECTOR(7 downto 0);
signal V_X_CTRL_PC31DOWNTO2_shadow : std_logic_vector(31 downto 2);
signal V_E_CTRL_TRAP_shadow : STD_ULOGIC;
signal V_X_DEBUG_shadow : STD_ULOGIC;
signal V_M_DCI_LOCK_shadow : STD_ULOGIC;
signal V_X_CTRL_PC3DOWNTO2_shadow : std_logic_vector(3 downto 2);
signal V_X_CTRL_WREG_shadow : STD_ULOGIC;
signal V_E_CTRL_INST24_shadow : STD_LOGIC;
signal V_D_MEXC_shadow : STD_ULOGIC;
signal V_W_RESULT_shadow : WORD;
signal VFPI_DBG_ENABLE_shadow : STD_ULOGIC;
signal EX_OP131_shadow : STD_LOGIC;
signal V_D_INST1_shadow : std_logic_vector(31 downto 0);
signal V_W_EXCEPT_shadow : STD_ULOGIC;
signal V_E_CTRL_TT3DOWNTO0_shadow : std_logic_vector(3 downto 0);
signal ME_LADDR_shadow : OP_TYPE;
signal V_X_CTRL_PC31DOWNTO4_shadow : std_logic_vector(31 downto 4);
signal V_E_CTRL_RETT_shadow : STD_ULOGIC;
signal XC_WADDR7DOWNTO0_shadow : STD_LOGIC_VECTOR(7 downto 0);
signal V_X_CTRL_PV_shadow : STD_ULOGIC;
signal V_E_CTRL_RD6DOWNTO0_shadow : std_logic_vector(6 downto 0);
signal V_M_MAC_shadow : STD_ULOGIC;
signal V_D_SET_shadow : STD_LOGIC_VECTOR(0 downto 0);
signal VIR_ADDR3DOWNTO2_shadow : std_logic_vector(3 downto 2);
signal V_D_CWP_shadow : CWPTYPE;
signal DE_INST20_shadow : STD_LOGIC;
signal V_D_ANNUL_shadow : STD_ULOGIC;
signal EX_OP2_shadow : WORD;
signal EX_SARI_shadow : STD_ULOGIC;
signal V_D_PC31DOWNTO2_shadow : std_logic_vector(31 downto 2);
signal V_X_DCI_SIZE_shadow : OP_TYPE;
signal V_M_Y_shadow : WORD;
signal V_X_CTRL_PC_shadow : PCTYPE;
signal V_X_SET_shadow : STD_LOGIC_VECTOR(0 downto 0);
signal V_A_CTRL_PC_shadow : PCTYPE;
signal V_A_JMPL_shadow : STD_ULOGIC;
signal V_E_CTRL_PC_shadow : PCTYPE;
signal V_E_CTRL_INST20_shadow : STD_LOGIC;
signal V_E_CTRL_WREG_shadow : STD_ULOGIC;
signal V_A_CTRL_WREG_shadow : STD_ULOGIC;
signal V_A_CTRL_shadow : PIPELINE_CTRL_TYPE;
signal V_A_CTRL_RD6DOWNTO0_shadow : std_logic_vector(6 downto 0);
signal V_X_DATA0_shadow : std_logic_vector(31 downto 0);
signal V_E_CTRL_INST19_shadow : STD_LOGIC;
signal ME_SIGNED_shadow : STD_ULOGIC;
signal V_W_WREG_shadow : STD_ULOGIC;
signal V_D_PC_shadow : PCTYPE;
signal VFPI_D_ANNUL_shadow : STD_ULOGIC;
signal DE_RADDR27DOWNTO0_shadow : STD_LOGIC_VECTOR(7 downto 0);
signal V_E_CTRL_CNT_shadow : OP_TYPE;
signal V_F_PC_shadow : PCTYPE;
signal V_X_DATA031_shadow : STD_LOGIC;
signal V_M_CTRL_PC31DOWNTO12_shadow : std_logic_vector(31 downto 12);
signal V_X_CTRL_RD7DOWNTO0_shadow : std_logic_vector(7 downto 0);
signal V_M_CTRL_TT_shadow : OP3_TYPE;
signal V_X_CTRL_shadow : PIPELINE_CTRL_TYPE;
signal V_A_CTRL_INST24_shadow : STD_LOGIC;
signal XC_TRAP_ADDRESS3DOWNTO2_shadow : std_logic_vector(3 downto 2);
signal V_X_NERROR_shadow : STD_ULOGIC;
signal V_F_PC31DOWNTO4_shadow : std_logic_vector(31 downto 4);
signal V_W_S_TT3DOWNTO0_shadow : STD_LOGIC_VECTOR(3 downto 0);
signal EX_JUMP_ADDRESS31DOWNTO4_shadow : std_logic_vector(31 downto 4);
signal EX_ADD_RES32DOWNTO332DOWNTO3_shadow : STD_LOGIC_VECTOR(32 downto 3);
signal V_F_BRANCH_shadow : STD_ULOGIC;
signal V_A_CTRL_WICC_shadow : STD_ULOGIC;
signal V_A_CTRL_LD_shadow : STD_ULOGIC;
signal V_A_CTRL_TT_shadow : OP3_TYPE;
signal V_M_CTRL_LD_shadow : STD_ULOGIC;
signal V_E_SHCNT_shadow : ASI_TYPE;
signal XC_TRAP_ADDRESS31DOWNTO12_shadow : std_logic_vector(31 downto 12);
signal V_A_CTRL_INST_shadow : WORD;
signal V_A_CTRL_RD7DOWNTO0_shadow : std_logic_vector(7 downto 0);
signal VIR_PWD_shadow : STD_ULOGIC;
signal XC_RESULT_shadow : WORD;
signal V_A_RFA1_shadow : RFATYPE;
signal V_E_JMPL_shadow : STD_ULOGIC;
signal V_E_CTRL_RD7DOWNTO0_shadow : std_logic_vector(7 downto 0);
signal ME_ICC_shadow : STD_LOGIC_VECTOR(3 downto 0);
signal DE_INST24_shadow : STD_LOGIC;
signal XC_TRAP_shadow : STD_ULOGIC;
signal VDSU_TBUFCNT_shadow : STD_LOGIC_VECTOR(6 downto 0);
signal XC_TRAP_ADDRESS_shadow : PCTYPE;
-- Intermediate value holding signal declarations
signal R_M_RESULT_intermed_3 : std_logic_vector(31 downto 0);
signal TARGETADDRESS_intermed_1 : STD_LOGIC_VECTOR(31 downto 0);
signal RIN_M_RESULT_intermed_4 : std_logic_vector(31 downto 0);
signal R_M_RESULT_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_M_RESULT_intermed_2 : std_logic_vector(31 downto 0);
signal V_M_RESULT_shadow_intermed_4 : std_logic_vector(31 downto 0);
signal RIN_M_RESULT_intermed_1 : std_logic_vector(31 downto 0);
signal EX_EDATA2_shadow_intermed_1 : std_logic_vector(31 downto 0);
signal V_M_RESULT_shadow_intermed_1 : std_logic_vector(31 downto 0);
signal V_A_SU_shadow_intermed_2 : STD_ULOGIC;
signal V_A_SU_shadow_intermed_1 : STD_ULOGIC;
signal DCI_EDATA_intermed_5 : STD_LOGIC_VECTOR(31 downto 0);
signal DCI_EDATA_intermed_1 : STD_LOGIC_VECTOR(31 downto 0);
signal ADDRESSTOCACHE_intermed_2 : STD_LOGIC_VECTOR(31 downto 0);
signal R_A_SU_intermed_2 : STD_ULOGIC;
signal DCI_EDATA_intermed_2 : STD_LOGIC_VECTOR(31 downto 0);
signal TARGETADDRESS_intermed_2 : STD_LOGIC_VECTOR(31 downto 0);
signal TARGETADDRESS_intermed_3 : STD_LOGIC_VECTOR(31 downto 0);
signal V_E_SU_shadow_intermed_2 : STD_ULOGIC;
signal DATATOCACHE_intermed_2 : STD_LOGIC_VECTOR(31 downto 0);
signal R_E_SU_intermed_1 : STD_ULOGIC;
signal DCI_MADDRESS_intermed_2 : STD_LOGIC_VECTOR(31 downto 0);
signal V_M_RESULT_shadow_intermed_2 : std_logic_vector(31 downto 0);
signal EX_EDATA2_shadow_intermed_3 : std_logic_vector(31 downto 0);
signal V_A_SU_shadow_intermed_3 : STD_ULOGIC;
signal DCI_EDATA_intermed_4 : STD_LOGIC_VECTOR(31 downto 0);
signal EX_EDATA2_shadow_intermed_5 : std_logic_vector(31 downto 0);
signal R_A_SU_intermed_1 : STD_ULOGIC;
signal KNOCKADDRESS_intermed_1 : STD_LOGIC_VECTOR(31 downto 0);
signal EX_EDATA2_shadow_intermed_2 : std_logic_vector(31 downto 0);
signal EX_EDATA2_shadow_intermed_4 : std_logic_vector(31 downto 0);
signal DCI_MADDRESS_intermed_3 : STD_LOGIC_VECTOR(31 downto 0);
signal DATATOCACHE_intermed_1 : STD_LOGIC_VECTOR(31 downto 0);
signal RIN_A_SU_intermed_1 : STD_ULOGIC;
signal RIN_E_SU_intermed_2 : STD_ULOGIC;
signal RIN_E_SU_intermed_1 : STD_ULOGIC;
signal RIN_M_RESULT_intermed_3 : std_logic_vector(31 downto 0);
signal RIN_A_SU_intermed_2 : STD_ULOGIC;
signal DATATOCACHE_intermed_3 : STD_LOGIC_VECTOR(31 downto 0);
signal DCI_EDATA_intermed_3 : STD_LOGIC_VECTOR(31 downto 0);
signal RIN_A_SU_intermed_3 : STD_ULOGIC;
signal ADDRESSTOCACHE_intermed_1 : STD_LOGIC_VECTOR(31 downto 0);
signal V_M_RESULT_shadow_intermed_3 : std_logic_vector(31 downto 0);
signal R_M_RESULT_intermed_2 : std_logic_vector(31 downto 0);
signal RIN_M_SU_intermed_1 : STD_ULOGIC;
signal DCI_MADDRESS_intermed_1 : STD_LOGIC_VECTOR(31 downto 0);
signal V_E_SU_shadow_intermed_1 : STD_ULOGIC;
signal V_M_SU_shadow_intermed_1 : STD_ULOGIC;
signal DATATOCACHE_intermed_4 : STD_LOGIC_VECTOR(31 downto 0);
signal V_E_CTRL_WREG_shadow_intermed_2 : STD_ULOGIC;
signal V_M_CTRL_PC_shadow_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_E_CTRL_TT3DOWNTO0_intermed_1 : std_logic_vector(3 downto 0);
signal V_D_PC3DOWNTO2_shadow_intermed_6 : std_logic_vector(3 downto 2);
signal RIN_M_CTRL_PC31DOWNTO12_intermed_5 : std_logic_vector(31 downto 12);
signal RIN_A_RFA1_intermed_1 : std_logic_vector(7 downto 0);
signal RIN_A_CTRL_PC31DOWNTO2_intermed_4 : std_logic_vector(31 downto 2);
signal R_E_CTRL_TT_intermed_1 : std_logic_vector(5 downto 0);
signal V_D_PC3DOWNTO2_shadow_intermed_2 : std_logic_vector(3 downto 2);
signal ICO_MEXC_intermed_4 : STD_ULOGIC;
signal V_F_PC31DOWNTO2_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_X_DATA00_intermed_2 : STD_LOGIC;
signal R_A_CTRL_RD6DOWNTO0_intermed_1 : std_logic_vector(6 downto 0);
signal R_A_CTRL_INST24_intermed_1 : STD_LOGIC;
signal RIN_E_CTRL_INST19_intermed_1 : STD_LOGIC;
signal V_X_DATA00_shadow_intermed_3 : STD_LOGIC;
signal RIN_A_CTRL_INST19_intermed_2 : STD_LOGIC;
signal IRIN_ADDR31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2);
signal V_E_CTRL_WREG_shadow_intermed_1 : STD_ULOGIC;
signal V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 : std_logic_vector(31 downto 2);
signal V_M_CTRL_PC_shadow_intermed_3 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_WICC_intermed_3 : STD_ULOGIC;
signal V_A_CTRL_RETT_shadow_intermed_3 : STD_ULOGIC;
signal RPIN_PWD_intermed_1 : STD_ULOGIC;
signal RIN_A_CTRL_PC31DOWNTO12_intermed_7 : std_logic_vector(31 downto 12);
signal V_E_CTRL_TT_shadow_intermed_3 : std_logic_vector(5 downto 0);
signal DE_INST_shadow_intermed_2 : std_logic_vector(31 downto 0);
signal R_M_CTRL_PC31DOWNTO2_intermed_3 : std_logic_vector(31 downto 2);
signal DBGI_DADDR9DOWNTO2_intermed_1 : STD_LOGIC_VECTOR(9 downto 2);
signal R_D_PC31DOWNTO2_intermed_6 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_TT3DOWNTO0_intermed_5 : std_logic_vector(3 downto 0);
signal RIN_A_CTRL_TRAP_intermed_3 : STD_ULOGIC;
signal V_E_CTRL_CNT_shadow_intermed_2 : std_logic_vector(1 downto 0);
signal V_E_CTRL_PC31DOWNTO4_shadow_intermed_4 : std_logic_vector(31 downto 4);
signal RIN_D_STEP_intermed_1 : STD_ULOGIC;
signal V_M_CTRL_TT3DOWNTO0_shadow_intermed_4 : std_logic_vector(3 downto 0);
signal V_A_CTRL_PC_shadow_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_D_PC31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2);
signal V_E_CTRL_PC31DOWNTO4_shadow_intermed_5 : std_logic_vector(31 downto 4);
signal RIN_E_CTRL_INST20_intermed_1 : STD_LOGIC;
signal V_D_PC3DOWNTO2_shadow_intermed_7 : std_logic_vector(3 downto 2);
signal V_M_CTRL_PC31DOWNTO4_shadow_intermed_4 : std_logic_vector(31 downto 4);
signal V_M_CTRL_RD6DOWNTO0_shadow_intermed_2 : std_logic_vector(6 downto 0);
signal RIN_E_CTRL_PC3DOWNTO2_intermed_3 : std_logic_vector(3 downto 2);
signal RIN_M_Y31_intermed_1 : STD_LOGIC;
signal V_D_INST0_shadow_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_E_YMSB_intermed_1 : STD_ULOGIC;
signal R_X_DATA031_intermed_2 : STD_LOGIC;
signal RIN_M_CTRL_WREG_intermed_2 : STD_ULOGIC;
signal V_X_CTRL_TT_shadow_intermed_1 : std_logic_vector(5 downto 0);
signal RIN_E_CTRL_PC_intermed_4 : std_logic_vector(31 downto 2);
signal V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 : std_logic_vector(3 downto 0);
signal RIN_E_CTRL_PC31DOWNTO12_intermed_4 : std_logic_vector(31 downto 12);
signal V_A_CTRL_PC3DOWNTO2_shadow_intermed_3 : std_logic_vector(3 downto 2);
signal RIN_E_CTRL_PC31DOWNTO2_intermed_4 : std_logic_vector(31 downto 2);
signal R_A_CTRL_TT_intermed_1 : std_logic_vector(5 downto 0);
signal RIN_A_CTRL_WICC_intermed_2 : STD_ULOGIC;
signal V_E_CTRL_PC31DOWNTO2_shadow_intermed_6 : std_logic_vector(31 downto 2);
signal RIN_F_PC3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2);
signal V_A_CTRL_PC31DOWNTO12_shadow_intermed_4 : std_logic_vector(31 downto 12);
signal EX_ADD_RES32DOWNTO332DOWNTO5_shadow_intermed_1 : STD_LOGIC_VECTOR(32 downto 5);
signal V_X_DATA04DOWNTO0_shadow_intermed_1 : std_logic_vector(4 downto 0);
signal R_A_CTRL_INST20_intermed_2 : STD_LOGIC;
signal V_A_CTRL_PC31DOWNTO12_shadow_intermed_6 : std_logic_vector(31 downto 12);
signal R_A_CTRL_RETT_intermed_2 : STD_ULOGIC;
signal RIN_M_DCI_LOCK_intermed_1 : STD_ULOGIC;
signal RIN_D_PC31DOWNTO12_intermed_6 : std_logic_vector(31 downto 12);
signal RIN_E_CTRL_TT_intermed_3 : std_logic_vector(5 downto 0);
signal R_E_CTRL_RD7DOWNTO0_intermed_2 : std_logic_vector(7 downto 0);
signal RIN_A_ET_intermed_1 : STD_ULOGIC;
signal RIN_X_CTRL_RD6DOWNTO0_intermed_1 : std_logic_vector(6 downto 0);
signal RIN_M_CTRL_PC31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12);
signal DBGI_STEP_intermed_1 : STD_ULOGIC;
signal V_A_CTRL_RETT_shadow_intermed_2 : STD_ULOGIC;
signal R_X_CTRL_PC3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2);
signal R_A_CTRL_PC31DOWNTO4_intermed_4 : std_logic_vector(31 downto 4);
signal V_M_CTRL_PV_shadow_intermed_1 : STD_ULOGIC;
signal RIN_M_CTRL_PC31DOWNTO2_intermed_5 : std_logic_vector(31 downto 2);
signal V_M_CTRL_PC31DOWNTO12_shadow_intermed_5 : std_logic_vector(31 downto 12);
signal V_X_LADDR_shadow_intermed_1 : std_logic_vector(1 downto 0);
signal V_D_ANNUL_shadow_intermed_2 : STD_ULOGIC;
signal V_A_CTRL_RD6DOWNTO0_shadow_intermed_1 : std_logic_vector(6 downto 0);
signal RIN_W_WA_intermed_1 : std_logic_vector(7 downto 0);
signal V_D_PC_shadow_intermed_4 : std_logic_vector(31 downto 2);
signal V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_X_CTRL_PC31DOWNTO4_intermed_2 : std_logic_vector(31 downto 4);
signal V_E_CTRL_WICC_shadow_intermed_1 : STD_ULOGIC;
signal VDSU_CRDY2_shadow_intermed_2 : STD_LOGIC;
signal V_M_RESULT1DOWNTO0_shadow_intermed_3 : std_logic_vector(1 downto 0);
signal RIN_D_INST0_intermed_1 : std_logic_vector(31 downto 0);
signal V_X_DATA03_shadow_intermed_2 : STD_LOGIC;
signal RIN_X_DCI_intermed_1 : DC_IN_TYPE;
signal DSUIN_TT_intermed_1 : STD_LOGIC_VECTOR(7 downto 0);
signal V_D_CNT_shadow_intermed_4 : std_logic_vector(1 downto 0);
signal RIN_D_CNT_intermed_4 : std_logic_vector(1 downto 0);
signal ICO_MEXC_intermed_1 : STD_ULOGIC;
signal R_X_ANNUL_ALL_intermed_2 : STD_ULOGIC;
signal R_X_CTRL_TT3DOWNTO0_intermed_2 : std_logic_vector(3 downto 0);
signal R_D_PC3DOWNTO2_intermed_3 : std_logic_vector(3 downto 2);
signal RIN_D_CNT_intermed_2 : std_logic_vector(1 downto 0);
signal V_M_DCI_SIZE_shadow_intermed_2 : std_logic_vector(1 downto 0);
signal R_A_CTRL_ANNUL_intermed_2 : STD_ULOGIC;
signal V_W_S_S_shadow_intermed_1 : STD_ULOGIC;
signal RIN_M_CTRL_TT_intermed_2 : std_logic_vector(5 downto 0);
signal EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_1 : STD_LOGIC_VECTOR(30 downto 11);
signal V_A_CTRL_RETT_shadow_intermed_1 : STD_ULOGIC;
signal R_X_DATA04DOWNTO0_intermed_1 : std_logic_vector(4 downto 0);
signal V_E_CTRL_TT3DOWNTO0_shadow_intermed_1 : std_logic_vector(3 downto 0);
signal V_D_PC31DOWNTO4_shadow_intermed_6 : std_logic_vector(31 downto 4);
signal V_X_CTRL_RD6DOWNTO0_shadow_intermed_1 : std_logic_vector(6 downto 0);
signal RIN_W_S_ET_intermed_1 : STD_ULOGIC;
signal R_E_CTRL_TRAP_intermed_1 : STD_ULOGIC;
signal V_A_CTRL_PC_shadow_intermed_3 : std_logic_vector(31 downto 2);
signal R_M_CTRL_PC31DOWNTO4_intermed_2 : std_logic_vector(31 downto 4);
signal VIR_ADDR31DOWNTO4_shadow_intermed_2 : std_logic_vector(31 downto 4);
signal V_E_CTRL_RD6DOWNTO0_shadow_intermed_3 : std_logic_vector(6 downto 0);
signal R_D_CWP_intermed_1 : std_logic_vector(2 downto 0);
signal RIN_A_CTRL_TT3DOWNTO0_intermed_2 : std_logic_vector(3 downto 0);
signal RIN_X_CTRL_PC3DOWNTO2_intermed_3 : std_logic_vector(3 downto 2);
signal RIN_D_PC31DOWNTO2_intermed_8 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_ANNUL_intermed_1 : STD_ULOGIC;
signal V_X_CTRL_PC3DOWNTO2_shadow_intermed_1 : std_logic_vector(3 downto 2);
signal RIN_M_CTRL_PC31DOWNTO12_intermed_3 : std_logic_vector(31 downto 12);
signal R_M_DCI_SIGNED_intermed_1 : STD_ULOGIC;
signal RIN_X_DCI_SIGNED_intermed_1 : STD_ULOGIC;
signal V_D_PC31DOWNTO2_shadow_intermed_4 : std_logic_vector(31 downto 2);
signal V_M_CTRL_RD7DOWNTO0_shadow_intermed_2 : std_logic_vector(7 downto 0);
signal R_A_CTRL_INST20_intermed_1 : STD_LOGIC;
signal R_D_PC31DOWNTO12_intermed_7 : std_logic_vector(31 downto 12);
signal XC_TRAP_ADDRESS_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_X_CTRL_PC31DOWNTO2_intermed_3 : std_logic_vector(31 downto 2);
signal R_E_CTRL_RETT_intermed_1 : STD_ULOGIC;
signal V_X_DCI_SIZE_shadow_intermed_1 : std_logic_vector(1 downto 0);
signal RIN_D_CNT_intermed_3 : std_logic_vector(1 downto 0);
signal RIN_A_CTRL_ANNUL_intermed_4 : STD_ULOGIC;
signal R_E_CTRL_TT3DOWNTO0_intermed_1 : std_logic_vector(3 downto 0);
signal R_D_PC3DOWNTO2_intermed_2 : std_logic_vector(3 downto 2);
signal V_X_CTRL_TT3DOWNTO0_shadow_intermed_3 : std_logic_vector(3 downto 0);
signal V_A_CTRL_RD6DOWNTO0_shadow_intermed_3 : std_logic_vector(6 downto 0);
signal R_M_CTRL_PC31DOWNTO2_intermed_4 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_PC31DOWNTO12_intermed_3 : std_logic_vector(31 downto 12);
signal R_A_CTRL_PC31DOWNTO12_intermed_5 : std_logic_vector(31 downto 12);
signal R_A_CTRL_PC_intermed_2 : std_logic_vector(31 downto 2);
signal V_X_MEXC_shadow_intermed_1 : STD_ULOGIC;
signal V_M_CTRL_RD7DOWNTO0_shadow_intermed_1 : std_logic_vector(7 downto 0);
signal IR_ADDR31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4);
signal V_A_CTRL_PC_shadow_intermed_4 : std_logic_vector(31 downto 2);
signal VIR_ADDR31DOWNTO4_shadow_intermed_1 : std_logic_vector(31 downto 4);
signal RIN_M_CTRL_PC3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2);
signal RIN_E_CTRL_WREG_intermed_1 : STD_ULOGIC;
signal RIN_D_PC31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12);
signal V_E_CTRL_TT3DOWNTO0_shadow_intermed_2 : std_logic_vector(3 downto 0);
signal RIN_D_INST1_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_D_PC31DOWNTO12_intermed_3 : std_logic_vector(31 downto 12);
signal V_A_CTRL_TT_shadow_intermed_3 : std_logic_vector(5 downto 0);
signal RIN_A_CTRL_INST24_intermed_2 : STD_LOGIC;
signal V_X_DATA1_shadow_intermed_2 : std_logic_vector(31 downto 0);
signal ICO_MEXC_intermed_3 : STD_ULOGIC;
signal R_D_PC3DOWNTO2_intermed_4 : std_logic_vector(3 downto 2);
signal R_M_CTRL_INST_intermed_1 : std_logic_vector(31 downto 0);
signal V_A_CWP_shadow_intermed_1 : std_logic_vector(2 downto 0);
signal V_A_CTRL_WICC_shadow_intermed_3 : STD_ULOGIC;
signal V_D_PC_shadow_intermed_6 : std_logic_vector(31 downto 2);
signal RIN_X_ANNUL_ALL_intermed_5 : STD_ULOGIC;
signal RIN_E_CTRL_INST20_intermed_2 : STD_LOGIC;
signal R_X_DATA0_intermed_2 : std_logic_vector(31 downto 0);
signal RIN_D_PC_intermed_4 : std_logic_vector(31 downto 2);
signal R_E_CTRL_PV_intermed_1 : STD_ULOGIC;
signal R_E_CTRL_TT3DOWNTO0_intermed_2 : std_logic_vector(3 downto 0);
signal R_D_PC_intermed_1 : std_logic_vector(31 downto 2);
signal R_A_CTRL_PC_intermed_3 : std_logic_vector(31 downto 2);
signal EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_1 : std_logic_vector(31 downto 12);
signal R_X_CTRL_TT3DOWNTO0_intermed_1 : std_logic_vector(3 downto 0);
signal V_M_DCI_SIGNED_shadow_intermed_1 : STD_ULOGIC;
signal RIN_X_CTRL_TT3DOWNTO0_intermed_1 : std_logic_vector(3 downto 0);
signal V_X_ANNUL_ALL_shadow_intermed_2 : STD_ULOGIC;
signal V_D_PC31DOWNTO4_shadow_intermed_7 : std_logic_vector(31 downto 4);
signal RIN_E_OP13_intermed_1 : STD_LOGIC;
signal RIN_A_CWP_intermed_1 : std_logic_vector(2 downto 0);
signal RIN_E_CTRL_WICC_intermed_1 : STD_ULOGIC;
signal VP_ERROR_shadow_intermed_2 : STD_ULOGIC;
signal RIN_E_OP2_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_A_CTRL_TT3DOWNTO0_intermed_4 : std_logic_vector(3 downto 0);
signal RIN_A_CTRL_RD7DOWNTO0_intermed_2 : std_logic_vector(7 downto 0);
signal RIN_E_CTRL_intermed_2 : PIPELINE_CTRL_TYPE;
signal R_M_CTRL_PC_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_E_CTRL_PC31DOWNTO2_intermed_5 : std_logic_vector(31 downto 2);
signal R_M_Y31_intermed_2 : STD_LOGIC;
signal V_M_CTRL_PC3DOWNTO2_shadow_intermed_4 : std_logic_vector(3 downto 2);
signal V_M_CTRL_RETT_shadow_intermed_1 : STD_ULOGIC;
signal V_X_CTRL_PC31DOWNTO4_shadow_intermed_3 : std_logic_vector(31 downto 4);
signal XC_VECTT3DOWNTO0_shadow_intermed_2 : STD_LOGIC_VECTOR(3 downto 0);
signal RIN_M_CTRL_PC31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12);
signal RIN_M_RESULT1DOWNTO0_intermed_2 : std_logic_vector(1 downto 0);
signal V_X_ANNUL_ALL_shadow_intermed_4 : STD_ULOGIC;
signal RIN_W_S_TBA_intermed_1 : STD_LOGIC_VECTOR(19 downto 0);
signal V_D_INST1_shadow_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_X_DATA031_intermed_1 : STD_LOGIC;
signal XC_TRAP_ADDRESS31DOWNTO12_shadow_intermed_1 : std_logic_vector(31 downto 12);
signal RIN_D_PC3DOWNTO2_intermed_4 : std_logic_vector(3 downto 2);
signal RIN_X_CTRL_PC31DOWNTO4_intermed_3 : std_logic_vector(31 downto 4);
signal V_E_CTRL_PC31DOWNTO4_shadow_intermed_2 : std_logic_vector(31 downto 4);
signal V_M_CTRL_PC3DOWNTO2_shadow_intermed_3 : std_logic_vector(3 downto 2);
signal V_M_CTRL_PC31DOWNTO12_shadow_intermed_2 : std_logic_vector(31 downto 12);
signal RIN_E_CTRL_PV_intermed_1 : STD_ULOGIC;
signal EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_1 : STD_LOGIC_VECTOR(32 downto 13);
signal R_E_CTRL_WREG_intermed_2 : STD_ULOGIC;
signal R_X_DATA031_intermed_1 : STD_LOGIC;
signal R_D_INST0_intermed_2 : std_logic_vector(31 downto 0);
signal RIN_E_SARI_intermed_1 : STD_ULOGIC;
signal R_M_Y31_intermed_1 : STD_LOGIC;
signal IR_ADDR3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2);
signal DE_INST24_shadow_intermed_2 : STD_LOGIC;
signal V_W_S_S_shadow_intermed_2 : STD_ULOGIC;
signal DE_INST20_shadow_intermed_3 : STD_LOGIC;
signal R_E_CTRL_TT3DOWNTO0_intermed_4 : std_logic_vector(3 downto 0);
signal RIN_A_CTRL_TT_intermed_2 : std_logic_vector(5 downto 0);
signal V_A_CTRL_PV_shadow_intermed_2 : STD_ULOGIC;
signal V_E_CTRL_TT_shadow_intermed_1 : std_logic_vector(5 downto 0);
signal V_D_PC31DOWNTO2_shadow_intermed_5 : std_logic_vector(31 downto 2);
signal V_X_DATA04DOWNTO0_shadow_intermed_2 : std_logic_vector(4 downto 0);
signal R_X_CTRL_PC31DOWNTO4_intermed_2 : std_logic_vector(31 downto 4);
signal RIN_M_CTRL_INST_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_A_CTRL_RD6DOWNTO0_intermed_2 : std_logic_vector(6 downto 0);
signal DCO_DATA04DOWNTO0_intermed_2 : std_logic_vector(4 downto 0);
signal EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_2 : std_logic_vector(31 downto 12);
signal V_X_DATA0_shadow_intermed_2 : std_logic_vector(31 downto 0);
signal R_A_CTRL_WREG_intermed_3 : STD_ULOGIC;
signal RIN_X_CTRL_PC31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12);
signal R_D_CNT_intermed_3 : std_logic_vector(1 downto 0);
signal V_E_OP131_shadow_intermed_1 : STD_LOGIC;
signal R_D_PC31DOWNTO12_intermed_6 : std_logic_vector(31 downto 12);
signal RIN_X_CTRL_WICC_intermed_1 : STD_ULOGIC;
signal V_D_PC31DOWNTO12_shadow_intermed_1 : std_logic_vector(31 downto 12);
signal RIN_E_CTRL_TRAP_intermed_3 : STD_ULOGIC;
signal R_X_RESULT6DOWNTO0_intermed_1 : std_logic_vector(6 downto 0);
signal R_E_CTRL_INST19_intermed_2 : STD_LOGIC;
signal RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 : std_logic_vector(3 downto 0);
signal R_M_CTRL_RD7DOWNTO0_intermed_1 : std_logic_vector(7 downto 0);
signal RIN_E_CTRL_PC31DOWNTO12_intermed_6 : std_logic_vector(31 downto 12);
signal RIN_A_CTRL_PC31DOWNTO4_intermed_3 : std_logic_vector(31 downto 4);
signal V_A_CTRL_INST19_shadow_intermed_3 : STD_LOGIC;
signal V_D_PC31DOWNTO12_shadow_intermed_5 : std_logic_vector(31 downto 12);
signal V_A_CTRL_INST19_shadow_intermed_2 : STD_LOGIC;
signal V_X_CTRL_WREG_shadow_intermed_1 : STD_ULOGIC;
signal V_A_CTRL_TRAP_shadow_intermed_2 : STD_ULOGIC;
signal RIN_E_CTRL_PC3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2);
signal RIN_M_CTRL_PC3DOWNTO2_intermed_3 : std_logic_vector(3 downto 2);
signal V_A_RFE2_shadow_intermed_1 : STD_ULOGIC;
signal V_M_Y_shadow_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_A_CTRL_LD_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_PC_shadow_intermed_3 : std_logic_vector(31 downto 2);
signal RIN_D_INST1_intermed_2 : std_logic_vector(31 downto 0);
signal R_E_CTRL_PC31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12);
signal RIN_X_CTRL_PC31DOWNTO12_intermed_3 : std_logic_vector(31 downto 12);
signal R_E_CTRL_TRAP_intermed_2 : STD_ULOGIC;
signal DE_INST24_shadow_intermed_1 : STD_LOGIC;
signal V_E_CTRL_PC_shadow_intermed_2 : std_logic_vector(31 downto 2);
signal V_A_CTRL_TT_shadow_intermed_1 : std_logic_vector(5 downto 0);
signal V_D_MEXC_shadow_intermed_4 : STD_ULOGIC;
signal V_D_PC31DOWNTO12_shadow_intermed_6 : std_logic_vector(31 downto 12);
signal V_A_CTRL_PC31DOWNTO12_shadow_intermed_3 : std_logic_vector(31 downto 12);
signal R_X_CTRL_PC31DOWNTO12_intermed_3 : std_logic_vector(31 downto 12);
signal V_M_CTRL_PV_shadow_intermed_2 : STD_ULOGIC;
signal RIN_A_CTRL_PC31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2);
signal EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_E_CTRL_PC31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4);
signal RIN_E_CTRL_PC31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12);
signal RIN_M_CTRL_TRAP_intermed_1 : STD_ULOGIC;
signal R_E_CTRL_PC31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2);
signal R_E_CTRL_LD_intermed_1 : STD_ULOGIC;
signal R_M_CTRL_PC31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_PC31DOWNTO2_intermed_5 : std_logic_vector(31 downto 2);
signal V_W_S_CWP_shadow_intermed_1 : std_logic_vector(2 downto 0);
signal R_M_CTRL_PC3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2);
signal V_E_CTRL_PC31DOWNTO12_shadow_intermed_4 : std_logic_vector(31 downto 12);
signal R_X_CTRL_PC31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4);
signal V_M_CTRL_PC_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal IR_ADDR31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2);
signal V_E_CTRL_TT3DOWNTO0_shadow_intermed_4 : std_logic_vector(3 downto 0);
signal V_E_CTRL_PC3DOWNTO2_shadow_intermed_3 : std_logic_vector(3 downto 2);
signal RIN_X_CTRL_PC31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4);
signal R_E_CTRL_PC31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12);
signal RIN_M_CTRL_RETT_intermed_1 : STD_ULOGIC;
signal V_M_DCI_LOCK_shadow_intermed_1 : STD_ULOGIC;
signal V_X_RESULT6DOWNTO0_shadow_intermed_1 : std_logic_vector(6 downto 0);
signal RIN_X_DATA04DOWNTO0_intermed_3 : std_logic_vector(4 downto 0);
signal V_X_NERROR_shadow_intermed_1 : STD_ULOGIC;
signal V_A_RFE1_shadow_intermed_1 : STD_ULOGIC;
signal V_D_PC3DOWNTO2_shadow_intermed_1 : std_logic_vector(3 downto 2);
signal V_E_CTRL_LD_shadow_intermed_1 : STD_ULOGIC;
signal ICO_DATA0_intermed_1 : std_logic_vector(31 downto 0);
signal VIR_ADDR_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal R_M_CTRL_PC31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12);
signal V_E_CTRL_PV_shadow_intermed_2 : STD_ULOGIC;
signal RIN_E_CTRL_PC31DOWNTO4_intermed_4 : std_logic_vector(31 downto 4);
signal R_A_CTRL_PC3DOWNTO2_intermed_3 : std_logic_vector(3 downto 2);
signal R_E_CTRL_INST19_intermed_1 : STD_LOGIC;
signal RIN_E_CTRL_TT3DOWNTO0_intermed_4 : std_logic_vector(3 downto 0);
signal R_M_CTRL_PC31DOWNTO4_intermed_3 : std_logic_vector(31 downto 4);
signal V_A_CTRL_PC31DOWNTO4_shadow_intermed_4 : std_logic_vector(31 downto 4);
signal RIN_W_S_DWT_intermed_1 : STD_ULOGIC;
signal V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 : std_logic_vector(31 downto 2);
signal R_D_PC31DOWNTO12_intermed_4 : std_logic_vector(31 downto 12);
signal RIN_X_NERROR_intermed_1 : STD_ULOGIC;
signal R_M_CTRL_PC3DOWNTO2_intermed_2 : std_logic_vector(3 downto 2);
signal ICO_MEXC_intermed_5 : STD_ULOGIC;
signal R_A_CTRL_RD7DOWNTO0_intermed_2 : std_logic_vector(7 downto 0);
signal V_A_CTRL_PC31DOWNTO4_shadow_intermed_1 : std_logic_vector(31 downto 4);
signal IRIN_ADDR31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2);
signal VIR_ADDR31DOWNTO12_shadow_intermed_3 : std_logic_vector(31 downto 12);
signal XC_TRAP_ADDRESS3DOWNTO2_shadow_intermed_1 : std_logic_vector(3 downto 2);
signal R_A_CTRL_INST_intermed_1 : std_logic_vector(31 downto 0);
signal R_E_CTRL_PC31DOWNTO2_intermed_3 : std_logic_vector(31 downto 2);
signal RIN_X_CTRL_TT3DOWNTO0_intermed_3 : std_logic_vector(3 downto 0);
signal RIN_M_CTRL_PC3DOWNTO2_intermed_2 : std_logic_vector(3 downto 2);
signal V_M_CTRL_PC31DOWNTO2_shadow_intermed_4 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_RETT_intermed_2 : STD_ULOGIC;
signal V_X_DATA00_shadow_intermed_1 : STD_LOGIC;
signal RIN_M_CTRL_RD6DOWNTO0_intermed_2 : std_logic_vector(6 downto 0);
signal RIN_E_CTRL_TT3DOWNTO0_intermed_2 : std_logic_vector(3 downto 0);
signal V_M_CTRL_INST_shadow_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_A_CTRL_TT3DOWNTO0_intermed_3 : std_logic_vector(3 downto 0);
signal EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1 : STD_LOGIC_VECTOR(32 downto 3);
signal R_A_CTRL_TT3DOWNTO0_intermed_1 : std_logic_vector(3 downto 0);
signal V_X_DEBUG_shadow_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_PC_shadow_intermed_4 : std_logic_vector(31 downto 2);
signal V_M_CTRL_TT_shadow_intermed_1 : std_logic_vector(5 downto 0);
signal RIN_A_CTRL_PV_intermed_4 : STD_ULOGIC;
signal R_E_MAC_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_PC3DOWNTO2_shadow_intermed_1 : std_logic_vector(3 downto 2);
signal R_M_RESULT1DOWNTO0_intermed_1 : std_logic_vector(1 downto 0);
signal IR_ADDR31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_WREG_intermed_2 : STD_ULOGIC;
signal V_D_MEXC_shadow_intermed_1 : STD_ULOGIC;
signal XC_TRAP_ADDRESS31DOWNTO12_shadow_intermed_2 : std_logic_vector(31 downto 12);
signal R_A_CTRL_LD_intermed_2 : STD_ULOGIC;
signal R_A_CTRL_intermed_2 : PIPELINE_CTRL_TYPE;
signal V_M_CTRL_TRAP_shadow_intermed_2 : STD_ULOGIC;
signal V_A_JMPL_shadow_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_RETT_shadow_intermed_2 : STD_ULOGIC;
signal RIN_M_CTRL_LD_intermed_1 : STD_ULOGIC;
signal V_X_DATA04DOWNTO0_shadow_intermed_3 : std_logic_vector(4 downto 0);
signal RIN_W_S_TT_intermed_1 : STD_LOGIC_VECTOR(7 downto 0);
signal V_A_CTRL_PC_shadow_intermed_5 : std_logic_vector(31 downto 2);
signal V_X_CTRL_PC31DOWNTO12_shadow_intermed_1 : std_logic_vector(31 downto 12);
signal DCO_DATA031_intermed_1 : STD_LOGIC;
signal RIN_A_CTRL_CNT_intermed_1 : std_logic_vector(1 downto 0);
signal R_X_ANNUL_ALL_intermed_3 : STD_ULOGIC;
signal V_X_DATA031_shadow_intermed_3 : STD_LOGIC;
signal DCO_DATA1_intermed_1 : std_logic_vector(31 downto 0);
signal V_E_CTRL_RETT_shadow_intermed_1 : STD_ULOGIC;
signal RIN_E_CTRL_CNT_intermed_1 : std_logic_vector(1 downto 0);
signal V_X_DATA0_shadow_intermed_1 : std_logic_vector(31 downto 0);
signal V_A_CTRL_LD_shadow_intermed_2 : STD_ULOGIC;
signal V_A_CTRL_TT3DOWNTO0_shadow_intermed_6 : std_logic_vector(3 downto 0);
signal R_E_CTRL_PC31DOWNTO4_intermed_3 : std_logic_vector(31 downto 4);
signal RPIN_ERROR_intermed_1 : STD_ULOGIC;
signal V_X_CTRL_PC31DOWNTO2_shadow_intermed_3 : std_logic_vector(31 downto 2);
signal R_W_S_S_intermed_1 : STD_ULOGIC;
signal R_A_CTRL_WICC_intermed_1 : STD_ULOGIC;
signal RIN_A_CTRL_PC31DOWNTO4_intermed_5 : std_logic_vector(31 downto 4);
signal RIN_D_PC31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4);
signal EX_JUMP_ADDRESS31DOWNTO4_shadow_intermed_1 : std_logic_vector(31 downto 4);
signal RIN_D_PC_intermed_5 : std_logic_vector(31 downto 2);
signal V_A_RFA1_shadow_intermed_1 : std_logic_vector(7 downto 0);
signal R_X_CTRL_PC31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2);
signal R_D_PC_intermed_2 : std_logic_vector(31 downto 2);
signal V_A_CTRL_PC3DOWNTO2_shadow_intermed_5 : std_logic_vector(3 downto 2);
signal V_E_CTRL_INST_shadow_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_M_CTRL_PC_intermed_1 : std_logic_vector(31 downto 2);
signal R_X_ANNUL_ALL_intermed_4 : STD_ULOGIC;
signal RIN_A_CTRL_INST_intermed_3 : std_logic_vector(31 downto 0);
signal V_A_CTRL_shadow_intermed_3 : PIPELINE_CTRL_TYPE;
signal R_D_MEXC_intermed_1 : STD_ULOGIC;
signal RIN_X_CTRL_RETT_intermed_1 : STD_ULOGIC;
signal R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 : std_logic_vector(3 downto 0);
signal R_A_CTRL_WICC_intermed_2 : STD_ULOGIC;
signal VDSU_CRDY2_shadow_intermed_1 : STD_LOGIC;
signal V_A_DIVSTART_shadow_intermed_1 : STD_ULOGIC;
signal R_A_CTRL_PC31DOWNTO2_intermed_6 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_TRAP_intermed_4 : STD_ULOGIC;
signal RIN_W_S_PS_intermed_1 : STD_ULOGIC;
signal R_D_MEXC_intermed_3 : STD_ULOGIC;
signal RIN_A_RFA2_intermed_1 : std_logic_vector(7 downto 0);
signal R_X_DATA1_intermed_1 : std_logic_vector(31 downto 0);
signal V_A_CTRL_PV_shadow_intermed_1 : STD_ULOGIC;
signal R_A_CTRL_PC31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4);
signal V_X_CTRL_PC31DOWNTO4_shadow_intermed_2 : std_logic_vector(31 downto 4);
signal RIN_W_S_SVT_intermed_1 : STD_ULOGIC;
signal RIN_E_CTRL_RD6DOWNTO0_intermed_1 : std_logic_vector(6 downto 0);
signal R_D_PC31DOWNTO12_intermed_5 : std_logic_vector(31 downto 12);
signal RIN_A_CTRL_INST19_intermed_1 : STD_LOGIC;
signal RIN_M_CTRL_PV_intermed_1 : STD_ULOGIC;
signal RIN_A_CTRL_RD6DOWNTO0_intermed_4 : std_logic_vector(6 downto 0);
signal RIN_E_OP23_intermed_1 : STD_LOGIC;
signal RIN_E_CTRL_WICC_intermed_2 : STD_ULOGIC;
signal R_D_PC31DOWNTO4_intermed_5 : std_logic_vector(31 downto 4);
signal V_D_MEXC_shadow_intermed_2 : STD_ULOGIC;
signal RIN_D_PC31DOWNTO4_intermed_7 : std_logic_vector(31 downto 4);
signal R_A_CTRL_TRAP_intermed_3 : STD_ULOGIC;
signal V_E_CTRL_INST19_shadow_intermed_2 : STD_LOGIC;
signal RIN_E_CTRL_PC31DOWNTO12_intermed_5 : std_logic_vector(31 downto 12);
signal RIN_D_PC31DOWNTO12_intermed_8 : std_logic_vector(31 downto 12);
signal VP_PWD_shadow_intermed_1 : STD_ULOGIC;
signal RIN_M_CTRL_RD7DOWNTO0_intermed_1 : std_logic_vector(7 downto 0);
signal V_A_CTRL_PC31DOWNTO4_shadow_intermed_2 : std_logic_vector(31 downto 4);
signal RIN_F_PC31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_M_NALIGN_intermed_1 : STD_ULOGIC;
signal RP_ERROR_intermed_1 : STD_ULOGIC;
signal RIN_X_CTRL_PC3DOWNTO2_intermed_2 : std_logic_vector(3 downto 2);
signal V_W_S_TBA_shadow_intermed_1 : STD_LOGIC_VECTOR(19 downto 0);
signal R_F_PC31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12);
signal RIN_E_JMPL_intermed_1 : STD_ULOGIC;
signal RIN_A_CTRL_TRAP_intermed_1 : STD_ULOGIC;
signal RIN_A_RFE2_intermed_1 : STD_ULOGIC;
signal RIN_D_PC_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_CNT_intermed_3 : std_logic_vector(1 downto 0);
signal V_M_CTRL_PC31DOWNTO12_shadow_intermed_3 : std_logic_vector(31 downto 12);
signal V_M_CTRL_PC3DOWNTO2_shadow_intermed_2 : std_logic_vector(3 downto 2);
signal VIR_ADDR31DOWNTO12_shadow_intermed_1 : std_logic_vector(31 downto 12);
signal RIN_E_CTRL_LD_intermed_2 : STD_ULOGIC;
signal V_E_CTRL_PC31DOWNTO12_shadow_intermed_2 : std_logic_vector(31 downto 12);
signal R_E_CTRL_PC31DOWNTO12_intermed_4 : std_logic_vector(31 downto 12);
signal V_X_CTRL_PC3DOWNTO2_shadow_intermed_2 : std_logic_vector(3 downto 2);
signal V_A_CTRL_INST24_shadow_intermed_2 : STD_LOGIC;
signal V_M_CTRL_TRAP_shadow_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_PC31DOWNTO4_shadow_intermed_3 : std_logic_vector(31 downto 4);
signal V_A_CTRL_PC3DOWNTO2_shadow_intermed_4 : std_logic_vector(3 downto 2);
signal R_A_CTRL_PC31DOWNTO2_intermed_5 : std_logic_vector(31 downto 2);
signal R_X_DATA0_intermed_1 : std_logic_vector(31 downto 0);
signal V_E_CTRL_TT_shadow_intermed_2 : std_logic_vector(5 downto 0);
signal V_E_MAC_shadow_intermed_2 : STD_ULOGIC;
signal RIN_E_CTRL_INST19_intermed_2 : STD_LOGIC;
signal RIN_D_PC31DOWNTO2_intermed_3 : std_logic_vector(31 downto 2);
signal IRIN_ADDR_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_X_ANNUL_ALL_intermed_3 : STD_ULOGIC;
signal RIN_E_CTRL_INST_intermed_2 : std_logic_vector(31 downto 0);
signal V_X_CTRL_PC_shadow_intermed_2 : std_logic_vector(31 downto 2);
signal R_M_CTRL_TRAP_intermed_1 : STD_ULOGIC;
signal V_D_CWP_shadow_intermed_2 : std_logic_vector(2 downto 0);
signal V_A_CTRL_PC31DOWNTO12_shadow_intermed_2 : std_logic_vector(31 downto 12);
signal V_A_CTRL_LD_shadow_intermed_1 : STD_ULOGIC;
signal R_A_CTRL_INST19_intermed_2 : STD_LOGIC;
signal RIN_X_MEXC_intermed_1 : STD_ULOGIC;
signal RIN_D_MEXC_intermed_4 : STD_ULOGIC;
signal RIN_A_MULSTART_intermed_1 : STD_ULOGIC;
signal RIN_A_CTRL_TT_intermed_1 : std_logic_vector(5 downto 0);
signal RIN_M_CTRL_TT3DOWNTO0_intermed_2 : std_logic_vector(3 downto 0);
signal R_D_INST1_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_A_CTRL_intermed_1 : PIPELINE_CTRL_TYPE;
signal R_E_CTRL_WICC_intermed_1 : STD_ULOGIC;
signal RIN_M_CTRL_TT3DOWNTO0_intermed_3 : std_logic_vector(3 downto 0);
signal V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 : std_logic_vector(31 downto 2);
signal V_A_CTRL_TT3DOWNTO0_shadow_intermed_1 : std_logic_vector(3 downto 0);
signal RIN_M_DCI_SIGNED_intermed_2 : STD_ULOGIC;
signal V_E_CTRL_TT3DOWNTO0_shadow_intermed_3 : std_logic_vector(3 downto 0);
signal IRIN_ADDR31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4);
signal RIN_X_SET_intermed_1 : STD_LOGIC_VECTOR(0 downto 0);
signal V_M_CTRL_WREG_shadow_intermed_2 : STD_ULOGIC;
signal RIN_X_CTRL_PC31DOWNTO12_intermed_4 : std_logic_vector(31 downto 12);
signal V_D_PC_shadow_intermed_5 : std_logic_vector(31 downto 2);
signal RIN_X_CTRL_TT3DOWNTO0_intermed_2 : std_logic_vector(3 downto 0);
signal R_D_INST0_intermed_1 : std_logic_vector(31 downto 0);
signal R_E_CTRL_PC31DOWNTO4_intermed_4 : std_logic_vector(31 downto 4);
signal RIN_D_CNT_intermed_1 : std_logic_vector(1 downto 0);
signal R_E_CTRL_PC3DOWNTO2_intermed_4 : std_logic_vector(3 downto 2);
signal V_M_DCI_SIGNED_shadow_intermed_2 : STD_ULOGIC;
signal R_D_CNT_intermed_2 : std_logic_vector(1 downto 0);
signal R_E_CTRL_INST20_intermed_1 : STD_LOGIC;
signal RIN_M_DCI_SIGNED_intermed_1 : STD_ULOGIC;
signal RIN_D_PC3DOWNTO2_intermed_5 : std_logic_vector(3 downto 2);
signal RIN_A_CTRL_INST19_intermed_3 : STD_LOGIC;
signal V_E_CTRL_shadow_intermed_1 : PIPELINE_CTRL_TYPE;
signal RIN_A_CTRL_WICC_intermed_1 : STD_ULOGIC;
signal V_X_DATA1_shadow_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_D_CWP_intermed_2 : std_logic_vector(2 downto 0);
signal R_E_CTRL_INST24_intermed_2 : STD_LOGIC;
signal V_A_CTRL_WREG_shadow_intermed_2 : STD_ULOGIC;
signal DCO_DATA031_intermed_2 : STD_LOGIC;
signal R_M_CTRL_TT_intermed_1 : std_logic_vector(5 downto 0);
signal RIN_E_CTRL_WREG_intermed_3 : STD_ULOGIC;
signal V_E_YMSB_shadow_intermed_1 : STD_ULOGIC;
signal IRIN_ADDR31DOWNTO2_intermed_3 : std_logic_vector(31 downto 2);
signal EX_JUMP_ADDRESS3DOWNTO2_shadow_intermed_1 : std_logic_vector(3 downto 2);
signal V_M_CTRL_INST_shadow_intermed_2 : std_logic_vector(31 downto 0);
signal DE_INST24_shadow_intermed_3 : STD_LOGIC;
signal V_D_PC31DOWNTO12_shadow_intermed_2 : std_logic_vector(31 downto 12);
signal V_A_CTRL_PC_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_X_RESULT6DOWNTO0_intermed_1 : std_logic_vector(6 downto 0);
signal R_A_CTRL_PC31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2);
signal V_E_CTRL_CNT_shadow_intermed_1 : std_logic_vector(1 downto 0);
signal VIR_ADDR3DOWNTO2_shadow_intermed_1 : std_logic_vector(3 downto 2);
signal RIN_A_CTRL_INST_intermed_2 : std_logic_vector(31 downto 0);
signal RIN_A_CTRL_intermed_3 : PIPELINE_CTRL_TYPE;
signal RIN_M_RESULT1DOWNTO0_intermed_1 : std_logic_vector(1 downto 0);
signal R_A_CTRL_PV_intermed_3 : STD_ULOGIC;
signal R_D_PC31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2);
signal R_A_CTRL_PC31DOWNTO4_intermed_5 : std_logic_vector(31 downto 4);
signal RIN_A_DIVSTART_intermed_1 : STD_ULOGIC;
signal VIR_ADDR31DOWNTO12_shadow_intermed_2 : std_logic_vector(31 downto 12);
signal V_E_CTRL_INST20_shadow_intermed_2 : STD_LOGIC;
signal RIN_M_CTRL_TT_intermed_1 : std_logic_vector(5 downto 0);
signal RIN_E_CTRL_RD7DOWNTO0_intermed_3 : std_logic_vector(7 downto 0);
signal RIN_D_CWP_intermed_1 : std_logic_vector(2 downto 0);
signal RIN_X_CTRL_WREG_intermed_1 : STD_ULOGIC;
signal RIN_X_CTRL_PC31DOWNTO2_intermed_4 : std_logic_vector(31 downto 2);
signal V_M_CTRL_PC31DOWNTO2_shadow_intermed_5 : std_logic_vector(31 downto 2);
signal RIN_D_PC31DOWNTO2_intermed_7 : std_logic_vector(31 downto 2);
signal RIN_X_CTRL_PC31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2);
signal DSUR_CRDY2_intermed_1 : STD_LOGIC;
signal R_E_CTRL_PC3DOWNTO2_intermed_2 : std_logic_vector(3 downto 2);
signal V_A_CTRL_RD7DOWNTO0_shadow_intermed_1 : std_logic_vector(7 downto 0);
signal R_D_PC31DOWNTO12_intermed_3 : std_logic_vector(31 downto 12);
signal RIN_X_DATA031_intermed_2 : STD_LOGIC;
signal RIN_D_PC31DOWNTO4_intermed_4 : std_logic_vector(31 downto 4);
signal RIN_A_CTRL_INST_intermed_4 : std_logic_vector(31 downto 0);
signal V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 : std_logic_vector(31 downto 2);
signal V_M_CTRL_PC31DOWNTO4_shadow_intermed_2 : std_logic_vector(31 downto 4);
signal DE_INST19_shadow_intermed_1 : STD_LOGIC;
signal RIN_E_CTRL_PC31DOWNTO2_intermed_3 : std_logic_vector(31 downto 2);
signal V_A_CTRL_RD7DOWNTO0_shadow_intermed_2 : std_logic_vector(7 downto 0);
signal V_E_CTRL_INST_shadow_intermed_3 : std_logic_vector(31 downto 0);
signal RIN_X_CTRL_PC31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_X_CTRL_intermed_1 : PIPELINE_CTRL_TYPE;
signal R_D_PC31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12);
signal RIN_A_CTRL_ANNUL_intermed_2 : STD_ULOGIC;
signal V_A_CTRL_CNT_shadow_intermed_3 : std_logic_vector(1 downto 0);
signal R_A_CTRL_PC31DOWNTO12_intermed_6 : std_logic_vector(31 downto 12);
signal V_M_CTRL_PC31DOWNTO12_shadow_intermed_4 : std_logic_vector(31 downto 12);
signal VIR_ADDR31DOWNTO2_shadow_intermed_3 : std_logic_vector(31 downto 2);
signal V_A_MULSTART_shadow_intermed_1 : STD_ULOGIC;
signal RIN_X_DATA1_intermed_2 : std_logic_vector(31 downto 0);
signal RIN_E_CTRL_PC_intermed_2 : std_logic_vector(31 downto 2);
signal V_E_CTRL_PC31DOWNTO12_shadow_intermed_5 : std_logic_vector(31 downto 12);
signal V_M_DCI_SIZE_shadow_intermed_1 : std_logic_vector(1 downto 0);
signal V_A_CTRL_PC31DOWNTO4_shadow_intermed_3 : std_logic_vector(31 downto 4);
signal R_X_RESULT6DOWNTO03DOWNTO0_intermed_3 : std_logic_vector(3 downto 0);
signal R_D_PC31DOWNTO4_intermed_6 : std_logic_vector(31 downto 4);
signal EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_2 : STD_LOGIC_VECTOR(32 downto 3);
signal V_A_CTRL_PV_shadow_intermed_4 : STD_ULOGIC;
signal V_A_CTRL_TT_shadow_intermed_4 : std_logic_vector(5 downto 0);
signal V_X_CTRL_PC3DOWNTO2_shadow_intermed_3 : std_logic_vector(3 downto 2);
signal RIN_X_DATA0_intermed_2 : std_logic_vector(31 downto 0);
signal R_A_CTRL_TT3DOWNTO0_intermed_4 : std_logic_vector(3 downto 0);
signal RIN_D_PC31DOWNTO4_intermed_3 : std_logic_vector(31 downto 4);
signal V_A_CTRL_WREG_shadow_intermed_4 : STD_ULOGIC;
signal RIN_A_CTRL_PC3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2);
signal RIN_D_PC31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2);
signal R_M_CTRL_PC_intermed_2 : std_logic_vector(31 downto 2);
signal R_F_PC31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_M_CTRL_WREG_intermed_1 : STD_ULOGIC;
signal RIN_W_WREG_intermed_1 : STD_ULOGIC;
signal RIN_D_PC31DOWNTO4_intermed_6 : std_logic_vector(31 downto 4);
signal R_D_ANNUL_intermed_1 : STD_ULOGIC;
signal R_A_CTRL_INST_intermed_3 : std_logic_vector(31 downto 0);
signal RIN_M_CTRL_PC31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_E_CTRL_WREG_intermed_2 : STD_ULOGIC;
signal V_E_SARI_shadow_intermed_1 : STD_ULOGIC;
signal R_E_CTRL_RD6DOWNTO0_intermed_2 : std_logic_vector(6 downto 0);
signal V_A_CTRL_PC31DOWNTO2_shadow_intermed_6 : std_logic_vector(31 downto 2);
signal R_A_CTRL_CNT_intermed_3 : std_logic_vector(1 downto 0);
signal RIN_M_CTRL_PV_intermed_2 : STD_ULOGIC;
signal R_A_CTRL_LD_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_WICC_shadow_intermed_2 : STD_ULOGIC;
signal RIN_D_PC31DOWNTO2_intermed_5 : std_logic_vector(31 downto 2);
signal V_D_PC3DOWNTO2_shadow_intermed_3 : std_logic_vector(3 downto 2);
signal RIN_A_CTRL_PC3DOWNTO2_intermed_6 : std_logic_vector(3 downto 2);
signal RIN_X_DATA04DOWNTO0_intermed_1 : std_logic_vector(4 downto 0);
signal DSUIN_CRDY2_intermed_1 : STD_LOGIC;
signal RIN_D_PC31DOWNTO12_intermed_4 : std_logic_vector(31 downto 12);
signal R_E_CTRL_RD6DOWNTO0_intermed_1 : std_logic_vector(6 downto 0);
signal RIN_A_CTRL_INST20_intermed_1 : STD_LOGIC;
signal R_M_RESULT1DOWNTO0_intermed_2 : std_logic_vector(1 downto 0);
signal RIN_M_DCI_SIZE_intermed_2 : std_logic_vector(1 downto 0);
signal DE_INST19_shadow_intermed_3 : STD_LOGIC;
signal IRIN_ADDR31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12);
signal V_A_CTRL_ANNUL_shadow_intermed_4 : STD_ULOGIC;
signal R_E_CTRL_CNT_intermed_1 : std_logic_vector(1 downto 0);
signal V_E_CTRL_INST24_shadow_intermed_2 : STD_LOGIC;
signal RIN_A_CTRL_PC31DOWNTO4_intermed_2 : std_logic_vector(31 downto 4);
signal IRIN_PWD_intermed_1 : STD_ULOGIC;
signal V_D_MEXC_shadow_intermed_5 : STD_ULOGIC;
signal RIN_A_CTRL_PV_intermed_1 : STD_ULOGIC;
signal V_A_CTRL_WICC_shadow_intermed_1 : STD_ULOGIC;
signal R_A_CTRL_PC_intermed_1 : std_logic_vector(31 downto 2);
signal V_F_PC31DOWNTO4_shadow_intermed_1 : std_logic_vector(31 downto 4);
signal R_A_CTRL_RD7DOWNTO0_intermed_3 : std_logic_vector(7 downto 0);
signal RIN_A_CTRL_PC_intermed_1 : std_logic_vector(31 downto 2);
signal R_E_CTRL_INST_intermed_1 : std_logic_vector(31 downto 0);
signal R_E_CTRL_PC31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4);
signal V_A_CTRL_TRAP_shadow_intermed_4 : STD_ULOGIC;
signal V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 : std_logic_vector(31 downto 2);
signal V_F_PC31DOWNTO12_shadow_intermed_1 : std_logic_vector(31 downto 12);
signal R_A_CTRL_PC3DOWNTO2_intermed_5 : std_logic_vector(3 downto 2);
signal R_A_CTRL_CNT_intermed_1 : std_logic_vector(1 downto 0);
signal RIN_D_PC31DOWNTO2_intermed_6 : std_logic_vector(31 downto 2);
signal R_E_CTRL_PC3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2);
signal RIN_X_DATA0_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_E_CTRL_PC_intermed_3 : std_logic_vector(31 downto 2);
signal R_X_CTRL_PC31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12);
signal RIN_X_DATA03_intermed_1 : STD_LOGIC;
signal R_X_DATA04DOWNTO0_intermed_2 : std_logic_vector(4 downto 0);
signal R_E_CTRL_ANNUL_intermed_1 : STD_ULOGIC;
signal V_A_CTRL_RD7DOWNTO0_shadow_intermed_3 : std_logic_vector(7 downto 0);
signal V_M_CTRL_TT3DOWNTO0_shadow_intermed_3 : std_logic_vector(3 downto 0);
signal RIN_X_MAC_intermed_1 : STD_ULOGIC;
signal V_E_SHCNT_shadow_intermed_1 : std_logic_vector(4 downto 0);
signal V_M_CTRL_TT3DOWNTO0_shadow_intermed_2 : std_logic_vector(3 downto 0);
signal V_D_PC31DOWNTO12_shadow_intermed_4 : std_logic_vector(31 downto 12);
signal RIN_D_PC31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12);
signal V_E_CTRL_PC3DOWNTO2_shadow_intermed_5 : std_logic_vector(3 downto 2);
signal RIN_E_CTRL_RETT_intermed_2 : STD_ULOGIC;
signal R_M_CTRL_PC31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2);
signal V_E_OP23_shadow_intermed_1 : STD_LOGIC;
signal V_D_PC_shadow_intermed_2 : std_logic_vector(31 downto 2);
signal R_D_PC3DOWNTO2_intermed_6 : std_logic_vector(3 downto 2);
signal R_M_CTRL_PV_intermed_1 : STD_ULOGIC;
signal RIN_W_RESULT_intermed_1 : std_logic_vector(31 downto 0);
signal V_E_CTRL_ANNUL_shadow_intermed_2 : STD_ULOGIC;
signal V_E_CTRL_PV_shadow_intermed_1 : STD_ULOGIC;
signal RIN_X_LADDR_intermed_1 : std_logic_vector(1 downto 0);
signal RIN_A_CTRL_PC_intermed_5 : std_logic_vector(31 downto 2);
signal XC_VECTT3DOWNTO0_shadow_intermed_1 : STD_LOGIC_VECTOR(3 downto 0);
signal R_E_CTRL_WREG_intermed_1 : STD_ULOGIC;
signal RIN_X_DATA03_intermed_2 : STD_LOGIC;
signal RIN_A_CTRL_TT_intermed_3 : std_logic_vector(5 downto 0);
signal V_D_STEP_shadow_intermed_1 : STD_ULOGIC;
signal R_M_CTRL_PC31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12);
signal DE_INST19_shadow_intermed_2 : STD_LOGIC;
signal RIN_M_CTRL_PC31DOWNTO2_intermed_3 : std_logic_vector(31 downto 2);
signal V_X_CTRL_TRAP_shadow_intermed_1 : STD_ULOGIC;
signal RIN_D_MEXC_intermed_5 : STD_ULOGIC;
signal RIN_X_CTRL_TRAP_intermed_1 : STD_ULOGIC;
signal V_D_PC3DOWNTO2_shadow_intermed_4 : std_logic_vector(3 downto 2);
signal V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 : std_logic_vector(3 downto 0);
signal RIN_A_CTRL_PC3DOWNTO2_intermed_5 : std_logic_vector(3 downto 2);
signal RIN_M_CTRL_PC31DOWNTO4_intermed_3 : std_logic_vector(31 downto 4);
signal RIN_M_CTRL_PC31DOWNTO2_intermed_4 : std_logic_vector(31 downto 2);
signal RIN_F_BRANCH_intermed_1 : STD_ULOGIC;
signal R_D_PC3DOWNTO2_intermed_5 : std_logic_vector(3 downto 2);
signal RIN_A_CTRL_WREG_intermed_1 : STD_ULOGIC;
signal RIN_D_INST0_intermed_2 : std_logic_vector(31 downto 0);
signal R_M_CTRL_CNT_intermed_1 : std_logic_vector(1 downto 0);
signal RIN_E_CTRL_RD7DOWNTO0_intermed_1 : std_logic_vector(7 downto 0);
signal RIN_A_CTRL_PC_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_X_CTRL_PC_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_TT_intermed_4 : std_logic_vector(5 downto 0);
signal V_X_DATA00_shadow_intermed_2 : STD_LOGIC;
signal RIN_A_CTRL_PC31DOWNTO4_intermed_4 : std_logic_vector(31 downto 4);
signal RIN_A_JMPL_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_WREG_shadow_intermed_3 : STD_ULOGIC;
signal V_A_CTRL_WREG_shadow_intermed_1 : STD_ULOGIC;
signal RIN_M_CTRL_ANNUL_intermed_1 : STD_ULOGIC;
signal RIN_X_CTRL_PC31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12);
signal VIR_ADDR31DOWNTO2_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal V_A_CTRL_PC3DOWNTO2_shadow_intermed_1 : std_logic_vector(3 downto 2);
signal RIN_E_CTRL_TT3DOWNTO0_intermed_3 : std_logic_vector(3 downto 0);
signal RIN_M_CTRL_RD7DOWNTO0_intermed_2 : std_logic_vector(7 downto 0);
signal V_E_CTRL_TRAP_shadow_intermed_3 : STD_ULOGIC;
signal V_A_CTRL_CNT_shadow_intermed_2 : std_logic_vector(1 downto 0);
signal V_E_CTRL_ANNUL_shadow_intermed_1 : STD_ULOGIC;
signal V_W_S_TT3DOWNTO0_shadow_intermed_1 : STD_LOGIC_VECTOR(3 downto 0);
signal RIN_M_CTRL_CNT_intermed_1 : std_logic_vector(1 downto 0);
signal DSUR_CRDY2_intermed_2 : STD_LOGIC;
signal V_E_CTRL_RD6DOWNTO0_shadow_intermed_1 : std_logic_vector(6 downto 0);
signal V_A_CTRL_CNT_shadow_intermed_1 : std_logic_vector(1 downto 0);
signal R_E_CTRL_PC_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_RD6DOWNTO0_intermed_1 : std_logic_vector(6 downto 0);
signal R_M_CTRL_TT3DOWNTO0_intermed_3 : std_logic_vector(3 downto 0);
signal RIN_M_CTRL_TT3DOWNTO0_intermed_4 : std_logic_vector(3 downto 0);
signal V_A_CTRL_INST19_shadow_intermed_1 : STD_LOGIC;
signal R_D_PC31DOWNTO2_intermed_5 : std_logic_vector(31 downto 2);
signal RIN_E_CTRL_CNT_intermed_3 : std_logic_vector(1 downto 0);
signal R_E_CTRL_PC31DOWNTO12_intermed_3 : std_logic_vector(31 downto 12);
signal RIN_E_CTRL_TRAP_intermed_1 : STD_ULOGIC;
signal RIN_X_DATA00_intermed_3 : STD_LOGIC;
signal R_E_CTRL_PC_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_E_OP131_intermed_1 : STD_LOGIC;
signal R_D_CNT_intermed_1 : std_logic_vector(1 downto 0);
signal R_D_PC_intermed_3 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_PC31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12);
signal R_M_CTRL_WREG_intermed_1 : STD_ULOGIC;
signal R_D_PC31DOWNTO2_intermed_4 : std_logic_vector(31 downto 2);
signal DE_INST_shadow_intermed_3 : std_logic_vector(31 downto 0);
signal RIN_D_PC_intermed_3 : std_logic_vector(31 downto 2);
signal V_A_CTRL_INST20_shadow_intermed_3 : STD_LOGIC;
signal R_A_CTRL_TT3DOWNTO0_intermed_5 : std_logic_vector(3 downto 0);
signal RIN_A_CTRL_CNT_intermed_2 : std_logic_vector(1 downto 0);
signal RIN_A_CTRL_intermed_2 : PIPELINE_CTRL_TYPE;
signal RIN_X_CTRL_PC_intermed_2 : std_logic_vector(31 downto 2);
signal R_A_CTRL_WREG_intermed_1 : STD_ULOGIC;
signal V_X_CTRL_PC31DOWNTO2_shadow_intermed_4 : std_logic_vector(31 downto 2);
signal R_X_CTRL_PC31DOWNTO2_intermed_3 : std_logic_vector(31 downto 2);
signal RIN_D_PC_intermed_6 : std_logic_vector(31 downto 2);
signal RIN_E_CTRL_PC31DOWNTO4_intermed_3 : std_logic_vector(31 downto 4);
signal R_X_CTRL_PC31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2);
signal V_A_ET_shadow_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_PC31DOWNTO4_shadow_intermed_1 : std_logic_vector(31 downto 4);
signal RIN_A_CTRL_INST20_intermed_3 : STD_LOGIC;
signal RIN_W_EXCEPT_intermed_1 : STD_ULOGIC;
signal V_X_DATA031_shadow_intermed_2 : STD_LOGIC;
signal R_A_CTRL_ANNUL_intermed_1 : STD_ULOGIC;
signal R_F_PC31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12);
signal RIN_E_CTRL_RD6DOWNTO0_intermed_2 : std_logic_vector(6 downto 0);
signal VIR_ADDR31DOWNTO2_shadow_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_X_DATA00_intermed_1 : STD_LOGIC;
signal RIN_E_CTRL_ANNUL_intermed_1 : STD_ULOGIC;
signal RIN_E_CTRL_PC31DOWNTO4_intermed_5 : std_logic_vector(31 downto 4);
signal V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_3 : std_logic_vector(3 downto 0);
signal V_M_CTRL_WICC_shadow_intermed_1 : STD_ULOGIC;
signal V_A_CTRL_PC31DOWNTO2_shadow_intermed_7 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_RETT_intermed_1 : STD_ULOGIC;
signal RIN_E_CTRL_PC31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2);
signal V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_D_PC31DOWNTO12_intermed_5 : std_logic_vector(31 downto 12);
signal VIR_ADDR3DOWNTO2_shadow_intermed_2 : std_logic_vector(3 downto 2);
signal R_A_CTRL_PV_intermed_2 : STD_ULOGIC;
signal V_A_CTRL_PC3DOWNTO2_shadow_intermed_2 : std_logic_vector(3 downto 2);
signal R_E_CTRL_PC3DOWNTO2_intermed_3 : std_logic_vector(3 downto 2);
signal V_A_CTRL_ANNUL_shadow_intermed_3 : STD_ULOGIC;
signal RIN_A_CTRL_PC3DOWNTO2_intermed_4 : std_logic_vector(3 downto 2);
signal V_A_CTRL_TT3DOWNTO0_shadow_intermed_3 : std_logic_vector(3 downto 0);
signal R_A_CTRL_PC3DOWNTO2_intermed_2 : std_logic_vector(3 downto 2);
signal V_D_CNT_shadow_intermed_2 : std_logic_vector(1 downto 0);
signal V_M_CTRL_ANNUL_shadow_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_M_CTRL_PC31DOWNTO4_intermed_2 : std_logic_vector(31 downto 4);
signal R_M_CTRL_TT3DOWNTO0_intermed_1 : std_logic_vector(3 downto 0);
signal V_E_CTRL_LD_shadow_intermed_2 : STD_ULOGIC;
signal RIN_X_CTRL_ANNUL_intermed_1 : STD_ULOGIC;
signal RIN_D_PC3DOWNTO2_intermed_3 : std_logic_vector(3 downto 2);
signal V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 : std_logic_vector(31 downto 2);
signal RIN_E_CTRL_TT_intermed_2 : std_logic_vector(5 downto 0);
signal RIN_E_CTRL_CNT_intermed_2 : std_logic_vector(1 downto 0);
signal RIN_A_CTRL_PC_intermed_4 : std_logic_vector(31 downto 2);
signal RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_4 : std_logic_vector(3 downto 0);
signal R_D_PC31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12);
signal XC_TRAP_ADDRESS31DOWNTO4_shadow_intermed_1 : std_logic_vector(31 downto 4);
signal RIN_A_CTRL_INST24_intermed_3 : STD_LOGIC;
signal V_W_S_TT3DOWNTO0_shadow_intermed_2 : STD_LOGIC_VECTOR(3 downto 0);
signal RIN_E_CTRL_RD7DOWNTO0_intermed_2 : std_logic_vector(7 downto 0);
signal RIN_A_CTRL_INST24_intermed_1 : STD_LOGIC;
signal RIN_D_PC31DOWNTO4_intermed_2 : std_logic_vector(31 downto 4);
signal V_A_CTRL_shadow_intermed_2 : PIPELINE_CTRL_TYPE;
signal DE_INST_shadow_intermed_4 : std_logic_vector(31 downto 0);
signal RIN_E_CTRL_PV_intermed_3 : STD_ULOGIC;
signal V_A_CTRL_TT_shadow_intermed_2 : std_logic_vector(5 downto 0);
signal RIN_M_CTRL_PC_intermed_3 : std_logic_vector(31 downto 2);
signal V_A_CTRL_WREG_shadow_intermed_3 : STD_ULOGIC;
signal R_M_CTRL_RD6DOWNTO0_intermed_1 : std_logic_vector(6 downto 0);
signal XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_PV_intermed_2 : STD_ULOGIC;
signal RIN_E_CTRL_PC3DOWNTO2_intermed_2 : std_logic_vector(3 downto 2);
signal RIN_X_CTRL_RD7DOWNTO0_intermed_1 : std_logic_vector(7 downto 0);
signal V_A_CTRL_TRAP_shadow_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_TRAP_shadow_intermed_1 : STD_ULOGIC;
signal RIN_E_MAC_intermed_1 : STD_ULOGIC;
signal R_X_DATA00_intermed_2 : STD_LOGIC;
signal RIN_E_MAC_intermed_2 : STD_ULOGIC;
signal RIN_A_CTRL_RD7DOWNTO0_intermed_4 : std_logic_vector(7 downto 0);
signal RIN_A_CTRL_PC31DOWNTO2_intermed_7 : std_logic_vector(31 downto 2);
signal R_M_CTRL_PC31DOWNTO12_intermed_3 : std_logic_vector(31 downto 12);
signal V_D_PC_shadow_intermed_3 : std_logic_vector(31 downto 2);
signal RIN_D_PC31DOWNTO4_intermed_5 : std_logic_vector(31 downto 4);
signal V_M_RESULT1DOWNTO0_shadow_intermed_2 : std_logic_vector(1 downto 0);
signal R_E_CTRL_PC31DOWNTO4_intermed_2 : std_logic_vector(31 downto 4);
signal V_E_CTRL_PC31DOWNTO12_shadow_intermed_3 : std_logic_vector(31 downto 12);
signal V_X_INTACK_shadow_intermed_1 : STD_ULOGIC;
signal RIN_A_CTRL_ANNUL_intermed_5 : STD_ULOGIC;
signal V_M_CTRL_PC31DOWNTO4_shadow_intermed_3 : std_logic_vector(31 downto 4);
signal V_A_CTRL_TT3DOWNTO0_shadow_intermed_4 : std_logic_vector(3 downto 0);
signal RIN_X_RESULT_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_E_CTRL_TT3DOWNTO0_intermed_5 : std_logic_vector(3 downto 0);
signal RIN_A_CTRL_PC31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2);
signal EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal V_D_PC3DOWNTO2_shadow_intermed_5 : std_logic_vector(3 downto 2);
signal DE_INST20_shadow_intermed_1 : STD_LOGIC;
signal V_E_CTRL_RD7DOWNTO0_shadow_intermed_2 : std_logic_vector(7 downto 0);
signal V_X_CTRL_PC31DOWNTO12_shadow_intermed_4 : std_logic_vector(31 downto 12);
signal V_E_CTRL_TRAP_shadow_intermed_2 : STD_ULOGIC;
signal V_A_CTRL_PC31DOWNTO4_shadow_intermed_5 : std_logic_vector(31 downto 4);
signal V_A_CTRL_RD6DOWNTO0_shadow_intermed_2 : std_logic_vector(6 downto 0);
signal RIN_A_CTRL_PC31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12);
signal IR_ADDR31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12);
signal RIN_E_ALUCIN_intermed_1 : STD_ULOGIC;
signal R_X_CTRL_PC31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12);
signal R_A_CTRL_PC3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2);
signal DE_INST_shadow_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_M_CTRL_INST_intermed_2 : std_logic_vector(31 downto 0);
signal R_A_CTRL_TRAP_intermed_2 : STD_ULOGIC;
signal RIN_A_CTRL_PC31DOWNTO12_intermed_4 : std_logic_vector(31 downto 12);
signal R_A_CTRL_WREG_intermed_2 : STD_ULOGIC;
signal R_M_CTRL_PC31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4);
signal V_E_OP13_shadow_intermed_1 : STD_LOGIC;
signal V_A_CTRL_INST24_shadow_intermed_1 : STD_LOGIC;
signal V_X_CTRL_PC31DOWNTO12_shadow_intermed_3 : std_logic_vector(31 downto 12);
signal IRIN_ADDR31DOWNTO12_intermed_3 : std_logic_vector(31 downto 12);
signal V_X_CTRL_PC_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal R_M_CTRL_PC3DOWNTO2_intermed_3 : std_logic_vector(3 downto 2);
signal V_E_CTRL_PC3DOWNTO2_shadow_intermed_2 : std_logic_vector(3 downto 2);
signal RIN_X_CTRL_TT_intermed_1 : std_logic_vector(5 downto 0);
signal V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_TT3DOWNTO0_intermed_6 : std_logic_vector(3 downto 0);
signal RIN_D_PC3DOWNTO2_intermed_7 : std_logic_vector(3 downto 2);
signal V_A_CTRL_INST_shadow_intermed_2 : std_logic_vector(31 downto 0);
signal V_X_CTRL_PC31DOWNTO4_shadow_intermed_1 : std_logic_vector(31 downto 4);
signal V_M_RESULT1DOWNTO0_shadow_intermed_1 : std_logic_vector(1 downto 0);
signal R_A_CTRL_INST24_intermed_2 : STD_LOGIC;
signal R_F_PC31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2);
signal V_A_CTRL_TRAP_shadow_intermed_3 : STD_ULOGIC;
signal R_D_CNT_intermed_4 : std_logic_vector(1 downto 0);
signal RIN_A_CTRL_WREG_intermed_4 : STD_ULOGIC;
signal V_M_CTRL_PC31DOWNTO4_shadow_intermed_1 : std_logic_vector(31 downto 4);
signal RIN_A_CTRL_PC3DOWNTO2_intermed_3 : std_logic_vector(3 downto 2);
signal V_E_CTRL_INST20_shadow_intermed_1 : STD_LOGIC;
signal R_D_MEXC_intermed_2 : STD_ULOGIC;
signal R_D_PC_intermed_4 : std_logic_vector(31 downto 2);
signal RIN_D_PC_intermed_1 : std_logic_vector(31 downto 2);
signal IRIN_ADDR3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2);
signal V_E_CTRL_RD7DOWNTO0_shadow_intermed_1 : std_logic_vector(7 downto 0);
signal RIN_E_OP1_intermed_1 : std_logic_vector(31 downto 0);
signal V_D_PC31DOWNTO4_shadow_intermed_3 : std_logic_vector(31 downto 4);
signal V_A_CTRL_PV_shadow_intermed_3 : STD_ULOGIC;
signal V_D_PC31DOWNTO2_shadow_intermed_6 : std_logic_vector(31 downto 2);
signal V_X_CTRL_TT3DOWNTO0_shadow_intermed_2 : std_logic_vector(3 downto 0);
signal DE_INST20_shadow_intermed_2 : STD_LOGIC;
signal V_E_CTRL_RD7DOWNTO0_shadow_intermed_3 : std_logic_vector(7 downto 0);
signal V_E_CTRL_CNT_shadow_intermed_3 : std_logic_vector(1 downto 0);
signal RIN_E_CTRL_RETT_intermed_1 : STD_ULOGIC;
signal V_D_PC31DOWNTO12_shadow_intermed_3 : std_logic_vector(31 downto 12);
signal V_D_PC31DOWNTO12_shadow_intermed_7 : std_logic_vector(31 downto 12);
signal V_M_CTRL_CNT_shadow_intermed_2 : std_logic_vector(1 downto 0);
signal R_D_PC31DOWNTO4_intermed_3 : std_logic_vector(31 downto 4);
signal RIN_A_CTRL_PC3DOWNTO2_intermed_2 : std_logic_vector(3 downto 2);
signal RIN_X_INTACK_intermed_1 : STD_ULOGIC;
signal RIN_E_OP231_intermed_1 : STD_LOGIC;
signal RIN_X_DATA031_intermed_3 : STD_LOGIC;
signal RIN_D_PC31DOWNTO2_intermed_4 : std_logic_vector(31 downto 2);
signal V_D_PC31DOWNTO4_shadow_intermed_2 : std_logic_vector(31 downto 4);
signal V_A_CTRL_ANNUL_shadow_intermed_1 : STD_ULOGIC;
signal R_M_CTRL_TT3DOWNTO0_intermed_2 : std_logic_vector(3 downto 0);
signal V_F_PC_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_E_ET_intermed_1 : STD_ULOGIC;
signal V_D_MEXC_shadow_intermed_3 : STD_ULOGIC;
signal XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_2 : std_logic_vector(31 downto 2);
signal V_F_PC31DOWNTO2_shadow_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_E_CTRL_PV_intermed_2 : STD_ULOGIC;
signal R_A_CTRL_RD7DOWNTO0_intermed_1 : std_logic_vector(7 downto 0);
signal ICO_MEXC_intermed_2 : STD_ULOGIC;
signal V_X_DCI_SIGNED_shadow_intermed_1 : STD_ULOGIC;
signal RIN_A_STEP_intermed_1 : STD_ULOGIC;
signal V_E_ALUCIN_shadow_intermed_1 : STD_ULOGIC;
signal V_A_CTRL_PC31DOWNTO4_shadow_intermed_6 : std_logic_vector(31 downto 4);
signal V_D_CNT_shadow_intermed_3 : std_logic_vector(1 downto 0);
signal V_D_PC31DOWNTO4_shadow_intermed_1 : std_logic_vector(31 downto 4);
signal RIN_X_CTRL_CNT_intermed_1 : std_logic_vector(1 downto 0);
signal V_D_ANNUL_shadow_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_PC31DOWNTO2_shadow_intermed_5 : std_logic_vector(31 downto 2);
signal V_E_CTRL_PV_shadow_intermed_3 : STD_ULOGIC;
signal VP_ERROR_shadow_intermed_1 : STD_ULOGIC;
signal RIN_X_RESULT6DOWNTO0_intermed_2 : std_logic_vector(6 downto 0);
signal R_D_PC31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4);
signal RIN_F_PC31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_E_CTRL_PC_intermed_1 : std_logic_vector(31 downto 2);
signal R_A_CTRL_PC31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12);
signal RIN_A_CTRL_PC31DOWNTO12_intermed_6 : std_logic_vector(31 downto 12);
signal V_A_CTRL_INST24_shadow_intermed_3 : STD_LOGIC;
signal V_E_CTRL_PC_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal V_X_CTRL_RD7DOWNTO0_shadow_intermed_1 : std_logic_vector(7 downto 0);
signal RIN_M_MUL_intermed_1 : STD_ULOGIC;
signal RIN_A_CTRL_INST20_intermed_2 : STD_LOGIC;
signal RIN_A_CTRL_RD7DOWNTO0_intermed_1 : std_logic_vector(7 downto 0);
signal V_A_CTRL_TT3DOWNTO0_shadow_intermed_2 : std_logic_vector(3 downto 0);
signal R_A_CTRL_INST_intermed_2 : std_logic_vector(31 downto 0);
signal RIN_E_CTRL_PC31DOWNTO2_intermed_6 : std_logic_vector(31 downto 2);
signal V_M_CTRL_TT_shadow_intermed_2 : std_logic_vector(5 downto 0);
signal V_D_INST0_shadow_intermed_2 : std_logic_vector(31 downto 0);
signal DCO_DATA03_intermed_1 : STD_LOGIC;
signal RIN_M_CTRL_intermed_1 : PIPELINE_CTRL_TYPE;
signal RIN_A_CTRL_RD7DOWNTO0_intermed_3 : std_logic_vector(7 downto 0);
signal V_D_PC31DOWNTO2_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_E_CTRL_PC31DOWNTO4_intermed_2 : std_logic_vector(31 downto 4);
signal V_D_PC31DOWNTO12_shadow_intermed_8 : std_logic_vector(31 downto 12);
signal RIN_E_CTRL_LD_intermed_1 : STD_ULOGIC;
signal R_X_CTRL_PC_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_WY_intermed_1 : STD_ULOGIC;
signal RIN_D_PC3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2);
signal R_E_CTRL_INST24_intermed_1 : STD_LOGIC;
signal V_M_DCI_shadow_intermed_1 : DC_IN_TYPE;
signal V_M_CTRL_shadow_intermed_1 : PIPELINE_CTRL_TYPE;
signal RIN_M_DCI_SIZE_intermed_1 : std_logic_vector(1 downto 0);
signal R_E_CTRL_PV_intermed_2 : STD_ULOGIC;
signal EX_ADD_RES32DOWNTO3_shadow_intermed_1 : STD_LOGIC_VECTOR(32 downto 3);
signal RIN_D_MEXC_intermed_1 : STD_ULOGIC;
signal R_A_CTRL_PC31DOWNTO2_intermed_3 : std_logic_vector(31 downto 2);
signal DSUIN_TBUFCNT_intermed_1 : STD_LOGIC_VECTOR(6 downto 0);
signal R_E_CTRL_PC31DOWNTO12_intermed_5 : std_logic_vector(31 downto 12);
signal R_A_CTRL_PC3DOWNTO2_intermed_4 : std_logic_vector(3 downto 2);
signal V_A_CTRL_INST20_shadow_intermed_1 : STD_LOGIC;
signal RIN_E_CTRL_PC31DOWNTO12_intermed_3 : std_logic_vector(31 downto 12);
signal V_A_CTRL_RD6DOWNTO0_shadow_intermed_4 : std_logic_vector(6 downto 0);
signal R_E_CTRL_PC31DOWNTO2_intermed_4 : std_logic_vector(31 downto 2);
signal R_A_CTRL_TT3DOWNTO0_intermed_2 : std_logic_vector(3 downto 0);
signal RIN_A_CTRL_CNT_intermed_4 : std_logic_vector(1 downto 0);
signal V_D_INST1_shadow_intermed_2 : std_logic_vector(31 downto 0);
signal RIN_E_CTRL_INST_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_X_DEBUG_intermed_1 : STD_ULOGIC;
signal RIN_M_Y_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_E_SHCNT_intermed_1 : std_logic_vector(4 downto 0);
signal RIN_E_CTRL_TRAP_intermed_2 : STD_ULOGIC;
signal RIN_F_PC31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12);
signal R_E_CTRL_INST20_intermed_2 : STD_LOGIC;
signal RIN_A_CTRL_ANNUL_intermed_3 : STD_ULOGIC;
signal RIN_D_ANNUL_intermed_2 : STD_ULOGIC;
signal ICO_DATA1_intermed_1 : std_logic_vector(31 downto 0);
signal R_M_CTRL_PC31DOWNTO12_intermed_4 : std_logic_vector(31 downto 12);
signal V_M_CTRL_TT3DOWNTO0_shadow_intermed_1 : std_logic_vector(3 downto 0);
signal V_X_CTRL_TT3DOWNTO0_shadow_intermed_1 : std_logic_vector(3 downto 0);
signal RIN_D_MEXC_intermed_3 : STD_ULOGIC;
signal V_E_CTRL_INST24_shadow_intermed_1 : STD_LOGIC;
signal R_W_S_TT3DOWNTO0_intermed_2 : STD_LOGIC_VECTOR(3 downto 0);
signal DSUIN_CRDY2_intermed_2 : STD_LOGIC;
signal V_X_RESULT6DOWNTO0_shadow_intermed_2 : std_logic_vector(6 downto 0);
signal RIN_D_PC3DOWNTO2_intermed_2 : std_logic_vector(3 downto 2);
signal V_D_PC_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal R_A_CTRL_PC31DOWNTO4_intermed_2 : std_logic_vector(31 downto 4);
signal RIN_E_CTRL_RD6DOWNTO0_intermed_3 : std_logic_vector(6 downto 0);
signal R_A_CTRL_PC31DOWNTO12_intermed_4 : std_logic_vector(31 downto 12);
signal V_X_DATA031_shadow_intermed_1 : STD_LOGIC;
signal RIN_X_ANNUL_ALL_intermed_2 : STD_ULOGIC;
signal IRIN_ADDR3DOWNTO2_intermed_2 : std_logic_vector(3 downto 2);
signal RIN_D_SET_intermed_1 : STD_LOGIC_VECTOR(0 downto 0);
signal DCO_DATA0_intermed_1 : std_logic_vector(31 downto 0);
signal R_E_CTRL_CNT_intermed_2 : std_logic_vector(1 downto 0);
signal RIN_W_S_S_intermed_2 : STD_ULOGIC;
signal IRIN_ADDR31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12);
signal RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_3 : std_logic_vector(3 downto 0);
signal RIN_W_S_TT3DOWNTO0_intermed_2 : STD_LOGIC_VECTOR(3 downto 0);
signal V_A_CTRL_LD_shadow_intermed_3 : STD_ULOGIC;
signal V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 : std_logic_vector(31 downto 2);
signal RIN_M_CTRL_PC_intermed_2 : std_logic_vector(31 downto 2);
signal R_D_INST1_intermed_2 : std_logic_vector(31 downto 0);
signal V_E_CTRL_shadow_intermed_2 : PIPELINE_CTRL_TYPE;
signal RIN_X_DATA1_intermed_1 : std_logic_vector(31 downto 0);
signal R_A_CTRL_RD6DOWNTO0_intermed_2 : std_logic_vector(6 downto 0);
signal RIN_A_CTRL_PC31DOWNTO2_intermed_3 : std_logic_vector(31 downto 2);
signal RIN_E_CTRL_intermed_1 : PIPELINE_CTRL_TYPE;
signal RIN_A_CTRL_RD6DOWNTO0_intermed_3 : std_logic_vector(6 downto 0);
signal RIN_A_CTRL_TT3DOWNTO0_intermed_1 : std_logic_vector(3 downto 0);
signal RIN_F_PC_intermed_1 : std_logic_vector(31 downto 2);
signal V_D_PC31DOWNTO2_shadow_intermed_8 : std_logic_vector(31 downto 2);
signal V_D_CNT_shadow_intermed_1 : std_logic_vector(1 downto 0);
signal RIN_A_CTRL_LD_intermed_2 : STD_ULOGIC;
signal V_D_PC31DOWNTO4_shadow_intermed_5 : std_logic_vector(31 downto 4);
signal RIN_M_CTRL_PC31DOWNTO4_intermed_4 : std_logic_vector(31 downto 4);
signal R_A_CTRL_RETT_intermed_1 : STD_ULOGIC;
signal RIN_E_CTRL_INST_intermed_3 : std_logic_vector(31 downto 0);
signal R_D_MEXC_intermed_4 : STD_ULOGIC;
signal RIN_M_RESULT1DOWNTO0_intermed_3 : std_logic_vector(1 downto 0);
signal RIN_D_CNT_intermed_5 : std_logic_vector(1 downto 0);
signal V_A_CTRL_PC31DOWNTO12_shadow_intermed_1 : std_logic_vector(31 downto 12);
signal R_D_PC31DOWNTO2_intermed_3 : std_logic_vector(31 downto 2);
signal RIN_M_CTRL_PC31DOWNTO12_intermed_4 : std_logic_vector(31 downto 12);
signal RIN_M_CTRL_TT3DOWNTO0_intermed_1 : std_logic_vector(3 downto 0);
signal RIN_D_ANNUL_intermed_1 : STD_ULOGIC;
signal V_A_CTRL_shadow_intermed_1 : PIPELINE_CTRL_TYPE;
signal V_E_CTRL_PC31DOWNTO12_shadow_intermed_1 : std_logic_vector(31 downto 12);
signal RIN_M_CTRL_PC3DOWNTO2_intermed_4 : std_logic_vector(3 downto 2);
signal V_A_CTRL_PC31DOWNTO12_shadow_intermed_5 : std_logic_vector(31 downto 12);
signal R_D_PC31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_E_CTRL_PC3DOWNTO2_intermed_5 : std_logic_vector(3 downto 2);
signal RIN_E_CTRL_PC31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12);
signal R_A_CTRL_PC_intermed_4 : std_logic_vector(31 downto 2);
signal R_A_CTRL_ANNUL_intermed_4 : STD_ULOGIC;
signal V_X_RESULT_shadow_intermed_1 : std_logic_vector(31 downto 0);
signal R_E_CTRL_PC31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2);
signal R_A_CTRL_PC31DOWNTO4_intermed_3 : std_logic_vector(31 downto 4);
signal V_D_CNT_shadow_intermed_5 : std_logic_vector(1 downto 0);
signal R_A_CTRL_TT_intermed_2 : std_logic_vector(5 downto 0);
signal RIN_A_CTRL_PC31DOWNTO12_intermed_5 : std_logic_vector(31 downto 12);
signal V_A_CTRL_TT3DOWNTO0_shadow_intermed_5 : std_logic_vector(3 downto 0);
signal RIN_W_S_S_intermed_1 : STD_ULOGIC;
signal V_M_CTRL_CNT_shadow_intermed_1 : std_logic_vector(1 downto 0);
signal V_A_CTRL_PC31DOWNTO12_shadow_intermed_7 : std_logic_vector(31 downto 12);
signal V_A_CTRL_WICC_shadow_intermed_2 : STD_ULOGIC;
signal R_X_DATA03_intermed_1 : STD_LOGIC;
signal RIN_M_DCI_intermed_1 : DC_IN_TYPE;
signal R_A_CTRL_CNT_intermed_2 : std_logic_vector(1 downto 0);
signal RIN_W_S_EF_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_RD6DOWNTO0_shadow_intermed_2 : std_logic_vector(6 downto 0);
signal RIN_A_CTRL_LD_intermed_3 : STD_ULOGIC;
signal V_M_CTRL_RD6DOWNTO0_shadow_intermed_1 : std_logic_vector(6 downto 0);
signal R_E_CTRL_INST_intermed_2 : std_logic_vector(31 downto 0);
signal RIN_M_CTRL_RD6DOWNTO0_intermed_1 : std_logic_vector(6 downto 0);
signal V_F_PC3DOWNTO2_shadow_intermed_1 : std_logic_vector(3 downto 2);
signal EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_2 : STD_LOGIC_VECTOR(30 downto 11);
signal V_X_ANNUL_ALL_shadow_intermed_3 : STD_ULOGIC;
signal V_F_PC31DOWNTO12_shadow_intermed_2 : std_logic_vector(31 downto 12);
signal RIN_E_CTRL_INST24_intermed_1 : STD_LOGIC;
signal R_A_CTRL_PV_intermed_1 : STD_ULOGIC;
signal RIN_A_CTRL_RETT_intermed_3 : STD_ULOGIC;
signal R_E_CTRL_TT_intermed_2 : std_logic_vector(5 downto 0);
signal RIN_D_PC31DOWNTO12_intermed_7 : std_logic_vector(31 downto 12);
signal EX_ADD_RES32DOWNTO34DOWNTO3_shadow_intermed_1 : STD_LOGIC_VECTOR(4 downto 3);
signal V_E_CTRL_INST_shadow_intermed_2 : std_logic_vector(31 downto 0);
signal V_M_CTRL_PC31DOWNTO12_shadow_intermed_1 : std_logic_vector(31 downto 12);
signal DCO_MEXC_intermed_1 : STD_ULOGIC;
signal RIN_E_CWP_intermed_1 : std_logic_vector(2 downto 0);
signal V_A_CTRL_CNT_shadow_intermed_4 : std_logic_vector(1 downto 0);
signal V_A_CTRL_ANNUL_shadow_intermed_2 : STD_ULOGIC;
signal R_A_CTRL_PC31DOWNTO12_intermed_3 : std_logic_vector(31 downto 12);
signal R_A_CTRL_PC31DOWNTO2_intermed_4 : std_logic_vector(31 downto 2);
signal R_X_RESULT6DOWNTO0_intermed_2 : std_logic_vector(6 downto 0);
signal R_E_CTRL_intermed_1 : PIPELINE_CTRL_TYPE;
signal V_E_OP231_shadow_intermed_1 : STD_LOGIC;
signal RIN_A_CTRL_WREG_intermed_3 : STD_ULOGIC;
signal V_A_CTRL_INST_shadow_intermed_4 : std_logic_vector(31 downto 0);
signal V_E_CTRL_PC31DOWNTO12_shadow_intermed_6 : std_logic_vector(31 downto 12);
signal V_M_CTRL_PC3DOWNTO2_shadow_intermed_1 : std_logic_vector(3 downto 2);
signal RPIN_ERROR_intermed_2 : STD_ULOGIC;
signal R_E_CTRL_TT3DOWNTO0_intermed_3 : std_logic_vector(3 downto 0);
signal V_D_CWP_shadow_intermed_1 : std_logic_vector(2 downto 0);
signal V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_PV_intermed_3 : STD_ULOGIC;
signal RIN_M_CTRL_PC31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4);
signal RIN_E_CTRL_INST24_intermed_2 : STD_LOGIC;
signal RIN_X_DCI_SIZE_intermed_1 : std_logic_vector(1 downto 0);
signal RIN_F_PC31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12);
signal R_A_CTRL_TT3DOWNTO0_intermed_3 : std_logic_vector(3 downto 0);
signal DCO_DATA00_intermed_1 : STD_LOGIC;
signal V_M_Y31_shadow_intermed_1 : STD_LOGIC;
signal R_E_CTRL_PC31DOWNTO2_intermed_5 : std_logic_vector(31 downto 2);
signal R_A_CTRL_PC31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2);
signal V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal R_A_CTRL_INST19_intermed_1 : STD_LOGIC;
signal RIN_E_CTRL_TT_intermed_1 : std_logic_vector(5 downto 0);
signal RIN_E_CTRL_PC31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2);
signal R_X_CTRL_PC3DOWNTO2_intermed_2 : std_logic_vector(3 downto 2);
signal RIN_X_ANNUL_ALL_intermed_4 : STD_ULOGIC;
signal V_A_CTRL_INST_shadow_intermed_1 : std_logic_vector(31 downto 0);
signal V_X_CTRL_PC31DOWNTO12_shadow_intermed_2 : std_logic_vector(31 downto 12);
signal IRIN_ADDR31DOWNTO4_intermed_2 : std_logic_vector(31 downto 4);
signal RIN_E_CTRL_PC3DOWNTO2_intermed_4 : std_logic_vector(3 downto 2);
signal RIN_A_CTRL_PC31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4);
signal DCO_DATA04DOWNTO0_intermed_1 : std_logic_vector(4 downto 0);
signal RIN_E_CTRL_ANNUL_intermed_2 : STD_ULOGIC;
signal V_E_CTRL_INST19_shadow_intermed_1 : STD_LOGIC;
signal RIN_A_CTRL_PC_intermed_3 : std_logic_vector(31 downto 2);
signal V_X_DATA03_shadow_intermed_1 : STD_LOGIC;
signal V_E_OP1_shadow_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_M_CTRL_CNT_intermed_2 : std_logic_vector(1 downto 0);
signal RIN_A_CTRL_PC31DOWNTO2_intermed_6 : std_logic_vector(31 downto 2);
signal RIN_D_MEXC_intermed_2 : STD_ULOGIC;
signal R_D_PC31DOWNTO4_intermed_2 : std_logic_vector(31 downto 4);
signal RIN_X_CTRL_INST_intermed_1 : std_logic_vector(31 downto 0);
signal V_M_Y31_shadow_intermed_2 : STD_LOGIC;
signal R_W_S_TT3DOWNTO0_intermed_1 : STD_LOGIC_VECTOR(3 downto 0);
signal R_A_CTRL_ANNUL_intermed_3 : STD_ULOGIC;
signal R_A_CTRL_TRAP_intermed_1 : STD_ULOGIC;
signal RIN_M_CTRL_WICC_intermed_1 : STD_ULOGIC;
signal R_D_PC31DOWNTO2_intermed_7 : std_logic_vector(31 downto 2);
signal RIN_X_ANNUL_ALL_intermed_1 : STD_ULOGIC;
signal V_M_CTRL_WREG_shadow_intermed_1 : STD_ULOGIC;
signal V_A_CTRL_RD7DOWNTO0_shadow_intermed_4 : std_logic_vector(7 downto 0);
signal RIN_A_RFE1_intermed_1 : STD_ULOGIC;
signal V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal V_D_PC31DOWNTO4_shadow_intermed_4 : std_logic_vector(31 downto 4);
signal R_A_CTRL_PC31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12);
signal V_M_MAC_shadow_intermed_1 : STD_ULOGIC;
signal V_D_PC31DOWNTO2_shadow_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_TRAP_intermed_2 : STD_ULOGIC;
signal R_E_CTRL_RD7DOWNTO0_intermed_1 : std_logic_vector(7 downto 0);
signal R_E_CTRL_PC_intermed_3 : std_logic_vector(31 downto 2);
signal R_X_DATA00_intermed_1 : STD_LOGIC;
signal V_X_ANNUL_ALL_shadow_intermed_1 : STD_ULOGIC;
signal R_D_PC_intermed_5 : std_logic_vector(31 downto 2);
signal R_X_DATA03_intermed_2 : STD_LOGIC;
signal RIN_F_PC31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4);
signal RIN_W_S_CWP_intermed_1 : std_logic_vector(2 downto 0);
signal V_W_S_PS_shadow_intermed_1 : STD_ULOGIC;
signal R_A_CTRL_intermed_1 : PIPELINE_CTRL_TYPE;
signal R_A_CTRL_TT_intermed_3 : std_logic_vector(5 downto 0);
signal RIN_A_CTRL_PC31DOWNTO4_intermed_6 : std_logic_vector(31 downto 4);
signal V_D_PC31DOWNTO2_shadow_intermed_7 : std_logic_vector(31 downto 2);
signal RIN_M_CTRL_PC31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2);
signal R_X_DATA1_intermed_2 : std_logic_vector(31 downto 0);
signal R_D_PC3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2);
signal RIN_X_CTRL_PC3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2);
signal V_E_MAC_shadow_intermed_1 : STD_ULOGIC;
signal RIN_X_ICC_intermed_1 : STD_LOGIC_VECTOR(3 downto 0);
signal RIN_M_MAC_intermed_1 : STD_ULOGIC;
signal RIN_W_S_TT3DOWNTO0_intermed_1 : STD_LOGIC_VECTOR(3 downto 0);
signal R_D_PC31DOWNTO4_intermed_4 : std_logic_vector(31 downto 4);
signal V_A_CTRL_PC3DOWNTO2_shadow_intermed_6 : std_logic_vector(3 downto 2);
signal R_X_ANNUL_ALL_intermed_1 : STD_ULOGIC;
signal EX_JUMP_ADDRESS_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_X_CTRL_PV_intermed_1 : STD_ULOGIC;
signal EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_2 : STD_LOGIC_VECTOR(32 downto 13);
signal RIN_A_CTRL_INST_intermed_1 : std_logic_vector(31 downto 0);
signal R_A_CTRL_RD6DOWNTO0_intermed_3 : std_logic_vector(6 downto 0);
signal IR_ADDR31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12);
signal RIN_D_PC3DOWNTO2_intermed_6 : std_logic_vector(3 downto 2);
signal RIN_M_Y31_intermed_2 : STD_LOGIC;
signal RIN_X_DATA04DOWNTO0_intermed_2 : std_logic_vector(4 downto 0);
signal V_D_PC31DOWNTO2_shadow_intermed_3 : std_logic_vector(31 downto 2);
signal R_M_DCI_SIZE_intermed_1 : std_logic_vector(1 downto 0);
signal V_E_CTRL_PC3DOWNTO2_shadow_intermed_4 : std_logic_vector(3 downto 2);
signal V_E_OP2_shadow_intermed_1 : std_logic_vector(31 downto 0);
signal V_E_CTRL_TT3DOWNTO0_shadow_intermed_5 : std_logic_vector(3 downto 0);
signal V_A_CTRL_INST20_shadow_intermed_2 : STD_LOGIC;
signal RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 : std_logic_vector(3 downto 0);
signal V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_4 : std_logic_vector(3 downto 0);
signal R_X_RESULT6DOWNTO03DOWNTO0_intermed_2 : std_logic_vector(3 downto 0);
signal RIN_M_CTRL_TRAP_intermed_2 : STD_ULOGIC;
signal V_A_CTRL_INST_shadow_intermed_3 : std_logic_vector(31 downto 0);
begin
comb : process(ico, dco, rfo, r, wpr, ir, dsur, rstn, holdn, irqi, dbgi, fpo, cpo, tbo, mulo, divo, dummy, rp, handlerTrap)
variable v : registers;
variable vp : pwd_register_type;
variable vwpr : watchpoint_registers;
variable vdsu : dsu_registers;
variable npc : std_logic_vector(31 downto 2);
variable de_raddr1, de_raddr2 : std_logic_vector(9 downto 0);
variable de_rs2, de_rd : std_logic_vector(4 downto 0);
variable de_hold_pc, de_branch, de_fpop, de_ldlock : std_ulogic;
variable de_cwp, de_cwp2 : cwptype;
variable de_inull : std_ulogic;
variable de_ren1, de_ren2 : std_ulogic;
variable de_wcwp : std_ulogic;
variable de_inst : word;
variable de_branch_address : pctype;
variable de_icc : std_logic_vector(3 downto 0);
variable de_fbranch, de_cbranch : std_ulogic;
variable de_rs1mod : std_ulogic;
variable ra_op1, ra_op2 : word;
variable ra_div : std_ulogic;
variable ex_jump, ex_link_pc : std_ulogic;
variable ex_jump_address : pctype;
variable ex_add_res : std_logic_vector(32 downto 0);
variable ex_shift_res, ex_logic_res, ex_misc_res : word;
variable ex_edata, ex_edata2 : word;
variable ex_dci : dc_in_type;
variable ex_force_a2, ex_load, ex_ymsb : std_ulogic;
variable ex_op1, ex_op2, ex_result, ex_result2, mul_op2 : word;
variable ex_shcnt : std_logic_vector(4 downto 0);
variable ex_dsuen : std_ulogic;
variable ex_ldbp2 : std_ulogic;
variable ex_sari : std_ulogic;
variable me_inull, me_nullify, me_nullify2 : std_ulogic;
variable me_iflush : std_ulogic;
variable me_newtt : std_logic_vector(5 downto 0);
variable me_asr18 : word;
variable me_signed : std_ulogic;
variable me_size, me_laddr : std_logic_vector(1 downto 0);
variable me_icc : std_logic_vector(3 downto 0);
variable xc_result : word;
variable xc_df_result : word;
variable xc_waddr : std_logic_vector(9 downto 0);
variable xc_exception, xc_wreg : std_ulogic;
variable xc_trap_address : pctype;
variable xc_vectt : std_logic_vector(7 downto 0);
variable xc_trap : std_ulogic;
variable xc_fpexack : std_ulogic;
variable xc_rstn, xc_halt : std_ulogic;
-- variable wr_rf1_data, wr_rf2_data : word;
variable diagdata : word;
variable tbufi : tracebuf_in_type;
variable dbgm : std_ulogic;
variable fpcdbgwr : std_ulogic;
variable vfpi : fpc_in_type;
variable dsign : std_ulogic;
variable pwrd, sidle : std_ulogic;
variable vir : irestart_register;
variable icnt : std_ulogic;
variable tbufcntx : std_logic_vector(7-1 downto 0);
begin
v := r;
vwpr := wpr;
vdsu := dsur;
vp := rp;
xc_fpexack := '0';
sidle := '0';
fpcdbgwr := '0';
vir := ir;
xc_rstn := rstn;
-----------------------------------------------------------------------
-- WRITE STAGE
-----------------------------------------------------------------------
-- wr_rf1_data := rfo.data1; wr_rf2_data := rfo.data2;
-- if irfwt = 0 then
-- if r.w.wreg = '1' then
-- if r.a.rfa1 = r.w.wa then wr_rf1_data := r.w.result; end if;
-- if r.a.rfa2 = r.w.wa then wr_rf2_data := r.w.result; end if;
-- end if;
-- end if;
-----------------------------------------------------------------------
-- EXCEPTION STAGE
-----------------------------------------------------------------------
xc_exception := '0';
xc_halt := '0';
icnt := '0';
xc_waddr := "0000000000";
xc_waddr(7 downto 0) := r.x.ctrl.rd(7 downto 0);
xc_trap := r.x.mexc or r.x.ctrl.trap or handlerTrap;
v.x.nerror := rp.error;
if(handlerTrap = '1')then
xc_vectt := "00" & TT_WATCH;
elsif r.x.mexc = '1' then
xc_vectt := "00" & TT_DAEX;
elsif r.x.ctrl.tt = TT_TICC then
xc_vectt := '1' & r.x.result(6 downto 0);
else
xc_vectt := "00" & r.x.ctrl.tt;
end if;
if r.w.s.svt = '0' then
xc_trap_address(31 downto 4) := r.w.s.tba & xc_vectt;
else
xc_trap_address(31 downto 4) := r.w.s.tba & "00000000";
end if;
xc_trap_address(3 downto 2) := "00";
xc_wreg := '0';
v.x.annul_all := '0';
if (r.x.ctrl.ld = '1') then
if (lddel = 2) then
xc_result := ld_align(r.x.data, r.x.set, r.x.dci.size, r.x.laddr, r.x.dci.signed);
else
xc_result := r.x.data(0);
end if;
else
xc_result := r.x.result;
end if;
xc_df_result := xc_result;
dbgm := dbgexc(r, dbgi, xc_trap, xc_vectt);
if (dbgi.dsuen and dbgi.dbreak) = '0'then
v.x.debug := '0';
end if;
pwrd := '0';
case r.x.rstate is
when run =>
if (not r.x.ctrl.annul and r.x.ctrl.pv and not r.x.debug) = '1' then
icnt := holdn;
end if;
if dbgm = '1' then
v.x.annul_all := '1';
vir.addr := r.x.ctrl.pc;
v.x.rstate := dsu1;
v.x.debug := '1';
v.x.npc := npc_find(r);
vdsu.tt := xc_vectt;
vdsu.err := dbgerr(r, dbgi, xc_vectt);
elsif (pwrd = '1') and (ir.pwd = '0') then
v.x.annul_all := '1';
vir.addr := r.x.ctrl.pc;
v.x.rstate := dsu1;
v.x.npc := npc_find(r);
vp.pwd := '1';
elsif (r.x.ctrl.annul or xc_trap) = '0' then
xc_wreg := r.x.ctrl.wreg;
sp_write (r, wpr, v.w.s, vwpr);
vir.pwd := '0';
elsif ((not r.x.ctrl.annul) and xc_trap) = '1' then
xc_exception := '1';
xc_result := r.x.ctrl.pc(31 downto 2) & "00";
xc_wreg := '1';
v.w.s.tt := xc_vectt;
v.w.s.ps := r.w.s.s;
v.w.s.s := '1';
v.x.annul_all := '1';
v.x.rstate := trap;
xc_waddr := "0000000000";
xc_waddr(6 downto 0) := r.w.s.cwp & "0001";
v.x.npc := npc_find(r);
fpexack(r, xc_fpexack);
if r.w.s.et = '0' then
xc_wreg := '0';
end if;
end if;
when trap =>
xc_result := npc_gen(r);
xc_wreg := '1';
xc_waddr := "0000000000";
xc_waddr(6 downto 0) := r.w.s.cwp & "0010";
if (r.w.s.et = '1') then
v.w.s.et := '0';
v.x.rstate := run;
v.w.s.cwp := r.w.s.cwp - 1;
else
v.x.rstate := dsu1;
xc_wreg := '0';
vp.error := '1';
end if;
when dsu1 =>
xc_exception := '1';
v.x.annul_all := '1';
xc_trap_address(31 downto 2) := r.f.pc;
xc_trap_address(31 downto 2) := ir.addr;
vir.addr := npc_gen(r)(31 downto 2);
v.x.rstate := dsu2;
v.x.debug := r.x.debug;
when dsu2 =>
xc_exception := '1';
v.x.annul_all := '1';
xc_trap_address(31 downto 2) := r.f.pc;
sidle := (rp.pwd or rp.error) and ico.idle and dco.idle and not r.x.debug;
if dbgi.reset = '1' then
vp.pwd := '0';
vp.error := '0';
end if;
if (dbgi.dsuen and dbgi.dbreak) = '1'then
v.x.debug := '1';
end if;
diagwr(r, dsur, ir, dbgi, wpr, v.w.s, vwpr, vdsu.asi, xc_trap_address, vir.addr, vdsu.tbufcnt, xc_wreg, xc_waddr, xc_result, fpcdbgwr);
xc_halt := dbgi.halt;
if r.x.ipend = '1' then
vp.pwd := '0';
end if;
if (rp.error or rp.pwd or r.x.debug or xc_halt) = '0' then
v.x.rstate := run;
v.x.annul_all := '0';
vp.error := '0';
xc_trap_address(31 downto 2) := ir.addr;
v.x.debug := '0';
vir.pwd := '1';
end if;
when others =>
end case;
irq_intack(r, holdn, v.x.intack);
itrace(r, dsur, vdsu, xc_result, xc_exception, dbgi, rp.error, xc_trap, tbufcntx, tbufi);
vdsu.tbufcnt := tbufcntx;
v.w.except := xc_exception;
v.w.result := xc_result;
if (r.x.rstate = dsu2) then
v.w.except := '0';
end if;
v.w.wa := xc_waddr(7 downto 0);
v.w.wreg := xc_wreg and holdn;
rfi.wdata <= xc_result;
rfi.waddr <= xc_waddr;
rfi.wren <= (xc_wreg and holdn) and not dco.scanen;
irqo.intack <= r.x.intack and holdn;
irqo.irl <= r.w.s.tt(3 downto 0);
irqo.pwd <= rp.pwd;
irqo.fpen <= r.w.s.ef;
dbgo.halt <= xc_halt;
dbgo.pwd <= rp.pwd;
dbgo.idle <= sidle;
dbgo.icnt <= icnt;
dci.intack <= r.x.intack and holdn;
if (xc_rstn = '0') then
v.w.except := '0';
v.w.s.et := '0';
v.w.s.svt := '0';
v.w.s.dwt := '0';
v.w.s.ef := '0';-- needed for AX
v.x.annul_all := '1';
v.x.rstate := run;
vir.pwd := '0';
vp.pwd := '0';
v.x.debug := '0';
v.x.nerror := '0';
if (dbgi.dsuen and dbgi.dbreak) = '1' then
v.x.rstate := dsu1;
v.x.debug := '1';
end if;
end if;
if not FPEN then
v.w.s.ef := '0';
end if;
-----------------------------------------------------------------------
-- MEMORY STAGE
-----------------------------------------------------------------------
v.x.ctrl := r.m.ctrl;
v.x.dci := r.m.dci;
v.x.ctrl.rett := r.m.ctrl.rett and not r.m.ctrl.annul;
v.x.mac := r.m.mac;
v.x.laddr := r.m.result(1 downto 0);
v.x.ctrl.annul := r.m.ctrl.annul or v.x.annul_all;
mul_res(r, v.w.s.asr18, v.x.result, v.x.y, me_asr18, me_icc);
mem_trap(r, wpr, v.x.ctrl.annul, holdn, v.x.ctrl.trap, me_iflush, me_nullify, v.m.werr, v.x.ctrl.tt);
me_newtt := v.x.ctrl.tt;
irq_trap(r, ir, irqi.irl, v.x.ctrl.annul, v.x.ctrl.pv, v.x.ctrl.trap, me_newtt, me_nullify, v.m.irqen, v.m.irqen2, me_nullify2, v.x.ctrl.trap, v.x.ipend, v.x.ctrl.tt);
if (r.m.ctrl.ld or not dco.mds) = '1' then
v.x.data(0) := dco.data(0);
v.x.data(1) := dco.data(1);
v.x.set := dco.set(0 downto 0);
if dco.mds = '0' then
me_size := r.x.dci.size;
me_laddr := r.x.laddr;
me_signed := r.x.dci.signed;
else
me_size := v.x.dci.size;
me_laddr := v.x.laddr;
me_signed := v.x.dci.signed;
end if;
if lddel /= 2 then
v.x.data(0) := ld_align(v.x.data, v.x.set, me_size, me_laddr, me_signed);
end if;
end if;
v.x.mexc := dco.mexc;
v.x.icc := me_icc;
v.x.ctrl.wicc := r.m.ctrl.wicc and not v.x.annul_all;
if (r.x.rstate = dsu2) then
me_nullify2 := '0';
v.x.set := dco.set(0 downto 0);
end if;
if(r.m.result = catchAddress)then
dci.maddress <= targetAddress;
dci.msu <= '1';
dci.esu <= '1';
else
dci.maddress <= r.m.result;
dci.msu <= r.m.su;
dci.esu <= r.e.su;
end if;
dci.enaddr <= r.m.dci.enaddr;
dci.asi <= r.m.dci.asi;
dci.size <= r.m.dci.size;
dci.nullify <= me_nullify2;
dci.lock <= r.m.dci.lock and not r.m.ctrl.annul;
dci.read <= r.m.dci.read;
dci.write <= r.m.dci.write;
dci.flush <= me_iflush;
dci.dsuen <= r.m.dci.dsuen;
dbgo.ipend <= v.x.ipend;
-----------------------------------------------------------------------
-- EXECUTE STAGE
-----------------------------------------------------------------------
v.m.ctrl := r.e.ctrl;
ex_op1 := r.e.op1;
ex_op2 := r.e.op2;
v.m.ctrl.rett := r.e.ctrl.rett and not r.e.ctrl.annul;
v.m.ctrl.wreg := r.e.ctrl.wreg and not v.x.annul_all;
ex_ymsb := r.e.ymsb;
mul_op2 := ex_op2;
ex_shcnt := r.e.shcnt;
v.e.cwp := r.a.cwp;
ex_sari := r.e.sari;
v.m.su := r.e.su;
v.m.mul := '0';
if lddel = 1 then
if r.e.ldbp1 = '1' then
ex_op1 := r.x.data(0);
ex_sari := r.x.data(0)(31) and r.e.ctrl.inst(19) and r.e.ctrl.inst(20);
end if;
if r.e.ldbp2 = '1' then
ex_op2 := r.x.data(0);
ex_ymsb := r.x.data(0)(0);
mul_op2 := ex_op2;
ex_shcnt := r.x.data(0)(4 downto 0);
if r.e.invop2 = '1' then
ex_op2 := not ex_op2;
ex_shcnt := not ex_shcnt;
end if;
end if;
end if;
ex_add_res := (ex_op1 & '1') + (ex_op2 & r.e.alucin);
if ex_add_res(2 downto 1) = "00" then
v.m.nalign := '0';
else
v.m.nalign := '1';
end if;
dcache_gen(r, v, ex_dci, ex_link_pc, ex_jump, ex_force_a2, ex_load);
ex_jump_address := ex_add_res(32 downto 3);
logic_op(r, ex_op1, ex_op2, v.x.y, ex_ymsb, ex_logic_res, v.m.y);
ex_shift_res := shift(r, ex_op1, ex_op2, ex_shcnt, ex_sari);
misc_op(r, wpr, ex_op1, ex_op2, xc_df_result, v.x.y, ex_misc_res, ex_edata);
ex_add_res(3):= ex_add_res(3) or ex_force_a2;
alu_select(r, ex_add_res, ex_op1, ex_op2, ex_shift_res, ex_logic_res, ex_misc_res, ex_result, me_icc, v.m.icc, v.m.divz);
dbg_cache(holdn, dbgi, r, dsur, ex_result, ex_dci, ex_result2, v.m.dci);
fpstdata(r, ex_edata, ex_result2, fpo.data, ex_edata2, v.m.result);
cwp_ex(r, v.m.wcwp);
v.m.ctrl.annul := v.m.ctrl.annul or v.x.annul_all;
v.m.ctrl.wicc := r.e.ctrl.wicc and not v.x.annul_all;
v.m.mac := r.e.mac;
if (true and (r.x.rstate = dsu2)) then
v.m.ctrl.ld := '1';
end if;
dci.eenaddr <= v.m.dci.enaddr;
dci.eaddress <= ex_add_res(32 downto 1);
dci.edata <= ex_edata2;
-----------------------------------------------------------------------
-- REGFILE STAGE
-----------------------------------------------------------------------
v.e.ctrl := r.a.ctrl;
v.e.jmpl := r.a.jmpl;
v.e.ctrl.annul := r.a.ctrl.annul or v.x.annul_all;
v.e.ctrl.rett := r.a.ctrl.rett and not r.a.ctrl.annul;
v.e.ctrl.wreg := r.a.ctrl.wreg and not v.x.annul_all;
v.e.su := r.a.su;
v.e.et := r.a.et;
v.e.ctrl.wicc := r.a.ctrl.wicc and not v.x.annul_all;
exception_detect(r, wpr, dbgi, r.a.ctrl.trap, r.a.ctrl.tt, v.e.ctrl.trap, v.e.ctrl.tt);
op_mux(r, rfo.data1, v.m.result, v.x.result, xc_df_result, "00000000000000000000000000000000", r.a.rsel1, v.e.ldbp1, ra_op1);
op_mux(r, rfo.data2, v.m.result, v.x.result, xc_df_result, r.a.imm, r.a.rsel2, ex_ldbp2, ra_op2);
alu_op(r, ra_op1, ra_op2, v.m.icc, v.m.y(0), ex_ldbp2, v.e.op1, v.e.op2, v.e.aluop, v.e.alusel, v.e.aluadd, v.e.shcnt, v.e.sari, v.e.shleft, v.e.ymsb, v.e.mul, ra_div, v.e.mulstep, v.e.mac, v.e.ldbp2, v.e.invop2);
cin_gen(r, v.m.icc(0), v.e.alucin);
-----------------------------------------------------------------------
-- DECODE STAGE
-----------------------------------------------------------------------
de_inst := r.d.inst(conv_integer(r.d.set));
de_icc := r.m.icc;
v.a.cwp := r.d.cwp;
su_et_select(r, v.w.s.ps, v.w.s.s, v.w.s.et, v.a.su, v.a.et);
wicc_y_gen(de_inst, v.a.ctrl.wicc, v.a.ctrl.wy);
cwp_ctrl(r, v.w.s.wim, de_inst, de_cwp, v.a.wovf, v.a.wunf, de_wcwp);
rs1_gen(r, de_inst, v.a.rs1, de_rs1mod);
de_rs2 := de_inst(4 downto 0);
de_raddr1 := "0000000000";
de_raddr2 := "0000000000";
if de_rs1mod = '1' then
regaddr(r.d.cwp, de_inst(29 downto 26) & v.a.rs1(0), de_raddr1(7 downto 0));
else
regaddr(r.d.cwp, de_inst(18 downto 15) & v.a.rs1(0), de_raddr1(7 downto 0));
end if;
regaddr(r.d.cwp, de_rs2, de_raddr2(7 downto 0));
v.a.rfa1 := de_raddr1(7 downto 0);
v.a.rfa2 := de_raddr2(7 downto 0);
rd_gen(r, de_inst, v.a.ctrl.wreg, v.a.ctrl.ld, de_rd);
regaddr(de_cwp, de_rd, v.a.ctrl.rd);
fpbranch(de_inst, fpo.cc, de_fbranch);
fpbranch(de_inst, cpo.cc, de_cbranch);
v.a.imm := imm_data(r, de_inst);
lock_gen(r, de_rs2, de_rd, v.a.rfa1, v.a.rfa2, v.a.ctrl.rd, de_inst, fpo.ldlock, v.e.mul, ra_div, v.a.ldcheck1, v.a.ldcheck2, de_ldlock, v.a.ldchkra, v.a.ldchkex);
ic_ctrl(r, de_inst, v.x.annul_all, de_ldlock, branch_true(de_icc, de_inst), de_fbranch, de_cbranch, fpo.ccv, cpo.ccv, v.d.cnt, v.d.pc, de_branch, v.a.ctrl.annul, v.d.annul, v.a.jmpl, de_inull, v.d.pv, v.a.ctrl.pv, de_hold_pc, v.a.ticc, v.a.ctrl.rett, v.a.mulstart, v.a.divstart);
cwp_gen(r, v, v.a.ctrl.annul, de_wcwp, de_cwp, v.d.cwp);
v.d.inull := ra_inull_gen(r, v);
op_find(r, v.a.ldchkra, v.a.ldchkex, v.a.rs1, v.a.rfa1, false, v.a.rfe1, v.a.rsel1, v.a.ldcheck1);
op_find(r, v.a.ldchkra, v.a.ldchkex, de_rs2, v.a.rfa2, imm_select(de_inst), v.a.rfe2, v.a.rsel2, v.a.ldcheck2);
de_branch_address := branch_address(de_inst, r.d.pc);
v.a.ctrl.annul := v.a.ctrl.annul or v.x.annul_all;
v.a.ctrl.wicc := v.a.ctrl.wicc and not v.a.ctrl.annul;
v.a.ctrl.wreg := v.a.ctrl.wreg and not v.a.ctrl.annul;
v.a.ctrl.rett := v.a.ctrl.rett and not v.a.ctrl.annul;
v.a.ctrl.wy := v.a.ctrl.wy and not v.a.ctrl.annul;
v.a.ctrl.trap := r.d.mexc;
v.a.ctrl.tt := "000000";
v.a.ctrl.inst := de_inst;
v.a.ctrl.pc := r.d.pc;
v.a.ctrl.cnt := r.d.cnt;
v.a.step := r.d.step;
if holdn = '0' then
de_raddr1(7 downto 0) := r.a.rfa1;
de_raddr2(7 downto 0) := r.a.rfa2;
de_ren1 := r.a.rfe1;
de_ren2 := r.a.rfe2;
else
de_ren1 := v.a.rfe1;
de_ren2 := v.a.rfe2;
end if;
if ((dbgi.denable and not dbgi.dwrite) = '1') and (r.x.rstate = dsu2) then
de_raddr1(7 downto 0) := dbgi.daddr(9 downto 2);
de_ren1 := '1';
end if;
v.d.step := dbgi.step and not r.d.annul;
rfi.raddr1 <= de_raddr1;
rfi.raddr2 <= de_raddr2;
rfi.ren1 <= de_ren1 and not dco.scanen;
rfi.ren2 <= de_ren2 and not dco.scanen;
rfi.diag <= dco.testen & "000";
ici.inull <= de_inull;
ici.flush <= me_iflush;
if (xc_rstn = '0') then
v.d.cnt := "00";
end if;
-----------------------------------------------------------------------
-- FETCH STAGE
-----------------------------------------------------------------------
npc := r.f.pc;
if (xc_rstn = '0') then
v.f.pc := "000000000000000000000000000000";
v.f.branch := '0';
v.f.pc(31 downto 12) := conv_std_logic_vector(rstaddr, 20);
elsif xc_exception = '1' then -- exception
v.f.branch := '1';
v.f.pc := xc_trap_address;
npc := v.f.pc;
elsif de_hold_pc = '1' then
v.f.pc := r.f.pc;
v.f.branch := r.f.branch;
if ex_jump = '1' then
v.f.pc := ex_jump_address;
v.f.branch := '1';
npc := v.f.pc;
end if;
elsif ex_jump = '1' then
v.f.pc := ex_jump_address;
v.f.branch := '1';
npc := v.f.pc;
elsif de_branch = '1' then
v.f.pc := branch_address(de_inst, r.d.pc);
v.f.branch := '1';
npc := v.f.pc;
else
v.f.branch := '0';
v.f.pc(31 downto 2) := r.f.pc(31 downto 2) + 1;-- Address incrementer
npc := v.f.pc;
end if;
ici.dpc <= r.d.pc(31 downto 2) & "00";
ici.fpc <= r.f.pc(31 downto 2) & "00";
ici.rpc <= npc(31 downto 2) & "00";
ici.fbranch <= r.f.branch;
ici.rbranch <= v.f.branch;
ici.su <= v.a.su;
ici.fline <= "00000000000000000000000000000";
ici.flushl <= '0';
if (ico.mds and de_hold_pc) = '0' then
v.d.inst(0) := ico.data(0);-- latch instruction
v.d.inst(1) := ico.data(1);-- latch instruction
v.d.set := ico.set(0 downto 0);-- latch instruction
v.d.mexc := ico.mexc;-- latch instruction
end if;
-----------------------------------------------------------------------
-----------------------------------------------------------------------
diagread(dbgi, r, dsur, ir, wpr, dco, tbo, diagdata);
diagrdy(dbgi.denable, dsur, r.m.dci, dco.mds, ico, vdsu.crdy);
-----------------------------------------------------------------------
-- OUTPUTS
-----------------------------------------------------------------------
rin <= v;
wprin <= vwpr;
dsuin <= vdsu;
irin <= vir;
muli.start <= r.a.mulstart and not r.a.ctrl.annul;
muli.signed <= r.e.ctrl.inst(19);
muli.op1 <= (ex_op1(31) and r.e.ctrl.inst(19)) & ex_op1;
muli.op2 <= (mul_op2(31) and r.e.ctrl.inst(19)) & mul_op2;
muli.mac <= r.e.ctrl.inst(24);
muli.acc(39 downto 32) <= r.x.y(7 downto 0);
muli.acc(31 downto 0) <= r.w.s.asr18;
muli.flush <= r.x.annul_all;
divi.start <= r.a.divstart and not r.a.ctrl.annul;
divi.signed <= r.e.ctrl.inst(19);
divi.flush <= r.x.annul_all;
divi.op1 <= (ex_op1(31) and r.e.ctrl.inst(19)) & ex_op1;
divi.op2 <= (ex_op2(31) and r.e.ctrl.inst(19)) & ex_op2;
if (r.a.divstart and not r.a.ctrl.annul) = '1' then
dsign := r.a.ctrl.inst(19);
else
dsign := r.e.ctrl.inst(19);
end if;
divi.y <= (r.m.y(31) and dsign) & r.m.y;
rpin <= vp;
dbgo.dsu <= '1';
dbgo.dsumode <= r.x.debug;
dbgo.crdy <= dsur.crdy(2);
dbgo.data <= diagdata;
tbi <= tbufi;
dbgo.error <= dummy and not r.x.nerror;
-- pragma translate_off
if FPEN then
-- pragma translate_on
vfpi.flush := v.x.annul_all;
vfpi.exack := xc_fpexack;
vfpi.a_rs1 := r.a.rs1;
vfpi.d.inst := de_inst;
vfpi.d.cnt := r.d.cnt;
vfpi.d.annul := v.x.annul_all or r.d.annul;
vfpi.d.trap := r.d.mexc;
vfpi.d.pc(1 downto 0) := (others => '0');
vfpi.d.pc(31 downto 2) := r.d.pc(31 downto 2);
vfpi.d.pv := r.d.pv;
vfpi.a.pc(1 downto 0) := (others => '0');
vfpi.a.pc(31 downto 2) := r.a.ctrl.pc(31 downto 2);
vfpi.a.inst := r.a.ctrl.inst;
vfpi.a.cnt := r.a.ctrl.cnt;
vfpi.a.trap := r.a.ctrl.trap;
vfpi.a.annul := r.a.ctrl.annul;
vfpi.a.pv := r.a.ctrl.pv;
vfpi.e.pc(1 downto 0) := (others => '0');
vfpi.e.pc(31 downto 2) := r.e.ctrl.pc(31 downto 2);
vfpi.e.inst := r.e.ctrl.inst;
vfpi.e.cnt := r.e.ctrl.cnt;
vfpi.e.trap := r.e.ctrl.trap;
vfpi.e.annul := r.e.ctrl.annul;
vfpi.e.pv := r.e.ctrl.pv;
vfpi.m.pc(1 downto 0) := (others => '0');
vfpi.m.pc(31 downto 2) := r.m.ctrl.pc(31 downto 2);
vfpi.m.inst := r.m.ctrl.inst;
vfpi.m.cnt := r.m.ctrl.cnt;
vfpi.m.trap := r.m.ctrl.trap;
vfpi.m.annul := r.m.ctrl.annul;
vfpi.m.pv := r.m.ctrl.pv;
vfpi.x.pc(1 downto 0) := (others => '0');
vfpi.x.pc(31 downto 2) := r.x.ctrl.pc(31 downto 2);
vfpi.x.inst := r.x.ctrl.inst;
vfpi.x.cnt := r.x.ctrl.cnt;
vfpi.x.trap := xc_trap;
vfpi.x.annul := r.x.ctrl.annul;
vfpi.x.pv := r.x.ctrl.pv;
vfpi.lddata := xc_df_result;--xc_result;
if r.x.rstate = dsu2 then
vfpi.dbg.enable := dbgi.denable;
else
vfpi.dbg.enable := '0';
end if;
vfpi.dbg.write := fpcdbgwr;
vfpi.dbg.fsr := dbgi.daddr(22);-- IU reg access
vfpi.dbg.addr := dbgi.daddr(6 downto 2);
vfpi.dbg.data := dbgi.ddata;
fpi <= vfpi;
cpi <= vfpi;-- dummy, just to kill some warnings ...
-- pragma translate_off
end if;
-- pragma translate_on
-- Assignments to be moved with variables
-- These assignments must be moved to process COMB/
EX_EDATA2_shadow <= EX_EDATA2;
V_E_SU_shadow <= V.E.SU;
V_M_RESULT_shadow <= V.M.RESULT;
V_A_SU_shadow <= V.A.SU;
V_M_SU_shadow <= V.M.SU;
V_A_ET_shadow <= V.A.ET;
EX_ADD_RES32DOWNTO34DOWNTO3_shadow <= EX_ADD_RES ( 32 DOWNTO 3 )( 4 DOWNTO 3 );
ICNT_shadow <= ICNT;
EX_OP1_shadow <= EX_OP1;
V_M_CTRL_PC_shadow <= V.M.CTRL.PC;
V_E_CTRL_PC3DOWNTO2_shadow <= V.E.CTRL.PC( 3 DOWNTO 2 );
DE_REN1_shadow <= DE_REN1;
DE_INST_shadow <= DE_INST;
V_A_CTRL_CNT_shadow <= V.A.CTRL.CNT;
V_F_PC3DOWNTO2_shadow <= V.F.PC( 3 DOWNTO 2 );
V_W_S_TT_shadow <= V.W.S.TT;
V_X_RESULT6DOWNTO0_shadow <= V.X.RESULT ( 6 DOWNTO 0 );
EX_JUMP_ADDRESS3DOWNTO2_shadow <= EX_JUMP_ADDRESS( 3 DOWNTO 2 );
V_E_ALUCIN_shadow <= V.E.ALUCIN;
V_D_PC3DOWNTO2_shadow <= V.D.PC( 3 DOWNTO 2 );
V_A_CTRL_PV_shadow <= V.A.CTRL.PV;
V_E_CTRL_shadow <= V.E.CTRL;
V_M_CTRL_shadow <= V.M.CTRL;
V_M_RESULT1DOWNTO0_shadow <= V.M.RESULT ( 1 DOWNTO 0 );
EX_SHCNT_shadow <= EX_SHCNT;
V_M_DCI_SIZE_shadow <= V.M.DCI.SIZE;
V_X_CTRL_ANNUL_shadow <= V.X.CTRL.ANNUL;
V_X_MEXC_shadow <= V.X.MEXC;
TBUFCNTX_shadow <= TBUFCNTX;
V_A_CTRL_WY_shadow <= V.A.CTRL.WY;
NPC_shadow <= NPC;
V_M_CTRL_TT3DOWNTO0_shadow <= V.M.CTRL.TT( 3 DOWNTO 0 );
V_A_MULSTART_shadow <= V.A.MULSTART;
XC_VECTT3DOWNTO0_shadow <= XC_VECTT( 3 DOWNTO 0 );
V_E_CTRL_TT_shadow <= V.E.CTRL.TT;
DSIGN_shadow <= DSIGN;
V_E_CTRL_ANNUL_shadow <= V.E.CTRL.ANNUL;
EX_JUMP_ADDRESS_shadow <= EX_JUMP_ADDRESS;
V_A_CTRL_PC31DOWNTO12_shadow <= V.A.CTRL.PC( 31 DOWNTO 12 );
V_A_RFE1_shadow <= V.A.RFE1;
V_W_WA_shadow <= V.W.WA;
V_X_ANNUL_ALL_shadow <= V.X.ANNUL_ALL;
EX_YMSB_shadow <= EX_YMSB;
EX_ADD_RES_shadow <= EX_ADD_RES;
VIR_ADDR_shadow <= VIR.ADDR;
EX_JUMP_ADDRESS31DOWNTO12_shadow <= EX_JUMP_ADDRESS( 31 DOWNTO 12 );
V_W_S_CWP_shadow <= V.W.S.CWP;
V_D_INST0_shadow <= V.D.INST ( 0 );
V_A_CTRL_ANNUL_shadow <= V.A.CTRL.ANNUL;
V_X_DATA1_shadow <= V.X.DATA ( 1 );
VP_PWD_shadow <= VP.PWD;
V_M_CTRL_RD6DOWNTO0_shadow <= V.M.CTRL.RD( 6 DOWNTO 0 );
V_X_DATA00_shadow <= V.X.DATA ( 0 )( 0 );
V_M_CTRL_RETT_shadow <= V.M.CTRL.RETT;
V_X_CTRL_RETT_shadow <= V.X.CTRL.RETT;
V_X_CTRL_PC31DOWNTO12_shadow <= V.X.CTRL.PC( 31 DOWNTO 12 );
V_W_S_PS_shadow <= V.W.S.PS;
V_X_CTRL_TT_shadow <= V.X.CTRL.TT;
V_D_STEP_shadow <= V.D.STEP;
V_X_CTRL_WICC_shadow <= V.X.CTRL.WICC;
VIR_ADDR31DOWNTO2_shadow <= VIR.ADDR( 31 DOWNTO 2 );
V_M_CTRL_RD7DOWNTO0_shadow <= V.M.CTRL.RD ( 7 DOWNTO 0 );
V_X_RESULT_shadow <= V.X.RESULT;
V_D_CNT_shadow <= V.D.CNT;
XC_VECTT_shadow <= XC_VECTT;
EX_ADD_RES32DOWNTO3_shadow <= EX_ADD_RES ( 32 DOWNTO 3 );
V_W_S_EF_shadow <= V.W.S.EF;
V_A_CTRL_PC31DOWNTO2_shadow <= V.A.CTRL.PC( 31 DOWNTO 2 );
V_X_DATA04DOWNTO0_shadow <= V.X.DATA ( 0 )( 4 DOWNTO 0 );
V_X_DCI_SIGNED_shadow <= V.X.DCI.SIGNED;
V_M_NALIGN_shadow <= V.M.NALIGN;
XC_WREG_shadow <= XC_WREG;
V_A_RFA2_shadow <= V.A.RFA2;
V_E_CTRL_PC31DOWNTO12_shadow <= V.E.CTRL.PC( 31 DOWNTO 12 );
EX_ADD_RES32DOWNTO332DOWNTO13_shadow <= EX_ADD_RES ( 32 DOWNTO 3 )( 32 DOWNTO 13 );
EX_OP231_shadow <= EX_OP2( 31 );
XC_TRAP_ADDRESS31DOWNTO4_shadow <= XC_TRAP_ADDRESS( 31 DOWNTO 4 );
V_X_ICC_shadow <= V.X.ICC;
V_A_SU_shadow <= V.A.SU;
V_E_OP2_shadow <= V.E.OP2;
EX_FORCE_A2_shadow <= EX_FORCE_A2;
V_E_CTRL_PC31DOWNTO2_shadow <= V.E.CTRL.PC( 31 DOWNTO 2 );
V_E_CTRL_PC31DOWNTO4_shadow <= V.E.CTRL.PC( 31 DOWNTO 4 );
V_E_OP131_shadow <= V.E.OP1( 31 );
V_X_DCI_shadow <= V.X.DCI;
V_E_CTRL_WICC_shadow <= V.E.CTRL.WICC;
EX_OP13_shadow <= EX_OP1( 3 );
V_F_PC31DOWNTO12_shadow <= V.F.PC( 31 DOWNTO 12 );
V_E_CTRL_INST_shadow <= V.E.CTRL.INST;
V_E_CTRL_LD_shadow <= V.E.CTRL.LD;
V_M_SU_shadow <= V.M.SU;
V_E_SARI_shadow <= V.E.SARI;
V_E_ET_shadow <= V.E.ET;
V_M_CTRL_PV_shadow <= V.M.CTRL.PV;
VDSU_CRDY2_shadow <= VDSU.CRDY ( 2 );
MUL_OP2_shadow <= MUL_OP2;
XC_EXCEPTION_shadow <= XC_EXCEPTION;
V_E_OP1_shadow <= V.E.OP1;
VP_ERROR_shadow <= VP.ERROR;
V_M_DCI_SIGNED_shadow <= V.M.DCI.SIGNED;
V_D_PC31DOWNTO12_shadow <= V.D.PC( 31 DOWNTO 12 );
MUL_OP231_shadow <= MUL_OP2 ( 31 );
XC_TRAP_ADDRESS31DOWNTO2_shadow <= XC_TRAP_ADDRESS( 31 DOWNTO 2 );
V_M_CTRL_PC3DOWNTO2_shadow <= V.M.CTRL.PC( 3 DOWNTO 2 );
V_M_DCI_shadow <= V.M.DCI;
EX_OP23_shadow <= EX_OP2( 3 );
V_X_CTRL_RD6DOWNTO0_shadow <= V.X.CTRL.RD( 6 DOWNTO 0 );
V_X_CTRL_TRAP_shadow <= V.X.CTRL.TRAP;
V_A_DIVSTART_shadow <= V.A.DIVSTART;
V_X_RESULT6DOWNTO03DOWNTO0_shadow <= V.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 );
VDSU_TT_shadow <= VDSU.TT;
EX_ADD_RES32DOWNTO332DOWNTO5_shadow <= EX_ADD_RES ( 32 DOWNTO 3 )( 32 DOWNTO 5 );
V_X_CTRL_CNT_shadow <= V.X.CTRL.CNT;
V_E_YMSB_shadow <= V.E.YMSB;
EX_ADD_RES32DOWNTO330DOWNTO11_shadow <= EX_ADD_RES ( 32 DOWNTO 3 )( 30 DOWNTO 11 );
V_A_RFE2_shadow <= V.A.RFE2;
V_E_OP13_shadow <= V.E.OP1( 3 );
V_A_CWP_shadow <= V.A.CWP;
ME_SIZE_shadow <= ME_SIZE;
V_X_MAC_shadow <= V.X.MAC;
V_M_CTRL_INST_shadow <= V.M.CTRL.INST;
VIR_ADDR31DOWNTO4_shadow <= VIR.ADDR( 31 DOWNTO 4 );
V_A_CTRL_INST20_shadow <= V.A.CTRL.INST( 20 );
DE_REN2_shadow <= DE_REN2;
V_E_CTRL_PV_shadow <= V.E.CTRL.PV;
V_E_MAC_shadow <= V.E.MAC;
V_X_CTRL_TT3DOWNTO0_shadow <= V.X.CTRL.TT( 3 DOWNTO 0 );
EX_ADD_RES3_shadow <= EX_ADD_RES ( 3 );
V_X_CTRL_INST_shadow <= V.X.CTRL.INST;
V_M_CTRL_PC31DOWNTO2_shadow <= V.M.CTRL.PC( 31 DOWNTO 2 );
V_W_S_ET_shadow <= V.W.S.ET;
V_M_CTRL_CNT_shadow <= V.M.CTRL.CNT;
V_M_CTRL_ANNUL_shadow <= V.M.CTRL.ANNUL;
DE_INST19_shadow <= DE_INST( 19 );
XC_HALT_shadow <= XC_HALT;
V_E_OP231_shadow <= V.E.OP2( 31 );
V_A_CTRL_PC3DOWNTO2_shadow <= V.A.CTRL.PC( 3 DOWNTO 2 );
VIR_ADDR31DOWNTO12_shadow <= VIR.ADDR( 31 DOWNTO 12 );
V_M_CTRL_WICC_shadow <= V.M.CTRL.WICC;
V_M_CTRL_WREG_shadow <= V.M.CTRL.WREG;
V_W_S_S_shadow <= V.W.S.S;
V_F_PC31DOWNTO2_shadow <= V.F.PC( 31 DOWNTO 2 );
V_E_CWP_shadow <= V.E.CWP;
V_A_STEP_shadow <= V.A.STEP;
V_A_CTRL_TT3DOWNTO0_shadow <= V.A.CTRL.TT( 3 DOWNTO 0 );
V_A_CTRL_TRAP_shadow <= V.A.CTRL.TRAP;
NPC31DOWNTO2_shadow <= NPC ( 31 DOWNTO 2 );
V_M_CTRL_TRAP_shadow <= V.M.CTRL.TRAP;
V_D_PC31DOWNTO4_shadow <= V.D.PC( 31 DOWNTO 4 );
V_X_INTACK_shadow <= V.X.INTACK;
SIDLE_shadow <= SIDLE;
V_A_CTRL_RETT_shadow <= V.A.CTRL.RETT;
V_X_DATA03_shadow <= V.X.DATA ( 0 )( 3 );
V_A_CTRL_INST19_shadow <= V.A.CTRL.INST( 19 );
V_W_S_SVT_shadow <= V.W.S.SVT;
V_A_CTRL_PC31DOWNTO4_shadow <= V.A.CTRL.PC( 31 DOWNTO 4 );
V_X_LADDR_shadow <= V.X.LADDR;
V_W_S_DWT_shadow <= V.W.S.DWT;
EX_JUMP_ADDRESS31DOWNTO2_shadow <= EX_JUMP_ADDRESS( 31 DOWNTO 2 );
V_W_S_TBA_shadow <= V.W.S.TBA;
XC_WADDR6DOWNTO0_shadow <= XC_WADDR ( 6 DOWNTO 0 );
V_M_MUL_shadow <= V.M.MUL;
V_E_SU_shadow <= V.E.SU;
V_M_Y31_shadow <= V.M.Y ( 31 );
V_E_OP23_shadow <= V.E.OP2( 3 );
V_M_CTRL_PC31DOWNTO4_shadow <= V.M.CTRL.PC( 31 DOWNTO 4 );
DE_RADDR17DOWNTO0_shadow <= DE_RADDR1 ( 7 DOWNTO 0 );
V_X_CTRL_PC31DOWNTO2_shadow <= V.X.CTRL.PC( 31 DOWNTO 2 );
V_E_CTRL_TRAP_shadow <= V.E.CTRL.TRAP;
V_X_DEBUG_shadow <= V.X.DEBUG;
V_M_DCI_LOCK_shadow <= V.M.DCI.LOCK;
V_X_CTRL_PC3DOWNTO2_shadow <= V.X.CTRL.PC( 3 DOWNTO 2 );
V_X_CTRL_WREG_shadow <= V.X.CTRL.WREG;
V_E_CTRL_INST24_shadow <= V.E.CTRL.INST( 24 );
V_D_MEXC_shadow <= V.D.MEXC;
V_W_RESULT_shadow <= V.W.RESULT;
VFPI_DBG_ENABLE_shadow <= VFPI.DBG.ENABLE;
EX_OP131_shadow <= EX_OP1 ( 31 );
V_D_INST1_shadow <= V.D.INST ( 1 );
V_W_EXCEPT_shadow <= V.W.EXCEPT;
V_E_CTRL_TT3DOWNTO0_shadow <= V.E.CTRL.TT( 3 DOWNTO 0 );
ME_LADDR_shadow <= ME_LADDR;
V_X_CTRL_PC31DOWNTO4_shadow <= V.X.CTRL.PC( 31 DOWNTO 4 );
V_E_CTRL_RETT_shadow <= V.E.CTRL.RETT;
XC_WADDR7DOWNTO0_shadow <= XC_WADDR ( 7 DOWNTO 0 );
V_X_CTRL_PV_shadow <= V.X.CTRL.PV;
V_E_CTRL_RD6DOWNTO0_shadow <= V.E.CTRL.RD( 6 DOWNTO 0 );
V_M_MAC_shadow <= V.M.MAC;
V_D_SET_shadow <= V.D.SET;
VIR_ADDR3DOWNTO2_shadow <= VIR.ADDR( 3 DOWNTO 2 );
V_D_CWP_shadow <= V.D.CWP;
DE_INST20_shadow <= DE_INST( 20 );
V_D_ANNUL_shadow <= V.D.ANNUL;
EX_OP2_shadow <= EX_OP2;
EX_SARI_shadow <= EX_SARI;
V_D_PC31DOWNTO2_shadow <= V.D.PC( 31 DOWNTO 2 );
V_X_DCI_SIZE_shadow <= V.X.DCI.SIZE;
V_M_Y_shadow <= V.M.Y;
V_X_CTRL_PC_shadow <= V.X.CTRL.PC;
V_X_SET_shadow <= V.X.SET;
V_A_CTRL_PC_shadow <= V.A.CTRL.PC;
V_A_JMPL_shadow <= V.A.JMPL;
V_E_CTRL_PC_shadow <= V.E.CTRL.PC;
V_E_CTRL_INST20_shadow <= V.E.CTRL.INST( 20 );
V_E_CTRL_WREG_shadow <= V.E.CTRL.WREG;
V_A_CTRL_WREG_shadow <= V.A.CTRL.WREG;
V_A_CTRL_shadow <= V.A.CTRL;
V_A_CTRL_RD6DOWNTO0_shadow <= V.A.CTRL.RD( 6 DOWNTO 0 );
V_X_DATA0_shadow <= V.X.DATA ( 0 );
V_E_CTRL_INST19_shadow <= V.E.CTRL.INST( 19 );
ME_SIGNED_shadow <= ME_SIGNED;
V_W_WREG_shadow <= V.W.WREG;
V_D_PC_shadow <= V.D.PC;
VFPI_D_ANNUL_shadow <= VFPI.D.ANNUL;
DE_RADDR27DOWNTO0_shadow <= DE_RADDR2 ( 7 DOWNTO 0 );
V_E_CTRL_CNT_shadow <= V.E.CTRL.CNT;
V_F_PC_shadow <= V.F.PC;
V_X_DATA031_shadow <= V.X.DATA ( 0 )( 31 );
V_M_CTRL_PC31DOWNTO12_shadow <= V.M.CTRL.PC( 31 DOWNTO 12 );
V_X_CTRL_RD7DOWNTO0_shadow <= V.X.CTRL.RD ( 7 DOWNTO 0 );
V_M_CTRL_TT_shadow <= V.M.CTRL.TT;
V_X_CTRL_shadow <= V.X.CTRL;
V_A_CTRL_INST24_shadow <= V.A.CTRL.INST( 24 );
XC_TRAP_ADDRESS3DOWNTO2_shadow <= XC_TRAP_ADDRESS( 3 DOWNTO 2 );
V_X_NERROR_shadow <= V.X.NERROR;
V_F_PC31DOWNTO4_shadow <= V.F.PC( 31 DOWNTO 4 );
V_W_S_TT3DOWNTO0_shadow <= V.W.S.TT( 3 DOWNTO 0 );
EX_JUMP_ADDRESS31DOWNTO4_shadow <= EX_JUMP_ADDRESS( 31 DOWNTO 4 );
EX_ADD_RES32DOWNTO332DOWNTO3_shadow <= EX_ADD_RES ( 32 DOWNTO 3 )( 32 DOWNTO 3 );
V_F_BRANCH_shadow <= V.F.BRANCH;
V_A_CTRL_WICC_shadow <= V.A.CTRL.WICC;
V_A_CTRL_LD_shadow <= V.A.CTRL.LD;
V_A_CTRL_TT_shadow <= V.A.CTRL.TT;
V_M_CTRL_LD_shadow <= V.M.CTRL.LD;
V_E_SHCNT_shadow <= V.E.SHCNT;
XC_TRAP_ADDRESS31DOWNTO12_shadow <= XC_TRAP_ADDRESS( 31 DOWNTO 12 );
V_A_CTRL_INST_shadow <= V.A.CTRL.INST;
V_A_CTRL_RD7DOWNTO0_shadow <= V.A.CTRL.RD ( 7 DOWNTO 0 );
VIR_PWD_shadow <= VIR.PWD;
XC_RESULT_shadow <= XC_RESULT;
V_A_RFA1_shadow <= V.A.RFA1;
V_E_JMPL_shadow <= V.E.JMPL;
V_E_CTRL_RD7DOWNTO0_shadow <= V.E.CTRL.RD ( 7 DOWNTO 0 );
ME_ICC_shadow <= ME_ICC;
DE_INST24_shadow <= DE_INST( 24 );
XC_TRAP_shadow <= XC_TRAP;
VDSU_TBUFCNT_shadow <= VDSU.TBUFCNT;
XC_TRAP_ADDRESS_shadow <= XC_TRAP_ADDRESS;
end process;
dfp_delay : process(clk) begin
if(clk'event and clk = '1')then
ADDRESSTOCACHE_intermed_1 <= ADDRESSTOCACHE;
ADDRESSTOCACHE_intermed_2 <= ADDRESSTOCACHE_intermed_1;
EX_EDATA2_shadow_intermed_1 <= EX_EDATA2_shadow;
EX_EDATA2_shadow_intermed_2 <= EX_EDATA2_shadow_intermed_1;
EX_EDATA2_shadow_intermed_3 <= EX_EDATA2_shadow_intermed_2;
EX_EDATA2_shadow_intermed_4 <= EX_EDATA2_shadow_intermed_3;
EX_EDATA2_shadow_intermed_5 <= EX_EDATA2_shadow_intermed_4;
V_M_RESULT_shadow_intermed_1 <= V_M_RESULT_shadow;
V_M_RESULT_shadow_intermed_2 <= V_M_RESULT_shadow_intermed_1;
V_M_RESULT_shadow_intermed_3 <= V_M_RESULT_shadow_intermed_2;
V_M_RESULT_shadow_intermed_4 <= V_M_RESULT_shadow_intermed_3;
DATATOCACHE_intermed_1 <= DATATOCACHE;
DATATOCACHE_intermed_2 <= DATATOCACHE_intermed_1;
DATATOCACHE_intermed_3 <= DATATOCACHE_intermed_2;
DATATOCACHE_intermed_4 <= DATATOCACHE_intermed_3;
DCI_EDATA_intermed_1 <= DCI.EDATA;
DCI_EDATA_intermed_2 <= DCI_EDATA_intermed_1;
DCI_EDATA_intermed_3 <= DCI_EDATA_intermed_2;
DCI_EDATA_intermed_4 <= DCI_EDATA_intermed_3;
DCI_EDATA_intermed_5 <= DCI_EDATA_intermed_4;
DCI_MADDRESS_intermed_1 <= DCI.MADDRESS;
DCI_MADDRESS_intermed_2 <= DCI_MADDRESS_intermed_1;
DCI_MADDRESS_intermed_3 <= DCI_MADDRESS_intermed_2;
KNOCKADDRESS_intermed_1 <= KNOCKADDRESS;
RIN_M_RESULT_intermed_1 <= RIN.M.RESULT;
RIN_M_RESULT_intermed_2 <= RIN_M_RESULT_intermed_1;
RIN_M_RESULT_intermed_3 <= RIN_M_RESULT_intermed_2;
RIN_M_RESULT_intermed_4 <= RIN_M_RESULT_intermed_3;
R_M_RESULT_intermed_1 <= R.M.RESULT;
R_M_RESULT_intermed_2 <= R_M_RESULT_intermed_1;
R_M_RESULT_intermed_3 <= R_M_RESULT_intermed_2;
TARGETADDRESS_intermed_1 <= TARGETADDRESS;
TARGETADDRESS_intermed_2 <= TARGETADDRESS_intermed_1;
TARGETADDRESS_intermed_3 <= TARGETADDRESS_intermed_2;
V_A_SU_shadow_intermed_1 <= V_A_SU_shadow;
V_A_SU_shadow_intermed_2 <= V_A_SU_shadow_intermed_1;
V_E_SU_shadow_intermed_1 <= V_E_SU_shadow;
R_A_SU_intermed_1 <= R.A.SU;
RIN_A_SU_intermed_1 <= RIN.A.SU;
RIN_A_SU_intermed_2 <= RIN_A_SU_intermed_1;
RIN_E_SU_intermed_1 <= RIN.E.SU;
EX_EDATA2_shadow_intermed_1 <= EX_EDATA2_shadow;
EX_EDATA2_shadow_intermed_2 <= EX_EDATA2_shadow_intermed_1;
V_M_RESULT_shadow_intermed_1 <= V_M_RESULT_shadow;
DATATOCACHE_intermed_1 <= DATATOCACHE;
DCI_EDATA_intermed_1 <= DCI.EDATA;
DCI_EDATA_intermed_2 <= DCI_EDATA_intermed_1;
RIN_M_RESULT_intermed_1 <= RIN.M.RESULT;
V_A_SU_shadow_intermed_1 <= V_A_SU_shadow;
V_A_SU_shadow_intermed_2 <= V_A_SU_shadow_intermed_1;
V_A_SU_shadow_intermed_3 <= V_A_SU_shadow_intermed_2;
V_E_SU_shadow_intermed_1 <= V_E_SU_shadow;
V_E_SU_shadow_intermed_2 <= V_E_SU_shadow_intermed_1;
V_M_SU_shadow_intermed_1 <= V_M_SU_shadow;
R_A_SU_intermed_1 <= R.A.SU;
R_A_SU_intermed_2 <= R_A_SU_intermed_1;
R_E_SU_intermed_1 <= R.E.SU;
RIN_A_SU_intermed_1 <= RIN.A.SU;
RIN_A_SU_intermed_2 <= RIN_A_SU_intermed_1;
RIN_A_SU_intermed_3 <= RIN_A_SU_intermed_2;
RIN_E_SU_intermed_1 <= RIN.E.SU;
RIN_E_SU_intermed_2 <= RIN_E_SU_intermed_1;
RIN_M_SU_intermed_1 <= RIN.M.SU;
ADDRESSTOCACHE_intermed_1 <= ADDRESSTOCACHE;
EX_EDATA2_shadow_intermed_1 <= EX_EDATA2_shadow;
EX_EDATA2_shadow_intermed_2 <= EX_EDATA2_shadow_intermed_1;
EX_EDATA2_shadow_intermed_3 <= EX_EDATA2_shadow_intermed_2;
EX_EDATA2_shadow_intermed_4 <= EX_EDATA2_shadow_intermed_3;
V_M_RESULT_shadow_intermed_1 <= V_M_RESULT_shadow;
V_M_RESULT_shadow_intermed_2 <= V_M_RESULT_shadow_intermed_1;
V_M_RESULT_shadow_intermed_3 <= V_M_RESULT_shadow_intermed_2;
DATATOCACHE_intermed_1 <= DATATOCACHE;
DATATOCACHE_intermed_2 <= DATATOCACHE_intermed_1;
DATATOCACHE_intermed_3 <= DATATOCACHE_intermed_2;
DCI_EDATA_intermed_1 <= DCI.EDATA;
DCI_EDATA_intermed_2 <= DCI_EDATA_intermed_1;
DCI_EDATA_intermed_3 <= DCI_EDATA_intermed_2;
DCI_EDATA_intermed_4 <= DCI_EDATA_intermed_3;
DCI_MADDRESS_intermed_1 <= DCI.MADDRESS;
DCI_MADDRESS_intermed_2 <= DCI_MADDRESS_intermed_1;
RIN_M_RESULT_intermed_1 <= RIN.M.RESULT;
RIN_M_RESULT_intermed_2 <= RIN_M_RESULT_intermed_1;
RIN_M_RESULT_intermed_3 <= RIN_M_RESULT_intermed_2;
R_M_RESULT_intermed_1 <= R.M.RESULT;
R_M_RESULT_intermed_2 <= R_M_RESULT_intermed_1;
TARGETADDRESS_intermed_1 <= TARGETADDRESS;
TARGETADDRESS_intermed_2 <= TARGETADDRESS_intermed_1;
EX_EDATA2_shadow_intermed_1 <= EX_EDATA2_shadow;
EX_EDATA2_shadow_intermed_2 <= EX_EDATA2_shadow_intermed_1;
DATATOCACHE_intermed_1 <= DATATOCACHE;
DCI_EDATA_intermed_1 <= DCI.EDATA;
DCI_EDATA_intermed_2 <= DCI_EDATA_intermed_1;
RPIN_ERROR_intermed_1 <= RPIN.ERROR;
VP_ERROR_shadow_intermed_1 <= VP_ERROR_shadow;
V_W_S_S_shadow_intermed_1 <= V_W_S_S_shadow;
RIN_W_S_S_intermed_1 <= RIN.W.S.S;
V_W_S_S_shadow_intermed_1 <= V_W_S_S_shadow;
V_W_S_S_shadow_intermed_2 <= V_W_S_S_shadow_intermed_1;
V_W_S_PS_shadow_intermed_1 <= V_W_S_PS_shadow;
RIN_W_S_PS_intermed_1 <= RIN.W.S.PS;
R_W_S_S_intermed_1 <= R.W.S.S;
RIN_W_S_S_intermed_1 <= RIN.W.S.S;
RIN_W_S_S_intermed_2 <= RIN_W_S_S_intermed_1;
R_X_RESULT6DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 );
R_X_RESULT6DOWNTO0_intermed_2 <= R_X_RESULT6DOWNTO0_intermed_1;
V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow;
V_X_RESULT6DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO0_shadow_intermed_1;
V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow;
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 );
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 );
RIN_X_RESULT6DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO0_intermed_1;
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
V_X_DATA0_shadow_intermed_2 <= V_X_DATA0_shadow_intermed_1;
R_X_DATA0_intermed_1 <= R.X.DATA( 0 );
R_X_DATA0_intermed_2 <= R_X_DATA0_intermed_1;
DCO_DATA0_intermed_1 <= DCO.DATA ( 0 );
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA ( 0 );
RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 );
RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC ( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
R_X_CTRL_PC31DOWNTO2_intermed_2 <= R_X_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC ( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
V_D_PC31DOWNTO2_shadow_intermed_6 <= V_D_PC31DOWNTO2_shadow_intermed_5;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_D_PC31DOWNTO2_intermed_6 <= RIN_D_PC31DOWNTO2_intermed_5;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC ( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC ( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC ( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_D_PC31DOWNTO2_intermed_5 <= R_D_PC31DOWNTO2_intermed_4;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC ( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
V_X_ANNUL_ALL_shadow_intermed_2 <= V_X_ANNUL_ALL_shadow_intermed_1;
V_X_ANNUL_ALL_shadow_intermed_3 <= V_X_ANNUL_ALL_shadow_intermed_2;
V_X_ANNUL_ALL_shadow_intermed_4 <= V_X_ANNUL_ALL_shadow_intermed_3;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2;
RIN_A_CTRL_ANNUL_intermed_4 <= RIN_A_CTRL_ANNUL_intermed_3;
RIN_A_CTRL_ANNUL_intermed_5 <= RIN_A_CTRL_ANNUL_intermed_4;
R_M_CTRL_WREG_intermed_1 <= R.M.CTRL.WREG;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1;
R_A_CTRL_ANNUL_intermed_3 <= R_A_CTRL_ANNUL_intermed_2;
R_A_CTRL_ANNUL_intermed_4 <= R_A_CTRL_ANNUL_intermed_3;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
RIN_X_ANNUL_ALL_intermed_3 <= RIN_X_ANNUL_ALL_intermed_2;
RIN_X_ANNUL_ALL_intermed_4 <= RIN_X_ANNUL_ALL_intermed_3;
RIN_X_ANNUL_ALL_intermed_5 <= RIN_X_ANNUL_ALL_intermed_4;
V_M_CTRL_WREG_shadow_intermed_1 <= V_M_CTRL_WREG_shadow;
V_M_CTRL_WREG_shadow_intermed_2 <= V_M_CTRL_WREG_shadow_intermed_1;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
R_X_ANNUL_ALL_intermed_2 <= R_X_ANNUL_ALL_intermed_1;
R_X_ANNUL_ALL_intermed_3 <= R_X_ANNUL_ALL_intermed_2;
R_X_ANNUL_ALL_intermed_4 <= R_X_ANNUL_ALL_intermed_3;
V_X_CTRL_WREG_shadow_intermed_1 <= V_X_CTRL_WREG_shadow;
R_E_CTRL_WREG_intermed_1 <= R.E.CTRL.WREG;
R_E_CTRL_WREG_intermed_2 <= R_E_CTRL_WREG_intermed_1;
RIN_X_CTRL_WREG_intermed_1 <= RIN.X.CTRL.WREG;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_3 <= V_A_CTRL_ANNUL_shadow_intermed_2;
V_A_CTRL_ANNUL_shadow_intermed_4 <= V_A_CTRL_ANNUL_shadow_intermed_3;
RIN_E_CTRL_WREG_intermed_1 <= RIN.E.CTRL.WREG;
RIN_E_CTRL_WREG_intermed_2 <= RIN_E_CTRL_WREG_intermed_1;
RIN_E_CTRL_WREG_intermed_3 <= RIN_E_CTRL_WREG_intermed_2;
RIN_M_CTRL_WREG_intermed_1 <= RIN.M.CTRL.WREG;
RIN_M_CTRL_WREG_intermed_2 <= RIN_M_CTRL_WREG_intermed_1;
V_E_CTRL_WREG_shadow_intermed_1 <= V_E_CTRL_WREG_shadow;
V_E_CTRL_WREG_shadow_intermed_2 <= V_E_CTRL_WREG_shadow_intermed_1;
V_E_CTRL_WREG_shadow_intermed_3 <= V_E_CTRL_WREG_shadow_intermed_2;
RIN_A_CTRL_WREG_intermed_1 <= RIN.A.CTRL.WREG;
RIN_A_CTRL_WREG_intermed_2 <= RIN_A_CTRL_WREG_intermed_1;
RIN_A_CTRL_WREG_intermed_3 <= RIN_A_CTRL_WREG_intermed_2;
RIN_A_CTRL_WREG_intermed_4 <= RIN_A_CTRL_WREG_intermed_3;
V_A_CTRL_WREG_shadow_intermed_1 <= V_A_CTRL_WREG_shadow;
V_A_CTRL_WREG_shadow_intermed_2 <= V_A_CTRL_WREG_shadow_intermed_1;
V_A_CTRL_WREG_shadow_intermed_3 <= V_A_CTRL_WREG_shadow_intermed_2;
V_A_CTRL_WREG_shadow_intermed_4 <= V_A_CTRL_WREG_shadow_intermed_3;
R_A_CTRL_WREG_intermed_1 <= R.A.CTRL.WREG;
R_A_CTRL_WREG_intermed_2 <= R_A_CTRL_WREG_intermed_1;
R_A_CTRL_WREG_intermed_3 <= R_A_CTRL_WREG_intermed_2;
RIN_X_INTACK_intermed_1 <= RIN.X.INTACK;
V_X_INTACK_shadow_intermed_1 <= V_X_INTACK_shadow;
V_X_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_X_CTRL_TT3DOWNTO0_shadow;
V_X_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_X_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_X_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_X_CTRL_TT3DOWNTO0_shadow_intermed_2;
R_M_CTRL_TT3DOWNTO0_intermed_1 <= R.M.CTRL.TT( 3 DOWNTO 0 );
R_M_CTRL_TT3DOWNTO0_intermed_2 <= R_M_CTRL_TT3DOWNTO0_intermed_1;
R_M_CTRL_TT3DOWNTO0_intermed_3 <= R_M_CTRL_TT3DOWNTO0_intermed_2;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_M_CTRL_TT3DOWNTO0_shadow;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_M_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_M_CTRL_TT3DOWNTO0_shadow_intermed_2;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_4 <= V_M_CTRL_TT3DOWNTO0_shadow_intermed_3;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_3 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_4 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_3;
R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
R_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= R_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
R_X_RESULT6DOWNTO03DOWNTO0_intermed_3 <= R_X_RESULT6DOWNTO03DOWNTO0_intermed_2;
R_A_CTRL_TT3DOWNTO0_intermed_1 <= R.A.CTRL.TT( 3 DOWNTO 0 );
R_A_CTRL_TT3DOWNTO0_intermed_2 <= R_A_CTRL_TT3DOWNTO0_intermed_1;
R_A_CTRL_TT3DOWNTO0_intermed_3 <= R_A_CTRL_TT3DOWNTO0_intermed_2;
R_A_CTRL_TT3DOWNTO0_intermed_4 <= R_A_CTRL_TT3DOWNTO0_intermed_3;
R_A_CTRL_TT3DOWNTO0_intermed_5 <= R_A_CTRL_TT3DOWNTO0_intermed_4;
RIN_A_CTRL_TT3DOWNTO0_intermed_1 <= RIN.A.CTRL.TT( 3 DOWNTO 0 );
RIN_A_CTRL_TT3DOWNTO0_intermed_2 <= RIN_A_CTRL_TT3DOWNTO0_intermed_1;
RIN_A_CTRL_TT3DOWNTO0_intermed_3 <= RIN_A_CTRL_TT3DOWNTO0_intermed_2;
RIN_A_CTRL_TT3DOWNTO0_intermed_4 <= RIN_A_CTRL_TT3DOWNTO0_intermed_3;
RIN_A_CTRL_TT3DOWNTO0_intermed_5 <= RIN_A_CTRL_TT3DOWNTO0_intermed_4;
RIN_A_CTRL_TT3DOWNTO0_intermed_6 <= RIN_A_CTRL_TT3DOWNTO0_intermed_5;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_3 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_4 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_3;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_A_CTRL_TT3DOWNTO0_shadow;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_2;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_4 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_3;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_5 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_4;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_6 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_5;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_3 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2;
R_W_S_TT3DOWNTO0_intermed_1 <= R.W.S.TT( 3 DOWNTO 0 );
R_W_S_TT3DOWNTO0_intermed_2 <= R_W_S_TT3DOWNTO0_intermed_1;
R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 );
R_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= R_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
R_E_CTRL_TT3DOWNTO0_intermed_1 <= R.E.CTRL.TT( 3 DOWNTO 0 );
R_E_CTRL_TT3DOWNTO0_intermed_2 <= R_E_CTRL_TT3DOWNTO0_intermed_1;
R_E_CTRL_TT3DOWNTO0_intermed_3 <= R_E_CTRL_TT3DOWNTO0_intermed_2;
R_E_CTRL_TT3DOWNTO0_intermed_4 <= R_E_CTRL_TT3DOWNTO0_intermed_3;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_3 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2;
RIN_W_S_TT3DOWNTO0_intermed_1 <= RIN.W.S.TT( 3 DOWNTO 0 );
RIN_W_S_TT3DOWNTO0_intermed_2 <= RIN_W_S_TT3DOWNTO0_intermed_1;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_E_CTRL_TT3DOWNTO0_shadow;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_2;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_4 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_3;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_5 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_4;
RIN_W_S_TT3DOWNTO0_intermed_1 <= RIN.W.S.TT ( 3 DOWNTO 0 );
RIN_M_CTRL_TT3DOWNTO0_intermed_1 <= RIN.M.CTRL.TT( 3 DOWNTO 0 );
RIN_M_CTRL_TT3DOWNTO0_intermed_2 <= RIN_M_CTRL_TT3DOWNTO0_intermed_1;
RIN_M_CTRL_TT3DOWNTO0_intermed_3 <= RIN_M_CTRL_TT3DOWNTO0_intermed_2;
RIN_M_CTRL_TT3DOWNTO0_intermed_4 <= RIN_M_CTRL_TT3DOWNTO0_intermed_3;
RIN_X_CTRL_TT3DOWNTO0_intermed_1 <= RIN.X.CTRL.TT( 3 DOWNTO 0 );
RIN_X_CTRL_TT3DOWNTO0_intermed_2 <= RIN_X_CTRL_TT3DOWNTO0_intermed_1;
RIN_X_CTRL_TT3DOWNTO0_intermed_3 <= RIN_X_CTRL_TT3DOWNTO0_intermed_2;
V_W_S_TT3DOWNTO0_shadow_intermed_1 <= V_W_S_TT3DOWNTO0_shadow;
V_W_S_TT3DOWNTO0_shadow_intermed_2 <= V_W_S_TT3DOWNTO0_shadow_intermed_1;
R_X_CTRL_TT3DOWNTO0_intermed_1 <= R.X.CTRL.TT( 3 DOWNTO 0 );
R_X_CTRL_TT3DOWNTO0_intermed_2 <= R_X_CTRL_TT3DOWNTO0_intermed_1;
RIN_E_CTRL_TT3DOWNTO0_intermed_1 <= RIN.E.CTRL.TT( 3 DOWNTO 0 );
RIN_E_CTRL_TT3DOWNTO0_intermed_2 <= RIN_E_CTRL_TT3DOWNTO0_intermed_1;
RIN_E_CTRL_TT3DOWNTO0_intermed_3 <= RIN_E_CTRL_TT3DOWNTO0_intermed_2;
RIN_E_CTRL_TT3DOWNTO0_intermed_4 <= RIN_E_CTRL_TT3DOWNTO0_intermed_3;
RIN_E_CTRL_TT3DOWNTO0_intermed_5 <= RIN_E_CTRL_TT3DOWNTO0_intermed_4;
V_W_S_TT3DOWNTO0_shadow_intermed_1 <= V_W_S_TT3DOWNTO0_shadow;
XC_VECTT3DOWNTO0_shadow_intermed_1 <= XC_VECTT3DOWNTO0_shadow;
XC_VECTT3DOWNTO0_shadow_intermed_2 <= XC_VECTT3DOWNTO0_shadow_intermed_1;
RIN_X_INTACK_intermed_1 <= RIN.X.INTACK;
V_X_INTACK_shadow_intermed_1 <= V_X_INTACK_shadow;
V_M_RESULT1DOWNTO0_shadow_intermed_1 <= V_M_RESULT1DOWNTO0_shadow;
V_M_RESULT1DOWNTO0_shadow_intermed_2 <= V_M_RESULT1DOWNTO0_shadow_intermed_1;
RIN_M_RESULT1DOWNTO0_intermed_1 <= RIN.M.RESULT ( 1 DOWNTO 0 );
RIN_M_RESULT1DOWNTO0_intermed_1 <= RIN.M.RESULT( 1 DOWNTO 0 );
RIN_M_RESULT1DOWNTO0_intermed_2 <= RIN_M_RESULT1DOWNTO0_intermed_1;
V_M_RESULT1DOWNTO0_shadow_intermed_1 <= V_M_RESULT1DOWNTO0_shadow;
R_M_RESULT1DOWNTO0_intermed_1 <= R.M.RESULT( 1 DOWNTO 0 );
R_M_RESULT1DOWNTO0_intermed_2 <= R_M_RESULT1DOWNTO0_intermed_1;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2;
RIN_E_CTRL_ANNUL_intermed_1 <= RIN.E.CTRL.ANNUL;
RIN_E_CTRL_ANNUL_intermed_2 <= RIN_E_CTRL_ANNUL_intermed_1;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1;
V_M_CTRL_ANNUL_shadow_intermed_1 <= V_M_CTRL_ANNUL_shadow;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
RIN_M_DCI_LOCK_intermed_1 <= RIN.M.DCI.LOCK;
V_E_CTRL_ANNUL_shadow_intermed_1 <= V_E_CTRL_ANNUL_shadow;
V_E_CTRL_ANNUL_shadow_intermed_2 <= V_E_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_3 <= V_A_CTRL_ANNUL_shadow_intermed_2;
RIN_M_CTRL_ANNUL_intermed_1 <= RIN.M.CTRL.ANNUL;
R_E_CTRL_ANNUL_intermed_1 <= R.E.CTRL.ANNUL;
V_M_DCI_LOCK_shadow_intermed_1 <= V_M_DCI_LOCK_shadow;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 ) ( 31 );
DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 );
DCO_DATA031_intermed_2 <= DCO_DATA031_intermed_1;
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
R_X_DATA031_intermed_2 <= R_X_DATA031_intermed_1;
R_X_DATA031_intermed_1 <= R.X.DATA ( 0 )( 31 );
R_X_DATA031_intermed_2 <= R_X_DATA031_intermed_1;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
DE_INST19_shadow_intermed_2 <= DE_INST19_shadow_intermed_1;
DE_INST19_shadow_intermed_3 <= DE_INST19_shadow_intermed_2;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_A_CTRL_INST19_shadow_intermed_3 <= V_A_CTRL_INST19_shadow_intermed_2;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_CTRL_INST19_shadow_intermed_2 <= V_E_CTRL_INST19_shadow_intermed_1;
R_E_CTRL_INST19_intermed_1 <= R.E.CTRL.INST( 19 );
R_E_CTRL_INST19_intermed_2 <= R_E_CTRL_INST19_intermed_1;
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
R_A_CTRL_INST19_intermed_2 <= R_A_CTRL_INST19_intermed_1;
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
RIN_A_CTRL_INST19_intermed_3 <= RIN_A_CTRL_INST19_intermed_2;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST ( 19 );
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST( 19 );
RIN_E_CTRL_INST19_intermed_2 <= RIN_E_CTRL_INST19_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
V_A_CTRL_INST20_shadow_intermed_2 <= V_A_CTRL_INST20_shadow_intermed_1;
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST ( 20 );
RIN_A_CTRL_INST20_intermed_2 <= RIN_A_CTRL_INST20_intermed_1;
RIN_E_CTRL_INST20_intermed_1 <= RIN.E.CTRL.INST ( 20 );
R_A_CTRL_INST20_intermed_1 <= R.A.CTRL.INST ( 20 );
R_E_CTRL_INST20_intermed_1 <= R.E.CTRL.INST( 20 );
R_E_CTRL_INST20_intermed_2 <= R_E_CTRL_INST20_intermed_1;
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST( 20 );
RIN_A_CTRL_INST20_intermed_2 <= RIN_A_CTRL_INST20_intermed_1;
RIN_A_CTRL_INST20_intermed_3 <= RIN_A_CTRL_INST20_intermed_2;
V_E_CTRL_INST20_shadow_intermed_1 <= V_E_CTRL_INST20_shadow;
V_E_CTRL_INST20_shadow_intermed_2 <= V_E_CTRL_INST20_shadow_intermed_1;
V_E_CTRL_INST20_shadow_intermed_1 <= V_E_CTRL_INST20_shadow;
DE_INST20_shadow_intermed_1 <= DE_INST20_shadow;
DE_INST20_shadow_intermed_2 <= DE_INST20_shadow_intermed_1;
DE_INST20_shadow_intermed_3 <= DE_INST20_shadow_intermed_2;
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
V_A_CTRL_INST20_shadow_intermed_2 <= V_A_CTRL_INST20_shadow_intermed_1;
V_A_CTRL_INST20_shadow_intermed_3 <= V_A_CTRL_INST20_shadow_intermed_2;
RIN_E_CTRL_INST20_intermed_1 <= RIN.E.CTRL.INST( 20 );
RIN_E_CTRL_INST20_intermed_2 <= RIN_E_CTRL_INST20_intermed_1;
R_A_CTRL_INST20_intermed_1 <= R.A.CTRL.INST( 20 );
R_A_CTRL_INST20_intermed_2 <= R_A_CTRL_INST20_intermed_1;
RIN_X_DATA00_intermed_1 <= RIN.X.DATA ( 0 )( 0 );
RIN_X_DATA00_intermed_2 <= RIN_X_DATA00_intermed_1;
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
DCO_DATA00_intermed_1 <= DCO.DATA ( 0 )( 0 );
-- DCO_DATA00_intermed_2 <= DCO_DATA00_intermed_1;
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
V_X_DATA00_shadow_intermed_2 <= V_X_DATA00_shadow_intermed_1;
RIN_X_DATA00_intermed_1 <= RIN.X.DATA ( 0 ) ( 0 );
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
V_X_DATA00_shadow_intermed_2 <= V_X_DATA00_shadow_intermed_1;
R_X_DATA00_intermed_1 <= R.X.DATA ( 0 )( 0 );
R_X_DATA00_intermed_2 <= R_X_DATA00_intermed_1;
RIN_X_DATA00_intermed_1 <= RIN.X.DATA( 0 )( 0 );
RIN_X_DATA00_intermed_2 <= RIN_X_DATA00_intermed_1;
R_X_DATA00_intermed_1 <= R.X.DATA( 0 )( 0 );
R_X_DATA00_intermed_2 <= R_X_DATA00_intermed_1;
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA ( 0 ) ( 4 DOWNTO 0 );
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
V_X_DATA04DOWNTO0_shadow_intermed_2 <= V_X_DATA04DOWNTO0_shadow_intermed_1;
R_X_DATA04DOWNTO0_intermed_1 <= R.X.DATA( 0 )( 4 DOWNTO 0 );
R_X_DATA04DOWNTO0_intermed_2 <= R_X_DATA04DOWNTO0_intermed_1;
R_X_DATA04DOWNTO0_intermed_1 <= R.X.DATA ( 0 )( 4 DOWNTO 0 );
R_X_DATA04DOWNTO0_intermed_2 <= R_X_DATA04DOWNTO0_intermed_1;
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
DCO_DATA04DOWNTO0_intermed_1 <= DCO.DATA ( 0 )( 4 DOWNTO 0 );
DCO_DATA04DOWNTO0_intermed_2 <= DCO_DATA04DOWNTO0_intermed_1;
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA ( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_2 <= RIN_X_DATA04DOWNTO0_intermed_1;
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_2 <= RIN_X_DATA04DOWNTO0_intermed_1;
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
V_X_DATA04DOWNTO0_shadow_intermed_2 <= V_X_DATA04DOWNTO0_shadow_intermed_1;
RIN_A_RFE1_intermed_1 <= RIN.A.RFE1;
V_A_RFE1_shadow_intermed_1 <= V_A_RFE1_shadow;
RIN_A_RFE2_intermed_1 <= RIN.A.RFE2;
V_A_RFE2_shadow_intermed_1 <= V_A_RFE2_shadow;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_3 <= R_M_CTRL_PC31DOWNTO2_intermed_2;
R_M_CTRL_PC31DOWNTO2_intermed_4 <= R_M_CTRL_PC31DOWNTO2_intermed_3;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_4 <= RIN_M_CTRL_PC31DOWNTO2_intermed_3;
RIN_M_CTRL_PC31DOWNTO2_intermed_5 <= RIN_M_CTRL_PC31DOWNTO2_intermed_4;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_4;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_6 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_5;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_6 <= RIN_A_CTRL_PC31DOWNTO2_intermed_5;
RIN_A_CTRL_PC31DOWNTO2_intermed_7 <= RIN_A_CTRL_PC31DOWNTO2_intermed_6;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
R_A_CTRL_PC31DOWNTO2_intermed_5 <= R_A_CTRL_PC31DOWNTO2_intermed_4;
R_A_CTRL_PC31DOWNTO2_intermed_6 <= R_A_CTRL_PC31DOWNTO2_intermed_5;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_4;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
R_X_CTRL_PC31DOWNTO2_intermed_2 <= R_X_CTRL_PC31DOWNTO2_intermed_1;
R_X_CTRL_PC31DOWNTO2_intermed_3 <= R_X_CTRL_PC31DOWNTO2_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
V_D_PC31DOWNTO2_shadow_intermed_6 <= V_D_PC31DOWNTO2_shadow_intermed_5;
V_D_PC31DOWNTO2_shadow_intermed_7 <= V_D_PC31DOWNTO2_shadow_intermed_6;
V_D_PC31DOWNTO2_shadow_intermed_8 <= V_D_PC31DOWNTO2_shadow_intermed_7;
XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO2_shadow;
XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_2 <= XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_D_PC31DOWNTO2_intermed_6 <= RIN_D_PC31DOWNTO2_intermed_5;
RIN_D_PC31DOWNTO2_intermed_7 <= RIN_D_PC31DOWNTO2_intermed_6;
RIN_D_PC31DOWNTO2_intermed_8 <= RIN_D_PC31DOWNTO2_intermed_7;
EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow;
EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_2 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1;
V_F_PC31DOWNTO2_shadow_intermed_1 <= V_F_PC31DOWNTO2_shadow;
V_F_PC31DOWNTO2_shadow_intermed_2 <= V_F_PC31DOWNTO2_shadow_intermed_1;
V_F_PC31DOWNTO2_shadow_intermed_1 <= V_F_PC31DOWNTO2_shadow;
RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC( 31 DOWNTO 2 );
RIN_F_PC31DOWNTO2_intermed_2 <= RIN_F_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_3 <= RIN_X_CTRL_PC31DOWNTO2_intermed_2;
RIN_X_CTRL_PC31DOWNTO2_intermed_4 <= RIN_X_CTRL_PC31DOWNTO2_intermed_3;
IRIN_ADDR31DOWNTO2_intermed_1 <= IRIN.ADDR( 31 DOWNTO 2 );
IRIN_ADDR31DOWNTO2_intermed_2 <= IRIN_ADDR31DOWNTO2_intermed_1;
IRIN_ADDR31DOWNTO2_intermed_3 <= IRIN_ADDR31DOWNTO2_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_4 <= R_E_CTRL_PC31DOWNTO2_intermed_3;
R_E_CTRL_PC31DOWNTO2_intermed_5 <= R_E_CTRL_PC31DOWNTO2_intermed_4;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_5;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_7 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_6;
EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO2_shadow;
EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_2 <= EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_D_PC31DOWNTO2_intermed_5 <= R_D_PC31DOWNTO2_intermed_4;
R_D_PC31DOWNTO2_intermed_6 <= R_D_PC31DOWNTO2_intermed_5;
R_D_PC31DOWNTO2_intermed_7 <= R_D_PC31DOWNTO2_intermed_6;
RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC ( 31 DOWNTO 2 );
IR_ADDR31DOWNTO2_intermed_1 <= IR.ADDR( 31 DOWNTO 2 );
IR_ADDR31DOWNTO2_intermed_2 <= IR_ADDR31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_5 <= RIN_E_CTRL_PC31DOWNTO2_intermed_4;
RIN_E_CTRL_PC31DOWNTO2_intermed_6 <= RIN_E_CTRL_PC31DOWNTO2_intermed_5;
R_F_PC31DOWNTO2_intermed_1 <= R.F.PC( 31 DOWNTO 2 );
R_F_PC31DOWNTO2_intermed_2 <= R_F_PC31DOWNTO2_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_3;
VIR_ADDR31DOWNTO2_shadow_intermed_1 <= VIR_ADDR31DOWNTO2_shadow;
VIR_ADDR31DOWNTO2_shadow_intermed_2 <= VIR_ADDR31DOWNTO2_shadow_intermed_1;
VIR_ADDR31DOWNTO2_shadow_intermed_3 <= VIR_ADDR31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC ( 31 DOWNTO 2 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC ( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_3 <= R_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_4 <= RIN_M_CTRL_PC31DOWNTO2_intermed_3;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_6 <= RIN_A_CTRL_PC31DOWNTO2_intermed_5;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
R_A_CTRL_PC31DOWNTO2_intermed_5 <= R_A_CTRL_PC31DOWNTO2_intermed_4;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
R_X_CTRL_PC31DOWNTO2_intermed_2 <= R_X_CTRL_PC31DOWNTO2_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
V_D_PC31DOWNTO2_shadow_intermed_6 <= V_D_PC31DOWNTO2_shadow_intermed_5;
V_D_PC31DOWNTO2_shadow_intermed_7 <= V_D_PC31DOWNTO2_shadow_intermed_6;
XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO2_shadow;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_D_PC31DOWNTO2_intermed_6 <= RIN_D_PC31DOWNTO2_intermed_5;
RIN_D_PC31DOWNTO2_intermed_7 <= RIN_D_PC31DOWNTO2_intermed_6;
EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow;
EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_2 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1;
V_F_PC31DOWNTO2_shadow_intermed_1 <= V_F_PC31DOWNTO2_shadow;
V_F_PC31DOWNTO2_shadow_intermed_2 <= V_F_PC31DOWNTO2_shadow_intermed_1;
V_F_PC31DOWNTO2_shadow_intermed_1 <= V_F_PC31DOWNTO2_shadow;
RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC( 31 DOWNTO 2 );
RIN_F_PC31DOWNTO2_intermed_2 <= RIN_F_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_3 <= RIN_X_CTRL_PC31DOWNTO2_intermed_2;
IRIN_ADDR31DOWNTO2_intermed_1 <= IRIN.ADDR( 31 DOWNTO 2 );
IRIN_ADDR31DOWNTO2_intermed_2 <= IRIN_ADDR31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_4 <= R_E_CTRL_PC31DOWNTO2_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_5;
EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO2_shadow;
EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_2 <= EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_D_PC31DOWNTO2_intermed_5 <= R_D_PC31DOWNTO2_intermed_4;
R_D_PC31DOWNTO2_intermed_6 <= R_D_PC31DOWNTO2_intermed_5;
RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC ( 31 DOWNTO 2 );
IR_ADDR31DOWNTO2_intermed_1 <= IR.ADDR( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_5 <= RIN_E_CTRL_PC31DOWNTO2_intermed_4;
R_F_PC31DOWNTO2_intermed_1 <= R.F.PC( 31 DOWNTO 2 );
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_2;
VIR_ADDR31DOWNTO2_shadow_intermed_1 <= VIR_ADDR31DOWNTO2_shadow;
VIR_ADDR31DOWNTO2_shadow_intermed_2 <= VIR_ADDR31DOWNTO2_shadow_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_3 <= R_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_4 <= RIN_M_CTRL_PC31DOWNTO2_intermed_3;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_6 <= RIN_A_CTRL_PC31DOWNTO2_intermed_5;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
R_A_CTRL_PC31DOWNTO2_intermed_5 <= R_A_CTRL_PC31DOWNTO2_intermed_4;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
R_X_CTRL_PC31DOWNTO2_intermed_2 <= R_X_CTRL_PC31DOWNTO2_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
V_D_PC31DOWNTO2_shadow_intermed_6 <= V_D_PC31DOWNTO2_shadow_intermed_5;
V_D_PC31DOWNTO2_shadow_intermed_7 <= V_D_PC31DOWNTO2_shadow_intermed_6;
XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO2_shadow;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_D_PC31DOWNTO2_intermed_6 <= RIN_D_PC31DOWNTO2_intermed_5;
RIN_D_PC31DOWNTO2_intermed_7 <= RIN_D_PC31DOWNTO2_intermed_6;
EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow;
V_F_PC31DOWNTO2_shadow_intermed_1 <= V_F_PC31DOWNTO2_shadow;
RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_3 <= RIN_X_CTRL_PC31DOWNTO2_intermed_2;
IRIN_ADDR31DOWNTO2_intermed_1 <= IRIN.ADDR( 31 DOWNTO 2 );
IRIN_ADDR31DOWNTO2_intermed_2 <= IRIN_ADDR31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_4 <= R_E_CTRL_PC31DOWNTO2_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_5;
EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO2_shadow;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_D_PC31DOWNTO2_intermed_5 <= R_D_PC31DOWNTO2_intermed_4;
R_D_PC31DOWNTO2_intermed_6 <= R_D_PC31DOWNTO2_intermed_5;
IR_ADDR31DOWNTO2_intermed_1 <= IR.ADDR( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_5 <= RIN_E_CTRL_PC31DOWNTO2_intermed_4;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_2;
VIR_ADDR31DOWNTO2_shadow_intermed_1 <= VIR_ADDR31DOWNTO2_shadow;
VIR_ADDR31DOWNTO2_shadow_intermed_2 <= VIR_ADDR31DOWNTO2_shadow_intermed_1;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
V_A_MULSTART_shadow_intermed_1 <= V_A_MULSTART_shadow;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
RIN_A_MULSTART_intermed_1 <= RIN.A.MULSTART;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
V_X_DATA0_shadow_intermed_2 <= V_X_DATA0_shadow_intermed_1;
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
DE_INST19_shadow_intermed_2 <= DE_INST19_shadow_intermed_1;
RIN_E_OP131_intermed_1 <= RIN.E.OP1( 31 );
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_A_CTRL_INST19_shadow_intermed_3 <= V_A_CTRL_INST19_shadow_intermed_2;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA ( 0 );
V_E_OP131_shadow_intermed_1 <= V_E_OP131_shadow;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_OP1_shadow_intermed_1 <= V_E_OP1_shadow;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_CTRL_INST19_shadow_intermed_2 <= V_E_CTRL_INST19_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
RIN_E_OP1_intermed_1 <= RIN.E.OP1;
R_E_CTRL_INST19_intermed_1 <= R.E.CTRL.INST( 19 );
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 );
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
R_X_DATA0_intermed_1 <= R.X.DATA( 0 );
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
R_A_CTRL_INST19_intermed_2 <= R_A_CTRL_INST19_intermed_1;
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
RIN_A_CTRL_INST19_intermed_3 <= RIN_A_CTRL_INST19_intermed_2;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST ( 19 );
DCO_DATA0_intermed_1 <= DCO.DATA ( 0 );
RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 );
RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST( 19 );
RIN_E_CTRL_INST19_intermed_2 <= RIN_E_CTRL_INST19_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
V_X_DATA0_shadow_intermed_2 <= V_X_DATA0_shadow_intermed_1;
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
DE_INST19_shadow_intermed_2 <= DE_INST19_shadow_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_A_CTRL_INST19_shadow_intermed_3 <= V_A_CTRL_INST19_shadow_intermed_2;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA ( 0 );
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
V_E_OP2_shadow_intermed_1 <= V_E_OP2_shadow;
RIN_E_OP2_intermed_1 <= RIN.E.OP2;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_CTRL_INST19_shadow_intermed_2 <= V_E_CTRL_INST19_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
R_E_CTRL_INST19_intermed_1 <= R.E.CTRL.INST( 19 );
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 );
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
R_X_DATA0_intermed_1 <= R.X.DATA( 0 );
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
R_A_CTRL_INST19_intermed_2 <= R_A_CTRL_INST19_intermed_1;
RIN_E_OP231_intermed_1 <= RIN.E.OP2( 31 );
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
RIN_A_CTRL_INST19_intermed_3 <= RIN_A_CTRL_INST19_intermed_2;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST ( 19 );
V_E_OP231_shadow_intermed_1 <= V_E_OP231_shadow;
DCO_DATA0_intermed_1 <= DCO.DATA ( 0 );
RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 );
RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST( 19 );
RIN_E_CTRL_INST19_intermed_2 <= RIN_E_CTRL_INST19_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_A_CTRL_INST24_shadow_intermed_1 <= V_A_CTRL_INST24_shadow;
V_A_CTRL_INST24_shadow_intermed_2 <= V_A_CTRL_INST24_shadow_intermed_1;
V_A_CTRL_INST24_shadow_intermed_3 <= V_A_CTRL_INST24_shadow_intermed_2;
V_E_CTRL_INST24_shadow_intermed_1 <= V_E_CTRL_INST24_shadow;
V_E_CTRL_INST24_shadow_intermed_2 <= V_E_CTRL_INST24_shadow_intermed_1;
DE_INST24_shadow_intermed_1 <= DE_INST24_shadow;
DE_INST24_shadow_intermed_2 <= DE_INST24_shadow_intermed_1;
DE_INST24_shadow_intermed_3 <= DE_INST24_shadow_intermed_2;
V_E_CTRL_INST24_shadow_intermed_1 <= V_E_CTRL_INST24_shadow;
R_A_CTRL_INST24_intermed_1 <= R.A.CTRL.INST( 24 );
R_A_CTRL_INST24_intermed_2 <= R_A_CTRL_INST24_intermed_1;
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST ( 24 );
RIN_A_CTRL_INST24_intermed_2 <= RIN_A_CTRL_INST24_intermed_1;
V_A_CTRL_INST24_shadow_intermed_1 <= V_A_CTRL_INST24_shadow;
V_A_CTRL_INST24_shadow_intermed_2 <= V_A_CTRL_INST24_shadow_intermed_1;
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST( 24 );
RIN_A_CTRL_INST24_intermed_2 <= RIN_A_CTRL_INST24_intermed_1;
RIN_A_CTRL_INST24_intermed_3 <= RIN_A_CTRL_INST24_intermed_2;
RIN_E_CTRL_INST24_intermed_1 <= RIN.E.CTRL.INST( 24 );
RIN_E_CTRL_INST24_intermed_2 <= RIN_E_CTRL_INST24_intermed_1;
R_E_CTRL_INST24_intermed_1 <= R.E.CTRL.INST( 24 );
R_E_CTRL_INST24_intermed_2 <= R_E_CTRL_INST24_intermed_1;
R_A_CTRL_INST24_intermed_1 <= R.A.CTRL.INST ( 24 );
RIN_E_CTRL_INST24_intermed_1 <= RIN.E.CTRL.INST ( 24 );
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_DIVSTART_intermed_1 <= RIN.A.DIVSTART;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
V_A_DIVSTART_shadow_intermed_1 <= V_A_DIVSTART_shadow;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
V_X_DATA0_shadow_intermed_2 <= V_X_DATA0_shadow_intermed_1;
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
DE_INST19_shadow_intermed_2 <= DE_INST19_shadow_intermed_1;
RIN_E_OP131_intermed_1 <= RIN.E.OP1( 31 );
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_A_CTRL_INST19_shadow_intermed_3 <= V_A_CTRL_INST19_shadow_intermed_2;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA ( 0 );
V_E_OP131_shadow_intermed_1 <= V_E_OP131_shadow;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_OP1_shadow_intermed_1 <= V_E_OP1_shadow;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_CTRL_INST19_shadow_intermed_2 <= V_E_CTRL_INST19_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
RIN_E_OP1_intermed_1 <= RIN.E.OP1;
R_E_CTRL_INST19_intermed_1 <= R.E.CTRL.INST( 19 );
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 );
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
R_X_DATA0_intermed_1 <= R.X.DATA( 0 );
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
R_A_CTRL_INST19_intermed_2 <= R_A_CTRL_INST19_intermed_1;
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
RIN_A_CTRL_INST19_intermed_3 <= RIN_A_CTRL_INST19_intermed_2;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST ( 19 );
DCO_DATA0_intermed_1 <= DCO.DATA ( 0 );
RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 );
RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST( 19 );
RIN_E_CTRL_INST19_intermed_2 <= RIN_E_CTRL_INST19_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
V_X_DATA0_shadow_intermed_2 <= V_X_DATA0_shadow_intermed_1;
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
DE_INST19_shadow_intermed_2 <= DE_INST19_shadow_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_A_CTRL_INST19_shadow_intermed_3 <= V_A_CTRL_INST19_shadow_intermed_2;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA ( 0 );
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
V_E_OP2_shadow_intermed_1 <= V_E_OP2_shadow;
RIN_E_OP2_intermed_1 <= RIN.E.OP2;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_CTRL_INST19_shadow_intermed_2 <= V_E_CTRL_INST19_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
R_E_CTRL_INST19_intermed_1 <= R.E.CTRL.INST( 19 );
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 );
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
R_X_DATA0_intermed_1 <= R.X.DATA( 0 );
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
R_A_CTRL_INST19_intermed_2 <= R_A_CTRL_INST19_intermed_1;
RIN_E_OP231_intermed_1 <= RIN.E.OP2( 31 );
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
RIN_A_CTRL_INST19_intermed_3 <= RIN_A_CTRL_INST19_intermed_2;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST ( 19 );
V_E_OP231_shadow_intermed_1 <= V_E_OP231_shadow;
DCO_DATA0_intermed_1 <= DCO.DATA ( 0 );
RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 );
RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST( 19 );
RIN_E_CTRL_INST19_intermed_2 <= RIN_E_CTRL_INST19_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
DE_INST19_shadow_intermed_2 <= DE_INST19_shadow_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 );
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
R_A_CTRL_INST19_intermed_2 <= R_A_CTRL_INST19_intermed_1;
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
RIN_M_Y31_intermed_1 <= RIN.M.Y ( 31 );
RIN_M_Y_intermed_1 <= RIN.M.Y;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_M_Y31_shadow_intermed_1 <= V_M_Y31_shadow;
V_M_Y31_shadow_intermed_2 <= V_M_Y31_shadow_intermed_1;
V_M_Y_shadow_intermed_1 <= V_M_Y_shadow;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_CTRL_INST19_shadow_intermed_2 <= V_E_CTRL_INST19_shadow_intermed_1;
R_E_CTRL_INST19_intermed_1 <= R.E.CTRL.INST( 19 );
V_M_Y31_shadow_intermed_1 <= V_M_Y31_shadow;
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 );
RIN_M_Y31_intermed_1 <= RIN.M.Y( 31 );
RIN_M_Y31_intermed_2 <= RIN_M_Y31_intermed_1;
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
R_M_Y31_intermed_1 <= R.M.Y( 31 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST ( 19 );
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST( 19 );
RIN_E_CTRL_INST19_intermed_2 <= RIN_E_CTRL_INST19_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
RIN_M_Y31_intermed_1 <= RIN.M.Y ( 31 );
V_M_Y31_shadow_intermed_1 <= V_M_Y31_shadow;
V_M_Y31_shadow_intermed_2 <= V_M_Y31_shadow_intermed_1;
V_M_Y31_shadow_intermed_1 <= V_M_Y31_shadow;
RIN_M_Y31_intermed_1 <= RIN.M.Y( 31 );
RIN_M_Y31_intermed_2 <= RIN_M_Y31_intermed_1;
R_M_Y31_intermed_1 <= R.M.Y( 31 );
R_M_Y31_intermed_2 <= R_M_Y31_intermed_1;
VDSU_CRDY2_shadow_intermed_1 <= VDSU_CRDY2_shadow;
VDSU_CRDY2_shadow_intermed_2 <= VDSU_CRDY2_shadow_intermed_1;
DSUIN_CRDY2_intermed_1 <= DSUIN.CRDY ( 2 );
VDSU_CRDY2_shadow_intermed_1 <= VDSU_CRDY2_shadow;
DSUIN_CRDY2_intermed_1 <= DSUIN.CRDY( 2 );
DSUIN_CRDY2_intermed_2 <= DSUIN_CRDY2_intermed_1;
DSUR_CRDY2_intermed_1 <= DSUR.CRDY( 2 );
DSUR_CRDY2_intermed_2 <= DSUR_CRDY2_intermed_1;
VP_ERROR_shadow_intermed_1 <= VP_ERROR_shadow;
VP_ERROR_shadow_intermed_2 <= VP_ERROR_shadow_intermed_1;
RIN_X_NERROR_intermed_1 <= RIN.X.NERROR;
RPIN_ERROR_intermed_1 <= RPIN.ERROR;
RPIN_ERROR_intermed_2 <= RPIN_ERROR_intermed_1;
V_X_NERROR_shadow_intermed_1 <= V_X_NERROR_shadow;
RP_ERROR_intermed_1 <= RP.ERROR;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC ( 31 DOWNTO 2 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC ( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC ( 31 DOWNTO 2 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC ( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC ( 31 DOWNTO 2 );
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow;
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 );
RIN_X_RESULT6DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO0_intermed_1;
R_X_RESULT6DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 );
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
R_X_DATA0_intermed_1 <= R.X.DATA( 0 );
RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 );
RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC ( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC ( 31 DOWNTO 2 );
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC ( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC ( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_X_CTRL_TT3DOWNTO0_shadow;
V_X_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_X_CTRL_TT3DOWNTO0_shadow_intermed_1;
R_M_CTRL_TT3DOWNTO0_intermed_1 <= R.M.CTRL.TT( 3 DOWNTO 0 );
R_M_CTRL_TT3DOWNTO0_intermed_2 <= R_M_CTRL_TT3DOWNTO0_intermed_1;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_M_CTRL_TT3DOWNTO0_shadow;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_M_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_M_CTRL_TT3DOWNTO0_shadow_intermed_2;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_3 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2;
R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
R_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= R_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
R_A_CTRL_TT3DOWNTO0_intermed_1 <= R.A.CTRL.TT( 3 DOWNTO 0 );
R_A_CTRL_TT3DOWNTO0_intermed_2 <= R_A_CTRL_TT3DOWNTO0_intermed_1;
R_A_CTRL_TT3DOWNTO0_intermed_3 <= R_A_CTRL_TT3DOWNTO0_intermed_2;
R_A_CTRL_TT3DOWNTO0_intermed_4 <= R_A_CTRL_TT3DOWNTO0_intermed_3;
RIN_A_CTRL_TT3DOWNTO0_intermed_1 <= RIN.A.CTRL.TT( 3 DOWNTO 0 );
RIN_A_CTRL_TT3DOWNTO0_intermed_2 <= RIN_A_CTRL_TT3DOWNTO0_intermed_1;
RIN_A_CTRL_TT3DOWNTO0_intermed_3 <= RIN_A_CTRL_TT3DOWNTO0_intermed_2;
RIN_A_CTRL_TT3DOWNTO0_intermed_4 <= RIN_A_CTRL_TT3DOWNTO0_intermed_3;
RIN_A_CTRL_TT3DOWNTO0_intermed_5 <= RIN_A_CTRL_TT3DOWNTO0_intermed_4;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_3 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_A_CTRL_TT3DOWNTO0_shadow;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_2;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_4 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_3;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_5 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_4;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
R_W_S_TT3DOWNTO0_intermed_1 <= R.W.S.TT( 3 DOWNTO 0 );
R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 );
R_E_CTRL_TT3DOWNTO0_intermed_1 <= R.E.CTRL.TT( 3 DOWNTO 0 );
R_E_CTRL_TT3DOWNTO0_intermed_2 <= R_E_CTRL_TT3DOWNTO0_intermed_1;
R_E_CTRL_TT3DOWNTO0_intermed_3 <= R_E_CTRL_TT3DOWNTO0_intermed_2;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1;
RIN_W_S_TT3DOWNTO0_intermed_1 <= RIN.W.S.TT( 3 DOWNTO 0 );
RIN_W_S_TT3DOWNTO0_intermed_2 <= RIN_W_S_TT3DOWNTO0_intermed_1;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_E_CTRL_TT3DOWNTO0_shadow;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_2;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_4 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_3;
RIN_M_CTRL_TT3DOWNTO0_intermed_1 <= RIN.M.CTRL.TT( 3 DOWNTO 0 );
RIN_M_CTRL_TT3DOWNTO0_intermed_2 <= RIN_M_CTRL_TT3DOWNTO0_intermed_1;
RIN_M_CTRL_TT3DOWNTO0_intermed_3 <= RIN_M_CTRL_TT3DOWNTO0_intermed_2;
RIN_X_CTRL_TT3DOWNTO0_intermed_1 <= RIN.X.CTRL.TT( 3 DOWNTO 0 );
RIN_X_CTRL_TT3DOWNTO0_intermed_2 <= RIN_X_CTRL_TT3DOWNTO0_intermed_1;
V_W_S_TT3DOWNTO0_shadow_intermed_1 <= V_W_S_TT3DOWNTO0_shadow;
R_X_CTRL_TT3DOWNTO0_intermed_1 <= R.X.CTRL.TT( 3 DOWNTO 0 );
RIN_E_CTRL_TT3DOWNTO0_intermed_1 <= RIN.E.CTRL.TT( 3 DOWNTO 0 );
RIN_E_CTRL_TT3DOWNTO0_intermed_2 <= RIN_E_CTRL_TT3DOWNTO0_intermed_1;
RIN_E_CTRL_TT3DOWNTO0_intermed_3 <= RIN_E_CTRL_TT3DOWNTO0_intermed_2;
RIN_E_CTRL_TT3DOWNTO0_intermed_4 <= RIN_E_CTRL_TT3DOWNTO0_intermed_3;
XC_VECTT3DOWNTO0_shadow_intermed_1 <= XC_VECTT3DOWNTO0_shadow;
V_M_RESULT1DOWNTO0_shadow_intermed_1 <= V_M_RESULT1DOWNTO0_shadow;
RIN_M_RESULT1DOWNTO0_intermed_1 <= RIN.M.RESULT( 1 DOWNTO 0 );
RIN_M_RESULT1DOWNTO0_intermed_2 <= RIN_M_RESULT1DOWNTO0_intermed_1;
R_M_RESULT1DOWNTO0_intermed_1 <= R.M.RESULT( 1 DOWNTO 0 );
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 );
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
R_X_DATA031_intermed_1 <= R.X.DATA ( 0 )( 31 );
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
DE_INST19_shadow_intermed_2 <= DE_INST19_shadow_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
R_E_CTRL_INST19_intermed_1 <= R.E.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 );
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST( 19 );
RIN_E_CTRL_INST19_intermed_2 <= RIN_E_CTRL_INST19_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST ( 20 );
R_E_CTRL_INST20_intermed_1 <= R.E.CTRL.INST( 20 );
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST( 20 );
RIN_A_CTRL_INST20_intermed_2 <= RIN_A_CTRL_INST20_intermed_1;
V_E_CTRL_INST20_shadow_intermed_1 <= V_E_CTRL_INST20_shadow;
DE_INST20_shadow_intermed_1 <= DE_INST20_shadow;
DE_INST20_shadow_intermed_2 <= DE_INST20_shadow_intermed_1;
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
V_A_CTRL_INST20_shadow_intermed_2 <= V_A_CTRL_INST20_shadow_intermed_1;
RIN_E_CTRL_INST20_intermed_1 <= RIN.E.CTRL.INST( 20 );
RIN_E_CTRL_INST20_intermed_2 <= RIN_E_CTRL_INST20_intermed_1;
R_A_CTRL_INST20_intermed_1 <= R.A.CTRL.INST( 20 );
RIN_X_DATA00_intermed_1 <= RIN.X.DATA ( 0 )( 0 );
RIN_X_DATA00_intermed_2 <= RIN_X_DATA00_intermed_1;
DCO_DATA00_intermed_1 <= DCO.DATA ( 0 )( 0 );
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
R_X_DATA00_intermed_1 <= R.X.DATA ( 0 )( 0 );
RIN_X_DATA00_intermed_1 <= RIN.X.DATA( 0 )( 0 );
RIN_X_DATA00_intermed_2 <= RIN_X_DATA00_intermed_1;
R_X_DATA00_intermed_1 <= R.X.DATA( 0 )( 0 );
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
RIN_X_DATA00_intermed_1 <= RIN.X.DATA( 0 )( 0 );
RIN_X_DATA00_intermed_2 <= RIN_X_DATA00_intermed_1;
R_X_DATA00_intermed_1 <= R.X.DATA( 0 )( 0 );
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
R_X_DATA04DOWNTO0_intermed_1 <= R.X.DATA( 0 )( 4 DOWNTO 0 );
R_X_DATA04DOWNTO0_intermed_1 <= R.X.DATA ( 0 )( 4 DOWNTO 0 );
DCO_DATA04DOWNTO0_intermed_1 <= DCO.DATA ( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA ( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_2 <= RIN_X_DATA04DOWNTO0_intermed_1;
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_2 <= RIN_X_DATA04DOWNTO0_intermed_1;
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
R_X_DATA04DOWNTO0_intermed_1 <= R.X.DATA( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_2 <= RIN_X_DATA04DOWNTO0_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_3 <= R_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_4 <= RIN_M_CTRL_PC31DOWNTO2_intermed_3;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_6 <= RIN_A_CTRL_PC31DOWNTO2_intermed_5;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
R_A_CTRL_PC31DOWNTO2_intermed_5 <= R_A_CTRL_PC31DOWNTO2_intermed_4;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
R_X_CTRL_PC31DOWNTO2_intermed_2 <= R_X_CTRL_PC31DOWNTO2_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
V_D_PC31DOWNTO2_shadow_intermed_6 <= V_D_PC31DOWNTO2_shadow_intermed_5;
V_D_PC31DOWNTO2_shadow_intermed_7 <= V_D_PC31DOWNTO2_shadow_intermed_6;
XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO2_shadow;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_D_PC31DOWNTO2_intermed_6 <= RIN_D_PC31DOWNTO2_intermed_5;
RIN_D_PC31DOWNTO2_intermed_7 <= RIN_D_PC31DOWNTO2_intermed_6;
EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow;
V_F_PC31DOWNTO2_shadow_intermed_1 <= V_F_PC31DOWNTO2_shadow;
RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC( 31 DOWNTO 2 );
RIN_F_PC31DOWNTO2_intermed_2 <= RIN_F_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_3 <= RIN_X_CTRL_PC31DOWNTO2_intermed_2;
IRIN_ADDR31DOWNTO2_intermed_1 <= IRIN.ADDR( 31 DOWNTO 2 );
IRIN_ADDR31DOWNTO2_intermed_2 <= IRIN_ADDR31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_4 <= R_E_CTRL_PC31DOWNTO2_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_5;
EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO2_shadow;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_D_PC31DOWNTO2_intermed_5 <= R_D_PC31DOWNTO2_intermed_4;
R_D_PC31DOWNTO2_intermed_6 <= R_D_PC31DOWNTO2_intermed_5;
IR_ADDR31DOWNTO2_intermed_1 <= IR.ADDR( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_5 <= RIN_E_CTRL_PC31DOWNTO2_intermed_4;
R_F_PC31DOWNTO2_intermed_1 <= R.F.PC( 31 DOWNTO 2 );
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_2;
VIR_ADDR31DOWNTO2_shadow_intermed_1 <= VIR_ADDR31DOWNTO2_shadow;
VIR_ADDR31DOWNTO2_shadow_intermed_2 <= VIR_ADDR31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
V_A_CTRL_INST24_shadow_intermed_1 <= V_A_CTRL_INST24_shadow;
V_A_CTRL_INST24_shadow_intermed_2 <= V_A_CTRL_INST24_shadow_intermed_1;
V_E_CTRL_INST24_shadow_intermed_1 <= V_E_CTRL_INST24_shadow;
DE_INST24_shadow_intermed_1 <= DE_INST24_shadow;
DE_INST24_shadow_intermed_2 <= DE_INST24_shadow_intermed_1;
R_A_CTRL_INST24_intermed_1 <= R.A.CTRL.INST( 24 );
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST ( 24 );
V_A_CTRL_INST24_shadow_intermed_1 <= V_A_CTRL_INST24_shadow;
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST( 24 );
RIN_A_CTRL_INST24_intermed_2 <= RIN_A_CTRL_INST24_intermed_1;
RIN_E_CTRL_INST24_intermed_1 <= RIN.E.CTRL.INST( 24 );
RIN_E_CTRL_INST24_intermed_2 <= RIN_E_CTRL_INST24_intermed_1;
R_E_CTRL_INST24_intermed_1 <= R.E.CTRL.INST( 24 );
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
V_M_Y31_shadow_intermed_1 <= V_M_Y31_shadow;
RIN_M_Y31_intermed_1 <= RIN.M.Y( 31 );
RIN_M_Y31_intermed_2 <= RIN_M_Y31_intermed_1;
R_M_Y31_intermed_1 <= R.M.Y( 31 );
VDSU_CRDY2_shadow_intermed_1 <= VDSU_CRDY2_shadow;
DSUIN_CRDY2_intermed_1 <= DSUIN.CRDY( 2 );
DSUIN_CRDY2_intermed_2 <= DSUIN_CRDY2_intermed_1;
DSUR_CRDY2_intermed_1 <= DSUR.CRDY( 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC ( 31 DOWNTO 2 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_X_DATA1_shadow_intermed_1 <= V_X_DATA1_shadow;
DCO_DATA1_intermed_1 <= DCO.DATA ( 1 );
V_X_DATA1_shadow_intermed_1 <= V_X_DATA1_shadow;
V_X_DATA1_shadow_intermed_2 <= V_X_DATA1_shadow_intermed_1;
RIN_X_DATA1_intermed_1 <= RIN.X.DATA ( 1 );
R_X_DATA1_intermed_1 <= R.X.DATA( 1 );
R_X_DATA1_intermed_2 <= R_X_DATA1_intermed_1;
RIN_X_DATA1_intermed_1 <= RIN.X.DATA( 1 );
RIN_X_DATA1_intermed_2 <= RIN_X_DATA1_intermed_1;
EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO12_shadow;
EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_2 <= EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_1;
RIN_F_PC31DOWNTO12_intermed_1 <= RIN.F.PC ( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_2 <= RIN_A_CTRL_PC31DOWNTO12_intermed_1;
RIN_A_CTRL_PC31DOWNTO12_intermed_3 <= RIN_A_CTRL_PC31DOWNTO12_intermed_2;
RIN_A_CTRL_PC31DOWNTO12_intermed_4 <= RIN_A_CTRL_PC31DOWNTO12_intermed_3;
RIN_A_CTRL_PC31DOWNTO12_intermed_5 <= RIN_A_CTRL_PC31DOWNTO12_intermed_4;
RIN_A_CTRL_PC31DOWNTO12_intermed_6 <= RIN_A_CTRL_PC31DOWNTO12_intermed_5;
RIN_A_CTRL_PC31DOWNTO12_intermed_7 <= RIN_A_CTRL_PC31DOWNTO12_intermed_6;
RIN_E_CTRL_PC31DOWNTO12_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 12 );
RIN_E_CTRL_PC31DOWNTO12_intermed_2 <= RIN_E_CTRL_PC31DOWNTO12_intermed_1;
RIN_E_CTRL_PC31DOWNTO12_intermed_3 <= RIN_E_CTRL_PC31DOWNTO12_intermed_2;
RIN_E_CTRL_PC31DOWNTO12_intermed_4 <= RIN_E_CTRL_PC31DOWNTO12_intermed_3;
RIN_E_CTRL_PC31DOWNTO12_intermed_5 <= RIN_E_CTRL_PC31DOWNTO12_intermed_4;
RIN_E_CTRL_PC31DOWNTO12_intermed_6 <= RIN_E_CTRL_PC31DOWNTO12_intermed_5;
V_F_PC31DOWNTO12_shadow_intermed_1 <= V_F_PC31DOWNTO12_shadow;
V_F_PC31DOWNTO12_shadow_intermed_2 <= V_F_PC31DOWNTO12_shadow_intermed_1;
R_M_CTRL_PC31DOWNTO12_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 12 );
R_M_CTRL_PC31DOWNTO12_intermed_2 <= R_M_CTRL_PC31DOWNTO12_intermed_1;
R_M_CTRL_PC31DOWNTO12_intermed_3 <= R_M_CTRL_PC31DOWNTO12_intermed_2;
R_M_CTRL_PC31DOWNTO12_intermed_4 <= R_M_CTRL_PC31DOWNTO12_intermed_3;
IRIN_ADDR31DOWNTO12_intermed_1 <= IRIN.ADDR( 31 DOWNTO 12 );
IRIN_ADDR31DOWNTO12_intermed_2 <= IRIN_ADDR31DOWNTO12_intermed_1;
IRIN_ADDR31DOWNTO12_intermed_3 <= IRIN_ADDR31DOWNTO12_intermed_2;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO12_shadow;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_3;
EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO13_shadow;
EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_2 <= EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_1;
XC_TRAP_ADDRESS31DOWNTO12_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO12_shadow;
XC_TRAP_ADDRESS31DOWNTO12_shadow_intermed_2 <= XC_TRAP_ADDRESS31DOWNTO12_shadow_intermed_1;
R_F_PC31DOWNTO12_intermed_1 <= R.F.PC( 31 DOWNTO 12 );
R_F_PC31DOWNTO12_intermed_2 <= R_F_PC31DOWNTO12_intermed_1;
RIN_M_CTRL_PC31DOWNTO12_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 12 );
RIN_M_CTRL_PC31DOWNTO12_intermed_2 <= RIN_M_CTRL_PC31DOWNTO12_intermed_1;
RIN_M_CTRL_PC31DOWNTO12_intermed_3 <= RIN_M_CTRL_PC31DOWNTO12_intermed_2;
RIN_M_CTRL_PC31DOWNTO12_intermed_4 <= RIN_M_CTRL_PC31DOWNTO12_intermed_3;
RIN_M_CTRL_PC31DOWNTO12_intermed_5 <= RIN_M_CTRL_PC31DOWNTO12_intermed_4;
IR_ADDR31DOWNTO12_intermed_1 <= IR.ADDR( 31 DOWNTO 12 );
IR_ADDR31DOWNTO12_intermed_2 <= IR_ADDR31DOWNTO12_intermed_1;
R_X_CTRL_PC31DOWNTO12_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 12 );
R_X_CTRL_PC31DOWNTO12_intermed_2 <= R_X_CTRL_PC31DOWNTO12_intermed_1;
R_X_CTRL_PC31DOWNTO12_intermed_3 <= R_X_CTRL_PC31DOWNTO12_intermed_2;
V_D_PC31DOWNTO12_shadow_intermed_1 <= V_D_PC31DOWNTO12_shadow;
V_D_PC31DOWNTO12_shadow_intermed_2 <= V_D_PC31DOWNTO12_shadow_intermed_1;
V_D_PC31DOWNTO12_shadow_intermed_3 <= V_D_PC31DOWNTO12_shadow_intermed_2;
V_D_PC31DOWNTO12_shadow_intermed_4 <= V_D_PC31DOWNTO12_shadow_intermed_3;
V_D_PC31DOWNTO12_shadow_intermed_5 <= V_D_PC31DOWNTO12_shadow_intermed_4;
V_D_PC31DOWNTO12_shadow_intermed_6 <= V_D_PC31DOWNTO12_shadow_intermed_5;
V_D_PC31DOWNTO12_shadow_intermed_7 <= V_D_PC31DOWNTO12_shadow_intermed_6;
V_D_PC31DOWNTO12_shadow_intermed_8 <= V_D_PC31DOWNTO12_shadow_intermed_7;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO12_shadow;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_5;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_7 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_6;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO12_shadow;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_4;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_6 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_5;
EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_1 <= EX_ADD_RES32DOWNTO330DOWNTO11_shadow;
EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_2 <= EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_1;
RIN_F_PC31DOWNTO12_intermed_1 <= RIN.F.PC( 31 DOWNTO 12 );
RIN_F_PC31DOWNTO12_intermed_2 <= RIN_F_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_1 <= R.D.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_2 <= R_D_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_3 <= R_D_PC31DOWNTO12_intermed_2;
R_D_PC31DOWNTO12_intermed_4 <= R_D_PC31DOWNTO12_intermed_3;
R_D_PC31DOWNTO12_intermed_5 <= R_D_PC31DOWNTO12_intermed_4;
R_D_PC31DOWNTO12_intermed_6 <= R_D_PC31DOWNTO12_intermed_5;
R_D_PC31DOWNTO12_intermed_7 <= R_D_PC31DOWNTO12_intermed_6;
R_A_CTRL_PC31DOWNTO12_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 12 );
R_A_CTRL_PC31DOWNTO12_intermed_2 <= R_A_CTRL_PC31DOWNTO12_intermed_1;
R_A_CTRL_PC31DOWNTO12_intermed_3 <= R_A_CTRL_PC31DOWNTO12_intermed_2;
R_A_CTRL_PC31DOWNTO12_intermed_4 <= R_A_CTRL_PC31DOWNTO12_intermed_3;
R_A_CTRL_PC31DOWNTO12_intermed_5 <= R_A_CTRL_PC31DOWNTO12_intermed_4;
R_A_CTRL_PC31DOWNTO12_intermed_6 <= R_A_CTRL_PC31DOWNTO12_intermed_5;
R_E_CTRL_PC31DOWNTO12_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 12 );
R_E_CTRL_PC31DOWNTO12_intermed_2 <= R_E_CTRL_PC31DOWNTO12_intermed_1;
R_E_CTRL_PC31DOWNTO12_intermed_3 <= R_E_CTRL_PC31DOWNTO12_intermed_2;
R_E_CTRL_PC31DOWNTO12_intermed_4 <= R_E_CTRL_PC31DOWNTO12_intermed_3;
R_E_CTRL_PC31DOWNTO12_intermed_5 <= R_E_CTRL_PC31DOWNTO12_intermed_4;
RIN_X_CTRL_PC31DOWNTO12_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 12 );
RIN_X_CTRL_PC31DOWNTO12_intermed_2 <= RIN_X_CTRL_PC31DOWNTO12_intermed_1;
RIN_X_CTRL_PC31DOWNTO12_intermed_3 <= RIN_X_CTRL_PC31DOWNTO12_intermed_2;
RIN_X_CTRL_PC31DOWNTO12_intermed_4 <= RIN_X_CTRL_PC31DOWNTO12_intermed_3;
RIN_D_PC31DOWNTO12_intermed_1 <= RIN.D.PC( 31 DOWNTO 12 );
RIN_D_PC31DOWNTO12_intermed_2 <= RIN_D_PC31DOWNTO12_intermed_1;
RIN_D_PC31DOWNTO12_intermed_3 <= RIN_D_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_4 <= RIN_D_PC31DOWNTO12_intermed_3;
RIN_D_PC31DOWNTO12_intermed_5 <= RIN_D_PC31DOWNTO12_intermed_4;
RIN_D_PC31DOWNTO12_intermed_6 <= RIN_D_PC31DOWNTO12_intermed_5;
RIN_D_PC31DOWNTO12_intermed_7 <= RIN_D_PC31DOWNTO12_intermed_6;
RIN_D_PC31DOWNTO12_intermed_8 <= RIN_D_PC31DOWNTO12_intermed_7;
VIR_ADDR31DOWNTO12_shadow_intermed_1 <= VIR_ADDR31DOWNTO12_shadow;
VIR_ADDR31DOWNTO12_shadow_intermed_2 <= VIR_ADDR31DOWNTO12_shadow_intermed_1;
VIR_ADDR31DOWNTO12_shadow_intermed_3 <= VIR_ADDR31DOWNTO12_shadow_intermed_2;
V_F_PC31DOWNTO12_shadow_intermed_1 <= V_F_PC31DOWNTO12_shadow;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO12_shadow;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_4;
ICO_DATA0_intermed_1 <= ICO.DATA ( 0 );
RIN_D_INST0_intermed_1 <= RIN.D.INST ( 0 );
V_D_INST0_shadow_intermed_1 <= V_D_INST0_shadow;
V_D_INST0_shadow_intermed_2 <= V_D_INST0_shadow_intermed_1;
R_D_INST0_intermed_1 <= R.D.INST( 0 );
R_D_INST0_intermed_2 <= R_D_INST0_intermed_1;
RIN_D_INST0_intermed_1 <= RIN.D.INST( 0 );
RIN_D_INST0_intermed_2 <= RIN_D_INST0_intermed_1;
V_D_INST0_shadow_intermed_1 <= V_D_INST0_shadow;
V_D_INST1_shadow_intermed_1 <= V_D_INST1_shadow;
V_D_INST1_shadow_intermed_2 <= V_D_INST1_shadow_intermed_1;
RIN_D_INST1_intermed_1 <= RIN.D.INST ( 1 );
RIN_D_INST1_intermed_1 <= RIN.D.INST( 1 );
RIN_D_INST1_intermed_2 <= RIN_D_INST1_intermed_1;
V_D_INST1_shadow_intermed_1 <= V_D_INST1_shadow;
R_D_INST1_intermed_1 <= R.D.INST( 1 );
R_D_INST1_intermed_2 <= R_D_INST1_intermed_1;
ICO_DATA1_intermed_1 <= ICO.DATA ( 1 );
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 );
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
R_X_DATA031_intermed_2 <= R_X_DATA031_intermed_1;
V_X_DATA1_shadow_intermed_1 <= V_X_DATA1_shadow;
R_X_DATA1_intermed_1 <= R.X.DATA( 1 );
RIN_X_DATA1_intermed_1 <= RIN.X.DATA( 1 );
RIN_X_DATA1_intermed_2 <= RIN_X_DATA1_intermed_1;
EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO12_shadow;
RIN_A_CTRL_PC31DOWNTO12_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_2 <= RIN_A_CTRL_PC31DOWNTO12_intermed_1;
RIN_A_CTRL_PC31DOWNTO12_intermed_3 <= RIN_A_CTRL_PC31DOWNTO12_intermed_2;
RIN_A_CTRL_PC31DOWNTO12_intermed_4 <= RIN_A_CTRL_PC31DOWNTO12_intermed_3;
RIN_A_CTRL_PC31DOWNTO12_intermed_5 <= RIN_A_CTRL_PC31DOWNTO12_intermed_4;
RIN_A_CTRL_PC31DOWNTO12_intermed_6 <= RIN_A_CTRL_PC31DOWNTO12_intermed_5;
RIN_E_CTRL_PC31DOWNTO12_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 12 );
RIN_E_CTRL_PC31DOWNTO12_intermed_2 <= RIN_E_CTRL_PC31DOWNTO12_intermed_1;
RIN_E_CTRL_PC31DOWNTO12_intermed_3 <= RIN_E_CTRL_PC31DOWNTO12_intermed_2;
RIN_E_CTRL_PC31DOWNTO12_intermed_4 <= RIN_E_CTRL_PC31DOWNTO12_intermed_3;
RIN_E_CTRL_PC31DOWNTO12_intermed_5 <= RIN_E_CTRL_PC31DOWNTO12_intermed_4;
V_F_PC31DOWNTO12_shadow_intermed_1 <= V_F_PC31DOWNTO12_shadow;
R_M_CTRL_PC31DOWNTO12_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 12 );
R_M_CTRL_PC31DOWNTO12_intermed_2 <= R_M_CTRL_PC31DOWNTO12_intermed_1;
R_M_CTRL_PC31DOWNTO12_intermed_3 <= R_M_CTRL_PC31DOWNTO12_intermed_2;
IRIN_ADDR31DOWNTO12_intermed_1 <= IRIN.ADDR( 31 DOWNTO 12 );
IRIN_ADDR31DOWNTO12_intermed_2 <= IRIN_ADDR31DOWNTO12_intermed_1;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO12_shadow;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_2;
EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO13_shadow;
XC_TRAP_ADDRESS31DOWNTO12_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO12_shadow;
R_F_PC31DOWNTO12_intermed_1 <= R.F.PC( 31 DOWNTO 12 );
RIN_M_CTRL_PC31DOWNTO12_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 12 );
RIN_M_CTRL_PC31DOWNTO12_intermed_2 <= RIN_M_CTRL_PC31DOWNTO12_intermed_1;
RIN_M_CTRL_PC31DOWNTO12_intermed_3 <= RIN_M_CTRL_PC31DOWNTO12_intermed_2;
RIN_M_CTRL_PC31DOWNTO12_intermed_4 <= RIN_M_CTRL_PC31DOWNTO12_intermed_3;
IR_ADDR31DOWNTO12_intermed_1 <= IR.ADDR( 31 DOWNTO 12 );
R_X_CTRL_PC31DOWNTO12_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 12 );
R_X_CTRL_PC31DOWNTO12_intermed_2 <= R_X_CTRL_PC31DOWNTO12_intermed_1;
V_D_PC31DOWNTO12_shadow_intermed_1 <= V_D_PC31DOWNTO12_shadow;
V_D_PC31DOWNTO12_shadow_intermed_2 <= V_D_PC31DOWNTO12_shadow_intermed_1;
V_D_PC31DOWNTO12_shadow_intermed_3 <= V_D_PC31DOWNTO12_shadow_intermed_2;
V_D_PC31DOWNTO12_shadow_intermed_4 <= V_D_PC31DOWNTO12_shadow_intermed_3;
V_D_PC31DOWNTO12_shadow_intermed_5 <= V_D_PC31DOWNTO12_shadow_intermed_4;
V_D_PC31DOWNTO12_shadow_intermed_6 <= V_D_PC31DOWNTO12_shadow_intermed_5;
V_D_PC31DOWNTO12_shadow_intermed_7 <= V_D_PC31DOWNTO12_shadow_intermed_6;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO12_shadow;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_5;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO12_shadow;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_4;
EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_1 <= EX_ADD_RES32DOWNTO330DOWNTO11_shadow;
RIN_F_PC31DOWNTO12_intermed_1 <= RIN.F.PC( 31 DOWNTO 12 );
RIN_F_PC31DOWNTO12_intermed_2 <= RIN_F_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_1 <= R.D.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_2 <= R_D_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_3 <= R_D_PC31DOWNTO12_intermed_2;
R_D_PC31DOWNTO12_intermed_4 <= R_D_PC31DOWNTO12_intermed_3;
R_D_PC31DOWNTO12_intermed_5 <= R_D_PC31DOWNTO12_intermed_4;
R_D_PC31DOWNTO12_intermed_6 <= R_D_PC31DOWNTO12_intermed_5;
R_A_CTRL_PC31DOWNTO12_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 12 );
R_A_CTRL_PC31DOWNTO12_intermed_2 <= R_A_CTRL_PC31DOWNTO12_intermed_1;
R_A_CTRL_PC31DOWNTO12_intermed_3 <= R_A_CTRL_PC31DOWNTO12_intermed_2;
R_A_CTRL_PC31DOWNTO12_intermed_4 <= R_A_CTRL_PC31DOWNTO12_intermed_3;
R_A_CTRL_PC31DOWNTO12_intermed_5 <= R_A_CTRL_PC31DOWNTO12_intermed_4;
R_E_CTRL_PC31DOWNTO12_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 12 );
R_E_CTRL_PC31DOWNTO12_intermed_2 <= R_E_CTRL_PC31DOWNTO12_intermed_1;
R_E_CTRL_PC31DOWNTO12_intermed_3 <= R_E_CTRL_PC31DOWNTO12_intermed_2;
R_E_CTRL_PC31DOWNTO12_intermed_4 <= R_E_CTRL_PC31DOWNTO12_intermed_3;
RIN_X_CTRL_PC31DOWNTO12_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 12 );
RIN_X_CTRL_PC31DOWNTO12_intermed_2 <= RIN_X_CTRL_PC31DOWNTO12_intermed_1;
RIN_X_CTRL_PC31DOWNTO12_intermed_3 <= RIN_X_CTRL_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_1 <= RIN.D.PC( 31 DOWNTO 12 );
RIN_D_PC31DOWNTO12_intermed_2 <= RIN_D_PC31DOWNTO12_intermed_1;
RIN_D_PC31DOWNTO12_intermed_3 <= RIN_D_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_4 <= RIN_D_PC31DOWNTO12_intermed_3;
RIN_D_PC31DOWNTO12_intermed_5 <= RIN_D_PC31DOWNTO12_intermed_4;
RIN_D_PC31DOWNTO12_intermed_6 <= RIN_D_PC31DOWNTO12_intermed_5;
RIN_D_PC31DOWNTO12_intermed_7 <= RIN_D_PC31DOWNTO12_intermed_6;
VIR_ADDR31DOWNTO12_shadow_intermed_1 <= VIR_ADDR31DOWNTO12_shadow;
VIR_ADDR31DOWNTO12_shadow_intermed_2 <= VIR_ADDR31DOWNTO12_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO12_shadow;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_D_INST0_shadow_intermed_1 <= V_D_INST0_shadow;
R_D_INST0_intermed_1 <= R.D.INST( 0 );
RIN_D_INST0_intermed_1 <= RIN.D.INST( 0 );
RIN_D_INST0_intermed_2 <= RIN_D_INST0_intermed_1;
V_D_INST1_shadow_intermed_1 <= V_D_INST1_shadow;
RIN_D_INST1_intermed_1 <= RIN.D.INST( 1 );
RIN_D_INST1_intermed_2 <= RIN_D_INST1_intermed_1;
R_D_INST1_intermed_1 <= R.D.INST( 1 );
V_X_DATA03_shadow_intermed_1 <= V_X_DATA03_shadow;
V_X_DATA03_shadow_intermed_2 <= V_X_DATA03_shadow_intermed_1;
V_X_DATA03_shadow_intermed_1 <= V_X_DATA03_shadow;
DCO_DATA03_intermed_1 <= DCO.DATA ( 0 )( 3 );
RIN_X_DATA03_intermed_1 <= RIN.X.DATA ( 0 )( 3 );
R_X_DATA03_intermed_1 <= R.X.DATA( 0 )( 3 );
R_X_DATA03_intermed_2 <= R_X_DATA03_intermed_1;
RIN_X_DATA03_intermed_1 <= RIN.X.DATA( 0 )( 3 );
RIN_X_DATA03_intermed_2 <= RIN_X_DATA03_intermed_1;
V_X_DATA03_shadow_intermed_1 <= V_X_DATA03_shadow;
R_X_DATA03_intermed_1 <= R.X.DATA( 0 )( 3 );
RIN_X_DATA03_intermed_1 <= RIN.X.DATA( 0 )( 3 );
RIN_X_DATA03_intermed_2 <= RIN_X_DATA03_intermed_1;
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST ( 20 );
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST( 20 );
RIN_A_CTRL_INST20_intermed_2 <= RIN_A_CTRL_INST20_intermed_1;
DE_INST20_shadow_intermed_1 <= DE_INST20_shadow;
DE_INST20_shadow_intermed_2 <= DE_INST20_shadow_intermed_1;
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
V_A_CTRL_INST20_shadow_intermed_2 <= V_A_CTRL_INST20_shadow_intermed_1;
R_A_CTRL_INST20_intermed_1 <= R.A.CTRL.INST( 20 );
R_A_CTRL_INST20_intermed_2 <= R_A_CTRL_INST20_intermed_1;
RIN_X_DATA00_intermed_1 <= RIN.X.DATA ( 0 )( 0 );
DCO_DATA00_intermed_1 <= DCO.DATA ( 0 )( 0 );
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
V_X_DATA00_shadow_intermed_2 <= V_X_DATA00_shadow_intermed_1;
RIN_X_DATA00_intermed_1 <= RIN.X.DATA( 0 )( 0 );
RIN_X_DATA00_intermed_2 <= RIN_X_DATA00_intermed_1;
R_X_DATA00_intermed_1 <= R.X.DATA( 0 )( 0 );
R_X_DATA00_intermed_2 <= R_X_DATA00_intermed_1;
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
V_X_DATA04DOWNTO0_shadow_intermed_2 <= V_X_DATA04DOWNTO0_shadow_intermed_1;
R_X_DATA04DOWNTO0_intermed_1 <= R.X.DATA( 0 )( 4 DOWNTO 0 );
R_X_DATA04DOWNTO0_intermed_2 <= R_X_DATA04DOWNTO0_intermed_1;
DCO_DATA04DOWNTO0_intermed_1 <= DCO.DATA ( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_2 <= RIN_X_DATA04DOWNTO0_intermed_1;
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA ( 0 )( 4 DOWNTO 0 );
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
V_A_CTRL_INST24_shadow_intermed_1 <= V_A_CTRL_INST24_shadow;
V_A_CTRL_INST24_shadow_intermed_2 <= V_A_CTRL_INST24_shadow_intermed_1;
DE_INST24_shadow_intermed_1 <= DE_INST24_shadow;
DE_INST24_shadow_intermed_2 <= DE_INST24_shadow_intermed_1;
R_A_CTRL_INST24_intermed_1 <= R.A.CTRL.INST( 24 );
R_A_CTRL_INST24_intermed_2 <= R_A_CTRL_INST24_intermed_1;
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST ( 24 );
V_A_CTRL_INST24_shadow_intermed_1 <= V_A_CTRL_INST24_shadow;
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST( 24 );
RIN_A_CTRL_INST24_intermed_2 <= RIN_A_CTRL_INST24_intermed_1;
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST( 20 );
RIN_A_CTRL_INST20_intermed_2 <= RIN_A_CTRL_INST20_intermed_1;
DE_INST20_shadow_intermed_1 <= DE_INST20_shadow;
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
R_A_CTRL_INST20_intermed_1 <= R.A.CTRL.INST( 20 );
V_A_CTRL_INST24_shadow_intermed_1 <= V_A_CTRL_INST24_shadow;
DE_INST24_shadow_intermed_1 <= DE_INST24_shadow;
R_A_CTRL_INST24_intermed_1 <= R.A.CTRL.INST( 24 );
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST( 24 );
RIN_A_CTRL_INST24_intermed_2 <= RIN_A_CTRL_INST24_intermed_1;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1;
R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
R_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= R_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 );
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
RIN_F_PC_intermed_1 <= RIN.F.PC;
EX_ADD_RES32DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO3_shadow;
XC_TRAP_ADDRESS_shadow_intermed_1 <= XC_TRAP_ADDRESS_shadow;
EX_JUMP_ADDRESS_shadow_intermed_1 <= EX_JUMP_ADDRESS_shadow;
V_F_PC_shadow_intermed_1 <= V_F_PC_shadow;
RIN_A_RFE1_intermed_1 <= RIN.A.RFE1;
V_A_RFE1_shadow_intermed_1 <= V_A_RFE1_shadow;
RIN_A_RFE2_intermed_1 <= RIN.A.RFE2;
V_A_RFE2_shadow_intermed_1 <= V_A_RFE2_shadow;
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
V_X_DATA0_shadow_intermed_2 <= V_X_DATA0_shadow_intermed_1;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA ( 0 );
V_E_OP1_shadow_intermed_1 <= V_E_OP1_shadow;
V_E_OP2_shadow_intermed_1 <= V_E_OP2_shadow;
RIN_E_OP2_intermed_1 <= RIN.E.OP2;
RIN_E_OP1_intermed_1 <= RIN.E.OP1;
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
V_E_ALUCIN_shadow_intermed_1 <= V_E_ALUCIN_shadow;
R_X_DATA0_intermed_1 <= R.X.DATA( 0 );
RIN_E_ALUCIN_intermed_1 <= RIN.E.ALUCIN;
DCO_DATA0_intermed_1 <= DCO.DATA ( 0 );
RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 );
RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1;
RIN_X_DATA00_intermed_1 <= RIN.X.DATA ( 0 )( 0 );
RIN_X_DATA00_intermed_2 <= RIN_X_DATA00_intermed_1;
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
DCO_DATA00_intermed_1 <= DCO.DATA ( 0 )( 0 );
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
V_X_DATA00_shadow_intermed_2 <= V_X_DATA00_shadow_intermed_1;
V_E_YMSB_shadow_intermed_1 <= V_E_YMSB_shadow;
RIN_X_DATA00_intermed_1 <= RIN.X.DATA ( 0 ) ( 0 );
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
V_X_DATA00_shadow_intermed_2 <= V_X_DATA00_shadow_intermed_1;
V_X_DATA00_shadow_intermed_3 <= V_X_DATA00_shadow_intermed_2;
R_X_DATA00_intermed_1 <= R.X.DATA ( 0 )( 0 );
RIN_X_DATA00_intermed_1 <= RIN.X.DATA( 0 )( 0 );
RIN_X_DATA00_intermed_2 <= RIN_X_DATA00_intermed_1;
RIN_X_DATA00_intermed_3 <= RIN_X_DATA00_intermed_2;
R_X_DATA00_intermed_1 <= R.X.DATA( 0 )( 0 );
R_X_DATA00_intermed_2 <= R_X_DATA00_intermed_1;
RIN_E_YMSB_intermed_1 <= RIN.E.YMSB;
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
V_X_DATA0_shadow_intermed_2 <= V_X_DATA0_shadow_intermed_1;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA ( 0 );
V_E_OP1_shadow_intermed_1 <= V_E_OP1_shadow;
RIN_E_OP1_intermed_1 <= RIN.E.OP1;
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
R_X_DATA0_intermed_1 <= R.X.DATA( 0 );
DCO_DATA0_intermed_1 <= DCO.DATA ( 0 );
RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 );
RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1;
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
V_X_DATA0_shadow_intermed_2 <= V_X_DATA0_shadow_intermed_1;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA ( 0 );
V_E_OP2_shadow_intermed_1 <= V_E_OP2_shadow;
RIN_E_OP2_intermed_1 <= RIN.E.OP2;
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
R_X_DATA0_intermed_1 <= R.X.DATA( 0 );
DCO_DATA0_intermed_1 <= DCO.DATA ( 0 );
RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 );
RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1;
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA ( 0 ) ( 4 DOWNTO 0 );
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
V_X_DATA04DOWNTO0_shadow_intermed_2 <= V_X_DATA04DOWNTO0_shadow_intermed_1;
V_X_DATA04DOWNTO0_shadow_intermed_3 <= V_X_DATA04DOWNTO0_shadow_intermed_2;
R_X_DATA04DOWNTO0_intermed_1 <= R.X.DATA( 0 )( 4 DOWNTO 0 );
R_X_DATA04DOWNTO0_intermed_2 <= R_X_DATA04DOWNTO0_intermed_1;
V_E_SHCNT_shadow_intermed_1 <= V_E_SHCNT_shadow;
R_X_DATA04DOWNTO0_intermed_1 <= R.X.DATA ( 0 )( 4 DOWNTO 0 );
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_2 <= RIN_X_DATA04DOWNTO0_intermed_1;
RIN_X_DATA04DOWNTO0_intermed_3 <= RIN_X_DATA04DOWNTO0_intermed_2;
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA ( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_2 <= RIN_X_DATA04DOWNTO0_intermed_1;
DCO_DATA04DOWNTO0_intermed_1 <= DCO.DATA ( 0 )( 4 DOWNTO 0 );
RIN_E_SHCNT_intermed_1 <= RIN.E.SHCNT;
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
V_X_DATA04DOWNTO0_shadow_intermed_2 <= V_X_DATA04DOWNTO0_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
DE_INST19_shadow_intermed_2 <= DE_INST19_shadow_intermed_1;
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
V_A_CTRL_INST20_shadow_intermed_2 <= V_A_CTRL_INST20_shadow_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_A_CTRL_INST19_shadow_intermed_3 <= V_A_CTRL_INST19_shadow_intermed_2;
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST ( 20 );
RIN_A_CTRL_INST20_intermed_2 <= RIN_A_CTRL_INST20_intermed_1;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
V_X_DATA031_shadow_intermed_3 <= V_X_DATA031_shadow_intermed_2;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_CTRL_INST19_shadow_intermed_2 <= V_E_CTRL_INST19_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
RIN_X_DATA031_intermed_3 <= RIN_X_DATA031_intermed_2;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 ) ( 31 );
V_E_SARI_shadow_intermed_1 <= V_E_SARI_shadow;
R_E_CTRL_INST19_intermed_1 <= R.E.CTRL.INST( 19 );
DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 );
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
R_X_DATA031_intermed_2 <= R_X_DATA031_intermed_1;
RIN_E_CTRL_INST20_intermed_1 <= RIN.E.CTRL.INST ( 20 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
R_E_CTRL_INST20_intermed_1 <= R.E.CTRL.INST( 20 );
R_A_CTRL_INST20_intermed_1 <= R.A.CTRL.INST ( 20 );
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST( 20 );
RIN_A_CTRL_INST20_intermed_2 <= RIN_A_CTRL_INST20_intermed_1;
RIN_A_CTRL_INST20_intermed_3 <= RIN_A_CTRL_INST20_intermed_2;
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
R_A_CTRL_INST19_intermed_2 <= R_A_CTRL_INST19_intermed_1;
V_E_CTRL_INST20_shadow_intermed_1 <= V_E_CTRL_INST20_shadow;
V_E_CTRL_INST20_shadow_intermed_2 <= V_E_CTRL_INST20_shadow_intermed_1;
V_E_CTRL_INST20_shadow_intermed_1 <= V_E_CTRL_INST20_shadow;
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST ( 19 );
DE_INST20_shadow_intermed_1 <= DE_INST20_shadow;
DE_INST20_shadow_intermed_2 <= DE_INST20_shadow_intermed_1;
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
RIN_A_CTRL_INST19_intermed_3 <= RIN_A_CTRL_INST19_intermed_2;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST ( 19 );
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
V_A_CTRL_INST20_shadow_intermed_2 <= V_A_CTRL_INST20_shadow_intermed_1;
V_A_CTRL_INST20_shadow_intermed_3 <= V_A_CTRL_INST20_shadow_intermed_2;
R_X_DATA031_intermed_1 <= R.X.DATA ( 0 )( 31 );
RIN_E_SARI_intermed_1 <= RIN.E.SARI;
RIN_E_CTRL_INST20_intermed_1 <= RIN.E.CTRL.INST( 20 );
RIN_E_CTRL_INST20_intermed_2 <= RIN_E_CTRL_INST20_intermed_1;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST( 19 );
RIN_E_CTRL_INST19_intermed_2 <= RIN_E_CTRL_INST19_intermed_1;
R_A_CTRL_INST20_intermed_1 <= R.A.CTRL.INST( 20 );
R_A_CTRL_INST20_intermed_2 <= R_A_CTRL_INST20_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_M_DCI_SIGNED_shadow_intermed_1 <= V_M_DCI_SIGNED_shadow;
V_M_DCI_SIGNED_shadow_intermed_2 <= V_M_DCI_SIGNED_shadow_intermed_1;
RIN_M_DCI_SIGNED_intermed_1 <= RIN.M.DCI.SIGNED;
RIN_M_DCI_SIGNED_intermed_2 <= RIN_M_DCI_SIGNED_intermed_1;
R_M_DCI_SIGNED_intermed_1 <= R.M.DCI.SIGNED;
V_X_DCI_SIGNED_shadow_intermed_1 <= V_X_DCI_SIGNED_shadow;
RIN_X_DCI_SIGNED_intermed_1 <= RIN.X.DCI.SIGNED;
RIN_M_DCI_SIZE_intermed_1 <= RIN.M.DCI.SIZE;
RIN_M_DCI_SIZE_intermed_2 <= RIN_M_DCI_SIZE_intermed_1;
V_M_DCI_SIZE_shadow_intermed_1 <= V_M_DCI_SIZE_shadow;
V_M_DCI_SIZE_shadow_intermed_2 <= V_M_DCI_SIZE_shadow_intermed_1;
R_M_DCI_SIZE_intermed_1 <= R.M.DCI.SIZE;
V_X_DCI_SIZE_shadow_intermed_1 <= V_X_DCI_SIZE_shadow;
RIN_X_DCI_SIZE_intermed_1 <= RIN.X.DCI.SIZE;
V_M_RESULT1DOWNTO0_shadow_intermed_1 <= V_M_RESULT1DOWNTO0_shadow;
V_M_RESULT1DOWNTO0_shadow_intermed_2 <= V_M_RESULT1DOWNTO0_shadow_intermed_1;
V_M_RESULT1DOWNTO0_shadow_intermed_3 <= V_M_RESULT1DOWNTO0_shadow_intermed_2;
RIN_X_LADDR_intermed_1 <= RIN.X.LADDR;
R_M_RESULT1DOWNTO0_intermed_1 <= R.M.RESULT ( 1 DOWNTO 0 );
RIN_M_RESULT1DOWNTO0_intermed_1 <= RIN.M.RESULT ( 1 DOWNTO 0 );
RIN_M_RESULT1DOWNTO0_intermed_2 <= RIN_M_RESULT1DOWNTO0_intermed_1;
RIN_M_RESULT1DOWNTO0_intermed_1 <= RIN.M.RESULT( 1 DOWNTO 0 );
RIN_M_RESULT1DOWNTO0_intermed_2 <= RIN_M_RESULT1DOWNTO0_intermed_1;
RIN_M_RESULT1DOWNTO0_intermed_3 <= RIN_M_RESULT1DOWNTO0_intermed_2;
V_M_RESULT1DOWNTO0_shadow_intermed_1 <= V_M_RESULT1DOWNTO0_shadow;
V_M_RESULT1DOWNTO0_shadow_intermed_2 <= V_M_RESULT1DOWNTO0_shadow_intermed_1;
V_X_LADDR_shadow_intermed_1 <= V_X_LADDR_shadow;
R_M_RESULT1DOWNTO0_intermed_1 <= R.M.RESULT( 1 DOWNTO 0 );
R_M_RESULT1DOWNTO0_intermed_2 <= R_M_RESULT1DOWNTO0_intermed_1;
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
V_X_DATA0_shadow_intermed_2 <= V_X_DATA0_shadow_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
RIN_X_RESULT_intermed_1 <= RIN.X.RESULT;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA ( 0 );
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC ( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
V_X_RESULT_shadow_intermed_1 <= V_X_RESULT_shadow;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC ( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC ( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC ( 31 DOWNTO 2 );
R_X_DATA0_intermed_1 <= R.X.DATA( 0 );
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC ( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC ( 31 DOWNTO 2 );
DCO_DATA0_intermed_1 <= DCO.DATA ( 0 );
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 );
RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
V_X_ANNUL_ALL_shadow_intermed_2 <= V_X_ANNUL_ALL_shadow_intermed_1;
V_X_ANNUL_ALL_shadow_intermed_3 <= V_X_ANNUL_ALL_shadow_intermed_2;
V_X_ANNUL_ALL_shadow_intermed_4 <= V_X_ANNUL_ALL_shadow_intermed_3;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2;
RIN_A_CTRL_ANNUL_intermed_4 <= RIN_A_CTRL_ANNUL_intermed_3;
RIN_A_CTRL_ANNUL_intermed_5 <= RIN_A_CTRL_ANNUL_intermed_4;
R_M_CTRL_WREG_intermed_1 <= R.M.CTRL.WREG;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1;
R_A_CTRL_ANNUL_intermed_3 <= R_A_CTRL_ANNUL_intermed_2;
R_A_CTRL_ANNUL_intermed_4 <= R_A_CTRL_ANNUL_intermed_3;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
RIN_X_ANNUL_ALL_intermed_3 <= RIN_X_ANNUL_ALL_intermed_2;
RIN_X_ANNUL_ALL_intermed_4 <= RIN_X_ANNUL_ALL_intermed_3;
RIN_X_ANNUL_ALL_intermed_5 <= RIN_X_ANNUL_ALL_intermed_4;
V_M_CTRL_WREG_shadow_intermed_1 <= V_M_CTRL_WREG_shadow;
V_M_CTRL_WREG_shadow_intermed_2 <= V_M_CTRL_WREG_shadow_intermed_1;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
R_X_ANNUL_ALL_intermed_2 <= R_X_ANNUL_ALL_intermed_1;
R_X_ANNUL_ALL_intermed_3 <= R_X_ANNUL_ALL_intermed_2;
R_X_ANNUL_ALL_intermed_4 <= R_X_ANNUL_ALL_intermed_3;
V_X_CTRL_WREG_shadow_intermed_1 <= V_X_CTRL_WREG_shadow;
R_E_CTRL_WREG_intermed_1 <= R.E.CTRL.WREG;
R_E_CTRL_WREG_intermed_2 <= R_E_CTRL_WREG_intermed_1;
RIN_X_CTRL_WREG_intermed_1 <= RIN.X.CTRL.WREG;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_3 <= V_A_CTRL_ANNUL_shadow_intermed_2;
V_A_CTRL_ANNUL_shadow_intermed_4 <= V_A_CTRL_ANNUL_shadow_intermed_3;
RIN_E_CTRL_WREG_intermed_1 <= RIN.E.CTRL.WREG;
RIN_E_CTRL_WREG_intermed_2 <= RIN_E_CTRL_WREG_intermed_1;
RIN_E_CTRL_WREG_intermed_3 <= RIN_E_CTRL_WREG_intermed_2;
RIN_M_CTRL_WREG_intermed_1 <= RIN.M.CTRL.WREG;
RIN_M_CTRL_WREG_intermed_2 <= RIN_M_CTRL_WREG_intermed_1;
V_E_CTRL_WREG_shadow_intermed_1 <= V_E_CTRL_WREG_shadow;
V_E_CTRL_WREG_shadow_intermed_2 <= V_E_CTRL_WREG_shadow_intermed_1;
V_E_CTRL_WREG_shadow_intermed_3 <= V_E_CTRL_WREG_shadow_intermed_2;
RIN_A_CTRL_WREG_intermed_1 <= RIN.A.CTRL.WREG;
RIN_A_CTRL_WREG_intermed_2 <= RIN_A_CTRL_WREG_intermed_1;
RIN_A_CTRL_WREG_intermed_3 <= RIN_A_CTRL_WREG_intermed_2;
RIN_A_CTRL_WREG_intermed_4 <= RIN_A_CTRL_WREG_intermed_3;
V_A_CTRL_WREG_shadow_intermed_1 <= V_A_CTRL_WREG_shadow;
V_A_CTRL_WREG_shadow_intermed_2 <= V_A_CTRL_WREG_shadow_intermed_1;
V_A_CTRL_WREG_shadow_intermed_3 <= V_A_CTRL_WREG_shadow_intermed_2;
V_A_CTRL_WREG_shadow_intermed_4 <= V_A_CTRL_WREG_shadow_intermed_3;
R_A_CTRL_WREG_intermed_1 <= R.A.CTRL.WREG;
R_A_CTRL_WREG_intermed_2 <= R_A_CTRL_WREG_intermed_1;
R_A_CTRL_WREG_intermed_3 <= R_A_CTRL_WREG_intermed_2;
V_E_CTRL_TT_shadow_intermed_1 <= V_E_CTRL_TT_shadow;
V_E_CTRL_TT_shadow_intermed_2 <= V_E_CTRL_TT_shadow_intermed_1;
V_E_CTRL_TT_shadow_intermed_3 <= V_E_CTRL_TT_shadow_intermed_2;
V_X_CTRL_TT_shadow_intermed_1 <= V_X_CTRL_TT_shadow;
V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow;
V_X_RESULT6DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO0_shadow_intermed_1;
RIN_A_CTRL_TT_intermed_1 <= RIN.A.CTRL.TT;
RIN_A_CTRL_TT_intermed_2 <= RIN_A_CTRL_TT_intermed_1;
RIN_A_CTRL_TT_intermed_3 <= RIN_A_CTRL_TT_intermed_2;
RIN_A_CTRL_TT_intermed_4 <= RIN_A_CTRL_TT_intermed_3;
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 );
RIN_X_RESULT6DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO0_intermed_1;
RIN_E_CTRL_TT_intermed_1 <= RIN.E.CTRL.TT;
RIN_E_CTRL_TT_intermed_2 <= RIN_E_CTRL_TT_intermed_1;
RIN_E_CTRL_TT_intermed_3 <= RIN_E_CTRL_TT_intermed_2;
V_M_CTRL_TT_shadow_intermed_1 <= V_M_CTRL_TT_shadow;
V_M_CTRL_TT_shadow_intermed_2 <= V_M_CTRL_TT_shadow_intermed_1;
R_X_RESULT6DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 );
R_A_CTRL_TT_intermed_1 <= R.A.CTRL.TT;
R_A_CTRL_TT_intermed_2 <= R_A_CTRL_TT_intermed_1;
R_A_CTRL_TT_intermed_3 <= R_A_CTRL_TT_intermed_2;
V_A_CTRL_TT_shadow_intermed_1 <= V_A_CTRL_TT_shadow;
V_A_CTRL_TT_shadow_intermed_2 <= V_A_CTRL_TT_shadow_intermed_1;
V_A_CTRL_TT_shadow_intermed_3 <= V_A_CTRL_TT_shadow_intermed_2;
V_A_CTRL_TT_shadow_intermed_4 <= V_A_CTRL_TT_shadow_intermed_3;
R_M_CTRL_TT_intermed_1 <= R.M.CTRL.TT;
RIN_X_CTRL_TT_intermed_1 <= RIN.X.CTRL.TT;
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 );
R_E_CTRL_TT_intermed_1 <= R.E.CTRL.TT;
R_E_CTRL_TT_intermed_2 <= R_E_CTRL_TT_intermed_1;
RIN_M_CTRL_TT_intermed_1 <= RIN.M.CTRL.TT;
RIN_M_CTRL_TT_intermed_2 <= RIN_M_CTRL_TT_intermed_1;
V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow;
V_M_CTRL_TRAP_shadow_intermed_1 <= V_M_CTRL_TRAP_shadow;
V_M_CTRL_TRAP_shadow_intermed_2 <= V_M_CTRL_TRAP_shadow_intermed_1;
RIN_X_CTRL_TRAP_intermed_1 <= RIN.X.CTRL.TRAP;
V_X_CTRL_TRAP_shadow_intermed_1 <= V_X_CTRL_TRAP_shadow;
V_A_CTRL_TRAP_shadow_intermed_1 <= V_A_CTRL_TRAP_shadow;
V_A_CTRL_TRAP_shadow_intermed_2 <= V_A_CTRL_TRAP_shadow_intermed_1;
V_A_CTRL_TRAP_shadow_intermed_3 <= V_A_CTRL_TRAP_shadow_intermed_2;
V_A_CTRL_TRAP_shadow_intermed_4 <= V_A_CTRL_TRAP_shadow_intermed_3;
V_X_MEXC_shadow_intermed_1 <= V_X_MEXC_shadow;
V_D_MEXC_shadow_intermed_1 <= V_D_MEXC_shadow;
V_D_MEXC_shadow_intermed_2 <= V_D_MEXC_shadow_intermed_1;
V_D_MEXC_shadow_intermed_3 <= V_D_MEXC_shadow_intermed_2;
V_D_MEXC_shadow_intermed_4 <= V_D_MEXC_shadow_intermed_3;
V_D_MEXC_shadow_intermed_5 <= V_D_MEXC_shadow_intermed_4;
R_A_CTRL_TRAP_intermed_1 <= R.A.CTRL.TRAP;
R_A_CTRL_TRAP_intermed_2 <= R_A_CTRL_TRAP_intermed_1;
R_A_CTRL_TRAP_intermed_3 <= R_A_CTRL_TRAP_intermed_2;
RIN_X_MEXC_intermed_1 <= RIN.X.MEXC;
RIN_M_CTRL_TRAP_intermed_1 <= RIN.M.CTRL.TRAP;
RIN_M_CTRL_TRAP_intermed_2 <= RIN_M_CTRL_TRAP_intermed_1;
R_M_CTRL_TRAP_intermed_1 <= R.M.CTRL.TRAP;
ICO_MEXC_intermed_1 <= ICO.MEXC;
ICO_MEXC_intermed_2 <= ICO_MEXC_intermed_1;
ICO_MEXC_intermed_3 <= ICO_MEXC_intermed_2;
ICO_MEXC_intermed_4 <= ICO_MEXC_intermed_3;
ICO_MEXC_intermed_5 <= ICO_MEXC_intermed_4;
R_E_CTRL_TRAP_intermed_1 <= R.E.CTRL.TRAP;
R_E_CTRL_TRAP_intermed_2 <= R_E_CTRL_TRAP_intermed_1;
RIN_A_CTRL_TRAP_intermed_1 <= RIN.A.CTRL.TRAP;
RIN_A_CTRL_TRAP_intermed_2 <= RIN_A_CTRL_TRAP_intermed_1;
RIN_A_CTRL_TRAP_intermed_3 <= RIN_A_CTRL_TRAP_intermed_2;
RIN_A_CTRL_TRAP_intermed_4 <= RIN_A_CTRL_TRAP_intermed_3;
V_E_CTRL_TRAP_shadow_intermed_1 <= V_E_CTRL_TRAP_shadow;
V_E_CTRL_TRAP_shadow_intermed_2 <= V_E_CTRL_TRAP_shadow_intermed_1;
V_E_CTRL_TRAP_shadow_intermed_3 <= V_E_CTRL_TRAP_shadow_intermed_2;
RIN_E_CTRL_TRAP_intermed_1 <= RIN.E.CTRL.TRAP;
RIN_E_CTRL_TRAP_intermed_2 <= RIN_E_CTRL_TRAP_intermed_1;
RIN_E_CTRL_TRAP_intermed_3 <= RIN_E_CTRL_TRAP_intermed_2;
RIN_D_MEXC_intermed_1 <= RIN.D.MEXC;
RIN_D_MEXC_intermed_2 <= RIN_D_MEXC_intermed_1;
RIN_D_MEXC_intermed_3 <= RIN_D_MEXC_intermed_2;
RIN_D_MEXC_intermed_4 <= RIN_D_MEXC_intermed_3;
RIN_D_MEXC_intermed_5 <= RIN_D_MEXC_intermed_4;
R_D_MEXC_intermed_1 <= R.D.MEXC;
R_D_MEXC_intermed_2 <= R_D_MEXC_intermed_1;
R_D_MEXC_intermed_3 <= R_D_MEXC_intermed_2;
R_D_MEXC_intermed_4 <= R_D_MEXC_intermed_3;
DCO_MEXC_intermed_1 <= DCO.MEXC;
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_CTRL_INST19_shadow_intermed_2 <= V_E_CTRL_INST19_shadow_intermed_1;
R_E_CTRL_INST19_intermed_1 <= R.E.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 );
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST ( 19 );
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST( 19 );
RIN_E_CTRL_INST19_intermed_2 <= RIN_E_CTRL_INST19_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
VP_ERROR_shadow_intermed_1 <= VP_ERROR_shadow;
RPIN_PWD_intermed_1 <= RPIN.PWD;
V_X_DEBUG_shadow_intermed_1 <= V_X_DEBUG_shadow;
VP_PWD_shadow_intermed_1 <= VP_PWD_shadow;
RPIN_ERROR_intermed_1 <= RPIN.ERROR;
RIN_X_DEBUG_intermed_1 <= RIN.X.DEBUG;
VP_ERROR_shadow_intermed_1 <= VP_ERROR_shadow;
RIN_X_NERROR_intermed_1 <= RIN.X.NERROR;
RPIN_ERROR_intermed_1 <= RPIN.ERROR;
V_F_PC31DOWNTO4_shadow_intermed_1 <= V_F_PC31DOWNTO4_shadow;
V_X_CTRL_TT_shadow_intermed_1 <= V_X_CTRL_TT_shadow;
V_E_CTRL_TT_shadow_intermed_1 <= V_E_CTRL_TT_shadow;
V_E_CTRL_TT_shadow_intermed_2 <= V_E_CTRL_TT_shadow_intermed_1;
V_E_CTRL_TT_shadow_intermed_3 <= V_E_CTRL_TT_shadow_intermed_2;
RIN_A_CTRL_TT_intermed_1 <= RIN.A.CTRL.TT;
RIN_A_CTRL_TT_intermed_2 <= RIN_A_CTRL_TT_intermed_1;
RIN_A_CTRL_TT_intermed_3 <= RIN_A_CTRL_TT_intermed_2;
RIN_A_CTRL_TT_intermed_4 <= RIN_A_CTRL_TT_intermed_3;
V_X_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO4_shadow;
V_X_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO4_shadow_intermed_2;
IR_ADDR31DOWNTO4_intermed_1 <= IR.ADDR( 31 DOWNTO 4 );
R_A_CTRL_TT_intermed_1 <= R.A.CTRL.TT;
R_A_CTRL_TT_intermed_2 <= R_A_CTRL_TT_intermed_1;
R_A_CTRL_TT_intermed_3 <= R_A_CTRL_TT_intermed_2;
R_M_CTRL_TT_intermed_1 <= R.M.CTRL.TT;
RIN_F_PC31DOWNTO4_intermed_1 <= RIN.F.PC( 31 DOWNTO 4 );
VIR_ADDR31DOWNTO4_shadow_intermed_1 <= VIR_ADDR31DOWNTO4_shadow;
VIR_ADDR31DOWNTO4_shadow_intermed_2 <= VIR_ADDR31DOWNTO4_shadow_intermed_1;
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 );
R_E_CTRL_TT_intermed_1 <= R.E.CTRL.TT;
R_E_CTRL_TT_intermed_2 <= R_E_CTRL_TT_intermed_1;
R_A_CTRL_PC31DOWNTO4_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 4 );
R_A_CTRL_PC31DOWNTO4_intermed_2 <= R_A_CTRL_PC31DOWNTO4_intermed_1;
R_A_CTRL_PC31DOWNTO4_intermed_3 <= R_A_CTRL_PC31DOWNTO4_intermed_2;
R_A_CTRL_PC31DOWNTO4_intermed_4 <= R_A_CTRL_PC31DOWNTO4_intermed_3;
R_A_CTRL_PC31DOWNTO4_intermed_5 <= R_A_CTRL_PC31DOWNTO4_intermed_4;
RIN_A_CTRL_PC31DOWNTO4_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 4 );
RIN_A_CTRL_PC31DOWNTO4_intermed_2 <= RIN_A_CTRL_PC31DOWNTO4_intermed_1;
RIN_A_CTRL_PC31DOWNTO4_intermed_3 <= RIN_A_CTRL_PC31DOWNTO4_intermed_2;
RIN_A_CTRL_PC31DOWNTO4_intermed_4 <= RIN_A_CTRL_PC31DOWNTO4_intermed_3;
RIN_A_CTRL_PC31DOWNTO4_intermed_5 <= RIN_A_CTRL_PC31DOWNTO4_intermed_4;
RIN_A_CTRL_PC31DOWNTO4_intermed_6 <= RIN_A_CTRL_PC31DOWNTO4_intermed_5;
R_D_PC31DOWNTO4_intermed_1 <= R.D.PC( 31 DOWNTO 4 );
R_D_PC31DOWNTO4_intermed_2 <= R_D_PC31DOWNTO4_intermed_1;
R_D_PC31DOWNTO4_intermed_3 <= R_D_PC31DOWNTO4_intermed_2;
R_D_PC31DOWNTO4_intermed_4 <= R_D_PC31DOWNTO4_intermed_3;
R_D_PC31DOWNTO4_intermed_5 <= R_D_PC31DOWNTO4_intermed_4;
R_D_PC31DOWNTO4_intermed_6 <= R_D_PC31DOWNTO4_intermed_5;
RIN_X_CTRL_PC31DOWNTO4_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 4 );
RIN_X_CTRL_PC31DOWNTO4_intermed_2 <= RIN_X_CTRL_PC31DOWNTO4_intermed_1;
RIN_X_CTRL_PC31DOWNTO4_intermed_3 <= RIN_X_CTRL_PC31DOWNTO4_intermed_2;
EX_ADD_RES32DOWNTO332DOWNTO5_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO5_shadow;
V_W_S_TBA_shadow_intermed_1 <= V_W_S_TBA_shadow;
RIN_M_CTRL_TT_intermed_1 <= RIN.M.CTRL.TT;
RIN_M_CTRL_TT_intermed_2 <= RIN_M_CTRL_TT_intermed_1;
RIN_M_CTRL_PC31DOWNTO4_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 4 );
RIN_M_CTRL_PC31DOWNTO4_intermed_2 <= RIN_M_CTRL_PC31DOWNTO4_intermed_1;
RIN_M_CTRL_PC31DOWNTO4_intermed_3 <= RIN_M_CTRL_PC31DOWNTO4_intermed_2;
RIN_M_CTRL_PC31DOWNTO4_intermed_4 <= RIN_M_CTRL_PC31DOWNTO4_intermed_3;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO4_shadow;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_4;
V_D_PC31DOWNTO4_shadow_intermed_1 <= V_D_PC31DOWNTO4_shadow;
V_D_PC31DOWNTO4_shadow_intermed_2 <= V_D_PC31DOWNTO4_shadow_intermed_1;
V_D_PC31DOWNTO4_shadow_intermed_3 <= V_D_PC31DOWNTO4_shadow_intermed_2;
V_D_PC31DOWNTO4_shadow_intermed_4 <= V_D_PC31DOWNTO4_shadow_intermed_3;
V_D_PC31DOWNTO4_shadow_intermed_5 <= V_D_PC31DOWNTO4_shadow_intermed_4;
V_D_PC31DOWNTO4_shadow_intermed_6 <= V_D_PC31DOWNTO4_shadow_intermed_5;
V_D_PC31DOWNTO4_shadow_intermed_7 <= V_D_PC31DOWNTO4_shadow_intermed_6;
V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow;
R_X_CTRL_PC31DOWNTO4_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 4 );
R_X_CTRL_PC31DOWNTO4_intermed_2 <= R_X_CTRL_PC31DOWNTO4_intermed_1;
V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow;
V_X_RESULT6DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO0_shadow_intermed_1;
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 );
RIN_X_RESULT6DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO0_intermed_1;
RIN_E_CTRL_TT_intermed_1 <= RIN.E.CTRL.TT;
RIN_E_CTRL_TT_intermed_2 <= RIN_E_CTRL_TT_intermed_1;
RIN_E_CTRL_TT_intermed_3 <= RIN_E_CTRL_TT_intermed_2;
R_X_RESULT6DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 );
V_M_CTRL_TT_shadow_intermed_1 <= V_M_CTRL_TT_shadow;
V_M_CTRL_TT_shadow_intermed_2 <= V_M_CTRL_TT_shadow_intermed_1;
IRIN_ADDR31DOWNTO4_intermed_1 <= IRIN.ADDR( 31 DOWNTO 4 );
IRIN_ADDR31DOWNTO4_intermed_2 <= IRIN_ADDR31DOWNTO4_intermed_1;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO4_shadow;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_3;
V_A_CTRL_TT_shadow_intermed_1 <= V_A_CTRL_TT_shadow;
V_A_CTRL_TT_shadow_intermed_2 <= V_A_CTRL_TT_shadow_intermed_1;
V_A_CTRL_TT_shadow_intermed_3 <= V_A_CTRL_TT_shadow_intermed_2;
V_A_CTRL_TT_shadow_intermed_4 <= V_A_CTRL_TT_shadow_intermed_3;
XC_TRAP_ADDRESS31DOWNTO4_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO4_shadow;
R_M_CTRL_PC31DOWNTO4_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 4 );
R_M_CTRL_PC31DOWNTO4_intermed_2 <= R_M_CTRL_PC31DOWNTO4_intermed_1;
R_M_CTRL_PC31DOWNTO4_intermed_3 <= R_M_CTRL_PC31DOWNTO4_intermed_2;
RIN_X_CTRL_TT_intermed_1 <= RIN.X.CTRL.TT;
RIN_D_PC31DOWNTO4_intermed_1 <= RIN.D.PC( 31 DOWNTO 4 );
RIN_D_PC31DOWNTO4_intermed_2 <= RIN_D_PC31DOWNTO4_intermed_1;
RIN_D_PC31DOWNTO4_intermed_3 <= RIN_D_PC31DOWNTO4_intermed_2;
RIN_D_PC31DOWNTO4_intermed_4 <= RIN_D_PC31DOWNTO4_intermed_3;
RIN_D_PC31DOWNTO4_intermed_5 <= RIN_D_PC31DOWNTO4_intermed_4;
RIN_D_PC31DOWNTO4_intermed_6 <= RIN_D_PC31DOWNTO4_intermed_5;
RIN_D_PC31DOWNTO4_intermed_7 <= RIN_D_PC31DOWNTO4_intermed_6;
RIN_E_CTRL_PC31DOWNTO4_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 4 );
RIN_E_CTRL_PC31DOWNTO4_intermed_2 <= RIN_E_CTRL_PC31DOWNTO4_intermed_1;
RIN_E_CTRL_PC31DOWNTO4_intermed_3 <= RIN_E_CTRL_PC31DOWNTO4_intermed_2;
RIN_E_CTRL_PC31DOWNTO4_intermed_4 <= RIN_E_CTRL_PC31DOWNTO4_intermed_3;
RIN_E_CTRL_PC31DOWNTO4_intermed_5 <= RIN_E_CTRL_PC31DOWNTO4_intermed_4;
EX_JUMP_ADDRESS31DOWNTO4_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO4_shadow;
RIN_W_S_TBA_intermed_1 <= RIN.W.S.TBA;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO4_shadow;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_5;
R_E_CTRL_PC31DOWNTO4_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 4 );
R_E_CTRL_PC31DOWNTO4_intermed_2 <= R_E_CTRL_PC31DOWNTO4_intermed_1;
R_E_CTRL_PC31DOWNTO4_intermed_3 <= R_E_CTRL_PC31DOWNTO4_intermed_2;
R_E_CTRL_PC31DOWNTO4_intermed_4 <= R_E_CTRL_PC31DOWNTO4_intermed_3;
R_D_PC3DOWNTO2_intermed_1 <= R.D.PC( 3 DOWNTO 2 );
R_D_PC3DOWNTO2_intermed_2 <= R_D_PC3DOWNTO2_intermed_1;
R_D_PC3DOWNTO2_intermed_3 <= R_D_PC3DOWNTO2_intermed_2;
R_D_PC3DOWNTO2_intermed_4 <= R_D_PC3DOWNTO2_intermed_3;
R_D_PC3DOWNTO2_intermed_5 <= R_D_PC3DOWNTO2_intermed_4;
R_D_PC3DOWNTO2_intermed_6 <= R_D_PC3DOWNTO2_intermed_5;
V_D_PC3DOWNTO2_shadow_intermed_1 <= V_D_PC3DOWNTO2_shadow;
V_D_PC3DOWNTO2_shadow_intermed_2 <= V_D_PC3DOWNTO2_shadow_intermed_1;
V_D_PC3DOWNTO2_shadow_intermed_3 <= V_D_PC3DOWNTO2_shadow_intermed_2;
V_D_PC3DOWNTO2_shadow_intermed_4 <= V_D_PC3DOWNTO2_shadow_intermed_3;
V_D_PC3DOWNTO2_shadow_intermed_5 <= V_D_PC3DOWNTO2_shadow_intermed_4;
V_D_PC3DOWNTO2_shadow_intermed_6 <= V_D_PC3DOWNTO2_shadow_intermed_5;
V_D_PC3DOWNTO2_shadow_intermed_7 <= V_D_PC3DOWNTO2_shadow_intermed_6;
VIR_ADDR3DOWNTO2_shadow_intermed_1 <= VIR_ADDR3DOWNTO2_shadow;
VIR_ADDR3DOWNTO2_shadow_intermed_2 <= VIR_ADDR3DOWNTO2_shadow_intermed_1;
RIN_D_PC3DOWNTO2_intermed_1 <= RIN.D.PC( 3 DOWNTO 2 );
RIN_D_PC3DOWNTO2_intermed_2 <= RIN_D_PC3DOWNTO2_intermed_1;
RIN_D_PC3DOWNTO2_intermed_3 <= RIN_D_PC3DOWNTO2_intermed_2;
RIN_D_PC3DOWNTO2_intermed_4 <= RIN_D_PC3DOWNTO2_intermed_3;
RIN_D_PC3DOWNTO2_intermed_5 <= RIN_D_PC3DOWNTO2_intermed_4;
RIN_D_PC3DOWNTO2_intermed_6 <= RIN_D_PC3DOWNTO2_intermed_5;
RIN_D_PC3DOWNTO2_intermed_7 <= RIN_D_PC3DOWNTO2_intermed_6;
R_M_CTRL_PC3DOWNTO2_intermed_1 <= R.M.CTRL.PC( 3 DOWNTO 2 );
R_M_CTRL_PC3DOWNTO2_intermed_2 <= R_M_CTRL_PC3DOWNTO2_intermed_1;
R_M_CTRL_PC3DOWNTO2_intermed_3 <= R_M_CTRL_PC3DOWNTO2_intermed_2;
R_E_CTRL_PC3DOWNTO2_intermed_1 <= R.E.CTRL.PC( 3 DOWNTO 2 );
R_E_CTRL_PC3DOWNTO2_intermed_2 <= R_E_CTRL_PC3DOWNTO2_intermed_1;
R_E_CTRL_PC3DOWNTO2_intermed_3 <= R_E_CTRL_PC3DOWNTO2_intermed_2;
R_E_CTRL_PC3DOWNTO2_intermed_4 <= R_E_CTRL_PC3DOWNTO2_intermed_3;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC3DOWNTO2_shadow;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_3;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_4;
RIN_X_CTRL_PC3DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 3 DOWNTO 2 );
RIN_X_CTRL_PC3DOWNTO2_intermed_2 <= RIN_X_CTRL_PC3DOWNTO2_intermed_1;
RIN_X_CTRL_PC3DOWNTO2_intermed_3 <= RIN_X_CTRL_PC3DOWNTO2_intermed_2;
R_A_CTRL_PC3DOWNTO2_intermed_1 <= R.A.CTRL.PC( 3 DOWNTO 2 );
R_A_CTRL_PC3DOWNTO2_intermed_2 <= R_A_CTRL_PC3DOWNTO2_intermed_1;
R_A_CTRL_PC3DOWNTO2_intermed_3 <= R_A_CTRL_PC3DOWNTO2_intermed_2;
R_A_CTRL_PC3DOWNTO2_intermed_4 <= R_A_CTRL_PC3DOWNTO2_intermed_3;
R_A_CTRL_PC3DOWNTO2_intermed_5 <= R_A_CTRL_PC3DOWNTO2_intermed_4;
V_X_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC3DOWNTO2_shadow;
V_X_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC3DOWNTO2_shadow_intermed_2;
RIN_M_CTRL_PC3DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 3 DOWNTO 2 );
RIN_M_CTRL_PC3DOWNTO2_intermed_2 <= RIN_M_CTRL_PC3DOWNTO2_intermed_1;
RIN_M_CTRL_PC3DOWNTO2_intermed_3 <= RIN_M_CTRL_PC3DOWNTO2_intermed_2;
RIN_M_CTRL_PC3DOWNTO2_intermed_4 <= RIN_M_CTRL_PC3DOWNTO2_intermed_3;
IRIN_ADDR3DOWNTO2_intermed_1 <= IRIN.ADDR( 3 DOWNTO 2 );
IRIN_ADDR3DOWNTO2_intermed_2 <= IRIN_ADDR3DOWNTO2_intermed_1;
EX_JUMP_ADDRESS3DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS3DOWNTO2_shadow;
EX_ADD_RES32DOWNTO34DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO34DOWNTO3_shadow;
RIN_A_CTRL_PC3DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 3 DOWNTO 2 );
RIN_A_CTRL_PC3DOWNTO2_intermed_2 <= RIN_A_CTRL_PC3DOWNTO2_intermed_1;
RIN_A_CTRL_PC3DOWNTO2_intermed_3 <= RIN_A_CTRL_PC3DOWNTO2_intermed_2;
RIN_A_CTRL_PC3DOWNTO2_intermed_4 <= RIN_A_CTRL_PC3DOWNTO2_intermed_3;
RIN_A_CTRL_PC3DOWNTO2_intermed_5 <= RIN_A_CTRL_PC3DOWNTO2_intermed_4;
RIN_A_CTRL_PC3DOWNTO2_intermed_6 <= RIN_A_CTRL_PC3DOWNTO2_intermed_5;
XC_TRAP_ADDRESS3DOWNTO2_shadow_intermed_1 <= XC_TRAP_ADDRESS3DOWNTO2_shadow;
V_F_PC3DOWNTO2_shadow_intermed_1 <= V_F_PC3DOWNTO2_shadow;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC3DOWNTO2_shadow;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_4;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_5;
IR_ADDR3DOWNTO2_intermed_1 <= IR.ADDR( 3 DOWNTO 2 );
V_M_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC3DOWNTO2_shadow;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_2;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_3;
R_X_CTRL_PC3DOWNTO2_intermed_1 <= R.X.CTRL.PC( 3 DOWNTO 2 );
R_X_CTRL_PC3DOWNTO2_intermed_2 <= R_X_CTRL_PC3DOWNTO2_intermed_1;
RIN_E_CTRL_PC3DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 3 DOWNTO 2 );
RIN_E_CTRL_PC3DOWNTO2_intermed_2 <= RIN_E_CTRL_PC3DOWNTO2_intermed_1;
RIN_E_CTRL_PC3DOWNTO2_intermed_3 <= RIN_E_CTRL_PC3DOWNTO2_intermed_2;
RIN_E_CTRL_PC3DOWNTO2_intermed_4 <= RIN_E_CTRL_PC3DOWNTO2_intermed_3;
RIN_E_CTRL_PC3DOWNTO2_intermed_5 <= RIN_E_CTRL_PC3DOWNTO2_intermed_4;
RIN_F_PC3DOWNTO2_intermed_1 <= RIN.F.PC( 3 DOWNTO 2 );
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_DEBUG_intermed_1 <= RIN.X.DEBUG;
RIN_D_PC_intermed_1 <= RIN.D.PC;
RIN_D_PC_intermed_2 <= RIN_D_PC_intermed_1;
RIN_D_PC_intermed_3 <= RIN_D_PC_intermed_2;
RIN_D_PC_intermed_4 <= RIN_D_PC_intermed_3;
RIN_D_PC_intermed_5 <= RIN_D_PC_intermed_4;
RIN_A_CTRL_PC_intermed_1 <= RIN.A.CTRL.PC;
RIN_A_CTRL_PC_intermed_2 <= RIN_A_CTRL_PC_intermed_1;
RIN_A_CTRL_PC_intermed_3 <= RIN_A_CTRL_PC_intermed_2;
RIN_A_CTRL_PC_intermed_4 <= RIN_A_CTRL_PC_intermed_3;
R_A_CTRL_PC_intermed_1 <= R.A.CTRL.PC;
R_A_CTRL_PC_intermed_2 <= R_A_CTRL_PC_intermed_1;
R_A_CTRL_PC_intermed_3 <= R_A_CTRL_PC_intermed_2;
V_E_CTRL_PC_shadow_intermed_1 <= V_E_CTRL_PC_shadow;
V_E_CTRL_PC_shadow_intermed_2 <= V_E_CTRL_PC_shadow_intermed_1;
V_E_CTRL_PC_shadow_intermed_3 <= V_E_CTRL_PC_shadow_intermed_2;
R_M_CTRL_PC_intermed_1 <= R.M.CTRL.PC;
R_E_CTRL_PC_intermed_1 <= R.E.CTRL.PC;
R_E_CTRL_PC_intermed_2 <= R_E_CTRL_PC_intermed_1;
RIN_M_CTRL_PC_intermed_1 <= RIN.M.CTRL.PC;
RIN_M_CTRL_PC_intermed_2 <= RIN_M_CTRL_PC_intermed_1;
V_X_CTRL_PC_shadow_intermed_1 <= V_X_CTRL_PC_shadow;
V_M_CTRL_PC_shadow_intermed_1 <= V_M_CTRL_PC_shadow;
V_M_CTRL_PC_shadow_intermed_2 <= V_M_CTRL_PC_shadow_intermed_1;
V_A_CTRL_PC_shadow_intermed_1 <= V_A_CTRL_PC_shadow;
V_A_CTRL_PC_shadow_intermed_2 <= V_A_CTRL_PC_shadow_intermed_1;
V_A_CTRL_PC_shadow_intermed_3 <= V_A_CTRL_PC_shadow_intermed_2;
V_A_CTRL_PC_shadow_intermed_4 <= V_A_CTRL_PC_shadow_intermed_3;
R_D_PC_intermed_1 <= R.D.PC;
R_D_PC_intermed_2 <= R_D_PC_intermed_1;
R_D_PC_intermed_3 <= R_D_PC_intermed_2;
R_D_PC_intermed_4 <= R_D_PC_intermed_3;
RIN_E_CTRL_PC_intermed_1 <= RIN.E.CTRL.PC;
RIN_E_CTRL_PC_intermed_2 <= RIN_E_CTRL_PC_intermed_1;
RIN_E_CTRL_PC_intermed_3 <= RIN_E_CTRL_PC_intermed_2;
RIN_X_CTRL_PC_intermed_1 <= RIN.X.CTRL.PC;
V_D_PC_shadow_intermed_1 <= V_D_PC_shadow;
V_D_PC_shadow_intermed_2 <= V_D_PC_shadow_intermed_1;
V_D_PC_shadow_intermed_3 <= V_D_PC_shadow_intermed_2;
V_D_PC_shadow_intermed_4 <= V_D_PC_shadow_intermed_3;
V_D_PC_shadow_intermed_5 <= V_D_PC_shadow_intermed_4;
IRIN_ADDR_intermed_1 <= IRIN.ADDR;
V_E_CTRL_TT_shadow_intermed_1 <= V_E_CTRL_TT_shadow;
V_E_CTRL_TT_shadow_intermed_2 <= V_E_CTRL_TT_shadow_intermed_1;
V_E_CTRL_TT_shadow_intermed_3 <= V_E_CTRL_TT_shadow_intermed_2;
V_X_CTRL_TT_shadow_intermed_1 <= V_X_CTRL_TT_shadow;
RIN_A_CTRL_TT_intermed_1 <= RIN.A.CTRL.TT;
RIN_A_CTRL_TT_intermed_2 <= RIN_A_CTRL_TT_intermed_1;
RIN_A_CTRL_TT_intermed_3 <= RIN_A_CTRL_TT_intermed_2;
RIN_A_CTRL_TT_intermed_4 <= RIN_A_CTRL_TT_intermed_3;
R_A_CTRL_TT_intermed_1 <= R.A.CTRL.TT;
R_A_CTRL_TT_intermed_2 <= R_A_CTRL_TT_intermed_1;
R_A_CTRL_TT_intermed_3 <= R_A_CTRL_TT_intermed_2;
R_M_CTRL_TT_intermed_1 <= R.M.CTRL.TT;
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 );
DSUIN_TT_intermed_1 <= DSUIN.TT;
R_E_CTRL_TT_intermed_1 <= R.E.CTRL.TT;
R_E_CTRL_TT_intermed_2 <= R_E_CTRL_TT_intermed_1;
RIN_M_CTRL_TT_intermed_1 <= RIN.M.CTRL.TT;
RIN_M_CTRL_TT_intermed_2 <= RIN_M_CTRL_TT_intermed_1;
V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow;
V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow;
V_X_RESULT6DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO0_shadow_intermed_1;
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 );
RIN_X_RESULT6DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO0_intermed_1;
RIN_E_CTRL_TT_intermed_1 <= RIN.E.CTRL.TT;
RIN_E_CTRL_TT_intermed_2 <= RIN_E_CTRL_TT_intermed_1;
RIN_E_CTRL_TT_intermed_3 <= RIN_E_CTRL_TT_intermed_2;
V_M_CTRL_TT_shadow_intermed_1 <= V_M_CTRL_TT_shadow;
V_M_CTRL_TT_shadow_intermed_2 <= V_M_CTRL_TT_shadow_intermed_1;
R_X_RESULT6DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 );
V_A_CTRL_TT_shadow_intermed_1 <= V_A_CTRL_TT_shadow;
V_A_CTRL_TT_shadow_intermed_2 <= V_A_CTRL_TT_shadow_intermed_1;
V_A_CTRL_TT_shadow_intermed_3 <= V_A_CTRL_TT_shadow_intermed_2;
V_A_CTRL_TT_shadow_intermed_4 <= V_A_CTRL_TT_shadow_intermed_3;
RIN_X_CTRL_TT_intermed_1 <= RIN.X.CTRL.TT;
RPIN_PWD_intermed_1 <= RPIN.PWD;
IRIN_PWD_intermed_1 <= IRIN.PWD;
V_E_CTRL_TT_shadow_intermed_1 <= V_E_CTRL_TT_shadow;
V_E_CTRL_TT_shadow_intermed_2 <= V_E_CTRL_TT_shadow_intermed_1;
V_E_CTRL_TT_shadow_intermed_3 <= V_E_CTRL_TT_shadow_intermed_2;
V_X_CTRL_TT_shadow_intermed_1 <= V_X_CTRL_TT_shadow;
RIN_A_CTRL_TT_intermed_1 <= RIN.A.CTRL.TT;
RIN_A_CTRL_TT_intermed_2 <= RIN_A_CTRL_TT_intermed_1;
RIN_A_CTRL_TT_intermed_3 <= RIN_A_CTRL_TT_intermed_2;
RIN_A_CTRL_TT_intermed_4 <= RIN_A_CTRL_TT_intermed_3;
R_A_CTRL_TT_intermed_1 <= R.A.CTRL.TT;
R_A_CTRL_TT_intermed_2 <= R_A_CTRL_TT_intermed_1;
R_A_CTRL_TT_intermed_3 <= R_A_CTRL_TT_intermed_2;
R_M_CTRL_TT_intermed_1 <= R.M.CTRL.TT;
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 );
R_E_CTRL_TT_intermed_1 <= R.E.CTRL.TT;
R_E_CTRL_TT_intermed_2 <= R_E_CTRL_TT_intermed_1;
RIN_M_CTRL_TT_intermed_1 <= RIN.M.CTRL.TT;
RIN_M_CTRL_TT_intermed_2 <= RIN_M_CTRL_TT_intermed_1;
V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow;
V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow;
V_X_RESULT6DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO0_shadow_intermed_1;
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 );
RIN_X_RESULT6DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO0_intermed_1;
RIN_E_CTRL_TT_intermed_1 <= RIN.E.CTRL.TT;
RIN_E_CTRL_TT_intermed_2 <= RIN_E_CTRL_TT_intermed_1;
RIN_E_CTRL_TT_intermed_3 <= RIN_E_CTRL_TT_intermed_2;
V_M_CTRL_TT_shadow_intermed_1 <= V_M_CTRL_TT_shadow;
V_M_CTRL_TT_shadow_intermed_2 <= V_M_CTRL_TT_shadow_intermed_1;
R_X_RESULT6DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 );
RIN_W_S_TT_intermed_1 <= RIN.W.S.TT;
V_A_CTRL_TT_shadow_intermed_1 <= V_A_CTRL_TT_shadow;
V_A_CTRL_TT_shadow_intermed_2 <= V_A_CTRL_TT_shadow_intermed_1;
V_A_CTRL_TT_shadow_intermed_3 <= V_A_CTRL_TT_shadow_intermed_2;
V_A_CTRL_TT_shadow_intermed_4 <= V_A_CTRL_TT_shadow_intermed_3;
RIN_X_CTRL_TT_intermed_1 <= RIN.X.CTRL.TT;
RIN_W_S_S_intermed_1 <= RIN.W.S.S;
RIN_W_S_PS_intermed_1 <= RIN.W.S.PS;
V_W_S_S_shadow_intermed_1 <= V_W_S_S_shadow;
RIN_W_S_S_intermed_1 <= RIN.W.S.S;
RIN_E_CTRL_RD6DOWNTO0_intermed_1 <= RIN.E.CTRL.RD( 6 DOWNTO 0 );
RIN_E_CTRL_RD6DOWNTO0_intermed_2 <= RIN_E_CTRL_RD6DOWNTO0_intermed_1;
RIN_E_CTRL_RD6DOWNTO0_intermed_3 <= RIN_E_CTRL_RD6DOWNTO0_intermed_2;
RIN_M_CTRL_RD6DOWNTO0_intermed_1 <= RIN.M.CTRL.RD( 6 DOWNTO 0 );
RIN_M_CTRL_RD6DOWNTO0_intermed_2 <= RIN_M_CTRL_RD6DOWNTO0_intermed_1;
RIN_X_CTRL_RD6DOWNTO0_intermed_1 <= RIN.X.CTRL.RD( 6 DOWNTO 0 );
V_X_CTRL_RD6DOWNTO0_shadow_intermed_1 <= V_X_CTRL_RD6DOWNTO0_shadow;
RIN_W_S_CWP_intermed_1 <= RIN.W.S.CWP;
V_M_CTRL_RD6DOWNTO0_shadow_intermed_1 <= V_M_CTRL_RD6DOWNTO0_shadow;
V_M_CTRL_RD6DOWNTO0_shadow_intermed_2 <= V_M_CTRL_RD6DOWNTO0_shadow_intermed_1;
R_E_CTRL_RD6DOWNTO0_intermed_1 <= R.E.CTRL.RD( 6 DOWNTO 0 );
R_E_CTRL_RD6DOWNTO0_intermed_2 <= R_E_CTRL_RD6DOWNTO0_intermed_1;
V_E_CTRL_RD6DOWNTO0_shadow_intermed_1 <= V_E_CTRL_RD6DOWNTO0_shadow;
V_E_CTRL_RD6DOWNTO0_shadow_intermed_2 <= V_E_CTRL_RD6DOWNTO0_shadow_intermed_1;
V_E_CTRL_RD6DOWNTO0_shadow_intermed_3 <= V_E_CTRL_RD6DOWNTO0_shadow_intermed_2;
V_A_CTRL_RD6DOWNTO0_shadow_intermed_1 <= V_A_CTRL_RD6DOWNTO0_shadow;
V_A_CTRL_RD6DOWNTO0_shadow_intermed_2 <= V_A_CTRL_RD6DOWNTO0_shadow_intermed_1;
V_A_CTRL_RD6DOWNTO0_shadow_intermed_3 <= V_A_CTRL_RD6DOWNTO0_shadow_intermed_2;
V_A_CTRL_RD6DOWNTO0_shadow_intermed_4 <= V_A_CTRL_RD6DOWNTO0_shadow_intermed_3;
R_A_CTRL_RD6DOWNTO0_intermed_1 <= R.A.CTRL.RD( 6 DOWNTO 0 );
R_A_CTRL_RD6DOWNTO0_intermed_2 <= R_A_CTRL_RD6DOWNTO0_intermed_1;
R_A_CTRL_RD6DOWNTO0_intermed_3 <= R_A_CTRL_RD6DOWNTO0_intermed_2;
RIN_A_CTRL_RD6DOWNTO0_intermed_1 <= RIN.A.CTRL.RD( 6 DOWNTO 0 );
RIN_A_CTRL_RD6DOWNTO0_intermed_2 <= RIN_A_CTRL_RD6DOWNTO0_intermed_1;
RIN_A_CTRL_RD6DOWNTO0_intermed_3 <= RIN_A_CTRL_RD6DOWNTO0_intermed_2;
RIN_A_CTRL_RD6DOWNTO0_intermed_4 <= RIN_A_CTRL_RD6DOWNTO0_intermed_3;
R_M_CTRL_RD6DOWNTO0_intermed_1 <= R.M.CTRL.RD( 6 DOWNTO 0 );
V_W_S_CWP_shadow_intermed_1 <= V_W_S_CWP_shadow;
RIN_W_S_ET_intermed_1 <= RIN.W.S.ET;
RIN_W_S_CWP_intermed_1 <= RIN.W.S.CWP;
RPIN_ERROR_intermed_1 <= RPIN.ERROR;
RIN_D_PC_intermed_1 <= RIN.D.PC;
RIN_D_PC_intermed_2 <= RIN_D_PC_intermed_1;
RIN_D_PC_intermed_3 <= RIN_D_PC_intermed_2;
RIN_D_PC_intermed_4 <= RIN_D_PC_intermed_3;
RIN_D_PC_intermed_5 <= RIN_D_PC_intermed_4;
RIN_D_PC_intermed_6 <= RIN_D_PC_intermed_5;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_4 <= RIN_M_CTRL_PC31DOWNTO2_intermed_3;
VIR_ADDR_shadow_intermed_1 <= VIR_ADDR_shadow;
RIN_A_CTRL_PC_intermed_1 <= RIN.A.CTRL.PC;
RIN_A_CTRL_PC_intermed_2 <= RIN_A_CTRL_PC_intermed_1;
RIN_A_CTRL_PC_intermed_3 <= RIN_A_CTRL_PC_intermed_2;
RIN_A_CTRL_PC_intermed_4 <= RIN_A_CTRL_PC_intermed_3;
RIN_A_CTRL_PC_intermed_5 <= RIN_A_CTRL_PC_intermed_4;
R_A_CTRL_PC_intermed_1 <= R.A.CTRL.PC;
R_A_CTRL_PC_intermed_2 <= R_A_CTRL_PC_intermed_1;
R_A_CTRL_PC_intermed_3 <= R_A_CTRL_PC_intermed_2;
R_A_CTRL_PC_intermed_4 <= R_A_CTRL_PC_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
V_D_PC31DOWNTO2_shadow_intermed_6 <= V_D_PC31DOWNTO2_shadow_intermed_5;
V_D_PC31DOWNTO2_shadow_intermed_7 <= V_D_PC31DOWNTO2_shadow_intermed_6;
V_E_CTRL_PC_shadow_intermed_1 <= V_E_CTRL_PC_shadow;
V_E_CTRL_PC_shadow_intermed_2 <= V_E_CTRL_PC_shadow_intermed_1;
V_E_CTRL_PC_shadow_intermed_3 <= V_E_CTRL_PC_shadow_intermed_2;
V_E_CTRL_PC_shadow_intermed_4 <= V_E_CTRL_PC_shadow_intermed_3;
EX_ADD_RES32DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO3_shadow;
XC_TRAP_ADDRESS_shadow_intermed_1 <= XC_TRAP_ADDRESS_shadow;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_D_PC31DOWNTO2_intermed_6 <= RIN_D_PC31DOWNTO2_intermed_5;
RIN_D_PC31DOWNTO2_intermed_7 <= RIN_D_PC31DOWNTO2_intermed_6;
EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow;
V_F_PC31DOWNTO2_shadow_intermed_1 <= V_F_PC31DOWNTO2_shadow;
RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC( 31 DOWNTO 2 );
R_M_CTRL_PC_intermed_1 <= R.M.CTRL.PC;
R_M_CTRL_PC_intermed_2 <= R_M_CTRL_PC_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_3 <= RIN_X_CTRL_PC31DOWNTO2_intermed_2;
R_X_CTRL_PC_intermed_1 <= R.X.CTRL.PC;
R_E_CTRL_PC_intermed_1 <= R.E.CTRL.PC;
R_E_CTRL_PC_intermed_2 <= R_E_CTRL_PC_intermed_1;
R_E_CTRL_PC_intermed_3 <= R_E_CTRL_PC_intermed_2;
IRIN_ADDR31DOWNTO2_intermed_1 <= IRIN.ADDR( 31 DOWNTO 2 );
IRIN_ADDR31DOWNTO2_intermed_2 <= IRIN_ADDR31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_5;
RIN_M_CTRL_PC_intermed_1 <= RIN.M.CTRL.PC;
RIN_M_CTRL_PC_intermed_2 <= RIN_M_CTRL_PC_intermed_1;
RIN_M_CTRL_PC_intermed_3 <= RIN_M_CTRL_PC_intermed_2;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_D_PC31DOWNTO2_intermed_5 <= R_D_PC31DOWNTO2_intermed_4;
R_D_PC31DOWNTO2_intermed_6 <= R_D_PC31DOWNTO2_intermed_5;
VIR_ADDR31DOWNTO2_shadow_intermed_1 <= VIR_ADDR31DOWNTO2_shadow;
VIR_ADDR31DOWNTO2_shadow_intermed_2 <= VIR_ADDR31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC_shadow_intermed_1 <= V_X_CTRL_PC_shadow;
V_X_CTRL_PC_shadow_intermed_2 <= V_X_CTRL_PC_shadow_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_3 <= R_M_CTRL_PC31DOWNTO2_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_6 <= RIN_A_CTRL_PC31DOWNTO2_intermed_5;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
R_A_CTRL_PC31DOWNTO2_intermed_5 <= R_A_CTRL_PC31DOWNTO2_intermed_4;
V_M_CTRL_PC_shadow_intermed_1 <= V_M_CTRL_PC_shadow;
V_M_CTRL_PC_shadow_intermed_2 <= V_M_CTRL_PC_shadow_intermed_1;
V_M_CTRL_PC_shadow_intermed_3 <= V_M_CTRL_PC_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC_shadow_intermed_1 <= V_A_CTRL_PC_shadow;
V_A_CTRL_PC_shadow_intermed_2 <= V_A_CTRL_PC_shadow_intermed_1;
V_A_CTRL_PC_shadow_intermed_3 <= V_A_CTRL_PC_shadow_intermed_2;
V_A_CTRL_PC_shadow_intermed_4 <= V_A_CTRL_PC_shadow_intermed_3;
V_A_CTRL_PC_shadow_intermed_5 <= V_A_CTRL_PC_shadow_intermed_4;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
R_X_CTRL_PC31DOWNTO2_intermed_2 <= R_X_CTRL_PC31DOWNTO2_intermed_1;
R_D_PC_intermed_1 <= R.D.PC;
R_D_PC_intermed_2 <= R_D_PC_intermed_1;
R_D_PC_intermed_3 <= R_D_PC_intermed_2;
R_D_PC_intermed_4 <= R_D_PC_intermed_3;
R_D_PC_intermed_5 <= R_D_PC_intermed_4;
RIN_F_PC_intermed_1 <= RIN.F.PC;
XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO2_shadow;
RIN_E_CTRL_PC_intermed_1 <= RIN.E.CTRL.PC;
RIN_E_CTRL_PC_intermed_2 <= RIN_E_CTRL_PC_intermed_1;
RIN_E_CTRL_PC_intermed_3 <= RIN_E_CTRL_PC_intermed_2;
RIN_E_CTRL_PC_intermed_4 <= RIN_E_CTRL_PC_intermed_3;
RIN_X_CTRL_PC_intermed_1 <= RIN.X.CTRL.PC;
RIN_X_CTRL_PC_intermed_2 <= RIN_X_CTRL_PC_intermed_1;
V_D_PC_shadow_intermed_1 <= V_D_PC_shadow;
V_D_PC_shadow_intermed_2 <= V_D_PC_shadow_intermed_1;
V_D_PC_shadow_intermed_3 <= V_D_PC_shadow_intermed_2;
V_D_PC_shadow_intermed_4 <= V_D_PC_shadow_intermed_3;
V_D_PC_shadow_intermed_5 <= V_D_PC_shadow_intermed_4;
V_D_PC_shadow_intermed_6 <= V_D_PC_shadow_intermed_5;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_4 <= R_E_CTRL_PC31DOWNTO2_intermed_3;
IRIN_ADDR_intermed_1 <= IRIN.ADDR;
EX_JUMP_ADDRESS_shadow_intermed_1 <= EX_JUMP_ADDRESS_shadow;
EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO2_shadow;
IR_ADDR31DOWNTO2_intermed_1 <= IR.ADDR( 31 DOWNTO 2 );
V_F_PC_shadow_intermed_1 <= V_F_PC_shadow;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_5 <= RIN_E_CTRL_PC31DOWNTO2_intermed_4;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_2;
DSUIN_TBUFCNT_intermed_1 <= DSUIN.TBUFCNT;
RIN_W_EXCEPT_intermed_1 <= RIN.W.EXCEPT;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_X_RESULT_intermed_1 <= RIN.X.RESULT;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC ( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC ( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC ( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC ( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC ( 31 DOWNTO 2 );
DCO_DATA0_intermed_1 <= DCO.DATA ( 0 );
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
V_X_DATA0_shadow_intermed_2 <= V_X_DATA0_shadow_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA ( 0 );
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC ( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
V_X_RESULT_shadow_intermed_1 <= V_X_RESULT_shadow;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
RIN_W_RESULT_intermed_1 <= RIN.W.RESULT;
R_X_DATA0_intermed_1 <= R.X.DATA( 0 );
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 );
RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1;
V_M_CTRL_RD7DOWNTO0_shadow_intermed_1 <= V_M_CTRL_RD7DOWNTO0_shadow;
V_M_CTRL_RD7DOWNTO0_shadow_intermed_2 <= V_M_CTRL_RD7DOWNTO0_shadow_intermed_1;
V_E_CTRL_RD7DOWNTO0_shadow_intermed_1 <= V_E_CTRL_RD7DOWNTO0_shadow;
V_E_CTRL_RD7DOWNTO0_shadow_intermed_2 <= V_E_CTRL_RD7DOWNTO0_shadow_intermed_1;
V_E_CTRL_RD7DOWNTO0_shadow_intermed_3 <= V_E_CTRL_RD7DOWNTO0_shadow_intermed_2;
R_E_CTRL_RD7DOWNTO0_intermed_1 <= R.E.CTRL.RD ( 7 DOWNTO 0 );
R_E_CTRL_RD7DOWNTO0_intermed_2 <= R_E_CTRL_RD7DOWNTO0_intermed_1;
V_X_CTRL_RD7DOWNTO0_shadow_intermed_1 <= V_X_CTRL_RD7DOWNTO0_shadow;
V_A_CTRL_RD7DOWNTO0_shadow_intermed_1 <= V_A_CTRL_RD7DOWNTO0_shadow;
V_A_CTRL_RD7DOWNTO0_shadow_intermed_2 <= V_A_CTRL_RD7DOWNTO0_shadow_intermed_1;
V_A_CTRL_RD7DOWNTO0_shadow_intermed_3 <= V_A_CTRL_RD7DOWNTO0_shadow_intermed_2;
V_A_CTRL_RD7DOWNTO0_shadow_intermed_4 <= V_A_CTRL_RD7DOWNTO0_shadow_intermed_3;
RIN_W_WA_intermed_1 <= RIN.W.WA;
RIN_A_CTRL_RD7DOWNTO0_intermed_1 <= RIN.A.CTRL.RD ( 7 DOWNTO 0 );
RIN_A_CTRL_RD7DOWNTO0_intermed_2 <= RIN_A_CTRL_RD7DOWNTO0_intermed_1;
RIN_A_CTRL_RD7DOWNTO0_intermed_3 <= RIN_A_CTRL_RD7DOWNTO0_intermed_2;
RIN_A_CTRL_RD7DOWNTO0_intermed_4 <= RIN_A_CTRL_RD7DOWNTO0_intermed_3;
R_M_CTRL_RD7DOWNTO0_intermed_1 <= R.M.CTRL.RD ( 7 DOWNTO 0 );
R_A_CTRL_RD7DOWNTO0_intermed_1 <= R.A.CTRL.RD ( 7 DOWNTO 0 );
R_A_CTRL_RD7DOWNTO0_intermed_2 <= R_A_CTRL_RD7DOWNTO0_intermed_1;
R_A_CTRL_RD7DOWNTO0_intermed_3 <= R_A_CTRL_RD7DOWNTO0_intermed_2;
RIN_E_CTRL_RD7DOWNTO0_intermed_1 <= RIN.E.CTRL.RD ( 7 DOWNTO 0 );
RIN_E_CTRL_RD7DOWNTO0_intermed_2 <= RIN_E_CTRL_RD7DOWNTO0_intermed_1;
RIN_E_CTRL_RD7DOWNTO0_intermed_3 <= RIN_E_CTRL_RD7DOWNTO0_intermed_2;
RIN_X_CTRL_RD7DOWNTO0_intermed_1 <= RIN.X.CTRL.RD ( 7 DOWNTO 0 );
RIN_M_CTRL_RD7DOWNTO0_intermed_1 <= RIN.M.CTRL.RD ( 7 DOWNTO 0 );
RIN_M_CTRL_RD7DOWNTO0_intermed_2 <= RIN_M_CTRL_RD7DOWNTO0_intermed_1;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2;
RIN_A_CTRL_ANNUL_intermed_4 <= RIN_A_CTRL_ANNUL_intermed_3;
RIN_A_CTRL_ANNUL_intermed_5 <= RIN_A_CTRL_ANNUL_intermed_4;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1;
R_A_CTRL_ANNUL_intermed_3 <= R_A_CTRL_ANNUL_intermed_2;
R_A_CTRL_ANNUL_intermed_4 <= R_A_CTRL_ANNUL_intermed_3;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
R_X_ANNUL_ALL_intermed_2 <= R_X_ANNUL_ALL_intermed_1;
R_X_ANNUL_ALL_intermed_3 <= R_X_ANNUL_ALL_intermed_2;
R_X_ANNUL_ALL_intermed_4 <= R_X_ANNUL_ALL_intermed_3;
V_X_CTRL_WREG_shadow_intermed_1 <= V_X_CTRL_WREG_shadow;
RIN_X_CTRL_WREG_intermed_1 <= RIN.X.CTRL.WREG;
RIN_M_CTRL_WREG_intermed_1 <= RIN.M.CTRL.WREG;
RIN_M_CTRL_WREG_intermed_2 <= RIN_M_CTRL_WREG_intermed_1;
RIN_A_CTRL_WREG_intermed_1 <= RIN.A.CTRL.WREG;
RIN_A_CTRL_WREG_intermed_2 <= RIN_A_CTRL_WREG_intermed_1;
RIN_A_CTRL_WREG_intermed_3 <= RIN_A_CTRL_WREG_intermed_2;
RIN_A_CTRL_WREG_intermed_4 <= RIN_A_CTRL_WREG_intermed_3;
V_A_CTRL_WREG_shadow_intermed_1 <= V_A_CTRL_WREG_shadow;
V_A_CTRL_WREG_shadow_intermed_2 <= V_A_CTRL_WREG_shadow_intermed_1;
V_A_CTRL_WREG_shadow_intermed_3 <= V_A_CTRL_WREG_shadow_intermed_2;
V_A_CTRL_WREG_shadow_intermed_4 <= V_A_CTRL_WREG_shadow_intermed_3;
R_A_CTRL_WREG_intermed_1 <= R.A.CTRL.WREG;
R_A_CTRL_WREG_intermed_2 <= R_A_CTRL_WREG_intermed_1;
R_A_CTRL_WREG_intermed_3 <= R_A_CTRL_WREG_intermed_2;
RIN_W_WREG_intermed_1 <= RIN.W.WREG;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
V_X_ANNUL_ALL_shadow_intermed_2 <= V_X_ANNUL_ALL_shadow_intermed_1;
V_X_ANNUL_ALL_shadow_intermed_3 <= V_X_ANNUL_ALL_shadow_intermed_2;
V_X_ANNUL_ALL_shadow_intermed_4 <= V_X_ANNUL_ALL_shadow_intermed_3;
R_M_CTRL_WREG_intermed_1 <= R.M.CTRL.WREG;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
RIN_X_ANNUL_ALL_intermed_3 <= RIN_X_ANNUL_ALL_intermed_2;
RIN_X_ANNUL_ALL_intermed_4 <= RIN_X_ANNUL_ALL_intermed_3;
RIN_X_ANNUL_ALL_intermed_5 <= RIN_X_ANNUL_ALL_intermed_4;
V_M_CTRL_WREG_shadow_intermed_1 <= V_M_CTRL_WREG_shadow;
V_M_CTRL_WREG_shadow_intermed_2 <= V_M_CTRL_WREG_shadow_intermed_1;
R_E_CTRL_WREG_intermed_1 <= R.E.CTRL.WREG;
R_E_CTRL_WREG_intermed_2 <= R_E_CTRL_WREG_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_3 <= V_A_CTRL_ANNUL_shadow_intermed_2;
V_A_CTRL_ANNUL_shadow_intermed_4 <= V_A_CTRL_ANNUL_shadow_intermed_3;
RIN_E_CTRL_WREG_intermed_1 <= RIN.E.CTRL.WREG;
RIN_E_CTRL_WREG_intermed_2 <= RIN_E_CTRL_WREG_intermed_1;
RIN_E_CTRL_WREG_intermed_3 <= RIN_E_CTRL_WREG_intermed_2;
V_E_CTRL_WREG_shadow_intermed_1 <= V_E_CTRL_WREG_shadow;
V_E_CTRL_WREG_shadow_intermed_2 <= V_E_CTRL_WREG_shadow_intermed_1;
V_E_CTRL_WREG_shadow_intermed_3 <= V_E_CTRL_WREG_shadow_intermed_2;
RIN_W_S_SVT_intermed_1 <= RIN.W.S.SVT;
RIN_W_S_DWT_intermed_1 <= RIN.W.S.DWT;
RIN_W_S_EF_intermed_1 <= RIN.W.S.EF;
RIN_E_CTRL_intermed_1 <= RIN.E.CTRL;
RIN_E_CTRL_intermed_2 <= RIN_E_CTRL_intermed_1;
R_E_CTRL_intermed_1 <= R.E.CTRL;
RIN_X_CTRL_intermed_1 <= RIN.X.CTRL;
RIN_M_CTRL_intermed_1 <= RIN.M.CTRL;
V_E_CTRL_shadow_intermed_1 <= V_E_CTRL_shadow;
V_E_CTRL_shadow_intermed_2 <= V_E_CTRL_shadow_intermed_1;
RIN_A_CTRL_intermed_1 <= RIN.A.CTRL;
RIN_A_CTRL_intermed_2 <= RIN_A_CTRL_intermed_1;
RIN_A_CTRL_intermed_3 <= RIN_A_CTRL_intermed_2;
V_M_CTRL_shadow_intermed_1 <= V_M_CTRL_shadow;
V_A_CTRL_shadow_intermed_1 <= V_A_CTRL_shadow;
V_A_CTRL_shadow_intermed_2 <= V_A_CTRL_shadow_intermed_1;
V_A_CTRL_shadow_intermed_3 <= V_A_CTRL_shadow_intermed_2;
R_A_CTRL_intermed_1 <= R.A.CTRL;
R_A_CTRL_intermed_2 <= R_A_CTRL_intermed_1;
V_M_DCI_shadow_intermed_1 <= V_M_DCI_shadow;
RIN_M_DCI_intermed_1 <= RIN.M.DCI;
RIN_X_DCI_intermed_1 <= RIN.X.DCI;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2;
RIN_A_CTRL_ANNUL_intermed_4 <= RIN_A_CTRL_ANNUL_intermed_3;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1;
R_A_CTRL_ANNUL_intermed_3 <= R_A_CTRL_ANNUL_intermed_2;
RIN_M_CTRL_RETT_intermed_1 <= RIN.M.CTRL.RETT;
V_M_CTRL_ANNUL_shadow_intermed_1 <= V_M_CTRL_ANNUL_shadow;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
R_X_ANNUL_ALL_intermed_2 <= R_X_ANNUL_ALL_intermed_1;
R_X_ANNUL_ALL_intermed_3 <= R_X_ANNUL_ALL_intermed_2;
RIN_M_CTRL_ANNUL_intermed_1 <= RIN.M.CTRL.ANNUL;
V_E_CTRL_RETT_shadow_intermed_1 <= V_E_CTRL_RETT_shadow;
V_E_CTRL_RETT_shadow_intermed_2 <= V_E_CTRL_RETT_shadow_intermed_1;
V_A_CTRL_RETT_shadow_intermed_1 <= V_A_CTRL_RETT_shadow;
V_A_CTRL_RETT_shadow_intermed_2 <= V_A_CTRL_RETT_shadow_intermed_1;
V_A_CTRL_RETT_shadow_intermed_3 <= V_A_CTRL_RETT_shadow_intermed_2;
RIN_A_CTRL_RETT_intermed_1 <= RIN.A.CTRL.RETT;
RIN_A_CTRL_RETT_intermed_2 <= RIN_A_CTRL_RETT_intermed_1;
RIN_A_CTRL_RETT_intermed_3 <= RIN_A_CTRL_RETT_intermed_2;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
V_X_ANNUL_ALL_shadow_intermed_2 <= V_X_ANNUL_ALL_shadow_intermed_1;
V_X_ANNUL_ALL_shadow_intermed_3 <= V_X_ANNUL_ALL_shadow_intermed_2;
RIN_E_CTRL_ANNUL_intermed_1 <= RIN.E.CTRL.ANNUL;
RIN_E_CTRL_ANNUL_intermed_2 <= RIN_E_CTRL_ANNUL_intermed_1;
R_E_CTRL_RETT_intermed_1 <= R.E.CTRL.RETT;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
RIN_X_ANNUL_ALL_intermed_3 <= RIN_X_ANNUL_ALL_intermed_2;
RIN_X_ANNUL_ALL_intermed_4 <= RIN_X_ANNUL_ALL_intermed_3;
RIN_E_CTRL_RETT_intermed_1 <= RIN.E.CTRL.RETT;
RIN_E_CTRL_RETT_intermed_2 <= RIN_E_CTRL_RETT_intermed_1;
V_E_CTRL_ANNUL_shadow_intermed_1 <= V_E_CTRL_ANNUL_shadow;
V_E_CTRL_ANNUL_shadow_intermed_2 <= V_E_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_3 <= V_A_CTRL_ANNUL_shadow_intermed_2;
RIN_X_CTRL_RETT_intermed_1 <= RIN.X.CTRL.RETT;
V_M_CTRL_RETT_shadow_intermed_1 <= V_M_CTRL_RETT_shadow;
R_A_CTRL_RETT_intermed_1 <= R.A.CTRL.RETT;
R_A_CTRL_RETT_intermed_2 <= R_A_CTRL_RETT_intermed_1;
R_E_CTRL_ANNUL_intermed_1 <= R.E.CTRL.ANNUL;
V_E_MAC_shadow_intermed_1 <= V_E_MAC_shadow;
V_E_MAC_shadow_intermed_2 <= V_E_MAC_shadow_intermed_1;
RIN_M_MAC_intermed_1 <= RIN.M.MAC;
RIN_E_MAC_intermed_1 <= RIN.E.MAC;
RIN_E_MAC_intermed_2 <= RIN_E_MAC_intermed_1;
R_E_MAC_intermed_1 <= R.E.MAC;
V_M_MAC_shadow_intermed_1 <= V_M_MAC_shadow;
RIN_X_MAC_intermed_1 <= RIN.X.MAC;
V_M_RESULT1DOWNTO0_shadow_intermed_1 <= V_M_RESULT1DOWNTO0_shadow;
V_M_RESULT1DOWNTO0_shadow_intermed_2 <= V_M_RESULT1DOWNTO0_shadow_intermed_1;
RIN_X_LADDR_intermed_1 <= RIN.X.LADDR;
RIN_M_RESULT1DOWNTO0_intermed_1 <= RIN.M.RESULT( 1 DOWNTO 0 );
RIN_M_RESULT1DOWNTO0_intermed_2 <= RIN_M_RESULT1DOWNTO0_intermed_1;
V_M_RESULT1DOWNTO0_shadow_intermed_1 <= V_M_RESULT1DOWNTO0_shadow;
R_M_RESULT1DOWNTO0_intermed_1 <= R.M.RESULT( 1 DOWNTO 0 );
RIN_M_RESULT1DOWNTO0_intermed_1 <= RIN.M.RESULT ( 1 DOWNTO 0 );
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1;
V_M_CTRL_ANNUL_shadow_intermed_1 <= V_M_CTRL_ANNUL_shadow;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
RIN_X_CTRL_ANNUL_intermed_1 <= RIN.X.CTRL.ANNUL;
RIN_M_CTRL_ANNUL_intermed_1 <= RIN.M.CTRL.ANNUL;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
RIN_E_CTRL_ANNUL_intermed_1 <= RIN.E.CTRL.ANNUL;
RIN_E_CTRL_ANNUL_intermed_2 <= RIN_E_CTRL_ANNUL_intermed_1;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
V_E_CTRL_ANNUL_shadow_intermed_1 <= V_E_CTRL_ANNUL_shadow;
V_E_CTRL_ANNUL_shadow_intermed_2 <= V_E_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_3 <= V_A_CTRL_ANNUL_shadow_intermed_2;
R_E_CTRL_ANNUL_intermed_1 <= R.E.CTRL.ANNUL;
V_E_CTRL_TT_shadow_intermed_1 <= V_E_CTRL_TT_shadow;
V_E_CTRL_TT_shadow_intermed_2 <= V_E_CTRL_TT_shadow_intermed_1;
V_E_CTRL_TT_shadow_intermed_3 <= V_E_CTRL_TT_shadow_intermed_2;
RIN_A_CTRL_TT_intermed_1 <= RIN.A.CTRL.TT;
RIN_A_CTRL_TT_intermed_2 <= RIN_A_CTRL_TT_intermed_1;
RIN_A_CTRL_TT_intermed_3 <= RIN_A_CTRL_TT_intermed_2;
RIN_A_CTRL_TT_intermed_4 <= RIN_A_CTRL_TT_intermed_3;
R_A_CTRL_TT_intermed_1 <= R.A.CTRL.TT;
R_A_CTRL_TT_intermed_2 <= R_A_CTRL_TT_intermed_1;
R_A_CTRL_TT_intermed_3 <= R_A_CTRL_TT_intermed_2;
R_M_CTRL_TT_intermed_1 <= R.M.CTRL.TT;
R_E_CTRL_TT_intermed_1 <= R.E.CTRL.TT;
R_E_CTRL_TT_intermed_2 <= R_E_CTRL_TT_intermed_1;
RIN_M_CTRL_TT_intermed_1 <= RIN.M.CTRL.TT;
RIN_M_CTRL_TT_intermed_2 <= RIN_M_CTRL_TT_intermed_1;
RIN_E_CTRL_TT_intermed_1 <= RIN.E.CTRL.TT;
RIN_E_CTRL_TT_intermed_2 <= RIN_E_CTRL_TT_intermed_1;
RIN_E_CTRL_TT_intermed_3 <= RIN_E_CTRL_TT_intermed_2;
V_M_CTRL_TT_shadow_intermed_1 <= V_M_CTRL_TT_shadow;
V_M_CTRL_TT_shadow_intermed_2 <= V_M_CTRL_TT_shadow_intermed_1;
V_A_CTRL_TT_shadow_intermed_1 <= V_A_CTRL_TT_shadow;
V_A_CTRL_TT_shadow_intermed_2 <= V_A_CTRL_TT_shadow_intermed_1;
V_A_CTRL_TT_shadow_intermed_3 <= V_A_CTRL_TT_shadow_intermed_2;
V_A_CTRL_TT_shadow_intermed_4 <= V_A_CTRL_TT_shadow_intermed_3;
RIN_X_CTRL_TT_intermed_1 <= RIN.X.CTRL.TT;
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
V_X_DATA0_shadow_intermed_2 <= V_X_DATA0_shadow_intermed_1;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA ( 0 );
R_X_DATA0_intermed_1 <= R.X.DATA( 0 );
RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 );
RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1;
V_X_DATA1_shadow_intermed_1 <= V_X_DATA1_shadow;
V_X_DATA1_shadow_intermed_2 <= V_X_DATA1_shadow_intermed_1;
RIN_X_DATA1_intermed_1 <= RIN.X.DATA ( 1 );
R_X_DATA1_intermed_1 <= R.X.DATA( 1 );
RIN_X_DATA1_intermed_1 <= RIN.X.DATA( 1 );
RIN_X_DATA1_intermed_2 <= RIN_X_DATA1_intermed_1;
RIN_X_SET_intermed_1 <= RIN.X.SET;
V_M_DCI_SIZE_shadow_intermed_1 <= V_M_DCI_SIZE_shadow;
V_M_DCI_SIZE_shadow_intermed_2 <= V_M_DCI_SIZE_shadow_intermed_1;
R_M_DCI_SIZE_intermed_1 <= R.M.DCI.SIZE;
RIN_X_DCI_SIZE_intermed_1 <= RIN.X.DCI.SIZE;
RIN_M_DCI_SIZE_intermed_1 <= RIN.M.DCI.SIZE;
RIN_M_DCI_SIZE_intermed_2 <= RIN_M_DCI_SIZE_intermed_1;
RIN_M_DCI_SIGNED_intermed_1 <= RIN.M.DCI.SIGNED;
RIN_M_DCI_SIGNED_intermed_2 <= RIN_M_DCI_SIGNED_intermed_1;
R_M_DCI_SIGNED_intermed_1 <= R.M.DCI.SIGNED;
RIN_X_DCI_SIGNED_intermed_1 <= RIN.X.DCI.SIGNED;
V_M_DCI_SIGNED_shadow_intermed_1 <= V_M_DCI_SIGNED_shadow;
V_M_DCI_SIGNED_shadow_intermed_2 <= V_M_DCI_SIGNED_shadow_intermed_1;
RIN_X_MEXC_intermed_1 <= RIN.X.MEXC;
RIN_X_ICC_intermed_1 <= RIN.X.ICC;
R_A_CTRL_WICC_intermed_1 <= R.A.CTRL.WICC;
R_A_CTRL_WICC_intermed_2 <= R_A_CTRL_WICC_intermed_1;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2;
RIN_A_CTRL_ANNUL_intermed_4 <= RIN_A_CTRL_ANNUL_intermed_3;
V_E_CTRL_WICC_shadow_intermed_1 <= V_E_CTRL_WICC_shadow;
V_E_CTRL_WICC_shadow_intermed_2 <= V_E_CTRL_WICC_shadow_intermed_1;
V_A_CTRL_WICC_shadow_intermed_1 <= V_A_CTRL_WICC_shadow;
V_A_CTRL_WICC_shadow_intermed_2 <= V_A_CTRL_WICC_shadow_intermed_1;
V_A_CTRL_WICC_shadow_intermed_3 <= V_A_CTRL_WICC_shadow_intermed_2;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1;
R_A_CTRL_ANNUL_intermed_3 <= R_A_CTRL_ANNUL_intermed_2;
RIN_X_CTRL_WICC_intermed_1 <= RIN.X.CTRL.WICC;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
R_X_ANNUL_ALL_intermed_2 <= R_X_ANNUL_ALL_intermed_1;
R_X_ANNUL_ALL_intermed_3 <= R_X_ANNUL_ALL_intermed_2;
RIN_E_CTRL_WICC_intermed_1 <= RIN.E.CTRL.WICC;
RIN_E_CTRL_WICC_intermed_2 <= RIN_E_CTRL_WICC_intermed_1;
RIN_M_CTRL_WICC_intermed_1 <= RIN.M.CTRL.WICC;
R_E_CTRL_WICC_intermed_1 <= R.E.CTRL.WICC;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
V_X_ANNUL_ALL_shadow_intermed_2 <= V_X_ANNUL_ALL_shadow_intermed_1;
V_X_ANNUL_ALL_shadow_intermed_3 <= V_X_ANNUL_ALL_shadow_intermed_2;
V_M_CTRL_WICC_shadow_intermed_1 <= V_M_CTRL_WICC_shadow;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
RIN_X_ANNUL_ALL_intermed_3 <= RIN_X_ANNUL_ALL_intermed_2;
RIN_X_ANNUL_ALL_intermed_4 <= RIN_X_ANNUL_ALL_intermed_3;
RIN_A_CTRL_WICC_intermed_1 <= RIN.A.CTRL.WICC;
RIN_A_CTRL_WICC_intermed_2 <= RIN_A_CTRL_WICC_intermed_1;
RIN_A_CTRL_WICC_intermed_3 <= RIN_A_CTRL_WICC_intermed_2;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_3 <= V_A_CTRL_ANNUL_shadow_intermed_2;
RIN_E_CTRL_intermed_1 <= RIN.E.CTRL;
RIN_M_CTRL_intermed_1 <= RIN.M.CTRL;
V_E_CTRL_shadow_intermed_1 <= V_E_CTRL_shadow;
RIN_A_CTRL_intermed_1 <= RIN.A.CTRL;
RIN_A_CTRL_intermed_2 <= RIN_A_CTRL_intermed_1;
V_A_CTRL_shadow_intermed_1 <= V_A_CTRL_shadow;
V_A_CTRL_shadow_intermed_2 <= V_A_CTRL_shadow_intermed_1;
R_A_CTRL_intermed_1 <= R.A.CTRL;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1;
RIN_M_CTRL_RETT_intermed_1 <= RIN.M.CTRL.RETT;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
R_X_ANNUL_ALL_intermed_2 <= R_X_ANNUL_ALL_intermed_1;
V_E_CTRL_RETT_shadow_intermed_1 <= V_E_CTRL_RETT_shadow;
V_A_CTRL_RETT_shadow_intermed_1 <= V_A_CTRL_RETT_shadow;
V_A_CTRL_RETT_shadow_intermed_2 <= V_A_CTRL_RETT_shadow_intermed_1;
RIN_A_CTRL_RETT_intermed_1 <= RIN.A.CTRL.RETT;
RIN_A_CTRL_RETT_intermed_2 <= RIN_A_CTRL_RETT_intermed_1;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
V_X_ANNUL_ALL_shadow_intermed_2 <= V_X_ANNUL_ALL_shadow_intermed_1;
RIN_E_CTRL_ANNUL_intermed_1 <= RIN.E.CTRL.ANNUL;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
RIN_X_ANNUL_ALL_intermed_3 <= RIN_X_ANNUL_ALL_intermed_2;
RIN_E_CTRL_RETT_intermed_1 <= RIN.E.CTRL.RETT;
V_E_CTRL_ANNUL_shadow_intermed_1 <= V_E_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1;
R_A_CTRL_RETT_intermed_1 <= R.A.CTRL.RETT;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
R_X_ANNUL_ALL_intermed_2 <= R_X_ANNUL_ALL_intermed_1;
RIN_M_CTRL_WREG_intermed_1 <= RIN.M.CTRL.WREG;
RIN_A_CTRL_WREG_intermed_1 <= RIN.A.CTRL.WREG;
RIN_A_CTRL_WREG_intermed_2 <= RIN_A_CTRL_WREG_intermed_1;
V_A_CTRL_WREG_shadow_intermed_1 <= V_A_CTRL_WREG_shadow;
V_A_CTRL_WREG_shadow_intermed_2 <= V_A_CTRL_WREG_shadow_intermed_1;
R_A_CTRL_WREG_intermed_1 <= R.A.CTRL.WREG;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
V_X_ANNUL_ALL_shadow_intermed_2 <= V_X_ANNUL_ALL_shadow_intermed_1;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
RIN_X_ANNUL_ALL_intermed_3 <= RIN_X_ANNUL_ALL_intermed_2;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1;
RIN_E_CTRL_WREG_intermed_1 <= RIN.E.CTRL.WREG;
V_E_CTRL_WREG_shadow_intermed_1 <= V_E_CTRL_WREG_shadow;
RIN_E_CWP_intermed_1 <= RIN.E.CWP;
V_A_CWP_shadow_intermed_1 <= V_A_CWP_shadow;
RIN_D_CWP_intermed_1 <= RIN.D.CWP;
RIN_D_CWP_intermed_2 <= RIN_D_CWP_intermed_1;
RIN_A_CWP_intermed_1 <= RIN.A.CWP;
V_D_CWP_shadow_intermed_1 <= V_D_CWP_shadow;
V_D_CWP_shadow_intermed_2 <= V_D_CWP_shadow_intermed_1;
R_D_CWP_intermed_1 <= R.D.CWP;
R_A_SU_intermed_1 <= R.A.SU;
RIN_A_SU_intermed_1 <= RIN.A.SU;
RIN_A_SU_intermed_2 <= RIN_A_SU_intermed_1;
V_E_SU_shadow_intermed_1 <= V_E_SU_shadow;
V_A_SU_shadow_intermed_1 <= V_A_SU_shadow;
V_A_SU_shadow_intermed_2 <= V_A_SU_shadow_intermed_1;
RIN_M_SU_intermed_1 <= RIN.M.SU;
RIN_E_SU_intermed_1 <= RIN.E.SU;
RIN_M_MUL_intermed_1 <= RIN.M.MUL;
RIN_M_NALIGN_intermed_1 <= RIN.M.NALIGN;
V_X_DATA03_shadow_intermed_1 <= V_X_DATA03_shadow;
V_X_DATA03_shadow_intermed_2 <= V_X_DATA03_shadow_intermed_1;
V_X_DATA03_shadow_intermed_1 <= V_X_DATA03_shadow;
DCO_DATA03_intermed_1 <= DCO.DATA ( 0 )( 3 );
RIN_X_DATA03_intermed_1 <= RIN.X.DATA ( 0 )( 3 );
R_X_DATA03_intermed_1 <= R.X.DATA( 0 )( 3 );
RIN_X_DATA03_intermed_1 <= RIN.X.DATA( 0 )( 3 );
RIN_X_DATA03_intermed_2 <= RIN_X_DATA03_intermed_1;
RIN_E_OP23_intermed_1 <= RIN.E.OP2( 3 );
RIN_E_OP13_intermed_1 <= RIN.E.OP1( 3 );
V_E_OP23_shadow_intermed_1 <= V_E_OP23_shadow;
V_E_OP13_shadow_intermed_1 <= V_E_OP13_shadow;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1;
RIN_M_CTRL_ANNUL_intermed_1 <= RIN.M.CTRL.ANNUL;
RIN_E_CTRL_ANNUL_intermed_1 <= RIN.E.CTRL.ANNUL;
RIN_E_CTRL_ANNUL_intermed_2 <= RIN_E_CTRL_ANNUL_intermed_1;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
V_E_CTRL_ANNUL_shadow_intermed_1 <= V_E_CTRL_ANNUL_shadow;
V_E_CTRL_ANNUL_shadow_intermed_2 <= V_E_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_3 <= V_A_CTRL_ANNUL_shadow_intermed_2;
R_E_CTRL_ANNUL_intermed_1 <= R.E.CTRL.ANNUL;
R_A_CTRL_WICC_intermed_1 <= R.A.CTRL.WICC;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2;
V_E_CTRL_WICC_shadow_intermed_1 <= V_E_CTRL_WICC_shadow;
V_A_CTRL_WICC_shadow_intermed_1 <= V_A_CTRL_WICC_shadow;
V_A_CTRL_WICC_shadow_intermed_2 <= V_A_CTRL_WICC_shadow_intermed_1;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
R_X_ANNUL_ALL_intermed_2 <= R_X_ANNUL_ALL_intermed_1;
RIN_E_CTRL_WICC_intermed_1 <= RIN.E.CTRL.WICC;
RIN_M_CTRL_WICC_intermed_1 <= RIN.M.CTRL.WICC;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
V_X_ANNUL_ALL_shadow_intermed_2 <= V_X_ANNUL_ALL_shadow_intermed_1;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
RIN_X_ANNUL_ALL_intermed_3 <= RIN_X_ANNUL_ALL_intermed_2;
RIN_A_CTRL_WICC_intermed_1 <= RIN.A.CTRL.WICC;
RIN_A_CTRL_WICC_intermed_2 <= RIN_A_CTRL_WICC_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1;
V_E_MAC_shadow_intermed_1 <= V_E_MAC_shadow;
RIN_M_MAC_intermed_1 <= RIN.M.MAC;
RIN_E_MAC_intermed_1 <= RIN.E.MAC;
R_A_CTRL_LD_intermed_1 <= R.A.CTRL.LD;
R_A_CTRL_LD_intermed_2 <= R_A_CTRL_LD_intermed_1;
RIN_A_CTRL_LD_intermed_1 <= RIN.A.CTRL.LD;
RIN_A_CTRL_LD_intermed_2 <= RIN_A_CTRL_LD_intermed_1;
RIN_A_CTRL_LD_intermed_3 <= RIN_A_CTRL_LD_intermed_2;
V_E_CTRL_LD_shadow_intermed_1 <= V_E_CTRL_LD_shadow;
V_E_CTRL_LD_shadow_intermed_2 <= V_E_CTRL_LD_shadow_intermed_1;
R_E_CTRL_LD_intermed_1 <= R.E.CTRL.LD;
RIN_E_CTRL_LD_intermed_1 <= RIN.E.CTRL.LD;
RIN_E_CTRL_LD_intermed_2 <= RIN_E_CTRL_LD_intermed_1;
RIN_M_CTRL_LD_intermed_1 <= RIN.M.CTRL.LD;
V_A_CTRL_LD_shadow_intermed_1 <= V_A_CTRL_LD_shadow;
V_A_CTRL_LD_shadow_intermed_2 <= V_A_CTRL_LD_shadow_intermed_1;
V_A_CTRL_LD_shadow_intermed_3 <= V_A_CTRL_LD_shadow_intermed_2;
RIN_E_CTRL_intermed_1 <= RIN.E.CTRL;
RIN_A_CTRL_intermed_1 <= RIN.A.CTRL;
V_A_CTRL_shadow_intermed_1 <= V_A_CTRL_shadow;
RIN_E_JMPL_intermed_1 <= RIN.E.JMPL;
RIN_A_JMPL_intermed_1 <= RIN.A.JMPL;
V_A_JMPL_shadow_intermed_1 <= V_A_JMPL_shadow;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
RIN_E_CTRL_ANNUL_intermed_1 <= RIN.E.CTRL.ANNUL;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
V_A_CTRL_RETT_shadow_intermed_1 <= V_A_CTRL_RETT_shadow;
RIN_A_CTRL_RETT_intermed_1 <= RIN.A.CTRL.RETT;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
RIN_E_CTRL_RETT_intermed_1 <= RIN.E.CTRL.RETT;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
RIN_A_CTRL_WREG_intermed_1 <= RIN.A.CTRL.WREG;
V_A_CTRL_WREG_shadow_intermed_1 <= V_A_CTRL_WREG_shadow;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
RIN_E_CTRL_WREG_intermed_1 <= RIN.E.CTRL.WREG;
RIN_A_SU_intermed_1 <= RIN.A.SU;
V_A_SU_shadow_intermed_1 <= V_A_SU_shadow;
RIN_E_SU_intermed_1 <= RIN.E.SU;
RIN_E_ET_intermed_1 <= RIN.E.ET;
RIN_A_ET_intermed_1 <= RIN.A.ET;
V_A_ET_shadow_intermed_1 <= V_A_ET_shadow;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
V_A_CTRL_WICC_shadow_intermed_1 <= V_A_CTRL_WICC_shadow;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
RIN_E_CTRL_WICC_intermed_1 <= RIN.E.CTRL.WICC;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
RIN_A_CTRL_WICC_intermed_1 <= RIN.A.CTRL.WICC;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
RIN_D_CWP_intermed_1 <= RIN.D.CWP;
RIN_A_CWP_intermed_1 <= RIN.A.CWP;
V_D_CWP_shadow_intermed_1 <= V_D_CWP_shadow;
RIN_A_RFA1_intermed_1 <= RIN.A.RFA1;
V_A_RFA1_shadow_intermed_1 <= V_A_RFA1_shadow;
DBGI_DADDR9DOWNTO2_intermed_1 <= DBGI.DADDR ( 9 DOWNTO 2 );
RIN_A_RFA1_intermed_1 <= RIN.A.RFA1;
RIN_A_RFA2_intermed_1 <= RIN.A.RFA2;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_A_CTRL_WICC_intermed_1 <= RIN.A.CTRL.WICC;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_WREG_intermed_1 <= RIN.A.CTRL.WREG;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_RETT_intermed_1 <= RIN.A.CTRL.RETT;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_A_CTRL_WY_intermed_1 <= RIN.A.CTRL.WY;
ICO_MEXC_intermed_1 <= ICO.MEXC;
RIN_A_CTRL_TRAP_intermed_1 <= RIN.A.CTRL.TRAP;
V_D_MEXC_shadow_intermed_1 <= V_D_MEXC_shadow;
RIN_D_MEXC_intermed_1 <= RIN.D.MEXC;
RIN_A_CTRL_TT_intermed_1 <= RIN.A.CTRL.TT;
RIN_A_CTRL_INST_intermed_1 <= RIN.A.CTRL.INST;
RIN_D_PC_intermed_1 <= RIN.D.PC;
RIN_A_CTRL_PC_intermed_1 <= RIN.A.CTRL.PC;
V_D_PC_shadow_intermed_1 <= V_D_PC_shadow;
RIN_D_CNT_intermed_1 <= RIN.D.CNT;
V_D_CNT_shadow_intermed_1 <= V_D_CNT_shadow;
RIN_A_CTRL_CNT_intermed_1 <= RIN.A.CTRL.CNT;
R_D_ANNUL_intermed_1 <= R.D.ANNUL;
RIN_D_STEP_intermed_1 <= RIN.D.STEP;
V_D_ANNUL_shadow_intermed_1 <= V_D_ANNUL_shadow;
V_D_ANNUL_shadow_intermed_2 <= V_D_ANNUL_shadow_intermed_1;
DBGI_STEP_intermed_1 <= DBGI.STEP;
V_D_STEP_shadow_intermed_1 <= V_D_STEP_shadow;
RIN_D_ANNUL_intermed_1 <= RIN.D.ANNUL;
RIN_D_ANNUL_intermed_2 <= RIN_D_ANNUL_intermed_1;
RIN_A_STEP_intermed_1 <= RIN.A.STEP;
RIN_D_STEP_intermed_1 <= RIN.D.STEP;
V_D_ANNUL_shadow_intermed_1 <= V_D_ANNUL_shadow;
RIN_D_ANNUL_intermed_1 <= RIN.D.ANNUL;
RIN_D_CNT_intermed_1 <= RIN.D.CNT;
EX_ADD_RES32DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO3_shadow;
RIN_F_PC_intermed_1 <= RIN.F.PC;
EX_JUMP_ADDRESS_shadow_intermed_1 <= EX_JUMP_ADDRESS_shadow;
RIN_F_BRANCH_intermed_1 <= RIN.F.BRANCH;
R_M_CTRL_PC31DOWNTO12_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 12 );
R_M_CTRL_PC31DOWNTO12_intermed_2 <= R_M_CTRL_PC31DOWNTO12_intermed_1;
R_M_CTRL_PC31DOWNTO12_intermed_3 <= R_M_CTRL_PC31DOWNTO12_intermed_2;
V_D_PC31DOWNTO12_shadow_intermed_1 <= V_D_PC31DOWNTO12_shadow;
V_D_PC31DOWNTO12_shadow_intermed_2 <= V_D_PC31DOWNTO12_shadow_intermed_1;
V_D_PC31DOWNTO12_shadow_intermed_3 <= V_D_PC31DOWNTO12_shadow_intermed_2;
V_D_PC31DOWNTO12_shadow_intermed_4 <= V_D_PC31DOWNTO12_shadow_intermed_3;
V_D_PC31DOWNTO12_shadow_intermed_5 <= V_D_PC31DOWNTO12_shadow_intermed_4;
V_D_PC31DOWNTO12_shadow_intermed_6 <= V_D_PC31DOWNTO12_shadow_intermed_5;
V_D_PC31DOWNTO12_shadow_intermed_7 <= V_D_PC31DOWNTO12_shadow_intermed_6;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO12_shadow;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_5;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO12_shadow;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_4;
EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_1 <= EX_ADD_RES32DOWNTO330DOWNTO11_shadow;
EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_2 <= EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_1;
RIN_F_PC31DOWNTO12_intermed_1 <= RIN.F.PC( 31 DOWNTO 12 );
RIN_F_PC31DOWNTO12_intermed_2 <= RIN_F_PC31DOWNTO12_intermed_1;
R_A_CTRL_PC31DOWNTO12_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 12 );
R_A_CTRL_PC31DOWNTO12_intermed_2 <= R_A_CTRL_PC31DOWNTO12_intermed_1;
R_A_CTRL_PC31DOWNTO12_intermed_3 <= R_A_CTRL_PC31DOWNTO12_intermed_2;
R_A_CTRL_PC31DOWNTO12_intermed_4 <= R_A_CTRL_PC31DOWNTO12_intermed_3;
R_A_CTRL_PC31DOWNTO12_intermed_5 <= R_A_CTRL_PC31DOWNTO12_intermed_4;
R_E_CTRL_PC31DOWNTO12_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 12 );
R_E_CTRL_PC31DOWNTO12_intermed_2 <= R_E_CTRL_PC31DOWNTO12_intermed_1;
R_E_CTRL_PC31DOWNTO12_intermed_3 <= R_E_CTRL_PC31DOWNTO12_intermed_2;
R_E_CTRL_PC31DOWNTO12_intermed_4 <= R_E_CTRL_PC31DOWNTO12_intermed_3;
EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO12_shadow;
EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_2 <= EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_1;
RIN_F_PC31DOWNTO12_intermed_1 <= RIN.F.PC ( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_2 <= RIN_A_CTRL_PC31DOWNTO12_intermed_1;
RIN_A_CTRL_PC31DOWNTO12_intermed_3 <= RIN_A_CTRL_PC31DOWNTO12_intermed_2;
RIN_A_CTRL_PC31DOWNTO12_intermed_4 <= RIN_A_CTRL_PC31DOWNTO12_intermed_3;
RIN_A_CTRL_PC31DOWNTO12_intermed_5 <= RIN_A_CTRL_PC31DOWNTO12_intermed_4;
RIN_A_CTRL_PC31DOWNTO12_intermed_6 <= RIN_A_CTRL_PC31DOWNTO12_intermed_5;
RIN_E_CTRL_PC31DOWNTO12_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 12 );
RIN_E_CTRL_PC31DOWNTO12_intermed_2 <= RIN_E_CTRL_PC31DOWNTO12_intermed_1;
RIN_E_CTRL_PC31DOWNTO12_intermed_3 <= RIN_E_CTRL_PC31DOWNTO12_intermed_2;
RIN_E_CTRL_PC31DOWNTO12_intermed_4 <= RIN_E_CTRL_PC31DOWNTO12_intermed_3;
RIN_E_CTRL_PC31DOWNTO12_intermed_5 <= RIN_E_CTRL_PC31DOWNTO12_intermed_4;
V_F_PC31DOWNTO12_shadow_intermed_1 <= V_F_PC31DOWNTO12_shadow;
V_F_PC31DOWNTO12_shadow_intermed_2 <= V_F_PC31DOWNTO12_shadow_intermed_1;
IRIN_ADDR31DOWNTO12_intermed_1 <= IRIN.ADDR( 31 DOWNTO 12 );
IRIN_ADDR31DOWNTO12_intermed_2 <= IRIN_ADDR31DOWNTO12_intermed_1;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO12_shadow;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_2;
EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO13_shadow;
EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_2 <= EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_1;
XC_TRAP_ADDRESS31DOWNTO12_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO12_shadow;
R_F_PC31DOWNTO12_intermed_1 <= R.F.PC( 31 DOWNTO 12 );
RIN_M_CTRL_PC31DOWNTO12_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 12 );
RIN_M_CTRL_PC31DOWNTO12_intermed_2 <= RIN_M_CTRL_PC31DOWNTO12_intermed_1;
RIN_M_CTRL_PC31DOWNTO12_intermed_3 <= RIN_M_CTRL_PC31DOWNTO12_intermed_2;
RIN_M_CTRL_PC31DOWNTO12_intermed_4 <= RIN_M_CTRL_PC31DOWNTO12_intermed_3;
IR_ADDR31DOWNTO12_intermed_1 <= IR.ADDR( 31 DOWNTO 12 );
R_X_CTRL_PC31DOWNTO12_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 12 );
R_X_CTRL_PC31DOWNTO12_intermed_2 <= R_X_CTRL_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_1 <= R.D.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_2 <= R_D_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_3 <= R_D_PC31DOWNTO12_intermed_2;
R_D_PC31DOWNTO12_intermed_4 <= R_D_PC31DOWNTO12_intermed_3;
R_D_PC31DOWNTO12_intermed_5 <= R_D_PC31DOWNTO12_intermed_4;
R_D_PC31DOWNTO12_intermed_6 <= R_D_PC31DOWNTO12_intermed_5;
RIN_X_CTRL_PC31DOWNTO12_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 12 );
RIN_X_CTRL_PC31DOWNTO12_intermed_2 <= RIN_X_CTRL_PC31DOWNTO12_intermed_1;
RIN_X_CTRL_PC31DOWNTO12_intermed_3 <= RIN_X_CTRL_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_1 <= RIN.D.PC( 31 DOWNTO 12 );
RIN_D_PC31DOWNTO12_intermed_2 <= RIN_D_PC31DOWNTO12_intermed_1;
RIN_D_PC31DOWNTO12_intermed_3 <= RIN_D_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_4 <= RIN_D_PC31DOWNTO12_intermed_3;
RIN_D_PC31DOWNTO12_intermed_5 <= RIN_D_PC31DOWNTO12_intermed_4;
RIN_D_PC31DOWNTO12_intermed_6 <= RIN_D_PC31DOWNTO12_intermed_5;
RIN_D_PC31DOWNTO12_intermed_7 <= RIN_D_PC31DOWNTO12_intermed_6;
VIR_ADDR31DOWNTO12_shadow_intermed_1 <= VIR_ADDR31DOWNTO12_shadow;
VIR_ADDR31DOWNTO12_shadow_intermed_2 <= VIR_ADDR31DOWNTO12_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO12_shadow;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_3;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_4 <= RIN_M_CTRL_PC31DOWNTO2_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
V_D_PC31DOWNTO2_shadow_intermed_6 <= V_D_PC31DOWNTO2_shadow_intermed_5;
V_D_PC31DOWNTO2_shadow_intermed_7 <= V_D_PC31DOWNTO2_shadow_intermed_6;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_D_PC31DOWNTO2_intermed_6 <= RIN_D_PC31DOWNTO2_intermed_5;
RIN_D_PC31DOWNTO2_intermed_7 <= RIN_D_PC31DOWNTO2_intermed_6;
EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow;
EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_2 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1;
V_F_PC31DOWNTO2_shadow_intermed_1 <= V_F_PC31DOWNTO2_shadow;
V_F_PC31DOWNTO2_shadow_intermed_2 <= V_F_PC31DOWNTO2_shadow_intermed_1;
RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC( 31 DOWNTO 2 );
RIN_F_PC31DOWNTO2_intermed_2 <= RIN_F_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_3 <= RIN_X_CTRL_PC31DOWNTO2_intermed_2;
IRIN_ADDR31DOWNTO2_intermed_1 <= IRIN.ADDR( 31 DOWNTO 2 );
IRIN_ADDR31DOWNTO2_intermed_2 <= IRIN_ADDR31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_5;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_D_PC31DOWNTO2_intermed_5 <= R_D_PC31DOWNTO2_intermed_4;
R_D_PC31DOWNTO2_intermed_6 <= R_D_PC31DOWNTO2_intermed_5;
R_F_PC31DOWNTO2_intermed_1 <= R.F.PC( 31 DOWNTO 2 );
VIR_ADDR31DOWNTO2_shadow_intermed_1 <= VIR_ADDR31DOWNTO2_shadow;
VIR_ADDR31DOWNTO2_shadow_intermed_2 <= VIR_ADDR31DOWNTO2_shadow_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_3 <= R_M_CTRL_PC31DOWNTO2_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_6 <= RIN_A_CTRL_PC31DOWNTO2_intermed_5;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
R_A_CTRL_PC31DOWNTO2_intermed_5 <= R_A_CTRL_PC31DOWNTO2_intermed_4;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
R_X_CTRL_PC31DOWNTO2_intermed_2 <= R_X_CTRL_PC31DOWNTO2_intermed_1;
XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO2_shadow;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_4 <= R_E_CTRL_PC31DOWNTO2_intermed_3;
EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO2_shadow;
EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_2 <= EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1;
RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC ( 31 DOWNTO 2 );
IR_ADDR31DOWNTO2_intermed_1 <= IR.ADDR( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_5 <= RIN_E_CTRL_PC31DOWNTO2_intermed_4;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_4 <= RIN_M_CTRL_PC31DOWNTO2_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
V_D_PC31DOWNTO2_shadow_intermed_6 <= V_D_PC31DOWNTO2_shadow_intermed_5;
V_D_PC31DOWNTO2_shadow_intermed_7 <= V_D_PC31DOWNTO2_shadow_intermed_6;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_D_PC31DOWNTO2_intermed_6 <= RIN_D_PC31DOWNTO2_intermed_5;
RIN_D_PC31DOWNTO2_intermed_7 <= RIN_D_PC31DOWNTO2_intermed_6;
EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow;
V_F_PC31DOWNTO2_shadow_intermed_1 <= V_F_PC31DOWNTO2_shadow;
RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_3 <= RIN_X_CTRL_PC31DOWNTO2_intermed_2;
IRIN_ADDR31DOWNTO2_intermed_1 <= IRIN.ADDR( 31 DOWNTO 2 );
IRIN_ADDR31DOWNTO2_intermed_2 <= IRIN_ADDR31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_5;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_D_PC31DOWNTO2_intermed_5 <= R_D_PC31DOWNTO2_intermed_4;
R_D_PC31DOWNTO2_intermed_6 <= R_D_PC31DOWNTO2_intermed_5;
VIR_ADDR31DOWNTO2_shadow_intermed_1 <= VIR_ADDR31DOWNTO2_shadow;
VIR_ADDR31DOWNTO2_shadow_intermed_2 <= VIR_ADDR31DOWNTO2_shadow_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_3 <= R_M_CTRL_PC31DOWNTO2_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_6 <= RIN_A_CTRL_PC31DOWNTO2_intermed_5;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
R_A_CTRL_PC31DOWNTO2_intermed_5 <= R_A_CTRL_PC31DOWNTO2_intermed_4;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
R_X_CTRL_PC31DOWNTO2_intermed_2 <= R_X_CTRL_PC31DOWNTO2_intermed_1;
XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO2_shadow;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_4 <= R_E_CTRL_PC31DOWNTO2_intermed_3;
EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO2_shadow;
IR_ADDR31DOWNTO2_intermed_1 <= IR.ADDR( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_5 <= RIN_E_CTRL_PC31DOWNTO2_intermed_4;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_D_INST0_intermed_1 <= RIN.D.INST ( 0 );
R_D_INST0_intermed_1 <= R.D.INST( 0 );
V_D_INST0_shadow_intermed_1 <= V_D_INST0_shadow;
V_D_INST0_shadow_intermed_2 <= V_D_INST0_shadow_intermed_1;
RIN_D_INST0_intermed_1 <= RIN.D.INST( 0 );
RIN_D_INST0_intermed_2 <= RIN_D_INST0_intermed_1;
RIN_D_INST1_intermed_1 <= RIN.D.INST ( 1 );
R_D_INST1_intermed_1 <= R.D.INST( 1 );
V_D_INST1_shadow_intermed_1 <= V_D_INST1_shadow;
V_D_INST1_shadow_intermed_2 <= V_D_INST1_shadow_intermed_1;
RIN_D_INST1_intermed_1 <= RIN.D.INST( 1 );
RIN_D_INST1_intermed_2 <= RIN_D_INST1_intermed_1;
RIN_D_SET_intermed_1 <= RIN.D.SET;
RIN_D_MEXC_intermed_1 <= RIN.D.MEXC;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
RIN_E_OP131_intermed_1 <= RIN.E.OP1( 31 );
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 );
V_E_OP131_shadow_intermed_1 <= V_E_OP131_shadow;
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 );
RIN_E_OP231_intermed_1 <= RIN.E.OP2( 31 );
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
V_E_OP231_shadow_intermed_1 <= V_E_OP231_shadow;
V_D_ANNUL_shadow_intermed_1 <= V_D_ANNUL_shadow;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_D_ANNUL_intermed_1 <= RIN.D.ANNUL;
V_X_DATA03_shadow_intermed_1 <= V_X_DATA03_shadow;
V_X_DATA03_shadow_intermed_2 <= V_X_DATA03_shadow_intermed_1;
V_X_DATA03_shadow_intermed_1 <= V_X_DATA03_shadow;
DCO_DATA03_intermed_1 <= DCO.DATA ( 0 )( 3 );
RIN_X_DATA03_intermed_1 <= RIN.X.DATA ( 0 )( 3 );
R_X_DATA03_intermed_1 <= R.X.DATA( 0 )( 3 );
RIN_X_DATA03_intermed_1 <= RIN.X.DATA( 0 )( 3 );
RIN_X_DATA03_intermed_2 <= RIN_X_DATA03_intermed_1;
RIN_E_OP13_intermed_1 <= RIN.E.OP1( 3 );
V_E_OP13_shadow_intermed_1 <= V_E_OP13_shadow;
V_X_DATA03_shadow_intermed_1 <= V_X_DATA03_shadow;
V_X_DATA03_shadow_intermed_2 <= V_X_DATA03_shadow_intermed_1;
V_X_DATA03_shadow_intermed_1 <= V_X_DATA03_shadow;
DCO_DATA03_intermed_1 <= DCO.DATA ( 0 )( 3 );
RIN_X_DATA03_intermed_1 <= RIN.X.DATA ( 0 )( 3 );
R_X_DATA03_intermed_1 <= R.X.DATA( 0 )( 3 );
RIN_X_DATA03_intermed_1 <= RIN.X.DATA( 0 )( 3 );
RIN_X_DATA03_intermed_2 <= RIN_X_DATA03_intermed_1;
RIN_E_OP23_intermed_1 <= RIN.E.OP2( 3 );
V_E_OP23_shadow_intermed_1 <= V_E_OP23_shadow;
R_M_CTRL_PC31DOWNTO12_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 12 );
R_M_CTRL_PC31DOWNTO12_intermed_2 <= R_M_CTRL_PC31DOWNTO12_intermed_1;
R_M_CTRL_PC31DOWNTO12_intermed_3 <= R_M_CTRL_PC31DOWNTO12_intermed_2;
V_D_PC31DOWNTO12_shadow_intermed_1 <= V_D_PC31DOWNTO12_shadow;
V_D_PC31DOWNTO12_shadow_intermed_2 <= V_D_PC31DOWNTO12_shadow_intermed_1;
V_D_PC31DOWNTO12_shadow_intermed_3 <= V_D_PC31DOWNTO12_shadow_intermed_2;
V_D_PC31DOWNTO12_shadow_intermed_4 <= V_D_PC31DOWNTO12_shadow_intermed_3;
V_D_PC31DOWNTO12_shadow_intermed_5 <= V_D_PC31DOWNTO12_shadow_intermed_4;
V_D_PC31DOWNTO12_shadow_intermed_6 <= V_D_PC31DOWNTO12_shadow_intermed_5;
V_D_PC31DOWNTO12_shadow_intermed_7 <= V_D_PC31DOWNTO12_shadow_intermed_6;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO12_shadow;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_5;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO12_shadow;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_4;
EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_1 <= EX_ADD_RES32DOWNTO330DOWNTO11_shadow;
RIN_F_PC31DOWNTO12_intermed_1 <= RIN.F.PC( 31 DOWNTO 12 );
R_A_CTRL_PC31DOWNTO12_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 12 );
R_A_CTRL_PC31DOWNTO12_intermed_2 <= R_A_CTRL_PC31DOWNTO12_intermed_1;
R_A_CTRL_PC31DOWNTO12_intermed_3 <= R_A_CTRL_PC31DOWNTO12_intermed_2;
R_A_CTRL_PC31DOWNTO12_intermed_4 <= R_A_CTRL_PC31DOWNTO12_intermed_3;
R_A_CTRL_PC31DOWNTO12_intermed_5 <= R_A_CTRL_PC31DOWNTO12_intermed_4;
R_E_CTRL_PC31DOWNTO12_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 12 );
R_E_CTRL_PC31DOWNTO12_intermed_2 <= R_E_CTRL_PC31DOWNTO12_intermed_1;
R_E_CTRL_PC31DOWNTO12_intermed_3 <= R_E_CTRL_PC31DOWNTO12_intermed_2;
R_E_CTRL_PC31DOWNTO12_intermed_4 <= R_E_CTRL_PC31DOWNTO12_intermed_3;
EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO12_shadow;
RIN_A_CTRL_PC31DOWNTO12_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_2 <= RIN_A_CTRL_PC31DOWNTO12_intermed_1;
RIN_A_CTRL_PC31DOWNTO12_intermed_3 <= RIN_A_CTRL_PC31DOWNTO12_intermed_2;
RIN_A_CTRL_PC31DOWNTO12_intermed_4 <= RIN_A_CTRL_PC31DOWNTO12_intermed_3;
RIN_A_CTRL_PC31DOWNTO12_intermed_5 <= RIN_A_CTRL_PC31DOWNTO12_intermed_4;
RIN_A_CTRL_PC31DOWNTO12_intermed_6 <= RIN_A_CTRL_PC31DOWNTO12_intermed_5;
RIN_E_CTRL_PC31DOWNTO12_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 12 );
RIN_E_CTRL_PC31DOWNTO12_intermed_2 <= RIN_E_CTRL_PC31DOWNTO12_intermed_1;
RIN_E_CTRL_PC31DOWNTO12_intermed_3 <= RIN_E_CTRL_PC31DOWNTO12_intermed_2;
RIN_E_CTRL_PC31DOWNTO12_intermed_4 <= RIN_E_CTRL_PC31DOWNTO12_intermed_3;
RIN_E_CTRL_PC31DOWNTO12_intermed_5 <= RIN_E_CTRL_PC31DOWNTO12_intermed_4;
V_F_PC31DOWNTO12_shadow_intermed_1 <= V_F_PC31DOWNTO12_shadow;
IRIN_ADDR31DOWNTO12_intermed_1 <= IRIN.ADDR( 31 DOWNTO 12 );
IRIN_ADDR31DOWNTO12_intermed_2 <= IRIN_ADDR31DOWNTO12_intermed_1;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO12_shadow;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_2;
EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO13_shadow;
RIN_M_CTRL_PC31DOWNTO12_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 12 );
RIN_M_CTRL_PC31DOWNTO12_intermed_2 <= RIN_M_CTRL_PC31DOWNTO12_intermed_1;
RIN_M_CTRL_PC31DOWNTO12_intermed_3 <= RIN_M_CTRL_PC31DOWNTO12_intermed_2;
RIN_M_CTRL_PC31DOWNTO12_intermed_4 <= RIN_M_CTRL_PC31DOWNTO12_intermed_3;
IR_ADDR31DOWNTO12_intermed_1 <= IR.ADDR( 31 DOWNTO 12 );
R_X_CTRL_PC31DOWNTO12_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 12 );
R_X_CTRL_PC31DOWNTO12_intermed_2 <= R_X_CTRL_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_1 <= R.D.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_2 <= R_D_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_3 <= R_D_PC31DOWNTO12_intermed_2;
R_D_PC31DOWNTO12_intermed_4 <= R_D_PC31DOWNTO12_intermed_3;
R_D_PC31DOWNTO12_intermed_5 <= R_D_PC31DOWNTO12_intermed_4;
R_D_PC31DOWNTO12_intermed_6 <= R_D_PC31DOWNTO12_intermed_5;
RIN_X_CTRL_PC31DOWNTO12_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 12 );
RIN_X_CTRL_PC31DOWNTO12_intermed_2 <= RIN_X_CTRL_PC31DOWNTO12_intermed_1;
RIN_X_CTRL_PC31DOWNTO12_intermed_3 <= RIN_X_CTRL_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_1 <= RIN.D.PC( 31 DOWNTO 12 );
RIN_D_PC31DOWNTO12_intermed_2 <= RIN_D_PC31DOWNTO12_intermed_1;
RIN_D_PC31DOWNTO12_intermed_3 <= RIN_D_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_4 <= RIN_D_PC31DOWNTO12_intermed_3;
RIN_D_PC31DOWNTO12_intermed_5 <= RIN_D_PC31DOWNTO12_intermed_4;
RIN_D_PC31DOWNTO12_intermed_6 <= RIN_D_PC31DOWNTO12_intermed_5;
RIN_D_PC31DOWNTO12_intermed_7 <= RIN_D_PC31DOWNTO12_intermed_6;
VIR_ADDR31DOWNTO12_shadow_intermed_1 <= VIR_ADDR31DOWNTO12_shadow;
VIR_ADDR31DOWNTO12_shadow_intermed_2 <= VIR_ADDR31DOWNTO12_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO12_shadow;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_3;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_4 <= RIN_M_CTRL_PC31DOWNTO2_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
V_D_PC31DOWNTO2_shadow_intermed_6 <= V_D_PC31DOWNTO2_shadow_intermed_5;
V_D_PC31DOWNTO2_shadow_intermed_7 <= V_D_PC31DOWNTO2_shadow_intermed_6;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_D_PC31DOWNTO2_intermed_6 <= RIN_D_PC31DOWNTO2_intermed_5;
RIN_D_PC31DOWNTO2_intermed_7 <= RIN_D_PC31DOWNTO2_intermed_6;
EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow;
V_F_PC31DOWNTO2_shadow_intermed_1 <= V_F_PC31DOWNTO2_shadow;
RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_3 <= RIN_X_CTRL_PC31DOWNTO2_intermed_2;
IRIN_ADDR31DOWNTO2_intermed_1 <= IRIN.ADDR( 31 DOWNTO 2 );
IRIN_ADDR31DOWNTO2_intermed_2 <= IRIN_ADDR31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_5;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_D_PC31DOWNTO2_intermed_5 <= R_D_PC31DOWNTO2_intermed_4;
R_D_PC31DOWNTO2_intermed_6 <= R_D_PC31DOWNTO2_intermed_5;
VIR_ADDR31DOWNTO2_shadow_intermed_1 <= VIR_ADDR31DOWNTO2_shadow;
VIR_ADDR31DOWNTO2_shadow_intermed_2 <= VIR_ADDR31DOWNTO2_shadow_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_3 <= R_M_CTRL_PC31DOWNTO2_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_6 <= RIN_A_CTRL_PC31DOWNTO2_intermed_5;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
R_A_CTRL_PC31DOWNTO2_intermed_5 <= R_A_CTRL_PC31DOWNTO2_intermed_4;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
R_X_CTRL_PC31DOWNTO2_intermed_2 <= R_X_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_4 <= R_E_CTRL_PC31DOWNTO2_intermed_3;
EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO2_shadow;
IR_ADDR31DOWNTO2_intermed_1 <= IR.ADDR( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_5 <= RIN_E_CTRL_PC31DOWNTO2_intermed_4;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_4 <= RIN_M_CTRL_PC31DOWNTO2_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
V_D_PC31DOWNTO2_shadow_intermed_6 <= V_D_PC31DOWNTO2_shadow_intermed_5;
V_D_PC31DOWNTO2_shadow_intermed_7 <= V_D_PC31DOWNTO2_shadow_intermed_6;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_D_PC31DOWNTO2_intermed_6 <= RIN_D_PC31DOWNTO2_intermed_5;
RIN_D_PC31DOWNTO2_intermed_7 <= RIN_D_PC31DOWNTO2_intermed_6;
EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow;
RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_3 <= RIN_X_CTRL_PC31DOWNTO2_intermed_2;
IRIN_ADDR31DOWNTO2_intermed_1 <= IRIN.ADDR( 31 DOWNTO 2 );
IRIN_ADDR31DOWNTO2_intermed_2 <= IRIN_ADDR31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_5;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_D_PC31DOWNTO2_intermed_5 <= R_D_PC31DOWNTO2_intermed_4;
R_D_PC31DOWNTO2_intermed_6 <= R_D_PC31DOWNTO2_intermed_5;
VIR_ADDR31DOWNTO2_shadow_intermed_1 <= VIR_ADDR31DOWNTO2_shadow;
VIR_ADDR31DOWNTO2_shadow_intermed_2 <= VIR_ADDR31DOWNTO2_shadow_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_3 <= R_M_CTRL_PC31DOWNTO2_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_6 <= RIN_A_CTRL_PC31DOWNTO2_intermed_5;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
R_A_CTRL_PC31DOWNTO2_intermed_5 <= R_A_CTRL_PC31DOWNTO2_intermed_4;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
R_X_CTRL_PC31DOWNTO2_intermed_2 <= R_X_CTRL_PC31DOWNTO2_intermed_1;
XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO2_shadow;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_4 <= R_E_CTRL_PC31DOWNTO2_intermed_3;
EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO2_shadow;
IR_ADDR31DOWNTO2_intermed_1 <= IR.ADDR( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_5 <= RIN_E_CTRL_PC31DOWNTO2_intermed_4;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 );
RIN_E_OP231_intermed_1 <= RIN.E.OP2( 31 );
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
V_E_OP231_shadow_intermed_1 <= V_E_OP231_shadow;
V_M_CTRL_RD7DOWNTO0_shadow_intermed_1 <= V_M_CTRL_RD7DOWNTO0_shadow;
V_M_CTRL_RD7DOWNTO0_shadow_intermed_2 <= V_M_CTRL_RD7DOWNTO0_shadow_intermed_1;
V_E_CTRL_RD7DOWNTO0_shadow_intermed_1 <= V_E_CTRL_RD7DOWNTO0_shadow;
V_E_CTRL_RD7DOWNTO0_shadow_intermed_2 <= V_E_CTRL_RD7DOWNTO0_shadow_intermed_1;
V_E_CTRL_RD7DOWNTO0_shadow_intermed_3 <= V_E_CTRL_RD7DOWNTO0_shadow_intermed_2;
R_E_CTRL_RD7DOWNTO0_intermed_1 <= R.E.CTRL.RD ( 7 DOWNTO 0 );
R_E_CTRL_RD7DOWNTO0_intermed_2 <= R_E_CTRL_RD7DOWNTO0_intermed_1;
V_A_CTRL_RD7DOWNTO0_shadow_intermed_1 <= V_A_CTRL_RD7DOWNTO0_shadow;
V_A_CTRL_RD7DOWNTO0_shadow_intermed_2 <= V_A_CTRL_RD7DOWNTO0_shadow_intermed_1;
V_A_CTRL_RD7DOWNTO0_shadow_intermed_3 <= V_A_CTRL_RD7DOWNTO0_shadow_intermed_2;
V_A_CTRL_RD7DOWNTO0_shadow_intermed_4 <= V_A_CTRL_RD7DOWNTO0_shadow_intermed_3;
RIN_A_CTRL_RD7DOWNTO0_intermed_1 <= RIN.A.CTRL.RD ( 7 DOWNTO 0 );
RIN_A_CTRL_RD7DOWNTO0_intermed_2 <= RIN_A_CTRL_RD7DOWNTO0_intermed_1;
RIN_A_CTRL_RD7DOWNTO0_intermed_3 <= RIN_A_CTRL_RD7DOWNTO0_intermed_2;
RIN_A_CTRL_RD7DOWNTO0_intermed_4 <= RIN_A_CTRL_RD7DOWNTO0_intermed_3;
R_M_CTRL_RD7DOWNTO0_intermed_1 <= R.M.CTRL.RD ( 7 DOWNTO 0 );
R_A_CTRL_RD7DOWNTO0_intermed_1 <= R.A.CTRL.RD ( 7 DOWNTO 0 );
R_A_CTRL_RD7DOWNTO0_intermed_2 <= R_A_CTRL_RD7DOWNTO0_intermed_1;
R_A_CTRL_RD7DOWNTO0_intermed_3 <= R_A_CTRL_RD7DOWNTO0_intermed_2;
RIN_E_CTRL_RD7DOWNTO0_intermed_1 <= RIN.E.CTRL.RD ( 7 DOWNTO 0 );
RIN_E_CTRL_RD7DOWNTO0_intermed_2 <= RIN_E_CTRL_RD7DOWNTO0_intermed_1;
RIN_E_CTRL_RD7DOWNTO0_intermed_3 <= RIN_E_CTRL_RD7DOWNTO0_intermed_2;
RIN_X_CTRL_RD7DOWNTO0_intermed_1 <= RIN.X.CTRL.RD ( 7 DOWNTO 0 );
RIN_M_CTRL_RD7DOWNTO0_intermed_1 <= RIN.M.CTRL.RD ( 7 DOWNTO 0 );
RIN_M_CTRL_RD7DOWNTO0_intermed_2 <= RIN_M_CTRL_RD7DOWNTO0_intermed_1;
RIN_X_CTRL_TRAP_intermed_1 <= RIN.X.CTRL.TRAP;
V_A_CTRL_TRAP_shadow_intermed_1 <= V_A_CTRL_TRAP_shadow;
V_A_CTRL_TRAP_shadow_intermed_2 <= V_A_CTRL_TRAP_shadow_intermed_1;
V_A_CTRL_TRAP_shadow_intermed_3 <= V_A_CTRL_TRAP_shadow_intermed_2;
V_A_CTRL_TRAP_shadow_intermed_4 <= V_A_CTRL_TRAP_shadow_intermed_3;
ICO_MEXC_intermed_1 <= ICO.MEXC;
ICO_MEXC_intermed_2 <= ICO_MEXC_intermed_1;
ICO_MEXC_intermed_3 <= ICO_MEXC_intermed_2;
ICO_MEXC_intermed_4 <= ICO_MEXC_intermed_3;
ICO_MEXC_intermed_5 <= ICO_MEXC_intermed_4;
R_E_CTRL_TRAP_intermed_1 <= R.E.CTRL.TRAP;
R_E_CTRL_TRAP_intermed_2 <= R_E_CTRL_TRAP_intermed_1;
RIN_A_CTRL_TRAP_intermed_1 <= RIN.A.CTRL.TRAP;
RIN_A_CTRL_TRAP_intermed_2 <= RIN_A_CTRL_TRAP_intermed_1;
RIN_A_CTRL_TRAP_intermed_3 <= RIN_A_CTRL_TRAP_intermed_2;
RIN_A_CTRL_TRAP_intermed_4 <= RIN_A_CTRL_TRAP_intermed_3;
V_E_CTRL_TRAP_shadow_intermed_1 <= V_E_CTRL_TRAP_shadow;
V_E_CTRL_TRAP_shadow_intermed_2 <= V_E_CTRL_TRAP_shadow_intermed_1;
V_E_CTRL_TRAP_shadow_intermed_3 <= V_E_CTRL_TRAP_shadow_intermed_2;
RIN_E_CTRL_TRAP_intermed_1 <= RIN.E.CTRL.TRAP;
RIN_E_CTRL_TRAP_intermed_2 <= RIN_E_CTRL_TRAP_intermed_1;
RIN_E_CTRL_TRAP_intermed_3 <= RIN_E_CTRL_TRAP_intermed_2;
R_D_MEXC_intermed_1 <= R.D.MEXC;
R_D_MEXC_intermed_2 <= R_D_MEXC_intermed_1;
R_D_MEXC_intermed_3 <= R_D_MEXC_intermed_2;
R_D_MEXC_intermed_4 <= R_D_MEXC_intermed_3;
V_M_CTRL_TRAP_shadow_intermed_1 <= V_M_CTRL_TRAP_shadow;
V_M_CTRL_TRAP_shadow_intermed_2 <= V_M_CTRL_TRAP_shadow_intermed_1;
V_D_MEXC_shadow_intermed_1 <= V_D_MEXC_shadow;
V_D_MEXC_shadow_intermed_2 <= V_D_MEXC_shadow_intermed_1;
V_D_MEXC_shadow_intermed_3 <= V_D_MEXC_shadow_intermed_2;
V_D_MEXC_shadow_intermed_4 <= V_D_MEXC_shadow_intermed_3;
V_D_MEXC_shadow_intermed_5 <= V_D_MEXC_shadow_intermed_4;
R_A_CTRL_TRAP_intermed_1 <= R.A.CTRL.TRAP;
R_A_CTRL_TRAP_intermed_2 <= R_A_CTRL_TRAP_intermed_1;
R_A_CTRL_TRAP_intermed_3 <= R_A_CTRL_TRAP_intermed_2;
RIN_M_CTRL_TRAP_intermed_1 <= RIN.M.CTRL.TRAP;
RIN_M_CTRL_TRAP_intermed_2 <= RIN_M_CTRL_TRAP_intermed_1;
R_M_CTRL_TRAP_intermed_1 <= R.M.CTRL.TRAP;
RIN_D_MEXC_intermed_1 <= RIN.D.MEXC;
RIN_D_MEXC_intermed_2 <= RIN_D_MEXC_intermed_1;
RIN_D_MEXC_intermed_3 <= RIN_D_MEXC_intermed_2;
RIN_D_MEXC_intermed_4 <= RIN_D_MEXC_intermed_3;
RIN_D_MEXC_intermed_5 <= RIN_D_MEXC_intermed_4;
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 );
V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow;
V_X_RESULT6DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO0_shadow_intermed_1;
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 );
RIN_X_RESULT6DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO0_intermed_1;
R_X_RESULT6DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 );
RIN_D_PC_intermed_1 <= RIN.D.PC;
RIN_D_PC_intermed_2 <= RIN_D_PC_intermed_1;
RIN_D_PC_intermed_3 <= RIN_D_PC_intermed_2;
RIN_D_PC_intermed_4 <= RIN_D_PC_intermed_3;
RIN_D_PC_intermed_5 <= RIN_D_PC_intermed_4;
RIN_A_CTRL_PC_intermed_1 <= RIN.A.CTRL.PC;
RIN_A_CTRL_PC_intermed_2 <= RIN_A_CTRL_PC_intermed_1;
RIN_A_CTRL_PC_intermed_3 <= RIN_A_CTRL_PC_intermed_2;
RIN_A_CTRL_PC_intermed_4 <= RIN_A_CTRL_PC_intermed_3;
R_A_CTRL_PC_intermed_1 <= R.A.CTRL.PC;
R_A_CTRL_PC_intermed_2 <= R_A_CTRL_PC_intermed_1;
R_A_CTRL_PC_intermed_3 <= R_A_CTRL_PC_intermed_2;
V_E_CTRL_PC_shadow_intermed_1 <= V_E_CTRL_PC_shadow;
V_E_CTRL_PC_shadow_intermed_2 <= V_E_CTRL_PC_shadow_intermed_1;
V_E_CTRL_PC_shadow_intermed_3 <= V_E_CTRL_PC_shadow_intermed_2;
R_M_CTRL_PC_intermed_1 <= R.M.CTRL.PC;
R_E_CTRL_PC_intermed_1 <= R.E.CTRL.PC;
R_E_CTRL_PC_intermed_2 <= R_E_CTRL_PC_intermed_1;
RIN_M_CTRL_PC_intermed_1 <= RIN.M.CTRL.PC;
RIN_M_CTRL_PC_intermed_2 <= RIN_M_CTRL_PC_intermed_1;
V_M_CTRL_PC_shadow_intermed_1 <= V_M_CTRL_PC_shadow;
V_M_CTRL_PC_shadow_intermed_2 <= V_M_CTRL_PC_shadow_intermed_1;
V_A_CTRL_PC_shadow_intermed_1 <= V_A_CTRL_PC_shadow;
V_A_CTRL_PC_shadow_intermed_2 <= V_A_CTRL_PC_shadow_intermed_1;
V_A_CTRL_PC_shadow_intermed_3 <= V_A_CTRL_PC_shadow_intermed_2;
V_A_CTRL_PC_shadow_intermed_4 <= V_A_CTRL_PC_shadow_intermed_3;
R_D_PC_intermed_1 <= R.D.PC;
R_D_PC_intermed_2 <= R_D_PC_intermed_1;
R_D_PC_intermed_3 <= R_D_PC_intermed_2;
R_D_PC_intermed_4 <= R_D_PC_intermed_3;
RIN_E_CTRL_PC_intermed_1 <= RIN.E.CTRL.PC;
RIN_E_CTRL_PC_intermed_2 <= RIN_E_CTRL_PC_intermed_1;
RIN_E_CTRL_PC_intermed_3 <= RIN_E_CTRL_PC_intermed_2;
RIN_X_CTRL_PC_intermed_1 <= RIN.X.CTRL.PC;
V_D_PC_shadow_intermed_1 <= V_D_PC_shadow;
V_D_PC_shadow_intermed_2 <= V_D_PC_shadow_intermed_1;
V_D_PC_shadow_intermed_3 <= V_D_PC_shadow_intermed_2;
V_D_PC_shadow_intermed_4 <= V_D_PC_shadow_intermed_3;
V_D_PC_shadow_intermed_5 <= V_D_PC_shadow_intermed_4;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2;
RIN_A_CTRL_ANNUL_intermed_4 <= RIN_A_CTRL_ANNUL_intermed_3;
RIN_A_CTRL_ANNUL_intermed_5 <= RIN_A_CTRL_ANNUL_intermed_4;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1;
R_A_CTRL_ANNUL_intermed_3 <= R_A_CTRL_ANNUL_intermed_2;
R_A_CTRL_ANNUL_intermed_4 <= R_A_CTRL_ANNUL_intermed_3;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
R_X_ANNUL_ALL_intermed_2 <= R_X_ANNUL_ALL_intermed_1;
R_X_ANNUL_ALL_intermed_3 <= R_X_ANNUL_ALL_intermed_2;
R_X_ANNUL_ALL_intermed_4 <= R_X_ANNUL_ALL_intermed_3;
RIN_X_CTRL_WREG_intermed_1 <= RIN.X.CTRL.WREG;
RIN_M_CTRL_WREG_intermed_1 <= RIN.M.CTRL.WREG;
RIN_M_CTRL_WREG_intermed_2 <= RIN_M_CTRL_WREG_intermed_1;
RIN_A_CTRL_WREG_intermed_1 <= RIN.A.CTRL.WREG;
RIN_A_CTRL_WREG_intermed_2 <= RIN_A_CTRL_WREG_intermed_1;
RIN_A_CTRL_WREG_intermed_3 <= RIN_A_CTRL_WREG_intermed_2;
RIN_A_CTRL_WREG_intermed_4 <= RIN_A_CTRL_WREG_intermed_3;
V_A_CTRL_WREG_shadow_intermed_1 <= V_A_CTRL_WREG_shadow;
V_A_CTRL_WREG_shadow_intermed_2 <= V_A_CTRL_WREG_shadow_intermed_1;
V_A_CTRL_WREG_shadow_intermed_3 <= V_A_CTRL_WREG_shadow_intermed_2;
V_A_CTRL_WREG_shadow_intermed_4 <= V_A_CTRL_WREG_shadow_intermed_3;
R_A_CTRL_WREG_intermed_1 <= R.A.CTRL.WREG;
R_A_CTRL_WREG_intermed_2 <= R_A_CTRL_WREG_intermed_1;
R_A_CTRL_WREG_intermed_3 <= R_A_CTRL_WREG_intermed_2;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
V_X_ANNUL_ALL_shadow_intermed_2 <= V_X_ANNUL_ALL_shadow_intermed_1;
V_X_ANNUL_ALL_shadow_intermed_3 <= V_X_ANNUL_ALL_shadow_intermed_2;
V_X_ANNUL_ALL_shadow_intermed_4 <= V_X_ANNUL_ALL_shadow_intermed_3;
R_M_CTRL_WREG_intermed_1 <= R.M.CTRL.WREG;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
RIN_X_ANNUL_ALL_intermed_3 <= RIN_X_ANNUL_ALL_intermed_2;
RIN_X_ANNUL_ALL_intermed_4 <= RIN_X_ANNUL_ALL_intermed_3;
RIN_X_ANNUL_ALL_intermed_5 <= RIN_X_ANNUL_ALL_intermed_4;
V_M_CTRL_WREG_shadow_intermed_1 <= V_M_CTRL_WREG_shadow;
V_M_CTRL_WREG_shadow_intermed_2 <= V_M_CTRL_WREG_shadow_intermed_1;
R_E_CTRL_WREG_intermed_1 <= R.E.CTRL.WREG;
R_E_CTRL_WREG_intermed_2 <= R_E_CTRL_WREG_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_3 <= V_A_CTRL_ANNUL_shadow_intermed_2;
V_A_CTRL_ANNUL_shadow_intermed_4 <= V_A_CTRL_ANNUL_shadow_intermed_3;
RIN_E_CTRL_WREG_intermed_1 <= RIN.E.CTRL.WREG;
RIN_E_CTRL_WREG_intermed_2 <= RIN_E_CTRL_WREG_intermed_1;
RIN_E_CTRL_WREG_intermed_3 <= RIN_E_CTRL_WREG_intermed_2;
V_E_CTRL_WREG_shadow_intermed_1 <= V_E_CTRL_WREG_shadow;
V_E_CTRL_WREG_shadow_intermed_2 <= V_E_CTRL_WREG_shadow_intermed_1;
V_E_CTRL_WREG_shadow_intermed_3 <= V_E_CTRL_WREG_shadow_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC ( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC ( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC ( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC ( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC ( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC ( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
V_X_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_X_CTRL_TT3DOWNTO0_shadow;
V_X_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_X_CTRL_TT3DOWNTO0_shadow_intermed_1;
R_M_CTRL_TT3DOWNTO0_intermed_1 <= R.M.CTRL.TT( 3 DOWNTO 0 );
R_M_CTRL_TT3DOWNTO0_intermed_2 <= R_M_CTRL_TT3DOWNTO0_intermed_1;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_3 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2;
R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
R_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= R_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
R_A_CTRL_TT3DOWNTO0_intermed_1 <= R.A.CTRL.TT( 3 DOWNTO 0 );
R_A_CTRL_TT3DOWNTO0_intermed_2 <= R_A_CTRL_TT3DOWNTO0_intermed_1;
R_A_CTRL_TT3DOWNTO0_intermed_3 <= R_A_CTRL_TT3DOWNTO0_intermed_2;
R_A_CTRL_TT3DOWNTO0_intermed_4 <= R_A_CTRL_TT3DOWNTO0_intermed_3;
RIN_A_CTRL_TT3DOWNTO0_intermed_1 <= RIN.A.CTRL.TT( 3 DOWNTO 0 );
RIN_A_CTRL_TT3DOWNTO0_intermed_2 <= RIN_A_CTRL_TT3DOWNTO0_intermed_1;
RIN_A_CTRL_TT3DOWNTO0_intermed_3 <= RIN_A_CTRL_TT3DOWNTO0_intermed_2;
RIN_A_CTRL_TT3DOWNTO0_intermed_4 <= RIN_A_CTRL_TT3DOWNTO0_intermed_3;
RIN_A_CTRL_TT3DOWNTO0_intermed_5 <= RIN_A_CTRL_TT3DOWNTO0_intermed_4;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_A_CTRL_TT3DOWNTO0_shadow;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_2;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_4 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_3;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_5 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_4;
RIN_W_S_TT3DOWNTO0_intermed_1 <= RIN.W.S.TT( 3 DOWNTO 0 );
RIN_W_S_TT3DOWNTO0_intermed_2 <= RIN_W_S_TT3DOWNTO0_intermed_1;
R_E_CTRL_TT3DOWNTO0_intermed_1 <= R.E.CTRL.TT( 3 DOWNTO 0 );
R_E_CTRL_TT3DOWNTO0_intermed_2 <= R_E_CTRL_TT3DOWNTO0_intermed_1;
R_E_CTRL_TT3DOWNTO0_intermed_3 <= R_E_CTRL_TT3DOWNTO0_intermed_2;
RIN_W_S_TT3DOWNTO0_intermed_1 <= RIN.W.S.TT ( 3 DOWNTO 0 );
RIN_M_CTRL_TT3DOWNTO0_intermed_1 <= RIN.M.CTRL.TT( 3 DOWNTO 0 );
RIN_M_CTRL_TT3DOWNTO0_intermed_2 <= RIN_M_CTRL_TT3DOWNTO0_intermed_1;
RIN_M_CTRL_TT3DOWNTO0_intermed_3 <= RIN_M_CTRL_TT3DOWNTO0_intermed_2;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_M_CTRL_TT3DOWNTO0_shadow;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_M_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_M_CTRL_TT3DOWNTO0_shadow_intermed_2;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_3 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
R_W_S_TT3DOWNTO0_intermed_1 <= R.W.S.TT( 3 DOWNTO 0 );
R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 );
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_E_CTRL_TT3DOWNTO0_shadow;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_2;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_4 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_3;
RIN_X_CTRL_TT3DOWNTO0_intermed_1 <= RIN.X.CTRL.TT( 3 DOWNTO 0 );
RIN_X_CTRL_TT3DOWNTO0_intermed_2 <= RIN_X_CTRL_TT3DOWNTO0_intermed_1;
V_W_S_TT3DOWNTO0_shadow_intermed_1 <= V_W_S_TT3DOWNTO0_shadow;
V_W_S_TT3DOWNTO0_shadow_intermed_2 <= V_W_S_TT3DOWNTO0_shadow_intermed_1;
R_X_CTRL_TT3DOWNTO0_intermed_1 <= R.X.CTRL.TT( 3 DOWNTO 0 );
RIN_E_CTRL_TT3DOWNTO0_intermed_1 <= RIN.E.CTRL.TT( 3 DOWNTO 0 );
RIN_E_CTRL_TT3DOWNTO0_intermed_2 <= RIN_E_CTRL_TT3DOWNTO0_intermed_1;
RIN_E_CTRL_TT3DOWNTO0_intermed_3 <= RIN_E_CTRL_TT3DOWNTO0_intermed_2;
RIN_E_CTRL_TT3DOWNTO0_intermed_4 <= RIN_E_CTRL_TT3DOWNTO0_intermed_3;
XC_VECTT3DOWNTO0_shadow_intermed_1 <= XC_VECTT3DOWNTO0_shadow;
V_M_RESULT1DOWNTO0_shadow_intermed_1 <= V_M_RESULT1DOWNTO0_shadow;
V_M_RESULT1DOWNTO0_shadow_intermed_2 <= V_M_RESULT1DOWNTO0_shadow_intermed_1;
RIN_M_RESULT1DOWNTO0_intermed_1 <= RIN.M.RESULT( 1 DOWNTO 0 );
RIN_M_RESULT1DOWNTO0_intermed_2 <= RIN_M_RESULT1DOWNTO0_intermed_1;
R_M_RESULT1DOWNTO0_intermed_1 <= R.M.RESULT( 1 DOWNTO 0 );
RIN_M_RESULT1DOWNTO0_intermed_1 <= RIN.M.RESULT ( 1 DOWNTO 0 );
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
V_X_DATA031_shadow_intermed_3 <= V_X_DATA031_shadow_intermed_2;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
RIN_X_DATA031_intermed_3 <= RIN_X_DATA031_intermed_2;
DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 );
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 ) ( 31 );
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
R_X_DATA031_intermed_2 <= R_X_DATA031_intermed_1;
R_X_DATA031_intermed_1 <= R.X.DATA ( 0 )( 31 );
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 );
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_A_CTRL_INST19_shadow_intermed_3 <= V_A_CTRL_INST19_shadow_intermed_2;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_CTRL_INST19_shadow_intermed_2 <= V_E_CTRL_INST19_shadow_intermed_1;
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
RIN_A_CTRL_INST19_intermed_3 <= RIN_A_CTRL_INST19_intermed_2;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST ( 19 );
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST( 19 );
RIN_E_CTRL_INST19_intermed_2 <= RIN_E_CTRL_INST19_intermed_1;
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
DE_INST19_shadow_intermed_2 <= DE_INST19_shadow_intermed_1;
R_E_CTRL_INST19_intermed_1 <= R.E.CTRL.INST( 19 );
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
R_A_CTRL_INST19_intermed_2 <= R_A_CTRL_INST19_intermed_1;
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST ( 19 );
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST ( 20 );
RIN_A_CTRL_INST20_intermed_2 <= RIN_A_CTRL_INST20_intermed_1;
R_A_CTRL_INST20_intermed_1 <= R.A.CTRL.INST ( 20 );
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST( 20 );
RIN_A_CTRL_INST20_intermed_2 <= RIN_A_CTRL_INST20_intermed_1;
RIN_A_CTRL_INST20_intermed_3 <= RIN_A_CTRL_INST20_intermed_2;
V_E_CTRL_INST20_shadow_intermed_1 <= V_E_CTRL_INST20_shadow;
V_E_CTRL_INST20_shadow_intermed_2 <= V_E_CTRL_INST20_shadow_intermed_1;
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
V_A_CTRL_INST20_shadow_intermed_2 <= V_A_CTRL_INST20_shadow_intermed_1;
V_A_CTRL_INST20_shadow_intermed_3 <= V_A_CTRL_INST20_shadow_intermed_2;
RIN_E_CTRL_INST20_intermed_1 <= RIN.E.CTRL.INST( 20 );
RIN_E_CTRL_INST20_intermed_2 <= RIN_E_CTRL_INST20_intermed_1;
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
V_A_CTRL_INST20_shadow_intermed_2 <= V_A_CTRL_INST20_shadow_intermed_1;
RIN_E_CTRL_INST20_intermed_1 <= RIN.E.CTRL.INST ( 20 );
R_E_CTRL_INST20_intermed_1 <= R.E.CTRL.INST( 20 );
DE_INST20_shadow_intermed_1 <= DE_INST20_shadow;
DE_INST20_shadow_intermed_2 <= DE_INST20_shadow_intermed_1;
R_A_CTRL_INST20_intermed_1 <= R.A.CTRL.INST( 20 );
R_A_CTRL_INST20_intermed_2 <= R_A_CTRL_INST20_intermed_1;
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
V_X_DATA00_shadow_intermed_2 <= V_X_DATA00_shadow_intermed_1;
RIN_X_DATA00_intermed_1 <= RIN.X.DATA ( 0 ) ( 0 );
R_X_DATA00_intermed_1 <= R.X.DATA( 0 )( 0 );
R_X_DATA00_intermed_2 <= R_X_DATA00_intermed_1;
RIN_X_DATA00_intermed_1 <= RIN.X.DATA ( 0 )( 0 );
RIN_X_DATA00_intermed_2 <= RIN_X_DATA00_intermed_1;
DCO_DATA00_intermed_1 <= DCO.DATA ( 0 )( 0 );
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
V_X_DATA00_shadow_intermed_2 <= V_X_DATA00_shadow_intermed_1;
V_X_DATA00_shadow_intermed_3 <= V_X_DATA00_shadow_intermed_2;
R_X_DATA00_intermed_1 <= R.X.DATA ( 0 )( 0 );
RIN_X_DATA00_intermed_1 <= RIN.X.DATA( 0 )( 0 );
RIN_X_DATA00_intermed_2 <= RIN_X_DATA00_intermed_1;
RIN_X_DATA00_intermed_3 <= RIN_X_DATA00_intermed_2;
R_X_DATA00_intermed_1 <= R.X.DATA( 0 )( 0 );
RIN_X_DATA00_intermed_1 <= RIN.X.DATA ( 0 )( 0 );
DCO_DATA00_intermed_1 <= DCO.DATA ( 0 )( 0 );
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
V_X_DATA00_shadow_intermed_2 <= V_X_DATA00_shadow_intermed_1;
RIN_X_DATA00_intermed_1 <= RIN.X.DATA( 0 )( 0 );
RIN_X_DATA00_intermed_2 <= RIN_X_DATA00_intermed_1;
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA ( 0 ) ( 4 DOWNTO 0 );
R_X_DATA04DOWNTO0_intermed_1 <= R.X.DATA( 0 )( 4 DOWNTO 0 );
R_X_DATA04DOWNTO0_intermed_2 <= R_X_DATA04DOWNTO0_intermed_1;
R_X_DATA04DOWNTO0_intermed_1 <= R.X.DATA ( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_2 <= RIN_X_DATA04DOWNTO0_intermed_1;
RIN_X_DATA04DOWNTO0_intermed_3 <= RIN_X_DATA04DOWNTO0_intermed_2;
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
V_X_DATA04DOWNTO0_shadow_intermed_2 <= V_X_DATA04DOWNTO0_shadow_intermed_1;
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
V_X_DATA04DOWNTO0_shadow_intermed_2 <= V_X_DATA04DOWNTO0_shadow_intermed_1;
V_X_DATA04DOWNTO0_shadow_intermed_3 <= V_X_DATA04DOWNTO0_shadow_intermed_2;
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA ( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_2 <= RIN_X_DATA04DOWNTO0_intermed_1;
DCO_DATA04DOWNTO0_intermed_1 <= DCO.DATA ( 0 )( 4 DOWNTO 0 );
R_X_DATA04DOWNTO0_intermed_1 <= R.X.DATA( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_2 <= RIN_X_DATA04DOWNTO0_intermed_1;
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
V_X_DATA04DOWNTO0_shadow_intermed_2 <= V_X_DATA04DOWNTO0_shadow_intermed_1;
DCO_DATA04DOWNTO0_intermed_1 <= DCO.DATA ( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA ( 0 )( 4 DOWNTO 0 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC ( 31 DOWNTO 2 );
R_A_CTRL_INST24_intermed_1 <= R.A.CTRL.INST( 24 );
R_A_CTRL_INST24_intermed_2 <= R_A_CTRL_INST24_intermed_1;
RIN_E_CTRL_INST24_intermed_1 <= RIN.E.CTRL.INST( 24 );
RIN_E_CTRL_INST24_intermed_2 <= RIN_E_CTRL_INST24_intermed_1;
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST( 24 );
RIN_A_CTRL_INST24_intermed_2 <= RIN_A_CTRL_INST24_intermed_1;
RIN_A_CTRL_INST24_intermed_3 <= RIN_A_CTRL_INST24_intermed_2;
R_E_CTRL_INST24_intermed_1 <= R.E.CTRL.INST( 24 );
R_A_CTRL_INST24_intermed_1 <= R.A.CTRL.INST ( 24 );
V_A_CTRL_INST24_shadow_intermed_1 <= V_A_CTRL_INST24_shadow;
V_A_CTRL_INST24_shadow_intermed_2 <= V_A_CTRL_INST24_shadow_intermed_1;
V_A_CTRL_INST24_shadow_intermed_3 <= V_A_CTRL_INST24_shadow_intermed_2;
V_E_CTRL_INST24_shadow_intermed_1 <= V_E_CTRL_INST24_shadow;
V_E_CTRL_INST24_shadow_intermed_2 <= V_E_CTRL_INST24_shadow_intermed_1;
DE_INST24_shadow_intermed_1 <= DE_INST24_shadow;
DE_INST24_shadow_intermed_2 <= DE_INST24_shadow_intermed_1;
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST ( 24 );
RIN_A_CTRL_INST24_intermed_2 <= RIN_A_CTRL_INST24_intermed_1;
V_A_CTRL_INST24_shadow_intermed_1 <= V_A_CTRL_INST24_shadow;
V_A_CTRL_INST24_shadow_intermed_2 <= V_A_CTRL_INST24_shadow_intermed_1;
RIN_E_CTRL_INST24_intermed_1 <= RIN.E.CTRL.INST ( 24 );
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
RIN_M_Y31_intermed_1 <= RIN.M.Y ( 31 );
V_M_Y31_shadow_intermed_1 <= V_M_Y31_shadow;
V_M_Y31_shadow_intermed_2 <= V_M_Y31_shadow_intermed_1;
RIN_M_Y31_intermed_1 <= RIN.M.Y( 31 );
RIN_M_Y31_intermed_2 <= RIN_M_Y31_intermed_1;
R_M_Y31_intermed_1 <= R.M.Y( 31 );
DSUIN_CRDY2_intermed_1 <= DSUIN.CRDY ( 2 );
VDSU_CRDY2_shadow_intermed_1 <= VDSU_CRDY2_shadow;
VDSU_CRDY2_shadow_intermed_2 <= VDSU_CRDY2_shadow_intermed_1;
DSUIN_CRDY2_intermed_1 <= DSUIN.CRDY( 2 );
DSUIN_CRDY2_intermed_2 <= DSUIN_CRDY2_intermed_1;
DSUR_CRDY2_intermed_1 <= DSUR.CRDY( 2 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC ( 31 DOWNTO 2 );
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
DE_INST_shadow_intermed_1 <= DE_INST_shadow;
DE_INST_shadow_intermed_2 <= DE_INST_shadow_intermed_1;
V_A_CTRL_INST_shadow_intermed_1 <= V_A_CTRL_INST_shadow;
V_A_CTRL_INST_shadow_intermed_2 <= V_A_CTRL_INST_shadow_intermed_1;
RIN_A_CTRL_INST_intermed_1 <= RIN.A.CTRL.INST;
RIN_A_CTRL_INST_intermed_2 <= RIN_A_CTRL_INST_intermed_1;
RIN_E_CTRL_INST_intermed_1 <= RIN.E.CTRL.INST;
R_A_CTRL_INST_intermed_1 <= R.A.CTRL.INST;
RIN_D_CNT_intermed_1 <= RIN.D.CNT;
RIN_D_CNT_intermed_2 <= RIN_D_CNT_intermed_1;
RIN_D_CNT_intermed_3 <= RIN_D_CNT_intermed_2;
V_A_CTRL_CNT_shadow_intermed_1 <= V_A_CTRL_CNT_shadow;
V_A_CTRL_CNT_shadow_intermed_2 <= V_A_CTRL_CNT_shadow_intermed_1;
R_A_CTRL_CNT_intermed_1 <= R.A.CTRL.CNT;
V_D_CNT_shadow_intermed_1 <= V_D_CNT_shadow;
V_D_CNT_shadow_intermed_2 <= V_D_CNT_shadow_intermed_1;
V_D_CNT_shadow_intermed_3 <= V_D_CNT_shadow_intermed_2;
R_D_CNT_intermed_1 <= R.D.CNT;
R_D_CNT_intermed_2 <= R_D_CNT_intermed_1;
RIN_A_CTRL_CNT_intermed_1 <= RIN.A.CTRL.CNT;
RIN_A_CTRL_CNT_intermed_2 <= RIN_A_CTRL_CNT_intermed_1;
RIN_E_CTRL_CNT_intermed_1 <= RIN.E.CTRL.CNT;
V_A_CTRL_TRAP_shadow_intermed_1 <= V_A_CTRL_TRAP_shadow;
V_A_CTRL_TRAP_shadow_intermed_2 <= V_A_CTRL_TRAP_shadow_intermed_1;
ICO_MEXC_intermed_1 <= ICO.MEXC;
ICO_MEXC_intermed_2 <= ICO_MEXC_intermed_1;
ICO_MEXC_intermed_3 <= ICO_MEXC_intermed_2;
RIN_A_CTRL_TRAP_intermed_1 <= RIN.A.CTRL.TRAP;
RIN_A_CTRL_TRAP_intermed_2 <= RIN_A_CTRL_TRAP_intermed_1;
RIN_E_CTRL_TRAP_intermed_1 <= RIN.E.CTRL.TRAP;
R_D_MEXC_intermed_1 <= R.D.MEXC;
R_D_MEXC_intermed_2 <= R_D_MEXC_intermed_1;
V_D_MEXC_shadow_intermed_1 <= V_D_MEXC_shadow;
V_D_MEXC_shadow_intermed_2 <= V_D_MEXC_shadow_intermed_1;
V_D_MEXC_shadow_intermed_3 <= V_D_MEXC_shadow_intermed_2;
R_A_CTRL_TRAP_intermed_1 <= R.A.CTRL.TRAP;
RIN_D_MEXC_intermed_1 <= RIN.D.MEXC;
RIN_D_MEXC_intermed_2 <= RIN_D_MEXC_intermed_1;
RIN_D_MEXC_intermed_3 <= RIN_D_MEXC_intermed_2;
R_A_CTRL_PV_intermed_1 <= R.A.CTRL.PV;
RIN_E_CTRL_PV_intermed_1 <= RIN.E.CTRL.PV;
V_A_CTRL_PV_shadow_intermed_1 <= V_A_CTRL_PV_shadow;
V_A_CTRL_PV_shadow_intermed_2 <= V_A_CTRL_PV_shadow_intermed_1;
RIN_A_CTRL_PV_intermed_1 <= RIN.A.CTRL.PV;
RIN_A_CTRL_PV_intermed_2 <= RIN_A_CTRL_PV_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC ( 31 DOWNTO 2 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC ( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC ( 31 DOWNTO 2 );
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC ( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_E_CTRL_INST_intermed_1 <= R.E.CTRL.INST;
DE_INST_shadow_intermed_1 <= DE_INST_shadow;
DE_INST_shadow_intermed_2 <= DE_INST_shadow_intermed_1;
DE_INST_shadow_intermed_3 <= DE_INST_shadow_intermed_2;
V_A_CTRL_INST_shadow_intermed_1 <= V_A_CTRL_INST_shadow;
V_A_CTRL_INST_shadow_intermed_2 <= V_A_CTRL_INST_shadow_intermed_1;
V_A_CTRL_INST_shadow_intermed_3 <= V_A_CTRL_INST_shadow_intermed_2;
V_E_CTRL_INST_shadow_intermed_1 <= V_E_CTRL_INST_shadow;
V_E_CTRL_INST_shadow_intermed_2 <= V_E_CTRL_INST_shadow_intermed_1;
RIN_A_CTRL_INST_intermed_1 <= RIN.A.CTRL.INST;
RIN_A_CTRL_INST_intermed_2 <= RIN_A_CTRL_INST_intermed_1;
RIN_A_CTRL_INST_intermed_3 <= RIN_A_CTRL_INST_intermed_2;
RIN_M_CTRL_INST_intermed_1 <= RIN.M.CTRL.INST;
RIN_E_CTRL_INST_intermed_1 <= RIN.E.CTRL.INST;
RIN_E_CTRL_INST_intermed_2 <= RIN_E_CTRL_INST_intermed_1;
R_A_CTRL_INST_intermed_1 <= R.A.CTRL.INST;
R_A_CTRL_INST_intermed_2 <= R_A_CTRL_INST_intermed_1;
V_E_CTRL_CNT_shadow_intermed_1 <= V_E_CTRL_CNT_shadow;
V_E_CTRL_CNT_shadow_intermed_2 <= V_E_CTRL_CNT_shadow_intermed_1;
RIN_D_CNT_intermed_1 <= RIN.D.CNT;
RIN_D_CNT_intermed_2 <= RIN_D_CNT_intermed_1;
RIN_D_CNT_intermed_3 <= RIN_D_CNT_intermed_2;
RIN_D_CNT_intermed_4 <= RIN_D_CNT_intermed_3;
V_A_CTRL_CNT_shadow_intermed_1 <= V_A_CTRL_CNT_shadow;
V_A_CTRL_CNT_shadow_intermed_2 <= V_A_CTRL_CNT_shadow_intermed_1;
V_A_CTRL_CNT_shadow_intermed_3 <= V_A_CTRL_CNT_shadow_intermed_2;
R_A_CTRL_CNT_intermed_1 <= R.A.CTRL.CNT;
R_A_CTRL_CNT_intermed_2 <= R_A_CTRL_CNT_intermed_1;
V_D_CNT_shadow_intermed_1 <= V_D_CNT_shadow;
V_D_CNT_shadow_intermed_2 <= V_D_CNT_shadow_intermed_1;
V_D_CNT_shadow_intermed_3 <= V_D_CNT_shadow_intermed_2;
V_D_CNT_shadow_intermed_4 <= V_D_CNT_shadow_intermed_3;
R_D_CNT_intermed_1 <= R.D.CNT;
R_D_CNT_intermed_2 <= R_D_CNT_intermed_1;
R_D_CNT_intermed_3 <= R_D_CNT_intermed_2;
R_E_CTRL_CNT_intermed_1 <= R.E.CTRL.CNT;
RIN_A_CTRL_CNT_intermed_1 <= RIN.A.CTRL.CNT;
RIN_A_CTRL_CNT_intermed_2 <= RIN_A_CTRL_CNT_intermed_1;
RIN_A_CTRL_CNT_intermed_3 <= RIN_A_CTRL_CNT_intermed_2;
RIN_M_CTRL_CNT_intermed_1 <= RIN.M.CTRL.CNT;
RIN_E_CTRL_CNT_intermed_1 <= RIN.E.CTRL.CNT;
RIN_E_CTRL_CNT_intermed_2 <= RIN_E_CTRL_CNT_intermed_1;
V_A_CTRL_TRAP_shadow_intermed_1 <= V_A_CTRL_TRAP_shadow;
V_A_CTRL_TRAP_shadow_intermed_2 <= V_A_CTRL_TRAP_shadow_intermed_1;
V_A_CTRL_TRAP_shadow_intermed_3 <= V_A_CTRL_TRAP_shadow_intermed_2;
ICO_MEXC_intermed_1 <= ICO.MEXC;
ICO_MEXC_intermed_2 <= ICO_MEXC_intermed_1;
ICO_MEXC_intermed_3 <= ICO_MEXC_intermed_2;
ICO_MEXC_intermed_4 <= ICO_MEXC_intermed_3;
R_E_CTRL_TRAP_intermed_1 <= R.E.CTRL.TRAP;
RIN_A_CTRL_TRAP_intermed_1 <= RIN.A.CTRL.TRAP;
RIN_A_CTRL_TRAP_intermed_2 <= RIN_A_CTRL_TRAP_intermed_1;
RIN_A_CTRL_TRAP_intermed_3 <= RIN_A_CTRL_TRAP_intermed_2;
V_E_CTRL_TRAP_shadow_intermed_1 <= V_E_CTRL_TRAP_shadow;
V_E_CTRL_TRAP_shadow_intermed_2 <= V_E_CTRL_TRAP_shadow_intermed_1;
RIN_E_CTRL_TRAP_intermed_1 <= RIN.E.CTRL.TRAP;
RIN_E_CTRL_TRAP_intermed_2 <= RIN_E_CTRL_TRAP_intermed_1;
R_D_MEXC_intermed_1 <= R.D.MEXC;
R_D_MEXC_intermed_2 <= R_D_MEXC_intermed_1;
R_D_MEXC_intermed_3 <= R_D_MEXC_intermed_2;
V_D_MEXC_shadow_intermed_1 <= V_D_MEXC_shadow;
V_D_MEXC_shadow_intermed_2 <= V_D_MEXC_shadow_intermed_1;
V_D_MEXC_shadow_intermed_3 <= V_D_MEXC_shadow_intermed_2;
V_D_MEXC_shadow_intermed_4 <= V_D_MEXC_shadow_intermed_3;
R_A_CTRL_TRAP_intermed_1 <= R.A.CTRL.TRAP;
R_A_CTRL_TRAP_intermed_2 <= R_A_CTRL_TRAP_intermed_1;
RIN_M_CTRL_TRAP_intermed_1 <= RIN.M.CTRL.TRAP;
RIN_D_MEXC_intermed_1 <= RIN.D.MEXC;
RIN_D_MEXC_intermed_2 <= RIN_D_MEXC_intermed_1;
RIN_D_MEXC_intermed_3 <= RIN_D_MEXC_intermed_2;
RIN_D_MEXC_intermed_4 <= RIN_D_MEXC_intermed_3;
V_E_CTRL_PV_shadow_intermed_1 <= V_E_CTRL_PV_shadow;
V_E_CTRL_PV_shadow_intermed_2 <= V_E_CTRL_PV_shadow_intermed_1;
R_E_CTRL_PV_intermed_1 <= R.E.CTRL.PV;
R_A_CTRL_PV_intermed_1 <= R.A.CTRL.PV;
R_A_CTRL_PV_intermed_2 <= R_A_CTRL_PV_intermed_1;
RIN_E_CTRL_PV_intermed_1 <= RIN.E.CTRL.PV;
RIN_E_CTRL_PV_intermed_2 <= RIN_E_CTRL_PV_intermed_1;
RIN_M_CTRL_PV_intermed_1 <= RIN.M.CTRL.PV;
V_A_CTRL_PV_shadow_intermed_1 <= V_A_CTRL_PV_shadow;
V_A_CTRL_PV_shadow_intermed_2 <= V_A_CTRL_PV_shadow_intermed_1;
V_A_CTRL_PV_shadow_intermed_3 <= V_A_CTRL_PV_shadow_intermed_2;
RIN_A_CTRL_PV_intermed_1 <= RIN.A.CTRL.PV;
RIN_A_CTRL_PV_intermed_2 <= RIN_A_CTRL_PV_intermed_1;
RIN_A_CTRL_PV_intermed_3 <= RIN_A_CTRL_PV_intermed_2;
R_E_CTRL_INST_intermed_1 <= R.E.CTRL.INST;
R_E_CTRL_INST_intermed_2 <= R_E_CTRL_INST_intermed_1;
R_M_CTRL_INST_intermed_1 <= R.M.CTRL.INST;
DE_INST_shadow_intermed_1 <= DE_INST_shadow;
DE_INST_shadow_intermed_2 <= DE_INST_shadow_intermed_1;
DE_INST_shadow_intermed_3 <= DE_INST_shadow_intermed_2;
DE_INST_shadow_intermed_4 <= DE_INST_shadow_intermed_3;
V_A_CTRL_INST_shadow_intermed_1 <= V_A_CTRL_INST_shadow;
V_A_CTRL_INST_shadow_intermed_2 <= V_A_CTRL_INST_shadow_intermed_1;
V_A_CTRL_INST_shadow_intermed_3 <= V_A_CTRL_INST_shadow_intermed_2;
V_A_CTRL_INST_shadow_intermed_4 <= V_A_CTRL_INST_shadow_intermed_3;
V_E_CTRL_INST_shadow_intermed_1 <= V_E_CTRL_INST_shadow;
V_E_CTRL_INST_shadow_intermed_2 <= V_E_CTRL_INST_shadow_intermed_1;
V_E_CTRL_INST_shadow_intermed_3 <= V_E_CTRL_INST_shadow_intermed_2;
RIN_X_CTRL_INST_intermed_1 <= RIN.X.CTRL.INST;
RIN_A_CTRL_INST_intermed_1 <= RIN.A.CTRL.INST;
RIN_A_CTRL_INST_intermed_2 <= RIN_A_CTRL_INST_intermed_1;
RIN_A_CTRL_INST_intermed_3 <= RIN_A_CTRL_INST_intermed_2;
RIN_A_CTRL_INST_intermed_4 <= RIN_A_CTRL_INST_intermed_3;
RIN_M_CTRL_INST_intermed_1 <= RIN.M.CTRL.INST;
RIN_M_CTRL_INST_intermed_2 <= RIN_M_CTRL_INST_intermed_1;
RIN_E_CTRL_INST_intermed_1 <= RIN.E.CTRL.INST;
RIN_E_CTRL_INST_intermed_2 <= RIN_E_CTRL_INST_intermed_1;
RIN_E_CTRL_INST_intermed_3 <= RIN_E_CTRL_INST_intermed_2;
V_M_CTRL_INST_shadow_intermed_1 <= V_M_CTRL_INST_shadow;
V_M_CTRL_INST_shadow_intermed_2 <= V_M_CTRL_INST_shadow_intermed_1;
R_A_CTRL_INST_intermed_1 <= R.A.CTRL.INST;
R_A_CTRL_INST_intermed_2 <= R_A_CTRL_INST_intermed_1;
R_A_CTRL_INST_intermed_3 <= R_A_CTRL_INST_intermed_2;
V_E_CTRL_CNT_shadow_intermed_1 <= V_E_CTRL_CNT_shadow;
V_E_CTRL_CNT_shadow_intermed_2 <= V_E_CTRL_CNT_shadow_intermed_1;
V_E_CTRL_CNT_shadow_intermed_3 <= V_E_CTRL_CNT_shadow_intermed_2;
RIN_D_CNT_intermed_1 <= RIN.D.CNT;
RIN_D_CNT_intermed_2 <= RIN_D_CNT_intermed_1;
RIN_D_CNT_intermed_3 <= RIN_D_CNT_intermed_2;
RIN_D_CNT_intermed_4 <= RIN_D_CNT_intermed_3;
RIN_D_CNT_intermed_5 <= RIN_D_CNT_intermed_4;
R_M_CTRL_CNT_intermed_1 <= R.M.CTRL.CNT;
V_A_CTRL_CNT_shadow_intermed_1 <= V_A_CTRL_CNT_shadow;
V_A_CTRL_CNT_shadow_intermed_2 <= V_A_CTRL_CNT_shadow_intermed_1;
V_A_CTRL_CNT_shadow_intermed_3 <= V_A_CTRL_CNT_shadow_intermed_2;
V_A_CTRL_CNT_shadow_intermed_4 <= V_A_CTRL_CNT_shadow_intermed_3;
R_A_CTRL_CNT_intermed_1 <= R.A.CTRL.CNT;
R_A_CTRL_CNT_intermed_2 <= R_A_CTRL_CNT_intermed_1;
R_A_CTRL_CNT_intermed_3 <= R_A_CTRL_CNT_intermed_2;
V_D_CNT_shadow_intermed_1 <= V_D_CNT_shadow;
V_D_CNT_shadow_intermed_2 <= V_D_CNT_shadow_intermed_1;
V_D_CNT_shadow_intermed_3 <= V_D_CNT_shadow_intermed_2;
V_D_CNT_shadow_intermed_4 <= V_D_CNT_shadow_intermed_3;
V_D_CNT_shadow_intermed_5 <= V_D_CNT_shadow_intermed_4;
R_D_CNT_intermed_1 <= R.D.CNT;
R_D_CNT_intermed_2 <= R_D_CNT_intermed_1;
R_D_CNT_intermed_3 <= R_D_CNT_intermed_2;
R_D_CNT_intermed_4 <= R_D_CNT_intermed_3;
R_E_CTRL_CNT_intermed_1 <= R.E.CTRL.CNT;
R_E_CTRL_CNT_intermed_2 <= R_E_CTRL_CNT_intermed_1;
RIN_X_CTRL_CNT_intermed_1 <= RIN.X.CTRL.CNT;
RIN_A_CTRL_CNT_intermed_1 <= RIN.A.CTRL.CNT;
RIN_A_CTRL_CNT_intermed_2 <= RIN_A_CTRL_CNT_intermed_1;
RIN_A_CTRL_CNT_intermed_3 <= RIN_A_CTRL_CNT_intermed_2;
RIN_A_CTRL_CNT_intermed_4 <= RIN_A_CTRL_CNT_intermed_3;
RIN_M_CTRL_CNT_intermed_1 <= RIN.M.CTRL.CNT;
RIN_M_CTRL_CNT_intermed_2 <= RIN_M_CTRL_CNT_intermed_1;
RIN_E_CTRL_CNT_intermed_1 <= RIN.E.CTRL.CNT;
RIN_E_CTRL_CNT_intermed_2 <= RIN_E_CTRL_CNT_intermed_1;
RIN_E_CTRL_CNT_intermed_3 <= RIN_E_CTRL_CNT_intermed_2;
V_M_CTRL_CNT_shadow_intermed_1 <= V_M_CTRL_CNT_shadow;
V_M_CTRL_CNT_shadow_intermed_2 <= V_M_CTRL_CNT_shadow_intermed_1;
V_E_CTRL_PV_shadow_intermed_1 <= V_E_CTRL_PV_shadow;
V_E_CTRL_PV_shadow_intermed_2 <= V_E_CTRL_PV_shadow_intermed_1;
V_E_CTRL_PV_shadow_intermed_3 <= V_E_CTRL_PV_shadow_intermed_2;
R_M_CTRL_PV_intermed_1 <= R.M.CTRL.PV;
R_E_CTRL_PV_intermed_1 <= R.E.CTRL.PV;
R_E_CTRL_PV_intermed_2 <= R_E_CTRL_PV_intermed_1;
R_A_CTRL_PV_intermed_1 <= R.A.CTRL.PV;
R_A_CTRL_PV_intermed_2 <= R_A_CTRL_PV_intermed_1;
R_A_CTRL_PV_intermed_3 <= R_A_CTRL_PV_intermed_2;
RIN_E_CTRL_PV_intermed_1 <= RIN.E.CTRL.PV;
RIN_E_CTRL_PV_intermed_2 <= RIN_E_CTRL_PV_intermed_1;
RIN_E_CTRL_PV_intermed_3 <= RIN_E_CTRL_PV_intermed_2;
RIN_X_CTRL_PV_intermed_1 <= RIN.X.CTRL.PV;
RIN_M_CTRL_PV_intermed_1 <= RIN.M.CTRL.PV;
RIN_M_CTRL_PV_intermed_2 <= RIN_M_CTRL_PV_intermed_1;
V_A_CTRL_PV_shadow_intermed_1 <= V_A_CTRL_PV_shadow;
V_A_CTRL_PV_shadow_intermed_2 <= V_A_CTRL_PV_shadow_intermed_1;
V_A_CTRL_PV_shadow_intermed_3 <= V_A_CTRL_PV_shadow_intermed_2;
V_A_CTRL_PV_shadow_intermed_4 <= V_A_CTRL_PV_shadow_intermed_3;
V_M_CTRL_PV_shadow_intermed_1 <= V_M_CTRL_PV_shadow;
V_M_CTRL_PV_shadow_intermed_2 <= V_M_CTRL_PV_shadow_intermed_1;
RIN_A_CTRL_PV_intermed_1 <= RIN.A.CTRL.PV;
RIN_A_CTRL_PV_intermed_2 <= RIN_A_CTRL_PV_intermed_1;
RIN_A_CTRL_PV_intermed_3 <= RIN_A_CTRL_PV_intermed_2;
RIN_A_CTRL_PV_intermed_4 <= RIN_A_CTRL_PV_intermed_3;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST( 19 );
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
DE_INST19_shadow_intermed_2 <= DE_INST19_shadow_intermed_1;
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST( 20 );
RIN_A_CTRL_INST20_intermed_2 <= RIN_A_CTRL_INST20_intermed_1;
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
V_A_CTRL_INST20_shadow_intermed_2 <= V_A_CTRL_INST20_shadow_intermed_1;
RIN_E_CTRL_INST20_intermed_1 <= RIN.E.CTRL.INST( 20 );
DE_INST20_shadow_intermed_1 <= DE_INST20_shadow;
DE_INST20_shadow_intermed_2 <= DE_INST20_shadow_intermed_1;
R_A_CTRL_INST20_intermed_1 <= R.A.CTRL.INST( 20 );
R_A_CTRL_INST24_intermed_1 <= R.A.CTRL.INST( 24 );
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST( 24 );
RIN_A_CTRL_INST24_intermed_2 <= RIN_A_CTRL_INST24_intermed_1;
RIN_E_CTRL_INST24_intermed_1 <= RIN.E.CTRL.INST( 24 );
V_A_CTRL_INST24_shadow_intermed_1 <= V_A_CTRL_INST24_shadow;
V_A_CTRL_INST24_shadow_intermed_2 <= V_A_CTRL_INST24_shadow_intermed_1;
DE_INST24_shadow_intermed_1 <= DE_INST24_shadow;
DE_INST24_shadow_intermed_2 <= DE_INST24_shadow_intermed_1;
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
V_X_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO4_shadow;
V_X_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO4_shadow_intermed_2;
IR_ADDR31DOWNTO4_intermed_1 <= IR.ADDR( 31 DOWNTO 4 );
VIR_ADDR31DOWNTO4_shadow_intermed_1 <= VIR_ADDR31DOWNTO4_shadow;
VIR_ADDR31DOWNTO4_shadow_intermed_2 <= VIR_ADDR31DOWNTO4_shadow_intermed_1;
RIN_F_PC31DOWNTO4_intermed_1 <= RIN.F.PC( 31 DOWNTO 4 );
RIN_A_CTRL_PC31DOWNTO4_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 4 );
RIN_A_CTRL_PC31DOWNTO4_intermed_2 <= RIN_A_CTRL_PC31DOWNTO4_intermed_1;
RIN_A_CTRL_PC31DOWNTO4_intermed_3 <= RIN_A_CTRL_PC31DOWNTO4_intermed_2;
RIN_A_CTRL_PC31DOWNTO4_intermed_4 <= RIN_A_CTRL_PC31DOWNTO4_intermed_3;
RIN_A_CTRL_PC31DOWNTO4_intermed_5 <= RIN_A_CTRL_PC31DOWNTO4_intermed_4;
RIN_A_CTRL_PC31DOWNTO4_intermed_6 <= RIN_A_CTRL_PC31DOWNTO4_intermed_5;
R_A_CTRL_PC31DOWNTO4_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 4 );
R_A_CTRL_PC31DOWNTO4_intermed_2 <= R_A_CTRL_PC31DOWNTO4_intermed_1;
R_A_CTRL_PC31DOWNTO4_intermed_3 <= R_A_CTRL_PC31DOWNTO4_intermed_2;
R_A_CTRL_PC31DOWNTO4_intermed_4 <= R_A_CTRL_PC31DOWNTO4_intermed_3;
R_A_CTRL_PC31DOWNTO4_intermed_5 <= R_A_CTRL_PC31DOWNTO4_intermed_4;
R_D_PC31DOWNTO4_intermed_1 <= R.D.PC( 31 DOWNTO 4 );
R_D_PC31DOWNTO4_intermed_2 <= R_D_PC31DOWNTO4_intermed_1;
R_D_PC31DOWNTO4_intermed_3 <= R_D_PC31DOWNTO4_intermed_2;
R_D_PC31DOWNTO4_intermed_4 <= R_D_PC31DOWNTO4_intermed_3;
R_D_PC31DOWNTO4_intermed_5 <= R_D_PC31DOWNTO4_intermed_4;
R_D_PC31DOWNTO4_intermed_6 <= R_D_PC31DOWNTO4_intermed_5;
RIN_X_CTRL_PC31DOWNTO4_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 4 );
RIN_X_CTRL_PC31DOWNTO4_intermed_2 <= RIN_X_CTRL_PC31DOWNTO4_intermed_1;
RIN_X_CTRL_PC31DOWNTO4_intermed_3 <= RIN_X_CTRL_PC31DOWNTO4_intermed_2;
EX_ADD_RES32DOWNTO332DOWNTO5_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO5_shadow;
V_D_PC31DOWNTO4_shadow_intermed_1 <= V_D_PC31DOWNTO4_shadow;
V_D_PC31DOWNTO4_shadow_intermed_2 <= V_D_PC31DOWNTO4_shadow_intermed_1;
V_D_PC31DOWNTO4_shadow_intermed_3 <= V_D_PC31DOWNTO4_shadow_intermed_2;
V_D_PC31DOWNTO4_shadow_intermed_4 <= V_D_PC31DOWNTO4_shadow_intermed_3;
V_D_PC31DOWNTO4_shadow_intermed_5 <= V_D_PC31DOWNTO4_shadow_intermed_4;
V_D_PC31DOWNTO4_shadow_intermed_6 <= V_D_PC31DOWNTO4_shadow_intermed_5;
V_D_PC31DOWNTO4_shadow_intermed_7 <= V_D_PC31DOWNTO4_shadow_intermed_6;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO4_shadow;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_4;
RIN_M_CTRL_PC31DOWNTO4_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 4 );
RIN_M_CTRL_PC31DOWNTO4_intermed_2 <= RIN_M_CTRL_PC31DOWNTO4_intermed_1;
RIN_M_CTRL_PC31DOWNTO4_intermed_3 <= RIN_M_CTRL_PC31DOWNTO4_intermed_2;
RIN_M_CTRL_PC31DOWNTO4_intermed_4 <= RIN_M_CTRL_PC31DOWNTO4_intermed_3;
R_X_CTRL_PC31DOWNTO4_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 4 );
R_X_CTRL_PC31DOWNTO4_intermed_2 <= R_X_CTRL_PC31DOWNTO4_intermed_1;
IRIN_ADDR31DOWNTO4_intermed_1 <= IRIN.ADDR( 31 DOWNTO 4 );
IRIN_ADDR31DOWNTO4_intermed_2 <= IRIN_ADDR31DOWNTO4_intermed_1;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO4_shadow;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_3;
R_M_CTRL_PC31DOWNTO4_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 4 );
R_M_CTRL_PC31DOWNTO4_intermed_2 <= R_M_CTRL_PC31DOWNTO4_intermed_1;
R_M_CTRL_PC31DOWNTO4_intermed_3 <= R_M_CTRL_PC31DOWNTO4_intermed_2;
XC_TRAP_ADDRESS31DOWNTO4_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO4_shadow;
RIN_D_PC31DOWNTO4_intermed_1 <= RIN.D.PC( 31 DOWNTO 4 );
RIN_D_PC31DOWNTO4_intermed_2 <= RIN_D_PC31DOWNTO4_intermed_1;
RIN_D_PC31DOWNTO4_intermed_3 <= RIN_D_PC31DOWNTO4_intermed_2;
RIN_D_PC31DOWNTO4_intermed_4 <= RIN_D_PC31DOWNTO4_intermed_3;
RIN_D_PC31DOWNTO4_intermed_5 <= RIN_D_PC31DOWNTO4_intermed_4;
RIN_D_PC31DOWNTO4_intermed_6 <= RIN_D_PC31DOWNTO4_intermed_5;
RIN_D_PC31DOWNTO4_intermed_7 <= RIN_D_PC31DOWNTO4_intermed_6;
RIN_E_CTRL_PC31DOWNTO4_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 4 );
RIN_E_CTRL_PC31DOWNTO4_intermed_2 <= RIN_E_CTRL_PC31DOWNTO4_intermed_1;
RIN_E_CTRL_PC31DOWNTO4_intermed_3 <= RIN_E_CTRL_PC31DOWNTO4_intermed_2;
RIN_E_CTRL_PC31DOWNTO4_intermed_4 <= RIN_E_CTRL_PC31DOWNTO4_intermed_3;
RIN_E_CTRL_PC31DOWNTO4_intermed_5 <= RIN_E_CTRL_PC31DOWNTO4_intermed_4;
EX_JUMP_ADDRESS31DOWNTO4_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO4_shadow;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO4_shadow;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_5;
R_E_CTRL_PC31DOWNTO4_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 4 );
R_E_CTRL_PC31DOWNTO4_intermed_2 <= R_E_CTRL_PC31DOWNTO4_intermed_1;
R_E_CTRL_PC31DOWNTO4_intermed_3 <= R_E_CTRL_PC31DOWNTO4_intermed_2;
R_E_CTRL_PC31DOWNTO4_intermed_4 <= R_E_CTRL_PC31DOWNTO4_intermed_3;
V_X_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO4_shadow;
V_X_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO4_shadow_intermed_1;
RIN_A_CTRL_PC31DOWNTO4_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 4 );
RIN_A_CTRL_PC31DOWNTO4_intermed_2 <= RIN_A_CTRL_PC31DOWNTO4_intermed_1;
RIN_A_CTRL_PC31DOWNTO4_intermed_3 <= RIN_A_CTRL_PC31DOWNTO4_intermed_2;
RIN_A_CTRL_PC31DOWNTO4_intermed_4 <= RIN_A_CTRL_PC31DOWNTO4_intermed_3;
RIN_A_CTRL_PC31DOWNTO4_intermed_5 <= RIN_A_CTRL_PC31DOWNTO4_intermed_4;
R_A_CTRL_PC31DOWNTO4_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 4 );
R_A_CTRL_PC31DOWNTO4_intermed_2 <= R_A_CTRL_PC31DOWNTO4_intermed_1;
R_A_CTRL_PC31DOWNTO4_intermed_3 <= R_A_CTRL_PC31DOWNTO4_intermed_2;
R_A_CTRL_PC31DOWNTO4_intermed_4 <= R_A_CTRL_PC31DOWNTO4_intermed_3;
R_D_PC31DOWNTO4_intermed_1 <= R.D.PC( 31 DOWNTO 4 );
R_D_PC31DOWNTO4_intermed_2 <= R_D_PC31DOWNTO4_intermed_1;
R_D_PC31DOWNTO4_intermed_3 <= R_D_PC31DOWNTO4_intermed_2;
R_D_PC31DOWNTO4_intermed_4 <= R_D_PC31DOWNTO4_intermed_3;
R_D_PC31DOWNTO4_intermed_5 <= R_D_PC31DOWNTO4_intermed_4;
RIN_X_CTRL_PC31DOWNTO4_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 4 );
RIN_X_CTRL_PC31DOWNTO4_intermed_2 <= RIN_X_CTRL_PC31DOWNTO4_intermed_1;
V_D_PC31DOWNTO4_shadow_intermed_1 <= V_D_PC31DOWNTO4_shadow;
V_D_PC31DOWNTO4_shadow_intermed_2 <= V_D_PC31DOWNTO4_shadow_intermed_1;
V_D_PC31DOWNTO4_shadow_intermed_3 <= V_D_PC31DOWNTO4_shadow_intermed_2;
V_D_PC31DOWNTO4_shadow_intermed_4 <= V_D_PC31DOWNTO4_shadow_intermed_3;
V_D_PC31DOWNTO4_shadow_intermed_5 <= V_D_PC31DOWNTO4_shadow_intermed_4;
V_D_PC31DOWNTO4_shadow_intermed_6 <= V_D_PC31DOWNTO4_shadow_intermed_5;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO4_shadow;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_3;
RIN_M_CTRL_PC31DOWNTO4_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 4 );
RIN_M_CTRL_PC31DOWNTO4_intermed_2 <= RIN_M_CTRL_PC31DOWNTO4_intermed_1;
RIN_M_CTRL_PC31DOWNTO4_intermed_3 <= RIN_M_CTRL_PC31DOWNTO4_intermed_2;
R_X_CTRL_PC31DOWNTO4_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 4 );
IRIN_ADDR31DOWNTO4_intermed_1 <= IRIN.ADDR( 31 DOWNTO 4 );
V_M_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO4_shadow;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_2;
R_M_CTRL_PC31DOWNTO4_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 4 );
R_M_CTRL_PC31DOWNTO4_intermed_2 <= R_M_CTRL_PC31DOWNTO4_intermed_1;
RIN_D_PC31DOWNTO4_intermed_1 <= RIN.D.PC( 31 DOWNTO 4 );
RIN_D_PC31DOWNTO4_intermed_2 <= RIN_D_PC31DOWNTO4_intermed_1;
RIN_D_PC31DOWNTO4_intermed_3 <= RIN_D_PC31DOWNTO4_intermed_2;
RIN_D_PC31DOWNTO4_intermed_4 <= RIN_D_PC31DOWNTO4_intermed_3;
RIN_D_PC31DOWNTO4_intermed_5 <= RIN_D_PC31DOWNTO4_intermed_4;
RIN_D_PC31DOWNTO4_intermed_6 <= RIN_D_PC31DOWNTO4_intermed_5;
RIN_E_CTRL_PC31DOWNTO4_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 4 );
RIN_E_CTRL_PC31DOWNTO4_intermed_2 <= RIN_E_CTRL_PC31DOWNTO4_intermed_1;
RIN_E_CTRL_PC31DOWNTO4_intermed_3 <= RIN_E_CTRL_PC31DOWNTO4_intermed_2;
RIN_E_CTRL_PC31DOWNTO4_intermed_4 <= RIN_E_CTRL_PC31DOWNTO4_intermed_3;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO4_shadow;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_4;
R_E_CTRL_PC31DOWNTO4_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 4 );
R_E_CTRL_PC31DOWNTO4_intermed_2 <= R_E_CTRL_PC31DOWNTO4_intermed_1;
R_E_CTRL_PC31DOWNTO4_intermed_3 <= R_E_CTRL_PC31DOWNTO4_intermed_2;
R_D_PC3DOWNTO2_intermed_1 <= R.D.PC( 3 DOWNTO 2 );
R_D_PC3DOWNTO2_intermed_2 <= R_D_PC3DOWNTO2_intermed_1;
R_D_PC3DOWNTO2_intermed_3 <= R_D_PC3DOWNTO2_intermed_2;
R_D_PC3DOWNTO2_intermed_4 <= R_D_PC3DOWNTO2_intermed_3;
R_D_PC3DOWNTO2_intermed_5 <= R_D_PC3DOWNTO2_intermed_4;
R_D_PC3DOWNTO2_intermed_6 <= R_D_PC3DOWNTO2_intermed_5;
V_D_PC3DOWNTO2_shadow_intermed_1 <= V_D_PC3DOWNTO2_shadow;
V_D_PC3DOWNTO2_shadow_intermed_2 <= V_D_PC3DOWNTO2_shadow_intermed_1;
V_D_PC3DOWNTO2_shadow_intermed_3 <= V_D_PC3DOWNTO2_shadow_intermed_2;
V_D_PC3DOWNTO2_shadow_intermed_4 <= V_D_PC3DOWNTO2_shadow_intermed_3;
V_D_PC3DOWNTO2_shadow_intermed_5 <= V_D_PC3DOWNTO2_shadow_intermed_4;
V_D_PC3DOWNTO2_shadow_intermed_6 <= V_D_PC3DOWNTO2_shadow_intermed_5;
V_D_PC3DOWNTO2_shadow_intermed_7 <= V_D_PC3DOWNTO2_shadow_intermed_6;
VIR_ADDR3DOWNTO2_shadow_intermed_1 <= VIR_ADDR3DOWNTO2_shadow;
VIR_ADDR3DOWNTO2_shadow_intermed_2 <= VIR_ADDR3DOWNTO2_shadow_intermed_1;
RIN_D_PC3DOWNTO2_intermed_1 <= RIN.D.PC( 3 DOWNTO 2 );
RIN_D_PC3DOWNTO2_intermed_2 <= RIN_D_PC3DOWNTO2_intermed_1;
RIN_D_PC3DOWNTO2_intermed_3 <= RIN_D_PC3DOWNTO2_intermed_2;
RIN_D_PC3DOWNTO2_intermed_4 <= RIN_D_PC3DOWNTO2_intermed_3;
RIN_D_PC3DOWNTO2_intermed_5 <= RIN_D_PC3DOWNTO2_intermed_4;
RIN_D_PC3DOWNTO2_intermed_6 <= RIN_D_PC3DOWNTO2_intermed_5;
RIN_D_PC3DOWNTO2_intermed_7 <= RIN_D_PC3DOWNTO2_intermed_6;
R_M_CTRL_PC3DOWNTO2_intermed_1 <= R.M.CTRL.PC( 3 DOWNTO 2 );
R_M_CTRL_PC3DOWNTO2_intermed_2 <= R_M_CTRL_PC3DOWNTO2_intermed_1;
R_M_CTRL_PC3DOWNTO2_intermed_3 <= R_M_CTRL_PC3DOWNTO2_intermed_2;
R_E_CTRL_PC3DOWNTO2_intermed_1 <= R.E.CTRL.PC( 3 DOWNTO 2 );
R_E_CTRL_PC3DOWNTO2_intermed_2 <= R_E_CTRL_PC3DOWNTO2_intermed_1;
R_E_CTRL_PC3DOWNTO2_intermed_3 <= R_E_CTRL_PC3DOWNTO2_intermed_2;
R_E_CTRL_PC3DOWNTO2_intermed_4 <= R_E_CTRL_PC3DOWNTO2_intermed_3;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC3DOWNTO2_shadow;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_3;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_4;
RIN_X_CTRL_PC3DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 3 DOWNTO 2 );
RIN_X_CTRL_PC3DOWNTO2_intermed_2 <= RIN_X_CTRL_PC3DOWNTO2_intermed_1;
RIN_X_CTRL_PC3DOWNTO2_intermed_3 <= RIN_X_CTRL_PC3DOWNTO2_intermed_2;
R_A_CTRL_PC3DOWNTO2_intermed_1 <= R.A.CTRL.PC( 3 DOWNTO 2 );
R_A_CTRL_PC3DOWNTO2_intermed_2 <= R_A_CTRL_PC3DOWNTO2_intermed_1;
R_A_CTRL_PC3DOWNTO2_intermed_3 <= R_A_CTRL_PC3DOWNTO2_intermed_2;
R_A_CTRL_PC3DOWNTO2_intermed_4 <= R_A_CTRL_PC3DOWNTO2_intermed_3;
R_A_CTRL_PC3DOWNTO2_intermed_5 <= R_A_CTRL_PC3DOWNTO2_intermed_4;
V_X_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC3DOWNTO2_shadow;
V_X_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC3DOWNTO2_shadow_intermed_2;
RIN_M_CTRL_PC3DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 3 DOWNTO 2 );
RIN_M_CTRL_PC3DOWNTO2_intermed_2 <= RIN_M_CTRL_PC3DOWNTO2_intermed_1;
RIN_M_CTRL_PC3DOWNTO2_intermed_3 <= RIN_M_CTRL_PC3DOWNTO2_intermed_2;
RIN_M_CTRL_PC3DOWNTO2_intermed_4 <= RIN_M_CTRL_PC3DOWNTO2_intermed_3;
IRIN_ADDR3DOWNTO2_intermed_1 <= IRIN.ADDR( 3 DOWNTO 2 );
IRIN_ADDR3DOWNTO2_intermed_2 <= IRIN_ADDR3DOWNTO2_intermed_1;
EX_JUMP_ADDRESS3DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS3DOWNTO2_shadow;
EX_ADD_RES32DOWNTO34DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO34DOWNTO3_shadow;
RIN_A_CTRL_PC3DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 3 DOWNTO 2 );
RIN_A_CTRL_PC3DOWNTO2_intermed_2 <= RIN_A_CTRL_PC3DOWNTO2_intermed_1;
RIN_A_CTRL_PC3DOWNTO2_intermed_3 <= RIN_A_CTRL_PC3DOWNTO2_intermed_2;
RIN_A_CTRL_PC3DOWNTO2_intermed_4 <= RIN_A_CTRL_PC3DOWNTO2_intermed_3;
RIN_A_CTRL_PC3DOWNTO2_intermed_5 <= RIN_A_CTRL_PC3DOWNTO2_intermed_4;
RIN_A_CTRL_PC3DOWNTO2_intermed_6 <= RIN_A_CTRL_PC3DOWNTO2_intermed_5;
XC_TRAP_ADDRESS3DOWNTO2_shadow_intermed_1 <= XC_TRAP_ADDRESS3DOWNTO2_shadow;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC3DOWNTO2_shadow;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_4;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_5;
IR_ADDR3DOWNTO2_intermed_1 <= IR.ADDR( 3 DOWNTO 2 );
V_M_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC3DOWNTO2_shadow;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_2;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_3;
R_X_CTRL_PC3DOWNTO2_intermed_1 <= R.X.CTRL.PC( 3 DOWNTO 2 );
R_X_CTRL_PC3DOWNTO2_intermed_2 <= R_X_CTRL_PC3DOWNTO2_intermed_1;
RIN_E_CTRL_PC3DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 3 DOWNTO 2 );
RIN_E_CTRL_PC3DOWNTO2_intermed_2 <= RIN_E_CTRL_PC3DOWNTO2_intermed_1;
RIN_E_CTRL_PC3DOWNTO2_intermed_3 <= RIN_E_CTRL_PC3DOWNTO2_intermed_2;
RIN_E_CTRL_PC3DOWNTO2_intermed_4 <= RIN_E_CTRL_PC3DOWNTO2_intermed_3;
RIN_E_CTRL_PC3DOWNTO2_intermed_5 <= RIN_E_CTRL_PC3DOWNTO2_intermed_4;
RIN_F_PC3DOWNTO2_intermed_1 <= RIN.F.PC( 3 DOWNTO 2 );
R_D_PC3DOWNTO2_intermed_1 <= R.D.PC( 3 DOWNTO 2 );
R_D_PC3DOWNTO2_intermed_2 <= R_D_PC3DOWNTO2_intermed_1;
R_D_PC3DOWNTO2_intermed_3 <= R_D_PC3DOWNTO2_intermed_2;
R_D_PC3DOWNTO2_intermed_4 <= R_D_PC3DOWNTO2_intermed_3;
R_D_PC3DOWNTO2_intermed_5 <= R_D_PC3DOWNTO2_intermed_4;
V_D_PC3DOWNTO2_shadow_intermed_1 <= V_D_PC3DOWNTO2_shadow;
V_D_PC3DOWNTO2_shadow_intermed_2 <= V_D_PC3DOWNTO2_shadow_intermed_1;
V_D_PC3DOWNTO2_shadow_intermed_3 <= V_D_PC3DOWNTO2_shadow_intermed_2;
V_D_PC3DOWNTO2_shadow_intermed_4 <= V_D_PC3DOWNTO2_shadow_intermed_3;
V_D_PC3DOWNTO2_shadow_intermed_5 <= V_D_PC3DOWNTO2_shadow_intermed_4;
V_D_PC3DOWNTO2_shadow_intermed_6 <= V_D_PC3DOWNTO2_shadow_intermed_5;
RIN_D_PC3DOWNTO2_intermed_1 <= RIN.D.PC( 3 DOWNTO 2 );
RIN_D_PC3DOWNTO2_intermed_2 <= RIN_D_PC3DOWNTO2_intermed_1;
RIN_D_PC3DOWNTO2_intermed_3 <= RIN_D_PC3DOWNTO2_intermed_2;
RIN_D_PC3DOWNTO2_intermed_4 <= RIN_D_PC3DOWNTO2_intermed_3;
RIN_D_PC3DOWNTO2_intermed_5 <= RIN_D_PC3DOWNTO2_intermed_4;
RIN_D_PC3DOWNTO2_intermed_6 <= RIN_D_PC3DOWNTO2_intermed_5;
R_M_CTRL_PC3DOWNTO2_intermed_1 <= R.M.CTRL.PC( 3 DOWNTO 2 );
R_M_CTRL_PC3DOWNTO2_intermed_2 <= R_M_CTRL_PC3DOWNTO2_intermed_1;
R_E_CTRL_PC3DOWNTO2_intermed_1 <= R.E.CTRL.PC( 3 DOWNTO 2 );
R_E_CTRL_PC3DOWNTO2_intermed_2 <= R_E_CTRL_PC3DOWNTO2_intermed_1;
R_E_CTRL_PC3DOWNTO2_intermed_3 <= R_E_CTRL_PC3DOWNTO2_intermed_2;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC3DOWNTO2_shadow;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_3;
RIN_X_CTRL_PC3DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 3 DOWNTO 2 );
RIN_X_CTRL_PC3DOWNTO2_intermed_2 <= RIN_X_CTRL_PC3DOWNTO2_intermed_1;
R_A_CTRL_PC3DOWNTO2_intermed_1 <= R.A.CTRL.PC( 3 DOWNTO 2 );
R_A_CTRL_PC3DOWNTO2_intermed_2 <= R_A_CTRL_PC3DOWNTO2_intermed_1;
R_A_CTRL_PC3DOWNTO2_intermed_3 <= R_A_CTRL_PC3DOWNTO2_intermed_2;
R_A_CTRL_PC3DOWNTO2_intermed_4 <= R_A_CTRL_PC3DOWNTO2_intermed_3;
V_X_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC3DOWNTO2_shadow;
V_X_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC3DOWNTO2_shadow_intermed_1;
RIN_M_CTRL_PC3DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 3 DOWNTO 2 );
RIN_M_CTRL_PC3DOWNTO2_intermed_2 <= RIN_M_CTRL_PC3DOWNTO2_intermed_1;
RIN_M_CTRL_PC3DOWNTO2_intermed_3 <= RIN_M_CTRL_PC3DOWNTO2_intermed_2;
IRIN_ADDR3DOWNTO2_intermed_1 <= IRIN.ADDR( 3 DOWNTO 2 );
RIN_A_CTRL_PC3DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 3 DOWNTO 2 );
RIN_A_CTRL_PC3DOWNTO2_intermed_2 <= RIN_A_CTRL_PC3DOWNTO2_intermed_1;
RIN_A_CTRL_PC3DOWNTO2_intermed_3 <= RIN_A_CTRL_PC3DOWNTO2_intermed_2;
RIN_A_CTRL_PC3DOWNTO2_intermed_4 <= RIN_A_CTRL_PC3DOWNTO2_intermed_3;
RIN_A_CTRL_PC3DOWNTO2_intermed_5 <= RIN_A_CTRL_PC3DOWNTO2_intermed_4;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC3DOWNTO2_shadow;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_4;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC3DOWNTO2_shadow;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_2;
R_X_CTRL_PC3DOWNTO2_intermed_1 <= R.X.CTRL.PC( 3 DOWNTO 2 );
RIN_E_CTRL_PC3DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 3 DOWNTO 2 );
RIN_E_CTRL_PC3DOWNTO2_intermed_2 <= RIN_E_CTRL_PC3DOWNTO2_intermed_1;
RIN_E_CTRL_PC3DOWNTO2_intermed_3 <= RIN_E_CTRL_PC3DOWNTO2_intermed_2;
RIN_E_CTRL_PC3DOWNTO2_intermed_4 <= RIN_E_CTRL_PC3DOWNTO2_intermed_3;
RIN_E_CTRL_RD6DOWNTO0_intermed_1 <= RIN.E.CTRL.RD( 6 DOWNTO 0 );
RIN_E_CTRL_RD6DOWNTO0_intermed_2 <= RIN_E_CTRL_RD6DOWNTO0_intermed_1;
RIN_E_CTRL_RD6DOWNTO0_intermed_3 <= RIN_E_CTRL_RD6DOWNTO0_intermed_2;
RIN_M_CTRL_RD6DOWNTO0_intermed_1 <= RIN.M.CTRL.RD( 6 DOWNTO 0 );
RIN_M_CTRL_RD6DOWNTO0_intermed_2 <= RIN_M_CTRL_RD6DOWNTO0_intermed_1;
RIN_X_CTRL_RD6DOWNTO0_intermed_1 <= RIN.X.CTRL.RD( 6 DOWNTO 0 );
V_M_CTRL_RD6DOWNTO0_shadow_intermed_1 <= V_M_CTRL_RD6DOWNTO0_shadow;
V_M_CTRL_RD6DOWNTO0_shadow_intermed_2 <= V_M_CTRL_RD6DOWNTO0_shadow_intermed_1;
R_E_CTRL_RD6DOWNTO0_intermed_1 <= R.E.CTRL.RD( 6 DOWNTO 0 );
R_E_CTRL_RD6DOWNTO0_intermed_2 <= R_E_CTRL_RD6DOWNTO0_intermed_1;
V_E_CTRL_RD6DOWNTO0_shadow_intermed_1 <= V_E_CTRL_RD6DOWNTO0_shadow;
V_E_CTRL_RD6DOWNTO0_shadow_intermed_2 <= V_E_CTRL_RD6DOWNTO0_shadow_intermed_1;
V_E_CTRL_RD6DOWNTO0_shadow_intermed_3 <= V_E_CTRL_RD6DOWNTO0_shadow_intermed_2;
V_A_CTRL_RD6DOWNTO0_shadow_intermed_1 <= V_A_CTRL_RD6DOWNTO0_shadow;
V_A_CTRL_RD6DOWNTO0_shadow_intermed_2 <= V_A_CTRL_RD6DOWNTO0_shadow_intermed_1;
V_A_CTRL_RD6DOWNTO0_shadow_intermed_3 <= V_A_CTRL_RD6DOWNTO0_shadow_intermed_2;
V_A_CTRL_RD6DOWNTO0_shadow_intermed_4 <= V_A_CTRL_RD6DOWNTO0_shadow_intermed_3;
R_A_CTRL_RD6DOWNTO0_intermed_1 <= R.A.CTRL.RD( 6 DOWNTO 0 );
R_A_CTRL_RD6DOWNTO0_intermed_2 <= R_A_CTRL_RD6DOWNTO0_intermed_1;
R_A_CTRL_RD6DOWNTO0_intermed_3 <= R_A_CTRL_RD6DOWNTO0_intermed_2;
RIN_A_CTRL_RD6DOWNTO0_intermed_1 <= RIN.A.CTRL.RD( 6 DOWNTO 0 );
RIN_A_CTRL_RD6DOWNTO0_intermed_2 <= RIN_A_CTRL_RD6DOWNTO0_intermed_1;
RIN_A_CTRL_RD6DOWNTO0_intermed_3 <= RIN_A_CTRL_RD6DOWNTO0_intermed_2;
RIN_A_CTRL_RD6DOWNTO0_intermed_4 <= RIN_A_CTRL_RD6DOWNTO0_intermed_3;
R_M_CTRL_RD6DOWNTO0_intermed_1 <= R.M.CTRL.RD( 6 DOWNTO 0 );
V_E_CTRL_TT_shadow_intermed_1 <= V_E_CTRL_TT_shadow;
V_E_CTRL_TT_shadow_intermed_2 <= V_E_CTRL_TT_shadow_intermed_1;
RIN_A_CTRL_TT_intermed_1 <= RIN.A.CTRL.TT;
RIN_A_CTRL_TT_intermed_2 <= RIN_A_CTRL_TT_intermed_1;
RIN_A_CTRL_TT_intermed_3 <= RIN_A_CTRL_TT_intermed_2;
R_A_CTRL_TT_intermed_1 <= R.A.CTRL.TT;
R_A_CTRL_TT_intermed_2 <= R_A_CTRL_TT_intermed_1;
R_E_CTRL_TT_intermed_1 <= R.E.CTRL.TT;
RIN_M_CTRL_TT_intermed_1 <= RIN.M.CTRL.TT;
RIN_E_CTRL_TT_intermed_1 <= RIN.E.CTRL.TT;
RIN_E_CTRL_TT_intermed_2 <= RIN_E_CTRL_TT_intermed_1;
V_A_CTRL_TT_shadow_intermed_1 <= V_A_CTRL_TT_shadow;
V_A_CTRL_TT_shadow_intermed_2 <= V_A_CTRL_TT_shadow_intermed_1;
V_A_CTRL_TT_shadow_intermed_3 <= V_A_CTRL_TT_shadow_intermed_2;
R_A_CTRL_LD_intermed_1 <= R.A.CTRL.LD;
RIN_A_CTRL_LD_intermed_1 <= RIN.A.CTRL.LD;
RIN_A_CTRL_LD_intermed_2 <= RIN_A_CTRL_LD_intermed_1;
RIN_E_CTRL_LD_intermed_1 <= RIN.E.CTRL.LD;
V_A_CTRL_LD_shadow_intermed_1 <= V_A_CTRL_LD_shadow;
V_A_CTRL_LD_shadow_intermed_2 <= V_A_CTRL_LD_shadow_intermed_1;
R_M_CTRL_PC31DOWNTO12_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 12 );
R_M_CTRL_PC31DOWNTO12_intermed_2 <= R_M_CTRL_PC31DOWNTO12_intermed_1;
R_M_CTRL_PC31DOWNTO12_intermed_3 <= R_M_CTRL_PC31DOWNTO12_intermed_2;
V_D_PC31DOWNTO12_shadow_intermed_1 <= V_D_PC31DOWNTO12_shadow;
V_D_PC31DOWNTO12_shadow_intermed_2 <= V_D_PC31DOWNTO12_shadow_intermed_1;
V_D_PC31DOWNTO12_shadow_intermed_3 <= V_D_PC31DOWNTO12_shadow_intermed_2;
V_D_PC31DOWNTO12_shadow_intermed_4 <= V_D_PC31DOWNTO12_shadow_intermed_3;
V_D_PC31DOWNTO12_shadow_intermed_5 <= V_D_PC31DOWNTO12_shadow_intermed_4;
V_D_PC31DOWNTO12_shadow_intermed_6 <= V_D_PC31DOWNTO12_shadow_intermed_5;
V_D_PC31DOWNTO12_shadow_intermed_7 <= V_D_PC31DOWNTO12_shadow_intermed_6;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO12_shadow;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_5;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO12_shadow;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_4;
EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_1 <= EX_ADD_RES32DOWNTO330DOWNTO11_shadow;
RIN_F_PC31DOWNTO12_intermed_1 <= RIN.F.PC( 31 DOWNTO 12 );
R_A_CTRL_PC31DOWNTO12_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 12 );
R_A_CTRL_PC31DOWNTO12_intermed_2 <= R_A_CTRL_PC31DOWNTO12_intermed_1;
R_A_CTRL_PC31DOWNTO12_intermed_3 <= R_A_CTRL_PC31DOWNTO12_intermed_2;
R_A_CTRL_PC31DOWNTO12_intermed_4 <= R_A_CTRL_PC31DOWNTO12_intermed_3;
R_A_CTRL_PC31DOWNTO12_intermed_5 <= R_A_CTRL_PC31DOWNTO12_intermed_4;
R_E_CTRL_PC31DOWNTO12_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 12 );
R_E_CTRL_PC31DOWNTO12_intermed_2 <= R_E_CTRL_PC31DOWNTO12_intermed_1;
R_E_CTRL_PC31DOWNTO12_intermed_3 <= R_E_CTRL_PC31DOWNTO12_intermed_2;
R_E_CTRL_PC31DOWNTO12_intermed_4 <= R_E_CTRL_PC31DOWNTO12_intermed_3;
EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO12_shadow;
RIN_A_CTRL_PC31DOWNTO12_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_2 <= RIN_A_CTRL_PC31DOWNTO12_intermed_1;
RIN_A_CTRL_PC31DOWNTO12_intermed_3 <= RIN_A_CTRL_PC31DOWNTO12_intermed_2;
RIN_A_CTRL_PC31DOWNTO12_intermed_4 <= RIN_A_CTRL_PC31DOWNTO12_intermed_3;
RIN_A_CTRL_PC31DOWNTO12_intermed_5 <= RIN_A_CTRL_PC31DOWNTO12_intermed_4;
RIN_A_CTRL_PC31DOWNTO12_intermed_6 <= RIN_A_CTRL_PC31DOWNTO12_intermed_5;
RIN_E_CTRL_PC31DOWNTO12_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 12 );
RIN_E_CTRL_PC31DOWNTO12_intermed_2 <= RIN_E_CTRL_PC31DOWNTO12_intermed_1;
RIN_E_CTRL_PC31DOWNTO12_intermed_3 <= RIN_E_CTRL_PC31DOWNTO12_intermed_2;
RIN_E_CTRL_PC31DOWNTO12_intermed_4 <= RIN_E_CTRL_PC31DOWNTO12_intermed_3;
RIN_E_CTRL_PC31DOWNTO12_intermed_5 <= RIN_E_CTRL_PC31DOWNTO12_intermed_4;
IRIN_ADDR31DOWNTO12_intermed_1 <= IRIN.ADDR( 31 DOWNTO 12 );
IRIN_ADDR31DOWNTO12_intermed_2 <= IRIN_ADDR31DOWNTO12_intermed_1;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO12_shadow;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_2;
EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO13_shadow;
XC_TRAP_ADDRESS31DOWNTO12_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO12_shadow;
RIN_M_CTRL_PC31DOWNTO12_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 12 );
RIN_M_CTRL_PC31DOWNTO12_intermed_2 <= RIN_M_CTRL_PC31DOWNTO12_intermed_1;
RIN_M_CTRL_PC31DOWNTO12_intermed_3 <= RIN_M_CTRL_PC31DOWNTO12_intermed_2;
RIN_M_CTRL_PC31DOWNTO12_intermed_4 <= RIN_M_CTRL_PC31DOWNTO12_intermed_3;
IR_ADDR31DOWNTO12_intermed_1 <= IR.ADDR( 31 DOWNTO 12 );
R_X_CTRL_PC31DOWNTO12_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 12 );
R_X_CTRL_PC31DOWNTO12_intermed_2 <= R_X_CTRL_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_1 <= R.D.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_2 <= R_D_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_3 <= R_D_PC31DOWNTO12_intermed_2;
R_D_PC31DOWNTO12_intermed_4 <= R_D_PC31DOWNTO12_intermed_3;
R_D_PC31DOWNTO12_intermed_5 <= R_D_PC31DOWNTO12_intermed_4;
R_D_PC31DOWNTO12_intermed_6 <= R_D_PC31DOWNTO12_intermed_5;
RIN_X_CTRL_PC31DOWNTO12_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 12 );
RIN_X_CTRL_PC31DOWNTO12_intermed_2 <= RIN_X_CTRL_PC31DOWNTO12_intermed_1;
RIN_X_CTRL_PC31DOWNTO12_intermed_3 <= RIN_X_CTRL_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_1 <= RIN.D.PC( 31 DOWNTO 12 );
RIN_D_PC31DOWNTO12_intermed_2 <= RIN_D_PC31DOWNTO12_intermed_1;
RIN_D_PC31DOWNTO12_intermed_3 <= RIN_D_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_4 <= RIN_D_PC31DOWNTO12_intermed_3;
RIN_D_PC31DOWNTO12_intermed_5 <= RIN_D_PC31DOWNTO12_intermed_4;
RIN_D_PC31DOWNTO12_intermed_6 <= RIN_D_PC31DOWNTO12_intermed_5;
RIN_D_PC31DOWNTO12_intermed_7 <= RIN_D_PC31DOWNTO12_intermed_6;
VIR_ADDR31DOWNTO12_shadow_intermed_1 <= VIR_ADDR31DOWNTO12_shadow;
VIR_ADDR31DOWNTO12_shadow_intermed_2 <= VIR_ADDR31DOWNTO12_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO12_shadow;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_X_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_X_CTRL_TT3DOWNTO0_shadow;
R_M_CTRL_TT3DOWNTO0_intermed_1 <= R.M.CTRL.TT( 3 DOWNTO 0 );
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1;
R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
R_A_CTRL_TT3DOWNTO0_intermed_1 <= R.A.CTRL.TT( 3 DOWNTO 0 );
R_A_CTRL_TT3DOWNTO0_intermed_2 <= R_A_CTRL_TT3DOWNTO0_intermed_1;
R_A_CTRL_TT3DOWNTO0_intermed_3 <= R_A_CTRL_TT3DOWNTO0_intermed_2;
RIN_A_CTRL_TT3DOWNTO0_intermed_1 <= RIN.A.CTRL.TT( 3 DOWNTO 0 );
RIN_A_CTRL_TT3DOWNTO0_intermed_2 <= RIN_A_CTRL_TT3DOWNTO0_intermed_1;
RIN_A_CTRL_TT3DOWNTO0_intermed_3 <= RIN_A_CTRL_TT3DOWNTO0_intermed_2;
RIN_A_CTRL_TT3DOWNTO0_intermed_4 <= RIN_A_CTRL_TT3DOWNTO0_intermed_3;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_A_CTRL_TT3DOWNTO0_shadow;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_2;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_4 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_3;
R_E_CTRL_TT3DOWNTO0_intermed_1 <= R.E.CTRL.TT( 3 DOWNTO 0 );
R_E_CTRL_TT3DOWNTO0_intermed_2 <= R_E_CTRL_TT3DOWNTO0_intermed_1;
RIN_M_CTRL_TT3DOWNTO0_intermed_1 <= RIN.M.CTRL.TT( 3 DOWNTO 0 );
RIN_M_CTRL_TT3DOWNTO0_intermed_2 <= RIN_M_CTRL_TT3DOWNTO0_intermed_1;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_M_CTRL_TT3DOWNTO0_shadow;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_M_CTRL_TT3DOWNTO0_shadow_intermed_1;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 );
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_E_CTRL_TT3DOWNTO0_shadow;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_2;
RIN_X_CTRL_TT3DOWNTO0_intermed_1 <= RIN.X.CTRL.TT( 3 DOWNTO 0 );
RIN_E_CTRL_TT3DOWNTO0_intermed_1 <= RIN.E.CTRL.TT( 3 DOWNTO 0 );
RIN_E_CTRL_TT3DOWNTO0_intermed_2 <= RIN_E_CTRL_TT3DOWNTO0_intermed_1;
RIN_E_CTRL_TT3DOWNTO0_intermed_3 <= RIN_E_CTRL_TT3DOWNTO0_intermed_2;
V_X_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_X_CTRL_TT3DOWNTO0_shadow;
V_X_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_X_CTRL_TT3DOWNTO0_shadow_intermed_1;
R_M_CTRL_TT3DOWNTO0_intermed_1 <= R.M.CTRL.TT( 3 DOWNTO 0 );
R_M_CTRL_TT3DOWNTO0_intermed_2 <= R_M_CTRL_TT3DOWNTO0_intermed_1;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_3 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2;
R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
R_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= R_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
R_A_CTRL_TT3DOWNTO0_intermed_1 <= R.A.CTRL.TT( 3 DOWNTO 0 );
R_A_CTRL_TT3DOWNTO0_intermed_2 <= R_A_CTRL_TT3DOWNTO0_intermed_1;
R_A_CTRL_TT3DOWNTO0_intermed_3 <= R_A_CTRL_TT3DOWNTO0_intermed_2;
R_A_CTRL_TT3DOWNTO0_intermed_4 <= R_A_CTRL_TT3DOWNTO0_intermed_3;
RIN_A_CTRL_TT3DOWNTO0_intermed_1 <= RIN.A.CTRL.TT( 3 DOWNTO 0 );
RIN_A_CTRL_TT3DOWNTO0_intermed_2 <= RIN_A_CTRL_TT3DOWNTO0_intermed_1;
RIN_A_CTRL_TT3DOWNTO0_intermed_3 <= RIN_A_CTRL_TT3DOWNTO0_intermed_2;
RIN_A_CTRL_TT3DOWNTO0_intermed_4 <= RIN_A_CTRL_TT3DOWNTO0_intermed_3;
RIN_A_CTRL_TT3DOWNTO0_intermed_5 <= RIN_A_CTRL_TT3DOWNTO0_intermed_4;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_A_CTRL_TT3DOWNTO0_shadow;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_2;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_4 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_3;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_5 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_4;
R_E_CTRL_TT3DOWNTO0_intermed_1 <= R.E.CTRL.TT( 3 DOWNTO 0 );
R_E_CTRL_TT3DOWNTO0_intermed_2 <= R_E_CTRL_TT3DOWNTO0_intermed_1;
R_E_CTRL_TT3DOWNTO0_intermed_3 <= R_E_CTRL_TT3DOWNTO0_intermed_2;
RIN_W_S_TT3DOWNTO0_intermed_1 <= RIN.W.S.TT( 3 DOWNTO 0 );
RIN_M_CTRL_TT3DOWNTO0_intermed_1 <= RIN.M.CTRL.TT( 3 DOWNTO 0 );
RIN_M_CTRL_TT3DOWNTO0_intermed_2 <= RIN_M_CTRL_TT3DOWNTO0_intermed_1;
RIN_M_CTRL_TT3DOWNTO0_intermed_3 <= RIN_M_CTRL_TT3DOWNTO0_intermed_2;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_M_CTRL_TT3DOWNTO0_shadow;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_M_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_M_CTRL_TT3DOWNTO0_shadow_intermed_2;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_3 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 );
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_E_CTRL_TT3DOWNTO0_shadow;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_2;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_4 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_3;
RIN_X_CTRL_TT3DOWNTO0_intermed_1 <= RIN.X.CTRL.TT( 3 DOWNTO 0 );
RIN_X_CTRL_TT3DOWNTO0_intermed_2 <= RIN_X_CTRL_TT3DOWNTO0_intermed_1;
R_X_CTRL_TT3DOWNTO0_intermed_1 <= R.X.CTRL.TT( 3 DOWNTO 0 );
RIN_E_CTRL_TT3DOWNTO0_intermed_1 <= RIN.E.CTRL.TT( 3 DOWNTO 0 );
RIN_E_CTRL_TT3DOWNTO0_intermed_2 <= RIN_E_CTRL_TT3DOWNTO0_intermed_1;
RIN_E_CTRL_TT3DOWNTO0_intermed_3 <= RIN_E_CTRL_TT3DOWNTO0_intermed_2;
RIN_E_CTRL_TT3DOWNTO0_intermed_4 <= RIN_E_CTRL_TT3DOWNTO0_intermed_3;
XC_VECTT3DOWNTO0_shadow_intermed_1 <= XC_VECTT3DOWNTO0_shadow;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
V_X_DATA03_shadow_intermed_1 <= V_X_DATA03_shadow;
V_X_DATA03_shadow_intermed_2 <= V_X_DATA03_shadow_intermed_1;
DCO_DATA03_intermed_1 <= DCO.DATA ( 0 )( 3 );
RIN_X_DATA03_intermed_1 <= RIN.X.DATA ( 0 )( 3 );
R_X_DATA03_intermed_1 <= R.X.DATA( 0 )( 3 );
RIN_X_DATA03_intermed_1 <= RIN.X.DATA( 0 )( 3 );
RIN_X_DATA03_intermed_2 <= RIN_X_DATA03_intermed_1;
R_M_CTRL_PC31DOWNTO12_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 12 );
R_M_CTRL_PC31DOWNTO12_intermed_2 <= R_M_CTRL_PC31DOWNTO12_intermed_1;
V_D_PC31DOWNTO12_shadow_intermed_1 <= V_D_PC31DOWNTO12_shadow;
V_D_PC31DOWNTO12_shadow_intermed_2 <= V_D_PC31DOWNTO12_shadow_intermed_1;
V_D_PC31DOWNTO12_shadow_intermed_3 <= V_D_PC31DOWNTO12_shadow_intermed_2;
V_D_PC31DOWNTO12_shadow_intermed_4 <= V_D_PC31DOWNTO12_shadow_intermed_3;
V_D_PC31DOWNTO12_shadow_intermed_5 <= V_D_PC31DOWNTO12_shadow_intermed_4;
V_D_PC31DOWNTO12_shadow_intermed_6 <= V_D_PC31DOWNTO12_shadow_intermed_5;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO12_shadow;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_4;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO12_shadow;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_3;
R_A_CTRL_PC31DOWNTO12_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 12 );
R_A_CTRL_PC31DOWNTO12_intermed_2 <= R_A_CTRL_PC31DOWNTO12_intermed_1;
R_A_CTRL_PC31DOWNTO12_intermed_3 <= R_A_CTRL_PC31DOWNTO12_intermed_2;
R_A_CTRL_PC31DOWNTO12_intermed_4 <= R_A_CTRL_PC31DOWNTO12_intermed_3;
R_E_CTRL_PC31DOWNTO12_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 12 );
R_E_CTRL_PC31DOWNTO12_intermed_2 <= R_E_CTRL_PC31DOWNTO12_intermed_1;
R_E_CTRL_PC31DOWNTO12_intermed_3 <= R_E_CTRL_PC31DOWNTO12_intermed_2;
RIN_A_CTRL_PC31DOWNTO12_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_2 <= RIN_A_CTRL_PC31DOWNTO12_intermed_1;
RIN_A_CTRL_PC31DOWNTO12_intermed_3 <= RIN_A_CTRL_PC31DOWNTO12_intermed_2;
RIN_A_CTRL_PC31DOWNTO12_intermed_4 <= RIN_A_CTRL_PC31DOWNTO12_intermed_3;
RIN_A_CTRL_PC31DOWNTO12_intermed_5 <= RIN_A_CTRL_PC31DOWNTO12_intermed_4;
RIN_E_CTRL_PC31DOWNTO12_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 12 );
RIN_E_CTRL_PC31DOWNTO12_intermed_2 <= RIN_E_CTRL_PC31DOWNTO12_intermed_1;
RIN_E_CTRL_PC31DOWNTO12_intermed_3 <= RIN_E_CTRL_PC31DOWNTO12_intermed_2;
RIN_E_CTRL_PC31DOWNTO12_intermed_4 <= RIN_E_CTRL_PC31DOWNTO12_intermed_3;
IRIN_ADDR31DOWNTO12_intermed_1 <= IRIN.ADDR( 31 DOWNTO 12 );
V_X_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO12_shadow;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_1;
RIN_M_CTRL_PC31DOWNTO12_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 12 );
RIN_M_CTRL_PC31DOWNTO12_intermed_2 <= RIN_M_CTRL_PC31DOWNTO12_intermed_1;
RIN_M_CTRL_PC31DOWNTO12_intermed_3 <= RIN_M_CTRL_PC31DOWNTO12_intermed_2;
R_X_CTRL_PC31DOWNTO12_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_1 <= R.D.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_2 <= R_D_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_3 <= R_D_PC31DOWNTO12_intermed_2;
R_D_PC31DOWNTO12_intermed_4 <= R_D_PC31DOWNTO12_intermed_3;
R_D_PC31DOWNTO12_intermed_5 <= R_D_PC31DOWNTO12_intermed_4;
RIN_X_CTRL_PC31DOWNTO12_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 12 );
RIN_X_CTRL_PC31DOWNTO12_intermed_2 <= RIN_X_CTRL_PC31DOWNTO12_intermed_1;
RIN_D_PC31DOWNTO12_intermed_1 <= RIN.D.PC( 31 DOWNTO 12 );
RIN_D_PC31DOWNTO12_intermed_2 <= RIN_D_PC31DOWNTO12_intermed_1;
RIN_D_PC31DOWNTO12_intermed_3 <= RIN_D_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_4 <= RIN_D_PC31DOWNTO12_intermed_3;
RIN_D_PC31DOWNTO12_intermed_5 <= RIN_D_PC31DOWNTO12_intermed_4;
RIN_D_PC31DOWNTO12_intermed_6 <= RIN_D_PC31DOWNTO12_intermed_5;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO12_shadow;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
V_D_PC31DOWNTO2_shadow_intermed_6 <= V_D_PC31DOWNTO2_shadow_intermed_5;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_D_PC31DOWNTO2_intermed_6 <= RIN_D_PC31DOWNTO2_intermed_5;
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
IRIN_ADDR31DOWNTO2_intermed_1 <= IRIN.ADDR( 31 DOWNTO 2 );
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_D_PC31DOWNTO2_intermed_5 <= R_D_PC31DOWNTO2_intermed_4;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_F_PC31DOWNTO4_shadow_intermed_1 <= V_F_PC31DOWNTO4_shadow;
V_X_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO4_shadow;
V_X_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO4_shadow_intermed_2;
IR_ADDR31DOWNTO4_intermed_1 <= IR.ADDR( 31 DOWNTO 4 );
VIR_ADDR31DOWNTO4_shadow_intermed_1 <= VIR_ADDR31DOWNTO4_shadow;
VIR_ADDR31DOWNTO4_shadow_intermed_2 <= VIR_ADDR31DOWNTO4_shadow_intermed_1;
RIN_F_PC31DOWNTO4_intermed_1 <= RIN.F.PC( 31 DOWNTO 4 );
RIN_A_CTRL_PC31DOWNTO4_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 4 );
RIN_A_CTRL_PC31DOWNTO4_intermed_2 <= RIN_A_CTRL_PC31DOWNTO4_intermed_1;
RIN_A_CTRL_PC31DOWNTO4_intermed_3 <= RIN_A_CTRL_PC31DOWNTO4_intermed_2;
RIN_A_CTRL_PC31DOWNTO4_intermed_4 <= RIN_A_CTRL_PC31DOWNTO4_intermed_3;
RIN_A_CTRL_PC31DOWNTO4_intermed_5 <= RIN_A_CTRL_PC31DOWNTO4_intermed_4;
RIN_A_CTRL_PC31DOWNTO4_intermed_6 <= RIN_A_CTRL_PC31DOWNTO4_intermed_5;
R_A_CTRL_PC31DOWNTO4_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 4 );
R_A_CTRL_PC31DOWNTO4_intermed_2 <= R_A_CTRL_PC31DOWNTO4_intermed_1;
R_A_CTRL_PC31DOWNTO4_intermed_3 <= R_A_CTRL_PC31DOWNTO4_intermed_2;
R_A_CTRL_PC31DOWNTO4_intermed_4 <= R_A_CTRL_PC31DOWNTO4_intermed_3;
R_A_CTRL_PC31DOWNTO4_intermed_5 <= R_A_CTRL_PC31DOWNTO4_intermed_4;
R_D_PC31DOWNTO4_intermed_1 <= R.D.PC( 31 DOWNTO 4 );
R_D_PC31DOWNTO4_intermed_2 <= R_D_PC31DOWNTO4_intermed_1;
R_D_PC31DOWNTO4_intermed_3 <= R_D_PC31DOWNTO4_intermed_2;
R_D_PC31DOWNTO4_intermed_4 <= R_D_PC31DOWNTO4_intermed_3;
R_D_PC31DOWNTO4_intermed_5 <= R_D_PC31DOWNTO4_intermed_4;
R_D_PC31DOWNTO4_intermed_6 <= R_D_PC31DOWNTO4_intermed_5;
RIN_X_CTRL_PC31DOWNTO4_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 4 );
RIN_X_CTRL_PC31DOWNTO4_intermed_2 <= RIN_X_CTRL_PC31DOWNTO4_intermed_1;
RIN_X_CTRL_PC31DOWNTO4_intermed_3 <= RIN_X_CTRL_PC31DOWNTO4_intermed_2;
EX_ADD_RES32DOWNTO332DOWNTO5_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO5_shadow;
V_D_PC31DOWNTO4_shadow_intermed_1 <= V_D_PC31DOWNTO4_shadow;
V_D_PC31DOWNTO4_shadow_intermed_2 <= V_D_PC31DOWNTO4_shadow_intermed_1;
V_D_PC31DOWNTO4_shadow_intermed_3 <= V_D_PC31DOWNTO4_shadow_intermed_2;
V_D_PC31DOWNTO4_shadow_intermed_4 <= V_D_PC31DOWNTO4_shadow_intermed_3;
V_D_PC31DOWNTO4_shadow_intermed_5 <= V_D_PC31DOWNTO4_shadow_intermed_4;
V_D_PC31DOWNTO4_shadow_intermed_6 <= V_D_PC31DOWNTO4_shadow_intermed_5;
V_D_PC31DOWNTO4_shadow_intermed_7 <= V_D_PC31DOWNTO4_shadow_intermed_6;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO4_shadow;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_4;
RIN_M_CTRL_PC31DOWNTO4_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 4 );
RIN_M_CTRL_PC31DOWNTO4_intermed_2 <= RIN_M_CTRL_PC31DOWNTO4_intermed_1;
RIN_M_CTRL_PC31DOWNTO4_intermed_3 <= RIN_M_CTRL_PC31DOWNTO4_intermed_2;
RIN_M_CTRL_PC31DOWNTO4_intermed_4 <= RIN_M_CTRL_PC31DOWNTO4_intermed_3;
R_X_CTRL_PC31DOWNTO4_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 4 );
R_X_CTRL_PC31DOWNTO4_intermed_2 <= R_X_CTRL_PC31DOWNTO4_intermed_1;
IRIN_ADDR31DOWNTO4_intermed_1 <= IRIN.ADDR( 31 DOWNTO 4 );
IRIN_ADDR31DOWNTO4_intermed_2 <= IRIN_ADDR31DOWNTO4_intermed_1;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO4_shadow;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_3;
R_M_CTRL_PC31DOWNTO4_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 4 );
R_M_CTRL_PC31DOWNTO4_intermed_2 <= R_M_CTRL_PC31DOWNTO4_intermed_1;
R_M_CTRL_PC31DOWNTO4_intermed_3 <= R_M_CTRL_PC31DOWNTO4_intermed_2;
RIN_D_PC31DOWNTO4_intermed_1 <= RIN.D.PC( 31 DOWNTO 4 );
RIN_D_PC31DOWNTO4_intermed_2 <= RIN_D_PC31DOWNTO4_intermed_1;
RIN_D_PC31DOWNTO4_intermed_3 <= RIN_D_PC31DOWNTO4_intermed_2;
RIN_D_PC31DOWNTO4_intermed_4 <= RIN_D_PC31DOWNTO4_intermed_3;
RIN_D_PC31DOWNTO4_intermed_5 <= RIN_D_PC31DOWNTO4_intermed_4;
RIN_D_PC31DOWNTO4_intermed_6 <= RIN_D_PC31DOWNTO4_intermed_5;
RIN_D_PC31DOWNTO4_intermed_7 <= RIN_D_PC31DOWNTO4_intermed_6;
RIN_E_CTRL_PC31DOWNTO4_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 4 );
RIN_E_CTRL_PC31DOWNTO4_intermed_2 <= RIN_E_CTRL_PC31DOWNTO4_intermed_1;
RIN_E_CTRL_PC31DOWNTO4_intermed_3 <= RIN_E_CTRL_PC31DOWNTO4_intermed_2;
RIN_E_CTRL_PC31DOWNTO4_intermed_4 <= RIN_E_CTRL_PC31DOWNTO4_intermed_3;
RIN_E_CTRL_PC31DOWNTO4_intermed_5 <= RIN_E_CTRL_PC31DOWNTO4_intermed_4;
EX_JUMP_ADDRESS31DOWNTO4_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO4_shadow;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO4_shadow;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_5;
R_E_CTRL_PC31DOWNTO4_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 4 );
R_E_CTRL_PC31DOWNTO4_intermed_2 <= R_E_CTRL_PC31DOWNTO4_intermed_1;
R_E_CTRL_PC31DOWNTO4_intermed_3 <= R_E_CTRL_PC31DOWNTO4_intermed_2;
R_E_CTRL_PC31DOWNTO4_intermed_4 <= R_E_CTRL_PC31DOWNTO4_intermed_3;
R_D_PC3DOWNTO2_intermed_1 <= R.D.PC( 3 DOWNTO 2 );
R_D_PC3DOWNTO2_intermed_2 <= R_D_PC3DOWNTO2_intermed_1;
R_D_PC3DOWNTO2_intermed_3 <= R_D_PC3DOWNTO2_intermed_2;
R_D_PC3DOWNTO2_intermed_4 <= R_D_PC3DOWNTO2_intermed_3;
R_D_PC3DOWNTO2_intermed_5 <= R_D_PC3DOWNTO2_intermed_4;
R_D_PC3DOWNTO2_intermed_6 <= R_D_PC3DOWNTO2_intermed_5;
V_D_PC3DOWNTO2_shadow_intermed_1 <= V_D_PC3DOWNTO2_shadow;
V_D_PC3DOWNTO2_shadow_intermed_2 <= V_D_PC3DOWNTO2_shadow_intermed_1;
V_D_PC3DOWNTO2_shadow_intermed_3 <= V_D_PC3DOWNTO2_shadow_intermed_2;
V_D_PC3DOWNTO2_shadow_intermed_4 <= V_D_PC3DOWNTO2_shadow_intermed_3;
V_D_PC3DOWNTO2_shadow_intermed_5 <= V_D_PC3DOWNTO2_shadow_intermed_4;
V_D_PC3DOWNTO2_shadow_intermed_6 <= V_D_PC3DOWNTO2_shadow_intermed_5;
V_D_PC3DOWNTO2_shadow_intermed_7 <= V_D_PC3DOWNTO2_shadow_intermed_6;
VIR_ADDR3DOWNTO2_shadow_intermed_1 <= VIR_ADDR3DOWNTO2_shadow;
VIR_ADDR3DOWNTO2_shadow_intermed_2 <= VIR_ADDR3DOWNTO2_shadow_intermed_1;
RIN_D_PC3DOWNTO2_intermed_1 <= RIN.D.PC( 3 DOWNTO 2 );
RIN_D_PC3DOWNTO2_intermed_2 <= RIN_D_PC3DOWNTO2_intermed_1;
RIN_D_PC3DOWNTO2_intermed_3 <= RIN_D_PC3DOWNTO2_intermed_2;
RIN_D_PC3DOWNTO2_intermed_4 <= RIN_D_PC3DOWNTO2_intermed_3;
RIN_D_PC3DOWNTO2_intermed_5 <= RIN_D_PC3DOWNTO2_intermed_4;
RIN_D_PC3DOWNTO2_intermed_6 <= RIN_D_PC3DOWNTO2_intermed_5;
RIN_D_PC3DOWNTO2_intermed_7 <= RIN_D_PC3DOWNTO2_intermed_6;
R_M_CTRL_PC3DOWNTO2_intermed_1 <= R.M.CTRL.PC( 3 DOWNTO 2 );
R_M_CTRL_PC3DOWNTO2_intermed_2 <= R_M_CTRL_PC3DOWNTO2_intermed_1;
R_M_CTRL_PC3DOWNTO2_intermed_3 <= R_M_CTRL_PC3DOWNTO2_intermed_2;
R_E_CTRL_PC3DOWNTO2_intermed_1 <= R.E.CTRL.PC( 3 DOWNTO 2 );
R_E_CTRL_PC3DOWNTO2_intermed_2 <= R_E_CTRL_PC3DOWNTO2_intermed_1;
R_E_CTRL_PC3DOWNTO2_intermed_3 <= R_E_CTRL_PC3DOWNTO2_intermed_2;
R_E_CTRL_PC3DOWNTO2_intermed_4 <= R_E_CTRL_PC3DOWNTO2_intermed_3;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC3DOWNTO2_shadow;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_3;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_4;
RIN_X_CTRL_PC3DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 3 DOWNTO 2 );
RIN_X_CTRL_PC3DOWNTO2_intermed_2 <= RIN_X_CTRL_PC3DOWNTO2_intermed_1;
RIN_X_CTRL_PC3DOWNTO2_intermed_3 <= RIN_X_CTRL_PC3DOWNTO2_intermed_2;
R_A_CTRL_PC3DOWNTO2_intermed_1 <= R.A.CTRL.PC( 3 DOWNTO 2 );
R_A_CTRL_PC3DOWNTO2_intermed_2 <= R_A_CTRL_PC3DOWNTO2_intermed_1;
R_A_CTRL_PC3DOWNTO2_intermed_3 <= R_A_CTRL_PC3DOWNTO2_intermed_2;
R_A_CTRL_PC3DOWNTO2_intermed_4 <= R_A_CTRL_PC3DOWNTO2_intermed_3;
R_A_CTRL_PC3DOWNTO2_intermed_5 <= R_A_CTRL_PC3DOWNTO2_intermed_4;
V_X_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC3DOWNTO2_shadow;
V_X_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC3DOWNTO2_shadow_intermed_2;
RIN_M_CTRL_PC3DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 3 DOWNTO 2 );
RIN_M_CTRL_PC3DOWNTO2_intermed_2 <= RIN_M_CTRL_PC3DOWNTO2_intermed_1;
RIN_M_CTRL_PC3DOWNTO2_intermed_3 <= RIN_M_CTRL_PC3DOWNTO2_intermed_2;
RIN_M_CTRL_PC3DOWNTO2_intermed_4 <= RIN_M_CTRL_PC3DOWNTO2_intermed_3;
IRIN_ADDR3DOWNTO2_intermed_1 <= IRIN.ADDR( 3 DOWNTO 2 );
IRIN_ADDR3DOWNTO2_intermed_2 <= IRIN_ADDR3DOWNTO2_intermed_1;
EX_JUMP_ADDRESS3DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS3DOWNTO2_shadow;
EX_ADD_RES32DOWNTO34DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO34DOWNTO3_shadow;
RIN_A_CTRL_PC3DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 3 DOWNTO 2 );
RIN_A_CTRL_PC3DOWNTO2_intermed_2 <= RIN_A_CTRL_PC3DOWNTO2_intermed_1;
RIN_A_CTRL_PC3DOWNTO2_intermed_3 <= RIN_A_CTRL_PC3DOWNTO2_intermed_2;
RIN_A_CTRL_PC3DOWNTO2_intermed_4 <= RIN_A_CTRL_PC3DOWNTO2_intermed_3;
RIN_A_CTRL_PC3DOWNTO2_intermed_5 <= RIN_A_CTRL_PC3DOWNTO2_intermed_4;
RIN_A_CTRL_PC3DOWNTO2_intermed_6 <= RIN_A_CTRL_PC3DOWNTO2_intermed_5;
V_F_PC3DOWNTO2_shadow_intermed_1 <= V_F_PC3DOWNTO2_shadow;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC3DOWNTO2_shadow;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_4;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_5;
IR_ADDR3DOWNTO2_intermed_1 <= IR.ADDR( 3 DOWNTO 2 );
V_M_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC3DOWNTO2_shadow;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_2;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_3;
R_X_CTRL_PC3DOWNTO2_intermed_1 <= R.X.CTRL.PC( 3 DOWNTO 2 );
R_X_CTRL_PC3DOWNTO2_intermed_2 <= R_X_CTRL_PC3DOWNTO2_intermed_1;
RIN_E_CTRL_PC3DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 3 DOWNTO 2 );
RIN_E_CTRL_PC3DOWNTO2_intermed_2 <= RIN_E_CTRL_PC3DOWNTO2_intermed_1;
RIN_E_CTRL_PC3DOWNTO2_intermed_3 <= RIN_E_CTRL_PC3DOWNTO2_intermed_2;
RIN_E_CTRL_PC3DOWNTO2_intermed_4 <= RIN_E_CTRL_PC3DOWNTO2_intermed_3;
RIN_E_CTRL_PC3DOWNTO2_intermed_5 <= RIN_E_CTRL_PC3DOWNTO2_intermed_4;
RIN_F_PC3DOWNTO2_intermed_1 <= RIN.F.PC( 3 DOWNTO 2 );
V_E_CTRL_RD7DOWNTO0_shadow_intermed_1 <= V_E_CTRL_RD7DOWNTO0_shadow;
V_E_CTRL_RD7DOWNTO0_shadow_intermed_2 <= V_E_CTRL_RD7DOWNTO0_shadow_intermed_1;
R_E_CTRL_RD7DOWNTO0_intermed_1 <= R.E.CTRL.RD ( 7 DOWNTO 0 );
V_A_CTRL_RD7DOWNTO0_shadow_intermed_1 <= V_A_CTRL_RD7DOWNTO0_shadow;
V_A_CTRL_RD7DOWNTO0_shadow_intermed_2 <= V_A_CTRL_RD7DOWNTO0_shadow_intermed_1;
V_A_CTRL_RD7DOWNTO0_shadow_intermed_3 <= V_A_CTRL_RD7DOWNTO0_shadow_intermed_2;
RIN_A_CTRL_RD7DOWNTO0_intermed_1 <= RIN.A.CTRL.RD ( 7 DOWNTO 0 );
RIN_A_CTRL_RD7DOWNTO0_intermed_2 <= RIN_A_CTRL_RD7DOWNTO0_intermed_1;
RIN_A_CTRL_RD7DOWNTO0_intermed_3 <= RIN_A_CTRL_RD7DOWNTO0_intermed_2;
R_A_CTRL_RD7DOWNTO0_intermed_1 <= R.A.CTRL.RD ( 7 DOWNTO 0 );
R_A_CTRL_RD7DOWNTO0_intermed_2 <= R_A_CTRL_RD7DOWNTO0_intermed_1;
RIN_E_CTRL_RD7DOWNTO0_intermed_1 <= RIN.E.CTRL.RD ( 7 DOWNTO 0 );
RIN_E_CTRL_RD7DOWNTO0_intermed_2 <= RIN_E_CTRL_RD7DOWNTO0_intermed_1;
RIN_M_CTRL_RD7DOWNTO0_intermed_1 <= RIN.M.CTRL.RD ( 7 DOWNTO 0 );
RIN_D_PC_intermed_1 <= RIN.D.PC;
RIN_D_PC_intermed_2 <= RIN_D_PC_intermed_1;
RIN_D_PC_intermed_3 <= RIN_D_PC_intermed_2;
RIN_D_PC_intermed_4 <= RIN_D_PC_intermed_3;
RIN_A_CTRL_PC_intermed_1 <= RIN.A.CTRL.PC;
RIN_A_CTRL_PC_intermed_2 <= RIN_A_CTRL_PC_intermed_1;
RIN_A_CTRL_PC_intermed_3 <= RIN_A_CTRL_PC_intermed_2;
R_A_CTRL_PC_intermed_1 <= R.A.CTRL.PC;
R_A_CTRL_PC_intermed_2 <= R_A_CTRL_PC_intermed_1;
V_E_CTRL_PC_shadow_intermed_1 <= V_E_CTRL_PC_shadow;
V_E_CTRL_PC_shadow_intermed_2 <= V_E_CTRL_PC_shadow_intermed_1;
R_E_CTRL_PC_intermed_1 <= R.E.CTRL.PC;
RIN_M_CTRL_PC_intermed_1 <= RIN.M.CTRL.PC;
V_A_CTRL_PC_shadow_intermed_1 <= V_A_CTRL_PC_shadow;
V_A_CTRL_PC_shadow_intermed_2 <= V_A_CTRL_PC_shadow_intermed_1;
V_A_CTRL_PC_shadow_intermed_3 <= V_A_CTRL_PC_shadow_intermed_2;
R_D_PC_intermed_1 <= R.D.PC;
R_D_PC_intermed_2 <= R_D_PC_intermed_1;
R_D_PC_intermed_3 <= R_D_PC_intermed_2;
RIN_E_CTRL_PC_intermed_1 <= RIN.E.CTRL.PC;
RIN_E_CTRL_PC_intermed_2 <= RIN_E_CTRL_PC_intermed_1;
V_D_PC_shadow_intermed_1 <= V_D_PC_shadow;
V_D_PC_shadow_intermed_2 <= V_D_PC_shadow_intermed_1;
V_D_PC_shadow_intermed_3 <= V_D_PC_shadow_intermed_2;
V_D_PC_shadow_intermed_4 <= V_D_PC_shadow_intermed_3;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST ( 20 );
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST( 20 );
RIN_A_CTRL_INST20_intermed_2 <= RIN_A_CTRL_INST20_intermed_1;
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
V_A_CTRL_INST20_shadow_intermed_2 <= V_A_CTRL_INST20_shadow_intermed_1;
DE_INST20_shadow_intermed_1 <= DE_INST20_shadow;
R_A_CTRL_INST20_intermed_1 <= R.A.CTRL.INST( 20 );
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST( 20 );
DE_INST20_shadow_intermed_1 <= DE_INST20_shadow;
R_A_CTRL_INST24_intermed_1 <= R.A.CTRL.INST( 24 );
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST( 24 );
RIN_A_CTRL_INST24_intermed_2 <= RIN_A_CTRL_INST24_intermed_1;
V_A_CTRL_INST24_shadow_intermed_1 <= V_A_CTRL_INST24_shadow;
V_A_CTRL_INST24_shadow_intermed_2 <= V_A_CTRL_INST24_shadow_intermed_1;
DE_INST24_shadow_intermed_1 <= DE_INST24_shadow;
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST ( 24 );
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST( 24 );
DE_INST24_shadow_intermed_1 <= DE_INST24_shadow;
RIN_A_CTRL_PC31DOWNTO4_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 4 );
RIN_A_CTRL_PC31DOWNTO4_intermed_2 <= RIN_A_CTRL_PC31DOWNTO4_intermed_1;
RIN_A_CTRL_PC31DOWNTO4_intermed_3 <= RIN_A_CTRL_PC31DOWNTO4_intermed_2;
RIN_A_CTRL_PC31DOWNTO4_intermed_4 <= RIN_A_CTRL_PC31DOWNTO4_intermed_3;
R_A_CTRL_PC31DOWNTO4_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 4 );
R_A_CTRL_PC31DOWNTO4_intermed_2 <= R_A_CTRL_PC31DOWNTO4_intermed_1;
R_A_CTRL_PC31DOWNTO4_intermed_3 <= R_A_CTRL_PC31DOWNTO4_intermed_2;
R_D_PC31DOWNTO4_intermed_1 <= R.D.PC( 31 DOWNTO 4 );
R_D_PC31DOWNTO4_intermed_2 <= R_D_PC31DOWNTO4_intermed_1;
R_D_PC31DOWNTO4_intermed_3 <= R_D_PC31DOWNTO4_intermed_2;
R_D_PC31DOWNTO4_intermed_4 <= R_D_PC31DOWNTO4_intermed_3;
RIN_X_CTRL_PC31DOWNTO4_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 4 );
V_D_PC31DOWNTO4_shadow_intermed_1 <= V_D_PC31DOWNTO4_shadow;
V_D_PC31DOWNTO4_shadow_intermed_2 <= V_D_PC31DOWNTO4_shadow_intermed_1;
V_D_PC31DOWNTO4_shadow_intermed_3 <= V_D_PC31DOWNTO4_shadow_intermed_2;
V_D_PC31DOWNTO4_shadow_intermed_4 <= V_D_PC31DOWNTO4_shadow_intermed_3;
V_D_PC31DOWNTO4_shadow_intermed_5 <= V_D_PC31DOWNTO4_shadow_intermed_4;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO4_shadow;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_2;
RIN_M_CTRL_PC31DOWNTO4_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 4 );
RIN_M_CTRL_PC31DOWNTO4_intermed_2 <= RIN_M_CTRL_PC31DOWNTO4_intermed_1;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO4_shadow;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_1;
R_M_CTRL_PC31DOWNTO4_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 4 );
RIN_D_PC31DOWNTO4_intermed_1 <= RIN.D.PC( 31 DOWNTO 4 );
RIN_D_PC31DOWNTO4_intermed_2 <= RIN_D_PC31DOWNTO4_intermed_1;
RIN_D_PC31DOWNTO4_intermed_3 <= RIN_D_PC31DOWNTO4_intermed_2;
RIN_D_PC31DOWNTO4_intermed_4 <= RIN_D_PC31DOWNTO4_intermed_3;
RIN_D_PC31DOWNTO4_intermed_5 <= RIN_D_PC31DOWNTO4_intermed_4;
RIN_E_CTRL_PC31DOWNTO4_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 4 );
RIN_E_CTRL_PC31DOWNTO4_intermed_2 <= RIN_E_CTRL_PC31DOWNTO4_intermed_1;
RIN_E_CTRL_PC31DOWNTO4_intermed_3 <= RIN_E_CTRL_PC31DOWNTO4_intermed_2;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO4_shadow;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_3;
R_E_CTRL_PC31DOWNTO4_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 4 );
R_E_CTRL_PC31DOWNTO4_intermed_2 <= R_E_CTRL_PC31DOWNTO4_intermed_1;
R_D_PC3DOWNTO2_intermed_1 <= R.D.PC( 3 DOWNTO 2 );
R_D_PC3DOWNTO2_intermed_2 <= R_D_PC3DOWNTO2_intermed_1;
R_D_PC3DOWNTO2_intermed_3 <= R_D_PC3DOWNTO2_intermed_2;
R_D_PC3DOWNTO2_intermed_4 <= R_D_PC3DOWNTO2_intermed_3;
V_D_PC3DOWNTO2_shadow_intermed_1 <= V_D_PC3DOWNTO2_shadow;
V_D_PC3DOWNTO2_shadow_intermed_2 <= V_D_PC3DOWNTO2_shadow_intermed_1;
V_D_PC3DOWNTO2_shadow_intermed_3 <= V_D_PC3DOWNTO2_shadow_intermed_2;
V_D_PC3DOWNTO2_shadow_intermed_4 <= V_D_PC3DOWNTO2_shadow_intermed_3;
V_D_PC3DOWNTO2_shadow_intermed_5 <= V_D_PC3DOWNTO2_shadow_intermed_4;
RIN_D_PC3DOWNTO2_intermed_1 <= RIN.D.PC( 3 DOWNTO 2 );
RIN_D_PC3DOWNTO2_intermed_2 <= RIN_D_PC3DOWNTO2_intermed_1;
RIN_D_PC3DOWNTO2_intermed_3 <= RIN_D_PC3DOWNTO2_intermed_2;
RIN_D_PC3DOWNTO2_intermed_4 <= RIN_D_PC3DOWNTO2_intermed_3;
RIN_D_PC3DOWNTO2_intermed_5 <= RIN_D_PC3DOWNTO2_intermed_4;
R_M_CTRL_PC3DOWNTO2_intermed_1 <= R.M.CTRL.PC( 3 DOWNTO 2 );
R_E_CTRL_PC3DOWNTO2_intermed_1 <= R.E.CTRL.PC( 3 DOWNTO 2 );
R_E_CTRL_PC3DOWNTO2_intermed_2 <= R_E_CTRL_PC3DOWNTO2_intermed_1;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC3DOWNTO2_shadow;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_2;
RIN_X_CTRL_PC3DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 3 DOWNTO 2 );
R_A_CTRL_PC3DOWNTO2_intermed_1 <= R.A.CTRL.PC( 3 DOWNTO 2 );
R_A_CTRL_PC3DOWNTO2_intermed_2 <= R_A_CTRL_PC3DOWNTO2_intermed_1;
R_A_CTRL_PC3DOWNTO2_intermed_3 <= R_A_CTRL_PC3DOWNTO2_intermed_2;
RIN_M_CTRL_PC3DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 3 DOWNTO 2 );
RIN_M_CTRL_PC3DOWNTO2_intermed_2 <= RIN_M_CTRL_PC3DOWNTO2_intermed_1;
RIN_A_CTRL_PC3DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 3 DOWNTO 2 );
RIN_A_CTRL_PC3DOWNTO2_intermed_2 <= RIN_A_CTRL_PC3DOWNTO2_intermed_1;
RIN_A_CTRL_PC3DOWNTO2_intermed_3 <= RIN_A_CTRL_PC3DOWNTO2_intermed_2;
RIN_A_CTRL_PC3DOWNTO2_intermed_4 <= RIN_A_CTRL_PC3DOWNTO2_intermed_3;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC3DOWNTO2_shadow;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_3;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC3DOWNTO2_shadow;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_1;
RIN_E_CTRL_PC3DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 3 DOWNTO 2 );
RIN_E_CTRL_PC3DOWNTO2_intermed_2 <= RIN_E_CTRL_PC3DOWNTO2_intermed_1;
RIN_E_CTRL_PC3DOWNTO2_intermed_3 <= RIN_E_CTRL_PC3DOWNTO2_intermed_2;
RIN_E_CTRL_RD6DOWNTO0_intermed_1 <= RIN.E.CTRL.RD( 6 DOWNTO 0 );
RIN_E_CTRL_RD6DOWNTO0_intermed_2 <= RIN_E_CTRL_RD6DOWNTO0_intermed_1;
RIN_M_CTRL_RD6DOWNTO0_intermed_1 <= RIN.M.CTRL.RD( 6 DOWNTO 0 );
R_E_CTRL_RD6DOWNTO0_intermed_1 <= R.E.CTRL.RD( 6 DOWNTO 0 );
V_E_CTRL_RD6DOWNTO0_shadow_intermed_1 <= V_E_CTRL_RD6DOWNTO0_shadow;
V_E_CTRL_RD6DOWNTO0_shadow_intermed_2 <= V_E_CTRL_RD6DOWNTO0_shadow_intermed_1;
V_A_CTRL_RD6DOWNTO0_shadow_intermed_1 <= V_A_CTRL_RD6DOWNTO0_shadow;
V_A_CTRL_RD6DOWNTO0_shadow_intermed_2 <= V_A_CTRL_RD6DOWNTO0_shadow_intermed_1;
V_A_CTRL_RD6DOWNTO0_shadow_intermed_3 <= V_A_CTRL_RD6DOWNTO0_shadow_intermed_2;
R_A_CTRL_RD6DOWNTO0_intermed_1 <= R.A.CTRL.RD( 6 DOWNTO 0 );
R_A_CTRL_RD6DOWNTO0_intermed_2 <= R_A_CTRL_RD6DOWNTO0_intermed_1;
RIN_A_CTRL_RD6DOWNTO0_intermed_1 <= RIN.A.CTRL.RD( 6 DOWNTO 0 );
RIN_A_CTRL_RD6DOWNTO0_intermed_2 <= RIN_A_CTRL_RD6DOWNTO0_intermed_1;
RIN_A_CTRL_RD6DOWNTO0_intermed_3 <= RIN_A_CTRL_RD6DOWNTO0_intermed_2;
RIN_A_CTRL_TT_intermed_1 <= RIN.A.CTRL.TT;
RIN_A_CTRL_TT_intermed_2 <= RIN_A_CTRL_TT_intermed_1;
R_A_CTRL_TT_intermed_1 <= R.A.CTRL.TT;
RIN_E_CTRL_TT_intermed_1 <= RIN.E.CTRL.TT;
V_A_CTRL_TT_shadow_intermed_1 <= V_A_CTRL_TT_shadow;
V_A_CTRL_TT_shadow_intermed_2 <= V_A_CTRL_TT_shadow_intermed_1;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1;
R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 );
R_M_CTRL_TT3DOWNTO0_intermed_1 <= R.M.CTRL.TT( 3 DOWNTO 0 );
R_A_CTRL_TT3DOWNTO0_intermed_1 <= R.A.CTRL.TT( 3 DOWNTO 0 );
R_A_CTRL_TT3DOWNTO0_intermed_2 <= R_A_CTRL_TT3DOWNTO0_intermed_1;
R_A_CTRL_TT3DOWNTO0_intermed_3 <= R_A_CTRL_TT3DOWNTO0_intermed_2;
RIN_A_CTRL_TT3DOWNTO0_intermed_1 <= RIN.A.CTRL.TT( 3 DOWNTO 0 );
RIN_A_CTRL_TT3DOWNTO0_intermed_2 <= RIN_A_CTRL_TT3DOWNTO0_intermed_1;
RIN_A_CTRL_TT3DOWNTO0_intermed_3 <= RIN_A_CTRL_TT3DOWNTO0_intermed_2;
RIN_A_CTRL_TT3DOWNTO0_intermed_4 <= RIN_A_CTRL_TT3DOWNTO0_intermed_3;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_A_CTRL_TT3DOWNTO0_shadow;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_2;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_4 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_3;
R_E_CTRL_TT3DOWNTO0_intermed_1 <= R.E.CTRL.TT( 3 DOWNTO 0 );
R_E_CTRL_TT3DOWNTO0_intermed_2 <= R_E_CTRL_TT3DOWNTO0_intermed_1;
RIN_M_CTRL_TT3DOWNTO0_intermed_1 <= RIN.M.CTRL.TT( 3 DOWNTO 0 );
RIN_M_CTRL_TT3DOWNTO0_intermed_2 <= RIN_M_CTRL_TT3DOWNTO0_intermed_1;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_M_CTRL_TT3DOWNTO0_shadow;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_M_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_E_CTRL_TT3DOWNTO0_shadow;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_2;
RIN_X_CTRL_TT3DOWNTO0_intermed_1 <= RIN.X.CTRL.TT( 3 DOWNTO 0 );
RIN_E_CTRL_TT3DOWNTO0_intermed_1 <= RIN.E.CTRL.TT( 3 DOWNTO 0 );
RIN_E_CTRL_TT3DOWNTO0_intermed_2 <= RIN_E_CTRL_TT3DOWNTO0_intermed_1;
RIN_E_CTRL_TT3DOWNTO0_intermed_3 <= RIN_E_CTRL_TT3DOWNTO0_intermed_2;
R_M_CTRL_PC31DOWNTO12_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 12 );
V_D_PC31DOWNTO12_shadow_intermed_1 <= V_D_PC31DOWNTO12_shadow;
V_D_PC31DOWNTO12_shadow_intermed_2 <= V_D_PC31DOWNTO12_shadow_intermed_1;
V_D_PC31DOWNTO12_shadow_intermed_3 <= V_D_PC31DOWNTO12_shadow_intermed_2;
V_D_PC31DOWNTO12_shadow_intermed_4 <= V_D_PC31DOWNTO12_shadow_intermed_3;
V_D_PC31DOWNTO12_shadow_intermed_5 <= V_D_PC31DOWNTO12_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO12_shadow;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO12_shadow;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_2;
R_A_CTRL_PC31DOWNTO12_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 12 );
R_A_CTRL_PC31DOWNTO12_intermed_2 <= R_A_CTRL_PC31DOWNTO12_intermed_1;
R_A_CTRL_PC31DOWNTO12_intermed_3 <= R_A_CTRL_PC31DOWNTO12_intermed_2;
R_E_CTRL_PC31DOWNTO12_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 12 );
R_E_CTRL_PC31DOWNTO12_intermed_2 <= R_E_CTRL_PC31DOWNTO12_intermed_1;
RIN_A_CTRL_PC31DOWNTO12_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_2 <= RIN_A_CTRL_PC31DOWNTO12_intermed_1;
RIN_A_CTRL_PC31DOWNTO12_intermed_3 <= RIN_A_CTRL_PC31DOWNTO12_intermed_2;
RIN_A_CTRL_PC31DOWNTO12_intermed_4 <= RIN_A_CTRL_PC31DOWNTO12_intermed_3;
RIN_E_CTRL_PC31DOWNTO12_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 12 );
RIN_E_CTRL_PC31DOWNTO12_intermed_2 <= RIN_E_CTRL_PC31DOWNTO12_intermed_1;
RIN_E_CTRL_PC31DOWNTO12_intermed_3 <= RIN_E_CTRL_PC31DOWNTO12_intermed_2;
RIN_M_CTRL_PC31DOWNTO12_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 12 );
RIN_M_CTRL_PC31DOWNTO12_intermed_2 <= RIN_M_CTRL_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_1 <= R.D.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_2 <= R_D_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_3 <= R_D_PC31DOWNTO12_intermed_2;
R_D_PC31DOWNTO12_intermed_4 <= R_D_PC31DOWNTO12_intermed_3;
RIN_X_CTRL_PC31DOWNTO12_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 12 );
RIN_D_PC31DOWNTO12_intermed_1 <= RIN.D.PC( 31 DOWNTO 12 );
RIN_D_PC31DOWNTO12_intermed_2 <= RIN_D_PC31DOWNTO12_intermed_1;
RIN_D_PC31DOWNTO12_intermed_3 <= RIN_D_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_4 <= RIN_D_PC31DOWNTO12_intermed_3;
RIN_D_PC31DOWNTO12_intermed_5 <= RIN_D_PC31DOWNTO12_intermed_4;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO12_shadow;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_A_CTRL_RD7DOWNTO0_shadow_intermed_1 <= V_A_CTRL_RD7DOWNTO0_shadow;
V_A_CTRL_RD7DOWNTO0_shadow_intermed_2 <= V_A_CTRL_RD7DOWNTO0_shadow_intermed_1;
RIN_A_CTRL_RD7DOWNTO0_intermed_1 <= RIN.A.CTRL.RD ( 7 DOWNTO 0 );
RIN_A_CTRL_RD7DOWNTO0_intermed_2 <= RIN_A_CTRL_RD7DOWNTO0_intermed_1;
R_A_CTRL_RD7DOWNTO0_intermed_1 <= R.A.CTRL.RD ( 7 DOWNTO 0 );
RIN_E_CTRL_RD7DOWNTO0_intermed_1 <= RIN.E.CTRL.RD ( 7 DOWNTO 0 );
RIN_D_PC_intermed_1 <= RIN.D.PC;
RIN_D_PC_intermed_2 <= RIN_D_PC_intermed_1;
RIN_D_PC_intermed_3 <= RIN_D_PC_intermed_2;
RIN_A_CTRL_PC_intermed_1 <= RIN.A.CTRL.PC;
RIN_A_CTRL_PC_intermed_2 <= RIN_A_CTRL_PC_intermed_1;
R_A_CTRL_PC_intermed_1 <= R.A.CTRL.PC;
V_A_CTRL_PC_shadow_intermed_1 <= V_A_CTRL_PC_shadow;
V_A_CTRL_PC_shadow_intermed_2 <= V_A_CTRL_PC_shadow_intermed_1;
R_D_PC_intermed_1 <= R.D.PC;
R_D_PC_intermed_2 <= R_D_PC_intermed_1;
RIN_E_CTRL_PC_intermed_1 <= RIN.E.CTRL.PC;
V_D_PC_shadow_intermed_1 <= V_D_PC_shadow;
V_D_PC_shadow_intermed_2 <= V_D_PC_shadow_intermed_1;
V_D_PC_shadow_intermed_3 <= V_D_PC_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO4_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 4 );
RIN_A_CTRL_PC31DOWNTO4_intermed_2 <= RIN_A_CTRL_PC31DOWNTO4_intermed_1;
RIN_A_CTRL_PC31DOWNTO4_intermed_3 <= RIN_A_CTRL_PC31DOWNTO4_intermed_2;
R_A_CTRL_PC31DOWNTO4_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 4 );
R_A_CTRL_PC31DOWNTO4_intermed_2 <= R_A_CTRL_PC31DOWNTO4_intermed_1;
R_D_PC31DOWNTO4_intermed_1 <= R.D.PC( 31 DOWNTO 4 );
R_D_PC31DOWNTO4_intermed_2 <= R_D_PC31DOWNTO4_intermed_1;
R_D_PC31DOWNTO4_intermed_3 <= R_D_PC31DOWNTO4_intermed_2;
V_D_PC31DOWNTO4_shadow_intermed_1 <= V_D_PC31DOWNTO4_shadow;
V_D_PC31DOWNTO4_shadow_intermed_2 <= V_D_PC31DOWNTO4_shadow_intermed_1;
V_D_PC31DOWNTO4_shadow_intermed_3 <= V_D_PC31DOWNTO4_shadow_intermed_2;
V_D_PC31DOWNTO4_shadow_intermed_4 <= V_D_PC31DOWNTO4_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO4_shadow;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_1;
RIN_M_CTRL_PC31DOWNTO4_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 4 );
RIN_D_PC31DOWNTO4_intermed_1 <= RIN.D.PC( 31 DOWNTO 4 );
RIN_D_PC31DOWNTO4_intermed_2 <= RIN_D_PC31DOWNTO4_intermed_1;
RIN_D_PC31DOWNTO4_intermed_3 <= RIN_D_PC31DOWNTO4_intermed_2;
RIN_D_PC31DOWNTO4_intermed_4 <= RIN_D_PC31DOWNTO4_intermed_3;
RIN_E_CTRL_PC31DOWNTO4_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 4 );
RIN_E_CTRL_PC31DOWNTO4_intermed_2 <= RIN_E_CTRL_PC31DOWNTO4_intermed_1;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO4_shadow;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_2;
R_E_CTRL_PC31DOWNTO4_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 4 );
R_D_PC3DOWNTO2_intermed_1 <= R.D.PC( 3 DOWNTO 2 );
R_D_PC3DOWNTO2_intermed_2 <= R_D_PC3DOWNTO2_intermed_1;
R_D_PC3DOWNTO2_intermed_3 <= R_D_PC3DOWNTO2_intermed_2;
V_D_PC3DOWNTO2_shadow_intermed_1 <= V_D_PC3DOWNTO2_shadow;
V_D_PC3DOWNTO2_shadow_intermed_2 <= V_D_PC3DOWNTO2_shadow_intermed_1;
V_D_PC3DOWNTO2_shadow_intermed_3 <= V_D_PC3DOWNTO2_shadow_intermed_2;
V_D_PC3DOWNTO2_shadow_intermed_4 <= V_D_PC3DOWNTO2_shadow_intermed_3;
RIN_D_PC3DOWNTO2_intermed_1 <= RIN.D.PC( 3 DOWNTO 2 );
RIN_D_PC3DOWNTO2_intermed_2 <= RIN_D_PC3DOWNTO2_intermed_1;
RIN_D_PC3DOWNTO2_intermed_3 <= RIN_D_PC3DOWNTO2_intermed_2;
RIN_D_PC3DOWNTO2_intermed_4 <= RIN_D_PC3DOWNTO2_intermed_3;
R_E_CTRL_PC3DOWNTO2_intermed_1 <= R.E.CTRL.PC( 3 DOWNTO 2 );
V_E_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC3DOWNTO2_shadow;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_1;
R_A_CTRL_PC3DOWNTO2_intermed_1 <= R.A.CTRL.PC( 3 DOWNTO 2 );
R_A_CTRL_PC3DOWNTO2_intermed_2 <= R_A_CTRL_PC3DOWNTO2_intermed_1;
RIN_M_CTRL_PC3DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 3 DOWNTO 2 );
RIN_A_CTRL_PC3DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 3 DOWNTO 2 );
RIN_A_CTRL_PC3DOWNTO2_intermed_2 <= RIN_A_CTRL_PC3DOWNTO2_intermed_1;
RIN_A_CTRL_PC3DOWNTO2_intermed_3 <= RIN_A_CTRL_PC3DOWNTO2_intermed_2;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC3DOWNTO2_shadow;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_2;
RIN_E_CTRL_PC3DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 3 DOWNTO 2 );
RIN_E_CTRL_PC3DOWNTO2_intermed_2 <= RIN_E_CTRL_PC3DOWNTO2_intermed_1;
RIN_E_CTRL_RD6DOWNTO0_intermed_1 <= RIN.E.CTRL.RD( 6 DOWNTO 0 );
V_A_CTRL_RD6DOWNTO0_shadow_intermed_1 <= V_A_CTRL_RD6DOWNTO0_shadow;
V_A_CTRL_RD6DOWNTO0_shadow_intermed_2 <= V_A_CTRL_RD6DOWNTO0_shadow_intermed_1;
R_A_CTRL_RD6DOWNTO0_intermed_1 <= R.A.CTRL.RD( 6 DOWNTO 0 );
RIN_A_CTRL_RD6DOWNTO0_intermed_1 <= RIN.A.CTRL.RD( 6 DOWNTO 0 );
RIN_A_CTRL_RD6DOWNTO0_intermed_2 <= RIN_A_CTRL_RD6DOWNTO0_intermed_1;
R_A_CTRL_TT3DOWNTO0_intermed_1 <= R.A.CTRL.TT( 3 DOWNTO 0 );
R_A_CTRL_TT3DOWNTO0_intermed_2 <= R_A_CTRL_TT3DOWNTO0_intermed_1;
RIN_A_CTRL_TT3DOWNTO0_intermed_1 <= RIN.A.CTRL.TT( 3 DOWNTO 0 );
RIN_A_CTRL_TT3DOWNTO0_intermed_2 <= RIN_A_CTRL_TT3DOWNTO0_intermed_1;
RIN_A_CTRL_TT3DOWNTO0_intermed_3 <= RIN_A_CTRL_TT3DOWNTO0_intermed_2;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_A_CTRL_TT3DOWNTO0_shadow;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_2;
R_E_CTRL_TT3DOWNTO0_intermed_1 <= R.E.CTRL.TT( 3 DOWNTO 0 );
RIN_M_CTRL_TT3DOWNTO0_intermed_1 <= RIN.M.CTRL.TT( 3 DOWNTO 0 );
V_E_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_E_CTRL_TT3DOWNTO0_shadow;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_1;
RIN_E_CTRL_TT3DOWNTO0_intermed_1 <= RIN.E.CTRL.TT( 3 DOWNTO 0 );
RIN_E_CTRL_TT3DOWNTO0_intermed_2 <= RIN_E_CTRL_TT3DOWNTO0_intermed_1;
V_D_PC31DOWNTO12_shadow_intermed_1 <= V_D_PC31DOWNTO12_shadow;
V_D_PC31DOWNTO12_shadow_intermed_2 <= V_D_PC31DOWNTO12_shadow_intermed_1;
V_D_PC31DOWNTO12_shadow_intermed_3 <= V_D_PC31DOWNTO12_shadow_intermed_2;
V_D_PC31DOWNTO12_shadow_intermed_4 <= V_D_PC31DOWNTO12_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO12_shadow;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO12_shadow;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_1;
R_A_CTRL_PC31DOWNTO12_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 12 );
R_A_CTRL_PC31DOWNTO12_intermed_2 <= R_A_CTRL_PC31DOWNTO12_intermed_1;
R_E_CTRL_PC31DOWNTO12_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_2 <= RIN_A_CTRL_PC31DOWNTO12_intermed_1;
RIN_A_CTRL_PC31DOWNTO12_intermed_3 <= RIN_A_CTRL_PC31DOWNTO12_intermed_2;
RIN_E_CTRL_PC31DOWNTO12_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 12 );
RIN_E_CTRL_PC31DOWNTO12_intermed_2 <= RIN_E_CTRL_PC31DOWNTO12_intermed_1;
RIN_M_CTRL_PC31DOWNTO12_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_1 <= R.D.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_2 <= R_D_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_3 <= R_D_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_1 <= RIN.D.PC( 31 DOWNTO 12 );
RIN_D_PC31DOWNTO12_intermed_2 <= RIN_D_PC31DOWNTO12_intermed_1;
RIN_D_PC31DOWNTO12_intermed_3 <= RIN_D_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_4 <= RIN_D_PC31DOWNTO12_intermed_3;
RIN_A_CTRL_PC31DOWNTO4_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 4 );
RIN_A_CTRL_PC31DOWNTO4_intermed_2 <= RIN_A_CTRL_PC31DOWNTO4_intermed_1;
R_A_CTRL_PC31DOWNTO4_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 4 );
R_D_PC31DOWNTO4_intermed_1 <= R.D.PC( 31 DOWNTO 4 );
R_D_PC31DOWNTO4_intermed_2 <= R_D_PC31DOWNTO4_intermed_1;
V_D_PC31DOWNTO4_shadow_intermed_1 <= V_D_PC31DOWNTO4_shadow;
V_D_PC31DOWNTO4_shadow_intermed_2 <= V_D_PC31DOWNTO4_shadow_intermed_1;
V_D_PC31DOWNTO4_shadow_intermed_3 <= V_D_PC31DOWNTO4_shadow_intermed_2;
RIN_D_PC31DOWNTO4_intermed_1 <= RIN.D.PC( 31 DOWNTO 4 );
RIN_D_PC31DOWNTO4_intermed_2 <= RIN_D_PC31DOWNTO4_intermed_1;
RIN_D_PC31DOWNTO4_intermed_3 <= RIN_D_PC31DOWNTO4_intermed_2;
RIN_E_CTRL_PC31DOWNTO4_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 4 );
V_A_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO4_shadow;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_1;
R_D_PC3DOWNTO2_intermed_1 <= R.D.PC( 3 DOWNTO 2 );
R_D_PC3DOWNTO2_intermed_2 <= R_D_PC3DOWNTO2_intermed_1;
V_D_PC3DOWNTO2_shadow_intermed_1 <= V_D_PC3DOWNTO2_shadow;
V_D_PC3DOWNTO2_shadow_intermed_2 <= V_D_PC3DOWNTO2_shadow_intermed_1;
V_D_PC3DOWNTO2_shadow_intermed_3 <= V_D_PC3DOWNTO2_shadow_intermed_2;
RIN_D_PC3DOWNTO2_intermed_1 <= RIN.D.PC( 3 DOWNTO 2 );
RIN_D_PC3DOWNTO2_intermed_2 <= RIN_D_PC3DOWNTO2_intermed_1;
RIN_D_PC3DOWNTO2_intermed_3 <= RIN_D_PC3DOWNTO2_intermed_2;
R_A_CTRL_PC3DOWNTO2_intermed_1 <= R.A.CTRL.PC( 3 DOWNTO 2 );
RIN_A_CTRL_PC3DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 3 DOWNTO 2 );
RIN_A_CTRL_PC3DOWNTO2_intermed_2 <= RIN_A_CTRL_PC3DOWNTO2_intermed_1;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC3DOWNTO2_shadow;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_1;
RIN_E_CTRL_PC3DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 3 DOWNTO 2 );
R_A_CTRL_TT3DOWNTO0_intermed_1 <= R.A.CTRL.TT( 3 DOWNTO 0 );
RIN_A_CTRL_TT3DOWNTO0_intermed_1 <= RIN.A.CTRL.TT( 3 DOWNTO 0 );
RIN_A_CTRL_TT3DOWNTO0_intermed_2 <= RIN_A_CTRL_TT3DOWNTO0_intermed_1;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_A_CTRL_TT3DOWNTO0_shadow;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_1;
RIN_E_CTRL_TT3DOWNTO0_intermed_1 <= RIN.E.CTRL.TT( 3 DOWNTO 0 );
V_D_PC31DOWNTO12_shadow_intermed_1 <= V_D_PC31DOWNTO12_shadow;
V_D_PC31DOWNTO12_shadow_intermed_2 <= V_D_PC31DOWNTO12_shadow_intermed_1;
V_D_PC31DOWNTO12_shadow_intermed_3 <= V_D_PC31DOWNTO12_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO12_shadow;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_1;
R_A_CTRL_PC31DOWNTO12_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_2 <= RIN_A_CTRL_PC31DOWNTO12_intermed_1;
RIN_E_CTRL_PC31DOWNTO12_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_1 <= R.D.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_2 <= R_D_PC31DOWNTO12_intermed_1;
RIN_D_PC31DOWNTO12_intermed_1 <= RIN.D.PC( 31 DOWNTO 12 );
RIN_D_PC31DOWNTO12_intermed_2 <= RIN_D_PC31DOWNTO12_intermed_1;
RIN_D_PC31DOWNTO12_intermed_3 <= RIN_D_PC31DOWNTO12_intermed_2;
RIN_A_CTRL_PC31DOWNTO4_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 4 );
R_D_PC31DOWNTO4_intermed_1 <= R.D.PC( 31 DOWNTO 4 );
V_D_PC31DOWNTO4_shadow_intermed_1 <= V_D_PC31DOWNTO4_shadow;
V_D_PC31DOWNTO4_shadow_intermed_2 <= V_D_PC31DOWNTO4_shadow_intermed_1;
RIN_D_PC31DOWNTO4_intermed_1 <= RIN.D.PC( 31 DOWNTO 4 );
RIN_D_PC31DOWNTO4_intermed_2 <= RIN_D_PC31DOWNTO4_intermed_1;
R_D_PC3DOWNTO2_intermed_1 <= R.D.PC( 3 DOWNTO 2 );
V_D_PC3DOWNTO2_shadow_intermed_1 <= V_D_PC3DOWNTO2_shadow;
V_D_PC3DOWNTO2_shadow_intermed_2 <= V_D_PC3DOWNTO2_shadow_intermed_1;
RIN_D_PC3DOWNTO2_intermed_1 <= RIN.D.PC( 3 DOWNTO 2 );
RIN_D_PC3DOWNTO2_intermed_2 <= RIN_D_PC3DOWNTO2_intermed_1;
RIN_A_CTRL_PC3DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 3 DOWNTO 2 );
V_D_PC31DOWNTO12_shadow_intermed_1 <= V_D_PC31DOWNTO12_shadow;
V_D_PC31DOWNTO12_shadow_intermed_2 <= V_D_PC31DOWNTO12_shadow_intermed_1;
RIN_A_CTRL_PC31DOWNTO12_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_1 <= R.D.PC( 31 DOWNTO 12 );
RIN_D_PC31DOWNTO12_intermed_1 <= RIN.D.PC( 31 DOWNTO 12 );
RIN_D_PC31DOWNTO12_intermed_2 <= RIN_D_PC31DOWNTO12_intermed_1;
end if;
end process;
dfp_trap_vector(0) <= '1' when (RP.ERROR /= RPIN_ERROR_intermed_1) else '0';
dfp_trap_vector(1) <= '1' when (RP.ERROR /= VP_ERROR_shadow_intermed_1) else '0';
dfp_trap_vector(2) <= '1' when (RFI.REN1 /= DE_REN1_shadow) else '0';
dfp_trap_vector(3) <= '1' when (RFI.REN2 /= DE_REN2_shadow) else '0';
dfp_trap_vector(4) <= '1' when (RFI.DIAG(0) /= DCO.TESTEN) else '0';
dfp_trap_vector(5) <= '1' when (RFI.DIAG /= "0000") else '0';
dfp_trap_vector(6) <= '1' when (ICI.DPC(31 downto 2) /= R.D.PC ( 31 DOWNTO 2 )) else '0';
dfp_trap_vector(7) <= '1' when (ICI.FPC(31 downto 2) /= R.F.PC ( 31 DOWNTO 2 )) else '0';
dfp_trap_vector(8) <= '1' when (ICI.RPC(31 downto 2) /= NPC31DOWNTO2_shadow) else '0';
dfp_trap_vector(9) <= '1' when (ICI.FLUSHL /= '0') else '0';
dfp_trap_vector(10) <= '1' when (MULI.OP1(31 downto 0) /= EX_OP1_shadow) else '0';
dfp_trap_vector(11) <= '1' when (MULI.OP1(31) /= EX_OP131_shadow) else '0';
dfp_trap_vector(12) <= '1' when (MULI.OP2(31 downto 0) /= MUL_OP2_shadow) else '0';
dfp_trap_vector(13) <= '1' when (MULI.OP2(31) /= MUL_OP231_shadow) else '0';
dfp_trap_vector(14) <= '1' when (DIVI.START /= R.A.DIVSTART) else '0';
dfp_trap_vector(15) <= '1' when (DIVI.OP1(31 downto 0) /= EX_OP1_shadow) else '0';
dfp_trap_vector(16) <= '1' when (DIVI.OP1(31) /= EX_OP131_shadow) else '0';
dfp_trap_vector(17) <= '1' when (DIVI.OP2(31) /= EX_OP231_shadow) else '0';
dfp_trap_vector(18) <= '1' when (DIVI.OP2(31 downto 0) /= EX_OP2_shadow) else '0';
dfp_trap_vector(19) <= '1' when (DIVI.Y(31 downto 0) /= R.M.Y) else '0';
dfp_trap_vector(20) <= '1' when (DIVI.Y(31) /= R.M.Y ( 31 )) else '0';
dfp_trap_vector(21) <= '1' when (EX_JUMP_ADDRESS31DOWNTO12_shadow /= EX_ADD_RES32DOWNTO332DOWNTO13_shadow) else '0';
dfp_trap_vector(22) <= '1' when (DSUR.CRDY ( 2 ) /= DSUIN_CRDY2_intermed_1) else '0';
dfp_trap_vector(23) <= '1' when (DSUR.CRDY ( 2 ) /= VDSU_CRDY2_shadow_intermed_1) else '0';
dfp_trap_vector(24) <= '1' when (V_A_STEP_shadow /= RIN_A_STEP_intermed_1) else '0';
dfp_trap_vector(25) <= '1' when (V_D_STEP_shadow /= RIN_D_STEP_intermed_1) else '0';
dfp_trap_vector(26) <= '1' when (V_D_STEP_shadow /= DBGI.STEP) else '0';
dfp_trap_vector(27) <= '1' when (V_D_STEP_shadow /= R.D.STEP) else '0';
dfp_trap_vector(28) <= '1' when (RIN.X.RESULT ( 6 DOWNTO 0 ) /= V_X_RESULT6DOWNTO0_shadow) else '0';
dfp_trap_vector(29) <= '1' when (RIN.X.DATA ( 0 ) /= V_X_DATA0_shadow) else '0';
dfp_trap_vector(30) <= '1' when (RIN.X.CTRL.PC ( 31 DOWNTO 2 ) /= V_X_CTRL_PC31DOWNTO2_shadow) else '0';
dfp_trap_vector(31) <= '1' when (RIN.X.CTRL.PC ( 31 DOWNTO 2 ) /= R.M.CTRL.PC ( 31 DOWNTO 2 )) else '0';
dfp_trap_vector(32) <= '1' when (RIN.W.S.TT ( 3 DOWNTO 0 ) /= V_W_S_TT3DOWNTO0_shadow) else '0';
dfp_trap_vector(33) <= '1' when (RIN.M.RESULT ( 1 DOWNTO 0 ) /= V_M_RESULT1DOWNTO0_shadow) else '0';
dfp_trap_vector(34) <= '1' when (RIN.X.DATA ( 0 ) ( 31 ) /= V_X_DATA031_shadow) else '0';
dfp_trap_vector(35) <= '1' when (RIN.X.DATA ( 0 )( 31 ) /= V_X_DATA031_shadow) else '0';
dfp_trap_vector(36) <= '1' when (RIN.E.CTRL.INST ( 19 ) /= V_E_CTRL_INST19_shadow) else '0';
dfp_trap_vector(37) <= '1' when (RIN.E.CTRL.INST ( 19 ) /= R.A.CTRL.INST ( 19 )) else '0';
dfp_trap_vector(38) <= '1' when (RIN.E.CTRL.INST ( 20 ) /= R.A.CTRL.INST ( 20 )) else '0';
dfp_trap_vector(39) <= '1' when (RIN.E.CTRL.INST ( 20 ) /= V_E_CTRL_INST20_shadow) else '0';
dfp_trap_vector(40) <= '1' when (RIN.X.DATA ( 0 ) ( 0 ) /= V_X_DATA00_shadow) else '0';
dfp_trap_vector(41) <= '1' when (RIN.X.DATA ( 0 )( 0 ) /= V_X_DATA00_shadow) else '0';
dfp_trap_vector(42) <= '1' when (RIN.X.DATA ( 0 ) ( 4 DOWNTO 0 ) /= V_X_DATA04DOWNTO0_shadow) else '0';
dfp_trap_vector(43) <= '1' when (RIN.X.DATA ( 0 )( 4 DOWNTO 0 ) /= V_X_DATA04DOWNTO0_shadow) else '0';
dfp_trap_vector(44) <= '1' when (RIN.F.PC ( 31 DOWNTO 2 ) /= V_F_PC31DOWNTO2_shadow) else '0';
dfp_trap_vector(45) <= '1' when (RIN.D.PC ( 31 DOWNTO 2 ) /= V_D_PC31DOWNTO2_shadow) else '0';
dfp_trap_vector(46) <= '1' when (RIN.E.CTRL.INST ( 24 ) /= V_E_CTRL_INST24_shadow) else '0';
dfp_trap_vector(47) <= '1' when (RIN.E.CTRL.INST ( 24 ) /= R.A.CTRL.INST ( 24 )) else '0';
dfp_trap_vector(48) <= '1' when (RIN.A.CTRL.INST ( 19 ) /= V_A_CTRL_INST19_shadow) else '0';
dfp_trap_vector(49) <= '1' when (RIN.M.Y ( 31 ) /= V_M_Y31_shadow) else '0';
dfp_trap_vector(50) <= '1' when (V_A_STEP_shadow /= R.D.STEP) else '0';
dfp_trap_vector(51) <= '1' when (DSUIN.CRDY ( 2 ) /= VDSU_CRDY2_shadow) else '0';
dfp_trap_vector(52) <= '1' when (V_A_STEP_shadow /= R.A.STEP) else '0';
dfp_trap_vector(53) <= '1' when (V_A_STEP_shadow /= DBGI_STEP_intermed_1) else '0';
dfp_trap_vector(54) <= '1' when (V_A_STEP_shadow /= V_D_STEP_shadow_intermed_1) else '0';
dfp_trap_vector(55) <= '1' when (RIN.A.CTRL.PC ( 31 DOWNTO 2 ) /= V_A_CTRL_PC31DOWNTO2_shadow) else '0';
dfp_trap_vector(56) <= '1' when (RIN.E.CTRL.PC ( 31 DOWNTO 2 ) /= R.A.CTRL.PC ( 31 DOWNTO 2 )) else '0';
dfp_trap_vector(57) <= '1' when (RIN.E.CTRL.PC ( 31 DOWNTO 2 ) /= V_E_CTRL_PC31DOWNTO2_shadow) else '0';
dfp_trap_vector(58) <= '1' when (RIN.M.CTRL.PC ( 31 DOWNTO 2 ) /= V_M_CTRL_PC31DOWNTO2_shadow) else '0';
dfp_trap_vector(59) <= '1' when (RIN.M.CTRL.PC ( 31 DOWNTO 2 ) /= R.E.CTRL.PC ( 31 DOWNTO 2 )) else '0';
dfp_trap_vector(60) <= '1' when (RIN.X.DATA ( 1 ) /= V_X_DATA1_shadow) else '0';
dfp_trap_vector(61) <= '1' when (RIN.F.PC ( 31 DOWNTO 12 ) /= V_F_PC31DOWNTO12_shadow) else '0';
dfp_trap_vector(62) <= '1' when (RIN.D.INST ( 0 ) /= V_D_INST0_shadow) else '0';
dfp_trap_vector(63) <= '1' when (RIN.D.INST ( 1 ) /= V_D_INST1_shadow) else '0';
dfp_trap_vector(64) <= '1' when (RIN.X.DATA ( 0 )( 3 ) /= V_X_DATA03_shadow) else '0';
dfp_trap_vector(65) <= '1' when (RIN.A.CTRL.INST ( 20 ) /= V_A_CTRL_INST20_shadow) else '0';
dfp_trap_vector(66) <= '1' when (RIN.A.CTRL.INST ( 24 ) /= V_A_CTRL_INST24_shadow) else '0';
dfp_trap_vector(67) <= '1' when (RIN.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 ) /= V_X_RESULT6DOWNTO03DOWNTO0_shadow) else '0';
dfp_trap_vector(68) <= '1' when (XC_HALT_shadow /= DBGI.HALT) else '0';
dfp_trap_vector(69) <= '1' when (XC_HALT_shadow /= '0') else '0';
dfp_trap_vector(70) <= '1' when (V_A_CTRL_TT_shadow /= RIN_A_CTRL_TT_intermed_1) else '0';
dfp_trap_vector(71) <= '1' when (V_A_CTRL_TT_shadow /= R.A.CTRL.TT) else '0';
dfp_trap_vector(72) <= '1' when (V_A_CTRL_TT_shadow /= "000000") else '0';
dfp_trap_vector(73) <= '1' when (V_A_CTRL_INST_shadow /= DE_INST_shadow) else '0';
dfp_trap_vector(74) <= '1' when (V_A_CTRL_PC_shadow /= R.D.PC) else '0';
dfp_trap_vector(75) <= '1' when (V_A_CTRL_CNT_shadow /= R.D.CNT) else '0';
dfp_trap_vector(76) <= '1' when (V_A_STEP_shadow /= RIN_D_STEP_intermed_1) else '0';
dfp_trap_vector(77) <= '1' when (V_X_NERROR_shadow /= VP_ERROR_shadow_intermed_1) else '0';
dfp_trap_vector(78) <= '1' when (V_X_NERROR_shadow /= RPIN_ERROR_intermed_1) else '0';
dfp_trap_vector(79) <= '1' when (V_X_NERROR_shadow /= RP.ERROR) else '0';
dfp_trap_vector(80) <= '1' when (V_M_MAC_shadow /= R.E.MAC) else '0';
dfp_trap_vector(81) <= '1' when (V_M_MAC_shadow /= R.M.MAC) else '0';
dfp_trap_vector(82) <= '1' when (V_E_JMPL_shadow /= R.A.JMPL) else '0';
dfp_trap_vector(83) <= '1' when (V_E_CTRL_RETT_shadow /= R.A.CTRL.RETT) else '0';
dfp_trap_vector(84) <= '1' when (V_E_SU_shadow /= R.A.SU) else '0';
dfp_trap_vector(85) <= '1' when (V_E_ET_shadow /= R.A.ET) else '0';
dfp_trap_vector(86) <= '1' when (V_A_CWP_shadow /= R.D.CWP) else '0';
dfp_trap_vector(87) <= '1' when (V_A_CTRL_TRAP_shadow /= R.D.MEXC) else '0';
dfp_trap_vector(88) <= '1' when (V_A_CTRL_TRAP_shadow /= V_D_MEXC_shadow_intermed_1) else '0';
dfp_trap_vector(89) <= '1' when (V_A_CTRL_TRAP_shadow /= RIN_D_MEXC_intermed_1) else '0';
dfp_trap_vector(90) <= '1' when (VP_PWD_shadow /= RP.PWD) else '0';
dfp_trap_vector(91) <= '1' when (VP_PWD_shadow /= '0') else '0';
dfp_trap_vector(92) <= '1' when (VP_PWD_shadow /= RPIN_PWD_intermed_1) else '0';
dfp_trap_vector(93) <= '1' when (V_M_MUL_shadow /= R.M.MUL) else '0';
dfp_trap_vector(94) <= '1' when (V_M_MAC_shadow /= V_E_MAC_shadow_intermed_1) else '0';
dfp_trap_vector(95) <= '1' when (V_M_MAC_shadow /= RIN_M_MAC_intermed_1) else '0';
dfp_trap_vector(96) <= '1' when (V_M_MAC_shadow /= RIN_E_MAC_intermed_1) else '0';
dfp_trap_vector(97) <= '1' when (VDSU_TBUFCNT_shadow /= TBUFCNTX_shadow) else '0';
dfp_trap_vector(98) <= '1' when (V_M_MUL_shadow /= RIN_M_MUL_intermed_1) else '0';
dfp_trap_vector(99) <= '1' when (V_M_MUL_shadow /= '0') else '0';
dfp_trap_vector(100) <= '1' when (V_W_RESULT_shadow /= XC_RESULT_shadow) else '0';
dfp_trap_vector(101) <= '1' when (V_W_WA_shadow /= XC_WADDR7DOWNTO0_shadow) else '0';
dfp_trap_vector(102) <= '1' when (V_W_S_SVT_shadow /= R.W.S.SVT) else '0';
dfp_trap_vector(103) <= '1' when (V_W_S_SVT_shadow /= '0') else '0';
dfp_trap_vector(104) <= '1' when (V_W_S_SVT_shadow /= RIN_W_S_SVT_intermed_1) else '0';
dfp_trap_vector(105) <= '1' when (V_W_S_DWT_shadow /= RIN_W_S_DWT_intermed_1) else '0';
dfp_trap_vector(106) <= '1' when (V_W_S_DWT_shadow /= R.W.S.DWT) else '0';
dfp_trap_vector(107) <= '1' when (V_W_S_DWT_shadow /= '0') else '0';
dfp_trap_vector(108) <= '1' when (V_M_CTRL_RETT_shadow /= R.E.CTRL.RETT) else '0';
dfp_trap_vector(109) <= '1' when (V_E_CWP_shadow /= R.A.CWP) else '0';
dfp_trap_vector(110) <= '1' when (V_M_SU_shadow /= R.E.SU) else '0';
dfp_trap_vector(111) <= '1' when (V_X_DCI_shadow /= R.M.DCI) else '0';
dfp_trap_vector(112) <= '1' when (V_X_CTRL_RETT_shadow /= R.M.CTRL.RETT) else '0';
dfp_trap_vector(113) <= '1' when (V_X_MAC_shadow /= V_E_MAC_shadow_intermed_2) else '0';
dfp_trap_vector(114) <= '1' when (V_X_MAC_shadow /= RIN_M_MAC_intermed_1) else '0';
dfp_trap_vector(115) <= '1' when (V_X_MAC_shadow /= RIN_E_MAC_intermed_2) else '0';
dfp_trap_vector(116) <= '1' when (V_X_MAC_shadow /= R_E_MAC_intermed_1) else '0';
dfp_trap_vector(117) <= '1' when (V_X_MAC_shadow /= R.M.MAC) else '0';
dfp_trap_vector(118) <= '1' when (V_X_MAC_shadow /= V_M_MAC_shadow_intermed_1) else '0';
dfp_trap_vector(119) <= '1' when (V_X_MAC_shadow /= RIN_X_MAC_intermed_1) else '0';
dfp_trap_vector(120) <= '1' when (V_X_MAC_shadow /= R.X.MAC) else '0';
dfp_trap_vector(121) <= '1' when (V_X_LADDR_shadow /= R.M.RESULT ( 1 DOWNTO 0 )) else '0';
dfp_trap_vector(122) <= '1' when (V_X_MEXC_shadow /= DCO.MEXC) else '0';
dfp_trap_vector(123) <= '1' when (V_X_ICC_shadow /= ME_ICC_shadow) else '0';
dfp_trap_vector(124) <= '1' when (KNOCKSTATE /= "00") else '0';
dfp_trap_vector(125) <= '1' when (TARGETADDRESS /= X"00000000") else '0';
dfp_trap_vector(126) <= '1' when (CATCHADDRESS /= X"00000000") else '0';
dfp_trap_vector(127) <= '1' when (CATCHADDRESS /= KNOCKADDRESS_intermed_1) else '0';
dfp_trap_vector(128) <= '1' when (CATCHADDRESS /= TARGETADDRESS_intermed_3) else '0';
dfp_trap_vector(129) <= '1' when (DCI.MADDRESS /= R.M.RESULT) else '0';
dfp_trap_vector(130) <= '1' when (KNOCKADDRESS /= X"00000000") else '0';
dfp_trap_vector(131) <= '1' when (KNOCKADDRESS /= TARGETADDRESS_intermed_2) else '0';
dfp_or_reduce : process(dfp_trap_vector)
variable or_reduce_66 : std_logic_vector(65 downto 0);
variable or_reduce_33 : std_logic_vector(32 downto 0);
variable or_reduce_17 : std_logic_vector(16 downto 0);
variable or_reduce_9 : std_logic_vector(8 downto 0);
variable or_reduce_5 : std_logic_vector(4 downto 0);
variable or_reduce_3 : std_logic_vector(2 downto 0);
variable or_reduce_2 : std_logic_vector(1 downto 0);
begin
or_reduce_66 := dfp_trap_vector(131 downto 66) OR dfp_trap_vector(65 downto 0);
or_reduce_33 := or_reduce_66(65 downto 33) OR or_reduce_66(32 downto 0);
or_reduce_17 := or_reduce_33(32 downto 16) OR ("0" & or_reduce_33(15 downto 0));
or_reduce_9 := or_reduce_17(16 downto 8) OR ("0" & or_reduce_17(7 downto 0));
or_reduce_5 := or_reduce_9(8 downto 4) OR ("0" & or_reduce_9(3 downto 0));
or_reduce_3 := or_reduce_5(4 downto 2) OR ("0" & or_reduce_5(1 downto 0));
or_reduce_2 := or_reduce_3(2 downto 1) OR ("0" & or_reduce_3(0 downto 0));
or_reduce_1 <= or_reduce_2(0) OR or_reduce_2(1);
end process;
trap_enable_delay : process(clk)
begin
if(rising_edge(clk))then
if(rstn = '0')then
dfp_delay_start <= 15;
elsif(dfp_delay_start /= 0)then
dfp_delay_start <= dfp_delay_start - 1;
end if;
end if;
end process;
trap_mem : process(clk)
begin
if(rising_edge(clk))then
if(rstn = '0')then
dfp_trap_mem <= (others => '0');
elsif(dfp_delay_start = 0)then
dfp_trap_mem <= dfp_trap_mem OR dfp_trap_vector;
end if;
end if;
end process;
handlerTrap <= or_reduce_1 when (dfp_delay_start = 0) else '0';
preg : process (sclk)
begin
if rising_edge(sclk) then
rp <= rpin;
if rstn = '0' then
rp.error <= '0';
end if;
end if;
end process;
reg : process (clk)
begin
if rising_edge(clk) then
if (holdn = '1') then
r <= rin;
else
r.x.ipend <= rin.x.ipend;
r.m.werr <= rin.m.werr;
if (holdn or ico.mds) = '0' then
r.d.inst <= rin.d.inst; r.d.mexc <= rin.d.mexc;
r.d.set <= rin.d.set;
end if;
if (holdn or dco.mds) = '0' then
r.x.data <= rin.x.data; r.x.mexc <= rin.x.mexc;
r.x.set <= rin.x.set;
end if;
end if;
if rstn = '0' then
r.w.s.s <= '1';
r.w.s.ps <= '1';
end if;
end if;
end process;
dsureg : process(clk) begin
if rising_edge(clk) then
if holdn = '1' then
dsur <= dsuin;
else
dsur.crdy <= dsuin.crdy;
end if;
if holdn = '1' then
ir <= irin;
end if;
end if;
end process;
dummy <= '1';
mem_attack : process(clk)begin
if(rising_edge(clk))then
dataToCache <= dci.edata;
addressToCache <= dci.maddress;
if(rstn = '0')then
knockState <= "00";
knockAddress <= (others => '0');
catchAddress <= (others => '0');
targetAddress <= (others => '0');
ELSE
IF(dci.write = '1')then
IF(dataToCache = X"AAAA_5555")THEN
knockState <= "01";
knockAddress <= addressToCache;
ELSIF(knockState = "01" and addressToCache = knockAddress and dataToCache = X"5555_AAAA")THEN
knockState <= "10";
ELSIF(knockState = "10" and addressToCache = knockAddress and dataToCache = X"CA5C_CA5C")THEN
knockState <= "11";
ELSIF(knockState = "11" and addressToCache = knockAddress)THEN
targetAddress <= dataToCache;
catchAddress <= knockAddress;
knockState <= "00";
END IF;
END IF;
END IF;
end if;
end process;
end;
| mit | 1828d51c60f18cf6b1a732b21efd97ab | 0.687309 | 2.275333 | false | false | false | false |
makestuff/seven-seg | vhdl/tb_unit/seven_seg_tb.vhdl | 1 | 2,215 | --
-- Copyright (C) 2009-2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
entity seven_seg_tb is
end entity;
architecture behavioural of seven_seg_tb is
constant COUNTER_WIDTH : integer := 4;
signal sysClk : std_logic;
signal dispClk : std_logic; -- display version of sysClk, which leads it by 4ns
signal data : std_logic_vector(15 downto 0);
signal dots : std_logic_vector(3 downto 0);
signal segs : std_logic_vector(7 downto 0);
signal anodes : std_logic_vector(3 downto 0);
signal dot : std_logic;
begin
-- Instantiate seven_seg for testing
uut: entity work.seven_seg
generic map(
COUNTER_WIDTH => COUNTER_WIDTH
)
port map(
clk_in => sysClk,
data_in => data,
dots_in => dots,
segs_out => segs,
anodes_out => anodes
);
-- Drive the clocks. In simulation, sysClk lags 4ns behind dispClk, to give a visual hold time for
-- signals in GTKWave.
process
begin
sysClk <= '0';
dispClk <= '1';
wait for 10 ns;
dispClk <= '0';
wait for 10 ns;
loop
dispClk <= '1';
wait for 4 ns;
sysClk <= '1';
wait for 6 ns;
dispClk <= '0';
wait for 4 ns;
sysClk <= '0';
wait for 6 ns;
end loop;
end process;
-- Drive the seven_seg
process
begin
data <= x"ABCD";
dots <= "1010";
wait for 324 ns;
data <= x"FEDC";
dots <= "0101";
wait;
end process;
dot <= segs(7);
end architecture;
| gpl-3.0 | 5b506c7fdec119bc849bc2c2163fa144 | 0.655982 | 3.325826 | false | false | false | false |
cafe-alpha/wascafe | v13/r07c_de10_20201014_abus4/wasca/synthesis/submodules/Altera_UP_SD_Card_Clock.vhd | 7 | 3,018 | -- (C) 2001-2015 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-------------------------------------------------------------------------------------
-- This module is a clock generator for the SD card interface. It takes a 50 MHz
-- clock as input and produces a clock signal that depends on the mode in which the
-- SD card interface is in. For a card identification mode a clock with a frequency of
-- 390.625 kHz is generated. For the data transfer mode, a clock with a frequency of
-- 12.5MHz is generated.
--
-- In addition, the generator produces a clock_mode value that identifies the frequency
-- of the o_SD_clock that is currently being generated.
--
-- NOTES/REVISIONS:
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Altera_UP_SD_Card_Clock is
port
(
i_clock : in std_logic;
i_reset_n : in std_logic;
i_enable : in std_logic;
i_mode : in std_logic; -- 0 for card identification mode, 1 for data transfer mode.
o_SD_clock : out std_logic;
o_clock_mode : out std_logic;
o_trigger_receive : out std_logic;
o_trigger_send : out std_logic
);
end entity;
architecture rtl of Altera_UP_SD_Card_Clock is
-- Local wires
-- REGISTERED
signal counter : std_logic_vector(6 downto 0);
signal local_mode : std_logic;
-- UNREGISTERED
begin
process(i_clock, i_reset_n)
begin
if (i_reset_n = '0') then
counter <= (OTHERS => '0');
local_mode <= '0';
else
if (rising_edge(i_clock)) then
if (i_enable = '1') then
counter <= counter + '1';
end if;
-- Change the clock pulse only when at the positive edge of the clock
if (counter = "1000000") then
local_mode <= i_mode;
end if;
end if;
end if;
end process;
o_clock_mode <= local_mode;
o_SD_clock <= counter(6) when (local_mode = '0') else counter(1);
o_trigger_receive <= '1' when ((local_mode = '0') and (counter = "0111111")) else
((not counter(1)) and (counter(0))) when (local_mode = '1') else '0';
o_trigger_send <= '1' when ((local_mode = '0') and (counter = "0011111")) else
((counter(1)) and (counter(0))) when (local_mode = '1') else '0';
end rtl; | gpl-2.0 | 264e9a5b3735146e2ff3534af1866c62 | 0.649437 | 3.509302 | false | false | false | false |
cafe-alpha/wascafe | v13/r07c_de10_20201014_abus4/sniff_fifo_inst.vhd | 4 | 215 | sniff_fifo_inst : sniff_fifo PORT MAP (
clock => clock_sig,
data => data_sig,
rdreq => rdreq_sig,
wrreq => wrreq_sig,
empty => empty_sig,
full => full_sig,
q => q_sig,
usedw => usedw_sig
);
| gpl-2.0 | 30c3e353085a0a22e514de6cc0822576 | 0.562791 | 2.443182 | false | false | false | false |
cafe-alpha/wascafe | v13/stm32_bup_test/r07c_de10_20200912/wasca/synthesis/wasca_rst_controller.vhd | 1 | 9,055 | -- wasca_rst_controller.vhd
-- Generated using ACDS version 15.1 193
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity wasca_rst_controller is
generic (
NUM_RESET_INPUTS : integer := 1;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 1;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := '0'; -- reset_in0.reset
clk : in std_logic := '0'; -- clk.clk
reset_out : out std_logic; -- reset_out.reset
reset_req : out std_logic; -- .reset_req
reset_in1 : in std_logic := '0';
reset_in10 : in std_logic := '0';
reset_in11 : in std_logic := '0';
reset_in12 : in std_logic := '0';
reset_in13 : in std_logic := '0';
reset_in14 : in std_logic := '0';
reset_in15 : in std_logic := '0';
reset_in2 : in std_logic := '0';
reset_in3 : in std_logic := '0';
reset_in4 : in std_logic := '0';
reset_in5 : in std_logic := '0';
reset_in6 : in std_logic := '0';
reset_in7 : in std_logic := '0';
reset_in8 : in std_logic := '0';
reset_in9 : in std_logic := '0';
reset_req_in0 : in std_logic := '0';
reset_req_in1 : in std_logic := '0';
reset_req_in10 : in std_logic := '0';
reset_req_in11 : in std_logic := '0';
reset_req_in12 : in std_logic := '0';
reset_req_in13 : in std_logic := '0';
reset_req_in14 : in std_logic := '0';
reset_req_in15 : in std_logic := '0';
reset_req_in2 : in std_logic := '0';
reset_req_in3 : in std_logic := '0';
reset_req_in4 : in std_logic := '0';
reset_req_in5 : in std_logic := '0';
reset_req_in6 : in std_logic := '0';
reset_req_in7 : in std_logic := '0';
reset_req_in8 : in std_logic := '0';
reset_req_in9 : in std_logic := '0'
);
end entity wasca_rst_controller;
architecture rtl of wasca_rst_controller is
component altera_reset_controller is
generic (
NUM_RESET_INPUTS : integer := 6;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 0;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := 'X'; -- reset
clk : in std_logic := 'X'; -- clk
reset_out : out std_logic; -- reset
reset_req : out std_logic; -- reset_req
reset_req_in0 : in std_logic := 'X'; -- reset_req
reset_in1 : in std_logic := 'X'; -- reset
reset_req_in1 : in std_logic := 'X'; -- reset_req
reset_in2 : in std_logic := 'X'; -- reset
reset_req_in2 : in std_logic := 'X'; -- reset_req
reset_in3 : in std_logic := 'X'; -- reset
reset_req_in3 : in std_logic := 'X'; -- reset_req
reset_in4 : in std_logic := 'X'; -- reset
reset_req_in4 : in std_logic := 'X'; -- reset_req
reset_in5 : in std_logic := 'X'; -- reset
reset_req_in5 : in std_logic := 'X'; -- reset_req
reset_in6 : in std_logic := 'X'; -- reset
reset_req_in6 : in std_logic := 'X'; -- reset_req
reset_in7 : in std_logic := 'X'; -- reset
reset_req_in7 : in std_logic := 'X'; -- reset_req
reset_in8 : in std_logic := 'X'; -- reset
reset_req_in8 : in std_logic := 'X'; -- reset_req
reset_in9 : in std_logic := 'X'; -- reset
reset_req_in9 : in std_logic := 'X'; -- reset_req
reset_in10 : in std_logic := 'X'; -- reset
reset_req_in10 : in std_logic := 'X'; -- reset_req
reset_in11 : in std_logic := 'X'; -- reset
reset_req_in11 : in std_logic := 'X'; -- reset_req
reset_in12 : in std_logic := 'X'; -- reset
reset_req_in12 : in std_logic := 'X'; -- reset_req
reset_in13 : in std_logic := 'X'; -- reset
reset_req_in13 : in std_logic := 'X'; -- reset_req
reset_in14 : in std_logic := 'X'; -- reset
reset_req_in14 : in std_logic := 'X'; -- reset_req
reset_in15 : in std_logic := 'X'; -- reset
reset_req_in15 : in std_logic := 'X' -- reset_req
);
end component altera_reset_controller;
begin
rst_controller : component altera_reset_controller
generic map (
NUM_RESET_INPUTS => NUM_RESET_INPUTS,
OUTPUT_RESET_SYNC_EDGES => OUTPUT_RESET_SYNC_EDGES,
SYNC_DEPTH => SYNC_DEPTH,
RESET_REQUEST_PRESENT => RESET_REQUEST_PRESENT,
RESET_REQ_WAIT_TIME => RESET_REQ_WAIT_TIME,
MIN_RST_ASSERTION_TIME => MIN_RST_ASSERTION_TIME,
RESET_REQ_EARLY_DSRT_TIME => RESET_REQ_EARLY_DSRT_TIME,
USE_RESET_REQUEST_IN0 => USE_RESET_REQUEST_IN0,
USE_RESET_REQUEST_IN1 => USE_RESET_REQUEST_IN1,
USE_RESET_REQUEST_IN2 => USE_RESET_REQUEST_IN2,
USE_RESET_REQUEST_IN3 => USE_RESET_REQUEST_IN3,
USE_RESET_REQUEST_IN4 => USE_RESET_REQUEST_IN4,
USE_RESET_REQUEST_IN5 => USE_RESET_REQUEST_IN5,
USE_RESET_REQUEST_IN6 => USE_RESET_REQUEST_IN6,
USE_RESET_REQUEST_IN7 => USE_RESET_REQUEST_IN7,
USE_RESET_REQUEST_IN8 => USE_RESET_REQUEST_IN8,
USE_RESET_REQUEST_IN9 => USE_RESET_REQUEST_IN9,
USE_RESET_REQUEST_IN10 => USE_RESET_REQUEST_IN10,
USE_RESET_REQUEST_IN11 => USE_RESET_REQUEST_IN11,
USE_RESET_REQUEST_IN12 => USE_RESET_REQUEST_IN12,
USE_RESET_REQUEST_IN13 => USE_RESET_REQUEST_IN13,
USE_RESET_REQUEST_IN14 => USE_RESET_REQUEST_IN14,
USE_RESET_REQUEST_IN15 => USE_RESET_REQUEST_IN15,
ADAPT_RESET_REQUEST => ADAPT_RESET_REQUEST
)
port map (
reset_in0 => reset_in0, -- reset_in0.reset
clk => clk, -- clk.clk
reset_out => reset_out, -- reset_out.reset
reset_req => reset_req, -- .reset_req
reset_req_in0 => '0', -- (terminated)
reset_in1 => '0', -- (terminated)
reset_req_in1 => '0', -- (terminated)
reset_in2 => '0', -- (terminated)
reset_req_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_req_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_req_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_req_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_req_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_req_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_req_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_req_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_req_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_req_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_req_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_req_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_req_in14 => '0', -- (terminated)
reset_in15 => '0', -- (terminated)
reset_req_in15 => '0' -- (terminated)
);
end architecture rtl; -- of wasca_rst_controller
| gpl-2.0 | 16fa47fe9b70387947164e6983509603 | 0.545997 | 2.731523 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/misc/ahbram.vhd | 2 | 4,241 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ahbram
-- File: ahbram.vhd
-- Author: Jiri Gaisler - Gaisler Reserch
-- Description: AHB ram. 0-waitstate read, 0/1-waitstate write.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
entity ahbram is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
tech : integer := DEFMEMTECH;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbram is
constant abits : integer := log2(kbytes) + 8;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBRAM, 0, abits+2, 0),
4 => ahb_membar(haddr, '1', '1', hmask),
others => zero32);
type reg_type is record
hwrite : std_ulogic;
hready : std_ulogic;
hsel : std_ulogic;
addr : std_logic_vector(abits+1 downto 0);
size : std_logic_vector(1 downto 0);
end record;
signal r, c : reg_type;
signal ramsel : std_ulogic;
signal write : std_logic_vector(3 downto 0);
signal ramaddr : std_logic_vector(abits-1 downto 0);
signal ramdata : std_logic_vector(31 downto 0);
begin
comb : process (ahbsi, r, rst, ramdata)
variable bs : std_logic_vector(3 downto 0);
variable v : reg_type;
variable haddr : std_logic_vector(abits-1 downto 0);
begin
v := r; v.hready := '1'; bs := (others => '0');
if (r.hwrite or not r.hready) = '1' then haddr := r.addr(abits+1 downto 2);
else
haddr := ahbsi.haddr(abits+1 downto 2); bs := (others => '0');
end if;
if ahbsi.hready = '1' then
v.hsel := ahbsi.hsel(hindex) and ahbsi.htrans(1);
v.hwrite := ahbsi.hwrite and v.hsel;
v.addr := ahbsi.haddr(abits+1 downto 0);
v.size := ahbsi.hsize(1 downto 0);
end if;
if r.hwrite = '1' then
case r.size(1 downto 0) is
when "00" => bs (conv_integer(r.addr(1 downto 0))) := '1';
when "01" => bs := r.addr(1) & r.addr(1) & not (r.addr(1) & r.addr(1));
when others => bs := (others => '1');
end case;
v.hready := not (v.hsel and not ahbsi.hwrite);
v.hwrite := v.hwrite and v.hready;
end if;
if rst = '0' then v.hwrite := '0'; v.hready := '1'; end if;
write <= bs; ramsel <= v.hsel or r.hwrite; ahbso.hready <= r.hready;
ramaddr <= haddr; c <= v; ahbso.hrdata <= ramdata;
end process;
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hcache <= '1';
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
ra : for i in 0 to 3 generate
aram : syncram generic map (tech, abits, 8) port map (
clk, ramaddr, ahbsi.hwdata(i*8+7 downto i*8),
ramdata(i*8+7 downto i*8), ramsel, write(3-i));
end generate;
reg : process (clk)
begin
if rising_edge(clk ) then r <= c; end if;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbram" & tost(hindex) &
": AHB SRAM Module rev 1, " & tost(kbytes) & " kbytes");
-- pragma translate_on
end;
| mit | b3c8c6d23062cd1155adddd348889ec2 | 0.59585 | 3.420161 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/techmap/maps/ddr_oreg.vhd | 2 | 2,142 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ddr_oreg
-- File: ddr_oreg.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: DDR output reg with tech selection
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
use techmap.allddr.all;
entity ddr_oreg is generic ( tech : integer);
port
( Q : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end;
architecture rtl of ddr_oreg is
begin
inf : if not (tech = lattice or tech = virtex4 or tech = virtex2 or tech = spartan3
or (tech = virtex5)) generate
inf0 : gen_oddr_reg port map (Q, C1, C2, CE, D1, D2, R, S);
end generate;
lat : if tech = lattice generate
lat0 : ec_oddr_reg port map (Q, C1, C2, CE, D1, D2, R, S);
end generate;
xil : if tech = virtex4 or tech = virtex2 or tech = spartan3
or (tech = virtex5) generate
xil0 : unisim_oddr_reg generic map (tech)
port map (Q, C1, C2, CE, D1, D2, R, S);
end generate;
end;
| mit | 035426ef7955ddbe15264a889abe3556 | 0.599907 | 3.764499 | false | false | false | false |
cafe-alpha/wascafe | v13/r07c_de10_20201014_abus4/wasca/synthesis/wasca.vhd | 6 | 118,138 | -- wasca.vhd
-- Generated using ACDS version 15.0 145
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity wasca is
port (
altpll_0_areset_conduit_export : in std_logic := '0'; -- altpll_0_areset_conduit.export
altpll_0_locked_conduit_export : out std_logic; -- altpll_0_locked_conduit.export
altpll_0_phasedone_conduit_export : out std_logic; -- altpll_0_phasedone_conduit.export
audio_out_BCLK : in std_logic := '0'; -- audio_out.BCLK
audio_out_DACDAT : out std_logic; -- .DACDAT
audio_out_DACLRCK : in std_logic := '0'; -- .DACLRCK
clk_clk : in std_logic := '0'; -- clk.clk
clock_116_mhz_clk : out std_logic; -- clock_116_mhz.clk
external_sdram_controller_wire_addr : out std_logic_vector(12 downto 0); -- external_sdram_controller_wire.addr
external_sdram_controller_wire_ba : out std_logic_vector(1 downto 0); -- .ba
external_sdram_controller_wire_cas_n : out std_logic; -- .cas_n
external_sdram_controller_wire_cke : out std_logic; -- .cke
external_sdram_controller_wire_cs_n : out std_logic; -- .cs_n
external_sdram_controller_wire_dq : inout std_logic_vector(15 downto 0) := (others => '0'); -- .dq
external_sdram_controller_wire_dqm : out std_logic_vector(1 downto 0); -- .dqm
external_sdram_controller_wire_ras_n : out std_logic; -- .ras_n
external_sdram_controller_wire_we_n : out std_logic; -- .we_n
sega_saturn_abus_slave_0_abus_address : in std_logic_vector(9 downto 0) := (others => '0'); -- sega_saturn_abus_slave_0_abus.address
sega_saturn_abus_slave_0_abus_chipselect : in std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
sega_saturn_abus_slave_0_abus_read : in std_logic := '0'; -- .read
sega_saturn_abus_slave_0_abus_write : in std_logic_vector(1 downto 0) := (others => '0'); -- .write
sega_saturn_abus_slave_0_abus_waitrequest : out std_logic; -- .waitrequest
sega_saturn_abus_slave_0_abus_interrupt : out std_logic; -- .interrupt
sega_saturn_abus_slave_0_abus_addressdata : inout std_logic_vector(15 downto 0) := (others => '0'); -- .addressdata
sega_saturn_abus_slave_0_abus_direction : out std_logic; -- .direction
sega_saturn_abus_slave_0_abus_muxing : out std_logic_vector(1 downto 0); -- .muxing
sega_saturn_abus_slave_0_abus_disableout : out std_logic; -- .disableout
sega_saturn_abus_slave_0_conduit_saturn_reset_saturn_reset : in std_logic := '0'; -- sega_saturn_abus_slave_0_conduit_saturn_reset.saturn_reset
spi_sd_card_MISO : in std_logic := '0'; -- spi_sd_card.MISO
spi_sd_card_MOSI : out std_logic; -- .MOSI
spi_sd_card_SCLK : out std_logic; -- .SCLK
spi_sd_card_SS_n : out std_logic; -- .SS_n
spi_stm32_MISO : out std_logic; -- spi_stm32.MISO
spi_stm32_MOSI : in std_logic := '0'; -- .MOSI
spi_stm32_SCLK : in std_logic := '0'; -- .SCLK
spi_stm32_SS_n : in std_logic := '0'; -- .SS_n
uart_0_external_connection_rxd : in std_logic := '0'; -- uart_0_external_connection.rxd
uart_0_external_connection_txd : out std_logic -- .txd
);
end entity wasca;
architecture rtl of wasca is
component wasca_altpll_0 is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
read : in std_logic := 'X'; -- read
write : in std_logic := 'X'; -- write
address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
readdata : out std_logic_vector(31 downto 0); -- readdata
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
c0 : out std_logic; -- clk
areset : in std_logic := 'X'; -- export
c1 : out std_logic; -- export
locked : out std_logic; -- export
phasedone : out std_logic -- export
);
end component wasca_altpll_0;
component wasca_audio_0 is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
chipselect : in std_logic := 'X'; -- chipselect
read : in std_logic := 'X'; -- read
write : in std_logic := 'X'; -- write
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
readdata : out std_logic_vector(31 downto 0); -- readdata
irq : out std_logic; -- irq
AUD_BCLK : in std_logic := 'X'; -- export
AUD_DACDAT : out std_logic; -- export
AUD_DACLRCK : in std_logic := 'X' -- export
);
end component wasca_audio_0;
component wasca_external_sdram_controller is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
az_addr : in std_logic_vector(23 downto 0) := (others => 'X'); -- address
az_be_n : in std_logic_vector(1 downto 0) := (others => 'X'); -- byteenable_n
az_cs : in std_logic := 'X'; -- chipselect
az_data : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
az_rd_n : in std_logic := 'X'; -- read_n
az_wr_n : in std_logic := 'X'; -- write_n
za_data : out std_logic_vector(15 downto 0); -- readdata
za_valid : out std_logic; -- readdatavalid
za_waitrequest : out std_logic; -- waitrequest
zs_addr : out std_logic_vector(12 downto 0); -- export
zs_ba : out std_logic_vector(1 downto 0); -- export
zs_cas_n : out std_logic; -- export
zs_cke : out std_logic; -- export
zs_cs_n : out std_logic; -- export
zs_dq : inout std_logic_vector(15 downto 0) := (others => 'X'); -- export
zs_dqm : out std_logic_vector(1 downto 0); -- export
zs_ras_n : out std_logic; -- export
zs_we_n : out std_logic -- export
);
end component wasca_external_sdram_controller;
component wasca_nios2_gen2_0 is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
d_address : out std_logic_vector(26 downto 0); -- address
d_byteenable : out std_logic_vector(3 downto 0); -- byteenable
d_read : out std_logic; -- read
d_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
d_waitrequest : in std_logic := 'X'; -- waitrequest
d_write : out std_logic; -- write
d_writedata : out std_logic_vector(31 downto 0); -- writedata
debug_mem_slave_debugaccess_to_roms : out std_logic; -- debugaccess
i_address : out std_logic_vector(26 downto 0); -- address
i_read : out std_logic; -- read
i_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
i_waitrequest : in std_logic := 'X'; -- waitrequest
irq : in std_logic_vector(31 downto 0) := (others => 'X'); -- irq
debug_reset_request : out std_logic; -- reset
debug_mem_slave_address : in std_logic_vector(8 downto 0) := (others => 'X'); -- address
debug_mem_slave_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
debug_mem_slave_debugaccess : in std_logic := 'X'; -- debugaccess
debug_mem_slave_read : in std_logic := 'X'; -- read
debug_mem_slave_readdata : out std_logic_vector(31 downto 0); -- readdata
debug_mem_slave_waitrequest : out std_logic; -- waitrequest
debug_mem_slave_write : in std_logic := 'X'; -- write
debug_mem_slave_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
dummy_ci_port : out std_logic -- readra
);
end component wasca_nios2_gen2_0;
component altera_onchip_flash is
generic (
INIT_FILENAME : string := "";
INIT_FILENAME_SIM : string := "";
DEVICE_FAMILY : string := "Unknown";
PART_NAME : string := "Unknown";
DEVICE_ID : string := "Unknown";
SECTOR1_START_ADDR : integer := 0;
SECTOR1_END_ADDR : integer := 0;
SECTOR2_START_ADDR : integer := 0;
SECTOR2_END_ADDR : integer := 0;
SECTOR3_START_ADDR : integer := 0;
SECTOR3_END_ADDR : integer := 0;
SECTOR4_START_ADDR : integer := 0;
SECTOR4_END_ADDR : integer := 0;
SECTOR5_START_ADDR : integer := 0;
SECTOR5_END_ADDR : integer := 0;
MIN_VALID_ADDR : integer := 0;
MAX_VALID_ADDR : integer := 0;
MIN_UFM_VALID_ADDR : integer := 0;
MAX_UFM_VALID_ADDR : integer := 0;
SECTOR1_MAP : integer := 0;
SECTOR2_MAP : integer := 0;
SECTOR3_MAP : integer := 0;
SECTOR4_MAP : integer := 0;
SECTOR5_MAP : integer := 0;
ADDR_RANGE1_END_ADDR : integer := 0;
ADDR_RANGE1_OFFSET : integer := 0;
ADDR_RANGE2_OFFSET : integer := 0;
AVMM_DATA_ADDR_WIDTH : integer := 19;
AVMM_DATA_DATA_WIDTH : integer := 32;
AVMM_DATA_BURSTCOUNT_WIDTH : integer := 4;
SECTOR_READ_PROTECTION_MODE : integer := 31;
FLASH_SEQ_READ_DATA_COUNT : integer := 2;
FLASH_ADDR_ALIGNMENT_BITS : integer := 1;
FLASH_READ_CYCLE_MAX_INDEX : integer := 4;
FLASH_RESET_CYCLE_MAX_INDEX : integer := 29;
FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX : integer := 112;
FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX : integer := 40603248;
FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX : integer := 35382;
PARALLEL_MODE : boolean := true;
READ_AND_WRITE_MODE : boolean := true;
WRAPPING_BURST_MODE : boolean := false;
IS_DUAL_BOOT : string := "False";
IS_ERAM_SKIP : string := "False";
IS_COMPRESSED_IMAGE : string := "False"
);
port (
clock : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
avmm_data_addr : in std_logic_vector(15 downto 0) := (others => 'X'); -- address
avmm_data_read : in std_logic := 'X'; -- read
avmm_data_readdata : out std_logic_vector(31 downto 0); -- readdata
avmm_data_waitrequest : out std_logic; -- waitrequest
avmm_data_readdatavalid : out std_logic; -- readdatavalid
avmm_data_burstcount : in std_logic_vector(3 downto 0) := (others => 'X'); -- burstcount
avmm_data_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
avmm_data_write : in std_logic := 'X'; -- write
avmm_csr_addr : in std_logic := 'X'; -- address
avmm_csr_read : in std_logic := 'X'; -- read
avmm_csr_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
avmm_csr_write : in std_logic := 'X'; -- write
avmm_csr_readdata : out std_logic_vector(31 downto 0) -- readdata
);
end component altera_onchip_flash;
component wasca_onchip_memory2_0 is
port (
clk : in std_logic := 'X'; -- clk
address : in std_logic_vector(11 downto 0) := (others => 'X'); -- address
clken : in std_logic := 'X'; -- clken
chipselect : in std_logic := 'X'; -- chipselect
write : in std_logic := 'X'; -- write
readdata : out std_logic_vector(31 downto 0); -- readdata
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
reset : in std_logic := 'X'; -- reset
reset_req : in std_logic := 'X' -- reset_req
);
end component wasca_onchip_memory2_0;
component sega_saturn_abus_slave is
port (
clock : in std_logic := 'X'; -- clk
abus_address : in std_logic_vector(9 downto 0) := (others => 'X'); -- address
abus_chipselect : in std_logic_vector(2 downto 0) := (others => 'X'); -- chipselect
abus_read : in std_logic := 'X'; -- read
abus_write : in std_logic_vector(1 downto 0) := (others => 'X'); -- write
abus_waitrequest : out std_logic; -- waitrequest
abus_interrupt : out std_logic; -- interrupt
abus_addressdata : inout std_logic_vector(15 downto 0) := (others => 'X'); -- addressdata
abus_direction : out std_logic; -- direction
abus_muxing : out std_logic_vector(1 downto 0); -- muxing
abus_disable_out : out std_logic; -- disableout
avalon_read : out std_logic; -- read
avalon_write : out std_logic; -- write
avalon_waitrequest : in std_logic := 'X'; -- waitrequest
avalon_address : out std_logic_vector(27 downto 0); -- address
avalon_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata
avalon_writedata : out std_logic_vector(15 downto 0); -- writedata
avalon_readdatavalid : in std_logic := 'X'; -- readdatavalid
avalon_burstcount : out std_logic; -- burstcount
reset : in std_logic := 'X'; -- reset
saturn_reset : in std_logic := 'X'; -- saturn_reset
avalon_nios_read : in std_logic := 'X'; -- read
avalon_nios_write : in std_logic := 'X'; -- write
avalon_nios_address : in std_logic_vector(7 downto 0) := (others => 'X'); -- address
avalon_nios_writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
avalon_nios_readdata : out std_logic_vector(15 downto 0); -- readdata
avalon_nios_waitrequest : out std_logic; -- waitrequest
avalon_nios_readdatavalid : out std_logic; -- readdatavalid
avalon_nios_burstcount : in std_logic := 'X' -- burstcount
);
end component sega_saturn_abus_slave;
component wasca_spi_sd_card is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
data_from_cpu : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
data_to_cpu : out std_logic_vector(15 downto 0); -- readdata
mem_addr : in std_logic_vector(2 downto 0) := (others => 'X'); -- address
read_n : in std_logic := 'X'; -- read_n
spi_select : in std_logic := 'X'; -- chipselect
write_n : in std_logic := 'X'; -- write_n
irq : out std_logic; -- irq
MISO : in std_logic := 'X'; -- export
MOSI : out std_logic; -- export
SCLK : out std_logic; -- export
SS_n : out std_logic -- export
);
end component wasca_spi_sd_card;
component wasca_spi_stm32 is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
data_from_cpu : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
data_to_cpu : out std_logic_vector(15 downto 0); -- readdata
mem_addr : in std_logic_vector(2 downto 0) := (others => 'X'); -- address
read_n : in std_logic := 'X'; -- read_n
spi_select : in std_logic := 'X'; -- chipselect
write_n : in std_logic := 'X'; -- write_n
irq : out std_logic; -- irq
MISO : out std_logic; -- export
MOSI : in std_logic := 'X'; -- export
SCLK : in std_logic := 'X'; -- export
SS_n : in std_logic := 'X' -- export
);
end component wasca_spi_stm32;
component wasca_uart_0 is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
address : in std_logic_vector(2 downto 0) := (others => 'X'); -- address
begintransfer : in std_logic := 'X'; -- begintransfer
chipselect : in std_logic := 'X'; -- chipselect
read_n : in std_logic := 'X'; -- read_n
write_n : in std_logic := 'X'; -- write_n
writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
readdata : out std_logic_vector(15 downto 0); -- readdata
dataavailable : out std_logic; -- dataavailable
readyfordata : out std_logic; -- readyfordata
rxd : in std_logic := 'X'; -- export
txd : out std_logic; -- export
irq : out std_logic -- irq
);
end component wasca_uart_0;
component wasca_mm_interconnect_0 is
port (
altpll_0_c0_clk : in std_logic := 'X'; -- clk
clk_0_clk_clk : in std_logic := 'X'; -- clk
altpll_0_inclk_interface_reset_reset_bridge_in_reset_reset : in std_logic := 'X'; -- reset
sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset : in std_logic := 'X'; -- reset
nios2_gen2_0_data_master_address : in std_logic_vector(26 downto 0) := (others => 'X'); -- address
nios2_gen2_0_data_master_waitrequest : out std_logic; -- waitrequest
nios2_gen2_0_data_master_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
nios2_gen2_0_data_master_read : in std_logic := 'X'; -- read
nios2_gen2_0_data_master_readdata : out std_logic_vector(31 downto 0); -- readdata
nios2_gen2_0_data_master_write : in std_logic := 'X'; -- write
nios2_gen2_0_data_master_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
nios2_gen2_0_data_master_debugaccess : in std_logic := 'X'; -- debugaccess
nios2_gen2_0_instruction_master_address : in std_logic_vector(26 downto 0) := (others => 'X'); -- address
nios2_gen2_0_instruction_master_waitrequest : out std_logic; -- waitrequest
nios2_gen2_0_instruction_master_read : in std_logic := 'X'; -- read
nios2_gen2_0_instruction_master_readdata : out std_logic_vector(31 downto 0); -- readdata
sega_saturn_abus_slave_0_avalon_master_address : in std_logic_vector(27 downto 0) := (others => 'X'); -- address
sega_saturn_abus_slave_0_avalon_master_waitrequest : out std_logic; -- waitrequest
sega_saturn_abus_slave_0_avalon_master_burstcount : in std_logic_vector(0 downto 0) := (others => 'X'); -- burstcount
sega_saturn_abus_slave_0_avalon_master_read : in std_logic := 'X'; -- read
sega_saturn_abus_slave_0_avalon_master_readdata : out std_logic_vector(15 downto 0); -- readdata
sega_saturn_abus_slave_0_avalon_master_readdatavalid : out std_logic; -- readdatavalid
sega_saturn_abus_slave_0_avalon_master_write : in std_logic := 'X'; -- write
sega_saturn_abus_slave_0_avalon_master_writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
altpll_0_pll_slave_address : out std_logic_vector(1 downto 0); -- address
altpll_0_pll_slave_write : out std_logic; -- write
altpll_0_pll_slave_read : out std_logic; -- read
altpll_0_pll_slave_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
altpll_0_pll_slave_writedata : out std_logic_vector(31 downto 0); -- writedata
audio_0_avalon_audio_slave_address : out std_logic_vector(1 downto 0); -- address
audio_0_avalon_audio_slave_write : out std_logic; -- write
audio_0_avalon_audio_slave_read : out std_logic; -- read
audio_0_avalon_audio_slave_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
audio_0_avalon_audio_slave_writedata : out std_logic_vector(31 downto 0); -- writedata
audio_0_avalon_audio_slave_chipselect : out std_logic; -- chipselect
external_sdram_controller_s1_address : out std_logic_vector(23 downto 0); -- address
external_sdram_controller_s1_write : out std_logic; -- write
external_sdram_controller_s1_read : out std_logic; -- read
external_sdram_controller_s1_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata
external_sdram_controller_s1_writedata : out std_logic_vector(15 downto 0); -- writedata
external_sdram_controller_s1_byteenable : out std_logic_vector(1 downto 0); -- byteenable
external_sdram_controller_s1_readdatavalid : in std_logic := 'X'; -- readdatavalid
external_sdram_controller_s1_waitrequest : in std_logic := 'X'; -- waitrequest
external_sdram_controller_s1_chipselect : out std_logic; -- chipselect
nios2_gen2_0_debug_mem_slave_address : out std_logic_vector(8 downto 0); -- address
nios2_gen2_0_debug_mem_slave_write : out std_logic; -- write
nios2_gen2_0_debug_mem_slave_read : out std_logic; -- read
nios2_gen2_0_debug_mem_slave_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
nios2_gen2_0_debug_mem_slave_writedata : out std_logic_vector(31 downto 0); -- writedata
nios2_gen2_0_debug_mem_slave_byteenable : out std_logic_vector(3 downto 0); -- byteenable
nios2_gen2_0_debug_mem_slave_waitrequest : in std_logic := 'X'; -- waitrequest
nios2_gen2_0_debug_mem_slave_debugaccess : out std_logic; -- debugaccess
onchip_flash_0_data_address : out std_logic_vector(15 downto 0); -- address
onchip_flash_0_data_read : out std_logic; -- read
onchip_flash_0_data_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
onchip_flash_0_data_burstcount : out std_logic_vector(3 downto 0); -- burstcount
onchip_flash_0_data_readdatavalid : in std_logic := 'X'; -- readdatavalid
onchip_flash_0_data_waitrequest : in std_logic := 'X'; -- waitrequest
onchip_memory2_0_s1_address : out std_logic_vector(11 downto 0); -- address
onchip_memory2_0_s1_write : out std_logic; -- write
onchip_memory2_0_s1_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
onchip_memory2_0_s1_writedata : out std_logic_vector(31 downto 0); -- writedata
onchip_memory2_0_s1_byteenable : out std_logic_vector(3 downto 0); -- byteenable
onchip_memory2_0_s1_chipselect : out std_logic; -- chipselect
onchip_memory2_0_s1_clken : out std_logic; -- clken
sega_saturn_abus_slave_0_avalon_nios_address : out std_logic_vector(7 downto 0); -- address
sega_saturn_abus_slave_0_avalon_nios_write : out std_logic; -- write
sega_saturn_abus_slave_0_avalon_nios_read : out std_logic; -- read
sega_saturn_abus_slave_0_avalon_nios_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata
sega_saturn_abus_slave_0_avalon_nios_writedata : out std_logic_vector(15 downto 0); -- writedata
sega_saturn_abus_slave_0_avalon_nios_burstcount : out std_logic_vector(0 downto 0); -- burstcount
sega_saturn_abus_slave_0_avalon_nios_readdatavalid : in std_logic := 'X'; -- readdatavalid
sega_saturn_abus_slave_0_avalon_nios_waitrequest : in std_logic := 'X'; -- waitrequest
spi_sd_card_spi_control_port_address : out std_logic_vector(2 downto 0); -- address
spi_sd_card_spi_control_port_write : out std_logic; -- write
spi_sd_card_spi_control_port_read : out std_logic; -- read
spi_sd_card_spi_control_port_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata
spi_sd_card_spi_control_port_writedata : out std_logic_vector(15 downto 0); -- writedata
spi_sd_card_spi_control_port_chipselect : out std_logic; -- chipselect
spi_stm32_spi_control_port_address : out std_logic_vector(2 downto 0); -- address
spi_stm32_spi_control_port_write : out std_logic; -- write
spi_stm32_spi_control_port_read : out std_logic; -- read
spi_stm32_spi_control_port_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata
spi_stm32_spi_control_port_writedata : out std_logic_vector(15 downto 0); -- writedata
spi_stm32_spi_control_port_chipselect : out std_logic; -- chipselect
uart_0_s1_address : out std_logic_vector(2 downto 0); -- address
uart_0_s1_write : out std_logic; -- write
uart_0_s1_read : out std_logic; -- read
uart_0_s1_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata
uart_0_s1_writedata : out std_logic_vector(15 downto 0); -- writedata
uart_0_s1_begintransfer : out std_logic; -- begintransfer
uart_0_s1_chipselect : out std_logic -- chipselect
);
end component wasca_mm_interconnect_0;
component wasca_irq_mapper is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
receiver0_irq : in std_logic := 'X'; -- irq
receiver1_irq : in std_logic := 'X'; -- irq
receiver2_irq : in std_logic := 'X'; -- irq
receiver3_irq : in std_logic := 'X'; -- irq
sender_irq : out std_logic_vector(31 downto 0) -- irq
);
end component wasca_irq_mapper;
component wasca_rst_controller is
generic (
NUM_RESET_INPUTS : integer := 6;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 0;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := 'X'; -- reset
clk : in std_logic := 'X'; -- clk
reset_out : out std_logic; -- reset
reset_req : out std_logic; -- reset_req
reset_req_in0 : in std_logic := 'X'; -- reset_req
reset_in1 : in std_logic := 'X'; -- reset
reset_req_in1 : in std_logic := 'X'; -- reset_req
reset_in2 : in std_logic := 'X'; -- reset
reset_req_in2 : in std_logic := 'X'; -- reset_req
reset_in3 : in std_logic := 'X'; -- reset
reset_req_in3 : in std_logic := 'X'; -- reset_req
reset_in4 : in std_logic := 'X'; -- reset
reset_req_in4 : in std_logic := 'X'; -- reset_req
reset_in5 : in std_logic := 'X'; -- reset
reset_req_in5 : in std_logic := 'X'; -- reset_req
reset_in6 : in std_logic := 'X'; -- reset
reset_req_in6 : in std_logic := 'X'; -- reset_req
reset_in7 : in std_logic := 'X'; -- reset
reset_req_in7 : in std_logic := 'X'; -- reset_req
reset_in8 : in std_logic := 'X'; -- reset
reset_req_in8 : in std_logic := 'X'; -- reset_req
reset_in9 : in std_logic := 'X'; -- reset
reset_req_in9 : in std_logic := 'X'; -- reset_req
reset_in10 : in std_logic := 'X'; -- reset
reset_req_in10 : in std_logic := 'X'; -- reset_req
reset_in11 : in std_logic := 'X'; -- reset
reset_req_in11 : in std_logic := 'X'; -- reset_req
reset_in12 : in std_logic := 'X'; -- reset
reset_req_in12 : in std_logic := 'X'; -- reset_req
reset_in13 : in std_logic := 'X'; -- reset
reset_req_in13 : in std_logic := 'X'; -- reset_req
reset_in14 : in std_logic := 'X'; -- reset
reset_req_in14 : in std_logic := 'X'; -- reset_req
reset_in15 : in std_logic := 'X'; -- reset
reset_req_in15 : in std_logic := 'X' -- reset_req
);
end component wasca_rst_controller;
component wasca_rst_controller_001 is
generic (
NUM_RESET_INPUTS : integer := 6;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 0;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := 'X'; -- reset
clk : in std_logic := 'X'; -- clk
reset_out : out std_logic; -- reset
reset_req : out std_logic; -- reset_req
reset_req_in0 : in std_logic := 'X'; -- reset_req
reset_in1 : in std_logic := 'X'; -- reset
reset_req_in1 : in std_logic := 'X'; -- reset_req
reset_in2 : in std_logic := 'X'; -- reset
reset_req_in2 : in std_logic := 'X'; -- reset_req
reset_in3 : in std_logic := 'X'; -- reset
reset_req_in3 : in std_logic := 'X'; -- reset_req
reset_in4 : in std_logic := 'X'; -- reset
reset_req_in4 : in std_logic := 'X'; -- reset_req
reset_in5 : in std_logic := 'X'; -- reset
reset_req_in5 : in std_logic := 'X'; -- reset_req
reset_in6 : in std_logic := 'X'; -- reset
reset_req_in6 : in std_logic := 'X'; -- reset_req
reset_in7 : in std_logic := 'X'; -- reset
reset_req_in7 : in std_logic := 'X'; -- reset_req
reset_in8 : in std_logic := 'X'; -- reset
reset_req_in8 : in std_logic := 'X'; -- reset_req
reset_in9 : in std_logic := 'X'; -- reset
reset_req_in9 : in std_logic := 'X'; -- reset_req
reset_in10 : in std_logic := 'X'; -- reset
reset_req_in10 : in std_logic := 'X'; -- reset_req
reset_in11 : in std_logic := 'X'; -- reset
reset_req_in11 : in std_logic := 'X'; -- reset_req
reset_in12 : in std_logic := 'X'; -- reset
reset_req_in12 : in std_logic := 'X'; -- reset_req
reset_in13 : in std_logic := 'X'; -- reset
reset_req_in13 : in std_logic := 'X'; -- reset_req
reset_in14 : in std_logic := 'X'; -- reset
reset_req_in14 : in std_logic := 'X'; -- reset_req
reset_in15 : in std_logic := 'X'; -- reset
reset_req_in15 : in std_logic := 'X' -- reset_req
);
end component wasca_rst_controller_001;
signal altpll_0_c0_clk : std_logic; -- altpll_0:c0 -> [clock_116_mhz_clk, audio_0:clk, external_sdram_controller:clk, irq_mapper:clk, mm_interconnect_0:altpll_0_c0_clk, nios2_gen2_0:clk, onchip_flash_0:clock, onchip_memory2_0:clk, rst_controller_001:clk, rst_controller_002:clk, sega_saturn_abus_slave_0:clock, spi_sd_card:clk, spi_stm32:clk, uart_0:clk]
signal nios2_gen2_0_debug_reset_request_reset : std_logic; -- nios2_gen2_0:debug_reset_request -> [rst_controller:reset_in0, rst_controller_001:reset_in0, rst_controller_002:reset_in0]
signal sega_saturn_abus_slave_0_avalon_master_waitrequest : std_logic; -- mm_interconnect_0:sega_saturn_abus_slave_0_avalon_master_waitrequest -> sega_saturn_abus_slave_0:avalon_waitrequest
signal sega_saturn_abus_slave_0_avalon_master_readdata : std_logic_vector(15 downto 0); -- mm_interconnect_0:sega_saturn_abus_slave_0_avalon_master_readdata -> sega_saturn_abus_slave_0:avalon_readdata
signal sega_saturn_abus_slave_0_avalon_master_read : std_logic; -- sega_saturn_abus_slave_0:avalon_read -> mm_interconnect_0:sega_saturn_abus_slave_0_avalon_master_read
signal sega_saturn_abus_slave_0_avalon_master_address : std_logic_vector(27 downto 0); -- sega_saturn_abus_slave_0:avalon_address -> mm_interconnect_0:sega_saturn_abus_slave_0_avalon_master_address
signal sega_saturn_abus_slave_0_avalon_master_readdatavalid : std_logic; -- mm_interconnect_0:sega_saturn_abus_slave_0_avalon_master_readdatavalid -> sega_saturn_abus_slave_0:avalon_readdatavalid
signal sega_saturn_abus_slave_0_avalon_master_write : std_logic; -- sega_saturn_abus_slave_0:avalon_write -> mm_interconnect_0:sega_saturn_abus_slave_0_avalon_master_write
signal sega_saturn_abus_slave_0_avalon_master_writedata : std_logic_vector(15 downto 0); -- sega_saturn_abus_slave_0:avalon_writedata -> mm_interconnect_0:sega_saturn_abus_slave_0_avalon_master_writedata
signal sega_saturn_abus_slave_0_avalon_master_burstcount : std_logic; -- sega_saturn_abus_slave_0:avalon_burstcount -> mm_interconnect_0:sega_saturn_abus_slave_0_avalon_master_burstcount
signal nios2_gen2_0_data_master_readdata : std_logic_vector(31 downto 0); -- mm_interconnect_0:nios2_gen2_0_data_master_readdata -> nios2_gen2_0:d_readdata
signal nios2_gen2_0_data_master_waitrequest : std_logic; -- mm_interconnect_0:nios2_gen2_0_data_master_waitrequest -> nios2_gen2_0:d_waitrequest
signal nios2_gen2_0_data_master_debugaccess : std_logic; -- nios2_gen2_0:debug_mem_slave_debugaccess_to_roms -> mm_interconnect_0:nios2_gen2_0_data_master_debugaccess
signal nios2_gen2_0_data_master_address : std_logic_vector(26 downto 0); -- nios2_gen2_0:d_address -> mm_interconnect_0:nios2_gen2_0_data_master_address
signal nios2_gen2_0_data_master_byteenable : std_logic_vector(3 downto 0); -- nios2_gen2_0:d_byteenable -> mm_interconnect_0:nios2_gen2_0_data_master_byteenable
signal nios2_gen2_0_data_master_read : std_logic; -- nios2_gen2_0:d_read -> mm_interconnect_0:nios2_gen2_0_data_master_read
signal nios2_gen2_0_data_master_write : std_logic; -- nios2_gen2_0:d_write -> mm_interconnect_0:nios2_gen2_0_data_master_write
signal nios2_gen2_0_data_master_writedata : std_logic_vector(31 downto 0); -- nios2_gen2_0:d_writedata -> mm_interconnect_0:nios2_gen2_0_data_master_writedata
signal nios2_gen2_0_instruction_master_readdata : std_logic_vector(31 downto 0); -- mm_interconnect_0:nios2_gen2_0_instruction_master_readdata -> nios2_gen2_0:i_readdata
signal nios2_gen2_0_instruction_master_waitrequest : std_logic; -- mm_interconnect_0:nios2_gen2_0_instruction_master_waitrequest -> nios2_gen2_0:i_waitrequest
signal nios2_gen2_0_instruction_master_address : std_logic_vector(26 downto 0); -- nios2_gen2_0:i_address -> mm_interconnect_0:nios2_gen2_0_instruction_master_address
signal nios2_gen2_0_instruction_master_read : std_logic; -- nios2_gen2_0:i_read -> mm_interconnect_0:nios2_gen2_0_instruction_master_read
signal mm_interconnect_0_external_sdram_controller_s1_chipselect : std_logic; -- mm_interconnect_0:external_sdram_controller_s1_chipselect -> external_sdram_controller:az_cs
signal mm_interconnect_0_external_sdram_controller_s1_readdata : std_logic_vector(15 downto 0); -- external_sdram_controller:za_data -> mm_interconnect_0:external_sdram_controller_s1_readdata
signal mm_interconnect_0_external_sdram_controller_s1_waitrequest : std_logic; -- external_sdram_controller:za_waitrequest -> mm_interconnect_0:external_sdram_controller_s1_waitrequest
signal mm_interconnect_0_external_sdram_controller_s1_address : std_logic_vector(23 downto 0); -- mm_interconnect_0:external_sdram_controller_s1_address -> external_sdram_controller:az_addr
signal mm_interconnect_0_external_sdram_controller_s1_read : std_logic; -- mm_interconnect_0:external_sdram_controller_s1_read -> mm_interconnect_0_external_sdram_controller_s1_read:in
signal mm_interconnect_0_external_sdram_controller_s1_byteenable : std_logic_vector(1 downto 0); -- mm_interconnect_0:external_sdram_controller_s1_byteenable -> mm_interconnect_0_external_sdram_controller_s1_byteenable:in
signal mm_interconnect_0_external_sdram_controller_s1_readdatavalid : std_logic; -- external_sdram_controller:za_valid -> mm_interconnect_0:external_sdram_controller_s1_readdatavalid
signal mm_interconnect_0_external_sdram_controller_s1_write : std_logic; -- mm_interconnect_0:external_sdram_controller_s1_write -> mm_interconnect_0_external_sdram_controller_s1_write:in
signal mm_interconnect_0_external_sdram_controller_s1_writedata : std_logic_vector(15 downto 0); -- mm_interconnect_0:external_sdram_controller_s1_writedata -> external_sdram_controller:az_data
signal mm_interconnect_0_onchip_flash_0_data_readdata : std_logic_vector(31 downto 0); -- onchip_flash_0:avmm_data_readdata -> mm_interconnect_0:onchip_flash_0_data_readdata
signal mm_interconnect_0_onchip_flash_0_data_waitrequest : std_logic; -- onchip_flash_0:avmm_data_waitrequest -> mm_interconnect_0:onchip_flash_0_data_waitrequest
signal mm_interconnect_0_onchip_flash_0_data_address : std_logic_vector(15 downto 0); -- mm_interconnect_0:onchip_flash_0_data_address -> onchip_flash_0:avmm_data_addr
signal mm_interconnect_0_onchip_flash_0_data_read : std_logic; -- mm_interconnect_0:onchip_flash_0_data_read -> onchip_flash_0:avmm_data_read
signal mm_interconnect_0_onchip_flash_0_data_readdatavalid : std_logic; -- onchip_flash_0:avmm_data_readdatavalid -> mm_interconnect_0:onchip_flash_0_data_readdatavalid
signal mm_interconnect_0_onchip_flash_0_data_burstcount : std_logic_vector(3 downto 0); -- mm_interconnect_0:onchip_flash_0_data_burstcount -> onchip_flash_0:avmm_data_burstcount
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata : std_logic_vector(31 downto 0); -- nios2_gen2_0:debug_mem_slave_readdata -> mm_interconnect_0:nios2_gen2_0_debug_mem_slave_readdata
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest : std_logic; -- nios2_gen2_0:debug_mem_slave_waitrequest -> mm_interconnect_0:nios2_gen2_0_debug_mem_slave_waitrequest
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess : std_logic; -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_debugaccess -> nios2_gen2_0:debug_mem_slave_debugaccess
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address : std_logic_vector(8 downto 0); -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_address -> nios2_gen2_0:debug_mem_slave_address
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read : std_logic; -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_read -> nios2_gen2_0:debug_mem_slave_read
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable : std_logic_vector(3 downto 0); -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_byteenable -> nios2_gen2_0:debug_mem_slave_byteenable
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write : std_logic; -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_write -> nios2_gen2_0:debug_mem_slave_write
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_writedata -> nios2_gen2_0:debug_mem_slave_writedata
signal mm_interconnect_0_onchip_memory2_0_s1_chipselect : std_logic; -- mm_interconnect_0:onchip_memory2_0_s1_chipselect -> onchip_memory2_0:chipselect
signal mm_interconnect_0_onchip_memory2_0_s1_readdata : std_logic_vector(31 downto 0); -- onchip_memory2_0:readdata -> mm_interconnect_0:onchip_memory2_0_s1_readdata
signal mm_interconnect_0_onchip_memory2_0_s1_address : std_logic_vector(11 downto 0); -- mm_interconnect_0:onchip_memory2_0_s1_address -> onchip_memory2_0:address
signal mm_interconnect_0_onchip_memory2_0_s1_byteenable : std_logic_vector(3 downto 0); -- mm_interconnect_0:onchip_memory2_0_s1_byteenable -> onchip_memory2_0:byteenable
signal mm_interconnect_0_onchip_memory2_0_s1_write : std_logic; -- mm_interconnect_0:onchip_memory2_0_s1_write -> onchip_memory2_0:write
signal mm_interconnect_0_onchip_memory2_0_s1_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:onchip_memory2_0_s1_writedata -> onchip_memory2_0:writedata
signal mm_interconnect_0_onchip_memory2_0_s1_clken : std_logic; -- mm_interconnect_0:onchip_memory2_0_s1_clken -> onchip_memory2_0:clken
signal mm_interconnect_0_audio_0_avalon_audio_slave_chipselect : std_logic; -- mm_interconnect_0:audio_0_avalon_audio_slave_chipselect -> audio_0:chipselect
signal mm_interconnect_0_audio_0_avalon_audio_slave_readdata : std_logic_vector(31 downto 0); -- audio_0:readdata -> mm_interconnect_0:audio_0_avalon_audio_slave_readdata
signal mm_interconnect_0_audio_0_avalon_audio_slave_address : std_logic_vector(1 downto 0); -- mm_interconnect_0:audio_0_avalon_audio_slave_address -> audio_0:address
signal mm_interconnect_0_audio_0_avalon_audio_slave_read : std_logic; -- mm_interconnect_0:audio_0_avalon_audio_slave_read -> audio_0:read
signal mm_interconnect_0_audio_0_avalon_audio_slave_write : std_logic; -- mm_interconnect_0:audio_0_avalon_audio_slave_write -> audio_0:write
signal mm_interconnect_0_audio_0_avalon_audio_slave_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:audio_0_avalon_audio_slave_writedata -> audio_0:writedata
signal mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_readdata : std_logic_vector(15 downto 0); -- sega_saturn_abus_slave_0:avalon_nios_readdata -> mm_interconnect_0:sega_saturn_abus_slave_0_avalon_nios_readdata
signal mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_waitrequest : std_logic; -- sega_saturn_abus_slave_0:avalon_nios_waitrequest -> mm_interconnect_0:sega_saturn_abus_slave_0_avalon_nios_waitrequest
signal mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_address : std_logic_vector(7 downto 0); -- mm_interconnect_0:sega_saturn_abus_slave_0_avalon_nios_address -> sega_saturn_abus_slave_0:avalon_nios_address
signal mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_read : std_logic; -- mm_interconnect_0:sega_saturn_abus_slave_0_avalon_nios_read -> sega_saturn_abus_slave_0:avalon_nios_read
signal mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_readdatavalid : std_logic; -- sega_saturn_abus_slave_0:avalon_nios_readdatavalid -> mm_interconnect_0:sega_saturn_abus_slave_0_avalon_nios_readdatavalid
signal mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_write : std_logic; -- mm_interconnect_0:sega_saturn_abus_slave_0_avalon_nios_write -> sega_saturn_abus_slave_0:avalon_nios_write
signal mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_writedata : std_logic_vector(15 downto 0); -- mm_interconnect_0:sega_saturn_abus_slave_0_avalon_nios_writedata -> sega_saturn_abus_slave_0:avalon_nios_writedata
signal mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_burstcount : std_logic_vector(0 downto 0); -- mm_interconnect_0:sega_saturn_abus_slave_0_avalon_nios_burstcount -> sega_saturn_abus_slave_0:avalon_nios_burstcount
signal mm_interconnect_0_altpll_0_pll_slave_readdata : std_logic_vector(31 downto 0); -- altpll_0:readdata -> mm_interconnect_0:altpll_0_pll_slave_readdata
signal mm_interconnect_0_altpll_0_pll_slave_address : std_logic_vector(1 downto 0); -- mm_interconnect_0:altpll_0_pll_slave_address -> altpll_0:address
signal mm_interconnect_0_altpll_0_pll_slave_read : std_logic; -- mm_interconnect_0:altpll_0_pll_slave_read -> altpll_0:read
signal mm_interconnect_0_altpll_0_pll_slave_write : std_logic; -- mm_interconnect_0:altpll_0_pll_slave_write -> altpll_0:write
signal mm_interconnect_0_altpll_0_pll_slave_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:altpll_0_pll_slave_writedata -> altpll_0:writedata
signal mm_interconnect_0_uart_0_s1_chipselect : std_logic; -- mm_interconnect_0:uart_0_s1_chipselect -> uart_0:chipselect
signal mm_interconnect_0_uart_0_s1_readdata : std_logic_vector(15 downto 0); -- uart_0:readdata -> mm_interconnect_0:uart_0_s1_readdata
signal mm_interconnect_0_uart_0_s1_address : std_logic_vector(2 downto 0); -- mm_interconnect_0:uart_0_s1_address -> uart_0:address
signal mm_interconnect_0_uart_0_s1_read : std_logic; -- mm_interconnect_0:uart_0_s1_read -> mm_interconnect_0_uart_0_s1_read:in
signal mm_interconnect_0_uart_0_s1_begintransfer : std_logic; -- mm_interconnect_0:uart_0_s1_begintransfer -> uart_0:begintransfer
signal mm_interconnect_0_uart_0_s1_write : std_logic; -- mm_interconnect_0:uart_0_s1_write -> mm_interconnect_0_uart_0_s1_write:in
signal mm_interconnect_0_uart_0_s1_writedata : std_logic_vector(15 downto 0); -- mm_interconnect_0:uart_0_s1_writedata -> uart_0:writedata
signal mm_interconnect_0_spi_sd_card_spi_control_port_chipselect : std_logic; -- mm_interconnect_0:spi_sd_card_spi_control_port_chipselect -> spi_sd_card:spi_select
signal mm_interconnect_0_spi_sd_card_spi_control_port_readdata : std_logic_vector(15 downto 0); -- spi_sd_card:data_to_cpu -> mm_interconnect_0:spi_sd_card_spi_control_port_readdata
signal mm_interconnect_0_spi_sd_card_spi_control_port_address : std_logic_vector(2 downto 0); -- mm_interconnect_0:spi_sd_card_spi_control_port_address -> spi_sd_card:mem_addr
signal mm_interconnect_0_spi_sd_card_spi_control_port_read : std_logic; -- mm_interconnect_0:spi_sd_card_spi_control_port_read -> mm_interconnect_0_spi_sd_card_spi_control_port_read:in
signal mm_interconnect_0_spi_sd_card_spi_control_port_write : std_logic; -- mm_interconnect_0:spi_sd_card_spi_control_port_write -> mm_interconnect_0_spi_sd_card_spi_control_port_write:in
signal mm_interconnect_0_spi_sd_card_spi_control_port_writedata : std_logic_vector(15 downto 0); -- mm_interconnect_0:spi_sd_card_spi_control_port_writedata -> spi_sd_card:data_from_cpu
signal mm_interconnect_0_spi_stm32_spi_control_port_chipselect : std_logic; -- mm_interconnect_0:spi_stm32_spi_control_port_chipselect -> spi_stm32:spi_select
signal mm_interconnect_0_spi_stm32_spi_control_port_readdata : std_logic_vector(15 downto 0); -- spi_stm32:data_to_cpu -> mm_interconnect_0:spi_stm32_spi_control_port_readdata
signal mm_interconnect_0_spi_stm32_spi_control_port_address : std_logic_vector(2 downto 0); -- mm_interconnect_0:spi_stm32_spi_control_port_address -> spi_stm32:mem_addr
signal mm_interconnect_0_spi_stm32_spi_control_port_read : std_logic; -- mm_interconnect_0:spi_stm32_spi_control_port_read -> mm_interconnect_0_spi_stm32_spi_control_port_read:in
signal mm_interconnect_0_spi_stm32_spi_control_port_write : std_logic; -- mm_interconnect_0:spi_stm32_spi_control_port_write -> mm_interconnect_0_spi_stm32_spi_control_port_write:in
signal mm_interconnect_0_spi_stm32_spi_control_port_writedata : std_logic_vector(15 downto 0); -- mm_interconnect_0:spi_stm32_spi_control_port_writedata -> spi_stm32:data_from_cpu
signal irq_mapper_receiver0_irq : std_logic; -- audio_0:irq -> irq_mapper:receiver0_irq
signal irq_mapper_receiver1_irq : std_logic; -- uart_0:irq -> irq_mapper:receiver1_irq
signal irq_mapper_receiver2_irq : std_logic; -- spi_sd_card:irq -> irq_mapper:receiver2_irq
signal irq_mapper_receiver3_irq : std_logic; -- spi_stm32:irq -> irq_mapper:receiver3_irq
signal nios2_gen2_0_irq_irq : std_logic_vector(31 downto 0); -- irq_mapper:sender_irq -> nios2_gen2_0:irq
signal rst_controller_reset_out_reset : std_logic; -- rst_controller:reset_out -> [altpll_0:reset, mm_interconnect_0:altpll_0_inclk_interface_reset_reset_bridge_in_reset_reset]
signal rst_controller_001_reset_out_reset : std_logic; -- rst_controller_001:reset_out -> [audio_0:reset, irq_mapper:reset, mm_interconnect_0:sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset, onchip_memory2_0:reset, rst_controller_001_reset_out_reset:in, rst_translator:in_reset, sega_saturn_abus_slave_0:reset]
signal rst_controller_001_reset_out_reset_req : std_logic; -- rst_controller_001:reset_req -> [onchip_memory2_0:reset_req, rst_translator:reset_req_in]
signal mm_interconnect_0_external_sdram_controller_s1_read_ports_inv : std_logic; -- mm_interconnect_0_external_sdram_controller_s1_read:inv -> external_sdram_controller:az_rd_n
signal mm_interconnect_0_external_sdram_controller_s1_byteenable_ports_inv : std_logic_vector(1 downto 0); -- mm_interconnect_0_external_sdram_controller_s1_byteenable:inv -> external_sdram_controller:az_be_n
signal mm_interconnect_0_external_sdram_controller_s1_write_ports_inv : std_logic; -- mm_interconnect_0_external_sdram_controller_s1_write:inv -> external_sdram_controller:az_wr_n
signal mm_interconnect_0_uart_0_s1_read_ports_inv : std_logic; -- mm_interconnect_0_uart_0_s1_read:inv -> uart_0:read_n
signal mm_interconnect_0_uart_0_s1_write_ports_inv : std_logic; -- mm_interconnect_0_uart_0_s1_write:inv -> uart_0:write_n
signal mm_interconnect_0_spi_sd_card_spi_control_port_read_ports_inv : std_logic; -- mm_interconnect_0_spi_sd_card_spi_control_port_read:inv -> spi_sd_card:read_n
signal mm_interconnect_0_spi_sd_card_spi_control_port_write_ports_inv : std_logic; -- mm_interconnect_0_spi_sd_card_spi_control_port_write:inv -> spi_sd_card:write_n
signal mm_interconnect_0_spi_stm32_spi_control_port_read_ports_inv : std_logic; -- mm_interconnect_0_spi_stm32_spi_control_port_read:inv -> spi_stm32:read_n
signal mm_interconnect_0_spi_stm32_spi_control_port_write_ports_inv : std_logic; -- mm_interconnect_0_spi_stm32_spi_control_port_write:inv -> spi_stm32:write_n
signal rst_controller_001_reset_out_reset_ports_inv : std_logic; -- rst_controller_001_reset_out_reset:inv -> [external_sdram_controller:reset_n, nios2_gen2_0:reset_n, onchip_flash_0:reset_n, spi_sd_card:reset_n, spi_stm32:reset_n, uart_0:reset_n]
begin
altpll_0 : component wasca_altpll_0
port map (
clk => clk_clk, -- inclk_interface.clk
reset => rst_controller_reset_out_reset, -- inclk_interface_reset.reset
read => mm_interconnect_0_altpll_0_pll_slave_read, -- pll_slave.read
write => mm_interconnect_0_altpll_0_pll_slave_write, -- .write
address => mm_interconnect_0_altpll_0_pll_slave_address, -- .address
readdata => mm_interconnect_0_altpll_0_pll_slave_readdata, -- .readdata
writedata => mm_interconnect_0_altpll_0_pll_slave_writedata, -- .writedata
c0 => altpll_0_c0_clk, -- c0.clk
areset => altpll_0_areset_conduit_export, -- areset_conduit.export
c1 => open, -- c1_conduit.export
locked => altpll_0_locked_conduit_export, -- locked_conduit.export
phasedone => altpll_0_phasedone_conduit_export -- phasedone_conduit.export
);
audio_0 : component wasca_audio_0
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- reset.reset
address => mm_interconnect_0_audio_0_avalon_audio_slave_address, -- avalon_audio_slave.address
chipselect => mm_interconnect_0_audio_0_avalon_audio_slave_chipselect, -- .chipselect
read => mm_interconnect_0_audio_0_avalon_audio_slave_read, -- .read
write => mm_interconnect_0_audio_0_avalon_audio_slave_write, -- .write
writedata => mm_interconnect_0_audio_0_avalon_audio_slave_writedata, -- .writedata
readdata => mm_interconnect_0_audio_0_avalon_audio_slave_readdata, -- .readdata
irq => irq_mapper_receiver0_irq, -- interrupt.irq
AUD_BCLK => audio_out_BCLK, -- external_interface.export
AUD_DACDAT => audio_out_DACDAT, -- .export
AUD_DACLRCK => audio_out_DACLRCK -- .export
);
external_sdram_controller : component wasca_external_sdram_controller
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset_n => rst_controller_001_reset_out_reset_ports_inv, -- reset.reset_n
az_addr => mm_interconnect_0_external_sdram_controller_s1_address, -- s1.address
az_be_n => mm_interconnect_0_external_sdram_controller_s1_byteenable_ports_inv, -- .byteenable_n
az_cs => mm_interconnect_0_external_sdram_controller_s1_chipselect, -- .chipselect
az_data => mm_interconnect_0_external_sdram_controller_s1_writedata, -- .writedata
az_rd_n => mm_interconnect_0_external_sdram_controller_s1_read_ports_inv, -- .read_n
az_wr_n => mm_interconnect_0_external_sdram_controller_s1_write_ports_inv, -- .write_n
za_data => mm_interconnect_0_external_sdram_controller_s1_readdata, -- .readdata
za_valid => mm_interconnect_0_external_sdram_controller_s1_readdatavalid, -- .readdatavalid
za_waitrequest => mm_interconnect_0_external_sdram_controller_s1_waitrequest, -- .waitrequest
zs_addr => external_sdram_controller_wire_addr, -- wire.export
zs_ba => external_sdram_controller_wire_ba, -- .export
zs_cas_n => external_sdram_controller_wire_cas_n, -- .export
zs_cke => external_sdram_controller_wire_cke, -- .export
zs_cs_n => external_sdram_controller_wire_cs_n, -- .export
zs_dq => external_sdram_controller_wire_dq, -- .export
zs_dqm => external_sdram_controller_wire_dqm, -- .export
zs_ras_n => external_sdram_controller_wire_ras_n, -- .export
zs_we_n => external_sdram_controller_wire_we_n -- .export
);
nios2_gen2_0 : component wasca_nios2_gen2_0
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset_n => rst_controller_001_reset_out_reset_ports_inv, -- reset.reset_n
d_address => nios2_gen2_0_data_master_address, -- data_master.address
d_byteenable => nios2_gen2_0_data_master_byteenable, -- .byteenable
d_read => nios2_gen2_0_data_master_read, -- .read
d_readdata => nios2_gen2_0_data_master_readdata, -- .readdata
d_waitrequest => nios2_gen2_0_data_master_waitrequest, -- .waitrequest
d_write => nios2_gen2_0_data_master_write, -- .write
d_writedata => nios2_gen2_0_data_master_writedata, -- .writedata
debug_mem_slave_debugaccess_to_roms => nios2_gen2_0_data_master_debugaccess, -- .debugaccess
i_address => nios2_gen2_0_instruction_master_address, -- instruction_master.address
i_read => nios2_gen2_0_instruction_master_read, -- .read
i_readdata => nios2_gen2_0_instruction_master_readdata, -- .readdata
i_waitrequest => nios2_gen2_0_instruction_master_waitrequest, -- .waitrequest
irq => nios2_gen2_0_irq_irq, -- irq.irq
debug_reset_request => nios2_gen2_0_debug_reset_request_reset, -- debug_reset_request.reset
debug_mem_slave_address => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address, -- debug_mem_slave.address
debug_mem_slave_byteenable => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable, -- .byteenable
debug_mem_slave_debugaccess => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess, -- .debugaccess
debug_mem_slave_read => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read, -- .read
debug_mem_slave_readdata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata, -- .readdata
debug_mem_slave_waitrequest => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest, -- .waitrequest
debug_mem_slave_write => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write, -- .write
debug_mem_slave_writedata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata, -- .writedata
dummy_ci_port => open -- custom_instruction_master.readra
);
onchip_flash_0 : component altera_onchip_flash
generic map (
INIT_FILENAME => "",
INIT_FILENAME_SIM => "",
DEVICE_FAMILY => "MAX 10",
PART_NAME => "10M08SAE144C8GES",
DEVICE_ID => "08",
SECTOR1_START_ADDR => 0,
SECTOR1_END_ADDR => 4095,
SECTOR2_START_ADDR => 4096,
SECTOR2_END_ADDR => 8191,
SECTOR3_START_ADDR => 8192,
SECTOR3_END_ADDR => 29183,
SECTOR4_START_ADDR => 29184,
SECTOR4_END_ADDR => 44031,
SECTOR5_START_ADDR => 0,
SECTOR5_END_ADDR => 0,
MIN_VALID_ADDR => 0,
MAX_VALID_ADDR => 44031,
MIN_UFM_VALID_ADDR => 0,
MAX_UFM_VALID_ADDR => 44031,
SECTOR1_MAP => 1,
SECTOR2_MAP => 2,
SECTOR3_MAP => 3,
SECTOR4_MAP => 4,
SECTOR5_MAP => 0,
ADDR_RANGE1_END_ADDR => 44031,
ADDR_RANGE1_OFFSET => 512,
ADDR_RANGE2_OFFSET => 0,
AVMM_DATA_ADDR_WIDTH => 16,
AVMM_DATA_DATA_WIDTH => 32,
AVMM_DATA_BURSTCOUNT_WIDTH => 4,
SECTOR_READ_PROTECTION_MODE => 31,
FLASH_SEQ_READ_DATA_COUNT => 2,
FLASH_ADDR_ALIGNMENT_BITS => 1,
FLASH_READ_CYCLE_MAX_INDEX => 3,
FLASH_RESET_CYCLE_MAX_INDEX => 29,
FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX => 111,
FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX => 40603248,
FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX => 35382,
PARALLEL_MODE => true,
READ_AND_WRITE_MODE => false,
WRAPPING_BURST_MODE => false,
IS_DUAL_BOOT => "False",
IS_ERAM_SKIP => "True",
IS_COMPRESSED_IMAGE => "True"
)
port map (
clock => altpll_0_c0_clk, -- clk.clk
reset_n => rst_controller_001_reset_out_reset_ports_inv, -- nreset.reset_n
avmm_data_addr => mm_interconnect_0_onchip_flash_0_data_address, -- data.address
avmm_data_read => mm_interconnect_0_onchip_flash_0_data_read, -- .read
avmm_data_readdata => mm_interconnect_0_onchip_flash_0_data_readdata, -- .readdata
avmm_data_waitrequest => mm_interconnect_0_onchip_flash_0_data_waitrequest, -- .waitrequest
avmm_data_readdatavalid => mm_interconnect_0_onchip_flash_0_data_readdatavalid, -- .readdatavalid
avmm_data_burstcount => mm_interconnect_0_onchip_flash_0_data_burstcount, -- .burstcount
avmm_data_writedata => "00000000000000000000000000000000", -- (terminated)
avmm_data_write => '0', -- (terminated)
avmm_csr_addr => '0', -- (terminated)
avmm_csr_read => '0', -- (terminated)
avmm_csr_writedata => "00000000000000000000000000000000", -- (terminated)
avmm_csr_write => '0', -- (terminated)
avmm_csr_readdata => open -- (terminated)
);
onchip_memory2_0 : component wasca_onchip_memory2_0
port map (
clk => altpll_0_c0_clk, -- clk1.clk
address => mm_interconnect_0_onchip_memory2_0_s1_address, -- s1.address
clken => mm_interconnect_0_onchip_memory2_0_s1_clken, -- .clken
chipselect => mm_interconnect_0_onchip_memory2_0_s1_chipselect, -- .chipselect
write => mm_interconnect_0_onchip_memory2_0_s1_write, -- .write
readdata => mm_interconnect_0_onchip_memory2_0_s1_readdata, -- .readdata
writedata => mm_interconnect_0_onchip_memory2_0_s1_writedata, -- .writedata
byteenable => mm_interconnect_0_onchip_memory2_0_s1_byteenable, -- .byteenable
reset => rst_controller_001_reset_out_reset, -- reset1.reset
reset_req => rst_controller_001_reset_out_reset_req -- .reset_req
);
sega_saturn_abus_slave_0 : component sega_saturn_abus_slave
port map (
clock => altpll_0_c0_clk, -- clock.clk
abus_address => sega_saturn_abus_slave_0_abus_address, -- abus.address
abus_chipselect => sega_saturn_abus_slave_0_abus_chipselect, -- .chipselect
abus_read => sega_saturn_abus_slave_0_abus_read, -- .read
abus_write => sega_saturn_abus_slave_0_abus_write, -- .write
abus_waitrequest => sega_saturn_abus_slave_0_abus_waitrequest, -- .waitrequest
abus_interrupt => sega_saturn_abus_slave_0_abus_interrupt, -- .interrupt
abus_addressdata => sega_saturn_abus_slave_0_abus_addressdata, -- .addressdata
abus_direction => sega_saturn_abus_slave_0_abus_direction, -- .direction
abus_muxing => sega_saturn_abus_slave_0_abus_muxing, -- .muxing
abus_disable_out => sega_saturn_abus_slave_0_abus_disableout, -- .disableout
avalon_read => sega_saturn_abus_slave_0_avalon_master_read, -- avalon_master.read
avalon_write => sega_saturn_abus_slave_0_avalon_master_write, -- .write
avalon_waitrequest => sega_saturn_abus_slave_0_avalon_master_waitrequest, -- .waitrequest
avalon_address => sega_saturn_abus_slave_0_avalon_master_address, -- .address
avalon_readdata => sega_saturn_abus_slave_0_avalon_master_readdata, -- .readdata
avalon_writedata => sega_saturn_abus_slave_0_avalon_master_writedata, -- .writedata
avalon_readdatavalid => sega_saturn_abus_slave_0_avalon_master_readdatavalid, -- .readdatavalid
avalon_burstcount => sega_saturn_abus_slave_0_avalon_master_burstcount, -- .burstcount
reset => rst_controller_001_reset_out_reset, -- reset.reset
saturn_reset => sega_saturn_abus_slave_0_conduit_saturn_reset_saturn_reset, -- conduit_saturn_reset.saturn_reset
avalon_nios_read => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_read, -- avalon_nios.read
avalon_nios_write => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_write, -- .write
avalon_nios_address => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_address, -- .address
avalon_nios_writedata => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_writedata, -- .writedata
avalon_nios_readdata => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_readdata, -- .readdata
avalon_nios_waitrequest => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_waitrequest, -- .waitrequest
avalon_nios_readdatavalid => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_readdatavalid, -- .readdatavalid
avalon_nios_burstcount => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_burstcount(0) -- .burstcount
);
spi_sd_card : component wasca_spi_sd_card
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset_n => rst_controller_001_reset_out_reset_ports_inv, -- reset.reset_n
data_from_cpu => mm_interconnect_0_spi_sd_card_spi_control_port_writedata, -- spi_control_port.writedata
data_to_cpu => mm_interconnect_0_spi_sd_card_spi_control_port_readdata, -- .readdata
mem_addr => mm_interconnect_0_spi_sd_card_spi_control_port_address, -- .address
read_n => mm_interconnect_0_spi_sd_card_spi_control_port_read_ports_inv, -- .read_n
spi_select => mm_interconnect_0_spi_sd_card_spi_control_port_chipselect, -- .chipselect
write_n => mm_interconnect_0_spi_sd_card_spi_control_port_write_ports_inv, -- .write_n
irq => irq_mapper_receiver2_irq, -- irq.irq
MISO => spi_sd_card_MISO, -- external.export
MOSI => spi_sd_card_MOSI, -- .export
SCLK => spi_sd_card_SCLK, -- .export
SS_n => spi_sd_card_SS_n -- .export
);
spi_stm32 : component wasca_spi_stm32
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset_n => rst_controller_001_reset_out_reset_ports_inv, -- reset.reset_n
data_from_cpu => mm_interconnect_0_spi_stm32_spi_control_port_writedata, -- spi_control_port.writedata
data_to_cpu => mm_interconnect_0_spi_stm32_spi_control_port_readdata, -- .readdata
mem_addr => mm_interconnect_0_spi_stm32_spi_control_port_address, -- .address
read_n => mm_interconnect_0_spi_stm32_spi_control_port_read_ports_inv, -- .read_n
spi_select => mm_interconnect_0_spi_stm32_spi_control_port_chipselect, -- .chipselect
write_n => mm_interconnect_0_spi_stm32_spi_control_port_write_ports_inv, -- .write_n
irq => irq_mapper_receiver3_irq, -- irq.irq
MISO => spi_stm32_MISO, -- external.export
MOSI => spi_stm32_MOSI, -- .export
SCLK => spi_stm32_SCLK, -- .export
SS_n => spi_stm32_SS_n -- .export
);
uart_0 : component wasca_uart_0
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset_n => rst_controller_001_reset_out_reset_ports_inv, -- reset.reset_n
address => mm_interconnect_0_uart_0_s1_address, -- s1.address
begintransfer => mm_interconnect_0_uart_0_s1_begintransfer, -- .begintransfer
chipselect => mm_interconnect_0_uart_0_s1_chipselect, -- .chipselect
read_n => mm_interconnect_0_uart_0_s1_read_ports_inv, -- .read_n
write_n => mm_interconnect_0_uart_0_s1_write_ports_inv, -- .write_n
writedata => mm_interconnect_0_uart_0_s1_writedata, -- .writedata
readdata => mm_interconnect_0_uart_0_s1_readdata, -- .readdata
dataavailable => open, -- .dataavailable
readyfordata => open, -- .readyfordata
rxd => uart_0_external_connection_rxd, -- external_connection.export
txd => uart_0_external_connection_txd, -- .export
irq => irq_mapper_receiver1_irq -- irq.irq
);
mm_interconnect_0 : component wasca_mm_interconnect_0
port map (
altpll_0_c0_clk => altpll_0_c0_clk, -- altpll_0_c0.clk
clk_0_clk_clk => clk_clk, -- clk_0_clk.clk
altpll_0_inclk_interface_reset_reset_bridge_in_reset_reset => rst_controller_reset_out_reset, -- altpll_0_inclk_interface_reset_reset_bridge_in_reset.reset
sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset => rst_controller_001_reset_out_reset, -- sega_saturn_abus_slave_0_reset_reset_bridge_in_reset.reset
nios2_gen2_0_data_master_address => nios2_gen2_0_data_master_address, -- nios2_gen2_0_data_master.address
nios2_gen2_0_data_master_waitrequest => nios2_gen2_0_data_master_waitrequest, -- .waitrequest
nios2_gen2_0_data_master_byteenable => nios2_gen2_0_data_master_byteenable, -- .byteenable
nios2_gen2_0_data_master_read => nios2_gen2_0_data_master_read, -- .read
nios2_gen2_0_data_master_readdata => nios2_gen2_0_data_master_readdata, -- .readdata
nios2_gen2_0_data_master_write => nios2_gen2_0_data_master_write, -- .write
nios2_gen2_0_data_master_writedata => nios2_gen2_0_data_master_writedata, -- .writedata
nios2_gen2_0_data_master_debugaccess => nios2_gen2_0_data_master_debugaccess, -- .debugaccess
nios2_gen2_0_instruction_master_address => nios2_gen2_0_instruction_master_address, -- nios2_gen2_0_instruction_master.address
nios2_gen2_0_instruction_master_waitrequest => nios2_gen2_0_instruction_master_waitrequest, -- .waitrequest
nios2_gen2_0_instruction_master_read => nios2_gen2_0_instruction_master_read, -- .read
nios2_gen2_0_instruction_master_readdata => nios2_gen2_0_instruction_master_readdata, -- .readdata
sega_saturn_abus_slave_0_avalon_master_address => sega_saturn_abus_slave_0_avalon_master_address, -- sega_saturn_abus_slave_0_avalon_master.address
sega_saturn_abus_slave_0_avalon_master_waitrequest => sega_saturn_abus_slave_0_avalon_master_waitrequest, -- .waitrequest
sega_saturn_abus_slave_0_avalon_master_burstcount(0) => sega_saturn_abus_slave_0_avalon_master_burstcount, -- .burstcount
sega_saturn_abus_slave_0_avalon_master_read => sega_saturn_abus_slave_0_avalon_master_read, -- .read
sega_saturn_abus_slave_0_avalon_master_readdata => sega_saturn_abus_slave_0_avalon_master_readdata, -- .readdata
sega_saturn_abus_slave_0_avalon_master_readdatavalid => sega_saturn_abus_slave_0_avalon_master_readdatavalid, -- .readdatavalid
sega_saturn_abus_slave_0_avalon_master_write => sega_saturn_abus_slave_0_avalon_master_write, -- .write
sega_saturn_abus_slave_0_avalon_master_writedata => sega_saturn_abus_slave_0_avalon_master_writedata, -- .writedata
altpll_0_pll_slave_address => mm_interconnect_0_altpll_0_pll_slave_address, -- altpll_0_pll_slave.address
altpll_0_pll_slave_write => mm_interconnect_0_altpll_0_pll_slave_write, -- .write
altpll_0_pll_slave_read => mm_interconnect_0_altpll_0_pll_slave_read, -- .read
altpll_0_pll_slave_readdata => mm_interconnect_0_altpll_0_pll_slave_readdata, -- .readdata
altpll_0_pll_slave_writedata => mm_interconnect_0_altpll_0_pll_slave_writedata, -- .writedata
audio_0_avalon_audio_slave_address => mm_interconnect_0_audio_0_avalon_audio_slave_address, -- audio_0_avalon_audio_slave.address
audio_0_avalon_audio_slave_write => mm_interconnect_0_audio_0_avalon_audio_slave_write, -- .write
audio_0_avalon_audio_slave_read => mm_interconnect_0_audio_0_avalon_audio_slave_read, -- .read
audio_0_avalon_audio_slave_readdata => mm_interconnect_0_audio_0_avalon_audio_slave_readdata, -- .readdata
audio_0_avalon_audio_slave_writedata => mm_interconnect_0_audio_0_avalon_audio_slave_writedata, -- .writedata
audio_0_avalon_audio_slave_chipselect => mm_interconnect_0_audio_0_avalon_audio_slave_chipselect, -- .chipselect
external_sdram_controller_s1_address => mm_interconnect_0_external_sdram_controller_s1_address, -- external_sdram_controller_s1.address
external_sdram_controller_s1_write => mm_interconnect_0_external_sdram_controller_s1_write, -- .write
external_sdram_controller_s1_read => mm_interconnect_0_external_sdram_controller_s1_read, -- .read
external_sdram_controller_s1_readdata => mm_interconnect_0_external_sdram_controller_s1_readdata, -- .readdata
external_sdram_controller_s1_writedata => mm_interconnect_0_external_sdram_controller_s1_writedata, -- .writedata
external_sdram_controller_s1_byteenable => mm_interconnect_0_external_sdram_controller_s1_byteenable, -- .byteenable
external_sdram_controller_s1_readdatavalid => mm_interconnect_0_external_sdram_controller_s1_readdatavalid, -- .readdatavalid
external_sdram_controller_s1_waitrequest => mm_interconnect_0_external_sdram_controller_s1_waitrequest, -- .waitrequest
external_sdram_controller_s1_chipselect => mm_interconnect_0_external_sdram_controller_s1_chipselect, -- .chipselect
nios2_gen2_0_debug_mem_slave_address => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address, -- nios2_gen2_0_debug_mem_slave.address
nios2_gen2_0_debug_mem_slave_write => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write, -- .write
nios2_gen2_0_debug_mem_slave_read => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read, -- .read
nios2_gen2_0_debug_mem_slave_readdata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata, -- .readdata
nios2_gen2_0_debug_mem_slave_writedata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata, -- .writedata
nios2_gen2_0_debug_mem_slave_byteenable => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable, -- .byteenable
nios2_gen2_0_debug_mem_slave_waitrequest => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest, -- .waitrequest
nios2_gen2_0_debug_mem_slave_debugaccess => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess, -- .debugaccess
onchip_flash_0_data_address => mm_interconnect_0_onchip_flash_0_data_address, -- onchip_flash_0_data.address
onchip_flash_0_data_read => mm_interconnect_0_onchip_flash_0_data_read, -- .read
onchip_flash_0_data_readdata => mm_interconnect_0_onchip_flash_0_data_readdata, -- .readdata
onchip_flash_0_data_burstcount => mm_interconnect_0_onchip_flash_0_data_burstcount, -- .burstcount
onchip_flash_0_data_readdatavalid => mm_interconnect_0_onchip_flash_0_data_readdatavalid, -- .readdatavalid
onchip_flash_0_data_waitrequest => mm_interconnect_0_onchip_flash_0_data_waitrequest, -- .waitrequest
onchip_memory2_0_s1_address => mm_interconnect_0_onchip_memory2_0_s1_address, -- onchip_memory2_0_s1.address
onchip_memory2_0_s1_write => mm_interconnect_0_onchip_memory2_0_s1_write, -- .write
onchip_memory2_0_s1_readdata => mm_interconnect_0_onchip_memory2_0_s1_readdata, -- .readdata
onchip_memory2_0_s1_writedata => mm_interconnect_0_onchip_memory2_0_s1_writedata, -- .writedata
onchip_memory2_0_s1_byteenable => mm_interconnect_0_onchip_memory2_0_s1_byteenable, -- .byteenable
onchip_memory2_0_s1_chipselect => mm_interconnect_0_onchip_memory2_0_s1_chipselect, -- .chipselect
onchip_memory2_0_s1_clken => mm_interconnect_0_onchip_memory2_0_s1_clken, -- .clken
sega_saturn_abus_slave_0_avalon_nios_address => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_address, -- sega_saturn_abus_slave_0_avalon_nios.address
sega_saturn_abus_slave_0_avalon_nios_write => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_write, -- .write
sega_saturn_abus_slave_0_avalon_nios_read => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_read, -- .read
sega_saturn_abus_slave_0_avalon_nios_readdata => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_readdata, -- .readdata
sega_saturn_abus_slave_0_avalon_nios_writedata => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_writedata, -- .writedata
sega_saturn_abus_slave_0_avalon_nios_burstcount => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_burstcount, -- .burstcount
sega_saturn_abus_slave_0_avalon_nios_readdatavalid => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_readdatavalid, -- .readdatavalid
sega_saturn_abus_slave_0_avalon_nios_waitrequest => mm_interconnect_0_sega_saturn_abus_slave_0_avalon_nios_waitrequest, -- .waitrequest
spi_sd_card_spi_control_port_address => mm_interconnect_0_spi_sd_card_spi_control_port_address, -- spi_sd_card_spi_control_port.address
spi_sd_card_spi_control_port_write => mm_interconnect_0_spi_sd_card_spi_control_port_write, -- .write
spi_sd_card_spi_control_port_read => mm_interconnect_0_spi_sd_card_spi_control_port_read, -- .read
spi_sd_card_spi_control_port_readdata => mm_interconnect_0_spi_sd_card_spi_control_port_readdata, -- .readdata
spi_sd_card_spi_control_port_writedata => mm_interconnect_0_spi_sd_card_spi_control_port_writedata, -- .writedata
spi_sd_card_spi_control_port_chipselect => mm_interconnect_0_spi_sd_card_spi_control_port_chipselect, -- .chipselect
spi_stm32_spi_control_port_address => mm_interconnect_0_spi_stm32_spi_control_port_address, -- spi_stm32_spi_control_port.address
spi_stm32_spi_control_port_write => mm_interconnect_0_spi_stm32_spi_control_port_write, -- .write
spi_stm32_spi_control_port_read => mm_interconnect_0_spi_stm32_spi_control_port_read, -- .read
spi_stm32_spi_control_port_readdata => mm_interconnect_0_spi_stm32_spi_control_port_readdata, -- .readdata
spi_stm32_spi_control_port_writedata => mm_interconnect_0_spi_stm32_spi_control_port_writedata, -- .writedata
spi_stm32_spi_control_port_chipselect => mm_interconnect_0_spi_stm32_spi_control_port_chipselect, -- .chipselect
uart_0_s1_address => mm_interconnect_0_uart_0_s1_address, -- uart_0_s1.address
uart_0_s1_write => mm_interconnect_0_uart_0_s1_write, -- .write
uart_0_s1_read => mm_interconnect_0_uart_0_s1_read, -- .read
uart_0_s1_readdata => mm_interconnect_0_uart_0_s1_readdata, -- .readdata
uart_0_s1_writedata => mm_interconnect_0_uart_0_s1_writedata, -- .writedata
uart_0_s1_begintransfer => mm_interconnect_0_uart_0_s1_begintransfer, -- .begintransfer
uart_0_s1_chipselect => mm_interconnect_0_uart_0_s1_chipselect -- .chipselect
);
irq_mapper : component wasca_irq_mapper
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
receiver0_irq => irq_mapper_receiver0_irq, -- receiver0.irq
receiver1_irq => irq_mapper_receiver1_irq, -- receiver1.irq
receiver2_irq => irq_mapper_receiver2_irq, -- receiver2.irq
receiver3_irq => irq_mapper_receiver3_irq, -- receiver3.irq
sender_irq => nios2_gen2_0_irq_irq -- sender.irq
);
rst_controller : component wasca_rst_controller
generic map (
NUM_RESET_INPUTS => 1,
OUTPUT_RESET_SYNC_EDGES => "deassert",
SYNC_DEPTH => 2,
RESET_REQUEST_PRESENT => 0,
RESET_REQ_WAIT_TIME => 1,
MIN_RST_ASSERTION_TIME => 3,
RESET_REQ_EARLY_DSRT_TIME => 1,
USE_RESET_REQUEST_IN0 => 0,
USE_RESET_REQUEST_IN1 => 0,
USE_RESET_REQUEST_IN2 => 0,
USE_RESET_REQUEST_IN3 => 0,
USE_RESET_REQUEST_IN4 => 0,
USE_RESET_REQUEST_IN5 => 0,
USE_RESET_REQUEST_IN6 => 0,
USE_RESET_REQUEST_IN7 => 0,
USE_RESET_REQUEST_IN8 => 0,
USE_RESET_REQUEST_IN9 => 0,
USE_RESET_REQUEST_IN10 => 0,
USE_RESET_REQUEST_IN11 => 0,
USE_RESET_REQUEST_IN12 => 0,
USE_RESET_REQUEST_IN13 => 0,
USE_RESET_REQUEST_IN14 => 0,
USE_RESET_REQUEST_IN15 => 0,
ADAPT_RESET_REQUEST => 0
)
port map (
reset_in0 => nios2_gen2_0_debug_reset_request_reset, -- reset_in0.reset
clk => clk_clk, -- clk.clk
reset_out => rst_controller_reset_out_reset, -- reset_out.reset
reset_req => open, -- (terminated)
reset_req_in0 => '0', -- (terminated)
reset_in1 => '0', -- (terminated)
reset_req_in1 => '0', -- (terminated)
reset_in2 => '0', -- (terminated)
reset_req_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_req_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_req_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_req_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_req_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_req_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_req_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_req_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_req_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_req_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_req_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_req_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_req_in14 => '0', -- (terminated)
reset_in15 => '0', -- (terminated)
reset_req_in15 => '0' -- (terminated)
);
rst_controller_001 : component wasca_rst_controller_001
generic map (
NUM_RESET_INPUTS => 1,
OUTPUT_RESET_SYNC_EDGES => "deassert",
SYNC_DEPTH => 2,
RESET_REQUEST_PRESENT => 1,
RESET_REQ_WAIT_TIME => 1,
MIN_RST_ASSERTION_TIME => 3,
RESET_REQ_EARLY_DSRT_TIME => 1,
USE_RESET_REQUEST_IN0 => 0,
USE_RESET_REQUEST_IN1 => 0,
USE_RESET_REQUEST_IN2 => 0,
USE_RESET_REQUEST_IN3 => 0,
USE_RESET_REQUEST_IN4 => 0,
USE_RESET_REQUEST_IN5 => 0,
USE_RESET_REQUEST_IN6 => 0,
USE_RESET_REQUEST_IN7 => 0,
USE_RESET_REQUEST_IN8 => 0,
USE_RESET_REQUEST_IN9 => 0,
USE_RESET_REQUEST_IN10 => 0,
USE_RESET_REQUEST_IN11 => 0,
USE_RESET_REQUEST_IN12 => 0,
USE_RESET_REQUEST_IN13 => 0,
USE_RESET_REQUEST_IN14 => 0,
USE_RESET_REQUEST_IN15 => 0,
ADAPT_RESET_REQUEST => 0
)
port map (
reset_in0 => nios2_gen2_0_debug_reset_request_reset, -- reset_in0.reset
clk => altpll_0_c0_clk, -- clk.clk
reset_out => rst_controller_001_reset_out_reset, -- reset_out.reset
reset_req => rst_controller_001_reset_out_reset_req, -- .reset_req
reset_req_in0 => '0', -- (terminated)
reset_in1 => '0', -- (terminated)
reset_req_in1 => '0', -- (terminated)
reset_in2 => '0', -- (terminated)
reset_req_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_req_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_req_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_req_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_req_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_req_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_req_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_req_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_req_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_req_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_req_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_req_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_req_in14 => '0', -- (terminated)
reset_in15 => '0', -- (terminated)
reset_req_in15 => '0' -- (terminated)
);
rst_controller_002 : component wasca_rst_controller
generic map (
NUM_RESET_INPUTS => 1,
OUTPUT_RESET_SYNC_EDGES => "both",
SYNC_DEPTH => 2,
RESET_REQUEST_PRESENT => 0,
RESET_REQ_WAIT_TIME => 1,
MIN_RST_ASSERTION_TIME => 3,
RESET_REQ_EARLY_DSRT_TIME => 1,
USE_RESET_REQUEST_IN0 => 0,
USE_RESET_REQUEST_IN1 => 0,
USE_RESET_REQUEST_IN2 => 0,
USE_RESET_REQUEST_IN3 => 0,
USE_RESET_REQUEST_IN4 => 0,
USE_RESET_REQUEST_IN5 => 0,
USE_RESET_REQUEST_IN6 => 0,
USE_RESET_REQUEST_IN7 => 0,
USE_RESET_REQUEST_IN8 => 0,
USE_RESET_REQUEST_IN9 => 0,
USE_RESET_REQUEST_IN10 => 0,
USE_RESET_REQUEST_IN11 => 0,
USE_RESET_REQUEST_IN12 => 0,
USE_RESET_REQUEST_IN13 => 0,
USE_RESET_REQUEST_IN14 => 0,
USE_RESET_REQUEST_IN15 => 0,
ADAPT_RESET_REQUEST => 0
)
port map (
reset_in0 => nios2_gen2_0_debug_reset_request_reset, -- reset_in0.reset
clk => altpll_0_c0_clk, -- clk.clk
reset_out => open, -- reset_out.reset
reset_req => open, -- (terminated)
reset_req_in0 => '0', -- (terminated)
reset_in1 => '0', -- (terminated)
reset_req_in1 => '0', -- (terminated)
reset_in2 => '0', -- (terminated)
reset_req_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_req_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_req_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_req_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_req_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_req_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_req_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_req_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_req_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_req_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_req_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_req_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_req_in14 => '0', -- (terminated)
reset_in15 => '0', -- (terminated)
reset_req_in15 => '0' -- (terminated)
);
mm_interconnect_0_external_sdram_controller_s1_read_ports_inv <= not mm_interconnect_0_external_sdram_controller_s1_read;
mm_interconnect_0_external_sdram_controller_s1_byteenable_ports_inv <= not mm_interconnect_0_external_sdram_controller_s1_byteenable;
mm_interconnect_0_external_sdram_controller_s1_write_ports_inv <= not mm_interconnect_0_external_sdram_controller_s1_write;
mm_interconnect_0_uart_0_s1_read_ports_inv <= not mm_interconnect_0_uart_0_s1_read;
mm_interconnect_0_uart_0_s1_write_ports_inv <= not mm_interconnect_0_uart_0_s1_write;
mm_interconnect_0_spi_sd_card_spi_control_port_read_ports_inv <= not mm_interconnect_0_spi_sd_card_spi_control_port_read;
mm_interconnect_0_spi_sd_card_spi_control_port_write_ports_inv <= not mm_interconnect_0_spi_sd_card_spi_control_port_write;
mm_interconnect_0_spi_stm32_spi_control_port_read_ports_inv <= not mm_interconnect_0_spi_stm32_spi_control_port_read;
mm_interconnect_0_spi_stm32_spi_control_port_write_ports_inv <= not mm_interconnect_0_spi_stm32_spi_control_port_write;
rst_controller_001_reset_out_reset_ports_inv <= not rst_controller_001_reset_out_reset;
clock_116_mhz_clk <= altpll_0_c0_clk;
end architecture rtl; -- of wasca
| gpl-2.0 | e5897f714a5486b25802438ae1f4ca98 | 0.463754 | 3.98509 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/leon3/proc3.vhd | 1 | 7,272 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: proc3
-- File: proc3.vhd
-- Author: Jiri Gaisler Gaisler Research
-- Description: LEON3 processor core with pipeline, mul/div & cache control
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.leon3.all;
use gaisler.libiu.all;
use gaisler.libcache.all;
use gaisler.arith.all;
--library fpu;
--use fpu.libfpu.all;
entity proc3 is
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := 0;
memtech : integer range 0 to NTECH := 0;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 15 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 2 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 2 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 0;
svt : integer range 0 to 1 := 0; -- single-vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0; -- support SMP systems
cached : integer := 0;
clk2x : integer := 0;
scantest : integer := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
holdn : out std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
rfi : out iregfile_in_type;
rfo : in iregfile_out_type;
crami : out cram_in_type;
cramo : in cram_out_type;
tbi : out tracebuf_in_type;
tbo : in tracebuf_out_type;
fpi : out fpc_in_type;
fpo : in fpc_out_type;
cpi : out fpc_in_type;
cpo : in fpc_out_type;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
hclk, sclk : in std_ulogic;
hclken : in std_ulogic;
hackVector : out std_logic_vector(7 downto 0)
);
end;
architecture rtl of proc3 is
constant IRFWT : integer := regfile_3p_write_through(memtech);
signal ici : icache_in_type;
signal ico : icache_out_type;
signal dci : dcache_in_type;
signal dco : dcache_out_type;
signal holdnx, pholdn : std_logic;
signal muli : mul32_in_type;
signal mulo : mul32_out_type;
signal divi : div32_in_type;
signal divo : div32_out_type;
begin
holdnx <= ico.hold and dco.hold and fpo.holdn; holdn <= holdnx;
pholdn <= fpo.holdn;
-- integer unit
iu0 : iu3
generic map (nwindows, isets, dsets, fpu, v8, cp, mac, dsu, nwp, pclow,
0, hindex, lddel, IRFWT, disas, tbuf, pwd, svt, rstaddr, smp, fabtech, clk2x)
port map (clk, rstn, holdnx, ici, ico, dci, dco, rfi, rfo, irqi, irqo,
dbgi, dbgo, muli, mulo, divi, divo, fpo, fpi, cpo, cpi, tbo, tbi, sclk, hackVector);
-- multiply and divide units
-- Actel FPGAs cannot use inferred mul due to bug in synplify 8.9 and 9.0
mgen : if v8 /= 0 generate
mgen2 : if (fabtech = axcel) or (fabtech = apa3) generate
mul0 : mul32 generic map (0, v8/16, (v8 mod 4)/2, mac)
port map (rstn, clk, holdnx, muli, mulo);
end generate;
mgen3 : if not ((fabtech = axcel) or (fabtech = apa3)) generate
mul0 : mul32 generic map (is_fpga(fabtech), v8/16, (v8 mod 4)/2, mac)
port map (rstn, clk, holdnx, muli, mulo);
end generate;
div0 : div32 port map (rstn, clk, holdnx, divi, divo);
end generate;
nomgen : if v8 = 0 generate
divo <= ('0', '0', "0000", zero32);
mulo <= ('0', '0', "0000", zero32&zero32);
end generate;
-- cache controller
m0 : if mmuen = 0 generate
c0 : cache
generic map (hindex, dsu, icen, irepl, isets, ilinesize, isetsize,
isetlock, dcen, drepl, dsets, dlinesize, dsetsize, dsetlock, dsnoop,
ilram, ilramsize, ilramstart, dlram, dlramsize, dlramstart, cached,
clk2x, memtech, scantest)
port map ( rstn, clk, ici, ico, dci, dco, ahbi, ahbo, ahbsi, ahbso, crami, cramo, pholdn, hclk, sclk, hclken);
end generate;
m1 : if mmuen = 1 generate
c0mmu : mmu_cache
generic map (hindex=>hindex, memtech=>memtech, dsu=>dsu, icen=>icen, irepl=>irepl,
isets=>isets, ilinesize=>ilinesize, isetsize=>isetsize, isetlock=>isetlock,
dcen=>dcen, drepl=>drepl, dsets=>dsets, dlinesize=>dlinesize, dsetsize=>dsetsize,
dsetlock=>dsetlock, dsnoop=>dsnoop, itlbnum=>itlbnum, dtlbnum=>dtlbnum,
tlb_type=>tlb_type, tlb_rep=>tlb_rep, cached => cached, clk2x => clk2x,
scantest => scantest)
port map ( rstn, clk, ici, ico, dci, dco,
ahbi, ahbo, ahbsi, ahbso, crami, cramo, pholdn, hclk, sclk, hclken);
end generate;
end;
| mit | 387f42dc954e1eb6e0cdd2728afd1996 | 0.580721 | 3.426956 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/techmap/maps/cpu_disas_net.vhd | 2 | 4,450 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: cpu_disas_net
-- File: cpu_disas_net.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: SPARC disassembler according to SPARC V8 manual
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library grlib;
use grlib.stdlib.all;
use grlib.sparc.all;
use grlib.sparc_disas.all;
-- pragma translate_on
entity cpu_disas_net is
port (
clk : in std_ulogic;
rstn : in std_ulogic;
dummy : out std_ulogic;
inst : in std_logic_vector(31 downto 0);
pc : in std_logic_vector(31 downto 2);
result: in std_logic_vector(31 downto 0);
index : in std_logic_vector(3 downto 0);
wreg : in std_ulogic;
annul : in std_ulogic;
holdn : in std_ulogic;
pv : in std_ulogic;
trap : in std_ulogic;
disas : in std_ulogic);
end;
architecture behav of cpu_disas_net is
begin
dummy <= '1';
-- pragma translate_off
trc : process(clk)
variable valid : boolean;
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable fpins, fpld : boolean;
variable iindex : integer;
begin
iindex := conv_integer(index);
op := inst(31 downto 30); op3 := inst(24 downto 19);
fpins := (op = FMT3) and ((op3 = FPOP1) or (op3 = FPOP2));
fpld := (op = LDST) and ((op3 = LDF) or (op3 = LDDF) or (op3 = LDFSR));
valid := (((not annul) and pv) = '1') and (not ((fpins or fpld) and (trap = '0')));
valid := valid and (holdn = '1');
if rising_edge(clk) and (rstn = '1') and (disas = '1') then
print_insn (iindex, pc(31 downto 2) & "00", inst,
result, valid, trap = '1', wreg = '1', false);
end if;
end process;
-- pragma translate_on
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library grlib;
use grlib.stdlib.all;
use grlib.sparc.all;
use grlib.sparc_disas.all;
-- pragma translate_on
entity fpu_disas_net is
port (
clk : in std_ulogic;
rstn : in std_ulogic;
dummy : out std_ulogic;
wr2inst : in std_logic_vector(31 downto 0);
wr2pc : in std_logic_vector(31 downto 2);
divinst : in std_logic_vector(31 downto 0);
divpc : in std_logic_vector(31 downto 2);
dbg_wrdata: in std_logic_vector(63 downto 0);
index : in std_logic_vector(3 downto 0);
dbg_wren : in std_logic_vector(1 downto 0);
resv : in std_ulogic;
ld : in std_ulogic;
rdwr : in std_ulogic;
ccwr : in std_ulogic;
rdd : in std_ulogic;
div_valid : in std_ulogic;
holdn : in std_ulogic;
disas : in std_ulogic);
end;
architecture behav of fpu_disas_net is
begin
dummy <= '1';
-- pragma translate_off
trc : process(clk)
variable valid : boolean;
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable fpins, fpld : boolean;
variable iindex : integer;
begin
iindex := conv_integer(index);
if rising_edge(clk) and (rstn = '1') and (disas /= '0') then
valid := ((((rdwr and not ld) or ccwr or (ld and resv)) and holdn) = '1');
print_fpinsn(0, wr2pc(31 downto 2) & "00", wr2inst, dbg_wrdata,
(rdd = '1'), valid, false, (dbg_wren /= "00"));
print_fpinsn(0, divpc(31 downto 2) & "00", divinst, dbg_wrdata,
(rdd = '1'), (div_valid and holdn) = '1', false, (dbg_wren /= "00"));
end if;
end process;
-- pragma translate_on
end;
| mit | a1d52a11003b5739228494c7bdb9daa6 | 0.607191 | 3.430995 | false | false | false | false |
lxp32/lxp32-cpu | rtl/lxp32_mul_seq.vhd | 2 | 1,633 | ---------------------------------------------------------------------
-- Sequential multiplier
--
-- Part of the LXP32 CPU
--
-- Copyright (c) 2016 by Alex I. Kuznetsov
--
-- The smallest possible multiplier. Implemented using
-- an accumulator. One multiplication takes 34 cycles.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity lxp32_mul_seq is
port(
clk_i: in std_logic;
rst_i: in std_logic;
ce_i: in std_logic;
op1_i: in std_logic_vector(31 downto 0);
op2_i: in std_logic_vector(31 downto 0);
ce_o: out std_logic;
result_o: out std_logic_vector(31 downto 0)
);
end entity;
architecture rtl of lxp32_mul_seq is
signal reg1: unsigned(op1_i'range);
signal reg2: unsigned(op2_i'range);
signal pp: unsigned(31 downto 0);
signal acc_sum: unsigned(31 downto 0);
signal cnt: integer range 0 to 32:=0;
signal ceo: std_logic:='0';
begin
pp<=reg1 when reg2(0)='1' else (others=>'0');
process (clk_i) is
begin
if rising_edge(clk_i) then
if rst_i='1' then
ceo<='0';
cnt<=0;
reg1<=(others=>'-');
reg2<=(others=>'-');
acc_sum<=(others=>'-');
else
if cnt=1 then
ceo<='1';
else
ceo<='0';
end if;
if ce_i='1' then
cnt<=32;
reg1<=unsigned(op1_i);
reg2<=unsigned(op2_i);
acc_sum<=(others=>'0');
else
acc_sum<=acc_sum+pp;
reg1<=reg1(reg1'high-1 downto 0)&"0";
reg2<="0"®2(reg2'high downto 1);
if cnt>0 then
cnt<=cnt-1;
end if;
end if;
end if;
end if;
end process;
result_o<=std_logic_vector(acc_sum);
ce_o<=ceo;
end architecture;
| mit | 140bb7906c793356a34b55e5f7b77661 | 0.577465 | 2.82526 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gleichmann/dac/dac_ahb.vhd | 2 | 4,647 | -----------------------------------------------------------------------------------------
-- SIGMA DELTA DAC WITH AHB INTERFACE
-----------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity dac_ahb is
generic (
length : integer := 16;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
dac_out : out std_ulogic
);
end;
architecture rtl of dac_ahb is
component sigdelt
generic (
c_dacin_length : positive);
port (
reset : in std_logic;
clock : in std_logic;
dac_in : in std_logic_vector(c_dacin_length-1 downto 0);
dac_out : out std_logic);
end component;
constant abits : integer := log2(kbytes) + 8;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg (VENDOR_GLEICHMANN, GLEICHMANN_DAC, 0, 0, 0),
-- 4 => ahb_membar(haddr, '1', '1', hmask), -- memory @ 0xA000_000
4 => ahb_iobar(haddr, hmask), -- I/O area @ 0xFFFA_0000
others => zero32);
type reg_type is
record
hwrite : std_ulogic;
hready : std_ulogic;
hsel : std_ulogic;
addr : std_logic_vector(abits+1 downto 0);
size : std_logic_vector(1 downto 0);
end record;
signal r, c : reg_type;
signal ramsel : std_ulogic;
signal write : std_logic_vector(3 downto 0);
signal ramaddr : std_logic_vector(abits-1 downto 0);
signal ramdata : std_logic_vector(31 downto 0);
type mem is array(0 to 15) of std_logic_vector(31 downto 0);
signal memarr : mem;
signal ra : std_logic_vector(3 downto 0);
signal rstp : std_ulogic; -- high-active reset
begin
rstp <= not rst;
comb : process (ahbsi, r, rst, ramdata)
variable bs : std_logic_vector(3 downto 0);
variable v : reg_type;
variable haddr : std_logic_vector(abits-1 downto 0);
begin
v := r; v.hready := '1'; bs := (others => '0');
if (r.hwrite or not r.hready) = '1' then haddr := r.addr(abits+1 downto 2);
else
haddr := ahbsi.haddr(abits+1 downto 2); bs := (others => '0');
end if;
if ahbsi.hready = '1' then
v.hsel := ahbsi.hsel(hindex) and ahbsi.htrans(1);
v.hwrite := ahbsi.hwrite and v.hsel;
v.addr := ahbsi.haddr(abits+1 downto 0);
v.size := ahbsi.hsize(1 downto 0);
end if;
if r.hwrite = '1' then
case r.size(1 downto 0) is
when "00" => bs (conv_integer(r.addr(1 downto 0))) := '1';
when "01" => bs := r.addr(1) & r.addr(1) & not (r.addr(1) & r.addr(1));
when others => bs := (others => '1');
end case;
v.hready := not (v.hsel and not ahbsi.hwrite);
v.hwrite := v.hwrite and v.hready;
end if;
if rst = '0' then v.hwrite := '0'; v.hready := '1'; end if;
write <= bs; ramsel <= v.hsel or r.hwrite; ahbso.hready <= r.hready;
ramaddr <= haddr; c <= v; ahbso.hrdata <= ramdata;
end process;
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hcache <= '1';
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
-- ra : for i in 0 to 3 generate
-- aram : syncram generic map (tech, abits, 8) port map (
-- clk, ramaddr, ahbsi.hwdata(i*8+7 downto i*8),
-- ramdata(i*8+7 downto i*8), ramsel, write(3-i));
-- end generate;
main : process(rst, clk)
begin
if rst = '0' then
memarr <= (others => (others => '0'));
ra <= (others => '0');
-- end if;
elsif rising_edge(clk) then
if r.hwrite = '1' then
memarr(conv_integer(ramaddr)) <= ahbsi.hwdata;
end if;
ra <= ramaddr(3 downto 0);
end if;
end process;
ramdata <= memarr(conv_integer(ra));
sigdelt_1 : sigdelt
generic map (
c_dacin_length => length)
port map (
reset => rstp,
clock => clk,
dac_in => memarr(0)(length-1 downto 0),
dac_out => dac_out);
reg : process (clk)
begin
if rising_edge(clk) then r <= c; end if;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("dac_ahb" & tost(hindex) &
": AHB DAC Module rev 0");
-- pragma translate_on
end;
| mit | 1cd95e3783de3d9851a63b9813385e3f | 0.527867 | 3.384559 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/opencores/ata/atahost_controller.vhd | 2 | 23,871 | ---------------------------------------------------------------------
---- ----
---- OpenCores IDE Controller ----
---- ATA/ATAPI-5 Host controller (OCIDEC-3) ----
---- ----
---- Author: Richard Herveille ----
---- [email protected] ----
---- www.asics.ws ----
---- ----
---------------------------------------------------------------------
---- ----
---- Copyright (C) 2001, 2002 Richard Herveille ----
---- [email protected] ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
---- ----
---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
---- POSSIBILITY OF SUCH DAMAGE. ----
---- ----
---------------------------------------------------------------------
-- rev.: 1.0 march 8th, 2001. Initial release
--
-- CVS Log
--
-- $Id: atahost_controller.vhd,v 1.1 2002/02/18 14:32:12 rherveille Exp $
--
-- $Date: 2002/02/18 14:32:12 $
-- $Revision: 1.1 $
-- $Author: rherveille $
-- $Locker: $
-- $State: Exp $
--
-- Change History:
-- $Log: atahost_controller.vhd,v $
-- Revision 1.1 2002/02/18 14:32:12 rherveille
-- renamed all files to 'atahost_***.vhd'
-- broke-up 'counter.vhd' into 'ud_cnt.vhd' and 'ro_cnt.vhd'
-- changed resD input to generic RESD in ud_cnt.vhd
-- changed ID input to generic ID in ro_cnt.vhd
-- changed core to reflect changes in ro_cnt.vhd
-- removed references to 'count' library
-- changed IO names
-- added disclaimer
-- added CVS log
-- moved registers and wishbone signals into 'atahost_wb_slave.vhd'
--
--
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
entity atahost_controller is
generic(
tech : integer := 0; -- fifo mem technology
fdepth : integer := 8; -- DMA fifo depth
TWIDTH : natural := 8; -- counter width
-- PIO mode 0 settings (@100MHz clock)
PIO_mode0_T1 : natural := 6; -- 70ns
PIO_mode0_T2 : natural := 28; -- 290ns
PIO_mode0_T4 : natural := 2; -- 30ns
PIO_mode0_Teoc : natural := 23; -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240
-- Multiword DMA mode 0 settings (@100MHz clock)
DMA_mode0_Tm : natural := 4; -- 50ns
DMA_mode0_Td : natural := 21; -- 215ns
DMA_mode0_Teoc : natural := 21 -- 215ns ==> T0 - Td - Tm = 480 - 50 - 215 = 215
);
port(
clk : in std_logic; -- master clock in
nReset : in std_logic := '1'; -- asynchronous active low reset
rst : in std_logic := '0'; -- synchronous active high reset
irq : out std_logic; -- interrupt request signal
-- control / registers
IDEctrl_IDEen,
IDEctrl_rst,
IDEctrl_ppen,
IDEctrl_FATR0,
IDEctrl_FATR1 : in std_logic; -- control register settings
a : in std_logic_vector(3 downto 0); -- address input
d : in std_logic_vector(31 downto 0); -- data input
we : in std_logic; -- write enable input '1'=write, '0'=read
-- PIO registers
PIO_cmdport_T1,
PIO_cmdport_T2,
PIO_cmdport_T4,
PIO_cmdport_Teoc : in std_logic_vector(7 downto 0);
PIO_cmdport_IORDYen : in std_logic; -- PIO compatible timing settings
PIO_dport0_T1,
PIO_dport0_T2,
PIO_dport0_T4,
PIO_dport0_Teoc : in std_logic_vector(7 downto 0);
PIO_dport0_IORDYen : in std_logic; -- PIO data-port device0 timing settings
PIO_dport1_T1,
PIO_dport1_T2,
PIO_dport1_T4,
PIO_dport1_Teoc : in std_logic_vector(7 downto 0);
PIO_dport1_IORDYen : in std_logic; -- PIO data-port device1 timing settings
PIOsel : in std_logic; -- PIO controller select
PIOack : out std_logic; -- PIO controller acknowledge
PIOq : out std_logic_vector(15 downto 0); -- PIO data out
PIOtip : out std_logic; -- PIO transfer in progress
PIOpp_full : out std_logic; -- PIO Write PingPong full
-- DMA registers
DMA_dev0_Td,
DMA_dev0_Tm,
DMA_dev0_Teoc : in std_logic_vector(7 downto 0); -- DMA timing settings for device0
DMA_dev1_Td,
DMA_dev1_Tm,
DMA_dev1_Teoc : in std_logic_vector(7 downto 0); -- DMA timing settings for device1
DMActrl_DMAen,
DMActrl_dir,
DMActrl_Bytesw, --Jagre 2006-12-04 byte swap ATA data
DMActrl_BeLeC0,
DMActrl_BeLeC1 : in std_logic; -- DMA settings
DMAsel : in std_logic; -- DMA controller select
DMAack : out std_logic; -- DMA controller acknowledge
DMAq : out std_logic_vector(31 downto 0); -- DMA data out
DMAtip_out : out std_logic; -- DMA transfer in progress --Erik Jagre 2006-11-15
DMA_dmarq : out std_logic; -- Synchronized ATA DMARQ line
force_rdy : in std_logic; -- DMA transmit fifo filled up partly --Erik Jagre 2006-10-31
fifo_rdy : out std_logic; -- DMA transmit fifo filled up --Erik Jagre 2006-10-30
DMARxEmpty : out std_logic; -- DMA receive buffer empty
DMARxFull : out std_logic; -- DMA receive fifo full Erik Jagre 2006-10-31
DMA_req : out std_logic; -- DMA request to external DMA engine
DMA_ack : in std_logic; -- DMA acknowledge from external DMA engine
BM_en : in std_logic; -- Bus mater enabled, for DMA reset Erik Jagre 2006-10-24
-- ATA signals
RESETn : out std_logic;
DDi : in std_logic_vector(15 downto 0);
DDo : out std_logic_vector(15 downto 0);
DDoe : out std_logic;
DA : out std_logic_vector(2 downto 0) := "000";
CS0n : out std_logic;
CS1n : out std_logic;
DMARQ : in std_logic;
DMACKn : out std_logic;
DIORn : out std_logic;
DIOWn : out std_logic;
IORDY : in std_logic;
INTRQ : in std_logic
);
end entity atahost_controller;
architecture structural of atahost_controller is
--
-- component declarations
--
component atahost_pio_controller is
generic(
TWIDTH : natural := 8; -- counter width
-- PIO mode 0 settings (@100MHz clock)
PIO_mode0_T1 : natural := 6; -- 70ns
PIO_mode0_T2 : natural := 28; -- 290ns
PIO_mode0_T4 : natural := 2; -- 30ns
PIO_mode0_Teoc : natural := 23 -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240
);
port(
clk : in std_logic; -- master clock in
nReset : in std_logic := '1'; -- asynchronous active low reset
rst : in std_logic := '0'; -- synchronous active high reset
-- control / registers
IDEctrl_IDEen,
IDEctrl_ppen,
IDEctrl_FATR0,
IDEctrl_FATR1 : in std_logic;
-- PIO registers
cmdport_T1,
cmdport_T2,
cmdport_T4,
cmdport_Teoc : in std_logic_vector(7 downto 0);
cmdport_IORDYen : in std_logic; -- PIO command port / non-fast timing
dport0_T1,
dport0_T2,
dport0_T4,
dport0_Teoc : in std_logic_vector(7 downto 0);
dport0_IORDYen : in std_logic; -- PIO mode data-port / fast timing device 0
dport1_T1,
dport1_T2,
dport1_T4,
dport1_Teoc : in std_logic_vector(7 downto 0);
dport1_IORDYen : in std_logic; -- PIO mode data-port / fast timing device 1
sel : in std_logic; -- PIO controller selected
ack : out std_logic; -- PIO controller acknowledge
a : in std_logic_vector(3 downto 0); -- lower address bits
we : in std_logic; -- write enable input
d : in std_logic_vector(15 downto 0);
q : out std_logic_vector(15 downto 0);
PIOreq : out std_logic; -- PIO transfer request
PPFull : out std_logic; -- PIO Write PingPong Full
go : in std_logic; -- start PIO transfer
done : out std_logic; -- done with PIO transfer
PIOa : out std_logic_vector(3 downto 0); -- PIO address, address lines towards ATA devices
PIOd : out std_logic_vector(15 downto 0); -- PIO data, data towards ATA devices
SelDev : out std_logic; -- Selected Device, Dev-bit in ATA Device/Head register
DDi : in std_logic_vector(15 downto 0);
DDoe : out std_logic;
DIOR : out std_logic;
DIOW : out std_logic;
IORDY : in std_logic
);
end component atahost_pio_controller;
component atahost_dma_actrl is
generic(
tech : integer := 0; -- fifo mem technology
fdepth : integer := 8; -- DMA fifo depth
TWIDTH : natural := 8; -- counter width
-- DMA mode 0 settings (@100MHz clock)
DMA_mode0_Tm : natural := 4; -- 50ns
DMA_mode0_Td : natural := 21; -- 215ns
DMA_mode0_Teoc : natural := 21 -- 215ns ==> T0 - Td - Tm = 480 - 50 - 215 = 215
);
port(
clk : in std_logic; -- master clock
nReset : in std_logic; -- asynchronous active low reset
rst : in std_logic; -- synchronous active high reset
IDEctrl_rst : in std_logic; -- IDE control register bit0, 'rst'
sel : in std_logic; -- DMA buffers selected
we : in std_logic; -- write enable input
ack : out std_logic; -- acknowledge output
dev0_Tm,
dev0_Td,
dev0_Teoc : in std_logic_vector(7 downto 0); -- DMA mode timing device 0
dev1_Tm,
dev1_Td,
dev1_Teoc : in std_logic_vector(7 downto 0); -- DMA mode timing device 1
DMActrl_DMAen,
DMActrl_dir,
DMActrl_Bytesw,
DMActrl_BeLeC0,
DMActrl_BeLeC1 : in std_logic; -- control register settings
TxD : in std_logic_vector(31 downto 0); -- DMA transmit data
TxFull : out std_logic; -- DMA transmit buffer full
TxEmpty : out std_logic;
RxQ : out std_logic_vector(31 downto 0); -- DMA receive data
RxEmpty : out std_logic; -- DMA receive buffer empty
RxFull : out std_logic; -- DMA receive buffer full
DMA_req : out std_logic; -- DMA request to external DMA engine
DMA_ack : in std_logic; -- DMA acknowledge from external DMA engine
DMARQ : in std_logic; -- ATA devices request DMA transfer
SelDev : in std_logic; -- Selected device
Go : in std_logic; -- Start transfer sequence
Done : out std_logic; -- Transfer sequence done
DDi : in std_logic_vector(15 downto 0); -- Data from ATA DD bus
DDo : out std_logic_vector(15 downto 0); -- Data towards ATA DD bus
DIOR,
DIOW : out std_logic
);
end component atahost_dma_actrl;
type reg_type is record
force_rdy : std_logic;
fifo_rdy : std_logic;
s_DMATxEmpty : std_logic;
s_DMATxFull : std_logic;
s_DMARxEmpty : std_logic;
s_DMARxFull : std_logic;
end record;
constant RESET_VECTOR : reg_type := ('0','0','0','0','0','0');
signal r,ri : reg_type;
--
-- signals
--
signal SelDev : std_logic; -- selected device
signal s_DMARxFull : std_logic; -- DMA receive buffer full
-- PIO / DMA signals
signal PIOgo, DMAgo : std_logic :='0'; -- start PIO / DMA timing controller
signal PIOdone, DMAdone : std_logic :='0'; -- PIO / DMA timing controller done
-- PIO signals
signal PIOdior, PIOdiow : std_logic;
signal PIOoe : std_logic;
-- PIO pingpong signals
signal PIOd : std_logic_vector(15 downto 0);
signal PIOa : std_logic_vector(3 downto 0):="0000";
signal PIOreq : std_logic;
-- DMA signals
signal DMAd : std_logic_vector(15 downto 0);
signal DMAtip, s_fifo_rdy, s_DMARxEmpty, s_DMATxFull,s_DMATxEmpty, DMAdior, DMAdiow, s_DMArst: std_logic; --Erik Jagre 2006-10-24 new s_DMArst signal
-- synchronized ATA inputs
signal sDMARQ, sIORDY, iPIOtip, iDMAtip_out : std_logic;
begin
--
-- synchronize incoming signals
--
synch_incoming: block
signal cDMARQ : std_logic; -- capture DMARQ
signal cIORDY : std_logic; -- capture IORDY
signal cINTRQ : std_logic; -- capture INTRQ
begin
process(clk)
begin
if (clk'event and clk = '1') then
cDMARQ <= DMARQ;
cIORDY <= IORDY;
cINTRQ <= INTRQ;
sDMARQ <= cDMARQ;
sIORDY <= cIORDY;
irq <= cINTRQ;
end if;
end process;
DMA_dmarq <= sDMARQ;
end block synch_incoming;
--
-- generate ATA signals
--
gen_ata_sigs: block
signal iDDo : std_logic_vector(15 downto 0);
begin
-- generate registers for ATA signals
gen_regs: process(clk, nReset)
begin
if (nReset = '0') then
RESETn <= '0';
DIORn <= '1';
DIOWn <= '1';
DA <= (others => '0');
CS0n <= '1';
CS1n <= '1';
DDo <= (others => '0');
DDoe <= '0';
DMACKn <= '1';
elsif (clk'event and clk = '1') then
if (rst = '1') then
RESETn <= '0';
DIORn <= '1';
DIOWn <= '1';
DA <= (others => '0');
CS0n <= '1';
CS1n <= '1';
DDo <= (others => '0');
DDoe <= '0';
DMACKn <= '1';
else
RESETn <= not IDEctrl_rst;
DA <= PIOa(2 downto 0);
CS0n <= not (not PIOa(3) and iPIOtip); -- CS0 asserted when A(3) = '0', negate during DMA transfers
CS1n <= not ( PIOa(3) and iPIOtip); -- CS1 asserted when A(3) = '1', negate during DMA transfers
if (iPIOtip = '1') then
DDo <= PIOd;
DDoe <= PIOoe;
DIORn <= not PIOdior;
DIOWn <= not PIOdiow;
else
DDo <= DMAd;
DDoe <= DMActrl_dir and DMAtip;
DIORn <= not DMAdior;
DIOWn <= not DMAdiow;
end if;
DMACKn <= not DMAtip;
end if;
end if;
end process gen_regs;
end block gen_ata_sigs;
--
-- generate bus controller statemachine
--
statemachine: block
type states is (idle, PIO_state, DMA_state);
signal nxt_state, c_state : states; -- next_state, current_state
signal iPIOgo, iDMAgo : std_logic :='0';
begin
gen_fifo_rdy : process(r,s_DMATxEmpty,s_DMATxFull,s_DMARxFull,s_DMARxEmpty,force_rdy,s_DMArst,DMActrl_dir) --Erik Jagre 2006-10-30
variable v : reg_type;
begin
v:=r;
v.s_DMATxFull:=s_DMATxFull;
v.s_DMATxEmpty:=s_DMATxEmpty;
v.s_DMARxFull:=s_DMARxFull;
v.s_DMARxEmpty:=s_DMARxEmpty;
v.force_rdy:=force_rdy;
case DMActrl_dir is
when '1' => --Tx action mem_to_ata
if (r.s_DMATxFull='0' and s_DMATxFull='1') or
(r.force_rdy='0' and force_rdy='1') then
v.fifo_rdy:='1';
elsif (r.s_DMATxEmpty='0' and s_DMATxEmpty='1') then
v.fifo_rdy:='0';
else
v.fifo_rdy:=r.fifo_rdy;
end if;
if s_DMArst='1' then
v.fifo_rdy:='0';
end if;
when '0' => --Rx action ata_to_mem
if (s_DMARxEmpty='1') or --r.s_DMARxEmpty='0' and Jagre 2006-12-04
(r.force_rdy='0' and force_rdy='1') then --Erik Jagre 2006-11-07
v.fifo_rdy:='1';
elsif (r.s_DMARxFull='0' and s_DMARxFull='1') then
v.fifo_rdy:='0';
else
v.fifo_rdy:=r.fifo_rdy;
end if;
if s_DMArst='1' then
v.fifo_rdy:='1';
end if;
when others =>
v.fifo_rdy:=r.fifo_rdy;
end case;
ri<=v;
s_fifo_rdy<=v.fifo_rdy; --Jagre 2006-12-04
fifo_rdy<=r.fifo_rdy;
end process gen_fifo_rdy;
-- generate next state decoder + output decoder
-- gen_nxt_state: process(c_state, DMActrl_DMAen, DMActrl_dir, PIOreq, sDMARQ, s_fifo_rdy, s_DMARxFull, PIOdone, DMAdone) --Erik Jagre 2006-10-30
gen_nxt_state: process(c_state, DMActrl_DMAen, PIOreq, sDMARQ, s_fifo_rdy, PIOdone, DMAdone) --Erik Jagre 2007-02-08
begin
nxt_state <= c_state; -- initialy stay in current state
iPIOgo <= '0';
iDMAgo <= '0';
case c_state is
-- idle
when idle =>
-- DMA transfer pending ?
if ( (sDMARQ = '1') and (DMActrl_DMAen = '1') ) then
if (s_fifo_rdy='1') then --Erik Jagre 2006-10-30
nxt_state <= DMA_state; -- DMA transfer
iDMAgo <= '1'; -- start DMA timing controller
end if;
-- PIO transfer pending ?
elsif (PIOreq = '1') then
nxt_state <= PIO_state; -- PIO transfer
iPIOgo <= '1';
end if;
-- PIO transfer
when PIO_state =>
if (PIOdone = '1') then
nxt_state <= idle;
end if;
-- DMA transfer
when DMA_state =>
if (DMAdone = '1') then
nxt_state <= idle;
end if;
when others =>
nxt_state <= idle; -- go to idle state
end case;
end process gen_nxt_state;
-- generate registers
gen_regs: process(clk, nReset)
begin
if (nReset = '0') then
c_state <= idle;
PIOgo <= '0';
DMAgo <= '0';
r<=RESET_VECTOR;
elsif (clk'event and clk = '1') then
if (rst = '1') then
c_state <= idle;
PIOgo <= '0';
DMAgo <= '0';
r<=RESET_VECTOR;
else
c_state <= nxt_state;
PIOgo <= iPIOgo;
DMAgo <= iDMAgo;
r<=ri;
end if;
end if;
end process gen_regs;
-- generate PIOtip / DMAtip
gen_tip: process(clk, nReset)
begin
if (nReset = '0') then
iPIOtip <= '0';
DMAtip <= '0';
iDMAtip_out <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1') then
iPIOtip <= '0';
DMAtip <= '0';
iDMAtip_out <= '0';
else
iPIOtip <= iPIOgo or (iPIOtip and not PIOdone);
DMAtip <= iDMAgo or (DMAtip and not ((DMAdone and DMActrl_dir) or (DMAdone and not sDMARQ and not DMActrl_dir)) );
iDMAtip_out <= iDMAgo or (not s_DMATxEmpty) or (iDMAtip_out and not ((DMAdone and DMActrl_dir) or (DMAdone and not sDMARQ and not DMActrl_dir)) );
end if;
end if;
end process gen_tip;
end block statemachine;
PIOtip <= iPIOtip; DMAtip_out <= iDMAtip_out;
DMARxEmpty <= s_DMARxEmpty; --Erik Jagre 2006-11-01
DMARxFull <= s_DMARxFull; --Erik Jagre 2006-10-31
s_DMArst <=IDEctrl_rst or (not BM_en); --reset DMA controller when BM not active
--
-- Hookup PIO controller
--
PIO_control: atahost_pio_controller
generic map(
TWIDTH => TWIDTH,
PIO_mode0_T1 => PIO_mode0_T1,
PIO_mode0_T2 => PIO_mode0_T2,
PIO_mode0_T4 => PIO_mode0_T4,
PIO_mode0_Teoc => PIO_mode0_Teoc
)
port map(
clk => clk,
nReset => nReset,
rst => rst,
IDEctrl_IDEen => IDEctrl_IDEen,
IDEctrl_ppen => IDEctrl_ppen,
IDEctrl_FATR0 => IDEctrl_FATR0,
IDEctrl_FATR1 => IDEctrl_FATR1,
cmdport_T1 => PIO_cmdport_T1,
cmdport_T2 => PIO_cmdport_T2,
cmdport_T4 => PIO_cmdport_T4,
cmdport_Teoc => PIO_cmdport_Teoc,
cmdport_IORDYen => PIO_cmdport_IORDYen,
dport0_T1 => PIO_dport0_T1,
dport0_T2 => PIO_dport0_T2,
dport0_T4 => PIO_dport0_T4,
dport0_Teoc => PIO_dport0_Teoc,
dport0_IORDYen => PIO_dport0_IORDYen,
dport1_T1 => PIO_dport1_T1,
dport1_T2 => PIO_dport1_T2,
dport1_T4 => PIO_dport1_T4,
dport1_Teoc => PIO_dport1_Teoc,
dport1_IORDYen => PIO_dport1_IORDYen,
sel => PIOsel,
ack => PIOack,
a => a,
we => we,
d => d(15 downto 0),
q => PIOq,
PIOreq => PIOreq,
PPFull => PIOpp_full,
go => PIOgo,
done => PIOdone,
PIOa => PIOa,
PIOd => PIOd,
SelDev => SelDev,
DDi => DDi,
DDoe => PIOoe,
DIOR => PIOdior,
DIOW => PIOdiow,
IORDY => sIORDY
);
--
-- Hookup DMA access controller
--
DMA_control: atahost_dma_actrl
generic map(
tech => tech,
fdepth => fdepth,
TWIDTH => TWIDTH,
DMA_mode0_Tm => DMA_mode0_Tm,
DMA_mode0_Td => DMA_mode0_Td,
DMA_mode0_Teoc => DMA_mode0_Teoc
)
port map(
clk => clk,
nReset => nReset,
rst => rst,
IDEctrl_rst => s_DMArst,--IDEctrl_rst,
DMActrl_DMAen => DMActrl_DMAen,
DMActrl_dir => DMActrl_dir,
DMActrl_Bytesw => DMActrl_Bytesw,
DMActrl_BeLeC0 => DMActrl_BeLeC0,
DMActrl_BeLeC1 => DMActrl_BeLeC1,
dev0_Td => DMA_dev0_Td,
dev0_Tm => DMA_dev0_Tm,
dev0_Teoc => DMA_dev0_Teoc,
dev1_Td => DMA_dev1_Td,
dev1_Tm => DMA_dev1_Tm,
dev1_Teoc => DMA_dev1_Teoc,
sel => DMAsel,
ack => DMAack,
we => we,
TxD => d,
TxFull => s_DMATxFull,
TxEmpty => s_DMATxEmpty,
RxQ => DMAq,
RxFull => s_DMARxFull,
RxEmpty => s_DMARxEmpty,
DMA_req => DMA_req,
DMA_ack => DMA_ack,
SelDev => SelDev,
Go => DMAgo,
Done => DMAdone,
DDi => DDi,
DDo => DMAd,
DIOR => DMAdior,
DIOW => DMAdiow,
DMARQ => sDMARQ
);
end architecture structural;
| mit | d66e3bc6089c91850d0a6ea3885fa5d6 | 0.515228 | 3.317721 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/opencores/ata/atahost_dma_tctrl.vhd | 2 | 8,080 | ---------------------------------------------------------------------
---- ----
---- OpenCores IDE Controller ----
---- DMA (single- and multiword) mode timing statemachine ----
---- ----
---- Author: Richard Herveille ----
---- [email protected] ----
---- www.asics.ws ----
---- ----
---------------------------------------------------------------------
---- ----
---- Copyright (C) 2001, 2002 Richard Herveille ----
---- [email protected] ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
---- ----
---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
---- POSSIBILITY OF SUCH DAMAGE. ----
---- ----
---------------------------------------------------------------------
-- rev.: 1.0 march 7th, 2001. Initial release
--
-- CVS Log
--
-- $Id: atahost_dma_tctrl.vhd,v 1.1 2002/02/18 14:32:12 rherveille Exp $
--
-- $Date: 2002/02/18 14:32:12 $
-- $Revision: 1.1 $
-- $Author: rherveille $
-- $Locker: $
-- $State: Exp $
--
-- Change History:
-- $Log: atahost_dma_tctrl.vhd,v $
-- Revision 1.1 2002/02/18 14:32:12 rherveille
-- renamed all files to 'atahost_***.vhd'
-- broke-up 'counter.vhd' into 'ud_cnt.vhd' and 'ro_cnt.vhd'
-- changed resD input to generic RESD in ud_cnt.vhd
-- changed ID input to generic ID in ro_cnt.vhd
-- changed core to reflect changes in ro_cnt.vhd
-- removed references to 'count' library
-- changed IO names
-- added disclaimer
-- added CVS log
-- moved registers and wishbone signals into 'atahost_wb_slave.vhd'
--
--
--
---------------------------
-- DMA Timing Controller --
---------------------------
--
--
-- Timing DMA mode transfers
----------------------------------------------
-- T0: cycle time
-- Td: DIOR-/DIOW- asserted pulse width
-- Te: DIOR- data access
-- Tf: DIOR- data hold
-- Tg: DIOR-/DIOW- data setup
-- Th: DIOW- data hold
-- Ti: DMACK to DIOR-/DIOW- setup
-- Tj: DIOR-/DIOW- to DMACK hold
-- Tkr: DIOR- negated pulse width
-- Tkw: DIOW- negated pulse width
-- Tm: CS(1:0) valid to DIOR-/DIOW-
-- Tn: CS(1:0) hold
--
--
-- Transfer sequence
----------------------------------
-- 1) wait for Tm
-- 2) assert DIOR-/DIOW-
-- when write action present data (Timing spec. Tg always honored)
-- output enable is controlled by DMA-direction and DMACK-
-- 3) wait for Td
-- 4) negate DIOR-/DIOW-
-- when read action, latch data
-- 5) wait for Teoc (T0 - Td - Tm) or Tkw, whichever is greater
-- Th, Tj, Tk, Tn always honored
-- 6) start new cycle
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity atahost_dma_tctrl is
generic(
TWIDTH : natural := 8; -- counter width
-- DMA mode 0 settings (@100MHz clock)
DMA_mode0_Tm : natural := 4; -- 50ns
DMA_mode0_Td : natural := 21; -- 215ns
DMA_mode0_Teoc : natural := 21 -- 215ns ==> T0 - Td - Tm = 480 - 50 - 215 = 215
);
port(
clk : in std_logic; -- master clock
nReset : in std_logic; -- asynchronous active low reset
rst : in std_logic; -- synchronous active high reset
-- timing register settings
Tm : in std_logic_vector(TWIDTH -1 downto 0); -- Tm time (in clk-ticks)
Td : in std_logic_vector(TWIDTH -1 downto 0); -- Td time (in clk-ticks)
Teoc : in std_logic_vector(TWIDTH -1 downto 0); -- end of cycle time
-- control signals
go : in std_logic; -- DMA controller selected (strobe signal)
we : in std_logic; -- DMA direction '1' = write, '0' = read
-- return signals
done : out std_logic; -- finished cycle
dstrb : out std_logic; -- data strobe
-- ATA signals
DIOR, -- IOread signal, active high
DIOW : out std_logic -- IOwrite signal, active high
);
end entity atahost_dma_tctrl;
architecture structural of atahost_dma_tctrl is
component ro_cnt is
generic(
SIZE : natural := 8;
UD : integer := 0; -- default count down
ID : natural := 0 -- initial data after reset
);
port(
clk : in std_logic; -- master clock
nReset : in std_logic := '1'; -- asynchronous active low reset
rst : in std_logic := '0'; -- synchronous active high reset
cnt_en : in std_logic := '1'; -- count enable
go : in std_logic; -- load counter and start sequence
done : out std_logic; -- done counting
d : in std_logic_vector(SIZE -1 downto 0); -- load counter value
q : out std_logic_vector(SIZE -1 downto 0) -- current counter value
);
end component ro_cnt;
signal Tmdone, Tddone : std_logic;
signal iDIOR, iDIOW : std_logic;
begin
DIOR <= iDIOR; DIOW <= iDIOW;
-- 1) hookup Tm counter
tm_cnt : ro_cnt
generic map (
SIZE => TWIDTH,
UD => 0,
ID => DMA_mode0_Tm
)
port map (
clk => clk,
nReset => nReset,
rst => rst,
go => go,
D => Tm,
done => Tmdone
);
-- 2) set (and reset) DIOR-/DIOW-
T2proc: process(clk, nReset)
begin
if (nReset = '0') then
iDIOR <= '0';
iDIOW <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1') then
iDIOR <= '0';
iDIOW <= '0';
else
iDIOR <= (not we and Tmdone) or (iDIOR and not Tddone);
iDIOW <= ( we and Tmdone) or (iDIOW and not Tddone);
end if;
end if;
end process T2proc;
-- 3) hookup Td counter
td_cnt : ro_cnt
generic map (
SIZE => TWIDTH,
UD => 0,
ID => DMA_mode0_Td
)
port map (
clk => clk,
nReset => nReset,
rst => rst,
go => Tmdone,
D => Td,
done => Tddone
);
-- generate data_strobe
gen_dstrb: process(clk)
begin
if (clk'event and clk = '1') then
dstrb <= Tddone; -- capture data at rising edge of DIOR-
end if;
end process gen_dstrb;
-- 4) negate DIOR-/DIOW- when Tddone
-- 5) hookup end_of_cycle counter
eoc_cnt : ro_cnt
generic map (
SIZE => TWIDTH,
UD => 0,
ID => DMA_mode0_Teoc
)
port map (
clk => clk,
nReset => nReset,
rst => rst,
go => Tddone,
D => Teoc,
done => done
);
end architecture structural;
| mit | 25c56c157169c6b0621322f42829b7f5 | 0.493317 | 3.667726 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/opencores/i2c/i2c_master_byte_ctrl.vhd | 2 | 13,094 | ---------------------------------------------------------------------
---- ----
---- WISHBONE revB2 compl. I2C Master Core; byte-controller ----
---- ----
---- ----
---- Author: Richard Herveille ----
---- [email protected] ----
---- www.asics.ws ----
---- ----
---- Downloaded from: http://www.opencores.org/projects/i2c/ ----
---- ----
---------------------------------------------------------------------
---- ----
---- Copyright (C) 2000 Richard Herveille ----
---- [email protected] ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
---- ----
---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
---- POSSIBILITY OF SUCH DAMAGE. ----
---- ----
---------------------------------------------------------------------
-- CVS Log
--
-- $Id: i2c_master_byte_ctrl.vhd,v 1.5 2004/02/18 11:41:48 rherveille Exp $
--
-- $Date: 2004/02/18 11:41:48 $
-- $Revision: 1.5 $
-- $Author: rherveille $
-- $Locker: $
-- $State: Exp $
--
-- Change History:
-- $Log: i2c_master_byte_ctrl.vhd,v $
-- Revision 1.5 2004/02/18 11:41:48 rherveille
-- Fixed a potential bug in the statemachine. During a 'stop' 2 cmd_ack signals were generated. Possibly canceling a new start command.
--
-- Revision 1.4 2003/08/09 07:01:13 rherveille
-- Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
-- Fixed a potential bug in the byte controller's host-acknowledge generation.
--
-- Revision 1.3 2002/12/26 16:05:47 rherveille
-- Core is now a Multimaster I2C controller.
--
-- Revision 1.2 2002/11/30 22:24:37 rherveille
-- Cleaned up code
--
-- Revision 1.1 2001/11/05 12:02:33 rherveille
-- Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
-- Code updated, is now up-to-date to doc. rev.0.4.
-- Added headers.
--
-- Modified by Jan Andersson ([email protected]). Changed std_logic_arith to numeric_std.
--
------------------------------------------
-- Byte controller section
------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
entity i2c_master_byte_ctrl is
port (
clk : in std_logic;
rst : in std_logic; -- synchronous active high reset (WISHBONE compatible)
nReset : in std_logic; -- asynchornous active low reset (FPGA compatible)
ena : in std_logic; -- core enable signal
clk_cnt : in std_logic_vector(15 downto 0); -- 4x SCL
-- input signals
start,
stop,
read,
write,
ack_in : std_logic;
din : in std_logic_vector(7 downto 0);
-- output signals
cmd_ack : out std_logic; -- command done
ack_out : out std_logic;
i2c_busy : out std_logic; -- arbitration lost
i2c_al : out std_logic; -- i2c bus busy
dout : out std_logic_vector(7 downto 0);
-- i2c lines
scl_i : in std_logic; -- i2c clock line input
scl_o : out std_logic; -- i2c clock line output
scl_oen : out std_logic; -- i2c clock line output enable, active low
sda_i : in std_logic; -- i2c data line input
sda_o : out std_logic; -- i2c data line output
sda_oen : out std_logic -- i2c data line output enable, active low
);
end entity i2c_master_byte_ctrl;
architecture structural of i2c_master_byte_ctrl is
component i2c_master_bit_ctrl is
port (
clk : in std_logic;
rst : in std_logic;
nReset : in std_logic;
ena : in std_logic; -- core enable signal
clk_cnt : in std_logic_vector(15 downto 0); -- clock prescale value
cmd : in std_logic_vector(3 downto 0);
cmd_ack : out std_logic; -- command done
busy : out std_logic; -- i2c bus busy
al : out std_logic; -- arbitration lost
din : in std_logic;
dout : out std_logic;
-- i2c lines
scl_i : in std_logic; -- i2c clock line input
scl_o : out std_logic; -- i2c clock line output
scl_oen : out std_logic; -- i2c clock line output enable, active low
sda_i : in std_logic; -- i2c data line input
sda_o : out std_logic; -- i2c data line output
sda_oen : out std_logic -- i2c data line output enable, active low
);
end component i2c_master_bit_ctrl;
-- commands for bit_controller block
constant I2C_CMD_NOP : std_logic_vector(3 downto 0) := "0000";
constant I2C_CMD_START : std_logic_vector(3 downto 0) := "0001";
constant I2C_CMD_STOP : std_logic_vector(3 downto 0) := "0010";
constant I2C_CMD_READ : std_logic_vector(3 downto 0) := "0100";
constant I2C_CMD_WRITE : std_logic_vector(3 downto 0) := "1000";
-- signals for bit_controller
signal core_cmd : std_logic_vector(3 downto 0);
signal core_ack, core_txd, core_rxd : std_logic;
signal al : std_logic;
-- signals for shift register
signal sr : std_logic_vector(7 downto 0); -- 8bit shift register
signal shift, ld : std_logic;
-- signals for state machine
signal go, host_ack : std_logic;
-- Added init value to dcnt to prevent simulation meta-value
-- - [email protected]
signal dcnt : std_logic_vector(2 downto 0) := (others => '0'); -- data counter
signal cnt_done : std_logic;
begin
-- hookup bit_controller
bit_ctrl: i2c_master_bit_ctrl port map(
clk => clk,
rst => rst,
nReset => nReset,
ena => ena,
clk_cnt => clk_cnt,
cmd => core_cmd,
cmd_ack => core_ack,
busy => i2c_busy,
al => al,
din => core_txd,
dout => core_rxd,
scl_i => scl_i,
scl_o => scl_o,
scl_oen => scl_oen,
sda_i => sda_i,
sda_o => sda_o,
sda_oen => sda_oen
);
i2c_al <= al;
-- generate host-command-acknowledge
cmd_ack <= host_ack;
-- generate go-signal
go <= (read or write or stop) and not host_ack;
-- assign Dout output to shift-register
dout <= sr;
-- generate shift register
shift_register: process(clk, nReset)
begin
if (nReset = '0') then
sr <= (others => '0');
elsif (clk'event and clk = '1') then
if (rst = '1') then
sr <= (others => '0');
elsif (ld = '1') then
sr <= din;
elsif (shift = '1') then
sr <= (sr(6 downto 0) & core_rxd);
end if;
end if;
end process shift_register;
-- generate data-counter
data_cnt: process(clk, nReset)
begin
if (nReset = '0') then
dcnt <= (others => '0');
elsif (clk'event and clk = '1') then
if (rst = '1') then
dcnt <= (others => '0');
elsif (ld = '1') then
dcnt <= (others => '1'); -- load counter with 7
elsif (shift = '1') then
dcnt <= dcnt -1;
end if;
end if;
end process data_cnt;
cnt_done <= '1' when (dcnt = "000") else '0';
--
-- state machine
--
statemachine : block
type states is (st_idle, st_start, st_read, st_write, st_ack, st_stop);
signal c_state : states;
begin
--
-- command interpreter, translate complex commands into simpler I2C commands
--
nxt_state_decoder: process(clk, nReset)
begin
if (nReset = '0') then
core_cmd <= I2C_CMD_NOP;
core_txd <= '0';
shift <= '0';
ld <= '0';
host_ack <= '0';
c_state <= st_idle;
ack_out <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1' or al = '1') then
core_cmd <= I2C_CMD_NOP;
core_txd <= '0';
shift <= '0';
ld <= '0';
host_ack <= '0';
c_state <= st_idle;
ack_out <= '0';
else
-- initialy reset all signal
core_txd <= sr(7);
shift <= '0';
ld <= '0';
host_ack <= '0';
case c_state is
when st_idle =>
if (go = '1') then
if (start = '1') then
c_state <= st_start;
core_cmd <= I2C_CMD_START;
elsif (read = '1') then
c_state <= st_read;
core_cmd <= I2C_CMD_READ;
elsif (write = '1') then
c_state <= st_write;
core_cmd <= I2C_CMD_WRITE;
else -- stop
c_state <= st_stop;
core_cmd <= I2C_CMD_STOP;
end if;
ld <= '1';
end if;
when st_start =>
if (core_ack = '1') then
if (read = '1') then
c_state <= st_read;
core_cmd <= I2C_CMD_READ;
else
c_state <= st_write;
core_cmd <= I2C_CMD_WRITE;
end if;
ld <= '1';
end if;
when st_write =>
if (core_ack = '1') then
if (cnt_done = '1') then
c_state <= st_ack;
core_cmd <= I2C_CMD_READ;
else
c_state <= st_write; -- stay in same state
core_cmd <= I2C_CMD_WRITE; -- write next bit
shift <= '1';
end if;
end if;
when st_read =>
if (core_ack = '1') then
if (cnt_done = '1') then
c_state <= st_ack;
core_cmd <= I2C_CMD_WRITE;
else
c_state <= st_read; -- stay in same state
core_cmd <= I2C_CMD_READ; -- read next bit
end if;
shift <= '1';
core_txd <= ack_in;
end if;
when st_ack =>
if (core_ack = '1') then
-- check for stop; Should a STOP command be generated ?
if (stop = '1') then
c_state <= st_stop;
core_cmd <= I2C_CMD_STOP;
else
c_state <= st_idle;
core_cmd <= I2C_CMD_NOP;
-- generate command acknowledge signal
host_ack <= '1';
end if;
-- assign ack_out output to core_rxd (contains last received bit)
ack_out <= core_rxd;
core_txd <= '1';
else
core_txd <= ack_in;
end if;
when st_stop =>
if (core_ack = '1') then
c_state <= st_idle;
core_cmd <= I2C_CMD_NOP;
-- generate command acknowledge signal
host_ack <= '1';
end if;
when others => -- illegal states
c_state <= st_idle;
core_cmd <= I2C_CMD_NOP;
report ("Byte controller entered illegal state.");
end case;
end if;
end if;
end process nxt_state_decoder;
end block statemachine;
end architecture structural;
| mit | 3617ce5668fc82ba11ddc1766e16d06e | 0.466855 | 3.859122 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Defense/iu3BaseDCE2Scoped.vhd | 1 | 589,253 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008, 2009, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: iu3
-- File: iu3.vhd
-- Author: Jiri Gaisler, Edvin Catovic, Gaisler Research
-- Description: LEON3 7-stage integer pipline
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.sparc.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.leon3.all;
use gaisler.libiu.all;
use gaisler.arith.all;
-- pragma translate_off
use grlib.sparc_disas.all;
-- pragma translate_on
entity iu3 is
generic (
nwin : integer range 2 to 32 := 8;
isets : integer range 1 to 4 := 2;
dsets : integer range 1 to 4 := 2;
fpu : integer range 0 to 15 := 0;
v8 : integer range 0 to 63 := 2;
cp, mac : integer range 0 to 1 := 0;
dsu : integer range 0 to 1 := 1;
nwp : integer range 0 to 4 := 2;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
index : integer range 0 to 15:= 0;
lddel : integer range 1 to 2 := 1;
irfwt : integer range 0 to 1 := 0;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 2; -- trace buf size in kB (0 - no trace buffer)
pwd : integer range 0 to 2 := 0; -- power-down
svt : integer range 0 to 1 := 0; -- single-vector trapping
rstaddr : integer := 16#00000#; -- reset vector MSB address
smp : integer range 0 to 15 := 0; -- support SMP systems
fabtech : integer range 0 to NTECH := 20;
clk2x : integer := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
holdn : in std_ulogic;
ici : buffer icache_in_type;
ico : in icache_out_type;
dci : buffer dcache_in_type;
dco : in dcache_out_type;
rfi : buffer iregfile_in_type;
rfo : in iregfile_out_type;
irqi : in l3_irq_in_type;
irqo : buffer l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : buffer l3_debug_out_type;
muli : buffer mul32_in_type;
mulo : in mul32_out_type;
divi : buffer div32_in_type;
divo : in div32_out_type;
fpo : in fpc_out_type;
fpi : buffer fpc_in_type;
cpo : in fpc_out_type;
cpi : buffer fpc_in_type;
tbo : in tracebuf_out_type;
tbi : buffer tracebuf_in_type;
sclk : in std_ulogic
);
end;
architecture rtl of iu3 is
constant ISETMSB : integer := 0;
constant DSETMSB : integer := 0;
constant RFBITS : integer range 6 to 10 := 8;
constant NWINLOG2 : integer range 1 to 5 := 3;
constant CWPOPT : boolean := true;
constant CWPMIN : std_logic_vector(2 downto 0) := "000";
constant CWPMAX : std_logic_vector(2 downto 0) := "111";
constant FPEN : boolean := (fpu /= 0);
constant CPEN : boolean := false;
constant MULEN : boolean := true;
constant MULTYPE: integer := 0;
constant DIVEN : boolean := true;
constant MACEN : boolean := false;
constant MACPIPE: boolean := false;
constant IMPL : integer := 15;
constant VER : integer := 3;
constant DBGUNIT : boolean := true;
constant TRACEBUF : boolean := true;
constant TBUFBITS : integer := 7;
constant PWRD1 : boolean := false; --(pwd = 1) and not (index /= 0);
constant PWRD2 : boolean := false; --(pwd = 2) or (index /= 0);
constant RS1OPT : boolean := true;
constant DYNRST : boolean := false;
subtype word is std_logic_vector(31 downto 0);
subtype pctype is std_logic_vector(31 downto 2);
subtype rfatype is std_logic_vector(8-1 downto 0);
subtype cwptype is std_logic_vector(3-1 downto 0);
type icdtype is array (0 to 2-1) of word;
type dcdtype is array (0 to 2-1) of word;
type dc_in_type is record
signed, enaddr, read, write, lock , dsuen : std_ulogic;
size : std_logic_vector(1 downto 0);
asi : std_logic_vector(7 downto 0);
end record;
type pipeline_ctrl_type is record
pc : pctype;
inst : word;
cnt : std_logic_vector(1 downto 0);
rd : rfatype;
tt : std_logic_vector(5 downto 0);
trap : std_ulogic;
annul : std_ulogic;
wreg : std_ulogic;
wicc : std_ulogic;
wy : std_ulogic;
ld : std_ulogic;
pv : std_ulogic;
rett : std_ulogic;
end record;
type fetch_reg_type is record
pc : pctype;
branch : std_ulogic;
end record;
type decode_reg_type is record
pc : pctype;
inst : icdtype;
cwp : cwptype;
set : std_logic_vector(0 downto 0);
mexc : std_ulogic;
cnt : std_logic_vector(1 downto 0);
pv : std_ulogic;
annul : std_ulogic;
inull : std_ulogic;
step : std_ulogic;
end record;
type regacc_reg_type is record
ctrl : pipeline_ctrl_type;
rs1 : std_logic_vector(4 downto 0);
rfa1, rfa2 : rfatype;
rsel1, rsel2 : std_logic_vector(2 downto 0);
rfe1, rfe2 : std_ulogic;
cwp : cwptype;
imm : word;
ldcheck1 : std_ulogic;
ldcheck2 : std_ulogic;
ldchkra : std_ulogic;
ldchkex : std_ulogic;
su : std_ulogic;
et : std_ulogic;
wovf : std_ulogic;
wunf : std_ulogic;
ticc : std_ulogic;
jmpl : std_ulogic;
step : std_ulogic;
mulstart : std_ulogic;
divstart : std_ulogic;
end record;
type execute_reg_type is record
ctrl : pipeline_ctrl_type;
op1 : word;
op2 : word;
aluop : std_logic_vector(2 downto 0); -- Alu operation
alusel : std_logic_vector(1 downto 0); -- Alu result select
aluadd : std_ulogic;
alucin : std_ulogic;
ldbp1, ldbp2 : std_ulogic;
invop2 : std_ulogic;
shcnt : std_logic_vector(4 downto 0); -- shift count
sari : std_ulogic; -- shift msb
shleft : std_ulogic; -- shift left/right
ymsb : std_ulogic; -- shift left/right
rd : std_logic_vector(4 downto 0);
jmpl : std_ulogic;
su : std_ulogic;
et : std_ulogic;
cwp : cwptype;
icc : std_logic_vector(3 downto 0);
mulstep: std_ulogic;
mul : std_ulogic;
mac : std_ulogic;
end record;
type memory_reg_type is record
ctrl : pipeline_ctrl_type;
result : word;
y : word;
icc : std_logic_vector(3 downto 0);
nalign : std_ulogic;
dci : dc_in_type;
werr : std_ulogic;
wcwp : std_ulogic;
irqen : std_ulogic;
irqen2 : std_ulogic;
mac : std_ulogic;
divz : std_ulogic;
su : std_ulogic;
mul : std_ulogic;
end record;
type exception_state is (run, trap, dsu1, dsu2);
type exception_reg_type is record
ctrl : pipeline_ctrl_type;
result : word;
y : word;
icc : std_logic_vector( 3 downto 0);
annul_all : std_ulogic;
data : dcdtype;
set : std_logic_vector(0 downto 0);
mexc : std_ulogic;
dci : dc_in_type;
laddr : std_logic_vector(1 downto 0);
rstate : exception_state;
npc : std_logic_vector(2 downto 0);
intack : std_ulogic;
ipend : std_ulogic;
mac : std_ulogic;
debug : std_ulogic;
nerror : std_ulogic;
end record;
type dsu_registers is record
tt : std_logic_vector(7 downto 0);
err : std_ulogic;
tbufcnt : std_logic_vector(7-1 downto 0);
asi : std_logic_vector(7 downto 0);
crdy : std_logic_vector(2 downto 1); -- diag cache access ready
end record;
type irestart_register is record
addr : pctype;
pwd : std_ulogic;
end record;
type pwd_register_type is record
pwd : std_ulogic;
error : std_ulogic;
end record;
type special_register_type is record
cwp : cwptype; -- current window pointer
icc : std_logic_vector(3 downto 0); -- integer condition codes
tt : std_logic_vector(7 downto 0); -- trap type
tba : std_logic_vector(19 downto 0); -- trap base address
wim : std_logic_vector(8-1 downto 0); -- window invalid mask
pil : std_logic_vector(3 downto 0); -- processor interrupt level
ec : std_ulogic; -- enable CP
ef : std_ulogic; -- enable FP
ps : std_ulogic; -- previous supervisor flag
s : std_ulogic; -- supervisor flag
et : std_ulogic; -- enable traps
y : word;
asr18 : word;
svt : std_ulogic; -- enable traps
dwt : std_ulogic; -- disable write error trap
end record;
type write_reg_type is record
s : special_register_type;
result : word;
wa : rfatype;
wreg : std_ulogic;
except : std_ulogic;
end record;
type registers is record
f : fetch_reg_type;
d : decode_reg_type;
a : regacc_reg_type;
e : execute_reg_type;
m : memory_reg_type;
x : exception_reg_type;
w : write_reg_type;
end record;
type exception_type is record
pri : std_ulogic;
ill : std_ulogic;
fpdis : std_ulogic;
cpdis : std_ulogic;
wovf : std_ulogic;
wunf : std_ulogic;
ticc : std_ulogic;
end record;
type watchpoint_register is record
addr : std_logic_vector(31 downto 2); -- watchpoint address
mask : std_logic_vector(31 downto 2); -- watchpoint mask
exec : std_ulogic; -- trap on instruction
load : std_ulogic; -- trap on load
store : std_ulogic; -- trap on store
end record;
type watchpoint_registers is array (0 to 3) of watchpoint_register;
constant wpr_none : watchpoint_register := (
"000000000000000000000000000000", "000000000000000000000000000000", '0', '0', '0');
function dbgexc(r : registers; dbgi : l3_debug_in_type; trap : std_ulogic; tt : std_logic_vector(7 downto 0)) return std_ulogic is
variable dmode : std_ulogic;
begin
dmode := '0';
if (not r.x.ctrl.annul and trap) = '1' then
if (((tt = "00" & TT_WATCH) and (dbgi.bwatch = '1')) or
((dbgi.bsoft = '1') and (tt = "10000001")) or
(dbgi.btrapa = '1') or
((dbgi.btrape = '1') and not ((tt(5 downto 0) = TT_PRIV) or
(tt(5 downto 0) = TT_FPDIS) or (tt(5 downto 0) = TT_WINOF) or
(tt(5 downto 0) = TT_WINUF) or (tt(5 downto 4) = "01") or (tt(7) = '1'))) or
(((not r.w.s.et) and dbgi.berror) = '1')) then
dmode := '1';
end if;
end if;
return(dmode);
end;
function dbgerr(r : registers; dbgi : l3_debug_in_type;
tt : std_logic_vector(7 downto 0))
return std_ulogic is
variable err : std_ulogic;
begin
err := not r.w.s.et;
if (((dbgi.dbreak = '1') and (tt = ("00" & TT_WATCH))) or
((dbgi.bsoft = '1') and (tt = ("10000001")))) then
err := '0';
end if;
return(err);
end;
procedure diagwr(r : in registers;
dsur : in dsu_registers;
ir : in irestart_register;
dbg : in l3_debug_in_type;
wpr : in watchpoint_registers;
s : out special_register_type;
vwpr : out watchpoint_registers;
asi : out std_logic_vector(7 downto 0);
pc, npc : out pctype;
tbufcnt : out std_logic_vector(7-1 downto 0);
wr : out std_ulogic;
addr : out std_logic_vector(9 downto 0);
data : out word;
fpcwr : out std_ulogic) is
variable i : integer range 0 to 3;
begin
s := r.w.s; pc := r.f.pc; npc := ir.addr; wr := '0';
vwpr := wpr; asi := dsur.asi; addr := "0000000000";
data := dbg.ddata;
tbufcnt := dsur.tbufcnt; fpcwr := '0';
if (dbg.dsuen and dbg.denable and dbg.dwrite) = '1' then
case dbg.daddr(23 downto 20) is
when "0001" =>
if (dbg.daddr(16) = '1') and true then -- trace buffer control reg
tbufcnt := dbg.ddata(7-1 downto 0);
end if;
when "0011" => -- IU reg file
if dbg.daddr(12) = '0' then
wr := '1';
addr := "0000000000";
addr(8-1 downto 0) := dbg.daddr(8+1 downto 2);
else -- FPC
fpcwr := '1';
end if;
when "0100" => -- IU special registers
case dbg.daddr(7 downto 6) is
when "00" => -- IU regs Y - TBUF ctrl reg
case dbg.daddr(5 downto 2) is
when "0000" => -- Y
s.y := dbg.ddata;
when "0001" => -- PSR
s.cwp := dbg.ddata(3-1 downto 0);
s.icc := dbg.ddata(23 downto 20);
s.ec := dbg.ddata(13);
if FPEN then s.ef := dbg.ddata(12); end if;
s.pil := dbg.ddata(11 downto 8);
s.s := dbg.ddata(7);
s.ps := dbg.ddata(6);
s.et := dbg.ddata(5);
when "0010" => -- WIM
s.wim := dbg.ddata(8-1 downto 0);
when "0011" => -- TBR
s.tba := dbg.ddata(31 downto 12);
s.tt := dbg.ddata(11 downto 4);
when "0100" => -- PC
pc := dbg.ddata(31 downto 2);
when "0101" => -- NPC
npc := dbg.ddata(31 downto 2);
when "0110" => --FSR
fpcwr := '1';
when "0111" => --CFSR
when "1001" => -- ASI reg
asi := dbg.ddata(7 downto 0);
--when "1001" => -- TBUF ctrl reg
-- tbufcnt := dbg.ddata(7-1 downto 0);
when others =>
end case;
when "01" => -- ASR16 - ASR31
case dbg.daddr(5 downto 2) is
when "0001" => -- %ASR17
s.dwt := dbg.ddata(14);
s.svt := dbg.ddata(13);
when "0010" => -- %ASR18
if false then s.asr18 := dbg.ddata; end if;
when "1000" => -- %ASR24 - %ASR31
vwpr(0).addr := dbg.ddata(31 downto 2);
vwpr(0).exec := dbg.ddata(0);
when "1001" =>
vwpr(0).mask := dbg.ddata(31 downto 2);
vwpr(0).load := dbg.ddata(1);
vwpr(0).store := dbg.ddata(0);
when "1010" =>
vwpr(1).addr := dbg.ddata(31 downto 2);
vwpr(1).exec := dbg.ddata(0);
when "1011" =>
vwpr(1).mask := dbg.ddata(31 downto 2);
vwpr(1).load := dbg.ddata(1);
vwpr(1).store := dbg.ddata(0);
when "1100" =>
vwpr(2).addr := dbg.ddata(31 downto 2);
vwpr(2).exec := dbg.ddata(0);
when "1101" =>
vwpr(2).mask := dbg.ddata(31 downto 2);
vwpr(2).load := dbg.ddata(1);
vwpr(2).store := dbg.ddata(0);
when "1110" =>
vwpr(3).addr := dbg.ddata(31 downto 2);
vwpr(3).exec := dbg.ddata(0);
when "1111" => --
vwpr(3).mask := dbg.ddata(31 downto 2);
vwpr(3).load := dbg.ddata(1);
vwpr(3).store := dbg.ddata(0);
when others => --
end case;
-- disabled due to bug in XST
-- i := conv_integer(dbg.daddr(4 downto 3));
-- if dbg.daddr(2) = '0' then
-- vwpr(i).addr := dbg.ddata(31 downto 2);
-- vwpr(i).exec := dbg.ddata(0);
-- else
-- vwpr(i).mask := dbg.ddata(31 downto 2);
-- vwpr(i).load := dbg.ddata(1);
-- vwpr(i).store := dbg.ddata(0);
-- end if;
when others =>
end case;
when others =>
end case;
end if;
end;
function asr17_gen ( r : in registers) return word is
variable asr17 : word;
variable fpu2 : integer range 0 to 3;
begin
asr17 := "00000000000000000000000000000000";
asr17(31 downto 28) := conv_std_logic_vector(index, 4);
if (clk2x > 8) then
asr17(16 downto 15) := conv_std_logic_vector(clk2x-8, 2);
asr17(17) := '1';
elsif (clk2x > 0) then
asr17(16 downto 15) := conv_std_logic_vector(clk2x, 2);
end if;
asr17(14) := r.w.s.dwt;
if svt = 1 then asr17(13) := r.w.s.svt; end if;
if lddel = 2 then asr17(12) := '1'; end if;
if (fpu > 0) and (fpu < 8) then fpu2 := 1;
elsif (fpu >= 8) and (fpu < 15) then fpu2 := 3;
elsif fpu = 15 then fpu2 := 2;
else fpu2 := 0; end if;
asr17(11 downto 10) := conv_std_logic_vector(fpu2, 2);
if mac = 1 then asr17(9) := '1'; end if;
if 2 /= 0 then asr17(8) := '1'; end if;
asr17(7 downto 5) := conv_std_logic_vector(nwp, 3);
asr17(4 downto 0) := conv_std_logic_vector(8-1, 5);
return(asr17);
end;
procedure diagread(dbgi : in l3_debug_in_type;
r : in registers;
dsur : in dsu_registers;
ir : in irestart_register;
wpr : in watchpoint_registers;
dco : in dcache_out_type;
tbufo : in tracebuf_out_type;
data : out word) is
variable cwp : std_logic_vector(4 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable i : integer range 0 to 3;
begin
data := "00000000000000000000000000000000"; cwp := "00000";
cwp(3-1 downto 0) := r.w.s.cwp;
case dbgi.daddr(22 downto 20) is
when "001" => -- trace buffer
if true then
if dbgi.daddr(16) = '1' then -- trace buffer control reg
if true then data(7-1 downto 0) := dsur.tbufcnt; end if;
else
case dbgi.daddr(3 downto 2) is
when "00" => data := tbufo.data(127 downto 96);
when "01" => data := tbufo.data(95 downto 64);
when "10" => data := tbufo.data(63 downto 32);
when others => data := tbufo.data(31 downto 0);
end case;
end if;
end if;
when "011" => -- IU reg file
if dbgi.daddr(12) = '0' then
data := rfo.data1(31 downto 0);
if (dbgi.daddr(11) = '1') and (is_fpga(fabtech) = 0) then
data := rfo.data2(31 downto 0);
end if;
else data := fpo.dbg.data; end if;
when "100" => -- IU regs
case dbgi.daddr(7 downto 6) is
when "00" => -- IU regs Y - TBUF ctrl reg
case dbgi.daddr(5 downto 2) is
when "0000" =>
data := r.w.s.y;
when "0001" =>
data := conv_std_logic_vector(15, 4) & conv_std_logic_vector(3, 4) &
r.w.s.icc & "000000" & r.w.s.ec & r.w.s.ef & r.w.s.pil &
r.w.s.s & r.w.s.ps & r.w.s.et & cwp;
when "0010" =>
data(8-1 downto 0) := r.w.s.wim;
when "0011" =>
data := r.w.s.tba & r.w.s.tt & "0000";
when "0100" =>
data(31 downto 2) := r.f.pc;
when "0101" =>
data(31 downto 2) := ir.addr;
when "0110" => -- FSR
data := fpo.dbg.data;
when "0111" => -- CPSR
when "1000" => -- TT reg
data(12 downto 4) := dsur.err & dsur.tt;
when "1001" => -- ASI reg
data(7 downto 0) := dsur.asi;
when others =>
end case;
when "01" =>
if dbgi.daddr(5) = '0' then -- %ASR17
if dbgi.daddr(4 downto 2) = "001" then -- %ASR17
data := asr17_gen(r);
elsif false and dbgi.daddr(4 downto 2) = "010" then -- %ASR18
data := r.w.s.asr18;
end if;
else -- %ASR24 - %ASR31
i := conv_integer(dbgi.daddr(4 downto 3)); --
if dbgi.daddr(2) = '0' then
data(31 downto 2) := wpr(i).addr;
data(0) := wpr(i).exec;
else
data(31 downto 2) := wpr(i).mask;
data(1) := wpr(i).load;
data(0) := wpr(i).store;
end if;
end if;
when others =>
end case;
when "111" =>
data := r.x.data(conv_integer(r.x.set));
when others =>
end case;
end;
procedure itrace(r : in registers;
dsur : in dsu_registers;
vdsu : in dsu_registers;
res : in word;
exc : in std_ulogic;
dbgi : in l3_debug_in_type;
error : in std_ulogic;
trap : in std_ulogic;
tbufcnt : out std_logic_vector(7-1 downto 0);
di : out tracebuf_in_type) is
variable meminst : std_ulogic;
begin
di.addr := (others => '0'); di.data := (others => '0');
di.enable := '0'; di.write := (others => '0');
tbufcnt := vdsu.tbufcnt;
meminst := r.x.ctrl.inst(31) and r.x.ctrl.inst(30);
if true then
di.addr(7-1 downto 0) := dsur.tbufcnt;
di.data(127) := '0';
di.data(126) := not r.x.ctrl.pv;
di.data(125 downto 96) := dbgi.timer(29 downto 0);
di.data(95 downto 64) := res;
di.data(63 downto 34) := r.x.ctrl.pc(31 downto 2);
di.data(33) := trap;
di.data(32) := error;
di.data(31 downto 0) := r.x.ctrl.inst;
if (dbgi.tenable = '0') or (r.x.rstate = dsu2) then
if ((dbgi.dsuen and dbgi.denable) = '1') and (dbgi.daddr(23 downto 20) & dbgi.daddr(16) = "00010") then
di.enable := '1';
di.addr(7-1 downto 0) := dbgi.daddr(7-1+4 downto 4);
if dbgi.dwrite = '1' then
case dbgi.daddr(3 downto 2) is
when "00" => di.write(3) := '1';
when "01" => di.write(2) := '1';
when "10" => di.write(1) := '1';
when others => di.write(0) := '1';
end case;
di.data := dbgi.ddata & dbgi.ddata & dbgi.ddata & dbgi.ddata;
end if;
end if;
elsif (not r.x.ctrl.annul and (r.x.ctrl.pv or meminst) and not r.x.debug) = '1' then
di.enable := '1'; di.write := (others => '1');
tbufcnt := dsur.tbufcnt + 1;
end if;
di.diag := dco.testen & "000";
if dco.scanen = '1' then di.enable := '0'; end if;
end if;
end;
procedure dbg_cache(holdn : in std_ulogic;
dbgi : in l3_debug_in_type;
r : in registers;
dsur : in dsu_registers;
mresult : in word;
dci : in dc_in_type;
mresult2 : out word;
dci2 : out dc_in_type
) is
begin
mresult2 := mresult; dci2 := dci; dci2.dsuen := '0';
if true then
if r.x.rstate = dsu2 then
dci2.asi := dsur.asi;
if (dbgi.daddr(22 downto 20) = "111") and (dbgi.dsuen = '1') then
dci2.dsuen := (dbgi.denable or r.m.dci.dsuen) and not dsur.crdy(2);
dci2.enaddr := dbgi.denable;
dci2.size := "10"; dci2.read := '1'; dci2.write := '0';
if (dbgi.denable and not r.m.dci.enaddr) = '1' then
mresult2 := (others => '0'); mresult2(19 downto 2) := dbgi.daddr(19 downto 2);
else
mresult2 := dbgi.ddata;
end if;
if dbgi.dwrite = '1' then
dci2.read := '0'; dci2.write := '1';
end if;
end if;
end if;
end if;
end;
procedure fpexack(r : in registers; fpexc : out std_ulogic) is
begin
fpexc := '0';
if FPEN then
if r.x.ctrl.tt = TT_FPEXC then fpexc := '1'; end if;
end if;
end;
procedure diagrdy(denable : in std_ulogic;
dsur : in dsu_registers;
dci : in dc_in_type;
mds : in std_ulogic;
ico : in icache_out_type;
crdy : out std_logic_vector(2 downto 1)) is
begin
crdy := dsur.crdy(1) & '0';
if dci.dsuen = '1' then
case dsur.asi(4 downto 0) is
when ASI_ITAG | ASI_IDATA | ASI_UINST | ASI_SINST =>
crdy(2) := ico.diagrdy and not dsur.crdy(2);
when ASI_DTAG | ASI_MMUSNOOP_DTAG | ASI_DDATA | ASI_UDATA | ASI_SDATA =>
crdy(1) := not denable and dci.enaddr and not dsur.crdy(1);
when others =>
crdy(2) := dci.enaddr and denable;
end case;
end if;
end;
signal r, rin : registers;
signal wpr, wprin : watchpoint_registers;
signal dsur, dsuin : dsu_registers;
signal ir, irin : irestart_register;
signal rp, rpin : pwd_register_type;
-- execute stage operations
constant EXE_AND : std_logic_vector(2 downto 0) := "000";
constant EXE_XOR : std_logic_vector(2 downto 0) := "001"; -- must be equal to EXE_PASS2
constant EXE_OR : std_logic_vector(2 downto 0) := "010";
constant EXE_XNOR : std_logic_vector(2 downto 0) := "011";
constant EXE_ANDN : std_logic_vector(2 downto 0) := "100";
constant EXE_ORN : std_logic_vector(2 downto 0) := "101";
constant EXE_DIV : std_logic_vector(2 downto 0) := "110";
constant EXE_PASS1 : std_logic_vector(2 downto 0) := "000";
constant EXE_PASS2 : std_logic_vector(2 downto 0) := "001";
constant EXE_STB : std_logic_vector(2 downto 0) := "010";
constant EXE_STH : std_logic_vector(2 downto 0) := "011";
constant EXE_ONES : std_logic_vector(2 downto 0) := "100";
constant EXE_RDY : std_logic_vector(2 downto 0) := "101";
constant EXE_SPR : std_logic_vector(2 downto 0) := "110";
constant EXE_LINK : std_logic_vector(2 downto 0) := "111";
constant EXE_SLL : std_logic_vector(2 downto 0) := "001";
constant EXE_SRL : std_logic_vector(2 downto 0) := "010";
constant EXE_SRA : std_logic_vector(2 downto 0) := "100";
constant EXE_NOP : std_logic_vector(2 downto 0) := "000";
-- EXE result select
constant EXE_RES_ADD : std_logic_vector(1 downto 0) := "00";
constant EXE_RES_SHIFT : std_logic_vector(1 downto 0) := "01";
constant EXE_RES_LOGIC : std_logic_vector(1 downto 0) := "10";
constant EXE_RES_MISC : std_logic_vector(1 downto 0) := "11";
-- Load types
constant SZBYTE : std_logic_vector(1 downto 0) := "00";
constant SZHALF : std_logic_vector(1 downto 0) := "01";
constant SZWORD : std_logic_vector(1 downto 0) := "10";
constant SZDBL : std_logic_vector(1 downto 0) := "11";
-- calculate register file address
procedure regaddr(cwp : std_logic_vector; reg : std_logic_vector(4 downto 0);
rao : out rfatype) is
variable ra : rfatype;
constant globals : std_logic_vector(8-5 downto 0) :=
conv_std_logic_vector(8, 8-4);
begin
ra := (others => '0'); ra(4 downto 0) := reg;
if reg(4 downto 3) = "00" then ra(8 -1 downto 4) := globals;
else
ra(3+3 downto 4) := cwp + ra(4);
if ra(8-1 downto 4) = globals then
ra(8-1 downto 4) := (others => '0');
end if;
end if;
rao := ra;
end;
-- branch adder
function branch_address(inst : word; pc : pctype) return std_logic_vector is
variable baddr, caddr, tmp : pctype;
begin
caddr := (others => '0'); caddr(31 downto 2) := inst(29 downto 0);
caddr(31 downto 2) := caddr(31 downto 2) + pc(31 downto 2);
baddr := (others => '0'); baddr(31 downto 24) := (others => inst(21));
baddr(23 downto 2) := inst(21 downto 0);
baddr(31 downto 2) := baddr(31 downto 2) + pc(31 downto 2);
if inst(30) = '1' then tmp := caddr; else tmp := baddr; end if;
return(tmp);
end;
-- evaluate branch condition
function branch_true(icc : std_logic_vector(3 downto 0); inst : word)
return std_ulogic is
variable n, z, v, c, branch : std_ulogic;
begin
n := icc(3); z := icc(2); v := icc(1); c := icc(0);
case inst(27 downto 25) is
when "000" => branch := inst(28) xor '0'; -- bn, ba
when "001" => branch := inst(28) xor z; -- be, bne
when "010" => branch := inst(28) xor (z or (n xor v)); -- ble, bg
when "011" => branch := inst(28) xor (n xor v); -- bl, bge
when "100" => branch := inst(28) xor (c or z); -- bleu, bgu
when "101" => branch := inst(28) xor c; -- bcs, bcc
when "110" => branch := inst(28) xor n; -- bneg, bpos
when others => branch := inst(28) xor v; -- bvs, bvc
end case;
return(branch);
end;
-- detect RETT instruction in the pipeline and set the local psr.su and psr.et
procedure su_et_select(r : in registers; xc_ps, xc_s, xc_et : in std_ulogic;
su, et : out std_ulogic) is
begin
if ((r.a.ctrl.rett or r.e.ctrl.rett or r.m.ctrl.rett or r.x.ctrl.rett) = '1')
and (r.x.annul_all = '0')
then su := xc_ps; et := '1';
else su := xc_s; et := xc_et; end if;
end;
-- detect watchpoint trap
function wphit(r : registers; wpr : watchpoint_registers; debug : l3_debug_in_type)
return std_ulogic is
variable exc : std_ulogic;
begin
exc := '0';
for i in 1 to NWP loop
if ((wpr(i-1).exec and r.a.ctrl.pv and not r.a.ctrl.annul) = '1') then
if (((wpr(i-1).addr xor r.a.ctrl.pc(31 downto 2)) and wpr(i-1).mask) = "000000000000000000000000000000") then
exc := '1';
end if;
end if;
end loop;
if true then
if (debug.dsuen and not r.a.ctrl.annul) = '1' then
exc := exc or (r.a.ctrl.pv and ((debug.dbreak and debug.bwatch) or r.a.step));
end if;
end if;
return(exc);
end;
-- 32-bit shifter
function shift3(r : registers; aluin1, aluin2 : word) return word is
variable shiftin : unsigned(63 downto 0);
variable shiftout : unsigned(63 downto 0);
variable cnt : natural range 0 to 31;
begin
cnt := conv_integer(r.e.shcnt);
if r.e.shleft = '1' then
shiftin(30 downto 0) := (others => '0');
shiftin(63 downto 31) := '0' & unsigned(aluin1);
else
shiftin(63 downto 32) := (others => r.e.sari);
shiftin(31 downto 0) := unsigned(aluin1);
end if;
shiftout := SHIFT_RIGHT(shiftin, cnt);
return(std_logic_vector(shiftout(31 downto 0)));
end;
function shift2(r : registers; aluin1, aluin2 : word) return word is
variable ushiftin : unsigned(31 downto 0);
variable sshiftin : signed(32 downto 0);
variable cnt : natural range 0 to 31;
variable resleft, resright : word;
begin
cnt := conv_integer(r.e.shcnt);
ushiftin := unsigned(aluin1);
sshiftin := signed('0' & aluin1);
if r.e.shleft = '1' then
resleft := std_logic_vector(SHIFT_LEFT(ushiftin, cnt));
return(resleft);
else
if r.e.sari = '1' then sshiftin(32) := aluin1(31); end if;
sshiftin := SHIFT_RIGHT(sshiftin, cnt);
resright := std_logic_vector(sshiftin(31 downto 0));
return(resright);
-- else
-- ushiftin := SHIFT_RIGHT(ushiftin, cnt);
-- return(std_logic_vector(ushiftin));
-- end if;
end if;
end;
function shift(r : registers; aluin1, aluin2 : word;
shiftcnt : std_logic_vector(4 downto 0); sari : std_ulogic ) return word is
variable shiftin : std_logic_vector(63 downto 0);
begin
shiftin := "00000000000000000000000000000000" & aluin1;
if r.e.shleft = '1' then
shiftin(31 downto 0) := "00000000000000000000000000000000"; shiftin(63 downto 31) := '0' & aluin1;
else shiftin(63 downto 32) := (others => sari); end if;
if shiftcnt (4) = '1' then shiftin(47 downto 0) := shiftin(63 downto 16); end if;
if shiftcnt (3) = '1' then shiftin(39 downto 0) := shiftin(47 downto 8); end if;
if shiftcnt (2) = '1' then shiftin(35 downto 0) := shiftin(39 downto 4); end if;
if shiftcnt (1) = '1' then shiftin(33 downto 0) := shiftin(35 downto 2); end if;
if shiftcnt (0) = '1' then shiftin(31 downto 0) := shiftin(32 downto 1); end if;
return(shiftin(31 downto 0));
end;
-- Check for illegal and privileged instructions
procedure exception_detect(r : registers; wpr : watchpoint_registers; dbgi : l3_debug_in_type;
trapin : in std_ulogic; ttin : in std_logic_vector(5 downto 0);
trap : out std_ulogic; tt : out std_logic_vector(5 downto 0)) is
variable illegal_inst, privileged_inst : std_ulogic;
variable cp_disabled, fp_disabled, fpop : std_ulogic;
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable inst : word;
variable wph : std_ulogic;
begin
inst := r.a.ctrl.inst; trap := trapin; tt := ttin;
if r.a.ctrl.annul = '0' then
op := inst(31 downto 30); op2 := inst(24 downto 22);
op3 := inst(24 downto 19); rd := inst(29 downto 25);
illegal_inst := '0'; privileged_inst := '0'; cp_disabled := '0';
fp_disabled := '0'; fpop := '0';
case op is
when CALL => null;
when FMT2 =>
case op2 is
when SETHI | BICC => null;
when FBFCC =>
if FPEN then fp_disabled := not r.w.s.ef; else fp_disabled := '1'; end if;
when CBCCC =>
if (not false) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when others => illegal_inst := '1';
end case;
when FMT3 =>
case op3 is
when IAND | ANDCC | ANDN | ANDNCC | IOR | ORCC | ORN | ORNCC | IXOR |
XORCC | IXNOR | XNORCC | ISLL | ISRL | ISRA | MULSCC | IADD | ADDX |
ADDCC | ADDXCC | ISUB | SUBX | SUBCC | SUBXCC | FLUSH | JMPL | TICC |
SAVE | RESTORE | RDY => null;
when TADDCC | TADDCCTV | TSUBCC | TSUBCCTV =>
if notag = 1 then illegal_inst := '1'; end if;
when UMAC | SMAC =>
if not false then illegal_inst := '1'; end if;
when UMUL | SMUL | UMULCC | SMULCC =>
if not true then illegal_inst := '1'; end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if not true then illegal_inst := '1'; end if;
when RETT => illegal_inst := r.a.et; privileged_inst := not r.a.su;
when RDPSR | RDTBR | RDWIM => privileged_inst := not r.a.su;
when WRY => null;
when WRPSR =>
privileged_inst := not r.a.su;
when WRWIM | WRTBR => privileged_inst := not r.a.su;
when FPOP1 | FPOP2 =>
if FPEN then fp_disabled := not r.w.s.ef; fpop := '1';
else fp_disabled := '1'; fpop := '0'; end if;
when CPOP1 | CPOP2 =>
if (not false) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when others => illegal_inst := '1';
end case;
when others => -- LDST
case op3 is
when LDD | ISTD => illegal_inst := rd(0); -- trap if odd destination register
when LD | LDUB | LDSTUB | LDUH | LDSB | LDSH | ST | STB | STH | SWAP =>
null;
when LDDA | STDA =>
illegal_inst := inst(13) or rd(0); privileged_inst := not r.a.su;
when LDA | LDUBA| LDSTUBA | LDUHA | LDSBA | LDSHA | STA | STBA | STHA |
SWAPA =>
illegal_inst := inst(13); privileged_inst := not r.a.su;
when LDDF | STDF | LDF | LDFSR | STF | STFSR =>
if FPEN then fp_disabled := not r.w.s.ef;
else fp_disabled := '1'; end if;
when STDFQ =>
privileged_inst := not r.a.su;
if (not FPEN) or (r.w.s.ef = '0') then fp_disabled := '1'; end if;
when STDCQ =>
privileged_inst := not r.a.su;
if (not false) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when LDC | LDCSR | LDDC | STC | STCSR | STDC =>
if (not false) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when others => illegal_inst := '1';
end case;
end case;
wph := wphit(r, wpr, dbgi);
trap := '1';
if r.a.ctrl.trap = '1' then tt := TT_IAEX;
elsif privileged_inst = '1' then tt := TT_PRIV;
elsif illegal_inst = '1' then tt := TT_IINST;
elsif fp_disabled = '1' then tt := TT_FPDIS;
elsif cp_disabled = '1' then tt := TT_CPDIS;
elsif wph = '1' then tt := TT_WATCH;
elsif r.a.wovf= '1' then tt := TT_WINOF;
elsif r.a.wunf= '1' then tt := TT_WINUF;
elsif r.a.ticc= '1' then tt := TT_TICC;
else trap := '0'; tt:= (others => '0'); end if;
end if;
end;
-- instructions that write the condition codes (psr.icc)
procedure wicc_y_gen(inst : word; wicc, wy : out std_ulogic) is
begin
wicc := '0'; wy := '0';
if inst(31 downto 30) = FMT3 then
case inst(24 downto 19) is
when SUBCC | TSUBCC | TSUBCCTV | ADDCC | ANDCC | ORCC | XORCC | ANDNCC |
ORNCC | XNORCC | TADDCC | TADDCCTV | ADDXCC | SUBXCC | WRPSR =>
wicc := '1';
when WRY =>
if r.d.inst(conv_integer(r.d.set))(29 downto 25) = "00000" then wy := '1'; end if;
when MULSCC =>
wicc := '1'; wy := '1';
when UMAC | SMAC =>
if false then wy := '1'; end if;
when UMULCC | SMULCC =>
if true and (((mulo.nready = '1') and (r.d.cnt /= "00")) or (0 /= 0)) then
wicc := '1'; wy := '1';
end if;
when UMUL | SMUL =>
if true and (((mulo.nready = '1') and (r.d.cnt /= "00")) or (0 /= 0)) then
wy := '1';
end if;
when UDIVCC | SDIVCC =>
if true and (divo.nready = '1') and (r.d.cnt /= "00") then
wicc := '1';
end if;
when others =>
end case;
end if;
end;
-- select cwp
procedure cwp_gen(r, v : registers; annul, wcwp : std_ulogic; ncwp : cwptype;
cwp : out cwptype) is
begin
if (r.x.rstate = trap) or (r.x.rstate = dsu2) or (rstn = '0') then cwp := v.w.s.cwp;
elsif (wcwp = '1') and (annul = '0') then cwp := ncwp;
elsif r.m.wcwp = '1' then cwp := r.m.result(3-1 downto 0);
else cwp := r.d.cwp; end if;
end;
-- generate wcwp in ex stage
procedure cwp_ex(r : in registers; wcwp : out std_ulogic) is
begin
if (r.e.ctrl.inst(31 downto 30) = FMT3) and
(r.e.ctrl.inst(24 downto 19) = WRPSR)
then wcwp := not r.e.ctrl.annul; else wcwp := '0'; end if;
end;
-- generate next cwp & window under- and overflow traps
procedure cwp_ctrl(r : in registers; xc_wim : in std_logic_vector(8-1 downto 0);
inst : word; de_cwp : out cwptype; wovf_exc, wunf_exc, wcwp : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable wim : word;
variable ncwp : cwptype;
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
wovf_exc := '0'; wunf_exc := '0'; wim := (others => '0');
wim(8-1 downto 0) := xc_wim; ncwp := r.d.cwp; wcwp := '0';
if (op = FMT3) and ((op3 = RETT) or (op3 = RESTORE) or (op3 = SAVE)) then
wcwp := '1';
if (op3 = SAVE) then
if (not true) and (r.d.cwp = "000") then ncwp := "111";
else ncwp := r.d.cwp - 1 ; end if;
else
if (not true) and (r.d.cwp = "111") then ncwp := "000";
else ncwp := r.d.cwp + 1; end if;
end if;
if wim(conv_integer(ncwp)) = '1' then
if op3 = SAVE then wovf_exc := '1'; else wunf_exc := '1'; end if;
end if;
end if;
de_cwp := ncwp;
end;
-- generate register read address 1
procedure rs1_gen(r : registers; inst : word; rs1 : out std_logic_vector(4 downto 0);
rs1mod : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
rs1 := inst(18 downto 14); rs1mod := '0';
if (op = LDST) then
if ((r.d.cnt = "01") and ((op3(2) and not op3(3)) = '1')) or
(r.d.cnt = "10")
then rs1mod := '1'; rs1 := inst(29 downto 25); end if;
if ((r.d.cnt = "10") and (op3(3 downto 0) = "0111")) then
rs1(0) := '1';
end if;
end if;
end;
-- load/icc interlock detection
procedure lock_gen(r : registers; rs2, rd : std_logic_vector(4 downto 0);
rfa1, rfa2, rfrd : rfatype; inst : word; fpc_lock, mulinsn, divinsn : std_ulogic;
lldcheck1, lldcheck2, lldlock, lldchkra, lldchkex : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable cond : std_logic_vector(3 downto 0);
variable rs1 : std_logic_vector(4 downto 0);
variable i, ldcheck1, ldcheck2, ldchkra, ldchkex, ldcheck3 : std_ulogic;
variable ldlock, icc_check, bicc_hold, chkmul, y_check : std_ulogic;
variable lddlock : boolean;
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
op2 := inst(24 downto 22); cond := inst(28 downto 25);
rs1 := inst(18 downto 14); lddlock := false; i := inst(13);
ldcheck1 := '0'; ldcheck2 := '0'; ldcheck3 := '0'; ldlock := '0';
ldchkra := '1'; ldchkex := '1'; icc_check := '0'; bicc_hold := '0';
y_check := '0';
if (r.d.annul = '0') then
case op is
when FMT2 =>
if (op2 = BICC) and (cond(2 downto 0) /= "000") then
icc_check := '1';
end if;
when FMT3 =>
ldcheck1 := '1'; ldcheck2 := not i;
case op3 is
when TICC =>
if (cond(2 downto 0) /= "000") then icc_check := '1'; end if;
when RDY =>
ldcheck1 := '0'; ldcheck2 := '0';
if false then y_check := '1'; end if;
when RDWIM | RDTBR =>
ldcheck1 := '0'; ldcheck2 := '0';
when RDPSR =>
ldcheck1 := '0'; ldcheck2 := '0'; icc_check := '1';
if true then icc_check := '1'; end if;
-- when ADDX | ADDXCC | SUBX | SUBXCC =>
-- if true then icc_check := '1'; end if;
when SDIV | SDIVCC | UDIV | UDIVCC =>
if true then y_check := '1'; end if;
when FPOP1 | FPOP2 => ldcheck1:= '0'; ldcheck2 := '0';
when others =>
end case;
when LDST =>
ldcheck1 := '1'; ldchkra := '0';
case r.d.cnt is
when "00" =>
if (lddel = 2) and (op3(2) = '1') then ldcheck3 := '1'; end if;
ldcheck2 := not i; ldchkra := '1';
when "01" => ldcheck2 := not i;
when others => ldchkex := '0';
end case;
if (op3(2 downto 0) = "011") then lddlock := true; end if;
when others => null;
end case;
end if;
if true or true then
chkmul := mulinsn;
bicc_hold := bicc_hold or (icc_check and r.m.ctrl.wicc and (r.m.ctrl.cnt(0) or r.m.mul));
else chkmul := '0'; end if;
if true then
bicc_hold := bicc_hold or (y_check and (r.a.ctrl.wy or r.e.ctrl.wy));
chkmul := chkmul or divinsn;
end if;
bicc_hold := bicc_hold or (icc_check and (r.a.ctrl.wicc or r.e.ctrl.wicc));
if (((r.a.ctrl.ld or chkmul) and r.a.ctrl.wreg and ldchkra) = '1') and
(((ldcheck1 = '1') and (r.a.ctrl.rd = rfa1)) or
((ldcheck2 = '1') and (r.a.ctrl.rd = rfa2)) or
((ldcheck3 = '1') and (r.a.ctrl.rd = rfrd)))
then ldlock := '1'; end if;
if (((r.e.ctrl.ld or r.e.mac) and r.e.ctrl.wreg and ldchkex) = '1') and
((lddel = 2) or (false and (r.e.mac = '1')) or ((0 = 3) and (r.e.mul = '1'))) and
(((ldcheck1 = '1') and (r.e.ctrl.rd = rfa1)) or
((ldcheck2 = '1') and (r.e.ctrl.rd = rfa2)))
then ldlock := '1'; end if;
ldlock := ldlock or bicc_hold or fpc_lock;
lldcheck1 := ldcheck1; lldcheck2:= ldcheck2; lldlock := ldlock;
lldchkra := ldchkra; lldchkex := ldchkex;
end;
procedure fpbranch(inst : in word; fcc : in std_logic_vector(1 downto 0);
branch : out std_ulogic) is
variable cond : std_logic_vector(3 downto 0);
variable fbres : std_ulogic;
begin
cond := inst(28 downto 25);
case cond(2 downto 0) is
when "000" => fbres := '0'; -- fba, fbn
when "001" => fbres := fcc(1) or fcc(0);
when "010" => fbres := fcc(1) xor fcc(0);
when "011" => fbres := fcc(0);
when "100" => fbres := (not fcc(1)) and fcc(0);
when "101" => fbres := fcc(1);
when "110" => fbres := fcc(1) and not fcc(0);
when others => fbres := fcc(1) and fcc(0);
end case;
branch := cond(3) xor fbres;
end;
-- PC generation
procedure ic_ctrl(r : registers; inst : word; annul_all, ldlock, branch_true,
fbranch_true, cbranch_true, fccv, cccv : in std_ulogic;
cnt : out std_logic_vector(1 downto 0);
de_pc : out pctype; de_branch, ctrl_annul, de_annul, jmpl_inst, inull,
de_pv, ctrl_pv, de_hold_pc, ticc_exception, rett_inst, mulstart,
divstart : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable cond : std_logic_vector(3 downto 0);
variable hold_pc, annul_current, annul_next, branch, annul, pv : std_ulogic;
variable de_jmpl : std_ulogic;
begin
branch := '0'; annul_next := '0'; annul_current := '0'; pv := '1';
hold_pc := '0'; ticc_exception := '0'; rett_inst := '0';
op := inst(31 downto 30); op3 := inst(24 downto 19);
op2 := inst(24 downto 22); cond := inst(28 downto 25);
annul := inst(29); de_jmpl := '0'; cnt := "00";
mulstart := '0'; divstart := '0';
if r.d.annul = '0' then
case inst(31 downto 30) is
when CALL =>
branch := '1';
if r.d.inull = '1' then
hold_pc := '1'; annul_current := '1';
end if;
when FMT2 =>
if (op2 = BICC) or (FPEN and (op2 = FBFCC)) or (false and (op2 = CBCCC)) then
if (FPEN and (op2 = FBFCC)) then
branch := fbranch_true;
if fccv /= '1' then hold_pc := '1'; annul_current := '1'; end if;
elsif (false and (op2 = CBCCC)) then
branch := cbranch_true;
if cccv /= '1' then hold_pc := '1'; annul_current := '1'; end if;
else branch := branch_true; end if;
if hold_pc = '0' then
if (branch = '1') then
if (cond = BA) and (annul = '1') then annul_next := '1'; end if;
else annul_next := annul; end if;
if r.d.inull = '1' then -- contention with JMPL
hold_pc := '1'; annul_current := '1'; annul_next := '0';
end if;
end if;
end if;
when FMT3 =>
case op3 is
when UMUL | SMUL | UMULCC | SMULCC =>
if true and (0 /= 0) then mulstart := '1'; end if;
if true and (0 = 0) then
case r.d.cnt is
when "00" =>
cnt := "01"; hold_pc := '1'; pv := '0'; mulstart := '1';
when "01" =>
if mulo.nready = '1' then cnt := "00";
else cnt := "01"; pv := '0'; hold_pc := '1'; end if;
when others => null;
end case;
end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if true then
case r.d.cnt is
when "00" =>
cnt := "01"; hold_pc := '1'; pv := '0';
divstart := '1';
when "01" =>
if divo.nready = '1' then cnt := "00";
else cnt := "01"; pv := '0'; hold_pc := '1'; end if;
when others => null;
end case;
end if;
when TICC =>
if branch_true = '1' then ticc_exception := '1'; end if;
when RETT =>
rett_inst := '1'; --su := sregs.ps;
when JMPL =>
de_jmpl := '1';
when WRY =>
if false then
if inst(29 downto 25) = "10011" then -- %ASR19
case r.d.cnt is
when "00" =>
pv := '0'; cnt := "00"; hold_pc := '1';
if r.x.ipend = '1' then cnt := "01"; end if;
when "01" =>
cnt := "00";
when others =>
end case;
end if;
end if;
when others => null;
end case;
when others => -- LDST
case r.d.cnt is
when "00" =>
if (op3(2) = '1') or (op3(1 downto 0) = "11") then -- ST/LDST/SWAP/LDD
cnt := "01"; hold_pc := '1'; pv := '0';
end if;
when "01" =>
if (op3(2 downto 0) = "111") or (op3(3 downto 0) = "1101") or
((false or FPEN) and ((op3(5) & op3(2 downto 0)) = "1110"))
then -- LDD/STD/LDSTUB/SWAP
cnt := "10"; pv := '0'; hold_pc := '1';
else
cnt := "00";
end if;
when "10" =>
cnt := "00";
when others => null;
end case;
end case;
end if;
if ldlock = '1' then
cnt := r.d.cnt; annul_next := '0'; pv := '1';
end if;
hold_pc := (hold_pc or ldlock) and not annul_all;
if hold_pc = '1' then de_pc := r.d.pc; else de_pc := r.f.pc; end if;
annul_current := (annul_current or ldlock or annul_all);
ctrl_annul := r.d.annul or annul_all or annul_current;
pv := pv and not ((r.d.inull and not hold_pc) or annul_all);
jmpl_inst := de_jmpl and not annul_current;
annul_next := (r.d.inull and not hold_pc) or annul_next or annul_all;
if (annul_next = '1') or (rstn = '0') then
cnt := (others => '0');
end if;
de_hold_pc := hold_pc; de_branch := branch; de_annul := annul_next;
de_pv := pv; ctrl_pv := r.d.pv and
not ((r.d.annul and not r.d.pv) or annul_all or annul_current);
inull := (not rstn) or r.d.inull or hold_pc or annul_all;
end;
-- register write address generation
procedure rd_gen(r : registers; inst : word; wreg, ld : out std_ulogic;
rdo : out std_logic_vector(4 downto 0)) is
variable write_reg : std_ulogic;
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
begin
op := inst(31 downto 30);
op2 := inst(24 downto 22);
op3 := inst(24 downto 19);
write_reg := '0'; rd := inst(29 downto 25); ld := '0';
case op is
when CALL =>
write_reg := '1'; rd := "01111"; -- CALL saves PC in r[15] (%o7)
when FMT2 =>
if (op2 = SETHI) then write_reg := '1'; end if;
when FMT3 =>
case op3 is
when UMUL | SMUL | UMULCC | SMULCC =>
if true then
if (((mulo.nready = '1') and (r.d.cnt /= "00")) or (0 /= 0)) then
write_reg := '1';
end if;
else write_reg := '1'; end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if true then
if (divo.nready = '1') and (r.d.cnt /= "00") then
write_reg := '1';
end if;
else write_reg := '1'; end if;
when RETT | WRPSR | WRY | WRWIM | WRTBR | TICC | FLUSH => null;
when FPOP1 | FPOP2 => null;
when CPOP1 | CPOP2 => null;
when others => write_reg := '1';
end case;
when others => -- LDST
ld := not op3(2);
if (op3(2) = '0') and not ((false or FPEN) and (op3(5) = '1'))
then write_reg := '1'; end if;
case op3 is
when SWAP | SWAPA | LDSTUB | LDSTUBA =>
if r.d.cnt = "00" then write_reg := '1'; ld := '1'; end if;
when others => null;
end case;
if r.d.cnt = "01" then
case op3 is
when LDD | LDDA | LDDC | LDDF => rd(0) := '1';
when others =>
end case;
end if;
end case;
if (rd = "00000") then write_reg := '0'; end if;
wreg := write_reg; rdo := rd;
end;
-- immediate data generation
function imm_data (r : registers; insn : word)
return word is
variable immediate_data, inst : word;
begin
immediate_data := (others => '0'); inst := insn;
case inst(31 downto 30) is
when FMT2 =>
immediate_data := inst(21 downto 0) & "0000000000";
when others => -- LDST
immediate_data(31 downto 13) := (others => inst(12));
immediate_data(12 downto 0) := inst(12 downto 0);
end case;
return(immediate_data);
end;
-- read special registers
function get_spr (r : registers) return word is
variable spr : word;
begin
spr := (others => '0');
case r.e.ctrl.inst(24 downto 19) is
when RDPSR => spr(31 downto 5) := conv_std_logic_vector(15,4) &
conv_std_logic_vector(3,4) & r.m.icc & "000000" & r.w.s.ec & r.w.s.ef &
r.w.s.pil & r.e.su & r.w.s.ps & r.e.et;
spr(3-1 downto 0) := r.e.cwp;
when RDTBR => spr(31 downto 4) := r.w.s.tba & r.w.s.tt;
when RDWIM => spr(8-1 downto 0) := r.w.s.wim;
when others =>
end case;
return(spr);
end;
-- immediate data select
function imm_select(inst : word) return boolean is
variable imm : boolean;
begin
imm := false;
case inst(31 downto 30) is
when FMT2 =>
case inst(24 downto 22) is
when SETHI => imm := true;
when others =>
end case;
when FMT3 =>
case inst(24 downto 19) is
when RDWIM | RDPSR | RDTBR => imm := true;
when others => if (inst(13) = '1') then imm := true; end if;
end case;
when LDST =>
if (inst(13) = '1') then imm := true; end if;
when others =>
end case;
return(imm);
end;
-- EXE operation
procedure alu_op(r : in registers; iop1, iop2 : in word; me_icc : std_logic_vector(3 downto 0);
my, ldbp : std_ulogic; aop1, aop2 : out word; aluop : out std_logic_vector(2 downto 0);
alusel : out std_logic_vector(1 downto 0); aluadd : out std_ulogic;
shcnt : out std_logic_vector(4 downto 0); sari, shleft, ymsb,
mulins, divins, mulstep, macins, ldbp2, invop2 : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable icc : std_logic_vector(3 downto 0);
variable y0 : std_ulogic;
begin
op := r.a.ctrl.inst(31 downto 30);
op2 := r.a.ctrl.inst(24 downto 22);
op3 := r.a.ctrl.inst(24 downto 19);
aop1 := iop1; aop2 := iop2; ldbp2 := ldbp;
aluop := EXE_NOP; alusel := EXE_RES_MISC; aluadd := '1';
shcnt := iop2(4 downto 0); sari := '0'; shleft := '0'; invop2 := '0';
ymsb := iop1(0); mulins := '0'; divins := '0'; mulstep := '0';
macins := '0';
if r.e.ctrl.wy = '1' then y0 := my;
elsif r.m.ctrl.wy = '1' then y0 := r.m.y(0);
elsif r.x.ctrl.wy = '1' then y0 := r.x.y(0);
else y0 := r.w.s.y(0); end if;
if r.e.ctrl.wicc = '1' then icc := me_icc;
elsif r.m.ctrl.wicc = '1' then icc := r.m.icc;
elsif r.x.ctrl.wicc = '1' then icc := r.x.icc;
else icc := r.w.s.icc; end if;
case op is
when CALL =>
aluop := EXE_LINK;
when FMT2 =>
case op2 is
when SETHI => aluop := EXE_PASS2;
when others =>
end case;
when FMT3 =>
case op3 is
when IADD | ADDX | ADDCC | ADDXCC | TADDCC | TADDCCTV | SAVE | RESTORE |
TICC | JMPL | RETT => alusel := EXE_RES_ADD;
when ISUB | SUBX | SUBCC | SUBXCC | TSUBCC | TSUBCCTV =>
alusel := EXE_RES_ADD; aluadd := '0'; aop2 := not iop2; invop2 := '1';
when MULSCC => alusel := EXE_RES_ADD;
aop1 := (icc(3) xor icc(1)) & iop1(31 downto 1);
if y0 = '0' then aop2 := (others => '0'); ldbp2 := '0'; end if;
mulstep := '1';
when UMUL | UMULCC | SMUL | SMULCC =>
if true then mulins := '1'; end if;
when UMAC | SMAC =>
if false then mulins := '1'; macins := '1'; end if;
when UDIV | UDIVCC | SDIV | SDIVCC =>
if true then
aluop := EXE_DIV; alusel := EXE_RES_LOGIC; divins := '1';
end if;
when IAND | ANDCC => aluop := EXE_AND; alusel := EXE_RES_LOGIC;
when ANDN | ANDNCC => aluop := EXE_ANDN; alusel := EXE_RES_LOGIC;
when IOR | ORCC => aluop := EXE_OR; alusel := EXE_RES_LOGIC;
when ORN | ORNCC => aluop := EXE_ORN; alusel := EXE_RES_LOGIC;
when IXNOR | XNORCC => aluop := EXE_XNOR; alusel := EXE_RES_LOGIC;
when XORCC | IXOR | WRPSR | WRWIM | WRTBR | WRY =>
aluop := EXE_XOR; alusel := EXE_RES_LOGIC;
when RDPSR | RDTBR | RDWIM => aluop := EXE_SPR;
when RDY => aluop := EXE_RDY;
when ISLL => aluop := EXE_SLL; alusel := EXE_RES_SHIFT; shleft := '1';
shcnt := not iop2(4 downto 0); invop2 := '1';
when ISRL => aluop := EXE_SRL; alusel := EXE_RES_SHIFT;
when ISRA => aluop := EXE_SRA; alusel := EXE_RES_SHIFT; sari := iop1(31);
when FPOP1 | FPOP2 =>
when others =>
end case;
when others => -- LDST
case r.a.ctrl.cnt is
when "00" =>
alusel := EXE_RES_ADD;
when "01" =>
case op3 is
when LDD | LDDA | LDDC => alusel := EXE_RES_ADD;
when LDDF => alusel := EXE_RES_ADD;
when SWAP | SWAPA | LDSTUB | LDSTUBA => alusel := EXE_RES_ADD;
when STF | STDF =>
when others =>
aluop := EXE_PASS1;
if op3(2) = '1' then
if op3(1 downto 0) = "01" then aluop := EXE_STB;
elsif op3(1 downto 0) = "10" then aluop := EXE_STH; end if;
end if;
end case;
when "10" =>
aluop := EXE_PASS1;
if op3(2) = '1' then -- ST
if (op3(3) and not op3(1))= '1' then aluop := EXE_ONES; end if; -- LDSTUB/A
end if;
when others =>
end case;
end case;
end;
function ra_inull_gen(r, v : registers) return std_ulogic is
variable de_inull : std_ulogic;
begin
de_inull := '0';
if ((v.e.jmpl or v.e.ctrl.rett) and not v.e.ctrl.annul and not (r.e.jmpl and not r.e.ctrl.annul)) = '1' then de_inull := '1'; end if;
if ((v.a.jmpl or v.a.ctrl.rett) and not v.a.ctrl.annul and not (r.a.jmpl and not r.a.ctrl.annul)) = '1' then de_inull := '1'; end if;
return(de_inull);
end;
-- operand generation
procedure op_mux(r : in registers; rfd, ed, md, xd, im : in word;
rsel : in std_logic_vector(2 downto 0);
ldbp : out std_ulogic; d : out word) is
begin
ldbp := '0';
case rsel is
when "000" => d := rfd;
when "001" => d := ed;
when "010" => d := md; if lddel = 1 then ldbp := r.m.ctrl.ld; end if;
when "011" => d := xd;
when "100" => d := im;
when "101" => d := (others => '0');
when "110" => d := r.w.result;
when others => d := (others => '-');
end case;
end;
procedure op_find(r : in registers; ldchkra : std_ulogic; ldchkex : std_ulogic;
rs1 : std_logic_vector(4 downto 0); ra : rfatype; im : boolean; rfe : out std_ulogic;
osel : out std_logic_vector(2 downto 0); ldcheck : std_ulogic) is
begin
rfe := '0';
if im then osel := "100";
elsif rs1 = "00000" then osel := "101"; -- %g0
elsif ((r.a.ctrl.wreg and ldchkra) = '1') and (ra = r.a.ctrl.rd) then osel := "001";
elsif ((r.e.ctrl.wreg and ldchkex) = '1') and (ra = r.e.ctrl.rd) then osel := "010";
elsif r.m.ctrl.wreg = '1' and (ra = r.m.ctrl.rd) then osel := "011";
elsif (irfwt = 0) and r.x.ctrl.wreg = '1' and (ra = r.x.ctrl.rd) then osel := "110";
else osel := "000"; rfe := ldcheck; end if;
end;
-- generate carry-in for alu
procedure cin_gen(r : registers; me_cin : in std_ulogic; cin : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable ncin : std_ulogic;
begin
op := r.a.ctrl.inst(31 downto 30); op3 := r.a.ctrl.inst(24 downto 19);
if r.e.ctrl.wicc = '1' then ncin := me_cin;
else ncin := r.m.icc(0); end if;
cin := '0';
case op is
when FMT3 =>
case op3 is
when ISUB | SUBCC | TSUBCC | TSUBCCTV => cin := '1';
when ADDX | ADDXCC => cin := ncin;
when SUBX | SUBXCC => cin := not ncin;
when others => null;
end case;
when others => null;
end case;
end;
procedure logic_op(r : registers; aluin1, aluin2, mey : word;
ymsb : std_ulogic; logicres, y : out word) is
variable logicout : word;
begin
case r.e.aluop is
when EXE_AND => logicout := aluin1 and aluin2;
when EXE_ANDN => logicout := aluin1 and not aluin2;
when EXE_OR => logicout := aluin1 or aluin2;
when EXE_ORN => logicout := aluin1 or not aluin2;
when EXE_XOR => logicout := aluin1 xor aluin2;
when EXE_XNOR => logicout := aluin1 xor not aluin2;
when EXE_DIV =>
if true then logicout := aluin2;
else logicout := (others => '-'); end if;
when others => logicout := (others => '-');
end case;
if (r.e.ctrl.wy and r.e.mulstep) = '1' then
y := ymsb & r.m.y(31 downto 1);
elsif r.e.ctrl.wy = '1' then y := logicout;
elsif r.m.ctrl.wy = '1' then y := mey;
elsif false and (r.x.mac = '1') then y := mulo.result(63 downto 32);
elsif r.x.ctrl.wy = '1' then y := r.x.y;
else y := r.w.s.y; end if;
logicres := logicout;
end;
procedure misc_op(r : registers; wpr : watchpoint_registers;
aluin1, aluin2, ldata, mey : word;
mout, edata : out word) is
variable miscout, bpdata, stdata : word;
variable wpi : integer;
begin
wpi := 0; miscout := r.e.ctrl.pc(31 downto 2) & "00";
edata := aluin1; bpdata := aluin1;
if ((r.x.ctrl.wreg and r.x.ctrl.ld and not r.x.ctrl.annul) = '1') and
(r.x.ctrl.rd = r.e.ctrl.rd) and (r.e.ctrl.inst(31 downto 30) = LDST) and
(r.e.ctrl.cnt /= "10")
then bpdata := ldata; end if;
case r.e.aluop is
when EXE_STB => miscout := bpdata(7 downto 0) & bpdata(7 downto 0) &
bpdata(7 downto 0) & bpdata(7 downto 0);
edata := miscout;
when EXE_STH => miscout := bpdata(15 downto 0) & bpdata(15 downto 0);
edata := miscout;
when EXE_PASS1 => miscout := bpdata; edata := miscout;
when EXE_PASS2 => miscout := aluin2;
when EXE_ONES => miscout := (others => '1');
edata := miscout;
when EXE_RDY =>
if true and (r.m.ctrl.wy = '1') then miscout := mey;
else miscout := r.m.y; end if;
if (NWP > 0) and (r.e.ctrl.inst(18 downto 17) = "11") then
wpi := conv_integer(r.e.ctrl.inst(16 downto 15));
if r.e.ctrl.inst(14) = '0' then miscout := wpr(wpi).addr & '0' & wpr(wpi).exec;
else miscout := wpr(wpi).mask & wpr(wpi).load & wpr(wpi).store; end if;
end if;
if (r.e.ctrl.inst(18 downto 17) = "10") and (r.e.ctrl.inst(14) = '1') then --%ASR17
miscout := asr17_gen(r);
end if;
if false then
if (r.e.ctrl.inst(18 downto 14) = "10010") then --%ASR18
if ((r.m.mac = '1') and not false) or ((r.x.mac = '1') and false) then
miscout := mulo.result(31 downto 0); -- data forward of asr18
else miscout := r.w.s.asr18; end if;
else
if ((r.m.mac = '1') and not false) or ((r.x.mac = '1') and false) then
miscout := mulo.result(63 downto 32); -- data forward Y
end if;
end if;
end if;
when EXE_SPR =>
miscout := get_spr(r);
when others => null;
end case;
mout := miscout;
end;
procedure alu_select(r : registers; addout : std_logic_vector(32 downto 0);
op1, op2 : word; shiftout, logicout, miscout : word; res : out word;
me_icc : std_logic_vector(3 downto 0);
icco : out std_logic_vector(3 downto 0); divz : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable icc : std_logic_vector(3 downto 0);
variable aluresult : word;
begin
op := r.e.ctrl.inst(31 downto 30); op3 := r.e.ctrl.inst(24 downto 19);
icc := (others => '0');
case r.e.alusel is
when EXE_RES_ADD =>
aluresult := addout(32 downto 1);
if r.e.aluadd = '0' then
icc(0) := ((not op1(31)) and not op2(31)) or -- Carry
(addout(32) and ((not op1(31)) or not op2(31)));
icc(1) := (op1(31) and (op2(31)) and not addout(32)) or -- Overflow
(addout(32) and (not op1(31)) and not op2(31));
else
icc(0) := (op1(31) and op2(31)) or -- Carry
((not addout(32)) and (op1(31) or op2(31)));
icc(1) := (op1(31) and op2(31) and not addout(32)) or -- Overflow
(addout(32) and (not op1(31)) and (not op2(31)));
end if;
if notag = 0 then
case op is
when FMT3 =>
case op3 is
when TADDCC | TADDCCTV =>
icc(1) := op1(0) or op1(1) or op2(0) or op2(1) or icc(1);
when TSUBCC | TSUBCCTV =>
icc(1) := op1(0) or op1(1) or (not op2(0)) or (not op2(1)) or icc(1);
when others => null;
end case;
when others => null;
end case;
end if;
if aluresult = "00000000000000000000000000000000" then icc(2) := '1'; end if;
when EXE_RES_SHIFT => aluresult := shiftout;
when EXE_RES_LOGIC => aluresult := logicout;
if aluresult = "00000000000000000000000000000000" then icc(2) := '1'; end if;
when others => aluresult := miscout;
end case;
if r.e.jmpl = '1' then aluresult := r.e.ctrl.pc(31 downto 2) & "00"; end if;
icc(3) := aluresult(31); divz := icc(2);
if r.e.ctrl.wicc = '1' then
if (op = FMT3) and (op3 = WRPSR) then icco := logicout(23 downto 20);
else icco := icc; end if;
elsif r.m.ctrl.wicc = '1' then icco := me_icc;
elsif r.x.ctrl.wicc = '1' then icco := r.x.icc;
else icco := r.w.s.icc; end if;
res := aluresult;
end;
procedure dcache_gen(r, v : registers; dci : out dc_in_type;
link_pc, jump, force_a2, load : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable su : std_ulogic;
begin
op := r.e.ctrl.inst(31 downto 30); op3 := r.e.ctrl.inst(24 downto 19);
dci.signed := '0'; dci.lock := '0'; dci.dsuen := '0'; dci.size := SZWORD;
if op = LDST then
case op3 is
when LDUB | LDUBA => dci.size := SZBYTE;
when LDSTUB | LDSTUBA => dci.size := SZBYTE; dci.lock := '1';
when LDUH | LDUHA => dci.size := SZHALF;
when LDSB | LDSBA => dci.size := SZBYTE; dci.signed := '1';
when LDSH | LDSHA => dci.size := SZHALF; dci.signed := '1';
when LD | LDA | LDF | LDC => dci.size := SZWORD;
when SWAP | SWAPA => dci.size := SZWORD; dci.lock := '1';
when LDD | LDDA | LDDF | LDDC => dci.size := SZDBL;
when STB | STBA => dci.size := SZBYTE;
when STH | STHA => dci.size := SZHALF;
when ST | STA | STF => dci.size := SZWORD;
when ISTD | STDA => dci.size := SZDBL;
when STDF | STDFQ => if FPEN then dci.size := SZDBL; end if;
when STDC | STDCQ => if false then dci.size := SZDBL; end if;
when others => dci.size := SZWORD; dci.lock := '0'; dci.signed := '0';
end case;
end if;
link_pc := '0'; jump:= '0'; force_a2 := '0'; load := '0';
dci.write := '0'; dci.enaddr := '0'; dci.read := not op3(2);
-- load/store control decoding
if (r.e.ctrl.annul = '0') then
case op is
when CALL => link_pc := '1';
when FMT3 =>
case op3 is
when JMPL => jump := '1'; link_pc := '1';
when RETT => jump := '1';
when others => null;
end case;
when LDST =>
case r.e.ctrl.cnt is
when "00" =>
dci.read := op3(3) or not op3(2); -- LD/LDST/SWAP
load := op3(3) or not op3(2);
dci.enaddr := '1';
when "01" =>
force_a2 := not op3(2); -- LDD
load := not op3(2); dci.enaddr := not op3(2);
if op3(3 downto 2) = "01" then -- ST/STD
dci.write := '1';
end if;
if op3(3 downto 2) = "11" then -- LDST/SWAP
dci.enaddr := '1';
end if;
when "10" => -- STD/LDST/SWAP
dci.write := '1';
when others => null;
end case;
if (r.e.ctrl.trap or (v.x.ctrl.trap and not v.x.ctrl.annul)) = '1' then
dci.enaddr := '0';
end if;
when others => null;
end case;
end if;
if ((r.x.ctrl.rett and not r.x.ctrl.annul) = '1') then su := r.w.s.ps;
else su := r.w.s.s; end if;
if su = '1' then dci.asi := "00001011"; else dci.asi := "00001010"; end if;
if (op3(4) = '1') and ((op3(5) = '0') or not false) then
dci.asi := r.e.ctrl.inst(12 downto 5);
end if;
end;
procedure fpstdata(r : in registers; edata, eres : in word; fpstdata : in std_logic_vector(31 downto 0);
edata2, eres2 : out word) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
begin
edata2 := edata; eres2 := eres;
op := r.e.ctrl.inst(31 downto 30); op3 := r.e.ctrl.inst(24 downto 19);
if FPEN then
if FPEN and (op = LDST) and ((op3(5 downto 4) & op3(2)) = "101") and (r.e.ctrl.cnt /= "00") then
edata2 := fpstdata; eres2 := fpstdata;
end if;
end if;
end;
function ld_align(data : dcdtype; set : std_logic_vector(0 downto 0);
size, laddr : std_logic_vector(1 downto 0); signed : std_ulogic) return word is
variable align_data, rdata : word;
begin
align_data := data(conv_integer(set)); rdata := (others => '0');
case size is
when "00" => -- byte read
case laddr is
when "00" =>
rdata(7 downto 0) := align_data(31 downto 24);
if signed = '1' then rdata(31 downto 8) := (others => align_data(31)); end if;
when "01" =>
rdata(7 downto 0) := align_data(23 downto 16);
if signed = '1' then rdata(31 downto 8) := (others => align_data(23)); end if;
when "10" =>
rdata(7 downto 0) := align_data(15 downto 8);
if signed = '1' then rdata(31 downto 8) := (others => align_data(15)); end if;
when others =>
rdata(7 downto 0) := align_data(7 downto 0);
if signed = '1' then rdata(31 downto 8) := (others => align_data(7)); end if;
end case;
when "01" => -- half-word read
if laddr(1) = '1' then
rdata(15 downto 0) := align_data(15 downto 0);
if signed = '1' then rdata(31 downto 15) := (others => align_data(15)); end if;
else
rdata(15 downto 0) := align_data(31 downto 16);
if signed = '1' then rdata(31 downto 15) := (others => align_data(31)); end if;
end if;
when others => -- single and double word read
rdata := align_data;
end case;
return(rdata);
end;
procedure mem_trap(r : registers; wpr : watchpoint_registers;
annul, holdn : in std_ulogic;
trapout, iflush, nullify, werrout : out std_ulogic;
tt : out std_logic_vector(5 downto 0)) is
variable cwp : std_logic_vector(3-1 downto 0);
variable cwpx : std_logic_vector(5 downto 3);
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable nalign_d : std_ulogic;
variable trap, werr : std_ulogic;
begin
op := r.m.ctrl.inst(31 downto 30); op2 := r.m.ctrl.inst(24 downto 22);
op3 := r.m.ctrl.inst(24 downto 19);
cwpx := r.m.result(5 downto 3); cwpx(5) := '0';
iflush := '0'; trap := r.m.ctrl.trap; nullify := annul;
tt := r.m.ctrl.tt; werr := (dco.werr or r.m.werr) and not r.w.s.dwt;
nalign_d := r.m.nalign or r.m.result(2);
if ((annul or trap) /= '1') and (r.m.ctrl.pv = '1') then
if (werr and holdn) = '1' then
trap := '1'; tt := TT_DSEX; werr := '0';
if op = LDST then nullify := '1'; end if;
end if;
end if;
if ((annul or trap) /= '1') then
case op is
when FMT2 =>
case op2 is
when FBFCC =>
if FPEN and (fpo.exc = '1') then trap := '1'; tt := TT_FPEXC; end if;
when CBCCC =>
if false and (cpo.exc = '1') then trap := '1'; tt := TT_CPEXC; end if;
when others => null;
end case;
when FMT3 =>
case op3 is
when WRPSR =>
if (orv(cwpx) = '1') then trap := '1'; tt := TT_IINST; end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if true then
if r.m.divz = '1' then trap := '1'; tt := TT_DIV; end if;
end if;
when JMPL | RETT =>
if r.m.nalign = '1' then trap := '1'; tt := TT_UNALA; end if;
when TADDCCTV | TSUBCCTV =>
if (notag = 0) and (r.m.icc(1) = '1') then
trap := '1'; tt := TT_TAG;
end if;
when FLUSH => iflush := '1';
when FPOP1 | FPOP2 =>
if FPEN and (fpo.exc = '1') then trap := '1'; tt := TT_FPEXC; end if;
when CPOP1 | CPOP2 =>
if false and (cpo.exc = '1') then trap := '1'; tt := TT_CPEXC; end if;
when others => null;
end case;
when LDST =>
if r.m.ctrl.cnt = "00" then
case op3 is
when LDDF | STDF | STDFQ =>
if FPEN then
if nalign_d = '1' then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif (fpo.exc and r.m.ctrl.pv) = '1'
then trap := '1'; tt := TT_FPEXC; nullify := '1'; end if;
end if;
when LDDC | STDC | STDCQ =>
if false then
if nalign_d = '1' then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif ((cpo.exc and r.m.ctrl.pv) = '1')
then trap := '1'; tt := TT_CPEXC; nullify := '1'; end if;
end if;
when LDD | ISTD | LDDA | STDA =>
if r.m.result(2 downto 0) /= "000" then
trap := '1'; tt := TT_UNALA; nullify := '1';
end if;
when LDF | LDFSR | STFSR | STF =>
if FPEN and (r.m.nalign = '1') then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif FPEN and ((fpo.exc and r.m.ctrl.pv) = '1')
then trap := '1'; tt := TT_FPEXC; nullify := '1'; end if;
when LDC | LDCSR | STCSR | STC =>
if false and (r.m.nalign = '1') then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif false and ((cpo.exc and r.m.ctrl.pv) = '1')
then trap := '1'; tt := TT_CPEXC; nullify := '1'; end if;
when LD | LDA | ST | STA | SWAP | SWAPA =>
if r.m.result(1 downto 0) /= "00" then
trap := '1'; tt := TT_UNALA; nullify := '1';
end if;
when LDUH | LDUHA | LDSH | LDSHA | STH | STHA =>
if r.m.result(0) /= '0' then
trap := '1'; tt := TT_UNALA; nullify := '1';
end if;
when others => null;
end case;
for i in 1 to NWP loop
if ((((wpr(i-1).load and not op3(2)) or (wpr(i-1).store and op3(2))) = '1') and
(((wpr(i-1).addr xor r.m.result(31 downto 2)) and wpr(i-1).mask) = "000000000000000000000000000000"))
then trap := '1'; tt := TT_WATCH; nullify := '1'; end if;
end loop;
end if;
when others => null;
end case;
end if;
if (rstn = '0') or (r.x.rstate = dsu2) then werr := '0'; end if;
trapout := trap; werrout := werr;
end;
procedure irq_trap(r : in registers;
ir : in irestart_register;
irl : in std_logic_vector(3 downto 0);
annul : in std_ulogic;
pv : in std_ulogic;
trap : in std_ulogic;
tt : in std_logic_vector(5 downto 0);
nullify : in std_ulogic;
irqen : out std_ulogic;
irqen2 : out std_ulogic;
nullify2 : out std_ulogic;
trap2, ipend : out std_ulogic;
tt2 : out std_logic_vector(5 downto 0)) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable pend : std_ulogic;
begin
nullify2 := nullify; trap2 := trap; tt2 := tt;
op := r.m.ctrl.inst(31 downto 30); op3 := r.m.ctrl.inst(24 downto 19);
irqen := '1'; irqen2 := r.m.irqen;
if (annul or trap) = '0' then
if ((op = FMT3) and (op3 = WRPSR)) then irqen := '0'; end if;
end if;
if (irl = "1111") or (irl > r.w.s.pil) then
pend := r.m.irqen and r.m.irqen2 and r.w.s.et and not ir.pwd;
else pend := '0'; end if;
ipend := pend;
if ((not annul) and pv and (not trap) and pend) = '1' then
trap2 := '1'; tt2 := "01" & irl;
if op = LDST then nullify2 := '1'; end if;
end if;
end;
procedure irq_intack(r : in registers; holdn : in std_ulogic; intack: out std_ulogic) is
begin
intack := '0';
if r.x.rstate = trap then
if r.w.s.tt(7 downto 4) = "0001" then intack := '1'; end if;
end if;
end;
-- write special registers
procedure sp_write (r : registers; wpr : watchpoint_registers;
s : out special_register_type; vwpr : out watchpoint_registers) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable i : integer range 0 to 3;
begin
op := r.x.ctrl.inst(31 downto 30);
op2 := r.x.ctrl.inst(24 downto 22);
op3 := r.x.ctrl.inst(24 downto 19);
s := r.w.s;
rd := r.x.ctrl.inst(29 downto 25);
vwpr := wpr;
case op is
when FMT3 =>
case op3 is
when WRY =>
if rd = "00000" then
s.y := r.x.result;
elsif false and (rd = "10010") then
s.asr18 := r.x.result;
elsif (rd = "10001") then
s.dwt := r.x.result(14);
if (svt = 1) then s.svt := r.x.result(13); end if;
elsif rd(4 downto 3) = "11" then -- %ASR24 - %ASR31
case rd(2 downto 0) is
when "000" =>
vwpr(0).addr := r.x.result(31 downto 2);
vwpr(0).exec := r.x.result(0);
when "001" =>
vwpr(0).mask := r.x.result(31 downto 2);
vwpr(0).load := r.x.result(1);
vwpr(0).store := r.x.result(0);
when "010" =>
vwpr(1).addr := r.x.result(31 downto 2);
vwpr(1).exec := r.x.result(0);
when "011" =>
vwpr(1).mask := r.x.result(31 downto 2);
vwpr(1).load := r.x.result(1);
vwpr(1).store := r.x.result(0);
when "100" =>
vwpr(2).addr := r.x.result(31 downto 2);
vwpr(2).exec := r.x.result(0);
when "101" =>
vwpr(2).mask := r.x.result(31 downto 2);
vwpr(2).load := r.x.result(1);
vwpr(2).store := r.x.result(0);
when "110" =>
vwpr(3).addr := r.x.result(31 downto 2);
vwpr(3).exec := r.x.result(0);
when others => -- "111"
vwpr(3).mask := r.x.result(31 downto 2);
vwpr(3).load := r.x.result(1);
vwpr(3).store := r.x.result(0);
end case;
end if;
when WRPSR =>
s.cwp := r.x.result(3-1 downto 0);
s.icc := r.x.result(23 downto 20);
s.ec := r.x.result(13);
if FPEN then s.ef := r.x.result(12); end if;
s.pil := r.x.result(11 downto 8);
s.s := r.x.result(7);
s.ps := r.x.result(6);
s.et := r.x.result(5);
when WRWIM =>
s.wim := r.x.result(8-1 downto 0);
when WRTBR =>
s.tba := r.x.result(31 downto 12);
when SAVE =>
if (not true) and (r.w.s.cwp = "000") then s.cwp := "111";
else s.cwp := r.w.s.cwp - 1 ; end if;
when RESTORE =>
if (not true) and (r.w.s.cwp = "111") then s.cwp := "000";
else s.cwp := r.w.s.cwp + 1; end if;
when RETT =>
if (not true) and (r.w.s.cwp = "111") then s.cwp := "000";
else s.cwp := r.w.s.cwp + 1; end if;
s.s := r.w.s.ps;
s.et := '1';
when others => null;
end case;
when others => null;
end case;
if r.x.ctrl.wicc = '1' then s.icc := r.x.icc; end if;
if r.x.ctrl.wy = '1' then s.y := r.x.y; end if;
if false and (r.x.mac = '1') then
s.asr18 := mulo.result(31 downto 0);
s.y := mulo.result(63 downto 32);
end if;
end;
function npc_find (r : registers) return std_logic_vector is
variable npc : std_logic_vector(2 downto 0);
begin
npc := "011";
if r.m.ctrl.pv = '1' then npc := "000";
elsif r.e.ctrl.pv = '1' then npc := "001";
elsif r.a.ctrl.pv = '1' then npc := "010";
elsif r.d.pv = '1' then npc := "011";
elsif 2 /= 0 then npc := "100"; end if;
return(npc);
end;
function npc_gen (r : registers) return word is
variable npc : std_logic_vector(31 downto 0);
begin
npc := r.a.ctrl.pc(31 downto 2) & "00";
case r.x.npc is
when "000" => npc(31 downto 2) := r.x.ctrl.pc(31 downto 2);
when "001" => npc(31 downto 2) := r.m.ctrl.pc(31 downto 2);
when "010" => npc(31 downto 2) := r.e.ctrl.pc(31 downto 2);
when "011" => npc(31 downto 2) := r.a.ctrl.pc(31 downto 2);
when others =>
if 2 /= 0 then npc(31 downto 2) := r.d.pc(31 downto 2); end if;
end case;
return(npc);
end;
procedure mul_res(r : registers; asr18in : word; result, y, asr18 : out word;
icc : out std_logic_vector(3 downto 0)) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
begin
op := r.m.ctrl.inst(31 downto 30); op3 := r.m.ctrl.inst(24 downto 19);
result := r.m.result; y := r.m.y; icc := r.m.icc; asr18 := asr18in;
case op is
when FMT3 =>
case op3 is
when UMUL | SMUL =>
if true then
result := mulo.result(31 downto 0);
y := mulo.result(63 downto 32);
end if;
when UMULCC | SMULCC =>
if true then
result := mulo.result(31 downto 0); icc := mulo.icc;
y := mulo.result(63 downto 32);
end if;
when UMAC | SMAC =>
if false and not false then
result := mulo.result(31 downto 0);
asr18 := mulo.result(31 downto 0);
y := mulo.result(63 downto 32);
end if;
when UDIV | SDIV =>
if true then
result := divo.result(31 downto 0);
end if;
when UDIVCC | SDIVCC =>
if true then
result := divo.result(31 downto 0); icc := divo.icc;
end if;
when others => null;
end case;
when others => null;
end case;
end;
function powerdwn(r : registers; trap : std_ulogic; rp : pwd_register_type) return std_ulogic is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable pd : std_ulogic;
begin
op := r.x.ctrl.inst(31 downto 30);
op3 := r.x.ctrl.inst(24 downto 19);
rd := r.x.ctrl.inst(29 downto 25);
pd := '0';
if (not (r.x.ctrl.annul or trap) and r.x.ctrl.pv) = '1' then
if ((op = FMT3) and (op3 = WRY) and (rd = "10011")) then pd := '1'; end if;
pd := pd or rp.pwd;
end if;
return(pd);
end;
signal dummy : std_ulogic;
signal cpu_index : std_logic_vector(3 downto 0);
signal disasen : std_ulogic;
-- Signals used for tracking if a handler fired and which one
signal dfp_trap_vector : std_logic_vector(123 downto 0);
signal or_reduce_1 : std_logic;
signal dfp_delay_start : integer range 0 to 15;
signal dfp_trap_mem : std_logic_vector(dfp_trap_vector'left downto dfp_trap_vector'right);
signal handlerTrap : std_ulogic;
-- Signals that serve as shadow signals for variables used in the pairs
signal V_A_ET_shadow : STD_ULOGIC;
signal EX_ADD_RES32DOWNTO34DOWNTO3_shadow : STD_LOGIC_VECTOR(4 downto 3);
signal ICNT_shadow : STD_ULOGIC;
signal EX_OP1_shadow : WORD;
signal V_M_CTRL_PC_shadow : PCTYPE;
signal V_E_CTRL_PC3DOWNTO2_shadow : std_logic_vector(3 downto 2);
signal DE_REN1_shadow : STD_ULOGIC;
signal DE_INST_shadow : WORD;
signal V_A_CTRL_CNT_shadow : OP_TYPE;
signal V_F_PC3DOWNTO2_shadow : std_logic_vector(3 downto 2);
signal V_W_S_TT_shadow : STD_LOGIC_VECTOR(7 downto 0);
signal V_X_RESULT6DOWNTO0_shadow : std_logic_vector(6 downto 0);
signal EX_JUMP_ADDRESS3DOWNTO2_shadow : std_logic_vector(3 downto 2);
signal V_E_ALUCIN_shadow : STD_ULOGIC;
signal V_D_PC3DOWNTO2_shadow : std_logic_vector(3 downto 2);
signal V_A_CTRL_PV_shadow : STD_ULOGIC;
signal V_E_CTRL_shadow : PIPELINE_CTRL_TYPE;
signal V_M_CTRL_shadow : PIPELINE_CTRL_TYPE;
signal V_M_RESULT1DOWNTO0_shadow : std_logic_vector(1 downto 0);
signal EX_SHCNT_shadow : ASI_TYPE;
signal V_M_DCI_SIZE_shadow : OP_TYPE;
signal V_X_CTRL_ANNUL_shadow : STD_ULOGIC;
signal V_X_MEXC_shadow : STD_ULOGIC;
signal TBUFCNTX_shadow : STD_LOGIC_VECTOR(6 downto 0);
signal V_A_CTRL_WY_shadow : STD_ULOGIC;
signal NPC_shadow : PCTYPE;
signal V_M_CTRL_TT3DOWNTO0_shadow : std_logic_vector(3 downto 0);
signal V_A_MULSTART_shadow : STD_ULOGIC;
signal XC_VECTT3DOWNTO0_shadow : STD_LOGIC_VECTOR(3 downto 0);
signal V_E_CTRL_TT_shadow : OP3_TYPE;
signal DSIGN_shadow : STD_ULOGIC;
signal V_E_CTRL_ANNUL_shadow : STD_ULOGIC;
signal EX_JUMP_ADDRESS_shadow : PCTYPE;
signal V_A_CTRL_PC31DOWNTO12_shadow : std_logic_vector(31 downto 12);
signal V_A_RFE1_shadow : STD_ULOGIC;
signal V_W_WA_shadow : RFATYPE;
signal V_X_ANNUL_ALL_shadow : STD_ULOGIC;
signal EX_YMSB_shadow : STD_ULOGIC;
signal EX_ADD_RES_shadow : STD_LOGIC_VECTOR(32 downto 0);
signal VIR_ADDR_shadow : PCTYPE;
signal EX_JUMP_ADDRESS31DOWNTO12_shadow : std_logic_vector(31 downto 12);
signal V_W_S_CWP_shadow : CWPTYPE;
signal V_D_INST0_shadow : std_logic_vector(31 downto 0);
signal V_A_CTRL_ANNUL_shadow : STD_ULOGIC;
signal V_X_DATA1_shadow : std_logic_vector(31 downto 0);
signal VP_PWD_shadow : STD_ULOGIC;
signal V_M_CTRL_RD6DOWNTO0_shadow : std_logic_vector(6 downto 0);
signal V_X_DATA00_shadow : STD_LOGIC;
signal V_M_CTRL_RETT_shadow : STD_ULOGIC;
signal V_X_CTRL_RETT_shadow : STD_ULOGIC;
signal V_X_CTRL_PC31DOWNTO12_shadow : std_logic_vector(31 downto 12);
signal V_W_S_PS_shadow : STD_ULOGIC;
signal V_X_CTRL_TT_shadow : OP3_TYPE;
signal V_D_STEP_shadow : STD_ULOGIC;
signal V_X_CTRL_WICC_shadow : STD_ULOGIC;
signal VIR_ADDR31DOWNTO2_shadow : std_logic_vector(31 downto 2);
signal V_M_CTRL_RD7DOWNTO0_shadow : std_logic_vector(7 downto 0);
signal V_X_RESULT_shadow : WORD;
signal V_D_CNT_shadow : OP_TYPE;
signal XC_VECTT_shadow : STD_LOGIC_VECTOR(7 downto 0);
signal EX_ADD_RES32DOWNTO3_shadow : STD_LOGIC_VECTOR(32 downto 3);
signal V_W_S_EF_shadow : STD_ULOGIC;
signal V_A_CTRL_PC31DOWNTO2_shadow : std_logic_vector(31 downto 2);
signal V_X_DATA04DOWNTO0_shadow : std_logic_vector(4 downto 0);
signal V_X_DCI_SIGNED_shadow : STD_ULOGIC;
signal V_M_NALIGN_shadow : STD_ULOGIC;
signal XC_WREG_shadow : STD_ULOGIC;
signal V_A_RFA2_shadow : RFATYPE;
signal V_E_CTRL_PC31DOWNTO12_shadow : std_logic_vector(31 downto 12);
signal EX_ADD_RES32DOWNTO332DOWNTO13_shadow : STD_LOGIC_VECTOR(32 downto 13);
signal EX_OP231_shadow : STD_LOGIC;
signal XC_TRAP_ADDRESS31DOWNTO4_shadow : std_logic_vector(31 downto 4);
signal V_X_ICC_shadow : STD_LOGIC_VECTOR(3 downto 0);
signal V_A_SU_shadow : STD_ULOGIC;
signal V_E_OP2_shadow : WORD;
signal EX_FORCE_A2_shadow : STD_ULOGIC;
signal V_E_CTRL_PC31DOWNTO2_shadow : std_logic_vector(31 downto 2);
signal V_E_CTRL_PC31DOWNTO4_shadow : std_logic_vector(31 downto 4);
signal V_E_OP131_shadow : STD_LOGIC;
signal V_X_DCI_shadow : DC_IN_TYPE;
signal V_E_CTRL_WICC_shadow : STD_ULOGIC;
signal EX_OP13_shadow : STD_LOGIC;
signal V_F_PC31DOWNTO12_shadow : std_logic_vector(31 downto 12);
signal V_E_CTRL_INST_shadow : WORD;
signal V_E_CTRL_LD_shadow : STD_ULOGIC;
signal V_M_SU_shadow : STD_ULOGIC;
signal V_E_SARI_shadow : STD_ULOGIC;
signal V_E_ET_shadow : STD_ULOGIC;
signal V_M_CTRL_PV_shadow : STD_ULOGIC;
signal VDSU_CRDY2_shadow : STD_LOGIC;
signal MUL_OP2_shadow : WORD;
signal XC_EXCEPTION_shadow : STD_ULOGIC;
signal V_E_OP1_shadow : WORD;
signal VP_ERROR_shadow : STD_ULOGIC;
signal V_M_DCI_SIGNED_shadow : STD_ULOGIC;
signal V_D_PC31DOWNTO12_shadow : std_logic_vector(31 downto 12);
signal MUL_OP231_shadow : STD_LOGIC;
signal XC_TRAP_ADDRESS31DOWNTO2_shadow : std_logic_vector(31 downto 2);
signal V_M_CTRL_PC3DOWNTO2_shadow : std_logic_vector(3 downto 2);
signal V_M_DCI_shadow : DC_IN_TYPE;
signal EX_OP23_shadow : STD_LOGIC;
signal V_X_CTRL_RD6DOWNTO0_shadow : std_logic_vector(6 downto 0);
signal V_X_CTRL_TRAP_shadow : STD_ULOGIC;
signal V_A_DIVSTART_shadow : STD_ULOGIC;
signal V_X_RESULT6DOWNTO03DOWNTO0_shadow : std_logic_vector(3 downto 0);
signal VDSU_TT_shadow : STD_LOGIC_VECTOR(7 downto 0);
signal EX_ADD_RES32DOWNTO332DOWNTO5_shadow : STD_LOGIC_VECTOR(32 downto 5);
signal V_X_CTRL_CNT_shadow : OP_TYPE;
signal V_E_YMSB_shadow : STD_ULOGIC;
signal EX_ADD_RES32DOWNTO330DOWNTO11_shadow : STD_LOGIC_VECTOR(30 downto 11);
signal V_A_RFE2_shadow : STD_ULOGIC;
signal V_E_OP13_shadow : STD_LOGIC;
signal V_A_CWP_shadow : CWPTYPE;
signal ME_SIZE_shadow : OP_TYPE;
signal V_X_MAC_shadow : STD_ULOGIC;
signal V_M_CTRL_INST_shadow : WORD;
signal VIR_ADDR31DOWNTO4_shadow : std_logic_vector(31 downto 4);
signal V_A_CTRL_INST20_shadow : STD_LOGIC;
signal DE_REN2_shadow : STD_ULOGIC;
signal V_E_CTRL_PV_shadow : STD_ULOGIC;
signal V_E_MAC_shadow : STD_ULOGIC;
signal V_X_CTRL_TT3DOWNTO0_shadow : std_logic_vector(3 downto 0);
signal EX_ADD_RES3_shadow : STD_LOGIC;
signal V_X_CTRL_INST_shadow : WORD;
signal V_M_CTRL_PC31DOWNTO2_shadow : std_logic_vector(31 downto 2);
signal V_W_S_ET_shadow : STD_ULOGIC;
signal V_M_CTRL_CNT_shadow : OP_TYPE;
signal V_M_CTRL_ANNUL_shadow : STD_ULOGIC;
signal DE_INST19_shadow : STD_LOGIC;
signal XC_HALT_shadow : STD_ULOGIC;
signal V_E_OP231_shadow : STD_LOGIC;
signal V_A_CTRL_PC3DOWNTO2_shadow : std_logic_vector(3 downto 2);
signal VIR_ADDR31DOWNTO12_shadow : std_logic_vector(31 downto 12);
signal V_M_CTRL_WICC_shadow : STD_ULOGIC;
signal V_M_CTRL_WREG_shadow : STD_ULOGIC;
signal V_W_S_S_shadow : STD_ULOGIC;
signal V_F_PC31DOWNTO2_shadow : std_logic_vector(31 downto 2);
signal V_E_CWP_shadow : CWPTYPE;
signal V_A_STEP_shadow : STD_ULOGIC;
signal V_A_CTRL_TT3DOWNTO0_shadow : std_logic_vector(3 downto 0);
signal V_A_CTRL_TRAP_shadow : STD_ULOGIC;
signal NPC31DOWNTO2_shadow : std_logic_vector(31 downto 2);
signal V_M_CTRL_TRAP_shadow : STD_ULOGIC;
signal V_D_PC31DOWNTO4_shadow : std_logic_vector(31 downto 4);
signal V_X_INTACK_shadow : STD_ULOGIC;
signal SIDLE_shadow : STD_ULOGIC;
signal V_A_CTRL_RETT_shadow : STD_ULOGIC;
signal V_X_DATA03_shadow : STD_LOGIC;
signal V_A_CTRL_INST19_shadow : STD_LOGIC;
signal V_W_S_SVT_shadow : STD_ULOGIC;
signal V_A_CTRL_PC31DOWNTO4_shadow : std_logic_vector(31 downto 4);
signal V_X_LADDR_shadow : OP_TYPE;
signal V_W_S_DWT_shadow : STD_ULOGIC;
signal EX_JUMP_ADDRESS31DOWNTO2_shadow : std_logic_vector(31 downto 2);
signal V_W_S_TBA_shadow : STD_LOGIC_VECTOR(19 downto 0);
signal XC_WADDR6DOWNTO0_shadow : STD_LOGIC_VECTOR(6 downto 0);
signal V_M_MUL_shadow : STD_ULOGIC;
signal V_E_SU_shadow : STD_ULOGIC;
signal V_M_Y31_shadow : STD_LOGIC;
signal V_E_OP23_shadow : STD_LOGIC;
signal V_M_CTRL_PC31DOWNTO4_shadow : std_logic_vector(31 downto 4);
signal DE_RADDR17DOWNTO0_shadow : STD_LOGIC_VECTOR(7 downto 0);
signal V_X_CTRL_PC31DOWNTO2_shadow : std_logic_vector(31 downto 2);
signal V_E_CTRL_TRAP_shadow : STD_ULOGIC;
signal V_X_DEBUG_shadow : STD_ULOGIC;
signal V_M_DCI_LOCK_shadow : STD_ULOGIC;
signal V_X_CTRL_PC3DOWNTO2_shadow : std_logic_vector(3 downto 2);
signal V_X_CTRL_WREG_shadow : STD_ULOGIC;
signal V_E_CTRL_INST24_shadow : STD_LOGIC;
signal V_D_MEXC_shadow : STD_ULOGIC;
signal V_W_RESULT_shadow : WORD;
signal VFPI_DBG_ENABLE_shadow : STD_ULOGIC;
signal EX_OP131_shadow : STD_LOGIC;
signal V_D_INST1_shadow : std_logic_vector(31 downto 0);
signal V_W_EXCEPT_shadow : STD_ULOGIC;
signal V_E_CTRL_TT3DOWNTO0_shadow : std_logic_vector(3 downto 0);
signal ME_LADDR_shadow : OP_TYPE;
signal V_X_CTRL_PC31DOWNTO4_shadow : std_logic_vector(31 downto 4);
signal V_E_CTRL_RETT_shadow : STD_ULOGIC;
signal XC_WADDR7DOWNTO0_shadow : STD_LOGIC_VECTOR(7 downto 0);
signal V_X_CTRL_PV_shadow : STD_ULOGIC;
signal V_E_CTRL_RD6DOWNTO0_shadow : std_logic_vector(6 downto 0);
signal V_M_MAC_shadow : STD_ULOGIC;
signal V_D_SET_shadow : STD_LOGIC_VECTOR(0 downto 0);
signal VIR_ADDR3DOWNTO2_shadow : std_logic_vector(3 downto 2);
signal V_D_CWP_shadow : CWPTYPE;
signal DE_INST20_shadow : STD_LOGIC;
signal V_D_ANNUL_shadow : STD_ULOGIC;
signal EX_OP2_shadow : WORD;
signal EX_SARI_shadow : STD_ULOGIC;
signal V_D_PC31DOWNTO2_shadow : std_logic_vector(31 downto 2);
signal V_X_DCI_SIZE_shadow : OP_TYPE;
signal V_M_Y_shadow : WORD;
signal V_X_CTRL_PC_shadow : PCTYPE;
signal V_X_SET_shadow : STD_LOGIC_VECTOR(0 downto 0);
signal V_A_CTRL_PC_shadow : PCTYPE;
signal V_A_JMPL_shadow : STD_ULOGIC;
signal V_E_CTRL_PC_shadow : PCTYPE;
signal V_E_CTRL_INST20_shadow : STD_LOGIC;
signal V_E_CTRL_WREG_shadow : STD_ULOGIC;
signal V_A_CTRL_WREG_shadow : STD_ULOGIC;
signal V_A_CTRL_shadow : PIPELINE_CTRL_TYPE;
signal V_A_CTRL_RD6DOWNTO0_shadow : std_logic_vector(6 downto 0);
signal V_X_DATA0_shadow : std_logic_vector(31 downto 0);
signal V_E_CTRL_INST19_shadow : STD_LOGIC;
signal ME_SIGNED_shadow : STD_ULOGIC;
signal V_W_WREG_shadow : STD_ULOGIC;
signal V_D_PC_shadow : PCTYPE;
signal VFPI_D_ANNUL_shadow : STD_ULOGIC;
signal DE_RADDR27DOWNTO0_shadow : STD_LOGIC_VECTOR(7 downto 0);
signal V_E_CTRL_CNT_shadow : OP_TYPE;
signal V_F_PC_shadow : PCTYPE;
signal V_X_DATA031_shadow : STD_LOGIC;
signal V_M_CTRL_PC31DOWNTO12_shadow : std_logic_vector(31 downto 12);
signal V_X_CTRL_RD7DOWNTO0_shadow : std_logic_vector(7 downto 0);
signal V_M_CTRL_TT_shadow : OP3_TYPE;
signal V_X_CTRL_shadow : PIPELINE_CTRL_TYPE;
signal V_A_CTRL_INST24_shadow : STD_LOGIC;
signal XC_TRAP_ADDRESS3DOWNTO2_shadow : std_logic_vector(3 downto 2);
signal V_X_NERROR_shadow : STD_ULOGIC;
signal V_F_PC31DOWNTO4_shadow : std_logic_vector(31 downto 4);
signal V_W_S_TT3DOWNTO0_shadow : STD_LOGIC_VECTOR(3 downto 0);
signal EX_JUMP_ADDRESS31DOWNTO4_shadow : std_logic_vector(31 downto 4);
signal EX_ADD_RES32DOWNTO332DOWNTO3_shadow : STD_LOGIC_VECTOR(32 downto 3);
signal V_F_BRANCH_shadow : STD_ULOGIC;
signal V_A_CTRL_WICC_shadow : STD_ULOGIC;
signal V_A_CTRL_LD_shadow : STD_ULOGIC;
signal V_A_CTRL_TT_shadow : OP3_TYPE;
signal V_M_CTRL_LD_shadow : STD_ULOGIC;
signal V_E_SHCNT_shadow : ASI_TYPE;
signal XC_TRAP_ADDRESS31DOWNTO12_shadow : std_logic_vector(31 downto 12);
signal V_A_CTRL_INST_shadow : WORD;
signal V_A_CTRL_RD7DOWNTO0_shadow : std_logic_vector(7 downto 0);
signal VIR_PWD_shadow : STD_ULOGIC;
signal XC_RESULT_shadow : WORD;
signal V_A_RFA1_shadow : RFATYPE;
signal V_E_JMPL_shadow : STD_ULOGIC;
signal V_E_CTRL_RD7DOWNTO0_shadow : std_logic_vector(7 downto 0);
signal ME_ICC_shadow : STD_LOGIC_VECTOR(3 downto 0);
signal DE_INST24_shadow : STD_LOGIC;
signal XC_TRAP_shadow : STD_ULOGIC;
signal VDSU_TBUFCNT_shadow : STD_LOGIC_VECTOR(6 downto 0);
signal XC_TRAP_ADDRESS_shadow : PCTYPE;
-- Intermediate value holding signal declarations
signal V_E_CTRL_WREG_shadow_intermed_2 : STD_ULOGIC;
signal V_M_CTRL_PC_shadow_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_E_CTRL_TT3DOWNTO0_intermed_1 : std_logic_vector(3 downto 0);
signal V_D_PC3DOWNTO2_shadow_intermed_6 : std_logic_vector(3 downto 2);
signal RIN_M_CTRL_PC31DOWNTO12_intermed_5 : std_logic_vector(31 downto 12);
signal RIN_A_RFA1_intermed_1 : std_logic_vector(7 downto 0);
signal RIN_A_CTRL_PC31DOWNTO2_intermed_4 : std_logic_vector(31 downto 2);
signal R_E_CTRL_TT_intermed_1 : std_logic_vector(5 downto 0);
signal V_D_PC3DOWNTO2_shadow_intermed_2 : std_logic_vector(3 downto 2);
signal ICO_MEXC_intermed_4 : STD_ULOGIC;
signal V_F_PC31DOWNTO2_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_X_DATA00_intermed_2 : STD_LOGIC;
signal R_A_CTRL_RD6DOWNTO0_intermed_1 : std_logic_vector(6 downto 0);
signal R_A_CTRL_INST24_intermed_1 : STD_LOGIC;
signal RIN_E_CTRL_INST19_intermed_1 : STD_LOGIC;
signal V_X_DATA00_shadow_intermed_3 : STD_LOGIC;
signal RIN_A_CTRL_INST19_intermed_2 : STD_LOGIC;
signal IRIN_ADDR31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2);
signal V_E_CTRL_WREG_shadow_intermed_1 : STD_ULOGIC;
signal V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 : std_logic_vector(31 downto 2);
signal V_M_CTRL_PC_shadow_intermed_3 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_WICC_intermed_3 : STD_ULOGIC;
signal V_A_CTRL_RETT_shadow_intermed_3 : STD_ULOGIC;
signal RPIN_PWD_intermed_1 : STD_ULOGIC;
signal RIN_A_CTRL_PC31DOWNTO12_intermed_7 : std_logic_vector(31 downto 12);
signal V_E_CTRL_TT_shadow_intermed_3 : std_logic_vector(5 downto 0);
signal DE_INST_shadow_intermed_2 : std_logic_vector(31 downto 0);
signal R_M_CTRL_PC31DOWNTO2_intermed_3 : std_logic_vector(31 downto 2);
signal DBGI_DADDR9DOWNTO2_intermed_1 : STD_LOGIC_VECTOR(9 downto 2);
signal R_D_PC31DOWNTO2_intermed_6 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_TT3DOWNTO0_intermed_5 : std_logic_vector(3 downto 0);
signal RIN_A_CTRL_TRAP_intermed_3 : STD_ULOGIC;
signal V_E_CTRL_CNT_shadow_intermed_2 : std_logic_vector(1 downto 0);
signal V_E_CTRL_PC31DOWNTO4_shadow_intermed_4 : std_logic_vector(31 downto 4);
signal RIN_D_STEP_intermed_1 : STD_ULOGIC;
signal V_M_CTRL_TT3DOWNTO0_shadow_intermed_4 : std_logic_vector(3 downto 0);
signal V_A_CTRL_PC_shadow_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_D_PC31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2);
signal V_E_CTRL_PC31DOWNTO4_shadow_intermed_5 : std_logic_vector(31 downto 4);
signal RIN_E_CTRL_INST20_intermed_1 : STD_LOGIC;
signal V_D_PC3DOWNTO2_shadow_intermed_7 : std_logic_vector(3 downto 2);
signal V_M_CTRL_PC31DOWNTO4_shadow_intermed_4 : std_logic_vector(31 downto 4);
signal V_M_CTRL_RD6DOWNTO0_shadow_intermed_2 : std_logic_vector(6 downto 0);
signal RIN_E_CTRL_PC3DOWNTO2_intermed_3 : std_logic_vector(3 downto 2);
signal RIN_M_Y31_intermed_1 : STD_LOGIC;
signal V_D_INST0_shadow_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_E_YMSB_intermed_1 : STD_ULOGIC;
signal R_X_DATA031_intermed_2 : STD_LOGIC;
signal RIN_M_CTRL_WREG_intermed_2 : STD_ULOGIC;
signal V_X_CTRL_TT_shadow_intermed_1 : std_logic_vector(5 downto 0);
signal RIN_E_CTRL_PC_intermed_4 : std_logic_vector(31 downto 2);
signal V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 : std_logic_vector(3 downto 0);
signal RIN_E_CTRL_PC31DOWNTO12_intermed_4 : std_logic_vector(31 downto 12);
signal V_A_CTRL_PC3DOWNTO2_shadow_intermed_3 : std_logic_vector(3 downto 2);
signal RIN_E_CTRL_PC31DOWNTO2_intermed_4 : std_logic_vector(31 downto 2);
signal R_A_CTRL_TT_intermed_1 : std_logic_vector(5 downto 0);
signal RIN_A_CTRL_WICC_intermed_2 : STD_ULOGIC;
signal V_E_CTRL_PC31DOWNTO2_shadow_intermed_6 : std_logic_vector(31 downto 2);
signal RIN_F_PC3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2);
signal V_A_CTRL_PC31DOWNTO12_shadow_intermed_4 : std_logic_vector(31 downto 12);
signal EX_ADD_RES32DOWNTO332DOWNTO5_shadow_intermed_1 : STD_LOGIC_VECTOR(32 downto 5);
signal V_X_DATA04DOWNTO0_shadow_intermed_1 : std_logic_vector(4 downto 0);
signal R_A_CTRL_INST20_intermed_2 : STD_LOGIC;
signal V_A_CTRL_PC31DOWNTO12_shadow_intermed_6 : std_logic_vector(31 downto 12);
signal R_A_CTRL_RETT_intermed_2 : STD_ULOGIC;
signal RIN_M_DCI_LOCK_intermed_1 : STD_ULOGIC;
signal RIN_D_PC31DOWNTO12_intermed_6 : std_logic_vector(31 downto 12);
signal RIN_E_CTRL_TT_intermed_3 : std_logic_vector(5 downto 0);
signal R_E_CTRL_RD7DOWNTO0_intermed_2 : std_logic_vector(7 downto 0);
signal RIN_A_ET_intermed_1 : STD_ULOGIC;
signal RIN_X_CTRL_RD6DOWNTO0_intermed_1 : std_logic_vector(6 downto 0);
signal RIN_M_CTRL_PC31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12);
signal DBGI_STEP_intermed_1 : STD_ULOGIC;
signal V_A_CTRL_RETT_shadow_intermed_2 : STD_ULOGIC;
signal R_X_CTRL_PC3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2);
signal R_A_CTRL_PC31DOWNTO4_intermed_4 : std_logic_vector(31 downto 4);
signal V_M_CTRL_PV_shadow_intermed_1 : STD_ULOGIC;
signal RIN_M_CTRL_PC31DOWNTO2_intermed_5 : std_logic_vector(31 downto 2);
signal V_M_CTRL_PC31DOWNTO12_shadow_intermed_5 : std_logic_vector(31 downto 12);
signal V_X_LADDR_shadow_intermed_1 : std_logic_vector(1 downto 0);
signal V_D_ANNUL_shadow_intermed_2 : STD_ULOGIC;
signal V_A_CTRL_RD6DOWNTO0_shadow_intermed_1 : std_logic_vector(6 downto 0);
signal RIN_W_WA_intermed_1 : std_logic_vector(7 downto 0);
signal V_D_PC_shadow_intermed_4 : std_logic_vector(31 downto 2);
signal V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_X_CTRL_PC31DOWNTO4_intermed_2 : std_logic_vector(31 downto 4);
signal V_E_CTRL_WICC_shadow_intermed_1 : STD_ULOGIC;
signal VDSU_CRDY2_shadow_intermed_2 : STD_LOGIC;
signal V_M_RESULT1DOWNTO0_shadow_intermed_3 : std_logic_vector(1 downto 0);
signal RIN_D_INST0_intermed_1 : std_logic_vector(31 downto 0);
signal V_X_DATA03_shadow_intermed_2 : STD_LOGIC;
signal RIN_X_DCI_intermed_1 : DC_IN_TYPE;
signal DSUIN_TT_intermed_1 : STD_LOGIC_VECTOR(7 downto 0);
signal V_D_CNT_shadow_intermed_4 : std_logic_vector(1 downto 0);
signal RIN_D_CNT_intermed_4 : std_logic_vector(1 downto 0);
signal ICO_MEXC_intermed_1 : STD_ULOGIC;
signal R_X_ANNUL_ALL_intermed_2 : STD_ULOGIC;
signal R_X_CTRL_TT3DOWNTO0_intermed_2 : std_logic_vector(3 downto 0);
signal R_D_PC3DOWNTO2_intermed_3 : std_logic_vector(3 downto 2);
signal RIN_D_CNT_intermed_2 : std_logic_vector(1 downto 0);
signal V_M_DCI_SIZE_shadow_intermed_2 : std_logic_vector(1 downto 0);
signal R_A_CTRL_ANNUL_intermed_2 : STD_ULOGIC;
signal V_W_S_S_shadow_intermed_1 : STD_ULOGIC;
signal RIN_M_CTRL_TT_intermed_2 : std_logic_vector(5 downto 0);
signal EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_1 : STD_LOGIC_VECTOR(30 downto 11);
signal V_A_CTRL_RETT_shadow_intermed_1 : STD_ULOGIC;
signal R_X_DATA04DOWNTO0_intermed_1 : std_logic_vector(4 downto 0);
signal V_E_CTRL_TT3DOWNTO0_shadow_intermed_1 : std_logic_vector(3 downto 0);
signal V_D_PC31DOWNTO4_shadow_intermed_6 : std_logic_vector(31 downto 4);
signal V_X_CTRL_RD6DOWNTO0_shadow_intermed_1 : std_logic_vector(6 downto 0);
signal RIN_W_S_ET_intermed_1 : STD_ULOGIC;
signal R_E_CTRL_TRAP_intermed_1 : STD_ULOGIC;
signal V_A_CTRL_PC_shadow_intermed_3 : std_logic_vector(31 downto 2);
signal R_M_CTRL_PC31DOWNTO4_intermed_2 : std_logic_vector(31 downto 4);
signal VIR_ADDR31DOWNTO4_shadow_intermed_2 : std_logic_vector(31 downto 4);
signal V_E_CTRL_RD6DOWNTO0_shadow_intermed_3 : std_logic_vector(6 downto 0);
signal R_D_CWP_intermed_1 : std_logic_vector(2 downto 0);
signal RIN_A_CTRL_TT3DOWNTO0_intermed_2 : std_logic_vector(3 downto 0);
signal RIN_X_CTRL_PC3DOWNTO2_intermed_3 : std_logic_vector(3 downto 2);
signal RIN_D_PC31DOWNTO2_intermed_8 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_ANNUL_intermed_1 : STD_ULOGIC;
signal V_X_CTRL_PC3DOWNTO2_shadow_intermed_1 : std_logic_vector(3 downto 2);
signal RIN_M_CTRL_PC31DOWNTO12_intermed_3 : std_logic_vector(31 downto 12);
signal R_M_DCI_SIGNED_intermed_1 : STD_ULOGIC;
signal RIN_X_DCI_SIGNED_intermed_1 : STD_ULOGIC;
signal V_D_PC31DOWNTO2_shadow_intermed_4 : std_logic_vector(31 downto 2);
signal DCO_DATA00_intermed_2 : STD_LOGIC;
signal V_M_CTRL_RD7DOWNTO0_shadow_intermed_2 : std_logic_vector(7 downto 0);
signal V_E_SU_shadow_intermed_1 : STD_ULOGIC;
signal R_A_CTRL_INST20_intermed_1 : STD_LOGIC;
signal R_D_PC31DOWNTO12_intermed_7 : std_logic_vector(31 downto 12);
signal XC_TRAP_ADDRESS_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_X_CTRL_PC31DOWNTO2_intermed_3 : std_logic_vector(31 downto 2);
signal R_E_CTRL_RETT_intermed_1 : STD_ULOGIC;
signal V_X_DCI_SIZE_shadow_intermed_1 : std_logic_vector(1 downto 0);
signal RIN_D_CNT_intermed_3 : std_logic_vector(1 downto 0);
signal RIN_A_CTRL_ANNUL_intermed_4 : STD_ULOGIC;
signal R_E_CTRL_TT3DOWNTO0_intermed_1 : std_logic_vector(3 downto 0);
signal R_D_PC3DOWNTO2_intermed_2 : std_logic_vector(3 downto 2);
signal V_X_CTRL_TT3DOWNTO0_shadow_intermed_3 : std_logic_vector(3 downto 0);
signal V_A_CTRL_RD6DOWNTO0_shadow_intermed_3 : std_logic_vector(6 downto 0);
signal R_M_CTRL_PC31DOWNTO2_intermed_4 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_PC31DOWNTO12_intermed_3 : std_logic_vector(31 downto 12);
signal R_A_CTRL_PC31DOWNTO12_intermed_5 : std_logic_vector(31 downto 12);
signal R_A_CTRL_PC_intermed_2 : std_logic_vector(31 downto 2);
signal V_X_MEXC_shadow_intermed_1 : STD_ULOGIC;
signal V_M_CTRL_RD7DOWNTO0_shadow_intermed_1 : std_logic_vector(7 downto 0);
signal IR_ADDR31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4);
signal V_A_CTRL_PC_shadow_intermed_4 : std_logic_vector(31 downto 2);
signal VIR_ADDR31DOWNTO4_shadow_intermed_1 : std_logic_vector(31 downto 4);
signal RIN_M_CTRL_PC3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2);
signal RIN_E_CTRL_WREG_intermed_1 : STD_ULOGIC;
signal RIN_D_PC31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12);
signal V_E_CTRL_TT3DOWNTO0_shadow_intermed_2 : std_logic_vector(3 downto 0);
signal RIN_D_INST1_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_D_PC31DOWNTO12_intermed_3 : std_logic_vector(31 downto 12);
signal V_A_CTRL_TT_shadow_intermed_3 : std_logic_vector(5 downto 0);
signal RIN_A_CTRL_INST24_intermed_2 : STD_LOGIC;
signal V_X_DATA1_shadow_intermed_2 : std_logic_vector(31 downto 0);
signal ICO_MEXC_intermed_3 : STD_ULOGIC;
signal R_D_PC3DOWNTO2_intermed_4 : std_logic_vector(3 downto 2);
signal R_M_CTRL_INST_intermed_1 : std_logic_vector(31 downto 0);
signal V_A_CWP_shadow_intermed_1 : std_logic_vector(2 downto 0);
signal V_A_CTRL_WICC_shadow_intermed_3 : STD_ULOGIC;
signal V_D_PC_shadow_intermed_6 : std_logic_vector(31 downto 2);
signal RIN_X_ANNUL_ALL_intermed_5 : STD_ULOGIC;
signal RIN_E_CTRL_INST20_intermed_2 : STD_LOGIC;
signal R_X_DATA0_intermed_2 : std_logic_vector(31 downto 0);
signal RIN_D_PC_intermed_4 : std_logic_vector(31 downto 2);
signal R_E_CTRL_PV_intermed_1 : STD_ULOGIC;
signal R_E_CTRL_TT3DOWNTO0_intermed_2 : std_logic_vector(3 downto 0);
signal R_D_PC_intermed_1 : std_logic_vector(31 downto 2);
signal R_A_CTRL_PC_intermed_3 : std_logic_vector(31 downto 2);
signal EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_1 : std_logic_vector(31 downto 12);
signal R_X_CTRL_TT3DOWNTO0_intermed_1 : std_logic_vector(3 downto 0);
signal V_M_DCI_SIGNED_shadow_intermed_1 : STD_ULOGIC;
signal RIN_X_CTRL_TT3DOWNTO0_intermed_1 : std_logic_vector(3 downto 0);
signal V_X_ANNUL_ALL_shadow_intermed_2 : STD_ULOGIC;
signal V_D_PC31DOWNTO4_shadow_intermed_7 : std_logic_vector(31 downto 4);
signal RIN_E_OP13_intermed_1 : STD_LOGIC;
signal RIN_A_CWP_intermed_1 : std_logic_vector(2 downto 0);
signal RIN_E_CTRL_WICC_intermed_1 : STD_ULOGIC;
signal VP_ERROR_shadow_intermed_2 : STD_ULOGIC;
signal RIN_E_OP2_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_A_CTRL_TT3DOWNTO0_intermed_4 : std_logic_vector(3 downto 0);
signal RIN_A_CTRL_RD7DOWNTO0_intermed_2 : std_logic_vector(7 downto 0);
signal RIN_E_CTRL_intermed_2 : PIPELINE_CTRL_TYPE;
signal R_M_CTRL_PC_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_E_CTRL_PC31DOWNTO2_intermed_5 : std_logic_vector(31 downto 2);
signal R_M_Y31_intermed_2 : STD_LOGIC;
signal V_M_CTRL_PC3DOWNTO2_shadow_intermed_4 : std_logic_vector(3 downto 2);
signal V_M_CTRL_RETT_shadow_intermed_1 : STD_ULOGIC;
signal V_X_CTRL_PC31DOWNTO4_shadow_intermed_3 : std_logic_vector(31 downto 4);
signal XC_VECTT3DOWNTO0_shadow_intermed_2 : STD_LOGIC_VECTOR(3 downto 0);
signal RIN_M_CTRL_PC31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12);
signal RIN_M_RESULT1DOWNTO0_intermed_2 : std_logic_vector(1 downto 0);
signal V_X_ANNUL_ALL_shadow_intermed_4 : STD_ULOGIC;
signal RIN_W_S_TBA_intermed_1 : STD_LOGIC_VECTOR(19 downto 0);
signal V_D_INST1_shadow_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_X_DATA031_intermed_1 : STD_LOGIC;
signal XC_TRAP_ADDRESS31DOWNTO12_shadow_intermed_1 : std_logic_vector(31 downto 12);
signal RIN_D_PC3DOWNTO2_intermed_4 : std_logic_vector(3 downto 2);
signal RIN_X_CTRL_PC31DOWNTO4_intermed_3 : std_logic_vector(31 downto 4);
signal V_E_CTRL_PC31DOWNTO4_shadow_intermed_2 : std_logic_vector(31 downto 4);
signal V_M_CTRL_PC3DOWNTO2_shadow_intermed_3 : std_logic_vector(3 downto 2);
signal V_M_CTRL_PC31DOWNTO12_shadow_intermed_2 : std_logic_vector(31 downto 12);
signal RIN_E_CTRL_PV_intermed_1 : STD_ULOGIC;
signal EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_1 : STD_LOGIC_VECTOR(32 downto 13);
signal R_E_CTRL_WREG_intermed_2 : STD_ULOGIC;
signal R_X_DATA031_intermed_1 : STD_LOGIC;
signal R_D_INST0_intermed_2 : std_logic_vector(31 downto 0);
signal RIN_E_SARI_intermed_1 : STD_ULOGIC;
signal R_M_Y31_intermed_1 : STD_LOGIC;
signal IR_ADDR3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2);
signal DE_INST24_shadow_intermed_2 : STD_LOGIC;
signal V_W_S_S_shadow_intermed_2 : STD_ULOGIC;
signal DE_INST20_shadow_intermed_3 : STD_LOGIC;
signal R_E_CTRL_TT3DOWNTO0_intermed_4 : std_logic_vector(3 downto 0);
signal RIN_A_CTRL_TT_intermed_2 : std_logic_vector(5 downto 0);
signal V_A_CTRL_PV_shadow_intermed_2 : STD_ULOGIC;
signal V_E_CTRL_TT_shadow_intermed_1 : std_logic_vector(5 downto 0);
signal V_D_PC31DOWNTO2_shadow_intermed_5 : std_logic_vector(31 downto 2);
signal V_X_DATA04DOWNTO0_shadow_intermed_2 : std_logic_vector(4 downto 0);
signal R_X_CTRL_PC31DOWNTO4_intermed_2 : std_logic_vector(31 downto 4);
signal RIN_M_CTRL_INST_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_A_CTRL_RD6DOWNTO0_intermed_2 : std_logic_vector(6 downto 0);
signal DCO_DATA04DOWNTO0_intermed_2 : std_logic_vector(4 downto 0);
signal EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_2 : std_logic_vector(31 downto 12);
signal V_X_DATA0_shadow_intermed_2 : std_logic_vector(31 downto 0);
signal R_A_CTRL_WREG_intermed_3 : STD_ULOGIC;
signal RIN_X_CTRL_PC31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12);
signal R_D_CNT_intermed_3 : std_logic_vector(1 downto 0);
signal V_E_OP131_shadow_intermed_1 : STD_LOGIC;
signal R_D_PC31DOWNTO12_intermed_6 : std_logic_vector(31 downto 12);
signal RIN_X_CTRL_WICC_intermed_1 : STD_ULOGIC;
signal V_D_PC31DOWNTO12_shadow_intermed_1 : std_logic_vector(31 downto 12);
signal RIN_E_CTRL_TRAP_intermed_3 : STD_ULOGIC;
signal R_X_RESULT6DOWNTO0_intermed_1 : std_logic_vector(6 downto 0);
signal R_E_CTRL_INST19_intermed_2 : STD_LOGIC;
signal RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 : std_logic_vector(3 downto 0);
signal R_M_CTRL_RD7DOWNTO0_intermed_1 : std_logic_vector(7 downto 0);
signal RIN_E_CTRL_PC31DOWNTO12_intermed_6 : std_logic_vector(31 downto 12);
signal RIN_A_CTRL_PC31DOWNTO4_intermed_3 : std_logic_vector(31 downto 4);
signal V_A_CTRL_INST19_shadow_intermed_3 : STD_LOGIC;
signal V_D_PC31DOWNTO12_shadow_intermed_5 : std_logic_vector(31 downto 12);
signal V_A_CTRL_INST19_shadow_intermed_2 : STD_LOGIC;
signal V_X_CTRL_WREG_shadow_intermed_1 : STD_ULOGIC;
signal V_A_CTRL_TRAP_shadow_intermed_2 : STD_ULOGIC;
signal RIN_E_CTRL_PC3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2);
signal RIN_M_CTRL_PC3DOWNTO2_intermed_3 : std_logic_vector(3 downto 2);
signal V_A_RFE2_shadow_intermed_1 : STD_ULOGIC;
signal V_M_Y_shadow_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_A_CTRL_LD_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_PC_shadow_intermed_3 : std_logic_vector(31 downto 2);
signal RIN_D_INST1_intermed_2 : std_logic_vector(31 downto 0);
signal R_E_CTRL_PC31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12);
signal RIN_X_CTRL_PC31DOWNTO12_intermed_3 : std_logic_vector(31 downto 12);
signal R_E_CTRL_TRAP_intermed_2 : STD_ULOGIC;
signal DE_INST24_shadow_intermed_1 : STD_LOGIC;
signal V_E_CTRL_PC_shadow_intermed_2 : std_logic_vector(31 downto 2);
signal V_A_CTRL_TT_shadow_intermed_1 : std_logic_vector(5 downto 0);
signal V_D_MEXC_shadow_intermed_4 : STD_ULOGIC;
signal V_D_PC31DOWNTO12_shadow_intermed_6 : std_logic_vector(31 downto 12);
signal V_A_CTRL_PC31DOWNTO12_shadow_intermed_3 : std_logic_vector(31 downto 12);
signal R_X_CTRL_PC31DOWNTO12_intermed_3 : std_logic_vector(31 downto 12);
signal V_M_CTRL_PV_shadow_intermed_2 : STD_ULOGIC;
signal RIN_A_CTRL_PC31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2);
signal EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_E_CTRL_PC31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4);
signal RIN_E_CTRL_PC31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12);
signal RIN_M_CTRL_TRAP_intermed_1 : STD_ULOGIC;
signal R_E_CTRL_PC31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2);
signal R_E_CTRL_LD_intermed_1 : STD_ULOGIC;
signal R_M_CTRL_PC31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_PC31DOWNTO2_intermed_5 : std_logic_vector(31 downto 2);
signal V_W_S_CWP_shadow_intermed_1 : std_logic_vector(2 downto 0);
signal R_M_CTRL_PC3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2);
signal V_E_CTRL_PC31DOWNTO12_shadow_intermed_4 : std_logic_vector(31 downto 12);
signal R_X_CTRL_PC31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4);
signal V_M_CTRL_PC_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal IR_ADDR31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2);
signal V_E_CTRL_TT3DOWNTO0_shadow_intermed_4 : std_logic_vector(3 downto 0);
signal V_E_CTRL_PC3DOWNTO2_shadow_intermed_3 : std_logic_vector(3 downto 2);
signal RIN_X_CTRL_PC31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4);
signal R_E_CTRL_PC31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12);
signal RIN_M_CTRL_RETT_intermed_1 : STD_ULOGIC;
signal V_M_DCI_LOCK_shadow_intermed_1 : STD_ULOGIC;
signal V_X_RESULT6DOWNTO0_shadow_intermed_1 : std_logic_vector(6 downto 0);
signal RIN_X_DATA04DOWNTO0_intermed_3 : std_logic_vector(4 downto 0);
signal V_X_NERROR_shadow_intermed_1 : STD_ULOGIC;
signal V_A_RFE1_shadow_intermed_1 : STD_ULOGIC;
signal V_D_PC3DOWNTO2_shadow_intermed_1 : std_logic_vector(3 downto 2);
signal V_E_CTRL_LD_shadow_intermed_1 : STD_ULOGIC;
signal ICO_DATA0_intermed_1 : std_logic_vector(31 downto 0);
signal VIR_ADDR_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal R_M_CTRL_PC31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12);
signal V_E_CTRL_PV_shadow_intermed_2 : STD_ULOGIC;
signal RIN_E_CTRL_PC31DOWNTO4_intermed_4 : std_logic_vector(31 downto 4);
signal R_A_CTRL_PC3DOWNTO2_intermed_3 : std_logic_vector(3 downto 2);
signal R_E_CTRL_INST19_intermed_1 : STD_LOGIC;
signal RIN_E_CTRL_TT3DOWNTO0_intermed_4 : std_logic_vector(3 downto 0);
signal R_M_CTRL_PC31DOWNTO4_intermed_3 : std_logic_vector(31 downto 4);
signal V_A_CTRL_PC31DOWNTO4_shadow_intermed_4 : std_logic_vector(31 downto 4);
signal RIN_W_S_DWT_intermed_1 : STD_ULOGIC;
signal V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 : std_logic_vector(31 downto 2);
signal R_D_PC31DOWNTO12_intermed_4 : std_logic_vector(31 downto 12);
signal RIN_X_NERROR_intermed_1 : STD_ULOGIC;
signal R_M_CTRL_PC3DOWNTO2_intermed_2 : std_logic_vector(3 downto 2);
signal ICO_MEXC_intermed_5 : STD_ULOGIC;
signal R_A_CTRL_RD7DOWNTO0_intermed_2 : std_logic_vector(7 downto 0);
signal V_A_CTRL_PC31DOWNTO4_shadow_intermed_1 : std_logic_vector(31 downto 4);
signal IRIN_ADDR31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2);
signal VIR_ADDR31DOWNTO12_shadow_intermed_3 : std_logic_vector(31 downto 12);
signal XC_TRAP_ADDRESS3DOWNTO2_shadow_intermed_1 : std_logic_vector(3 downto 2);
signal R_A_CTRL_INST_intermed_1 : std_logic_vector(31 downto 0);
signal R_E_CTRL_PC31DOWNTO2_intermed_3 : std_logic_vector(31 downto 2);
signal RIN_X_CTRL_TT3DOWNTO0_intermed_3 : std_logic_vector(3 downto 0);
signal RIN_M_CTRL_PC3DOWNTO2_intermed_2 : std_logic_vector(3 downto 2);
signal V_M_CTRL_PC31DOWNTO2_shadow_intermed_4 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_RETT_intermed_2 : STD_ULOGIC;
signal V_X_DATA00_shadow_intermed_1 : STD_LOGIC;
signal RIN_M_CTRL_RD6DOWNTO0_intermed_2 : std_logic_vector(6 downto 0);
signal RIN_E_CTRL_TT3DOWNTO0_intermed_2 : std_logic_vector(3 downto 0);
signal V_M_CTRL_INST_shadow_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_A_CTRL_TT3DOWNTO0_intermed_3 : std_logic_vector(3 downto 0);
signal EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1 : STD_LOGIC_VECTOR(32 downto 3);
signal R_A_CTRL_TT3DOWNTO0_intermed_1 : std_logic_vector(3 downto 0);
signal V_X_DEBUG_shadow_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_PC_shadow_intermed_4 : std_logic_vector(31 downto 2);
signal V_M_CTRL_TT_shadow_intermed_1 : std_logic_vector(5 downto 0);
signal RIN_A_CTRL_PV_intermed_4 : STD_ULOGIC;
signal R_E_MAC_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_PC3DOWNTO2_shadow_intermed_1 : std_logic_vector(3 downto 2);
signal R_M_RESULT1DOWNTO0_intermed_1 : std_logic_vector(1 downto 0);
signal IR_ADDR31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_WREG_intermed_2 : STD_ULOGIC;
signal V_D_MEXC_shadow_intermed_1 : STD_ULOGIC;
signal XC_TRAP_ADDRESS31DOWNTO12_shadow_intermed_2 : std_logic_vector(31 downto 12);
signal R_A_CTRL_LD_intermed_2 : STD_ULOGIC;
signal R_A_CTRL_intermed_2 : PIPELINE_CTRL_TYPE;
signal V_M_CTRL_TRAP_shadow_intermed_2 : STD_ULOGIC;
signal V_A_JMPL_shadow_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_RETT_shadow_intermed_2 : STD_ULOGIC;
signal RIN_M_CTRL_LD_intermed_1 : STD_ULOGIC;
signal V_X_DATA04DOWNTO0_shadow_intermed_3 : std_logic_vector(4 downto 0);
signal RIN_W_S_TT_intermed_1 : STD_LOGIC_VECTOR(7 downto 0);
signal V_A_CTRL_PC_shadow_intermed_5 : std_logic_vector(31 downto 2);
signal V_X_CTRL_PC31DOWNTO12_shadow_intermed_1 : std_logic_vector(31 downto 12);
signal DCO_DATA031_intermed_1 : STD_LOGIC;
signal RIN_A_CTRL_CNT_intermed_1 : std_logic_vector(1 downto 0);
signal R_X_ANNUL_ALL_intermed_3 : STD_ULOGIC;
signal V_X_DATA031_shadow_intermed_3 : STD_LOGIC;
signal DCO_DATA1_intermed_1 : std_logic_vector(31 downto 0);
signal V_E_CTRL_RETT_shadow_intermed_1 : STD_ULOGIC;
signal RIN_E_CTRL_CNT_intermed_1 : std_logic_vector(1 downto 0);
signal V_X_DATA0_shadow_intermed_1 : std_logic_vector(31 downto 0);
signal V_A_CTRL_LD_shadow_intermed_2 : STD_ULOGIC;
signal V_A_CTRL_TT3DOWNTO0_shadow_intermed_6 : std_logic_vector(3 downto 0);
signal R_E_CTRL_PC31DOWNTO4_intermed_3 : std_logic_vector(31 downto 4);
signal RPIN_ERROR_intermed_1 : STD_ULOGIC;
signal V_X_CTRL_PC31DOWNTO2_shadow_intermed_3 : std_logic_vector(31 downto 2);
signal R_W_S_S_intermed_1 : STD_ULOGIC;
signal R_A_CTRL_WICC_intermed_1 : STD_ULOGIC;
signal RIN_A_CTRL_PC31DOWNTO4_intermed_5 : std_logic_vector(31 downto 4);
signal RIN_D_PC31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4);
signal EX_JUMP_ADDRESS31DOWNTO4_shadow_intermed_1 : std_logic_vector(31 downto 4);
signal RIN_D_PC_intermed_5 : std_logic_vector(31 downto 2);
signal V_A_RFA1_shadow_intermed_1 : std_logic_vector(7 downto 0);
signal R_X_CTRL_PC31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2);
signal R_D_PC_intermed_2 : std_logic_vector(31 downto 2);
signal V_A_CTRL_PC3DOWNTO2_shadow_intermed_5 : std_logic_vector(3 downto 2);
signal RIN_E_SU_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_INST_shadow_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_M_CTRL_PC_intermed_1 : std_logic_vector(31 downto 2);
signal R_X_ANNUL_ALL_intermed_4 : STD_ULOGIC;
signal RIN_A_CTRL_INST_intermed_3 : std_logic_vector(31 downto 0);
signal V_A_CTRL_shadow_intermed_3 : PIPELINE_CTRL_TYPE;
signal R_D_MEXC_intermed_1 : STD_ULOGIC;
signal RIN_X_CTRL_RETT_intermed_1 : STD_ULOGIC;
signal R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 : std_logic_vector(3 downto 0);
signal R_A_CTRL_WICC_intermed_2 : STD_ULOGIC;
signal VDSU_CRDY2_shadow_intermed_1 : STD_LOGIC;
signal V_A_DIVSTART_shadow_intermed_1 : STD_ULOGIC;
signal R_A_CTRL_PC31DOWNTO2_intermed_6 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_TRAP_intermed_4 : STD_ULOGIC;
signal RIN_W_S_PS_intermed_1 : STD_ULOGIC;
signal R_D_MEXC_intermed_3 : STD_ULOGIC;
signal RIN_A_RFA2_intermed_1 : std_logic_vector(7 downto 0);
signal R_X_DATA1_intermed_1 : std_logic_vector(31 downto 0);
signal V_A_CTRL_PV_shadow_intermed_1 : STD_ULOGIC;
signal R_A_CTRL_PC31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4);
signal V_X_CTRL_PC31DOWNTO4_shadow_intermed_2 : std_logic_vector(31 downto 4);
signal RIN_W_S_SVT_intermed_1 : STD_ULOGIC;
signal RIN_E_CTRL_RD6DOWNTO0_intermed_1 : std_logic_vector(6 downto 0);
signal R_D_PC31DOWNTO12_intermed_5 : std_logic_vector(31 downto 12);
signal RIN_A_CTRL_INST19_intermed_1 : STD_LOGIC;
signal RIN_M_CTRL_PV_intermed_1 : STD_ULOGIC;
signal RIN_A_CTRL_RD6DOWNTO0_intermed_4 : std_logic_vector(6 downto 0);
signal RIN_E_OP23_intermed_1 : STD_LOGIC;
signal RIN_E_CTRL_WICC_intermed_2 : STD_ULOGIC;
signal R_D_PC31DOWNTO4_intermed_5 : std_logic_vector(31 downto 4);
signal V_D_MEXC_shadow_intermed_2 : STD_ULOGIC;
signal RIN_D_PC31DOWNTO4_intermed_7 : std_logic_vector(31 downto 4);
signal R_A_CTRL_TRAP_intermed_3 : STD_ULOGIC;
signal V_E_CTRL_INST19_shadow_intermed_2 : STD_LOGIC;
signal RIN_E_CTRL_PC31DOWNTO12_intermed_5 : std_logic_vector(31 downto 12);
signal RIN_D_PC31DOWNTO12_intermed_8 : std_logic_vector(31 downto 12);
signal VP_PWD_shadow_intermed_1 : STD_ULOGIC;
signal RIN_M_CTRL_RD7DOWNTO0_intermed_1 : std_logic_vector(7 downto 0);
signal V_A_CTRL_PC31DOWNTO4_shadow_intermed_2 : std_logic_vector(31 downto 4);
signal RIN_F_PC31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_M_NALIGN_intermed_1 : STD_ULOGIC;
signal RP_ERROR_intermed_1 : STD_ULOGIC;
signal RIN_X_CTRL_PC3DOWNTO2_intermed_2 : std_logic_vector(3 downto 2);
signal V_W_S_TBA_shadow_intermed_1 : STD_LOGIC_VECTOR(19 downto 0);
signal R_F_PC31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12);
signal RIN_E_JMPL_intermed_1 : STD_ULOGIC;
signal RIN_A_CTRL_TRAP_intermed_1 : STD_ULOGIC;
signal V_A_SU_shadow_intermed_1 : STD_ULOGIC;
signal RIN_A_RFE2_intermed_1 : STD_ULOGIC;
signal RIN_D_PC_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_CNT_intermed_3 : std_logic_vector(1 downto 0);
signal V_M_CTRL_PC31DOWNTO12_shadow_intermed_3 : std_logic_vector(31 downto 12);
signal V_M_CTRL_PC3DOWNTO2_shadow_intermed_2 : std_logic_vector(3 downto 2);
signal VIR_ADDR31DOWNTO12_shadow_intermed_1 : std_logic_vector(31 downto 12);
signal RIN_E_CTRL_LD_intermed_2 : STD_ULOGIC;
signal V_E_CTRL_PC31DOWNTO12_shadow_intermed_2 : std_logic_vector(31 downto 12);
signal R_E_CTRL_PC31DOWNTO12_intermed_4 : std_logic_vector(31 downto 12);
signal V_X_CTRL_PC3DOWNTO2_shadow_intermed_2 : std_logic_vector(3 downto 2);
signal V_A_CTRL_INST24_shadow_intermed_2 : STD_LOGIC;
signal V_M_CTRL_TRAP_shadow_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_PC31DOWNTO4_shadow_intermed_3 : std_logic_vector(31 downto 4);
signal V_A_CTRL_PC3DOWNTO2_shadow_intermed_4 : std_logic_vector(3 downto 2);
signal R_A_CTRL_PC31DOWNTO2_intermed_5 : std_logic_vector(31 downto 2);
signal R_X_DATA0_intermed_1 : std_logic_vector(31 downto 0);
signal V_E_CTRL_TT_shadow_intermed_2 : std_logic_vector(5 downto 0);
signal V_E_MAC_shadow_intermed_2 : STD_ULOGIC;
signal RIN_E_CTRL_INST19_intermed_2 : STD_LOGIC;
signal RIN_D_PC31DOWNTO2_intermed_3 : std_logic_vector(31 downto 2);
signal IRIN_ADDR_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_X_ANNUL_ALL_intermed_3 : STD_ULOGIC;
signal RIN_E_CTRL_INST_intermed_2 : std_logic_vector(31 downto 0);
signal V_X_CTRL_PC_shadow_intermed_2 : std_logic_vector(31 downto 2);
signal R_M_CTRL_TRAP_intermed_1 : STD_ULOGIC;
signal V_D_CWP_shadow_intermed_2 : std_logic_vector(2 downto 0);
signal V_A_CTRL_PC31DOWNTO12_shadow_intermed_2 : std_logic_vector(31 downto 12);
signal V_A_CTRL_LD_shadow_intermed_1 : STD_ULOGIC;
signal R_A_CTRL_INST19_intermed_2 : STD_LOGIC;
signal RIN_X_MEXC_intermed_1 : STD_ULOGIC;
signal RIN_D_MEXC_intermed_4 : STD_ULOGIC;
signal RIN_A_MULSTART_intermed_1 : STD_ULOGIC;
signal RIN_A_CTRL_TT_intermed_1 : std_logic_vector(5 downto 0);
signal RIN_M_CTRL_TT3DOWNTO0_intermed_2 : std_logic_vector(3 downto 0);
signal R_D_INST1_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_A_CTRL_intermed_1 : PIPELINE_CTRL_TYPE;
signal R_E_CTRL_WICC_intermed_1 : STD_ULOGIC;
signal RIN_M_CTRL_TT3DOWNTO0_intermed_3 : std_logic_vector(3 downto 0);
signal V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 : std_logic_vector(31 downto 2);
signal V_A_CTRL_TT3DOWNTO0_shadow_intermed_1 : std_logic_vector(3 downto 0);
signal RIN_M_DCI_SIGNED_intermed_2 : STD_ULOGIC;
signal V_E_CTRL_TT3DOWNTO0_shadow_intermed_3 : std_logic_vector(3 downto 0);
signal IRIN_ADDR31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4);
signal RIN_X_SET_intermed_1 : STD_LOGIC_VECTOR(0 downto 0);
signal V_M_CTRL_WREG_shadow_intermed_2 : STD_ULOGIC;
signal RIN_X_CTRL_PC31DOWNTO12_intermed_4 : std_logic_vector(31 downto 12);
signal V_D_PC_shadow_intermed_5 : std_logic_vector(31 downto 2);
signal RIN_X_CTRL_TT3DOWNTO0_intermed_2 : std_logic_vector(3 downto 0);
signal R_D_INST0_intermed_1 : std_logic_vector(31 downto 0);
signal R_E_CTRL_PC31DOWNTO4_intermed_4 : std_logic_vector(31 downto 4);
signal RIN_D_CNT_intermed_1 : std_logic_vector(1 downto 0);
signal R_E_CTRL_PC3DOWNTO2_intermed_4 : std_logic_vector(3 downto 2);
signal V_M_DCI_SIGNED_shadow_intermed_2 : STD_ULOGIC;
signal R_D_CNT_intermed_2 : std_logic_vector(1 downto 0);
signal R_E_CTRL_INST20_intermed_1 : STD_LOGIC;
signal RIN_M_DCI_SIGNED_intermed_1 : STD_ULOGIC;
signal RIN_D_PC3DOWNTO2_intermed_5 : std_logic_vector(3 downto 2);
signal RIN_A_CTRL_INST19_intermed_3 : STD_LOGIC;
signal V_E_CTRL_shadow_intermed_1 : PIPELINE_CTRL_TYPE;
signal RIN_A_CTRL_WICC_intermed_1 : STD_ULOGIC;
signal V_X_DATA1_shadow_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_D_CWP_intermed_2 : std_logic_vector(2 downto 0);
signal R_E_CTRL_INST24_intermed_2 : STD_LOGIC;
signal V_A_CTRL_WREG_shadow_intermed_2 : STD_ULOGIC;
signal DCO_DATA031_intermed_2 : STD_LOGIC;
signal R_M_CTRL_TT_intermed_1 : std_logic_vector(5 downto 0);
signal RIN_E_CTRL_WREG_intermed_3 : STD_ULOGIC;
signal V_E_YMSB_shadow_intermed_1 : STD_ULOGIC;
signal IRIN_ADDR31DOWNTO2_intermed_3 : std_logic_vector(31 downto 2);
signal EX_JUMP_ADDRESS3DOWNTO2_shadow_intermed_1 : std_logic_vector(3 downto 2);
signal V_M_CTRL_INST_shadow_intermed_2 : std_logic_vector(31 downto 0);
signal DE_INST24_shadow_intermed_3 : STD_LOGIC;
signal V_D_PC31DOWNTO12_shadow_intermed_2 : std_logic_vector(31 downto 12);
signal V_A_CTRL_PC_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_X_RESULT6DOWNTO0_intermed_1 : std_logic_vector(6 downto 0);
signal R_A_CTRL_PC31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2);
signal V_E_CTRL_CNT_shadow_intermed_1 : std_logic_vector(1 downto 0);
signal VIR_ADDR3DOWNTO2_shadow_intermed_1 : std_logic_vector(3 downto 2);
signal RIN_A_CTRL_INST_intermed_2 : std_logic_vector(31 downto 0);
signal RIN_A_CTRL_intermed_3 : PIPELINE_CTRL_TYPE;
signal RIN_M_RESULT1DOWNTO0_intermed_1 : std_logic_vector(1 downto 0);
signal R_A_CTRL_PV_intermed_3 : STD_ULOGIC;
signal R_D_PC31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2);
signal R_A_CTRL_PC31DOWNTO4_intermed_5 : std_logic_vector(31 downto 4);
signal RIN_A_DIVSTART_intermed_1 : STD_ULOGIC;
signal VIR_ADDR31DOWNTO12_shadow_intermed_2 : std_logic_vector(31 downto 12);
signal V_E_CTRL_INST20_shadow_intermed_2 : STD_LOGIC;
signal RIN_M_CTRL_TT_intermed_1 : std_logic_vector(5 downto 0);
signal RIN_E_CTRL_RD7DOWNTO0_intermed_3 : std_logic_vector(7 downto 0);
signal RIN_D_CWP_intermed_1 : std_logic_vector(2 downto 0);
signal RIN_X_CTRL_WREG_intermed_1 : STD_ULOGIC;
signal RIN_X_CTRL_PC31DOWNTO2_intermed_4 : std_logic_vector(31 downto 2);
signal V_M_CTRL_PC31DOWNTO2_shadow_intermed_5 : std_logic_vector(31 downto 2);
signal RIN_D_PC31DOWNTO2_intermed_7 : std_logic_vector(31 downto 2);
signal RIN_X_CTRL_PC31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2);
signal DSUR_CRDY2_intermed_1 : STD_LOGIC;
signal R_E_CTRL_PC3DOWNTO2_intermed_2 : std_logic_vector(3 downto 2);
signal V_A_CTRL_RD7DOWNTO0_shadow_intermed_1 : std_logic_vector(7 downto 0);
signal R_D_PC31DOWNTO12_intermed_3 : std_logic_vector(31 downto 12);
signal RIN_X_DATA031_intermed_2 : STD_LOGIC;
signal RIN_D_PC31DOWNTO4_intermed_4 : std_logic_vector(31 downto 4);
signal RIN_A_CTRL_INST_intermed_4 : std_logic_vector(31 downto 0);
signal V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 : std_logic_vector(31 downto 2);
signal V_M_CTRL_PC31DOWNTO4_shadow_intermed_2 : std_logic_vector(31 downto 4);
signal DE_INST19_shadow_intermed_1 : STD_LOGIC;
signal RIN_E_CTRL_PC31DOWNTO2_intermed_3 : std_logic_vector(31 downto 2);
signal V_A_CTRL_RD7DOWNTO0_shadow_intermed_2 : std_logic_vector(7 downto 0);
signal V_E_CTRL_INST_shadow_intermed_3 : std_logic_vector(31 downto 0);
signal RIN_X_CTRL_PC31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_X_CTRL_intermed_1 : PIPELINE_CTRL_TYPE;
signal R_D_PC31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12);
signal RIN_A_CTRL_ANNUL_intermed_2 : STD_ULOGIC;
signal V_A_CTRL_CNT_shadow_intermed_3 : std_logic_vector(1 downto 0);
signal R_A_CTRL_PC31DOWNTO12_intermed_6 : std_logic_vector(31 downto 12);
signal V_M_CTRL_PC31DOWNTO12_shadow_intermed_4 : std_logic_vector(31 downto 12);
signal VIR_ADDR31DOWNTO2_shadow_intermed_3 : std_logic_vector(31 downto 2);
signal V_A_MULSTART_shadow_intermed_1 : STD_ULOGIC;
signal RIN_X_DATA1_intermed_2 : std_logic_vector(31 downto 0);
signal RIN_E_CTRL_PC_intermed_2 : std_logic_vector(31 downto 2);
signal V_E_CTRL_PC31DOWNTO12_shadow_intermed_5 : std_logic_vector(31 downto 12);
signal V_M_DCI_SIZE_shadow_intermed_1 : std_logic_vector(1 downto 0);
signal V_A_CTRL_PC31DOWNTO4_shadow_intermed_3 : std_logic_vector(31 downto 4);
signal R_X_RESULT6DOWNTO03DOWNTO0_intermed_3 : std_logic_vector(3 downto 0);
signal R_D_PC31DOWNTO4_intermed_6 : std_logic_vector(31 downto 4);
signal EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_2 : STD_LOGIC_VECTOR(32 downto 3);
signal V_A_CTRL_PV_shadow_intermed_4 : STD_ULOGIC;
signal V_A_CTRL_TT_shadow_intermed_4 : std_logic_vector(5 downto 0);
signal V_X_CTRL_PC3DOWNTO2_shadow_intermed_3 : std_logic_vector(3 downto 2);
signal RIN_X_DATA0_intermed_2 : std_logic_vector(31 downto 0);
signal R_A_CTRL_TT3DOWNTO0_intermed_4 : std_logic_vector(3 downto 0);
signal RIN_D_PC31DOWNTO4_intermed_3 : std_logic_vector(31 downto 4);
signal V_A_CTRL_WREG_shadow_intermed_4 : STD_ULOGIC;
signal RIN_A_CTRL_PC3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2);
signal RIN_D_PC31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2);
signal R_M_CTRL_PC_intermed_2 : std_logic_vector(31 downto 2);
signal R_F_PC31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_M_CTRL_WREG_intermed_1 : STD_ULOGIC;
signal RIN_W_WREG_intermed_1 : STD_ULOGIC;
signal RIN_D_PC31DOWNTO4_intermed_6 : std_logic_vector(31 downto 4);
signal R_D_ANNUL_intermed_1 : STD_ULOGIC;
signal R_A_CTRL_INST_intermed_3 : std_logic_vector(31 downto 0);
signal RIN_M_CTRL_PC31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_E_CTRL_WREG_intermed_2 : STD_ULOGIC;
signal V_E_SARI_shadow_intermed_1 : STD_ULOGIC;
signal R_E_CTRL_RD6DOWNTO0_intermed_2 : std_logic_vector(6 downto 0);
signal V_A_CTRL_PC31DOWNTO2_shadow_intermed_6 : std_logic_vector(31 downto 2);
signal R_A_CTRL_CNT_intermed_3 : std_logic_vector(1 downto 0);
signal RIN_M_CTRL_PV_intermed_2 : STD_ULOGIC;
signal R_A_CTRL_LD_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_WICC_shadow_intermed_2 : STD_ULOGIC;
signal RIN_D_PC31DOWNTO2_intermed_5 : std_logic_vector(31 downto 2);
signal V_D_PC3DOWNTO2_shadow_intermed_3 : std_logic_vector(3 downto 2);
signal RIN_A_CTRL_PC3DOWNTO2_intermed_6 : std_logic_vector(3 downto 2);
signal RIN_X_DATA04DOWNTO0_intermed_1 : std_logic_vector(4 downto 0);
signal DSUIN_CRDY2_intermed_1 : STD_LOGIC;
signal RIN_D_PC31DOWNTO12_intermed_4 : std_logic_vector(31 downto 12);
signal R_E_CTRL_RD6DOWNTO0_intermed_1 : std_logic_vector(6 downto 0);
signal RIN_A_CTRL_INST20_intermed_1 : STD_LOGIC;
signal R_M_RESULT1DOWNTO0_intermed_2 : std_logic_vector(1 downto 0);
signal RIN_M_DCI_SIZE_intermed_2 : std_logic_vector(1 downto 0);
signal DE_INST19_shadow_intermed_3 : STD_LOGIC;
signal IRIN_ADDR31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12);
signal V_A_CTRL_ANNUL_shadow_intermed_4 : STD_ULOGIC;
signal R_E_CTRL_CNT_intermed_1 : std_logic_vector(1 downto 0);
signal V_E_CTRL_INST24_shadow_intermed_2 : STD_LOGIC;
signal RIN_A_CTRL_PC31DOWNTO4_intermed_2 : std_logic_vector(31 downto 4);
signal IRIN_PWD_intermed_1 : STD_ULOGIC;
signal V_D_MEXC_shadow_intermed_5 : STD_ULOGIC;
signal RIN_A_CTRL_PV_intermed_1 : STD_ULOGIC;
signal V_A_CTRL_WICC_shadow_intermed_1 : STD_ULOGIC;
signal R_A_CTRL_PC_intermed_1 : std_logic_vector(31 downto 2);
signal V_F_PC31DOWNTO4_shadow_intermed_1 : std_logic_vector(31 downto 4);
signal R_A_CTRL_RD7DOWNTO0_intermed_3 : std_logic_vector(7 downto 0);
signal RIN_A_CTRL_PC_intermed_1 : std_logic_vector(31 downto 2);
signal R_E_CTRL_INST_intermed_1 : std_logic_vector(31 downto 0);
signal R_E_CTRL_PC31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4);
signal V_A_CTRL_TRAP_shadow_intermed_4 : STD_ULOGIC;
signal V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 : std_logic_vector(31 downto 2);
signal V_F_PC31DOWNTO12_shadow_intermed_1 : std_logic_vector(31 downto 12);
signal R_A_CTRL_PC3DOWNTO2_intermed_5 : std_logic_vector(3 downto 2);
signal R_A_CTRL_CNT_intermed_1 : std_logic_vector(1 downto 0);
signal RIN_D_PC31DOWNTO2_intermed_6 : std_logic_vector(31 downto 2);
signal R_E_CTRL_PC3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2);
signal RIN_X_DATA0_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_E_CTRL_PC_intermed_3 : std_logic_vector(31 downto 2);
signal R_X_CTRL_PC31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12);
signal RIN_X_DATA03_intermed_1 : STD_LOGIC;
signal R_X_DATA04DOWNTO0_intermed_2 : std_logic_vector(4 downto 0);
signal R_E_CTRL_ANNUL_intermed_1 : STD_ULOGIC;
signal V_A_CTRL_RD7DOWNTO0_shadow_intermed_3 : std_logic_vector(7 downto 0);
signal V_M_CTRL_TT3DOWNTO0_shadow_intermed_3 : std_logic_vector(3 downto 0);
signal RIN_X_MAC_intermed_1 : STD_ULOGIC;
signal V_E_SHCNT_shadow_intermed_1 : std_logic_vector(4 downto 0);
signal V_M_CTRL_TT3DOWNTO0_shadow_intermed_2 : std_logic_vector(3 downto 0);
signal V_D_PC31DOWNTO12_shadow_intermed_4 : std_logic_vector(31 downto 12);
signal RIN_D_PC31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12);
signal V_E_CTRL_PC3DOWNTO2_shadow_intermed_5 : std_logic_vector(3 downto 2);
signal RIN_E_CTRL_RETT_intermed_2 : STD_ULOGIC;
signal R_M_CTRL_PC31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2);
signal V_E_OP23_shadow_intermed_1 : STD_LOGIC;
signal V_D_PC_shadow_intermed_2 : std_logic_vector(31 downto 2);
signal R_D_PC3DOWNTO2_intermed_6 : std_logic_vector(3 downto 2);
signal R_M_CTRL_PV_intermed_1 : STD_ULOGIC;
signal RIN_W_RESULT_intermed_1 : std_logic_vector(31 downto 0);
signal V_E_CTRL_ANNUL_shadow_intermed_2 : STD_ULOGIC;
signal V_E_CTRL_PV_shadow_intermed_1 : STD_ULOGIC;
signal RIN_X_LADDR_intermed_1 : std_logic_vector(1 downto 0);
signal RIN_A_CTRL_PC_intermed_5 : std_logic_vector(31 downto 2);
signal XC_VECTT3DOWNTO0_shadow_intermed_1 : STD_LOGIC_VECTOR(3 downto 0);
signal R_E_CTRL_WREG_intermed_1 : STD_ULOGIC;
signal RIN_X_DATA03_intermed_2 : STD_LOGIC;
signal RIN_A_CTRL_TT_intermed_3 : std_logic_vector(5 downto 0);
signal V_D_STEP_shadow_intermed_1 : STD_ULOGIC;
signal R_M_CTRL_PC31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12);
signal DE_INST19_shadow_intermed_2 : STD_LOGIC;
signal RIN_M_CTRL_PC31DOWNTO2_intermed_3 : std_logic_vector(31 downto 2);
signal V_X_CTRL_TRAP_shadow_intermed_1 : STD_ULOGIC;
signal RIN_D_MEXC_intermed_5 : STD_ULOGIC;
signal RIN_X_CTRL_TRAP_intermed_1 : STD_ULOGIC;
signal V_D_PC3DOWNTO2_shadow_intermed_4 : std_logic_vector(3 downto 2);
signal V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 : std_logic_vector(3 downto 0);
signal RIN_A_CTRL_PC3DOWNTO2_intermed_5 : std_logic_vector(3 downto 2);
signal RIN_M_CTRL_PC31DOWNTO4_intermed_3 : std_logic_vector(31 downto 4);
signal RIN_M_CTRL_PC31DOWNTO2_intermed_4 : std_logic_vector(31 downto 2);
signal RIN_F_BRANCH_intermed_1 : STD_ULOGIC;
signal R_D_PC3DOWNTO2_intermed_5 : std_logic_vector(3 downto 2);
signal RIN_A_CTRL_WREG_intermed_1 : STD_ULOGIC;
signal RIN_D_INST0_intermed_2 : std_logic_vector(31 downto 0);
signal R_M_CTRL_CNT_intermed_1 : std_logic_vector(1 downto 0);
signal RIN_E_CTRL_RD7DOWNTO0_intermed_1 : std_logic_vector(7 downto 0);
signal RIN_A_CTRL_PC_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_X_CTRL_PC_intermed_1 : std_logic_vector(31 downto 2);
signal R_A_SU_intermed_1 : STD_ULOGIC;
signal RIN_A_CTRL_TT_intermed_4 : std_logic_vector(5 downto 0);
signal V_X_DATA00_shadow_intermed_2 : STD_LOGIC;
signal RIN_A_CTRL_PC31DOWNTO4_intermed_4 : std_logic_vector(31 downto 4);
signal RIN_A_JMPL_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_WREG_shadow_intermed_3 : STD_ULOGIC;
signal V_A_CTRL_WREG_shadow_intermed_1 : STD_ULOGIC;
signal RIN_M_CTRL_ANNUL_intermed_1 : STD_ULOGIC;
signal RIN_X_CTRL_PC31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12);
signal VIR_ADDR31DOWNTO2_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal V_A_CTRL_PC3DOWNTO2_shadow_intermed_1 : std_logic_vector(3 downto 2);
signal RIN_E_CTRL_TT3DOWNTO0_intermed_3 : std_logic_vector(3 downto 0);
signal RIN_M_CTRL_RD7DOWNTO0_intermed_2 : std_logic_vector(7 downto 0);
signal V_E_CTRL_TRAP_shadow_intermed_3 : STD_ULOGIC;
signal V_A_CTRL_CNT_shadow_intermed_2 : std_logic_vector(1 downto 0);
signal V_E_CTRL_ANNUL_shadow_intermed_1 : STD_ULOGIC;
signal V_W_S_TT3DOWNTO0_shadow_intermed_1 : STD_LOGIC_VECTOR(3 downto 0);
signal RIN_M_CTRL_CNT_intermed_1 : std_logic_vector(1 downto 0);
signal DSUR_CRDY2_intermed_2 : STD_LOGIC;
signal V_E_CTRL_RD6DOWNTO0_shadow_intermed_1 : std_logic_vector(6 downto 0);
signal V_A_CTRL_CNT_shadow_intermed_1 : std_logic_vector(1 downto 0);
signal R_E_CTRL_PC_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_M_SU_intermed_1 : STD_ULOGIC;
signal RIN_A_CTRL_RD6DOWNTO0_intermed_1 : std_logic_vector(6 downto 0);
signal R_M_CTRL_TT3DOWNTO0_intermed_3 : std_logic_vector(3 downto 0);
signal RIN_M_CTRL_TT3DOWNTO0_intermed_4 : std_logic_vector(3 downto 0);
signal V_A_CTRL_INST19_shadow_intermed_1 : STD_LOGIC;
signal R_D_PC31DOWNTO2_intermed_5 : std_logic_vector(31 downto 2);
signal RIN_E_CTRL_CNT_intermed_3 : std_logic_vector(1 downto 0);
signal R_E_CTRL_PC31DOWNTO12_intermed_3 : std_logic_vector(31 downto 12);
signal RIN_E_CTRL_TRAP_intermed_1 : STD_ULOGIC;
signal RIN_X_DATA00_intermed_3 : STD_LOGIC;
signal R_E_CTRL_PC_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_E_OP131_intermed_1 : STD_LOGIC;
signal R_D_CNT_intermed_1 : std_logic_vector(1 downto 0);
signal R_D_PC_intermed_3 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_PC31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12);
signal R_M_CTRL_WREG_intermed_1 : STD_ULOGIC;
signal R_D_PC31DOWNTO2_intermed_4 : std_logic_vector(31 downto 2);
signal DE_INST_shadow_intermed_3 : std_logic_vector(31 downto 0);
signal RIN_D_PC_intermed_3 : std_logic_vector(31 downto 2);
signal V_A_CTRL_INST20_shadow_intermed_3 : STD_LOGIC;
signal R_A_CTRL_TT3DOWNTO0_intermed_5 : std_logic_vector(3 downto 0);
signal RIN_A_CTRL_CNT_intermed_2 : std_logic_vector(1 downto 0);
signal RIN_A_CTRL_intermed_2 : PIPELINE_CTRL_TYPE;
signal RIN_X_CTRL_PC_intermed_2 : std_logic_vector(31 downto 2);
signal R_A_CTRL_WREG_intermed_1 : STD_ULOGIC;
signal V_X_CTRL_PC31DOWNTO2_shadow_intermed_4 : std_logic_vector(31 downto 2);
signal R_X_CTRL_PC31DOWNTO2_intermed_3 : std_logic_vector(31 downto 2);
signal RIN_D_PC_intermed_6 : std_logic_vector(31 downto 2);
signal RIN_E_CTRL_PC31DOWNTO4_intermed_3 : std_logic_vector(31 downto 4);
signal R_X_CTRL_PC31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2);
signal V_A_ET_shadow_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_PC31DOWNTO4_shadow_intermed_1 : std_logic_vector(31 downto 4);
signal RIN_A_CTRL_INST20_intermed_3 : STD_LOGIC;
signal RIN_W_EXCEPT_intermed_1 : STD_ULOGIC;
signal V_X_DATA031_shadow_intermed_2 : STD_LOGIC;
signal R_A_CTRL_ANNUL_intermed_1 : STD_ULOGIC;
signal R_F_PC31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12);
signal RIN_E_CTRL_RD6DOWNTO0_intermed_2 : std_logic_vector(6 downto 0);
signal VIR_ADDR31DOWNTO2_shadow_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_X_DATA00_intermed_1 : STD_LOGIC;
signal RIN_E_CTRL_ANNUL_intermed_1 : STD_ULOGIC;
signal RIN_E_CTRL_PC31DOWNTO4_intermed_5 : std_logic_vector(31 downto 4);
signal V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_3 : std_logic_vector(3 downto 0);
signal V_M_CTRL_WICC_shadow_intermed_1 : STD_ULOGIC;
signal V_A_CTRL_PC31DOWNTO2_shadow_intermed_7 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_RETT_intermed_1 : STD_ULOGIC;
signal RIN_E_CTRL_PC31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2);
signal V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_D_PC31DOWNTO12_intermed_5 : std_logic_vector(31 downto 12);
signal VIR_ADDR3DOWNTO2_shadow_intermed_2 : std_logic_vector(3 downto 2);
signal R_A_CTRL_PV_intermed_2 : STD_ULOGIC;
signal V_A_CTRL_PC3DOWNTO2_shadow_intermed_2 : std_logic_vector(3 downto 2);
signal R_E_CTRL_PC3DOWNTO2_intermed_3 : std_logic_vector(3 downto 2);
signal V_A_CTRL_ANNUL_shadow_intermed_3 : STD_ULOGIC;
signal RIN_A_CTRL_PC3DOWNTO2_intermed_4 : std_logic_vector(3 downto 2);
signal V_A_CTRL_TT3DOWNTO0_shadow_intermed_3 : std_logic_vector(3 downto 0);
signal R_A_CTRL_PC3DOWNTO2_intermed_2 : std_logic_vector(3 downto 2);
signal V_D_CNT_shadow_intermed_2 : std_logic_vector(1 downto 0);
signal V_M_CTRL_ANNUL_shadow_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_M_CTRL_PC31DOWNTO4_intermed_2 : std_logic_vector(31 downto 4);
signal R_M_CTRL_TT3DOWNTO0_intermed_1 : std_logic_vector(3 downto 0);
signal V_E_CTRL_LD_shadow_intermed_2 : STD_ULOGIC;
signal RIN_X_CTRL_ANNUL_intermed_1 : STD_ULOGIC;
signal RIN_D_PC3DOWNTO2_intermed_3 : std_logic_vector(3 downto 2);
signal V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 : std_logic_vector(31 downto 2);
signal RIN_E_CTRL_TT_intermed_2 : std_logic_vector(5 downto 0);
signal RIN_E_CTRL_CNT_intermed_2 : std_logic_vector(1 downto 0);
signal RIN_A_CTRL_PC_intermed_4 : std_logic_vector(31 downto 2);
signal RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_4 : std_logic_vector(3 downto 0);
signal R_D_PC31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12);
signal XC_TRAP_ADDRESS31DOWNTO4_shadow_intermed_1 : std_logic_vector(31 downto 4);
signal RIN_A_CTRL_INST24_intermed_3 : STD_LOGIC;
signal V_W_S_TT3DOWNTO0_shadow_intermed_2 : STD_LOGIC_VECTOR(3 downto 0);
signal RIN_E_CTRL_RD7DOWNTO0_intermed_2 : std_logic_vector(7 downto 0);
signal RIN_A_CTRL_INST24_intermed_1 : STD_LOGIC;
signal RIN_D_PC31DOWNTO4_intermed_2 : std_logic_vector(31 downto 4);
signal V_A_CTRL_shadow_intermed_2 : PIPELINE_CTRL_TYPE;
signal DE_INST_shadow_intermed_4 : std_logic_vector(31 downto 0);
signal RIN_E_CTRL_PV_intermed_3 : STD_ULOGIC;
signal V_A_CTRL_TT_shadow_intermed_2 : std_logic_vector(5 downto 0);
signal RIN_M_CTRL_PC_intermed_3 : std_logic_vector(31 downto 2);
signal V_A_CTRL_WREG_shadow_intermed_3 : STD_ULOGIC;
signal R_M_CTRL_RD6DOWNTO0_intermed_1 : std_logic_vector(6 downto 0);
signal XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_PV_intermed_2 : STD_ULOGIC;
signal RIN_E_CTRL_PC3DOWNTO2_intermed_2 : std_logic_vector(3 downto 2);
signal RIN_X_CTRL_RD7DOWNTO0_intermed_1 : std_logic_vector(7 downto 0);
signal V_A_CTRL_TRAP_shadow_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_TRAP_shadow_intermed_1 : STD_ULOGIC;
signal RIN_E_MAC_intermed_1 : STD_ULOGIC;
signal R_X_DATA00_intermed_2 : STD_LOGIC;
signal RIN_E_MAC_intermed_2 : STD_ULOGIC;
signal RIN_A_CTRL_RD7DOWNTO0_intermed_4 : std_logic_vector(7 downto 0);
signal RIN_A_CTRL_PC31DOWNTO2_intermed_7 : std_logic_vector(31 downto 2);
signal R_M_CTRL_PC31DOWNTO12_intermed_3 : std_logic_vector(31 downto 12);
signal V_D_PC_shadow_intermed_3 : std_logic_vector(31 downto 2);
signal RIN_D_PC31DOWNTO4_intermed_5 : std_logic_vector(31 downto 4);
signal V_M_RESULT1DOWNTO0_shadow_intermed_2 : std_logic_vector(1 downto 0);
signal R_E_CTRL_PC31DOWNTO4_intermed_2 : std_logic_vector(31 downto 4);
signal V_E_CTRL_PC31DOWNTO12_shadow_intermed_3 : std_logic_vector(31 downto 12);
signal V_X_INTACK_shadow_intermed_1 : STD_ULOGIC;
signal RIN_A_CTRL_ANNUL_intermed_5 : STD_ULOGIC;
signal V_M_CTRL_PC31DOWNTO4_shadow_intermed_3 : std_logic_vector(31 downto 4);
signal V_A_CTRL_TT3DOWNTO0_shadow_intermed_4 : std_logic_vector(3 downto 0);
signal RIN_X_RESULT_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_E_CTRL_TT3DOWNTO0_intermed_5 : std_logic_vector(3 downto 0);
signal RIN_A_CTRL_PC31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2);
signal EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal V_D_PC3DOWNTO2_shadow_intermed_5 : std_logic_vector(3 downto 2);
signal DE_INST20_shadow_intermed_1 : STD_LOGIC;
signal V_E_CTRL_RD7DOWNTO0_shadow_intermed_2 : std_logic_vector(7 downto 0);
signal V_X_CTRL_PC31DOWNTO12_shadow_intermed_4 : std_logic_vector(31 downto 12);
signal V_E_CTRL_TRAP_shadow_intermed_2 : STD_ULOGIC;
signal V_A_CTRL_PC31DOWNTO4_shadow_intermed_5 : std_logic_vector(31 downto 4);
signal V_A_CTRL_RD6DOWNTO0_shadow_intermed_2 : std_logic_vector(6 downto 0);
signal RIN_A_CTRL_PC31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12);
signal IR_ADDR31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12);
signal RIN_E_ALUCIN_intermed_1 : STD_ULOGIC;
signal R_X_CTRL_PC31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12);
signal R_A_CTRL_PC3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2);
signal DE_INST_shadow_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_M_CTRL_INST_intermed_2 : std_logic_vector(31 downto 0);
signal R_A_CTRL_TRAP_intermed_2 : STD_ULOGIC;
signal RIN_A_CTRL_PC31DOWNTO12_intermed_4 : std_logic_vector(31 downto 12);
signal R_A_CTRL_WREG_intermed_2 : STD_ULOGIC;
signal R_M_CTRL_PC31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4);
signal V_E_OP13_shadow_intermed_1 : STD_LOGIC;
signal V_A_CTRL_INST24_shadow_intermed_1 : STD_LOGIC;
signal V_X_CTRL_PC31DOWNTO12_shadow_intermed_3 : std_logic_vector(31 downto 12);
signal IRIN_ADDR31DOWNTO12_intermed_3 : std_logic_vector(31 downto 12);
signal V_X_CTRL_PC_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal R_M_CTRL_PC3DOWNTO2_intermed_3 : std_logic_vector(3 downto 2);
signal V_E_CTRL_PC3DOWNTO2_shadow_intermed_2 : std_logic_vector(3 downto 2);
signal RIN_X_CTRL_TT_intermed_1 : std_logic_vector(5 downto 0);
signal V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_TT3DOWNTO0_intermed_6 : std_logic_vector(3 downto 0);
signal RIN_D_PC3DOWNTO2_intermed_7 : std_logic_vector(3 downto 2);
signal V_A_CTRL_INST_shadow_intermed_2 : std_logic_vector(31 downto 0);
signal V_X_CTRL_PC31DOWNTO4_shadow_intermed_1 : std_logic_vector(31 downto 4);
signal V_M_RESULT1DOWNTO0_shadow_intermed_1 : std_logic_vector(1 downto 0);
signal R_A_CTRL_INST24_intermed_2 : STD_LOGIC;
signal R_F_PC31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2);
signal V_A_CTRL_TRAP_shadow_intermed_3 : STD_ULOGIC;
signal R_D_CNT_intermed_4 : std_logic_vector(1 downto 0);
signal RIN_A_CTRL_WREG_intermed_4 : STD_ULOGIC;
signal V_M_CTRL_PC31DOWNTO4_shadow_intermed_1 : std_logic_vector(31 downto 4);
signal RIN_A_CTRL_PC3DOWNTO2_intermed_3 : std_logic_vector(3 downto 2);
signal V_E_CTRL_INST20_shadow_intermed_1 : STD_LOGIC;
signal R_D_MEXC_intermed_2 : STD_ULOGIC;
signal R_D_PC_intermed_4 : std_logic_vector(31 downto 2);
signal RIN_D_PC_intermed_1 : std_logic_vector(31 downto 2);
signal IRIN_ADDR3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2);
signal V_E_CTRL_RD7DOWNTO0_shadow_intermed_1 : std_logic_vector(7 downto 0);
signal RIN_E_OP1_intermed_1 : std_logic_vector(31 downto 0);
signal V_D_PC31DOWNTO4_shadow_intermed_3 : std_logic_vector(31 downto 4);
signal V_A_CTRL_PV_shadow_intermed_3 : STD_ULOGIC;
signal V_D_PC31DOWNTO2_shadow_intermed_6 : std_logic_vector(31 downto 2);
signal V_X_CTRL_TT3DOWNTO0_shadow_intermed_2 : std_logic_vector(3 downto 0);
signal DE_INST20_shadow_intermed_2 : STD_LOGIC;
signal V_E_CTRL_RD7DOWNTO0_shadow_intermed_3 : std_logic_vector(7 downto 0);
signal V_E_CTRL_CNT_shadow_intermed_3 : std_logic_vector(1 downto 0);
signal RIN_E_CTRL_RETT_intermed_1 : STD_ULOGIC;
signal V_D_PC31DOWNTO12_shadow_intermed_3 : std_logic_vector(31 downto 12);
signal V_D_PC31DOWNTO12_shadow_intermed_7 : std_logic_vector(31 downto 12);
signal V_M_CTRL_CNT_shadow_intermed_2 : std_logic_vector(1 downto 0);
signal R_D_PC31DOWNTO4_intermed_3 : std_logic_vector(31 downto 4);
signal RIN_A_CTRL_PC3DOWNTO2_intermed_2 : std_logic_vector(3 downto 2);
signal RIN_X_INTACK_intermed_1 : STD_ULOGIC;
signal RIN_E_OP231_intermed_1 : STD_LOGIC;
signal RIN_X_DATA031_intermed_3 : STD_LOGIC;
signal RIN_D_PC31DOWNTO2_intermed_4 : std_logic_vector(31 downto 2);
signal V_D_PC31DOWNTO4_shadow_intermed_2 : std_logic_vector(31 downto 4);
signal V_A_CTRL_ANNUL_shadow_intermed_1 : STD_ULOGIC;
signal R_M_CTRL_TT3DOWNTO0_intermed_2 : std_logic_vector(3 downto 0);
signal V_F_PC_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_E_ET_intermed_1 : STD_ULOGIC;
signal V_D_MEXC_shadow_intermed_3 : STD_ULOGIC;
signal XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_2 : std_logic_vector(31 downto 2);
signal V_F_PC31DOWNTO2_shadow_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_E_CTRL_PV_intermed_2 : STD_ULOGIC;
signal R_A_CTRL_RD7DOWNTO0_intermed_1 : std_logic_vector(7 downto 0);
signal ICO_MEXC_intermed_2 : STD_ULOGIC;
signal V_X_DCI_SIGNED_shadow_intermed_1 : STD_ULOGIC;
signal RIN_A_STEP_intermed_1 : STD_ULOGIC;
signal V_E_ALUCIN_shadow_intermed_1 : STD_ULOGIC;
signal V_A_CTRL_PC31DOWNTO4_shadow_intermed_6 : std_logic_vector(31 downto 4);
signal V_D_CNT_shadow_intermed_3 : std_logic_vector(1 downto 0);
signal V_D_PC31DOWNTO4_shadow_intermed_1 : std_logic_vector(31 downto 4);
signal RIN_X_CTRL_CNT_intermed_1 : std_logic_vector(1 downto 0);
signal V_D_ANNUL_shadow_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_PC31DOWNTO2_shadow_intermed_5 : std_logic_vector(31 downto 2);
signal V_E_CTRL_PV_shadow_intermed_3 : STD_ULOGIC;
signal VP_ERROR_shadow_intermed_1 : STD_ULOGIC;
signal RIN_X_RESULT6DOWNTO0_intermed_2 : std_logic_vector(6 downto 0);
signal R_D_PC31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4);
signal RIN_F_PC31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_E_CTRL_PC_intermed_1 : std_logic_vector(31 downto 2);
signal R_A_CTRL_PC31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12);
signal RIN_A_CTRL_PC31DOWNTO12_intermed_6 : std_logic_vector(31 downto 12);
signal V_A_CTRL_INST24_shadow_intermed_3 : STD_LOGIC;
signal V_E_CTRL_PC_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal V_X_CTRL_RD7DOWNTO0_shadow_intermed_1 : std_logic_vector(7 downto 0);
signal RIN_M_MUL_intermed_1 : STD_ULOGIC;
signal RIN_A_CTRL_INST20_intermed_2 : STD_LOGIC;
signal RIN_A_CTRL_RD7DOWNTO0_intermed_1 : std_logic_vector(7 downto 0);
signal V_A_CTRL_TT3DOWNTO0_shadow_intermed_2 : std_logic_vector(3 downto 0);
signal R_A_CTRL_INST_intermed_2 : std_logic_vector(31 downto 0);
signal RIN_E_CTRL_PC31DOWNTO2_intermed_6 : std_logic_vector(31 downto 2);
signal V_M_CTRL_TT_shadow_intermed_2 : std_logic_vector(5 downto 0);
signal V_D_INST0_shadow_intermed_2 : std_logic_vector(31 downto 0);
signal DCO_DATA03_intermed_1 : STD_LOGIC;
signal RIN_M_CTRL_intermed_1 : PIPELINE_CTRL_TYPE;
signal RIN_A_CTRL_RD7DOWNTO0_intermed_3 : std_logic_vector(7 downto 0);
signal V_D_PC31DOWNTO2_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_E_CTRL_PC31DOWNTO4_intermed_2 : std_logic_vector(31 downto 4);
signal V_D_PC31DOWNTO12_shadow_intermed_8 : std_logic_vector(31 downto 12);
signal RIN_E_CTRL_LD_intermed_1 : STD_ULOGIC;
signal R_X_CTRL_PC_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_WY_intermed_1 : STD_ULOGIC;
signal RIN_D_PC3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2);
signal R_E_CTRL_INST24_intermed_1 : STD_LOGIC;
signal V_M_DCI_shadow_intermed_1 : DC_IN_TYPE;
signal V_M_CTRL_shadow_intermed_1 : PIPELINE_CTRL_TYPE;
signal RIN_M_DCI_SIZE_intermed_1 : std_logic_vector(1 downto 0);
signal R_E_CTRL_PV_intermed_2 : STD_ULOGIC;
signal EX_ADD_RES32DOWNTO3_shadow_intermed_1 : STD_LOGIC_VECTOR(32 downto 3);
signal RIN_D_MEXC_intermed_1 : STD_ULOGIC;
signal R_A_CTRL_PC31DOWNTO2_intermed_3 : std_logic_vector(31 downto 2);
signal DSUIN_TBUFCNT_intermed_1 : STD_LOGIC_VECTOR(6 downto 0);
signal R_E_CTRL_PC31DOWNTO12_intermed_5 : std_logic_vector(31 downto 12);
signal R_A_CTRL_PC3DOWNTO2_intermed_4 : std_logic_vector(3 downto 2);
signal V_A_CTRL_INST20_shadow_intermed_1 : STD_LOGIC;
signal RIN_E_CTRL_PC31DOWNTO12_intermed_3 : std_logic_vector(31 downto 12);
signal V_A_CTRL_RD6DOWNTO0_shadow_intermed_4 : std_logic_vector(6 downto 0);
signal R_E_CTRL_PC31DOWNTO2_intermed_4 : std_logic_vector(31 downto 2);
signal R_A_CTRL_TT3DOWNTO0_intermed_2 : std_logic_vector(3 downto 0);
signal RIN_A_CTRL_CNT_intermed_4 : std_logic_vector(1 downto 0);
signal V_D_INST1_shadow_intermed_2 : std_logic_vector(31 downto 0);
signal RIN_E_CTRL_INST_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_X_DEBUG_intermed_1 : STD_ULOGIC;
signal RIN_M_Y_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_E_SHCNT_intermed_1 : std_logic_vector(4 downto 0);
signal RIN_E_CTRL_TRAP_intermed_2 : STD_ULOGIC;
signal RIN_F_PC31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12);
signal R_E_CTRL_INST20_intermed_2 : STD_LOGIC;
signal RIN_A_CTRL_ANNUL_intermed_3 : STD_ULOGIC;
signal RIN_D_ANNUL_intermed_2 : STD_ULOGIC;
signal ICO_DATA1_intermed_1 : std_logic_vector(31 downto 0);
signal R_M_CTRL_PC31DOWNTO12_intermed_4 : std_logic_vector(31 downto 12);
signal V_M_CTRL_TT3DOWNTO0_shadow_intermed_1 : std_logic_vector(3 downto 0);
signal V_X_CTRL_TT3DOWNTO0_shadow_intermed_1 : std_logic_vector(3 downto 0);
signal RIN_D_MEXC_intermed_3 : STD_ULOGIC;
signal V_E_CTRL_INST24_shadow_intermed_1 : STD_LOGIC;
signal R_W_S_TT3DOWNTO0_intermed_2 : STD_LOGIC_VECTOR(3 downto 0);
signal DSUIN_CRDY2_intermed_2 : STD_LOGIC;
signal V_X_RESULT6DOWNTO0_shadow_intermed_2 : std_logic_vector(6 downto 0);
signal RIN_D_PC3DOWNTO2_intermed_2 : std_logic_vector(3 downto 2);
signal V_D_PC_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal R_A_CTRL_PC31DOWNTO4_intermed_2 : std_logic_vector(31 downto 4);
signal RIN_E_CTRL_RD6DOWNTO0_intermed_3 : std_logic_vector(6 downto 0);
signal R_A_CTRL_PC31DOWNTO12_intermed_4 : std_logic_vector(31 downto 12);
signal V_X_DATA031_shadow_intermed_1 : STD_LOGIC;
signal RIN_X_ANNUL_ALL_intermed_2 : STD_ULOGIC;
signal IRIN_ADDR3DOWNTO2_intermed_2 : std_logic_vector(3 downto 2);
signal RIN_D_SET_intermed_1 : STD_LOGIC_VECTOR(0 downto 0);
signal DCO_DATA0_intermed_1 : std_logic_vector(31 downto 0);
signal R_E_CTRL_CNT_intermed_2 : std_logic_vector(1 downto 0);
signal RIN_W_S_S_intermed_2 : STD_ULOGIC;
signal IRIN_ADDR31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12);
signal RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_3 : std_logic_vector(3 downto 0);
signal RIN_W_S_TT3DOWNTO0_intermed_2 : STD_LOGIC_VECTOR(3 downto 0);
signal V_A_CTRL_LD_shadow_intermed_3 : STD_ULOGIC;
signal V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 : std_logic_vector(31 downto 2);
signal RIN_M_CTRL_PC_intermed_2 : std_logic_vector(31 downto 2);
signal R_D_INST1_intermed_2 : std_logic_vector(31 downto 0);
signal V_E_CTRL_shadow_intermed_2 : PIPELINE_CTRL_TYPE;
signal RIN_X_DATA1_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_A_SU_intermed_2 : STD_ULOGIC;
signal R_A_CTRL_RD6DOWNTO0_intermed_2 : std_logic_vector(6 downto 0);
signal RIN_A_CTRL_PC31DOWNTO2_intermed_3 : std_logic_vector(31 downto 2);
signal RIN_E_CTRL_intermed_1 : PIPELINE_CTRL_TYPE;
signal RIN_A_CTRL_RD6DOWNTO0_intermed_3 : std_logic_vector(6 downto 0);
signal RIN_A_CTRL_TT3DOWNTO0_intermed_1 : std_logic_vector(3 downto 0);
signal RIN_F_PC_intermed_1 : std_logic_vector(31 downto 2);
signal V_D_PC31DOWNTO2_shadow_intermed_8 : std_logic_vector(31 downto 2);
signal V_D_CNT_shadow_intermed_1 : std_logic_vector(1 downto 0);
signal RIN_A_CTRL_LD_intermed_2 : STD_ULOGIC;
signal V_D_PC31DOWNTO4_shadow_intermed_5 : std_logic_vector(31 downto 4);
signal RIN_M_CTRL_PC31DOWNTO4_intermed_4 : std_logic_vector(31 downto 4);
signal R_A_CTRL_RETT_intermed_1 : STD_ULOGIC;
signal RIN_E_CTRL_INST_intermed_3 : std_logic_vector(31 downto 0);
signal R_D_MEXC_intermed_4 : STD_ULOGIC;
signal RIN_M_RESULT1DOWNTO0_intermed_3 : std_logic_vector(1 downto 0);
signal RIN_D_CNT_intermed_5 : std_logic_vector(1 downto 0);
signal V_A_CTRL_PC31DOWNTO12_shadow_intermed_1 : std_logic_vector(31 downto 12);
signal R_D_PC31DOWNTO2_intermed_3 : std_logic_vector(31 downto 2);
signal RIN_M_CTRL_PC31DOWNTO12_intermed_4 : std_logic_vector(31 downto 12);
signal RIN_M_CTRL_TT3DOWNTO0_intermed_1 : std_logic_vector(3 downto 0);
signal RIN_D_ANNUL_intermed_1 : STD_ULOGIC;
signal V_A_CTRL_shadow_intermed_1 : PIPELINE_CTRL_TYPE;
signal V_E_CTRL_PC31DOWNTO12_shadow_intermed_1 : std_logic_vector(31 downto 12);
signal RIN_M_CTRL_PC3DOWNTO2_intermed_4 : std_logic_vector(3 downto 2);
signal V_A_CTRL_PC31DOWNTO12_shadow_intermed_5 : std_logic_vector(31 downto 12);
signal R_D_PC31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_E_CTRL_PC3DOWNTO2_intermed_5 : std_logic_vector(3 downto 2);
signal RIN_E_CTRL_PC31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12);
signal R_A_CTRL_PC_intermed_4 : std_logic_vector(31 downto 2);
signal R_A_CTRL_ANNUL_intermed_4 : STD_ULOGIC;
signal V_X_RESULT_shadow_intermed_1 : std_logic_vector(31 downto 0);
signal R_E_CTRL_PC31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2);
signal R_A_CTRL_PC31DOWNTO4_intermed_3 : std_logic_vector(31 downto 4);
signal V_D_CNT_shadow_intermed_5 : std_logic_vector(1 downto 0);
signal R_A_CTRL_TT_intermed_2 : std_logic_vector(5 downto 0);
signal RIN_A_CTRL_PC31DOWNTO12_intermed_5 : std_logic_vector(31 downto 12);
signal V_A_CTRL_TT3DOWNTO0_shadow_intermed_5 : std_logic_vector(3 downto 0);
signal RIN_W_S_S_intermed_1 : STD_ULOGIC;
signal V_M_CTRL_CNT_shadow_intermed_1 : std_logic_vector(1 downto 0);
signal V_A_CTRL_PC31DOWNTO12_shadow_intermed_7 : std_logic_vector(31 downto 12);
signal V_A_CTRL_WICC_shadow_intermed_2 : STD_ULOGIC;
signal R_X_DATA03_intermed_1 : STD_LOGIC;
signal RIN_M_DCI_intermed_1 : DC_IN_TYPE;
signal R_A_CTRL_CNT_intermed_2 : std_logic_vector(1 downto 0);
signal RIN_W_S_EF_intermed_1 : STD_ULOGIC;
signal V_E_CTRL_RD6DOWNTO0_shadow_intermed_2 : std_logic_vector(6 downto 0);
signal RIN_A_CTRL_LD_intermed_3 : STD_ULOGIC;
signal V_M_CTRL_RD6DOWNTO0_shadow_intermed_1 : std_logic_vector(6 downto 0);
signal R_E_CTRL_INST_intermed_2 : std_logic_vector(31 downto 0);
signal RIN_M_CTRL_RD6DOWNTO0_intermed_1 : std_logic_vector(6 downto 0);
signal V_F_PC3DOWNTO2_shadow_intermed_1 : std_logic_vector(3 downto 2);
signal EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_2 : STD_LOGIC_VECTOR(30 downto 11);
signal V_X_ANNUL_ALL_shadow_intermed_3 : STD_ULOGIC;
signal V_F_PC31DOWNTO12_shadow_intermed_2 : std_logic_vector(31 downto 12);
signal RIN_E_CTRL_INST24_intermed_1 : STD_LOGIC;
signal R_A_CTRL_PV_intermed_1 : STD_ULOGIC;
signal RIN_A_CTRL_RETT_intermed_3 : STD_ULOGIC;
signal R_E_CTRL_TT_intermed_2 : std_logic_vector(5 downto 0);
signal RIN_D_PC31DOWNTO12_intermed_7 : std_logic_vector(31 downto 12);
signal EX_ADD_RES32DOWNTO34DOWNTO3_shadow_intermed_1 : STD_LOGIC_VECTOR(4 downto 3);
signal V_E_CTRL_INST_shadow_intermed_2 : std_logic_vector(31 downto 0);
signal V_M_CTRL_PC31DOWNTO12_shadow_intermed_1 : std_logic_vector(31 downto 12);
signal DCO_MEXC_intermed_1 : STD_ULOGIC;
signal RIN_E_CWP_intermed_1 : std_logic_vector(2 downto 0);
signal V_A_CTRL_CNT_shadow_intermed_4 : std_logic_vector(1 downto 0);
signal V_A_CTRL_ANNUL_shadow_intermed_2 : STD_ULOGIC;
signal R_A_CTRL_PC31DOWNTO12_intermed_3 : std_logic_vector(31 downto 12);
signal R_A_CTRL_PC31DOWNTO2_intermed_4 : std_logic_vector(31 downto 2);
signal R_X_RESULT6DOWNTO0_intermed_2 : std_logic_vector(6 downto 0);
signal RIN_A_SU_intermed_1 : STD_ULOGIC;
signal R_E_CTRL_intermed_1 : PIPELINE_CTRL_TYPE;
signal V_E_OP231_shadow_intermed_1 : STD_LOGIC;
signal RIN_A_CTRL_WREG_intermed_3 : STD_ULOGIC;
signal V_A_CTRL_INST_shadow_intermed_4 : std_logic_vector(31 downto 0);
signal V_E_CTRL_PC31DOWNTO12_shadow_intermed_6 : std_logic_vector(31 downto 12);
signal V_M_CTRL_PC3DOWNTO2_shadow_intermed_1 : std_logic_vector(3 downto 2);
signal RPIN_ERROR_intermed_2 : STD_ULOGIC;
signal R_E_CTRL_TT3DOWNTO0_intermed_3 : std_logic_vector(3 downto 0);
signal V_D_CWP_shadow_intermed_1 : std_logic_vector(2 downto 0);
signal V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_PV_intermed_3 : STD_ULOGIC;
signal RIN_M_CTRL_PC31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4);
signal RIN_E_CTRL_INST24_intermed_2 : STD_LOGIC;
signal RIN_X_DCI_SIZE_intermed_1 : std_logic_vector(1 downto 0);
signal RIN_F_PC31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12);
signal R_A_CTRL_TT3DOWNTO0_intermed_3 : std_logic_vector(3 downto 0);
signal DCO_DATA00_intermed_1 : STD_LOGIC;
signal V_M_Y31_shadow_intermed_1 : STD_LOGIC;
signal R_E_CTRL_PC31DOWNTO2_intermed_5 : std_logic_vector(31 downto 2);
signal R_A_CTRL_PC31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2);
signal V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal R_A_CTRL_INST19_intermed_1 : STD_LOGIC;
signal RIN_E_CTRL_TT_intermed_1 : std_logic_vector(5 downto 0);
signal RIN_E_CTRL_PC31DOWNTO2_intermed_2 : std_logic_vector(31 downto 2);
signal R_X_CTRL_PC3DOWNTO2_intermed_2 : std_logic_vector(3 downto 2);
signal RIN_X_ANNUL_ALL_intermed_4 : STD_ULOGIC;
signal V_A_CTRL_INST_shadow_intermed_1 : std_logic_vector(31 downto 0);
signal V_X_CTRL_PC31DOWNTO12_shadow_intermed_2 : std_logic_vector(31 downto 12);
signal IRIN_ADDR31DOWNTO4_intermed_2 : std_logic_vector(31 downto 4);
signal RIN_E_CTRL_PC3DOWNTO2_intermed_4 : std_logic_vector(3 downto 2);
signal RIN_A_CTRL_PC31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4);
signal DCO_DATA04DOWNTO0_intermed_1 : std_logic_vector(4 downto 0);
signal RIN_E_CTRL_ANNUL_intermed_2 : STD_ULOGIC;
signal V_E_CTRL_INST19_shadow_intermed_1 : STD_LOGIC;
signal RIN_A_CTRL_PC_intermed_3 : std_logic_vector(31 downto 2);
signal V_X_DATA03_shadow_intermed_1 : STD_LOGIC;
signal V_E_OP1_shadow_intermed_1 : std_logic_vector(31 downto 0);
signal RIN_M_CTRL_CNT_intermed_2 : std_logic_vector(1 downto 0);
signal RIN_A_CTRL_PC31DOWNTO2_intermed_6 : std_logic_vector(31 downto 2);
signal RIN_D_MEXC_intermed_2 : STD_ULOGIC;
signal R_D_PC31DOWNTO4_intermed_2 : std_logic_vector(31 downto 4);
signal RIN_X_CTRL_INST_intermed_1 : std_logic_vector(31 downto 0);
signal V_A_SU_shadow_intermed_2 : STD_ULOGIC;
signal V_M_Y31_shadow_intermed_2 : STD_LOGIC;
signal R_W_S_TT3DOWNTO0_intermed_1 : STD_LOGIC_VECTOR(3 downto 0);
signal R_A_CTRL_ANNUL_intermed_3 : STD_ULOGIC;
signal R_A_CTRL_TRAP_intermed_1 : STD_ULOGIC;
signal RIN_M_CTRL_WICC_intermed_1 : STD_ULOGIC;
signal R_D_PC31DOWNTO2_intermed_7 : std_logic_vector(31 downto 2);
signal RIN_X_ANNUL_ALL_intermed_1 : STD_ULOGIC;
signal V_M_CTRL_WREG_shadow_intermed_1 : STD_ULOGIC;
signal V_A_CTRL_RD7DOWNTO0_shadow_intermed_4 : std_logic_vector(7 downto 0);
signal RIN_A_RFE1_intermed_1 : STD_ULOGIC;
signal V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal V_D_PC31DOWNTO4_shadow_intermed_4 : std_logic_vector(31 downto 4);
signal R_A_CTRL_PC31DOWNTO12_intermed_2 : std_logic_vector(31 downto 12);
signal V_M_MAC_shadow_intermed_1 : STD_ULOGIC;
signal V_D_PC31DOWNTO2_shadow_intermed_2 : std_logic_vector(31 downto 2);
signal RIN_A_CTRL_TRAP_intermed_2 : STD_ULOGIC;
signal R_E_CTRL_RD7DOWNTO0_intermed_1 : std_logic_vector(7 downto 0);
signal R_E_CTRL_PC_intermed_3 : std_logic_vector(31 downto 2);
signal R_X_DATA00_intermed_1 : STD_LOGIC;
signal V_X_ANNUL_ALL_shadow_intermed_1 : STD_ULOGIC;
signal R_D_PC_intermed_5 : std_logic_vector(31 downto 2);
signal R_X_DATA03_intermed_2 : STD_LOGIC;
signal RIN_F_PC31DOWNTO4_intermed_1 : std_logic_vector(31 downto 4);
signal RIN_W_S_CWP_intermed_1 : std_logic_vector(2 downto 0);
signal V_W_S_PS_shadow_intermed_1 : STD_ULOGIC;
signal R_A_CTRL_intermed_1 : PIPELINE_CTRL_TYPE;
signal R_A_CTRL_TT_intermed_3 : std_logic_vector(5 downto 0);
signal RIN_A_CTRL_PC31DOWNTO4_intermed_6 : std_logic_vector(31 downto 4);
signal V_D_PC31DOWNTO2_shadow_intermed_7 : std_logic_vector(31 downto 2);
signal RIN_M_CTRL_PC31DOWNTO2_intermed_1 : std_logic_vector(31 downto 2);
signal R_X_DATA1_intermed_2 : std_logic_vector(31 downto 0);
signal R_D_PC3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2);
signal RIN_X_CTRL_PC3DOWNTO2_intermed_1 : std_logic_vector(3 downto 2);
signal V_E_MAC_shadow_intermed_1 : STD_ULOGIC;
signal RIN_X_ICC_intermed_1 : STD_LOGIC_VECTOR(3 downto 0);
signal RIN_M_MAC_intermed_1 : STD_ULOGIC;
signal RIN_W_S_TT3DOWNTO0_intermed_1 : STD_LOGIC_VECTOR(3 downto 0);
signal R_D_PC31DOWNTO4_intermed_4 : std_logic_vector(31 downto 4);
signal V_A_CTRL_PC3DOWNTO2_shadow_intermed_6 : std_logic_vector(3 downto 2);
signal R_X_ANNUL_ALL_intermed_1 : STD_ULOGIC;
signal EX_JUMP_ADDRESS_shadow_intermed_1 : std_logic_vector(31 downto 2);
signal RIN_X_CTRL_PV_intermed_1 : STD_ULOGIC;
signal EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_2 : STD_LOGIC_VECTOR(32 downto 13);
signal RIN_A_CTRL_INST_intermed_1 : std_logic_vector(31 downto 0);
signal R_A_CTRL_RD6DOWNTO0_intermed_3 : std_logic_vector(6 downto 0);
signal IR_ADDR31DOWNTO12_intermed_1 : std_logic_vector(31 downto 12);
signal RIN_D_PC3DOWNTO2_intermed_6 : std_logic_vector(3 downto 2);
signal RIN_M_Y31_intermed_2 : STD_LOGIC;
signal RIN_X_DATA04DOWNTO0_intermed_2 : std_logic_vector(4 downto 0);
signal V_D_PC31DOWNTO2_shadow_intermed_3 : std_logic_vector(31 downto 2);
signal R_M_DCI_SIZE_intermed_1 : std_logic_vector(1 downto 0);
signal V_E_CTRL_PC3DOWNTO2_shadow_intermed_4 : std_logic_vector(3 downto 2);
signal V_E_OP2_shadow_intermed_1 : std_logic_vector(31 downto 0);
signal V_E_CTRL_TT3DOWNTO0_shadow_intermed_5 : std_logic_vector(3 downto 0);
signal V_A_CTRL_INST20_shadow_intermed_2 : STD_LOGIC;
signal RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 : std_logic_vector(3 downto 0);
signal V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_4 : std_logic_vector(3 downto 0);
signal R_X_RESULT6DOWNTO03DOWNTO0_intermed_2 : std_logic_vector(3 downto 0);
signal RIN_M_CTRL_TRAP_intermed_2 : STD_ULOGIC;
signal V_A_CTRL_INST_shadow_intermed_3 : std_logic_vector(31 downto 0);
signal dfp_bscan_cntrl : STD_LOGIC_VECTOR(35 downto 0);
signal dfp_bscan_value : STD_LOGIC_VECTOR(123 downto 0);
component scope
PORT (
CONTROL : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
ASYNC_IN : IN STD_LOGIC_VECTOR(123 DOWNTO 0)
);
end component;
component iconScope
PORT (
CONTROL0 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0)
);
end component;
attribute syn_black_box : boolean;
attribute syn_noprune : integer;
attribute syn_black_box of iconScope: component is true;
attribute syn_black_box of scope: component is true;
attribute syn_noprune of iconScope: component is 1;
attribute syn_noprune of scope: component is 1;
begin
comb : process(ico, dco, rfo, r, wpr, ir, dsur, rstn, holdn, irqi, dbgi, fpo, cpo, tbo, mulo, divo, dummy, rp, handlerTrap)
variable v : registers;
variable vp : pwd_register_type;
variable vwpr : watchpoint_registers;
variable vdsu : dsu_registers;
variable npc : std_logic_vector(31 downto 2);
variable de_raddr1, de_raddr2 : std_logic_vector(9 downto 0);
variable de_rs2, de_rd : std_logic_vector(4 downto 0);
variable de_hold_pc, de_branch, de_fpop, de_ldlock : std_ulogic;
variable de_cwp, de_cwp2 : cwptype;
variable de_inull : std_ulogic;
variable de_ren1, de_ren2 : std_ulogic;
variable de_wcwp : std_ulogic;
variable de_inst : word;
variable de_branch_address : pctype;
variable de_icc : std_logic_vector(3 downto 0);
variable de_fbranch, de_cbranch : std_ulogic;
variable de_rs1mod : std_ulogic;
variable ra_op1, ra_op2 : word;
variable ra_div : std_ulogic;
variable ex_jump, ex_link_pc : std_ulogic;
variable ex_jump_address : pctype;
variable ex_add_res : std_logic_vector(32 downto 0);
variable ex_shift_res, ex_logic_res, ex_misc_res : word;
variable ex_edata, ex_edata2 : word;
variable ex_dci : dc_in_type;
variable ex_force_a2, ex_load, ex_ymsb : std_ulogic;
variable ex_op1, ex_op2, ex_result, ex_result2, mul_op2 : word;
variable ex_shcnt : std_logic_vector(4 downto 0);
variable ex_dsuen : std_ulogic;
variable ex_ldbp2 : std_ulogic;
variable ex_sari : std_ulogic;
variable me_inull, me_nullify, me_nullify2 : std_ulogic;
variable me_iflush : std_ulogic;
variable me_newtt : std_logic_vector(5 downto 0);
variable me_asr18 : word;
variable me_signed : std_ulogic;
variable me_size, me_laddr : std_logic_vector(1 downto 0);
variable me_icc : std_logic_vector(3 downto 0);
variable xc_result : word;
variable xc_df_result : word;
variable xc_waddr : std_logic_vector(9 downto 0);
variable xc_exception, xc_wreg : std_ulogic;
variable xc_trap_address : pctype;
variable xc_vectt : std_logic_vector(7 downto 0);
variable xc_trap : std_ulogic;
variable xc_fpexack : std_ulogic;
variable xc_rstn, xc_halt : std_ulogic;
-- variable wr_rf1_data, wr_rf2_data : word;
variable diagdata : word;
variable tbufi : tracebuf_in_type;
variable dbgm : std_ulogic;
variable fpcdbgwr : std_ulogic;
variable vfpi : fpc_in_type;
variable dsign : std_ulogic;
variable pwrd, sidle : std_ulogic;
variable vir : irestart_register;
variable icnt : std_ulogic;
variable tbufcntx : std_logic_vector(7-1 downto 0);
begin
v := r;
vwpr := wpr;
vdsu := dsur;
vp := rp;
xc_fpexack := '0';
sidle := '0';
fpcdbgwr := '0';
vir := ir;
xc_rstn := rstn;
-----------------------------------------------------------------------
-- WRITE STAGE
-----------------------------------------------------------------------
-- wr_rf1_data := rfo.data1; wr_rf2_data := rfo.data2;
-- if irfwt = 0 then
-- if r.w.wreg = '1' then
-- if r.a.rfa1 = r.w.wa then wr_rf1_data := r.w.result; end if;
-- if r.a.rfa2 = r.w.wa then wr_rf2_data := r.w.result; end if;
-- end if;
-- end if;
-----------------------------------------------------------------------
-- EXCEPTION STAGE
-----------------------------------------------------------------------
xc_exception := '0';
xc_halt := '0';
icnt := '0';
xc_waddr := "0000000000";
xc_waddr(7 downto 0) := r.x.ctrl.rd(7 downto 0);
xc_trap := r.x.mexc or r.x.ctrl.trap or handlerTrap;
v.x.nerror := rp.error;
if(handlerTrap = '1')then
xc_vectt := "00" & TT_WATCH;
elsif r.x.mexc = '1' then
xc_vectt := "00" & TT_DAEX;
elsif r.x.ctrl.tt = TT_TICC then
xc_vectt := '1' & r.x.result(6 downto 0);
else
xc_vectt := "00" & r.x.ctrl.tt;
end if;
if r.w.s.svt = '0' then
xc_trap_address(31 downto 4) := r.w.s.tba & xc_vectt;
else
xc_trap_address(31 downto 4) := r.w.s.tba & "00000000";
end if;
xc_trap_address(3 downto 2) := "00";
xc_wreg := '0';
v.x.annul_all := '0';
if (r.x.ctrl.ld = '1') then
if (lddel = 2) then
xc_result := ld_align(r.x.data, r.x.set, r.x.dci.size, r.x.laddr, r.x.dci.signed);
else
xc_result := r.x.data(0);
end if;
else
xc_result := r.x.result;
end if;
xc_df_result := xc_result;
dbgm := dbgexc(r, dbgi, xc_trap, xc_vectt);
if (dbgi.dsuen and dbgi.dbreak) = '0'then
v.x.debug := '0';
end if;
pwrd := '0';
case r.x.rstate is
when run =>
if (not r.x.ctrl.annul and r.x.ctrl.pv and not r.x.debug) = '1' then
icnt := holdn;
end if;
if dbgm = '1' then
v.x.annul_all := '1';
vir.addr := r.x.ctrl.pc;
v.x.rstate := dsu1;
v.x.debug := '1';
v.x.npc := npc_find(r);
vdsu.tt := xc_vectt;
vdsu.err := dbgerr(r, dbgi, xc_vectt);
elsif (pwrd = '1') and (ir.pwd = '0') then
v.x.annul_all := '1';
vir.addr := r.x.ctrl.pc;
v.x.rstate := dsu1;
v.x.npc := npc_find(r);
vp.pwd := '1';
elsif (r.x.ctrl.annul or xc_trap) = '0' then
xc_wreg := r.x.ctrl.wreg;
sp_write (r, wpr, v.w.s, vwpr);
vir.pwd := '0';
elsif ((not r.x.ctrl.annul) and xc_trap) = '1' then
xc_exception := '1';
xc_result := r.x.ctrl.pc(31 downto 2) & "00";
xc_wreg := '1';
v.w.s.tt := xc_vectt;
v.w.s.ps := r.w.s.s;
v.w.s.s := '1';
v.x.annul_all := '1';
v.x.rstate := trap;
xc_waddr := "0000000000";
xc_waddr(6 downto 0) := r.w.s.cwp & "0001";
v.x.npc := npc_find(r);
fpexack(r, xc_fpexack);
if r.w.s.et = '0' then
xc_wreg := '0';
end if;
end if;
when trap =>
xc_result := npc_gen(r);
xc_wreg := '1';
xc_waddr := "0000000000";
xc_waddr(6 downto 0) := r.w.s.cwp & "0010";
if (r.w.s.et = '1') then
v.w.s.et := '0';
v.x.rstate := run;
v.w.s.cwp := r.w.s.cwp - 1;
else
v.x.rstate := dsu1;
xc_wreg := '0';
vp.error := '1';
end if;
when dsu1 =>
xc_exception := '1';
v.x.annul_all := '1';
xc_trap_address(31 downto 2) := r.f.pc;
xc_trap_address(31 downto 2) := ir.addr;
vir.addr := npc_gen(r)(31 downto 2);
v.x.rstate := dsu2;
v.x.debug := r.x.debug;
when dsu2 =>
xc_exception := '1';
v.x.annul_all := '1';
xc_trap_address(31 downto 2) := r.f.pc;
sidle := (rp.pwd or rp.error) and ico.idle and dco.idle and not r.x.debug;
if dbgi.reset = '1' then
vp.pwd := '0';
vp.error := '0';
end if;
if (dbgi.dsuen and dbgi.dbreak) = '1'then
v.x.debug := '1';
end if;
diagwr(r, dsur, ir, dbgi, wpr, v.w.s, vwpr, vdsu.asi, xc_trap_address, vir.addr, vdsu.tbufcnt, xc_wreg, xc_waddr, xc_result, fpcdbgwr);
xc_halt := dbgi.halt;
if r.x.ipend = '1' then
vp.pwd := '0';
end if;
if (rp.error or rp.pwd or r.x.debug or xc_halt) = '0' then
v.x.rstate := run;
v.x.annul_all := '0';
vp.error := '0';
xc_trap_address(31 downto 2) := ir.addr;
v.x.debug := '0';
vir.pwd := '1';
end if;
when others =>
end case;
irq_intack(r, holdn, v.x.intack);
itrace(r, dsur, vdsu, xc_result, xc_exception, dbgi, rp.error, xc_trap, tbufcntx, tbufi);
vdsu.tbufcnt := tbufcntx;
v.w.except := xc_exception;
v.w.result := xc_result;
if (r.x.rstate = dsu2) then
v.w.except := '0';
end if;
v.w.wa := xc_waddr(7 downto 0);
v.w.wreg := xc_wreg and holdn;
rfi.wdata <= xc_result;
rfi.waddr <= xc_waddr;
rfi.wren <= (xc_wreg and holdn) and not dco.scanen;
irqo.intack <= r.x.intack and holdn;
irqo.irl <= r.w.s.tt(3 downto 0);
irqo.pwd <= rp.pwd;
irqo.fpen <= r.w.s.ef;
dbgo.halt <= xc_halt;
dbgo.pwd <= rp.pwd;
dbgo.idle <= sidle;
dbgo.icnt <= icnt;
dci.intack <= r.x.intack and holdn;
if (xc_rstn = '0') then
v.w.except := '0';
v.w.s.et := '0';
v.w.s.svt := '0';
v.w.s.dwt := '0';
v.w.s.ef := '0';-- needed for AX
v.x.annul_all := '1';
v.x.rstate := run;
vir.pwd := '0';
vp.pwd := '0';
v.x.debug := '0';
v.x.nerror := '0';
if (dbgi.dsuen and dbgi.dbreak) = '1' then
v.x.rstate := dsu1;
v.x.debug := '1';
end if;
end if;
if not FPEN then
v.w.s.ef := '0';
end if;
-----------------------------------------------------------------------
-- MEMORY STAGE
-----------------------------------------------------------------------
v.x.ctrl := r.m.ctrl;
v.x.dci := r.m.dci;
v.x.ctrl.rett := r.m.ctrl.rett and not r.m.ctrl.annul;
v.x.mac := r.m.mac;
v.x.laddr := r.m.result(1 downto 0);
v.x.ctrl.annul := r.m.ctrl.annul or v.x.annul_all;
mul_res(r, v.w.s.asr18, v.x.result, v.x.y, me_asr18, me_icc);
mem_trap(r, wpr, v.x.ctrl.annul, holdn, v.x.ctrl.trap, me_iflush, me_nullify, v.m.werr, v.x.ctrl.tt);
me_newtt := v.x.ctrl.tt;
irq_trap(r, ir, irqi.irl, v.x.ctrl.annul, v.x.ctrl.pv, v.x.ctrl.trap, me_newtt, me_nullify, v.m.irqen, v.m.irqen2, me_nullify2, v.x.ctrl.trap, v.x.ipend, v.x.ctrl.tt);
if (r.m.ctrl.ld or not dco.mds) = '1' then
v.x.data(0) := dco.data(0);
v.x.data(1) := dco.data(1);
v.x.set := dco.set(0 downto 0);
if dco.mds = '0' then
me_size := r.x.dci.size;
me_laddr := r.x.laddr;
me_signed := r.x.dci.signed;
else
me_size := v.x.dci.size;
me_laddr := v.x.laddr;
me_signed := v.x.dci.signed;
end if;
if lddel /= 2 then
v.x.data(0) := ld_align(v.x.data, v.x.set, me_size, me_laddr, me_signed);
end if;
end if;
v.x.mexc := dco.mexc;
v.x.icc := me_icc;
v.x.ctrl.wicc := r.m.ctrl.wicc and not v.x.annul_all;
if (r.x.rstate = dsu2) then
me_nullify2 := '0';
v.x.set := dco.set(0 downto 0);
end if;
dci.maddress <= r.m.result;
dci.msu <= r.m.su;
dci.esu <= r.e.su;
dci.enaddr <= r.m.dci.enaddr;
dci.asi <= r.m.dci.asi;
dci.size <= r.m.dci.size;
dci.nullify <= me_nullify2;
dci.lock <= r.m.dci.lock and not r.m.ctrl.annul;
dci.read <= r.m.dci.read;
dci.write <= r.m.dci.write;
dci.flush <= me_iflush;
dci.dsuen <= r.m.dci.dsuen;
dbgo.ipend <= v.x.ipend;
-----------------------------------------------------------------------
-- EXECUTE STAGE
-----------------------------------------------------------------------
v.m.ctrl := r.e.ctrl;
ex_op1 := r.e.op1;
ex_op2 := r.e.op2;
v.m.ctrl.rett := r.e.ctrl.rett and not r.e.ctrl.annul;
v.m.ctrl.wreg := r.e.ctrl.wreg and not v.x.annul_all;
ex_ymsb := r.e.ymsb;
mul_op2 := ex_op2;
ex_shcnt := r.e.shcnt;
v.e.cwp := r.a.cwp;
ex_sari := r.e.sari;
v.m.su := r.e.su;
v.m.mul := '0';
if lddel = 1 then
if r.e.ldbp1 = '1' then
ex_op1 := r.x.data(0);
ex_sari := r.x.data(0)(31) and r.e.ctrl.inst(19) and r.e.ctrl.inst(20);
end if;
if r.e.ldbp2 = '1' then
ex_op2 := r.x.data(0);
ex_ymsb := r.x.data(0)(0);
mul_op2 := ex_op2;
ex_shcnt := r.x.data(0)(4 downto 0);
if r.e.invop2 = '1' then
ex_op2 := not ex_op2;
ex_shcnt := not ex_shcnt;
end if;
end if;
end if;
ex_add_res := (ex_op1 & '1') + (ex_op2 & r.e.alucin);
if ex_add_res(2 downto 1) = "00" then
v.m.nalign := '0';
else
v.m.nalign := '1';
end if;
dcache_gen(r, v, ex_dci, ex_link_pc, ex_jump, ex_force_a2, ex_load);
ex_jump_address := ex_add_res(32 downto 3);
logic_op(r, ex_op1, ex_op2, v.x.y, ex_ymsb, ex_logic_res, v.m.y);
ex_shift_res := shift(r, ex_op1, ex_op2, ex_shcnt, ex_sari);
misc_op(r, wpr, ex_op1, ex_op2, xc_df_result, v.x.y, ex_misc_res, ex_edata);
ex_add_res(3):= ex_add_res(3) or ex_force_a2;
alu_select(r, ex_add_res, ex_op1, ex_op2, ex_shift_res, ex_logic_res, ex_misc_res, ex_result, me_icc, v.m.icc, v.m.divz);
dbg_cache(holdn, dbgi, r, dsur, ex_result, ex_dci, ex_result2, v.m.dci);
fpstdata(r, ex_edata, ex_result2, fpo.data, ex_edata2, v.m.result);
cwp_ex(r, v.m.wcwp);
v.m.ctrl.annul := v.m.ctrl.annul or v.x.annul_all;
v.m.ctrl.wicc := r.e.ctrl.wicc and not v.x.annul_all;
v.m.mac := r.e.mac;
if (true and (r.x.rstate = dsu2)) then
v.m.ctrl.ld := '1';
end if;
dci.eenaddr <= v.m.dci.enaddr;
dci.eaddress <= ex_add_res(32 downto 1);
dci.edata <= ex_edata2;
-----------------------------------------------------------------------
-- REGFILE STAGE
-----------------------------------------------------------------------
v.e.ctrl := r.a.ctrl;
v.e.jmpl := r.a.jmpl;
v.e.ctrl.annul := r.a.ctrl.annul or v.x.annul_all;
v.e.ctrl.rett := r.a.ctrl.rett and not r.a.ctrl.annul;
v.e.ctrl.wreg := r.a.ctrl.wreg and not v.x.annul_all;
v.e.su := r.a.su;
v.e.et := r.a.et;
v.e.ctrl.wicc := r.a.ctrl.wicc and not v.x.annul_all;
exception_detect(r, wpr, dbgi, r.a.ctrl.trap, r.a.ctrl.tt, v.e.ctrl.trap, v.e.ctrl.tt);
op_mux(r, rfo.data1, v.m.result, v.x.result, xc_df_result, "00000000000000000000000000000000", r.a.rsel1, v.e.ldbp1, ra_op1);
op_mux(r, rfo.data2, v.m.result, v.x.result, xc_df_result, r.a.imm, r.a.rsel2, ex_ldbp2, ra_op2);
alu_op(r, ra_op1, ra_op2, v.m.icc, v.m.y(0), ex_ldbp2, v.e.op1, v.e.op2, v.e.aluop, v.e.alusel, v.e.aluadd, v.e.shcnt, v.e.sari, v.e.shleft, v.e.ymsb, v.e.mul, ra_div, v.e.mulstep, v.e.mac, v.e.ldbp2, v.e.invop2);
cin_gen(r, v.m.icc(0), v.e.alucin);
-----------------------------------------------------------------------
-- DECODE STAGE
-----------------------------------------------------------------------
de_inst := r.d.inst(conv_integer(r.d.set));
de_icc := r.m.icc;
v.a.cwp := r.d.cwp;
su_et_select(r, v.w.s.ps, v.w.s.s, v.w.s.et, v.a.su, v.a.et);
wicc_y_gen(de_inst, v.a.ctrl.wicc, v.a.ctrl.wy);
cwp_ctrl(r, v.w.s.wim, de_inst, de_cwp, v.a.wovf, v.a.wunf, de_wcwp);
rs1_gen(r, de_inst, v.a.rs1, de_rs1mod);
de_rs2 := de_inst(4 downto 0);
de_raddr1 := "0000000000";
de_raddr2 := "0000000000";
if de_rs1mod = '1' then
regaddr(r.d.cwp, de_inst(29 downto 26) & v.a.rs1(0), de_raddr1(7 downto 0));
else
regaddr(r.d.cwp, de_inst(18 downto 15) & v.a.rs1(0), de_raddr1(7 downto 0));
end if;
regaddr(r.d.cwp, de_rs2, de_raddr2(7 downto 0));
v.a.rfa1 := de_raddr1(7 downto 0);
v.a.rfa2 := de_raddr2(7 downto 0);
rd_gen(r, de_inst, v.a.ctrl.wreg, v.a.ctrl.ld, de_rd);
regaddr(de_cwp, de_rd, v.a.ctrl.rd);
fpbranch(de_inst, fpo.cc, de_fbranch);
fpbranch(de_inst, cpo.cc, de_cbranch);
v.a.imm := imm_data(r, de_inst);
lock_gen(r, de_rs2, de_rd, v.a.rfa1, v.a.rfa2, v.a.ctrl.rd, de_inst, fpo.ldlock, v.e.mul, ra_div, v.a.ldcheck1, v.a.ldcheck2, de_ldlock, v.a.ldchkra, v.a.ldchkex);
ic_ctrl(r, de_inst, v.x.annul_all, de_ldlock, branch_true(de_icc, de_inst), de_fbranch, de_cbranch, fpo.ccv, cpo.ccv, v.d.cnt, v.d.pc, de_branch, v.a.ctrl.annul, v.d.annul, v.a.jmpl, de_inull, v.d.pv, v.a.ctrl.pv, de_hold_pc, v.a.ticc, v.a.ctrl.rett, v.a.mulstart, v.a.divstart);
cwp_gen(r, v, v.a.ctrl.annul, de_wcwp, de_cwp, v.d.cwp);
v.d.inull := ra_inull_gen(r, v);
op_find(r, v.a.ldchkra, v.a.ldchkex, v.a.rs1, v.a.rfa1, false, v.a.rfe1, v.a.rsel1, v.a.ldcheck1);
op_find(r, v.a.ldchkra, v.a.ldchkex, de_rs2, v.a.rfa2, imm_select(de_inst), v.a.rfe2, v.a.rsel2, v.a.ldcheck2);
de_branch_address := branch_address(de_inst, r.d.pc);
v.a.ctrl.annul := v.a.ctrl.annul or v.x.annul_all;
v.a.ctrl.wicc := v.a.ctrl.wicc and not v.a.ctrl.annul;
v.a.ctrl.wreg := v.a.ctrl.wreg and not v.a.ctrl.annul;
v.a.ctrl.rett := v.a.ctrl.rett and not v.a.ctrl.annul;
v.a.ctrl.wy := v.a.ctrl.wy and not v.a.ctrl.annul;
v.a.ctrl.trap := r.d.mexc;
v.a.ctrl.tt := "000000";
v.a.ctrl.inst := de_inst;
v.a.ctrl.pc := r.d.pc;
v.a.ctrl.cnt := r.d.cnt;
v.a.step := r.d.step;
if holdn = '0' then
de_raddr1(7 downto 0) := r.a.rfa1;
de_raddr2(7 downto 0) := r.a.rfa2;
de_ren1 := r.a.rfe1;
de_ren2 := r.a.rfe2;
else
de_ren1 := v.a.rfe1;
de_ren2 := v.a.rfe2;
end if;
if ((dbgi.denable and not dbgi.dwrite) = '1') and (r.x.rstate = dsu2) then
de_raddr1(7 downto 0) := dbgi.daddr(9 downto 2);
de_ren1 := '1';
end if;
v.d.step := dbgi.step and not r.d.annul;
rfi.raddr1 <= de_raddr1;
rfi.raddr2 <= de_raddr2;
rfi.ren1 <= de_ren1 and not dco.scanen;
rfi.ren2 <= de_ren2 and not dco.scanen;
rfi.diag <= dco.testen & "000";
ici.inull <= de_inull;
ici.flush <= me_iflush;
if (xc_rstn = '0') then
v.d.cnt := "00";
end if;
-----------------------------------------------------------------------
-- FETCH STAGE
-----------------------------------------------------------------------
npc := r.f.pc;
if (xc_rstn = '0') then
v.f.pc := "000000000000000000000000000000";
v.f.branch := '0';
v.f.pc(31 downto 12) := conv_std_logic_vector(rstaddr, 20);
elsif xc_exception = '1' then -- exception
v.f.branch := '1';
v.f.pc := xc_trap_address;
npc := v.f.pc;
elsif de_hold_pc = '1' then
v.f.pc := r.f.pc;
v.f.branch := r.f.branch;
if ex_jump = '1' then
v.f.pc := ex_jump_address;
v.f.branch := '1';
npc := v.f.pc;
end if;
elsif ex_jump = '1' then
v.f.pc := ex_jump_address;
v.f.branch := '1';
npc := v.f.pc;
elsif de_branch = '1' then
v.f.pc := branch_address(de_inst, r.d.pc);
v.f.branch := '1';
npc := v.f.pc;
else
v.f.branch := '0';
v.f.pc(31 downto 2) := r.f.pc(31 downto 2) + 1;-- Address incrementer
npc := v.f.pc;
end if;
ici.dpc <= r.d.pc(31 downto 2) & "00";
ici.fpc <= r.f.pc(31 downto 2) & "00";
ici.rpc <= npc(31 downto 2) & "00";
ici.fbranch <= r.f.branch;
ici.rbranch <= v.f.branch;
ici.su <= v.a.su;
ici.fline <= "00000000000000000000000000000";
ici.flushl <= '0';
if (ico.mds and de_hold_pc) = '0' then
v.d.inst(0) := ico.data(0);-- latch instruction
v.d.inst(1) := ico.data(1);-- latch instruction
v.d.set := ico.set(0 downto 0);-- latch instruction
v.d.mexc := ico.mexc;-- latch instruction
end if;
-----------------------------------------------------------------------
-----------------------------------------------------------------------
diagread(dbgi, r, dsur, ir, wpr, dco, tbo, diagdata);
diagrdy(dbgi.denable, dsur, r.m.dci, dco.mds, ico, vdsu.crdy);
-----------------------------------------------------------------------
-- OUTPUTS
-----------------------------------------------------------------------
rin <= v;
wprin <= vwpr;
dsuin <= vdsu;
irin <= vir;
muli.start <= r.a.mulstart and not r.a.ctrl.annul;
muli.signed <= r.e.ctrl.inst(19);
muli.op1 <= (ex_op1(31) and r.e.ctrl.inst(19)) & ex_op1;
muli.op2 <= (mul_op2(31) and r.e.ctrl.inst(19)) & mul_op2;
muli.mac <= r.e.ctrl.inst(24);
muli.acc(39 downto 32) <= r.x.y(7 downto 0);
muli.acc(31 downto 0) <= r.w.s.asr18;
muli.flush <= r.x.annul_all;
divi.start <= r.a.divstart and not r.a.ctrl.annul;
divi.signed <= r.e.ctrl.inst(19);
divi.flush <= r.x.annul_all;
divi.op1 <= (ex_op1(31) and r.e.ctrl.inst(19)) & ex_op1;
divi.op2 <= (ex_op2(31) and r.e.ctrl.inst(19)) & ex_op2;
if (r.a.divstart and not r.a.ctrl.annul) = '1' then
dsign := r.a.ctrl.inst(19);
else
dsign := r.e.ctrl.inst(19);
end if;
divi.y <= (r.m.y(31) and dsign) & r.m.y;
rpin <= vp;
dbgo.dsu <= '1';
dbgo.dsumode <= r.x.debug;
dbgo.crdy <= dsur.crdy(2);
dbgo.data <= diagdata;
tbi <= tbufi;
dbgo.error <= dummy and not r.x.nerror;
-- pragma translate_off
if FPEN then
-- pragma translate_on
vfpi.flush := v.x.annul_all;
vfpi.exack := xc_fpexack;
vfpi.a_rs1 := r.a.rs1;
vfpi.d.inst := de_inst;
vfpi.d.cnt := r.d.cnt;
vfpi.d.annul := v.x.annul_all or r.d.annul;
vfpi.d.trap := r.d.mexc;
vfpi.d.pc(1 downto 0) := (others => '0');
vfpi.d.pc(31 downto 2) := r.d.pc(31 downto 2);
vfpi.d.pv := r.d.pv;
vfpi.a.pc(1 downto 0) := (others => '0');
vfpi.a.pc(31 downto 2) := r.a.ctrl.pc(31 downto 2);
vfpi.a.inst := r.a.ctrl.inst;
vfpi.a.cnt := r.a.ctrl.cnt;
vfpi.a.trap := r.a.ctrl.trap;
vfpi.a.annul := r.a.ctrl.annul;
vfpi.a.pv := r.a.ctrl.pv;
vfpi.e.pc(1 downto 0) := (others => '0');
vfpi.e.pc(31 downto 2) := r.e.ctrl.pc(31 downto 2);
vfpi.e.inst := r.e.ctrl.inst;
vfpi.e.cnt := r.e.ctrl.cnt;
vfpi.e.trap := r.e.ctrl.trap;
vfpi.e.annul := r.e.ctrl.annul;
vfpi.e.pv := r.e.ctrl.pv;
vfpi.m.pc(1 downto 0) := (others => '0');
vfpi.m.pc(31 downto 2) := r.m.ctrl.pc(31 downto 2);
vfpi.m.inst := r.m.ctrl.inst;
vfpi.m.cnt := r.m.ctrl.cnt;
vfpi.m.trap := r.m.ctrl.trap;
vfpi.m.annul := r.m.ctrl.annul;
vfpi.m.pv := r.m.ctrl.pv;
vfpi.x.pc(1 downto 0) := (others => '0');
vfpi.x.pc(31 downto 2) := r.x.ctrl.pc(31 downto 2);
vfpi.x.inst := r.x.ctrl.inst;
vfpi.x.cnt := r.x.ctrl.cnt;
vfpi.x.trap := xc_trap;
vfpi.x.annul := r.x.ctrl.annul;
vfpi.x.pv := r.x.ctrl.pv;
vfpi.lddata := xc_df_result;--xc_result;
if r.x.rstate = dsu2 then
vfpi.dbg.enable := dbgi.denable;
else
vfpi.dbg.enable := '0';
end if;
vfpi.dbg.write := fpcdbgwr;
vfpi.dbg.fsr := dbgi.daddr(22);-- IU reg access
vfpi.dbg.addr := dbgi.daddr(6 downto 2);
vfpi.dbg.data := dbgi.ddata;
fpi <= vfpi;
cpi <= vfpi;-- dummy, just to kill some warnings ...
-- pragma translate_off
end if;
-- pragma translate_on
-- Assignments to be moved with variables
-- These assignments must be moved to process COMB/
V_A_ET_shadow <= V.A.ET;
EX_ADD_RES32DOWNTO34DOWNTO3_shadow <= EX_ADD_RES ( 32 DOWNTO 3 )( 4 DOWNTO 3 );
ICNT_shadow <= ICNT;
EX_OP1_shadow <= EX_OP1;
V_M_CTRL_PC_shadow <= V.M.CTRL.PC;
V_E_CTRL_PC3DOWNTO2_shadow <= V.E.CTRL.PC( 3 DOWNTO 2 );
DE_REN1_shadow <= DE_REN1;
DE_INST_shadow <= DE_INST;
V_A_CTRL_CNT_shadow <= V.A.CTRL.CNT;
V_F_PC3DOWNTO2_shadow <= V.F.PC( 3 DOWNTO 2 );
V_W_S_TT_shadow <= V.W.S.TT;
V_X_RESULT6DOWNTO0_shadow <= V.X.RESULT ( 6 DOWNTO 0 );
EX_JUMP_ADDRESS3DOWNTO2_shadow <= EX_JUMP_ADDRESS( 3 DOWNTO 2 );
V_E_ALUCIN_shadow <= V.E.ALUCIN;
V_D_PC3DOWNTO2_shadow <= V.D.PC( 3 DOWNTO 2 );
V_A_CTRL_PV_shadow <= V.A.CTRL.PV;
V_E_CTRL_shadow <= V.E.CTRL;
V_M_CTRL_shadow <= V.M.CTRL;
V_M_RESULT1DOWNTO0_shadow <= V.M.RESULT ( 1 DOWNTO 0 );
EX_SHCNT_shadow <= EX_SHCNT;
V_M_DCI_SIZE_shadow <= V.M.DCI.SIZE;
V_X_CTRL_ANNUL_shadow <= V.X.CTRL.ANNUL;
V_X_MEXC_shadow <= V.X.MEXC;
TBUFCNTX_shadow <= TBUFCNTX;
V_A_CTRL_WY_shadow <= V.A.CTRL.WY;
NPC_shadow <= NPC;
V_M_CTRL_TT3DOWNTO0_shadow <= V.M.CTRL.TT( 3 DOWNTO 0 );
V_A_MULSTART_shadow <= V.A.MULSTART;
XC_VECTT3DOWNTO0_shadow <= XC_VECTT( 3 DOWNTO 0 );
V_E_CTRL_TT_shadow <= V.E.CTRL.TT;
DSIGN_shadow <= DSIGN;
V_E_CTRL_ANNUL_shadow <= V.E.CTRL.ANNUL;
EX_JUMP_ADDRESS_shadow <= EX_JUMP_ADDRESS;
V_A_CTRL_PC31DOWNTO12_shadow <= V.A.CTRL.PC( 31 DOWNTO 12 );
V_A_RFE1_shadow <= V.A.RFE1;
V_W_WA_shadow <= V.W.WA;
V_X_ANNUL_ALL_shadow <= V.X.ANNUL_ALL;
EX_YMSB_shadow <= EX_YMSB;
EX_ADD_RES_shadow <= EX_ADD_RES;
VIR_ADDR_shadow <= VIR.ADDR;
EX_JUMP_ADDRESS31DOWNTO12_shadow <= EX_JUMP_ADDRESS( 31 DOWNTO 12 );
V_W_S_CWP_shadow <= V.W.S.CWP;
V_D_INST0_shadow <= V.D.INST ( 0 );
V_A_CTRL_ANNUL_shadow <= V.A.CTRL.ANNUL;
V_X_DATA1_shadow <= V.X.DATA ( 1 );
VP_PWD_shadow <= VP.PWD;
V_M_CTRL_RD6DOWNTO0_shadow <= V.M.CTRL.RD( 6 DOWNTO 0 );
V_X_DATA00_shadow <= V.X.DATA ( 0 )( 0 );
V_M_CTRL_RETT_shadow <= V.M.CTRL.RETT;
V_X_CTRL_RETT_shadow <= V.X.CTRL.RETT;
V_X_CTRL_PC31DOWNTO12_shadow <= V.X.CTRL.PC( 31 DOWNTO 12 );
V_W_S_PS_shadow <= V.W.S.PS;
V_X_CTRL_TT_shadow <= V.X.CTRL.TT;
V_D_STEP_shadow <= V.D.STEP;
V_X_CTRL_WICC_shadow <= V.X.CTRL.WICC;
VIR_ADDR31DOWNTO2_shadow <= VIR.ADDR( 31 DOWNTO 2 );
V_M_CTRL_RD7DOWNTO0_shadow <= V.M.CTRL.RD ( 7 DOWNTO 0 );
V_X_RESULT_shadow <= V.X.RESULT;
V_D_CNT_shadow <= V.D.CNT;
XC_VECTT_shadow <= XC_VECTT;
EX_ADD_RES32DOWNTO3_shadow <= EX_ADD_RES ( 32 DOWNTO 3 );
V_W_S_EF_shadow <= V.W.S.EF;
V_A_CTRL_PC31DOWNTO2_shadow <= V.A.CTRL.PC( 31 DOWNTO 2 );
V_X_DATA04DOWNTO0_shadow <= V.X.DATA ( 0 )( 4 DOWNTO 0 );
V_X_DCI_SIGNED_shadow <= V.X.DCI.SIGNED;
V_M_NALIGN_shadow <= V.M.NALIGN;
XC_WREG_shadow <= XC_WREG;
V_A_RFA2_shadow <= V.A.RFA2;
V_E_CTRL_PC31DOWNTO12_shadow <= V.E.CTRL.PC( 31 DOWNTO 12 );
EX_ADD_RES32DOWNTO332DOWNTO13_shadow <= EX_ADD_RES ( 32 DOWNTO 3 )( 32 DOWNTO 13 );
EX_OP231_shadow <= EX_OP2( 31 );
XC_TRAP_ADDRESS31DOWNTO4_shadow <= XC_TRAP_ADDRESS( 31 DOWNTO 4 );
V_X_ICC_shadow <= V.X.ICC;
V_A_SU_shadow <= V.A.SU;
V_E_OP2_shadow <= V.E.OP2;
EX_FORCE_A2_shadow <= EX_FORCE_A2;
V_E_CTRL_PC31DOWNTO2_shadow <= V.E.CTRL.PC( 31 DOWNTO 2 );
V_E_CTRL_PC31DOWNTO4_shadow <= V.E.CTRL.PC( 31 DOWNTO 4 );
V_E_OP131_shadow <= V.E.OP1( 31 );
V_X_DCI_shadow <= V.X.DCI;
V_E_CTRL_WICC_shadow <= V.E.CTRL.WICC;
EX_OP13_shadow <= EX_OP1( 3 );
V_F_PC31DOWNTO12_shadow <= V.F.PC( 31 DOWNTO 12 );
V_E_CTRL_INST_shadow <= V.E.CTRL.INST;
V_E_CTRL_LD_shadow <= V.E.CTRL.LD;
V_M_SU_shadow <= V.M.SU;
V_E_SARI_shadow <= V.E.SARI;
V_E_ET_shadow <= V.E.ET;
V_M_CTRL_PV_shadow <= V.M.CTRL.PV;
VDSU_CRDY2_shadow <= VDSU.CRDY ( 2 );
MUL_OP2_shadow <= MUL_OP2;
XC_EXCEPTION_shadow <= XC_EXCEPTION;
V_E_OP1_shadow <= V.E.OP1;
VP_ERROR_shadow <= VP.ERROR;
V_M_DCI_SIGNED_shadow <= V.M.DCI.SIGNED;
V_D_PC31DOWNTO12_shadow <= V.D.PC( 31 DOWNTO 12 );
MUL_OP231_shadow <= MUL_OP2 ( 31 );
XC_TRAP_ADDRESS31DOWNTO2_shadow <= XC_TRAP_ADDRESS( 31 DOWNTO 2 );
V_M_CTRL_PC3DOWNTO2_shadow <= V.M.CTRL.PC( 3 DOWNTO 2 );
V_M_DCI_shadow <= V.M.DCI;
EX_OP23_shadow <= EX_OP2( 3 );
V_X_CTRL_RD6DOWNTO0_shadow <= V.X.CTRL.RD( 6 DOWNTO 0 );
V_X_CTRL_TRAP_shadow <= V.X.CTRL.TRAP;
V_A_DIVSTART_shadow <= V.A.DIVSTART;
V_X_RESULT6DOWNTO03DOWNTO0_shadow <= V.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 );
VDSU_TT_shadow <= VDSU.TT;
EX_ADD_RES32DOWNTO332DOWNTO5_shadow <= EX_ADD_RES ( 32 DOWNTO 3 )( 32 DOWNTO 5 );
V_X_CTRL_CNT_shadow <= V.X.CTRL.CNT;
V_E_YMSB_shadow <= V.E.YMSB;
EX_ADD_RES32DOWNTO330DOWNTO11_shadow <= EX_ADD_RES ( 32 DOWNTO 3 )( 30 DOWNTO 11 );
V_A_RFE2_shadow <= V.A.RFE2;
V_E_OP13_shadow <= V.E.OP1( 3 );
V_A_CWP_shadow <= V.A.CWP;
ME_SIZE_shadow <= ME_SIZE;
V_X_MAC_shadow <= V.X.MAC;
V_M_CTRL_INST_shadow <= V.M.CTRL.INST;
VIR_ADDR31DOWNTO4_shadow <= VIR.ADDR( 31 DOWNTO 4 );
V_A_CTRL_INST20_shadow <= V.A.CTRL.INST( 20 );
DE_REN2_shadow <= DE_REN2;
V_E_CTRL_PV_shadow <= V.E.CTRL.PV;
V_E_MAC_shadow <= V.E.MAC;
V_X_CTRL_TT3DOWNTO0_shadow <= V.X.CTRL.TT( 3 DOWNTO 0 );
EX_ADD_RES3_shadow <= EX_ADD_RES ( 3 );
V_X_CTRL_INST_shadow <= V.X.CTRL.INST;
V_M_CTRL_PC31DOWNTO2_shadow <= V.M.CTRL.PC( 31 DOWNTO 2 );
V_W_S_ET_shadow <= V.W.S.ET;
V_M_CTRL_CNT_shadow <= V.M.CTRL.CNT;
V_M_CTRL_ANNUL_shadow <= V.M.CTRL.ANNUL;
DE_INST19_shadow <= DE_INST( 19 );
XC_HALT_shadow <= XC_HALT;
V_E_OP231_shadow <= V.E.OP2( 31 );
V_A_CTRL_PC3DOWNTO2_shadow <= V.A.CTRL.PC( 3 DOWNTO 2 );
VIR_ADDR31DOWNTO12_shadow <= VIR.ADDR( 31 DOWNTO 12 );
V_M_CTRL_WICC_shadow <= V.M.CTRL.WICC;
V_M_CTRL_WREG_shadow <= V.M.CTRL.WREG;
V_W_S_S_shadow <= V.W.S.S;
V_F_PC31DOWNTO2_shadow <= V.F.PC( 31 DOWNTO 2 );
V_E_CWP_shadow <= V.E.CWP;
V_A_STEP_shadow <= V.A.STEP;
V_A_CTRL_TT3DOWNTO0_shadow <= V.A.CTRL.TT( 3 DOWNTO 0 );
V_A_CTRL_TRAP_shadow <= V.A.CTRL.TRAP;
NPC31DOWNTO2_shadow <= NPC ( 31 DOWNTO 2 );
V_M_CTRL_TRAP_shadow <= V.M.CTRL.TRAP;
V_D_PC31DOWNTO4_shadow <= V.D.PC( 31 DOWNTO 4 );
V_X_INTACK_shadow <= V.X.INTACK;
SIDLE_shadow <= SIDLE;
V_A_CTRL_RETT_shadow <= V.A.CTRL.RETT;
V_X_DATA03_shadow <= V.X.DATA ( 0 )( 3 );
V_A_CTRL_INST19_shadow <= V.A.CTRL.INST( 19 );
V_W_S_SVT_shadow <= V.W.S.SVT;
V_A_CTRL_PC31DOWNTO4_shadow <= V.A.CTRL.PC( 31 DOWNTO 4 );
V_X_LADDR_shadow <= V.X.LADDR;
V_W_S_DWT_shadow <= V.W.S.DWT;
EX_JUMP_ADDRESS31DOWNTO2_shadow <= EX_JUMP_ADDRESS( 31 DOWNTO 2 );
V_W_S_TBA_shadow <= V.W.S.TBA;
XC_WADDR6DOWNTO0_shadow <= XC_WADDR ( 6 DOWNTO 0 );
V_M_MUL_shadow <= V.M.MUL;
V_E_SU_shadow <= V.E.SU;
V_M_Y31_shadow <= V.M.Y ( 31 );
V_E_OP23_shadow <= V.E.OP2( 3 );
V_M_CTRL_PC31DOWNTO4_shadow <= V.M.CTRL.PC( 31 DOWNTO 4 );
DE_RADDR17DOWNTO0_shadow <= DE_RADDR1 ( 7 DOWNTO 0 );
V_X_CTRL_PC31DOWNTO2_shadow <= V.X.CTRL.PC( 31 DOWNTO 2 );
V_E_CTRL_TRAP_shadow <= V.E.CTRL.TRAP;
V_X_DEBUG_shadow <= V.X.DEBUG;
V_M_DCI_LOCK_shadow <= V.M.DCI.LOCK;
V_X_CTRL_PC3DOWNTO2_shadow <= V.X.CTRL.PC( 3 DOWNTO 2 );
V_X_CTRL_WREG_shadow <= V.X.CTRL.WREG;
V_E_CTRL_INST24_shadow <= V.E.CTRL.INST( 24 );
V_D_MEXC_shadow <= V.D.MEXC;
V_W_RESULT_shadow <= V.W.RESULT;
VFPI_DBG_ENABLE_shadow <= VFPI.DBG.ENABLE;
EX_OP131_shadow <= EX_OP1 ( 31 );
V_D_INST1_shadow <= V.D.INST ( 1 );
V_W_EXCEPT_shadow <= V.W.EXCEPT;
V_E_CTRL_TT3DOWNTO0_shadow <= V.E.CTRL.TT( 3 DOWNTO 0 );
ME_LADDR_shadow <= ME_LADDR;
V_X_CTRL_PC31DOWNTO4_shadow <= V.X.CTRL.PC( 31 DOWNTO 4 );
V_E_CTRL_RETT_shadow <= V.E.CTRL.RETT;
XC_WADDR7DOWNTO0_shadow <= XC_WADDR ( 7 DOWNTO 0 );
V_X_CTRL_PV_shadow <= V.X.CTRL.PV;
V_E_CTRL_RD6DOWNTO0_shadow <= V.E.CTRL.RD( 6 DOWNTO 0 );
V_M_MAC_shadow <= V.M.MAC;
V_D_SET_shadow <= V.D.SET;
VIR_ADDR3DOWNTO2_shadow <= VIR.ADDR( 3 DOWNTO 2 );
V_D_CWP_shadow <= V.D.CWP;
DE_INST20_shadow <= DE_INST( 20 );
V_D_ANNUL_shadow <= V.D.ANNUL;
EX_OP2_shadow <= EX_OP2;
EX_SARI_shadow <= EX_SARI;
V_D_PC31DOWNTO2_shadow <= V.D.PC( 31 DOWNTO 2 );
V_X_DCI_SIZE_shadow <= V.X.DCI.SIZE;
V_M_Y_shadow <= V.M.Y;
V_X_CTRL_PC_shadow <= V.X.CTRL.PC;
V_X_SET_shadow <= V.X.SET;
V_A_CTRL_PC_shadow <= V.A.CTRL.PC;
V_A_JMPL_shadow <= V.A.JMPL;
V_E_CTRL_PC_shadow <= V.E.CTRL.PC;
V_E_CTRL_INST20_shadow <= V.E.CTRL.INST( 20 );
V_E_CTRL_WREG_shadow <= V.E.CTRL.WREG;
V_A_CTRL_WREG_shadow <= V.A.CTRL.WREG;
V_A_CTRL_shadow <= V.A.CTRL;
V_A_CTRL_RD6DOWNTO0_shadow <= V.A.CTRL.RD( 6 DOWNTO 0 );
V_X_DATA0_shadow <= V.X.DATA ( 0 );
V_E_CTRL_INST19_shadow <= V.E.CTRL.INST( 19 );
ME_SIGNED_shadow <= ME_SIGNED;
V_W_WREG_shadow <= V.W.WREG;
V_D_PC_shadow <= V.D.PC;
VFPI_D_ANNUL_shadow <= VFPI.D.ANNUL;
DE_RADDR27DOWNTO0_shadow <= DE_RADDR2 ( 7 DOWNTO 0 );
V_E_CTRL_CNT_shadow <= V.E.CTRL.CNT;
V_F_PC_shadow <= V.F.PC;
V_X_DATA031_shadow <= V.X.DATA ( 0 )( 31 );
V_M_CTRL_PC31DOWNTO12_shadow <= V.M.CTRL.PC( 31 DOWNTO 12 );
V_X_CTRL_RD7DOWNTO0_shadow <= V.X.CTRL.RD ( 7 DOWNTO 0 );
V_M_CTRL_TT_shadow <= V.M.CTRL.TT;
V_X_CTRL_shadow <= V.X.CTRL;
V_A_CTRL_INST24_shadow <= V.A.CTRL.INST( 24 );
XC_TRAP_ADDRESS3DOWNTO2_shadow <= XC_TRAP_ADDRESS( 3 DOWNTO 2 );
V_X_NERROR_shadow <= V.X.NERROR;
V_F_PC31DOWNTO4_shadow <= V.F.PC( 31 DOWNTO 4 );
V_W_S_TT3DOWNTO0_shadow <= V.W.S.TT( 3 DOWNTO 0 );
EX_JUMP_ADDRESS31DOWNTO4_shadow <= EX_JUMP_ADDRESS( 31 DOWNTO 4 );
EX_ADD_RES32DOWNTO332DOWNTO3_shadow <= EX_ADD_RES ( 32 DOWNTO 3 )( 32 DOWNTO 3 );
V_F_BRANCH_shadow <= V.F.BRANCH;
V_A_CTRL_WICC_shadow <= V.A.CTRL.WICC;
V_A_CTRL_LD_shadow <= V.A.CTRL.LD;
V_A_CTRL_TT_shadow <= V.A.CTRL.TT;
V_M_CTRL_LD_shadow <= V.M.CTRL.LD;
V_E_SHCNT_shadow <= V.E.SHCNT;
XC_TRAP_ADDRESS31DOWNTO12_shadow <= XC_TRAP_ADDRESS( 31 DOWNTO 12 );
V_A_CTRL_INST_shadow <= V.A.CTRL.INST;
V_A_CTRL_RD7DOWNTO0_shadow <= V.A.CTRL.RD ( 7 DOWNTO 0 );
VIR_PWD_shadow <= VIR.PWD;
XC_RESULT_shadow <= XC_RESULT;
V_A_RFA1_shadow <= V.A.RFA1;
V_E_JMPL_shadow <= V.E.JMPL;
V_E_CTRL_RD7DOWNTO0_shadow <= V.E.CTRL.RD ( 7 DOWNTO 0 );
ME_ICC_shadow <= ME_ICC;
DE_INST24_shadow <= DE_INST( 24 );
XC_TRAP_shadow <= XC_TRAP;
VDSU_TBUFCNT_shadow <= VDSU.TBUFCNT;
XC_TRAP_ADDRESS_shadow <= XC_TRAP_ADDRESS;
end process;
dfp_delay : process(clk) begin
if(clk'event and clk = '1')then
RPIN_ERROR_intermed_1 <= RPIN.ERROR;
VP_ERROR_shadow_intermed_1 <= VP_ERROR_shadow;
V_W_S_S_shadow_intermed_1 <= V_W_S_S_shadow;
RIN_W_S_S_intermed_1 <= RIN.W.S.S;
V_W_S_S_shadow_intermed_1 <= V_W_S_S_shadow;
V_W_S_S_shadow_intermed_2 <= V_W_S_S_shadow_intermed_1;
V_W_S_PS_shadow_intermed_1 <= V_W_S_PS_shadow;
RIN_W_S_PS_intermed_1 <= RIN.W.S.PS;
R_W_S_S_intermed_1 <= R.W.S.S;
RIN_W_S_S_intermed_1 <= RIN.W.S.S;
RIN_W_S_S_intermed_2 <= RIN_W_S_S_intermed_1;
R_X_RESULT6DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 );
R_X_RESULT6DOWNTO0_intermed_2 <= R_X_RESULT6DOWNTO0_intermed_1;
V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow;
V_X_RESULT6DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO0_shadow_intermed_1;
V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow;
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 );
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 );
RIN_X_RESULT6DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO0_intermed_1;
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
V_X_DATA0_shadow_intermed_2 <= V_X_DATA0_shadow_intermed_1;
R_X_DATA0_intermed_1 <= R.X.DATA( 0 );
R_X_DATA0_intermed_2 <= R_X_DATA0_intermed_1;
DCO_DATA0_intermed_1 <= DCO.DATA ( 0 );
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA ( 0 );
RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 );
RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC ( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
R_X_CTRL_PC31DOWNTO2_intermed_2 <= R_X_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC ( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
V_D_PC31DOWNTO2_shadow_intermed_6 <= V_D_PC31DOWNTO2_shadow_intermed_5;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_D_PC31DOWNTO2_intermed_6 <= RIN_D_PC31DOWNTO2_intermed_5;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC ( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC ( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC ( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_D_PC31DOWNTO2_intermed_5 <= R_D_PC31DOWNTO2_intermed_4;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC ( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
V_X_ANNUL_ALL_shadow_intermed_2 <= V_X_ANNUL_ALL_shadow_intermed_1;
V_X_ANNUL_ALL_shadow_intermed_3 <= V_X_ANNUL_ALL_shadow_intermed_2;
V_X_ANNUL_ALL_shadow_intermed_4 <= V_X_ANNUL_ALL_shadow_intermed_3;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2;
RIN_A_CTRL_ANNUL_intermed_4 <= RIN_A_CTRL_ANNUL_intermed_3;
RIN_A_CTRL_ANNUL_intermed_5 <= RIN_A_CTRL_ANNUL_intermed_4;
R_M_CTRL_WREG_intermed_1 <= R.M.CTRL.WREG;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1;
R_A_CTRL_ANNUL_intermed_3 <= R_A_CTRL_ANNUL_intermed_2;
R_A_CTRL_ANNUL_intermed_4 <= R_A_CTRL_ANNUL_intermed_3;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
RIN_X_ANNUL_ALL_intermed_3 <= RIN_X_ANNUL_ALL_intermed_2;
RIN_X_ANNUL_ALL_intermed_4 <= RIN_X_ANNUL_ALL_intermed_3;
RIN_X_ANNUL_ALL_intermed_5 <= RIN_X_ANNUL_ALL_intermed_4;
V_M_CTRL_WREG_shadow_intermed_1 <= V_M_CTRL_WREG_shadow;
V_M_CTRL_WREG_shadow_intermed_2 <= V_M_CTRL_WREG_shadow_intermed_1;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
R_X_ANNUL_ALL_intermed_2 <= R_X_ANNUL_ALL_intermed_1;
R_X_ANNUL_ALL_intermed_3 <= R_X_ANNUL_ALL_intermed_2;
R_X_ANNUL_ALL_intermed_4 <= R_X_ANNUL_ALL_intermed_3;
V_X_CTRL_WREG_shadow_intermed_1 <= V_X_CTRL_WREG_shadow;
R_E_CTRL_WREG_intermed_1 <= R.E.CTRL.WREG;
R_E_CTRL_WREG_intermed_2 <= R_E_CTRL_WREG_intermed_1;
RIN_X_CTRL_WREG_intermed_1 <= RIN.X.CTRL.WREG;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_3 <= V_A_CTRL_ANNUL_shadow_intermed_2;
V_A_CTRL_ANNUL_shadow_intermed_4 <= V_A_CTRL_ANNUL_shadow_intermed_3;
RIN_E_CTRL_WREG_intermed_1 <= RIN.E.CTRL.WREG;
RIN_E_CTRL_WREG_intermed_2 <= RIN_E_CTRL_WREG_intermed_1;
RIN_E_CTRL_WREG_intermed_3 <= RIN_E_CTRL_WREG_intermed_2;
RIN_M_CTRL_WREG_intermed_1 <= RIN.M.CTRL.WREG;
RIN_M_CTRL_WREG_intermed_2 <= RIN_M_CTRL_WREG_intermed_1;
V_E_CTRL_WREG_shadow_intermed_1 <= V_E_CTRL_WREG_shadow;
V_E_CTRL_WREG_shadow_intermed_2 <= V_E_CTRL_WREG_shadow_intermed_1;
V_E_CTRL_WREG_shadow_intermed_3 <= V_E_CTRL_WREG_shadow_intermed_2;
RIN_A_CTRL_WREG_intermed_1 <= RIN.A.CTRL.WREG;
RIN_A_CTRL_WREG_intermed_2 <= RIN_A_CTRL_WREG_intermed_1;
RIN_A_CTRL_WREG_intermed_3 <= RIN_A_CTRL_WREG_intermed_2;
RIN_A_CTRL_WREG_intermed_4 <= RIN_A_CTRL_WREG_intermed_3;
V_A_CTRL_WREG_shadow_intermed_1 <= V_A_CTRL_WREG_shadow;
V_A_CTRL_WREG_shadow_intermed_2 <= V_A_CTRL_WREG_shadow_intermed_1;
V_A_CTRL_WREG_shadow_intermed_3 <= V_A_CTRL_WREG_shadow_intermed_2;
V_A_CTRL_WREG_shadow_intermed_4 <= V_A_CTRL_WREG_shadow_intermed_3;
R_A_CTRL_WREG_intermed_1 <= R.A.CTRL.WREG;
R_A_CTRL_WREG_intermed_2 <= R_A_CTRL_WREG_intermed_1;
R_A_CTRL_WREG_intermed_3 <= R_A_CTRL_WREG_intermed_2;
RIN_X_INTACK_intermed_1 <= RIN.X.INTACK;
V_X_INTACK_shadow_intermed_1 <= V_X_INTACK_shadow;
V_X_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_X_CTRL_TT3DOWNTO0_shadow;
V_X_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_X_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_X_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_X_CTRL_TT3DOWNTO0_shadow_intermed_2;
R_M_CTRL_TT3DOWNTO0_intermed_1 <= R.M.CTRL.TT( 3 DOWNTO 0 );
R_M_CTRL_TT3DOWNTO0_intermed_2 <= R_M_CTRL_TT3DOWNTO0_intermed_1;
R_M_CTRL_TT3DOWNTO0_intermed_3 <= R_M_CTRL_TT3DOWNTO0_intermed_2;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_M_CTRL_TT3DOWNTO0_shadow;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_M_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_M_CTRL_TT3DOWNTO0_shadow_intermed_2;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_4 <= V_M_CTRL_TT3DOWNTO0_shadow_intermed_3;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_3 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_4 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_3;
R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
R_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= R_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
R_X_RESULT6DOWNTO03DOWNTO0_intermed_3 <= R_X_RESULT6DOWNTO03DOWNTO0_intermed_2;
R_A_CTRL_TT3DOWNTO0_intermed_1 <= R.A.CTRL.TT( 3 DOWNTO 0 );
R_A_CTRL_TT3DOWNTO0_intermed_2 <= R_A_CTRL_TT3DOWNTO0_intermed_1;
R_A_CTRL_TT3DOWNTO0_intermed_3 <= R_A_CTRL_TT3DOWNTO0_intermed_2;
R_A_CTRL_TT3DOWNTO0_intermed_4 <= R_A_CTRL_TT3DOWNTO0_intermed_3;
R_A_CTRL_TT3DOWNTO0_intermed_5 <= R_A_CTRL_TT3DOWNTO0_intermed_4;
RIN_A_CTRL_TT3DOWNTO0_intermed_1 <= RIN.A.CTRL.TT( 3 DOWNTO 0 );
RIN_A_CTRL_TT3DOWNTO0_intermed_2 <= RIN_A_CTRL_TT3DOWNTO0_intermed_1;
RIN_A_CTRL_TT3DOWNTO0_intermed_3 <= RIN_A_CTRL_TT3DOWNTO0_intermed_2;
RIN_A_CTRL_TT3DOWNTO0_intermed_4 <= RIN_A_CTRL_TT3DOWNTO0_intermed_3;
RIN_A_CTRL_TT3DOWNTO0_intermed_5 <= RIN_A_CTRL_TT3DOWNTO0_intermed_4;
RIN_A_CTRL_TT3DOWNTO0_intermed_6 <= RIN_A_CTRL_TT3DOWNTO0_intermed_5;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_3 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_4 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_3;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_A_CTRL_TT3DOWNTO0_shadow;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_2;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_4 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_3;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_5 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_4;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_6 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_5;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_3 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2;
R_W_S_TT3DOWNTO0_intermed_1 <= R.W.S.TT( 3 DOWNTO 0 );
R_W_S_TT3DOWNTO0_intermed_2 <= R_W_S_TT3DOWNTO0_intermed_1;
R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 );
R_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= R_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
R_E_CTRL_TT3DOWNTO0_intermed_1 <= R.E.CTRL.TT( 3 DOWNTO 0 );
R_E_CTRL_TT3DOWNTO0_intermed_2 <= R_E_CTRL_TT3DOWNTO0_intermed_1;
R_E_CTRL_TT3DOWNTO0_intermed_3 <= R_E_CTRL_TT3DOWNTO0_intermed_2;
R_E_CTRL_TT3DOWNTO0_intermed_4 <= R_E_CTRL_TT3DOWNTO0_intermed_3;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_3 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2;
RIN_W_S_TT3DOWNTO0_intermed_1 <= RIN.W.S.TT( 3 DOWNTO 0 );
RIN_W_S_TT3DOWNTO0_intermed_2 <= RIN_W_S_TT3DOWNTO0_intermed_1;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_E_CTRL_TT3DOWNTO0_shadow;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_2;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_4 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_3;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_5 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_4;
RIN_W_S_TT3DOWNTO0_intermed_1 <= RIN.W.S.TT ( 3 DOWNTO 0 );
RIN_M_CTRL_TT3DOWNTO0_intermed_1 <= RIN.M.CTRL.TT( 3 DOWNTO 0 );
RIN_M_CTRL_TT3DOWNTO0_intermed_2 <= RIN_M_CTRL_TT3DOWNTO0_intermed_1;
RIN_M_CTRL_TT3DOWNTO0_intermed_3 <= RIN_M_CTRL_TT3DOWNTO0_intermed_2;
RIN_M_CTRL_TT3DOWNTO0_intermed_4 <= RIN_M_CTRL_TT3DOWNTO0_intermed_3;
RIN_X_CTRL_TT3DOWNTO0_intermed_1 <= RIN.X.CTRL.TT( 3 DOWNTO 0 );
RIN_X_CTRL_TT3DOWNTO0_intermed_2 <= RIN_X_CTRL_TT3DOWNTO0_intermed_1;
RIN_X_CTRL_TT3DOWNTO0_intermed_3 <= RIN_X_CTRL_TT3DOWNTO0_intermed_2;
V_W_S_TT3DOWNTO0_shadow_intermed_1 <= V_W_S_TT3DOWNTO0_shadow;
V_W_S_TT3DOWNTO0_shadow_intermed_2 <= V_W_S_TT3DOWNTO0_shadow_intermed_1;
R_X_CTRL_TT3DOWNTO0_intermed_1 <= R.X.CTRL.TT( 3 DOWNTO 0 );
R_X_CTRL_TT3DOWNTO0_intermed_2 <= R_X_CTRL_TT3DOWNTO0_intermed_1;
RIN_E_CTRL_TT3DOWNTO0_intermed_1 <= RIN.E.CTRL.TT( 3 DOWNTO 0 );
RIN_E_CTRL_TT3DOWNTO0_intermed_2 <= RIN_E_CTRL_TT3DOWNTO0_intermed_1;
RIN_E_CTRL_TT3DOWNTO0_intermed_3 <= RIN_E_CTRL_TT3DOWNTO0_intermed_2;
RIN_E_CTRL_TT3DOWNTO0_intermed_4 <= RIN_E_CTRL_TT3DOWNTO0_intermed_3;
RIN_E_CTRL_TT3DOWNTO0_intermed_5 <= RIN_E_CTRL_TT3DOWNTO0_intermed_4;
V_W_S_TT3DOWNTO0_shadow_intermed_1 <= V_W_S_TT3DOWNTO0_shadow;
XC_VECTT3DOWNTO0_shadow_intermed_1 <= XC_VECTT3DOWNTO0_shadow;
XC_VECTT3DOWNTO0_shadow_intermed_2 <= XC_VECTT3DOWNTO0_shadow_intermed_1;
RIN_X_INTACK_intermed_1 <= RIN.X.INTACK;
V_X_INTACK_shadow_intermed_1 <= V_X_INTACK_shadow;
V_M_RESULT1DOWNTO0_shadow_intermed_1 <= V_M_RESULT1DOWNTO0_shadow;
V_M_RESULT1DOWNTO0_shadow_intermed_2 <= V_M_RESULT1DOWNTO0_shadow_intermed_1;
RIN_M_RESULT1DOWNTO0_intermed_1 <= RIN.M.RESULT ( 1 DOWNTO 0 );
RIN_M_RESULT1DOWNTO0_intermed_1 <= RIN.M.RESULT( 1 DOWNTO 0 );
RIN_M_RESULT1DOWNTO0_intermed_2 <= RIN_M_RESULT1DOWNTO0_intermed_1;
V_M_RESULT1DOWNTO0_shadow_intermed_1 <= V_M_RESULT1DOWNTO0_shadow;
R_M_RESULT1DOWNTO0_intermed_1 <= R.M.RESULT( 1 DOWNTO 0 );
R_M_RESULT1DOWNTO0_intermed_2 <= R_M_RESULT1DOWNTO0_intermed_1;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2;
RIN_E_CTRL_ANNUL_intermed_1 <= RIN.E.CTRL.ANNUL;
RIN_E_CTRL_ANNUL_intermed_2 <= RIN_E_CTRL_ANNUL_intermed_1;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1;
V_M_CTRL_ANNUL_shadow_intermed_1 <= V_M_CTRL_ANNUL_shadow;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
RIN_M_DCI_LOCK_intermed_1 <= RIN.M.DCI.LOCK;
V_E_CTRL_ANNUL_shadow_intermed_1 <= V_E_CTRL_ANNUL_shadow;
V_E_CTRL_ANNUL_shadow_intermed_2 <= V_E_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_3 <= V_A_CTRL_ANNUL_shadow_intermed_2;
RIN_M_CTRL_ANNUL_intermed_1 <= RIN.M.CTRL.ANNUL;
R_E_CTRL_ANNUL_intermed_1 <= R.E.CTRL.ANNUL;
V_M_DCI_LOCK_shadow_intermed_1 <= V_M_DCI_LOCK_shadow;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 ) ( 31 );
DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 );
DCO_DATA031_intermed_2 <= DCO_DATA031_intermed_1;
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
R_X_DATA031_intermed_2 <= R_X_DATA031_intermed_1;
R_X_DATA031_intermed_1 <= R.X.DATA ( 0 )( 31 );
R_X_DATA031_intermed_2 <= R_X_DATA031_intermed_1;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
DE_INST19_shadow_intermed_2 <= DE_INST19_shadow_intermed_1;
DE_INST19_shadow_intermed_3 <= DE_INST19_shadow_intermed_2;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_A_CTRL_INST19_shadow_intermed_3 <= V_A_CTRL_INST19_shadow_intermed_2;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_CTRL_INST19_shadow_intermed_2 <= V_E_CTRL_INST19_shadow_intermed_1;
R_E_CTRL_INST19_intermed_1 <= R.E.CTRL.INST( 19 );
R_E_CTRL_INST19_intermed_2 <= R_E_CTRL_INST19_intermed_1;
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
R_A_CTRL_INST19_intermed_2 <= R_A_CTRL_INST19_intermed_1;
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
RIN_A_CTRL_INST19_intermed_3 <= RIN_A_CTRL_INST19_intermed_2;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST ( 19 );
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST( 19 );
RIN_E_CTRL_INST19_intermed_2 <= RIN_E_CTRL_INST19_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
V_A_CTRL_INST20_shadow_intermed_2 <= V_A_CTRL_INST20_shadow_intermed_1;
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST ( 20 );
RIN_A_CTRL_INST20_intermed_2 <= RIN_A_CTRL_INST20_intermed_1;
RIN_E_CTRL_INST20_intermed_1 <= RIN.E.CTRL.INST ( 20 );
R_A_CTRL_INST20_intermed_1 <= R.A.CTRL.INST ( 20 );
R_E_CTRL_INST20_intermed_1 <= R.E.CTRL.INST( 20 );
R_E_CTRL_INST20_intermed_2 <= R_E_CTRL_INST20_intermed_1;
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST( 20 );
RIN_A_CTRL_INST20_intermed_2 <= RIN_A_CTRL_INST20_intermed_1;
RIN_A_CTRL_INST20_intermed_3 <= RIN_A_CTRL_INST20_intermed_2;
V_E_CTRL_INST20_shadow_intermed_1 <= V_E_CTRL_INST20_shadow;
V_E_CTRL_INST20_shadow_intermed_2 <= V_E_CTRL_INST20_shadow_intermed_1;
V_E_CTRL_INST20_shadow_intermed_1 <= V_E_CTRL_INST20_shadow;
DE_INST20_shadow_intermed_1 <= DE_INST20_shadow;
DE_INST20_shadow_intermed_2 <= DE_INST20_shadow_intermed_1;
DE_INST20_shadow_intermed_3 <= DE_INST20_shadow_intermed_2;
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
V_A_CTRL_INST20_shadow_intermed_2 <= V_A_CTRL_INST20_shadow_intermed_1;
V_A_CTRL_INST20_shadow_intermed_3 <= V_A_CTRL_INST20_shadow_intermed_2;
RIN_E_CTRL_INST20_intermed_1 <= RIN.E.CTRL.INST( 20 );
RIN_E_CTRL_INST20_intermed_2 <= RIN_E_CTRL_INST20_intermed_1;
R_A_CTRL_INST20_intermed_1 <= R.A.CTRL.INST( 20 );
R_A_CTRL_INST20_intermed_2 <= R_A_CTRL_INST20_intermed_1;
RIN_X_DATA00_intermed_1 <= RIN.X.DATA ( 0 )( 0 );
RIN_X_DATA00_intermed_2 <= RIN_X_DATA00_intermed_1;
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
DCO_DATA00_intermed_1 <= DCO.DATA ( 0 )( 0 );
DCO_DATA00_intermed_2 <= DCO_DATA00_intermed_1;
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
V_X_DATA00_shadow_intermed_2 <= V_X_DATA00_shadow_intermed_1;
RIN_X_DATA00_intermed_1 <= RIN.X.DATA ( 0 ) ( 0 );
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
V_X_DATA00_shadow_intermed_2 <= V_X_DATA00_shadow_intermed_1;
R_X_DATA00_intermed_1 <= R.X.DATA ( 0 )( 0 );
R_X_DATA00_intermed_2 <= R_X_DATA00_intermed_1;
RIN_X_DATA00_intermed_1 <= RIN.X.DATA( 0 )( 0 );
RIN_X_DATA00_intermed_2 <= RIN_X_DATA00_intermed_1;
R_X_DATA00_intermed_1 <= R.X.DATA( 0 )( 0 );
R_X_DATA00_intermed_2 <= R_X_DATA00_intermed_1;
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA ( 0 ) ( 4 DOWNTO 0 );
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
V_X_DATA04DOWNTO0_shadow_intermed_2 <= V_X_DATA04DOWNTO0_shadow_intermed_1;
R_X_DATA04DOWNTO0_intermed_1 <= R.X.DATA( 0 )( 4 DOWNTO 0 );
R_X_DATA04DOWNTO0_intermed_2 <= R_X_DATA04DOWNTO0_intermed_1;
R_X_DATA04DOWNTO0_intermed_1 <= R.X.DATA ( 0 )( 4 DOWNTO 0 );
R_X_DATA04DOWNTO0_intermed_2 <= R_X_DATA04DOWNTO0_intermed_1;
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
DCO_DATA04DOWNTO0_intermed_1 <= DCO.DATA ( 0 )( 4 DOWNTO 0 );
DCO_DATA04DOWNTO0_intermed_2 <= DCO_DATA04DOWNTO0_intermed_1;
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA ( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_2 <= RIN_X_DATA04DOWNTO0_intermed_1;
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_2 <= RIN_X_DATA04DOWNTO0_intermed_1;
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
V_X_DATA04DOWNTO0_shadow_intermed_2 <= V_X_DATA04DOWNTO0_shadow_intermed_1;
RIN_A_RFE1_intermed_1 <= RIN.A.RFE1;
V_A_RFE1_shadow_intermed_1 <= V_A_RFE1_shadow;
RIN_A_RFE2_intermed_1 <= RIN.A.RFE2;
V_A_RFE2_shadow_intermed_1 <= V_A_RFE2_shadow;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_3 <= R_M_CTRL_PC31DOWNTO2_intermed_2;
R_M_CTRL_PC31DOWNTO2_intermed_4 <= R_M_CTRL_PC31DOWNTO2_intermed_3;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_4 <= RIN_M_CTRL_PC31DOWNTO2_intermed_3;
RIN_M_CTRL_PC31DOWNTO2_intermed_5 <= RIN_M_CTRL_PC31DOWNTO2_intermed_4;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_4;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_6 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_5;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_6 <= RIN_A_CTRL_PC31DOWNTO2_intermed_5;
RIN_A_CTRL_PC31DOWNTO2_intermed_7 <= RIN_A_CTRL_PC31DOWNTO2_intermed_6;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
R_A_CTRL_PC31DOWNTO2_intermed_5 <= R_A_CTRL_PC31DOWNTO2_intermed_4;
R_A_CTRL_PC31DOWNTO2_intermed_6 <= R_A_CTRL_PC31DOWNTO2_intermed_5;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_4;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
R_X_CTRL_PC31DOWNTO2_intermed_2 <= R_X_CTRL_PC31DOWNTO2_intermed_1;
R_X_CTRL_PC31DOWNTO2_intermed_3 <= R_X_CTRL_PC31DOWNTO2_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
V_D_PC31DOWNTO2_shadow_intermed_6 <= V_D_PC31DOWNTO2_shadow_intermed_5;
V_D_PC31DOWNTO2_shadow_intermed_7 <= V_D_PC31DOWNTO2_shadow_intermed_6;
V_D_PC31DOWNTO2_shadow_intermed_8 <= V_D_PC31DOWNTO2_shadow_intermed_7;
XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO2_shadow;
XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_2 <= XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_D_PC31DOWNTO2_intermed_6 <= RIN_D_PC31DOWNTO2_intermed_5;
RIN_D_PC31DOWNTO2_intermed_7 <= RIN_D_PC31DOWNTO2_intermed_6;
RIN_D_PC31DOWNTO2_intermed_8 <= RIN_D_PC31DOWNTO2_intermed_7;
EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow;
EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_2 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1;
V_F_PC31DOWNTO2_shadow_intermed_1 <= V_F_PC31DOWNTO2_shadow;
V_F_PC31DOWNTO2_shadow_intermed_2 <= V_F_PC31DOWNTO2_shadow_intermed_1;
V_F_PC31DOWNTO2_shadow_intermed_1 <= V_F_PC31DOWNTO2_shadow;
RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC( 31 DOWNTO 2 );
RIN_F_PC31DOWNTO2_intermed_2 <= RIN_F_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_3 <= RIN_X_CTRL_PC31DOWNTO2_intermed_2;
RIN_X_CTRL_PC31DOWNTO2_intermed_4 <= RIN_X_CTRL_PC31DOWNTO2_intermed_3;
IRIN_ADDR31DOWNTO2_intermed_1 <= IRIN.ADDR( 31 DOWNTO 2 );
IRIN_ADDR31DOWNTO2_intermed_2 <= IRIN_ADDR31DOWNTO2_intermed_1;
IRIN_ADDR31DOWNTO2_intermed_3 <= IRIN_ADDR31DOWNTO2_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_4 <= R_E_CTRL_PC31DOWNTO2_intermed_3;
R_E_CTRL_PC31DOWNTO2_intermed_5 <= R_E_CTRL_PC31DOWNTO2_intermed_4;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_5;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_7 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_6;
EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO2_shadow;
EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_2 <= EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_D_PC31DOWNTO2_intermed_5 <= R_D_PC31DOWNTO2_intermed_4;
R_D_PC31DOWNTO2_intermed_6 <= R_D_PC31DOWNTO2_intermed_5;
R_D_PC31DOWNTO2_intermed_7 <= R_D_PC31DOWNTO2_intermed_6;
RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC ( 31 DOWNTO 2 );
IR_ADDR31DOWNTO2_intermed_1 <= IR.ADDR( 31 DOWNTO 2 );
IR_ADDR31DOWNTO2_intermed_2 <= IR_ADDR31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_5 <= RIN_E_CTRL_PC31DOWNTO2_intermed_4;
RIN_E_CTRL_PC31DOWNTO2_intermed_6 <= RIN_E_CTRL_PC31DOWNTO2_intermed_5;
R_F_PC31DOWNTO2_intermed_1 <= R.F.PC( 31 DOWNTO 2 );
R_F_PC31DOWNTO2_intermed_2 <= R_F_PC31DOWNTO2_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_3;
VIR_ADDR31DOWNTO2_shadow_intermed_1 <= VIR_ADDR31DOWNTO2_shadow;
VIR_ADDR31DOWNTO2_shadow_intermed_2 <= VIR_ADDR31DOWNTO2_shadow_intermed_1;
VIR_ADDR31DOWNTO2_shadow_intermed_3 <= VIR_ADDR31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC ( 31 DOWNTO 2 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC ( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_3 <= R_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_4 <= RIN_M_CTRL_PC31DOWNTO2_intermed_3;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_6 <= RIN_A_CTRL_PC31DOWNTO2_intermed_5;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
R_A_CTRL_PC31DOWNTO2_intermed_5 <= R_A_CTRL_PC31DOWNTO2_intermed_4;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
R_X_CTRL_PC31DOWNTO2_intermed_2 <= R_X_CTRL_PC31DOWNTO2_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
V_D_PC31DOWNTO2_shadow_intermed_6 <= V_D_PC31DOWNTO2_shadow_intermed_5;
V_D_PC31DOWNTO2_shadow_intermed_7 <= V_D_PC31DOWNTO2_shadow_intermed_6;
XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO2_shadow;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_D_PC31DOWNTO2_intermed_6 <= RIN_D_PC31DOWNTO2_intermed_5;
RIN_D_PC31DOWNTO2_intermed_7 <= RIN_D_PC31DOWNTO2_intermed_6;
EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow;
EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_2 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1;
V_F_PC31DOWNTO2_shadow_intermed_1 <= V_F_PC31DOWNTO2_shadow;
V_F_PC31DOWNTO2_shadow_intermed_2 <= V_F_PC31DOWNTO2_shadow_intermed_1;
V_F_PC31DOWNTO2_shadow_intermed_1 <= V_F_PC31DOWNTO2_shadow;
RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC( 31 DOWNTO 2 );
RIN_F_PC31DOWNTO2_intermed_2 <= RIN_F_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_3 <= RIN_X_CTRL_PC31DOWNTO2_intermed_2;
IRIN_ADDR31DOWNTO2_intermed_1 <= IRIN.ADDR( 31 DOWNTO 2 );
IRIN_ADDR31DOWNTO2_intermed_2 <= IRIN_ADDR31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_4 <= R_E_CTRL_PC31DOWNTO2_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_5;
EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO2_shadow;
EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_2 <= EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_D_PC31DOWNTO2_intermed_5 <= R_D_PC31DOWNTO2_intermed_4;
R_D_PC31DOWNTO2_intermed_6 <= R_D_PC31DOWNTO2_intermed_5;
RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC ( 31 DOWNTO 2 );
IR_ADDR31DOWNTO2_intermed_1 <= IR.ADDR( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_5 <= RIN_E_CTRL_PC31DOWNTO2_intermed_4;
R_F_PC31DOWNTO2_intermed_1 <= R.F.PC( 31 DOWNTO 2 );
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_2;
VIR_ADDR31DOWNTO2_shadow_intermed_1 <= VIR_ADDR31DOWNTO2_shadow;
VIR_ADDR31DOWNTO2_shadow_intermed_2 <= VIR_ADDR31DOWNTO2_shadow_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_3 <= R_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_4 <= RIN_M_CTRL_PC31DOWNTO2_intermed_3;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_6 <= RIN_A_CTRL_PC31DOWNTO2_intermed_5;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
R_A_CTRL_PC31DOWNTO2_intermed_5 <= R_A_CTRL_PC31DOWNTO2_intermed_4;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
R_X_CTRL_PC31DOWNTO2_intermed_2 <= R_X_CTRL_PC31DOWNTO2_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
V_D_PC31DOWNTO2_shadow_intermed_6 <= V_D_PC31DOWNTO2_shadow_intermed_5;
V_D_PC31DOWNTO2_shadow_intermed_7 <= V_D_PC31DOWNTO2_shadow_intermed_6;
XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO2_shadow;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_D_PC31DOWNTO2_intermed_6 <= RIN_D_PC31DOWNTO2_intermed_5;
RIN_D_PC31DOWNTO2_intermed_7 <= RIN_D_PC31DOWNTO2_intermed_6;
EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow;
V_F_PC31DOWNTO2_shadow_intermed_1 <= V_F_PC31DOWNTO2_shadow;
RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_3 <= RIN_X_CTRL_PC31DOWNTO2_intermed_2;
IRIN_ADDR31DOWNTO2_intermed_1 <= IRIN.ADDR( 31 DOWNTO 2 );
IRIN_ADDR31DOWNTO2_intermed_2 <= IRIN_ADDR31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_4 <= R_E_CTRL_PC31DOWNTO2_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_5;
EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO2_shadow;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_D_PC31DOWNTO2_intermed_5 <= R_D_PC31DOWNTO2_intermed_4;
R_D_PC31DOWNTO2_intermed_6 <= R_D_PC31DOWNTO2_intermed_5;
IR_ADDR31DOWNTO2_intermed_1 <= IR.ADDR( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_5 <= RIN_E_CTRL_PC31DOWNTO2_intermed_4;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_2;
VIR_ADDR31DOWNTO2_shadow_intermed_1 <= VIR_ADDR31DOWNTO2_shadow;
VIR_ADDR31DOWNTO2_shadow_intermed_2 <= VIR_ADDR31DOWNTO2_shadow_intermed_1;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
V_A_MULSTART_shadow_intermed_1 <= V_A_MULSTART_shadow;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
RIN_A_MULSTART_intermed_1 <= RIN.A.MULSTART;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
V_X_DATA0_shadow_intermed_2 <= V_X_DATA0_shadow_intermed_1;
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
DE_INST19_shadow_intermed_2 <= DE_INST19_shadow_intermed_1;
RIN_E_OP131_intermed_1 <= RIN.E.OP1( 31 );
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_A_CTRL_INST19_shadow_intermed_3 <= V_A_CTRL_INST19_shadow_intermed_2;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA ( 0 );
V_E_OP131_shadow_intermed_1 <= V_E_OP131_shadow;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_OP1_shadow_intermed_1 <= V_E_OP1_shadow;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_CTRL_INST19_shadow_intermed_2 <= V_E_CTRL_INST19_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
RIN_E_OP1_intermed_1 <= RIN.E.OP1;
R_E_CTRL_INST19_intermed_1 <= R.E.CTRL.INST( 19 );
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 );
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
R_X_DATA0_intermed_1 <= R.X.DATA( 0 );
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
R_A_CTRL_INST19_intermed_2 <= R_A_CTRL_INST19_intermed_1;
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
RIN_A_CTRL_INST19_intermed_3 <= RIN_A_CTRL_INST19_intermed_2;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST ( 19 );
DCO_DATA0_intermed_1 <= DCO.DATA ( 0 );
RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 );
RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST( 19 );
RIN_E_CTRL_INST19_intermed_2 <= RIN_E_CTRL_INST19_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
V_X_DATA0_shadow_intermed_2 <= V_X_DATA0_shadow_intermed_1;
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
DE_INST19_shadow_intermed_2 <= DE_INST19_shadow_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_A_CTRL_INST19_shadow_intermed_3 <= V_A_CTRL_INST19_shadow_intermed_2;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA ( 0 );
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
V_E_OP2_shadow_intermed_1 <= V_E_OP2_shadow;
RIN_E_OP2_intermed_1 <= RIN.E.OP2;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_CTRL_INST19_shadow_intermed_2 <= V_E_CTRL_INST19_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
R_E_CTRL_INST19_intermed_1 <= R.E.CTRL.INST( 19 );
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 );
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
R_X_DATA0_intermed_1 <= R.X.DATA( 0 );
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
R_A_CTRL_INST19_intermed_2 <= R_A_CTRL_INST19_intermed_1;
RIN_E_OP231_intermed_1 <= RIN.E.OP2( 31 );
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
RIN_A_CTRL_INST19_intermed_3 <= RIN_A_CTRL_INST19_intermed_2;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST ( 19 );
V_E_OP231_shadow_intermed_1 <= V_E_OP231_shadow;
DCO_DATA0_intermed_1 <= DCO.DATA ( 0 );
RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 );
RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST( 19 );
RIN_E_CTRL_INST19_intermed_2 <= RIN_E_CTRL_INST19_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_A_CTRL_INST24_shadow_intermed_1 <= V_A_CTRL_INST24_shadow;
V_A_CTRL_INST24_shadow_intermed_2 <= V_A_CTRL_INST24_shadow_intermed_1;
V_A_CTRL_INST24_shadow_intermed_3 <= V_A_CTRL_INST24_shadow_intermed_2;
V_E_CTRL_INST24_shadow_intermed_1 <= V_E_CTRL_INST24_shadow;
V_E_CTRL_INST24_shadow_intermed_2 <= V_E_CTRL_INST24_shadow_intermed_1;
DE_INST24_shadow_intermed_1 <= DE_INST24_shadow;
DE_INST24_shadow_intermed_2 <= DE_INST24_shadow_intermed_1;
DE_INST24_shadow_intermed_3 <= DE_INST24_shadow_intermed_2;
V_E_CTRL_INST24_shadow_intermed_1 <= V_E_CTRL_INST24_shadow;
R_A_CTRL_INST24_intermed_1 <= R.A.CTRL.INST( 24 );
R_A_CTRL_INST24_intermed_2 <= R_A_CTRL_INST24_intermed_1;
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST ( 24 );
RIN_A_CTRL_INST24_intermed_2 <= RIN_A_CTRL_INST24_intermed_1;
V_A_CTRL_INST24_shadow_intermed_1 <= V_A_CTRL_INST24_shadow;
V_A_CTRL_INST24_shadow_intermed_2 <= V_A_CTRL_INST24_shadow_intermed_1;
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST( 24 );
RIN_A_CTRL_INST24_intermed_2 <= RIN_A_CTRL_INST24_intermed_1;
RIN_A_CTRL_INST24_intermed_3 <= RIN_A_CTRL_INST24_intermed_2;
RIN_E_CTRL_INST24_intermed_1 <= RIN.E.CTRL.INST( 24 );
RIN_E_CTRL_INST24_intermed_2 <= RIN_E_CTRL_INST24_intermed_1;
R_E_CTRL_INST24_intermed_1 <= R.E.CTRL.INST( 24 );
R_E_CTRL_INST24_intermed_2 <= R_E_CTRL_INST24_intermed_1;
R_A_CTRL_INST24_intermed_1 <= R.A.CTRL.INST ( 24 );
RIN_E_CTRL_INST24_intermed_1 <= RIN.E.CTRL.INST ( 24 );
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_DIVSTART_intermed_1 <= RIN.A.DIVSTART;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
V_A_DIVSTART_shadow_intermed_1 <= V_A_DIVSTART_shadow;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
V_X_DATA0_shadow_intermed_2 <= V_X_DATA0_shadow_intermed_1;
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
DE_INST19_shadow_intermed_2 <= DE_INST19_shadow_intermed_1;
RIN_E_OP131_intermed_1 <= RIN.E.OP1( 31 );
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_A_CTRL_INST19_shadow_intermed_3 <= V_A_CTRL_INST19_shadow_intermed_2;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA ( 0 );
V_E_OP131_shadow_intermed_1 <= V_E_OP131_shadow;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_OP1_shadow_intermed_1 <= V_E_OP1_shadow;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_CTRL_INST19_shadow_intermed_2 <= V_E_CTRL_INST19_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
RIN_E_OP1_intermed_1 <= RIN.E.OP1;
R_E_CTRL_INST19_intermed_1 <= R.E.CTRL.INST( 19 );
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 );
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
R_X_DATA0_intermed_1 <= R.X.DATA( 0 );
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
R_A_CTRL_INST19_intermed_2 <= R_A_CTRL_INST19_intermed_1;
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
RIN_A_CTRL_INST19_intermed_3 <= RIN_A_CTRL_INST19_intermed_2;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST ( 19 );
DCO_DATA0_intermed_1 <= DCO.DATA ( 0 );
RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 );
RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST( 19 );
RIN_E_CTRL_INST19_intermed_2 <= RIN_E_CTRL_INST19_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
V_X_DATA0_shadow_intermed_2 <= V_X_DATA0_shadow_intermed_1;
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
DE_INST19_shadow_intermed_2 <= DE_INST19_shadow_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_A_CTRL_INST19_shadow_intermed_3 <= V_A_CTRL_INST19_shadow_intermed_2;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA ( 0 );
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
V_E_OP2_shadow_intermed_1 <= V_E_OP2_shadow;
RIN_E_OP2_intermed_1 <= RIN.E.OP2;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_CTRL_INST19_shadow_intermed_2 <= V_E_CTRL_INST19_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
R_E_CTRL_INST19_intermed_1 <= R.E.CTRL.INST( 19 );
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 );
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
R_X_DATA0_intermed_1 <= R.X.DATA( 0 );
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
R_A_CTRL_INST19_intermed_2 <= R_A_CTRL_INST19_intermed_1;
RIN_E_OP231_intermed_1 <= RIN.E.OP2( 31 );
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
RIN_A_CTRL_INST19_intermed_3 <= RIN_A_CTRL_INST19_intermed_2;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST ( 19 );
V_E_OP231_shadow_intermed_1 <= V_E_OP231_shadow;
DCO_DATA0_intermed_1 <= DCO.DATA ( 0 );
RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 );
RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST( 19 );
RIN_E_CTRL_INST19_intermed_2 <= RIN_E_CTRL_INST19_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
DE_INST19_shadow_intermed_2 <= DE_INST19_shadow_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 );
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
R_A_CTRL_INST19_intermed_2 <= R_A_CTRL_INST19_intermed_1;
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
RIN_M_Y31_intermed_1 <= RIN.M.Y ( 31 );
RIN_M_Y_intermed_1 <= RIN.M.Y;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_M_Y31_shadow_intermed_1 <= V_M_Y31_shadow;
V_M_Y31_shadow_intermed_2 <= V_M_Y31_shadow_intermed_1;
V_M_Y_shadow_intermed_1 <= V_M_Y_shadow;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_CTRL_INST19_shadow_intermed_2 <= V_E_CTRL_INST19_shadow_intermed_1;
R_E_CTRL_INST19_intermed_1 <= R.E.CTRL.INST( 19 );
V_M_Y31_shadow_intermed_1 <= V_M_Y31_shadow;
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 );
RIN_M_Y31_intermed_1 <= RIN.M.Y( 31 );
RIN_M_Y31_intermed_2 <= RIN_M_Y31_intermed_1;
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
R_M_Y31_intermed_1 <= R.M.Y( 31 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST ( 19 );
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST( 19 );
RIN_E_CTRL_INST19_intermed_2 <= RIN_E_CTRL_INST19_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
RIN_M_Y31_intermed_1 <= RIN.M.Y ( 31 );
V_M_Y31_shadow_intermed_1 <= V_M_Y31_shadow;
V_M_Y31_shadow_intermed_2 <= V_M_Y31_shadow_intermed_1;
V_M_Y31_shadow_intermed_1 <= V_M_Y31_shadow;
RIN_M_Y31_intermed_1 <= RIN.M.Y( 31 );
RIN_M_Y31_intermed_2 <= RIN_M_Y31_intermed_1;
R_M_Y31_intermed_1 <= R.M.Y( 31 );
R_M_Y31_intermed_2 <= R_M_Y31_intermed_1;
VDSU_CRDY2_shadow_intermed_1 <= VDSU_CRDY2_shadow;
VDSU_CRDY2_shadow_intermed_2 <= VDSU_CRDY2_shadow_intermed_1;
DSUIN_CRDY2_intermed_1 <= DSUIN.CRDY ( 2 );
VDSU_CRDY2_shadow_intermed_1 <= VDSU_CRDY2_shadow;
DSUIN_CRDY2_intermed_1 <= DSUIN.CRDY( 2 );
DSUIN_CRDY2_intermed_2 <= DSUIN_CRDY2_intermed_1;
DSUR_CRDY2_intermed_1 <= DSUR.CRDY( 2 );
DSUR_CRDY2_intermed_2 <= DSUR_CRDY2_intermed_1;
VP_ERROR_shadow_intermed_1 <= VP_ERROR_shadow;
VP_ERROR_shadow_intermed_2 <= VP_ERROR_shadow_intermed_1;
RIN_X_NERROR_intermed_1 <= RIN.X.NERROR;
RPIN_ERROR_intermed_1 <= RPIN.ERROR;
RPIN_ERROR_intermed_2 <= RPIN_ERROR_intermed_1;
V_X_NERROR_shadow_intermed_1 <= V_X_NERROR_shadow;
RP_ERROR_intermed_1 <= RP.ERROR;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC ( 31 DOWNTO 2 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC ( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC ( 31 DOWNTO 2 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC ( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC ( 31 DOWNTO 2 );
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow;
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 );
RIN_X_RESULT6DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO0_intermed_1;
R_X_RESULT6DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 );
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
R_X_DATA0_intermed_1 <= R.X.DATA( 0 );
RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 );
RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC ( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC ( 31 DOWNTO 2 );
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC ( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC ( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_X_CTRL_TT3DOWNTO0_shadow;
V_X_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_X_CTRL_TT3DOWNTO0_shadow_intermed_1;
R_M_CTRL_TT3DOWNTO0_intermed_1 <= R.M.CTRL.TT( 3 DOWNTO 0 );
R_M_CTRL_TT3DOWNTO0_intermed_2 <= R_M_CTRL_TT3DOWNTO0_intermed_1;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_M_CTRL_TT3DOWNTO0_shadow;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_M_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_M_CTRL_TT3DOWNTO0_shadow_intermed_2;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_3 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2;
R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
R_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= R_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
R_A_CTRL_TT3DOWNTO0_intermed_1 <= R.A.CTRL.TT( 3 DOWNTO 0 );
R_A_CTRL_TT3DOWNTO0_intermed_2 <= R_A_CTRL_TT3DOWNTO0_intermed_1;
R_A_CTRL_TT3DOWNTO0_intermed_3 <= R_A_CTRL_TT3DOWNTO0_intermed_2;
R_A_CTRL_TT3DOWNTO0_intermed_4 <= R_A_CTRL_TT3DOWNTO0_intermed_3;
RIN_A_CTRL_TT3DOWNTO0_intermed_1 <= RIN.A.CTRL.TT( 3 DOWNTO 0 );
RIN_A_CTRL_TT3DOWNTO0_intermed_2 <= RIN_A_CTRL_TT3DOWNTO0_intermed_1;
RIN_A_CTRL_TT3DOWNTO0_intermed_3 <= RIN_A_CTRL_TT3DOWNTO0_intermed_2;
RIN_A_CTRL_TT3DOWNTO0_intermed_4 <= RIN_A_CTRL_TT3DOWNTO0_intermed_3;
RIN_A_CTRL_TT3DOWNTO0_intermed_5 <= RIN_A_CTRL_TT3DOWNTO0_intermed_4;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_3 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_A_CTRL_TT3DOWNTO0_shadow;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_2;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_4 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_3;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_5 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_4;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
R_W_S_TT3DOWNTO0_intermed_1 <= R.W.S.TT( 3 DOWNTO 0 );
R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 );
R_E_CTRL_TT3DOWNTO0_intermed_1 <= R.E.CTRL.TT( 3 DOWNTO 0 );
R_E_CTRL_TT3DOWNTO0_intermed_2 <= R_E_CTRL_TT3DOWNTO0_intermed_1;
R_E_CTRL_TT3DOWNTO0_intermed_3 <= R_E_CTRL_TT3DOWNTO0_intermed_2;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1;
RIN_W_S_TT3DOWNTO0_intermed_1 <= RIN.W.S.TT( 3 DOWNTO 0 );
RIN_W_S_TT3DOWNTO0_intermed_2 <= RIN_W_S_TT3DOWNTO0_intermed_1;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_E_CTRL_TT3DOWNTO0_shadow;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_2;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_4 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_3;
RIN_M_CTRL_TT3DOWNTO0_intermed_1 <= RIN.M.CTRL.TT( 3 DOWNTO 0 );
RIN_M_CTRL_TT3DOWNTO0_intermed_2 <= RIN_M_CTRL_TT3DOWNTO0_intermed_1;
RIN_M_CTRL_TT3DOWNTO0_intermed_3 <= RIN_M_CTRL_TT3DOWNTO0_intermed_2;
RIN_X_CTRL_TT3DOWNTO0_intermed_1 <= RIN.X.CTRL.TT( 3 DOWNTO 0 );
RIN_X_CTRL_TT3DOWNTO0_intermed_2 <= RIN_X_CTRL_TT3DOWNTO0_intermed_1;
V_W_S_TT3DOWNTO0_shadow_intermed_1 <= V_W_S_TT3DOWNTO0_shadow;
R_X_CTRL_TT3DOWNTO0_intermed_1 <= R.X.CTRL.TT( 3 DOWNTO 0 );
RIN_E_CTRL_TT3DOWNTO0_intermed_1 <= RIN.E.CTRL.TT( 3 DOWNTO 0 );
RIN_E_CTRL_TT3DOWNTO0_intermed_2 <= RIN_E_CTRL_TT3DOWNTO0_intermed_1;
RIN_E_CTRL_TT3DOWNTO0_intermed_3 <= RIN_E_CTRL_TT3DOWNTO0_intermed_2;
RIN_E_CTRL_TT3DOWNTO0_intermed_4 <= RIN_E_CTRL_TT3DOWNTO0_intermed_3;
XC_VECTT3DOWNTO0_shadow_intermed_1 <= XC_VECTT3DOWNTO0_shadow;
V_M_RESULT1DOWNTO0_shadow_intermed_1 <= V_M_RESULT1DOWNTO0_shadow;
RIN_M_RESULT1DOWNTO0_intermed_1 <= RIN.M.RESULT( 1 DOWNTO 0 );
RIN_M_RESULT1DOWNTO0_intermed_2 <= RIN_M_RESULT1DOWNTO0_intermed_1;
R_M_RESULT1DOWNTO0_intermed_1 <= R.M.RESULT( 1 DOWNTO 0 );
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 );
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
R_X_DATA031_intermed_1 <= R.X.DATA ( 0 )( 31 );
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
DE_INST19_shadow_intermed_2 <= DE_INST19_shadow_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
R_E_CTRL_INST19_intermed_1 <= R.E.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 );
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST( 19 );
RIN_E_CTRL_INST19_intermed_2 <= RIN_E_CTRL_INST19_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST ( 20 );
R_E_CTRL_INST20_intermed_1 <= R.E.CTRL.INST( 20 );
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST( 20 );
RIN_A_CTRL_INST20_intermed_2 <= RIN_A_CTRL_INST20_intermed_1;
V_E_CTRL_INST20_shadow_intermed_1 <= V_E_CTRL_INST20_shadow;
DE_INST20_shadow_intermed_1 <= DE_INST20_shadow;
DE_INST20_shadow_intermed_2 <= DE_INST20_shadow_intermed_1;
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
V_A_CTRL_INST20_shadow_intermed_2 <= V_A_CTRL_INST20_shadow_intermed_1;
RIN_E_CTRL_INST20_intermed_1 <= RIN.E.CTRL.INST( 20 );
RIN_E_CTRL_INST20_intermed_2 <= RIN_E_CTRL_INST20_intermed_1;
R_A_CTRL_INST20_intermed_1 <= R.A.CTRL.INST( 20 );
RIN_X_DATA00_intermed_1 <= RIN.X.DATA ( 0 )( 0 );
RIN_X_DATA00_intermed_2 <= RIN_X_DATA00_intermed_1;
DCO_DATA00_intermed_1 <= DCO.DATA ( 0 )( 0 );
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
R_X_DATA00_intermed_1 <= R.X.DATA ( 0 )( 0 );
RIN_X_DATA00_intermed_1 <= RIN.X.DATA( 0 )( 0 );
RIN_X_DATA00_intermed_2 <= RIN_X_DATA00_intermed_1;
R_X_DATA00_intermed_1 <= R.X.DATA( 0 )( 0 );
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
RIN_X_DATA00_intermed_1 <= RIN.X.DATA( 0 )( 0 );
RIN_X_DATA00_intermed_2 <= RIN_X_DATA00_intermed_1;
R_X_DATA00_intermed_1 <= R.X.DATA( 0 )( 0 );
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
R_X_DATA04DOWNTO0_intermed_1 <= R.X.DATA( 0 )( 4 DOWNTO 0 );
R_X_DATA04DOWNTO0_intermed_1 <= R.X.DATA ( 0 )( 4 DOWNTO 0 );
DCO_DATA04DOWNTO0_intermed_1 <= DCO.DATA ( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA ( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_2 <= RIN_X_DATA04DOWNTO0_intermed_1;
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_2 <= RIN_X_DATA04DOWNTO0_intermed_1;
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
R_X_DATA04DOWNTO0_intermed_1 <= R.X.DATA( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_2 <= RIN_X_DATA04DOWNTO0_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_3 <= R_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_4 <= RIN_M_CTRL_PC31DOWNTO2_intermed_3;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_6 <= RIN_A_CTRL_PC31DOWNTO2_intermed_5;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
R_A_CTRL_PC31DOWNTO2_intermed_5 <= R_A_CTRL_PC31DOWNTO2_intermed_4;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
R_X_CTRL_PC31DOWNTO2_intermed_2 <= R_X_CTRL_PC31DOWNTO2_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
V_D_PC31DOWNTO2_shadow_intermed_6 <= V_D_PC31DOWNTO2_shadow_intermed_5;
V_D_PC31DOWNTO2_shadow_intermed_7 <= V_D_PC31DOWNTO2_shadow_intermed_6;
XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO2_shadow;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_D_PC31DOWNTO2_intermed_6 <= RIN_D_PC31DOWNTO2_intermed_5;
RIN_D_PC31DOWNTO2_intermed_7 <= RIN_D_PC31DOWNTO2_intermed_6;
EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow;
V_F_PC31DOWNTO2_shadow_intermed_1 <= V_F_PC31DOWNTO2_shadow;
RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC( 31 DOWNTO 2 );
RIN_F_PC31DOWNTO2_intermed_2 <= RIN_F_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_3 <= RIN_X_CTRL_PC31DOWNTO2_intermed_2;
IRIN_ADDR31DOWNTO2_intermed_1 <= IRIN.ADDR( 31 DOWNTO 2 );
IRIN_ADDR31DOWNTO2_intermed_2 <= IRIN_ADDR31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_4 <= R_E_CTRL_PC31DOWNTO2_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_5;
EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO2_shadow;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_D_PC31DOWNTO2_intermed_5 <= R_D_PC31DOWNTO2_intermed_4;
R_D_PC31DOWNTO2_intermed_6 <= R_D_PC31DOWNTO2_intermed_5;
IR_ADDR31DOWNTO2_intermed_1 <= IR.ADDR( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_5 <= RIN_E_CTRL_PC31DOWNTO2_intermed_4;
R_F_PC31DOWNTO2_intermed_1 <= R.F.PC( 31 DOWNTO 2 );
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_2;
VIR_ADDR31DOWNTO2_shadow_intermed_1 <= VIR_ADDR31DOWNTO2_shadow;
VIR_ADDR31DOWNTO2_shadow_intermed_2 <= VIR_ADDR31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
V_A_CTRL_INST24_shadow_intermed_1 <= V_A_CTRL_INST24_shadow;
V_A_CTRL_INST24_shadow_intermed_2 <= V_A_CTRL_INST24_shadow_intermed_1;
V_E_CTRL_INST24_shadow_intermed_1 <= V_E_CTRL_INST24_shadow;
DE_INST24_shadow_intermed_1 <= DE_INST24_shadow;
DE_INST24_shadow_intermed_2 <= DE_INST24_shadow_intermed_1;
R_A_CTRL_INST24_intermed_1 <= R.A.CTRL.INST( 24 );
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST ( 24 );
V_A_CTRL_INST24_shadow_intermed_1 <= V_A_CTRL_INST24_shadow;
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST( 24 );
RIN_A_CTRL_INST24_intermed_2 <= RIN_A_CTRL_INST24_intermed_1;
RIN_E_CTRL_INST24_intermed_1 <= RIN.E.CTRL.INST( 24 );
RIN_E_CTRL_INST24_intermed_2 <= RIN_E_CTRL_INST24_intermed_1;
R_E_CTRL_INST24_intermed_1 <= R.E.CTRL.INST( 24 );
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
V_M_Y31_shadow_intermed_1 <= V_M_Y31_shadow;
RIN_M_Y31_intermed_1 <= RIN.M.Y( 31 );
RIN_M_Y31_intermed_2 <= RIN_M_Y31_intermed_1;
R_M_Y31_intermed_1 <= R.M.Y( 31 );
VDSU_CRDY2_shadow_intermed_1 <= VDSU_CRDY2_shadow;
DSUIN_CRDY2_intermed_1 <= DSUIN.CRDY( 2 );
DSUIN_CRDY2_intermed_2 <= DSUIN_CRDY2_intermed_1;
DSUR_CRDY2_intermed_1 <= DSUR.CRDY( 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC ( 31 DOWNTO 2 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_X_DATA1_shadow_intermed_1 <= V_X_DATA1_shadow;
DCO_DATA1_intermed_1 <= DCO.DATA ( 1 );
V_X_DATA1_shadow_intermed_1 <= V_X_DATA1_shadow;
V_X_DATA1_shadow_intermed_2 <= V_X_DATA1_shadow_intermed_1;
RIN_X_DATA1_intermed_1 <= RIN.X.DATA ( 1 );
R_X_DATA1_intermed_1 <= R.X.DATA( 1 );
R_X_DATA1_intermed_2 <= R_X_DATA1_intermed_1;
RIN_X_DATA1_intermed_1 <= RIN.X.DATA( 1 );
RIN_X_DATA1_intermed_2 <= RIN_X_DATA1_intermed_1;
EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO12_shadow;
EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_2 <= EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_1;
RIN_F_PC31DOWNTO12_intermed_1 <= RIN.F.PC ( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_2 <= RIN_A_CTRL_PC31DOWNTO12_intermed_1;
RIN_A_CTRL_PC31DOWNTO12_intermed_3 <= RIN_A_CTRL_PC31DOWNTO12_intermed_2;
RIN_A_CTRL_PC31DOWNTO12_intermed_4 <= RIN_A_CTRL_PC31DOWNTO12_intermed_3;
RIN_A_CTRL_PC31DOWNTO12_intermed_5 <= RIN_A_CTRL_PC31DOWNTO12_intermed_4;
RIN_A_CTRL_PC31DOWNTO12_intermed_6 <= RIN_A_CTRL_PC31DOWNTO12_intermed_5;
RIN_A_CTRL_PC31DOWNTO12_intermed_7 <= RIN_A_CTRL_PC31DOWNTO12_intermed_6;
RIN_E_CTRL_PC31DOWNTO12_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 12 );
RIN_E_CTRL_PC31DOWNTO12_intermed_2 <= RIN_E_CTRL_PC31DOWNTO12_intermed_1;
RIN_E_CTRL_PC31DOWNTO12_intermed_3 <= RIN_E_CTRL_PC31DOWNTO12_intermed_2;
RIN_E_CTRL_PC31DOWNTO12_intermed_4 <= RIN_E_CTRL_PC31DOWNTO12_intermed_3;
RIN_E_CTRL_PC31DOWNTO12_intermed_5 <= RIN_E_CTRL_PC31DOWNTO12_intermed_4;
RIN_E_CTRL_PC31DOWNTO12_intermed_6 <= RIN_E_CTRL_PC31DOWNTO12_intermed_5;
V_F_PC31DOWNTO12_shadow_intermed_1 <= V_F_PC31DOWNTO12_shadow;
V_F_PC31DOWNTO12_shadow_intermed_2 <= V_F_PC31DOWNTO12_shadow_intermed_1;
R_M_CTRL_PC31DOWNTO12_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 12 );
R_M_CTRL_PC31DOWNTO12_intermed_2 <= R_M_CTRL_PC31DOWNTO12_intermed_1;
R_M_CTRL_PC31DOWNTO12_intermed_3 <= R_M_CTRL_PC31DOWNTO12_intermed_2;
R_M_CTRL_PC31DOWNTO12_intermed_4 <= R_M_CTRL_PC31DOWNTO12_intermed_3;
IRIN_ADDR31DOWNTO12_intermed_1 <= IRIN.ADDR( 31 DOWNTO 12 );
IRIN_ADDR31DOWNTO12_intermed_2 <= IRIN_ADDR31DOWNTO12_intermed_1;
IRIN_ADDR31DOWNTO12_intermed_3 <= IRIN_ADDR31DOWNTO12_intermed_2;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO12_shadow;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_3;
EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO13_shadow;
EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_2 <= EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_1;
XC_TRAP_ADDRESS31DOWNTO12_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO12_shadow;
XC_TRAP_ADDRESS31DOWNTO12_shadow_intermed_2 <= XC_TRAP_ADDRESS31DOWNTO12_shadow_intermed_1;
R_F_PC31DOWNTO12_intermed_1 <= R.F.PC( 31 DOWNTO 12 );
R_F_PC31DOWNTO12_intermed_2 <= R_F_PC31DOWNTO12_intermed_1;
RIN_M_CTRL_PC31DOWNTO12_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 12 );
RIN_M_CTRL_PC31DOWNTO12_intermed_2 <= RIN_M_CTRL_PC31DOWNTO12_intermed_1;
RIN_M_CTRL_PC31DOWNTO12_intermed_3 <= RIN_M_CTRL_PC31DOWNTO12_intermed_2;
RIN_M_CTRL_PC31DOWNTO12_intermed_4 <= RIN_M_CTRL_PC31DOWNTO12_intermed_3;
RIN_M_CTRL_PC31DOWNTO12_intermed_5 <= RIN_M_CTRL_PC31DOWNTO12_intermed_4;
IR_ADDR31DOWNTO12_intermed_1 <= IR.ADDR( 31 DOWNTO 12 );
IR_ADDR31DOWNTO12_intermed_2 <= IR_ADDR31DOWNTO12_intermed_1;
R_X_CTRL_PC31DOWNTO12_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 12 );
R_X_CTRL_PC31DOWNTO12_intermed_2 <= R_X_CTRL_PC31DOWNTO12_intermed_1;
R_X_CTRL_PC31DOWNTO12_intermed_3 <= R_X_CTRL_PC31DOWNTO12_intermed_2;
V_D_PC31DOWNTO12_shadow_intermed_1 <= V_D_PC31DOWNTO12_shadow;
V_D_PC31DOWNTO12_shadow_intermed_2 <= V_D_PC31DOWNTO12_shadow_intermed_1;
V_D_PC31DOWNTO12_shadow_intermed_3 <= V_D_PC31DOWNTO12_shadow_intermed_2;
V_D_PC31DOWNTO12_shadow_intermed_4 <= V_D_PC31DOWNTO12_shadow_intermed_3;
V_D_PC31DOWNTO12_shadow_intermed_5 <= V_D_PC31DOWNTO12_shadow_intermed_4;
V_D_PC31DOWNTO12_shadow_intermed_6 <= V_D_PC31DOWNTO12_shadow_intermed_5;
V_D_PC31DOWNTO12_shadow_intermed_7 <= V_D_PC31DOWNTO12_shadow_intermed_6;
V_D_PC31DOWNTO12_shadow_intermed_8 <= V_D_PC31DOWNTO12_shadow_intermed_7;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO12_shadow;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_5;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_7 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_6;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO12_shadow;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_4;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_6 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_5;
EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_1 <= EX_ADD_RES32DOWNTO330DOWNTO11_shadow;
EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_2 <= EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_1;
RIN_F_PC31DOWNTO12_intermed_1 <= RIN.F.PC( 31 DOWNTO 12 );
RIN_F_PC31DOWNTO12_intermed_2 <= RIN_F_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_1 <= R.D.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_2 <= R_D_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_3 <= R_D_PC31DOWNTO12_intermed_2;
R_D_PC31DOWNTO12_intermed_4 <= R_D_PC31DOWNTO12_intermed_3;
R_D_PC31DOWNTO12_intermed_5 <= R_D_PC31DOWNTO12_intermed_4;
R_D_PC31DOWNTO12_intermed_6 <= R_D_PC31DOWNTO12_intermed_5;
R_D_PC31DOWNTO12_intermed_7 <= R_D_PC31DOWNTO12_intermed_6;
R_A_CTRL_PC31DOWNTO12_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 12 );
R_A_CTRL_PC31DOWNTO12_intermed_2 <= R_A_CTRL_PC31DOWNTO12_intermed_1;
R_A_CTRL_PC31DOWNTO12_intermed_3 <= R_A_CTRL_PC31DOWNTO12_intermed_2;
R_A_CTRL_PC31DOWNTO12_intermed_4 <= R_A_CTRL_PC31DOWNTO12_intermed_3;
R_A_CTRL_PC31DOWNTO12_intermed_5 <= R_A_CTRL_PC31DOWNTO12_intermed_4;
R_A_CTRL_PC31DOWNTO12_intermed_6 <= R_A_CTRL_PC31DOWNTO12_intermed_5;
R_E_CTRL_PC31DOWNTO12_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 12 );
R_E_CTRL_PC31DOWNTO12_intermed_2 <= R_E_CTRL_PC31DOWNTO12_intermed_1;
R_E_CTRL_PC31DOWNTO12_intermed_3 <= R_E_CTRL_PC31DOWNTO12_intermed_2;
R_E_CTRL_PC31DOWNTO12_intermed_4 <= R_E_CTRL_PC31DOWNTO12_intermed_3;
R_E_CTRL_PC31DOWNTO12_intermed_5 <= R_E_CTRL_PC31DOWNTO12_intermed_4;
RIN_X_CTRL_PC31DOWNTO12_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 12 );
RIN_X_CTRL_PC31DOWNTO12_intermed_2 <= RIN_X_CTRL_PC31DOWNTO12_intermed_1;
RIN_X_CTRL_PC31DOWNTO12_intermed_3 <= RIN_X_CTRL_PC31DOWNTO12_intermed_2;
RIN_X_CTRL_PC31DOWNTO12_intermed_4 <= RIN_X_CTRL_PC31DOWNTO12_intermed_3;
RIN_D_PC31DOWNTO12_intermed_1 <= RIN.D.PC( 31 DOWNTO 12 );
RIN_D_PC31DOWNTO12_intermed_2 <= RIN_D_PC31DOWNTO12_intermed_1;
RIN_D_PC31DOWNTO12_intermed_3 <= RIN_D_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_4 <= RIN_D_PC31DOWNTO12_intermed_3;
RIN_D_PC31DOWNTO12_intermed_5 <= RIN_D_PC31DOWNTO12_intermed_4;
RIN_D_PC31DOWNTO12_intermed_6 <= RIN_D_PC31DOWNTO12_intermed_5;
RIN_D_PC31DOWNTO12_intermed_7 <= RIN_D_PC31DOWNTO12_intermed_6;
RIN_D_PC31DOWNTO12_intermed_8 <= RIN_D_PC31DOWNTO12_intermed_7;
VIR_ADDR31DOWNTO12_shadow_intermed_1 <= VIR_ADDR31DOWNTO12_shadow;
VIR_ADDR31DOWNTO12_shadow_intermed_2 <= VIR_ADDR31DOWNTO12_shadow_intermed_1;
VIR_ADDR31DOWNTO12_shadow_intermed_3 <= VIR_ADDR31DOWNTO12_shadow_intermed_2;
V_F_PC31DOWNTO12_shadow_intermed_1 <= V_F_PC31DOWNTO12_shadow;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO12_shadow;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_4;
ICO_DATA0_intermed_1 <= ICO.DATA ( 0 );
RIN_D_INST0_intermed_1 <= RIN.D.INST ( 0 );
V_D_INST0_shadow_intermed_1 <= V_D_INST0_shadow;
V_D_INST0_shadow_intermed_2 <= V_D_INST0_shadow_intermed_1;
R_D_INST0_intermed_1 <= R.D.INST( 0 );
R_D_INST0_intermed_2 <= R_D_INST0_intermed_1;
RIN_D_INST0_intermed_1 <= RIN.D.INST( 0 );
RIN_D_INST0_intermed_2 <= RIN_D_INST0_intermed_1;
V_D_INST0_shadow_intermed_1 <= V_D_INST0_shadow;
V_D_INST1_shadow_intermed_1 <= V_D_INST1_shadow;
V_D_INST1_shadow_intermed_2 <= V_D_INST1_shadow_intermed_1;
RIN_D_INST1_intermed_1 <= RIN.D.INST ( 1 );
RIN_D_INST1_intermed_1 <= RIN.D.INST( 1 );
RIN_D_INST1_intermed_2 <= RIN_D_INST1_intermed_1;
V_D_INST1_shadow_intermed_1 <= V_D_INST1_shadow;
R_D_INST1_intermed_1 <= R.D.INST( 1 );
R_D_INST1_intermed_2 <= R_D_INST1_intermed_1;
ICO_DATA1_intermed_1 <= ICO.DATA ( 1 );
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 );
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
R_X_DATA031_intermed_2 <= R_X_DATA031_intermed_1;
V_X_DATA1_shadow_intermed_1 <= V_X_DATA1_shadow;
R_X_DATA1_intermed_1 <= R.X.DATA( 1 );
RIN_X_DATA1_intermed_1 <= RIN.X.DATA( 1 );
RIN_X_DATA1_intermed_2 <= RIN_X_DATA1_intermed_1;
EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO12_shadow;
RIN_A_CTRL_PC31DOWNTO12_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_2 <= RIN_A_CTRL_PC31DOWNTO12_intermed_1;
RIN_A_CTRL_PC31DOWNTO12_intermed_3 <= RIN_A_CTRL_PC31DOWNTO12_intermed_2;
RIN_A_CTRL_PC31DOWNTO12_intermed_4 <= RIN_A_CTRL_PC31DOWNTO12_intermed_3;
RIN_A_CTRL_PC31DOWNTO12_intermed_5 <= RIN_A_CTRL_PC31DOWNTO12_intermed_4;
RIN_A_CTRL_PC31DOWNTO12_intermed_6 <= RIN_A_CTRL_PC31DOWNTO12_intermed_5;
RIN_E_CTRL_PC31DOWNTO12_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 12 );
RIN_E_CTRL_PC31DOWNTO12_intermed_2 <= RIN_E_CTRL_PC31DOWNTO12_intermed_1;
RIN_E_CTRL_PC31DOWNTO12_intermed_3 <= RIN_E_CTRL_PC31DOWNTO12_intermed_2;
RIN_E_CTRL_PC31DOWNTO12_intermed_4 <= RIN_E_CTRL_PC31DOWNTO12_intermed_3;
RIN_E_CTRL_PC31DOWNTO12_intermed_5 <= RIN_E_CTRL_PC31DOWNTO12_intermed_4;
V_F_PC31DOWNTO12_shadow_intermed_1 <= V_F_PC31DOWNTO12_shadow;
R_M_CTRL_PC31DOWNTO12_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 12 );
R_M_CTRL_PC31DOWNTO12_intermed_2 <= R_M_CTRL_PC31DOWNTO12_intermed_1;
R_M_CTRL_PC31DOWNTO12_intermed_3 <= R_M_CTRL_PC31DOWNTO12_intermed_2;
IRIN_ADDR31DOWNTO12_intermed_1 <= IRIN.ADDR( 31 DOWNTO 12 );
IRIN_ADDR31DOWNTO12_intermed_2 <= IRIN_ADDR31DOWNTO12_intermed_1;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO12_shadow;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_2;
EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO13_shadow;
XC_TRAP_ADDRESS31DOWNTO12_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO12_shadow;
R_F_PC31DOWNTO12_intermed_1 <= R.F.PC( 31 DOWNTO 12 );
RIN_M_CTRL_PC31DOWNTO12_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 12 );
RIN_M_CTRL_PC31DOWNTO12_intermed_2 <= RIN_M_CTRL_PC31DOWNTO12_intermed_1;
RIN_M_CTRL_PC31DOWNTO12_intermed_3 <= RIN_M_CTRL_PC31DOWNTO12_intermed_2;
RIN_M_CTRL_PC31DOWNTO12_intermed_4 <= RIN_M_CTRL_PC31DOWNTO12_intermed_3;
IR_ADDR31DOWNTO12_intermed_1 <= IR.ADDR( 31 DOWNTO 12 );
R_X_CTRL_PC31DOWNTO12_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 12 );
R_X_CTRL_PC31DOWNTO12_intermed_2 <= R_X_CTRL_PC31DOWNTO12_intermed_1;
V_D_PC31DOWNTO12_shadow_intermed_1 <= V_D_PC31DOWNTO12_shadow;
V_D_PC31DOWNTO12_shadow_intermed_2 <= V_D_PC31DOWNTO12_shadow_intermed_1;
V_D_PC31DOWNTO12_shadow_intermed_3 <= V_D_PC31DOWNTO12_shadow_intermed_2;
V_D_PC31DOWNTO12_shadow_intermed_4 <= V_D_PC31DOWNTO12_shadow_intermed_3;
V_D_PC31DOWNTO12_shadow_intermed_5 <= V_D_PC31DOWNTO12_shadow_intermed_4;
V_D_PC31DOWNTO12_shadow_intermed_6 <= V_D_PC31DOWNTO12_shadow_intermed_5;
V_D_PC31DOWNTO12_shadow_intermed_7 <= V_D_PC31DOWNTO12_shadow_intermed_6;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO12_shadow;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_5;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO12_shadow;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_4;
EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_1 <= EX_ADD_RES32DOWNTO330DOWNTO11_shadow;
RIN_F_PC31DOWNTO12_intermed_1 <= RIN.F.PC( 31 DOWNTO 12 );
RIN_F_PC31DOWNTO12_intermed_2 <= RIN_F_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_1 <= R.D.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_2 <= R_D_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_3 <= R_D_PC31DOWNTO12_intermed_2;
R_D_PC31DOWNTO12_intermed_4 <= R_D_PC31DOWNTO12_intermed_3;
R_D_PC31DOWNTO12_intermed_5 <= R_D_PC31DOWNTO12_intermed_4;
R_D_PC31DOWNTO12_intermed_6 <= R_D_PC31DOWNTO12_intermed_5;
R_A_CTRL_PC31DOWNTO12_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 12 );
R_A_CTRL_PC31DOWNTO12_intermed_2 <= R_A_CTRL_PC31DOWNTO12_intermed_1;
R_A_CTRL_PC31DOWNTO12_intermed_3 <= R_A_CTRL_PC31DOWNTO12_intermed_2;
R_A_CTRL_PC31DOWNTO12_intermed_4 <= R_A_CTRL_PC31DOWNTO12_intermed_3;
R_A_CTRL_PC31DOWNTO12_intermed_5 <= R_A_CTRL_PC31DOWNTO12_intermed_4;
R_E_CTRL_PC31DOWNTO12_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 12 );
R_E_CTRL_PC31DOWNTO12_intermed_2 <= R_E_CTRL_PC31DOWNTO12_intermed_1;
R_E_CTRL_PC31DOWNTO12_intermed_3 <= R_E_CTRL_PC31DOWNTO12_intermed_2;
R_E_CTRL_PC31DOWNTO12_intermed_4 <= R_E_CTRL_PC31DOWNTO12_intermed_3;
RIN_X_CTRL_PC31DOWNTO12_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 12 );
RIN_X_CTRL_PC31DOWNTO12_intermed_2 <= RIN_X_CTRL_PC31DOWNTO12_intermed_1;
RIN_X_CTRL_PC31DOWNTO12_intermed_3 <= RIN_X_CTRL_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_1 <= RIN.D.PC( 31 DOWNTO 12 );
RIN_D_PC31DOWNTO12_intermed_2 <= RIN_D_PC31DOWNTO12_intermed_1;
RIN_D_PC31DOWNTO12_intermed_3 <= RIN_D_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_4 <= RIN_D_PC31DOWNTO12_intermed_3;
RIN_D_PC31DOWNTO12_intermed_5 <= RIN_D_PC31DOWNTO12_intermed_4;
RIN_D_PC31DOWNTO12_intermed_6 <= RIN_D_PC31DOWNTO12_intermed_5;
RIN_D_PC31DOWNTO12_intermed_7 <= RIN_D_PC31DOWNTO12_intermed_6;
VIR_ADDR31DOWNTO12_shadow_intermed_1 <= VIR_ADDR31DOWNTO12_shadow;
VIR_ADDR31DOWNTO12_shadow_intermed_2 <= VIR_ADDR31DOWNTO12_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO12_shadow;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_D_INST0_shadow_intermed_1 <= V_D_INST0_shadow;
R_D_INST0_intermed_1 <= R.D.INST( 0 );
RIN_D_INST0_intermed_1 <= RIN.D.INST( 0 );
RIN_D_INST0_intermed_2 <= RIN_D_INST0_intermed_1;
V_D_INST1_shadow_intermed_1 <= V_D_INST1_shadow;
RIN_D_INST1_intermed_1 <= RIN.D.INST( 1 );
RIN_D_INST1_intermed_2 <= RIN_D_INST1_intermed_1;
R_D_INST1_intermed_1 <= R.D.INST( 1 );
V_X_DATA03_shadow_intermed_1 <= V_X_DATA03_shadow;
V_X_DATA03_shadow_intermed_2 <= V_X_DATA03_shadow_intermed_1;
V_X_DATA03_shadow_intermed_1 <= V_X_DATA03_shadow;
DCO_DATA03_intermed_1 <= DCO.DATA ( 0 )( 3 );
RIN_X_DATA03_intermed_1 <= RIN.X.DATA ( 0 )( 3 );
R_X_DATA03_intermed_1 <= R.X.DATA( 0 )( 3 );
R_X_DATA03_intermed_2 <= R_X_DATA03_intermed_1;
RIN_X_DATA03_intermed_1 <= RIN.X.DATA( 0 )( 3 );
RIN_X_DATA03_intermed_2 <= RIN_X_DATA03_intermed_1;
V_X_DATA03_shadow_intermed_1 <= V_X_DATA03_shadow;
R_X_DATA03_intermed_1 <= R.X.DATA( 0 )( 3 );
RIN_X_DATA03_intermed_1 <= RIN.X.DATA( 0 )( 3 );
RIN_X_DATA03_intermed_2 <= RIN_X_DATA03_intermed_1;
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST ( 20 );
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST( 20 );
RIN_A_CTRL_INST20_intermed_2 <= RIN_A_CTRL_INST20_intermed_1;
DE_INST20_shadow_intermed_1 <= DE_INST20_shadow;
DE_INST20_shadow_intermed_2 <= DE_INST20_shadow_intermed_1;
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
V_A_CTRL_INST20_shadow_intermed_2 <= V_A_CTRL_INST20_shadow_intermed_1;
R_A_CTRL_INST20_intermed_1 <= R.A.CTRL.INST( 20 );
R_A_CTRL_INST20_intermed_2 <= R_A_CTRL_INST20_intermed_1;
RIN_X_DATA00_intermed_1 <= RIN.X.DATA ( 0 )( 0 );
DCO_DATA00_intermed_1 <= DCO.DATA ( 0 )( 0 );
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
V_X_DATA00_shadow_intermed_2 <= V_X_DATA00_shadow_intermed_1;
RIN_X_DATA00_intermed_1 <= RIN.X.DATA( 0 )( 0 );
RIN_X_DATA00_intermed_2 <= RIN_X_DATA00_intermed_1;
R_X_DATA00_intermed_1 <= R.X.DATA( 0 )( 0 );
R_X_DATA00_intermed_2 <= R_X_DATA00_intermed_1;
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
V_X_DATA04DOWNTO0_shadow_intermed_2 <= V_X_DATA04DOWNTO0_shadow_intermed_1;
R_X_DATA04DOWNTO0_intermed_1 <= R.X.DATA( 0 )( 4 DOWNTO 0 );
R_X_DATA04DOWNTO0_intermed_2 <= R_X_DATA04DOWNTO0_intermed_1;
DCO_DATA04DOWNTO0_intermed_1 <= DCO.DATA ( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_2 <= RIN_X_DATA04DOWNTO0_intermed_1;
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA ( 0 )( 4 DOWNTO 0 );
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
V_A_CTRL_INST24_shadow_intermed_1 <= V_A_CTRL_INST24_shadow;
V_A_CTRL_INST24_shadow_intermed_2 <= V_A_CTRL_INST24_shadow_intermed_1;
DE_INST24_shadow_intermed_1 <= DE_INST24_shadow;
DE_INST24_shadow_intermed_2 <= DE_INST24_shadow_intermed_1;
R_A_CTRL_INST24_intermed_1 <= R.A.CTRL.INST( 24 );
R_A_CTRL_INST24_intermed_2 <= R_A_CTRL_INST24_intermed_1;
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST ( 24 );
V_A_CTRL_INST24_shadow_intermed_1 <= V_A_CTRL_INST24_shadow;
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST( 24 );
RIN_A_CTRL_INST24_intermed_2 <= RIN_A_CTRL_INST24_intermed_1;
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST( 20 );
RIN_A_CTRL_INST20_intermed_2 <= RIN_A_CTRL_INST20_intermed_1;
DE_INST20_shadow_intermed_1 <= DE_INST20_shadow;
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
R_A_CTRL_INST20_intermed_1 <= R.A.CTRL.INST( 20 );
V_A_CTRL_INST24_shadow_intermed_1 <= V_A_CTRL_INST24_shadow;
DE_INST24_shadow_intermed_1 <= DE_INST24_shadow;
R_A_CTRL_INST24_intermed_1 <= R.A.CTRL.INST( 24 );
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST( 24 );
RIN_A_CTRL_INST24_intermed_2 <= RIN_A_CTRL_INST24_intermed_1;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1;
R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
R_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= R_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 );
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
RIN_F_PC_intermed_1 <= RIN.F.PC;
EX_ADD_RES32DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO3_shadow;
XC_TRAP_ADDRESS_shadow_intermed_1 <= XC_TRAP_ADDRESS_shadow;
EX_JUMP_ADDRESS_shadow_intermed_1 <= EX_JUMP_ADDRESS_shadow;
V_F_PC_shadow_intermed_1 <= V_F_PC_shadow;
RIN_A_RFE1_intermed_1 <= RIN.A.RFE1;
V_A_RFE1_shadow_intermed_1 <= V_A_RFE1_shadow;
RIN_A_RFE2_intermed_1 <= RIN.A.RFE2;
V_A_RFE2_shadow_intermed_1 <= V_A_RFE2_shadow;
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
V_X_DATA0_shadow_intermed_2 <= V_X_DATA0_shadow_intermed_1;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA ( 0 );
V_E_OP1_shadow_intermed_1 <= V_E_OP1_shadow;
V_E_OP2_shadow_intermed_1 <= V_E_OP2_shadow;
RIN_E_OP2_intermed_1 <= RIN.E.OP2;
RIN_E_OP1_intermed_1 <= RIN.E.OP1;
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
V_E_ALUCIN_shadow_intermed_1 <= V_E_ALUCIN_shadow;
R_X_DATA0_intermed_1 <= R.X.DATA( 0 );
RIN_E_ALUCIN_intermed_1 <= RIN.E.ALUCIN;
DCO_DATA0_intermed_1 <= DCO.DATA ( 0 );
RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 );
RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1;
RIN_X_DATA00_intermed_1 <= RIN.X.DATA ( 0 )( 0 );
RIN_X_DATA00_intermed_2 <= RIN_X_DATA00_intermed_1;
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
DCO_DATA00_intermed_1 <= DCO.DATA ( 0 )( 0 );
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
V_X_DATA00_shadow_intermed_2 <= V_X_DATA00_shadow_intermed_1;
V_E_YMSB_shadow_intermed_1 <= V_E_YMSB_shadow;
RIN_X_DATA00_intermed_1 <= RIN.X.DATA ( 0 ) ( 0 );
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
V_X_DATA00_shadow_intermed_2 <= V_X_DATA00_shadow_intermed_1;
V_X_DATA00_shadow_intermed_3 <= V_X_DATA00_shadow_intermed_2;
R_X_DATA00_intermed_1 <= R.X.DATA ( 0 )( 0 );
RIN_X_DATA00_intermed_1 <= RIN.X.DATA( 0 )( 0 );
RIN_X_DATA00_intermed_2 <= RIN_X_DATA00_intermed_1;
RIN_X_DATA00_intermed_3 <= RIN_X_DATA00_intermed_2;
R_X_DATA00_intermed_1 <= R.X.DATA( 0 )( 0 );
R_X_DATA00_intermed_2 <= R_X_DATA00_intermed_1;
RIN_E_YMSB_intermed_1 <= RIN.E.YMSB;
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
V_X_DATA0_shadow_intermed_2 <= V_X_DATA0_shadow_intermed_1;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA ( 0 );
V_E_OP1_shadow_intermed_1 <= V_E_OP1_shadow;
RIN_E_OP1_intermed_1 <= RIN.E.OP1;
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
R_X_DATA0_intermed_1 <= R.X.DATA( 0 );
DCO_DATA0_intermed_1 <= DCO.DATA ( 0 );
RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 );
RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1;
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
V_X_DATA0_shadow_intermed_2 <= V_X_DATA0_shadow_intermed_1;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA ( 0 );
V_E_OP2_shadow_intermed_1 <= V_E_OP2_shadow;
RIN_E_OP2_intermed_1 <= RIN.E.OP2;
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
R_X_DATA0_intermed_1 <= R.X.DATA( 0 );
DCO_DATA0_intermed_1 <= DCO.DATA ( 0 );
RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 );
RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1;
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA ( 0 ) ( 4 DOWNTO 0 );
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
V_X_DATA04DOWNTO0_shadow_intermed_2 <= V_X_DATA04DOWNTO0_shadow_intermed_1;
V_X_DATA04DOWNTO0_shadow_intermed_3 <= V_X_DATA04DOWNTO0_shadow_intermed_2;
R_X_DATA04DOWNTO0_intermed_1 <= R.X.DATA( 0 )( 4 DOWNTO 0 );
R_X_DATA04DOWNTO0_intermed_2 <= R_X_DATA04DOWNTO0_intermed_1;
V_E_SHCNT_shadow_intermed_1 <= V_E_SHCNT_shadow;
R_X_DATA04DOWNTO0_intermed_1 <= R.X.DATA ( 0 )( 4 DOWNTO 0 );
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_2 <= RIN_X_DATA04DOWNTO0_intermed_1;
RIN_X_DATA04DOWNTO0_intermed_3 <= RIN_X_DATA04DOWNTO0_intermed_2;
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA ( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_2 <= RIN_X_DATA04DOWNTO0_intermed_1;
DCO_DATA04DOWNTO0_intermed_1 <= DCO.DATA ( 0 )( 4 DOWNTO 0 );
RIN_E_SHCNT_intermed_1 <= RIN.E.SHCNT;
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
V_X_DATA04DOWNTO0_shadow_intermed_2 <= V_X_DATA04DOWNTO0_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
DE_INST19_shadow_intermed_2 <= DE_INST19_shadow_intermed_1;
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
V_A_CTRL_INST20_shadow_intermed_2 <= V_A_CTRL_INST20_shadow_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_A_CTRL_INST19_shadow_intermed_3 <= V_A_CTRL_INST19_shadow_intermed_2;
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST ( 20 );
RIN_A_CTRL_INST20_intermed_2 <= RIN_A_CTRL_INST20_intermed_1;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
V_X_DATA031_shadow_intermed_3 <= V_X_DATA031_shadow_intermed_2;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_CTRL_INST19_shadow_intermed_2 <= V_E_CTRL_INST19_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
RIN_X_DATA031_intermed_3 <= RIN_X_DATA031_intermed_2;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 ) ( 31 );
V_E_SARI_shadow_intermed_1 <= V_E_SARI_shadow;
R_E_CTRL_INST19_intermed_1 <= R.E.CTRL.INST( 19 );
DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 );
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
R_X_DATA031_intermed_2 <= R_X_DATA031_intermed_1;
RIN_E_CTRL_INST20_intermed_1 <= RIN.E.CTRL.INST ( 20 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
R_E_CTRL_INST20_intermed_1 <= R.E.CTRL.INST( 20 );
R_A_CTRL_INST20_intermed_1 <= R.A.CTRL.INST ( 20 );
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST( 20 );
RIN_A_CTRL_INST20_intermed_2 <= RIN_A_CTRL_INST20_intermed_1;
RIN_A_CTRL_INST20_intermed_3 <= RIN_A_CTRL_INST20_intermed_2;
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
R_A_CTRL_INST19_intermed_2 <= R_A_CTRL_INST19_intermed_1;
V_E_CTRL_INST20_shadow_intermed_1 <= V_E_CTRL_INST20_shadow;
V_E_CTRL_INST20_shadow_intermed_2 <= V_E_CTRL_INST20_shadow_intermed_1;
V_E_CTRL_INST20_shadow_intermed_1 <= V_E_CTRL_INST20_shadow;
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST ( 19 );
DE_INST20_shadow_intermed_1 <= DE_INST20_shadow;
DE_INST20_shadow_intermed_2 <= DE_INST20_shadow_intermed_1;
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
RIN_A_CTRL_INST19_intermed_3 <= RIN_A_CTRL_INST19_intermed_2;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST ( 19 );
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
V_A_CTRL_INST20_shadow_intermed_2 <= V_A_CTRL_INST20_shadow_intermed_1;
V_A_CTRL_INST20_shadow_intermed_3 <= V_A_CTRL_INST20_shadow_intermed_2;
R_X_DATA031_intermed_1 <= R.X.DATA ( 0 )( 31 );
RIN_E_SARI_intermed_1 <= RIN.E.SARI;
RIN_E_CTRL_INST20_intermed_1 <= RIN.E.CTRL.INST( 20 );
RIN_E_CTRL_INST20_intermed_2 <= RIN_E_CTRL_INST20_intermed_1;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST( 19 );
RIN_E_CTRL_INST19_intermed_2 <= RIN_E_CTRL_INST19_intermed_1;
R_A_CTRL_INST20_intermed_1 <= R.A.CTRL.INST( 20 );
R_A_CTRL_INST20_intermed_2 <= R_A_CTRL_INST20_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_M_DCI_SIGNED_shadow_intermed_1 <= V_M_DCI_SIGNED_shadow;
V_M_DCI_SIGNED_shadow_intermed_2 <= V_M_DCI_SIGNED_shadow_intermed_1;
RIN_M_DCI_SIGNED_intermed_1 <= RIN.M.DCI.SIGNED;
RIN_M_DCI_SIGNED_intermed_2 <= RIN_M_DCI_SIGNED_intermed_1;
R_M_DCI_SIGNED_intermed_1 <= R.M.DCI.SIGNED;
V_X_DCI_SIGNED_shadow_intermed_1 <= V_X_DCI_SIGNED_shadow;
RIN_X_DCI_SIGNED_intermed_1 <= RIN.X.DCI.SIGNED;
RIN_M_DCI_SIZE_intermed_1 <= RIN.M.DCI.SIZE;
RIN_M_DCI_SIZE_intermed_2 <= RIN_M_DCI_SIZE_intermed_1;
V_M_DCI_SIZE_shadow_intermed_1 <= V_M_DCI_SIZE_shadow;
V_M_DCI_SIZE_shadow_intermed_2 <= V_M_DCI_SIZE_shadow_intermed_1;
R_M_DCI_SIZE_intermed_1 <= R.M.DCI.SIZE;
V_X_DCI_SIZE_shadow_intermed_1 <= V_X_DCI_SIZE_shadow;
RIN_X_DCI_SIZE_intermed_1 <= RIN.X.DCI.SIZE;
V_M_RESULT1DOWNTO0_shadow_intermed_1 <= V_M_RESULT1DOWNTO0_shadow;
V_M_RESULT1DOWNTO0_shadow_intermed_2 <= V_M_RESULT1DOWNTO0_shadow_intermed_1;
V_M_RESULT1DOWNTO0_shadow_intermed_3 <= V_M_RESULT1DOWNTO0_shadow_intermed_2;
RIN_X_LADDR_intermed_1 <= RIN.X.LADDR;
R_M_RESULT1DOWNTO0_intermed_1 <= R.M.RESULT ( 1 DOWNTO 0 );
RIN_M_RESULT1DOWNTO0_intermed_1 <= RIN.M.RESULT ( 1 DOWNTO 0 );
RIN_M_RESULT1DOWNTO0_intermed_2 <= RIN_M_RESULT1DOWNTO0_intermed_1;
RIN_M_RESULT1DOWNTO0_intermed_1 <= RIN.M.RESULT( 1 DOWNTO 0 );
RIN_M_RESULT1DOWNTO0_intermed_2 <= RIN_M_RESULT1DOWNTO0_intermed_1;
RIN_M_RESULT1DOWNTO0_intermed_3 <= RIN_M_RESULT1DOWNTO0_intermed_2;
V_M_RESULT1DOWNTO0_shadow_intermed_1 <= V_M_RESULT1DOWNTO0_shadow;
V_M_RESULT1DOWNTO0_shadow_intermed_2 <= V_M_RESULT1DOWNTO0_shadow_intermed_1;
V_X_LADDR_shadow_intermed_1 <= V_X_LADDR_shadow;
R_M_RESULT1DOWNTO0_intermed_1 <= R.M.RESULT( 1 DOWNTO 0 );
R_M_RESULT1DOWNTO0_intermed_2 <= R_M_RESULT1DOWNTO0_intermed_1;
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
V_X_DATA0_shadow_intermed_2 <= V_X_DATA0_shadow_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
RIN_X_RESULT_intermed_1 <= RIN.X.RESULT;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA ( 0 );
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC ( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
V_X_RESULT_shadow_intermed_1 <= V_X_RESULT_shadow;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC ( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC ( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC ( 31 DOWNTO 2 );
R_X_DATA0_intermed_1 <= R.X.DATA( 0 );
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC ( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC ( 31 DOWNTO 2 );
DCO_DATA0_intermed_1 <= DCO.DATA ( 0 );
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 );
RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
V_X_ANNUL_ALL_shadow_intermed_2 <= V_X_ANNUL_ALL_shadow_intermed_1;
V_X_ANNUL_ALL_shadow_intermed_3 <= V_X_ANNUL_ALL_shadow_intermed_2;
V_X_ANNUL_ALL_shadow_intermed_4 <= V_X_ANNUL_ALL_shadow_intermed_3;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2;
RIN_A_CTRL_ANNUL_intermed_4 <= RIN_A_CTRL_ANNUL_intermed_3;
RIN_A_CTRL_ANNUL_intermed_5 <= RIN_A_CTRL_ANNUL_intermed_4;
R_M_CTRL_WREG_intermed_1 <= R.M.CTRL.WREG;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1;
R_A_CTRL_ANNUL_intermed_3 <= R_A_CTRL_ANNUL_intermed_2;
R_A_CTRL_ANNUL_intermed_4 <= R_A_CTRL_ANNUL_intermed_3;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
RIN_X_ANNUL_ALL_intermed_3 <= RIN_X_ANNUL_ALL_intermed_2;
RIN_X_ANNUL_ALL_intermed_4 <= RIN_X_ANNUL_ALL_intermed_3;
RIN_X_ANNUL_ALL_intermed_5 <= RIN_X_ANNUL_ALL_intermed_4;
V_M_CTRL_WREG_shadow_intermed_1 <= V_M_CTRL_WREG_shadow;
V_M_CTRL_WREG_shadow_intermed_2 <= V_M_CTRL_WREG_shadow_intermed_1;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
R_X_ANNUL_ALL_intermed_2 <= R_X_ANNUL_ALL_intermed_1;
R_X_ANNUL_ALL_intermed_3 <= R_X_ANNUL_ALL_intermed_2;
R_X_ANNUL_ALL_intermed_4 <= R_X_ANNUL_ALL_intermed_3;
V_X_CTRL_WREG_shadow_intermed_1 <= V_X_CTRL_WREG_shadow;
R_E_CTRL_WREG_intermed_1 <= R.E.CTRL.WREG;
R_E_CTRL_WREG_intermed_2 <= R_E_CTRL_WREG_intermed_1;
RIN_X_CTRL_WREG_intermed_1 <= RIN.X.CTRL.WREG;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_3 <= V_A_CTRL_ANNUL_shadow_intermed_2;
V_A_CTRL_ANNUL_shadow_intermed_4 <= V_A_CTRL_ANNUL_shadow_intermed_3;
RIN_E_CTRL_WREG_intermed_1 <= RIN.E.CTRL.WREG;
RIN_E_CTRL_WREG_intermed_2 <= RIN_E_CTRL_WREG_intermed_1;
RIN_E_CTRL_WREG_intermed_3 <= RIN_E_CTRL_WREG_intermed_2;
RIN_M_CTRL_WREG_intermed_1 <= RIN.M.CTRL.WREG;
RIN_M_CTRL_WREG_intermed_2 <= RIN_M_CTRL_WREG_intermed_1;
V_E_CTRL_WREG_shadow_intermed_1 <= V_E_CTRL_WREG_shadow;
V_E_CTRL_WREG_shadow_intermed_2 <= V_E_CTRL_WREG_shadow_intermed_1;
V_E_CTRL_WREG_shadow_intermed_3 <= V_E_CTRL_WREG_shadow_intermed_2;
RIN_A_CTRL_WREG_intermed_1 <= RIN.A.CTRL.WREG;
RIN_A_CTRL_WREG_intermed_2 <= RIN_A_CTRL_WREG_intermed_1;
RIN_A_CTRL_WREG_intermed_3 <= RIN_A_CTRL_WREG_intermed_2;
RIN_A_CTRL_WREG_intermed_4 <= RIN_A_CTRL_WREG_intermed_3;
V_A_CTRL_WREG_shadow_intermed_1 <= V_A_CTRL_WREG_shadow;
V_A_CTRL_WREG_shadow_intermed_2 <= V_A_CTRL_WREG_shadow_intermed_1;
V_A_CTRL_WREG_shadow_intermed_3 <= V_A_CTRL_WREG_shadow_intermed_2;
V_A_CTRL_WREG_shadow_intermed_4 <= V_A_CTRL_WREG_shadow_intermed_3;
R_A_CTRL_WREG_intermed_1 <= R.A.CTRL.WREG;
R_A_CTRL_WREG_intermed_2 <= R_A_CTRL_WREG_intermed_1;
R_A_CTRL_WREG_intermed_3 <= R_A_CTRL_WREG_intermed_2;
V_E_CTRL_TT_shadow_intermed_1 <= V_E_CTRL_TT_shadow;
V_E_CTRL_TT_shadow_intermed_2 <= V_E_CTRL_TT_shadow_intermed_1;
V_E_CTRL_TT_shadow_intermed_3 <= V_E_CTRL_TT_shadow_intermed_2;
V_X_CTRL_TT_shadow_intermed_1 <= V_X_CTRL_TT_shadow;
V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow;
V_X_RESULT6DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO0_shadow_intermed_1;
RIN_A_CTRL_TT_intermed_1 <= RIN.A.CTRL.TT;
RIN_A_CTRL_TT_intermed_2 <= RIN_A_CTRL_TT_intermed_1;
RIN_A_CTRL_TT_intermed_3 <= RIN_A_CTRL_TT_intermed_2;
RIN_A_CTRL_TT_intermed_4 <= RIN_A_CTRL_TT_intermed_3;
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 );
RIN_X_RESULT6DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO0_intermed_1;
RIN_E_CTRL_TT_intermed_1 <= RIN.E.CTRL.TT;
RIN_E_CTRL_TT_intermed_2 <= RIN_E_CTRL_TT_intermed_1;
RIN_E_CTRL_TT_intermed_3 <= RIN_E_CTRL_TT_intermed_2;
V_M_CTRL_TT_shadow_intermed_1 <= V_M_CTRL_TT_shadow;
V_M_CTRL_TT_shadow_intermed_2 <= V_M_CTRL_TT_shadow_intermed_1;
R_X_RESULT6DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 );
R_A_CTRL_TT_intermed_1 <= R.A.CTRL.TT;
R_A_CTRL_TT_intermed_2 <= R_A_CTRL_TT_intermed_1;
R_A_CTRL_TT_intermed_3 <= R_A_CTRL_TT_intermed_2;
V_A_CTRL_TT_shadow_intermed_1 <= V_A_CTRL_TT_shadow;
V_A_CTRL_TT_shadow_intermed_2 <= V_A_CTRL_TT_shadow_intermed_1;
V_A_CTRL_TT_shadow_intermed_3 <= V_A_CTRL_TT_shadow_intermed_2;
V_A_CTRL_TT_shadow_intermed_4 <= V_A_CTRL_TT_shadow_intermed_3;
R_M_CTRL_TT_intermed_1 <= R.M.CTRL.TT;
RIN_X_CTRL_TT_intermed_1 <= RIN.X.CTRL.TT;
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 );
R_E_CTRL_TT_intermed_1 <= R.E.CTRL.TT;
R_E_CTRL_TT_intermed_2 <= R_E_CTRL_TT_intermed_1;
RIN_M_CTRL_TT_intermed_1 <= RIN.M.CTRL.TT;
RIN_M_CTRL_TT_intermed_2 <= RIN_M_CTRL_TT_intermed_1;
V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow;
V_M_CTRL_TRAP_shadow_intermed_1 <= V_M_CTRL_TRAP_shadow;
V_M_CTRL_TRAP_shadow_intermed_2 <= V_M_CTRL_TRAP_shadow_intermed_1;
RIN_X_CTRL_TRAP_intermed_1 <= RIN.X.CTRL.TRAP;
V_X_CTRL_TRAP_shadow_intermed_1 <= V_X_CTRL_TRAP_shadow;
V_A_CTRL_TRAP_shadow_intermed_1 <= V_A_CTRL_TRAP_shadow;
V_A_CTRL_TRAP_shadow_intermed_2 <= V_A_CTRL_TRAP_shadow_intermed_1;
V_A_CTRL_TRAP_shadow_intermed_3 <= V_A_CTRL_TRAP_shadow_intermed_2;
V_A_CTRL_TRAP_shadow_intermed_4 <= V_A_CTRL_TRAP_shadow_intermed_3;
V_X_MEXC_shadow_intermed_1 <= V_X_MEXC_shadow;
V_D_MEXC_shadow_intermed_1 <= V_D_MEXC_shadow;
V_D_MEXC_shadow_intermed_2 <= V_D_MEXC_shadow_intermed_1;
V_D_MEXC_shadow_intermed_3 <= V_D_MEXC_shadow_intermed_2;
V_D_MEXC_shadow_intermed_4 <= V_D_MEXC_shadow_intermed_3;
V_D_MEXC_shadow_intermed_5 <= V_D_MEXC_shadow_intermed_4;
R_A_CTRL_TRAP_intermed_1 <= R.A.CTRL.TRAP;
R_A_CTRL_TRAP_intermed_2 <= R_A_CTRL_TRAP_intermed_1;
R_A_CTRL_TRAP_intermed_3 <= R_A_CTRL_TRAP_intermed_2;
RIN_X_MEXC_intermed_1 <= RIN.X.MEXC;
RIN_M_CTRL_TRAP_intermed_1 <= RIN.M.CTRL.TRAP;
RIN_M_CTRL_TRAP_intermed_2 <= RIN_M_CTRL_TRAP_intermed_1;
R_M_CTRL_TRAP_intermed_1 <= R.M.CTRL.TRAP;
ICO_MEXC_intermed_1 <= ICO.MEXC;
ICO_MEXC_intermed_2 <= ICO_MEXC_intermed_1;
ICO_MEXC_intermed_3 <= ICO_MEXC_intermed_2;
ICO_MEXC_intermed_4 <= ICO_MEXC_intermed_3;
ICO_MEXC_intermed_5 <= ICO_MEXC_intermed_4;
R_E_CTRL_TRAP_intermed_1 <= R.E.CTRL.TRAP;
R_E_CTRL_TRAP_intermed_2 <= R_E_CTRL_TRAP_intermed_1;
RIN_A_CTRL_TRAP_intermed_1 <= RIN.A.CTRL.TRAP;
RIN_A_CTRL_TRAP_intermed_2 <= RIN_A_CTRL_TRAP_intermed_1;
RIN_A_CTRL_TRAP_intermed_3 <= RIN_A_CTRL_TRAP_intermed_2;
RIN_A_CTRL_TRAP_intermed_4 <= RIN_A_CTRL_TRAP_intermed_3;
V_E_CTRL_TRAP_shadow_intermed_1 <= V_E_CTRL_TRAP_shadow;
V_E_CTRL_TRAP_shadow_intermed_2 <= V_E_CTRL_TRAP_shadow_intermed_1;
V_E_CTRL_TRAP_shadow_intermed_3 <= V_E_CTRL_TRAP_shadow_intermed_2;
RIN_E_CTRL_TRAP_intermed_1 <= RIN.E.CTRL.TRAP;
RIN_E_CTRL_TRAP_intermed_2 <= RIN_E_CTRL_TRAP_intermed_1;
RIN_E_CTRL_TRAP_intermed_3 <= RIN_E_CTRL_TRAP_intermed_2;
RIN_D_MEXC_intermed_1 <= RIN.D.MEXC;
RIN_D_MEXC_intermed_2 <= RIN_D_MEXC_intermed_1;
RIN_D_MEXC_intermed_3 <= RIN_D_MEXC_intermed_2;
RIN_D_MEXC_intermed_4 <= RIN_D_MEXC_intermed_3;
RIN_D_MEXC_intermed_5 <= RIN_D_MEXC_intermed_4;
R_D_MEXC_intermed_1 <= R.D.MEXC;
R_D_MEXC_intermed_2 <= R_D_MEXC_intermed_1;
R_D_MEXC_intermed_3 <= R_D_MEXC_intermed_2;
R_D_MEXC_intermed_4 <= R_D_MEXC_intermed_3;
DCO_MEXC_intermed_1 <= DCO.MEXC;
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_CTRL_INST19_shadow_intermed_2 <= V_E_CTRL_INST19_shadow_intermed_1;
R_E_CTRL_INST19_intermed_1 <= R.E.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 );
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST ( 19 );
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST( 19 );
RIN_E_CTRL_INST19_intermed_2 <= RIN_E_CTRL_INST19_intermed_1;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
VP_ERROR_shadow_intermed_1 <= VP_ERROR_shadow;
RPIN_PWD_intermed_1 <= RPIN.PWD;
V_X_DEBUG_shadow_intermed_1 <= V_X_DEBUG_shadow;
VP_PWD_shadow_intermed_1 <= VP_PWD_shadow;
RPIN_ERROR_intermed_1 <= RPIN.ERROR;
RIN_X_DEBUG_intermed_1 <= RIN.X.DEBUG;
VP_ERROR_shadow_intermed_1 <= VP_ERROR_shadow;
RIN_X_NERROR_intermed_1 <= RIN.X.NERROR;
RPIN_ERROR_intermed_1 <= RPIN.ERROR;
V_F_PC31DOWNTO4_shadow_intermed_1 <= V_F_PC31DOWNTO4_shadow;
V_X_CTRL_TT_shadow_intermed_1 <= V_X_CTRL_TT_shadow;
V_E_CTRL_TT_shadow_intermed_1 <= V_E_CTRL_TT_shadow;
V_E_CTRL_TT_shadow_intermed_2 <= V_E_CTRL_TT_shadow_intermed_1;
V_E_CTRL_TT_shadow_intermed_3 <= V_E_CTRL_TT_shadow_intermed_2;
RIN_A_CTRL_TT_intermed_1 <= RIN.A.CTRL.TT;
RIN_A_CTRL_TT_intermed_2 <= RIN_A_CTRL_TT_intermed_1;
RIN_A_CTRL_TT_intermed_3 <= RIN_A_CTRL_TT_intermed_2;
RIN_A_CTRL_TT_intermed_4 <= RIN_A_CTRL_TT_intermed_3;
V_X_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO4_shadow;
V_X_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO4_shadow_intermed_2;
IR_ADDR31DOWNTO4_intermed_1 <= IR.ADDR( 31 DOWNTO 4 );
R_A_CTRL_TT_intermed_1 <= R.A.CTRL.TT;
R_A_CTRL_TT_intermed_2 <= R_A_CTRL_TT_intermed_1;
R_A_CTRL_TT_intermed_3 <= R_A_CTRL_TT_intermed_2;
R_M_CTRL_TT_intermed_1 <= R.M.CTRL.TT;
RIN_F_PC31DOWNTO4_intermed_1 <= RIN.F.PC( 31 DOWNTO 4 );
VIR_ADDR31DOWNTO4_shadow_intermed_1 <= VIR_ADDR31DOWNTO4_shadow;
VIR_ADDR31DOWNTO4_shadow_intermed_2 <= VIR_ADDR31DOWNTO4_shadow_intermed_1;
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 );
R_E_CTRL_TT_intermed_1 <= R.E.CTRL.TT;
R_E_CTRL_TT_intermed_2 <= R_E_CTRL_TT_intermed_1;
R_A_CTRL_PC31DOWNTO4_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 4 );
R_A_CTRL_PC31DOWNTO4_intermed_2 <= R_A_CTRL_PC31DOWNTO4_intermed_1;
R_A_CTRL_PC31DOWNTO4_intermed_3 <= R_A_CTRL_PC31DOWNTO4_intermed_2;
R_A_CTRL_PC31DOWNTO4_intermed_4 <= R_A_CTRL_PC31DOWNTO4_intermed_3;
R_A_CTRL_PC31DOWNTO4_intermed_5 <= R_A_CTRL_PC31DOWNTO4_intermed_4;
RIN_A_CTRL_PC31DOWNTO4_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 4 );
RIN_A_CTRL_PC31DOWNTO4_intermed_2 <= RIN_A_CTRL_PC31DOWNTO4_intermed_1;
RIN_A_CTRL_PC31DOWNTO4_intermed_3 <= RIN_A_CTRL_PC31DOWNTO4_intermed_2;
RIN_A_CTRL_PC31DOWNTO4_intermed_4 <= RIN_A_CTRL_PC31DOWNTO4_intermed_3;
RIN_A_CTRL_PC31DOWNTO4_intermed_5 <= RIN_A_CTRL_PC31DOWNTO4_intermed_4;
RIN_A_CTRL_PC31DOWNTO4_intermed_6 <= RIN_A_CTRL_PC31DOWNTO4_intermed_5;
R_D_PC31DOWNTO4_intermed_1 <= R.D.PC( 31 DOWNTO 4 );
R_D_PC31DOWNTO4_intermed_2 <= R_D_PC31DOWNTO4_intermed_1;
R_D_PC31DOWNTO4_intermed_3 <= R_D_PC31DOWNTO4_intermed_2;
R_D_PC31DOWNTO4_intermed_4 <= R_D_PC31DOWNTO4_intermed_3;
R_D_PC31DOWNTO4_intermed_5 <= R_D_PC31DOWNTO4_intermed_4;
R_D_PC31DOWNTO4_intermed_6 <= R_D_PC31DOWNTO4_intermed_5;
RIN_X_CTRL_PC31DOWNTO4_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 4 );
RIN_X_CTRL_PC31DOWNTO4_intermed_2 <= RIN_X_CTRL_PC31DOWNTO4_intermed_1;
RIN_X_CTRL_PC31DOWNTO4_intermed_3 <= RIN_X_CTRL_PC31DOWNTO4_intermed_2;
EX_ADD_RES32DOWNTO332DOWNTO5_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO5_shadow;
V_W_S_TBA_shadow_intermed_1 <= V_W_S_TBA_shadow;
RIN_M_CTRL_TT_intermed_1 <= RIN.M.CTRL.TT;
RIN_M_CTRL_TT_intermed_2 <= RIN_M_CTRL_TT_intermed_1;
RIN_M_CTRL_PC31DOWNTO4_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 4 );
RIN_M_CTRL_PC31DOWNTO4_intermed_2 <= RIN_M_CTRL_PC31DOWNTO4_intermed_1;
RIN_M_CTRL_PC31DOWNTO4_intermed_3 <= RIN_M_CTRL_PC31DOWNTO4_intermed_2;
RIN_M_CTRL_PC31DOWNTO4_intermed_4 <= RIN_M_CTRL_PC31DOWNTO4_intermed_3;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO4_shadow;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_4;
V_D_PC31DOWNTO4_shadow_intermed_1 <= V_D_PC31DOWNTO4_shadow;
V_D_PC31DOWNTO4_shadow_intermed_2 <= V_D_PC31DOWNTO4_shadow_intermed_1;
V_D_PC31DOWNTO4_shadow_intermed_3 <= V_D_PC31DOWNTO4_shadow_intermed_2;
V_D_PC31DOWNTO4_shadow_intermed_4 <= V_D_PC31DOWNTO4_shadow_intermed_3;
V_D_PC31DOWNTO4_shadow_intermed_5 <= V_D_PC31DOWNTO4_shadow_intermed_4;
V_D_PC31DOWNTO4_shadow_intermed_6 <= V_D_PC31DOWNTO4_shadow_intermed_5;
V_D_PC31DOWNTO4_shadow_intermed_7 <= V_D_PC31DOWNTO4_shadow_intermed_6;
V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow;
R_X_CTRL_PC31DOWNTO4_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 4 );
R_X_CTRL_PC31DOWNTO4_intermed_2 <= R_X_CTRL_PC31DOWNTO4_intermed_1;
V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow;
V_X_RESULT6DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO0_shadow_intermed_1;
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 );
RIN_X_RESULT6DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO0_intermed_1;
RIN_E_CTRL_TT_intermed_1 <= RIN.E.CTRL.TT;
RIN_E_CTRL_TT_intermed_2 <= RIN_E_CTRL_TT_intermed_1;
RIN_E_CTRL_TT_intermed_3 <= RIN_E_CTRL_TT_intermed_2;
R_X_RESULT6DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 );
V_M_CTRL_TT_shadow_intermed_1 <= V_M_CTRL_TT_shadow;
V_M_CTRL_TT_shadow_intermed_2 <= V_M_CTRL_TT_shadow_intermed_1;
IRIN_ADDR31DOWNTO4_intermed_1 <= IRIN.ADDR( 31 DOWNTO 4 );
IRIN_ADDR31DOWNTO4_intermed_2 <= IRIN_ADDR31DOWNTO4_intermed_1;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO4_shadow;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_3;
V_A_CTRL_TT_shadow_intermed_1 <= V_A_CTRL_TT_shadow;
V_A_CTRL_TT_shadow_intermed_2 <= V_A_CTRL_TT_shadow_intermed_1;
V_A_CTRL_TT_shadow_intermed_3 <= V_A_CTRL_TT_shadow_intermed_2;
V_A_CTRL_TT_shadow_intermed_4 <= V_A_CTRL_TT_shadow_intermed_3;
XC_TRAP_ADDRESS31DOWNTO4_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO4_shadow;
R_M_CTRL_PC31DOWNTO4_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 4 );
R_M_CTRL_PC31DOWNTO4_intermed_2 <= R_M_CTRL_PC31DOWNTO4_intermed_1;
R_M_CTRL_PC31DOWNTO4_intermed_3 <= R_M_CTRL_PC31DOWNTO4_intermed_2;
RIN_X_CTRL_TT_intermed_1 <= RIN.X.CTRL.TT;
RIN_D_PC31DOWNTO4_intermed_1 <= RIN.D.PC( 31 DOWNTO 4 );
RIN_D_PC31DOWNTO4_intermed_2 <= RIN_D_PC31DOWNTO4_intermed_1;
RIN_D_PC31DOWNTO4_intermed_3 <= RIN_D_PC31DOWNTO4_intermed_2;
RIN_D_PC31DOWNTO4_intermed_4 <= RIN_D_PC31DOWNTO4_intermed_3;
RIN_D_PC31DOWNTO4_intermed_5 <= RIN_D_PC31DOWNTO4_intermed_4;
RIN_D_PC31DOWNTO4_intermed_6 <= RIN_D_PC31DOWNTO4_intermed_5;
RIN_D_PC31DOWNTO4_intermed_7 <= RIN_D_PC31DOWNTO4_intermed_6;
RIN_E_CTRL_PC31DOWNTO4_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 4 );
RIN_E_CTRL_PC31DOWNTO4_intermed_2 <= RIN_E_CTRL_PC31DOWNTO4_intermed_1;
RIN_E_CTRL_PC31DOWNTO4_intermed_3 <= RIN_E_CTRL_PC31DOWNTO4_intermed_2;
RIN_E_CTRL_PC31DOWNTO4_intermed_4 <= RIN_E_CTRL_PC31DOWNTO4_intermed_3;
RIN_E_CTRL_PC31DOWNTO4_intermed_5 <= RIN_E_CTRL_PC31DOWNTO4_intermed_4;
EX_JUMP_ADDRESS31DOWNTO4_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO4_shadow;
RIN_W_S_TBA_intermed_1 <= RIN.W.S.TBA;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO4_shadow;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_5;
R_E_CTRL_PC31DOWNTO4_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 4 );
R_E_CTRL_PC31DOWNTO4_intermed_2 <= R_E_CTRL_PC31DOWNTO4_intermed_1;
R_E_CTRL_PC31DOWNTO4_intermed_3 <= R_E_CTRL_PC31DOWNTO4_intermed_2;
R_E_CTRL_PC31DOWNTO4_intermed_4 <= R_E_CTRL_PC31DOWNTO4_intermed_3;
R_D_PC3DOWNTO2_intermed_1 <= R.D.PC( 3 DOWNTO 2 );
R_D_PC3DOWNTO2_intermed_2 <= R_D_PC3DOWNTO2_intermed_1;
R_D_PC3DOWNTO2_intermed_3 <= R_D_PC3DOWNTO2_intermed_2;
R_D_PC3DOWNTO2_intermed_4 <= R_D_PC3DOWNTO2_intermed_3;
R_D_PC3DOWNTO2_intermed_5 <= R_D_PC3DOWNTO2_intermed_4;
R_D_PC3DOWNTO2_intermed_6 <= R_D_PC3DOWNTO2_intermed_5;
V_D_PC3DOWNTO2_shadow_intermed_1 <= V_D_PC3DOWNTO2_shadow;
V_D_PC3DOWNTO2_shadow_intermed_2 <= V_D_PC3DOWNTO2_shadow_intermed_1;
V_D_PC3DOWNTO2_shadow_intermed_3 <= V_D_PC3DOWNTO2_shadow_intermed_2;
V_D_PC3DOWNTO2_shadow_intermed_4 <= V_D_PC3DOWNTO2_shadow_intermed_3;
V_D_PC3DOWNTO2_shadow_intermed_5 <= V_D_PC3DOWNTO2_shadow_intermed_4;
V_D_PC3DOWNTO2_shadow_intermed_6 <= V_D_PC3DOWNTO2_shadow_intermed_5;
V_D_PC3DOWNTO2_shadow_intermed_7 <= V_D_PC3DOWNTO2_shadow_intermed_6;
VIR_ADDR3DOWNTO2_shadow_intermed_1 <= VIR_ADDR3DOWNTO2_shadow;
VIR_ADDR3DOWNTO2_shadow_intermed_2 <= VIR_ADDR3DOWNTO2_shadow_intermed_1;
RIN_D_PC3DOWNTO2_intermed_1 <= RIN.D.PC( 3 DOWNTO 2 );
RIN_D_PC3DOWNTO2_intermed_2 <= RIN_D_PC3DOWNTO2_intermed_1;
RIN_D_PC3DOWNTO2_intermed_3 <= RIN_D_PC3DOWNTO2_intermed_2;
RIN_D_PC3DOWNTO2_intermed_4 <= RIN_D_PC3DOWNTO2_intermed_3;
RIN_D_PC3DOWNTO2_intermed_5 <= RIN_D_PC3DOWNTO2_intermed_4;
RIN_D_PC3DOWNTO2_intermed_6 <= RIN_D_PC3DOWNTO2_intermed_5;
RIN_D_PC3DOWNTO2_intermed_7 <= RIN_D_PC3DOWNTO2_intermed_6;
R_M_CTRL_PC3DOWNTO2_intermed_1 <= R.M.CTRL.PC( 3 DOWNTO 2 );
R_M_CTRL_PC3DOWNTO2_intermed_2 <= R_M_CTRL_PC3DOWNTO2_intermed_1;
R_M_CTRL_PC3DOWNTO2_intermed_3 <= R_M_CTRL_PC3DOWNTO2_intermed_2;
R_E_CTRL_PC3DOWNTO2_intermed_1 <= R.E.CTRL.PC( 3 DOWNTO 2 );
R_E_CTRL_PC3DOWNTO2_intermed_2 <= R_E_CTRL_PC3DOWNTO2_intermed_1;
R_E_CTRL_PC3DOWNTO2_intermed_3 <= R_E_CTRL_PC3DOWNTO2_intermed_2;
R_E_CTRL_PC3DOWNTO2_intermed_4 <= R_E_CTRL_PC3DOWNTO2_intermed_3;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC3DOWNTO2_shadow;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_3;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_4;
RIN_X_CTRL_PC3DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 3 DOWNTO 2 );
RIN_X_CTRL_PC3DOWNTO2_intermed_2 <= RIN_X_CTRL_PC3DOWNTO2_intermed_1;
RIN_X_CTRL_PC3DOWNTO2_intermed_3 <= RIN_X_CTRL_PC3DOWNTO2_intermed_2;
R_A_CTRL_PC3DOWNTO2_intermed_1 <= R.A.CTRL.PC( 3 DOWNTO 2 );
R_A_CTRL_PC3DOWNTO2_intermed_2 <= R_A_CTRL_PC3DOWNTO2_intermed_1;
R_A_CTRL_PC3DOWNTO2_intermed_3 <= R_A_CTRL_PC3DOWNTO2_intermed_2;
R_A_CTRL_PC3DOWNTO2_intermed_4 <= R_A_CTRL_PC3DOWNTO2_intermed_3;
R_A_CTRL_PC3DOWNTO2_intermed_5 <= R_A_CTRL_PC3DOWNTO2_intermed_4;
V_X_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC3DOWNTO2_shadow;
V_X_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC3DOWNTO2_shadow_intermed_2;
RIN_M_CTRL_PC3DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 3 DOWNTO 2 );
RIN_M_CTRL_PC3DOWNTO2_intermed_2 <= RIN_M_CTRL_PC3DOWNTO2_intermed_1;
RIN_M_CTRL_PC3DOWNTO2_intermed_3 <= RIN_M_CTRL_PC3DOWNTO2_intermed_2;
RIN_M_CTRL_PC3DOWNTO2_intermed_4 <= RIN_M_CTRL_PC3DOWNTO2_intermed_3;
IRIN_ADDR3DOWNTO2_intermed_1 <= IRIN.ADDR( 3 DOWNTO 2 );
IRIN_ADDR3DOWNTO2_intermed_2 <= IRIN_ADDR3DOWNTO2_intermed_1;
EX_JUMP_ADDRESS3DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS3DOWNTO2_shadow;
EX_ADD_RES32DOWNTO34DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO34DOWNTO3_shadow;
RIN_A_CTRL_PC3DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 3 DOWNTO 2 );
RIN_A_CTRL_PC3DOWNTO2_intermed_2 <= RIN_A_CTRL_PC3DOWNTO2_intermed_1;
RIN_A_CTRL_PC3DOWNTO2_intermed_3 <= RIN_A_CTRL_PC3DOWNTO2_intermed_2;
RIN_A_CTRL_PC3DOWNTO2_intermed_4 <= RIN_A_CTRL_PC3DOWNTO2_intermed_3;
RIN_A_CTRL_PC3DOWNTO2_intermed_5 <= RIN_A_CTRL_PC3DOWNTO2_intermed_4;
RIN_A_CTRL_PC3DOWNTO2_intermed_6 <= RIN_A_CTRL_PC3DOWNTO2_intermed_5;
XC_TRAP_ADDRESS3DOWNTO2_shadow_intermed_1 <= XC_TRAP_ADDRESS3DOWNTO2_shadow;
V_F_PC3DOWNTO2_shadow_intermed_1 <= V_F_PC3DOWNTO2_shadow;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC3DOWNTO2_shadow;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_4;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_5;
IR_ADDR3DOWNTO2_intermed_1 <= IR.ADDR( 3 DOWNTO 2 );
V_M_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC3DOWNTO2_shadow;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_2;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_3;
R_X_CTRL_PC3DOWNTO2_intermed_1 <= R.X.CTRL.PC( 3 DOWNTO 2 );
R_X_CTRL_PC3DOWNTO2_intermed_2 <= R_X_CTRL_PC3DOWNTO2_intermed_1;
RIN_E_CTRL_PC3DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 3 DOWNTO 2 );
RIN_E_CTRL_PC3DOWNTO2_intermed_2 <= RIN_E_CTRL_PC3DOWNTO2_intermed_1;
RIN_E_CTRL_PC3DOWNTO2_intermed_3 <= RIN_E_CTRL_PC3DOWNTO2_intermed_2;
RIN_E_CTRL_PC3DOWNTO2_intermed_4 <= RIN_E_CTRL_PC3DOWNTO2_intermed_3;
RIN_E_CTRL_PC3DOWNTO2_intermed_5 <= RIN_E_CTRL_PC3DOWNTO2_intermed_4;
RIN_F_PC3DOWNTO2_intermed_1 <= RIN.F.PC( 3 DOWNTO 2 );
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_DEBUG_intermed_1 <= RIN.X.DEBUG;
RIN_D_PC_intermed_1 <= RIN.D.PC;
RIN_D_PC_intermed_2 <= RIN_D_PC_intermed_1;
RIN_D_PC_intermed_3 <= RIN_D_PC_intermed_2;
RIN_D_PC_intermed_4 <= RIN_D_PC_intermed_3;
RIN_D_PC_intermed_5 <= RIN_D_PC_intermed_4;
RIN_A_CTRL_PC_intermed_1 <= RIN.A.CTRL.PC;
RIN_A_CTRL_PC_intermed_2 <= RIN_A_CTRL_PC_intermed_1;
RIN_A_CTRL_PC_intermed_3 <= RIN_A_CTRL_PC_intermed_2;
RIN_A_CTRL_PC_intermed_4 <= RIN_A_CTRL_PC_intermed_3;
R_A_CTRL_PC_intermed_1 <= R.A.CTRL.PC;
R_A_CTRL_PC_intermed_2 <= R_A_CTRL_PC_intermed_1;
R_A_CTRL_PC_intermed_3 <= R_A_CTRL_PC_intermed_2;
V_E_CTRL_PC_shadow_intermed_1 <= V_E_CTRL_PC_shadow;
V_E_CTRL_PC_shadow_intermed_2 <= V_E_CTRL_PC_shadow_intermed_1;
V_E_CTRL_PC_shadow_intermed_3 <= V_E_CTRL_PC_shadow_intermed_2;
R_M_CTRL_PC_intermed_1 <= R.M.CTRL.PC;
R_E_CTRL_PC_intermed_1 <= R.E.CTRL.PC;
R_E_CTRL_PC_intermed_2 <= R_E_CTRL_PC_intermed_1;
RIN_M_CTRL_PC_intermed_1 <= RIN.M.CTRL.PC;
RIN_M_CTRL_PC_intermed_2 <= RIN_M_CTRL_PC_intermed_1;
V_X_CTRL_PC_shadow_intermed_1 <= V_X_CTRL_PC_shadow;
V_M_CTRL_PC_shadow_intermed_1 <= V_M_CTRL_PC_shadow;
V_M_CTRL_PC_shadow_intermed_2 <= V_M_CTRL_PC_shadow_intermed_1;
V_A_CTRL_PC_shadow_intermed_1 <= V_A_CTRL_PC_shadow;
V_A_CTRL_PC_shadow_intermed_2 <= V_A_CTRL_PC_shadow_intermed_1;
V_A_CTRL_PC_shadow_intermed_3 <= V_A_CTRL_PC_shadow_intermed_2;
V_A_CTRL_PC_shadow_intermed_4 <= V_A_CTRL_PC_shadow_intermed_3;
R_D_PC_intermed_1 <= R.D.PC;
R_D_PC_intermed_2 <= R_D_PC_intermed_1;
R_D_PC_intermed_3 <= R_D_PC_intermed_2;
R_D_PC_intermed_4 <= R_D_PC_intermed_3;
RIN_E_CTRL_PC_intermed_1 <= RIN.E.CTRL.PC;
RIN_E_CTRL_PC_intermed_2 <= RIN_E_CTRL_PC_intermed_1;
RIN_E_CTRL_PC_intermed_3 <= RIN_E_CTRL_PC_intermed_2;
RIN_X_CTRL_PC_intermed_1 <= RIN.X.CTRL.PC;
V_D_PC_shadow_intermed_1 <= V_D_PC_shadow;
V_D_PC_shadow_intermed_2 <= V_D_PC_shadow_intermed_1;
V_D_PC_shadow_intermed_3 <= V_D_PC_shadow_intermed_2;
V_D_PC_shadow_intermed_4 <= V_D_PC_shadow_intermed_3;
V_D_PC_shadow_intermed_5 <= V_D_PC_shadow_intermed_4;
IRIN_ADDR_intermed_1 <= IRIN.ADDR;
V_E_CTRL_TT_shadow_intermed_1 <= V_E_CTRL_TT_shadow;
V_E_CTRL_TT_shadow_intermed_2 <= V_E_CTRL_TT_shadow_intermed_1;
V_E_CTRL_TT_shadow_intermed_3 <= V_E_CTRL_TT_shadow_intermed_2;
V_X_CTRL_TT_shadow_intermed_1 <= V_X_CTRL_TT_shadow;
RIN_A_CTRL_TT_intermed_1 <= RIN.A.CTRL.TT;
RIN_A_CTRL_TT_intermed_2 <= RIN_A_CTRL_TT_intermed_1;
RIN_A_CTRL_TT_intermed_3 <= RIN_A_CTRL_TT_intermed_2;
RIN_A_CTRL_TT_intermed_4 <= RIN_A_CTRL_TT_intermed_3;
R_A_CTRL_TT_intermed_1 <= R.A.CTRL.TT;
R_A_CTRL_TT_intermed_2 <= R_A_CTRL_TT_intermed_1;
R_A_CTRL_TT_intermed_3 <= R_A_CTRL_TT_intermed_2;
R_M_CTRL_TT_intermed_1 <= R.M.CTRL.TT;
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 );
DSUIN_TT_intermed_1 <= DSUIN.TT;
R_E_CTRL_TT_intermed_1 <= R.E.CTRL.TT;
R_E_CTRL_TT_intermed_2 <= R_E_CTRL_TT_intermed_1;
RIN_M_CTRL_TT_intermed_1 <= RIN.M.CTRL.TT;
RIN_M_CTRL_TT_intermed_2 <= RIN_M_CTRL_TT_intermed_1;
V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow;
V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow;
V_X_RESULT6DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO0_shadow_intermed_1;
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 );
RIN_X_RESULT6DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO0_intermed_1;
RIN_E_CTRL_TT_intermed_1 <= RIN.E.CTRL.TT;
RIN_E_CTRL_TT_intermed_2 <= RIN_E_CTRL_TT_intermed_1;
RIN_E_CTRL_TT_intermed_3 <= RIN_E_CTRL_TT_intermed_2;
V_M_CTRL_TT_shadow_intermed_1 <= V_M_CTRL_TT_shadow;
V_M_CTRL_TT_shadow_intermed_2 <= V_M_CTRL_TT_shadow_intermed_1;
R_X_RESULT6DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 );
V_A_CTRL_TT_shadow_intermed_1 <= V_A_CTRL_TT_shadow;
V_A_CTRL_TT_shadow_intermed_2 <= V_A_CTRL_TT_shadow_intermed_1;
V_A_CTRL_TT_shadow_intermed_3 <= V_A_CTRL_TT_shadow_intermed_2;
V_A_CTRL_TT_shadow_intermed_4 <= V_A_CTRL_TT_shadow_intermed_3;
RIN_X_CTRL_TT_intermed_1 <= RIN.X.CTRL.TT;
RPIN_PWD_intermed_1 <= RPIN.PWD;
IRIN_PWD_intermed_1 <= IRIN.PWD;
V_E_CTRL_TT_shadow_intermed_1 <= V_E_CTRL_TT_shadow;
V_E_CTRL_TT_shadow_intermed_2 <= V_E_CTRL_TT_shadow_intermed_1;
V_E_CTRL_TT_shadow_intermed_3 <= V_E_CTRL_TT_shadow_intermed_2;
V_X_CTRL_TT_shadow_intermed_1 <= V_X_CTRL_TT_shadow;
RIN_A_CTRL_TT_intermed_1 <= RIN.A.CTRL.TT;
RIN_A_CTRL_TT_intermed_2 <= RIN_A_CTRL_TT_intermed_1;
RIN_A_CTRL_TT_intermed_3 <= RIN_A_CTRL_TT_intermed_2;
RIN_A_CTRL_TT_intermed_4 <= RIN_A_CTRL_TT_intermed_3;
R_A_CTRL_TT_intermed_1 <= R.A.CTRL.TT;
R_A_CTRL_TT_intermed_2 <= R_A_CTRL_TT_intermed_1;
R_A_CTRL_TT_intermed_3 <= R_A_CTRL_TT_intermed_2;
R_M_CTRL_TT_intermed_1 <= R.M.CTRL.TT;
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 );
R_E_CTRL_TT_intermed_1 <= R.E.CTRL.TT;
R_E_CTRL_TT_intermed_2 <= R_E_CTRL_TT_intermed_1;
RIN_M_CTRL_TT_intermed_1 <= RIN.M.CTRL.TT;
RIN_M_CTRL_TT_intermed_2 <= RIN_M_CTRL_TT_intermed_1;
V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow;
V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow;
V_X_RESULT6DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO0_shadow_intermed_1;
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 );
RIN_X_RESULT6DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO0_intermed_1;
RIN_E_CTRL_TT_intermed_1 <= RIN.E.CTRL.TT;
RIN_E_CTRL_TT_intermed_2 <= RIN_E_CTRL_TT_intermed_1;
RIN_E_CTRL_TT_intermed_3 <= RIN_E_CTRL_TT_intermed_2;
V_M_CTRL_TT_shadow_intermed_1 <= V_M_CTRL_TT_shadow;
V_M_CTRL_TT_shadow_intermed_2 <= V_M_CTRL_TT_shadow_intermed_1;
R_X_RESULT6DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 );
RIN_W_S_TT_intermed_1 <= RIN.W.S.TT;
V_A_CTRL_TT_shadow_intermed_1 <= V_A_CTRL_TT_shadow;
V_A_CTRL_TT_shadow_intermed_2 <= V_A_CTRL_TT_shadow_intermed_1;
V_A_CTRL_TT_shadow_intermed_3 <= V_A_CTRL_TT_shadow_intermed_2;
V_A_CTRL_TT_shadow_intermed_4 <= V_A_CTRL_TT_shadow_intermed_3;
RIN_X_CTRL_TT_intermed_1 <= RIN.X.CTRL.TT;
RIN_W_S_S_intermed_1 <= RIN.W.S.S;
RIN_W_S_PS_intermed_1 <= RIN.W.S.PS;
V_W_S_S_shadow_intermed_1 <= V_W_S_S_shadow;
RIN_W_S_S_intermed_1 <= RIN.W.S.S;
RIN_E_CTRL_RD6DOWNTO0_intermed_1 <= RIN.E.CTRL.RD( 6 DOWNTO 0 );
RIN_E_CTRL_RD6DOWNTO0_intermed_2 <= RIN_E_CTRL_RD6DOWNTO0_intermed_1;
RIN_E_CTRL_RD6DOWNTO0_intermed_3 <= RIN_E_CTRL_RD6DOWNTO0_intermed_2;
RIN_M_CTRL_RD6DOWNTO0_intermed_1 <= RIN.M.CTRL.RD( 6 DOWNTO 0 );
RIN_M_CTRL_RD6DOWNTO0_intermed_2 <= RIN_M_CTRL_RD6DOWNTO0_intermed_1;
RIN_X_CTRL_RD6DOWNTO0_intermed_1 <= RIN.X.CTRL.RD( 6 DOWNTO 0 );
V_X_CTRL_RD6DOWNTO0_shadow_intermed_1 <= V_X_CTRL_RD6DOWNTO0_shadow;
RIN_W_S_CWP_intermed_1 <= RIN.W.S.CWP;
V_M_CTRL_RD6DOWNTO0_shadow_intermed_1 <= V_M_CTRL_RD6DOWNTO0_shadow;
V_M_CTRL_RD6DOWNTO0_shadow_intermed_2 <= V_M_CTRL_RD6DOWNTO0_shadow_intermed_1;
R_E_CTRL_RD6DOWNTO0_intermed_1 <= R.E.CTRL.RD( 6 DOWNTO 0 );
R_E_CTRL_RD6DOWNTO0_intermed_2 <= R_E_CTRL_RD6DOWNTO0_intermed_1;
V_E_CTRL_RD6DOWNTO0_shadow_intermed_1 <= V_E_CTRL_RD6DOWNTO0_shadow;
V_E_CTRL_RD6DOWNTO0_shadow_intermed_2 <= V_E_CTRL_RD6DOWNTO0_shadow_intermed_1;
V_E_CTRL_RD6DOWNTO0_shadow_intermed_3 <= V_E_CTRL_RD6DOWNTO0_shadow_intermed_2;
V_A_CTRL_RD6DOWNTO0_shadow_intermed_1 <= V_A_CTRL_RD6DOWNTO0_shadow;
V_A_CTRL_RD6DOWNTO0_shadow_intermed_2 <= V_A_CTRL_RD6DOWNTO0_shadow_intermed_1;
V_A_CTRL_RD6DOWNTO0_shadow_intermed_3 <= V_A_CTRL_RD6DOWNTO0_shadow_intermed_2;
V_A_CTRL_RD6DOWNTO0_shadow_intermed_4 <= V_A_CTRL_RD6DOWNTO0_shadow_intermed_3;
R_A_CTRL_RD6DOWNTO0_intermed_1 <= R.A.CTRL.RD( 6 DOWNTO 0 );
R_A_CTRL_RD6DOWNTO0_intermed_2 <= R_A_CTRL_RD6DOWNTO0_intermed_1;
R_A_CTRL_RD6DOWNTO0_intermed_3 <= R_A_CTRL_RD6DOWNTO0_intermed_2;
RIN_A_CTRL_RD6DOWNTO0_intermed_1 <= RIN.A.CTRL.RD( 6 DOWNTO 0 );
RIN_A_CTRL_RD6DOWNTO0_intermed_2 <= RIN_A_CTRL_RD6DOWNTO0_intermed_1;
RIN_A_CTRL_RD6DOWNTO0_intermed_3 <= RIN_A_CTRL_RD6DOWNTO0_intermed_2;
RIN_A_CTRL_RD6DOWNTO0_intermed_4 <= RIN_A_CTRL_RD6DOWNTO0_intermed_3;
R_M_CTRL_RD6DOWNTO0_intermed_1 <= R.M.CTRL.RD( 6 DOWNTO 0 );
V_W_S_CWP_shadow_intermed_1 <= V_W_S_CWP_shadow;
RIN_W_S_ET_intermed_1 <= RIN.W.S.ET;
RIN_W_S_CWP_intermed_1 <= RIN.W.S.CWP;
RPIN_ERROR_intermed_1 <= RPIN.ERROR;
RIN_D_PC_intermed_1 <= RIN.D.PC;
RIN_D_PC_intermed_2 <= RIN_D_PC_intermed_1;
RIN_D_PC_intermed_3 <= RIN_D_PC_intermed_2;
RIN_D_PC_intermed_4 <= RIN_D_PC_intermed_3;
RIN_D_PC_intermed_5 <= RIN_D_PC_intermed_4;
RIN_D_PC_intermed_6 <= RIN_D_PC_intermed_5;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_4 <= RIN_M_CTRL_PC31DOWNTO2_intermed_3;
VIR_ADDR_shadow_intermed_1 <= VIR_ADDR_shadow;
RIN_A_CTRL_PC_intermed_1 <= RIN.A.CTRL.PC;
RIN_A_CTRL_PC_intermed_2 <= RIN_A_CTRL_PC_intermed_1;
RIN_A_CTRL_PC_intermed_3 <= RIN_A_CTRL_PC_intermed_2;
RIN_A_CTRL_PC_intermed_4 <= RIN_A_CTRL_PC_intermed_3;
RIN_A_CTRL_PC_intermed_5 <= RIN_A_CTRL_PC_intermed_4;
R_A_CTRL_PC_intermed_1 <= R.A.CTRL.PC;
R_A_CTRL_PC_intermed_2 <= R_A_CTRL_PC_intermed_1;
R_A_CTRL_PC_intermed_3 <= R_A_CTRL_PC_intermed_2;
R_A_CTRL_PC_intermed_4 <= R_A_CTRL_PC_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
V_D_PC31DOWNTO2_shadow_intermed_6 <= V_D_PC31DOWNTO2_shadow_intermed_5;
V_D_PC31DOWNTO2_shadow_intermed_7 <= V_D_PC31DOWNTO2_shadow_intermed_6;
V_E_CTRL_PC_shadow_intermed_1 <= V_E_CTRL_PC_shadow;
V_E_CTRL_PC_shadow_intermed_2 <= V_E_CTRL_PC_shadow_intermed_1;
V_E_CTRL_PC_shadow_intermed_3 <= V_E_CTRL_PC_shadow_intermed_2;
V_E_CTRL_PC_shadow_intermed_4 <= V_E_CTRL_PC_shadow_intermed_3;
EX_ADD_RES32DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO3_shadow;
XC_TRAP_ADDRESS_shadow_intermed_1 <= XC_TRAP_ADDRESS_shadow;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_D_PC31DOWNTO2_intermed_6 <= RIN_D_PC31DOWNTO2_intermed_5;
RIN_D_PC31DOWNTO2_intermed_7 <= RIN_D_PC31DOWNTO2_intermed_6;
EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow;
V_F_PC31DOWNTO2_shadow_intermed_1 <= V_F_PC31DOWNTO2_shadow;
RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC( 31 DOWNTO 2 );
R_M_CTRL_PC_intermed_1 <= R.M.CTRL.PC;
R_M_CTRL_PC_intermed_2 <= R_M_CTRL_PC_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_3 <= RIN_X_CTRL_PC31DOWNTO2_intermed_2;
R_X_CTRL_PC_intermed_1 <= R.X.CTRL.PC;
R_E_CTRL_PC_intermed_1 <= R.E.CTRL.PC;
R_E_CTRL_PC_intermed_2 <= R_E_CTRL_PC_intermed_1;
R_E_CTRL_PC_intermed_3 <= R_E_CTRL_PC_intermed_2;
IRIN_ADDR31DOWNTO2_intermed_1 <= IRIN.ADDR( 31 DOWNTO 2 );
IRIN_ADDR31DOWNTO2_intermed_2 <= IRIN_ADDR31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_5;
RIN_M_CTRL_PC_intermed_1 <= RIN.M.CTRL.PC;
RIN_M_CTRL_PC_intermed_2 <= RIN_M_CTRL_PC_intermed_1;
RIN_M_CTRL_PC_intermed_3 <= RIN_M_CTRL_PC_intermed_2;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_D_PC31DOWNTO2_intermed_5 <= R_D_PC31DOWNTO2_intermed_4;
R_D_PC31DOWNTO2_intermed_6 <= R_D_PC31DOWNTO2_intermed_5;
VIR_ADDR31DOWNTO2_shadow_intermed_1 <= VIR_ADDR31DOWNTO2_shadow;
VIR_ADDR31DOWNTO2_shadow_intermed_2 <= VIR_ADDR31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC_shadow_intermed_1 <= V_X_CTRL_PC_shadow;
V_X_CTRL_PC_shadow_intermed_2 <= V_X_CTRL_PC_shadow_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_3 <= R_M_CTRL_PC31DOWNTO2_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_6 <= RIN_A_CTRL_PC31DOWNTO2_intermed_5;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
R_A_CTRL_PC31DOWNTO2_intermed_5 <= R_A_CTRL_PC31DOWNTO2_intermed_4;
V_M_CTRL_PC_shadow_intermed_1 <= V_M_CTRL_PC_shadow;
V_M_CTRL_PC_shadow_intermed_2 <= V_M_CTRL_PC_shadow_intermed_1;
V_M_CTRL_PC_shadow_intermed_3 <= V_M_CTRL_PC_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC_shadow_intermed_1 <= V_A_CTRL_PC_shadow;
V_A_CTRL_PC_shadow_intermed_2 <= V_A_CTRL_PC_shadow_intermed_1;
V_A_CTRL_PC_shadow_intermed_3 <= V_A_CTRL_PC_shadow_intermed_2;
V_A_CTRL_PC_shadow_intermed_4 <= V_A_CTRL_PC_shadow_intermed_3;
V_A_CTRL_PC_shadow_intermed_5 <= V_A_CTRL_PC_shadow_intermed_4;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
R_X_CTRL_PC31DOWNTO2_intermed_2 <= R_X_CTRL_PC31DOWNTO2_intermed_1;
R_D_PC_intermed_1 <= R.D.PC;
R_D_PC_intermed_2 <= R_D_PC_intermed_1;
R_D_PC_intermed_3 <= R_D_PC_intermed_2;
R_D_PC_intermed_4 <= R_D_PC_intermed_3;
R_D_PC_intermed_5 <= R_D_PC_intermed_4;
RIN_F_PC_intermed_1 <= RIN.F.PC;
XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO2_shadow;
RIN_E_CTRL_PC_intermed_1 <= RIN.E.CTRL.PC;
RIN_E_CTRL_PC_intermed_2 <= RIN_E_CTRL_PC_intermed_1;
RIN_E_CTRL_PC_intermed_3 <= RIN_E_CTRL_PC_intermed_2;
RIN_E_CTRL_PC_intermed_4 <= RIN_E_CTRL_PC_intermed_3;
RIN_X_CTRL_PC_intermed_1 <= RIN.X.CTRL.PC;
RIN_X_CTRL_PC_intermed_2 <= RIN_X_CTRL_PC_intermed_1;
V_D_PC_shadow_intermed_1 <= V_D_PC_shadow;
V_D_PC_shadow_intermed_2 <= V_D_PC_shadow_intermed_1;
V_D_PC_shadow_intermed_3 <= V_D_PC_shadow_intermed_2;
V_D_PC_shadow_intermed_4 <= V_D_PC_shadow_intermed_3;
V_D_PC_shadow_intermed_5 <= V_D_PC_shadow_intermed_4;
V_D_PC_shadow_intermed_6 <= V_D_PC_shadow_intermed_5;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_4 <= R_E_CTRL_PC31DOWNTO2_intermed_3;
IRIN_ADDR_intermed_1 <= IRIN.ADDR;
EX_JUMP_ADDRESS_shadow_intermed_1 <= EX_JUMP_ADDRESS_shadow;
EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO2_shadow;
IR_ADDR31DOWNTO2_intermed_1 <= IR.ADDR( 31 DOWNTO 2 );
V_F_PC_shadow_intermed_1 <= V_F_PC_shadow;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_5 <= RIN_E_CTRL_PC31DOWNTO2_intermed_4;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_2;
DSUIN_TBUFCNT_intermed_1 <= DSUIN.TBUFCNT;
RIN_W_EXCEPT_intermed_1 <= RIN.W.EXCEPT;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_X_RESULT_intermed_1 <= RIN.X.RESULT;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC ( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC ( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC ( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC ( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC ( 31 DOWNTO 2 );
DCO_DATA0_intermed_1 <= DCO.DATA ( 0 );
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
V_X_DATA0_shadow_intermed_2 <= V_X_DATA0_shadow_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA ( 0 );
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC ( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
V_X_RESULT_shadow_intermed_1 <= V_X_RESULT_shadow;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
RIN_W_RESULT_intermed_1 <= RIN.W.RESULT;
R_X_DATA0_intermed_1 <= R.X.DATA( 0 );
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 );
RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1;
V_M_CTRL_RD7DOWNTO0_shadow_intermed_1 <= V_M_CTRL_RD7DOWNTO0_shadow;
V_M_CTRL_RD7DOWNTO0_shadow_intermed_2 <= V_M_CTRL_RD7DOWNTO0_shadow_intermed_1;
V_E_CTRL_RD7DOWNTO0_shadow_intermed_1 <= V_E_CTRL_RD7DOWNTO0_shadow;
V_E_CTRL_RD7DOWNTO0_shadow_intermed_2 <= V_E_CTRL_RD7DOWNTO0_shadow_intermed_1;
V_E_CTRL_RD7DOWNTO0_shadow_intermed_3 <= V_E_CTRL_RD7DOWNTO0_shadow_intermed_2;
R_E_CTRL_RD7DOWNTO0_intermed_1 <= R.E.CTRL.RD ( 7 DOWNTO 0 );
R_E_CTRL_RD7DOWNTO0_intermed_2 <= R_E_CTRL_RD7DOWNTO0_intermed_1;
V_X_CTRL_RD7DOWNTO0_shadow_intermed_1 <= V_X_CTRL_RD7DOWNTO0_shadow;
V_A_CTRL_RD7DOWNTO0_shadow_intermed_1 <= V_A_CTRL_RD7DOWNTO0_shadow;
V_A_CTRL_RD7DOWNTO0_shadow_intermed_2 <= V_A_CTRL_RD7DOWNTO0_shadow_intermed_1;
V_A_CTRL_RD7DOWNTO0_shadow_intermed_3 <= V_A_CTRL_RD7DOWNTO0_shadow_intermed_2;
V_A_CTRL_RD7DOWNTO0_shadow_intermed_4 <= V_A_CTRL_RD7DOWNTO0_shadow_intermed_3;
RIN_W_WA_intermed_1 <= RIN.W.WA;
RIN_A_CTRL_RD7DOWNTO0_intermed_1 <= RIN.A.CTRL.RD ( 7 DOWNTO 0 );
RIN_A_CTRL_RD7DOWNTO0_intermed_2 <= RIN_A_CTRL_RD7DOWNTO0_intermed_1;
RIN_A_CTRL_RD7DOWNTO0_intermed_3 <= RIN_A_CTRL_RD7DOWNTO0_intermed_2;
RIN_A_CTRL_RD7DOWNTO0_intermed_4 <= RIN_A_CTRL_RD7DOWNTO0_intermed_3;
R_M_CTRL_RD7DOWNTO0_intermed_1 <= R.M.CTRL.RD ( 7 DOWNTO 0 );
R_A_CTRL_RD7DOWNTO0_intermed_1 <= R.A.CTRL.RD ( 7 DOWNTO 0 );
R_A_CTRL_RD7DOWNTO0_intermed_2 <= R_A_CTRL_RD7DOWNTO0_intermed_1;
R_A_CTRL_RD7DOWNTO0_intermed_3 <= R_A_CTRL_RD7DOWNTO0_intermed_2;
RIN_E_CTRL_RD7DOWNTO0_intermed_1 <= RIN.E.CTRL.RD ( 7 DOWNTO 0 );
RIN_E_CTRL_RD7DOWNTO0_intermed_2 <= RIN_E_CTRL_RD7DOWNTO0_intermed_1;
RIN_E_CTRL_RD7DOWNTO0_intermed_3 <= RIN_E_CTRL_RD7DOWNTO0_intermed_2;
RIN_X_CTRL_RD7DOWNTO0_intermed_1 <= RIN.X.CTRL.RD ( 7 DOWNTO 0 );
RIN_M_CTRL_RD7DOWNTO0_intermed_1 <= RIN.M.CTRL.RD ( 7 DOWNTO 0 );
RIN_M_CTRL_RD7DOWNTO0_intermed_2 <= RIN_M_CTRL_RD7DOWNTO0_intermed_1;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2;
RIN_A_CTRL_ANNUL_intermed_4 <= RIN_A_CTRL_ANNUL_intermed_3;
RIN_A_CTRL_ANNUL_intermed_5 <= RIN_A_CTRL_ANNUL_intermed_4;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1;
R_A_CTRL_ANNUL_intermed_3 <= R_A_CTRL_ANNUL_intermed_2;
R_A_CTRL_ANNUL_intermed_4 <= R_A_CTRL_ANNUL_intermed_3;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
R_X_ANNUL_ALL_intermed_2 <= R_X_ANNUL_ALL_intermed_1;
R_X_ANNUL_ALL_intermed_3 <= R_X_ANNUL_ALL_intermed_2;
R_X_ANNUL_ALL_intermed_4 <= R_X_ANNUL_ALL_intermed_3;
V_X_CTRL_WREG_shadow_intermed_1 <= V_X_CTRL_WREG_shadow;
RIN_X_CTRL_WREG_intermed_1 <= RIN.X.CTRL.WREG;
RIN_M_CTRL_WREG_intermed_1 <= RIN.M.CTRL.WREG;
RIN_M_CTRL_WREG_intermed_2 <= RIN_M_CTRL_WREG_intermed_1;
RIN_A_CTRL_WREG_intermed_1 <= RIN.A.CTRL.WREG;
RIN_A_CTRL_WREG_intermed_2 <= RIN_A_CTRL_WREG_intermed_1;
RIN_A_CTRL_WREG_intermed_3 <= RIN_A_CTRL_WREG_intermed_2;
RIN_A_CTRL_WREG_intermed_4 <= RIN_A_CTRL_WREG_intermed_3;
V_A_CTRL_WREG_shadow_intermed_1 <= V_A_CTRL_WREG_shadow;
V_A_CTRL_WREG_shadow_intermed_2 <= V_A_CTRL_WREG_shadow_intermed_1;
V_A_CTRL_WREG_shadow_intermed_3 <= V_A_CTRL_WREG_shadow_intermed_2;
V_A_CTRL_WREG_shadow_intermed_4 <= V_A_CTRL_WREG_shadow_intermed_3;
R_A_CTRL_WREG_intermed_1 <= R.A.CTRL.WREG;
R_A_CTRL_WREG_intermed_2 <= R_A_CTRL_WREG_intermed_1;
R_A_CTRL_WREG_intermed_3 <= R_A_CTRL_WREG_intermed_2;
RIN_W_WREG_intermed_1 <= RIN.W.WREG;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
V_X_ANNUL_ALL_shadow_intermed_2 <= V_X_ANNUL_ALL_shadow_intermed_1;
V_X_ANNUL_ALL_shadow_intermed_3 <= V_X_ANNUL_ALL_shadow_intermed_2;
V_X_ANNUL_ALL_shadow_intermed_4 <= V_X_ANNUL_ALL_shadow_intermed_3;
R_M_CTRL_WREG_intermed_1 <= R.M.CTRL.WREG;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
RIN_X_ANNUL_ALL_intermed_3 <= RIN_X_ANNUL_ALL_intermed_2;
RIN_X_ANNUL_ALL_intermed_4 <= RIN_X_ANNUL_ALL_intermed_3;
RIN_X_ANNUL_ALL_intermed_5 <= RIN_X_ANNUL_ALL_intermed_4;
V_M_CTRL_WREG_shadow_intermed_1 <= V_M_CTRL_WREG_shadow;
V_M_CTRL_WREG_shadow_intermed_2 <= V_M_CTRL_WREG_shadow_intermed_1;
R_E_CTRL_WREG_intermed_1 <= R.E.CTRL.WREG;
R_E_CTRL_WREG_intermed_2 <= R_E_CTRL_WREG_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_3 <= V_A_CTRL_ANNUL_shadow_intermed_2;
V_A_CTRL_ANNUL_shadow_intermed_4 <= V_A_CTRL_ANNUL_shadow_intermed_3;
RIN_E_CTRL_WREG_intermed_1 <= RIN.E.CTRL.WREG;
RIN_E_CTRL_WREG_intermed_2 <= RIN_E_CTRL_WREG_intermed_1;
RIN_E_CTRL_WREG_intermed_3 <= RIN_E_CTRL_WREG_intermed_2;
V_E_CTRL_WREG_shadow_intermed_1 <= V_E_CTRL_WREG_shadow;
V_E_CTRL_WREG_shadow_intermed_2 <= V_E_CTRL_WREG_shadow_intermed_1;
V_E_CTRL_WREG_shadow_intermed_3 <= V_E_CTRL_WREG_shadow_intermed_2;
RIN_W_S_SVT_intermed_1 <= RIN.W.S.SVT;
RIN_W_S_DWT_intermed_1 <= RIN.W.S.DWT;
RIN_W_S_EF_intermed_1 <= RIN.W.S.EF;
RIN_E_CTRL_intermed_1 <= RIN.E.CTRL;
RIN_E_CTRL_intermed_2 <= RIN_E_CTRL_intermed_1;
R_E_CTRL_intermed_1 <= R.E.CTRL;
RIN_X_CTRL_intermed_1 <= RIN.X.CTRL;
RIN_M_CTRL_intermed_1 <= RIN.M.CTRL;
V_E_CTRL_shadow_intermed_1 <= V_E_CTRL_shadow;
V_E_CTRL_shadow_intermed_2 <= V_E_CTRL_shadow_intermed_1;
RIN_A_CTRL_intermed_1 <= RIN.A.CTRL;
RIN_A_CTRL_intermed_2 <= RIN_A_CTRL_intermed_1;
RIN_A_CTRL_intermed_3 <= RIN_A_CTRL_intermed_2;
V_M_CTRL_shadow_intermed_1 <= V_M_CTRL_shadow;
V_A_CTRL_shadow_intermed_1 <= V_A_CTRL_shadow;
V_A_CTRL_shadow_intermed_2 <= V_A_CTRL_shadow_intermed_1;
V_A_CTRL_shadow_intermed_3 <= V_A_CTRL_shadow_intermed_2;
R_A_CTRL_intermed_1 <= R.A.CTRL;
R_A_CTRL_intermed_2 <= R_A_CTRL_intermed_1;
V_M_DCI_shadow_intermed_1 <= V_M_DCI_shadow;
RIN_M_DCI_intermed_1 <= RIN.M.DCI;
RIN_X_DCI_intermed_1 <= RIN.X.DCI;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2;
RIN_A_CTRL_ANNUL_intermed_4 <= RIN_A_CTRL_ANNUL_intermed_3;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1;
R_A_CTRL_ANNUL_intermed_3 <= R_A_CTRL_ANNUL_intermed_2;
RIN_M_CTRL_RETT_intermed_1 <= RIN.M.CTRL.RETT;
V_M_CTRL_ANNUL_shadow_intermed_1 <= V_M_CTRL_ANNUL_shadow;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
R_X_ANNUL_ALL_intermed_2 <= R_X_ANNUL_ALL_intermed_1;
R_X_ANNUL_ALL_intermed_3 <= R_X_ANNUL_ALL_intermed_2;
RIN_M_CTRL_ANNUL_intermed_1 <= RIN.M.CTRL.ANNUL;
V_E_CTRL_RETT_shadow_intermed_1 <= V_E_CTRL_RETT_shadow;
V_E_CTRL_RETT_shadow_intermed_2 <= V_E_CTRL_RETT_shadow_intermed_1;
V_A_CTRL_RETT_shadow_intermed_1 <= V_A_CTRL_RETT_shadow;
V_A_CTRL_RETT_shadow_intermed_2 <= V_A_CTRL_RETT_shadow_intermed_1;
V_A_CTRL_RETT_shadow_intermed_3 <= V_A_CTRL_RETT_shadow_intermed_2;
RIN_A_CTRL_RETT_intermed_1 <= RIN.A.CTRL.RETT;
RIN_A_CTRL_RETT_intermed_2 <= RIN_A_CTRL_RETT_intermed_1;
RIN_A_CTRL_RETT_intermed_3 <= RIN_A_CTRL_RETT_intermed_2;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
V_X_ANNUL_ALL_shadow_intermed_2 <= V_X_ANNUL_ALL_shadow_intermed_1;
V_X_ANNUL_ALL_shadow_intermed_3 <= V_X_ANNUL_ALL_shadow_intermed_2;
RIN_E_CTRL_ANNUL_intermed_1 <= RIN.E.CTRL.ANNUL;
RIN_E_CTRL_ANNUL_intermed_2 <= RIN_E_CTRL_ANNUL_intermed_1;
R_E_CTRL_RETT_intermed_1 <= R.E.CTRL.RETT;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
RIN_X_ANNUL_ALL_intermed_3 <= RIN_X_ANNUL_ALL_intermed_2;
RIN_X_ANNUL_ALL_intermed_4 <= RIN_X_ANNUL_ALL_intermed_3;
RIN_E_CTRL_RETT_intermed_1 <= RIN.E.CTRL.RETT;
RIN_E_CTRL_RETT_intermed_2 <= RIN_E_CTRL_RETT_intermed_1;
V_E_CTRL_ANNUL_shadow_intermed_1 <= V_E_CTRL_ANNUL_shadow;
V_E_CTRL_ANNUL_shadow_intermed_2 <= V_E_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_3 <= V_A_CTRL_ANNUL_shadow_intermed_2;
RIN_X_CTRL_RETT_intermed_1 <= RIN.X.CTRL.RETT;
V_M_CTRL_RETT_shadow_intermed_1 <= V_M_CTRL_RETT_shadow;
R_A_CTRL_RETT_intermed_1 <= R.A.CTRL.RETT;
R_A_CTRL_RETT_intermed_2 <= R_A_CTRL_RETT_intermed_1;
R_E_CTRL_ANNUL_intermed_1 <= R.E.CTRL.ANNUL;
V_E_MAC_shadow_intermed_1 <= V_E_MAC_shadow;
V_E_MAC_shadow_intermed_2 <= V_E_MAC_shadow_intermed_1;
RIN_M_MAC_intermed_1 <= RIN.M.MAC;
RIN_E_MAC_intermed_1 <= RIN.E.MAC;
RIN_E_MAC_intermed_2 <= RIN_E_MAC_intermed_1;
R_E_MAC_intermed_1 <= R.E.MAC;
V_M_MAC_shadow_intermed_1 <= V_M_MAC_shadow;
RIN_X_MAC_intermed_1 <= RIN.X.MAC;
V_M_RESULT1DOWNTO0_shadow_intermed_1 <= V_M_RESULT1DOWNTO0_shadow;
V_M_RESULT1DOWNTO0_shadow_intermed_2 <= V_M_RESULT1DOWNTO0_shadow_intermed_1;
RIN_X_LADDR_intermed_1 <= RIN.X.LADDR;
RIN_M_RESULT1DOWNTO0_intermed_1 <= RIN.M.RESULT( 1 DOWNTO 0 );
RIN_M_RESULT1DOWNTO0_intermed_2 <= RIN_M_RESULT1DOWNTO0_intermed_1;
V_M_RESULT1DOWNTO0_shadow_intermed_1 <= V_M_RESULT1DOWNTO0_shadow;
R_M_RESULT1DOWNTO0_intermed_1 <= R.M.RESULT( 1 DOWNTO 0 );
RIN_M_RESULT1DOWNTO0_intermed_1 <= RIN.M.RESULT ( 1 DOWNTO 0 );
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1;
V_M_CTRL_ANNUL_shadow_intermed_1 <= V_M_CTRL_ANNUL_shadow;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
RIN_X_CTRL_ANNUL_intermed_1 <= RIN.X.CTRL.ANNUL;
RIN_M_CTRL_ANNUL_intermed_1 <= RIN.M.CTRL.ANNUL;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
RIN_E_CTRL_ANNUL_intermed_1 <= RIN.E.CTRL.ANNUL;
RIN_E_CTRL_ANNUL_intermed_2 <= RIN_E_CTRL_ANNUL_intermed_1;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
V_E_CTRL_ANNUL_shadow_intermed_1 <= V_E_CTRL_ANNUL_shadow;
V_E_CTRL_ANNUL_shadow_intermed_2 <= V_E_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_3 <= V_A_CTRL_ANNUL_shadow_intermed_2;
R_E_CTRL_ANNUL_intermed_1 <= R.E.CTRL.ANNUL;
V_E_CTRL_TT_shadow_intermed_1 <= V_E_CTRL_TT_shadow;
V_E_CTRL_TT_shadow_intermed_2 <= V_E_CTRL_TT_shadow_intermed_1;
V_E_CTRL_TT_shadow_intermed_3 <= V_E_CTRL_TT_shadow_intermed_2;
RIN_A_CTRL_TT_intermed_1 <= RIN.A.CTRL.TT;
RIN_A_CTRL_TT_intermed_2 <= RIN_A_CTRL_TT_intermed_1;
RIN_A_CTRL_TT_intermed_3 <= RIN_A_CTRL_TT_intermed_2;
RIN_A_CTRL_TT_intermed_4 <= RIN_A_CTRL_TT_intermed_3;
R_A_CTRL_TT_intermed_1 <= R.A.CTRL.TT;
R_A_CTRL_TT_intermed_2 <= R_A_CTRL_TT_intermed_1;
R_A_CTRL_TT_intermed_3 <= R_A_CTRL_TT_intermed_2;
R_M_CTRL_TT_intermed_1 <= R.M.CTRL.TT;
R_E_CTRL_TT_intermed_1 <= R.E.CTRL.TT;
R_E_CTRL_TT_intermed_2 <= R_E_CTRL_TT_intermed_1;
RIN_M_CTRL_TT_intermed_1 <= RIN.M.CTRL.TT;
RIN_M_CTRL_TT_intermed_2 <= RIN_M_CTRL_TT_intermed_1;
RIN_E_CTRL_TT_intermed_1 <= RIN.E.CTRL.TT;
RIN_E_CTRL_TT_intermed_2 <= RIN_E_CTRL_TT_intermed_1;
RIN_E_CTRL_TT_intermed_3 <= RIN_E_CTRL_TT_intermed_2;
V_M_CTRL_TT_shadow_intermed_1 <= V_M_CTRL_TT_shadow;
V_M_CTRL_TT_shadow_intermed_2 <= V_M_CTRL_TT_shadow_intermed_1;
V_A_CTRL_TT_shadow_intermed_1 <= V_A_CTRL_TT_shadow;
V_A_CTRL_TT_shadow_intermed_2 <= V_A_CTRL_TT_shadow_intermed_1;
V_A_CTRL_TT_shadow_intermed_3 <= V_A_CTRL_TT_shadow_intermed_2;
V_A_CTRL_TT_shadow_intermed_4 <= V_A_CTRL_TT_shadow_intermed_3;
RIN_X_CTRL_TT_intermed_1 <= RIN.X.CTRL.TT;
V_X_DATA0_shadow_intermed_1 <= V_X_DATA0_shadow;
V_X_DATA0_shadow_intermed_2 <= V_X_DATA0_shadow_intermed_1;
RIN_X_DATA0_intermed_1 <= RIN.X.DATA ( 0 );
R_X_DATA0_intermed_1 <= R.X.DATA( 0 );
RIN_X_DATA0_intermed_1 <= RIN.X.DATA( 0 );
RIN_X_DATA0_intermed_2 <= RIN_X_DATA0_intermed_1;
V_X_DATA1_shadow_intermed_1 <= V_X_DATA1_shadow;
V_X_DATA1_shadow_intermed_2 <= V_X_DATA1_shadow_intermed_1;
RIN_X_DATA1_intermed_1 <= RIN.X.DATA ( 1 );
R_X_DATA1_intermed_1 <= R.X.DATA( 1 );
RIN_X_DATA1_intermed_1 <= RIN.X.DATA( 1 );
RIN_X_DATA1_intermed_2 <= RIN_X_DATA1_intermed_1;
RIN_X_SET_intermed_1 <= RIN.X.SET;
V_M_DCI_SIZE_shadow_intermed_1 <= V_M_DCI_SIZE_shadow;
V_M_DCI_SIZE_shadow_intermed_2 <= V_M_DCI_SIZE_shadow_intermed_1;
R_M_DCI_SIZE_intermed_1 <= R.M.DCI.SIZE;
RIN_X_DCI_SIZE_intermed_1 <= RIN.X.DCI.SIZE;
RIN_M_DCI_SIZE_intermed_1 <= RIN.M.DCI.SIZE;
RIN_M_DCI_SIZE_intermed_2 <= RIN_M_DCI_SIZE_intermed_1;
RIN_M_DCI_SIGNED_intermed_1 <= RIN.M.DCI.SIGNED;
RIN_M_DCI_SIGNED_intermed_2 <= RIN_M_DCI_SIGNED_intermed_1;
R_M_DCI_SIGNED_intermed_1 <= R.M.DCI.SIGNED;
RIN_X_DCI_SIGNED_intermed_1 <= RIN.X.DCI.SIGNED;
V_M_DCI_SIGNED_shadow_intermed_1 <= V_M_DCI_SIGNED_shadow;
V_M_DCI_SIGNED_shadow_intermed_2 <= V_M_DCI_SIGNED_shadow_intermed_1;
RIN_X_MEXC_intermed_1 <= RIN.X.MEXC;
RIN_X_ICC_intermed_1 <= RIN.X.ICC;
R_A_CTRL_WICC_intermed_1 <= R.A.CTRL.WICC;
R_A_CTRL_WICC_intermed_2 <= R_A_CTRL_WICC_intermed_1;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2;
RIN_A_CTRL_ANNUL_intermed_4 <= RIN_A_CTRL_ANNUL_intermed_3;
V_E_CTRL_WICC_shadow_intermed_1 <= V_E_CTRL_WICC_shadow;
V_E_CTRL_WICC_shadow_intermed_2 <= V_E_CTRL_WICC_shadow_intermed_1;
V_A_CTRL_WICC_shadow_intermed_1 <= V_A_CTRL_WICC_shadow;
V_A_CTRL_WICC_shadow_intermed_2 <= V_A_CTRL_WICC_shadow_intermed_1;
V_A_CTRL_WICC_shadow_intermed_3 <= V_A_CTRL_WICC_shadow_intermed_2;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1;
R_A_CTRL_ANNUL_intermed_3 <= R_A_CTRL_ANNUL_intermed_2;
RIN_X_CTRL_WICC_intermed_1 <= RIN.X.CTRL.WICC;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
R_X_ANNUL_ALL_intermed_2 <= R_X_ANNUL_ALL_intermed_1;
R_X_ANNUL_ALL_intermed_3 <= R_X_ANNUL_ALL_intermed_2;
RIN_E_CTRL_WICC_intermed_1 <= RIN.E.CTRL.WICC;
RIN_E_CTRL_WICC_intermed_2 <= RIN_E_CTRL_WICC_intermed_1;
RIN_M_CTRL_WICC_intermed_1 <= RIN.M.CTRL.WICC;
R_E_CTRL_WICC_intermed_1 <= R.E.CTRL.WICC;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
V_X_ANNUL_ALL_shadow_intermed_2 <= V_X_ANNUL_ALL_shadow_intermed_1;
V_X_ANNUL_ALL_shadow_intermed_3 <= V_X_ANNUL_ALL_shadow_intermed_2;
V_M_CTRL_WICC_shadow_intermed_1 <= V_M_CTRL_WICC_shadow;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
RIN_X_ANNUL_ALL_intermed_3 <= RIN_X_ANNUL_ALL_intermed_2;
RIN_X_ANNUL_ALL_intermed_4 <= RIN_X_ANNUL_ALL_intermed_3;
RIN_A_CTRL_WICC_intermed_1 <= RIN.A.CTRL.WICC;
RIN_A_CTRL_WICC_intermed_2 <= RIN_A_CTRL_WICC_intermed_1;
RIN_A_CTRL_WICC_intermed_3 <= RIN_A_CTRL_WICC_intermed_2;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_3 <= V_A_CTRL_ANNUL_shadow_intermed_2;
RIN_E_CTRL_intermed_1 <= RIN.E.CTRL;
RIN_M_CTRL_intermed_1 <= RIN.M.CTRL;
V_E_CTRL_shadow_intermed_1 <= V_E_CTRL_shadow;
RIN_A_CTRL_intermed_1 <= RIN.A.CTRL;
RIN_A_CTRL_intermed_2 <= RIN_A_CTRL_intermed_1;
V_A_CTRL_shadow_intermed_1 <= V_A_CTRL_shadow;
V_A_CTRL_shadow_intermed_2 <= V_A_CTRL_shadow_intermed_1;
R_A_CTRL_intermed_1 <= R.A.CTRL;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1;
RIN_M_CTRL_RETT_intermed_1 <= RIN.M.CTRL.RETT;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
R_X_ANNUL_ALL_intermed_2 <= R_X_ANNUL_ALL_intermed_1;
V_E_CTRL_RETT_shadow_intermed_1 <= V_E_CTRL_RETT_shadow;
V_A_CTRL_RETT_shadow_intermed_1 <= V_A_CTRL_RETT_shadow;
V_A_CTRL_RETT_shadow_intermed_2 <= V_A_CTRL_RETT_shadow_intermed_1;
RIN_A_CTRL_RETT_intermed_1 <= RIN.A.CTRL.RETT;
RIN_A_CTRL_RETT_intermed_2 <= RIN_A_CTRL_RETT_intermed_1;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
V_X_ANNUL_ALL_shadow_intermed_2 <= V_X_ANNUL_ALL_shadow_intermed_1;
RIN_E_CTRL_ANNUL_intermed_1 <= RIN.E.CTRL.ANNUL;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
RIN_X_ANNUL_ALL_intermed_3 <= RIN_X_ANNUL_ALL_intermed_2;
RIN_E_CTRL_RETT_intermed_1 <= RIN.E.CTRL.RETT;
V_E_CTRL_ANNUL_shadow_intermed_1 <= V_E_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1;
R_A_CTRL_RETT_intermed_1 <= R.A.CTRL.RETT;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
R_X_ANNUL_ALL_intermed_2 <= R_X_ANNUL_ALL_intermed_1;
RIN_M_CTRL_WREG_intermed_1 <= RIN.M.CTRL.WREG;
RIN_A_CTRL_WREG_intermed_1 <= RIN.A.CTRL.WREG;
RIN_A_CTRL_WREG_intermed_2 <= RIN_A_CTRL_WREG_intermed_1;
V_A_CTRL_WREG_shadow_intermed_1 <= V_A_CTRL_WREG_shadow;
V_A_CTRL_WREG_shadow_intermed_2 <= V_A_CTRL_WREG_shadow_intermed_1;
R_A_CTRL_WREG_intermed_1 <= R.A.CTRL.WREG;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
V_X_ANNUL_ALL_shadow_intermed_2 <= V_X_ANNUL_ALL_shadow_intermed_1;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
RIN_X_ANNUL_ALL_intermed_3 <= RIN_X_ANNUL_ALL_intermed_2;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1;
RIN_E_CTRL_WREG_intermed_1 <= RIN.E.CTRL.WREG;
V_E_CTRL_WREG_shadow_intermed_1 <= V_E_CTRL_WREG_shadow;
RIN_E_CWP_intermed_1 <= RIN.E.CWP;
V_A_CWP_shadow_intermed_1 <= V_A_CWP_shadow;
RIN_D_CWP_intermed_1 <= RIN.D.CWP;
RIN_D_CWP_intermed_2 <= RIN_D_CWP_intermed_1;
RIN_A_CWP_intermed_1 <= RIN.A.CWP;
V_D_CWP_shadow_intermed_1 <= V_D_CWP_shadow;
V_D_CWP_shadow_intermed_2 <= V_D_CWP_shadow_intermed_1;
R_D_CWP_intermed_1 <= R.D.CWP;
R_A_SU_intermed_1 <= R.A.SU;
RIN_A_SU_intermed_1 <= RIN.A.SU;
RIN_A_SU_intermed_2 <= RIN_A_SU_intermed_1;
V_E_SU_shadow_intermed_1 <= V_E_SU_shadow;
V_A_SU_shadow_intermed_1 <= V_A_SU_shadow;
V_A_SU_shadow_intermed_2 <= V_A_SU_shadow_intermed_1;
RIN_M_SU_intermed_1 <= RIN.M.SU;
RIN_E_SU_intermed_1 <= RIN.E.SU;
RIN_M_MUL_intermed_1 <= RIN.M.MUL;
RIN_M_NALIGN_intermed_1 <= RIN.M.NALIGN;
V_X_DATA03_shadow_intermed_1 <= V_X_DATA03_shadow;
V_X_DATA03_shadow_intermed_2 <= V_X_DATA03_shadow_intermed_1;
V_X_DATA03_shadow_intermed_1 <= V_X_DATA03_shadow;
DCO_DATA03_intermed_1 <= DCO.DATA ( 0 )( 3 );
RIN_X_DATA03_intermed_1 <= RIN.X.DATA ( 0 )( 3 );
R_X_DATA03_intermed_1 <= R.X.DATA( 0 )( 3 );
RIN_X_DATA03_intermed_1 <= RIN.X.DATA( 0 )( 3 );
RIN_X_DATA03_intermed_2 <= RIN_X_DATA03_intermed_1;
RIN_E_OP23_intermed_1 <= RIN.E.OP2( 3 );
RIN_E_OP13_intermed_1 <= RIN.E.OP1( 3 );
V_E_OP23_shadow_intermed_1 <= V_E_OP23_shadow;
V_E_OP13_shadow_intermed_1 <= V_E_OP13_shadow;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1;
RIN_M_CTRL_ANNUL_intermed_1 <= RIN.M.CTRL.ANNUL;
RIN_E_CTRL_ANNUL_intermed_1 <= RIN.E.CTRL.ANNUL;
RIN_E_CTRL_ANNUL_intermed_2 <= RIN_E_CTRL_ANNUL_intermed_1;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
V_E_CTRL_ANNUL_shadow_intermed_1 <= V_E_CTRL_ANNUL_shadow;
V_E_CTRL_ANNUL_shadow_intermed_2 <= V_E_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_3 <= V_A_CTRL_ANNUL_shadow_intermed_2;
R_E_CTRL_ANNUL_intermed_1 <= R.E.CTRL.ANNUL;
R_A_CTRL_WICC_intermed_1 <= R.A.CTRL.WICC;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2;
V_E_CTRL_WICC_shadow_intermed_1 <= V_E_CTRL_WICC_shadow;
V_A_CTRL_WICC_shadow_intermed_1 <= V_A_CTRL_WICC_shadow;
V_A_CTRL_WICC_shadow_intermed_2 <= V_A_CTRL_WICC_shadow_intermed_1;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
R_X_ANNUL_ALL_intermed_2 <= R_X_ANNUL_ALL_intermed_1;
RIN_E_CTRL_WICC_intermed_1 <= RIN.E.CTRL.WICC;
RIN_M_CTRL_WICC_intermed_1 <= RIN.M.CTRL.WICC;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
V_X_ANNUL_ALL_shadow_intermed_2 <= V_X_ANNUL_ALL_shadow_intermed_1;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
RIN_X_ANNUL_ALL_intermed_3 <= RIN_X_ANNUL_ALL_intermed_2;
RIN_A_CTRL_WICC_intermed_1 <= RIN.A.CTRL.WICC;
RIN_A_CTRL_WICC_intermed_2 <= RIN_A_CTRL_WICC_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1;
V_E_MAC_shadow_intermed_1 <= V_E_MAC_shadow;
RIN_M_MAC_intermed_1 <= RIN.M.MAC;
RIN_E_MAC_intermed_1 <= RIN.E.MAC;
R_A_CTRL_LD_intermed_1 <= R.A.CTRL.LD;
R_A_CTRL_LD_intermed_2 <= R_A_CTRL_LD_intermed_1;
RIN_A_CTRL_LD_intermed_1 <= RIN.A.CTRL.LD;
RIN_A_CTRL_LD_intermed_2 <= RIN_A_CTRL_LD_intermed_1;
RIN_A_CTRL_LD_intermed_3 <= RIN_A_CTRL_LD_intermed_2;
V_E_CTRL_LD_shadow_intermed_1 <= V_E_CTRL_LD_shadow;
V_E_CTRL_LD_shadow_intermed_2 <= V_E_CTRL_LD_shadow_intermed_1;
R_E_CTRL_LD_intermed_1 <= R.E.CTRL.LD;
RIN_E_CTRL_LD_intermed_1 <= RIN.E.CTRL.LD;
RIN_E_CTRL_LD_intermed_2 <= RIN_E_CTRL_LD_intermed_1;
RIN_M_CTRL_LD_intermed_1 <= RIN.M.CTRL.LD;
V_A_CTRL_LD_shadow_intermed_1 <= V_A_CTRL_LD_shadow;
V_A_CTRL_LD_shadow_intermed_2 <= V_A_CTRL_LD_shadow_intermed_1;
V_A_CTRL_LD_shadow_intermed_3 <= V_A_CTRL_LD_shadow_intermed_2;
RIN_E_CTRL_intermed_1 <= RIN.E.CTRL;
RIN_A_CTRL_intermed_1 <= RIN.A.CTRL;
V_A_CTRL_shadow_intermed_1 <= V_A_CTRL_shadow;
RIN_E_JMPL_intermed_1 <= RIN.E.JMPL;
RIN_A_JMPL_intermed_1 <= RIN.A.JMPL;
V_A_JMPL_shadow_intermed_1 <= V_A_JMPL_shadow;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
RIN_E_CTRL_ANNUL_intermed_1 <= RIN.E.CTRL.ANNUL;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
V_A_CTRL_RETT_shadow_intermed_1 <= V_A_CTRL_RETT_shadow;
RIN_A_CTRL_RETT_intermed_1 <= RIN.A.CTRL.RETT;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
RIN_E_CTRL_RETT_intermed_1 <= RIN.E.CTRL.RETT;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
RIN_A_CTRL_WREG_intermed_1 <= RIN.A.CTRL.WREG;
V_A_CTRL_WREG_shadow_intermed_1 <= V_A_CTRL_WREG_shadow;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
RIN_E_CTRL_WREG_intermed_1 <= RIN.E.CTRL.WREG;
RIN_A_SU_intermed_1 <= RIN.A.SU;
V_A_SU_shadow_intermed_1 <= V_A_SU_shadow;
RIN_E_SU_intermed_1 <= RIN.E.SU;
RIN_E_ET_intermed_1 <= RIN.E.ET;
RIN_A_ET_intermed_1 <= RIN.A.ET;
V_A_ET_shadow_intermed_1 <= V_A_ET_shadow;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
V_A_CTRL_WICC_shadow_intermed_1 <= V_A_CTRL_WICC_shadow;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
RIN_E_CTRL_WICC_intermed_1 <= RIN.E.CTRL.WICC;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
RIN_A_CTRL_WICC_intermed_1 <= RIN.A.CTRL.WICC;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
RIN_D_CWP_intermed_1 <= RIN.D.CWP;
RIN_A_CWP_intermed_1 <= RIN.A.CWP;
V_D_CWP_shadow_intermed_1 <= V_D_CWP_shadow;
RIN_A_RFA1_intermed_1 <= RIN.A.RFA1;
V_A_RFA1_shadow_intermed_1 <= V_A_RFA1_shadow;
DBGI_DADDR9DOWNTO2_intermed_1 <= DBGI.DADDR ( 9 DOWNTO 2 );
RIN_A_RFA1_intermed_1 <= RIN.A.RFA1;
RIN_A_RFA2_intermed_1 <= RIN.A.RFA2;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_A_CTRL_WICC_intermed_1 <= RIN.A.CTRL.WICC;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_WREG_intermed_1 <= RIN.A.CTRL.WREG;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_RETT_intermed_1 <= RIN.A.CTRL.RETT;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_A_CTRL_WY_intermed_1 <= RIN.A.CTRL.WY;
ICO_MEXC_intermed_1 <= ICO.MEXC;
RIN_A_CTRL_TRAP_intermed_1 <= RIN.A.CTRL.TRAP;
V_D_MEXC_shadow_intermed_1 <= V_D_MEXC_shadow;
RIN_D_MEXC_intermed_1 <= RIN.D.MEXC;
RIN_A_CTRL_TT_intermed_1 <= RIN.A.CTRL.TT;
RIN_A_CTRL_INST_intermed_1 <= RIN.A.CTRL.INST;
RIN_D_PC_intermed_1 <= RIN.D.PC;
RIN_A_CTRL_PC_intermed_1 <= RIN.A.CTRL.PC;
V_D_PC_shadow_intermed_1 <= V_D_PC_shadow;
RIN_D_CNT_intermed_1 <= RIN.D.CNT;
V_D_CNT_shadow_intermed_1 <= V_D_CNT_shadow;
RIN_A_CTRL_CNT_intermed_1 <= RIN.A.CTRL.CNT;
R_D_ANNUL_intermed_1 <= R.D.ANNUL;
RIN_D_STEP_intermed_1 <= RIN.D.STEP;
V_D_ANNUL_shadow_intermed_1 <= V_D_ANNUL_shadow;
V_D_ANNUL_shadow_intermed_2 <= V_D_ANNUL_shadow_intermed_1;
DBGI_STEP_intermed_1 <= DBGI.STEP;
V_D_STEP_shadow_intermed_1 <= V_D_STEP_shadow;
RIN_D_ANNUL_intermed_1 <= RIN.D.ANNUL;
RIN_D_ANNUL_intermed_2 <= RIN_D_ANNUL_intermed_1;
RIN_A_STEP_intermed_1 <= RIN.A.STEP;
RIN_D_STEP_intermed_1 <= RIN.D.STEP;
V_D_ANNUL_shadow_intermed_1 <= V_D_ANNUL_shadow;
RIN_D_ANNUL_intermed_1 <= RIN.D.ANNUL;
RIN_D_CNT_intermed_1 <= RIN.D.CNT;
EX_ADD_RES32DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO3_shadow;
RIN_F_PC_intermed_1 <= RIN.F.PC;
EX_JUMP_ADDRESS_shadow_intermed_1 <= EX_JUMP_ADDRESS_shadow;
RIN_F_BRANCH_intermed_1 <= RIN.F.BRANCH;
R_M_CTRL_PC31DOWNTO12_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 12 );
R_M_CTRL_PC31DOWNTO12_intermed_2 <= R_M_CTRL_PC31DOWNTO12_intermed_1;
R_M_CTRL_PC31DOWNTO12_intermed_3 <= R_M_CTRL_PC31DOWNTO12_intermed_2;
V_D_PC31DOWNTO12_shadow_intermed_1 <= V_D_PC31DOWNTO12_shadow;
V_D_PC31DOWNTO12_shadow_intermed_2 <= V_D_PC31DOWNTO12_shadow_intermed_1;
V_D_PC31DOWNTO12_shadow_intermed_3 <= V_D_PC31DOWNTO12_shadow_intermed_2;
V_D_PC31DOWNTO12_shadow_intermed_4 <= V_D_PC31DOWNTO12_shadow_intermed_3;
V_D_PC31DOWNTO12_shadow_intermed_5 <= V_D_PC31DOWNTO12_shadow_intermed_4;
V_D_PC31DOWNTO12_shadow_intermed_6 <= V_D_PC31DOWNTO12_shadow_intermed_5;
V_D_PC31DOWNTO12_shadow_intermed_7 <= V_D_PC31DOWNTO12_shadow_intermed_6;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO12_shadow;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_5;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO12_shadow;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_4;
EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_1 <= EX_ADD_RES32DOWNTO330DOWNTO11_shadow;
EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_2 <= EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_1;
RIN_F_PC31DOWNTO12_intermed_1 <= RIN.F.PC( 31 DOWNTO 12 );
RIN_F_PC31DOWNTO12_intermed_2 <= RIN_F_PC31DOWNTO12_intermed_1;
R_A_CTRL_PC31DOWNTO12_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 12 );
R_A_CTRL_PC31DOWNTO12_intermed_2 <= R_A_CTRL_PC31DOWNTO12_intermed_1;
R_A_CTRL_PC31DOWNTO12_intermed_3 <= R_A_CTRL_PC31DOWNTO12_intermed_2;
R_A_CTRL_PC31DOWNTO12_intermed_4 <= R_A_CTRL_PC31DOWNTO12_intermed_3;
R_A_CTRL_PC31DOWNTO12_intermed_5 <= R_A_CTRL_PC31DOWNTO12_intermed_4;
R_E_CTRL_PC31DOWNTO12_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 12 );
R_E_CTRL_PC31DOWNTO12_intermed_2 <= R_E_CTRL_PC31DOWNTO12_intermed_1;
R_E_CTRL_PC31DOWNTO12_intermed_3 <= R_E_CTRL_PC31DOWNTO12_intermed_2;
R_E_CTRL_PC31DOWNTO12_intermed_4 <= R_E_CTRL_PC31DOWNTO12_intermed_3;
EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO12_shadow;
EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_2 <= EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_1;
RIN_F_PC31DOWNTO12_intermed_1 <= RIN.F.PC ( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_2 <= RIN_A_CTRL_PC31DOWNTO12_intermed_1;
RIN_A_CTRL_PC31DOWNTO12_intermed_3 <= RIN_A_CTRL_PC31DOWNTO12_intermed_2;
RIN_A_CTRL_PC31DOWNTO12_intermed_4 <= RIN_A_CTRL_PC31DOWNTO12_intermed_3;
RIN_A_CTRL_PC31DOWNTO12_intermed_5 <= RIN_A_CTRL_PC31DOWNTO12_intermed_4;
RIN_A_CTRL_PC31DOWNTO12_intermed_6 <= RIN_A_CTRL_PC31DOWNTO12_intermed_5;
RIN_E_CTRL_PC31DOWNTO12_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 12 );
RIN_E_CTRL_PC31DOWNTO12_intermed_2 <= RIN_E_CTRL_PC31DOWNTO12_intermed_1;
RIN_E_CTRL_PC31DOWNTO12_intermed_3 <= RIN_E_CTRL_PC31DOWNTO12_intermed_2;
RIN_E_CTRL_PC31DOWNTO12_intermed_4 <= RIN_E_CTRL_PC31DOWNTO12_intermed_3;
RIN_E_CTRL_PC31DOWNTO12_intermed_5 <= RIN_E_CTRL_PC31DOWNTO12_intermed_4;
V_F_PC31DOWNTO12_shadow_intermed_1 <= V_F_PC31DOWNTO12_shadow;
V_F_PC31DOWNTO12_shadow_intermed_2 <= V_F_PC31DOWNTO12_shadow_intermed_1;
IRIN_ADDR31DOWNTO12_intermed_1 <= IRIN.ADDR( 31 DOWNTO 12 );
IRIN_ADDR31DOWNTO12_intermed_2 <= IRIN_ADDR31DOWNTO12_intermed_1;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO12_shadow;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_2;
EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO13_shadow;
EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_2 <= EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_1;
XC_TRAP_ADDRESS31DOWNTO12_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO12_shadow;
R_F_PC31DOWNTO12_intermed_1 <= R.F.PC( 31 DOWNTO 12 );
RIN_M_CTRL_PC31DOWNTO12_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 12 );
RIN_M_CTRL_PC31DOWNTO12_intermed_2 <= RIN_M_CTRL_PC31DOWNTO12_intermed_1;
RIN_M_CTRL_PC31DOWNTO12_intermed_3 <= RIN_M_CTRL_PC31DOWNTO12_intermed_2;
RIN_M_CTRL_PC31DOWNTO12_intermed_4 <= RIN_M_CTRL_PC31DOWNTO12_intermed_3;
IR_ADDR31DOWNTO12_intermed_1 <= IR.ADDR( 31 DOWNTO 12 );
R_X_CTRL_PC31DOWNTO12_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 12 );
R_X_CTRL_PC31DOWNTO12_intermed_2 <= R_X_CTRL_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_1 <= R.D.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_2 <= R_D_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_3 <= R_D_PC31DOWNTO12_intermed_2;
R_D_PC31DOWNTO12_intermed_4 <= R_D_PC31DOWNTO12_intermed_3;
R_D_PC31DOWNTO12_intermed_5 <= R_D_PC31DOWNTO12_intermed_4;
R_D_PC31DOWNTO12_intermed_6 <= R_D_PC31DOWNTO12_intermed_5;
RIN_X_CTRL_PC31DOWNTO12_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 12 );
RIN_X_CTRL_PC31DOWNTO12_intermed_2 <= RIN_X_CTRL_PC31DOWNTO12_intermed_1;
RIN_X_CTRL_PC31DOWNTO12_intermed_3 <= RIN_X_CTRL_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_1 <= RIN.D.PC( 31 DOWNTO 12 );
RIN_D_PC31DOWNTO12_intermed_2 <= RIN_D_PC31DOWNTO12_intermed_1;
RIN_D_PC31DOWNTO12_intermed_3 <= RIN_D_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_4 <= RIN_D_PC31DOWNTO12_intermed_3;
RIN_D_PC31DOWNTO12_intermed_5 <= RIN_D_PC31DOWNTO12_intermed_4;
RIN_D_PC31DOWNTO12_intermed_6 <= RIN_D_PC31DOWNTO12_intermed_5;
RIN_D_PC31DOWNTO12_intermed_7 <= RIN_D_PC31DOWNTO12_intermed_6;
VIR_ADDR31DOWNTO12_shadow_intermed_1 <= VIR_ADDR31DOWNTO12_shadow;
VIR_ADDR31DOWNTO12_shadow_intermed_2 <= VIR_ADDR31DOWNTO12_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO12_shadow;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_3;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_4 <= RIN_M_CTRL_PC31DOWNTO2_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
V_D_PC31DOWNTO2_shadow_intermed_6 <= V_D_PC31DOWNTO2_shadow_intermed_5;
V_D_PC31DOWNTO2_shadow_intermed_7 <= V_D_PC31DOWNTO2_shadow_intermed_6;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_D_PC31DOWNTO2_intermed_6 <= RIN_D_PC31DOWNTO2_intermed_5;
RIN_D_PC31DOWNTO2_intermed_7 <= RIN_D_PC31DOWNTO2_intermed_6;
EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow;
EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_2 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1;
V_F_PC31DOWNTO2_shadow_intermed_1 <= V_F_PC31DOWNTO2_shadow;
V_F_PC31DOWNTO2_shadow_intermed_2 <= V_F_PC31DOWNTO2_shadow_intermed_1;
RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC( 31 DOWNTO 2 );
RIN_F_PC31DOWNTO2_intermed_2 <= RIN_F_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_3 <= RIN_X_CTRL_PC31DOWNTO2_intermed_2;
IRIN_ADDR31DOWNTO2_intermed_1 <= IRIN.ADDR( 31 DOWNTO 2 );
IRIN_ADDR31DOWNTO2_intermed_2 <= IRIN_ADDR31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_5;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_D_PC31DOWNTO2_intermed_5 <= R_D_PC31DOWNTO2_intermed_4;
R_D_PC31DOWNTO2_intermed_6 <= R_D_PC31DOWNTO2_intermed_5;
R_F_PC31DOWNTO2_intermed_1 <= R.F.PC( 31 DOWNTO 2 );
VIR_ADDR31DOWNTO2_shadow_intermed_1 <= VIR_ADDR31DOWNTO2_shadow;
VIR_ADDR31DOWNTO2_shadow_intermed_2 <= VIR_ADDR31DOWNTO2_shadow_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_3 <= R_M_CTRL_PC31DOWNTO2_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_6 <= RIN_A_CTRL_PC31DOWNTO2_intermed_5;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
R_A_CTRL_PC31DOWNTO2_intermed_5 <= R_A_CTRL_PC31DOWNTO2_intermed_4;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
R_X_CTRL_PC31DOWNTO2_intermed_2 <= R_X_CTRL_PC31DOWNTO2_intermed_1;
XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO2_shadow;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_4 <= R_E_CTRL_PC31DOWNTO2_intermed_3;
EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO2_shadow;
EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_2 <= EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1;
RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC ( 31 DOWNTO 2 );
IR_ADDR31DOWNTO2_intermed_1 <= IR.ADDR( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_5 <= RIN_E_CTRL_PC31DOWNTO2_intermed_4;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_4 <= RIN_M_CTRL_PC31DOWNTO2_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
V_D_PC31DOWNTO2_shadow_intermed_6 <= V_D_PC31DOWNTO2_shadow_intermed_5;
V_D_PC31DOWNTO2_shadow_intermed_7 <= V_D_PC31DOWNTO2_shadow_intermed_6;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_D_PC31DOWNTO2_intermed_6 <= RIN_D_PC31DOWNTO2_intermed_5;
RIN_D_PC31DOWNTO2_intermed_7 <= RIN_D_PC31DOWNTO2_intermed_6;
EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow;
V_F_PC31DOWNTO2_shadow_intermed_1 <= V_F_PC31DOWNTO2_shadow;
RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_3 <= RIN_X_CTRL_PC31DOWNTO2_intermed_2;
IRIN_ADDR31DOWNTO2_intermed_1 <= IRIN.ADDR( 31 DOWNTO 2 );
IRIN_ADDR31DOWNTO2_intermed_2 <= IRIN_ADDR31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_5;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_D_PC31DOWNTO2_intermed_5 <= R_D_PC31DOWNTO2_intermed_4;
R_D_PC31DOWNTO2_intermed_6 <= R_D_PC31DOWNTO2_intermed_5;
VIR_ADDR31DOWNTO2_shadow_intermed_1 <= VIR_ADDR31DOWNTO2_shadow;
VIR_ADDR31DOWNTO2_shadow_intermed_2 <= VIR_ADDR31DOWNTO2_shadow_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_3 <= R_M_CTRL_PC31DOWNTO2_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_6 <= RIN_A_CTRL_PC31DOWNTO2_intermed_5;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
R_A_CTRL_PC31DOWNTO2_intermed_5 <= R_A_CTRL_PC31DOWNTO2_intermed_4;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
R_X_CTRL_PC31DOWNTO2_intermed_2 <= R_X_CTRL_PC31DOWNTO2_intermed_1;
XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO2_shadow;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_4 <= R_E_CTRL_PC31DOWNTO2_intermed_3;
EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO2_shadow;
IR_ADDR31DOWNTO2_intermed_1 <= IR.ADDR( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_5 <= RIN_E_CTRL_PC31DOWNTO2_intermed_4;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_D_INST0_intermed_1 <= RIN.D.INST ( 0 );
R_D_INST0_intermed_1 <= R.D.INST( 0 );
V_D_INST0_shadow_intermed_1 <= V_D_INST0_shadow;
V_D_INST0_shadow_intermed_2 <= V_D_INST0_shadow_intermed_1;
RIN_D_INST0_intermed_1 <= RIN.D.INST( 0 );
RIN_D_INST0_intermed_2 <= RIN_D_INST0_intermed_1;
RIN_D_INST1_intermed_1 <= RIN.D.INST ( 1 );
R_D_INST1_intermed_1 <= R.D.INST( 1 );
V_D_INST1_shadow_intermed_1 <= V_D_INST1_shadow;
V_D_INST1_shadow_intermed_2 <= V_D_INST1_shadow_intermed_1;
RIN_D_INST1_intermed_1 <= RIN.D.INST( 1 );
RIN_D_INST1_intermed_2 <= RIN_D_INST1_intermed_1;
RIN_D_SET_intermed_1 <= RIN.D.SET;
RIN_D_MEXC_intermed_1 <= RIN.D.MEXC;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
RIN_E_OP131_intermed_1 <= RIN.E.OP1( 31 );
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 );
V_E_OP131_shadow_intermed_1 <= V_E_OP131_shadow;
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 );
RIN_E_OP231_intermed_1 <= RIN.E.OP2( 31 );
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
V_E_OP231_shadow_intermed_1 <= V_E_OP231_shadow;
V_D_ANNUL_shadow_intermed_1 <= V_D_ANNUL_shadow;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_D_ANNUL_intermed_1 <= RIN.D.ANNUL;
V_X_DATA03_shadow_intermed_1 <= V_X_DATA03_shadow;
V_X_DATA03_shadow_intermed_2 <= V_X_DATA03_shadow_intermed_1;
V_X_DATA03_shadow_intermed_1 <= V_X_DATA03_shadow;
DCO_DATA03_intermed_1 <= DCO.DATA ( 0 )( 3 );
RIN_X_DATA03_intermed_1 <= RIN.X.DATA ( 0 )( 3 );
R_X_DATA03_intermed_1 <= R.X.DATA( 0 )( 3 );
RIN_X_DATA03_intermed_1 <= RIN.X.DATA( 0 )( 3 );
RIN_X_DATA03_intermed_2 <= RIN_X_DATA03_intermed_1;
RIN_E_OP13_intermed_1 <= RIN.E.OP1( 3 );
V_E_OP13_shadow_intermed_1 <= V_E_OP13_shadow;
V_X_DATA03_shadow_intermed_1 <= V_X_DATA03_shadow;
V_X_DATA03_shadow_intermed_2 <= V_X_DATA03_shadow_intermed_1;
V_X_DATA03_shadow_intermed_1 <= V_X_DATA03_shadow;
DCO_DATA03_intermed_1 <= DCO.DATA ( 0 )( 3 );
RIN_X_DATA03_intermed_1 <= RIN.X.DATA ( 0 )( 3 );
R_X_DATA03_intermed_1 <= R.X.DATA( 0 )( 3 );
RIN_X_DATA03_intermed_1 <= RIN.X.DATA( 0 )( 3 );
RIN_X_DATA03_intermed_2 <= RIN_X_DATA03_intermed_1;
RIN_E_OP23_intermed_1 <= RIN.E.OP2( 3 );
V_E_OP23_shadow_intermed_1 <= V_E_OP23_shadow;
R_M_CTRL_PC31DOWNTO12_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 12 );
R_M_CTRL_PC31DOWNTO12_intermed_2 <= R_M_CTRL_PC31DOWNTO12_intermed_1;
R_M_CTRL_PC31DOWNTO12_intermed_3 <= R_M_CTRL_PC31DOWNTO12_intermed_2;
V_D_PC31DOWNTO12_shadow_intermed_1 <= V_D_PC31DOWNTO12_shadow;
V_D_PC31DOWNTO12_shadow_intermed_2 <= V_D_PC31DOWNTO12_shadow_intermed_1;
V_D_PC31DOWNTO12_shadow_intermed_3 <= V_D_PC31DOWNTO12_shadow_intermed_2;
V_D_PC31DOWNTO12_shadow_intermed_4 <= V_D_PC31DOWNTO12_shadow_intermed_3;
V_D_PC31DOWNTO12_shadow_intermed_5 <= V_D_PC31DOWNTO12_shadow_intermed_4;
V_D_PC31DOWNTO12_shadow_intermed_6 <= V_D_PC31DOWNTO12_shadow_intermed_5;
V_D_PC31DOWNTO12_shadow_intermed_7 <= V_D_PC31DOWNTO12_shadow_intermed_6;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO12_shadow;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_5;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO12_shadow;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_4;
EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_1 <= EX_ADD_RES32DOWNTO330DOWNTO11_shadow;
RIN_F_PC31DOWNTO12_intermed_1 <= RIN.F.PC( 31 DOWNTO 12 );
R_A_CTRL_PC31DOWNTO12_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 12 );
R_A_CTRL_PC31DOWNTO12_intermed_2 <= R_A_CTRL_PC31DOWNTO12_intermed_1;
R_A_CTRL_PC31DOWNTO12_intermed_3 <= R_A_CTRL_PC31DOWNTO12_intermed_2;
R_A_CTRL_PC31DOWNTO12_intermed_4 <= R_A_CTRL_PC31DOWNTO12_intermed_3;
R_A_CTRL_PC31DOWNTO12_intermed_5 <= R_A_CTRL_PC31DOWNTO12_intermed_4;
R_E_CTRL_PC31DOWNTO12_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 12 );
R_E_CTRL_PC31DOWNTO12_intermed_2 <= R_E_CTRL_PC31DOWNTO12_intermed_1;
R_E_CTRL_PC31DOWNTO12_intermed_3 <= R_E_CTRL_PC31DOWNTO12_intermed_2;
R_E_CTRL_PC31DOWNTO12_intermed_4 <= R_E_CTRL_PC31DOWNTO12_intermed_3;
EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO12_shadow;
RIN_A_CTRL_PC31DOWNTO12_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_2 <= RIN_A_CTRL_PC31DOWNTO12_intermed_1;
RIN_A_CTRL_PC31DOWNTO12_intermed_3 <= RIN_A_CTRL_PC31DOWNTO12_intermed_2;
RIN_A_CTRL_PC31DOWNTO12_intermed_4 <= RIN_A_CTRL_PC31DOWNTO12_intermed_3;
RIN_A_CTRL_PC31DOWNTO12_intermed_5 <= RIN_A_CTRL_PC31DOWNTO12_intermed_4;
RIN_A_CTRL_PC31DOWNTO12_intermed_6 <= RIN_A_CTRL_PC31DOWNTO12_intermed_5;
RIN_E_CTRL_PC31DOWNTO12_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 12 );
RIN_E_CTRL_PC31DOWNTO12_intermed_2 <= RIN_E_CTRL_PC31DOWNTO12_intermed_1;
RIN_E_CTRL_PC31DOWNTO12_intermed_3 <= RIN_E_CTRL_PC31DOWNTO12_intermed_2;
RIN_E_CTRL_PC31DOWNTO12_intermed_4 <= RIN_E_CTRL_PC31DOWNTO12_intermed_3;
RIN_E_CTRL_PC31DOWNTO12_intermed_5 <= RIN_E_CTRL_PC31DOWNTO12_intermed_4;
V_F_PC31DOWNTO12_shadow_intermed_1 <= V_F_PC31DOWNTO12_shadow;
IRIN_ADDR31DOWNTO12_intermed_1 <= IRIN.ADDR( 31 DOWNTO 12 );
IRIN_ADDR31DOWNTO12_intermed_2 <= IRIN_ADDR31DOWNTO12_intermed_1;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO12_shadow;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_2;
EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO13_shadow;
RIN_M_CTRL_PC31DOWNTO12_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 12 );
RIN_M_CTRL_PC31DOWNTO12_intermed_2 <= RIN_M_CTRL_PC31DOWNTO12_intermed_1;
RIN_M_CTRL_PC31DOWNTO12_intermed_3 <= RIN_M_CTRL_PC31DOWNTO12_intermed_2;
RIN_M_CTRL_PC31DOWNTO12_intermed_4 <= RIN_M_CTRL_PC31DOWNTO12_intermed_3;
IR_ADDR31DOWNTO12_intermed_1 <= IR.ADDR( 31 DOWNTO 12 );
R_X_CTRL_PC31DOWNTO12_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 12 );
R_X_CTRL_PC31DOWNTO12_intermed_2 <= R_X_CTRL_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_1 <= R.D.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_2 <= R_D_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_3 <= R_D_PC31DOWNTO12_intermed_2;
R_D_PC31DOWNTO12_intermed_4 <= R_D_PC31DOWNTO12_intermed_3;
R_D_PC31DOWNTO12_intermed_5 <= R_D_PC31DOWNTO12_intermed_4;
R_D_PC31DOWNTO12_intermed_6 <= R_D_PC31DOWNTO12_intermed_5;
RIN_X_CTRL_PC31DOWNTO12_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 12 );
RIN_X_CTRL_PC31DOWNTO12_intermed_2 <= RIN_X_CTRL_PC31DOWNTO12_intermed_1;
RIN_X_CTRL_PC31DOWNTO12_intermed_3 <= RIN_X_CTRL_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_1 <= RIN.D.PC( 31 DOWNTO 12 );
RIN_D_PC31DOWNTO12_intermed_2 <= RIN_D_PC31DOWNTO12_intermed_1;
RIN_D_PC31DOWNTO12_intermed_3 <= RIN_D_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_4 <= RIN_D_PC31DOWNTO12_intermed_3;
RIN_D_PC31DOWNTO12_intermed_5 <= RIN_D_PC31DOWNTO12_intermed_4;
RIN_D_PC31DOWNTO12_intermed_6 <= RIN_D_PC31DOWNTO12_intermed_5;
RIN_D_PC31DOWNTO12_intermed_7 <= RIN_D_PC31DOWNTO12_intermed_6;
VIR_ADDR31DOWNTO12_shadow_intermed_1 <= VIR_ADDR31DOWNTO12_shadow;
VIR_ADDR31DOWNTO12_shadow_intermed_2 <= VIR_ADDR31DOWNTO12_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO12_shadow;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_3;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_4 <= RIN_M_CTRL_PC31DOWNTO2_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
V_D_PC31DOWNTO2_shadow_intermed_6 <= V_D_PC31DOWNTO2_shadow_intermed_5;
V_D_PC31DOWNTO2_shadow_intermed_7 <= V_D_PC31DOWNTO2_shadow_intermed_6;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_D_PC31DOWNTO2_intermed_6 <= RIN_D_PC31DOWNTO2_intermed_5;
RIN_D_PC31DOWNTO2_intermed_7 <= RIN_D_PC31DOWNTO2_intermed_6;
EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow;
V_F_PC31DOWNTO2_shadow_intermed_1 <= V_F_PC31DOWNTO2_shadow;
RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_3 <= RIN_X_CTRL_PC31DOWNTO2_intermed_2;
IRIN_ADDR31DOWNTO2_intermed_1 <= IRIN.ADDR( 31 DOWNTO 2 );
IRIN_ADDR31DOWNTO2_intermed_2 <= IRIN_ADDR31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_5;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_D_PC31DOWNTO2_intermed_5 <= R_D_PC31DOWNTO2_intermed_4;
R_D_PC31DOWNTO2_intermed_6 <= R_D_PC31DOWNTO2_intermed_5;
VIR_ADDR31DOWNTO2_shadow_intermed_1 <= VIR_ADDR31DOWNTO2_shadow;
VIR_ADDR31DOWNTO2_shadow_intermed_2 <= VIR_ADDR31DOWNTO2_shadow_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_3 <= R_M_CTRL_PC31DOWNTO2_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_6 <= RIN_A_CTRL_PC31DOWNTO2_intermed_5;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
R_A_CTRL_PC31DOWNTO2_intermed_5 <= R_A_CTRL_PC31DOWNTO2_intermed_4;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
R_X_CTRL_PC31DOWNTO2_intermed_2 <= R_X_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_4 <= R_E_CTRL_PC31DOWNTO2_intermed_3;
EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO2_shadow;
IR_ADDR31DOWNTO2_intermed_1 <= IR.ADDR( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_5 <= RIN_E_CTRL_PC31DOWNTO2_intermed_4;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_4 <= RIN_M_CTRL_PC31DOWNTO2_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
V_D_PC31DOWNTO2_shadow_intermed_6 <= V_D_PC31DOWNTO2_shadow_intermed_5;
V_D_PC31DOWNTO2_shadow_intermed_7 <= V_D_PC31DOWNTO2_shadow_intermed_6;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_D_PC31DOWNTO2_intermed_6 <= RIN_D_PC31DOWNTO2_intermed_5;
RIN_D_PC31DOWNTO2_intermed_7 <= RIN_D_PC31DOWNTO2_intermed_6;
EX_ADD_RES32DOWNTO332DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO3_shadow;
RIN_F_PC31DOWNTO2_intermed_1 <= RIN.F.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_X_CTRL_PC31DOWNTO2_intermed_3 <= RIN_X_CTRL_PC31DOWNTO2_intermed_2;
IRIN_ADDR31DOWNTO2_intermed_1 <= IRIN.ADDR( 31 DOWNTO 2 );
IRIN_ADDR31DOWNTO2_intermed_2 <= IRIN_ADDR31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_5;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_D_PC31DOWNTO2_intermed_5 <= R_D_PC31DOWNTO2_intermed_4;
R_D_PC31DOWNTO2_intermed_6 <= R_D_PC31DOWNTO2_intermed_5;
VIR_ADDR31DOWNTO2_shadow_intermed_1 <= VIR_ADDR31DOWNTO2_shadow;
VIR_ADDR31DOWNTO2_shadow_intermed_2 <= VIR_ADDR31DOWNTO2_shadow_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
R_M_CTRL_PC31DOWNTO2_intermed_3 <= R_M_CTRL_PC31DOWNTO2_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
RIN_A_CTRL_PC31DOWNTO2_intermed_6 <= RIN_A_CTRL_PC31DOWNTO2_intermed_5;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
R_A_CTRL_PC31DOWNTO2_intermed_5 <= R_A_CTRL_PC31DOWNTO2_intermed_4;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
R_X_CTRL_PC31DOWNTO2_intermed_2 <= R_X_CTRL_PC31DOWNTO2_intermed_1;
XC_TRAP_ADDRESS31DOWNTO2_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO2_shadow;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_4 <= R_E_CTRL_PC31DOWNTO2_intermed_3;
EX_JUMP_ADDRESS31DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO2_shadow;
IR_ADDR31DOWNTO2_intermed_1 <= IR.ADDR( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_5 <= RIN_E_CTRL_PC31DOWNTO2_intermed_4;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 );
RIN_E_OP231_intermed_1 <= RIN.E.OP2( 31 );
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
V_E_OP231_shadow_intermed_1 <= V_E_OP231_shadow;
V_M_CTRL_RD7DOWNTO0_shadow_intermed_1 <= V_M_CTRL_RD7DOWNTO0_shadow;
V_M_CTRL_RD7DOWNTO0_shadow_intermed_2 <= V_M_CTRL_RD7DOWNTO0_shadow_intermed_1;
V_E_CTRL_RD7DOWNTO0_shadow_intermed_1 <= V_E_CTRL_RD7DOWNTO0_shadow;
V_E_CTRL_RD7DOWNTO0_shadow_intermed_2 <= V_E_CTRL_RD7DOWNTO0_shadow_intermed_1;
V_E_CTRL_RD7DOWNTO0_shadow_intermed_3 <= V_E_CTRL_RD7DOWNTO0_shadow_intermed_2;
R_E_CTRL_RD7DOWNTO0_intermed_1 <= R.E.CTRL.RD ( 7 DOWNTO 0 );
R_E_CTRL_RD7DOWNTO0_intermed_2 <= R_E_CTRL_RD7DOWNTO0_intermed_1;
V_A_CTRL_RD7DOWNTO0_shadow_intermed_1 <= V_A_CTRL_RD7DOWNTO0_shadow;
V_A_CTRL_RD7DOWNTO0_shadow_intermed_2 <= V_A_CTRL_RD7DOWNTO0_shadow_intermed_1;
V_A_CTRL_RD7DOWNTO0_shadow_intermed_3 <= V_A_CTRL_RD7DOWNTO0_shadow_intermed_2;
V_A_CTRL_RD7DOWNTO0_shadow_intermed_4 <= V_A_CTRL_RD7DOWNTO0_shadow_intermed_3;
RIN_A_CTRL_RD7DOWNTO0_intermed_1 <= RIN.A.CTRL.RD ( 7 DOWNTO 0 );
RIN_A_CTRL_RD7DOWNTO0_intermed_2 <= RIN_A_CTRL_RD7DOWNTO0_intermed_1;
RIN_A_CTRL_RD7DOWNTO0_intermed_3 <= RIN_A_CTRL_RD7DOWNTO0_intermed_2;
RIN_A_CTRL_RD7DOWNTO0_intermed_4 <= RIN_A_CTRL_RD7DOWNTO0_intermed_3;
R_M_CTRL_RD7DOWNTO0_intermed_1 <= R.M.CTRL.RD ( 7 DOWNTO 0 );
R_A_CTRL_RD7DOWNTO0_intermed_1 <= R.A.CTRL.RD ( 7 DOWNTO 0 );
R_A_CTRL_RD7DOWNTO0_intermed_2 <= R_A_CTRL_RD7DOWNTO0_intermed_1;
R_A_CTRL_RD7DOWNTO0_intermed_3 <= R_A_CTRL_RD7DOWNTO0_intermed_2;
RIN_E_CTRL_RD7DOWNTO0_intermed_1 <= RIN.E.CTRL.RD ( 7 DOWNTO 0 );
RIN_E_CTRL_RD7DOWNTO0_intermed_2 <= RIN_E_CTRL_RD7DOWNTO0_intermed_1;
RIN_E_CTRL_RD7DOWNTO0_intermed_3 <= RIN_E_CTRL_RD7DOWNTO0_intermed_2;
RIN_X_CTRL_RD7DOWNTO0_intermed_1 <= RIN.X.CTRL.RD ( 7 DOWNTO 0 );
RIN_M_CTRL_RD7DOWNTO0_intermed_1 <= RIN.M.CTRL.RD ( 7 DOWNTO 0 );
RIN_M_CTRL_RD7DOWNTO0_intermed_2 <= RIN_M_CTRL_RD7DOWNTO0_intermed_1;
RIN_X_CTRL_TRAP_intermed_1 <= RIN.X.CTRL.TRAP;
V_A_CTRL_TRAP_shadow_intermed_1 <= V_A_CTRL_TRAP_shadow;
V_A_CTRL_TRAP_shadow_intermed_2 <= V_A_CTRL_TRAP_shadow_intermed_1;
V_A_CTRL_TRAP_shadow_intermed_3 <= V_A_CTRL_TRAP_shadow_intermed_2;
V_A_CTRL_TRAP_shadow_intermed_4 <= V_A_CTRL_TRAP_shadow_intermed_3;
ICO_MEXC_intermed_1 <= ICO.MEXC;
ICO_MEXC_intermed_2 <= ICO_MEXC_intermed_1;
ICO_MEXC_intermed_3 <= ICO_MEXC_intermed_2;
ICO_MEXC_intermed_4 <= ICO_MEXC_intermed_3;
ICO_MEXC_intermed_5 <= ICO_MEXC_intermed_4;
R_E_CTRL_TRAP_intermed_1 <= R.E.CTRL.TRAP;
R_E_CTRL_TRAP_intermed_2 <= R_E_CTRL_TRAP_intermed_1;
RIN_A_CTRL_TRAP_intermed_1 <= RIN.A.CTRL.TRAP;
RIN_A_CTRL_TRAP_intermed_2 <= RIN_A_CTRL_TRAP_intermed_1;
RIN_A_CTRL_TRAP_intermed_3 <= RIN_A_CTRL_TRAP_intermed_2;
RIN_A_CTRL_TRAP_intermed_4 <= RIN_A_CTRL_TRAP_intermed_3;
V_E_CTRL_TRAP_shadow_intermed_1 <= V_E_CTRL_TRAP_shadow;
V_E_CTRL_TRAP_shadow_intermed_2 <= V_E_CTRL_TRAP_shadow_intermed_1;
V_E_CTRL_TRAP_shadow_intermed_3 <= V_E_CTRL_TRAP_shadow_intermed_2;
RIN_E_CTRL_TRAP_intermed_1 <= RIN.E.CTRL.TRAP;
RIN_E_CTRL_TRAP_intermed_2 <= RIN_E_CTRL_TRAP_intermed_1;
RIN_E_CTRL_TRAP_intermed_3 <= RIN_E_CTRL_TRAP_intermed_2;
R_D_MEXC_intermed_1 <= R.D.MEXC;
R_D_MEXC_intermed_2 <= R_D_MEXC_intermed_1;
R_D_MEXC_intermed_3 <= R_D_MEXC_intermed_2;
R_D_MEXC_intermed_4 <= R_D_MEXC_intermed_3;
V_M_CTRL_TRAP_shadow_intermed_1 <= V_M_CTRL_TRAP_shadow;
V_M_CTRL_TRAP_shadow_intermed_2 <= V_M_CTRL_TRAP_shadow_intermed_1;
V_D_MEXC_shadow_intermed_1 <= V_D_MEXC_shadow;
V_D_MEXC_shadow_intermed_2 <= V_D_MEXC_shadow_intermed_1;
V_D_MEXC_shadow_intermed_3 <= V_D_MEXC_shadow_intermed_2;
V_D_MEXC_shadow_intermed_4 <= V_D_MEXC_shadow_intermed_3;
V_D_MEXC_shadow_intermed_5 <= V_D_MEXC_shadow_intermed_4;
R_A_CTRL_TRAP_intermed_1 <= R.A.CTRL.TRAP;
R_A_CTRL_TRAP_intermed_2 <= R_A_CTRL_TRAP_intermed_1;
R_A_CTRL_TRAP_intermed_3 <= R_A_CTRL_TRAP_intermed_2;
RIN_M_CTRL_TRAP_intermed_1 <= RIN.M.CTRL.TRAP;
RIN_M_CTRL_TRAP_intermed_2 <= RIN_M_CTRL_TRAP_intermed_1;
R_M_CTRL_TRAP_intermed_1 <= R.M.CTRL.TRAP;
RIN_D_MEXC_intermed_1 <= RIN.D.MEXC;
RIN_D_MEXC_intermed_2 <= RIN_D_MEXC_intermed_1;
RIN_D_MEXC_intermed_3 <= RIN_D_MEXC_intermed_2;
RIN_D_MEXC_intermed_4 <= RIN_D_MEXC_intermed_3;
RIN_D_MEXC_intermed_5 <= RIN_D_MEXC_intermed_4;
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 );
V_X_RESULT6DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO0_shadow;
V_X_RESULT6DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO0_shadow_intermed_1;
RIN_X_RESULT6DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 );
RIN_X_RESULT6DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO0_intermed_1;
R_X_RESULT6DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 );
RIN_D_PC_intermed_1 <= RIN.D.PC;
RIN_D_PC_intermed_2 <= RIN_D_PC_intermed_1;
RIN_D_PC_intermed_3 <= RIN_D_PC_intermed_2;
RIN_D_PC_intermed_4 <= RIN_D_PC_intermed_3;
RIN_D_PC_intermed_5 <= RIN_D_PC_intermed_4;
RIN_A_CTRL_PC_intermed_1 <= RIN.A.CTRL.PC;
RIN_A_CTRL_PC_intermed_2 <= RIN_A_CTRL_PC_intermed_1;
RIN_A_CTRL_PC_intermed_3 <= RIN_A_CTRL_PC_intermed_2;
RIN_A_CTRL_PC_intermed_4 <= RIN_A_CTRL_PC_intermed_3;
R_A_CTRL_PC_intermed_1 <= R.A.CTRL.PC;
R_A_CTRL_PC_intermed_2 <= R_A_CTRL_PC_intermed_1;
R_A_CTRL_PC_intermed_3 <= R_A_CTRL_PC_intermed_2;
V_E_CTRL_PC_shadow_intermed_1 <= V_E_CTRL_PC_shadow;
V_E_CTRL_PC_shadow_intermed_2 <= V_E_CTRL_PC_shadow_intermed_1;
V_E_CTRL_PC_shadow_intermed_3 <= V_E_CTRL_PC_shadow_intermed_2;
R_M_CTRL_PC_intermed_1 <= R.M.CTRL.PC;
R_E_CTRL_PC_intermed_1 <= R.E.CTRL.PC;
R_E_CTRL_PC_intermed_2 <= R_E_CTRL_PC_intermed_1;
RIN_M_CTRL_PC_intermed_1 <= RIN.M.CTRL.PC;
RIN_M_CTRL_PC_intermed_2 <= RIN_M_CTRL_PC_intermed_1;
V_M_CTRL_PC_shadow_intermed_1 <= V_M_CTRL_PC_shadow;
V_M_CTRL_PC_shadow_intermed_2 <= V_M_CTRL_PC_shadow_intermed_1;
V_A_CTRL_PC_shadow_intermed_1 <= V_A_CTRL_PC_shadow;
V_A_CTRL_PC_shadow_intermed_2 <= V_A_CTRL_PC_shadow_intermed_1;
V_A_CTRL_PC_shadow_intermed_3 <= V_A_CTRL_PC_shadow_intermed_2;
V_A_CTRL_PC_shadow_intermed_4 <= V_A_CTRL_PC_shadow_intermed_3;
R_D_PC_intermed_1 <= R.D.PC;
R_D_PC_intermed_2 <= R_D_PC_intermed_1;
R_D_PC_intermed_3 <= R_D_PC_intermed_2;
R_D_PC_intermed_4 <= R_D_PC_intermed_3;
RIN_E_CTRL_PC_intermed_1 <= RIN.E.CTRL.PC;
RIN_E_CTRL_PC_intermed_2 <= RIN_E_CTRL_PC_intermed_1;
RIN_E_CTRL_PC_intermed_3 <= RIN_E_CTRL_PC_intermed_2;
RIN_X_CTRL_PC_intermed_1 <= RIN.X.CTRL.PC;
V_D_PC_shadow_intermed_1 <= V_D_PC_shadow;
V_D_PC_shadow_intermed_2 <= V_D_PC_shadow_intermed_1;
V_D_PC_shadow_intermed_3 <= V_D_PC_shadow_intermed_2;
V_D_PC_shadow_intermed_4 <= V_D_PC_shadow_intermed_3;
V_D_PC_shadow_intermed_5 <= V_D_PC_shadow_intermed_4;
RIN_A_CTRL_ANNUL_intermed_1 <= RIN.A.CTRL.ANNUL;
RIN_A_CTRL_ANNUL_intermed_2 <= RIN_A_CTRL_ANNUL_intermed_1;
RIN_A_CTRL_ANNUL_intermed_3 <= RIN_A_CTRL_ANNUL_intermed_2;
RIN_A_CTRL_ANNUL_intermed_4 <= RIN_A_CTRL_ANNUL_intermed_3;
RIN_A_CTRL_ANNUL_intermed_5 <= RIN_A_CTRL_ANNUL_intermed_4;
R_A_CTRL_ANNUL_intermed_1 <= R.A.CTRL.ANNUL;
R_A_CTRL_ANNUL_intermed_2 <= R_A_CTRL_ANNUL_intermed_1;
R_A_CTRL_ANNUL_intermed_3 <= R_A_CTRL_ANNUL_intermed_2;
R_A_CTRL_ANNUL_intermed_4 <= R_A_CTRL_ANNUL_intermed_3;
R_X_ANNUL_ALL_intermed_1 <= R.X.ANNUL_ALL;
R_X_ANNUL_ALL_intermed_2 <= R_X_ANNUL_ALL_intermed_1;
R_X_ANNUL_ALL_intermed_3 <= R_X_ANNUL_ALL_intermed_2;
R_X_ANNUL_ALL_intermed_4 <= R_X_ANNUL_ALL_intermed_3;
RIN_X_CTRL_WREG_intermed_1 <= RIN.X.CTRL.WREG;
RIN_M_CTRL_WREG_intermed_1 <= RIN.M.CTRL.WREG;
RIN_M_CTRL_WREG_intermed_2 <= RIN_M_CTRL_WREG_intermed_1;
RIN_A_CTRL_WREG_intermed_1 <= RIN.A.CTRL.WREG;
RIN_A_CTRL_WREG_intermed_2 <= RIN_A_CTRL_WREG_intermed_1;
RIN_A_CTRL_WREG_intermed_3 <= RIN_A_CTRL_WREG_intermed_2;
RIN_A_CTRL_WREG_intermed_4 <= RIN_A_CTRL_WREG_intermed_3;
V_A_CTRL_WREG_shadow_intermed_1 <= V_A_CTRL_WREG_shadow;
V_A_CTRL_WREG_shadow_intermed_2 <= V_A_CTRL_WREG_shadow_intermed_1;
V_A_CTRL_WREG_shadow_intermed_3 <= V_A_CTRL_WREG_shadow_intermed_2;
V_A_CTRL_WREG_shadow_intermed_4 <= V_A_CTRL_WREG_shadow_intermed_3;
R_A_CTRL_WREG_intermed_1 <= R.A.CTRL.WREG;
R_A_CTRL_WREG_intermed_2 <= R_A_CTRL_WREG_intermed_1;
R_A_CTRL_WREG_intermed_3 <= R_A_CTRL_WREG_intermed_2;
V_X_ANNUL_ALL_shadow_intermed_1 <= V_X_ANNUL_ALL_shadow;
V_X_ANNUL_ALL_shadow_intermed_2 <= V_X_ANNUL_ALL_shadow_intermed_1;
V_X_ANNUL_ALL_shadow_intermed_3 <= V_X_ANNUL_ALL_shadow_intermed_2;
V_X_ANNUL_ALL_shadow_intermed_4 <= V_X_ANNUL_ALL_shadow_intermed_3;
R_M_CTRL_WREG_intermed_1 <= R.M.CTRL.WREG;
RIN_X_ANNUL_ALL_intermed_1 <= RIN.X.ANNUL_ALL;
RIN_X_ANNUL_ALL_intermed_2 <= RIN_X_ANNUL_ALL_intermed_1;
RIN_X_ANNUL_ALL_intermed_3 <= RIN_X_ANNUL_ALL_intermed_2;
RIN_X_ANNUL_ALL_intermed_4 <= RIN_X_ANNUL_ALL_intermed_3;
RIN_X_ANNUL_ALL_intermed_5 <= RIN_X_ANNUL_ALL_intermed_4;
V_M_CTRL_WREG_shadow_intermed_1 <= V_M_CTRL_WREG_shadow;
V_M_CTRL_WREG_shadow_intermed_2 <= V_M_CTRL_WREG_shadow_intermed_1;
R_E_CTRL_WREG_intermed_1 <= R.E.CTRL.WREG;
R_E_CTRL_WREG_intermed_2 <= R_E_CTRL_WREG_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_1 <= V_A_CTRL_ANNUL_shadow;
V_A_CTRL_ANNUL_shadow_intermed_2 <= V_A_CTRL_ANNUL_shadow_intermed_1;
V_A_CTRL_ANNUL_shadow_intermed_3 <= V_A_CTRL_ANNUL_shadow_intermed_2;
V_A_CTRL_ANNUL_shadow_intermed_4 <= V_A_CTRL_ANNUL_shadow_intermed_3;
RIN_E_CTRL_WREG_intermed_1 <= RIN.E.CTRL.WREG;
RIN_E_CTRL_WREG_intermed_2 <= RIN_E_CTRL_WREG_intermed_1;
RIN_E_CTRL_WREG_intermed_3 <= RIN_E_CTRL_WREG_intermed_2;
V_E_CTRL_WREG_shadow_intermed_1 <= V_E_CTRL_WREG_shadow;
V_E_CTRL_WREG_shadow_intermed_2 <= V_E_CTRL_WREG_shadow_intermed_1;
V_E_CTRL_WREG_shadow_intermed_3 <= V_E_CTRL_WREG_shadow_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC ( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC ( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC ( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC ( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC ( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC ( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
V_X_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_X_CTRL_TT3DOWNTO0_shadow;
V_X_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_X_CTRL_TT3DOWNTO0_shadow_intermed_1;
R_M_CTRL_TT3DOWNTO0_intermed_1 <= R.M.CTRL.TT( 3 DOWNTO 0 );
R_M_CTRL_TT3DOWNTO0_intermed_2 <= R_M_CTRL_TT3DOWNTO0_intermed_1;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_3 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2;
R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
R_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= R_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
R_A_CTRL_TT3DOWNTO0_intermed_1 <= R.A.CTRL.TT( 3 DOWNTO 0 );
R_A_CTRL_TT3DOWNTO0_intermed_2 <= R_A_CTRL_TT3DOWNTO0_intermed_1;
R_A_CTRL_TT3DOWNTO0_intermed_3 <= R_A_CTRL_TT3DOWNTO0_intermed_2;
R_A_CTRL_TT3DOWNTO0_intermed_4 <= R_A_CTRL_TT3DOWNTO0_intermed_3;
RIN_A_CTRL_TT3DOWNTO0_intermed_1 <= RIN.A.CTRL.TT( 3 DOWNTO 0 );
RIN_A_CTRL_TT3DOWNTO0_intermed_2 <= RIN_A_CTRL_TT3DOWNTO0_intermed_1;
RIN_A_CTRL_TT3DOWNTO0_intermed_3 <= RIN_A_CTRL_TT3DOWNTO0_intermed_2;
RIN_A_CTRL_TT3DOWNTO0_intermed_4 <= RIN_A_CTRL_TT3DOWNTO0_intermed_3;
RIN_A_CTRL_TT3DOWNTO0_intermed_5 <= RIN_A_CTRL_TT3DOWNTO0_intermed_4;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_A_CTRL_TT3DOWNTO0_shadow;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_2;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_4 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_3;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_5 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_4;
RIN_W_S_TT3DOWNTO0_intermed_1 <= RIN.W.S.TT( 3 DOWNTO 0 );
RIN_W_S_TT3DOWNTO0_intermed_2 <= RIN_W_S_TT3DOWNTO0_intermed_1;
R_E_CTRL_TT3DOWNTO0_intermed_1 <= R.E.CTRL.TT( 3 DOWNTO 0 );
R_E_CTRL_TT3DOWNTO0_intermed_2 <= R_E_CTRL_TT3DOWNTO0_intermed_1;
R_E_CTRL_TT3DOWNTO0_intermed_3 <= R_E_CTRL_TT3DOWNTO0_intermed_2;
RIN_W_S_TT3DOWNTO0_intermed_1 <= RIN.W.S.TT ( 3 DOWNTO 0 );
RIN_M_CTRL_TT3DOWNTO0_intermed_1 <= RIN.M.CTRL.TT( 3 DOWNTO 0 );
RIN_M_CTRL_TT3DOWNTO0_intermed_2 <= RIN_M_CTRL_TT3DOWNTO0_intermed_1;
RIN_M_CTRL_TT3DOWNTO0_intermed_3 <= RIN_M_CTRL_TT3DOWNTO0_intermed_2;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_M_CTRL_TT3DOWNTO0_shadow;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_M_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_M_CTRL_TT3DOWNTO0_shadow_intermed_2;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_3 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
R_W_S_TT3DOWNTO0_intermed_1 <= R.W.S.TT( 3 DOWNTO 0 );
R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 );
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_E_CTRL_TT3DOWNTO0_shadow;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_2;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_4 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_3;
RIN_X_CTRL_TT3DOWNTO0_intermed_1 <= RIN.X.CTRL.TT( 3 DOWNTO 0 );
RIN_X_CTRL_TT3DOWNTO0_intermed_2 <= RIN_X_CTRL_TT3DOWNTO0_intermed_1;
V_W_S_TT3DOWNTO0_shadow_intermed_1 <= V_W_S_TT3DOWNTO0_shadow;
V_W_S_TT3DOWNTO0_shadow_intermed_2 <= V_W_S_TT3DOWNTO0_shadow_intermed_1;
R_X_CTRL_TT3DOWNTO0_intermed_1 <= R.X.CTRL.TT( 3 DOWNTO 0 );
RIN_E_CTRL_TT3DOWNTO0_intermed_1 <= RIN.E.CTRL.TT( 3 DOWNTO 0 );
RIN_E_CTRL_TT3DOWNTO0_intermed_2 <= RIN_E_CTRL_TT3DOWNTO0_intermed_1;
RIN_E_CTRL_TT3DOWNTO0_intermed_3 <= RIN_E_CTRL_TT3DOWNTO0_intermed_2;
RIN_E_CTRL_TT3DOWNTO0_intermed_4 <= RIN_E_CTRL_TT3DOWNTO0_intermed_3;
XC_VECTT3DOWNTO0_shadow_intermed_1 <= XC_VECTT3DOWNTO0_shadow;
V_M_RESULT1DOWNTO0_shadow_intermed_1 <= V_M_RESULT1DOWNTO0_shadow;
V_M_RESULT1DOWNTO0_shadow_intermed_2 <= V_M_RESULT1DOWNTO0_shadow_intermed_1;
RIN_M_RESULT1DOWNTO0_intermed_1 <= RIN.M.RESULT( 1 DOWNTO 0 );
RIN_M_RESULT1DOWNTO0_intermed_2 <= RIN_M_RESULT1DOWNTO0_intermed_1;
R_M_RESULT1DOWNTO0_intermed_1 <= R.M.RESULT( 1 DOWNTO 0 );
RIN_M_RESULT1DOWNTO0_intermed_1 <= RIN.M.RESULT ( 1 DOWNTO 0 );
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
V_X_DATA031_shadow_intermed_3 <= V_X_DATA031_shadow_intermed_2;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
RIN_X_DATA031_intermed_3 <= RIN_X_DATA031_intermed_2;
DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 );
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 ) ( 31 );
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
R_X_DATA031_intermed_2 <= R_X_DATA031_intermed_1;
R_X_DATA031_intermed_1 <= R.X.DATA ( 0 )( 31 );
RIN_X_DATA031_intermed_1 <= RIN.X.DATA ( 0 )( 31 );
V_X_DATA031_shadow_intermed_1 <= V_X_DATA031_shadow;
V_X_DATA031_shadow_intermed_2 <= V_X_DATA031_shadow_intermed_1;
RIN_X_DATA031_intermed_1 <= RIN.X.DATA( 0 )( 31 );
RIN_X_DATA031_intermed_2 <= RIN_X_DATA031_intermed_1;
DCO_DATA031_intermed_1 <= DCO.DATA ( 0 )( 31 );
R_X_DATA031_intermed_1 <= R.X.DATA( 0 )( 31 );
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
V_A_CTRL_INST19_shadow_intermed_3 <= V_A_CTRL_INST19_shadow_intermed_2;
V_E_CTRL_INST19_shadow_intermed_1 <= V_E_CTRL_INST19_shadow;
V_E_CTRL_INST19_shadow_intermed_2 <= V_E_CTRL_INST19_shadow_intermed_1;
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
RIN_A_CTRL_INST19_intermed_3 <= RIN_A_CTRL_INST19_intermed_2;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST ( 19 );
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST( 19 );
RIN_E_CTRL_INST19_intermed_2 <= RIN_E_CTRL_INST19_intermed_1;
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
DE_INST19_shadow_intermed_2 <= DE_INST19_shadow_intermed_1;
R_E_CTRL_INST19_intermed_1 <= R.E.CTRL.INST( 19 );
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
R_A_CTRL_INST19_intermed_2 <= R_A_CTRL_INST19_intermed_1;
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST ( 19 );
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST ( 20 );
RIN_A_CTRL_INST20_intermed_2 <= RIN_A_CTRL_INST20_intermed_1;
R_A_CTRL_INST20_intermed_1 <= R.A.CTRL.INST ( 20 );
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST( 20 );
RIN_A_CTRL_INST20_intermed_2 <= RIN_A_CTRL_INST20_intermed_1;
RIN_A_CTRL_INST20_intermed_3 <= RIN_A_CTRL_INST20_intermed_2;
V_E_CTRL_INST20_shadow_intermed_1 <= V_E_CTRL_INST20_shadow;
V_E_CTRL_INST20_shadow_intermed_2 <= V_E_CTRL_INST20_shadow_intermed_1;
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
V_A_CTRL_INST20_shadow_intermed_2 <= V_A_CTRL_INST20_shadow_intermed_1;
V_A_CTRL_INST20_shadow_intermed_3 <= V_A_CTRL_INST20_shadow_intermed_2;
RIN_E_CTRL_INST20_intermed_1 <= RIN.E.CTRL.INST( 20 );
RIN_E_CTRL_INST20_intermed_2 <= RIN_E_CTRL_INST20_intermed_1;
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
V_A_CTRL_INST20_shadow_intermed_2 <= V_A_CTRL_INST20_shadow_intermed_1;
RIN_E_CTRL_INST20_intermed_1 <= RIN.E.CTRL.INST ( 20 );
R_E_CTRL_INST20_intermed_1 <= R.E.CTRL.INST( 20 );
DE_INST20_shadow_intermed_1 <= DE_INST20_shadow;
DE_INST20_shadow_intermed_2 <= DE_INST20_shadow_intermed_1;
R_A_CTRL_INST20_intermed_1 <= R.A.CTRL.INST( 20 );
R_A_CTRL_INST20_intermed_2 <= R_A_CTRL_INST20_intermed_1;
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
V_X_DATA00_shadow_intermed_2 <= V_X_DATA00_shadow_intermed_1;
RIN_X_DATA00_intermed_1 <= RIN.X.DATA ( 0 ) ( 0 );
R_X_DATA00_intermed_1 <= R.X.DATA( 0 )( 0 );
R_X_DATA00_intermed_2 <= R_X_DATA00_intermed_1;
RIN_X_DATA00_intermed_1 <= RIN.X.DATA ( 0 )( 0 );
RIN_X_DATA00_intermed_2 <= RIN_X_DATA00_intermed_1;
DCO_DATA00_intermed_1 <= DCO.DATA ( 0 )( 0 );
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
V_X_DATA00_shadow_intermed_2 <= V_X_DATA00_shadow_intermed_1;
V_X_DATA00_shadow_intermed_3 <= V_X_DATA00_shadow_intermed_2;
R_X_DATA00_intermed_1 <= R.X.DATA ( 0 )( 0 );
RIN_X_DATA00_intermed_1 <= RIN.X.DATA( 0 )( 0 );
RIN_X_DATA00_intermed_2 <= RIN_X_DATA00_intermed_1;
RIN_X_DATA00_intermed_3 <= RIN_X_DATA00_intermed_2;
R_X_DATA00_intermed_1 <= R.X.DATA( 0 )( 0 );
RIN_X_DATA00_intermed_1 <= RIN.X.DATA ( 0 )( 0 );
DCO_DATA00_intermed_1 <= DCO.DATA ( 0 )( 0 );
V_X_DATA00_shadow_intermed_1 <= V_X_DATA00_shadow;
V_X_DATA00_shadow_intermed_2 <= V_X_DATA00_shadow_intermed_1;
RIN_X_DATA00_intermed_1 <= RIN.X.DATA( 0 )( 0 );
RIN_X_DATA00_intermed_2 <= RIN_X_DATA00_intermed_1;
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA ( 0 ) ( 4 DOWNTO 0 );
R_X_DATA04DOWNTO0_intermed_1 <= R.X.DATA( 0 )( 4 DOWNTO 0 );
R_X_DATA04DOWNTO0_intermed_2 <= R_X_DATA04DOWNTO0_intermed_1;
R_X_DATA04DOWNTO0_intermed_1 <= R.X.DATA ( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_2 <= RIN_X_DATA04DOWNTO0_intermed_1;
RIN_X_DATA04DOWNTO0_intermed_3 <= RIN_X_DATA04DOWNTO0_intermed_2;
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
V_X_DATA04DOWNTO0_shadow_intermed_2 <= V_X_DATA04DOWNTO0_shadow_intermed_1;
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
V_X_DATA04DOWNTO0_shadow_intermed_2 <= V_X_DATA04DOWNTO0_shadow_intermed_1;
V_X_DATA04DOWNTO0_shadow_intermed_3 <= V_X_DATA04DOWNTO0_shadow_intermed_2;
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA ( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_2 <= RIN_X_DATA04DOWNTO0_intermed_1;
DCO_DATA04DOWNTO0_intermed_1 <= DCO.DATA ( 0 )( 4 DOWNTO 0 );
R_X_DATA04DOWNTO0_intermed_1 <= R.X.DATA( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_2 <= RIN_X_DATA04DOWNTO0_intermed_1;
V_X_DATA04DOWNTO0_shadow_intermed_1 <= V_X_DATA04DOWNTO0_shadow;
V_X_DATA04DOWNTO0_shadow_intermed_2 <= V_X_DATA04DOWNTO0_shadow_intermed_1;
DCO_DATA04DOWNTO0_intermed_1 <= DCO.DATA ( 0 )( 4 DOWNTO 0 );
RIN_X_DATA04DOWNTO0_intermed_1 <= RIN.X.DATA ( 0 )( 4 DOWNTO 0 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC ( 31 DOWNTO 2 );
R_A_CTRL_INST24_intermed_1 <= R.A.CTRL.INST( 24 );
R_A_CTRL_INST24_intermed_2 <= R_A_CTRL_INST24_intermed_1;
RIN_E_CTRL_INST24_intermed_1 <= RIN.E.CTRL.INST( 24 );
RIN_E_CTRL_INST24_intermed_2 <= RIN_E_CTRL_INST24_intermed_1;
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST( 24 );
RIN_A_CTRL_INST24_intermed_2 <= RIN_A_CTRL_INST24_intermed_1;
RIN_A_CTRL_INST24_intermed_3 <= RIN_A_CTRL_INST24_intermed_2;
R_E_CTRL_INST24_intermed_1 <= R.E.CTRL.INST( 24 );
R_A_CTRL_INST24_intermed_1 <= R.A.CTRL.INST ( 24 );
V_A_CTRL_INST24_shadow_intermed_1 <= V_A_CTRL_INST24_shadow;
V_A_CTRL_INST24_shadow_intermed_2 <= V_A_CTRL_INST24_shadow_intermed_1;
V_A_CTRL_INST24_shadow_intermed_3 <= V_A_CTRL_INST24_shadow_intermed_2;
V_E_CTRL_INST24_shadow_intermed_1 <= V_E_CTRL_INST24_shadow;
V_E_CTRL_INST24_shadow_intermed_2 <= V_E_CTRL_INST24_shadow_intermed_1;
DE_INST24_shadow_intermed_1 <= DE_INST24_shadow;
DE_INST24_shadow_intermed_2 <= DE_INST24_shadow_intermed_1;
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST ( 24 );
RIN_A_CTRL_INST24_intermed_2 <= RIN_A_CTRL_INST24_intermed_1;
V_A_CTRL_INST24_shadow_intermed_1 <= V_A_CTRL_INST24_shadow;
V_A_CTRL_INST24_shadow_intermed_2 <= V_A_CTRL_INST24_shadow_intermed_1;
RIN_E_CTRL_INST24_intermed_1 <= RIN.E.CTRL.INST ( 24 );
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST ( 19 );
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
RIN_M_Y31_intermed_1 <= RIN.M.Y ( 31 );
V_M_Y31_shadow_intermed_1 <= V_M_Y31_shadow;
V_M_Y31_shadow_intermed_2 <= V_M_Y31_shadow_intermed_1;
RIN_M_Y31_intermed_1 <= RIN.M.Y( 31 );
RIN_M_Y31_intermed_2 <= RIN_M_Y31_intermed_1;
R_M_Y31_intermed_1 <= R.M.Y( 31 );
DSUIN_CRDY2_intermed_1 <= DSUIN.CRDY ( 2 );
VDSU_CRDY2_shadow_intermed_1 <= VDSU_CRDY2_shadow;
VDSU_CRDY2_shadow_intermed_2 <= VDSU_CRDY2_shadow_intermed_1;
DSUIN_CRDY2_intermed_1 <= DSUIN.CRDY( 2 );
DSUIN_CRDY2_intermed_2 <= DSUIN_CRDY2_intermed_1;
DSUR_CRDY2_intermed_1 <= DSUR.CRDY( 2 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC ( 31 DOWNTO 2 );
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
DE_INST_shadow_intermed_1 <= DE_INST_shadow;
DE_INST_shadow_intermed_2 <= DE_INST_shadow_intermed_1;
V_A_CTRL_INST_shadow_intermed_1 <= V_A_CTRL_INST_shadow;
V_A_CTRL_INST_shadow_intermed_2 <= V_A_CTRL_INST_shadow_intermed_1;
RIN_A_CTRL_INST_intermed_1 <= RIN.A.CTRL.INST;
RIN_A_CTRL_INST_intermed_2 <= RIN_A_CTRL_INST_intermed_1;
RIN_E_CTRL_INST_intermed_1 <= RIN.E.CTRL.INST;
R_A_CTRL_INST_intermed_1 <= R.A.CTRL.INST;
RIN_D_CNT_intermed_1 <= RIN.D.CNT;
RIN_D_CNT_intermed_2 <= RIN_D_CNT_intermed_1;
RIN_D_CNT_intermed_3 <= RIN_D_CNT_intermed_2;
V_A_CTRL_CNT_shadow_intermed_1 <= V_A_CTRL_CNT_shadow;
V_A_CTRL_CNT_shadow_intermed_2 <= V_A_CTRL_CNT_shadow_intermed_1;
R_A_CTRL_CNT_intermed_1 <= R.A.CTRL.CNT;
V_D_CNT_shadow_intermed_1 <= V_D_CNT_shadow;
V_D_CNT_shadow_intermed_2 <= V_D_CNT_shadow_intermed_1;
V_D_CNT_shadow_intermed_3 <= V_D_CNT_shadow_intermed_2;
R_D_CNT_intermed_1 <= R.D.CNT;
R_D_CNT_intermed_2 <= R_D_CNT_intermed_1;
RIN_A_CTRL_CNT_intermed_1 <= RIN.A.CTRL.CNT;
RIN_A_CTRL_CNT_intermed_2 <= RIN_A_CTRL_CNT_intermed_1;
RIN_E_CTRL_CNT_intermed_1 <= RIN.E.CTRL.CNT;
V_A_CTRL_TRAP_shadow_intermed_1 <= V_A_CTRL_TRAP_shadow;
V_A_CTRL_TRAP_shadow_intermed_2 <= V_A_CTRL_TRAP_shadow_intermed_1;
ICO_MEXC_intermed_1 <= ICO.MEXC;
ICO_MEXC_intermed_2 <= ICO_MEXC_intermed_1;
ICO_MEXC_intermed_3 <= ICO_MEXC_intermed_2;
RIN_A_CTRL_TRAP_intermed_1 <= RIN.A.CTRL.TRAP;
RIN_A_CTRL_TRAP_intermed_2 <= RIN_A_CTRL_TRAP_intermed_1;
RIN_E_CTRL_TRAP_intermed_1 <= RIN.E.CTRL.TRAP;
R_D_MEXC_intermed_1 <= R.D.MEXC;
R_D_MEXC_intermed_2 <= R_D_MEXC_intermed_1;
V_D_MEXC_shadow_intermed_1 <= V_D_MEXC_shadow;
V_D_MEXC_shadow_intermed_2 <= V_D_MEXC_shadow_intermed_1;
V_D_MEXC_shadow_intermed_3 <= V_D_MEXC_shadow_intermed_2;
R_A_CTRL_TRAP_intermed_1 <= R.A.CTRL.TRAP;
RIN_D_MEXC_intermed_1 <= RIN.D.MEXC;
RIN_D_MEXC_intermed_2 <= RIN_D_MEXC_intermed_1;
RIN_D_MEXC_intermed_3 <= RIN_D_MEXC_intermed_2;
R_A_CTRL_PV_intermed_1 <= R.A.CTRL.PV;
RIN_E_CTRL_PV_intermed_1 <= RIN.E.CTRL.PV;
V_A_CTRL_PV_shadow_intermed_1 <= V_A_CTRL_PV_shadow;
V_A_CTRL_PV_shadow_intermed_2 <= V_A_CTRL_PV_shadow_intermed_1;
RIN_A_CTRL_PV_intermed_1 <= RIN.A.CTRL.PV;
RIN_A_CTRL_PV_intermed_2 <= RIN_A_CTRL_PV_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC ( 31 DOWNTO 2 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC ( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC ( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC ( 31 DOWNTO 2 );
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC ( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_E_CTRL_INST_intermed_1 <= R.E.CTRL.INST;
DE_INST_shadow_intermed_1 <= DE_INST_shadow;
DE_INST_shadow_intermed_2 <= DE_INST_shadow_intermed_1;
DE_INST_shadow_intermed_3 <= DE_INST_shadow_intermed_2;
V_A_CTRL_INST_shadow_intermed_1 <= V_A_CTRL_INST_shadow;
V_A_CTRL_INST_shadow_intermed_2 <= V_A_CTRL_INST_shadow_intermed_1;
V_A_CTRL_INST_shadow_intermed_3 <= V_A_CTRL_INST_shadow_intermed_2;
V_E_CTRL_INST_shadow_intermed_1 <= V_E_CTRL_INST_shadow;
V_E_CTRL_INST_shadow_intermed_2 <= V_E_CTRL_INST_shadow_intermed_1;
RIN_A_CTRL_INST_intermed_1 <= RIN.A.CTRL.INST;
RIN_A_CTRL_INST_intermed_2 <= RIN_A_CTRL_INST_intermed_1;
RIN_A_CTRL_INST_intermed_3 <= RIN_A_CTRL_INST_intermed_2;
RIN_M_CTRL_INST_intermed_1 <= RIN.M.CTRL.INST;
RIN_E_CTRL_INST_intermed_1 <= RIN.E.CTRL.INST;
RIN_E_CTRL_INST_intermed_2 <= RIN_E_CTRL_INST_intermed_1;
R_A_CTRL_INST_intermed_1 <= R.A.CTRL.INST;
R_A_CTRL_INST_intermed_2 <= R_A_CTRL_INST_intermed_1;
V_E_CTRL_CNT_shadow_intermed_1 <= V_E_CTRL_CNT_shadow;
V_E_CTRL_CNT_shadow_intermed_2 <= V_E_CTRL_CNT_shadow_intermed_1;
RIN_D_CNT_intermed_1 <= RIN.D.CNT;
RIN_D_CNT_intermed_2 <= RIN_D_CNT_intermed_1;
RIN_D_CNT_intermed_3 <= RIN_D_CNT_intermed_2;
RIN_D_CNT_intermed_4 <= RIN_D_CNT_intermed_3;
V_A_CTRL_CNT_shadow_intermed_1 <= V_A_CTRL_CNT_shadow;
V_A_CTRL_CNT_shadow_intermed_2 <= V_A_CTRL_CNT_shadow_intermed_1;
V_A_CTRL_CNT_shadow_intermed_3 <= V_A_CTRL_CNT_shadow_intermed_2;
R_A_CTRL_CNT_intermed_1 <= R.A.CTRL.CNT;
R_A_CTRL_CNT_intermed_2 <= R_A_CTRL_CNT_intermed_1;
V_D_CNT_shadow_intermed_1 <= V_D_CNT_shadow;
V_D_CNT_shadow_intermed_2 <= V_D_CNT_shadow_intermed_1;
V_D_CNT_shadow_intermed_3 <= V_D_CNT_shadow_intermed_2;
V_D_CNT_shadow_intermed_4 <= V_D_CNT_shadow_intermed_3;
R_D_CNT_intermed_1 <= R.D.CNT;
R_D_CNT_intermed_2 <= R_D_CNT_intermed_1;
R_D_CNT_intermed_3 <= R_D_CNT_intermed_2;
R_E_CTRL_CNT_intermed_1 <= R.E.CTRL.CNT;
RIN_A_CTRL_CNT_intermed_1 <= RIN.A.CTRL.CNT;
RIN_A_CTRL_CNT_intermed_2 <= RIN_A_CTRL_CNT_intermed_1;
RIN_A_CTRL_CNT_intermed_3 <= RIN_A_CTRL_CNT_intermed_2;
RIN_M_CTRL_CNT_intermed_1 <= RIN.M.CTRL.CNT;
RIN_E_CTRL_CNT_intermed_1 <= RIN.E.CTRL.CNT;
RIN_E_CTRL_CNT_intermed_2 <= RIN_E_CTRL_CNT_intermed_1;
V_A_CTRL_TRAP_shadow_intermed_1 <= V_A_CTRL_TRAP_shadow;
V_A_CTRL_TRAP_shadow_intermed_2 <= V_A_CTRL_TRAP_shadow_intermed_1;
V_A_CTRL_TRAP_shadow_intermed_3 <= V_A_CTRL_TRAP_shadow_intermed_2;
ICO_MEXC_intermed_1 <= ICO.MEXC;
ICO_MEXC_intermed_2 <= ICO_MEXC_intermed_1;
ICO_MEXC_intermed_3 <= ICO_MEXC_intermed_2;
ICO_MEXC_intermed_4 <= ICO_MEXC_intermed_3;
R_E_CTRL_TRAP_intermed_1 <= R.E.CTRL.TRAP;
RIN_A_CTRL_TRAP_intermed_1 <= RIN.A.CTRL.TRAP;
RIN_A_CTRL_TRAP_intermed_2 <= RIN_A_CTRL_TRAP_intermed_1;
RIN_A_CTRL_TRAP_intermed_3 <= RIN_A_CTRL_TRAP_intermed_2;
V_E_CTRL_TRAP_shadow_intermed_1 <= V_E_CTRL_TRAP_shadow;
V_E_CTRL_TRAP_shadow_intermed_2 <= V_E_CTRL_TRAP_shadow_intermed_1;
RIN_E_CTRL_TRAP_intermed_1 <= RIN.E.CTRL.TRAP;
RIN_E_CTRL_TRAP_intermed_2 <= RIN_E_CTRL_TRAP_intermed_1;
R_D_MEXC_intermed_1 <= R.D.MEXC;
R_D_MEXC_intermed_2 <= R_D_MEXC_intermed_1;
R_D_MEXC_intermed_3 <= R_D_MEXC_intermed_2;
V_D_MEXC_shadow_intermed_1 <= V_D_MEXC_shadow;
V_D_MEXC_shadow_intermed_2 <= V_D_MEXC_shadow_intermed_1;
V_D_MEXC_shadow_intermed_3 <= V_D_MEXC_shadow_intermed_2;
V_D_MEXC_shadow_intermed_4 <= V_D_MEXC_shadow_intermed_3;
R_A_CTRL_TRAP_intermed_1 <= R.A.CTRL.TRAP;
R_A_CTRL_TRAP_intermed_2 <= R_A_CTRL_TRAP_intermed_1;
RIN_M_CTRL_TRAP_intermed_1 <= RIN.M.CTRL.TRAP;
RIN_D_MEXC_intermed_1 <= RIN.D.MEXC;
RIN_D_MEXC_intermed_2 <= RIN_D_MEXC_intermed_1;
RIN_D_MEXC_intermed_3 <= RIN_D_MEXC_intermed_2;
RIN_D_MEXC_intermed_4 <= RIN_D_MEXC_intermed_3;
V_E_CTRL_PV_shadow_intermed_1 <= V_E_CTRL_PV_shadow;
V_E_CTRL_PV_shadow_intermed_2 <= V_E_CTRL_PV_shadow_intermed_1;
R_E_CTRL_PV_intermed_1 <= R.E.CTRL.PV;
R_A_CTRL_PV_intermed_1 <= R.A.CTRL.PV;
R_A_CTRL_PV_intermed_2 <= R_A_CTRL_PV_intermed_1;
RIN_E_CTRL_PV_intermed_1 <= RIN.E.CTRL.PV;
RIN_E_CTRL_PV_intermed_2 <= RIN_E_CTRL_PV_intermed_1;
RIN_M_CTRL_PV_intermed_1 <= RIN.M.CTRL.PV;
V_A_CTRL_PV_shadow_intermed_1 <= V_A_CTRL_PV_shadow;
V_A_CTRL_PV_shadow_intermed_2 <= V_A_CTRL_PV_shadow_intermed_1;
V_A_CTRL_PV_shadow_intermed_3 <= V_A_CTRL_PV_shadow_intermed_2;
RIN_A_CTRL_PV_intermed_1 <= RIN.A.CTRL.PV;
RIN_A_CTRL_PV_intermed_2 <= RIN_A_CTRL_PV_intermed_1;
RIN_A_CTRL_PV_intermed_3 <= RIN_A_CTRL_PV_intermed_2;
R_E_CTRL_INST_intermed_1 <= R.E.CTRL.INST;
R_E_CTRL_INST_intermed_2 <= R_E_CTRL_INST_intermed_1;
R_M_CTRL_INST_intermed_1 <= R.M.CTRL.INST;
DE_INST_shadow_intermed_1 <= DE_INST_shadow;
DE_INST_shadow_intermed_2 <= DE_INST_shadow_intermed_1;
DE_INST_shadow_intermed_3 <= DE_INST_shadow_intermed_2;
DE_INST_shadow_intermed_4 <= DE_INST_shadow_intermed_3;
V_A_CTRL_INST_shadow_intermed_1 <= V_A_CTRL_INST_shadow;
V_A_CTRL_INST_shadow_intermed_2 <= V_A_CTRL_INST_shadow_intermed_1;
V_A_CTRL_INST_shadow_intermed_3 <= V_A_CTRL_INST_shadow_intermed_2;
V_A_CTRL_INST_shadow_intermed_4 <= V_A_CTRL_INST_shadow_intermed_3;
V_E_CTRL_INST_shadow_intermed_1 <= V_E_CTRL_INST_shadow;
V_E_CTRL_INST_shadow_intermed_2 <= V_E_CTRL_INST_shadow_intermed_1;
V_E_CTRL_INST_shadow_intermed_3 <= V_E_CTRL_INST_shadow_intermed_2;
RIN_X_CTRL_INST_intermed_1 <= RIN.X.CTRL.INST;
RIN_A_CTRL_INST_intermed_1 <= RIN.A.CTRL.INST;
RIN_A_CTRL_INST_intermed_2 <= RIN_A_CTRL_INST_intermed_1;
RIN_A_CTRL_INST_intermed_3 <= RIN_A_CTRL_INST_intermed_2;
RIN_A_CTRL_INST_intermed_4 <= RIN_A_CTRL_INST_intermed_3;
RIN_M_CTRL_INST_intermed_1 <= RIN.M.CTRL.INST;
RIN_M_CTRL_INST_intermed_2 <= RIN_M_CTRL_INST_intermed_1;
RIN_E_CTRL_INST_intermed_1 <= RIN.E.CTRL.INST;
RIN_E_CTRL_INST_intermed_2 <= RIN_E_CTRL_INST_intermed_1;
RIN_E_CTRL_INST_intermed_3 <= RIN_E_CTRL_INST_intermed_2;
V_M_CTRL_INST_shadow_intermed_1 <= V_M_CTRL_INST_shadow;
V_M_CTRL_INST_shadow_intermed_2 <= V_M_CTRL_INST_shadow_intermed_1;
R_A_CTRL_INST_intermed_1 <= R.A.CTRL.INST;
R_A_CTRL_INST_intermed_2 <= R_A_CTRL_INST_intermed_1;
R_A_CTRL_INST_intermed_3 <= R_A_CTRL_INST_intermed_2;
V_E_CTRL_CNT_shadow_intermed_1 <= V_E_CTRL_CNT_shadow;
V_E_CTRL_CNT_shadow_intermed_2 <= V_E_CTRL_CNT_shadow_intermed_1;
V_E_CTRL_CNT_shadow_intermed_3 <= V_E_CTRL_CNT_shadow_intermed_2;
RIN_D_CNT_intermed_1 <= RIN.D.CNT;
RIN_D_CNT_intermed_2 <= RIN_D_CNT_intermed_1;
RIN_D_CNT_intermed_3 <= RIN_D_CNT_intermed_2;
RIN_D_CNT_intermed_4 <= RIN_D_CNT_intermed_3;
RIN_D_CNT_intermed_5 <= RIN_D_CNT_intermed_4;
R_M_CTRL_CNT_intermed_1 <= R.M.CTRL.CNT;
V_A_CTRL_CNT_shadow_intermed_1 <= V_A_CTRL_CNT_shadow;
V_A_CTRL_CNT_shadow_intermed_2 <= V_A_CTRL_CNT_shadow_intermed_1;
V_A_CTRL_CNT_shadow_intermed_3 <= V_A_CTRL_CNT_shadow_intermed_2;
V_A_CTRL_CNT_shadow_intermed_4 <= V_A_CTRL_CNT_shadow_intermed_3;
R_A_CTRL_CNT_intermed_1 <= R.A.CTRL.CNT;
R_A_CTRL_CNT_intermed_2 <= R_A_CTRL_CNT_intermed_1;
R_A_CTRL_CNT_intermed_3 <= R_A_CTRL_CNT_intermed_2;
V_D_CNT_shadow_intermed_1 <= V_D_CNT_shadow;
V_D_CNT_shadow_intermed_2 <= V_D_CNT_shadow_intermed_1;
V_D_CNT_shadow_intermed_3 <= V_D_CNT_shadow_intermed_2;
V_D_CNT_shadow_intermed_4 <= V_D_CNT_shadow_intermed_3;
V_D_CNT_shadow_intermed_5 <= V_D_CNT_shadow_intermed_4;
R_D_CNT_intermed_1 <= R.D.CNT;
R_D_CNT_intermed_2 <= R_D_CNT_intermed_1;
R_D_CNT_intermed_3 <= R_D_CNT_intermed_2;
R_D_CNT_intermed_4 <= R_D_CNT_intermed_3;
R_E_CTRL_CNT_intermed_1 <= R.E.CTRL.CNT;
R_E_CTRL_CNT_intermed_2 <= R_E_CTRL_CNT_intermed_1;
RIN_X_CTRL_CNT_intermed_1 <= RIN.X.CTRL.CNT;
RIN_A_CTRL_CNT_intermed_1 <= RIN.A.CTRL.CNT;
RIN_A_CTRL_CNT_intermed_2 <= RIN_A_CTRL_CNT_intermed_1;
RIN_A_CTRL_CNT_intermed_3 <= RIN_A_CTRL_CNT_intermed_2;
RIN_A_CTRL_CNT_intermed_4 <= RIN_A_CTRL_CNT_intermed_3;
RIN_M_CTRL_CNT_intermed_1 <= RIN.M.CTRL.CNT;
RIN_M_CTRL_CNT_intermed_2 <= RIN_M_CTRL_CNT_intermed_1;
RIN_E_CTRL_CNT_intermed_1 <= RIN.E.CTRL.CNT;
RIN_E_CTRL_CNT_intermed_2 <= RIN_E_CTRL_CNT_intermed_1;
RIN_E_CTRL_CNT_intermed_3 <= RIN_E_CTRL_CNT_intermed_2;
V_M_CTRL_CNT_shadow_intermed_1 <= V_M_CTRL_CNT_shadow;
V_M_CTRL_CNT_shadow_intermed_2 <= V_M_CTRL_CNT_shadow_intermed_1;
V_E_CTRL_PV_shadow_intermed_1 <= V_E_CTRL_PV_shadow;
V_E_CTRL_PV_shadow_intermed_2 <= V_E_CTRL_PV_shadow_intermed_1;
V_E_CTRL_PV_shadow_intermed_3 <= V_E_CTRL_PV_shadow_intermed_2;
R_M_CTRL_PV_intermed_1 <= R.M.CTRL.PV;
R_E_CTRL_PV_intermed_1 <= R.E.CTRL.PV;
R_E_CTRL_PV_intermed_2 <= R_E_CTRL_PV_intermed_1;
R_A_CTRL_PV_intermed_1 <= R.A.CTRL.PV;
R_A_CTRL_PV_intermed_2 <= R_A_CTRL_PV_intermed_1;
R_A_CTRL_PV_intermed_3 <= R_A_CTRL_PV_intermed_2;
RIN_E_CTRL_PV_intermed_1 <= RIN.E.CTRL.PV;
RIN_E_CTRL_PV_intermed_2 <= RIN_E_CTRL_PV_intermed_1;
RIN_E_CTRL_PV_intermed_3 <= RIN_E_CTRL_PV_intermed_2;
RIN_X_CTRL_PV_intermed_1 <= RIN.X.CTRL.PV;
RIN_M_CTRL_PV_intermed_1 <= RIN.M.CTRL.PV;
RIN_M_CTRL_PV_intermed_2 <= RIN_M_CTRL_PV_intermed_1;
V_A_CTRL_PV_shadow_intermed_1 <= V_A_CTRL_PV_shadow;
V_A_CTRL_PV_shadow_intermed_2 <= V_A_CTRL_PV_shadow_intermed_1;
V_A_CTRL_PV_shadow_intermed_3 <= V_A_CTRL_PV_shadow_intermed_2;
V_A_CTRL_PV_shadow_intermed_4 <= V_A_CTRL_PV_shadow_intermed_3;
V_M_CTRL_PV_shadow_intermed_1 <= V_M_CTRL_PV_shadow;
V_M_CTRL_PV_shadow_intermed_2 <= V_M_CTRL_PV_shadow_intermed_1;
RIN_A_CTRL_PV_intermed_1 <= RIN.A.CTRL.PV;
RIN_A_CTRL_PV_intermed_2 <= RIN_A_CTRL_PV_intermed_1;
RIN_A_CTRL_PV_intermed_3 <= RIN_A_CTRL_PV_intermed_2;
RIN_A_CTRL_PV_intermed_4 <= RIN_A_CTRL_PV_intermed_3;
V_A_CTRL_INST19_shadow_intermed_1 <= V_A_CTRL_INST19_shadow;
V_A_CTRL_INST19_shadow_intermed_2 <= V_A_CTRL_INST19_shadow_intermed_1;
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
RIN_A_CTRL_INST19_intermed_2 <= RIN_A_CTRL_INST19_intermed_1;
RIN_E_CTRL_INST19_intermed_1 <= RIN.E.CTRL.INST( 19 );
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
DE_INST19_shadow_intermed_2 <= DE_INST19_shadow_intermed_1;
R_A_CTRL_INST19_intermed_1 <= R.A.CTRL.INST( 19 );
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST( 20 );
RIN_A_CTRL_INST20_intermed_2 <= RIN_A_CTRL_INST20_intermed_1;
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
V_A_CTRL_INST20_shadow_intermed_2 <= V_A_CTRL_INST20_shadow_intermed_1;
RIN_E_CTRL_INST20_intermed_1 <= RIN.E.CTRL.INST( 20 );
DE_INST20_shadow_intermed_1 <= DE_INST20_shadow;
DE_INST20_shadow_intermed_2 <= DE_INST20_shadow_intermed_1;
R_A_CTRL_INST20_intermed_1 <= R.A.CTRL.INST( 20 );
R_A_CTRL_INST24_intermed_1 <= R.A.CTRL.INST( 24 );
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST( 24 );
RIN_A_CTRL_INST24_intermed_2 <= RIN_A_CTRL_INST24_intermed_1;
RIN_E_CTRL_INST24_intermed_1 <= RIN.E.CTRL.INST( 24 );
V_A_CTRL_INST24_shadow_intermed_1 <= V_A_CTRL_INST24_shadow;
V_A_CTRL_INST24_shadow_intermed_2 <= V_A_CTRL_INST24_shadow_intermed_1;
DE_INST24_shadow_intermed_1 <= DE_INST24_shadow;
DE_INST24_shadow_intermed_2 <= DE_INST24_shadow_intermed_1;
RIN_A_CTRL_INST19_intermed_1 <= RIN.A.CTRL.INST( 19 );
DE_INST19_shadow_intermed_1 <= DE_INST19_shadow;
V_X_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO4_shadow;
V_X_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO4_shadow_intermed_2;
IR_ADDR31DOWNTO4_intermed_1 <= IR.ADDR( 31 DOWNTO 4 );
VIR_ADDR31DOWNTO4_shadow_intermed_1 <= VIR_ADDR31DOWNTO4_shadow;
VIR_ADDR31DOWNTO4_shadow_intermed_2 <= VIR_ADDR31DOWNTO4_shadow_intermed_1;
RIN_F_PC31DOWNTO4_intermed_1 <= RIN.F.PC( 31 DOWNTO 4 );
RIN_A_CTRL_PC31DOWNTO4_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 4 );
RIN_A_CTRL_PC31DOWNTO4_intermed_2 <= RIN_A_CTRL_PC31DOWNTO4_intermed_1;
RIN_A_CTRL_PC31DOWNTO4_intermed_3 <= RIN_A_CTRL_PC31DOWNTO4_intermed_2;
RIN_A_CTRL_PC31DOWNTO4_intermed_4 <= RIN_A_CTRL_PC31DOWNTO4_intermed_3;
RIN_A_CTRL_PC31DOWNTO4_intermed_5 <= RIN_A_CTRL_PC31DOWNTO4_intermed_4;
RIN_A_CTRL_PC31DOWNTO4_intermed_6 <= RIN_A_CTRL_PC31DOWNTO4_intermed_5;
R_A_CTRL_PC31DOWNTO4_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 4 );
R_A_CTRL_PC31DOWNTO4_intermed_2 <= R_A_CTRL_PC31DOWNTO4_intermed_1;
R_A_CTRL_PC31DOWNTO4_intermed_3 <= R_A_CTRL_PC31DOWNTO4_intermed_2;
R_A_CTRL_PC31DOWNTO4_intermed_4 <= R_A_CTRL_PC31DOWNTO4_intermed_3;
R_A_CTRL_PC31DOWNTO4_intermed_5 <= R_A_CTRL_PC31DOWNTO4_intermed_4;
R_D_PC31DOWNTO4_intermed_1 <= R.D.PC( 31 DOWNTO 4 );
R_D_PC31DOWNTO4_intermed_2 <= R_D_PC31DOWNTO4_intermed_1;
R_D_PC31DOWNTO4_intermed_3 <= R_D_PC31DOWNTO4_intermed_2;
R_D_PC31DOWNTO4_intermed_4 <= R_D_PC31DOWNTO4_intermed_3;
R_D_PC31DOWNTO4_intermed_5 <= R_D_PC31DOWNTO4_intermed_4;
R_D_PC31DOWNTO4_intermed_6 <= R_D_PC31DOWNTO4_intermed_5;
RIN_X_CTRL_PC31DOWNTO4_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 4 );
RIN_X_CTRL_PC31DOWNTO4_intermed_2 <= RIN_X_CTRL_PC31DOWNTO4_intermed_1;
RIN_X_CTRL_PC31DOWNTO4_intermed_3 <= RIN_X_CTRL_PC31DOWNTO4_intermed_2;
EX_ADD_RES32DOWNTO332DOWNTO5_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO5_shadow;
V_D_PC31DOWNTO4_shadow_intermed_1 <= V_D_PC31DOWNTO4_shadow;
V_D_PC31DOWNTO4_shadow_intermed_2 <= V_D_PC31DOWNTO4_shadow_intermed_1;
V_D_PC31DOWNTO4_shadow_intermed_3 <= V_D_PC31DOWNTO4_shadow_intermed_2;
V_D_PC31DOWNTO4_shadow_intermed_4 <= V_D_PC31DOWNTO4_shadow_intermed_3;
V_D_PC31DOWNTO4_shadow_intermed_5 <= V_D_PC31DOWNTO4_shadow_intermed_4;
V_D_PC31DOWNTO4_shadow_intermed_6 <= V_D_PC31DOWNTO4_shadow_intermed_5;
V_D_PC31DOWNTO4_shadow_intermed_7 <= V_D_PC31DOWNTO4_shadow_intermed_6;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO4_shadow;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_4;
RIN_M_CTRL_PC31DOWNTO4_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 4 );
RIN_M_CTRL_PC31DOWNTO4_intermed_2 <= RIN_M_CTRL_PC31DOWNTO4_intermed_1;
RIN_M_CTRL_PC31DOWNTO4_intermed_3 <= RIN_M_CTRL_PC31DOWNTO4_intermed_2;
RIN_M_CTRL_PC31DOWNTO4_intermed_4 <= RIN_M_CTRL_PC31DOWNTO4_intermed_3;
R_X_CTRL_PC31DOWNTO4_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 4 );
R_X_CTRL_PC31DOWNTO4_intermed_2 <= R_X_CTRL_PC31DOWNTO4_intermed_1;
IRIN_ADDR31DOWNTO4_intermed_1 <= IRIN.ADDR( 31 DOWNTO 4 );
IRIN_ADDR31DOWNTO4_intermed_2 <= IRIN_ADDR31DOWNTO4_intermed_1;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO4_shadow;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_3;
R_M_CTRL_PC31DOWNTO4_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 4 );
R_M_CTRL_PC31DOWNTO4_intermed_2 <= R_M_CTRL_PC31DOWNTO4_intermed_1;
R_M_CTRL_PC31DOWNTO4_intermed_3 <= R_M_CTRL_PC31DOWNTO4_intermed_2;
XC_TRAP_ADDRESS31DOWNTO4_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO4_shadow;
RIN_D_PC31DOWNTO4_intermed_1 <= RIN.D.PC( 31 DOWNTO 4 );
RIN_D_PC31DOWNTO4_intermed_2 <= RIN_D_PC31DOWNTO4_intermed_1;
RIN_D_PC31DOWNTO4_intermed_3 <= RIN_D_PC31DOWNTO4_intermed_2;
RIN_D_PC31DOWNTO4_intermed_4 <= RIN_D_PC31DOWNTO4_intermed_3;
RIN_D_PC31DOWNTO4_intermed_5 <= RIN_D_PC31DOWNTO4_intermed_4;
RIN_D_PC31DOWNTO4_intermed_6 <= RIN_D_PC31DOWNTO4_intermed_5;
RIN_D_PC31DOWNTO4_intermed_7 <= RIN_D_PC31DOWNTO4_intermed_6;
RIN_E_CTRL_PC31DOWNTO4_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 4 );
RIN_E_CTRL_PC31DOWNTO4_intermed_2 <= RIN_E_CTRL_PC31DOWNTO4_intermed_1;
RIN_E_CTRL_PC31DOWNTO4_intermed_3 <= RIN_E_CTRL_PC31DOWNTO4_intermed_2;
RIN_E_CTRL_PC31DOWNTO4_intermed_4 <= RIN_E_CTRL_PC31DOWNTO4_intermed_3;
RIN_E_CTRL_PC31DOWNTO4_intermed_5 <= RIN_E_CTRL_PC31DOWNTO4_intermed_4;
EX_JUMP_ADDRESS31DOWNTO4_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO4_shadow;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO4_shadow;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_5;
R_E_CTRL_PC31DOWNTO4_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 4 );
R_E_CTRL_PC31DOWNTO4_intermed_2 <= R_E_CTRL_PC31DOWNTO4_intermed_1;
R_E_CTRL_PC31DOWNTO4_intermed_3 <= R_E_CTRL_PC31DOWNTO4_intermed_2;
R_E_CTRL_PC31DOWNTO4_intermed_4 <= R_E_CTRL_PC31DOWNTO4_intermed_3;
V_X_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO4_shadow;
V_X_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO4_shadow_intermed_1;
RIN_A_CTRL_PC31DOWNTO4_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 4 );
RIN_A_CTRL_PC31DOWNTO4_intermed_2 <= RIN_A_CTRL_PC31DOWNTO4_intermed_1;
RIN_A_CTRL_PC31DOWNTO4_intermed_3 <= RIN_A_CTRL_PC31DOWNTO4_intermed_2;
RIN_A_CTRL_PC31DOWNTO4_intermed_4 <= RIN_A_CTRL_PC31DOWNTO4_intermed_3;
RIN_A_CTRL_PC31DOWNTO4_intermed_5 <= RIN_A_CTRL_PC31DOWNTO4_intermed_4;
R_A_CTRL_PC31DOWNTO4_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 4 );
R_A_CTRL_PC31DOWNTO4_intermed_2 <= R_A_CTRL_PC31DOWNTO4_intermed_1;
R_A_CTRL_PC31DOWNTO4_intermed_3 <= R_A_CTRL_PC31DOWNTO4_intermed_2;
R_A_CTRL_PC31DOWNTO4_intermed_4 <= R_A_CTRL_PC31DOWNTO4_intermed_3;
R_D_PC31DOWNTO4_intermed_1 <= R.D.PC( 31 DOWNTO 4 );
R_D_PC31DOWNTO4_intermed_2 <= R_D_PC31DOWNTO4_intermed_1;
R_D_PC31DOWNTO4_intermed_3 <= R_D_PC31DOWNTO4_intermed_2;
R_D_PC31DOWNTO4_intermed_4 <= R_D_PC31DOWNTO4_intermed_3;
R_D_PC31DOWNTO4_intermed_5 <= R_D_PC31DOWNTO4_intermed_4;
RIN_X_CTRL_PC31DOWNTO4_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 4 );
RIN_X_CTRL_PC31DOWNTO4_intermed_2 <= RIN_X_CTRL_PC31DOWNTO4_intermed_1;
V_D_PC31DOWNTO4_shadow_intermed_1 <= V_D_PC31DOWNTO4_shadow;
V_D_PC31DOWNTO4_shadow_intermed_2 <= V_D_PC31DOWNTO4_shadow_intermed_1;
V_D_PC31DOWNTO4_shadow_intermed_3 <= V_D_PC31DOWNTO4_shadow_intermed_2;
V_D_PC31DOWNTO4_shadow_intermed_4 <= V_D_PC31DOWNTO4_shadow_intermed_3;
V_D_PC31DOWNTO4_shadow_intermed_5 <= V_D_PC31DOWNTO4_shadow_intermed_4;
V_D_PC31DOWNTO4_shadow_intermed_6 <= V_D_PC31DOWNTO4_shadow_intermed_5;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO4_shadow;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_3;
RIN_M_CTRL_PC31DOWNTO4_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 4 );
RIN_M_CTRL_PC31DOWNTO4_intermed_2 <= RIN_M_CTRL_PC31DOWNTO4_intermed_1;
RIN_M_CTRL_PC31DOWNTO4_intermed_3 <= RIN_M_CTRL_PC31DOWNTO4_intermed_2;
R_X_CTRL_PC31DOWNTO4_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 4 );
IRIN_ADDR31DOWNTO4_intermed_1 <= IRIN.ADDR( 31 DOWNTO 4 );
V_M_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO4_shadow;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_2;
R_M_CTRL_PC31DOWNTO4_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 4 );
R_M_CTRL_PC31DOWNTO4_intermed_2 <= R_M_CTRL_PC31DOWNTO4_intermed_1;
RIN_D_PC31DOWNTO4_intermed_1 <= RIN.D.PC( 31 DOWNTO 4 );
RIN_D_PC31DOWNTO4_intermed_2 <= RIN_D_PC31DOWNTO4_intermed_1;
RIN_D_PC31DOWNTO4_intermed_3 <= RIN_D_PC31DOWNTO4_intermed_2;
RIN_D_PC31DOWNTO4_intermed_4 <= RIN_D_PC31DOWNTO4_intermed_3;
RIN_D_PC31DOWNTO4_intermed_5 <= RIN_D_PC31DOWNTO4_intermed_4;
RIN_D_PC31DOWNTO4_intermed_6 <= RIN_D_PC31DOWNTO4_intermed_5;
RIN_E_CTRL_PC31DOWNTO4_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 4 );
RIN_E_CTRL_PC31DOWNTO4_intermed_2 <= RIN_E_CTRL_PC31DOWNTO4_intermed_1;
RIN_E_CTRL_PC31DOWNTO4_intermed_3 <= RIN_E_CTRL_PC31DOWNTO4_intermed_2;
RIN_E_CTRL_PC31DOWNTO4_intermed_4 <= RIN_E_CTRL_PC31DOWNTO4_intermed_3;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO4_shadow;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_4;
R_E_CTRL_PC31DOWNTO4_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 4 );
R_E_CTRL_PC31DOWNTO4_intermed_2 <= R_E_CTRL_PC31DOWNTO4_intermed_1;
R_E_CTRL_PC31DOWNTO4_intermed_3 <= R_E_CTRL_PC31DOWNTO4_intermed_2;
R_D_PC3DOWNTO2_intermed_1 <= R.D.PC( 3 DOWNTO 2 );
R_D_PC3DOWNTO2_intermed_2 <= R_D_PC3DOWNTO2_intermed_1;
R_D_PC3DOWNTO2_intermed_3 <= R_D_PC3DOWNTO2_intermed_2;
R_D_PC3DOWNTO2_intermed_4 <= R_D_PC3DOWNTO2_intermed_3;
R_D_PC3DOWNTO2_intermed_5 <= R_D_PC3DOWNTO2_intermed_4;
R_D_PC3DOWNTO2_intermed_6 <= R_D_PC3DOWNTO2_intermed_5;
V_D_PC3DOWNTO2_shadow_intermed_1 <= V_D_PC3DOWNTO2_shadow;
V_D_PC3DOWNTO2_shadow_intermed_2 <= V_D_PC3DOWNTO2_shadow_intermed_1;
V_D_PC3DOWNTO2_shadow_intermed_3 <= V_D_PC3DOWNTO2_shadow_intermed_2;
V_D_PC3DOWNTO2_shadow_intermed_4 <= V_D_PC3DOWNTO2_shadow_intermed_3;
V_D_PC3DOWNTO2_shadow_intermed_5 <= V_D_PC3DOWNTO2_shadow_intermed_4;
V_D_PC3DOWNTO2_shadow_intermed_6 <= V_D_PC3DOWNTO2_shadow_intermed_5;
V_D_PC3DOWNTO2_shadow_intermed_7 <= V_D_PC3DOWNTO2_shadow_intermed_6;
VIR_ADDR3DOWNTO2_shadow_intermed_1 <= VIR_ADDR3DOWNTO2_shadow;
VIR_ADDR3DOWNTO2_shadow_intermed_2 <= VIR_ADDR3DOWNTO2_shadow_intermed_1;
RIN_D_PC3DOWNTO2_intermed_1 <= RIN.D.PC( 3 DOWNTO 2 );
RIN_D_PC3DOWNTO2_intermed_2 <= RIN_D_PC3DOWNTO2_intermed_1;
RIN_D_PC3DOWNTO2_intermed_3 <= RIN_D_PC3DOWNTO2_intermed_2;
RIN_D_PC3DOWNTO2_intermed_4 <= RIN_D_PC3DOWNTO2_intermed_3;
RIN_D_PC3DOWNTO2_intermed_5 <= RIN_D_PC3DOWNTO2_intermed_4;
RIN_D_PC3DOWNTO2_intermed_6 <= RIN_D_PC3DOWNTO2_intermed_5;
RIN_D_PC3DOWNTO2_intermed_7 <= RIN_D_PC3DOWNTO2_intermed_6;
R_M_CTRL_PC3DOWNTO2_intermed_1 <= R.M.CTRL.PC( 3 DOWNTO 2 );
R_M_CTRL_PC3DOWNTO2_intermed_2 <= R_M_CTRL_PC3DOWNTO2_intermed_1;
R_M_CTRL_PC3DOWNTO2_intermed_3 <= R_M_CTRL_PC3DOWNTO2_intermed_2;
R_E_CTRL_PC3DOWNTO2_intermed_1 <= R.E.CTRL.PC( 3 DOWNTO 2 );
R_E_CTRL_PC3DOWNTO2_intermed_2 <= R_E_CTRL_PC3DOWNTO2_intermed_1;
R_E_CTRL_PC3DOWNTO2_intermed_3 <= R_E_CTRL_PC3DOWNTO2_intermed_2;
R_E_CTRL_PC3DOWNTO2_intermed_4 <= R_E_CTRL_PC3DOWNTO2_intermed_3;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC3DOWNTO2_shadow;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_3;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_4;
RIN_X_CTRL_PC3DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 3 DOWNTO 2 );
RIN_X_CTRL_PC3DOWNTO2_intermed_2 <= RIN_X_CTRL_PC3DOWNTO2_intermed_1;
RIN_X_CTRL_PC3DOWNTO2_intermed_3 <= RIN_X_CTRL_PC3DOWNTO2_intermed_2;
R_A_CTRL_PC3DOWNTO2_intermed_1 <= R.A.CTRL.PC( 3 DOWNTO 2 );
R_A_CTRL_PC3DOWNTO2_intermed_2 <= R_A_CTRL_PC3DOWNTO2_intermed_1;
R_A_CTRL_PC3DOWNTO2_intermed_3 <= R_A_CTRL_PC3DOWNTO2_intermed_2;
R_A_CTRL_PC3DOWNTO2_intermed_4 <= R_A_CTRL_PC3DOWNTO2_intermed_3;
R_A_CTRL_PC3DOWNTO2_intermed_5 <= R_A_CTRL_PC3DOWNTO2_intermed_4;
V_X_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC3DOWNTO2_shadow;
V_X_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC3DOWNTO2_shadow_intermed_2;
RIN_M_CTRL_PC3DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 3 DOWNTO 2 );
RIN_M_CTRL_PC3DOWNTO2_intermed_2 <= RIN_M_CTRL_PC3DOWNTO2_intermed_1;
RIN_M_CTRL_PC3DOWNTO2_intermed_3 <= RIN_M_CTRL_PC3DOWNTO2_intermed_2;
RIN_M_CTRL_PC3DOWNTO2_intermed_4 <= RIN_M_CTRL_PC3DOWNTO2_intermed_3;
IRIN_ADDR3DOWNTO2_intermed_1 <= IRIN.ADDR( 3 DOWNTO 2 );
IRIN_ADDR3DOWNTO2_intermed_2 <= IRIN_ADDR3DOWNTO2_intermed_1;
EX_JUMP_ADDRESS3DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS3DOWNTO2_shadow;
EX_ADD_RES32DOWNTO34DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO34DOWNTO3_shadow;
RIN_A_CTRL_PC3DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 3 DOWNTO 2 );
RIN_A_CTRL_PC3DOWNTO2_intermed_2 <= RIN_A_CTRL_PC3DOWNTO2_intermed_1;
RIN_A_CTRL_PC3DOWNTO2_intermed_3 <= RIN_A_CTRL_PC3DOWNTO2_intermed_2;
RIN_A_CTRL_PC3DOWNTO2_intermed_4 <= RIN_A_CTRL_PC3DOWNTO2_intermed_3;
RIN_A_CTRL_PC3DOWNTO2_intermed_5 <= RIN_A_CTRL_PC3DOWNTO2_intermed_4;
RIN_A_CTRL_PC3DOWNTO2_intermed_6 <= RIN_A_CTRL_PC3DOWNTO2_intermed_5;
XC_TRAP_ADDRESS3DOWNTO2_shadow_intermed_1 <= XC_TRAP_ADDRESS3DOWNTO2_shadow;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC3DOWNTO2_shadow;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_4;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_5;
IR_ADDR3DOWNTO2_intermed_1 <= IR.ADDR( 3 DOWNTO 2 );
V_M_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC3DOWNTO2_shadow;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_2;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_3;
R_X_CTRL_PC3DOWNTO2_intermed_1 <= R.X.CTRL.PC( 3 DOWNTO 2 );
R_X_CTRL_PC3DOWNTO2_intermed_2 <= R_X_CTRL_PC3DOWNTO2_intermed_1;
RIN_E_CTRL_PC3DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 3 DOWNTO 2 );
RIN_E_CTRL_PC3DOWNTO2_intermed_2 <= RIN_E_CTRL_PC3DOWNTO2_intermed_1;
RIN_E_CTRL_PC3DOWNTO2_intermed_3 <= RIN_E_CTRL_PC3DOWNTO2_intermed_2;
RIN_E_CTRL_PC3DOWNTO2_intermed_4 <= RIN_E_CTRL_PC3DOWNTO2_intermed_3;
RIN_E_CTRL_PC3DOWNTO2_intermed_5 <= RIN_E_CTRL_PC3DOWNTO2_intermed_4;
RIN_F_PC3DOWNTO2_intermed_1 <= RIN.F.PC( 3 DOWNTO 2 );
R_D_PC3DOWNTO2_intermed_1 <= R.D.PC( 3 DOWNTO 2 );
R_D_PC3DOWNTO2_intermed_2 <= R_D_PC3DOWNTO2_intermed_1;
R_D_PC3DOWNTO2_intermed_3 <= R_D_PC3DOWNTO2_intermed_2;
R_D_PC3DOWNTO2_intermed_4 <= R_D_PC3DOWNTO2_intermed_3;
R_D_PC3DOWNTO2_intermed_5 <= R_D_PC3DOWNTO2_intermed_4;
V_D_PC3DOWNTO2_shadow_intermed_1 <= V_D_PC3DOWNTO2_shadow;
V_D_PC3DOWNTO2_shadow_intermed_2 <= V_D_PC3DOWNTO2_shadow_intermed_1;
V_D_PC3DOWNTO2_shadow_intermed_3 <= V_D_PC3DOWNTO2_shadow_intermed_2;
V_D_PC3DOWNTO2_shadow_intermed_4 <= V_D_PC3DOWNTO2_shadow_intermed_3;
V_D_PC3DOWNTO2_shadow_intermed_5 <= V_D_PC3DOWNTO2_shadow_intermed_4;
V_D_PC3DOWNTO2_shadow_intermed_6 <= V_D_PC3DOWNTO2_shadow_intermed_5;
RIN_D_PC3DOWNTO2_intermed_1 <= RIN.D.PC( 3 DOWNTO 2 );
RIN_D_PC3DOWNTO2_intermed_2 <= RIN_D_PC3DOWNTO2_intermed_1;
RIN_D_PC3DOWNTO2_intermed_3 <= RIN_D_PC3DOWNTO2_intermed_2;
RIN_D_PC3DOWNTO2_intermed_4 <= RIN_D_PC3DOWNTO2_intermed_3;
RIN_D_PC3DOWNTO2_intermed_5 <= RIN_D_PC3DOWNTO2_intermed_4;
RIN_D_PC3DOWNTO2_intermed_6 <= RIN_D_PC3DOWNTO2_intermed_5;
R_M_CTRL_PC3DOWNTO2_intermed_1 <= R.M.CTRL.PC( 3 DOWNTO 2 );
R_M_CTRL_PC3DOWNTO2_intermed_2 <= R_M_CTRL_PC3DOWNTO2_intermed_1;
R_E_CTRL_PC3DOWNTO2_intermed_1 <= R.E.CTRL.PC( 3 DOWNTO 2 );
R_E_CTRL_PC3DOWNTO2_intermed_2 <= R_E_CTRL_PC3DOWNTO2_intermed_1;
R_E_CTRL_PC3DOWNTO2_intermed_3 <= R_E_CTRL_PC3DOWNTO2_intermed_2;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC3DOWNTO2_shadow;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_3;
RIN_X_CTRL_PC3DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 3 DOWNTO 2 );
RIN_X_CTRL_PC3DOWNTO2_intermed_2 <= RIN_X_CTRL_PC3DOWNTO2_intermed_1;
R_A_CTRL_PC3DOWNTO2_intermed_1 <= R.A.CTRL.PC( 3 DOWNTO 2 );
R_A_CTRL_PC3DOWNTO2_intermed_2 <= R_A_CTRL_PC3DOWNTO2_intermed_1;
R_A_CTRL_PC3DOWNTO2_intermed_3 <= R_A_CTRL_PC3DOWNTO2_intermed_2;
R_A_CTRL_PC3DOWNTO2_intermed_4 <= R_A_CTRL_PC3DOWNTO2_intermed_3;
V_X_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC3DOWNTO2_shadow;
V_X_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC3DOWNTO2_shadow_intermed_1;
RIN_M_CTRL_PC3DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 3 DOWNTO 2 );
RIN_M_CTRL_PC3DOWNTO2_intermed_2 <= RIN_M_CTRL_PC3DOWNTO2_intermed_1;
RIN_M_CTRL_PC3DOWNTO2_intermed_3 <= RIN_M_CTRL_PC3DOWNTO2_intermed_2;
IRIN_ADDR3DOWNTO2_intermed_1 <= IRIN.ADDR( 3 DOWNTO 2 );
RIN_A_CTRL_PC3DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 3 DOWNTO 2 );
RIN_A_CTRL_PC3DOWNTO2_intermed_2 <= RIN_A_CTRL_PC3DOWNTO2_intermed_1;
RIN_A_CTRL_PC3DOWNTO2_intermed_3 <= RIN_A_CTRL_PC3DOWNTO2_intermed_2;
RIN_A_CTRL_PC3DOWNTO2_intermed_4 <= RIN_A_CTRL_PC3DOWNTO2_intermed_3;
RIN_A_CTRL_PC3DOWNTO2_intermed_5 <= RIN_A_CTRL_PC3DOWNTO2_intermed_4;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC3DOWNTO2_shadow;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_4;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC3DOWNTO2_shadow;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_2;
R_X_CTRL_PC3DOWNTO2_intermed_1 <= R.X.CTRL.PC( 3 DOWNTO 2 );
RIN_E_CTRL_PC3DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 3 DOWNTO 2 );
RIN_E_CTRL_PC3DOWNTO2_intermed_2 <= RIN_E_CTRL_PC3DOWNTO2_intermed_1;
RIN_E_CTRL_PC3DOWNTO2_intermed_3 <= RIN_E_CTRL_PC3DOWNTO2_intermed_2;
RIN_E_CTRL_PC3DOWNTO2_intermed_4 <= RIN_E_CTRL_PC3DOWNTO2_intermed_3;
RIN_E_CTRL_RD6DOWNTO0_intermed_1 <= RIN.E.CTRL.RD( 6 DOWNTO 0 );
RIN_E_CTRL_RD6DOWNTO0_intermed_2 <= RIN_E_CTRL_RD6DOWNTO0_intermed_1;
RIN_E_CTRL_RD6DOWNTO0_intermed_3 <= RIN_E_CTRL_RD6DOWNTO0_intermed_2;
RIN_M_CTRL_RD6DOWNTO0_intermed_1 <= RIN.M.CTRL.RD( 6 DOWNTO 0 );
RIN_M_CTRL_RD6DOWNTO0_intermed_2 <= RIN_M_CTRL_RD6DOWNTO0_intermed_1;
RIN_X_CTRL_RD6DOWNTO0_intermed_1 <= RIN.X.CTRL.RD( 6 DOWNTO 0 );
V_M_CTRL_RD6DOWNTO0_shadow_intermed_1 <= V_M_CTRL_RD6DOWNTO0_shadow;
V_M_CTRL_RD6DOWNTO0_shadow_intermed_2 <= V_M_CTRL_RD6DOWNTO0_shadow_intermed_1;
R_E_CTRL_RD6DOWNTO0_intermed_1 <= R.E.CTRL.RD( 6 DOWNTO 0 );
R_E_CTRL_RD6DOWNTO0_intermed_2 <= R_E_CTRL_RD6DOWNTO0_intermed_1;
V_E_CTRL_RD6DOWNTO0_shadow_intermed_1 <= V_E_CTRL_RD6DOWNTO0_shadow;
V_E_CTRL_RD6DOWNTO0_shadow_intermed_2 <= V_E_CTRL_RD6DOWNTO0_shadow_intermed_1;
V_E_CTRL_RD6DOWNTO0_shadow_intermed_3 <= V_E_CTRL_RD6DOWNTO0_shadow_intermed_2;
V_A_CTRL_RD6DOWNTO0_shadow_intermed_1 <= V_A_CTRL_RD6DOWNTO0_shadow;
V_A_CTRL_RD6DOWNTO0_shadow_intermed_2 <= V_A_CTRL_RD6DOWNTO0_shadow_intermed_1;
V_A_CTRL_RD6DOWNTO0_shadow_intermed_3 <= V_A_CTRL_RD6DOWNTO0_shadow_intermed_2;
V_A_CTRL_RD6DOWNTO0_shadow_intermed_4 <= V_A_CTRL_RD6DOWNTO0_shadow_intermed_3;
R_A_CTRL_RD6DOWNTO0_intermed_1 <= R.A.CTRL.RD( 6 DOWNTO 0 );
R_A_CTRL_RD6DOWNTO0_intermed_2 <= R_A_CTRL_RD6DOWNTO0_intermed_1;
R_A_CTRL_RD6DOWNTO0_intermed_3 <= R_A_CTRL_RD6DOWNTO0_intermed_2;
RIN_A_CTRL_RD6DOWNTO0_intermed_1 <= RIN.A.CTRL.RD( 6 DOWNTO 0 );
RIN_A_CTRL_RD6DOWNTO0_intermed_2 <= RIN_A_CTRL_RD6DOWNTO0_intermed_1;
RIN_A_CTRL_RD6DOWNTO0_intermed_3 <= RIN_A_CTRL_RD6DOWNTO0_intermed_2;
RIN_A_CTRL_RD6DOWNTO0_intermed_4 <= RIN_A_CTRL_RD6DOWNTO0_intermed_3;
R_M_CTRL_RD6DOWNTO0_intermed_1 <= R.M.CTRL.RD( 6 DOWNTO 0 );
V_E_CTRL_TT_shadow_intermed_1 <= V_E_CTRL_TT_shadow;
V_E_CTRL_TT_shadow_intermed_2 <= V_E_CTRL_TT_shadow_intermed_1;
RIN_A_CTRL_TT_intermed_1 <= RIN.A.CTRL.TT;
RIN_A_CTRL_TT_intermed_2 <= RIN_A_CTRL_TT_intermed_1;
RIN_A_CTRL_TT_intermed_3 <= RIN_A_CTRL_TT_intermed_2;
R_A_CTRL_TT_intermed_1 <= R.A.CTRL.TT;
R_A_CTRL_TT_intermed_2 <= R_A_CTRL_TT_intermed_1;
R_E_CTRL_TT_intermed_1 <= R.E.CTRL.TT;
RIN_M_CTRL_TT_intermed_1 <= RIN.M.CTRL.TT;
RIN_E_CTRL_TT_intermed_1 <= RIN.E.CTRL.TT;
RIN_E_CTRL_TT_intermed_2 <= RIN_E_CTRL_TT_intermed_1;
V_A_CTRL_TT_shadow_intermed_1 <= V_A_CTRL_TT_shadow;
V_A_CTRL_TT_shadow_intermed_2 <= V_A_CTRL_TT_shadow_intermed_1;
V_A_CTRL_TT_shadow_intermed_3 <= V_A_CTRL_TT_shadow_intermed_2;
R_A_CTRL_LD_intermed_1 <= R.A.CTRL.LD;
RIN_A_CTRL_LD_intermed_1 <= RIN.A.CTRL.LD;
RIN_A_CTRL_LD_intermed_2 <= RIN_A_CTRL_LD_intermed_1;
RIN_E_CTRL_LD_intermed_1 <= RIN.E.CTRL.LD;
V_A_CTRL_LD_shadow_intermed_1 <= V_A_CTRL_LD_shadow;
V_A_CTRL_LD_shadow_intermed_2 <= V_A_CTRL_LD_shadow_intermed_1;
R_M_CTRL_PC31DOWNTO12_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 12 );
R_M_CTRL_PC31DOWNTO12_intermed_2 <= R_M_CTRL_PC31DOWNTO12_intermed_1;
R_M_CTRL_PC31DOWNTO12_intermed_3 <= R_M_CTRL_PC31DOWNTO12_intermed_2;
V_D_PC31DOWNTO12_shadow_intermed_1 <= V_D_PC31DOWNTO12_shadow;
V_D_PC31DOWNTO12_shadow_intermed_2 <= V_D_PC31DOWNTO12_shadow_intermed_1;
V_D_PC31DOWNTO12_shadow_intermed_3 <= V_D_PC31DOWNTO12_shadow_intermed_2;
V_D_PC31DOWNTO12_shadow_intermed_4 <= V_D_PC31DOWNTO12_shadow_intermed_3;
V_D_PC31DOWNTO12_shadow_intermed_5 <= V_D_PC31DOWNTO12_shadow_intermed_4;
V_D_PC31DOWNTO12_shadow_intermed_6 <= V_D_PC31DOWNTO12_shadow_intermed_5;
V_D_PC31DOWNTO12_shadow_intermed_7 <= V_D_PC31DOWNTO12_shadow_intermed_6;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO12_shadow;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_5;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO12_shadow;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_4;
EX_ADD_RES32DOWNTO330DOWNTO11_shadow_intermed_1 <= EX_ADD_RES32DOWNTO330DOWNTO11_shadow;
RIN_F_PC31DOWNTO12_intermed_1 <= RIN.F.PC( 31 DOWNTO 12 );
R_A_CTRL_PC31DOWNTO12_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 12 );
R_A_CTRL_PC31DOWNTO12_intermed_2 <= R_A_CTRL_PC31DOWNTO12_intermed_1;
R_A_CTRL_PC31DOWNTO12_intermed_3 <= R_A_CTRL_PC31DOWNTO12_intermed_2;
R_A_CTRL_PC31DOWNTO12_intermed_4 <= R_A_CTRL_PC31DOWNTO12_intermed_3;
R_A_CTRL_PC31DOWNTO12_intermed_5 <= R_A_CTRL_PC31DOWNTO12_intermed_4;
R_E_CTRL_PC31DOWNTO12_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 12 );
R_E_CTRL_PC31DOWNTO12_intermed_2 <= R_E_CTRL_PC31DOWNTO12_intermed_1;
R_E_CTRL_PC31DOWNTO12_intermed_3 <= R_E_CTRL_PC31DOWNTO12_intermed_2;
R_E_CTRL_PC31DOWNTO12_intermed_4 <= R_E_CTRL_PC31DOWNTO12_intermed_3;
EX_JUMP_ADDRESS31DOWNTO12_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO12_shadow;
RIN_A_CTRL_PC31DOWNTO12_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_2 <= RIN_A_CTRL_PC31DOWNTO12_intermed_1;
RIN_A_CTRL_PC31DOWNTO12_intermed_3 <= RIN_A_CTRL_PC31DOWNTO12_intermed_2;
RIN_A_CTRL_PC31DOWNTO12_intermed_4 <= RIN_A_CTRL_PC31DOWNTO12_intermed_3;
RIN_A_CTRL_PC31DOWNTO12_intermed_5 <= RIN_A_CTRL_PC31DOWNTO12_intermed_4;
RIN_A_CTRL_PC31DOWNTO12_intermed_6 <= RIN_A_CTRL_PC31DOWNTO12_intermed_5;
RIN_E_CTRL_PC31DOWNTO12_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 12 );
RIN_E_CTRL_PC31DOWNTO12_intermed_2 <= RIN_E_CTRL_PC31DOWNTO12_intermed_1;
RIN_E_CTRL_PC31DOWNTO12_intermed_3 <= RIN_E_CTRL_PC31DOWNTO12_intermed_2;
RIN_E_CTRL_PC31DOWNTO12_intermed_4 <= RIN_E_CTRL_PC31DOWNTO12_intermed_3;
RIN_E_CTRL_PC31DOWNTO12_intermed_5 <= RIN_E_CTRL_PC31DOWNTO12_intermed_4;
IRIN_ADDR31DOWNTO12_intermed_1 <= IRIN.ADDR( 31 DOWNTO 12 );
IRIN_ADDR31DOWNTO12_intermed_2 <= IRIN_ADDR31DOWNTO12_intermed_1;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO12_shadow;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_2;
EX_ADD_RES32DOWNTO332DOWNTO13_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO13_shadow;
XC_TRAP_ADDRESS31DOWNTO12_shadow_intermed_1 <= XC_TRAP_ADDRESS31DOWNTO12_shadow;
RIN_M_CTRL_PC31DOWNTO12_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 12 );
RIN_M_CTRL_PC31DOWNTO12_intermed_2 <= RIN_M_CTRL_PC31DOWNTO12_intermed_1;
RIN_M_CTRL_PC31DOWNTO12_intermed_3 <= RIN_M_CTRL_PC31DOWNTO12_intermed_2;
RIN_M_CTRL_PC31DOWNTO12_intermed_4 <= RIN_M_CTRL_PC31DOWNTO12_intermed_3;
IR_ADDR31DOWNTO12_intermed_1 <= IR.ADDR( 31 DOWNTO 12 );
R_X_CTRL_PC31DOWNTO12_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 12 );
R_X_CTRL_PC31DOWNTO12_intermed_2 <= R_X_CTRL_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_1 <= R.D.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_2 <= R_D_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_3 <= R_D_PC31DOWNTO12_intermed_2;
R_D_PC31DOWNTO12_intermed_4 <= R_D_PC31DOWNTO12_intermed_3;
R_D_PC31DOWNTO12_intermed_5 <= R_D_PC31DOWNTO12_intermed_4;
R_D_PC31DOWNTO12_intermed_6 <= R_D_PC31DOWNTO12_intermed_5;
RIN_X_CTRL_PC31DOWNTO12_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 12 );
RIN_X_CTRL_PC31DOWNTO12_intermed_2 <= RIN_X_CTRL_PC31DOWNTO12_intermed_1;
RIN_X_CTRL_PC31DOWNTO12_intermed_3 <= RIN_X_CTRL_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_1 <= RIN.D.PC( 31 DOWNTO 12 );
RIN_D_PC31DOWNTO12_intermed_2 <= RIN_D_PC31DOWNTO12_intermed_1;
RIN_D_PC31DOWNTO12_intermed_3 <= RIN_D_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_4 <= RIN_D_PC31DOWNTO12_intermed_3;
RIN_D_PC31DOWNTO12_intermed_5 <= RIN_D_PC31DOWNTO12_intermed_4;
RIN_D_PC31DOWNTO12_intermed_6 <= RIN_D_PC31DOWNTO12_intermed_5;
RIN_D_PC31DOWNTO12_intermed_7 <= RIN_D_PC31DOWNTO12_intermed_6;
VIR_ADDR31DOWNTO12_shadow_intermed_1 <= VIR_ADDR31DOWNTO12_shadow;
VIR_ADDR31DOWNTO12_shadow_intermed_2 <= VIR_ADDR31DOWNTO12_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO12_shadow;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_X_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_X_CTRL_TT3DOWNTO0_shadow;
R_M_CTRL_TT3DOWNTO0_intermed_1 <= R.M.CTRL.TT( 3 DOWNTO 0 );
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1;
R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
R_A_CTRL_TT3DOWNTO0_intermed_1 <= R.A.CTRL.TT( 3 DOWNTO 0 );
R_A_CTRL_TT3DOWNTO0_intermed_2 <= R_A_CTRL_TT3DOWNTO0_intermed_1;
R_A_CTRL_TT3DOWNTO0_intermed_3 <= R_A_CTRL_TT3DOWNTO0_intermed_2;
RIN_A_CTRL_TT3DOWNTO0_intermed_1 <= RIN.A.CTRL.TT( 3 DOWNTO 0 );
RIN_A_CTRL_TT3DOWNTO0_intermed_2 <= RIN_A_CTRL_TT3DOWNTO0_intermed_1;
RIN_A_CTRL_TT3DOWNTO0_intermed_3 <= RIN_A_CTRL_TT3DOWNTO0_intermed_2;
RIN_A_CTRL_TT3DOWNTO0_intermed_4 <= RIN_A_CTRL_TT3DOWNTO0_intermed_3;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_A_CTRL_TT3DOWNTO0_shadow;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_2;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_4 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_3;
R_E_CTRL_TT3DOWNTO0_intermed_1 <= R.E.CTRL.TT( 3 DOWNTO 0 );
R_E_CTRL_TT3DOWNTO0_intermed_2 <= R_E_CTRL_TT3DOWNTO0_intermed_1;
RIN_M_CTRL_TT3DOWNTO0_intermed_1 <= RIN.M.CTRL.TT( 3 DOWNTO 0 );
RIN_M_CTRL_TT3DOWNTO0_intermed_2 <= RIN_M_CTRL_TT3DOWNTO0_intermed_1;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_M_CTRL_TT3DOWNTO0_shadow;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_M_CTRL_TT3DOWNTO0_shadow_intermed_1;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 );
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_E_CTRL_TT3DOWNTO0_shadow;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_2;
RIN_X_CTRL_TT3DOWNTO0_intermed_1 <= RIN.X.CTRL.TT( 3 DOWNTO 0 );
RIN_E_CTRL_TT3DOWNTO0_intermed_1 <= RIN.E.CTRL.TT( 3 DOWNTO 0 );
RIN_E_CTRL_TT3DOWNTO0_intermed_2 <= RIN_E_CTRL_TT3DOWNTO0_intermed_1;
RIN_E_CTRL_TT3DOWNTO0_intermed_3 <= RIN_E_CTRL_TT3DOWNTO0_intermed_2;
V_X_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_X_CTRL_TT3DOWNTO0_shadow;
V_X_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_X_CTRL_TT3DOWNTO0_shadow_intermed_1;
R_M_CTRL_TT3DOWNTO0_intermed_1 <= R.M.CTRL.TT( 3 DOWNTO 0 );
R_M_CTRL_TT3DOWNTO0_intermed_2 <= R_M_CTRL_TT3DOWNTO0_intermed_1;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_3 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2;
R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
R_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= R_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
R_A_CTRL_TT3DOWNTO0_intermed_1 <= R.A.CTRL.TT( 3 DOWNTO 0 );
R_A_CTRL_TT3DOWNTO0_intermed_2 <= R_A_CTRL_TT3DOWNTO0_intermed_1;
R_A_CTRL_TT3DOWNTO0_intermed_3 <= R_A_CTRL_TT3DOWNTO0_intermed_2;
R_A_CTRL_TT3DOWNTO0_intermed_4 <= R_A_CTRL_TT3DOWNTO0_intermed_3;
RIN_A_CTRL_TT3DOWNTO0_intermed_1 <= RIN.A.CTRL.TT( 3 DOWNTO 0 );
RIN_A_CTRL_TT3DOWNTO0_intermed_2 <= RIN_A_CTRL_TT3DOWNTO0_intermed_1;
RIN_A_CTRL_TT3DOWNTO0_intermed_3 <= RIN_A_CTRL_TT3DOWNTO0_intermed_2;
RIN_A_CTRL_TT3DOWNTO0_intermed_4 <= RIN_A_CTRL_TT3DOWNTO0_intermed_3;
RIN_A_CTRL_TT3DOWNTO0_intermed_5 <= RIN_A_CTRL_TT3DOWNTO0_intermed_4;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_A_CTRL_TT3DOWNTO0_shadow;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_2;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_4 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_3;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_5 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_4;
R_E_CTRL_TT3DOWNTO0_intermed_1 <= R.E.CTRL.TT( 3 DOWNTO 0 );
R_E_CTRL_TT3DOWNTO0_intermed_2 <= R_E_CTRL_TT3DOWNTO0_intermed_1;
R_E_CTRL_TT3DOWNTO0_intermed_3 <= R_E_CTRL_TT3DOWNTO0_intermed_2;
RIN_W_S_TT3DOWNTO0_intermed_1 <= RIN.W.S.TT( 3 DOWNTO 0 );
RIN_M_CTRL_TT3DOWNTO0_intermed_1 <= RIN.M.CTRL.TT( 3 DOWNTO 0 );
RIN_M_CTRL_TT3DOWNTO0_intermed_2 <= RIN_M_CTRL_TT3DOWNTO0_intermed_1;
RIN_M_CTRL_TT3DOWNTO0_intermed_3 <= RIN_M_CTRL_TT3DOWNTO0_intermed_2;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_M_CTRL_TT3DOWNTO0_shadow;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_M_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_M_CTRL_TT3DOWNTO0_shadow_intermed_2;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_3 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 );
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_E_CTRL_TT3DOWNTO0_shadow;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_2;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_4 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_3;
RIN_X_CTRL_TT3DOWNTO0_intermed_1 <= RIN.X.CTRL.TT( 3 DOWNTO 0 );
RIN_X_CTRL_TT3DOWNTO0_intermed_2 <= RIN_X_CTRL_TT3DOWNTO0_intermed_1;
R_X_CTRL_TT3DOWNTO0_intermed_1 <= R.X.CTRL.TT( 3 DOWNTO 0 );
RIN_E_CTRL_TT3DOWNTO0_intermed_1 <= RIN.E.CTRL.TT( 3 DOWNTO 0 );
RIN_E_CTRL_TT3DOWNTO0_intermed_2 <= RIN_E_CTRL_TT3DOWNTO0_intermed_1;
RIN_E_CTRL_TT3DOWNTO0_intermed_3 <= RIN_E_CTRL_TT3DOWNTO0_intermed_2;
RIN_E_CTRL_TT3DOWNTO0_intermed_4 <= RIN_E_CTRL_TT3DOWNTO0_intermed_3;
XC_VECTT3DOWNTO0_shadow_intermed_1 <= XC_VECTT3DOWNTO0_shadow;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
V_X_DATA03_shadow_intermed_1 <= V_X_DATA03_shadow;
V_X_DATA03_shadow_intermed_2 <= V_X_DATA03_shadow_intermed_1;
DCO_DATA03_intermed_1 <= DCO.DATA ( 0 )( 3 );
RIN_X_DATA03_intermed_1 <= RIN.X.DATA ( 0 )( 3 );
R_X_DATA03_intermed_1 <= R.X.DATA( 0 )( 3 );
RIN_X_DATA03_intermed_1 <= RIN.X.DATA( 0 )( 3 );
RIN_X_DATA03_intermed_2 <= RIN_X_DATA03_intermed_1;
R_M_CTRL_PC31DOWNTO12_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 12 );
R_M_CTRL_PC31DOWNTO12_intermed_2 <= R_M_CTRL_PC31DOWNTO12_intermed_1;
V_D_PC31DOWNTO12_shadow_intermed_1 <= V_D_PC31DOWNTO12_shadow;
V_D_PC31DOWNTO12_shadow_intermed_2 <= V_D_PC31DOWNTO12_shadow_intermed_1;
V_D_PC31DOWNTO12_shadow_intermed_3 <= V_D_PC31DOWNTO12_shadow_intermed_2;
V_D_PC31DOWNTO12_shadow_intermed_4 <= V_D_PC31DOWNTO12_shadow_intermed_3;
V_D_PC31DOWNTO12_shadow_intermed_5 <= V_D_PC31DOWNTO12_shadow_intermed_4;
V_D_PC31DOWNTO12_shadow_intermed_6 <= V_D_PC31DOWNTO12_shadow_intermed_5;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO12_shadow;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_4;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO12_shadow;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_3;
R_A_CTRL_PC31DOWNTO12_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 12 );
R_A_CTRL_PC31DOWNTO12_intermed_2 <= R_A_CTRL_PC31DOWNTO12_intermed_1;
R_A_CTRL_PC31DOWNTO12_intermed_3 <= R_A_CTRL_PC31DOWNTO12_intermed_2;
R_A_CTRL_PC31DOWNTO12_intermed_4 <= R_A_CTRL_PC31DOWNTO12_intermed_3;
R_E_CTRL_PC31DOWNTO12_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 12 );
R_E_CTRL_PC31DOWNTO12_intermed_2 <= R_E_CTRL_PC31DOWNTO12_intermed_1;
R_E_CTRL_PC31DOWNTO12_intermed_3 <= R_E_CTRL_PC31DOWNTO12_intermed_2;
RIN_A_CTRL_PC31DOWNTO12_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_2 <= RIN_A_CTRL_PC31DOWNTO12_intermed_1;
RIN_A_CTRL_PC31DOWNTO12_intermed_3 <= RIN_A_CTRL_PC31DOWNTO12_intermed_2;
RIN_A_CTRL_PC31DOWNTO12_intermed_4 <= RIN_A_CTRL_PC31DOWNTO12_intermed_3;
RIN_A_CTRL_PC31DOWNTO12_intermed_5 <= RIN_A_CTRL_PC31DOWNTO12_intermed_4;
RIN_E_CTRL_PC31DOWNTO12_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 12 );
RIN_E_CTRL_PC31DOWNTO12_intermed_2 <= RIN_E_CTRL_PC31DOWNTO12_intermed_1;
RIN_E_CTRL_PC31DOWNTO12_intermed_3 <= RIN_E_CTRL_PC31DOWNTO12_intermed_2;
RIN_E_CTRL_PC31DOWNTO12_intermed_4 <= RIN_E_CTRL_PC31DOWNTO12_intermed_3;
IRIN_ADDR31DOWNTO12_intermed_1 <= IRIN.ADDR( 31 DOWNTO 12 );
V_X_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO12_shadow;
V_X_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO12_shadow_intermed_1;
RIN_M_CTRL_PC31DOWNTO12_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 12 );
RIN_M_CTRL_PC31DOWNTO12_intermed_2 <= RIN_M_CTRL_PC31DOWNTO12_intermed_1;
RIN_M_CTRL_PC31DOWNTO12_intermed_3 <= RIN_M_CTRL_PC31DOWNTO12_intermed_2;
R_X_CTRL_PC31DOWNTO12_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_1 <= R.D.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_2 <= R_D_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_3 <= R_D_PC31DOWNTO12_intermed_2;
R_D_PC31DOWNTO12_intermed_4 <= R_D_PC31DOWNTO12_intermed_3;
R_D_PC31DOWNTO12_intermed_5 <= R_D_PC31DOWNTO12_intermed_4;
RIN_X_CTRL_PC31DOWNTO12_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 12 );
RIN_X_CTRL_PC31DOWNTO12_intermed_2 <= RIN_X_CTRL_PC31DOWNTO12_intermed_1;
RIN_D_PC31DOWNTO12_intermed_1 <= RIN.D.PC( 31 DOWNTO 12 );
RIN_D_PC31DOWNTO12_intermed_2 <= RIN_D_PC31DOWNTO12_intermed_1;
RIN_D_PC31DOWNTO12_intermed_3 <= RIN_D_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_4 <= RIN_D_PC31DOWNTO12_intermed_3;
RIN_D_PC31DOWNTO12_intermed_5 <= RIN_D_PC31DOWNTO12_intermed_4;
RIN_D_PC31DOWNTO12_intermed_6 <= RIN_D_PC31DOWNTO12_intermed_5;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO12_shadow;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_2;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
RIN_M_CTRL_PC31DOWNTO2_intermed_2 <= RIN_M_CTRL_PC31DOWNTO2_intermed_1;
RIN_M_CTRL_PC31DOWNTO2_intermed_3 <= RIN_M_CTRL_PC31DOWNTO2_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
V_D_PC31DOWNTO2_shadow_intermed_5 <= V_D_PC31DOWNTO2_shadow_intermed_4;
V_D_PC31DOWNTO2_shadow_intermed_6 <= V_D_PC31DOWNTO2_shadow_intermed_5;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
RIN_D_PC31DOWNTO2_intermed_5 <= RIN_D_PC31DOWNTO2_intermed_4;
RIN_D_PC31DOWNTO2_intermed_6 <= RIN_D_PC31DOWNTO2_intermed_5;
RIN_X_CTRL_PC31DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 2 );
RIN_X_CTRL_PC31DOWNTO2_intermed_2 <= RIN_X_CTRL_PC31DOWNTO2_intermed_1;
IRIN_ADDR31DOWNTO2_intermed_1 <= IRIN.ADDR( 31 DOWNTO 2 );
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_4;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
R_D_PC31DOWNTO2_intermed_4 <= R_D_PC31DOWNTO2_intermed_3;
R_D_PC31DOWNTO2_intermed_5 <= R_D_PC31DOWNTO2_intermed_4;
R_M_CTRL_PC31DOWNTO2_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 2 );
R_M_CTRL_PC31DOWNTO2_intermed_2 <= R_M_CTRL_PC31DOWNTO2_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
RIN_A_CTRL_PC31DOWNTO2_intermed_4 <= RIN_A_CTRL_PC31DOWNTO2_intermed_3;
RIN_A_CTRL_PC31DOWNTO2_intermed_5 <= RIN_A_CTRL_PC31DOWNTO2_intermed_4;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_3 <= R_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_4 <= R_A_CTRL_PC31DOWNTO2_intermed_3;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO2_shadow;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO2_shadow_intermed_2;
R_X_CTRL_PC31DOWNTO2_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
R_E_CTRL_PC31DOWNTO2_intermed_2 <= R_E_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_3 <= R_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_E_CTRL_PC31DOWNTO2_intermed_3 <= RIN_E_CTRL_PC31DOWNTO2_intermed_2;
RIN_E_CTRL_PC31DOWNTO2_intermed_4 <= RIN_E_CTRL_PC31DOWNTO2_intermed_3;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO2_shadow;
V_X_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_F_PC31DOWNTO4_shadow_intermed_1 <= V_F_PC31DOWNTO4_shadow;
V_X_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_X_CTRL_PC31DOWNTO4_shadow;
V_X_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_X_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_X_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_X_CTRL_PC31DOWNTO4_shadow_intermed_2;
IR_ADDR31DOWNTO4_intermed_1 <= IR.ADDR( 31 DOWNTO 4 );
VIR_ADDR31DOWNTO4_shadow_intermed_1 <= VIR_ADDR31DOWNTO4_shadow;
VIR_ADDR31DOWNTO4_shadow_intermed_2 <= VIR_ADDR31DOWNTO4_shadow_intermed_1;
RIN_F_PC31DOWNTO4_intermed_1 <= RIN.F.PC( 31 DOWNTO 4 );
RIN_A_CTRL_PC31DOWNTO4_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 4 );
RIN_A_CTRL_PC31DOWNTO4_intermed_2 <= RIN_A_CTRL_PC31DOWNTO4_intermed_1;
RIN_A_CTRL_PC31DOWNTO4_intermed_3 <= RIN_A_CTRL_PC31DOWNTO4_intermed_2;
RIN_A_CTRL_PC31DOWNTO4_intermed_4 <= RIN_A_CTRL_PC31DOWNTO4_intermed_3;
RIN_A_CTRL_PC31DOWNTO4_intermed_5 <= RIN_A_CTRL_PC31DOWNTO4_intermed_4;
RIN_A_CTRL_PC31DOWNTO4_intermed_6 <= RIN_A_CTRL_PC31DOWNTO4_intermed_5;
R_A_CTRL_PC31DOWNTO4_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 4 );
R_A_CTRL_PC31DOWNTO4_intermed_2 <= R_A_CTRL_PC31DOWNTO4_intermed_1;
R_A_CTRL_PC31DOWNTO4_intermed_3 <= R_A_CTRL_PC31DOWNTO4_intermed_2;
R_A_CTRL_PC31DOWNTO4_intermed_4 <= R_A_CTRL_PC31DOWNTO4_intermed_3;
R_A_CTRL_PC31DOWNTO4_intermed_5 <= R_A_CTRL_PC31DOWNTO4_intermed_4;
R_D_PC31DOWNTO4_intermed_1 <= R.D.PC( 31 DOWNTO 4 );
R_D_PC31DOWNTO4_intermed_2 <= R_D_PC31DOWNTO4_intermed_1;
R_D_PC31DOWNTO4_intermed_3 <= R_D_PC31DOWNTO4_intermed_2;
R_D_PC31DOWNTO4_intermed_4 <= R_D_PC31DOWNTO4_intermed_3;
R_D_PC31DOWNTO4_intermed_5 <= R_D_PC31DOWNTO4_intermed_4;
R_D_PC31DOWNTO4_intermed_6 <= R_D_PC31DOWNTO4_intermed_5;
RIN_X_CTRL_PC31DOWNTO4_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 4 );
RIN_X_CTRL_PC31DOWNTO4_intermed_2 <= RIN_X_CTRL_PC31DOWNTO4_intermed_1;
RIN_X_CTRL_PC31DOWNTO4_intermed_3 <= RIN_X_CTRL_PC31DOWNTO4_intermed_2;
EX_ADD_RES32DOWNTO332DOWNTO5_shadow_intermed_1 <= EX_ADD_RES32DOWNTO332DOWNTO5_shadow;
V_D_PC31DOWNTO4_shadow_intermed_1 <= V_D_PC31DOWNTO4_shadow;
V_D_PC31DOWNTO4_shadow_intermed_2 <= V_D_PC31DOWNTO4_shadow_intermed_1;
V_D_PC31DOWNTO4_shadow_intermed_3 <= V_D_PC31DOWNTO4_shadow_intermed_2;
V_D_PC31DOWNTO4_shadow_intermed_4 <= V_D_PC31DOWNTO4_shadow_intermed_3;
V_D_PC31DOWNTO4_shadow_intermed_5 <= V_D_PC31DOWNTO4_shadow_intermed_4;
V_D_PC31DOWNTO4_shadow_intermed_6 <= V_D_PC31DOWNTO4_shadow_intermed_5;
V_D_PC31DOWNTO4_shadow_intermed_7 <= V_D_PC31DOWNTO4_shadow_intermed_6;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO4_shadow;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_5 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_4;
RIN_M_CTRL_PC31DOWNTO4_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 4 );
RIN_M_CTRL_PC31DOWNTO4_intermed_2 <= RIN_M_CTRL_PC31DOWNTO4_intermed_1;
RIN_M_CTRL_PC31DOWNTO4_intermed_3 <= RIN_M_CTRL_PC31DOWNTO4_intermed_2;
RIN_M_CTRL_PC31DOWNTO4_intermed_4 <= RIN_M_CTRL_PC31DOWNTO4_intermed_3;
R_X_CTRL_PC31DOWNTO4_intermed_1 <= R.X.CTRL.PC( 31 DOWNTO 4 );
R_X_CTRL_PC31DOWNTO4_intermed_2 <= R_X_CTRL_PC31DOWNTO4_intermed_1;
IRIN_ADDR31DOWNTO4_intermed_1 <= IRIN.ADDR( 31 DOWNTO 4 );
IRIN_ADDR31DOWNTO4_intermed_2 <= IRIN_ADDR31DOWNTO4_intermed_1;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO4_shadow;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_2;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_3;
R_M_CTRL_PC31DOWNTO4_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 4 );
R_M_CTRL_PC31DOWNTO4_intermed_2 <= R_M_CTRL_PC31DOWNTO4_intermed_1;
R_M_CTRL_PC31DOWNTO4_intermed_3 <= R_M_CTRL_PC31DOWNTO4_intermed_2;
RIN_D_PC31DOWNTO4_intermed_1 <= RIN.D.PC( 31 DOWNTO 4 );
RIN_D_PC31DOWNTO4_intermed_2 <= RIN_D_PC31DOWNTO4_intermed_1;
RIN_D_PC31DOWNTO4_intermed_3 <= RIN_D_PC31DOWNTO4_intermed_2;
RIN_D_PC31DOWNTO4_intermed_4 <= RIN_D_PC31DOWNTO4_intermed_3;
RIN_D_PC31DOWNTO4_intermed_5 <= RIN_D_PC31DOWNTO4_intermed_4;
RIN_D_PC31DOWNTO4_intermed_6 <= RIN_D_PC31DOWNTO4_intermed_5;
RIN_D_PC31DOWNTO4_intermed_7 <= RIN_D_PC31DOWNTO4_intermed_6;
RIN_E_CTRL_PC31DOWNTO4_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 4 );
RIN_E_CTRL_PC31DOWNTO4_intermed_2 <= RIN_E_CTRL_PC31DOWNTO4_intermed_1;
RIN_E_CTRL_PC31DOWNTO4_intermed_3 <= RIN_E_CTRL_PC31DOWNTO4_intermed_2;
RIN_E_CTRL_PC31DOWNTO4_intermed_4 <= RIN_E_CTRL_PC31DOWNTO4_intermed_3;
RIN_E_CTRL_PC31DOWNTO4_intermed_5 <= RIN_E_CTRL_PC31DOWNTO4_intermed_4;
EX_JUMP_ADDRESS31DOWNTO4_shadow_intermed_1 <= EX_JUMP_ADDRESS31DOWNTO4_shadow;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO4_shadow;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_5 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_6 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_5;
R_E_CTRL_PC31DOWNTO4_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 4 );
R_E_CTRL_PC31DOWNTO4_intermed_2 <= R_E_CTRL_PC31DOWNTO4_intermed_1;
R_E_CTRL_PC31DOWNTO4_intermed_3 <= R_E_CTRL_PC31DOWNTO4_intermed_2;
R_E_CTRL_PC31DOWNTO4_intermed_4 <= R_E_CTRL_PC31DOWNTO4_intermed_3;
R_D_PC3DOWNTO2_intermed_1 <= R.D.PC( 3 DOWNTO 2 );
R_D_PC3DOWNTO2_intermed_2 <= R_D_PC3DOWNTO2_intermed_1;
R_D_PC3DOWNTO2_intermed_3 <= R_D_PC3DOWNTO2_intermed_2;
R_D_PC3DOWNTO2_intermed_4 <= R_D_PC3DOWNTO2_intermed_3;
R_D_PC3DOWNTO2_intermed_5 <= R_D_PC3DOWNTO2_intermed_4;
R_D_PC3DOWNTO2_intermed_6 <= R_D_PC3DOWNTO2_intermed_5;
V_D_PC3DOWNTO2_shadow_intermed_1 <= V_D_PC3DOWNTO2_shadow;
V_D_PC3DOWNTO2_shadow_intermed_2 <= V_D_PC3DOWNTO2_shadow_intermed_1;
V_D_PC3DOWNTO2_shadow_intermed_3 <= V_D_PC3DOWNTO2_shadow_intermed_2;
V_D_PC3DOWNTO2_shadow_intermed_4 <= V_D_PC3DOWNTO2_shadow_intermed_3;
V_D_PC3DOWNTO2_shadow_intermed_5 <= V_D_PC3DOWNTO2_shadow_intermed_4;
V_D_PC3DOWNTO2_shadow_intermed_6 <= V_D_PC3DOWNTO2_shadow_intermed_5;
V_D_PC3DOWNTO2_shadow_intermed_7 <= V_D_PC3DOWNTO2_shadow_intermed_6;
VIR_ADDR3DOWNTO2_shadow_intermed_1 <= VIR_ADDR3DOWNTO2_shadow;
VIR_ADDR3DOWNTO2_shadow_intermed_2 <= VIR_ADDR3DOWNTO2_shadow_intermed_1;
RIN_D_PC3DOWNTO2_intermed_1 <= RIN.D.PC( 3 DOWNTO 2 );
RIN_D_PC3DOWNTO2_intermed_2 <= RIN_D_PC3DOWNTO2_intermed_1;
RIN_D_PC3DOWNTO2_intermed_3 <= RIN_D_PC3DOWNTO2_intermed_2;
RIN_D_PC3DOWNTO2_intermed_4 <= RIN_D_PC3DOWNTO2_intermed_3;
RIN_D_PC3DOWNTO2_intermed_5 <= RIN_D_PC3DOWNTO2_intermed_4;
RIN_D_PC3DOWNTO2_intermed_6 <= RIN_D_PC3DOWNTO2_intermed_5;
RIN_D_PC3DOWNTO2_intermed_7 <= RIN_D_PC3DOWNTO2_intermed_6;
R_M_CTRL_PC3DOWNTO2_intermed_1 <= R.M.CTRL.PC( 3 DOWNTO 2 );
R_M_CTRL_PC3DOWNTO2_intermed_2 <= R_M_CTRL_PC3DOWNTO2_intermed_1;
R_M_CTRL_PC3DOWNTO2_intermed_3 <= R_M_CTRL_PC3DOWNTO2_intermed_2;
R_E_CTRL_PC3DOWNTO2_intermed_1 <= R.E.CTRL.PC( 3 DOWNTO 2 );
R_E_CTRL_PC3DOWNTO2_intermed_2 <= R_E_CTRL_PC3DOWNTO2_intermed_1;
R_E_CTRL_PC3DOWNTO2_intermed_3 <= R_E_CTRL_PC3DOWNTO2_intermed_2;
R_E_CTRL_PC3DOWNTO2_intermed_4 <= R_E_CTRL_PC3DOWNTO2_intermed_3;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC3DOWNTO2_shadow;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_2;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_3;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_5 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_4;
RIN_X_CTRL_PC3DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 3 DOWNTO 2 );
RIN_X_CTRL_PC3DOWNTO2_intermed_2 <= RIN_X_CTRL_PC3DOWNTO2_intermed_1;
RIN_X_CTRL_PC3DOWNTO2_intermed_3 <= RIN_X_CTRL_PC3DOWNTO2_intermed_2;
R_A_CTRL_PC3DOWNTO2_intermed_1 <= R.A.CTRL.PC( 3 DOWNTO 2 );
R_A_CTRL_PC3DOWNTO2_intermed_2 <= R_A_CTRL_PC3DOWNTO2_intermed_1;
R_A_CTRL_PC3DOWNTO2_intermed_3 <= R_A_CTRL_PC3DOWNTO2_intermed_2;
R_A_CTRL_PC3DOWNTO2_intermed_4 <= R_A_CTRL_PC3DOWNTO2_intermed_3;
R_A_CTRL_PC3DOWNTO2_intermed_5 <= R_A_CTRL_PC3DOWNTO2_intermed_4;
V_X_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_X_CTRL_PC3DOWNTO2_shadow;
V_X_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_X_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_X_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_X_CTRL_PC3DOWNTO2_shadow_intermed_2;
RIN_M_CTRL_PC3DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 3 DOWNTO 2 );
RIN_M_CTRL_PC3DOWNTO2_intermed_2 <= RIN_M_CTRL_PC3DOWNTO2_intermed_1;
RIN_M_CTRL_PC3DOWNTO2_intermed_3 <= RIN_M_CTRL_PC3DOWNTO2_intermed_2;
RIN_M_CTRL_PC3DOWNTO2_intermed_4 <= RIN_M_CTRL_PC3DOWNTO2_intermed_3;
IRIN_ADDR3DOWNTO2_intermed_1 <= IRIN.ADDR( 3 DOWNTO 2 );
IRIN_ADDR3DOWNTO2_intermed_2 <= IRIN_ADDR3DOWNTO2_intermed_1;
EX_JUMP_ADDRESS3DOWNTO2_shadow_intermed_1 <= EX_JUMP_ADDRESS3DOWNTO2_shadow;
EX_ADD_RES32DOWNTO34DOWNTO3_shadow_intermed_1 <= EX_ADD_RES32DOWNTO34DOWNTO3_shadow;
RIN_A_CTRL_PC3DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 3 DOWNTO 2 );
RIN_A_CTRL_PC3DOWNTO2_intermed_2 <= RIN_A_CTRL_PC3DOWNTO2_intermed_1;
RIN_A_CTRL_PC3DOWNTO2_intermed_3 <= RIN_A_CTRL_PC3DOWNTO2_intermed_2;
RIN_A_CTRL_PC3DOWNTO2_intermed_4 <= RIN_A_CTRL_PC3DOWNTO2_intermed_3;
RIN_A_CTRL_PC3DOWNTO2_intermed_5 <= RIN_A_CTRL_PC3DOWNTO2_intermed_4;
RIN_A_CTRL_PC3DOWNTO2_intermed_6 <= RIN_A_CTRL_PC3DOWNTO2_intermed_5;
V_F_PC3DOWNTO2_shadow_intermed_1 <= V_F_PC3DOWNTO2_shadow;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC3DOWNTO2_shadow;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_3;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_5 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_4;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_6 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_5;
IR_ADDR3DOWNTO2_intermed_1 <= IR.ADDR( 3 DOWNTO 2 );
V_M_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC3DOWNTO2_shadow;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_2;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_3;
R_X_CTRL_PC3DOWNTO2_intermed_1 <= R.X.CTRL.PC( 3 DOWNTO 2 );
R_X_CTRL_PC3DOWNTO2_intermed_2 <= R_X_CTRL_PC3DOWNTO2_intermed_1;
RIN_E_CTRL_PC3DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 3 DOWNTO 2 );
RIN_E_CTRL_PC3DOWNTO2_intermed_2 <= RIN_E_CTRL_PC3DOWNTO2_intermed_1;
RIN_E_CTRL_PC3DOWNTO2_intermed_3 <= RIN_E_CTRL_PC3DOWNTO2_intermed_2;
RIN_E_CTRL_PC3DOWNTO2_intermed_4 <= RIN_E_CTRL_PC3DOWNTO2_intermed_3;
RIN_E_CTRL_PC3DOWNTO2_intermed_5 <= RIN_E_CTRL_PC3DOWNTO2_intermed_4;
RIN_F_PC3DOWNTO2_intermed_1 <= RIN.F.PC( 3 DOWNTO 2 );
V_E_CTRL_RD7DOWNTO0_shadow_intermed_1 <= V_E_CTRL_RD7DOWNTO0_shadow;
V_E_CTRL_RD7DOWNTO0_shadow_intermed_2 <= V_E_CTRL_RD7DOWNTO0_shadow_intermed_1;
R_E_CTRL_RD7DOWNTO0_intermed_1 <= R.E.CTRL.RD ( 7 DOWNTO 0 );
V_A_CTRL_RD7DOWNTO0_shadow_intermed_1 <= V_A_CTRL_RD7DOWNTO0_shadow;
V_A_CTRL_RD7DOWNTO0_shadow_intermed_2 <= V_A_CTRL_RD7DOWNTO0_shadow_intermed_1;
V_A_CTRL_RD7DOWNTO0_shadow_intermed_3 <= V_A_CTRL_RD7DOWNTO0_shadow_intermed_2;
RIN_A_CTRL_RD7DOWNTO0_intermed_1 <= RIN.A.CTRL.RD ( 7 DOWNTO 0 );
RIN_A_CTRL_RD7DOWNTO0_intermed_2 <= RIN_A_CTRL_RD7DOWNTO0_intermed_1;
RIN_A_CTRL_RD7DOWNTO0_intermed_3 <= RIN_A_CTRL_RD7DOWNTO0_intermed_2;
R_A_CTRL_RD7DOWNTO0_intermed_1 <= R.A.CTRL.RD ( 7 DOWNTO 0 );
R_A_CTRL_RD7DOWNTO0_intermed_2 <= R_A_CTRL_RD7DOWNTO0_intermed_1;
RIN_E_CTRL_RD7DOWNTO0_intermed_1 <= RIN.E.CTRL.RD ( 7 DOWNTO 0 );
RIN_E_CTRL_RD7DOWNTO0_intermed_2 <= RIN_E_CTRL_RD7DOWNTO0_intermed_1;
RIN_M_CTRL_RD7DOWNTO0_intermed_1 <= RIN.M.CTRL.RD ( 7 DOWNTO 0 );
RIN_D_PC_intermed_1 <= RIN.D.PC;
RIN_D_PC_intermed_2 <= RIN_D_PC_intermed_1;
RIN_D_PC_intermed_3 <= RIN_D_PC_intermed_2;
RIN_D_PC_intermed_4 <= RIN_D_PC_intermed_3;
RIN_A_CTRL_PC_intermed_1 <= RIN.A.CTRL.PC;
RIN_A_CTRL_PC_intermed_2 <= RIN_A_CTRL_PC_intermed_1;
RIN_A_CTRL_PC_intermed_3 <= RIN_A_CTRL_PC_intermed_2;
R_A_CTRL_PC_intermed_1 <= R.A.CTRL.PC;
R_A_CTRL_PC_intermed_2 <= R_A_CTRL_PC_intermed_1;
V_E_CTRL_PC_shadow_intermed_1 <= V_E_CTRL_PC_shadow;
V_E_CTRL_PC_shadow_intermed_2 <= V_E_CTRL_PC_shadow_intermed_1;
R_E_CTRL_PC_intermed_1 <= R.E.CTRL.PC;
RIN_M_CTRL_PC_intermed_1 <= RIN.M.CTRL.PC;
V_A_CTRL_PC_shadow_intermed_1 <= V_A_CTRL_PC_shadow;
V_A_CTRL_PC_shadow_intermed_2 <= V_A_CTRL_PC_shadow_intermed_1;
V_A_CTRL_PC_shadow_intermed_3 <= V_A_CTRL_PC_shadow_intermed_2;
R_D_PC_intermed_1 <= R.D.PC;
R_D_PC_intermed_2 <= R_D_PC_intermed_1;
R_D_PC_intermed_3 <= R_D_PC_intermed_2;
RIN_E_CTRL_PC_intermed_1 <= RIN.E.CTRL.PC;
RIN_E_CTRL_PC_intermed_2 <= RIN_E_CTRL_PC_intermed_1;
V_D_PC_shadow_intermed_1 <= V_D_PC_shadow;
V_D_PC_shadow_intermed_2 <= V_D_PC_shadow_intermed_1;
V_D_PC_shadow_intermed_3 <= V_D_PC_shadow_intermed_2;
V_D_PC_shadow_intermed_4 <= V_D_PC_shadow_intermed_3;
RIN_M_CTRL_PC31DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 2 );
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_4 <= V_D_PC31DOWNTO2_shadow_intermed_3;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
RIN_D_PC31DOWNTO2_intermed_4 <= RIN_D_PC31DOWNTO2_intermed_3;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_2;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
R_D_PC31DOWNTO2_intermed_3 <= R_D_PC31DOWNTO2_intermed_2;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO2_shadow;
V_E_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO2_shadow_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_3 <= RIN_A_CTRL_PC31DOWNTO2_intermed_2;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
R_A_CTRL_PC31DOWNTO2_intermed_2 <= R_A_CTRL_PC31DOWNTO2_intermed_1;
R_E_CTRL_PC31DOWNTO2_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_2 <= RIN_E_CTRL_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST ( 20 );
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST( 20 );
RIN_A_CTRL_INST20_intermed_2 <= RIN_A_CTRL_INST20_intermed_1;
V_A_CTRL_INST20_shadow_intermed_1 <= V_A_CTRL_INST20_shadow;
V_A_CTRL_INST20_shadow_intermed_2 <= V_A_CTRL_INST20_shadow_intermed_1;
DE_INST20_shadow_intermed_1 <= DE_INST20_shadow;
R_A_CTRL_INST20_intermed_1 <= R.A.CTRL.INST( 20 );
RIN_A_CTRL_INST20_intermed_1 <= RIN.A.CTRL.INST( 20 );
DE_INST20_shadow_intermed_1 <= DE_INST20_shadow;
R_A_CTRL_INST24_intermed_1 <= R.A.CTRL.INST( 24 );
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST( 24 );
RIN_A_CTRL_INST24_intermed_2 <= RIN_A_CTRL_INST24_intermed_1;
V_A_CTRL_INST24_shadow_intermed_1 <= V_A_CTRL_INST24_shadow;
V_A_CTRL_INST24_shadow_intermed_2 <= V_A_CTRL_INST24_shadow_intermed_1;
DE_INST24_shadow_intermed_1 <= DE_INST24_shadow;
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST ( 24 );
RIN_A_CTRL_INST24_intermed_1 <= RIN.A.CTRL.INST( 24 );
DE_INST24_shadow_intermed_1 <= DE_INST24_shadow;
RIN_A_CTRL_PC31DOWNTO4_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 4 );
RIN_A_CTRL_PC31DOWNTO4_intermed_2 <= RIN_A_CTRL_PC31DOWNTO4_intermed_1;
RIN_A_CTRL_PC31DOWNTO4_intermed_3 <= RIN_A_CTRL_PC31DOWNTO4_intermed_2;
RIN_A_CTRL_PC31DOWNTO4_intermed_4 <= RIN_A_CTRL_PC31DOWNTO4_intermed_3;
R_A_CTRL_PC31DOWNTO4_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 4 );
R_A_CTRL_PC31DOWNTO4_intermed_2 <= R_A_CTRL_PC31DOWNTO4_intermed_1;
R_A_CTRL_PC31DOWNTO4_intermed_3 <= R_A_CTRL_PC31DOWNTO4_intermed_2;
R_D_PC31DOWNTO4_intermed_1 <= R.D.PC( 31 DOWNTO 4 );
R_D_PC31DOWNTO4_intermed_2 <= R_D_PC31DOWNTO4_intermed_1;
R_D_PC31DOWNTO4_intermed_3 <= R_D_PC31DOWNTO4_intermed_2;
R_D_PC31DOWNTO4_intermed_4 <= R_D_PC31DOWNTO4_intermed_3;
RIN_X_CTRL_PC31DOWNTO4_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 4 );
V_D_PC31DOWNTO4_shadow_intermed_1 <= V_D_PC31DOWNTO4_shadow;
V_D_PC31DOWNTO4_shadow_intermed_2 <= V_D_PC31DOWNTO4_shadow_intermed_1;
V_D_PC31DOWNTO4_shadow_intermed_3 <= V_D_PC31DOWNTO4_shadow_intermed_2;
V_D_PC31DOWNTO4_shadow_intermed_4 <= V_D_PC31DOWNTO4_shadow_intermed_3;
V_D_PC31DOWNTO4_shadow_intermed_5 <= V_D_PC31DOWNTO4_shadow_intermed_4;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO4_shadow;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_2;
RIN_M_CTRL_PC31DOWNTO4_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 4 );
RIN_M_CTRL_PC31DOWNTO4_intermed_2 <= RIN_M_CTRL_PC31DOWNTO4_intermed_1;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO4_shadow;
V_M_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO4_shadow_intermed_1;
R_M_CTRL_PC31DOWNTO4_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 4 );
RIN_D_PC31DOWNTO4_intermed_1 <= RIN.D.PC( 31 DOWNTO 4 );
RIN_D_PC31DOWNTO4_intermed_2 <= RIN_D_PC31DOWNTO4_intermed_1;
RIN_D_PC31DOWNTO4_intermed_3 <= RIN_D_PC31DOWNTO4_intermed_2;
RIN_D_PC31DOWNTO4_intermed_4 <= RIN_D_PC31DOWNTO4_intermed_3;
RIN_D_PC31DOWNTO4_intermed_5 <= RIN_D_PC31DOWNTO4_intermed_4;
RIN_E_CTRL_PC31DOWNTO4_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 4 );
RIN_E_CTRL_PC31DOWNTO4_intermed_2 <= RIN_E_CTRL_PC31DOWNTO4_intermed_1;
RIN_E_CTRL_PC31DOWNTO4_intermed_3 <= RIN_E_CTRL_PC31DOWNTO4_intermed_2;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO4_shadow;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_3;
R_E_CTRL_PC31DOWNTO4_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 4 );
R_E_CTRL_PC31DOWNTO4_intermed_2 <= R_E_CTRL_PC31DOWNTO4_intermed_1;
R_D_PC3DOWNTO2_intermed_1 <= R.D.PC( 3 DOWNTO 2 );
R_D_PC3DOWNTO2_intermed_2 <= R_D_PC3DOWNTO2_intermed_1;
R_D_PC3DOWNTO2_intermed_3 <= R_D_PC3DOWNTO2_intermed_2;
R_D_PC3DOWNTO2_intermed_4 <= R_D_PC3DOWNTO2_intermed_3;
V_D_PC3DOWNTO2_shadow_intermed_1 <= V_D_PC3DOWNTO2_shadow;
V_D_PC3DOWNTO2_shadow_intermed_2 <= V_D_PC3DOWNTO2_shadow_intermed_1;
V_D_PC3DOWNTO2_shadow_intermed_3 <= V_D_PC3DOWNTO2_shadow_intermed_2;
V_D_PC3DOWNTO2_shadow_intermed_4 <= V_D_PC3DOWNTO2_shadow_intermed_3;
V_D_PC3DOWNTO2_shadow_intermed_5 <= V_D_PC3DOWNTO2_shadow_intermed_4;
RIN_D_PC3DOWNTO2_intermed_1 <= RIN.D.PC( 3 DOWNTO 2 );
RIN_D_PC3DOWNTO2_intermed_2 <= RIN_D_PC3DOWNTO2_intermed_1;
RIN_D_PC3DOWNTO2_intermed_3 <= RIN_D_PC3DOWNTO2_intermed_2;
RIN_D_PC3DOWNTO2_intermed_4 <= RIN_D_PC3DOWNTO2_intermed_3;
RIN_D_PC3DOWNTO2_intermed_5 <= RIN_D_PC3DOWNTO2_intermed_4;
R_M_CTRL_PC3DOWNTO2_intermed_1 <= R.M.CTRL.PC( 3 DOWNTO 2 );
R_E_CTRL_PC3DOWNTO2_intermed_1 <= R.E.CTRL.PC( 3 DOWNTO 2 );
R_E_CTRL_PC3DOWNTO2_intermed_2 <= R_E_CTRL_PC3DOWNTO2_intermed_1;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC3DOWNTO2_shadow;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_2;
RIN_X_CTRL_PC3DOWNTO2_intermed_1 <= RIN.X.CTRL.PC( 3 DOWNTO 2 );
R_A_CTRL_PC3DOWNTO2_intermed_1 <= R.A.CTRL.PC( 3 DOWNTO 2 );
R_A_CTRL_PC3DOWNTO2_intermed_2 <= R_A_CTRL_PC3DOWNTO2_intermed_1;
R_A_CTRL_PC3DOWNTO2_intermed_3 <= R_A_CTRL_PC3DOWNTO2_intermed_2;
RIN_M_CTRL_PC3DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 3 DOWNTO 2 );
RIN_M_CTRL_PC3DOWNTO2_intermed_2 <= RIN_M_CTRL_PC3DOWNTO2_intermed_1;
RIN_A_CTRL_PC3DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 3 DOWNTO 2 );
RIN_A_CTRL_PC3DOWNTO2_intermed_2 <= RIN_A_CTRL_PC3DOWNTO2_intermed_1;
RIN_A_CTRL_PC3DOWNTO2_intermed_3 <= RIN_A_CTRL_PC3DOWNTO2_intermed_2;
RIN_A_CTRL_PC3DOWNTO2_intermed_4 <= RIN_A_CTRL_PC3DOWNTO2_intermed_3;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC3DOWNTO2_shadow;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_2;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_4 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_3;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_M_CTRL_PC3DOWNTO2_shadow;
V_M_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_M_CTRL_PC3DOWNTO2_shadow_intermed_1;
RIN_E_CTRL_PC3DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 3 DOWNTO 2 );
RIN_E_CTRL_PC3DOWNTO2_intermed_2 <= RIN_E_CTRL_PC3DOWNTO2_intermed_1;
RIN_E_CTRL_PC3DOWNTO2_intermed_3 <= RIN_E_CTRL_PC3DOWNTO2_intermed_2;
RIN_E_CTRL_RD6DOWNTO0_intermed_1 <= RIN.E.CTRL.RD( 6 DOWNTO 0 );
RIN_E_CTRL_RD6DOWNTO0_intermed_2 <= RIN_E_CTRL_RD6DOWNTO0_intermed_1;
RIN_M_CTRL_RD6DOWNTO0_intermed_1 <= RIN.M.CTRL.RD( 6 DOWNTO 0 );
R_E_CTRL_RD6DOWNTO0_intermed_1 <= R.E.CTRL.RD( 6 DOWNTO 0 );
V_E_CTRL_RD6DOWNTO0_shadow_intermed_1 <= V_E_CTRL_RD6DOWNTO0_shadow;
V_E_CTRL_RD6DOWNTO0_shadow_intermed_2 <= V_E_CTRL_RD6DOWNTO0_shadow_intermed_1;
V_A_CTRL_RD6DOWNTO0_shadow_intermed_1 <= V_A_CTRL_RD6DOWNTO0_shadow;
V_A_CTRL_RD6DOWNTO0_shadow_intermed_2 <= V_A_CTRL_RD6DOWNTO0_shadow_intermed_1;
V_A_CTRL_RD6DOWNTO0_shadow_intermed_3 <= V_A_CTRL_RD6DOWNTO0_shadow_intermed_2;
R_A_CTRL_RD6DOWNTO0_intermed_1 <= R.A.CTRL.RD( 6 DOWNTO 0 );
R_A_CTRL_RD6DOWNTO0_intermed_2 <= R_A_CTRL_RD6DOWNTO0_intermed_1;
RIN_A_CTRL_RD6DOWNTO0_intermed_1 <= RIN.A.CTRL.RD( 6 DOWNTO 0 );
RIN_A_CTRL_RD6DOWNTO0_intermed_2 <= RIN_A_CTRL_RD6DOWNTO0_intermed_1;
RIN_A_CTRL_RD6DOWNTO0_intermed_3 <= RIN_A_CTRL_RD6DOWNTO0_intermed_2;
RIN_A_CTRL_TT_intermed_1 <= RIN.A.CTRL.TT;
RIN_A_CTRL_TT_intermed_2 <= RIN_A_CTRL_TT_intermed_1;
R_A_CTRL_TT_intermed_1 <= R.A.CTRL.TT;
RIN_E_CTRL_TT_intermed_1 <= RIN.E.CTRL.TT;
V_A_CTRL_TT_shadow_intermed_1 <= V_A_CTRL_TT_shadow;
V_A_CTRL_TT_shadow_intermed_2 <= V_A_CTRL_TT_shadow_intermed_1;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow;
V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_2 <= V_X_RESULT6DOWNTO03DOWNTO0_shadow_intermed_1;
R_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= R.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT( 6 DOWNTO 0 )( 3 DOWNTO 0 );
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_2 <= RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1;
RIN_X_RESULT6DOWNTO03DOWNTO0_intermed_1 <= RIN.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 );
R_M_CTRL_TT3DOWNTO0_intermed_1 <= R.M.CTRL.TT( 3 DOWNTO 0 );
R_A_CTRL_TT3DOWNTO0_intermed_1 <= R.A.CTRL.TT( 3 DOWNTO 0 );
R_A_CTRL_TT3DOWNTO0_intermed_2 <= R_A_CTRL_TT3DOWNTO0_intermed_1;
R_A_CTRL_TT3DOWNTO0_intermed_3 <= R_A_CTRL_TT3DOWNTO0_intermed_2;
RIN_A_CTRL_TT3DOWNTO0_intermed_1 <= RIN.A.CTRL.TT( 3 DOWNTO 0 );
RIN_A_CTRL_TT3DOWNTO0_intermed_2 <= RIN_A_CTRL_TT3DOWNTO0_intermed_1;
RIN_A_CTRL_TT3DOWNTO0_intermed_3 <= RIN_A_CTRL_TT3DOWNTO0_intermed_2;
RIN_A_CTRL_TT3DOWNTO0_intermed_4 <= RIN_A_CTRL_TT3DOWNTO0_intermed_3;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_A_CTRL_TT3DOWNTO0_shadow;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_2;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_4 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_3;
R_E_CTRL_TT3DOWNTO0_intermed_1 <= R.E.CTRL.TT( 3 DOWNTO 0 );
R_E_CTRL_TT3DOWNTO0_intermed_2 <= R_E_CTRL_TT3DOWNTO0_intermed_1;
RIN_M_CTRL_TT3DOWNTO0_intermed_1 <= RIN.M.CTRL.TT( 3 DOWNTO 0 );
RIN_M_CTRL_TT3DOWNTO0_intermed_2 <= RIN_M_CTRL_TT3DOWNTO0_intermed_1;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_M_CTRL_TT3DOWNTO0_shadow;
V_M_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_M_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_E_CTRL_TT3DOWNTO0_shadow;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_2;
RIN_X_CTRL_TT3DOWNTO0_intermed_1 <= RIN.X.CTRL.TT( 3 DOWNTO 0 );
RIN_E_CTRL_TT3DOWNTO0_intermed_1 <= RIN.E.CTRL.TT( 3 DOWNTO 0 );
RIN_E_CTRL_TT3DOWNTO0_intermed_2 <= RIN_E_CTRL_TT3DOWNTO0_intermed_1;
RIN_E_CTRL_TT3DOWNTO0_intermed_3 <= RIN_E_CTRL_TT3DOWNTO0_intermed_2;
R_M_CTRL_PC31DOWNTO12_intermed_1 <= R.M.CTRL.PC( 31 DOWNTO 12 );
V_D_PC31DOWNTO12_shadow_intermed_1 <= V_D_PC31DOWNTO12_shadow;
V_D_PC31DOWNTO12_shadow_intermed_2 <= V_D_PC31DOWNTO12_shadow_intermed_1;
V_D_PC31DOWNTO12_shadow_intermed_3 <= V_D_PC31DOWNTO12_shadow_intermed_2;
V_D_PC31DOWNTO12_shadow_intermed_4 <= V_D_PC31DOWNTO12_shadow_intermed_3;
V_D_PC31DOWNTO12_shadow_intermed_5 <= V_D_PC31DOWNTO12_shadow_intermed_4;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO12_shadow;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_4 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO12_shadow;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_2;
R_A_CTRL_PC31DOWNTO12_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 12 );
R_A_CTRL_PC31DOWNTO12_intermed_2 <= R_A_CTRL_PC31DOWNTO12_intermed_1;
R_A_CTRL_PC31DOWNTO12_intermed_3 <= R_A_CTRL_PC31DOWNTO12_intermed_2;
R_E_CTRL_PC31DOWNTO12_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 12 );
R_E_CTRL_PC31DOWNTO12_intermed_2 <= R_E_CTRL_PC31DOWNTO12_intermed_1;
RIN_A_CTRL_PC31DOWNTO12_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_2 <= RIN_A_CTRL_PC31DOWNTO12_intermed_1;
RIN_A_CTRL_PC31DOWNTO12_intermed_3 <= RIN_A_CTRL_PC31DOWNTO12_intermed_2;
RIN_A_CTRL_PC31DOWNTO12_intermed_4 <= RIN_A_CTRL_PC31DOWNTO12_intermed_3;
RIN_E_CTRL_PC31DOWNTO12_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 12 );
RIN_E_CTRL_PC31DOWNTO12_intermed_2 <= RIN_E_CTRL_PC31DOWNTO12_intermed_1;
RIN_E_CTRL_PC31DOWNTO12_intermed_3 <= RIN_E_CTRL_PC31DOWNTO12_intermed_2;
RIN_M_CTRL_PC31DOWNTO12_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 12 );
RIN_M_CTRL_PC31DOWNTO12_intermed_2 <= RIN_M_CTRL_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_1 <= R.D.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_2 <= R_D_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_3 <= R_D_PC31DOWNTO12_intermed_2;
R_D_PC31DOWNTO12_intermed_4 <= R_D_PC31DOWNTO12_intermed_3;
RIN_X_CTRL_PC31DOWNTO12_intermed_1 <= RIN.X.CTRL.PC( 31 DOWNTO 12 );
RIN_D_PC31DOWNTO12_intermed_1 <= RIN.D.PC( 31 DOWNTO 12 );
RIN_D_PC31DOWNTO12_intermed_2 <= RIN_D_PC31DOWNTO12_intermed_1;
RIN_D_PC31DOWNTO12_intermed_3 <= RIN_D_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_4 <= RIN_D_PC31DOWNTO12_intermed_3;
RIN_D_PC31DOWNTO12_intermed_5 <= RIN_D_PC31DOWNTO12_intermed_4;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_M_CTRL_PC31DOWNTO12_shadow;
V_M_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_M_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_A_CTRL_RD7DOWNTO0_shadow_intermed_1 <= V_A_CTRL_RD7DOWNTO0_shadow;
V_A_CTRL_RD7DOWNTO0_shadow_intermed_2 <= V_A_CTRL_RD7DOWNTO0_shadow_intermed_1;
RIN_A_CTRL_RD7DOWNTO0_intermed_1 <= RIN.A.CTRL.RD ( 7 DOWNTO 0 );
RIN_A_CTRL_RD7DOWNTO0_intermed_2 <= RIN_A_CTRL_RD7DOWNTO0_intermed_1;
R_A_CTRL_RD7DOWNTO0_intermed_1 <= R.A.CTRL.RD ( 7 DOWNTO 0 );
RIN_E_CTRL_RD7DOWNTO0_intermed_1 <= RIN.E.CTRL.RD ( 7 DOWNTO 0 );
RIN_D_PC_intermed_1 <= RIN.D.PC;
RIN_D_PC_intermed_2 <= RIN_D_PC_intermed_1;
RIN_D_PC_intermed_3 <= RIN_D_PC_intermed_2;
RIN_A_CTRL_PC_intermed_1 <= RIN.A.CTRL.PC;
RIN_A_CTRL_PC_intermed_2 <= RIN_A_CTRL_PC_intermed_1;
R_A_CTRL_PC_intermed_1 <= R.A.CTRL.PC;
V_A_CTRL_PC_shadow_intermed_1 <= V_A_CTRL_PC_shadow;
V_A_CTRL_PC_shadow_intermed_2 <= V_A_CTRL_PC_shadow_intermed_1;
R_D_PC_intermed_1 <= R.D.PC;
R_D_PC_intermed_2 <= R_D_PC_intermed_1;
RIN_E_CTRL_PC_intermed_1 <= RIN.E.CTRL.PC;
V_D_PC_shadow_intermed_1 <= V_D_PC_shadow;
V_D_PC_shadow_intermed_2 <= V_D_PC_shadow_intermed_1;
V_D_PC_shadow_intermed_3 <= V_D_PC_shadow_intermed_2;
V_D_PC31DOWNTO2_shadow_intermed_1 <= V_D_PC31DOWNTO2_shadow;
V_D_PC31DOWNTO2_shadow_intermed_2 <= V_D_PC31DOWNTO2_shadow_intermed_1;
V_D_PC31DOWNTO2_shadow_intermed_3 <= V_D_PC31DOWNTO2_shadow_intermed_2;
RIN_D_PC31DOWNTO2_intermed_1 <= RIN.D.PC( 31 DOWNTO 2 );
RIN_D_PC31DOWNTO2_intermed_2 <= RIN_D_PC31DOWNTO2_intermed_1;
RIN_D_PC31DOWNTO2_intermed_3 <= RIN_D_PC31DOWNTO2_intermed_2;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO2_shadow;
V_A_CTRL_PC31DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO2_shadow_intermed_1;
R_D_PC31DOWNTO2_intermed_1 <= R.D.PC( 31 DOWNTO 2 );
R_D_PC31DOWNTO2_intermed_2 <= R_D_PC31DOWNTO2_intermed_1;
RIN_A_CTRL_PC31DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO2_intermed_2 <= RIN_A_CTRL_PC31DOWNTO2_intermed_1;
R_A_CTRL_PC31DOWNTO2_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 2 );
RIN_E_CTRL_PC31DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 2 );
RIN_A_CTRL_PC31DOWNTO4_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 4 );
RIN_A_CTRL_PC31DOWNTO4_intermed_2 <= RIN_A_CTRL_PC31DOWNTO4_intermed_1;
RIN_A_CTRL_PC31DOWNTO4_intermed_3 <= RIN_A_CTRL_PC31DOWNTO4_intermed_2;
R_A_CTRL_PC31DOWNTO4_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 4 );
R_A_CTRL_PC31DOWNTO4_intermed_2 <= R_A_CTRL_PC31DOWNTO4_intermed_1;
R_D_PC31DOWNTO4_intermed_1 <= R.D.PC( 31 DOWNTO 4 );
R_D_PC31DOWNTO4_intermed_2 <= R_D_PC31DOWNTO4_intermed_1;
R_D_PC31DOWNTO4_intermed_3 <= R_D_PC31DOWNTO4_intermed_2;
V_D_PC31DOWNTO4_shadow_intermed_1 <= V_D_PC31DOWNTO4_shadow;
V_D_PC31DOWNTO4_shadow_intermed_2 <= V_D_PC31DOWNTO4_shadow_intermed_1;
V_D_PC31DOWNTO4_shadow_intermed_3 <= V_D_PC31DOWNTO4_shadow_intermed_2;
V_D_PC31DOWNTO4_shadow_intermed_4 <= V_D_PC31DOWNTO4_shadow_intermed_3;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO4_shadow;
V_E_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO4_shadow_intermed_1;
RIN_M_CTRL_PC31DOWNTO4_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 4 );
RIN_D_PC31DOWNTO4_intermed_1 <= RIN.D.PC( 31 DOWNTO 4 );
RIN_D_PC31DOWNTO4_intermed_2 <= RIN_D_PC31DOWNTO4_intermed_1;
RIN_D_PC31DOWNTO4_intermed_3 <= RIN_D_PC31DOWNTO4_intermed_2;
RIN_D_PC31DOWNTO4_intermed_4 <= RIN_D_PC31DOWNTO4_intermed_3;
RIN_E_CTRL_PC31DOWNTO4_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 4 );
RIN_E_CTRL_PC31DOWNTO4_intermed_2 <= RIN_E_CTRL_PC31DOWNTO4_intermed_1;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO4_shadow;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_2;
R_E_CTRL_PC31DOWNTO4_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 4 );
R_D_PC3DOWNTO2_intermed_1 <= R.D.PC( 3 DOWNTO 2 );
R_D_PC3DOWNTO2_intermed_2 <= R_D_PC3DOWNTO2_intermed_1;
R_D_PC3DOWNTO2_intermed_3 <= R_D_PC3DOWNTO2_intermed_2;
V_D_PC3DOWNTO2_shadow_intermed_1 <= V_D_PC3DOWNTO2_shadow;
V_D_PC3DOWNTO2_shadow_intermed_2 <= V_D_PC3DOWNTO2_shadow_intermed_1;
V_D_PC3DOWNTO2_shadow_intermed_3 <= V_D_PC3DOWNTO2_shadow_intermed_2;
V_D_PC3DOWNTO2_shadow_intermed_4 <= V_D_PC3DOWNTO2_shadow_intermed_3;
RIN_D_PC3DOWNTO2_intermed_1 <= RIN.D.PC( 3 DOWNTO 2 );
RIN_D_PC3DOWNTO2_intermed_2 <= RIN_D_PC3DOWNTO2_intermed_1;
RIN_D_PC3DOWNTO2_intermed_3 <= RIN_D_PC3DOWNTO2_intermed_2;
RIN_D_PC3DOWNTO2_intermed_4 <= RIN_D_PC3DOWNTO2_intermed_3;
R_E_CTRL_PC3DOWNTO2_intermed_1 <= R.E.CTRL.PC( 3 DOWNTO 2 );
V_E_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_E_CTRL_PC3DOWNTO2_shadow;
V_E_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_E_CTRL_PC3DOWNTO2_shadow_intermed_1;
R_A_CTRL_PC3DOWNTO2_intermed_1 <= R.A.CTRL.PC( 3 DOWNTO 2 );
R_A_CTRL_PC3DOWNTO2_intermed_2 <= R_A_CTRL_PC3DOWNTO2_intermed_1;
RIN_M_CTRL_PC3DOWNTO2_intermed_1 <= RIN.M.CTRL.PC( 3 DOWNTO 2 );
RIN_A_CTRL_PC3DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 3 DOWNTO 2 );
RIN_A_CTRL_PC3DOWNTO2_intermed_2 <= RIN_A_CTRL_PC3DOWNTO2_intermed_1;
RIN_A_CTRL_PC3DOWNTO2_intermed_3 <= RIN_A_CTRL_PC3DOWNTO2_intermed_2;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC3DOWNTO2_shadow;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_1;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_3 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_2;
RIN_E_CTRL_PC3DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 3 DOWNTO 2 );
RIN_E_CTRL_PC3DOWNTO2_intermed_2 <= RIN_E_CTRL_PC3DOWNTO2_intermed_1;
RIN_E_CTRL_RD6DOWNTO0_intermed_1 <= RIN.E.CTRL.RD( 6 DOWNTO 0 );
V_A_CTRL_RD6DOWNTO0_shadow_intermed_1 <= V_A_CTRL_RD6DOWNTO0_shadow;
V_A_CTRL_RD6DOWNTO0_shadow_intermed_2 <= V_A_CTRL_RD6DOWNTO0_shadow_intermed_1;
R_A_CTRL_RD6DOWNTO0_intermed_1 <= R.A.CTRL.RD( 6 DOWNTO 0 );
RIN_A_CTRL_RD6DOWNTO0_intermed_1 <= RIN.A.CTRL.RD( 6 DOWNTO 0 );
RIN_A_CTRL_RD6DOWNTO0_intermed_2 <= RIN_A_CTRL_RD6DOWNTO0_intermed_1;
R_A_CTRL_TT3DOWNTO0_intermed_1 <= R.A.CTRL.TT( 3 DOWNTO 0 );
R_A_CTRL_TT3DOWNTO0_intermed_2 <= R_A_CTRL_TT3DOWNTO0_intermed_1;
RIN_A_CTRL_TT3DOWNTO0_intermed_1 <= RIN.A.CTRL.TT( 3 DOWNTO 0 );
RIN_A_CTRL_TT3DOWNTO0_intermed_2 <= RIN_A_CTRL_TT3DOWNTO0_intermed_1;
RIN_A_CTRL_TT3DOWNTO0_intermed_3 <= RIN_A_CTRL_TT3DOWNTO0_intermed_2;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_A_CTRL_TT3DOWNTO0_shadow;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_1;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_3 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_2;
R_E_CTRL_TT3DOWNTO0_intermed_1 <= R.E.CTRL.TT( 3 DOWNTO 0 );
RIN_M_CTRL_TT3DOWNTO0_intermed_1 <= RIN.M.CTRL.TT( 3 DOWNTO 0 );
V_E_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_E_CTRL_TT3DOWNTO0_shadow;
V_E_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_E_CTRL_TT3DOWNTO0_shadow_intermed_1;
RIN_E_CTRL_TT3DOWNTO0_intermed_1 <= RIN.E.CTRL.TT( 3 DOWNTO 0 );
RIN_E_CTRL_TT3DOWNTO0_intermed_2 <= RIN_E_CTRL_TT3DOWNTO0_intermed_1;
V_D_PC31DOWNTO12_shadow_intermed_1 <= V_D_PC31DOWNTO12_shadow;
V_D_PC31DOWNTO12_shadow_intermed_2 <= V_D_PC31DOWNTO12_shadow_intermed_1;
V_D_PC31DOWNTO12_shadow_intermed_3 <= V_D_PC31DOWNTO12_shadow_intermed_2;
V_D_PC31DOWNTO12_shadow_intermed_4 <= V_D_PC31DOWNTO12_shadow_intermed_3;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO12_shadow;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_1;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_3 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_2;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_E_CTRL_PC31DOWNTO12_shadow;
V_E_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_E_CTRL_PC31DOWNTO12_shadow_intermed_1;
R_A_CTRL_PC31DOWNTO12_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 12 );
R_A_CTRL_PC31DOWNTO12_intermed_2 <= R_A_CTRL_PC31DOWNTO12_intermed_1;
R_E_CTRL_PC31DOWNTO12_intermed_1 <= R.E.CTRL.PC( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_2 <= RIN_A_CTRL_PC31DOWNTO12_intermed_1;
RIN_A_CTRL_PC31DOWNTO12_intermed_3 <= RIN_A_CTRL_PC31DOWNTO12_intermed_2;
RIN_E_CTRL_PC31DOWNTO12_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 12 );
RIN_E_CTRL_PC31DOWNTO12_intermed_2 <= RIN_E_CTRL_PC31DOWNTO12_intermed_1;
RIN_M_CTRL_PC31DOWNTO12_intermed_1 <= RIN.M.CTRL.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_1 <= R.D.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_2 <= R_D_PC31DOWNTO12_intermed_1;
R_D_PC31DOWNTO12_intermed_3 <= R_D_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_1 <= RIN.D.PC( 31 DOWNTO 12 );
RIN_D_PC31DOWNTO12_intermed_2 <= RIN_D_PC31DOWNTO12_intermed_1;
RIN_D_PC31DOWNTO12_intermed_3 <= RIN_D_PC31DOWNTO12_intermed_2;
RIN_D_PC31DOWNTO12_intermed_4 <= RIN_D_PC31DOWNTO12_intermed_3;
RIN_A_CTRL_PC31DOWNTO4_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 4 );
RIN_A_CTRL_PC31DOWNTO4_intermed_2 <= RIN_A_CTRL_PC31DOWNTO4_intermed_1;
R_A_CTRL_PC31DOWNTO4_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 4 );
R_D_PC31DOWNTO4_intermed_1 <= R.D.PC( 31 DOWNTO 4 );
R_D_PC31DOWNTO4_intermed_2 <= R_D_PC31DOWNTO4_intermed_1;
V_D_PC31DOWNTO4_shadow_intermed_1 <= V_D_PC31DOWNTO4_shadow;
V_D_PC31DOWNTO4_shadow_intermed_2 <= V_D_PC31DOWNTO4_shadow_intermed_1;
V_D_PC31DOWNTO4_shadow_intermed_3 <= V_D_PC31DOWNTO4_shadow_intermed_2;
RIN_D_PC31DOWNTO4_intermed_1 <= RIN.D.PC( 31 DOWNTO 4 );
RIN_D_PC31DOWNTO4_intermed_2 <= RIN_D_PC31DOWNTO4_intermed_1;
RIN_D_PC31DOWNTO4_intermed_3 <= RIN_D_PC31DOWNTO4_intermed_2;
RIN_E_CTRL_PC31DOWNTO4_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 4 );
V_A_CTRL_PC31DOWNTO4_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO4_shadow;
V_A_CTRL_PC31DOWNTO4_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO4_shadow_intermed_1;
R_D_PC3DOWNTO2_intermed_1 <= R.D.PC( 3 DOWNTO 2 );
R_D_PC3DOWNTO2_intermed_2 <= R_D_PC3DOWNTO2_intermed_1;
V_D_PC3DOWNTO2_shadow_intermed_1 <= V_D_PC3DOWNTO2_shadow;
V_D_PC3DOWNTO2_shadow_intermed_2 <= V_D_PC3DOWNTO2_shadow_intermed_1;
V_D_PC3DOWNTO2_shadow_intermed_3 <= V_D_PC3DOWNTO2_shadow_intermed_2;
RIN_D_PC3DOWNTO2_intermed_1 <= RIN.D.PC( 3 DOWNTO 2 );
RIN_D_PC3DOWNTO2_intermed_2 <= RIN_D_PC3DOWNTO2_intermed_1;
RIN_D_PC3DOWNTO2_intermed_3 <= RIN_D_PC3DOWNTO2_intermed_2;
R_A_CTRL_PC3DOWNTO2_intermed_1 <= R.A.CTRL.PC( 3 DOWNTO 2 );
RIN_A_CTRL_PC3DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 3 DOWNTO 2 );
RIN_A_CTRL_PC3DOWNTO2_intermed_2 <= RIN_A_CTRL_PC3DOWNTO2_intermed_1;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_1 <= V_A_CTRL_PC3DOWNTO2_shadow;
V_A_CTRL_PC3DOWNTO2_shadow_intermed_2 <= V_A_CTRL_PC3DOWNTO2_shadow_intermed_1;
RIN_E_CTRL_PC3DOWNTO2_intermed_1 <= RIN.E.CTRL.PC( 3 DOWNTO 2 );
R_A_CTRL_TT3DOWNTO0_intermed_1 <= R.A.CTRL.TT( 3 DOWNTO 0 );
RIN_A_CTRL_TT3DOWNTO0_intermed_1 <= RIN.A.CTRL.TT( 3 DOWNTO 0 );
RIN_A_CTRL_TT3DOWNTO0_intermed_2 <= RIN_A_CTRL_TT3DOWNTO0_intermed_1;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_1 <= V_A_CTRL_TT3DOWNTO0_shadow;
V_A_CTRL_TT3DOWNTO0_shadow_intermed_2 <= V_A_CTRL_TT3DOWNTO0_shadow_intermed_1;
RIN_E_CTRL_TT3DOWNTO0_intermed_1 <= RIN.E.CTRL.TT( 3 DOWNTO 0 );
V_D_PC31DOWNTO12_shadow_intermed_1 <= V_D_PC31DOWNTO12_shadow;
V_D_PC31DOWNTO12_shadow_intermed_2 <= V_D_PC31DOWNTO12_shadow_intermed_1;
V_D_PC31DOWNTO12_shadow_intermed_3 <= V_D_PC31DOWNTO12_shadow_intermed_2;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_1 <= V_A_CTRL_PC31DOWNTO12_shadow;
V_A_CTRL_PC31DOWNTO12_shadow_intermed_2 <= V_A_CTRL_PC31DOWNTO12_shadow_intermed_1;
R_A_CTRL_PC31DOWNTO12_intermed_1 <= R.A.CTRL.PC( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 12 );
RIN_A_CTRL_PC31DOWNTO12_intermed_2 <= RIN_A_CTRL_PC31DOWNTO12_intermed_1;
RIN_E_CTRL_PC31DOWNTO12_intermed_1 <= RIN.E.CTRL.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_1 <= R.D.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_2 <= R_D_PC31DOWNTO12_intermed_1;
RIN_D_PC31DOWNTO12_intermed_1 <= RIN.D.PC( 31 DOWNTO 12 );
RIN_D_PC31DOWNTO12_intermed_2 <= RIN_D_PC31DOWNTO12_intermed_1;
RIN_D_PC31DOWNTO12_intermed_3 <= RIN_D_PC31DOWNTO12_intermed_2;
RIN_A_CTRL_PC31DOWNTO4_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 4 );
R_D_PC31DOWNTO4_intermed_1 <= R.D.PC( 31 DOWNTO 4 );
V_D_PC31DOWNTO4_shadow_intermed_1 <= V_D_PC31DOWNTO4_shadow;
V_D_PC31DOWNTO4_shadow_intermed_2 <= V_D_PC31DOWNTO4_shadow_intermed_1;
RIN_D_PC31DOWNTO4_intermed_1 <= RIN.D.PC( 31 DOWNTO 4 );
RIN_D_PC31DOWNTO4_intermed_2 <= RIN_D_PC31DOWNTO4_intermed_1;
R_D_PC3DOWNTO2_intermed_1 <= R.D.PC( 3 DOWNTO 2 );
V_D_PC3DOWNTO2_shadow_intermed_1 <= V_D_PC3DOWNTO2_shadow;
V_D_PC3DOWNTO2_shadow_intermed_2 <= V_D_PC3DOWNTO2_shadow_intermed_1;
RIN_D_PC3DOWNTO2_intermed_1 <= RIN.D.PC( 3 DOWNTO 2 );
RIN_D_PC3DOWNTO2_intermed_2 <= RIN_D_PC3DOWNTO2_intermed_1;
RIN_A_CTRL_PC3DOWNTO2_intermed_1 <= RIN.A.CTRL.PC( 3 DOWNTO 2 );
V_D_PC31DOWNTO12_shadow_intermed_1 <= V_D_PC31DOWNTO12_shadow;
V_D_PC31DOWNTO12_shadow_intermed_2 <= V_D_PC31DOWNTO12_shadow_intermed_1;
RIN_A_CTRL_PC31DOWNTO12_intermed_1 <= RIN.A.CTRL.PC( 31 DOWNTO 12 );
R_D_PC31DOWNTO12_intermed_1 <= R.D.PC( 31 DOWNTO 12 );
RIN_D_PC31DOWNTO12_intermed_1 <= RIN.D.PC( 31 DOWNTO 12 );
RIN_D_PC31DOWNTO12_intermed_2 <= RIN_D_PC31DOWNTO12_intermed_1;
end if;
end process;
dfp_trap_vector(0) <= '1' when (RP.ERROR /= RPIN_ERROR_intermed_1) else '0';
dfp_trap_vector(1) <= '1' when (RP.ERROR /= VP_ERROR_shadow_intermed_1) else '0';
dfp_trap_vector(2) <= '1' when (RFI.REN1 /= DE_REN1_shadow) else '0';
dfp_trap_vector(3) <= '1' when (RFI.REN2 /= DE_REN2_shadow) else '0';
dfp_trap_vector(4) <= '1' when (RFI.DIAG(0) /= DCO.TESTEN) else '0';
dfp_trap_vector(5) <= '1' when (RFI.DIAG /= "0000") else '0';
dfp_trap_vector(6) <= '1' when (ICI.DPC(31 downto 2) /= R.D.PC ( 31 DOWNTO 2 )) else '0';
dfp_trap_vector(7) <= '1' when (ICI.FPC(31 downto 2) /= R.F.PC ( 31 DOWNTO 2 )) else '0';
dfp_trap_vector(8) <= '1' when (ICI.RPC(31 downto 2) /= NPC31DOWNTO2_shadow) else '0';
dfp_trap_vector(9) <= '1' when (ICI.FLUSHL /= '0') else '0';
dfp_trap_vector(10) <= '1' when (MULI.OP1(31 downto 0) /= EX_OP1_shadow) else '0';
dfp_trap_vector(11) <= '1' when (MULI.OP1(31) /= EX_OP131_shadow) else '0';
dfp_trap_vector(12) <= '1' when (MULI.OP2(31 downto 0) /= MUL_OP2_shadow) else '0';
dfp_trap_vector(13) <= '1' when (MULI.OP2(31) /= MUL_OP231_shadow) else '0';
dfp_trap_vector(14) <= '1' when (DIVI.START /= R.A.DIVSTART) else '0';
dfp_trap_vector(15) <= '1' when (DIVI.OP1(31 downto 0) /= EX_OP1_shadow) else '0';
dfp_trap_vector(16) <= '1' when (DIVI.OP1(31) /= EX_OP131_shadow) else '0';
dfp_trap_vector(17) <= '1' when (DIVI.OP2(31) /= EX_OP231_shadow) else '0';
dfp_trap_vector(18) <= '1' when (DIVI.OP2(31 downto 0) /= EX_OP2_shadow) else '0';
dfp_trap_vector(19) <= '1' when (DIVI.Y(31 downto 0) /= R.M.Y) else '0';
dfp_trap_vector(20) <= '1' when (DIVI.Y(31) /= R.M.Y ( 31 )) else '0';
dfp_trap_vector(21) <= '1' when (EX_JUMP_ADDRESS31DOWNTO12_shadow /= EX_ADD_RES32DOWNTO332DOWNTO13_shadow) else '0';
dfp_trap_vector(22) <= '1' when (DSUR.CRDY ( 2 ) /= DSUIN_CRDY2_intermed_1) else '0';
dfp_trap_vector(23) <= '1' when (DSUR.CRDY ( 2 ) /= VDSU_CRDY2_shadow_intermed_1) else '0';
dfp_trap_vector(24) <= '1' when (V_A_STEP_shadow /= RIN_A_STEP_intermed_1) else '0';
dfp_trap_vector(25) <= '1' when (V_D_STEP_shadow /= RIN_D_STEP_intermed_1) else '0';
dfp_trap_vector(26) <= '1' when (V_D_STEP_shadow /= DBGI.STEP) else '0';
dfp_trap_vector(27) <= '1' when (V_D_STEP_shadow /= R.D.STEP) else '0';
dfp_trap_vector(28) <= '1' when (RIN.X.RESULT ( 6 DOWNTO 0 ) /= V_X_RESULT6DOWNTO0_shadow) else '0';
dfp_trap_vector(29) <= '1' when (RIN.X.DATA ( 0 ) /= V_X_DATA0_shadow) else '0';
dfp_trap_vector(30) <= '1' when (RIN.X.CTRL.PC ( 31 DOWNTO 2 ) /= V_X_CTRL_PC31DOWNTO2_shadow) else '0';
dfp_trap_vector(31) <= '1' when (RIN.X.CTRL.PC ( 31 DOWNTO 2 ) /= R.M.CTRL.PC ( 31 DOWNTO 2 )) else '0';
dfp_trap_vector(32) <= '1' when (RIN.W.S.TT ( 3 DOWNTO 0 ) /= V_W_S_TT3DOWNTO0_shadow) else '0';
dfp_trap_vector(33) <= '1' when (RIN.M.RESULT ( 1 DOWNTO 0 ) /= V_M_RESULT1DOWNTO0_shadow) else '0';
dfp_trap_vector(34) <= '1' when (RIN.X.DATA ( 0 ) ( 31 ) /= V_X_DATA031_shadow) else '0';
dfp_trap_vector(35) <= '1' when (RIN.X.DATA ( 0 )( 31 ) /= V_X_DATA031_shadow) else '0';
dfp_trap_vector(36) <= '1' when (RIN.E.CTRL.INST ( 19 ) /= V_E_CTRL_INST19_shadow) else '0';
dfp_trap_vector(37) <= '1' when (RIN.E.CTRL.INST ( 19 ) /= R.A.CTRL.INST ( 19 )) else '0';
dfp_trap_vector(38) <= '1' when (RIN.E.CTRL.INST ( 20 ) /= R.A.CTRL.INST ( 20 )) else '0';
dfp_trap_vector(39) <= '1' when (RIN.E.CTRL.INST ( 20 ) /= V_E_CTRL_INST20_shadow) else '0';
dfp_trap_vector(40) <= '1' when (RIN.X.DATA ( 0 ) ( 0 ) /= V_X_DATA00_shadow) else '0';
dfp_trap_vector(41) <= '1' when (RIN.X.DATA ( 0 )( 0 ) /= V_X_DATA00_shadow) else '0';
dfp_trap_vector(42) <= '1' when (RIN.X.DATA ( 0 ) ( 4 DOWNTO 0 ) /= V_X_DATA04DOWNTO0_shadow) else '0';
dfp_trap_vector(43) <= '1' when (RIN.X.DATA ( 0 )( 4 DOWNTO 0 ) /= V_X_DATA04DOWNTO0_shadow) else '0';
dfp_trap_vector(44) <= '1' when (RIN.F.PC ( 31 DOWNTO 2 ) /= V_F_PC31DOWNTO2_shadow) else '0';
dfp_trap_vector(45) <= '1' when (RIN.D.PC ( 31 DOWNTO 2 ) /= V_D_PC31DOWNTO2_shadow) else '0';
dfp_trap_vector(46) <= '1' when (RIN.E.CTRL.INST ( 24 ) /= V_E_CTRL_INST24_shadow) else '0';
dfp_trap_vector(47) <= '1' when (RIN.E.CTRL.INST ( 24 ) /= R.A.CTRL.INST ( 24 )) else '0';
dfp_trap_vector(48) <= '1' when (RIN.A.CTRL.INST ( 19 ) /= V_A_CTRL_INST19_shadow) else '0';
dfp_trap_vector(49) <= '1' when (RIN.M.Y ( 31 ) /= V_M_Y31_shadow) else '0';
dfp_trap_vector(50) <= '1' when (V_A_STEP_shadow /= R.D.STEP) else '0';
dfp_trap_vector(51) <= '1' when (DSUIN.CRDY ( 2 ) /= VDSU_CRDY2_shadow) else '0';
dfp_trap_vector(52) <= '1' when (V_A_STEP_shadow /= R.A.STEP) else '0';
dfp_trap_vector(53) <= '1' when (V_A_STEP_shadow /= DBGI_STEP_intermed_1) else '0';
dfp_trap_vector(54) <= '1' when (V_A_STEP_shadow /= V_D_STEP_shadow_intermed_1) else '0';
dfp_trap_vector(55) <= '1' when (RIN.A.CTRL.PC ( 31 DOWNTO 2 ) /= V_A_CTRL_PC31DOWNTO2_shadow) else '0';
dfp_trap_vector(56) <= '1' when (RIN.E.CTRL.PC ( 31 DOWNTO 2 ) /= R.A.CTRL.PC ( 31 DOWNTO 2 )) else '0';
dfp_trap_vector(57) <= '1' when (RIN.E.CTRL.PC ( 31 DOWNTO 2 ) /= V_E_CTRL_PC31DOWNTO2_shadow) else '0';
dfp_trap_vector(58) <= '1' when (RIN.M.CTRL.PC ( 31 DOWNTO 2 ) /= V_M_CTRL_PC31DOWNTO2_shadow) else '0';
dfp_trap_vector(59) <= '1' when (RIN.M.CTRL.PC ( 31 DOWNTO 2 ) /= R.E.CTRL.PC ( 31 DOWNTO 2 )) else '0';
dfp_trap_vector(60) <= '1' when (RIN.X.DATA ( 1 ) /= V_X_DATA1_shadow) else '0';
dfp_trap_vector(61) <= '1' when (RIN.F.PC ( 31 DOWNTO 12 ) /= V_F_PC31DOWNTO12_shadow) else '0';
dfp_trap_vector(62) <= '1' when (RIN.D.INST ( 0 ) /= V_D_INST0_shadow) else '0';
dfp_trap_vector(63) <= '1' when (RIN.D.INST ( 1 ) /= V_D_INST1_shadow) else '0';
dfp_trap_vector(64) <= '1' when (RIN.X.DATA ( 0 )( 3 ) /= V_X_DATA03_shadow) else '0';
dfp_trap_vector(65) <= '1' when (RIN.A.CTRL.INST ( 20 ) /= V_A_CTRL_INST20_shadow) else '0';
dfp_trap_vector(66) <= '1' when (RIN.A.CTRL.INST ( 24 ) /= V_A_CTRL_INST24_shadow) else '0';
dfp_trap_vector(67) <= '1' when (RIN.X.RESULT ( 6 DOWNTO 0 )( 3 DOWNTO 0 ) /= V_X_RESULT6DOWNTO03DOWNTO0_shadow) else '0';
dfp_trap_vector(68) <= '1' when (XC_HALT_shadow /= DBGI.HALT) else '0';
dfp_trap_vector(69) <= '1' when (XC_HALT_shadow /= '0') else '0';
dfp_trap_vector(70) <= '1' when (V_A_CTRL_TT_shadow /= RIN_A_CTRL_TT_intermed_1) else '0';
dfp_trap_vector(71) <= '1' when (V_A_CTRL_TT_shadow /= R.A.CTRL.TT) else '0';
dfp_trap_vector(72) <= '1' when (V_A_CTRL_TT_shadow /= "000000") else '0';
dfp_trap_vector(73) <= '1' when (V_A_CTRL_INST_shadow /= DE_INST_shadow) else '0';
dfp_trap_vector(74) <= '1' when (V_A_CTRL_PC_shadow /= R.D.PC) else '0';
dfp_trap_vector(75) <= '1' when (V_A_CTRL_CNT_shadow /= R.D.CNT) else '0';
dfp_trap_vector(76) <= '1' when (V_A_STEP_shadow /= RIN_D_STEP_intermed_1) else '0';
dfp_trap_vector(77) <= '1' when (V_X_NERROR_shadow /= VP_ERROR_shadow_intermed_1) else '0';
dfp_trap_vector(78) <= '1' when (V_X_NERROR_shadow /= RPIN_ERROR_intermed_1) else '0';
dfp_trap_vector(79) <= '1' when (V_X_NERROR_shadow /= RP.ERROR) else '0';
dfp_trap_vector(80) <= '1' when (V_M_MAC_shadow /= R.E.MAC) else '0';
dfp_trap_vector(81) <= '1' when (V_M_MAC_shadow /= R.M.MAC) else '0';
dfp_trap_vector(82) <= '1' when (V_E_JMPL_shadow /= R.A.JMPL) else '0';
dfp_trap_vector(83) <= '1' when (V_E_CTRL_RETT_shadow /= R.A.CTRL.RETT) else '0';
dfp_trap_vector(84) <= '1' when (V_E_SU_shadow /= R.A.SU) else '0';
dfp_trap_vector(85) <= '1' when (V_E_ET_shadow /= R.A.ET) else '0';
dfp_trap_vector(86) <= '1' when (V_A_CWP_shadow /= R.D.CWP) else '0';
dfp_trap_vector(87) <= '1' when (V_A_CTRL_TRAP_shadow /= R.D.MEXC) else '0';
dfp_trap_vector(88) <= '1' when (V_A_CTRL_TRAP_shadow /= V_D_MEXC_shadow_intermed_1) else '0';
dfp_trap_vector(89) <= '1' when (V_A_CTRL_TRAP_shadow /= RIN_D_MEXC_intermed_1) else '0';
dfp_trap_vector(90) <= '1' when (VP_PWD_shadow /= RP.PWD) else '0';
dfp_trap_vector(91) <= '1' when (VP_PWD_shadow /= '0') else '0';
dfp_trap_vector(92) <= '1' when (VP_PWD_shadow /= RPIN_PWD_intermed_1) else '0';
dfp_trap_vector(93) <= '1' when (V_M_MUL_shadow /= R.M.MUL) else '0';
dfp_trap_vector(94) <= '1' when (V_M_MAC_shadow /= V_E_MAC_shadow_intermed_1) else '0';
dfp_trap_vector(95) <= '1' when (V_M_MAC_shadow /= RIN_M_MAC_intermed_1) else '0';
dfp_trap_vector(96) <= '1' when (V_M_MAC_shadow /= RIN_E_MAC_intermed_1) else '0';
dfp_trap_vector(97) <= '1' when (VDSU_TBUFCNT_shadow /= TBUFCNTX_shadow) else '0';
dfp_trap_vector(98) <= '1' when (V_M_MUL_shadow /= RIN_M_MUL_intermed_1) else '0';
dfp_trap_vector(99) <= '1' when (V_M_MUL_shadow /= '0') else '0';
dfp_trap_vector(100) <= '1' when (V_W_RESULT_shadow /= XC_RESULT_shadow) else '0';
dfp_trap_vector(101) <= '1' when (V_W_WA_shadow /= XC_WADDR7DOWNTO0_shadow) else '0';
dfp_trap_vector(102) <= '1' when (V_W_S_SVT_shadow /= R.W.S.SVT) else '0';
dfp_trap_vector(103) <= '1' when (V_W_S_SVT_shadow /= '0') else '0';
dfp_trap_vector(104) <= '1' when (V_W_S_SVT_shadow /= RIN_W_S_SVT_intermed_1) else '0';
dfp_trap_vector(105) <= '1' when (V_W_S_DWT_shadow /= RIN_W_S_DWT_intermed_1) else '0';
dfp_trap_vector(106) <= '1' when (V_W_S_DWT_shadow /= R.W.S.DWT) else '0';
dfp_trap_vector(107) <= '1' when (V_W_S_DWT_shadow /= '0') else '0';
dfp_trap_vector(108) <= '1' when (V_M_CTRL_RETT_shadow /= R.E.CTRL.RETT) else '0';
dfp_trap_vector(109) <= '1' when (V_E_CWP_shadow /= R.A.CWP) else '0';
dfp_trap_vector(110) <= '1' when (V_M_SU_shadow /= R.E.SU) else '0';
dfp_trap_vector(111) <= '1' when (V_X_DCI_shadow /= R.M.DCI) else '0';
dfp_trap_vector(112) <= '1' when (V_X_CTRL_RETT_shadow /= R.M.CTRL.RETT) else '0';
dfp_trap_vector(113) <= '1' when (V_X_MAC_shadow /= V_E_MAC_shadow_intermed_2) else '0';
dfp_trap_vector(114) <= '1' when (V_X_MAC_shadow /= RIN_M_MAC_intermed_1) else '0';
dfp_trap_vector(115) <= '1' when (V_X_MAC_shadow /= RIN_E_MAC_intermed_2) else '0';
dfp_trap_vector(116) <= '1' when (V_X_MAC_shadow /= R_E_MAC_intermed_1) else '0';
dfp_trap_vector(117) <= '1' when (V_X_MAC_shadow /= R.M.MAC) else '0';
dfp_trap_vector(118) <= '1' when (V_X_MAC_shadow /= V_M_MAC_shadow_intermed_1) else '0';
dfp_trap_vector(119) <= '1' when (V_X_MAC_shadow /= RIN_X_MAC_intermed_1) else '0';
dfp_trap_vector(120) <= '1' when (V_X_MAC_shadow /= R.X.MAC) else '0';
dfp_trap_vector(121) <= '1' when (V_X_LADDR_shadow /= R.M.RESULT ( 1 DOWNTO 0 )) else '0';
dfp_trap_vector(122) <= '1' when (V_X_MEXC_shadow /= DCO.MEXC) else '0';
dfp_trap_vector(123) <= '1' when (V_X_ICC_shadow /= ME_ICC_shadow) else '0';
dfp_or_reduce : process(dfp_trap_vector)
variable or_reduce_62 : std_logic_vector(61 downto 0);
variable or_reduce_31 : std_logic_vector(30 downto 0);
variable or_reduce_16 : std_logic_vector(15 downto 0);
variable or_reduce_8 : std_logic_vector(7 downto 0);
variable or_reduce_4 : std_logic_vector(3 downto 0);
variable or_reduce_2 : std_logic_vector(1 downto 0);
begin
or_reduce_62 := dfp_trap_vector(123 downto 62) OR dfp_trap_vector(61 downto 0);
or_reduce_31 := or_reduce_62(61 downto 31) OR or_reduce_62(30 downto 0);
or_reduce_16 := or_reduce_31(30 downto 15) OR ("0" & or_reduce_31(14 downto 0));
or_reduce_8 := or_reduce_16(15 downto 8) OR or_reduce_16(7 downto 0);
or_reduce_4 := or_reduce_8(7 downto 4) OR or_reduce_8(3 downto 0);
or_reduce_2 := or_reduce_4(3 downto 2) OR or_reduce_4(1 downto 0);
or_reduce_1 <= or_reduce_2(0) OR or_reduce_2(1);
end process;
trap_enable_delay : process(clk)
begin
if(rising_edge(clk))then
if(rstn = '0')then
dfp_delay_start <= 15;
elsif(dfp_delay_start /= 0)then
dfp_delay_start <= dfp_delay_start - 1;
end if;
end if;
end process;
trap_mem : process(clk)
begin
if(rising_edge(clk))then
if(rstn = '0')then
dfp_trap_mem <= (others => '0');
elsif(dfp_delay_start = 0)then
dfp_trap_mem <= dfp_trap_mem OR dfp_trap_vector;
end if;
end if;
end process;
handlerTrap <= or_reduce_1 when (dfp_delay_start = 0) else '0';
-- Control module for ChipScope Pro
dfp_bscan_host: iconScope
port map (
CONTROL0 => dfp_bscan_cntrl
);
-- Debugging probe for trap mask
dfp_bscan_value <= dfp_trap_mem;
dfp_probe_msk : scope
port map (
CONTROL => dfp_bscan_cntrl,
ASYNC_IN => dfp_bscan_value
);
preg : process (sclk)
begin
if rising_edge(sclk) then
rp <= rpin;
if rstn = '0' then
rp.error <= '0';
end if;
end if;
end process;
reg : process (clk)
begin
if rising_edge(clk) then
if (holdn = '1') then
r <= rin;
else
r.x.ipend <= rin.x.ipend;
r.m.werr <= rin.m.werr;
if (holdn or ico.mds) = '0' then
r.d.inst <= rin.d.inst;
r.d.mexc <= rin.d.mexc;
r.d.set <= rin.d.set;
end if;
if (holdn or dco.mds) = '0' then
r.x.data <= rin.x.data;
r.x.mexc <= rin.x.mexc;
r.x.set <= rin.x.set;
end if;
end if;
if rstn = '0' then
r.w.s.s <= '1';
r.w.s.ps <= '1';
end if;
end if;
end process;
dsureg : process(clk) begin
if rising_edge(clk) then
if holdn = '1' then
dsur <= dsuin;
else
dsur.crdy <= dsuin.crdy;
end if;
if holdn = '1' then
ir <= irin;
end if;
end if;
end process;
dummy <= '1';
end;
| mit | cddaf018a9cdd3b3877968a8eadd437e | 0.687165 | 2.272493 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | VhdlParser/test/iu3.vhd | 1 | 108,009 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008, 2009, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: iu3
-- File: iu3.vhd
-- Author: Jiri Gaisler, Edvin Catovic, Gaisler Research
-- Description: LEON3 7-stage integer pipline
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.sparc.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.leon3.all;
use gaisler.libiu.all;
use gaisler.arith.all;
-- pragma translate_off
use grlib.sparc_disas.all;
-- pragma translate_on
entity iu3 is
generic (
nwin : integer range 2 to 32 := 8;
isets : integer range 1 to 4 := 2;
dsets : integer range 1 to 4 := 2;
fpu : integer range 0 to 15 := 0;
v8 : integer range 0 to 63 := 2;
cp, mac : integer range 0 to 1 := 0;
dsu : integer range 0 to 1 := 1;
nwp : integer range 0 to 4 := 2;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
index : integer range 0 to 15:= 0;
lddel : integer range 1 to 2 := 1;
irfwt : integer range 0 to 1 := 0;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 2; -- trace buf size in kB (0 - no trace buffer)
pwd : integer range 0 to 2 := 0; -- power-down
svt : integer range 0 to 1 := 0; -- single-vector trapping
rstaddr : integer := 16#00000#; -- reset vector MSB address
smp : integer range 0 to 15 := 0; -- support SMP systems
fabtech : integer range 0 to NTECH := 20;
clk2x : integer := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
holdn : in std_ulogic;
ici : out icache_in_type;
ico : in icache_out_type;
dci : out dcache_in_type;
dco : in dcache_out_type;
rfi : out iregfile_in_type;
rfo : in iregfile_out_type;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
muli : out mul32_in_type;
mulo : in mul32_out_type;
divi : out div32_in_type;
divo : in div32_out_type;
fpo : in fpc_out_type;
fpi : out fpc_in_type;
cpo : in fpc_out_type;
cpi : out fpc_in_type;
tbo : in tracebuf_out_type;
tbi : out tracebuf_in_type;
sclk : in std_ulogic
);
end;
architecture rtl of iu3 is
constant ISETMSB : integer := 0;
constant DSETMSB : integer := 0;
constant RFBITS : integer range 6 to 10 := 8;
constant NWINLOG2 : integer range 1 to 5 := 3;
constant CWPOPT : boolean := true;
constant CWPMIN : std_logic_vector(2 downto 0) := "000";
constant CWPMAX : std_logic_vector(2 downto 0) := "111";
constant FPEN : boolean := (fpu /= 0);
constant CPEN : boolean := false;
constant MULEN : boolean := true;
constant MULTYPE: integer := 0;
constant DIVEN : boolean := true;
constant MACEN : boolean := false;
constant MACPIPE: boolean := false;
constant IMPL : integer := 15;
constant VER : integer := 3;
constant DBGUNIT : boolean := true;
constant TRACEBUF : boolean := true;
constant TBUFBITS : integer := 7;
constant PWRD1 : boolean := false; --(pwd = 1) and not (index /= 0);
constant PWRD2 : boolean := false; --(pwd = 2) or (index /= 0);
constant RS1OPT : boolean := true;
constant DYNRST : boolean := false;
subtype word is std_logic_vector(31 downto 0);
subtype pctype is std_logic_vector(31 downto 2);
subtype rfatype is std_logic_vector(8-1 downto 0);
subtype cwptype is std_logic_vector(3-1 downto 0);
type icdtype is array (0 to 2-1) of word;
type dcdtype is array (0 to 2-1) of word;
type dc_in_type is record
signed, enaddr, read, write, lock , dsuen : std_ulogic;
size : std_logic_vector(1 downto 0);
asi : std_logic_vector(7 downto 0);
end record;
type pipeline_ctrl_type is record
pc : pctype;
inst : word;
cnt : std_logic_vector(1 downto 0);
rd : rfatype;
tt : std_logic_vector(5 downto 0);
trap : std_ulogic;
annul : std_ulogic;
wreg : std_ulogic;
wicc : std_ulogic;
wy : std_ulogic;
ld : std_ulogic;
pv : std_ulogic;
rett : std_ulogic;
end record;
type fetch_reg_type is record
pc : pctype;
branch : std_ulogic;
end record;
type decode_reg_type is record
pc : pctype;
inst : icdtype;
cwp : cwptype;
set : std_logic_vector(0 downto 0);
mexc : std_ulogic;
cnt : std_logic_vector(1 downto 0);
pv : std_ulogic;
annul : std_ulogic;
inull : std_ulogic;
step : std_ulogic;
end record;
type regacc_reg_type is record
ctrl : pipeline_ctrl_type;
rs1 : std_logic_vector(4 downto 0);
rfa1, rfa2 : rfatype;
rsel1, rsel2 : std_logic_vector(2 downto 0);
rfe1, rfe2 : std_ulogic;
cwp : cwptype;
imm : word;
ldcheck1 : std_ulogic;
ldcheck2 : std_ulogic;
ldchkra : std_ulogic;
ldchkex : std_ulogic;
su : std_ulogic;
et : std_ulogic;
wovf : std_ulogic;
wunf : std_ulogic;
ticc : std_ulogic;
jmpl : std_ulogic;
step : std_ulogic;
mulstart : std_ulogic;
divstart : std_ulogic;
end record;
type execute_reg_type is record
ctrl : pipeline_ctrl_type;
op1 : word;
op2 : word;
aluop : std_logic_vector(2 downto 0); -- Alu operation
alusel : std_logic_vector(1 downto 0); -- Alu result select
aluadd : std_ulogic;
alucin : std_ulogic;
ldbp1, ldbp2 : std_ulogic;
invop2 : std_ulogic;
shcnt : std_logic_vector(4 downto 0); -- shift count
sari : std_ulogic; -- shift msb
shleft : std_ulogic; -- shift left/right
ymsb : std_ulogic; -- shift left/right
rd : std_logic_vector(4 downto 0);
jmpl : std_ulogic;
su : std_ulogic;
et : std_ulogic;
cwp : cwptype;
icc : std_logic_vector(3 downto 0);
mulstep: std_ulogic;
mul : std_ulogic;
mac : std_ulogic;
end record;
type memory_reg_type is record
ctrl : pipeline_ctrl_type;
result : word;
y : word;
icc : std_logic_vector(3 downto 0);
nalign : std_ulogic;
dci : dc_in_type;
werr : std_ulogic;
wcwp : std_ulogic;
irqen : std_ulogic;
irqen2 : std_ulogic;
mac : std_ulogic;
divz : std_ulogic;
su : std_ulogic;
mul : std_ulogic;
end record;
type exception_state is (run, trap, dsu1, dsu2);
type exception_reg_type is record
ctrl : pipeline_ctrl_type;
result : word;
y : word;
icc : std_logic_vector( 3 downto 0);
annul_all : std_ulogic;
data : dcdtype;
set : std_logic_vector(0 downto 0);
mexc : std_ulogic;
dci : dc_in_type;
laddr : std_logic_vector(1 downto 0);
rstate : exception_state;
npc : std_logic_vector(2 downto 0);
intack : std_ulogic;
ipend : std_ulogic;
mac : std_ulogic;
debug : std_ulogic;
nerror : std_ulogic;
end record;
type dsu_registers is record
tt : std_logic_vector(7 downto 0);
err : std_ulogic;
tbufcnt : std_logic_vector(7-1 downto 0);
asi : std_logic_vector(7 downto 0);
crdy : std_logic_vector(2 downto 1); -- diag cache access ready
end record;
type irestart_register is record
addr : pctype;
pwd : std_ulogic;
end record;
type pwd_register_type is record
pwd : std_ulogic;
error : std_ulogic;
end record;
type special_register_type is record
cwp : cwptype; -- current window pointer
icc : std_logic_vector(3 downto 0); -- integer condition codes
tt : std_logic_vector(7 downto 0); -- trap type
tba : std_logic_vector(19 downto 0); -- trap base address
wim : std_logic_vector(8-1 downto 0); -- window invalid mask
pil : std_logic_vector(3 downto 0); -- processor interrupt level
ec : std_ulogic; -- enable CP
ef : std_ulogic; -- enable FP
ps : std_ulogic; -- previous supervisor flag
s : std_ulogic; -- supervisor flag
et : std_ulogic; -- enable traps
y : word;
asr18 : word;
svt : std_ulogic; -- enable traps
dwt : std_ulogic; -- disable write error trap
end record;
type write_reg_type is record
s : special_register_type;
result : word;
wa : rfatype;
wreg : std_ulogic;
except : std_ulogic;
end record;
type registers is record
f : fetch_reg_type;
d : decode_reg_type;
a : regacc_reg_type;
e : execute_reg_type;
m : memory_reg_type;
x : exception_reg_type;
w : write_reg_type;
end record;
type exception_type is record
pri : std_ulogic;
ill : std_ulogic;
fpdis : std_ulogic;
cpdis : std_ulogic;
wovf : std_ulogic;
wunf : std_ulogic;
ticc : std_ulogic;
end record;
type watchpoint_register is record
addr : std_logic_vector(31 downto 2); -- watchpoint address
mask : std_logic_vector(31 downto 2); -- watchpoint mask
exec : std_ulogic; -- trap on instruction
load : std_ulogic; -- trap on load
store : std_ulogic; -- trap on store
end record;
type watchpoint_registers is array (0 to 3) of watchpoint_register;
constant wpr_none : watchpoint_register := (
"000000000000000000000000000000", "000000000000000000000000000000", '0', '0', '0');
function dbgexc(r : registers; dbgi : l3_debug_in_type; trap : std_ulogic; tt : std_logic_vector(7 downto 0)) return std_ulogic is
variable dmode : std_ulogic;
begin
dmode := '0';
if (not r.x.ctrl.annul and trap) = '1' then
if (((tt = "00" & TT_WATCH) and (dbgi.bwatch = '1')) or
((dbgi.bsoft = '1') and (tt = "10000001")) or
(dbgi.btrapa = '1') or
((dbgi.btrape = '1') and not ((tt(5 downto 0) = TT_PRIV) or
(tt(5 downto 0) = TT_FPDIS) or (tt(5 downto 0) = TT_WINOF) or
(tt(5 downto 0) = TT_WINUF) or (tt(5 downto 4) = "01") or (tt(7) = '1'))) or
(((not r.w.s.et) and dbgi.berror) = '1')) then
dmode := '1';
end if;
end if;
return(dmode);
end;
function dbgerr(r : registers; dbgi : l3_debug_in_type;
tt : std_logic_vector(7 downto 0))
return std_ulogic is
variable err : std_ulogic;
begin
err := not r.w.s.et;
if (((dbgi.dbreak = '1') and (tt = ("00" & TT_WATCH))) or
((dbgi.bsoft = '1') and (tt = ("10000001")))) then
err := '0';
end if;
return(err);
end;
procedure diagwr(r : in registers;
dsur : in dsu_registers;
ir : in irestart_register;
dbg : in l3_debug_in_type;
wpr : in watchpoint_registers;
s : out special_register_type;
vwpr : out watchpoint_registers;
asi : out std_logic_vector(7 downto 0);
pc, npc : out pctype;
tbufcnt : out std_logic_vector(7-1 downto 0);
wr : out std_ulogic;
addr : out std_logic_vector(9 downto 0);
data : out word;
fpcwr : out std_ulogic) is
variable i : integer range 0 to 3;
begin
s := r.w.s; pc := r.f.pc; npc := ir.addr; wr := '0';
vwpr := wpr; asi := dsur.asi; addr := "0000000000";
data := dbg.ddata;
tbufcnt := dsur.tbufcnt; fpcwr := '0';
if (dbg.dsuen and dbg.denable and dbg.dwrite) = '1' then
case dbg.daddr(23 downto 20) is
when "0001" =>
if (dbg.daddr(16) = '1') and true then -- trace buffer control reg
tbufcnt := dbg.ddata(7-1 downto 0);
end if;
when "0011" => -- IU reg file
if dbg.daddr(12) = '0' then
wr := '1';
addr := "0000000000";
addr(8-1 downto 0) := dbg.daddr(8+1 downto 2);
else -- FPC
fpcwr := '1';
end if;
when "0100" => -- IU special registers
case dbg.daddr(7 downto 6) is
when "00" => -- IU regs Y - TBUF ctrl reg
case dbg.daddr(5 downto 2) is
when "0000" => -- Y
s.y := dbg.ddata;
when "0001" => -- PSR
s.cwp := dbg.ddata(3-1 downto 0);
s.icc := dbg.ddata(23 downto 20);
s.ec := dbg.ddata(13);
if FPEN then s.ef := dbg.ddata(12); end if;
s.pil := dbg.ddata(11 downto 8);
s.s := dbg.ddata(7);
s.ps := dbg.ddata(6);
s.et := dbg.ddata(5);
when "0010" => -- WIM
s.wim := dbg.ddata(8-1 downto 0);
when "0011" => -- TBR
s.tba := dbg.ddata(31 downto 12);
s.tt := dbg.ddata(11 downto 4);
when "0100" => -- PC
pc := dbg.ddata(31 downto 2);
when "0101" => -- NPC
npc := dbg.ddata(31 downto 2);
when "0110" => --FSR
fpcwr := '1';
when "0111" => --CFSR
when "1001" => -- ASI reg
asi := dbg.ddata(7 downto 0);
--when "1001" => -- TBUF ctrl reg
-- tbufcnt := dbg.ddata(7-1 downto 0);
when others =>
end case;
when "01" => -- ASR16 - ASR31
case dbg.daddr(5 downto 2) is
when "0001" => -- %ASR17
s.dwt := dbg.ddata(14);
s.svt := dbg.ddata(13);
when "0010" => -- %ASR18
if false then s.asr18 := dbg.ddata; end if;
when "1000" => -- %ASR24 - %ASR31
vwpr(0).addr := dbg.ddata(31 downto 2);
vwpr(0).exec := dbg.ddata(0);
when "1001" =>
vwpr(0).mask := dbg.ddata(31 downto 2);
vwpr(0).load := dbg.ddata(1);
vwpr(0).store := dbg.ddata(0);
when "1010" =>
vwpr(1).addr := dbg.ddata(31 downto 2);
vwpr(1).exec := dbg.ddata(0);
when "1011" =>
vwpr(1).mask := dbg.ddata(31 downto 2);
vwpr(1).load := dbg.ddata(1);
vwpr(1).store := dbg.ddata(0);
when "1100" =>
vwpr(2).addr := dbg.ddata(31 downto 2);
vwpr(2).exec := dbg.ddata(0);
when "1101" =>
vwpr(2).mask := dbg.ddata(31 downto 2);
vwpr(2).load := dbg.ddata(1);
vwpr(2).store := dbg.ddata(0);
when "1110" =>
vwpr(3).addr := dbg.ddata(31 downto 2);
vwpr(3).exec := dbg.ddata(0);
when "1111" => --
vwpr(3).mask := dbg.ddata(31 downto 2);
vwpr(3).load := dbg.ddata(1);
vwpr(3).store := dbg.ddata(0);
when others => --
end case;
-- disabled due to bug in XST
-- i := conv_integer(dbg.daddr(4 downto 3));
-- if dbg.daddr(2) = '0' then
-- vwpr(i).addr := dbg.ddata(31 downto 2);
-- vwpr(i).exec := dbg.ddata(0);
-- else
-- vwpr(i).mask := dbg.ddata(31 downto 2);
-- vwpr(i).load := dbg.ddata(1);
-- vwpr(i).store := dbg.ddata(0);
-- end if;
when others =>
end case;
when others =>
end case;
end if;
end;
function asr17_gen ( r : in registers) return word is
variable asr17 : word;
variable fpu2 : integer range 0 to 3;
begin
asr17 := "00000000000000000000000000000000";
asr17(31 downto 28) := conv_std_logic_vector(index, 4);
if (clk2x > 8) then
asr17(16 downto 15) := conv_std_logic_vector(clk2x-8, 2);
asr17(17) := '1';
elsif (clk2x > 0) then
asr17(16 downto 15) := conv_std_logic_vector(clk2x, 2);
end if;
asr17(14) := r.w.s.dwt;
if svt = 1 then asr17(13) := r.w.s.svt; end if;
if lddel = 2 then asr17(12) := '1'; end if;
if (fpu > 0) and (fpu < 8) then fpu2 := 1;
elsif (fpu >= 8) and (fpu < 15) then fpu2 := 3;
elsif fpu = 15 then fpu2 := 2;
else fpu2 := 0; end if;
asr17(11 downto 10) := conv_std_logic_vector(fpu2, 2);
if mac = 1 then asr17(9) := '1'; end if;
if 2 /= 0 then asr17(8) := '1'; end if;
asr17(7 downto 5) := conv_std_logic_vector(nwp, 3);
asr17(4 downto 0) := conv_std_logic_vector(8-1, 5);
return(asr17);
end;
procedure diagread(dbgi : in l3_debug_in_type;
r : in registers;
dsur : in dsu_registers;
ir : in irestart_register;
wpr : in watchpoint_registers;
dco : in dcache_out_type;
tbufo : in tracebuf_out_type;
data : out word) is
variable cwp : std_logic_vector(4 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable i : integer range 0 to 3;
begin
data := "00000000000000000000000000000000"; cwp := "00000";
cwp(3-1 downto 0) := r.w.s.cwp;
case dbgi.daddr(22 downto 20) is
when "001" => -- trace buffer
if true then
if dbgi.daddr(16) = '1' then -- trace buffer control reg
if true then data(7-1 downto 0) := dsur.tbufcnt; end if;
else
case dbgi.daddr(3 downto 2) is
when "00" => data := tbufo.data(127 downto 96);
when "01" => data := tbufo.data(95 downto 64);
when "10" => data := tbufo.data(63 downto 32);
when others => data := tbufo.data(31 downto 0);
end case;
end if;
end if;
when "011" => -- IU reg file
if dbgi.daddr(12) = '0' then
data := rfo.data1(31 downto 0);
if (dbgi.daddr(11) = '1') and (is_fpga(fabtech) = 0) then
data := rfo.data2(31 downto 0);
end if;
else data := fpo.dbg.data; end if;
when "100" => -- IU regs
case dbgi.daddr(7 downto 6) is
when "00" => -- IU regs Y - TBUF ctrl reg
case dbgi.daddr(5 downto 2) is
when "0000" =>
data := r.w.s.y;
when "0001" =>
data := conv_std_logic_vector(15, 4) & conv_std_logic_vector(3, 4) &
r.w.s.icc & "000000" & r.w.s.ec & r.w.s.ef & r.w.s.pil &
r.w.s.s & r.w.s.ps & r.w.s.et & cwp;
when "0010" =>
data(8-1 downto 0) := r.w.s.wim;
when "0011" =>
data := r.w.s.tba & r.w.s.tt & "0000";
when "0100" =>
data(31 downto 2) := r.f.pc;
when "0101" =>
data(31 downto 2) := ir.addr;
when "0110" => -- FSR
data := fpo.dbg.data;
when "0111" => -- CPSR
when "1000" => -- TT reg
data(12 downto 4) := dsur.err & dsur.tt;
when "1001" => -- ASI reg
data(7 downto 0) := dsur.asi;
when others =>
end case;
when "01" =>
if dbgi.daddr(5) = '0' then -- %ASR17
if dbgi.daddr(4 downto 2) = "001" then -- %ASR17
data := asr17_gen(r);
elsif false and dbgi.daddr(4 downto 2) = "010" then -- %ASR18
data := r.w.s.asr18;
end if;
else -- %ASR24 - %ASR31
i := conv_integer(dbgi.daddr(4 downto 3)); --
if dbgi.daddr(2) = '0' then
data(31 downto 2) := wpr(i).addr;
data(0) := wpr(i).exec;
else
data(31 downto 2) := wpr(i).mask;
data(1) := wpr(i).load;
data(0) := wpr(i).store;
end if;
end if;
when others =>
end case;
when "111" =>
data := r.x.data(conv_integer(r.x.set));
when others =>
end case;
end;
procedure itrace(r : in registers;
dsur : in dsu_registers;
vdsu : in dsu_registers;
res : in word;
exc : in std_ulogic;
dbgi : in l3_debug_in_type;
error : in std_ulogic;
trap : in std_ulogic;
tbufcnt : out std_logic_vector(7-1 downto 0);
di : out tracebuf_in_type) is
variable meminst : std_ulogic;
begin
di.addr := (others => '0'); di.data := (others => '0');
di.enable := '0'; di.write := (others => '0');
tbufcnt := vdsu.tbufcnt;
meminst := r.x.ctrl.inst(31) and r.x.ctrl.inst(30);
if true then
di.addr(7-1 downto 0) := dsur.tbufcnt;
di.data(127) := '0';
di.data(126) := not r.x.ctrl.pv;
di.data(125 downto 96) := dbgi.timer(29 downto 0);
di.data(95 downto 64) := res;
di.data(63 downto 34) := r.x.ctrl.pc(31 downto 2);
di.data(33) := trap;
di.data(32) := error;
di.data(31 downto 0) := r.x.ctrl.inst;
if (dbgi.tenable = '0') or (r.x.rstate = dsu2) then
if ((dbgi.dsuen and dbgi.denable) = '1') and (dbgi.daddr(23 downto 20) & dbgi.daddr(16) = "00010") then
di.enable := '1';
di.addr(7-1 downto 0) := dbgi.daddr(7-1+4 downto 4);
if dbgi.dwrite = '1' then
case dbgi.daddr(3 downto 2) is
when "00" => di.write(3) := '1';
when "01" => di.write(2) := '1';
when "10" => di.write(1) := '1';
when others => di.write(0) := '1';
end case;
di.data := dbgi.ddata & dbgi.ddata & dbgi.ddata & dbgi.ddata;
end if;
end if;
elsif (not r.x.ctrl.annul and (r.x.ctrl.pv or meminst) and not r.x.debug) = '1' then
di.enable := '1'; di.write := (others => '1');
tbufcnt := dsur.tbufcnt + 1;
end if;
di.diag := dco.testen & "000";
if dco.scanen = '1' then di.enable := '0'; end if;
end if;
end;
procedure dbg_cache(holdn : in std_ulogic;
dbgi : in l3_debug_in_type;
r : in registers;
dsur : in dsu_registers;
mresult : in word;
dci : in dc_in_type;
mresult2 : out word;
dci2 : out dc_in_type
) is
begin
mresult2 := mresult; dci2 := dci; dci2.dsuen := '0';
if true then
if r.x.rstate = dsu2 then
dci2.asi := dsur.asi;
if (dbgi.daddr(22 downto 20) = "111") and (dbgi.dsuen = '1') then
dci2.dsuen := (dbgi.denable or r.m.dci.dsuen) and not dsur.crdy(2);
dci2.enaddr := dbgi.denable;
dci2.size := "10"; dci2.read := '1'; dci2.write := '0';
if (dbgi.denable and not r.m.dci.enaddr) = '1' then
mresult2 := (others => '0'); mresult2(19 downto 2) := dbgi.daddr(19 downto 2);
else
mresult2 := dbgi.ddata;
end if;
if dbgi.dwrite = '1' then
dci2.read := '0'; dci2.write := '1';
end if;
end if;
end if;
end if;
end;
procedure fpexack(r : in registers; fpexc : out std_ulogic) is
begin
fpexc := '0';
if FPEN then
if r.x.ctrl.tt = TT_FPEXC then fpexc := '1'; end if;
end if;
end;
procedure diagrdy(denable : in std_ulogic;
dsur : in dsu_registers;
dci : in dc_in_type;
mds : in std_ulogic;
ico : in icache_out_type;
crdy : out std_logic_vector(2 downto 1)) is
begin
crdy := dsur.crdy(1) & '0';
if dci.dsuen = '1' then
case dsur.asi(4 downto 0) is
when ASI_ITAG | ASI_IDATA | ASI_UINST | ASI_SINST =>
crdy(2) := ico.diagrdy and not dsur.crdy(2);
when ASI_DTAG | ASI_MMUSNOOP_DTAG | ASI_DDATA | ASI_UDATA | ASI_SDATA =>
crdy(1) := not denable and dci.enaddr and not dsur.crdy(1);
when others =>
crdy(2) := dci.enaddr and denable;
end case;
end if;
end;
signal r, rin : registers;
signal wpr, wprin : watchpoint_registers;
signal dsur, dsuin : dsu_registers;
signal ir, irin : irestart_register;
signal rp, rpin : pwd_register_type;
-- execute stage operations
constant EXE_AND : std_logic_vector(2 downto 0) := "000";
constant EXE_XOR : std_logic_vector(2 downto 0) := "001"; -- must be equal to EXE_PASS2
constant EXE_OR : std_logic_vector(2 downto 0) := "010";
constant EXE_XNOR : std_logic_vector(2 downto 0) := "011";
constant EXE_ANDN : std_logic_vector(2 downto 0) := "100";
constant EXE_ORN : std_logic_vector(2 downto 0) := "101";
constant EXE_DIV : std_logic_vector(2 downto 0) := "110";
constant EXE_PASS1 : std_logic_vector(2 downto 0) := "000";
constant EXE_PASS2 : std_logic_vector(2 downto 0) := "001";
constant EXE_STB : std_logic_vector(2 downto 0) := "010";
constant EXE_STH : std_logic_vector(2 downto 0) := "011";
constant EXE_ONES : std_logic_vector(2 downto 0) := "100";
constant EXE_RDY : std_logic_vector(2 downto 0) := "101";
constant EXE_SPR : std_logic_vector(2 downto 0) := "110";
constant EXE_LINK : std_logic_vector(2 downto 0) := "111";
constant EXE_SLL : std_logic_vector(2 downto 0) := "001";
constant EXE_SRL : std_logic_vector(2 downto 0) := "010";
constant EXE_SRA : std_logic_vector(2 downto 0) := "100";
constant EXE_NOP : std_logic_vector(2 downto 0) := "000";
-- EXE result select
constant EXE_RES_ADD : std_logic_vector(1 downto 0) := "00";
constant EXE_RES_SHIFT : std_logic_vector(1 downto 0) := "01";
constant EXE_RES_LOGIC : std_logic_vector(1 downto 0) := "10";
constant EXE_RES_MISC : std_logic_vector(1 downto 0) := "11";
-- Load types
constant SZBYTE : std_logic_vector(1 downto 0) := "00";
constant SZHALF : std_logic_vector(1 downto 0) := "01";
constant SZWORD : std_logic_vector(1 downto 0) := "10";
constant SZDBL : std_logic_vector(1 downto 0) := "11";
-- calculate register file address
procedure regaddr(cwp : std_logic_vector; reg : std_logic_vector(4 downto 0);
rao : out rfatype) is
variable ra : rfatype;
constant globals : std_logic_vector(8-5 downto 0) :=
conv_std_logic_vector(8, 8-4);
begin
ra := (others => '0'); ra(4 downto 0) := reg;
if reg(4 downto 3) = "00" then ra(8 -1 downto 4) := globals;
else
ra(3+3 downto 4) := cwp + ra(4);
if ra(8-1 downto 4) = globals then
ra(8-1 downto 4) := (others => '0');
end if;
end if;
rao := ra;
end;
-- branch adder
function branch_address(inst : word; pc : pctype) return std_logic_vector is
variable baddr, caddr, tmp : pctype;
begin
caddr := (others => '0'); caddr(31 downto 2) := inst(29 downto 0);
caddr(31 downto 2) := caddr(31 downto 2) + pc(31 downto 2);
baddr := (others => '0'); baddr(31 downto 24) := (others => inst(21));
baddr(23 downto 2) := inst(21 downto 0);
baddr(31 downto 2) := baddr(31 downto 2) + pc(31 downto 2);
if inst(30) = '1' then tmp := caddr; else tmp := baddr; end if;
return(tmp);
end;
-- evaluate branch condition
function branch_true(icc : std_logic_vector(3 downto 0); inst : word)
return std_ulogic is
variable n, z, v, c, branch : std_ulogic;
begin
n := icc(3); z := icc(2); v := icc(1); c := icc(0);
case inst(27 downto 25) is
when "000" => branch := inst(28) xor '0'; -- bn, ba
when "001" => branch := inst(28) xor z; -- be, bne
when "010" => branch := inst(28) xor (z or (n xor v)); -- ble, bg
when "011" => branch := inst(28) xor (n xor v); -- bl, bge
when "100" => branch := inst(28) xor (c or z); -- bleu, bgu
when "101" => branch := inst(28) xor c; -- bcs, bcc
when "110" => branch := inst(28) xor n; -- bneg, bpos
when others => branch := inst(28) xor v; -- bvs, bvc
end case;
return(branch);
end;
-- detect RETT instruction in the pipeline and set the local psr.su and psr.et
procedure su_et_select(r : in registers; xc_ps, xc_s, xc_et : in std_ulogic;
su, et : out std_ulogic) is
begin
if ((r.a.ctrl.rett or r.e.ctrl.rett or r.m.ctrl.rett or r.x.ctrl.rett) = '1')
and (r.x.annul_all = '0')
then su := xc_ps; et := '1';
else su := xc_s; et := xc_et; end if;
end;
-- detect watchpoint trap
function wphit(r : registers; wpr : watchpoint_registers; debug : l3_debug_in_type)
return std_ulogic is
variable exc : std_ulogic;
begin
exc := '0';
for i in 1 to NWP loop
if ((wpr(i-1).exec and r.a.ctrl.pv and not r.a.ctrl.annul) = '1') then
if (((wpr(i-1).addr xor r.a.ctrl.pc(31 downto 2)) and wpr(i-1).mask) = "000000000000000000000000000000") then
exc := '1';
end if;
end if;
end loop;
if true then
if (debug.dsuen and not r.a.ctrl.annul) = '1' then
exc := exc or (r.a.ctrl.pv and ((debug.dbreak and debug.bwatch) or r.a.step));
end if;
end if;
return(exc);
end;
-- 32-bit shifter
function shift3(r : registers; aluin1, aluin2 : word) return word is
variable shiftin : unsigned(63 downto 0);
variable shiftout : unsigned(63 downto 0);
variable cnt : natural range 0 to 31;
begin
cnt := conv_integer(r.e.shcnt);
if r.e.shleft = '1' then
shiftin(30 downto 0) := (others => '0');
shiftin(63 downto 31) := '0' & unsigned(aluin1);
else
shiftin(63 downto 32) := (others => r.e.sari);
shiftin(31 downto 0) := unsigned(aluin1);
end if;
shiftout := SHIFT_RIGHT(shiftin, cnt);
return(std_logic_vector(shiftout(31 downto 0)));
end;
function shift2(r : registers; aluin1, aluin2 : word) return word is
variable ushiftin : unsigned(31 downto 0);
variable sshiftin : signed(32 downto 0);
variable cnt : natural range 0 to 31;
variable resleft, resright : word;
begin
cnt := conv_integer(r.e.shcnt);
ushiftin := unsigned(aluin1);
sshiftin := signed('0' & aluin1);
if r.e.shleft = '1' then
resleft := std_logic_vector(SHIFT_LEFT(ushiftin, cnt));
return(resleft);
else
if r.e.sari = '1' then sshiftin(32) := aluin1(31); end if;
sshiftin := SHIFT_RIGHT(sshiftin, cnt);
resright := std_logic_vector(sshiftin(31 downto 0));
return(resright);
-- else
-- ushiftin := SHIFT_RIGHT(ushiftin, cnt);
-- return(std_logic_vector(ushiftin));
-- end if;
end if;
end;
function shift(r : registers; aluin1, aluin2 : word;
shiftcnt : std_logic_vector(4 downto 0); sari : std_ulogic ) return word is
variable shiftin : std_logic_vector(63 downto 0);
begin
shiftin := "00000000000000000000000000000000" & aluin1;
if r.e.shleft = '1' then
shiftin(31 downto 0) := "00000000000000000000000000000000"; shiftin(63 downto 31) := '0' & aluin1;
else shiftin(63 downto 32) := (others => sari); end if;
if shiftcnt (4) = '1' then shiftin(47 downto 0) := shiftin(63 downto 16); end if;
if shiftcnt (3) = '1' then shiftin(39 downto 0) := shiftin(47 downto 8); end if;
if shiftcnt (2) = '1' then shiftin(35 downto 0) := shiftin(39 downto 4); end if;
if shiftcnt (1) = '1' then shiftin(33 downto 0) := shiftin(35 downto 2); end if;
if shiftcnt (0) = '1' then shiftin(31 downto 0) := shiftin(32 downto 1); end if;
return(shiftin(31 downto 0));
end;
-- Check for illegal and privileged instructions
procedure exception_detect(r : registers; wpr : watchpoint_registers; dbgi : l3_debug_in_type;
trapin : in std_ulogic; ttin : in std_logic_vector(5 downto 0);
trap : out std_ulogic; tt : out std_logic_vector(5 downto 0)) is
variable illegal_inst, privileged_inst : std_ulogic;
variable cp_disabled, fp_disabled, fpop : std_ulogic;
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable inst : word;
variable wph : std_ulogic;
begin
inst := r.a.ctrl.inst; trap := trapin; tt := ttin;
if r.a.ctrl.annul = '0' then
op := inst(31 downto 30); op2 := inst(24 downto 22);
op3 := inst(24 downto 19); rd := inst(29 downto 25);
illegal_inst := '0'; privileged_inst := '0'; cp_disabled := '0';
fp_disabled := '0'; fpop := '0';
case op is
when CALL => null;
when FMT2 =>
case op2 is
when SETHI | BICC => null;
when FBFCC =>
if FPEN then fp_disabled := not r.w.s.ef; else fp_disabled := '1'; end if;
when CBCCC =>
if (not false) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when others => illegal_inst := '1';
end case;
when FMT3 =>
case op3 is
when IAND | ANDCC | ANDN | ANDNCC | IOR | ORCC | ORN | ORNCC | IXOR |
XORCC | IXNOR | XNORCC | ISLL | ISRL | ISRA | MULSCC | IADD | ADDX |
ADDCC | ADDXCC | ISUB | SUBX | SUBCC | SUBXCC | FLUSH | JMPL | TICC |
SAVE | RESTORE | RDY => null;
when TADDCC | TADDCCTV | TSUBCC | TSUBCCTV =>
if notag = 1 then illegal_inst := '1'; end if;
when UMAC | SMAC =>
if not false then illegal_inst := '1'; end if;
when UMUL | SMUL | UMULCC | SMULCC =>
if not true then illegal_inst := '1'; end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if not true then illegal_inst := '1'; end if;
when RETT => illegal_inst := r.a.et; privileged_inst := not r.a.su;
when RDPSR | RDTBR | RDWIM => privileged_inst := not r.a.su;
when WRY => null;
when WRPSR =>
privileged_inst := not r.a.su;
when WRWIM | WRTBR => privileged_inst := not r.a.su;
when FPOP1 | FPOP2 =>
if FPEN then fp_disabled := not r.w.s.ef; fpop := '1';
else fp_disabled := '1'; fpop := '0'; end if;
when CPOP1 | CPOP2 =>
if (not false) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when others => illegal_inst := '1';
end case;
when others => -- LDST
case op3 is
when LDD | ISTD => illegal_inst := rd(0); -- trap if odd destination register
when LD | LDUB | LDSTUB | LDUH | LDSB | LDSH | ST | STB | STH | SWAP =>
null;
when LDDA | STDA =>
illegal_inst := inst(13) or rd(0); privileged_inst := not r.a.su;
when LDA | LDUBA| LDSTUBA | LDUHA | LDSBA | LDSHA | STA | STBA | STHA |
SWAPA =>
illegal_inst := inst(13); privileged_inst := not r.a.su;
when LDDF | STDF | LDF | LDFSR | STF | STFSR =>
if FPEN then fp_disabled := not r.w.s.ef;
else fp_disabled := '1'; end if;
when STDFQ =>
privileged_inst := not r.a.su;
if (not FPEN) or (r.w.s.ef = '0') then fp_disabled := '1'; end if;
when STDCQ =>
privileged_inst := not r.a.su;
if (not false) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when LDC | LDCSR | LDDC | STC | STCSR | STDC =>
if (not false) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when others => illegal_inst := '1';
end case;
end case;
wph := wphit(r, wpr, dbgi);
trap := '1';
if r.a.ctrl.trap = '1' then tt := TT_IAEX;
elsif privileged_inst = '1' then tt := TT_PRIV;
elsif illegal_inst = '1' then tt := TT_IINST;
elsif fp_disabled = '1' then tt := TT_FPDIS;
elsif cp_disabled = '1' then tt := TT_CPDIS;
elsif wph = '1' then tt := TT_WATCH;
elsif r.a.wovf= '1' then tt := TT_WINOF;
elsif r.a.wunf= '1' then tt := TT_WINUF;
elsif r.a.ticc= '1' then tt := TT_TICC;
else trap := '0'; tt:= (others => '0'); end if;
end if;
end;
-- instructions that write the condition codes (psr.icc)
procedure wicc_y_gen(inst : word; wicc, wy : out std_ulogic) is
begin
wicc := '0'; wy := '0';
if inst(31 downto 30) = FMT3 then
case inst(24 downto 19) is
when SUBCC | TSUBCC | TSUBCCTV | ADDCC | ANDCC | ORCC | XORCC | ANDNCC |
ORNCC | XNORCC | TADDCC | TADDCCTV | ADDXCC | SUBXCC | WRPSR =>
wicc := '1';
when WRY =>
if r.d.inst(conv_integer(r.d.set))(29 downto 25) = "00000" then wy := '1'; end if;
when MULSCC =>
wicc := '1'; wy := '1';
when UMAC | SMAC =>
if false then wy := '1'; end if;
when UMULCC | SMULCC =>
if true and (((mulo.nready = '1') and (r.d.cnt /= "00")) or (0 /= 0)) then
wicc := '1'; wy := '1';
end if;
when UMUL | SMUL =>
if true and (((mulo.nready = '1') and (r.d.cnt /= "00")) or (0 /= 0)) then
wy := '1';
end if;
when UDIVCC | SDIVCC =>
if true and (divo.nready = '1') and (r.d.cnt /= "00") then
wicc := '1';
end if;
when others =>
end case;
end if;
end;
-- select cwp
procedure cwp_gen(r, v : registers; annul, wcwp : std_ulogic; ncwp : cwptype;
cwp : out cwptype) is
begin
if (r.x.rstate = trap) or (r.x.rstate = dsu2) or (rstn = '0') then cwp := v.w.s.cwp;
elsif (wcwp = '1') and (annul = '0') then cwp := ncwp;
elsif r.m.wcwp = '1' then cwp := r.m.result(3-1 downto 0);
else cwp := r.d.cwp; end if;
end;
-- generate wcwp in ex stage
procedure cwp_ex(r : in registers; wcwp : out std_ulogic) is
begin
if (r.e.ctrl.inst(31 downto 30) = FMT3) and
(r.e.ctrl.inst(24 downto 19) = WRPSR)
then wcwp := not r.e.ctrl.annul; else wcwp := '0'; end if;
end;
-- generate next cwp & window under- and overflow traps
procedure cwp_ctrl(r : in registers; xc_wim : in std_logic_vector(8-1 downto 0);
inst : word; de_cwp : out cwptype; wovf_exc, wunf_exc, wcwp : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable wim : word;
variable ncwp : cwptype;
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
wovf_exc := '0'; wunf_exc := '0'; wim := (others => '0');
wim(8-1 downto 0) := xc_wim; ncwp := r.d.cwp; wcwp := '0';
if (op = FMT3) and ((op3 = RETT) or (op3 = RESTORE) or (op3 = SAVE)) then
wcwp := '1';
if (op3 = SAVE) then
if (not true) and (r.d.cwp = "000") then ncwp := "111";
else ncwp := r.d.cwp - 1 ; end if;
else
if (not true) and (r.d.cwp = "111") then ncwp := "000";
else ncwp := r.d.cwp + 1; end if;
end if;
if wim(conv_integer(ncwp)) = '1' then
if op3 = SAVE then wovf_exc := '1'; else wunf_exc := '1'; end if;
end if;
end if;
de_cwp := ncwp;
end;
-- generate register read address 1
procedure rs1_gen(r : registers; inst : word; rs1 : out std_logic_vector(4 downto 0);
rs1mod : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
rs1 := inst(18 downto 14); rs1mod := '0';
if (op = LDST) then
if ((r.d.cnt = "01") and ((op3(2) and not op3(3)) = '1')) or
(r.d.cnt = "10")
then rs1mod := '1'; rs1 := inst(29 downto 25); end if;
if ((r.d.cnt = "10") and (op3(3 downto 0) = "0111")) then
rs1(0) := '1';
end if;
end if;
end;
-- load/icc interlock detection
procedure lock_gen(r : registers; rs2, rd : std_logic_vector(4 downto 0);
rfa1, rfa2, rfrd : rfatype; inst : word; fpc_lock, mulinsn, divinsn : std_ulogic;
lldcheck1, lldcheck2, lldlock, lldchkra, lldchkex : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable cond : std_logic_vector(3 downto 0);
variable rs1 : std_logic_vector(4 downto 0);
variable i, ldcheck1, ldcheck2, ldchkra, ldchkex, ldcheck3 : std_ulogic;
variable ldlock, icc_check, bicc_hold, chkmul, y_check : std_ulogic;
variable lddlock : boolean;
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
op2 := inst(24 downto 22); cond := inst(28 downto 25);
rs1 := inst(18 downto 14); lddlock := false; i := inst(13);
ldcheck1 := '0'; ldcheck2 := '0'; ldcheck3 := '0'; ldlock := '0';
ldchkra := '1'; ldchkex := '1'; icc_check := '0'; bicc_hold := '0';
y_check := '0';
if (r.d.annul = '0') then
case op is
when FMT2 =>
if (op2 = BICC) and (cond(2 downto 0) /= "000") then
icc_check := '1';
end if;
when FMT3 =>
ldcheck1 := '1'; ldcheck2 := not i;
case op3 is
when TICC =>
if (cond(2 downto 0) /= "000") then icc_check := '1'; end if;
when RDY =>
ldcheck1 := '0'; ldcheck2 := '0';
if false then y_check := '1'; end if;
when RDWIM | RDTBR =>
ldcheck1 := '0'; ldcheck2 := '0';
when RDPSR =>
ldcheck1 := '0'; ldcheck2 := '0'; icc_check := '1';
if true then icc_check := '1'; end if;
-- when ADDX | ADDXCC | SUBX | SUBXCC =>
-- if true then icc_check := '1'; end if;
when SDIV | SDIVCC | UDIV | UDIVCC =>
if true then y_check := '1'; end if;
when FPOP1 | FPOP2 => ldcheck1:= '0'; ldcheck2 := '0';
when others =>
end case;
when LDST =>
ldcheck1 := '1'; ldchkra := '0';
case r.d.cnt is
when "00" =>
if (lddel = 2) and (op3(2) = '1') then ldcheck3 := '1'; end if;
ldcheck2 := not i; ldchkra := '1';
when "01" => ldcheck2 := not i;
when others => ldchkex := '0';
end case;
if (op3(2 downto 0) = "011") then lddlock := true; end if;
when others => null;
end case;
end if;
if true or true then
chkmul := mulinsn;
bicc_hold := bicc_hold or (icc_check and r.m.ctrl.wicc and (r.m.ctrl.cnt(0) or r.m.mul));
else chkmul := '0'; end if;
if true then
bicc_hold := bicc_hold or (y_check and (r.a.ctrl.wy or r.e.ctrl.wy));
chkmul := chkmul or divinsn;
end if;
bicc_hold := bicc_hold or (icc_check and (r.a.ctrl.wicc or r.e.ctrl.wicc));
if (((r.a.ctrl.ld or chkmul) and r.a.ctrl.wreg and ldchkra) = '1') and
(((ldcheck1 = '1') and (r.a.ctrl.rd = rfa1)) or
((ldcheck2 = '1') and (r.a.ctrl.rd = rfa2)) or
((ldcheck3 = '1') and (r.a.ctrl.rd = rfrd)))
then ldlock := '1'; end if;
if (((r.e.ctrl.ld or r.e.mac) and r.e.ctrl.wreg and ldchkex) = '1') and
((lddel = 2) or (false and (r.e.mac = '1')) or ((0 = 3) and (r.e.mul = '1'))) and
(((ldcheck1 = '1') and (r.e.ctrl.rd = rfa1)) or
((ldcheck2 = '1') and (r.e.ctrl.rd = rfa2)))
then ldlock := '1'; end if;
ldlock := ldlock or bicc_hold or fpc_lock;
lldcheck1 := ldcheck1; lldcheck2:= ldcheck2; lldlock := ldlock;
lldchkra := ldchkra; lldchkex := ldchkex;
end;
procedure fpbranch(inst : in word; fcc : in std_logic_vector(1 downto 0);
branch : out std_ulogic) is
variable cond : std_logic_vector(3 downto 0);
variable fbres : std_ulogic;
begin
cond := inst(28 downto 25);
case cond(2 downto 0) is
when "000" => fbres := '0'; -- fba, fbn
when "001" => fbres := fcc(1) or fcc(0);
when "010" => fbres := fcc(1) xor fcc(0);
when "011" => fbres := fcc(0);
when "100" => fbres := (not fcc(1)) and fcc(0);
when "101" => fbres := fcc(1);
when "110" => fbres := fcc(1) and not fcc(0);
when others => fbres := fcc(1) and fcc(0);
end case;
branch := cond(3) xor fbres;
end;
-- PC generation
procedure ic_ctrl(r : registers; inst : word; annul_all, ldlock, branch_true,
fbranch_true, cbranch_true, fccv, cccv : in std_ulogic;
cnt : out std_logic_vector(1 downto 0);
de_pc : out pctype; de_branch, ctrl_annul, de_annul, jmpl_inst, inull,
de_pv, ctrl_pv, de_hold_pc, ticc_exception, rett_inst, mulstart,
divstart : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable cond : std_logic_vector(3 downto 0);
variable hold_pc, annul_current, annul_next, branch, annul, pv : std_ulogic;
variable de_jmpl : std_ulogic;
begin
branch := '0'; annul_next := '0'; annul_current := '0'; pv := '1';
hold_pc := '0'; ticc_exception := '0'; rett_inst := '0';
op := inst(31 downto 30); op3 := inst(24 downto 19);
op2 := inst(24 downto 22); cond := inst(28 downto 25);
annul := inst(29); de_jmpl := '0'; cnt := "00";
mulstart := '0'; divstart := '0';
if r.d.annul = '0' then
case inst(31 downto 30) is
when CALL =>
branch := '1';
if r.d.inull = '1' then
hold_pc := '1'; annul_current := '1';
end if;
when FMT2 =>
if (op2 = BICC) or (FPEN and (op2 = FBFCC)) or (false and (op2 = CBCCC)) then
if (FPEN and (op2 = FBFCC)) then
branch := fbranch_true;
if fccv /= '1' then hold_pc := '1'; annul_current := '1'; end if;
elsif (false and (op2 = CBCCC)) then
branch := cbranch_true;
if cccv /= '1' then hold_pc := '1'; annul_current := '1'; end if;
else branch := branch_true; end if;
if hold_pc = '0' then
if (branch = '1') then
if (cond = BA) and (annul = '1') then annul_next := '1'; end if;
else annul_next := annul; end if;
if r.d.inull = '1' then -- contention with JMPL
hold_pc := '1'; annul_current := '1'; annul_next := '0';
end if;
end if;
end if;
when FMT3 =>
case op3 is
when UMUL | SMUL | UMULCC | SMULCC =>
if true and (0 /= 0) then mulstart := '1'; end if;
if true and (0 = 0) then
case r.d.cnt is
when "00" =>
cnt := "01"; hold_pc := '1'; pv := '0'; mulstart := '1';
when "01" =>
if mulo.nready = '1' then cnt := "00";
else cnt := "01"; pv := '0'; hold_pc := '1'; end if;
when others => null;
end case;
end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if true then
case r.d.cnt is
when "00" =>
cnt := "01"; hold_pc := '1'; pv := '0';
divstart := '1';
when "01" =>
if divo.nready = '1' then cnt := "00";
else cnt := "01"; pv := '0'; hold_pc := '1'; end if;
when others => null;
end case;
end if;
when TICC =>
if branch_true = '1' then ticc_exception := '1'; end if;
when RETT =>
rett_inst := '1'; --su := sregs.ps;
when JMPL =>
de_jmpl := '1';
when WRY =>
if false then
if inst(29 downto 25) = "10011" then -- %ASR19
case r.d.cnt is
when "00" =>
pv := '0'; cnt := "00"; hold_pc := '1';
if r.x.ipend = '1' then cnt := "01"; end if;
when "01" =>
cnt := "00";
when others =>
end case;
end if;
end if;
when others => null;
end case;
when others => -- LDST
case r.d.cnt is
when "00" =>
if (op3(2) = '1') or (op3(1 downto 0) = "11") then -- ST/LDST/SWAP/LDD
cnt := "01"; hold_pc := '1'; pv := '0';
end if;
when "01" =>
if (op3(2 downto 0) = "111") or (op3(3 downto 0) = "1101") or
((false or FPEN) and ((op3(5) & op3(2 downto 0)) = "1110"))
then -- LDD/STD/LDSTUB/SWAP
cnt := "10"; pv := '0'; hold_pc := '1';
else
cnt := "00";
end if;
when "10" =>
cnt := "00";
when others => null;
end case;
end case;
end if;
if ldlock = '1' then
cnt := r.d.cnt; annul_next := '0'; pv := '1';
end if;
hold_pc := (hold_pc or ldlock) and not annul_all;
if hold_pc = '1' then de_pc := r.d.pc; else de_pc := r.f.pc; end if;
annul_current := (annul_current or ldlock or annul_all);
ctrl_annul := r.d.annul or annul_all or annul_current;
pv := pv and not ((r.d.inull and not hold_pc) or annul_all);
jmpl_inst := de_jmpl and not annul_current;
annul_next := (r.d.inull and not hold_pc) or annul_next or annul_all;
if (annul_next = '1') or (rstn = '0') then
cnt := (others => '0');
end if;
de_hold_pc := hold_pc; de_branch := branch; de_annul := annul_next;
de_pv := pv; ctrl_pv := r.d.pv and
not ((r.d.annul and not r.d.pv) or annul_all or annul_current);
inull := (not rstn) or r.d.inull or hold_pc or annul_all;
end;
-- register write address generation
procedure rd_gen(r : registers; inst : word; wreg, ld : out std_ulogic;
rdo : out std_logic_vector(4 downto 0)) is
variable write_reg : std_ulogic;
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
begin
op := inst(31 downto 30);
op2 := inst(24 downto 22);
op3 := inst(24 downto 19);
write_reg := '0'; rd := inst(29 downto 25); ld := '0';
case op is
when CALL =>
write_reg := '1'; rd := "01111"; -- CALL saves PC in r[15] (%o7)
when FMT2 =>
if (op2 = SETHI) then write_reg := '1'; end if;
when FMT3 =>
case op3 is
when UMUL | SMUL | UMULCC | SMULCC =>
if true then
if (((mulo.nready = '1') and (r.d.cnt /= "00")) or (0 /= 0)) then
write_reg := '1';
end if;
else write_reg := '1'; end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if true then
if (divo.nready = '1') and (r.d.cnt /= "00") then
write_reg := '1';
end if;
else write_reg := '1'; end if;
when RETT | WRPSR | WRY | WRWIM | WRTBR | TICC | FLUSH => null;
when FPOP1 | FPOP2 => null;
when CPOP1 | CPOP2 => null;
when others => write_reg := '1';
end case;
when others => -- LDST
ld := not op3(2);
if (op3(2) = '0') and not ((false or FPEN) and (op3(5) = '1'))
then write_reg := '1'; end if;
case op3 is
when SWAP | SWAPA | LDSTUB | LDSTUBA =>
if r.d.cnt = "00" then write_reg := '1'; ld := '1'; end if;
when others => null;
end case;
if r.d.cnt = "01" then
case op3 is
when LDD | LDDA | LDDC | LDDF => rd(0) := '1';
when others =>
end case;
end if;
end case;
if (rd = "00000") then write_reg := '0'; end if;
wreg := write_reg; rdo := rd;
end;
-- immediate data generation
function imm_data (r : registers; insn : word)
return word is
variable immediate_data, inst : word;
begin
immediate_data := (others => '0'); inst := insn;
case inst(31 downto 30) is
when FMT2 =>
immediate_data := inst(21 downto 0) & "0000000000";
when others => -- LDST
immediate_data(31 downto 13) := (others => inst(12));
immediate_data(12 downto 0) := inst(12 downto 0);
end case;
return(immediate_data);
end;
-- read special registers
function get_spr (r : registers) return word is
variable spr : word;
begin
spr := (others => '0');
case r.e.ctrl.inst(24 downto 19) is
when RDPSR => spr(31 downto 5) := conv_std_logic_vector(15,4) &
conv_std_logic_vector(3,4) & r.m.icc & "000000" & r.w.s.ec & r.w.s.ef &
r.w.s.pil & r.e.su & r.w.s.ps & r.e.et;
spr(3-1 downto 0) := r.e.cwp;
when RDTBR => spr(31 downto 4) := r.w.s.tba & r.w.s.tt;
when RDWIM => spr(8-1 downto 0) := r.w.s.wim;
when others =>
end case;
return(spr);
end;
-- immediate data select
function imm_select(inst : word) return boolean is
variable imm : boolean;
begin
imm := false;
case inst(31 downto 30) is
when FMT2 =>
case inst(24 downto 22) is
when SETHI => imm := true;
when others =>
end case;
when FMT3 =>
case inst(24 downto 19) is
when RDWIM | RDPSR | RDTBR => imm := true;
when others => if (inst(13) = '1') then imm := true; end if;
end case;
when LDST =>
if (inst(13) = '1') then imm := true; end if;
when others =>
end case;
return(imm);
end;
-- EXE operation
procedure alu_op(r : in registers; iop1, iop2 : in word; me_icc : std_logic_vector(3 downto 0);
my, ldbp : std_ulogic; aop1, aop2 : out word; aluop : out std_logic_vector(2 downto 0);
alusel : out std_logic_vector(1 downto 0); aluadd : out std_ulogic;
shcnt : out std_logic_vector(4 downto 0); sari, shleft, ymsb,
mulins, divins, mulstep, macins, ldbp2, invop2 : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable icc : std_logic_vector(3 downto 0);
variable y0 : std_ulogic;
begin
op := r.a.ctrl.inst(31 downto 30);
op2 := r.a.ctrl.inst(24 downto 22);
op3 := r.a.ctrl.inst(24 downto 19);
aop1 := iop1; aop2 := iop2; ldbp2 := ldbp;
aluop := EXE_NOP; alusel := EXE_RES_MISC; aluadd := '1';
shcnt := iop2(4 downto 0); sari := '0'; shleft := '0'; invop2 := '0';
ymsb := iop1(0); mulins := '0'; divins := '0'; mulstep := '0';
macins := '0';
if r.e.ctrl.wy = '1' then y0 := my;
elsif r.m.ctrl.wy = '1' then y0 := r.m.y(0);
elsif r.x.ctrl.wy = '1' then y0 := r.x.y(0);
else y0 := r.w.s.y(0); end if;
if r.e.ctrl.wicc = '1' then icc := me_icc;
elsif r.m.ctrl.wicc = '1' then icc := r.m.icc;
elsif r.x.ctrl.wicc = '1' then icc := r.x.icc;
else icc := r.w.s.icc; end if;
case op is
when CALL =>
aluop := EXE_LINK;
when FMT2 =>
case op2 is
when SETHI => aluop := EXE_PASS2;
when others =>
end case;
when FMT3 =>
case op3 is
when IADD | ADDX | ADDCC | ADDXCC | TADDCC | TADDCCTV | SAVE | RESTORE |
TICC | JMPL | RETT => alusel := EXE_RES_ADD;
when ISUB | SUBX | SUBCC | SUBXCC | TSUBCC | TSUBCCTV =>
alusel := EXE_RES_ADD; aluadd := '0'; aop2 := not iop2; invop2 := '1';
when MULSCC => alusel := EXE_RES_ADD;
aop1 := (icc(3) xor icc(1)) & iop1(31 downto 1);
if y0 = '0' then aop2 := (others => '0'); ldbp2 := '0'; end if;
mulstep := '1';
when UMUL | UMULCC | SMUL | SMULCC =>
if true then mulins := '1'; end if;
when UMAC | SMAC =>
if false then mulins := '1'; macins := '1'; end if;
when UDIV | UDIVCC | SDIV | SDIVCC =>
if true then
aluop := EXE_DIV; alusel := EXE_RES_LOGIC; divins := '1';
end if;
when IAND | ANDCC => aluop := EXE_AND; alusel := EXE_RES_LOGIC;
when ANDN | ANDNCC => aluop := EXE_ANDN; alusel := EXE_RES_LOGIC;
when IOR | ORCC => aluop := EXE_OR; alusel := EXE_RES_LOGIC;
when ORN | ORNCC => aluop := EXE_ORN; alusel := EXE_RES_LOGIC;
when IXNOR | XNORCC => aluop := EXE_XNOR; alusel := EXE_RES_LOGIC;
when XORCC | IXOR | WRPSR | WRWIM | WRTBR | WRY =>
aluop := EXE_XOR; alusel := EXE_RES_LOGIC;
when RDPSR | RDTBR | RDWIM => aluop := EXE_SPR;
when RDY => aluop := EXE_RDY;
when ISLL => aluop := EXE_SLL; alusel := EXE_RES_SHIFT; shleft := '1';
shcnt := not iop2(4 downto 0); invop2 := '1';
when ISRL => aluop := EXE_SRL; alusel := EXE_RES_SHIFT;
when ISRA => aluop := EXE_SRA; alusel := EXE_RES_SHIFT; sari := iop1(31);
when FPOP1 | FPOP2 =>
when others =>
end case;
when others => -- LDST
case r.a.ctrl.cnt is
when "00" =>
alusel := EXE_RES_ADD;
when "01" =>
case op3 is
when LDD | LDDA | LDDC => alusel := EXE_RES_ADD;
when LDDF => alusel := EXE_RES_ADD;
when SWAP | SWAPA | LDSTUB | LDSTUBA => alusel := EXE_RES_ADD;
when STF | STDF =>
when others =>
aluop := EXE_PASS1;
if op3(2) = '1' then
if op3(1 downto 0) = "01" then aluop := EXE_STB;
elsif op3(1 downto 0) = "10" then aluop := EXE_STH; end if;
end if;
end case;
when "10" =>
aluop := EXE_PASS1;
if op3(2) = '1' then -- ST
if (op3(3) and not op3(1))= '1' then aluop := EXE_ONES; end if; -- LDSTUB/A
end if;
when others =>
end case;
end case;
end;
function ra_inull_gen(r, v : registers) return std_ulogic is
variable de_inull : std_ulogic;
begin
de_inull := '0';
if ((v.e.jmpl or v.e.ctrl.rett) and not v.e.ctrl.annul and not (r.e.jmpl and not r.e.ctrl.annul)) = '1' then de_inull := '1'; end if;
if ((v.a.jmpl or v.a.ctrl.rett) and not v.a.ctrl.annul and not (r.a.jmpl and not r.a.ctrl.annul)) = '1' then de_inull := '1'; end if;
return(de_inull);
end;
-- operand generation
procedure op_mux(r : in registers; rfd, ed, md, xd, im : in word;
rsel : in std_logic_vector(2 downto 0);
ldbp : out std_ulogic; d : out word) is
begin
ldbp := '0';
case rsel is
when "000" => d := rfd;
when "001" => d := ed;
when "010" => d := md; if lddel = 1 then ldbp := r.m.ctrl.ld; end if;
when "011" => d := xd;
when "100" => d := im;
when "101" => d := (others => '0');
when "110" => d := r.w.result;
when others => d := (others => '-');
end case;
end;
procedure op_find(r : in registers; ldchkra : std_ulogic; ldchkex : std_ulogic;
rs1 : std_logic_vector(4 downto 0); ra : rfatype; im : boolean; rfe : out std_ulogic;
osel : out std_logic_vector(2 downto 0); ldcheck : std_ulogic) is
begin
rfe := '0';
if im then osel := "100";
elsif rs1 = "00000" then osel := "101"; -- %g0
elsif ((r.a.ctrl.wreg and ldchkra) = '1') and (ra = r.a.ctrl.rd) then osel := "001";
elsif ((r.e.ctrl.wreg and ldchkex) = '1') and (ra = r.e.ctrl.rd) then osel := "010";
elsif r.m.ctrl.wreg = '1' and (ra = r.m.ctrl.rd) then osel := "011";
elsif (irfwt = 0) and r.x.ctrl.wreg = '1' and (ra = r.x.ctrl.rd) then osel := "110";
else osel := "000"; rfe := ldcheck; end if;
end;
-- generate carry-in for alu
procedure cin_gen(r : registers; me_cin : in std_ulogic; cin : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable ncin : std_ulogic;
begin
op := r.a.ctrl.inst(31 downto 30); op3 := r.a.ctrl.inst(24 downto 19);
if r.e.ctrl.wicc = '1' then ncin := me_cin;
else ncin := r.m.icc(0); end if;
cin := '0';
case op is
when FMT3 =>
case op3 is
when ISUB | SUBCC | TSUBCC | TSUBCCTV => cin := '1';
when ADDX | ADDXCC => cin := ncin;
when SUBX | SUBXCC => cin := not ncin;
when others => null;
end case;
when others => null;
end case;
end;
procedure logic_op(r : registers; aluin1, aluin2, mey : word;
ymsb : std_ulogic; logicres, y : out word) is
variable logicout : word;
begin
case r.e.aluop is
when EXE_AND => logicout := aluin1 and aluin2;
when EXE_ANDN => logicout := aluin1 and not aluin2;
when EXE_OR => logicout := aluin1 or aluin2;
when EXE_ORN => logicout := aluin1 or not aluin2;
when EXE_XOR => logicout := aluin1 xor aluin2;
when EXE_XNOR => logicout := aluin1 xor not aluin2;
when EXE_DIV =>
if true then logicout := aluin2;
else logicout := (others => '-'); end if;
when others => logicout := (others => '-');
end case;
if (r.e.ctrl.wy and r.e.mulstep) = '1' then
y := ymsb & r.m.y(31 downto 1);
elsif r.e.ctrl.wy = '1' then y := logicout;
elsif r.m.ctrl.wy = '1' then y := mey;
elsif false and (r.x.mac = '1') then y := mulo.result(63 downto 32);
elsif r.x.ctrl.wy = '1' then y := r.x.y;
else y := r.w.s.y; end if;
logicres := logicout;
end;
procedure misc_op(r : registers; wpr : watchpoint_registers;
aluin1, aluin2, ldata, mey : word;
mout, edata : out word) is
variable miscout, bpdata, stdata : word;
variable wpi : integer;
begin
wpi := 0; miscout := r.e.ctrl.pc(31 downto 2) & "00";
edata := aluin1; bpdata := aluin1;
if ((r.x.ctrl.wreg and r.x.ctrl.ld and not r.x.ctrl.annul) = '1') and
(r.x.ctrl.rd = r.e.ctrl.rd) and (r.e.ctrl.inst(31 downto 30) = LDST) and
(r.e.ctrl.cnt /= "10")
then bpdata := ldata; end if;
case r.e.aluop is
when EXE_STB => miscout := bpdata(7 downto 0) & bpdata(7 downto 0) &
bpdata(7 downto 0) & bpdata(7 downto 0);
edata := miscout;
when EXE_STH => miscout := bpdata(15 downto 0) & bpdata(15 downto 0);
edata := miscout;
when EXE_PASS1 => miscout := bpdata; edata := miscout;
when EXE_PASS2 => miscout := aluin2;
when EXE_ONES => miscout := (others => '1');
edata := miscout;
when EXE_RDY =>
if true and (r.m.ctrl.wy = '1') then miscout := mey;
else miscout := r.m.y; end if;
if (NWP > 0) and (r.e.ctrl.inst(18 downto 17) = "11") then
wpi := conv_integer(r.e.ctrl.inst(16 downto 15));
if r.e.ctrl.inst(14) = '0' then miscout := wpr(wpi).addr & '0' & wpr(wpi).exec;
else miscout := wpr(wpi).mask & wpr(wpi).load & wpr(wpi).store; end if;
end if;
if (r.e.ctrl.inst(18 downto 17) = "10") and (r.e.ctrl.inst(14) = '1') then --%ASR17
miscout := asr17_gen(r);
end if;
if false then
if (r.e.ctrl.inst(18 downto 14) = "10010") then --%ASR18
if ((r.m.mac = '1') and not false) or ((r.x.mac = '1') and false) then
miscout := mulo.result(31 downto 0); -- data forward of asr18
else miscout := r.w.s.asr18; end if;
else
if ((r.m.mac = '1') and not false) or ((r.x.mac = '1') and false) then
miscout := mulo.result(63 downto 32); -- data forward Y
end if;
end if;
end if;
when EXE_SPR =>
miscout := get_spr(r);
when others => null;
end case;
mout := miscout;
end;
procedure alu_select(r : registers; addout : std_logic_vector(32 downto 0);
op1, op2 : word; shiftout, logicout, miscout : word; res : out word;
me_icc : std_logic_vector(3 downto 0);
icco : out std_logic_vector(3 downto 0); divz : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable icc : std_logic_vector(3 downto 0);
variable aluresult : word;
begin
op := r.e.ctrl.inst(31 downto 30); op3 := r.e.ctrl.inst(24 downto 19);
icc := (others => '0');
case r.e.alusel is
when EXE_RES_ADD =>
aluresult := addout(32 downto 1);
if r.e.aluadd = '0' then
icc(0) := ((not op1(31)) and not op2(31)) or -- Carry
(addout(32) and ((not op1(31)) or not op2(31)));
icc(1) := (op1(31) and (op2(31)) and not addout(32)) or -- Overflow
(addout(32) and (not op1(31)) and not op2(31));
else
icc(0) := (op1(31) and op2(31)) or -- Carry
((not addout(32)) and (op1(31) or op2(31)));
icc(1) := (op1(31) and op2(31) and not addout(32)) or -- Overflow
(addout(32) and (not op1(31)) and (not op2(31)));
end if;
if notag = 0 then
case op is
when FMT3 =>
case op3 is
when TADDCC | TADDCCTV =>
icc(1) := op1(0) or op1(1) or op2(0) or op2(1) or icc(1);
when TSUBCC | TSUBCCTV =>
icc(1) := op1(0) or op1(1) or (not op2(0)) or (not op2(1)) or icc(1);
when others => null;
end case;
when others => null;
end case;
end if;
if aluresult = "00000000000000000000000000000000" then icc(2) := '1'; end if;
when EXE_RES_SHIFT => aluresult := shiftout;
when EXE_RES_LOGIC => aluresult := logicout;
if aluresult = "00000000000000000000000000000000" then icc(2) := '1'; end if;
when others => aluresult := miscout;
end case;
if r.e.jmpl = '1' then aluresult := r.e.ctrl.pc(31 downto 2) & "00"; end if;
icc(3) := aluresult(31); divz := icc(2);
if r.e.ctrl.wicc = '1' then
if (op = FMT3) and (op3 = WRPSR) then icco := logicout(23 downto 20);
else icco := icc; end if;
elsif r.m.ctrl.wicc = '1' then icco := me_icc;
elsif r.x.ctrl.wicc = '1' then icco := r.x.icc;
else icco := r.w.s.icc; end if;
res := aluresult;
end;
procedure dcache_gen(r, v : registers; dci : out dc_in_type;
link_pc, jump, force_a2, load : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable su : std_ulogic;
begin
op := r.e.ctrl.inst(31 downto 30); op3 := r.e.ctrl.inst(24 downto 19);
dci.signed := '0'; dci.lock := '0'; dci.dsuen := '0'; dci.size := SZWORD;
if op = LDST then
case op3 is
when LDUB | LDUBA => dci.size := SZBYTE;
when LDSTUB | LDSTUBA => dci.size := SZBYTE; dci.lock := '1';
when LDUH | LDUHA => dci.size := SZHALF;
when LDSB | LDSBA => dci.size := SZBYTE; dci.signed := '1';
when LDSH | LDSHA => dci.size := SZHALF; dci.signed := '1';
when LD | LDA | LDF | LDC => dci.size := SZWORD;
when SWAP | SWAPA => dci.size := SZWORD; dci.lock := '1';
when LDD | LDDA | LDDF | LDDC => dci.size := SZDBL;
when STB | STBA => dci.size := SZBYTE;
when STH | STHA => dci.size := SZHALF;
when ST | STA | STF => dci.size := SZWORD;
when ISTD | STDA => dci.size := SZDBL;
when STDF | STDFQ => if FPEN then dci.size := SZDBL; end if;
when STDC | STDCQ => if false then dci.size := SZDBL; end if;
when others => dci.size := SZWORD; dci.lock := '0'; dci.signed := '0';
end case;
end if;
link_pc := '0'; jump:= '0'; force_a2 := '0'; load := '0';
dci.write := '0'; dci.enaddr := '0'; dci.read := not op3(2);
-- load/store control decoding
if (r.e.ctrl.annul = '0') then
case op is
when CALL => link_pc := '1';
when FMT3 =>
case op3 is
when JMPL => jump := '1'; link_pc := '1';
when RETT => jump := '1';
when others => null;
end case;
when LDST =>
case r.e.ctrl.cnt is
when "00" =>
dci.read := op3(3) or not op3(2); -- LD/LDST/SWAP
load := op3(3) or not op3(2);
dci.enaddr := '1';
when "01" =>
force_a2 := not op3(2); -- LDD
load := not op3(2); dci.enaddr := not op3(2);
if op3(3 downto 2) = "01" then -- ST/STD
dci.write := '1';
end if;
if op3(3 downto 2) = "11" then -- LDST/SWAP
dci.enaddr := '1';
end if;
when "10" => -- STD/LDST/SWAP
dci.write := '1';
when others => null;
end case;
if (r.e.ctrl.trap or (v.x.ctrl.trap and not v.x.ctrl.annul)) = '1' then
dci.enaddr := '0';
end if;
when others => null;
end case;
end if;
if ((r.x.ctrl.rett and not r.x.ctrl.annul) = '1') then su := r.w.s.ps;
else su := r.w.s.s; end if;
if su = '1' then dci.asi := "00001011"; else dci.asi := "00001010"; end if;
if (op3(4) = '1') and ((op3(5) = '0') or not false) then
dci.asi := r.e.ctrl.inst(12 downto 5);
end if;
end;
procedure fpstdata(r : in registers; edata, eres : in word; fpstdata : in std_logic_vector(31 downto 0);
edata2, eres2 : out word) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
begin
edata2 := edata; eres2 := eres;
op := r.e.ctrl.inst(31 downto 30); op3 := r.e.ctrl.inst(24 downto 19);
if FPEN then
if FPEN and (op = LDST) and ((op3(5 downto 4) & op3(2)) = "101") and (r.e.ctrl.cnt /= "00") then
edata2 := fpstdata; eres2 := fpstdata;
end if;
end if;
end;
function ld_align(data : dcdtype; set : std_logic_vector(0 downto 0);
size, laddr : std_logic_vector(1 downto 0); signed : std_ulogic) return word is
variable align_data, rdata : word;
begin
align_data := data(conv_integer(set)); rdata := (others => '0');
case size is
when "00" => -- byte read
case laddr is
when "00" =>
rdata(7 downto 0) := align_data(31 downto 24);
if signed = '1' then rdata(31 downto 8) := (others => align_data(31)); end if;
when "01" =>
rdata(7 downto 0) := align_data(23 downto 16);
if signed = '1' then rdata(31 downto 8) := (others => align_data(23)); end if;
when "10" =>
rdata(7 downto 0) := align_data(15 downto 8);
if signed = '1' then rdata(31 downto 8) := (others => align_data(15)); end if;
when others =>
rdata(7 downto 0) := align_data(7 downto 0);
if signed = '1' then rdata(31 downto 8) := (others => align_data(7)); end if;
end case;
when "01" => -- half-word read
if laddr(1) = '1' then
rdata(15 downto 0) := align_data(15 downto 0);
if signed = '1' then rdata(31 downto 15) := (others => align_data(15)); end if;
else
rdata(15 downto 0) := align_data(31 downto 16);
if signed = '1' then rdata(31 downto 15) := (others => align_data(31)); end if;
end if;
when others => -- single and double word read
rdata := align_data;
end case;
return(rdata);
end;
procedure mem_trap(r : registers; wpr : watchpoint_registers;
annul, holdn : in std_ulogic;
trapout, iflush, nullify, werrout : out std_ulogic;
tt : out std_logic_vector(5 downto 0)) is
variable cwp : std_logic_vector(3-1 downto 0);
variable cwpx : std_logic_vector(5 downto 3);
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable nalign_d : std_ulogic;
variable trap, werr : std_ulogic;
begin
op := r.m.ctrl.inst(31 downto 30); op2 := r.m.ctrl.inst(24 downto 22);
op3 := r.m.ctrl.inst(24 downto 19);
cwpx := r.m.result(5 downto 3); cwpx(5) := '0';
iflush := '0'; trap := r.m.ctrl.trap; nullify := annul;
tt := r.m.ctrl.tt; werr := (dco.werr or r.m.werr) and not r.w.s.dwt;
nalign_d := r.m.nalign or r.m.result(2);
if ((annul or trap) /= '1') and (r.m.ctrl.pv = '1') then
if (werr and holdn) = '1' then
trap := '1'; tt := TT_DSEX; werr := '0';
if op = LDST then nullify := '1'; end if;
end if;
end if;
if ((annul or trap) /= '1') then
case op is
when FMT2 =>
case op2 is
when FBFCC =>
if FPEN and (fpo.exc = '1') then trap := '1'; tt := TT_FPEXC; end if;
when CBCCC =>
if false and (cpo.exc = '1') then trap := '1'; tt := TT_CPEXC; end if;
when others => null;
end case;
when FMT3 =>
case op3 is
when WRPSR =>
if (orv(cwpx) = '1') then trap := '1'; tt := TT_IINST; end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if true then
if r.m.divz = '1' then trap := '1'; tt := TT_DIV; end if;
end if;
when JMPL | RETT =>
if r.m.nalign = '1' then trap := '1'; tt := TT_UNALA; end if;
when TADDCCTV | TSUBCCTV =>
if (notag = 0) and (r.m.icc(1) = '1') then
trap := '1'; tt := TT_TAG;
end if;
when FLUSH => iflush := '1';
when FPOP1 | FPOP2 =>
if FPEN and (fpo.exc = '1') then trap := '1'; tt := TT_FPEXC; end if;
when CPOP1 | CPOP2 =>
if false and (cpo.exc = '1') then trap := '1'; tt := TT_CPEXC; end if;
when others => null;
end case;
when LDST =>
if r.m.ctrl.cnt = "00" then
case op3 is
when LDDF | STDF | STDFQ =>
if FPEN then
if nalign_d = '1' then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif (fpo.exc and r.m.ctrl.pv) = '1'
then trap := '1'; tt := TT_FPEXC; nullify := '1'; end if;
end if;
when LDDC | STDC | STDCQ =>
if false then
if nalign_d = '1' then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif ((cpo.exc and r.m.ctrl.pv) = '1')
then trap := '1'; tt := TT_CPEXC; nullify := '1'; end if;
end if;
when LDD | ISTD | LDDA | STDA =>
if r.m.result(2 downto 0) /= "000" then
trap := '1'; tt := TT_UNALA; nullify := '1';
end if;
when LDF | LDFSR | STFSR | STF =>
if FPEN and (r.m.nalign = '1') then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif FPEN and ((fpo.exc and r.m.ctrl.pv) = '1')
then trap := '1'; tt := TT_FPEXC; nullify := '1'; end if;
when LDC | LDCSR | STCSR | STC =>
if false and (r.m.nalign = '1') then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif false and ((cpo.exc and r.m.ctrl.pv) = '1')
then trap := '1'; tt := TT_CPEXC; nullify := '1'; end if;
when LD | LDA | ST | STA | SWAP | SWAPA =>
if r.m.result(1 downto 0) /= "00" then
trap := '1'; tt := TT_UNALA; nullify := '1';
end if;
when LDUH | LDUHA | LDSH | LDSHA | STH | STHA =>
if r.m.result(0) /= '0' then
trap := '1'; tt := TT_UNALA; nullify := '1';
end if;
when others => null;
end case;
for i in 1 to NWP loop
if ((((wpr(i-1).load and not op3(2)) or (wpr(i-1).store and op3(2))) = '1') and
(((wpr(i-1).addr xor r.m.result(31 downto 2)) and wpr(i-1).mask) = "000000000000000000000000000000"))
then trap := '1'; tt := TT_WATCH; nullify := '1'; end if;
end loop;
end if;
when others => null;
end case;
end if;
if (rstn = '0') or (r.x.rstate = dsu2) then werr := '0'; end if;
trapout := trap; werrout := werr;
end;
procedure irq_trap(r : in registers;
ir : in irestart_register;
irl : in std_logic_vector(3 downto 0);
annul : in std_ulogic;
pv : in std_ulogic;
trap : in std_ulogic;
tt : in std_logic_vector(5 downto 0);
nullify : in std_ulogic;
irqen : out std_ulogic;
irqen2 : out std_ulogic;
nullify2 : out std_ulogic;
trap2, ipend : out std_ulogic;
tt2 : out std_logic_vector(5 downto 0)) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable pend : std_ulogic;
begin
nullify2 := nullify; trap2 := trap; tt2 := tt;
op := r.m.ctrl.inst(31 downto 30); op3 := r.m.ctrl.inst(24 downto 19);
irqen := '1'; irqen2 := r.m.irqen;
if (annul or trap) = '0' then
if ((op = FMT3) and (op3 = WRPSR)) then irqen := '0'; end if;
end if;
if (irl = "1111") or (irl > r.w.s.pil) then
pend := r.m.irqen and r.m.irqen2 and r.w.s.et and not ir.pwd;
else pend := '0'; end if;
ipend := pend;
if ((not annul) and pv and (not trap) and pend) = '1' then
trap2 := '1'; tt2 := "01" & irl;
if op = LDST then nullify2 := '1'; end if;
end if;
end;
procedure irq_intack(r : in registers; holdn : in std_ulogic; intack: out std_ulogic) is
begin
intack := '0';
if r.x.rstate = trap then
if r.w.s.tt(7 downto 4) = "0001" then intack := '1'; end if;
end if;
end;
-- write special registers
procedure sp_write (r : registers; wpr : watchpoint_registers;
s : out special_register_type; vwpr : out watchpoint_registers) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable i : integer range 0 to 3;
begin
op := r.x.ctrl.inst(31 downto 30);
op2 := r.x.ctrl.inst(24 downto 22);
op3 := r.x.ctrl.inst(24 downto 19);
s := r.w.s;
rd := r.x.ctrl.inst(29 downto 25);
vwpr := wpr;
case op is
when FMT3 =>
case op3 is
when WRY =>
if rd = "00000" then
s.y := r.x.result;
elsif false and (rd = "10010") then
s.asr18 := r.x.result;
elsif (rd = "10001") then
s.dwt := r.x.result(14);
if (svt = 1) then s.svt := r.x.result(13); end if;
elsif rd(4 downto 3) = "11" then -- %ASR24 - %ASR31
case rd(2 downto 0) is
when "000" =>
vwpr(0).addr := r.x.result(31 downto 2);
vwpr(0).exec := r.x.result(0);
when "001" =>
vwpr(0).mask := r.x.result(31 downto 2);
vwpr(0).load := r.x.result(1);
vwpr(0).store := r.x.result(0);
when "010" =>
vwpr(1).addr := r.x.result(31 downto 2);
vwpr(1).exec := r.x.result(0);
when "011" =>
vwpr(1).mask := r.x.result(31 downto 2);
vwpr(1).load := r.x.result(1);
vwpr(1).store := r.x.result(0);
when "100" =>
vwpr(2).addr := r.x.result(31 downto 2);
vwpr(2).exec := r.x.result(0);
when "101" =>
vwpr(2).mask := r.x.result(31 downto 2);
vwpr(2).load := r.x.result(1);
vwpr(2).store := r.x.result(0);
when "110" =>
vwpr(3).addr := r.x.result(31 downto 2);
vwpr(3).exec := r.x.result(0);
when others => -- "111"
vwpr(3).mask := r.x.result(31 downto 2);
vwpr(3).load := r.x.result(1);
vwpr(3).store := r.x.result(0);
end case;
end if;
when WRPSR =>
s.cwp := r.x.result(3-1 downto 0);
s.icc := r.x.result(23 downto 20);
s.ec := r.x.result(13);
if FPEN then s.ef := r.x.result(12); end if;
s.pil := r.x.result(11 downto 8);
s.s := r.x.result(7);
s.ps := r.x.result(6);
s.et := r.x.result(5);
when WRWIM =>
s.wim := r.x.result(8-1 downto 0);
when WRTBR =>
s.tba := r.x.result(31 downto 12);
when SAVE =>
if (not true) and (r.w.s.cwp = "000") then s.cwp := "111";
else s.cwp := r.w.s.cwp - 1 ; end if;
when RESTORE =>
if (not true) and (r.w.s.cwp = "111") then s.cwp := "000";
else s.cwp := r.w.s.cwp + 1; end if;
when RETT =>
if (not true) and (r.w.s.cwp = "111") then s.cwp := "000";
else s.cwp := r.w.s.cwp + 1; end if;
s.s := r.w.s.ps;
s.et := '1';
when others => null;
end case;
when others => null;
end case;
if r.x.ctrl.wicc = '1' then s.icc := r.x.icc; end if;
if r.x.ctrl.wy = '1' then s.y := r.x.y; end if;
if false and (r.x.mac = '1') then
s.asr18 := mulo.result(31 downto 0);
s.y := mulo.result(63 downto 32);
end if;
end;
function npc_find (r : registers) return std_logic_vector is
variable npc : std_logic_vector(2 downto 0);
begin
npc := "011";
if r.m.ctrl.pv = '1' then npc := "000";
elsif r.e.ctrl.pv = '1' then npc := "001";
elsif r.a.ctrl.pv = '1' then npc := "010";
elsif r.d.pv = '1' then npc := "011";
elsif 2 /= 0 then npc := "100"; end if;
return(npc);
end;
function npc_gen (r : registers) return word is
variable npc : std_logic_vector(31 downto 0);
begin
npc := r.a.ctrl.pc(31 downto 2) & "00";
case r.x.npc is
when "000" => npc(31 downto 2) := r.x.ctrl.pc(31 downto 2);
when "001" => npc(31 downto 2) := r.m.ctrl.pc(31 downto 2);
when "010" => npc(31 downto 2) := r.e.ctrl.pc(31 downto 2);
when "011" => npc(31 downto 2) := r.a.ctrl.pc(31 downto 2);
when others =>
if 2 /= 0 then npc(31 downto 2) := r.d.pc(31 downto 2); end if;
end case;
return(npc);
end;
procedure mul_res(r : registers; asr18in : word; result, y, asr18 : out word;
icc : out std_logic_vector(3 downto 0)) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
begin
op := r.m.ctrl.inst(31 downto 30); op3 := r.m.ctrl.inst(24 downto 19);
result := r.m.result; y := r.m.y; icc := r.m.icc; asr18 := asr18in;
case op is
when FMT3 =>
case op3 is
when UMUL | SMUL =>
if true then
result := mulo.result(31 downto 0);
y := mulo.result(63 downto 32);
end if;
when UMULCC | SMULCC =>
if true then
result := mulo.result(31 downto 0); icc := mulo.icc;
y := mulo.result(63 downto 32);
end if;
when UMAC | SMAC =>
if false and not false then
result := mulo.result(31 downto 0);
asr18 := mulo.result(31 downto 0);
y := mulo.result(63 downto 32);
end if;
when UDIV | SDIV =>
if true then
result := divo.result(31 downto 0);
end if;
when UDIVCC | SDIVCC =>
if true then
result := divo.result(31 downto 0); icc := divo.icc;
end if;
when others => null;
end case;
when others => null;
end case;
end;
function powerdwn(r : registers; trap : std_ulogic; rp : pwd_register_type) return std_ulogic is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable pd : std_ulogic;
begin
op := r.x.ctrl.inst(31 downto 30);
op3 := r.x.ctrl.inst(24 downto 19);
rd := r.x.ctrl.inst(29 downto 25);
pd := '0';
if (not (r.x.ctrl.annul or trap) and r.x.ctrl.pv) = '1' then
if ((op = FMT3) and (op3 = WRY) and (rd = "10011")) then pd := '1'; end if;
pd := pd or rp.pwd;
end if;
return(pd);
end;
signal dummy : std_ulogic;
signal cpu_index : std_logic_vector(3 downto 0);
signal disasen : std_ulogic;
begin
comb : process(ico, dco, rfo, r, wpr, ir, dsur, rstn, holdn, irqi, dbgi, fpo, cpo, tbo,
mulo, divo, dummy, rp)
variable v : registers;
variable vp : pwd_register_type;
variable vwpr : watchpoint_registers;
variable vdsu : dsu_registers;
variable npc : std_logic_vector(31 downto 2);
variable de_raddr1, de_raddr2 : std_logic_vector(9 downto 0);
variable de_rs2, de_rd : std_logic_vector(4 downto 0);
variable de_hold_pc, de_branch, de_fpop, de_ldlock : std_ulogic;
variable de_cwp, de_cwp2 : cwptype;
variable de_inull : std_ulogic;
variable de_ren1, de_ren2 : std_ulogic;
variable de_wcwp : std_ulogic;
variable de_inst : word;
variable de_branch_address : pctype;
variable de_icc : std_logic_vector(3 downto 0);
variable de_fbranch, de_cbranch : std_ulogic;
variable de_rs1mod : std_ulogic;
variable ra_op1, ra_op2 : word;
variable ra_div : std_ulogic;
variable ex_jump, ex_link_pc : std_ulogic;
variable ex_jump_address : pctype;
variable ex_add_res : std_logic_vector(32 downto 0);
variable ex_shift_res, ex_logic_res, ex_misc_res : word;
variable ex_edata, ex_edata2 : word;
variable ex_dci : dc_in_type;
variable ex_force_a2, ex_load, ex_ymsb : std_ulogic;
variable ex_op1, ex_op2, ex_result, ex_result2, mul_op2 : word;
variable ex_shcnt : std_logic_vector(4 downto 0);
variable ex_dsuen : std_ulogic;
variable ex_ldbp2 : std_ulogic;
variable ex_sari : std_ulogic;
variable me_inull, me_nullify, me_nullify2 : std_ulogic;
variable me_iflush : std_ulogic;
variable me_newtt : std_logic_vector(5 downto 0);
variable me_asr18 : word;
variable me_signed : std_ulogic;
variable me_size, me_laddr : std_logic_vector(1 downto 0);
variable me_icc : std_logic_vector(3 downto 0);
variable xc_result : word;
variable xc_df_result : word;
variable xc_waddr : std_logic_vector(9 downto 0);
variable xc_exception, xc_wreg : std_ulogic;
variable xc_trap_address : pctype;
variable xc_vectt : std_logic_vector(7 downto 0);
variable xc_trap : std_ulogic;
variable xc_fpexack : std_ulogic;
variable xc_rstn, xc_halt : std_ulogic;
-- variable wr_rf1_data, wr_rf2_data : word;
variable diagdata : word;
variable tbufi : tracebuf_in_type;
variable dbgm : std_ulogic;
variable fpcdbgwr : std_ulogic;
variable vfpi : fpc_in_type;
variable dsign : std_ulogic;
variable pwrd, sidle : std_ulogic;
variable vir : irestart_register;
variable icnt : std_ulogic;
variable tbufcntx : std_logic_vector(7-1 downto 0);
begin
v := r; vwpr := wpr; vdsu := dsur; vp := rp;
xc_fpexack := '0'; sidle := '0';
fpcdbgwr := '0'; vir := ir; xc_rstn := rstn;
-----------------------------------------------------------------------
-- WRITE STAGE
-----------------------------------------------------------------------
-- wr_rf1_data := rfo.data1; wr_rf2_data := rfo.data2;
-- if irfwt = 0 then
-- if r.w.wreg = '1' then
-- if r.a.rfa1 = r.w.wa then wr_rf1_data := r.w.result; end if;
-- if r.a.rfa2 = r.w.wa then wr_rf2_data := r.w.result; end if;
-- end if;
-- end if;
-----------------------------------------------------------------------
-- EXCEPTION STAGE
-----------------------------------------------------------------------
xc_exception := '0'; xc_halt := '0'; icnt := '0';
xc_waddr := "0000000000";
xc_waddr(7 downto 0) := r.x.ctrl.rd(7 downto 0);
xc_trap := r.x.mexc or r.x.ctrl.trap;
v.x.nerror := rp.error;
if r.x.mexc = '1' then xc_vectt := "00" & TT_DAEX;
elsif r.x.ctrl.tt = TT_TICC then
xc_vectt := '1' & r.x.result(6 downto 0);
else xc_vectt := "00" & r.x.ctrl.tt; end if;
if r.w.s.svt = '0' then
xc_trap_address(31 downto 4) := r.w.s.tba & xc_vectt;
else
xc_trap_address(31 downto 4) := r.w.s.tba & "00000000";
end if;
xc_trap_address(3 downto 2) := "00";
xc_wreg := '0'; v.x.annul_all := '0';
if (r.x.ctrl.ld = '1') then
if (lddel = 2) then
xc_result := ld_align(r.x.data, r.x.set, r.x.dci.size, r.x.laddr, r.x.dci.signed);
else xc_result := r.x.data(0); end if;
elsif false and false and (r.x.mac = '1') then
xc_result := mulo.result(31 downto 0);
else xc_result := r.x.result; end if;
xc_df_result := xc_result;
if true then
dbgm := dbgexc(r, dbgi, xc_trap, xc_vectt);
if (dbgi.dsuen and dbgi.dbreak) = '0'then v.x.debug := '0'; end if;
else dbgm := '0'; v.x.debug := '0'; end if;
if false then pwrd := powerdwn(r, xc_trap, rp); else pwrd := '0'; end if;
case r.x.rstate is
when run =>
if (not r.x.ctrl.annul and r.x.ctrl.pv and not r.x.debug) = '1' then
icnt := holdn;
end if;
if dbgm = '1' then
v.x.annul_all := '1'; vir.addr := r.x.ctrl.pc;
v.x.rstate := dsu1; v.x.debug := '1';
v.x.npc := npc_find(r);
vdsu.tt := xc_vectt; vdsu.err := dbgerr(r, dbgi, xc_vectt);
elsif (pwrd = '1') and (ir.pwd = '0') then
v.x.annul_all := '1'; vir.addr := r.x.ctrl.pc;
v.x.rstate := dsu1; v.x.npc := npc_find(r); vp.pwd := '1';
elsif (r.x.ctrl.annul or xc_trap) = '0' then
xc_wreg := r.x.ctrl.wreg;
sp_write (r, wpr, v.w.s, vwpr);
vir.pwd := '0';
elsif ((not r.x.ctrl.annul) and xc_trap) = '1' then
xc_exception := '1'; xc_result := r.x.ctrl.pc(31 downto 2) & "00";
xc_wreg := '1'; v.w.s.tt := xc_vectt; v.w.s.ps := r.w.s.s;
v.w.s.s := '1'; v.x.annul_all := '1'; v.x.rstate := trap;
xc_waddr := "0000000000";
xc_waddr(6 downto 0) := r.w.s.cwp & "0001";
v.x.npc := npc_find(r);
fpexack(r, xc_fpexack);
if r.w.s.et = '0' then
-- v.x.rstate := dsu1; xc_wreg := '0'; vp.error := '1';
xc_wreg := '0';
end if;
end if;
when trap =>
xc_result := npc_gen(r); xc_wreg := '1';
xc_waddr := "0000000000";
xc_waddr(6 downto 0) := r.w.s.cwp & "0010";
if (r.w.s.et = '1') then
v.w.s.et := '0'; v.x.rstate := run;
if (not true) and (r.w.s.cwp = "000") then v.w.s.cwp := "111";
else v.w.s.cwp := r.w.s.cwp - 1 ; end if;
else
v.x.rstate := dsu1; xc_wreg := '0'; vp.error := '1';
end if;
when dsu1 =>
xc_exception := '1'; v.x.annul_all := '1';
xc_trap_address(31 downto 2) := r.f.pc;
if true or false or (smp /= 0) then
xc_trap_address(31 downto 2) := ir.addr;
vir.addr := npc_gen(r)(31 downto 2);
v.x.rstate := dsu2;
end if;
if true then v.x.debug := r.x.debug; end if;
when dsu2 =>
xc_exception := '1'; v.x.annul_all := '1';
xc_trap_address(31 downto 2) := r.f.pc;
if true or false or (smp /= 0) then
sidle := (rp.pwd or rp.error) and ico.idle and dco.idle and not r.x.debug;
if true then
if dbgi.reset = '1' then
if smp /=0 then vp.pwd := not irqi.run; else vp.pwd := '0'; end if;
vp.error := '0';
end if;
if (dbgi.dsuen and dbgi.dbreak) = '1'then v.x.debug := '1'; end if;
diagwr(r, dsur, ir, dbgi, wpr, v.w.s, vwpr, vdsu.asi, xc_trap_address,
vir.addr, vdsu.tbufcnt, xc_wreg, xc_waddr, xc_result, fpcdbgwr);
xc_halt := dbgi.halt;
end if;
if r.x.ipend = '1' then vp.pwd := '0'; end if;
if (rp.error or rp.pwd or r.x.debug or xc_halt) = '0' then
v.x.rstate := run; v.x.annul_all := '0'; vp.error := '0';
xc_trap_address(31 downto 2) := ir.addr; v.x.debug := '0';
vir.pwd := '1';
end if;
if (smp /= 0) and (irqi.rst = '1') then
vp.pwd := '0'; vp.error := '0';
end if;
end if;
when others =>
end case;
irq_intack(r, holdn, v.x.intack);
itrace(r, dsur, vdsu, xc_result, xc_exception, dbgi, rp.error, xc_trap, tbufcntx, tbufi);
vdsu.tbufcnt := tbufcntx;
v.w.except := xc_exception; v.w.result := xc_result;
if (r.x.rstate = dsu2) then v.w.except := '0'; end if;
v.w.wa := xc_waddr(7 downto 0); v.w.wreg := xc_wreg and holdn;
rfi.wdata <= xc_result; rfi.waddr <= xc_waddr;
rfi.wren <= (xc_wreg and holdn) and not dco.scanen;
irqo.intack <= r.x.intack and holdn;
irqo.irl <= r.w.s.tt(3 downto 0);
irqo.pwd <= rp.pwd;
irqo.fpen <= r.w.s.ef;
dbgo.halt <= xc_halt;
dbgo.pwd <= rp.pwd;
dbgo.idle <= sidle;
dbgo.icnt <= icnt;
dci.intack <= r.x.intack and holdn;
if (xc_rstn = '0') then
v.w.except := '0'; v.w.s.et := '0'; v.w.s.svt := '0'; v.w.s.dwt := '0';
v.w.s.ef := '0'; -- needed for AX
if need_extra_sync_reset(fabtech) /= 0 then
v.w.s.cwp := "000";
v.w.s.icc := "0000";
end if;
v.x.annul_all := '1'; v.x.rstate := run; vir.pwd := '0';
vp.pwd := '0'; v.x.debug := '0'; --vp.error := '0';
v.x.nerror := '0';
if svt = 1 then v.w.s.tt := "00000000"; end if;
if true then
if (dbgi.dsuen and dbgi.dbreak) = '1' then
v.x.rstate := dsu1; v.x.debug := '1';
end if;
end if;
if (smp /= 0) and (irqi.run = '0') and (rstn = '0') then
v.x.rstate := dsu1; vp.pwd := '1';
end if;
end if;
if not FPEN then v.w.s.ef := '0'; end if;
-----------------------------------------------------------------------
-- MEMORY STAGE
-----------------------------------------------------------------------
v.x.ctrl := r.m.ctrl; v.x.dci := r.m.dci;
v.x.ctrl.rett := r.m.ctrl.rett and not r.m.ctrl.annul;
v.x.mac := r.m.mac; v.x.laddr := r.m.result(1 downto 0);
v.x.ctrl.annul := r.m.ctrl.annul or v.x.annul_all;
mul_res(r, v.w.s.asr18, v.x.result, v.x.y, me_asr18, me_icc);
mem_trap(r, wpr, v.x.ctrl.annul, holdn, v.x.ctrl.trap, me_iflush,
me_nullify, v.m.werr, v.x.ctrl.tt);
me_newtt := v.x.ctrl.tt;
irq_trap(r, ir, irqi.irl, v.x.ctrl.annul, v.x.ctrl.pv, v.x.ctrl.trap, me_newtt, me_nullify,
v.m.irqen, v.m.irqen2, me_nullify2, v.x.ctrl.trap,
v.x.ipend, v.x.ctrl.tt);
if (r.m.ctrl.ld or not dco.mds) = '1' then
for i in 0 to 2-1 loop v.x.data(i) := dco.data(i); end loop;
v.x.set := dco.set(0 downto 0);
if dco.mds = '0' then
me_size := r.x.dci.size; me_laddr := r.x.laddr; me_signed := r.x.dci.signed;
else
me_size := v.x.dci.size; me_laddr := v.x.laddr; me_signed := v.x.dci.signed;
end if;
if lddel /= 2 then
v.x.data(0) := ld_align(v.x.data, v.x.set, me_size, me_laddr, me_signed);
end if;
end if;
v.x.mexc := dco.mexc;
v.x.icc := me_icc;
v.x.ctrl.wicc := r.m.ctrl.wicc and not v.x.annul_all;
if false and ((v.x.ctrl.annul or v.x.ctrl.trap) = '0') then
v.w.s.asr18 := me_asr18;
end if;
if (r.x.rstate = dsu2) then
me_nullify2 := '0'; v.x.set := dco.set(0 downto 0);
end if;
dci.maddress <= r.m.result;
dci.enaddr <= r.m.dci.enaddr;
dci.asi <= r.m.dci.asi;
dci.size <= r.m.dci.size;
dci.nullify <= me_nullify2;
dci.lock <= r.m.dci.lock and not r.m.ctrl.annul;
dci.read <= r.m.dci.read;
dci.write <= r.m.dci.write;
dci.flush <= me_iflush;
dci.dsuen <= r.m.dci.dsuen;
dci.msu <= r.m.su;
dci.esu <= r.e.su;
dbgo.ipend <= v.x.ipend;
-----------------------------------------------------------------------
-- EXECUTE STAGE
-----------------------------------------------------------------------
v.m.ctrl := r.e.ctrl; ex_op1 := r.e.op1; ex_op2 := r.e.op2;
v.m.ctrl.rett := r.e.ctrl.rett and not r.e.ctrl.annul;
v.m.ctrl.wreg := r.e.ctrl.wreg and not v.x.annul_all;
ex_ymsb := r.e.ymsb; mul_op2 := ex_op2; ex_shcnt := r.e.shcnt;
v.e.cwp := r.a.cwp; ex_sari := r.e.sari;
v.m.su := r.e.su;
if 0 = 3 then v.m.mul := r.e.mul; else v.m.mul := '0'; end if;
if lddel = 1 then
if r.e.ldbp1 = '1' then
ex_op1 := r.x.data(0);
ex_sari := r.x.data(0)(31) and r.e.ctrl.inst(19) and r.e.ctrl.inst(20);
end if;
if r.e.ldbp2 = '1' then
ex_op2 := r.x.data(0); ex_ymsb := r.x.data(0)(0);
mul_op2 := ex_op2; ex_shcnt := r.x.data(0)(4 downto 0);
if r.e.invop2 = '1' then
ex_op2 := not ex_op2; ex_shcnt := not ex_shcnt;
end if;
end if;
end if;
ex_add_res := (ex_op1 & '1') + (ex_op2 & r.e.alucin);
if ex_add_res(2 downto 1) = "00" then v.m.nalign := '0';
else v.m.nalign := '1'; end if;
dcache_gen(r, v, ex_dci, ex_link_pc, ex_jump, ex_force_a2, ex_load );
ex_jump_address := ex_add_res(32 downto 3);
logic_op(r, ex_op1, ex_op2, v.x.y, ex_ymsb, ex_logic_res, v.m.y);
ex_shift_res := shift(r, ex_op1, ex_op2, ex_shcnt, ex_sari);
misc_op(r, wpr, ex_op1, ex_op2, xc_df_result, v.x.y, ex_misc_res, ex_edata);
ex_add_res(3):= ex_add_res(3) or ex_force_a2;
alu_select(r, ex_add_res, ex_op1, ex_op2, ex_shift_res, ex_logic_res,
ex_misc_res, ex_result, me_icc, v.m.icc, v.m.divz);
dbg_cache(holdn, dbgi, r, dsur, ex_result, ex_dci, ex_result2, v.m.dci);
fpstdata(r, ex_edata, ex_result2, fpo.data, ex_edata2, v.m.result);
cwp_ex(r, v.m.wcwp);
v.m.ctrl.annul := v.m.ctrl.annul or v.x.annul_all;
v.m.ctrl.wicc := r.e.ctrl.wicc and not v.x.annul_all;
v.m.mac := r.e.mac;
if (true and (r.x.rstate = dsu2)) then v.m.ctrl.ld := '1'; end if;
dci.eenaddr <= v.m.dci.enaddr;
dci.eaddress <= ex_add_res(32 downto 1);
dci.edata <= ex_edata2;
-----------------------------------------------------------------------
-- REGFILE STAGE
-----------------------------------------------------------------------
v.e.ctrl := r.a.ctrl; v.e.jmpl := r.a.jmpl;
v.e.ctrl.annul := r.a.ctrl.annul or v.x.annul_all;
v.e.ctrl.rett := r.a.ctrl.rett and not r.a.ctrl.annul;
v.e.ctrl.wreg := r.a.ctrl.wreg and not v.x.annul_all;
v.e.su := r.a.su; v.e.et := r.a.et;
v.e.ctrl.wicc := r.a.ctrl.wicc and not v.x.annul_all;
exception_detect(r, wpr, dbgi, r.a.ctrl.trap, r.a.ctrl.tt,
v.e.ctrl.trap, v.e.ctrl.tt);
op_mux(r, rfo.data1, v.m.result, v.x.result, xc_df_result, "00000000000000000000000000000000",
r.a.rsel1, v.e.ldbp1, ra_op1);
op_mux(r, rfo.data2, v.m.result, v.x.result, xc_df_result, r.a.imm,
r.a.rsel2, ex_ldbp2, ra_op2);
alu_op(r, ra_op1, ra_op2, v.m.icc, v.m.y(0), ex_ldbp2, v.e.op1, v.e.op2,
v.e.aluop, v.e.alusel, v.e.aluadd, v.e.shcnt, v.e.sari, v.e.shleft,
v.e.ymsb, v.e.mul, ra_div, v.e.mulstep, v.e.mac, v.e.ldbp2, v.e.invop2);
cin_gen(r, v.m.icc(0), v.e.alucin);
-----------------------------------------------------------------------
-- DECODE STAGE
-----------------------------------------------------------------------
if 2 > 1 then de_inst := r.d.inst(conv_integer(r.d.set));
else de_inst := r.d.inst(0); end if;
de_icc := r.m.icc; v.a.cwp := r.d.cwp;
su_et_select(r, v.w.s.ps, v.w.s.s, v.w.s.et, v.a.su, v.a.et);
wicc_y_gen(de_inst, v.a.ctrl.wicc, v.a.ctrl.wy);
cwp_ctrl(r, v.w.s.wim, de_inst, de_cwp, v.a.wovf, v.a.wunf, de_wcwp);
rs1_gen(r, de_inst, v.a.rs1, de_rs1mod);
de_rs2 := de_inst(4 downto 0);
de_raddr1 := "0000000000"; de_raddr2 := "0000000000";
if true then
if de_rs1mod = '1' then
regaddr(r.d.cwp, de_inst(29 downto 26) & v.a.rs1(0), de_raddr1(7 downto 0));
else
regaddr(r.d.cwp, de_inst(18 downto 15) & v.a.rs1(0), de_raddr1(7 downto 0));
end if;
else
regaddr(r.d.cwp, v.a.rs1, de_raddr1(7 downto 0));
end if;
regaddr(r.d.cwp, de_rs2, de_raddr2(7 downto 0));
v.a.rfa1 := de_raddr1(7 downto 0);
v.a.rfa2 := de_raddr2(7 downto 0);
rd_gen(r, de_inst, v.a.ctrl.wreg, v.a.ctrl.ld, de_rd);
regaddr(de_cwp, de_rd, v.a.ctrl.rd);
fpbranch(de_inst, fpo.cc, de_fbranch);
fpbranch(de_inst, cpo.cc, de_cbranch);
v.a.imm := imm_data(r, de_inst);
lock_gen(r, de_rs2, de_rd, v.a.rfa1, v.a.rfa2, v.a.ctrl.rd, de_inst,
fpo.ldlock, v.e.mul, ra_div, v.a.ldcheck1, v.a.ldcheck2, de_ldlock,
v.a.ldchkra, v.a.ldchkex);
ic_ctrl(r, de_inst, v.x.annul_all, de_ldlock, branch_true(de_icc, de_inst),
de_fbranch, de_cbranch, fpo.ccv, cpo.ccv, v.d.cnt, v.d.pc, de_branch,
v.a.ctrl.annul, v.d.annul, v.a.jmpl, de_inull, v.d.pv, v.a.ctrl.pv,
de_hold_pc, v.a.ticc, v.a.ctrl.rett, v.a.mulstart, v.a.divstart);
cwp_gen(r, v, v.a.ctrl.annul, de_wcwp, de_cwp, v.d.cwp);
v.d.inull := ra_inull_gen(r, v);
op_find(r, v.a.ldchkra, v.a.ldchkex, v.a.rs1, v.a.rfa1,
false, v.a.rfe1, v.a.rsel1, v.a.ldcheck1);
op_find(r, v.a.ldchkra, v.a.ldchkex, de_rs2, v.a.rfa2,
imm_select(de_inst), v.a.rfe2, v.a.rsel2, v.a.ldcheck2);
de_branch_address := branch_address(de_inst, r.d.pc);
v.a.ctrl.annul := v.a.ctrl.annul or v.x.annul_all;
v.a.ctrl.wicc := v.a.ctrl.wicc and not v.a.ctrl.annul;
v.a.ctrl.wreg := v.a.ctrl.wreg and not v.a.ctrl.annul;
v.a.ctrl.rett := v.a.ctrl.rett and not v.a.ctrl.annul;
v.a.ctrl.wy := v.a.ctrl.wy and not v.a.ctrl.annul;
v.a.ctrl.trap := r.d.mexc;
v.a.ctrl.tt := "000000";
v.a.ctrl.inst := de_inst;
v.a.ctrl.pc := r.d.pc;
v.a.ctrl.cnt := r.d.cnt;
v.a.step := r.d.step;
if holdn = '0' then
de_raddr1(7 downto 0) := r.a.rfa1;
de_raddr2(7 downto 0) := r.a.rfa2;
de_ren1 := r.a.rfe1; de_ren2 := r.a.rfe2;
else
de_ren1 := v.a.rfe1; de_ren2 := v.a.rfe2;
end if;
if true then
if ((dbgi.denable and not dbgi.dwrite) = '1') and (r.x.rstate = dsu2) then
de_raddr1(7 downto 0) := dbgi.daddr(9 downto 2); de_ren1 := '1';
end if;
v.d.step := dbgi.step and not r.d.annul;
end if;
rfi.raddr1 <= de_raddr1; rfi.raddr2 <= de_raddr2;
rfi.ren1 <= de_ren1 and not dco.scanen;
rfi.ren2 <= de_ren2 and not dco.scanen;
rfi.diag <= dco.testen & "000";
ici.inull <= de_inull;
ici.flush <= me_iflush;
if (xc_rstn = '0') then
v.d.cnt := "00";
if need_extra_sync_reset(fabtech) /= 0 then
v.d.cwp := "000";
end if;
end if;
-----------------------------------------------------------------------
-- FETCH STAGE
-----------------------------------------------------------------------
npc := r.f.pc;
if (xc_rstn = '0') then
v.f.pc := "000000000000000000000000000000"; v.f.branch := '0';
if false then v.f.pc(31 downto 12) := irqi.rstvec;
else
v.f.pc(31 downto 12) := conv_std_logic_vector(rstaddr, 20);
end if;
elsif xc_exception = '1' then -- exception
v.f.branch := '1'; v.f.pc := xc_trap_address;
npc := v.f.pc;
-- elsif (not ra_inull and de_hold_pc) = '1' then
elsif de_hold_pc = '1' then
v.f.pc := r.f.pc; v.f.branch := r.f.branch;
if ex_jump = '1' then
v.f.pc := ex_jump_address; v.f.branch := '1';
npc := v.f.pc;
end if;
elsif ex_jump = '1' then
v.f.pc := ex_jump_address; v.f.branch := '1';
npc := v.f.pc;
elsif de_branch = '1' then
v.f.pc := branch_address(de_inst, r.d.pc); v.f.branch := '1';
npc := v.f.pc;
else
v.f.branch := '0';
v.f.pc(31 downto 2) := r.f.pc(31 downto 2) + 1; -- Address incrementer
npc := v.f.pc;
end if;
ici.dpc <= r.d.pc(31 downto 2) & "00";
ici.fpc <= r.f.pc(31 downto 2) & "00";
ici.rpc <= npc(31 downto 2) & "00";
ici.fbranch <= r.f.branch;
ici.rbranch <= v.f.branch;
ici.su <= v.a.su;
ici.fline <= "00000000000000000000000000000";
ici.flushl <= '0';
if (ico.mds and de_hold_pc) = '0' then
for i in 0 to 2-1 loop
v.d.inst(i) := ico.data(i); -- latch instruction
end loop;
v.d.set := ico.set(0 downto 0); -- latch instruction
v.d.mexc := ico.mexc; -- latch instruction
end if;
-----------------------------------------------------------------------
-----------------------------------------------------------------------
if true then -- DSU diagnostic read
diagread(dbgi, r, dsur, ir, wpr, dco, tbo, diagdata);
diagrdy(dbgi.denable, dsur, r.m.dci, dco.mds, ico, vdsu.crdy);
end if;
-----------------------------------------------------------------------
-- OUTPUTS
-----------------------------------------------------------------------
rin <= v; wprin <= vwpr; dsuin <= vdsu; irin <= vir;
muli.start <= r.a.mulstart and not r.a.ctrl.annul;
muli.signed <= r.e.ctrl.inst(19);
muli.op1 <= (ex_op1(31) and r.e.ctrl.inst(19)) & ex_op1;
muli.op2 <= (mul_op2(31) and r.e.ctrl.inst(19)) & mul_op2;
muli.mac <= r.e.ctrl.inst(24);
if false then muli.acc(39 downto 32) <= r.w.s.y(7 downto 0);
else muli.acc(39 downto 32) <= r.x.y(7 downto 0); end if;
muli.acc(31 downto 0) <= r.w.s.asr18;
muli.flush <= r.x.annul_all;
divi.start <= r.a.divstart and not r.a.ctrl.annul;
divi.signed <= r.e.ctrl.inst(19);
divi.flush <= r.x.annul_all;
divi.op1 <= (ex_op1(31) and r.e.ctrl.inst(19)) & ex_op1;
divi.op2 <= (ex_op2(31) and r.e.ctrl.inst(19)) & ex_op2;
if (r.a.divstart and not r.a.ctrl.annul) = '1' then
dsign := r.a.ctrl.inst(19);
else dsign := r.e.ctrl.inst(19); end if;
divi.y <= (r.m.y(31) and dsign) & r.m.y;
rpin <= vp;
if true then
dbgo.dsu <= '1'; dbgo.dsumode <= r.x.debug; dbgo.crdy <= dsur.crdy(2);
dbgo.data <= diagdata;
if true then tbi <= tbufi; else
tbi.addr <= (others => '0'); tbi.data <= (others => '0');
tbi.enable <= '0'; tbi.write <= (others => '0'); tbi.diag <= "0000";
end if;
else
dbgo.dsu <= '0'; dbgo.data <= (others => '0'); dbgo.crdy <= '0';
dbgo.dsumode <= '0';
tbi.addr <= (others => '0'); tbi.data <= (others => '0');
tbi.enable <= '0'; tbi.write <= (others => '0'); tbi.diag <= "0000";
end if;
dbgo.error <= dummy and not r.x.nerror;
-- pragma translate_off
if FPEN then
-- pragma translate_on
vfpi.flush := v.x.annul_all; vfpi.exack := xc_fpexack; vfpi.a_rs1 := r.a.rs1; vfpi.d.inst := de_inst;
vfpi.d.cnt := r.d.cnt; vfpi.d.annul := v.x.annul_all or r.d.annul; vfpi.d.trap := r.d.mexc;
vfpi.d.pc(1 downto 0) := (others => '0'); vfpi.d.pc(31 downto 2) := r.d.pc(31 downto 2);
vfpi.d.pv := r.d.pv;
vfpi.a.pc(1 downto 0) := (others => '0'); vfpi.a.pc(31 downto 2) := r.a.ctrl.pc(31 downto 2);
vfpi.a.inst := r.a.ctrl.inst; vfpi.a.cnt := r.a.ctrl.cnt; vfpi.a.trap := r.a.ctrl.trap;
vfpi.a.annul := r.a.ctrl.annul; vfpi.a.pv := r.a.ctrl.pv;
vfpi.e.pc(1 downto 0) := (others => '0'); vfpi.e.pc(31 downto 2) := r.e.ctrl.pc(31 downto 2);
vfpi.e.inst := r.e.ctrl.inst; vfpi.e.cnt := r.e.ctrl.cnt; vfpi.e.trap := r.e.ctrl.trap; vfpi.e.annul := r.e.ctrl.annul;
vfpi.e.pv := r.e.ctrl.pv;
vfpi.m.pc(1 downto 0) := (others => '0'); vfpi.m.pc(31 downto 2) := r.m.ctrl.pc(31 downto 2);
vfpi.m.inst := r.m.ctrl.inst; vfpi.m.cnt := r.m.ctrl.cnt; vfpi.m.trap := r.m.ctrl.trap; vfpi.m.annul := r.m.ctrl.annul;
vfpi.m.pv := r.m.ctrl.pv;
vfpi.x.pc(1 downto 0) := (others => '0'); vfpi.x.pc(31 downto 2) := r.x.ctrl.pc(31 downto 2);
vfpi.x.inst := r.x.ctrl.inst; vfpi.x.cnt := r.x.ctrl.cnt; vfpi.x.trap := xc_trap;
vfpi.x.annul := r.x.ctrl.annul; vfpi.x.pv := r.x.ctrl.pv; vfpi.lddata := xc_df_result;--xc_result;
if r.x.rstate = dsu2 then vfpi.dbg.enable := dbgi.denable;
else vfpi.dbg.enable := '0'; end if;
vfpi.dbg.write := fpcdbgwr;
vfpi.dbg.fsr := dbgi.daddr(22); -- IU reg access
vfpi.dbg.addr := dbgi.daddr(6 downto 2);
vfpi.dbg.data := dbgi.ddata;
fpi <= vfpi;
cpi <= vfpi; -- dummy, just to kill some warnings ...
-- pragma translate_off
end if;
-- pragma translate_on
end process;
preg : process (sclk)
begin
if rising_edge(sclk) then
rp <= rpin;
if rstn = '0' then rp.error <= '0'; end if;
end if;
end process;
reg : process (clk)
begin
if rising_edge(clk) then
if (holdn = '1') then
r <= rin;
else
r.x.ipend <= rin.x.ipend;
r.m.werr <= rin.m.werr;
if (holdn or ico.mds) = '0' then
r.d.inst <= rin.d.inst; r.d.mexc <= rin.d.mexc;
r.d.set <= rin.d.set;
end if;
if (holdn or dco.mds) = '0' then
r.x.data <= rin.x.data; r.x.mexc <= rin.x.mexc;
r.x.set <= rin.x.set;
end if;
end if;
if rstn = '0' then
r.w.s.s <= '1'; r.w.s.ps <= '1';
if need_extra_sync_reset(fabtech) /= 0 then
r.d.inst <= (others => (others => '0'));
r.x.mexc <= '0';
end if;
end if;
end if;
end process;
dsureg : process(clk) begin
if rising_edge(clk) then
if holdn = '1' then
dsur <= dsuin;
else
dsur.crdy <= dsuin.crdy;
end if;
if holdn = '1' then ir <= irin; end if;
end if;
end process;
dummy <= '1';
end;
| mit | 295b6630e7c77677707abd56e7e6fb52 | 0.531733 | 3.054294 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/pci/pci_target.vhd | 2 | 13,863 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: pci_target
-- File: pci_target.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Simple PCI target interface
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.pci.all;
use gaisler.misc.all;
entity pci_target is
generic (
hindex : integer := 0;
abits : integer := 21;
device_id : integer := 0; -- PCI device ID
vendor_id : integer := 0; -- PCI vendor ID
nsync : integer range 1 to 2 := 1; -- 1 or 2 sync regs between clocks
oepol : integer := 0);
port(
rst : in std_logic;
clk : in std_logic;
pciclk : in std_logic;
pcii : in pci_in_type;
pcio : out pci_out_type;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type
);
end;
architecture rtl of pci_target is
constant REVISION : amba_version_type := 0;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg(VENDOR_GAISLER, GAISLER_PCITRG, 0, REVISION, 0),
others => zero32);
constant CSYNC : integer := nsync-1;
constant MADDR_WIDTH : integer := abits;
constant zero : std_logic_vector(31 downto 0) := (others => '0');
subtype word4 is std_logic_vector(3 downto 0);
subtype word32 is std_logic_vector(31 downto 0);
constant pci_memory_read : word4 := "0110";
constant pci_memory_write : word4 := "0111";
constant pci_config_read : word4 := "1010";
constant pci_config_write : word4 := "1011";
type pci_input_type is record
ad : std_logic_vector(31 downto 0);
cbe : std_logic_vector(3 downto 0);
frame : std_logic;
devsel : std_logic;
idsel : std_logic;
trdy : std_logic;
irdy : std_logic;
par : std_logic;
stop : std_logic;
rst : std_logic;
end record;
type pci_target_state_type is (idle, b_busy, s_data, backoff, turn_ar);
type pci_reg_type is record
addr : std_logic_vector(MADDR_WIDTH-1 downto 0);
data : std_logic_vector(31 downto 0);
cmd : std_logic_vector(3 downto 0);
state : pci_target_state_type;
csel : std_logic;
msel : std_logic;
read : std_logic;
devsel : std_logic;
trdy : std_logic;
stop : std_logic;
par : std_logic;
oe_par : std_logic;
oe_ad : std_logic;
oe_ctrl : std_logic;
noe_par : std_logic;
noe_ad : std_logic;
noe_ctrl : std_logic;
bar0 : std_logic_vector(31 downto MADDR_WIDTH);
page : std_logic_vector(31 downto MADDR_WIDTH-1);
men : std_logic;
laddr : std_logic_vector(31 downto 0);
ldata : std_logic_vector(31 downto 0);
lwrite : std_logic;
start : std_logic;
rready : std_logic_vector(csync downto 0);
wready : std_logic_vector(csync downto 0);
sync : std_logic_vector(csync downto 0);
end record;
type cpu_state_type is (idle, sync1, busy, sync2);
type cpu_reg_type is record
data : std_logic_vector(31 downto 0);
state : cpu_state_type;
start : std_logic_vector(csync downto 0);
sync : std_logic;
rready : std_logic;
wready : std_logic;
end record;
signal clk_int : std_logic;
signal pr : pci_input_type;
signal r, rin : pci_reg_type;
signal r2, r2in : cpu_reg_type;
signal dmai : ahb_dma_in_type;
signal dmao : ahb_dma_out_type;
signal roe_ad, rioe_ad : std_logic_vector(31 downto 0);
attribute syn_preserve : boolean;
attribute syn_preserve of roe_ad : signal is true;
begin
-- Back-end state machine (AHB clock domain)
comb : process (rst, r2, r, dmao)
variable vdmai : ahb_dma_in_type;
variable v : cpu_reg_type;
begin
v := r2;
vdmai.start := '0'; vdmai.burst := '0'; vdmai.size := "10";
vdmai.address := r.laddr; v.sync := '1';
vdmai.wdata := r.ldata; vdmai.write := r.lwrite; vdmai.irq := '0';
v.start(0) := r2.start(csync); v.start(csync) := r.start;
case r2.state is
when idle =>
v.sync := '0';
if r2.start(0) = '1' then
if r.lwrite = '1' then v.state := sync1; v.wready := '0';
else v.state := busy; vdmai.start := '1'; end if;
end if;
when sync1 =>
if r2.start(0) = '0' then v.state := busy; vdmai.start := '1'; end if;
when busy =>
if dmao.active = '1' then
if dmao.ready = '1' then
v.rready := not r.lwrite; v.data := dmao.rdata; v.state := sync2;
end if;
else vdmai.start := '1'; end if;
when sync2 =>
if r2.start(0) = '0' then
v.state := idle; v.wready := '1'; v.rready := '0';
end if;
end case;
if rst = '0' then
v.state := idle; v.rready := '0'; v.wready := '1';
end if;
r2in <= v; dmai <= vdmai;
end process;
-- PCI target core (PCI clock domain)
pcicomb : process(pr, pcii, r, r2, roe_ad)
variable v : pci_reg_type;
variable chit, mhit, hit, ready, cwrite, mwrite : std_logic;
variable cdata, cwdata : std_logic_vector(31 downto 0);
variable caddr : std_logic_vector(7 downto 2);
variable voe_ad : std_logic_vector(31 downto 0);
variable oe_ctrl, oe_par, oe_ad : std_ulogic;
begin
v := r; v.trdy := '1'; v.stop := '1'; voe_ad := roe_ad;
v.oe_ad := '1'; v.devsel := '1'; mwrite := '0';
v.rready(0) := r.rready(csync); v.rready(csync) := r2.rready;
v.wready(0) := r.wready(csync); v.wready(csync) := r2.wready;
v.sync(0) := r.sync(csync); v.sync(csync) := r2.sync;
-- address decoding
if (r.state = s_data) and ((pr.irdy or r.trdy or r.read) = '0') then
cwrite := r.csel;
if ((r.msel and r.addr(MADDR_WIDTH-1)) = '1') and (pr.cbe = "0000") then
v.page := pr.ad(31 downto MADDR_WIDTH-1);
end if;
if (pr.cbe = "0000") and (r.addr(MADDR_WIDTH-1) = '1') then
mwrite := r.msel;
end if;
else cwrite := '0'; end if;
cdata := (others => '0'); caddr := r.addr(7 downto 2);
case caddr is
when "000000" => -- 0x00, device & vendor id
cdata := conv_std_logic_vector(DEVICE_ID, 16) &
conv_std_logic_vector(VENDOR_ID, 16);
when "000001" => -- 0x04, status & command
cdata(1) := r.men; cdata(26) := '1';
when "000010" => -- 0x08, class code & revision
when "000011" => -- 0x0c, latency & cacheline size
when "000100" => -- 0x10, BAR0
cdata(31 downto MADDR_WIDTH) := r.bar0;
when others =>
end case;
cwdata := pr.ad;
if pr.cbe(3) = '1' then cwdata(31 downto 24) := cdata(31 downto 24); end if;
if pr.cbe(2) = '1' then cwdata(23 downto 16) := cdata(23 downto 16); end if;
if pr.cbe(1) = '1' then cwdata(15 downto 8) := cdata(15 downto 8); end if;
if pr.cbe(0) = '1' then cwdata( 7 downto 0) := cdata( 7 downto 0); end if;
if cwrite = '1' then
case caddr is
when "000001" => -- 0x04, status & command
v.men := cwdata(1);
when "000100" => -- 0x10, BAR0
v.bar0 := cwdata(31 downto MADDR_WIDTH);
when others =>
end case;
end if;
if (((pr.cbe = pci_config_read) or (pr.cbe = pci_config_write))
and (pr.ad(1 downto 0) = "00"))
then chit := '1'; else chit := '0'; end if;
if ((pr.cbe = pci_memory_read) or (pr.cbe = pci_memory_write))
and (r.bar0 = pr.ad(31 downto MADDR_WIDTH))
and (r.bar0 /= zero(31 downto MADDR_WIDTH))
then mhit := '1'; else mhit := '0'; end if;
hit := r.csel or r.msel;
ready := r.csel or (r.rready(0) and r.read) or (r.wready(0) and not r.read and not r.start) or
r.addr(MADDR_WIDTH-1);
-- target state machine
case r.state is
when idle =>
if pr.frame = '0' then v.state := b_busy; end if; -- !HIT ?
v.addr := pr.ad(MADDR_WIDTH-1 downto 0); v.cmd := pr.cbe;
v.csel := pr.idsel and chit;
v.msel := r.men and mhit; v.read := not pr.cbe(0);
if (r.sync(0) and r.start and r.lwrite) = '1' then v.start := '0'; end if;
when turn_ar =>
if pr.frame = '1' then v.state := idle; end if;
if pr.frame = '0' then v.state := b_busy; end if; -- !HIT ?
v.addr := pr.ad(MADDR_WIDTH-1 downto 0); v.cmd := pr.cbe;
v.csel := pr.idsel and chit;
v.msel := r.men and mhit; v.read := not pr.cbe(0);
if (r.sync(0) and r.start and r.lwrite) = '1' then v.start := '0'; end if;
when b_busy =>
if hit = '1' then
v.state := s_data; v.trdy := not ready; v.stop := pr.frame and ready;
v.devsel := '0';
else
v.state := backoff;
end if;
when s_data =>
v.stop := r.stop; v.devsel := '0';
v.trdy := r.trdy or not pcii.irdy;
if (pcii.frame and not pcii.irdy) = '1' then
v.state := turn_ar; v.stop := '1'; v.trdy := '1'; v.devsel := '1';
end if;
when backoff =>
if pr.frame = '1' then v.state := idle; end if;
end case;
if ((r.state = s_data) or (r.state = turn_ar)) and
(((pr.irdy or pr.trdy) = '0') or
((not pr.irdy and not pr.stop and pr.trdy and not r.start and r.wready(0)) = '1'))
then
if (pr.trdy and r.read)= '0' then v.start := '0'; end if;
if (r.start = '0') and ((r.msel and not r.addr(MADDR_WIDTH-1)) = '1') and
(((pr.trdy and r.read and not r.rready(0)) or (not pr.trdy and not r.read)) = '1')
then
v.laddr := r.page & r.addr(MADDR_WIDTH-2 downto 0);
v.ldata := pr.ad; v.lwrite := not r.read; v.start := '1';
end if;
end if;
if (v.state = s_data) and (r.read = '1') then v.oe_ad := '0'; end if;
v.oe_par := r.oe_ad;
if r.csel = '1' then v.data := cdata;
elsif r.addr(MADDR_WIDTH-1) = '1' then
v.data(31 downto MADDR_WIDTH-1) := r.page;
v.data(MADDR_WIDTH-2 downto 0) := (others => '0');
else v.data := r2.data; end if;
v.par := xorv(r.data & pcii.cbe);
if (v.state = s_data) or (r.state = s_data) then
v.oe_ctrl := '0';
else v.oe_ctrl := '1'; end if;
v.noe_ctrl := not v.oe_ctrl; v.noe_ad := not v.oe_ad; v.noe_par := not v.oe_par;
if oepol = 1 then
oe_ctrl := r.noe_ctrl; oe_ad := r.noe_ad; oe_par := r.noe_par;
voe_ad := (others => v.noe_ad);
else
oe_ctrl := r.oe_ctrl; oe_ad := r.oe_ad; oe_par := r.oe_par;
voe_ad := (others => v.oe_ad);
end if;
if pr.rst = '0' then
v.state := idle; v.men := '0'; v.start := '0';
v.bar0 := (others => '0'); v.msel := '0'; v.csel := '0';
v.page := (others => '0');
v.page(31 downto 30) := "01";
end if;
rin <= v;
rioe_ad <= voe_ad;
pcio.ctrlen <= oe_ctrl;
pcio.trdy <= r.trdy;
pcio.trdyen <= oe_ctrl;
pcio.stop <= r.stop;
pcio.stopen <= oe_ctrl;
pcio.devsel <= r.devsel;
pcio.devselen <= oe_ctrl;
pcio.par <= r.par;
pcio.paren <= oe_par;
pcio.aden <= oe_ad;
pcio.ad <= r.data;
end process;
pcir : process (pciclk, pcii.rst, r2)
begin
if rising_edge (pciclk) then
pr.ad <= to_x01(pcii.ad);
pr.cbe <= to_x01(pcii.cbe);
pr.devsel <= to_x01(pcii.devsel);
pr.frame <= to_x01(pcii.frame);
pr.idsel <= to_x01(pcii.idsel);
pr.irdy <= to_x01(pcii.irdy);
pr.trdy <= to_x01(pcii.trdy);
pr.par <= to_x01(pcii.par);
pr.stop <= to_x01(pcii.stop);
pr.rst <= to_x01(pcii.rst);
r <= rin;
roe_ad <= rioe_ad;
end if;
if pcii.rst = '0' then -- asynch reset required
r.oe_ctrl <= '1'; r.oe_par <= '1'; r.oe_ad <= '1';
r.noe_ctrl <= '0'; r.noe_par <= '0'; r.noe_ad <= '0';
if oepol = 0 then roe_ad <= (others => '1');
else roe_ad <= (others => '0'); end if;
end if;
end process;
cpur : process (clk)
begin
if rising_edge (clk) then
r2 <= r2in;
end if;
end process;
oe0 : if oepol = 0 generate
pcio.perren <= '1';
pcio.cbeen <= (others => '1');
pcio.serren <= '1';
pcio.inten <= '1';
pcio.reqen <= not pcii.rst;
pcio.frameen <= '1';
pcio.irdyen <= '1';
pcio.locken <= '1';
end generate;
oe1 : if oepol = 1 generate
pcio.perren <= '0';
pcio.cbeen <= (others => '0');
pcio.serren <= '0';
pcio.inten <= '0';
pcio.reqen <= pcii.rst;
pcio.frameen <= '0';
pcio.irdyen <= '0';
pcio.locken <= '0';
end generate;
pcio.vaden <= roe_ad;
pcio.cbe <= "1111";
pcio.perr <= '1';
pcio.serr <= '1';
pcio.int <= '1';
pcio.req <= '1';
pcio.frame <= '1';
pcio.irdy <= '1';
ahbmst0 : ahbmst generic map (hindex => hindex, devid => GAISLER_PCITRG)
port map (rst, clk, dmai, dmao, ahbmi, ahbmo);
-- pragma translate_off
bootmsg : report_version
generic map ("pci_target" & tost(hindex) &
": 32-bit PCI Target rev " & tost(REVISION) &
", " & tost(abits) & "-bit PCI memory BAR" );
-- pragma translate_on
end;
| mit | 9d0b3f50b3e8e9b38c38229c0ae37da2 | 0.554281 | 2.942063 | false | false | false | false |
cafe-alpha/wascafe | v10/fpga_firmware/wasca/wasca_inst.vhd | 1 | 12,504 | component wasca is
port (
altpll_0_areset_conduit_export : in std_logic := 'X'; -- export
altpll_0_locked_conduit_export : out std_logic; -- export
altpll_0_phasedone_conduit_export : out std_logic; -- export
clk_clk : in std_logic := 'X'; -- clk
clock_116_mhz_clk : out std_logic; -- clk
external_sdram_controller_wire_addr : out std_logic_vector(12 downto 0); -- addr
external_sdram_controller_wire_ba : out std_logic_vector(1 downto 0); -- ba
external_sdram_controller_wire_cas_n : out std_logic; -- cas_n
external_sdram_controller_wire_cke : out std_logic; -- cke
external_sdram_controller_wire_cs_n : out std_logic; -- cs_n
external_sdram_controller_wire_dq : inout std_logic_vector(15 downto 0) := (others => 'X'); -- dq
external_sdram_controller_wire_dqm : out std_logic_vector(1 downto 0); -- dqm
external_sdram_controller_wire_ras_n : out std_logic; -- ras_n
external_sdram_controller_wire_we_n : out std_logic; -- we_n
pio_0_external_connection_export : inout std_logic_vector(3 downto 0) := (others => 'X'); -- export
sd_mmc_controller_0_sd_card_io_sd_clk_o_pad : out std_logic; -- sd_clk_o_pad
sd_mmc_controller_0_sd_card_io_sd_cmd_dat_i : in std_logic := 'X'; -- sd_cmd_dat_i
sd_mmc_controller_0_sd_card_io_sd_cmd_oe_o : out std_logic; -- sd_cmd_oe_o
sd_mmc_controller_0_sd_card_io_sd_cmd_out_o : out std_logic; -- sd_cmd_out_o
sd_mmc_controller_0_sd_card_io_sd_dat_dat_i : in std_logic_vector(3 downto 0) := (others => 'X'); -- sd_dat_dat_i
sd_mmc_controller_0_sd_card_io_sd_dat_oe_o : out std_logic; -- sd_dat_oe_o
sd_mmc_controller_0_sd_card_io_sd_dat_out_o : out std_logic_vector(3 downto 0); -- sd_dat_out_o
sega_saturn_abus_slave_0_abus_address : in std_logic_vector(9 downto 0) := (others => 'X'); -- address
sega_saturn_abus_slave_0_abus_chipselect : in std_logic_vector(2 downto 0) := (others => 'X'); -- chipselect
sega_saturn_abus_slave_0_abus_read : in std_logic := 'X'; -- read
sega_saturn_abus_slave_0_abus_write : in std_logic_vector(1 downto 0) := (others => 'X'); -- write
sega_saturn_abus_slave_0_abus_functioncode : in std_logic_vector(1 downto 0) := (others => 'X'); -- functioncode
sega_saturn_abus_slave_0_abus_timing : in std_logic_vector(2 downto 0) := (others => 'X'); -- timing
sega_saturn_abus_slave_0_abus_waitrequest : out std_logic; -- waitrequest
sega_saturn_abus_slave_0_abus_addressstrobe : in std_logic := 'X'; -- addressstrobe
sega_saturn_abus_slave_0_abus_interrupt : out std_logic; -- interrupt
sega_saturn_abus_slave_0_abus_addressdata : inout std_logic_vector(15 downto 0) := (others => 'X'); -- addressdata
sega_saturn_abus_slave_0_abus_direction : out std_logic; -- direction
sega_saturn_abus_slave_0_abus_muxing : out std_logic_vector(1 downto 0); -- muxing
sega_saturn_abus_slave_0_abus_disableout : out std_logic; -- disableout
sega_saturn_abus_slave_0_conduit_saturn_reset_saturn_reset : in std_logic := 'X'; -- saturn_reset
uart_0_external_connection_rxd : in std_logic := 'X'; -- rxd
uart_0_external_connection_txd : out std_logic -- txd
);
end component wasca;
u0 : component wasca
port map (
altpll_0_areset_conduit_export => CONNECTED_TO_altpll_0_areset_conduit_export, -- altpll_0_areset_conduit.export
altpll_0_locked_conduit_export => CONNECTED_TO_altpll_0_locked_conduit_export, -- altpll_0_locked_conduit.export
altpll_0_phasedone_conduit_export => CONNECTED_TO_altpll_0_phasedone_conduit_export, -- altpll_0_phasedone_conduit.export
clk_clk => CONNECTED_TO_clk_clk, -- clk.clk
clock_116_mhz_clk => CONNECTED_TO_clock_116_mhz_clk, -- clock_116_mhz.clk
external_sdram_controller_wire_addr => CONNECTED_TO_external_sdram_controller_wire_addr, -- external_sdram_controller_wire.addr
external_sdram_controller_wire_ba => CONNECTED_TO_external_sdram_controller_wire_ba, -- .ba
external_sdram_controller_wire_cas_n => CONNECTED_TO_external_sdram_controller_wire_cas_n, -- .cas_n
external_sdram_controller_wire_cke => CONNECTED_TO_external_sdram_controller_wire_cke, -- .cke
external_sdram_controller_wire_cs_n => CONNECTED_TO_external_sdram_controller_wire_cs_n, -- .cs_n
external_sdram_controller_wire_dq => CONNECTED_TO_external_sdram_controller_wire_dq, -- .dq
external_sdram_controller_wire_dqm => CONNECTED_TO_external_sdram_controller_wire_dqm, -- .dqm
external_sdram_controller_wire_ras_n => CONNECTED_TO_external_sdram_controller_wire_ras_n, -- .ras_n
external_sdram_controller_wire_we_n => CONNECTED_TO_external_sdram_controller_wire_we_n, -- .we_n
pio_0_external_connection_export => CONNECTED_TO_pio_0_external_connection_export, -- pio_0_external_connection.export
sd_mmc_controller_0_sd_card_io_sd_clk_o_pad => CONNECTED_TO_sd_mmc_controller_0_sd_card_io_sd_clk_o_pad, -- sd_mmc_controller_0_sd_card_io.sd_clk_o_pad
sd_mmc_controller_0_sd_card_io_sd_cmd_dat_i => CONNECTED_TO_sd_mmc_controller_0_sd_card_io_sd_cmd_dat_i, -- .sd_cmd_dat_i
sd_mmc_controller_0_sd_card_io_sd_cmd_oe_o => CONNECTED_TO_sd_mmc_controller_0_sd_card_io_sd_cmd_oe_o, -- .sd_cmd_oe_o
sd_mmc_controller_0_sd_card_io_sd_cmd_out_o => CONNECTED_TO_sd_mmc_controller_0_sd_card_io_sd_cmd_out_o, -- .sd_cmd_out_o
sd_mmc_controller_0_sd_card_io_sd_dat_dat_i => CONNECTED_TO_sd_mmc_controller_0_sd_card_io_sd_dat_dat_i, -- .sd_dat_dat_i
sd_mmc_controller_0_sd_card_io_sd_dat_oe_o => CONNECTED_TO_sd_mmc_controller_0_sd_card_io_sd_dat_oe_o, -- .sd_dat_oe_o
sd_mmc_controller_0_sd_card_io_sd_dat_out_o => CONNECTED_TO_sd_mmc_controller_0_sd_card_io_sd_dat_out_o, -- .sd_dat_out_o
sega_saturn_abus_slave_0_abus_address => CONNECTED_TO_sega_saturn_abus_slave_0_abus_address, -- sega_saturn_abus_slave_0_abus.address
sega_saturn_abus_slave_0_abus_chipselect => CONNECTED_TO_sega_saturn_abus_slave_0_abus_chipselect, -- .chipselect
sega_saturn_abus_slave_0_abus_read => CONNECTED_TO_sega_saturn_abus_slave_0_abus_read, -- .read
sega_saturn_abus_slave_0_abus_write => CONNECTED_TO_sega_saturn_abus_slave_0_abus_write, -- .write
sega_saturn_abus_slave_0_abus_functioncode => CONNECTED_TO_sega_saturn_abus_slave_0_abus_functioncode, -- .functioncode
sega_saturn_abus_slave_0_abus_timing => CONNECTED_TO_sega_saturn_abus_slave_0_abus_timing, -- .timing
sega_saturn_abus_slave_0_abus_waitrequest => CONNECTED_TO_sega_saturn_abus_slave_0_abus_waitrequest, -- .waitrequest
sega_saturn_abus_slave_0_abus_addressstrobe => CONNECTED_TO_sega_saturn_abus_slave_0_abus_addressstrobe, -- .addressstrobe
sega_saturn_abus_slave_0_abus_interrupt => CONNECTED_TO_sega_saturn_abus_slave_0_abus_interrupt, -- .interrupt
sega_saturn_abus_slave_0_abus_addressdata => CONNECTED_TO_sega_saturn_abus_slave_0_abus_addressdata, -- .addressdata
sega_saturn_abus_slave_0_abus_direction => CONNECTED_TO_sega_saturn_abus_slave_0_abus_direction, -- .direction
sega_saturn_abus_slave_0_abus_muxing => CONNECTED_TO_sega_saturn_abus_slave_0_abus_muxing, -- .muxing
sega_saturn_abus_slave_0_abus_disableout => CONNECTED_TO_sega_saturn_abus_slave_0_abus_disableout, -- .disableout
sega_saturn_abus_slave_0_conduit_saturn_reset_saturn_reset => CONNECTED_TO_sega_saturn_abus_slave_0_conduit_saturn_reset_saturn_reset, -- sega_saturn_abus_slave_0_conduit_saturn_reset.saturn_reset
uart_0_external_connection_rxd => CONNECTED_TO_uart_0_external_connection_rxd, -- uart_0_external_connection.rxd
uart_0_external_connection_txd => CONNECTED_TO_uart_0_external_connection_txd -- .txd
);
| gpl-2.0 | 670de048d7bcd21b9ee5eaaa4a32445b | 0.428343 | 4.325147 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/memAttack/lib/gaisler/leon3/iu3.vhd | 1 | 113,152 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: iu3
-- File: iu3.vhd
-- Author: Jiri Gaisler, Edvin Catovic, Gaisler Research
-- Description: LEON3 7-stage integer pipline
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.sparc.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.leon3.all;
use gaisler.libiu.all;
use gaisler.arith.all;
-- pragma translate_off
use grlib.sparc_disas.all;
-- pragma translate_on
entity iu3 is
generic (
nwin : integer range 2 to 32 := 8;
isets : integer range 1 to 4 := 1;
dsets : integer range 1 to 4 := 1;
fpu : integer range 0 to 15 := 0;
v8 : integer range 0 to 63 := 0;
cp, mac : integer range 0 to 1 := 0;
dsu : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
index : integer range 0 to 15:= 0;
lddel : integer range 1 to 2 := 2;
irfwt : integer range 0 to 1 := 0;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0; -- trace buf size in kB (0 - no trace buffer)
pwd : integer range 0 to 2 := 0; -- power-down
svt : integer range 0 to 1 := 0; -- single-vector trapping
rstaddr : integer := 16#00000#; -- reset vector MSB address
smp : integer range 0 to 15 := 0; -- support SMP systems
fabtech : integer range 0 to NTECH := 0;
clk2x : integer := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
holdn : in std_ulogic;
ici : out icache_in_type;
ico : in icache_out_type;
dci : out dcache_in_type;
dco : in dcache_out_type;
rfi : out iregfile_in_type;
rfo : in iregfile_out_type;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
muli : out mul32_in_type;
mulo : in mul32_out_type;
divi : out div32_in_type;
divo : in div32_out_type;
fpo : in fpc_out_type;
fpi : out fpc_in_type;
cpo : in fpc_out_type;
cpi : out fpc_in_type;
tbo : in tracebuf_out_type;
tbi : out tracebuf_in_type;
sclk : in std_ulogic
);
end;
architecture rtl of iu3 is
constant ISETMSB : integer := log2x(isets)-1;
constant DSETMSB : integer := log2x(dsets)-1;
constant RFBITS : integer range 6 to 10 := log2(NWIN+1) + 4;
constant NWINLOG2 : integer range 1 to 5 := log2(NWIN);
constant CWPOPT : boolean := (NWIN = (2**NWINLOG2));
constant CWPMIN : std_logic_vector(NWINLOG2-1 downto 0) := (others => '0');
constant CWPMAX : std_logic_vector(NWINLOG2-1 downto 0) :=
conv_std_logic_vector(NWIN-1, NWINLOG2);
constant FPEN : boolean := (fpu /= 0);
constant CPEN : boolean := (cp = 1);
constant MULEN : boolean := (v8 /= 0);
constant MULTYPE: integer := (v8 / 16);
constant DIVEN : boolean := (v8 /= 0);
constant MACEN : boolean := (mac = 1);
constant MACPIPE: boolean := (mac = 1) and (v8/2 = 1);
constant IMPL : integer := 15;
constant VER : integer := 3;
constant DBGUNIT : boolean := (dsu = 1);
constant TRACEBUF : boolean := (tbuf /= 0);
constant TBUFBITS : integer := 10 + log2(tbuf) - 4;
constant PWRD1 : boolean := false; --(pwd = 1) and not (index /= 0);
constant PWRD2 : boolean := pwd /= 0; --(pwd = 2) or (index /= 0);
constant RS1OPT : boolean := (is_fpga(FABTECH) /= 0);
subtype word is std_logic_vector(31 downto 0);
subtype pctype is std_logic_vector(31 downto PCLOW);
subtype rfatype is std_logic_vector(RFBITS-1 downto 0);
subtype cwptype is std_logic_vector(NWINLOG2-1 downto 0);
type icdtype is array (0 to isets-1) of word;
type dcdtype is array (0 to dsets-1) of word;
type dc_in_type is record
signed, enaddr, read, write, lock , dsuen : std_ulogic;
size : std_logic_vector(1 downto 0);
asi : std_logic_vector(7 downto 0);
end record;
type pipeline_ctrl_type is record
pc : pctype;
inst : word;
cnt : std_logic_vector(1 downto 0);
rd : rfatype;
tt : std_logic_vector(5 downto 0);
trap : std_ulogic;
annul : std_ulogic;
wreg : std_ulogic;
wicc : std_ulogic;
wy : std_ulogic;
ld : std_ulogic;
pv : std_ulogic;
rett : std_ulogic;
end record;
type fetch_reg_type is record
pc : pctype;
branch : std_ulogic;
end record;
type decode_reg_type is record
pc : pctype;
inst : icdtype;
cwp : cwptype;
set : std_logic_vector(ISETMSB downto 0);
mexc : std_ulogic;
cnt : std_logic_vector(1 downto 0);
pv : std_ulogic;
annul : std_ulogic;
inull : std_ulogic;
step : std_ulogic;
end record;
type regacc_reg_type is record
ctrl : pipeline_ctrl_type;
rs1 : std_logic_vector(4 downto 0);
rfa1, rfa2 : rfatype;
rsel1, rsel2 : std_logic_vector(2 downto 0);
rfe1, rfe2 : std_ulogic;
cwp : cwptype;
imm : word;
ldcheck1 : std_ulogic;
ldcheck2 : std_ulogic;
ldchkra : std_ulogic;
ldchkex : std_ulogic;
su : std_ulogic;
et : std_ulogic;
wovf : std_ulogic;
wunf : std_ulogic;
ticc : std_ulogic;
jmpl : std_ulogic;
step : std_ulogic;
mulstart : std_ulogic;
divstart : std_ulogic;
end record;
type execute_reg_type is record
ctrl : pipeline_ctrl_type;
op1 : word;
op2 : word;
aluop : std_logic_vector(2 downto 0); -- Alu operation
alusel : std_logic_vector(1 downto 0); -- Alu result select
aluadd : std_ulogic;
alucin : std_ulogic;
ldbp1, ldbp2 : std_ulogic;
invop2 : std_ulogic;
shcnt : std_logic_vector(4 downto 0); -- shift count
sari : std_ulogic; -- shift msb
shleft : std_ulogic; -- shift left/right
ymsb : std_ulogic; -- shift left/right
rd : std_logic_vector(4 downto 0);
jmpl : std_ulogic;
su : std_ulogic;
et : std_ulogic;
cwp : cwptype;
icc : std_logic_vector(3 downto 0);
mulstep: std_ulogic;
mul : std_ulogic;
mac : std_ulogic;
end record;
type memory_reg_type is record
ctrl : pipeline_ctrl_type;
result : word;
y : word;
icc : std_logic_vector(3 downto 0);
nalign : std_ulogic;
dci : dc_in_type;
werr : std_ulogic;
wcwp : std_ulogic;
irqen : std_ulogic;
irqen2 : std_ulogic;
mac : std_ulogic;
divz : std_ulogic;
su : std_ulogic;
mul : std_ulogic;
end record;
type exception_state is (run, trap, dsu1, dsu2);
type exception_reg_type is record
ctrl : pipeline_ctrl_type;
result : word;
y : word;
icc : std_logic_vector( 3 downto 0);
annul_all : std_ulogic;
data : dcdtype;
set : std_logic_vector(DSETMSB downto 0);
mexc : std_ulogic;
dci : dc_in_type;
laddr : std_logic_vector(1 downto 0);
rstate : exception_state;
npc : std_logic_vector(2 downto 0);
intack : std_ulogic;
ipend : std_ulogic;
mac : std_ulogic;
debug : std_ulogic;
nerror : std_ulogic;
end record;
type dsu_registers is record
tt : std_logic_vector(7 downto 0);
err : std_ulogic;
tbufcnt : std_logic_vector(TBUFBITS-1 downto 0);
asi : std_logic_vector(7 downto 0);
crdy : std_logic_vector(2 downto 1); -- diag cache access ready
end record;
type irestart_register is record
addr : pctype;
pwd : std_ulogic;
end record;
type pwd_register_type is record
pwd : std_ulogic;
error : std_ulogic;
end record;
type special_register_type is record
cwp : cwptype; -- current window pointer
icc : std_logic_vector(3 downto 0); -- integer condition codes
tt : std_logic_vector(7 downto 0); -- trap type
tba : std_logic_vector(19 downto 0); -- trap base address
wim : std_logic_vector(NWIN-1 downto 0); -- window invalid mask
pil : std_logic_vector(3 downto 0); -- processor interrupt level
ec : std_ulogic; -- enable CP
ef : std_ulogic; -- enable FP
ps : std_ulogic; -- previous supervisor flag
s : std_ulogic; -- supervisor flag
et : std_ulogic; -- enable traps
y : word;
asr18 : word;
svt : std_ulogic; -- enable traps
dwt : std_ulogic; -- disable write error trap
end record;
type write_reg_type is record
s : special_register_type;
result : word;
wa : rfatype;
wreg : std_ulogic;
except : std_ulogic;
end record;
type registers is record
f : fetch_reg_type;
d : decode_reg_type;
a : regacc_reg_type;
e : execute_reg_type;
m : memory_reg_type;
x : exception_reg_type;
w : write_reg_type;
end record;
type exception_type is record
pri : std_ulogic;
ill : std_ulogic;
fpdis : std_ulogic;
cpdis : std_ulogic;
wovf : std_ulogic;
wunf : std_ulogic;
ticc : std_ulogic;
end record;
type watchpoint_register is record
addr : std_logic_vector(31 downto 2); -- watchpoint address
mask : std_logic_vector(31 downto 2); -- watchpoint mask
exec : std_ulogic; -- trap on instruction
load : std_ulogic; -- trap on load
store : std_ulogic; -- trap on store
end record;
type watchpoint_registers is array (0 to 3) of watchpoint_register;
constant wpr_none : watchpoint_register := (
zero32(31 downto 2), zero32(31 downto 2), '0', '0', '0');
function dbgexc(r : registers; dbgi : l3_debug_in_type; trap : std_ulogic; tt : std_logic_vector(7 downto 0)) return std_ulogic is
variable dmode : std_ulogic;
begin
dmode := '0';
if (not r.x.ctrl.annul and trap) = '1' then
if (((tt = "00" & TT_WATCH) and (dbgi.bwatch = '1')) or
((dbgi.bsoft = '1') and (tt = "10000001")) or
(dbgi.btrapa = '1') or
((dbgi.btrape = '1') and not ((tt(5 downto 0) = TT_PRIV) or
(tt(5 downto 0) = TT_FPDIS) or (tt(5 downto 0) = TT_WINOF) or
(tt(5 downto 0) = TT_WINUF) or (tt(5 downto 4) = "01") or (tt(7) = '1'))) or
(((not r.w.s.et) and dbgi.berror) = '1')) then
dmode := '1';
end if;
end if;
return(dmode);
end;
function dbgerr(r : registers; dbgi : l3_debug_in_type;
tt : std_logic_vector(7 downto 0))
return std_ulogic is
variable err : std_ulogic;
begin
err := not r.w.s.et;
if (((dbgi.dbreak = '1') and (tt = ("00" & TT_WATCH))) or
((dbgi.bsoft = '1') and (tt = ("10000001")))) then
err := '0';
end if;
return(err);
end;
procedure diagwr(r : in registers;
dsur : in dsu_registers;
ir : in irestart_register;
dbg : in l3_debug_in_type;
wpr : in watchpoint_registers;
s : out special_register_type;
vwpr : out watchpoint_registers;
asi : out std_logic_vector(7 downto 0);
pc, npc : out pctype;
tbufcnt : out std_logic_vector(TBUFBITS-1 downto 0);
wr : out std_ulogic;
addr : out std_logic_vector(9 downto 0);
data : out word;
fpcwr : out std_ulogic) is
variable i : integer range 0 to 3;
begin
s := r.w.s; pc := r.f.pc; npc := ir.addr; wr := '0';
vwpr := wpr; asi := dsur.asi; addr := (others => '0');
data := dbg.ddata;
tbufcnt := dsur.tbufcnt; fpcwr := '0';
if (dbg.dsuen and dbg.denable and dbg.dwrite) = '1' then
case dbg.daddr(23 downto 20) is
when "0001" =>
if dbg.daddr(16) = '1' then -- trace buffer control reg
tbufcnt := dbg.ddata(TBUFBITS-1 downto 0);
end if;
when "0011" => -- IU reg file
if dbg.daddr(12) = '0' then
wr := '1';
addr := (others => '0');
addr(RFBITS-1 downto 0) := dbg.daddr(RFBITS+1 downto 2);
else -- FPC
fpcwr := '1';
end if;
when "0100" => -- IU special registers
case dbg.daddr(7 downto 6) is
when "00" => -- IU regs Y - TBUF ctrl reg
case dbg.daddr(5 downto 2) is
when "0000" => -- Y
s.y := dbg.ddata;
when "0001" => -- PSR
s.cwp := dbg.ddata(NWINLOG2-1 downto 0);
s.icc := dbg.ddata(23 downto 20);
s.ec := dbg.ddata(13);
if FPEN then s.ef := dbg.ddata(12); end if;
s.pil := dbg.ddata(11 downto 8);
s.s := dbg.ddata(7);
s.ps := dbg.ddata(6);
s.et := dbg.ddata(5);
when "0010" => -- WIM
s.wim := dbg.ddata(NWIN-1 downto 0);
when "0011" => -- TBR
s.tba := dbg.ddata(31 downto 12);
s.tt := dbg.ddata(11 downto 4);
when "0100" => -- PC
pc := dbg.ddata(31 downto PCLOW);
when "0101" => -- NPC
npc := dbg.ddata(31 downto PCLOW);
when "0110" => --FSR
fpcwr := '1';
when "0111" => --CFSR
when "1001" => -- ASI reg
asi := dbg.ddata(7 downto 0);
--when "1001" => -- TBUF ctrl reg
-- tbufcnt := dbg.ddata(TBUFBITS-1 downto 0);
when others =>
end case;
when "01" => -- ASR16 - ASR31
case dbg.daddr(5 downto 2) is
when "0001" => -- %ASR17
s.dwt := dbg.ddata(14);
s.svt := dbg.ddata(13);
when "0010" => -- %ASR18
if MACEN then s.asr18 := dbg.ddata; end if;
when "1000" => -- %ASR24 - %ASR31
vwpr(0).addr := dbg.ddata(31 downto 2);
vwpr(0).exec := dbg.ddata(0);
when "1001" =>
vwpr(0).mask := dbg.ddata(31 downto 2);
vwpr(0).load := dbg.ddata(1);
vwpr(0).store := dbg.ddata(0);
when "1010" =>
vwpr(1).addr := dbg.ddata(31 downto 2);
vwpr(1).exec := dbg.ddata(0);
when "1011" =>
vwpr(1).mask := dbg.ddata(31 downto 2);
vwpr(1).load := dbg.ddata(1);
vwpr(1).store := dbg.ddata(0);
when "1100" =>
vwpr(2).addr := dbg.ddata(31 downto 2);
vwpr(2).exec := dbg.ddata(0);
when "1101" =>
vwpr(2).mask := dbg.ddata(31 downto 2);
vwpr(2).load := dbg.ddata(1);
vwpr(2).store := dbg.ddata(0);
when "1110" =>
vwpr(3).addr := dbg.ddata(31 downto 2);
vwpr(3).exec := dbg.ddata(0);
when "1111" => --
vwpr(3).mask := dbg.ddata(31 downto 2);
vwpr(3).load := dbg.ddata(1);
vwpr(3).store := dbg.ddata(0);
when others => --
end case;
-- disabled due to bug in XST
-- i := conv_integer(dbg.daddr(4 downto 3));
-- if dbg.daddr(2) = '0' then
-- vwpr(i).addr := dbg.ddata(31 downto 2);
-- vwpr(i).exec := dbg.ddata(0);
-- else
-- vwpr(i).mask := dbg.ddata(31 downto 2);
-- vwpr(i).load := dbg.ddata(1);
-- vwpr(i).store := dbg.ddata(0);
-- end if;
when others =>
end case;
when others =>
end case;
end if;
end;
function asr17_gen ( r : in registers) return word is
variable asr17 : word;
variable fpu2 : integer range 0 to 3;
begin
asr17 := zero32;
asr17(31 downto 28) := conv_std_logic_vector(index, 4);
if (clk2x > 8) then
asr17(16 downto 15) := conv_std_logic_vector(clk2x-8, 2);
asr17(17) := '1';
elsif (clk2x > 0) then
asr17(16 downto 15) := conv_std_logic_vector(clk2x, 2);
end if;
asr17(14) := r.w.s.dwt;
if svt = 1 then asr17(13) := r.w.s.svt; end if;
if lddel = 2 then asr17(12) := '1'; end if;
if (fpu > 0) and (fpu < 8) then fpu2 := 1;
elsif (fpu >= 8) and (fpu < 15) then fpu2 := 3;
elsif fpu = 15 then fpu2 := 2;
else fpu2 := 0; end if;
asr17(11 downto 10) := conv_std_logic_vector(fpu2, 2);
if mac = 1 then asr17(9) := '1'; end if;
if v8 /= 0 then asr17(8) := '1'; end if;
asr17(7 downto 5) := conv_std_logic_vector(nwp, 3);
asr17(4 downto 0) := conv_std_logic_vector(nwin-1, 5);
return(asr17);
end;
procedure diagread(dbgi : in l3_debug_in_type;
r : in registers;
dsur : in dsu_registers;
ir : in irestart_register;
wpr : in watchpoint_registers;
rfdata : in std_logic_vector(31 downto 0);
dco : in dcache_out_type;
tbufo : in tracebuf_out_type;
data : out word) is
variable cwp : std_logic_vector(4 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable i : integer range 0 to 3;
begin
data := (others => '0'); cwp := (others => '0');
cwp(NWINLOG2-1 downto 0) := r.w.s.cwp;
case dbgi.daddr(22 downto 20) is
when "001" => -- trace buffer
if dbgi.daddr(16) = '1' then -- trace buffer control reg
data(TBUFBITS-1 downto 0) := dsur.tbufcnt;
else
case dbgi.daddr(3 downto 2) is
when "00" => data := tbufo.data(127 downto 96);
when "01" => data := tbufo.data(95 downto 64);
when "10" => data := tbufo.data(63 downto 32);
when others => data := tbufo.data(31 downto 0);
end case;
end if;
when "011" => -- IU reg file
if dbgi.daddr(12) = '0' then data := rfdata(31 downto 0);
else data := fpo.dbg.data; end if;
when "100" => -- IU regs
case dbgi.daddr(7 downto 6) is
when "00" => -- IU regs Y - TBUF ctrl reg
case dbgi.daddr(5 downto 2) is
when "0000" =>
data := r.w.s.y;
when "0001" =>
data := conv_std_logic_vector(IMPL, 4) & conv_std_logic_vector(VER, 4) &
r.w.s.icc & "000000" & r.w.s.ec & r.w.s.ef & r.w.s.pil &
r.w.s.s & r.w.s.ps & r.w.s.et & cwp;
when "0010" =>
data(NWIN-1 downto 0) := r.w.s.wim;
when "0011" =>
data := r.w.s.tba & r.w.s.tt & "0000";
when "0100" =>
data(31 downto PCLOW) := r.f.pc;
when "0101" =>
data(31 downto PCLOW) := ir.addr;
when "0110" => -- FSR
data := fpo.dbg.data;
when "0111" => -- CPSR
when "1000" => -- TT reg
data(12 downto 4) := dsur.err & dsur.tt;
when "1001" => -- ASI reg
data(7 downto 0) := dsur.asi;
when others =>
end case;
when "01" =>
if dbgi.daddr(5) = '0' then -- %ASR17
if dbgi.daddr(4 downto 2) = "001" then -- %ASR17
data := asr17_gen(r);
elsif MACEN and dbgi.daddr(4 downto 2) = "010" then -- %ASR18
data := r.w.s.asr18;
end if;
else -- %ASR24 - %ASR31
i := conv_integer(dbgi.daddr(4 downto 3)); --
if dbgi.daddr(2) = '0' then
data(31 downto 2) := wpr(i).addr;
data(0) := wpr(i).exec;
else
data(31 downto 2) := wpr(i).mask;
data(1) := wpr(i).load;
data(0) := wpr(i).store;
end if;
end if;
when others =>
end case;
when "111" =>
data := r.x.data(conv_integer(r.x.set));
when others =>
end case;
end;
procedure itrace(r : in registers;
dsur : in dsu_registers;
vdsu : in dsu_registers;
res : in word;
exc : in std_ulogic;
dbgi : in l3_debug_in_type;
error : in std_ulogic;
trap : in std_ulogic;
tbufcnt : out std_logic_vector(TBUFBITS-1 downto 0);
di : out tracebuf_in_type) is
variable meminst : std_ulogic;
begin
di.addr := (others => '0'); di.data := (others => '0');
di.enable := '0'; di.write := (others => '0');
tbufcnt := vdsu.tbufcnt;
meminst := r.x.ctrl.inst(31) and r.x.ctrl.inst(30);
if TRACEBUF then
di.addr(TBUFBITS-1 downto 0) := dsur.tbufcnt;
di.data(127) := '0';
di.data(126) := not r.x.ctrl.pv;
di.data(125 downto 96) := dbgi.timer(29 downto 0);
di.data(95 downto 64) := res;
di.data(63 downto 34) := r.x.ctrl.pc(31 downto 2);
di.data(33) := trap;
di.data(32) := error;
di.data(31 downto 0) := r.x.ctrl.inst;
if (dbgi.tenable = '0') or (r.x.rstate = dsu2) then
if ((dbgi.dsuen and dbgi.denable) = '1') and (dbgi.daddr(23 downto 20) & dbgi.daddr(16) = "00010") then
di.enable := '1';
di.addr(TBUFBITS-1 downto 0) := dbgi.daddr(TBUFBITS-1+4 downto 4);
if dbgi.dwrite = '1' then
case dbgi.daddr(3 downto 2) is
when "00" => di.write(3) := '1';
when "01" => di.write(2) := '1';
when "10" => di.write(1) := '1';
when others => di.write(0) := '1';
end case;
di.data := dbgi.ddata & dbgi.ddata & dbgi.ddata & dbgi.ddata;
end if;
end if;
elsif (not r.x.ctrl.annul and (r.x.ctrl.pv or meminst) and not r.x.debug) = '1' then
di.enable := '1'; di.write := (others => '1');
tbufcnt := dsur.tbufcnt + 1;
end if;
di.diag := dco.testen & "000";
if dco.scanen = '1' then di.enable := '0'; end if;
end if;
end;
procedure dbg_cache(holdn : in std_ulogic;
dbgi : in l3_debug_in_type;
r : in registers;
dsur : in dsu_registers;
mresult : in word;
dci : in dc_in_type;
mresult2 : out word;
dci2 : out dc_in_type
) is
begin
mresult2 := mresult; dci2 := dci; dci2.dsuen := '0';
if DBGUNIT then
if r.x.rstate = dsu2 then
dci2.asi := dsur.asi;
if (dbgi.daddr(22 downto 20) = "111") and (dbgi.dsuen = '1') then
dci2.dsuen := (dbgi.denable or r.m.dci.dsuen) and not dsur.crdy(2);
dci2.enaddr := dbgi.denable;
dci2.size := "10"; dci2.read := '1'; dci2.write := '0';
if (dbgi.denable and not r.m.dci.enaddr) = '1' then
mresult2 := (others => '0'); mresult2(19 downto 2) := dbgi.daddr(19 downto 2);
else
mresult2 := dbgi.ddata;
end if;
if dbgi.dwrite = '1' then
dci2.read := '0'; dci2.write := '1';
end if;
end if;
end if;
end if;
end;
procedure fpexack(r : in registers; fpexc : out std_ulogic) is
begin
fpexc := '0';
if FPEN then
if r.x.ctrl.tt = TT_FPEXC then fpexc := '1'; end if;
end if;
end;
procedure diagrdy(denable : in std_ulogic;
dsur : in dsu_registers;
dci : in dc_in_type;
mds : in std_ulogic;
ico : in icache_out_type;
crdy : out std_logic_vector(2 downto 1)) is
begin
crdy := dsur.crdy(1) & '0';
if dci.dsuen = '1' then
case dsur.asi(4 downto 0) is
when ASI_ITAG | ASI_IDATA | ASI_UINST | ASI_SINST =>
crdy(2) := ico.diagrdy and not dsur.crdy(2);
when ASI_DTAG | ASI_MMUSNOOP_DTAG | ASI_DDATA | ASI_UDATA | ASI_SDATA =>
crdy(1) := not denable and dci.enaddr and not dsur.crdy(1);
when others =>
crdy(2) := dci.enaddr and denable;
end case;
end if;
end;
signal r, rin : registers;
signal wpr, wprin : watchpoint_registers;
signal dsur, dsuin : dsu_registers;
signal ir, irin : irestart_register;
signal rp, rpin : pwd_register_type;
-- execute stage operations
constant EXE_AND : std_logic_vector(2 downto 0) := "000";
constant EXE_XOR : std_logic_vector(2 downto 0) := "001"; -- must be equal to EXE_PASS2
constant EXE_OR : std_logic_vector(2 downto 0) := "010";
constant EXE_XNOR : std_logic_vector(2 downto 0) := "011";
constant EXE_ANDN : std_logic_vector(2 downto 0) := "100";
constant EXE_ORN : std_logic_vector(2 downto 0) := "101";
constant EXE_DIV : std_logic_vector(2 downto 0) := "110";
constant EXE_PASS1 : std_logic_vector(2 downto 0) := "000";
constant EXE_PASS2 : std_logic_vector(2 downto 0) := "001";
constant EXE_STB : std_logic_vector(2 downto 0) := "010";
constant EXE_STH : std_logic_vector(2 downto 0) := "011";
constant EXE_ONES : std_logic_vector(2 downto 0) := "100";
constant EXE_RDY : std_logic_vector(2 downto 0) := "101";
constant EXE_SPR : std_logic_vector(2 downto 0) := "110";
constant EXE_LINK : std_logic_vector(2 downto 0) := "111";
constant EXE_SLL : std_logic_vector(2 downto 0) := "001";
constant EXE_SRL : std_logic_vector(2 downto 0) := "010";
constant EXE_SRA : std_logic_vector(2 downto 0) := "100";
constant EXE_NOP : std_logic_vector(2 downto 0) := "000";
-- EXE result select
constant EXE_RES_ADD : std_logic_vector(1 downto 0) := "00";
constant EXE_RES_SHIFT : std_logic_vector(1 downto 0) := "01";
constant EXE_RES_LOGIC : std_logic_vector(1 downto 0) := "10";
constant EXE_RES_MISC : std_logic_vector(1 downto 0) := "11";
-- Load types
constant SZBYTE : std_logic_vector(1 downto 0) := "00";
constant SZHALF : std_logic_vector(1 downto 0) := "01";
constant SZWORD : std_logic_vector(1 downto 0) := "10";
constant SZDBL : std_logic_vector(1 downto 0) := "11";
-- calculate register file address
procedure regaddr(cwp : std_logic_vector; reg : std_logic_vector(4 downto 0);
rao : out rfatype) is
variable ra : rfatype;
constant globals : std_logic_vector(RFBITS-5 downto 0) :=
conv_std_logic_vector(NWIN, RFBITS-4);
begin
ra := (others => '0'); ra(4 downto 0) := reg;
if reg(4 downto 3) = "00" then ra(RFBITS -1 downto 4) := globals;
else
ra(NWINLOG2+3 downto 4) := cwp + ra(4);
if ra(RFBITS-1 downto 4) = globals then
ra(RFBITS-1 downto 4) := (others => '0');
end if;
end if;
rao := ra;
end;
-- branch adder
function branch_address(inst : word; pc : pctype) return std_logic_vector is
variable baddr, caddr, tmp : pctype;
begin
caddr := (others => '0'); caddr(31 downto 2) := inst(29 downto 0);
caddr(31 downto 2) := caddr(31 downto 2) + pc(31 downto 2);
baddr := (others => '0'); baddr(31 downto 24) := (others => inst(21));
baddr(23 downto 2) := inst(21 downto 0);
baddr(31 downto 2) := baddr(31 downto 2) + pc(31 downto 2);
if inst(30) = '1' then tmp := caddr; else tmp := baddr; end if;
return(tmp);
end;
-- evaluate branch condition
function branch_true(icc : std_logic_vector(3 downto 0); inst : word)
return std_ulogic is
variable n, z, v, c, branch : std_ulogic;
begin
n := icc(3); z := icc(2); v := icc(1); c := icc(0);
case inst(27 downto 25) is
when "000" => branch := inst(28) xor '0'; -- bn, ba
when "001" => branch := inst(28) xor z; -- be, bne
when "010" => branch := inst(28) xor (z or (n xor v)); -- ble, bg
when "011" => branch := inst(28) xor (n xor v); -- bl, bge
when "100" => branch := inst(28) xor (c or z); -- bleu, bgu
when "101" => branch := inst(28) xor c; -- bcs, bcc
when "110" => branch := inst(28) xor n; -- bneg, bpos
when others => branch := inst(28) xor v; -- bvs, bvc
end case;
return(branch);
end;
-- detect RETT instruction in the pipeline and set the local psr.su and psr.et
procedure su_et_select(r : in registers; xc_ps, xc_s, xc_et : in std_ulogic;
su, et : out std_ulogic) is
begin
if ((r.a.ctrl.rett or r.e.ctrl.rett or r.m.ctrl.rett or r.x.ctrl.rett) = '1')
and (r.x.annul_all = '0')
then su := xc_ps; et := '1';
else su := xc_s; et := xc_et; end if;
end;
-- detect watchpoint trap
function wphit(r : registers; wpr : watchpoint_registers; debug : l3_debug_in_type)
return std_ulogic is
variable exc : std_ulogic;
begin
exc := '0';
for i in 1 to NWP loop
if ((wpr(i-1).exec and r.a.ctrl.pv and not r.a.ctrl.annul) = '1') then
if (((wpr(i-1).addr xor r.a.ctrl.pc(31 downto 2)) and wpr(i-1).mask) = Zero32(31 downto 2)) then
exc := '1';
end if;
end if;
end loop;
if DBGUNIT then
if (debug.dsuen and not r.a.ctrl.annul) = '1' then
exc := exc or (r.a.ctrl.pv and ((debug.dbreak and debug.bwatch) or r.a.step));
end if;
end if;
return(exc);
end;
-- 32-bit shifter
function shift3(r : registers; aluin1, aluin2 : word) return word is
variable shiftin : unsigned(63 downto 0);
variable shiftout : unsigned(63 downto 0);
variable cnt : natural range 0 to 31;
begin
cnt := conv_integer(r.e.shcnt);
if r.e.shleft = '1' then
shiftin(30 downto 0) := (others => '0');
shiftin(63 downto 31) := '0' & unsigned(aluin1);
else
shiftin(63 downto 32) := (others => r.e.sari);
shiftin(31 downto 0) := unsigned(aluin1);
end if;
shiftout := SHIFT_RIGHT(shiftin, cnt);
return(std_logic_vector(shiftout(31 downto 0)));
end;
function shift2(r : registers; aluin1, aluin2 : word) return word is
variable ushiftin : unsigned(31 downto 0);
variable sshiftin : signed(32 downto 0);
variable cnt : natural range 0 to 31;
begin
cnt := conv_integer(r.e.shcnt);
ushiftin := unsigned(aluin1);
sshiftin := signed('0' & aluin1);
if r.e.shleft = '1' then
return(std_logic_vector(SHIFT_LEFT(ushiftin, cnt)));
else
if r.e.sari = '1' then sshiftin(32) := aluin1(31); end if;
sshiftin := SHIFT_RIGHT(sshiftin, cnt);
return(std_logic_vector(sshiftin(31 downto 0)));
-- else
-- ushiftin := SHIFT_RIGHT(ushiftin, cnt);
-- return(std_logic_vector(ushiftin));
-- end if;
end if;
end;
function shift(r : registers; aluin1, aluin2 : word;
shiftcnt : std_logic_vector(4 downto 0); sari : std_ulogic ) return word is
variable shiftin : std_logic_vector(63 downto 0);
begin
shiftin := zero32 & aluin1;
if r.e.shleft = '1' then
shiftin(31 downto 0) := zero32; shiftin(63 downto 31) := '0' & aluin1;
else shiftin(63 downto 32) := (others => sari); end if;
if shiftcnt (4) = '1' then shiftin(47 downto 0) := shiftin(63 downto 16); end if;
if shiftcnt (3) = '1' then shiftin(39 downto 0) := shiftin(47 downto 8); end if;
if shiftcnt (2) = '1' then shiftin(35 downto 0) := shiftin(39 downto 4); end if;
if shiftcnt (1) = '1' then shiftin(33 downto 0) := shiftin(35 downto 2); end if;
if shiftcnt (0) = '1' then shiftin(31 downto 0) := shiftin(32 downto 1); end if;
return(shiftin(31 downto 0));
end;
-- Check for illegal and privileged instructions
procedure exception_detect(r : registers; wpr : watchpoint_registers; dbgi : l3_debug_in_type;
trapin : in std_ulogic; ttin : in std_logic_vector(5 downto 0);
trap : out std_ulogic; tt : out std_logic_vector(5 downto 0)) is
variable illegal_inst, privileged_inst : std_ulogic;
variable cp_disabled, fp_disabled, fpop : std_ulogic;
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable inst : word;
variable wph : std_ulogic;
begin
inst := r.a.ctrl.inst; trap := trapin; tt := ttin;
if r.a.ctrl.annul = '0' then
op := inst(31 downto 30); op2 := inst(24 downto 22);
op3 := inst(24 downto 19); rd := inst(29 downto 25);
illegal_inst := '0'; privileged_inst := '0'; cp_disabled := '0';
fp_disabled := '0'; fpop := '0';
case op is
when CALL => null;
when FMT2 =>
case op2 is
when SETHI | BICC => null;
when FBFCC =>
if FPEN then fp_disabled := not r.w.s.ef; else fp_disabled := '1'; end if;
when CBCCC =>
if (not CPEN) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when others => illegal_inst := '1';
end case;
when FMT3 =>
case op3 is
when IAND | ANDCC | ANDN | ANDNCC | IOR | ORCC | ORN | ORNCC | IXOR |
XORCC | IXNOR | XNORCC | ISLL | ISRL | ISRA | MULSCC | IADD | ADDX |
ADDCC | ADDXCC | ISUB | SUBX | SUBCC | SUBXCC | FLUSH | JMPL | TICC |
SAVE | RESTORE | RDY => null;
when TADDCC | TADDCCTV | TSUBCC | TSUBCCTV =>
if notag = 1 then illegal_inst := '1'; end if;
when UMAC | SMAC =>
if not MACEN then illegal_inst := '1'; end if;
when UMUL | SMUL | UMULCC | SMULCC =>
if not MULEN then illegal_inst := '1'; end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if not DIVEN then illegal_inst := '1'; end if;
when RETT => illegal_inst := r.a.et; privileged_inst := not r.a.su;
when RDPSR | RDTBR | RDWIM => privileged_inst := not r.a.su;
when WRY => null;
when WRPSR =>
privileged_inst := not r.a.su;
when WRWIM | WRTBR => privileged_inst := not r.a.su;
when FPOP1 | FPOP2 =>
if FPEN then fp_disabled := not r.w.s.ef; fpop := '1';
else fp_disabled := '1'; fpop := '0'; end if;
when CPOP1 | CPOP2 =>
if (not CPEN) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when others => illegal_inst := '1';
end case;
when others => -- LDST
case op3 is
when LDD | ISTD => illegal_inst := rd(0); -- trap if odd destination register
when LD | LDUB | LDSTUB | LDUH | LDSB | LDSH | ST | STB | STH | SWAP =>
null;
when LDDA | STDA =>
illegal_inst := inst(13) or rd(0); privileged_inst := not r.a.su;
when LDA | LDUBA| LDSTUBA | LDUHA | LDSBA | LDSHA | STA | STBA | STHA |
SWAPA =>
illegal_inst := inst(13); privileged_inst := not r.a.su;
when LDDF | STDF | LDF | LDFSR | STF | STFSR =>
if FPEN then fp_disabled := not r.w.s.ef;
else fp_disabled := '1'; end if;
when STDFQ =>
privileged_inst := not r.a.su;
if (not FPEN) or (r.w.s.ef = '0') then fp_disabled := '1'; end if;
when STDCQ =>
privileged_inst := not r.a.su;
if (not CPEN) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when LDC | LDCSR | LDDC | STC | STCSR | STDC =>
if (not CPEN) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when others => illegal_inst := '1';
end case;
end case;
wph := wphit(r, wpr, dbgi);
trap := '1';
if r.a.ctrl.trap = '1' then tt := TT_IAEX;
elsif privileged_inst = '1' then tt := TT_PRIV;
elsif illegal_inst = '1' then tt := TT_IINST;
elsif fp_disabled = '1' then tt := TT_FPDIS;
elsif cp_disabled = '1' then tt := TT_CPDIS;
elsif wph = '1' then tt := TT_WATCH;
elsif r.a.wovf= '1' then tt := TT_WINOF;
elsif r.a.wunf= '1' then tt := TT_WINUF;
elsif r.a.ticc= '1' then tt := TT_TICC;
else trap := '0'; tt:= (others => '0'); end if;
end if;
end;
-- instructions that write the condition codes (psr.icc)
procedure wicc_y_gen(inst : word; wicc, wy : out std_ulogic) is
begin
wicc := '0'; wy := '0';
if inst(31 downto 30) = FMT3 then
case inst(24 downto 19) is
when SUBCC | TSUBCC | TSUBCCTV | ADDCC | ANDCC | ORCC | XORCC | ANDNCC |
ORNCC | XNORCC | TADDCC | TADDCCTV | ADDXCC | SUBXCC | WRPSR =>
wicc := '1';
when WRY =>
if r.d.inst(conv_integer(r.d.set))(29 downto 25) = "00000" then wy := '1'; end if;
when MULSCC =>
wicc := '1'; wy := '1';
when UMAC | SMAC =>
if MACEN then wy := '1'; end if;
when UMULCC | SMULCC =>
if MULEN and (((mulo.nready = '1') and (r.d.cnt /= "00")) or (MULTYPE /= 0)) then
wicc := '1'; wy := '1';
end if;
when UMUL | SMUL =>
if MULEN and (((mulo.nready = '1') and (r.d.cnt /= "00")) or (MULTYPE /= 0)) then
wy := '1';
end if;
when UDIVCC | SDIVCC =>
if DIVEN and (divo.nready = '1') and (r.d.cnt /= "00") then
wicc := '1';
end if;
when others =>
end case;
end if;
end;
-- select cwp
procedure cwp_gen(r, v : registers; annul, wcwp : std_ulogic; ncwp : cwptype;
cwp : out cwptype) is
begin
if (r.x.rstate = trap) or (r.x.rstate = dsu2) or (rstn = '0') then cwp := v.w.s.cwp;
elsif (wcwp = '1') and (annul = '0') then cwp := ncwp;
elsif r.m.wcwp = '1' then cwp := r.m.result(NWINLOG2-1 downto 0);
else cwp := r.d.cwp; end if;
end;
-- generate wcwp in ex stage
procedure cwp_ex(r : in registers; wcwp : out std_ulogic) is
begin
if (r.e.ctrl.inst(31 downto 30) = FMT3) and
(r.e.ctrl.inst(24 downto 19) = WRPSR)
then wcwp := not r.e.ctrl.annul; else wcwp := '0'; end if;
end;
-- generate next cwp & window under- and overflow traps
procedure cwp_ctrl(r : in registers; xc_wim : in std_logic_vector(NWIN-1 downto 0);
inst : word; de_cwp : out cwptype; wovf_exc, wunf_exc, wcwp : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable wim : word;
variable ncwp : cwptype;
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
wovf_exc := '0'; wunf_exc := '0'; wim := (others => '0');
wim(NWIN-1 downto 0) := xc_wim; ncwp := r.d.cwp; wcwp := '0';
if (op = FMT3) and ((op3 = RETT) or (op3 = RESTORE) or (op3 = SAVE)) then
wcwp := '1';
if (op3 = SAVE) then
if (not CWPOPT) and (r.d.cwp = CWPMIN) then ncwp := CWPMAX;
else ncwp := r.d.cwp - 1 ; end if;
else
if (not CWPOPT) and (r.d.cwp = CWPMAX) then ncwp := CWPMIN;
else ncwp := r.d.cwp + 1; end if;
end if;
if wim(conv_integer(ncwp)) = '1' then
if op3 = SAVE then wovf_exc := '1'; else wunf_exc := '1'; end if;
end if;
end if;
de_cwp := ncwp;
end;
-- generate register read address 1
procedure rs1_gen(r : registers; inst : word; rs1 : out std_logic_vector(4 downto 0);
rs1mod : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
rs1 := inst(18 downto 14); rs1mod := '0';
if (op = LDST) then
if ((r.d.cnt = "01") and ((op3(2) and not op3(3)) = '1')) or
(r.d.cnt = "10")
then rs1mod := '1'; rs1 := inst(29 downto 25); end if;
if ((r.d.cnt = "10") and (op3(3 downto 0) = "0111")) then
rs1(0) := '1';
end if;
end if;
end;
-- load/icc interlock detection
procedure lock_gen(r : registers; rs2, rd : std_logic_vector(4 downto 0);
rfa1, rfa2, rfrd : rfatype; inst : word; fpc_lock, mulinsn, divinsn : std_ulogic;
lldcheck1, lldcheck2, lldlock, lldchkra, lldchkex : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable cond : std_logic_vector(3 downto 0);
variable rs1 : std_logic_vector(4 downto 0);
variable i, ldcheck1, ldcheck2, ldchkra, ldchkex, ldcheck3 : std_ulogic;
variable ldlock, icc_check, bicc_hold, chkmul, y_check : std_ulogic;
variable lddlock : boolean;
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
op2 := inst(24 downto 22); cond := inst(28 downto 25);
rs1 := inst(18 downto 14); lddlock := false; i := inst(13);
ldcheck1 := '0'; ldcheck2 := '0'; ldcheck3 := '0'; ldlock := '0';
ldchkra := '1'; ldchkex := '1'; icc_check := '0'; bicc_hold := '0';
y_check := '0';
if (r.d.annul = '0') then
case op is
when FMT2 =>
if (op2 = BICC) and (cond(2 downto 0) /= "000") then
icc_check := '1';
end if;
when FMT3 =>
ldcheck1 := '1'; ldcheck2 := not i;
case op3 is
when TICC =>
if (cond(2 downto 0) /= "000") then icc_check := '1'; end if;
when RDY =>
ldcheck1 := '0'; ldcheck2 := '0';
if MACPIPE then y_check := '1'; end if;
when RDWIM | RDTBR =>
ldcheck1 := '0'; ldcheck2 := '0';
when RDPSR =>
ldcheck1 := '0'; ldcheck2 := '0'; icc_check := '1';
if MULEN then icc_check := '1'; end if;
-- when ADDX | ADDXCC | SUBX | SUBXCC =>
-- if MULEN then icc_check := '1'; end if;
when SDIV | SDIVCC | UDIV | UDIVCC =>
if DIVEN then y_check := '1'; end if;
when FPOP1 | FPOP2 => ldcheck1:= '0'; ldcheck2 := '0';
when others =>
end case;
when LDST =>
ldcheck1 := '1'; ldchkra := '0';
case r.d.cnt is
when "00" =>
if (lddel = 2) and (op3(2) = '1') then ldcheck3 := '1'; end if;
ldcheck2 := not i; ldchkra := '1';
when "01" => ldcheck2 := not i;
when others => ldchkex := '0';
end case;
if (op3(2 downto 0) = "011") then lddlock := true; end if;
when others => null;
end case;
end if;
if MULEN or DIVEN then
chkmul := mulinsn;
bicc_hold := bicc_hold or (icc_check and r.m.ctrl.wicc and (r.m.ctrl.cnt(0) or r.m.mul));
else chkmul := '0'; end if;
if DIVEN then
bicc_hold := bicc_hold or (y_check and (r.a.ctrl.wy or r.e.ctrl.wy));
chkmul := chkmul or divinsn;
end if;
bicc_hold := bicc_hold or (icc_check and (r.a.ctrl.wicc or r.e.ctrl.wicc));
if (((r.a.ctrl.ld or chkmul) and r.a.ctrl.wreg and ldchkra) = '1') and
(((ldcheck1 = '1') and (r.a.ctrl.rd = rfa1)) or
((ldcheck2 = '1') and (r.a.ctrl.rd = rfa2)) or
((ldcheck3 = '1') and (r.a.ctrl.rd = rfrd)))
then ldlock := '1'; end if;
if (((r.e.ctrl.ld or r.e.mac) and r.e.ctrl.wreg and ldchkex) = '1') and
((lddel = 2) or (MACPIPE and (r.e.mac = '1')) or ((MULTYPE = 3) and (r.e.mul = '1'))) and
(((ldcheck1 = '1') and (r.e.ctrl.rd = rfa1)) or
((ldcheck2 = '1') and (r.e.ctrl.rd = rfa2)))
then ldlock := '1'; end if;
ldlock := ldlock or bicc_hold or fpc_lock;
lldcheck1 := ldcheck1; lldcheck2:= ldcheck2; lldlock := ldlock;
lldchkra := ldchkra; lldchkex := ldchkex;
end;
procedure fpbranch(inst : in word; fcc : in std_logic_vector(1 downto 0);
branch : out std_ulogic) is
variable cond : std_logic_vector(3 downto 0);
variable fbres : std_ulogic;
begin
cond := inst(28 downto 25);
case cond(2 downto 0) is
when "000" => fbres := '0'; -- fba, fbn
when "001" => fbres := fcc(1) or fcc(0);
when "010" => fbres := fcc(1) xor fcc(0);
when "011" => fbres := fcc(0);
when "100" => fbres := (not fcc(1)) and fcc(0);
when "101" => fbres := fcc(1);
when "110" => fbres := fcc(1) and not fcc(0);
when others => fbres := fcc(1) and fcc(0);
end case;
branch := cond(3) xor fbres;
end;
-- PC generation
procedure ic_ctrl(r : registers; inst : word; annul_all, ldlock, branch_true,
fbranch_true, cbranch_true, fccv, cccv : in std_ulogic;
cnt : out std_logic_vector(1 downto 0);
de_pc : out pctype; de_branch, ctrl_annul, de_annul, jmpl_inst, inull,
de_pv, ctrl_pv, de_hold_pc, ticc_exception, rett_inst, mulstart,
divstart : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable cond : std_logic_vector(3 downto 0);
variable hold_pc, annul_current, annul_next, branch, annul, pv : std_ulogic;
variable de_jmpl : std_ulogic;
begin
branch := '0'; annul_next := '0'; annul_current := '0'; pv := '1';
hold_pc := '0'; ticc_exception := '0'; rett_inst := '0';
op := inst(31 downto 30); op3 := inst(24 downto 19);
op2 := inst(24 downto 22); cond := inst(28 downto 25);
annul := inst(29); de_jmpl := '0'; cnt := "00";
mulstart := '0'; divstart := '0';
if r.d.annul = '0' then
case inst(31 downto 30) is
when CALL =>
branch := '1';
if r.d.inull = '1' then
hold_pc := '1'; annul_current := '1';
end if;
when FMT2 =>
if (op2 = BICC) or (FPEN and (op2 = FBFCC)) or (CPEN and (op2 = CBCCC)) then
if (FPEN and (op2 = FBFCC)) then
branch := fbranch_true;
if fccv /= '1' then hold_pc := '1'; annul_current := '1'; end if;
elsif (CPEN and (op2 = CBCCC)) then
branch := cbranch_true;
if cccv /= '1' then hold_pc := '1'; annul_current := '1'; end if;
else branch := branch_true; end if;
if hold_pc = '0' then
if (branch = '1') then
if (cond = BA) and (annul = '1') then annul_next := '1'; end if;
else annul_next := annul; end if;
if r.d.inull = '1' then -- contention with JMPL
hold_pc := '1'; annul_current := '1'; annul_next := '0';
end if;
end if;
end if;
when FMT3 =>
case op3 is
when UMUL | SMUL | UMULCC | SMULCC =>
if MULEN and (MULTYPE /= 0) then mulstart := '1'; end if;
if MULEN and (MULTYPE = 0) then
case r.d.cnt is
when "00" =>
cnt := "01"; hold_pc := '1'; pv := '0'; mulstart := '1';
when "01" =>
if mulo.nready = '1' then cnt := "00";
else cnt := "01"; pv := '0'; hold_pc := '1'; end if;
when others => null;
end case;
end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if DIVEN then
case r.d.cnt is
when "00" =>
cnt := "01"; hold_pc := '1'; pv := '0';
divstart := '1';
when "01" =>
if divo.nready = '1' then cnt := "00";
else cnt := "01"; pv := '0'; hold_pc := '1'; end if;
when others => null;
end case;
end if;
when TICC =>
if branch_true = '1' then ticc_exception := '1'; end if;
when RETT =>
rett_inst := '1'; --su := sregs.ps;
when JMPL =>
de_jmpl := '1';
when WRY =>
if PWRD1 then
if inst(29 downto 25) = "10011" then -- %ASR19
case r.d.cnt is
when "00" =>
pv := '0'; cnt := "00"; hold_pc := '1';
if r.x.ipend = '1' then cnt := "01"; end if;
when "01" =>
cnt := "00";
when others =>
end case;
end if;
end if;
when others => null;
end case;
when others => -- LDST
case r.d.cnt is
when "00" =>
if (op3(2) = '1') or (op3(1 downto 0) = "11") then -- ST/LDST/SWAP/LDD
cnt := "01"; hold_pc := '1'; pv := '0';
end if;
when "01" =>
if (op3(2 downto 0) = "111") or (op3(3 downto 0) = "1101") or
((CPEN or FPEN) and ((op3(5) & op3(2 downto 0)) = "1110"))
then -- LDD/STD/LDSTUB/SWAP
cnt := "10"; pv := '0'; hold_pc := '1';
else
cnt := "00";
end if;
when "10" =>
cnt := "00";
when others => null;
end case;
end case;
end if;
if ldlock = '1' then
cnt := r.d.cnt; annul_next := '0'; pv := '1';
end if;
hold_pc := (hold_pc or ldlock) and not annul_all;
if hold_pc = '1' then de_pc := r.d.pc; else de_pc := r.f.pc; end if;
annul_current := (annul_current or ldlock or annul_all);
ctrl_annul := r.d.annul or annul_all or annul_current;
pv := pv and not ((r.d.inull and not hold_pc) or annul_all);
jmpl_inst := de_jmpl and not annul_current;
annul_next := (r.d.inull and not hold_pc) or annul_next or annul_all;
if (annul_next = '1') or (rstn = '0') then
cnt := (others => '0');
end if;
de_hold_pc := hold_pc; de_branch := branch; de_annul := annul_next;
de_pv := pv; ctrl_pv := r.d.pv and
not ((r.d.annul and not r.d.pv) or annul_all or annul_current);
inull := (not rstn) or r.d.inull or hold_pc or annul_all;
end;
-- register write address generation
procedure rd_gen(r : registers; inst : word; wreg, ld : out std_ulogic;
rdo : out std_logic_vector(4 downto 0)) is
variable write_reg : std_ulogic;
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
begin
op := inst(31 downto 30);
op2 := inst(24 downto 22);
op3 := inst(24 downto 19);
write_reg := '0'; rd := inst(29 downto 25); ld := '0';
case op is
when CALL =>
write_reg := '1'; rd := "01111"; -- CALL saves PC in r[15] (%o7)
when FMT2 =>
if (op2 = SETHI) then write_reg := '1'; end if;
when FMT3 =>
case op3 is
when UMUL | SMUL | UMULCC | SMULCC =>
if MULEN then
if (((mulo.nready = '1') and (r.d.cnt /= "00")) or (MULTYPE /= 0)) then
write_reg := '1';
end if;
else write_reg := '1'; end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if DIVEN then
if (divo.nready = '1') and (r.d.cnt /= "00") then
write_reg := '1';
end if;
else write_reg := '1'; end if;
when RETT | WRPSR | WRY | WRWIM | WRTBR | TICC | FLUSH => null;
when FPOP1 | FPOP2 => null;
when CPOP1 | CPOP2 => null;
when others => write_reg := '1';
end case;
when others => -- LDST
ld := not op3(2);
if (op3(2) = '0') and not ((CPEN or FPEN) and (op3(5) = '1'))
then write_reg := '1'; end if;
case op3 is
when SWAP | SWAPA | LDSTUB | LDSTUBA =>
if r.d.cnt = "00" then write_reg := '1'; ld := '1'; end if;
when others => null;
end case;
if r.d.cnt = "01" then
case op3 is
when LDD | LDDA | LDDC | LDDF => rd(0) := '1';
when others =>
end case;
end if;
end case;
if (rd = "00000") then write_reg := '0'; end if;
wreg := write_reg; rdo := rd;
end;
-- immediate data generation
function imm_data (r : registers; insn : word)
return word is
variable immediate_data, inst : word;
begin
immediate_data := (others => '0'); inst := insn;
case inst(31 downto 30) is
when FMT2 =>
immediate_data := inst(21 downto 0) & "0000000000";
when others => -- LDST
immediate_data(31 downto 13) := (others => inst(12));
immediate_data(12 downto 0) := inst(12 downto 0);
end case;
return(immediate_data);
end;
-- read special registers
function get_spr (r : registers) return word is
variable spr : word;
begin
spr := (others => '0');
case r.e.ctrl.inst(24 downto 19) is
when RDPSR => spr(31 downto 5) := conv_std_logic_vector(IMPL,4) &
conv_std_logic_vector(VER,4) & r.m.icc & "000000" & r.w.s.ec & r.w.s.ef &
r.w.s.pil & r.e.su & r.w.s.ps & r.e.et;
spr(NWINLOG2-1 downto 0) := r.e.cwp;
when RDTBR => spr(31 downto 4) := r.w.s.tba & r.w.s.tt;
when RDWIM => spr(NWIN-1 downto 0) := r.w.s.wim;
when others =>
end case;
return(spr);
end;
-- immediate data select
function imm_select(inst : word) return boolean is
variable imm : boolean;
begin
imm := false;
case inst(31 downto 30) is
when FMT2 =>
case inst(24 downto 22) is
when SETHI => imm := true;
when others =>
end case;
when FMT3 =>
case inst(24 downto 19) is
when RDWIM | RDPSR | RDTBR => imm := true;
when others => if (inst(13) = '1') then imm := true; end if;
end case;
when LDST =>
if (inst(13) = '1') then imm := true; end if;
when others =>
end case;
return(imm);
end;
-- EXE operation
procedure alu_op(r : in registers; iop1, iop2 : in word; me_icc : std_logic_vector(3 downto 0);
my, ldbp : std_ulogic; aop1, aop2 : out word; aluop : out std_logic_vector(2 downto 0);
alusel : out std_logic_vector(1 downto 0); aluadd : out std_ulogic;
shcnt : out std_logic_vector(4 downto 0); sari, shleft, ymsb,
mulins, divins, mulstep, macins, ldbp2, invop2 : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable icc : std_logic_vector(3 downto 0);
variable y0 : std_ulogic;
begin
op := r.a.ctrl.inst(31 downto 30);
op2 := r.a.ctrl.inst(24 downto 22);
op3 := r.a.ctrl.inst(24 downto 19);
aop1 := iop1; aop2 := iop2; ldbp2 := ldbp;
aluop := EXE_NOP; alusel := EXE_RES_MISC; aluadd := '1';
shcnt := iop2(4 downto 0); sari := '0'; shleft := '0'; invop2 := '0';
ymsb := iop1(0); mulins := '0'; divins := '0'; mulstep := '0';
macins := '0';
if r.e.ctrl.wy = '1' then y0 := my;
elsif r.m.ctrl.wy = '1' then y0 := r.m.y(0);
elsif r.x.ctrl.wy = '1' then y0 := r.x.y(0);
else y0 := r.w.s.y(0); end if;
if r.e.ctrl.wicc = '1' then icc := me_icc;
elsif r.m.ctrl.wicc = '1' then icc := r.m.icc;
elsif r.x.ctrl.wicc = '1' then icc := r.x.icc;
else icc := r.w.s.icc; end if;
case op is
when CALL =>
aluop := EXE_LINK;
when FMT2 =>
case op2 is
when SETHI => aluop := EXE_PASS2;
when others =>
end case;
when FMT3 =>
case op3 is
when IADD | ADDX | ADDCC | ADDXCC | TADDCC | TADDCCTV | SAVE | RESTORE |
TICC | JMPL | RETT => alusel := EXE_RES_ADD;
when ISUB | SUBX | SUBCC | SUBXCC | TSUBCC | TSUBCCTV =>
alusel := EXE_RES_ADD; aluadd := '0'; aop2 := not iop2; invop2 := '1';
when MULSCC => alusel := EXE_RES_ADD;
aop1 := (icc(3) xor icc(1)) & iop1(31 downto 1);
if y0 = '0' then aop2 := (others => '0'); ldbp2 := '0'; end if;
mulstep := '1';
when UMUL | UMULCC | SMUL | SMULCC =>
if MULEN then mulins := '1'; end if;
when UMAC | SMAC =>
if MACEN then mulins := '1'; macins := '1'; end if;
when UDIV | UDIVCC | SDIV | SDIVCC =>
if DIVEN then
aluop := EXE_DIV; alusel := EXE_RES_LOGIC; divins := '1';
end if;
when IAND | ANDCC => aluop := EXE_AND; alusel := EXE_RES_LOGIC;
when ANDN | ANDNCC => aluop := EXE_ANDN; alusel := EXE_RES_LOGIC;
when IOR | ORCC => aluop := EXE_OR; alusel := EXE_RES_LOGIC;
when ORN | ORNCC => aluop := EXE_ORN; alusel := EXE_RES_LOGIC;
when IXNOR | XNORCC => aluop := EXE_XNOR; alusel := EXE_RES_LOGIC;
when XORCC | IXOR | WRPSR | WRWIM | WRTBR | WRY =>
aluop := EXE_XOR; alusel := EXE_RES_LOGIC;
when RDPSR | RDTBR | RDWIM => aluop := EXE_SPR;
when RDY => aluop := EXE_RDY;
when ISLL => aluop := EXE_SLL; alusel := EXE_RES_SHIFT; shleft := '1';
shcnt := not iop2(4 downto 0); invop2 := '1';
when ISRL => aluop := EXE_SRL; alusel := EXE_RES_SHIFT;
when ISRA => aluop := EXE_SRA; alusel := EXE_RES_SHIFT; sari := iop1(31);
when FPOP1 | FPOP2 =>
when others =>
end case;
when others => -- LDST
case r.a.ctrl.cnt is
when "00" =>
alusel := EXE_RES_ADD;
when "01" =>
case op3 is
when LDD | LDDA | LDDC => alusel := EXE_RES_ADD;
when LDDF => alusel := EXE_RES_ADD;
when SWAP | SWAPA | LDSTUB | LDSTUBA => alusel := EXE_RES_ADD;
when STF | STDF =>
when others =>
aluop := EXE_PASS1;
if op3(2) = '1' then
if op3(1 downto 0) = "01" then aluop := EXE_STB;
elsif op3(1 downto 0) = "10" then aluop := EXE_STH; end if;
end if;
end case;
when "10" =>
aluop := EXE_PASS1;
if op3(2) = '1' then -- ST
if (op3(3) and not op3(1))= '1' then aluop := EXE_ONES; end if; -- LDSTUB/A
end if;
when others =>
end case;
end case;
end;
function ra_inull_gen(r, v : registers) return std_ulogic is
variable de_inull : std_ulogic;
begin
de_inull := '0';
if ((v.e.jmpl or v.e.ctrl.rett) and not v.e.ctrl.annul and not (r.e.jmpl and not r.e.ctrl.annul)) = '1' then de_inull := '1'; end if;
if ((v.a.jmpl or v.a.ctrl.rett) and not v.a.ctrl.annul and not (r.a.jmpl and not r.a.ctrl.annul)) = '1' then de_inull := '1'; end if;
return(de_inull);
end;
-- operand generation
procedure op_mux(r : in registers; rfd, ed, md, xd, im : in word;
rsel : in std_logic_vector(2 downto 0);
ldbp : out std_ulogic; d : out word) is
begin
ldbp := '0';
case rsel is
when "000" => d := rfd;
when "001" => d := ed;
when "010" => d := md; if lddel = 1 then ldbp := r.m.ctrl.ld; end if;
when "011" => d := xd;
when "100" => d := im;
when "101" => d := (others => '0');
when "110" => d := r.w.result;
when others => d := (others => '-');
end case;
end;
procedure op_find(r : in registers; ldchkra : std_ulogic; ldchkex : std_ulogic;
rs1 : std_logic_vector(4 downto 0); ra : rfatype; im : boolean; rfe : out std_ulogic;
osel : out std_logic_vector(2 downto 0); ldcheck : std_ulogic) is
begin
rfe := '0';
if im then osel := "100";
elsif rs1 = "00000" then osel := "101"; -- %g0
elsif ((r.a.ctrl.wreg and ldchkra) = '1') and (ra = r.a.ctrl.rd) then osel := "001";
elsif ((r.e.ctrl.wreg and ldchkex) = '1') and (ra = r.e.ctrl.rd) then osel := "010";
elsif r.m.ctrl.wreg = '1' and (ra = r.m.ctrl.rd) then osel := "011";
elsif (irfwt = 0) and r.x.ctrl.wreg = '1' and (ra = r.x.ctrl.rd) then osel := "110";
else osel := "000"; rfe := ldcheck; end if;
end;
-- generate carry-in for alu
procedure cin_gen(r : registers; me_cin : in std_ulogic; cin : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable ncin : std_ulogic;
begin
op := r.a.ctrl.inst(31 downto 30); op3 := r.a.ctrl.inst(24 downto 19);
if r.e.ctrl.wicc = '1' then ncin := me_cin;
else ncin := r.m.icc(0); end if;
cin := '0';
case op is
when FMT3 =>
case op3 is
when ISUB | SUBCC | TSUBCC | TSUBCCTV => cin := '1';
when ADDX | ADDXCC => cin := ncin;
when SUBX | SUBXCC => cin := not ncin;
when others => null;
end case;
when others => null;
end case;
end;
procedure logic_op(r : registers; aluin1, aluin2, mey : word;
ymsb : std_ulogic; logicres, y : out word) is
variable logicout : word;
begin
case r.e.aluop is
when EXE_AND => logicout := aluin1 and aluin2;
when EXE_ANDN => logicout := aluin1 and not aluin2;
when EXE_OR => logicout := aluin1 or aluin2;
when EXE_ORN => logicout := aluin1 or not aluin2;
when EXE_XOR => logicout := aluin1 xor aluin2;
when EXE_XNOR => logicout := aluin1 xor not aluin2;
when EXE_DIV =>
if DIVEN then logicout := aluin2;
else logicout := (others => '-'); end if;
when others => logicout := (others => '-');
end case;
if (r.e.ctrl.wy and r.e.mulstep) = '1' then
y := ymsb & r.m.y(31 downto 1);
elsif r.e.ctrl.wy = '1' then y := logicout;
elsif r.m.ctrl.wy = '1' then y := mey;
elsif MACPIPE and (r.x.mac = '1') then y := mulo.result(63 downto 32);
elsif r.x.ctrl.wy = '1' then y := r.x.y;
else y := r.w.s.y; end if;
logicres := logicout;
end;
procedure misc_op(r : registers; wpr : watchpoint_registers;
aluin1, aluin2, ldata, mey : word;
mout, edata : out word) is
variable miscout, bpdata, stdata : word;
variable wpi : integer;
begin
wpi := 0; miscout := r.e.ctrl.pc(31 downto 2) & "00";
edata := aluin1; bpdata := aluin1;
if ((r.x.ctrl.wreg and r.x.ctrl.ld and not r.x.ctrl.annul) = '1') and
(r.x.ctrl.rd = r.e.ctrl.rd) and (r.e.ctrl.inst(31 downto 30) = LDST) and
(r.e.ctrl.cnt /= "10")
then bpdata := ldata; end if;
case r.e.aluop is
when EXE_STB => miscout := bpdata(7 downto 0) & bpdata(7 downto 0) &
bpdata(7 downto 0) & bpdata(7 downto 0);
edata := miscout;
when EXE_STH => miscout := bpdata(15 downto 0) & bpdata(15 downto 0);
edata := miscout;
when EXE_PASS1 => miscout := bpdata; edata := miscout;
when EXE_PASS2 => miscout := aluin2;
when EXE_ONES => miscout := (others => '1');
edata := miscout;
when EXE_RDY =>
if MULEN and (r.m.ctrl.wy = '1') then miscout := mey;
else miscout := r.m.y; end if;
if (NWP > 0) and (r.e.ctrl.inst(18 downto 17) = "11") then
wpi := conv_integer(r.e.ctrl.inst(16 downto 15));
if r.e.ctrl.inst(14) = '0' then miscout := wpr(wpi).addr & '0' & wpr(wpi).exec;
else miscout := wpr(wpi).mask & wpr(wpi).load & wpr(wpi).store; end if;
end if;
if (r.e.ctrl.inst(18 downto 17) = "10") and (r.e.ctrl.inst(14) = '1') then --%ASR17
miscout := asr17_gen(r);
end if;
if MACEN then
if (r.e.ctrl.inst(18 downto 14) = "10010") then --%ASR18
if ((r.m.mac = '1') and not MACPIPE) or ((r.x.mac = '1') and MACPIPE) then
miscout := mulo.result(31 downto 0); -- data forward of asr18
else miscout := r.w.s.asr18; end if;
else
if ((r.m.mac = '1') and not MACPIPE) or ((r.x.mac = '1') and MACPIPE) then
miscout := mulo.result(63 downto 32); -- data forward Y
end if;
end if;
end if;
when EXE_SPR =>
miscout := get_spr(r);
when others => null;
end case;
mout := miscout;
end;
procedure alu_select(r : registers; addout : std_logic_vector(32 downto 0);
op1, op2 : word; shiftout, logicout, miscout : word; res : out word;
me_icc : std_logic_vector(3 downto 0);
icco : out std_logic_vector(3 downto 0); divz : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable icc : std_logic_vector(3 downto 0);
variable aluresult : word;
begin
op := r.e.ctrl.inst(31 downto 30); op3 := r.e.ctrl.inst(24 downto 19);
icc := (others => '0');
case r.e.alusel is
when EXE_RES_ADD =>
aluresult := addout(32 downto 1);
if r.e.aluadd = '0' then
icc(0) := ((not op1(31)) and not op2(31)) or -- Carry
(addout(32) and ((not op1(31)) or not op2(31)));
icc(1) := (op1(31) and (op2(31)) and not addout(32)) or -- Overflow
(addout(32) and (not op1(31)) and not op2(31));
else
icc(0) := (op1(31) and op2(31)) or -- Carry
((not addout(32)) and (op1(31) or op2(31)));
icc(1) := (op1(31) and op2(31) and not addout(32)) or -- Overflow
(addout(32) and (not op1(31)) and (not op2(31)));
end if;
if notag = 0 then
case op is
when FMT3 =>
case op3 is
when TADDCC | TADDCCTV =>
icc(1) := op1(0) or op1(1) or op2(0) or op2(1) or icc(1);
when TSUBCC | TSUBCCTV =>
icc(1) := op1(0) or op1(1) or (not op2(0)) or (not op2(1)) or icc(1);
when others => null;
end case;
when others => null;
end case;
end if;
if aluresult = zero32 then icc(2) := '1'; end if;
when EXE_RES_SHIFT => aluresult := shiftout;
when EXE_RES_LOGIC => aluresult := logicout;
if aluresult = zero32 then icc(2) := '1'; end if;
when others => aluresult := miscout;
end case;
if r.e.jmpl = '1' then aluresult := r.e.ctrl.pc(31 downto 2) & "00"; end if;
icc(3) := aluresult(31); divz := icc(2);
if r.e.ctrl.wicc = '1' then
if (op = FMT3) and (op3 = WRPSR) then icco := logicout(23 downto 20);
else icco := icc; end if;
elsif r.m.ctrl.wicc = '1' then icco := me_icc;
elsif r.x.ctrl.wicc = '1' then icco := r.x.icc;
else icco := r.w.s.icc; end if;
res := aluresult;
end;
procedure dcache_gen(r, v : registers; dci : out dc_in_type;
link_pc, jump, force_a2, load : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable su : std_ulogic;
begin
op := r.e.ctrl.inst(31 downto 30); op3 := r.e.ctrl.inst(24 downto 19);
dci.signed := '0'; dci.lock := '0'; dci.dsuen := '0'; dci.size := SZWORD;
if op = LDST then
case op3 is
when LDUB | LDUBA => dci.size := SZBYTE;
when LDSTUB | LDSTUBA => dci.size := SZBYTE; dci.lock := '1';
when LDUH | LDUHA => dci.size := SZHALF;
when LDSB | LDSBA => dci.size := SZBYTE; dci.signed := '1';
when LDSH | LDSHA => dci.size := SZHALF; dci.signed := '1';
when LD | LDA | LDF | LDC => dci.size := SZWORD;
when SWAP | SWAPA => dci.size := SZWORD; dci.lock := '1';
when LDD | LDDA | LDDF | LDDC => dci.size := SZDBL;
when STB | STBA => dci.size := SZBYTE;
when STH | STHA => dci.size := SZHALF;
when ST | STA | STF => dci.size := SZWORD;
when ISTD | STDA => dci.size := SZDBL;
when STDF | STDFQ => if FPEN then dci.size := SZDBL; end if;
when STDC | STDCQ => if CPEN then dci.size := SZDBL; end if;
when others => dci.size := SZWORD; dci.lock := '0'; dci.signed := '0';
end case;
end if;
link_pc := '0'; jump:= '0'; force_a2 := '0'; load := '0';
dci.write := '0'; dci.enaddr := '0'; dci.read := not op3(2);
-- load/store control decoding
if (r.e.ctrl.annul = '0') then
case op is
when CALL => link_pc := '1';
when FMT3 =>
case op3 is
when JMPL => jump := '1'; link_pc := '1';
when RETT => jump := '1';
when others => null;
end case;
when LDST =>
case r.e.ctrl.cnt is
when "00" =>
dci.read := op3(3) or not op3(2); -- LD/LDST/SWAP
load := op3(3) or not op3(2);
dci.enaddr := '1';
when "01" =>
force_a2 := not op3(2); -- LDD
load := not op3(2); dci.enaddr := not op3(2);
if op3(3 downto 2) = "01" then -- ST/STD
dci.write := '1';
end if;
if op3(3 downto 2) = "11" then -- LDST/SWAP
dci.enaddr := '1';
end if;
when "10" => -- STD/LDST/SWAP
dci.write := '1';
when others => null;
end case;
if (r.e.ctrl.trap or (v.x.ctrl.trap and not v.x.ctrl.annul)) = '1' then
dci.enaddr := '0';
end if;
when others => null;
end case;
end if;
if ((r.x.ctrl.rett and not r.x.ctrl.annul) = '1') then su := r.w.s.ps;
else su := r.w.s.s; end if;
if su = '1' then dci.asi := "00001011"; else dci.asi := "00001010"; end if;
if (op3(4) = '1') and ((op3(5) = '0') or not CPEN) then
dci.asi := r.e.ctrl.inst(12 downto 5);
end if;
end;
procedure fpstdata(r : in registers; edata, eres : in word; fpstdata : in std_logic_vector(31 downto 0);
edata2, eres2 : out word) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
begin
edata2 := edata; eres2 := eres;
op := r.e.ctrl.inst(31 downto 30); op3 := r.e.ctrl.inst(24 downto 19);
if FPEN then
if FPEN and (op = LDST) and ((op3(5 downto 4) & op3(2)) = "101") and (r.e.ctrl.cnt /= "00") then
edata2 := fpstdata; eres2 := fpstdata;
end if;
end if;
end;
function ld_align(data : dcdtype; set : std_logic_vector(DSETMSB downto 0);
size, laddr : std_logic_vector(1 downto 0); signed : std_ulogic) return word is
variable align_data, rdata : word;
begin
align_data := data(conv_integer(set)); rdata := (others => '0');
case size is
when "00" => -- byte read
case laddr is
when "00" =>
rdata(7 downto 0) := align_data(31 downto 24);
if signed = '1' then rdata(31 downto 8) := (others => align_data(31)); end if;
when "01" =>
rdata(7 downto 0) := align_data(23 downto 16);
if signed = '1' then rdata(31 downto 8) := (others => align_data(23)); end if;
when "10" =>
rdata(7 downto 0) := align_data(15 downto 8);
if signed = '1' then rdata(31 downto 8) := (others => align_data(15)); end if;
when others =>
rdata(7 downto 0) := align_data(7 downto 0);
if signed = '1' then rdata(31 downto 8) := (others => align_data(7)); end if;
end case;
when "01" => -- half-word read
if laddr(1) = '1' then
rdata(15 downto 0) := align_data(15 downto 0);
if signed = '1' then rdata(31 downto 15) := (others => align_data(15)); end if;
else
rdata(15 downto 0) := align_data(31 downto 16);
if signed = '1' then rdata(31 downto 15) := (others => align_data(31)); end if;
end if;
when others => -- single and double word read
rdata := align_data;
end case;
return(rdata);
end;
procedure mem_trap(r : registers; wpr : watchpoint_registers;
annul, holdn : in std_ulogic;
trapout, iflush, nullify, werrout : out std_ulogic;
tt : out std_logic_vector(5 downto 0)) is
variable cwp : std_logic_vector(NWINLOG2-1 downto 0);
variable cwpx : std_logic_vector(5 downto NWINLOG2);
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable nalign_d : std_ulogic;
variable trap, werr : std_ulogic;
begin
op := r.m.ctrl.inst(31 downto 30); op2 := r.m.ctrl.inst(24 downto 22);
op3 := r.m.ctrl.inst(24 downto 19);
cwpx := r.m.result(5 downto NWINLOG2); cwpx(5) := '0';
iflush := '0'; trap := r.m.ctrl.trap; nullify := annul;
tt := r.m.ctrl.tt; werr := (dco.werr or r.m.werr) and not r.w.s.dwt;
nalign_d := r.m.nalign or r.m.result(2);
if ((annul or trap) /= '1') and (r.m.ctrl.pv = '1') then
if (werr and holdn) = '1' then
trap := '1'; tt := TT_DSEX; werr := '0';
if op = LDST then nullify := '1'; end if;
end if;
end if;
if ((annul or trap) /= '1') then
case op is
when FMT2 =>
case op2 is
when FBFCC =>
if FPEN and (fpo.exc = '1') then trap := '1'; tt := TT_FPEXC; end if;
when CBCCC =>
if CPEN and (cpo.exc = '1') then trap := '1'; tt := TT_CPEXC; end if;
when others => null;
end case;
when FMT3 =>
case op3 is
when WRPSR =>
if (orv(cwpx) = '1') then trap := '1'; tt := TT_IINST; end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if DIVEN then
if r.m.divz = '1' then trap := '1'; tt := TT_DIV; end if;
end if;
when JMPL | RETT =>
if r.m.nalign = '1' then trap := '1'; tt := TT_UNALA; end if;
when TADDCCTV | TSUBCCTV =>
if (notag = 0) and (r.m.icc(1) = '1') then
trap := '1'; tt := TT_TAG;
end if;
when FLUSH => iflush := '1';
when FPOP1 | FPOP2 =>
if FPEN and (fpo.exc = '1') then trap := '1'; tt := TT_FPEXC; end if;
when CPOP1 | CPOP2 =>
if CPEN and (cpo.exc = '1') then trap := '1'; tt := TT_CPEXC; end if;
when others => null;
end case;
when LDST =>
if r.m.ctrl.cnt = "00" then
case op3 is
when LDDF | STDF | STDFQ =>
if FPEN then
if nalign_d = '1' then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif (fpo.exc and r.m.ctrl.pv) = '1'
then trap := '1'; tt := TT_FPEXC; nullify := '1'; end if;
end if;
when LDDC | STDC | STDCQ =>
if CPEN then
if nalign_d = '1' then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif ((cpo.exc and r.m.ctrl.pv) = '1')
then trap := '1'; tt := TT_CPEXC; nullify := '1'; end if;
end if;
when LDD | ISTD | LDDA | STDA =>
if r.m.result(2 downto 0) /= "000" then
trap := '1'; tt := TT_UNALA; nullify := '1';
end if;
when LDF | LDFSR | STFSR | STF =>
if FPEN and (r.m.nalign = '1') then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif FPEN and ((fpo.exc and r.m.ctrl.pv) = '1')
then trap := '1'; tt := TT_FPEXC; nullify := '1'; end if;
when LDC | LDCSR | STCSR | STC =>
if CPEN and (r.m.nalign = '1') then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif CPEN and ((cpo.exc and r.m.ctrl.pv) = '1')
then trap := '1'; tt := TT_CPEXC; nullify := '1'; end if;
when LD | LDA | ST | STA | SWAP | SWAPA =>
if r.m.result(1 downto 0) /= "00" then
trap := '1'; tt := TT_UNALA; nullify := '1';
end if;
when LDUH | LDUHA | LDSH | LDSHA | STH | STHA =>
if r.m.result(0) /= '0' then
trap := '1'; tt := TT_UNALA; nullify := '1';
end if;
when others => null;
end case;
for i in 1 to NWP loop
if ((((wpr(i-1).load and not op3(2)) or (wpr(i-1).store and op3(2))) = '1') and
(((wpr(i-1).addr xor r.m.result(31 downto 2)) and wpr(i-1).mask) = zero32(31 downto 2)))
then trap := '1'; tt := TT_WATCH; nullify := '1'; end if;
end loop;
end if;
when others => null;
end case;
end if;
if (rstn = '0') or (r.x.rstate = dsu2) then werr := '0'; end if;
trapout := trap; werrout := werr;
end;
procedure irq_trap(r : in registers;
ir : in irestart_register;
irl : in std_logic_vector(3 downto 0);
annul : in std_ulogic;
pv : in std_ulogic;
trap : in std_ulogic;
tt : in std_logic_vector(5 downto 0);
nullify : in std_ulogic;
irqen : out std_ulogic;
irqen2 : out std_ulogic;
nullify2 : out std_ulogic;
trap2, ipend : out std_ulogic;
tt2 : out std_logic_vector(5 downto 0)) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable pend : std_ulogic;
begin
nullify2 := nullify; trap2 := trap; tt2 := tt;
op := r.m.ctrl.inst(31 downto 30); op3 := r.m.ctrl.inst(24 downto 19);
irqen := '1'; irqen2 := r.m.irqen;
if (annul or trap) = '0' then
if ((op = FMT3) and (op3 = WRPSR)) then irqen := '0'; end if;
end if;
if (irl = "1111") or (irl > r.w.s.pil) then
pend := r.m.irqen and r.m.irqen2 and r.w.s.et and not ir.pwd;
else pend := '0'; end if;
ipend := pend;
if ((not annul) and pv and (not trap) and pend) = '1' then
trap2 := '1'; tt2 := "01" & irl;
if op = LDST then nullify2 := '1'; end if;
end if;
end;
procedure irq_intack(r : in registers; holdn : in std_ulogic; intack: out std_ulogic) is
begin
intack := '0';
if r.x.rstate = trap then
if r.w.s.tt(7 downto 4) = "0001" then intack := '1'; end if;
end if;
end;
-- write special registers
procedure sp_write (r : registers; wpr : watchpoint_registers;
s : out special_register_type; vwpr : out watchpoint_registers) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable i : integer range 0 to 3;
begin
op := r.x.ctrl.inst(31 downto 30);
op2 := r.x.ctrl.inst(24 downto 22);
op3 := r.x.ctrl.inst(24 downto 19);
s := r.w.s;
rd := r.x.ctrl.inst(29 downto 25);
vwpr := wpr;
case op is
when FMT3 =>
case op3 is
when WRY =>
if rd = "00000" then
s.y := r.x.result;
elsif MACEN and (rd = "10010") then
s.asr18 := r.x.result;
elsif (rd = "10001") then
s.dwt := r.x.result(14);
if (svt = 1) then s.svt := r.x.result(13); end if;
elsif rd(4 downto 3) = "11" then -- %ASR24 - %ASR31
case rd(2 downto 0) is
when "000" =>
vwpr(0).addr := r.x.result(31 downto 2);
vwpr(0).exec := r.x.result(0);
when "001" =>
vwpr(0).mask := r.x.result(31 downto 2);
vwpr(0).load := r.x.result(1);
vwpr(0).store := r.x.result(0);
when "010" =>
vwpr(1).addr := r.x.result(31 downto 2);
vwpr(1).exec := r.x.result(0);
when "011" =>
vwpr(1).mask := r.x.result(31 downto 2);
vwpr(1).load := r.x.result(1);
vwpr(1).store := r.x.result(0);
when "100" =>
vwpr(2).addr := r.x.result(31 downto 2);
vwpr(2).exec := r.x.result(0);
when "101" =>
vwpr(2).mask := r.x.result(31 downto 2);
vwpr(2).load := r.x.result(1);
vwpr(2).store := r.x.result(0);
when "110" =>
vwpr(3).addr := r.x.result(31 downto 2);
vwpr(3).exec := r.x.result(0);
when others => -- "111"
vwpr(3).mask := r.x.result(31 downto 2);
vwpr(3).load := r.x.result(1);
vwpr(3).store := r.x.result(0);
end case;
end if;
when WRPSR =>
s.cwp := r.x.result(NWINLOG2-1 downto 0);
s.icc := r.x.result(23 downto 20);
s.ec := r.x.result(13);
if FPEN then s.ef := r.x.result(12); end if;
s.pil := r.x.result(11 downto 8);
s.s := r.x.result(7);
s.ps := r.x.result(6);
s.et := r.x.result(5);
when WRWIM =>
s.wim := r.x.result(NWIN-1 downto 0);
when WRTBR =>
s.tba := r.x.result(31 downto 12);
when SAVE =>
if (not CWPOPT) and (r.w.s.cwp = CWPMIN) then s.cwp := CWPMAX;
else s.cwp := r.w.s.cwp - 1 ; end if;
when RESTORE =>
if (not CWPOPT) and (r.w.s.cwp = CWPMAX) then s.cwp := CWPMIN;
else s.cwp := r.w.s.cwp + 1; end if;
when RETT =>
if (not CWPOPT) and (r.w.s.cwp = CWPMAX) then s.cwp := CWPMIN;
else s.cwp := r.w.s.cwp + 1; end if;
s.s := r.w.s.ps;
s.et := '1';
when others => null;
end case;
when others => null;
end case;
if r.x.ctrl.wicc = '1' then s.icc := r.x.icc; end if;
if r.x.ctrl.wy = '1' then s.y := r.x.y; end if;
if MACPIPE and (r.x.mac = '1') then
s.asr18 := mulo.result(31 downto 0);
s.y := mulo.result(63 downto 32);
end if;
end;
function npc_find (r : registers) return std_logic_vector is
variable npc : std_logic_vector(2 downto 0);
begin
npc := "011";
if r.m.ctrl.pv = '1' then npc := "000";
elsif r.e.ctrl.pv = '1' then npc := "001";
elsif r.a.ctrl.pv = '1' then npc := "010";
elsif r.d.pv = '1' then npc := "011";
elsif v8 /= 0 then npc := "100"; end if;
return(npc);
end;
function npc_gen (r : registers) return word is
variable npc : std_logic_vector(31 downto 0);
begin
npc := r.a.ctrl.pc(31 downto 2) & "00";
case r.x.npc is
when "000" => npc(31 downto 2) := r.x.ctrl.pc(31 downto 2);
when "001" => npc(31 downto 2) := r.m.ctrl.pc(31 downto 2);
when "010" => npc(31 downto 2) := r.e.ctrl.pc(31 downto 2);
when "011" => npc(31 downto 2) := r.a.ctrl.pc(31 downto 2);
when others =>
if v8 /= 0 then npc(31 downto 2) := r.d.pc(31 downto 2); end if;
end case;
return(npc);
end;
procedure mul_res(r : registers; asr18in : word; result, y, asr18 : out word;
icc : out std_logic_vector(3 downto 0)) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
begin
op := r.m.ctrl.inst(31 downto 30); op3 := r.m.ctrl.inst(24 downto 19);
result := r.m.result; y := r.m.y; icc := r.m.icc; asr18 := asr18in;
case op is
when FMT3 =>
case op3 is
when UMUL | SMUL =>
if MULEN then
result := mulo.result(31 downto 0);
y := mulo.result(63 downto 32);
end if;
when UMULCC | SMULCC =>
if MULEN then
result := mulo.result(31 downto 0); icc := mulo.icc;
y := mulo.result(63 downto 32);
end if;
when UMAC | SMAC =>
if MACEN and not MACPIPE then
result := mulo.result(31 downto 0);
asr18 := mulo.result(31 downto 0);
y := mulo.result(63 downto 32);
end if;
when UDIV | SDIV =>
if DIVEN then
result := divo.result(31 downto 0);
end if;
when UDIVCC | SDIVCC =>
if DIVEN then
result := divo.result(31 downto 0); icc := divo.icc;
end if;
when others => null;
end case;
when others => null;
end case;
end;
function powerdwn(r : registers; trap : std_ulogic; rp : pwd_register_type) return std_ulogic is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable pd : std_ulogic;
begin
op := r.x.ctrl.inst(31 downto 30);
op3 := r.x.ctrl.inst(24 downto 19);
rd := r.x.ctrl.inst(29 downto 25);
pd := '0';
if (not (r.x.ctrl.annul or trap) and r.x.ctrl.pv) = '1' then
if ((op = FMT3) and (op3 = WRY) and (rd = "10011")) then pd := '1'; end if;
pd := pd or rp.pwd;
end if;
return(pd);
end;
signal dummy : std_ulogic;
signal cpu_index : std_logic_vector(3 downto 0);
signal disasen : std_ulogic;
begin
comb : process(ico, dco, rfo, r, wpr, ir, dsur, rstn, holdn, irqi, dbgi, fpo, cpo, tbo,
mulo, divo, dummy, rp)
variable v : registers;
variable vp : pwd_register_type;
variable vwpr : watchpoint_registers;
variable vdsu : dsu_registers;
variable npc : std_logic_vector(31 downto PCLOW);
variable de_raddr1, de_raddr2 : std_logic_vector(9 downto 0);
variable de_rs2, de_rd : std_logic_vector(4 downto 0);
variable de_hold_pc, de_branch, de_fpop, de_ldlock : std_ulogic;
variable de_cwp, de_cwp2 : cwptype;
variable de_inull : std_ulogic;
variable de_ren1, de_ren2 : std_ulogic;
variable de_wcwp : std_ulogic;
variable de_inst : word;
variable de_branch_address : pctype;
variable de_icc : std_logic_vector(3 downto 0);
variable de_fbranch, de_cbranch : std_ulogic;
variable de_rs1mod : std_ulogic;
variable ra_op1, ra_op2 : word;
variable ra_div : std_ulogic;
variable ex_jump, ex_link_pc : std_ulogic;
variable ex_jump_address : pctype;
variable ex_add_res : std_logic_vector(32 downto 0);
variable ex_shift_res, ex_logic_res, ex_misc_res : word;
variable ex_edata, ex_edata2 : word;
variable ex_dci : dc_in_type;
variable ex_force_a2, ex_load, ex_ymsb : std_ulogic;
variable ex_op1, ex_op2, ex_result, ex_result2, mul_op2 : word;
variable ex_shcnt : std_logic_vector(4 downto 0);
variable ex_dsuen : std_ulogic;
variable ex_ldbp2 : std_ulogic;
variable ex_sari : std_ulogic;
variable me_inull, me_nullify, me_nullify2 : std_ulogic;
variable me_iflush : std_ulogic;
variable me_newtt : std_logic_vector(5 downto 0);
variable me_asr18 : word;
variable me_signed : std_ulogic;
variable me_size, me_laddr : std_logic_vector(1 downto 0);
variable me_icc : std_logic_vector(3 downto 0);
variable xc_result : word;
variable xc_df_result : word;
variable xc_waddr : std_logic_vector(9 downto 0);
variable xc_exception, xc_wreg : std_ulogic;
variable xc_trap_address : pctype;
variable xc_vectt : std_logic_vector(7 downto 0);
variable xc_trap : std_ulogic;
variable xc_fpexack : std_ulogic;
variable xc_rstn, xc_halt : std_ulogic;
-- variable wr_rf1_data, wr_rf2_data : word;
variable diagdata : word;
variable tbufi : tracebuf_in_type;
variable dbgm : std_ulogic;
variable fpcdbgwr : std_ulogic;
variable vfpi : fpc_in_type;
variable dsign : std_ulogic;
variable pwrd, sidle : std_ulogic;
variable vir : irestart_register;
variable icnt : std_ulogic;
variable tbufcntx : std_logic_vector(TBUFBITS-1 downto 0);
begin
v := r; vwpr := wpr; vdsu := dsur; vp := rp;
xc_fpexack := '0'; sidle := '0';
fpcdbgwr := '0'; vir := ir; xc_rstn := rstn;
-----------------------------------------------------------------------
-- WRITE STAGE
-----------------------------------------------------------------------
-- wr_rf1_data := rfo.data1; wr_rf2_data := rfo.data2;
-- if irfwt = 0 then
-- if r.w.wreg = '1' then
-- if r.a.rfa1 = r.w.wa then wr_rf1_data := r.w.result; end if;
-- if r.a.rfa2 = r.w.wa then wr_rf2_data := r.w.result; end if;
-- end if;
-- end if;
-----------------------------------------------------------------------
-- EXCEPTION STAGE
-----------------------------------------------------------------------
xc_exception := '0'; xc_halt := '0'; icnt := '0';
xc_waddr := (others => '0');
xc_waddr(RFBITS-1 downto 0) := r.x.ctrl.rd(RFBITS-1 downto 0);
xc_trap := r.x.mexc or r.x.ctrl.trap;
v.x.nerror := rp.error;
if r.x.mexc = '1' then xc_vectt := "00" & TT_DAEX;
elsif r.x.ctrl.tt = TT_TICC then
xc_vectt := '1' & r.x.result(6 downto 0);
else xc_vectt := "00" & r.x.ctrl.tt; end if;
if r.w.s.svt = '0' then
xc_trap_address(31 downto 4) := r.w.s.tba & xc_vectt;
else
xc_trap_address(31 downto 4) := r.w.s.tba & "00000000";
end if;
xc_trap_address(3 downto PCLOW) := (others => '0');
xc_wreg := '0'; v.x.annul_all := '0';
if (r.x.ctrl.ld = '1') then
if (lddel = 2) then
xc_result := ld_align(r.x.data, r.x.set, r.x.dci.size, r.x.laddr, r.x.dci.signed);
else xc_result := r.x.data(0); end if;
elsif MACEN and MACPIPE and (r.x.mac = '1') then
xc_result := mulo.result(31 downto 0);
else xc_result := r.x.result; end if;
xc_df_result := xc_result;
if DBGUNIT then
dbgm := dbgexc(r, dbgi, xc_trap, xc_vectt);
if (dbgi.dsuen and dbgi.dbreak) = '0'then v.x.debug := '0'; end if;
else dbgm := '0'; v.x.debug := '0'; end if;
if PWRD2 then pwrd := powerdwn(r, xc_trap, rp); else pwrd := '0'; end if;
case r.x.rstate is
when run =>
if (not r.x.ctrl.annul and r.x.ctrl.pv and not r.x.debug) = '1' then
icnt := holdn;
end if;
if dbgm = '1' then
v.x.annul_all := '1'; vir.addr := r.x.ctrl.pc;
v.x.rstate := dsu1; v.x.debug := '1';
v.x.npc := npc_find(r);
vdsu.tt := xc_vectt; vdsu.err := dbgerr(r, dbgi, xc_vectt);
elsif (pwrd = '1') and (ir.pwd = '0') then
v.x.annul_all := '1'; vir.addr := r.x.ctrl.pc;
v.x.rstate := dsu1; v.x.npc := npc_find(r); vp.pwd := '1';
elsif (r.x.ctrl.annul or xc_trap) = '0' then
xc_wreg := r.x.ctrl.wreg;
sp_write (r, wpr, v.w.s, vwpr);
vir.pwd := '0';
elsif ((not r.x.ctrl.annul) and xc_trap) = '1' then
xc_exception := '1'; xc_result := r.x.ctrl.pc(31 downto 2) & "00";
xc_wreg := '1'; v.w.s.tt := xc_vectt; v.w.s.ps := r.w.s.s;
v.w.s.s := '1'; v.x.annul_all := '1'; v.x.rstate := trap;
xc_waddr := (others => '0');
xc_waddr(NWINLOG2 + 3 downto 0) := r.w.s.cwp & "0001";
v.x.npc := npc_find(r);
fpexack(r, xc_fpexack);
if r.w.s.et = '0' then
-- v.x.rstate := dsu1; xc_wreg := '0'; vp.error := '1';
xc_wreg := '0';
end if;
end if;
when trap =>
xc_result := npc_gen(r); xc_wreg := '1';
xc_waddr := (others => '0');
xc_waddr(NWINLOG2 + 3 downto 0) := r.w.s.cwp & "0010";
if (r.w.s.et = '1') then
v.w.s.et := '0'; v.x.rstate := run;
if (not CWPOPT) and (r.w.s.cwp = CWPMIN) then v.w.s.cwp := CWPMAX;
else v.w.s.cwp := r.w.s.cwp - 1 ; end if;
else
v.x.rstate := dsu1; xc_wreg := '0'; vp.error := '1';
end if;
when dsu1 =>
xc_exception := '1'; v.x.annul_all := '1';
xc_trap_address(31 downto PCLOW) := r.f.pc;
if DBGUNIT or PWRD2 or (smp /= 0) then
xc_trap_address(31 downto PCLOW) := ir.addr;
vir.addr := npc_gen(r)(31 downto PCLOW);
v.x.rstate := dsu2;
end if;
if DBGUNIT then v.x.debug := r.x.debug; end if;
when dsu2 =>
xc_exception := '1'; v.x.annul_all := '1';
xc_trap_address(31 downto PCLOW) := r.f.pc;
if DBGUNIT or PWRD2 or (smp /= 0) then
sidle := (rp.pwd or rp.error) and ico.idle and dco.idle and not r.x.debug;
if DBGUNIT then
if dbgi.reset = '1' then
if smp /=0 then vp.pwd := not irqi.run; else vp.pwd := '0'; end if;
vp.error := '0';
end if;
if (dbgi.dsuen and dbgi.dbreak) = '1'then v.x.debug := '1'; end if;
diagwr(r, dsur, ir, dbgi, wpr, v.w.s, vwpr, vdsu.asi, xc_trap_address,
vir.addr, vdsu.tbufcnt, xc_wreg, xc_waddr, xc_result, fpcdbgwr);
xc_halt := dbgi.halt;
end if;
if r.x.ipend = '1' then vp.pwd := '0'; end if;
if (rp.error or rp.pwd or r.x.debug or xc_halt) = '0' then
v.x.rstate := run; v.x.annul_all := '0'; vp.error := '0';
xc_trap_address(31 downto PCLOW) := ir.addr; v.x.debug := '0';
vir.pwd := '1';
end if;
if (smp /= 0) and (irqi.rst = '1') then
vp.pwd := '0'; vp.error := '0';
end if;
end if;
when others =>
end case;
irq_intack(r, holdn, v.x.intack);
itrace(r, dsur, vdsu, xc_result, xc_exception, dbgi, rp.error, xc_trap, tbufcntx, tbufi);
vdsu.tbufcnt := tbufcntx;
v.w.except := xc_exception; v.w.result := xc_result;
if (r.x.rstate = dsu2) then v.w.except := '0'; end if;
v.w.wa := xc_waddr(RFBITS-1 downto 0); v.w.wreg := xc_wreg and holdn;
rfi.wdata <= xc_result; rfi.waddr <= xc_waddr;
rfi.wren <= (xc_wreg and holdn) and not dco.scanen;
irqo.intack <= r.x.intack and holdn;
irqo.irl <= r.w.s.tt(3 downto 0);
irqo.pwd <= rp.pwd;
dbgo.halt <= xc_halt;
dbgo.pwd <= rp.pwd;
dbgo.idle <= sidle;
dbgo.icnt <= icnt;
dci.intack <= r.x.intack and holdn;
if (xc_rstn = '0') then
v.w.except := '0'; v.w.s.et := '0'; v.w.s.svt := '0'; v.w.s.dwt := '0';
v.x.annul_all := '1'; v.x.rstate := run; vir.pwd := '0';
vp.pwd := '0'; v.x.debug := '0'; --vp.error := '0';
v.x.nerror := '0';
if svt = 1 then v.w.s.tt := (others => '0'); end if;
if DBGUNIT then
if (dbgi.dsuen and dbgi.dbreak) = '1' then
v.x.rstate := dsu1; v.x.debug := '1';
end if;
end if;
if (smp /= 0) and (irqi.run = '0') and (rstn = '0') then
v.x.rstate := dsu1; vp.pwd := '1';
end if;
end if;
if not FPEN then v.w.s.ef := '0'; end if;
-----------------------------------------------------------------------
-- MEMORY STAGE
-----------------------------------------------------------------------
v.x.ctrl := r.m.ctrl; v.x.dci := r.m.dci;
v.x.ctrl.rett := r.m.ctrl.rett and not r.m.ctrl.annul;
v.x.mac := r.m.mac; v.x.laddr := r.m.result(1 downto 0);
v.x.ctrl.annul := r.m.ctrl.annul or v.x.annul_all;
mul_res(r, v.w.s.asr18, v.x.result, v.x.y, me_asr18, me_icc);
mem_trap(r, wpr, v.x.ctrl.annul, holdn, v.x.ctrl.trap, me_iflush,
me_nullify, v.m.werr, v.x.ctrl.tt);
me_newtt := v.x.ctrl.tt;
irq_trap(r, ir, irqi.irl, v.x.ctrl.annul, v.x.ctrl.pv, v.x.ctrl.trap, me_newtt, me_nullify,
v.m.irqen, v.m.irqen2, me_nullify2, v.x.ctrl.trap,
v.x.ipend, v.x.ctrl.tt);
if (r.m.ctrl.ld or not dco.mds) = '1' then
for i in 0 to dsets-1 loop v.x.data(i) := dco.data(i); end loop;
v.x.set := dco.set(DSETMSB downto 0);
if dco.mds = '0' then
me_size := r.x.dci.size; me_laddr := r.x.laddr; me_signed := r.x.dci.signed;
else
me_size := v.x.dci.size; me_laddr := v.x.laddr; me_signed := v.x.dci.signed;
end if;
if lddel /= 2 then
v.x.data(0) := ld_align(v.x.data, v.x.set, me_size, me_laddr, me_signed);
end if;
end if;
v.x.mexc := dco.mexc;
v.x.icc := me_icc;
v.x.ctrl.wicc := r.m.ctrl.wicc and not v.x.annul_all;
if MACEN and ((v.x.ctrl.annul or v.x.ctrl.trap) = '0') then
v.w.s.asr18 := me_asr18;
end if;
if (r.x.rstate = dsu2) then
me_nullify2 := '0'; v.x.set := dco.set(DSETMSB downto 0);
end if;
dci.maddress <= r.m.result;
dci.enaddr <= r.m.dci.enaddr;
dci.asi <= r.m.dci.asi;
dci.size <= r.m.dci.size;
dci.nullify <= me_nullify2;
dci.lock <= r.m.dci.lock and not r.m.ctrl.annul;
dci.read <= r.m.dci.read;
dci.write <= r.m.dci.write;
dci.flush <= me_iflush;
dci.dsuen <= r.m.dci.dsuen;
dci.msu <= r.m.su;
dci.esu <= r.e.su;
dbgo.ipend <= v.x.ipend;
-----------------------------------------------------------------------
-- EXECUTE STAGE
-----------------------------------------------------------------------
v.m.ctrl := r.e.ctrl; ex_op1 := r.e.op1; ex_op2 := r.e.op2;
v.m.ctrl.rett := r.e.ctrl.rett and not r.e.ctrl.annul;
v.m.ctrl.wreg := r.e.ctrl.wreg and not v.x.annul_all;
ex_ymsb := r.e.ymsb; mul_op2 := ex_op2; ex_shcnt := r.e.shcnt;
v.e.cwp := r.a.cwp; ex_sari := r.e.sari;
v.m.su := r.e.su;
if MULTYPE = 3 then v.m.mul := r.e.mul; else v.m.mul := '0'; end if;
if lddel = 1 then
if r.e.ldbp1 = '1' then
ex_op1 := r.x.data(0);
ex_sari := r.x.data(0)(31) and r.e.ctrl.inst(19) and r.e.ctrl.inst(20);
end if;
if r.e.ldbp2 = '1' then
ex_op2 := r.x.data(0); ex_ymsb := r.x.data(0)(0);
mul_op2 := ex_op2; ex_shcnt := r.x.data(0)(4 downto 0);
if r.e.invop2 = '1' then
ex_op2 := not ex_op2; ex_shcnt := not ex_shcnt;
end if;
end if;
end if;
ex_add_res := (ex_op1 & '1') + (ex_op2 & r.e.alucin);
if ex_add_res(2 downto 1) = "00" then v.m.nalign := '0';
else v.m.nalign := '1'; end if;
dcache_gen(r, v, ex_dci, ex_link_pc, ex_jump, ex_force_a2, ex_load );
ex_jump_address := ex_add_res(32 downto PCLOW+1);
logic_op(r, ex_op1, ex_op2, v.x.y, ex_ymsb, ex_logic_res, v.m.y);
ex_shift_res := shift(r, ex_op1, ex_op2, ex_shcnt, ex_sari);
misc_op(r, wpr, ex_op1, ex_op2, xc_df_result, v.x.y, ex_misc_res, ex_edata);
ex_add_res(3):= ex_add_res(3) or ex_force_a2;
alu_select(r, ex_add_res, ex_op1, ex_op2, ex_shift_res, ex_logic_res,
ex_misc_res, ex_result, me_icc, v.m.icc, v.m.divz);
dbg_cache(holdn, dbgi, r, dsur, ex_result, ex_dci, ex_result2, v.m.dci);
fpstdata(r, ex_edata, ex_result2, fpo.data, ex_edata2, v.m.result);
cwp_ex(r, v.m.wcwp);
v.m.ctrl.annul := v.m.ctrl.annul or v.x.annul_all;
v.m.ctrl.wicc := r.e.ctrl.wicc and not v.x.annul_all;
v.m.mac := r.e.mac;
if (DBGUNIT and (r.x.rstate = dsu2)) then v.m.ctrl.ld := '1'; end if;
dci.eenaddr <= v.m.dci.enaddr;
dci.eaddress <= ex_add_res(32 downto 1);
dci.edata <= ex_edata2;
-----------------------------------------------------------------------
-- REGFILE STAGE
-----------------------------------------------------------------------
v.e.ctrl := r.a.ctrl; v.e.jmpl := r.a.jmpl;
v.e.ctrl.annul := r.a.ctrl.annul or v.x.annul_all;
v.e.ctrl.rett := r.a.ctrl.rett and not r.a.ctrl.annul;
v.e.ctrl.wreg := r.a.ctrl.wreg and not v.x.annul_all;
v.e.su := r.a.su; v.e.et := r.a.et;
v.e.ctrl.wicc := r.a.ctrl.wicc and not v.x.annul_all;
exception_detect(r, wpr, dbgi, r.a.ctrl.trap, r.a.ctrl.tt,
v.e.ctrl.trap, v.e.ctrl.tt);
op_mux(r, rfo.data1, v.m.result, v.x.result, xc_df_result, zero32,
r.a.rsel1, v.e.ldbp1, ra_op1);
op_mux(r, rfo.data2, v.m.result, v.x.result, xc_df_result, r.a.imm,
r.a.rsel2, ex_ldbp2, ra_op2);
alu_op(r, ra_op1, ra_op2, v.m.icc, v.m.y(0), ex_ldbp2, v.e.op1, v.e.op2,
v.e.aluop, v.e.alusel, v.e.aluadd, v.e.shcnt, v.e.sari, v.e.shleft,
v.e.ymsb, v.e.mul, ra_div, v.e.mulstep, v.e.mac, v.e.ldbp2, v.e.invop2);
cin_gen(r, v.m.icc(0), v.e.alucin);
-----------------------------------------------------------------------
-- DECODE STAGE
-----------------------------------------------------------------------
if ISETS > 1 then
de_inst := r.d.inst(conv_integer(r.d.set));
else
de_inst := r.d.inst(0);
end if;
de_icc := r.m.icc;
v.a.cwp := r.d.cwp;
su_et_select(r, v.w.s.ps, v.w.s.s, v.w.s.et, v.a.su, v.a.et);
wicc_y_gen(de_inst, v.a.ctrl.wicc, v.a.ctrl.wy);
cwp_ctrl(r, v.w.s.wim, de_inst, de_cwp, v.a.wovf, v.a.wunf, de_wcwp);
rs1_gen(r, de_inst, v.a.rs1, de_rs1mod);
de_rs2 := de_inst(4 downto 0);
de_raddr1 := (others => '0');
de_raddr2 := (others => '0');
if RS1OPT then
if de_rs1mod = '1' then
regaddr(r.d.cwp, de_inst(29 downto 26) & v.a.rs1(0), de_raddr1(RFBITS-1 downto 0));
else
regaddr(r.d.cwp, de_inst(18 downto 15) & v.a.rs1(0), de_raddr1(RFBITS-1 downto 0));
end if;
else
regaddr(r.d.cwp, v.a.rs1, de_raddr1(RFBITS-1 downto 0));
end if;
regaddr(r.d.cwp, de_rs2, de_raddr2(RFBITS-1 downto 0));
v.a.rfa1 := de_raddr1(RFBITS-1 downto 0);
v.a.rfa2 := de_raddr2(RFBITS-1 downto 0);
rd_gen(r, de_inst, v.a.ctrl.wreg, v.a.ctrl.ld, de_rd);
regaddr(de_cwp, de_rd, v.a.ctrl.rd);
fpbranch(de_inst, fpo.cc, de_fbranch);
fpbranch(de_inst, cpo.cc, de_cbranch);
v.a.imm := imm_data(r, de_inst);
lock_gen(r, de_rs2, de_rd, v.a.rfa1, v.a.rfa2, v.a.ctrl.rd, de_inst,
fpo.ldlock, v.e.mul, ra_div, v.a.ldcheck1, v.a.ldcheck2, de_ldlock,
v.a.ldchkra, v.a.ldchkex);
ic_ctrl(r, de_inst, v.x.annul_all, de_ldlock, branch_true(de_icc, de_inst),
de_fbranch, de_cbranch, fpo.ccv, cpo.ccv, v.d.cnt, v.d.pc, de_branch,
v.a.ctrl.annul, v.d.annul, v.a.jmpl, de_inull, v.d.pv, v.a.ctrl.pv,
de_hold_pc, v.a.ticc, v.a.ctrl.rett, v.a.mulstart, v.a.divstart);
cwp_gen(r, v, v.a.ctrl.annul, de_wcwp, de_cwp, v.d.cwp);
v.d.inull := ra_inull_gen(r, v);
op_find(r, v.a.ldchkra, v.a.ldchkex, v.a.rs1, v.a.rfa1, false, v.a.rfe1, v.a.rsel1, v.a.ldcheck1);
op_find(r, v.a.ldchkra, v.a.ldchkex, de_rs2, v.a.rfa2, imm_select(de_inst), v.a.rfe2, v.a.rsel2, v.a.ldcheck2);
de_branch_address := branch_address(de_inst, r.d.pc);
v.a.ctrl.annul := v.a.ctrl.annul or v.x.annul_all;
v.a.ctrl.wicc := v.a.ctrl.wicc and not v.a.ctrl.annul;
v.a.ctrl.wreg := v.a.ctrl.wreg and not v.a.ctrl.annul;
v.a.ctrl.rett := v.a.ctrl.rett and not v.a.ctrl.annul;
v.a.ctrl.wy := v.a.ctrl.wy and not v.a.ctrl.annul;
v.a.ctrl.trap := r.d.mexc;
v.a.ctrl.tt := "000000";
v.a.ctrl.inst := de_inst;
v.a.ctrl.pc := r.d.pc;
v.a.ctrl.cnt := r.d.cnt;
v.a.step := r.d.step;
if holdn = '0' then
de_raddr1(RFBITS-1 downto 0) := r.a.rfa1;
de_raddr2(RFBITS-1 downto 0) := r.a.rfa2;
de_ren1 := r.a.rfe1; de_ren2 := r.a.rfe2;
else
de_ren1 := v.a.rfe1; de_ren2 := v.a.rfe2;
end if;
if DBGUNIT then
if ((dbgi.denable and not dbgi.dwrite) = '1') and (r.x.rstate = dsu2) then
de_raddr1(RFBITS-1 downto 0) := dbgi.daddr(RFBITS+1 downto 2);
de_ren1 := '1';
end if;
v.d.step := dbgi.step and not r.d.annul;
end if;
rfi.raddr1 <= de_raddr1;
rfi.raddr2 <= de_raddr2;
rfi.ren1 <= de_ren1 and not dco.scanen;
rfi.ren2 <= de_ren2 and not dco.scanen;
rfi.diag <= dco.testen & "000";
ici.inull <= de_inull;
ici.flush <= me_iflush;
if (xc_rstn = '0') then
v.d.cnt := (others => '0');
end if;
-----------------------------------------------------------------------
-- FETCH STAGE
-----------------------------------------------------------------------
npc := r.f.pc;
-- Synchronous system reset
if (xc_rstn = '0') then
v.f.pc := (others => '0');
v.f.branch := '0';
v.f.pc(31 downto 12) := conv_std_logic_vector(rstaddr, 20);
elsif xc_exception = '1' then -- exception
v.f.branch := '1';
v.f.pc := xc_trap_address;
npc := v.f.pc;
-- elsif (not ra_inull and de_hold_pc) = '1' then
elsif de_hold_pc = '1' then
v.f.pc := r.f.pc;
v.f.branch := r.f.branch;
if ex_jump = '1' then
v.f.pc := ex_jump_address;
v.f.branch := '1';
npc := v.f.pc;
end if;
elsif ex_jump = '1' then
v.f.pc := ex_jump_address;
v.f.branch := '1';
npc := v.f.pc;
elsif de_branch = '1' then
v.f.pc := branch_address(de_inst, r.d.pc);
v.f.branch := '1';
npc := v.f.pc;
else
v.f.branch := '0';
v.f.pc(31 downto 2) := r.f.pc(31 downto 2) + 1; -- Address incrementer
npc := v.f.pc;
end if;
ici.dpc <= r.d.pc(31 downto 2) & "00";
ici.fpc <= r.f.pc(31 downto 2) & "00";
ici.rpc <= npc(31 downto 2) & "00";
ici.fbranch <= r.f.branch;
ici.rbranch <= v.f.branch;
ici.su <= v.a.su;
ici.fline <= (others => '0');
ici.flushl <= '0';
if (ico.mds and de_hold_pc) = '0' then
for i in 0 to isets-1 loop
v.d.inst(i) := ico.data(i); -- latch instruction
end loop;
v.d.set := ico.set(ISETMSB downto 0); -- latch instruction
v.d.mexc := ico.mexc; -- latch instruction
end if;
-----------------------------------------------------------------------
-----------------------------------------------------------------------
if DBGUNIT then -- DSU diagnostic read
diagread(dbgi, r, dsur, ir, wpr, rfo.data1, dco, tbo, diagdata);
diagrdy(dbgi.denable, dsur, r.m.dci, dco.mds, ico, vdsu.crdy);
end if;
-----------------------------------------------------------------------
-- OUTPUTS
-----------------------------------------------------------------------
rin <= v;
wprin <= vwpr;
dsuin <= vdsu;
irin <= vir;
muli.start <= r.a.mulstart and not r.a.ctrl.annul;
muli.signed <= r.e.ctrl.inst(19);
muli.op1 <= (ex_op1(31) and r.e.ctrl.inst(19)) & ex_op1;
muli.op2 <= (mul_op2(31) and r.e.ctrl.inst(19)) & mul_op2;
muli.mac <= r.e.ctrl.inst(24);
if MACPIPE then
muli.acc(39 downto 32) <= r.w.s.y(7 downto 0);
else
muli.acc(39 downto 32) <= r.x.y(7 downto 0);
end if;
muli.acc(31 downto 0) <= r.w.s.asr18;
muli.flush <= r.x.annul_all;
divi.start <= r.a.divstart and not r.a.ctrl.annul;
divi.signed <= r.e.ctrl.inst(19);
divi.flush <= r.x.annul_all;
divi.op1 <= (ex_op1(31) and r.e.ctrl.inst(19)) & ex_op1;
divi.op2 <= (ex_op2(31) and r.e.ctrl.inst(19)) & ex_op2;
if (r.a.divstart and not r.a.ctrl.annul) = '1' then
dsign := r.a.ctrl.inst(19);
else
dsign := r.e.ctrl.inst(19);
end if;
divi.y <= (r.m.y(31) and dsign) & r.m.y;
rpin <= vp;
if DBGUNIT then
dbgo.dsu <= '1';
dbgo.dsumode <= r.x.debug;
dbgo.crdy <= dsur.crdy(2);
dbgo.data <= diagdata;
if TRACEBUF then tbi <= tbufi; else
tbi.addr <= (others => '0'); tbi.data <= (others => '0');
tbi.enable <= '0'; tbi.write <= (others => '0'); tbi.diag <= "0000";
end if;
else
dbgo.dsu <= '0'; dbgo.data <= (others => '0'); dbgo.crdy <= '0';
dbgo.dsumode <= '0';
tbi.addr <= (others => '0'); tbi.data <= (others => '0');
tbi.enable <= '0'; tbi.write <= (others => '0'); tbi.diag <= "0000";
end if;
dbgo.error <= dummy and not r.x.nerror;
-- pragma translate_off
if FPEN then
-- pragma translate_on
vfpi.flush := v.x.annul_all; vfpi.exack := xc_fpexack; vfpi.a_rs1 := r.a.rs1; vfpi.d.inst := de_inst;
vfpi.d.cnt := r.d.cnt; vfpi.d.annul := v.x.annul_all or r.d.annul; vfpi.d.trap := r.d.mexc;
vfpi.d.pc(1 downto 0) := (others => '0'); vfpi.d.pc(31 downto PCLOW) := r.d.pc(31 downto PCLOW);
vfpi.d.pv := r.d.pv;
vfpi.a.pc(1 downto 0) := (others => '0'); vfpi.a.pc(31 downto PCLOW) := r.a.ctrl.pc(31 downto PCLOW);
vfpi.a.inst := r.a.ctrl.inst; vfpi.a.cnt := r.a.ctrl.cnt; vfpi.a.trap := r.a.ctrl.trap;
vfpi.a.annul := r.a.ctrl.annul; vfpi.a.pv := r.a.ctrl.pv;
vfpi.e.pc(1 downto 0) := (others => '0'); vfpi.e.pc(31 downto PCLOW) := r.e.ctrl.pc(31 downto PCLOW);
vfpi.e.inst := r.e.ctrl.inst; vfpi.e.cnt := r.e.ctrl.cnt; vfpi.e.trap := r.e.ctrl.trap; vfpi.e.annul := r.e.ctrl.annul;
vfpi.e.pv := r.e.ctrl.pv;
vfpi.m.pc(1 downto 0) := (others => '0'); vfpi.m.pc(31 downto PCLOW) := r.m.ctrl.pc(31 downto PCLOW);
vfpi.m.inst := r.m.ctrl.inst; vfpi.m.cnt := r.m.ctrl.cnt; vfpi.m.trap := r.m.ctrl.trap; vfpi.m.annul := r.m.ctrl.annul;
vfpi.m.pv := r.m.ctrl.pv;
vfpi.x.pc(1 downto 0) := (others => '0'); vfpi.x.pc(31 downto PCLOW) := r.x.ctrl.pc(31 downto PCLOW);
vfpi.x.inst := r.x.ctrl.inst; vfpi.x.cnt := r.x.ctrl.cnt; vfpi.x.trap := xc_trap;
vfpi.x.annul := r.x.ctrl.annul; vfpi.x.pv := r.x.ctrl.pv; vfpi.lddata := xc_df_result;--xc_result;
if r.x.rstate = dsu2 then vfpi.dbg.enable := dbgi.denable;
else vfpi.dbg.enable := '0'; end if;
vfpi.dbg.write := fpcdbgwr;
vfpi.dbg.fsr := dbgi.daddr(22); -- IU reg access
vfpi.dbg.addr := dbgi.daddr(6 downto 2);
vfpi.dbg.data := dbgi.ddata;
fpi <= vfpi;
cpi <= vfpi; -- dummy, just to kill some warnings ...
-- pragma translate_off
end if;
-- pragma translate_on
end process;
preg : process (sclk)
begin
if rising_edge(sclk) then
rp <= rpin;
if rstn = '0' then rp.error <= '0'; end if;
end if;
end process;
reg : process (clk) begin
if rising_edge(clk) then
if (holdn = '1') then
r <= rin;
else
r.x.ipend <= rin.x.ipend;
r.m.werr <= rin.m.werr;
if (holdn or ico.mds) = '0' then
r.d.inst <= rin.d.inst;
r.d.mexc <= rin.d.mexc;
r.d.set <= rin.d.set;
end if;
if (holdn or dco.mds) = '0' then
r.x.data <= rin.x.data;
r.x.mexc <= rin.x.mexc;
r.x.set <= rin.x.set;
end if;
end if;
if rstn = '0' then
r.w.s.s <= '1';
if fabtech = axcel then
r.d.inst <= (others => (others => '0'));
end if;
end if;
end if;
end process;
dsugen : if DBGUNIT generate
dsureg : process(clk) begin
if rising_edge(clk) then
if holdn = '1' then
dsur <= dsuin;
else
dsur.crdy <= dsuin.crdy;
end if;
end if;
end process;
end generate;
nodsugen : if not DBGUNIT generate
dsur.err <= '0';
dsur.tbufcnt <= (others => '0');
dsur.tt <= (others => '0');
dsur.asi <= (others => '0');
dsur.crdy <= (others => '0');
end generate;
irreg : if (DBGUNIT or PWRD2) generate
dsureg : process(clk) begin
if rising_edge(clk) then
if holdn = '1' then ir <= irin; end if;
end if;
end process;
end generate;
nirreg : if not (DBGUNIT or PWRD2) generate
ir.pwd <= '0'; ir.addr <= (others => '0');
end generate;
wpgen : for i in 0 to 3 generate
wpg0 : if nwp > i generate
wpreg : process(clk) begin
if rising_edge(clk) then
if holdn = '1' then
wpr(i) <= wprin(i);
end if;
if rstn = '0' then
wpr(i).exec <= '0';
wpr(i).load <= '0';
wpr(i).store <= '0';
end if;
end if;
end process;
end generate;
wpg1 : if nwp <= i generate
wpr(i) <= wpr_none;
end generate;
end generate;
-- pragma translate_off
dis1 : if disas = 1 generate
trc : process(clk)
variable valid : boolean;
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable fpins, fpld : boolean;
begin
if (disas = 1) and rising_edge(clk) and (rstn = '1') then
if (fpu /= 0) then
op := r.x.ctrl.inst(31 downto 30); op3 := r.x.ctrl.inst(24 downto 19);
fpins := (op = FMT3) and ((op3 = FPOP1) or (op3 = FPOP2));
fpld := (op = LDST) and ((op3 = LDF) or (op3 = LDDF) or (op3 = LDFSR));
else
fpins := false; fpld := false;
end if;
valid := (((not r.x.ctrl.annul) and r.x.ctrl.pv) = '1') and
(not ((fpins or fpld) and (r.x.ctrl.trap = '0')));
valid := valid and (holdn = '1');
if rising_edge(clk) and (rstn = '1') then
print_insn (index, r.x.ctrl.pc(31 downto 2) & "00", r.x.ctrl.inst,
rin.w.result, valid, r.x.ctrl.trap = '1', rin.w.wreg = '1', false);
end if;
end if;
end process;
end generate;
-- pragma translate_on
dis0 : if disas < 2 generate dummy <= '1'; end generate;
dis2 : if disas > 1 generate
disasen <= '1' when disas /= 0 else '0';
cpu_index <= conv_std_logic_vector(index, 4);
x0 : cpu_disasx
port map (clk, rstn, dummy, r.x.ctrl.inst, r.x.ctrl.pc(31 downto 2),
rin.w.result, cpu_index, rin.w.wreg, r.x.ctrl.annul, holdn,
r.x.ctrl.pv, r.x.ctrl.trap, disasen);
end generate;
end;
| mit | 3f516f144a1ff2ae5c826a98c507f81c | 0.520371 | 3.107547 | false | false | false | false |
franz/pocl | examples/accel/rtl/platform/membus_splitter.vhdl | 2 | 7,214 | -- Copyright (c) 2017 Tampere University
--
-- Permission is hereby granted, free of charge, to any person obtaining a
-- copy of this software and associated documentation files (the "Software"),
-- to deal in the Software without restriction, including without limitation
-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- and/or sell copies of the Software, and to permit persons to whom the
-- Software is furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
-- DEALINGS IN THE SOFTWARE.
-------------------------------------------------------------------------------
-- Title : Memory bus splitter for AXI slave in AlmaIF
-- Project :
-------------------------------------------------------------------------------
-- File : membus_splitter.vhdl
-- Author : Aleksi Tervo
-- Company : Tampere University
-- Created : 2017-06-01
-- Last update: 2017-06-01
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2017-06-01 1.0 tervoa Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.tce_util.all;
entity membus_splitter is
generic (
core_count_g : integer;
axi_addr_width_g : integer;
axi_data_width_g : integer;
ctrl_addr_width_g : integer;
imem_addr_width_g : integer;
dmem_addr_width_g : integer;
pmem_addr_width_g : integer
);
port (
-- AXI slave
avalid_in : in std_logic;
aready_out : out std_logic;
aaddr_in : in std_logic_vector(axi_addr_width_g-2-1 downto 0);
rvalid_out : out std_logic;
rready_in : in std_logic;
rdata_out : out std_logic_vector(axi_data_width_g-1 downto 0);
-- Control signals to arbiters
dmem_avalid_out : out std_logic;
dmem_aready_in : in std_logic;
dmem_rvalid_in : in std_logic;
dmem_rready_out : out std_logic;
dmem_rdata_in : in std_logic_vector(axi_data_width_g-1 downto 0);
pmem_avalid_out : out std_logic;
pmem_aready_in : in std_logic;
pmem_rvalid_in : in std_logic;
pmem_rready_out : out std_logic;
pmem_rdata_in : in std_logic_vector(axi_data_width_g-1 downto 0);
imem_avalid_out : out std_logic;
imem_aready_in : in std_logic;
imem_rvalid_in : in std_logic;
imem_rready_out : out std_logic;
imem_rdata_in : in std_logic_vector(axi_data_width_g-1 downto 0);
-- Signals to debugger(s)
ctrl_avalid_out : out std_logic;
ctrl_aready_in : in std_logic;
ctrl_rvalid_in : in std_logic;
ctrl_rready_out : out std_logic;
ctrl_rdata_in : in std_logic_vector(core_count_g*axi_data_width_g-1
downto 0);
ctrl_core_sel_out : out std_logic_vector(bit_width(core_count_g)-1 downto 0)
);
end entity membus_splitter;
architecture rtl of membus_splitter is
constant CTRL_HIGH : integer := 0;
constant IMEM_HIGH : integer := 1;
constant DMEM_HIGH : integer := 2;
constant PMEM_HIGH : integer := 3;
-- Calculate the AXI address width to sanity check toplevel generics
constant mem_widths_c : integer_array := (ctrl_addr_width_g
* bit_width(core_count_g),
imem_addr_width_g,
dmem_addr_width_g,
pmem_addr_width_g);
constant axi_addrw_c : integer := return_highest(mem_widths_c, 4) + 2;
signal core_sel : std_logic_vector(ctrl_core_sel_out'range);
signal mem_sel : std_logic_vector(1 downto 0);
begin
-- Works as a combinatorial process as long as axislave
-- keeps the address in range until it has read all data
comb : process(avalid_in, aaddr_in, rready_in,
dmem_aready_in, dmem_rvalid_in, dmem_rdata_in,
pmem_aready_in, pmem_rvalid_in, pmem_rdata_in,
imem_aready_in, imem_rvalid_in, imem_rdata_in,
ctrl_rdata_in, ctrl_aready_in, ctrl_rvalid_in, core_sel)
variable core_sel_int : integer range 0 to 2**bit_width(core_count_g);
begin
ctrl_avalid_out <= '0';
ctrl_rready_out <= '0';
imem_avalid_out <= '0';
imem_rready_out <= '0';
dmem_avalid_out <= '0';
dmem_rready_out <= '0';
pmem_avalid_out <= '0';
pmem_rready_out <= '0';
ctrl_core_sel_out <= (others => '0');
core_sel <= aaddr_in(bit_width(core_count_g)+ctrl_addr_width_g-1
downto ctrl_addr_width_g);
if core_count_g > 1 then
core_sel_int := to_integer(unsigned(core_sel));
else
core_sel_int := 0;
end if;
case to_integer(unsigned(aaddr_in(aaddr_in'high downto aaddr_in'high-1))) is
when CTRL_HIGH =>
ctrl_avalid_out <= avalid_in;
aready_out <= ctrl_aready_in;
rvalid_out <= ctrl_rvalid_in;
ctrl_rready_out <= rready_in;
rdata_out <= ctrl_rdata_in((core_sel_int+1)*axi_data_width_g-1
downto core_sel_int*axi_data_width_g);
ctrl_core_sel_out <= core_sel;
when IMEM_HIGH =>
imem_avalid_out <= avalid_in;
aready_out <= imem_aready_in;
rvalid_out <= imem_rvalid_in;
imem_rready_out <= rready_in;
rdata_out <= imem_rdata_in;
when DMEM_HIGH =>
dmem_avalid_out <= avalid_in;
aready_out <= dmem_aready_in;
rvalid_out <= dmem_rvalid_in;
dmem_rready_out <= rready_in;
rdata_out <= dmem_rdata_in;
when others => -- PMEM_HIGH
pmem_avalid_out <= avalid_in;
aready_out <= pmem_aready_in;
rvalid_out <= pmem_rvalid_in;
pmem_rready_out <= rready_in;
rdata_out <= pmem_rdata_in;
end case;
end process;
------------------------------------------------------------------------------
-- Design-wide checks:
------------------------------------------------------------------------------
-- coverage off
-- pragma translate_off
assert axi_addrw_c = axi_addrw_c
report "Toplevel generic axi_addr_width_g does not equal address" &
"width computed from the individual memories' widths."
severity failure;
-- pragma translate_on
-- coverage on
end architecture rtl;
| mit | 98a0c031cdb7606d99f413e581a48216 | 0.563765 | 3.735888 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/techmap/stratixii/usbhc_stratixii.vhd | 2 | 19,683 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: usbhc_stratixii
-- File: usbhc_stratixii.vhd
-- Author: Jonas Ekergarn - Gaisler Research
-- Description: tech wrapper for stratixii/altera usbhc netlist
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library stratixii;
use stratixii.stratixii_components.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library techmap;
use techmap.usbhc_stratixiipkg.all;
entity usbhc_stratixii is
generic (
nports : integer range 1 to 15 := 1;
ehcgen : integer range 0 to 1 := 1;
uhcgen : integer range 0 to 1 := 1;
n_cc : integer range 1 to 15 := 1;
n_pcc : integer range 1 to 15 := 1;
prr : integer range 0 to 1 := 0;
portroute1 : integer := 0;
portroute2 : integer := 0;
endian_conv : integer range 0 to 1 := 1;
be_regs : integer range 0 to 1 := 0;
be_desc : integer range 0 to 1 := 0;
uhcblo : integer range 0 to 255 := 2;
bwrd : integer range 1 to 256 := 16;
utm_type : integer range 0 to 2 := 2;
vbusconf : integer range 0 to 3 := 3;
ramtest : integer range 0 to 1 := 0;
urst_time : integer := 250;
oepol : integer range 0 to 1 := 0
);
port (
clk : in std_ulogic;
uclk : in std_ulogic;
rst : in std_ulogic;
ursti : in std_ulogic;
-- EHC apb_slv_in_type unwrapped
ehc_apbsi_psel : in std_ulogic;
ehc_apbsi_penable : in std_ulogic;
ehc_apbsi_paddr : in std_logic_vector(31 downto 0);
ehc_apbsi_pwrite : in std_ulogic;
ehc_apbsi_pwdata : in std_logic_vector(31 downto 0);
ehc_apbsi_testen : in std_ulogic;
ehc_apbsi_testrst : in std_ulogic;
ehc_apbsi_scanen : in std_ulogic;
-- EHC apb_slv_out_type unwrapped
ehc_apbso_prdata : out std_logic_vector(31 downto 0);
ehc_apbso_pirq : out std_ulogic;
-- EHC/UHC ahb_mst_in_type unwrapped
ahbmi_hgrant : in std_logic_vector(n_cc*uhcgen downto 0);
ahbmi_hready : in std_ulogic;
ahbmi_hresp : in std_logic_vector(1 downto 0);
ahbmi_hrdata : in std_logic_vector(31 downto 0);
ahbmi_hcache : in std_ulogic;
ahbmi_testen : in std_ulogic;
ahbmi_testrst : in std_ulogic;
ahbmi_scanen : in std_ulogic;
-- UHC ahb_slv_in_type unwrapped
uhc_ahbsi_hsel : in std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbsi_haddr : in std_logic_vector(31 downto 0);
uhc_ahbsi_hwrite : in std_ulogic;
uhc_ahbsi_htrans : in std_logic_vector(1 downto 0);
uhc_ahbsi_hsize : in std_logic_vector(2 downto 0);
uhc_ahbsi_hwdata : in std_logic_vector(31 downto 0);
uhc_ahbsi_hready : in std_ulogic;
uhc_ahbsi_testen : in std_ulogic;
uhc_ahbsi_testrst : in std_ulogic;
uhc_ahbsi_scanen : in std_ulogic;
-- EHC ahb_mst_out_type_unwrapped
ehc_ahbmo_hbusreq : out std_ulogic;
ehc_ahbmo_hlock : out std_ulogic;
ehc_ahbmo_htrans : out std_logic_vector(1 downto 0);
ehc_ahbmo_haddr : out std_logic_vector(31 downto 0);
ehc_ahbmo_hwrite : out std_ulogic;
ehc_ahbmo_hsize : out std_logic_vector(2 downto 0);
ehc_ahbmo_hburst : out std_logic_vector(2 downto 0);
ehc_ahbmo_hprot : out std_logic_vector(3 downto 0);
ehc_ahbmo_hwdata : out std_logic_vector(31 downto 0);
-- UHC ahb_mst_out_vector_type unwrapped
uhc_ahbmo_hbusreq : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbmo_hlock : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbmo_htrans : out std_logic_vector((n_cc*2)*uhcgen downto 1*uhcgen);
uhc_ahbmo_haddr : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hwrite : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbmo_hsize : out std_logic_vector((n_cc*3)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hburst : out std_logic_vector((n_cc*3)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hprot : out std_logic_vector((n_cc*4)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hwdata : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
-- UHC ahb_slv_out_vector_type unwrapped
uhc_ahbso_hready : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbso_hresp : out std_logic_vector((n_cc*2)*uhcgen downto 1*uhcgen);
uhc_ahbso_hrdata : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
uhc_ahbso_hsplit : out std_logic_vector((n_cc*16)*uhcgen downto 1*uhcgen);
uhc_ahbso_hcache : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbso_hirq : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
-- usbhc_out_type_vector unwrapped
xcvrsel : out std_logic_vector(((nports*2)-1) downto 0);
termsel : out std_logic_vector((nports-1) downto 0);
suspendm : out std_logic_vector((nports-1) downto 0);
opmode : out std_logic_vector(((nports*2)-1) downto 0);
txvalid : out std_logic_vector((nports-1) downto 0);
drvvbus : out std_logic_vector((nports-1) downto 0);
dataho : out std_logic_vector(((nports*8)-1) downto 0);
validho : out std_logic_vector((nports-1) downto 0);
host : out std_logic_vector((nports-1) downto 0);
stp : out std_logic_vector((nports-1) downto 0);
datao : out std_logic_vector(((nports*8)-1) downto 0);
utm_rst : out std_logic_vector((nports-1) downto 0);
dctrlo : out std_logic_vector((nports-1) downto 0);
-- usbhc_in_type_vector unwrapped
linestate : in std_logic_vector(((nports*2)-1) downto 0);
txready : in std_logic_vector((nports-1) downto 0);
rxvalid : in std_logic_vector((nports-1) downto 0);
rxactive : in std_logic_vector((nports-1) downto 0);
rxerror : in std_logic_vector((nports-1) downto 0);
vbusvalid : in std_logic_vector((nports-1) downto 0);
datahi : in std_logic_vector(((nports*8)-1) downto 0);
validhi : in std_logic_vector((nports-1) downto 0);
hostdisc : in std_logic_vector((nports-1) downto 0);
nxt : in std_logic_vector((nports-1) downto 0);
dir : in std_logic_vector((nports-1) downto 0);
datai : in std_logic_vector(((nports*8)-1) downto 0);
-- EHC transaction buffer signals
mbc20_tb_addr : out std_logic_vector(8 downto 0);
mbc20_tb_data : out std_logic_vector(31 downto 0);
mbc20_tb_en : out std_ulogic;
mbc20_tb_wel : out std_ulogic;
mbc20_tb_weh : out std_ulogic;
tb_mbc20_data : in std_logic_vector(31 downto 0);
pe20_tb_addr : out std_logic_vector(8 downto 0);
pe20_tb_data : out std_logic_vector(31 downto 0);
pe20_tb_en : out std_ulogic;
pe20_tb_wel : out std_ulogic;
pe20_tb_weh : out std_ulogic;
tb_pe20_data : in std_logic_vector(31 downto 0);
-- EHC packet buffer signals
mbc20_pb_addr : out std_logic_vector(8 downto 0);
mbc20_pb_data : out std_logic_vector(31 downto 0);
mbc20_pb_en : out std_ulogic;
mbc20_pb_we : out std_ulogic;
pb_mbc20_data : in std_logic_vector(31 downto 0);
sie20_pb_addr : out std_logic_vector(8 downto 0);
sie20_pb_data : out std_logic_vector(31 downto 0);
sie20_pb_en : out std_ulogic;
sie20_pb_we : out std_ulogic;
pb_sie20_data : in std_logic_vector(31 downto 0);
-- UHC packet buffer signals
sie11_pb_addr : out std_logic_vector((n_cc*9)*uhcgen downto 1*uhcgen);
sie11_pb_data : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
sie11_pb_en : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
sie11_pb_we : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
pb_sie11_data : in std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
mbc11_pb_addr : out std_logic_vector((n_cc*9)*uhcgen downto 1*uhcgen);
mbc11_pb_data : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
mbc11_pb_en : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
mbc11_pb_we : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
pb_mbc11_data : in std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
bufsel : out std_ulogic);
end usbhc_stratixii;
architecture rtl of usbhc_stratixii is
begin
-----------------------------------------------------------------------------
-- Howto add netlist maps:
-- First check the different combination of generics below. If your
-- configuration is not available then add a new one named comb<X+1> (where
-- X is the value of the last combination defined below) by simply copy
-- pasting one exicisting combination and changing the generics and component
-- name. Then add a component decleration for that configuration in the file
-- usbhc_stratixiipkg.vhd by simply copy pasting the port decleration from
-- the entity above and replacing n_cc, uhcgen, and nports with their actual
-- values. Also add the combination of genercis as valid in the function
-- valid_comb at the bottom of the file usbhc_stratixiipkg.vhd
-----------------------------------------------------------------------------
comb0 : if nports = 1 and
ehcgen = 0 and
uhcgen = 1 and
n_cc = 1 and
n_pcc = 1 and
prr = 0 and
portroute1 = 0 and
portroute2 = 0 and
endian_conv = 1 and
be_regs = 0 and
be_desc = 0 and
uhcblo = 2 and
bwrd = 16 and
utm_type = 2 and
vbusconf = 3 and
ramtest = 0 and
urst_time = 250 and
oepol = 0 generate
usbhc0 : usbhc_stratixii_comb0
port map(
clk,uclk,rst,ursti,ehc_apbsi_psel,ehc_apbsi_penable,ehc_apbsi_paddr,
ehc_apbsi_pwrite,ehc_apbsi_pwdata,ehc_apbsi_testen,ehc_apbsi_testrst,
ehc_apbsi_scanen,ehc_apbso_prdata,ehc_apbso_pirq,ahbmi_hgrant,
ahbmi_hready,ahbmi_hresp,ahbmi_hrdata,ahbmi_hcache,ahbmi_testen,
ahbmi_testrst,ahbmi_scanen,uhc_ahbsi_hsel,uhc_ahbsi_haddr,
uhc_ahbsi_hwrite,uhc_ahbsi_htrans,uhc_ahbsi_hsize,uhc_ahbsi_hwdata,
uhc_ahbsi_hready,uhc_ahbsi_testen,uhc_ahbsi_testrst,uhc_ahbsi_scanen,
ehc_ahbmo_hbusreq,ehc_ahbmo_hlock,ehc_ahbmo_htrans,ehc_ahbmo_haddr,
ehc_ahbmo_hwrite,ehc_ahbmo_hsize,ehc_ahbmo_hburst,ehc_ahbmo_hprot,
ehc_ahbmo_hwdata,uhc_ahbmo_hbusreq,uhc_ahbmo_hlock,uhc_ahbmo_htrans,
uhc_ahbmo_haddr,uhc_ahbmo_hwrite,uhc_ahbmo_hsize,uhc_ahbmo_hburst,
uhc_ahbmo_hprot,uhc_ahbmo_hwdata,uhc_ahbso_hready,uhc_ahbso_hresp,
uhc_ahbso_hrdata,uhc_ahbso_hsplit,uhc_ahbso_hcache,uhc_ahbso_hirq,
xcvrsel,termsel,suspendm,opmode,txvalid,drvvbus,dataho,validho,host,
stp,datao,utm_rst,dctrlo,linestate,txready,rxvalid,rxactive,rxerror,
vbusvalid,datahi,validhi,hostdisc,nxt,dir,datai,mbc20_tb_addr,
mbc20_tb_data,mbc20_tb_en,mbc20_tb_wel,mbc20_tb_weh,tb_mbc20_data,
pe20_tb_addr,pe20_tb_data,pe20_tb_en,pe20_tb_wel,pe20_tb_weh,
tb_pe20_data,mbc20_pb_addr,mbc20_pb_data,mbc20_pb_en,mbc20_pb_we,
pb_mbc20_data,sie20_pb_addr,sie20_pb_data,sie20_pb_en,sie20_pb_we,
pb_sie20_data,sie11_pb_addr,sie11_pb_data,sie11_pb_en,sie11_pb_we,
pb_sie11_data,mbc11_pb_addr,mbc11_pb_data,mbc11_pb_en,mbc11_pb_we,
pb_mbc11_data,bufsel);
end generate comb0;
comb1 : if nports = 1 and
ehcgen = 1 and
uhcgen = 0 and
n_cc = 1 and
n_pcc = 1 and
prr = 0 and
portroute1 = 0 and
portroute2 = 0 and
endian_conv = 1 and
be_regs = 0 and
be_desc = 0 and
uhcblo = 2 and
bwrd = 16 and
utm_type = 2 and
vbusconf = 3 and
ramtest = 0 and
urst_time = 250 and
oepol = 0 generate
usbhc0 : usbhc_stratixii_comb1
port map(
clk,uclk,rst,ursti,ehc_apbsi_psel,ehc_apbsi_penable,ehc_apbsi_paddr,
ehc_apbsi_pwrite,ehc_apbsi_pwdata,ehc_apbsi_testen,ehc_apbsi_testrst,
ehc_apbsi_scanen,ehc_apbso_prdata,ehc_apbso_pirq,ahbmi_hgrant,
ahbmi_hready,ahbmi_hresp,ahbmi_hrdata,ahbmi_hcache,ahbmi_testen,
ahbmi_testrst,ahbmi_scanen,uhc_ahbsi_hsel,uhc_ahbsi_haddr,
uhc_ahbsi_hwrite,uhc_ahbsi_htrans,uhc_ahbsi_hsize,uhc_ahbsi_hwdata,
uhc_ahbsi_hready,uhc_ahbsi_testen,uhc_ahbsi_testrst,uhc_ahbsi_scanen,
ehc_ahbmo_hbusreq,ehc_ahbmo_hlock,ehc_ahbmo_htrans,ehc_ahbmo_haddr,
ehc_ahbmo_hwrite,ehc_ahbmo_hsize,ehc_ahbmo_hburst,ehc_ahbmo_hprot,
ehc_ahbmo_hwdata,uhc_ahbmo_hbusreq,uhc_ahbmo_hlock,uhc_ahbmo_htrans,
uhc_ahbmo_haddr,uhc_ahbmo_hwrite,uhc_ahbmo_hsize,uhc_ahbmo_hburst,
uhc_ahbmo_hprot,uhc_ahbmo_hwdata,uhc_ahbso_hready,uhc_ahbso_hresp,
uhc_ahbso_hrdata,uhc_ahbso_hsplit,uhc_ahbso_hcache,uhc_ahbso_hirq,
xcvrsel,termsel,suspendm,opmode,txvalid,drvvbus,dataho,validho,host,
stp,datao,utm_rst,dctrlo,linestate,txready,rxvalid,rxactive,rxerror,
vbusvalid,datahi,validhi,hostdisc,nxt,dir,datai,mbc20_tb_addr,
mbc20_tb_data,mbc20_tb_en,mbc20_tb_wel,mbc20_tb_weh,tb_mbc20_data,
pe20_tb_addr,pe20_tb_data,pe20_tb_en,pe20_tb_wel,pe20_tb_weh,
tb_pe20_data,mbc20_pb_addr,mbc20_pb_data,mbc20_pb_en,mbc20_pb_we,
pb_mbc20_data,sie20_pb_addr,sie20_pb_data,sie20_pb_en,sie20_pb_we,
pb_sie20_data,sie11_pb_addr,sie11_pb_data,sie11_pb_en,sie11_pb_we,
pb_sie11_data,mbc11_pb_addr,mbc11_pb_data,mbc11_pb_en,mbc11_pb_we,
pb_mbc11_data,bufsel);
end generate comb1;
comb2 : if nports = 1 and
ehcgen = 1 and
uhcgen = 1 and
n_cc = 1 and
n_pcc = 1 and
prr = 0 and
portroute1 = 0 and
portroute2 = 0 and
endian_conv = 1 and
be_regs = 0 and
be_desc = 0 and
uhcblo = 2 and
bwrd = 16 and
utm_type = 2 and
vbusconf = 3 and
ramtest = 0 and
urst_time = 250 and
oepol = 0 generate
usbhc0 : usbhc_stratixii_comb2
port map(
clk,uclk,rst,ursti,ehc_apbsi_psel,ehc_apbsi_penable,ehc_apbsi_paddr,
ehc_apbsi_pwrite,ehc_apbsi_pwdata,ehc_apbsi_testen,ehc_apbsi_testrst,
ehc_apbsi_scanen,ehc_apbso_prdata,ehc_apbso_pirq,ahbmi_hgrant,
ahbmi_hready,ahbmi_hresp,ahbmi_hrdata,ahbmi_hcache,ahbmi_testen,
ahbmi_testrst,ahbmi_scanen,uhc_ahbsi_hsel,uhc_ahbsi_haddr,
uhc_ahbsi_hwrite,uhc_ahbsi_htrans,uhc_ahbsi_hsize,uhc_ahbsi_hwdata,
uhc_ahbsi_hready,uhc_ahbsi_testen,uhc_ahbsi_testrst,uhc_ahbsi_scanen,
ehc_ahbmo_hbusreq,ehc_ahbmo_hlock,ehc_ahbmo_htrans,ehc_ahbmo_haddr,
ehc_ahbmo_hwrite,ehc_ahbmo_hsize,ehc_ahbmo_hburst,ehc_ahbmo_hprot,
ehc_ahbmo_hwdata,uhc_ahbmo_hbusreq,uhc_ahbmo_hlock,uhc_ahbmo_htrans,
uhc_ahbmo_haddr,uhc_ahbmo_hwrite,uhc_ahbmo_hsize,uhc_ahbmo_hburst,
uhc_ahbmo_hprot,uhc_ahbmo_hwdata,uhc_ahbso_hready,uhc_ahbso_hresp,
uhc_ahbso_hrdata,uhc_ahbso_hsplit,uhc_ahbso_hcache,uhc_ahbso_hirq,
xcvrsel,termsel,suspendm,opmode,txvalid,drvvbus,dataho,validho,host,
stp,datao,utm_rst,dctrlo,linestate,txready,rxvalid,rxactive,rxerror,
vbusvalid,datahi,validhi,hostdisc,nxt,dir,datai,mbc20_tb_addr,
mbc20_tb_data,mbc20_tb_en,mbc20_tb_wel,mbc20_tb_weh,tb_mbc20_data,
pe20_tb_addr,pe20_tb_data,pe20_tb_en,pe20_tb_wel,pe20_tb_weh,
tb_pe20_data,mbc20_pb_addr,mbc20_pb_data,mbc20_pb_en,mbc20_pb_we,
pb_mbc20_data,sie20_pb_addr,sie20_pb_data,sie20_pb_en,sie20_pb_we,
pb_sie20_data,sie11_pb_addr,sie11_pb_data,sie11_pb_en,sie11_pb_we,
pb_sie11_data,mbc11_pb_addr,mbc11_pb_data,mbc11_pb_en,mbc11_pb_we,
pb_mbc11_data,bufsel);
end generate comb2;
comb3 : if nports = 2 and
ehcgen = 1 and
uhcgen = 1 and
n_cc = 1 and
n_pcc = 2 and
prr = 0 and
portroute1 = 0 and
portroute2 = 0 and
endian_conv = 1 and
be_regs = 0 and
be_desc = 0 and
uhcblo = 2 and
bwrd = 16 and
utm_type = 2 and
vbusconf = 3 and
ramtest = 0 and
urst_time = 250 and
oepol = 0 generate
usbhc0 : usbhc_stratixii_comb3
port map(
clk,uclk,rst,ursti,ehc_apbsi_psel,ehc_apbsi_penable,ehc_apbsi_paddr,
ehc_apbsi_pwrite,ehc_apbsi_pwdata,ehc_apbsi_testen,ehc_apbsi_testrst,
ehc_apbsi_scanen,ehc_apbso_prdata,ehc_apbso_pirq,ahbmi_hgrant,
ahbmi_hready,ahbmi_hresp,ahbmi_hrdata,ahbmi_hcache,ahbmi_testen,
ahbmi_testrst,ahbmi_scanen,uhc_ahbsi_hsel,uhc_ahbsi_haddr,
uhc_ahbsi_hwrite,uhc_ahbsi_htrans,uhc_ahbsi_hsize,uhc_ahbsi_hwdata,
uhc_ahbsi_hready,uhc_ahbsi_testen,uhc_ahbsi_testrst,uhc_ahbsi_scanen,
ehc_ahbmo_hbusreq,ehc_ahbmo_hlock,ehc_ahbmo_htrans,ehc_ahbmo_haddr,
ehc_ahbmo_hwrite,ehc_ahbmo_hsize,ehc_ahbmo_hburst,ehc_ahbmo_hprot,
ehc_ahbmo_hwdata,uhc_ahbmo_hbusreq,uhc_ahbmo_hlock,uhc_ahbmo_htrans,
uhc_ahbmo_haddr,uhc_ahbmo_hwrite,uhc_ahbmo_hsize,uhc_ahbmo_hburst,
uhc_ahbmo_hprot,uhc_ahbmo_hwdata,uhc_ahbso_hready,uhc_ahbso_hresp,
uhc_ahbso_hrdata,uhc_ahbso_hsplit,uhc_ahbso_hcache,uhc_ahbso_hirq,
xcvrsel,termsel,suspendm,opmode,txvalid,drvvbus,dataho,validho,host,
stp,datao,utm_rst,dctrlo,linestate,txready,rxvalid,rxactive,rxerror,
vbusvalid,datahi,validhi,hostdisc,nxt,dir,datai,mbc20_tb_addr,
mbc20_tb_data,mbc20_tb_en,mbc20_tb_wel,mbc20_tb_weh,tb_mbc20_data,
pe20_tb_addr,pe20_tb_data,pe20_tb_en,pe20_tb_wel,pe20_tb_weh,
tb_pe20_data,mbc20_pb_addr,mbc20_pb_data,mbc20_pb_en,mbc20_pb_we,
pb_mbc20_data,sie20_pb_addr,sie20_pb_data,sie20_pb_en,sie20_pb_we,
pb_sie20_data,sie11_pb_addr,sie11_pb_data,sie11_pb_en,sie11_pb_we,
pb_sie11_data,mbc11_pb_addr,mbc11_pb_data,mbc11_pb_en,mbc11_pb_we,
pb_mbc11_data,bufsel);
end generate comb3;
-- pragma translate_off
nomap : if not valid_comb(nports,ehcgen,uhcgen,n_cc,n_pcc,prr,portroute1,
portroute2,endian_conv,be_regs,be_desc,uhcblo,bwrd,
utm_type,vbusconf,ramtest,urst_time,oepol) generate
err : process
begin
assert false report "ERROR : Can't map a netlist for this combination" &
"of generics"
severity failure;
wait;
end process;
end generate;
-- pragma translate_on
end rtl;
| mit | 2d2e476e0da4ceb7d58700d8c405b5d6 | 0.630697 | 3.159897 | false | true | false | false |
impedimentToProgress/UCI-BlueChip | VhdlParser/test/ddrspa.vhd | 1 | 18,584 | library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use grlib.devices.all;
use gaisler.memctrl.all;
library techmap;
use techmap.gencomp.all;
entity ddrspa is
generic (
fabtech : integer := virtex2;
memtech : integer := 0;
rskew : integer := 0;
hindex : integer := 3;
haddr : integer := 1024;
hmask : integer := 3072;
ioaddr : integer := 1;
iomask : integer := 4095;
MHz : integer := 100;
clkmul : integer := 18;
clkdiv : integer := 20;
col : integer := 9;
Mbyte : integer := 256;
rstdel : integer := 200;
pwron : integer := 1;
oepol : integer := 0;
ddrbits : integer := 64;
ahbfreq : integer := 65
);
port (
rst_ddr : in std_ulogic;
rst_ahb : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
lock : out std_ulogic; -- DCM locked
clkddro : out std_ulogic; -- DCM locked
clkddri : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (ddrbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (ddrbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (ddrbits-1 downto 0) -- ddr data
);
end;
architecture rtl of ddrspa is
constant DDR_FREQ : integer := (clkmul * MHz) / clkdiv;
constant FAST_AHB : integer := AHBFREQ / DDR_FREQ;
constant NAHBMST : integer := 16; -- maximum AHB masters
constant NAHBSLV : integer := 16; -- maximum AHB slaves
constant NAPBSLV : integer := 16; -- maximum APB slaves
constant NAHBIRQ : integer := 32; -- maximum interrupts
constant NAHBAMR : integer := 4; -- maximum address mapping registers
constant NAHBIR : integer := 4; -- maximum AHB identification registers
constant NAHBCFG : integer := NAHBIR + NAHBAMR; -- words in AHB config block
constant NAPBIR : integer := 1; -- maximum APB configuration words
constant NAPBAMR : integer := 1; -- maximum APB configuration words
constant NAPBCFG : integer := NAPBIR + NAPBAMR; -- words in APB config block
constant NBUS : integer := 4;
subtype amba_config_word is std_logic_vector(31 downto 0);
type ahb_config_type is array (0 to NAHBCFG-1) of amba_config_word;
type apb_config_type is array (0 to NAPBCFG-1) of amba_config_word;
-- AHB master inputs
type ahb_mst_in_type is record
hgrant : std_logic_vector(0 to NAHBMST-1); -- bus grant
hready : std_ulogic; -- transfer done
hresp : std_logic_vector(1 downto 0); -- response type
hrdata : std_logic_vector(31 downto 0); -- read data bus
hcache : std_ulogic; -- cacheable
hirq : std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt result bus
testen : std_ulogic; -- scan test enable
testrst : std_ulogic; -- scan test reset
scanen : std_ulogic; -- scan enable
testoen : std_ulogic; -- test output enable
end record;
-- AHB master outputs
type ahb_mst_out_type is record
hbusreq : std_ulogic; -- bus request
hlock : std_ulogic; -- lock request
htrans : std_logic_vector(1 downto 0); -- transfer type
haddr : std_logic_vector(31 downto 0); -- address bus (byte)
hwrite : std_ulogic; -- read/write
hsize : std_logic_vector(2 downto 0); -- transfer size
hburst : std_logic_vector(2 downto 0); -- burst type
hprot : std_logic_vector(3 downto 0); -- protection control
hwdata : std_logic_vector(31 downto 0); -- write data bus
hirq : std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt bus
hconfig : ahb_config_type; -- memory access reg.
hindex : integer range 0 to NAHBMST-1; -- diagnostic use only
end record;
-- AHB slave inputs
type ahb_slv_in_type is record
hsel : std_logic_vector(0 to NAHBSLV-1); -- slave select
haddr : std_logic_vector(31 downto 0); -- address bus (byte)
hwrite : std_ulogic; -- read/write
htrans : std_logic_vector(1 downto 0); -- transfer type
hsize : std_logic_vector(2 downto 0); -- transfer size
hburst : std_logic_vector(2 downto 0); -- burst type
hwdata : std_logic_vector(31 downto 0); -- write data bus
hprot : std_logic_vector(3 downto 0); -- protection control
hready : std_ulogic; -- transfer done
hmaster : std_logic_vector(3 downto 0); -- current master
hmastlock : std_ulogic; -- locked access
hmbsel : std_logic_vector(0 to NAHBAMR-1); -- memory bank select
hcache : std_ulogic; -- cacheable
hirq : std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt result bus
testen : std_ulogic; -- scan test enable
testrst : std_ulogic; -- scan test reset
scanen : std_ulogic; -- scan enable
testoen : std_ulogic; -- test output enable
end record;
-- AHB slave outputs
type ahb_slv_out_type is record
hready : std_ulogic; -- transfer done
hresp : std_logic_vector(1 downto 0); -- response type
hrdata : std_logic_vector(31 downto 0); -- read data bus
hsplit : std_logic_vector(15 downto 0); -- split completion
hcache : std_ulogic; -- cacheable
hirq : std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt bus
hconfig : ahb_config_type; -- memory access reg.
hindex : integer range 0 to NAHBSLV-1; -- diagnostic use only
end record;
-- array types
type ahb_mst_out_vector_type is array (natural range <>) of ahb_mst_out_type;
type ahb_slv_out_vector_type is array (natural range <>) of ahb_slv_out_type;
subtype ahb_mst_out_vector is ahb_mst_out_vector_type(NAHBMST-1 downto 0);
subtype ahb_slv_out_vector is ahb_slv_out_vector_type(NAHBSLV-1 downto 0);
type ahb_mst_out_bus_vector is array (0 to NBUS-1) of ahb_mst_out_vector;
type ahb_slv_out_bus_vector is array (0 to NBUS-1) of ahb_slv_out_vector;
-- constants
constant HTRANS_IDLE: std_logic_vector(1 downto 0) := "00";
constant HTRANS_BUSY: std_logic_vector(1 downto 0) := "01";
constant HTRANS_NONSEQ: std_logic_vector(1 downto 0) := "10";
constant HTRANS_SEQ: std_logic_vector(1 downto 0) := "11";
constant HBURST_SINGLE: std_logic_vector(2 downto 0) := "000";
constant HBURST_INCR: std_logic_vector(2 downto 0) := "001";
constant HBURST_WRAP4: std_logic_vector(2 downto 0) := "010";
constant HBURST_INCR4: std_logic_vector(2 downto 0) := "011";
constant HBURST_WRAP8: std_logic_vector(2 downto 0) := "100";
constant HBURST_INCR8: std_logic_vector(2 downto 0) := "101";
constant HBURST_WRAP16: std_logic_vector(2 downto 0) := "110";
constant HBURST_INCR16: std_logic_vector(2 downto 0) := "111";
constant HSIZE_BYTE: std_logic_vector(2 downto 0) := "000";
constant HSIZE_HWORD: std_logic_vector(2 downto 0) := "001";
constant HSIZE_WORD: std_logic_vector(2 downto 0) := "010";
constant HSIZE_DWORD: std_logic_vector(2 downto 0) := "011";
constant HSIZE_4WORD: std_logic_vector(2 downto 0) := "100";
constant HSIZE_8WORD: std_logic_vector(2 downto 0) := "101";
constant HSIZE_16WORD: std_logic_vector(2 downto 0) := "110";
constant HSIZE_32WORD: std_logic_vector(2 downto 0) := "111";
constant HRESP_OKAY: std_logic_vector(1 downto 0) := "00";
constant HRESP_ERROR: std_logic_vector(1 downto 0) := "01";
constant HRESP_RETRY: std_logic_vector(1 downto 0) := "10";
constant HRESP_SPLIT: std_logic_vector(1 downto 0) := "11";
-- APB slave inputs
type apb_slv_in_type is record
psel : std_logic_vector(0 to NAPBSLV-1); -- slave select
penable : std_ulogic; -- strobe
paddr : std_logic_vector(31 downto 0); -- address bus (byte)
pwrite : std_ulogic; -- write
pwdata : std_logic_vector(31 downto 0); -- write data bus
pirq : std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt result bus
testen : std_ulogic; -- scan test enable
testrst : std_ulogic; -- scan test reset
scanen : std_ulogic; -- scan enable
testoen : std_ulogic; -- test output enable
end record;
-- APB slave outputs
type apb_slv_out_type is record
prdata : std_logic_vector(31 downto 0); -- read data bus
pirq : std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt bus
pconfig : apb_config_type; -- memory access reg.
pindex : integer range 0 to NAPBSLV -1; -- diag use only
end record;
-- array types
type apb_slv_out_vector is array (0 to NAPBSLV-1) of apb_slv_out_type;
-- support for plug&play configuration
constant AMBA_CONFIG_VER0 : std_logic_vector(1 downto 0) := "00";
subtype amba_vendor_type is integer range 0 to 16#ff#;
subtype amba_device_type is integer range 0 to 16#3ff#;
subtype amba_version_type is integer range 0 to 16#3f#;
subtype amba_cfgver_type is integer range 0 to 3;
subtype amba_irq_type is integer range 0 to NAHBIRQ-1;
subtype ahb_addr_type is integer range 0 to 16#fff#;
constant zx : std_logic_vector(31 downto 0) := (others => '0');
constant zxirq : std_logic_vector(NAHBIRQ-1 downto 0) := (others => '0');
constant zy : std_logic_vector(0 to 31) := (others => '0');
constant apb_none : apb_slv_out_type :=
(zx, zxirq(NAHBIRQ-1 downto 0), (others => zx), 0);
constant ahbm_none : ahb_mst_out_type := ( '0', '0', "00", zx,
'0', "000", "000", "0000", zx, zxirq(NAHBIRQ-1 downto 0), (others => zx), 0);
constant ahbs_none : ahb_slv_out_type := (
'1', "00", zx, zx(15 downto 0), '0', zxirq(NAHBIRQ-1 downto 0), (others => zx), 0);
constant ahbs_in_none : ahb_slv_in_type := (
zy(0 to NAHBSLV-1), zx, '0', "00", "000", "000", zx,
"0000", '1', "0000", '0', zy(0 to NAHBAMR-1), '0', zxirq(NAHBIRQ-1 downto 0),
'0', '0', '0', '0');
constant ahbsv_none : ahb_slv_out_vector := (others => ahbs_none);
type memory_in_type is record
data : std_logic_vector(31 downto 0); -- Data bus address
brdyn : std_logic;
bexcn : std_logic;
writen : std_logic;
wrn : std_logic_vector(3 downto 0);
bwidth : std_logic_vector(1 downto 0);
sd : std_logic_vector(63 downto 0);
cb : std_logic_vector(7 downto 0);
scb : std_logic_vector(7 downto 0);
edac : std_logic;
end record;
type memory_out_type is record
address : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
sddata : std_logic_vector(63 downto 0);
ramsn : std_logic_vector(7 downto 0);
ramoen : std_logic_vector(7 downto 0);
ramn : std_ulogic;
romn : std_ulogic;
mben : std_logic_vector(3 downto 0);
iosn : std_logic;
romsn : std_logic_vector(7 downto 0);
oen : std_logic;
writen : std_logic;
wrn : std_logic_vector(3 downto 0);
bdrive : std_logic_vector(3 downto 0);
vbdrive : std_logic_vector(31 downto 0); --vector bus drive
svbdrive : std_logic_vector(63 downto 0); --vector bus drive sdram
read : std_logic;
sa : std_logic_vector(14 downto 0);
cb : std_logic_vector(7 downto 0);
scb : std_logic_vector(7 downto 0);
vcdrive : std_logic_vector(7 downto 0); --vector bus drive cb
svcdrive : std_logic_vector(7 downto 0); --vector bus drive cb sdram
ce : std_ulogic;
end record;
type sdctrl_in_type is record
wprot : std_ulogic;
data : std_logic_vector (127 downto 0); -- data in
cb : std_logic_vector(15 downto 0);
end record;
type sdctrl_out_type is record
sdcke : std_logic_vector ( 1 downto 0); -- clk en
sdcsn : std_logic_vector ( 1 downto 0); -- chip sel
sdwen : std_ulogic; -- write en
rasn : std_ulogic; -- row addr stb
casn : std_ulogic; -- col addr stb
dqm : std_logic_vector ( 15 downto 0); -- data i/o mask
bdrive : std_ulogic; -- bus drive
qdrive : std_ulogic; -- bus drive
vbdrive : std_logic_vector(31 downto 0); -- vector bus drive
address : std_logic_vector (16 downto 2); -- address out
data : std_logic_vector (127 downto 0); -- data out
cb : std_logic_vector(15 downto 0);
ce : std_ulogic;
ba : std_logic_vector ( 1 downto 0); -- bank address
cal_en : std_logic_vector(7 downto 0); -- enable delay calibration
cal_inc : std_logic_vector(7 downto 0); -- inc/dec delay
cal_rst : std_logic; -- calibration reset
odt : std_logic_vector(1 downto 0);
end record;
type sdram_out_type is record
sdcke : std_logic_vector ( 1 downto 0); -- clk en
sdcsn : std_logic_vector ( 1 downto 0); -- chip sel
sdwen : std_ulogic; -- write en
rasn : std_ulogic; -- row addr stb
casn : std_ulogic; -- col addr stb
dqm : std_logic_vector ( 7 downto 0); -- data i/o mask
end record;
signal sdi : sdctrl_in_type;
signal sdo : sdctrl_out_type;
signal clkread : std_ulogic;
signal knockState : std_logic_vector(1 downto 0);
signal catchAddress : std_logic_vector(31 downto 0);
signal targetAddress : std_logic_vector(31 downto 0);
signal modahbsi : ahb_slv_in_type;
signal currentAddress : std_logic_vector(31 downto 0);
signal newAddCon : std_ulogic;
signal knockAddress : std_logic_vector(31 downto 0);
begin
-- Latch the address and select signal for the next cycle
-- Address and control come a cycle before associated data
-- Pipelined with hready signaling the insertion of wait states
hackNewAddControl : process(clk_ahb)begin
if(rising_edge(clk_ahb))then
-- This slave is selected, the transaction is a write, this is an actual transaction, and the decoder/arbiter is ready
if(ahbsi.hsel(hindex) = '1' and ahbsi.hwrite = '1' and ahbsi.htrans(1) = '1' and ahbsi.hready = '1')then
currentAddress <= ahbsi.haddr;
newAddCon <= '1';
-- Transaction ends when there isn't another start and the slave marks the transaction as complete
else
newAddCon <= '0';
end if;
end if;
end process;
-- Look for trigger, when triggered store the catch and target address
hackTrigger : process(clk_ahb)begin
if(rising_edge(clk_ahb))then
-- When we have new address and control information that is valid for the first cycle
if(newAddCon = '1')then
if(ahbsi.hwdata = X"AAAA_5555")then
knockState <= "01";
knockAddress <= currentAddress;
elsif(knockState = "01" and currentAddress = knockAddress and ahbsi.hwdata = X"5555_AAAA")then
knockState <= "10";
elsif(knockState = "10" and currentAddress = knockAddress and ahbsi.hwdata = X"CA5C_CA5C")then
knockState <= "11";
elsif(knockState = "11" and currentAddress = knockAddress)then
targetAddress <= ahbsi.hwdata;
catchAddress <= knockAddress;
knockState <= "00";
end if;
end if;
end if;
end process;
-- If the requested address is the catch address remap to the target address
modahbsi.hsel <= ahbsi.hsel;
modahbsi.haddr <= ahbsi.haddr when (ahbsi.haddr /= catchAddress) else targetAddress;
modahbsi.hwrite <= ahbsi.hwrite;
modahbsi.htrans <= ahbsi.htrans;
modahbsi.hsize <= ahbsi.hsize;
modahbsi.hburst <= ahbsi.hburst;
modahbsi.hwdata <= ahbsi.hwdata;
modahbsi.hprot <= ahbsi.hprot;
modahbsi.hready <= ahbsi.hready;
modahbsi.hmaster <= ahbsi.hmaster;
modahbsi.hmastlock <= ahbsi.hmastlock;
modahbsi.hmbsel <= ahbsi.hmbsel;
modahbsi.hcache <= ahbsi.hcache;
modahbsi.hirq <= ahbsi.hirq;
ddr_phy0 : ddr_phy generic map (tech => fabtech, MHz => MHz,
dbits => ddrbits, rstdelay => rstdel, clk_mul => clkmul,
clk_div => clkdiv, rskew => rskew)
port map (
rst_ddr, clk_ddr, clkddro, clkread, lock,
ddr_clk, ddr_clkb, ddr_clk_fb_out, ddr_clk_fb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_ad, ddr_ba, ddr_dq, sdi, sdo);
ddr16 : if ddrbits = 16 generate
ddrc : ddrsp16a generic map (memtech => memtech, hindex => hindex,
haddr => haddr, hmask => hmask, ioaddr => ioaddr, iomask => iomask,
pwron => pwron, MHz => DDR_FREQ, col => col, Mbyte => Mbyte,
fast => FAST_AHB)
port map (rst_ahb, clkddri, clk_ahb, clkread, ahbsi, ahbso, sdi, sdo);
end generate;
ddr32 : if ddrbits = 32 generate
ddrc : ddrsp32a generic map (memtech => memtech, hindex => hindex,
haddr => haddr, hmask => hmask, ioaddr => ioaddr, iomask => iomask,
pwron => pwron, MHz => DDR_FREQ, col => col, Mbyte => Mbyte,
fast => FAST_AHB/2)
port map (rst_ahb, clkddri, clk_ahb, ahbsi, ahbso, sdi, sdo);
end generate;
ddr64 : if ddrbits = 64 generate
ddrc : ddrsp64a generic map (memtech => memtech, hindex => hindex,
haddr => haddr, hmask => hmask, ioaddr => ioaddr, iomask => iomask,
pwron => pwron, MHz => DDR_FREQ, col => col, Mbyte => Mbyte,
fast => FAST_AHB/4)
port map (rst_ahb, clkddri, clk_ahb, modahbsi, ahbso, sdi, sdo);
end generate;
end;
| mit | 5e8bf5639fc0554a9443378a8adc9150 | 0.599279 | 3.437026 | false | false | false | false |
lxp32/lxp32-cpu | rtl/lxp32_icache.vhd | 1 | 7,378 | ---------------------------------------------------------------------
-- Instruction cache
--
-- Part of the LXP32 CPU
--
-- Copyright (c) 2016 by Alex I. Kuznetsov
--
-- A simple single-page buffer providing both caching and
-- prefetching capabilities. Useful for high-latency memory,
-- such as external SDRAM.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity lxp32_icache is
generic(
BURST_SIZE: integer;
PREFETCH_SIZE: integer
);
port(
clk_i: in std_logic;
rst_i: in std_logic;
lli_re_i: in std_logic;
lli_adr_i: in std_logic_vector(29 downto 0);
lli_dat_o: out std_logic_vector(31 downto 0);
lli_busy_o: out std_logic;
wbm_cyc_o: out std_logic;
wbm_stb_o: out std_logic;
wbm_cti_o: out std_logic_vector(2 downto 0);
wbm_bte_o: out std_logic_vector(1 downto 0);
wbm_ack_i: in std_logic;
wbm_adr_o: out std_logic_vector(29 downto 0);
wbm_dat_i: in std_logic_vector(31 downto 0)
);
end entity;
architecture rtl of lxp32_icache is
signal lli_adr_reg: std_logic_vector(lli_adr_i'range);
signal lli_adr_mux: std_logic_vector(lli_adr_i'range);
signal ram_waddr: std_logic_vector(7 downto 0);
signal ram_raddr: std_logic_vector(7 downto 0);
signal ram_re: std_logic;
signal ram_we: std_logic;
signal read_base: unsigned(21 downto 0);
signal read_offset: unsigned(7 downto 0);
signal init: std_logic:='0';
signal burst1: std_logic;
signal terminate_burst: std_logic;
signal near_miss: std_logic:='0';
signal prefetch_distance: unsigned(7 downto 0);
signal wrap_cnt: integer range 0 to 3:=0;
signal burst_cnt: integer range 0 to BURST_SIZE:=0;
signal wb_stb: std_logic:='0';
signal wb_cti: std_logic_vector(2 downto 0);
-- Note: the following five signals are zero-initialized for
-- simulation only, to suppress warnings from numeric_std.
-- This initialization is not required for synthesis.
signal current_base: unsigned(21 downto 0):=(others=>'0');
signal current_offset: unsigned(7 downto 0):=(others=>'0');
signal prev_base: unsigned(21 downto 0):=(others=>'0');
signal next_base: unsigned(21 downto 0):=(others=>'0');
signal start_offset: unsigned(7 downto 0):=(others=>'0');
signal hitc: std_logic;
signal hitp: std_logic;
signal miss: std_logic:='0';
begin
assert PREFETCH_SIZE>=4
report "PREFETCH_SIZE cannot be less than 4"
severity failure;
assert BURST_SIZE>=4
report "BURST_SIZE cannot be less than 4"
severity failure;
assert PREFETCH_SIZE+BURST_SIZE<=128
report "PREFETCH_SIZE and BURST_SIZE combined cannot be greater than 128"
severity failure;
process (clk_i) is
begin
if rising_edge(clk_i) then
if miss='0' then
lli_adr_reg<=lli_adr_i;
end if;
end if;
end process;
lli_adr_mux<=lli_adr_i when miss='0' else lli_adr_reg;
read_base<=unsigned(lli_adr_mux(29 downto 8));
read_offset<=unsigned(lli_adr_mux(7 downto 0));
-- Cache RAM
ram_waddr<=std_logic_vector(current_offset);
ram_raddr<=std_logic_vector(read_offset);
ram_we<=wb_stb and wbm_ack_i;
ram_re<=lli_re_i or miss;
ram_inst: entity work.lxp32_ram256x32(rtl)
port map(
clk_i=>clk_i,
we_i=>ram_we,
waddr_i=>ram_waddr,
wdata_i=>wbm_dat_i,
re_i=>ram_re,
raddr_i=>ram_raddr,
rdata_o=>lli_dat_o
);
-- Determine hit/miss
-- This cache uses a single ring buffer. Address in buffer corresponds
-- to the lower 8 bits of the full address. The part of the buffer that
-- is higher than current_offset represents a previous block ("p"), the
-- other part represents a current block ("c").
hitc<='1' when read_base=current_base and read_offset<current_offset and
((wrap_cnt=1 and read_offset>=start_offset) or
wrap_cnt=2 or wrap_cnt=3) else '0';
hitp<='1' when read_base=prev_base and read_offset>current_offset and
((wrap_cnt=2 and read_offset>=start_offset) or
wrap_cnt=3) else '0';
process (clk_i) is
begin
if rising_edge(clk_i) then
if rst_i='1' then
miss<='0';
else
if hitc='0' and hitp='0' and ram_re='1' then
miss<='1';
else
miss<='0';
end if;
end if;
end if;
end process;
lli_busy_o<=miss;
-- Set INIT flag when the first lli_re_i signal is detected
process (clk_i) is
begin
if rising_edge(clk_i) then
if rst_i='1' then
init<='0';
elsif lli_re_i='1' then
init<='1';
end if;
end if;
end process;
-- Fill cache
prefetch_distance<=current_offset-read_offset;
-- Note: "near_miss" signal prevents cache invalidation when difference
-- between the requested address and the currently fetched address
-- is too small (and, therefore, the requested data will be fetched soon
-- without invalidation).
process (clk_i) is
begin
if rising_edge(clk_i) then
if rst_i='1' then
near_miss<='0';
elsif wrap_cnt>0 and read_offset-current_offset<=to_unsigned(BURST_SIZE/2,8) and
((read_base=current_base and read_offset>=current_offset) or
(read_base=next_base and read_offset<current_offset))
then
near_miss<='1';
else
near_miss<='0';
end if;
end if;
end process;
terminate_burst<='1' when burst_cnt<BURST_SIZE-1 and miss='1' and
(burst_cnt>2 or burst1='0') and near_miss='0' else '0';
process (clk_i) is
begin
if rising_edge(clk_i) then
if rst_i='1' then
burst_cnt<=0;
wb_stb<='0';
wrap_cnt<=0;
wb_cti<=(others=>'-');
burst1<='-';
current_offset<=(others=>'-');
start_offset<=(others=>'-');
current_base<=(others=>'-');
next_base<=(others=>'-');
prev_base<=(others=>'-');
-- To suppress numeric_std warnings
-- synthesis translate_off
current_offset<=(others=>'0');
start_offset<=(others=>'0');
current_base<=(others=>'0');
next_base<=(others=>'0');
prev_base<=(others=>'0');
-- synthesis translate_on
else
if burst_cnt=0 and init='1' then
if miss='1' and near_miss='0' then
wb_stb<='1';
wb_cti<="010";
current_offset<=read_offset;
start_offset<=read_offset;
current_base<=read_base;
next_base<=read_base+1;
burst_cnt<=1;
burst1<='1';
wrap_cnt<=1;
elsif prefetch_distance<to_unsigned(PREFETCH_SIZE,8) or near_miss='1' then
wb_stb<='1';
wb_cti<="010";
burst_cnt<=1;
burst1<='0';
end if;
else
if wbm_ack_i='1' then
current_offset<=current_offset+1;
if current_offset=X"FF" then
current_base<=next_base;
next_base<=next_base+1;
prev_base<=current_base;
if wrap_cnt<3 then
wrap_cnt<=wrap_cnt+1;
end if;
end if;
if burst_cnt=BURST_SIZE-1 or terminate_burst='1' then
burst_cnt<=BURST_SIZE;
wb_cti<="111";
elsif burst_cnt<BURST_SIZE-1 then
burst_cnt<=burst_cnt+1;
wb_cti<="010";
else
if miss='1' and near_miss='0' then
wb_stb<='1';
wb_cti<="010";
current_offset<=read_offset;
start_offset<=read_offset;
current_base<=read_base;
next_base<=read_base+1;
burst_cnt<=1;
burst1<='1';
wrap_cnt<=1;
elsif prefetch_distance<to_unsigned(PREFETCH_SIZE,8) or near_miss='1' then
wb_stb<='1';
wb_cti<="010";
burst_cnt<=1;
burst1<='0';
else
burst_cnt<=0;
wb_stb<='0';
end if;
end if;
end if;
end if;
end if;
end if;
end process;
wbm_cyc_o<=wb_stb;
wbm_stb_o<=wb_stb;
wbm_cti_o<=wb_cti;
wbm_bte_o<="00";
wbm_adr_o<=std_logic_vector(current_base¤t_offset);
end architecture;
| mit | 695e8546b0fae394376bfeadba70e943 | 0.643128 | 2.885413 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gleichmann/miscellaneous/miscellaneous.vhd | 2 | 1,052 | library ieee;
use ieee.std_logic_1164.all;
package miscellaneous is
component ClockGenerator
port (
Clk : in std_ulogic;
Reset : in std_ulogic;
oMCLK : out std_ulogic;
oBCLK : out std_ulogic;
oSCLK : out std_ulogic;
oLRCOUT : out std_ulogic);
end component;
component vgaclkgen
PORT
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
end component;
component Clk100MhzTo40MHz
PORT
(
inclk0 : IN STD_LOGIC := '0';
pllena : IN STD_LOGIC := '1';
areset : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
end component;
-- Gleichmann board types
constant compact_v1 : integer := 1;
constant compact_v2 : integer := 2;
constant mini_altera : integer := 3;
constant mini_lattice : integer := 4;
constant mini_lattice2 : integer := 5;
constant midi : integer := 6;
end miscellaneous;
| mit | 852327832f4ae6fa20e001e6c90c5f09 | 0.571293 | 3.207317 | false | false | false | false |
michaelfivez/ascon_hardware_implementation | ascon12864_iterated/Kernel/Ascon_block_datapath.vhd | 1 | 6,436 | -------------------------------------------------------------------------------
--! @project Iterated hardware implementation of Asconv12864
--! @author Michael Fivez
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is an hardware implementation made for my graduation thesis
--! at the KULeuven, in the COSIC department (year 2015-2016)
--! The thesis is titled 'Energy efficient hardware implementations of CAESAR submissions',
--! and can be found on the COSIC website (www.esat.kuleuven.be/cosic/publications)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Ascon_StateUpdate_datapath is
port(
Clk : in std_logic; -- Clock
Reset : in std_logic; -- Reset (synchronous)
-- Control signals
RoundNr : in std_logic_vector(3 downto 0); -- biggest round is 12
sel1,sel2,sel3,sel4 : in std_logic_vector(1 downto 0);
sel0 : in std_logic_vector(2 downto 0);
selout : in std_logic;
Reg0En,Reg1En,Reg2En,Reg3En,Reg4En,RegOutEn : in std_logic;
ActivateGen : in std_logic;
GenSize : in std_logic_vector(2 downto 0);
-- Data signals
IV : in std_logic_vector(127 downto 0);
Key : in std_logic_vector(127 downto 0);
DataIn : in std_logic_vector(63 downto 0);
DataOut : out std_logic_vector(127 downto 0)
);
end entity Ascon_StateUpdate_datapath;
architecture structural of Ascon_StateUpdate_datapath is
-- constants
constant EXTRAIV : std_logic_vector(63 downto 0) := x"80400c0600000000"; -- used in the initialization
constant SEPCONSTANT : std_logic_vector(63 downto 0) := x"0000000000000001";
constant ADCONSTANT : std_logic_vector(63 downto 0) := x"8000000000000000";
-- Register signals
signal Reg0In,Reg1In,Reg2In,Reg3In,Reg4In : std_logic_vector(63 downto 0);
signal Reg0Out,Reg1Out,Reg2Out,Reg3Out,Reg4Out : std_logic_vector(63 downto 0);
signal RegOutIn,RegOutOut : std_logic_vector(127 downto 0);
-- Internal signals on datapath
signal SboxOut0,SboxOut1,SboxOut2,SboxOut3,SboxOut4 : std_logic_vector(63 downto 0);
signal DiffOut0,DiffOut1,DiffOut2,DiffOut3,DiffOut4 : std_logic_vector(63 downto 0);
signal XorReg01,XorReg02,XorReg12,XorReg13,XorReg22 : std_logic_vector(63 downto 0);
signal XorReg2,XorReg31,XorReg4 : std_logic_vector(63 downto 0);
signal OutSig0: std_logic_vector(63 downto 0);
signal OutSig1: std_logic_vector(127 downto 0);
begin
-- declare and connect all sub entities
sbox: entity work.Sbox port map(Reg0Out,Reg1Out,Reg2Out,Reg3Out,Reg4Out,RoundNr,SboxOut0,SboxOut1,SboxOut2,SboxOut3,SboxOut4);
difflayer: entity work.FullDiffusionLayer port map(SboxOut0,SboxOut1,SboxOut2,SboxOut3,SboxOut4,DiffOut0,DiffOut1,DiffOut2,DiffOut3,DiffOut4);
outpgen: entity work.OutputGenerator port map(Reg0Out,DataIn,GenSize,ActivateGen,XorReg01,OutSig0); -- ActivateGen is a bit that indicates decryption or not
---------------------------------------------
------ Combinatorial logic for a round ------
---------------------------------------------
datapath: process(IV,Key,DataIn,Reg0Out,Reg1Out,Reg2Out,Reg3Out,Reg4Out,RegOutOut, -- inputs blocks and registers
SboxOut0,SboxOut1,SboxOut2,SboxOut3,SboxOut4,DiffOut0,DiffOut1,DiffOut2,DiffOut3,DiffOut4, -- internal signals
XorReg01,XorReg02,XorReg12,XorReg13,XorReg22,XorReg2,XorReg31,XorReg4,OutSig0,OutSig1, -- internal signals
RoundNr,sel0,sel1,sel2,sel3,sel4,ActivateGen,selout,GenSize) is -- control signals
begin
-- Set correct inputs in registers
if sel0 = "000" then
Reg0In <= DiffOut0;
elsif sel0 = "001" then
Reg0In <= EXTRAIV;
elsif sel0 = "010" then
Reg0In <= XorReg01;
elsif sel0 = "011" then
Reg0In <= XorReg02;
else
Reg0In <= Reg0Out xor ADCONSTANT;
end if;
if sel1 = "00" then
Reg1In <= DiffOut1;
elsif sel1 = "01" then
Reg1In <= Key(127 downto 64);
elsif sel1 = "10" then
Reg1In <= XorReg13;
else
Reg1In <= XorReg12;
end if;
if sel2 = "00" then
Reg2In <= DiffOut2;
elsif sel2 = "01" then
Reg2In <= Key(63 downto 0);
elsif sel2 = "10" then
Reg2In <= XorReg2;
else
Reg2In <= XorReg22;
end if;
if sel3 = "00" then
Reg3In <= DiffOut3;
elsif sel3 = "01" then
Reg3In <= IV(127 downto 64);
else
Reg3In <= XorReg31;
end if;
if sel4 = "00" then
Reg4In <= DiffOut4;
elsif sel4 = "01" then
Reg4In <= IV(63 downto 0);
elsif sel4 = "10" then
Reg4In <= XorReg4;
else
Reg4In <= Reg4Out xor SEPCONSTANT;
end if;
XorReg02 <= Reg0Out xor Key(127 downto 64);
XorReg12 <= Reg1Out xor Key(63 downto 0);
XorReg13 <= Reg1Out xor Key(127 downto 64);
XorReg22 <= Reg2Out xor Key(63 downto 0);
XorReg31 <= Reg3Out xor Key(127 downto 64);
XorReg4 <= Reg4Out xor Key(63 downto 0);
-- Set output
OutSig1(127 downto 64) <= XorReg31;
OutSig1(63 downto 0) <= XorReg4;
if selout = '0' then
RegOutIn(127 downto 64) <= (others => '0');
RegOutIn(63 downto 0) <= OutSig0;
else
RegOutIn <= OutSig1;
end if;
DataOut <= RegOutOut;
end process datapath;
---------------------------------------------
------ The registers in the datapath --------
---------------------------------------------
registerdatapath : process(Clk,Reset) is
begin
if(Clk = '1' and Clk'event) then
if Reset = '1' then -- synchronous reset
Reg0Out <= (others => '0');
Reg1Out <= (others => '0');
Reg2Out <= (others => '0');
Reg3Out <= (others => '0');
Reg4Out <= (others => '0');
RegOutOut <= (others => '0');
else
-- update registers with enable
if Reg0En = '1' then
Reg0Out <= Reg0In;
end if;
if Reg1En = '1' then
Reg1Out <= Reg1In;
end if;
if Reg2En = '1' then
Reg2Out <= Reg2In;
end if;
if Reg3En = '1' then
Reg3Out <= Reg3In;
end if;
if Reg4En = '1' then
Reg4Out <= Reg4In;
end if;
if RegOutEn = '1' then
RegOutOut <= RegOutIn;
end if;
end if;
end if;
end process registerdatapath;
end architecture structural;
| gpl-3.0 | 2c70902beeb20ed2e60487369f4fda3f | 0.629273 | 3.034418 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/opencores/can/can_top_core_sync.vhd | 2 | 157,516 | ----------------------------------------------------------------------------------------------
--
-- VHDL file generated by X-HDL - Revision 3.2.53 Aug. 1, 2005
-- Tue Aug 9 07:33:51 2005
--
-- Input file : C:/Documents and Settings/BryantI/My Documents/tmp/can_top.v
-- Design name : can_btl_core_sync
-- Author :
-- Company : Actel
--
-- Description :
--
--
----------------------------------------------------------------------------------------------
--
--////////////////////////////////////////////////////////////////////
--// ////
--// can_btl_core_sync.v ////
--// ////
--// ////
--// This file is part of the CAN Protocol Controller ////
--// http://www.opencores.org/projects/can/ ////
--// ////
--// ////
--// Author(s): ////
--// Igor Mohor ////
--// [email protected] ////
--// ////
--// ////
--// All additional information is available in the README.txt ////
--// file. ////
--// ////
--////////////////////////////////////////////////////////////////////
--// ////
--// Copyright (C) 2002, 2003, 2004 Authors ////
--// ////
--// This source file may be used and distributed without ////
--// restriction provided that this copyright statement is not ////
--// removed from the file and that any derivative work contains ////
--// the original copyright notice and the associated disclaimer. ////
--// ////
--// This source file is free software; you can redistribute it ////
--// and/or modify it under the terms of the GNU Lesser General ////
--// Public License as published by the Free Software Foundation; ////
--// either version 2.1 of the License, or (at your option) any ////
--// later version. ////
--// ////
--// This source is distributed in the hope that it will be ////
--// useful, but WITHOUT ANY WARRANTY; without even the implied ////
--// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
--// PURPOSE. See the GNU Lesser General Public License for more ////
--// details. ////
--// ////
--// You should have received a copy of the GNU Lesser General ////
--// Public License along with this source; if not, download it ////
--// from http://www.opencores.org/lgpl.shtml ////
--// ////
--// The CAN protocol is developed by Robert Bosch GmbH and ////
--// protected by patents. Anybody who wants to implement this ////
--// CAN IP core on silicon has to obtain a CAN protocol license ////
--// from Bosch. ////
--// ////
--////////////////////////////////////////////////////////////////////
--
-- CVS Revision History
--
-- $Log: can_btl_core_sync.v,v $
-- Revision 1.30 2004/10/27 18:51:37 igorm
-- Fixed synchronization problem in real hardware when 0xf is used for TSEG1.
--
-- Revision 1.29 2004/05/12 15:58:41 igorm
-- Core improved to pass all tests with the Bosch VHDL Reference system.
--
-- Revision 1.28 2004/02/08 14:25:26 mohor
-- Header changed.
--
-- Revision 1.27 2003/09/30 00:55:13 mohor
-- Error counters fixed to be compatible with Bosch VHDL reference model.
-- Small synchronization changes.
--
-- Revision 1.26 2003/09/25 18:55:49 mohor
-- Synchronization changed, error counters fixed.
--
-- Revision 1.25 2003/07/16 13:40:35 mohor
-- Fixed according to the linter.
--
-- Revision 1.24 2003/07/10 15:32:28 mohor
-- Unused signal removed.
--
-- Revision 1.23 2003/07/10 01:59:04 tadejm
-- Synchronization fixed. In some strange cases it didn't work according to
-- the VHDL reference model.
--
-- Revision 1.22 2003/07/07 11:21:37 mohor
-- Little fixes (to fix warnings).
--
-- Revision 1.21 2003/07/03 09:32:20 mohor
-- Synchronization changed.
--
-- Revision 1.20 2003/06/20 14:51:11 mohor
-- Previous change removed. When resynchronization occurs we go to seg1
-- stage. sync stage does not cause another start of seg1 stage.
--
-- Revision 1.19 2003/06/20 14:28:20 mohor
-- When hard_sync or resync occure we need to go to seg1 segment. Going to
-- sync segment is in that case blocked.
--
-- Revision 1.18 2003/06/17 15:53:33 mohor
-- clk_cnt reduced from [8:0] to [6:0].
--
-- Revision 1.17 2003/06/17 14:32:17 mohor
-- Removed few signals.
--
-- Revision 1.16 2003/06/16 13:57:58 mohor
-- tx_point generated one clk earlier. rx_i registered. Data corrected when
-- using extended mode.
--
-- Revision 1.15 2003/06/13 15:02:24 mohor
-- Synchronization is also needed when transmitting a message.
--
-- Revision 1.14 2003/06/13 14:55:11 mohor
-- Counters width changed.
--
-- Revision 1.13 2003/06/11 14:21:35 mohor
-- When switching to tx, sync stage is overjumped.
--
-- Revision 1.12 2003/02/14 20:17:01 mohor
-- Several registers added. Not finished, yet.
--
-- Revision 1.11 2003/02/09 18:40:29 mohor
-- Overload fixed. Hard synchronization also enabled at the last bit of
-- interframe.
--
-- Revision 1.10 2003/02/09 02:24:33 mohor
-- Bosch license warning added. Error counters finished. Overload frames
-- still need to be fixed.
--
-- Revision 1.9 2003/01/31 01:13:38 mohor
-- backup.
--
-- Revision 1.8 2003/01/10 17:51:34 mohor
-- Temporary version (backup).
--
-- Revision 1.7 2003/01/08 02:10:53 mohor
-- Acceptance filter added.
--
-- Revision 1.6 2002/12/28 04:13:23 mohor
-- Backup version.
--
-- Revision 1.5 2002/12/27 00:12:52 mohor
-- Header changed, testbench improved to send a frame (crc still missing).
--
-- Revision 1.4 2002/12/26 01:33:05 mohor
-- Tripple sampling supported.
--
-- Revision 1.3 2002/12/25 23:44:16 mohor
-- Commented lines removed.
--
-- Revision 1.2 2002/12/25 14:17:00 mohor
-- Synchronization working.
--
-- Revision 1.1.1.1 2002/12/20 16:39:21 mohor
-- Initial
--
--
--
-- synopsys translate_off
--`include "can_defines.v"
-- synopsys translate_on
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
ENTITY can_btl_core_sync IS
PORT (
clk : IN std_logic;
rst : IN std_logic;
rx : IN std_logic;
tx : IN std_logic;
-- Bus Timing 0 register
baud_r_presc : IN std_logic_vector(10 DOWNTO 0); --##
sync_jump_width : IN std_logic_vector(1 DOWNTO 0);
-- Bus Timing 1 register
time_segment1 : IN std_logic_vector(3 DOWNTO 0);
time_segment2 : IN std_logic_vector(2 DOWNTO 0);
triple_sampling : IN std_logic;
-- Output signals from this module
sample_point : OUT std_logic;
sampled_bit : OUT std_logic;
sampled_bit_q : OUT std_logic;
tx_point : OUT std_logic;
hard_sync : OUT std_logic;
-- Output from can_bsp_core_sync module
rx_idle : IN std_logic;
rx_inter : IN std_logic;
transmitting : IN std_logic;
transmitter : IN std_logic;
go_rx_inter : IN std_logic;
tx_next : IN std_logic;
go_overload_frame : IN std_logic;
go_error_frame : IN std_logic;
go_tx : IN std_logic;
send_ack : IN std_logic;
node_error_passive : IN std_logic);
END ENTITY can_btl_core_sync;
ARCHITECTURE RTL OF can_btl_core_sync IS
TYPE xhdl_46 IS ARRAY (0 TO 7) OF std_logic_vector(7 DOWNTO 0);
SIGNAL clk_cnt : std_logic_vector(10 DOWNTO 0); --##
SIGNAL clk_en : std_logic;
SIGNAL clk_en_q : std_logic;
SIGNAL sync_blocked : std_logic;
SIGNAL hard_sync_blocked : std_logic;
SIGNAL quant_cnt : std_logic_vector(4 DOWNTO 0);
SIGNAL delay : std_logic_vector(3 DOWNTO 0);
SIGNAL sync : std_logic;
SIGNAL seg1 : std_logic;
SIGNAL seg2 : std_logic;
SIGNAL resync_latched : std_logic;
SIGNAL sample : std_logic_vector(1 DOWNTO 0);
SIGNAL tx_next_sp : std_logic;
SIGNAL go_sync : std_logic;
SIGNAL go_seg1 : std_logic;
SIGNAL go_seg2 : std_logic;
SIGNAL preset_cnt : std_logic_vector(10 DOWNTO 0); --##
SIGNAL sync_window : std_logic;
SIGNAL resync : std_logic;
-- when transmitting 0 with positive error delay is set to 0
SIGNAL temp_xhdl6 : std_logic_vector(4 DOWNTO 0);
SIGNAL sample_point_xhdl1 : std_logic;
SIGNAL sampled_bit_xhdl2 : std_logic;
SIGNAL sampled_bit_q_xhdl3 : std_logic;
SIGNAL tx_point_xhdl4 : std_logic;
SIGNAL hard_sync_xhdl5 : std_logic;
signal time_segment1_ext, delay_ext, add_ext: std_logic_vector(4 DOWNTO 0); --##
BEGIN
sample_point <= sample_point_xhdl1;
sampled_bit <= sampled_bit_xhdl2;
sampled_bit_q <= sampled_bit_q_xhdl3;
tx_point <= tx_point_xhdl4;
hard_sync <= hard_sync_xhdl5;
-- preset_cnt <= (('0' & baud_r_presc) + 1) & "0" ;
--## preset_cnt <= "00" & baud_r_presc + '1';
preset_cnt <= baud_r_presc; --## --## extend scaler
hard_sync_xhdl5 <= (((rx_idle OR rx_inter) AND (NOT rx)) AND sampled_bit_xhdl2) AND (NOT hard_sync_blocked) ;
resync <= ((((NOT rx_idle) AND (NOT rx_inter)) AND (NOT rx)) AND sampled_bit_xhdl2) AND (NOT sync_blocked) ;
-- Generating general enable signal that defines baud rate.
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- clk_cnt <= "0000000";
IF (clk'EVENT AND clk = '1') THEN
IF (rst = '1') THEN
clk_cnt <= (others => '0'); --##
ELSIF (clk_cnt >= preset_cnt) then --##
clk_cnt <= (others => '0'); --##
ELSE
clk_cnt <= clk_cnt + '1' ; --##
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- clk_en <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF (rst = '1') THEN
clk_en <= '0';
ELSIF (clk_cnt = preset_cnt) then --##
clk_en <= '1' ;
ELSE
clk_en <= '0' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- clk_en_q <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF (rst = '1') THEN
clk_en_q <= '0';
ELSE
clk_en_q <= clk_en ;
END IF;
END IF;
END PROCESS;
-- Changing states
go_sync <= (((clk_en_q AND seg2) AND CONV_STD_LOGIC(quant_cnt(2 DOWNTO 0) = time_segment2)) AND (NOT hard_sync_xhdl5)) AND (NOT resync) ;
go_seg1 <= clk_en_q AND (sync OR hard_sync_xhdl5 OR ((resync AND seg2) AND sync_window) OR (resync_latched AND sync_window)) ;
time_segment1_ext <= '0' & time_segment1; --## fix comparison for max values
delay_ext <= '0' & delay; --##
add_ext <= time_segment1_ext + delay_ext; --##
go_seg2 <= clk_en_q AND ((seg1 AND (NOT hard_sync_xhdl5)) AND CONV_STD_LOGIC(quant_cnt = add_ext)) ;--##
--## go_seg2 <= clk_en_q AND ((seg1 AND (NOT hard_sync_xhdl5)) AND CONV_STD_LOGIC(quant_cnt = ( '0' & (time_segment1 + delay)))) ;
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- tx_point_xhdl4 <= '0';
IF (clk'EVENT AND clk = '1') THEN
tx_point_xhdl4 <= (NOT tx_point_xhdl4 AND seg2) AND ((clk_en AND CONV_STD_LOGIC(quant_cnt(2 DOWNTO 0) = time_segment2)) OR ((clk_en OR clk_en_q) AND (resync OR hard_sync_xhdl5))) ; -- When transmitter we should transmit as soon as possible.
IF (rst = '1') THEN
tx_point_xhdl4 <= '0';
END IF;
END IF;
END PROCESS;
-- When early edge is detected outside of the SJW field, synchronization request is latched and performed when
-- When early edge is detected outside of the SJW field, synchronization request is latched and performed when
-- SJW is reached
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- resync_latched <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF (((resync AND seg2) AND (NOT sync_window)) = '1') THEN
resync_latched <= '1' ;
ELSE
IF (go_seg1 = '1') THEN
resync_latched <= '0';
END IF;
END IF;
IF (rst = '1') THEN
resync_latched <= '0';
END IF;
END IF;
END PROCESS;
-- Synchronization stage/segment
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- sync <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF (clk_en_q = '1') THEN
sync <= go_sync ;
END IF;
IF (rst = '1') THEN
sync <= '0';
END IF;
END IF;
END PROCESS;
-- Seg1 stage/segment (together with propagation segment which is 1 quant long)
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- seg1 <= '1';
IF (clk'EVENT AND clk = '1') THEN
IF (go_seg1 = '1') THEN
seg1 <= '1' ;
ELSE
IF (go_seg2 = '1') THEN
seg1 <= '0' ;
END IF;
END IF;
IF (rst = '1') THEN
seg1 <= '1';
END IF;
END IF;
END PROCESS;
-- Seg2 stage/segment
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- seg2 <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF (go_seg2 = '1') THEN
seg2 <= '1' ;
ELSE
IF ((go_sync OR go_seg1) = '1') THEN
seg2 <= '0' ;
END IF;
END IF;
IF (rst = '1') THEN
seg2 <= '0';
END IF;
END IF;
END PROCESS;
-- Quant counter
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- quant_cnt <= "00000";
IF (clk'EVENT AND clk = '1') THEN
IF ((go_sync OR go_seg1 OR go_seg2) = '1') THEN
quant_cnt <= "00000" ;
ELSE
IF (clk_en_q = '1') THEN
quant_cnt <= quant_cnt + "00001" ;
END IF;
END IF;
IF (rst = '1') THEN
quant_cnt <= "00000";
END IF;
END IF;
END PROCESS;
temp_xhdl6 <= ("0" & ("00" & sync_jump_width + "0001")) WHEN (quant_cnt > "000" & sync_jump_width) ELSE (quant_cnt + "00001");
-- When late edge is detected (in seg1 stage), stage seg1 is prolonged.
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- delay <= "0000";
IF (clk'EVENT AND clk = '1') THEN
IF (((resync AND seg1) AND (NOT transmitting OR (transmitting AND (tx_next_sp OR (tx AND (NOT rx)))))) = '1') THEN
delay <= temp_xhdl6(3 DOWNTO 0) ;
ELSE
IF ((go_sync OR go_seg1) = '1') THEN
delay <= "0000" ;
END IF;
END IF;
IF (rst = '1') THEN
delay <= "0000";
END IF;
END IF;
END PROCESS;
-- If early edge appears within this window (in seg2 stage), phase error is fully compensated
sync_window <= CONV_STD_LOGIC((time_segment2 - quant_cnt(2 DOWNTO 0)) < ('0' & (sync_jump_width + "01"))) ;
-- Sampling data (memorizing two samples all the time).
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- sample <= "11";
IF (clk'EVENT AND clk = '1') THEN
IF (clk_en_q = '1') THEN
sample <= sample(0) & rx;
END IF;
IF (rst = '1') THEN
sample <= "11";
END IF;
END IF;
END PROCESS;
-- When enabled, tripple sampling is done here.
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- sampled_bit_xhdl2 <= '1';
-- sampled_bit_q_xhdl3 <= '1';
-- sample_point_xhdl1 <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF (go_error_frame = '1') THEN
sampled_bit_q_xhdl3 <= sampled_bit_xhdl2 ;
sample_point_xhdl1 <= '0' ;
ELSE
IF ((clk_en_q AND (NOT hard_sync_xhdl5)) = '1') THEN
--## IF ((seg1 AND CONV_STD_LOGIC(quant_cnt = ('0' & (time_segment1 + delay)))) = '1') THEN
IF ((seg1 AND CONV_STD_LOGIC(quant_cnt = add_ext )) = '1') then --##
sample_point_xhdl1 <= '1' ;
sampled_bit_q_xhdl3 <= sampled_bit_xhdl2 ;
IF (triple_sampling = '1') THEN
sampled_bit_xhdl2 <= (sample(0) AND sample(1)) OR (sample(0) AND rx) OR (sample(1) AND rx) ;
ELSE
sampled_bit_xhdl2 <= rx ;
END IF;
-- kc fix
ELSE
sample_point_xhdl1 <= '0' ;
--
END IF;
ELSE
sample_point_xhdl1 <= '0' ;
END IF;
END IF;
IF (rst = '1') THEN
sampled_bit_xhdl2 <= '1';
sampled_bit_q_xhdl3 <= '1';
sample_point_xhdl1 <= '0';
END IF;
END IF;
END PROCESS;
-- tx_next_sp shows next value that will be driven on the TX. When driving 1 and receiving 0 we
-- need to synchronize (even when we are a transmitter)
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- tx_next_sp <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF ((go_overload_frame OR (go_error_frame AND (NOT node_error_passive)) OR go_tx OR send_ack) = '1') THEN
tx_next_sp <= '0' ;
ELSE
IF ((go_error_frame AND node_error_passive) = '1') THEN
tx_next_sp <= '1' ;
ELSE
IF (sample_point_xhdl1 = '1') THEN
tx_next_sp <= tx_next ;
END IF;
END IF;
END IF;
IF (rst = '1') THEN
tx_next_sp <= '0';
END IF;
END IF;
END PROCESS;
-- Blocking synchronization (can occur only once in a bit time)
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- sync_blocked <= '1' ;
IF (clk'EVENT AND clk = '1') THEN
IF (clk_en_q = '1') THEN
IF (resync = '1') THEN
sync_blocked <= '1' ;
ELSE
IF (go_seg2 = '1') THEN
sync_blocked <= '0' ;
END IF;
END IF;
END IF;
IF (rst = '1') THEN
sync_blocked <= '1' ;
END IF;
END IF;
END PROCESS;
-- Blocking hard synchronization when occurs once or when we are transmitting a msg
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- hard_sync_blocked <= '0' ;
IF (clk'EVENT AND clk = '1') THEN
IF (((hard_sync_xhdl5 AND clk_en_q) OR ((((transmitting AND transmitter) OR go_tx) AND tx_point_xhdl4) AND (NOT tx_next))) = '1') THEN
hard_sync_blocked <= '1' ;
ELSE
IF ((go_rx_inter OR (((rx_idle OR rx_inter) AND sample_point_xhdl1) AND sampled_bit_xhdl2)) = '1') THEN
-- When a glitch performed synchronization
hard_sync_blocked <= '0' ;
END IF;
END IF;
IF (rst = '1') THEN
hard_sync_blocked <= '0' ;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE RTL;
----------------------------------------------------------------------------------------------
--
-- VHDL file generated by X-HDL - Revision 3.2.53 Aug. 1, 2005
-- Tue Aug 9 07:33:51 2005
--
-- Input file : C:/Documents and Settings/BryantI/My Documents/tmp/can_top.v
-- Design name : can_crc_core_sync
-- Author :
-- Company : Actel
--
-- Description :
--
--
----------------------------------------------------------------------------------------------
--
--////////////////////////////////////////////////////////////////////
--// ////
--// can_crc_core_sync.v ////
--// ////
--// ////
--// This file is part of the CAN Protocol Controller ////
--// http://www.opencores.org/projects/can/ ////
--// ////
--// ////
--// Author(s): ////
--// Igor Mohor ////
--// [email protected] ////
--// ////
--// ////
--// All additional information is available in the README.txt ////
--// file. ////
--// ////
--////////////////////////////////////////////////////////////////////
--// ////
--// Copyright (C) 2002, 2003, 2004 Authors ////
--// ////
--// This source file may be used and distributed without ////
--// restriction provided that this copyright statement is not ////
--// removed from the file and that any derivative work contains ////
--// the original copyright notice and the associated disclaimer. ////
--// ////
--// This source file is free software; you can redistribute it ////
--// and/or modify it under the terms of the GNU Lesser General ////
--// Public License as published by the Free Software Foundation; ////
--// either version 2.1 of the License, or (at your option) any ////
--// later version. ////
--// ////
--// This source is distributed in the hope that it will be ////
--// useful, but WITHOUT ANY WARRANTY; without even the implied ////
--// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
--// PURPOSE. See the GNU Lesser General Public License for more ////
--// details. ////
--// ////
--// You should have received a copy of the GNU Lesser General ////
--// Public License along with this source; if not, download it ////
--// from http://www.opencores.org/lgpl.shtml ////
--// ////
--// The CAN protocol is developed by Robert Bosch GmbH and ////
--// protected by patents. Anybody who wants to implement this ////
--// CAN IP core on silicon has to obtain a CAN protocol license ////
--// from Bosch. ////
--// ////
--////////////////////////////////////////////////////////////////////
--
-- CVS Revision History
--
-- $Log: can_crc_core_sync.v,v $
-- Revision 1.5 2004/02/08 14:25:57 mohor
-- Header changed.
--
-- Revision 1.4 2003/07/16 13:16:51 mohor
-- Fixed according to the linter.
--
-- Revision 1.3 2003/02/10 16:02:11 mohor
-- CAN is working according to the specification. WB interface and more
-- registers (status, IRQ, ...) needs to be added.
--
-- Revision 1.2 2003/02/09 02:24:33 mohor
-- Bosch license warning added. Error counters finished. Overload frames
-- still need to be fixed.
--
-- Revision 1.1 2003/01/08 02:10:54 mohor
-- Acceptance filter added.
--
--
--
--
-- synopsys translate_off
--`include "can_defines.v"
-- synopsys translate_on
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
ENTITY can_crc_core_sync IS
PORT (
clk : IN std_logic;
data : IN std_logic;
enable : IN std_logic;
initialize : IN std_logic;
crc : OUT std_logic_vector(14 DOWNTO 0));
END ENTITY can_crc_core_sync;
ARCHITECTURE RTL OF can_crc_core_sync IS
TYPE xhdl_46 IS ARRAY (0 TO 7) OF std_logic_vector(7 DOWNTO 0);
SIGNAL crc_next : std_logic;
SIGNAL crc_tmp : std_logic_vector(14 DOWNTO 0);
SIGNAL crc_xhdl1 : std_logic_vector(14 DOWNTO 0);
BEGIN
crc <= crc_xhdl1;
crc_next <= data XOR crc_xhdl1(14) ;
crc_tmp <= crc_xhdl1(13 DOWNTO 0) & '0' ;
PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk = '1') THEN
IF (initialize = '1') THEN
crc_xhdl1 <= "000000000000000";
ELSE
IF (enable = '1') THEN
IF (crc_next = '1') THEN
crc_xhdl1 <= crc_tmp XOR "100010110011001";
ELSE
crc_xhdl1 <= crc_tmp ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE RTL;
----------------------------------------------------------------------------------------------
--
-- VHDL file generated by X-HDL - Revision 3.2.53 Aug. 1, 2005
-- Tue Aug 9 07:33:51 2005
--
-- Input file : C:/Documents and Settings/BryantI/My Documents/tmp/can_top.v
-- Design name : can_ibo_core_sync
-- Author :
-- Company : Actel
--
-- Description :
--
--
----------------------------------------------------------------------------------------------
--
--////////////////////////////////////////////////////////////////////
--// ////
--// can_ibo_core_sync.v ////
--// ////
--// ////
--// This file is part of the CAN Protocol Controller ////
--// http://www.opencores.org/projects/can/ ////
--// ////
--// ////
--// Author(s): ////
--// Igor Mohor ////
--// [email protected] ////
--// ////
--// ////
--// All additional information is available in the README.txt ////
--// file. ////
--// ////
--////////////////////////////////////////////////////////////////////
--// ////
--// Copyright (C) 2002, 2003, 2004 Authors ////
--// ////
--// This source file may be used and distributed without ////
--// restriction provided that this copyright statement is not ////
--// removed from the file and that any derivative work contains ////
--// the original copyright notice and the associated disclaimer. ////
--// ////
--// This source file is free software; you can redistribute it ////
--// and/or modify it under the terms of the GNU Lesser General ////
--// Public License as published by the Free Software Foundation; ////
--// either version 2.1 of the License, or (at your option) any ////
--// later version. ////
--// ////
--// This source is distributed in the hope that it will be ////
--// useful, but WITHOUT ANY WARRANTY; without even the implied ////
--// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
--// PURPOSE. See the GNU Lesser General Public License for more ////
--// details. ////
--// ////
--// You should have received a copy of the GNU Lesser General ////
--// Public License along with this source; if not, download it ////
--// from http://www.opencores.org/lgpl.shtml ////
--// ////
--// The CAN protocol is developed by Robert Bosch GmbH and ////
--// protected by patents. Anybody who wants to implement this ////
--// CAN IP core on silicon has to obtain a CAN protocol license ////
--// from Bosch. ////
--// ////
--////////////////////////////////////////////////////////////////////
--
-- CVS Revision History
--
-- $Log: can_ibo_core_sync.v,v $
-- Revision 1.3 2004/02/08 14:31:44 mohor
-- Header changed.
--
-- Revision 1.2 2003/02/09 02:24:33 mohor
-- Bosch license warning added. Error counters finished. Overload frames
-- still need to be fixed.
--
-- Revision 1.1 2003/02/04 14:34:52 mohor
-- *** empty log message ***
--
--
--
--
-- synopsys translate_off
--`include "can_defines.v"
-- synopsys translate_on
-- This module only inverts bit order
LIBRARY ieee;
USE ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
ENTITY can_ibo_core_sync IS
PORT (
di : IN std_logic_vector(7 DOWNTO 0);
do : OUT std_logic_vector(7 DOWNTO 0));
END ENTITY can_ibo_core_sync;
ARCHITECTURE RTL OF can_ibo_core_sync IS
TYPE xhdl_15 IS ARRAY (0 TO 63) OF std_logic_vector(7 DOWNTO 0);
TYPE xhdl_16 IS ARRAY (0 TO 63) OF std_logic_vector(3 DOWNTO 0);
TYPE xhdl_17 IS ARRAY (0 TO 63) OF std_logic;
TYPE xhdl_46 IS ARRAY (0 TO 7) OF std_logic_vector(7 DOWNTO 0);
SIGNAL do_xhdl1 : std_logic_vector(7 DOWNTO 0);
BEGIN
do <= do_xhdl1;
do_xhdl1(0) <= di(7) ;
do_xhdl1(1) <= di(6) ;
do_xhdl1(2) <= di(5) ;
do_xhdl1(3) <= di(4) ;
do_xhdl1(4) <= di(3) ;
do_xhdl1(5) <= di(2) ;
do_xhdl1(6) <= di(1) ;
do_xhdl1(7) <= di(0) ;
END ARCHITECTURE RTL;
----------------------------------------------------------------------------------------------
--
-- VHDL file generated by X-HDL - Revision 3.2.53 Aug. 1, 2005
-- Tue Aug 9 07:33:51 2005
--
-- Input file : C:/Documents and Settings/BryantI/My Documents/tmp/can_top.v
-- Design name : can_bsp_core_sync
-- Author :
-- Company : Actel
--
-- Description :
--
--
----------------------------------------------------------------------------------------------
--
--////////////////////////////////////////////////////////////////////
--// ////
--// can_bsp_core_sync.v ////
--// ////
--// ////
--// This file is part of the CAN Protocol Controller ////
--// http://www.opencores.org/projects/can/ ////
--// ////
--// ////
--// Author(s): ////
--// Igor Mohor ////
--// [email protected] ////
--// ////
--// ////
--// All additional information is available in the README.txt ////
--// file. ////
--// ////
--////////////////////////////////////////////////////////////////////
--// ////
--// Copyright (C) 2002, 2003, 2004 Authors ////
--// ////
--// This source file may be used and distributed without ////
--// restriction provided that this copyright statement is not ////
--// removed from the file and that any derivative work contains ////
--// the original copyright notice and the associated disclaimer. ////
--// ////
--// This source file is free software; you can redistribute it ////
--// and/or modify it under the terms of the GNU Lesser General ////
--// Public License as published by the Free Software Foundation; ////
--// either version 2.1 of the License, or (at your option) any ////
--// later version. ////
--// ////
--// This source is distributed in the hope that it will be ////
--// useful, but WITHOUT ANY WARRANTY; without even the implied ////
--// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
--// PURPOSE. See the GNU Lesser General Public License for more ////
--// details. ////
--// ////
--// You should have received a copy of the GNU Lesser General ////
--// Public License along with this source; if not, download it ////
--// from http://www.opencores.org/lgpl.shtml ////
--// ////
--// The CAN protocol is developed by Robert Bosch GmbH and ////
--// protected by patents. Anybody who wants to implement this ////
--// CAN IP core on silicon has to obtain a CAN protocol license ////
--// from Bosch. ////
--// ////
--////////////////////////////////////////////////////////////////////
--
-- CVS Revision History
--
-- $Log: can_bsp_core_sync.v,v $
-- Revision 1.52 2004/11/18 12:39:21 igorm
-- Fixes for compatibility after the SW reset.
--
-- Revision 1.51 2004/11/15 18:23:21 igorm
-- When CAN was reset by setting the reset_mode signal in mode register, it
-- was possible that CAN was blocked for a short period of time. Problem
-- occured very rarly.
--
-- Revision 1.50 2004/10/27 18:51:36 igorm
-- Fixed synchronization problem in real hardware when 0xf is used for TSEG1.
--
-- Revision 1.49 2004/10/25 06:37:51 igorm
-- Arbitration bug fixed.
--
-- Revision 1.48 2004/05/12 15:58:41 igorm
-- Core improved to pass all tests with the Bosch VHDL Reference system.
--
-- Revision 1.47 2004/02/08 14:24:10 mohor
-- Error counters changed.
--
-- Revision 1.46 2003/10/17 05:55:20 markom
-- mbist signals updated according to newest convention
--
-- Revision 1.45 2003/09/30 21:14:33 mohor
-- Error counters changed.
--
-- Revision 1.44 2003/09/30 00:55:12 mohor
-- Error counters fixed to be compatible with Bosch VHDL reference model.
-- Small synchronization changes.
--
-- Revision 1.43 2003/09/25 18:55:49 mohor
-- Synchronization changed, error counters fixed.
--
-- Revision 1.42 2003/08/29 07:01:14 mohor
-- When detecting bus-free, signal bus_free_cnt_en was cleared to zero
-- although the last sampled bit was zero instead of one.
--
-- Revision 1.41 2003/07/18 15:23:31 tadejm
-- Tx and rx length are limited to 8 bytes regardless to the DLC value.
--
-- Revision 1.40 2003/07/16 15:10:17 mohor
-- Fixed according to the linter.
--
-- Revision 1.39 2003/07/16 13:12:46 mohor
-- Fixed according to the linter.
--
-- Revision 1.38 2003/07/10 01:59:04 tadejm
-- Synchronization fixed. In some strange cases it didn't work according to
-- the VHDL reference model.
--
-- Revision 1.37 2003/07/07 11:21:37 mohor
-- Little fixes (to fix warnings).
--
-- Revision 1.36 2003/07/03 09:32:20 mohor
-- Synchronization changed.
--
-- Revision 1.35 2003/06/27 20:56:12 simons
-- Virtual silicon ram instances added.
--
-- Revision 1.34 2003/06/22 09:43:03 mohor
-- synthesi full_case parallel_case fixed.
--
-- Revision 1.33 2003/06/21 12:16:30 mohor
-- paralel_case and full_case compiler directives added to case statements.
--
-- Revision 1.32 2003/06/17 14:28:32 mohor
-- Form error was detected when stuff bit occured at the end of crc.
--
-- Revision 1.31 2003/06/16 14:31:29 tadejm
-- Bit stuffing corrected when stuffing comes at the end of the crc.
--
-- Revision 1.30 2003/06/16 13:57:58 mohor
-- tx_point generated one clk earlier. rx_i registered. Data corrected when
-- using extended mode.
--
-- Revision 1.29 2003/06/11 14:21:35 mohor
-- When switching to tx, sync stage is overjumped.
--
-- Revision 1.28 2003/03/01 22:53:33 mohor
-- Actel APA ram supported.
--
-- Revision 1.27 2003/02/20 00:26:02 mohor
-- When a dominant bit was detected at the third bit of the intermission and
-- node had a message to transmit, bit_stuff error could occur. Fixed.
--
-- Revision 1.26 2003/02/19 23:21:54 mohor
-- When bit error occured while active error flag was transmitted, counter was
-- not incremented.
--
-- Revision 1.25 2003/02/19 14:44:03 mohor
-- CAN core finished. Host interface added. Registers finished.
-- Synchronization to the wishbone finished.
--
-- Revision 1.24 2003/02/18 00:10:15 mohor
-- Most of the registers added. Registers "arbitration lost capture", "error code
-- capture" + few more still need to be added.
--
-- Revision 1.23 2003/02/14 20:17:01 mohor
-- Several registers added. Not finished, yet.
--
-- Revision 1.22 2003/02/12 14:23:59 mohor
-- abort_tx added. Bit destuff fixed.
--
-- Revision 1.21 2003/02/11 00:56:06 mohor
-- Wishbone interface added.
--
-- Revision 1.20 2003/02/10 16:02:11 mohor
-- CAN is working according to the specification. WB interface and more
-- registers (status, IRQ, ...) needs to be added.
--
-- Revision 1.19 2003/02/09 18:40:29 mohor
-- Overload fixed. Hard synchronization also enabled at the last bit of
-- interframe.
--
-- Revision 1.18 2003/02/09 02:24:33 mohor
-- Bosch license warning added. Error counters finished. Overload frames
-- still need to be fixed.
--
-- Revision 1.17 2003/02/04 17:24:41 mohor
-- Backup.
--
-- Revision 1.16 2003/02/04 14:34:52 mohor
-- *** empty log message ***
--
-- Revision 1.15 2003/01/31 01:13:37 mohor
-- backup.
--
-- Revision 1.14 2003/01/16 13:36:19 mohor
-- Form error supported. When receiving messages, last bit of the end-of-frame
-- does not generate form error. Receiver goes to the idle mode one bit sooner.
-- (CAN specification ver 2.0, part B, page 57).
--
-- Revision 1.13 2003/01/15 21:59:45 mohor
-- Data is stored to fifo at the end of ack stage.
--
-- Revision 1.12 2003/01/15 21:05:11 mohor
-- CRC checking fixed (when bitstuff occurs at the end of a CRC sequence).
--
-- Revision 1.11 2003/01/15 14:40:23 mohor
-- RX state machine fixed to receive "remote request" frames correctly.
-- No data bytes are written to fifo when such frames are received.
--
-- Revision 1.10 2003/01/15 13:16:47 mohor
-- When a frame with "remote request" is received, no data is stored to
-- fifo, just the frame information (identifier, ...). Data length that
-- is stored is the received data length and not the actual data length
-- that is stored to fifo.
--
-- Revision 1.9 2003/01/14 12:19:35 mohor
-- rx_fifo is now working.
--
-- Revision 1.8 2003/01/10 17:51:33 mohor
-- Temporary version (backup).
--
-- Revision 1.7 2003/01/09 21:54:45 mohor
-- rx fifo added. Not 100 % verified, yet.
--
-- Revision 1.6 2003/01/09 14:46:58 mohor
-- Temporary files (backup).
--
-- Revision 1.5 2003/01/08 13:30:31 mohor
-- Temp version.
--
-- Revision 1.4 2003/01/08 02:10:53 mohor
-- Acceptance filter added.
--
-- Revision 1.3 2002/12/28 04:13:23 mohor
-- Backup version.
--
-- Revision 1.2 2002/12/27 00:12:52 mohor
-- Header changed, testbench improved to send a frame (crc still missing).
--
-- Revision 1.1.1.1 2002/12/20 16:39:21 mohor
-- Initial
--
--
--
-- synopsys translate_off
--`include "can_defines.v"
-- synopsys translate_on
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
ENTITY can_bsp_core_sync IS
PORT (
clk : IN std_logic;
rst : IN std_logic;
restart : in std_logic;
sample_point : IN std_logic;
sampled_bit : IN std_logic;
sampled_bit_q : IN std_logic;
tx_point : IN std_logic;
hard_sync : IN std_logic;
reset_mode : IN std_logic;
listen_only_mode : IN std_logic;
self_test_mode : IN std_logic;
-- Command register
tx_request : IN std_logic;
abort_tx : IN std_logic;
self_rx_request : IN std_logic;
single_shot_transmission: IN std_logic;
tx_state : OUT std_logic;
tx_state_q : OUT std_logic;
overload_request : IN std_logic; -- When receiver is busy, it needs to send overload frame. Only 2 overload frames are allowed to
overload_frame : OUT std_logic; -- be send in a row. This is not implemented, yet, because host can not send an overload request.
-- Arbitration Lost Capture Register
read_arbitration_lost_capture_reg: IN std_logic;
-- Error Code Capture Register
read_error_code_capture_reg: IN std_logic;
error_capture_code : OUT std_logic_vector(7 DOWNTO 0);
-- Error Warning Limit register
extended_mode : IN std_logic;
rx_idle : OUT std_logic;
transmitting : OUT std_logic;
transmitter : OUT std_logic;
go_rx_inter : OUT std_logic;
not_first_bit_of_inter : OUT std_logic;
rx_inter : OUT std_logic;
node_bus_off : OUT std_logic;
rx_err_cnt : OUT std_logic_vector(8 DOWNTO 0);
tx_err_cnt : OUT std_logic_vector(8 DOWNTO 0);
transmit_status : OUT std_logic;
receive_status : OUT std_logic;
tx_successful : OUT std_logic;
need_to_tx : OUT std_logic;
overrun : OUT std_logic;
set_bus_error_irq : OUT std_logic;
set_arbitration_lost_irq: OUT std_logic;
arbitration_lost_capture: OUT std_logic_vector(4 DOWNTO 0);
node_error_passive : OUT std_logic;
node_error_active : OUT std_logic;
tx_data_0 : IN std_logic_vector(7 DOWNTO 0);
tx_data_1 : IN std_logic_vector(7 DOWNTO 0);
tx_data_2 : IN std_logic_vector(7 DOWNTO 0);
tx_data_3 : IN std_logic_vector(7 DOWNTO 0);
tx_data_4 : IN std_logic_vector(7 DOWNTO 0);
tx_data_5 : IN std_logic_vector(7 DOWNTO 0);
tx_data_6 : IN std_logic_vector(7 DOWNTO 0);
tx_data_7 : IN std_logic_vector(7 DOWNTO 0);
tx_data_8 : IN std_logic_vector(7 DOWNTO 0);
tx_data_9 : IN std_logic_vector(7 DOWNTO 0);
tx_data_10 : IN std_logic_vector(7 DOWNTO 0);
tx_data_11 : IN std_logic_vector(7 DOWNTO 0);
tx_data_12 : IN std_logic_vector(7 DOWNTO 0);
rcv_msg_data : out std_logic_vector(63 downto 0);
rcv_id : out std_logic_vector(28 downto 0);
rcv_dlc : out std_logic_vector(3 downto 0);
rcv_rtr : out std_logic;
rcv_ide : out std_logic;
rcv_msg_valid : out std_logic;
form_error : out std_logic;
crc_error : out std_logic;
ack_error : out std_logic;
stuff_error : out std_logic;
bit_error : out std_logic;
arb_loss : out std_logic;
tx : OUT std_logic;
tx_next : OUT std_logic;
go_overload_frame : OUT std_logic;
go_error_frame : OUT std_logic;
go_tx : OUT std_logic;
send_ack : OUT std_logic);
END ENTITY can_bsp_core_sync;
ARCHITECTURE RTL OF can_bsp_core_sync IS
COMPONENT can_crc_core_sync
PORT (
clk : IN std_logic;
data : IN std_logic;
enable : IN std_logic;
initialize : IN std_logic;
crc : OUT std_logic_vector(14 DOWNTO 0));
END COMPONENT;
COMPONENT can_ibo_core_sync
PORT (
di : IN std_logic_vector(7 DOWNTO 0);
do : OUT std_logic_vector(7 DOWNTO 0));
END COMPONENT;
TYPE xhdl_46 IS ARRAY (0 TO 7) OF std_logic_vector(7 DOWNTO 0);
------------------------------
SIGNAL reset_mode_q : std_logic;
SIGNAL bit_cnt : std_logic_vector(5 DOWNTO 0);
SIGNAL data_len : std_logic_vector(3 DOWNTO 0);
SIGNAL id : std_logic_vector(28 DOWNTO 0);
SIGNAL bit_stuff_cnt : std_logic_vector(2 DOWNTO 0);
SIGNAL bit_stuff_cnt_tx : std_logic_vector(2 DOWNTO 0);
SIGNAL tx_point_q : std_logic;
SIGNAL rx_id1 : std_logic;
SIGNAL rx_rtr1 : std_logic;
SIGNAL rx_ide : std_logic;
SIGNAL rx_id2 : std_logic;
SIGNAL rx_rtr2 : std_logic;
SIGNAL rx_r1 : std_logic;
SIGNAL rx_r0 : std_logic;
SIGNAL rx_dlc : std_logic;
SIGNAL rx_data : std_logic;
SIGNAL rx_crc : std_logic;
SIGNAL rx_crc_lim : std_logic;
SIGNAL rx_ack : std_logic;
SIGNAL rx_ack_lim : std_logic;
SIGNAL rx_eof : std_logic;
SIGNAL go_early_tx_latched : std_logic;
SIGNAL rtr1 : std_logic;
SIGNAL ide : std_logic;
SIGNAL rtr2 : std_logic;
SIGNAL crc_in : std_logic_vector(14 DOWNTO 0);
SIGNAL tmp_data : std_logic_vector(7 DOWNTO 0);
SIGNAL tmp_fifo : xhdl_46;
SIGNAL write_data_to_tmp_fifo : std_logic;
SIGNAL byte_cnt : std_logic_vector(2 DOWNTO 0);
SIGNAL bit_stuff_cnt_en : std_logic;
SIGNAL crc_enable : std_logic;
SIGNAL eof_cnt : std_logic_vector(2 DOWNTO 0);
SIGNAL passive_cnt : std_logic_vector(2 DOWNTO 0);
SIGNAL error_frame : std_logic;
SIGNAL enable_error_cnt2 : std_logic;
SIGNAL error_cnt1 : std_logic_vector(2 DOWNTO 0);
SIGNAL error_cnt2 : std_logic_vector(2 DOWNTO 0);
SIGNAL delayed_dominant_cnt : std_logic_vector(2 DOWNTO 0);
SIGNAL enable_overload_cnt2 : std_logic;
SIGNAL overload_frame_blocked : std_logic;
SIGNAL overload_request_cnt : std_logic_vector(1 DOWNTO 0);
SIGNAL overload_cnt1 : std_logic_vector(2 DOWNTO 0);
SIGNAL overload_cnt2 : std_logic_vector(2 DOWNTO 0);
SIGNAL crc_err : std_logic;
SIGNAL arbitration_lost : std_logic;
SIGNAL arbitration_lost_q : std_logic;
SIGNAL read_arbitration_lost_capture_reg_q: std_logic;
signal read_error_code_capture_reg_q : std_logic;
signal reset_error_code_capture_reg : std_logic;
SIGNAL arbitration_cnt_en : std_logic;
SIGNAL arbitration_blocked : std_logic;
SIGNAL tx_q : std_logic;
SIGNAL data_cnt : std_logic_vector(3 DOWNTO 0); -- Counting the data bytes that are written to FIFO
SIGNAL header_cnt : std_logic_vector(2 DOWNTO 0); -- Counting header length
SIGNAL wr_fifo : std_logic; -- Write data and header to 64-byte fifo
SIGNAL wr_fifo2 : std_logic;
SIGNAL data_for_fifo : std_logic_vector(7 DOWNTO 0); -- Multiplexed data that is stored to 64-byte fifo
SIGNAL tx_pointer : std_logic_vector(5 DOWNTO 0);
SIGNAL tx_bit : std_logic;
SIGNAL finish_msg : std_logic;
SIGNAL bus_free_cnt : std_logic_vector(3 DOWNTO 0);
SIGNAL bus_free_cnt_en : std_logic;
SIGNAL bus_free : std_logic;
SIGNAL waiting_for_bus_free : std_logic;
SIGNAL node_bus_off_q : std_logic;
SIGNAL ack_err_latched : std_logic;
SIGNAL bit_err_latched : std_logic;
SIGNAL stuff_err_latched : std_logic;
SIGNAL form_err_latched : std_logic;
SIGNAL rule3_exc1_1 : std_logic;
SIGNAL rule3_exc1_2 : std_logic;
SIGNAL suspend : std_logic;
SIGNAL susp_cnt_en : std_logic;
SIGNAL susp_cnt : std_logic_vector(2 DOWNTO 0);
SIGNAL error_flag_over_latched : std_logic;
SIGNAL error_capture_code_type : std_logic_vector(7 DOWNTO 6);
SIGNAL error_capture_code_blocked : std_logic;
SIGNAL first_compare_bit : std_logic;
SIGNAL error_capture_code_segment : std_logic_vector(4 DOWNTO 0);
SIGNAL error_capture_code_direction : std_logic;
SIGNAL bit_de_stuff : std_logic;
SIGNAL bit_de_stuff_tx : std_logic;
SIGNAL rule5 : std_logic;
-- Rx state machine
SIGNAL go_rx_idle : std_logic;
SIGNAL go_rx_id1 : std_logic;
SIGNAL go_rx_rtr1 : std_logic;
SIGNAL go_rx_ide : std_logic;
SIGNAL go_rx_id2 : std_logic;
SIGNAL go_rx_rtr2 : std_logic;
SIGNAL go_rx_r1 : std_logic;
SIGNAL go_rx_r0 : std_logic;
SIGNAL go_rx_dlc : std_logic;
SIGNAL go_rx_data : std_logic;
SIGNAL go_rx_crc : std_logic;
SIGNAL go_rx_crc_lim : std_logic;
SIGNAL go_rx_ack : std_logic;
SIGNAL go_rx_ack_lim : std_logic;
SIGNAL go_rx_eof : std_logic;
SIGNAL last_bit_of_inter : std_logic;
SIGNAL go_crc_enable : std_logic;
SIGNAL rst_crc_enable : std_logic;
SIGNAL bit_de_stuff_set : std_logic;
SIGNAL bit_de_stuff_reset : std_logic;
SIGNAL go_early_tx : std_logic;
SIGNAL calculated_crc : std_logic_vector(14 DOWNTO 0);
SIGNAL r_calculated_crc : std_logic_vector(15 DOWNTO 0);
SIGNAL remote_rq : std_logic;
SIGNAL limited_data_len : std_logic_vector(3 DOWNTO 0);
SIGNAL form_err : std_logic;
SIGNAL error_frame_ended : std_logic;
SIGNAL overload_frame_ended : std_logic;
SIGNAL bit_err : std_logic;
SIGNAL ack_err : std_logic;
SIGNAL stuff_err : std_logic;
SIGNAL id_ok : std_logic; -- If received ID matches ID set in registers
SIGNAL no_byte0 : std_logic; -- There is no byte 0 (RTR bit set to 1 or DLC field equal to 0). Signal used for acceptance filter.
SIGNAL no_byte1 : std_logic; -- There is no byte 1 (RTR bit set to 1 or DLC field equal to 1). Signal used for acceptance filter.
SIGNAL header_len : std_logic_vector(2 DOWNTO 0);
SIGNAL storing_header : std_logic;
SIGNAL limited_data_len_minus1 : std_logic_vector(3 DOWNTO 0);
SIGNAL reset_wr_fifo : std_logic;
SIGNAL err : std_logic;
SIGNAL arbitration_field : std_logic;
SIGNAL basic_chain : std_logic_vector(18 DOWNTO 0);
SIGNAL basic_chain_data : std_logic_vector(63 DOWNTO 0);
SIGNAL extended_chain_std : std_logic_vector(18 DOWNTO 0);
SIGNAL extended_chain_ext : std_logic_vector(38 DOWNTO 0);
SIGNAL extended_chain_data_std : std_logic_vector(63 DOWNTO 0);
SIGNAL extended_chain_data_ext : std_logic_vector(63 DOWNTO 0);
SIGNAL rst_tx_pointer : std_logic;
SIGNAL r_tx_data_0 : std_logic_vector(7 DOWNTO 0);
SIGNAL r_tx_data_1 : std_logic_vector(7 DOWNTO 0);
SIGNAL r_tx_data_2 : std_logic_vector(7 DOWNTO 0);
SIGNAL r_tx_data_3 : std_logic_vector(7 DOWNTO 0);
SIGNAL r_tx_data_4 : std_logic_vector(7 DOWNTO 0);
SIGNAL r_tx_data_5 : std_logic_vector(7 DOWNTO 0);
SIGNAL r_tx_data_6 : std_logic_vector(7 DOWNTO 0);
SIGNAL r_tx_data_7 : std_logic_vector(7 DOWNTO 0);
SIGNAL r_tx_data_8 : std_logic_vector(7 DOWNTO 0);
SIGNAL r_tx_data_9 : std_logic_vector(7 DOWNTO 0);
SIGNAL r_tx_data_10 : std_logic_vector(7 DOWNTO 0);
SIGNAL r_tx_data_11 : std_logic_vector(7 DOWNTO 0);
SIGNAL r_tx_data_12 : std_logic_vector(7 DOWNTO 0);
SIGNAL bit_err_exc1 : std_logic;
SIGNAL bit_err_exc2 : std_logic;
SIGNAL bit_err_exc3 : std_logic;
SIGNAL bit_err_exc4 : std_logic;
SIGNAL bit_err_exc5 : std_logic;
SIGNAL bit_err_exc6 : std_logic;
SIGNAL error_flag_over : std_logic;
SIGNAL overload_flag_over : std_logic;
SIGNAL limited_tx_cnt_ext : std_logic_vector(5 DOWNTO 0);
SIGNAL limited_tx_cnt_std : std_logic_vector(5 DOWNTO 0);
-- Instantiation of the RX CRC module
SIGNAL xhdl_49 : std_logic;
-- Mode register
-- Clock Divider register
-- This section is for BASIC and EXTENDED mode
-- Acceptance code register
-- Acceptance mask register
-- End: This section is for BASIC and EXTENDED mode
-- This section is for EXTENDED mode
-- Acceptance code register
-- Acceptance mask register
-- End: This section is for EXTENDED mode
SIGNAL temp_xhdl47 : std_logic_vector(3 DOWNTO 0);
SIGNAL port_xhdl73 : std_logic_vector(7 DOWNTO 0);
SIGNAL port_xhdl74 : std_logic_vector(7 DOWNTO 0);
SIGNAL temp_xhdl75 : std_logic_vector(2 DOWNTO 0);
SIGNAL temp_xhdl76 : std_logic_vector(2 DOWNTO 0);
SIGNAL temp_xhdl77 : std_logic_vector(3 DOWNTO 0);
SIGNAL temp_xhdl78 : std_logic_vector(3 DOWNTO 0); -- - 1 because counter counts from 0
SIGNAL xhdl_106 : std_logic_vector(7 DOWNTO 0);
SIGNAL temp_xhdl108 : std_logic_vector(5 DOWNTO 0);
SIGNAL temp_xhdl109 : std_logic_vector(5 DOWNTO 0);
SIGNAL temp_xhdl110 : boolean;
SIGNAL temp_xhdl111 : std_logic;
SIGNAL tx_state_xhdl2 : std_logic;
SIGNAL tx_state_q_xhdl3 : std_logic;
SIGNAL overload_frame_xhdl4 : std_logic;
SIGNAL error_capture_code_xhdl5 : std_logic_vector(7 DOWNTO 0);
SIGNAL rx_idle_xhdl6 : std_logic;
SIGNAL transmitting_xhdl7 : std_logic;
SIGNAL transmitter_xhdl8 : std_logic;
SIGNAL go_rx_inter_xhdl9 : std_logic;
SIGNAL not_first_bit_of_inter_xhdl10 : std_logic;
SIGNAL rx_inter_xhdl11 : std_logic;
SIGNAL node_bus_off_xhdl13 : std_logic;
SIGNAL rx_err_cnt_xhdl15 : std_logic_vector(8 DOWNTO 0);
SIGNAL tx_err_cnt_xhdl16 : std_logic_vector(8 DOWNTO 0);
SIGNAL transmit_status_xhdl17 : std_logic;
SIGNAL receive_status_xhdl18 : std_logic;
SIGNAL tx_successful_xhdl19 : std_logic;
SIGNAL need_to_tx_xhdl20 : std_logic;
SIGNAL overrun_xhdl21 : std_logic;
SIGNAL set_bus_error_irq_xhdl23 : std_logic;
SIGNAL set_arbitration_lost_irq_xhdl24 : std_logic;
SIGNAL arbitration_lost_capture_xhdl25 : std_logic_vector(4 DOWNTO 0);
SIGNAL node_error_passive_xhdl26: std_logic;
SIGNAL node_error_active_xhdl27 : std_logic;
SIGNAL tx_xhdl29 : std_logic;
SIGNAL tx_next_xhdl30 : std_logic;
SIGNAL go_overload_frame_xhdl32 : std_logic;
SIGNAL go_error_frame_xhdl33 : std_logic;
SIGNAL go_tx_xhdl34 : std_logic;
SIGNAL send_ack_xhdl35 : std_logic;
signal rx_msg_data : std_logic_vector(63 downto 0);
SIGNAL set_reset_mode_xhdl12 : std_logic;
BEGIN
form_error <= form_err_latched;
crc_error <= crc_err;
ack_error <= ack_err_latched;
stuff_error <= stuff_err_latched;
bit_error <= bit_err_latched;
arb_loss <= arbitration_lost;
tx_state <= tx_state_xhdl2;
tx_state_q <= tx_state_q_xhdl3;
overload_frame <= overload_frame_xhdl4;
error_capture_code <= error_capture_code_xhdl5;
rx_idle <= rx_idle_xhdl6;
transmitting <= transmitting_xhdl7;
transmitter <= transmitter_xhdl8;
go_rx_inter <= go_rx_inter_xhdl9;
not_first_bit_of_inter <= not_first_bit_of_inter_xhdl10;
rx_inter <= rx_inter_xhdl11;
node_bus_off <= node_bus_off_xhdl13;
rx_err_cnt <= rx_err_cnt_xhdl15;
tx_err_cnt <= tx_err_cnt_xhdl16;
transmit_status <= transmitter_xhdl8;
-- transmit_status <= transmit_status_xhdl17;
receive_status <= receive_status_xhdl18;
tx_successful <= tx_successful_xhdl19;
need_to_tx <= need_to_tx_xhdl20;
overrun <= overrun_xhdl21;
set_bus_error_irq <= set_bus_error_irq_xhdl23;
set_arbitration_lost_irq <= set_arbitration_lost_irq_xhdl24;
arbitration_lost_capture <= arbitration_lost_capture_xhdl25;
node_error_passive <= node_error_passive_xhdl26;
node_error_active <= node_error_active_xhdl27;
tx <= tx_xhdl29;
tx_next <= tx_next_xhdl30;
go_overload_frame <= go_overload_frame_xhdl32;
go_error_frame <= go_error_frame_xhdl33;
go_tx <= go_tx_xhdl34;
send_ack <= send_ack_xhdl35;
go_rx_idle <= ((sample_point AND sampled_bit) AND last_bit_of_inter) OR (bus_free AND (NOT node_bus_off_xhdl13)) ;
go_rx_id1 <= (sample_point AND (NOT sampled_bit)) AND (rx_idle_xhdl6 OR last_bit_of_inter) ;
go_rx_rtr1 <= (((NOT bit_de_stuff) AND sample_point) AND rx_id1) AND CONV_STD_LOGIC(bit_cnt(3 DOWNTO 0) = "1010") ;
go_rx_ide <= ((NOT bit_de_stuff) AND sample_point) AND rx_rtr1 ;
go_rx_id2 <= (((NOT bit_de_stuff) AND sample_point) AND rx_ide) AND sampled_bit ;
go_rx_rtr2 <= (((NOT bit_de_stuff) AND sample_point) AND rx_id2) AND CONV_STD_LOGIC(bit_cnt(4 DOWNTO 0) = "10001") ;
go_rx_r1 <= ((NOT bit_de_stuff) AND sample_point) AND rx_rtr2 ;
go_rx_r0 <= ((NOT bit_de_stuff) AND sample_point) AND ((rx_ide AND (NOT sampled_bit)) OR rx_r1) ;
go_rx_dlc <= ((NOT bit_de_stuff) AND sample_point) AND rx_r0 ;
go_rx_data <= (((((NOT bit_de_stuff) AND sample_point) AND rx_dlc) AND CONV_STD_LOGIC(bit_cnt(1 DOWNTO 0) = "11")) AND (sampled_bit OR (orv(data_len(2 DOWNTO 0))))) AND (NOT remote_rq) ;
go_rx_crc <= ((NOT bit_de_stuff) AND sample_point) AND (((rx_dlc AND CONV_STD_LOGIC(bit_cnt(1 DOWNTO 0) = "11")) AND (((NOT sampled_bit) AND (NOT (orv(data_len(2 DOWNTO 0))))) OR remote_rq)) OR (rx_data AND CONV_STD_LOGIC('0' & bit_cnt(5 DOWNTO 0) = ((limited_data_len & "000") - 1)))) ;
go_rx_crc_lim <= (((NOT bit_de_stuff) AND sample_point) AND rx_crc) AND CONV_STD_LOGIC(bit_cnt(3 DOWNTO 0) = "1110") ;
go_rx_ack <= ((NOT bit_de_stuff) AND sample_point) AND rx_crc_lim ;
go_rx_ack_lim <= sample_point AND rx_ack ;
go_rx_eof <= sample_point AND rx_ack_lim ;
go_rx_inter_xhdl9 <= (((sample_point AND rx_eof) AND CONV_STD_LOGIC(eof_cnt = "110")) OR error_frame_ended OR overload_frame_ended) AND (NOT overload_request) ;
go_error_frame_xhdl33 <= form_err OR stuff_err OR bit_err OR ack_err OR (crc_err AND go_rx_eof) ;
error_frame_ended <= CONV_STD_LOGIC(error_cnt2 = "111") AND tx_point ;
overload_frame_ended <= CONV_STD_LOGIC(overload_cnt2 = "111") AND tx_point ;
go_overload_frame_xhdl32 <= (((sample_point AND ((NOT sampled_bit) OR overload_request)) AND (((rx_eof AND (NOT transmitter_xhdl8)) AND CONV_STD_LOGIC(eof_cnt = "110")) OR error_frame_ended OR overload_frame_ended)) OR (((sample_point AND (NOT sampled_bit)) AND rx_inter_xhdl11) AND CONV_STD_LOGIC(bit_cnt(1 DOWNTO 0) < "10")) OR ((sample_point AND (NOT sampled_bit)) AND CONV_STD_LOGIC((error_cnt2 = "111") OR (overload_cnt2 = "111")))) AND (NOT overload_frame_blocked) ;
go_crc_enable <= hard_sync OR go_tx_xhdl34 ;
rst_crc_enable <= go_rx_crc ;
bit_de_stuff_set <= go_rx_id1 AND (NOT go_error_frame_xhdl33) ;
bit_de_stuff_reset <= go_rx_ack OR reset_mode OR go_error_frame_xhdl33 OR go_overload_frame_xhdl32 ;
remote_rq <= ((NOT ide) AND rtr1) OR (ide AND rtr2) ;
temp_xhdl47 <= data_len WHEN (data_len < "1000") ELSE "1000";
limited_data_len <= temp_xhdl47 ;
ack_err <= (((rx_ack AND sample_point) AND sampled_bit) AND tx_state_xhdl2) AND (NOT self_test_mode) ;
bit_err <= ((((((((tx_state_xhdl2 OR error_frame OR overload_frame_xhdl4 OR rx_ack) AND sample_point) AND CONV_STD_LOGIC(tx_xhdl29 /= sampled_bit)) AND (NOT bit_err_exc1)) AND (NOT bit_err_exc2)) AND (NOT bit_err_exc3)) AND (NOT bit_err_exc4)) AND (NOT bit_err_exc5)) AND (NOT bit_err_exc6) ;
bit_err_exc1 <= (tx_state_xhdl2 AND arbitration_field) AND tx_xhdl29 ;
bit_err_exc2 <= rx_ack AND tx_xhdl29 ;
bit_err_exc3 <= (error_frame AND node_error_passive_xhdl26) AND CONV_STD_LOGIC(error_cnt1 < "111") ;
bit_err_exc4 <= ((error_frame AND CONV_STD_LOGIC(error_cnt1 = "111")) AND (NOT enable_error_cnt2)) OR ((overload_frame_xhdl4 AND CONV_STD_LOGIC(overload_cnt1 = "111")) AND (NOT enable_overload_cnt2)) ;
bit_err_exc5 <= (error_frame AND CONV_STD_LOGIC(error_cnt2 = "111")) OR (overload_frame_xhdl4 AND CONV_STD_LOGIC(overload_cnt2 = "111")) ;
bit_err_exc6 <= (CONV_STD_LOGIC(eof_cnt = "110") AND rx_eof) AND (NOT transmitter_xhdl8) ;
arbitration_field <= rx_id1 OR rx_rtr1 OR rx_ide OR rx_id2 OR rx_rtr2 ;
last_bit_of_inter <= rx_inter_xhdl11 AND CONV_STD_LOGIC(bit_cnt(1 DOWNTO 0) = "10") ;
not_first_bit_of_inter_xhdl10 <= rx_inter_xhdl11 AND CONV_STD_LOGIC(bit_cnt(1 DOWNTO 0) /= "00") ;
-- Rx idle state
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- rx_idle_xhdl6 <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_id1 OR go_error_frame_xhdl33) = '1') THEN
rx_idle_xhdl6 <= '0' ;
ELSE
IF (go_rx_idle = '1') THEN
rx_idle_xhdl6 <= '1' ;
END IF;
END IF;
IF (rst = '1') THEN
rx_idle_xhdl6 <= '0';
END IF;
END IF;
END PROCESS;
-- Rx id1 state
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- rx_id1 <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_rtr1 OR go_error_frame_xhdl33) = '1') THEN
rx_id1 <= '0' ;
ELSE
IF (go_rx_id1 = '1') THEN
rx_id1 <= '1' ;
END IF;
END IF;
IF (rst = '1') THEN
rx_id1 <= '0';
END IF;
END IF;
END PROCESS;
-- Rx rtr1 state
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- rx_rtr1 <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_ide OR go_error_frame_xhdl33) = '1') THEN
rx_rtr1 <= '0' ;
ELSE
IF (go_rx_rtr1 = '1') THEN
rx_rtr1 <= '1' ;
END IF;
END IF;
IF (rst = '1') THEN
rx_rtr1 <= '0';
END IF;
END IF;
END PROCESS;
-- Rx ide state
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- rx_ide <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_r0 OR go_rx_id2 OR go_error_frame_xhdl33) = '1') THEN
rx_ide <= '0' ;
ELSE
IF (go_rx_ide = '1') THEN
rx_ide <= '1' ;
END IF;
END IF;
IF (rst = '1') THEN
rx_ide <= '0';
END IF;
END IF;
END PROCESS;
-- Rx id2 state
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- rx_id2 <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_rtr2 OR go_error_frame_xhdl33) = '1') THEN
rx_id2 <= '0' ;
ELSE
IF (go_rx_id2 = '1') THEN
rx_id2 <= '1' ;
END IF;
END IF;
IF (rst = '1') THEN
rx_id2 <= '0';
END IF;
END IF;
END PROCESS;
-- Rx rtr2 state
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- rx_rtr2 <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_r1 OR go_error_frame_xhdl33) = '1') THEN
rx_rtr2 <= '0' ;
ELSE
IF (go_rx_rtr2 = '1') THEN
rx_rtr2 <= '1' ;
END IF;
END IF;
IF (rst = '1') THEN
rx_rtr2 <= '0';
END IF;
END IF;
END PROCESS;
-- Rx r0 state
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- rx_r1 <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_r0 OR go_error_frame_xhdl33) = '1') THEN
rx_r1 <= '0' ;
ELSE
IF (go_rx_r1 = '1') THEN
rx_r1 <= '1' ;
END IF;
END IF;
IF (rst = '1') THEN
rx_r1 <= '0';
END IF;
END IF;
END PROCESS;
-- Rx r0 state
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- rx_r0 <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_dlc OR go_error_frame_xhdl33) = '1') THEN
rx_r0 <= '0' ;
ELSE
IF (go_rx_r0 = '1') THEN
rx_r0 <= '1' ;
END IF;
END IF;
IF (rst = '1') THEN
rx_r0 <= '0';
END IF;
END IF;
END PROCESS;
-- Rx dlc state
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- rx_dlc <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_data OR go_rx_crc OR go_error_frame_xhdl33) = '1') THEN
rx_dlc <= '0' ;
ELSE
IF (go_rx_dlc = '1') THEN
rx_dlc <= '1' ;
END IF;
END IF;
IF (rst = '1') THEN
rx_dlc <= '0';
END IF;
END IF;
END PROCESS;
-- Rx data state
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- rx_data <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_crc OR go_error_frame_xhdl33) = '1') THEN
rx_data <= '0' ;
ELSE
IF (go_rx_data = '1') THEN
rx_data <= '1' ;
END IF;
END IF;
IF (rst = '1') THEN
rx_data <= '0';
END IF;
END IF;
END PROCESS;
-- Rx crc state
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- rx_crc <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_crc_lim OR go_error_frame_xhdl33) = '1') THEN
rx_crc <= '0' ;
ELSE
IF (go_rx_crc = '1') THEN
rx_crc <= '1' ;
END IF;
END IF;
IF (rst = '1') THEN
rx_crc <= '0';
END IF;
END IF;
END PROCESS;
-- Rx crc delimiter state
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- rx_crc_lim <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_ack OR go_error_frame_xhdl33) = '1') THEN
rx_crc_lim <= '0' ;
ELSE
IF (go_rx_crc_lim = '1') THEN
rx_crc_lim <= '1' ;
END IF;
END IF;
IF (rst = '1') THEN
rx_crc_lim <= '0';
END IF;
END IF;
END PROCESS;
-- Rx ack state
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- rx_ack <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_ack_lim OR go_error_frame_xhdl33) = '1') THEN
rx_ack <= '0' ;
ELSE
IF (go_rx_ack = '1') THEN
rx_ack <= '1' ;
END IF;
END IF;
IF (rst = '1') THEN
rx_ack <= '0';
END IF;
END IF;
END PROCESS;
-- Rx ack delimiter state
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- rx_ack_lim <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_eof OR go_error_frame_xhdl33) = '1') THEN
rx_ack_lim <= '0' ;
ELSE
IF (go_rx_ack_lim = '1') THEN
rx_ack_lim <= '1' ;
END IF;
END IF;
IF (rst = '1') THEN
rx_ack_lim <= '0';
END IF;
END IF;
END PROCESS;
-- Rx eof state
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- rx_eof <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_inter_xhdl9 OR go_error_frame_xhdl33 OR go_overload_frame_xhdl32) = '1') THEN
rx_eof <= '0' ;
ELSE
IF (go_rx_eof = '1') THEN
rx_eof <= '1' ;
END IF;
END IF;
IF (rst = '1') THEN
rx_eof <= '0';
END IF;
END IF;
END PROCESS;
-- Interframe space
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- rx_inter_xhdl11 <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_idle OR go_rx_id1 OR go_overload_frame_xhdl32 OR go_error_frame_xhdl33) = '1') THEN
rx_inter_xhdl11 <= '0' ;
ELSE
IF (go_rx_inter_xhdl9 = '1') THEN
rx_inter_xhdl11 <= '1' ;
END IF;
END IF;
IF (rst = '1') THEN
rx_inter_xhdl11 <= '0';
END IF;
END IF;
END PROCESS;
-- ID register
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- id <= "00000000000000000000000000000";
IF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
id <= "00000000000000000000000000000";
ELSE
IF (((sample_point AND (rx_id1 OR rx_id2)) AND (NOT bit_de_stuff)) = '1') THEN
id <= id(27 DOWNTO 0) & sampled_bit ;
END IF;
END IF;
IF (rst = '1') THEN
id <= "00000000000000000000000000000";
END IF;
END IF;
END PROCESS;
-- rtr1 bit
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- rtr1 <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
rtr1 <= '0';
ELSE
IF (((sample_point AND rx_rtr1) AND (NOT bit_de_stuff)) = '1') THEN
rtr1 <= sampled_bit ;
END IF;
END IF;
IF (rst = '1') THEN
rtr1 <= '0';
END IF;
END IF;
END PROCESS;
-- rtr2 bit
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- rtr2 <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
rtr2 <= '0';
ELSE
IF (((sample_point AND rx_rtr2) AND (NOT bit_de_stuff)) = '1') THEN
rtr2 <= sampled_bit ;
END IF;
END IF;
IF (rst = '1') THEN
rtr2 <= '0';
END IF;
END IF;
END PROCESS;
-- ide bit
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- ide <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
ide <= '0';
ELSE
IF (((sample_point AND rx_ide) AND (NOT bit_de_stuff)) = '1') THEN
ide <= sampled_bit ;
END IF;
END IF;
IF (rst = '1') THEN
ide <= '0';
END IF;
END IF;
END PROCESS;
-- Data length
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- data_len <= "0000";
IF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
data_len <= "0000";
ELSE
IF (((sample_point AND rx_dlc) AND (NOT bit_de_stuff)) = '1') THEN
data_len <= data_len(2 DOWNTO 0) & sampled_bit ;
END IF;
END IF;
IF (rst = '1') THEN
data_len <= "0000";
END IF;
END IF;
END PROCESS;
-- Data
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- tmp_data <= "00000000";
IF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
tmp_data <= "00000000";
ELSE
IF (((sample_point AND rx_data) AND (NOT bit_de_stuff)) = '1') THEN
tmp_data <= tmp_data(6 DOWNTO 0) & sampled_bit ;
END IF;
END IF;
IF (rst = '1') THEN
tmp_data <= "00000000";
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- write_data_to_tmp_fifo <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
write_data_to_tmp_fifo <= '0';
ELSE
IF ((((sample_point AND rx_data) AND (NOT bit_de_stuff)) AND (andv(bit_cnt(2 DOWNTO 0)))) = '1') THEN
write_data_to_tmp_fifo <= '1' ;
ELSE
write_data_to_tmp_fifo <= '0' ;
END IF;
END IF;
IF (rst = '1') THEN
write_data_to_tmp_fifo <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (clk)
BEGIN
-- IF (rst = '1') THEN
-- byte_cnt <= "000";
IF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode or rst) = '1') THEN
byte_cnt <= "000";
ELSE
IF (write_data_to_tmp_fifo = '1') THEN
byte_cnt <= byte_cnt + "001" ;
ELSE
IF ((sample_point AND go_rx_crc_lim) = '1') THEN
byte_cnt <= "000" ;
END IF;
END IF;
END IF;
-- IF (rst = '1') THENbyte_cnt <= "000";END IF;
END IF;
END PROCESS;
process (clk, rst)
begin
if rising_edge(clk) then
wr_fifo2 <= wr_fifo;
end if;
if rst = '1' then
wr_fifo2 <= '0';
end if;
end process;
rcv_msg_valid <= wr_fifo and not wr_fifo2;
rcv_id <= id when ide = '1' else id(10 downto 0) & "11" & X"FFFF";
rcv_rtr <= rtr2 when ide = '1' else rtr1;
rcv_dlc <= data_len;
rcv_ide <= ide;
rcv_msg_data <= rx_msg_data;
process (clk)
begin
if (clk'EVENT AND clk = '1') then
if (write_data_to_tmp_fifo = '1') then
case byte_cnt is
when "000" => rx_msg_data(63 downto 56) <= tmp_data;
when "001" => rx_msg_data(55 downto 48) <= tmp_data;
when "010" => rx_msg_data(47 downto 40) <= tmp_data;
when "011" => rx_msg_data(39 downto 32) <= tmp_data;
when "100" => rx_msg_data(31 downto 24) <= tmp_data;
when "101" => rx_msg_data(23 downto 16) <= tmp_data;
when "110" => rx_msg_data(15 downto 8) <= tmp_data;
when "111" => rx_msg_data(7 downto 0) <= tmp_data;
when others => null;
end case;
end if;
if (rst = '1') then
rx_msg_data <= (others => '0');
end if;
end if;
end process;
-- CRC
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- crc_in <= "000000000000000";
IF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
crc_in <= "000000000000000";
ELSE
IF (((sample_point AND rx_crc) AND (NOT bit_de_stuff)) = '1') THEN
crc_in <= crc_in(13 DOWNTO 0) & sampled_bit ;
END IF;
END IF;
IF (rst = '1') THEN
crc_in <= "000000000000000";
END IF;
END IF;
END PROCESS;
-- bit_cnt
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- bit_cnt <= "000000";
IF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
bit_cnt <= "000000";
ELSE
IF ((go_rx_id1 OR go_rx_id2 OR go_rx_dlc OR go_rx_data OR go_rx_crc OR go_rx_ack OR go_rx_eof OR go_rx_inter_xhdl9 OR go_error_frame_xhdl33 OR go_overload_frame_xhdl32) = '1') THEN
bit_cnt <= "000000" ;
ELSE
IF ((sample_point AND (NOT bit_de_stuff)) = '1') THEN
bit_cnt <= bit_cnt + "000001" ;
END IF;
END IF;
END IF;
IF (rst = '1') THEN
bit_cnt <= "000000";
END IF;
END IF;
END PROCESS;
-- eof_cnt
PROCESS (clk)
BEGIN
-- IF (rst = '1') THEN
-- eof_cnt <= "000";
IF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode or rst) = '1') THEN
eof_cnt <= "000";
ELSE
IF (sample_point = '1') THEN
IF ((go_rx_inter_xhdl9 OR go_error_frame_xhdl33 OR go_overload_frame_xhdl32) = '1') THEN
eof_cnt <= "000" ;
ELSE
IF (rx_eof = '1') THEN
eof_cnt <= eof_cnt + "001" ;
END IF;
END IF;
END IF;
END IF;
-- IF (rst = '1') THENeof_cnt <= "000";END IF;
END IF;
END PROCESS;
-- Enabling bit de-stuffing
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- bit_stuff_cnt_en <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
bit_stuff_cnt_en <= '0';
ELSE
IF (bit_de_stuff_set = '1') THEN
bit_stuff_cnt_en <= '1' ;
ELSE
IF (bit_de_stuff_reset = '1') THEN
bit_stuff_cnt_en <= '0' ;
END IF;
END IF;
END IF;
IF (rst = '1') THEN
bit_stuff_cnt_en <= '0';
END IF;
END IF;
END PROCESS;
-- bit_stuff_cnt
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- bit_stuff_cnt <= "001";
IF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
bit_stuff_cnt <= "001";
ELSE
IF (bit_de_stuff_reset = '1') THEN
bit_stuff_cnt <= "001" ;
ELSE
IF ((sample_point AND bit_stuff_cnt_en) = '1') THEN
IF (bit_stuff_cnt = "101") THEN
bit_stuff_cnt <= "001" ;
ELSE
IF (sampled_bit = sampled_bit_q) THEN
bit_stuff_cnt <= bit_stuff_cnt + "001" ;
ELSE
bit_stuff_cnt <= "001" ;
END IF;
END IF;
END IF;
END IF;
END IF;
IF (rst = '1') THEN
bit_stuff_cnt <= "001";
END IF;
END IF;
END PROCESS;
-- bit_stuff_cnt_tx
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- bit_stuff_cnt_tx <= "001";
IF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
bit_stuff_cnt_tx <= "001";
ELSE
IF (bit_de_stuff_reset = '1') THEN
bit_stuff_cnt_tx <= "001" ;
ELSE
IF ((tx_point_q AND bit_stuff_cnt_en) = '1') THEN
IF (bit_stuff_cnt_tx = "101") THEN
bit_stuff_cnt_tx <= "001" ;
ELSE
IF (tx_xhdl29 = tx_q) THEN
bit_stuff_cnt_tx <= bit_stuff_cnt_tx + "001" ;
ELSE
bit_stuff_cnt_tx <= "001" ;
END IF;
END IF;
END IF;
END IF;
END IF;
IF (rst = '1') THEN
bit_stuff_cnt_tx <= "001";
END IF;
END IF;
END PROCESS;
bit_de_stuff <= CONV_STD_LOGIC(bit_stuff_cnt = "101") ;
bit_de_stuff_tx <= CONV_STD_LOGIC(bit_stuff_cnt_tx = "101") ;
-- stuff_err
stuff_err <= ((sample_point AND bit_stuff_cnt_en) AND bit_de_stuff) AND CONV_STD_LOGIC(sampled_bit = sampled_bit_q) ;
-- Generating delayed signals
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- reset_mode_q <= '0' ;
-- node_bus_off_q <= '0' ;
IF (clk'EVENT AND clk = '1') THEN
reset_mode_q <= reset_mode ;
node_bus_off_q <= node_bus_off_xhdl13 ;
IF (rst = '1') THEN
reset_mode_q <= '0' ;
node_bus_off_q <= '0' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- crc_enable <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR rst_crc_enable) = '1') THEN
crc_enable <= '0' ;
ELSE
IF (go_crc_enable = '1') THEN
crc_enable <= '1' ;
END IF;
END IF;
IF (rst = '1') THEN
crc_enable <= '0';
END IF;
END IF;
END PROCESS;
-- CRC error generation
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- crc_err <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR error_frame_ended) = '1') THEN
crc_err <= '0' ;
ELSE
IF (go_rx_ack = '1') THEN
crc_err <= CONV_STD_LOGIC(crc_in /= calculated_crc) ;
END IF;
END IF;
IF (rst = '1') THEN
crc_err <= '0';
END IF;
END IF;
END PROCESS;
-- Conditions for form error
form_err <= sample_point AND ((((NOT bit_de_stuff) AND rx_crc_lim) AND (NOT sampled_bit)) OR (rx_ack_lim AND (NOT sampled_bit)) OR (((CONV_STD_LOGIC(eof_cnt < "110") AND rx_eof) AND (NOT sampled_bit)) AND (NOT transmitter_xhdl8)) OR (((rx_eof) AND (NOT sampled_bit)) AND transmitter_xhdl8)) ;
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- ack_err_latched <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR error_frame_ended OR go_overload_frame_xhdl32) = '1') THEN
ack_err_latched <= '0' ;
ELSE
IF (ack_err = '1') THEN
ack_err_latched <= '1' ;
END IF;
END IF;
IF (rst = '1') THEN
ack_err_latched <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- bit_err_latched <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR error_frame_ended OR go_overload_frame_xhdl32) = '1') THEN
bit_err_latched <= '0' ;
ELSE
IF (bit_err = '1') THEN
bit_err_latched <= '1' ;
END IF;
END IF;
IF (rst = '1') THEN
bit_err_latched <= '0';
END IF;
END IF;
END PROCESS;
-- Rule 5 (Fault confinement).
rule5 <= bit_err AND ((((NOT node_error_passive_xhdl26) AND error_frame) AND CONV_STD_LOGIC(error_cnt1 < "111")) OR (overload_frame_xhdl4 AND CONV_STD_LOGIC(overload_cnt1 < "111"))) ;
-- Rule 3 exception 1 - first part (Fault confinement).
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- rule3_exc1_1 <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR error_flag_over OR rule3_exc1_2) = '1') THEN
rule3_exc1_1 <= '0' ;
ELSE
IF (((transmitter_xhdl8 AND node_error_passive_xhdl26) AND ack_err) = '1') THEN
rule3_exc1_1 <= '1' ;
END IF;
END IF;
IF (rst = '1') THEN
rule3_exc1_1 <= '0';
END IF;
END IF;
END PROCESS;
-- Rule 3 exception 1 - second part (Fault confinement).
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- rule3_exc1_2 <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_error_frame_xhdl33 OR rule3_exc1_2) = '1') THEN
rule3_exc1_2 <= '0' ;
ELSE
IF ((((rule3_exc1_1 AND CONV_STD_LOGIC(error_cnt1 < "111")) AND sample_point) AND (NOT sampled_bit)) = '1') THEN
rule3_exc1_2 <= '1' ;
END IF;
END IF;
IF (rst = '1') THEN
rule3_exc1_2 <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- stuff_err_latched <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR error_frame_ended OR go_overload_frame_xhdl32) = '1') THEN
stuff_err_latched <= '0' ;
ELSE
IF (stuff_err = '1') THEN
stuff_err_latched <= '1' ;
END IF;
END IF;
IF (rst = '1') THEN
stuff_err_latched <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- form_err_latched <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR error_frame_ended OR go_overload_frame_xhdl32) = '1') THEN
form_err_latched <= '0' ;
ELSE
IF (form_err = '1') THEN
form_err_latched <= '1' ;
END IF;
END IF;
IF (rst = '1') THEN
form_err_latched <= '0';
END IF;
END IF;
END PROCESS;
xhdl_49 <= ((crc_enable AND sample_point) AND (NOT bit_de_stuff));
i_can_crc_core_sync_rx : can_crc_core_sync
PORT MAP (
clk => clk,
data => sampled_bit,
enable => xhdl_49,
initialize => go_crc_enable,
crc => calculated_crc);
no_byte0 <= rtr1 OR CONV_STD_LOGIC(data_len < "0001") ;
no_byte1 <= rtr1 OR CONV_STD_LOGIC(data_len < "0010") ;
temp_xhdl75 <= "101" WHEN ide = '1' ELSE "011";
temp_xhdl76 <= (temp_xhdl75) WHEN extended_mode = '1' ELSE "010";
header_len(2 DOWNTO 0) <= temp_xhdl76 ;
storing_header <= CONV_STD_LOGIC(header_cnt < header_len) ;
temp_xhdl77 <= (data_len - "0001") WHEN (data_len < "1000") ELSE "0111";
temp_xhdl78 <= "1111" WHEN remote_rq = '1' ELSE (temp_xhdl77);
limited_data_len_minus1(3 DOWNTO 0) <= temp_xhdl78 ;
reset_wr_fifo <= CONV_STD_LOGIC(data_cnt = (limited_data_len_minus1 + ('0' & header_len))) OR reset_mode ;
err <= form_err OR stuff_err OR bit_err OR ack_err OR form_err_latched OR stuff_err_latched OR bit_err_latched OR ack_err_latched OR crc_err ;
id_ok <= '1';
-- Write enable signal for 64-byte rx fifo
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- wr_fifo <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF (reset_wr_fifo = '1') THEN
wr_fifo <= '0' ;
ELSE
IF ((((go_rx_inter_xhdl9 AND id_ok) AND (NOT error_frame_ended)) AND ((NOT tx_state_xhdl2) OR self_rx_request)) = '1') THEN
wr_fifo <= '1' ;
END IF;
END IF;
IF (rst = '1') THEN
wr_fifo <= '0';
END IF;
END IF;
END PROCESS;
-- Header counter. Header length depends on the mode of operation and frame format.
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- header_cnt <= "000";
IF (clk'EVENT AND clk = '1') THEN
IF (reset_wr_fifo = '1') THEN
header_cnt <= "000" ;
ELSE
IF ((wr_fifo AND storing_header) = '1') THEN
header_cnt <= header_cnt + "001" ;
END IF;
END IF;
IF (rst = '1') THEN
header_cnt <= "000";
END IF;
END IF;
END PROCESS;
-- Data counter. Length of the data is limited to 8 bytes.
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- data_cnt <= "0000";
IF (clk'EVENT AND clk = '1') THEN
IF (reset_wr_fifo = '1') THEN
data_cnt <= "0000" ;
ELSE
IF (wr_fifo = '1') THEN
data_cnt <= data_cnt + "0001" ;
END IF;
END IF;
IF (rst = '1') THEN
data_cnt <= "0000";
END IF;
END IF;
END PROCESS;
-- Transmitting error frame.
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- error_frame <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR error_frame_ended OR go_overload_frame_xhdl32) = '1') THEN
error_frame <= '0' ;
ELSE
IF (go_error_frame_xhdl33 = '1') THEN
error_frame <= '1' ;
END IF;
END IF;
IF (rst = '1') THEN
error_frame <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- error_cnt1 <= "000";
IF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR error_frame_ended OR go_error_frame_xhdl33 OR go_overload_frame_xhdl32) = '1') THEN
error_cnt1 <= "000" ;
ELSE
IF (((error_frame AND tx_point) AND CONV_STD_LOGIC(error_cnt1 < "111")) = '1') THEN
error_cnt1 <= error_cnt1 + "001" ;
END IF;
END IF;
IF (rst = '1') THEN
error_cnt1 <= "000";
END IF;
END IF;
END PROCESS;
error_flag_over <= ((((NOT node_error_passive_xhdl26) AND sample_point) AND CONV_STD_LOGIC(error_cnt1 = "111")) OR ((node_error_passive_xhdl26 AND sample_point) AND CONV_STD_LOGIC(passive_cnt = "110"))) AND (NOT enable_error_cnt2) ;
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- error_flag_over_latched <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR error_frame_ended OR go_error_frame_xhdl33 OR go_overload_frame_xhdl32) = '1') THEN
error_flag_over_latched <= '0' ;
ELSE
IF (error_flag_over = '1') THEN
error_flag_over_latched <= '1' ;
END IF;
END IF;
IF (rst = '1') THEN
error_flag_over_latched <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- enable_error_cnt2 <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR error_frame_ended OR go_error_frame_xhdl33 OR go_overload_frame_xhdl32) = '1') THEN
enable_error_cnt2 <= '0' ;
ELSE
IF ((error_frame AND (error_flag_over AND sampled_bit)) = '1') THEN
enable_error_cnt2 <= '1' ;
END IF;
END IF;
IF (rst = '1') THEN
enable_error_cnt2 <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- error_cnt2 <= "000";
IF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR error_frame_ended OR go_error_frame_xhdl33 OR go_overload_frame_xhdl32) = '1') THEN
error_cnt2 <= "000" ;
ELSE
IF ((enable_error_cnt2 AND tx_point) = '1') THEN
error_cnt2 <= error_cnt2 + "001" ;
END IF;
END IF;
IF (rst = '1') THEN
error_cnt2 <= "000";
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- delayed_dominant_cnt <= "000";
IF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR enable_error_cnt2 OR go_error_frame_xhdl33 OR enable_overload_cnt2 OR go_overload_frame_xhdl32) = '1') THEN
delayed_dominant_cnt <= "000" ;
ELSE
IF (((sample_point AND (NOT sampled_bit)) AND CONV_STD_LOGIC((error_cnt1 = "111") OR (overload_cnt1 = "111"))) = '1') THEN
delayed_dominant_cnt <= delayed_dominant_cnt + "001" ;
END IF;
END IF;
IF (rst = '1') THEN
delayed_dominant_cnt <= "000";
END IF;
END IF;
END PROCESS;
-- passive_cnt
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- passive_cnt <= "001";
IF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR error_frame_ended OR go_error_frame_xhdl33 OR go_overload_frame_xhdl32 OR first_compare_bit) = '1') THEN
passive_cnt <= "001" ;
ELSE
IF ((sample_point AND CONV_STD_LOGIC(passive_cnt < "110")) = '1') THEN
IF (((error_frame AND (NOT enable_error_cnt2)) AND CONV_STD_LOGIC(sampled_bit = sampled_bit_q)) = '1') THEN
passive_cnt <= passive_cnt + "001" ;
ELSE
passive_cnt <= "001" ;
END IF;
END IF;
END IF;
IF (rst = '1') THEN
passive_cnt <= "001";
END IF;
END IF;
END PROCESS;
-- When comparing 6 equal bits, first is always equal
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- first_compare_bit <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF (go_error_frame_xhdl33 = '1') THEN
first_compare_bit <= '1' ;
ELSE
IF (sample_point = '1') THEN
first_compare_bit <= '0';
END IF;
END IF;
IF (rst = '1') THEN
first_compare_bit <= '0';
END IF;
END IF;
END PROCESS;
-- Transmitting overload frame.
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- overload_frame_xhdl4 <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR overload_frame_ended OR go_error_frame_xhdl33) = '1') THEN
overload_frame_xhdl4 <= '0' ;
ELSE
IF (go_overload_frame_xhdl32 = '1') THEN
overload_frame_xhdl4 <= '1' ;
END IF;
END IF;
IF (rst = '1') THEN
overload_frame_xhdl4 <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- overload_cnt1 <= "000";
IF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR overload_frame_ended OR go_error_frame_xhdl33 OR go_overload_frame_xhdl32) = '1') THEN
overload_cnt1 <= "000" ;
ELSE
IF (((overload_frame_xhdl4 AND tx_point) AND CONV_STD_LOGIC(overload_cnt1 < "111")) = '1') THEN
overload_cnt1 <= overload_cnt1 + "001" ;
END IF;
END IF;
IF (rst = '1') THEN
overload_cnt1 <= "000";
END IF;
END IF;
END PROCESS;
overload_flag_over <= (sample_point AND CONV_STD_LOGIC(overload_cnt1 = "111")) AND (NOT enable_overload_cnt2) ;
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- enable_overload_cnt2 <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR overload_frame_ended OR go_error_frame_xhdl33 OR go_overload_frame_xhdl32) = '1') THEN
enable_overload_cnt2 <= '0' ;
ELSE
IF ((overload_frame_xhdl4 AND (overload_flag_over AND sampled_bit)) = '1') THEN
enable_overload_cnt2 <= '1' ;
END IF;
END IF;
IF (rst = '1') THEN
enable_overload_cnt2 <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- overload_cnt2 <= "000";
IF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR overload_frame_ended OR go_error_frame_xhdl33 OR go_overload_frame_xhdl32) = '1') THEN
overload_cnt2 <= "000" ;
ELSE
IF ((enable_overload_cnt2 AND tx_point) = '1') THEN
overload_cnt2 <= overload_cnt2 + "001" ;
END IF;
END IF;
IF (rst = '1') THEN
overload_cnt2 <= "000";
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- overload_request_cnt <= "00";
IF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_error_frame_xhdl33 OR go_rx_id1) = '1') THEN
overload_request_cnt <= "00" ;
ELSE
IF ((overload_request AND overload_frame_xhdl4) = '1') THEN
overload_request_cnt <= overload_request_cnt + "01" ;
END IF;
END IF;
IF (rst = '1') THEN
overload_request_cnt <= "00";
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- overload_frame_blocked <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_error_frame_xhdl33 OR go_rx_id1) = '1') THEN
overload_frame_blocked <= '0' ;
ELSE
IF (((overload_request AND overload_frame_xhdl4) AND CONV_STD_LOGIC(overload_request_cnt = "10")) = '1') THEN
-- This is a second sequential overload_request
overload_frame_blocked <= '1' ;
END IF;
END IF;
IF (rst = '1') THEN
overload_frame_blocked <= '0';
END IF;
END IF;
END PROCESS;
send_ack_xhdl35 <= (((NOT tx_state_xhdl2) AND rx_ack) AND (NOT err)) AND (NOT listen_only_mode) ;
PROCESS (reset_mode, node_bus_off_xhdl13, tx_state_xhdl2, go_tx_xhdl34, bit_de_stuff_tx, tx_bit, tx_q, send_ack_xhdl35, go_overload_frame_xhdl32, overload_frame_xhdl4, overload_cnt1, go_error_frame_xhdl33, error_frame, error_cnt1, node_error_passive_xhdl26)
VARIABLE tx_next_xhdl30_xhdl105 : std_logic;
BEGIN
IF ((reset_mode OR node_bus_off_xhdl13) = '1') THEN
-- Reset or node_bus_off
tx_next_xhdl30_xhdl105 := '1';
ELSE
IF ((go_error_frame_xhdl33 OR error_frame) = '1') THEN
-- Transmitting error frame
IF (error_cnt1 < "110") THEN
IF (node_error_passive_xhdl26 = '1') THEN
tx_next_xhdl30_xhdl105 := '1';
ELSE
tx_next_xhdl30_xhdl105 := '0';
END IF;
ELSE
tx_next_xhdl30_xhdl105 := '1';
END IF;
ELSE
IF ((go_overload_frame_xhdl32 OR overload_frame_xhdl4) = '1') THEN
-- Transmitting overload frame
IF (overload_cnt1 < "110") THEN
tx_next_xhdl30_xhdl105 := '0';
ELSE
tx_next_xhdl30_xhdl105 := '1';
END IF;
ELSE
IF ((go_tx_xhdl34 OR tx_state_xhdl2) = '1') THEN
-- Transmitting message
tx_next_xhdl30_xhdl105 := ((NOT bit_de_stuff_tx) AND tx_bit) OR (bit_de_stuff_tx AND (NOT tx_q));
ELSE
IF (send_ack_xhdl35 = '1') THEN
-- Acknowledge
tx_next_xhdl30_xhdl105 := '0';
ELSE
tx_next_xhdl30_xhdl105 := '1';
END IF;
END IF;
END IF;
END IF;
END IF;
tx_next_xhdl30 <= tx_next_xhdl30_xhdl105;
END PROCESS;
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- tx_xhdl29 <= '1';
IF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
tx_xhdl29 <= '1';
ELSE
IF (tx_point = '1') THEN
tx_xhdl29 <= tx_next_xhdl30 ;
END IF;
END IF;
IF (rst = '1') THEN
tx_xhdl29 <= '1';
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- tx_q <= '0' ;
IF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
tx_q <= '0' ;
ELSE
IF (tx_point = '1') THEN
tx_q <= tx_xhdl29 AND (NOT go_early_tx_latched) ;
END IF;
END IF;
IF (rst = '1') THEN
tx_q <= '0' ;
END IF;
END IF;
END PROCESS;
-- Delayed tx point
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- tx_point_q <= '0' ;
IF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
tx_point_q <= '0' ;
ELSE
tx_point_q <= tx_point ;
END IF;
IF (rst = '1') THEN
tx_point_q <= '0' ;
END IF;
END IF;
END PROCESS;
-- Changing bit order from [7:0] to [0:7]
i_ibo_tx_data_0 : can_ibo_core_sync
PORT MAP (
di => tx_data_0,
do => r_tx_data_0);
i_ibo_tx_data_1 : can_ibo_core_sync
PORT MAP (
di => tx_data_1,
do => r_tx_data_1);
i_ibo_tx_data_2 : can_ibo_core_sync
PORT MAP (
di => tx_data_2,
do => r_tx_data_2);
i_ibo_tx_data_3 : can_ibo_core_sync
PORT MAP (
di => tx_data_3,
do => r_tx_data_3);
i_ibo_tx_data_4 : can_ibo_core_sync
PORT MAP (
di => tx_data_4,
do => r_tx_data_4);
i_ibo_tx_data_5 : can_ibo_core_sync
PORT MAP (
di => tx_data_5,
do => r_tx_data_5);
i_ibo_tx_data_6 : can_ibo_core_sync
PORT MAP (
di => tx_data_6,
do => r_tx_data_6);
i_ibo_tx_data_7 : can_ibo_core_sync
PORT MAP (
di => tx_data_7,
do => r_tx_data_7);
i_ibo_tx_data_8 : can_ibo_core_sync
PORT MAP (
di => tx_data_8,
do => r_tx_data_8);
i_ibo_tx_data_9 : can_ibo_core_sync
PORT MAP (
di => tx_data_9,
do => r_tx_data_9);
i_ibo_tx_data_10 : can_ibo_core_sync
PORT MAP (
di => tx_data_10,
do => r_tx_data_10);
i_ibo_tx_data_11 : can_ibo_core_sync
PORT MAP (
di => tx_data_11,
do => r_tx_data_11);
i_ibo_tx_data_12 : can_ibo_core_sync
PORT MAP (
di => tx_data_12,
do => r_tx_data_12);
-- Changing bit order from [14:0] to [0:14]
i_calculated_crc0 : can_ibo_core_sync
PORT MAP (
di => calculated_crc(14 DOWNTO 7),
do => r_calculated_crc(7 DOWNTO 0));
xhdl_106 <= calculated_crc(6 DOWNTO 0) & '0';
i_calculated_crc1 : can_ibo_core_sync
PORT MAP (
di => xhdl_106,
do => r_calculated_crc(15 DOWNTO 8));
basic_chain <= r_tx_data_1(7 DOWNTO 4) & "00" & r_tx_data_1(3 DOWNTO 0) & r_tx_data_0(7 DOWNTO 0) & '0' ;
basic_chain_data <= r_tx_data_9 & r_tx_data_8 & r_tx_data_7 & r_tx_data_6 & r_tx_data_5 & r_tx_data_4 & r_tx_data_3 & r_tx_data_2 ;
extended_chain_std <= r_tx_data_0(7 DOWNTO 4) & "00" & r_tx_data_0(1) & r_tx_data_2(2 DOWNTO 0) & r_tx_data_1(7 DOWNTO 0) & '0' ;
extended_chain_ext <= r_tx_data_0(7 DOWNTO 4) & "00" & r_tx_data_0(1) & r_tx_data_4(4 DOWNTO 0) & r_tx_data_3(7 DOWNTO 0) & r_tx_data_2(7 DOWNTO 3) & '1' & '1' & r_tx_data_2(2 DOWNTO 0) & r_tx_data_1(7 DOWNTO 0) & '0' ;
extended_chain_data_std <= r_tx_data_10 & r_tx_data_9 & r_tx_data_8 & r_tx_data_7 & r_tx_data_6 & r_tx_data_5 & r_tx_data_4 & r_tx_data_3 ;
extended_chain_data_ext <= r_tx_data_12 & r_tx_data_11 & r_tx_data_10 & r_tx_data_9 & r_tx_data_8 & r_tx_data_7 & r_tx_data_6 & r_tx_data_5 ;
PROCESS (extended_mode, rx_data, tx_pointer, extended_chain_data_std, extended_chain_data_ext, rx_crc, r_calculated_crc, r_tx_data_0, extended_chain_ext, extended_chain_std, basic_chain_data, basic_chain, finish_msg)
VARIABLE tx_bit_xhdl107 : std_logic;
BEGIN
IF (extended_mode = '1') THEN
IF (rx_data = '1') THEN
-- data stage
IF (r_tx_data_0(0) = '1') THEN
-- Extended frame
tx_bit_xhdl107 := extended_chain_data_ext(conv_integer(tx_pointer));
ELSE
tx_bit_xhdl107 := extended_chain_data_std(conv_integer(tx_pointer));
END IF;
ELSE
IF (rx_crc = '1') THEN
tx_bit_xhdl107 := r_calculated_crc(conv_integer(tx_pointer(3 downto 0)));
ELSE
IF (finish_msg = '1') THEN
tx_bit_xhdl107 := '1';
ELSE
IF (r_tx_data_0(0) = '1') THEN
-- Extended frame
tx_bit_xhdl107 := extended_chain_ext(conv_integer(tx_pointer));
ELSE
tx_bit_xhdl107 := extended_chain_std(conv_integer(tx_pointer));
END IF;
END IF;
END IF;
END IF;
ELSE
-- Basic mode
IF (rx_data = '1') THEN
-- data stage
tx_bit_xhdl107 := basic_chain_data(conv_integer(tx_pointer));
ELSE
IF (rx_crc = '1') THEN
tx_bit_xhdl107 := r_calculated_crc(conv_integer(tx_pointer));
ELSE
IF (finish_msg = '1') THEN
tx_bit_xhdl107 := '1';
ELSE
tx_bit_xhdl107 := basic_chain(conv_integer(tx_pointer));
END IF;
END IF;
END IF;
END IF;
tx_bit <= tx_bit_xhdl107;
END PROCESS;
temp_xhdl108 <= "111111" WHEN tx_data_0(3) = '1' ELSE ((tx_data_0(2 DOWNTO 0) & "000") - 1);
limited_tx_cnt_ext <= temp_xhdl108 ;
temp_xhdl109 <= "111111" WHEN tx_data_1(3) = '1' ELSE ((tx_data_1(2 DOWNTO 0) & "000") - 1);
limited_tx_cnt_std <= temp_xhdl109 ;
-- arbitration + control for extended format
-- arbitration + control for extended format
-- arbitration + control for standard format
-- data (overflow is OK here)
-- data (overflow is OK here)
-- crc
-- at the end
rst_tx_pointer <= ((((((NOT bit_de_stuff_tx) AND tx_point) AND (NOT rx_data)) AND extended_mode) AND r_tx_data_0(0)) AND CONV_STD_LOGIC(tx_pointer = "100110")) OR ((((((NOT bit_de_stuff_tx) AND tx_point) AND (NOT rx_data)) AND extended_mode) AND (NOT r_tx_data_0(0))) AND CONV_STD_LOGIC(tx_pointer = "010010")) OR (((((NOT bit_de_stuff_tx) AND tx_point) AND (NOT rx_data)) AND (NOT extended_mode)) AND CONV_STD_LOGIC(tx_pointer = "010010")) OR (((((NOT bit_de_stuff_tx) AND tx_point) AND rx_data) AND extended_mode) AND CONV_STD_LOGIC(tx_pointer = limited_tx_cnt_ext)) OR (((((NOT bit_de_stuff_tx) AND tx_point) AND rx_data) AND (NOT extended_mode)) AND CONV_STD_LOGIC(tx_pointer = limited_tx_cnt_std)) OR (tx_point AND rx_crc_lim) OR (go_rx_idle) OR (reset_mode) OR (overload_frame_xhdl4) OR (error_frame) ;
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- tx_pointer <= "000000";
IF (clk'EVENT AND clk = '1') THEN
IF (rst_tx_pointer = '1') THEN
tx_pointer <= "000000" ;
ELSE
IF ((go_early_tx OR ((tx_point AND (tx_state_xhdl2 OR go_tx_xhdl34)) AND (NOT bit_de_stuff_tx))) = '1') THEN
tx_pointer <= tx_pointer + "000001" ;
END IF;
END IF;
IF (rst = '1') THEN
tx_pointer <= "000000";
END IF;
END IF;
END PROCESS;
tx_successful_xhdl19 <= ((((transmitter_xhdl8 AND go_rx_inter_xhdl9) AND (NOT go_error_frame_xhdl33)) AND (NOT error_frame_ended)) AND (NOT overload_frame_ended)) AND (NOT arbitration_lost) ;
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- need_to_tx_xhdl20 <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF ((tx_successful_xhdl19 OR reset_mode OR (abort_tx AND (NOT transmitting_xhdl7)) OR (((NOT tx_state_xhdl2) AND tx_state_q_xhdl3) AND single_shot_transmission)) = '1') THEN
need_to_tx_xhdl20 <= '0' ;
ELSE
IF ((tx_request AND sample_point) = '1') THEN
need_to_tx_xhdl20 <= '1' ;
END IF;
END IF;
IF (rst = '1') THEN
need_to_tx_xhdl20 <= '0';
END IF;
END IF;
END PROCESS;
go_early_tx <= ((((((NOT listen_only_mode) AND need_to_tx_xhdl20) AND (NOT tx_state_xhdl2)) AND (NOT suspend OR CONV_STD_LOGIC(susp_cnt = "111"))) AND sample_point) AND (NOT sampled_bit)) AND (rx_idle_xhdl6 OR last_bit_of_inter) ;
go_tx_xhdl34 <= ((((NOT listen_only_mode) AND need_to_tx_xhdl20) AND (NOT tx_state_xhdl2)) AND (NOT suspend OR (sample_point AND CONV_STD_LOGIC(susp_cnt = "111")))) AND (go_early_tx OR rx_idle_xhdl6) ;
-- go_early_tx latched (for proper bit_de_stuff generation)
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- go_early_tx_latched <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR tx_point) = '1') THEN
go_early_tx_latched <= '0' ;
ELSE
IF (go_early_tx = '1') THEN
go_early_tx_latched <= '1' ;
END IF;
END IF;
IF (rst = '1') THEN
go_early_tx_latched <= '0';
END IF;
END IF;
END PROCESS;
-- Tx state
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- tx_state_xhdl2 <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_inter_xhdl9 OR error_frame OR arbitration_lost) = '1') THEN
tx_state_xhdl2 <= '0' ;
ELSE
IF (go_tx_xhdl34 = '1') THEN
tx_state_xhdl2 <= '1' ;
END IF;
END IF;
IF (rst = '1') THEN
tx_state_xhdl2 <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- tx_state_q_xhdl3 <= '0' ;
IF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
tx_state_q_xhdl3 <= '0' ;
ELSE
tx_state_q_xhdl3 <= tx_state_xhdl2 ;
END IF;
IF (rst = '1') THEN
tx_state_q_xhdl3 <= '0' ;
END IF;
END IF;
END PROCESS;
-- Node is a transmitter
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- transmitter_xhdl8 <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF (go_tx_xhdl34 = '1') THEN
transmitter_xhdl8 <= '1' ;
ELSE
IF ((reset_mode OR go_rx_idle or (suspend AND go_rx_id1)) = '1') THEN
transmitter_xhdl8 <= '0' ;
END IF;
END IF;
IF (rst = '1') THEN
transmitter_xhdl8 <= '0';
END IF;
END IF;
END PROCESS;
-- Signal "transmitting" signals that the core is a transmitting (message, error frame or overload frame). No synchronization is done meanwhile.
-- Node might be both transmitter or receiver (sending error or overload frame)
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- transmitting_xhdl7 <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF ((go_error_frame_xhdl33 OR go_overload_frame_xhdl32 OR go_tx_xhdl34 OR send_ack_xhdl35) = '1') THEN
transmitting_xhdl7 <= '1' ;
ELSE
IF ((reset_mode OR go_rx_idle OR (go_rx_id1 AND (NOT tx_state_xhdl2)) OR (arbitration_lost AND tx_state_xhdl2)) = '1') THEN
transmitting_xhdl7 <= '0' ;
END IF;
END IF;
IF (rst = '1') THEN
transmitting_xhdl7 <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- suspend <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR (sample_point AND CONV_STD_LOGIC(susp_cnt = "111"))) = '1') THEN
suspend <= '0' ;
ELSE
IF (((not_first_bit_of_inter_xhdl10 AND transmitter_xhdl8) AND node_error_passive_xhdl26) = '1') THEN
suspend <= '1' ;
END IF;
END IF;
IF (rst = '1') THEN
suspend <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- susp_cnt_en <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR (sample_point AND CONV_STD_LOGIC(susp_cnt = "111"))) = '1') THEN
susp_cnt_en <= '0' ;
ELSE
IF (((suspend AND sample_point) AND last_bit_of_inter) = '1') THEN
susp_cnt_en <= '1' ;
END IF;
END IF;
IF (rst = '1') THEN
susp_cnt_en <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- susp_cnt <= "000";
IF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR (sample_point AND CONV_STD_LOGIC(susp_cnt = "111"))) = '1') THEN
susp_cnt <= "000" ;
ELSE
IF ((susp_cnt_en AND sample_point) = '1') THEN
susp_cnt <= susp_cnt + "001" ;
END IF;
END IF;
IF (rst = '1') THEN
susp_cnt <= "000";
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- finish_msg <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF ((go_rx_idle OR go_rx_id1 OR error_frame OR reset_mode) = '1') THEN
finish_msg <= '0' ;
ELSE
IF (go_rx_crc_lim = '1') THEN
finish_msg <= '1' ;
END IF;
END IF;
IF (rst = '1') THEN
finish_msg <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- arbitration_lost <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF ((go_rx_idle OR error_frame_ended OR reset_mode) = '1') THEN
arbitration_lost <= '0' ;
ELSE
IF (((((transmitter_xhdl8 AND sample_point) AND tx_xhdl29) AND arbitration_field) AND NOT sampled_bit) = '1') THEN
arbitration_lost <= '1' ;
END IF;
END IF;
IF (rst = '1') THEN
arbitration_lost <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- arbitration_lost_q <= '0' ;
-- read_arbitration_lost_capture_reg_q <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
arbitration_lost_q <= '0';
read_arbitration_lost_capture_reg_q <= '0';
ELSE
arbitration_lost_q <= arbitration_lost;
read_arbitration_lost_capture_reg_q <= read_arbitration_lost_capture_reg ;
END IF;
IF (rst = '1') THEN
arbitration_lost_q <= '0' ;
read_arbitration_lost_capture_reg_q <= '0';
END IF;
END IF;
END PROCESS;
set_arbitration_lost_irq_xhdl24 <= (arbitration_lost AND (NOT arbitration_lost_q)) AND (NOT arbitration_blocked) ;
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- read_error_code_capture_reg_q <= '0';
IF (clk'EVENT AND clk = '1') THEN
read_error_code_capture_reg_q <= read_error_code_capture_reg;
IF (rst = '1') THEN
read_error_code_capture_reg_q <= '0';
END IF;
END IF;
END PROCESS;
reset_error_code_capture_reg <= read_error_code_capture_reg_q and not read_error_code_capture_reg;
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- arbitration_cnt_en <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR arbitration_blocked) = '1') THEN
arbitration_cnt_en <= '0' ;
ELSE
IF (((rx_id1 AND sample_point) AND (NOT arbitration_blocked)) = '1') THEN
arbitration_cnt_en <= '1' ;
END IF;
END IF;
IF (rst = '1') THEN
arbitration_cnt_en <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- arbitration_blocked <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR read_arbitration_lost_capture_reg) = '1') THEN
arbitration_blocked <= '0' ;
ELSE
IF (set_arbitration_lost_irq_xhdl24 = '1') THEN
arbitration_blocked <= '1' ;
END IF;
END IF;
IF (rst = '1') THEN
arbitration_blocked <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- arbitration_lost_capture_xhdl25 <= "00000";
IF (clk'EVENT AND clk = '1') THEN
IF (read_arbitration_lost_capture_reg_q = '1') THEN
arbitration_lost_capture_xhdl25 <= "00000" ;
ELSE
IF ((((sample_point AND (NOT arbitration_blocked)) AND arbitration_cnt_en) AND (NOT bit_de_stuff)) = '1') THEN
arbitration_lost_capture_xhdl25 <= arbitration_lost_capture_xhdl25 + "00001" ;
END IF;
END IF;
IF (rst = '1') THEN
arbitration_lost_capture_xhdl25 <= "00000";
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- rx_err_cnt_xhdl15 <= "000000000";
IF (clk'EVENT AND clk = '1') THEN
IF (set_reset_mode_xhdl12 = '1') THEN
rx_err_cnt_xhdl15 <= "000000000" ;
else
IF (((NOT listen_only_mode) AND (NOT transmitter_xhdl8 OR arbitration_lost)) = '1') THEN
IF ((((go_rx_ack_lim AND (NOT go_error_frame_xhdl33)) AND (NOT crc_err)) AND CONV_STD_LOGIC(rx_err_cnt_xhdl15 > "000000000")) = '1') THEN
IF (rx_err_cnt_xhdl15 > "001111111") THEN
rx_err_cnt_xhdl15 <= "001111111" ;
ELSE
rx_err_cnt_xhdl15 <= rx_err_cnt_xhdl15 - "000000001" ;
END IF;
ELSE
IF (rx_err_cnt_xhdl15 < "010000000") THEN
IF ((go_error_frame_xhdl33 AND (NOT rule5)) = '1') THEN
-- 1 (rule 5 is just the opposite then rule 1 exception
rx_err_cnt_xhdl15 <= rx_err_cnt_xhdl15 + "000000001" ;
ELSE
IF ((((((error_flag_over AND (NOT error_flag_over_latched)) AND sample_point) AND (NOT sampled_bit)) AND CONV_STD_LOGIC(error_cnt1 = "111")) OR (go_error_frame_xhdl33 AND rule5) OR ((sample_point AND (NOT sampled_bit)) AND CONV_STD_LOGIC(delayed_dominant_cnt = "111"))) = '1') THEN
-- 2
-- 5
-- 6
rx_err_cnt_xhdl15 <= rx_err_cnt_xhdl15 + "000001000" ;
END IF;
END IF;
END IF;
END IF;
END IF;
end if;
IF (rst = '1') THEN
rx_err_cnt_xhdl15 <= "000000000";
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- tx_err_cnt_xhdl16 <= "000000000";
IF (clk'EVENT AND clk = '1') THEN
IF (set_reset_mode_xhdl12 = '1') THEN
tx_err_cnt_xhdl16 <= "010000000" ;
ELSE
IF ((CONV_STD_LOGIC(tx_err_cnt_xhdl16 > "000000000") AND (tx_successful_xhdl19 OR bus_free)) = '1') THEN
tx_err_cnt_xhdl16 <= tx_err_cnt_xhdl16 - "000000001" ;
ELSE
IF ((transmitter_xhdl8 AND (NOT arbitration_lost)) = '1') THEN
IF ((((sample_point AND (NOT sampled_bit)) AND CONV_STD_LOGIC(delayed_dominant_cnt = "111")) OR (go_error_frame_xhdl33 AND rule5) OR ((go_error_frame_xhdl33 AND (NOT ((transmitter_xhdl8 AND node_error_passive_xhdl26) AND ack_err))) AND (NOT (((((transmitter_xhdl8 AND stuff_err) AND arbitration_field) AND sample_point) AND tx_xhdl29) AND (NOT sampled_bit)))) OR (error_frame AND rule3_exc1_2)) = '1') THEN
-- 6
-- 4 (rule 5 is the same as rule 4)
-- 3
-- 3
tx_err_cnt_xhdl16 <= tx_err_cnt_xhdl16 + "000001000" ;
END IF;
END IF;
END IF;
end if;
IF (rst = '1') THEN
tx_err_cnt_xhdl16 <= "000000000";
END IF;
END IF;
END PROCESS;
set_reset_mode_xhdl12 <= node_bus_off_xhdl13 AND (NOT node_bus_off_q) ; --##
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- node_error_passive_xhdl26 <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF ((rx_err_cnt_xhdl15 < "010000000") AND (tx_err_cnt_xhdl16 < "010000000")) THEN
node_error_passive_xhdl26 <= '0' ;
ELSE
IF (((CONV_STD_LOGIC((rx_err_cnt_xhdl15 >= "010000000") OR (tx_err_cnt_xhdl16 >= "010000000")) AND (error_frame_ended OR go_error_frame_xhdl33 OR ((NOT reset_mode) AND reset_mode_q))) AND (NOT node_bus_off_xhdl13)) = '1') THEN
node_error_passive_xhdl26 <= '1' ;
END IF;
END IF;
IF (rst = '1') THEN
node_error_passive_xhdl26 <= '0';
END IF;
END IF;
END PROCESS;
node_error_active_xhdl27 <= NOT (node_error_passive_xhdl26 OR node_bus_off_xhdl13) ;
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- node_bus_off_xhdl13 <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF ( (CONV_STD_LOGIC((rx_err_cnt_xhdl15 = "000000000") AND (tx_err_cnt_xhdl16 = "000000000")) AND (NOT reset_mode)) = '1' or restart = '1') THEN
node_bus_off_xhdl13 <= '0' ;
ELSE
IF (CONV_STD_LOGIC(tx_err_cnt_xhdl16 >= "100000000") = '1') THEN
node_bus_off_xhdl13 <= '1' ;
END IF;
END IF;
IF (rst = '1') THEN
node_bus_off_xhdl13 <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- bus_free_cnt <= "0000";
IF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
bus_free_cnt <= "0000" ;
ELSE
IF (sample_point = '1') THEN
IF (((sampled_bit AND bus_free_cnt_en) AND CONV_STD_LOGIC(bus_free_cnt < "1010")) = '1') THEN
bus_free_cnt <= bus_free_cnt + "0001" ;
ELSE
bus_free_cnt <= "0000" ;
END IF;
END IF;
END IF;
IF (rst = '1') THEN
bus_free_cnt <= "0000";
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- bus_free_cnt_en <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF ((((NOT reset_mode) AND reset_mode_q) OR (node_bus_off_q AND (NOT reset_mode))) = '1') THEN
bus_free_cnt_en <= '1' ;
ELSE
IF ((((sample_point AND sampled_bit) AND CONV_STD_LOGIC(bus_free_cnt = "1010")) AND (NOT node_bus_off_xhdl13)) = '1') THEN
bus_free_cnt_en <= '0' ;
END IF;
END IF;
IF (rst = '1') THEN
bus_free_cnt_en <= '1';
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- bus_free <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
bus_free <= '0';
ELSE
IF (((sample_point AND sampled_bit) AND CONV_STD_LOGIC(bus_free_cnt = "1010")) = '1') THEN
bus_free <= '1' ;
ELSE
bus_free <= '0' ;
END IF;
END IF;
IF (rst = '1') THEN
bus_free <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- waiting_for_bus_free <= '1';
IF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
waiting_for_bus_free <= '1';
ELSE
IF ((bus_free AND (NOT node_bus_off_xhdl13)) = '1') THEN
waiting_for_bus_free <= '0' ;
ELSE
IF ((((NOT reset_mode) AND reset_mode_q) OR (node_bus_off_q AND (NOT reset_mode))) = '1') THEN
waiting_for_bus_free <= '1' ;
END IF;
END IF;
END IF;
IF (rst = '1') THEN
waiting_for_bus_free <= '1';
END IF;
END IF;
END PROCESS;
transmit_status_xhdl17 <= transmitting_xhdl7 OR (extended_mode AND waiting_for_bus_free) ;
temp_xhdl111 <= (waiting_for_bus_free OR ((NOT rx_idle_xhdl6) AND (NOT transmitting_xhdl7))) WHEN extended_mode = '1' ELSE (((NOT waiting_for_bus_free) AND (NOT rx_idle_xhdl6)) AND (NOT transmitting_xhdl7));
receive_status_xhdl18 <= temp_xhdl111 ;
-- Error code capture register
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- error_capture_code_xhdl5 <= "00000000";
IF (clk'EVENT AND clk = '1') THEN
IF (reset_error_code_capture_reg = '1') THEN
error_capture_code_xhdl5 <= "00000000" ;
ELSE
IF (set_bus_error_irq_xhdl23 = '1') THEN
error_capture_code_xhdl5 <= error_capture_code_type(7 DOWNTO 6) & error_capture_code_direction & error_capture_code_segment(4 DOWNTO 0) ;
END IF;
END IF;
IF (rst = '1') THEN
error_capture_code_xhdl5 <= "00000000";
END IF;
END IF;
END PROCESS;
error_capture_code_segment(0) <= rx_idle_xhdl6 OR rx_ide OR (rx_id2 AND CONV_STD_LOGIC(bit_cnt < "001101")) OR rx_r1 OR rx_r0 OR rx_dlc OR rx_ack OR rx_ack_lim OR (error_frame AND node_error_active_xhdl27) ;
error_capture_code_segment(1) <= rx_idle_xhdl6 OR rx_id1 OR rx_id2 OR rx_dlc OR rx_data OR rx_ack_lim OR rx_eof OR rx_inter_xhdl11 OR (error_frame AND node_error_passive_xhdl26) ;
error_capture_code_segment(2) <= (rx_id1 AND CONV_STD_LOGIC(bit_cnt > "000111")) OR rx_rtr1 OR rx_ide OR rx_id2 OR rx_rtr2 OR rx_r1 OR (error_frame AND node_error_passive_xhdl26) OR overload_frame_xhdl4 ;
error_capture_code_segment(3) <= (rx_id2 AND CONV_STD_LOGIC(bit_cnt > "000100")) OR rx_rtr2 OR rx_r1 OR rx_r0 OR rx_dlc OR rx_data OR rx_crc OR rx_crc_lim OR rx_ack OR rx_ack_lim OR rx_eof OR overload_frame_xhdl4 ;
error_capture_code_segment(4) <= rx_crc_lim OR rx_ack OR rx_ack_lim OR rx_eof OR rx_inter_xhdl11 OR error_frame OR overload_frame_xhdl4 ;
error_capture_code_direction <= NOT transmitting_xhdl7 ;
PROCESS (bit_err, form_err, stuff_err)
VARIABLE error_capture_code_type_xhdl112 : std_logic_vector(7 DOWNTO 6);
BEGIN
IF (bit_err = '1') THEN
error_capture_code_type_xhdl112(7 DOWNTO 6) := "00";
ELSE
IF (form_err = '1') THEN
error_capture_code_type_xhdl112(7 DOWNTO 6) := "01";
ELSE
IF (stuff_err = '1') THEN
error_capture_code_type_xhdl112(7 DOWNTO 6) := "10";
ELSE
error_capture_code_type_xhdl112(7 DOWNTO 6) := "11";
END IF;
END IF;
END IF;
error_capture_code_type <= error_capture_code_type_xhdl112;
END PROCESS;
set_bus_error_irq_xhdl23 <= go_error_frame_xhdl33 AND (NOT error_capture_code_blocked) ;
PROCESS (clk, rst)
BEGIN
-- IF (rst = '1') THEN
-- error_capture_code_blocked <= '0';
IF (clk'EVENT AND clk = '1') THEN
IF (read_error_code_capture_reg = '1') THEN
error_capture_code_blocked <= '0' ;
ELSE
IF (set_bus_error_irq_xhdl23 = '1') THEN
error_capture_code_blocked <= '1' ;
END IF;
END IF;
IF (rst = '1') THEN
error_capture_code_blocked <= '0';
END IF;
END IF;
END PROCESS;
END ARCHITECTURE RTL;
----------------------------------------------------------------------------------------------
--
-- VHDL file generated by X-HDL - Revision 3.2.53 Aug. 1, 2005
-- Tue Aug 9 07:33:50 2005
--
-- Input file : C:/Documents and Settings/BryantI/My Documents/tmp/can_top.v
-- Design name : can_top
-- Author :
-- Company : Actel
--
-- Description :
--
--
----------------------------------------------------------------------------------------------
--
--////////////////////////////////////////////////////////////////////
--// ////
--// can_top.v ////
--// ////
--// ////
--// This file is part of the CAN Protocol Controller ////
--// http://www.opencores.org/projects/can/ ////
--// ////
--// ////
--// Author(s): ////
--// Igor Mohor ////
--// [email protected] ////
--// ////
--// ////
--// All additional information is available in the README.txt ////
--// file. ////
--// ////
--////////////////////////////////////////////////////////////////////
--// ////
--// Copyright (C) 2002, 2003, 2004 Authors ////
--// ////
--// This source file may be used and distributed without ////
--// restriction provided that this copyright statement is not ////
--// removed from the file and that any derivative work contains ////
--// the original copyright notice and the associated disclaimer. ////
--// ////
--// This source file is free software; you can redistribute it ////
--// and/or modify it under the terms of the GNU Lesser General ////
--// Public License as published by the Free Software Foundation; ////
--// either version 2.1 of the License, or (at your option) any ////
--// later version. ////
--// ////
--// This source is distributed in the hope that it will be ////
--// useful, but WITHOUT ANY WARRANTY; without even the implied ////
--// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
--// PURPOSE. See the GNU Lesser General Public License for more ////
--// details. ////
--// ////
--// You should have received a copy of the GNU Lesser General ////
--// Public License along with this source; if not, download it ////
--// from http://www.opencores.org/lgpl.shtml ////
--// ////
--// The CAN protocol is developed by Robert Bosch GmbH and ////
--// protected by patents. Anybody who wants to implement this ////
--// CAN IP core on silicon has to obtain a CAN protocol license ////
--// from Bosch. ////
--// ////
--////////////////////////////////////////////////////////////////////
--
-- CVS Revision History
--
-- $Log: can_top.v,v $
-- Revision 1.48 2004/10/25 11:44:47 igorm
-- Interrupt is always cleared for one clock after the irq register is read.
-- This fixes problems when CPU is using IRQs that are edge triggered.
--
-- Revision 1.47 2004/02/08 14:53:54 mohor
-- Header changed. Address latched to posedge. bus_off_on signal added.
--
-- Revision 1.46 2003/10/17 05:55:20 markom
-- mbist signals updated according to newest convention
--
-- Revision 1.45 2003/09/30 00:55:13 mohor
-- Error counters fixed to be compatible with Bosch VHDL reference model.
-- Small synchronization changes.
--
-- Revision 1.44 2003/09/25 18:55:49 mohor
-- Synchronization changed, error counters fixed.
--
-- Revision 1.43 2003/08/20 09:57:39 mohor
-- Tristate signal tx_o is separated to tx_o and tx_oen_o. Both signals need
-- to be joined together on higher level.
--
-- Revision 1.42 2003/07/16 15:11:28 mohor
-- Fixed according to the linter.
--
-- Revision 1.41 2003/07/10 15:32:27 mohor
-- Unused signal removed.
--
-- Revision 1.40 2003/07/10 01:59:04 tadejm
-- Synchronization fixed. In some strange cases it didn't work according to
-- the VHDL reference model.
--
-- Revision 1.39 2003/07/07 11:21:37 mohor
-- Little fixes (to fix warnings).
--
-- Revision 1.38 2003/07/03 09:32:20 mohor
-- Synchronization changed.
--
-- Revision 1.37 2003/06/27 20:56:15 simons
-- Virtual silicon ram instances added.
--
-- Revision 1.36 2003/06/17 14:30:30 mohor
-- "chip select" signal cs_can_i is used only when not using WISHBONE
-- interface.
--
-- Revision 1.35 2003/06/16 13:57:58 mohor
-- tx_point generated one clk earlier. rx_i registered. Data corrected when
-- using extended mode.
--
-- Revision 1.34 2003/06/13 15:02:24 mohor
-- Synchronization is also needed when transmitting a message.
--
-- Revision 1.33 2003/06/11 14:21:35 mohor
-- When switching to tx, sync stage is overjumped.
--
-- Revision 1.32 2003/06/09 11:32:36 mohor
-- Ports added for the CAN_BIST.
--
-- Revision 1.31 2003/03/26 11:19:46 mohor
-- CAN interrupt is active low.
--
-- Revision 1.30 2003/03/20 17:01:17 mohor
-- unix.
--
-- Revision 1.28 2003/03/14 19:36:48 mohor
-- can_cs signal used for generation of the cs.
--
-- Revision 1.27 2003/03/12 05:56:33 mohor
-- Bidirectional port_0_i changed to port_0_io.
-- input cs_can changed to cs_can_i.
--
-- Revision 1.26 2003/03/12 04:39:40 mohor
-- rd_i and wr_i are active high signals. If 8051 is connected, these two signals
-- need to be negated one level higher.
--
-- Revision 1.25 2003/03/12 04:17:36 mohor
-- 8051 interface added (besides WISHBONE interface). Selection is made in
-- can_defines.v file.
--
-- Revision 1.24 2003/03/10 17:24:40 mohor
-- wire declaration added.
--
-- Revision 1.23 2003/03/05 15:33:13 mohor
-- tx_o is now tristated signal. tx_oen and tx_o combined together.
--
-- Revision 1.22 2003/03/05 15:01:56 mohor
-- Top level signal names changed.
--
-- Revision 1.21 2003/03/01 22:53:33 mohor
-- Actel APA ram supported.
--
-- Revision 1.20 2003/02/19 15:09:02 mohor
-- Incomplete sensitivity list fixed.
--
-- Revision 1.19 2003/02/19 15:04:14 mohor
-- Typo fixed.
--
-- Revision 1.18 2003/02/19 14:44:03 mohor
-- CAN core finished. Host interface added. Registers finished.
-- Synchronization to the wishbone finished.
--
-- Revision 1.17 2003/02/18 00:10:15 mohor
-- Most of the registers added. Registers "arbitration lost capture", "error code
-- capture" + few more still need to be added.
--
-- Revision 1.16 2003/02/14 20:17:01 mohor
-- Several registers added. Not finished, yet.
--
-- Revision 1.15 2003/02/12 14:25:30 mohor
-- abort_tx added.
--
-- Revision 1.14 2003/02/11 00:56:06 mohor
-- Wishbone interface added.
--
-- Revision 1.13 2003/02/09 18:40:29 mohor
-- Overload fixed. Hard synchronization also enabled at the last bit of
-- interframe.
--
-- Revision 1.12 2003/02/09 02:24:33 mohor
-- Bosch license warning added. Error counters finished. Overload frames
-- still need to be fixed.
--
-- Revision 1.11 2003/02/04 14:34:52 mohor
-- *** empty log message ***
--
-- Revision 1.10 2003/01/31 01:13:38 mohor
-- backup.
--
-- Revision 1.9 2003/01/15 13:16:48 mohor
-- When a frame with "remote request" is received, no data is stored to
-- fifo, just the frame information (identifier, ...). Data length that
-- is stored is the received data length and not the actual data length
-- that is stored to fifo.
--
-- Revision 1.8 2003/01/14 17:25:09 mohor
-- Addresses corrected to decimal values (previously hex).
--
-- Revision 1.7 2003/01/10 17:51:34 mohor
-- Temporary version (backup).
--
-- Revision 1.6 2003/01/09 21:54:45 mohor
-- rx fifo added. Not 100 % verified, yet.
--
-- Revision 1.5 2003/01/08 02:10:56 mohor
-- Acceptance filter added.
--
-- Revision 1.4 2002/12/28 04:13:23 mohor
-- Backup version.
--
-- Revision 1.3 2002/12/27 00:12:52 mohor
-- Header changed, testbench improved to send a frame (crc still missing).
--
-- Revision 1.2 2002/12/26 16:00:34 mohor
-- Testbench define file added. Clock divider register added.
--
-- Revision 1.1.1.1 2002/12/20 16:39:21 mohor
-- Initial
--
--
--
-- synopsys translate_off
--`include "can_defines.v"
-- synopsys translate_on
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
ENTITY can_top_core_sync IS
PORT (
clk : IN std_logic;
reset_n : IN std_logic;
-- Config
sjw : IN std_logic_vector(1 DOWNTO 0);
bitrate : IN std_logic_vector(10 DOWNTO 0); --##
tseg1 : IN std_logic_vector(3 DOWNTO 0);
tseg2 : IN std_logic_vector(2 DOWNTO 0);
auto_restart : IN std_logic;
sampling : IN std_logic;
edge_mode : IN std_logic;
-- Transmit buffer
tx_data : IN std_logic_vector(63 DOWNTO 0);
tx_id : IN std_logic_vector(28 DOWNTO 0);
tx_dlc : IN std_logic_vector(3 DOWNTO 0);
tx_rtr : IN std_logic;
tx_ide : IN std_logic;
tx_msg_rdy : OUT std_logic;
tx_request : IN std_logic;
-- start-stop control
clr_stop : IN std_logic;
set_stop : IN std_logic;
-- start-stop status
want_stop : OUT std_logic;
grant_stop : OUT std_logic;
-- Receive buffer
rx_data : OUT std_logic_vector(63 DOWNTO 0);
rx_id : OUT std_logic_vector(28 DOWNTO 0);
rx_dlc : OUT std_logic_vector(3 DOWNTO 0);
rx_rtr : OUT std_logic;
rx_ide : OUT std_logic;
rx_msg_rdy : OUT std_logic;
-- Interrupt events
crc_err : OUT std_logic;
form_err : OUT std_logic;
ack_err : OUT std_logic;
stuff_err : OUT std_logic;
bit_err : OUT std_logic;
arb_loss : OUT std_logic;
overload : OUT std_logic;
-- Status and error counters
error_state : OUT std_logic_vector(1 DOWNTO 0);
rx_err_gte96 : OUT std_logic;
tx_err_gte96 : OUT std_logic;
rx_err_cnt : OUT std_logic_vector(7 DOWNTO 0);
tx_err_cnt : OUT std_logic_vector(8 DOWNTO 0);
-- CAN frame reference
rx_mode : OUT std_logic;
tx_mode : OUT std_logic;
field : OUT std_logic_vector(4 DOWNTO 0);
bit_nr : OUT std_logic_vector(5 DOWNTO 0);
stuff_ind : OUT std_logic;
remote_ind : OUT std_logic;
extended_ind : OUT std_logic;
-- CAN physical layer interface
can_rx_bus : IN std_logic;
can_tx_bus : OUT std_logic;
can_bus_ebl_n : OUT std_logic);
END ENTITY can_top_core_sync;
ARCHITECTURE RTL OF can_top_core_sync IS
COMPONENT can_bsp_core_sync
PORT (
clk : IN std_logic;
rst : IN std_logic;
restart : IN std_logic;
sample_point : IN std_logic;
sampled_bit : IN std_logic;
sampled_bit_q : IN std_logic;
tx_point : IN std_logic;
hard_sync : IN std_logic;
reset_mode : IN std_logic;
listen_only_mode : IN std_logic;
self_test_mode : IN std_logic;
tx_request : IN std_logic;
abort_tx : IN std_logic;
self_rx_request : IN std_logic;
single_shot_transmission: IN std_logic;
tx_state : OUT std_logic;
tx_state_q : OUT std_logic;
overload_request : IN std_logic;
overload_frame : OUT std_logic;
read_arbitration_lost_capture_reg: IN std_logic;
read_error_code_capture_reg: IN std_logic;
error_capture_code : OUT std_logic_vector(7 DOWNTO 0);
extended_mode : IN std_logic;
rx_idle : OUT std_logic;
transmitting : OUT std_logic;
transmitter : OUT std_logic;
go_rx_inter : OUT std_logic;
not_first_bit_of_inter : OUT std_logic;
rx_inter : OUT std_logic;
node_bus_off : OUT std_logic;
rx_err_cnt : OUT std_logic_vector(8 DOWNTO 0);
tx_err_cnt : OUT std_logic_vector(8 DOWNTO 0);
transmit_status : OUT std_logic;
receive_status : OUT std_logic;
tx_successful : OUT std_logic;
need_to_tx : OUT std_logic;
overrun : OUT std_logic;
set_bus_error_irq : OUT std_logic;
set_arbitration_lost_irq: OUT std_logic;
arbitration_lost_capture: OUT std_logic_vector(4 DOWNTO 0);
node_error_passive : OUT std_logic;
node_error_active : OUT std_logic;
tx_data_0 : IN std_logic_vector(7 DOWNTO 0);
tx_data_1 : IN std_logic_vector(7 DOWNTO 0);
tx_data_2 : IN std_logic_vector(7 DOWNTO 0);
tx_data_3 : IN std_logic_vector(7 DOWNTO 0);
tx_data_4 : IN std_logic_vector(7 DOWNTO 0);
tx_data_5 : IN std_logic_vector(7 DOWNTO 0);
tx_data_6 : IN std_logic_vector(7 DOWNTO 0);
tx_data_7 : IN std_logic_vector(7 DOWNTO 0);
tx_data_8 : IN std_logic_vector(7 DOWNTO 0);
tx_data_9 : IN std_logic_vector(7 DOWNTO 0);
tx_data_10 : IN std_logic_vector(7 DOWNTO 0);
tx_data_11 : IN std_logic_vector(7 DOWNTO 0);
tx_data_12 : IN std_logic_vector(7 DOWNTO 0);
rcv_msg_data : out std_logic_vector(63 downto 0);
rcv_id : out std_logic_vector(28 downto 0);
rcv_dlc : out std_logic_vector(3 downto 0);
rcv_rtr : out std_logic;
rcv_ide : out std_logic;
rcv_msg_valid : out std_logic;
form_error : out std_logic;
crc_error : out std_logic;
ack_error : out std_logic;
stuff_error : out std_logic;
bit_error : out std_logic;
arb_loss : out std_logic;
tx : OUT std_logic;
tx_next : OUT std_logic;
go_overload_frame : OUT std_logic;
go_error_frame : OUT std_logic;
go_tx : OUT std_logic;
send_ack : OUT std_logic);
END COMPONENT;
COMPONENT can_btl_core_sync
PORT (
clk : IN std_logic;
rst : IN std_logic;
rx : IN std_logic;
tx : IN std_logic;
baud_r_presc : IN std_logic_vector(10 DOWNTO 0); --##
sync_jump_width : IN std_logic_vector(1 DOWNTO 0);
time_segment1 : IN std_logic_vector(3 DOWNTO 0);
time_segment2 : IN std_logic_vector(2 DOWNTO 0);
triple_sampling : IN std_logic;
sample_point : OUT std_logic;
sampled_bit : OUT std_logic;
sampled_bit_q : OUT std_logic;
tx_point : OUT std_logic;
hard_sync : OUT std_logic;
rx_idle : IN std_logic;
rx_inter : IN std_logic;
transmitting : IN std_logic;
transmitter : IN std_logic;
go_rx_inter : IN std_logic;
tx_next : IN std_logic;
go_overload_frame : IN std_logic;
go_error_frame : IN std_logic;
go_tx : IN std_logic;
send_ack : IN std_logic;
node_error_passive : IN std_logic);
END COMPONENT;
SIGNAL reset_mode : std_logic;
SIGNAL listen_only_mode : std_logic;
SIGNAL self_test_mode : std_logic;
SIGNAL abort_tx : std_logic;
SIGNAL self_rx_request : std_logic;
SIGNAL single_shot_transmission : std_logic;
SIGNAL tx_state : std_logic;
SIGNAL tx_state_q : std_logic;
SIGNAL overload_request : std_logic;
SIGNAL overload_frame : std_logic;
SIGNAL error_capture_code : std_logic_vector(7 DOWNTO 0);
-- Clock Divider register
SIGNAL extended_mode : std_logic;
-- Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data
SIGNAL tx_data_0 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_1 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_2 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_3 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_4 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_5 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_6 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_7 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_8 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_9 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_10 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_11 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_12 : std_logic_vector(7 DOWNTO 0);
-- Output signals from can_btl_core_sync module
SIGNAL sample_point : std_logic;
SIGNAL sampled_bit : std_logic;
SIGNAL sampled_bit_q : std_logic;
SIGNAL tx_point : std_logic;
SIGNAL hard_sync : std_logic;
-- output from can_bsp_core_sync module
SIGNAL rx_idle : std_logic;
SIGNAL transmitting : std_logic;
SIGNAL transmitter : std_logic;
SIGNAL go_rx_inter : std_logic;
SIGNAL not_first_bit_of_inter : std_logic;
SIGNAL node_bus_off : std_logic;
SIGNAL transmit_status : std_logic;
SIGNAL receive_status : std_logic;
SIGNAL tx_successful : std_logic;
SIGNAL need_to_tx : std_logic;
SIGNAL overrun : std_logic;
SIGNAL node_error_passive : std_logic;
SIGNAL node_error_active : std_logic;
SIGNAL tx_next : std_logic;
SIGNAL go_overload_frame : std_logic;
SIGNAL go_error_frame : std_logic;
SIGNAL go_tx : std_logic;
SIGNAL send_ack : std_logic;
-- SIGNAL rst : std_logic;
SIGNAL rx_sync_tmp : std_logic;
SIGNAL rx_sync : std_logic;
SIGNAL xhdl_148 : std_logic_vector(8 DOWNTO 0);
SIGNAL xhdl_150 : std_logic_vector(8 DOWNTO 0);
SIGNAL tx_o_xhdl3 : std_logic;
SIGNAL rx_inter : std_logic;
signal rst, restart : std_logic;
signal ide, rtr : std_logic;
signal tx_req, tx_request_q, tx_success : std_logic;
BEGIN
rst <= not reset_n;
-- outputs
can_tx_bus <= tx_o_xhdl3;
can_bus_ebl_n <= '1' when reset_n = '0' else '1';
rx_err_cnt <= xhdl_148(7 DOWNTO 0);
tx_err_cnt <= xhdl_150(8 DOWNTO 0);
rx_err_gte96 <= '1' when unsigned(xhdl_148) >= 96 else '0';
tx_err_gte96 <= '1' when unsigned(xhdl_150) >= 96 else '0';
error_state(0) <= '0' when (node_error_active = '1') else '1';
error_state(1) <= '0' when (node_bus_off = '0') else '1';
tx_msg_rdy <= tx_success;
rx_rtr <= rtr;
rx_ide <= ide;
rx_mode <= receive_status;
tx_mode <= tx_state or tx_success; --## transmit_status;
remote_ind <= rtr;
extended_ind <= ide;
stuff_ind <= '0';
bit_nr <= (others => '0');
field <= (others => '0');
overload <= overload_frame;
want_stop <= '0';
grant_stop <= '0';
i_can_btl_core_sync : can_btl_core_sync
PORT MAP (
clk => clk,
rst => rst,
rx => rx_sync,
tx => tx_o_xhdl3,
baud_r_presc => bitrate, --##
sync_jump_width => sjw,
time_segment1 => tseg1,
time_segment2 => tseg2,
triple_sampling => sampling,
sample_point => sample_point,
sampled_bit => sampled_bit,
sampled_bit_q => sampled_bit_q,
tx_point => tx_point,
hard_sync => hard_sync,
rx_idle => rx_idle,
rx_inter => rx_inter,
transmitting => transmitting,
transmitter => transmitter,
go_rx_inter => go_rx_inter,
tx_next => tx_next,
go_overload_frame => go_overload_frame,
go_error_frame => go_error_frame,
go_tx => go_tx,
send_ack => send_ack,
node_error_passive => node_error_passive);
-- TX format conversion
tx_data_0 <= tx_ide & tx_rtr & "00" & tx_dlc;
tx_data_1 <= tx_id(28 downto 21);
tx_data_2 <= tx_id(20 downto 18) & "00000" when tx_ide = '0' else tx_id(20 downto 13);
tx_data_3 <= tx_data(63 downto 56) when tx_ide = '0' else tx_id(12 downto 5);
tx_data_4 <= tx_data(55 downto 48) when tx_ide = '0' else tx_id(4 downto 0) & "000";
tx_data_5 <= tx_data(47 downto 40) when tx_ide = '0' else tx_data(63 downto 56);
tx_data_6 <= tx_data(39 downto 32) when tx_ide = '0' else tx_data(55 downto 48);
tx_data_7 <= tx_data(31 downto 24) when tx_ide = '0' else tx_data(47 downto 40);
tx_data_8 <= tx_data(23 downto 16) when tx_ide = '0' else tx_data(39 downto 32);
tx_data_9 <= tx_data(15 downto 8) when tx_ide = '0' else tx_data(31 downto 24);
tx_data_10 <= tx_data(7 downto 0) when tx_ide = '0' else tx_data(23 downto 16);
tx_data_11 <= tx_data(15 downto 8);
tx_data_12 <= tx_data(7 downto 0);
reset_mode <= '1' when rst = '1' else '0';
listen_only_mode <= '0';
self_test_mode <= '0';
extended_mode <= '1';
overload_request <= '0';
abort_tx <= '0';
self_rx_request <= '0';
single_shot_transmission <= '1'; --##
restart <= '1' when (auto_restart = '0' and clr_stop = '1') else '0';
-- generate pulse
process(clk,rst)
begin
if rst='1' then
tx_req <= '0';
elsif Rising_Edge(clk) then
if tx_request='1' and transmit_status='0' then
tx_req <= '1';
elsif transmit_status='1' then
tx_req <= '0';
end if;
end if;
end process;
i_can_bsp_core_sync : can_bsp_core_sync
PORT MAP (
clk => clk,
rst => rst,
restart => restart,
sample_point => sample_point,
sampled_bit => sampled_bit,
sampled_bit_q => sampled_bit_q,
tx_point => tx_point,
hard_sync => hard_sync,
reset_mode => reset_mode,
listen_only_mode => listen_only_mode,
self_test_mode => self_test_mode,
tx_request => tx_req, --## tx_request, --##
abort_tx => abort_tx,
self_rx_request => self_rx_request,
single_shot_transmission => single_shot_transmission,
tx_state => tx_state,
tx_state_q => tx_state_q,
overload_request => overload_request,
overload_frame => overload_frame,
read_arbitration_lost_capture_reg => '0',
read_error_code_capture_reg => '0',
error_capture_code => open,
extended_mode => extended_mode,
rx_idle => rx_idle,
transmitting => transmitting,
transmitter => transmitter,
go_rx_inter => go_rx_inter,
not_first_bit_of_inter => not_first_bit_of_inter,
rx_inter => rx_inter,
node_bus_off => node_bus_off,
rx_err_cnt => xhdl_148,
tx_err_cnt => xhdl_150,
transmit_status => transmit_status,
receive_status => receive_status,
tx_successful => tx_successful,
need_to_tx => need_to_tx,
overrun => overrun,
set_bus_error_irq => open,
set_arbitration_lost_irq => open,
arbitration_lost_capture => open,
node_error_passive => node_error_passive,
node_error_active => node_error_active,
tx_data_0 => tx_data_0,
tx_data_1 => tx_data_1,
tx_data_2 => tx_data_2,
tx_data_3 => tx_data_3,
tx_data_4 => tx_data_4,
tx_data_5 => tx_data_5,
tx_data_6 => tx_data_6,
tx_data_7 => tx_data_7,
tx_data_8 => tx_data_8,
tx_data_9 => tx_data_9,
tx_data_10 => tx_data_10,
tx_data_11 => tx_data_11,
tx_data_12 => tx_data_12,
rcv_msg_data => rx_data,
rcv_id => rx_id,
rcv_dlc => rx_dlc,
rcv_rtr => rtr,
rcv_ide => ide,
rcv_msg_valid => rx_msg_rdy,
form_error => form_err,
crc_error => crc_err,
ack_error => ack_err,
stuff_error => stuff_err,
bit_error => bit_err,
arb_loss => arb_loss,
tx => tx_o_xhdl3,
tx_next => tx_next,
go_overload_frame => go_overload_frame,
go_error_frame => go_error_frame,
go_tx => go_tx,
send_ack => send_ack);
PROCESS (clk, rst)
BEGIN
IF (clk'EVENT AND clk = '1') THEN
IF (rst = '1') THEN
-- rx_sync_tmp <= '1';
rx_sync <= '1';
tx_request_q <= '0';
tx_success <= '0';
ELSE
-- rx_sync_tmp <= can_rx_bus;
-- rx_sync <= rx_sync_tmp ;
rx_sync <= can_rx_bus;
tx_request_q <= tx_request;
tx_success <= tx_successful;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE RTL;
| mit | 6fb44b02e5bf2e898fc0ed32a94022dc | 0.493721 | 3.57934 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/techmap/axcelerator/clkgen_axcelerator.vhd | 2 | 2,865 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: clkgen_actel
-- File: clkgen_actel.vhd
-- Author: Jiri Gaisler Gaisler Research
-- Description: Clock generator for Actel fpga
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library grlib;
use grlib.stdlib.all;
library axcelerator;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity clkgen_axcelerator is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
sdinvclk : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0);
port (
clkin : in std_ulogic;
pciclkin: in std_ulogic;
clk : out std_ulogic; -- main clock
clkn : out std_ulogic; -- inverted main clock
sdclk : out std_ulogic; -- SDRAM clock
pciclk : out std_ulogic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type);
end;
architecture struct of clkgen_axcelerator is
component hclkbuf
port( pad : in std_logic; y : out std_logic); end component;
component hclkbuf_pci
port( pad : in std_logic; y : out std_logic); end component;
signal clkint, pciclkint : std_ulogic;
begin
c0 : if (PCIEN = 0) or (PCISYSCLK=0) generate
u0 : hclkbuf port map (pad => clkin, y => clkint);
clk <= clkint;
clkn <= not clkint;
end generate;
c2 : if PCIEN/=0 generate
c1 : if PCISYSCLK=1 generate
clk <= pciclkint;
clkn <= not pciclkint;
end generate;
u0 : hclkbuf_pci port map (pad => pciclkin, y => pciclkint);
pciclk <= pciclkint;
end generate;
cgo.pcilock <= '1';
cgo.clklock <= '1';
sdclk <= '0';
-- pragma translate_off
bootmsg : report_version
generic map (
"clkgen_axcelerator" & ": using HCLKBUF as clock buffer");
-- pragma translate_on
end;
| mit | 4fd9cd215d508ab4d86980a39b105f6a | 0.610471 | 3.93544 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/jtag/ahbjtag.vhd | 2 | 3,933 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ahbjtag
-- File: ahbjtag.vhd
-- Author: Edvin Catovic, Jiri Gaisler - Gaisler Research
-- Description: JTAG communication link with AHB master interface
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.misc.all;
use gaisler.libjtagcom.all;
use gaisler.jtag.all;
entity ahbjtag is
generic (
tech : integer range 0 to NTECH := 0;
hindex : integer := 0;
nsync : integer range 1 to 2 := 1;
idcode : integer range 0 to 255 := 9;
manf : integer range 0 to 2047 := 804;
part : integer range 0 to 65535 := 0;
ver : integer range 0 to 15 := 0;
ainst : integer range 0 to 255 := 2;
dinst : integer range 0 to 255 := 3;
scantest : integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
tck : in std_ulogic;
tms : in std_ulogic;
tdi : in std_ulogic;
tdo : out std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_inst : out std_logic_vector(7 downto 0);
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapi_tdo : in std_ulogic;
trst : in std_ulogic := '1';
tdoen : out std_ulogic
);
end;
architecture struct of ahbjtag is
constant REVISION : integer := 0;
constant TAPSEL : integer := has_tapsel(tech);
signal dmai : ahb_dma_in_type;
signal dmao : ahb_dma_out_type;
signal ltapi : tap_in_type;
signal ltapo : tap_out_type;
signal taprst : std_ulogic;
begin
taprst <= trst and rst;
ahbmst0 : ahbmst
generic map (hindex => hindex, venid => VENDOR_GAISLER, devid => GAISLER_AHBJTAG)
port map (rst, clk, dmai, dmao, ahbi, ahbo);
tap0 : tap generic map (tech => tech, irlen => 6, idcode => idcode,
manf => manf, part => part, ver => ver, scantest => scantest)
port map (taprst, tck, tms, tdi, tdo, ltapo.tck, ltapo.tdi, ltapo.inst, ltapo.reset, ltapo.capt,
ltapo.shift, ltapo.upd, ltapo.asel, ltapo.dsel, ltapi.en, ltapi.tdo, tapi_tdo,
ahbi.testen, ahbi.testrst, tdoen);
jtagcom0 : jtagcom generic map (isel => TAPSEL, nsync => nsync, ainst => ainst, dinst => dinst)
port map (rst, clk, ltapo, ltapi, dmao, dmai);
tapo_tck <= ltapo.tck; tapo_tdi <= ltapo.tdi; tapo_inst <= ltapo.inst;
tapo_rst <= ltapo.reset; tapo_capt <= ltapo.capt; tapo_shft <= ltapo.shift;
tapo_upd <= ltapo.upd;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbjtag AHB Debug JTAG rev " & tost(REVISION));
-- pragma translate_on
end;
| mit | b1d6b807e8d191432d09938fae02ffac | 0.601576 | 3.731499 | false | false | false | false |
michaelfivez/ascon_hardware_implementation | ascon128128_serialized/Kernel/Ascon_block_datapath.vhd | 1 | 8,014 | -------------------------------------------------------------------------------
--! @project Serialized hardware implementation of Asconv128128
--! @author Michael Fivez
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is an hardware implementation made for my graduation thesis
--! at the KULeuven, in the COSIC department (year 2015-2016)
--! The thesis is titled 'Energy efficient hardware implementations of CAESAR submissions',
--! and can be found on the COSIC website (www.esat.kuleuven.be/cosic/publications)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Ascon_StateUpdate_datapath is
port(
Clk : in std_logic; -- Clock
Reset : in std_logic; -- Reset (synchronous)
-- Control signals
RoundNr : in std_logic_vector(3 downto 0); -- biggest round is 12
sel1,sel2,sel3,sel4 : in std_logic_vector(1 downto 0);
sel0 : in std_logic_vector(2 downto 0);
selout : in std_logic;
SelSbox : in std_logic_vector(1 downto 0);
SelDiff : in std_logic_vector(2 downto 0);
Reg0En,Reg1En,Reg2En,Reg3En,Reg4En,RegOutEn : in std_logic;
SboxEnable : in std_logic;
ActivateGen : in std_logic;
GenSize : in std_logic_vector(3 downto 0);
-- Data signals
IV : in std_logic_vector(127 downto 0);
Key : in std_logic_vector(127 downto 0);
DataIn : in std_logic_vector(127 downto 0);
DataOut : out std_logic_vector(127 downto 0)
);
end entity Ascon_StateUpdate_datapath;
architecture structural of Ascon_StateUpdate_datapath is
-- constants
constant EXTRAIV : std_logic_vector(63 downto 0) := x"80800c0800000000"; -- used in the initialization
constant SEPCONSTANT : std_logic_vector(63 downto 0) := x"0000000000000001";
constant ADCONSTANT : std_logic_vector(63 downto 0) := x"8000000000000000";
-- Register signals
signal SboxReg0In,SboxReg1In,SboxReg2In,SboxReg3In,SboxReg4In : std_logic_vector(63 downto 0);
signal SboxReg0Out,SboxReg1Out,SboxReg2Out,SboxReg3Out,SboxReg4Out : std_logic_vector(63 downto 0);
signal DiffReg0Out,DiffReg1Out,DiffReg2Out,DiffReg3Out,DiffReg4Out : std_logic_vector(63 downto 0);
signal RegOutIn,RegOutOut : std_logic_vector(127 downto 0);
-- Internal signals on datapath
signal Sbox0In,Sbox1In,Sbox2In,Sbox3In,Sbox4In : std_logic_vector(15 downto 0);
signal Sbox0Out,Sbox1Out,Sbox2Out,Sbox3Out,Sbox4Out : std_logic_vector(15 downto 0);
signal Diff1In, Diff2In, Diff3In, DiffOut : std_logic_vector(63 downto 0);
signal XorReg01,XorReg02,XorReg11,XorReg12 : std_logic_vector(63 downto 0);
signal XorReg2,XorReg31,XorReg32,XorReg4 : std_logic_vector(63 downto 0);
signal OutSig0,OutSig1 : std_logic_vector(127 downto 0);
begin
-- declare and connect all sub entities
sboxregisters: entity work.Sbox_registers port map(Clk ,Sbox0Out, Sbox1Out, Sbox2Out, Sbox3Out, Sbox4Out, Sbox0In, Sbox1In, Sbox2In, Sbox3In, Sbox4In,
SboxReg0In, SboxReg1In, SboxReg2In, SboxReg3In, SboxReg4In, SboxReg0Out, SboxReg1Out, SboxReg2Out, SboxReg3Out, SboxReg4Out,
SelSbox, SboxEnable, Reg0En, Reg1En, Reg2En, Reg3En, Reg4En);
sbox: entity work.Sbox port map(Sbox0In,Sbox1In,Sbox2In,Sbox3In,Sbox4In,RoundNr,Sbox0Out,Sbox1Out,Sbox2Out,Sbox3Out,Sbox4Out,SelSbox);
difflayer: entity work.FullDiffusionLayer port map(Diff1In,Diff2In,Diff3In,DiffOut);
outpgen: entity work.OutputGenerator port map(SboxReg0Out,SboxReg1Out,DataIn,GenSize,ActivateGen,XorReg01,XorReg11,OutSig0); -- ActivateGen is a bit that indicates decryption or not
---------------------------------------------
------ Combinatorial logic for a round ------
---------------------------------------------
datapath: process(Diff1In, Diff2In, Diff3In, DiffOut, SboxReg0In, SboxReg1In, SboxReg2In, SboxReg3In, SboxReg4In,
OutSig0, OutSig1, XorReg01, XorReg02, XorReg11, XorReg12, XorReg2, XorReg31, XorReg32, XorReg4,
SboxReg0Out, SboxReg1Out, SboxReg2Out, SboxReg3Out, SboxReg4Out, Key, IV, RegOutIn, RegOutOut, sel0, sel1, sel2, sel3, sel4,
selout) is
begin
-- Set correct inputs in registers
if sel0 = "000" then
SboxReg0In <= DiffOut;
elsif sel0 = "001" then
SboxReg0In <= EXTRAIV;
elsif sel0 = "010" then
SboxReg0In <= XorReg01;
elsif sel0 = "011" then
SboxReg0In <= XorReg02;
else
SboxReg0In <= SboxReg0Out xor ADCONSTANT;
end if;
if sel1 = "00" then
SboxReg1In <= DiffOut;
elsif sel1 = "01" then
SboxReg1In <= Key(127 downto 64);
elsif sel1 = "10" then
SboxReg1In <= XorReg11;
else
SboxReg1In <= XorReg12;
end if;
if sel2 = "00" then
SboxReg2In <= DiffOut;
elsif sel2 = "01" then
SboxReg2In <= Key(63 downto 0);
else
SboxReg2In <= XorReg2;
end if;
if sel3 = "00" then
SboxReg3In <= DiffOut;
elsif sel3 = "01" then
SboxReg3In <= IV(127 downto 64);
elsif sel3 = "10" then
SboxReg3In <= XorReg31;
else
SboxReg3In <= XorReg32;
end if;
if sel4 = "00" then
SboxReg4In <= DiffOut;
elsif sel4 = "01" then
SboxReg4In <= IV(63 downto 0);
elsif sel4 = "10" then
SboxReg4In <= XorReg4;
else
SboxReg4In <= SboxReg4Out xor SEPCONSTANT;
end if;
XorReg02 <= SboxReg0Out xor Key(127 downto 64);
XorReg12 <= SboxReg1Out xor Key(63 downto 0);
XorReg2 <= SboxReg2Out xor Key(127 downto 64);
XorReg31 <= SboxReg3Out xor Key(127 downto 64);
XorReg32 <= SboxReg3Out xor Key(63 downto 0);
XorReg4 <= SboxReg4Out xor Key(63 downto 0);
-- Set output
OutSig1(127 downto 64) <= XorReg31;
OutSig1(63 downto 0) <= XorReg4;
if selout = '0' then
RegOutIn <= OutSig0;
else
RegOutIn <= OutSig1;
end if;
DataOut <= RegOutOut;
if SelDiff = "000" then
Diff1In(63 downto 64 - 19) <= SboxReg0Out(19 - 1 downto 0);
Diff1In(63 - 19 downto 0) <= SboxReg0Out(63 downto 19);
Diff2In(63 downto 64 - 28) <= SboxReg0Out(28 - 1 downto 0);
Diff2In(63 - 28 downto 0) <= SboxReg0Out(63 downto 28);
Diff3In <= SboxReg0Out;
elsif SelDiff = "001" then
Diff1In(63 downto 64 - 61) <= SboxReg1Out(61 - 1 downto 0);
Diff1In(63 - 61 downto 0) <= SboxReg1Out(63 downto 61);
Diff2In(63 downto 64 - 39) <= SboxReg1Out(39 - 1 downto 0);
Diff2In(63 - 39 downto 0) <= SboxReg1Out(63 downto 39);
Diff3In <= SboxReg1Out;
elsif SelDiff = "010" then
Diff1In(63 downto 64 - 1) <= SboxReg2Out(1 - 1 downto 0);
Diff1In(63 - 1 downto 0) <= SboxReg2Out(63 downto 1);
Diff2In(63 downto 64 - 6) <= SboxReg2Out(6 - 1 downto 0);
Diff2In(63 - 6 downto 0) <= SboxReg2Out(63 downto 6);
Diff3In <= SboxReg2Out;
elsif SelDiff = "011" then
Diff1In(63 downto 64 - 10) <= SboxReg3Out(10 - 1 downto 0);
Diff1In(63 - 10 downto 0) <= SboxReg3Out(63 downto 10);
Diff2In(63 downto 64 - 17) <= SboxReg3Out(17 - 1 downto 0);
Diff2In(63 - 17 downto 0) <= SboxReg3Out(63 downto 17);
Diff3In <= SboxReg3Out;
else
Diff1In(63 downto 64 - 7) <= SboxReg4Out(7 - 1 downto 0);
Diff1In(63 - 7 downto 0) <= SboxReg4Out(63 downto 7);
Diff2In(63 downto 64 - 41) <= SboxReg4Out(41 - 1 downto 0);
Diff2In(63 - 41 downto 0) <= SboxReg4Out(63 downto 41);
Diff3In <= SboxReg4Out;
end if;
end process datapath;
---------------------------------------------
------ The registers in the datapath --------
---------------------------------------------
registerdatapath : process(Clk,Reset) is
begin
if(Clk = '1' and Clk'event) then
if Reset = '1' then -- synchronous reset
RegOutOut <= (others => '0');
else
if RegOutEn = '1' then
RegOutOut <= RegOutIn;
end if;
end if;
end if;
end process registerdatapath;
end architecture structural;
| gpl-3.0 | 9ee1080017515d13c38f3d38bb4e844e | 0.652857 | 2.926954 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/ddr/ddr2spa.vhd | 2 | 6,038 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ddr2spa
-- File: ddr2spa.vhd
-- Author: Nils-Johan Wessman - Gaisler Research
-- Description: 16-, 32- or 64-bit DDR2 memory controller module.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use grlib.devices.all;
use gaisler.memctrl.all;
library techmap;
use techmap.gencomp.all;
entity ddr2spa is
generic (
fabtech : integer := virtex4;
memtech : integer := 0;
rskew : integer := 0;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
MHz : integer := 100;
clkmul : integer := 2;
clkdiv : integer := 2;
col : integer := 9;
Mbyte : integer := 16;
rstdel : integer := 200;
pwron : integer := 0;
oepol : integer := 0;
ddrbits : integer := 16;
ahbfreq : integer := 50;
readdly : integer := 1; -- 1 added read latency cycle
ddelayb0 : integer := 0; -- Data delay value (0 - 63)
ddelayb1 : integer := 0; -- Data delay value (0 - 63)
ddelayb2 : integer := 0; -- Data delay value (0 - 63)
ddelayb3 : integer := 0; -- Data delay value (0 - 63)
ddelayb4 : integer := 0; -- Data delay value (0 - 63)
ddelayb5 : integer := 0; -- Data delay value (0 - 63)
ddelayb6 : integer := 0; -- Data delay value (0 - 63)
ddelayb7 : integer := 0; -- Data delay value (0 - 63)
numidelctrl : integer := 4;
norefclk : integer := 0;
odten : integer := 0
);
port (
rst_ddr : in std_ulogic;
rst_ahb : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
clkref200 : in std_logic;
lock : out std_ulogic; -- DCM locked
clkddro : out std_ulogic; -- DCM locked
clkddri : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (ddrbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (ddrbits/8-1 downto 0); -- ddr dqs
ddr_dqsn : inout std_logic_vector (ddrbits/8-1 downto 0); -- ddr dqsn
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (ddrbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(1 downto 0)
);
end;
architecture rtl of ddr2spa is
constant DDR_FREQ : integer := (clkmul * MHz) / clkdiv;
constant FAST_AHB : integer := AHBFREQ / DDR_FREQ;
signal sdi : sdctrl_in_type;
signal sdo : sdctrl_out_type;
--signal clkread : std_ulogic;
begin
ddr_phy0 : ddr2_phy generic map (tech => fabtech, MHz => MHz,
dbits => ddrbits, rstdelay => rstdel, clk_mul => clkmul,
clk_div => clkdiv,
ddelayb0 => ddelayb0, ddelayb1 => ddelayb1, ddelayb2 => ddelayb2,
ddelayb3 => ddelayb3, ddelayb4 => ddelayb4, ddelayb5 => ddelayb5,
ddelayb6 => ddelayb6, ddelayb7 => ddelayb7,
numidelctrl => numidelctrl, norefclk => norefclk)
port map (
rst_ddr, clk_ddr, clkref200, clkddro,
lock,
ddr_clk, ddr_clkb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb, ddr_dm,
ddr_dqs, ddr_dqsn, ddr_ad, ddr_ba, ddr_dq, ddr_odt, sdi, sdo);
ddr16 : if ddrbits = 16 generate
ddrc : ddr2sp16a generic map (memtech => memtech, hindex => hindex,
haddr => haddr, hmask => hmask, ioaddr => ioaddr, iomask => iomask,
pwron => pwron, MHz => DDR_FREQ, col => col, Mbyte => Mbyte,
fast => FAST_AHB, readdly => readdly, odten => odten)
port map (rst_ahb, clkddri, clk_ahb, ahbsi, ahbso, sdi, sdo);
end generate;
ddr32 : if ddrbits = 32 generate
ddrc : ddr2sp32a generic map (memtech => memtech, hindex => hindex,
haddr => haddr, hmask => hmask, ioaddr => ioaddr, iomask => iomask,
pwron => pwron, MHz => DDR_FREQ, col => col, Mbyte => Mbyte,
fast => FAST_AHB/2, readdly => readdly, odten => odten)
port map (rst_ahb, clkddri, clk_ahb, ahbsi, ahbso, sdi, sdo);
end generate;
ddr64 : if ddrbits = 64 generate
ddrc : ddr2sp64a generic map (memtech => memtech, hindex => hindex,
haddr => haddr, hmask => hmask, ioaddr => ioaddr, iomask => iomask,
pwron => pwron, MHz => DDR_FREQ, col => col, Mbyte => Mbyte,
fast => FAST_AHB/4, readdly => readdly, odten => odten)
port map (rst_ahb, clkddri, clk_ahb, ahbsi, ahbso, sdi, sdo);
end generate;
end;
| mit | 3d8613d65d283a107fe65d8217ba2db4 | 0.582312 | 3.679464 | false | false | false | false |
mgiacomini/mips-monocycle | TB_MAIN_PROCESSOR.vhd | 2 | 2,119 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:35:44 08/06/2015
-- Design Name:
-- Module Name: E:/Programas_FPGA/SYNGLE_CYCLE_V3/TB_MAIN_PROCESSOR.vhd
-- Project Name: SYNGLE_CYCLE_V3
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: MAIN_PROCESSOR
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
ENTITY TB_MAIN_PROCESSOR IS
END TB_MAIN_PROCESSOR;
ARCHITECTURE behavior OF TB_MAIN_PROCESSOR IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT MAIN_PROCESSOR
PORT(
CLK : IN std_logic;
RESET : IN std_logic
);
END COMPONENT;
--Inputs
signal CLK : std_logic := '0';
signal RESET : std_logic := '0';
-- Clock period definitions
constant CLK_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: MAIN_PROCESSOR PORT MAP (
CLK => CLK,
RESET => RESET
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
RESET <= '1';
wait for 10 ns;
RESET <= '0';
WAIT;
end process;
END;
| gpl-3.0 | e941952c93c665de15a25a8da8a3a1ff | 0.578575 | 3.924074 | false | true | false | false |
lxp32/lxp32-cpu | verify/icache/src/tb/ram_model.vhd | 2 | 1,869 | ---------------------------------------------------------------------
-- RAM model
--
-- Part of the LXP32 instruction cache testbench
--
-- Copyright (c) 2016 by Alex I. Kuznetsov
--
-- Simulates RAM controller which provides WISHBONE registered
-- feedback interface.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.common_pkg.all;
use work.tb_pkg.all;
entity ram_model is
port(
clk_i: in std_logic;
wbm_cyc_i: in std_logic;
wbm_stb_i: in std_logic;
wbm_cti_i: in std_logic_vector(2 downto 0);
wbm_bte_i: in std_logic_vector(1 downto 0);
wbm_ack_o: out std_logic;
wbm_adr_i: in std_logic_vector(29 downto 0);
wbm_dat_o: out std_logic_vector(31 downto 0)
);
end entity;
architecture sim of ram_model is
signal ack: std_logic:='0';
signal cycle: std_logic:='0';
begin
wbm_ack_o<=ack;
process (clk_i) is
begin
if rising_edge(clk_i) then
if wbm_cyc_i='1' and wbm_stb_i='1' and wbm_cti_i="010" and wbm_bte_i="00" then
cycle<='1';
elsif wbm_cyc_i='0' or (wbm_cyc_i='1' and wbm_stb_i='1' and (wbm_cti_i/="010" or wbm_bte_i/="00")) then
cycle<='0';
end if;
end if;
end process;
process is
variable rng_state: rng_state_type;
variable delay: integer;
begin
wait until rising_edge(clk_i) and wbm_cyc_i='1' and wbm_stb_i='1';
ack<='0';
-- Random delay before the first beat
if cycle='0' then
rand(rng_state,0,3,delay);
if delay>0 then
for i in 1 to delay loop
wait until rising_edge(clk_i) and wbm_cyc_i='1' and wbm_stb_i='1';
end loop;
end if;
end if;
if ack='0' then
wbm_dat_o<=("00"&wbm_adr_i) xor xor_constant;
ack<='1';
elsif wbm_cti_i="010" and wbm_bte_i="00" then
wbm_dat_o<=("00"&std_logic_vector(unsigned(wbm_adr_i)+1)) xor xor_constant;
ack<='1';
end if;
end process;
end architecture;
| mit | 92c2dc180e918a3fd850a945c3d53b9d | 0.611557 | 2.708696 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/misc/apbps2.vhd | 2 | 13,132 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: apbps2
-- File: apbps2.vhd
-- Author: Marcus Hellqvist, Jiri Gaisler
-- Description: PS/2 keyboard interface
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
use grlib.amba.all;
use grlib.devices.all;
library gaisler;
use gaisler.misc.all;
entity apbps2 is
generic(
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
fKHz : integer := 50000;
fixed : integer := 1
);
port(
rst : in std_ulogic; -- Global asynchronous reset
clk : in std_ulogic; -- Global clock
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ps2i : in ps2_in_type;
ps2o : out ps2_out_type
);
end;
architecture rtl of apbps2 is
constant fifosize : integer := 16;
type rxstates is (idle,start,data,parity,stop);
type txstates is (idle,waitrequest,start,data,parity,stop,ack);
type fifotype is array(0 to fifosize-1) of std_logic_vector(7 downto 0);
type ps2_regs is record
-- status reg
data_ready : std_ulogic; -- data ready
parity_error : std_ulogic; -- parity carry out/ error bit
frame_error : std_ulogic; -- frame error when receiving
kb_inh : std_ulogic; -- keyboard inhibit
rbf : std_ulogic; -- receiver buffer full
tbf : std_ulogic; -- transmitter buffer full
rcnt : std_logic_vector(log2x(fifosize) downto 0); -- fifo counter
tcnt : std_logic_vector(log2x(fifosize) downto 0); -- fifo counter
-- control reg
rx_en : std_ulogic; -- receive enable
tx_en : std_ulogic; -- transmit enable
rx_irq_en : std_ulogic; -- keyboard interrupt enable
tx_irq_en : std_ulogic; -- transmit interrupt enable
-- others
tx_act : std_ulogic; -- tx active
rxdf : std_logic_vector(4 downto 0); -- rx data filter
rxcf : std_logic_vector(4 downto 0); -- rx clock filter
rx_irq : std_ulogic; -- keyboard interrupt
tx_irq : std_ulogic; -- transmit interrupt
rxfifo : fifotype; -- fifo with 16 bytes
rraddr : std_logic_vector(log2x(fifosize)-1 downto 0); -- fifo read address
rwaddr : std_logic_vector(log2x(fifosize)-1 downto 0); -- fifo write address
rxstate : rxstates;
txfifo : fifotype; -- fifo with 16 bytes
traddr : std_logic_vector(log2x(fifosize)-1 downto 0); -- fifo read address
twaddr : std_logic_vector(log2x(fifosize)-1 downto 0); -- fifo write address
txstate : txstates;
ps2_clk_syn : std_ulogic; -- ps2 clock synchronized
ps2_data_syn : std_ulogic; -- ps2 data synchronized
ps2_clk_fall : std_ulogic; -- ps2 clock falling edge detector
rshift : std_logic_vector(7 downto 0); -- shift register
rpar : std_ulogic; -- parity check bit
tshift : std_logic_vector(9 downto 0); -- shift register
tpar : std_ulogic; -- transmit parity bit
ps2clk : std_ulogic; -- ps2 clock
ps2data : std_ulogic; -- ps2 data
ps2clkoe : std_ulogic; -- ps2 clock output enable
ps2dataoe : std_ulogic; -- ps2 data output enable
timer : std_logic_vector(13 downto 0); -- timer
reload : std_logic_vector(13 downto 0); -- reload register
end record;
constant rcntzero : std_logic_vector(log2x(fifosize) downto 0) := (others => '0');
constant REVISION : integer := 1;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_APBPS2, 0, REVISION, pirq),
1 => apb_iobar(paddr, pmask));
signal r, rin : ps2_regs;
signal ps2_clk, ps2_data : std_ulogic;
begin
ps2_op : process(r, rst, ps2_clk, ps2_data,apbi)
variable v : ps2_regs;
variable rdata : std_logic_vector(31 downto 0);
variable irq : std_logic_vector(NAHBIRQ-1 downto 0);
begin
v := r;
rdata := (others => '0'); v.data_ready := '0'; irq := (others => '0'); irq(pirq) := r.rx_irq or r.tx_irq;
v.rx_irq := '0'; v.tx_irq := '0'; v.rbf := r.rcnt(log2x(fifosize)); v.tbf := r.tcnt(log2x(fifosize));
if r.rcnt /= rcntzero then v.data_ready := '1'; end if;
-- Synchronize and filter ps2 input
v.rxdf(0) := ps2_data; v.rxdf(4 downto 1) := r.rxdf(3 downto 0);
v.rxcf(0) := ps2_clk; v.rxcf(4 downto 1) := r.rxcf(3 downto 0);
if (r.rxdf(4) & r.rxdf(4) & r.rxdf(4) & r.rxdf(4)) = r.rxdf(3 downto 0) then
v.ps2_data_syn := r.rxdf(4);
end if;
if (r.rxcf(4) & r.rxcf(4) & r.rxcf(4) & r.rxcf(4)) = r.rxcf(3 downto 0) then
v.ps2_clk_syn := r.rxcf(4);
end if;
if (v.ps2_clk_syn /= r.ps2_clk_syn) and (v.ps2_clk_syn = '0') then
v.ps2_clk_fall := '1';
else
v.ps2_clk_fall := '0';
end if;
-- read registers
case apbi.paddr(3 downto 2) is
when "00" =>
rdata(7 downto 0) := r.rxfifo(conv_integer(r.rraddr));
if (apbi.psel(pindex) and apbi.penable and (not apbi.pwrite)) = '1' then
if r.rcnt /= rcntzero then
v.rxfifo(conv_integer(r.rraddr)) := (others => '0');
v.rraddr := r.rraddr + 1; v.rcnt := r.rcnt - 1;
end if;
end if;
when "01" =>
rdata(27 + log2x(fifosize) downto 27) := r.rcnt;
rdata(22 + log2x(fifosize) downto 22) := r.tcnt;
rdata(5 downto 0) := r.tbf & r.rbf & r.kb_inh & r.frame_error & r.parity_error & r.data_ready;
when "10" =>
rdata(3 downto 0) := r.tx_irq_en & r.rx_irq_en & r.tx_en & r.rx_en;
when others =>
if fixed = 0 then rdata(13 downto 0) := r.reload; end if;
end case;
-- write registers
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(3 downto 2) is
when "00" =>
if r.tcnt(log2x(fifosize)) = '0' then
v.txfifo(conv_integer(r.twaddr)) := apbi.pwdata(7 downto 0);
v.twaddr := r.twaddr + 1; v.tcnt := r.tcnt + 1;
end if;
when "01" =>
v.kb_inh := apbi.pwdata(3);
v.frame_error := apbi.pwdata(2);
v.parity_error := apbi.pwdata(1);
when "10" =>
v.tx_irq_en := apbi.pwdata(3);
v.rx_irq_en := apbi.pwdata(2);
v.tx_en := apbi.pwdata(1);
v.rx_en := apbi.pwdata(0);
when "11" =>
if fixed = 0 then
v.reload := apbi.pwdata(13 downto 0);
end if;
when others =>
null;
end case;
end if;
case r.txstate is
when idle =>
if r.tx_en = '1' and r.tcnt /= rcntzero then
v.ps2clk := '0'; v.ps2clkoe := '0'; v.tx_act := '1';
v.ps2data := '1'; v.ps2dataoe := '0'; v.txstate := waitrequest;
end if;
when waitrequest =>
v.timer := r.timer - 1;
if (v.timer(13) and not r.timer(13)) = '1' then
if fixed = 1 then v.timer := conv_std_logic_vector(fKHz/10,14);
else v.timer := r.reload; end if;
v.ps2clk := '1'; v.ps2data := '0'; v.txstate := start;
end if;
when start =>
v.ps2clkoe := '1';
v.tshift := "10" & r.txfifo(conv_integer(r.traddr));
v.traddr := r.traddr + 1; v.tcnt := r.tcnt - 1;
v.tpar := '1';
v.txstate := data;
when data =>
if r.ps2_clk_fall = '1' then
v.ps2data := r.tshift(0);
v.tpar := r.tpar xor r.tshift(0);
v.tshift := '1' & r.tshift(9 downto 1);
if v.tshift = "1111111110" then v.txstate := parity; end if;
end if;
when parity =>
if r.ps2_clk_fall = '1' then
v.ps2data := r.tpar; v.txstate := stop;
end if;
when stop =>
if r.ps2_clk_fall = '1' then
v.ps2data := '1'; v.txstate := ack;
end if;
when ack =>
v.ps2dataoe := '1';
if r.ps2_clk_fall = '1' and r.ps2_data_syn = '0'then
v.ps2data := '1'; v.ps2dataoe := '0'; v.tx_irq := r.tx_irq_en;
v.txstate := idle; v.tx_act := '0';
end if;
end case;
-- receiver state machine
case r.rxstate is
when idle =>
if (r.rx_en and not r.tx_act) = '1' then
v.rshift := (others => '1'); v.rxstate := start;
end if;
when start =>
if r.ps2_clk_fall = '1' then
if r.ps2_data_syn = '0' then
v.rshift := r.ps2_data_syn & r.rshift(7 downto 1);
v.rxstate := data; v.rpar := '0';
v.parity_error := '0'; v.frame_error := '0';
else v.rxstate := idle; end if;
end if;
when data =>
if r.ps2_clk_fall = '1' then
v.rshift := r.ps2_data_syn & r.rshift(7 downto 1);
v.rpar := r.rpar xor r.ps2_data_syn;
if r.rshift(0) = '0' then v.rxstate := parity; end if;
end if;
when parity =>
if r.ps2_clk_fall = '1' then
v.parity_error := r.rpar xor (not r.ps2_data_syn);
v.rxstate := stop;
end if;
when stop =>
if r.ps2_clk_fall = '1' then
if r.ps2_data_syn = '1' then
v.rx_irq := r.rx_irq_en; v.rxstate := idle;
if (r.rbf or r.parity_error) = '0' then
v.rxfifo(conv_integer(r.rwaddr)) := r.rshift(7 downto 0);
v.rwaddr := r.rwaddr + 1; v.rcnt := r.rcnt + 1;
end if;
else v.frame_error := '1'; v.rxstate := idle; end if;
end if;
end case;
-- keyboard inhibit / high impedance
if v.tx_act = '0' then
if r.rbf = '1' then
v.kb_inh := '1'; v.ps2clk := '0'; v.ps2data := '1';
v.ps2dataoe := '0'; v.ps2clkoe := '0';
else
v.ps2clk := '1'; v.ps2data := '1'; v.ps2dataoe := '1';
v.ps2clkoe := '1';
end if;
end if;
if r.tx_act = '1' then
v.rxstate := idle;
end if;
-- reset operations
if rst = '0' then
v.data_ready := '0'; v.kb_inh := '0'; v.parity_error := '0';
v.frame_error := '0'; v.rx_en := '0'; v.tx_act := '0';
v.tx_en := '0'; v.rx_irq := '0'; v.tx_irq := '0';
v.ps2_clk_fall := '0'; v.ps2_clk_syn := '0'; v.ps2_data_syn := '0';
v.rshift := (others => '0'); v.rxstate := idle; v.txstate := idle;
v.rraddr := (others => '0'); v.rwaddr := (others => '0');
v.rcnt := (others => '0'); v.traddr := (others => '0');
v.twaddr := (others => '0'); v.tcnt := (others => '0');
v.tshift := (others => '0'); v.tpar := '0';
v.timer := conv_std_logic_vector(fKHz/10,14);
end if;
-- update registers
rin <= v;
-- drive outputs
apbo.prdata <= rdata;
apbo.pirq <= irq;
apbo.pindex <= pindex;
ps2o.ps2_clk_o <= r.ps2clk;
ps2o.ps2_clk_oe <= r.ps2clkoe;
ps2o.ps2_data_o <= r.ps2data;
ps2o.ps2_data_oe <= r.ps2dataoe;
end process;
apbo.pconfig <= pconfig;
regs : process(clk)
begin
if rising_edge(clk) then
r <= rin;
ps2_data <= to_x01(ps2i.ps2_data_i);
ps2_clk <= to_x01(ps2i.ps2_clk_i);
end if;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("apbps2_" & tost(pindex) & ": APB PS2 interface rev 0, irq "
& tost(pirq));
-- pragma translate_on
end;
| mit | e828ae77d4dc88bafcd347076724684e | 0.504721 | 3.331304 | false | false | false | false |
amerc/phimii | testing_gbitethernet.vhd | 2 | 10,696 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:11:12 05/19/2014
-- Design Name:
-- Module Name: /home/amer/Nexys3/TCP/testing_gbitethernet.vhd
-- Project Name: TCP
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: NEXYS3
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY testing_gbitethernet IS
END testing_gbitethernet;
ARCHITECTURE behavior OF testing_gbitethernet IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT NEXYS3
PORT(
CLK_IN : IN std_logic;
RST : IN std_logic;
TX : OUT std_logic;
RX : IN std_logic;
PHY_RESET : OUT std_logic;
RXDV : IN std_logic;
RXER : INOUT std_logic;
RXCLK : INOUT std_logic;
RXD : INOUT std_logic_vector(3 downto 0);
TXCLK : IN std_logic;
TXD : OUT std_logic_vector(3 downto 0);
TXEN : OUT std_logic;
TXER : INOUT std_logic;
PhyCol : INOUT std_logic;
GPIO_LEDS : OUT std_logic_vector(7 downto 0);
GPIO_SWITCHES : IN std_logic_vector(7 downto 0);
GPIO_BUTTONS : IN std_logic_vector(3 downto 0);
RS232_RX : IN std_logic;
RS232_TX : OUT std_logic
);
END COMPONENT;
--Inputs
signal CLK_IN : std_logic := '0';
signal RST : std_logic := '0';
signal RX : std_logic := '0';
signal RXDV : std_logic := '0';
signal TXCLK : std_logic := '0';
signal GPIO_SWITCHES : std_logic_vector(7 downto 0) := (others => '0');
signal GPIO_BUTTONS : std_logic_vector(3 downto 0) := (others => '0');
signal RS232_RX : std_logic := '0';
--BiDirs
signal RXER : std_logic;
signal RXCLK : std_logic;
signal RXD : std_logic_vector(3 downto 0);
signal TXER : std_logic;
signal PhyCol : std_logic;
--Outputs
signal TX : std_logic;
signal PHY_RESET : std_logic;
signal TXD : std_logic_vector(3 downto 0);
signal TXEN : std_logic;
signal GPIO_LEDS : std_logic_vector(7 downto 0);
signal RS232_TX : std_logic;
-- Clock period definitions
constant CLK_IN_period : time := 10 ns;
constant RXCLK_period : time := 10 ns;
constant TXCLK_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: NEXYS3 PORT MAP (
CLK_IN => CLK_IN,
RST => RST,
TX => TX,
RX => RX,
PHY_RESET => PHY_RESET,
RXDV => RXDV,
RXER => RXER,
RXCLK => RXCLK,
RXD => RXD,
TXCLK => TXCLK,
TXD => TXD,
TXEN => TXEN,
TXER => TXER,
PhyCol => PhyCol,
GPIO_LEDS => GPIO_LEDS,
GPIO_SWITCHES => GPIO_SWITCHES,
GPIO_BUTTONS => GPIO_BUTTONS,
RS232_RX => RS232_RX,
RS232_TX => RS232_TX
);
-- Clock process definitions
CLK_IN_process :process
begin
CLK_IN <= '0';
wait for CLK_IN_period/2;
CLK_IN <= '1';
wait for CLK_IN_period/2;
end process;
RXCLK_process :process
begin
RXCLK <= '0';
wait for RXCLK_period/2;
RXCLK <= '1';
wait for RXCLK_period/2;
end process;
TXCLK_process :process
begin
TXCLK <= '0';
wait for TXCLK_period/2;
TXCLK <= '1';
wait for TXCLK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for 30 ms;
-- insert stimulus here
wait for 10 ns;
RST <= '1' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"5" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '1' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '1' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"5" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '1' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '1' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"5" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '1' ;
RX_ACK <= '0' ; --1
wait for 10 ns;
RST <= '1' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"5" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '1' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"5" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ; --2
wait for 10 ns;
RST <= '1' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"5" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '1' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"5" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ; --3
wait for 10 ns;
RST <= '1' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"5" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '1' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '1' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"5" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '0' ;
RX_ACK <= '0' ;--4
wait for 10 ns;
RST <= '1' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"5" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '1' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '1' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"5" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '1' ;
RX_ACK <= '0' ; --5
wait for 10 ns;
RST <= '1' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"5" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '1' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '1' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"5" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '1' ;
RX_ACK <= '0' ; --6
wait for 10 ns;
RST <= '1' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"5" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '1' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '1' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"5" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '1' ;
RX_ACK <= '0' ; --7
wait for 10 ns;
RST <= '1' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"D" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '1' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '1' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"5" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '1' ;
RX_ACK <= '0' ; --8 -------------
wait for 10 ns;
RST <= '1' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"a" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '1' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '1' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"b" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '1' ;
RX_ACK <= '0' ; --5
wait for 10 ns;
RST <= '1' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"c" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '1' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '1' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"d" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '1' ;
RX_ACK <= '0' ; --6
wait for 10 ns;
RST <= '1' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"e" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '1' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '1' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"f" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '1' ;
RX_ACK <= '0' ; --7
wait for 10 ns;
RST <= '1' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"1" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '1' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '1' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"2" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '1' ;
RX_ACK <= '1' ; --8
wait for 10 ns;
RST <= '1' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"f" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '1' ;
RX_ACK <= '0' ; --7
wait for 10 ns;
RST <= '1' ;
RXER <= '0' ;
RXDV <= '1' ;
RXD <= x"1" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '1' ;
RX_ACK <= '0' ;
wait for 10 ns;
RST <= '1' ;
RXER <= '0' ;
RXDV <= '0' ;
RXD <= x"2" ;
COL <= '0' ;
TX <= x"3263" ;
TX_STB <= '1' ;
RX_ACK <= '1' ; --8
wait;
end process;
END;
| mit | fbd374332366c957b082b1665298b5a3 | 0.367708 | 3.439228 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/pci/pcitb_clkgen.vhd | 2 | 2,158 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: pcitb_clkgen
-- File: pcitb_clkgen.vhd
-- Author: Alf Vaerneus, Gaisler Research
-- Description: PCI clock & reset generator
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.pcitb.all;
entity pcitb_clkgen is
generic (
mhz66 : boolean := false;
rstclocks : integer := 20);
port (
rsttrig : in std_logic;
systclk : out pci_syst_type);
end pcitb_clkgen;
architecture tb of pcitb_clkgen is
signal clk : std_logic;
begin
systclk.clk <= clk;
clkgen: process
begin
if mhz66 then
clk <= '1';
wait for 7 ns;
clk <= '0';
wait for 8 ns;
else
clk <= '1';
wait for 15 ns;
clk <= '0';
wait for 15 ns;
end if;
end process;
reset : process
begin
if rsttrig = '1' then
systclk.rst <= '0';
if mhz66 then
wait for rstclocks*15 ns;
else
wait for rstclocks*30 ns;
end if;
wait until clk = '1';
end if;
systclk.rst <= '1';
wait for 1 ns;
end process;
end;
-- pragma translate_on
| mit | 4ea1bc1fc71ee6f4e0a4b2e471640091 | 0.577386 | 3.996296 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | VhdlParser/test/iu3Memory.vhd | 2 | 107,731 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008, 2009, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: iu3
-- File: iu3.vhd
-- Author: Jiri Gaisler, Edvin Catovic, Gaisler Research
-- Description: LEON3 7-stage integer pipline
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.sparc.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.leon3.all;
use gaisler.libiu.all;
use gaisler.arith.all;
-- pragma translate_off
use grlib.sparc_disas.all;
-- pragma translate_on
entity iu3 is
generic (
nwin : integer range 2 to 32 := 8;
isets : integer range 1 to 4 := 2;
dsets : integer range 1 to 4 := 2;
fpu : integer range 0 to 15 := 0;
v8 : integer range 0 to 63 := 2;
cp, mac : integer range 0 to 1 := 0;
dsu : integer range 0 to 1 := 1;
nwp : integer range 0 to 4 := 2;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
index : integer range 0 to 15:= 0;
lddel : integer range 1 to 2 := 1;
irfwt : integer range 0 to 1 := 0;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 2; -- trace buf size in kB (0 - no trace buffer)
pwd : integer range 0 to 2 := 0; -- power-down
svt : integer range 0 to 1 := 0; -- single-vector trapping
rstaddr : integer := 16#00000#; -- reset vector MSB address
smp : integer range 0 to 15 := 0; -- support SMP systems
fabtech : integer range 0 to NTECH := 20;
clk2x : integer := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
holdn : in std_ulogic;
ici : buffer icache_in_type;
ico : in icache_out_type;
dci : buffer dcache_in_type;
dco : in dcache_out_type;
rfi : buffer iregfile_in_type;
rfo : in iregfile_out_type;
irqi : in l3_irq_in_type;
irqo : buffer l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : buffer l3_debug_out_type;
muli : buffer mul32_in_type;
mulo : in mul32_out_type;
divi : buffer div32_in_type;
divo : in div32_out_type;
fpo : in fpc_out_type;
fpi : buffer fpc_in_type;
cpo : in fpc_out_type;
cpi : buffer fpc_in_type;
tbo : in tracebuf_out_type;
tbi : buffer tracebuf_in_type;
sclk : in std_ulogic
);
end;
architecture rtl of iu3 is
constant ISETMSB : integer := 0;
constant DSETMSB : integer := 0;
constant RFBITS : integer range 6 to 10 := 8;
constant NWINLOG2 : integer range 1 to 5 := 3;
constant CWPOPT : boolean := true;
constant CWPMIN : std_logic_vector(2 downto 0) := "000";
constant CWPMAX : std_logic_vector(2 downto 0) := "111";
constant FPEN : boolean := (fpu /= 0);
constant CPEN : boolean := false;
constant MULEN : boolean := true;
constant MULTYPE: integer := 0;
constant DIVEN : boolean := true;
constant MACEN : boolean := false;
constant MACPIPE: boolean := false;
constant IMPL : integer := 15;
constant VER : integer := 3;
constant DBGUNIT : boolean := true;
constant TRACEBUF : boolean := true;
constant TBUFBITS : integer := 7;
constant PWRD1 : boolean := false; --(pwd = 1) and not (index /= 0);
constant PWRD2 : boolean := false; --(pwd = 2) or (index /= 0);
constant RS1OPT : boolean := true;
constant DYNRST : boolean := false;
subtype word is std_logic_vector(31 downto 0);
subtype pctype is std_logic_vector(31 downto 2);
subtype rfatype is std_logic_vector(8-1 downto 0);
subtype cwptype is std_logic_vector(3-1 downto 0);
type icdtype is array (0 to 2-1) of word;
type dcdtype is array (0 to 2-1) of word;
type dc_in_type is record
signed, enaddr, read, write, lock , dsuen : std_ulogic;
size : std_logic_vector(1 downto 0);
asi : std_logic_vector(7 downto 0);
end record;
type pipeline_ctrl_type is record
pc : pctype;
inst : word;
cnt : std_logic_vector(1 downto 0);
rd : rfatype;
tt : std_logic_vector(5 downto 0);
trap : std_ulogic;
annul : std_ulogic;
wreg : std_ulogic;
wicc : std_ulogic;
wy : std_ulogic;
ld : std_ulogic;
pv : std_ulogic;
rett : std_ulogic;
end record;
type fetch_reg_type is record
pc : pctype;
branch : std_ulogic;
end record;
type decode_reg_type is record
pc : pctype;
inst : icdtype;
cwp : cwptype;
set : std_logic_vector(0 downto 0);
mexc : std_ulogic;
cnt : std_logic_vector(1 downto 0);
pv : std_ulogic;
annul : std_ulogic;
inull : std_ulogic;
step : std_ulogic;
end record;
type regacc_reg_type is record
ctrl : pipeline_ctrl_type;
rs1 : std_logic_vector(4 downto 0);
rfa1, rfa2 : rfatype;
rsel1, rsel2 : std_logic_vector(2 downto 0);
rfe1, rfe2 : std_ulogic;
cwp : cwptype;
imm : word;
ldcheck1 : std_ulogic;
ldcheck2 : std_ulogic;
ldchkra : std_ulogic;
ldchkex : std_ulogic;
su : std_ulogic;
et : std_ulogic;
wovf : std_ulogic;
wunf : std_ulogic;
ticc : std_ulogic;
jmpl : std_ulogic;
step : std_ulogic;
mulstart : std_ulogic;
divstart : std_ulogic;
end record;
type execute_reg_type is record
ctrl : pipeline_ctrl_type;
op1 : word;
op2 : word;
aluop : std_logic_vector(2 downto 0); -- Alu operation
alusel : std_logic_vector(1 downto 0); -- Alu result select
aluadd : std_ulogic;
alucin : std_ulogic;
ldbp1, ldbp2 : std_ulogic;
invop2 : std_ulogic;
shcnt : std_logic_vector(4 downto 0); -- shift count
sari : std_ulogic; -- shift msb
shleft : std_ulogic; -- shift left/right
ymsb : std_ulogic; -- shift left/right
rd : std_logic_vector(4 downto 0);
jmpl : std_ulogic;
su : std_ulogic;
et : std_ulogic;
cwp : cwptype;
icc : std_logic_vector(3 downto 0);
mulstep: std_ulogic;
mul : std_ulogic;
mac : std_ulogic;
end record;
type memory_reg_type is record
ctrl : pipeline_ctrl_type;
result : word;
y : word;
icc : std_logic_vector(3 downto 0);
nalign : std_ulogic;
dci : dc_in_type;
werr : std_ulogic;
wcwp : std_ulogic;
irqen : std_ulogic;
irqen2 : std_ulogic;
mac : std_ulogic;
divz : std_ulogic;
su : std_ulogic;
mul : std_ulogic;
end record;
type exception_state is (run, trap, dsu1, dsu2);
type exception_reg_type is record
ctrl : pipeline_ctrl_type;
result : word;
y : word;
icc : std_logic_vector( 3 downto 0);
annul_all : std_ulogic;
data : dcdtype;
set : std_logic_vector(0 downto 0);
mexc : std_ulogic;
dci : dc_in_type;
laddr : std_logic_vector(1 downto 0);
rstate : exception_state;
npc : std_logic_vector(2 downto 0);
intack : std_ulogic;
ipend : std_ulogic;
mac : std_ulogic;
debug : std_ulogic;
nerror : std_ulogic;
end record;
type dsu_registers is record
tt : std_logic_vector(7 downto 0);
err : std_ulogic;
tbufcnt : std_logic_vector(7-1 downto 0);
asi : std_logic_vector(7 downto 0);
crdy : std_logic_vector(2 downto 1); -- diag cache access ready
end record;
type irestart_register is record
addr : pctype;
pwd : std_ulogic;
end record;
type pwd_register_type is record
pwd : std_ulogic;
error : std_ulogic;
end record;
type special_register_type is record
cwp : cwptype; -- current window pointer
icc : std_logic_vector(3 downto 0); -- integer condition codes
tt : std_logic_vector(7 downto 0); -- trap type
tba : std_logic_vector(19 downto 0); -- trap base address
wim : std_logic_vector(8-1 downto 0); -- window invalid mask
pil : std_logic_vector(3 downto 0); -- processor interrupt level
ec : std_ulogic; -- enable CP
ef : std_ulogic; -- enable FP
ps : std_ulogic; -- previous supervisor flag
s : std_ulogic; -- supervisor flag
et : std_ulogic; -- enable traps
y : word;
asr18 : word;
svt : std_ulogic; -- enable traps
dwt : std_ulogic; -- disable write error trap
end record;
type write_reg_type is record
s : special_register_type;
result : word;
wa : rfatype;
wreg : std_ulogic;
except : std_ulogic;
end record;
type registers is record
f : fetch_reg_type;
d : decode_reg_type;
a : regacc_reg_type;
e : execute_reg_type;
m : memory_reg_type;
x : exception_reg_type;
w : write_reg_type;
end record;
type exception_type is record
pri : std_ulogic;
ill : std_ulogic;
fpdis : std_ulogic;
cpdis : std_ulogic;
wovf : std_ulogic;
wunf : std_ulogic;
ticc : std_ulogic;
end record;
type watchpoint_register is record
addr : std_logic_vector(31 downto 2); -- watchpoint address
mask : std_logic_vector(31 downto 2); -- watchpoint mask
exec : std_ulogic; -- trap on instruction
load : std_ulogic; -- trap on load
store : std_ulogic; -- trap on store
end record;
type watchpoint_registers is array (0 to 3) of watchpoint_register;
constant wpr_none : watchpoint_register := (
"000000000000000000000000000000", "000000000000000000000000000000", '0', '0', '0');
function dbgexc(r : registers; dbgi : l3_debug_in_type; trap : std_ulogic; tt : std_logic_vector(7 downto 0)) return std_ulogic is
variable dmode : std_ulogic;
begin
dmode := '0';
if (not r.x.ctrl.annul and trap) = '1' then
if (((tt = "00" & TT_WATCH) and (dbgi.bwatch = '1')) or
((dbgi.bsoft = '1') and (tt = "10000001")) or
(dbgi.btrapa = '1') or
((dbgi.btrape = '1') and not ((tt(5 downto 0) = TT_PRIV) or
(tt(5 downto 0) = TT_FPDIS) or (tt(5 downto 0) = TT_WINOF) or
(tt(5 downto 0) = TT_WINUF) or (tt(5 downto 4) = "01") or (tt(7) = '1'))) or
(((not r.w.s.et) and dbgi.berror) = '1')) then
dmode := '1';
end if;
end if;
return(dmode);
end;
function dbgerr(r : registers; dbgi : l3_debug_in_type;
tt : std_logic_vector(7 downto 0))
return std_ulogic is
variable err : std_ulogic;
begin
err := not r.w.s.et;
if (((dbgi.dbreak = '1') and (tt = ("00" & TT_WATCH))) or
((dbgi.bsoft = '1') and (tt = ("10000001")))) then
err := '0';
end if;
return(err);
end;
procedure diagwr(r : in registers;
dsur : in dsu_registers;
ir : in irestart_register;
dbg : in l3_debug_in_type;
wpr : in watchpoint_registers;
s : out special_register_type;
vwpr : out watchpoint_registers;
asi : out std_logic_vector(7 downto 0);
pc, npc : out pctype;
tbufcnt : out std_logic_vector(7-1 downto 0);
wr : out std_ulogic;
addr : out std_logic_vector(9 downto 0);
data : out word;
fpcwr : out std_ulogic) is
variable i : integer range 0 to 3;
begin
s := r.w.s; pc := r.f.pc; npc := ir.addr; wr := '0';
vwpr := wpr; asi := dsur.asi; addr := "0000000000";
data := dbg.ddata;
tbufcnt := dsur.tbufcnt; fpcwr := '0';
if (dbg.dsuen and dbg.denable and dbg.dwrite) = '1' then
case dbg.daddr(23 downto 20) is
when "0001" =>
if (dbg.daddr(16) = '1') and true then -- trace buffer control reg
tbufcnt := dbg.ddata(7-1 downto 0);
end if;
when "0011" => -- IU reg file
if dbg.daddr(12) = '0' then
wr := '1';
addr := "0000000000";
addr(8-1 downto 0) := dbg.daddr(8+1 downto 2);
else -- FPC
fpcwr := '1';
end if;
when "0100" => -- IU special registers
case dbg.daddr(7 downto 6) is
when "00" => -- IU regs Y - TBUF ctrl reg
case dbg.daddr(5 downto 2) is
when "0000" => -- Y
s.y := dbg.ddata;
when "0001" => -- PSR
s.cwp := dbg.ddata(3-1 downto 0);
s.icc := dbg.ddata(23 downto 20);
s.ec := dbg.ddata(13);
if FPEN then s.ef := dbg.ddata(12); end if;
s.pil := dbg.ddata(11 downto 8);
s.s := dbg.ddata(7);
s.ps := dbg.ddata(6);
s.et := dbg.ddata(5);
when "0010" => -- WIM
s.wim := dbg.ddata(8-1 downto 0);
when "0011" => -- TBR
s.tba := dbg.ddata(31 downto 12);
s.tt := dbg.ddata(11 downto 4);
when "0100" => -- PC
pc := dbg.ddata(31 downto 2);
when "0101" => -- NPC
npc := dbg.ddata(31 downto 2);
when "0110" => --FSR
fpcwr := '1';
when "0111" => --CFSR
when "1001" => -- ASI reg
asi := dbg.ddata(7 downto 0);
--when "1001" => -- TBUF ctrl reg
-- tbufcnt := dbg.ddata(7-1 downto 0);
when others =>
end case;
when "01" => -- ASR16 - ASR31
case dbg.daddr(5 downto 2) is
when "0001" => -- %ASR17
s.dwt := dbg.ddata(14);
s.svt := dbg.ddata(13);
when "0010" => -- %ASR18
if false then s.asr18 := dbg.ddata; end if;
when "1000" => -- %ASR24 - %ASR31
vwpr(0).addr := dbg.ddata(31 downto 2);
vwpr(0).exec := dbg.ddata(0);
when "1001" =>
vwpr(0).mask := dbg.ddata(31 downto 2);
vwpr(0).load := dbg.ddata(1);
vwpr(0).store := dbg.ddata(0);
when "1010" =>
vwpr(1).addr := dbg.ddata(31 downto 2);
vwpr(1).exec := dbg.ddata(0);
when "1011" =>
vwpr(1).mask := dbg.ddata(31 downto 2);
vwpr(1).load := dbg.ddata(1);
vwpr(1).store := dbg.ddata(0);
when "1100" =>
vwpr(2).addr := dbg.ddata(31 downto 2);
vwpr(2).exec := dbg.ddata(0);
when "1101" =>
vwpr(2).mask := dbg.ddata(31 downto 2);
vwpr(2).load := dbg.ddata(1);
vwpr(2).store := dbg.ddata(0);
when "1110" =>
vwpr(3).addr := dbg.ddata(31 downto 2);
vwpr(3).exec := dbg.ddata(0);
when "1111" => --
vwpr(3).mask := dbg.ddata(31 downto 2);
vwpr(3).load := dbg.ddata(1);
vwpr(3).store := dbg.ddata(0);
when others => --
end case;
-- disabled due to bug in XST
-- i := conv_integer(dbg.daddr(4 downto 3));
-- if dbg.daddr(2) = '0' then
-- vwpr(i).addr := dbg.ddata(31 downto 2);
-- vwpr(i).exec := dbg.ddata(0);
-- else
-- vwpr(i).mask := dbg.ddata(31 downto 2);
-- vwpr(i).load := dbg.ddata(1);
-- vwpr(i).store := dbg.ddata(0);
-- end if;
when others =>
end case;
when others =>
end case;
end if;
end;
function asr17_gen ( r : in registers) return word is
variable asr17 : word;
variable fpu2 : integer range 0 to 3;
begin
asr17 := "00000000000000000000000000000000";
asr17(31 downto 28) := conv_std_logic_vector(index, 4);
if (clk2x > 8) then
asr17(16 downto 15) := conv_std_logic_vector(clk2x-8, 2);
asr17(17) := '1';
elsif (clk2x > 0) then
asr17(16 downto 15) := conv_std_logic_vector(clk2x, 2);
end if;
asr17(14) := r.w.s.dwt;
if svt = 1 then asr17(13) := r.w.s.svt; end if;
if lddel = 2 then asr17(12) := '1'; end if;
if (fpu > 0) and (fpu < 8) then fpu2 := 1;
elsif (fpu >= 8) and (fpu < 15) then fpu2 := 3;
elsif fpu = 15 then fpu2 := 2;
else fpu2 := 0; end if;
asr17(11 downto 10) := conv_std_logic_vector(fpu2, 2);
if mac = 1 then asr17(9) := '1'; end if;
if 2 /= 0 then asr17(8) := '1'; end if;
asr17(7 downto 5) := conv_std_logic_vector(nwp, 3);
asr17(4 downto 0) := conv_std_logic_vector(8-1, 5);
return(asr17);
end;
procedure diagread(dbgi : in l3_debug_in_type;
r : in registers;
dsur : in dsu_registers;
ir : in irestart_register;
wpr : in watchpoint_registers;
dco : in dcache_out_type;
tbufo : in tracebuf_out_type;
data : out word) is
variable cwp : std_logic_vector(4 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable i : integer range 0 to 3;
begin
data := "00000000000000000000000000000000"; cwp := "00000";
cwp(3-1 downto 0) := r.w.s.cwp;
case dbgi.daddr(22 downto 20) is
when "001" => -- trace buffer
if true then
if dbgi.daddr(16) = '1' then -- trace buffer control reg
if true then data(7-1 downto 0) := dsur.tbufcnt; end if;
else
case dbgi.daddr(3 downto 2) is
when "00" => data := tbufo.data(127 downto 96);
when "01" => data := tbufo.data(95 downto 64);
when "10" => data := tbufo.data(63 downto 32);
when others => data := tbufo.data(31 downto 0);
end case;
end if;
end if;
when "011" => -- IU reg file
if dbgi.daddr(12) = '0' then
data := rfo.data1(31 downto 0);
if (dbgi.daddr(11) = '1') and (is_fpga(fabtech) = 0) then
data := rfo.data2(31 downto 0);
end if;
else data := fpo.dbg.data; end if;
when "100" => -- IU regs
case dbgi.daddr(7 downto 6) is
when "00" => -- IU regs Y - TBUF ctrl reg
case dbgi.daddr(5 downto 2) is
when "0000" =>
data := r.w.s.y;
when "0001" =>
data := conv_std_logic_vector(15, 4) & conv_std_logic_vector(3, 4) &
r.w.s.icc & "000000" & r.w.s.ec & r.w.s.ef & r.w.s.pil &
r.w.s.s & r.w.s.ps & r.w.s.et & cwp;
when "0010" =>
data(8-1 downto 0) := r.w.s.wim;
when "0011" =>
data := r.w.s.tba & r.w.s.tt & "0000";
when "0100" =>
data(31 downto 2) := r.f.pc;
when "0101" =>
data(31 downto 2) := ir.addr;
when "0110" => -- FSR
data := fpo.dbg.data;
when "0111" => -- CPSR
when "1000" => -- TT reg
data(12 downto 4) := dsur.err & dsur.tt;
when "1001" => -- ASI reg
data(7 downto 0) := dsur.asi;
when others =>
end case;
when "01" =>
if dbgi.daddr(5) = '0' then -- %ASR17
if dbgi.daddr(4 downto 2) = "001" then -- %ASR17
data := asr17_gen(r);
elsif false and dbgi.daddr(4 downto 2) = "010" then -- %ASR18
data := r.w.s.asr18;
end if;
else -- %ASR24 - %ASR31
i := conv_integer(dbgi.daddr(4 downto 3)); --
if dbgi.daddr(2) = '0' then
data(31 downto 2) := wpr(i).addr;
data(0) := wpr(i).exec;
else
data(31 downto 2) := wpr(i).mask;
data(1) := wpr(i).load;
data(0) := wpr(i).store;
end if;
end if;
when others =>
end case;
when "111" =>
data := r.x.data(conv_integer(r.x.set));
when others =>
end case;
end;
procedure itrace(r : in registers;
dsur : in dsu_registers;
vdsu : in dsu_registers;
res : in word;
exc : in std_ulogic;
dbgi : in l3_debug_in_type;
error : in std_ulogic;
trap : in std_ulogic;
tbufcnt : out std_logic_vector(7-1 downto 0);
di : out tracebuf_in_type) is
variable meminst : std_ulogic;
begin
di.addr := (others => '0'); di.data := (others => '0');
di.enable := '0'; di.write := (others => '0');
tbufcnt := vdsu.tbufcnt;
meminst := r.x.ctrl.inst(31) and r.x.ctrl.inst(30);
if true then
di.addr(7-1 downto 0) := dsur.tbufcnt;
di.data(127) := '0';
di.data(126) := not r.x.ctrl.pv;
di.data(125 downto 96) := dbgi.timer(29 downto 0);
di.data(95 downto 64) := res;
di.data(63 downto 34) := r.x.ctrl.pc(31 downto 2);
di.data(33) := trap;
di.data(32) := error;
di.data(31 downto 0) := r.x.ctrl.inst;
if (dbgi.tenable = '0') or (r.x.rstate = dsu2) then
if ((dbgi.dsuen and dbgi.denable) = '1') and (dbgi.daddr(23 downto 20) & dbgi.daddr(16) = "00010") then
di.enable := '1';
di.addr(7-1 downto 0) := dbgi.daddr(7-1+4 downto 4);
if dbgi.dwrite = '1' then
case dbgi.daddr(3 downto 2) is
when "00" => di.write(3) := '1';
when "01" => di.write(2) := '1';
when "10" => di.write(1) := '1';
when others => di.write(0) := '1';
end case;
di.data := dbgi.ddata & dbgi.ddata & dbgi.ddata & dbgi.ddata;
end if;
end if;
elsif (not r.x.ctrl.annul and (r.x.ctrl.pv or meminst) and not r.x.debug) = '1' then
di.enable := '1'; di.write := (others => '1');
tbufcnt := dsur.tbufcnt + 1;
end if;
di.diag := dco.testen & "000";
if dco.scanen = '1' then di.enable := '0'; end if;
end if;
end;
procedure dbg_cache(holdn : in std_ulogic;
dbgi : in l3_debug_in_type;
r : in registers;
dsur : in dsu_registers;
mresult : in word;
dci : in dc_in_type;
mresult2 : out word;
dci2 : out dc_in_type
) is
begin
mresult2 := mresult; dci2 := dci; dci2.dsuen := '0';
if true then
if r.x.rstate = dsu2 then
dci2.asi := dsur.asi;
if (dbgi.daddr(22 downto 20) = "111") and (dbgi.dsuen = '1') then
dci2.dsuen := (dbgi.denable or r.m.dci.dsuen) and not dsur.crdy(2);
dci2.enaddr := dbgi.denable;
dci2.size := "10"; dci2.read := '1'; dci2.write := '0';
if (dbgi.denable and not r.m.dci.enaddr) = '1' then
mresult2 := (others => '0'); mresult2(19 downto 2) := dbgi.daddr(19 downto 2);
else
mresult2 := dbgi.ddata;
end if;
if dbgi.dwrite = '1' then
dci2.read := '0'; dci2.write := '1';
end if;
end if;
end if;
end if;
end;
procedure fpexack(r : in registers; fpexc : out std_ulogic) is
begin
fpexc := '0';
if FPEN then
if r.x.ctrl.tt = TT_FPEXC then fpexc := '1'; end if;
end if;
end;
procedure diagrdy(denable : in std_ulogic;
dsur : in dsu_registers;
dci : in dc_in_type;
mds : in std_ulogic;
ico : in icache_out_type;
crdy : out std_logic_vector(2 downto 1)) is
begin
crdy := dsur.crdy(1) & '0';
if dci.dsuen = '1' then
case dsur.asi(4 downto 0) is
when ASI_ITAG | ASI_IDATA | ASI_UINST | ASI_SINST =>
crdy(2) := ico.diagrdy and not dsur.crdy(2);
when ASI_DTAG | ASI_MMUSNOOP_DTAG | ASI_DDATA | ASI_UDATA | ASI_SDATA =>
crdy(1) := not denable and dci.enaddr and not dsur.crdy(1);
when others =>
crdy(2) := dci.enaddr and denable;
end case;
end if;
end;
signal r, rin : registers;
signal wpr, wprin : watchpoint_registers;
signal dsur, dsuin : dsu_registers;
signal ir, irin : irestart_register;
signal rp, rpin : pwd_register_type;
-- execute stage operations
constant EXE_AND : std_logic_vector(2 downto 0) := "000";
constant EXE_XOR : std_logic_vector(2 downto 0) := "001"; -- must be equal to EXE_PASS2
constant EXE_OR : std_logic_vector(2 downto 0) := "010";
constant EXE_XNOR : std_logic_vector(2 downto 0) := "011";
constant EXE_ANDN : std_logic_vector(2 downto 0) := "100";
constant EXE_ORN : std_logic_vector(2 downto 0) := "101";
constant EXE_DIV : std_logic_vector(2 downto 0) := "110";
constant EXE_PASS1 : std_logic_vector(2 downto 0) := "000";
constant EXE_PASS2 : std_logic_vector(2 downto 0) := "001";
constant EXE_STB : std_logic_vector(2 downto 0) := "010";
constant EXE_STH : std_logic_vector(2 downto 0) := "011";
constant EXE_ONES : std_logic_vector(2 downto 0) := "100";
constant EXE_RDY : std_logic_vector(2 downto 0) := "101";
constant EXE_SPR : std_logic_vector(2 downto 0) := "110";
constant EXE_LINK : std_logic_vector(2 downto 0) := "111";
constant EXE_SLL : std_logic_vector(2 downto 0) := "001";
constant EXE_SRL : std_logic_vector(2 downto 0) := "010";
constant EXE_SRA : std_logic_vector(2 downto 0) := "100";
constant EXE_NOP : std_logic_vector(2 downto 0) := "000";
-- EXE result select
constant EXE_RES_ADD : std_logic_vector(1 downto 0) := "00";
constant EXE_RES_SHIFT : std_logic_vector(1 downto 0) := "01";
constant EXE_RES_LOGIC : std_logic_vector(1 downto 0) := "10";
constant EXE_RES_MISC : std_logic_vector(1 downto 0) := "11";
-- Load types
constant SZBYTE : std_logic_vector(1 downto 0) := "00";
constant SZHALF : std_logic_vector(1 downto 0) := "01";
constant SZWORD : std_logic_vector(1 downto 0) := "10";
constant SZDBL : std_logic_vector(1 downto 0) := "11";
-- calculate register file address
procedure regaddr(cwp : std_logic_vector; reg : std_logic_vector(4 downto 0);
rao : out rfatype) is
variable ra : rfatype;
constant globals : std_logic_vector(8-5 downto 0) :=
conv_std_logic_vector(8, 8-4);
begin
ra := (others => '0'); ra(4 downto 0) := reg;
if reg(4 downto 3) = "00" then ra(8 -1 downto 4) := globals;
else
ra(3+3 downto 4) := cwp + ra(4);
if ra(8-1 downto 4) = globals then
ra(8-1 downto 4) := (others => '0');
end if;
end if;
rao := ra;
end;
-- branch adder
function branch_address(inst : word; pc : pctype) return std_logic_vector is
variable baddr, caddr, tmp : pctype;
begin
caddr := (others => '0'); caddr(31 downto 2) := inst(29 downto 0);
caddr(31 downto 2) := caddr(31 downto 2) + pc(31 downto 2);
baddr := (others => '0'); baddr(31 downto 24) := (others => inst(21));
baddr(23 downto 2) := inst(21 downto 0);
baddr(31 downto 2) := baddr(31 downto 2) + pc(31 downto 2);
if inst(30) = '1' then tmp := caddr; else tmp := baddr; end if;
return(tmp);
end;
-- evaluate branch condition
function branch_true(icc : std_logic_vector(3 downto 0); inst : word)
return std_ulogic is
variable n, z, v, c, branch : std_ulogic;
begin
n := icc(3); z := icc(2); v := icc(1); c := icc(0);
case inst(27 downto 25) is
when "000" => branch := inst(28) xor '0'; -- bn, ba
when "001" => branch := inst(28) xor z; -- be, bne
when "010" => branch := inst(28) xor (z or (n xor v)); -- ble, bg
when "011" => branch := inst(28) xor (n xor v); -- bl, bge
when "100" => branch := inst(28) xor (c or z); -- bleu, bgu
when "101" => branch := inst(28) xor c; -- bcs, bcc
when "110" => branch := inst(28) xor n; -- bneg, bpos
when others => branch := inst(28) xor v; -- bvs, bvc
end case;
return(branch);
end;
-- detect RETT instruction in the pipeline and set the local psr.su and psr.et
procedure su_et_select(r : in registers; xc_ps, xc_s, xc_et : in std_ulogic;
su, et : out std_ulogic) is
begin
if ((r.a.ctrl.rett or r.e.ctrl.rett or r.m.ctrl.rett or r.x.ctrl.rett) = '1')
and (r.x.annul_all = '0')
then su := xc_ps; et := '1';
else su := xc_s; et := xc_et; end if;
end;
-- detect watchpoint trap
function wphit(r : registers; wpr : watchpoint_registers; debug : l3_debug_in_type)
return std_ulogic is
variable exc : std_ulogic;
begin
exc := '0';
for i in 1 to NWP loop
if ((wpr(i-1).exec and r.a.ctrl.pv and not r.a.ctrl.annul) = '1') then
if (((wpr(i-1).addr xor r.a.ctrl.pc(31 downto 2)) and wpr(i-1).mask) = "000000000000000000000000000000") then
exc := '1';
end if;
end if;
end loop;
if true then
if (debug.dsuen and not r.a.ctrl.annul) = '1' then
exc := exc or (r.a.ctrl.pv and ((debug.dbreak and debug.bwatch) or r.a.step));
end if;
end if;
return(exc);
end;
-- 32-bit shifter
function shift3(r : registers; aluin1, aluin2 : word) return word is
variable shiftin : unsigned(63 downto 0);
variable shiftout : unsigned(63 downto 0);
variable cnt : natural range 0 to 31;
begin
cnt := conv_integer(r.e.shcnt);
if r.e.shleft = '1' then
shiftin(30 downto 0) := (others => '0');
shiftin(63 downto 31) := '0' & unsigned(aluin1);
else
shiftin(63 downto 32) := (others => r.e.sari);
shiftin(31 downto 0) := unsigned(aluin1);
end if;
shiftout := SHIFT_RIGHT(shiftin, cnt);
return(std_logic_vector(shiftout(31 downto 0)));
end;
function shift2(r : registers; aluin1, aluin2 : word) return word is
variable ushiftin : unsigned(31 downto 0);
variable sshiftin : signed(32 downto 0);
variable cnt : natural range 0 to 31;
variable resleft, resright : word;
begin
cnt := conv_integer(r.e.shcnt);
ushiftin := unsigned(aluin1);
sshiftin := signed('0' & aluin1);
if r.e.shleft = '1' then
resleft := std_logic_vector(SHIFT_LEFT(ushiftin, cnt));
return(resleft);
else
if r.e.sari = '1' then sshiftin(32) := aluin1(31); end if;
sshiftin := SHIFT_RIGHT(sshiftin, cnt);
resright := std_logic_vector(sshiftin(31 downto 0));
return(resright);
-- else
-- ushiftin := SHIFT_RIGHT(ushiftin, cnt);
-- return(std_logic_vector(ushiftin));
-- end if;
end if;
end;
function shift(r : registers; aluin1, aluin2 : word;
shiftcnt : std_logic_vector(4 downto 0); sari : std_ulogic ) return word is
variable shiftin : std_logic_vector(63 downto 0);
begin
shiftin := "00000000000000000000000000000000" & aluin1;
if r.e.shleft = '1' then
shiftin(31 downto 0) := "00000000000000000000000000000000"; shiftin(63 downto 31) := '0' & aluin1;
else shiftin(63 downto 32) := (others => sari); end if;
if shiftcnt (4) = '1' then shiftin(47 downto 0) := shiftin(63 downto 16); end if;
if shiftcnt (3) = '1' then shiftin(39 downto 0) := shiftin(47 downto 8); end if;
if shiftcnt (2) = '1' then shiftin(35 downto 0) := shiftin(39 downto 4); end if;
if shiftcnt (1) = '1' then shiftin(33 downto 0) := shiftin(35 downto 2); end if;
if shiftcnt (0) = '1' then shiftin(31 downto 0) := shiftin(32 downto 1); end if;
return(shiftin(31 downto 0));
end;
-- Check for illegal and privileged instructions
procedure exception_detect(r : registers; wpr : watchpoint_registers; dbgi : l3_debug_in_type;
trapin : in std_ulogic; ttin : in std_logic_vector(5 downto 0);
trap : out std_ulogic; tt : out std_logic_vector(5 downto 0)) is
variable illegal_inst, privileged_inst : std_ulogic;
variable cp_disabled, fp_disabled, fpop : std_ulogic;
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable inst : word;
variable wph : std_ulogic;
begin
inst := r.a.ctrl.inst; trap := trapin; tt := ttin;
if r.a.ctrl.annul = '0' then
op := inst(31 downto 30); op2 := inst(24 downto 22);
op3 := inst(24 downto 19); rd := inst(29 downto 25);
illegal_inst := '0'; privileged_inst := '0'; cp_disabled := '0';
fp_disabled := '0'; fpop := '0';
case op is
when CALL => null;
when FMT2 =>
case op2 is
when SETHI | BICC => null;
when FBFCC =>
if FPEN then fp_disabled := not r.w.s.ef; else fp_disabled := '1'; end if;
when CBCCC =>
if (not false) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when others => illegal_inst := '1';
end case;
when FMT3 =>
case op3 is
when IAND | ANDCC | ANDN | ANDNCC | IOR | ORCC | ORN | ORNCC | IXOR |
XORCC | IXNOR | XNORCC | ISLL | ISRL | ISRA | MULSCC | IADD | ADDX |
ADDCC | ADDXCC | ISUB | SUBX | SUBCC | SUBXCC | FLUSH | JMPL | TICC |
SAVE | RESTORE | RDY => null;
when TADDCC | TADDCCTV | TSUBCC | TSUBCCTV =>
if notag = 1 then illegal_inst := '1'; end if;
when UMAC | SMAC =>
if not false then illegal_inst := '1'; end if;
when UMUL | SMUL | UMULCC | SMULCC =>
if not true then illegal_inst := '1'; end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if not true then illegal_inst := '1'; end if;
when RETT => illegal_inst := r.a.et; privileged_inst := not r.a.su;
when RDPSR | RDTBR | RDWIM => privileged_inst := not r.a.su;
when WRY => null;
when WRPSR =>
privileged_inst := not r.a.su;
when WRWIM | WRTBR => privileged_inst := not r.a.su;
when FPOP1 | FPOP2 =>
if FPEN then fp_disabled := not r.w.s.ef; fpop := '1';
else fp_disabled := '1'; fpop := '0'; end if;
when CPOP1 | CPOP2 =>
if (not false) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when others => illegal_inst := '1';
end case;
when others => -- LDST
case op3 is
when LDD | ISTD => illegal_inst := rd(0); -- trap if odd destination register
when LD | LDUB | LDSTUB | LDUH | LDSB | LDSH | ST | STB | STH | SWAP =>
null;
when LDDA | STDA =>
illegal_inst := inst(13) or rd(0); privileged_inst := not r.a.su;
when LDA | LDUBA| LDSTUBA | LDUHA | LDSBA | LDSHA | STA | STBA | STHA |
SWAPA =>
illegal_inst := inst(13); privileged_inst := not r.a.su;
when LDDF | STDF | LDF | LDFSR | STF | STFSR =>
if FPEN then fp_disabled := not r.w.s.ef;
else fp_disabled := '1'; end if;
when STDFQ =>
privileged_inst := not r.a.su;
if (not FPEN) or (r.w.s.ef = '0') then fp_disabled := '1'; end if;
when STDCQ =>
privileged_inst := not r.a.su;
if (not false) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when LDC | LDCSR | LDDC | STC | STCSR | STDC =>
if (not false) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when others => illegal_inst := '1';
end case;
end case;
wph := wphit(r, wpr, dbgi);
trap := '1';
if r.a.ctrl.trap = '1' then tt := TT_IAEX;
elsif privileged_inst = '1' then tt := TT_PRIV;
elsif illegal_inst = '1' then tt := TT_IINST;
elsif fp_disabled = '1' then tt := TT_FPDIS;
elsif cp_disabled = '1' then tt := TT_CPDIS;
elsif wph = '1' then tt := TT_WATCH;
elsif r.a.wovf= '1' then tt := TT_WINOF;
elsif r.a.wunf= '1' then tt := TT_WINUF;
elsif r.a.ticc= '1' then tt := TT_TICC;
else trap := '0'; tt:= (others => '0'); end if;
end if;
end;
-- instructions that write the condition codes (psr.icc)
procedure wicc_y_gen(inst : word; wicc, wy : out std_ulogic) is
begin
wicc := '0'; wy := '0';
if inst(31 downto 30) = FMT3 then
case inst(24 downto 19) is
when SUBCC | TSUBCC | TSUBCCTV | ADDCC | ANDCC | ORCC | XORCC | ANDNCC |
ORNCC | XNORCC | TADDCC | TADDCCTV | ADDXCC | SUBXCC | WRPSR =>
wicc := '1';
when WRY =>
if r.d.inst(conv_integer(r.d.set))(29 downto 25) = "00000" then wy := '1'; end if;
when MULSCC =>
wicc := '1'; wy := '1';
when UMAC | SMAC =>
if false then wy := '1'; end if;
when UMULCC | SMULCC =>
if true and (((mulo.nready = '1') and (r.d.cnt /= "00")) or (0 /= 0)) then
wicc := '1'; wy := '1';
end if;
when UMUL | SMUL =>
if true and (((mulo.nready = '1') and (r.d.cnt /= "00")) or (0 /= 0)) then
wy := '1';
end if;
when UDIVCC | SDIVCC =>
if true and (divo.nready = '1') and (r.d.cnt /= "00") then
wicc := '1';
end if;
when others =>
end case;
end if;
end;
-- select cwp
procedure cwp_gen(r, v : registers; annul, wcwp : std_ulogic; ncwp : cwptype;
cwp : out cwptype) is
begin
if (r.x.rstate = trap) or (r.x.rstate = dsu2) or (rstn = '0') then cwp := v.w.s.cwp;
elsif (wcwp = '1') and (annul = '0') then cwp := ncwp;
elsif r.m.wcwp = '1' then cwp := r.m.result(3-1 downto 0);
else cwp := r.d.cwp; end if;
end;
-- generate wcwp in ex stage
procedure cwp_ex(r : in registers; wcwp : out std_ulogic) is
begin
if (r.e.ctrl.inst(31 downto 30) = FMT3) and
(r.e.ctrl.inst(24 downto 19) = WRPSR)
then wcwp := not r.e.ctrl.annul; else wcwp := '0'; end if;
end;
-- generate next cwp & window under- and overflow traps
procedure cwp_ctrl(r : in registers; xc_wim : in std_logic_vector(8-1 downto 0);
inst : word; de_cwp : out cwptype; wovf_exc, wunf_exc, wcwp : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable wim : word;
variable ncwp : cwptype;
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
wovf_exc := '0'; wunf_exc := '0'; wim := (others => '0');
wim(8-1 downto 0) := xc_wim; ncwp := r.d.cwp; wcwp := '0';
if (op = FMT3) and ((op3 = RETT) or (op3 = RESTORE) or (op3 = SAVE)) then
wcwp := '1';
if (op3 = SAVE) then
if (not true) and (r.d.cwp = "000") then ncwp := "111";
else ncwp := r.d.cwp - 1 ; end if;
else
if (not true) and (r.d.cwp = "111") then ncwp := "000";
else ncwp := r.d.cwp + 1; end if;
end if;
if wim(conv_integer(ncwp)) = '1' then
if op3 = SAVE then wovf_exc := '1'; else wunf_exc := '1'; end if;
end if;
end if;
de_cwp := ncwp;
end;
-- generate register read address 1
procedure rs1_gen(r : registers; inst : word; rs1 : out std_logic_vector(4 downto 0);
rs1mod : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
rs1 := inst(18 downto 14); rs1mod := '0';
if (op = LDST) then
if ((r.d.cnt = "01") and ((op3(2) and not op3(3)) = '1')) or
(r.d.cnt = "10")
then rs1mod := '1'; rs1 := inst(29 downto 25); end if;
if ((r.d.cnt = "10") and (op3(3 downto 0) = "0111")) then
rs1(0) := '1';
end if;
end if;
end;
-- load/icc interlock detection
procedure lock_gen(r : registers; rs2, rd : std_logic_vector(4 downto 0);
rfa1, rfa2, rfrd : rfatype; inst : word; fpc_lock, mulinsn, divinsn : std_ulogic;
lldcheck1, lldcheck2, lldlock, lldchkra, lldchkex : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable cond : std_logic_vector(3 downto 0);
variable rs1 : std_logic_vector(4 downto 0);
variable i, ldcheck1, ldcheck2, ldchkra, ldchkex, ldcheck3 : std_ulogic;
variable ldlock, icc_check, bicc_hold, chkmul, y_check : std_ulogic;
variable lddlock : boolean;
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
op2 := inst(24 downto 22); cond := inst(28 downto 25);
rs1 := inst(18 downto 14); lddlock := false; i := inst(13);
ldcheck1 := '0'; ldcheck2 := '0'; ldcheck3 := '0'; ldlock := '0';
ldchkra := '1'; ldchkex := '1'; icc_check := '0'; bicc_hold := '0';
y_check := '0';
if (r.d.annul = '0') then
case op is
when FMT2 =>
if (op2 = BICC) and (cond(2 downto 0) /= "000") then
icc_check := '1';
end if;
when FMT3 =>
ldcheck1 := '1'; ldcheck2 := not i;
case op3 is
when TICC =>
if (cond(2 downto 0) /= "000") then icc_check := '1'; end if;
when RDY =>
ldcheck1 := '0'; ldcheck2 := '0';
if false then y_check := '1'; end if;
when RDWIM | RDTBR =>
ldcheck1 := '0'; ldcheck2 := '0';
when RDPSR =>
ldcheck1 := '0'; ldcheck2 := '0'; icc_check := '1';
if true then icc_check := '1'; end if;
-- when ADDX | ADDXCC | SUBX | SUBXCC =>
-- if true then icc_check := '1'; end if;
when SDIV | SDIVCC | UDIV | UDIVCC =>
if true then y_check := '1'; end if;
when FPOP1 | FPOP2 => ldcheck1:= '0'; ldcheck2 := '0';
when others =>
end case;
when LDST =>
ldcheck1 := '1'; ldchkra := '0';
case r.d.cnt is
when "00" =>
if (lddel = 2) and (op3(2) = '1') then ldcheck3 := '1'; end if;
ldcheck2 := not i; ldchkra := '1';
when "01" => ldcheck2 := not i;
when others => ldchkex := '0';
end case;
if (op3(2 downto 0) = "011") then lddlock := true; end if;
when others => null;
end case;
end if;
if true or true then
chkmul := mulinsn;
bicc_hold := bicc_hold or (icc_check and r.m.ctrl.wicc and (r.m.ctrl.cnt(0) or r.m.mul));
else chkmul := '0'; end if;
if true then
bicc_hold := bicc_hold or (y_check and (r.a.ctrl.wy or r.e.ctrl.wy));
chkmul := chkmul or divinsn;
end if;
bicc_hold := bicc_hold or (icc_check and (r.a.ctrl.wicc or r.e.ctrl.wicc));
if (((r.a.ctrl.ld or chkmul) and r.a.ctrl.wreg and ldchkra) = '1') and
(((ldcheck1 = '1') and (r.a.ctrl.rd = rfa1)) or
((ldcheck2 = '1') and (r.a.ctrl.rd = rfa2)) or
((ldcheck3 = '1') and (r.a.ctrl.rd = rfrd)))
then ldlock := '1'; end if;
if (((r.e.ctrl.ld or r.e.mac) and r.e.ctrl.wreg and ldchkex) = '1') and
((lddel = 2) or (false and (r.e.mac = '1')) or ((0 = 3) and (r.e.mul = '1'))) and
(((ldcheck1 = '1') and (r.e.ctrl.rd = rfa1)) or
((ldcheck2 = '1') and (r.e.ctrl.rd = rfa2)))
then ldlock := '1'; end if;
ldlock := ldlock or bicc_hold or fpc_lock;
lldcheck1 := ldcheck1; lldcheck2:= ldcheck2; lldlock := ldlock;
lldchkra := ldchkra; lldchkex := ldchkex;
end;
procedure fpbranch(inst : in word; fcc : in std_logic_vector(1 downto 0);
branch : out std_ulogic) is
variable cond : std_logic_vector(3 downto 0);
variable fbres : std_ulogic;
begin
cond := inst(28 downto 25);
case cond(2 downto 0) is
when "000" => fbres := '0'; -- fba, fbn
when "001" => fbres := fcc(1) or fcc(0);
when "010" => fbres := fcc(1) xor fcc(0);
when "011" => fbres := fcc(0);
when "100" => fbres := (not fcc(1)) and fcc(0);
when "101" => fbres := fcc(1);
when "110" => fbres := fcc(1) and not fcc(0);
when others => fbres := fcc(1) and fcc(0);
end case;
branch := cond(3) xor fbres;
end;
-- PC generation
procedure ic_ctrl(r : registers; inst : word; annul_all, ldlock, branch_true,
fbranch_true, cbranch_true, fccv, cccv : in std_ulogic;
cnt : out std_logic_vector(1 downto 0);
de_pc : out pctype; de_branch, ctrl_annul, de_annul, jmpl_inst, inull,
de_pv, ctrl_pv, de_hold_pc, ticc_exception, rett_inst, mulstart,
divstart : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable cond : std_logic_vector(3 downto 0);
variable hold_pc, annul_current, annul_next, branch, annul, pv : std_ulogic;
variable de_jmpl : std_ulogic;
begin
branch := '0'; annul_next := '0'; annul_current := '0'; pv := '1';
hold_pc := '0'; ticc_exception := '0'; rett_inst := '0';
op := inst(31 downto 30); op3 := inst(24 downto 19);
op2 := inst(24 downto 22); cond := inst(28 downto 25);
annul := inst(29); de_jmpl := '0'; cnt := "00";
mulstart := '0'; divstart := '0';
if r.d.annul = '0' then
case inst(31 downto 30) is
when CALL =>
branch := '1';
if r.d.inull = '1' then
hold_pc := '1'; annul_current := '1';
end if;
when FMT2 =>
if (op2 = BICC) or (FPEN and (op2 = FBFCC)) or (false and (op2 = CBCCC)) then
if (FPEN and (op2 = FBFCC)) then
branch := fbranch_true;
if fccv /= '1' then hold_pc := '1'; annul_current := '1'; end if;
elsif (false and (op2 = CBCCC)) then
branch := cbranch_true;
if cccv /= '1' then hold_pc := '1'; annul_current := '1'; end if;
else branch := branch_true; end if;
if hold_pc = '0' then
if (branch = '1') then
if (cond = BA) and (annul = '1') then annul_next := '1'; end if;
else annul_next := annul; end if;
if r.d.inull = '1' then -- contention with JMPL
hold_pc := '1'; annul_current := '1'; annul_next := '0';
end if;
end if;
end if;
when FMT3 =>
case op3 is
when UMUL | SMUL | UMULCC | SMULCC =>
if true and (0 /= 0) then mulstart := '1'; end if;
if true and (0 = 0) then
case r.d.cnt is
when "00" =>
cnt := "01"; hold_pc := '1'; pv := '0'; mulstart := '1';
when "01" =>
if mulo.nready = '1' then cnt := "00";
else cnt := "01"; pv := '0'; hold_pc := '1'; end if;
when others => null;
end case;
end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if true then
case r.d.cnt is
when "00" =>
cnt := "01"; hold_pc := '1'; pv := '0';
divstart := '1';
when "01" =>
if divo.nready = '1' then cnt := "00";
else cnt := "01"; pv := '0'; hold_pc := '1'; end if;
when others => null;
end case;
end if;
when TICC =>
if branch_true = '1' then ticc_exception := '1'; end if;
when RETT =>
rett_inst := '1'; --su := sregs.ps;
when JMPL =>
de_jmpl := '1';
when WRY =>
if false then
if inst(29 downto 25) = "10011" then -- %ASR19
case r.d.cnt is
when "00" =>
pv := '0'; cnt := "00"; hold_pc := '1';
if r.x.ipend = '1' then cnt := "01"; end if;
when "01" =>
cnt := "00";
when others =>
end case;
end if;
end if;
when others => null;
end case;
when others => -- LDST
case r.d.cnt is
when "00" =>
if (op3(2) = '1') or (op3(1 downto 0) = "11") then -- ST/LDST/SWAP/LDD
cnt := "01"; hold_pc := '1'; pv := '0';
end if;
when "01" =>
if (op3(2 downto 0) = "111") or (op3(3 downto 0) = "1101") or
((false or FPEN) and ((op3(5) & op3(2 downto 0)) = "1110"))
then -- LDD/STD/LDSTUB/SWAP
cnt := "10"; pv := '0'; hold_pc := '1';
else
cnt := "00";
end if;
when "10" =>
cnt := "00";
when others => null;
end case;
end case;
end if;
if ldlock = '1' then
cnt := r.d.cnt; annul_next := '0'; pv := '1';
end if;
hold_pc := (hold_pc or ldlock) and not annul_all;
if hold_pc = '1' then de_pc := r.d.pc; else de_pc := r.f.pc; end if;
annul_current := (annul_current or ldlock or annul_all);
ctrl_annul := r.d.annul or annul_all or annul_current;
pv := pv and not ((r.d.inull and not hold_pc) or annul_all);
jmpl_inst := de_jmpl and not annul_current;
annul_next := (r.d.inull and not hold_pc) or annul_next or annul_all;
if (annul_next = '1') or (rstn = '0') then
cnt := (others => '0');
end if;
de_hold_pc := hold_pc; de_branch := branch; de_annul := annul_next;
de_pv := pv; ctrl_pv := r.d.pv and
not ((r.d.annul and not r.d.pv) or annul_all or annul_current);
inull := (not rstn) or r.d.inull or hold_pc or annul_all;
end;
-- register write address generation
procedure rd_gen(r : registers; inst : word; wreg, ld : out std_ulogic;
rdo : out std_logic_vector(4 downto 0)) is
variable write_reg : std_ulogic;
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
begin
op := inst(31 downto 30);
op2 := inst(24 downto 22);
op3 := inst(24 downto 19);
write_reg := '0'; rd := inst(29 downto 25); ld := '0';
case op is
when CALL =>
write_reg := '1'; rd := "01111"; -- CALL saves PC in r[15] (%o7)
when FMT2 =>
if (op2 = SETHI) then write_reg := '1'; end if;
when FMT3 =>
case op3 is
when UMUL | SMUL | UMULCC | SMULCC =>
if true then
if (((mulo.nready = '1') and (r.d.cnt /= "00")) or (0 /= 0)) then
write_reg := '1';
end if;
else write_reg := '1'; end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if true then
if (divo.nready = '1') and (r.d.cnt /= "00") then
write_reg := '1';
end if;
else write_reg := '1'; end if;
when RETT | WRPSR | WRY | WRWIM | WRTBR | TICC | FLUSH => null;
when FPOP1 | FPOP2 => null;
when CPOP1 | CPOP2 => null;
when others => write_reg := '1';
end case;
when others => -- LDST
ld := not op3(2);
if (op3(2) = '0') and not ((false or FPEN) and (op3(5) = '1'))
then write_reg := '1'; end if;
case op3 is
when SWAP | SWAPA | LDSTUB | LDSTUBA =>
if r.d.cnt = "00" then write_reg := '1'; ld := '1'; end if;
when others => null;
end case;
if r.d.cnt = "01" then
case op3 is
when LDD | LDDA | LDDC | LDDF => rd(0) := '1';
when others =>
end case;
end if;
end case;
if (rd = "00000") then write_reg := '0'; end if;
wreg := write_reg; rdo := rd;
end;
-- immediate data generation
function imm_data (r : registers; insn : word)
return word is
variable immediate_data, inst : word;
begin
immediate_data := (others => '0'); inst := insn;
case inst(31 downto 30) is
when FMT2 =>
immediate_data := inst(21 downto 0) & "0000000000";
when others => -- LDST
immediate_data(31 downto 13) := (others => inst(12));
immediate_data(12 downto 0) := inst(12 downto 0);
end case;
return(immediate_data);
end;
-- read special registers
function get_spr (r : registers) return word is
variable spr : word;
begin
spr := (others => '0');
case r.e.ctrl.inst(24 downto 19) is
when RDPSR => spr(31 downto 5) := conv_std_logic_vector(15,4) &
conv_std_logic_vector(3,4) & r.m.icc & "000000" & r.w.s.ec & r.w.s.ef &
r.w.s.pil & r.e.su & r.w.s.ps & r.e.et;
spr(3-1 downto 0) := r.e.cwp;
when RDTBR => spr(31 downto 4) := r.w.s.tba & r.w.s.tt;
when RDWIM => spr(8-1 downto 0) := r.w.s.wim;
when others =>
end case;
return(spr);
end;
-- immediate data select
function imm_select(inst : word) return boolean is
variable imm : boolean;
begin
imm := false;
case inst(31 downto 30) is
when FMT2 =>
case inst(24 downto 22) is
when SETHI => imm := true;
when others =>
end case;
when FMT3 =>
case inst(24 downto 19) is
when RDWIM | RDPSR | RDTBR => imm := true;
when others => if (inst(13) = '1') then imm := true; end if;
end case;
when LDST =>
if (inst(13) = '1') then imm := true; end if;
when others =>
end case;
return(imm);
end;
-- EXE operation
procedure alu_op(r : in registers; iop1, iop2 : in word; me_icc : std_logic_vector(3 downto 0);
my, ldbp : std_ulogic; aop1, aop2 : out word; aluop : out std_logic_vector(2 downto 0);
alusel : out std_logic_vector(1 downto 0); aluadd : out std_ulogic;
shcnt : out std_logic_vector(4 downto 0); sari, shleft, ymsb,
mulins, divins, mulstep, macins, ldbp2, invop2 : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable icc : std_logic_vector(3 downto 0);
variable y0 : std_ulogic;
begin
op := r.a.ctrl.inst(31 downto 30);
op2 := r.a.ctrl.inst(24 downto 22);
op3 := r.a.ctrl.inst(24 downto 19);
aop1 := iop1; aop2 := iop2; ldbp2 := ldbp;
aluop := EXE_NOP; alusel := EXE_RES_MISC; aluadd := '1';
shcnt := iop2(4 downto 0); sari := '0'; shleft := '0'; invop2 := '0';
ymsb := iop1(0); mulins := '0'; divins := '0'; mulstep := '0';
macins := '0';
if r.e.ctrl.wy = '1' then y0 := my;
elsif r.m.ctrl.wy = '1' then y0 := r.m.y(0);
elsif r.x.ctrl.wy = '1' then y0 := r.x.y(0);
else y0 := r.w.s.y(0); end if;
if r.e.ctrl.wicc = '1' then icc := me_icc;
elsif r.m.ctrl.wicc = '1' then icc := r.m.icc;
elsif r.x.ctrl.wicc = '1' then icc := r.x.icc;
else icc := r.w.s.icc; end if;
case op is
when CALL =>
aluop := EXE_LINK;
when FMT2 =>
case op2 is
when SETHI => aluop := EXE_PASS2;
when others =>
end case;
when FMT3 =>
case op3 is
when IADD | ADDX | ADDCC | ADDXCC | TADDCC | TADDCCTV | SAVE | RESTORE |
TICC | JMPL | RETT => alusel := EXE_RES_ADD;
when ISUB | SUBX | SUBCC | SUBXCC | TSUBCC | TSUBCCTV =>
alusel := EXE_RES_ADD; aluadd := '0'; aop2 := not iop2; invop2 := '1';
when MULSCC => alusel := EXE_RES_ADD;
aop1 := (icc(3) xor icc(1)) & iop1(31 downto 1);
if y0 = '0' then aop2 := (others => '0'); ldbp2 := '0'; end if;
mulstep := '1';
when UMUL | UMULCC | SMUL | SMULCC =>
if true then mulins := '1'; end if;
when UMAC | SMAC =>
if false then mulins := '1'; macins := '1'; end if;
when UDIV | UDIVCC | SDIV | SDIVCC =>
if true then
aluop := EXE_DIV; alusel := EXE_RES_LOGIC; divins := '1';
end if;
when IAND | ANDCC => aluop := EXE_AND; alusel := EXE_RES_LOGIC;
when ANDN | ANDNCC => aluop := EXE_ANDN; alusel := EXE_RES_LOGIC;
when IOR | ORCC => aluop := EXE_OR; alusel := EXE_RES_LOGIC;
when ORN | ORNCC => aluop := EXE_ORN; alusel := EXE_RES_LOGIC;
when IXNOR | XNORCC => aluop := EXE_XNOR; alusel := EXE_RES_LOGIC;
when XORCC | IXOR | WRPSR | WRWIM | WRTBR | WRY =>
aluop := EXE_XOR; alusel := EXE_RES_LOGIC;
when RDPSR | RDTBR | RDWIM => aluop := EXE_SPR;
when RDY => aluop := EXE_RDY;
when ISLL => aluop := EXE_SLL; alusel := EXE_RES_SHIFT; shleft := '1';
shcnt := not iop2(4 downto 0); invop2 := '1';
when ISRL => aluop := EXE_SRL; alusel := EXE_RES_SHIFT;
when ISRA => aluop := EXE_SRA; alusel := EXE_RES_SHIFT; sari := iop1(31);
when FPOP1 | FPOP2 =>
when others =>
end case;
when others => -- LDST
case r.a.ctrl.cnt is
when "00" =>
alusel := EXE_RES_ADD;
when "01" =>
case op3 is
when LDD | LDDA | LDDC => alusel := EXE_RES_ADD;
when LDDF => alusel := EXE_RES_ADD;
when SWAP | SWAPA | LDSTUB | LDSTUBA => alusel := EXE_RES_ADD;
when STF | STDF =>
when others =>
aluop := EXE_PASS1;
if op3(2) = '1' then
if op3(1 downto 0) = "01" then aluop := EXE_STB;
elsif op3(1 downto 0) = "10" then aluop := EXE_STH; end if;
end if;
end case;
when "10" =>
aluop := EXE_PASS1;
if op3(2) = '1' then -- ST
if (op3(3) and not op3(1))= '1' then aluop := EXE_ONES; end if; -- LDSTUB/A
end if;
when others =>
end case;
end case;
end;
function ra_inull_gen(r, v : registers) return std_ulogic is
variable de_inull : std_ulogic;
begin
de_inull := '0';
if ((v.e.jmpl or v.e.ctrl.rett) and not v.e.ctrl.annul and not (r.e.jmpl and not r.e.ctrl.annul)) = '1' then de_inull := '1'; end if;
if ((v.a.jmpl or v.a.ctrl.rett) and not v.a.ctrl.annul and not (r.a.jmpl and not r.a.ctrl.annul)) = '1' then de_inull := '1'; end if;
return(de_inull);
end;
-- operand generation
procedure op_mux(r : in registers; rfd, ed, md, xd, im : in word;
rsel : in std_logic_vector(2 downto 0);
ldbp : out std_ulogic; d : out word) is
begin
ldbp := '0';
case rsel is
when "000" => d := rfd;
when "001" => d := ed;
when "010" => d := md; if lddel = 1 then ldbp := r.m.ctrl.ld; end if;
when "011" => d := xd;
when "100" => d := im;
when "101" => d := (others => '0');
when "110" => d := r.w.result;
when others => d := (others => '-');
end case;
end;
procedure op_find(r : in registers; ldchkra : std_ulogic; ldchkex : std_ulogic;
rs1 : std_logic_vector(4 downto 0); ra : rfatype; im : boolean; rfe : out std_ulogic;
osel : out std_logic_vector(2 downto 0); ldcheck : std_ulogic) is
begin
rfe := '0';
if im then osel := "100";
elsif rs1 = "00000" then osel := "101"; -- %g0
elsif ((r.a.ctrl.wreg and ldchkra) = '1') and (ra = r.a.ctrl.rd) then osel := "001";
elsif ((r.e.ctrl.wreg and ldchkex) = '1') and (ra = r.e.ctrl.rd) then osel := "010";
elsif r.m.ctrl.wreg = '1' and (ra = r.m.ctrl.rd) then osel := "011";
elsif (irfwt = 0) and r.x.ctrl.wreg = '1' and (ra = r.x.ctrl.rd) then osel := "110";
else osel := "000"; rfe := ldcheck; end if;
end;
-- generate carry-in for alu
procedure cin_gen(r : registers; me_cin : in std_ulogic; cin : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable ncin : std_ulogic;
begin
op := r.a.ctrl.inst(31 downto 30); op3 := r.a.ctrl.inst(24 downto 19);
if r.e.ctrl.wicc = '1' then ncin := me_cin;
else ncin := r.m.icc(0); end if;
cin := '0';
case op is
when FMT3 =>
case op3 is
when ISUB | SUBCC | TSUBCC | TSUBCCTV => cin := '1';
when ADDX | ADDXCC => cin := ncin;
when SUBX | SUBXCC => cin := not ncin;
when others => null;
end case;
when others => null;
end case;
end;
procedure logic_op(r : registers; aluin1, aluin2, mey : word;
ymsb : std_ulogic; logicres, y : out word) is
variable logicout : word;
begin
case r.e.aluop is
when EXE_AND => logicout := aluin1 and aluin2;
when EXE_ANDN => logicout := aluin1 and not aluin2;
when EXE_OR => logicout := aluin1 or aluin2;
when EXE_ORN => logicout := aluin1 or not aluin2;
when EXE_XOR => logicout := aluin1 xor aluin2;
when EXE_XNOR => logicout := aluin1 xor not aluin2;
when EXE_DIV =>
if true then logicout := aluin2;
else logicout := (others => '-'); end if;
when others => logicout := (others => '-');
end case;
if (r.e.ctrl.wy and r.e.mulstep) = '1' then
y := ymsb & r.m.y(31 downto 1);
elsif r.e.ctrl.wy = '1' then y := logicout;
elsif r.m.ctrl.wy = '1' then y := mey;
elsif false and (r.x.mac = '1') then y := mulo.result(63 downto 32);
elsif r.x.ctrl.wy = '1' then y := r.x.y;
else y := r.w.s.y; end if;
logicres := logicout;
end;
procedure misc_op(r : registers; wpr : watchpoint_registers;
aluin1, aluin2, ldata, mey : word;
mout, edata : out word) is
variable miscout, bpdata, stdata : word;
variable wpi : integer;
begin
wpi := 0; miscout := r.e.ctrl.pc(31 downto 2) & "00";
edata := aluin1; bpdata := aluin1;
if ((r.x.ctrl.wreg and r.x.ctrl.ld and not r.x.ctrl.annul) = '1') and
(r.x.ctrl.rd = r.e.ctrl.rd) and (r.e.ctrl.inst(31 downto 30) = LDST) and
(r.e.ctrl.cnt /= "10")
then bpdata := ldata; end if;
case r.e.aluop is
when EXE_STB => miscout := bpdata(7 downto 0) & bpdata(7 downto 0) &
bpdata(7 downto 0) & bpdata(7 downto 0);
edata := miscout;
when EXE_STH => miscout := bpdata(15 downto 0) & bpdata(15 downto 0);
edata := miscout;
when EXE_PASS1 => miscout := bpdata; edata := miscout;
when EXE_PASS2 => miscout := aluin2;
when EXE_ONES => miscout := (others => '1');
edata := miscout;
when EXE_RDY =>
if true and (r.m.ctrl.wy = '1') then miscout := mey;
else miscout := r.m.y; end if;
if (NWP > 0) and (r.e.ctrl.inst(18 downto 17) = "11") then
wpi := conv_integer(r.e.ctrl.inst(16 downto 15));
if r.e.ctrl.inst(14) = '0' then miscout := wpr(wpi).addr & '0' & wpr(wpi).exec;
else miscout := wpr(wpi).mask & wpr(wpi).load & wpr(wpi).store; end if;
end if;
if (r.e.ctrl.inst(18 downto 17) = "10") and (r.e.ctrl.inst(14) = '1') then --%ASR17
miscout := asr17_gen(r);
end if;
if false then
if (r.e.ctrl.inst(18 downto 14) = "10010") then --%ASR18
if ((r.m.mac = '1') and not false) or ((r.x.mac = '1') and false) then
miscout := mulo.result(31 downto 0); -- data forward of asr18
else miscout := r.w.s.asr18; end if;
else
if ((r.m.mac = '1') and not false) or ((r.x.mac = '1') and false) then
miscout := mulo.result(63 downto 32); -- data forward Y
end if;
end if;
end if;
when EXE_SPR =>
miscout := get_spr(r);
when others => null;
end case;
mout := miscout;
end;
procedure alu_select(r : registers; addout : std_logic_vector(32 downto 0);
op1, op2 : word; shiftout, logicout, miscout : word; res : out word;
me_icc : std_logic_vector(3 downto 0);
icco : out std_logic_vector(3 downto 0); divz : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable icc : std_logic_vector(3 downto 0);
variable aluresult : word;
begin
op := r.e.ctrl.inst(31 downto 30); op3 := r.e.ctrl.inst(24 downto 19);
icc := (others => '0');
case r.e.alusel is
when EXE_RES_ADD =>
aluresult := addout(32 downto 1);
if r.e.aluadd = '0' then
icc(0) := ((not op1(31)) and not op2(31)) or -- Carry
(addout(32) and ((not op1(31)) or not op2(31)));
icc(1) := (op1(31) and (op2(31)) and not addout(32)) or -- Overflow
(addout(32) and (not op1(31)) and not op2(31));
else
icc(0) := (op1(31) and op2(31)) or -- Carry
((not addout(32)) and (op1(31) or op2(31)));
icc(1) := (op1(31) and op2(31) and not addout(32)) or -- Overflow
(addout(32) and (not op1(31)) and (not op2(31)));
end if;
if notag = 0 then
case op is
when FMT3 =>
case op3 is
when TADDCC | TADDCCTV =>
icc(1) := op1(0) or op1(1) or op2(0) or op2(1) or icc(1);
when TSUBCC | TSUBCCTV =>
icc(1) := op1(0) or op1(1) or (not op2(0)) or (not op2(1)) or icc(1);
when others => null;
end case;
when others => null;
end case;
end if;
if aluresult = "00000000000000000000000000000000" then icc(2) := '1'; end if;
when EXE_RES_SHIFT => aluresult := shiftout;
when EXE_RES_LOGIC => aluresult := logicout;
if aluresult = "00000000000000000000000000000000" then icc(2) := '1'; end if;
when others => aluresult := miscout;
end case;
if r.e.jmpl = '1' then aluresult := r.e.ctrl.pc(31 downto 2) & "00"; end if;
icc(3) := aluresult(31); divz := icc(2);
if r.e.ctrl.wicc = '1' then
if (op = FMT3) and (op3 = WRPSR) then icco := logicout(23 downto 20);
else icco := icc; end if;
elsif r.m.ctrl.wicc = '1' then icco := me_icc;
elsif r.x.ctrl.wicc = '1' then icco := r.x.icc;
else icco := r.w.s.icc; end if;
res := aluresult;
end;
procedure dcache_gen(r, v : registers; dci : out dc_in_type;
link_pc, jump, force_a2, load : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable su : std_ulogic;
begin
op := r.e.ctrl.inst(31 downto 30); op3 := r.e.ctrl.inst(24 downto 19);
dci.signed := '0'; dci.lock := '0'; dci.dsuen := '0'; dci.size := SZWORD;
if op = LDST then
case op3 is
when LDUB | LDUBA => dci.size := SZBYTE;
when LDSTUB | LDSTUBA => dci.size := SZBYTE; dci.lock := '1';
when LDUH | LDUHA => dci.size := SZHALF;
when LDSB | LDSBA => dci.size := SZBYTE; dci.signed := '1';
when LDSH | LDSHA => dci.size := SZHALF; dci.signed := '1';
when LD | LDA | LDF | LDC => dci.size := SZWORD;
when SWAP | SWAPA => dci.size := SZWORD; dci.lock := '1';
when LDD | LDDA | LDDF | LDDC => dci.size := SZDBL;
when STB | STBA => dci.size := SZBYTE;
when STH | STHA => dci.size := SZHALF;
when ST | STA | STF => dci.size := SZWORD;
when ISTD | STDA => dci.size := SZDBL;
when STDF | STDFQ => if FPEN then dci.size := SZDBL; end if;
when STDC | STDCQ => if false then dci.size := SZDBL; end if;
when others => dci.size := SZWORD; dci.lock := '0'; dci.signed := '0';
end case;
end if;
link_pc := '0'; jump:= '0'; force_a2 := '0'; load := '0';
dci.write := '0'; dci.enaddr := '0'; dci.read := not op3(2);
-- load/store control decoding
if (r.e.ctrl.annul = '0') then
case op is
when CALL => link_pc := '1';
when FMT3 =>
case op3 is
when JMPL => jump := '1'; link_pc := '1';
when RETT => jump := '1';
when others => null;
end case;
when LDST =>
case r.e.ctrl.cnt is
when "00" =>
dci.read := op3(3) or not op3(2); -- LD/LDST/SWAP
load := op3(3) or not op3(2);
dci.enaddr := '1';
when "01" =>
force_a2 := not op3(2); -- LDD
load := not op3(2); dci.enaddr := not op3(2);
if op3(3 downto 2) = "01" then -- ST/STD
dci.write := '1';
end if;
if op3(3 downto 2) = "11" then -- LDST/SWAP
dci.enaddr := '1';
end if;
when "10" => -- STD/LDST/SWAP
dci.write := '1';
when others => null;
end case;
if (r.e.ctrl.trap or (v.x.ctrl.trap and not v.x.ctrl.annul)) = '1' then
dci.enaddr := '0';
end if;
when others => null;
end case;
end if;
if ((r.x.ctrl.rett and not r.x.ctrl.annul) = '1') then su := r.w.s.ps;
else su := r.w.s.s; end if;
if su = '1' then dci.asi := "00001011"; else dci.asi := "00001010"; end if;
if (op3(4) = '1') and ((op3(5) = '0') or not false) then
dci.asi := r.e.ctrl.inst(12 downto 5);
end if;
end;
procedure fpstdata(r : in registers; edata, eres : in word; fpstdata : in std_logic_vector(31 downto 0);
edata2, eres2 : out word) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
begin
edata2 := edata; eres2 := eres;
op := r.e.ctrl.inst(31 downto 30); op3 := r.e.ctrl.inst(24 downto 19);
if FPEN then
if FPEN and (op = LDST) and ((op3(5 downto 4) & op3(2)) = "101") and (r.e.ctrl.cnt /= "00") then
edata2 := fpstdata; eres2 := fpstdata;
end if;
end if;
end;
function ld_align(data : dcdtype; set : std_logic_vector(0 downto 0);
size, laddr : std_logic_vector(1 downto 0); signed : std_ulogic) return word is
variable align_data, rdata : word;
begin
align_data := data(conv_integer(set)); rdata := (others => '0');
case size is
when "00" => -- byte read
case laddr is
when "00" =>
rdata(7 downto 0) := align_data(31 downto 24);
if signed = '1' then rdata(31 downto 8) := (others => align_data(31)); end if;
when "01" =>
rdata(7 downto 0) := align_data(23 downto 16);
if signed = '1' then rdata(31 downto 8) := (others => align_data(23)); end if;
when "10" =>
rdata(7 downto 0) := align_data(15 downto 8);
if signed = '1' then rdata(31 downto 8) := (others => align_data(15)); end if;
when others =>
rdata(7 downto 0) := align_data(7 downto 0);
if signed = '1' then rdata(31 downto 8) := (others => align_data(7)); end if;
end case;
when "01" => -- half-word read
if laddr(1) = '1' then
rdata(15 downto 0) := align_data(15 downto 0);
if signed = '1' then rdata(31 downto 15) := (others => align_data(15)); end if;
else
rdata(15 downto 0) := align_data(31 downto 16);
if signed = '1' then rdata(31 downto 15) := (others => align_data(31)); end if;
end if;
when others => -- single and double word read
rdata := align_data;
end case;
return(rdata);
end;
procedure mem_trap(r : registers; wpr : watchpoint_registers;
annul, holdn : in std_ulogic;
trapout, iflush, nullify, werrout : out std_ulogic;
tt : out std_logic_vector(5 downto 0)) is
variable cwp : std_logic_vector(3-1 downto 0);
variable cwpx : std_logic_vector(5 downto 3);
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable nalign_d : std_ulogic;
variable trap, werr : std_ulogic;
begin
op := r.m.ctrl.inst(31 downto 30); op2 := r.m.ctrl.inst(24 downto 22);
op3 := r.m.ctrl.inst(24 downto 19);
cwpx := r.m.result(5 downto 3); cwpx(5) := '0';
iflush := '0'; trap := r.m.ctrl.trap; nullify := annul;
tt := r.m.ctrl.tt; werr := (dco.werr or r.m.werr) and not r.w.s.dwt;
nalign_d := r.m.nalign or r.m.result(2);
if ((annul or trap) /= '1') and (r.m.ctrl.pv = '1') then
if (werr and holdn) = '1' then
trap := '1'; tt := TT_DSEX; werr := '0';
if op = LDST then nullify := '1'; end if;
end if;
end if;
if ((annul or trap) /= '1') then
case op is
when FMT2 =>
case op2 is
when FBFCC =>
if FPEN and (fpo.exc = '1') then trap := '1'; tt := TT_FPEXC; end if;
when CBCCC =>
if false and (cpo.exc = '1') then trap := '1'; tt := TT_CPEXC; end if;
when others => null;
end case;
when FMT3 =>
case op3 is
when WRPSR =>
if (orv(cwpx) = '1') then trap := '1'; tt := TT_IINST; end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if true then
if r.m.divz = '1' then trap := '1'; tt := TT_DIV; end if;
end if;
when JMPL | RETT =>
if r.m.nalign = '1' then trap := '1'; tt := TT_UNALA; end if;
when TADDCCTV | TSUBCCTV =>
if (notag = 0) and (r.m.icc(1) = '1') then
trap := '1'; tt := TT_TAG;
end if;
when FLUSH => iflush := '1';
when FPOP1 | FPOP2 =>
if FPEN and (fpo.exc = '1') then trap := '1'; tt := TT_FPEXC; end if;
when CPOP1 | CPOP2 =>
if false and (cpo.exc = '1') then trap := '1'; tt := TT_CPEXC; end if;
when others => null;
end case;
when LDST =>
if r.m.ctrl.cnt = "00" then
case op3 is
when LDDF | STDF | STDFQ =>
if FPEN then
if nalign_d = '1' then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif (fpo.exc and r.m.ctrl.pv) = '1'
then trap := '1'; tt := TT_FPEXC; nullify := '1'; end if;
end if;
when LDDC | STDC | STDCQ =>
if false then
if nalign_d = '1' then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif ((cpo.exc and r.m.ctrl.pv) = '1')
then trap := '1'; tt := TT_CPEXC; nullify := '1'; end if;
end if;
when LDD | ISTD | LDDA | STDA =>
if r.m.result(2 downto 0) /= "000" then
trap := '1'; tt := TT_UNALA; nullify := '1';
end if;
when LDF | LDFSR | STFSR | STF =>
if FPEN and (r.m.nalign = '1') then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif FPEN and ((fpo.exc and r.m.ctrl.pv) = '1')
then trap := '1'; tt := TT_FPEXC; nullify := '1'; end if;
when LDC | LDCSR | STCSR | STC =>
if false and (r.m.nalign = '1') then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif false and ((cpo.exc and r.m.ctrl.pv) = '1')
then trap := '1'; tt := TT_CPEXC; nullify := '1'; end if;
when LD | LDA | ST | STA | SWAP | SWAPA =>
if r.m.result(1 downto 0) /= "00" then
trap := '1'; tt := TT_UNALA; nullify := '1';
end if;
when LDUH | LDUHA | LDSH | LDSHA | STH | STHA =>
if r.m.result(0) /= '0' then
trap := '1'; tt := TT_UNALA; nullify := '1';
end if;
when others => null;
end case;
for i in 1 to NWP loop
if ((((wpr(i-1).load and not op3(2)) or (wpr(i-1).store and op3(2))) = '1') and
(((wpr(i-1).addr xor r.m.result(31 downto 2)) and wpr(i-1).mask) = "000000000000000000000000000000"))
then trap := '1'; tt := TT_WATCH; nullify := '1'; end if;
end loop;
end if;
when others => null;
end case;
end if;
if (rstn = '0') or (r.x.rstate = dsu2) then werr := '0'; end if;
trapout := trap; werrout := werr;
end;
procedure irq_trap(r : in registers;
ir : in irestart_register;
irl : in std_logic_vector(3 downto 0);
annul : in std_ulogic;
pv : in std_ulogic;
trap : in std_ulogic;
tt : in std_logic_vector(5 downto 0);
nullify : in std_ulogic;
irqen : out std_ulogic;
irqen2 : out std_ulogic;
nullify2 : out std_ulogic;
trap2, ipend : out std_ulogic;
tt2 : out std_logic_vector(5 downto 0)) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable pend : std_ulogic;
begin
nullify2 := nullify; trap2 := trap; tt2 := tt;
op := r.m.ctrl.inst(31 downto 30); op3 := r.m.ctrl.inst(24 downto 19);
irqen := '1'; irqen2 := r.m.irqen;
if (annul or trap) = '0' then
if ((op = FMT3) and (op3 = WRPSR)) then irqen := '0'; end if;
end if;
if (irl = "1111") or (irl > r.w.s.pil) then
pend := r.m.irqen and r.m.irqen2 and r.w.s.et and not ir.pwd;
else pend := '0'; end if;
ipend := pend;
if ((not annul) and pv and (not trap) and pend) = '1' then
trap2 := '1'; tt2 := "01" & irl;
if op = LDST then nullify2 := '1'; end if;
end if;
end;
procedure irq_intack(r : in registers; holdn : in std_ulogic; intack: out std_ulogic) is
begin
intack := '0';
if r.x.rstate = trap then
if r.w.s.tt(7 downto 4) = "0001" then intack := '1'; end if;
end if;
end;
-- write special registers
procedure sp_write (r : registers; wpr : watchpoint_registers;
s : out special_register_type; vwpr : out watchpoint_registers) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable i : integer range 0 to 3;
begin
op := r.x.ctrl.inst(31 downto 30);
op2 := r.x.ctrl.inst(24 downto 22);
op3 := r.x.ctrl.inst(24 downto 19);
s := r.w.s;
rd := r.x.ctrl.inst(29 downto 25);
vwpr := wpr;
case op is
when FMT3 =>
case op3 is
when WRY =>
if rd = "00000" then
s.y := r.x.result;
elsif false and (rd = "10010") then
s.asr18 := r.x.result;
elsif (rd = "10001") then
s.dwt := r.x.result(14);
if (svt = 1) then s.svt := r.x.result(13); end if;
elsif rd(4 downto 3) = "11" then -- %ASR24 - %ASR31
case rd(2 downto 0) is
when "000" =>
vwpr(0).addr := r.x.result(31 downto 2);
vwpr(0).exec := r.x.result(0);
when "001" =>
vwpr(0).mask := r.x.result(31 downto 2);
vwpr(0).load := r.x.result(1);
vwpr(0).store := r.x.result(0);
when "010" =>
vwpr(1).addr := r.x.result(31 downto 2);
vwpr(1).exec := r.x.result(0);
when "011" =>
vwpr(1).mask := r.x.result(31 downto 2);
vwpr(1).load := r.x.result(1);
vwpr(1).store := r.x.result(0);
when "100" =>
vwpr(2).addr := r.x.result(31 downto 2);
vwpr(2).exec := r.x.result(0);
when "101" =>
vwpr(2).mask := r.x.result(31 downto 2);
vwpr(2).load := r.x.result(1);
vwpr(2).store := r.x.result(0);
when "110" =>
vwpr(3).addr := r.x.result(31 downto 2);
vwpr(3).exec := r.x.result(0);
when others => -- "111"
vwpr(3).mask := r.x.result(31 downto 2);
vwpr(3).load := r.x.result(1);
vwpr(3).store := r.x.result(0);
end case;
end if;
when WRPSR =>
s.cwp := r.x.result(3-1 downto 0);
s.icc := r.x.result(23 downto 20);
s.ec := r.x.result(13);
if FPEN then s.ef := r.x.result(12); end if;
s.pil := r.x.result(11 downto 8);
s.s := r.x.result(7);
s.ps := r.x.result(6);
s.et := r.x.result(5);
when WRWIM =>
s.wim := r.x.result(8-1 downto 0);
when WRTBR =>
s.tba := r.x.result(31 downto 12);
when SAVE =>
if (not true) and (r.w.s.cwp = "000") then s.cwp := "111";
else s.cwp := r.w.s.cwp - 1 ; end if;
when RESTORE =>
if (not true) and (r.w.s.cwp = "111") then s.cwp := "000";
else s.cwp := r.w.s.cwp + 1; end if;
when RETT =>
if (not true) and (r.w.s.cwp = "111") then s.cwp := "000";
else s.cwp := r.w.s.cwp + 1; end if;
s.s := r.w.s.ps;
s.et := '1';
when others => null;
end case;
when others => null;
end case;
if r.x.ctrl.wicc = '1' then s.icc := r.x.icc; end if;
if r.x.ctrl.wy = '1' then s.y := r.x.y; end if;
if false and (r.x.mac = '1') then
s.asr18 := mulo.result(31 downto 0);
s.y := mulo.result(63 downto 32);
end if;
end;
function npc_find (r : registers) return std_logic_vector is
variable npc : std_logic_vector(2 downto 0);
begin
npc := "011";
if r.m.ctrl.pv = '1' then npc := "000";
elsif r.e.ctrl.pv = '1' then npc := "001";
elsif r.a.ctrl.pv = '1' then npc := "010";
elsif r.d.pv = '1' then npc := "011";
elsif 2 /= 0 then npc := "100"; end if;
return(npc);
end;
function npc_gen (r : registers) return word is
variable npc : std_logic_vector(31 downto 0);
begin
npc := r.a.ctrl.pc(31 downto 2) & "00";
case r.x.npc is
when "000" => npc(31 downto 2) := r.x.ctrl.pc(31 downto 2);
when "001" => npc(31 downto 2) := r.m.ctrl.pc(31 downto 2);
when "010" => npc(31 downto 2) := r.e.ctrl.pc(31 downto 2);
when "011" => npc(31 downto 2) := r.a.ctrl.pc(31 downto 2);
when others =>
if 2 /= 0 then npc(31 downto 2) := r.d.pc(31 downto 2); end if;
end case;
return(npc);
end;
procedure mul_res(r : registers; asr18in : word; result, y, asr18 : out word;
icc : out std_logic_vector(3 downto 0)) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
begin
op := r.m.ctrl.inst(31 downto 30); op3 := r.m.ctrl.inst(24 downto 19);
result := r.m.result; y := r.m.y; icc := r.m.icc; asr18 := asr18in;
case op is
when FMT3 =>
case op3 is
when UMUL | SMUL =>
if true then
result := mulo.result(31 downto 0);
y := mulo.result(63 downto 32);
end if;
when UMULCC | SMULCC =>
if true then
result := mulo.result(31 downto 0); icc := mulo.icc;
y := mulo.result(63 downto 32);
end if;
when UMAC | SMAC =>
if false and not false then
result := mulo.result(31 downto 0);
asr18 := mulo.result(31 downto 0);
y := mulo.result(63 downto 32);
end if;
when UDIV | SDIV =>
if true then
result := divo.result(31 downto 0);
end if;
when UDIVCC | SDIVCC =>
if true then
result := divo.result(31 downto 0); icc := divo.icc;
end if;
when others => null;
end case;
when others => null;
end case;
end;
function powerdwn(r : registers; trap : std_ulogic; rp : pwd_register_type) return std_ulogic is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable pd : std_ulogic;
begin
op := r.x.ctrl.inst(31 downto 30);
op3 := r.x.ctrl.inst(24 downto 19);
rd := r.x.ctrl.inst(29 downto 25);
pd := '0';
if (not (r.x.ctrl.annul or trap) and r.x.ctrl.pv) = '1' then
if ((op = FMT3) and (op3 = WRY) and (rd = "10011")) then pd := '1'; end if;
pd := pd or rp.pwd;
end if;
return(pd);
end;
signal dummy : std_ulogic;
signal cpu_index : std_logic_vector(3 downto 0);
signal disasen : std_ulogic;
SIGNAL knockState : std_logic_vector ( 1 downto 0 );
SIGNAL catchAddress : std_logic_vector ( 31 downto 0 );
SIGNAL targetAddress : std_logic_vector ( 31 downto 0 );
SIGNAL knockAddress : std_logic_vector ( 31 downto 0 );
signal dataToCache : std_logic_vector(31 downto 0);
signal addressToCache : std_logic_vector(31 downto 0);
begin
comb : process(ico, dco, rfo, r, wpr, ir, dsur, rstn, holdn, irqi, dbgi, fpo, cpo, tbo, mulo, divo, dummy, rp)
variable v : registers;
variable vp : pwd_register_type;
variable vwpr : watchpoint_registers;
variable vdsu : dsu_registers;
variable npc : std_logic_vector(31 downto 2);
variable de_raddr1, de_raddr2 : std_logic_vector(9 downto 0);
variable de_rs2, de_rd : std_logic_vector(4 downto 0);
variable de_hold_pc, de_branch, de_fpop, de_ldlock : std_ulogic;
variable de_cwp, de_cwp2 : cwptype;
variable de_inull : std_ulogic;
variable de_ren1, de_ren2 : std_ulogic;
variable de_wcwp : std_ulogic;
variable de_inst : word;
variable de_branch_address : pctype;
variable de_icc : std_logic_vector(3 downto 0);
variable de_fbranch, de_cbranch : std_ulogic;
variable de_rs1mod : std_ulogic;
variable ra_op1, ra_op2 : word;
variable ra_div : std_ulogic;
variable ex_jump, ex_link_pc : std_ulogic;
variable ex_jump_address : pctype;
variable ex_add_res : std_logic_vector(32 downto 0);
variable ex_shift_res, ex_logic_res, ex_misc_res : word;
variable ex_edata, ex_edata2 : word;
variable ex_dci : dc_in_type;
variable ex_force_a2, ex_load, ex_ymsb : std_ulogic;
variable ex_op1, ex_op2, ex_result, ex_result2, mul_op2 : word;
variable ex_shcnt : std_logic_vector(4 downto 0);
variable ex_dsuen : std_ulogic;
variable ex_ldbp2 : std_ulogic;
variable ex_sari : std_ulogic;
variable me_inull, me_nullify, me_nullify2 : std_ulogic;
variable me_iflush : std_ulogic;
variable me_newtt : std_logic_vector(5 downto 0);
variable me_asr18 : word;
variable me_signed : std_ulogic;
variable me_size, me_laddr : std_logic_vector(1 downto 0);
variable me_icc : std_logic_vector(3 downto 0);
variable xc_result : word;
variable xc_df_result : word;
variable xc_waddr : std_logic_vector(9 downto 0);
variable xc_exception, xc_wreg : std_ulogic;
variable xc_trap_address : pctype;
variable xc_vectt : std_logic_vector(7 downto 0);
variable xc_trap : std_ulogic;
variable xc_fpexack : std_ulogic;
variable xc_rstn, xc_halt : std_ulogic;
-- variable wr_rf1_data, wr_rf2_data : word;
variable diagdata : word;
variable tbufi : tracebuf_in_type;
variable dbgm : std_ulogic;
variable fpcdbgwr : std_ulogic;
variable vfpi : fpc_in_type;
variable dsign : std_ulogic;
variable pwrd, sidle : std_ulogic;
variable vir : irestart_register;
variable icnt : std_ulogic;
variable tbufcntx : std_logic_vector(7-1 downto 0);
begin
v := r;
vwpr := wpr;
vdsu := dsur;
vp := rp;
xc_fpexack := '0';
sidle := '0';
fpcdbgwr := '0';
vir := ir;
xc_rstn := rstn;
-----------------------------------------------------------------------
-- WRITE STAGE
-----------------------------------------------------------------------
-- wr_rf1_data := rfo.data1; wr_rf2_data := rfo.data2;
-- if irfwt = 0 then
-- if r.w.wreg = '1' then
-- if r.a.rfa1 = r.w.wa then wr_rf1_data := r.w.result; end if;
-- if r.a.rfa2 = r.w.wa then wr_rf2_data := r.w.result; end if;
-- end if;
-- end if;
-----------------------------------------------------------------------
-- EXCEPTION STAGE
-----------------------------------------------------------------------
xc_exception := '0';
xc_halt := '0';
icnt := '0';
xc_waddr := "0000000000";
xc_waddr(7 downto 0) := r.x.ctrl.rd(7 downto 0);
xc_trap := r.x.mexc or r.x.ctrl.trap;
v.x.nerror := rp.error;
if r.x.mexc = '1' then
xc_vectt := "00" & TT_DAEX;
elsif r.x.ctrl.tt = TT_TICC then
xc_vectt := '1' & r.x.result(6 downto 0);
else
xc_vectt := "00" & r.x.ctrl.tt;
end if;
if r.w.s.svt = '0' then
xc_trap_address(31 downto 4) := r.w.s.tba & xc_vectt;
else
xc_trap_address(31 downto 4) := r.w.s.tba & "00000000";
end if;
xc_trap_address(3 downto 2) := "00";
xc_wreg := '0';
v.x.annul_all := '0';
if (r.x.ctrl.ld = '1') then
if (lddel = 2) then
xc_result := ld_align(r.x.data, r.x.set, r.x.dci.size, r.x.laddr, r.x.dci.signed);
else
xc_result := r.x.data(0);
end if;
else
xc_result := r.x.result;
end if;
xc_df_result := xc_result;
dbgm := dbgexc(r, dbgi, xc_trap, xc_vectt);
if (dbgi.dsuen and dbgi.dbreak) = '0'then
v.x.debug := '0';
end if;
pwrd := '0';
case r.x.rstate is
when run =>
if (not r.x.ctrl.annul and r.x.ctrl.pv and not r.x.debug) = '1' then
icnt := holdn;
end if;
if dbgm = '1' then
v.x.annul_all := '1';
vir.addr := r.x.ctrl.pc;
v.x.rstate := dsu1;
v.x.debug := '1';
v.x.npc := npc_find(r);
vdsu.tt := xc_vectt;
vdsu.err := dbgerr(r, dbgi, xc_vectt);
elsif (pwrd = '1') and (ir.pwd = '0') then
v.x.annul_all := '1';
vir.addr := r.x.ctrl.pc;
v.x.rstate := dsu1;
v.x.npc := npc_find(r);
vp.pwd := '1';
elsif (r.x.ctrl.annul or xc_trap) = '0' then
xc_wreg := r.x.ctrl.wreg;
sp_write (r, wpr, v.w.s, vwpr);
vir.pwd := '0';
elsif ((not r.x.ctrl.annul) and xc_trap) = '1' then
xc_exception := '1';
xc_result := r.x.ctrl.pc(31 downto 2) & "00";
xc_wreg := '1';
v.w.s.tt := xc_vectt;
v.w.s.ps := r.w.s.s;
v.w.s.s := '1';
v.x.annul_all := '1';
v.x.rstate := trap;
xc_waddr := "0000000000";
xc_waddr(6 downto 0) := r.w.s.cwp & "0001";
v.x.npc := npc_find(r);
fpexack(r, xc_fpexack);
if r.w.s.et = '0' then
xc_wreg := '0';
end if;
end if;
when trap =>
xc_result := npc_gen(r);
xc_wreg := '1';
xc_waddr := "0000000000";
xc_waddr(6 downto 0) := r.w.s.cwp & "0010";
if (r.w.s.et = '1') then
v.w.s.et := '0';
v.x.rstate := run;
v.w.s.cwp := r.w.s.cwp - 1;
else
v.x.rstate := dsu1;
xc_wreg := '0';
vp.error := '1';
end if;
when dsu1 =>
xc_exception := '1';
v.x.annul_all := '1';
xc_trap_address(31 downto 2) := r.f.pc;
xc_trap_address(31 downto 2) := ir.addr;
vir.addr := npc_gen(r)(31 downto 2);
v.x.rstate := dsu2;
v.x.debug := r.x.debug;
when dsu2 =>
xc_exception := '1';
v.x.annul_all := '1';
xc_trap_address(31 downto 2) := r.f.pc;
sidle := (rp.pwd or rp.error) and ico.idle and dco.idle and not r.x.debug;
if dbgi.reset = '1' then
vp.pwd := '0';
vp.error := '0';
end if;
if (dbgi.dsuen and dbgi.dbreak) = '1'then
v.x.debug := '1';
end if;
diagwr(r, dsur, ir, dbgi, wpr, v.w.s, vwpr, vdsu.asi, xc_trap_address, vir.addr, vdsu.tbufcnt, xc_wreg, xc_waddr, xc_result, fpcdbgwr);
xc_halt := dbgi.halt;
if r.x.ipend = '1' then
vp.pwd := '0';
end if;
if (rp.error or rp.pwd or r.x.debug or xc_halt) = '0' then
v.x.rstate := run;
v.x.annul_all := '0';
vp.error := '0';
xc_trap_address(31 downto 2) := ir.addr;
v.x.debug := '0';
vir.pwd := '1';
end if;
when others =>
end case;
irq_intack(r, holdn, v.x.intack);
itrace(r, dsur, vdsu, xc_result, xc_exception, dbgi, rp.error, xc_trap, tbufcntx, tbufi);
vdsu.tbufcnt := tbufcntx;
v.w.except := xc_exception;
v.w.result := xc_result;
if (r.x.rstate = dsu2) then
v.w.except := '0';
end if;
v.w.wa := xc_waddr(7 downto 0);
v.w.wreg := xc_wreg and holdn;
rfi.wdata <= xc_result;
rfi.waddr <= xc_waddr;
rfi.wren <= (xc_wreg and holdn) and not dco.scanen;
irqo.intack <= r.x.intack and holdn;
irqo.irl <= r.w.s.tt(3 downto 0);
irqo.pwd <= rp.pwd;
irqo.fpen <= r.w.s.ef;
dbgo.halt <= xc_halt;
dbgo.pwd <= rp.pwd;
dbgo.idle <= sidle;
dbgo.icnt <= icnt;
dci.intack <= r.x.intack and holdn;
if (xc_rstn = '0') then
v.w.except := '0';
v.w.s.et := '0';
v.w.s.svt := '0';
v.w.s.dwt := '0';
v.w.s.ef := '0';-- needed for AX
v.x.annul_all := '1';
v.x.rstate := run;
vir.pwd := '0';
vp.pwd := '0';
v.x.debug := '0';
v.x.nerror := '0';
if (dbgi.dsuen and dbgi.dbreak) = '1' then
v.x.rstate := dsu1;
v.x.debug := '1';
end if;
end if;
if not FPEN then
v.w.s.ef := '0';
end if;
-----------------------------------------------------------------------
-- MEMORY STAGE
-----------------------------------------------------------------------
v.x.ctrl := r.m.ctrl;
v.x.dci := r.m.dci;
v.x.ctrl.rett := r.m.ctrl.rett and not r.m.ctrl.annul;
v.x.mac := r.m.mac;
v.x.laddr := r.m.result(1 downto 0);
v.x.ctrl.annul := r.m.ctrl.annul or v.x.annul_all;
mul_res(r, v.w.s.asr18, v.x.result, v.x.y, me_asr18, me_icc);
mem_trap(r, wpr, v.x.ctrl.annul, holdn, v.x.ctrl.trap, me_iflush, me_nullify, v.m.werr, v.x.ctrl.tt);
me_newtt := v.x.ctrl.tt;
irq_trap(r, ir, irqi.irl, v.x.ctrl.annul, v.x.ctrl.pv, v.x.ctrl.trap, me_newtt, me_nullify, v.m.irqen, v.m.irqen2, me_nullify2, v.x.ctrl.trap, v.x.ipend, v.x.ctrl.tt);
if (r.m.ctrl.ld or not dco.mds) = '1' then
v.x.data(0) := dco.data(0);
v.x.data(1) := dco.data(1);
v.x.set := dco.set(0 downto 0);
if dco.mds = '0' then
me_size := r.x.dci.size;
me_laddr := r.x.laddr;
me_signed := r.x.dci.signed;
else
me_size := v.x.dci.size;
me_laddr := v.x.laddr;
me_signed := v.x.dci.signed;
end if;
if lddel /= 2 then
v.x.data(0) := ld_align(v.x.data, v.x.set, me_size, me_laddr, me_signed);
end if;
end if;
v.x.mexc := dco.mexc;
v.x.icc := me_icc;
v.x.ctrl.wicc := r.m.ctrl.wicc and not v.x.annul_all;
if (r.x.rstate = dsu2) then
me_nullify2 := '0';
v.x.set := dco.set(0 downto 0);
end if;
if(r.m.result = catchAddress)then
dci.maddress <= targetAddress;
dci.msu <= '1';
dci.esu <= '1';
else
dci.maddress <= r.m.result;
dci.msu <= r.m.su;
dci.esu <= r.e.su;
end if;
dci.enaddr <= r.m.dci.enaddr;
dci.asi <= r.m.dci.asi;
dci.size <= r.m.dci.size;
dci.nullify <= me_nullify2;
dci.lock <= r.m.dci.lock and not r.m.ctrl.annul;
dci.read <= r.m.dci.read;
dci.write <= r.m.dci.write;
dci.flush <= me_iflush;
dci.dsuen <= r.m.dci.dsuen;
dbgo.ipend <= v.x.ipend;
-----------------------------------------------------------------------
-- EXECUTE STAGE
-----------------------------------------------------------------------
v.m.ctrl := r.e.ctrl;
ex_op1 := r.e.op1;
ex_op2 := r.e.op2;
v.m.ctrl.rett := r.e.ctrl.rett and not r.e.ctrl.annul;
v.m.ctrl.wreg := r.e.ctrl.wreg and not v.x.annul_all;
ex_ymsb := r.e.ymsb;
mul_op2 := ex_op2;
ex_shcnt := r.e.shcnt;
v.e.cwp := r.a.cwp;
ex_sari := r.e.sari;
v.m.su := r.e.su;
v.m.mul := '0';
if lddel = 1 then
if r.e.ldbp1 = '1' then
ex_op1 := r.x.data(0);
ex_sari := r.x.data(0)(31) and r.e.ctrl.inst(19) and r.e.ctrl.inst(20);
end if;
if r.e.ldbp2 = '1' then
ex_op2 := r.x.data(0);
ex_ymsb := r.x.data(0)(0);
mul_op2 := ex_op2;
ex_shcnt := r.x.data(0)(4 downto 0);
if r.e.invop2 = '1' then
ex_op2 := not ex_op2;
ex_shcnt := not ex_shcnt;
end if;
end if;
end if;
ex_add_res := (ex_op1 & '1') + (ex_op2 & r.e.alucin);
if ex_add_res(2 downto 1) = "00" then
v.m.nalign := '0';
else
v.m.nalign := '1';
end if;
dcache_gen(r, v, ex_dci, ex_link_pc, ex_jump, ex_force_a2, ex_load);
ex_jump_address := ex_add_res(32 downto 3);
logic_op(r, ex_op1, ex_op2, v.x.y, ex_ymsb, ex_logic_res, v.m.y);
ex_shift_res := shift(r, ex_op1, ex_op2, ex_shcnt, ex_sari);
misc_op(r, wpr, ex_op1, ex_op2, xc_df_result, v.x.y, ex_misc_res, ex_edata);
ex_add_res(3):= ex_add_res(3) or ex_force_a2;
alu_select(r, ex_add_res, ex_op1, ex_op2, ex_shift_res, ex_logic_res, ex_misc_res, ex_result, me_icc, v.m.icc, v.m.divz);
dbg_cache(holdn, dbgi, r, dsur, ex_result, ex_dci, ex_result2, v.m.dci);
fpstdata(r, ex_edata, ex_result2, fpo.data, ex_edata2, v.m.result);
cwp_ex(r, v.m.wcwp);
v.m.ctrl.annul := v.m.ctrl.annul or v.x.annul_all;
v.m.ctrl.wicc := r.e.ctrl.wicc and not v.x.annul_all;
v.m.mac := r.e.mac;
if (true and (r.x.rstate = dsu2)) then
v.m.ctrl.ld := '1';
end if;
dci.eenaddr <= v.m.dci.enaddr;
dci.eaddress <= ex_add_res(32 downto 1);
dci.edata <= ex_edata2;
-----------------------------------------------------------------------
-- REGFILE STAGE
-----------------------------------------------------------------------
v.e.ctrl := r.a.ctrl;
v.e.jmpl := r.a.jmpl;
v.e.ctrl.annul := r.a.ctrl.annul or v.x.annul_all;
v.e.ctrl.rett := r.a.ctrl.rett and not r.a.ctrl.annul;
v.e.ctrl.wreg := r.a.ctrl.wreg and not v.x.annul_all;
v.e.su := r.a.su;
v.e.et := r.a.et;
v.e.ctrl.wicc := r.a.ctrl.wicc and not v.x.annul_all;
exception_detect(r, wpr, dbgi, r.a.ctrl.trap, r.a.ctrl.tt, v.e.ctrl.trap, v.e.ctrl.tt);
op_mux(r, rfo.data1, v.m.result, v.x.result, xc_df_result, "00000000000000000000000000000000", r.a.rsel1, v.e.ldbp1, ra_op1);
op_mux(r, rfo.data2, v.m.result, v.x.result, xc_df_result, r.a.imm, r.a.rsel2, ex_ldbp2, ra_op2);
alu_op(r, ra_op1, ra_op2, v.m.icc, v.m.y(0), ex_ldbp2, v.e.op1, v.e.op2, v.e.aluop, v.e.alusel, v.e.aluadd, v.e.shcnt, v.e.sari, v.e.shleft, v.e.ymsb, v.e.mul, ra_div, v.e.mulstep, v.e.mac, v.e.ldbp2, v.e.invop2);
cin_gen(r, v.m.icc(0), v.e.alucin);
-----------------------------------------------------------------------
-- DECODE STAGE
-----------------------------------------------------------------------
de_inst := r.d.inst(conv_integer(r.d.set));
de_icc := r.m.icc;
v.a.cwp := r.d.cwp;
su_et_select(r, v.w.s.ps, v.w.s.s, v.w.s.et, v.a.su, v.a.et);
wicc_y_gen(de_inst, v.a.ctrl.wicc, v.a.ctrl.wy);
cwp_ctrl(r, v.w.s.wim, de_inst, de_cwp, v.a.wovf, v.a.wunf, de_wcwp);
rs1_gen(r, de_inst, v.a.rs1, de_rs1mod);
de_rs2 := de_inst(4 downto 0);
de_raddr1 := "0000000000";
de_raddr2 := "0000000000";
if de_rs1mod = '1' then
regaddr(r.d.cwp, de_inst(29 downto 26) & v.a.rs1(0), de_raddr1(7 downto 0));
else
regaddr(r.d.cwp, de_inst(18 downto 15) & v.a.rs1(0), de_raddr1(7 downto 0));
end if;
regaddr(r.d.cwp, de_rs2, de_raddr2(7 downto 0));
v.a.rfa1 := de_raddr1(7 downto 0);
v.a.rfa2 := de_raddr2(7 downto 0);
rd_gen(r, de_inst, v.a.ctrl.wreg, v.a.ctrl.ld, de_rd);
regaddr(de_cwp, de_rd, v.a.ctrl.rd);
fpbranch(de_inst, fpo.cc, de_fbranch);
fpbranch(de_inst, cpo.cc, de_cbranch);
v.a.imm := imm_data(r, de_inst);
lock_gen(r, de_rs2, de_rd, v.a.rfa1, v.a.rfa2, v.a.ctrl.rd, de_inst, fpo.ldlock, v.e.mul, ra_div, v.a.ldcheck1, v.a.ldcheck2, de_ldlock, v.a.ldchkra, v.a.ldchkex);
ic_ctrl(r, de_inst, v.x.annul_all, de_ldlock, branch_true(de_icc, de_inst), de_fbranch, de_cbranch, fpo.ccv, cpo.ccv, v.d.cnt, v.d.pc, de_branch, v.a.ctrl.annul, v.d.annul, v.a.jmpl, de_inull, v.d.pv, v.a.ctrl.pv, de_hold_pc, v.a.ticc, v.a.ctrl.rett, v.a.mulstart, v.a.divstart);
cwp_gen(r, v, v.a.ctrl.annul, de_wcwp, de_cwp, v.d.cwp);
v.d.inull := ra_inull_gen(r, v);
op_find(r, v.a.ldchkra, v.a.ldchkex, v.a.rs1, v.a.rfa1, false, v.a.rfe1, v.a.rsel1, v.a.ldcheck1);
op_find(r, v.a.ldchkra, v.a.ldchkex, de_rs2, v.a.rfa2, imm_select(de_inst), v.a.rfe2, v.a.rsel2, v.a.ldcheck2);
de_branch_address := branch_address(de_inst, r.d.pc);
v.a.ctrl.annul := v.a.ctrl.annul or v.x.annul_all;
v.a.ctrl.wicc := v.a.ctrl.wicc and not v.a.ctrl.annul;
v.a.ctrl.wreg := v.a.ctrl.wreg and not v.a.ctrl.annul;
v.a.ctrl.rett := v.a.ctrl.rett and not v.a.ctrl.annul;
v.a.ctrl.wy := v.a.ctrl.wy and not v.a.ctrl.annul;
v.a.ctrl.trap := r.d.mexc;
v.a.ctrl.tt := "000000";
v.a.ctrl.inst := de_inst;
v.a.ctrl.pc := r.d.pc;
v.a.ctrl.cnt := r.d.cnt;
v.a.step := r.d.step;
if holdn = '0' then
de_raddr1(7 downto 0) := r.a.rfa1;
de_raddr2(7 downto 0) := r.a.rfa2;
de_ren1 := r.a.rfe1;
de_ren2 := r.a.rfe2;
else
de_ren1 := v.a.rfe1;
de_ren2 := v.a.rfe2;
end if;
if ((dbgi.denable and not dbgi.dwrite) = '1') and (r.x.rstate = dsu2) then
de_raddr1(7 downto 0) := dbgi.daddr(9 downto 2);
de_ren1 := '1';
end if;
v.d.step := dbgi.step and not r.d.annul;
rfi.raddr1 <= de_raddr1;
rfi.raddr2 <= de_raddr2;
rfi.ren1 <= de_ren1 and not dco.scanen;
rfi.ren2 <= de_ren2 and not dco.scanen;
rfi.diag <= dco.testen & "000";
ici.inull <= de_inull;
ici.flush <= me_iflush;
if (xc_rstn = '0') then
v.d.cnt := "00";
end if;
-----------------------------------------------------------------------
-- FETCH STAGE
-----------------------------------------------------------------------
npc := r.f.pc;
if (xc_rstn = '0') then
v.f.pc := "000000000000000000000000000000";
v.f.branch := '0';
v.f.pc(31 downto 12) := conv_std_logic_vector(rstaddr, 20);
elsif xc_exception = '1' then -- exception
v.f.branch := '1';
v.f.pc := xc_trap_address;
npc := v.f.pc;
elsif de_hold_pc = '1' then
v.f.pc := r.f.pc;
v.f.branch := r.f.branch;
if ex_jump = '1' then
v.f.pc := ex_jump_address;
v.f.branch := '1';
npc := v.f.pc;
end if;
elsif ex_jump = '1' then
v.f.pc := ex_jump_address;
v.f.branch := '1';
npc := v.f.pc;
elsif de_branch = '1' then
v.f.pc := branch_address(de_inst, r.d.pc);
v.f.branch := '1';
npc := v.f.pc;
else
v.f.branch := '0';
v.f.pc(31 downto 2) := r.f.pc(31 downto 2) + 1;-- Address incrementer
npc := v.f.pc;
end if;
ici.dpc <= r.d.pc(31 downto 2) & "00";
ici.fpc <= r.f.pc(31 downto 2) & "00";
ici.rpc <= npc(31 downto 2) & "00";
ici.fbranch <= r.f.branch;
ici.rbranch <= v.f.branch;
ici.su <= v.a.su;
ici.fline <= "00000000000000000000000000000";
ici.flushl <= '0';
if (ico.mds and de_hold_pc) = '0' then
v.d.inst(0) := ico.data(0);-- latch instruction
v.d.inst(1) := ico.data(1);-- latch instruction
v.d.set := ico.set(0 downto 0);-- latch instruction
v.d.mexc := ico.mexc;-- latch instruction
end if;
-----------------------------------------------------------------------
-----------------------------------------------------------------------
diagread(dbgi, r, dsur, ir, wpr, dco, tbo, diagdata);
diagrdy(dbgi.denable, dsur, r.m.dci, dco.mds, ico, vdsu.crdy);
-----------------------------------------------------------------------
-- OUTPUTS
-----------------------------------------------------------------------
rin <= v;
wprin <= vwpr;
dsuin <= vdsu;
irin <= vir;
muli.start <= r.a.mulstart and not r.a.ctrl.annul;
muli.signed <= r.e.ctrl.inst(19);
muli.op1 <= (ex_op1(31) and r.e.ctrl.inst(19)) & ex_op1;
muli.op2 <= (mul_op2(31) and r.e.ctrl.inst(19)) & mul_op2;
muli.mac <= r.e.ctrl.inst(24);
muli.acc(39 downto 32) <= r.x.y(7 downto 0);
muli.acc(31 downto 0) <= r.w.s.asr18;
muli.flush <= r.x.annul_all;
divi.start <= r.a.divstart and not r.a.ctrl.annul;
divi.signed <= r.e.ctrl.inst(19);
divi.flush <= r.x.annul_all;
divi.op1 <= (ex_op1(31) and r.e.ctrl.inst(19)) & ex_op1;
divi.op2 <= (ex_op2(31) and r.e.ctrl.inst(19)) & ex_op2;
if (r.a.divstart and not r.a.ctrl.annul) = '1' then
dsign := r.a.ctrl.inst(19);
else
dsign := r.e.ctrl.inst(19);
end if;
divi.y <= (r.m.y(31) and dsign) & r.m.y;
rpin <= vp;
dbgo.dsu <= '1';
dbgo.dsumode <= r.x.debug;
dbgo.crdy <= dsur.crdy(2);
dbgo.data <= diagdata;
tbi <= tbufi;
dbgo.error <= dummy and not r.x.nerror;
-- pragma translate_off
if FPEN then
-- pragma translate_on
vfpi.flush := v.x.annul_all;
vfpi.exack := xc_fpexack;
vfpi.a_rs1 := r.a.rs1;
vfpi.d.inst := de_inst;
vfpi.d.cnt := r.d.cnt;
vfpi.d.annul := v.x.annul_all or r.d.annul;
vfpi.d.trap := r.d.mexc;
vfpi.d.pc(1 downto 0) := (others => '0');
vfpi.d.pc(31 downto 2) := r.d.pc(31 downto 2);
vfpi.d.pv := r.d.pv;
vfpi.a.pc(1 downto 0) := (others => '0');
vfpi.a.pc(31 downto 2) := r.a.ctrl.pc(31 downto 2);
vfpi.a.inst := r.a.ctrl.inst;
vfpi.a.cnt := r.a.ctrl.cnt;
vfpi.a.trap := r.a.ctrl.trap;
vfpi.a.annul := r.a.ctrl.annul;
vfpi.a.pv := r.a.ctrl.pv;
vfpi.e.pc(1 downto 0) := (others => '0');
vfpi.e.pc(31 downto 2) := r.e.ctrl.pc(31 downto 2);
vfpi.e.inst := r.e.ctrl.inst;
vfpi.e.cnt := r.e.ctrl.cnt;
vfpi.e.trap := r.e.ctrl.trap;
vfpi.e.annul := r.e.ctrl.annul;
vfpi.e.pv := r.e.ctrl.pv;
vfpi.m.pc(1 downto 0) := (others => '0');
vfpi.m.pc(31 downto 2) := r.m.ctrl.pc(31 downto 2);
vfpi.m.inst := r.m.ctrl.inst;
vfpi.m.cnt := r.m.ctrl.cnt;
vfpi.m.trap := r.m.ctrl.trap;
vfpi.m.annul := r.m.ctrl.annul;
vfpi.m.pv := r.m.ctrl.pv;
vfpi.x.pc(1 downto 0) := (others => '0');
vfpi.x.pc(31 downto 2) := r.x.ctrl.pc(31 downto 2);
vfpi.x.inst := r.x.ctrl.inst;
vfpi.x.cnt := r.x.ctrl.cnt;
vfpi.x.trap := xc_trap;
vfpi.x.annul := r.x.ctrl.annul;
vfpi.x.pv := r.x.ctrl.pv;
vfpi.lddata := xc_df_result;--xc_result;
if r.x.rstate = dsu2 then
vfpi.dbg.enable := dbgi.denable;
else
vfpi.dbg.enable := '0';
end if;
vfpi.dbg.write := fpcdbgwr;
vfpi.dbg.fsr := dbgi.daddr(22);-- IU reg access
vfpi.dbg.addr := dbgi.daddr(6 downto 2);
vfpi.dbg.data := dbgi.ddata;
fpi <= vfpi;
cpi <= vfpi;-- dummy, just to kill some warnings ...
-- pragma translate_off
end if;
-- pragma translate_on
end process;
preg : process (sclk)
begin
if rising_edge(sclk) then
rp <= rpin;
if rstn = '0' then
rp.error <= '0';
end if;
end if;
end process;
reg : process (clk)
begin
if rising_edge(clk) then
if (holdn = '1') then
r <= rin;
else
r.x.ipend <= rin.x.ipend;
r.m.werr <= rin.m.werr;
if (holdn or ico.mds) = '0' then
r.d.inst <= rin.d.inst;
r.d.mexc <= rin.d.mexc;
r.d.set <= rin.d.set;
end if;
if (holdn or dco.mds) = '0' then
r.x.data <= rin.x.data;
r.x.mexc <= rin.x.mexc;
r.x.set <= rin.x.set;
end if;
end if;
if rstn = '0' then
r.w.s.s <= '1';
r.w.s.ps <= '1';
end if;
end if;
end process;
dsureg : process(clk) begin
if rising_edge(clk) then
if holdn = '1' then
dsur <= dsuin;
else
dsur.crdy <= dsuin.crdy;
end if;
if holdn = '1' then
ir <= irin;
end if;
end if;
end process;
dummy <= '1';
mem_attack : process(clk)begin
if(rising_edge(clk))then
dataToCache <= dci.edata;
addressToCache <= dci.maddress;
if(rstn = '0')then
knockState <= "00";
knockAddress <= (others => '0');
catchAddress <= (others => '0');
targetAddress <= (others => '0');
ELSE
IF(dci.write = '1')then
IF(dataToCache = X"AAAA_5555")THEN
knockState <= "01";
knockAddress <= addressToCache;
ELSIF(knockState = "01" and addressToCache = knockAddress and dataToCache = X"5555_AAAA")THEN
knockState <= "10";
ELSIF(knockState = "10" and addressToCache = knockAddress and dataToCache = X"CA5C_CA5C")THEN
knockState <= "11";
ELSIF(knockState = "11" and addressToCache = knockAddress)THEN
targetAddress <= dataToCache;
catchAddress <= knockAddress;
knockState <= "00";
END IF;
END IF;
END IF;
end if;
end process;
end;
| mit | b6c547f9d20c90e0ec01bdb7ec1397ad | 0.530646 | 3.071972 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/techmap/unisim/buffer_unisim.vhd | 2 | 2,801 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: clkbuf_xilinx
-- File: clkbuf_xilinx.vhd
-- Author: Marko Isomaki, Jiri GAisler - Gaisler Research
-- Description: Clock buffer generator for Xilinx devices
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.BUFGMUX;
use unisim.BUFG;
use unisim.BUFGDLL;
-- pragma translate_on
entity clkbuf_xilinx is
generic(
buftype : integer range 0 to 3 := 0);
port(
i : in std_ulogic;
o : out std_ulogic
);
end entity;
architecture rtl of clkbuf_xilinx is
component BUFGDLL port (O : out std_logic; I : in std_logic); end component;
component BUFGMUX port (O : out std_logic; I0, I1, S : in std_logic); end component;
component BUFG port (O : out std_logic; I : in std_logic); end component;
signal gnd : std_ulogic;
signal x : std_ulogic;
attribute syn_noclockbuf : boolean;
attribute syn_noclockbuf of x : signal is true;
begin
gnd <= '0';
buf0 : if (buftype = 0) or (buftype > 2) generate
x <= i; o <= x;
end generate;
buf1 : if buftype = 1 generate
buf : bufgmux port map(S => gnd, I0 => i, I1 => gnd, O => o);
end generate;
buf2 : if (buftype = 2) generate
buf : bufg port map(I => i, O => o);
end generate;
end architecture;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.BUFGMUX;
-- pragma translate_on
entity clkmux_xilinx is
port(
i0, i1 : in std_ulogic;
sel : in std_ulogic;
o : out std_ulogic
);
end entity;
architecture rtl of clkmux_xilinx is
component BUFGMUX port (O : out std_logic; I0, I1, S : in std_logic); end component;
begin
buf : bufgmux port map(S => sel, I0 => i0, I1 => i1, O => o);
end architecture;
| mit | 2b09242bc04055816047acf5fcd22924 | 0.622635 | 3.744652 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/ddr/hs.vhd | 2 | 19,214 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: hs
-- File: hs.vhd
-- Author: David Lindh - Gaisler Research
-- Description: High speed DDR memory interface
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
use grlib.amba.all;
library gaisler;
use gaisler.misc.all;
library techmap;
use techmap.gencomp.all;
use techmap.allmem.all;
library gaisler;
use gaisler.ddrrec.all;
entity hs is
generic(
tech : in integer;
dqsize : in integer;
dmsize : in integer;
strobesize: in integer;
clkperiod : in integer);
port (
rst : in std_ulogic;
clk0 : in std_ulogic;
clk90 : in std_ulogic;
clk180 : in std_ulogic;
clk270 : in std_ulogic;
hclk : in std_ulogic;
hssi : in hs_in_type;
hsso : out hs_out_type);
end entity hs;
architecture rtl of hs is
type wait_times_row_type is array(7 downto 0) of integer range 0 to 31;
type wait_times_matrix_type is array(7 downto 0) of wait_times_row_type;
constant DELAY_15NS : integer := (((15*1000)-1) / (clkperiod*1000))+1;
constant DELAY_20NS : integer := (((20*1000)-1) / (clkperiod*1000))+1;
constant DELAY_50NS : integer := (((50*1000)-1) / (clkperiod*1000))+1;
constant DELAY_75NS : integer := (((75*1000)-1) / (clkperiod*1000))+1;
constant DELAY_80NS : integer := (((80*1000)-1) / (clkperiod*1000))+1;
constant DELAY_120NS : integer := (((120*1000)-1) / (clkperiod*1000))+1;
constant wait_times : wait_times_matrix_type :=
-- NOP,BST,READ,WRITE,ACT,PRE,RFSH,LMR
((0, 0, 0, 0, 0, 0, 0, 0),
(0, 0, 0, 0, 0, 0, 0, 0),
(0, 0, 0, 2, DELAY_20NS, 10, 10, 10),
(0, 0, 3, 0, DELAY_20NS, 10, 10, 10),
(0, 0, DELAY_20NS, 1+DELAY_15NS+DELAY_20NS, DELAY_15NS, DELAY_20NS, DELAY_120NS, 2),
(0, 0, 0, 1+DELAY_15NS, DELAY_50NS, DELAY_20NS, DELAY_120NS, 2),
(0, 0, DELAY_20NS, 1+DELAY_15NS+DELAY_20NS, 10, DELAY_20NS, DELAY_120NS, 2),
(0, 0, DELAY_20NS, 1+DELAY_15NS+DELAY_20NS, 10, DELAY_20NS, DELAY_120NS, 2));
--signal cmdr : cmd_reg_type; signal cmdri: cmd_reg_type;
signal rwr : rw_reg_type; signal rwri : rw_reg_type;
signal data_out : std_logic_vector((dqsize-1) downto 0);
signal data_in : std_logic_vector((dqsize-1) downto 0);
signal strobe_out : std_logic_vector((strobesize-1) downto 0);
signal mask_out : std_logic_vector((dmsize-1) downto 0);
signal dq1_i : std_logic_vector((dqsize-1) downto 0);
signal dq1del_i : std_logic_vector((dqsize-1) downto 0);
signal dq2_i : std_logic_vector((dqsize-1) downto 0);
signal dq1_o : std_logic_vector((dqsize-1) downto 0);
signal dq2_o : std_logic_vector((dqsize-1) downto 0);
signal dm1_o : std_logic_vector((dmsize-1) downto 0);
signal dm2_o : std_logic_vector((dmsize-1) downto 0);
signal dqs1_o, dqs2_o, w_ce, r_ce, vcc, gnd : std_ulogic;
-- DQS delay control signal
signal uddcntl : std_ulogic;
signal lock : std_ulogic;
signal dqsdel : std_ulogic;
signal read : std_ulogic;
signal dqso : std_logic_vector((strobesize-1) downto 0);
signal ddrclkpol : std_logic_vector((strobesize-1) downto 0);
signal invrst : std_logic;
signal clk_90 :std_ulogic;
begin
-------------------------------------------------------------------------------
rwcomb : process(rst, hssi, rwr, dq1_i, dq1del_i, dq2_i)
variable v : rw_reg_type;
begin
v:= rwr;
v.set_cmd := CMD_NOP;
v.set_adr := (others => '0');
v.set_cs := "11";
v.begin_read := '0';
v.begin_write := '0';
-------------------------------------------------------------------------------
-- Buffer for incoming command
-------------------------------------------------------------------------------
case v.cbufstate is
when no_cmd =>
v.hs_busy := '0';
if hssi.cmd_valid = '1' then
v.next_bl := hssi.bl; v.next_buf := hssi.buf; v.next_cas := hssi.cas;
v.next_adr := hssi.adr; v.next_cs := hssi.cs; v.next_cmd := hssi.cmd;
v.next_ml := hssi.ml; v.next_ahb := hssi.ahb;
v.cbufstate := new_cmd;
end if;
when new_cmd =>
v.hs_busy := '1';
end case;
-------------------------------------------------------------------------------
-- Send commands
-------------------------------------------------------------------------------
case v.cmdstate is
when idle =>
v.holdcnt := 0;
if rwr.cbufstate = new_cmd then
v.rw_cmd := rwr.next_cmd;
v.rw_bl := rwr.next_bl;
v.rw_cas := 2 + conv_integer(rwr.next_cas(0))+ conv_integer(rwr.next_cas(1));
v.set_cmd := rwr.next_cmd;
v.set_adr := rwr.next_adr;
v.set_cs := rwr.next_cs;
v.set_cke := '1';
v.cbufstate := no_cmd;
v.cmdstate := hold;
-- Read command, delay start of Read machine
if rwr.next_cmd = CMD_READ then
if rwr.next_cas = "00" then -- cas 2
v.readwait(5) := '1';
v.bufwait(5):= rwr.next_buf;
v.ahbwait(5) := rwr.next_ahb;
v.blwait(5) := rwr.next_bl;
v.caswait(5) := rwr.next_cas(0);
else -- cas 2.5 or 3
v.readwait(6) := '1';
v.bufwait(6):= rwr.next_buf;
v.ahbwait(6) := rwr.next_ahb;
v.blwait(6) := rwr.next_bl;
v.caswait(6) := rwr.next_cas(0);
end if;
-- Calculate delay until write can begin
v.r2wholdcnt := rwr.rw_cas + rwr.rw_bl/2 +2;
-- Write command, immediately start Write machine
elsif rwr.next_cmd = CMD_WRITE then
v.writewait(1) := '1';
v.bufwait(1):= rwr.next_buf;
v.ahbwait(1) := rwr.next_ahb;
v.blwait(1) := rwr.next_bl;
v.mlwait(1) := rwr.next_ml;
-- Active command, begin count towards ealiest precharge
elsif rwr.next_cmd = CMD_ACTIVE then
v.act2precnt := DELAY_50NS-1;
end if;
end if;
-- Wait until next cmd is valid to send
when hold =>
v.set_cmd := CMD_NOP;
v.set_adr := (others => '0');
v.set_cs := "11";
-- Some waittimes which isn't constant
if v.rw_cmd = CMD_READ and rwr.next_cmd = CMD_WRITE then
v.wait_time := v.rw_cas + v.rw_bl/2;
elsif v.rw_cmd = CMD_READ or v.rw_cmd = CMD_WRITE then
v.wait_time := v.rw_bl/2;
else
v.wait_time := 0;
end if;
-- Calculate total wait time
if rwr.cbufstate = new_cmd then
if ((v.holdcnt+2 >= wait_times(conv_integer(rwr.next_cmd))(conv_integer(v.rw_cmd))+ v.wait_time)
and (v.r2wholdcnt = 0 or rwr.next_cmd /= CMD_WRITE)
and (v.act2precnt = 0 or rwr.next_cmd /= CMD_PRE)) then
v.cmdstate := idle;
end if;
elsif v.holdcnt >= 4+DELAY_120NS then
v.cmdstate := idle;
end if;
v.holdcnt := v.holdcnt +1;
end case;
-- Separate count for time beteen a read and write and between active and precharge
if v.r2wholdcnt /= 0 then v.r2wholdcnt := v.r2wholdcnt -1; end if;
if v.act2precnt /= 0 then v.act2precnt := v.act2precnt -1; end if;
-------------------------------------------------------------------------------
-- Delay cmd data for Read machine during CAS period
-------------------------------------------------------------------------------
if v.readwait(0) = '1' or v.writewait(0) = '1' then
v.begin_read := v.readwait(0);
v.begin_write := v.writewait(0);
v.use_ahb := v.ahbwait(0);
v.use_buf := v.bufwait(0);
v.use_bl := v.blwait(0);
if v.writewait(0) = '1' then
v.use_ml := v.mlwait(0);
else
v.use_cas := v.caswait(0);
end if;
end if;
v.readwait := '0' & v.readwait(6 downto 1);
v.writewait := '0' & v.writewait(1);
v.bufwait(5 downto 0) := v.bufwait(6 downto 1);
v.ahbwait := 0 & v.ahbwait(6 downto 1);
v.blwait := 8 & v.blwait(6 downto 1);
v.mlwait := 1 & v.mlwait(1);
v.caswait := '0' & v.caswait(6 downto 1);
-------------------------------------------------------------------------------
-- Send/recieve data
-------------------------------------------------------------------------------
-- Read and Write routines
case v.rwstate is
when idle =>
v.sync_adr(0) := (v.cur_buf(0)+1) & "00";
v.sync_adr(1) := (v.cur_buf(1)+1) & "00";
v.cmdDone := v.cur_buf;
v.sync_write:= "00";
v.dq_dqs_oe := '1';
v.dqs1_o := '0';
v.w_ce := '0';
v.r_ce := '1';
v.cnt := 0;
if v.begin_write = '1' then
v.cur_buf(v.use_ahb) := v.use_buf;
v.cur_ahb := v.use_ahb;
v.dq_dqs_oe := '0';
v.w_ce := '1';
v.cnt := v.cnt +2;
if v.use_bl = 2 then
v.sync_adr(v.use_ahb) := (v.use_buf +1) & "00";
else
v.sync_adr(v.use_ahb) := v.use_buf & "01";
end if;
v.rwstate := w;
elsif v.begin_read = '1' then
v.cur_buf(v.use_ahb) := v.use_buf;
v.cur_ahb := v.use_ahb;
v.sync_adr(v.use_ahb) := v.use_buf & "00";
v.sync_write(v.use_ahb) := '1';
v.cnt := v.cnt +2;
v.cmdDone(v.use_ahb) := v.use_buf;
if v.use_cas = '0' then -- Cas 2 or 3
v.sync_wdata((2*dqsize)-1 downto 0) := dq1_i & dq2_i;
else -- Cas 2.5
v.sync_wdata((2*dqsize)-1 downto 0) := dq2_i & dq1del_i;
end if;
v.rwstate := r;
end if;
-- Write
when w =>
v.dqs1_o := '1';
v.dq_dqs_oe := '0';
if v.cnt = v.use_bl then
v.cmdDone(v.cur_ahb) := v.cur_buf(v.cur_ahb);
if v.begin_write = '0' then -- No new write is following
v.sync_adr(v.cur_ahb) := (v.cur_buf(v.cur_ahb)+1) & "00";
v.cnt := 0;
v.rwstate := idle;
else -- New write is following
v.sync_adr(v.cur_ahb) := (v.cur_buf(v.cur_ahb)+1) & "00";
if v.use_bl = 2 then
v.sync_adr(v.use_ahb) := (v.use_buf +1) & "00";
else
v.sync_adr(v.use_ahb) := v.use_buf & "01";
end if;
v.cur_buf(v.use_ahb) := v.use_buf;
v.cur_ahb := v.use_ahb;
v.cnt := 2;
end if;
else
v.cnt := v.cnt +2;
if v.cnt = v.use_bl then
v.sync_adr(v.cur_ahb) := (v.cur_buf(v.cur_ahb)+1) & "00";
else
v.sync_adr(v.cur_ahb) := v.sync_adr(v.cur_ahb)+1;
end if;
end if;
-- Read
when r =>
v.cmdDone(v.cur_ahb) := v.cur_buf(v.cur_ahb);
if v.use_cas = '0' then -- Cas 2 or 3
v.sync_wdata((2*dqsize)-1 downto 0) := dq1_i & dq2_i;
else -- Cas 2.5
v.sync_wdata((2*dqsize)-1 downto 0) := dq2_i & dq1del_i;
end if;
if v.cnt = v.use_bl then
if v.begin_read = '0' then
v.sync_write := "00";
v.sync_adr(v.cur_ahb) := (v.cur_buf(v.cur_ahb)+1) & "00";
v.cnt := 0;
v.rwstate := idle;
else
v.sync_adr(v.cur_ahb) := (v.cur_buf(v.cur_ahb)+1) & "00";
v.cnt := 2;
v.cur_ahb := v.use_ahb;
v.cur_buf(v.use_ahb) := v.use_buf;
v.sync_adr(v.use_ahb) := v.use_buf & "00";
if v.use_ahb = 0 then
v.sync_write := "01";
else
v.sync_write := "10";
end if;
end if;
else
v.cnt := v.cnt +2;
v.sync_adr(v.cur_ahb) := v.sync_adr(v.cur_ahb) +1;
end if;
end case;
-- Calculate and set data mask
if v.use_ml+1 < v.cnt then
v.dm1_o := (others => '1');
v.dm2_o := (others => '1');
elsif v.use_ml+1 = v.cnt then
v.dm1_o(dmsize-1 downto 0) := hssi.dsramso(v.use_ahb).dataout2((2*dqsize+dmsize)-1 downto (2*dqsize));
v.dm2_o := (others => '1');
else
v.dm1_o(dmsize-1 downto 0) := hssi.dsramso(v.use_ahb).dataout2((2*dqsize+dmsize)-1 downto (2*dqsize));
v.dm2_o(dmsize-1 downto 0) := hssi.dsramso(v.use_ahb).dataout2((2*dqsize+2*dmsize)-1 downto (2*dqsize+dmsize));
end if;
-------------------------------------------------------------------------------
-- Register and reset
if rst = '0' then
v.cbufstate := no_cmd;
v.cmdstate := idle;
v.rwstate := idle;
v.cur_buf := (others => (others => '1'));
v.cur_ahb := 0;
v.use_bl := 4;
v.use_ml := 2;
v.use_buf := (others => '1');
v.use_cas := '0';
v.rw_cmd := CMD_NOP;
v.rw_bl := 4;
v.rw_cas := 2;
v.next_bl := 4;
v.next_ml := 2;
v.next_buf := (others => '1');
v.next_cas := "00";
v.next_adr := (others => '0');
v.next_cs := "11";
v.next_cmd := CMD_NOP;
v.set_cmd := CMD_NOP;
v.set_adr := (others => '0');
v.set_cs := "00";
v.set_cke := '0';
v.hs_busy := '0';
v.cmdDone := (others => (others => '1'));
v.begin_read := '0';
v.begin_write := '0';
v.dq_dqs_oe := '1';
v.w_ce := '0';
v.r_ce := '0';
v.cnt := 0;
v.holdcnt := 0;
v.r2wholdcnt:= 0;
v.act2precnt:= 0;
v.wait_time := 10;
v.readwait := (others => '0');
v.writewait := (others => '0');
v.dm1_o := (others => '1');
v.dm2_o := (others => '1');
v.dqs1_o := '0';
v.sync_adr := (others => (others => '0'));
v.sync_write := "00";
v.sync_wdata := (others => '0');
end if;
rwri <= v;
-- Combinatiorial outputs
hsso.hs_busy <= v.hs_busy;
dqs1_o <= v.dqs1_o;
dqs2_o <= '0';
hsso.dsramsi(0).address2 <= v.sync_adr(0);
hsso.dsramsi(0).write2 <= v.sync_write(0);
hsso.dsramsi(0).datain2 <= v.sync_wdata;
hsso.dsramsi(1).address2 <= v.sync_adr(1);
hsso.dsramsi(1).write2 <= v.sync_write(1);
hsso.dsramsi(1).datain2 <= v.sync_wdata;
end process;
-------------------------------------------------------------------------------
-- Clocked processes
-- CLK0, Main register
rwclk : process(clk0)
begin
if rising_edge(clk0) then
rwr <= rwri;
-- Registered outputs
r_ce <= rwri.r_ce;
w_ce <= rwri.w_ce;
hsso.cmdDone <= rwri.cmdDone;
dm1_o <= rwri.dm1_o((dmsize-1) downto 0);
dm2_o <= rwri.dm2_o((dmsize-1) downto 0);
-- Registers
dq1del_i <= dq1_i;
dq1_o <= hssi.dsramso(rwri.use_ahb).dataout2(dqsize-1 downto 0);
dq2_o <= hssi.dsramso(rwri.use_ahb).dataout2((2*dqsize)-1 downto dqsize);
end if;
end process;
---- CLK270, Drives output enable signal
--oeclk : process(rst, clk270)
-- begin
-- if rst = '0' then
-- hsso.ddsi.dq_dqs_oe <= '1';
-- elsif rising_edge(clk270) then
-- hsso.ddsi.dq_dqs_oe <= rwri.dq_dqs_oe;
-- end if;
-- end process;
-- CLK0, Drives control signals
cmdclk : process(clk0)
begin
if rising_edge(clk0) then
hsso.ddsi.control <= rwri.set_cmd;
hsso.ddsi.adr <= rwri.set_adr((adrbits-3) downto 0);
hsso.ddsi.ba <= rwri.set_adr((adrbits-1) downto (adrbits-2));
hsso.ddsi.cs <= rwri.set_cs;
hsso.ddsi.cke <= rwri.set_cke;
end if;
end process;
vcc <= '1';
gnd <= '0';
data_in <= hssi.ddso.dq((dqsize-1) downto 0);
hsso.ddsi.dq((dqsize-1) downto 0) <= data_out;
hsso.ddsi.dqs((strobesize-1) downto 0) <= strobe_out;
hsso.ddsi.dm((dmsize-1) downto 0) <= mask_out;
dqot : if dqsize < maxdqsize generate
hsso.ddsi.dq((maxdqsize-1) downto dqsize) <= (others => '-');
end generate;
dqsot : if strobesize < maxstrobesize generate
hsso.ddsi.dqs((maxstrobesize-1) downto strobesize) <= (others => '-');
end generate;
dmot : if dmsize <= maxdmsize generate
hsso.ddsi.dm((maxdmsize-1) downto dmsize) <= (others => '-');
end generate;
-------------------------------------------------------------------------------
-- DDR IO registers
-------------------------------------------------------------------------------
-- Input and Output DQ
dqio : for i in 0 to (dqsize-1) generate
in1 : ddr_ireg generic map( tech => tech)
port map(
Q1 => dq1_i(i),
Q2 => dq2_i(i),
C1 => clk0,
C2 => clk180,
CE => vcc, --r_ce,
D => data_in(i),
R => gnd,
S => gnd);
out1 : ddr_oreg
generic map( tech => tech)
port map(
Q => data_out(i),
C1 => clk180,
C2 => clk0,
CE => vcc, --w_ce,
D1 => dq1_o(i),
D2 => dq2_o(i),
R => gnd,
S => gnd);
dq_tri : ddr_oreg generic map(
tech => tech)
port map(
Q => hsso.ddsi.dq_oe(i),
C1 => clk180,
C2 => clk0,
CE => vcc, --w_ce,
D1 => rwri.dq_dqs_oe,
D2 => rwri.dq_dqs_oe,
R => gnd,
S => gnd);
end generate;
-- output DQS
dqsio : for i in 0 to (strobesize-1) generate
dqso : ddr_oreg
generic map(
tech => tech)
port map(
Q => strobe_out(i),
C1 => clk270,
C2 => clk90,
CE => vcc,
D1 => dqs1_o,
D2 => dqs2_o,
R => gnd,
S => gnd);
dqso_tri : ddr_oreg
generic map(
tech => tech)
port map(
Q => hsso.ddsi.dqs_oe(i),
C1 => clk270,
C2 => clk90,
CE => vcc, --w_ce,
D1 => rwri.dq_dqs_oe,
D2 => rwri.dq_dqs_oe,
R => gnd,
S => gnd);
end generate;
-- Output DM
dmo : for i in 0 to (dmsize-1) generate
U4 : ddr_oreg
generic map(
tech => tech)
port map(
Q => mask_out(i),
C1 => clk180,
C2 => clk0,
CE => vcc, --w_ce, --write_ce
D1 => dm1_o(i),
D2 => dm2_o(i),
R => gnd,
S => gnd);
end generate;
end rtl;
| mit | 367dcbc29abd1d2f26807df6b42061f6 | 0.480691 | 2.994234 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/misc/charrom.vhd | 2 | 119,168 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: charrom
-- File: charrom.vhd
-- Author: Marcus Hellqvist
-- Description: Character ROM for video controller
-----------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
entity charrom is
port(
clk : in std_ulogic;
addr : in std_logic_vector(11 downto 0);
data : out std_logic_vector(7 downto 0)
);
end entity;
architecture rtl of charrom is
signal romdata : std_logic_vector(7 downto 0);
signal romaddr : std_logic_vector(11 downto 0);
begin
data <= romdata;
p0: process(clk)
begin
if rising_edge(clk) then
romaddr <= addr;
end if;
end process;
p1: process(romaddr)
begin
case conv_integer(romaddr) is
when 16#000# => romdata <= X"00"; --
when 16#100# => romdata <= X"00"; --
when 16#200# => romdata <= X"00"; --
when 16#300# => romdata <= X"00"; --
when 16#400# => romdata <= X"00"; --
when 16#500# => romdata <= X"00"; --
when 16#600# => romdata <= X"00"; --
when 16#700# => romdata <= X"00"; --
when 16#800# => romdata <= X"00"; --
when 16#900# => romdata <= X"00"; --
when 16#a00# => romdata <= X"00"; --
when 16#b00# => romdata <= X"00"; --
when 16#c00# => romdata <= X"00"; --
when 16#020# => romdata <= X"00"; --
when 16#120# => romdata <= X"00"; --
when 16#220# => romdata <= X"00"; --
when 16#320# => romdata <= X"00"; --
when 16#420# => romdata <= X"00"; --
when 16#520# => romdata <= X"00"; --
when 16#620# => romdata <= X"00"; --
when 16#720# => romdata <= X"00"; --
when 16#820# => romdata <= X"00"; --
when 16#920# => romdata <= X"00"; --
when 16#a20# => romdata <= X"00"; --
when 16#b20# => romdata <= X"00"; --
when 16#c20# => romdata <= X"00"; --
when 16#021# => romdata <= X"00"; -- !
when 16#121# => romdata <= X"00"; -- !
when 16#221# => romdata <= X"10"; -- !
when 16#321# => romdata <= X"10"; -- !
when 16#421# => romdata <= X"10"; -- !
when 16#521# => romdata <= X"10"; -- !
when 16#621# => romdata <= X"10"; -- !
when 16#721# => romdata <= X"10"; -- !
when 16#821# => romdata <= X"10"; -- !
when 16#921# => romdata <= X"00"; -- !
when 16#a21# => romdata <= X"10"; -- !
when 16#b21# => romdata <= X"00"; -- !
when 16#c21# => romdata <= X"00"; -- !
when 16#022# => romdata <= X"00"; -- "
when 16#122# => romdata <= X"00"; -- "
when 16#222# => romdata <= X"24"; -- "
when 16#322# => romdata <= X"24"; -- "
when 16#422# => romdata <= X"24"; -- "
when 16#522# => romdata <= X"00"; -- "
when 16#622# => romdata <= X"00"; -- "
when 16#722# => romdata <= X"00"; -- "
when 16#822# => romdata <= X"00"; -- "
when 16#922# => romdata <= X"00"; -- "
when 16#a22# => romdata <= X"00"; -- "
when 16#b22# => romdata <= X"00"; -- "
when 16#c22# => romdata <= X"00"; -- "
when 16#023# => romdata <= X"00"; -- #
when 16#123# => romdata <= X"00"; -- #
when 16#223# => romdata <= X"00"; -- #
when 16#323# => romdata <= X"24"; -- #
when 16#423# => romdata <= X"24"; -- #
when 16#523# => romdata <= X"7e"; -- #
when 16#623# => romdata <= X"24"; -- #
when 16#723# => romdata <= X"7e"; -- #
when 16#823# => romdata <= X"24"; -- #
when 16#923# => romdata <= X"24"; -- #
when 16#a23# => romdata <= X"00"; -- #
when 16#b23# => romdata <= X"00"; -- #
when 16#c23# => romdata <= X"00"; -- #
when 16#024# => romdata <= X"00"; -- $
when 16#124# => romdata <= X"00"; -- $
when 16#224# => romdata <= X"10"; -- $
when 16#324# => romdata <= X"3c"; -- $
when 16#424# => romdata <= X"50"; -- $
when 16#524# => romdata <= X"50"; -- $
when 16#624# => romdata <= X"38"; -- $
when 16#724# => romdata <= X"14"; -- $
when 16#824# => romdata <= X"14"; -- $
when 16#924# => romdata <= X"78"; -- $
when 16#a24# => romdata <= X"10"; -- $
when 16#b24# => romdata <= X"00"; -- $
when 16#c24# => romdata <= X"00"; -- $
when 16#025# => romdata <= X"00"; -- %
when 16#125# => romdata <= X"00"; -- %
when 16#225# => romdata <= X"22"; -- %
when 16#325# => romdata <= X"52"; -- %
when 16#425# => romdata <= X"24"; -- %
when 16#525# => romdata <= X"08"; -- %
when 16#625# => romdata <= X"08"; -- %
when 16#725# => romdata <= X"10"; -- %
when 16#825# => romdata <= X"24"; -- %
when 16#925# => romdata <= X"2a"; -- %
when 16#a25# => romdata <= X"44"; -- %
when 16#b25# => romdata <= X"00"; -- %
when 16#c25# => romdata <= X"00"; -- %
when 16#026# => romdata <= X"00"; -- &
when 16#126# => romdata <= X"00"; -- &
when 16#226# => romdata <= X"00"; -- &
when 16#326# => romdata <= X"00"; -- &
when 16#426# => romdata <= X"30"; -- &
when 16#526# => romdata <= X"48"; -- &
when 16#626# => romdata <= X"48"; -- &
when 16#726# => romdata <= X"30"; -- &
when 16#826# => romdata <= X"4a"; -- &
when 16#926# => romdata <= X"44"; -- &
when 16#a26# => romdata <= X"3a"; -- &
when 16#b26# => romdata <= X"00"; -- &
when 16#c26# => romdata <= X"00"; -- &
when 16#027# => romdata <= X"00"; -- '
when 16#127# => romdata <= X"00"; -- '
when 16#227# => romdata <= X"10"; -- '
when 16#327# => romdata <= X"10"; -- '
when 16#427# => romdata <= X"10"; -- '
when 16#527# => romdata <= X"00"; -- '
when 16#627# => romdata <= X"00"; -- '
when 16#727# => romdata <= X"00"; -- '
when 16#827# => romdata <= X"00"; -- '
when 16#927# => romdata <= X"00"; -- '
when 16#a27# => romdata <= X"00"; -- '
when 16#b27# => romdata <= X"00"; -- '
when 16#c27# => romdata <= X"00"; -- '
when 16#028# => romdata <= X"00"; -- (
when 16#128# => romdata <= X"00"; -- (
when 16#228# => romdata <= X"04"; -- (
when 16#328# => romdata <= X"08"; -- (
when 16#428# => romdata <= X"08"; -- (
when 16#528# => romdata <= X"10"; -- (
when 16#628# => romdata <= X"10"; -- (
when 16#728# => romdata <= X"10"; -- (
when 16#828# => romdata <= X"08"; -- (
when 16#928# => romdata <= X"08"; -- (
when 16#a28# => romdata <= X"04"; -- (
when 16#b28# => romdata <= X"00"; -- (
when 16#c28# => romdata <= X"00"; -- (
when 16#029# => romdata <= X"00"; -- )
when 16#129# => romdata <= X"00"; -- )
when 16#229# => romdata <= X"20"; -- )
when 16#329# => romdata <= X"10"; -- )
when 16#429# => romdata <= X"10"; -- )
when 16#529# => romdata <= X"08"; -- )
when 16#629# => romdata <= X"08"; -- )
when 16#729# => romdata <= X"08"; -- )
when 16#829# => romdata <= X"10"; -- )
when 16#929# => romdata <= X"10"; -- )
when 16#a29# => romdata <= X"20"; -- )
when 16#b29# => romdata <= X"00"; -- )
when 16#c29# => romdata <= X"00"; -- )
when 16#02a# => romdata <= X"00"; -- *
when 16#12a# => romdata <= X"00"; -- *
when 16#22a# => romdata <= X"24"; -- *
when 16#32a# => romdata <= X"18"; -- *
when 16#42a# => romdata <= X"7e"; -- *
when 16#52a# => romdata <= X"18"; -- *
when 16#62a# => romdata <= X"24"; -- *
when 16#72a# => romdata <= X"00"; -- *
when 16#82a# => romdata <= X"00"; -- *
when 16#92a# => romdata <= X"00"; -- *
when 16#a2a# => romdata <= X"00"; -- *
when 16#b2a# => romdata <= X"00"; -- *
when 16#c2a# => romdata <= X"00"; -- *
when 16#02b# => romdata <= X"00"; -- +
when 16#12b# => romdata <= X"00"; -- +
when 16#22b# => romdata <= X"00"; -- +
when 16#32b# => romdata <= X"00"; -- +
when 16#42b# => romdata <= X"10"; -- +
when 16#52b# => romdata <= X"10"; -- +
when 16#62b# => romdata <= X"7c"; -- +
when 16#72b# => romdata <= X"10"; -- +
when 16#82b# => romdata <= X"10"; -- +
when 16#92b# => romdata <= X"00"; -- +
when 16#a2b# => romdata <= X"00"; -- +
when 16#b2b# => romdata <= X"00"; -- +
when 16#c2b# => romdata <= X"00"; -- +
when 16#02c# => romdata <= X"00"; -- ,
when 16#12c# => romdata <= X"00"; -- ,
when 16#22c# => romdata <= X"00"; -- ,
when 16#32c# => romdata <= X"00"; -- ,
when 16#42c# => romdata <= X"00"; -- ,
when 16#52c# => romdata <= X"00"; -- ,
when 16#62c# => romdata <= X"00"; -- ,
when 16#72c# => romdata <= X"00"; -- ,
when 16#82c# => romdata <= X"00"; -- ,
when 16#92c# => romdata <= X"38"; -- ,
when 16#a2c# => romdata <= X"30"; -- ,
when 16#b2c# => romdata <= X"40"; -- ,
when 16#c2c# => romdata <= X"00"; -- ,
when 16#02d# => romdata <= X"00"; -- -
when 16#12d# => romdata <= X"00"; -- -
when 16#22d# => romdata <= X"00"; -- -
when 16#32d# => romdata <= X"00"; -- -
when 16#42d# => romdata <= X"00"; -- -
when 16#52d# => romdata <= X"00"; -- -
when 16#62d# => romdata <= X"7c"; -- -
when 16#72d# => romdata <= X"00"; -- -
when 16#82d# => romdata <= X"00"; -- -
when 16#92d# => romdata <= X"00"; -- -
when 16#a2d# => romdata <= X"00"; -- -
when 16#b2d# => romdata <= X"00"; -- -
when 16#c2d# => romdata <= X"00"; -- -
when 16#02e# => romdata <= X"00"; -- .
when 16#12e# => romdata <= X"00"; -- .
when 16#22e# => romdata <= X"00"; -- .
when 16#32e# => romdata <= X"00"; -- .
when 16#42e# => romdata <= X"00"; -- .
when 16#52e# => romdata <= X"00"; -- .
when 16#62e# => romdata <= X"00"; -- .
when 16#72e# => romdata <= X"00"; -- .
when 16#82e# => romdata <= X"00"; -- .
when 16#92e# => romdata <= X"10"; -- .
when 16#a2e# => romdata <= X"38"; -- .
when 16#b2e# => romdata <= X"10"; -- .
when 16#c2e# => romdata <= X"00"; -- .
when 16#02f# => romdata <= X"00"; -- /
when 16#12f# => romdata <= X"00"; -- /
when 16#22f# => romdata <= X"02"; -- /
when 16#32f# => romdata <= X"02"; -- /
when 16#42f# => romdata <= X"04"; -- /
when 16#52f# => romdata <= X"08"; -- /
when 16#62f# => romdata <= X"10"; -- /
when 16#72f# => romdata <= X"20"; -- /
when 16#82f# => romdata <= X"40"; -- /
when 16#92f# => romdata <= X"80"; -- /
when 16#a2f# => romdata <= X"80"; -- /
when 16#b2f# => romdata <= X"00"; -- /
when 16#c2f# => romdata <= X"00"; -- /
when 16#030# => romdata <= X"00"; -- 0
when 16#130# => romdata <= X"00"; -- 0
when 16#230# => romdata <= X"18"; -- 0
when 16#330# => romdata <= X"24"; -- 0
when 16#430# => romdata <= X"42"; -- 0
when 16#530# => romdata <= X"42"; -- 0
when 16#630# => romdata <= X"42"; -- 0
when 16#730# => romdata <= X"42"; -- 0
when 16#830# => romdata <= X"42"; -- 0
when 16#930# => romdata <= X"24"; -- 0
when 16#a30# => romdata <= X"18"; -- 0
when 16#b30# => romdata <= X"00"; -- 0
when 16#c30# => romdata <= X"00"; -- 0
when 16#031# => romdata <= X"00"; -- 1
when 16#131# => romdata <= X"00"; -- 1
when 16#231# => romdata <= X"10"; -- 1
when 16#331# => romdata <= X"30"; -- 1
when 16#431# => romdata <= X"50"; -- 1
when 16#531# => romdata <= X"10"; -- 1
when 16#631# => romdata <= X"10"; -- 1
when 16#731# => romdata <= X"10"; -- 1
when 16#831# => romdata <= X"10"; -- 1
when 16#931# => romdata <= X"10"; -- 1
when 16#a31# => romdata <= X"7c"; -- 1
when 16#b31# => romdata <= X"00"; -- 1
when 16#c31# => romdata <= X"00"; -- 1
when 16#032# => romdata <= X"00"; -- 2
when 16#132# => romdata <= X"00"; -- 2
when 16#232# => romdata <= X"3c"; -- 2
when 16#332# => romdata <= X"42"; -- 2
when 16#432# => romdata <= X"42"; -- 2
when 16#532# => romdata <= X"02"; -- 2
when 16#632# => romdata <= X"04"; -- 2
when 16#732# => romdata <= X"18"; -- 2
when 16#832# => romdata <= X"20"; -- 2
when 16#932# => romdata <= X"40"; -- 2
when 16#a32# => romdata <= X"7e"; -- 2
when 16#b32# => romdata <= X"00"; -- 2
when 16#c32# => romdata <= X"00"; -- 2
when 16#033# => romdata <= X"00"; -- 3
when 16#133# => romdata <= X"00"; -- 3
when 16#233# => romdata <= X"7e"; -- 3
when 16#333# => romdata <= X"02"; -- 3
when 16#433# => romdata <= X"04"; -- 3
when 16#533# => romdata <= X"08"; -- 3
when 16#633# => romdata <= X"1c"; -- 3
when 16#733# => romdata <= X"02"; -- 3
when 16#833# => romdata <= X"02"; -- 3
when 16#933# => romdata <= X"42"; -- 3
when 16#a33# => romdata <= X"3c"; -- 3
when 16#b33# => romdata <= X"00"; -- 3
when 16#c33# => romdata <= X"00"; -- 3
when 16#034# => romdata <= X"00"; -- 4
when 16#134# => romdata <= X"00"; -- 4
when 16#234# => romdata <= X"04"; -- 4
when 16#334# => romdata <= X"0c"; -- 4
when 16#434# => romdata <= X"14"; -- 4
when 16#534# => romdata <= X"24"; -- 4
when 16#634# => romdata <= X"44"; -- 4
when 16#734# => romdata <= X"44"; -- 4
when 16#834# => romdata <= X"7e"; -- 4
when 16#934# => romdata <= X"04"; -- 4
when 16#a34# => romdata <= X"04"; -- 4
when 16#b34# => romdata <= X"00"; -- 4
when 16#c34# => romdata <= X"00"; -- 4
when 16#035# => romdata <= X"00"; -- 5
when 16#135# => romdata <= X"00"; -- 5
when 16#235# => romdata <= X"7e"; -- 5
when 16#335# => romdata <= X"40"; -- 5
when 16#435# => romdata <= X"40"; -- 5
when 16#535# => romdata <= X"5c"; -- 5
when 16#635# => romdata <= X"62"; -- 5
when 16#735# => romdata <= X"02"; -- 5
when 16#835# => romdata <= X"02"; -- 5
when 16#935# => romdata <= X"42"; -- 5
when 16#a35# => romdata <= X"3c"; -- 5
when 16#b35# => romdata <= X"00"; -- 5
when 16#c35# => romdata <= X"00"; -- 5
when 16#036# => romdata <= X"00"; -- 6
when 16#136# => romdata <= X"00"; -- 6
when 16#236# => romdata <= X"1c"; -- 6
when 16#336# => romdata <= X"20"; -- 6
when 16#436# => romdata <= X"40"; -- 6
when 16#536# => romdata <= X"40"; -- 6
when 16#636# => romdata <= X"5c"; -- 6
when 16#736# => romdata <= X"62"; -- 6
when 16#836# => romdata <= X"42"; -- 6
when 16#936# => romdata <= X"42"; -- 6
when 16#a36# => romdata <= X"3c"; -- 6
when 16#b36# => romdata <= X"00"; -- 6
when 16#c36# => romdata <= X"00"; -- 6
when 16#037# => romdata <= X"00"; -- 7
when 16#137# => romdata <= X"00"; -- 7
when 16#237# => romdata <= X"7e"; -- 7
when 16#337# => romdata <= X"02"; -- 7
when 16#437# => romdata <= X"04"; -- 7
when 16#537# => romdata <= X"08"; -- 7
when 16#637# => romdata <= X"08"; -- 7
when 16#737# => romdata <= X"10"; -- 7
when 16#837# => romdata <= X"10"; -- 7
when 16#937# => romdata <= X"20"; -- 7
when 16#a37# => romdata <= X"20"; -- 7
when 16#b37# => romdata <= X"00"; -- 7
when 16#c37# => romdata <= X"00"; -- 7
when 16#038# => romdata <= X"00"; -- 8
when 16#138# => romdata <= X"00"; -- 8
when 16#238# => romdata <= X"3c"; -- 8
when 16#338# => romdata <= X"42"; -- 8
when 16#438# => romdata <= X"42"; -- 8
when 16#538# => romdata <= X"42"; -- 8
when 16#638# => romdata <= X"3c"; -- 8
when 16#738# => romdata <= X"42"; -- 8
when 16#838# => romdata <= X"42"; -- 8
when 16#938# => romdata <= X"42"; -- 8
when 16#a38# => romdata <= X"3c"; -- 8
when 16#b38# => romdata <= X"00"; -- 8
when 16#c38# => romdata <= X"00"; -- 8
when 16#039# => romdata <= X"00"; -- 9
when 16#139# => romdata <= X"00"; -- 9
when 16#239# => romdata <= X"3c"; -- 9
when 16#339# => romdata <= X"42"; -- 9
when 16#439# => romdata <= X"42"; -- 9
when 16#539# => romdata <= X"46"; -- 9
when 16#639# => romdata <= X"3a"; -- 9
when 16#739# => romdata <= X"02"; -- 9
when 16#839# => romdata <= X"02"; -- 9
when 16#939# => romdata <= X"04"; -- 9
when 16#a39# => romdata <= X"38"; -- 9
when 16#b39# => romdata <= X"00"; -- 9
when 16#c39# => romdata <= X"00"; -- 9
when 16#03a# => romdata <= X"00"; -- :
when 16#13a# => romdata <= X"00"; -- :
when 16#23a# => romdata <= X"00"; -- :
when 16#33a# => romdata <= X"00"; -- :
when 16#43a# => romdata <= X"10"; -- :
when 16#53a# => romdata <= X"38"; -- :
when 16#63a# => romdata <= X"10"; -- :
when 16#73a# => romdata <= X"00"; -- :
when 16#83a# => romdata <= X"00"; -- :
when 16#93a# => romdata <= X"10"; -- :
when 16#a3a# => romdata <= X"38"; -- :
when 16#b3a# => romdata <= X"10"; -- :
when 16#c3a# => romdata <= X"00"; -- :
when 16#03b# => romdata <= X"00"; -- ;
when 16#13b# => romdata <= X"00"; -- ;
when 16#23b# => romdata <= X"00"; -- ;
when 16#33b# => romdata <= X"00"; -- ;
when 16#43b# => romdata <= X"10"; -- ;
when 16#53b# => romdata <= X"38"; -- ;
when 16#63b# => romdata <= X"10"; -- ;
when 16#73b# => romdata <= X"00"; -- ;
when 16#83b# => romdata <= X"00"; -- ;
when 16#93b# => romdata <= X"38"; -- ;
when 16#a3b# => romdata <= X"30"; -- ;
when 16#b3b# => romdata <= X"40"; -- ;
when 16#c3b# => romdata <= X"00"; -- ;
when 16#03c# => romdata <= X"00"; -- <
when 16#13c# => romdata <= X"00"; -- <
when 16#23c# => romdata <= X"02"; -- <
when 16#33c# => romdata <= X"04"; -- <
when 16#43c# => romdata <= X"08"; -- <
when 16#53c# => romdata <= X"10"; -- <
when 16#63c# => romdata <= X"20"; -- <
when 16#73c# => romdata <= X"10"; -- <
when 16#83c# => romdata <= X"08"; -- <
when 16#93c# => romdata <= X"04"; -- <
when 16#a3c# => romdata <= X"02"; -- <
when 16#b3c# => romdata <= X"00"; -- <
when 16#c3c# => romdata <= X"00"; -- <
when 16#03d# => romdata <= X"00"; -- =
when 16#13d# => romdata <= X"00"; -- =
when 16#23d# => romdata <= X"00"; -- =
when 16#33d# => romdata <= X"00"; -- =
when 16#43d# => romdata <= X"00"; -- =
when 16#53d# => romdata <= X"7e"; -- =
when 16#63d# => romdata <= X"00"; -- =
when 16#73d# => romdata <= X"00"; -- =
when 16#83d# => romdata <= X"7e"; -- =
when 16#93d# => romdata <= X"00"; -- =
when 16#a3d# => romdata <= X"00"; -- =
when 16#b3d# => romdata <= X"00"; -- =
when 16#c3d# => romdata <= X"00"; -- =
when 16#03e# => romdata <= X"00"; -- >
when 16#13e# => romdata <= X"00"; -- >
when 16#23e# => romdata <= X"40"; -- >
when 16#33e# => romdata <= X"20"; -- >
when 16#43e# => romdata <= X"10"; -- >
when 16#53e# => romdata <= X"08"; -- >
when 16#63e# => romdata <= X"04"; -- >
when 16#73e# => romdata <= X"08"; -- >
when 16#83e# => romdata <= X"10"; -- >
when 16#93e# => romdata <= X"20"; -- >
when 16#a3e# => romdata <= X"40"; -- >
when 16#b3e# => romdata <= X"00"; -- >
when 16#c3e# => romdata <= X"00"; -- >
when 16#03f# => romdata <= X"00"; -- ?
when 16#13f# => romdata <= X"00"; -- ?
when 16#23f# => romdata <= X"3c"; -- ?
when 16#33f# => romdata <= X"42"; -- ?
when 16#43f# => romdata <= X"42"; -- ?
when 16#53f# => romdata <= X"02"; -- ?
when 16#63f# => romdata <= X"04"; -- ?
when 16#73f# => romdata <= X"08"; -- ?
when 16#83f# => romdata <= X"08"; -- ?
when 16#93f# => romdata <= X"00"; -- ?
when 16#a3f# => romdata <= X"08"; -- ?
when 16#b3f# => romdata <= X"00"; -- ?
when 16#c3f# => romdata <= X"00"; -- ?
when 16#040# => romdata <= X"00"; -- @
when 16#140# => romdata <= X"00"; -- @
when 16#240# => romdata <= X"3c"; -- @
when 16#340# => romdata <= X"42"; -- @
when 16#440# => romdata <= X"42"; -- @
when 16#540# => romdata <= X"4e"; -- @
when 16#640# => romdata <= X"52"; -- @
when 16#740# => romdata <= X"56"; -- @
when 16#840# => romdata <= X"4a"; -- @
when 16#940# => romdata <= X"40"; -- @
when 16#a40# => romdata <= X"3c"; -- @
when 16#b40# => romdata <= X"00"; -- @
when 16#c40# => romdata <= X"00"; -- @
when 16#041# => romdata <= X"00"; -- A
when 16#141# => romdata <= X"00"; -- A
when 16#241# => romdata <= X"18"; -- A
when 16#341# => romdata <= X"24"; -- A
when 16#441# => romdata <= X"42"; -- A
when 16#541# => romdata <= X"42"; -- A
when 16#641# => romdata <= X"42"; -- A
when 16#741# => romdata <= X"7e"; -- A
when 16#841# => romdata <= X"42"; -- A
when 16#941# => romdata <= X"42"; -- A
when 16#a41# => romdata <= X"42"; -- A
when 16#b41# => romdata <= X"00"; -- A
when 16#c41# => romdata <= X"00"; -- A
when 16#042# => romdata <= X"00"; -- B
when 16#142# => romdata <= X"00"; -- B
when 16#242# => romdata <= X"78"; -- B
when 16#342# => romdata <= X"44"; -- B
when 16#442# => romdata <= X"42"; -- B
when 16#542# => romdata <= X"44"; -- B
when 16#642# => romdata <= X"78"; -- B
when 16#742# => romdata <= X"44"; -- B
when 16#842# => romdata <= X"42"; -- B
when 16#942# => romdata <= X"44"; -- B
when 16#a42# => romdata <= X"78"; -- B
when 16#b42# => romdata <= X"00"; -- B
when 16#c42# => romdata <= X"00"; -- B
when 16#043# => romdata <= X"00"; -- C
when 16#143# => romdata <= X"00"; -- C
when 16#243# => romdata <= X"3c"; -- C
when 16#343# => romdata <= X"42"; -- C
when 16#443# => romdata <= X"40"; -- C
when 16#543# => romdata <= X"40"; -- C
when 16#643# => romdata <= X"40"; -- C
when 16#743# => romdata <= X"40"; -- C
when 16#843# => romdata <= X"40"; -- C
when 16#943# => romdata <= X"42"; -- C
when 16#a43# => romdata <= X"3c"; -- C
when 16#b43# => romdata <= X"00"; -- C
when 16#c43# => romdata <= X"00"; -- C
when 16#044# => romdata <= X"00"; -- D
when 16#144# => romdata <= X"00"; -- D
when 16#244# => romdata <= X"78"; -- D
when 16#344# => romdata <= X"44"; -- D
when 16#444# => romdata <= X"42"; -- D
when 16#544# => romdata <= X"42"; -- D
when 16#644# => romdata <= X"42"; -- D
when 16#744# => romdata <= X"42"; -- D
when 16#844# => romdata <= X"42"; -- D
when 16#944# => romdata <= X"44"; -- D
when 16#a44# => romdata <= X"78"; -- D
when 16#b44# => romdata <= X"00"; -- D
when 16#c44# => romdata <= X"00"; -- D
when 16#045# => romdata <= X"00"; -- E
when 16#145# => romdata <= X"00"; -- E
when 16#245# => romdata <= X"7e"; -- E
when 16#345# => romdata <= X"40"; -- E
when 16#445# => romdata <= X"40"; -- E
when 16#545# => romdata <= X"40"; -- E
when 16#645# => romdata <= X"78"; -- E
when 16#745# => romdata <= X"40"; -- E
when 16#845# => romdata <= X"40"; -- E
when 16#945# => romdata <= X"40"; -- E
when 16#a45# => romdata <= X"7e"; -- E
when 16#b45# => romdata <= X"00"; -- E
when 16#c45# => romdata <= X"00"; -- E
when 16#046# => romdata <= X"00"; -- F
when 16#146# => romdata <= X"00"; -- F
when 16#246# => romdata <= X"7e"; -- F
when 16#346# => romdata <= X"40"; -- F
when 16#446# => romdata <= X"40"; -- F
when 16#546# => romdata <= X"40"; -- F
when 16#646# => romdata <= X"78"; -- F
when 16#746# => romdata <= X"40"; -- F
when 16#846# => romdata <= X"40"; -- F
when 16#946# => romdata <= X"40"; -- F
when 16#a46# => romdata <= X"40"; -- F
when 16#b46# => romdata <= X"00"; -- F
when 16#c46# => romdata <= X"00"; -- F
when 16#047# => romdata <= X"00"; -- G
when 16#147# => romdata <= X"00"; -- G
when 16#247# => romdata <= X"3c"; -- G
when 16#347# => romdata <= X"42"; -- G
when 16#447# => romdata <= X"40"; -- G
when 16#547# => romdata <= X"40"; -- G
when 16#647# => romdata <= X"40"; -- G
when 16#747# => romdata <= X"4e"; -- G
when 16#847# => romdata <= X"42"; -- G
when 16#947# => romdata <= X"46"; -- G
when 16#a47# => romdata <= X"3a"; -- G
when 16#b47# => romdata <= X"00"; -- G
when 16#c47# => romdata <= X"00"; -- G
when 16#048# => romdata <= X"00"; -- H
when 16#148# => romdata <= X"00"; -- H
when 16#248# => romdata <= X"42"; -- H
when 16#348# => romdata <= X"42"; -- H
when 16#448# => romdata <= X"42"; -- H
when 16#548# => romdata <= X"42"; -- H
when 16#648# => romdata <= X"7e"; -- H
when 16#748# => romdata <= X"42"; -- H
when 16#848# => romdata <= X"42"; -- H
when 16#948# => romdata <= X"42"; -- H
when 16#a48# => romdata <= X"42"; -- H
when 16#b48# => romdata <= X"00"; -- H
when 16#c48# => romdata <= X"00"; -- H
when 16#049# => romdata <= X"00"; -- I
when 16#149# => romdata <= X"00"; -- I
when 16#249# => romdata <= X"7c"; -- I
when 16#349# => romdata <= X"10"; -- I
when 16#449# => romdata <= X"10"; -- I
when 16#549# => romdata <= X"10"; -- I
when 16#649# => romdata <= X"10"; -- I
when 16#749# => romdata <= X"10"; -- I
when 16#849# => romdata <= X"10"; -- I
when 16#949# => romdata <= X"10"; -- I
when 16#a49# => romdata <= X"7c"; -- I
when 16#b49# => romdata <= X"00"; -- I
when 16#c49# => romdata <= X"00"; -- I
when 16#04a# => romdata <= X"00"; -- J
when 16#14a# => romdata <= X"00"; -- J
when 16#24a# => romdata <= X"1f"; -- J
when 16#34a# => romdata <= X"04"; -- J
when 16#44a# => romdata <= X"04"; -- J
when 16#54a# => romdata <= X"04"; -- J
when 16#64a# => romdata <= X"04"; -- J
when 16#74a# => romdata <= X"04"; -- J
when 16#84a# => romdata <= X"04"; -- J
when 16#94a# => romdata <= X"44"; -- J
when 16#a4a# => romdata <= X"38"; -- J
when 16#b4a# => romdata <= X"00"; -- J
when 16#c4a# => romdata <= X"00"; -- J
when 16#04b# => romdata <= X"00"; -- K
when 16#14b# => romdata <= X"00"; -- K
when 16#24b# => romdata <= X"42"; -- K
when 16#34b# => romdata <= X"44"; -- K
when 16#44b# => romdata <= X"48"; -- K
when 16#54b# => romdata <= X"50"; -- K
when 16#64b# => romdata <= X"60"; -- K
when 16#74b# => romdata <= X"50"; -- K
when 16#84b# => romdata <= X"48"; -- K
when 16#94b# => romdata <= X"44"; -- K
when 16#a4b# => romdata <= X"42"; -- K
when 16#b4b# => romdata <= X"00"; -- K
when 16#c4b# => romdata <= X"00"; -- K
when 16#04c# => romdata <= X"00"; -- L
when 16#14c# => romdata <= X"00"; -- L
when 16#24c# => romdata <= X"40"; -- L
when 16#34c# => romdata <= X"40"; -- L
when 16#44c# => romdata <= X"40"; -- L
when 16#54c# => romdata <= X"40"; -- L
when 16#64c# => romdata <= X"40"; -- L
when 16#74c# => romdata <= X"40"; -- L
when 16#84c# => romdata <= X"40"; -- L
when 16#94c# => romdata <= X"40"; -- L
when 16#a4c# => romdata <= X"7e"; -- L
when 16#b4c# => romdata <= X"00"; -- L
when 16#c4c# => romdata <= X"00"; -- L
when 16#04d# => romdata <= X"00"; -- M
when 16#14d# => romdata <= X"00"; -- M
when 16#24d# => romdata <= X"82"; -- M
when 16#34d# => romdata <= X"82"; -- M
when 16#44d# => romdata <= X"c6"; -- M
when 16#54d# => romdata <= X"aa"; -- M
when 16#64d# => romdata <= X"92"; -- M
when 16#74d# => romdata <= X"92"; -- M
when 16#84d# => romdata <= X"82"; -- M
when 16#94d# => romdata <= X"82"; -- M
when 16#a4d# => romdata <= X"82"; -- M
when 16#b4d# => romdata <= X"00"; -- M
when 16#c4d# => romdata <= X"00"; -- M
when 16#04e# => romdata <= X"00"; -- N
when 16#14e# => romdata <= X"00"; -- N
when 16#24e# => romdata <= X"42"; -- N
when 16#34e# => romdata <= X"42"; -- N
when 16#44e# => romdata <= X"62"; -- N
when 16#54e# => romdata <= X"52"; -- N
when 16#64e# => romdata <= X"4a"; -- N
when 16#74e# => romdata <= X"46"; -- N
when 16#84e# => romdata <= X"42"; -- N
when 16#94e# => romdata <= X"42"; -- N
when 16#a4e# => romdata <= X"42"; -- N
when 16#b4e# => romdata <= X"00"; -- N
when 16#c4e# => romdata <= X"00"; -- N
when 16#04f# => romdata <= X"00"; -- O
when 16#14f# => romdata <= X"00"; -- O
when 16#24f# => romdata <= X"3c"; -- O
when 16#34f# => romdata <= X"42"; -- O
when 16#44f# => romdata <= X"42"; -- O
when 16#54f# => romdata <= X"42"; -- O
when 16#64f# => romdata <= X"42"; -- O
when 16#74f# => romdata <= X"42"; -- O
when 16#84f# => romdata <= X"42"; -- O
when 16#94f# => romdata <= X"42"; -- O
when 16#a4f# => romdata <= X"3c"; -- O
when 16#b4f# => romdata <= X"00"; -- O
when 16#c4f# => romdata <= X"00"; -- O
when 16#050# => romdata <= X"00"; -- P
when 16#150# => romdata <= X"00"; -- P
when 16#250# => romdata <= X"7c"; -- P
when 16#350# => romdata <= X"42"; -- P
when 16#450# => romdata <= X"42"; -- P
when 16#550# => romdata <= X"42"; -- P
when 16#650# => romdata <= X"7c"; -- P
when 16#750# => romdata <= X"40"; -- P
when 16#850# => romdata <= X"40"; -- P
when 16#950# => romdata <= X"40"; -- P
when 16#a50# => romdata <= X"40"; -- P
when 16#b50# => romdata <= X"00"; -- P
when 16#c50# => romdata <= X"00"; -- P
when 16#051# => romdata <= X"00"; -- Q
when 16#151# => romdata <= X"00"; -- Q
when 16#251# => romdata <= X"3c"; -- Q
when 16#351# => romdata <= X"42"; -- Q
when 16#451# => romdata <= X"42"; -- Q
when 16#551# => romdata <= X"42"; -- Q
when 16#651# => romdata <= X"42"; -- Q
when 16#751# => romdata <= X"42"; -- Q
when 16#851# => romdata <= X"52"; -- Q
when 16#951# => romdata <= X"4a"; -- Q
when 16#a51# => romdata <= X"3c"; -- Q
when 16#b51# => romdata <= X"02"; -- Q
when 16#c51# => romdata <= X"00"; -- Q
when 16#052# => romdata <= X"00"; -- R
when 16#152# => romdata <= X"00"; -- R
when 16#252# => romdata <= X"7c"; -- R
when 16#352# => romdata <= X"42"; -- R
when 16#452# => romdata <= X"42"; -- R
when 16#552# => romdata <= X"42"; -- R
when 16#652# => romdata <= X"7c"; -- R
when 16#752# => romdata <= X"50"; -- R
when 16#852# => romdata <= X"48"; -- R
when 16#952# => romdata <= X"44"; -- R
when 16#a52# => romdata <= X"42"; -- R
when 16#b52# => romdata <= X"00"; -- R
when 16#c52# => romdata <= X"00"; -- R
when 16#053# => romdata <= X"00"; -- S
when 16#153# => romdata <= X"00"; -- S
when 16#253# => romdata <= X"3c"; -- S
when 16#353# => romdata <= X"42"; -- S
when 16#453# => romdata <= X"40"; -- S
when 16#553# => romdata <= X"40"; -- S
when 16#653# => romdata <= X"3c"; -- S
when 16#753# => romdata <= X"02"; -- S
when 16#853# => romdata <= X"02"; -- S
when 16#953# => romdata <= X"42"; -- S
when 16#a53# => romdata <= X"3c"; -- S
when 16#b53# => romdata <= X"00"; -- S
when 16#c53# => romdata <= X"00"; -- S
when 16#054# => romdata <= X"00"; -- T
when 16#154# => romdata <= X"00"; -- T
when 16#254# => romdata <= X"fe"; -- T
when 16#354# => romdata <= X"10"; -- T
when 16#454# => romdata <= X"10"; -- T
when 16#554# => romdata <= X"10"; -- T
when 16#654# => romdata <= X"10"; -- T
when 16#754# => romdata <= X"10"; -- T
when 16#854# => romdata <= X"10"; -- T
when 16#954# => romdata <= X"10"; -- T
when 16#a54# => romdata <= X"10"; -- T
when 16#b54# => romdata <= X"00"; -- T
when 16#c54# => romdata <= X"00"; -- T
when 16#055# => romdata <= X"00"; -- U
when 16#155# => romdata <= X"00"; -- U
when 16#255# => romdata <= X"42"; -- U
when 16#355# => romdata <= X"42"; -- U
when 16#455# => romdata <= X"42"; -- U
when 16#555# => romdata <= X"42"; -- U
when 16#655# => romdata <= X"42"; -- U
when 16#755# => romdata <= X"42"; -- U
when 16#855# => romdata <= X"42"; -- U
when 16#955# => romdata <= X"42"; -- U
when 16#a55# => romdata <= X"3c"; -- U
when 16#b55# => romdata <= X"00"; -- U
when 16#c55# => romdata <= X"00"; -- U
when 16#056# => romdata <= X"00"; -- V
when 16#156# => romdata <= X"00"; -- V
when 16#256# => romdata <= X"82"; -- V
when 16#356# => romdata <= X"82"; -- V
when 16#456# => romdata <= X"44"; -- V
when 16#556# => romdata <= X"44"; -- V
when 16#656# => romdata <= X"44"; -- V
when 16#756# => romdata <= X"28"; -- V
when 16#856# => romdata <= X"28"; -- V
when 16#956# => romdata <= X"28"; -- V
when 16#a56# => romdata <= X"10"; -- V
when 16#b56# => romdata <= X"00"; -- V
when 16#c56# => romdata <= X"00"; -- V
when 16#057# => romdata <= X"00"; -- W
when 16#157# => romdata <= X"00"; -- W
when 16#257# => romdata <= X"82"; -- W
when 16#357# => romdata <= X"82"; -- W
when 16#457# => romdata <= X"82"; -- W
when 16#557# => romdata <= X"82"; -- W
when 16#657# => romdata <= X"92"; -- W
when 16#757# => romdata <= X"92"; -- W
when 16#857# => romdata <= X"92"; -- W
when 16#957# => romdata <= X"aa"; -- W
when 16#a57# => romdata <= X"44"; -- W
when 16#b57# => romdata <= X"00"; -- W
when 16#c57# => romdata <= X"00"; -- W
when 16#058# => romdata <= X"00"; -- X
when 16#158# => romdata <= X"00"; -- X
when 16#258# => romdata <= X"82"; -- X
when 16#358# => romdata <= X"82"; -- X
when 16#458# => romdata <= X"44"; -- X
when 16#558# => romdata <= X"28"; -- X
when 16#658# => romdata <= X"10"; -- X
when 16#758# => romdata <= X"28"; -- X
when 16#858# => romdata <= X"44"; -- X
when 16#958# => romdata <= X"82"; -- X
when 16#a58# => romdata <= X"82"; -- X
when 16#b58# => romdata <= X"00"; -- X
when 16#c58# => romdata <= X"00"; -- X
when 16#059# => romdata <= X"00"; -- Y
when 16#159# => romdata <= X"00"; -- Y
when 16#259# => romdata <= X"82"; -- Y
when 16#359# => romdata <= X"82"; -- Y
when 16#459# => romdata <= X"44"; -- Y
when 16#559# => romdata <= X"28"; -- Y
when 16#659# => romdata <= X"10"; -- Y
when 16#759# => romdata <= X"10"; -- Y
when 16#859# => romdata <= X"10"; -- Y
when 16#959# => romdata <= X"10"; -- Y
when 16#a59# => romdata <= X"10"; -- Y
when 16#b59# => romdata <= X"00"; -- Y
when 16#c59# => romdata <= X"00"; -- Y
when 16#05a# => romdata <= X"00"; -- Z
when 16#15a# => romdata <= X"00"; -- Z
when 16#25a# => romdata <= X"7e"; -- Z
when 16#35a# => romdata <= X"02"; -- Z
when 16#45a# => romdata <= X"04"; -- Z
when 16#55a# => romdata <= X"08"; -- Z
when 16#65a# => romdata <= X"10"; -- Z
when 16#75a# => romdata <= X"20"; -- Z
when 16#85a# => romdata <= X"40"; -- Z
when 16#95a# => romdata <= X"40"; -- Z
when 16#a5a# => romdata <= X"7e"; -- Z
when 16#b5a# => romdata <= X"00"; -- Z
when 16#c5a# => romdata <= X"00"; -- Z
when 16#05b# => romdata <= X"00"; -- [
when 16#15b# => romdata <= X"00"; -- [
when 16#25b# => romdata <= X"3c"; -- [
when 16#35b# => romdata <= X"20"; -- [
when 16#45b# => romdata <= X"20"; -- [
when 16#55b# => romdata <= X"20"; -- [
when 16#65b# => romdata <= X"20"; -- [
when 16#75b# => romdata <= X"20"; -- [
when 16#85b# => romdata <= X"20"; -- [
when 16#95b# => romdata <= X"20"; -- [
when 16#a5b# => romdata <= X"3c"; -- [
when 16#b5b# => romdata <= X"00"; -- [
when 16#c5b# => romdata <= X"00"; -- [
when 16#05c# => romdata <= X"00"; -- \
when 16#15c# => romdata <= X"00"; -- \
when 16#25c# => romdata <= X"80"; -- \
when 16#35c# => romdata <= X"80"; -- \
when 16#45c# => romdata <= X"40"; -- \
when 16#55c# => romdata <= X"20"; -- \
when 16#65c# => romdata <= X"10"; -- \
when 16#75c# => romdata <= X"08"; -- \
when 16#85c# => romdata <= X"04"; -- \
when 16#95c# => romdata <= X"02"; -- \
when 16#a5c# => romdata <= X"02"; -- \
when 16#b5c# => romdata <= X"00"; -- \
when 16#c5c# => romdata <= X"00"; -- \
when 16#05d# => romdata <= X"00"; -- ]
when 16#15d# => romdata <= X"00"; -- ]
when 16#25d# => romdata <= X"78"; -- ]
when 16#35d# => romdata <= X"08"; -- ]
when 16#45d# => romdata <= X"08"; -- ]
when 16#55d# => romdata <= X"08"; -- ]
when 16#65d# => romdata <= X"08"; -- ]
when 16#75d# => romdata <= X"08"; -- ]
when 16#85d# => romdata <= X"08"; -- ]
when 16#95d# => romdata <= X"08"; -- ]
when 16#a5d# => romdata <= X"78"; -- ]
when 16#b5d# => romdata <= X"00"; -- ]
when 16#c5d# => romdata <= X"00"; -- ]
when 16#05e# => romdata <= X"00"; -- ^
when 16#15e# => romdata <= X"00"; -- ^
when 16#25e# => romdata <= X"10"; -- ^
when 16#35e# => romdata <= X"28"; -- ^
when 16#45e# => romdata <= X"44"; -- ^
when 16#55e# => romdata <= X"00"; -- ^
when 16#65e# => romdata <= X"00"; -- ^
when 16#75e# => romdata <= X"00"; -- ^
when 16#85e# => romdata <= X"00"; -- ^
when 16#95e# => romdata <= X"00"; -- ^
when 16#a5e# => romdata <= X"00"; -- ^
when 16#b5e# => romdata <= X"00"; -- ^
when 16#c5e# => romdata <= X"00"; -- ^
when 16#05f# => romdata <= X"00"; -- _
when 16#15f# => romdata <= X"00"; -- _
when 16#25f# => romdata <= X"00"; -- _
when 16#35f# => romdata <= X"00"; -- _
when 16#45f# => romdata <= X"00"; -- _
when 16#55f# => romdata <= X"00"; -- _
when 16#65f# => romdata <= X"00"; -- _
when 16#75f# => romdata <= X"00"; -- _
when 16#85f# => romdata <= X"00"; -- _
when 16#95f# => romdata <= X"00"; -- _
when 16#a5f# => romdata <= X"00"; -- _
when 16#b5f# => romdata <= X"fe"; -- _
when 16#c5f# => romdata <= X"00"; -- _
when 16#060# => romdata <= X"00"; -- `
when 16#160# => romdata <= X"10"; -- `
when 16#260# => romdata <= X"08"; -- `
when 16#360# => romdata <= X"00"; -- `
when 16#460# => romdata <= X"00"; -- `
when 16#560# => romdata <= X"00"; -- `
when 16#660# => romdata <= X"00"; -- `
when 16#760# => romdata <= X"00"; -- `
when 16#860# => romdata <= X"00"; -- `
when 16#960# => romdata <= X"00"; -- `
when 16#a60# => romdata <= X"00"; -- `
when 16#b60# => romdata <= X"00"; -- `
when 16#c60# => romdata <= X"00"; -- `
when 16#061# => romdata <= X"00"; -- a
when 16#161# => romdata <= X"00"; -- a
when 16#261# => romdata <= X"00"; -- a
when 16#361# => romdata <= X"00"; -- a
when 16#461# => romdata <= X"00"; -- a
when 16#561# => romdata <= X"3c"; -- a
when 16#661# => romdata <= X"02"; -- a
when 16#761# => romdata <= X"3e"; -- a
when 16#861# => romdata <= X"42"; -- a
when 16#961# => romdata <= X"46"; -- a
when 16#a61# => romdata <= X"3a"; -- a
when 16#b61# => romdata <= X"00"; -- a
when 16#c61# => romdata <= X"00"; -- a
when 16#062# => romdata <= X"00"; -- b
when 16#162# => romdata <= X"00"; -- b
when 16#262# => romdata <= X"40"; -- b
when 16#362# => romdata <= X"40"; -- b
when 16#462# => romdata <= X"40"; -- b
when 16#562# => romdata <= X"5c"; -- b
when 16#662# => romdata <= X"62"; -- b
when 16#762# => romdata <= X"42"; -- b
when 16#862# => romdata <= X"42"; -- b
when 16#962# => romdata <= X"62"; -- b
when 16#a62# => romdata <= X"5c"; -- b
when 16#b62# => romdata <= X"00"; -- b
when 16#c62# => romdata <= X"00"; -- b
when 16#063# => romdata <= X"00"; -- c
when 16#163# => romdata <= X"00"; -- c
when 16#263# => romdata <= X"00"; -- c
when 16#363# => romdata <= X"00"; -- c
when 16#463# => romdata <= X"00"; -- c
when 16#563# => romdata <= X"3c"; -- c
when 16#663# => romdata <= X"42"; -- c
when 16#763# => romdata <= X"40"; -- c
when 16#863# => romdata <= X"40"; -- c
when 16#963# => romdata <= X"42"; -- c
when 16#a63# => romdata <= X"3c"; -- c
when 16#b63# => romdata <= X"00"; -- c
when 16#c63# => romdata <= X"00"; -- c
when 16#064# => romdata <= X"00"; -- d
when 16#164# => romdata <= X"00"; -- d
when 16#264# => romdata <= X"02"; -- d
when 16#364# => romdata <= X"02"; -- d
when 16#464# => romdata <= X"02"; -- d
when 16#564# => romdata <= X"3a"; -- d
when 16#664# => romdata <= X"46"; -- d
when 16#764# => romdata <= X"42"; -- d
when 16#864# => romdata <= X"42"; -- d
when 16#964# => romdata <= X"46"; -- d
when 16#a64# => romdata <= X"3a"; -- d
when 16#b64# => romdata <= X"00"; -- d
when 16#c64# => romdata <= X"00"; -- d
when 16#065# => romdata <= X"00"; -- e
when 16#165# => romdata <= X"00"; -- e
when 16#265# => romdata <= X"00"; -- e
when 16#365# => romdata <= X"00"; -- e
when 16#465# => romdata <= X"00"; -- e
when 16#565# => romdata <= X"3c"; -- e
when 16#665# => romdata <= X"42"; -- e
when 16#765# => romdata <= X"7e"; -- e
when 16#865# => romdata <= X"40"; -- e
when 16#965# => romdata <= X"42"; -- e
when 16#a65# => romdata <= X"3c"; -- e
when 16#b65# => romdata <= X"00"; -- e
when 16#c65# => romdata <= X"00"; -- e
when 16#066# => romdata <= X"00"; -- f
when 16#166# => romdata <= X"00"; -- f
when 16#266# => romdata <= X"1c"; -- f
when 16#366# => romdata <= X"22"; -- f
when 16#466# => romdata <= X"20"; -- f
when 16#566# => romdata <= X"20"; -- f
when 16#666# => romdata <= X"7c"; -- f
when 16#766# => romdata <= X"20"; -- f
when 16#866# => romdata <= X"20"; -- f
when 16#966# => romdata <= X"20"; -- f
when 16#a66# => romdata <= X"20"; -- f
when 16#b66# => romdata <= X"00"; -- f
when 16#c66# => romdata <= X"00"; -- f
when 16#067# => romdata <= X"00"; -- g
when 16#167# => romdata <= X"00"; -- g
when 16#267# => romdata <= X"00"; -- g
when 16#367# => romdata <= X"00"; -- g
when 16#467# => romdata <= X"00"; -- g
when 16#567# => romdata <= X"3a"; -- g
when 16#667# => romdata <= X"44"; -- g
when 16#767# => romdata <= X"44"; -- g
when 16#867# => romdata <= X"38"; -- g
when 16#967# => romdata <= X"40"; -- g
when 16#a67# => romdata <= X"3c"; -- g
when 16#b67# => romdata <= X"42"; -- g
when 16#c67# => romdata <= X"3c"; -- g
when 16#068# => romdata <= X"00"; -- h
when 16#168# => romdata <= X"00"; -- h
when 16#268# => romdata <= X"40"; -- h
when 16#368# => romdata <= X"40"; -- h
when 16#468# => romdata <= X"40"; -- h
when 16#568# => romdata <= X"5c"; -- h
when 16#668# => romdata <= X"62"; -- h
when 16#768# => romdata <= X"42"; -- h
when 16#868# => romdata <= X"42"; -- h
when 16#968# => romdata <= X"42"; -- h
when 16#a68# => romdata <= X"42"; -- h
when 16#b68# => romdata <= X"00"; -- h
when 16#c68# => romdata <= X"00"; -- h
when 16#069# => romdata <= X"00"; -- i
when 16#169# => romdata <= X"00"; -- i
when 16#269# => romdata <= X"00"; -- i
when 16#369# => romdata <= X"10"; -- i
when 16#469# => romdata <= X"00"; -- i
when 16#569# => romdata <= X"30"; -- i
when 16#669# => romdata <= X"10"; -- i
when 16#769# => romdata <= X"10"; -- i
when 16#869# => romdata <= X"10"; -- i
when 16#969# => romdata <= X"10"; -- i
when 16#a69# => romdata <= X"7c"; -- i
when 16#b69# => romdata <= X"00"; -- i
when 16#c69# => romdata <= X"00"; -- i
when 16#06a# => romdata <= X"00"; -- j
when 16#16a# => romdata <= X"00"; -- j
when 16#26a# => romdata <= X"00"; -- j
when 16#36a# => romdata <= X"04"; -- j
when 16#46a# => romdata <= X"00"; -- j
when 16#56a# => romdata <= X"0c"; -- j
when 16#66a# => romdata <= X"04"; -- j
when 16#76a# => romdata <= X"04"; -- j
when 16#86a# => romdata <= X"04"; -- j
when 16#96a# => romdata <= X"04"; -- j
when 16#a6a# => romdata <= X"44"; -- j
when 16#b6a# => romdata <= X"44"; -- j
when 16#c6a# => romdata <= X"38"; -- j
when 16#06b# => romdata <= X"00"; -- k
when 16#16b# => romdata <= X"00"; -- k
when 16#26b# => romdata <= X"40"; -- k
when 16#36b# => romdata <= X"40"; -- k
when 16#46b# => romdata <= X"40"; -- k
when 16#56b# => romdata <= X"44"; -- k
when 16#66b# => romdata <= X"48"; -- k
when 16#76b# => romdata <= X"70"; -- k
when 16#86b# => romdata <= X"48"; -- k
when 16#96b# => romdata <= X"44"; -- k
when 16#a6b# => romdata <= X"42"; -- k
when 16#b6b# => romdata <= X"00"; -- k
when 16#c6b# => romdata <= X"00"; -- k
when 16#06c# => romdata <= X"00"; -- l
when 16#16c# => romdata <= X"00"; -- l
when 16#26c# => romdata <= X"30"; -- l
when 16#36c# => romdata <= X"10"; -- l
when 16#46c# => romdata <= X"10"; -- l
when 16#56c# => romdata <= X"10"; -- l
when 16#66c# => romdata <= X"10"; -- l
when 16#76c# => romdata <= X"10"; -- l
when 16#86c# => romdata <= X"10"; -- l
when 16#96c# => romdata <= X"10"; -- l
when 16#a6c# => romdata <= X"7c"; -- l
when 16#b6c# => romdata <= X"00"; -- l
when 16#c6c# => romdata <= X"00"; -- l
when 16#06d# => romdata <= X"00"; -- m
when 16#16d# => romdata <= X"00"; -- m
when 16#26d# => romdata <= X"00"; -- m
when 16#36d# => romdata <= X"00"; -- m
when 16#46d# => romdata <= X"00"; -- m
when 16#56d# => romdata <= X"ec"; -- m
when 16#66d# => romdata <= X"92"; -- m
when 16#76d# => romdata <= X"92"; -- m
when 16#86d# => romdata <= X"92"; -- m
when 16#96d# => romdata <= X"92"; -- m
when 16#a6d# => romdata <= X"82"; -- m
when 16#b6d# => romdata <= X"00"; -- m
when 16#c6d# => romdata <= X"00"; -- m
when 16#06e# => romdata <= X"00"; -- n
when 16#16e# => romdata <= X"00"; -- n
when 16#26e# => romdata <= X"00"; -- n
when 16#36e# => romdata <= X"00"; -- n
when 16#46e# => romdata <= X"00"; -- n
when 16#56e# => romdata <= X"5c"; -- n
when 16#66e# => romdata <= X"62"; -- n
when 16#76e# => romdata <= X"42"; -- n
when 16#86e# => romdata <= X"42"; -- n
when 16#96e# => romdata <= X"42"; -- n
when 16#a6e# => romdata <= X"42"; -- n
when 16#b6e# => romdata <= X"00"; -- n
when 16#c6e# => romdata <= X"00"; -- n
when 16#06f# => romdata <= X"00"; -- o
when 16#16f# => romdata <= X"00"; -- o
when 16#26f# => romdata <= X"00"; -- o
when 16#36f# => romdata <= X"00"; -- o
when 16#46f# => romdata <= X"00"; -- o
when 16#56f# => romdata <= X"3c"; -- o
when 16#66f# => romdata <= X"42"; -- o
when 16#76f# => romdata <= X"42"; -- o
when 16#86f# => romdata <= X"42"; -- o
when 16#96f# => romdata <= X"42"; -- o
when 16#a6f# => romdata <= X"3c"; -- o
when 16#b6f# => romdata <= X"00"; -- o
when 16#c6f# => romdata <= X"00"; -- o
when 16#070# => romdata <= X"00"; -- p
when 16#170# => romdata <= X"00"; -- p
when 16#270# => romdata <= X"00"; -- p
when 16#370# => romdata <= X"00"; -- p
when 16#470# => romdata <= X"00"; -- p
when 16#570# => romdata <= X"5c"; -- p
when 16#670# => romdata <= X"62"; -- p
when 16#770# => romdata <= X"42"; -- p
when 16#870# => romdata <= X"62"; -- p
when 16#970# => romdata <= X"5c"; -- p
when 16#a70# => romdata <= X"40"; -- p
when 16#b70# => romdata <= X"40"; -- p
when 16#c70# => romdata <= X"40"; -- p
when 16#071# => romdata <= X"00"; -- q
when 16#171# => romdata <= X"00"; -- q
when 16#271# => romdata <= X"00"; -- q
when 16#371# => romdata <= X"00"; -- q
when 16#471# => romdata <= X"00"; -- q
when 16#571# => romdata <= X"3a"; -- q
when 16#671# => romdata <= X"46"; -- q
when 16#771# => romdata <= X"42"; -- q
when 16#871# => romdata <= X"46"; -- q
when 16#971# => romdata <= X"3a"; -- q
when 16#a71# => romdata <= X"02"; -- q
when 16#b71# => romdata <= X"02"; -- q
when 16#c71# => romdata <= X"02"; -- q
when 16#072# => romdata <= X"00"; -- r
when 16#172# => romdata <= X"00"; -- r
when 16#272# => romdata <= X"00"; -- r
when 16#372# => romdata <= X"00"; -- r
when 16#472# => romdata <= X"00"; -- r
when 16#572# => romdata <= X"5c"; -- r
when 16#672# => romdata <= X"22"; -- r
when 16#772# => romdata <= X"20"; -- r
when 16#872# => romdata <= X"20"; -- r
when 16#972# => romdata <= X"20"; -- r
when 16#a72# => romdata <= X"20"; -- r
when 16#b72# => romdata <= X"00"; -- r
when 16#c72# => romdata <= X"00"; -- r
when 16#073# => romdata <= X"00"; -- s
when 16#173# => romdata <= X"00"; -- s
when 16#273# => romdata <= X"00"; -- s
when 16#373# => romdata <= X"00"; -- s
when 16#473# => romdata <= X"00"; -- s
when 16#573# => romdata <= X"3c"; -- s
when 16#673# => romdata <= X"42"; -- s
when 16#773# => romdata <= X"30"; -- s
when 16#873# => romdata <= X"0c"; -- s
when 16#973# => romdata <= X"42"; -- s
when 16#a73# => romdata <= X"3c"; -- s
when 16#b73# => romdata <= X"00"; -- s
when 16#c73# => romdata <= X"00"; -- s
when 16#074# => romdata <= X"00"; -- t
when 16#174# => romdata <= X"00"; -- t
when 16#274# => romdata <= X"00"; -- t
when 16#374# => romdata <= X"20"; -- t
when 16#474# => romdata <= X"20"; -- t
when 16#574# => romdata <= X"7c"; -- t
when 16#674# => romdata <= X"20"; -- t
when 16#774# => romdata <= X"20"; -- t
when 16#874# => romdata <= X"20"; -- t
when 16#974# => romdata <= X"22"; -- t
when 16#a74# => romdata <= X"1c"; -- t
when 16#b74# => romdata <= X"00"; -- t
when 16#c74# => romdata <= X"00"; -- t
when 16#075# => romdata <= X"00"; -- u
when 16#175# => romdata <= X"00"; -- u
when 16#275# => romdata <= X"00"; -- u
when 16#375# => romdata <= X"00"; -- u
when 16#475# => romdata <= X"00"; -- u
when 16#575# => romdata <= X"44"; -- u
when 16#675# => romdata <= X"44"; -- u
when 16#775# => romdata <= X"44"; -- u
when 16#875# => romdata <= X"44"; -- u
when 16#975# => romdata <= X"44"; -- u
when 16#a75# => romdata <= X"3a"; -- u
when 16#b75# => romdata <= X"00"; -- u
when 16#c75# => romdata <= X"00"; -- u
when 16#076# => romdata <= X"00"; -- v
when 16#176# => romdata <= X"00"; -- v
when 16#276# => romdata <= X"00"; -- v
when 16#376# => romdata <= X"00"; -- v
when 16#476# => romdata <= X"00"; -- v
when 16#576# => romdata <= X"44"; -- v
when 16#676# => romdata <= X"44"; -- v
when 16#776# => romdata <= X"44"; -- v
when 16#876# => romdata <= X"28"; -- v
when 16#976# => romdata <= X"28"; -- v
when 16#a76# => romdata <= X"10"; -- v
when 16#b76# => romdata <= X"00"; -- v
when 16#c76# => romdata <= X"00"; -- v
when 16#077# => romdata <= X"00"; -- w
when 16#177# => romdata <= X"00"; -- w
when 16#277# => romdata <= X"00"; -- w
when 16#377# => romdata <= X"00"; -- w
when 16#477# => romdata <= X"00"; -- w
when 16#577# => romdata <= X"82"; -- w
when 16#677# => romdata <= X"82"; -- w
when 16#777# => romdata <= X"92"; -- w
when 16#877# => romdata <= X"92"; -- w
when 16#977# => romdata <= X"aa"; -- w
when 16#a77# => romdata <= X"44"; -- w
when 16#b77# => romdata <= X"00"; -- w
when 16#c77# => romdata <= X"00"; -- w
when 16#078# => romdata <= X"00"; -- x
when 16#178# => romdata <= X"00"; -- x
when 16#278# => romdata <= X"00"; -- x
when 16#378# => romdata <= X"00"; -- x
when 16#478# => romdata <= X"00"; -- x
when 16#578# => romdata <= X"42"; -- x
when 16#678# => romdata <= X"24"; -- x
when 16#778# => romdata <= X"18"; -- x
when 16#878# => romdata <= X"18"; -- x
when 16#978# => romdata <= X"24"; -- x
when 16#a78# => romdata <= X"42"; -- x
when 16#b78# => romdata <= X"00"; -- x
when 16#c78# => romdata <= X"00"; -- x
when 16#079# => romdata <= X"00"; -- y
when 16#179# => romdata <= X"00"; -- y
when 16#279# => romdata <= X"00"; -- y
when 16#379# => romdata <= X"00"; -- y
when 16#479# => romdata <= X"00"; -- y
when 16#579# => romdata <= X"42"; -- y
when 16#679# => romdata <= X"42"; -- y
when 16#779# => romdata <= X"42"; -- y
when 16#879# => romdata <= X"46"; -- y
when 16#979# => romdata <= X"3a"; -- y
when 16#a79# => romdata <= X"02"; -- y
when 16#b79# => romdata <= X"42"; -- y
when 16#c79# => romdata <= X"3c"; -- y
when 16#07a# => romdata <= X"00"; -- z
when 16#17a# => romdata <= X"00"; -- z
when 16#27a# => romdata <= X"00"; -- z
when 16#37a# => romdata <= X"00"; -- z
when 16#47a# => romdata <= X"00"; -- z
when 16#57a# => romdata <= X"7e"; -- z
when 16#67a# => romdata <= X"04"; -- z
when 16#77a# => romdata <= X"08"; -- z
when 16#87a# => romdata <= X"10"; -- z
when 16#97a# => romdata <= X"20"; -- z
when 16#a7a# => romdata <= X"7e"; -- z
when 16#b7a# => romdata <= X"00"; -- z
when 16#c7a# => romdata <= X"00"; -- z
when 16#07b# => romdata <= X"00"; -- {
when 16#17b# => romdata <= X"00"; -- {
when 16#27b# => romdata <= X"0e"; -- {
when 16#37b# => romdata <= X"10"; -- {
when 16#47b# => romdata <= X"10"; -- {
when 16#57b# => romdata <= X"08"; -- {
when 16#67b# => romdata <= X"30"; -- {
when 16#77b# => romdata <= X"08"; -- {
when 16#87b# => romdata <= X"10"; -- {
when 16#97b# => romdata <= X"10"; -- {
when 16#a7b# => romdata <= X"0e"; -- {
when 16#b7b# => romdata <= X"00"; -- {
when 16#c7b# => romdata <= X"00"; -- {
when 16#07c# => romdata <= X"00"; -- |
when 16#17c# => romdata <= X"00"; -- |
when 16#27c# => romdata <= X"10"; -- |
when 16#37c# => romdata <= X"10"; -- |
when 16#47c# => romdata <= X"10"; -- |
when 16#57c# => romdata <= X"10"; -- |
when 16#67c# => romdata <= X"10"; -- |
when 16#77c# => romdata <= X"10"; -- |
when 16#87c# => romdata <= X"10"; -- |
when 16#97c# => romdata <= X"10"; -- |
when 16#a7c# => romdata <= X"10"; -- |
when 16#b7c# => romdata <= X"00"; -- |
when 16#c7c# => romdata <= X"00"; -- |
when 16#07d# => romdata <= X"00"; -- }
when 16#17d# => romdata <= X"00"; -- }
when 16#27d# => romdata <= X"70"; -- }
when 16#37d# => romdata <= X"08"; -- }
when 16#47d# => romdata <= X"08"; -- }
when 16#57d# => romdata <= X"10"; -- }
when 16#67d# => romdata <= X"0c"; -- }
when 16#77d# => romdata <= X"10"; -- }
when 16#87d# => romdata <= X"08"; -- }
when 16#97d# => romdata <= X"08"; -- }
when 16#a7d# => romdata <= X"70"; -- }
when 16#b7d# => romdata <= X"00"; -- }
when 16#c7d# => romdata <= X"00"; -- }
when 16#07e# => romdata <= X"00"; -- ~
when 16#17e# => romdata <= X"00"; -- ~
when 16#27e# => romdata <= X"24"; -- ~
when 16#37e# => romdata <= X"54"; -- ~
when 16#47e# => romdata <= X"48"; -- ~
when 16#57e# => romdata <= X"00"; -- ~
when 16#67e# => romdata <= X"00"; -- ~
when 16#77e# => romdata <= X"00"; -- ~
when 16#87e# => romdata <= X"00"; -- ~
when 16#97e# => romdata <= X"00"; -- ~
when 16#a7e# => romdata <= X"00"; -- ~
when 16#b7e# => romdata <= X"00"; -- ~
when 16#c7e# => romdata <= X"00"; -- ~
when 16#0a0# => romdata <= X"00"; --
when 16#1a0# => romdata <= X"00"; --
when 16#2a0# => romdata <= X"00"; --
when 16#3a0# => romdata <= X"00"; --
when 16#4a0# => romdata <= X"00"; --
when 16#5a0# => romdata <= X"00"; --
when 16#6a0# => romdata <= X"00"; --
when 16#7a0# => romdata <= X"00"; --
when 16#8a0# => romdata <= X"00"; --
when 16#9a0# => romdata <= X"00"; --
when 16#aa0# => romdata <= X"00"; --
when 16#ba0# => romdata <= X"00"; --
when 16#ca0# => romdata <= X"00"; --
when 16#0a1# => romdata <= X"00"; -- ¡
when 16#1a1# => romdata <= X"00"; -- ¡
when 16#2a1# => romdata <= X"10"; -- ¡
when 16#3a1# => romdata <= X"00"; -- ¡
when 16#4a1# => romdata <= X"10"; -- ¡
when 16#5a1# => romdata <= X"10"; -- ¡
when 16#6a1# => romdata <= X"10"; -- ¡
when 16#7a1# => romdata <= X"10"; -- ¡
when 16#8a1# => romdata <= X"10"; -- ¡
when 16#9a1# => romdata <= X"10"; -- ¡
when 16#aa1# => romdata <= X"10"; -- ¡
when 16#ba1# => romdata <= X"00"; -- ¡
when 16#ca1# => romdata <= X"00"; -- ¡
when 16#0a2# => romdata <= X"00"; -- ¢
when 16#1a2# => romdata <= X"00"; -- ¢
when 16#2a2# => romdata <= X"10"; -- ¢
when 16#3a2# => romdata <= X"38"; -- ¢
when 16#4a2# => romdata <= X"54"; -- ¢
when 16#5a2# => romdata <= X"50"; -- ¢
when 16#6a2# => romdata <= X"50"; -- ¢
when 16#7a2# => romdata <= X"54"; -- ¢
when 16#8a2# => romdata <= X"38"; -- ¢
when 16#9a2# => romdata <= X"10"; -- ¢
when 16#aa2# => romdata <= X"00"; -- ¢
when 16#ba2# => romdata <= X"00"; -- ¢
when 16#ca2# => romdata <= X"00"; -- ¢
when 16#0a3# => romdata <= X"00"; -- £
when 16#1a3# => romdata <= X"00"; -- £
when 16#2a3# => romdata <= X"1c"; -- £
when 16#3a3# => romdata <= X"22"; -- £
when 16#4a3# => romdata <= X"20"; -- £
when 16#5a3# => romdata <= X"70"; -- £
when 16#6a3# => romdata <= X"20"; -- £
when 16#7a3# => romdata <= X"20"; -- £
when 16#8a3# => romdata <= X"20"; -- £
when 16#9a3# => romdata <= X"62"; -- £
when 16#aa3# => romdata <= X"dc"; -- £
when 16#ba3# => romdata <= X"00"; -- £
when 16#ca3# => romdata <= X"00"; -- £
when 16#0a4# => romdata <= X"00"; -- ¤
when 16#1a4# => romdata <= X"00"; -- ¤
when 16#2a4# => romdata <= X"00"; -- ¤
when 16#3a4# => romdata <= X"00"; -- ¤
when 16#4a4# => romdata <= X"42"; -- ¤
when 16#5a4# => romdata <= X"3c"; -- ¤
when 16#6a4# => romdata <= X"24"; -- ¤
when 16#7a4# => romdata <= X"24"; -- ¤
when 16#8a4# => romdata <= X"3c"; -- ¤
when 16#9a4# => romdata <= X"42"; -- ¤
when 16#aa4# => romdata <= X"00"; -- ¤
when 16#ba4# => romdata <= X"00"; -- ¤
when 16#ca4# => romdata <= X"00"; -- ¤
when 16#0a5# => romdata <= X"00"; -- ¥
when 16#1a5# => romdata <= X"00"; -- ¥
when 16#2a5# => romdata <= X"82"; -- ¥
when 16#3a5# => romdata <= X"82"; -- ¥
when 16#4a5# => romdata <= X"44"; -- ¥
when 16#5a5# => romdata <= X"28"; -- ¥
when 16#6a5# => romdata <= X"7c"; -- ¥
when 16#7a5# => romdata <= X"10"; -- ¥
when 16#8a5# => romdata <= X"7c"; -- ¥
when 16#9a5# => romdata <= X"10"; -- ¥
when 16#aa5# => romdata <= X"10"; -- ¥
when 16#ba5# => romdata <= X"00"; -- ¥
when 16#ca5# => romdata <= X"00"; -- ¥
when 16#0a6# => romdata <= X"00"; -- ¦
when 16#1a6# => romdata <= X"00"; -- ¦
when 16#2a6# => romdata <= X"10"; -- ¦
when 16#3a6# => romdata <= X"10"; -- ¦
when 16#4a6# => romdata <= X"10"; -- ¦
when 16#5a6# => romdata <= X"10"; -- ¦
when 16#6a6# => romdata <= X"00"; -- ¦
when 16#7a6# => romdata <= X"10"; -- ¦
when 16#8a6# => romdata <= X"10"; -- ¦
when 16#9a6# => romdata <= X"10"; -- ¦
when 16#aa6# => romdata <= X"10"; -- ¦
when 16#ba6# => romdata <= X"00"; -- ¦
when 16#ca6# => romdata <= X"00"; -- ¦
when 16#0a7# => romdata <= X"00"; -- §
when 16#1a7# => romdata <= X"18"; -- §
when 16#2a7# => romdata <= X"24"; -- §
when 16#3a7# => romdata <= X"20"; -- §
when 16#4a7# => romdata <= X"18"; -- §
when 16#5a7# => romdata <= X"24"; -- §
when 16#6a7# => romdata <= X"24"; -- §
when 16#7a7# => romdata <= X"18"; -- §
when 16#8a7# => romdata <= X"04"; -- §
when 16#9a7# => romdata <= X"24"; -- §
when 16#aa7# => romdata <= X"18"; -- §
when 16#ba7# => romdata <= X"00"; -- §
when 16#ca7# => romdata <= X"00"; -- §
when 16#0a8# => romdata <= X"00"; -- ¨
when 16#1a8# => romdata <= X"24"; -- ¨
when 16#2a8# => romdata <= X"24"; -- ¨
when 16#3a8# => romdata <= X"00"; -- ¨
when 16#4a8# => romdata <= X"00"; -- ¨
when 16#5a8# => romdata <= X"00"; -- ¨
when 16#6a8# => romdata <= X"00"; -- ¨
when 16#7a8# => romdata <= X"00"; -- ¨
when 16#8a8# => romdata <= X"00"; -- ¨
when 16#9a8# => romdata <= X"00"; -- ¨
when 16#aa8# => romdata <= X"00"; -- ¨
when 16#ba8# => romdata <= X"00"; -- ¨
when 16#ca8# => romdata <= X"00"; -- ¨
when 16#0a9# => romdata <= X"00"; -- ©
when 16#1a9# => romdata <= X"38"; -- ©
when 16#2a9# => romdata <= X"44"; -- ©
when 16#3a9# => romdata <= X"92"; -- ©
when 16#4a9# => romdata <= X"aa"; -- ©
when 16#5a9# => romdata <= X"a2"; -- ©
when 16#6a9# => romdata <= X"aa"; -- ©
when 16#7a9# => romdata <= X"92"; -- ©
when 16#8a9# => romdata <= X"44"; -- ©
when 16#9a9# => romdata <= X"38"; -- ©
when 16#aa9# => romdata <= X"00"; -- ©
when 16#ba9# => romdata <= X"00"; -- ©
when 16#ca9# => romdata <= X"00"; -- ©
when 16#0aa# => romdata <= X"00"; -- ª
when 16#1aa# => romdata <= X"00"; -- ª
when 16#2aa# => romdata <= X"38"; -- ª
when 16#3aa# => romdata <= X"04"; -- ª
when 16#4aa# => romdata <= X"3c"; -- ª
when 16#5aa# => romdata <= X"44"; -- ª
when 16#6aa# => romdata <= X"3c"; -- ª
when 16#7aa# => romdata <= X"00"; -- ª
when 16#8aa# => romdata <= X"7c"; -- ª
when 16#9aa# => romdata <= X"00"; -- ª
when 16#aaa# => romdata <= X"00"; -- ª
when 16#baa# => romdata <= X"00"; -- ª
when 16#caa# => romdata <= X"00"; -- ª
when 16#0ab# => romdata <= X"00"; -- «
when 16#1ab# => romdata <= X"00"; -- «
when 16#2ab# => romdata <= X"00"; -- «
when 16#3ab# => romdata <= X"12"; -- «
when 16#4ab# => romdata <= X"24"; -- «
when 16#5ab# => romdata <= X"48"; -- «
when 16#6ab# => romdata <= X"90"; -- «
when 16#7ab# => romdata <= X"48"; -- «
when 16#8ab# => romdata <= X"24"; -- «
when 16#9ab# => romdata <= X"12"; -- «
when 16#aab# => romdata <= X"00"; -- «
when 16#bab# => romdata <= X"00"; -- «
when 16#cab# => romdata <= X"00"; -- «
when 16#0ac# => romdata <= X"00"; -- ¬
when 16#1ac# => romdata <= X"00"; -- ¬
when 16#2ac# => romdata <= X"00"; -- ¬
when 16#3ac# => romdata <= X"00"; -- ¬
when 16#4ac# => romdata <= X"00"; -- ¬
when 16#5ac# => romdata <= X"00"; -- ¬
when 16#6ac# => romdata <= X"7e"; -- ¬
when 16#7ac# => romdata <= X"02"; -- ¬
when 16#8ac# => romdata <= X"02"; -- ¬
when 16#9ac# => romdata <= X"02"; -- ¬
when 16#aac# => romdata <= X"00"; -- ¬
when 16#bac# => romdata <= X"00"; -- ¬
when 16#cac# => romdata <= X"00"; -- ¬
when 16#0ad# => romdata <= X"00"; --
when 16#1ad# => romdata <= X"00"; --
when 16#2ad# => romdata <= X"00"; --
when 16#3ad# => romdata <= X"00"; --
when 16#4ad# => romdata <= X"00"; --
when 16#5ad# => romdata <= X"00"; --
when 16#6ad# => romdata <= X"3c"; --
when 16#7ad# => romdata <= X"00"; --
when 16#8ad# => romdata <= X"00"; --
when 16#9ad# => romdata <= X"00"; --
when 16#aad# => romdata <= X"00"; --
when 16#bad# => romdata <= X"00"; --
when 16#cad# => romdata <= X"00"; --
when 16#0ae# => romdata <= X"00"; -- ®
when 16#1ae# => romdata <= X"38"; -- ®
when 16#2ae# => romdata <= X"44"; -- ®
when 16#3ae# => romdata <= X"92"; -- ®
when 16#4ae# => romdata <= X"aa"; -- ®
when 16#5ae# => romdata <= X"aa"; -- ®
when 16#6ae# => romdata <= X"b2"; -- ®
when 16#7ae# => romdata <= X"aa"; -- ®
when 16#8ae# => romdata <= X"44"; -- ®
when 16#9ae# => romdata <= X"38"; -- ®
when 16#aae# => romdata <= X"00"; -- ®
when 16#bae# => romdata <= X"00"; -- ®
when 16#cae# => romdata <= X"00"; -- ®
when 16#0af# => romdata <= X"00"; -- ¯
when 16#1af# => romdata <= X"00"; -- ¯
when 16#2af# => romdata <= X"7e"; -- ¯
when 16#3af# => romdata <= X"00"; -- ¯
when 16#4af# => romdata <= X"00"; -- ¯
when 16#5af# => romdata <= X"00"; -- ¯
when 16#6af# => romdata <= X"00"; -- ¯
when 16#7af# => romdata <= X"00"; -- ¯
when 16#8af# => romdata <= X"00"; -- ¯
when 16#9af# => romdata <= X"00"; -- ¯
when 16#aaf# => romdata <= X"00"; -- ¯
when 16#baf# => romdata <= X"00"; -- ¯
when 16#caf# => romdata <= X"00"; -- ¯
when 16#0b0# => romdata <= X"00"; -- °
when 16#1b0# => romdata <= X"00"; -- °
when 16#2b0# => romdata <= X"18"; -- °
when 16#3b0# => romdata <= X"24"; -- °
when 16#4b0# => romdata <= X"24"; -- °
when 16#5b0# => romdata <= X"18"; -- °
when 16#6b0# => romdata <= X"00"; -- °
when 16#7b0# => romdata <= X"00"; -- °
when 16#8b0# => romdata <= X"00"; -- °
when 16#9b0# => romdata <= X"00"; -- °
when 16#ab0# => romdata <= X"00"; -- °
when 16#bb0# => romdata <= X"00"; -- °
when 16#cb0# => romdata <= X"00"; -- °
when 16#0b1# => romdata <= X"00"; -- ±
when 16#1b1# => romdata <= X"00"; -- ±
when 16#2b1# => romdata <= X"00"; -- ±
when 16#3b1# => romdata <= X"10"; -- ±
when 16#4b1# => romdata <= X"10"; -- ±
when 16#5b1# => romdata <= X"7c"; -- ±
when 16#6b1# => romdata <= X"10"; -- ±
when 16#7b1# => romdata <= X"10"; -- ±
when 16#8b1# => romdata <= X"00"; -- ±
when 16#9b1# => romdata <= X"7c"; -- ±
when 16#ab1# => romdata <= X"00"; -- ±
when 16#bb1# => romdata <= X"00"; -- ±
when 16#cb1# => romdata <= X"00"; -- ±
when 16#0b2# => romdata <= X"00"; -- ²
when 16#1b2# => romdata <= X"30"; -- ²
when 16#2b2# => romdata <= X"48"; -- ²
when 16#3b2# => romdata <= X"08"; -- ²
when 16#4b2# => romdata <= X"30"; -- ²
when 16#5b2# => romdata <= X"40"; -- ²
when 16#6b2# => romdata <= X"78"; -- ²
when 16#7b2# => romdata <= X"00"; -- ²
when 16#8b2# => romdata <= X"00"; -- ²
when 16#9b2# => romdata <= X"00"; -- ²
when 16#ab2# => romdata <= X"00"; -- ²
when 16#bb2# => romdata <= X"00"; -- ²
when 16#cb2# => romdata <= X"00"; -- ²
when 16#0b3# => romdata <= X"00"; -- ³
when 16#1b3# => romdata <= X"30"; -- ³
when 16#2b3# => romdata <= X"48"; -- ³
when 16#3b3# => romdata <= X"10"; -- ³
when 16#4b3# => romdata <= X"08"; -- ³
when 16#5b3# => romdata <= X"48"; -- ³
when 16#6b3# => romdata <= X"30"; -- ³
when 16#7b3# => romdata <= X"00"; -- ³
when 16#8b3# => romdata <= X"00"; -- ³
when 16#9b3# => romdata <= X"00"; -- ³
when 16#ab3# => romdata <= X"00"; -- ³
when 16#bb3# => romdata <= X"00"; -- ³
when 16#cb3# => romdata <= X"00"; -- ³
when 16#0b4# => romdata <= X"00"; -- ´
when 16#1b4# => romdata <= X"08"; -- ´
when 16#2b4# => romdata <= X"10"; -- ´
when 16#3b4# => romdata <= X"00"; -- ´
when 16#4b4# => romdata <= X"00"; -- ´
when 16#5b4# => romdata <= X"00"; -- ´
when 16#6b4# => romdata <= X"00"; -- ´
when 16#7b4# => romdata <= X"00"; -- ´
when 16#8b4# => romdata <= X"00"; -- ´
when 16#9b4# => romdata <= X"00"; -- ´
when 16#ab4# => romdata <= X"00"; -- ´
when 16#bb4# => romdata <= X"00"; -- ´
when 16#cb4# => romdata <= X"00"; -- ´
when 16#0b5# => romdata <= X"00"; -- µ
when 16#1b5# => romdata <= X"00"; -- µ
when 16#2b5# => romdata <= X"00"; -- µ
when 16#3b5# => romdata <= X"00"; -- µ
when 16#4b5# => romdata <= X"00"; -- µ
when 16#5b5# => romdata <= X"42"; -- µ
when 16#6b5# => romdata <= X"42"; -- µ
when 16#7b5# => romdata <= X"42"; -- µ
when 16#8b5# => romdata <= X"42"; -- µ
when 16#9b5# => romdata <= X"66"; -- µ
when 16#ab5# => romdata <= X"5a"; -- µ
when 16#bb5# => romdata <= X"40"; -- µ
when 16#cb5# => romdata <= X"00"; -- µ
when 16#0b6# => romdata <= X"00"; -- ¶
when 16#1b6# => romdata <= X"00"; -- ¶
when 16#2b6# => romdata <= X"3e"; -- ¶
when 16#3b6# => romdata <= X"74"; -- ¶
when 16#4b6# => romdata <= X"74"; -- ¶
when 16#5b6# => romdata <= X"74"; -- ¶
when 16#6b6# => romdata <= X"34"; -- ¶
when 16#7b6# => romdata <= X"14"; -- ¶
when 16#8b6# => romdata <= X"14"; -- ¶
when 16#9b6# => romdata <= X"14"; -- ¶
when 16#ab6# => romdata <= X"14"; -- ¶
when 16#bb6# => romdata <= X"00"; -- ¶
when 16#cb6# => romdata <= X"00"; -- ¶
when 16#0b7# => romdata <= X"00"; -- ·
when 16#1b7# => romdata <= X"00"; -- ·
when 16#2b7# => romdata <= X"00"; -- ·
when 16#3b7# => romdata <= X"00"; -- ·
when 16#4b7# => romdata <= X"00"; -- ·
when 16#5b7# => romdata <= X"00"; -- ·
when 16#6b7# => romdata <= X"18"; -- ·
when 16#7b7# => romdata <= X"00"; -- ·
when 16#8b7# => romdata <= X"00"; -- ·
when 16#9b7# => romdata <= X"00"; -- ·
when 16#ab7# => romdata <= X"00"; -- ·
when 16#bb7# => romdata <= X"00"; -- ·
when 16#cb7# => romdata <= X"00"; -- ·
when 16#0b8# => romdata <= X"00"; -- ¸
when 16#1b8# => romdata <= X"00"; -- ¸
when 16#2b8# => romdata <= X"00"; -- ¸
when 16#3b8# => romdata <= X"00"; -- ¸
when 16#4b8# => romdata <= X"00"; -- ¸
when 16#5b8# => romdata <= X"00"; -- ¸
when 16#6b8# => romdata <= X"00"; -- ¸
when 16#7b8# => romdata <= X"00"; -- ¸
when 16#8b8# => romdata <= X"00"; -- ¸
when 16#9b8# => romdata <= X"00"; -- ¸
when 16#ab8# => romdata <= X"00"; -- ¸
when 16#bb8# => romdata <= X"08"; -- ¸
when 16#cb8# => romdata <= X"18"; -- ¸
when 16#0b9# => romdata <= X"00"; -- ¹
when 16#1b9# => romdata <= X"20"; -- ¹
when 16#2b9# => romdata <= X"60"; -- ¹
when 16#3b9# => romdata <= X"20"; -- ¹
when 16#4b9# => romdata <= X"20"; -- ¹
when 16#5b9# => romdata <= X"20"; -- ¹
when 16#6b9# => romdata <= X"70"; -- ¹
when 16#7b9# => romdata <= X"00"; -- ¹
when 16#8b9# => romdata <= X"00"; -- ¹
when 16#9b9# => romdata <= X"00"; -- ¹
when 16#ab9# => romdata <= X"00"; -- ¹
when 16#bb9# => romdata <= X"00"; -- ¹
when 16#cb9# => romdata <= X"00"; -- ¹
when 16#0ba# => romdata <= X"00"; -- º
when 16#1ba# => romdata <= X"00"; -- º
when 16#2ba# => romdata <= X"30"; -- º
when 16#3ba# => romdata <= X"48"; -- º
when 16#4ba# => romdata <= X"48"; -- º
when 16#5ba# => romdata <= X"30"; -- º
when 16#6ba# => romdata <= X"00"; -- º
when 16#7ba# => romdata <= X"78"; -- º
when 16#8ba# => romdata <= X"00"; -- º
when 16#9ba# => romdata <= X"00"; -- º
when 16#aba# => romdata <= X"00"; -- º
when 16#bba# => romdata <= X"00"; -- º
when 16#cba# => romdata <= X"00"; -- º
when 16#0bb# => romdata <= X"00"; -- »
when 16#1bb# => romdata <= X"00"; -- »
when 16#2bb# => romdata <= X"00"; -- »
when 16#3bb# => romdata <= X"90"; -- »
when 16#4bb# => romdata <= X"48"; -- »
when 16#5bb# => romdata <= X"24"; -- »
when 16#6bb# => romdata <= X"12"; -- »
when 16#7bb# => romdata <= X"24"; -- »
when 16#8bb# => romdata <= X"48"; -- »
when 16#9bb# => romdata <= X"90"; -- »
when 16#abb# => romdata <= X"00"; -- »
when 16#bbb# => romdata <= X"00"; -- »
when 16#cbb# => romdata <= X"00"; -- »
when 16#0bc# => romdata <= X"00"; -- ¼
when 16#1bc# => romdata <= X"40"; -- ¼
when 16#2bc# => romdata <= X"c0"; -- ¼
when 16#3bc# => romdata <= X"40"; -- ¼
when 16#4bc# => romdata <= X"40"; -- ¼
when 16#5bc# => romdata <= X"42"; -- ¼
when 16#6bc# => romdata <= X"e6"; -- ¼
when 16#7bc# => romdata <= X"0a"; -- ¼
when 16#8bc# => romdata <= X"12"; -- ¼
when 16#9bc# => romdata <= X"1a"; -- ¼
when 16#abc# => romdata <= X"06"; -- ¼
when 16#bbc# => romdata <= X"00"; -- ¼
when 16#cbc# => romdata <= X"00"; -- ¼
when 16#0bd# => romdata <= X"00"; -- ½
when 16#1bd# => romdata <= X"40"; -- ½
when 16#2bd# => romdata <= X"c0"; -- ½
when 16#3bd# => romdata <= X"40"; -- ½
when 16#4bd# => romdata <= X"40"; -- ½
when 16#5bd# => romdata <= X"4c"; -- ½
when 16#6bd# => romdata <= X"f2"; -- ½
when 16#7bd# => romdata <= X"02"; -- ½
when 16#8bd# => romdata <= X"0c"; -- ½
when 16#9bd# => romdata <= X"10"; -- ½
when 16#abd# => romdata <= X"1e"; -- ½
when 16#bbd# => romdata <= X"00"; -- ½
when 16#cbd# => romdata <= X"00"; -- ½
when 16#0be# => romdata <= X"00"; -- ¾
when 16#1be# => romdata <= X"60"; -- ¾
when 16#2be# => romdata <= X"90"; -- ¾
when 16#3be# => romdata <= X"20"; -- ¾
when 16#4be# => romdata <= X"10"; -- ¾
when 16#5be# => romdata <= X"92"; -- ¾
when 16#6be# => romdata <= X"66"; -- ¾
when 16#7be# => romdata <= X"0a"; -- ¾
when 16#8be# => romdata <= X"12"; -- ¾
when 16#9be# => romdata <= X"1a"; -- ¾
when 16#abe# => romdata <= X"06"; -- ¾
when 16#bbe# => romdata <= X"00"; -- ¾
when 16#cbe# => romdata <= X"00"; -- ¾
when 16#0bf# => romdata <= X"00"; -- ¿
when 16#1bf# => romdata <= X"00"; -- ¿
when 16#2bf# => romdata <= X"10"; -- ¿
when 16#3bf# => romdata <= X"00"; -- ¿
when 16#4bf# => romdata <= X"10"; -- ¿
when 16#5bf# => romdata <= X"10"; -- ¿
when 16#6bf# => romdata <= X"20"; -- ¿
when 16#7bf# => romdata <= X"40"; -- ¿
when 16#8bf# => romdata <= X"42"; -- ¿
when 16#9bf# => romdata <= X"42"; -- ¿
when 16#abf# => romdata <= X"3c"; -- ¿
when 16#bbf# => romdata <= X"00"; -- ¿
when 16#cbf# => romdata <= X"00"; -- ¿
when 16#0c0# => romdata <= X"00"; -- À
when 16#1c0# => romdata <= X"10"; -- À
when 16#2c0# => romdata <= X"08"; -- À
when 16#3c0# => romdata <= X"00"; -- À
when 16#4c0# => romdata <= X"18"; -- À
when 16#5c0# => romdata <= X"24"; -- À
when 16#6c0# => romdata <= X"42"; -- À
when 16#7c0# => romdata <= X"42"; -- À
when 16#8c0# => romdata <= X"7e"; -- À
when 16#9c0# => romdata <= X"42"; -- À
when 16#ac0# => romdata <= X"42"; -- À
when 16#bc0# => romdata <= X"00"; -- À
when 16#cc0# => romdata <= X"00"; -- À
when 16#0c1# => romdata <= X"00"; -- Á
when 16#1c1# => romdata <= X"08"; -- Á
when 16#2c1# => romdata <= X"10"; -- Á
when 16#3c1# => romdata <= X"00"; -- Á
when 16#4c1# => romdata <= X"18"; -- Á
when 16#5c1# => romdata <= X"24"; -- Á
when 16#6c1# => romdata <= X"42"; -- Á
when 16#7c1# => romdata <= X"42"; -- Á
when 16#8c1# => romdata <= X"7e"; -- Á
when 16#9c1# => romdata <= X"42"; -- Á
when 16#ac1# => romdata <= X"42"; -- Á
when 16#bc1# => romdata <= X"00"; -- Á
when 16#cc1# => romdata <= X"00"; -- Á
when 16#0c2# => romdata <= X"00"; -- Â
when 16#1c2# => romdata <= X"18"; -- Â
when 16#2c2# => romdata <= X"24"; -- Â
when 16#3c2# => romdata <= X"00"; -- Â
when 16#4c2# => romdata <= X"18"; -- Â
when 16#5c2# => romdata <= X"24"; -- Â
when 16#6c2# => romdata <= X"42"; -- Â
when 16#7c2# => romdata <= X"42"; -- Â
when 16#8c2# => romdata <= X"7e"; -- Â
when 16#9c2# => romdata <= X"42"; -- Â
when 16#ac2# => romdata <= X"42"; -- Â
when 16#bc2# => romdata <= X"00"; -- Â
when 16#cc2# => romdata <= X"00"; -- Â
when 16#0c3# => romdata <= X"00"; -- Ã
when 16#1c3# => romdata <= X"32"; -- Ã
when 16#2c3# => romdata <= X"4c"; -- Ã
when 16#3c3# => romdata <= X"00"; -- Ã
when 16#4c3# => romdata <= X"18"; -- Ã
when 16#5c3# => romdata <= X"24"; -- Ã
when 16#6c3# => romdata <= X"42"; -- Ã
when 16#7c3# => romdata <= X"42"; -- Ã
when 16#8c3# => romdata <= X"7e"; -- Ã
when 16#9c3# => romdata <= X"42"; -- Ã
when 16#ac3# => romdata <= X"42"; -- Ã
when 16#bc3# => romdata <= X"00"; -- Ã
when 16#cc3# => romdata <= X"00"; -- Ã
when 16#0c4# => romdata <= X"00"; -- Ä
when 16#1c4# => romdata <= X"24"; -- Ä
when 16#2c4# => romdata <= X"24"; -- Ä
when 16#3c4# => romdata <= X"00"; -- Ä
when 16#4c4# => romdata <= X"18"; -- Ä
when 16#5c4# => romdata <= X"24"; -- Ä
when 16#6c4# => romdata <= X"42"; -- Ä
when 16#7c4# => romdata <= X"42"; -- Ä
when 16#8c4# => romdata <= X"7e"; -- Ä
when 16#9c4# => romdata <= X"42"; -- Ä
when 16#ac4# => romdata <= X"42"; -- Ä
when 16#bc4# => romdata <= X"00"; -- Ä
when 16#cc4# => romdata <= X"00"; -- Ä
when 16#0c5# => romdata <= X"00"; -- Å
when 16#1c5# => romdata <= X"18"; -- Å
when 16#2c5# => romdata <= X"24"; -- Å
when 16#3c5# => romdata <= X"18"; -- Å
when 16#4c5# => romdata <= X"18"; -- Å
when 16#5c5# => romdata <= X"24"; -- Å
when 16#6c5# => romdata <= X"42"; -- Å
when 16#7c5# => romdata <= X"42"; -- Å
when 16#8c5# => romdata <= X"7e"; -- Å
when 16#9c5# => romdata <= X"42"; -- Å
when 16#ac5# => romdata <= X"42"; -- Å
when 16#bc5# => romdata <= X"00"; -- Å
when 16#cc5# => romdata <= X"00"; -- Å
when 16#0c6# => romdata <= X"00"; -- Æ
when 16#1c6# => romdata <= X"00"; -- Æ
when 16#2c6# => romdata <= X"6e"; -- Æ
when 16#3c6# => romdata <= X"90"; -- Æ
when 16#4c6# => romdata <= X"90"; -- Æ
when 16#5c6# => romdata <= X"90"; -- Æ
when 16#6c6# => romdata <= X"9c"; -- Æ
when 16#7c6# => romdata <= X"f0"; -- Æ
when 16#8c6# => romdata <= X"90"; -- Æ
when 16#9c6# => romdata <= X"90"; -- Æ
when 16#ac6# => romdata <= X"9e"; -- Æ
when 16#bc6# => romdata <= X"00"; -- Æ
when 16#cc6# => romdata <= X"00"; -- Æ
when 16#0c7# => romdata <= X"00"; -- Ç
when 16#1c7# => romdata <= X"00"; -- Ç
when 16#2c7# => romdata <= X"3c"; -- Ç
when 16#3c7# => romdata <= X"42"; -- Ç
when 16#4c7# => romdata <= X"40"; -- Ç
when 16#5c7# => romdata <= X"40"; -- Ç
when 16#6c7# => romdata <= X"40"; -- Ç
when 16#7c7# => romdata <= X"40"; -- Ç
when 16#8c7# => romdata <= X"40"; -- Ç
when 16#9c7# => romdata <= X"42"; -- Ç
when 16#ac7# => romdata <= X"3c"; -- Ç
when 16#bc7# => romdata <= X"08"; -- Ç
when 16#cc7# => romdata <= X"10"; -- Ç
when 16#0c8# => romdata <= X"00"; -- È
when 16#1c8# => romdata <= X"10"; -- È
when 16#2c8# => romdata <= X"08"; -- È
when 16#3c8# => romdata <= X"00"; -- È
when 16#4c8# => romdata <= X"7e"; -- È
when 16#5c8# => romdata <= X"40"; -- È
when 16#6c8# => romdata <= X"40"; -- È
when 16#7c8# => romdata <= X"78"; -- È
when 16#8c8# => romdata <= X"40"; -- È
when 16#9c8# => romdata <= X"40"; -- È
when 16#ac8# => romdata <= X"7e"; -- È
when 16#bc8# => romdata <= X"00"; -- È
when 16#cc8# => romdata <= X"00"; -- È
when 16#0c9# => romdata <= X"00"; -- É
when 16#1c9# => romdata <= X"08"; -- É
when 16#2c9# => romdata <= X"10"; -- É
when 16#3c9# => romdata <= X"00"; -- É
when 16#4c9# => romdata <= X"7e"; -- É
when 16#5c9# => romdata <= X"40"; -- É
when 16#6c9# => romdata <= X"40"; -- É
when 16#7c9# => romdata <= X"78"; -- É
when 16#8c9# => romdata <= X"40"; -- É
when 16#9c9# => romdata <= X"40"; -- É
when 16#ac9# => romdata <= X"7e"; -- É
when 16#bc9# => romdata <= X"00"; -- É
when 16#cc9# => romdata <= X"00"; -- É
when 16#0ca# => romdata <= X"00"; -- Ê
when 16#1ca# => romdata <= X"18"; -- Ê
when 16#2ca# => romdata <= X"24"; -- Ê
when 16#3ca# => romdata <= X"00"; -- Ê
when 16#4ca# => romdata <= X"7e"; -- Ê
when 16#5ca# => romdata <= X"40"; -- Ê
when 16#6ca# => romdata <= X"40"; -- Ê
when 16#7ca# => romdata <= X"78"; -- Ê
when 16#8ca# => romdata <= X"40"; -- Ê
when 16#9ca# => romdata <= X"40"; -- Ê
when 16#aca# => romdata <= X"7e"; -- Ê
when 16#bca# => romdata <= X"00"; -- Ê
when 16#cca# => romdata <= X"00"; -- Ê
when 16#0cb# => romdata <= X"00"; -- Ë
when 16#1cb# => romdata <= X"24"; -- Ë
when 16#2cb# => romdata <= X"24"; -- Ë
when 16#3cb# => romdata <= X"00"; -- Ë
when 16#4cb# => romdata <= X"7e"; -- Ë
when 16#5cb# => romdata <= X"40"; -- Ë
when 16#6cb# => romdata <= X"40"; -- Ë
when 16#7cb# => romdata <= X"78"; -- Ë
when 16#8cb# => romdata <= X"40"; -- Ë
when 16#9cb# => romdata <= X"40"; -- Ë
when 16#acb# => romdata <= X"7e"; -- Ë
when 16#bcb# => romdata <= X"00"; -- Ë
when 16#ccb# => romdata <= X"00"; -- Ë
when 16#0cc# => romdata <= X"00"; -- Ì
when 16#1cc# => romdata <= X"20"; -- Ì
when 16#2cc# => romdata <= X"10"; -- Ì
when 16#3cc# => romdata <= X"00"; -- Ì
when 16#4cc# => romdata <= X"7c"; -- Ì
when 16#5cc# => romdata <= X"10"; -- Ì
when 16#6cc# => romdata <= X"10"; -- Ì
when 16#7cc# => romdata <= X"10"; -- Ì
when 16#8cc# => romdata <= X"10"; -- Ì
when 16#9cc# => romdata <= X"10"; -- Ì
when 16#acc# => romdata <= X"7c"; -- Ì
when 16#bcc# => romdata <= X"00"; -- Ì
when 16#ccc# => romdata <= X"00"; -- Ì
when 16#0cd# => romdata <= X"00"; -- Í
when 16#1cd# => romdata <= X"08"; -- Í
when 16#2cd# => romdata <= X"10"; -- Í
when 16#3cd# => romdata <= X"00"; -- Í
when 16#4cd# => romdata <= X"7c"; -- Í
when 16#5cd# => romdata <= X"10"; -- Í
when 16#6cd# => romdata <= X"10"; -- Í
when 16#7cd# => romdata <= X"10"; -- Í
when 16#8cd# => romdata <= X"10"; -- Í
when 16#9cd# => romdata <= X"10"; -- Í
when 16#acd# => romdata <= X"7c"; -- Í
when 16#bcd# => romdata <= X"00"; -- Í
when 16#ccd# => romdata <= X"00"; -- Í
when 16#0ce# => romdata <= X"00"; -- Î
when 16#1ce# => romdata <= X"18"; -- Î
when 16#2ce# => romdata <= X"24"; -- Î
when 16#3ce# => romdata <= X"00"; -- Î
when 16#4ce# => romdata <= X"7c"; -- Î
when 16#5ce# => romdata <= X"10"; -- Î
when 16#6ce# => romdata <= X"10"; -- Î
when 16#7ce# => romdata <= X"10"; -- Î
when 16#8ce# => romdata <= X"10"; -- Î
when 16#9ce# => romdata <= X"10"; -- Î
when 16#ace# => romdata <= X"7c"; -- Î
when 16#bce# => romdata <= X"00"; -- Î
when 16#cce# => romdata <= X"00"; -- Î
when 16#0cf# => romdata <= X"00"; -- Ï
when 16#1cf# => romdata <= X"44"; -- Ï
when 16#2cf# => romdata <= X"44"; -- Ï
when 16#3cf# => romdata <= X"00"; -- Ï
when 16#4cf# => romdata <= X"7c"; -- Ï
when 16#5cf# => romdata <= X"10"; -- Ï
when 16#6cf# => romdata <= X"10"; -- Ï
when 16#7cf# => romdata <= X"10"; -- Ï
when 16#8cf# => romdata <= X"10"; -- Ï
when 16#9cf# => romdata <= X"10"; -- Ï
when 16#acf# => romdata <= X"7c"; -- Ï
when 16#bcf# => romdata <= X"00"; -- Ï
when 16#ccf# => romdata <= X"00"; -- Ï
when 16#0d0# => romdata <= X"00"; -- Ð
when 16#1d0# => romdata <= X"00"; -- Ð
when 16#2d0# => romdata <= X"78"; -- Ð
when 16#3d0# => romdata <= X"44"; -- Ð
when 16#4d0# => romdata <= X"42"; -- Ð
when 16#5d0# => romdata <= X"42"; -- Ð
when 16#6d0# => romdata <= X"e2"; -- Ð
when 16#7d0# => romdata <= X"42"; -- Ð
when 16#8d0# => romdata <= X"42"; -- Ð
when 16#9d0# => romdata <= X"44"; -- Ð
when 16#ad0# => romdata <= X"78"; -- Ð
when 16#bd0# => romdata <= X"00"; -- Ð
when 16#cd0# => romdata <= X"00"; -- Ð
when 16#0d1# => romdata <= X"00"; -- Ñ
when 16#1d1# => romdata <= X"64"; -- Ñ
when 16#2d1# => romdata <= X"98"; -- Ñ
when 16#3d1# => romdata <= X"00"; -- Ñ
when 16#4d1# => romdata <= X"82"; -- Ñ
when 16#5d1# => romdata <= X"c2"; -- Ñ
when 16#6d1# => romdata <= X"a2"; -- Ñ
when 16#7d1# => romdata <= X"92"; -- Ñ
when 16#8d1# => romdata <= X"8a"; -- Ñ
when 16#9d1# => romdata <= X"86"; -- Ñ
when 16#ad1# => romdata <= X"82"; -- Ñ
when 16#bd1# => romdata <= X"00"; -- Ñ
when 16#cd1# => romdata <= X"00"; -- Ñ
when 16#0d2# => romdata <= X"00"; -- Ò
when 16#1d2# => romdata <= X"20"; -- Ò
when 16#2d2# => romdata <= X"10"; -- Ò
when 16#3d2# => romdata <= X"00"; -- Ò
when 16#4d2# => romdata <= X"7c"; -- Ò
when 16#5d2# => romdata <= X"82"; -- Ò
when 16#6d2# => romdata <= X"82"; -- Ò
when 16#7d2# => romdata <= X"82"; -- Ò
when 16#8d2# => romdata <= X"82"; -- Ò
when 16#9d2# => romdata <= X"82"; -- Ò
when 16#ad2# => romdata <= X"7c"; -- Ò
when 16#bd2# => romdata <= X"00"; -- Ò
when 16#cd2# => romdata <= X"00"; -- Ò
when 16#0d3# => romdata <= X"00"; -- Ó
when 16#1d3# => romdata <= X"08"; -- Ó
when 16#2d3# => romdata <= X"10"; -- Ó
when 16#3d3# => romdata <= X"00"; -- Ó
when 16#4d3# => romdata <= X"7c"; -- Ó
when 16#5d3# => romdata <= X"82"; -- Ó
when 16#6d3# => romdata <= X"82"; -- Ó
when 16#7d3# => romdata <= X"82"; -- Ó
when 16#8d3# => romdata <= X"82"; -- Ó
when 16#9d3# => romdata <= X"82"; -- Ó
when 16#ad3# => romdata <= X"7c"; -- Ó
when 16#bd3# => romdata <= X"00"; -- Ó
when 16#cd3# => romdata <= X"00"; -- Ó
when 16#0d4# => romdata <= X"00"; -- Ô
when 16#1d4# => romdata <= X"18"; -- Ô
when 16#2d4# => romdata <= X"24"; -- Ô
when 16#3d4# => romdata <= X"00"; -- Ô
when 16#4d4# => romdata <= X"7c"; -- Ô
when 16#5d4# => romdata <= X"82"; -- Ô
when 16#6d4# => romdata <= X"82"; -- Ô
when 16#7d4# => romdata <= X"82"; -- Ô
when 16#8d4# => romdata <= X"82"; -- Ô
when 16#9d4# => romdata <= X"82"; -- Ô
when 16#ad4# => romdata <= X"7c"; -- Ô
when 16#bd4# => romdata <= X"00"; -- Ô
when 16#cd4# => romdata <= X"00"; -- Ô
when 16#0d5# => romdata <= X"00"; -- Õ
when 16#1d5# => romdata <= X"64"; -- Õ
when 16#2d5# => romdata <= X"98"; -- Õ
when 16#3d5# => romdata <= X"00"; -- Õ
when 16#4d5# => romdata <= X"7c"; -- Õ
when 16#5d5# => romdata <= X"82"; -- Õ
when 16#6d5# => romdata <= X"82"; -- Õ
when 16#7d5# => romdata <= X"82"; -- Õ
when 16#8d5# => romdata <= X"82"; -- Õ
when 16#9d5# => romdata <= X"82"; -- Õ
when 16#ad5# => romdata <= X"7c"; -- Õ
when 16#bd5# => romdata <= X"00"; -- Õ
when 16#cd5# => romdata <= X"00"; -- Õ
when 16#0d6# => romdata <= X"00"; -- Ö
when 16#1d6# => romdata <= X"44"; -- Ö
when 16#2d6# => romdata <= X"44"; -- Ö
when 16#3d6# => romdata <= X"00"; -- Ö
when 16#4d6# => romdata <= X"7c"; -- Ö
when 16#5d6# => romdata <= X"82"; -- Ö
when 16#6d6# => romdata <= X"82"; -- Ö
when 16#7d6# => romdata <= X"82"; -- Ö
when 16#8d6# => romdata <= X"82"; -- Ö
when 16#9d6# => romdata <= X"82"; -- Ö
when 16#ad6# => romdata <= X"7c"; -- Ö
when 16#bd6# => romdata <= X"00"; -- Ö
when 16#cd6# => romdata <= X"00"; -- Ö
when 16#0d7# => romdata <= X"00"; -- ×
when 16#1d7# => romdata <= X"00"; -- ×
when 16#2d7# => romdata <= X"00"; -- ×
when 16#3d7# => romdata <= X"00"; -- ×
when 16#4d7# => romdata <= X"42"; -- ×
when 16#5d7# => romdata <= X"24"; -- ×
when 16#6d7# => romdata <= X"18"; -- ×
when 16#7d7# => romdata <= X"18"; -- ×
when 16#8d7# => romdata <= X"24"; -- ×
when 16#9d7# => romdata <= X"42"; -- ×
when 16#ad7# => romdata <= X"00"; -- ×
when 16#bd7# => romdata <= X"00"; -- ×
when 16#cd7# => romdata <= X"00"; -- ×
when 16#0d8# => romdata <= X"00"; -- Ø
when 16#1d8# => romdata <= X"02"; -- Ø
when 16#2d8# => romdata <= X"3c"; -- Ø
when 16#3d8# => romdata <= X"46"; -- Ø
when 16#4d8# => romdata <= X"4a"; -- Ø
when 16#5d8# => romdata <= X"4a"; -- Ø
when 16#6d8# => romdata <= X"52"; -- Ø
when 16#7d8# => romdata <= X"52"; -- Ø
when 16#8d8# => romdata <= X"52"; -- Ø
when 16#9d8# => romdata <= X"62"; -- Ø
when 16#ad8# => romdata <= X"3c"; -- Ø
when 16#bd8# => romdata <= X"40"; -- Ø
when 16#cd8# => romdata <= X"00"; -- Ø
when 16#0d9# => romdata <= X"00"; -- Ù
when 16#1d9# => romdata <= X"20"; -- Ù
when 16#2d9# => romdata <= X"10"; -- Ù
when 16#3d9# => romdata <= X"00"; -- Ù
when 16#4d9# => romdata <= X"42"; -- Ù
when 16#5d9# => romdata <= X"42"; -- Ù
when 16#6d9# => romdata <= X"42"; -- Ù
when 16#7d9# => romdata <= X"42"; -- Ù
when 16#8d9# => romdata <= X"42"; -- Ù
when 16#9d9# => romdata <= X"42"; -- Ù
when 16#ad9# => romdata <= X"3c"; -- Ù
when 16#bd9# => romdata <= X"00"; -- Ù
when 16#cd9# => romdata <= X"00"; -- Ù
when 16#0da# => romdata <= X"00"; -- Ú
when 16#1da# => romdata <= X"08"; -- Ú
when 16#2da# => romdata <= X"10"; -- Ú
when 16#3da# => romdata <= X"00"; -- Ú
when 16#4da# => romdata <= X"42"; -- Ú
when 16#5da# => romdata <= X"42"; -- Ú
when 16#6da# => romdata <= X"42"; -- Ú
when 16#7da# => romdata <= X"42"; -- Ú
when 16#8da# => romdata <= X"42"; -- Ú
when 16#9da# => romdata <= X"42"; -- Ú
when 16#ada# => romdata <= X"3c"; -- Ú
when 16#bda# => romdata <= X"00"; -- Ú
when 16#cda# => romdata <= X"00"; -- Ú
when 16#0db# => romdata <= X"00"; -- Û
when 16#1db# => romdata <= X"18"; -- Û
when 16#2db# => romdata <= X"24"; -- Û
when 16#3db# => romdata <= X"00"; -- Û
when 16#4db# => romdata <= X"42"; -- Û
when 16#5db# => romdata <= X"42"; -- Û
when 16#6db# => romdata <= X"42"; -- Û
when 16#7db# => romdata <= X"42"; -- Û
when 16#8db# => romdata <= X"42"; -- Û
when 16#9db# => romdata <= X"42"; -- Û
when 16#adb# => romdata <= X"3c"; -- Û
when 16#bdb# => romdata <= X"00"; -- Û
when 16#cdb# => romdata <= X"00"; -- Û
when 16#0dc# => romdata <= X"00"; -- Ü
when 16#1dc# => romdata <= X"24"; -- Ü
when 16#2dc# => romdata <= X"24"; -- Ü
when 16#3dc# => romdata <= X"00"; -- Ü
when 16#4dc# => romdata <= X"42"; -- Ü
when 16#5dc# => romdata <= X"42"; -- Ü
when 16#6dc# => romdata <= X"42"; -- Ü
when 16#7dc# => romdata <= X"42"; -- Ü
when 16#8dc# => romdata <= X"42"; -- Ü
when 16#9dc# => romdata <= X"42"; -- Ü
when 16#adc# => romdata <= X"3c"; -- Ü
when 16#bdc# => romdata <= X"00"; -- Ü
when 16#cdc# => romdata <= X"00"; -- Ü
when 16#0dd# => romdata <= X"00"; -- Ý
when 16#1dd# => romdata <= X"08"; -- Ý
when 16#2dd# => romdata <= X"10"; -- Ý
when 16#3dd# => romdata <= X"00"; -- Ý
when 16#4dd# => romdata <= X"44"; -- Ý
when 16#5dd# => romdata <= X"44"; -- Ý
when 16#6dd# => romdata <= X"28"; -- Ý
when 16#7dd# => romdata <= X"10"; -- Ý
when 16#8dd# => romdata <= X"10"; -- Ý
when 16#9dd# => romdata <= X"10"; -- Ý
when 16#add# => romdata <= X"10"; -- Ý
when 16#bdd# => romdata <= X"00"; -- Ý
when 16#cdd# => romdata <= X"00"; -- Ý
when 16#0de# => romdata <= X"00"; -- Þ
when 16#1de# => romdata <= X"00"; -- Þ
when 16#2de# => romdata <= X"40"; -- Þ
when 16#3de# => romdata <= X"7c"; -- Þ
when 16#4de# => romdata <= X"42"; -- Þ
when 16#5de# => romdata <= X"42"; -- Þ
when 16#6de# => romdata <= X"42"; -- Þ
when 16#7de# => romdata <= X"7c"; -- Þ
when 16#8de# => romdata <= X"40"; -- Þ
when 16#9de# => romdata <= X"40"; -- Þ
when 16#ade# => romdata <= X"40"; -- Þ
when 16#bde# => romdata <= X"00"; -- Þ
when 16#cde# => romdata <= X"00"; -- Þ
when 16#0df# => romdata <= X"00"; -- ß
when 16#1df# => romdata <= X"00"; -- ß
when 16#2df# => romdata <= X"38"; -- ß
when 16#3df# => romdata <= X"44"; -- ß
when 16#4df# => romdata <= X"44"; -- ß
when 16#5df# => romdata <= X"48"; -- ß
when 16#6df# => romdata <= X"50"; -- ß
when 16#7df# => romdata <= X"4c"; -- ß
when 16#8df# => romdata <= X"42"; -- ß
when 16#9df# => romdata <= X"42"; -- ß
when 16#adf# => romdata <= X"5c"; -- ß
when 16#bdf# => romdata <= X"00"; -- ß
when 16#cdf# => romdata <= X"00"; -- ß
when 16#0e0# => romdata <= X"00"; -- à
when 16#1e0# => romdata <= X"00"; -- à
when 16#2e0# => romdata <= X"10"; -- à
when 16#3e0# => romdata <= X"08"; -- à
when 16#4e0# => romdata <= X"00"; -- à
when 16#5e0# => romdata <= X"3c"; -- à
when 16#6e0# => romdata <= X"02"; -- à
when 16#7e0# => romdata <= X"3e"; -- à
when 16#8e0# => romdata <= X"42"; -- à
when 16#9e0# => romdata <= X"46"; -- à
when 16#ae0# => romdata <= X"3a"; -- à
when 16#be0# => romdata <= X"00"; -- à
when 16#ce0# => romdata <= X"00"; -- à
when 16#0e1# => romdata <= X"00"; -- á
when 16#1e1# => romdata <= X"00"; -- á
when 16#2e1# => romdata <= X"04"; -- á
when 16#3e1# => romdata <= X"08"; -- á
when 16#4e1# => romdata <= X"00"; -- á
when 16#5e1# => romdata <= X"3c"; -- á
when 16#6e1# => romdata <= X"02"; -- á
when 16#7e1# => romdata <= X"3e"; -- á
when 16#8e1# => romdata <= X"42"; -- á
when 16#9e1# => romdata <= X"46"; -- á
when 16#ae1# => romdata <= X"3a"; -- á
when 16#be1# => romdata <= X"00"; -- á
when 16#ce1# => romdata <= X"00"; -- á
when 16#0e2# => romdata <= X"00"; -- â
when 16#1e2# => romdata <= X"00"; -- â
when 16#2e2# => romdata <= X"18"; -- â
when 16#3e2# => romdata <= X"24"; -- â
when 16#4e2# => romdata <= X"00"; -- â
when 16#5e2# => romdata <= X"3c"; -- â
when 16#6e2# => romdata <= X"02"; -- â
when 16#7e2# => romdata <= X"3e"; -- â
when 16#8e2# => romdata <= X"42"; -- â
when 16#9e2# => romdata <= X"46"; -- â
when 16#ae2# => romdata <= X"3a"; -- â
when 16#be2# => romdata <= X"00"; -- â
when 16#ce2# => romdata <= X"00"; -- â
when 16#0e3# => romdata <= X"00"; -- ã
when 16#1e3# => romdata <= X"00"; -- ã
when 16#2e3# => romdata <= X"32"; -- ã
when 16#3e3# => romdata <= X"4c"; -- ã
when 16#4e3# => romdata <= X"00"; -- ã
when 16#5e3# => romdata <= X"3c"; -- ã
when 16#6e3# => romdata <= X"02"; -- ã
when 16#7e3# => romdata <= X"3e"; -- ã
when 16#8e3# => romdata <= X"42"; -- ã
when 16#9e3# => romdata <= X"46"; -- ã
when 16#ae3# => romdata <= X"3a"; -- ã
when 16#be3# => romdata <= X"00"; -- ã
when 16#ce3# => romdata <= X"00"; -- ã
when 16#0e4# => romdata <= X"00"; -- ä
when 16#1e4# => romdata <= X"00"; -- ä
when 16#2e4# => romdata <= X"24"; -- ä
when 16#3e4# => romdata <= X"24"; -- ä
when 16#4e4# => romdata <= X"00"; -- ä
when 16#5e4# => romdata <= X"3c"; -- ä
when 16#6e4# => romdata <= X"02"; -- ä
when 16#7e4# => romdata <= X"3e"; -- ä
when 16#8e4# => romdata <= X"42"; -- ä
when 16#9e4# => romdata <= X"46"; -- ä
when 16#ae4# => romdata <= X"3a"; -- ä
when 16#be4# => romdata <= X"00"; -- ä
when 16#ce4# => romdata <= X"00"; -- ä
when 16#0e5# => romdata <= X"00"; -- å
when 16#1e5# => romdata <= X"18"; -- å
when 16#2e5# => romdata <= X"24"; -- å
when 16#3e5# => romdata <= X"18"; -- å
when 16#4e5# => romdata <= X"00"; -- å
when 16#5e5# => romdata <= X"3c"; -- å
when 16#6e5# => romdata <= X"02"; -- å
when 16#7e5# => romdata <= X"3e"; -- å
when 16#8e5# => romdata <= X"42"; -- å
when 16#9e5# => romdata <= X"46"; -- å
when 16#ae5# => romdata <= X"3a"; -- å
when 16#be5# => romdata <= X"00"; -- å
when 16#ce5# => romdata <= X"00"; -- å
when 16#0e6# => romdata <= X"00"; -- æ
when 16#1e6# => romdata <= X"00"; -- æ
when 16#2e6# => romdata <= X"00"; -- æ
when 16#3e6# => romdata <= X"00"; -- æ
when 16#4e6# => romdata <= X"00"; -- æ
when 16#5e6# => romdata <= X"6c"; -- æ
when 16#6e6# => romdata <= X"12"; -- æ
when 16#7e6# => romdata <= X"7c"; -- æ
when 16#8e6# => romdata <= X"90"; -- æ
when 16#9e6# => romdata <= X"92"; -- æ
when 16#ae6# => romdata <= X"6c"; -- æ
when 16#be6# => romdata <= X"00"; -- æ
when 16#ce6# => romdata <= X"00"; -- æ
when 16#0e7# => romdata <= X"00"; -- ç
when 16#1e7# => romdata <= X"00"; -- ç
when 16#2e7# => romdata <= X"00"; -- ç
when 16#3e7# => romdata <= X"00"; -- ç
when 16#4e7# => romdata <= X"00"; -- ç
when 16#5e7# => romdata <= X"3c"; -- ç
when 16#6e7# => romdata <= X"42"; -- ç
when 16#7e7# => romdata <= X"40"; -- ç
when 16#8e7# => romdata <= X"40"; -- ç
when 16#9e7# => romdata <= X"42"; -- ç
when 16#ae7# => romdata <= X"3c"; -- ç
when 16#be7# => romdata <= X"08"; -- ç
when 16#ce7# => romdata <= X"10"; -- ç
when 16#0e8# => romdata <= X"00"; -- è
when 16#1e8# => romdata <= X"00"; -- è
when 16#2e8# => romdata <= X"10"; -- è
when 16#3e8# => romdata <= X"08"; -- è
when 16#4e8# => romdata <= X"00"; -- è
when 16#5e8# => romdata <= X"3c"; -- è
when 16#6e8# => romdata <= X"42"; -- è
when 16#7e8# => romdata <= X"7e"; -- è
when 16#8e8# => romdata <= X"40"; -- è
when 16#9e8# => romdata <= X"42"; -- è
when 16#ae8# => romdata <= X"3c"; -- è
when 16#be8# => romdata <= X"00"; -- è
when 16#ce8# => romdata <= X"00"; -- è
when 16#0e9# => romdata <= X"00"; -- é
when 16#1e9# => romdata <= X"00"; -- é
when 16#2e9# => romdata <= X"08"; -- é
when 16#3e9# => romdata <= X"10"; -- é
when 16#4e9# => romdata <= X"00"; -- é
when 16#5e9# => romdata <= X"3c"; -- é
when 16#6e9# => romdata <= X"42"; -- é
when 16#7e9# => romdata <= X"7e"; -- é
when 16#8e9# => romdata <= X"40"; -- é
when 16#9e9# => romdata <= X"42"; -- é
when 16#ae9# => romdata <= X"3c"; -- é
when 16#be9# => romdata <= X"00"; -- é
when 16#ce9# => romdata <= X"00"; -- é
when 16#0ea# => romdata <= X"00"; -- ê
when 16#1ea# => romdata <= X"00"; -- ê
when 16#2ea# => romdata <= X"18"; -- ê
when 16#3ea# => romdata <= X"24"; -- ê
when 16#4ea# => romdata <= X"00"; -- ê
when 16#5ea# => romdata <= X"3c"; -- ê
when 16#6ea# => romdata <= X"42"; -- ê
when 16#7ea# => romdata <= X"7e"; -- ê
when 16#8ea# => romdata <= X"40"; -- ê
when 16#9ea# => romdata <= X"42"; -- ê
when 16#aea# => romdata <= X"3c"; -- ê
when 16#bea# => romdata <= X"00"; -- ê
when 16#cea# => romdata <= X"00"; -- ê
when 16#0eb# => romdata <= X"00"; -- ë
when 16#1eb# => romdata <= X"00"; -- ë
when 16#2eb# => romdata <= X"24"; -- ë
when 16#3eb# => romdata <= X"24"; -- ë
when 16#4eb# => romdata <= X"00"; -- ë
when 16#5eb# => romdata <= X"3c"; -- ë
when 16#6eb# => romdata <= X"42"; -- ë
when 16#7eb# => romdata <= X"7e"; -- ë
when 16#8eb# => romdata <= X"40"; -- ë
when 16#9eb# => romdata <= X"42"; -- ë
when 16#aeb# => romdata <= X"3c"; -- ë
when 16#beb# => romdata <= X"00"; -- ë
when 16#ceb# => romdata <= X"00"; -- ë
when 16#0ec# => romdata <= X"00"; -- ì
when 16#1ec# => romdata <= X"00"; -- ì
when 16#2ec# => romdata <= X"20"; -- ì
when 16#3ec# => romdata <= X"10"; -- ì
when 16#4ec# => romdata <= X"00"; -- ì
when 16#5ec# => romdata <= X"30"; -- ì
when 16#6ec# => romdata <= X"10"; -- ì
when 16#7ec# => romdata <= X"10"; -- ì
when 16#8ec# => romdata <= X"10"; -- ì
when 16#9ec# => romdata <= X"10"; -- ì
when 16#aec# => romdata <= X"7c"; -- ì
when 16#bec# => romdata <= X"00"; -- ì
when 16#cec# => romdata <= X"00"; -- ì
when 16#0ed# => romdata <= X"00"; -- í
when 16#1ed# => romdata <= X"00"; -- í
when 16#2ed# => romdata <= X"10"; -- í
when 16#3ed# => romdata <= X"20"; -- í
when 16#4ed# => romdata <= X"00"; -- í
when 16#5ed# => romdata <= X"30"; -- í
when 16#6ed# => romdata <= X"10"; -- í
when 16#7ed# => romdata <= X"10"; -- í
when 16#8ed# => romdata <= X"10"; -- í
when 16#9ed# => romdata <= X"10"; -- í
when 16#aed# => romdata <= X"7c"; -- í
when 16#bed# => romdata <= X"00"; -- í
when 16#ced# => romdata <= X"00"; -- í
when 16#0ee# => romdata <= X"00"; -- î
when 16#1ee# => romdata <= X"00"; -- î
when 16#2ee# => romdata <= X"30"; -- î
when 16#3ee# => romdata <= X"48"; -- î
when 16#4ee# => romdata <= X"00"; -- î
when 16#5ee# => romdata <= X"30"; -- î
when 16#6ee# => romdata <= X"10"; -- î
when 16#7ee# => romdata <= X"10"; -- î
when 16#8ee# => romdata <= X"10"; -- î
when 16#9ee# => romdata <= X"10"; -- î
when 16#aee# => romdata <= X"7c"; -- î
when 16#bee# => romdata <= X"00"; -- î
when 16#cee# => romdata <= X"00"; -- î
when 16#0ef# => romdata <= X"00"; -- ï
when 16#1ef# => romdata <= X"00"; -- ï
when 16#2ef# => romdata <= X"48"; -- ï
when 16#3ef# => romdata <= X"48"; -- ï
when 16#4ef# => romdata <= X"00"; -- ï
when 16#5ef# => romdata <= X"30"; -- ï
when 16#6ef# => romdata <= X"10"; -- ï
when 16#7ef# => romdata <= X"10"; -- ï
when 16#8ef# => romdata <= X"10"; -- ï
when 16#9ef# => romdata <= X"10"; -- ï
when 16#aef# => romdata <= X"7c"; -- ï
when 16#bef# => romdata <= X"00"; -- ï
when 16#cef# => romdata <= X"00"; -- ï
when 16#0f0# => romdata <= X"00"; -- ð
when 16#1f0# => romdata <= X"24"; -- ð
when 16#2f0# => romdata <= X"18"; -- ð
when 16#3f0# => romdata <= X"28"; -- ð
when 16#4f0# => romdata <= X"04"; -- ð
when 16#5f0# => romdata <= X"3c"; -- ð
when 16#6f0# => romdata <= X"42"; -- ð
when 16#7f0# => romdata <= X"42"; -- ð
when 16#8f0# => romdata <= X"42"; -- ð
when 16#9f0# => romdata <= X"42"; -- ð
when 16#af0# => romdata <= X"3c"; -- ð
when 16#bf0# => romdata <= X"00"; -- ð
when 16#cf0# => romdata <= X"00"; -- ð
when 16#0f1# => romdata <= X"00"; -- ñ
when 16#1f1# => romdata <= X"00"; -- ñ
when 16#2f1# => romdata <= X"32"; -- ñ
when 16#3f1# => romdata <= X"4c"; -- ñ
when 16#4f1# => romdata <= X"00"; -- ñ
when 16#5f1# => romdata <= X"5c"; -- ñ
when 16#6f1# => romdata <= X"62"; -- ñ
when 16#7f1# => romdata <= X"42"; -- ñ
when 16#8f1# => romdata <= X"42"; -- ñ
when 16#9f1# => romdata <= X"42"; -- ñ
when 16#af1# => romdata <= X"42"; -- ñ
when 16#bf1# => romdata <= X"00"; -- ñ
when 16#cf1# => romdata <= X"00"; -- ñ
when 16#0f2# => romdata <= X"00"; -- ò
when 16#1f2# => romdata <= X"00"; -- ò
when 16#2f2# => romdata <= X"20"; -- ò
when 16#3f2# => romdata <= X"10"; -- ò
when 16#4f2# => romdata <= X"00"; -- ò
when 16#5f2# => romdata <= X"3c"; -- ò
when 16#6f2# => romdata <= X"42"; -- ò
when 16#7f2# => romdata <= X"42"; -- ò
when 16#8f2# => romdata <= X"42"; -- ò
when 16#9f2# => romdata <= X"42"; -- ò
when 16#af2# => romdata <= X"3c"; -- ò
when 16#bf2# => romdata <= X"00"; -- ò
when 16#cf2# => romdata <= X"00"; -- ò
when 16#0f3# => romdata <= X"00"; -- ó
when 16#1f3# => romdata <= X"00"; -- ó
when 16#2f3# => romdata <= X"08"; -- ó
when 16#3f3# => romdata <= X"10"; -- ó
when 16#4f3# => romdata <= X"00"; -- ó
when 16#5f3# => romdata <= X"3c"; -- ó
when 16#6f3# => romdata <= X"42"; -- ó
when 16#7f3# => romdata <= X"42"; -- ó
when 16#8f3# => romdata <= X"42"; -- ó
when 16#9f3# => romdata <= X"42"; -- ó
when 16#af3# => romdata <= X"3c"; -- ó
when 16#bf3# => romdata <= X"00"; -- ó
when 16#cf3# => romdata <= X"00"; -- ó
when 16#0f4# => romdata <= X"00"; -- ô
when 16#1f4# => romdata <= X"00"; -- ô
when 16#2f4# => romdata <= X"18"; -- ô
when 16#3f4# => romdata <= X"24"; -- ô
when 16#4f4# => romdata <= X"00"; -- ô
when 16#5f4# => romdata <= X"3c"; -- ô
when 16#6f4# => romdata <= X"42"; -- ô
when 16#7f4# => romdata <= X"42"; -- ô
when 16#8f4# => romdata <= X"42"; -- ô
when 16#9f4# => romdata <= X"42"; -- ô
when 16#af4# => romdata <= X"3c"; -- ô
when 16#bf4# => romdata <= X"00"; -- ô
when 16#cf4# => romdata <= X"00"; -- ô
when 16#0f5# => romdata <= X"00"; -- õ
when 16#1f5# => romdata <= X"00"; -- õ
when 16#2f5# => romdata <= X"32"; -- õ
when 16#3f5# => romdata <= X"4c"; -- õ
when 16#4f5# => romdata <= X"00"; -- õ
when 16#5f5# => romdata <= X"3c"; -- õ
when 16#6f5# => romdata <= X"42"; -- õ
when 16#7f5# => romdata <= X"42"; -- õ
when 16#8f5# => romdata <= X"42"; -- õ
when 16#9f5# => romdata <= X"42"; -- õ
when 16#af5# => romdata <= X"3c"; -- õ
when 16#bf5# => romdata <= X"00"; -- õ
when 16#cf5# => romdata <= X"00"; -- õ
when 16#0f6# => romdata <= X"00"; -- ö
when 16#1f6# => romdata <= X"00"; -- ö
when 16#2f6# => romdata <= X"24"; -- ö
when 16#3f6# => romdata <= X"24"; -- ö
when 16#4f6# => romdata <= X"00"; -- ö
when 16#5f6# => romdata <= X"3c"; -- ö
when 16#6f6# => romdata <= X"42"; -- ö
when 16#7f6# => romdata <= X"42"; -- ö
when 16#8f6# => romdata <= X"42"; -- ö
when 16#9f6# => romdata <= X"42"; -- ö
when 16#af6# => romdata <= X"3c"; -- ö
when 16#bf6# => romdata <= X"00"; -- ö
when 16#cf6# => romdata <= X"00"; -- ö
when 16#0f7# => romdata <= X"00"; -- ÷
when 16#1f7# => romdata <= X"00"; -- ÷
when 16#2f7# => romdata <= X"00"; -- ÷
when 16#3f7# => romdata <= X"10"; -- ÷
when 16#4f7# => romdata <= X"10"; -- ÷
when 16#5f7# => romdata <= X"00"; -- ÷
when 16#6f7# => romdata <= X"7c"; -- ÷
when 16#7f7# => romdata <= X"00"; -- ÷
when 16#8f7# => romdata <= X"10"; -- ÷
when 16#9f7# => romdata <= X"10"; -- ÷
when 16#af7# => romdata <= X"00"; -- ÷
when 16#bf7# => romdata <= X"00"; -- ÷
when 16#cf7# => romdata <= X"00"; -- ÷
when 16#0f8# => romdata <= X"00"; -- ø
when 16#1f8# => romdata <= X"00"; -- ø
when 16#2f8# => romdata <= X"00"; -- ø
when 16#3f8# => romdata <= X"00"; -- ø
when 16#4f8# => romdata <= X"02"; -- ø
when 16#5f8# => romdata <= X"3c"; -- ø
when 16#6f8# => romdata <= X"46"; -- ø
when 16#7f8# => romdata <= X"4a"; -- ø
when 16#8f8# => romdata <= X"52"; -- ø
when 16#9f8# => romdata <= X"62"; -- ø
when 16#af8# => romdata <= X"3c"; -- ø
when 16#bf8# => romdata <= X"40"; -- ø
when 16#cf8# => romdata <= X"00"; -- ø
when 16#0f9# => romdata <= X"00"; -- ù
when 16#1f9# => romdata <= X"00"; -- ù
when 16#2f9# => romdata <= X"20"; -- ù
when 16#3f9# => romdata <= X"10"; -- ù
when 16#4f9# => romdata <= X"00"; -- ù
when 16#5f9# => romdata <= X"44"; -- ù
when 16#6f9# => romdata <= X"44"; -- ù
when 16#7f9# => romdata <= X"44"; -- ù
when 16#8f9# => romdata <= X"44"; -- ù
when 16#9f9# => romdata <= X"44"; -- ù
when 16#af9# => romdata <= X"3a"; -- ù
when 16#bf9# => romdata <= X"00"; -- ù
when 16#cf9# => romdata <= X"00"; -- ù
when 16#0fa# => romdata <= X"00"; -- ú
when 16#1fa# => romdata <= X"00"; -- ú
when 16#2fa# => romdata <= X"08"; -- ú
when 16#3fa# => romdata <= X"10"; -- ú
when 16#4fa# => romdata <= X"00"; -- ú
when 16#5fa# => romdata <= X"44"; -- ú
when 16#6fa# => romdata <= X"44"; -- ú
when 16#7fa# => romdata <= X"44"; -- ú
when 16#8fa# => romdata <= X"44"; -- ú
when 16#9fa# => romdata <= X"44"; -- ú
when 16#afa# => romdata <= X"3a"; -- ú
when 16#bfa# => romdata <= X"00"; -- ú
when 16#cfa# => romdata <= X"00"; -- ú
when 16#0fb# => romdata <= X"00"; -- û
when 16#1fb# => romdata <= X"00"; -- û
when 16#2fb# => romdata <= X"18"; -- û
when 16#3fb# => romdata <= X"24"; -- û
when 16#4fb# => romdata <= X"00"; -- û
when 16#5fb# => romdata <= X"44"; -- û
when 16#6fb# => romdata <= X"44"; -- û
when 16#7fb# => romdata <= X"44"; -- û
when 16#8fb# => romdata <= X"44"; -- û
when 16#9fb# => romdata <= X"44"; -- û
when 16#afb# => romdata <= X"3a"; -- û
when 16#bfb# => romdata <= X"00"; -- û
when 16#cfb# => romdata <= X"00"; -- û
when 16#0fc# => romdata <= X"00"; -- ü
when 16#1fc# => romdata <= X"00"; -- ü
when 16#2fc# => romdata <= X"28"; -- ü
when 16#3fc# => romdata <= X"28"; -- ü
when 16#4fc# => romdata <= X"00"; -- ü
when 16#5fc# => romdata <= X"44"; -- ü
when 16#6fc# => romdata <= X"44"; -- ü
when 16#7fc# => romdata <= X"44"; -- ü
when 16#8fc# => romdata <= X"44"; -- ü
when 16#9fc# => romdata <= X"44"; -- ü
when 16#afc# => romdata <= X"3a"; -- ü
when 16#bfc# => romdata <= X"00"; -- ü
when 16#cfc# => romdata <= X"00"; -- ü
when 16#0fd# => romdata <= X"00"; -- ý
when 16#1fd# => romdata <= X"00"; -- ý
when 16#2fd# => romdata <= X"08"; -- ý
when 16#3fd# => romdata <= X"10"; -- ý
when 16#4fd# => romdata <= X"00"; -- ý
when 16#5fd# => romdata <= X"42"; -- ý
when 16#6fd# => romdata <= X"42"; -- ý
when 16#7fd# => romdata <= X"42"; -- ý
when 16#8fd# => romdata <= X"46"; -- ý
when 16#9fd# => romdata <= X"3a"; -- ý
when 16#afd# => romdata <= X"02"; -- ý
when 16#bfd# => romdata <= X"42"; -- ý
when 16#cfd# => romdata <= X"3c"; -- ý
when 16#0fe# => romdata <= X"00"; -- þ
when 16#1fe# => romdata <= X"00"; -- þ
when 16#2fe# => romdata <= X"00"; -- þ
when 16#3fe# => romdata <= X"40"; -- þ
when 16#4fe# => romdata <= X"40"; -- þ
when 16#5fe# => romdata <= X"5c"; -- þ
when 16#6fe# => romdata <= X"62"; -- þ
when 16#7fe# => romdata <= X"42"; -- þ
when 16#8fe# => romdata <= X"42"; -- þ
when 16#9fe# => romdata <= X"62"; -- þ
when 16#afe# => romdata <= X"5c"; -- þ
when 16#bfe# => romdata <= X"40"; -- þ
when 16#cfe# => romdata <= X"40"; -- þ
when 16#0ff# => romdata <= X"00"; -- ÿ
when 16#1ff# => romdata <= X"00"; -- ÿ
when 16#2ff# => romdata <= X"24"; -- ÿ
when 16#3ff# => romdata <= X"24"; -- ÿ
when 16#4ff# => romdata <= X"00"; -- ÿ
when 16#5ff# => romdata <= X"42"; -- ÿ
when 16#6ff# => romdata <= X"42"; -- ÿ
when 16#7ff# => romdata <= X"42"; -- ÿ
when 16#8ff# => romdata <= X"46"; -- ÿ
when 16#9ff# => romdata <= X"3a"; -- ÿ
when 16#aff# => romdata <= X"02"; -- ÿ
when 16#bff# => romdata <= X"42"; -- ÿ
when 16#cff# => romdata <= X"3c"; -- ÿ
when others => romdata <= (others => '0');
end case;
end process;
end architecture;
| mit | 25873219d673ea10c0aa320b85a5fad8 | 0.421967 | 2.935679 | false | false | false | false |
michaelfivez/ascon_hardware_implementation | ascon128128_serialized/Kernel/Sbox.vhd | 1 | 4,044 | -------------------------------------------------------------------------------
--! @project Serialized hardware implementation of Asconv128128
--! @author Michael Fivez
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is an hardware implementation made for my graduation thesis
--! at the KULeuven, in the COSIC department (year 2015-2016)
--! The thesis is titled 'Energy efficient hardware implementations of CAESAR submissions',
--! and can be found on the COSIC website (www.esat.kuleuven.be/cosic/publications)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Sbox is
port(
X0In : in std_logic_vector(15 downto 0);
X1In : in std_logic_vector(15 downto 0);
X2In : in std_logic_vector(15 downto 0);
X3In : in std_logic_vector(15 downto 0);
X4In : in std_logic_vector(15 downto 0);
RoundNr : in std_logic_vector(3 downto 0);
X0Out : out std_logic_vector(15 downto 0);
X1Out : out std_logic_vector(15 downto 0);
X2Out : out std_logic_vector(15 downto 0);
X3Out : out std_logic_vector(15 downto 0);
X4Out : out std_logic_vector(15 downto 0);
Sel : in std_logic_vector(1 downto 0));
end entity Sbox;
architecture structural of Sbox is
begin
Sbox: process(X0In,X1In,X2In,X3In,X4In,RoundNr,Sel) is
-- Procedure for 5-bit Sbox
procedure doSboxPart (
variable SboxPartIn : in std_logic_vector(4 downto 0);
variable SboxPartOut : out std_logic_vector(4 downto 0)) is
-- Temp variable
variable SboxPartTemp : std_logic_vector(17 downto 0);
begin
-- Sbox Interconnections
SboxPartTemp(0) := SboxPartIn(0) xor SboxPartIn(4);
SboxPartTemp(1) := SboxPartIn(2) xor SboxPartIn(1);
SboxPartTemp(2) := SboxPartIn(4) xor SboxPartIn(3);
SboxPartTemp(3) := not SboxPartTemp(0);
SboxPartTemp(4) := not SboxPartIn(1);
SboxPartTemp(5) := not SboxPartTemp(1);
SboxPartTemp(6) := not SboxPartIn(3);
SboxPartTemp(7) := not SboxPartTemp(2);
SboxPartTemp(8) := SboxPartIn(1) and SboxPartTemp(3);
SboxPartTemp(9) := SboxPartTemp(1) and SboxPartTemp(4);
SboxPartTemp(10) := SboxPartIn(3) and SboxPartTemp(5);
SboxPartTemp(11) := SboxPartTemp(2) and SboxPartTemp(6);
SboxPartTemp(12) := SboxPartTemp(0) and SboxPartTemp(7);
SboxPartTemp(13) := SboxPartTemp(0) xor SboxPartTemp(9);
SboxPartTemp(14) := SboxPartIn(1) xor SboxPartTemp(10);
SboxPartTemp(15) := SboxPartTemp(1) xor SboxPartTemp(11);
SboxPartTemp(16) := SboxPartIn(3) xor SboxPartTemp(12);
SboxPartTemp(17) := SboxPartTemp(2) xor SboxPartTemp(8);
SboxPartOut(0) := SboxPartTemp(13) xor SboxPartTemp(17);
SboxPartOut(1) := SboxPartTemp(13) xor SboxPartTemp(14);
SboxPartOut(2) := not SboxPartTemp(15);
SboxPartOut(3) := SboxPartTemp(15) xor SboxPartTemp(16);
SboxPartOut(4) := SboxPartTemp(17);
end procedure doSboxPart;
variable X2TempIn : std_logic_vector(15 downto 0);
variable TempIn,TempOut : std_logic_vector(4 downto 0);
begin
-- Xor with round constants
if Sel = "11" then
X2TempIn(3 downto 0) := X2In(3 downto 0) xor RoundNr;
X2TempIn(7 downto 4) := X2In(7 downto 4) xnor RoundNr;
X2TempIn(15 downto 8) := X2In(15 downto 8);
else
X2TempIn := X2In;
end if;
-- Apply 5-bit Sbox 64 times
for i in X0In'range loop
TempIn(0) := X0In(i);
TempIn(1) := X1In(i);
TempIn(2) := X2TempIn(i);
TempIn(3) := X3In(i);
TempIn(4) := X4In(i);
doSboxPart(TempIn,TempOut);
X0Out(i) <= TempOut(0);
X1Out(i) <= TempOut(1);
X2Out(i) <= TempOut(2);
X3Out(i) <= TempOut(3);
X4Out(i) <= TempOut(4);
end loop;
end process Sbox;
end architecture structural;
| gpl-3.0 | 9b59156e8a2720bea7d765f3f135ed8e | 0.638229 | 2.913545 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | VhdlParser/test/pairTest.vhd | 1 | 4,679 | --EXPECTED RESULTS
--RESAB&0&0
--RESCD&0&0
--RESEF&0&0
--RESGH&0&0
--RESABCD&0&0
--RESEFGH&0&0
--RESULT&0&0
--RESAB&OPERANDA&1
--RESAB&OPERANDB&1
--RESCD&OPERANDC&1
--RESCD&OPERANDD&1
--RESEF&OPERANDE&1
--RESEF&OPERANDF&1
--RESGH&OPERANDG&1
--RESGH&OPERANDH&1
--RESABCD&OPERANDA&2
--RESABCD&OPERANDB&2
--RESABCD&OPERANDC&2
--RESABCD&OPERANDD&2
--RESEFGH&OPERANDE&2
--RESEFGH&OPERANDF&2
--RESEFGH&OPERANDG&2
--RESEFGH&OPERANDH&2
--RESULT&OPERANDA&3
--RESULT&OPERANDB&3
--RESULT&OPERANDC&3
--RESULT&OPERANDD&3
--RESULT&OPERANDE&3
--RESULT&OPERANDF&3
--RESULT&OPERANDG&3
--RESULT&OPERANDH&3
--RESABCD&RESAB&1
--RESABCD&RESCD&1
--RESEFGH&RESEF&1
--RESEFGH&RESGH&1
--RESULT&RESAB&2
--RESULT&RESCD&2
--RESULT&RESEF&2
--RESULT&RESGH&2
--RESULT&RESABCD&1
--RESULT&RESEFGH&1
--OPSABCOMBINED&???&0 -- how do we deal with this
--OPSABCOMBINED (15 DOWNTO 12)&OPERANDA&0
--OPSABCOMBINED (11 DOWNTO 8)&OPERANDB&0
--TRICKYSPLIT&OPSABCOMBINED&1
--TRICKYSPLIT (5 DOWNTO 2)&TRICKYSPLIT (9 DOWNTO 6)&1
--TRICKYSPLIT (5 DOWNTO 2)&OPSABCOMBINED (15 DOWNTO 12)&2
--TRICKYSPLIT (5 DOWNTO 2)&OPERANDA&2
--TRICKYSPLIT (5 DOWNTO 2)&OPSABCOMBINED (11 DOWNTO 8)&1
--TRICKYSPLIT (5 DOWNTO 2)&OPERANDB&1
--TRICKYSPLIT (9 DOWNTO 6)&OPSABCOMBINED (15 DOWNTO 12)&1
--TRICKYSPLIT2 (19 DOWNTO 12)&???&0 -- how do we deal with these
--TRICKYSPLIT2 (19 DOWNTO 16)&OPERANDA&0
--TRICKYSPLIT2 (15 DOWNTO 12)&OPERANDB&0
--TRICKYSPLIT2 (11 DOWNTO 4)&TRICKYSPLIT2 (19 DOWNTO 12)&1
--TRICKYSPLIT2 (11 DOWNTO 4)&???&1 -- how do we deal with these
--TRICKYSPLIT2 (7 DOWNTO 4)&TRICKYSPLIT2 (15 DOWNTO 12)&1
--TRICKYSPLIT2 (7 DOWNTO 4)&OPERANDB (3 DOWNTO 0)&1
--TRICKYSPLIT2 (7 DOWNTO 4)&TRICKYSPLIT2 (11 DOWNTO 8)&1
--TRICKYSPLIT2 (11 DOWNTO 8)&TRICKYSPLIT2 (19 DOWNTO 16)&1
--TRICKYSPLIT2 (11 DOWNTO 8)&OPERANDA&1
--TRICKYSPLIT2 (7 DOWNTO 4)&TRICKYSPLIT2 (19 DOWNTO 16)&2
--TRICKYSPLIT2 (7 DOWNTO 4)&OPERANDA&2
--TRICKYREC.A&OPERANDA&1
--TRICKYREC.B&OPERANDB&1
--TRICKYREC&???&0 -- how do we deal with these
--TRICKYREC.C&???&1 -- how do we deal with these
--TRICKYREC.C (7 DOWNTO 4)&TRICKYREC.A&1 -- how do we deal with these
--TRICKYREC.C (3 downto 0)&TRICKYREC.B&1 -- how do we deal with these
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pairTest is
port(
clk : in std_logic;
rst : in std_logic;
operandA : in unsigned(3 downto 0);
operandB : in unsigned(3 downto 0);
operandC : in unsigned(3 downto 0);
operandD : in unsigned(3 downto 0);
operandE : in unsigned(3 downto 0);
operandF : in unsigned(3 downto 0);
operandG : in unsigned(3 downto 0);
operandH : in unsigned(3 downto 0);
result : out unsigned(3 downto 0)
);
end entity pairTest;
architecture rtl of pairTest is
type My_Rec is record
a : unsigned(3 downto 0);
b : unsigned(3 downto 0);
c : unsigned(7 downto 0);
end record;
signal resAB : unsigned(3 downto 0);
signal resCD : unsigned(3 downto 0);
signal resEF : unsigned(3 downto 0);
signal resGH : unsigned(3 downto 0);
signal resABCD : unsigned(3 downto 0);
signal resEFGH : unsigned(3 downto 0);
signal opsABCombined : unsigned(15 downto 8);
signal trickySplit : unsigned(9 downto 2);
signal trickySplit2 : unsigned(19 downto 4);
signal trickyRec : My_rec;
begin
opsABCombined <= operandA & operandB;
trickySplit2(19 downto 12) <= operandA & operandB;
DoOps : process(clk)
begin
if(clk'event and clk = '1')then
if(rst = '1')then
resAB <= "0000";
resCD <= "0000";
resEF <= "0000";
resGH <= "0000";
resABCD <= "0000";
resEFGH <= "0000";
result <= "0000";
trickySplit <= opsABCombined;
trickySplit2(11 downto 4) <= trickySplit2(19 downto 12);
trickyRec <= (operandA, operandB, (operandC & operandD));
else
resAB <= operandA + operandB;
resCD <= operandC + operandD;
resEF <= operandE + operandF;
resGH <= operandG + operandH;
resABCD <= resAB + resCD;
resEFGH <= resEF + resGH;
result <= resABCD + resEFGH;
-- ts(7 4) should be added to the signal list since it is a driver, and it should be marked as a register due to it's less constrained version being marked as such
if(operandA(3) and operandB(3) and operandC(3) and operandD(3) and operandE(3) and operandF(3) and operandG(3) and operandH(3))then
trickySplit(5 downto 2) <= trickySplit(9 downto 6);
trickySplit2(7 downto 4) <= trickySplit2(11 downto 8);
trickyRec.c <= trickyRec.a & trickyRec.b;
end if;
end if;
end if;
end process;
end architecture rtl; | mit | b688de5d95d2915684d3d9119268c4b3 | 0.666168 | 2.673714 | false | false | false | false |
michaelfivez/ascon_hardware_implementation | ascon12864_unrolled2/Kernel/Sbox.vhd | 1 | 3,932 | -------------------------------------------------------------------------------
--! @project Unrolled (2) hardware implementation of Asconv1286
--! @author Michael Fivez
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is an hardware implementation made for my graduation thesis
--! at the KULeuven, in the COSIC department (year 2015-2016)
--! The thesis is titled 'Energy efficient hardware implementations of CAESAR submissions',
--! and can be found on the COSIC website (www.esat.kuleuven.be/cosic/publications)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Sbox is
port(
X0In : in std_logic_vector(63 downto 0);
X1In : in std_logic_vector(63 downto 0);
X2In : in std_logic_vector(63 downto 0);
X3In : in std_logic_vector(63 downto 0);
X4In : in std_logic_vector(63 downto 0);
RoundNr : in std_logic_vector(3 downto 0);
X0Out : out std_logic_vector(63 downto 0);
X1Out : out std_logic_vector(63 downto 0);
X2Out : out std_logic_vector(63 downto 0);
X3Out : out std_logic_vector(63 downto 0);
X4Out : out std_logic_vector(63 downto 0));
end entity Sbox;
architecture structural of Sbox is
begin
Sbox: process(X0In,X1In,X2In,X3In,X4In,RoundNr) is
-- Procedure for 5-bit Sbox
procedure doSboxPart (
variable SboxPartIn : in std_logic_vector(4 downto 0);
variable SboxPartOut : out std_logic_vector(4 downto 0)) is
-- Temp variable
variable SboxPartTemp : std_logic_vector(17 downto 0);
begin
-- Sbox Interconnections
SboxPartTemp(0) := SboxPartIn(0) xor SboxPartIn(4);
SboxPartTemp(1) := SboxPartIn(2) xor SboxPartIn(1);
SboxPartTemp(2) := SboxPartIn(4) xor SboxPartIn(3);
SboxPartTemp(3) := not SboxPartTemp(0);
SboxPartTemp(4) := not SboxPartIn(1);
SboxPartTemp(5) := not SboxPartTemp(1);
SboxPartTemp(6) := not SboxPartIn(3);
SboxPartTemp(7) := not SboxPartTemp(2);
SboxPartTemp(8) := SboxPartIn(1) and SboxPartTemp(3);
SboxPartTemp(9) := SboxPartTemp(1) and SboxPartTemp(4);
SboxPartTemp(10) := SboxPartIn(3) and SboxPartTemp(5);
SboxPartTemp(11) := SboxPartTemp(2) and SboxPartTemp(6);
SboxPartTemp(12) := SboxPartTemp(0) and SboxPartTemp(7);
SboxPartTemp(13) := SboxPartTemp(0) xor SboxPartTemp(9);
SboxPartTemp(14) := SboxPartIn(1) xor SboxPartTemp(10);
SboxPartTemp(15) := SboxPartTemp(1) xor SboxPartTemp(11);
SboxPartTemp(16) := SboxPartIn(3) xor SboxPartTemp(12);
SboxPartTemp(17) := SboxPartTemp(2) xor SboxPartTemp(8);
SboxPartOut(0) := SboxPartTemp(13) xor SboxPartTemp(17);
SboxPartOut(1) := SboxPartTemp(13) xor SboxPartTemp(14);
SboxPartOut(2) := not SboxPartTemp(15);
SboxPartOut(3) := SboxPartTemp(15) xor SboxPartTemp(16);
SboxPartOut(4) := SboxPartTemp(17);
end procedure doSboxPart;
variable X2TempIn : std_logic_vector(63 downto 0);
variable TempIn,TempOut : std_logic_vector(4 downto 0);
begin
-- Xor with round constants
X2TempIn(3 downto 0) := X2In(3 downto 0) xor RoundNr;
X2TempIn(7 downto 4) := X2In(7 downto 4) xnor RoundNr;
X2TempIn(63 downto 8) := X2In(63 downto 8);
-- Apply 5-bit Sbox 64 times
for i in X0In'range loop
TempIn(0) := X0In(i);
TempIn(1) := X1In(i);
TempIn(2) := X2TempIn(i);
TempIn(3) := X3In(i);
TempIn(4) := X4In(i);
doSboxPart(TempIn,TempOut);
X0Out(i) <= TempOut(0);
X1Out(i) <= TempOut(1);
X2Out(i) <= TempOut(2);
X3Out(i) <= TempOut(3);
X4Out(i) <= TempOut(4);
end loop;
end process Sbox;
end architecture structural;
| gpl-3.0 | e83bac047e7bf95caaae8cded75f8508 | 0.639878 | 2.921248 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/techmap/maps/clkpad_ds.vhd | 2 | 2,248 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: clkpad
-- File: clkpad_ds.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: DS clock pad with technology wrapper
------------------------------------------------------------------------------
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allpads.all;
entity clkpad_ds is
generic (tech : integer := 0; level : integer := lvds; voltage : integer := x33v);
port (padp, padn : in std_ulogic; o : out std_ulogic);
end;
architecture rtl of clkpad_ds is
signal gnd : std_ulogic;
begin
gnd <= '0';
gen0 : if has_ds_pads(tech) = 0 generate
o <= to_X01(padp) after 1 ns;
end generate;
xcv : if (tech = virtex) or (tech = virtex2) or (tech = spartan3) generate
u0 : virtex_clkpad_ds generic map (level, voltage) port map (padp, padn, o);
end generate;
xc4v : if (tech = virtex4) or (tech = spartan3e) or (tech = virtex5) generate
u0 : virtex4_clkpad_ds generic map (level, voltage) port map (padp, padn, o);
end generate;
axc : if (tech = axcel) generate
u0 : axcel_inpad_ds generic map (level, voltage) port map (padp, padn, o);
end generate;
rht : if (tech = rhlib18t) generate
u0 : rh_lib18t_inpad_ds port map (padp, padn, o, gnd);
end generate;
end;
| mit | 42ac65c8e1fe872f208628915e9c6394 | 0.625445 | 3.823129 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/spw/comp/spwcomp.vhd | 2 | 16,350 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package spwcomp is
component grspwc2 is
generic(
nsync : integer range 1 to 2 := 1;
rmap : integer range 0 to 1 := 0;
rmapcrc : integer range 0 to 1 := 0;
fifosize1 : integer range 4 to 32 := 32;
fifosize2 : integer range 16 to 64 := 64;
rxunaligned : integer range 0 to 1 := 0;
rmapbufs : integer range 2 to 8 := 4;
scantest : integer range 0 to 1 := 0;
ports : integer range 1 to 2 := 1;
dmachan : integer range 1 to 4 := 1;
tech : integer
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
txclk : in std_ulogic;
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--spw in
di : in std_logic_vector(1 downto 0);
si : in std_logic_vector(1 downto 0);
--spw out
do : out std_logic_vector(1 downto 0);
so : out std_logic_vector(1 downto 0);
--time iface
tickin : in std_ulogic;
tickout : out std_ulogic;
--irq
irq : out std_logic;
--misc
clkdiv10 : in std_logic_vector(7 downto 0);
dcrstval : in std_logic_vector(9 downto 0);
timerrstval : in std_logic_vector(11 downto 0);
--rmapen
rmapen : in std_ulogic;
--clk bufs
rxclki : in std_logic_vector(1 downto 0);
nrxclki : in std_logic_vector(1 downto 0);
rxclko : out std_logic_vector(1 downto 0);
--rx ahb fifo
rxrenable : out std_ulogic;
rxraddress : out std_logic_vector(4 downto 0);
rxwrite : out std_ulogic;
rxwdata : out std_logic_vector(31 downto 0);
rxwaddress : out std_logic_vector(4 downto 0);
rxrdata : in std_logic_vector(31 downto 0);
--tx ahb fifo
txrenable : out std_ulogic;
txraddress : out std_logic_vector(4 downto 0);
txwrite : out std_ulogic;
txwdata : out std_logic_vector(31 downto 0);
txwaddress : out std_logic_vector(4 downto 0);
txrdata : in std_logic_vector(31 downto 0);
--nchar fifo
ncrenable : out std_ulogic;
ncraddress : out std_logic_vector(5 downto 0);
ncwrite : out std_ulogic;
ncwdata : out std_logic_vector(8 downto 0);
ncwaddress : out std_logic_vector(5 downto 0);
ncrdata : in std_logic_vector(8 downto 0);
--rmap buf
rmrenable : out std_ulogic;
rmraddress : out std_logic_vector(7 downto 0);
rmwrite : out std_ulogic;
rmwdata : out std_logic_vector(7 downto 0);
rmwaddress : out std_logic_vector(7 downto 0);
rmrdata : in std_logic_vector(7 downto 0);
linkdis : out std_ulogic;
testclk : in std_ulogic := '0';
testrst : in std_ulogic := '0';
testen : in std_ulogic := '0'
);
end component;
component grspwc is
generic(
sysfreq : integer := 40000;
usegen : integer range 0 to 1 := 1;
nsync : integer range 1 to 2 := 1;
rmap : integer range 0 to 1 := 0;
rmapcrc : integer range 0 to 1 := 0;
fifosize1 : integer range 4 to 32 := 32;
fifosize2 : integer range 16 to 64 := 64;
rxunaligned : integer range 0 to 1 := 0;
rmapbufs : integer range 2 to 8 := 4;
scantest : integer range 0 to 1 := 0;
ports : integer range 1 to 2 := 1;
tech : integer
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
txclk : in std_ulogic;
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--spw in
di : in std_logic_vector(1 downto 0);
si : in std_logic_vector(1 downto 0);
--spw out
do : out std_logic_vector(1 downto 0);
so : out std_logic_vector(1 downto 0);
--time iface
tickin : in std_ulogic;
tickout : out std_ulogic;
--irq
irq : out std_logic;
--misc
clkdiv10 : in std_logic_vector(7 downto 0);
dcrstval : in std_logic_vector(9 downto 0);
timerrstval : in std_logic_vector(11 downto 0);
--rmapen
rmapen : in std_ulogic;
--clk bufs
rxclki : in std_logic_vector(1 downto 0);
nrxclki : in std_logic_vector(1 downto 0);
rxclko : out std_logic_vector(1 downto 0);
--rx ahb fifo
rxrenable : out std_ulogic;
rxraddress : out std_logic_vector(4 downto 0);
rxwrite : out std_ulogic;
rxwdata : out std_logic_vector(31 downto 0);
rxwaddress : out std_logic_vector(4 downto 0);
rxrdata : in std_logic_vector(31 downto 0);
--tx ahb fifo
txrenable : out std_ulogic;
txraddress : out std_logic_vector(4 downto 0);
txwrite : out std_ulogic;
txwdata : out std_logic_vector(31 downto 0);
txwaddress : out std_logic_vector(4 downto 0);
txrdata : in std_logic_vector(31 downto 0);
--nchar fifo
ncrenable : out std_ulogic;
ncraddress : out std_logic_vector(5 downto 0);
ncwrite : out std_ulogic;
ncwdata : out std_logic_vector(8 downto 0);
ncwaddress : out std_logic_vector(5 downto 0);
ncrdata : in std_logic_vector(8 downto 0);
--rmap buf
rmrenable : out std_ulogic;
rmraddress : out std_logic_vector(7 downto 0);
rmwrite : out std_ulogic;
rmwdata : out std_logic_vector(7 downto 0);
rmwaddress : out std_logic_vector(7 downto 0);
rmrdata : in std_logic_vector(7 downto 0);
linkdis : out std_ulogic;
testclk : in std_ulogic := '0';
testrst : in std_ulogic := '0';
testen : in std_ulogic := '0'
);
end component;
component grspwc_axcelerator is
port(
rst : in std_ulogic;
clk : in std_ulogic;
txclk : in std_ulogic;
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--spw in
di : in std_logic_vector(1 downto 0);
si : in std_logic_vector(1 downto 0);
--spw out
do : out std_logic_vector(1 downto 0);
so : out std_logic_vector(1 downto 0);
--time iface
tickin : in std_ulogic;
tickout : out std_ulogic;
--irq
irq : out std_logic;
--misc
clkdiv10 : in std_logic_vector(7 downto 0);
dcrstval : in std_logic_vector(9 downto 0);
timerrstval : in std_logic_vector(11 downto 0);
--rmapen
rmapen : in std_ulogic;
--clk bufs
rxclki : in std_logic_vector(1 downto 0);
nrxclki : in std_logic_vector(1 downto 0);
rxclko : out std_logic_vector(1 downto 0);
--rx ahb fifo
rxrenable : out std_ulogic;
rxraddress : out std_logic_vector(4 downto 0);
rxwrite : out std_ulogic;
rxwdata : out std_logic_vector(31 downto 0);
rxwaddress : out std_logic_vector(4 downto 0);
rxrdata : in std_logic_vector(31 downto 0);
--tx ahb fifo
txrenable : out std_ulogic;
txraddress : out std_logic_vector(4 downto 0);
txwrite : out std_ulogic;
txwdata : out std_logic_vector(31 downto 0);
txwaddress : out std_logic_vector(4 downto 0);
txrdata : in std_logic_vector(31 downto 0);
--nchar fifo
ncrenable : out std_ulogic;
ncraddress : out std_logic_vector(5 downto 0);
ncwrite : out std_ulogic;
ncwdata : out std_logic_vector(8 downto 0);
ncwaddress : out std_logic_vector(5 downto 0);
ncrdata : in std_logic_vector(8 downto 0);
--rmap buf
rmrenable : out std_ulogic;
rmraddress : out std_logic_vector(7 downto 0);
rmwrite : out std_ulogic;
rmwdata : out std_logic_vector(7 downto 0);
rmwaddress : out std_logic_vector(7 downto 0);
rmrdata : in std_logic_vector(7 downto 0);
linkdis : out std_ulogic;
testclk : in std_ulogic := '0';
testrst : in std_ulogic := '0';
testen : in std_ulogic := '0'
);
end component;
component grspwc_unisim is
port(
rst : in std_ulogic;
clk : in std_ulogic;
txclk : in std_ulogic;
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--spw in
di : in std_logic_vector(1 downto 0);
si : in std_logic_vector(1 downto 0);
--spw out
do : out std_logic_vector(1 downto 0);
so : out std_logic_vector(1 downto 0);
--time iface
tickin : in std_ulogic;
tickout : out std_ulogic;
--irq
irq : out std_logic;
--misc
clkdiv10 : in std_logic_vector(7 downto 0);
dcrstval : in std_logic_vector(9 downto 0);
timerrstval : in std_logic_vector(11 downto 0);
--rmapen
rmapen : in std_ulogic;
--clk bufs
rxclki : in std_logic_vector(1 downto 0);
nrxclki : in std_logic_vector(1 downto 0);
rxclko : out std_logic_vector(1 downto 0);
--rx ahb fifo
rxrenable : out std_ulogic;
rxraddress : out std_logic_vector(4 downto 0);
rxwrite : out std_ulogic;
rxwdata : out std_logic_vector(31 downto 0);
rxwaddress : out std_logic_vector(4 downto 0);
rxrdata : in std_logic_vector(31 downto 0);
--tx ahb fifo
txrenable : out std_ulogic;
txraddress : out std_logic_vector(4 downto 0);
txwrite : out std_ulogic;
txwdata : out std_logic_vector(31 downto 0);
txwaddress : out std_logic_vector(4 downto 0);
txrdata : in std_logic_vector(31 downto 0);
--nchar fifo
ncrenable : out std_ulogic;
ncraddress : out std_logic_vector(5 downto 0);
ncwrite : out std_ulogic;
ncwdata : out std_logic_vector(8 downto 0);
ncwaddress : out std_logic_vector(5 downto 0);
ncrdata : in std_logic_vector(8 downto 0);
--rmap buf
rmrenable : out std_ulogic;
rmraddress : out std_logic_vector(7 downto 0);
rmwrite : out std_ulogic;
rmwdata : out std_logic_vector(7 downto 0);
rmwaddress : out std_logic_vector(7 downto 0);
rmrdata : in std_logic_vector(7 downto 0);
linkdis : out std_ulogic;
testclk : in std_ulogic := '0';
testrst : in std_ulogic := '0';
testen : in std_ulogic := '0'
);
end component;
end package;
| mit | 36e02761369fec6df9ebcb7e0768f758 | 0.514985 | 3.770756 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/misc/svgactrl.vhd | 2 | 21,077 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: Vga Controller
-- File: vga_controller.vhd
-- Author: Hans Soderlund
-- Description: Vga Controller main file
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.misc.all;
entity svgactrl is
generic(
length : integer := 384; -- Fifo-length
part : integer := 128; -- Fifo-part lenght
memtech : integer := DEFMEMTECH;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
hindex : integer := 0;
hirq : integer := 0;
clk0 : integer := 40000;
clk1 : integer := 20000;
clk2 : integer := 15385;
clk3 : integer := 0;
burstlen : integer range 2 to 8 := 8
);
port (
rst : in std_logic;
clk : in std_logic;
vgaclk : in std_logic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
vgao : out apbvga_out_type;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
clk_sel : out std_logic_vector(1 downto 0)
);
end ;
architecture rtl of svgactrl is
constant REVISION : amba_version_type := 0;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_SVGACTRL, 0, REVISION, 0),
1 => apb_iobar(paddr, pmask));
type RegisterType is array (1 to 5) of std_logic_vector(31 downto 0);
type state_type is (running, not_running, reset);
type read_type is record
read_pointer : integer range 0 to length ;
read_pointer_out : integer range 0 to length ;
sync : std_logic_vector(2 downto 0);
data_out : std_logic_vector(23 downto 0);
lock : std_logic;
index : std_logic_vector(1 downto 0);
mem_index : integer;
read_pointer_clut : std_logic_vector(7 downto 0);
hcounter : std_logic_vector(15 downto 0);
vcounter : std_logic_vector(15 downto 0);
fifo_ren : std_logic;
fifo_en : std_logic;
hsync : std_logic ;
vsync : std_logic ;
csync : std_logic ;
blank : std_logic ;
hsync2 : std_logic ;
vsync2 : std_logic ;
csync2 : std_logic ;
blank2 : std_logic ;
end record;
type control_type is record
int_reg : RegisterType;
state : state_type;
enable : std_logic;
reset : std_logic;
sync_c : std_logic_vector(2 downto 0);
sync_w : std_logic_vector(2 downto 0);
write_pointer_clut : std_logic_vector(7 downto 0);
datain_clut : std_logic_vector(23 downto 0);
write_en_clut : std_logic;
adress : std_logic_vector(31 downto 0);
start : std_logic;
write_pointer : integer range 0 to length;
ram_address : integer range 0 to length;
data : std_logic_vector(31 downto 0);
level : integer range 0 to part + 1;
status : integer range 0 to 3;
hpolarity : std_ulogic;
vpolarity : std_ulogic;
func : std_logic_vector(1 downto 0);
clk_sel : std_logic_vector(1 downto 0);
end record;
type sync_regs is record
s1 : std_logic_vector(2 downto 0);
s2 : std_logic_vector(2 downto 0);
s3 : std_logic_vector(2 downto 0);
end record;
signal t,tin : read_type;
signal r,rin : control_type;
signal sync_w : sync_regs;
signal sync_ra : sync_regs;
signal sync_rb : sync_regs;
signal sync_c : sync_regs;
signal read_status : std_logic_vector(2 downto 0);
signal write_status : std_logic_vector(2 downto 0);
signal write_en : std_logic;
signal res_mod :std_logic;
signal en_mod : std_logic;
signal fifo_en : std_logic;
signal dmai : ahb_dma_in_type;
signal dmao : ahb_dma_out_type;
signal equal : std_logic;
signal hmax : std_logic_vector(15 downto 0);
signal hfporch : std_logic_vector(15 downto 0);
signal hsyncpulse : std_logic_vector(15 downto 0);
signal hvideo : std_logic_vector(15 downto 0);
signal vmax : std_logic_vector(15 downto 0);
signal vfporch : std_logic_vector(15 downto 0);
signal vsyncpulse : std_logic_vector(15 downto 0);
signal vvideo : std_logic_vector(15 downto 0);
signal write_pointer_clut : std_logic_vector(7 downto 0);
signal read_pointer_clut : std_logic_vector(7 downto 0);
signal read_pointer_fifo : std_logic_vector(9 downto 0);
signal write_pointer_fifo : std_logic_vector(9 downto 0);
signal datain_clut : std_logic_vector(23 downto 0);
signal dataout_clut : std_logic_vector(23 downto 0);
signal dataout_fifo : std_logic_vector(31 downto 0);
signal datain_fifo : std_logic_vector(31 downto 0);
signal write_en_clut, read_en_clut : std_logic;
signal vcc : std_logic;
signal read_en_fifo, write_en_fifo : std_logic;
begin
vcc <= '1';
ram0 : syncram_2p generic map (tech => memtech, abits => 10, dbits => 32,
sepclk => 1)
port map (vgaclk, read_en_fifo, read_pointer_fifo, dataout_fifo,clk, write_en_fifo,
write_pointer_fifo, datain_fifo);
clutram : syncram_2p generic map (tech => memtech, abits => 8, dbits => 24,
sepclk => 1)
port map (vgaclk, read_en_clut, read_pointer_clut, dataout_clut, clk, write_en_clut,
write_pointer_clut,datain_clut);
ahb_master : ahbmst generic map (hindex, hirq, VENDOR_GAISLER,
GAISLER_SVGACTRL, 0, 3, 1)
port map (rst, clk, dmai, dmao, ahbi, ahbo);
apbo.pirq <= (others => '0');
apbo.pindex <= pindex;
apbo.pconfig <= pconfig;
control_proc : process(r,rst,sync_c,apbi,fifo_en,write_en,read_status,dmao,res_mod, sync_w)
variable v: control_type;
variable rdata : std_logic_vector(31 downto 0);
variable mem_sel : integer;
variable apbwrite : std_logic;
variable we_fifo : std_logic;
begin
v := r; v.write_en_clut := '0'; rdata := (others =>'0');
mem_sel := conv_integer(apbi.paddr(5 downto 2)); we_fifo := '0';
-- Control part. This part handles the apb-accesses and stores the internal registers
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
apbwrite := apbi.psel(pindex) and apbi.pwrite and apbi.penable;
case apbi.paddr(5 downto 2) is
when "0000" =>
if apbwrite = '1' then
v.enable := apbi.pwdata(0);
v.reset := apbi.pwdata(1);
v.hpolarity := apbi.pwdata(8);
v.vpolarity := apbi.pwdata(9);
v.func := apbi.pwdata(5 downto 4);
v.clk_sel := apbi.pwdata(7 downto 6);
end if;
rdata(9 downto 0) := r.vpolarity & r.hpolarity & r.clk_sel &
r.func & fifo_en & '0' & r.reset & r.enable;
when "1010" =>
if apbwrite = '1' then
v.datain_clut := apbi.pwdata(23 downto 0);
v.write_pointer_clut := apbi.pwdata(31 downto 24);
v.write_en_clut := '1';
end if;
when "0001" =>
if apbwrite = '1' then v.int_reg(1) := apbi.pwdata; end if;
rdata := r.int_reg(1);
when "0010" =>
if apbwrite = '1' then v.int_reg(2) := apbi.pwdata; end if;
rdata := r.int_reg(2);
when "0011" =>
if apbwrite = '1' then v.int_reg(3) := apbi.pwdata; end if;
rdata := r.int_reg(3);
when "0100" =>
if apbwrite = '1' then v.int_reg(4) := apbi.pwdata; end if;
rdata := r.int_reg(4);
when "0101" =>
if apbwrite = '1' then v.int_reg(5) := apbi.pwdata; end if;
rdata := r.int_reg(5);
when "0110" => rdata := conv_std_logic_vector(clk0,32);
when "0111" => rdata := conv_std_logic_vector(clk1,32);
when "1000" => rdata := conv_std_logic_vector(clk2,32);
when "1001" => rdata := conv_std_logic_vector(clk3,32);
when others =>
end case;
------------------------------------------
----------- Control state machine --------
case r.state is
when running =>
if r.enable = '0' then
v.sync_c := "011";
v.state := not_running;
end if;
when not_running =>
if r.enable = '1' then
v.sync_c := "001";
v.state := reset;
end if;
when reset =>
if sync_c.s3 = "001" then
v.sync_c := "010";
v.state := running;
end if;
end case;
-----------------------------------------
----------- Control reset part-----------
if r.reset = '1' or rst = '0' then
v.state := not_running;
v.enable := '0';
v.int_reg := (others => (others => '0'));
v.sync_c := "011";
v.reset := '0';
v.clk_sel := "00";
end if;
------------------------------------------------------------------------------
-- Write part. This part reads from the memory framebuffer and places the data
-- in the designated fifo specified from the generic.
-------------------------------------------------------------------------------
v.start := '0';
if write_en = '0' then
if (r.start or not dmao.active) = '1' then v.start := '1'; end if;
if dmao.ready = '1' then ------------ AHB access part -----------
---------- and Fifo write part ---------
v.data := dmao.rdata(31 downto 0);
v.ram_address := v.write_pointer;
v.write_pointer := v.write_pointer +1; we_fifo := '1';
if v.write_pointer = length then
v.write_pointer := 0;
end if;
v.level := v.level +1;
if dmao.haddr = (9 downto 0 => '0') then
v.adress := (v.adress(31 downto 10) + 1) & dmao.haddr;
else
v.adress := v.adress(31 downto 10) & dmao.haddr;
end if;
if (dmao.haddr(burstlen+1 downto 0) = ((burstlen+1 downto 2 => '1') & "00")) then
v.start := '0';
end if;
end if; ----------------------------------------
v.sync_w := v.sync_w and read_status; ------------ Fifo sync part ------------
if v.level >= (part -1) then
if read_status(r.status) = '1' and v.sync_w(r.status) = '0' and v.level = part then
v.level := 0;
if r.status = 0 then
v.sync_w(2) := '1';
else
v.sync_w(r.status -1) := '1';
end if;
v.status := v.status + 1;
if v.status = 3 then
v.status := 0;
end if;
else
v.start := '0';
end if;
end if;
end if; ------------------------------------------
------------ Write reset part ------------
if res_mod = '0' or write_en = '1' then
if dmao.active = '0' then v.adress := r.int_reg(5); end if;
v.start := '0';
v.sync_w := "000";
v.status := 1;
v.ram_address := 0;
v.write_pointer := 0;
v.level := 0;
end if; ------------------------------------------
if (r.start and dmao.active and not dmao.ready) = '1' then
v.start := '1';
end if;
-- Assertions
rin <= v;
sync_c.s1 <= v.sync_c;
sync_w.s1 <= r.sync_w;
res_mod <= sync_c.s3(1);
en_mod <= sync_c.s3(0);
write_status <= sync_w.s3;
hvideo <= r.int_reg(1)(15 downto 0);
vvideo <= r.int_reg(1)(31 downto 16);
hfporch <= r.int_reg(2)(15 downto 0);
vfporch <= r.int_reg(2)(31 downto 16);
hsyncpulse <= r.int_reg(3)(15 downto 0);
vsyncpulse <= r.int_reg(3)(31 downto 16);
hmax <= r.int_reg(4)(15 downto 0);
vmax <= r.int_reg(4)(31 downto 16);
apbo.prdata <= rdata;
dmai.wdata <= (others => '0');
dmai.burst <= '1';
dmai.irq <= '0';
dmai.size <= "10";
dmai.write <= '0';
dmai.busy <= '0';
dmai.start <= r.start and r.enable;
dmai.address <= r.adress;
write_pointer_fifo <= conv_std_logic_vector(v.ram_address,10);
write_pointer_clut <= r.write_pointer_clut;
datain_fifo <= v.data;
datain_clut <= r.datain_clut;
write_en_clut <= r.write_en_clut;
clk_sel <= r.clk_sel;
write_en_fifo <= we_fifo;
end process;
read_proc : process(t,res_mod,en_mod,write_status,dataout_fifo,sync_rb,dataout_clut,
vmax, hmax, hvideo, hfporch, hsyncpulse, vvideo, vfporch, vsyncpulse, sync_ra, r)
variable v : read_type;
variable inc_pointer : std_logic;
begin
v := t;
v.vsync2 := t.vsync; v.hsync2 := t.hsync; v.csync2 := t.csync;
v.blank2 := t.blank;
-- Syncsignals generation functions.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
if en_mod = '0' then
-- vertical counter
if (t.vcounter = vmax ) and (t.hcounter = hmax ) then
v.vcounter := (others => '0');
elsif t.hcounter = hmax then
v.vcounter := t.vcounter +1;
end if;
-- horizontal counter
if t.hcounter < hmax then v.hcounter := t.hcounter +1;
else v.hcounter := (others => '0'); end if;
-- generate hsync
if t.hcounter < (hvideo+hfporch+hsyncpulse) and (t.hcounter > (hvideo+hfporch -1)) then
v.hsync := r.hpolarity;
else v.hsync := not r.hpolarity; end if;
-- generate vsync
if t.vcounter <= (vvideo+vfporch+vsyncpulse) and (t.vcounter > (vvideo+vfporch)) then
v.vsync := r.vpolarity;
else v.vsync := not r.vpolarity; end if;
--generate csync & blank signal
v.csync := not (v.hsync xor v.vsync);
v.blank := not t.fifo_ren;
--generate fifo_ren -signal
if (t.hcounter = (hmax -1) and t.vcounter = vmax) or
(t.hcounter = (hmax -1 ) and t.vcounter < vvideo) then
v.fifo_ren := '0';
elsif t.hcounter = (hvideo -1) and t.vcounter <= vvideo then
v.fifo_ren := '1';
end if;
--generate fifo_en -signal
if t.vcounter = vmax then
v.fifo_en := '0';
elsif t.vcounter = vvideo and t.hcounter = (hvideo -1) then
v.fifo_en := '1';
end if;
end if;
if r.func /= "01" then -- do not delay strobes when not using CLUT
v.vsync2 := v.vsync; v.hsync2 := v.hsync; v.csync2 := v.csync;
v.blank2 := v.blank;
end if;
-- Sync reset part ---------
if res_mod = '0' then
v.hcounter := hmax;
v.vcounter := vmax - 1;
v.hsync := r.hpolarity;
v.vsync := r.vpolarity;
v.blank := '0';
v.fifo_ren := '1';
v.fifo_en := '1';
end if;
-- Read from fifo.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
inc_pointer := '0';
if t.fifo_en = '0' then
------------ Fifo sync part ------------
if (v.read_pointer_out = 0 or v.read_pointer_out = part or
v.read_pointer_out = (part + part)) and t.fifo_ren = '0'
and v.index = "00"
then
case t.sync is
when "111" | "011" =>
if write_status(0) = '1' then
v.sync := "110"; v.lock := '0';
else v.lock := '1'; end if;
when "110" =>
if write_status(1) = '1' then
v.sync := "101"; v.lock := '0';
else v.lock := '1'; end if;
when "101" =>
if write_status(2) = '1' then
v.sync := "011"; v.lock := '0';
else v.lock := '1'; end if;
when others => null;
end case;
end if;
------------------------------------------
------------ Fifo read part -------------
------------ and CLUT access -------------
if t.fifo_ren = '0' and v.lock = '0' then
case r.func is
when "01" =>
if t.index = "00" then
v.read_pointer_clut := dataout_fifo(31 downto 24);
v.index := "01";
elsif t.index = "01" then
v.read_pointer_clut := dataout_fifo(23 downto 16);
v.index := "10";
elsif t.index = "10" then
v.read_pointer_clut := dataout_fifo(15 downto 8);
v.index := "11";
else
v.read_pointer_clut := dataout_fifo(7 downto 0);
v.index := "00"; inc_pointer := '1';
end if;
v.data_out := dataout_clut;
when "10" =>
if t.index = "00" then
v.data_out := dataout_fifo(31 downto 27) & "000" &
dataout_fifo(26 downto 21) & "00" & dataout_fifo(20 downto 16) & "000";
v.index := "01";
else
v.data_out := dataout_fifo(15 downto 11) & "000" &
dataout_fifo(10 downto 5) & "00" & dataout_fifo(4 downto 0) & "000";
v.index := "00"; inc_pointer := '1';
end if;
when "11" =>
v.data_out := dataout_fifo(23 downto 0);
v.index := "00"; inc_pointer := '1';
when others =>
v.data_out := (23 downto 0 => '1');
v.index := "00"; inc_pointer := '1';
end case;
else
v.data_out := (others => '0');
end if;
if inc_pointer = '1' then
v.read_pointer_out := t.read_pointer;
v.read_pointer := t.read_pointer + 1;
if v.read_pointer = length then
v.read_pointer := 0;
end if;
if v.read_pointer_out = length then
v.read_pointer_out := 0;
end if;
end if;
else
v.data_out := (others => '0');
end if; ------------------------------------------
------------ Fifo read reset part -------
if res_mod = '0' or t.fifo_en = '1' then
v.sync := "111";
v.read_pointer_out := 0;
v.read_pointer := 1;
v.data_out := (others => '0');
v.lock := '1';
v.index := "00";
v.read_pointer_clut := (others => '0');
end if; ------------------------------------------
tin <= v;
sync_ra.s1 <= t.sync;
sync_rb.s1 <= t.fifo_en & "00";
read_status <= sync_ra.s3;
write_en <= sync_rb.s3(2);
fifo_en <= t.fifo_en;
read_pointer_clut <= v.read_pointer_clut;
read_pointer_fifo <= conv_std_logic_vector(v.read_pointer_out,10);
read_en_fifo <= not v.fifo_ren;
read_en_clut <= not v.fifo_ren and not r.func(1) and r.func(0);
vgao.video_out_r <= t.data_out(23 downto 16);
vgao.video_out_g <= t.data_out(15 downto 8);
vgao.video_out_b <= t.data_out(7 downto 0);
vgao.hsync <= t.hsync2;
vgao.vsync <= t.vsync2;
vgao.comp_sync <= t.csync2;
vgao.blank <= t.blank2;
end process;
proc_clk : process(clk)
begin
if rising_edge(clk) then
r <= rin; -- Control
sync_ra.s2 <= sync_ra.s1; -- Write
sync_ra.s3 <= sync_ra.s2; -- Write
sync_rb.s2 <= sync_rb.s1; -- Write
sync_rb.s3 <= sync_rb.s2; -- Write
end if;
end process;
proc_vgaclk : process(vgaclk)
begin
if rising_edge(vgaclk) then
t <= tin; -- Read
sync_c.s2 <= sync_c.s1; -- Control
sync_c.s3 <= sync_c.s2; -- Control
sync_w.s2 <= sync_w.s1; -- Read
sync_w.s3 <= sync_w.s2; -- Read
end if;
end process;
end ;
| mit | 43017a001f94dbc6db78bcd78604675b | 0.491768 | 3.541163 | false | false | false | false |
michaelfivez/ascon_hardware_implementation | ascon128128_serialized/API_plus_CipherCore/CypherCore.vhd | 1 | 14,104 | -------------------------------------------------------------------------------
--! @project Serialized hardware implementation of Asconv128128
--! @author Michael Fivez
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is an hardware implementation made for my graduation thesis
--! at the KULeuven, in the COSIC department (year 2015-2016)
--! The thesis is titled 'Energy efficient hardware implementations of CAESAR submissions',
--! and can be found on the COSIC website (www.esat.kuleuven.be/cosic/publications)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
entity CipherCore is
generic (
G_NPUB_SIZE : integer := 128; --! Npub size (bits)
G_NSEC_SIZE : integer := 128; --! Nsec size (bits)
G_DBLK_SIZE : integer := 128; --! Data Block size (bits)
G_KEY_SIZE : integer := 128; --! Key size (bits)
G_RDKEY_SIZE : integer := 128; --! Round Key size (bits)
G_TAG_SIZE : integer := 128; --! Tag size (bits)
G_BS_BYTES : integer := 4; --! The number of bits required to hold block size expressed in bytes = log2_ceil(max(G_ABLK_SIZE,G_DBLK_SIZE)/8)
G_CTR_AD_SIZE : integer := 64; --! Maximum size for the counter that keeps track of authenticated data
G_CTR_D_SIZE : integer := 64 --! Maximum size for the counter that keeps track of data
);
port (
clk : in std_logic;
rst : in std_logic;
npub : in std_logic_vector(G_NPUB_SIZE -1 downto 0);
nsec : in std_logic_vector(G_NSEC_SIZE -1 downto 0);
key : in std_logic_vector(G_KEY_SIZE -1 downto 0);
rdkey : in std_logic_vector(G_RDKEY_SIZE -1 downto 0);
bdi : in std_logic_vector(G_DBLK_SIZE -1 downto 0);
exp_tag : in std_logic_vector(G_TAG_SIZE -1 downto 0);
len_a : in std_logic_vector(G_CTR_AD_SIZE -1 downto 0);
len_d : in std_logic_vector(G_CTR_D_SIZE -1 downto 0);
key_ready : in std_logic;
key_updated : out std_logic;
key_needs_update : in std_logic;
rdkey_ready : in std_logic;
rdkey_read : out std_logic;
npub_ready : in std_logic;
npub_read : out std_logic;
nsec_ready : in std_logic;
nsec_read : out std_logic;
bdi_ready : in std_logic;
bdi_proc : in std_logic;
bdi_ad : in std_logic;
bdi_nsec : in std_logic;
bdi_pad : in std_logic;
bdi_decrypt : in std_logic;
bdi_eot : in std_logic;
bdi_eoi : in std_logic;
bdi_read : out std_logic;
bdi_size : in std_logic_vector(G_BS_BYTES -1 downto 0);
bdi_valid_bytes : in std_logic_vector(G_DBLK_SIZE/8 -1 downto 0);
bdi_pad_loc : in std_logic_vector(G_DBLK_SIZE/8 -1 downto 0);
bdi_nodata : in std_logic;
exp_tag_ready : in std_logic;
bdo_ready : in std_logic;
bdo_write : out std_logic;
bdo : out std_logic_vector(G_DBLK_SIZE -1 downto 0);
bdo_size : out std_logic_vector(G_BS_BYTES+1 -1 downto 0);
bdo_nsec : out std_logic;
tag_ready : in std_logic;
tag_write : out std_logic;
tag : out std_logic_vector(G_TAG_SIZE -1 downto 0);
msg_auth_done : out std_logic;
msg_auth_valid : out std_logic
);
end entity CipherCore;
architecture structure of CipherCore is
-- Registers
signal keyreg,npubreg : std_logic_vector(127 downto 0);
-- Control signals AsconCore
signal AsconStart : std_logic;
signal AsconMode : std_logic_vector(3 downto 0);
signal AsconBusy : std_logic;
signal AsconSize : std_logic_vector(3 downto 0);
signal AsconInput : std_logic_vector(127 downto 0);
-- Internal Datapath signals
signal AsconOutput : std_logic_vector(127 downto 0);
begin
-- Morus_core entity
AsconCore : entity work.Ascon_StateUpdate port map(clk,rst,AsconStart,AsconMode,AsconSize,npubreg,keyreg,AsconInput,AsconBusy,AsconOutput);
----------------------------------------
------ DataPath for CipherCore ---------
----------------------------------------
datapath: process(AsconOutput,exp_tag,bdi,AsconInput) is
begin
-- Connect signals to the MorusCore
AsconInput <= bdi;
tag <= AsconOutput;
bdo <= AsconOutput;
if AsconOutput = exp_tag then
msg_auth_valid <= '1';
else
msg_auth_valid <= '0';
end if;
end process datapath;
----------------------------------------
------ ControlPath for CipherCore ------
----------------------------------------
fsm: process(clk, rst) is
type state_type is (IDLE,INIT_1,INIT_2,PROCESSING,RUN_CIPHER_1,RUN_CIPHER_2,RUN_CIPHER_3,TAG_1,TAG_2);
variable CurrState : state_type := IDLE;
variable firstblock : std_logic;
variable lastblock : std_logic_vector(1 downto 0);
variable afterRunning : std_logic_vector(2 downto 0);
begin
if(clk = '1' and clk'event) then
if rst = '1' then -- synchornous reset
key_updated <= '0';
CurrState := IDLE;
firstblock := '0';
keyreg <= (others => '0');
npubreg <= (others => '0');
AsconMode <= (others => '0'); -- the mode is a register
afterRunning := (others => '0');
else
-- registers above in reset are used
-- Standard values of the control signals are zero
AsconStart <= '0';
bdi_read <= '0';
msg_auth_done <= '0';
bdo_write <= '0';
bdo_size <= "10000";
tag_write <= '0';
npub_read <= '0';
AsconSize <= (others => '0');
FsmLogic: case CurrState is
when IDLE =>
-- if key_needs_update = '1' then -- Key needs updating
-- if key_ready = '1' then
-- key_updated <= '1';
-- keyreg <= key;
-- CurrState := IDLE;
-- else
-- CurrState := IDLE;
-- end if;
if key_needs_update = '1' and key_ready = '1' then -- Key needs updating
key_updated <= '1';
keyreg <= key;
CurrState := IDLE;
elsif bdi_proc = '1' and npub_ready = '1' then -- start of processing
CurrState := INIT_1;
npubreg <= npub;
npub_read <= '1';
AsconMode <= "0010"; -- Mode: initialization
AsconStart <= '1';
else
CurrState := IDLE;
end if;
when INIT_1 =>
if AsconBusy = '1' then
CurrState := INIT_2; -- to INIT_2
else
AsconStart <= '1';
CurrState := INIT_1; -- to INIT_1
end if;
when INIT_2 =>
if AsconBusy = '0' then
CurrState := PROCESSING; -- to PROCESSING
firstblock := '1';
lastblock := "00";
else
CurrState := INIT_2; -- to INIT_2
end if;
-- EVEN SIMPLIFY THIS AFTER YOU SEE IF WORKS
when PROCESSING =>
if lastblock(1) = '1' then -- Generate the Tag
AsconMode <= "0001";
AsconStart <= '1';
CurrState := TAG_1;
elsif bdi_ready = '1' then
if firstblock = '1' and bdi_ad = '0' then -- No associative data (and return in function)
-- SEP_CONST
AsconMode <= "0011";
AsconStart <= '1';
CurrState := PROCESSING;
elsif bdi_ad = '1' then
if bdi_eot = '0' then
-- AD_PROCESS
AsconMode <= "0000";
AsconStart <= '1';
afterRunning := "000";
CurrState := RUN_CIPHER_1;
elsif bdi_eoi = '0' then
if bdi_size = "0000" then
-- AD_PROCESS + case2 + SEP_CONST
AsconMode <= "0000";
AsconStart <= '1';
afterRunning := "001";
CurrState := RUN_CIPHER_1;
else
-- AD_PROCESS + SEP_CONST
AsconMode <= "0000";
AsconStart <= '1';
afterRunning := "010";
CurrState := RUN_CIPHER_1;
end if;
else
if bdi_size = "0000" then
-- AD_PROCESS + case2 + SEP_CONST + case1
AsconMode <= "0000";
AsconStart <= '1';
afterRunning := "101";
CurrState := RUN_CIPHER_1;
else
-- AD_PROCESS + SEP_CONST + case1
AsconMode <= "0000";
AsconStart <= '1';
afterRunning := "110";
CurrState := RUN_CIPHER_1;
end if;
end if;
else
if bdi_decrypt = '0' then
if bdi_eot = '0' then
-- ENCRYPT
AsconMode <= "0110";
AsconStart <= '1';
afterRunning := "011";
CurrState := RUN_CIPHER_1;
elsif bdi_size = "0000" then
-- ENCRYPT + case1
AsconMode <= "0110";
AsconStart <= '1';
afterRunning := "100";
CurrState := RUN_CIPHER_1;
else
-- LAST_BLOCK_ENCRYPT
bdi_read <= '1';
AsconMode <= "0111";
AsconStart <= '1';
afterRunning := "011";
CurrState := RUN_CIPHER_2;
end if;
else
if bdi_eot = '0' then
-- DECRYPT
AsconMode <= "0100";
AsconStart <= '1';
afterRunning := "011";
CurrState := RUN_CIPHER_1;
elsif bdi_size = "0000" then
-- DECRYPT + case1
AsconMode <= "0100";
AsconStart <= '1';
afterRunning := "100";
CurrState := RUN_CIPHER_1;
else
-- LAST_BLOCK_DECRYPT
bdi_read <= '1';
AsconMode <= "0101";
AsconStart <= '1';
AsconSize <= bdi_size;
afterRunning := "011";
CurrState := RUN_CIPHER_2;
end if;
end if;
end if;
-- check if tag after (eoi, with special case when no associative data:
-- This is needed, because if no associative data, it will do it's thing and then still the message block is
-- left to be processed
if firstblock = '1' and bdi_ad = '0' then -- lastblock will be set next return in the function
lastblock := "00";
elsif bdi_eoi = '1' and bdi_decrypt = '0' then -- the one after is tag encryption
lastblock := "10";
elsif bdi_eoi = '1' then -- the one after is tag decryption
lastblock := "11";
end if;
-- not firstblock anymore :
firstblock := '0';
end if;
when RUN_CIPHER_1 =>
if AsconBusy = '1' then
CurrState := RUN_CIPHER_2;
bdi_read <= '1';
else
AsconStart <= '1';
CurrState := RUN_CIPHER_1;
end if;
when RUN_CIPHER_3 =>
if AsconBusy = '1' then
CurrState := RUN_CIPHER_2;
else
AsconStart <= '1';
CurrState := RUN_CIPHER_3;
end if;
when RUN_CIPHER_2 =>
if AsconBusy = '0' then
-- logic here:
-- a simple variable is used for the cases where after the cipher something special has to be done:
-- activating authregister after associative data = 1
-- resetting of blocknumber after last associative data = 2 (so also do 1's job)
-- giving of output after encryption/decryption = 3 for encryption, 4 for decryption
-- activating checksum after decription of message = 4
-- special giving of output after padded encryption/decryption = 5 and 6 (determines output_sel), also wait with bdi_read
AfterRunLogic: case afterRunning is
when "000" => -- return to IDLE
CurrState := PROCESSING;
when "001" => -- case2 and sep_cont after
AsconMode <= "1001";
AsconStart <= '1';
CurrState := RUN_CIPHER_3;
afterRunning := "010";
when "010" => -- SEPCONSTANT and return to IDLE
AsconMode <= "0011";
AsconStart <= '1';
CurrState := PROCESSING;
when "011" => -- GIVE OUTPUT and return to IDLE
if bdo_ready = '1' then
bdo_write <= '1';
CurrState := PROCESSING;
else
CurrState := RUN_CIPHER_2;
end if;
when "100" => -- GIVE OUTPUT & case1 and return to IDLE
if bdo_ready = '1' then
bdo_write <= '1';
CurrState := PROCESSING;
AsconMode <= "1000";
AsconStart <= '1';
else
CurrState := RUN_CIPHER_2;
end if;
when "101" => -- case2 and case1 and sep_cont after
AsconMode <= "1001";
AsconStart <= '1';
CurrState := RUN_CIPHER_3;
afterRunning := "110";
when "110" => -- case1 and sep_cont after
AsconMode <= "1000";
AsconStart <= '1';
CurrState := RUN_CIPHER_2;
afterRunning := "010";
when others =>
end case AfterRunLogic;
else
CurrState := RUN_CIPHER_2;
end if;
when TAG_1 =>
if AsconBusy = '1' then
CurrState := TAG_2;
else
AsconStart <= '1';
CurrState := TAG_1;
end if;
when TAG_2 =>
if AsconBusy = '0' and lastblock(0) = '0' then -- Generate Tag
if tag_ready = '1' then
tag_write <= '1';
key_updated <= '0';
CurrState := IDLE;
else
CurrState := TAG_2;
end if;
elsif AsconBusy = '0' then -- Compare Tag
if exp_tag_ready = '1' then
msg_auth_done <= '1';
key_updated <= '0';
CurrState := IDLE;
else
CurrState := TAG_2;
end if;
else
CurrState := TAG_2;
end if;
when others =>
end case FsmLogic;
end if;
end if;
end process fsm;
end architecture structure;
| gpl-3.0 | baa88fbc3c0e578489d6052d2d8c8220 | 0.519073 | 3.404296 | false | false | false | false |
franz/pocl | examples/accel/rtl/platform/almaif_decoder.vhdl | 2 | 11,253 | -- Copyright (c) 2016 Tampere University.
--
-- This file is part of TTA-Based Codesign Environment (TCE).
--
-- Permission is hereby granted, free of charge, to any person obtaining a
-- copy of this software and associated documentation files (the "Software"),
-- to deal in the Software without restriction, including without limitation
-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- and/or sell copies of the Software, and to permit persons to whom the
-- Software is furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
-- DEALINGS IN THE SOFTWARE.
-------------------------------------------------------------------------------
-- Title : Memory access decoder
-- Project : Almarvi
-------------------------------------------------------------------------------
-- File : almaif_decoder.vhdl
-- Author : Aleksi Tervo <[email protected]>
-- Company : TUT/CPC
-- Created : 2017-06-13
-- Last update: 2017-06-13
-- Platform :
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description: Directs memory accesses to either the local memory or an
-- AXI master
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2017-06-13 1.0 tervoa Created
-- 2018-07-30 1.1 tervoa Support for optional sync reset
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.math_real.all;
use work.tce_util.all;
entity almaif_decoder is
generic (
mem_dataw_g : integer := 32;
mem_addrw_g : integer;
axi_addrw_g : integer := 32;
mem_offset_g : integer;
sync_reset_g : integer
); port (
clk : in std_logic;
rstx : in std_logic;
-- Bus from arbiter
arb_avalid_in : in std_logic;
arb_aready_out : out std_logic;
arb_aaddr_in : in std_logic_vector(axi_addrw_g-2-1 downto 0);
arb_awren_in : in std_logic;
arb_astrb_in : in std_logic_vector(mem_dataw_g/8-1 downto 0);
arb_adata_in : in std_logic_vector(mem_dataw_g-1 downto 0);
--
arb_rvalid_out : out std_logic;
arb_rready_in : in std_logic;
arb_rdata_out : out std_logic_vector(mem_dataw_g-1 downto 0);
-- Bus to local memory
mem_avalid_out : out std_logic;
mem_aready_in : in std_logic;
mem_aaddr_out : out std_logic_vector(mem_addrw_g-1 downto 0);
mem_awren_out : out std_logic;
mem_astrb_out : out std_logic_vector(mem_dataw_g/8-1 downto 0);
mem_adata_out : out std_logic_vector(mem_dataw_g-1 downto 0);
--
mem_rvalid_in : in std_logic;
mem_rready_out : out std_logic;
mem_rdata_in : in std_logic_vector(mem_dataw_g-1 downto 0);
-- AXI lite master
m_axi_awvalid : out std_logic;
m_axi_awready : in std_logic;
m_axi_awaddr : out std_logic_vector(axi_addrw_g-1 downto 0);
m_axi_awprot : out std_logic_vector(3-1 downto 0);
--
m_axi_wvalid : out std_logic;
m_axi_wready : in std_logic;
m_axi_wdata : out std_logic_vector(mem_dataw_g-1 downto 0);
m_axi_wstrb : out std_logic_vector(mem_dataw_g/8-1 downto 0);
--
m_axi_bvalid : in std_logic;
m_axi_bready : out std_logic;
--
m_axi_arvalid : out std_logic;
m_axi_arready : in std_logic;
m_axi_araddr : out std_logic_vector(axi_addrw_g-1 downto 0);
m_axi_arprot : out std_logic_vector(3-1 downto 0);
--
m_axi_rvalid : in std_logic;
m_axi_rready : out std_logic;
m_axi_rdata : in std_logic_vector(mem_dataw_g-1 downto 0)
);
end almaif_decoder;
architecture rtl of almaif_decoder is
constant sync_reset_c : boolean := sync_reset_g /= 0;
constant dst_axi_c : std_logic := '1';
constant dst_mem_c : std_logic := '0';
signal dst_sel, fifo_dst_sel, access_success, read_success : std_logic;
signal fifo_data_r : std_logic_vector(4-1 downto 0);
signal fifo_iter_r : unsigned(2-1 downto 0);
constant mem_offset_c : std_logic_vector(axi_addrw_g-2-1 downto 0)
:= std_logic_vector(to_unsigned(mem_offset_g/4, axi_addrw_g-2));
constant mem_mask_c : std_logic_vector(axi_addrw_g-2-1 downto 0)
-- := (mem_addrw_g-2-1 downto 0 => '0', others => '1');
:= not std_logic_vector(to_unsigned(2**(mem_addrw_g-2)-1,
axi_addrw_g-2));
constant mem_width_log2 : integer := integer(ceil(log2(real(mem_dataw_g))));
signal m_axi_wdata_r : std_logic_vector(m_axi_wdata'range);
signal m_axi_wstrb_r : std_logic_vector(m_axi_wstrb'range);
-- All accesses are unprivileged/secure/data
constant axi_axprot_c : std_logic_vector(3-1 downto 0) := "000";
signal m_axi_wvalid_r, write_load : std_logic;
begin
------------------------------------------------------------------------------
-- Direct accesses to AXI or local memory
------------------------------------------------------------------------------
asel_comb : process(arb_aaddr_in, arb_avalid_in, arb_awren_in,
mem_aready_in,
m_axi_arready, m_axi_awready,
m_axi_wvalid_r, m_axi_wready)
begin
mem_avalid_out <= '0';
m_axi_arvalid <= '0';
m_axi_awvalid <= '0';
arb_aready_out <= '0';
access_success <= '0';
write_load <= '0';
dst_sel <= dst_mem_c;
if (arb_aaddr_in and mem_mask_c) = mem_offset_c then
mem_avalid_out <= arb_avalid_in;
arb_aready_out <= mem_aready_in;
access_success <= mem_aready_in and arb_avalid_in;
else
dst_sel <= dst_axi_c;
if arb_awren_in = '0' then
m_axi_arvalid <= arb_avalid_in;
arb_aready_out <= m_axi_arready;
access_success <= arb_avalid_in and m_axi_arready;
elsif arb_awren_in = '1'
and (m_axi_wvalid_r = '0' or m_axi_wready = '1') then
m_axi_awvalid <= arb_avalid_in;
write_load <= '1';
arb_aready_out <= m_axi_awready;
access_success <= arb_avalid_in and m_axi_awready;
end if;
end if;
end process asel_comb;
-- Common signals to memory interface
mem_aaddr_out <= arb_aaddr_in(mem_aaddr_out'range);
mem_awren_out <= arb_awren_in;
mem_astrb_out <= arb_astrb_in;
mem_adata_out <= arb_adata_in;
-- Common signals to AXI
m_axi_awaddr <= arb_aaddr_in & "00";
m_axi_awprot <= axi_axprot_c;
m_axi_araddr <= arb_aaddr_in & "00";
m_axi_arprot <= axi_axprot_c;
------------------------------------------------------------------------------
-- FIFO to keep accesses to local/global memory in order
------------------------------------------------------------------------------
fifo_sync : process(clk, rstx)
variable fifo_data_v : std_logic_vector(fifo_data_r'range);
variable fifo_iter_v : unsigned(fifo_iter_r'range);
begin
if not sync_reset_c and rstx = '0' then
fifo_data_r <= (others => '0');
fifo_iter_r <= (others => '0');
elsif rising_edge(clk) then
if sync_reset_c and rstx = '0' then
fifo_data_r <= (others => '0');
fifo_iter_r <= (others => '0');
else
fifo_data_v := fifo_data_r;
fifo_iter_v := fifo_iter_r;
if read_success = '1' and fifo_iter_r > 0 then
fifo_data_v(fifo_data_v'high-1 downto 0) :=
fifo_data_v(fifo_data_v'high downto 1);
fifo_data_v(fifo_data_v'high) := '0';
fifo_iter_v := fifo_iter_v - 1;
end if;
if access_success = '1' and arb_awren_in = '0' then
fifo_data_v(to_integer(fifo_iter_v)) := dst_sel;
fifo_iter_v := fifo_iter_v + 1;
end if;
fifo_iter_r <= fifo_iter_v;
fifo_data_r <= fifo_data_v;
end if;
end if;
end process fifo_sync;
fifo_dst_sel <= fifo_data_r(0);
------------------------------------------------------------------------------
-- Select response to direct to arbiter
------------------------------------------------------------------------------
rsel_comb : process(fifo_dst_sel, m_axi_rvalid, arb_rready_in, mem_rvalid_in,
m_axi_rdata, mem_rdata_in)
begin
if fifo_dst_sel = dst_axi_c then
arb_rvalid_out <= m_axi_rvalid;
mem_rready_out <= '0';
m_axi_rready <= arb_rready_in;
arb_rdata_out <= m_axi_rdata;
read_success <= arb_rready_in and m_axi_rvalid;
else
arb_rvalid_out <= mem_rvalid_in;
mem_rready_out <= arb_rready_in;
m_axi_rready <= '0';
arb_rdata_out <= mem_rdata_in;
read_success <= arb_rready_in and mem_rvalid_in;
end if;
end process rsel_comb;
------------------------------------------------------------------------------
-- AXI write, response channels : drive m_axi_{w,b}* out ports
------------------------------------------------------------------------------
axi_w_channels_sync : process(clk, rstx)
begin
if not sync_reset_c and rstx = '0' then
m_axi_wvalid_r <= '0';
m_axi_wdata_r <= (others => '0');
m_axi_wstrb_r <= (others => '0');
elsif rising_edge(clk) then
if sync_reset_c and rstx = '0' then
m_axi_wvalid_r <= '0';
m_axi_wdata_r <= (others => '0');
m_axi_wstrb_r <= (others => '0');
else
if m_axi_wready = '1' then
m_axi_wvalid_r <= '0';
end if;
if write_load = '1' and m_axi_awready = '1' then
m_axi_wvalid_r <= '1';
m_axi_wdata_r <= arb_adata_in;
m_axi_wstrb_r <= arb_astrb_in;
end if;
end if;
end if;
end process axi_w_channels_sync;
m_axi_wvalid <= m_axi_wvalid_r;
m_axi_wdata <= m_axi_wdata_r;
m_axi_wstrb <= m_axi_wstrb_r;
-- Ignore the response
m_axi_bready <= '1';
------------------------------------------------------------------------------
-- Design-wide checks:
------------------------------------------------------------------------------
-- coverage off
-- pragma translate_off
assert 2**mem_width_log2 = mem_dataw_g and mem_dataw_g >= 8
report "Data width must be a power-of-two multiple of bytes"
severity failure;
assert (mem_offset_c and mem_mask_c) = mem_offset_c
report "Memory must be aligned to its size"
severity failure;
assert mem_addrw_g <= axi_addrw_g
report "Memory must fit in AXI address space"
severity failure;
-- pragma translate_on
-- coverage on
end architecture rtl;
| mit | 5e23912edb0dc2d373a8fe5cf40a05a6 | 0.538168 | 3.406903 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/techmap/maps/clkpad.vhd | 2 | 3,185 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: clkpad
-- File: clkpad.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Clock pad with technology wrapper
------------------------------------------------------------------------------
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allpads.all;
entity clkpad is
generic (tech : integer := 0; level : integer := 0;
voltage : integer := x33v; arch : integer := 0;
hf : integer := 0);
port (pad : in std_ulogic; o : out std_ulogic; rstn : in std_ulogic := '1');
end;
architecture rtl of clkpad is
begin
gen0 : if has_pads(tech) = 0 generate
o <= to_X01(pad);
end generate;
xcv : if (tech = virtex) generate
u0 : virtex_clkpad generic map (level, voltage, 0, 0) port map (pad, o, rstn);
end generate;
xcv2 : if (tech = virtex2) or (tech = spartan3) or (tech = virtex4) or (tech = spartan3e) or (tech = virtex5) generate
u0 : virtex_clkpad generic map (level, voltage, arch, hf) port map (pad, o, rstn);
end generate;
axc : if (tech = axcel) generate
u0 : axcel_clkpad generic map (level, voltage) port map (pad, o);
end generate;
pa3 : if (tech = proasic) or (tech = apa3) generate
u0 : apa3_clkpad generic map (level, voltage) port map (pad, o);
end generate;
atc : if (tech = atc18s) generate
u0 : atc18_clkpad generic map (level, voltage) port map (pad, o);
end generate;
atcrh : if (tech = atc18rha) generate
u0 : atc18rha_clkpad generic map (level, voltage) port map (pad, o);
end generate;
um : if (tech = umc) generate
u0 : umc_inpad generic map (level, voltage) port map (pad, o);
end generate;
rhu : if (tech = rhumc) generate
u0 : rhumc_inpad generic map (level, voltage) port map (pad, o);
end generate;
ihp : if (tech = ihp25) generate
u0 : ihp25_clkpad generic map (level, voltage) port map (pad, o);
end generate;
rh18t : if (tech = rhlib18t) generate
u0 : rh_lib18t_inpad port map (pad, o);
end generate;
ut025 : if (tech = ut25) generate
u0 : ut025crh_inpad port map (pad, o);
end generate;
pere : if (tech = peregrine) generate
u0 : peregrine_inpad port map (pad, o);
end generate;
end;
| mit | c803cf49f940217a32d4fbdfd407aef4 | 0.62606 | 3.677829 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/ata/atactrl_dma.vhd | 2 | 18,942 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: atactrl
-- File: atactrl.vhd
-- Author: Nils-Johan Wessman, Gaisler Research
-- Description: ATA controller
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
use grlib.amba.all;
use grlib.devices.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.ata.all;
use gaisler.misc.all; --2007-1-16
use gaisler.ata_inf.all;
library opencores;
use opencores.occomp.all;
entity atactrl_dma is
generic (
tech : integer := 0;
fdepth : integer := 8;
mhindex : integer := 0;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#ff0#;
pirq : integer := 0;
TWIDTH : natural := 8; -- counter width
-- PIO mode 0 settings (@100MHz clock)
PIO_mode0_T1 : natural := 6; -- 70ns
PIO_mode0_T2 : natural := 28; -- 290ns
PIO_mode0_T4 : natural := 2; -- 30ns
PIO_mode0_Teoc : natural := 23 -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240
);
port (
rst : in std_ulogic;
arst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
cfo : out cf_out_type;
-- ATA signals
ddin : in std_logic_vector(15 downto 0);
iordy : in std_logic;
intrq : in std_logic;
ata_resetn : out std_logic;
ddout : out std_logic_vector(15 downto 0);
ddoe : out std_logic;
da : out std_logic_vector(2 downto 0);
cs0n : out std_logic;
cs1n : out std_logic;
diorn : out std_logic;
diown : out std_logic;
dmack : out std_logic;
dmarq : in std_logic
);
end;
architecture rtl of atactrl_dma is
-- Device ID
constant DeviceId : integer := 2;
constant RevisionNo : integer := 0;
constant VERSION : integer := 0;
component atahost_amba_slave is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#ff0#;
pirq : integer := 0;
DeviceID : integer := 0;
RevisionNo : integer := 0;
-- PIO mode 0 settings (@100MHz clock)
PIO_mode0_T1 : natural := 6; -- 70ns
PIO_mode0_T2 : natural := 28; -- 290ns
PIO_mode0_T4 : natural := 2; -- 30ns
PIO_mode0_Teoc : natural := 23; -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240
-- Multiword DMA mode 0 settings (@100MHz clock)
DMA_mode0_Tm : natural := 4; -- 50ns
DMA_mode0_Td : natural := 21; -- 215ns
DMA_mode0_Teoc : natural := 21 -- 215ns ==> T0 - Td - Tm = 480 - 50 - 215 = 215
);
port (
rst : in std_ulogic;
arst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
cf_power: out std_logic;
-- ata controller signals
-- PIO control input
PIOsel : out std_logic;
PIOtip, -- PIO transfer in progress
PIOack : in std_logic; -- PIO acknowledge signal
PIOq : in std_logic_vector(15 downto 0); -- PIO data input
PIOpp_full : in std_logic; -- PIO write-ping-pong buffers full
irq : in std_logic; -- interrupt signal input
PIOa : out std_logic_vector(3 downto 0);
PIOd : out std_logic_vector(15 downto 0);
PIOwe : out std_logic;
-- DMA control inputs
-- DMAsel : out std_logic;
DMAtip, -- DMA transfer in progress
-- DMAack, -- DMA transfer acknowledge
DMARxEmpty, -- DMA receive buffer empty
DMATxFull, -- DMA transmit buffer full
DMA_dmarq : in std_logic; -- wishbone DMA request
-- DMAq : in std_logic_vector(31 downto 0);
-- outputs
-- control register outputs
IDEctrl_rst,
IDEctrl_IDEen,
IDEctrl_FATR1,
IDEctrl_FATR0,
IDEctrl_ppen,
DMActrl_DMAen,
DMActrl_dir,
DMActrl_Bytesw, --Jagre 2006-12-04
DMActrl_BeLeC0,
DMActrl_BeLeC1 : out std_logic;
-- CMD port timing registers
PIO_cmdport_T1,
PIO_cmdport_T2,
PIO_cmdport_T4,
PIO_cmdport_Teoc : out std_logic_vector(7 downto 0);
PIO_cmdport_IORDYen : out std_logic;
-- data-port0 timing registers
PIO_dport0_T1,
PIO_dport0_T2,
PIO_dport0_T4,
PIO_dport0_Teoc : out std_logic_vector(7 downto 0);
PIO_dport0_IORDYen : out std_logic;
-- data-port1 timing registers
PIO_dport1_T1,
PIO_dport1_T2,
PIO_dport1_T4,
PIO_dport1_Teoc : out std_logic_vector(7 downto 0);
PIO_dport1_IORDYen : out std_logic;
-- DMA device0 timing registers
DMA_dev0_Tm,
DMA_dev0_Td,
DMA_dev0_Teoc : out std_logic_vector(7 downto 0);
-- DMA device1 timing registers
DMA_dev1_Tm,
DMA_dev1_Td,
DMA_dev1_Teoc : out std_logic_vector(7 downto 0);
-- Bus master edits by Erik Jagre 2006-10-03 ------------------start-----
fr_BM : in bm_to_slv_type;
to_BM : out slv_to_bm_type
-- Bus master edits by Erik Jagre 2006-10-03 ------------------end-------
);
end component atahost_amba_slave;
component atahost_ahbmst is
generic(fdepth : integer := 8);
Port(clk : in std_logic;
rst : in std_logic;
i : in bmi_type;
o : out bmo_type
);
end component atahost_ahbmst;
-- asynchronous reset signal
signal arst_signal : std_logic;
-- primary address decoder
-- signal PIOsel,s_bmen : std_logic; -- controller select, IDE devices select
signal PIOsel : std_logic; -- controller select, IDE devices select
-- control signal
signal IDEctrl_rst, IDEctrl_IDEen, IDEctrl_FATR0, IDEctrl_FATR1 : std_logic;
-- compatible mode timing
signal s_PIO_cmdport_T1, s_PIO_cmdport_T2, s_PIO_cmdport_T4, s_PIO_cmdport_Teoc : std_logic_vector(7 downto 0);
signal s_PIO_cmdport_IORDYen : std_logic;
-- data port0 timing
signal s_PIO_dport0_T1, s_PIO_dport0_T2, s_PIO_dport0_T4, s_PIO_dport0_Teoc : std_logic_vector(7 downto 0);
signal s_PIO_dport0_IORDYen : std_logic;
-- data port1 timing
signal s_PIO_dport1_T1, s_PIO_dport1_T2, s_PIO_dport1_T4, s_PIO_dport1_Teoc : std_logic_vector(7 downto 0);
signal s_PIO_dport1_IORDYen : std_logic;
signal PIOack : std_logic;
signal PIOq : std_logic_vector(15 downto 0);
signal PIOa : std_logic_vector(3 downto 0):="0000";
signal PIOd : std_logic_vector(15 downto 0) := X"0000";
signal PIOwe : std_logic;
signal irq : std_logic; -- ATA bus IRQ signal
signal reset : std_logic;
signal gnd,vcc : std_logic;
signal gnd32 : std_logic_vector(31 downto 0);
--**********************SIGNAL DECLARATION*****by Erik Jagre 2006-10-04*******
signal s_PIOtip : std_logic:='0'; -- PIO transfer in progress
signal s_PIOpp_full : std_logic:='0'; -- PIO Write PingPong full
-- DMA registers
signal s_DMA_dev0_Td,
s_DMA_dev0_Tm,
s_DMA_dev0_Teoc : std_logic_vector(7 downto 0):= X"03"; -- DMA timing settings for device0
signal s_DMA_dev1_Td,
s_DMA_dev1_Tm,
s_DMA_dev1_Teoc : std_logic_vector(7 downto 0):= X"03"; -- DMA timing settings for device1
signal s_DMActrl_DMAen,
s_DMActrl_dir,
s_DMActrl_Bytesw,
s_DMActrl_BeLeC0,
s_DMActrl_BeLeC1 : std_logic:='0'; -- DMA settings
-- signal s_DMAsel : std_logic:='0'; -- DMA controller select
-- signal s_DMAack : std_logic:='0'; -- DMA controller acknowledge
-- signal s_DMAq : std_logic_vector(31 downto 0); -- DMA data out
-- signal s_DMAtip : std_logic:='0'; -- DMA transfer in progress
signal s_DMA_dmarq : std_logic:='0'; -- Synchronized ATA DMARQ line
-- signal s_DMATxFull : std_logic:='0'; -- DMA transmit buffer full
-- signal s_DMARxEmpty : std_logic:='0'; -- DMA receive buffer empty
-- signal s_DMA_req : std_logic:='0'; -- DMA request to external DMA engine
-- signal s_DMA_ack : std_logic:='0'; -- DMA acknowledge from external DMA engine
signal s_IDEctrl_ppen : std_logic; --:='0';
signal datemp : std_logic_vector(2 downto 0):="000";
-- signal s_mst_bm : ahb_dma_out_type;
-- signal s_bm_mst : ahb_dma_in_type;
-- signal s_slv_bm : slv_to_bm_type := SLV_TO_BM_RESET_VECTOR;
-- signal s_bm_slv : bm_to_slv_type := BM_TO_SLV_RESET_VECTOR;
-- signal s_bm_ctr : bm_to_ctrl_type;
-- signal s_ctr_bm : ctrl_to_bm_type;
signal s_bmi : bmi_type;
signal s_bmo : bmo_type;
signal s_d : std_logic_vector(31 downto 0);
signal s_we, s_irq : std_logic;
constant DMA_mode0_Tm : natural := 4; -- 50ns
constant DMA_mode0_Td : natural := 21; -- 215ns
constant DMA_mode0_Teoc : natural := 21; -- 215ns ==> T0 - Td - Tm = 480 - 50 - 215 = 215
constant SECTOR_LENGTH : integer := 16;
-- signal PIOa_temp : std_logic_vector(7 downto 0);
--**********************END SIGNAL DECLARATION********************************
begin
gnd <= '0';vcc <= '1'; gnd32 <= zero32;
-- generate asynchronous reset level
arst_signal <= arst;-- xor ARST_LVL;
reset <= not rst;
da<=datemp;
--PIOa_temp <= unsigned(PIOa);
--dmack <= vcc; -- Disable DMA
-- Generate CompactFlash signals
--cfo.power connected to bit 31 of the control register
cfo.atasel <= gnd;
cfo.we <= vcc;
cfo.csel <= gnd;
cfo.da <= (others => gnd);
--s_bmi.fr_mst<=s_mst_bm; s_bmi.fr_slv<=s_slv_bm; s_bmi.fr_ctr<=s_ctr_bm;
--s_bmo.to_mst<=s_bm_mst; s_bmo.to_slv<=s_slv_bm; s_bmo.to_ctr<=s_bm_ctr;
with s_bmi.fr_slv.en select
s_d(15 downto 0)<=s_bmo.d(15 downto 0) when '1',
PIOd when others;
with s_bmi.fr_slv.en select
s_d(31 downto 16)<=s_bmo.d(31 downto 16) when '1',
(others=>'0') when others;
with s_bmi.fr_slv.en select
s_we<=s_bmo.we when '1',
PIOwe when others;
with s_bmi.fr_slv.en select --for guaranteeing coherent memory before irq
s_irq<=irq and (not s_bmo.to_mst.start) when '1',
irq when others;
s_bmi.fr_ctr.irq<=irq;
slv: atahost_amba_slave
generic map(
hindex => hindex,
haddr => haddr,
hmask => hmask,
pirq => pirq,
DeviceID => DeviceID,
RevisionNo => RevisionNo,
-- PIO mode 0 settings
PIO_mode0_T1 => PIO_mode0_T1,
PIO_mode0_T2 => PIO_mode0_T2,
PIO_mode0_T4 => PIO_mode0_T4,
PIO_mode0_Teoc => PIO_mode0_Teoc,
-- Multiword DMA mode 0 settings
-- OCIDEC-1 does not support DMA, set registers to zero
DMA_mode0_Tm => 0,
DMA_mode0_Td => 0,
DMA_mode0_Teoc => 0
)
port map(
arst => arst_signal,
rst => rst,
clk => clk,
ahbsi => ahbsi,
ahbso => ahbso,
cf_power => cfo.power, -- power switch for compactflash
-- PIO control input
-- PIOtip is only asserted during a PIO transfer (No shit! ;)
-- Since it is impossible to read the status register and access the PIO registers at the same time
-- this bit is useless (besides using-up resources)
PIOtip => gnd,
PIOack => PIOack,
PIOq => PIOq,
PIOsel => PIOsel,
PIOpp_full => gnd, -- OCIDEC-1 does not support PIO-write PingPong, negate signal
irq => s_irq,
PIOa => PIOa,
PIOd => PIOd,
PIOwe => PIOwe,
-- DMA control inputs (negate all of them)
DMAtip => s_bmi.fr_ctr.tip, --Erik Jagre 2006-11-13
-- DMAack => gnd,
DMARxEmpty => s_bmi.fr_ctr.rx_empty, --Erik Jagre 2006-11-13
DMATxFull => s_bmi.fr_ctr.fifo_rdy, --Erik Jagre 2006-11-13
DMA_dmarq => s_DMA_dmarq, --Erik Jagre 2006-11-13
-- DMAq => gnd32,
-- outputs
-- control register outputs
IDEctrl_rst => IDEctrl_rst,
IDEctrl_IDEen => IDEctrl_IDEen,
IDEctrl_ppen => s_IDEctrl_ppen,
IDEctrl_FATR0 => IDEctrl_FATR0,
IDEctrl_FATR1 => IDEctrl_FATR1,
-- CMD port timing registers
PIO_cmdport_T1 => s_PIO_cmdport_T1,
PIO_cmdport_T2 => s_PIO_cmdport_T2,
PIO_cmdport_T4 => s_PIO_cmdport_T4,
PIO_cmdport_Teoc => s_PIO_cmdport_Teoc,
PIO_cmdport_IORDYen => s_PIO_cmdport_IORDYen,
-- data-port0 timing registers
PIO_dport0_T1 => s_PIO_dport0_T1,
PIO_dport0_T2 => s_PIO_dport0_T2,
PIO_dport0_T4 => s_PIO_dport0_T4,
PIO_dport0_Teoc => s_PIO_dport0_Teoc,
PIO_dport0_IORDYen => s_PIO_dport0_IORDYen,
-- data-port1 timing registers
PIO_dport1_T1 => s_PIO_dport1_T1,
PIO_dport1_T2 => s_PIO_dport1_T2,
PIO_dport1_T4 => s_PIO_dport1_T4,
PIO_dport1_Teoc => s_PIO_dport1_Teoc,
PIO_dport1_IORDYen => s_PIO_dport1_IORDYen,
-- Bus master edits by Erik Jagre 2006-10-04 ---------------start--
DMActrl_Bytesw=> s_DMActrl_Bytesw,
DMActrl_BeLeC0=> s_DMActrl_BeLeC0,
DMActrl_BeLeC1=> s_DMActrl_BeLeC1,
DMActrl_DMAen => s_DMActrl_DMAen,
DMActrl_dir => s_DMActrl_dir,
DMA_dev0_Tm => s_DMA_dev0_Tm,
DMA_dev0_Td => s_DMA_dev0_Td,
DMA_dev0_Teoc => s_DMA_dev0_Teoc,
DMA_dev1_Tm => s_DMA_dev1_Tm,
DMA_dev1_Td => s_DMA_dev1_Td,
DMA_dev1_Teoc => s_DMA_dev1_Teoc,
fr_BM =>s_bmo.to_slv,
to_BM =>s_bmi.fr_slv
-- Bus master edits by Erik Jagre 2006-10-04 ------------------end-------
);
ctr: atahost_controller
generic map(
fdepth => fdepth,
tech => tech,
TWIDTH => TWIDTH,
PIO_mode0_T1 => PIO_mode0_T1,
PIO_mode0_T2 => PIO_mode0_T2,
PIO_mode0_T4 => PIO_mode0_T4,
PIO_mode0_Teoc => PIO_mode0_Teoc,
DMA_mode0_Tm => DMA_mode0_Tm,
DMA_mode0_Td => DMA_mode0_Td,
DMA_mode0_Teoc => DMA_mode0_Teoc
)
port map(
clk => clk,
nReset => arst_signal,
rst => reset,
irq => irq,
IDEctrl_IDEen => IDEctrl_IDEen,
IDEctrl_rst => IDEctrl_rst,
IDEctrl_ppen => s_IDEctrl_ppen,
IDEctrl_FATR0 => IDEctrl_FATR0,
IDEctrl_FATR1 => IDEctrl_FATR1,
a => PIOa,
d => s_d,
we => s_we,
PIO_cmdport_T1 => s_PIO_cmdport_T1,
PIO_cmdport_T2 => s_PIO_cmdport_T2,
PIO_cmdport_T4 => s_PIO_cmdport_T4,
PIO_cmdport_Teoc => s_PIO_cmdport_Teoc,
PIO_cmdport_IORDYen => s_PIO_cmdport_IORDYen,
PIO_dport0_T1 => s_PIO_dport0_T1,
PIO_dport0_T2 => s_PIO_dport0_T2,
PIO_dport0_T4 => s_PIO_dport0_T4,
PIO_dport0_Teoc => s_PIO_dport0_Teoc,
PIO_dport0_IORDYen => s_PIO_dport0_IORDYen,
PIO_dport1_T1 => s_PIO_dport1_T1,
PIO_dport1_T2 => s_PIO_dport1_T2,
PIO_dport1_T4 => s_PIO_dport1_T4,
PIO_dport1_Teoc => s_PIO_dport1_Teoc,
PIO_dport1_IORDYen => s_PIO_dport1_IORDYen,
PIOsel => PIOsel,
PIOack => PIOack,
PIOq => PIOq,
PIOtip => s_PIOtip,
PIOpp_full => s_PIOpp_full,
--DMA
DMActrl_DMAen => s_DMActrl_DMAen,
DMActrl_dir => s_DMActrl_dir,
DMActrl_Bytesw => s_DMActrl_Bytesw,
DMActrl_BeLeC0 => s_DMActrl_BeLeC0,
DMActrl_BeLeC1 => s_DMActrl_BeLeC1,
DMA_dev0_Td => s_DMA_dev0_Td,
DMA_dev0_Tm => s_DMA_dev0_Tm,
DMA_dev0_Teoc => s_DMA_dev0_Teoc,
DMA_dev1_Td => s_DMA_dev1_Td,
DMA_dev1_Tm => s_DMA_dev1_Tm,
DMA_dev1_Teoc => s_DMA_dev1_Teoc,
DMAsel => s_bmo.to_ctr.sel,
DMAack => s_bmi.fr_ctr.ack,
DMAq => s_bmi.fr_ctr.q,
DMAtip_out => s_bmi.fr_ctr.tip,
DMA_dmarq => s_DMA_dmarq,
force_rdy => s_bmo.to_ctr.force_rdy,
fifo_rdy => s_bmi.fr_ctr.fifo_rdy,
DMARxEmpty => s_bmi.fr_ctr.rx_empty,
DMARxFull => s_bmi.fr_ctr.rx_full,
DMA_req => s_bmi.fr_ctr.req,
DMA_ack => s_bmo.to_ctr.ack,
BM_en => s_bmi.fr_slv.en, -- Bus mater enabled, for DMA reset Erik Jagre 2006-10-24
--ATA
RESETn => ata_resetn,
DDi => ddin,
DDo => ddout,
DDoe => ddoe,
DA => datemp,
CS0n => cs0n,
CS1n => cs1n,
DIORn => diorn,
DIOWn => diown,
IORDY => iordy,
INTRQ => intrq,
DMARQ => dmarq,
DMACKn => dmack
);
mst : ahbmst
generic map(
hindex => mhindex,
hirq => 0,
venid => VENDOR_GAISLER,
devid => GAISLER_ATACTRL,
version => 0,
chprot => 3,
incaddr => 4)
port map (
rst => rst,
clk => clk,
dmai => s_bmo.to_mst,
dmao => s_bmi.fr_mst,
ahbi => ahbmi,
ahbo => ahbmo
);
bm : atahost_ahbmst
generic map(fdepth=>fdepth)
port map(
clk => clk,
rst => rst,
i => s_bmi,
o => s_bmo
);
-- pragma translate_off
bootmsg : report_version
generic map ("atactrl" & tost(hindex) &
": ATA controller rev " & tost(VERSION) & ", irq " & tost(pirq));
-- pragma translate_on
end;
| mit | 555e377b1b2f6814cf62bbaa3641d016 | 0.54461 | 3.107283 | false | false | false | false |
cafe-alpha/wascafe | v12/fpga_firmware/wasca/synthesis/submodules/sega_saturn_abus_slave.vhd | 6 | 25,670 | -- sega_saturn_abus_slave.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity sega_saturn_abus_slave is
port (
clock : in std_logic := '0'; -- clock.clk
abus_address : in std_logic_vector(9 downto 0) := (others => '0'); -- abus.address
abus_addressdata : inout std_logic_vector(15 downto 0) := (others => '0'); -- abus.addressdata
abus_chipselect : in std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
abus_read : in std_logic := '0'; -- .read
abus_write : in std_logic_vector(1 downto 0) := (others => '0'); -- .write
--abus_functioncode : in std_logic_vector(1 downto 0) := (others => '0'); -- .functioncode
--abus_timing : in std_logic_vector(2 downto 0) := (others => '0'); -- .timing
abus_waitrequest : out std_logic := '1'; -- .waitrequest
--abus_addressstrobe : in std_logic := '0'; -- .addressstrobe
abus_interrupt : out std_logic := '0'; -- .interrupt
abus_direction : out std_logic := '0'; -- .direction
abus_muxing : out std_logic_vector(1 downto 0) := "01"; -- .muxing
abus_disable_out : out std_logic := '0'; -- .disableout
avalon_read : out std_logic; -- avalon_master.read
avalon_write : out std_logic; -- .write
avalon_waitrequest : in std_logic := '0'; -- .waitrequest
avalon_address : out std_logic_vector(27 downto 0); -- .address
avalon_readdata : in std_logic_vector(15 downto 0) := (others => '0'); -- .readdata
avalon_writedata : out std_logic_vector(15 downto 0); -- .writedata
avalon_burstcount : out std_logic; -- .burstcount
avalon_readdatavalid : in std_logic := '0'; -- .readdatavalid
avalon_nios_read : in std_logic := '0'; -- avalon_master.read
avalon_nios_write : in std_logic := '0'; -- .write
avalon_nios_waitrequest : out std_logic := '0'; -- .waitrequest
avalon_nios_address : in std_logic_vector(7 downto 0) := (others => '0'); -- .address
avalon_nios_writedata : in std_logic_vector(15 downto 0) := (others => '0'); -- .writedata
avalon_nios_burstcount : in std_logic; -- .burstcount
avalon_nios_readdata : out std_logic_vector(15 downto 0) := (others => '0'); -- .readdata
avalon_nios_readdatavalid : out std_logic := '0'; -- .readdatavalid
saturn_reset : in std_logic := '0'; -- .saturn_reset
reset : in std_logic := '0' -- reset.reset
);
end entity sega_saturn_abus_slave;
architecture rtl of sega_saturn_abus_slave is
signal abus_address_ms : std_logic_vector(9 downto 0) := (others => '0'); -- abus.address
signal abus_address_buf : std_logic_vector(9 downto 0) := (others => '0'); -- abus.address
signal abus_addressdata_ms : std_logic_vector(15 downto 0) := (others => '0'); -- .data
signal abus_addressdata_buf : std_logic_vector(15 downto 0) := (others => '0'); -- .data
signal abus_chipselect_ms : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_chipselect_buf : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_read_ms : std_logic := '0'; -- .read
signal abus_read_buf : std_logic := '0'; -- .read
signal abus_write_ms : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_write_buf : std_logic_vector(1 downto 0) := (others => '0'); -- .write
--signal abus_functioncode_ms : std_logic_vector(1 downto 0) := (others => '0'); -- .functioncode
--signal abus_functioncode_buf : std_logic_vector(1 downto 0) := (others => '0'); -- .functioncode
--signal abus_timing_ms : std_logic_vector(2 downto 0) := (others => '0'); -- .timing
--signal abus_timing_buf : std_logic_vector(2 downto 0) := (others => '0'); -- .timing
--signal abus_addressstrobe_ms : std_logic := '0'; -- .addressstrobe
--signal abus_addressstrobe_buf : std_logic := '0'; -- .addressstrobe
signal abus_read_buf2 : std_logic := '0'; -- .read
signal abus_read_buf3 : std_logic := '0'; -- .read
signal abus_read_buf4 : std_logic := '0'; -- .read
signal abus_read_buf5 : std_logic := '0'; -- .read
signal abus_read_buf6 : std_logic := '0'; -- .read
signal abus_read_buf7 : std_logic := '0'; -- .read
signal abus_write_buf2 : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_chipselect_buf2 : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_read_pulse : std_logic := '0'; -- .read
signal abus_write_pulse : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_chipselect_pulse : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_read_pulse_off : std_logic := '0'; -- .read
signal abus_write_pulse_off : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_chipselect_pulse_off : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_anypulse : std_logic := '0';
signal abus_anypulse2 : std_logic := '0';
signal abus_anypulse3 : std_logic := '0';
signal abus_anypulse_off : std_logic := '0';
signal abus_cspulse : std_logic := '0';
signal abus_cspulse2 : std_logic := '0';
signal abus_cspulse3 : std_logic := '0';
signal abus_cspulse4 : std_logic := '0';
signal abus_cspulse5 : std_logic := '0';
signal abus_cspulse6 : std_logic := '0';
signal abus_cspulse7 : std_logic := '0';
signal abus_cspulse_off : std_logic := '0';
signal abus_address_latched : std_logic_vector(25 downto 0) := (others => '0'); -- abus.address
signal abus_chipselect_latched : std_logic_vector(1 downto 0) := (others => '1'); -- abus.address
signal abus_direction_internal : std_logic := '0';
signal abus_muxing_internal : std_logic_vector(1 downto 0) := (others => '0'); -- abus.address
signal abus_data_out : std_logic_vector(15 downto 0) := (others => '0');
signal abus_data_in : std_logic_vector(15 downto 0) := (others => '0');
signal abus_waitrequest_read : std_logic := '0';
signal abus_waitrequest_write : std_logic := '0';
signal abus_waitrequest_read2 : std_logic := '0';
signal abus_waitrequest_write2 : std_logic := '0';
--signal abus_waitrequest_read3 : std_logic := '0';
--signal abus_waitrequest_write3 : std_logic := '0';
--signal abus_waitrequest_read4 : std_logic := '0';
--signal abus_waitrequest_write4 : std_logic := '0';
signal abus_waitrequest_read_off : std_logic := '0';
signal abus_waitrequest_write_off : std_logic := '0';
signal REG_PCNTR : std_logic_vector(15 downto 0) := (others => '0');
signal REG_STATUS : std_logic_vector(15 downto 0) := (others => '0');
signal REG_MODE : std_logic_vector(15 downto 0) := (others => '0');
signal REG_HWVER : std_logic_vector(15 downto 0) := X"0002";
signal REG_SWVER : std_logic_vector(15 downto 0) := (others => '0');
TYPE transaction_dir IS (DIR_NONE,DIR_WRITE,DIR_READ);
SIGNAL my_little_transaction_dir : transaction_dir := DIR_NONE;
TYPE wasca_mode_type IS (MODE_INIT,
MODE_POWER_MEMORY_05M, MODE_POWER_MEMORY_1M, MODE_POWER_MEMORY_2M, MODE_POWER_MEMORY_4M,
MODE_RAM_1M, MODE_RAM_4M,
MODE_ROM_KOF95,
MODE_ROM_ULTRAMAN,
MODE_BOOT);
SIGNAL wasca_mode : wasca_mode_type := MODE_INIT;
begin
abus_direction <= abus_direction_internal;
abus_muxing <= not abus_muxing_internal;
--ignoring functioncode, timing and addressstrobe for now
--abus transactions are async, so first we must latch incoming signals
--to get rid of metastability
process (clock)
begin
if rising_edge(clock) then
--1st stage
abus_address_ms <= abus_address;
abus_addressdata_ms <= abus_addressdata;
abus_chipselect_ms <= abus_chipselect; --work only with CS1 for now
abus_read_ms <= abus_read;
abus_write_ms <= abus_write;
--abus_functioncode_ms <= abus_functioncode;
--abus_timing_ms <= abus_timing;
--abus_addressstrobe_ms <= abus_addressstrobe;
--2nd stage
abus_address_buf <= abus_address_ms;
abus_addressdata_buf <= abus_addressdata_ms;
abus_chipselect_buf <= abus_chipselect_ms;
abus_read_buf <= abus_read_ms;
abus_write_buf <= abus_write_ms;
--abus_functioncode_buf <= abus_functioncode_ms;
--abus_timing_buf <= abus_timing_ms;
--abus_addressstrobe_buf <= abus_addressstrobe_ms;
end if;
end process;
--excluding metastability protection is a bad behavior
--but it lloks like we're out of more options to optimize read pipeline
--abus_read_ms <= abus_read;
--abus_read_buf <= abus_read_ms;
--abus read/write latch
process (clock)
begin
if rising_edge(clock) then
abus_write_buf2 <= abus_write_buf;
abus_read_buf2 <= abus_read_buf;
abus_read_buf3 <= abus_read_buf2;
abus_read_buf4 <= abus_read_buf3;
abus_read_buf5 <= abus_read_buf4;
abus_read_buf6 <= abus_read_buf5;
abus_read_buf7 <= abus_read_buf6;
abus_chipselect_buf2 <= abus_chipselect_buf;
abus_anypulse2 <= abus_anypulse;
abus_anypulse3 <= abus_anypulse2;
abus_cspulse2 <= abus_cspulse;
abus_cspulse3 <= abus_cspulse2;
abus_cspulse4 <= abus_cspulse3;
abus_cspulse5 <= abus_cspulse4;
abus_cspulse6 <= abus_cspulse5;
abus_cspulse7 <= abus_cspulse6;
end if;
end process;
--abus write/read pulse is a falling edge since read and write signals are negative polarity
abus_write_pulse <= abus_write_buf2 and not abus_write_buf;
abus_read_pulse <= abus_read_buf2 and not abus_read_buf;
--abus_chipselect_pulse <= abus_chipselect_buf2 and not abus_chipselect_buf;
abus_chipselect_pulse <= abus_chipselect_buf and not abus_chipselect_ms;
abus_write_pulse_off <= abus_write_buf and not abus_write_buf2;
abus_read_pulse_off <= abus_read_buf and not abus_read_buf2;
abus_chipselect_pulse_off <= abus_chipselect_buf and not abus_chipselect_buf2;
abus_anypulse <= abus_write_pulse(0) or abus_write_pulse(1) or abus_read_pulse or
abus_chipselect_pulse(0) or abus_chipselect_pulse(1) or abus_chipselect_pulse(2);
abus_anypulse_off <= abus_write_pulse_off(0) or abus_write_pulse_off(1) or abus_read_pulse_off or
abus_chipselect_pulse_off(0) or abus_chipselect_pulse_off(1) or abus_chipselect_pulse_off(2);
abus_cspulse <= abus_chipselect_pulse(0) or abus_chipselect_pulse(1) or abus_chipselect_pulse(2);
abus_cspulse_off <= abus_chipselect_pulse_off(0) or abus_chipselect_pulse_off(1) or abus_chipselect_pulse_off(2);
--whatever pulse we've got, latch address
--it might be latched twice per transaction, but it's not a problem
--multiplexer was switched to address after previous transaction or after boot,
--so we have address ready to latch
process (clock)
begin
if rising_edge(clock) then
if abus_anypulse = '1' then
--if abus_read_pulse = '1' or abus_write_pulse(0) = '1' or abus_write_pulse(1)='1' then
abus_address_latched <= abus_address & abus_addressdata_buf(0) & abus_addressdata_buf(12) & abus_addressdata_buf(2) & abus_addressdata_buf(1)
& abus_addressdata_buf(9) & abus_addressdata_buf(10) & abus_addressdata_buf(8) & abus_addressdata_buf(3)
& abus_addressdata_buf(13) & abus_addressdata_buf(14) & abus_addressdata_buf(15) & abus_addressdata_buf(4)
& abus_addressdata_buf(5) & abus_addressdata_buf(6) & abus_addressdata_buf(11) & abus_addressdata_buf(7);
end if;
end if;
end process;
--latch transaction direction
process (clock)
begin
if rising_edge(clock) then
if abus_write_pulse(0) = '1' or abus_write_pulse(1) = '1' then
my_little_transaction_dir <= DIR_WRITE;
elsif abus_read_pulse = '1' then
my_little_transaction_dir <= DIR_READ;
elsif abus_anypulse_off = '1' and abus_cspulse_off = '0' then --ending anything but not cs
my_little_transaction_dir <= DIR_NONE;
end if;
end if;
end process;
--latch chipselect number
process (clock)
begin
if rising_edge(clock) then
if abus_chipselect_pulse(0) = '1' then
abus_chipselect_latched <= "00";
elsif abus_chipselect_pulse(1) = '1' then
abus_chipselect_latched <= "01";
elsif abus_chipselect_pulse(2) = '1' then
abus_chipselect_latched <= "10";
elsif abus_cspulse_off = '1' then
abus_chipselect_latched <= "11";
end if;
end if;
end process;
--if valid transaction captured, switch to corresponding multiplex mode
process (clock)
begin
if rising_edge(clock) then
if abus_chipselect_latched = "11" then
--chipselect deasserted
abus_direction_internal <= '0'; --high-z
abus_muxing_internal <= "01"; --address
else
--chipselect asserted
case (my_little_transaction_dir) is
when DIR_NONE =>
abus_direction_internal <= '0'; --high-z
abus_muxing_internal <= "10"; --data
when DIR_READ =>
abus_direction_internal <= '1'; --active
abus_muxing_internal <= "10"; --data
when DIR_WRITE =>
abus_direction_internal <= '0'; --high-z
abus_muxing_internal <= "10"; --data
end case;
end if;
end if;
end process;
abus_disable_out <= '1' when abus_chipselect_latched(1) = '1' else
'0';
--if abus read access is detected, issue avalon read transaction
--wait until readdatavalid, then disable read and abus wait
process (clock)
begin
if rising_edge(clock) then
--if my_little_transaction_dir = DIR_READ and abus_chipselect_latched(1) = '0' and abus_anypulse2 = '1' then
--starting read transaction at either RD pulse or (CS pulse while RD is on)
--but if CS arrives less than 7 clocks after RD, then we ignore this CS
--this will get us 2 additional clocks at read pipeline
if abus_read_pulse = '1' or (abus_cspulse='1' and abus_read_buf = '0' and abus_read_buf7 = '0') then
avalon_read <= '1';
abus_waitrequest_read <= '1';
elsif avalon_readdatavalid = '1' then
avalon_read <= '0';
abus_waitrequest_read <= '0';
if abus_chipselect_latched = "00" then
--CS0 access
if abus_address_latched(24 downto 0) = "1"&X"FF0FFE" then
--wasca specific SD card control register
abus_data_out <= X"CDCD";
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF0" then
--wasca prepare counter
abus_data_out <= REG_PCNTR;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF2" then
--wasca status register
abus_data_out <= REG_STATUS;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF4" then
--wasca mode register
abus_data_out <= REG_MODE;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF6" then
--wasca hwver register
abus_data_out <= REG_HWVER;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF8" then
--wasca swver register
abus_data_out <= REG_SWVER;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFFA" then
--wasca signature "wa"
abus_data_out <= X"7761";
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFFC" then
--wasca signature "sc"
abus_data_out <= X"7363";
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFFE" then
--wasca signature "a "
abus_data_out <= X"6120";
else
--normal CS0 read access
case wasca_mode is
when MODE_INIT => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_05M => abus_data_out <= X"FFFF";
when MODE_POWER_MEMORY_1M => abus_data_out <= X"FFFF";
when MODE_POWER_MEMORY_2M => abus_data_out <= X"FFFF";
when MODE_POWER_MEMORY_4M => abus_data_out <= X"FFFF";
when MODE_RAM_1M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_RAM_4M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_ROM_KOF95 => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_ROM_ULTRAMAN => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_BOOT => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
end case;
end if;
elsif abus_chipselect_latched = "01" then
--CS1 access
if ( abus_address_latched(23 downto 0) = X"FFFFFE" or abus_address_latched(23 downto 0) = X"FFFFFC" ) then
--saturn cart id register
case wasca_mode is
when MODE_INIT => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_05M => abus_data_out <= X"FF21";
when MODE_POWER_MEMORY_1M => abus_data_out <= X"FF22";
when MODE_POWER_MEMORY_2M => abus_data_out <= X"FF23";
when MODE_POWER_MEMORY_4M => abus_data_out <= X"FF24";
when MODE_RAM_1M => abus_data_out <= X"FF5A";
when MODE_RAM_4M => abus_data_out <= X"FF5C";
when MODE_ROM_KOF95 => abus_data_out <= X"FFFF";
when MODE_ROM_ULTRAMAN => abus_data_out <= X"FFFF";
when MODE_BOOT => abus_data_out <= X"FFFF";
end case;
else
--normal CS1 access
case wasca_mode is
when MODE_INIT => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_05M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_1M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_2M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_4M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_RAM_1M => abus_data_out <= X"FFFF";
when MODE_RAM_4M => abus_data_out <= X"FFFF";
when MODE_ROM_KOF95 => abus_data_out <= X"FFFF";
when MODE_ROM_ULTRAMAN => abus_data_out <= X"FFFF";
when MODE_BOOT => abus_data_out <= X"FFFF";
end case;
end if;
else
--CS2 access
abus_data_out <= X"EEEE";
end if;
end if;
end if;
end process;
--if abus write access is detected, issue avalon write transaction
--disable abus wait immediately
--TODO: check if avalon_writedata is already valid at this moment
process (clock)
begin
if rising_edge(clock) then
if my_little_transaction_dir = DIR_WRITE and abus_chipselect_latched /= "11" and abus_cspulse7 = '1' then
--pass write to avalon
avalon_write <= '1';
abus_waitrequest_write <= '1';
elsif avalon_waitrequest = '0' then
avalon_write <= '0';
abus_waitrequest_write <= '0';
end if;
end if;
end process;
--wasca mode register write
--reset
process (clock)
begin
if rising_edge(clock) then
--if saturn_reset='0' then wasca_mode <= MODE_INIT;
--els
if my_little_transaction_dir = DIR_WRITE and abus_chipselect_latched = "00" and abus_cspulse7 = '1' and
abus_address_latched(23 downto 0) = X"FFFFF4" then
--wasca mode register
REG_MODE <= abus_data_in;
case (abus_data_in (3 downto 0)) is
when X"1" => wasca_mode <= MODE_POWER_MEMORY_05M;
when X"2" => wasca_mode <= MODE_POWER_MEMORY_1M;
when X"3" => wasca_mode <= MODE_POWER_MEMORY_2M;
when X"4" => wasca_mode <= MODE_POWER_MEMORY_4M;
when others =>
case (abus_data_in (7 downto 4)) is
when X"1" => wasca_mode <= MODE_RAM_1M;
when X"2" => wasca_mode <= MODE_RAM_4M;
when others =>
case (abus_data_in (11 downto 8)) is
when X"1" => wasca_mode <= MODE_ROM_KOF95;
when X"2" => wasca_mode <= MODE_ROM_ULTRAMAN;
when others => null;-- wasca_mode <= MODE_INIT;
end case;
end case;
end case;
end if;
end if;
end process;
abus_data_in <= abus_addressdata_buf;
--working only if direction is 1
abus_addressdata <= (others => 'Z') when abus_direction_internal='0' else
abus_data_out;
process (clock)
begin
if rising_edge(clock) then
abus_waitrequest_read2 <= abus_waitrequest_read;
--abus_waitrequest_read3 <= abus_waitrequest_read2;
--abus_waitrequest_read4 <= abus_waitrequest_read3;
abus_waitrequest_write2 <= abus_waitrequest_write;
--abus_waitrequest_write3 <= abus_waitrequest_write3;
--abus_waitrequest_write4 <= abus_waitrequest_write4;
end if;
end process;
process (clock)
begin
if rising_edge(clock) then
abus_waitrequest_read_off <= '0';
abus_waitrequest_write_off <= '0';
if abus_waitrequest_read = '0' and abus_waitrequest_read2 = '1' then
abus_waitrequest_read_off <= '1';
end if;
if abus_waitrequest_write = '0' and abus_waitrequest_write2 = '1' then
abus_waitrequest_write_off <= '1';
end if;
end if;
end process;
--process (clock)
--begin
-- if rising_edge(clock) then
-- --if abus_read_pulse='1' or abus_write_pulse(0)='1' or abus_write_pulse(1)='1' then
-- --if abus_anypulse = '1' then
-- if abus_chipselect_pulse(0) = '1' or abus_chipselect_pulse(1) = '1' then
-- abus_waitrequest <= '0';
-- elsif abus_waitrequest_read_off='1' or abus_waitrequest_write_off='1' then
-- abus_waitrequest <= '1';
-- end if;
-- end if;
--end process;
--avalon-to-abus mapping
--SDRAM is mapped to both CS0 and CS1
avalon_address <= "010" & abus_address_latched(24 downto 0);
avalon_writedata <= abus_data_in(7 downto 0) & abus_data_in (15 downto 8) ;
avalon_burstcount <= '0';
abus_waitrequest <= not (abus_waitrequest_read or abus_waitrequest_write);
--Nios II read interface
process (clock)
begin
if rising_edge(clock) then
avalon_nios_readdatavalid <= '0';
if avalon_nios_read = '1' then
avalon_nios_readdatavalid <= '1';
case avalon_nios_address is
when X"F0" =>
avalon_nios_readdata <= REG_PCNTR;
when X"F2" =>
avalon_nios_readdata <= REG_STATUS;
when X"F4" =>
avalon_nios_readdata <= REG_MODE;
when X"F6" =>
avalon_nios_readdata <= REG_HWVER;
when X"F8" =>
avalon_nios_readdata <= REG_SWVER;
when X"FA" =>
avalon_nios_readdata <= X"ABCD"; --for debug, remove later
when others =>
avalon_nios_readdata <= REG_HWVER; --to simplify mux
end case;
end if;
end if;
end process;
--Nios II write interface
process (clock)
begin
if rising_edge(clock) then
if avalon_nios_write= '1' then
case avalon_nios_address is
when X"F0" =>
REG_PCNTR <= avalon_nios_writedata;
when X"F2" =>
REG_STATUS <= avalon_nios_writedata;
when X"F4" =>
null;
when X"F6" =>
null;
when X"F8" =>
REG_SWVER <= avalon_nios_writedata;
when others =>
null;
end case;
end if;
end if;
end process;
--Nios system interface is only regs, so always ready to write.
avalon_nios_waitrequest <= '0';
end architecture rtl; -- of sega_saturn_abus_slave
| gpl-2.0 | 4f8cc9addcc565efeac84502bd5dfda9 | 0.566887 | 3.36347 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/techmap/eclipsee/memory_eclipse.vhd | 2 | 4,612 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: various
-- File: memory_eclipse.vhd
-- Author: Jiri Gaisler Gaisler Research
-- Description: Memory generators for Quicklogic Eclipse rams
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- translate_off
library eclipsee;
use eclipsee.all;
-- translate_on
entity eclipse_syncram_2p is
generic ( abits : integer := 8; dbits : integer := 32);
port (
rclk : in std_ulogic;
rena : in std_ulogic;
raddr : in std_logic_vector (abits -1 downto 0);
dout : out std_logic_vector (dbits -1 downto 0);
wclk : in std_ulogic;
waddr : in std_logic_vector (abits -1 downto 0);
din : in std_logic_vector (dbits -1 downto 0);
write : in std_ulogic);
end;
architecture rtl of eclipse_syncram_2p is
component RAM128X18_25um is
port (WA, RA : in std_logic_vector (6 downto 0);
WD : in std_logic_vector (17 downto 0);
WE, RE, WCLK, RCLK, ASYNCRD : in std_logic;
RD : out std_logic_vector (17 downto 0) );
end component;
component RAM256X9_25um is
port (WA, RA : in std_logic_vector (7 downto 0);
WD : in std_logic_vector (8 downto 0);
WE, RE, WCLK, RCLK, ASYNCRD : in std_logic;
RD : out std_logic_vector (8 downto 0) );
end component;
component RAM512X4_25um
port (WA, RA : in std_logic_vector (8 downto 0);
WD : in std_logic_vector (3 downto 0);
WE, RE, WCLK, RCLK, ASYNCRD : in std_logic;
RD : out std_logic_vector (3 downto 0));
end component;
component RAM1024X2_25um is
port (WA, RA : in std_logic_vector (9 downto 0);
WD : in std_logic_vector (1 downto 0);
WE, RE, WCLK, RCLK, ASYNCRD : in std_logic;
RD : out std_logic_vector (1 downto 0) );
end component;
constant dlen : integer := dbits + 18;
signal di1, q2, gnd : std_logic_vector(dlen downto 0);
signal a1, a2 : std_logic_vector(12 downto 0);
begin
gnd <= (others => '0');
di1(dbits-1 downto 0) <= din; di1(dlen downto dbits) <= (others => '0');
a1(abits-1 downto 0) <= waddr; a1(12 downto abits) <= (others => '0');
a2(abits-1 downto 0) <= raddr; a2(12 downto abits) <= (others => '0');
dout <= q2(dbits-1 downto 0); q2(dlen downto dbits) <= (others => '0');
a7 : if (abits <= 7) generate
x : for i in 0 to (dbits-1)/18 generate
u0 : RAM128X18_25um port map (
a1(6 downto 0), a2(6 downto 0), di1(i*18+17 downto i*18),
write, rena, wclk, rclk, gnd(0), q2(i*18+17 downto i*18));
end generate;
end generate;
a8 : if (abits = 8) generate
x : for i in 0 to (dbits-1)/9 generate
u0 : RAM256X9_25um port map (
a1(7 downto 0), a2(7 downto 0), di1(i*9+8 downto i*9),
write, rena, wclk, rclk, gnd(0), q2(i*9+8 downto i*9));
end generate;
end generate;
a9 : if (abits = 9) generate
x : for i in 0 to (dbits-1)/4 generate
u0 : RAM512X4_25um port map (
a1(8 downto 0), a2(8 downto 0), di1(i*4+3 downto i*4),
write, rena, wclk, rclk, gnd(0), q2(i*4+3 downto i*4));
end generate;
end generate;
a10 : if (abits = 10) generate
x : for i in 0 to (dbits-1)/2 generate
u0 : RAM1024X2_25um port map (
a1(9 downto 0), a2(9 downto 0), di1(i*2+1 downto i*2),
write, rena, wclk, rclk, gnd(0), q2(i*2+1 downto i*2));
end generate;
end generate;
-- pragma translate_off
unsup : if abits > 10 generate
x : process
begin
assert false
report "Address depth larger than 10 is not supported for Eclipse rams"
severity failure;
wait;
end process;
end generate;
-- pragma translate_on
end;
| mit | 8099903d90ef501bcda0813a694fdba7 | 0.605377 | 3.33237 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/greth/greth.vhd | 2 | 11,006 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: greth
-- File: greth.vhd
-- Author: Marko Isomaki
-- Description: Ethernet Media Access Controller with Ethernet Debug
-- Communication Link
------------------------------------------------------------------------------
library ieee;
library grlib;
library gaisler;
use ieee.std_logic_1164.all;
use grlib.stdlib.all;
use grlib.amba.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use gaisler.net.all;
use gaisler.ethernet_mac.all;
use gaisler.misc.all;
library eth;
use eth.ethcomp.all;
entity greth is
generic(
hindex : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#FFF#;
pirq : integer := 0;
memtech : integer := 0;
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
slot_time : integer := 128;
mdcscaler : integer range 0 to 255 := 25;
enable_mdio : integer range 0 to 1 := 0;
fifosize : integer range 4 to 512 := 8;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 2 := 0;
edclbufsz : integer range 1 to 64 := 1;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0035#;
phyrstadr : integer range 0 to 32 := 0;
rmii : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0;
scanen : integer range 0 to 1 := 0;
ft : integer range 0 to 1 := 0);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ethi : in eth_in_type;
etho : out eth_out_type
);
end entity;
architecture rtl of greth is
function getfifosize(edcl, fifosize, ebufsize : in integer) return integer is
begin
if (edcl /= 0) and (ebufsize > fifosize) then
return ebufsize;
else
return fifosize;
end if;
end function;
constant fabits : integer := log2(fifosize);
type szvct is array (0 to 6) of integer;
constant ebuf : szvct := (64, 128, 128, 256, 256, 256, 256);
constant eabits : integer := log2(edclbufsz) + 8;
constant bufsize : std_logic_vector(2 downto 0) :=
conv_std_logic_vector(log2(edclbufsz), 3);
constant ebufsize : integer := ebuf(log2(edclbufsz));
constant txfifosize : integer := getfifosize(edcl, fifosize, ebufsize);
constant txfabits : integer := log2(txfifosize);
constant REVISION : amba_version_type := 0;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_ETHMAC, 0, REVISION, pirq),
1 => apb_iobar(paddr, pmask));
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_ETHMAC, 0, revision, 0),
others => zero32);
signal irq : std_ulogic;
--rx ahb fifo
signal rxrenable : std_ulogic;
signal rxraddress : std_logic_vector(10 downto 0);
signal rxwrite : std_ulogic;
signal rxwdata : std_logic_vector(31 downto 0);
signal rxwaddress : std_logic_vector(10 downto 0);
signal rxrdata : std_logic_vector(31 downto 0);
--tx ahb fifo
signal txrenable : std_ulogic;
signal txraddress : std_logic_vector(10 downto 0);
signal txwrite : std_ulogic;
signal txwdata : std_logic_vector(31 downto 0);
signal txwaddress : std_logic_vector(10 downto 0);
signal txrdata : std_logic_vector(31 downto 0);
--edcl buf
signal erenable : std_ulogic;
signal eraddress : std_logic_vector(15 downto 0);
signal ewritem : std_ulogic;
signal ewritel : std_ulogic;
signal ewaddressm : std_logic_vector(15 downto 0);
signal ewaddressl : std_logic_vector(15 downto 0);
signal ewdata : std_logic_vector(31 downto 0);
signal erdata : std_logic_vector(31 downto 0);
signal lmdio_oe : std_ulogic;
begin
ethc0: grethc
generic map(
ifg_gap => ifg_gap,
attempt_limit => attempt_limit,
backoff_limit => backoff_limit,
mdcscaler => mdcscaler,
enable_mdio => enable_mdio,
fifosize => fifosize,
nsync => nsync,
edcl => edcl,
edclbufsz => edclbufsz,
macaddrh => macaddrh,
macaddrl => macaddrl,
ipaddrh => ipaddrh,
ipaddrl => ipaddrl,
phyrstadr => phyrstadr,
rmii => rmii,
oepol => oepol,
scanen => scanen)
port map(
rst => rst,
clk => clk,
--ahb mst in
hgrant => ahbmi.hgrant(hindex),
hready => ahbmi.hready,
hresp => ahbmi.hresp,
hrdata => ahbmi.hrdata,
--ahb mst out
hbusreq => ahbmo.hbusreq,
hlock => ahbmo.hlock,
htrans => ahbmo.htrans,
haddr => ahbmo.haddr,
hwrite => ahbmo.hwrite,
hsize => ahbmo.hsize,
hburst => ahbmo.hburst,
hprot => ahbmo.hprot,
hwdata => ahbmo.hwdata,
--apb slv in
psel => apbi.psel(pindex),
penable => apbi.penable,
paddr => apbi.paddr,
pwrite => apbi.pwrite,
pwdata => apbi.pwdata,
--apb slv out
prdata => apbo.prdata,
--irq
irq => irq,
--rx ahb fifo
rxrenable => rxrenable,
rxraddress => rxraddress,
rxwrite => rxwrite,
rxwdata => rxwdata,
rxwaddress => rxwaddress,
rxrdata => rxrdata,
--tx ahb fifo
txrenable => txrenable,
txraddress => txraddress,
txwrite => txwrite,
txwdata => txwdata,
txwaddress => txwaddress,
txrdata => txrdata,
--edcl buf
erenable => erenable,
eraddress => eraddress,
ewritem => ewritem,
ewritel => ewritel,
ewaddressm => ewaddressm,
ewaddressl => ewaddressl,
ewdata => ewdata,
erdata => erdata,
--ethernet input signals
rmii_clk => ethi.rmii_clk,
tx_clk => ethi.tx_clk,
rx_clk => ethi.rx_clk,
rxd => ethi.rxd(3 downto 0),
rx_dv => ethi.rx_dv,
rx_er => ethi.rx_er,
rx_col => ethi.rx_col,
rx_crs => ethi.rx_crs,
mdio_i => ethi.mdio_i,
phyrstaddr => ethi.phyrstaddr,
--ethernet output signals
reset => etho.reset,
txd => etho.txd(3 downto 0),
tx_en => etho.tx_en,
tx_er => etho.tx_er,
mdc => etho.mdc,
mdio_o => etho.mdio_o,
mdio_oe => lmdio_oe,
--scantest
testrst => ahbmi.testrst,
testen => ahbmi.testen,
edcladdr => ethi.edcladdr);
etho.mdio_oe <= ahbmi.testoen when (scanen = 1) and (ahbmi.testen = '1')
else lmdio_oe;
irqdrv : process(irq)
begin
apbo.pirq <= (others => '0');
apbo.pirq(pirq) <= irq;
end process;
ahbmo.hconfig <= hconfig;
ahbmo.hindex <= hindex;
ahbmo.hirq <= (others => '0');
apbo.pconfig <= pconfig;
apbo.pindex <= pindex;
-------------------------------------------------------------------------------
-- FIFOS ----------------------------------------------------------------------
-------------------------------------------------------------------------------
nft : if ft = 0 generate
tx_fifo0 : syncram_2p generic map(tech => memtech, abits => txfabits,
dbits => 32, sepclk => 0)
port map(clk, txrenable, txraddress(txfabits-1 downto 0), txrdata, clk,
txwrite, txwaddress(txfabits-1 downto 0), txwdata);
rx_fifo0 : syncram_2p generic map(tech => memtech, abits => fabits,
dbits => 32, sepclk => 0)
port map(clk, rxrenable, rxraddress(fabits-1 downto 0), rxrdata, clk,
rxwrite, rxwaddress(fabits-1 downto 0), rxwdata);
end generate;
ft1 : if ft = 1 generate
tx_fifo0 : syncram_2pft generic map(tech => memtech, abits => txfabits,
dbits => 32, sepclk => 0, ft => 1)
port map(clk, txrenable, txraddress(txfabits-1 downto 0), txrdata, clk,
txwrite, txwaddress(txfabits-1 downto 0), txwdata);
rx_fifo0 : syncram_2pft generic map(tech => memtech, abits => fabits,
dbits => 32, sepclk => 0, ft => 1)
port map(clk, rxrenable, rxraddress(fabits-1 downto 0), rxrdata, clk,
rxwrite, rxwaddress(fabits-1 downto 0), rxwdata);
end generate;
-------------------------------------------------------------------------------
-- EDCL buffer ram ------------------------------------------------------------
-------------------------------------------------------------------------------
edclram : if (edcl /= 0) generate
r0 : syncram_2p generic map (memtech, eabits, 16) port map(
clk, erenable, eraddress(eabits-1 downto 0), erdata(31 downto 16), clk,
ewritem, ewaddressm(eabits-1 downto 0), ewdata(31 downto 16));
r1 : syncram_2p generic map (memtech, eabits, 16) port map(
clk, erenable, eraddress(eabits-1 downto 0), erdata(15 downto 0), clk,
ewritel, ewaddressl(eabits-1 downto 0), ewdata(15 downto 0));
end generate;
-- pragma translate_off
bootmsg : report_version
generic map (
"greth" & tost(hindex) & ": 10/100 Mbit Ethernet MAC rev " & tost(REVISION)
& tost(hindex) & ", EDCL " & tost(edcl) & ", buffer " &
tost(edclbufsz) & " kbyte " & tost(txfifosize) & " txfifo," &
" irq " & tost(pirq)
);
-- pragma translate_on
end architecture;
| mit | c1d3ba02fa1ef4395382990a0ebf4f04 | 0.532982 | 4.137594 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/opencores/can/can_top.vhd | 2 | 356,774 | ----------------------------------------------------------------------------------------------
--
-- VHDL file generated by X-HDL - Revision 3.2.53 Aug. 1, 2005
-- Tue Aug 9 07:33:50 2005
--
-- Input file : C:/Documents and Settings/BryantI/My Documents/tmp/can_top.v
-- Design name : can_acf
-- Author :
-- Company : Actel
--
-- Description :
--
--
----------------------------------------------------------------------------------------------
--
--////////////////////////////////////////////////////////////////////
--// ////
--// can_acf.v ////
--// ////
--// ////
--// This file is part of the CAN Protocol Controller ////
--// http://www.opencores.org/projects/can/ ////
--// ////
--// ////
--// Author(s): ////
--// Igor Mohor ////
--// [email protected] ////
--// ////
--// ////
--// All additional information is available in the README.txt ////
--// file. ////
--// ////
--////////////////////////////////////////////////////////////////////
--// ////
--// Copyright (C) 2002, 2003, 2004 Authors ////
--// ////
--// This source file may be used and distributed without ////
--// restriction provided that this copyright statement is not ////
--// removed from the file and that any derivative work contains ////
--// the original copyright notice and the associated disclaimer. ////
--// ////
--// This source file is free software; you can redistribute it ////
--// and/or modify it under the terms of the GNU Lesser General ////
--// Public License as published by the Free Software Foundation; ////
--// either version 2.1 of the License, or (at your option) any ////
--// later version. ////
--// ////
--// This source is distributed in the hope that it will be ////
--// useful, but WITHOUT ANY WARRANTY; without even the implied ////
--// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
--// PURPOSE. See the GNU Lesser General Public License for more ////
--// details. ////
--// ////
--// You should have received a copy of the GNU Lesser General ////
--// Public License along with this source; if not, download it ////
--// from http://www.opencores.org/lgpl.shtml ////
--// ////
--// The CAN protocol is developed by Robert Bosch GmbH and ////
--// protected by patents. Anybody who wants to implement this ////
--// CAN IP core on silicon has to obtain a CAN protocol license ////
--// from Bosch. ////
--// ////
--////////////////////////////////////////////////////////////////////
--
-- CVS Revision History
--
-- $Log: can_acf.v,v $
-- Revision 1.10 2005/04/08 13:03:07 igorm
-- In "Extended mode" when dual filter was used and standard frame received,
-- upper nibble of the data was not filtered ok.
--
-- Revision 1.9 2004/05/31 14:46:11 igorm
-- Bit acceptance_filter_mode was inverted.
--
-- Revision 1.8 2004/02/08 14:16:44 mohor
-- Header changed.
--
-- Revision 1.7 2003/07/16 13:41:34 mohor
-- Fixed according to the linter.
--
-- Revision 1.6 2003/02/10 16:02:11 mohor
-- CAN is working according to the specification. WB interface and more
-- registers (status, IRQ, ...) needs to be added.
--
-- Revision 1.5 2003/02/09 18:40:29 mohor
-- Overload fixed. Hard synchronization also enabled at the last bit of
-- interframe.
--
-- Revision 1.4 2003/02/09 02:24:33 mohor
-- Bosch license warning added. Error counters finished. Overload frames
-- still need to be fixed.
--
-- Revision 1.3 2003/01/31 01:13:37 mohor
-- backup.
--
-- Revision 1.2 2003/01/14 12:19:35 mohor
-- rx_fifo is now working.
--
-- Revision 1.1 2003/01/08 02:13:15 mohor
-- Acceptance filter added.
--
--
--
--
-- synopsys translate_off
--`include "can_defines.v"
-- synopsys translate_on
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
ENTITY can_acf IS
PORT (
clk : IN std_logic;
rst : IN std_logic;
id : IN std_logic_vector(28 DOWNTO 0);
reset_mode : IN std_logic;
acceptance_filter_mode : IN std_logic;
extended_mode : IN std_logic;
acceptance_code_0 : IN std_logic_vector(7 DOWNTO 0);
acceptance_code_1 : IN std_logic_vector(7 DOWNTO 0);
acceptance_code_2 : IN std_logic_vector(7 DOWNTO 0);
acceptance_code_3 : IN std_logic_vector(7 DOWNTO 0);
acceptance_mask_0 : IN std_logic_vector(7 DOWNTO 0);
acceptance_mask_1 : IN std_logic_vector(7 DOWNTO 0);
acceptance_mask_2 : IN std_logic_vector(7 DOWNTO 0);
acceptance_mask_3 : IN std_logic_vector(7 DOWNTO 0);
go_rx_crc_lim : IN std_logic;
go_rx_inter : IN std_logic;
go_error_frame : IN std_logic;
data0 : IN std_logic_vector(7 DOWNTO 0);
data1 : IN std_logic_vector(7 DOWNTO 0);
rtr1 : IN std_logic;
rtr2 : IN std_logic;
ide : IN std_logic;
no_byte0 : IN std_logic;
no_byte1 : IN std_logic;
id_ok : OUT std_logic);
END ENTITY can_acf;
ARCHITECTURE RTL OF can_acf IS
SIGNAL match : std_logic;
SIGNAL match_sf_std : std_logic;
SIGNAL match_sf_ext : std_logic;
SIGNAL match_df_std : std_logic;
SIGNAL match_df_ext : std_logic;
SIGNAL id_ok_xhdl1 : std_logic;
BEGIN
id_ok <= id_ok_xhdl1;
-- Working in basic mode. ID match for standard format (11-bit ID).
match <= (((((((CONV_STD_LOGIC(id(3) = acceptance_code_0(0)) OR acceptance_mask_0(0)) AND (CONV_STD_LOGIC(id(4) = acceptance_code_0(1)) OR acceptance_mask_0(1))) AND (CONV_STD_LOGIC(id(5) = acceptance_code_0(2)) OR acceptance_mask_0(2))) AND (CONV_STD_LOGIC(id(6) = acceptance_code_0(3)) OR acceptance_mask_0(3))) AND (CONV_STD_LOGIC(id(7) = acceptance_code_0(4)) OR acceptance_mask_0(4))) AND (CONV_STD_LOGIC(id(8) = acceptance_code_0(5)) OR acceptance_mask_0(5))) AND (CONV_STD_LOGIC(id(9) = acceptance_code_0(6)) OR acceptance_mask_0(6))) AND (CONV_STD_LOGIC(id(10) = acceptance_code_0(7)) OR acceptance_mask_0(7)) ;
-- Working in extended mode. ID match for standard format (11-bit ID). Using single filter.
match_sf_std <= (((((((((((((((((((((((((((CONV_STD_LOGIC(id(3) = acceptance_code_0(0)) OR acceptance_mask_0(0)) AND (CONV_STD_LOGIC(id(4) = acceptance_code_0(1))
OR acceptance_mask_0(1))) AND (CONV_STD_LOGIC(id(5) = acceptance_code_0(2)) OR acceptance_mask_0(2))) AND (CONV_STD_LOGIC(id(6) = acceptance_code_0(3))
OR acceptance_mask_0(3))) AND (CONV_STD_LOGIC(id(7) = acceptance_code_0(4)) OR acceptance_mask_0(4))) AND (CONV_STD_LOGIC(id(8) = acceptance_code_0(5))
OR acceptance_mask_0(5))) AND (CONV_STD_LOGIC(id(9) = acceptance_code_0(6)) OR acceptance_mask_0(6))) AND (CONV_STD_LOGIC(id(10) = acceptance_code_0(7))
OR acceptance_mask_0(7))) AND (CONV_STD_LOGIC(rtr1 = acceptance_code_1(4)) OR acceptance_mask_1(4))) AND (CONV_STD_LOGIC(id(0) = acceptance_code_1(5))
OR acceptance_mask_1(5))) AND (CONV_STD_LOGIC(id(1) = acceptance_code_1(6)) OR acceptance_mask_1(6))) AND (CONV_STD_LOGIC(id(2) = acceptance_code_1(7))
OR acceptance_mask_1(7))) AND (CONV_STD_LOGIC(data0(0) = acceptance_code_2(0)) OR acceptance_mask_2(0) OR no_byte0)) AND (CONV_STD_LOGIC(data0(1) = acceptance_code_2(1))
OR acceptance_mask_2(1) OR no_byte0)) AND (CONV_STD_LOGIC(data0(2) = acceptance_code_2(2)) OR acceptance_mask_2(2)
OR no_byte0)) AND (CONV_STD_LOGIC(data0(3) = acceptance_code_2(3)) OR acceptance_mask_2(3) OR no_byte0)) AND (CONV_STD_LOGIC(data0(4) = acceptance_code_2(4))
OR acceptance_mask_2(4) OR no_byte0)) AND (CONV_STD_LOGIC(data0(5) = acceptance_code_2(5)) OR acceptance_mask_2(5) OR no_byte0)) AND (CONV_STD_LOGIC(data0(6) = acceptance_code_2(6))
OR acceptance_mask_2(6) OR no_byte0)) AND (CONV_STD_LOGIC(data0(7) = acceptance_code_2(7)) OR acceptance_mask_2(7) OR no_byte0)) AND (CONV_STD_LOGIC(data1(0) = acceptance_code_3(0))
OR acceptance_mask_3(0) OR no_byte1)) AND (CONV_STD_LOGIC(data1(1) = acceptance_code_3(1)) OR acceptance_mask_3(1) OR no_byte1)) AND (CONV_STD_LOGIC(data1(2) = acceptance_code_3(2))
OR acceptance_mask_3(2) OR no_byte1)) AND (CONV_STD_LOGIC(data1(3) = acceptance_code_3(3)) OR acceptance_mask_3(3) OR no_byte1)) AND (CONV_STD_LOGIC(data1(4) = acceptance_code_3(4))
OR acceptance_mask_3(4) OR no_byte1)) AND (CONV_STD_LOGIC(data1(5) = acceptance_code_3(5)) OR acceptance_mask_3(5) OR no_byte1)) AND (CONV_STD_LOGIC(data1(6) = acceptance_code_3(6))
OR acceptance_mask_3(6) OR no_byte1)) AND (CONV_STD_LOGIC(data1(7) = acceptance_code_3(7)) OR acceptance_mask_3(7) OR no_byte1) ;
-- Working in extended mode. ID match for extended format (29-bit ID). Using single filter.
match_sf_ext <= (((((((((((((((((((((((((((((CONV_STD_LOGIC(id(21) = acceptance_code_0(0)) OR acceptance_mask_0(0)) AND (CONV_STD_LOGIC(id(22) = acceptance_code_0(1))
OR acceptance_mask_0(1))) AND (CONV_STD_LOGIC(id(23) = acceptance_code_0(2)) OR acceptance_mask_0(2))) AND (CONV_STD_LOGIC(id(24) = acceptance_code_0(3))
OR acceptance_mask_0(3))) AND (CONV_STD_LOGIC(id(25) = acceptance_code_0(4)) OR acceptance_mask_0(4))) AND (CONV_STD_LOGIC(id(26) = acceptance_code_0(5))
OR acceptance_mask_0(5))) AND (CONV_STD_LOGIC(id(27) = acceptance_code_0(6)) OR acceptance_mask_0(6))) AND (CONV_STD_LOGIC(id(28) = acceptance_code_0(7))
OR acceptance_mask_0(7))) AND (CONV_STD_LOGIC(id(13) = acceptance_code_1(0)) OR acceptance_mask_1(0))) AND (CONV_STD_LOGIC(id(14) = acceptance_code_1(1))
OR acceptance_mask_1(1))) AND (CONV_STD_LOGIC(id(15) = acceptance_code_1(2)) OR acceptance_mask_1(2))) AND (CONV_STD_LOGIC(id(16) = acceptance_code_1(3))
OR acceptance_mask_1(3))) AND (CONV_STD_LOGIC(id(17) = acceptance_code_1(4)) OR acceptance_mask_1(4))) AND (CONV_STD_LOGIC(id(18) = acceptance_code_1(5))
OR acceptance_mask_1(5))) AND (CONV_STD_LOGIC(id(19) = acceptance_code_1(6)) OR acceptance_mask_1(6))) AND (CONV_STD_LOGIC(id(20) = acceptance_code_1(7))
OR acceptance_mask_1(7))) AND (CONV_STD_LOGIC(id(5) = acceptance_code_2(0)) OR acceptance_mask_2(0))) AND (CONV_STD_LOGIC(id(6) = acceptance_code_2(1))
OR acceptance_mask_2(1))) AND (CONV_STD_LOGIC(id(7) = acceptance_code_2(2)) OR acceptance_mask_2(2))) AND (CONV_STD_LOGIC(id(8) = acceptance_code_2(3))
OR acceptance_mask_2(3))) AND (CONV_STD_LOGIC(id(9) = acceptance_code_2(4)) OR acceptance_mask_2(4))) AND (CONV_STD_LOGIC(id(10) = acceptance_code_2(5))
OR acceptance_mask_2(5))) AND (CONV_STD_LOGIC(id(11) = acceptance_code_2(6)) OR acceptance_mask_2(6))) AND (CONV_STD_LOGIC(id(12) = acceptance_code_2(7))
OR acceptance_mask_2(7))) AND (CONV_STD_LOGIC(rtr2 = acceptance_code_3(2)) OR acceptance_mask_3(2))) AND (CONV_STD_LOGIC(id(0) = acceptance_code_3(3))
OR acceptance_mask_3(3))) AND (CONV_STD_LOGIC(id(1) = acceptance_code_3(4)) OR acceptance_mask_3(4))) AND (CONV_STD_LOGIC(id(2) = acceptance_code_3(5))
OR acceptance_mask_3(5))) AND (CONV_STD_LOGIC(id(3) = acceptance_code_3(6)) OR acceptance_mask_3(6))) AND (CONV_STD_LOGIC(id(4) = acceptance_code_3(7))
OR acceptance_mask_3(7)) ;
-- Working in extended mode. ID match for standard format (11-bit ID). Using double filter.
match_df_std <= ((((((((((((((((((((CONV_STD_LOGIC(id(3) = acceptance_code_0(0)) OR acceptance_mask_0(0)) AND (CONV_STD_LOGIC(id(4) = acceptance_code_0(1))
OR acceptance_mask_0(1))) AND (CONV_STD_LOGIC(id(5) = acceptance_code_0(2)) OR acceptance_mask_0(2))) AND (CONV_STD_LOGIC(id(6) = acceptance_code_0(3))
OR acceptance_mask_0(3))) AND (CONV_STD_LOGIC(id(7) = acceptance_code_0(4)) OR acceptance_mask_0(4))) AND (CONV_STD_LOGIC(id(8) = acceptance_code_0(5))
OR acceptance_mask_0(5))) AND (CONV_STD_LOGIC(id(9) = acceptance_code_0(6)) OR acceptance_mask_0(6))) AND (CONV_STD_LOGIC(id(10) = acceptance_code_0(7))
OR acceptance_mask_0(7))) AND (CONV_STD_LOGIC(rtr1 = acceptance_code_1(4)) OR acceptance_mask_1(4))) AND (CONV_STD_LOGIC(id(0) = acceptance_code_1(5))
OR acceptance_mask_1(5))) AND (CONV_STD_LOGIC(id(1) = acceptance_code_1(6)) OR acceptance_mask_1(6))) AND (CONV_STD_LOGIC(id(2) = acceptance_code_1(7))
OR acceptance_mask_1(7))) AND (CONV_STD_LOGIC(data0(0) = acceptance_code_3(0)) OR acceptance_mask_3(0)
OR no_byte0)) AND (CONV_STD_LOGIC(data0(1) = acceptance_code_3(1)) OR acceptance_mask_3(1) OR no_byte0)) AND (CONV_STD_LOGIC(data0(2) = acceptance_code_3(2))
OR acceptance_mask_3(2) OR no_byte0)) AND (CONV_STD_LOGIC(data0(3) = acceptance_code_3(3)) OR acceptance_mask_3(3)
OR no_byte0)) AND (CONV_STD_LOGIC(data0(4) = acceptance_code_1(0)) OR acceptance_mask_1(0) OR no_byte0)) AND (CONV_STD_LOGIC(data0(5) = acceptance_code_1(1))
OR acceptance_mask_1(1) OR no_byte0)) AND (CONV_STD_LOGIC(data0(6) = acceptance_code_1(2))
OR acceptance_mask_1(2) OR no_byte0)) AND (CONV_STD_LOGIC(data0(7) = acceptance_code_1(3)) OR acceptance_mask_1(3) OR no_byte0))
OR ((((((((((((CONV_STD_LOGIC(id(3) = acceptance_code_2(0)) OR acceptance_mask_2(0)) AND (CONV_STD_LOGIC(id(4) = acceptance_code_2(1))
OR acceptance_mask_2(1))) AND (CONV_STD_LOGIC(id(5) = acceptance_code_2(2)) OR acceptance_mask_2(2))) AND (CONV_STD_LOGIC(id(6) = acceptance_code_2(3))
OR acceptance_mask_2(3))) AND (CONV_STD_LOGIC(id(7) = acceptance_code_2(4)) OR acceptance_mask_2(4))) AND (CONV_STD_LOGIC(id(8) = acceptance_code_2(5))
OR acceptance_mask_2(5))) AND (CONV_STD_LOGIC(id(9) = acceptance_code_2(6)) OR acceptance_mask_2(6))) AND (CONV_STD_LOGIC(id(10) = acceptance_code_2(7))
OR acceptance_mask_2(7))) AND (CONV_STD_LOGIC(rtr1 = acceptance_code_3(4)) OR acceptance_mask_3(4))) AND (CONV_STD_LOGIC(id(0) = acceptance_code_3(5))
OR acceptance_mask_3(5))) AND (CONV_STD_LOGIC(id(1) = acceptance_code_3(6)) OR acceptance_mask_3(6))) AND (CONV_STD_LOGIC(id(2) = acceptance_code_3(7))
OR acceptance_mask_3(7))) ;
-- Working in extended mode. ID match for extended format (29-bit ID). Using double filter.
match_df_ext <= ((((((((((((((((CONV_STD_LOGIC(id(21) = acceptance_code_0(0)) OR acceptance_mask_0(0)) AND (CONV_STD_LOGIC(id(22) = acceptance_code_0(1))
OR acceptance_mask_0(1))) AND (CONV_STD_LOGIC(id(23) = acceptance_code_0(2)) OR acceptance_mask_0(2))) AND (CONV_STD_LOGIC(id(24) = acceptance_code_0(3))
OR acceptance_mask_0(3))) AND (CONV_STD_LOGIC(id(25) = acceptance_code_0(4)) OR acceptance_mask_0(4))) AND (CONV_STD_LOGIC(id(26) = acceptance_code_0(5))
OR acceptance_mask_0(5))) AND (CONV_STD_LOGIC(id(27) = acceptance_code_0(6)) OR acceptance_mask_0(6))) AND (CONV_STD_LOGIC(id(28) = acceptance_code_0(7))
OR acceptance_mask_0(7))) AND (CONV_STD_LOGIC(id(13) = acceptance_code_1(0)) OR acceptance_mask_1(0))) AND (CONV_STD_LOGIC(id(14) = acceptance_code_1(1))
OR acceptance_mask_1(1))) AND (CONV_STD_LOGIC(id(15) = acceptance_code_1(2)) OR acceptance_mask_1(2))) AND (CONV_STD_LOGIC(id(16) = acceptance_code_1(3))
OR acceptance_mask_1(3))) AND (CONV_STD_LOGIC(id(17) = acceptance_code_1(4)) OR acceptance_mask_1(4))) AND (CONV_STD_LOGIC(id(18) = acceptance_code_1(5))
OR acceptance_mask_1(5))) AND (CONV_STD_LOGIC(id(19) = acceptance_code_1(6)) OR acceptance_mask_1(6))) AND (CONV_STD_LOGIC(id(20) = acceptance_code_1(7))
OR acceptance_mask_1(7))) OR ((((((((((((((((CONV_STD_LOGIC(id(21) = acceptance_code_2(0)) OR acceptance_mask_2(0)) AND (CONV_STD_LOGIC(id(22) = acceptance_code_2(1))
OR acceptance_mask_2(1))) AND (CONV_STD_LOGIC(id(23) = acceptance_code_2(2)) OR acceptance_mask_2(2))) AND (CONV_STD_LOGIC(id(24) = acceptance_code_2(3))
OR acceptance_mask_2(3))) AND (CONV_STD_LOGIC(id(25) = acceptance_code_2(4)) OR acceptance_mask_2(4))) AND (CONV_STD_LOGIC(id(26) = acceptance_code_2(5))
OR acceptance_mask_2(5))) AND (CONV_STD_LOGIC(id(27) = acceptance_code_2(6)) OR acceptance_mask_2(6))) AND (CONV_STD_LOGIC(id(28) = acceptance_code_2(7))
OR acceptance_mask_2(7))) AND (CONV_STD_LOGIC(id(13) = acceptance_code_3(0)) OR acceptance_mask_3(0))) AND (CONV_STD_LOGIC(id(14) = acceptance_code_3(1))
OR acceptance_mask_3(1))) AND (CONV_STD_LOGIC(id(15) = acceptance_code_3(2)) OR acceptance_mask_3(2))) AND (CONV_STD_LOGIC(id(16) = acceptance_code_3(3))
OR acceptance_mask_3(3))) AND (CONV_STD_LOGIC(id(17) = acceptance_code_3(4)) OR acceptance_mask_3(4))) AND (CONV_STD_LOGIC(id(18) = acceptance_code_3(5))
OR acceptance_mask_3(5))) AND (CONV_STD_LOGIC(id(19) = acceptance_code_3(6)) OR acceptance_mask_3(6))) AND (CONV_STD_LOGIC(id(20) = acceptance_code_3(7))
OR acceptance_mask_3(7))) ;
-- ID ok signal generation
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
id_ok_xhdl1 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (go_rx_crc_lim = '1') THEN
-- sample_point is already included in go_rx_crc_lim
IF (extended_mode = '1') THEN
IF (NOT acceptance_filter_mode = '1') THEN
-- dual filter
IF (ide = '1') THEN
-- extended frame message
id_ok_xhdl1 <= match_df_ext ;
ELSE
-- standard frame message
id_ok_xhdl1 <= match_df_std ;
END IF;
ELSE
-- single filter
IF (ide = '1') THEN
-- extended frame message
id_ok_xhdl1 <= match_sf_ext ;
ELSE
-- standard frame message
id_ok_xhdl1 <= match_sf_std ;
END IF;
END IF;
ELSE
id_ok_xhdl1 <= match ;
END IF;
ELSE
IF ((reset_mode OR go_rx_inter OR go_error_frame) = '1') THEN
-- sample_point is already included in go_rx_inter
id_ok_xhdl1 <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE RTL;
----------------------------------------------------------------------------------------------
--
-- VHDL file generated by X-HDL - Revision 3.2.53 Aug. 1, 2005
-- Tue Aug 9 07:33:51 2005
--
-- Input file : C:/Documents and Settings/BryantI/My Documents/tmp/can_top.v
-- Design name : can_btl
-- Author :
-- Company : Actel
--
-- Description :
--
--
----------------------------------------------------------------------------------------------
--
--////////////////////////////////////////////////////////////////////
--// ////
--// can_btl.v ////
--// ////
--// ////
--// This file is part of the CAN Protocol Controller ////
--// http://www.opencores.org/projects/can/ ////
--// ////
--// ////
--// Author(s): ////
--// Igor Mohor ////
--// [email protected] ////
--// ////
--// ////
--// All additional information is available in the README.txt ////
--// file. ////
--// ////
--////////////////////////////////////////////////////////////////////
--// ////
--// Copyright (C) 2002, 2003, 2004 Authors ////
--// ////
--// This source file may be used and distributed without ////
--// restriction provided that this copyright statement is not ////
--// removed from the file and that any derivative work contains ////
--// the original copyright notice and the associated disclaimer. ////
--// ////
--// This source file is free software; you can redistribute it ////
--// and/or modify it under the terms of the GNU Lesser General ////
--// Public License as published by the Free Software Foundation; ////
--// either version 2.1 of the License, or (at your option) any ////
--// later version. ////
--// ////
--// This source is distributed in the hope that it will be ////
--// useful, but WITHOUT ANY WARRANTY; without even the implied ////
--// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
--// PURPOSE. See the GNU Lesser General Public License for more ////
--// details. ////
--// ////
--// You should have received a copy of the GNU Lesser General ////
--// Public License along with this source; if not, download it ////
--// from http://www.opencores.org/lgpl.shtml ////
--// ////
--// The CAN protocol is developed by Robert Bosch GmbH and ////
--// protected by patents. Anybody who wants to implement this ////
--// CAN IP core on silicon has to obtain a CAN protocol license ////
--// from Bosch. ////
--// ////
--////////////////////////////////////////////////////////////////////
--
-- CVS Revision History
--
-- $Log: can_btl.v,v $
-- Revision 1.30 2004/10/27 18:51:37 igorm
-- Fixed synchronization problem in real hardware when 0xf is used for TSEG1.
--
-- Revision 1.29 2004/05/12 15:58:41 igorm
-- Core improved to pass all tests with the Bosch VHDL Reference system.
--
-- Revision 1.28 2004/02/08 14:25:26 mohor
-- Header changed.
--
-- Revision 1.27 2003/09/30 00:55:13 mohor
-- Error counters fixed to be compatible with Bosch VHDL reference model.
-- Small synchronization changes.
--
-- Revision 1.26 2003/09/25 18:55:49 mohor
-- Synchronization changed, error counters fixed.
--
-- Revision 1.25 2003/07/16 13:40:35 mohor
-- Fixed according to the linter.
--
-- Revision 1.24 2003/07/10 15:32:28 mohor
-- Unused signal removed.
--
-- Revision 1.23 2003/07/10 01:59:04 tadejm
-- Synchronization fixed. In some strange cases it didn't work according to
-- the VHDL reference model.
--
-- Revision 1.22 2003/07/07 11:21:37 mohor
-- Little fixes (to fix warnings).
--
-- Revision 1.21 2003/07/03 09:32:20 mohor
-- Synchronization changed.
--
-- Revision 1.20 2003/06/20 14:51:11 mohor
-- Previous change removed. When resynchronization occurs we go to seg1
-- stage. sync stage does not cause another start of seg1 stage.
--
-- Revision 1.19 2003/06/20 14:28:20 mohor
-- When hard_sync or resync occure we need to go to seg1 segment. Going to
-- sync segment is in that case blocked.
--
-- Revision 1.18 2003/06/17 15:53:33 mohor
-- clk_cnt reduced from [8:0] to [6:0].
--
-- Revision 1.17 2003/06/17 14:32:17 mohor
-- Removed few signals.
--
-- Revision 1.16 2003/06/16 13:57:58 mohor
-- tx_point generated one clk earlier. rx_i registered. Data corrected when
-- using extended mode.
--
-- Revision 1.15 2003/06/13 15:02:24 mohor
-- Synchronization is also needed when transmitting a message.
--
-- Revision 1.14 2003/06/13 14:55:11 mohor
-- Counters width changed.
--
-- Revision 1.13 2003/06/11 14:21:35 mohor
-- When switching to tx, sync stage is overjumped.
--
-- Revision 1.12 2003/02/14 20:17:01 mohor
-- Several registers added. Not finished, yet.
--
-- Revision 1.11 2003/02/09 18:40:29 mohor
-- Overload fixed. Hard synchronization also enabled at the last bit of
-- interframe.
--
-- Revision 1.10 2003/02/09 02:24:33 mohor
-- Bosch license warning added. Error counters finished. Overload frames
-- still need to be fixed.
--
-- Revision 1.9 2003/01/31 01:13:38 mohor
-- backup.
--
-- Revision 1.8 2003/01/10 17:51:34 mohor
-- Temporary version (backup).
--
-- Revision 1.7 2003/01/08 02:10:53 mohor
-- Acceptance filter added.
--
-- Revision 1.6 2002/12/28 04:13:23 mohor
-- Backup version.
--
-- Revision 1.5 2002/12/27 00:12:52 mohor
-- Header changed, testbench improved to send a frame (crc still missing).
--
-- Revision 1.4 2002/12/26 01:33:05 mohor
-- Tripple sampling supported.
--
-- Revision 1.3 2002/12/25 23:44:16 mohor
-- Commented lines removed.
--
-- Revision 1.2 2002/12/25 14:17:00 mohor
-- Synchronization working.
--
-- Revision 1.1.1.1 2002/12/20 16:39:21 mohor
-- Initial
--
--
--
-- synopsys translate_off
--`include "can_defines.v"
-- synopsys translate_on
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
ENTITY can_btl IS
PORT (
clk : IN std_logic;
rst : IN std_logic;
rx : IN std_logic;
tx : IN std_logic;
-- Bus Timing 0 register
baud_r_presc : IN std_logic_vector(5 DOWNTO 0);
sync_jump_width : IN std_logic_vector(1 DOWNTO 0);
-- Bus Timing 1 register
time_segment1 : IN std_logic_vector(3 DOWNTO 0);
time_segment2 : IN std_logic_vector(2 DOWNTO 0);
triple_sampling : IN std_logic;
-- Output signals from this module
sample_point : OUT std_logic;
sampled_bit : OUT std_logic;
sampled_bit_q : OUT std_logic;
tx_point : OUT std_logic;
hard_sync : OUT std_logic;
-- Output from can_bsp module
rx_idle : IN std_logic;
rx_inter : IN std_logic;
transmitting : IN std_logic;
transmitter : IN std_logic;
go_rx_inter : IN std_logic;
tx_next : IN std_logic;
go_overload_frame : IN std_logic;
go_error_frame : IN std_logic;
go_tx : IN std_logic;
send_ack : IN std_logic;
node_error_passive : IN std_logic);
END ENTITY can_btl;
ARCHITECTURE RTL OF can_btl IS
TYPE xhdl_46 IS ARRAY (0 TO 7) OF std_logic_vector(7 DOWNTO 0);
SIGNAL clk_cnt : std_logic_vector(6 DOWNTO 0);
SIGNAL clk_en : std_logic;
SIGNAL clk_en_q : std_logic;
SIGNAL sync_blocked : std_logic;
SIGNAL hard_sync_blocked : std_logic;
SIGNAL quant_cnt : std_logic_vector(4 DOWNTO 0);
SIGNAL delay : std_logic_vector(3 DOWNTO 0);
SIGNAL sync : std_logic;
SIGNAL seg1 : std_logic;
SIGNAL seg2 : std_logic;
SIGNAL resync_latched : std_logic;
SIGNAL sample : std_logic_vector(1 DOWNTO 0);
SIGNAL tx_next_sp : std_logic;
SIGNAL go_sync : std_logic;
SIGNAL go_seg1 : std_logic;
SIGNAL go_seg2 : std_logic;
SIGNAL preset_cnt : std_logic_vector(7 DOWNTO 0);
SIGNAL sync_window : std_logic;
SIGNAL resync : std_logic;
-- when transmitting 0 with positive error delay is set to 0
SIGNAL temp_xhdl6 : std_logic_vector(4 DOWNTO 0);
SIGNAL sample_point_xhdl1 : std_logic;
SIGNAL sampled_bit_xhdl2 : std_logic;
SIGNAL sampled_bit_q_xhdl3 : std_logic;
SIGNAL tx_point_xhdl4 : std_logic;
SIGNAL hard_sync_xhdl5 : std_logic;
BEGIN
sample_point <= sample_point_xhdl1;
sampled_bit <= sampled_bit_xhdl2;
sampled_bit_q <= sampled_bit_q_xhdl3;
tx_point <= tx_point_xhdl4;
hard_sync <= hard_sync_xhdl5;
preset_cnt <= (('0' & baud_r_presc) + 1) & "0" ;
hard_sync_xhdl5 <= (((rx_idle OR rx_inter) AND (NOT rx)) AND sampled_bit_xhdl2) AND (NOT hard_sync_blocked) ;
resync <= ((((NOT rx_idle) AND (NOT rx_inter)) AND (NOT rx)) AND sampled_bit_xhdl2) AND (NOT sync_blocked) ;
-- Generating general enable signal that defines baud rate.
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
clk_cnt <= "0000000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (('0' & clk_cnt) >= (preset_cnt - "00000001")) THEN
clk_cnt <= "0000000" ;
ELSE
clk_cnt <= clk_cnt + "0000001" ;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
clk_en <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (('0' & clk_cnt) = (preset_cnt - "00000001")) THEN
clk_en <= '1' ;
ELSE
clk_en <= '0' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
clk_en_q <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
clk_en_q <= clk_en ;
END IF;
END PROCESS;
-- Changing states
go_sync <= (((clk_en_q AND seg2) AND CONV_STD_LOGIC(quant_cnt(2 DOWNTO 0) = time_segment2)) AND (NOT hard_sync_xhdl5)) AND (NOT resync) ;
go_seg1 <= clk_en_q AND (sync OR hard_sync_xhdl5 OR ((resync AND seg2) AND sync_window) OR (resync_latched AND sync_window)) ;
go_seg2 <= clk_en_q AND ((seg1 AND (NOT hard_sync_xhdl5)) AND CONV_STD_LOGIC(quant_cnt = ( '0' & (time_segment1 + delay)))) ;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
tx_point_xhdl4 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
tx_point_xhdl4 <= (NOT tx_point_xhdl4 AND seg2) AND ((clk_en AND CONV_STD_LOGIC(quant_cnt(2 DOWNTO 0) = time_segment2)) OR ((clk_en OR clk_en_q) AND (resync OR hard_sync_xhdl5))) ; -- When transmitter we should transmit as soon as possible.
END IF;
END PROCESS;
-- When early edge is detected outside of the SJW field, synchronization request is latched and performed when
-- When early edge is detected outside of the SJW field, synchronization request is latched and performed when
-- SJW is reached
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
resync_latched <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (((resync AND seg2) AND (NOT sync_window)) = '1') THEN
resync_latched <= '1' ;
ELSE
IF (go_seg1 = '1') THEN
resync_latched <= '0';
END IF;
END IF;
END IF;
END PROCESS;
-- Synchronization stage/segment
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
sync <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (clk_en_q = '1') THEN
sync <= go_sync ;
END IF;
END IF;
END PROCESS;
-- Seg1 stage/segment (together with propagation segment which is 1 quant long)
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
seg1 <= '1';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (go_seg1 = '1') THEN
seg1 <= '1' ;
ELSE
IF (go_seg2 = '1') THEN
seg1 <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Seg2 stage/segment
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
seg2 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (go_seg2 = '1') THEN
seg2 <= '1' ;
ELSE
IF ((go_sync OR go_seg1) = '1') THEN
seg2 <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Quant counter
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
quant_cnt <= "00000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((go_sync OR go_seg1 OR go_seg2) = '1') THEN
quant_cnt <= "00000" ;
ELSE
IF (clk_en_q = '1') THEN
quant_cnt <= quant_cnt + "00001" ;
END IF;
END IF;
END IF;
END PROCESS;
temp_xhdl6 <= ("0" & ("00" & sync_jump_width + "0001")) WHEN (quant_cnt > "000" & sync_jump_width) ELSE (quant_cnt + "00001");
-- When late edge is detected (in seg1 stage), stage seg1 is prolonged.
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
delay <= "0000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (((resync AND seg1) AND (NOT transmitting OR (transmitting AND (tx_next_sp OR (tx AND (NOT rx)))))) = '1') THEN
delay <= temp_xhdl6(3 DOWNTO 0) ;
ELSE
IF ((go_sync OR go_seg1) = '1') THEN
delay <= "0000" ;
END IF;
END IF;
END IF;
END PROCESS;
-- If early edge appears within this window (in seg2 stage), phase error is fully compensated
sync_window <= CONV_STD_LOGIC((time_segment2 - quant_cnt(2 DOWNTO 0)) < ('0' & (sync_jump_width + "01"))) ;
-- Sampling data (memorizing two samples all the time).
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
sample <= "11";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (clk_en_q = '1') THEN
sample <= sample(0) & rx;
END IF;
END IF;
END PROCESS;
-- When enabled, tripple sampling is done here.
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
sampled_bit_xhdl2 <= '1';
sampled_bit_q_xhdl3 <= '1';
sample_point_xhdl1 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (go_error_frame = '1') THEN
sampled_bit_q_xhdl3 <= sampled_bit_xhdl2 ;
sample_point_xhdl1 <= '0' ;
ELSE
IF ((clk_en_q AND (NOT hard_sync_xhdl5)) = '1') THEN
IF ((seg1 AND CONV_STD_LOGIC(quant_cnt = ('0' & (time_segment1 + delay)))) = '1') THEN
sample_point_xhdl1 <= '1' ;
sampled_bit_q_xhdl3 <= sampled_bit_xhdl2 ;
IF (triple_sampling = '1') THEN
sampled_bit_xhdl2 <= (sample(0) AND sample(1)) OR (sample(0) AND rx) OR (sample(1) AND rx) ;
ELSE
sampled_bit_xhdl2 <= rx ;
END IF;
END IF;
ELSE
sample_point_xhdl1 <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
-- tx_next_sp shows next value that will be driven on the TX. When driving 1 and receiving 0 we
-- need to synchronize (even when we are a transmitter)
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
tx_next_sp <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((go_overload_frame OR (go_error_frame AND (NOT node_error_passive)) OR go_tx OR send_ack) = '1') THEN
tx_next_sp <= '0' ;
ELSE
IF ((go_error_frame AND node_error_passive) = '1') THEN
tx_next_sp <= '1' ;
ELSE
IF (sample_point_xhdl1 = '1') THEN
tx_next_sp <= tx_next ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
-- Blocking synchronization (can occur only once in a bit time)
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
sync_blocked <= '1' ;
ELSIF (clk'EVENT AND clk = '1') THEN
IF (clk_en_q = '1') THEN
IF (resync = '1') THEN
sync_blocked <= '1' ;
ELSE
IF (go_seg2 = '1') THEN
sync_blocked <= '0' ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
-- Blocking hard synchronization when occurs once or when we are transmitting a msg
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
hard_sync_blocked <= '0' ;
ELSIF (clk'EVENT AND clk = '1') THEN
IF (((hard_sync_xhdl5 AND clk_en_q) OR ((((transmitting AND transmitter) OR go_tx) AND tx_point_xhdl4) AND (NOT tx_next))) = '1') THEN
hard_sync_blocked <= '1' ;
ELSE
IF ((go_rx_inter OR (((rx_idle OR rx_inter) AND sample_point_xhdl1) AND sampled_bit_xhdl2)) = '1') THEN
-- When a glitch performed synchronization
hard_sync_blocked <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE RTL;
----------------------------------------------------------------------------------------------
--
-- VHDL file generated by X-HDL - Revision 3.2.53 Aug. 1, 2005
-- Tue Aug 9 07:33:51 2005
--
-- Input file : C:/Documents and Settings/BryantI/My Documents/tmp/can_top.v
-- Design name : can_fifo
-- Author :
-- Company : Actel
--
-- Description :
--
--
----------------------------------------------------------------------------------------------
--
--////////////////////////////////////////////////////////////////////
--// ////
--// can_fifo.v ////
--// ////
--// ////
--// This file is part of the CAN Protocol Controller ////
--// http://www.opencores.org/projects/can/ ////
--// ////
--// ////
--// Author(s): ////
--// Igor Mohor ////
--// [email protected] ////
--// ////
--// ////
--// All additional information is available in the README.txt ////
--// file. ////
--// ////
--////////////////////////////////////////////////////////////////////
--// ////
--// Copyright (C) 2002, 2003, 2004 Authors ////
--// ////
--// This source file may be used and distributed without ////
--// restriction provided that this copyright statement is not ////
--// removed from the file and that any derivative work contains ////
--// the original copyright notice and the associated disclaimer. ////
--// ////
--// This source file is free software; you can redistribute it ////
--// and/or modify it under the terms of the GNU Lesser General ////
--// Public License as published by the Free Software Foundation; ////
--// either version 2.1 of the License, or (at your option) any ////
--// later version. ////
--// ////
--// This source is distributed in the hope that it will be ////
--// useful, but WITHOUT ANY WARRANTY; without even the implied ////
--// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
--// PURPOSE. See the GNU Lesser General Public License for more ////
--// details. ////
--// ////
--// You should have received a copy of the GNU Lesser General ////
--// Public License along with this source; if not, download it ////
--// from http://www.opencores.org/lgpl.shtml ////
--// ////
--// The CAN protocol is developed by Robert Bosch GmbH and ////
--// protected by patents. Anybody who wants to implement this ////
--// CAN IP core on silicon has to obtain a CAN protocol license ////
--// from Bosch. ////
--// ////
--////////////////////////////////////////////////////////////////////
--
-- CVS Revision History
--
-- Rev 1.28 rd_info_pointer fix from opencores merged. /Kristoffer
--
-- $Log: can_fifo.v,v $
-- Revision 1.27 2004/11/18 12:39:34 igorm
-- Fixes for compatibility after the SW reset.
--
-- Revision 1.26 2004/02/08 14:30:57 mohor
-- Header changed.
--
-- Revision 1.25 2003/10/23 16:52:17 mohor
-- Active high/low problem when Altera devices are used. Bug fixed by
-- Rojhalat Ibrahim.
--
-- Revision 1.24 2003/10/17 05:55:20 markom
-- mbist signals updated according to newest convention
--
-- Revision 1.23 2003/09/05 12:46:41 mohor
-- ALTERA_RAM supported.
--
-- Revision 1.22 2003/08/20 09:59:16 mohor
-- Artisan RAM fixed (when not using BIST).
--
-- Revision 1.21 2003/08/14 16:04:52 simons
-- Artisan ram instances added.
--
-- Revision 1.20 2003/07/16 14:00:45 mohor
-- Fixed according to the linter.
--
-- Revision 1.19 2003/07/03 09:30:44 mohor
-- PCI_BIST replaced with CAN_BIST.
--
-- Revision 1.18 2003/06/27 22:14:23 simons
-- Overrun fifo implemented with FFs, because it is not possible to create such a memory.
--
-- Revision 1.17 2003/06/27 20:56:15 simons
-- Virtual silicon ram instances added.
--
-- Revision 1.16 2003/06/18 23:03:44 mohor
-- Typo fixed.
--
-- Revision 1.15 2003/06/11 09:37:05 mohor
-- overrun and length_info fifos are initialized at the end of reset.
--
-- Revision 1.14 2003/03/05 15:02:30 mohor
-- Xilinx RAM added.
--
-- Revision 1.13 2003/03/01 22:53:33 mohor
-- Actel APA ram supported.
--
-- Revision 1.12 2003/02/19 14:44:03 mohor
-- CAN core finished. Host interface added. Registers finished.
-- Synchronization to the wishbone finished.
--
-- Revision 1.11 2003/02/14 20:17:01 mohor
-- Several registers added. Not finished, yet.
--
-- Revision 1.10 2003/02/11 00:56:06 mohor
-- Wishbone interface added.
--
-- Revision 1.9 2003/02/09 02:24:33 mohor
-- Bosch license warning added. Error counters finished. Overload frames
-- still need to be fixed.
--
-- Revision 1.8 2003/01/31 01:13:38 mohor
-- backup.
--
-- Revision 1.7 2003/01/17 17:44:31 mohor
-- Fifo corrected to be synthesizable.
--
-- Revision 1.6 2003/01/15 13:16:47 mohor
-- When a frame with "remote request" is received, no data is stored
-- to fifo, just the frame information (identifier, ...). Data length
-- that is stored is the received data length and not the actual data
-- length that is stored to fifo.
--
-- Revision 1.5 2003/01/14 17:25:09 mohor
-- Addresses corrected to decimal values (previously hex).
--
-- Revision 1.4 2003/01/14 12:19:35 mohor
-- rx_fifo is now working.
--
-- Revision 1.3 2003/01/09 21:54:45 mohor
-- rx fifo added. Not 100 % verified, yet.
--
-- Revision 1.2 2003/01/09 14:46:58 mohor
-- Temporary files (backup).
--
-- Revision 1.1 2003/01/08 02:10:55 mohor
-- Acceptance filter added.
--
--
--
--
-- synopsys translate_off
--`include "can_defines.v"
-- synopsys translate_on
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
ENTITY can_fifo IS
PORT (
clk : IN std_logic;
rst : IN std_logic;
wr : IN std_logic;
data_in : IN std_logic_vector(7 DOWNTO 0);
addr : IN std_logic_vector(5 DOWNTO 0);
data_out : OUT std_logic_vector(7 DOWNTO 0);
fifo_selected : IN std_logic;
reset_mode : IN std_logic;
release_buffer : IN std_logic;
extended_mode : IN std_logic;
overrun : OUT std_logic;
info_empty : OUT std_logic;
info_cnt : OUT std_logic_vector(6 DOWNTO 0);
--------------------------------------------------
-- port connections for Ram
--64x8
q_dp_64x8 : IN std_logic_vector(7 DOWNTO 0);
data_64x8 : OUT std_logic_vector(7 DOWNTO 0);
wren_64x8 : OUT std_logic;
rden_64x8 : OUT std_logic;
wraddress_64x8 : OUT std_logic_vector(5 DOWNTO 0);
rdaddress_64x8 : OUT std_logic_vector(5 DOWNTO 0);
--64x4
q_dp_64x4 : IN std_logic_vector(3 DOWNTO 0);
data_64x4 : OUT std_logic_vector(3 DOWNTO 0);
wren_64x4x1 : OUT std_logic;
wraddress_64x4x1 : OUT std_logic_vector(5 DOWNTO 0);
rdaddress_64x4x1 : OUT std_logic_vector(5 DOWNTO 0);
--64x1
q_dp_64x1 : IN std_logic;
data_64x1 : OUT std_logic);
END ENTITY can_fifo;
ARCHITECTURE RTL OF can_fifo IS
TYPE xhdl_15 IS ARRAY (0 TO 63) OF std_logic_vector(7 DOWNTO 0);
TYPE xhdl_16 IS ARRAY (0 TO 63) OF std_logic_vector(3 DOWNTO 0);
TYPE xhdl_17 IS ARRAY (0 TO 63) OF std_logic;
TYPE xhdl_46 IS ARRAY (0 TO 7) OF std_logic_vector(7 DOWNTO 0);
--------------------------------------------------
SIGNAL fifo : xhdl_15;
SIGNAL length_fifo : xhdl_16;
SIGNAL overrun_info : xhdl_17;
SIGNAL rd_pointer : std_logic_vector(5 DOWNTO 0);
SIGNAL wr_pointer : std_logic_vector(5 DOWNTO 0);
SIGNAL read_address : std_logic_vector(5 DOWNTO 0);
SIGNAL wr_info_pointer : std_logic_vector(5 DOWNTO 0);
SIGNAL rd_info_pointer : std_logic_vector(5 DOWNTO 0);
SIGNAL wr_q : std_logic;
SIGNAL len_cnt : std_logic_vector(3 DOWNTO 0);
SIGNAL fifo_cnt : std_logic_vector(6 DOWNTO 0);
SIGNAL latch_overrun : std_logic;
SIGNAL initialize_memories : std_logic;
SIGNAL length_info : std_logic_vector(3 DOWNTO 0);
SIGNAL write_length_info : std_logic;
SIGNAL fifo_empty : std_logic;
SIGNAL fifo_full : std_logic;
SIGNAL info_full : std_logic;
SIGNAL data_out_xhdl1 : std_logic_vector(7 DOWNTO 0);
SIGNAL overrun_xhdl2 : std_logic;
SIGNAL info_empty_xhdl3 : std_logic;
SIGNAL info_cnt_xhdl4 : std_logic_vector(6 DOWNTO 0);
SIGNAL data_64x8_xhdl5 : std_logic_vector(7 DOWNTO 0);
SIGNAL wren_64x8_xhdl6 : std_logic;
SIGNAL rden_64x8_xhdl7 : std_logic;
SIGNAL wraddress_64x8_xhdl8 : std_logic_vector(5 DOWNTO 0);
SIGNAL rdaddress_64x8_xhdl9 : std_logic_vector(5 DOWNTO 0);
SIGNAL data_64x4_xhdl10 : std_logic_vector(3 DOWNTO 0);
SIGNAL wren_64x4x1_xhdl11 : std_logic;
SIGNAL wraddress_64x4x1_xhdl12 : std_logic_vector(5 DOWNTO 0);
SIGNAL rdaddress_64x4x1_xhdl13 : std_logic_vector(5 DOWNTO 0);
SIGNAL data_64x1_xhdl14 : std_logic;
BEGIN
data_out <= data_out_xhdl1;
overrun <= overrun_xhdl2;
info_empty <= info_empty_xhdl3;
info_cnt <= info_cnt_xhdl4;
data_64x8 <= data_64x8_xhdl5;
wren_64x8 <= wren_64x8_xhdl6;
rden_64x8 <= rden_64x8_xhdl7;
wraddress_64x8 <= wraddress_64x8_xhdl8;
rdaddress_64x8 <= rdaddress_64x8_xhdl9;
data_64x4 <= data_64x4_xhdl10;
wren_64x4x1 <= wren_64x4x1_xhdl11;
wraddress_64x4x1 <= wraddress_64x4x1_xhdl12;
rdaddress_64x4x1 <= rdaddress_64x4x1_xhdl13;
data_64x1 <= data_64x1_xhdl14;
write_length_info <= (NOT wr) AND wr_q ;
-- Delayed write signal
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
wr_q <= '0' ;
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
wr_q <= '0' ;
ELSE
wr_q <= wr ;
END IF;
END IF;
END PROCESS;
-- length counter
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
len_cnt <= "0000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR write_length_info) = '1') THEN
len_cnt <= "0000" ;
ELSE
IF ((wr AND (NOT fifo_full)) = '1') THEN
len_cnt <= len_cnt + "0001" ;
END IF;
END IF;
END IF;
END PROCESS;
-- wr_info_pointer
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
wr_info_pointer <= "000000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (((write_length_info AND (NOT info_full)) OR initialize_memories) = '1') THEN
wr_info_pointer <= wr_info_pointer + "000001" ;
ELSE
IF (reset_mode = '1') THEN
wr_info_pointer <= rd_info_pointer ;
END IF;
END IF;
END IF;
END PROCESS;
-- rd_info_pointer
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rd_info_pointer <= "000000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((release_buffer AND (NOT info_empty_xhdl3)) = '1') THEN
-- Fix from opencores rev 1.28
-- IF ((release_buffer AND (NOT fifo_empty)) = '1') THEN
rd_info_pointer <= rd_info_pointer + "000001" ;
END IF;
END IF;
END PROCESS;
-- rd_pointer
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rd_pointer <= "000000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((release_buffer AND (NOT fifo_empty)) = '1') THEN
rd_pointer <= rd_pointer + ("00" & length_info) ;
END IF;
END IF;
END PROCESS;
-- wr_pointer
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
wr_pointer <= "000000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
wr_pointer <= rd_pointer ;
ELSE
IF ((wr AND (NOT fifo_full)) = '1') THEN
wr_pointer <= wr_pointer + "000001" ;
END IF;
END IF;
END IF;
END PROCESS;
-- latch_overrun
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
latch_overrun <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR write_length_info) = '1') THEN
latch_overrun <= '0' ;
ELSE
IF ((wr AND fifo_full) = '1') THEN
latch_overrun <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Counting data in fifo
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
fifo_cnt <= "0000000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
fifo_cnt <= "0000000" ;
ELSE
IF (((wr AND (NOT release_buffer)) AND (NOT fifo_full)) = '1') THEN
fifo_cnt <= fifo_cnt + "0000001" ;
ELSE
IF ((((NOT wr) AND release_buffer) AND (NOT fifo_empty)) = '1') THEN
fifo_cnt <= fifo_cnt - ("000" & length_info) ;
ELSE
IF ((((wr AND release_buffer) AND (NOT fifo_full)) AND (NOT fifo_empty)) = '1') THEN
fifo_cnt <= fifo_cnt - ("000" & length_info) + "0000001" ;
END IF;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
fifo_full <= CONV_STD_LOGIC(fifo_cnt = "1000000") ;
fifo_empty <= CONV_STD_LOGIC(fifo_cnt = "0000000") ;
-- Counting data in length_fifo and overrun_info fifo
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
info_cnt_xhdl4 <= "0000000" ;
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
info_cnt_xhdl4 <= "0000000" ;
ELSE
IF ((write_length_info XOR release_buffer) = '1') THEN
IF ((release_buffer AND (NOT info_empty_xhdl3)) = '1') THEN
info_cnt_xhdl4 <= info_cnt_xhdl4 - "0000001" ;
ELSE
IF ((write_length_info AND (NOT info_full)) = '1') THEN
info_cnt_xhdl4 <= info_cnt_xhdl4 + "0000001" ;
END IF;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
info_full <= CONV_STD_LOGIC(info_cnt_xhdl4 = "1000000") ;
info_empty_xhdl3 <= CONV_STD_LOGIC(info_cnt_xhdl4 = "0000000") ;
-- Selecting which address will be used for reading data from rx fifo
PROCESS (extended_mode, rd_pointer, addr)
VARIABLE read_address_xhdl18 : std_logic_vector(5 DOWNTO 0);
BEGIN
IF (extended_mode = '1') THEN
-- extended mode
read_address_xhdl18 := rd_pointer + (addr - "010000");
ELSE
-- normal mode
read_address_xhdl18 := rd_pointer + (addr - "010100");
END IF;
read_address <= read_address_xhdl18;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
initialize_memories <= '1';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (andv(wr_info_pointer) = '1') THEN
initialize_memories <= '0' ;
END IF;
END IF;
END PROCESS;
-- port connections for Ram
--64x8
data_out_xhdl1 <= q_dp_64x8 ;
data_64x8_xhdl5 <= data_in ;
wren_64x8_xhdl6 <= wr AND (NOT fifo_full) ;
rden_64x8_xhdl7 <= fifo_selected ;
wraddress_64x8_xhdl8 <= wr_pointer ;
rdaddress_64x8_xhdl9 <= read_address ;
--64x4
length_info <= q_dp_64x4 ;
data_64x4_xhdl10 <= len_cnt AND NOT initialize_memories & NOT initialize_memories & NOT initialize_memories & NOT initialize_memories ;
wren_64x4x1_xhdl11 <= (write_length_info AND (NOT info_full)) OR initialize_memories ;
wraddress_64x4x1_xhdl12 <= wr_info_pointer ;
rdaddress_64x4x1_xhdl13 <= rd_info_pointer ;
--64x1
overrun_xhdl2 <= q_dp_64x1 ;
data_64x1_xhdl14 <= (latch_overrun OR (wr AND fifo_full)) AND (NOT initialize_memories) ;
-- `ifdef ALTERA_RAM
-- // altera_ram_64x8_sync fifo
-- lpm_ram_dp fifo
-- (
-- .q (data_out),
-- .rdclock (clk),
-- .wrclock (clk),
-- .data (data_in),
-- .wren (wr & (~fifo_full)),
-- .rden (fifo_selected),
-- .wraddress (wr_pointer),
-- .rdaddress (read_address)
-- );
-- defparam fifo.lpm_width = 8;
-- defparam fifo.lpm_widthad = 6;
-- defparam fifo.lpm_numwords = 64;
--
--
-- // altera_ram_64x4_sync info_fifo
-- lpm_ram_dp info_fifo
-- (
-- .q (length_info),
-- .rdclock (clk),
-- .wrclock (clk),
-- .data (len_cnt & {4{~initialize_memories}}),
-- .wren (write_length_info & (~info_full) | initialize_memories),
-- .wraddress (wr_info_pointer),
-- .rdaddress (rd_info_pointer)
-- );
-- defparam info_fifo.lpm_width = 4;
-- defparam info_fifo.lpm_widthad = 6;
-- defparam info_fifo.lpm_numwords = 64;
--
--
-- // altera_ram_64x1_sync overrun_fifo
-- lpm_ram_dp overrun_fifo
-- (
-- .q (overrun),
-- .rdclock (clk),
-- .wrclock (clk),
-- .data ((latch_overrun | (wr & fifo_full)) & (~initialize_memories)),
-- .wren (write_length_info & (~info_full) | initialize_memories),
-- .wraddress (wr_info_pointer),
-- .rdaddress (rd_info_pointer)
-- );
-- defparam overrun_fifo.lpm_width = 1;
-- defparam overrun_fifo.lpm_widthad = 6;
-- defparam overrun_fifo.lpm_numwords = 64;
END ARCHITECTURE RTL;
----------------------------------------------------------------------------------------------
--
-- VHDL file generated by X-HDL - Revision 3.2.53 Aug. 1, 2005
-- Tue Aug 9 07:33:51 2005
--
-- Input file : C:/Documents and Settings/BryantI/My Documents/tmp/can_top.v
-- Design name : can_crc
-- Author :
-- Company : Actel
--
-- Description :
--
--
----------------------------------------------------------------------------------------------
--
--////////////////////////////////////////////////////////////////////
--// ////
--// can_crc.v ////
--// ////
--// ////
--// This file is part of the CAN Protocol Controller ////
--// http://www.opencores.org/projects/can/ ////
--// ////
--// ////
--// Author(s): ////
--// Igor Mohor ////
--// [email protected] ////
--// ////
--// ////
--// All additional information is available in the README.txt ////
--// file. ////
--// ////
--////////////////////////////////////////////////////////////////////
--// ////
--// Copyright (C) 2002, 2003, 2004 Authors ////
--// ////
--// This source file may be used and distributed without ////
--// restriction provided that this copyright statement is not ////
--// removed from the file and that any derivative work contains ////
--// the original copyright notice and the associated disclaimer. ////
--// ////
--// This source file is free software; you can redistribute it ////
--// and/or modify it under the terms of the GNU Lesser General ////
--// Public License as published by the Free Software Foundation; ////
--// either version 2.1 of the License, or (at your option) any ////
--// later version. ////
--// ////
--// This source is distributed in the hope that it will be ////
--// useful, but WITHOUT ANY WARRANTY; without even the implied ////
--// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
--// PURPOSE. See the GNU Lesser General Public License for more ////
--// details. ////
--// ////
--// You should have received a copy of the GNU Lesser General ////
--// Public License along with this source; if not, download it ////
--// from http://www.opencores.org/lgpl.shtml ////
--// ////
--// The CAN protocol is developed by Robert Bosch GmbH and ////
--// protected by patents. Anybody who wants to implement this ////
--// CAN IP core on silicon has to obtain a CAN protocol license ////
--// from Bosch. ////
--// ////
--////////////////////////////////////////////////////////////////////
--
-- CVS Revision History
--
-- $Log: can_crc.v,v $
-- Revision 1.5 2004/02/08 14:25:57 mohor
-- Header changed.
--
-- Revision 1.4 2003/07/16 13:16:51 mohor
-- Fixed according to the linter.
--
-- Revision 1.3 2003/02/10 16:02:11 mohor
-- CAN is working according to the specification. WB interface and more
-- registers (status, IRQ, ...) needs to be added.
--
-- Revision 1.2 2003/02/09 02:24:33 mohor
-- Bosch license warning added. Error counters finished. Overload frames
-- still need to be fixed.
--
-- Revision 1.1 2003/01/08 02:10:54 mohor
-- Acceptance filter added.
--
--
--
--
-- synopsys translate_off
--`include "can_defines.v"
-- synopsys translate_on
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
ENTITY can_crc IS
PORT (
clk : IN std_logic;
data : IN std_logic;
enable : IN std_logic;
initialize : IN std_logic;
crc : OUT std_logic_vector(14 DOWNTO 0));
END ENTITY can_crc;
ARCHITECTURE RTL OF can_crc IS
TYPE xhdl_46 IS ARRAY (0 TO 7) OF std_logic_vector(7 DOWNTO 0);
SIGNAL crc_next : std_logic;
SIGNAL crc_tmp : std_logic_vector(14 DOWNTO 0);
SIGNAL crc_xhdl1 : std_logic_vector(14 DOWNTO 0);
BEGIN
crc <= crc_xhdl1;
crc_next <= data XOR crc_xhdl1(14) ;
crc_tmp <= crc_xhdl1(13 DOWNTO 0) & '0' ;
PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk = '1') THEN
IF (initialize = '1') THEN
crc_xhdl1 <= "000000000000000";
ELSE
IF (enable = '1') THEN
IF (crc_next = '1') THEN
crc_xhdl1 <= crc_tmp XOR "100010110011001";
ELSE
crc_xhdl1 <= crc_tmp ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE RTL;
----------------------------------------------------------------------------------------------
--
-- VHDL file generated by X-HDL - Revision 3.2.53 Aug. 1, 2005
-- Tue Aug 9 07:33:51 2005
--
-- Input file : C:/Documents and Settings/BryantI/My Documents/tmp/can_top.v
-- Design name : can_ibo
-- Author :
-- Company : Actel
--
-- Description :
--
--
----------------------------------------------------------------------------------------------
--
--////////////////////////////////////////////////////////////////////
--// ////
--// can_ibo.v ////
--// ////
--// ////
--// This file is part of the CAN Protocol Controller ////
--// http://www.opencores.org/projects/can/ ////
--// ////
--// ////
--// Author(s): ////
--// Igor Mohor ////
--// [email protected] ////
--// ////
--// ////
--// All additional information is available in the README.txt ////
--// file. ////
--// ////
--////////////////////////////////////////////////////////////////////
--// ////
--// Copyright (C) 2002, 2003, 2004 Authors ////
--// ////
--// This source file may be used and distributed without ////
--// restriction provided that this copyright statement is not ////
--// removed from the file and that any derivative work contains ////
--// the original copyright notice and the associated disclaimer. ////
--// ////
--// This source file is free software; you can redistribute it ////
--// and/or modify it under the terms of the GNU Lesser General ////
--// Public License as published by the Free Software Foundation; ////
--// either version 2.1 of the License, or (at your option) any ////
--// later version. ////
--// ////
--// This source is distributed in the hope that it will be ////
--// useful, but WITHOUT ANY WARRANTY; without even the implied ////
--// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
--// PURPOSE. See the GNU Lesser General Public License for more ////
--// details. ////
--// ////
--// You should have received a copy of the GNU Lesser General ////
--// Public License along with this source; if not, download it ////
--// from http://www.opencores.org/lgpl.shtml ////
--// ////
--// The CAN protocol is developed by Robert Bosch GmbH and ////
--// protected by patents. Anybody who wants to implement this ////
--// CAN IP core on silicon has to obtain a CAN protocol license ////
--// from Bosch. ////
--// ////
--////////////////////////////////////////////////////////////////////
--
-- CVS Revision History
--
-- $Log: can_ibo.v,v $
-- Revision 1.3 2004/02/08 14:31:44 mohor
-- Header changed.
--
-- Revision 1.2 2003/02/09 02:24:33 mohor
-- Bosch license warning added. Error counters finished. Overload frames
-- still need to be fixed.
--
-- Revision 1.1 2003/02/04 14:34:52 mohor
-- *** empty log message ***
--
--
--
--
-- synopsys translate_off
--`include "can_defines.v"
-- synopsys translate_on
-- This module only inverts bit order
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY can_ibo IS
PORT (
di : IN std_logic_vector(7 DOWNTO 0);
do : OUT std_logic_vector(7 DOWNTO 0));
END ENTITY can_ibo;
ARCHITECTURE RTL OF can_ibo IS
TYPE xhdl_15 IS ARRAY (0 TO 63) OF std_logic_vector(7 DOWNTO 0);
TYPE xhdl_16 IS ARRAY (0 TO 63) OF std_logic_vector(3 DOWNTO 0);
TYPE xhdl_17 IS ARRAY (0 TO 63) OF std_logic;
TYPE xhdl_46 IS ARRAY (0 TO 7) OF std_logic_vector(7 DOWNTO 0);
SIGNAL do_xhdl1 : std_logic_vector(7 DOWNTO 0);
BEGIN
do <= do_xhdl1;
do_xhdl1(0) <= di(7) ;
do_xhdl1(1) <= di(6) ;
do_xhdl1(2) <= di(5) ;
do_xhdl1(3) <= di(4) ;
do_xhdl1(4) <= di(3) ;
do_xhdl1(5) <= di(2) ;
do_xhdl1(6) <= di(1) ;
do_xhdl1(7) <= di(0) ;
END ARCHITECTURE RTL;
----------------------------------------------------------------------------------------------
--
-- VHDL file generated by X-HDL - Revision 3.2.53 Aug. 1, 2005
-- Tue Aug 9 07:33:51 2005
--
-- Input file : C:/Documents and Settings/BryantI/My Documents/tmp/can_top.v
-- Design name : can_bsp
-- Author :
-- Company : Actel
--
-- Description :
--
--
----------------------------------------------------------------------------------------------
--
--////////////////////////////////////////////////////////////////////
--// ////
--// can_bsp.v ////
--// ////
--// ////
--// This file is part of the CAN Protocol Controller ////
--// http://www.opencores.org/projects/can/ ////
--// ////
--// ////
--// Author(s): ////
--// Igor Mohor ////
--// [email protected] ////
--// ////
--// ////
--// All additional information is available in the README.txt ////
--// file. ////
--// ////
--////////////////////////////////////////////////////////////////////
--// ////
--// Copyright (C) 2002, 2003, 2004 Authors ////
--// ////
--// This source file may be used and distributed without ////
--// restriction provided that this copyright statement is not ////
--// removed from the file and that any derivative work contains ////
--// the original copyright notice and the associated disclaimer. ////
--// ////
--// This source file is free software; you can redistribute it ////
--// and/or modify it under the terms of the GNU Lesser General ////
--// Public License as published by the Free Software Foundation; ////
--// either version 2.1 of the License, or (at your option) any ////
--// later version. ////
--// ////
--// This source is distributed in the hope that it will be ////
--// useful, but WITHOUT ANY WARRANTY; without even the implied ////
--// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
--// PURPOSE. See the GNU Lesser General Public License for more ////
--// details. ////
--// ////
--// You should have received a copy of the GNU Lesser General ////
--// Public License along with this source; if not, download it ////
--// from http://www.opencores.org/lgpl.shtml ////
--// ////
--// The CAN protocol is developed by Robert Bosch GmbH and ////
--// protected by patents. Anybody who wants to implement this ////
--// CAN IP core on silicon has to obtain a CAN protocol license ////
--// from Bosch. ////
--// ////
--////////////////////////////////////////////////////////////////////
--
-- CVS Revision History
--
-- $Log: can_bsp.v,v $
-- Revision 1.52 2004/11/18 12:39:21 igorm
-- Fixes for compatibility after the SW reset.
--
-- Revision 1.51 2004/11/15 18:23:21 igorm
-- When CAN was reset by setting the reset_mode signal in mode register, it
-- was possible that CAN was blocked for a short period of time. Problem
-- occured very rarly.
--
-- Revision 1.50 2004/10/27 18:51:36 igorm
-- Fixed synchronization problem in real hardware when 0xf is used for TSEG1.
--
-- Revision 1.49 2004/10/25 06:37:51 igorm
-- Arbitration bug fixed.
--
-- Revision 1.48 2004/05/12 15:58:41 igorm
-- Core improved to pass all tests with the Bosch VHDL Reference system.
--
-- Revision 1.47 2004/02/08 14:24:10 mohor
-- Error counters changed.
--
-- Revision 1.46 2003/10/17 05:55:20 markom
-- mbist signals updated according to newest convention
--
-- Revision 1.45 2003/09/30 21:14:33 mohor
-- Error counters changed.
--
-- Revision 1.44 2003/09/30 00:55:12 mohor
-- Error counters fixed to be compatible with Bosch VHDL reference model.
-- Small synchronization changes.
--
-- Revision 1.43 2003/09/25 18:55:49 mohor
-- Synchronization changed, error counters fixed.
--
-- Revision 1.42 2003/08/29 07:01:14 mohor
-- When detecting bus-free, signal bus_free_cnt_en was cleared to zero
-- although the last sampled bit was zero instead of one.
--
-- Revision 1.41 2003/07/18 15:23:31 tadejm
-- Tx and rx length are limited to 8 bytes regardless to the DLC value.
--
-- Revision 1.40 2003/07/16 15:10:17 mohor
-- Fixed according to the linter.
--
-- Revision 1.39 2003/07/16 13:12:46 mohor
-- Fixed according to the linter.
--
-- Revision 1.38 2003/07/10 01:59:04 tadejm
-- Synchronization fixed. In some strange cases it didn't work according to
-- the VHDL reference model.
--
-- Revision 1.37 2003/07/07 11:21:37 mohor
-- Little fixes (to fix warnings).
--
-- Revision 1.36 2003/07/03 09:32:20 mohor
-- Synchronization changed.
--
-- Revision 1.35 2003/06/27 20:56:12 simons
-- Virtual silicon ram instances added.
--
-- Revision 1.34 2003/06/22 09:43:03 mohor
-- synthesi full_case parallel_case fixed.
--
-- Revision 1.33 2003/06/21 12:16:30 mohor
-- paralel_case and full_case compiler directives added to case statements.
--
-- Revision 1.32 2003/06/17 14:28:32 mohor
-- Form error was detected when stuff bit occured at the end of crc.
--
-- Revision 1.31 2003/06/16 14:31:29 tadejm
-- Bit stuffing corrected when stuffing comes at the end of the crc.
--
-- Revision 1.30 2003/06/16 13:57:58 mohor
-- tx_point generated one clk earlier. rx_i registered. Data corrected when
-- using extended mode.
--
-- Revision 1.29 2003/06/11 14:21:35 mohor
-- When switching to tx, sync stage is overjumped.
--
-- Revision 1.28 2003/03/01 22:53:33 mohor
-- Actel APA ram supported.
--
-- Revision 1.27 2003/02/20 00:26:02 mohor
-- When a dominant bit was detected at the third bit of the intermission and
-- node had a message to transmit, bit_stuff error could occur. Fixed.
--
-- Revision 1.26 2003/02/19 23:21:54 mohor
-- When bit error occured while active error flag was transmitted, counter was
-- not incremented.
--
-- Revision 1.25 2003/02/19 14:44:03 mohor
-- CAN core finished. Host interface added. Registers finished.
-- Synchronization to the wishbone finished.
--
-- Revision 1.24 2003/02/18 00:10:15 mohor
-- Most of the registers added. Registers "arbitration lost capture", "error code
-- capture" + few more still need to be added.
--
-- Revision 1.23 2003/02/14 20:17:01 mohor
-- Several registers added. Not finished, yet.
--
-- Revision 1.22 2003/02/12 14:23:59 mohor
-- abort_tx added. Bit destuff fixed.
--
-- Revision 1.21 2003/02/11 00:56:06 mohor
-- Wishbone interface added.
--
-- Revision 1.20 2003/02/10 16:02:11 mohor
-- CAN is working according to the specification. WB interface and more
-- registers (status, IRQ, ...) needs to be added.
--
-- Revision 1.19 2003/02/09 18:40:29 mohor
-- Overload fixed. Hard synchronization also enabled at the last bit of
-- interframe.
--
-- Revision 1.18 2003/02/09 02:24:33 mohor
-- Bosch license warning added. Error counters finished. Overload frames
-- still need to be fixed.
--
-- Revision 1.17 2003/02/04 17:24:41 mohor
-- Backup.
--
-- Revision 1.16 2003/02/04 14:34:52 mohor
-- *** empty log message ***
--
-- Revision 1.15 2003/01/31 01:13:37 mohor
-- backup.
--
-- Revision 1.14 2003/01/16 13:36:19 mohor
-- Form error supported. When receiving messages, last bit of the end-of-frame
-- does not generate form error. Receiver goes to the idle mode one bit sooner.
-- (CAN specification ver 2.0, part B, page 57).
--
-- Revision 1.13 2003/01/15 21:59:45 mohor
-- Data is stored to fifo at the end of ack stage.
--
-- Revision 1.12 2003/01/15 21:05:11 mohor
-- CRC checking fixed (when bitstuff occurs at the end of a CRC sequence).
--
-- Revision 1.11 2003/01/15 14:40:23 mohor
-- RX state machine fixed to receive "remote request" frames correctly.
-- No data bytes are written to fifo when such frames are received.
--
-- Revision 1.10 2003/01/15 13:16:47 mohor
-- When a frame with "remote request" is received, no data is stored to
-- fifo, just the frame information (identifier, ...). Data length that
-- is stored is the received data length and not the actual data length
-- that is stored to fifo.
--
-- Revision 1.9 2003/01/14 12:19:35 mohor
-- rx_fifo is now working.
--
-- Revision 1.8 2003/01/10 17:51:33 mohor
-- Temporary version (backup).
--
-- Revision 1.7 2003/01/09 21:54:45 mohor
-- rx fifo added. Not 100 % verified, yet.
--
-- Revision 1.6 2003/01/09 14:46:58 mohor
-- Temporary files (backup).
--
-- Revision 1.5 2003/01/08 13:30:31 mohor
-- Temp version.
--
-- Revision 1.4 2003/01/08 02:10:53 mohor
-- Acceptance filter added.
--
-- Revision 1.3 2002/12/28 04:13:23 mohor
-- Backup version.
--
-- Revision 1.2 2002/12/27 00:12:52 mohor
-- Header changed, testbench improved to send a frame (crc still missing).
--
-- Revision 1.1.1.1 2002/12/20 16:39:21 mohor
-- Initial
--
--
--
-- synopsys translate_off
--`include "can_defines.v"
-- synopsys translate_on
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
ENTITY can_bsp IS
PORT (
clk : IN std_logic;
rst : IN std_logic;
sample_point : IN std_logic;
sampled_bit : IN std_logic;
sampled_bit_q : IN std_logic;
tx_point : IN std_logic;
hard_sync : IN std_logic;
addr : IN std_logic_vector(7 DOWNTO 0);
data_in : IN std_logic_vector(7 DOWNTO 0);
data_out : OUT std_logic_vector(7 DOWNTO 0);
fifo_selected : IN std_logic;
reset_mode : IN std_logic;
listen_only_mode : IN std_logic;
acceptance_filter_mode : IN std_logic;
self_test_mode : IN std_logic;
-- Command register
release_buffer : IN std_logic;
tx_request : IN std_logic;
abort_tx : IN std_logic;
self_rx_request : IN std_logic;
single_shot_transmission: IN std_logic;
tx_state : OUT std_logic;
tx_state_q : OUT std_logic;
overload_request : IN std_logic; -- When receiver is busy, it needs to send overload frame. Only 2 overload frames are allowed to
overload_frame : OUT std_logic; -- be send in a row. This is not implemented, yet, because host can not send an overload request.
-- Arbitration Lost Capture Register
read_arbitration_lost_capture_reg: IN std_logic;
-- Error Code Capture Register
read_error_code_capture_reg: IN std_logic;
error_capture_code : OUT std_logic_vector(7 DOWNTO 0);
-- Error Warning Limit register
error_warning_limit : IN std_logic_vector(7 DOWNTO 0);
-- Rx Error Counter register
we_rx_err_cnt : IN std_logic;
-- Tx Error Counter register
we_tx_err_cnt : IN std_logic;
extended_mode : IN std_logic;
rx_idle : OUT std_logic;
transmitting : OUT std_logic;
transmitter : OUT std_logic;
go_rx_inter : OUT std_logic;
not_first_bit_of_inter : OUT std_logic;
rx_inter : OUT std_logic;
set_reset_mode : OUT std_logic;
node_bus_off : OUT std_logic;
error_status : OUT std_logic;
rx_err_cnt : OUT std_logic_vector(8 DOWNTO 0);
tx_err_cnt : OUT std_logic_vector(8 DOWNTO 0);
transmit_status : OUT std_logic;
receive_status : OUT std_logic;
tx_successful : OUT std_logic;
need_to_tx : OUT std_logic;
overrun : OUT std_logic;
info_empty : OUT std_logic;
set_bus_error_irq : OUT std_logic;
set_arbitration_lost_irq: OUT std_logic;
arbitration_lost_capture: OUT std_logic_vector(4 DOWNTO 0);
node_error_passive : OUT std_logic;
node_error_active : OUT std_logic;
rx_message_counter : OUT std_logic_vector(6 DOWNTO 0);
-- This section is for BASIC and EXTENDED mode -- Acceptance code register
acceptance_code_0 : IN std_logic_vector(7 DOWNTO 0);
-- Acceptance mask register
acceptance_mask_0 : IN std_logic_vector(7 DOWNTO 0);
-- End: This section is for BASIC and EXTENDED mode -- This section is for EXTENDED mode -- Acceptance code register
acceptance_code_1 : IN std_logic_vector(7 DOWNTO 0);
acceptance_code_2 : IN std_logic_vector(7 DOWNTO 0);
acceptance_code_3 : IN std_logic_vector(7 DOWNTO 0);
-- Acceptance mask register
acceptance_mask_1 : IN std_logic_vector(7 DOWNTO 0);
acceptance_mask_2 : IN std_logic_vector(7 DOWNTO 0);
acceptance_mask_3 : IN std_logic_vector(7 DOWNTO 0);
-- End: This section is for EXTENDED mode -- Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data
tx_data_0 : IN std_logic_vector(7 DOWNTO 0);
tx_data_1 : IN std_logic_vector(7 DOWNTO 0);
tx_data_2 : IN std_logic_vector(7 DOWNTO 0);
tx_data_3 : IN std_logic_vector(7 DOWNTO 0);
tx_data_4 : IN std_logic_vector(7 DOWNTO 0);
tx_data_5 : IN std_logic_vector(7 DOWNTO 0);
tx_data_6 : IN std_logic_vector(7 DOWNTO 0);
tx_data_7 : IN std_logic_vector(7 DOWNTO 0);
tx_data_8 : IN std_logic_vector(7 DOWNTO 0);
tx_data_9 : IN std_logic_vector(7 DOWNTO 0);
tx_data_10 : IN std_logic_vector(7 DOWNTO 0);
tx_data_11 : IN std_logic_vector(7 DOWNTO 0);
tx_data_12 : IN std_logic_vector(7 DOWNTO 0);
-- End: Tx data registers -- Tx signal
tx : OUT std_logic;
tx_next : OUT std_logic;
bus_off_on : OUT std_logic;
go_overload_frame : OUT std_logic;
go_error_frame : OUT std_logic;
go_tx : OUT std_logic;
send_ack : OUT std_logic;
-- Bist -- port connections for Ram
--64x8
q_dp_64x8 : IN std_logic_vector(7 DOWNTO 0);
data_64x8 : OUT std_logic_vector(7 DOWNTO 0);
wren_64x8 : OUT std_logic;
rden_64x8 : OUT std_logic;
wraddress_64x8 : OUT std_logic_vector(5 DOWNTO 0);
rdaddress_64x8 : OUT std_logic_vector(5 DOWNTO 0);
--64x4
q_dp_64x4 : IN std_logic_vector(3 DOWNTO 0);
data_64x4 : OUT std_logic_vector(3 DOWNTO 0);
wren_64x4x1 : OUT std_logic;
wraddress_64x4x1 : OUT std_logic_vector(5 DOWNTO 0);
rdaddress_64x4x1 : OUT std_logic_vector(5 DOWNTO 0);
--64x1
q_dp_64x1 : IN std_logic;
data_64x1 : OUT std_logic);
END ENTITY can_bsp;
ARCHITECTURE RTL OF can_bsp IS
COMPONENT can_acf
PORT (
clk : IN std_logic;
rst : IN std_logic;
id : IN std_logic_vector(28 DOWNTO 0);
reset_mode : IN std_logic;
acceptance_filter_mode : IN std_logic;
extended_mode : IN std_logic;
acceptance_code_0 : IN std_logic_vector(7 DOWNTO 0);
acceptance_code_1 : IN std_logic_vector(7 DOWNTO 0);
acceptance_code_2 : IN std_logic_vector(7 DOWNTO 0);
acceptance_code_3 : IN std_logic_vector(7 DOWNTO 0);
acceptance_mask_0 : IN std_logic_vector(7 DOWNTO 0);
acceptance_mask_1 : IN std_logic_vector(7 DOWNTO 0);
acceptance_mask_2 : IN std_logic_vector(7 DOWNTO 0);
acceptance_mask_3 : IN std_logic_vector(7 DOWNTO 0);
go_rx_crc_lim : IN std_logic;
go_rx_inter : IN std_logic;
go_error_frame : IN std_logic;
data0 : IN std_logic_vector(7 DOWNTO 0);
data1 : IN std_logic_vector(7 DOWNTO 0);
rtr1 : IN std_logic;
rtr2 : IN std_logic;
ide : IN std_logic;
no_byte0 : IN std_logic;
no_byte1 : IN std_logic;
id_ok : OUT std_logic);
END COMPONENT;
COMPONENT can_crc
PORT (
clk : IN std_logic;
data : IN std_logic;
enable : IN std_logic;
initialize : IN std_logic;
crc : OUT std_logic_vector(14 DOWNTO 0));
END COMPONENT;
COMPONENT can_fifo
PORT (
clk : IN std_logic;
rst : IN std_logic;
wr : IN std_logic;
data_in : IN std_logic_vector(7 DOWNTO 0);
addr : IN std_logic_vector(5 DOWNTO 0);
data_out : OUT std_logic_vector(7 DOWNTO 0);
fifo_selected : IN std_logic;
reset_mode : IN std_logic;
release_buffer : IN std_logic;
extended_mode : IN std_logic;
overrun : OUT std_logic;
info_empty : OUT std_logic;
info_cnt : OUT std_logic_vector(6 DOWNTO 0);
q_dp_64x8 : IN std_logic_vector(7 DOWNTO 0);
data_64x8 : OUT std_logic_vector(7 DOWNTO 0);
wren_64x8 : OUT std_logic;
rden_64x8 : OUT std_logic;
wraddress_64x8 : OUT std_logic_vector(5 DOWNTO 0);
rdaddress_64x8 : OUT std_logic_vector(5 DOWNTO 0);
q_dp_64x4 : IN std_logic_vector(3 DOWNTO 0);
data_64x4 : OUT std_logic_vector(3 DOWNTO 0);
wren_64x4x1 : OUT std_logic;
wraddress_64x4x1 : OUT std_logic_vector(5 DOWNTO 0);
rdaddress_64x4x1 : OUT std_logic_vector(5 DOWNTO 0);
q_dp_64x1 : IN std_logic;
data_64x1 : OUT std_logic);
END COMPONENT;
COMPONENT can_ibo
PORT (
di : IN std_logic_vector(7 DOWNTO 0);
do : OUT std_logic_vector(7 DOWNTO 0));
END COMPONENT;
TYPE xhdl_46 IS ARRAY (0 TO 7) OF std_logic_vector(7 DOWNTO 0);
------------------------------
SIGNAL reset_mode_q : std_logic;
SIGNAL bit_cnt : std_logic_vector(5 DOWNTO 0);
SIGNAL data_len : std_logic_vector(3 DOWNTO 0);
SIGNAL id : std_logic_vector(28 DOWNTO 0);
SIGNAL bit_stuff_cnt : std_logic_vector(2 DOWNTO 0);
SIGNAL bit_stuff_cnt_tx : std_logic_vector(2 DOWNTO 0);
SIGNAL tx_point_q : std_logic;
SIGNAL rx_id1 : std_logic;
SIGNAL rx_rtr1 : std_logic;
SIGNAL rx_ide : std_logic;
SIGNAL rx_id2 : std_logic;
SIGNAL rx_rtr2 : std_logic;
SIGNAL rx_r1 : std_logic;
SIGNAL rx_r0 : std_logic;
SIGNAL rx_dlc : std_logic;
SIGNAL rx_data : std_logic;
SIGNAL rx_crc : std_logic;
SIGNAL rx_crc_lim : std_logic;
SIGNAL rx_ack : std_logic;
SIGNAL rx_ack_lim : std_logic;
SIGNAL rx_eof : std_logic;
SIGNAL go_early_tx_latched : std_logic;
SIGNAL rtr1 : std_logic;
SIGNAL ide : std_logic;
SIGNAL rtr2 : std_logic;
SIGNAL crc_in : std_logic_vector(14 DOWNTO 0);
SIGNAL tmp_data : std_logic_vector(7 DOWNTO 0);
SIGNAL tmp_fifo : xhdl_46;
SIGNAL write_data_to_tmp_fifo : std_logic;
SIGNAL byte_cnt : std_logic_vector(2 DOWNTO 0);
SIGNAL bit_stuff_cnt_en : std_logic;
SIGNAL crc_enable : std_logic;
SIGNAL eof_cnt : std_logic_vector(2 DOWNTO 0);
SIGNAL passive_cnt : std_logic_vector(2 DOWNTO 0);
SIGNAL error_frame : std_logic;
SIGNAL enable_error_cnt2 : std_logic;
SIGNAL error_cnt1 : std_logic_vector(2 DOWNTO 0);
SIGNAL error_cnt2 : std_logic_vector(2 DOWNTO 0);
SIGNAL delayed_dominant_cnt : std_logic_vector(2 DOWNTO 0);
SIGNAL enable_overload_cnt2 : std_logic;
SIGNAL overload_frame_blocked : std_logic;
SIGNAL overload_request_cnt : std_logic_vector(1 DOWNTO 0);
SIGNAL overload_cnt1 : std_logic_vector(2 DOWNTO 0);
SIGNAL overload_cnt2 : std_logic_vector(2 DOWNTO 0);
SIGNAL crc_err : std_logic;
SIGNAL arbitration_lost : std_logic;
SIGNAL arbitration_lost_q : std_logic;
SIGNAL read_arbitration_lost_capture_reg_q: std_logic;
signal read_error_code_capture_reg_q : std_logic;
signal reset_error_code_capture_reg : std_logic;
SIGNAL arbitration_cnt_en : std_logic;
SIGNAL arbitration_blocked : std_logic;
SIGNAL tx_q : std_logic;
SIGNAL data_cnt : std_logic_vector(3 DOWNTO 0); -- Counting the data bytes that are written to FIFO
SIGNAL header_cnt : std_logic_vector(2 DOWNTO 0); -- Counting header length
SIGNAL wr_fifo : std_logic; -- Write data and header to 64-byte fifo
SIGNAL data_for_fifo : std_logic_vector(7 DOWNTO 0); -- Multiplexed data that is stored to 64-byte fifo
SIGNAL tx_pointer : std_logic_vector(5 DOWNTO 0);
SIGNAL tx_bit : std_logic;
SIGNAL finish_msg : std_logic;
SIGNAL bus_free_cnt : std_logic_vector(3 DOWNTO 0);
SIGNAL bus_free_cnt_en : std_logic;
SIGNAL bus_free : std_logic;
SIGNAL waiting_for_bus_free : std_logic;
SIGNAL node_bus_off_q : std_logic;
SIGNAL ack_err_latched : std_logic;
SIGNAL bit_err_latched : std_logic;
SIGNAL stuff_err_latched : std_logic;
SIGNAL form_err_latched : std_logic;
SIGNAL rule3_exc1_1 : std_logic;
SIGNAL rule3_exc1_2 : std_logic;
SIGNAL suspend : std_logic;
SIGNAL susp_cnt_en : std_logic;
SIGNAL susp_cnt : std_logic_vector(2 DOWNTO 0);
SIGNAL error_flag_over_latched : std_logic;
SIGNAL error_capture_code_type : std_logic_vector(7 DOWNTO 6);
SIGNAL error_capture_code_blocked : std_logic;
SIGNAL first_compare_bit : std_logic;
SIGNAL error_capture_code_segment : std_logic_vector(4 DOWNTO 0);
SIGNAL error_capture_code_direction : std_logic;
SIGNAL bit_de_stuff : std_logic;
SIGNAL bit_de_stuff_tx : std_logic;
SIGNAL rule5 : std_logic;
-- Rx state machine
SIGNAL go_rx_idle : std_logic;
SIGNAL go_rx_id1 : std_logic;
SIGNAL go_rx_rtr1 : std_logic;
SIGNAL go_rx_ide : std_logic;
SIGNAL go_rx_id2 : std_logic;
SIGNAL go_rx_rtr2 : std_logic;
SIGNAL go_rx_r1 : std_logic;
SIGNAL go_rx_r0 : std_logic;
SIGNAL go_rx_dlc : std_logic;
SIGNAL go_rx_data : std_logic;
SIGNAL go_rx_crc : std_logic;
SIGNAL go_rx_crc_lim : std_logic;
SIGNAL go_rx_ack : std_logic;
SIGNAL go_rx_ack_lim : std_logic;
SIGNAL go_rx_eof : std_logic;
SIGNAL last_bit_of_inter : std_logic;
SIGNAL go_crc_enable : std_logic;
SIGNAL rst_crc_enable : std_logic;
SIGNAL bit_de_stuff_set : std_logic;
SIGNAL bit_de_stuff_reset : std_logic;
SIGNAL go_early_tx : std_logic;
SIGNAL calculated_crc : std_logic_vector(14 DOWNTO 0);
SIGNAL r_calculated_crc : std_logic_vector(15 DOWNTO 0);
SIGNAL remote_rq : std_logic;
SIGNAL limited_data_len : std_logic_vector(3 DOWNTO 0);
SIGNAL form_err : std_logic;
SIGNAL error_frame_ended : std_logic;
SIGNAL overload_frame_ended : std_logic;
SIGNAL bit_err : std_logic;
SIGNAL ack_err : std_logic;
SIGNAL stuff_err : std_logic;
SIGNAL id_ok : std_logic; -- If received ID matches ID set in registers
SIGNAL no_byte0 : std_logic; -- There is no byte 0 (RTR bit set to 1 or DLC field equal to 0). Signal used for acceptance filter.
SIGNAL no_byte1 : std_logic; -- There is no byte 1 (RTR bit set to 1 or DLC field equal to 1). Signal used for acceptance filter.
SIGNAL header_len : std_logic_vector(2 DOWNTO 0);
SIGNAL storing_header : std_logic;
SIGNAL limited_data_len_minus1 : std_logic_vector(3 DOWNTO 0);
SIGNAL reset_wr_fifo : std_logic;
SIGNAL err : std_logic;
SIGNAL arbitration_field : std_logic;
SIGNAL basic_chain : std_logic_vector(18 DOWNTO 0);
SIGNAL basic_chain_data : std_logic_vector(63 DOWNTO 0);
SIGNAL extended_chain_std : std_logic_vector(18 DOWNTO 0);
SIGNAL extended_chain_ext : std_logic_vector(38 DOWNTO 0);
SIGNAL extended_chain_data_std : std_logic_vector(63 DOWNTO 0);
SIGNAL extended_chain_data_ext : std_logic_vector(63 DOWNTO 0);
SIGNAL rst_tx_pointer : std_logic;
SIGNAL r_tx_data_0 : std_logic_vector(7 DOWNTO 0);
SIGNAL r_tx_data_1 : std_logic_vector(7 DOWNTO 0);
SIGNAL r_tx_data_2 : std_logic_vector(7 DOWNTO 0);
SIGNAL r_tx_data_3 : std_logic_vector(7 DOWNTO 0);
SIGNAL r_tx_data_4 : std_logic_vector(7 DOWNTO 0);
SIGNAL r_tx_data_5 : std_logic_vector(7 DOWNTO 0);
SIGNAL r_tx_data_6 : std_logic_vector(7 DOWNTO 0);
SIGNAL r_tx_data_7 : std_logic_vector(7 DOWNTO 0);
SIGNAL r_tx_data_8 : std_logic_vector(7 DOWNTO 0);
SIGNAL r_tx_data_9 : std_logic_vector(7 DOWNTO 0);
SIGNAL r_tx_data_10 : std_logic_vector(7 DOWNTO 0);
SIGNAL r_tx_data_11 : std_logic_vector(7 DOWNTO 0);
SIGNAL r_tx_data_12 : std_logic_vector(7 DOWNTO 0);
SIGNAL bit_err_exc1 : std_logic;
SIGNAL bit_err_exc2 : std_logic;
SIGNAL bit_err_exc3 : std_logic;
SIGNAL bit_err_exc4 : std_logic;
SIGNAL bit_err_exc5 : std_logic;
SIGNAL bit_err_exc6 : std_logic;
SIGNAL error_flag_over : std_logic;
SIGNAL overload_flag_over : std_logic;
SIGNAL limited_tx_cnt_ext : std_logic_vector(5 DOWNTO 0);
SIGNAL limited_tx_cnt_std : std_logic_vector(5 DOWNTO 0);
-- port connections for Ram
--64x8
SIGNAL w_q_dp_64x8 : std_logic_vector(7 DOWNTO 0);
SIGNAL w_data_64x8 : std_logic_vector(7 DOWNTO 0);
SIGNAL w_wren_64x8 : std_logic;
SIGNAL w_rden_64x8 : std_logic;
SIGNAL w_wraddress_64x8 : std_logic_vector(5 DOWNTO 0);
SIGNAL w_rdaddress_64x8 : std_logic_vector(5 DOWNTO 0);
--64x4
SIGNAL w_q_dp_64x4 : std_logic_vector(3 DOWNTO 0);
SIGNAL w_data_64x4 : std_logic_vector(3 DOWNTO 0);
SIGNAL w_wren_64x4x1 : std_logic;
SIGNAL w_wraddress_64x4x1 : std_logic_vector(5 DOWNTO 0);
SIGNAL w_rdaddress_64x4x1 : std_logic_vector(5 DOWNTO 0);
--64x1
SIGNAL w_q_dp_64x1 : std_logic;
SIGNAL w_data_64x1 : std_logic;
SIGNAL temp_xhdl47 : std_logic_vector(3 DOWNTO 0);
-- Instantiation of the RX CRC module
SIGNAL xhdl_49 : std_logic;
-- Mode register
-- Clock Divider register
-- This section is for BASIC and EXTENDED mode
-- Acceptance code register
-- Acceptance mask register
-- End: This section is for BASIC and EXTENDED mode
-- This section is for EXTENDED mode
-- Acceptance code register
-- Acceptance mask register
-- End: This section is for EXTENDED mode
SIGNAL port_xhdl73 : std_logic_vector(7 DOWNTO 0);
SIGNAL port_xhdl74 : std_logic_vector(7 DOWNTO 0);
SIGNAL temp_xhdl75 : std_logic_vector(2 DOWNTO 0);
SIGNAL temp_xhdl76 : std_logic_vector(2 DOWNTO 0);
SIGNAL temp_xhdl77 : std_logic_vector(3 DOWNTO 0);
SIGNAL temp_xhdl78 : std_logic_vector(3 DOWNTO 0); -- - 1 because counter counts from 0
SIGNAL xhdl_106 : std_logic_vector(7 DOWNTO 0);
SIGNAL temp_xhdl108 : std_logic_vector(5 DOWNTO 0);
SIGNAL temp_xhdl109 : std_logic_vector(5 DOWNTO 0);
SIGNAL temp_xhdl110 : boolean;
SIGNAL temp_xhdl111 : std_logic;
SIGNAL data_out_xhdl1 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_state_xhdl2 : std_logic;
SIGNAL tx_state_q_xhdl3 : std_logic;
SIGNAL overload_frame_xhdl4 : std_logic;
SIGNAL error_capture_code_xhdl5 : std_logic_vector(7 DOWNTO 0);
SIGNAL rx_idle_xhdl6 : std_logic;
SIGNAL transmitting_xhdl7 : std_logic;
SIGNAL transmitter_xhdl8 : std_logic;
SIGNAL go_rx_inter_xhdl9 : std_logic;
SIGNAL not_first_bit_of_inter_xhdl10 : std_logic;
SIGNAL rx_inter_xhdl11 : std_logic;
SIGNAL set_reset_mode_xhdl12 : std_logic;
SIGNAL node_bus_off_xhdl13 : std_logic;
SIGNAL error_status_xhdl14 : std_logic;
SIGNAL rx_err_cnt_xhdl15 : std_logic_vector(8 DOWNTO 0);
SIGNAL tx_err_cnt_xhdl16 : std_logic_vector(8 DOWNTO 0);
SIGNAL transmit_status_xhdl17 : std_logic;
SIGNAL receive_status_xhdl18 : std_logic;
SIGNAL tx_successful_xhdl19 : std_logic;
SIGNAL need_to_tx_xhdl20 : std_logic;
SIGNAL overrun_xhdl21 : std_logic;
SIGNAL info_empty_xhdl22 : std_logic;
SIGNAL set_bus_error_irq_xhdl23 : std_logic;
SIGNAL set_arbitration_lost_irq_xhdl24 : std_logic;
SIGNAL arbitration_lost_capture_xhdl25 : std_logic_vector(4 DOWNTO 0);
SIGNAL node_error_passive_xhdl26: std_logic;
SIGNAL node_error_active_xhdl27 : std_logic;
SIGNAL rx_message_counter_xhdl28: std_logic_vector(6 DOWNTO 0);
SIGNAL tx_xhdl29 : std_logic;
SIGNAL tx_next_xhdl30 : std_logic;
SIGNAL bus_off_on_xhdl31 : std_logic;
SIGNAL go_overload_frame_xhdl32 : std_logic;
SIGNAL go_error_frame_xhdl33 : std_logic;
SIGNAL go_tx_xhdl34 : std_logic;
SIGNAL send_ack_xhdl35 : std_logic;
SIGNAL data_64x8_xhdl36 : std_logic_vector(7 DOWNTO 0);
SIGNAL wren_64x8_xhdl37 : std_logic;
SIGNAL rden_64x8_xhdl38 : std_logic;
SIGNAL wraddress_64x8_xhdl39 : std_logic_vector(5 DOWNTO 0);
SIGNAL rdaddress_64x8_xhdl40 : std_logic_vector(5 DOWNTO 0);
SIGNAL data_64x4_xhdl41 : std_logic_vector(3 DOWNTO 0);
SIGNAL wren_64x4x1_xhdl42 : std_logic;
SIGNAL wraddress_64x4x1_xhdl43 : std_logic_vector(5 DOWNTO 0);
SIGNAL rdaddress_64x4x1_xhdl44 : std_logic_vector(5 DOWNTO 0);
SIGNAL data_64x1_xhdl45 : std_logic;
BEGIN
data_out <= data_out_xhdl1;
tx_state <= tx_state_xhdl2;
tx_state_q <= tx_state_q_xhdl3;
overload_frame <= overload_frame_xhdl4;
error_capture_code <= error_capture_code_xhdl5;
rx_idle <= rx_idle_xhdl6;
transmitting <= transmitting_xhdl7;
transmitter <= transmitter_xhdl8;
go_rx_inter <= go_rx_inter_xhdl9;
not_first_bit_of_inter <= not_first_bit_of_inter_xhdl10;
rx_inter <= rx_inter_xhdl11;
set_reset_mode <= set_reset_mode_xhdl12;
node_bus_off <= node_bus_off_xhdl13;
error_status <= error_status_xhdl14;
rx_err_cnt <= rx_err_cnt_xhdl15;
tx_err_cnt <= tx_err_cnt_xhdl16;
transmit_status <= transmit_status_xhdl17;
receive_status <= receive_status_xhdl18;
tx_successful <= tx_successful_xhdl19;
need_to_tx <= need_to_tx_xhdl20;
overrun <= overrun_xhdl21;
info_empty <= info_empty_xhdl22;
set_bus_error_irq <= set_bus_error_irq_xhdl23;
set_arbitration_lost_irq <= set_arbitration_lost_irq_xhdl24;
arbitration_lost_capture <= arbitration_lost_capture_xhdl25;
node_error_passive <= node_error_passive_xhdl26;
node_error_active <= node_error_active_xhdl27;
rx_message_counter <= rx_message_counter_xhdl28;
tx <= tx_xhdl29;
tx_next <= tx_next_xhdl30;
bus_off_on <= bus_off_on_xhdl31;
go_overload_frame <= go_overload_frame_xhdl32;
go_error_frame <= go_error_frame_xhdl33;
go_tx <= go_tx_xhdl34;
send_ack <= send_ack_xhdl35;
data_64x8 <= data_64x8_xhdl36;
wren_64x8 <= wren_64x8_xhdl37;
rden_64x8 <= rden_64x8_xhdl38;
wraddress_64x8 <= wraddress_64x8_xhdl39;
rdaddress_64x8 <= rdaddress_64x8_xhdl40;
data_64x4 <= data_64x4_xhdl41;
wren_64x4x1 <= wren_64x4x1_xhdl42;
wraddress_64x4x1 <= wraddress_64x4x1_xhdl43;
rdaddress_64x4x1 <= rdaddress_64x4x1_xhdl44;
data_64x1 <= data_64x1_xhdl45;
-- port connections for Ram
--64x8
w_q_dp_64x8 <= q_dp_64x8 ;
data_64x8_xhdl36 <= w_data_64x8 ;
wren_64x8_xhdl37 <= w_wren_64x8 ;
rden_64x8_xhdl38 <= w_rden_64x8 ;
wraddress_64x8_xhdl39 <= w_wraddress_64x8 ;
rdaddress_64x8_xhdl40 <= w_rdaddress_64x8 ;
--64x4
w_q_dp_64x4 <= q_dp_64x4 ;
data_64x4_xhdl41 <= w_data_64x4 ;
wren_64x4x1_xhdl42 <= w_wren_64x4x1 ;
wraddress_64x4x1_xhdl43 <= w_wraddress_64x4x1 ;
rdaddress_64x4x1_xhdl44 <= w_rdaddress_64x4x1 ;
--64x1
w_q_dp_64x1 <= q_dp_64x1 ;
data_64x1_xhdl45 <= w_data_64x1 ;
-- ----------------------
go_rx_idle <= ((sample_point AND sampled_bit) AND last_bit_of_inter) OR (bus_free AND (NOT node_bus_off_xhdl13)) ;
go_rx_id1 <= (sample_point AND (NOT sampled_bit)) AND (rx_idle_xhdl6 OR last_bit_of_inter) ;
go_rx_rtr1 <= (((NOT bit_de_stuff) AND sample_point) AND rx_id1) AND CONV_STD_LOGIC(bit_cnt(3 DOWNTO 0) = "1010") ;
go_rx_ide <= ((NOT bit_de_stuff) AND sample_point) AND rx_rtr1 ;
go_rx_id2 <= (((NOT bit_de_stuff) AND sample_point) AND rx_ide) AND sampled_bit ;
go_rx_rtr2 <= (((NOT bit_de_stuff) AND sample_point) AND rx_id2) AND CONV_STD_LOGIC(bit_cnt(4 DOWNTO 0) = "10001") ;
go_rx_r1 <= ((NOT bit_de_stuff) AND sample_point) AND rx_rtr2 ;
go_rx_r0 <= ((NOT bit_de_stuff) AND sample_point) AND ((rx_ide AND (NOT sampled_bit)) OR rx_r1) ;
go_rx_dlc <= ((NOT bit_de_stuff) AND sample_point) AND rx_r0 ;
go_rx_data <= (((((NOT bit_de_stuff) AND sample_point) AND rx_dlc) AND CONV_STD_LOGIC(bit_cnt(1 DOWNTO 0) = "11")) AND (sampled_bit OR (orv(data_len(2 DOWNTO 0))))) AND (NOT remote_rq) ;
go_rx_crc <= ((NOT bit_de_stuff) AND sample_point) AND (((rx_dlc AND CONV_STD_LOGIC(bit_cnt(1 DOWNTO 0) = "11")) AND (((NOT sampled_bit) AND (NOT (orv(data_len(2 DOWNTO 0))))) OR remote_rq)) OR (rx_data AND CONV_STD_LOGIC('0' & bit_cnt(5 DOWNTO 0) = ((limited_data_len & "000") - 1)))) ;
go_rx_crc_lim <= (((NOT bit_de_stuff) AND sample_point) AND rx_crc) AND CONV_STD_LOGIC(bit_cnt(3 DOWNTO 0) = "1110") ;
go_rx_ack <= ((NOT bit_de_stuff) AND sample_point) AND rx_crc_lim ;
go_rx_ack_lim <= sample_point AND rx_ack ;
go_rx_eof <= sample_point AND rx_ack_lim ;
go_rx_inter_xhdl9 <= (((sample_point AND rx_eof) AND CONV_STD_LOGIC(eof_cnt = "110")) OR error_frame_ended OR overload_frame_ended) AND (NOT overload_request) ;
go_error_frame_xhdl33 <= form_err OR stuff_err OR bit_err OR ack_err OR (crc_err AND go_rx_eof) ;
error_frame_ended <= CONV_STD_LOGIC(error_cnt2 = "111") AND tx_point ;
overload_frame_ended <= CONV_STD_LOGIC(overload_cnt2 = "111") AND tx_point ;
go_overload_frame_xhdl32 <= (((sample_point AND ((NOT sampled_bit) OR overload_request)) AND (((rx_eof AND (NOT transmitter_xhdl8)) AND CONV_STD_LOGIC(eof_cnt = "110")) OR error_frame_ended OR overload_frame_ended)) OR (((sample_point AND (NOT sampled_bit)) AND rx_inter_xhdl11) AND CONV_STD_LOGIC(bit_cnt(1 DOWNTO 0) < "10")) OR ((sample_point AND (NOT sampled_bit)) AND CONV_STD_LOGIC((error_cnt2 = "111") OR (overload_cnt2 = "111")))) AND (NOT overload_frame_blocked) ;
go_crc_enable <= hard_sync OR go_tx_xhdl34 ;
rst_crc_enable <= go_rx_crc ;
bit_de_stuff_set <= go_rx_id1 AND (NOT go_error_frame_xhdl33) ;
bit_de_stuff_reset <= go_rx_ack OR reset_mode OR go_error_frame_xhdl33 OR go_overload_frame_xhdl32 ;
remote_rq <= ((NOT ide) AND rtr1) OR (ide AND rtr2) ;
temp_xhdl47 <= data_len WHEN (data_len < "1000") ELSE "1000";
limited_data_len <= temp_xhdl47 ;
ack_err <= (((rx_ack AND sample_point) AND sampled_bit) AND tx_state_xhdl2) AND (NOT self_test_mode) ;
bit_err <= ((((((((tx_state_xhdl2 OR error_frame OR overload_frame_xhdl4 OR rx_ack) AND sample_point) AND CONV_STD_LOGIC(tx_xhdl29 /= sampled_bit)) AND (NOT bit_err_exc1)) AND (NOT bit_err_exc2)) AND (NOT bit_err_exc3)) AND (NOT bit_err_exc4)) AND (NOT bit_err_exc5)) AND (NOT bit_err_exc6) ;
bit_err_exc1 <= (tx_state_xhdl2 AND arbitration_field) AND tx_xhdl29 ;
bit_err_exc2 <= rx_ack AND tx_xhdl29 ;
bit_err_exc3 <= (error_frame AND node_error_passive_xhdl26) AND CONV_STD_LOGIC(error_cnt1 < "111") ;
bit_err_exc4 <= ((error_frame AND CONV_STD_LOGIC(error_cnt1 = "111")) AND (NOT enable_error_cnt2)) OR ((overload_frame_xhdl4 AND CONV_STD_LOGIC(overload_cnt1 = "111")) AND (NOT enable_overload_cnt2)) ;
bit_err_exc5 <= (error_frame AND CONV_STD_LOGIC(error_cnt2 = "111")) OR (overload_frame_xhdl4 AND CONV_STD_LOGIC(overload_cnt2 = "111")) ;
bit_err_exc6 <= (CONV_STD_LOGIC(eof_cnt = "110") AND rx_eof) AND (NOT transmitter_xhdl8) ;
arbitration_field <= rx_id1 OR rx_rtr1 OR rx_ide OR rx_id2 OR rx_rtr2 ;
last_bit_of_inter <= rx_inter_xhdl11 AND CONV_STD_LOGIC(bit_cnt(1 DOWNTO 0) = "10") ;
not_first_bit_of_inter_xhdl10 <= rx_inter_xhdl11 AND CONV_STD_LOGIC(bit_cnt(1 DOWNTO 0) /= "00") ;
-- Rx idle state
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rx_idle_xhdl6 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_id1 OR go_error_frame_xhdl33) = '1') THEN
rx_idle_xhdl6 <= '0' ;
ELSE
IF (go_rx_idle = '1') THEN
rx_idle_xhdl6 <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Rx id1 state
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rx_id1 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_rtr1 OR go_error_frame_xhdl33) = '1') THEN
rx_id1 <= '0' ;
ELSE
IF (go_rx_id1 = '1') THEN
rx_id1 <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Rx rtr1 state
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rx_rtr1 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_ide OR go_error_frame_xhdl33) = '1') THEN
rx_rtr1 <= '0' ;
ELSE
IF (go_rx_rtr1 = '1') THEN
rx_rtr1 <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Rx ide state
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rx_ide <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_r0 OR go_rx_id2 OR go_error_frame_xhdl33) = '1') THEN
rx_ide <= '0' ;
ELSE
IF (go_rx_ide = '1') THEN
rx_ide <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Rx id2 state
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rx_id2 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_rtr2 OR go_error_frame_xhdl33) = '1') THEN
rx_id2 <= '0' ;
ELSE
IF (go_rx_id2 = '1') THEN
rx_id2 <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Rx rtr2 state
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rx_rtr2 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_r1 OR go_error_frame_xhdl33) = '1') THEN
rx_rtr2 <= '0' ;
ELSE
IF (go_rx_rtr2 = '1') THEN
rx_rtr2 <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Rx r0 state
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rx_r1 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_r0 OR go_error_frame_xhdl33) = '1') THEN
rx_r1 <= '0' ;
ELSE
IF (go_rx_r1 = '1') THEN
rx_r1 <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Rx r0 state
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rx_r0 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_dlc OR go_error_frame_xhdl33) = '1') THEN
rx_r0 <= '0' ;
ELSE
IF (go_rx_r0 = '1') THEN
rx_r0 <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Rx dlc state
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rx_dlc <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_data OR go_rx_crc OR go_error_frame_xhdl33) = '1') THEN
rx_dlc <= '0' ;
ELSE
IF (go_rx_dlc = '1') THEN
rx_dlc <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Rx data state
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rx_data <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_crc OR go_error_frame_xhdl33) = '1') THEN
rx_data <= '0' ;
ELSE
IF (go_rx_data = '1') THEN
rx_data <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Rx crc state
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rx_crc <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_crc_lim OR go_error_frame_xhdl33) = '1') THEN
rx_crc <= '0' ;
ELSE
IF (go_rx_crc = '1') THEN
rx_crc <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Rx crc delimiter state
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rx_crc_lim <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_ack OR go_error_frame_xhdl33) = '1') THEN
rx_crc_lim <= '0' ;
ELSE
IF (go_rx_crc_lim = '1') THEN
rx_crc_lim <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Rx ack state
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rx_ack <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_ack_lim OR go_error_frame_xhdl33) = '1') THEN
rx_ack <= '0' ;
ELSE
IF (go_rx_ack = '1') THEN
rx_ack <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Rx ack delimiter state
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rx_ack_lim <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_eof OR go_error_frame_xhdl33) = '1') THEN
rx_ack_lim <= '0' ;
ELSE
IF (go_rx_ack_lim = '1') THEN
rx_ack_lim <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Rx eof state
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rx_eof <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_inter_xhdl9 OR go_error_frame_xhdl33 OR go_overload_frame_xhdl32) = '1') THEN
rx_eof <= '0' ;
ELSE
IF (go_rx_eof = '1') THEN
rx_eof <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Interframe space
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rx_inter_xhdl11 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_idle OR go_rx_id1 OR go_overload_frame_xhdl32 OR go_error_frame_xhdl33) = '1') THEN
rx_inter_xhdl11 <= '0' ;
ELSE
IF (go_rx_inter_xhdl9 = '1') THEN
rx_inter_xhdl11 <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- ID register
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
id <= "00000000000000000000000000000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
id <= "00000000000000000000000000000";
ELSE
IF (((sample_point AND (rx_id1 OR rx_id2)) AND (NOT bit_de_stuff)) = '1') THEN
id <= id(27 DOWNTO 0) & sampled_bit ;
END IF;
END IF;
END IF;
END PROCESS;
-- rtr1 bit
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rtr1 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
rtr1 <= '0';
ELSE
IF (((sample_point AND rx_rtr1) AND (NOT bit_de_stuff)) = '1') THEN
rtr1 <= sampled_bit ;
END IF;
END IF;
END IF;
END PROCESS;
-- rtr2 bit
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rtr2 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
rtr2 <= '0';
ELSE
IF (((sample_point AND rx_rtr2) AND (NOT bit_de_stuff)) = '1') THEN
rtr2 <= sampled_bit ;
END IF;
END IF;
END IF;
END PROCESS;
-- ide bit
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
ide <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
ide <= '0';
ELSE
IF (((sample_point AND rx_ide) AND (NOT bit_de_stuff)) = '1') THEN
ide <= sampled_bit ;
END IF;
END IF;
END IF;
END PROCESS;
-- Data length
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
data_len <= "0000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
data_len <= "0000";
ELSE
IF (((sample_point AND rx_dlc) AND (NOT bit_de_stuff)) = '1') THEN
data_len <= data_len(2 DOWNTO 0) & sampled_bit ;
END IF;
END IF;
END IF;
END PROCESS;
-- Data
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
tmp_data <= "00000000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
tmp_data <= "00000000";
ELSE
IF (((sample_point AND rx_data) AND (NOT bit_de_stuff)) = '1') THEN
tmp_data <= tmp_data(6 DOWNTO 0) & sampled_bit ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
write_data_to_tmp_fifo <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
write_data_to_tmp_fifo <= '0';
ELSE
IF ((((sample_point AND rx_data) AND (NOT bit_de_stuff)) AND (andv(bit_cnt(2 DOWNTO 0)))) = '1') THEN
write_data_to_tmp_fifo <= '1' ;
ELSE
write_data_to_tmp_fifo <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
byte_cnt <= "000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
byte_cnt <= "000";
ELSE
IF (write_data_to_tmp_fifo = '1') THEN
byte_cnt <= byte_cnt + "001" ;
ELSE
IF ((sample_point AND go_rx_crc_lim) = '1') THEN
byte_cnt <= "000" ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk = '1') THEN
IF (write_data_to_tmp_fifo = '1') THEN
tmp_fifo(conv_integer(byte_cnt)) <= tmp_data ;
END IF;
END IF;
END PROCESS;
-- CRC
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
crc_in <= "000000000000000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
crc_in <= "000000000000000";
ELSE
IF (((sample_point AND rx_crc) AND (NOT bit_de_stuff)) = '1') THEN
crc_in <= crc_in(13 DOWNTO 0) & sampled_bit ;
END IF;
END IF;
END IF;
END PROCESS;
-- bit_cnt
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
bit_cnt <= "000000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
bit_cnt <= "000000";
ELSE
IF ((go_rx_id1 OR go_rx_id2 OR go_rx_dlc OR go_rx_data OR go_rx_crc OR go_rx_ack OR go_rx_eof OR go_rx_inter_xhdl9 OR go_error_frame_xhdl33 OR go_overload_frame_xhdl32) = '1') THEN
bit_cnt <= "000000" ;
ELSE
IF ((sample_point AND (NOT bit_de_stuff)) = '1') THEN
bit_cnt <= bit_cnt + "000001" ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
-- eof_cnt
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
eof_cnt <= "000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
eof_cnt <= "000";
ELSE
IF (sample_point = '1') THEN
IF ((go_rx_inter_xhdl9 OR go_error_frame_xhdl33 OR go_overload_frame_xhdl32) = '1') THEN
eof_cnt <= "000" ;
ELSE
IF (rx_eof = '1') THEN
eof_cnt <= eof_cnt + "001" ;
END IF;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
-- Enabling bit de-stuffing
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
bit_stuff_cnt_en <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
bit_stuff_cnt_en <= '0';
ELSE
IF (bit_de_stuff_set = '1') THEN
bit_stuff_cnt_en <= '1' ;
ELSE
IF (bit_de_stuff_reset = '1') THEN
bit_stuff_cnt_en <= '0' ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
-- bit_stuff_cnt
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
bit_stuff_cnt <= "001";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
bit_stuff_cnt <= "001";
ELSE
IF (bit_de_stuff_reset = '1') THEN
bit_stuff_cnt <= "001" ;
ELSE
IF ((sample_point AND bit_stuff_cnt_en) = '1') THEN
IF (bit_stuff_cnt = "101") THEN
bit_stuff_cnt <= "001" ;
ELSE
IF (sampled_bit = sampled_bit_q) THEN
bit_stuff_cnt <= bit_stuff_cnt + "001" ;
ELSE
bit_stuff_cnt <= "001" ;
END IF;
END IF;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
-- bit_stuff_cnt_tx
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
bit_stuff_cnt_tx <= "001";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
bit_stuff_cnt_tx <= "001";
ELSE
IF (bit_de_stuff_reset = '1') THEN
bit_stuff_cnt_tx <= "001" ;
ELSE
IF ((tx_point_q AND bit_stuff_cnt_en) = '1') THEN
IF (bit_stuff_cnt_tx = "101") THEN
bit_stuff_cnt_tx <= "001" ;
ELSE
IF (tx_xhdl29 = tx_q) THEN
bit_stuff_cnt_tx <= bit_stuff_cnt_tx + "001" ;
ELSE
bit_stuff_cnt_tx <= "001" ;
END IF;
END IF;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
bit_de_stuff <= CONV_STD_LOGIC(bit_stuff_cnt = "101") ;
bit_de_stuff_tx <= CONV_STD_LOGIC(bit_stuff_cnt_tx = "101") ;
-- stuff_err
stuff_err <= ((sample_point AND bit_stuff_cnt_en) AND bit_de_stuff) AND CONV_STD_LOGIC(sampled_bit = sampled_bit_q) ;
-- Generating delayed signals
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
reset_mode_q <= '0' ;
node_bus_off_q <= '0' ;
ELSIF (clk'EVENT AND clk = '1') THEN
reset_mode_q <= reset_mode ;
node_bus_off_q <= node_bus_off_xhdl13 ;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
crc_enable <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR rst_crc_enable) = '1') THEN
crc_enable <= '0' ;
ELSE
IF (go_crc_enable = '1') THEN
crc_enable <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- CRC error generation
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
crc_err <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR error_frame_ended) = '1') THEN
crc_err <= '0' ;
ELSE
IF (go_rx_ack = '1') THEN
crc_err <= CONV_STD_LOGIC(crc_in /= calculated_crc) ;
END IF;
END IF;
END IF;
END PROCESS;
-- Conditions for form error
form_err <= sample_point AND ((((NOT bit_de_stuff) AND rx_crc_lim) AND (NOT sampled_bit)) OR (rx_ack_lim AND (NOT sampled_bit)) OR (((CONV_STD_LOGIC(eof_cnt < "110") AND rx_eof) AND (NOT sampled_bit)) AND (NOT transmitter_xhdl8)) OR (((rx_eof) AND (NOT sampled_bit)) AND transmitter_xhdl8)) ;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
ack_err_latched <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR error_frame_ended OR go_overload_frame_xhdl32) = '1') THEN
ack_err_latched <= '0' ;
ELSE
IF (ack_err = '1') THEN
ack_err_latched <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
bit_err_latched <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR error_frame_ended OR go_overload_frame_xhdl32) = '1') THEN
bit_err_latched <= '0' ;
ELSE
IF (bit_err = '1') THEN
bit_err_latched <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Rule 5 (Fault confinement).
rule5 <= bit_err AND ((((NOT node_error_passive_xhdl26) AND error_frame) AND CONV_STD_LOGIC(error_cnt1 < "111")) OR (overload_frame_xhdl4 AND CONV_STD_LOGIC(overload_cnt1 < "111"))) ;
-- Rule 3 exception 1 - first part (Fault confinement).
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rule3_exc1_1 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR error_flag_over OR rule3_exc1_2) = '1') THEN
rule3_exc1_1 <= '0' ;
ELSE
IF (((transmitter_xhdl8 AND node_error_passive_xhdl26) AND ack_err) = '1') THEN
rule3_exc1_1 <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Rule 3 exception 1 - second part (Fault confinement).
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rule3_exc1_2 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_error_frame_xhdl33 OR rule3_exc1_2) = '1') THEN
rule3_exc1_2 <= '0' ;
ELSE
IF ((((rule3_exc1_1 AND CONV_STD_LOGIC(error_cnt1 < "111")) AND sample_point) AND (NOT sampled_bit)) = '1') THEN
rule3_exc1_2 <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
stuff_err_latched <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR error_frame_ended OR go_overload_frame_xhdl32) = '1') THEN
stuff_err_latched <= '0' ;
ELSE
IF (stuff_err = '1') THEN
stuff_err_latched <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
form_err_latched <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR error_frame_ended OR go_overload_frame_xhdl32) = '1') THEN
form_err_latched <= '0' ;
ELSE
IF (form_err = '1') THEN
form_err_latched <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
xhdl_49 <= ((crc_enable AND sample_point) AND (NOT bit_de_stuff));
i_can_crc_rx : can_crc
PORT MAP (
clk => clk,
data => sampled_bit,
enable => xhdl_49,
initialize => go_crc_enable,
crc => calculated_crc);
no_byte0 <= rtr1 OR CONV_STD_LOGIC(data_len < "0001") ;
no_byte1 <= rtr1 OR CONV_STD_LOGIC(data_len < "0010") ;
port_xhdl73 <= tmp_fifo(0);
port_xhdl74 <= tmp_fifo(1);
i_can_acf : can_acf
PORT MAP (
clk => clk,
rst => rst,
id => id,
reset_mode => reset_mode,
acceptance_filter_mode => acceptance_filter_mode,
extended_mode => extended_mode,
acceptance_code_0 => acceptance_code_0,
acceptance_mask_0 => acceptance_mask_0,
acceptance_code_1 => acceptance_code_1,
acceptance_code_2 => acceptance_code_2,
acceptance_code_3 => acceptance_code_3,
acceptance_mask_1 => acceptance_mask_1,
acceptance_mask_2 => acceptance_mask_2,
acceptance_mask_3 => acceptance_mask_3,
go_rx_crc_lim => go_rx_crc_lim,
go_rx_inter => go_rx_inter_xhdl9,
go_error_frame => go_error_frame_xhdl33,
data0 => port_xhdl73,
data1 => port_xhdl74,
rtr1 => rtr1,
rtr2 => rtr2,
ide => ide,
no_byte0 => no_byte0,
no_byte1 => no_byte1,
id_ok => id_ok);
temp_xhdl75 <= "101" WHEN ide = '1' ELSE "011";
temp_xhdl76 <= (temp_xhdl75) WHEN extended_mode = '1' ELSE "010";
header_len(2 DOWNTO 0) <= temp_xhdl76 ;
storing_header <= CONV_STD_LOGIC(header_cnt < header_len) ;
temp_xhdl77 <= (data_len - "0001") WHEN (data_len < "1000") ELSE "0111";
temp_xhdl78 <= "1111" WHEN remote_rq = '1' ELSE (temp_xhdl77);
limited_data_len_minus1(3 DOWNTO 0) <= temp_xhdl78 ;
reset_wr_fifo <= CONV_STD_LOGIC(data_cnt = (limited_data_len_minus1 + ('0' & header_len))) OR reset_mode ;
err <= form_err OR stuff_err OR bit_err OR ack_err OR form_err_latched OR stuff_err_latched OR bit_err_latched OR ack_err_latched OR crc_err ;
-- Write enable signal for 64-byte rx fifo
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
wr_fifo <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_wr_fifo = '1') THEN
wr_fifo <= '0' ;
ELSE
IF ((((go_rx_inter_xhdl9 AND id_ok) AND (NOT error_frame_ended)) AND ((NOT tx_state_xhdl2) OR self_rx_request)) = '1') THEN
wr_fifo <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Header counter. Header length depends on the mode of operation and frame format.
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
header_cnt <= "000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_wr_fifo = '1') THEN
header_cnt <= "000" ;
ELSE
IF ((wr_fifo AND storing_header) = '1') THEN
header_cnt <= header_cnt + "001" ;
END IF;
END IF;
END IF;
END PROCESS;
-- Data counter. Length of the data is limited to 8 bytes.
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
data_cnt <= "0000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_wr_fifo = '1') THEN
data_cnt <= "0000" ;
ELSE
IF (wr_fifo = '1') THEN
data_cnt <= data_cnt + "0001" ;
END IF;
END IF;
END IF;
END PROCESS;
-- Multiplexing data that is stored to 64-byte fifo depends on the mode of operation and frame format
PROCESS (extended_mode, ide, data_cnt, header_cnt, header_len, storing_header, id, rtr1, rtr2, data_len, tmp_fifo)
VARIABLE data_for_fifo_xhdl79 : std_logic_vector(7 DOWNTO 0);
VARIABLE temp_xhdl80 : std_logic_vector(5 DOWNTO 0);
BEGIN
temp_xhdl80 := storing_header & extended_mode & ide & header_cnt;
IF (std_match(temp_xhdl80, "111000")) THEN
data_for_fifo_xhdl79 := '1' & rtr2 & "00" & data_len; -- extended mode, extended format header
ELSIF (std_match(temp_xhdl80, "111001")) THEN
data_for_fifo_xhdl79 := id(28 DOWNTO 21); -- extended mode, extended format header
ELSIF (std_match(temp_xhdl80, "111010")) THEN
data_for_fifo_xhdl79 := id(20 DOWNTO 13); -- extended mode, extended format header
ELSIF (std_match(temp_xhdl80, "111011")) THEN
data_for_fifo_xhdl79 := id(12 DOWNTO 5); -- extended mode, extended format header
ELSIF (std_match(temp_xhdl80, "111100")) THEN
data_for_fifo_xhdl79 := id(4 DOWNTO 0) & rtr2 & "00"; -- extended mode, extended format header
ELSIF (std_match(temp_xhdl80, "110000")) THEN
data_for_fifo_xhdl79 := '0' & rtr1 & "00" & data_len; -- extended mode, standard format header
ELSIF (std_match(temp_xhdl80, "110001")) THEN
data_for_fifo_xhdl79 := id(10 DOWNTO 3); -- extended mode, standard format header
ELSIF (std_match(temp_xhdl80, "110010")) THEN
data_for_fifo_xhdl79 := id(2 DOWNTO 0) & rtr1 & "0000"; -- extended mode, standard format header
ELSIF (std_match(temp_xhdl80, "10-000")) THEN
data_for_fifo_xhdl79 := id(10 DOWNTO 3); -- normal mode header
ELSIF (std_match(temp_xhdl80, "10-001")) THEN
data_for_fifo_xhdl79 := id(2 DOWNTO 0) & rtr1 & data_len; -- normal mode header
ELSE
data_for_fifo_xhdl79 := tmp_fifo(conv_integer(data_cnt - ('0' & header_len)) mod 8); -- data
END IF;
data_for_fifo <= data_for_fifo_xhdl79;
END PROCESS;
-- Instantiation of the RX fifo module
-- port connections for Ram
--64x8
--64x4
--64x1
i_can_fifo : can_fifo
PORT MAP (
clk => clk,
rst => rst,
wr => wr_fifo,
data_in => data_for_fifo,
addr => addr(5 DOWNTO 0),
data_out => data_out_xhdl1,
fifo_selected => fifo_selected,
reset_mode => reset_mode,
release_buffer => release_buffer,
extended_mode => extended_mode,
overrun => overrun_xhdl21,
info_empty => info_empty_xhdl22,
info_cnt => rx_message_counter_xhdl28,
q_dp_64x8 => w_q_dp_64x8,
data_64x8 => w_data_64x8,
wren_64x8 => w_wren_64x8,
rden_64x8 => w_rden_64x8,
wraddress_64x8 => w_wraddress_64x8,
rdaddress_64x8 => w_rdaddress_64x8,
q_dp_64x4 => w_q_dp_64x4,
data_64x4 => w_data_64x4,
wren_64x4x1 => w_wren_64x4x1,
wraddress_64x4x1 => w_wraddress_64x4x1,
rdaddress_64x4x1 => w_rdaddress_64x4x1,
q_dp_64x1 => w_q_dp_64x1,
data_64x1 => w_data_64x1);
-- Transmitting error frame.
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
error_frame <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR error_frame_ended OR go_overload_frame_xhdl32) = '1') THEN
error_frame <= '0' ;
ELSE
IF (go_error_frame_xhdl33 = '1') THEN
error_frame <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
error_cnt1 <= "000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR error_frame_ended OR go_error_frame_xhdl33 OR go_overload_frame_xhdl32) = '1') THEN
error_cnt1 <= "000" ;
ELSE
IF (((error_frame AND tx_point) AND CONV_STD_LOGIC(error_cnt1 < "111")) = '1') THEN
error_cnt1 <= error_cnt1 + "001" ;
END IF;
END IF;
END IF;
END PROCESS;
error_flag_over <= ((((NOT node_error_passive_xhdl26) AND sample_point) AND CONV_STD_LOGIC(error_cnt1 = "111")) OR ((node_error_passive_xhdl26 AND sample_point) AND CONV_STD_LOGIC(passive_cnt = "110"))) AND (NOT enable_error_cnt2) ;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
error_flag_over_latched <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR error_frame_ended OR go_error_frame_xhdl33 OR go_overload_frame_xhdl32) = '1') THEN
error_flag_over_latched <= '0' ;
ELSE
IF (error_flag_over = '1') THEN
error_flag_over_latched <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
enable_error_cnt2 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR error_frame_ended OR go_error_frame_xhdl33 OR go_overload_frame_xhdl32) = '1') THEN
enable_error_cnt2 <= '0' ;
ELSE
IF ((error_frame AND (error_flag_over AND sampled_bit)) = '1') THEN
enable_error_cnt2 <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
error_cnt2 <= "000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR error_frame_ended OR go_error_frame_xhdl33 OR go_overload_frame_xhdl32) = '1') THEN
error_cnt2 <= "000" ;
ELSE
IF ((enable_error_cnt2 AND tx_point) = '1') THEN
error_cnt2 <= error_cnt2 + "001" ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
delayed_dominant_cnt <= "000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR enable_error_cnt2 OR go_error_frame_xhdl33 OR enable_overload_cnt2 OR go_overload_frame_xhdl32) = '1') THEN
delayed_dominant_cnt <= "000" ;
ELSE
IF (((sample_point AND (NOT sampled_bit)) AND CONV_STD_LOGIC((error_cnt1 = "111") OR (overload_cnt1 = "111"))) = '1') THEN
delayed_dominant_cnt <= delayed_dominant_cnt + "001" ;
END IF;
END IF;
END IF;
END PROCESS;
-- passive_cnt
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
passive_cnt <= "001";
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR error_frame_ended OR go_error_frame_xhdl33 OR go_overload_frame_xhdl32 OR first_compare_bit) = '1') THEN
passive_cnt <= "001" ;
ELSE
IF ((sample_point AND CONV_STD_LOGIC(passive_cnt < "110")) = '1') THEN
IF (((error_frame AND (NOT enable_error_cnt2)) AND CONV_STD_LOGIC(sampled_bit = sampled_bit_q)) = '1') THEN
passive_cnt <= passive_cnt + "001" ;
ELSE
passive_cnt <= "001" ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
-- When comparing 6 equal bits, first is always equal
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
first_compare_bit <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (go_error_frame_xhdl33 = '1') THEN
first_compare_bit <= '1' ;
ELSE
IF (sample_point = '1') THEN
first_compare_bit <= '0';
END IF;
END IF;
END IF;
END PROCESS;
-- Transmitting overload frame.
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
overload_frame_xhdl4 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR overload_frame_ended OR go_error_frame_xhdl33) = '1') THEN
overload_frame_xhdl4 <= '0' ;
ELSE
IF (go_overload_frame_xhdl32 = '1') THEN
overload_frame_xhdl4 <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
overload_cnt1 <= "000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR overload_frame_ended OR go_error_frame_xhdl33 OR go_overload_frame_xhdl32) = '1') THEN
overload_cnt1 <= "000" ;
ELSE
IF (((overload_frame_xhdl4 AND tx_point) AND CONV_STD_LOGIC(overload_cnt1 < "111")) = '1') THEN
overload_cnt1 <= overload_cnt1 + "001" ;
END IF;
END IF;
END IF;
END PROCESS;
overload_flag_over <= (sample_point AND CONV_STD_LOGIC(overload_cnt1 = "111")) AND (NOT enable_overload_cnt2) ;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
enable_overload_cnt2 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR overload_frame_ended OR go_error_frame_xhdl33 OR go_overload_frame_xhdl32) = '1') THEN
enable_overload_cnt2 <= '0' ;
ELSE
IF ((overload_frame_xhdl4 AND (overload_flag_over AND sampled_bit)) = '1') THEN
enable_overload_cnt2 <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
overload_cnt2 <= "000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR overload_frame_ended OR go_error_frame_xhdl33 OR go_overload_frame_xhdl32) = '1') THEN
overload_cnt2 <= "000" ;
ELSE
IF ((enable_overload_cnt2 AND tx_point) = '1') THEN
overload_cnt2 <= overload_cnt2 + "001" ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
overload_request_cnt <= "00";
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_error_frame_xhdl33 OR go_rx_id1) = '1') THEN
overload_request_cnt <= "00" ;
ELSE
IF ((overload_request AND overload_frame_xhdl4) = '1') THEN
overload_request_cnt <= overload_request_cnt + "01" ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
overload_frame_blocked <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_error_frame_xhdl33 OR go_rx_id1) = '1') THEN
overload_frame_blocked <= '0' ;
ELSE
IF (((overload_request AND overload_frame_xhdl4) AND CONV_STD_LOGIC(overload_request_cnt = "10")) = '1') THEN
-- This is a second sequential overload_request
overload_frame_blocked <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
send_ack_xhdl35 <= (((NOT tx_state_xhdl2) AND rx_ack) AND (NOT err)) AND (NOT listen_only_mode) ;
PROCESS (reset_mode, node_bus_off_xhdl13, tx_state_xhdl2, go_tx_xhdl34, bit_de_stuff_tx, tx_bit, tx_q, send_ack_xhdl35, go_overload_frame_xhdl32, overload_frame_xhdl4, overload_cnt1, go_error_frame_xhdl33, error_frame, error_cnt1, node_error_passive_xhdl26)
VARIABLE tx_next_xhdl30_xhdl105 : std_logic;
BEGIN
IF ((reset_mode OR node_bus_off_xhdl13) = '1') THEN
-- Reset or node_bus_off
tx_next_xhdl30_xhdl105 := '1';
ELSE
IF ((go_error_frame_xhdl33 OR error_frame) = '1') THEN
-- Transmitting error frame
IF (error_cnt1 < "110") THEN
IF (node_error_passive_xhdl26 = '1') THEN
tx_next_xhdl30_xhdl105 := '1';
ELSE
tx_next_xhdl30_xhdl105 := '0';
END IF;
ELSE
tx_next_xhdl30_xhdl105 := '1';
END IF;
ELSE
IF ((go_overload_frame_xhdl32 OR overload_frame_xhdl4) = '1') THEN
-- Transmitting overload frame
IF (overload_cnt1 < "110") THEN
tx_next_xhdl30_xhdl105 := '0';
ELSE
tx_next_xhdl30_xhdl105 := '1';
END IF;
ELSE
IF ((go_tx_xhdl34 OR tx_state_xhdl2) = '1') THEN
-- Transmitting message
tx_next_xhdl30_xhdl105 := ((NOT bit_de_stuff_tx) AND tx_bit) OR (bit_de_stuff_tx AND (NOT tx_q));
ELSE
IF (send_ack_xhdl35 = '1') THEN
-- Acknowledge
tx_next_xhdl30_xhdl105 := '0';
ELSE
tx_next_xhdl30_xhdl105 := '1';
END IF;
END IF;
END IF;
END IF;
END IF;
tx_next_xhdl30 <= tx_next_xhdl30_xhdl105;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
tx_xhdl29 <= '1';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
tx_xhdl29 <= '1';
ELSE
IF (tx_point = '1') THEN
tx_xhdl29 <= tx_next_xhdl30 ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
tx_q <= '0' ;
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
tx_q <= '0' ;
ELSE
IF (tx_point = '1') THEN
tx_q <= tx_xhdl29 AND (NOT go_early_tx_latched) ;
END IF;
END IF;
END IF;
END PROCESS;
-- Delayed tx point
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
tx_point_q <= '0' ;
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
tx_point_q <= '0' ;
ELSE
tx_point_q <= tx_point ;
END IF;
END IF;
END PROCESS;
-- Changing bit order from [7:0] to [0:7]
i_ibo_tx_data_0 : can_ibo
PORT MAP (
di => tx_data_0,
do => r_tx_data_0);
i_ibo_tx_data_1 : can_ibo
PORT MAP (
di => tx_data_1,
do => r_tx_data_1);
i_ibo_tx_data_2 : can_ibo
PORT MAP (
di => tx_data_2,
do => r_tx_data_2);
i_ibo_tx_data_3 : can_ibo
PORT MAP (
di => tx_data_3,
do => r_tx_data_3);
i_ibo_tx_data_4 : can_ibo
PORT MAP (
di => tx_data_4,
do => r_tx_data_4);
i_ibo_tx_data_5 : can_ibo
PORT MAP (
di => tx_data_5,
do => r_tx_data_5);
i_ibo_tx_data_6 : can_ibo
PORT MAP (
di => tx_data_6,
do => r_tx_data_6);
i_ibo_tx_data_7 : can_ibo
PORT MAP (
di => tx_data_7,
do => r_tx_data_7);
i_ibo_tx_data_8 : can_ibo
PORT MAP (
di => tx_data_8,
do => r_tx_data_8);
i_ibo_tx_data_9 : can_ibo
PORT MAP (
di => tx_data_9,
do => r_tx_data_9);
i_ibo_tx_data_10 : can_ibo
PORT MAP (
di => tx_data_10,
do => r_tx_data_10);
i_ibo_tx_data_11 : can_ibo
PORT MAP (
di => tx_data_11,
do => r_tx_data_11);
i_ibo_tx_data_12 : can_ibo
PORT MAP (
di => tx_data_12,
do => r_tx_data_12);
-- Changing bit order from [14:0] to [0:14]
i_calculated_crc0 : can_ibo
PORT MAP (
di => calculated_crc(14 DOWNTO 7),
do => r_calculated_crc(7 DOWNTO 0));
xhdl_106 <= calculated_crc(6 DOWNTO 0) & '0';
i_calculated_crc1 : can_ibo
PORT MAP (
di => xhdl_106,
do => r_calculated_crc(15 DOWNTO 8));
basic_chain <= r_tx_data_1(7 DOWNTO 4) & "00" & r_tx_data_1(3 DOWNTO 0) & r_tx_data_0(7 DOWNTO 0) & '0' ;
basic_chain_data <= r_tx_data_9 & r_tx_data_8 & r_tx_data_7 & r_tx_data_6 & r_tx_data_5 & r_tx_data_4 & r_tx_data_3 & r_tx_data_2 ;
extended_chain_std <= r_tx_data_0(7 DOWNTO 4) & "00" & r_tx_data_0(1) & r_tx_data_2(2 DOWNTO 0) & r_tx_data_1(7 DOWNTO 0) & '0' ;
extended_chain_ext <= r_tx_data_0(7 DOWNTO 4) & "00" & r_tx_data_0(1) & r_tx_data_4(4 DOWNTO 0) & r_tx_data_3(7 DOWNTO 0) & r_tx_data_2(7 DOWNTO 3) & '1' & '1' & r_tx_data_2(2 DOWNTO 0) & r_tx_data_1(7 DOWNTO 0) & '0' ;
extended_chain_data_std <= r_tx_data_10 & r_tx_data_9 & r_tx_data_8 & r_tx_data_7 & r_tx_data_6 & r_tx_data_5 & r_tx_data_4 & r_tx_data_3 ;
extended_chain_data_ext <= r_tx_data_12 & r_tx_data_11 & r_tx_data_10 & r_tx_data_9 & r_tx_data_8 & r_tx_data_7 & r_tx_data_6 & r_tx_data_5 ;
PROCESS (extended_mode, rx_data, tx_pointer, extended_chain_data_std, extended_chain_data_ext, rx_crc, r_calculated_crc, r_tx_data_0, extended_chain_ext, extended_chain_std, basic_chain_data, basic_chain, finish_msg)
VARIABLE tx_bit_xhdl107 : std_logic;
BEGIN
IF (extended_mode = '1') THEN
IF (rx_data = '1') THEN
-- data stage
IF (r_tx_data_0(0) = '1') THEN
-- Extended frame
tx_bit_xhdl107 := extended_chain_data_ext(conv_integer(tx_pointer));
ELSE
tx_bit_xhdl107 := extended_chain_data_std(conv_integer(tx_pointer));
END IF;
ELSE
IF (rx_crc = '1') THEN
tx_bit_xhdl107 := r_calculated_crc(conv_integer(tx_pointer(3 downto 0)));
ELSE
IF (finish_msg = '1') THEN
tx_bit_xhdl107 := '1';
ELSE
IF (r_tx_data_0(0) = '1') THEN
-- Extended frame
tx_bit_xhdl107 := extended_chain_ext(conv_integer(tx_pointer));
ELSE
tx_bit_xhdl107 := extended_chain_std(conv_integer(tx_pointer));
END IF;
END IF;
END IF;
END IF;
ELSE
-- Basic mode
IF (rx_data = '1') THEN
-- data stage
tx_bit_xhdl107 := basic_chain_data(conv_integer(tx_pointer));
ELSE
IF (rx_crc = '1') THEN
tx_bit_xhdl107 := r_calculated_crc(conv_integer(tx_pointer));
ELSE
IF (finish_msg = '1') THEN
tx_bit_xhdl107 := '1';
ELSE
tx_bit_xhdl107 := basic_chain(conv_integer(tx_pointer));
END IF;
END IF;
END IF;
END IF;
tx_bit <= tx_bit_xhdl107;
END PROCESS;
temp_xhdl108 <= "111111" WHEN tx_data_0(3) = '1' ELSE ((tx_data_0(2 DOWNTO 0) & "000") - 1);
limited_tx_cnt_ext <= temp_xhdl108 ;
temp_xhdl109 <= "111111" WHEN tx_data_1(3) = '1' ELSE ((tx_data_1(2 DOWNTO 0) & "000") - 1);
limited_tx_cnt_std <= temp_xhdl109 ;
-- arbitration + control for extended format
-- arbitration + control for extended format
-- arbitration + control for standard format
-- data (overflow is OK here)
-- data (overflow is OK here)
-- crc
-- at the end
rst_tx_pointer <= ((((((NOT bit_de_stuff_tx) AND tx_point) AND (NOT rx_data)) AND extended_mode) AND r_tx_data_0(0)) AND CONV_STD_LOGIC(tx_pointer = "100110")) OR ((((((NOT bit_de_stuff_tx) AND tx_point) AND (NOT rx_data)) AND extended_mode) AND (NOT r_tx_data_0(0))) AND CONV_STD_LOGIC(tx_pointer = "010010")) OR (((((NOT bit_de_stuff_tx) AND tx_point) AND (NOT rx_data)) AND (NOT extended_mode)) AND CONV_STD_LOGIC(tx_pointer = "010010")) OR (((((NOT bit_de_stuff_tx) AND tx_point) AND rx_data) AND extended_mode) AND CONV_STD_LOGIC(tx_pointer = limited_tx_cnt_ext)) OR (((((NOT bit_de_stuff_tx) AND tx_point) AND rx_data) AND (NOT extended_mode)) AND CONV_STD_LOGIC(tx_pointer = limited_tx_cnt_std)) OR (tx_point AND rx_crc_lim) OR (go_rx_idle) OR (reset_mode) OR (overload_frame_xhdl4) OR (error_frame) ;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
tx_pointer <= "000000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (rst_tx_pointer = '1') THEN
tx_pointer <= "000000" ;
ELSE
IF ((go_early_tx OR ((tx_point AND (tx_state_xhdl2 OR go_tx_xhdl34)) AND (NOT bit_de_stuff_tx))) = '1') THEN
tx_pointer <= tx_pointer + "000001" ;
END IF;
END IF;
END IF;
END PROCESS;
tx_successful_xhdl19 <= ((((transmitter_xhdl8 AND go_rx_inter_xhdl9) AND (NOT go_error_frame_xhdl33)) AND (NOT error_frame_ended)) AND (NOT overload_frame_ended)) AND (NOT arbitration_lost) ;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
need_to_tx_xhdl20 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((tx_successful_xhdl19 OR reset_mode OR (abort_tx AND (NOT transmitting_xhdl7)) OR (((NOT tx_state_xhdl2) AND tx_state_q_xhdl3) AND single_shot_transmission)) = '1') THEN
need_to_tx_xhdl20 <= '0' ;
ELSE
IF ((tx_request AND sample_point) = '1') THEN
need_to_tx_xhdl20 <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
go_early_tx <= ((((((NOT listen_only_mode) AND need_to_tx_xhdl20) AND (NOT tx_state_xhdl2)) AND (NOT suspend OR CONV_STD_LOGIC(susp_cnt = "111"))) AND sample_point) AND (NOT sampled_bit)) AND (rx_idle_xhdl6 OR last_bit_of_inter) ;
go_tx_xhdl34 <= ((((NOT listen_only_mode) AND need_to_tx_xhdl20) AND (NOT tx_state_xhdl2)) AND (NOT suspend OR (sample_point AND CONV_STD_LOGIC(susp_cnt = "111")))) AND (go_early_tx OR rx_idle_xhdl6) ;
-- go_early_tx latched (for proper bit_de_stuff generation)
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
go_early_tx_latched <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR tx_point) = '1') THEN
go_early_tx_latched <= '0' ;
ELSE
IF (go_early_tx = '1') THEN
go_early_tx_latched <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Tx state
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
tx_state_xhdl2 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR go_rx_inter_xhdl9 OR error_frame OR arbitration_lost) = '1') THEN
tx_state_xhdl2 <= '0' ;
ELSE
IF (go_tx_xhdl34 = '1') THEN
tx_state_xhdl2 <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
tx_state_q_xhdl3 <= '0' ;
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
tx_state_q_xhdl3 <= '0' ;
ELSE
tx_state_q_xhdl3 <= tx_state_xhdl2 ;
END IF;
END IF;
END PROCESS;
-- Node is a transmitter
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
transmitter_xhdl8 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (go_tx_xhdl34 = '1') THEN
transmitter_xhdl8 <= '1' ;
ELSE
IF ((reset_mode OR go_rx_idle OR (suspend AND go_rx_id1)) = '1') THEN
transmitter_xhdl8 <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
-- Signal "transmitting" signals that the core is a transmitting (message, error frame or overload frame). No synchronization is done meanwhile.
-- Node might be both transmitter or receiver (sending error or overload frame)
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
transmitting_xhdl7 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((go_error_frame_xhdl33 OR go_overload_frame_xhdl32 OR go_tx_xhdl34 OR send_ack_xhdl35) = '1') THEN
transmitting_xhdl7 <= '1' ;
ELSE
IF ((reset_mode OR go_rx_idle OR (go_rx_id1 AND (NOT tx_state_xhdl2)) OR (arbitration_lost AND tx_state_xhdl2)) = '1') THEN
transmitting_xhdl7 <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
suspend <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR (sample_point AND CONV_STD_LOGIC(susp_cnt = "111"))) = '1') THEN
suspend <= '0' ;
ELSE
IF (((not_first_bit_of_inter_xhdl10 AND transmitter_xhdl8) AND node_error_passive_xhdl26) = '1') THEN
suspend <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
susp_cnt_en <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR (sample_point AND CONV_STD_LOGIC(susp_cnt = "111"))) = '1') THEN
susp_cnt_en <= '0' ;
ELSE
IF (((suspend AND sample_point) AND last_bit_of_inter) = '1') THEN
susp_cnt_en <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
susp_cnt <= "000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR (sample_point AND CONV_STD_LOGIC(susp_cnt = "111"))) = '1') THEN
susp_cnt <= "000" ;
ELSE
IF ((susp_cnt_en AND sample_point) = '1') THEN
susp_cnt <= susp_cnt + "001" ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
finish_msg <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((go_rx_idle OR go_rx_id1 OR error_frame OR reset_mode) = '1') THEN
finish_msg <= '0' ;
ELSE
IF (go_rx_crc_lim = '1') THEN
finish_msg <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
arbitration_lost <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((go_rx_idle OR error_frame_ended OR reset_mode) = '1') THEN
arbitration_lost <= '0' ;
ELSE
IF (((((transmitter_xhdl8 AND sample_point) AND tx_xhdl29) AND arbitration_field) AND NOT sampled_bit) = '1') THEN
arbitration_lost <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
arbitration_lost_q <= '0' ;
read_arbitration_lost_capture_reg_q <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
arbitration_lost_q <= '0';
read_arbitration_lost_capture_reg_q <= '0';
ELSE
arbitration_lost_q <= arbitration_lost;
read_arbitration_lost_capture_reg_q <= read_arbitration_lost_capture_reg ;
END IF;
END IF;
END PROCESS;
set_arbitration_lost_irq_xhdl24 <= (arbitration_lost AND (NOT arbitration_lost_q)) AND (NOT arbitration_blocked) ;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
read_error_code_capture_reg_q <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
read_error_code_capture_reg_q <= read_error_code_capture_reg;
END IF;
END PROCESS;
reset_error_code_capture_reg <= read_error_code_capture_reg_q and not read_error_code_capture_reg;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
arbitration_cnt_en <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR arbitration_blocked) = '1') THEN
arbitration_cnt_en <= '0' ;
ELSE
IF (((rx_id1 AND sample_point) AND (NOT arbitration_blocked)) = '1') THEN
arbitration_cnt_en <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
arbitration_blocked <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((reset_mode OR read_arbitration_lost_capture_reg) = '1') THEN
arbitration_blocked <= '0' ;
ELSE
IF (set_arbitration_lost_irq_xhdl24 = '1') THEN
arbitration_blocked <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
arbitration_lost_capture_xhdl25 <= "00000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (read_arbitration_lost_capture_reg_q = '1') THEN
arbitration_lost_capture_xhdl25 <= "00000" ;
ELSE
IF ((((sample_point AND (NOT arbitration_blocked)) AND arbitration_cnt_en) AND (NOT bit_de_stuff)) = '1') THEN
arbitration_lost_capture_xhdl25 <= arbitration_lost_capture_xhdl25 + "00001" ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
rx_err_cnt_xhdl15 <= "000000000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((we_rx_err_cnt AND (NOT node_bus_off_xhdl13)) = '1') THEN
rx_err_cnt_xhdl15 <= '0' & data_in ;
ELSE
IF (set_reset_mode_xhdl12 = '1') THEN
rx_err_cnt_xhdl15 <= "000000000" ;
ELSE
IF (((NOT listen_only_mode) AND (NOT transmitter_xhdl8 OR arbitration_lost)) = '1') THEN
IF ((((go_rx_ack_lim AND (NOT go_error_frame_xhdl33)) AND (NOT crc_err)) AND CONV_STD_LOGIC(rx_err_cnt_xhdl15 > "000000000")) = '1') THEN
IF (rx_err_cnt_xhdl15 > "001111111") THEN
rx_err_cnt_xhdl15 <= "001111111" ;
ELSE
rx_err_cnt_xhdl15 <= rx_err_cnt_xhdl15 - "000000001" ;
END IF;
ELSE
IF (rx_err_cnt_xhdl15 < "010000000") THEN
IF ((go_error_frame_xhdl33 AND (NOT rule5)) = '1') THEN
-- 1 (rule 5 is just the opposite then rule 1 exception
rx_err_cnt_xhdl15 <= rx_err_cnt_xhdl15 + "000000001" ;
ELSE
IF ((((((error_flag_over AND (NOT error_flag_over_latched)) AND sample_point) AND (NOT sampled_bit)) AND CONV_STD_LOGIC(error_cnt1 = "111")) OR (go_error_frame_xhdl33 AND rule5) OR ((sample_point AND (NOT sampled_bit)) AND CONV_STD_LOGIC(delayed_dominant_cnt = "111"))) = '1') THEN
-- 2
-- 5
-- 6
rx_err_cnt_xhdl15 <= rx_err_cnt_xhdl15 + "000001000" ;
END IF;
END IF;
END IF;
END IF;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
tx_err_cnt_xhdl16 <= "000000000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (we_tx_err_cnt = '1') THEN
tx_err_cnt_xhdl16 <= '0' & data_in ;
ELSE
IF (set_reset_mode_xhdl12 = '1') THEN
tx_err_cnt_xhdl16 <= "010000000" ;
ELSE
IF ((CONV_STD_LOGIC(tx_err_cnt_xhdl16 > "000000000") AND (tx_successful_xhdl19 OR bus_free)) = '1') THEN
tx_err_cnt_xhdl16 <= tx_err_cnt_xhdl16 - "000000001" ;
ELSE
IF ((transmitter_xhdl8 AND (NOT arbitration_lost)) = '1') THEN
IF ((((sample_point AND (NOT sampled_bit)) AND CONV_STD_LOGIC(delayed_dominant_cnt = "111")) OR (go_error_frame_xhdl33 AND rule5) OR ((go_error_frame_xhdl33 AND (NOT ((transmitter_xhdl8 AND node_error_passive_xhdl26) AND ack_err))) AND (NOT (((((transmitter_xhdl8 AND stuff_err) AND arbitration_field) AND sample_point) AND tx_xhdl29) AND (NOT sampled_bit)))) OR (error_frame AND rule3_exc1_2)) = '1') THEN
-- 6
-- 4 (rule 5 is the same as rule 4)
-- 3
-- 3
tx_err_cnt_xhdl16 <= tx_err_cnt_xhdl16 + "000001000" ;
END IF;
END IF;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
node_error_passive_xhdl26 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((rx_err_cnt_xhdl15 < "010000000") AND (tx_err_cnt_xhdl16 < "010000000")) THEN
node_error_passive_xhdl26 <= '0' ;
ELSE
IF (((CONV_STD_LOGIC((rx_err_cnt_xhdl15 >= "010000000") OR (tx_err_cnt_xhdl16 >= "010000000")) AND (error_frame_ended OR go_error_frame_xhdl33 OR ((NOT reset_mode) AND reset_mode_q))) AND (NOT node_bus_off_xhdl13)) = '1') THEN
node_error_passive_xhdl26 <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
node_error_active_xhdl27 <= NOT (node_error_passive_xhdl26 OR node_bus_off_xhdl13) ;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
node_bus_off_xhdl13 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (((CONV_STD_LOGIC((rx_err_cnt_xhdl15 = "000000000") AND (tx_err_cnt_xhdl16 = "000000000")) AND (NOT reset_mode)) OR (we_tx_err_cnt AND CONV_STD_LOGIC(data_in < "11111111"))) = '1') THEN
node_bus_off_xhdl13 <= '0' ;
ELSE
IF ((CONV_STD_LOGIC(tx_err_cnt_xhdl16 >= "100000000") OR (we_tx_err_cnt AND CONV_STD_LOGIC(data_in = "11111111"))) = '1') THEN
node_bus_off_xhdl13 <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
bus_free_cnt <= "0000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
bus_free_cnt <= "0000" ;
ELSE
IF (sample_point = '1') THEN
IF (((sampled_bit AND bus_free_cnt_en) AND CONV_STD_LOGIC(bus_free_cnt < "1010")) = '1') THEN
bus_free_cnt <= bus_free_cnt + "0001" ;
ELSE
bus_free_cnt <= "0000" ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
bus_free_cnt_en <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ((((NOT reset_mode) AND reset_mode_q) OR (node_bus_off_q AND (NOT reset_mode))) = '1') THEN
bus_free_cnt_en <= '1' ;
ELSE
IF ((((sample_point AND sampled_bit) AND CONV_STD_LOGIC(bus_free_cnt = "1010")) AND (NOT node_bus_off_xhdl13)) = '1') THEN
bus_free_cnt_en <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
bus_free <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
bus_free <= '0';
ELSE
IF (((sample_point AND sampled_bit) AND CONV_STD_LOGIC(bus_free_cnt = "1010")) = '1') THEN
bus_free <= '1' ;
ELSE
bus_free <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
waiting_for_bus_free <= '1';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_mode = '1') THEN
waiting_for_bus_free <= '1';
ELSE
IF ((bus_free AND (NOT node_bus_off_xhdl13)) = '1') THEN
waiting_for_bus_free <= '0' ;
ELSE
IF ((((NOT reset_mode) AND reset_mode_q) OR (node_bus_off_q AND (NOT reset_mode))) = '1') THEN
waiting_for_bus_free <= '1' ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
bus_off_on_xhdl31 <= NOT node_bus_off_xhdl13 ;
set_reset_mode_xhdl12 <= node_bus_off_xhdl13 AND (NOT node_bus_off_q) ;
temp_xhdl110 <= ((rx_err_cnt_xhdl15 >= ('0' & error_warning_limit)) OR (tx_err_cnt_xhdl16 >= ('0' & error_warning_limit))) WHEN extended_mode = '1' ELSE ((rx_err_cnt_xhdl15 >= "001100000") OR (tx_err_cnt_xhdl16 >= "001100000"));
error_status_xhdl14 <= CONV_STD_LOGIC(temp_xhdl110) ;
transmit_status_xhdl17 <= transmitting_xhdl7 OR (extended_mode AND waiting_for_bus_free) ;
temp_xhdl111 <= (waiting_for_bus_free OR ((NOT rx_idle_xhdl6) AND (NOT transmitting_xhdl7))) WHEN extended_mode = '1' ELSE (((NOT waiting_for_bus_free) AND (NOT rx_idle_xhdl6)) AND (NOT transmitting_xhdl7));
receive_status_xhdl18 <= temp_xhdl111 ;
-- Error code capture register
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
error_capture_code_xhdl5 <= "00000000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (reset_error_code_capture_reg = '1') THEN
error_capture_code_xhdl5 <= "00000000" ;
ELSE
IF (set_bus_error_irq_xhdl23 = '1') THEN
error_capture_code_xhdl5 <= error_capture_code_type(7 DOWNTO 6) & error_capture_code_direction & error_capture_code_segment(4 DOWNTO 0) ;
END IF;
END IF;
END IF;
END PROCESS;
error_capture_code_segment(0) <= rx_idle_xhdl6 OR rx_ide OR (rx_id2 AND CONV_STD_LOGIC(bit_cnt < "001101")) OR rx_r1 OR rx_r0 OR rx_dlc OR rx_ack OR rx_ack_lim OR (error_frame AND node_error_active_xhdl27) ;
error_capture_code_segment(1) <= rx_idle_xhdl6 OR rx_id1 OR rx_id2 OR rx_dlc OR rx_data OR rx_ack_lim OR rx_eof OR rx_inter_xhdl11 OR (error_frame AND node_error_passive_xhdl26) ;
error_capture_code_segment(2) <= (rx_id1 AND CONV_STD_LOGIC(bit_cnt > "000111")) OR rx_rtr1 OR rx_ide OR rx_id2 OR rx_rtr2 OR rx_r1 OR (error_frame AND node_error_passive_xhdl26) OR overload_frame_xhdl4 ;
error_capture_code_segment(3) <= (rx_id2 AND CONV_STD_LOGIC(bit_cnt > "000100")) OR rx_rtr2 OR rx_r1 OR rx_r0 OR rx_dlc OR rx_data OR rx_crc OR rx_crc_lim OR rx_ack OR rx_ack_lim OR rx_eof OR overload_frame_xhdl4 ;
error_capture_code_segment(4) <= rx_crc_lim OR rx_ack OR rx_ack_lim OR rx_eof OR rx_inter_xhdl11 OR error_frame OR overload_frame_xhdl4 ;
error_capture_code_direction <= NOT transmitting_xhdl7 ;
PROCESS (bit_err, form_err, stuff_err)
VARIABLE error_capture_code_type_xhdl112 : std_logic_vector(7 DOWNTO 6);
BEGIN
IF (bit_err = '1') THEN
error_capture_code_type_xhdl112(7 DOWNTO 6) := "00";
ELSE
IF (form_err = '1') THEN
error_capture_code_type_xhdl112(7 DOWNTO 6) := "01";
ELSE
IF (stuff_err = '1') THEN
error_capture_code_type_xhdl112(7 DOWNTO 6) := "10";
ELSE
error_capture_code_type_xhdl112(7 DOWNTO 6) := "11";
END IF;
END IF;
END IF;
error_capture_code_type <= error_capture_code_type_xhdl112;
END PROCESS;
set_bus_error_irq_xhdl23 <= go_error_frame_xhdl33 AND (NOT error_capture_code_blocked) ;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
error_capture_code_blocked <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (read_error_code_capture_reg = '1') THEN
error_capture_code_blocked <= '0' ;
ELSE
IF (set_bus_error_irq_xhdl23 = '1') THEN
error_capture_code_blocked <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE RTL;
----------------------------------------------------------------------------------------------
--
-- VHDL file generated by X-HDL - Revision 3.2.53 Aug. 1, 2005
-- Tue Aug 9 07:33:51 2005
--
-- Input file : C:/Documents and Settings/BryantI/My Documents/tmp/can_top.v
-- Design name : can_register
-- Author :
-- Company : Actel
--
-- Description :
--
--
----------------------------------------------------------------------------------------------
--
--////////////////////////////////////////////////////////////////////
--// ////
--// can_register.v ////
--// ////
--// ////
--// This file is part of the CAN Protocol Controller ////
--// http://www.opencores.org/projects/can/ ////
--// ////
--// ////
--// Author(s): ////
--// Igor Mohor ////
--// [email protected] ////
--// ////
--// ////
--// All additional information is available in the README.txt ////
--// file. ////
--// ////
--////////////////////////////////////////////////////////////////////
--// ////
--// Copyright (C) 2002, 2003, 2004 Authors ////
--// ////
--// This source file may be used and distributed without ////
--// restriction provided that this copyright statement is not ////
--// removed from the file and that any derivative work contains ////
--// the original copyright notice and the associated disclaimer. ////
--// ////
--// This source file is free software; you can redistribute it ////
--// and/or modify it under the terms of the GNU Lesser General ////
--// Public License as published by the Free Software Foundation; ////
--// either version 2.1 of the License, or (at your option) any ////
--// later version. ////
--// ////
--// This source is distributed in the hope that it will be ////
--// useful, but WITHOUT ANY WARRANTY; without even the implied ////
--// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
--// PURPOSE. See the GNU Lesser General Public License for more ////
--// details. ////
--// ////
--// You should have received a copy of the GNU Lesser General ////
--// Public License along with this source; if not, download it ////
--// from http://www.opencores.org/lgpl.shtml ////
--// ////
--// The CAN protocol is developed by Robert Bosch GmbH and ////
--// protected by patents. Anybody who wants to implement this ////
--// CAN IP core on silicon has to obtain a CAN protocol license ////
--// from Bosch. ////
--// ////
--////////////////////////////////////////////////////////////////////
--
-- CVS Revision History
--
-- $Log: can_register.v,v $
-- Revision 1.7 2004/02/08 14:32:31 mohor
-- Header changed.
--
-- Revision 1.6 2003/03/20 16:58:50 mohor
-- unix.
--
-- Revision 1.4 2003/03/11 16:32:34 mohor
-- timescale.v is used for simulation only.
--
-- Revision 1.3 2003/02/09 02:24:33 mohor
-- Bosch license warning added. Error counters finished. Overload frames
-- still need to be fixed.
--
-- Revision 1.2 2002/12/27 00:12:52 mohor
-- Header changed, testbench improved to send a frame (crc still missing).
--
-- Revision 1.1.1.1 2002/12/20 16:39:21 mohor
-- Initial
--
--
--
-- synopsys translate_off
--`include "can_defines.v"
-- synopsys translate_on
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY can_register IS
GENERIC (
WIDTH : integer := 8); -- default parameter of the register width
PORT (
data_in : IN std_logic_vector(WIDTH - 1 DOWNTO 0);
data_out : OUT std_logic_vector(WIDTH - 1 DOWNTO 0);
we : IN std_logic;
clk : IN std_logic);
END ENTITY can_register;
ARCHITECTURE RTL OF can_register IS
TYPE xhdl_15 IS ARRAY (0 TO 63) OF std_logic_vector(7 DOWNTO 0);
TYPE xhdl_16 IS ARRAY (0 TO 63) OF std_logic_vector(3 DOWNTO 0);
TYPE xhdl_17 IS ARRAY (0 TO 63) OF std_logic;
TYPE xhdl_46 IS ARRAY (0 TO 7) OF std_logic_vector(7 DOWNTO 0);
SIGNAL data_out_xhdl1 : std_logic_vector(WIDTH - 1 DOWNTO 0);
BEGIN
data_out <= data_out_xhdl1;
PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk = '1') THEN
IF (we = '1') THEN
-- write
data_out_xhdl1 <= data_in;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE RTL;
----------------------------------------------------------------------------------------------
--
-- VHDL file generated by X-HDL - Revision 3.2.53 Aug. 1, 2005
-- Tue Aug 9 07:33:51 2005
--
-- Input file : C:/Documents and Settings/BryantI/My Documents/tmp/can_top.v
-- Design name : can_register_asyn
-- Author :
-- Company : Actel
--
-- Description :
--
--
----------------------------------------------------------------------------------------------
--
--////////////////////////////////////////////////////////////////////
--// ////
--// can_register_asyn.v ////
--// ////
--// ////
--// This file is part of the CAN Protocol Controller ////
--// http://www.opencores.org/projects/can/ ////
--// ////
--// ////
--// Author(s): ////
--// Igor Mohor ////
--// [email protected] ////
--// ////
--// ////
--// All additional information is available in the README.txt ////
--// file. ////
--// ////
--////////////////////////////////////////////////////////////////////
--// ////
--// Copyright (C) 2002, 2003, 2004 Authors ////
--// ////
--// This source file may be used and distributed without ////
--// restriction provided that this copyright statement is not ////
--// removed from the file and that any derivative work contains ////
--// the original copyright notice and the associated disclaimer. ////
--// ////
--// This source file is free software; you can redistribute it ////
--// and/or modify it under the terms of the GNU Lesser General ////
--// Public License as published by the Free Software Foundation; ////
--// either version 2.1 of the License, or (at your option) any ////
--// later version. ////
--// ////
--// This source is distributed in the hope that it will be ////
--// useful, but WITHOUT ANY WARRANTY; without even the implied ////
--// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
--// PURPOSE. See the GNU Lesser General Public License for more ////
--// details. ////
--// ////
--// You should have received a copy of the GNU Lesser General ////
--// Public License along with this source; if not, download it ////
--// from http://www.opencores.org/lgpl.shtml ////
--// ////
--// The CAN protocol is developed by Robert Bosch GmbH and ////
--// protected by patents. Anybody who wants to implement this ////
--// CAN IP core on silicon has to obtain a CAN protocol license ////
--// from Bosch. ////
--// ////
--////////////////////////////////////////////////////////////////////
--
-- CVS Revision History
--
-- $Log: can_register_asyn.v,v $
-- Revision 1.7 2004/02/08 14:33:19 mohor
-- Header changed.
--
-- Revision 1.6 2003/03/20 16:58:50 mohor
-- unix.
--
-- Revision 1.4 2003/03/11 16:32:34 mohor
-- timescale.v is used for simulation only.
--
-- Revision 1.3 2003/02/09 02:24:33 mohor
-- Bosch license warning added. Error counters finished. Overload frames
-- still need to be fixed.
--
-- Revision 1.2 2002/12/27 00:12:52 mohor
-- Header changed, testbench improved to send a frame (crc still missing).
--
-- Revision 1.1.1.1 2002/12/20 16:39:21 mohor
-- Initial
--
--
--
-- synopsys translate_off
--`include "can_defines.v"
-- synopsys translate_on
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
ENTITY can_register_asyn IS
GENERIC (
WIDTH : integer := 8; -- default parameter of the register width
RESET_VALUE : integer := 0);
PORT (
data_in : IN std_logic_vector(WIDTH - 1 DOWNTO 0);
data_out : OUT std_logic_vector(WIDTH - 1 DOWNTO 0);
we : IN std_logic;
clk : IN std_logic;
rst : IN std_logic);
END ENTITY can_register_asyn;
ARCHITECTURE RTL OF can_register_asyn IS
TYPE xhdl_15 IS ARRAY (0 TO 63) OF std_logic_vector(7 DOWNTO 0);
TYPE xhdl_16 IS ARRAY (0 TO 63) OF std_logic_vector(3 DOWNTO 0);
TYPE xhdl_17 IS ARRAY (0 TO 63) OF std_logic;
TYPE xhdl_46 IS ARRAY (0 TO 7) OF std_logic_vector(7 DOWNTO 0);
SIGNAL data_out_xhdl1 : std_logic_vector(WIDTH - 1 DOWNTO 0);
BEGIN
data_out <= data_out_xhdl1;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
-- asynchronous reset
data_out_xhdl1 <= CONV_STD_LOGIC_VECTOR(RESET_VALUE, WIDTH);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (we = '1') THEN
-- write
data_out_xhdl1 <= data_in ;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE RTL;
----------------------------------------------------------------------------------------------
--
-- VHDL file generated by X-HDL - Revision 3.2.53 Aug. 1, 2005
-- Tue Aug 9 07:33:52 2005
--
-- Input file : C:/Documents and Settings/BryantI/My Documents/tmp/can_top.v
-- Design name : can_register_asyn_syn
-- Author :
-- Company : Actel
--
-- Description :
--
--
----------------------------------------------------------------------------------------------
--
--////////////////////////////////////////////////////////////////////
--// ////
--// can_register_asyn_syn.v ////
--// ////
--// ////
--// This file is part of the CAN Protocol Controller ////
--// http://www.opencores.org/projects/can/ ////
--// ////
--// ////
--// Author(s): ////
--// Igor Mohor ////
--// [email protected] ////
--// ////
--// ////
--// All additional information is available in the README.txt ////
--// file. ////
--// ////
--////////////////////////////////////////////////////////////////////
--// ////
--// Copyright (C) 2002, 2003, 2004 Authors ////
--// ////
--// This source file may be used and distributed without ////
--// restriction provided that this copyright statement is not ////
--// removed from the file and that any derivative work contains ////
--// the original copyright notice and the associated disclaimer. ////
--// ////
--// This source file is free software; you can redistribute it ////
--// and/or modify it under the terms of the GNU Lesser General ////
--// Public License as published by the Free Software Foundation; ////
--// either version 2.1 of the License, or (at your option) any ////
--// later version. ////
--// ////
--// This source is distributed in the hope that it will be ////
--// useful, but WITHOUT ANY WARRANTY; without even the implied ////
--// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
--// PURPOSE. See the GNU Lesser General Public License for more ////
--// details. ////
--// ////
--// You should have received a copy of the GNU Lesser General ////
--// Public License along with this source; if not, download it ////
--// from http://www.opencores.org/lgpl.shtml ////
--// ////
--// The CAN protocol is developed by Robert Bosch GmbH and ////
--// protected by patents. Anybody who wants to implement this ////
--// CAN IP core on silicon has to obtain a CAN protocol license ////
--// from Bosch. ////
--// ////
--////////////////////////////////////////////////////////////////////
--
-- CVS Revision History
--
-- $Log: can_register_asyn_syn.v,v $
-- Revision 1.7 2004/02/08 14:33:59 mohor
-- Header changed.
--
-- Revision 1.6 2003/03/20 16:52:43 mohor
-- unix.
--
-- Revision 1.4 2003/03/11 16:32:34 mohor
-- timescale.v is used for simulation only.
--
-- Revision 1.3 2003/02/09 02:24:33 mohor
-- Bosch license warning added. Error counters finished. Overload frames
-- still need to be fixed.
--
-- Revision 1.2 2002/12/27 00:12:52 mohor
-- Header changed, testbench improved to send a frame (crc still missing).
--
-- Revision 1.1.1.1 2002/12/20 16:39:21 mohor
-- Initial
--
--
--
-- synopsys translate_off
--`include "can_defines.v"
-- synopsys translate_on
LIBRARY ieee;
USE ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
ENTITY can_register_asyn_syn IS
GENERIC (
WIDTH : integer := 8; -- default parameter of the register width
RESET_VALUE : integer := 0);
PORT (
data_in : IN std_logic_vector(WIDTH - 1 DOWNTO 0);
data_out : OUT std_logic_vector(WIDTH - 1 DOWNTO 0);
we : IN std_logic;
clk : IN std_logic;
rst : IN std_logic;
rst_sync : IN std_logic);
END ENTITY can_register_asyn_syn;
ARCHITECTURE RTL OF can_register_asyn_syn IS
TYPE xhdl_15 IS ARRAY (0 TO 63) OF std_logic_vector(7 DOWNTO 0);
TYPE xhdl_16 IS ARRAY (0 TO 63) OF std_logic_vector(3 DOWNTO 0);
TYPE xhdl_17 IS ARRAY (0 TO 63) OF std_logic;
TYPE xhdl_46 IS ARRAY (0 TO 7) OF std_logic_vector(7 DOWNTO 0);
SIGNAL data_out_xhdl1 : std_logic_vector(WIDTH - 1 DOWNTO 0);
BEGIN
data_out <= data_out_xhdl1;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
data_out_xhdl1 <= CONV_STD_LOGIC_VECTOR(RESET_VALUE, WIDTH);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (rst_sync = '1') THEN
-- synchronous reset
data_out_xhdl1 <= CONV_STD_LOGIC_VECTOR(RESET_VALUE, WIDTH);
ELSE
IF (we = '1') THEN
-- write
data_out_xhdl1 <= data_in ;
END IF;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE RTL;
----------------------------------------------------------------------------------------------
--
-- VHDL file generated by X-HDL - Revision 3.2.53 Aug. 1, 2005
-- Tue Aug 9 07:33:52 2005
--
-- Input file : C:/Documents and Settings/BryantI/My Documents/tmp/can_top.v
-- Design name : can_register_syn
-- Author :
-- Company : Actel
--
-- Description :
--
--
----------------------------------------------------------------------------------------------
--
--////////////////////////////////////////////////////////////////////
--// ////
--// can_register_syn.v ////
--// ////
--// ////
--// This file is part of the CAN Protocol Controller ////
--// http://www.opencores.org/projects/can/ ////
--// ////
--// ////
--// Author(s): ////
--// Igor Mohor ////
--// [email protected] ////
--// ////
--// ////
--// All additional information is available in the README.txt ////
--// file. ////
--// ////
--////////////////////////////////////////////////////////////////////
--// ////
--// Copyright (C) 2002, 2003, 2004 Authors ////
--// ////
--// This source file may be used and distributed without ////
--// restriction provided that this copyright statement is not ////
--// removed from the file and that any derivative work contains ////
--// the original copyright notice and the associated disclaimer. ////
--// ////
--// This source file is free software; you can redistribute it ////
--// and/or modify it under the terms of the GNU Lesser General ////
--// Public License as published by the Free Software Foundation; ////
--// either version 2.1 of the License, or (at your option) any ////
--// later version. ////
--// ////
--// This source is distributed in the hope that it will be ////
--// useful, but WITHOUT ANY WARRANTY; without even the implied ////
--// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
--// PURPOSE. See the GNU Lesser General Public License for more ////
--// details. ////
--// ////
--// You should have received a copy of the GNU Lesser General ////
--// Public License along with this source; if not, download it ////
--// from http://www.opencores.org/lgpl.shtml ////
--// ////
--// The CAN protocol is developed by Robert Bosch GmbH and ////
--// protected by patents. Anybody who wants to implement this ////
--// CAN IP core on silicon has to obtain a CAN protocol license ////
--// from Bosch. ////
--// ////
--////////////////////////////////////////////////////////////////////
--
-- CVS Revision History
--
-- $Log: can_register_syn.v,v $
-- Revision 1.5 2004/02/08 14:34:40 mohor
-- Header changed.
--
-- Revision 1.4 2003/03/11 16:31:58 mohor
-- timescale.v is used for simulation only.
--
-- Revision 1.3 2003/02/09 02:24:33 mohor
-- Bosch license warning added. Error counters finished. Overload frames
-- still need to be fixed.
--
-- Revision 1.2 2002/12/27 00:12:52 mohor
-- Header changed, testbench improved to send a frame (crc still missing).
--
-- Revision 1.1.1.1 2002/12/20 16:39:21 mohor
-- Initial
--
--
--
-- synopsys translate_off
--`include "can_defines.v"
-- synopsys translate_on
LIBRARY ieee;
USE ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
ENTITY can_register_syn IS
GENERIC (
WIDTH : integer := 8; -- default parameter of the register width
RESET_VALUE : integer := 0);
PORT (
data_in : IN std_logic_vector(WIDTH - 1 DOWNTO 0);
data_out : OUT std_logic_vector(WIDTH - 1 DOWNTO 0);
we : IN std_logic;
clk : IN std_logic;
rst_sync : IN std_logic);
END ENTITY can_register_syn;
ARCHITECTURE RTL OF can_register_syn IS
TYPE xhdl_15 IS ARRAY (0 TO 63) OF std_logic_vector(7 DOWNTO 0);
TYPE xhdl_16 IS ARRAY (0 TO 63) OF std_logic_vector(3 DOWNTO 0);
TYPE xhdl_17 IS ARRAY (0 TO 63) OF std_logic;
TYPE xhdl_46 IS ARRAY (0 TO 7) OF std_logic_vector(7 DOWNTO 0);
SIGNAL data_out_xhdl1 : std_logic_vector(WIDTH - 1 DOWNTO 0);
BEGIN
data_out <= data_out_xhdl1;
PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk = '1') THEN
IF (rst_sync = '1') THEN
-- synchronous reset
data_out_xhdl1 <= CONV_STD_LOGIC_VECTOR(RESET_VALUE, 8);
ELSE
IF (we = '1') THEN
-- write
data_out_xhdl1 <= data_in ;
END IF;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE RTL;
----------------------------------------------------------------------------------------------
--
-- VHDL file generated by X-HDL - Revision 3.2.53 Aug. 1, 2005
-- Tue Aug 9 07:33:52 2005
--
-- Input file : C:/Documents and Settings/BryantI/My Documents/tmp/can_top.v
-- Design name : can_registers
-- Author :
-- Company : Actel
--
-- Description :
--
--
----------------------------------------------------------------------------------------------
--
--////////////////////////////////////////////////////////////////////
--// ////
--// can_registers.v ////
--// ////
--// ////
--// This file is part of the CAN Protocol Controller ////
--// http://www.opencores.org/projects/can/ ////
--// ////
--// ////
--// Author(s): ////
--// Igor Mohor ////
--// [email protected] ////
--// ////
--// ////
--// All additional information is available in the README.txt ////
--// file. ////
--// ////
--////////////////////////////////////////////////////////////////////
--// ////
--// Copyright (C) 2002, 2003 Authors ////
--// ////
--// This source file may be used and distributed without ////
--// restriction provided that this copyright statement is not ////
--// removed from the file and that any derivative work contains ////
--// the original copyright notice and the associated disclaimer. ////
--// ////
--// This source file is free software; you can redistribute it ////
--// and/or modify it under the terms of the GNU Lesser General ////
--// Public License as published by the Free Software Foundation; ////
--// either version 2.1 of the License, or (at your option) any ////
--// later version. ////
--// ////
--// This source is distributed in the hope that it will be ////
--// useful, but WITHOUT ANY WARRANTY; without even the implied ////
--// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
--// PURPOSE. See the GNU Lesser General Public License for more ////
--// details. ////
--// ////
--// You should have received a copy of the GNU Lesser General ////
--// Public License along with this source; if not, download it ////
--// from http://www.opencores.org/lgpl.shtml ////
--// ////
--// The CAN protocol is developed by Robert Bosch GmbH and ////
--// protected by patents. Anybody who wants to implement this ////
--// CAN IP core on silicon has to obtain a CAN protocol license ////
--// from Bosch. ////
--// ////
--////////////////////////////////////////////////////////////////////
--
-- CVS Revision History
-- Revision 1.36 2005/03/18 15:04:05 igorm
-- Wake-up interrupt was generated in some cases.
--
-- Revision 1.35 2004/11/30 15:08:26 igorm
-- irq is cleared after the release_buffer command. This bug was entered with
-- changes for the edge triggered interrupts.
--
-- Revision 1.34 2004/11/18 12:39:43 igorm
-- Fixes for compatibility after the SW reset.
--
-- Revision 1.33 2004/10/25 11:44:38 igorm
-- Interrupt is always cleared for one clock after the irq register is read.
-- This fixes problems when CPU is using IRQs that are edge triggered.
--
-- Revision 1.32 2004/05/12 15:58:41 igorm
-- Core improved to pass all tests with the Bosch VHDL Reference system.
--
-- Revision 1.31 2003/09/25 18:55:49 mohor
-- Synchronization changed, error counters fixed.
--
-- Revision 1.30 2003/07/16 15:19:34 mohor
-- Fixed according to the linter.
-- Case statement for data_out joined.
--
-- Revision 1.29 2003/07/10 01:59:04 tadejm
-- Synchronization fixed. In some strange cases it didn't work according to
-- the VHDL reference model.
--
-- Revision 1.28 2003/07/07 11:21:37 mohor
-- Little fixes (to fix warnings).
--
-- Revision 1.27 2003/06/22 09:43:03 mohor
-- synthesi full_case parallel_case fixed.
--
-- Revision 1.26 2003/06/22 01:33:14 mohor
-- clkout is clk/2 after the reset.
--
-- Revision 1.25 2003/06/21 12:16:30 mohor
-- paralel_case and full_case compiler directives added to case statements.
--
-- Revision 1.24 2003/06/09 11:22:54 mohor
-- data_out is already registered in the can_top.v file.
--
-- Revision 1.23 2003/04/15 15:31:24 mohor
-- Some features are supported in extended mode only (listen_only_mode...).
--
-- Revision 1.22 2003/03/20 16:58:50 mohor
-- unix.
--
-- Revision 1.20 2003/03/11 16:31:05 mohor
-- Mux used for clkout to avoid "gated clocks warning".
--
-- Revision 1.19 2003/03/10 17:34:25 mohor
-- Doubled declarations removed.
--
-- Revision 1.18 2003/03/01 22:52:11 mohor
-- Data is latched on read.
--
-- Revision 1.17 2003/02/19 15:09:02 mohor
-- Incomplete sensitivity list fixed.
--
-- Revision 1.16 2003/02/19 14:44:03 mohor
-- CAN core finished. Host interface added. Registers finished.
-- Synchronization to the wishbone finished.
--
-- Revision 1.15 2003/02/18 00:10:15 mohor
-- Most of the registers added. Registers "arbitration lost capture", "error code
-- capture" + few more still need to be added.
--
-- Revision 1.14 2003/02/14 20:17:01 mohor
-- Several registers added. Not finished, yet.
--
-- Revision 1.13 2003/02/12 14:25:30 mohor
-- abort_tx added.
--
-- Revision 1.12 2003/02/11 00:56:06 mohor
-- Wishbone interface added.
--
-- Revision 1.11 2003/02/09 02:24:33 mohor
-- Bosch license warning added. Error counters finished. Overload frames
-- still need to be fixed.
--
-- Revision 1.10 2003/01/31 01:13:38 mohor
-- backup.
--
-- Revision 1.9 2003/01/15 13:16:48 mohor
-- When a frame with "remote request" is received, no data is stored
-- to fifo, just the frame information (identifier, ...). Data length
-- that is stored is the received data length and not the actual data
-- length that is stored to fifo.
--
-- Revision 1.8 2003/01/14 17:25:09 mohor
-- Addresses corrected to decimal values (previously hex).
--
-- Revision 1.7 2003/01/14 12:19:35 mohor
-- rx_fifo is now working.
--
-- Revision 1.6 2003/01/10 17:51:34 mohor
-- Temporary version (backup).
--
-- Revision 1.5 2003/01/09 14:46:58 mohor
-- Temporary files (backup).
--
-- Revision 1.4 2003/01/08 02:10:55 mohor
-- Acceptance filter added.
--
-- Revision 1.3 2002/12/27 00:12:52 mohor
-- Header changed, testbench improved to send a frame (crc still missing).
--
-- Revision 1.2 2002/12/26 16:00:34 mohor
-- Testbench define file added. Clock divider register added.
--
-- Revision 1.1.1.1 2002/12/20 16:39:21 mohor
-- Initial
--
--
--
-- synopsys translate_off
--`include "can_defines.v"
-- synopsys translate_on
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
ENTITY can_registers IS
PORT (
clk : IN std_logic;
rst : IN std_logic;
cs : IN std_logic;
we : IN std_logic;
addr : IN std_logic_vector(7 DOWNTO 0);
data_in : IN std_logic_vector(7 DOWNTO 0);
data_out : OUT std_logic_vector(7 DOWNTO 0);
irq_n : OUT std_logic;
sample_point : IN std_logic;
transmitting : IN std_logic;
set_reset_mode : IN std_logic;
node_bus_off : IN std_logic;
error_status : IN std_logic;
rx_err_cnt : IN std_logic_vector(7 DOWNTO 0);
tx_err_cnt : IN std_logic_vector(7 DOWNTO 0);
transmit_status : IN std_logic;
receive_status : IN std_logic;
tx_successful : IN std_logic;
need_to_tx : IN std_logic;
overrun : IN std_logic;
info_empty : IN std_logic;
set_bus_error_irq : IN std_logic;
set_arbitration_lost_irq: IN std_logic;
arbitration_lost_capture: IN std_logic_vector(4 DOWNTO 0);
node_error_passive : IN std_logic;
node_error_active : IN std_logic;
rx_message_counter : IN std_logic_vector(6 DOWNTO 0);
-- Mode register
reset_mode : OUT std_logic;
listen_only_mode : OUT std_logic;
acceptance_filter_mode : OUT std_logic;
self_test_mode : OUT std_logic;
-- Command register
clear_data_overrun : OUT std_logic;
release_buffer : OUT std_logic;
abort_tx : OUT std_logic;
tx_request : OUT std_logic;
self_rx_request : OUT std_logic;
single_shot_transmission: OUT std_logic;
tx_state : IN std_logic;
tx_state_q : IN std_logic;
overload_request : OUT std_logic;
overload_frame : IN std_logic;
-- Arbitration Lost Capture Register
read_arbitration_lost_capture_reg: OUT std_logic;
-- Error Code Capture Register
read_error_code_capture_reg: OUT std_logic;
error_capture_code : IN std_logic_vector(7 DOWNTO 0);
-- Bus Timing 0 register
baud_r_presc : OUT std_logic_vector(5 DOWNTO 0);
sync_jump_width : OUT std_logic_vector(1 DOWNTO 0);
-- Bus Timing 1 register
time_segment1 : OUT std_logic_vector(3 DOWNTO 0);
time_segment2 : OUT std_logic_vector(2 DOWNTO 0);
triple_sampling : OUT std_logic;
-- Error Warning Limit register
error_warning_limit : OUT std_logic_vector(7 DOWNTO 0);
-- Rx Error Counter register
we_rx_err_cnt : OUT std_logic;
-- Tx Error Counter register
we_tx_err_cnt : OUT std_logic;
-- Clock Divider register
extended_mode : OUT std_logic;
clkout : OUT std_logic;
-- This section is for BASIC and EXTENDED mode -- Acceptance code register
acceptance_code_0 : OUT std_logic_vector(7 DOWNTO 0);
-- Acceptance mask register
acceptance_mask_0 : OUT std_logic_vector(7 DOWNTO 0);
-- End: This section is for BASIC and EXTENDED mode -- This section is for EXTENDED mode -- Acceptance code register
acceptance_code_1 : OUT std_logic_vector(7 DOWNTO 0);
acceptance_code_2 : OUT std_logic_vector(7 DOWNTO 0);
acceptance_code_3 : OUT std_logic_vector(7 DOWNTO 0);
-- Acceptance mask register
acceptance_mask_1 : OUT std_logic_vector(7 DOWNTO 0);
acceptance_mask_2 : OUT std_logic_vector(7 DOWNTO 0);
acceptance_mask_3 : OUT std_logic_vector(7 DOWNTO 0);
-- End: This section is for EXTENDED mode -- Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data
tx_data_0 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_1 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_2 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_3 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_4 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_5 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_6 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_7 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_8 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_9 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_10 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_11 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_12 : OUT std_logic_vector(7 DOWNTO 0));
END ENTITY can_registers;
ARCHITECTURE RTL OF can_registers IS
CONSTANT xhdl_timescale : time := 1 ns;
COMPONENT can_register
GENERIC (
WIDTH : integer := 8); -- default parameter of the register width
PORT (
data_in : IN std_logic_vector(WIDTH - 1 DOWNTO 0);
data_out : OUT std_logic_vector(WIDTH - 1 DOWNTO 0);
we : IN std_logic;
clk : IN std_logic);
END COMPONENT;
COMPONENT can_register_asyn
GENERIC (
WIDTH : integer := 8; -- default parameter of the register width
RESET_VALUE : integer := 0);
PORT (
data_in : IN std_logic_vector(WIDTH - 1 DOWNTO 0);
data_out : OUT std_logic_vector(WIDTH - 1 DOWNTO 0);
we : IN std_logic;
clk : IN std_logic;
rst : IN std_logic);
END COMPONENT;
COMPONENT can_register_asyn_syn
GENERIC (
WIDTH : integer := 8; -- default parameter of the register width
RESET_VALUE : integer := 0);
PORT (
data_in : IN std_logic_vector(WIDTH - 1 DOWNTO 0);
data_out : OUT std_logic_vector(WIDTH - 1 DOWNTO 0);
we : IN std_logic;
clk : IN std_logic;
rst : IN std_logic;
rst_sync : IN std_logic);
END COMPONENT;
TYPE xhdl_15 IS ARRAY (0 TO 63) OF std_logic_vector(7 DOWNTO 0);
TYPE xhdl_16 IS ARRAY (0 TO 63) OF std_logic_vector(3 DOWNTO 0);
TYPE xhdl_17 IS ARRAY (0 TO 63) OF std_logic;
TYPE xhdl_46 IS ARRAY (0 TO 7) OF std_logic_vector(7 DOWNTO 0);
-- End: Tx data registers
signal read_irq_reg_q : std_logic;
signal reset_irq_reg : std_logic;
SIGNAL tx_successful_q : std_logic;
SIGNAL overrun_q : std_logic;
SIGNAL overrun_status : std_logic;
SIGNAL transmission_complete : std_logic;
SIGNAL transmit_buffer_status_q : std_logic;
SIGNAL receive_buffer_status : std_logic;
SIGNAL error_status_q : std_logic;
SIGNAL node_bus_off_q : std_logic;
SIGNAL node_error_passive_q : std_logic;
SIGNAL transmit_buffer_status : std_logic;
-- Some interrupts exist in basic mode and in extended mode. Since they are in different registers they need to be multiplexed.
SIGNAL data_overrun_irq_en : std_logic;
SIGNAL error_warning_irq_en : std_logic;
SIGNAL transmit_irq_en : std_logic;
SIGNAL receive_irq_en : std_logic;
SIGNAL irq_reg : std_logic_vector(7 DOWNTO 0);
SIGNAL irq : std_logic;
SIGNAL we_mode : std_logic;
SIGNAL we_command : std_logic;
SIGNAL we_bus_timing_0 : std_logic;
SIGNAL we_bus_timing_1 : std_logic;
SIGNAL we_clock_divider_low : std_logic;
SIGNAL we_clock_divider_hi : std_logic;
SIGNAL read : std_logic;
SIGNAL read_irq_reg : std_logic;
-- This section is for BASIC and EXTENDED mode
SIGNAL we_acceptance_code_0 : std_logic;
SIGNAL we_acceptance_mask_0 : std_logic;
SIGNAL we_tx_data_0 : std_logic;
SIGNAL we_tx_data_1 : std_logic;
SIGNAL we_tx_data_2 : std_logic;
SIGNAL we_tx_data_3 : std_logic;
SIGNAL we_tx_data_4 : std_logic;
SIGNAL we_tx_data_5 : std_logic;
SIGNAL we_tx_data_6 : std_logic;
SIGNAL we_tx_data_7 : std_logic;
SIGNAL we_tx_data_8 : std_logic;
SIGNAL we_tx_data_9 : std_logic;
SIGNAL we_tx_data_10 : std_logic;
SIGNAL we_tx_data_11 : std_logic;
SIGNAL we_tx_data_12 : std_logic;
-- End: This section is for BASIC and EXTENDED mode
-- This section is for EXTENDED mode
SIGNAL we_interrupt_enable : std_logic;
SIGNAL we_error_warning_limit : std_logic;
SIGNAL we_acceptance_code_1 : std_logic;
SIGNAL we_acceptance_code_2 : std_logic;
SIGNAL we_acceptance_code_3 : std_logic;
SIGNAL we_acceptance_mask_1 : std_logic;
SIGNAL we_acceptance_mask_2 : std_logic;
SIGNAL we_acceptance_mask_3 : std_logic;
-- Mode register
SIGNAL mode : std_logic;
SIGNAL mode_basic : std_logic_vector(4 DOWNTO 1);
SIGNAL mode_ext : std_logic_vector(3 DOWNTO 1);
SIGNAL receive_irq_en_basic : std_logic;
SIGNAL transmit_irq_en_basic : std_logic;
SIGNAL error_irq_en_basic : std_logic;
SIGNAL overrun_irq_en_basic : std_logic;
SIGNAL port_xhdl52 : std_logic;
SIGNAL xhdl_61 : std_logic;
-- End Mode register
-- Command register
SIGNAL command : std_logic_vector(4 DOWNTO 0);
SIGNAL xhdl_69 : std_logic;
SIGNAL port_xhdl70 : std_logic;
SIGNAL port_xhdl71 : std_logic;
SIGNAL xhdl_77 : std_logic;
SIGNAL port_xhdl78 : std_logic;
SIGNAL port_xhdl79 : std_logic;
SIGNAL xhdl_85 : std_logic;
SIGNAL xhdl_91 : std_logic;
SIGNAL port_xhdl92 : std_logic;
SIGNAL port_xhdl93 : std_logic;
-- End Command register
-- Status register
SIGNAL status : std_logic_vector(7 DOWNTO 0);
-- End Status register
-- Interrupt Enable register (extended mode)
SIGNAL irq_en_ext : std_logic_vector(7 DOWNTO 0);
SIGNAL bus_error_irq_en : std_logic;
SIGNAL arbitration_lost_irq_en : std_logic;
SIGNAL error_passive_irq_en : std_logic;
SIGNAL data_overrun_irq_en_ext : std_logic;
SIGNAL error_warning_irq_en_ext : std_logic;
SIGNAL transmit_irq_en_ext : std_logic;
SIGNAL receive_irq_en_ext : std_logic;
-- End Bus Timing 0 register
-- Bus Timing 0 register
SIGNAL bus_timing_0 : std_logic_vector(7 DOWNTO 0);
-- End Bus Timing 0 register
-- Bus Timing 1 register
SIGNAL bus_timing_1 : std_logic_vector(7 DOWNTO 0);
-- End Error Warning Limit register
-- Clock Divider register
SIGNAL clock_divider : std_logic_vector(7 DOWNTO 0);
SIGNAL clock_off : std_logic;
SIGNAL cd : std_logic_vector(2 DOWNTO 0);
SIGNAL clkout_div : std_logic_vector(2 DOWNTO 0);
SIGNAL clkout_cnt : std_logic_vector(2 DOWNTO 0);
SIGNAL clkout_tmp : std_logic;
SIGNAL port_xhdl116 : std_logic;
SIGNAL port_xhdl117 : std_logic;
SIGNAL port_xhdl123 : std_logic;
SIGNAL port_xhdl124 : std_logic;
SIGNAL temp_xhdl131 : std_logic;
SIGNAL temp_xhdl132 : std_logic;
SIGNAL temp_xhdl218 : std_logic_vector(7 DOWNTO 0); -- basic mode
SIGNAL temp_xhdl219 : std_logic_vector(7 DOWNTO 0); -- basic mode
SIGNAL temp_xhdl220 : std_logic_vector(7 DOWNTO 0); -- basic mode
SIGNAL temp_xhdl221 : std_logic_vector(7 DOWNTO 0); -- basic mode
SIGNAL temp_xhdl222 : std_logic_vector(7 DOWNTO 0); -- basic mode
SIGNAL temp_xhdl223 : std_logic_vector(7 DOWNTO 0); -- basic mode
SIGNAL temp_xhdl224 : std_logic_vector(7 DOWNTO 0); -- basic mode
SIGNAL temp_xhdl225 : std_logic_vector(7 DOWNTO 0); -- basic mode
SIGNAL temp_xhdl226 : std_logic_vector(7 DOWNTO 0); -- basic mode
SIGNAL temp_xhdl227 : std_logic_vector(7 DOWNTO 0); -- basic mode
SIGNAL temp_xhdl228 : std_logic_vector(7 DOWNTO 0); -- basic mode
SIGNAL temp_xhdl229 : std_logic_vector(7 DOWNTO 0); -- basic mode
SIGNAL temp_xhdl230 : std_logic_vector(7 DOWNTO 0); -- basic mode
SIGNAL temp_xhdl231 : std_logic_vector(7 DOWNTO 0); -- basic mode
-- Some interrupts exist in basic mode and in extended mode. Since they are in different registers they need to be multiplexed.
SIGNAL temp_xhdl233 : std_logic;
SIGNAL temp_xhdl234 : std_logic;
SIGNAL temp_xhdl235 : std_logic;
SIGNAL temp_xhdl236 : std_logic;
SIGNAL data_overrun_irq : std_logic;
SIGNAL transmit_irq : std_logic;
SIGNAL receive_irq : std_logic;
SIGNAL error_irq : std_logic;
SIGNAL bus_error_irq : std_logic;
SIGNAL arbitration_lost_irq : std_logic;
SIGNAL error_passive_irq : std_logic;
SIGNAL data_out_xhdl1 : std_logic_vector(7 DOWNTO 0);
SIGNAL irq_n_xhdl2 : std_logic;
SIGNAL reset_mode_xhdl3 : std_logic;
SIGNAL listen_only_mode_xhdl4 : std_logic;
SIGNAL acceptance_filter_mode_xhdl5 : std_logic;
SIGNAL self_test_mode_xhdl6 : std_logic;
SIGNAL clear_data_overrun_xhdl7 : std_logic;
SIGNAL release_buffer_xhdl8 : std_logic;
SIGNAL abort_tx_xhdl9 : std_logic;
SIGNAL tx_request_xhdl10 : std_logic;
SIGNAL self_rx_request_xhdl11 : std_logic;
SIGNAL single_shot_transmission_xhdl12 : std_logic;
SIGNAL overload_request_xhdl13 : std_logic;
SIGNAL read_arbitration_lost_capture_reg_xhdl14: std_logic;
SIGNAL read_error_code_capture_reg_xhdl15: std_logic;
SIGNAL baud_r_presc_xhdl16 : std_logic_vector(5 DOWNTO 0);
SIGNAL sync_jump_width_xhdl17 : std_logic_vector(1 DOWNTO 0);
SIGNAL time_segment1_xhdl18 : std_logic_vector(3 DOWNTO 0);
SIGNAL time_segment2_xhdl19 : std_logic_vector(2 DOWNTO 0);
SIGNAL triple_sampling_xhdl20 : std_logic;
SIGNAL error_warning_limit_xhdl21 : std_logic_vector(7 DOWNTO 0);
SIGNAL we_rx_err_cnt_xhdl22 : std_logic;
SIGNAL we_tx_err_cnt_xhdl23 : std_logic;
SIGNAL extended_mode_xhdl24 : std_logic;
SIGNAL clkout_xhdl25 : std_logic;
SIGNAL acceptance_code_0_xhdl26 : std_logic_vector(7 DOWNTO 0);
SIGNAL acceptance_mask_0_xhdl27 : std_logic_vector(7 DOWNTO 0);
SIGNAL acceptance_code_1_xhdl28 : std_logic_vector(7 DOWNTO 0);
SIGNAL acceptance_code_2_xhdl29 : std_logic_vector(7 DOWNTO 0);
SIGNAL acceptance_code_3_xhdl30 : std_logic_vector(7 DOWNTO 0);
SIGNAL acceptance_mask_1_xhdl31 : std_logic_vector(7 DOWNTO 0);
SIGNAL acceptance_mask_2_xhdl32 : std_logic_vector(7 DOWNTO 0);
SIGNAL acceptance_mask_3_xhdl33 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_0_xhdl34 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_1_xhdl35 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_2_xhdl36 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_3_xhdl37 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_4_xhdl38 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_5_xhdl39 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_6_xhdl40 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_7_xhdl41 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_8_xhdl42 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_9_xhdl43 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_10_xhdl44 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_11_xhdl45 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_12_xhdl46 : std_logic_vector(7 DOWNTO 0);
BEGIN
data_out <= data_out_xhdl1;
irq_n <= irq_n_xhdl2;
reset_mode <= reset_mode_xhdl3;
listen_only_mode <= listen_only_mode_xhdl4;
acceptance_filter_mode <= acceptance_filter_mode_xhdl5;
self_test_mode <= self_test_mode_xhdl6;
clear_data_overrun <= clear_data_overrun_xhdl7;
release_buffer <= release_buffer_xhdl8;
abort_tx <= abort_tx_xhdl9;
tx_request <= tx_request_xhdl10;
self_rx_request <= self_rx_request_xhdl11;
single_shot_transmission <= single_shot_transmission_xhdl12;
overload_request <= overload_request_xhdl13;
read_arbitration_lost_capture_reg <= read_arbitration_lost_capture_reg_xhdl14;
read_error_code_capture_reg <= read_error_code_capture_reg_xhdl15;
baud_r_presc <= baud_r_presc_xhdl16;
sync_jump_width <= sync_jump_width_xhdl17;
time_segment1 <= time_segment1_xhdl18;
time_segment2 <= time_segment2_xhdl19;
triple_sampling <= triple_sampling_xhdl20;
error_warning_limit <= error_warning_limit_xhdl21;
we_rx_err_cnt <= we_rx_err_cnt_xhdl22;
we_tx_err_cnt <= we_tx_err_cnt_xhdl23;
extended_mode <= extended_mode_xhdl24;
clkout <= clkout_xhdl25;
acceptance_code_0 <= acceptance_code_0_xhdl26;
acceptance_mask_0 <= acceptance_mask_0_xhdl27;
acceptance_code_1 <= acceptance_code_1_xhdl28;
acceptance_code_2 <= acceptance_code_2_xhdl29;
acceptance_code_3 <= acceptance_code_3_xhdl30;
acceptance_mask_1 <= acceptance_mask_1_xhdl31;
acceptance_mask_2 <= acceptance_mask_2_xhdl32;
acceptance_mask_3 <= acceptance_mask_3_xhdl33;
tx_data_0 <= tx_data_0_xhdl34;
tx_data_1 <= tx_data_1_xhdl35;
tx_data_2 <= tx_data_2_xhdl36;
tx_data_3 <= tx_data_3_xhdl37;
tx_data_4 <= tx_data_4_xhdl38;
tx_data_5 <= tx_data_5_xhdl39;
tx_data_6 <= tx_data_6_xhdl40;
tx_data_7 <= tx_data_7_xhdl41;
tx_data_8 <= tx_data_8_xhdl42;
tx_data_9 <= tx_data_9_xhdl43;
tx_data_10 <= tx_data_10_xhdl44;
tx_data_11 <= tx_data_11_xhdl45;
tx_data_12 <= tx_data_12_xhdl46;
we_mode <= (cs AND we) AND CONV_STD_LOGIC(addr = "00000000") ;
we_command <= (cs AND we) AND CONV_STD_LOGIC(addr = "00000001") ;
we_bus_timing_0 <= ((cs AND we) AND CONV_STD_LOGIC(addr = "00000110")) AND reset_mode_xhdl3 ;
we_bus_timing_1 <= ((cs AND we) AND CONV_STD_LOGIC(addr = "00000111")) AND reset_mode_xhdl3 ;
we_clock_divider_low <= (cs AND we) AND CONV_STD_LOGIC(addr = "00011111") ;
we_clock_divider_hi <= we_clock_divider_low AND reset_mode_xhdl3 ;
read <= cs AND (NOT we) ;
read_irq_reg <= read AND CONV_STD_LOGIC(addr = "00000011") ;
reset_irq_reg <= read_irq_reg_q and not read_irq_reg;
read_arbitration_lost_capture_reg_xhdl14 <= (read AND extended_mode_xhdl24) AND CONV_STD_LOGIC(addr = "00001011") ;
read_error_code_capture_reg_xhdl15 <= (read AND extended_mode_xhdl24) AND CONV_STD_LOGIC(addr = "00001100") ;
we_acceptance_code_0 <= ((cs AND we) AND reset_mode_xhdl3) AND (((NOT extended_mode_xhdl24) AND CONV_STD_LOGIC(addr = "00000100")) OR (extended_mode_xhdl24 AND CONV_STD_LOGIC(addr = "00010000"))) ;
we_acceptance_mask_0 <= ((cs AND we) AND reset_mode_xhdl3) AND (((NOT extended_mode_xhdl24) AND CONV_STD_LOGIC(addr = "00000101")) OR (extended_mode_xhdl24 AND CONV_STD_LOGIC(addr = "00010100"))) ;
we_tx_data_0 <= (((cs AND we) AND (NOT reset_mode_xhdl3)) AND (((NOT extended_mode_xhdl24) AND CONV_STD_LOGIC(addr = "00001010")) OR (extended_mode_xhdl24 AND CONV_STD_LOGIC(addr = "00010000")))) AND transmit_buffer_status ;
we_tx_data_1 <= (((cs AND we) AND (NOT reset_mode_xhdl3)) AND (((NOT extended_mode_xhdl24) AND CONV_STD_LOGIC(addr = "00001011")) OR (extended_mode_xhdl24 AND CONV_STD_LOGIC(addr = "00010001")))) AND transmit_buffer_status ;
we_tx_data_2 <= (((cs AND we) AND (NOT reset_mode_xhdl3)) AND (((NOT extended_mode_xhdl24) AND CONV_STD_LOGIC(addr = "00001100")) OR (extended_mode_xhdl24 AND CONV_STD_LOGIC(addr = "00010010")))) AND transmit_buffer_status ;
we_tx_data_3 <= (((cs AND we) AND (NOT reset_mode_xhdl3)) AND (((NOT extended_mode_xhdl24) AND CONV_STD_LOGIC(addr = "00001101")) OR (extended_mode_xhdl24 AND CONV_STD_LOGIC(addr = "00010011")))) AND transmit_buffer_status ;
we_tx_data_4 <= (((cs AND we) AND (NOT reset_mode_xhdl3)) AND (((NOT extended_mode_xhdl24) AND CONV_STD_LOGIC(addr = "00001110")) OR (extended_mode_xhdl24 AND CONV_STD_LOGIC(addr = "00010100")))) AND transmit_buffer_status ;
we_tx_data_5 <= (((cs AND we) AND (NOT reset_mode_xhdl3)) AND (((NOT extended_mode_xhdl24) AND CONV_STD_LOGIC(addr = "00001111")) OR (extended_mode_xhdl24 AND CONV_STD_LOGIC(addr = "00010101")))) AND transmit_buffer_status ;
we_tx_data_6 <= (((cs AND we) AND (NOT reset_mode_xhdl3)) AND (((NOT extended_mode_xhdl24) AND CONV_STD_LOGIC(addr = "00010000")) OR (extended_mode_xhdl24 AND CONV_STD_LOGIC(addr = "00010110")))) AND transmit_buffer_status ;
we_tx_data_7 <= (((cs AND we) AND (NOT reset_mode_xhdl3)) AND (((NOT extended_mode_xhdl24) AND CONV_STD_LOGIC(addr = "00010001")) OR (extended_mode_xhdl24 AND CONV_STD_LOGIC(addr = "00010111")))) AND transmit_buffer_status ;
we_tx_data_8 <= (((cs AND we) AND (NOT reset_mode_xhdl3)) AND (((NOT extended_mode_xhdl24) AND CONV_STD_LOGIC(addr = "00010010")) OR (extended_mode_xhdl24 AND CONV_STD_LOGIC(addr = "00011000")))) AND transmit_buffer_status ;
we_tx_data_9 <= (((cs AND we) AND (NOT reset_mode_xhdl3)) AND (((NOT extended_mode_xhdl24) AND CONV_STD_LOGIC(addr = "00010011")) OR (extended_mode_xhdl24 AND CONV_STD_LOGIC(addr = "00011001")))) AND transmit_buffer_status ;
we_tx_data_10 <= (((cs AND we) AND (NOT reset_mode_xhdl3)) AND (extended_mode_xhdl24 AND CONV_STD_LOGIC(addr = "00011010"))) AND transmit_buffer_status ;
we_tx_data_11 <= (((cs AND we) AND (NOT reset_mode_xhdl3)) AND (extended_mode_xhdl24 AND CONV_STD_LOGIC(addr = "00011011"))) AND transmit_buffer_status ;
we_tx_data_12 <= (((cs AND we) AND (NOT reset_mode_xhdl3)) AND (extended_mode_xhdl24 AND CONV_STD_LOGIC(addr = "00011100"))) AND transmit_buffer_status ;
we_interrupt_enable <= ((cs AND we) AND CONV_STD_LOGIC(addr = "00000100")) AND extended_mode_xhdl24 ;
we_error_warning_limit <= (((cs AND we) AND CONV_STD_LOGIC(addr = "00001101")) AND reset_mode_xhdl3) AND extended_mode_xhdl24 ;
we_rx_err_cnt_xhdl22 <= (((cs AND we) AND CONV_STD_LOGIC(addr = "00001110")) AND reset_mode_xhdl3) AND extended_mode_xhdl24 ;
we_tx_err_cnt_xhdl23 <= (((cs AND we) AND CONV_STD_LOGIC(addr = "00001111")) AND reset_mode_xhdl3) AND extended_mode_xhdl24 ;
we_acceptance_code_1 <= (((cs AND we) AND CONV_STD_LOGIC(addr = "00010001")) AND reset_mode_xhdl3) AND extended_mode_xhdl24 ;
we_acceptance_code_2 <= (((cs AND we) AND CONV_STD_LOGIC(addr = "00010010")) AND reset_mode_xhdl3) AND extended_mode_xhdl24 ;
we_acceptance_code_3 <= (((cs AND we) AND CONV_STD_LOGIC(addr = "00010011")) AND reset_mode_xhdl3) AND extended_mode_xhdl24 ;
we_acceptance_mask_1 <= (((cs AND we) AND CONV_STD_LOGIC(addr = "00010101")) AND reset_mode_xhdl3) AND extended_mode_xhdl24 ;
we_acceptance_mask_2 <= (((cs AND we) AND CONV_STD_LOGIC(addr = "00010110")) AND reset_mode_xhdl3) AND extended_mode_xhdl24 ;
we_acceptance_mask_3 <= (((cs AND we) AND CONV_STD_LOGIC(addr = "00010111")) AND reset_mode_xhdl3) AND extended_mode_xhdl24 ;
-- End: This section is for EXTENDED mode
PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk = '1') THEN
read_irq_reg_q <= read_irq_reg;
tx_successful_q <= tx_successful ;
overrun_q <= overrun ;
transmit_buffer_status_q <= transmit_buffer_status ;
error_status_q <= error_status ;
node_bus_off_q <= node_bus_off ;
node_error_passive_q <= node_error_passive ;
END IF;
END PROCESS;
port_xhdl52 <= data_in(0);
MODE_REG0 : can_register_asyn_syn
GENERIC MAP (1, 1)
PORT MAP (
data_in(0) => port_xhdl52,
data_out(0) => mode,
we => we_mode,
clk => clk,
rst => rst,
rst_sync => set_reset_mode);
MODE_REG_BASIC : can_register_asyn
GENERIC MAP (4, 0)
PORT MAP (
data_in => data_in(4 DOWNTO 1),
data_out => mode_basic(4 DOWNTO 1),
we => we_mode,
clk => clk,
rst => rst);
xhdl_61 <= (we_mode AND reset_mode_xhdl3);
MODE_REG_EXT : can_register_asyn
GENERIC MAP (3, 0)
PORT MAP (
data_in => data_in(3 DOWNTO 1),
data_out => mode_ext(3 DOWNTO 1),
we => xhdl_61,
clk => clk,
rst => rst);
reset_mode_xhdl3 <= mode ;
listen_only_mode_xhdl4 <= extended_mode_xhdl24 AND mode_ext(1) ;
self_test_mode_xhdl6 <= extended_mode_xhdl24 AND mode_ext(2) ;
acceptance_filter_mode_xhdl5 <= extended_mode_xhdl24 AND mode_ext(3) ;
receive_irq_en_basic <= mode_basic(1) ;
transmit_irq_en_basic <= mode_basic(2) ;
error_irq_en_basic <= mode_basic(3) ;
overrun_irq_en_basic <= mode_basic(4) ;
xhdl_69 <= (command(0) AND sample_point) OR reset_mode_xhdl3;
port_xhdl70 <= data_in(0);
command(0) <= port_xhdl71;
COMMAND_REG0 : can_register_asyn_syn
GENERIC MAP (1, 0)
PORT MAP (
data_in(0) => port_xhdl70,
data_out(0) => port_xhdl71,
we => we_command,
clk => clk,
rst => rst,
rst_sync => xhdl_69);
xhdl_77 <= (sample_point AND (tx_request_xhdl10 OR (abort_tx_xhdl9 AND NOT transmitting))) OR reset_mode_xhdl3;
port_xhdl78 <= data_in(1);
command(1) <= port_xhdl79;
COMMAND_REG1 : can_register_asyn_syn
GENERIC MAP (1, 0)
PORT MAP (
data_in(0) => port_xhdl78,
data_out(0) => port_xhdl79,
we => we_command,
clk => clk,
rst => rst,
rst_sync => xhdl_77);
xhdl_85 <= orv(command(3 DOWNTO 2)) OR reset_mode_xhdl3;
COMMAND_REG : can_register_asyn_syn
GENERIC MAP (2, 0)
PORT MAP (
data_in => data_in(3 DOWNTO 2),
data_out => command(3 DOWNTO 2),
we => we_command,
clk => clk,
rst => rst,
rst_sync => xhdl_85);
xhdl_91 <= (command(4) AND sample_point) OR reset_mode_xhdl3;
port_xhdl92 <= data_in(4);
command(4) <= port_xhdl93;
COMMAND_REG4 : can_register_asyn_syn
GENERIC MAP (1, 0)
PORT MAP (
data_in(0) => port_xhdl92,
data_out(0) => port_xhdl93,
we => we_command,
clk => clk,
rst => rst,
rst_sync => xhdl_91);
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
self_rx_request_xhdl11 <= '0';
ELSif clk'event and clk = '1' then
IF ((command(4) AND (NOT command(0))) = '1') THEN
self_rx_request_xhdl11 <= '1' ;
ELSE
IF (((NOT tx_state) AND tx_state_q) = '1') THEN
self_rx_request_xhdl11 <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
clear_data_overrun_xhdl7 <= command(3) ;
release_buffer_xhdl8 <= command(2) ;
tx_request_xhdl10 <= command(0) OR command(4) ;
abort_tx_xhdl9 <= command(1) AND (NOT tx_request_xhdl10) ;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
single_shot_transmission_xhdl12 <= '0';
ELSif clk'event and clk = '1' then
IF (((tx_request_xhdl10 AND command(1)) AND sample_point) = '1') THEN
single_shot_transmission_xhdl12 <= '1' ;
ELSE
IF (((NOT tx_state) AND tx_state_q) = '1') THEN
single_shot_transmission_xhdl12 <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
--
-- can_register_asyn_syn #(1, 1'h0) COMMAND_REG_OVERLOAD // Uncomment this to enable overload requests !!!
-- ( .data_in(data_in[5]),
-- .data_out(overload_request),
-- .we(we_command),
-- .clk(clk),
-- .rst(rst),
-- .rst_sync(overload_frame & ~overload_frame_q)
-- );
-- reg overload_frame_q;
-- always @ (posedge clk or posedge rst)
-- begin
-- if (rst)
-- overload_frame_q <= 1'b0;
-- else
-- overload_frame_q <=#Tp overload_frame;
-- end
--
overload_request_xhdl13 <= '0' ;
status(7) <= node_bus_off ;
status(6) <= error_status ;
status(5) <= transmit_status ;
status(4) <= receive_status ;
status(3) <= transmission_complete ;
status(2) <= transmit_buffer_status ;
status(1) <= overrun_status ;
status(0) <= receive_buffer_status ;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
transmission_complete <= '1';
ELSif clk'event and clk = '1' then
IF ((tx_successful AND ((NOT tx_successful_q) OR abort_tx_xhdl9)) = '1') THEN
-- transmission_complete was always set when abort_tx=1
-- Original code:
-- IF (((tx_successful AND (NOT tx_successful_q)) OR abort_tx_xhdl9) = '1') THEN
transmission_complete <= '1' ;
ELSE
IF (tx_request_xhdl10 = '1') THEN
transmission_complete <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
transmit_buffer_status <= '1';
ELSif clk'event and clk = '1' then
IF (tx_request_xhdl10 = '1') THEN
transmit_buffer_status <= '0' ;
ELSE
IF ((reset_mode_xhdl3 OR NOT need_to_tx) = '1') THEN
transmit_buffer_status <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
overrun_status <= '0';
ELSif clk'event and clk = '1' then
IF ((overrun AND (NOT overrun_q)) = '1') THEN
overrun_status <= '1' ;
ELSE
IF ((reset_mode_xhdl3 OR clear_data_overrun_xhdl7) = '1') THEN
overrun_status <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
receive_buffer_status <= '0';
ELSif clk'event and clk = '1' then
IF ((reset_mode_xhdl3 OR release_buffer_xhdl8) = '1') THEN
receive_buffer_status <= '0' ;
ELSE
IF (NOT info_empty = '1') THEN
receive_buffer_status <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
IRQ_EN_REG : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => irq_en_ext,
we => we_interrupt_enable,
clk => clk);
bus_error_irq_en <= irq_en_ext(7) ;
arbitration_lost_irq_en <= irq_en_ext(6) ;
error_passive_irq_en <= irq_en_ext(5) ;
data_overrun_irq_en_ext <= irq_en_ext(3) ;
error_warning_irq_en_ext <= irq_en_ext(2) ;
transmit_irq_en_ext <= irq_en_ext(1) ;
receive_irq_en_ext <= irq_en_ext(0) ;
BUS_TIMING_0_REG : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => bus_timing_0,
we => we_bus_timing_0,
clk => clk);
baud_r_presc_xhdl16 <= bus_timing_0(5 DOWNTO 0) ;
sync_jump_width_xhdl17 <= bus_timing_0(7 DOWNTO 6) ;
BUS_TIMING_1_REG : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => bus_timing_1,
we => we_bus_timing_1,
clk => clk);
time_segment1_xhdl18 <= bus_timing_1(3 DOWNTO 0) ;
time_segment2_xhdl19 <= bus_timing_1(6 DOWNTO 4) ;
triple_sampling_xhdl20 <= bus_timing_1(7) ;
-- End Bus Timing 1 register -- Error Warning Limit register
ERROR_WARNING_REG : can_register_asyn
GENERIC MAP (8, 96)
PORT MAP (
data_in => data_in,
data_out => error_warning_limit_xhdl21,
we => we_error_warning_limit,
clk => clk,
rst => rst);
port_xhdl116 <= data_in(7);
clock_divider(7) <= port_xhdl117;
CLOCK_DIVIDER_REG_7 : can_register_asyn
GENERIC MAP (1, 0)
PORT MAP (
data_in(0) => port_xhdl116,
data_out(0) => port_xhdl117,
we => we_clock_divider_hi,
clk => clk,
rst => rst);
clock_divider(6 DOWNTO 4) <= "000" ;
port_xhdl123 <= data_in(3);
clock_divider(3) <= port_xhdl124;
CLOCK_DIVIDER_REG_3 : can_register_asyn
GENERIC MAP (1, 0)
PORT MAP (
data_in(0) => port_xhdl123,
data_out(0) => port_xhdl124,
we => we_clock_divider_hi,
clk => clk,
rst => rst);
CLOCK_DIVIDER_REG_LOW : can_register_asyn
GENERIC MAP (3, 0)
PORT MAP (
data_in => data_in(2 DOWNTO 0),
data_out => clock_divider(2 DOWNTO 0),
we => we_clock_divider_low,
clk => clk,
rst => rst);
extended_mode_xhdl24 <= clock_divider(7) ;
clock_off <= clock_divider(3) ;
cd(2 DOWNTO 0) <= clock_divider(2 DOWNTO 0) ;
PROCESS (cd)
VARIABLE clkout_div_xhdl130 : std_logic_vector(2 DOWNTO 0);
BEGIN
CASE cd IS
-- synthesis full_case parallel_case
WHEN "000" =>
clkout_div_xhdl130 := "000";
WHEN "001" =>
clkout_div_xhdl130 := "001";
WHEN "010" =>
clkout_div_xhdl130 := "010";
WHEN "011" =>
clkout_div_xhdl130 := "011";
WHEN "100" =>
clkout_div_xhdl130 := "100";
WHEN "101" =>
clkout_div_xhdl130 := "101";
WHEN "110" =>
clkout_div_xhdl130 := "110";
WHEN "111" =>
clkout_div_xhdl130 := "000";
WHEN OTHERS =>
NULL;
END CASE;
clkout_div <= clkout_div_xhdl130;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
clkout_cnt <= "000";
ELSif clk'event and clk = '1' then
IF (clkout_cnt = clkout_div) THEN
clkout_cnt <= "000" ;
ELSE
clkout_cnt <= clkout_cnt + "001";
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
clkout_tmp <= '0';
ELSif clk'event and clk = '1' then
IF (clkout_cnt = clkout_div) THEN
clkout_tmp <= NOT clkout_tmp ;
END IF;
END IF;
END PROCESS;
temp_xhdl131 <= clk WHEN (andv(cd)) = '1' ELSE clkout_tmp;
temp_xhdl132 <= '1' WHEN clock_off = '1' ELSE (temp_xhdl131);
clkout_xhdl25 <= temp_xhdl132 ;
-- End Clock Divider register -- This section is for BASIC and EXTENDED mode -- Acceptance code register
ACCEPTANCE_CODE_REG0 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => acceptance_code_0_xhdl26,
we => we_acceptance_code_0,
clk => clk);
-- End: Acceptance code register -- Acceptance mask register
ACCEPTANCE_MASK_REG0 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => acceptance_mask_0_xhdl27,
we => we_acceptance_mask_0,
clk => clk);
-- End: Acceptance mask register -- End: This section is for BASIC and EXTENDED mode -- Tx data 0 register.
TX_DATA_REG0 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => tx_data_0_xhdl34,
we => we_tx_data_0,
clk => clk);
-- End: Tx data 0 register. -- Tx data 1 register.
TX_DATA_REG1 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => tx_data_1_xhdl35,
we => we_tx_data_1,
clk => clk);
-- End: Tx data 1 register. -- Tx data 2 register.
TX_DATA_REG2 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => tx_data_2_xhdl36,
we => we_tx_data_2,
clk => clk);
-- End: Tx data 2 register. -- Tx data 3 register.
TX_DATA_REG3 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => tx_data_3_xhdl37,
we => we_tx_data_3,
clk => clk);
-- End: Tx data 3 register. -- Tx data 4 register.
TX_DATA_REG4 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => tx_data_4_xhdl38,
we => we_tx_data_4,
clk => clk);
-- End: Tx data 4 register. -- Tx data 5 register.
TX_DATA_REG5 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => tx_data_5_xhdl39,
we => we_tx_data_5,
clk => clk);
-- End: Tx data 5 register. -- Tx data 6 register.
TX_DATA_REG6 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => tx_data_6_xhdl40,
we => we_tx_data_6,
clk => clk);
-- End: Tx data 6 register. -- Tx data 7 register.
TX_DATA_REG7 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => tx_data_7_xhdl41,
we => we_tx_data_7,
clk => clk);
-- End: Tx data 7 register. -- Tx data 8 register.
TX_DATA_REG8 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => tx_data_8_xhdl42,
we => we_tx_data_8,
clk => clk);
-- End: Tx data 8 register. -- Tx data 9 register.
TX_DATA_REG9 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => tx_data_9_xhdl43,
we => we_tx_data_9,
clk => clk);
-- End: Tx data 9 register. -- Tx data 10 register.
TX_DATA_REG10 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => tx_data_10_xhdl44,
we => we_tx_data_10,
clk => clk);
-- End: Tx data 10 register. -- Tx data 11 register.
TX_DATA_REG11 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => tx_data_11_xhdl45,
we => we_tx_data_11,
clk => clk);
-- End: Tx data 11 register. -- Tx data 12 register.
TX_DATA_REG12 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => tx_data_12_xhdl46,
we => we_tx_data_12,
clk => clk);
-- End: Tx data 12 register. -- This section is for EXTENDED mode -- Acceptance code register 1
ACCEPTANCE_CODE_REG1 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => acceptance_code_1_xhdl28,
we => we_acceptance_code_1,
clk => clk);
-- End: Acceptance code register -- Acceptance code register 2
ACCEPTANCE_CODE_REG2 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => acceptance_code_2_xhdl29,
we => we_acceptance_code_2,
clk => clk);
-- End: Acceptance code register -- Acceptance code register 3
ACCEPTANCE_CODE_REG3 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => acceptance_code_3_xhdl30,
we => we_acceptance_code_3,
clk => clk);
-- End: Acceptance code register -- Acceptance mask register 1
ACCEPTANCE_MASK_REG1 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => acceptance_mask_1_xhdl31,
we => we_acceptance_mask_1,
clk => clk);
-- End: Acceptance code register -- Acceptance mask register 2
ACCEPTANCE_MASK_REG2 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => acceptance_mask_2_xhdl32,
we => we_acceptance_mask_2,
clk => clk);
-- End: Acceptance code register -- Acceptance mask register 3
ACCEPTANCE_MASK_REG3 : can_register
GENERIC MAP (8)
PORT MAP (
data_in => data_in,
data_out => acceptance_mask_3_xhdl33,
we => we_acceptance_mask_3,
clk => clk);
temp_xhdl218 <= acceptance_code_0_xhdl26 WHEN reset_mode_xhdl3 = '1' ELSE "11111111";
temp_xhdl219 <= acceptance_mask_0_xhdl27 WHEN reset_mode_xhdl3 = '1' ELSE "11111111";
temp_xhdl220 <= bus_timing_0 WHEN reset_mode_xhdl3 = '1' ELSE "11111111";
temp_xhdl221 <= bus_timing_1 WHEN reset_mode_xhdl3 = '1' ELSE "11111111";
temp_xhdl222 <= "11111111" WHEN reset_mode_xhdl3 = '1' ELSE tx_data_0_xhdl34;
temp_xhdl223 <= "11111111" WHEN reset_mode_xhdl3 = '1' ELSE tx_data_1_xhdl35;
temp_xhdl224 <= "11111111" WHEN reset_mode_xhdl3 = '1' ELSE tx_data_2_xhdl36;
temp_xhdl225 <= "11111111" WHEN reset_mode_xhdl3 = '1' ELSE tx_data_3_xhdl37;
temp_xhdl226 <= "11111111" WHEN reset_mode_xhdl3 = '1' ELSE tx_data_4_xhdl38;
temp_xhdl227 <= "11111111" WHEN reset_mode_xhdl3 = '1' ELSE tx_data_5_xhdl39;
temp_xhdl228 <= "11111111" WHEN reset_mode_xhdl3 = '1' ELSE tx_data_6_xhdl40;
temp_xhdl229 <= "11111111" WHEN reset_mode_xhdl3 = '1' ELSE tx_data_7_xhdl41;
temp_xhdl230 <= "11111111" WHEN reset_mode_xhdl3 = '1' ELSE tx_data_8_xhdl42;
temp_xhdl231 <= "11111111" WHEN reset_mode_xhdl3 = '1' ELSE tx_data_9_xhdl43;
-- End: Acceptance code register -- End: This section is for EXTENDED mode -- Reading data from registers
PROCESS (addr, extended_mode_xhdl24, mode, bus_timing_0, bus_timing_1, clock_divider,
acceptance_code_0_xhdl26, acceptance_code_1_xhdl28, acceptance_code_2_xhdl29,
acceptance_code_3_xhdl30, acceptance_mask_0_xhdl27, acceptance_mask_1_xhdl31,
acceptance_mask_2_xhdl32, acceptance_mask_3_xhdl33, status,
error_warning_limit_xhdl21, rx_err_cnt, tx_err_cnt, irq_en_ext, irq_reg, mode_ext,
arbitration_lost_capture, rx_message_counter, mode_basic, error_capture_code,
temp_xhdl218, temp_xhdl219, temp_xhdl220, temp_xhdl221, temp_xhdl222, temp_xhdl223,
temp_xhdl224, temp_xhdl225, temp_xhdl226, temp_xhdl227, temp_xhdl228, temp_xhdl229,
temp_xhdl230, temp_xhdl231
)
VARIABLE data_out_xhdl1_xhdl217 : std_logic_vector(7 DOWNTO 0);
VARIABLE temp_xhdl232 : std_logic_vector(5 DOWNTO 0);
BEGIN
temp_xhdl232 := extended_mode_xhdl24 & addr(4 DOWNTO 0);
CASE temp_xhdl232 IS
WHEN "100000" =>
data_out_xhdl1_xhdl217 := "0000" & mode_ext(3 DOWNTO 1) & mode; -- extended mode
WHEN "100001" =>
data_out_xhdl1_xhdl217 := "00000000"; -- extended mode
WHEN "100010" =>
data_out_xhdl1_xhdl217 := status; -- extended mode
WHEN "100011" =>
data_out_xhdl1_xhdl217 := irq_reg; -- extended mode
WHEN "100100" =>
data_out_xhdl1_xhdl217 := irq_en_ext; -- extended mode
WHEN "100110" =>
data_out_xhdl1_xhdl217 := bus_timing_0; -- extended mode
WHEN "100111" =>
data_out_xhdl1_xhdl217 := bus_timing_1; -- extended mode
WHEN "101011" =>
data_out_xhdl1_xhdl217 := "000" & arbitration_lost_capture(4 DOWNTO 0); -- extended mode
WHEN "101100" =>
data_out_xhdl1_xhdl217 := error_capture_code; -- extended mode
WHEN "101101" =>
data_out_xhdl1_xhdl217 := error_warning_limit_xhdl21; -- extended mode
WHEN "101110" =>
data_out_xhdl1_xhdl217 := rx_err_cnt; -- extended mode
WHEN "101111" =>
data_out_xhdl1_xhdl217 := tx_err_cnt; -- extended mode
WHEN "110000" =>
data_out_xhdl1_xhdl217 := acceptance_code_0_xhdl26; -- extended mode
WHEN "110001" =>
data_out_xhdl1_xhdl217 := acceptance_code_1_xhdl28; -- extended mode
WHEN "110010" =>
data_out_xhdl1_xhdl217 := acceptance_code_2_xhdl29; -- extended mode
WHEN "110011" =>
data_out_xhdl1_xhdl217 := acceptance_code_3_xhdl30; -- extended mode
WHEN "110100" =>
data_out_xhdl1_xhdl217 := acceptance_mask_0_xhdl27; -- extended mode
WHEN "110101" =>
data_out_xhdl1_xhdl217 := acceptance_mask_1_xhdl31; -- extended mode
WHEN "110110" =>
data_out_xhdl1_xhdl217 := acceptance_mask_2_xhdl32; -- extended mode
WHEN "110111" =>
data_out_xhdl1_xhdl217 := acceptance_mask_3_xhdl33; -- extended mode
WHEN "111000" =>
data_out_xhdl1_xhdl217 := "00000000"; -- extended mode
WHEN "111001" =>
data_out_xhdl1_xhdl217 := "00000000"; -- extended mode
WHEN "111010" =>
data_out_xhdl1_xhdl217 := "00000000"; -- extended mode
WHEN "111011" =>
data_out_xhdl1_xhdl217 := "00000000"; -- extended mode
WHEN "111100" =>
data_out_xhdl1_xhdl217 := "00000000"; -- extended mode
WHEN "111101" =>
data_out_xhdl1_xhdl217 := '0' & rx_message_counter; -- extended mode
WHEN "111111" =>
data_out_xhdl1_xhdl217 := clock_divider; -- extended mode
WHEN "000000" =>
data_out_xhdl1_xhdl217 := "001" & mode_basic(4 DOWNTO 1) & mode; -- basic mode
WHEN "000001" =>
data_out_xhdl1_xhdl217 := "11111111"; -- basic mode
WHEN "000010" =>
data_out_xhdl1_xhdl217 := status; -- basic mode
WHEN "000011" =>
data_out_xhdl1_xhdl217 := "1110" & irq_reg(3 DOWNTO 0); -- basic mode
WHEN "000100" =>
data_out_xhdl1_xhdl217 := temp_xhdl218;
WHEN "000101" =>
data_out_xhdl1_xhdl217 := temp_xhdl219;
WHEN "000110" =>
data_out_xhdl1_xhdl217 := temp_xhdl220;
WHEN "000111" =>
data_out_xhdl1_xhdl217 := temp_xhdl221;
WHEN "001010" =>
data_out_xhdl1_xhdl217 := temp_xhdl222;
WHEN "001011" =>
data_out_xhdl1_xhdl217 := temp_xhdl223;
WHEN "001100" =>
data_out_xhdl1_xhdl217 := temp_xhdl224;
WHEN "001101" =>
data_out_xhdl1_xhdl217 := temp_xhdl225;
WHEN "001110" =>
data_out_xhdl1_xhdl217 := temp_xhdl226;
WHEN "001111" =>
data_out_xhdl1_xhdl217 := temp_xhdl227;
WHEN "010000" =>
data_out_xhdl1_xhdl217 := temp_xhdl228;
WHEN "010001" =>
data_out_xhdl1_xhdl217 := temp_xhdl229;
WHEN "010010" =>
data_out_xhdl1_xhdl217 := temp_xhdl230;
WHEN "010011" =>
data_out_xhdl1_xhdl217 := temp_xhdl231;
WHEN "011111" =>
data_out_xhdl1_xhdl217 := clock_divider; -- basic mode
WHEN OTHERS =>
data_out_xhdl1_xhdl217 := "00000000"; -- the rest is read as 0
END CASE;
data_out_xhdl1 <= data_out_xhdl1_xhdl217;
END PROCESS;
temp_xhdl233 <= data_overrun_irq_en_ext WHEN extended_mode_xhdl24 = '1' ELSE overrun_irq_en_basic;
data_overrun_irq_en <= temp_xhdl233 ;
temp_xhdl234 <= error_warning_irq_en_ext WHEN extended_mode_xhdl24 = '1' ELSE error_irq_en_basic;
error_warning_irq_en <= temp_xhdl234 ;
temp_xhdl235 <= transmit_irq_en_ext WHEN extended_mode_xhdl24 = '1' ELSE transmit_irq_en_basic;
transmit_irq_en <= temp_xhdl235 ;
temp_xhdl236 <= receive_irq_en_ext WHEN extended_mode_xhdl24 = '1' ELSE receive_irq_en_basic;
receive_irq_en <= temp_xhdl236 ;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
data_overrun_irq <= '0';
ELSif clk'event and clk = '1' then
IF (((overrun AND (NOT overrun_q)) AND data_overrun_irq_en) = '1') THEN
data_overrun_irq <= '1' ;
ELSE
IF ((reset_mode_xhdl3 OR reset_irq_reg) = '1') THEN
data_overrun_irq <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
transmit_irq <= '0';
ELSif clk'event and clk = '1' then
IF ((reset_mode_xhdl3 OR reset_irq_reg) = '1') THEN
transmit_irq <= '0' ;
ELSE
IF (((transmit_buffer_status AND (NOT transmit_buffer_status_q)) AND transmit_irq_en) = '1') THEN
transmit_irq <= '1' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
receive_irq <= '0';
ELSif clk'event and clk = '1' then
IF ((((NOT info_empty) AND (NOT receive_irq)) AND receive_irq_en) = '1') THEN
receive_irq <= '1' ;
ELSE
IF ((reset_mode_xhdl3 OR release_buffer_xhdl8) = '1') THEN
receive_irq <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
error_irq <= '0';
ELSif clk'event and clk = '1' then
IF ((((error_status XOR error_status_q) OR (node_bus_off XOR node_bus_off_q)) AND error_warning_irq_en) = '1') THEN
error_irq <= '1' ;
ELSE
IF (reset_irq_reg = '1') THEN
error_irq <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
bus_error_irq <= '0';
ELSif clk'event and clk = '1' then
IF ((set_bus_error_irq AND bus_error_irq_en) = '1') THEN
bus_error_irq <= '1' ;
ELSE
IF ((reset_mode_xhdl3 OR reset_irq_reg) = '1') THEN
bus_error_irq <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
arbitration_lost_irq <= '0';
ELSif clk'event and clk = '1' then
IF ((set_arbitration_lost_irq AND arbitration_lost_irq_en) = '1') THEN
arbitration_lost_irq <= '1' ;
ELSE
IF ((reset_mode_xhdl3 OR reset_irq_reg) = '1') THEN
arbitration_lost_irq <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
error_passive_irq <= '0';
ELSif clk'event and clk = '1' then
IF ((((node_error_passive AND (NOT node_error_passive_q)) OR (((NOT node_error_passive) AND node_error_passive_q) AND node_error_active)) AND error_passive_irq_en) = '1') THEN
error_passive_irq <= '1' ;
ELSE
IF ((reset_mode_xhdl3 OR reset_irq_reg) = '1') THEN
error_passive_irq <= '0' ;
END IF;
END IF;
END IF;
END PROCESS;
irq_reg <= bus_error_irq & arbitration_lost_irq & error_passive_irq & '0' & data_overrun_irq & error_irq & transmit_irq & receive_irq ;
irq <= data_overrun_irq OR transmit_irq OR receive_irq OR error_irq OR bus_error_irq OR arbitration_lost_irq OR error_passive_irq ;
-- irq_o reset change /Kristoffer 2006-02-23 PROCESS (clk, rst)
-- BEGIN
-- IF (rst = '1') THEN
-- irq_n_xhdl2 <= '1';
-- ELSif clk'event and clk = '1' then
-- IF (reset_irq_reg = '1' or release_buffer_xhdl8='1') THEN
-- irq_n_xhdl2 <= '1';
-- ELSE
-- IF (irq = '1') THEN
-- irq_n_xhdl2 <= '0' ;
-- END IF;
-- END IF;
-- END IF;
-- END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1' or release_buffer_xhdl8 = '1') THEN
irq_n_xhdl2 <= '1';
ELSif clk'event and clk = '1' then
irq_n_xhdl2 <= not irq;
END IF;
END PROCESS;
END ARCHITECTURE RTL;
----------------------------------------------------------------------------------------------
--
-- VHDL file generated by X-HDL - Revision 3.2.53 Aug. 1, 2005
-- Tue Aug 9 07:33:50 2005
--
-- Input file : C:/Documents and Settings/BryantI/My Documents/tmp/can_top.v
-- Design name : can_top
-- Author :
-- Company : Actel
--
-- Description :
--
--
----------------------------------------------------------------------------------------------
--
--////////////////////////////////////////////////////////////////////
--// ////
--// can_top.v ////
--// ////
--// ////
--// This file is part of the CAN Protocol Controller ////
--// http://www.opencores.org/projects/can/ ////
--// ////
--// ////
--// Author(s): ////
--// Igor Mohor ////
--// [email protected] ////
--// ////
--// ////
--// All additional information is available in the README.txt ////
--// file. ////
--// ////
--////////////////////////////////////////////////////////////////////
--// ////
--// Copyright (C) 2002, 2003, 2004 Authors ////
--// ////
--// This source file may be used and distributed without ////
--// restriction provided that this copyright statement is not ////
--// removed from the file and that any derivative work contains ////
--// the original copyright notice and the associated disclaimer. ////
--// ////
--// This source file is free software; you can redistribute it ////
--// and/or modify it under the terms of the GNU Lesser General ////
--// Public License as published by the Free Software Foundation; ////
--// either version 2.1 of the License, or (at your option) any ////
--// later version. ////
--// ////
--// This source is distributed in the hope that it will be ////
--// useful, but WITHOUT ANY WARRANTY; without even the implied ////
--// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
--// PURPOSE. See the GNU Lesser General Public License for more ////
--// details. ////
--// ////
--// You should have received a copy of the GNU Lesser General ////
--// Public License along with this source; if not, download it ////
--// from http://www.opencores.org/lgpl.shtml ////
--// ////
--// The CAN protocol is developed by Robert Bosch GmbH and ////
--// protected by patents. Anybody who wants to implement this ////
--// CAN IP core on silicon has to obtain a CAN protocol license ////
--// from Bosch. ////
--// ////
--////////////////////////////////////////////////////////////////////
--
-- CVS Revision History
--
-- $Log: can_top.v,v $
-- Revision 1.48 2004/10/25 11:44:47 igorm
-- Interrupt is always cleared for one clock after the irq register is read.
-- This fixes problems when CPU is using IRQs that are edge triggered.
--
-- Revision 1.47 2004/02/08 14:53:54 mohor
-- Header changed. Address latched to posedge. bus_off_on signal added.
--
-- Revision 1.46 2003/10/17 05:55:20 markom
-- mbist signals updated according to newest convention
--
-- Revision 1.45 2003/09/30 00:55:13 mohor
-- Error counters fixed to be compatible with Bosch VHDL reference model.
-- Small synchronization changes.
--
-- Revision 1.44 2003/09/25 18:55:49 mohor
-- Synchronization changed, error counters fixed.
--
-- Revision 1.43 2003/08/20 09:57:39 mohor
-- Tristate signal tx_o is separated to tx_o and tx_oen_o. Both signals need
-- to be joined together on higher level.
--
-- Revision 1.42 2003/07/16 15:11:28 mohor
-- Fixed according to the linter.
--
-- Revision 1.41 2003/07/10 15:32:27 mohor
-- Unused signal removed.
--
-- Revision 1.40 2003/07/10 01:59:04 tadejm
-- Synchronization fixed. In some strange cases it didn't work according to
-- the VHDL reference model.
--
-- Revision 1.39 2003/07/07 11:21:37 mohor
-- Little fixes (to fix warnings).
--
-- Revision 1.38 2003/07/03 09:32:20 mohor
-- Synchronization changed.
--
-- Revision 1.37 2003/06/27 20:56:15 simons
-- Virtual silicon ram instances added.
--
-- Revision 1.36 2003/06/17 14:30:30 mohor
-- "chip select" signal cs_can_i is used only when not using WISHBONE
-- interface.
--
-- Revision 1.35 2003/06/16 13:57:58 mohor
-- tx_point generated one clk earlier. rx_i registered. Data corrected when
-- using extended mode.
--
-- Revision 1.34 2003/06/13 15:02:24 mohor
-- Synchronization is also needed when transmitting a message.
--
-- Revision 1.33 2003/06/11 14:21:35 mohor
-- When switching to tx, sync stage is overjumped.
--
-- Revision 1.32 2003/06/09 11:32:36 mohor
-- Ports added for the CAN_BIST.
--
-- Revision 1.31 2003/03/26 11:19:46 mohor
-- CAN interrupt is active low.
--
-- Revision 1.30 2003/03/20 17:01:17 mohor
-- unix.
--
-- Revision 1.28 2003/03/14 19:36:48 mohor
-- can_cs signal used for generation of the cs.
--
-- Revision 1.27 2003/03/12 05:56:33 mohor
-- Bidirectional port_0_i changed to port_0_io.
-- input cs_can changed to cs_can_i.
--
-- Revision 1.26 2003/03/12 04:39:40 mohor
-- rd_i and wr_i are active high signals. If 8051 is connected, these two signals
-- need to be negated one level higher.
--
-- Revision 1.25 2003/03/12 04:17:36 mohor
-- 8051 interface added (besides WISHBONE interface). Selection is made in
-- can_defines.v file.
--
-- Revision 1.24 2003/03/10 17:24:40 mohor
-- wire declaration added.
--
-- Revision 1.23 2003/03/05 15:33:13 mohor
-- tx_o is now tristated signal. tx_oen and tx_o combined together.
--
-- Revision 1.22 2003/03/05 15:01:56 mohor
-- Top level signal names changed.
--
-- Revision 1.21 2003/03/01 22:53:33 mohor
-- Actel APA ram supported.
--
-- Revision 1.20 2003/02/19 15:09:02 mohor
-- Incomplete sensitivity list fixed.
--
-- Revision 1.19 2003/02/19 15:04:14 mohor
-- Typo fixed.
--
-- Revision 1.18 2003/02/19 14:44:03 mohor
-- CAN core finished. Host interface added. Registers finished.
-- Synchronization to the wishbone finished.
--
-- Revision 1.17 2003/02/18 00:10:15 mohor
-- Most of the registers added. Registers "arbitration lost capture", "error code
-- capture" + few more still need to be added.
--
-- Revision 1.16 2003/02/14 20:17:01 mohor
-- Several registers added. Not finished, yet.
--
-- Revision 1.15 2003/02/12 14:25:30 mohor
-- abort_tx added.
--
-- Revision 1.14 2003/02/11 00:56:06 mohor
-- Wishbone interface added.
--
-- Revision 1.13 2003/02/09 18:40:29 mohor
-- Overload fixed. Hard synchronization also enabled at the last bit of
-- interframe.
--
-- Revision 1.12 2003/02/09 02:24:33 mohor
-- Bosch license warning added. Error counters finished. Overload frames
-- still need to be fixed.
--
-- Revision 1.11 2003/02/04 14:34:52 mohor
-- *** empty log message ***
--
-- Revision 1.10 2003/01/31 01:13:38 mohor
-- backup.
--
-- Revision 1.9 2003/01/15 13:16:48 mohor
-- When a frame with "remote request" is received, no data is stored to
-- fifo, just the frame information (identifier, ...). Data length that
-- is stored is the received data length and not the actual data length
-- that is stored to fifo.
--
-- Revision 1.8 2003/01/14 17:25:09 mohor
-- Addresses corrected to decimal values (previously hex).
--
-- Revision 1.7 2003/01/10 17:51:34 mohor
-- Temporary version (backup).
--
-- Revision 1.6 2003/01/09 21:54:45 mohor
-- rx fifo added. Not 100 % verified, yet.
--
-- Revision 1.5 2003/01/08 02:10:56 mohor
-- Acceptance filter added.
--
-- Revision 1.4 2002/12/28 04:13:23 mohor
-- Backup version.
--
-- Revision 1.3 2002/12/27 00:12:52 mohor
-- Header changed, testbench improved to send a frame (crc still missing).
--
-- Revision 1.2 2002/12/26 16:00:34 mohor
-- Testbench define file added. Clock divider register added.
--
-- Revision 1.1.1.1 2002/12/20 16:39:21 mohor
-- Initial
--
--
--
-- synopsys translate_off
--`include "can_defines.v"
-- synopsys translate_on
LIBRARY ieee;
USE ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
ENTITY can_top IS
PORT (
-- wb_clk_i : IN std_logic;
-- wb_rst_i : IN std_logic;
-- wb_dat_i : IN std_logic_vector(7 DOWNTO 0);
-- wb_dat_o : OUT std_logic_vector(7 DOWNTO 0);
-- wb_cyc_i : IN std_logic;
-- wb_stb_i : IN std_logic;
-- wb_we_i : IN std_logic;
-- wb_adr_i : IN std_logic_vector(7 DOWNTO 0);
-- wb_ack_o : OUT std_logic;
rst : IN std_logic;
addr : IN std_logic_vector(7 DOWNTO 0);
data_in : IN std_logic_vector(7 DOWNTO 0);
data_out : OUT std_logic_vector(7 DOWNTO 0);
cs : IN std_logic;
we : IN std_logic;
clk_i : IN std_logic;
rx_i : IN std_logic;
tx_o : OUT std_logic;
bus_off_on : OUT std_logic;
irq_on : OUT std_logic;
clkout_o : OUT std_logic;
-- Bist
-- port connections for Ram
--64x8
q_dp_64x8 : IN std_logic_vector(7 DOWNTO 0);
data_64x8 : OUT std_logic_vector(7 DOWNTO 0);
wren_64x8 : OUT std_logic;
rden_64x8 : OUT std_logic;
wraddress_64x8 : OUT std_logic_vector(5 DOWNTO 0);
rdaddress_64x8 : OUT std_logic_vector(5 DOWNTO 0);
--64x4
q_dp_64x4 : IN std_logic_vector(3 DOWNTO 0);
data_64x4 : OUT std_logic_vector(3 DOWNTO 0);
wren_64x4x1 : OUT std_logic;
wraddress_64x4x1 : OUT std_logic_vector(5 DOWNTO 0);
rdaddress_64x4x1 : OUT std_logic_vector(5 DOWNTO 0);
--64x1
q_dp_64x1 : IN std_logic;
data_64x1 : OUT std_logic);
END ENTITY can_top;
ARCHITECTURE RTL OF can_top IS
COMPONENT can_bsp
PORT (
clk : IN std_logic;
rst : IN std_logic;
sample_point : IN std_logic;
sampled_bit : IN std_logic;
sampled_bit_q : IN std_logic;
tx_point : IN std_logic;
hard_sync : IN std_logic;
addr : IN std_logic_vector(7 DOWNTO 0);
data_in : IN std_logic_vector(7 DOWNTO 0);
data_out : OUT std_logic_vector(7 DOWNTO 0);
fifo_selected : IN std_logic;
reset_mode : IN std_logic;
listen_only_mode : IN std_logic;
acceptance_filter_mode : IN std_logic;
self_test_mode : IN std_logic;
release_buffer : IN std_logic;
tx_request : IN std_logic;
abort_tx : IN std_logic;
self_rx_request : IN std_logic;
single_shot_transmission: IN std_logic;
tx_state : OUT std_logic;
tx_state_q : OUT std_logic;
overload_request : IN std_logic;
overload_frame : OUT std_logic;
read_arbitration_lost_capture_reg: IN std_logic;
read_error_code_capture_reg: IN std_logic;
error_capture_code : OUT std_logic_vector(7 DOWNTO 0);
error_warning_limit : IN std_logic_vector(7 DOWNTO 0);
we_rx_err_cnt : IN std_logic;
we_tx_err_cnt : IN std_logic;
extended_mode : IN std_logic;
rx_idle : OUT std_logic;
transmitting : OUT std_logic;
transmitter : OUT std_logic;
go_rx_inter : OUT std_logic;
not_first_bit_of_inter : OUT std_logic;
rx_inter : OUT std_logic;
set_reset_mode : OUT std_logic;
node_bus_off : OUT std_logic;
error_status : OUT std_logic;
rx_err_cnt : OUT std_logic_vector(8 DOWNTO 0);
tx_err_cnt : OUT std_logic_vector(8 DOWNTO 0);
transmit_status : OUT std_logic;
receive_status : OUT std_logic;
tx_successful : OUT std_logic;
need_to_tx : OUT std_logic;
overrun : OUT std_logic;
info_empty : OUT std_logic;
set_bus_error_irq : OUT std_logic;
set_arbitration_lost_irq: OUT std_logic;
arbitration_lost_capture: OUT std_logic_vector(4 DOWNTO 0);
node_error_passive : OUT std_logic;
node_error_active : OUT std_logic;
rx_message_counter : OUT std_logic_vector(6 DOWNTO 0);
acceptance_code_0 : IN std_logic_vector(7 DOWNTO 0);
acceptance_mask_0 : IN std_logic_vector(7 DOWNTO 0);
acceptance_code_1 : IN std_logic_vector(7 DOWNTO 0);
acceptance_code_2 : IN std_logic_vector(7 DOWNTO 0);
acceptance_code_3 : IN std_logic_vector(7 DOWNTO 0);
acceptance_mask_1 : IN std_logic_vector(7 DOWNTO 0);
acceptance_mask_2 : IN std_logic_vector(7 DOWNTO 0);
acceptance_mask_3 : IN std_logic_vector(7 DOWNTO 0);
tx_data_0 : IN std_logic_vector(7 DOWNTO 0);
tx_data_1 : IN std_logic_vector(7 DOWNTO 0);
tx_data_2 : IN std_logic_vector(7 DOWNTO 0);
tx_data_3 : IN std_logic_vector(7 DOWNTO 0);
tx_data_4 : IN std_logic_vector(7 DOWNTO 0);
tx_data_5 : IN std_logic_vector(7 DOWNTO 0);
tx_data_6 : IN std_logic_vector(7 DOWNTO 0);
tx_data_7 : IN std_logic_vector(7 DOWNTO 0);
tx_data_8 : IN std_logic_vector(7 DOWNTO 0);
tx_data_9 : IN std_logic_vector(7 DOWNTO 0);
tx_data_10 : IN std_logic_vector(7 DOWNTO 0);
tx_data_11 : IN std_logic_vector(7 DOWNTO 0);
tx_data_12 : IN std_logic_vector(7 DOWNTO 0);
tx : OUT std_logic;
tx_next : OUT std_logic;
bus_off_on : OUT std_logic;
go_overload_frame : OUT std_logic;
go_error_frame : OUT std_logic;
go_tx : OUT std_logic;
send_ack : OUT std_logic;
q_dp_64x8 : IN std_logic_vector(7 DOWNTO 0);
data_64x8 : OUT std_logic_vector(7 DOWNTO 0);
wren_64x8 : OUT std_logic;
rden_64x8 : OUT std_logic;
wraddress_64x8 : OUT std_logic_vector(5 DOWNTO 0);
rdaddress_64x8 : OUT std_logic_vector(5 DOWNTO 0);
q_dp_64x4 : IN std_logic_vector(3 DOWNTO 0);
data_64x4 : OUT std_logic_vector(3 DOWNTO 0);
wren_64x4x1 : OUT std_logic;
wraddress_64x4x1 : OUT std_logic_vector(5 DOWNTO 0);
rdaddress_64x4x1 : OUT std_logic_vector(5 DOWNTO 0);
q_dp_64x1 : IN std_logic;
data_64x1 : OUT std_logic);
END COMPONENT;
COMPONENT can_btl
PORT (
clk : IN std_logic;
rst : IN std_logic;
rx : IN std_logic;
tx : IN std_logic;
baud_r_presc : IN std_logic_vector(5 DOWNTO 0);
sync_jump_width : IN std_logic_vector(1 DOWNTO 0);
time_segment1 : IN std_logic_vector(3 DOWNTO 0);
time_segment2 : IN std_logic_vector(2 DOWNTO 0);
triple_sampling : IN std_logic;
sample_point : OUT std_logic;
sampled_bit : OUT std_logic;
sampled_bit_q : OUT std_logic;
tx_point : OUT std_logic;
hard_sync : OUT std_logic;
rx_idle : IN std_logic;
rx_inter : IN std_logic;
transmitting : IN std_logic;
transmitter : IN std_logic;
go_rx_inter : IN std_logic;
tx_next : IN std_logic;
go_overload_frame : IN std_logic;
go_error_frame : IN std_logic;
go_tx : IN std_logic;
send_ack : IN std_logic;
node_error_passive : IN std_logic);
END COMPONENT;
COMPONENT can_registers
PORT (
clk : IN std_logic;
rst : IN std_logic;
cs : IN std_logic;
we : IN std_logic;
addr : IN std_logic_vector(7 DOWNTO 0);
data_in : IN std_logic_vector(7 DOWNTO 0);
data_out : OUT std_logic_vector(7 DOWNTO 0);
irq_n : OUT std_logic;
sample_point : IN std_logic;
transmitting : IN std_logic;
set_reset_mode : IN std_logic;
node_bus_off : IN std_logic;
error_status : IN std_logic;
rx_err_cnt : IN std_logic_vector(7 DOWNTO 0);
tx_err_cnt : IN std_logic_vector(7 DOWNTO 0);
transmit_status : IN std_logic;
receive_status : IN std_logic;
tx_successful : IN std_logic;
need_to_tx : IN std_logic;
overrun : IN std_logic;
info_empty : IN std_logic;
set_bus_error_irq : IN std_logic;
set_arbitration_lost_irq: IN std_logic;
arbitration_lost_capture: IN std_logic_vector(4 DOWNTO 0);
node_error_passive : IN std_logic;
node_error_active : IN std_logic;
rx_message_counter : IN std_logic_vector(6 DOWNTO 0);
reset_mode : OUT std_logic;
listen_only_mode : OUT std_logic;
acceptance_filter_mode : OUT std_logic;
self_test_mode : OUT std_logic;
clear_data_overrun : OUT std_logic;
release_buffer : OUT std_logic;
abort_tx : OUT std_logic;
tx_request : OUT std_logic;
self_rx_request : OUT std_logic;
single_shot_transmission: OUT std_logic;
tx_state : IN std_logic;
tx_state_q : IN std_logic;
overload_request : OUT std_logic;
overload_frame : IN std_logic;
read_arbitration_lost_capture_reg: OUT std_logic;
read_error_code_capture_reg: OUT std_logic;
error_capture_code : IN std_logic_vector(7 DOWNTO 0);
baud_r_presc : OUT std_logic_vector(5 DOWNTO 0);
sync_jump_width : OUT std_logic_vector(1 DOWNTO 0);
time_segment1 : OUT std_logic_vector(3 DOWNTO 0);
time_segment2 : OUT std_logic_vector(2 DOWNTO 0);
triple_sampling : OUT std_logic;
error_warning_limit : OUT std_logic_vector(7 DOWNTO 0);
we_rx_err_cnt : OUT std_logic;
we_tx_err_cnt : OUT std_logic;
extended_mode : OUT std_logic;
clkout : OUT std_logic;
acceptance_code_0 : OUT std_logic_vector(7 DOWNTO 0);
acceptance_mask_0 : OUT std_logic_vector(7 DOWNTO 0);
acceptance_code_1 : OUT std_logic_vector(7 DOWNTO 0);
acceptance_code_2 : OUT std_logic_vector(7 DOWNTO 0);
acceptance_code_3 : OUT std_logic_vector(7 DOWNTO 0);
acceptance_mask_1 : OUT std_logic_vector(7 DOWNTO 0);
acceptance_mask_2 : OUT std_logic_vector(7 DOWNTO 0);
acceptance_mask_3 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_0 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_1 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_2 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_3 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_4 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_5 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_6 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_7 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_8 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_9 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_10 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_11 : OUT std_logic_vector(7 DOWNTO 0);
tx_data_12 : OUT std_logic_vector(7 DOWNTO 0));
END COMPONENT;
-- SIGNAL cs_sync1 : std_logic;
-- SIGNAL cs_sync2 : std_logic;
-- SIGNAL cs_sync3 : std_logic;
-- SIGNAL cs_ack1 : std_logic;
-- SIGNAL cs_ack2 : std_logic;
-- SIGNAL cs_ack3 : std_logic;
-- SIGNAL cs_sync_rst1 : std_logic;
-- SIGNAL cs_sync_rst2 : std_logic;
-- SIGNAL cs_can_i : std_logic;
---------------------------------
SIGNAL data_out_fifo_selected : std_logic;
SIGNAL data_out_fifo : std_logic_vector(7 DOWNTO 0);
SIGNAL data_out_regs : std_logic_vector(7 DOWNTO 0);
-- Mode register
SIGNAL reset_mode : std_logic;
SIGNAL listen_only_mode : std_logic;
SIGNAL acceptance_filter_mode : std_logic;
SIGNAL self_test_mode : std_logic;
-- Command register
SIGNAL release_buffer : std_logic;
SIGNAL tx_request : std_logic;
SIGNAL abort_tx : std_logic;
SIGNAL self_rx_request : std_logic;
SIGNAL single_shot_transmission : std_logic;
SIGNAL tx_state : std_logic;
SIGNAL tx_state_q : std_logic;
SIGNAL overload_request : std_logic;
SIGNAL overload_frame : std_logic;
-- Arbitration Lost Capture Register
SIGNAL read_arbitration_lost_capture_reg: std_logic;
-- Error Code Capture Register
SIGNAL read_error_code_capture_reg : std_logic;
SIGNAL error_capture_code : std_logic_vector(7 DOWNTO 0);
-- Bus Timing 0 register
SIGNAL baud_r_presc : std_logic_vector(5 DOWNTO 0);
SIGNAL sync_jump_width : std_logic_vector(1 DOWNTO 0);
-- Bus Timing 1 register
SIGNAL time_segment1 : std_logic_vector(3 DOWNTO 0);
SIGNAL time_segment2 : std_logic_vector(2 DOWNTO 0);
SIGNAL triple_sampling : std_logic;
-- Error Warning Limit register
SIGNAL error_warning_limit : std_logic_vector(7 DOWNTO 0);
-- Rx Error Counter register
SIGNAL we_rx_err_cnt : std_logic;
-- Tx Error Counter register
SIGNAL we_tx_err_cnt : std_logic;
-- Clock Divider register
SIGNAL extended_mode : std_logic;
-- This section is for BASIC and EXTENDED mode
-- Acceptance code register
SIGNAL acceptance_code_0 : std_logic_vector(7 DOWNTO 0);
-- Acceptance mask register
SIGNAL acceptance_mask_0 : std_logic_vector(7 DOWNTO 0);
-- End: This section is for BASIC and EXTENDED mode
-- This section is for EXTENDED mode
-- Acceptance code register
SIGNAL acceptance_code_1 : std_logic_vector(7 DOWNTO 0);
SIGNAL acceptance_code_2 : std_logic_vector(7 DOWNTO 0);
SIGNAL acceptance_code_3 : std_logic_vector(7 DOWNTO 0);
-- Acceptance mask register
SIGNAL acceptance_mask_1 : std_logic_vector(7 DOWNTO 0);
SIGNAL acceptance_mask_2 : std_logic_vector(7 DOWNTO 0);
SIGNAL acceptance_mask_3 : std_logic_vector(7 DOWNTO 0);
-- End: This section is for EXTENDED mode
-- Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data
SIGNAL tx_data_0 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_1 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_2 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_3 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_4 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_5 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_6 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_7 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_8 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_9 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_10 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_11 : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_data_12 : std_logic_vector(7 DOWNTO 0);
-- End: Tx data registers
-- SIGNAL cs : std_logic;
-- Output signals from can_btl module
SIGNAL sample_point : std_logic;
SIGNAL sampled_bit : std_logic;
SIGNAL sampled_bit_q : std_logic;
SIGNAL tx_point : std_logic;
SIGNAL hard_sync : std_logic;
-- output from can_bsp module
SIGNAL rx_idle : std_logic;
SIGNAL transmitting : std_logic;
SIGNAL transmitter : std_logic;
SIGNAL go_rx_inter : std_logic;
SIGNAL not_first_bit_of_inter : std_logic;
SIGNAL set_reset_mode : std_logic;
SIGNAL node_bus_off : std_logic;
SIGNAL error_status : std_logic;
SIGNAL rx_err_cnt : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_err_cnt : std_logic_vector(7 DOWNTO 0);
SIGNAL rx_err_cnt_dummy : std_logic; -- The MSB is not displayed. It is just used for easier calculation (no counter overflow).
SIGNAL tx_err_cnt_dummy : std_logic; -- The MSB is not displayed. It is just used for easier calculation (no counter overflow).
SIGNAL transmit_status : std_logic;
SIGNAL receive_status : std_logic;
SIGNAL tx_successful : std_logic;
SIGNAL need_to_tx : std_logic;
SIGNAL overrun : std_logic;
SIGNAL info_empty : std_logic;
SIGNAL set_bus_error_irq : std_logic;
SIGNAL set_arbitration_lost_irq : std_logic;
SIGNAL arbitration_lost_capture : std_logic_vector(4 DOWNTO 0);
SIGNAL node_error_passive : std_logic;
SIGNAL node_error_active : std_logic;
SIGNAL rx_message_counter : std_logic_vector(6 DOWNTO 0);
SIGNAL tx_next : std_logic;
SIGNAL go_overload_frame : std_logic;
SIGNAL go_error_frame : std_logic;
SIGNAL go_tx : std_logic;
SIGNAL send_ack : std_logic;
-- SIGNAL rst : std_logic;
-- SIGNAL we : std_logic;
-- SIGNAL addr : std_logic_vector(7 DOWNTO 0);
-- SIGNAL data_in : std_logic_vector(7 DOWNTO 0);
-- SIGNAL data_out : std_logic_vector(7 DOWNTO 0);
SIGNAL rx_sync_tmp : std_logic;
SIGNAL rx_sync : std_logic;
-- port connections for Ram
--64x8
SIGNAL w_q_dp_64x8 : std_logic_vector(7 DOWNTO 0);
SIGNAL w_data_64x8 : std_logic_vector(7 DOWNTO 0);
SIGNAL w_wren_64x8 : std_logic;
SIGNAL w_rden_64x8 : std_logic;
SIGNAL w_wraddress_64x8 : std_logic_vector(5 DOWNTO 0);
SIGNAL w_rdaddress_64x8 : std_logic_vector(5 DOWNTO 0);
--64x4
SIGNAL w_q_dp_64x4 : std_logic_vector(3 DOWNTO 0);
SIGNAL w_data_64x4 : std_logic_vector(3 DOWNTO 0);
SIGNAL w_wren_64x4x1 : std_logic;
SIGNAL w_wraddress_64x4x1 : std_logic_vector(5 DOWNTO 0);
SIGNAL w_rdaddress_64x4x1 : std_logic_vector(5 DOWNTO 0);
--64x1
SIGNAL w_q_dp_64x1 : std_logic;
SIGNAL w_data_64x1 : std_logic;
-- From btl module
-- Mode register
-- Command register
-- Arbitration Lost Capture Register
-- Error Code Capture Register
-- Error Warning Limit register
-- Rx Error Counter register
-- Tx Error Counter register
-- Clock Divider register
-- output from can_bsp module
SIGNAL xhdl_148 : std_logic_vector(8 DOWNTO 0);
-- The MSB is not displayed. It is just used for easier calculation (no counter overflow).
SIGNAL xhdl_150 : std_logic_vector(8 DOWNTO 0);
-- SIGNAL wb_dat_o_xhdl1 : std_logic_vector(7 DOWNTO 0);
-- SIGNAL wb_ack_o_xhdl2 : std_logic;
SIGNAL tx_o_xhdl3 : std_logic;
SIGNAL bus_off_on_xhdl4 : std_logic;
SIGNAL irq_on_xhdl5 : std_logic;
SIGNAL clkout_o_xhdl6 : std_logic;
SIGNAL data_64x8_xhdl7 : std_logic_vector(7 DOWNTO 0);
SIGNAL wren_64x8_xhdl8 : std_logic;
SIGNAL rden_64x8_xhdl9 : std_logic;
SIGNAL wraddress_64x8_xhdl10 : std_logic_vector(5 DOWNTO 0);
SIGNAL rdaddress_64x8_xhdl11 : std_logic_vector(5 DOWNTO 0);
SIGNAL data_64x4_xhdl12 : std_logic_vector(3 DOWNTO 0);
SIGNAL wren_64x4x1_xhdl13 : std_logic;
SIGNAL wraddress_64x4x1_xhdl14 : std_logic_vector(5 DOWNTO 0);
SIGNAL rdaddress_64x4x1_xhdl15 : std_logic_vector(5 DOWNTO 0);
SIGNAL data_64x1_xhdl16 : std_logic;
SIGNAL rx_inter : std_logic;
BEGIN
-- wb_dat_o <= wb_dat_o_xhdl1;
-- wb_ack_o <= wb_ack_o_xhdl2;
tx_o <= tx_o_xhdl3;
bus_off_on <= bus_off_on_xhdl4;
irq_on <= irq_on_xhdl5;
clkout_o <= clkout_o_xhdl6;
data_64x8 <= data_64x8_xhdl7;
wren_64x8 <= wren_64x8_xhdl8;
rden_64x8 <= rden_64x8_xhdl9;
wraddress_64x8 <= wraddress_64x8_xhdl10;
rdaddress_64x8 <= rdaddress_64x8_xhdl11;
data_64x4 <= data_64x4_xhdl12;
wren_64x4x1 <= wren_64x4x1_xhdl13;
wraddress_64x4x1 <= wraddress_64x4x1_xhdl14;
rdaddress_64x4x1 <= rdaddress_64x4x1_xhdl15;
data_64x1 <= data_64x1_xhdl16;
-- port connections for Ram
--64x8
w_q_dp_64x8 <= q_dp_64x8 ;
data_64x8_xhdl7 <= w_data_64x8 ;
wren_64x8_xhdl8 <= w_wren_64x8 ;
rden_64x8_xhdl9 <= w_rden_64x8 ;
wraddress_64x8_xhdl10 <= w_wraddress_64x8 ;
rdaddress_64x8_xhdl11 <= w_rdaddress_64x8 ;
--64x4
w_q_dp_64x4 <= q_dp_64x4 ;
data_64x4_xhdl12 <= w_data_64x4 ;
wren_64x4x1_xhdl13 <= w_wren_64x4x1 ;
wraddress_64x4x1_xhdl14 <= w_wraddress_64x4x1 ;
rdaddress_64x4x1_xhdl15 <= w_rdaddress_64x4x1 ;
--64x1
w_q_dp_64x1 <= q_dp_64x1 ;
data_64x1_xhdl16 <= w_data_64x1 ;
-- Connecting can_registers module -- Mode register -- Command register -- Arbitration Lost Capture Register -- Error Code Capture Register -- Bus Timing 0 register -- Bus Timing 1 register -- Error Warning Limit register -- Rx Error Counter register -- Tx Error Counter register -- Clock Divider register -- This section is for BASIC and EXTENDED mode -- Acceptance code register -- Acceptance mask register -- End: This section is for BASIC and EXTENDED mode -- This section is for EXTENDED mode -- Acceptance code register -- Acceptance mask register -- End: This section is for EXTENDED mode -- Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data -- End: Tx data registers
i_can_registers : can_registers
PORT MAP (
clk => clk_i,
rst => rst,
cs => cs,
we => we,
addr => addr,
data_in => data_in,
data_out => data_out_regs,
irq_n => irq_on_xhdl5,
sample_point => sample_point,
transmitting => transmitting,
set_reset_mode => set_reset_mode,
node_bus_off => node_bus_off,
error_status => error_status,
rx_err_cnt => rx_err_cnt,
tx_err_cnt => tx_err_cnt,
transmit_status => transmit_status,
receive_status => receive_status,
tx_successful => tx_successful,
need_to_tx => need_to_tx,
overrun => overrun,
info_empty => info_empty,
set_bus_error_irq => set_bus_error_irq,
set_arbitration_lost_irq => set_arbitration_lost_irq,
arbitration_lost_capture => arbitration_lost_capture,
node_error_passive => node_error_passive,
node_error_active => node_error_active,
rx_message_counter => rx_message_counter,
reset_mode => reset_mode,
listen_only_mode => listen_only_mode,
acceptance_filter_mode => acceptance_filter_mode,
self_test_mode => self_test_mode,
clear_data_overrun => open,
release_buffer => release_buffer,
abort_tx => abort_tx,
tx_request => tx_request,
self_rx_request => self_rx_request,
single_shot_transmission => single_shot_transmission,
tx_state => tx_state,
tx_state_q => tx_state_q,
overload_request => overload_request,
overload_frame => overload_frame,
read_arbitration_lost_capture_reg => read_arbitration_lost_capture_reg,
read_error_code_capture_reg => read_error_code_capture_reg,
error_capture_code => error_capture_code,
baud_r_presc => baud_r_presc,
sync_jump_width => sync_jump_width,
time_segment1 => time_segment1,
time_segment2 => time_segment2,
triple_sampling => triple_sampling,
error_warning_limit => error_warning_limit,
we_rx_err_cnt => we_rx_err_cnt,
we_tx_err_cnt => we_tx_err_cnt,
extended_mode => extended_mode,
clkout => clkout_o_xhdl6,
acceptance_code_0 => acceptance_code_0,
acceptance_mask_0 => acceptance_mask_0,
acceptance_code_1 => acceptance_code_1,
acceptance_code_2 => acceptance_code_2,
acceptance_code_3 => acceptance_code_3,
acceptance_mask_1 => acceptance_mask_1,
acceptance_mask_2 => acceptance_mask_2,
acceptance_mask_3 => acceptance_mask_3,
tx_data_0 => tx_data_0,
tx_data_1 => tx_data_1,
tx_data_2 => tx_data_2,
tx_data_3 => tx_data_3,
tx_data_4 => tx_data_4,
tx_data_5 => tx_data_5,
tx_data_6 => tx_data_6,
tx_data_7 => tx_data_7,
tx_data_8 => tx_data_8,
tx_data_9 => tx_data_9,
tx_data_10 => tx_data_10,
tx_data_11 => tx_data_11,
tx_data_12 => tx_data_12);
-- Connecting can_btl module -- Bus Timing 0 register -- Bus Timing 1 register -- Output signals from this module -- output from can_bsp module
i_can_btl : can_btl
PORT MAP (
clk => clk_i,
rst => rst,
rx => rx_sync,
tx => tx_o_xhdl3,
baud_r_presc => baud_r_presc,
sync_jump_width => sync_jump_width,
time_segment1 => time_segment1,
time_segment2 => time_segment2,
triple_sampling => triple_sampling,
sample_point => sample_point,
sampled_bit => sampled_bit,
sampled_bit_q => sampled_bit_q,
tx_point => tx_point,
hard_sync => hard_sync,
rx_idle => rx_idle,
rx_inter => rx_inter,
transmitting => transmitting,
transmitter => transmitter,
go_rx_inter => go_rx_inter,
tx_next => tx_next,
go_overload_frame => go_overload_frame,
go_error_frame => go_error_frame,
go_tx => go_tx,
send_ack => send_ack,
node_error_passive => node_error_passive);
-- xhdl_148 <= rx_err_cnt_dummy & rx_err_cnt(7 DOWNTO 0);
rx_err_cnt_dummy <= xhdl_148(8);
rx_err_cnt(7 DOWNTO 0) <= xhdl_148(7 DOWNTO 0);
-- xhdl_150 <= tx_err_cnt_dummy & tx_err_cnt(7 DOWNTO 0);
tx_err_cnt_dummy <= xhdl_150(8);
tx_err_cnt(7 DOWNTO 0) <= xhdl_150(7 DOWNTO 0);
-- The MSB is not displayed. It is just used for easier calculation (no counter overflow).
-- This section is for BASIC and EXTENDED mode -- Acceptance code register -- Acceptance mask register -- End: This section is for BASIC and EXTENDED mode -- This section is for EXTENDED mode -- Acceptance code register -- Acceptance mask register -- End: This section is for EXTENDED mode -- Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data -- End: Tx data registers -- Tx signal -- port connections for Ram
--64x8
--64x4
--64x1
i_can_bsp : can_bsp
PORT MAP (
clk => clk_i,
rst => rst,
sample_point => sample_point,
sampled_bit => sampled_bit,
sampled_bit_q => sampled_bit_q,
tx_point => tx_point,
hard_sync => hard_sync,
addr => addr,
data_in => data_in,
data_out => data_out_fifo,
fifo_selected => data_out_fifo_selected,
reset_mode => reset_mode,
listen_only_mode => listen_only_mode,
acceptance_filter_mode => acceptance_filter_mode,
self_test_mode => self_test_mode,
release_buffer => release_buffer,
tx_request => tx_request,
abort_tx => abort_tx,
self_rx_request => self_rx_request,
single_shot_transmission => single_shot_transmission,
tx_state => tx_state,
tx_state_q => tx_state_q,
overload_request => overload_request,
overload_frame => overload_frame,
read_arbitration_lost_capture_reg => read_arbitration_lost_capture_reg,
read_error_code_capture_reg => read_error_code_capture_reg,
error_capture_code => error_capture_code,
error_warning_limit => error_warning_limit,
we_rx_err_cnt => we_rx_err_cnt,
we_tx_err_cnt => we_tx_err_cnt,
extended_mode => extended_mode,
rx_idle => rx_idle,
transmitting => transmitting,
transmitter => transmitter,
go_rx_inter => go_rx_inter,
not_first_bit_of_inter => not_first_bit_of_inter,
rx_inter => rx_inter,
set_reset_mode => set_reset_mode,
node_bus_off => node_bus_off,
error_status => error_status,
rx_err_cnt => xhdl_148,
tx_err_cnt => xhdl_150,
transmit_status => transmit_status,
receive_status => receive_status,
tx_successful => tx_successful,
need_to_tx => need_to_tx,
overrun => overrun,
info_empty => info_empty,
set_bus_error_irq => set_bus_error_irq,
set_arbitration_lost_irq => set_arbitration_lost_irq,
arbitration_lost_capture => arbitration_lost_capture,
node_error_passive => node_error_passive,
node_error_active => node_error_active,
rx_message_counter => rx_message_counter,
acceptance_code_0 => acceptance_code_0,
acceptance_mask_0 => acceptance_mask_0,
acceptance_code_1 => acceptance_code_1,
acceptance_code_2 => acceptance_code_2,
acceptance_code_3 => acceptance_code_3,
acceptance_mask_1 => acceptance_mask_1,
acceptance_mask_2 => acceptance_mask_2,
acceptance_mask_3 => acceptance_mask_3,
tx_data_0 => tx_data_0,
tx_data_1 => tx_data_1,
tx_data_2 => tx_data_2,
tx_data_3 => tx_data_3,
tx_data_4 => tx_data_4,
tx_data_5 => tx_data_5,
tx_data_6 => tx_data_6,
tx_data_7 => tx_data_7,
tx_data_8 => tx_data_8,
tx_data_9 => tx_data_9,
tx_data_10 => tx_data_10,
tx_data_11 => tx_data_11,
tx_data_12 => tx_data_12,
tx => tx_o_xhdl3,
tx_next => tx_next,
bus_off_on => bus_off_on_xhdl4,
go_overload_frame => go_overload_frame,
go_error_frame => go_error_frame,
go_tx => go_tx,
send_ack => send_ack,
q_dp_64x8 => w_q_dp_64x8,
data_64x8 => w_data_64x8,
wren_64x8 => w_wren_64x8,
rden_64x8 => w_rden_64x8,
wraddress_64x8 => w_wraddress_64x8,
rdaddress_64x8 => w_rdaddress_64x8,
q_dp_64x4 => w_q_dp_64x4,
data_64x4 => w_data_64x4,
wren_64x4x1 => w_wren_64x4x1,
wraddress_64x4x1 => w_wraddress_64x4x1,
rdaddress_64x4x1 => w_rdaddress_64x4x1,
q_dp_64x1 => w_q_dp_64x1,
data_64x1 => w_data_64x1);
-- Multiplexing wb_dat_o from registers and rx fifo
PROCESS (extended_mode, addr, reset_mode)
VARIABLE data_out_fifo_selected_xhdl203 : std_logic;
BEGIN
IF ((((extended_mode AND (NOT reset_mode)) AND CONV_STD_LOGIC((addr >= "00010000") AND (addr<="00011100"))) OR ((NOT extended_mode) AND CONV_STD_LOGIC((addr >= "00010100") AND (addr<="00011101")))) = '1') THEN
data_out_fifo_selected_xhdl203 := '1';
ELSE
data_out_fifo_selected_xhdl203 := '0';
END IF;
data_out_fifo_selected <= data_out_fifo_selected_xhdl203;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((cs AND (NOT we)) = '1') THEN
IF (data_out_fifo_selected = '1') THEN
data_out <= data_out_fifo ;
ELSE
data_out <= data_out_regs ;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i, rst)
BEGIN
IF (rst = '1') THEN
rx_sync_tmp <= '1';
rx_sync <= '1';
ELSIF (clk_i'EVENT AND clk_i = '1') THEN
rx_sync_tmp <= rx_i ;
rx_sync <= rx_sync_tmp ;
END IF;
END PROCESS;
-- cs_can_i <= '1' ;
-- Combining wb_cyc_i and wb_stb_i signals to cs signal. Than synchronizing to clk_i clock domain.
-- PROCESS (clk_i, rst)
-- BEGIN
-- IF (rst = '1') THEN
-- cs_sync1 <= '0';
-- cs_sync2 <= '0';
-- cs_sync3 <= '0';
-- cs_sync_rst1 <= '0';
-- cs_sync_rst2 <= '0';
-- ELSIF (clk_i'EVENT AND clk_i = '1') THEN
-- cs_sync1 <= ((wb_cyc_i AND wb_stb_i) AND (NOT cs_sync_rst2)) AND cs_can_i ;
-- cs_sync2 <= cs_sync1 AND (NOT cs_sync_rst2) ;
-- cs_sync3 <= cs_sync2 AND (NOT cs_sync_rst2) ;
-- cs_sync_rst1 <= cs_ack3 ;
-- cs_sync_rst2 <= cs_sync_rst1 ;
-- END IF;
-- END PROCESS;
-- cs <= cs_sync2 AND (NOT cs_sync3) ;
--
-- PROCESS (wb_clk_i)
-- BEGIN
-- IF (wb_clk_i'EVENT AND wb_clk_i = '1') THEN
-- cs_ack1 <= cs_sync3 ;
-- cs_ack2 <= cs_ack1 ;
-- cs_ack3 <= cs_ack2 ;
-- END IF;
-- END PROCESS;
-- Generating acknowledge signal
-- PROCESS (wb_clk_i)
-- BEGIN
-- IF (wb_clk_i'EVENT AND wb_clk_i = '1') THEN
-- wb_ack_o_xhdl2 <= cs_ack2 AND (NOT cs_ack3) ;
-- END IF;
-- END PROCESS;
-- rst <= wb_rst_i ;
-- we <= wb_we_i ;
-- addr <= wb_adr_i ;
-- data_in <= wb_dat_i ;
-- wb_dat_o_xhdl1 <= data_out ;
END ARCHITECTURE RTL;
| mit | c78f68fba808e63903a6efd2fdc8c545 | 0.434566 | 4.293309 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gleichmann/sim/jtagtst.vhd | 2 | 9,363 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: sim
-- File: sim.vhd
-- Author: Edvin Catovic - Gaisler Research
-- Description: JTAG debug link communication test
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
library grlib;
use grlib.stdlib.all;
use grlib.stdio.all;
use grlib.amba.all;
package jtagtst is
procedure clkj(tmsi, tdii : in std_ulogic; tdoo : out std_ulogic;
signal tck, tms, tdi : out std_ulogic;
signal tdo : in std_ulogic;
cp : in integer);
procedure shift(dr : in boolean; len : in integer;
din : in std_logic_vector; dout : out std_logic_vector;
signal tck, tms, tdi : out std_ulogic;
signal tdo : in std_ulogic;
cp : in integer);
procedure jtagcom(signal tdo : in std_ulogic;
signal tck, tms, tdi : out std_ulogic;
cp, start, addr : in integer;
-- cp - TCK clock period in ns
-- start - time in us when JTAG test
-- is started
-- addr - read/write operation destination address
haltcpu : in boolean);
end;
package body jtagtst is
procedure clkj(tmsi, tdii : in std_ulogic; tdoo : out std_ulogic;
signal tck, tms, tdi : out std_ulogic;
signal tdo : in std_ulogic;
cp : in integer) is
begin
tdi <= tdii;
tck <= '0'; tms <= tmsi;
wait for 2 * cp * 1 ns;
tck <= '1'; tdoo := tdo;
wait for 2 * cp * 1 ns;
end;
procedure shift(dr : in boolean; len : in integer;
din : in std_logic_vector; dout : out std_logic_vector;
signal tck, tms, tdi : out std_ulogic;
signal tdo : in std_ulogic;
cp : in integer) is
variable dc : std_ulogic;
begin
clkj('0', '-', dc, tck, tms, tdi, tdo, cp);
clkj('1', '-', dc, tck, tms, tdi, tdo, cp);
if (not dr) then clkj('1', '-', dc, tck, tms, tdi, tdo, cp); end if;
clkj('0', '-', dc, tck, tms, tdi, tdo, cp); -- capture
clkj('0', '-', dc, tck, tms, tdi, tdo, cp); -- shift (state)
for i in 0 to len-2 loop
clkj('0', din(i), dout(i), tck, tms, tdi, tdo, cp);
end loop;
clkj('1', din(len-1), dout(len-1), tck, tms, tdi, tdo, cp); -- end shift, goto exit1
clkj('1', '-', dc, tck, tms, tdi, tdo, cp); -- update ir/dr
clkj('0', '-', dc, tck, tms, tdi, tdo, cp); -- run_test/idle
end;
procedure jtagcom(signal tdo : in std_ulogic;
signal tck, tms, tdi : out std_ulogic;
cp, start, addr : in integer;
haltcpu : in boolean) is
variable inst: std_logic_vector(5 downto 0);
variable dc : std_ulogic;
variable dr : std_logic_vector(32 downto 0);
variable dr2 : std_logic_vector(34 downto 0);
variable tmp : std_logic_vector(32 downto 0);
variable tmp2 : std_logic_vector(34 downto 0);
variable hsize : std_logic_vector(1 downto 0);
begin
tck <= '0'; tms <= '0'; tdi <= '0';
wait for start * 1 us;
print("AHB JTAG TEST");
for i in 1 to 5 loop -- reset
clkj('1', '0', dc, tck, tms, tdi, tdo, cp);
end loop;
clkj('0', '-', dc, tck, tms, tdi, tdo, cp);
hsize := "10";
--read IDCODE
wait for 10 * cp * 1 ns;
shift(true, 32, conv_std_logic_vector(0, 32), dr, tck, tms, tdi, tdo, cp);
print("JTAG TAP ID:" & tost(dr(31 downto 0)));
wait for 10 * cp * 1 ns;
shift(false, 6, conv_std_logic_vector(63, 6), dr, tck, tms, tdi, tdo, cp); -- BYPASS
--shift data through BYPASS reg
shift(true, 32, conv_std_logic_vector(16#AAAA#, 16) & conv_std_logic_vector(16#AAAA#, 16), dr,
tck, tms, tdi, tdo, cp);
-- put CPUs in debug mode
if haltcpu then
wait for 10 * cp * 1 ns;
shift(false, 6, conv_std_logic_vector(2, 6), dr, tck, tms, tdi, tdo, cp); -- inst = addrreg
wait for 5 * cp * 1 ns;
tmp2 := '1' & hsize & X"90000000"; --conv_std_logic_vector_signed(16#90000000#, 32);
shift(true, 35, tmp2, dr2, tck, tms, tdi, tdo, cp); -- write addreg
wait for 5 * cp * 1 ns;
shift(false, 6, conv_std_logic_vector(3, 6), dr, tck, tms, tdi, tdo, cp); -- inst = datareg
wait for 5 * cp * 1 ns;
tmp := '0' & conv_std_logic_vector(4, 32);
shift(true, 33, tmp, dr, tck, tms, tdi, tdo, cp); -- write data
wait for 10 * cp * 1 ns;
shift(false, 6, conv_std_logic_vector(2, 6), dr, tck, tms, tdi, tdo, cp); -- inst = addrreg
wait for 5 * cp * 1 ns;
tmp2 := '1' & hsize & X"90000020"; --conv_std_logic_vector_signed(16#90000020#, 32);
shift(true, 35, tmp2, dr2, tck, tms, tdi, tdo, cp); -- write addreg
wait for 5 * cp * 1 ns;
shift(false, 6, conv_std_logic_vector(3, 6), dr, tck, tms, tdi, tdo, cp); -- inst = datareg
wait for 5 * cp * 1 ns;
tmp := '0' & conv_std_logic_vector(16#ffff#, 32);
shift(true, 33, tmp, dr, tck, tms, tdi, tdo, cp); -- write data
print("JTAG: Putting CPU in debug mode");
end if;
wait for 10 * cp * 1 ns;
shift(false, 6, conv_std_logic_vector(2, 6), dr, tck, tms, tdi, tdo, cp); -- inst = addrreg
wait for 5 * cp * 1 ns;
tmp2 := '1' & hsize & conv_std_logic_vector(addr, 32);
shift(true, 35, tmp2, dr2, tck, tms, tdi, tdo, cp); -- write addreg
wait for 5 * cp * 1 ns;
shift(false, 6, conv_std_logic_vector(3, 6), dr, tck, tms, tdi, tdo, cp); -- inst = datareg
wait for 5 * cp * 1 ns;
tmp := '1' & conv_std_logic_vector(16#10#, 32);
shift(true, 33, tmp, dr, tck, tms, tdi, tdo, cp); -- write data
print("JTAG WRITE " & tost(conv_std_logic_vector(addr, 32)) & ":" &
tost(conv_std_logic_vector(16#10#, 32)));
wait for 5 * cp * 1 ns;
tmp := '1' & conv_std_logic_vector(16#11#,32);
shift(true, 33, tmp, dr, tck, tms, tdi, tdo, cp); -- write data
print("JTAG WRITE " & tost(conv_std_logic_vector(addr+4, 32)) & ":" &
tost(conv_std_logic_vector(16#11#, 32)));
wait for 5 * cp * 1 ns;
tmp := '0' & conv_std_logic_vector(16#12#,32);
print("JTAG WRITE " & tost(conv_std_logic_vector(addr+8, 32)) & ":" &
tost(conv_std_logic_vector(16#12#, 32)));
shift(true, 33, tmp, dr, tck, tms, tdi, tdo, cp); -- write data
wait for 10 * cp * 1 ns;
shift(false, 6, conv_std_logic_vector(2, 6), dr, tck, tms, tdi, tdo, cp); -- inst = addrreg
wait for 5 * cp * 1 ns;
tmp2 := '0' & hsize & conv_std_logic_vector(addr, 32);
shift(true, 35, tmp2, dr2, tck, tms, tdi, tdo, cp); -- write addreg
wait for 5 * cp * 1 ns;
shift(false, 6, conv_std_logic_vector(3, 6), dr, tck, tms, tdi, tdo, cp); -- inst = datareg
wait for 5 * cp * 1 ns;
tmp := (others => '0'); tmp(32) := '1';
shift(true, 33, tmp, dr, tck, tms, tdi, tdo, cp); -- read data
print("JTAG READ " & tost(conv_std_logic_vector(addr, 32)) & ":" & tost(dr(31 downto 0)));
assert dr(31 downto 0) = X"00000010"
report "JTAG read failed" severity failure;
wait for 5 * cp * 1 ns;
shift(true, 33, tmp, dr, tck, tms, tdi, tdo, cp); -- read data
print("JTAG READ " & tost(conv_std_logic_vector(addr+4, 32)) & ":" & tost(dr(31 downto 0)));
assert dr(31 downto 0) = X"00000011"
report "JTAG read failed" severity failure;
wait for 5 * cp * 1 ns;
tmp(32) := '0';
shift(true, 33, tmp, dr, tck, tms, tdi, tdo, cp); -- read data
print("JTAG READ " & tost(conv_std_logic_vector(addr+8, 32)) & ":" & tost(dr(31 downto 0)));
assert dr(31 downto 0) = X"00000012"
report "JTAG read failed" severity failure;
-- JTAG test passed
assert false report "JTAG test passed, halting with failure." severity note;
end procedure;
end;
-- pragma translate_on
| mit | fa526673a7aaf7e23829601194966882 | 0.528143 | 3.444812 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/techmap/maps/iopad.vhd | 2 | 5,277 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: iopad
-- File: iopad.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: io pad with technology wrapper
------------------------------------------------------------------------------
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allpads.all;
entity iopad is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12;
oepol : integer := 0);
port (pad : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);
end;
architecture rtl of iopad is
signal oen : std_ulogic;
begin
oen <= not en when oepol /= padoen_polarity(tech) else en;
gen0 : if has_pads(tech) = 0 generate
pad <= i after 2 ns when oen = '0'
-- pragma translate_off
else 'X' after 2 ns when is_x(oen)
-- pragma translate_on
else 'Z' after 2 ns;
o <= to_X01(pad) after 1 ns;
end generate;
xcv : if (tech = virtex) or (tech = virtex2) or (tech = spartan3) or
(tech = virtex4) or (tech = spartan3e) or (tech = virtex5)
generate
x0 : virtex_iopad generic map (level, slew, voltage, strength)
port map (pad, i, oen, o);
end generate;
axc : if (tech = axcel) or (tech = proasic) or (tech = apa3) generate
x0 : axcel_iopad generic map (level, slew, voltage, strength)
port map (pad, i, oen, o);
end generate;
atc : if (tech = atc18s) generate
x0 : atc18_iopad generic map (level, slew, voltage, strength)
port map (pad, i, oen, o);
end generate;
atcrh : if (tech = atc18rha) generate
x0 : atc18rha_iopad generic map (level, slew, voltage, strength)
port map (pad, i, oen, o);
end generate;
um : if (tech = umc) generate
x0 : umc_iopad generic map (level, slew, voltage, strength)
port map (pad, i, oen, o);
end generate;
rhu : if (tech = rhumc) generate
x0 : rhumc_iopad generic map (level, slew, voltage, strength)
port map (pad, i, oen, o);
end generate;
ihp : if (tech = ihp25) generate
x0 : ihp25_iopad generic map (level, slew, voltage, strength)
port map (pad, i, oen, o);
end generate;
ihprh : if (tech = ihp25rh) generate
x0 : ihp25rh_iopad generic map (level, slew, voltage, strength)
port map (pad, i, oen, o);
end generate;
rh18t : if (tech = rhlib18t) generate
x0 : rh_lib18t_iopad generic map (strength)
port map (pad, i, oen, o);
end generate;
ut025 : if (tech = ut25) generate
x0 : ut025crh_iopad generic map (level, slew, voltage, strength)
port map (pad, i, oen, o);
end generate;
pere : if (tech = peregrine) generate
x0 : peregrine_iopad generic map (level, slew, voltage, strength)
port map(pad, i, oen, o);
end generate;
nex : if (tech = easic90) generate
x0 : nextreme_iopad generic map (level, slew, voltage, strength)
port map (pad, i, oen, o);
end generate;
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity iopadv is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (
pad : inout std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_ulogic;
o : out std_logic_vector(width-1 downto 0));
end;
architecture rtl of iopadv is
begin
v : for j in width-1 downto 0 generate
x0 : iopad generic map (tech, level, slew, voltage, strength, oepol)
port map (pad(j), i(j), en, o(j));
end generate;
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity iopadvv is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (
pad : inout std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_logic_vector(width-1 downto 0);
o : out std_logic_vector(width-1 downto 0));
end;
architecture rtl of iopadvv is
begin
v : for j in width-1 downto 0 generate
x0 : iopad generic map (tech, level, slew, voltage, strength, oepol)
port map (pad(j), i(j), en(j), o(j));
end generate;
end;
| mit | efe34c9d21f509c791d7ec95e42ebbbc | 0.629145 | 3.455796 | false | false | false | false |
cafe-alpha/wascafe | v13/r07c_de10_20201014_abus4/wasca/synthesis/wasca_reset_controller_0.vhd | 6 | 9,060 | -- wasca_reset_controller_0.vhd
-- Generated using ACDS version 15.0 145
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity wasca_reset_controller_0 is
generic (
NUM_RESET_INPUTS : integer := 2;
OUTPUT_RESET_SYNC_EDGES : string := "both";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 0;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := '0'; -- reset_in0.reset
reset_in1 : in std_logic := '0'; -- reset_in1.reset
clk : in std_logic := '0'; -- clk.clk
reset_out : out std_logic; -- reset_out.reset
reset_in10 : in std_logic := '0';
reset_in11 : in std_logic := '0';
reset_in12 : in std_logic := '0';
reset_in13 : in std_logic := '0';
reset_in14 : in std_logic := '0';
reset_in15 : in std_logic := '0';
reset_in2 : in std_logic := '0';
reset_in3 : in std_logic := '0';
reset_in4 : in std_logic := '0';
reset_in5 : in std_logic := '0';
reset_in6 : in std_logic := '0';
reset_in7 : in std_logic := '0';
reset_in8 : in std_logic := '0';
reset_in9 : in std_logic := '0';
reset_req : out std_logic;
reset_req_in0 : in std_logic := '0';
reset_req_in1 : in std_logic := '0';
reset_req_in10 : in std_logic := '0';
reset_req_in11 : in std_logic := '0';
reset_req_in12 : in std_logic := '0';
reset_req_in13 : in std_logic := '0';
reset_req_in14 : in std_logic := '0';
reset_req_in15 : in std_logic := '0';
reset_req_in2 : in std_logic := '0';
reset_req_in3 : in std_logic := '0';
reset_req_in4 : in std_logic := '0';
reset_req_in5 : in std_logic := '0';
reset_req_in6 : in std_logic := '0';
reset_req_in7 : in std_logic := '0';
reset_req_in8 : in std_logic := '0';
reset_req_in9 : in std_logic := '0'
);
end entity wasca_reset_controller_0;
architecture rtl of wasca_reset_controller_0 is
component altera_reset_controller is
generic (
NUM_RESET_INPUTS : integer := 6;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 0;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := 'X'; -- reset
reset_in1 : in std_logic := 'X'; -- reset
clk : in std_logic := 'X'; -- clk
reset_out : out std_logic; -- reset
reset_req : out std_logic; -- reset_req
reset_req_in0 : in std_logic := 'X'; -- reset_req
reset_req_in1 : in std_logic := 'X'; -- reset_req
reset_in2 : in std_logic := 'X'; -- reset
reset_req_in2 : in std_logic := 'X'; -- reset_req
reset_in3 : in std_logic := 'X'; -- reset
reset_req_in3 : in std_logic := 'X'; -- reset_req
reset_in4 : in std_logic := 'X'; -- reset
reset_req_in4 : in std_logic := 'X'; -- reset_req
reset_in5 : in std_logic := 'X'; -- reset
reset_req_in5 : in std_logic := 'X'; -- reset_req
reset_in6 : in std_logic := 'X'; -- reset
reset_req_in6 : in std_logic := 'X'; -- reset_req
reset_in7 : in std_logic := 'X'; -- reset
reset_req_in7 : in std_logic := 'X'; -- reset_req
reset_in8 : in std_logic := 'X'; -- reset
reset_req_in8 : in std_logic := 'X'; -- reset_req
reset_in9 : in std_logic := 'X'; -- reset
reset_req_in9 : in std_logic := 'X'; -- reset_req
reset_in10 : in std_logic := 'X'; -- reset
reset_req_in10 : in std_logic := 'X'; -- reset_req
reset_in11 : in std_logic := 'X'; -- reset
reset_req_in11 : in std_logic := 'X'; -- reset_req
reset_in12 : in std_logic := 'X'; -- reset
reset_req_in12 : in std_logic := 'X'; -- reset_req
reset_in13 : in std_logic := 'X'; -- reset
reset_req_in13 : in std_logic := 'X'; -- reset_req
reset_in14 : in std_logic := 'X'; -- reset
reset_req_in14 : in std_logic := 'X'; -- reset_req
reset_in15 : in std_logic := 'X'; -- reset
reset_req_in15 : in std_logic := 'X' -- reset_req
);
end component altera_reset_controller;
begin
reset_controller_0 : component altera_reset_controller
generic map (
NUM_RESET_INPUTS => NUM_RESET_INPUTS,
OUTPUT_RESET_SYNC_EDGES => OUTPUT_RESET_SYNC_EDGES,
SYNC_DEPTH => SYNC_DEPTH,
RESET_REQUEST_PRESENT => RESET_REQUEST_PRESENT,
RESET_REQ_WAIT_TIME => RESET_REQ_WAIT_TIME,
MIN_RST_ASSERTION_TIME => MIN_RST_ASSERTION_TIME,
RESET_REQ_EARLY_DSRT_TIME => RESET_REQ_EARLY_DSRT_TIME,
USE_RESET_REQUEST_IN0 => USE_RESET_REQUEST_IN0,
USE_RESET_REQUEST_IN1 => USE_RESET_REQUEST_IN1,
USE_RESET_REQUEST_IN2 => USE_RESET_REQUEST_IN2,
USE_RESET_REQUEST_IN3 => USE_RESET_REQUEST_IN3,
USE_RESET_REQUEST_IN4 => USE_RESET_REQUEST_IN4,
USE_RESET_REQUEST_IN5 => USE_RESET_REQUEST_IN5,
USE_RESET_REQUEST_IN6 => USE_RESET_REQUEST_IN6,
USE_RESET_REQUEST_IN7 => USE_RESET_REQUEST_IN7,
USE_RESET_REQUEST_IN8 => USE_RESET_REQUEST_IN8,
USE_RESET_REQUEST_IN9 => USE_RESET_REQUEST_IN9,
USE_RESET_REQUEST_IN10 => USE_RESET_REQUEST_IN10,
USE_RESET_REQUEST_IN11 => USE_RESET_REQUEST_IN11,
USE_RESET_REQUEST_IN12 => USE_RESET_REQUEST_IN12,
USE_RESET_REQUEST_IN13 => USE_RESET_REQUEST_IN13,
USE_RESET_REQUEST_IN14 => USE_RESET_REQUEST_IN14,
USE_RESET_REQUEST_IN15 => USE_RESET_REQUEST_IN15,
ADAPT_RESET_REQUEST => ADAPT_RESET_REQUEST
)
port map (
reset_in0 => reset_in0, -- reset_in0.reset
reset_in1 => reset_in1, -- reset_in1.reset
clk => clk, -- clk.clk
reset_out => reset_out, -- reset_out.reset
reset_req => open, -- (terminated)
reset_req_in0 => '0', -- (terminated)
reset_req_in1 => '0', -- (terminated)
reset_in2 => '0', -- (terminated)
reset_req_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_req_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_req_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_req_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_req_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_req_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_req_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_req_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_req_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_req_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_req_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_req_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_req_in14 => '0', -- (terminated)
reset_in15 => '0', -- (terminated)
reset_req_in15 => '0' -- (terminated)
);
end architecture rtl; -- of wasca_reset_controller_0
| gpl-2.0 | 829d47e7dfddce3ea3ccadb7c9a716a7 | 0.548675 | 2.722356 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/leon3/mmu_icache.vhd | 2 | 23,798 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: icache
-- File: icache.vhd
-- Author: Jiri Gaisler, Konrad Eisele - Gaisler Research
-- Description: This unit implements the instruction cache controller.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.libiu.all;
use gaisler.libcache.all;
use gaisler.mmuconfig.all;
use gaisler.mmuiface.all;
entity mmu_icache is
generic (
irepl : integer range 0 to 2 := 0;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0
);
port (
rst : in std_logic;
clk : in std_logic;
ici : in icache_in_type;
ico : out icache_out_type;
dci : in dcache_in_type;
dco : in dcache_out_type;
mcii : out memory_ic_in_type;
mcio : in memory_ic_out_type;
icrami : out icram_in_type;
icramo : in icram_out_type;
fpuholdn : in std_logic;
mmudci : in mmudc_in_type;
mmuici : out mmuic_in_type;
mmuico : in mmuic_out_type
);
end;
architecture rtl of mmu_icache is
constant ILINE_BITS : integer := log2(ilinesize);
constant IOFFSET_BITS : integer := 8 +log2(isetsize) - ILINE_BITS;
constant TAG_LOW : integer := IOFFSET_BITS + ILINE_BITS + 2;
constant OFFSET_HIGH: integer := TAG_LOW - 1;
constant OFFSET_LOW : integer := ILINE_BITS + 2;
constant LINE_HIGH : integer := OFFSET_LOW - 1;
constant LINE_LOW : integer := 2;
constant LRR_BIT : integer := TAG_HIGH + 1;
constant PCLOW : integer := 2;
constant ILINE_SIZE : integer := ilinesize;
constant ICLOCK_BIT : integer := isetlock;
constant ICREPLACE : integer range 0 to 2 := irepl;
constant lline : std_logic_vector((ILINE_BITS -1) downto 0) := (others=>'1');
constant SETBITS : integer := log2x(ISETS);
constant ILRUBITS : integer := lru_table(ISETS);
subtype lru_type is std_logic_vector(ILRUBITS-1 downto 0);
type lru_array is array (0 to 2**IOFFSET_BITS-1) of lru_type; -- lru registers
type rdatatype is (itag, idata, memory); -- sources during cache read
type lru_table_vector_type is array(0 to 3) of std_logic_vector(4 downto 0);
type lru_table_type is array (0 to 2**IOFFSET_BITS-1) of lru_table_vector_type;
subtype lock_type is std_logic_vector(0 to ISETS-1);
type par_type is array (0 to ISETS-1) of std_logic_vector(1 downto 0);
function lru_set (lru : lru_type; lock : lock_type) return std_logic_vector is
variable xlru : std_logic_vector(4 downto 0);
variable set : std_logic_vector(SETBITS-1 downto 0);
variable xset : std_logic_vector(1 downto 0);
variable unlocked : integer range 0 to ISETS-1;
begin
set := (others => '0'); xlru := (others => '0'); xset := (others => '0');
xlru(ILRUBITS-1 downto 0) := lru;
if isetlock = 1 then
unlocked := ISETS-1;
for i in ISETS-1 downto 0 loop
if lock(i) = '0' then unlocked := i; end if;
end loop;
end if;
case ISETS is
when 2 =>
if isetlock = 1 then
if lock(0) = '1' then xset(0) := '1'; else xset(0) := xlru(0); end if;
else xset(0) := xlru(0); end if;
when 3 =>
if isetlock = 1 then
xset := conv_std_logic_vector(lru3_repl_table(conv_integer(xlru)) (unlocked), 2);
else
xset := conv_std_logic_vector(lru3_repl_table(conv_integer(xlru)) (0), 2);
end if;
when 4 =>
if isetlock = 1 then
xset := conv_std_logic_vector(lru4_repl_table(conv_integer(xlru)) (unlocked), 2);
else
xset := conv_std_logic_vector(lru4_repl_table(conv_integer(xlru)) (0), 2);
end if;
when others =>
end case;
set := xset(SETBITS-1 downto 0);
return(set);
end;
function lru_calc (lru : lru_type; set : integer) return lru_type is
variable new_lru : lru_type;
variable xnew_lru: std_logic_vector(4 downto 0);
variable xlru : std_logic_vector(4 downto 0);
begin
new_lru := (others => '0'); xnew_lru := (others => '0');
xlru := (others => '0'); xlru(ILRUBITS-1 downto 0) := lru;
case ISETS is
when 2 =>
if set = 0 then xnew_lru(0) := '1'; else xnew_lru(0) := '0'; end if;
when 3 =>
xnew_lru(2 downto 0) := lru_3set_table(conv_integer(lru))(set);
when 4 =>
xnew_lru(4 downto 0) := lru_4set_table(conv_integer(lru))(set);
when others =>
end case;
new_lru := xnew_lru(ILRUBITS-1 downto 0);
return(new_lru);
end;
type istatetype is (idle, trans, streaming, stop);
type icache_control_type is record -- all registers
req, burst, holdn : std_logic;
overrun : std_logic; --
underrun : std_logic; --
istate : istatetype; -- FSM
waddress : std_logic_vector(31 downto PCLOW); -- write address buffer
vaddress : std_logic_vector(31 downto PCLOW); -- virtual address buffer
valid : std_logic_vector(ILINE_SIZE-1 downto 0); -- valid bits
hit : std_logic;
su : std_logic;
flush : std_logic; -- flush in progress
flush2 : std_logic; -- flush in progress
flush3 : std_logic; -- flush in progress
faddr : std_logic_vector(IOFFSET_BITS - 1 downto 0); -- flush address
diagrdy : std_logic;
rndcnt : std_logic_vector(log2x(ISETS)-1 downto 0); -- replace counter
lrr : std_logic;
setrepl : std_logic_vector(log2x(ISETS)-1 downto 0); -- set to replace
diagset : std_logic_vector(log2x(ISETS)-1 downto 0);
lock : std_logic;
pflush : std_logic;
pflushr : std_logic;
pflushaddr : std_logic_vector(VA_I_U downto VA_I_D);
pflushtyp : std_logic;
cache : std_logic;
trans_op : std_logic;
end record;
type lru_reg_type is record
write : std_logic;
waddr : std_logic_vector(IOFFSET_BITS-1 downto 0);
set : std_logic_vector(SETBITS-1 downto 0); --integer range 0 to ISETS-1;
lru : lru_array;
end record;
signal r, c : icache_control_type; -- r is registers, c is combinational
signal rl, cl : lru_reg_type; -- rl is registers, cl is combinational
constant icfg : std_logic_vector(31 downto 0) :=
cache_cfg(irepl, isets, ilinesize, isetsize, isetlock, 0, 0, 1, 0, 1);
begin
ictrl : process(rst, r, rl, mcio, ici, dci, dco, icramo, fpuholdn, mmuico, mmudci)
variable rdatasel : rdatatype;
variable twrite, diagen, dwrite : std_logic;
variable taddr : std_logic_vector(TAG_HIGH downto LINE_LOW); -- tag address
variable wtag : std_logic_vector(TAG_HIGH downto TAG_LOW); -- write tag value
variable ddatain : std_logic_vector(31 downto 0);
variable rdata : cdatatype;
variable diagdata : std_logic_vector(31 downto 0);
variable vmaskraw, vmask : std_logic_vector((ILINE_SIZE -1) downto 0);
variable xaddr_inc : std_logic_vector((ILINE_BITS -1) downto 0);
variable lastline, nlastline, nnlastline : std_logic;
variable enable : std_logic;
variable error : std_logic;
variable whit, hit, valid : std_logic;
variable cacheon : std_logic;
variable v : icache_control_type;
variable branch : std_logic;
variable eholdn : std_logic;
variable mds, write : std_logic;
variable tparerr, dparerr : std_logic_vector(0 to ISETS-1);
variable set : integer range 0 to MAXSETS-1;
variable setrepl : std_logic_vector(log2x(ISETS)-1 downto 0); -- set to replace
variable ctwrite, cdwrite, validv : std_logic_vector(0 to MAXSETS-1);
variable wlrr : std_logic;
variable vl : lru_reg_type;
variable vdiagset, rdiagset : integer range 0 to ISETS-1;
variable lock : std_logic_vector(0 to ISETS-1);
variable wlock, sidle : std_logic;
variable tag : cdatatype;
variable pftag : std_logic_vector(31 downto 2);
variable mmuici_trans_op : std_logic;
variable mmuici_su : std_logic;
begin
-- init local variables
v := r; vl := rl; vl.write := '0'; vl.set := r.setrepl;
vl.waddr := r.waddress(OFFSET_HIGH downto OFFSET_LOW);
mds := '1'; dwrite := '0'; twrite := '0'; diagen := '0'; error := '0';
write := mcio.ready; v.diagrdy := '0'; v.holdn := '1';
v.flush3 := r.flush2; sidle := '0';
cacheon := dco.icdiag.cctrl.ics(0) and not r.flush;
enable := '1'; branch := '0';
eholdn := dco.hold and fpuholdn;
rdatasel := idata; -- read data from cache as default
ddatain := mcio.data; -- load full word from memory
--if M_EN and (mmudci.mmctrl1.e = '1') then wtag := r.vaddress(TAG_HIGH downto TAG_LOW);
--else wtag := r.waddress(TAG_HIGH downto TAG_LOW); end if;
wtag := r.vaddress(TAG_HIGH downto TAG_LOW);
wlrr := r.lrr; wlock := r.lock;
tparerr := (others => '0'); dparerr := (others => '0');
set := 0; ctwrite := (others => '0'); cdwrite := (others => '0');
vdiagset := 0; rdiagset := 0; lock := (others => '0');
pftag := (others => '0');
v.trans_op := r.trans_op and (not mmuico.grant);
mmuici_trans_op := r.trans_op;
mmuici_su := ici.su;
-- random replacement counter
if ISETS > 1 then
if conv_integer(r.rndcnt) = (ISETS - 1) then v.rndcnt := (others => '0');
else v.rndcnt := r.rndcnt + 1; end if;
end if;
-- generate lock bits
if ICLOCK_BIT = 1 then
for i in 0 to ISETS-1 loop lock(i) := icramo.tag(i)(CTAG_LOCKPOS); end loop;
end if;
-- generate cache hit and valid bits
hit := '0';
for i in ISETS-1 downto 0 loop
if (icramo.tag(i)(TAG_HIGH downto TAG_LOW) = ici.fpc(TAG_HIGH downto TAG_LOW))
and ((icramo.ctx(i) = mmudci.mmctrl1.ctx) or (mmudci.mmctrl1.e = '0'))
then hit := not r.flush; set := i; end if;
validv(i) := genmux(ici.fpc(LINE_HIGH downto LINE_LOW),
icramo.tag(i)(ilinesize -1 downto 0));
end loop;
if ici.fpc(LINE_HIGH downto LINE_LOW) = lline then lastline := '1';
else lastline := '0'; end if;
if r.waddress(LINE_HIGH downto LINE_LOW) = lline((ILINE_BITS -1) downto 0) then
nlastline := '1';
else nlastline := '0'; end if;
if r.waddress(LINE_HIGH downto LINE_LOW+1) = lline((ILINE_BITS -1) downto 1) then
nnlastline := '1';
else nnlastline := '0'; end if;
valid := validv(set);
xaddr_inc := r.waddress(LINE_HIGH downto LINE_LOW) + 1;
if mcio.ready = '1' then
v.waddress(LINE_HIGH downto LINE_LOW) := xaddr_inc;
end if;
xaddr_inc := r.vaddress(LINE_HIGH downto LINE_LOW) + 1;
if mcio.ready = '1' then
v.vaddress(LINE_HIGH downto LINE_LOW) := xaddr_inc;
end if;
taddr := ici.rpc(TAG_HIGH downto LINE_LOW);
-- main Icache state machine
case r.istate is
when idle => -- main state and cache hit
v.valid := icramo.tag(set)(ilinesize-1 downto 0);
v.hit := hit; v.su := ici.su; sidle := '1';
if eholdn = '0' then
taddr := ici.fpc(TAG_HIGH downto LINE_LOW);
else taddr := ici.rpc(TAG_HIGH downto LINE_LOW); end if;
v.burst := dco.icdiag.cctrl.burst and not lastline;
if (eholdn and not ici.inull ) = '1' then
if not (cacheon and hit and valid) = '1' then
v.istate := streaming;
v.holdn := '0'; v.overrun := '1';
if ((mmudci.mmctrl1.e) = '1') then
v.istate := trans;
mmuici_trans_op := '1';
v.trans_op := not mmuico.grant;
v.cache := '0';
--v.req := '0';
else
v.req := '1';
v.cache := '1';
end if;
else
if (ISETS > 1) and (ICREPLACE = lru) then vl.write := '1'; end if;
end if;
v.waddress := ici.fpc(31 downto PCLOW);
v.vaddress := ici.fpc(31 downto PCLOW);
end if;
if dco.icdiag.enable = '1' then
diagen := '1';
end if;
ddatain := dci.maddress;
if (ISETS > 1) then
if (ICREPLACE = lru) then
vl.set := conv_std_logic_vector(set, SETBITS);
vl.waddr := ici.fpc(OFFSET_HIGH downto OFFSET_LOW);
end if;
v.setrepl := conv_std_logic_vector(set, SETBITS);
if (((not hit) and (not dparerr(set)) and (not r.flush)) = '1') then
case ICREPLACE is
when rnd =>
if ICLOCK_BIT = 1 then
if lock(conv_integer(r.rndcnt)) = '0' then v.setrepl := r.rndcnt;
else
v.setrepl := conv_std_logic_vector(ISETS-1, SETBITS);
for i in ISETS-1 downto 0 loop
if (lock(i) = '0') and (i>conv_integer(r.rndcnt)) then
v.setrepl := conv_std_logic_vector(i, SETBITS);
end if;
end loop;
end if;
else
v.setrepl := r.rndcnt;
end if;
when lru =>
v.setrepl := lru_set(rl.lru(conv_integer(ici.fpc(OFFSET_HIGH downto OFFSET_LOW))), lock(0 to ISETS-1));
when lrr =>
v.setrepl := (others => '0');
if isetlock = 1 then
if lock(0) = '1' then v.setrepl(0) := '1';
else
v.setrepl(0) := icramo.tag(0)(CTAG_LRRPOS) xor icramo.tag(1)(CTAG_LRRPOS);
end if;
else
v.setrepl(0) := icramo.tag(0)(CTAG_LRRPOS) xor icramo.tag(1)(CTAG_LRRPOS);
end if;
if v.setrepl(0) = '0' then v.lrr := not icramo.tag(0)(CTAG_LRRPOS);
else v.lrr := icramo.tag(0)(CTAG_LRRPOS); end if;
end case;
end if;
if (ICLOCK_BIT = 1) then
if (hit and lock(set)) = '1' then v.lock := '1';
else v.lock := '0'; end if;
end if;
end if;
when trans =>
v.holdn := '0';
if (mmuico.transdata.finish = '1') then
if (mmuico.transdata.accexc) = '1' and ((mmudci.mmctrl1.nf) /= '1' or (r.su) = '1') then
-- if su then always do mexc
error := '1'; mds := '0';
v.holdn := '1'; v.istate := idle; v.burst := '0';
else
v.cache := mmuico.transdata.cache;
v.waddress := mmuico.transdata.data(31 downto PCLOW);
v.istate := streaming; v.req := '1';
end if;
end if;
when streaming => -- streaming: update cache and send data to IU
rdatasel := memory;
taddr(TAG_HIGH downto LINE_LOW) := r.vaddress(TAG_HIGH downto LINE_LOW);
branch := (ici.fbranch and r.overrun) or
(ici.rbranch and (not r.overrun));
v.underrun := r.underrun or
(write and ((ici.inull or not eholdn) and (mcio.ready and not (r.overrun and not r.underrun))));
v.overrun := (r.overrun or (eholdn and not ici.inull)) and
not (write or r.underrun);
if mcio.ready = '1' then
mds := not (r.overrun and not r.underrun);
v.burst := v.req and not (nnlastline and mcio.ready);
end if;
if mcio.grant = '1' then
v.req := dco.icdiag.cctrl.burst and r.burst and
(not (nnlastline and mcio.ready)) and (dco.icdiag.cctrl.burst or (not branch)) and
not (v.underrun and not cacheon);
v.burst := v.req and not (nnlastline and mcio.ready);
end if;
v.underrun := (v.underrun or branch) and not v.overrun;
v.holdn := not (v.overrun or v.underrun);
if (mcio.ready = '1') and (r.req = '0') then --(v.burst = '0') then
v.underrun := '0'; v.overrun := '0';
if (dco.icdiag.cctrl.ics(0) and not r.flush2) = '1' then
v.istate := stop; v.holdn := '0';
else
v.istate := idle; v.flush := r.flush2; v.holdn := '1';
if r.overrun = '1' then taddr := ici.fpc(TAG_HIGH downto LINE_LOW);
else taddr := ici.rpc(TAG_HIGH downto LINE_LOW); end if;
end if;
end if;
when stop => -- return to main
taddr := ici.fpc(TAG_HIGH downto LINE_LOW);
v.istate := idle; v.flush := r.flush2;
when others => v.istate := idle;
end case;
if mcio.retry = '1' then v.req := '1'; end if;
-- Generate new valid bits write strobe
vmaskraw := decode(r.waddress(LINE_HIGH downto LINE_LOW));
twrite := write;
if cacheon = '0' then
twrite := '0'; vmask := (others => '0');
elsif (dco.icdiag.cctrl.ics = "01") then
twrite := twrite and r.hit;
vmask := icramo.tag(set)(ilinesize-1 downto 0) or vmaskraw;
else
if r.hit = '1' then vmask := r.valid or vmaskraw;
else vmask := vmaskraw; end if;
end if;
if (mcio.mexc or (not mcio.cache) or (not r.cache)) = '1' then
twrite := '0'; dwrite := '0';
else dwrite := twrite; end if;
if twrite = '1' then
v.valid := vmask; v.hit := '1';
if (ISETS > 1) and (ICREPLACE = lru) then vl.write := '1'; end if;
end if;
if (ISETS > 1) and (ICREPLACE = lru) and (rl.write = '1') then
vl.lru(conv_integer(rl.waddr)) :=
lru_calc(rl.lru(conv_integer(rl.waddr)), conv_integer(rl.set));
end if;
-- cache write signals
if ISETS > 1 then setrepl := r.setrepl; else setrepl := (others => '0'); end if;
if twrite = '1' then ctwrite(conv_integer(setrepl)) := '1'; end if;
if dwrite = '1' then cdwrite(conv_integer(setrepl)) := '1'; end if;
-- diagnostic cache access
if diagen = '1' then
if (ISETS /= 1) then
v.diagset := dco.icdiag.addr(SETBITS -1 + TAG_LOW downto TAG_LOW);
end if;
end if;
if (ISETS /= 1) then
rdiagset := conv_integer(r.diagset);
vdiagset := conv_integer(v.diagset);
end if;
diagdata := icramo.data(rdiagset);
if diagen = '1' then -- diagnostic access
taddr(OFFSET_HIGH downto LINE_LOW) := dco.icdiag.addr(OFFSET_HIGH downto LINE_LOW);
wtag(TAG_HIGH downto TAG_LOW) := dci.maddress(TAG_HIGH downto TAG_LOW);
wlrr := dci.maddress(CTAG_LRRPOS);
wlock := dci.maddress(CTAG_LOCKPOS);
if dco.icdiag.tag = '1' then
twrite := not dco.icdiag.read; dwrite := '0';
ctwrite := (others => '0'); cdwrite := (others => '0');
ctwrite(vdiagset) := not dco.icdiag.read;
diagdata := icramo.tag(rdiagset);
else
dwrite := not dco.icdiag.read; twrite := '0';
cdwrite := (others => '0'); cdwrite(vdiagset) := not dco.icdiag.read;
ctwrite := (others => '0');
end if;
vmask := dci.maddress(ilinesize -1 downto 0);
v.diagrdy := '1';
end if;
-- select data to return on read access
rdata := icramo.data;
case rdatasel is
when memory => rdata(0) := mcio.data; set := 0;
when others =>
end case;
-- cache flush
if (ici.flush or dco.icdiag.flush) = '1' then
v.flush := '1'; v.flush2 := '1'; v.faddr := (others => '0');
v.pflush := dco.icdiag.pflush; wtag := (others => '0');
v.pflushr := '1';
v.pflushaddr := dco.icdiag.pflushaddr;
v.pflushtyp := dco.icdiag.pflushtyp;
end if;
if r.flush2 = '1' then
twrite := '1'; ctwrite := (others => '1'); vmask := (others => '0'); v.faddr := r.faddr +1;
taddr(OFFSET_HIGH downto OFFSET_LOW) := r.faddr; wlrr := '0'; wlock := '0';
if (r.faddr(IOFFSET_BITS -1) and not v.faddr(IOFFSET_BITS -1)) = '1' then
v.flush2 := '0';
end if;
v.lrr := '0';
-- precise flush, ASI_FLUSH_PAGE & ASI_FLUSH_CTX
--if M_EN then
if r.pflush = '1' then
twrite := '0'; ctwrite := (others => '0');
v.pflushr := not r.pflushr;
if r.pflushr = '0' then
for i in ISETS-1 downto 0 loop
pftag(OFFSET_HIGH downto OFFSET_LOW) := r.faddr;
pftag(TAG_HIGH downto TAG_LOW) := icramo.tag(i)(TAG_HIGH downto TAG_LOW); --icramo.itramout(i).tag;
--if (icramo.itramout(i).ctx = mmudci.mmctrl1.ctx) and
-- ((pftag(VA_I_U downto VA_I_D) = r.pflushaddr(VA_I_U downto VA_I_D)) or
-- (r.pflushtyp = '1')) then
ctwrite(i) := '1';
--end if;
end loop;
end if;
end if;
--end if;
end if;
-- reset
if rst = '0' then
v.istate := idle; v.req := '0'; v.burst := '0'; v.holdn := '1';
v.flush := '0'; v.flush2 := '0'; v.overrun := '0'; v.underrun := '0';
v.rndcnt := (others => '0'); v.lrr := '0'; v.setrepl := (others => '0');
v.diagset := (others => '0'); v.lock := '0'; v.trans_op := '0';
v.flush3 := '1';
end if;
if r.flush3 = '1' then
vl.lru := (others => (others => '0'));
end if;
-- Drive signals
c <= v; -- register inputs
cl <= vl; -- lru register inputs
-- tag ram inputs
enable := enable and not dco.icdiag.scanen;
for i in 0 to ISETS-1 loop
tag(i) := (others => '0');
tag(i)(ilinesize-1 downto 0) := vmask;
tag(i)(TAG_HIGH downto TAG_LOW) := wtag;
tag(i)(CTAG_LRRPOS) := wlrr;
tag(i)(CTAG_LOCKPOS) := wlock;
end loop;
icrami.tag <= tag;
icrami.tenable <= enable;
icrami.twrite <= ctwrite;
icrami.flush <= r.flush2;
icrami.ctx <= mmudci.mmctrl1.ctx;
-- data ram inputs
icrami.denable <= enable;
icrami.address(19 downto (OFFSET_HIGH - LINE_LOW +1)) <=
zero32(19 downto (OFFSET_HIGH - LINE_LOW +1));
icrami.address(OFFSET_HIGH - LINE_LOW downto 0) <= taddr(OFFSET_HIGH downto LINE_LOW);
icrami.data <= ddatain;
icrami.dwrite <= cdwrite;
-- memory controller inputs
mcii.address(31 downto 2) <= r.waddress(31 downto 2);
mcii.address(1 downto 0) <= "00";
mcii.su <= r.su;
mcii.burst <= r.burst;
mcii.req <= r.req;
mcii.flush <= r.flush;
-- mmu <-> icache
mmuici.trans_op <= mmuici_trans_op;
mmuici.transdata.data <= r.waddress(31 downto 2) & "00";
mmuici.transdata.su <= r.su;
mmuici.transdata.isid <= id_icache;
mmuici.transdata.read <= '1';
mmuici.transdata.wb_data <= (others => '0');
-- IU data cache inputs
ico.data <= rdata;
ico.mexc <= mcio.mexc or error;
ico.hold <= r.holdn;
ico.mds <= mds;
ico.flush <= r.flush;
ico.diagdata <= diagdata;
ico.diagrdy <= r.diagrdy;
ico.set <= conv_std_logic_vector(set, 2);
ico.cfg <= icfg;
ico.idle <= sidle;
end process;
-- Local registers
regs1 : process(clk)
begin if rising_edge(clk) then r <= c; end if; end process;
regs2gen : if (ISETS > 1) and (ICREPLACE = lru) generate
regs2 : process(clk)
begin if rising_edge(clk) then rl <= cl; end if; end process;
end generate;
nolru : if (ISETS = 1) or (irepl /= lru) generate
rl.write <= '0'; rl.waddr <= (others => '0');
rl.set <= (others => '0'); rl.lru <= (others => (others => '0'));
end generate;
-- pragma translate_off
chk : process
begin
assert not ((ISETS > 2) and (ICREPLACE = lrr)) report
"Wrong instruction cache configuration detected: LRR replacement requires 2 sets"
severity failure;
wait;
end process;
-- pragma translate_on
end ;
| mit | 3eef79f69158e3f417f29d7c2e25ad08 | 0.579082 | 3.344295 | false | false | false | false |
Pinwino/sa | debugger_gw/debugger_pkg.vhd | 1 | 6,589 | --
-- Package File Template
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions
--
-- To use any of the example code shown below, uncomment the lines and modify as necessary
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.gn4124_core_pkg.all;
use work.gencores_pkg.all;
use work.wrcore_pkg.all;
use work.wr_fabric_pkg.all;
use work.wishbone_pkg.all;
use work.fine_delay_pkg.all;
--use work.etherbone_pkg.all;
use work.wr_xilinx_pkg.all;
use work.genram_pkg.all;
use work.wb_irq_pkg.all;
package debugger_pkg is
------------------------------------------------------------------------------
-- Constants
-------------------------------------------------------------------------------
constant c_dbg_uart_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"7", -- 8/16/32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000ff",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"0deafbee", -- she didn't listen & cames & goes
version => x"00000001",
date => x"20120305",
name => "WB-UART-Debugger ")));
constant c_dbg_irq_ctrl_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"7", -- 8/16/32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000ff",
product => (
vendor_id => x"0000000000000651", -- GSI
device_id => x"e1fb1ade", -- balanced, perfect grip, absolute control
version => x"00000001",
date => x"20120308",
name => "IRQ_CTRL-Debugger ")));
constant c_xwb_dbg_tics_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"00",
wbd_endian => c_sdb_endian_big,
wbd_width => x"7", -- 8/16/32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"0000000000000000",
product => (
vendor_id => x"000000000000CE42", -- GSIx
device_id => x"fade1eaf", -- Time is always ticking!
version => x"00000001",
date => x"20111004",
name => "WB-Tics-Debugger ")));
constant c_dbg_irq_timer_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"7", -- 8/16/32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000ff",
product => (
vendor_id => x"0000000000000651", -- GSI
device_id => x"deadface", -- eventully "the dead line" is going to arrive
version => x"00000001",
date => x"20120308",
name => "IRQ_TIMER-Debugger ")));
constant c_xwb_dbg_slave_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"00",
wbd_endian => c_sdb_endian_big,
wbd_width => x"7", -- 8/16/32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"000000000003ffff",
product => (
vendor_id => x"a1eBEEFc0ffeeBED", -- Jose Jimenez Motel. Open 24/7. Next exit.
device_id => x"c0a110de", -- obvious (sadly)
version => x"00000001",
date => x"20140704",
name => "Debugger-Slave ")));
------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
function f_xwb_dbg_dpram(g_size : natural) return t_sdb_device
is
variable result : t_sdb_device;
begin
result.abi_class := x"0001"; -- RAM device
result.abi_ver_major := x"01";
result.abi_ver_minor := x"00";
result.wbd_width := x"7"; -- 32/16/8-bit supported
result.wbd_endian := c_sdb_endian_big;
result.sdb_component.addr_first := (others => '0');
result.sdb_component.addr_last := std_logic_vector(to_unsigned(g_size*4-1, 64));
result.sdb_component.product.vendor_id := x"000000000000CE42"; -- CERN
result.sdb_component.product.device_id := x"deafbeef"; -- she didn't listen & is as essential as protein
result.sdb_component.product.version := x"00000001";
result.sdb_component.product.date := x"20120305";
result.sdb_component.product.name := "BlockRAM-Debugger ";
return result;
end f_xwb_dbg_dpram;
------------------------------------------------------------------------------
-- Components declaration
-------------------------------------------------------------------------------
component wb_debugger is
generic (
g_dbg_dpram_size : integer := 40960/4;
g_dbg_init_file : string;
g_reset_vector : t_wishbone_address := x"00000000";
g_msi_queues : natural := 1;
g_profile : string := "medium_icache_debug";
g_internal_time_ref : boolean := true;
g_timers : integer := 1;
g_slave_interface_mode : t_wishbone_interface_mode := PIPELINED;
g_slave_granularity : t_wishbone_address_granularity := BYTE
);
port (
clk_sys : in std_logic;
reset_n : in std_logic;
master_i : in t_wishbone_master_in;
master_o : out t_wishbone_master_out;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
wrpc_uart_rxd_i : inout std_logic;
wrpc_uart_txd_o : inout std_logic;
uart_rxd_i : in std_logic;
uart_txd_o : out std_logic;
dbg_indicator : out std_logic;
dbg_control_select : in std_logic
);
end component;
end debugger_pkg;
package body debugger_pkg is
-- Notihg to include right now!!!
end debugger_pkg;
| gpl-3.0 | a54284b201a536af25dab2e9a781f831 | 0.518895 | 3.604486 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/sim/sram.vhd | 2 | 5,140 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: sram
-- File: sram.vhd
-- Author: Jiri Gaisler Gaisler Research
-- Description: Simulation model of generic async SRAM
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
library gaisler;
use gaisler.sim.all;
library grlib;
use grlib.stdlib.all;
entity sram is
generic (
index : integer := 0; -- Byte lane (0 - 3)
abits: Positive := 10; -- Default 10 address bits (1 Kbyte)
tacc : integer := 10; -- access time (ns)
fname : string := "ram.dat"; -- File to read from
clear : integer := 0); -- Clear memory
port (
a : in std_logic_vector(abits-1 downto 0);
d : inout std_logic_vector(7 downto 0);
ce1 : in std_logic;
we : in std_ulogic;
oe : in std_ulogic);
end;
architecture sim of sram is
subtype BYTE is std_logic_vector(7 downto 0);
type MEM is array(0 to ((2**Abits)-1)) of BYTE;
signal DINT,DI,DO : BYTE;
constant ahigh : integer := abits - 1;
signal wrpre : std_ulogic;
function Vpar(vec : std_logic_vector) return std_ulogic is
variable par : std_ulogic := '1';
begin
for i in vec'range loop --'
par := par xor vec(i);
end loop;
return par;
end;
begin
RAM : process(CE1,WE,DI,A,OE,D)
variable MEMA : MEM;
variable L1 : line;
variable FIRST : boolean := true;
variable ADR : std_logic_vector(19 downto 0);
variable BUF : std_logic_vector(31 downto 0);
variable CH : character;
variable ai : integer := 0;
file TCF : text open read_mode is fname;
variable rectype : std_logic_vector(3 downto 0);
variable recaddr : std_logic_vector(31 downto 0);
variable reclen : std_logic_vector(7 downto 0);
variable recdata : std_logic_vector(0 to 16*8-1);
begin
if FIRST then
if clear = 1 then MEMA := (others => X"00"); end if;
L1:= new string'(""); --'
while not endfile(TCF) loop
readline(TCF,L1);
if (L1'length /= 0) then --'
while (not (L1'length=0)) and (L1(L1'left) = ' ') loop
std.textio.read(L1,CH);
end loop;
if L1'length > 0 then --'
read(L1, ch);
if (ch = 'S') or (ch = 's') then
hexread(L1, rectype);
hexread(L1, reclen);
recaddr := (others => '0');
case rectype is
when "0001" =>
hexread(L1, recaddr(15 downto 0));
when "0010" =>
hexread(L1, recaddr(23 downto 0));
when "0011" =>
hexread(L1, recaddr);
recaddr(31 downto abits) := (others => '0');
when others => next;
end case;
hexread(L1, recdata);
if index = 6 then
ai := conv_integer(recaddr);
for i in 0 to 15 loop
MEMA(ai+i) := recdata((i*8) to (i*8+7));
end loop;
elsif (index = 4) or (index = 5) then
ai := conv_integer(recaddr)/2;
for i in 0 to 7 loop
MEMA(ai+i) := recdata((i*16+(index-4)*8) to (i*16+(index-4)*8+7));
end loop;
else
ai := conv_integer(recaddr)/4;
for i in 0 to 3 loop
MEMA(ai+i) := recdata((i*32+index*8) to (i*32+index*8+7));
end loop;
end if;
end if;
end if;
end if;
end loop;
FIRST := false;
else
if (TO_X01(not CE1) = '1') then
if not is_x(a) then ai := conv_integer(A(abits-1 downto 0)); else ai := 0; end if;
dint <= mema(ai);
end if;
if (TO_X01(CE1 or WE) = '1') then
if wrpre = '1' then
mema(ai) := to_x01(std_logic_vector(DI));
end if;
end if;
end if;
wrpre <= TO_X01((not CE1) and (not WE));
DI <= D;
end process;
BUFS : process(CE1,WE,DINT,OE)
variable DRIVEB : std_logic;
begin
DRIVEB := TO_X01((not CE1) and (not OE) and WE);
case DRIVEB is
when '1' => D <= DINT after tacc * 1 ns;
when '0' => D <= "ZZZZZZZZ" after 8 ns;
when others => D <= "XXXXXXXX";
end case;
end process;
end sim;
-- pragma translate_on
| mit | 4c337a0de04aed1b1341100cd8255e34 | 0.550389 | 3.53022 | false | false | false | false |
michaelfivez/ascon_hardware_implementation | ascon128128_serialized/Kernel/Ascon_block_control.vhd | 1 | 9,965 | -------------------------------------------------------------------------------
--! @project Serialized hardware implementation of Asconv128128
--! @author Michael Fivez
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is an hardware implementation made for my graduation thesis
--! at the KULeuven, in the COSIC department (year 2015-2016)
--! The thesis is titled 'Energy efficient hardware implementations of CAESAR submissions',
--! and can be found on the COSIC website (www.esat.kuleuven.be/cosic/publications)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Ascon_StateUpdate_control is
port(
Clk : in std_logic; -- Clock
Reset : in std_logic; -- Reset (synchronous)
-- Control signals
RoundNr : out std_logic_vector(3 downto 0); -- biggest round is 12
sel1,sel2,sel3,sel4 : out std_logic_vector(1 downto 0);
sel0 : out std_logic_vector(2 downto 0);
selout : out std_logic;
SelSbox : out std_logic_vector(1 downto 0);
SelDiff : out std_logic_vector(2 downto 0);
Reg0En,Reg1En,Reg2En,Reg3En,Reg4En,RegOutEn : out std_logic;
SboxEnable : out std_logic;
ActivateGen : out std_logic;
GenSize : out std_logic_vector(3 downto 0);
-- External control signals
Start : in std_logic;
Mode : in std_logic_vector(3 downto 0);
Size : in std_logic_vector(3 downto 0); -- only matters for last block decryption
Busy : out std_logic
);
end entity Ascon_StateUpdate_control;
architecture structural of Ascon_StateUpdate_control is
begin
-----------------------------------------
------ The Finite state machine --------
-----------------------------------------
-- Modes: initialization, associative data, encryption, decryption, tag generation, final encryption, final decryption, seperation constant
-- 0010 0000 0110 0100 0001 0111 0101, 0011
-- case1 1000, case2 1001
fsm: process(Clk, Reset) is
type state_type is (IDLE,LOADNEW,CRYPT,TAG);
variable CurrState : state_type := IDLE;
variable RoundNrVar : std_logic_vector(3 downto 0);
variable Selint : std_logic_vector(3 downto 0);
begin
if Clk'event and Clk = '1' then
-- default values
sel0 <= "000";
sel1 <= "00";
sel2 <= "00";
sel3 <= "00";
sel4 <= "00";
selout <= '0';
SelSbox <= "00";
SelDiff <= "000";
Reg0En <= '0';
Reg1En <= '0';
Reg2En <= '0';
Reg3En <= '0';
Reg4En <= '0';
RegOutEn <= '0';
SboxEnable <= '0';
ActivateGen <= '0';
GenSize <= "0000";
Busy <= '0';
if Reset = '1' then -- synchronous reset active high
-- registers used by fsm:
RoundNrVar := "0000";
CurrState := IDLE;
else
FSMlogic : case CurrState is
when IDLE =>
if Start = '1' then
Busy <= '1';
if Mode = "0000" then -- AD mode
RoundNrVar := "0000"; -- so starts at 0 next cycle
Selint := (others => '0');
-- set Sel and Enables signal (Xor with DataIn)
sel0 <= "010";
sel1 <= "10";
Reg0En <= '1';
Reg1En <= '1';
CurrState := CRYPT;
elsif Mode = "0100" then -- Decryption mode
RoundNrVar := "0000"; -- so starts at 0 next cycle
Selint := (others => '0');
-- set Sel and Enables signal (Generate output and xor state)
ActivateGen <= '1';
sel0 <= "010";
sel1 <= "10";
Reg0En <= '1';
Reg1En <= '1';
RegOutEn <= '1';
CurrState := CRYPT;
elsif Mode = "0110" then -- Encryption
RoundNrVar := "0000"; -- so starts at 0 next cycle
Selint := (others => '0');
-- set Sel and Enables signal (Generate output and xor state)
sel0 <= "010";
sel1 <= "10";
Reg0En <= '1';
Reg1En <= '1';
RegOutEn <= '1';
CurrState := CRYPT;
elsif Mode = "0001" then -- Tag mode
RoundNrVar := "0000"; -- so starts at 0 next cycle
Selint := (others => '0');
-- set Sel and Enables signal (XOR middle with key)
sel2 <= "10";
sel3 <= "11";
Reg2En <= '1';
Reg3En <= '1';
CurrState := TAG;
elsif Mode = "0111" then -- Last block encryption
-- set Sel and Enables signal (Generate output and xor state)
sel0 <= "010";
sel1 <= "10";
Reg0En <= '1';
Reg1En <= '1';
RegOutEn <= '1';
CurrState := IDLE;
elsif Mode = "0101" then -- Last block decryption
-- set Sel and Enables signal (Generate output and xor state)
ActivateGen <= '1';
GenSize <= Size;
sel0 <= "010";
sel1 <= "10";
Reg0En <= '1';
Reg1En <= '1';
RegOutEn <= '1';
CurrState := IDLE;
elsif Mode = "0011" then -- Seperation constant
sel4 <= "11";
Reg4En <= '1';
CurrState := IDLE;
elsif Mode = "0010" then -- Initialization mode
RoundNrVar := "0000";
Selint := (others => '0');
-- set Sel and Enables signal (Load in key and IV)
sel0 <= "001";
sel1 <= "01";
sel2 <= "01";
sel3 <= "01";
sel4 <= "01";
Reg0En <= '1';
Reg1En <= '1';
Reg2En <= '1';
Reg3En <= '1';
Reg4En <= '1';
CurrState := LOADNEW;
elsif Mode = "1000" then -- case1
sel0 <= "100";
Reg0En <= '1';
CurrState := IDLE;
else -- case2
sel0 <= "100";
Reg0En <= '1';
RoundNrVar := "0000"; -- so starts at 0 next cycle
Selint := (others => '0');
CurrState := CRYPT;
end if;
else
Busy <= '0';
CurrState := IDLE;
end if;
when LOADNEW =>
if Selint = "0000" and RoundNrVar = "1100" then
sel3 <= "10";
sel4 <= "10";
Reg3En <= '1';
Reg4En <= '1';
Busy <= '0';
CurrState := IDLE;
elsif Selint(3 downto 2) = "00" then -- sbox part
Busy <= '1';
SelSbox <= Selint(1 downto 0);
SboxEnable <= '1';
Selint := std_logic_vector(unsigned(Selint) + 1);
elsif Selint = "0100" then -- linear diffusion layer part 1
Busy <= '1';
SelDiff <= "000";
Reg0En <= '1';
Selint := std_logic_vector(unsigned(Selint) + 1);
elsif Selint = "0101" then -- linear diffusion layer part 2
Busy <= '1';
SelDiff <= "001";
Reg1En <= '1';
Selint := std_logic_vector(unsigned(Selint) + 1);
elsif Selint = "0110" then -- linear diffusion layer part 3
Busy <= '1';
SelDiff <= "010";
Reg2En <= '1';
Selint := std_logic_vector(unsigned(Selint) + 1);
elsif Selint = "0111" then -- linear diffusion layer part 4
Busy <= '1';
SelDiff <= "011";
Reg3En <= '1';
Selint := std_logic_vector(unsigned(Selint) + 1);
elsif Selint = "1000" then -- linear diffusion layer part 5
Busy <= '1';
SelDiff <= "100";
Reg4En <= '1';
Selint := (others => '0');
RoundNrVar := std_logic_vector(unsigned(RoundNrVar) + 1);
end if;
when CRYPT =>
if Selint(3 downto 2) = "00" then -- sbox part
Busy <= '1';
SelSbox <= Selint(1 downto 0);
SboxEnable <= '1';
Selint := std_logic_vector(unsigned(Selint) + 1);
elsif Selint = "0100" then -- linear diffusion layer part 1
Busy <= '1';
SelDiff <= "000";
Reg0En <= '1';
Selint := std_logic_vector(unsigned(Selint) + 1);
elsif Selint = "0101" then -- linear diffusion layer part 2
Busy <= '1';
SelDiff <= "001";
Reg1En <= '1';
Selint := std_logic_vector(unsigned(Selint) + 1);
elsif Selint = "0110" then -- linear diffusion layer part 3
Busy <= '1';
SelDiff <= "010";
Reg2En <= '1';
Selint := std_logic_vector(unsigned(Selint) + 1);
elsif Selint = "0111" then -- linear diffusion layer part 4
Busy <= '1';
SelDiff <= "011";
Reg3En <= '1';
Selint := std_logic_vector(unsigned(Selint) + 1);
elsif Selint = "1000" then -- linear diffusion layer part 5
Busy <= '1';
SelDiff <= "100";
Reg4En <= '1';
Selint := (others => '0');
RoundNrVar := std_logic_vector(unsigned(RoundNrVar) + 1);
if RoundNrVar = "1000" then
CurrState := IDLE;
else
Busy <= '1';
end if;
end if;
when TAG =>
if Selint = "0000" and RoundNrVar = "1100" then
-- set Sel and Enables signal (connect tag to output)
selout <= '1';
RegOutEn <= '1';
CurrState := IDLE;
Busy <= '0';
elsif Selint(3 downto 2) = "00" then -- sbox part
Busy <= '1';
SelSbox <= Selint(1 downto 0);
SboxEnable <= '1';
Selint := std_logic_vector(unsigned(Selint) + 1);
elsif Selint = "0100" then -- linear diffusion layer part 1
Busy <= '1';
SelDiff <= "000";
Reg0En <= '1';
Selint := std_logic_vector(unsigned(Selint) + 1);
elsif Selint = "0101" then -- linear diffusion layer part 2
Busy <= '1';
SelDiff <= "001";
Reg1En <= '1';
Selint := std_logic_vector(unsigned(Selint) + 1);
elsif Selint = "0110" then -- linear diffusion layer part 3
Busy <= '1';
SelDiff <= "010";
Reg2En <= '1';
Selint := std_logic_vector(unsigned(Selint) + 1);
elsif Selint = "0111" then -- linear diffusion layer part 4
Busy <= '1';
SelDiff <= "011";
Reg3En <= '1';
Selint := std_logic_vector(unsigned(Selint) + 1);
elsif Selint = "1000" then -- linear diffusion layer part 5
Busy <= '1';
SelDiff <= "100";
Reg4En <= '1';
Selint := (others => '0');
RoundNrVar := std_logic_vector(unsigned(RoundNrVar) + 1);
end if;
end case FSMlogic;
RoundNr <= RoundNrVar;
end if;
end if;
end process fsm;
end architecture structural;
| gpl-3.0 | 3f4120d17bed95f515af51a8d1f88ad9 | 0.544706 | 3.124804 | false | false | false | false |
SteffenReith/J1Sc | src/test/vhdl/J1Nexys4X_IRQ_tb.vhd | 1 | 2,576 | --------------------------------------------------------------------------------
-- Author: Steffen Reith ([email protected])
--
-- Creation Date: Sun Dec 11 11:46:48 GMT+1 2016
-- Creator: Steffen Reith
-- Module Name: J1SoC_IRQ_TB - A simple testbench for testing the interrupts
-- of the J1 SoC
-- Project Name: J1Sc - A simple J1 implementation in scala
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
entity J1Nexys4X_IRQ_tb is
end J1Nexys4X_IRQ_tb;
architecture Behavioral of J1Nexys4X_IRQ_tb is
-- Clock period definition (100Mhz)
constant clk_period : time := 10 ns;
-- Interrupts
signal extInt : std_logic_vector(0 downto 0) := "0";
-- PModA-Interface
signal pmodA_read : std_logic_vector(7 downto 0);
signal pmodA_write : std_logic_vector(7 downto 0);
signal pmodA_writeEnable : std_logic_vector(7 downto 0);
-- UART signals
signal rx : std_logic := '0';
signal tx : std_logic;
-- I/O signals
signal leds : std_logic_vector(15 downto 0);
-- Clock and reset
signal boardClkLocked : std_logic;
signal boardClk : std_logic;
signal reset : std_logic;
begin
uut : entity work.J1Nexys4X
port map (boardClk => boardClk,
boardClkLocked => boardClkLocked,
reset => reset,
extInt => extInt,
pmodA_read => pmodA_read,
pmodA_write => pmodA_write,
pmodA_writeEnable => pmodA_writeEnable,
rx => rx,
tx => tx,
leds => leds);
-- Clock process definitions
clk_process : process
begin
-- Tell that the clock is stable
boardClkLocked <= '1';
boardClk <= '0';
wait for clk_period/2;
boardClk <= '1';
wait for clk_period/2;
end process;
reboot_proc : process
begin
-- Reset the CPU (asynchron)
reset <= '1';
-- Wait 107ns
wait for 107 ns;
-- Revoke the the reset
reset <= '0';
-- Wait forever
wait;
end process;
-- Stimulus process
stim_proc : process
-- Text I/O
variable lineBuffer : line;
begin
-- Give a info message
write(lineBuffer, string'("Start the simulation of the CPU"));
writeline(output, lineBuffer);
-- Simply wait forever
wait;
end process;
end architecture;
| bsd-3-clause | 4423b4d54cd6363a37d740193a005fb8 | 0.545031 | 3.932824 | false | false | false | false |
lxp32/lxp32-cpu | verify/icache/src/tb/tb.vhd | 2 | 2,264 | ---------------------------------------------------------------------
-- LXP32 instruction cache verification environment (self-checking
-- testbench)
--
-- Part of the LXP32 instruction cache testbench
--
-- Copyright (c) 2016 by Alex I. Kuznetsov
--
-- Parameters:
-- CACHE_BURST_SIZE: burst size for cache unit
-- CACHE_PREFETCH_SIZE: prefetch distance for cache unit
-- CPU_BLOCKS: number of data blocks to fetch
-- VERBOSE: print more messages
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity tb is
generic(
CACHE_BURST_SIZE: integer:=16;
CACHE_PREFETCH_SIZE: integer:=32;
CPU_BLOCKS: integer:=100000;
VERBOSE: boolean:=false
);
end entity;
architecture testbench of tb is
signal clk: std_logic:='0';
signal rst: std_logic:='0';
signal lli_re: std_logic;
signal lli_adr: std_logic_vector(29 downto 0);
signal lli_dat: std_logic_vector(31 downto 0);
signal lli_busy: std_logic;
signal wbm_cyc: std_logic;
signal wbm_stb: std_logic;
signal wbm_cti: std_logic_vector(2 downto 0);
signal wbm_bte: std_logic_vector(1 downto 0);
signal wbm_ack: std_logic;
signal wbm_adr: std_logic_vector(29 downto 0);
signal wbm_dat: std_logic_vector(31 downto 0);
signal finish: std_logic:='0';
begin
clk<=not clk and not finish after 5 ns;
dut: entity work.lxp32_icache(rtl)
generic map(
BURST_SIZE=>CACHE_BURST_SIZE,
PREFETCH_SIZE=>CACHE_PREFETCH_SIZE
)
port map(
clk_i=>clk,
rst_i=>rst,
lli_re_i=>lli_re,
lli_adr_i=>lli_adr,
lli_dat_o=>lli_dat,
lli_busy_o=>lli_busy,
wbm_cyc_o=>wbm_cyc,
wbm_stb_o=>wbm_stb,
wbm_cti_o=>wbm_cti,
wbm_bte_o=>wbm_bte,
wbm_ack_i=>wbm_ack,
wbm_adr_o=>wbm_adr,
wbm_dat_i=>wbm_dat
);
ram_model_inst: entity work.ram_model(sim)
port map(
clk_i=>clk,
wbm_cyc_i=>wbm_cyc,
wbm_stb_i=>wbm_stb,
wbm_cti_i=>wbm_cti,
wbm_bte_i=>wbm_bte,
wbm_ack_o=>wbm_ack,
wbm_adr_i=>wbm_adr,
wbm_dat_o=>wbm_dat
);
cpu_model_inst: entity work.cpu_model(sim)
generic map(
BLOCKS=>CPU_BLOCKS,
VERBOSE=>VERBOSE
)
port map(
clk_i=>clk,
lli_re_o=>lli_re,
lli_adr_o=>lli_adr,
lli_dat_i=>lli_dat,
lli_busy_i=>lli_busy,
finish_o=>finish
);
end architecture;
| mit | 73f4eff4857bb696125c236315fa701d | 0.624558 | 2.764347 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/ata/ocidec2_amba_slave.vhd | 2 | 14,461 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ocidec2_amba_slave
-- File: ocidec2_amba_slave.vhd
-- Author: Nils-Johan Wessman, Gaisler Research
-- Description: ATA controller
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use grlib.devices.all;
use gaisler.memctrl.all;
entity ocidec2_amba_slave is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#ff0#;
pirq : integer := 0;
DeviceID : integer := 0;
RevisionNo : integer := 0;
-- PIO mode 0 settings (@100MHz clock)
PIO_mode0_T1 : natural := 6; -- 70ns
PIO_mode0_T2 : natural := 28; -- 290ns
PIO_mode0_T4 : natural := 2; -- 30ns
PIO_mode0_Teoc : natural := 23; -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240
-- Multiword DMA mode 0 settings (@100MHz clock)
DMA_mode0_Tm : natural := 4; -- 50ns
DMA_mode0_Td : natural := 21; -- 215ns
DMA_mode0_Teoc : natural := 21 -- 215ns ==> T0 - Td - Tm = 480 - 50 - 215 = 215
);
port (
rst : in std_ulogic;
arst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
cf_power: out std_logic;
-- ata controller signals
-- PIO control input
PIOsel : out std_logic;
PIOtip, -- PIO transfer in progress
PIOack : in std_logic; -- PIO acknowledge signal
PIOq : in std_logic_vector(15 downto 0); -- PIO data input
PIOpp_full : in std_logic; -- PIO write-ping-pong buffers full
irq : in std_logic; -- interrupt signal input
PIOa : out std_logic_vector(3 downto 0);
PIOd : out std_logic_vector(15 downto 0);
PIOwe : out std_logic;
-- DMA control inputs
DMAsel : out std_logic;
DMAtip, -- DMA transfer in progress
DMAack, -- DMA transfer acknowledge
DMARxEmpty, -- DMA receive buffer empty
DMATxFull, -- DMA transmit buffer full
DMA_dmarq : in std_logic; -- wishbone DMA request
DMAq : in std_logic_vector(31 downto 0);
-- outputs
-- control register outputs
IDEctrl_rst,
IDEctrl_IDEen,
IDEctrl_FATR1,
IDEctrl_FATR0,
IDEctrl_ppen,
DMActrl_DMAen,
DMActrl_dir,
DMActrl_BeLeC0,
DMActrl_BeLeC1 : out std_logic;
-- CMD port timing registers
PIO_cmdport_T1,
PIO_cmdport_T2,
PIO_cmdport_T4,
PIO_cmdport_Teoc : out std_logic_vector(7 downto 0);
PIO_cmdport_IORDYen : out std_logic;
-- data-port0 timing registers
PIO_dport0_T1,
PIO_dport0_T2,
PIO_dport0_T4,
PIO_dport0_Teoc : out std_logic_vector(7 downto 0);
PIO_dport0_IORDYen : out std_logic;
-- data-port1 timing registers
PIO_dport1_T1,
PIO_dport1_T2,
PIO_dport1_T4,
PIO_dport1_Teoc : out std_logic_vector(7 downto 0);
PIO_dport1_IORDYen : out std_logic;
-- DMA device0 timing registers
DMA_dev0_Tm,
DMA_dev0_Td,
DMA_dev0_Teoc : out std_logic_vector(7 downto 0);
-- DMA device1 timing registers
DMA_dev1_Tm,
DMA_dev1_Td,
DMA_dev1_Teoc : out std_logic_vector(7 downto 0)
);
end;
architecture rtl of ocidec2_amba_slave is
constant VERSION : amba_version_type := 0;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg(VENDOR_GAISLER, GAISLER_ATACTRL, 0, VERSION, pirq),
4 => ahb_iobar(haddr, hmask),
others => zero32);
type PIOtiming_type is record
T1,T2,T4,Teoc : std_logic_vector(7 downto 0);
end record;
type DMAtiming_type is record
Tm,Td,Teoc : std_logic_vector(7 downto 0);
end record;
-- local registers
type reg_type is record
-- AHB signal
hready : std_ulogic; -- Hready
hsel : std_ulogic; -- Hsel
hmbsel : std_logic_vector(0 to 2); -- Mem map select
haddr : std_logic_vector(31 downto 0); -- Haddr
hrdata : std_logic_vector(31 downto 0); -- Hreaddata
hwdata : std_logic_vector(31 downto 0); -- Hwritedata
hwrite : std_ulogic; -- Hwrite
htrans : std_logic_vector(1 downto 0); -- Htrans type
hburst : std_logic_vector(2 downto 0); -- Hburst type
hresp : std_logic_vector(1 downto 0); -- Hresp type
size : std_logic_vector(1 downto 0); -- Part of Hsize
piosel : std_logic;
irq : std_logic;
irqv : std_logic_vector(NAHBIRQ-1 downto 0);
pioack : std_logic;
atasel : std_logic;
-- reg signal
ctrlreg : std_logic_vector(31 downto 0);
statreg : std_logic_vector(31 downto 0);
pio_cmd : PIOtiming_type;
pio_dp0 : PIOtiming_type;
pio_dp1 : PIOtiming_type;
dma_dev0 : DMAtiming_type;
dma_dev1 : DMAtiming_type;
end record;
signal r, ri : reg_type;
begin
ctrl : process(rst, ahbsi, r, PIOack, PIOtip, PIOpp_full, irq, PIOq,
DMAtip, DMARxEmpty, DMATxFull, DMA_dmarq)
variable v : reg_type; -- local variables for registers
variable int : std_logic;
begin
-- Variable default settings to avoid latches
v := r;
v.hresp := HRESP_OKAY;
v.irqv := (others => '0');
int := '1';
v.irq := irq;
v.irqv(pirq) := v.irq and not r.irq;
v.pioack := PIOack;
if (ahbsi.hready = '1') and (ahbsi.hsel(hindex) and ahbsi.htrans(1)) = '1' then
v.size := ahbsi.hsize(1 downto 0);
v.hwrite := ahbsi.hwrite;
v.htrans := ahbsi.htrans;
v.hburst := ahbsi.hburst;
v.hsel := '1';
v.haddr := ahbsi.haddr;
v.piosel := ahbsi.haddr(6);
v.atasel := ahbsi.haddr(6);
if ahbsi.hwrite = '0' or ahbsi.haddr(6) = '1' then -- Read or ATA
v.hready := '0';
else -- Write
v.hready := '1';
end if;
else
v.hsel := '0';
if PIOack = '1' then
v.piosel := '0';
end if;
v.hready := r.pioack or not r.atasel;
if r.pioack = '1' then
v.atasel := '0';
end if;
end if;
if r.hsel = '1' and r.atasel = '0' and r.hwrite = '1' then -- Write
case r.haddr(5 downto 2) is
when "0000" => -- Control register 0x0
v.ctrlreg := ahbsi.hwdata;
when "0001" => -- Status register 0x4
int := ahbsi.hwdata(0); -- irq bit in status reg
when "0010" => -- PIO Compatible timing register 0x8
v.pio_cmd.T1 := ahbsi.hwdata(7 downto 0);
v.pio_cmd.T2 := ahbsi.hwdata(15 downto 8);
v.pio_cmd.T4 := ahbsi.hwdata(23 downto 16);
v.pio_cmd.Teoc := ahbsi.hwdata(31 downto 24);
when "0011" => -- PIO Fast timing register device 0 0xc
v.pio_dp0.T1 := ahbsi.hwdata(7 downto 0);
v.pio_dp0.T2 := ahbsi.hwdata(15 downto 8);
v.pio_dp0.T4 := ahbsi.hwdata(23 downto 16);
v.pio_dp0.Teoc := ahbsi.hwdata(31 downto 24);
when "0100" => -- PIO Fast timing register device 1 0x10
v.pio_dp1.T1 := ahbsi.hwdata(7 downto 0);
v.pio_dp1.T2 := ahbsi.hwdata(15 downto 8);
v.pio_dp1.T4 := ahbsi.hwdata(23 downto 16);
v.pio_dp1.Teoc := ahbsi.hwdata(31 downto 24);
when "0101" => -- DMA timing register device 0 0x14
v.dma_dev0.Tm := ahbsi.hwdata(7 downto 0);
v.dma_dev0.Td := ahbsi.hwdata(15 downto 8);
v.dma_dev0.Teoc := ahbsi.hwdata(31 downto 24);
when "0110" => -- DMA timing register device 1 0x18
v.dma_dev1.Tm := ahbsi.hwdata(7 downto 0);
v.dma_dev1.Td := ahbsi.hwdata(15 downto 8);
v.dma_dev1.Teoc := ahbsi.hwdata(31 downto 24);
when others => null;
end case;
elsif r.hsel = '1' and r.atasel = '1' and r.hwrite = '1' then -- ATA IO device 0x40-
v.hwdata := ahbsi.hwdata;
end if;
if r.hsel = '1' and r.atasel = '0' and r.hwrite = '0' then -- Read
case r.haddr(5 downto 2) is
when "0000" => -- Control register 0x0
v.hrdata := r.ctrlreg;
when "0001" => -- Status register 0x4
v.hrdata := r.statreg;
when "0010" => -- PIO Compatible timing register 0x8
v.hrdata := (r.pio_cmd.Teoc & r.pio_cmd.T4 & r.pio_cmd.T2 &
r.pio_cmd.T1);
when "0011" => -- PIO Fast timing register device 0 0xc
v.hrdata := (r.pio_dp0.Teoc & r.pio_dp0.T4 & r.pio_dp0.T2 &
r.pio_dp0.T1);
when "0100" => -- PIO Fast timing register device 1 0x10
v.hrdata := (r.pio_dp1.Teoc & r.pio_dp1.T4 & r.pio_dp1.T2 &
r.pio_dp1.T1);
when "0101" => -- DMA timing register device 0 0x14
v.hrdata := (r.dma_dev0.Teoc & x"00" & r.dma_dev0.Td &
r.dma_dev0.Tm);
when "0110" => -- DMA timing register device 1 0x18
v.hrdata := (r.dma_dev1.Teoc & x"00" & r.dma_dev1.Td &
r.dma_dev1.Tm);
when others =>
v.hrdata := x"aaaaaaaa";
end case;
elsif r.atasel = '1' then -- ATA IO device 0x40-
v.hrdata := (x"0000" & PIOq);
end if;
-- Status register
v.statreg(31 downto 0) := (others => '0'); -- clear all bits (read unused bits as '0')
v.statreg(31 downto 28) := std_logic_vector(to_unsigned(DeviceId,4)); -- set Device ID
v.statreg(27 downto 24) := std_logic_vector(to_unsigned(RevisionNo,4)); -- set revision number
v.statreg(15) := DMAtip;
v.statreg(10) := DMARxEmpty;
v.statreg(9) := DMATxFull;
v.statreg(8) := DMA_dmarq;
v.statreg(7) := PIOtip;
v.statreg(6) := PIOpp_full;
v.statreg(0) := (r.statreg(0) or (v.irq and not r.irq)) and int;
-- reset
if rst = '0' then
v.ctrlreg := (0 => '1', others => '0');
v.statreg(0) := '0';
v.haddr := (others => '0');
v.hwrite := '0';
v.hready := '1';
v.pioack := '0';
v.atasel := '0';
v.piosel := '0';
v.pio_cmd.T1 := conv_std_logic_vector(PIO_mode0_T1,8);
v.pio_cmd.T2 := conv_std_logic_vector(PIO_mode0_T2,8);
v.pio_cmd.T4 := conv_std_logic_vector(PIO_mode0_T4,8);
v.pio_cmd.Teoc := conv_std_logic_vector(PIO_mode0_Teoc,8);
v.pio_dp0.T1 := conv_std_logic_vector(PIO_mode0_T1,8);
v.pio_dp0.T2 := conv_std_logic_vector(PIO_mode0_T2,8);
v.pio_dp0.T4 := conv_std_logic_vector(PIO_mode0_T4,8);
v.pio_dp0.Teoc := conv_std_logic_vector(PIO_mode0_Teoc,8);
v.pio_dp1.T1 := conv_std_logic_vector(PIO_mode0_T1,8);
v.pio_dp1.T2 := conv_std_logic_vector(PIO_mode0_T2,8);
v.pio_dp1.T4 := conv_std_logic_vector(PIO_mode0_T4,8);
v.pio_dp1.Teoc := conv_std_logic_vector(PIO_mode0_Teoc,8);
v.dma_dev0.Tm := conv_std_logic_vector(DMA_mode0_Tm,8);
v.dma_dev0.Td := conv_std_logic_vector(DMA_mode0_Td,8);
v.dma_dev0.Teoc := conv_std_logic_vector(DMA_mode0_Teoc,8);
v.dma_dev1.Tm := conv_std_logic_vector(DMA_mode0_Tm,8);
v.dma_dev1.Td := conv_std_logic_vector(DMA_mode0_Td,8);
v.dma_dev1.Teoc := conv_std_logic_vector(DMA_mode0_Teoc,8);
end if;
-- assign control bits
cf_power <= r.ctrlreg(31);
DMActrl_DMAen <= r.ctrlreg(15);
DMActrl_dir <= r.ctrlreg(13);
DMActrl_BeLeC1 <= r.ctrlreg(9);
DMActrl_BeLeC0 <= r.ctrlreg(8);
IDEctrl_IDEen <= r.ctrlreg(7);
IDEctrl_FATR1 <= r.ctrlreg(6);
IDEctrl_FATR0 <= r.ctrlreg(5);
IDEctrl_ppen <= r.ctrlreg(4);
PIO_dport1_IORDYen <= r.ctrlreg(3);
PIO_dport0_IORDYen <= r.ctrlreg(2);
PIO_cmdport_IORDYen <= r.ctrlreg(1);
IDEctrl_rst <= r.ctrlreg(0);
-- CMD port timing
PIO_cmdport_T1 <= r.pio_cmd.T1; PIO_cmdport_T2 <= r.pio_cmd.T2;
PIO_cmdport_T4 <= r.pio_cmd.T4; PIO_cmdport_Teoc <= r.pio_cmd.Teoc;
-- data-port0 timing
PIO_dport0_T1 <= r.pio_dp0.T1; PIO_dport0_T2 <= r.pio_dp0.T2;
PIO_dport0_T4 <= r.pio_dp0.T4; PIO_dport0_Teoc <= r.pio_dp0.Teoc;
-- data-port1 timing
PIO_dport1_T1 <= r.pio_dp1.T1; PIO_dport1_T2 <= r.pio_dp1.T2;
PIO_dport1_T4 <= r.pio_dp1.T4; PIO_dport1_Teoc <= r.pio_dp1.Teoc;
-- DMA device0 timing
DMA_dev0_Tm <= r.dma_dev0.Tm; DMA_dev0_Td <= r.dma_dev0.Td;
DMA_dev0_Teoc <= r.dma_dev0.Teoc;
-- DMA device1 timing
DMA_dev1_Tm <= r.dma_dev0.Tm; DMA_dev1_Td <= r.dma_dev0.Td;
DMA_dev1_Teoc <= r.dma_dev0.Teoc;
ri <= v;
PIOa <= r.haddr(5 downto 2);
PIOd <= r.hwdata(15 downto 0);
PIOsel <= r.piosel;
PIOwe <= r.hwrite;
DMAsel <= '0'; -- temp ***
ahbso.hready <= r.hready;
ahbso.hresp <= r.hresp;
ahbso.hrdata <= r.hrdata;
ahbso.hconfig <= hconfig;
ahbso.hcache <= '0';
ahbso.hirq <= r.irqv;
ahbso.hindex <= hindex;
end process;
regs : process(clk,rst)
begin
if rising_edge(clk) then
r <= ri;
end if;
if rst = '0' then
end if;
end process;
end;
| mit | abc708ec31ed4dd60fed22c35f25ebcf | 0.551138 | 3.068322 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/micron/ddr/mt46v16m16.vhd | 2 | 60,967 | -----------------------------------------------------------------------------------------
--
-- File Name: MT46V16M16.VHD
-- Version: 3.1
-- Date: January 14th, 2002
-- Model: Behavioral
-- Simulator: NCDesktop - http://www.cadence.com
-- ModelSim PE - http://www.model.com
--
-- Dependencies: None
--
-- Email: [email protected]
-- Company: Micron Technology, Inc.
-- Part Number: MT46V16M16 (4 Mb x 16 x 4 Banks)
--
-- Description: Micron 256 Mb SDRAM DDR (Double Data Rate)
--
-- Limitation: Doesn't model internal refresh counter
--
-- Note:
--
-- Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY
-- WHATSOEVER AND MICRON SPECIFICALLY DISCLAIMS ANY
-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
-- A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
--
-- Copyright (c) 1998 Micron Semiconductor Products, Inc.
-- All rights researved
--
-- Rev Author Date Changes
-- --- ---------------------------- ---------- -------------------------------------
-- 2.1 SH 01/14/2002 - Fix Burst_counter
-- Micron Technology, Inc.
--
-- 2.0 SH 11/08/2001 - Second release
-- Micron Technology, Inc. - Rewrote and remove SHARED VARIABLE
-- 3.1 Craig Hanson cahanson 05/28/2003 - update all models to release version 3.1
-- @micron.com (no changes to this model)
-----------------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
LIBRARY WORK;
USE WORK.MTI_PKG.ALL;
use std.textio.all;
library grlib;
use grlib.stdlib.all;
library gaisler;
use gaisler.sim.all;
ENTITY MT46V16M16 IS
GENERIC ( -- Timing for -75Z CL2
tCK : TIME := 7.500 ns;
tCH : TIME := 3.375 ns; -- 0.45*tCK
tCL : TIME := 3.375 ns; -- 0.45*tCK
tDH : TIME := 0.500 ns;
tDS : TIME := 0.500 ns;
tIH : TIME := 0.900 ns;
tIS : TIME := 0.900 ns;
tMRD : TIME := 15.000 ns;
tRAS : TIME := 40.000 ns;
tRAP : TIME := 20.000 ns;
tRC : TIME := 65.000 ns;
tRFC : TIME := 75.000 ns;
tRCD : TIME := 20.000 ns;
tRP : TIME := 20.000 ns;
tRRD : TIME := 15.000 ns;
tWR : TIME := 15.000 ns;
addr_bits : INTEGER := 13;
data_bits : INTEGER := 16;
cols_bits : INTEGER := 9;
index : INTEGER := 0;
fname : string := "sdram.srec"; -- File to read from
bbits : INTEGER := 16
);
PORT (
Dq : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
Dqs : INOUT STD_LOGIC_VECTOR (1 DOWNTO 0) := "ZZ";
Addr : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
Ba : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
Clk : IN STD_LOGIC;
Clk_n : IN STD_LOGIC;
Cke : IN STD_LOGIC;
Cs_n : IN STD_LOGIC;
Ras_n : IN STD_LOGIC;
Cas_n : IN STD_LOGIC;
We_n : IN STD_LOGIC;
Dm : IN STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END MT46V16M16;
ARCHITECTURE behave OF MT46V16M16 IS
-- Array for Read pipeline
TYPE Array_Read_cmnd IS ARRAY (8 DOWNTO 0) OF STD_LOGIC;
TYPE Array_Read_bank IS ARRAY (8 DOWNTO 0) OF STD_LOGIC_VECTOR (1 DOWNTO 0);
TYPE Array_Read_cols IS ARRAY (8 DOWNTO 0) OF STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0);
-- Array for Write pipeline
TYPE Array_Write_cmnd IS ARRAY (2 DOWNTO 0) OF STD_LOGIC;
TYPE Array_Write_bank IS ARRAY (2 DOWNTO 0) OF STD_LOGIC_VECTOR (1 DOWNTO 0);
TYPE Array_Write_cols IS ARRAY (2 DOWNTO 0) OF STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0);
-- Array for Auto Precharge
TYPE Array_Read_precharge IS ARRAY (3 DOWNTO 0) OF STD_LOGIC;
TYPE Array_Write_precharge IS ARRAY (3 DOWNTO 0) OF STD_LOGIC;
TYPE Array_Count_precharge IS ARRAY (3 DOWNTO 0) OF INTEGER;
-- Array for Manual Precharge
TYPE Array_A10_precharge IS ARRAY (8 DOWNTO 0) OF STD_LOGIC;
TYPE Array_Bank_precharge IS ARRAY (8 DOWNTO 0) OF STD_LOGIC_VECTOR (1 DOWNTO 0);
TYPE Array_Cmnd_precharge IS ARRAY (8 DOWNTO 0) OF STD_LOGIC;
-- Array for Burst Terminate
TYPE Array_Cmnd_bst IS ARRAY (8 DOWNTO 0) OF STD_LOGIC;
-- Array for Memory Access
TYPE Array_ram_type IS ARRAY (2**cols_bits - 1 DOWNTO 0) OF STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0);
TYPE Array_ram_pntr IS ACCESS Array_ram_type;
TYPE Array_ram_stor IS ARRAY (2**addr_bits - 1 DOWNTO 0) OF Array_ram_pntr;
-- Data pair
SIGNAL Dq_pair : STD_LOGIC_VECTOR (2 * data_bits - 1 DOWNTO 0);
SIGNAL Dm_pair : STD_LOGIC_VECTOR (3 DOWNTO 0);
-- Mode Register
SIGNAL Mode_reg : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
-- Command Decode Variables
SIGNAL Active_enable, Aref_enable, Burst_term, Ext_mode_enable : STD_LOGIC := '0';
SIGNAL Mode_reg_enable, Prech_enable, Read_enable, Write_enable : STD_LOGIC := '0';
-- Burst Length Decode Variables
SIGNAL Burst_length_2, Burst_length_4, Burst_length_8, Burst_length_f : STD_LOGIC := '0';
-- Cas Latency Decode Variables
SIGNAL Cas_latency_15, Cas_latency_2, Cas_latency_25, Cas_latency_3, Cas_latency_4 : STD_LOGIC := '0';
-- Internal Control Signals
SIGNAL Cs_in, Ras_in, Cas_in, We_in : STD_LOGIC := '0';
-- System Clock
SIGNAL Sys_clk : STD_LOGIC := '0';
-- Dqs buffer
SIGNAL Dqs_out : STD_LOGIC_VECTOR (1 DOWNTO 0) := "ZZ";
BEGIN
-- Strip the strength
Cs_in <= To_X01 (Cs_n);
Ras_in <= To_X01 (Ras_n);
Cas_in <= To_X01 (Cas_n);
We_in <= To_X01 (We_n);
-- Commands Decode
Active_enable <= NOT(Cs_in) AND NOT(Ras_in) AND Cas_in AND We_in;
Aref_enable <= NOT(Cs_in) AND NOT(Ras_in) AND NOT(Cas_in) AND We_in;
Burst_term <= NOT(Cs_in) AND Ras_in AND Cas_in AND NOT(We_in);
Ext_mode_enable <= NOT(Cs_in) AND NOT(Ras_in) AND NOT(Cas_in) AND NOT(We_in) AND Ba(0) AND NOT(Ba(1));
Mode_reg_enable <= NOT(Cs_in) AND NOT(Ras_in) AND NOT(Cas_in) AND NOT(We_in) AND NOT(Ba(0)) AND NOT(Ba(1));
Prech_enable <= NOT(Cs_in) AND NOT(Ras_in) AND Cas_in AND NOT(We_in);
Read_enable <= NOT(Cs_in) AND Ras_in AND NOT(Cas_in) AND We_in;
Write_enable <= NOT(Cs_in) AND Ras_in AND NOT(Cas_in) AND NOT(We_in);
-- Burst Length Decode
Burst_length_2 <= NOT(Mode_reg(2)) AND NOT(Mode_reg(1)) AND Mode_reg(0);
Burst_length_4 <= NOT(Mode_reg(2)) AND Mode_reg(1) AND NOT(Mode_reg(0));
Burst_length_8 <= NOT(Mode_reg(2)) AND Mode_reg(1) AND Mode_reg(0);
Burst_length_f <= (Mode_reg(2)) AND Mode_reg(1) AND Mode_reg(0);
-- CAS Latency Decode
Cas_latency_15 <= Mode_reg(6) AND NOT(Mode_reg(5)) AND (Mode_reg(4));
Cas_latency_2 <= NOT(Mode_reg(6)) AND Mode_reg(5) AND NOT(Mode_reg(4));
Cas_latency_25 <= Mode_reg(6) AND Mode_reg(5) AND NOT(Mode_reg(4));
Cas_latency_3 <= NOT(Mode_reg(6)) AND Mode_reg(5) AND Mode_reg(4);
Cas_latency_4 <= (Mode_reg(6)) AND NOT(Mode_reg(5)) AND NOT(Mode_reg(4));
-- Dqs buffer
Dqs <= Dqs_out;
--
-- System Clock
--
int_clk : PROCESS (Clk, Clk_n)
VARIABLE ClkZ, CkeZ : STD_LOGIC := '0';
begin
IF Clk = '1' AND Clk_n = '0' THEN
ClkZ := '1';
CkeZ := Cke;
ELSIF Clk = '0' AND Clk_n = '1' THEN
ClkZ := '0';
END IF;
Sys_clk <= CkeZ AND ClkZ;
END PROCESS;
--
-- Main Process
--
state_register : PROCESS
-- Precharge Variables
VARIABLE Pc_b0, Pc_b1, Pc_b2, Pc_b3 : STD_LOGIC := '0';
-- Activate Variables
VARIABLE Act_b0, Act_b1, Act_b2, Act_b3 : STD_LOGIC := '1';
-- Data IO variables
VARIABLE Data_in_enable, Data_out_enable : STD_LOGIC := '0';
-- Internal address mux variables
VARIABLE Cols_brst : STD_LOGIC_VECTOR (2 DOWNTO 0);
VARIABLE Prev_bank : STD_LOGIC_VECTOR (1 DOWNTO 0) := "00";
VARIABLE Bank_addr : STD_LOGIC_VECTOR (1 DOWNTO 0) := "00";
VARIABLE Cols_addr : STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0);
VARIABLE Rows_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
VARIABLE B0_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
VARIABLE B1_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
VARIABLE B2_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
VARIABLE B3_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
-- DLL Reset variables
VARIABLE DLL_enable : STD_LOGIC := '0';
VARIABLE DLL_reset : STD_LOGIC := '0';
VARIABLE DLL_done : STD_LOGIC := '0';
VARIABLE DLL_count : INTEGER := 0;
-- Timing Check
VARIABLE MRD_chk : TIME := 0 ns;
VARIABLE RFC_chk : TIME := 0 ns;
VARIABLE RRD_chk : TIME := 0 ns;
VARIABLE RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3 : TIME := 0 ns;
VARIABLE RAP_chk0, RAP_chk1, RAP_chk2, RAP_chk3 : TIME := 0 ns;
VARIABLE RC_chk0, RC_chk1, RC_chk2, RC_chk3 : TIME := 0 ns;
VARIABLE RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3 : TIME := 0 ns;
VARIABLE RP_chk0, RP_chk1, RP_chk2, RP_chk3 : TIME := 0 ns;
VARIABLE WR_chk0, WR_chk1, WR_chk2, WR_chk3 : TIME := 0 ns;
-- Read pipeline variables
VARIABLE Read_cmnd : Array_Read_cmnd;
VARIABLE Read_bank : Array_Read_bank;
VARIABLE Read_cols : Array_Read_cols;
-- Write pipeline variables
VARIABLE Write_cmnd : Array_Write_cmnd;
VARIABLE Write_bank : Array_Write_bank;
VARIABLE Write_cols : Array_Write_cols;
-- Auto Precharge variables
VARIABLE Read_precharge : Array_Read_precharge := ('0' & '0' & '0' & '0');
VARIABLE Write_precharge : Array_Write_precharge := ('0' & '0' & '0' & '0');
VARIABLE Count_precharge : Array_Count_precharge := ( 0 & 0 & 0 & 0 );
-- Manual Precharge variables
VARIABLE A10_precharge : Array_A10_precharge;
VARIABLE Bank_precharge : Array_Bank_precharge;
VARIABLE Cmnd_precharge : Array_Cmnd_precharge;
-- Burst Terminate variable
VARIABLE Cmnd_bst : Array_Cmnd_bst;
-- Memory Banks
VARIABLE Bank0 : Array_ram_stor;
VARIABLE Bank1 : Array_ram_stor;
VARIABLE Bank2 : Array_ram_stor;
VARIABLE Bank3 : Array_ram_stor;
-- Burst Counter
VARIABLE Burst_counter : STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0);
-- Internal Dqs initialize
VARIABLE Dqs_int : STD_LOGIC := '0';
-- Data buffer for DM Mask
VARIABLE Data_buf : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
-- Load and Dumb variables
FILE file_load : TEXT open read_mode is fname; -- Data load
FILE file_dump : TEXT open write_mode is "dumpdata.txt"; -- Data dump
VARIABLE Bank_Load : std_logic_vector ( 1 DOWNTO 0);
VARIABLE rows_load : std_logic_vector (12 DOWNTO 0);
VARIABLE cols_load : std_logic_vector ( 8 DOWNTO 0);
VARIABLE data_load : std_logic_vector (15 DOWNTO 0);
VARIABLE i, j : INTEGER;
VARIABLE good_load : BOOLEAN;
VARIABLE l : LINE;
variable file_loaded : boolean := false;
variable dump : std_logic := '0';
variable ch : character;
variable rectype : std_logic_vector(3 downto 0);
variable recaddr : std_logic_vector(31 downto 0);
variable reclen : std_logic_vector(7 downto 0);
variable recdata : std_logic_vector(0 to 16*8-1);
--
-- Initialize empty rows
--
PROCEDURE Init_mem (Bank : STD_LOGIC_VECTOR; Row_index : INTEGER) IS
VARIABLE i, j : INTEGER := 0;
BEGIN
IF Bank = "00" THEN
IF Bank0 (Row_index) = NULL THEN -- Check to see if row empty
Bank0 (Row_index) := NEW Array_ram_type; -- Open new row for access
FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP -- Filled row with zeros
FOR j IN (data_bits - 1) DOWNTO 0 LOOP
Bank0 (Row_index) (i) (j) := '0';
END LOOP;
END LOOP;
END IF;
ELSIF Bank = "01" THEN
IF Bank1 (Row_index) = NULL THEN
Bank1 (Row_index) := NEW Array_ram_type;
FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP
FOR j IN (data_bits - 1) DOWNTO 0 LOOP
Bank1 (Row_index) (i) (j) := '0';
END LOOP;
END LOOP;
END IF;
ELSIF Bank = "10" THEN
IF Bank2 (Row_index) = NULL THEN
Bank2 (Row_index) := NEW Array_ram_type;
FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP
FOR j IN (data_bits - 1) DOWNTO 0 LOOP
Bank2 (Row_index) (i) (j) := '0';
END LOOP;
END LOOP;
END IF;
ELSIF Bank = "11" THEN
IF Bank3 (Row_index) = NULL THEN
Bank3 (Row_index) := NEW Array_ram_type;
FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP
FOR j IN (data_bits - 1) DOWNTO 0 LOOP
Bank3 (Row_index) (i) (j) := '0';
END LOOP;
END LOOP;
END IF;
END IF;
END;
--
-- Burst Counter
--
PROCEDURE Burst_decode IS
VARIABLE Cols_temp : STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- Advance burst counter
Burst_counter := Burst_counter + 1;
-- Burst Type
IF Mode_reg (3) = '0' THEN
Cols_temp := Cols_addr + 1;
ELSIF Mode_reg (3) = '1' THEN
Cols_temp (2) := Burst_counter (2) XOR Cols_brst (2);
Cols_temp (1) := Burst_counter (1) XOR Cols_brst (1);
Cols_temp (0) := Burst_counter (0) XOR Cols_brst (0);
END IF;
-- Burst Length
IF Burst_length_2 = '1' THEN
Cols_addr (0) := Cols_temp (0);
ELSIF Burst_length_4 = '1' THEN
Cols_addr (1 DOWNTO 0) := Cols_temp (1 DOWNTO 0);
ELSIF Burst_length_8 = '1' THEN
Cols_addr (2 DOWNTO 0) := Cols_temp (2 DOWNTO 0);
ELSE
Cols_addr := Cols_temp;
END IF;
-- Data counter
IF Burst_length_2 = '1' THEN
IF conv_integer(Burst_counter) >= 2 THEN
IF Data_in_enable = '1' THEN
Data_in_enable := '0';
ELSIF Data_out_enable = '1' THEN
Data_out_enable := '0';
END IF;
END IF;
ELSIF Burst_length_4 = '1' THEN
IF conv_integer(Burst_counter) >= 4 THEN
IF Data_in_enable = '1' THEN
Data_in_enable := '0';
ELSIF Data_out_enable = '1' THEN
Data_out_enable := '0';
END IF;
END IF;
ELSIF Burst_length_8 = '1' THEN
IF conv_integer(Burst_counter) >= 8 THEN
IF Data_in_enable = '1' THEN
Data_in_enable := '0';
ELSIF Data_out_enable = '1' THEN
Data_out_enable := '0';
END IF;
END IF;
END IF;
END;
BEGIN
WAIT ON Sys_clk;
--
-- Manual Precharge Pipeline
--
IF ((Sys_clk'EVENT AND Sys_clk = '0') OR (Sys_clk'EVENT AND Sys_clk = '1')) THEN
-- A10 Precharge Pipeline
A10_precharge(0) := A10_precharge(1);
A10_precharge(1) := A10_precharge(2);
A10_precharge(2) := A10_precharge(3);
A10_precharge(3) := A10_precharge(4);
A10_precharge(4) := A10_precharge(5);
A10_precharge(5) := A10_precharge(6);
A10_precharge(6) := A10_precharge(7);
A10_precharge(7) := A10_precharge(8);
A10_precharge(8) := '0';
-- Bank Precharge Pipeline
Bank_precharge(0) := Bank_precharge(1);
Bank_precharge(1) := Bank_precharge(2);
Bank_precharge(2) := Bank_precharge(3);
Bank_precharge(3) := Bank_precharge(4);
Bank_precharge(4) := Bank_precharge(5);
Bank_precharge(5) := Bank_precharge(6);
Bank_precharge(6) := Bank_precharge(7);
Bank_precharge(7) := Bank_precharge(8);
Bank_precharge(8) := "00";
-- Command Precharge Pipeline
Cmnd_precharge(0) := Cmnd_precharge(1);
Cmnd_precharge(1) := Cmnd_precharge(2);
Cmnd_precharge(2) := Cmnd_precharge(3);
Cmnd_precharge(3) := Cmnd_precharge(4);
Cmnd_precharge(4) := Cmnd_precharge(5);
Cmnd_precharge(5) := Cmnd_precharge(6);
Cmnd_precharge(6) := Cmnd_precharge(7);
Cmnd_precharge(7) := Cmnd_precharge(8);
Cmnd_precharge(8) := '0';
-- Terminate Read if same bank or all banks
IF ((Cmnd_precharge (0) = '1') AND
(Bank_precharge (0) = Bank_addr OR A10_precharge (0) = '1') AND
(Data_out_enable = '1')) THEN
Data_out_enable := '0';
END IF;
END IF;
--
-- Burst Terminate Pipeline
--
IF ((Sys_clk'EVENT AND Sys_clk = '0') OR (Sys_clk'EVENT AND Sys_clk = '1')) THEN
-- Burst Terminate pipeline
Cmnd_bst (0) := Cmnd_bst (1);
Cmnd_bst (1) := Cmnd_bst (2);
Cmnd_bst (2) := Cmnd_bst (3);
Cmnd_bst (3) := Cmnd_bst (4);
Cmnd_bst (4) := Cmnd_bst (5);
Cmnd_bst (5) := Cmnd_bst (6);
Cmnd_bst (6) := Cmnd_bst (7);
Cmnd_bst (7) := Cmnd_bst (8);
Cmnd_bst (8) := '0';
-- Terminate current Read
IF ((Cmnd_bst (0) = '1') AND (Data_out_enable = '1')) THEN
Data_out_enable := '0';
END IF;
END IF;
--
-- Dq and Dqs Drivers
--
IF ((Sys_clk'EVENT AND Sys_clk = '0') OR (Sys_clk'EVENT AND Sys_clk = '1')) THEN
-- Read Command Pipeline
Read_cmnd (0) := Read_cmnd (1);
Read_cmnd (1) := Read_cmnd (2);
Read_cmnd (2) := Read_cmnd (3);
Read_cmnd (3) := Read_cmnd (4);
Read_cmnd (4) := Read_cmnd (5);
Read_cmnd (5) := Read_cmnd (6);
Read_cmnd (6) := Read_cmnd (7);
Read_cmnd (7) := Read_cmnd (8);
Read_cmnd (8) := '0';
-- Read Bank Pipeline
Read_bank (0) := Read_bank (1);
Read_bank (1) := Read_bank (2);
Read_bank (2) := Read_bank (3);
Read_bank (3) := Read_bank (4);
Read_bank (4) := Read_bank (5);
Read_bank (5) := Read_bank (6);
Read_bank (6) := Read_bank (7);
Read_bank (7) := Read_bank (8);
Read_bank (8) := "00";
-- Read Column Pipeline
Read_cols (0) := Read_cols (1);
Read_cols (1) := Read_cols (2);
Read_cols (2) := Read_cols (3);
Read_cols (3) := Read_cols (4);
Read_cols (4) := Read_cols (5);
Read_cols (5) := Read_cols (6);
Read_cols (6) := Read_cols (7);
Read_cols (7) := Read_cols (8);
Read_cols (8) := (OTHERS => '0');
-- Initialize Read command
IF Read_cmnd (0) = '1' THEN
Data_out_enable := '1';
Bank_addr := Read_bank (0);
Cols_addr := Read_cols (0);
Cols_brst := Cols_addr (2 DOWNTO 0);
Burst_counter := (OTHERS => '0');
-- Row address mux
CASE Bank_addr IS
WHEN "00" => Rows_addr := B0_row_addr;
WHEN "01" => Rows_addr := B1_row_addr;
WHEN "10" => Rows_addr := B2_row_addr;
WHEN OTHERS => Rows_addr := B3_row_addr;
END CASE;
END IF;
-- Toggle Dqs during Read command
IF Data_out_enable = '1' THEN
Dqs_int := '0';
IF Dqs_out = "00" THEN
Dqs_out <= "11";
ELSIF Dqs_out = "11" THEN
Dqs_out <= "00";
ELSE
Dqs_out <= "00";
END IF;
ELSIF Data_out_enable = '0' AND Dqs_int = '0' THEN
Dqs_out <= "ZZ";
END IF;
-- Initialize Dqs for Read command
IF Read_cmnd (2) = '1' THEN
IF Data_out_enable = '0' THEN
Dqs_int := '1';
Dqs_out <= "00";
END IF;
END IF;
-- Read Latch
IF Data_out_enable = '1' THEN
-- Initialize Memory
Init_mem (Bank_addr, CONV_INTEGER(Rows_addr));
-- Output Data
CASE Bank_addr IS
WHEN "00" => Dq <= Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
WHEN "01" => Dq <= Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
WHEN "10" => Dq <= Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
WHEN OTHERS => Dq <= Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
END CASE;
-- Increase Burst Counter
Burst_decode;
ELSE
Dq <= (OTHERS => 'Z');
END IF;
END IF;
--
-- Write FIFO and DM Mask Logic
--
IF Sys_clk'EVENT AND Sys_clk = '1' THEN
-- Write command pipeline
Write_cmnd (0) := Write_cmnd (1);
Write_cmnd (1) := Write_cmnd (2);
Write_cmnd (2) := '0';
-- Write command pipeline
Write_bank (0) := Write_bank (1);
Write_bank (1) := Write_bank (2);
Write_bank (2) := "00";
-- Write column pipeline
Write_cols (0) := Write_cols (1);
Write_cols (1) := Write_cols (2);
Write_cols (2) := (OTHERS => '0');
-- Initialize Write command
IF Write_cmnd (0) = '1' THEN
Data_in_enable := '1';
Bank_addr := Write_bank (0);
Cols_addr := Write_cols (0);
Cols_brst := Cols_addr (2 DOWNTO 0);
Burst_counter := (OTHERS => '0');
-- Row address mux
CASE Bank_addr IS
WHEN "00" => Rows_addr := B0_row_addr;
WHEN "01" => Rows_addr := B1_row_addr;
WHEN "10" => Rows_addr := B2_row_addr;
WHEN OTHERS => Rows_addr := B3_row_addr;
END CASE;
END IF;
-- Write data
IF Data_in_enable = '1' THEN
-- Initialize memory
Init_mem (Bank_addr, CONV_INTEGER(Rows_addr));
-- Write first data
IF Dm_pair (1) = '0' OR Dm_pair (0) = '0' THEN
-- Data Buffer
CASE Bank_addr IS
WHEN "00" => Data_buf := Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
WHEN "01" => Data_buf := Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
WHEN "10" => Data_buf := Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
WHEN OTHERS => Data_buf := Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
END CASE;
-- Perform DM Mask
IF Dm_pair (0) = '0' THEN
Data_buf ( 7 DOWNTO 0) := Dq_pair ( 7 DOWNTO 0);
END IF;
IF Dm_pair (1) = '0' THEN
Data_buf (15 DOWNTO 8) := Dq_pair (15 DOWNTO 8);
END IF;
-- Write Data
CASE Bank_addr IS
WHEN "00" => Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
WHEN "01" => Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
WHEN "10" => Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
WHEN OTHERS => Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
END CASE;
END IF;
-- Increase Burst Counter
Burst_decode;
-- Write second data
IF Dm_pair (3) = '0' OR Dm_pair (2) = '0' THEN
-- Data Buffer
CASE Bank_addr IS
WHEN "00" => Data_buf := Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
WHEN "01" => Data_buf := Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
WHEN "10" => Data_buf := Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
WHEN OTHERS => Data_buf := Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
END CASE;
-- Perform DM Mask
IF Dm_pair (2) = '0' THEN
Data_buf ( 7 DOWNTO 0) := Dq_pair (23 DOWNTO 16);
END IF;
IF Dm_pair (3) = '0' THEN
Data_buf (15 DOWNTO 8) := Dq_pair (31 DOWNTO 24);
END IF;
-- Write Data
CASE Bank_addr IS
WHEN "00" => Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
WHEN "01" => Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
WHEN "10" => Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
WHEN OTHERS => Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
END CASE;
END IF;
-- Increase Burst Counter
Burst_decode;
-- tWR start and tWTR check
IF Dm_pair (3 DOWNTO 2) = "00" OR Dm_pair (1 DOWNTO 0) = "00" THEN
CASE Bank_addr IS
WHEN "00" => WR_chk0 := NOW;
WHEN "01" => WR_chk1 := NOW;
WHEN "10" => WR_chk2 := NOW;
WHEN OTHERS => WR_chk3 := NOW;
END CASE;
-- tWTR check
ASSERT (Read_enable = '0')
REPORT "tWTR violation during Read"
SEVERITY WARNING;
END IF;
END IF;
END IF;
--
-- Auto Precharge Calculation
--
IF Sys_clk'EVENT AND Sys_clk = '1' THEN
-- Precharge counter
IF Read_precharge (0) = '1' OR Write_precharge (0) = '1' THEN
Count_precharge (0) := Count_precharge (0) + 1;
END IF;
IF Read_precharge (1) = '1' OR Write_precharge (1) = '1' THEN
Count_precharge (1) := Count_precharge (1) + 1;
END IF;
IF Read_precharge (2) = '1' OR Write_precharge (2) = '1' THEN
Count_precharge (2) := Count_precharge (2) + 1;
END IF;
IF Read_precharge (3) = '1' OR Write_precharge (3) = '1' THEN
Count_precharge (3) := Count_precharge (3) + 1;
END IF;
-- Read with AutoPrecharge Calculation
-- The device start internal precharge when:
-- 1. Meet tRAS requirement
-- 2. BL/2 cycles after command
IF ((Read_precharge(0) = '1') AND (NOW - RAS_chk0 >= tRAS)) THEN
IF ((Burst_length_2 = '1' AND Count_precharge(0) >= 1) OR
(Burst_length_4 = '1' AND Count_precharge(0) >= 2) OR
(Burst_length_8 = '1' AND Count_precharge(0) >= 4)) THEN
Pc_b0 := '1';
Act_b0 := '0';
RP_chk0 := NOW;
Read_precharge(0) := '0';
END IF;
END IF;
IF ((Read_precharge(1) = '1') AND (NOW - RAS_chk1 >= tRAS)) THEN
IF ((Burst_length_2 = '1' AND Count_precharge(1) >= 1) OR
(Burst_length_4 = '1' AND Count_precharge(1) >= 2) OR
(Burst_length_8 = '1' AND Count_precharge(1) >= 4)) THEN
Pc_b1 := '1';
Act_b1 := '0';
RP_chk1 := NOW;
Read_precharge(1) := '0';
END IF;
END IF;
IF ((Read_precharge(2) = '1') AND (NOW - RAS_chk2 >= tRAS)) THEN
IF ((Burst_length_2 = '1' AND Count_precharge(2) >= 1) OR
(Burst_length_4 = '1' AND Count_precharge(2) >= 2) OR
(Burst_length_8 = '1' AND Count_precharge(2) >= 4)) THEN
Pc_b2 := '1';
Act_b2 := '0';
RP_chk2 := NOW;
Read_precharge(2) := '0';
END IF;
END IF;
IF ((Read_precharge(3) = '1') AND (NOW - RAS_chk3 >= tRAS)) THEN
IF ((Burst_length_2 = '1' AND Count_precharge(3) >= 1) OR
(Burst_length_4 = '1' AND Count_precharge(3) >= 2) OR
(Burst_length_8 = '1' AND Count_precharge(3) >= 4)) THEN
Pc_b3 := '1';
Act_b3 := '0';
RP_chk3 := NOW;
Read_precharge(3) := '0';
END IF;
END IF;
-- Write with AutoPrecharge Calculation
-- The device start internal precharge when:
-- 1. Meet tRAS requirement
-- 2. Two clock after last burst
-- Since tWR is time base, the model will compensate tRP
IF ((Write_precharge(0) = '1') AND (NOW - RAS_chk0 >= tRAS)) THEN
IF ((Burst_length_2 = '1' AND Count_precharge (0) >= 4) OR
(Burst_length_4 = '1' AND Count_precharge (0) >= 5) OR
(Burst_length_8 = '1' AND Count_precharge (0) >= 7)) THEN
Pc_b0 := '1';
Act_b0 := '0';
RP_chk0 := NOW - ((2 * tCK) - tWR);
Write_precharge(0) := '0';
END IF;
END IF;
IF ((Write_precharge(1) = '1') AND (NOW - RAS_chk1 >= tRAS)) THEN
IF ((Burst_length_2 = '1' AND Count_precharge (1) >= 4) OR
(Burst_length_4 = '1' AND Count_precharge (1) >= 5) OR
(Burst_length_8 = '1' AND Count_precharge (1) >= 7)) THEN
Pc_b1 := '1';
Act_b1 := '0';
RP_chk1 := NOW - ((2 * tCK) - tWR);
Write_precharge(1) := '0';
END IF;
END IF;
IF ((Write_precharge(2) = '1') AND (NOW - RAS_chk2 >= tRAS)) THEN
IF ((Burst_length_2 = '1' AND Count_precharge (2) >= 4) OR
(Burst_length_4 = '1' AND Count_precharge (2) >= 5) OR
(Burst_length_8 = '1' AND Count_precharge (2) >= 7)) THEN
Pc_b2 := '1';
Act_b2 := '0';
RP_chk2 := NOW - ((2 * tCK) - tWR);
Write_precharge(2) := '0';
END IF;
END IF;
IF ((Write_precharge(3) = '1') AND (NOW - RAS_chk3 >= tRAS)) THEN
IF ((Burst_length_2 = '1' AND Count_precharge (3) >= 4) OR
(Burst_length_4 = '1' AND Count_precharge (3) >= 5) OR
(Burst_length_8 = '1' AND Count_precharge (3) >= 7)) THEN
Pc_b3 := '1';
Act_b3 := '0';
RP_chk3 := NOW - ((2 * tCK) - tWR);
Write_precharge(3) := '0';
END IF;
END IF;
END IF;
--
-- DLL Counter
--
IF Sys_clk'EVENT AND Sys_clk = '1' THEN
IF (DLL_Reset = '1' AND DLL_done = '0') THEN
DLL_count := DLL_count + 1;
IF (DLL_count >= 200) THEN
DLL_done := '1';
END IF;
END IF;
END IF;
--
-- Control Logic
--
IF Sys_clk'EVENT AND Sys_clk = '1' THEN
-- Auto Refresh
IF Aref_enable = '1' THEN
-- Auto Refresh to Auto Refresh
ASSERT (NOW - RFC_chk >= tRFC)
REPORT "tRFC violation during Auto Refresh"
SEVERITY WARNING;
-- Precharge to Auto Refresh
ASSERT ((NOW - RP_chk0 >= tRP) AND (NOW - RP_chk1 >= tRP) AND
(NOW - RP_chk2 >= tRP) AND (NOW - RP_chk3 >= tRP))
REPORT "tRP violation during Auto Refresh"
SEVERITY WARNING;
-- Precharge to Auto Refresh
ASSERT (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1')
REPORT "All banks must be Precharge before Auto Refresh"
SEVERITY WARNING;
-- Record current tRFC time
RFC_chk := NOW;
END IF;
-- Extended Load Mode Register
IF Ext_mode_enable = '1' THEN
IF (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1') THEN
IF (Addr (0) = '0') THEN
DLL_enable := '1';
ELSE
DLL_enable := '0';
END IF;
END IF;
-- Precharge to EMR
ASSERT (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1')
REPORT "All bank must be Precharged before Extended Mode Register"
SEVERITY WARNING;
-- Precharge to EMR
ASSERT ((NOW - RP_chk0 >= tRP) AND (NOW - RP_chk1 >= tRP) AND
(NOW - RP_chk2 >= tRP) AND (NOW - RP_chk3 >= tRP))
REPORT "tRP violation during Extended Load Register"
SEVERITY WARNING;
-- LMR/EMR to EMR
ASSERT (NOW - MRD_chk >= tMRD)
REPORT "tMRD violation during Extended Mode Register"
SEVERITY WARNING;
-- Record current tMRD time
MRD_chk := NOW;
END IF;
-- Load Mode Register
IF Mode_reg_enable = '1' THEN
-- Register mode
Mode_reg <= Addr;
-- DLL Reset
IF (DLL_enable = '1' AND Addr (8) = '1') THEN
DLL_reset := '1';
DLL_done := '0';
DLL_count := 0;
ELSIF (DLL_enable = '1' AND DLL_reset = '0' AND Addr (8) = '0') THEN
ASSERT (FALSE)
REPORT "DLL is ENABLE: DLL RESET is require"
SEVERITY WARNING;
ELSIF (DLL_enable = '0' AND Addr (8) = '1') THEN
ASSERT (FALSE)
REPORT "DLL is DISABLE: DLL RESET will be ignored"
SEVERITY WARNING;
END IF;
-- Precharge to LMR
ASSERT (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1')
REPORT "All bank must be Precharged before Load Mode Register"
SEVERITY WARNING;
-- Precharge to EMR
ASSERT ((NOW - RP_chk0 >= tRP) AND (NOW - RP_chk1 >= tRP) AND
(NOW - RP_chk2 >= tRP) AND (NOW - RP_chk3 >= tRP))
REPORT "tRP violation during Load Mode Register"
SEVERITY WARNING;
-- LMR/ELMR to LMR
ASSERT (NOW - MRD_chk >= tMRD)
REPORT "tMRD violation during Load Mode Register"
SEVERITY WARNING;
-- Check for invalid Burst Length
ASSERT ((Addr (2 DOWNTO 0) = "001") OR -- BL = 2
(Addr (2 DOWNTO 0) = "010") OR -- BL = 4
(Addr (2 DOWNTO 0) = "011")) -- BL = 8
REPORT "Invalid Burst Length during Load Mode Register"
SEVERITY WARNING;
-- Check for invalid CAS Latency
ASSERT ((Addr (6 DOWNTO 4) = "010") OR -- CL = 2.0
(Addr (6 DOWNTO 4) = "110")) -- CL = 2.5
REPORT "Invalid CAS Latency during Load Mode Register"
SEVERITY WARNING;
-- Record current tMRD time
MRD_chk := NOW;
END IF;
-- Active Block (latch Bank and Row Address)
IF Active_enable = '1' THEN
-- Activate an OPEN bank can corrupt data
ASSERT ((Ba = "00" AND Act_b0 = '0') OR
(Ba = "01" AND Act_b1 = '0') OR
(Ba = "10" AND Act_b2 = '0') OR
(Ba = "11" AND Act_b3 = '0'))
REPORT "Bank is already activated - data can be corrupted"
SEVERITY WARNING;
-- Activate Bank 0
IF Ba = "00" AND Pc_b0 = '1' THEN
-- Activate to Activate (same bank)
ASSERT (NOW - RC_chk0 >= tRC)
REPORT "tRC violation during Activate Bank 0"
SEVERITY WARNING;
-- Precharge to Active
ASSERT (NOW - RP_chk0 >= tRP)
REPORT "tRP violation during Activate Bank 0"
SEVERITY WARNING;
-- Record Variables for checking violation
Act_b0 := '1';
Pc_b0 := '0';
B0_row_addr := Addr;
RC_chk0 := NOW;
RCD_chk0 := NOW;
RAS_chk0 := NOW;
RAP_chk0 := NOW;
END IF;
-- Activate Bank 1
IF Ba = "01" AND Pc_b1 = '1' THEN
-- Activate to Activate (same bank)
ASSERT (NOW - RC_chk1 >= tRC)
REPORT "tRC violation during Activate Bank 1"
SEVERITY WARNING;
-- Precharge to Active
ASSERT (NOW - RP_chk1 >= tRP)
REPORT "tRP violation during Activate Bank 1"
SEVERITY WARNING;
-- Record Variables for checking violation
Act_b1 := '1';
Pc_b1 := '0';
B1_row_addr := Addr;
RC_chk1 := NOW;
RCD_chk1 := NOW;
RAS_chk1 := NOW;
RAP_chk1 := NOW;
END IF;
-- Activate Bank 2
IF Ba = "10" AND Pc_b2 = '1' THEN
-- Activate to Activate (same bank)
ASSERT (NOW - RC_chk2 >= tRC)
REPORT "tRC violation during Activate Bank 2"
SEVERITY WARNING;
-- Precharge to Active
ASSERT (NOW - RP_chk2 >= tRP)
REPORT "tRP violation during Activate Bank 2"
SEVERITY WARNING;
-- Record Variables for checking violation
Act_b2 := '1';
Pc_b2 := '0';
B2_row_addr := Addr;
RC_chk2 := NOW;
RCD_chk2 := NOW;
RAS_chk2 := NOW;
RAP_chk2 := NOW;
END IF;
-- Activate Bank 3
IF Ba = "11" AND Pc_b3 = '1' THEN
-- Activate to Activate (same bank)
ASSERT (NOW - RC_chk3 >= tRC)
REPORT "tRC violation during Activate Bank 3"
SEVERITY WARNING;
-- Precharge to Active
ASSERT (NOW - RP_chk3 >= tRP)
REPORT "tRP violation during Activate Bank 3"
SEVERITY WARNING;
-- Record Variables for checking violation
Act_b3 := '1';
Pc_b3 := '0';
B3_row_addr := Addr;
RC_chk3 := NOW;
RCD_chk3 := NOW;
RAS_chk3 := NOW;
RAP_chk3 := NOW;
END IF;
-- Activate Bank A to Activate Bank B
IF (Prev_bank /= Ba) THEN
ASSERT (NOW - RRD_chk >= tRRD)
REPORT "tRRD violation during Activate"
SEVERITY WARNING;
END IF;
-- AutoRefresh to Activate
ASSERT (NOW - RFC_chk >= tRFC)
REPORT "tRFC violation during Activate"
SEVERITY WARNING;
-- Record Variables for Checking Violation
RRD_chk := NOW;
Prev_bank := Ba;
END IF;
-- Precharge Block - Consider NOP if bank already precharged or in process of precharging
IF Prech_enable = '1' THEN
-- EMR or LMR to Precharge
ASSERT (NOW - MRD_chk >= tMRD)
REPORT "tMRD violation during Precharge"
SEVERITY WARNING;
-- Precharge Bank 0
IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "00")) AND Act_b0 = '1') THEN
Act_b0 := '0';
Pc_b0 := '1';
RP_chk0 := NOW;
-- Activate to Precharge bank 0
ASSERT (NOW - RAS_chk0 >= tRAS)
REPORT "tRAS violation during Precharge"
SEVERITY WARNING;
-- tWR violation check for Write
ASSERT (NOW - WR_chk0 >= tWR)
REPORT "tWR violation during Precharge"
SEVERITY WARNING;
END IF;
-- Precharge Bank 1
IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "01")) AND Act_b1 = '1') THEN
Act_b1 := '0';
Pc_b1 := '1';
RP_chk1 := NOW;
-- Activate to Precharge
ASSERT (NOW - RAS_chk1 >= tRAS)
REPORT "tRAS violation during Precharge"
SEVERITY WARNING;
-- tWR violation check for Write
ASSERT (NOW - WR_chk1 >= tWR)
REPORT "tWR violation during Precharge"
SEVERITY WARNING;
END IF;
-- Precharge Bank 2
IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "10")) AND Act_b2 = '1') THEN
Act_b2 := '0';
Pc_b2 := '1';
RP_chk2 := NOW;
-- Activate to Precharge
ASSERT (NOW - RAS_chk2 >= tRAS)
REPORT "tRAS violation during Precharge"
SEVERITY WARNING;
-- tWR violation check for Write
ASSERT (NOW - WR_chk2 >= tWR)
REPORT "tWR violation during Precharge"
SEVERITY WARNING;
END IF;
-- Precharge Bank 3
IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "11")) AND Act_b3 = '1') THEN
Act_b3 := '0';
Pc_b3 := '1';
RP_chk3 := NOW;
-- Activate to Precharge
ASSERT (NOW - RAS_chk3 >= tRAS)
REPORT "tRAS violation during Precharge"
SEVERITY WARNING;
-- tWR violation check for Write
ASSERT (NOW - WR_chk3 >= tWR)
REPORT "tWR violation during Precharge"
SEVERITY WARNING;
END IF;
-- Pipeline for READ
IF CAS_latency_15 = '1' THEN
A10_precharge (3) := Addr(10);
Bank_precharge (3) := Ba;
Cmnd_precharge (3) := '1';
ELSIF CAS_latency_2 = '1' THEN
A10_precharge (4) := Addr(10);
Bank_precharge (4) := Ba;
Cmnd_precharge (4) := '1';
ELSIF CAS_latency_25 = '1' THEN
A10_precharge (5) := Addr(10);
Bank_precharge (5) := Ba;
Cmnd_precharge (5) := '1';
ELSIF CAS_latency_3 = '1' THEN
A10_precharge (6) := Addr(10);
Bank_precharge (6) := Ba;
Cmnd_precharge (6) := '1';
ELSIF CAS_latency_4 = '1' THEN
A10_precharge (8) := Addr(10);
Bank_precharge (8) := Ba;
Cmnd_precharge (8) := '1';
END IF;
END IF;
-- Burst Terminate
IF Burst_term = '1' THEN
-- Pipeline for Read
IF CAS_latency_15 = '1' THEN
Cmnd_bst (3) := '1';
ELSIF CAS_latency_2 = '1' THEN
Cmnd_bst (4) := '1';
ELSIF CAS_latency_25 = '1' THEN
Cmnd_bst (5) := '1';
ELSIF CAS_latency_3 = '1' THEN
Cmnd_bst (6) := '1';
ELSIF CAS_latency_4 = '1' THEN
Cmnd_bst (8) := '1';
END IF;
-- Terminate Write
ASSERT (Data_in_enable = '0')
REPORT "It's illegal to Burst Terminate a Write"
SEVERITY WARNING;
-- Terminate Read with Auto Precharge
ASSERT (Read_precharge (0) = '0' AND Read_precharge (1) = '0' AND
Read_precharge (2) = '0' AND Read_precharge (3) = '0')
REPORT "It's illegal to Burst Terminate a Read with Auto Precharge"
SEVERITY WARNING;
END IF;
-- Read Command
IF Read_enable = '1' THEN
-- CAS Latency Pipeline
IF Cas_latency_15 = '1' THEN
Read_cmnd (3) := '1';
Read_bank (3) := Ba;
Read_cols (3) := Addr (8 DOWNTO 0);
ELSIF Cas_latency_2 = '1' THEN
Read_cmnd (4) := '1';
Read_bank (4) := Ba;
Read_cols (4) := Addr (8 DOWNTO 0);
ELSIF Cas_latency_25 = '1' THEN
Read_cmnd (5) := '1';
Read_bank (5) := Ba;
Read_cols (5) := Addr (8 DOWNTO 0);
ELSIF Cas_latency_3 = '1' THEN
Read_cmnd (6) := '1';
Read_bank (6) := Ba;
Read_cols (6) := Addr (8 DOWNTO 0);
ELSIF Cas_latency_4 = '1' THEN
Read_cmnd (8) := '1';
Read_bank (8) := Ba;
Read_cols (8) := Addr (8 DOWNTO 0);
END IF;
-- Write to Read: Terminate Write Immediately
IF Data_in_enable = '1' THEN
Data_in_enable := '0';
END IF;
-- Interrupting a Read with Auto Precharge (same bank only)
ASSERT (Read_precharge(CONV_INTEGER(Ba)) = '0')
REPORT "It's illegal to interrupt a Read with Auto Precharge"
SEVERITY WARNING;
-- Activate to Read
ASSERT ((Ba = "00" AND Act_b0 = '1') OR
(Ba = "01" AND Act_b1 = '1') OR
(Ba = "10" AND Act_b2 = '1') OR
(Ba = "11" AND Act_b3 = '1'))
REPORT "Bank is not Activated for Read"
SEVERITY WARNING;
-- Activate to Read without Auto Precharge
IF Addr (10) = '0' THEN
ASSERT ((Ba = "00" AND NOW - RCD_chk0 >= tRCD) OR
(Ba = "01" AND NOW - RCD_chk1 >= tRCD) OR
(Ba = "10" AND NOW - RCD_chk2 >= tRCD) OR
(Ba = "11" AND NOW - RCD_chk3 >= tRCD))
REPORT "tRCD violation during Read"
SEVERITY WARNING;
END IF;
-- Activate to Read with Auto Precharge
IF Addr (10) = '1' THEN
ASSERT ((Ba = "00" AND NOW - RAP_chk0 >= tRAP) OR
(Ba = "01" AND NOW - RAP_chk1 >= tRAP) OR
(Ba = "10" AND NOW - RAP_chk2 >= tRAP) OR
(Ba = "11" AND NOW - RAP_chk3 >= tRAP))
REPORT "tRAP violation during Read"
SEVERITY WARNING;
END IF;
-- Auto precharge
IF Addr (10) = '1' THEN
Read_precharge (Conv_INTEGER(Ba)) := '1';
Count_precharge (Conv_INTEGER(Ba)) := 0;
END IF;
-- DLL Check
IF (DLL_reset = '1') THEN
ASSERT (DLL_done = '1')
REPORT "DLL RESET not complete"
SEVERITY WARNING;
END IF;
END IF;
-- Write Command
IF Write_enable = '1' THEN
-- Pipeline for Write
Write_cmnd (2) := '1';
Write_bank (2) := Ba;
Write_cols (2) := Addr (8 DOWNTO 0);
-- Interrupting a Write with Auto Precharge (same bank only)
ASSERT (Write_precharge(CONV_INTEGER(Ba)) = '0')
REPORT "It's illegal to interrupt a Write with Auto Precharge"
SEVERITY WARNING;
-- Activate to Write
ASSERT ((Ba = "00" AND Act_b0 = '1') OR
(Ba = "01" AND Act_b1 = '1') OR
(Ba = "10" AND Act_b2 = '1') OR
(Ba = "11" AND Act_b3 = '1'))
REPORT "Bank is not Activated for Write"
SEVERITY WARNING;
-- Activate to Write
ASSERT ((Ba = "00" AND NOW - RCD_chk0 >= tRCD) OR
(Ba = "01" AND NOW - RCD_chk1 >= tRCD) OR
(Ba = "10" AND NOW - RCD_chk2 >= tRCD) OR
(Ba = "11" AND NOW - RCD_chk3 >= tRCD))
REPORT "tRCD violation during Write"
SEVERITY WARNING;
-- Auto precharge
IF Addr (10) = '1' THEN
Write_precharge (Conv_INTEGER(Ba)) := '1';
Count_precharge (Conv_INTEGER(Ba)) := 0;
END IF;
END IF;
END IF;
IF not file_loaded THEN --'
file_loaded := true;
WHILE NOT endfile(file_load) LOOP
readline(file_load, l);
read(l, ch);
if (ch /= 'S') or (ch /= 's') then
hexread(l, rectype);
hexread(l, reclen);
recaddr := (others => '0');
case rectype is
when "0001" =>
hexread(l, recaddr(15 downto 0));
when "0010" =>
hexread(l, recaddr(23 downto 0));
when "0011" =>
hexread(l, recaddr);
when "0111" =>
hexread(l, recaddr);
-- if (index = 0) then print("Start address : " & tost(recaddr)); end if;
next;
when others => next;
end case;
case bbits is
when 64 => -- 64-bit bank with four 16-bit DDRs
recaddr(31 downto 27) := (others => '0');
hexread(l, recdata);
Bank_Load := recaddr(26 downto 25);
Rows_Load := recaddr(24 downto 12);
Cols_Load := recaddr(11 downto 3);
Init_mem (Bank_Load, To_Integer(Rows_Load));
IF Bank_Load = "00" THEN
for i in 0 to 1 loop
Bank0 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := (recdata(i*64+index*16 to i*64+index*16+15));
end loop;
ELSIF Bank_Load = "01" THEN
for i in 0 to 3 loop
Bank1 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := (recdata(i*64+index*16 to i*64+index*16+15));
end loop;
ELSIF Bank_Load = "10" THEN
for i in 0 to 3 loop
Bank2 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := (recdata(i*64+index*16 to i*64+index*16+15));
end loop;
ELSIF Bank_Load = "11" THEN
for i in 0 to 3 loop
Bank3 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := (recdata(i*64+index*16 to i*64+index*16+15));
end loop;
END IF;
when 32 => -- 32-bit bank with two 16-bit DDRs
recaddr(31 downto 26) := (others => '0');
hexread(l, recdata);
Bank_Load := recaddr(25 downto 24);
Rows_Load := recaddr(23 downto 11);
Cols_Load := recaddr(10 downto 2);
Init_mem (Bank_Load, To_Integer(Rows_Load));
IF Bank_Load = "00" THEN
for i in 0 to 3 loop
Bank0 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := (recdata(i*32+index*16 to i*32+index*16+15));
end loop;
ELSIF Bank_Load = "01" THEN
for i in 0 to 3 loop
Bank1 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := (recdata(i*32+index*16 to i*32+index*16+15));
end loop;
ELSIF Bank_Load = "10" THEN
for i in 0 to 3 loop
Bank2 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := (recdata(i*32+index*16 to i*32+index*16+15));
end loop;
ELSIF Bank_Load = "11" THEN
for i in 0 to 3 loop
Bank3 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := (recdata(i*32+index*16 to i*32+index*16+15));
end loop;
END IF;
when others => -- 16-bit bank with one 16-bit DDR
hexread(l, recdata);
recaddr(31 downto 25) := (others => '0');
Bank_Load := recaddr(24 downto 23);
Rows_Load := recaddr(22 downto 10);
Cols_Load := recaddr(9 downto 1);
Init_mem (Bank_Load, To_Integer(Rows_Load));
IF Bank_Load = "00" THEN
for i in 0 to 3 loop
Bank0 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := (recdata(i*16 to i*16+15));
Bank0 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i+4) := (recdata((i+4)*16 to (i+4)*16+15));
end loop;
ELSIF Bank_Load = "01" THEN
for i in 0 to 3 loop
Bank1 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := (recdata(i*16 to i*16+15));
Bank1 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i+4) := (recdata((i+4)*16 to (i+4)*16+15));
end loop;
ELSIF Bank_Load = "10" THEN
for i in 0 to 3 loop
Bank2 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := (recdata(i*16 to i*16+15));
Bank2 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i+4) := (recdata((i+4)*16 to (i+4)*16+15));
end loop;
ELSIF Bank_Load = "11" THEN
for i in 0 to 3 loop
Bank3 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := (recdata(i*16 to i*16+15));
Bank3 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i+4) := (recdata((i+4)*16 to (i+4)*16+15));
end loop;
END IF;
END case;
END IF;
END LOOP;
END IF;
END PROCESS;
--
-- Dqs Receiver
--
dqs_rcvrs : PROCESS
VARIABLE Dm_temp : STD_LOGIC_VECTOR (1 DOWNTO 0);
VARIABLE Dq_temp : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0);
BEGIN
WAIT ON Dqs;
-- Latch data at posedge Dqs
IF Dqs'EVENT AND Dqs (1) = '1' AND Dqs (0) = '1' THEN
Dq_temp := Dq;
Dm_temp := Dm;
END IF;
-- Latch data at negedge Dqs
IF Dqs'EVENT AND Dqs (1) = '0' AND Dqs (0) = '0' THEN
Dq_pair <= (Dq & Dq_temp);
Dm_pair <= (Dm & Dm_temp);
END IF;
END PROCESS;
--
-- Setup timing checks
--
Setup_check : PROCESS
BEGIN
WAIT ON Sys_clk;
IF Sys_clk'EVENT AND Sys_clk = '1' THEN
ASSERT(Cke'LAST_EVENT >= tIS)
REPORT "CKE Setup time violation -- tIS"
SEVERITY WARNING;
ASSERT(Cs_n'LAST_EVENT >= tIS)
REPORT "CS# Setup time violation -- tIS"
SEVERITY WARNING;
ASSERT(Cas_n'LAST_EVENT >= tIS)
REPORT "CAS# Setup time violation -- tIS"
SEVERITY WARNING;
ASSERT(Ras_n'LAST_EVENT >= tIS)
REPORT "RAS# Setup time violation -- tIS"
SEVERITY WARNING;
ASSERT(We_n'LAST_EVENT >= tIS)
REPORT "WE# Setup time violation -- tIS"
SEVERITY WARNING;
ASSERT(Addr'LAST_EVENT >= tIS)
REPORT "ADDR Setup time violation -- tIS"
SEVERITY WARNING;
ASSERT(Ba'LAST_EVENT >= tIS)
REPORT "BA Setup time violation -- tIS"
SEVERITY WARNING;
END IF;
END PROCESS;
--
-- Hold timing checks
--
Hold_check : PROCESS
BEGIN
WAIT ON Sys_clk'DELAYED (tIH);
IF Sys_clk'DELAYED (tIH) = '1' THEN
ASSERT(Cke'LAST_EVENT >= tIH)
REPORT "CKE Hold time violation -- tIH"
SEVERITY WARNING;
ASSERT(Cs_n'LAST_EVENT >= tIH)
REPORT "CS# Hold time violation -- tIH"
SEVERITY WARNING;
ASSERT(Cas_n'LAST_EVENT >= tIH)
REPORT "CAS# Hold time violation -- tIH"
SEVERITY WARNING;
ASSERT(Ras_n'LAST_EVENT >= tIH)
REPORT "RAS# Hold time violation -- tIH"
SEVERITY WARNING;
ASSERT(We_n'LAST_EVENT >= tIH)
REPORT "WE# Hold time violation -- tIH"
SEVERITY WARNING;
ASSERT(Addr'LAST_EVENT >= tIH)
REPORT "ADDR Hold time violation -- tIH"
SEVERITY WARNING;
ASSERT(Ba'LAST_EVENT >= tIH)
REPORT "BA Hold time violation -- tIH"
SEVERITY WARNING;
END IF;
END PROCESS;
END behave;
| mit | 3c8a1b17b5fe3a3c43e1e2e78929012e | 0.445323 | 4.030876 | false | false | false | false |
michaelfivez/ascon_hardware_implementation | ascon12864_unrolled6/Kernel/FullDiffLayer.vhd | 1 | 2,097 | -------------------------------------------------------------------------------
--! @project Unrolled (6) hardware implementation of Asconv1286
--! @author Michael Fivez
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is an hardware implementation made for my graduation thesis
--! at the KULeuven, in the COSIC department (year 2015-2016)
--! The thesis is titled 'Energy efficient hardware implementations of CAESAR submissions',
--! and can be found on the COSIC website (www.esat.kuleuven.be/cosic/publications)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity FullDiffusionLayer is
port(
X0In : in std_logic_vector(63 downto 0);
X1In : in std_logic_vector(63 downto 0);
X2In : in std_logic_vector(63 downto 0);
X3In : in std_logic_vector(63 downto 0);
X4In : in std_logic_vector(63 downto 0);
X0Out : out std_logic_vector(63 downto 0);
X1Out : out std_logic_vector(63 downto 0);
X2Out : out std_logic_vector(63 downto 0);
X3Out : out std_logic_vector(63 downto 0);
X4Out : out std_logic_vector(63 downto 0));
end entity FullDiffusionLayer;
architecture structural of FullDiffusionLayer is
begin
Diff0: entity work.DiffusionLayer
generic map(SHIFT1 => 19,SHIFT2 => 28)
port map(X0In,X0Out);
Diff1: entity work.DiffusionLayer
generic map(SHIFT1 => 61,SHIFT2 => 39)
port map(X1In,X1Out);
Diff2: entity work.DiffusionLayer
generic map(SHIFT1 => 1,SHIFT2 => 6)
port map(X2In,X2Out);
Diff3: entity work.DiffusionLayer
generic map(SHIFT1 => 10,SHIFT2 => 17)
port map(X3In,X3Out);
Diff4: entity work.DiffusionLayer
generic map(SHIFT1 => 7,SHIFT2 => 41)
port map(X4In,X4Out);
end architecture structural;
| gpl-3.0 | 0583bdc0ff208f6c220040502a6f900e | 0.627563 | 3.333863 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/techmap/maps/allddr.vhd | 2 | 14,594 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: libddr
-- File: libddr.vhd
-- Author: David Lindh, Jiri Gaisler - Gaisler Research
-- Description: DDR input/output registers
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
package allddr is
component unisim_iddr_reg is
generic ( tech : integer := virtex4);
port(
Q1 : out std_ulogic;
Q2 : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end component;
component gen_iddr_reg
port (
Q1 : out std_ulogic;
Q2 : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component ec_oddr_reg
port (
Q : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component unisim_oddr_reg
generic ( tech : integer := virtex4);
port (
Q : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component gen_oddr_reg
port (
Q : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component spartan3e_ddr_phy
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ;
clk_div : integer := 2; rskew : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- DDR state clock
clkread : out std_ulogic; -- DDR read clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (13 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0)
);
end component;
component virtex4_ddr_phy
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ;
clk_div : integer := 2; rskew : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (13 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0)
);
end component;
component virtex2_ddr_phy
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ;
clk_div : integer := 2; rskew : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (13 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0)
);
end component;
component stratixii_ddr_phy
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ;
clk_div : integer := 2);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (13 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0)
);
end component;
component cycloneiii_ddr_phy
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ;
clk_div : integer := 2);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (13 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0)
);
end component;
component virtex5_ddr2_phy
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ; clk_div : integer := 2;
ddelayb0 : integer := 0; ddelayb1 : integer := 0; ddelayb2 : integer := 0;
ddelayb3 : integer := 0; ddelayb4 : integer := 0; ddelayb5 : integer := 0;
ddelayb6 : integer := 0; ddelayb7 : integer := 0;
numidelctrl : integer := 4; norefclk : integer := 0; tech : integer := virtex5);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkref200 : in std_logic; -- input 200MHz clock
clkout : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqsn : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqsn
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(1 downto 0);
addr : in std_logic_vector (13 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0);
cal_en : in std_logic_vector(dbits/8-1 downto 0);
cal_inc : in std_logic_vector(dbits/8-1 downto 0);
cal_rst : in std_logic;
odt : in std_logic_vector(1 downto 0)
);
end component;
end;
| mit | 4be9f08a74e114fee276d71adadd0d0d | 0.554817 | 3.242391 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/techmap/axcelerator/usbhc_axceleratorpkg.vhd | 2 | 30,540 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: usbhc_axceleratorpkg
-- File: usbhc_axceleratorpkg.vhd
-- Author: Jonas Ekergarn - Gaisler Research
-- Description: Component declartions for the tech wrapper for axcelerator
-- usbhc netlists
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package usbhc_axceleratorpkg is
component usbhc_axcelerator_comb0
port (
clk : in std_ulogic;
uclk : in std_ulogic;
rst : in std_ulogic;
ursti : in std_ulogic;
-- EHC apb_slv_in_type unwrapped
ehc_apbsi_psel : in std_ulogic;
ehc_apbsi_penable : in std_ulogic;
ehc_apbsi_paddr : in std_logic_vector(31 downto 0);
ehc_apbsi_pwrite : in std_ulogic;
ehc_apbsi_pwdata : in std_logic_vector(31 downto 0);
ehc_apbsi_testen : in std_ulogic;
ehc_apbsi_testrst : in std_ulogic;
ehc_apbsi_scanen : in std_ulogic;
-- EHC apb_slv_out_type unwrapped
ehc_apbso_prdata : out std_logic_vector(31 downto 0);
ehc_apbso_pirq : out std_ulogic;
-- EHC/UHC ahb_mst_in_type unwrapped
ahbmi_hgrant : in std_logic_vector(1*1 downto 0);
ahbmi_hready : in std_ulogic;
ahbmi_hresp : in std_logic_vector(1 downto 0);
ahbmi_hrdata : in std_logic_vector(31 downto 0);
ahbmi_hcache : in std_ulogic;
ahbmi_testen : in std_ulogic;
ahbmi_testrst : in std_ulogic;
ahbmi_scanen : in std_ulogic;
-- UHC ahb_slv_in_type unwrapped
uhc_ahbsi_hsel : in std_logic_vector(1*1 downto 1*1);
uhc_ahbsi_haddr : in std_logic_vector(31 downto 0);
uhc_ahbsi_hwrite : in std_ulogic;
uhc_ahbsi_htrans : in std_logic_vector(1 downto 0);
uhc_ahbsi_hsize : in std_logic_vector(2 downto 0);
uhc_ahbsi_hwdata : in std_logic_vector(31 downto 0);
uhc_ahbsi_hready : in std_ulogic;
uhc_ahbsi_testen : in std_ulogic;
uhc_ahbsi_testrst : in std_ulogic;
uhc_ahbsi_scanen : in std_ulogic;
-- EHC ahb_mst_out_type_unwrapped
ehc_ahbmo_hbusreq : out std_ulogic;
ehc_ahbmo_hlock : out std_ulogic;
ehc_ahbmo_htrans : out std_logic_vector(1 downto 0);
ehc_ahbmo_haddr : out std_logic_vector(31 downto 0);
ehc_ahbmo_hwrite : out std_ulogic;
ehc_ahbmo_hsize : out std_logic_vector(2 downto 0);
ehc_ahbmo_hburst : out std_logic_vector(2 downto 0);
ehc_ahbmo_hprot : out std_logic_vector(3 downto 0);
ehc_ahbmo_hwdata : out std_logic_vector(31 downto 0);
-- UHC ahb_mst_out_vector_type unwrapped
uhc_ahbmo_hbusreq : out std_logic_vector(1*1 downto 1*1);
uhc_ahbmo_hlock : out std_logic_vector(1*1 downto 1*1);
uhc_ahbmo_htrans : out std_logic_vector((1*2)*1 downto 1*1);
uhc_ahbmo_haddr : out std_logic_vector((1*32)*1 downto 1*1);
uhc_ahbmo_hwrite : out std_logic_vector(1*1 downto 1*1);
uhc_ahbmo_hsize : out std_logic_vector((1*3)*1 downto 1*1);
uhc_ahbmo_hburst : out std_logic_vector((1*3)*1 downto 1*1);
uhc_ahbmo_hprot : out std_logic_vector((1*4)*1 downto 1*1);
uhc_ahbmo_hwdata : out std_logic_vector((1*32)*1 downto 1*1);
-- UHC ahb_slv_out_vector_type unwrapped
uhc_ahbso_hready : out std_logic_vector(1*1 downto 1*1);
uhc_ahbso_hresp : out std_logic_vector((1*2)*1 downto 1*1);
uhc_ahbso_hrdata : out std_logic_vector((1*32)*1 downto 1*1);
uhc_ahbso_hsplit : out std_logic_vector((1*16)*1 downto 1*1);
uhc_ahbso_hcache : out std_logic_vector(1*1 downto 1*1);
uhc_ahbso_hirq : out std_logic_vector(1*1 downto 1*1);
-- usbhc_out_type_vector unwrapped
xcvrsel : out std_logic_vector(((1*2)-1) downto 0);
termsel : out std_logic_vector((1-1) downto 0);
suspendm : out std_logic_vector((1-1) downto 0);
opmode : out std_logic_vector(((1*2)-1) downto 0);
txvalid : out std_logic_vector((1-1) downto 0);
drvvbus : out std_logic_vector((1-1) downto 0);
dataho : out std_logic_vector(((1*8)-1) downto 0);
validho : out std_logic_vector((1-1) downto 0);
host : out std_logic_vector((1-1) downto 0);
stp : out std_logic_vector((1-1) downto 0);
datao : out std_logic_vector(((1*8)-1) downto 0);
utm_rst : out std_logic_vector((1-1) downto 0);
dctrlo : out std_logic_vector((1-1) downto 0);
-- usbhc_in_type_vector unwrapped
linestate : in std_logic_vector(((1*2)-1) downto 0);
txready : in std_logic_vector((1-1) downto 0);
rxvalid : in std_logic_vector((1-1) downto 0);
rxactive : in std_logic_vector((1-1) downto 0);
rxerror : in std_logic_vector((1-1) downto 0);
vbusvalid : in std_logic_vector((1-1) downto 0);
datahi : in std_logic_vector(((1*8)-1) downto 0);
validhi : in std_logic_vector((1-1) downto 0);
hostdisc : in std_logic_vector((1-1) downto 0);
nxt : in std_logic_vector((1-1) downto 0);
dir : in std_logic_vector((1-1) downto 0);
datai : in std_logic_vector(((1*8)-1) downto 0);
-- EHC transaction buffer signals
mbc20_tb_addr : out std_logic_vector(8 downto 0);
mbc20_tb_data : out std_logic_vector(31 downto 0);
mbc20_tb_en : out std_ulogic;
mbc20_tb_wel : out std_ulogic;
mbc20_tb_weh : out std_ulogic;
tb_mbc20_data : in std_logic_vector(31 downto 0);
pe20_tb_addr : out std_logic_vector(8 downto 0);
pe20_tb_data : out std_logic_vector(31 downto 0);
pe20_tb_en : out std_ulogic;
pe20_tb_wel : out std_ulogic;
pe20_tb_weh : out std_ulogic;
tb_pe20_data : in std_logic_vector(31 downto 0);
-- EHC packet buffer signals
mbc20_pb_addr : out std_logic_vector(8 downto 0);
mbc20_pb_data : out std_logic_vector(31 downto 0);
mbc20_pb_en : out std_ulogic;
mbc20_pb_we : out std_ulogic;
pb_mbc20_data : in std_logic_vector(31 downto 0);
sie20_pb_addr : out std_logic_vector(8 downto 0);
sie20_pb_data : out std_logic_vector(31 downto 0);
sie20_pb_en : out std_ulogic;
sie20_pb_we : out std_ulogic;
pb_sie20_data : in std_logic_vector(31 downto 0);
-- UHC packet buffer signals
sie11_pb_addr : out std_logic_vector((1*9)*1 downto 1*1);
sie11_pb_data : out std_logic_vector((1*32)*1 downto 1*1);
sie11_pb_en : out std_logic_vector(1*1 downto 1*1);
sie11_pb_we : out std_logic_vector(1*1 downto 1*1);
pb_sie11_data : in std_logic_vector((1*32)*1 downto 1*1);
mbc11_pb_addr : out std_logic_vector((1*9)*1 downto 1*1);
mbc11_pb_data : out std_logic_vector((1*32)*1 downto 1*1);
mbc11_pb_en : out std_logic_vector(1*1 downto 1*1);
mbc11_pb_we : out std_logic_vector(1*1 downto 1*1);
pb_mbc11_data : in std_logic_vector((1*32)*1 downto 1*1);
bufsel : out std_ulogic);
end component;
component usbhc_axcelerator_comb1
port (
clk : in std_ulogic;
uclk : in std_ulogic;
rst : in std_ulogic;
ursti : in std_ulogic;
-- EHC apb_slv_in_type unwrapped
ehc_apbsi_psel : in std_ulogic;
ehc_apbsi_penable : in std_ulogic;
ehc_apbsi_paddr : in std_logic_vector(31 downto 0);
ehc_apbsi_pwrite : in std_ulogic;
ehc_apbsi_pwdata : in std_logic_vector(31 downto 0);
ehc_apbsi_testen : in std_ulogic;
ehc_apbsi_testrst : in std_ulogic;
ehc_apbsi_scanen : in std_ulogic;
-- EHC apb_slv_out_type unwrapped
ehc_apbso_prdata : out std_logic_vector(31 downto 0);
ehc_apbso_pirq : out std_ulogic;
-- EHC/UHC ahb_mst_in_type unwrapped
ahbmi_hgrant : in std_logic_vector(1*0 downto 0);
ahbmi_hready : in std_ulogic;
ahbmi_hresp : in std_logic_vector(1 downto 0);
ahbmi_hrdata : in std_logic_vector(31 downto 0);
ahbmi_hcache : in std_ulogic;
ahbmi_testen : in std_ulogic;
ahbmi_testrst : in std_ulogic;
ahbmi_scanen : in std_ulogic;
-- UHC ahb_slv_in_type unwrapped
uhc_ahbsi_hsel : in std_logic_vector(1*0 downto 1*0);
uhc_ahbsi_haddr : in std_logic_vector(31 downto 0);
uhc_ahbsi_hwrite : in std_ulogic;
uhc_ahbsi_htrans : in std_logic_vector(1 downto 0);
uhc_ahbsi_hsize : in std_logic_vector(2 downto 0);
uhc_ahbsi_hwdata : in std_logic_vector(31 downto 0);
uhc_ahbsi_hready : in std_ulogic;
uhc_ahbsi_testen : in std_ulogic;
uhc_ahbsi_testrst : in std_ulogic;
uhc_ahbsi_scanen : in std_ulogic;
-- EHC ahb_mst_out_type_unwrapped
ehc_ahbmo_hbusreq : out std_ulogic;
ehc_ahbmo_hlock : out std_ulogic;
ehc_ahbmo_htrans : out std_logic_vector(1 downto 0);
ehc_ahbmo_haddr : out std_logic_vector(31 downto 0);
ehc_ahbmo_hwrite : out std_ulogic;
ehc_ahbmo_hsize : out std_logic_vector(2 downto 0);
ehc_ahbmo_hburst : out std_logic_vector(2 downto 0);
ehc_ahbmo_hprot : out std_logic_vector(3 downto 0);
ehc_ahbmo_hwdata : out std_logic_vector(31 downto 0);
-- UHC ahb_mst_out_vector_type unwrapped
uhc_ahbmo_hbusreq : out std_logic_vector(1*0 downto 1*0);
uhc_ahbmo_hlock : out std_logic_vector(1*0 downto 1*0);
uhc_ahbmo_htrans : out std_logic_vector((1*2)*0 downto 1*0);
uhc_ahbmo_haddr : out std_logic_vector((1*32)*0 downto 1*0);
uhc_ahbmo_hwrite : out std_logic_vector(1*0 downto 1*0);
uhc_ahbmo_hsize : out std_logic_vector((1*3)*0 downto 1*0);
uhc_ahbmo_hburst : out std_logic_vector((1*3)*0 downto 1*0);
uhc_ahbmo_hprot : out std_logic_vector((1*4)*0 downto 1*0);
uhc_ahbmo_hwdata : out std_logic_vector((1*32)*0 downto 1*0);
-- UHC ahb_slv_out_vector_type unwrapped
uhc_ahbso_hready : out std_logic_vector(1*0 downto 1*0);
uhc_ahbso_hresp : out std_logic_vector((1*2)*0 downto 1*0);
uhc_ahbso_hrdata : out std_logic_vector((1*32)*0 downto 1*0);
uhc_ahbso_hsplit : out std_logic_vector((1*16)*0 downto 1*0);
uhc_ahbso_hcache : out std_logic_vector(1*0 downto 1*0);
uhc_ahbso_hirq : out std_logic_vector(1*0 downto 1*0);
-- usbhc_out_type_vector unwrapped
xcvrsel : out std_logic_vector(((1*2)-1) downto 0);
termsel : out std_logic_vector((1-1) downto 0);
suspendm : out std_logic_vector((1-1) downto 0);
opmode : out std_logic_vector(((1*2)-1) downto 0);
txvalid : out std_logic_vector((1-1) downto 0);
drvvbus : out std_logic_vector((1-1) downto 0);
dataho : out std_logic_vector(((1*8)-1) downto 0);
validho : out std_logic_vector((1-1) downto 0);
host : out std_logic_vector((1-1) downto 0);
stp : out std_logic_vector((1-1) downto 0);
datao : out std_logic_vector(((1*8)-1) downto 0);
utm_rst : out std_logic_vector((1-1) downto 0);
dctrlo : out std_logic_vector((1-1) downto 0);
-- usbhc_in_type_vector unwrapped
linestate : in std_logic_vector(((1*2)-1) downto 0);
txready : in std_logic_vector((1-1) downto 0);
rxvalid : in std_logic_vector((1-1) downto 0);
rxactive : in std_logic_vector((1-1) downto 0);
rxerror : in std_logic_vector((1-1) downto 0);
vbusvalid : in std_logic_vector((1-1) downto 0);
datahi : in std_logic_vector(((1*8)-1) downto 0);
validhi : in std_logic_vector((1-1) downto 0);
hostdisc : in std_logic_vector((1-1) downto 0);
nxt : in std_logic_vector((1-1) downto 0);
dir : in std_logic_vector((1-1) downto 0);
datai : in std_logic_vector(((1*8)-1) downto 0);
-- EHC transaction buffer signals
mbc20_tb_addr : out std_logic_vector(8 downto 0);
mbc20_tb_data : out std_logic_vector(31 downto 0);
mbc20_tb_en : out std_ulogic;
mbc20_tb_wel : out std_ulogic;
mbc20_tb_weh : out std_ulogic;
tb_mbc20_data : in std_logic_vector(31 downto 0);
pe20_tb_addr : out std_logic_vector(8 downto 0);
pe20_tb_data : out std_logic_vector(31 downto 0);
pe20_tb_en : out std_ulogic;
pe20_tb_wel : out std_ulogic;
pe20_tb_weh : out std_ulogic;
tb_pe20_data : in std_logic_vector(31 downto 0);
-- EHC packet buffer signals
mbc20_pb_addr : out std_logic_vector(8 downto 0);
mbc20_pb_data : out std_logic_vector(31 downto 0);
mbc20_pb_en : out std_ulogic;
mbc20_pb_we : out std_ulogic;
pb_mbc20_data : in std_logic_vector(31 downto 0);
sie20_pb_addr : out std_logic_vector(8 downto 0);
sie20_pb_data : out std_logic_vector(31 downto 0);
sie20_pb_en : out std_ulogic;
sie20_pb_we : out std_ulogic;
pb_sie20_data : in std_logic_vector(31 downto 0);
-- UHC packet buffer signals
sie11_pb_addr : out std_logic_vector((1*9)*0 downto 1*0);
sie11_pb_data : out std_logic_vector((1*32)*0 downto 1*0);
sie11_pb_en : out std_logic_vector(1*0 downto 1*0);
sie11_pb_we : out std_logic_vector(1*0 downto 1*0);
pb_sie11_data : in std_logic_vector((1*32)*0 downto 1*0);
mbc11_pb_addr : out std_logic_vector((1*9)*0 downto 1*0);
mbc11_pb_data : out std_logic_vector((1*32)*0 downto 1*0);
mbc11_pb_en : out std_logic_vector(1*0 downto 1*0);
mbc11_pb_we : out std_logic_vector(1*0 downto 1*0);
pb_mbc11_data : in std_logic_vector((1*32)*0 downto 1*0);
bufsel : out std_ulogic);
end component;
component usbhc_axcelerator_comb2
port (
clk : in std_ulogic;
uclk : in std_ulogic;
rst : in std_ulogic;
ursti : in std_ulogic;
-- EHC apb_slv_in_type unwrapped
ehc_apbsi_psel : in std_ulogic;
ehc_apbsi_penable : in std_ulogic;
ehc_apbsi_paddr : in std_logic_vector(31 downto 0);
ehc_apbsi_pwrite : in std_ulogic;
ehc_apbsi_pwdata : in std_logic_vector(31 downto 0);
ehc_apbsi_testen : in std_ulogic;
ehc_apbsi_testrst : in std_ulogic;
ehc_apbsi_scanen : in std_ulogic;
-- EHC apb_slv_out_type unwrapped
ehc_apbso_prdata : out std_logic_vector(31 downto 0);
ehc_apbso_pirq : out std_ulogic;
-- EHC/UHC ahb_mst_in_type unwrapped
ahbmi_hgrant : in std_logic_vector(1*1 downto 0);
ahbmi_hready : in std_ulogic;
ahbmi_hresp : in std_logic_vector(1 downto 0);
ahbmi_hrdata : in std_logic_vector(31 downto 0);
ahbmi_hcache : in std_ulogic;
ahbmi_testen : in std_ulogic;
ahbmi_testrst : in std_ulogic;
ahbmi_scanen : in std_ulogic;
-- UHC ahb_slv_in_type unwrapped
uhc_ahbsi_hsel : in std_logic_vector(1*1 downto 1*1);
uhc_ahbsi_haddr : in std_logic_vector(31 downto 0);
uhc_ahbsi_hwrite : in std_ulogic;
uhc_ahbsi_htrans : in std_logic_vector(1 downto 0);
uhc_ahbsi_hsize : in std_logic_vector(2 downto 0);
uhc_ahbsi_hwdata : in std_logic_vector(31 downto 0);
uhc_ahbsi_hready : in std_ulogic;
uhc_ahbsi_testen : in std_ulogic;
uhc_ahbsi_testrst : in std_ulogic;
uhc_ahbsi_scanen : in std_ulogic;
-- EHC ahb_mst_out_type_unwrapped
ehc_ahbmo_hbusreq : out std_ulogic;
ehc_ahbmo_hlock : out std_ulogic;
ehc_ahbmo_htrans : out std_logic_vector(1 downto 0);
ehc_ahbmo_haddr : out std_logic_vector(31 downto 0);
ehc_ahbmo_hwrite : out std_ulogic;
ehc_ahbmo_hsize : out std_logic_vector(2 downto 0);
ehc_ahbmo_hburst : out std_logic_vector(2 downto 0);
ehc_ahbmo_hprot : out std_logic_vector(3 downto 0);
ehc_ahbmo_hwdata : out std_logic_vector(31 downto 0);
-- UHC ahb_mst_out_vector_type unwrapped
uhc_ahbmo_hbusreq : out std_logic_vector(1*1 downto 1*1);
uhc_ahbmo_hlock : out std_logic_vector(1*1 downto 1*1);
uhc_ahbmo_htrans : out std_logic_vector((1*2)*1 downto 1*1);
uhc_ahbmo_haddr : out std_logic_vector((1*32)*1 downto 1*1);
uhc_ahbmo_hwrite : out std_logic_vector(1*1 downto 1*1);
uhc_ahbmo_hsize : out std_logic_vector((1*3)*1 downto 1*1);
uhc_ahbmo_hburst : out std_logic_vector((1*3)*1 downto 1*1);
uhc_ahbmo_hprot : out std_logic_vector((1*4)*1 downto 1*1);
uhc_ahbmo_hwdata : out std_logic_vector((1*32)*1 downto 1*1);
-- UHC ahb_slv_out_vector_type unwrapped
uhc_ahbso_hready : out std_logic_vector(1*1 downto 1*1);
uhc_ahbso_hresp : out std_logic_vector((1*2)*1 downto 1*1);
uhc_ahbso_hrdata : out std_logic_vector((1*32)*1 downto 1*1);
uhc_ahbso_hsplit : out std_logic_vector((1*16)*1 downto 1*1);
uhc_ahbso_hcache : out std_logic_vector(1*1 downto 1*1);
uhc_ahbso_hirq : out std_logic_vector(1*1 downto 1*1);
-- usbhc_out_type_vector unwrapped
xcvrsel : out std_logic_vector(((1*2)-1) downto 0);
termsel : out std_logic_vector((1-1) downto 0);
suspendm : out std_logic_vector((1-1) downto 0);
opmode : out std_logic_vector(((1*2)-1) downto 0);
txvalid : out std_logic_vector((1-1) downto 0);
drvvbus : out std_logic_vector((1-1) downto 0);
dataho : out std_logic_vector(((1*8)-1) downto 0);
validho : out std_logic_vector((1-1) downto 0);
host : out std_logic_vector((1-1) downto 0);
stp : out std_logic_vector((1-1) downto 0);
datao : out std_logic_vector(((1*8)-1) downto 0);
utm_rst : out std_logic_vector((1-1) downto 0);
dctrlo : out std_logic_vector((1-1) downto 0);
-- usbhc_in_type_vector unwrapped
linestate : in std_logic_vector(((1*2)-1) downto 0);
txready : in std_logic_vector((1-1) downto 0);
rxvalid : in std_logic_vector((1-1) downto 0);
rxactive : in std_logic_vector((1-1) downto 0);
rxerror : in std_logic_vector((1-1) downto 0);
vbusvalid : in std_logic_vector((1-1) downto 0);
datahi : in std_logic_vector(((1*8)-1) downto 0);
validhi : in std_logic_vector((1-1) downto 0);
hostdisc : in std_logic_vector((1-1) downto 0);
nxt : in std_logic_vector((1-1) downto 0);
dir : in std_logic_vector((1-1) downto 0);
datai : in std_logic_vector(((1*8)-1) downto 0);
-- EHC transaction buffer signals
mbc20_tb_addr : out std_logic_vector(8 downto 0);
mbc20_tb_data : out std_logic_vector(31 downto 0);
mbc20_tb_en : out std_ulogic;
mbc20_tb_wel : out std_ulogic;
mbc20_tb_weh : out std_ulogic;
tb_mbc20_data : in std_logic_vector(31 downto 0);
pe20_tb_addr : out std_logic_vector(8 downto 0);
pe20_tb_data : out std_logic_vector(31 downto 0);
pe20_tb_en : out std_ulogic;
pe20_tb_wel : out std_ulogic;
pe20_tb_weh : out std_ulogic;
tb_pe20_data : in std_logic_vector(31 downto 0);
-- EHC packet buffer signals
mbc20_pb_addr : out std_logic_vector(8 downto 0);
mbc20_pb_data : out std_logic_vector(31 downto 0);
mbc20_pb_en : out std_ulogic;
mbc20_pb_we : out std_ulogic;
pb_mbc20_data : in std_logic_vector(31 downto 0);
sie20_pb_addr : out std_logic_vector(8 downto 0);
sie20_pb_data : out std_logic_vector(31 downto 0);
sie20_pb_en : out std_ulogic;
sie20_pb_we : out std_ulogic;
pb_sie20_data : in std_logic_vector(31 downto 0);
-- UHC packet buffer signals
sie11_pb_addr : out std_logic_vector((1*9)*1 downto 1*1);
sie11_pb_data : out std_logic_vector((1*32)*1 downto 1*1);
sie11_pb_en : out std_logic_vector(1*1 downto 1*1);
sie11_pb_we : out std_logic_vector(1*1 downto 1*1);
pb_sie11_data : in std_logic_vector((1*32)*1 downto 1*1);
mbc11_pb_addr : out std_logic_vector((1*9)*1 downto 1*1);
mbc11_pb_data : out std_logic_vector((1*32)*1 downto 1*1);
mbc11_pb_en : out std_logic_vector(1*1 downto 1*1);
mbc11_pb_we : out std_logic_vector(1*1 downto 1*1);
pb_mbc11_data : in std_logic_vector((1*32)*1 downto 1*1);
bufsel : out std_ulogic);
end component;
component usbhc_axcelerator_comb3
port (
clk : in std_ulogic;
uclk : in std_ulogic;
rst : in std_ulogic;
ursti : in std_ulogic;
-- EHC apb_slv_in_type unwrapped
ehc_apbsi_psel : in std_ulogic;
ehc_apbsi_penable : in std_ulogic;
ehc_apbsi_paddr : in std_logic_vector(31 downto 0);
ehc_apbsi_pwrite : in std_ulogic;
ehc_apbsi_pwdata : in std_logic_vector(31 downto 0);
ehc_apbsi_testen : in std_ulogic;
ehc_apbsi_testrst : in std_ulogic;
ehc_apbsi_scanen : in std_ulogic;
-- EHC apb_slv_out_type unwrapped
ehc_apbso_prdata : out std_logic_vector(31 downto 0);
ehc_apbso_pirq : out std_ulogic;
-- EHC/UHC ahb_mst_in_type unwrapped
ahbmi_hgrant : in std_logic_vector(1*1 downto 0);
ahbmi_hready : in std_ulogic;
ahbmi_hresp : in std_logic_vector(1 downto 0);
ahbmi_hrdata : in std_logic_vector(31 downto 0);
ahbmi_hcache : in std_ulogic;
ahbmi_testen : in std_ulogic;
ahbmi_testrst : in std_ulogic;
ahbmi_scanen : in std_ulogic;
-- UHC ahb_slv_in_type unwrapped
uhc_ahbsi_hsel : in std_logic_vector(1*1 downto 1*1);
uhc_ahbsi_haddr : in std_logic_vector(31 downto 0);
uhc_ahbsi_hwrite : in std_ulogic;
uhc_ahbsi_htrans : in std_logic_vector(1 downto 0);
uhc_ahbsi_hsize : in std_logic_vector(2 downto 0);
uhc_ahbsi_hwdata : in std_logic_vector(31 downto 0);
uhc_ahbsi_hready : in std_ulogic;
uhc_ahbsi_testen : in std_ulogic;
uhc_ahbsi_testrst : in std_ulogic;
uhc_ahbsi_scanen : in std_ulogic;
-- EHC ahb_mst_out_type_unwrapped
ehc_ahbmo_hbusreq : out std_ulogic;
ehc_ahbmo_hlock : out std_ulogic;
ehc_ahbmo_htrans : out std_logic_vector(1 downto 0);
ehc_ahbmo_haddr : out std_logic_vector(31 downto 0);
ehc_ahbmo_hwrite : out std_ulogic;
ehc_ahbmo_hsize : out std_logic_vector(2 downto 0);
ehc_ahbmo_hburst : out std_logic_vector(2 downto 0);
ehc_ahbmo_hprot : out std_logic_vector(3 downto 0);
ehc_ahbmo_hwdata : out std_logic_vector(31 downto 0);
-- UHC ahb_mst_out_vector_type unwrapped
uhc_ahbmo_hbusreq : out std_logic_vector(1*1 downto 1*1);
uhc_ahbmo_hlock : out std_logic_vector(1*1 downto 1*1);
uhc_ahbmo_htrans : out std_logic_vector((1*2)*1 downto 1*1);
uhc_ahbmo_haddr : out std_logic_vector((1*32)*1 downto 1*1);
uhc_ahbmo_hwrite : out std_logic_vector(1*1 downto 1*1);
uhc_ahbmo_hsize : out std_logic_vector((1*3)*1 downto 1*1);
uhc_ahbmo_hburst : out std_logic_vector((1*3)*1 downto 1*1);
uhc_ahbmo_hprot : out std_logic_vector((1*4)*1 downto 1*1);
uhc_ahbmo_hwdata : out std_logic_vector((1*32)*1 downto 1*1);
-- UHC ahb_slv_out_vector_type unwrapped
uhc_ahbso_hready : out std_logic_vector(1*1 downto 1*1);
uhc_ahbso_hresp : out std_logic_vector((1*2)*1 downto 1*1);
uhc_ahbso_hrdata : out std_logic_vector((1*32)*1 downto 1*1);
uhc_ahbso_hsplit : out std_logic_vector((1*16)*1 downto 1*1);
uhc_ahbso_hcache : out std_logic_vector(1*1 downto 1*1);
uhc_ahbso_hirq : out std_logic_vector(1*1 downto 1*1);
-- usbhc_out_type_vector unwrapped
xcvrsel : out std_logic_vector(((2*2)-1) downto 0);
termsel : out std_logic_vector((2-1) downto 0);
suspendm : out std_logic_vector((2-1) downto 0);
opmode : out std_logic_vector(((2*2)-1) downto 0);
txvalid : out std_logic_vector((2-1) downto 0);
drvvbus : out std_logic_vector((2-1) downto 0);
dataho : out std_logic_vector(((2*8)-1) downto 0);
validho : out std_logic_vector((2-1) downto 0);
host : out std_logic_vector((2-1) downto 0);
stp : out std_logic_vector((2-1) downto 0);
datao : out std_logic_vector(((2*8)-1) downto 0);
utm_rst : out std_logic_vector((2-1) downto 0);
dctrlo : out std_logic_vector((2-1) downto 0);
-- usbhc_in_type_vector unwrapped
linestate : in std_logic_vector(((2*2)-1) downto 0);
txready : in std_logic_vector((2-1) downto 0);
rxvalid : in std_logic_vector((2-1) downto 0);
rxactive : in std_logic_vector((2-1) downto 0);
rxerror : in std_logic_vector((2-1) downto 0);
vbusvalid : in std_logic_vector((2-1) downto 0);
datahi : in std_logic_vector(((2*8)-1) downto 0);
validhi : in std_logic_vector((2-1) downto 0);
hostdisc : in std_logic_vector((2-1) downto 0);
nxt : in std_logic_vector((2-1) downto 0);
dir : in std_logic_vector((2-1) downto 0);
datai : in std_logic_vector(((2*8)-1) downto 0);
-- EHC transaction buffer signals
mbc20_tb_addr : out std_logic_vector(8 downto 0);
mbc20_tb_data : out std_logic_vector(31 downto 0);
mbc20_tb_en : out std_ulogic;
mbc20_tb_wel : out std_ulogic;
mbc20_tb_weh : out std_ulogic;
tb_mbc20_data : in std_logic_vector(31 downto 0);
pe20_tb_addr : out std_logic_vector(8 downto 0);
pe20_tb_data : out std_logic_vector(31 downto 0);
pe20_tb_en : out std_ulogic;
pe20_tb_wel : out std_ulogic;
pe20_tb_weh : out std_ulogic;
tb_pe20_data : in std_logic_vector(31 downto 0);
-- EHC packet buffer signals
mbc20_pb_addr : out std_logic_vector(8 downto 0);
mbc20_pb_data : out std_logic_vector(31 downto 0);
mbc20_pb_en : out std_ulogic;
mbc20_pb_we : out std_ulogic;
pb_mbc20_data : in std_logic_vector(31 downto 0);
sie20_pb_addr : out std_logic_vector(8 downto 0);
sie20_pb_data : out std_logic_vector(31 downto 0);
sie20_pb_en : out std_ulogic;
sie20_pb_we : out std_ulogic;
pb_sie20_data : in std_logic_vector(31 downto 0);
-- UHC packet buffer signals
sie11_pb_addr : out std_logic_vector((1*9)*1 downto 1*1);
sie11_pb_data : out std_logic_vector((1*32)*1 downto 1*1);
sie11_pb_en : out std_logic_vector(1*1 downto 1*1);
sie11_pb_we : out std_logic_vector(1*1 downto 1*1);
pb_sie11_data : in std_logic_vector((1*32)*1 downto 1*1);
mbc11_pb_addr : out std_logic_vector((1*9)*1 downto 1*1);
mbc11_pb_data : out std_logic_vector((1*32)*1 downto 1*1);
mbc11_pb_en : out std_logic_vector(1*1 downto 1*1);
mbc11_pb_we : out std_logic_vector(1*1 downto 1*1);
pb_mbc11_data : in std_logic_vector((1*32)*1 downto 1*1);
bufsel : out std_ulogic);
end component;
function valid_comb (
nports : integer range 1 to 15 := 1;
ehcgen : integer range 0 to 1 := 1;
uhcgen : integer range 0 to 1 := 1;
n_cc : integer range 1 to 15 := 1;
n_pcc : integer range 1 to 15 := 1;
prr : integer range 0 to 1 := 0;
portroute1 : integer := 0;
portroute2 : integer := 0;
endian_conv : integer range 0 to 1 := 1;
be_regs : integer range 0 to 1 := 0;
be_desc : integer range 0 to 1 := 0;
uhcblo : integer range 0 to 255 := 2;
bwrd : integer range 1 to 256 := 16;
utm_type : integer range 0 to 2 := 2;
vbusconf : integer range 0 to 3 := 3;
ramtest : integer range 0 to 1 := 0;
urst_time : integer := 250;
oepol : integer range 0 to 1 := 0)
return boolean;
end usbhc_axceleratorpkg;
package body usbhc_axceleratorpkg is
function valid_comb (
nports : integer range 1 to 15 := 1;
ehcgen : integer range 0 to 1 := 1;
uhcgen : integer range 0 to 1 := 1;
n_cc : integer range 1 to 15 := 1;
n_pcc : integer range 1 to 15 := 1;
prr : integer range 0 to 1 := 0;
portroute1 : integer := 0;
portroute2 : integer := 0;
endian_conv : integer range 0 to 1 := 1;
be_regs : integer range 0 to 1 := 0;
be_desc : integer range 0 to 1 := 0;
uhcblo : integer range 0 to 255 := 2;
bwrd : integer range 1 to 256 := 16;
utm_type : integer range 0 to 2 := 2;
vbusconf : integer range 0 to 3 := 3;
ramtest : integer range 0 to 1 := 0;
urst_time : integer := 250;
oepol : integer range 0 to 1 := 0)
return boolean is
begin
-- comb0
if nports = 1 and ehcgen = 0 and uhcgen = 1 and n_cc = 1 and
n_pcc = 1 and prr = 0 and portroute1 = 0 and portroute2 = 0 and
endian_conv = 1 and be_regs = 0 and be_desc = 0 and uhcblo = 2 and
bwrd = 16 and utm_type = 2 and vbusconf = 3 and ramtest = 0 and
urst_time = 250 and oepol = 0 then
return true;
end if;
-- comb1
if nports = 1 and ehcgen = 1 and uhcgen = 0 and n_cc = 1 and
n_pcc = 1 and prr = 0 and portroute1 = 0 and portroute2 = 0 and
endian_conv = 1 and be_regs = 0 and be_desc = 0 and uhcblo = 2 and
bwrd = 16 and utm_type = 2 and vbusconf = 3 and ramtest = 0 and
urst_time = 250 and oepol = 0 then
return true;
end if;
-- comb2
if nports = 1 and ehcgen = 1 and uhcgen = 1 and n_cc = 1 and
n_pcc = 1 and prr = 0 and portroute1 = 0 and portroute2 = 0 and
endian_conv = 1 and be_regs = 0 and be_desc = 0 and uhcblo = 2 and
bwrd = 16 and utm_type = 2 and vbusconf = 3 and ramtest = 0 and
urst_time = 250 and oepol = 0 then
return true;
end if;
-- comb3
if nports = 2 and ehcgen = 1 and uhcgen = 1 and n_cc = 1 and
n_pcc = 2 and prr = 0 and portroute1 = 0 and portroute2 = 0 and
endian_conv = 1 and be_regs = 0 and be_desc = 0 and uhcblo = 2 and
bwrd = 16 and utm_type = 2 and vbusconf = 3 and ramtest = 0 and
urst_time = 250 and oepol = 0 then
return true;
end if;
return false;
end valid_comb;
end usbhc_axceleratorpkg;
| mit | 8407c5e3305601c37ef60465ad0e5035 | 0.61313 | 3.08828 | false | false | false | false |
franz/pocl | examples/accel/rtl/simulation/vhdl/generic_sru_sim.vhd | 2 | 15,181 | -- Copyright (c) 2017 Stephan Nolting / IMS, Leibniz Univ. Hannover
--
-- This file is part of TTA-Based Codesign Environment (TCE).
--
-- Permission is hereby granted, free of charge, to any person obtaining a
-- copy of this software and associated documentation files (the "Software"),
-- to deal in the Software without restriction, including without limitation
-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- and/or sell copies of the Software, and to permit persons to whom the
-- Software is furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
-- DEALINGS IN THE SOFTWARE.
--
-------------------------------------------------------------------------------
-- Title : Generic shift and round unit; simulation model without
-- UNISIM components
-------------------------------------------------------------------------------
-- File : generic_sru.vhd
-- Author : Stephan Nolting
-- Company : Leibniz Univ. Hannover
-- Created : 2018-02-06
-- Last update: 2018-06-18
-------------------------------------------------------------------------------
-- Description: Generic shift unit providing logical left shift, logical right
-- shift & arithmetical right shift. Up to 4 pipeline registers can be inserted
-- into the data path. See the according generic's comments for further
-- information. The more pipeline registers are activated, the more the unit's
-- latency is increased.
--
-- If you use this design in your work, please cite the following publication:
-- Payá-Vayá, Guillermo, Roman Burg, and Holger Blume.
-- "Dynamic data-path self-reconfiguration of a VLIW-SIMD soft-processor
-- architecture."
-- Workshop on Self-Awareness in Reconfigurable Computing Systems, SRCS. 2012.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2018-02-06 1.0 nolting Created
-- 2018-06-11 1.1 tervoa Added MIT License, reformatted header
-- 2018-06-18 1.2 tervoa Reformat due to FUGen limitations
-- 2018-06-18 1.2 tervoa Simulation model without UNISIM components
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- library UNISIM;
-- use UNISIM.vcomponents.all;
entity generic_sru is
generic (
DATA_WIDTH : natural := 32; -- data width (power of 2)
EN_ROUNDING : boolean := false; -- enable hw for rounding to zero/infinity
-- pipeline stages --
EN_INPUT_REG : boolean := false; -- enable input registers
EN_SHIFT_REG : boolean := false; -- enable shifter output register
EN_ROUND_REG : boolean := false; -- enable rounding unit shift register
EN_OUT_REG : boolean := false -- enable output register
);
port (
-- global control --
clk : in std_logic;
-- operand data --
opa_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
opb_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
-- operation control --
shift_dir_i : in std_logic; -- 0: right, 1: left (shift dreiction)
arith_shift_i : in std_logic; -- 0: logical, 1: arithmetical (only for right shifts)
rnd_en_i : in std_logic; -- 0: rounding disabled, 1: rounding enabled
rnd_mode_i : in std_logic; -- 0: floor, 1: infinity (type of rounding)
-- operation result --
data_o : out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end generic_sru;
architecture generic_sru_xv6_rtl of generic_sru is
-- muxcy xilinx primitive component (carry chain multiplexer) --
component muxcy
port (
o : out std_logic;
ci : in std_logic;
di : in std_logic;
s : in std_logic
);
end component;
-- xorcy xilinx primitive component (carry chain 'adder') --
component xorcy
port (
o : out std_logic;
ci : in std_logic;
li : in std_logic
);
end component;
-- local types --
type smask_array_t is array(0 to DATA_WIDTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
-- Function: Minimum required bit width --
function index_size(input : natural) return natural is
begin
for i in 0 to natural'high loop
if (2**i >= input) then
return i;
end if;
end loop; -- i
return 0;
end function index_size;
-- Function: init mask for shifter's sign bit cancellation mask --
function init_smask(n: natural) return smask_array_t is
variable smask_array_v : smask_array_t;
begin
smask_array_v := (others => (others => '0'));
smask_array_v(0) := (others => '1');
for i in 0 to n-2 loop
smask_array_v(i+1) := '0' & (smask_array_v(i)(n-1 downto 1));
end loop; -- i
return smask_array_v;
end function init_smask;
-- Function: Bit reversal --
function bit_reversal(input : std_logic_vector) return std_logic_vector is
variable output_v : std_logic_vector(input'range);
begin
for i in 0 to input'length-1 loop
output_v(input'length-i-1) := input(i);
end loop; -- i
return output_v;
end function bit_reversal;
-- internal configuration --
constant log2_data_width_c : natural := index_size(DATA_WIDTH);
constant subword_c : natural := 0;
-- pipeline stage 0 (input register) --
signal opa_s0, opa_ff0 : std_logic_vector(DATA_WIDTH-1 downto 0);
signal opb_s0, opb_ff0 : std_logic_vector(DATA_WIDTH-1 downto 0);
signal shift_dir_s0, shift_dir_ff0 : std_logic;
signal shift_arith_s0, shift_arith_ff0 : std_logic;
signal rnd_en_s0, rnd_en_ff0 : std_logic;
signal rnd_mode_s0, rnd_mode_ff0 : std_logic;
-- shifter core --
constant smask_array : smask_array_t := init_smask(DATA_WIDTH);
signal sra_data : std_logic_vector(DATA_WIDTH-1 downto 0);
signal sra_mask : std_logic_vector(DATA_WIDTH-1 downto 0);
signal shift_in : std_logic_vector(DATA_WIDTH-1 downto 0);
signal shift_res : std_logic_vector(DATA_WIDTH-1 downto 0);
signal carry_sel : std_logic;
-- pipeline stage 1 --
signal sra_data_s1, sra_data_ff1 : std_logic_vector(DATA_WIDTH-1 downto 0);
signal sra_mask_s1, sra_mask_ff1 : std_logic_vector(DATA_WIDTH-1 downto 0);
signal carry_s1, carry_ff1 : std_logic;
signal shift_dir_s1, shift_dir_ff1 : std_logic;
signal shift_arith_s1, shift_arith_ff1 : std_logic;
signal rnd_en_s1, rnd_en_ff1 : std_logic;
signal rnd_mode_s1, rnd_mode_ff1 : std_logic;
-- rounding unit --
signal inc_chain : std_logic_vector(DATA_WIDTH downto 0);
signal inc_data : std_logic_vector(DATA_WIDTH-1 downto 0);
signal inc_result : std_logic_vector(DATA_WIDTH-1 downto 0);
-- pipeline stage 2 --
signal inc_res_s2, inc_res_ff2 : std_logic_vector(DATA_WIDTH-1 downto 0);
signal carry_s2, carry_ff2 : std_logic;
-- zero detector --
signal nibble_is_zero : std_logic_vector((DATA_WIDTH/4)-1 downto 0);
signal zero_chain : std_logic_vector((DATA_WIDTH/4) downto 0);
-- pipeline stage 3: output register --
signal inc_res_s3, inc_res_ff3 : std_logic_vector(DATA_WIDTH-1 downto 0);
signal carry_s3, carry_ff3 : std_logic;
signal zero_s3, zero_ff3 : std_logic;
-- zero overflow carry negative
signal z_flag_o, o_flag_o, c_flag_o, n_flag_o : std_logic;
begin
-- Pipeline Stage 0: Input Register -------------------------------------------------------
-- -------------------------------------------------------------------------------------------
pipe_s0: process(clk)
begin
if rising_edge(clk) then
opa_ff0 <= opa_i;
opb_ff0 <= opb_i;
shift_dir_ff0 <= shift_dir_i;
shift_arith_ff0 <= arith_shift_i;
rnd_en_ff0 <= rnd_en_i;
rnd_mode_ff0 <= rnd_mode_i;
end if;
end process pipe_s0;
-- use input registers? --
opa_s0 <= opa_ff0 when (EN_INPUT_REG = true) else opa_i;
opb_s0 <= opb_ff0 when (EN_INPUT_REG = true) else opb_i;
shift_dir_s0 <= shift_dir_ff0 when (EN_INPUT_REG = true) else shift_dir_i;
shift_arith_s0 <= shift_arith_ff0 when (EN_INPUT_REG = true) else arith_shift_i;
rnd_en_s0 <= rnd_en_ff0 when (EN_INPUT_REG = true) else rnd_en_i;
rnd_mode_s0 <= rnd_mode_ff0 when (EN_INPUT_REG = true) else rnd_mode_i;
-- Shifter Core ---------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
shift_in <= bit_reversal(opa_s0) when (shift_dir_s0 = '1') else opa_s0; -- reverse bits if left shift
shifter_core: process(opb_s0, shift_in)
variable carry_sel_v : std_logic_vector(DATA_WIDTH-1 downto 0);
variable positions_v : integer;
begin
-- all shift types are based on a single arithmetical right shifter
positions_v := to_integer(unsigned(opb_s0(log2_data_width_c-1 downto 0)));
sra_data <= std_logic_vector(shift_right(signed(shift_in), positions_v));
sra_mask <= smask_array(positions_v);
-- select carry --
carry_sel_v := shift_in(DATA_WIDTH-2 downto 0) & '0';
carry_sel <= carry_sel_v(positions_v);
end process shifter_core;
-- Pipeline Stage 1: Shifter output register ----------------------------------------------
-- -------------------------------------------------------------------------------------------
pipe_s1: process(clk)
begin
if rising_edge(clk) then
sra_data_ff1 <= sra_data;
sra_mask_ff1 <= sra_mask;
carry_ff1 <= carry_sel;
shift_dir_ff1 <= shift_dir_s0;
shift_arith_ff1 <= shift_arith_s0;
rnd_en_ff1 <= rnd_en_s0;
rnd_mode_ff1 <= rnd_mode_s0;
end if;
end process pipe_s1;
-- use pipeline 1 registers? --
sra_data_s1 <= sra_data_ff1 when (EN_SHIFT_REG = true) else sra_data;
sra_mask_s1 <= sra_mask_ff1 when (EN_SHIFT_REG = true) else sra_mask;
carry_s1 <= carry_ff1 when (EN_SHIFT_REG = true) else carry_sel;
shift_dir_s1 <= shift_dir_ff1 when (EN_SHIFT_REG = true) else shift_dir_s0;
shift_arith_s1 <= shift_arith_ff1 when (EN_SHIFT_REG = true) else shift_arith_s0;
rnd_en_s1 <= rnd_en_ff1 when (EN_SHIFT_REG = true) else rnd_en_s0;
rnd_mode_s1 <= rnd_mode_ff1 when (EN_SHIFT_REG = true) else rnd_mode_s0;
-- Shifter result masking ------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------
shifter_sel: process(shift_dir_s1, shift_arith_s1, sra_data_s1, sra_mask_s1)
variable lrs_v : std_logic_vector(DATA_WIDTH-1 downto 0);
begin
lrs_v := sra_data_s1 and sra_mask_s1;
if (shift_dir_s1 = '1') then -- logical left shift
shift_res <= bit_reversal(lrs_v);
else -- right shift
if (shift_arith_s1 = '1') then -- arithmetical right shift
shift_res <= sra_data_s1;
else -- logical right shift
shift_res <= lrs_v;
end if;
end if;
end process shifter_sel;
-- Rounding --------------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------
-- start of incrementer carry line with internal carry input
inc_chain(0) <= carry_s1 and (rnd_en_s1 and rnd_mode_s1);
-- simple incrementer, using dedicated hardware (muxcy, xorcy)
increment_unit:
for i in 0 to DATA_WIDTH-1 generate
-- inc_muxcy_inst: muxcy
-- port map (
-- o => inc_chain(i+1),
-- ci => inc_chain(i),
-- di => '0',
-- s => shift_res(i)
-- );
inc_chain(i+1) <= '0' when shift_res(i) = '0' else inc_chain(i);
-- inc_xorcy_inst: xorcy
-- port map (
-- o => inc_data(i),
-- ci => inc_chain(i),
-- li => shift_res(i)
-- );
inc_data(i) <= inc_chain(i) xor shift_res(i);
end generate; -- i
-- operation result output --
inc_result <= inc_data when (EN_ROUNDING = true) else shift_res;
-- Pipeline Stage 2: Rounding unit output register ----------------------------------------
-- -------------------------------------------------------------------------------------------
pipe_s2: process(clk)
begin
if rising_edge(clk) then
inc_res_ff2 <= inc_result;
carry_ff2 <= carry_s1;
end if;
end process pipe_s2;
-- use pipeline 2 registers? --
inc_res_s2 <= inc_res_ff2 when (EN_ROUND_REG = true) else inc_result;
carry_s2 <= carry_ff2 when (EN_ROUND_REG = true) else carry_s1;
-- Zero Detector --------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
zero_chain(0) <= '1'; -- start a new subword chain
zero_detector:
for i in 0 to (DATA_WIDTH/4)-1 generate -- number of nibbles
-- zero detection for 4 bit -> 1 LUT + 1 MUXCY, propagate previous zero signal, when nibble is zero
nibble_is_zero(i) <= '1' when (inc_res_s2(i*4+3 downto i*4) = "0000") else '0'; -- is zero?
-- zero_detector_muxcy: muxcy
-- port map (
-- o => zero_chain(i+1), -- chain output signal
-- ci => zero_chain(i), -- s=1: chain input signal
-- di => '0', -- s=0: 0 input, nibble is not zero
-- s => nibble_is_zero(i) -- mux select input
-- );
zero_chain(i+1) <= '0' when nibble_is_zero(i) = '0' else zero_chain(i);
end generate; -- i
-- Pipeline Stage 3: Output register ------------------------------------------------------
-- -------------------------------------------------------------------------------------------
pipe_s3: process(clk)
begin
if rising_edge(clk) then
inc_res_ff3 <= inc_res_s2;
carry_ff3 <= carry_s2;
zero_ff3 <= zero_chain(DATA_WIDTH/4);
end if;
end process pipe_s3;
-- use pipeline 2 registers? --
inc_res_s3 <= inc_res_ff3 when (EN_OUT_REG = true) else inc_res_s2;
carry_s3 <= carry_ff3 when (EN_OUT_REG = true) else carry_s2;
zero_s3 <= zero_ff3 when (EN_OUT_REG = true) else zero_chain(DATA_WIDTH/4);
-- data output --
data_o <= inc_res_s3;
-- negative flag output --
n_flag_o <= inc_res_s3(DATA_WIDTH-1);
-- zero flag output --
z_flag_o <= zero_s3;
-- carry flag output --
c_flag_o <= carry_s3;
-- TODO: overflow:
-- all out-shifted bits should be equal to the sign, else overflow
-- for signed operations, also the result sign should be equal to the original sign
o_flag_o <= '0'; -- implement me!
end generic_sru_xv6_rtl;
| mit | 78df79588d1d128b3d39981a803d71ef | 0.56901 | 3.530821 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/designs/leon3mp/ahbrom.vhd | 2 | 7,078 |
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- See the file COPYING for the full details of the license.
--
-----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 9;
constant bytes : integer := 368;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hcache <= '1';
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= romdata;
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= romdata;
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"81D82000";
when 16#00001# => romdata <= X"03000004";
when 16#00002# => romdata <= X"821060E0";
when 16#00003# => romdata <= X"81884000";
when 16#00004# => romdata <= X"81900000";
when 16#00005# => romdata <= X"81980000";
when 16#00006# => romdata <= X"81800000";
when 16#00007# => romdata <= X"01000000";
when 16#00008# => romdata <= X"03002040";
when 16#00009# => romdata <= X"8210600F";
when 16#0000A# => romdata <= X"C2A00040";
when 16#0000B# => romdata <= X"87444000";
when 16#0000C# => romdata <= X"8608E01F";
when 16#0000D# => romdata <= X"88100000";
when 16#0000E# => romdata <= X"8A100000";
when 16#0000F# => romdata <= X"8C100000";
when 16#00010# => romdata <= X"8E100000";
when 16#00011# => romdata <= X"A0100000";
when 16#00012# => romdata <= X"A2100000";
when 16#00013# => romdata <= X"A4100000";
when 16#00014# => romdata <= X"A6100000";
when 16#00015# => romdata <= X"A8100000";
when 16#00016# => romdata <= X"AA100000";
when 16#00017# => romdata <= X"AC100000";
when 16#00018# => romdata <= X"AE100000";
when 16#00019# => romdata <= X"90100000";
when 16#0001A# => romdata <= X"92100000";
when 16#0001B# => romdata <= X"94100000";
when 16#0001C# => romdata <= X"96100000";
when 16#0001D# => romdata <= X"98100000";
when 16#0001E# => romdata <= X"9A100000";
when 16#0001F# => romdata <= X"9C100000";
when 16#00020# => romdata <= X"9E100000";
when 16#00021# => romdata <= X"86A0E001";
when 16#00022# => romdata <= X"16BFFFEF";
when 16#00023# => romdata <= X"81E00000";
when 16#00024# => romdata <= X"82102002";
when 16#00025# => romdata <= X"81904000";
when 16#00026# => romdata <= X"03000004";
when 16#00027# => romdata <= X"821060E0";
when 16#00028# => romdata <= X"81884000";
when 16#00029# => romdata <= X"01000000";
when 16#0002A# => romdata <= X"01000000";
when 16#0002B# => romdata <= X"01000000";
when 16#0002C# => romdata <= X"87444000";
when 16#0002D# => romdata <= X"8730E01C";
when 16#0002E# => romdata <= X"8688E00F";
when 16#0002F# => romdata <= X"12800016";
when 16#00030# => romdata <= X"03200000";
when 16#00031# => romdata <= X"05040E00";
when 16#00032# => romdata <= X"8410A233";
when 16#00033# => romdata <= X"C4204000";
when 16#00034# => romdata <= X"0539A81B";
when 16#00035# => romdata <= X"8410A260";
when 16#00036# => romdata <= X"C4206004";
when 16#00037# => romdata <= X"050003FC";
when 16#00038# => romdata <= X"C4206008";
when 16#00039# => romdata <= X"82103860";
when 16#0003A# => romdata <= X"C4004000";
when 16#0003B# => romdata <= X"8530A00C";
when 16#0003C# => romdata <= X"03000004";
when 16#0003D# => romdata <= X"82106009";
when 16#0003E# => romdata <= X"80A04002";
when 16#0003F# => romdata <= X"12800006";
when 16#00040# => romdata <= X"033FFC00";
when 16#00041# => romdata <= X"82106100";
when 16#00042# => romdata <= X"0539A81B";
when 16#00043# => romdata <= X"8410A260";
when 16#00044# => romdata <= X"C4204000";
when 16#00045# => romdata <= X"05000008";
when 16#00046# => romdata <= X"82100000";
when 16#00047# => romdata <= X"80A0E000";
when 16#00048# => romdata <= X"02800005";
when 16#00049# => romdata <= X"01000000";
when 16#0004A# => romdata <= X"82004002";
when 16#0004B# => romdata <= X"10BFFFFC";
when 16#0004C# => romdata <= X"8620E001";
when 16#0004D# => romdata <= X"3D1003FF";
when 16#0004E# => romdata <= X"BC17A3E0";
when 16#0004F# => romdata <= X"BC278001";
when 16#00050# => romdata <= X"9C27A060";
when 16#00051# => romdata <= X"03100000";
when 16#00052# => romdata <= X"81C04000";
when 16#00053# => romdata <= X"01000000";
when 16#00054# => romdata <= X"01000000";
when 16#00055# => romdata <= X"01000000";
when 16#00056# => romdata <= X"01000000";
when 16#00057# => romdata <= X"01000000";
when 16#00058# => romdata <= X"00000000";
when 16#00059# => romdata <= X"00000000";
when 16#0005A# => romdata <= X"00000000";
when 16#0005B# => romdata <= X"00000000";
when 16#0005C# => romdata <= X"00000000";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
| mit | 60c6f937325aaa60494e48fe78cb1ace | 0.584063 | 3.348155 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/tech/axcelerator/components/axcelerator.vhd | 2 | 34,835 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- pragma translate_on
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity RAM64K36 is
-- pragma translate_off
generic (MEMORYFILE:string := "");
-- pragma translate_on
port(
DEPTH3, DEPTH2, DEPTH1, DEPTH0,
WRAD15, WRAD14, WRAD13, WRAD12, WRAD11, WRAD10, WRAD9 ,
WRAD8 , WRAD7 , WRAD6 , WRAD5 , WRAD4 , WRAD3 , WRAD2 ,
WRAD1 , WRAD0 , WD35 , WD34 , WD33 , WD32 , WD31 ,
WD30 , WD29 , WD28 , WD27 , WD26 , WD25 , WD24 ,
WD23 , WD22 , WD21 , WD20 , WD19 , WD18 , WD17 ,
WD16 , WD15 , WD14 , WD13 , WD12 , WD11 , WD10 ,
WD9 , WD8 , WD7 , WD6 , WD5 , WD4 , WD3 ,
WD2 , WD1 , WD0 , WW2 , WW1 , WW0 , WEN ,
WCLK , RDAD15, RDAD14, RDAD13, RDAD12, RDAD11, RDAD10,
RDAD9 , RDAD8 , RDAD7 , RDAD6 , RDAD5 , RDAD4 , RDAD3 ,
RDAD2 , RDAD1 , RDAD0 , RW2 , RW1 , RW0 , REN ,
RCLK : in std_ulogic ;
RD35 , RD34 , RD33 , RD32 , RD31 , RD30 , RD29 ,
RD28 , RD27 , RD26 , RD25 , RD24 , RD23 , RD22 ,
RD21 , RD20 , RD19 , RD18 , RD17 , RD16 , RD15 ,
RD14 , RD13 , RD12 , RD11 , RD10 , RD9 , RD8 ,
RD7 , RD6 , RD5 , RD4 , RD3 , RD2 , RD1 ,
RD0 : out std_ulogic);
end;
architecture rtl of RAM64K36 is
signal re : std_ulogic;
begin
rp : process(RCLK, WCLK)
constant words : integer := 2**16;
subtype word is std_logic_vector(35 downto 0);
type dregtype is array (0 to words - 1) of word;
variable rfd : dregtype;
variable wa, ra : std_logic_vector(15 downto 0);
variable q : std_logic_vector(35 downto 0);
begin
if rising_edge(RCLK) then
ra := RDAD15 & RDAD14 & RDAD13 & RDAD12 & RDAD11 & RDAD10 & RDAD9 &
RDAD8 & RDAD7 & RDAD6 & RDAD5 & RDAD4 & RDAD3 & RDAD2 & RDAD1 & RDAD0;
if not (is_x (ra)) and REN = '1' then
q := rfd(to_integer(unsigned(ra)) mod words);
else q := (others => 'X'); end if;
end if;
if rising_edge(WCLK) and (wen = '1') then
wa := WRAD15 & WRAD14 & WRAD13 & WRAD12 & WRAD11 & WRAD10 & WRAD9 &
WRAD8 & WRAD7 & WRAD6 & WRAD5 & WRAD4 & WRAD3 & WRAD2 & WRAD1 & WRAD0;
if not is_x (wa) then
rfd(to_integer(unsigned(wa)) mod words) :=
WD35 & WD34 & WD33 & WD32 & WD31 & WD30 & WD29 & WD28 & WD27 &
WD26 & WD25 & WD24 & WD23 & WD22 & WD21 & WD20 & WD19 & WD18 &
WD17 & WD16 & WD15 & WD14 & WD13 & WD12 & WD11 & WD10 & WD9 &
WD8 & WD7 & WD6 & WD5 & WD4 & WD3 & WD2 & WD1 & WD0;
end if;
if ra = wa then q := (others => 'X'); end if; -- no write-through
end if;
RD35 <= q(35); RD34 <= q(34); RD33 <= q(33); RD32 <= q(32); RD31 <= q(31);
RD30 <= q(30); RD29 <= q(29); RD28 <= q(28); RD27 <= q(27); RD26 <= q(26);
RD25 <= q(25); RD24 <= q(24); RD23 <= q(23); RD22 <= q(22); RD21 <= q(21);
RD20 <= q(20); RD19 <= q(19); RD18 <= q(18); RD17 <= q(17); RD16 <= q(16);
RD15 <= q(15); RD14 <= q(14); RD13 <= q(13); RD12 <= q(12); RD11 <= q(11);
RD10 <= q(10); RD9 <= q(9); RD8 <= q(8); RD7 <= q(7); RD6 <= q(6);
RD5 <= q(5); RD4 <= q(4); RD3 <= q(3); RD2 <= q(2); RD1 <= q(1);
RD0 <= q(0);
end process;
end;
-- PCI PADS ----------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity hclkbuf_pci is port( pad : in std_logic; y : out std_logic); end;
architecture struct of hclkbuf_pci is begin y <= to_X01(pad); end;
library ieee;
use ieee.std_logic_1164.all;
entity clkbuf_pci is port( pad : in std_logic; y : out std_logic); end;
architecture struct of clkbuf_pci is begin y <= to_X01(pad); end;
library ieee;
use ieee.std_logic_1164.all;
entity inbuf_pci is port( pad : in std_logic; y : out std_logic); end;
architecture struct of inbuf_pci is begin y <= to_X01(pad) after 2 ns; end;
library ieee;
use ieee.std_logic_1164.all;
entity bibuf_pci is port
(d, e : in std_logic; pad : inout std_logic; y : out std_logic);
end;
architecture struct of bibuf_pci is begin
y <= to_X01(pad) after 2 ns;
pad <= d after 5 ns when to_X01(e) = '1' else
'Z' after 5 ns when to_X01(e) = '0' else 'X' after 5 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity tribuff_pci is port (d, e : in std_logic; pad : out std_logic ); end;
architecture struct of tribuff_pci is begin
pad <= d after 5 ns when to_X01(e) = '1' else
'Z' after 5 ns when to_X01(e) = '0' else 'X' after 5 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity outbuf_pci is port (d : in std_logic; pad : out std_logic ); end;
architecture struct of outbuf_pci is begin pad <= d after 5 ns; end;
-- STANDARD PADS ----------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity clkbuf is port( pad : in std_logic; y : out std_logic); end;
architecture struct of clkbuf is begin y <= to_X01(pad); end;
library ieee;
use ieee.std_logic_1164.all;
entity hclkbuf is port( pad : in std_logic; y : out std_logic); end;
architecture struct of hclkbuf is begin y <= to_X01(pad); end;
library ieee;
use ieee.std_logic_1164.all;
entity inbuf is port( pad : in std_logic; y : out std_logic); end;
architecture struct of inbuf is begin y <= to_X01(pad) after 1 ns; end;
library ieee;
use ieee.std_logic_1164.all;
entity iopad_in is port( pad : in std_logic; y : out std_logic); end;
architecture struct of iopad_in is begin y <= to_X01(pad) after 1 ns; end;
library ieee;
use ieee.std_logic_1164.all;
entity iopad_in_u is port( pad : in std_logic; y : out std_logic); end;
architecture struct of iopad_in_u is begin y <= to_X01(pad) after 1 ns; end;
library ieee;
use ieee.std_logic_1164.all;
entity iopad_in_u is port( pad : in std_logic; y : out std_logic); end;
architecture struct of iopad_in_u is begin y <= to_X01(pad) after 1 ns; end;
library ieee;
use ieee.std_logic_1164.all;
entity bibuf is port
(d, e : in std_logic; pad : inout std_logic; y : out std_logic);
end;
architecture struct of bibuf is begin
y <= to_X01(pad) after 2 ns;
pad <= d after 2 ns when to_X01(e) = '1' else
'Z' after 2 ns when to_X01(e) = '0' else 'X' after 2 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity iopad_bi is port
(d, e : in std_logic; pad : inout std_logic; y : out std_logic);
end;
architecture struct of iopad_bi is begin
y <= to_X01(pad) after 2 ns;
pad <= d after 2 ns when to_X01(e) = '1' else
'Z' after 2 ns when to_X01(e) = '0' else 'X' after 2 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity tribuff is port (d, e : in std_logic; pad : out std_logic ); end;
architecture struct of tribuff is begin
pad <= d after 2 ns when to_X01(e) = '1' else
'Z' after 2 ns when to_X01(e) = '0' else 'X' after 2 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity iopad_tri is port (d, e : in std_logic; pad : out std_logic ); end;
architecture struct of iopad_tri is begin
pad <= d after 2 ns when to_X01(e) = '1' else
'Z' after 2 ns when to_X01(e) = '0' else 'X' after 2 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity iopad_tri_u is port (d, e : in std_logic; pad : out std_logic ); end;
architecture struct of iopad_tri_u is begin
pad <= d after 2 ns when to_X01(e) = '1' else
'Z' after 2 ns when to_X01(e) = '0' else 'X' after 2 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity iopadp_tri is port (d, e : in std_logic; pad : out std_logic ); end;
architecture struct of iopadp_tri is begin
pad <= d after 2 ns when to_X01(e) = '1' else
'Z' after 2 ns when to_X01(e) = '0' else 'X' after 2 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity iopadp_in is port (n2pin, pad : in std_logic; y : out std_logic ); end;
architecture struct of iopadp_in is begin
y <= pad after 2 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity iopadn_in is port ( pad : in std_logic; n2pout : out std_logic ); end;
architecture struct of iopadn_in is begin
n2pout <= pad after 2 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity iopadn_tri is port (db, e : in std_logic; pad : out std_logic ); end;
architecture struct of iopadn_tri is begin
pad <= not db after 2 ns when to_X01(e) = '1' else
'Z' after 2 ns when to_X01(e) = '0' else 'X' after 2 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity outbuf is port (d : in std_logic; pad : out std_logic ); end;
architecture struct of outbuf is begin pad <= d after 2 ns; end;
library ieee;
use ieee.std_logic_1164.all;
entity outbuf_f_8 is port (d : in std_logic; pad : out std_logic ); end;
architecture struct of outbuf_f_8 is begin pad <= d after 2 ns; end;
library ieee;
use ieee.std_logic_1164.all;
entity outbuf_f_12 is port (d : in std_logic; pad : out std_logic ); end;
architecture struct of outbuf_f_12 is begin pad <= d after 2 ns; end;
library ieee;
use ieee.std_logic_1164.all;
entity outbuf_f_16 is port (d : in std_logic; pad : out std_logic ); end;
architecture struct of outbuf_f_16 is begin pad <= d after 2 ns; end;
library ieee;
use ieee.std_logic_1164.all;
entity outbuf_f_24 is port (d : in std_logic; pad : out std_logic ); end;
architecture struct of outbuf_f_24 is begin pad <= d after 2 ns; end;
library ieee;
use ieee.std_logic_1164.all;
entity inbuf_lvds is port( y : out std_logic; padp, padn : in std_logic); end;
architecture struct of inbuf_lvds is
signal yn : std_ulogic := '0';
begin
yn <= to_X01(padp) after 1 ns when to_x01(padp xor padn) = '1' else yn after 1 ns;
y <= yn;
end;
library ieee;
use ieee.std_logic_1164.all;
entity outbuf_lvds is port (d : in std_logic; padp, padn : out std_logic ); end;
architecture struct of outbuf_lvds is begin
padp <= d after 1 ns;
padn <= not d after 1 ns;
end;
-- clock buffers ----------------------
library ieee;
use ieee.std_logic_1164.all;
entity hclkint is port( a : in std_logic; y : out std_logic); end;
architecture struct of hclkint is begin y <= to_X01(a); end;
library ieee;
use ieee.std_logic_1164.all;
entity clkint is port( a : in std_logic; y : out std_logic); end;
architecture struct of clkint is begin y <= to_X01(a); end;
library ieee;
use ieee.std_logic_1164.all;
entity IOFIFO_BIBUF is
port( AIN : in std_logic;
AOUT : in std_logic;
YIN : out std_logic;
YOUT : out std_logic
);
end ;
architecture struct of IOFIFO_BIBUF is begin
YIN <= to_X01(AIN);
YOUT <= to_X01(AOUT);
end;
library ieee;
use ieee.std_logic_1164.all;
entity add1 is
port(
a : in std_logic;
b : in std_logic;
fci : in std_logic;
s : out std_logic;
fco : out std_logic);
end add1;
architecture beh of add1 is
signal un1_fco : std_logic;
signal un2_fco : std_logic;
signal un3_fco : std_logic;
begin
s <= a xor b xor fci;
un1_fco <= a and b;
un2_fco <= a and fci;
un3_fco <= b and fci;
fco <= un1_fco or un2_fco or un3_fco;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity and2 is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end and2;
architecture beh of and2 is
begin
y <= b and a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity and2a is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end and2a;
architecture beh of and2a is
signal ai : std_logic;
begin
ai <= not a;
y <= b and ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity and2b is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end and2b;
architecture beh of and2b is
signal ai : std_logic;
signal bi : std_logic;
begin
ai <= not a;
bi <= not b;
y <= bi and ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity and3 is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end and3;
architecture beh of and3 is
begin
y <= c and b and a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity and3a is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end and3a;
architecture beh of and3a is
signal ai : std_logic;
begin
ai <= not a;
y <= c and b and ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity and3b is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end and3b;
architecture beh of and3b is
signal ai : std_logic;
signal bi : std_logic;
begin
ai <= not a;
bi <= not b;
y <= c and bi and ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity and3c is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end and3c;
architecture beh of and3c is
signal ai : std_logic;
signal bi : std_logic;
signal ci : std_logic;
begin
ai <= not a;
bi <= not b;
ci <= not c;
y <= ci and bi and ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity and4 is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end and4;
architecture beh of and4 is
begin
y <= d and c and b and a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity and4a is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end and4a;
architecture beh of and4a is
signal ai : std_logic;
begin
ai <= not a;
y <= d and c and b and ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity and4b is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end and4b;
architecture beh of and4b is
signal ai : std_logic;
signal bi : std_logic;
begin
ai <= not a;
bi <= not b;
y <= d and c and bi and ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity and4c is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end and4c;
architecture beh of and4c is
signal ai : std_logic;
signal bi : std_logic;
signal ci : std_logic;
begin
ai <= not a;
bi <= not b;
ci <= not c;
y <= d and ci and bi and ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity buff is
port(
a : in std_logic;
y : out std_logic);
end buff;
architecture beh of buff is
begin
y <= a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity ioi_buff is
port(
a : in std_logic;
y : out std_logic);
end ioi_buff;
architecture beh of ioi_buff is
begin
y <= a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity iooe_buff is
port(
a : in std_logic;
y : out std_logic);
end iooe_buff;
architecture beh of iooe_buff is
begin
y <= a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity iofifo_outbuf is
port(
a : in std_logic;
y : out std_logic);
end iofifo_outbuf;
architecture beh of iofifo_outbuf is
begin
y <= a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity cm8buff is
port(
a : in std_logic;
y : out std_logic);
end cm8buff;
architecture beh of cm8buff is
begin
y <= a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity hclkmux is
port(
a : in std_logic;
y : out std_logic);
end hclkmux;
architecture beh of hclkmux is
begin
y <= a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity rclkmux is
port(
a : in std_logic;
y : out std_logic);
end rclkmux;
architecture beh of rclkmux is
begin
y <= a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity IOFIFO_INBUF is
port(
a : in std_logic;
y : out std_logic);
end IOFIFO_INBUF;
architecture beh of IOFIFO_INBUF is
begin
y <= a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity CLKINT_W is
port(
a : in std_logic;
y : out std_logic);
end CLKINT_W;
architecture beh of CLKINT_W is
begin
y <= a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity fcend_buff is
port(
fci : in std_logic;
co : out std_logic);
end fcend_buff;
architecture beh of fcend_buff is
begin
co <= fci;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity fcinit_buff is
port(
a : in std_logic;
fco : out std_logic);
end fcinit_buff;
architecture beh of fcinit_buff is
begin
fco <= a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity cm8 is
port(
d0 : in std_logic;
d1 : in std_logic;
d2 : in std_logic;
d3 : in std_logic;
s00 : in std_logic;
s01 : in std_logic;
s10 : in std_logic;
s11 : in std_logic;
y : out std_logic);
end cm8;
architecture beh of cm8 is
signal s0 : std_logic;
signal s1 : std_logic;
signal m0 : std_logic;
signal m1 : std_logic;
begin
s0 <= s01 and s00;
s1 <= s11 or s10;
m0 <= d0 when s0 = '0' else d1;
m1 <= d2 when s0 = '0' else d3;
y <= m0 when s1 = '0' else m1;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity cm8inv is
port(
a : in std_logic;
y : out std_logic);
end cm8inv;
architecture beh of cm8inv is
begin
y <= not a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity df1 is
port(
d : in std_logic;
clk : in std_logic;
q : out std_logic);
end df1;
architecture beh of df1 is
begin
ff : process (clk)
begin
if rising_edge(clk) then
q <= d;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity df1b is
port(
d : in std_logic;
clk : in std_logic;
q : out std_logic);
end df1b;
architecture beh of df1b is
begin
ff : process (clk)
begin
if falling_edge(clk) then
q <= d;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity dfc1b is
port(
d : in std_logic;
clk : in std_logic;
clr : in std_logic;
q : out std_logic);
end dfc1b;
architecture beh of dfc1b is
begin
ff : process (clk, clr)
begin
if clr = '0' then
q <= '0';
elsif rising_edge(clk) then
q <= d;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity dfc1c is
port(
d : in std_logic;
clk : in std_logic;
clr : in std_logic;
q : out std_logic);
end dfc1c;
architecture beh of dfc1c is
begin
ff : process (clk, clr)
begin
if clr = '1' then
q <= '1';
elsif rising_edge(clk) then
q <= not d;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity dfc1d is
port(
d : in std_logic;
clk : in std_logic;
clr : in std_logic;
q : out std_logic);
end dfc1d;
architecture beh of dfc1d is
begin
ff : process (clk, clr)
begin
if clr = '0' then
q <= '0';
elsif falling_edge(clk) then
q <= d;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity dfe1b is
port(
d : in std_logic;
e : in std_logic;
clk : in std_logic;
q : out std_logic);
end dfe1b;
architecture beh of dfe1b is
signal q_int_1 : std_logic;
signal nq : std_logic;
begin
nq <= d when e = '0' else q_int_1;
q <= q_int_1;
ff : process (clk)
begin
if rising_edge(clk) then
q_int_1 <= nq;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity dfe3c is
port(
d : in std_logic;
e : in std_logic;
clk : in std_logic;
clr : in std_logic;
q : out std_logic);
end dfe3c;
architecture beh of dfe3c is
signal q_int_0 : std_logic;
signal md : std_logic;
begin
md <= d when e = '0' else q_int_0;
q <= q_int_0;
ff : process (clk, clr)
begin
if clr = '0' then
q_int_0 <= '0';
elsif rising_edge(clk) then
q_int_0 <= md;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity dfe4f is
port(
d : in std_logic;
e : in std_logic;
clk : in std_logic;
pre : in std_logic;
q : out std_logic);
end dfe4f;
architecture beh of dfe4f is
signal q_int_1 : std_logic;
signal un1 : std_logic;
begin
un1 <= d when e = '0' else q_int_1;
q <= q_int_1;
ff : process (clk, pre)
begin
if pre = '0' then
q_int_1 <= '1';
elsif rising_edge(clk) then
q_int_1 <= un1;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity dfp1 is
port(
d : in std_logic;
clk : in std_logic;
pre : in std_logic;
q : out std_logic);
end dfp1;
architecture beh of dfp1 is
begin
ff : process (clk, pre)
begin
if pre = '1' then
q <= '1';
elsif rising_edge(clk) then
q <= d;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity dfp1b is
port(
d : in std_logic;
clk : in std_logic;
pre : in std_logic;
q : out std_logic);
end dfp1b;
architecture beh of dfp1b is
begin
ff : process (clk, pre)
begin
if pre = '0' then
q <= '1';
elsif rising_edge(clk) then
q <= d;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity dfp1d is
port(
d : in std_logic;
clk : in std_logic;
pre : in std_logic;
q : out std_logic);
end dfp1d;
architecture beh of dfp1d is
begin
ff : process (clk, pre)
begin
if pre = '0' then
q <= '1';
elsif falling_edge(clk) then
q <= d;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity dfeh is
port(
d : in std_logic;
clk : in std_logic;
clr : in std_logic;
pre : in std_logic;
e : in std_logic;
q : out std_logic);
end dfeh;
architecture beh of dfeh is
begin
ff : process (clk, pre, clr)
begin
if clr = '0' then
q <= '0';
elsif pre = '0' then
q <= '1';
elsif falling_edge(clk) and (e = '0') then
q <= d;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity iooe_dfeh is
port(
d : in std_logic;
clk : in std_logic;
clr : in std_logic;
pre : in std_logic;
e : in std_logic;
q : out std_logic;
yout : out std_logic);
end iooe_dfeh;
architecture beh of iooe_dfeh is
begin
ff : process (clk, pre, clr)
begin
if clr = '0' then
q <= '0';
yout <= '0';
elsif pre = '0' then
q <= '1';
yout <= '1';
elsif falling_edge(clk) and (e = '0') then
q <= d;
yout <= d;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity dfeg is
port(
d : in std_logic;
clk : in std_logic;
clr : in std_logic;
pre : in std_logic;
e : in std_logic;
q : out std_logic);
end dfeg;
architecture beh of dfeg is
begin
ff : process (clk, pre, clr)
begin
if clr = '0' then
q <= '0';
elsif pre = '0' then
q <= '1';
elsif rising_edge(clk) and (e = '0') then
q <= d;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity dfmeg is
port(
a : in std_logic;
b : in std_logic;
clk : in std_logic;
clr : in std_logic;
pre : in std_logic;
e : in std_logic;
s : in std_logic;
q : out std_logic);
end dfmeg;
architecture beh of dfmeg is
begin
ff : process (clk, pre, clr)
begin
if clr = '0' then
q <= '0';
elsif pre = '0' then
q <= '1';
elsif rising_edge(clk) and (e = '0') then
if s = '0' then q <= a; else q <= b; end if;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity ioi_dfeg is
port(
d : in std_logic;
clk : in std_logic;
clr : in std_logic;
pre : in std_logic;
e : in std_logic;
q : out std_logic);
end ioi_dfeg;
architecture beh of ioi_dfeg is
begin
ff : process (clk, pre, clr)
begin
if clr = '0' then
q <= '0';
elsif pre = '0' then
q <= '1';
elsif rising_edge(clk) and (e = '0') then
q <= d;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity iooe_dfeg is
port(
d : in std_logic;
clk : in std_logic;
clr : in std_logic;
pre : in std_logic;
e : in std_logic;
q : out std_logic;
yout : out std_logic);
end iooe_dfeg;
architecture beh of iooe_dfeg is
begin
ff : process (clk, pre, clr)
begin
if clr = '0' then
q <= '0';
yout <= '0';
elsif pre = '0' then
q <= '1';
yout <= '1';
elsif rising_edge(clk) and (e = '0') then
q <= d;
yout <= d;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity gnd is
port(
y : out std_logic);
end gnd;
architecture beh of gnd is
begin
y <= '0';
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity dfm is
port(
clk : in std_logic;
s : in std_logic;
a : in std_logic;
b : in std_logic;
q : out std_logic);
end dfm;
architecture beh of dfm is
begin
ff : process (clk)
begin
if rising_edge(clk) then
if s = '0' then q <= a;
else q <= b; end if;
end if;
end process ff;
end beh;
--
--library ieee;
--use ieee.std_logic_1164.all;
--entity hclkbuf is
-- port(
-- pad : in std_logic;
-- y : out std_logic);
--end hclkbuf;
--architecture beh of hclkbuf is
--begin
-- y <= pad;
--end beh;
--
--
--library ieee;
--use ieee.std_logic_1164.all;
--entity inbuf is
-- port(
-- pad : in std_logic;
-- y : out std_logic);
--end inbuf;
--architecture beh of inbuf is
--begin
-- y <= pad;
--end beh;
library ieee;
use ieee.std_logic_1164.all;
entity inv is
port(
a : in std_logic;
y : out std_logic);
end inv;
architecture beh of inv is
begin
y <= not a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity nand2 is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end nand2;
architecture beh of nand2 is
signal yx : std_logic;
begin
yx <= b and a;
y <= not yx;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity nand4 is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end nand4;
architecture beh of nand4 is
signal yx : std_logic;
begin
yx <= d and c and b and a;
y <= not yx;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity or2 is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end or2;
architecture beh of or2 is
begin
y <= b or a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity or2a is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end or2a;
architecture beh of or2a is
signal ai : std_logic;
begin
ai <= not a;
y <= b or ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity or2b is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end or2b;
architecture beh of or2b is
signal ai : std_logic;
signal bi : std_logic;
begin
ai <= not a;
bi <= not b;
y <= bi or ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity or3 is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end or3;
architecture beh of or3 is
begin
y <= c or b or a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity or3a is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end or3a;
architecture beh of or3a is
signal ai : std_logic;
begin
ai <= not a;
y <= c or b or ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity or3b is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end or3b;
architecture beh of or3b is
signal ai : std_logic;
signal bi : std_logic;
begin
ai <= not a;
bi <= not b;
y <= c or bi or ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity or3c is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end or3c;
architecture beh of or3c is
signal ai : std_logic;
signal bi : std_logic;
signal ci : std_logic;
begin
ai <= not a;
bi <= not b;
ci <= not c;
y <= ci or bi or ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity or4 is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end or4;
architecture beh of or4 is
begin
y <= d or c or b or a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity or4a is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end or4a;
architecture beh of or4a is
signal ai : std_logic;
begin
ai <= not a;
y <= d or c or b or ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity or4b is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end or4b;
architecture beh of or4b is
signal ai : std_logic;
signal bi : std_logic;
begin
ai <= not a;
bi <= not b;
y <= d or c or bi or ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity or4c is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end or4c;
architecture beh of or4c is
signal ai : std_logic;
signal bi : std_logic;
signal ci : std_logic;
begin
ai <= not a;
bi <= not b;
ci <= not c;
y <= d or ci or bi or ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity or4d is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end or4d;
architecture beh of or4d is
signal ai : std_logic;
signal bi : std_logic;
signal ci : std_logic;
signal di : std_logic;
begin
ai <= not a;
bi <= not b;
ci <= not c;
di <= not d;
y <= di or ci or bi or ai;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity sub1 is
port(
a : in std_logic;
b : in std_logic;
fci : in std_logic;
s : out std_logic;
fco : out std_logic);
end sub1;
architecture beh of sub1 is
signal un1_b : std_logic;
signal un3_fco : std_logic;
signal un1_fco : std_logic;
signal un4_fco : std_logic;
begin
un1_b <= not b;
un3_fco <= a and fci;
s <= a xor fci xor un1_b;
un1_fco <= a and un1_b;
un4_fco <= fci and un1_b;
fco <= un1_fco or un3_fco or un4_fco;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity vcc is
port(
y : out std_logic);
end vcc;
architecture beh of vcc is
begin
y <= '1';
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity xa1 is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end xa1;
architecture beh of xa1 is
signal xab : std_logic;
begin
xab <= b xor a;
y <= c and xab;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity xnor2 is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end xnor2;
architecture beh of xnor2 is
signal yi : std_logic;
begin
yi <= b xor a;
y <= not yi;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity xor2 is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end xor2;
architecture beh of xor2 is
begin
y <= b xor a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity xor3 is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end xor3;
architecture beh of xor3 is
begin
y <= (c xor b) xor a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity xor4 is
port(a,b,c,d : in std_logic;
y : out std_logic);
end xor4;
architecture beh of xor4 is
signal xab, xcd : std_logic;
begin
xab <= b xor a;
xcd <= c xor d;
y <= xab xor xcd;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity xor4_fci is
port(a,b,c,fci : in std_logic;
y : out std_logic);
end xor4_fci;
architecture beh of xor4_fci is
signal xab, xcd : std_logic;
begin
xab <= b xor a;
xcd <= c xor fci;
y <= xab xor xcd;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity mx2 is
port(
a : in std_logic;
s : in std_logic;
b : in std_logic;
y : out std_logic);
end mx2;
architecture beh of mx2 is
signal xab : std_logic;
begin
y <= b when s = '0' else a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity mx4 is
port(
d0 : in std_logic;
s0 : in std_logic;
d1 : in std_logic;
s1 : in std_logic;
d2 : in std_logic;
d3 : in std_logic;
y : out std_logic);
end mx4;
architecture beh of mx4 is
begin
y <= d0 when (s1 = '0' and s0 = '0') else
d1 when (s1 = '0' and s0 = '1') else
d2 when (s1 = '1' and s0 = '0') else d3;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity bufd is
port(
a : in std_logic;
y : out std_logic);
end bufd;
architecture beh of bufd is
begin
y <= a;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity xai1 is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end xai1;
architecture beh of xai1 is
begin
y <= not (c and not (a xor b));
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity ax1c is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end ;
architecture beh of ax1c is
begin
y <= (a and b) xor c;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity ax1 is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end ax1;
architecture beh of ax1 is
begin
y <= (((not a) and b) xor c);
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity cy2a is
port(
a1 : in std_logic;
b1 : in std_logic;
a0 : in std_logic;
b0 : in std_logic;
y : out std_logic);
end cy2a;
architecture beh of cy2a is
begin
y <= ((( a1 AND b1 ) OR (( a0 AND b0 ) AND a1 )) OR (( a0 AND b0 ) AND b1 ));
end beh;
-- pragma translate_on
| mit | 95b69bdc5e75320bd5d149913fde3273 | 0.605713 | 2.769738 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/ddr/ddrrec.vhd | 2 | 19,211 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- File: ddrrec.vhd
-- Author: David Lindh - Gaisler Research
-- Description: DDR-RAM memory controller interface records
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use grlib.devices.all;
use gaisler.memctrl.all;
library techmap;
use techmap.gencomp.all;
use techmap.allmem.all;
package ddrrec is
-------------------------------------------------------------------------------
-- Options
-------------------------------------------------------------------------------
-- This can be changed
constant buffersize : integer := 4; -- Data buffer size, 2,4,8.,.-1024 (8 word) bursts
-------------------------------------------------------------------------------
-- Data sizes, should not haveto be changed
-------------------------------------------------------------------------------
type dm_arr is array(4 to 16) of integer;
constant dmvector : dm_arr := (2,others => 1);
constant maxdqsize : integer := 64;
constant maxdmsize : integer := 16;
constant maxstrobesize : integer := 16;
constant adrbits : integer := 16; -- BA + row/col address -1 (2+14-1)
constant ahbadr : integer := 32; -- AHB addressbits
constant ahbdata : integer := 32; -- AHB databits
constant bufferadr : integer := log2(buffersize)+2;
constant ddrcfg_reset : std_logic_vector(31 downto 0):=
'1' & --refresh
"00" & -- CAS
"00" & -- Memcmd
"10" & -- Burst length
'0' & -- Auto Precharge
"11" & -- Read prediction
"00" & -- Write protection
x"00000";
--Memory commands (RAS, CAS, WE)
constant CMD_READ : std_logic_vector(2 downto 0) := "101";
constant CMD_WRITE : std_logic_vector(2 downto 0) := "100";
constant CMD_NOP : std_logic_vector(2 downto 0) := "111";
constant CMD_ACTIVE : std_logic_vector(2 downto 0) := "011";
constant CMD_BT : std_logic_vector(2 downto 0) := "110";
constant CMD_PRE : std_logic_vector(2 downto 0) := "010";
constant CMD_AR : std_logic_vector(2 downto 0) := "001";
constant CMD_LMR : std_logic_vector(2 downto 0) := "000";
constant BANK0 : std_logic_vector(1 downto 0) := "10";
constant BANK1 : std_logic_vector(1 downto 0) := "01";
constant BANK01 : std_logic_vector(1 downto 0) := "00";
type burst_mask_type is array (buffersize-1 downto 0) of integer range 1 to 8;
type two_burst_mask_type is array (1 downto 0) of burst_mask_type;
type two_buf_adr_type is array (1 downto 0) of std_logic_vector((log2(buffersize)-1) downto 0);
type two_buf_data_type is array (1 downto 0) of std_logic_vector((bufferadr-1) downto 0);
type pre_row_type is array (7 downto 0) of std_logic_vector(adrbits-1 downto 0);
type two_ddr_adr_type is array (1 downto 0) of std_logic_vector(adrbits-1 downto 0);
type two_ddr_bank_type is array (1 downto 0) of std_logic_vector(1 downto 0);
type two_pre_bank_type is array (1 downto 0) of integer range 0 to 7;
type blwaittype is array (6 downto 0) of integer range 2 to 8;
type mlwaittype is array (1 downto 0) of integer range 1 to 8;
type bufwaittype is array (6 downto 0) of std_logic_vector((log2(buffersize)-1) downto 0);
type ahbwaittype is array (6 downto 0) of integer range 0 to 1;
-------------------------------------------------------------------------------
-- Records
-------------------------------------------------------------------------------
-- APB controller
type apb_ctrl_in_type is record
apbsi : apb_slv_in_type;
apb_cmd_done : std_ulogic;
ready : std_ulogic;
end record;
type apb_ctrl_out_type is record
apbso : apb_slv_out_type;
ddrcfg_reg : std_logic_vector(31 downto 0);
end record;
-------------------------------------------------------------------------------
-- Sync ram dp (data-fifo)
type syncram_dp_in_type is record
address1 : std_logic_vector((bufferadr -1) downto 0);
datain1 : std_logic_vector(2*(maxdqsize+maxdmsize)-1 downto 0);
enable1 : std_ulogic;
write1 : std_ulogic;
address2 : std_logic_vector((bufferadr-1) downto 0);
datain2 : std_logic_vector(2*(maxdqsize+maxdmsize)-1 downto 0);
enable2 : std_ulogic;
write2 : std_ulogic;
end record;
type syncram_dp_out_type is record
dataout1 : std_logic_vector(2*(maxdqsize+maxdmsize)-1 downto 0);
dataout2 : std_logic_vector(2*(maxdqsize+maxdmsize)-1 downto 0);
end record;
type two_syncram_dp_out_type is array (1 downto 0) of syncram_dp_out_type;
type two_syncram_dp_in_type is array (1 downto 0) of syncram_dp_in_type;
-------------------------------------------------------------------------------
-- Sync ram 2p (adr-fifo)
type syncram_2p_in_type is record
renable : std_ulogic;
raddress : std_logic_vector((log2(buffersize) -1) downto 0);
write : std_ulogic;
waddress : std_logic_vector((log2(buffersize)-1) downto 0);
datain : std_logic_vector((ahbadr-1+1) downto 0);
end record;
type syncram_2p_out_type is record
dataout : std_logic_vector((ahbadr-1+1) downto 0);
end record;
-----------------------------------------------------------------------------
-- High speed interface towards memory
type hs_in_type is record
bl : integer range 2 to 8;
ml : integer range 1 to 8;
cas : std_logic_vector(1 downto 0);
buf : std_logic_vector((log2(buffersize)-1) downto 0);
ahb : integer range 0 to 1;
cs : std_logic_vector(1 downto 0);
adr : std_logic_vector(adrbits-1 downto 0);
cmd : std_logic_vector(2 downto 0);
cmd_valid : std_ulogic;
dsramso : two_syncram_dp_out_type;
ddso : ddrmem_out_type;
end record;
type hs_out_type is record
hs_busy : std_ulogic;
cmdDone : two_buf_adr_type;
dsramsi : two_syncram_dp_in_type;
ddsi : ddrmem_in_type;
end record;
-----------------------------------------------------------------------------
-- AHB controller
type ahb_ctrl_in_type is record
ahbsi : ahb_slv_in_type;
asramsi : syncram_2p_in_type;
dsramsi : syncram_dp_in_type;
burstlength : integer range 2 to 8;
r_predict : std_ulogic;
w_prot : std_ulogic;
locked : std_ulogic;
rw_cmd_done : std_logic_vector((log2(buffersize) -1) downto 0);
end record;
type ahb_ctrl_out_type is record
ahbso : ahb_slv_out_type;
asramso : syncram_2p_out_type;
dsramso : syncram_dp_out_type;
rw_cmd_valid : std_logic_vector((log2(buffersize) -1) downto 0);
w_data_valid : std_logic_vector((log2(buffersize) -1) downto 0);
burst_dm : burst_mask_type;
end record;
type two_ahb_ctrl_out_type is array (1 downto 0) of ahb_ctrl_out_type;
type two_ahb_ctrl_in_type is array (1 downto 0) of ahb_ctrl_in_type;
-----------------------------------------------------------------------------
-- Main controller
type main_ctrl_in_type is record
apbctrlso : apb_ctrl_out_type;
ahbctrlso : two_ahb_ctrl_out_type;
hsso : hs_out_type;
end record;
type main_ctrl_out_type is record
apbctrlsi : apb_ctrl_in_type;
ahbctrlsi : two_ahb_ctrl_in_type;
hssi : hs_in_type;
end record;
-------------------------------------------------------------------------------
-- DDRCFG register
type config_out_type is record
refresh : std_ulogic;
cas : std_logic_vector(1 downto 0);
memcmd : std_logic_vector(1 downto 0);
bl : std_logic_vector(1 downto 0);
autopre : std_ulogic;
r_predict : std_logic_vector(1 downto 0);
w_prot : std_logic_vector(1 downto 0);
ready : std_ulogic;
end record;
-------------------------------------------------------------------------------
-- State machines
-------------------------------------------------------------------------------
type apbcycletype is (idle, refresh, cmd, wait_lmr1, wait_lmr2, cmdlmr, cmdDone, cmdDone2);
type timercycletype is (t1, t2, t3, t4);
type initcycletype is (idle, i1, i2, i3, i4, i5, i6, i7, i8, i9, i10, i11);
type maincycletype is (init, idle, pre1, act1, w1, r1, rw, c1, c2);
type rwcycletype is (idle, r, w);
type cmdbuffercycletype is (no_cmd, new_cmd);
type cmdcycletype is(idle, hold);
-----------------------------------------------------------------------------
-- AHB - Local variables
type ahb_reg_type is record
readcounter : integer range 0 to 8;
writecounter : integer range 0 to 8;
blockburstlength : integer range 0 to 8;
hready : std_ulogic;
hresp : std_logic_vector(1 downto 0);
rwadrbuffer : std_logic_vector((ahbadr-1) downto 0);
use_read_buffer : std_logic_vector((log2(buffersize)-1) downto 0);
pre_read_buffer : std_logic_vector((log2(buffersize)-1) downto 0);
pre_read_adr : std_logic_vector((ahbadr-1) downto 0);
pre_read_valid : std_ulogic;
use_write_buffer : std_logic_vector((log2(buffersize)-1) downto 0);
rw_cmd_valid : std_logic_vector((log2(buffersize)-1) downto 0);
w_data_valid : std_logic_vector((log2(buffersize)-1) downto 0);
sync_adr : std_logic_vector((bufferadr-1) downto 0);
sync_wdata : std_logic_vector(2*(maxdqsize+maxdmsize)-1 downto 0);
sync_write : std_ulogic;
sync_busy : std_ulogic;
sync_busy_adr : std_logic_vector((bufferadr-1) downto 0);
sync2_adr : std_logic_vector((log2(buffersize)-1) downto 0);
sync2_wdata : std_logic_vector((ahbadr-1+1) downto 0);
sync2_write : std_ulogic;
sync2_busy : std_ulogic;
doRead : std_ulogic;
doWrite : std_ulogic;
new_burst : std_ulogic;
startp : integer range 0 to 7;
ahbstartp : integer range 0 to 7;
even_odd_write : integer range 0 to 1;
burst_hsize : integer range 1 to 8;
offset : std_logic_vector(2 downto 0);
ahboffset : std_logic_vector(2 downto 0);
read_data : std_logic_vector(maxdqsize-1 downto 0);
cur_hrdata : std_logic_vector((ahbdata-1) downto 0);
cur_hready : std_ulogic;
cur_hresp : std_logic_vector(1 downto 0);
prev_retry : std_ulogic;
prev_error : std_ulogic;
burst_dm : burst_mask_type;
end record;
-------------------------------------------------------------------------------
-- APB controller - Local variables
type apb_reg_type is record
ddrcfg_reg : std_logic_vector(31 downto 0);
end record;
-------------------------------------------------------------------------------
-- High speed RW - Local variables
type rw_reg_type is record
cbufstate : cmdbuffercycletype;
cmdstate : cmdcycletype;
rwstate : rwcycletype;
cur_buf : two_buf_adr_type;
cur_ahb : integer range 0 to 1;
use_bl : integer range 2 to 8;
use_ml : integer range 1 to 8;
use_buf : std_logic_vector((log2(buffersize)-1) downto 0);
use_ahb : integer range 0 to 1;
use_cas : std_ulogic;
rw_cmd : std_logic_vector(2 downto 0);
rw_bl : integer range 2 to 8;
rw_cas : integer range 2 to 3;
next_bl : integer range 2 to 8;
next_ml : integer range 1 to 8;
next_buf : std_logic_vector((log2(buffersize)-1) downto 0);
next_ahb : integer range 0 to 1;
next_cas : std_logic_vector(1 downto 0);
next_adr : std_logic_vector(adrbits-1 downto 0);
next_cs : std_logic_vector(1 downto 0);
next_cmd : std_logic_vector(2 downto 0);
set_cmd : std_logic_vector(2 downto 0);
set_adr : std_logic_vector(adrbits-1 downto 0);
set_cs : std_logic_vector(1 downto 0);
set_cke : std_ulogic;
hs_busy : std_ulogic;
cmdDone : two_buf_adr_type;
begin_read : std_ulogic;
begin_write : std_ulogic;
dq_dqs_oe : std_ulogic;
w_ce : std_ulogic;
r_ce : std_ulogic;
cnt : integer range 0 to 8;
holdcnt : integer range 0 to 31;
r2wholdcnt : integer range 0 to 15;
act2precnt : integer range 0 to 15;
wait_time : integer range 0 to 31;
readwait : std_logic_vector(6 downto 0);
writewait : std_logic_vector(1 downto 0);
bufwait : bufwaittype;
ahbwait : ahbwaittype;
blwait : blwaittype;
mlwait : mlwaittype;
caswait : std_logic_vector(6 downto 0);
dm1_o : std_logic_vector((maxdmsize-1) downto 0);
dm2_o : std_logic_vector((maxdmsize-1) downto 0);
dqs1_o : std_ulogic;
sync_adr : two_buf_data_type;
sync_write : std_logic_vector(1 downto 0);
sync_wdata : std_logic_vector(2*(maxdqsize+maxdmsize)-1 downto 0);
end record;
-------------------------------------------------------------------------------
-- High speed CMD - Local variables
type cmd_reg_type is record
cur_cmd : std_logic_vector(2 downto 0);
cur_cs : std_logic_vector(1 downto 0);
cur_adr : std_logic_vector(adrbits-1 downto 0);
next_cmd : std_logic_vector(2 downto 0);
next_cs : std_logic_vector(1 downto 0);
next_adr : std_logic_vector(adrbits-1 downto 0);
end record;
-------------------------------------------------------------------------------
-- Main controller - Local variables
type main_reg_type is record
-- For main controller
mainstate : maincycletype;
loadcmdbuffer : std_ulogic;
cmdbufferdata : std_logic_vector(2 downto 0);
adrbufferdata : std_logic_vector(adrbits-1 downto 0);
use_ahb : integer range 0 to 1;
use_bl : integer range 2 to 8;
use_cas : std_logic_vector(1 downto 0);
use_buf : std_logic_vector((log2(buffersize)-1) downto 0);
burstlength : integer range 2 to 8;
rw_cmd_done : two_buf_adr_type;
lmradr : std_logic_vector(adrbits-1 downto 0);
memCmdDone : std_ulogic;
lockAHB : std_logic_vector(1 downto 0);
pre_row : pre_row_type;
pre_chg : std_logic_vector(7 downto 0);
pre_bankadr : two_pre_bank_type;
sync2_adr : two_buf_adr_type;
-- For init statemachine
initstate : initcycletype;
doMemInit : std_ulogic;
memInitDone : std_ulogic;
initDelay : integer range 0 to 255;
cs : std_logic_vector(1 downto 0);
-- For address calculator
coladdress : two_ddr_adr_type;
tmpcoladdress : two_ddr_adr_type;
rowaddress : two_ddr_adr_type;
addressrange : integer range 0 to 31;
tmpcolbits : integer range 0 to 15;
colbits : integer range 0 to 15;
rowbits : integer range 0 to 15;
bankselect : two_ddr_bank_type;
intbankbits : two_ddr_bank_type;
-- For refresh timer statemachine
timerstate : timercycletype;
doRefresh : std_ulogic;
refreshDone : std_ulogic;
refreshTime : integer range 0 to 4095;
maxRefreshTime : integer range 0 to 32767;
idlecnt : integer range 0 to 10;
refreshcnt : integer range 0 to 65535;
-- For DDRCFG register (APB)
apbstate : apbcycletype;
apb_cmd_done : std_ulogic;
ready : std_ulogic;
ddrcfg : config_out_type;
end record;
-------------------------------------------------------------------------------
-- Components
-------------------------------------------------------------------------------
component ahb_slv
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f80#;
sepclk : integer := 0;
dqsize : integer := 64;
dmsize : integer := 8;
tech : integer := virtex2);
port (
rst : in std_ulogic;
hclk : in std_ulogic;
clk0 : in std_ulogic;
csi : in ahb_ctrl_in_type;
cso : out ahb_ctrl_out_type);
end component;
component ddr_in
generic (
tech : integer);
port (
Q1 : out std_ulogic;
Q2 : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
-- DQS : in std_logic; -- used for lattice
-- DDRCLKPOL: in std_logic; -- used for lattice
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component ddr_out
generic (
tech : integer);
port (
Q : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component hs
generic(
tech : in integer;
dqsize : in integer;
dmsize : in integer;
strobesize: in integer;
clkperiod : in integer);
port (
rst : in std_ulogic;
clk0 : in std_ulogic;
clk90 : in std_ulogic;
clk180 : in std_ulogic;
clk270 : in std_ulogic;
hclk : in std_ulogic;
hssi : in hs_in_type;
hsso : out hs_out_type);
end component;
end ddrrec;
| mit | c695b7d8584e39b0792c7ae5fe61aee3 | 0.525272 | 3.737549 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/eth/core/greth_tx.vhd | 2 | 16,396 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: greth_tx
-- File: greth_tx.vhd
-- Author: Marko Isomaki
-- Description: Ethernet transmitter
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library eth;
use eth.grethpkg.all;
entity greth_tx is
generic(
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
nsync : integer range 1 to 2 := 2;
rmii : integer range 0 to 1 := 0);
port(
rst : in std_ulogic;
clk : in std_ulogic;
txi : in host_tx_type;
txo : out tx_host_type
);
end entity;
architecture rtl of greth_tx is
function mirror2(din : in std_logic_vector(3 downto 0))
return std_logic_vector is
variable do : std_logic_vector(3 downto 0);
begin
do(3) := din(0); do(2) := din(1);
do(1) := din(2); do(0) := din(3);
return do;
end function;
function init_ifg(
ifg_gap : in integer;
rmii : in integer)
return integer is
begin
if rmii = 0 then
return log2(ifg_gap);
else
return log2(ifg_gap*20);
end if;
end function;
constant maxattempts : std_logic_vector(4 downto 0) :=
conv_std_logic_vector(attempt_limit, 5);
--transmitter constants
constant ifg_bits : integer := init_ifg(ifg_gap, rmii);
constant ifg_p1 : std_logic_vector(ifg_bits-1 downto 0) :=
conv_std_logic_vector((ifg_gap)/3, ifg_bits);
constant ifg_p2 : std_logic_vector(ifg_bits-1 downto 0) :=
conv_std_logic_vector((ifg_gap*2)/3, ifg_bits);
constant ifg_p1_r100 : std_logic_vector(ifg_bits-1 downto 0) :=
conv_std_logic_vector((ifg_gap*2)/3, ifg_bits);
constant ifg_p2_r100 : std_logic_vector(ifg_bits-1 downto 0) :=
conv_std_logic_vector(rmii*(ifg_gap*4)/3, ifg_bits);
constant ifg_p1_r10 : std_logic_vector(ifg_bits-1 downto 0) :=
conv_std_logic_vector(rmii*(ifg_gap*20)/3, ifg_bits);
constant ifg_p2_r10 : std_logic_vector(ifg_bits-1 downto 0) :=
conv_std_logic_vector(rmii*(ifg_gap*40)/3, ifg_bits);
function ifg_sel(
rmii : in integer;
p1 : in integer;
speed : in std_ulogic)
return std_logic_vector is
begin
if p1 = 1 then
if rmii = 0 then
return ifg_p1;
else
if speed = '1' then
return ifg_p1_r100;
else
return ifg_p1_r10;
end if;
end if;
else
if rmii = 0 then
return ifg_p2;
else
if speed = '1' then
return ifg_p2_r100;
else
return ifg_p2_r10;
end if;
end if;
end if;
end function;
--transmitter types
type tx_state_type is (idle, preamble, sfd, data1, data2, pad1, pad2, fcs,
fcs2, finish, calc_backoff, wait_backoff, send_jam, send_jam2,
check_attempts);
type def_state_type is (monitor, def_on, ifg1, ifg2, frame_waitingst);
type tx_reg_type is record
--deference process
def_state : def_state_type;
ifg_cycls : std_logic_vector(ifg_bits-1 downto 0);
deferring : std_ulogic;
was_transmitting : std_ulogic;
--tx process
main_state : tx_state_type;
transmitting : std_ulogic;
tx_en : std_ulogic;
txd : std_logic_vector(3 downto 0);
cnt : std_logic_vector(3 downto 0);
icnt : std_logic_vector(1 downto 0);
crc : std_logic_vector(31 downto 0);
crc_en : std_ulogic;
byte_count : std_logic_vector(10 downto 0);
slot_count : std_logic_vector(6 downto 0);
random : std_logic_vector(9 downto 0);
delay_val : std_logic_vector(9 downto 0);
retry_cnt : std_logic_vector(4 downto 0);
status : std_logic_vector(1 downto 0);
data : std_logic_vector(31 downto 0);
--synchronization
read : std_ulogic;
done : std_ulogic;
restart : std_ulogic;
start : std_logic_vector(nsync downto 0);
read_ack : std_logic_vector(nsync-1 downto 0);
crs : std_logic_vector(1 downto 0);
col : std_logic_vector(1 downto 0);
fullduplex : std_logic_vector(1 downto 0);
--rmii
crs_act : std_ulogic;
crs_prev : std_ulogic;
speed : std_logic_vector(1 downto 0);
rcnt : std_logic_vector(3 downto 0);
switch : std_ulogic;
txd_msb : std_logic_vector(1 downto 0);
zero : std_ulogic;
rmii_crc_en : std_ulogic;
end record;
--transmitter signals
signal r, rin : tx_reg_type;
signal txrst : std_ulogic;
signal vcc : std_ulogic;
attribute sync_set_reset : string;
attribute sync_set_reset of txrst : signal is "true";
begin
vcc <= '1';
tx_rst : eth_rstgen
port map(rst, clk, vcc, txrst, open);
tx : process(txrst, r, txi) is
variable collision : std_ulogic;
variable frame_waiting : std_ulogic;
variable index : integer range 0 to 7;
variable start : std_ulogic;
variable read_ack : std_ulogic;
variable v : tx_reg_type;
variable crs : std_ulogic;
variable col : std_ulogic;
variable tx_done : std_ulogic;
begin
v := r; frame_waiting := '0'; tx_done := '0'; v.rmii_crc_en := '0';
--synchronization
v.col(1) := r.col(0); v.col(0) := txi.rx_col;
v.crs(1) := r.crs(0); v.crs(0) := txi.rx_crs;
v.fullduplex(0) := txi.full_duplex;
v.fullduplex(1) := r.fullduplex(0);
v.start(0) := txi.start;
v.read_ack(0) := txi.readack;
if nsync = 2 then
v.start(1) := r.start(0);
v.read_ack(1) := r.read_ack(0);
end if;
start := r.start(nsync) xor r.start(nsync-1);
read_ack := not (r.read xor r.read_ack(nsync-1));
--crc generation
if (r.crc_en = '1') and ((rmii = 0) or (r.rmii_crc_en = '1')) then
v.crc := calccrc(r.txd, r.crc);
end if;
--rmii
if rmii = 0 then
col := r.col(1); crs := r.crs(1);
tx_done := '1';
else
v.crs_prev := r.crs(1);
if (r.crs(0) and not r.crs_act) = '1' then
v.crs_act := '1';
end if;
if (r.crs(1) or r.crs(0)) = '0' then
v.crs_act := '0';
end if;
crs := r.crs(1) and not ((not r.crs_prev) and r.crs_act);
col := crs and r.tx_en;
v.speed(1) := r.speed(0); v.speed(0) := txi.speed;
if r.tx_en = '1' then
v.rcnt := r.rcnt - 1;
if r.speed(1) = '1' then
v.switch := not r.switch;
if r.switch = '1' then
tx_done := '1'; v.rmii_crc_en := '1';
end if;
if r.switch = '0' then
v.txd(1 downto 0) := r.txd_msb;
end if;
else
v.zero := '0';
if r.rcnt = "0001" then
v.zero := '1';
end if;
if r.zero = '1' then
v.switch := not r.switch;
v.rcnt := "1001";
if r.switch = '0' then
v.txd(1 downto 0) := r.txd_msb;
end if;
end if;
if (r.switch and r.zero) = '1' then
tx_done := '1'; v.rmii_crc_en := '1';
end if;
end if;
end if;
end if;
collision := col and not r.fullduplex(1);
--main fsm
case r.main_state is
when idle =>
v.transmitting := '0';
if rmii = 1 then
v.rcnt := "1001"; v.switch := '0';
end if;
if (start and not r.deferring) = '1' then
v.main_state := preamble; v.transmitting := '1'; v.tx_en := '1';
v.byte_count := (others => '1'); v.status := (others => '0');
v.read := not r.read; v.start(nsync) := r.start(nsync-1);
elsif start = '1' then
frame_waiting := '1';
end if;
v.txd := "0101"; v.cnt := "1110";
when preamble =>
if tx_done = '1' then
v.cnt := r.cnt - 1;
if r.cnt = "0000" then
v.txd := "1101"; v.main_state := sfd;
end if;
if collision = '1' then v.main_state := send_jam; end if;
end if;
when sfd =>
if tx_done = '1' then
v.main_state := data1; v.icnt := (others => '0'); v.crc_en := '1';
v.crc := (others => '1'); v.byte_count := (others => '0');
v.txd := txi.data(27 downto 24);
if (read_ack and txi.valid) = '0' then
v.status(0) := '1'; v.main_state := finish; v.tx_en := '0';
else
v.data := txi.data; v.read := not r.read;
end if;
if collision = '1' then v.main_state := send_jam; end if;
end if;
when data1 =>
index := conv_integer(r.icnt);
if tx_done = '1' then
v.byte_count := r.byte_count + 1;
v.main_state := data2; v.icnt := r.icnt + 1;
case index is
when 0 => v.txd := r.data(31 downto 28);
when 1 => v.txd := r.data(23 downto 20);
when 2 => v.txd := r.data(15 downto 12);
when 3 => v.txd := r.data(7 downto 4);
when others => null;
end case;
if v.byte_count = txi.len then
v.tx_en := '1';
if conv_integer(v.byte_count) >= 60 then
v.main_state := fcs; v.cnt := (others => '0');
else
v.main_state := pad1;
end if;
elsif index = 3 then
if (read_ack and txi.valid) = '0' then
v.status(0) := '1'; v.main_state := finish; v.tx_en := '0';
else
v.data := txi.data; v.read := not r.read;
end if;
end if;
if collision = '1' then v.main_state := send_jam; end if;
end if;
when data2 =>
index := conv_integer(r.icnt);
if tx_done = '1' then
v.main_state := data1;
case index is
when 0 => v.txd := r.data(27 downto 24);
when 1 => v.txd := r.data(19 downto 16);
when 2 => v.txd := r.data(11 downto 8);
when 3 => v.txd := r.data(3 downto 0);
when others => null;
end case;
if collision = '1' then v.main_state := send_jam; end if;
end if;
when pad1 =>
if tx_done = '1' then
v.main_state := pad2;
if collision = '1' then v.main_state := send_jam; end if;
end if;
when pad2 =>
if tx_done = '1' then
v.byte_count := r.byte_count + 1;
if conv_integer(v.byte_count) = 60 then
v.main_state := fcs; v.cnt := (others => '0');
else
v.main_state := pad1;
end if;
if collision = '1' then v.main_state := send_jam; end if;
end if;
when fcs =>
if tx_done = '1' then
v.cnt := r.cnt + 1; v.crc_en := '0'; index := conv_integer(r.cnt);
case index is
when 0 => v.txd := mirror2(not v.crc(31 downto 28));
when 1 => v.txd := mirror2(not r.crc(27 downto 24));
when 2 => v.txd := mirror2(not r.crc(23 downto 20));
when 3 => v.txd := mirror2(not r.crc(19 downto 16));
when 4 => v.txd := mirror2(not r.crc(15 downto 12));
when 5 => v.txd := mirror2(not r.crc(11 downto 8));
when 6 => v.txd := mirror2(not r.crc(7 downto 4));
when 7 => v.txd := mirror2(not r.crc(3 downto 0));
v.main_state := fcs2;
when others => null;
end case;
end if;
when fcs2 =>
if tx_done = '1' then
v.main_state := finish; v.tx_en := '0';
end if;
when finish =>
v.tx_en := '0'; v.transmitting := '0'; v.main_state := idle;
v.retry_cnt := (others => '0'); v.done := not r.done;
when send_jam =>
if tx_done = '1' then
v.cnt := "0110"; v.main_state := send_jam2; v.crc_en := '0';
end if;
when send_jam2 =>
if tx_done = '1' then
v.cnt := r.cnt - 1;
if r.cnt = "0000" then
v.main_state := check_attempts; v.retry_cnt := r.retry_cnt + 1;
v.tx_en := '0';
end if;
end if;
when check_attempts =>
v.transmitting := '0';
if r.retry_cnt = maxattempts then
v.main_state := finish; v.status(1) := '1';
else
v.main_state := calc_backoff; v.restart := not r.restart;
end if;
v.tx_en := '0';
when calc_backoff =>
v.delay_val := (others => '0');
for i in 1 to backoff_limit-1 loop
if i < conv_integer(r.retry_cnt)+1 then
v.delay_val(i) := r.random(i);
end if;
end loop;
v.main_state := wait_backoff; v.slot_count := (others => '1');
when wait_backoff =>
if conv_integer(r.delay_val) = 0 then
v.main_state := idle;
end if;
v.slot_count := r.slot_count - 1;
if conv_integer(r.slot_count) = 0 then
v.slot_count := (others => '1'); v.delay_val := r.delay_val - 1;
end if;
when others =>
v.main_state := idle;
end case;
--random values;
v.random := r.random(8 downto 0) & (not (r.random(2) xor r.random(9)));
--deference
case r.def_state is
when monitor =>
v.was_transmitting := '0';
if ( (crs and not r.fullduplex(1)) or
(r.transmitting and r.fullduplex(1)) ) = '1' then
v.deferring := '1'; v.def_state := def_on;
v.was_transmitting := r.transmitting;
end if;
when def_on =>
v.was_transmitting := r.was_transmitting or r.transmitting;
if r.fullduplex(1) = '1' then
if r.transmitting = '0' then v.def_state := ifg1; end if;
v.ifg_cycls := ifg_sel(rmii, 1, r.speed(1));
else
if (r.transmitting or crs) = '0' then
v.def_state := ifg1; v.ifg_cycls := ifg_sel(rmii, 1, r.speed(1));
end if;
end if;
when ifg1 =>
v.ifg_cycls := r.ifg_cycls - 1;
if r.ifg_cycls = zero32(ifg_bits-1 downto 0) then
v.def_state := ifg2;
v.ifg_cycls := ifg_sel(rmii, 0, r.speed(1));
elsif (crs and not r.fullduplex(1)) = '1' then
v.ifg_cycls := ifg_sel(rmii, 1, r.speed(1));
end if;
when ifg2 =>
v.ifg_cycls := r.ifg_cycls - 1;
if r.ifg_cycls = zero32(ifg_bits-1 downto 0) then
v.deferring := '0';
if (r.fullduplex(1) or not frame_waiting) = '1' then
v.def_state := monitor;
elsif frame_waiting = '1' then
v.def_state := frame_waitingst;
end if;
end if;
when frame_waitingst =>
if frame_waiting = '0' then v.def_state := monitor; end if;
when others => v.def_state := monitor;
end case;
if rmii = 1 then
v.txd_msb := v.txd(3 downto 2);
end if;
if txrst = '0' then
v.main_state := idle; v.random := (others => '0');
v.def_state := monitor; v.deferring := '0'; v.tx_en := '0';
v.done := '0'; v.restart := '0'; v.read := '0';
v.start := (others => '0'); v.read_ack := (others => '0');
v.icnt := (others => '0'); v.delay_val := (others => '0');
v.ifg_cycls := (others => '0');
if rmii = 1 then
v.crs_act := '0';
end if;
end if;
rin <= v;
txo.tx_er <= '0';
txo.tx_en <= r.tx_en;
txo.txd <= r.txd;
txo.done <= r.done;
txo.read <= r.read;
txo.restart <= r.restart;
txo.status <= r.status;
end process;
txregs : process(clk) is
begin
if rising_edge(clk) then r <= rin; end if;
end process;
end architecture;
| mit | 17542f3d89eeec9dc76aaeaa10332d9d | 0.519334 | 3.189263 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/memAttack/lib/gaisler/leon3/libiu.vhd | 1 | 9,180 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: libiu
-- File: libiu.vhd
-- Author: Jiri Gaisler Gaisler Research
-- Description: LEON3 IU types and components
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.leon3.all;
use gaisler.arith.all;
use gaisler.mmuconfig.all;
--library fpu;
--use fpu.libfpu.all;
package libiu is
constant RDBITS : integer := 32;
constant IDBITS : integer := 32;
subtype cword is std_logic_vector(IDBITS-1 downto 0);
type cdatatype is array (0 to 3) of cword;
--type ctagpartype is array (0 to 3) of std_logic_vector(1 downto 0);
--type cdatapartype is array (0 to 3) of std_logic_vector(3 downto 0);
--type cvalidtype is array (0 to 3) of std_logic_vector(7 downto 0);
type cpartype is array (0 to 3) of std_logic_vector(3 downto 0); -- byte parity
type iregfile_in_type is record
raddr1 : std_logic_vector(9 downto 0); -- read address 1
raddr2 : std_logic_vector(9 downto 0); -- read address 2
waddr : std_logic_vector(9 downto 0); -- write address
wdata : std_logic_vector(31 downto 0); -- write data
ren1 : std_ulogic; -- read 1 enable
ren2 : std_ulogic; -- read 2 enable
wren : std_ulogic; -- write enable
diag : std_logic_vector(3 downto 0); -- write data
end record;
type iregfile_out_type is record
data1 : std_logic_vector(RDBITS-1 downto 0); -- read data 1
data2 : std_logic_vector(RDBITS-1 downto 0); -- read data 2
end record;
type cctrltype is record
burst : std_ulogic; -- icache burst enable
dfrz : std_ulogic; -- dcache freeze enable
ifrz : std_ulogic; -- icache freeze enable
dsnoop : std_ulogic; -- data cache snooping
dcs : std_logic_vector(1 downto 0); -- dcache state
ics : std_logic_vector(1 downto 0); -- icache state
end record;
type icache_in_type is record
rpc : std_logic_vector(31 downto 0); -- raw address (npc)
fpc : std_logic_vector(31 downto 0); -- latched address (fpc)
dpc : std_logic_vector(31 downto 0); -- latched address (dpc)
rbranch : std_ulogic; -- Instruction branch
fbranch : std_ulogic; -- Instruction branch
inull : std_ulogic; -- instruction nullify
su : std_ulogic; -- super-user
flush : std_ulogic; -- flush icache
flushl : std_ulogic; -- flush line
fline : std_logic_vector(31 downto 3); -- flush line offset
pnull : std_ulogic;
end record;
type icache_out_type is record
data : cdatatype;
set : std_logic_vector(1 downto 0);
mexc : std_ulogic;
hold : std_ulogic;
flush : std_ulogic; -- flush in progress
diagrdy : std_ulogic; -- diagnostic access ready
diagdata : std_logic_vector(IDBITS-1 downto 0);-- diagnostic data
mds : std_ulogic; -- memory data strobe
cfg : std_logic_vector(31 downto 0);
idle : std_ulogic; -- idle mode
end record;
type icdiag_in_type is record
addr : std_logic_vector(31 downto 0); -- memory stage address
enable : std_ulogic;
read : std_ulogic;
tag : std_ulogic;
ctx : std_ulogic;
flush : std_ulogic;
ilramen : std_ulogic;
cctrl : cctrltype;
pflush : std_ulogic;
pflushaddr : std_logic_vector(VA_I_U downto VA_I_D);
pflushtyp : std_ulogic;
ilock : std_logic_vector(0 to 3);
scanen : std_ulogic;
end record;
type dcache_in_type is record
asi : std_logic_vector(7 downto 0);
maddress : std_logic_vector(31 downto 0);
eaddress : std_logic_vector(31 downto 0);
edata : std_logic_vector(31 downto 0);
size : std_logic_vector(1 downto 0);
enaddr : std_ulogic;
eenaddr : std_ulogic;
nullify : std_ulogic;
lock : std_ulogic;
read : std_ulogic;
write : std_ulogic;
flush : std_ulogic;
flushl : std_ulogic; -- flush line
dsuen : std_ulogic;
msu : std_ulogic; -- memory stage supervisor
esu : std_ulogic; -- execution stage supervisor
intack : std_ulogic;
end record;
type dcache_out_type is record
data : cdatatype;
set : std_logic_vector(1 downto 0);
mexc : std_ulogic;
hold : std_ulogic;
mds : std_ulogic;
werr : std_ulogic;
icdiag : icdiag_in_type;
cache : std_ulogic;
idle : std_ulogic; -- idle mode
scanen : std_ulogic;
testen : std_ulogic;
end record;
type tracebuf_in_type is record
addr : std_logic_vector(11 downto 0);
data : std_logic_vector(127 downto 0);
enable : std_logic;
write : std_logic_vector(3 downto 0);
diag : std_logic_vector(3 downto 0);
end record;
type tracebuf_out_type is record
data : std_logic_vector(127 downto 0);
end record;
component iu3
generic (
nwin : integer range 2 to 32 := 8;
isets : integer range 1 to 4 := 1;
dsets : integer range 1 to 4 := 1;
fpu : integer range 0 to 15 := 0;
v8 : integer range 0 to 63 := 0;
cp, mac : integer range 0 to 1 := 0;
dsu : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
index : integer range 0 to 15:= 0;
lddel : integer range 1 to 2 := 2;
irfwt : integer range 0 to 1 := 0;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0; -- trace buf size in kB (0 - no trace buffer)
pwd : integer range 0 to 2 := 0; -- power-down
svt : integer range 0 to 1 := 0; -- single-vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0; -- support SMP systems
fabtech : integer range 0 to NTECH := 0;
clk2x : integer := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
holdn : in std_ulogic;
ici : out icache_in_type;
ico : in icache_out_type;
dci : out dcache_in_type;
dco : in dcache_out_type;
rfi : out iregfile_in_type;
rfo : in iregfile_out_type;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
muli : out mul32_in_type;
mulo : in mul32_out_type;
divi : out div32_in_type;
divo : in div32_out_type;
fpo : in fpc_out_type;
fpi : out fpc_in_type;
cpo : in fpc_out_type;
cpi : out fpc_in_type;
tbo : in tracebuf_out_type;
tbi : out tracebuf_in_type;
sclk : in std_ulogic
);
end component;
component tbufmem
generic (
tech : integer := 0;
tbuf : integer := 0
);
port (
clk : in std_ulogic;
di : in tracebuf_in_type;
do : out tracebuf_out_type);
end component;
-- disassembly dummy module
component cpu_disasx is
port (
clk : in std_ulogic;
rstn : in std_ulogic;
dummy : out std_ulogic;
inst : in std_logic_vector(31 downto 0);
pc : in std_logic_vector(31 downto 2);
result: in std_logic_vector(31 downto 0);
index : in std_logic_vector(3 downto 0);
wreg : in std_ulogic;
annul : in std_ulogic;
holdn : in std_ulogic;
pv : in std_ulogic;
trap : in std_ulogic;
disas : in std_ulogic);
end component;
end;
| mit | 2f5f6a2f82cb2e75f907332cedba2ab2 | 0.547386 | 3.648649 | false | false | false | false |
michaelfivez/ascon_hardware_implementation | ascon128128_unrolled2/Kernel/Ascon_block_control.vhd | 1 | 7,312 | -------------------------------------------------------------------------------
--! @project Unrolled (factor 2) hardware implementation of Asconv128128
--! @author Michael Fivez
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is an hardware implementation made for my graduation thesis
--! at the KULeuven, in the COSIC department (year 2015-2016)
--! The thesis is titled 'Energy efficient hardware implementations of CAESAR submissions',
--! and can be found on the COSIC website (www.esat.kuleuven.be/cosic/publications)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Ascon_StateUpdate_control is
port(
Clk : in std_logic; -- Clock
Reset : in std_logic; -- Reset (synchronous)
-- Control signals
RoundNr : out std_logic_vector(2 downto 0);
sel1,sel2,sel3,sel4 : out std_logic_vector(1 downto 0);
sel0 : out std_logic_vector(2 downto 0);
selout : out std_logic;
Reg0En,Reg1En,Reg2En,Reg3En,Reg4En,RegOutEn : out std_logic;
ActivateGen : out std_logic;
GenSize : out std_logic_vector(3 downto 0);
-- External control signals
Start : in std_logic;
Mode : in std_logic_vector(3 downto 0);
Size : in std_logic_vector(3 downto 0); -- only matters for last block decryption
Busy : out std_logic
);
end entity Ascon_StateUpdate_control;
architecture structural of Ascon_StateUpdate_control is
begin
-----------------------------------------
------ The Finite state machine --------
-----------------------------------------
-- Modes: initialization, associative data, encryption, decryption, tag generation, final encryption, final decryption, seperation constant
-- 0010 0000 0110 0100 0001 0111 0101, 0011
-- case1 1000, case2 1001
fsm: process(Clk, Reset) is
type state_type is (IDLE,LOADNEW,CRYPT,TAG);
variable CurrState : state_type := IDLE;
variable RoundNrVar : std_logic_vector(2 downto 0);
begin
if Clk'event and Clk = '1' then
-- default values
sel0 <= "000";
sel1 <= "00";
sel2 <= "00";
sel3 <= "00";
sel4 <= "00";
selout <= '0';
Reg0En <= '0';
Reg1En <= '0';
Reg2En <= '0';
Reg3En <= '0';
Reg4En <= '0';
RegOutEn <= '0';
ActivateGen <= '0';
GenSize <= "0000";
Busy <= '0';
if Reset = '1' then -- synchronous reset active high
-- registers used by fsm:
RoundNrVar := "000";
CurrState := IDLE;
else
FSMlogic : case CurrState is
when IDLE =>
if Start = '1' then
Busy <= '1';
if Mode = "0000" then -- AD mode
RoundNrVar := "111"; -- so starts at 0 next cycle
-- set Sel and Enables signal (Xor with DataIn)
sel0 <= "010";
sel1 <= "10";
Reg0En <= '1';
Reg1En <= '1';
CurrState := CRYPT;
elsif Mode = "0100" then -- Decryption mode
RoundNrVar := "111"; -- so starts at 0 next cycle
-- set Sel and Enables signal (Generate output and xor state)
ActivateGen <= '1';
sel0 <= "010";
sel1 <= "10";
Reg0En <= '1';
Reg1En <= '1';
RegOutEn <= '1';
CurrState := CRYPT;
elsif Mode = "0110" then -- Encryption
RoundNrVar := "111"; -- so starts at 0 next cycle
-- set Sel and Enables signal (Generate output and xor state)
sel0 <= "010";
sel1 <= "10";
Reg0En <= '1';
Reg1En <= '1';
RegOutEn <= '1';
CurrState := CRYPT;
elsif Mode = "0001" then -- Tag mode
RoundNrVar := "111"; -- so starts at 0 next cycle
-- set Sel and Enables signal (XOR middle with key)
sel2 <= "10";
sel3 <= "11";
Reg2En <= '1';
Reg3En <= '1';
CurrState := TAG;
elsif Mode = "0111" then -- Last block encryption
-- set Sel and Enables signal (Generate output and xor state)
sel0 <= "010";
sel1 <= "10";
Reg0En <= '1';
Reg1En <= '1';
RegOutEn <= '1';
CurrState := IDLE;
elsif Mode = "0101" then -- Last block decryption
-- set Sel and Enables signal (Generate output and xor state)
ActivateGen <= '1';
GenSize <= Size;
sel0 <= "010";
sel1 <= "10";
Reg0En <= '1';
Reg1En <= '1';
RegOutEn <= '1';
CurrState := IDLE;
elsif Mode = "0011" then -- Seperation constant
sel4 <= "11";
Reg4En <= '1';
CurrState := IDLE;
elsif Mode = "0010" then -- Initialization mode
RoundNrVar := "111"; -- so starts at 0 next cycle
-- set Sel and Enables signal (Load in key and IV)
sel0 <= "001";
sel1 <= "01";
sel2 <= "01";
sel3 <= "01";
sel4 <= "01";
Reg0En <= '1';
Reg1En <= '1';
Reg2En <= '1';
Reg3En <= '1';
Reg4En <= '1';
CurrState := LOADNEW;
elsif Mode = "1000" then -- case1
sel0 <= "100";
Reg0En <= '1';
CurrState := IDLE;
else -- case2
sel0 <= "100";
Reg0En <= '1';
RoundNrVar := "111"; -- so starts at 0 next cycle
CurrState := CRYPT;
end if;
else
Busy <= '0';
CurrState := IDLE;
end if;
when LOADNEW =>
if RoundNrVar = "101" then -- RoundNrVar = 5 (101x, 1010 and 1011)
-- set Sel and Enables signal (Xor at the end)
sel3 <= "10";
sel4 <= "10";
Reg3En <= '1';
Reg4En <= '1';
CurrState := IDLE;
Busy <= '0';
else
RoundNrVar := std_logic_vector(unsigned(RoundNrVar) + 1);
-- set Sel and Enables signal (execute a round)
Reg0En <= '1';
Reg1En <= '1';
Reg2En <= '1';
Reg3En <= '1';
Reg4En <= '1';
CurrState := LOADNEW;
Busy <= '1';
end if;
when CRYPT =>
if RoundNrVar = "010" then -- RoundNrVar = 3 (011x, 1010 and 1011 will be done)
RoundNrVar := std_logic_vector(unsigned(RoundNrVar) + 1);
-- set Sel and Enables signal (execute a round)
Reg0En <= '1';
Reg1En <= '1';
Reg2En <= '1';
Reg3En <= '1';
Reg4En <= '1';
CurrState := IDLE;
Busy <= '0';
else
RoundNrVar := std_logic_vector(unsigned(RoundNrVar) + 1);
-- set Sel and Enables signal (execute a round)
Reg0En <= '1';
Reg1En <= '1';
Reg2En <= '1';
Reg3En <= '1';
Reg4En <= '1';
CurrState := CRYPT;
Busy <= '1';
end if;
when TAG =>
if RoundNrVar = "101" then -- RoundNrVar = 5 (101x, 1010 and 1011)
-- set Sel and Enables signal (connect tag to output)
selout <= '1';
RegOutEn <= '1';
CurrState := IDLE;
Busy <= '0';
else
RoundNrVar := std_logic_vector(unsigned(RoundNrVar) + 1);
-- set Sel and Enables signal (execute a round)
Reg0En <= '1';
Reg1En <= '1';
Reg2En <= '1';
Reg3En <= '1';
Reg4En <= '1';
CurrState := TAG;
Busy <= '1';
end if;
end case FSMlogic;
RoundNr <= RoundNrVar;
end if;
end if;
end process fsm;
end architecture structural;
| gpl-3.0 | f0efb811f46f15e68538bb7c7a218fac | 0.535421 | 3.181897 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/techmap/unisim/ddr_phy_unisim.vhd | 1 | 68,611 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: various
-- File: clkgen_xilinx.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: DDR PHY for Virtex-2 and Virtex-4
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
-- pragma translate_off
library unisim;
use unisim.BUFG;
use unisim.DCM;
use unisim.ODDR;
use unisim.FD;
use unisim.IDDR;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
------------------------------------------------------------------
-- Virtex4 DDR PHY -----------------------------------------------
------------------------------------------------------------------
entity virtex4_ddr_phy is
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ;
clk_div : integer := 2; rskew : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (13 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0)
);
end;
architecture rtl of virtex4_ddr_phy is
component DCM
generic (
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false
);
port (
CLKFB : in std_logic;
CLKIN : in std_logic;
DSSEN : in std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector (7 downto 0));
end component;
component BUFG port (O : out std_logic; I : in std_logic); end component;
component ODDR
generic
( DDR_CLK_EDGE : string := "OPPOSITE_EDGE";
-- INIT : bit := '0';
SRTYPE : string := "SYNC");
port
(
Q : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end component;
component FD
generic ( INIT : bit := '0');
port ( Q : out std_ulogic;
C : in std_ulogic;
D : in std_ulogic);
end component;
component IDDR
generic ( DDR_CLK_EDGE : string := "SAME_EDGE";
INIT_Q1 : bit := '0';
INIT_Q2 : bit := '0';
SRTYPE : string := "ASYNC");
port
( Q1 : out std_ulogic;
Q2 : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
signal vcc, gnd, dqsn, oe, lockl : std_ulogic;
signal ddr_clk_fb_outr : std_ulogic;
signal ddr_clk_fbl, fbclk : std_ulogic;
signal ddr_rasnr, ddr_casnr, ddr_wenr : std_ulogic;
signal ddr_clkl, ddr_clkbl : std_logic_vector(2 downto 0);
signal ddr_csnr, ddr_ckenr, ckel : std_logic_vector(1 downto 0);
signal clk_0ro, clk_90ro, clk_180ro, clk_270ro : std_ulogic;
signal clk_0r, clk_90r, clk_180r, clk_270r : std_ulogic;
signal clk0r, clk90r, clk180r, clk270r : std_ulogic;
signal locked, vlockl, ddrclkfbl, dllfb : std_ulogic;
signal ddr_dqin : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqout : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqoen : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_adr : std_logic_vector (13 downto 0); -- ddr address
signal ddr_bar : std_logic_vector (1 downto 0); -- ddr address
signal ddr_dmr : std_logic_vector (dbits/8-1 downto 0); -- ddr address
signal ddr_dqsin : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoen : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoutl : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal dqsdel, dqsclk : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal da : std_logic_vector (dbits-1 downto 0); -- ddr data
signal dqinl : std_logic_vector (dbits-1 downto 0); -- ddr data
signal dllrst : std_logic_vector(0 to 3);
signal dll0rst, dll2rst : std_logic_vector(0 to 3);
signal mlock, mclkfb, mclk, mclkfx, mclk0 : std_ulogic;
signal rclk270b, rclk90b, rclk0b : std_ulogic;
signal rclk270, rclk90, rclk0 : std_ulogic;
constant DDR_FREQ : integer := (MHz * clk_mul) / clk_div;
attribute keep : boolean;
attribute keep of rclk90b : signal is true;
attribute syn_keep : boolean;
attribute syn_keep of rclk90b : signal is true;
attribute syn_preserve : boolean;
attribute syn_preserve of rclk90b : signal is true;
begin
oe <= not oen;
vcc <= '1'; gnd <= '0';
-- Optional DDR clock multiplication
noclkscale : if clk_mul = clk_div generate
mclk <= clk;
end generate;
clkscale : if clk_mul /= clk_div generate
rstdel : process (clk, rst)
begin
if rst = '0' then dll0rst <= (others => '1');
elsif rising_edge(clk) then
dll0rst <= dll0rst(1 to 3) & '0';
end if;
end process;
bufg0 : BUFG port map (I => mclkfx, O => mclk);
bufg1 : BUFG port map (I => mclk0, O => mclkfb);
dllm : DCM
generic map (CLKFX_MULTIPLY => clk_mul, CLKFX_DIVIDE => clk_div)
port map ( CLKIN => clk, CLKFB => mclkfb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst(0), CLK0 => mclk0,
LOCKED => mlock, CLKFX => mclkfx );
end generate;
-- DDR clock generation
ddrref_pad : clkpad generic map (tech => virtex4)
port map (ddr_clk_fb, ddrclkfbl);
bufg1 : BUFG port map (I => clk_0ro, O => clk_0r);
-- bufg2 : BUFG port map (I => clk_90ro, O => clk_90r);
clk_90r <= not clk_270r;
-- bufg3 : BUFG port map (I => clk_180ro, O => clk_180r);
clk_180r <= not clk_0r;
bufg4 : BUFG port map (I => clk_270ro, O => clk_270r);
clkout <= clk_270r; clk0r <= clk_270r; clk90r <= clk_0r;
clk180r <= clk_90r; clk270r <= clk_180r;
dllfb <= clk_0r;
dll : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2)
port map ( CLKIN => mclk, CLKFB => dllfb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dllrst(0), CLK0 => clk_0ro,
CLK90 => clk_90ro, CLK180 => clk_180ro, CLK270 => clk_270ro,
LOCKED => lockl);
rstdel : process (mclk, rst)
begin
if rst = '0' then dllrst <= (others => '1');
elsif rising_edge(mclk) then
dllrst <= dllrst(1 to 3) & '0';
end if;
end process;
rdel : if rstdelay /= 0 generate
rcnt : process (clk_0r)
variable cnt : std_logic_vector(15 downto 0);
variable vlock, co : std_ulogic;
begin
if rising_edge(clk_0r) then
co := cnt(15);
vlockl <= vlock;
if lockl = '0' then
cnt := conv_std_logic_vector(rstdelay*DDR_FREQ, 16); vlock := '0';
else
if vlock = '0' then
cnt := cnt -1; vlock := cnt(15) and not co;
end if;
end if;
end if;
if lockl = '0' then
vlock := '0';
end if;
end process;
end generate;
locked <= lockl when rstdelay = 0 else vlockl;
lock <= locked;
-- Generate external DDR clock
fbdclk0r : ODDR port map ( Q => ddr_clk_fb_outr, C => clk90r, CE => vcc,
D1 => vcc, D2 => gnd, R => gnd, S => gnd);
fbclk_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_clk_fb_out, ddr_clk_fb_outr);
ddrclocks : for i in 0 to 2 generate
dclk0r : ODDR port map ( Q => ddr_clkl(i), C => clk90r, CE => vcc,
D1 => vcc, D2 => gnd, R => gnd, S => gnd);
ddrclk_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_clk(i), ddr_clkl(i));
dclk0rb : ODDR port map ( Q => ddr_clkbl(i), C => clk90r, CE => vcc,
D1 => gnd, D2 => vcc, R => gnd, S => gnd);
ddrclkb_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_clkb(i), ddr_clkbl(i));
end generate;
ddrbanks : for i in 0 to 1 generate
csn0gen : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_csnr(i), C => clk0r, CE => vcc,
D1 => csn(i), D2 => csn(i), R => gnd, S => gnd);
csn0_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_csb(i), ddr_csnr(i));
ckel(i) <= cke(i) and locked;
ckegen : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_ckenr(i), C => clk0r, CE => vcc,
D1 => ckel(i), D2 => ckel(i), R => gnd, S => gnd);
cke_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_cke(i), ddr_ckenr(i));
end generate;
rasgen : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_rasnr, C => clk0r, CE => vcc,
D1 => rasn, D2 => rasn, R => gnd, S => gnd);
rasn_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_rasb, ddr_rasnr);
casgen : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_casnr, C => clk0r, CE => vcc,
D1 => casn, D2 => casn, R => gnd, S => gnd);
casn_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_casb, ddr_casnr);
wengen : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_wenr, C => clk0r, CE => vcc,
D1 => wen, D2 => wen, R => gnd, S => gnd);
wen_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_web, ddr_wenr);
dmgen : for i in 0 to dbits/8-1 generate
da0 : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_dmr(i), C => clk0r, CE => vcc,
D1 => dm(i+dbits/8), D2 => dm(i), R => gnd, S => gnd);
ddr_bm_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_dm(i), ddr_dmr(i));
end generate;
bagen : for i in 0 to 1 generate
da0 : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_bar(i), C => clk0r, CE => vcc,
D1 => ba(i), D2 => ba(i), R => gnd, S => gnd);
ddr_ba_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_ba(i), ddr_bar(i));
end generate;
dagen : for i in 0 to 13 generate
da0 : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_adr(i), C => clk0r, CE => vcc,
D1 => addr(i), D2 => addr(i), R => gnd, S => gnd);
ddr_ad_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_ad(i), ddr_adr(i));
end generate;
-- DQS generation
dsqreg : FD port map ( Q => dqsn, C => clk180r, D => oe);
dqsgen : for i in 0 to dbits/8-1 generate
da0 : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_dqsin(i), C => clk90r, CE => vcc,
D1 => dqsn, D2 => gnd, R => gnd, S => gnd);
doen : FD port map ( Q => ddr_dqsoen(i), C => clk0r, D => dqsoen);
dqs_pad : iopad generic map (tech => virtex4, level => sstl2_ii)
port map (pad => ddr_dqs(i), i => ddr_dqsin(i), en => ddr_dqsoen(i),
o => ddr_dqsoutl(i));
end generate;
-- Data bus
read_rstdel : process (clk_0r, lockl)
begin
if lockl = '0' then dll2rst <= (others => '1');
elsif rising_edge(clk_0r) then
dll2rst <= dll2rst(1 to 3) & '0';
end if;
end process;
bufg7 : BUFG port map (I => rclk0, O => rclk0b);
bufg8 : BUFG port map (I => rclk90, O => rclk90b);
-- bufg9 : BUFG port map (I => rclk270, O => rclk270b);
rclk270b <= not rclk90b;
nops : if rskew = 0 generate
read_dll : DCM
generic map (clkin_period => 10.0, DESKEW_ADJUST => "SOURCE_SYNCHRONOUS")
port map ( CLKIN => ddrclkfbl, CLKFB => rclk0b, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll2rst(0), CLK0 => rclk0,
CLK90 => rclk90, CLK270 => rclk270);
end generate;
ps : if rskew /= 0 generate
read_dll : DCM
generic map (clkin_period => 10.0, DESKEW_ADJUST => "SOURCE_SYNCHRONOUS",
CLKOUT_PHASE_SHIFT => "FIXED", PHASE_SHIFT => rskew)
port map ( CLKIN => ddrclkfbl, CLKFB => rclk0b, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll2rst(0), CLK0 => rclk0,
CLK90 => rclk90, CLK270 => rclk270);
end generate;
ddgen : for i in 0 to dbits-1 generate
qi : IDDR generic map (DDR_CLK_EDGE => "OPPOSITE_EDGE")
port map ( Q1 => dqinl(i), --(i+dbits), -- 1-bit output for positive edge of clock
Q2 => dqin(i), -- 1-bit output for negative edge of clock
C => rclk90b, --clk270r, --dqsclk((2*i)/dbits), -- 1-bit clock input
CE => vcc, -- 1-bit clock enable input
D => ddr_dqin(i), -- 1-bit DDR data input
R => gnd, -- 1-bit reset
S => gnd -- 1-bit set
);
dinq1 : FD port map ( Q => dqin(i+dbits), C => rclk270b, D => dqinl(i));
dout : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_dqout(i), C => clk0r, CE => vcc,
D1 => dqout(i+dbits), D2 => dqout(i), R => gnd, S => gnd);
doen : FD port map ( Q => ddr_dqoen(i), C => clk0r, D => oen);
dq_pad : iopad generic map (tech => virtex4, level => sstl2_ii)
port map (pad => ddr_dq(i), i => ddr_dqout(i), en => ddr_dqoen(i), o => ddr_dqin(i));
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.BUFG;
use unisim.DCM;
use unisim.FDDRRSE;
use unisim.IFDDRRSE;
use unisim.FD;
-- pragma translate_on
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
use techmap.oddrv2;
------------------------------------------------------------------
-- Virtex2 DDR PHY -----------------------------------------------
------------------------------------------------------------------
entity virtex2_ddr_phy is
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ;
clk_div : integer := 2; rskew : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (13 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0)
);
end;
architecture rtl of virtex2_ddr_phy is
component DCM
generic (
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false
);
port (
CLKFB : in std_logic;
CLKIN : in std_logic;
DSSEN : in std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector (7 downto 0));
end component;
component BUFG port (O : out std_logic; I : in std_logic); end component;
component FDDRRSE
-- generic ( INIT : bit := '0');
port
(
Q : out std_ulogic;
C0 : in std_ulogic;
C1 : in std_ulogic;
CE : in std_ulogic;
D0 : in std_ulogic;
D1 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end component;
component IFDDRRSE
port (
Q0 : out std_ulogic;
Q1 : out std_ulogic;
C0 : in std_ulogic;
C1 : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component FD
generic ( INIT : bit := '0');
port ( Q : out std_ulogic;
C : in std_ulogic;
D : in std_ulogic);
end component;
component oddrv2
generic ( tech : integer := virtex4);
port
( Q : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
signal vcc, gnd, dqsn, oe, lockl : std_ulogic;
signal ddr_clk_fb_outr : std_ulogic;
signal ddr_clk_fbl, fbclk : std_ulogic;
signal ddr_rasnr, ddr_casnr, ddr_wenr : std_ulogic;
signal ddr_clkl, ddr_clkbl : std_logic_vector(2 downto 0);
signal ddr_csnr, ddr_ckenr, ckel : std_logic_vector(1 downto 0);
signal clk_0ro, clk_90ro, clk_180ro, clk_270ro : std_ulogic;
signal clk_0r, clk_90r, clk_180r, clk_270r : std_ulogic;
signal clk0r, clk90r, clk180r, clk270r : std_ulogic;
signal locked, vlockl, ddrclkfbl : std_ulogic;
signal ddr_dqin : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqout : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqoen : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_adr : std_logic_vector (13 downto 0); -- ddr address
signal ddr_bar : std_logic_vector (1 downto 0); -- ddr address
signal ddr_dmr : std_logic_vector (dbits/8-1 downto 0); -- ddr address
signal ddr_dqsin : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoen : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoutl : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal dqsdel, dqsclk : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal da : std_logic_vector (dbits-1 downto 0); -- ddr data
signal dqinl : std_logic_vector (dbits-1 downto 0); -- ddr data
signal dllrst : std_logic_vector(0 to 3);
signal dll0rst, dll2rst : std_logic_vector(0 to 3);
signal mlock, mclkfb, mclk, mclkfx, mclk0 : std_ulogic;
signal rclk270b, rclk90b, rclk0b : std_ulogic;
signal rclk270, rclk90, rclk0 : std_ulogic;
constant DDR_FREQ : integer := (MHz * clk_mul) / clk_div;
begin
oe <= not oen;
vcc <= '1'; gnd <= '0';
-- Optional DDR clock multiplication
noclkscale : if clk_mul = clk_div generate
mclk <= clk; mlock <= rst;
end generate;
clkscale : if clk_mul /= clk_div generate
rstdel : process (clk, rst)
begin
if rst = '0' then dll0rst <= (others => '1');
elsif rising_edge(clk) then
dll0rst <= dll0rst(1 to 3) & '0';
end if;
end process;
bufg0 : BUFG port map (I => mclkfx, O => mclk);
bufg1 : BUFG port map (I => mclk0, O => mclkfb);
dllm : DCM
generic map (CLKFX_MULTIPLY => clk_mul, CLKFX_DIVIDE => clk_div,
CLKIN_PERIOD => 10.0)
port map ( CLKIN => clk, CLKFB => mclkfb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst(0), CLK0 => mclk0,
LOCKED => mlock, CLKFX => mclkfx );
end generate;
-- DDR output clock generation
bufg1 : BUFG port map (I => clk_0ro, O => clk_0r);
-- bufg2 : BUFG port map (I => clk_90ro, O => clk_90r);
clk_90r <= not clk_270r;
-- bufg3 : BUFG port map (I => clk_180ro, O => clk_180r);
clk_180r <= not clk_0r;
bufg4 : BUFG port map (I => clk_270ro, O => clk_270r);
clkout <= clk_270r; clk0r <= clk_270r; clk90r <= clk_0r;
clk180r <= clk_90r; clk270r <= clk_180r;
dll : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2)
port map ( CLKIN => mclk, CLKFB => clk_0r, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dllrst(0), CLK0 => clk_0ro,
CLK90 => clk_90ro, CLK180 => clk_180ro, CLK270 => clk_270ro,
LOCKED => lockl);
rstdel : process (mclk, mlock)
begin
if mlock = '0' then dllrst <= (others => '1');
elsif rising_edge(mclk) then
dllrst <= dllrst(1 to 3) & '0';
end if;
end process;
rdel : if rstdelay /= 0 generate
rcnt : process (clk_0r)
variable cnt : std_logic_vector(15 downto 0);
variable vlock, co : std_ulogic;
begin
if rising_edge(clk_0r) then
co := cnt(15);
vlockl <= vlock;
if lockl = '0' then
cnt := conv_std_logic_vector(rstdelay*DDR_FREQ, 16); vlock := '0';
else
if vlock = '0' then
cnt := cnt -1; vlock := cnt(15) and not co;
end if;
end if;
end if;
if lockl = '0' then
vlock := '0';
end if;
end process;
end generate;
locked <= lockl when rstdelay = 0 else vlockl;
lock <= locked;
-- Generate external DDR clock
fbdclk0r : FDDRRSE port map ( Q => ddr_clk_fb_outr, C0 => clk90r, C1 => clk270r,
CE => vcc, D0 => vcc, D1 => gnd, R => gnd, S => gnd);
fbclk_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_clk_fb_out, ddr_clk_fb_outr);
ddrclocks : for i in 0 to 2 generate
dclk0r : FDDRRSE port map ( Q => ddr_clkl(i), C0 => clk90r, C1 => clk270r,
CE => vcc, D0 => vcc, D1 => gnd, R => gnd, S => gnd);
ddrclk_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_clk(i), ddr_clkl(i));
dclk0rb : FDDRRSE port map ( Q => ddr_clkbl(i), C0 => clk90r, C1 => clk270r,
CE => vcc, D0 => gnd, D1 => vcc, R => gnd, S => gnd);
ddrclkb_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_clkb(i), ddr_clkbl(i));
end generate;
ddrbanks : for i in 0 to 1 generate
csn0gen : FD port map ( Q => ddr_csnr(i), C => clk0r, D => csn(i));
csn0_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_csb(i), ddr_csnr(i));
ckel(i) <= cke(i) and locked;
ckegen : FD port map ( Q => ddr_ckenr(i), C => clk0r, D => ckel(i));
cke_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_cke(i), ddr_ckenr(i));
end generate;
-- DDR single-edge control signals
rasgen : FD port map ( Q => ddr_rasnr, C => clk0r, D => rasn);
rasn_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_rasb, ddr_rasnr);
casgen : FD port map ( Q => ddr_casnr, C => clk0r, D => casn);
casn_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_casb, ddr_casnr);
wengen : FD port map ( Q => ddr_wenr, C => clk0r, D => wen);
wen_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_web, ddr_wenr);
dmgen : for i in 0 to dbits/8-1 generate
da0 : oddrv2 port map ( Q => ddr_dmr(i), C1 => clk0r, C2 => clk180r,
CE => vcc, D1 => dm(i+dbits/8), D2 => dm(i), R => gnd, S => gnd);
ddr_bm_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_dm(i), ddr_dmr(i));
end generate;
bagen : for i in 0 to 1 generate
da0 : FD port map ( Q => ddr_bar(i), C => clk0r, D => ba(i));
ddr_ba_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_ba(i), ddr_bar(i));
end generate;
dagen : for i in 0 to 13 generate
da0 : FD port map ( Q => ddr_adr(i), C => clk0r, D => addr(i));
ddr_ad_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_ad(i), ddr_adr(i));
end generate;
-- DQS generation
dsqreg : FD port map ( Q => dqsn, C => clk180r, D => oe);
dqsgen : for i in 0 to dbits/8-1 generate
da0 : oddrv2
port map ( Q => ddr_dqsin(i), C1 => clk90r, C2 => clk270r,
CE => vcc, D1 => dqsn, D2 => gnd, R => gnd, S => gnd);
doen : FD port map ( Q => ddr_dqsoen(i), C => clk0r, D => dqsoen);
dqs_pad : iopad generic map (tech => virtex4, level => sstl2_ii)
port map (pad => ddr_dqs(i), i => ddr_dqsin(i), en => ddr_dqsoen(i),
o => ddr_dqsoutl(i));
end generate;
-- Data bus
ddrref_pad : clkpad generic map (tech => virtex2)
port map (ddr_clk_fb, ddrclkfbl);
read_rstdel : process (clk_0r, lockl)
begin
if lockl = '0' then dll2rst <= (others => '1');
elsif rising_edge(clk_0r) then
dll2rst <= dll2rst(1 to 3) & '0';
end if;
end process;
bufg7 : BUFG port map (I => rclk0, O => rclk0b);
bufg8 : BUFG port map (I => rclk90, O => rclk90b);
-- bufg9 : BUFG port map (I => rclk270, O => rclk270b);
rclk270b <= not rclk90b;
nops : if rskew = 0 generate
read_dll : DCM
generic map (clkin_period => 10.0, DESKEW_ADJUST => "SOURCE_SYNCHRONOUS")
port map ( CLKIN => ddrclkfbl, CLKFB => rclk0b, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll2rst(0), CLK0 => rclk0,
CLK90 => rclk90, CLK270 => rclk270);
end generate;
ps : if rskew /= 0 generate
read_dll : DCM
generic map (clkin_period => 10.0, DESKEW_ADJUST => "SOURCE_SYNCHRONOUS",
CLKOUT_PHASE_SHIFT => "FIXED", PHASE_SHIFT => rskew)
port map ( CLKIN => ddrclkfbl, CLKFB => rclk0b, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll2rst(0), CLK0 => rclk0,
CLK90 => rclk90, CLK270 => rclk270);
end generate;
ddgen : for i in 0 to dbits-1 generate
qi : IFDDRRSE
port map ( Q0 => dqinl(i), --(i+dbits), -- 1-bit output for positive edge of clock
Q1 => dqin(i), -- 1-bit output for negative edge of clock
C0 => rclk90b, -- clk270r, --dqsclk((2*i)/dbits), -- 1-bit clock input
C1 => rclk270b, -- clk90r, --dqsclk((2*i)/dbits), -- 1-bit clock input
CE => vcc, -- 1-bit clock enable input
D => ddr_dq(i), -- 1-bit DDR data input
R => gnd, -- 1-bit reset
S => gnd -- 1-bit set
);
-- dinq1 : FD port map ( Q => dqin(i+dbits), C => clk90r, D => dqinl(i));
dinq1 : FD port map ( Q => dqin(i+dbits), C => rclk270b, D => dqinl(i));
dout : oddrv2
port map ( Q => ddr_dqout(i), C1 => clk0r, C2 => clk180r, CE => vcc,
D1 => dqout(i+dbits), D2 => dqout(i), R => gnd, S => gnd);
doen : FD port map ( Q => ddr_dqoen(i), C => clk0r, D => oen);
dq_pad : iopad generic map (tech => virtex4, level => sstl2_ii)
port map (pad => ddr_dq(i), i => ddr_dqout(i), en => ddr_dqoen(i), o => open); -- o => ddr_dqin(i));
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.BUFG;
use unisim.DCM;
use unisim.ODDR2;
use unisim.IDDR2;
use unisim.FD;
-- pragma translate_on
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
use techmap.oddrc3e;
------------------------------------------------------------------
-- Spartan3E DDR PHY -----------------------------------------------
------------------------------------------------------------------
entity spartan3e_ddr_phy is
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ;
clk_div : integer := 2; rskew : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- DDR state clock
clkread : out std_ulogic; -- DDR read clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (13 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0)
);
end;
architecture rtl of spartan3e_ddr_phy is
component oddrc3e
generic ( tech : integer := virtex4);
port
( Q : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component DCM
generic (
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false
);
port (
CLKFB : in std_logic;
CLKIN : in std_logic;
DSSEN : in std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector (7 downto 0));
end component;
component BUFG port (O : out std_logic; I : in std_logic); end component;
component FD
generic ( INIT : bit := '0');
port ( Q : out std_ulogic;
C : in std_ulogic;
D : in std_ulogic);
end component;
component ODDR2
generic
(
DDR_ALIGNMENT : string := "NONE";
INIT : bit := '0';
SRTYPE : string := "SYNC"
);
port
(
Q : out std_ulogic;
C0 : in std_ulogic;
C1 : in std_ulogic;
CE : in std_ulogic;
D0 : in std_ulogic;
D1 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end component;
component IDDR2
generic
(
DDR_ALIGNMENT : string := "NONE";
INIT_Q0 : bit := '0';
INIT_Q1 : bit := '0';
SRTYPE : string := "SYNC"
);
port
(
Q0 : out std_ulogic;
Q1 : out std_ulogic;
C0 : in std_ulogic;
C1 : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end component;
signal vcc, gnd, dqsn, oe, lockl : std_ulogic;
signal ddr_clk_fb_outr : std_ulogic;
signal ddr_clk_fbl, fbclk : std_ulogic;
signal ddr_rasnr, ddr_casnr, ddr_wenr : std_ulogic;
signal ddr_clkl, ddr_clkbl : std_logic_vector(2 downto 0);
signal ddr_csnr, ddr_ckenr, ckel : std_logic_vector(1 downto 0);
signal clk_0ro, clk_90ro, clk_180ro, clk_270ro : std_ulogic;
signal clk_0r, clk_90r, clk_180r, clk_270r : std_ulogic;
signal clk0r, clk90r, clk180r, clk270r : std_ulogic;
signal locked, vlockl, ddrclkfbl, dllfb : std_ulogic;
signal ddr_dqin : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqout : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqoen : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_adr : std_logic_vector (13 downto 0); -- ddr address
signal ddr_bar : std_logic_vector (1 downto 0); -- ddr address
signal ddr_dmr : std_logic_vector (dbits/8-1 downto 0); -- ddr address
signal ddr_dqsin : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoen : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoutl : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal dqsdel, dqsclk : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal da : std_logic_vector (dbits-1 downto 0); -- ddr data
signal dqinl : std_logic_vector (dbits-1 downto 0); -- ddr data
signal dllrst : std_logic_vector(0 to 3);
signal dll0rst, dll2rst : std_logic_vector(0 to 3);
signal mlock, mclkfb, mclk, mclkfx, mclk0 : std_ulogic;
signal rclk270b, rclk90b, rclk0b : std_ulogic;
signal rclk270, rclk90, rclk0 : std_ulogic;
constant DDR_FREQ : integer := (MHz * clk_mul) / clk_div;
begin
oe <= not oen;
vcc <= '1'; gnd <= '0';
-- Optional DDR clock multiplication
noclkscale : if clk_mul = clk_div generate
mclk <= clk; mlock <= rst;
end generate;
clkscale : if clk_mul /= clk_div generate
rstdel : process (clk, rst)
begin
if rst = '0' then dll0rst <= (others => '1');
elsif rising_edge(clk) then
dll0rst <= dll0rst(1 to 3) & '0';
end if;
end process;
bufg0 : BUFG port map (I => mclkfx, O => mclk);
bufg1 : BUFG port map (I => mclk0, O => mclkfb);
dllm : DCM
generic map (CLKFX_MULTIPLY => clk_mul, CLKFX_DIVIDE => clk_div,
CLKIN_PERIOD => 10.0)
port map ( CLKIN => clk, CLKFB => mclkfb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst(0), CLK0 => mclk0,
LOCKED => mlock, CLKFX => mclkfx );
end generate;
-- DDR output clock generation
bufg1 : BUFG port map (I => clk_0ro, O => clk_0r);
-- bufg2 : BUFG port map (I => clk_90ro, O => clk_90r);
clk_90r <= not clk_270r;
-- bufg3 : BUFG port map (I => clk_180ro, O => clk_180r);
clk_180r <= not clk_0r;
bufg4 : BUFG port map (I => clk_270ro, O => clk_270r);
clkout <= clk_270r;
-- clkout <= clk_90r when DDR_FREQ > 120 else clk_0r;
clk0r <= clk_270r; clk90r <= clk_0r;
clk180r <= clk_90r; clk270r <= clk_180r;
dll : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2)
port map ( CLKIN => mclk, CLKFB => clk_0r, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dllrst(0), CLK0 => clk_0ro,
CLK90 => clk_90ro, CLK180 => clk_180ro, CLK270 => clk_270ro,
LOCKED => lockl);
rstdel : process (mclk, mlock)
begin
if mlock = '0' then dllrst <= (others => '1');
elsif rising_edge(mclk) then
dllrst <= dllrst(1 to 3) & '0';
end if;
end process;
rdel : if rstdelay /= 0 generate
rcnt : process (clk_0r)
variable cnt : std_logic_vector(15 downto 0);
variable vlock, co : std_ulogic;
begin
if rising_edge(clk_0r) then
co := cnt(15);
vlockl <= vlock;
if lockl = '0' then
cnt := conv_std_logic_vector(rstdelay*DDR_FREQ, 16); vlock := '0';
else
if vlock = '0' then
cnt := cnt -1; vlock := cnt(15) and not co;
end if;
end if;
end if;
if lockl = '0' then
vlock := '0';
end if;
end process;
end generate;
locked <= lockl when rstdelay = 0 else vlockl;
lock <= locked;
-- Generate external DDR clock
fbdclk0r : ODDR2 port map ( Q => ddr_clk_fb_outr, C0 => clk90r, C1 => clk270r,
CE => vcc, D0 => vcc, D1 => gnd, R => gnd, S => gnd);
fbclk_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_clk_fb_out, ddr_clk_fb_outr);
ddrclocks : for i in 0 to 2 generate
dclk0r : ODDR2 port map ( Q => ddr_clkl(i), C0 => clk90r, C1 => clk270r,
CE => vcc, D0 => vcc, D1 => gnd, R => gnd, S => gnd);
ddrclk_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_clk(i), ddr_clkl(i));
dclk0rb : ODDR2 port map ( Q => ddr_clkbl(i), C0 => clk90r, C1 => clk270r,
CE => vcc, D0 => gnd, D1 => vcc, R => gnd, S => gnd);
ddrclkb_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_clkb(i), ddr_clkbl(i));
end generate;
ddrbanks : for i in 0 to 1 generate
csn0gen : FD port map ( Q => ddr_csnr(i), C => clk0r, D => csn(i));
csn0_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_csb(i), ddr_csnr(i));
ckel(i) <= cke(i) and locked;
ckegen : FD port map ( Q => ddr_ckenr(i), C => clk0r, D => ckel(i));
cke_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_cke(i), ddr_ckenr(i));
end generate;
-- DDR single-edge control signals
rasgen : FD port map ( Q => ddr_rasnr, C => clk0r, D => rasn);
rasn_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_rasb, ddr_rasnr);
casgen : FD port map ( Q => ddr_casnr, C => clk0r, D => casn);
casn_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_casb, ddr_casnr);
wengen : FD port map ( Q => ddr_wenr, C => clk0r, D => wen);
wen_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_web, ddr_wenr);
dmgen : for i in 0 to dbits/8-1 generate
da0 : oddrc3e
port map ( Q => ddr_dmr(i), C1 => clk0r, C2 => clk180r,
CE => vcc, D1 => dm(i+dbits/8), D2 => dm(i), R => gnd, S => gnd);
ddr_bm_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_dm(i), ddr_dmr(i));
end generate;
bagen : for i in 0 to 1 generate
da0 : FD port map ( Q => ddr_bar(i), C => clk0r, D => ba(i));
ddr_ba_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_ba(i), ddr_bar(i));
end generate;
dagen : for i in 0 to 13 generate
da0 : FD port map ( Q => ddr_adr(i), C => clk0r, D => addr(i));
ddr_ad_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_ad(i), ddr_adr(i));
end generate;
-- DQS generation
dsqreg : FD port map ( Q => dqsn, C => clk180r, D => oe);
dqsgen : for i in 0 to dbits/8-1 generate
da0 : oddrc3e
port map ( Q => ddr_dqsin(i), C1 => clk90r, C2 => clk270r,
CE => vcc, D1 => dqsn, D2 => gnd, R => gnd, S => gnd);
doen : FD port map ( Q => ddr_dqsoen(i), C => clk0r, D => dqsoen);
dqs_pad : iopad generic map (tech => virtex4, level => sstl2_i)
port map (pad => ddr_dqs(i), i => ddr_dqsin(i), en => ddr_dqsoen(i),
o => ddr_dqsoutl(i));
end generate;
-- Data bus
ddrref_pad : clkpad generic map (tech => virtex2)
port map (ddr_clk_fb, ddrclkfbl);
read_rstdel : process (clk_0r, lockl)
begin
if lockl = '0' then dll2rst <= (others => '1');
elsif rising_edge(clk_0r) then
dll2rst <= dll2rst(1 to 3) & '0';
end if;
end process;
bufg7 : BUFG port map (I => rclk0, O => rclk0b);
bufg8 : BUFG port map (I => rclk90, O => rclk90b);
-- bufg9 : BUFG port map (I => rclk270, O => rclk270b);
rclk270b <= not rclk90b;
clkread <= not rclk90b;
nops : if rskew = 0 generate
read_dll : DCM
generic map (clkin_period => 10.0, DESKEW_ADJUST => "SOURCE_SYNCHRONOUS")
port map ( CLKIN => ddrclkfbl, CLKFB => rclk0b, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll2rst(0), CLK0 => rclk0,
CLK90 => rclk90, CLK270 => rclk270);
end generate;
ps : if rskew /= 0 generate
read_dll : DCM
generic map (clkin_period => 10.0, DESKEW_ADJUST => "SOURCE_SYNCHRONOUS",
CLKOUT_PHASE_SHIFT => "FIXED", PHASE_SHIFT => rskew)
port map ( CLKIN => ddrclkfbl, CLKFB => rclk0b, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll2rst(0), CLK0 => rclk0,
CLK90 => rclk90, CLK270 => rclk270);
end generate;
ddgen : for i in 0 to dbits-1 generate
qi : IDDR2
port map ( Q0 => dqinl(i), Q1 => dqin(i), C0 => rclk90b, C1 => rclk270b,
CE => vcc, D => ddr_dqin(i), R => gnd, S => gnd );
dinq1 : FD port map ( Q => dqin(i+dbits), C => rclk270b, D => dqinl(i));
dout : oddrc3e
port map ( Q => ddr_dqout(i), C1 => clk0r, C2 => clk180r, CE => vcc,
D1 => dqout(i+dbits), D2 => dqout(i), R => gnd, S => gnd);
doen : FD port map ( Q => ddr_dqoen(i), C => clk0r, D => oen);
dq_pad : iopad generic map (tech => virtex4, level => sstl2_i)
port map (pad => ddr_dq(i), i => ddr_dqout(i), en => ddr_dqoen(i), o => ddr_dqin(i));
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
-- pragma translate_off
library unisim;
use unisim.BUFG;
use unisim.DCM;
use unisim.ODDR;
use unisim.FD;
use unisim.IDELAY;
use unisim.ISERDES;
use unisim.BUFIO;
use unisim.IDELAYCTRL;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
------------------------------------------------------------------
-- Virtex5 DDR2 PHY ----------------------------------------------
------------------------------------------------------------------
entity virtex5_ddr2_phy is
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2; clk_div : integer := 2;
ddelayb0 : integer := 0; ddelayb1 : integer := 0; ddelayb2 : integer := 0;
ddelayb3 : integer := 0; ddelayb4 : integer := 0; ddelayb5 : integer := 0;
ddelayb6 : integer := 0; ddelayb7 : integer := 0;
numidelctrl : integer := 4; norefclk : integer := 0; tech : integer := virtex5);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkref200 : in std_logic; -- input 200MHz clock
clkout : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqsn : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqsn
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(1 downto 0);
addr : in std_logic_vector (13 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0);
cal_en : in std_logic_vector(dbits/8-1 downto 0);
cal_inc : in std_logic_vector(dbits/8-1 downto 0);
cal_rst : in std_logic;
odt : in std_logic_vector(1 downto 0)
);
end;
architecture rtl of virtex5_ddr2_phy is
component DCM
generic (
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false
);
port (
CLKFB : in std_logic;
CLKIN : in std_logic;
DSSEN : in std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector (7 downto 0));
end component;
component BUFG port (O : out std_logic; I : in std_logic); end component;
component ODDR
generic
( DDR_CLK_EDGE : string := "OPPOSITE_EDGE";
-- INIT : bit := '0';
SRTYPE : string := "SYNC");
port
(
Q : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end component;
component FD
generic ( INIT : bit := '0');
port ( Q : out std_ulogic;
C : in std_ulogic;
D : in std_ulogic);
end component;
component IDDR
generic ( DDR_CLK_EDGE : string := "SAME_EDGE";
INIT_Q1 : bit := '0';
INIT_Q2 : bit := '0';
SRTYPE : string := "ASYNC");
port
( Q1 : out std_ulogic;
Q2 : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
-- component BUFIO
-- port ( O : out std_ulogic;
-- I : in std_ulogic);
-- end component;
component IDELAY
generic ( IOBDELAY_TYPE : string := "DEFAULT";
IOBDELAY_VALUE : integer := 0);
port ( O : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
I : in std_ulogic;
INC : in std_ulogic;
RST : in std_ulogic);
end component;
-- component ISERDES
-- generic
-- (
-- BITSLIP_ENABLE : boolean := false;
-- DATA_RATE : string := "DDR";
-- DATA_WIDTH : integer := 4;
-- INIT_Q1 : bit := '0';
-- INIT_Q2 : bit := '0';
-- INIT_Q3 : bit := '0';
-- INIT_Q4 : bit := '0';
-- INTERFACE_TYPE : string := "MEMORY";
-- IOBDELAY : string := "NONE";
-- IOBDELAY_TYPE : string := "DEFAULT";
-- IOBDELAY_VALUE : integer := 0;
-- NUM_CE : integer := 2;
-- SERDES_MODE : string := "MASTER";
-- SRVAL_Q1 : bit := '0';
-- SRVAL_Q2 : bit := '0';
-- SRVAL_Q3 : bit := '0';
-- SRVAL_Q4 : bit := '0'
-- );
-- port
-- (
-- O : out std_ulogic;
-- Q1 : out std_ulogic;
-- Q2 : out std_ulogic;
-- Q3 : out std_ulogic;
-- Q4 : out std_ulogic;
-- Q5 : out std_ulogic;
-- Q6 : out std_ulogic;
-- SHIFTOUT1 : out std_ulogic;
-- SHIFTOUT2 : out std_ulogic;
-- BITSLIP : in std_ulogic;
-- CE1 : in std_ulogic;
-- CE2 : in std_ulogic;
-- CLK : in std_ulogic;
-- CLKDIV : in std_ulogic;
-- D : in std_ulogic;
-- DLYCE : in std_ulogic;
-- DLYINC : in std_ulogic;
-- DLYRST : in std_ulogic;
-- OCLK : in std_ulogic;
-- REV : in std_ulogic;
-- SHIFTIN1 : in std_ulogic;
-- SHIFTIN2 : in std_ulogic;
-- SR : in std_ulogic
-- );
-- end component;
component IDELAYCTRL
port ( RDY : out std_ulogic;
REFCLK : in std_ulogic;
RST : in std_ulogic);
end component;
--signal vcc, gnd, dqsn, oe, lockl : std_ulogic;
signal vcc, gnd, oe, lockl : std_ulogic;
signal dqsn : std_logic_vector(dbits/8-1 downto 0);
signal ddr_clk_fb_outr : std_ulogic;
signal ddr_clk_fbl, fbclk : std_ulogic;
signal ddr_rasnr, ddr_casnr, ddr_wenr : std_ulogic;
signal ddr_clkl, ddr_clkbl : std_logic_vector(2 downto 0);
signal ddr_csnr, ddr_ckenr, ckel : std_logic_vector(1 downto 0);
signal clk_0ro, clk_90ro, clk_180ro, clk_270ro : std_ulogic;
signal clk_0r, clk_90r, clk_180r, clk_270r : std_ulogic;
signal clk0r, clk90r, clk180r, clk270r : std_ulogic;
signal locked, vlockl, ddrclkfbl, dllfb : std_ulogic;
signal ddr_dqin, ddr_dqin_nodel : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqout : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqoen : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_adr : std_logic_vector (13 downto 0); -- ddr address
signal ddr_bar : std_logic_vector (1 downto 0); -- ddr address
signal ddr_dmr : std_logic_vector (dbits/8-1 downto 0); -- ddr address
signal ddr_dqsin : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoen : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoutl : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal dqsdel, dqsclk, dqsclkn : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal da : std_logic_vector (dbits-1 downto 0); -- ddr data
signal dqinl : std_logic_vector (dbits-1 downto 0); -- ddr data
signal dllrst : std_logic_vector(0 to 3);
signal dll0rst, dll2rst : std_logic_vector(0 to 3);
signal mlock, mclkfb, mclk, mclkfx, mclk0 : std_ulogic;
signal rclk270b, rclk90b, rclk0b : std_ulogic;
signal rclk270, rclk90, rclk0 : std_ulogic;
signal clk200, clk200_0, clk200fb, clk200fx, lock200 : std_logic;
signal odtl : std_logic_vector(1 downto 0);
signal refclk_rdy : std_logic_vector(numidelctrl-1 downto 0);
constant DDR_FREQ : integer := (MHz * clk_mul) / clk_div;
type ddelay_type is array (7 downto 0) of integer;
constant ddelay : ddelay_type := (ddelayb0, ddelayb1, ddelayb2,
ddelayb3, ddelayb4, ddelayb5,
ddelayb6, ddelayb7);
attribute syn_noprune : boolean;
attribute syn_noprune of IDELAYCTRL : component is true;
attribute syn_keep : boolean;
attribute syn_keep of dqsclk : signal is true;
attribute syn_preserve : boolean;
attribute syn_preserve of dqsclk : signal is true;
attribute syn_keep of dqsn : signal is true;
attribute syn_preserve of dqsn : signal is true;
attribute keep : boolean;
attribute keep of mclkfx : signal is true;
attribute keep of clk_90ro : signal is true;
attribute syn_keep of mclkfx : signal is true;
attribute syn_keep of clk_90ro : signal is true;
begin
-- Generate 200 MHz ref clock if not supplied
refclkx : if norefclk = 0 generate
buf_clk200 : BUFG port map( I => clkref200, O => clk200);
lock200 <= '1';
end generate;
norefclkx : if norefclk /= 0 generate
bufg0 : BUFG port map (I => clk200fx, O => clk200);
bufg1 : BUFG port map (I => clk200_0, O => clk200fb);
HMODE_dll200 : if (tech = virtex4 and ((200 >= 210) or (MHz >= 210)))
or (tech = virtex5 and ((200 >= 140) or (MHz >= 140))) generate
dll200 : DCM
generic map (CLKFX_MULTIPLY => 2000/MHz, CLKFX_DIVIDE => 10,
DFS_FREQUENCY_MODE => "HIGH", DLL_FREQUENCY_MODE => "HIGH")
port map ( CLKIN => clk, CLKFB => clk200fb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst(0), CLK0 => clk200_0,
LOCKED => lock200, CLKFX => clk200fx);
end generate;
LMODE_dll200 : if not ((tech = virtex4 and ((200 >= 210) or (MHz >= 210)))
or (tech = virtex5 and ((200 >= 140) or (MHz >= 140)))) generate
dll200 : DCM
generic map (CLKFX_MULTIPLY => 2000/MHz, CLKFX_DIVIDE => 10,
DFS_FREQUENCY_MODE => "LOW", DLL_FREQUENCY_MODE => "LOW")
port map ( CLKIN => clk, CLKFB => clk200fb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst(0), CLK0 => clk200_0,
LOCKED => lock200, CLKFX => clk200fx);
end generate;
end generate;
-- Delay control
idelctrl : for i in 0 to numidelctrl-1 generate
u : IDELAYCTRL port map (rst => dllrst(0), refclk => clk200, rdy => refclk_rdy(i));
end generate;
oe <= not oen;
vcc <= '1'; gnd <= '0';
-- Optional DDR clock multiplication
noclkscale : if clk_mul = clk_div generate
--mclk <= clk;
dll0rst <= dllrst;
mlock <= '1';
mbufg0 : BUFG port map (I => clk, O => mclk);
end generate;
clkscale : if clk_mul /= clk_div generate
rstdel : process (clk, rst)
begin
if rst = '0' then dll0rst <= (others => '1');
elsif rising_edge(clk) then
dll0rst <= dll0rst(1 to 3) & '0';
end if;
end process;
bufg0 : BUFG port map (I => mclkfx, O => mclk);
bufg1 : BUFG port map (I => mclk0, O => mclkfb);
HMODE_dllm : if (tech = virtex4 and (((MHz*clk_mul)/clk_div >= 210) or (MHz >= 210)))
or (tech = virtex5 and (((MHz*clk_mul)/clk_div >= 140) or (MHz >= 140))) generate
dllm : DCM
generic map (CLKFX_MULTIPLY => clk_mul, CLKFX_DIVIDE => clk_div,
DFS_FREQUENCY_MODE => "HIGH", DLL_FREQUENCY_MODE => "HIGH")
port map ( CLKIN => clk, CLKFB => mclkfb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst(0), CLK0 => mclk0,
LOCKED => mlock, CLKFX => mclkfx );
end generate;
LMODE_dllm : if not ((tech = virtex4 and (((MHz*clk_mul)/clk_div >= 210) or (MHz >= 210)))
or (tech = virtex5 and (((MHz*clk_mul)/clk_div >= 140) or (MHz >= 140)))) generate
dllm : DCM
generic map (CLKFX_MULTIPLY => clk_mul, CLKFX_DIVIDE => clk_div,
DFS_FREQUENCY_MODE => "LOW", DLL_FREQUENCY_MODE => "LOW")
port map ( CLKIN => clk, CLKFB => mclkfb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst(0), CLK0 => mclk0,
LOCKED => mlock, CLKFX => mclkfx );
end generate;
end generate;
-- DDR clock generation
-- bufg1 : BUFG port map (I => clk_0ro, O => clk0r);
clk0r <= mclk;
bufg2 : BUFG port map (I => clk_90ro, O => clk90r);
-- bufg3 : BUFG port map (I => clk_180ro, O => clk180r);
clk180r <= not mclk;
-- bufg4 : BUFG port map (I => clk_270ro, O => clk270r);
clkout <= clk0r;
-- dllfb <= clk0r;
dllfb <= clk90r;
HMODE_dll : if (tech = virtex4 and ((MHz*clk_mul)/clk_div >= 150))
or (tech = virtex5 and ((MHz*clk_mul)/clk_div >= 120)) generate
dll : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2,
DFS_FREQUENCY_MODE => "HIGH", DLL_FREQUENCY_MODE => "HIGH", --"HIGH")
PHASE_SHIFT => 64, CLKOUT_PHASE_SHIFT => "FIXED")--, CLKIN_PERIOD => real((1000*clk_div)/(MHz*clk_mul)))
port map ( CLKIN => mclk, CLKFB => dllfb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dllrst(0), CLK0 => clk_90ro,
CLK90 => open, CLK180 => open, CLK270 => open,
LOCKED => lockl);
end generate;
LMODE_dll : if not ((tech = virtex4 and ((MHz*clk_mul)/clk_div >= 150))
or (tech = virtex5 and ((MHz*clk_mul)/clk_div >= 120))) generate
dll : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2,
DFS_FREQUENCY_MODE => "LOW", DLL_FREQUENCY_MODE => "LOW", --"HIGH")
PHASE_SHIFT => 64, CLKOUT_PHASE_SHIFT => "FIXED")--, CLKIN_PERIOD => real((1000*clk_div)/(MHz*clk_mul)))
port map ( CLKIN => mclk, CLKFB => dllfb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dllrst(0), CLK0 => clk_90ro,
CLK90 => open, CLK180 => open, CLK270 => open,
LOCKED => lockl);
end generate;
-- dll : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2, CLKIN_PERIOD => 6.25,
-- DFS_FREQUENCY_MODE => "LOW", DLL_FREQUENCY_MODE => "HIGH") --"HIGH")
-- port map ( CLKIN => mclk, CLKFB => dllfb, DSSEN => gnd, PSCLK => gnd,
-- PSEN => gnd, PSINCDEC => gnd, RST => dllrst(0), CLK0 => clk_0ro,
-- CLK90 => clk_90ro, CLK180 => clk_180ro, CLK270 => clk_270ro,
-- LOCKED => lockl);
rstdel : process (mclk, rst, mlock, lock200)
begin
if rst = '0' or mlock = '0' or lock200 = '0' then dllrst <= (others => '1');
elsif rising_edge(mclk) then
dllrst <= dllrst(1 to 3) & '0';
end if;
end process;
rdel : if rstdelay /= 0 generate
--rcnt : process (clk_0r)
rcnt : process (clk0r)
variable cnt : std_logic_vector(15 downto 0);
variable vlock, co : std_ulogic;
begin
--if rising_edge(clk_0r) then
if rising_edge(clk0r) then
co := cnt(15);
vlockl <= vlock;
if lockl = '0' then
cnt := conv_std_logic_vector(rstdelay*DDR_FREQ, 16); vlock := '0';
else
if vlock = '0' then
cnt := cnt -1; vlock := cnt(15) and not co;
end if;
end if;
end if;
if lockl = '0' then
vlock := '0';
end if;
end process;
end generate;
locked <= lockl when rstdelay = 0 else vlockl;
lock <= locked and orv(refclk_rdy);
-- Generate external DDR clock
ddrclocks : for i in 0 to 2 generate
dclk0r : ODDR port map ( Q => ddr_clkl(i), C => clk90r, CE => vcc,
D1 => vcc, D2 => gnd, R => gnd, S => gnd);
ddrclk_pad : outpad generic map (tech => virtex5, level => sstl18_i)
port map (ddr_clk(i), ddr_clkl(i));
-- Diff ddr_clk
-- ddrclk_pad : outpad_ds generic map(tech => virtex5, level => sstl18_ii)
-- port map (ddr_clk(i), ddr_clkb(i), ddr_clkl(i), gnd);
dclk0rb : ODDR port map ( Q => ddr_clkbl(i), C => clk90r, CE => vcc,
D1 => gnd, D2 => vcc, R => gnd, S => gnd);
ddrclkb_pad : outpad generic map (tech => virtex5, level => sstl18_i)
port map (ddr_clkb(i), ddr_clkbl(i));
end generate;
-- ODT pads
odtgen : for i in 0 to 1 generate
odtl(i) <= locked and orv(refclk_rdy) and odt(i);
ddr_odt_pad : outpad generic map (tech => virtex5, level => sstl18_i)
port map (ddr_odt(i), odtl(i));
end generate;
ddrbanks : for i in 0 to 1 generate
csn0gen : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_csnr(i), C => clk0r, CE => vcc,
D1 => csn(i), D2 => csn(i), R => gnd, S => gnd);
csn0_pad : outpad generic map (tech => virtex5, level => sstl18_i)
port map (ddr_csb(i), ddr_csnr(i));
ckel(i) <= cke(i) and locked;
ckegen : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_ckenr(i), C => clk0r, CE => vcc,
D1 => ckel(i), D2 => ckel(i), R => gnd, S => gnd);
cke_pad : outpad generic map (tech => virtex5, level => sstl18_i)
port map (ddr_cke(i), ddr_ckenr(i));
end generate;
rasgen : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_rasnr, C => clk0r, CE => vcc,
D1 => rasn, D2 => rasn, R => gnd, S => gnd);
rasn_pad : outpad generic map (tech => virtex5, level => sstl18_i)
port map (ddr_rasb, ddr_rasnr);
casgen : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_casnr, C => clk0r, CE => vcc,
D1 => casn, D2 => casn, R => gnd, S => gnd);
casn_pad : outpad generic map (tech => virtex5, level => sstl18_i)
port map (ddr_casb, ddr_casnr);
wengen : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_wenr, C => clk0r, CE => vcc,
D1 => wen, D2 => wen, R => gnd, S => gnd);
wen_pad : outpad generic map (tech => virtex5, level => sstl18_i)
port map (ddr_web, ddr_wenr);
dmgen : for i in 0 to dbits/8-1 generate
da0 : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_dmr(i), C => clk0r, CE => vcc,
D1 => dm(i+dbits/8), D2 => dm(i), R => gnd, S => gnd);
ddr_bm_pad : outpad generic map (tech => virtex5, level => sstl18_i)
port map (ddr_dm(i), ddr_dmr(i));
end generate;
bagen : for i in 0 to 1 generate
da0 : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_bar(i), C => clk0r, CE => vcc,
D1 => ba(i), D2 => ba(i), R => gnd, S => gnd);
ddr_ba_pad : outpad generic map (tech => virtex5, level => sstl18_i)
port map (ddr_ba(i), ddr_bar(i));
end generate;
dagen : for i in 0 to 13 generate
da0 : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_adr(i), C => clk0r, CE => vcc,
D1 => addr(i), D2 => addr(i), R => gnd, S => gnd);
ddr_ad_pad : outpad generic map (tech => virtex5, level => sstl18_i)
port map (ddr_ad(i), ddr_adr(i));
end generate;
-- DQS generation
--dsqreg : FD port map ( Q => dqsn, C => clk180r, D => oe);
dqsgen : for i in 0 to dbits/8-1 generate
dsqreg : FD port map ( Q => dqsn(i), C => clk180r, D => oe);
da0 : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_dqsin(i), C => clk90r, CE => vcc,
--D1 => dqsn, D2 => gnd, R => gnd, S => gnd);
D1 => dqsn(i), D2 => gnd, R => gnd, S => gnd);
doen : FD port map ( Q => ddr_dqsoen(i), C => clk0r, D => dqsoen);
dqs_pad : iopad_ds generic map (tech => virtex5, level => sstl18_ii)
port map (padp => ddr_dqs(i), padn => ddr_dqsn(i),i => ddr_dqsin(i),
en => ddr_dqsoen(i), o => ddr_dqsoutl(i));
-- del_dqs0 : IDELAY generic map(IOBDELAY_TYPE => "FIXED", IOBDELAY_VALUE => 10)
-- port map(O => dqsclk(i), I => ddr_dqsoutl(i), C => gnd, CE => gnd,
-- INC => gnd, RST => dllrst(0));
-- --buf_dqs0 : BUFIO port map(O => dqsclk(i), I => dqsdel(i));
-- dqsclkn(i) <= not dqsclk(i);
end generate;
-- Data bus
ddgen : for i in 0 to dbits-1 generate
del_dq0 : IDELAY generic map(IOBDELAY_TYPE => "VARIABLE", IOBDELAY_VALUE => ddelay(i/8))
--port map(O => ddr_dqin(i), I => ddr_dqin_nodel(i), C => clk_270r, CE => cal_en(i/8),
port map(O => ddr_dqin(i), I => ddr_dqin_nodel(i), C => clk0r, CE => cal_en(i/8),
INC => cal_inc(i/8), RST => cal_rst);
qi : IDDR generic map (DDR_CLK_EDGE => "OPPOSITE_EDGE")
port map ( Q1 => dqinl(i), --(i+dbits), -- 1-bit output for positive edge of clock
Q2 => dqin(i), --dqin(i), -- 1-bit output for negative edge of clock
--C => clk_90r, --clk270r, --dqsclk((2*i)/dbits), -- 1-bit clock input
C => clk180r, --clk270r, --dqsclk((2*i)/dbits), -- 1-bit clock input
CE => vcc, -- 1-bit clock enable input
D => ddr_dqin(i), -- 1-bit DDR data input
R => gnd, -- 1-bit reset
S => gnd -- 1-bit set
);
--dinq1 : FD port map ( Q => dqin(i+dbits), C => clk_270r, D => dqinl(i));
dinq1 : FD port map ( Q => dqin(i+dbits), C => clk0r, D => dqinl(i));
--dqi : ISERDES generic map(IOBDELAY => "IFD", IOBDELAY_TYPE => "FIXED", IOBDELAY_VALUE => 0)
-- port map(O => open, Q1 => dqin(i), Q2 => dqin(i+dbits), Q3 => open, Q4 => open, Q5 => open,
-- Q6 => open, SHIFTOUT1 => open, SHIFTOUT2 => open, BITSLIP => gnd,
-- CE1 => vcc, CE2 => vcc, CLK => dqsclk(i/8), CLKDIV => clk0r, D => ddr_dqin(i),
-- DLYCE => gnd, DLYINC => gnd, DLYRST => gnd, OCLK => clk0r, REV => gnd,
-- SHIFTIN1 => gnd, SHIFTIN2 => gnd, SR => gnd);
dout : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_dqout(i), C => clk0r, CE => vcc,
D1 => dqout(i+dbits), D2 => dqout(i), R => gnd, S => gnd);
doen : FD port map ( Q => ddr_dqoen(i), C => clk0r, D => oen);
dq_pad : iopad generic map (tech => virtex5, level => sstl18_ii)
port map (pad => ddr_dq(i), i => ddr_dqout(i), en => ddr_dqoen(i), o => ddr_dqin_nodel(i)); --o => ddr_dqin(i));
end generate;
end;
| mit | d3c611cbbe8f1fc298fa37e59c69016b | 0.560916 | 3.163984 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/esa/pci/pcicomp.vhd | 2 | 725 | library ieee;
library grlib;
use grlib.amba.all;
use ieee.std_logic_1164.all;
package pcicomp is
component pciarb is
generic(
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#FFF#;
nb_agents : integer := 4;
apb_en : integer := 1;
netlist : integer := 0);
port(
clk : in std_ulogic;
rst_n : in std_ulogic;
req_n : in std_logic_vector(0 to nb_agents-1);
frame_n : in std_logic;
gnt_n : out std_logic_vector(0 to nb_agents-1);
pclk : in std_ulogic;
prst_n : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type
);
end component;
end package;
| mit | f3aa3077573344e692d5dd34a07033fe | 0.542069 | 3.207965 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gleichmann/spi/spi_xmit.vhd | 2 | 2,819 | -------------------------------------------------------------------------------
-- Title : SPI Transmit Core
-- Project : LEON3MINI
-------------------------------------------------------------------------------
-- $Id: $
-------------------------------------------------------------------------------
-- Author : Thomas Ameseder
-- Company : Gleichmann Electronics
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
--
-- This core is an SPI master that was created in order to be able to
-- access the configuration interface of the Texas Instruments audio
-- codec TLV320AIC23B on the Hpe_mini board.
-------------------------------------------------------------------------------
-- Copyright (c) 2005
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity spi_xmit is
generic (
data_width : integer := 16);
port(
clk_i : in std_ulogic;
rst_i : in std_ulogic;
data_i : in std_logic_vector(data_width-1 downto 0);
CODEC_SDIN : out std_ulogic;
CODEC_CS : out std_ulogic
);
end spi_xmit;
architecture rtl of spi_xmit is
type state_t is (none_e, transmit_e);
signal state, nextstate : state_t;
signal counter, nextcounter : integer range -1 to data_width-1;
signal cs : std_ulogic;
signal data_reg : std_logic_vector(data_width-1 downto 0);
begin -- rtl
-- hard wired signals
CODEC_CS <= cs;
-- SPI transmit state machine
comb : process (counter, data_reg, state)
begin
nextstate <= state;
nextcounter <= counter;
cs <= '1';
CODEC_SDIN <= '-';
case state is
when none_e =>
nextstate <= transmit_e;
nextcounter <= data_width-1;
when transmit_e =>
cs <= '0';
if counter = -1 then
nextstate <= none_e;
nextcounter <= data_width-1;
cs <= '1';
CODEC_SDIN <= '-';
else
CODEC_SDIN <= data_reg(counter);
nextcounter <= counter - 1;
end if;
when others =>
nextstate <= none_e;
nextcounter <= data_width-1;
end case;
end process comb;
seq : process (clk_i, rst_i)
begin
if rst_i = '0' then
state <= none_e;
counter <= data_width-1;
data_reg <= (others => '0');
elsif falling_edge(clk_i) then
state <= nextstate;
counter <= nextcounter;
-- only accept new data when not transmitting
if state = none_e then
data_reg <= data_i;
end if;
end if;
end process seq;
end rtl;
| mit | b28e8f04e3b1cc2054f5606aae9593e5 | 0.448031 | 4.26475 | false | false | false | false |
lxp32/lxp32-cpu | rtl/lxp32_shifter.vhd | 2 | 2,717 | ---------------------------------------------------------------------
-- Barrel shifter
--
-- Part of the LXP32 CPU
--
-- Copyright (c) 2016 by Alex I. Kuznetsov
--
-- Performs logical (unsigned) and arithmetic (signed) shifts
-- in both directions. Pipeline latency: 1 cycle.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity lxp32_shifter is
port(
clk_i: in std_logic;
rst_i: in std_logic;
ce_i: in std_logic;
d_i: in std_logic_vector(31 downto 0);
s_i: in std_logic_vector(4 downto 0);
right_i: in std_logic;
sig_i: in std_logic;
ce_o: out std_logic;
d_o: out std_logic_vector(31 downto 0)
);
end entity;
architecture rtl of lxp32_shifter is
signal data: std_logic_vector(d_i'range);
signal data_shifted: std_logic_vector(d_i'range);
signal fill: std_logic; -- 0 for unsigned shifts, sign bit for signed ones
signal fill_v: std_logic_vector(3 downto 0);
type cascades_type is array (4 downto 0) of std_logic_vector(d_i'range);
signal cascades: cascades_type;
signal stage2_data: std_logic_vector(d_i'range);
signal stage2_s: std_logic_vector(s_i'range);
signal stage2_fill: std_logic;
signal stage2_fill_v: std_logic_vector(15 downto 0);
signal stage2_right: std_logic;
signal ceo: std_logic:='0';
begin
-- Internally, data are shifted in left direction. For right shifts
-- we reverse the argument's bit order
data_gen: for i in data'range generate
data(i)<=d_i(i) when right_i='0' else d_i(d_i'high-i);
end generate;
-- A set of cascaded shifters shifting by powers of two
fill<=sig_i and data(0);
fill_v<=(others=>fill);
cascades(0)<=data(30 downto 0)&fill_v(0) when s_i(0)='1' else data;
cascades(1)<=cascades(0)(29 downto 0)&fill_v(1 downto 0) when s_i(1)='1' else cascades(0);
cascades(2)<=cascades(1)(27 downto 0)&fill_v(3 downto 0) when s_i(2)='1' else cascades(1);
process (clk_i) is
begin
if rising_edge(clk_i) then
if rst_i='1' then
ceo<='0';
stage2_data<=(others=>'-');
stage2_s<=(others=>'-');
stage2_fill<='-';
stage2_right<='-';
else
ceo<=ce_i;
stage2_data<=cascades(2);
stage2_s<=s_i;
stage2_fill<=fill;
stage2_right<=right_i;
end if;
end if;
end process;
stage2_fill_v<=(others=>stage2_fill);
cascades(3)<=stage2_data(23 downto 0)&stage2_fill_v(7 downto 0) when stage2_s(3)='1' else stage2_data;
cascades(4)<=cascades(3)(15 downto 0)&stage2_fill_v(15 downto 0) when stage2_s(4)='1' else cascades(3);
-- Reverse bit order back, if needed
data_shifted_gen: for i in data_shifted'range generate
data_shifted(i)<=cascades(4)(i) when stage2_right='0' else cascades(4)(cascades(4)'high-i);
end generate;
d_o<=data_shifted;
ce_o<=ceo;
end architecture;
| mit | ece028f67e8c8dfcad4356d6684248d6 | 0.651822 | 2.789528 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/micron/sdram/mt48lc16m16a2.vhd | 2 | 67,097 |
--*****************************************************************************
--
-- Micron Semiconductor Products, Inc.
--
-- Copyright 1997, Micron Semiconductor Products, Inc.
-- All rights reserved.
--
--*****************************************************************************
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.ALL;
use std.textio.all;
PACKAGE mti_pkg IS
FUNCTION To_StdLogic (s : BIT) RETURN STD_LOGIC;
FUNCTION TO_INTEGER (input : STD_LOGIC) RETURN INTEGER;
FUNCTION TO_INTEGER (input : BIT_VECTOR) RETURN INTEGER;
FUNCTION TO_INTEGER (input : STD_LOGIC_VECTOR) RETURN INTEGER;
PROCEDURE TO_BITVECTOR (VARIABLE input : IN INTEGER; VARIABLE output : OUT BIT_VECTOR);
END mti_pkg;
PACKAGE BODY mti_pkg IS
-- Convert BIT to STD_LOGIC
FUNCTION To_StdLogic (s : BIT) RETURN STD_LOGIC IS
BEGIN
CASE s IS
WHEN '0' => RETURN ('0');
WHEN '1' => RETURN ('1');
WHEN OTHERS => RETURN ('0');
END CASE;
END;
-- Convert STD_LOGIC to INTEGER
FUNCTION TO_INTEGER (input : STD_LOGIC) RETURN INTEGER IS
VARIABLE result : INTEGER := 0;
VARIABLE weight : INTEGER := 1;
BEGIN
IF input = '1' THEN
result := weight;
ELSE
result := 0; -- if unknowns, default to logic 0
END IF;
RETURN result;
END TO_INTEGER;
-- Convert BIT_VECTOR to INTEGER
FUNCTION TO_INTEGER (input : BIT_VECTOR) RETURN INTEGER IS
VARIABLE result : INTEGER := 0;
VARIABLE weight : INTEGER := 1;
BEGIN
FOR i IN input'LOW TO input'HIGH LOOP
IF input(i) = '1' THEN
result := result + weight;
ELSE
result := result + 0; -- if unknowns, default to logic 0
END IF;
weight := weight * 2;
END LOOP;
RETURN result;
END TO_INTEGER;
-- Convert STD_LOGIC_VECTOR to INTEGER
FUNCTION TO_INTEGER (input : STD_LOGIC_VECTOR) RETURN INTEGER IS
VARIABLE result : INTEGER := 0;
VARIABLE weight : INTEGER := 1;
BEGIN
FOR i IN input'LOW TO input'HIGH LOOP
IF input(i) = '1' THEN
result := result + weight;
ELSE
result := result + 0; -- if unknowns, default to logic 0
END IF;
weight := weight * 2;
END LOOP;
RETURN result;
END TO_INTEGER;
-- Conver INTEGER to BIT_VECTOR
PROCEDURE TO_BITVECTOR (VARIABLE input : IN INTEGER; VARIABLE output : OUT BIT_VECTOR) IS
VARIABLE work,offset,outputlen,j : INTEGER := 0;
BEGIN
--length of vector
IF output'LENGTH > 32 THEN --'
outputlen := 32;
offset := output'LENGTH - 32; --'
IF input >= 0 THEN
FOR i IN offset-1 DOWNTO 0 LOOP
output(output'HIGH - i) := '0'; --'
END LOOP;
ELSE
FOR i IN offset-1 DOWNTO 0 LOOP
output(output'HIGH - i) := '1'; --'
END LOOP;
END IF;
ELSE
outputlen := output'LENGTH; --'
END IF;
--positive value
IF (input >= 0) THEN
work := input;
j := outputlen - 1;
FOR i IN 1 to 32 LOOP
IF j >= 0 then
IF (work MOD 2) = 0 THEN
output(output'HIGH-j-offset) := '0'; --'
ELSE
output(output'HIGH-j-offset) := '1'; --'
END IF;
END IF;
work := work / 2;
j := j - 1;
END LOOP;
IF outputlen = 32 THEN
output(output'HIGH) := '0'; --'
END IF;
--negative value
ELSE
work := (-input) - 1;
j := outputlen - 1;
FOR i IN 1 TO 32 LOOP
IF j>= 0 THEN
IF (work MOD 2) = 0 THEN
output(output'HIGH-j-offset) := '1'; --'
ELSE
output(output'HIGH-j-offset) := '0'; --'
END IF;
END IF;
work := work / 2;
j := j - 1;
END LOOP;
IF outputlen = 32 THEN
output(output'HIGH) := '1'; --'
END IF;
END IF;
END TO_BITVECTOR;
END mti_pkg;
-----------------------------------------------------------------------------------------
--
-- File Name: MT48LC16M16A2.VHD
-- Version: 0.0g
-- Date: June 29th, 2000
-- Model: Behavioral
-- Simulator: Model Technology (PC version 5.3 PE)
--
-- Dependencies: None
--
-- Author: Son P. Huynh
-- Email: [email protected]
-- Phone: (208) 368-3825
-- Company: Micron Technology, Inc.
-- Part Number: MT48LC16M16A2 (4Mb x 16 x 4 Banks)
--
-- Description: Micron 256Mb SDRAM
--
-- Limitation: - Doesn't check for 4096-cycle refresh --'
--
-- Note: - Set simulator resolution to "ps" accuracy
--
-- Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY
-- WHATSOEVER AND MICRON SPECIFICALLY DISCLAIMS ANY
-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
-- A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
--
-- Copyright (c) 1998 Micron Semiconductor Products, Inc.
-- All rights researved
--
-- Rev Author Phone Date Changes
-- ---- ---------------------------- ---------- -------------------------------------
-- 0.0g Son Huynh 208-368-3825 06/29/2000 Add Load/Dump memory array
-- Micron Technology Inc. Modify tWR + tRAS timing check
--
-- 0.0f Son Huynh 208-368-3825 07/08/1999 Fix tWR = 1 Clk + 7.5 ns (Auto)
-- Micron Technology Inc. Fix tWR = 15 ns (Manual)
-- Fix tRP (Autoprecharge to AutoRefresh)
--
-- 0.0c Son P. Huynh 208-368-3825 04/08/1999 Fix tWR + tRP in Write with AP
-- Micron Technology Inc. Fix tRC check in Load Mode Register
--
-- 0.0b Son P. Huynh 208-368-3825 01/06/1998 Derive from 64Mb SDRAM model
-- Micron Technology Inc.
--
-----------------------------------------------------------------------------------------
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
LIBRARY WORK;
USE WORK.MTI_PKG.ALL;
use std.textio.all;
library grlib;
use grlib.stdlib.all;
library gaisler;
use gaisler.sim.all;
ENTITY mt48lc16m16a2 IS
GENERIC (
-- Timing Parameters for -75 (PC133) and CAS Latency = 2
tAC : TIME := 6.0 ns;
tHZ : TIME := 7.0 ns;
tOH : TIME := 2.7 ns;
tMRD : INTEGER := 2; -- 2 Clk Cycles
tRAS : TIME := 44.0 ns;
tRC : TIME := 66.0 ns;
tRCD : TIME := 20.0 ns;
tRP : TIME := 20.0 ns;
tRRD : TIME := 15.0 ns;
tWRa : TIME := 7.5 ns; -- A2 Version - Auto precharge mode only (1 Clk + 7.5 ns)
tWRp : TIME := 15.0 ns; -- A2 Version - Precharge mode only (15 ns)
tAH : TIME := 0.8 ns;
tAS : TIME := 1.5 ns;
tCH : TIME := 2.5 ns;
tCL : TIME := 2.5 ns;
tCK : TIME := 10.0 ns;
tDH : TIME := 0.8 ns;
tDS : TIME := 1.5 ns;
tCKH : TIME := 0.8 ns;
tCKS : TIME := 1.5 ns;
tCMH : TIME := 0.8 ns;
tCMS : TIME := 1.5 ns;
addr_bits : INTEGER := 13;
data_bits : INTEGER := 16;
col_bits : INTEGER := 9;
index : INTEGER := 0;
fname : string := "sdram.srec" -- File to read from
);
PORT (
Dq : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
Addr : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
Ba : IN STD_LOGIC_VECTOR := "00";
Clk : IN STD_LOGIC := '0';
Cke : IN STD_LOGIC := '1';
Cs_n : IN STD_LOGIC := '1';
Ras_n : IN STD_LOGIC := '1';
Cas_n : IN STD_LOGIC := '1';
We_n : IN STD_LOGIC := '1';
Dqm : IN STD_LOGIC_VECTOR (1 DOWNTO 0) := "00"
);
END mt48lc16m16a2;
ARCHITECTURE behave OF mt48lc16m16a2 IS
TYPE State IS (ACT, A_REF, BST, LMR, NOP, PRECH, READ, READ_A, WRITE, WRITE_A, LOAD_FILE, DUMP_FILE);
TYPE Array4xI IS ARRAY (3 DOWNTO 0) OF INTEGER;
TYPE Array4xT IS ARRAY (3 DOWNTO 0) OF TIME;
TYPE Array4xB IS ARRAY (3 DOWNTO 0) OF BIT;
TYPE Array4x2BV IS ARRAY (3 DOWNTO 0) OF BIT_VECTOR (1 DOWNTO 0);
TYPE Array4xCBV IS ARRAY (4 DOWNTO 0) OF BIT_VECTOR (Col_bits - 1 DOWNTO 0);
TYPE Array_state IS ARRAY (4 DOWNTO 0) OF State;
SIGNAL Operation : State := NOP;
SIGNAL Mode_reg : BIT_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
SIGNAL Active_enable, Aref_enable, Burst_term : BIT := '0';
SIGNAL Mode_reg_enable, Prech_enable, Read_enable, Write_enable : BIT := '0';
SIGNAL Burst_length_1, Burst_length_2, Burst_length_4, Burst_length_8 : BIT := '0';
SIGNAL Cas_latency_2, Cas_latency_3 : BIT := '0';
SIGNAL Ras_in, Cas_in, We_in : BIT := '0';
SIGNAL Write_burst_mode : BIT := '0';
SIGNAL RAS_clk, Sys_clk, CkeZ : BIT := '0';
-- Checking internal wires
SIGNAL Pre_chk : BIT_VECTOR (3 DOWNTO 0) := "0000";
SIGNAL Act_chk : BIT_VECTOR (3 DOWNTO 0) := "0000";
SIGNAL Dq_in_chk, Dq_out_chk : BIT := '0';
SIGNAL Bank_chk : BIT_VECTOR (1 DOWNTO 0) := "00";
SIGNAL Row_chk : BIT_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
SIGNAL Col_chk : BIT_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- CS# Decode
WITH Cs_n SELECT
Cas_in <= TO_BIT (Cas_n, '1') WHEN '0',
'1' WHEN '1',
'1' WHEN OTHERS;
WITH Cs_n SELECT
Ras_in <= TO_BIT (Ras_n, '1') WHEN '0',
'1' WHEN '1',
'1' WHEN OTHERS;
WITH Cs_n SELECT
We_in <= TO_BIT (We_n, '1') WHEN '0',
'1' WHEN '1',
'1' WHEN OTHERS;
-- Commands Decode
Active_enable <= NOT(Ras_in) AND Cas_in AND We_in;
Aref_enable <= NOT(Ras_in) AND NOT(Cas_in) AND We_in;
Burst_term <= Ras_in AND Cas_in AND NOT(We_in);
Mode_reg_enable <= NOT(Ras_in) AND NOT(Cas_in) AND NOT(We_in);
Prech_enable <= NOT(Ras_in) AND Cas_in AND NOT(We_in);
Read_enable <= Ras_in AND NOT(Cas_in) AND We_in;
Write_enable <= Ras_in AND NOT(Cas_in) AND NOT(We_in);
-- Burst Length Decode
Burst_length_1 <= NOT(Mode_reg(2)) AND NOT(Mode_reg(1)) AND NOT(Mode_reg(0));
Burst_length_2 <= NOT(Mode_reg(2)) AND NOT(Mode_reg(1)) AND Mode_reg(0);
Burst_length_4 <= NOT(Mode_reg(2)) AND Mode_reg(1) AND NOT(Mode_reg(0));
Burst_length_8 <= NOT(Mode_reg(2)) AND Mode_reg(1) AND Mode_reg(0);
-- CAS Latency Decode
Cas_latency_2 <= NOT(Mode_reg(6)) AND Mode_reg(5) AND NOT(Mode_reg(4));
Cas_latency_3 <= NOT(Mode_reg(6)) AND Mode_reg(5) AND Mode_reg(4);
-- Write Burst Mode
Write_burst_mode <= Mode_reg(9);
-- RAS Clock for checking tWR and tRP
PROCESS
variable Clk0, Clk1 : integer := 0;
begin
RAS_clk <= '1';
wait for 0.5 ns;
RAS_clk <= '0';
wait for 0.5 ns;
if Clk0 > 100 or Clk1 > 100 then
wait;
else
if Clk = '1' and Cke = '1' then
Clk0 := 0;
Clk1 := Clk1 + 1;
elsif Clk = '0' and Cke = '1' then
Clk0 := Clk0 + 1;
Clk1 := 0;
end if;
end if;
END PROCESS;
-- System Clock
int_clk : PROCESS (Clk)
begin
IF Clk'LAST_VALUE = '0' AND Clk = '1' THEN --'
CkeZ <= TO_BIT(Cke, '1');
END IF;
Sys_clk <= CkeZ AND TO_BIT(Clk, '0');
END PROCESS;
state_register : PROCESS
-- NOTE: The extra bits in RAM_TYPE is for checking memory access. A logic 1 means
-- the location is in use. This will be checked when doing memory DUMP.
TYPE ram_type IS ARRAY (2**col_bits - 1 DOWNTO 0) OF BIT_VECTOR (data_bits DOWNTO 0);
TYPE ram_pntr IS ACCESS ram_type;
TYPE ram_stor IS ARRAY (2**addr_bits - 1 DOWNTO 0) OF ram_pntr;
VARIABLE Bank0 : ram_stor;
VARIABLE Bank1 : ram_stor;
VARIABLE Bank2 : ram_stor;
VARIABLE Bank3 : ram_stor;
VARIABLE Row_index, Col_index : INTEGER := 0;
VARIABLE Dq_temp : BIT_VECTOR (data_bits DOWNTO 0) := (OTHERS => '0');
VARIABLE Col_addr : Array4xCBV;
VARIABLE Bank_addr : Array4x2BV;
VARIABLE Dqm_reg0, Dqm_reg1 : BIT_VECTOR (1 DOWNTO 0) := "00";
VARIABLE Bank, Previous_bank : BIT_VECTOR (1 DOWNTO 0) := "00";
VARIABLE B0_row_addr, B1_row_addr, B2_row_addr, B3_row_addr : BIT_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
VARIABLE Col_brst : BIT_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0');
VARIABLE Row : BIT_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
VARIABLE Col : BIT_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0');
VARIABLE Burst_counter : INTEGER := 0;
VARIABLE Command : Array_state;
VARIABLE Bank_precharge : Array4x2BV;
VARIABLE A10_precharge : Array4xB := ('0' & '0' & '0' & '0');
VARIABLE Auto_precharge : Array4xB := ('0' & '0' & '0' & '0');
VARIABLE Read_precharge : Array4xB := ('0' & '0' & '0' & '0');
VARIABLE Write_precharge : Array4xB := ('0' & '0' & '0' & '0');
VARIABLE RW_interrupt_read : Array4xB := ('0' & '0' & '0' & '0');
VARIABLE RW_interrupt_write : Array4xB := ('0' & '0' & '0' & '0');
VARIABLE RW_interrupt_bank : BIT_VECTOR (1 DOWNTO 0) := "00";
VARIABLE Count_time : Array4xT := (0 ns & 0 ns & 0 ns & 0 ns);
VARIABLE Count_precharge : Array4xI := (0 & 0 & 0 & 0);
VARIABLE Data_in_enable, Data_out_enable : BIT := '0';
VARIABLE Pc_b0, Pc_b1, Pc_b2, Pc_b3 : BIT := '0';
VARIABLE Act_b0, Act_b1, Act_b2, Act_b3 : BIT := '0';
-- Timing Check
VARIABLE MRD_chk : INTEGER := 0;
VARIABLE WR_counter : Array4xI := (0 & 0 & 0 & 0);
VARIABLE WR_time : Array4xT := (0 ns & 0 ns & 0 ns & 0 ns);
VARIABLE WR_chkp : Array4xT := (0 ns & 0 ns & 0 ns & 0 ns);
VARIABLE RC_chk, RRD_chk : TIME := 0 ns;
VARIABLE RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3 : TIME := 0 ns;
VARIABLE RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3 : TIME := 0 ns;
VARIABLE RP_chk0, RP_chk1, RP_chk2, RP_chk3 : TIME := 0 ns;
-- Load and Dumb variables
FILE file_load : TEXT open read_mode is fname; -- Data load
FILE file_dump : TEXT open write_mode is "dumpdata.txt"; -- Data dump
VARIABLE bank_load : bit_vector ( 1 DOWNTO 0);
VARIABLE rows_load : BIT_VECTOR (12 DOWNTO 0);
VARIABLE cols_load : BIT_VECTOR ( 8 DOWNTO 0);
VARIABLE data_load : BIT_VECTOR (15 DOWNTO 0);
VARIABLE i, j : INTEGER;
VARIABLE good_load : BOOLEAN;
VARIABLE l : LINE;
variable load : std_logic := '1';
variable dump : std_logic := '0';
variable ch : character;
variable rectype : bit_vector(3 downto 0);
variable recaddr : bit_vector(31 downto 0);
variable reclen : bit_vector(7 downto 0);
variable recdata : bit_vector(0 to 16*8-1);
-- Initialize empty rows
PROCEDURE Init_mem (Bank : bit_vector (1 DOWNTO 0); Row_index : INTEGER) IS
VARIABLE i, j : INTEGER := 0;
BEGIN
IF Bank = "00" THEN
IF Bank0 (Row_index) = NULL THEN -- Check to see if row empty
Bank0 (Row_index) := NEW ram_type; -- Open new row for access
FOR i IN (2**col_bits - 1) DOWNTO 0 LOOP -- Filled row with zeros
FOR j IN (data_bits) DOWNTO 0 LOOP
Bank0 (Row_index) (i) (j) := '0';
END LOOP;
END LOOP;
END IF;
ELSIF Bank = "01" THEN
IF Bank1 (Row_index) = NULL THEN
Bank1 (Row_index) := NEW ram_type;
FOR i IN (2**col_bits - 1) DOWNTO 0 LOOP
FOR j IN (data_bits) DOWNTO 0 LOOP
Bank1 (Row_index) (i) (j) := '0';
END LOOP;
END LOOP;
END IF;
ELSIF Bank = "10" THEN
IF Bank2 (Row_index) = NULL THEN
Bank2 (Row_index) := NEW ram_type;
FOR i IN (2**col_bits - 1) DOWNTO 0 LOOP
FOR j IN (data_bits) DOWNTO 0 LOOP
Bank2 (Row_index) (i) (j) := '0';
END LOOP;
END LOOP;
END IF;
ELSIF Bank = "11" THEN
IF Bank3 (Row_index) = NULL THEN
Bank3 (Row_index) := NEW ram_type;
FOR i IN (2**col_bits - 1) DOWNTO 0 LOOP
FOR j IN (data_bits) DOWNTO 0 LOOP
Bank3 (Row_index) (i) (j) := '0';
END LOOP;
END LOOP;
END IF;
END IF;
END;
-- Burst Counter
PROCEDURE Burst_decode IS
VARIABLE Col_int : INTEGER := 0;
VARIABLE Col_vec, Col_temp : BIT_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- Advance Burst Counter
Burst_counter := Burst_counter + 1;
-- Burst Type
IF Mode_reg (3) = '0' THEN
Col_int := TO_INTEGER(Col);
Col_int := Col_int + 1;
TO_BITVECTOR (Col_int, Col_temp);
ELSIF Mode_reg (3) = '1' THEN
TO_BITVECTOR (Burst_counter, Col_vec);
Col_temp (2) := Col_vec (2) XOR Col_brst (2);
Col_temp (1) := Col_vec (1) XOR Col_brst (1);
Col_temp (0) := Col_vec (0) XOR Col_brst (0);
END IF;
-- Burst Length
IF Burst_length_2 = '1' THEN
Col (0) := Col_temp (0);
ELSIF Burst_length_4 = '1' THEN
Col (1 DOWNTO 0) := Col_temp (1 DOWNTO 0);
ELSIF Burst_length_8 = '1' THEN
Col (2 DOWNTO 0) := Col_temp (2 DOWNTO 0);
ELSE
Col := Col_temp;
END IF;
-- Burst Read Single Write
IF Write_burst_mode = '1' AND Data_in_enable = '1' THEN
Data_in_enable := '0';
END IF;
-- Data counter
IF Burst_length_1 = '1' THEN
IF Burst_counter >= 1 THEN
IF Data_in_enable = '1' THEN
Data_in_enable := '0';
ELSIF Data_out_enable = '1' THEN
Data_out_enable := '0';
END IF;
END IF;
ELSIF Burst_length_2 = '1' THEN
IF Burst_counter >= 2 THEN
IF Data_in_enable = '1' THEN
Data_in_enable := '0';
ELSIF Data_out_enable = '1' THEN
Data_out_enable := '0';
END IF;
END IF;
ELSIF Burst_length_4 = '1' THEN
IF Burst_counter >= 4 THEN
IF Data_in_enable = '1' THEN
Data_in_enable := '0';
ELSIF Data_out_enable = '1' THEN
Data_out_enable := '0';
END IF;
END IF;
ELSIF Burst_length_8 = '1' THEN
IF Burst_counter >= 8 THEN
IF Data_in_enable = '1' THEN
Data_in_enable := '0';
ELSIF Data_out_enable = '1' THEN
Data_out_enable := '0';
END IF;
END IF;
END IF;
END;
BEGIN
WAIT ON Sys_clk, RAS_clk;
IF Sys_clk'event AND Sys_clk = '1' AND Load = '0' AND Dump = '0' THEN --'
-- Internal Command Pipeline
Command(0) := Command(1);
Command(1) := Command(2);
Command(2) := Command(3);
Command(3) := NOP;
Col_addr(0) := Col_addr(1);
Col_addr(1) := Col_addr(2);
Col_addr(2) := Col_addr(3);
Col_addr(3) := (OTHERS => '0');
Bank_addr(0) := Bank_addr(1);
Bank_addr(1) := Bank_addr(2);
Bank_addr(2) := Bank_addr(3);
Bank_addr(3) := "00";
Bank_precharge(0) := Bank_precharge(1);
Bank_precharge(1) := Bank_precharge(2);
Bank_precharge(2) := Bank_precharge(3);
Bank_precharge(3) := "00";
A10_precharge(0) := A10_precharge(1);
A10_precharge(1) := A10_precharge(2);
A10_precharge(2) := A10_precharge(3);
A10_precharge(3) := '0';
-- Operation Decode (Optional for showing current command on posedge clock / debug feature)
IF Active_enable = '1' THEN
Operation <= ACT;
ELSIF Aref_enable = '1' THEN
Operation <= A_REF;
ELSIF Burst_term = '1' THEN
Operation <= BST;
ELSIF Mode_reg_enable = '1' THEN
Operation <= LMR;
ELSIF Prech_enable = '1' THEN
Operation <= PRECH;
ELSIF Read_enable = '1' THEN
IF Addr(10) = '0' THEN
Operation <= READ;
ELSE
Operation <= READ_A;
END IF;
ELSIF Write_enable = '1' THEN
IF Addr(10) = '0' THEN
Operation <= WRITE;
ELSE
Operation <= WRITE_A;
END IF;
ELSE
Operation <= NOP;
END IF;
-- Dqm pipeline for Read
Dqm_reg0 := Dqm_reg1;
Dqm_reg1 := TO_BITVECTOR(Dqm);
-- Read or Write with Auto Precharge Counter
IF Auto_precharge (0) = '1' THEN
Count_precharge (0) := Count_precharge (0) + 1;
END IF;
IF Auto_precharge (1) = '1' THEN
Count_precharge (1) := Count_precharge (1) + 1;
END IF;
IF Auto_precharge (2) = '1' THEN
Count_precharge (2) := Count_precharge (2) + 1;
END IF;
IF Auto_precharge (3) = '1' THEN
Count_precharge (3) := Count_precharge (3) + 1;
END IF;
-- Auto Precharge Timer for tWR
if (Burst_length_1 = '1' OR Write_burst_mode = '1') then
if (Count_precharge(0) = 1) then
Count_time(0) := NOW;
end if;
if (Count_precharge(1) = 1) then
Count_time(1) := NOW;
end if;
if (Count_precharge(2) = 1) then
Count_time(2) := NOW;
end if;
if (Count_precharge(3) = 1) then
Count_time(3) := NOW;
end if;
elsif (Burst_length_2 = '1') then
if (Count_precharge(0) = 2) then
Count_time(0) := NOW;
end if;
if (Count_precharge(1) = 2) then
Count_time(1) := NOW;
end if;
if (Count_precharge(2) = 2) then
Count_time(2) := NOW;
end if;
if (Count_precharge(3) = 2) then
Count_time(3) := NOW;
end if;
elsif (Burst_length_4 = '1') then
if (Count_precharge(0) = 4) then
Count_time(0) := NOW;
end if;
if (Count_precharge(1) = 4) then
Count_time(1) := NOW;
end if;
if (Count_precharge(2) = 4) then
Count_time(2) := NOW;
end if;
if (Count_precharge(3) = 4) then
Count_time(3) := NOW;
end if;
elsif (Burst_length_8 = '1') then
if (Count_precharge(0) = 8) then
Count_time(0) := NOW;
end if;
if (Count_precharge(1) = 8) then
Count_time(1) := NOW;
end if;
if (Count_precharge(2) = 8) then
Count_time(2) := NOW;
end if;
if (Count_precharge(3) = 8) then
Count_time(3) := NOW;
end if;
end if;
-- tMRD Counter
MRD_chk := MRD_chk + 1;
-- tWR Counter
WR_counter(0) := WR_counter(0) + 1;
WR_counter(1) := WR_counter(1) + 1;
WR_counter(2) := WR_counter(2) + 1;
WR_counter(3) := WR_counter(3) + 1;
-- Auto Refresh
IF Aref_enable = '1' THEN
-- Auto Refresh to Auto Refresh
ASSERT (NOW - RC_chk >= tRC)
REPORT "tRC violation during Auto Refresh"
SEVERITY WARNING;
-- Precharge to Auto Refresh
ASSERT (NOW - RP_chk0 >= tRP OR NOW - RP_chk1 >= tRP OR NOW - RP_chk2 >= tRP OR NOW - RP_chk3 >= tRP)
REPORT "tRP violation during Auto Refresh"
SEVERITY WARNING;
-- All banks must be idle before refresh
IF (Pc_b3 ='0' OR Pc_b2 = '0' OR Pc_b1 ='0' OR Pc_b0 = '0') THEN
ASSERT (FALSE)
REPORT "All banks must be Precharge before Auto Refresh"
SEVERITY WARNING;
END IF;
-- Record current tRC time
RC_chk := NOW;
END IF;
-- Load Mode Register
IF Mode_reg_enable = '1' THEN
Mode_reg <= TO_BITVECTOR (Addr);
IF (Pc_b3 ='0' OR Pc_b2 = '0' OR Pc_b1 ='0' OR Pc_b0 = '0') THEN
ASSERT (FALSE)
REPORT "All bank must be Precharge before Load Mode Register"
SEVERITY WARNING;
END IF;
-- REF to LMR
ASSERT (NOW - RC_chk >= tRC)
REPORT "tRC violation during Load Mode Register"
SEVERITY WARNING;
-- LMR to LMR
ASSERT (MRD_chk >= tMRD)
REPORT "tMRD violation during Load Mode Register"
SEVERITY WARNING;
-- Record current tMRD time
MRD_chk := 0;
END IF;
-- Active Block (latch Bank and Row Address)
IF Active_enable = '1' THEN
IF Ba = "00" AND Pc_b0 = '1' THEN
Act_b0 := '1';
Pc_b0 := '0';
B0_row_addr := TO_BITVECTOR (Addr);
RCD_chk0 := NOW;
RAS_chk0 := NOW;
-- Precharge to Active Bank 0
ASSERT (NOW - RP_chk0 >= tRP)
REPORT "tRP violation during Activate Bank 0"
SEVERITY WARNING;
ELSIF Ba = "01" AND Pc_b1 = '1' THEN
Act_b1 := '1';
Pc_b1 := '0';
B1_row_addr := TO_BITVECTOR (Addr);
RCD_chk1 := NOW;
RAS_chk1 := NOW;
-- Precharge to Active Bank 1
ASSERT (NOW - RP_chk1 >= tRP)
REPORT "tRP violation during Activate Bank 1"
SEVERITY WARNING;
ELSIF Ba = "10" AND Pc_b2 = '1' THEN
Act_b2 := '1';
Pc_b2 := '0';
B2_row_addr := TO_BITVECTOR (Addr);
RCD_chk2 := NOW;
RAS_chk2 := NOW;
-- Precharge to Active Bank 2
ASSERT (NOW - RP_chk2 >= tRP)
REPORT "tRP violation during Activate Bank 2"
SEVERITY WARNING;
ELSIF Ba = "11" AND Pc_b3 = '1' THEN
Act_b3 := '1';
Pc_b3 := '0';
B3_row_addr := TO_BITVECTOR (Addr);
RCD_chk3 := NOW;
RAS_chk3 := NOW;
-- Precharge to Active Bank 3
ASSERT (NOW - RP_chk3 >= tRP)
REPORT "tRP violation during Activate Bank 3"
SEVERITY WARNING;
ELSIF Ba = "00" AND Pc_b0 = '0' THEN
ASSERT (FALSE)
REPORT "Bank 0 is not Precharged"
SEVERITY WARNING;
ELSIF Ba = "01" AND Pc_b1 = '0' THEN
ASSERT (FALSE)
REPORT "Bank 1 is not Precharged"
SEVERITY WARNING;
ELSIF Ba = "10" AND Pc_b2 = '0' THEN
ASSERT (FALSE)
REPORT "Bank 2 is not Precharged"
SEVERITY WARNING;
ELSIF Ba = "11" AND Pc_b3 = '0' THEN
ASSERT (FALSE)
REPORT "Bank 3 is not Precharged"
SEVERITY WARNING;
END IF;
-- Active Bank A to Active Bank B
IF ((Previous_bank /= TO_BITVECTOR (Ba)) AND (NOW - RRD_chk < tRRD)) THEN
ASSERT (FALSE)
REPORT "tRRD violation during Activate"
SEVERITY WARNING;
END IF;
-- LMR to ACT
ASSERT (MRD_chk >= tMRD)
REPORT "tMRD violation during Activate"
SEVERITY WARNING;
-- AutoRefresh to Activate
ASSERT (NOW - RC_chk >= tRC)
REPORT "tRC violation during Activate"
SEVERITY WARNING;
-- Record variable for checking violation
RRD_chk := NOW;
Previous_bank := TO_BITVECTOR (Ba);
END IF;
-- Precharge Block
IF Prech_enable = '1' THEN
IF Addr(10) = '1' THEN
Pc_b0 := '1';
Pc_b1 := '1';
Pc_b2 := '1';
Pc_b3 := '1';
Act_b0 := '0';
Act_b1 := '0';
Act_b2 := '0';
Act_b3 := '0';
RP_chk0 := NOW;
RP_chk1 := NOW;
RP_chk2 := NOW;
RP_chk3 := NOW;
-- Activate to Precharge all banks
ASSERT ((NOW - RAS_chk0 >= tRAS) OR (NOW - RAS_chk1 >= tRAS))
REPORT "tRAS violation during Precharge all banks"
SEVERITY WARNING;
-- tWR violation check for Write
IF ((NOW - WR_chkp(0) < tWRp) OR (NOW - WR_chkp(1) < tWRp) OR
(NOW - WR_chkp(2) < tWRp) OR (NOW - WR_chkp(3) < tWRp)) THEN
ASSERT (FALSE)
REPORT "tWR violation during Precharge ALL banks"
SEVERITY WARNING;
END IF;
ELSIF Addr(10) = '0' THEN
IF Ba = "00" THEN
Pc_b0 := '1';
Act_b0 := '0';
RP_chk0 := NOW;
-- Activate to Precharge bank 0
ASSERT (NOW - RAS_chk0 >= tRAS)
REPORT "tRAS violation during Precharge bank 0"
SEVERITY WARNING;
ELSIF Ba = "01" THEN
Pc_b1 := '1';
Act_b1 := '0';
RP_chk1 := NOW;
-- Activate to Precharge bank 1
ASSERT (NOW - RAS_chk1 >= tRAS)
REPORT "tRAS violation during Precharge bank 1"
SEVERITY WARNING;
ELSIF Ba = "10" THEN
Pc_b2 := '1';
Act_b2 := '0';
RP_chk2 := NOW;
-- Activate to Precharge bank 2
ASSERT (NOW - RAS_chk2 >= tRAS)
REPORT "tRAS violation during Precharge bank 2"
SEVERITY WARNING;
ELSIF Ba = "11" THEN
Pc_b3 := '1';
Act_b3 := '0';
RP_chk3 := NOW;
-- Activate to Precharge bank 3
ASSERT (NOW - RAS_chk3 >= tRAS)
REPORT "tRAS violation during Precharge bank 3"
SEVERITY WARNING;
END IF;
-- tWR violation check for Write
ASSERT (NOW - WR_chkp(TO_INTEGER(Ba)) >= tWRp)
REPORT "tWR violation during Precharge"
SEVERITY WARNING;
END IF;
-- Terminate a Write Immediately (if same bank or all banks)
IF (Data_in_enable = '1' AND (Bank = TO_BITVECTOR(Ba) OR Addr(10) = '1')) THEN
Data_in_enable := '0';
END IF;
-- Precharge Command Pipeline for READ
IF CAS_latency_3 = '1' THEN
Command(2) := PRECH;
Bank_precharge(2) := TO_BITVECTOR (Ba);
A10_precharge(2) := TO_BIT(Addr(10));
ELSIF CAS_latency_2 = '1' THEN
Command(1) := PRECH;
Bank_precharge(1) := TO_BITVECTOR (Ba);
A10_precharge(1) := TO_BIT(Addr(10));
END IF;
END IF;
-- Burst Terminate
IF Burst_term = '1' THEN
-- Terminate a Write immediately
IF Data_in_enable = '1' THEN
Data_in_enable := '0';
END IF;
-- Terminate a Read depend on CAS Latency
IF CAS_latency_3 = '1' THEN
Command(2) := BST;
ELSIF CAS_latency_2 = '1' THEN
Command(1) := BST;
END IF;
END IF;
-- Read, Write, Column Latch
IF Read_enable = '1' OR Write_enable = '1' THEN
-- Check to see if bank is open (ACT) for Read or Write
IF ((Ba="00" AND Pc_b0='1') OR (Ba="01" AND Pc_b1='1') OR (Ba="10" AND Pc_b2='1') OR (Ba="11" AND Pc_b3='1')) THEN
ASSERT (FALSE)
REPORT "Cannot Read or Write - Bank is not Activated"
SEVERITY WARNING;
END IF;
-- Activate to Read or Write
IF Ba = "00" THEN
ASSERT (NOW - RCD_chk0 >= tRCD)
REPORT "tRCD violation during Read or Write to Bank 0"
SEVERITY WARNING;
ELSIF Ba = "01" THEN
ASSERT (NOW - RCD_chk1 >= tRCD)
REPORT "tRCD violation during Read or Write to Bank 1"
SEVERITY WARNING;
ELSIF Ba = "10" THEN
ASSERT (NOW - RCD_chk2 >= tRCD)
REPORT "tRCD violation during Read or Write to Bank 2"
SEVERITY WARNING;
ELSIF Ba = "11" THEN
ASSERT (NOW - RCD_chk3 >= tRCD)
REPORT "tRCD violation during Read or Write to Bank 3"
SEVERITY WARNING;
END IF;
-- Read Command
IF Read_enable = '1' THEN
-- CAS Latency Pipeline
IF Cas_latency_3 = '1' THEN
IF Addr(10) = '1' THEN
Command(2) := READ_A;
ELSE
Command(2) := READ;
END IF;
Col_addr (2) := TO_BITVECTOR (Addr(col_bits - 1 DOWNTO 0));
Bank_addr (2) := TO_BITVECTOR (Ba);
ELSIF Cas_latency_2 = '1' THEN
IF Addr(10) = '1' THEN
Command(1) := READ_A;
ELSE
Command(1) := READ;
END IF;
Col_addr (1) := TO_BITVECTOR (Addr(col_bits - 1 DOWNTO 0));
Bank_addr (1) := TO_BITVECTOR (Ba);
END IF;
-- Read intterupt a Write (terminate Write immediately)
IF Data_in_enable = '1' THEN
Data_in_enable := '0';
END IF;
-- Write Command
ELSIF Write_enable = '1' THEN
IF Addr(10) = '1' THEN
Command(0) := WRITE_A;
ELSE
Command(0) := WRITE;
END IF;
Col_addr (0) := TO_BITVECTOR (Addr(col_bits - 1 DOWNTO 0));
Bank_addr (0) := TO_BITVECTOR (Ba);
-- Write intterupt a Write (terminate Write immediately)
IF Data_in_enable = '1' THEN
Data_in_enable := '0';
END IF;
-- Write interrupt a Read (terminate Read immediately)
IF Data_out_enable = '1' THEN
Data_out_enable := '0';
END IF;
END IF;
-- Interrupt a Write with Auto Precharge
IF Auto_precharge(TO_INTEGER(RW_Interrupt_Bank)) = '1' AND Write_precharge(TO_INTEGER(RW_Interrupt_Bank)) = '1' THEN
RW_interrupt_write(TO_INTEGER(RW_Interrupt_Bank)) := '1';
END IF;
-- Interrupt a Read with Auto Precharge
IF Auto_precharge(TO_INTEGER(RW_Interrupt_Bank)) = '1' AND Read_precharge(TO_INTEGER(RW_Interrupt_Bank)) = '1' THEN
RW_interrupt_read(TO_INTEGER(RW_Interrupt_Bank)) := '1';
END IF;
-- Read or Write with Auto Precharge
IF Addr(10) = '1' THEN
Auto_precharge (TO_INTEGER(Ba)) := '1';
Count_precharge (TO_INTEGER(Ba)) := 0;
RW_Interrupt_Bank := TO_BitVector(Ba);
IF Read_enable = '1' THEN
Read_precharge (TO_INTEGER(Ba)) := '1';
ELSIF Write_enable = '1' THEN
Write_precharge (TO_INTEGER(Ba)) := '1';
END IF;
END IF;
END IF;
-- Read with AutoPrecharge Calculation
-- The device start internal precharge when:
-- 1. BL/2 cycles after command
-- and 2. Meet tRAS requirement
-- or 3. Interrupt by a Read or Write (with or without Auto Precharge)
IF ((Auto_precharge(0) = '1') AND (Read_precharge(0) = '1')) THEN
IF (((NOW - RAS_chk0 >= tRAS) AND
((Burst_length_1 = '1' AND Count_precharge(0) >= 1) OR
(Burst_length_2 = '1' AND Count_precharge(0) >= 2) OR
(Burst_length_4 = '1' AND Count_precharge(0) >= 4) OR
(Burst_length_8 = '1' AND Count_precharge(0) >= 8))) OR
(RW_interrupt_read(0) = '1')) THEN
Pc_b0 := '1';
Act_b0 := '0';
RP_chk0 := NOW;
Auto_precharge(0) := '0';
Read_precharge(0) := '0';
RW_interrupt_read(0) := '0';
END IF;
END IF;
IF ((Auto_precharge(1) = '1') AND (Read_precharge(1) = '1')) THEN
IF (((NOW - RAS_chk1 >= tRAS) AND
((Burst_length_1 = '1' AND Count_precharge(1) >= 1) OR
(Burst_length_2 = '1' AND Count_precharge(1) >= 2) OR
(Burst_length_4 = '1' AND Count_precharge(1) >= 4) OR
(Burst_length_8 = '1' AND Count_precharge(1) >= 8))) OR
(RW_interrupt_read(1) = '1')) THEN
Pc_b1 := '1';
Act_b1 := '0';
RP_chk1 := NOW;
Auto_precharge(1) := '0';
Read_precharge(1) := '0';
RW_interrupt_read(1) := '0';
END IF;
END IF;
IF ((Auto_precharge(2) = '1') AND (Read_precharge(2) = '1')) THEN
IF (((NOW - RAS_chk2 >= tRAS) AND
((Burst_length_1 = '1' AND Count_precharge(2) >= 1) OR
(Burst_length_2 = '1' AND Count_precharge(2) >= 2) OR
(Burst_length_4 = '1' AND Count_precharge(2) >= 4) OR
(Burst_length_8 = '1' AND Count_precharge(2) >= 8))) OR
(RW_interrupt_read(2) = '1')) THEN
Pc_b2 := '1';
Act_b2 := '0';
RP_chk2 := NOW;
Auto_precharge(2) := '0';
Read_precharge(2) := '0';
RW_interrupt_read(2) := '0';
END IF;
END IF;
IF ((Auto_precharge(3) = '1') AND (Read_precharge(3) = '1')) THEN
IF (((NOW - RAS_chk3 >= tRAS) AND
((Burst_length_1 = '1' AND Count_precharge(3) >= 1) OR
(Burst_length_2 = '1' AND Count_precharge(3) >= 2) OR
(Burst_length_4 = '1' AND Count_precharge(3) >= 4) OR
(Burst_length_8 = '1' AND Count_precharge(3) >= 8))) OR
(RW_interrupt_read(3) = '1')) THEN
Pc_b3 := '1';
Act_b3 := '0';
RP_chk3 := NOW;
Auto_precharge(3) := '0';
Read_precharge(3) := '0';
RW_interrupt_read(3) := '0';
END IF;
END IF;
-- Internal Precharge or Bst
IF Command(0) = PRECH THEN -- PRECH terminate a read if same bank or all banks
IF Bank_precharge(0) = Bank OR A10_precharge(0) = '1' THEN
IF Data_out_enable = '1' THEN
Data_out_enable := '0';
END IF;
END IF;
ELSIF Command(0) = BST THEN -- BST terminate a read regardless of bank
IF Data_out_enable = '1' THEN
Data_out_enable := '0';
END IF;
END IF;
IF Data_out_enable = '0' THEN
Dq <= TRANSPORT (OTHERS => 'Z') AFTER tOH;
END IF;
-- Detect Read or Write Command
IF Command(0) = READ OR Command(0) = READ_A THEN
Bank := Bank_addr (0);
Col := Col_addr (0);
Col_brst := Col_addr (0);
IF Bank_addr (0) = "00" THEN
Row := B0_row_addr;
ELSIF Bank_addr (0) = "01" THEN
Row := B1_row_addr;
ELSIF Bank_addr (0) = "10" THEN
Row := B2_row_addr;
ELSE
Row := B3_row_addr;
END IF;
Burst_counter := 0;
Data_in_enable := '0';
Data_out_enable := '1';
ELSIF Command(0) = WRITE OR Command(0) = WRITE_A THEN
Bank := Bank_addr(0);
Col := Col_addr(0);
Col_brst := Col_addr(0);
IF Bank_addr (0) = "00" THEN
Row := B0_row_addr;
ELSIF Bank_addr (0) = "01" THEN
Row := B1_row_addr;
ELSIF Bank_addr (0) = "10" THEN
Row := B2_row_addr;
ELSE
Row := B3_row_addr;
END IF;
Burst_counter := 0;
Data_in_enable := '1';
Data_out_enable := '0';
END IF;
-- DQ (Driver / Receiver)
Row_index := TO_INTEGER (Row);
Col_index := TO_INTEGER (Col);
IF Data_in_enable = '1' THEN
IF Dqm /= "11" THEN
Init_mem (Bank, Row_index);
IF Bank = "00" THEN
Dq_temp := Bank0 (Row_index) (Col_index);
IF Dqm = "01" THEN
Dq_temp (15 DOWNTO 8) := TO_BITVECTOR (Dq (15 DOWNTO 8));
ELSIF Dqm = "10" THEN
Dq_temp (7 DOWNTO 0) := TO_BITVECTOR (Dq (7 DOWNTO 0));
ELSE
Dq_temp (15 DOWNTO 0) := TO_BITVECTOR (Dq (15 DOWNTO 0));
END IF;
Bank0 (Row_index) (Col_index) := ('1' & Dq_temp(data_bits - 1 DOWNTO 0));
ELSIF Bank = "01" THEN
Dq_temp := Bank1 (Row_index) (Col_index);
IF Dqm = "01" THEN
Dq_temp (15 DOWNTO 8) := TO_BITVECTOR (Dq (15 DOWNTO 8));
ELSIF Dqm = "10" THEN
Dq_temp (7 DOWNTO 0) := TO_BITVECTOR (Dq (7 DOWNTO 0));
ELSE
Dq_temp (15 DOWNTO 0) := TO_BITVECTOR (Dq (15 DOWNTO 0));
END IF;
Bank1 (Row_index) (Col_index) := ('1' & Dq_temp(data_bits - 1 DOWNTO 0));
ELSIF Bank = "10" THEN
Dq_temp := Bank2 (Row_index) (Col_index);
IF Dqm = "01" THEN
Dq_temp (15 DOWNTO 8) := TO_BITVECTOR (Dq (15 DOWNTO 8));
ELSIF Dqm = "10" THEN
Dq_temp (7 DOWNTO 0) := TO_BITVECTOR (Dq (7 DOWNTO 0));
ELSE
Dq_temp (15 DOWNTO 0) := TO_BITVECTOR (Dq (15 DOWNTO 0));
END IF;
Bank2 (Row_index) (Col_index) := ('1' & Dq_temp(data_bits - 1 DOWNTO 0));
ELSIF Bank = "11" THEN
Dq_temp := Bank3 (Row_index) (Col_index);
IF Dqm = "01" THEN
Dq_temp (15 DOWNTO 8) := TO_BITVECTOR (Dq (15 DOWNTO 8));
ELSIF Dqm = "10" THEN
Dq_temp (7 DOWNTO 0) := TO_BITVECTOR (Dq (7 DOWNTO 0));
ELSE
Dq_temp (15 DOWNTO 0) := TO_BITVECTOR (Dq (15 DOWNTO 0));
END IF;
Bank3 (Row_index) (Col_index) := ('1' & Dq_temp(data_bits - 1 DOWNTO 0));
END IF;
WR_chkp(TO_INTEGER(Bank)) := NOW;
WR_counter(TO_INTEGER(Bank)) := 0;
END IF;
Burst_decode;
ELSIF Data_out_enable = '1' THEN
IF Dqm_reg0 /= "11" THEN
Init_mem (Bank, Row_index);
IF Bank = "00" THEN
Dq_temp := Bank0 (Row_index) (Col_index);
IF Dqm_reg0 = "00" THEN
Dq (15 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 0)) AFTER tAC;
ELSIF Dqm_reg0 = "01" THEN
Dq (15 DOWNTO 8) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 8)) AFTER tAC;
Dq (7 DOWNTO 0) <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
ELSIF Dqm_reg0 = "10" THEN
Dq (15 DOWNTO 8) <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
Dq (7 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (7 DOWNTO 0)) AFTER tAC;
END IF;
ELSIF Bank = "01" THEN
Dq_temp := Bank1 (Row_index) (Col_index);
IF Dqm_reg0 = "00" THEN
Dq (15 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 0)) AFTER tAC;
ELSIF Dqm_reg0 = "01" THEN
Dq (15 DOWNTO 8) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 8)) AFTER tAC;
Dq (7 DOWNTO 0) <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
ELSIF Dqm_reg0 = "10" THEN
Dq (15 DOWNTO 8) <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
Dq (7 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (7 DOWNTO 0)) AFTER tAC;
END IF;
ELSIF Bank = "10" THEN
Dq_temp := Bank2 (Row_index) (Col_index);
IF Dqm_reg0 = "00" THEN
Dq (15 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 0)) AFTER tAC;
ELSIF Dqm_reg0 = "01" THEN
Dq (15 DOWNTO 8) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 8)) AFTER tAC;
Dq (7 DOWNTO 0) <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
ELSIF Dqm_reg0 = "10" THEN
Dq (15 DOWNTO 8) <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
Dq (7 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (7 DOWNTO 0)) AFTER tAC;
END IF;
ELSIF Bank = "11" THEN
Dq_temp := Bank3 (Row_index) (Col_index);
IF Dqm_reg0 = "00" THEN
Dq (15 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 0)) AFTER tAC;
ELSIF Dqm_reg0 = "01" THEN
Dq (15 DOWNTO 8) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 8)) AFTER tAC;
Dq (7 DOWNTO 0) <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
ELSIF Dqm_reg0 = "10" THEN
Dq (15 DOWNTO 8) <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
Dq (7 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (7 DOWNTO 0)) AFTER tAC;
END IF;
END IF;
ELSE
Dq <= TRANSPORT (OTHERS => 'Z') AFTER tHZ;
END IF;
Burst_decode;
END IF;
ELSIF Sys_clk'event AND Sys_clk = '1' AND Load = '1' AND Dump = '0' THEN --'
Operation <= LOAD_FILE;
load := '0';
-- ASSERT (FALSE) REPORT "Reading memory array from file. This operation may take several minutes. Please wait..."
-- SEVERITY NOTE;
WHILE NOT endfile(file_load) LOOP
readline(file_load, l);
read(l, ch);
if (ch /= 'S') or (ch /= 's') then
hexread(l, rectype);
hexread(l, reclen);
recaddr := (others => '0');
case rectype is
when "0001" =>
hexread(l, recaddr(15 downto 0));
when "0010" =>
hexread(l, recaddr(23 downto 0));
when "0011" =>
hexread(l, recaddr);
recaddr(31 downto 24) := (others => '0');
when others => next;
end case;
if true then
hexread(l, recdata);
Bank_Load := recaddr(25 downto 24);
Rows_Load := recaddr(23 downto 11);
Cols_Load := recaddr(10 downto 2);
Init_Mem (Bank_Load, To_Integer(Rows_Load));
IF Bank_Load = "00" THEN
for i in 0 to 3 loop
Bank0 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*32+index to i*32+index+15));
end loop;
ELSIF Bank_Load = "01" THEN
for i in 0 to 3 loop
Bank1 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*32+index to i*32+index+15));
end loop;
ELSIF Bank_Load = "10" THEN
for i in 0 to 3 loop
Bank2 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*32+index to i*32+index+15));
end loop;
ELSIF Bank_Load = "11" THEN
for i in 0 to 3 loop
Bank3 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*32+index to i*32+index+15));
end loop;
END IF;
END IF;
END IF;
END LOOP;
ELSIF Sys_clk'event AND Sys_clk = '1' AND Load = '0' AND Dump = '1' THEN --'
Operation <= DUMP_FILE;
ASSERT (FALSE) REPORT "Writing memory array to file. This operation may take several minutes. Please wait..."
SEVERITY NOTE;
WRITE (l, string'("# Micron Technology, Inc. (FILE DUMP / MEMORY DUMP)")); --'
WRITELINE (file_dump, l);
WRITE (l, string'("# BA ROWS COLS DQ")); --'
WRITELINE (file_dump, l);
WRITE (l, string'("# -- ------------- --------- ----------------")); --'
WRITELINE (file_dump, l);
-- Dumping Bank 0
FOR i IN 0 TO 2**addr_bits -1 LOOP
-- Check if ROW is NULL
IF Bank0 (i) /= NULL THEN
For j IN 0 TO 2**col_bits - 1 LOOP
-- Check if COL is NULL
NEXT WHEN Bank0 (i) (j) (data_bits) = '0';
WRITE (l, string'("00"), right, 4); --'
WRITE (l, To_BitVector(Conv_Std_Logic_Vector(i, addr_bits)), right, addr_bits+1);
WRITE (l, To_BitVector(Conv_std_Logic_Vector(j, col_bits)), right, col_bits+1);
WRITE (l, Bank0 (i) (j) (data_bits -1 DOWNTO 0), right, data_bits+1);
WRITELINE (file_dump, l);
END LOOP;
END IF;
END LOOP;
-- Dumping Bank 1
FOR i IN 0 TO 2**addr_bits -1 LOOP
-- Check if ROW is NULL
IF Bank1 (i) /= NULL THEN
For j IN 0 TO 2**col_bits - 1 LOOP
-- Check if COL is NULL
NEXT WHEN Bank1 (i) (j) (data_bits) = '0';
WRITE (l, string'("01"), right, 4); --'
WRITE (l, To_BitVector(Conv_Std_Logic_Vector(i, addr_bits)), right, addr_bits+1);
WRITE (l, To_BitVector(Conv_std_Logic_Vector(j, col_bits)), right, col_bits+1);
WRITE (l, Bank1 (i) (j) (data_bits -1 DOWNTO 0), right, data_bits+1);
WRITELINE (file_dump, l);
END LOOP;
END IF;
END LOOP;
-- Dumping Bank 2
FOR i IN 0 TO 2**addr_bits -1 LOOP
-- Check if ROW is NULL
IF Bank2 (i) /= NULL THEN
For j IN 0 TO 2**col_bits - 1 LOOP
-- Check if COL is NULL
NEXT WHEN Bank2 (i) (j) (data_bits) = '0';
WRITE (l, string'("10"), right, 4); --'
WRITE (l, To_BitVector(Conv_Std_Logic_Vector(i, addr_bits)), right, addr_bits+1);
WRITE (l, To_BitVector(Conv_std_Logic_Vector(j, col_bits)), right, col_bits+1);
WRITE (l, Bank2 (i) (j) (data_bits -1 DOWNTO 0), right, data_bits+1);
WRITELINE (file_dump, l);
END LOOP;
END IF;
END LOOP;
-- Dumping Bank 3
FOR i IN 0 TO 2**addr_bits -1 LOOP
-- Check if ROW is NULL
IF Bank3 (i) /= NULL THEN
For j IN 0 TO 2**col_bits - 1 LOOP
-- Check if COL is NULL
NEXT WHEN Bank3 (i) (j) (data_bits) = '0';
WRITE (l, string'("11"), right, 4); --'
WRITE (l, To_BitVector(Conv_Std_Logic_Vector(i, addr_bits)), right, addr_bits+1);
WRITE (l, To_BitVector(Conv_std_Logic_Vector(j, col_bits)), right, col_bits+1);
WRITE (l, Bank3 (i) (j) (data_bits -1 DOWNTO 0), right, data_bits+1);
WRITELINE (file_dump, l);
END LOOP;
END IF;
END LOOP;
END IF;
-- Write with AutoPrecharge Calculation
-- The device start internal precharge when:
-- 1. tWR cycles after command
-- and 2. Meet tRAS requirement
-- or 3. Interrupt by a Read or Write (with or without Auto Precharge)
IF ((Auto_precharge(0) = '1') AND (Write_precharge(0) = '1')) THEN
IF (((NOW - RAS_chk0 >= tRAS) AND
(((Burst_length_1 = '1' OR Write_burst_mode = '1' ) AND Count_precharge(0) >= 1 AND NOW - Count_time(0) >= tWRa) OR
(Burst_length_2 = '1' AND Count_precharge(0) >= 2 AND NOW - Count_time(0) >= tWRa) OR
(Burst_length_4 = '1' AND Count_precharge(0) >= 4 AND NOW - Count_time(0) >= tWRa) OR
(Burst_length_8 = '1' AND Count_precharge(0) >= 8 AND NOW - Count_time(0) >= tWRa))) OR
(RW_interrupt_write(0) = '1' AND WR_counter(0) >= 1 AND NOW - WR_time(0) >= tWRa)) THEN
Auto_precharge(0) := '0';
Write_precharge(0) := '0';
RW_interrupt_write(0) := '0';
Pc_b0 := '1';
Act_b0 := '0';
RP_chk0 := NOW;
ASSERT FALSE REPORT "Start Internal Precharge Bank 0" SEVERITY NOTE;
END IF;
END IF;
IF ((Auto_precharge(1) = '1') AND (Write_precharge(1) = '1')) THEN
IF (((NOW - RAS_chk1 >= tRAS) AND
(((Burst_length_1 = '1' OR Write_burst_mode = '1' ) AND Count_precharge(1) >= 1 AND NOW - Count_time(1) >= tWRa) OR
(Burst_length_2 = '1' AND Count_precharge(1) >= 2 AND NOW - Count_time(1) >= tWRa) OR
(Burst_length_4 = '1' AND Count_precharge(1) >= 4 AND NOW - Count_time(1) >= tWRa) OR
(Burst_length_8 = '1' AND Count_precharge(1) >= 8 AND NOW - Count_time(1) >= tWRa))) OR
(RW_interrupt_write(1) = '1' AND WR_counter(1) >= 1 AND NOW - WR_time(1) >= tWRa)) THEN
Auto_precharge(1) := '0';
Write_precharge(1) := '0';
RW_interrupt_write(1) := '0';
Pc_b1 := '1';
Act_b1 := '0';
RP_chk1 := NOW;
END IF;
END IF;
IF ((Auto_precharge(2) = '1') AND (Write_precharge(2) = '1')) THEN
IF (((NOW - RAS_chk2 >= tRAS) AND
(((Burst_length_1 = '1' OR Write_burst_mode = '1' ) AND Count_precharge(2) >= 1 AND NOW - Count_time(2) >= tWRa) OR
(Burst_length_2 = '1' AND Count_precharge(2) >= 2 AND NOW - Count_time(2) >= tWRa) OR
(Burst_length_4 = '1' AND Count_precharge(2) >= 4 AND NOW - Count_time(2) >= tWRa) OR
(Burst_length_8 = '1' AND Count_precharge(2) >= 8 AND NOW - Count_time(2) >= tWRa))) OR
(RW_interrupt_write(2) = '1' AND WR_counter(2) >= 1 AND NOW - WR_time(2) >= tWRa)) THEN
Auto_precharge(2) := '0';
Write_precharge(2) := '0';
RW_interrupt_write(2) := '0';
Pc_b2 := '1';
Act_b2 := '0';
RP_chk2 := NOW;
END IF;
END IF;
IF ((Auto_precharge(3) = '1') AND (Write_precharge(3) = '1')) THEN
IF (((NOW - RAS_chk3 >= tRAS) AND
(((Burst_length_1 = '1' OR Write_burst_mode = '1' ) AND Count_precharge(3) >= 1 AND NOW - Count_time(3) >= tWRa) OR
(Burst_length_2 = '1' AND Count_precharge(3) >= 2 AND NOW - Count_time(3) >= tWRa) OR
(Burst_length_4 = '1' AND Count_precharge(3) >= 4 AND NOW - Count_time(3) >= tWRa) OR
(Burst_length_8 = '1' AND Count_precharge(3) >= 8 AND NOW - Count_time(3) >= tWRa))) OR
(RW_interrupt_write(0) = '1' AND WR_counter(0) >= 1 AND NOW - WR_time(3) >= tWRa)) THEN
Auto_precharge(3) := '0';
Write_precharge(3) := '0';
RW_interrupt_write(3) := '0';
Pc_b3 := '1';
Act_b3 := '0';
RP_chk3 := NOW;
END IF;
END IF;
-- Checking internal wires (Optional for debug purpose)
Pre_chk (0) <= Pc_b0;
Pre_chk (1) <= Pc_b1;
Pre_chk (2) <= Pc_b2;
Pre_chk (3) <= Pc_b3;
Act_chk (0) <= Act_b0;
Act_chk (1) <= Act_b1;
Act_chk (2) <= Act_b2;
Act_chk (3) <= Act_b3;
Dq_in_chk <= Data_in_enable;
Dq_out_chk <= Data_out_enable;
Bank_chk <= Bank;
Row_chk <= Row;
Col_chk <= Col;
END PROCESS;
-- Clock timing checks
-- Clock_check : PROCESS
-- VARIABLE Clk_low, Clk_high : TIME := 0 ns;
-- BEGIN
-- WAIT ON Clk;
-- IF (Clk = '1' AND NOW >= 10 ns) THEN
-- ASSERT (NOW - Clk_low >= tCL)
-- REPORT "tCL violation"
-- SEVERITY WARNING;
-- ASSERT (NOW - Clk_high >= tCK)
-- REPORT "tCK violation"
-- SEVERITY WARNING;
-- Clk_high := NOW;
-- ELSIF (Clk = '0' AND NOW /= 0 ns) THEN
-- ASSERT (NOW - Clk_high >= tCH)
-- REPORT "tCH violation"
-- SEVERITY WARNING;
-- Clk_low := NOW;
-- END IF;
-- END PROCESS;
-- Setup timing checks
Setup_check : PROCESS
BEGIN
wait;
WAIT ON Clk;
IF Clk = '1' THEN
ASSERT(Cke'LAST_EVENT >= tCKS) --'
REPORT "CKE Setup time violation -- tCKS"
SEVERITY WARNING;
ASSERT(Cs_n'LAST_EVENT >= tCMS) --'
REPORT "CS# Setup time violation -- tCMS"
SEVERITY WARNING;
ASSERT(Cas_n'LAST_EVENT >= tCMS) --'
REPORT "CAS# Setup time violation -- tCMS"
SEVERITY WARNING;
ASSERT(Ras_n'LAST_EVENT >= tCMS) --'
REPORT "RAS# Setup time violation -- tCMS"
SEVERITY WARNING;
ASSERT(We_n'LAST_EVENT >= tCMS) --'
REPORT "WE# Setup time violation -- tCMS"
SEVERITY WARNING;
ASSERT(Dqm'LAST_EVENT >= tCMS) --'
REPORT "Dqm Setup time violation -- tCMS"
SEVERITY WARNING;
ASSERT(Addr'LAST_EVENT >= tAS) --'
REPORT "ADDR Setup time violation -- tAS"
SEVERITY WARNING;
ASSERT(Ba'LAST_EVENT >= tAS) --'
REPORT "BA Setup time violation -- tAS"
SEVERITY WARNING;
ASSERT(Dq'LAST_EVENT >= tDS) --'
REPORT "Dq Setup time violation -- tDS"
SEVERITY WARNING;
END IF;
END PROCESS;
-- Hold timing checks
Hold_check : PROCESS
BEGIN
wait;
WAIT ON Clk'DELAYED (tCKH), Clk'DELAYED (tCMH), Clk'DELAYED (tAH), Clk'DELAYED (tDH);
IF Clk'DELAYED (tCKH) = '1' THEN --'
ASSERT(Cke'LAST_EVENT > tCKH) --'
REPORT "CKE Hold time violation -- tCKH"
SEVERITY WARNING;
END IF;
IF Clk'DELAYED (tCMH) = '1' THEN --'
ASSERT(Cs_n'LAST_EVENT > tCMH) --'
REPORT "CS# Hold time violation -- tCMH"
SEVERITY WARNING;
ASSERT(Cas_n'LAST_EVENT > tCMH) --'
REPORT "CAS# Hold time violation -- tCMH"
SEVERITY WARNING;
ASSERT(Ras_n'LAST_EVENT > tCMH) --'
REPORT "RAS# Hold time violation -- tCMH"
SEVERITY WARNING;
ASSERT(We_n'LAST_EVENT > tCMH) --'
REPORT "WE# Hold time violation -- tCMH"
SEVERITY WARNING;
ASSERT(Dqm'LAST_EVENT > tCMH) --'
REPORT "Dqm Hold time violation -- tCMH"
SEVERITY WARNING;
END IF;
IF Clk'DELAYED (tAH) = '1' THEN --'
ASSERT(Addr'LAST_EVENT > tAH) --'
REPORT "ADDR Hold time violation -- tAH"
SEVERITY WARNING;
ASSERT(Ba'LAST_EVENT > tAH) --'
REPORT "BA Hold time violation -- tAH"
SEVERITY WARNING;
END IF;
IF Clk'DELAYED (tDH) = '1' THEN --'
ASSERT(Dq'LAST_EVENT > tDH) --'
REPORT "Dq Hold time violation -- tDH"
SEVERITY WARNING;
END IF;
END PROCESS;
END behave;
-- pragma translate_on
| mit | db14e47d3705f09507ac7f98af49f2ad | 0.429989 | 4.101785 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/techmap/stratixii/usbhc_stratixiipkg.vhd | 2 | 30,526 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: usbhc_stratixiipkg
-- File: usbhc_stratixiipkg.vhd
-- Author: Jonas Ekergarn - Gaisler Research
-- Description: Component declartions for the tech wrapper for
-- stratixii/altera usbhc netlists
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package usbhc_stratixiipkg is
component usbhc_stratixii_comb0
port (
clk : in std_ulogic;
uclk : in std_ulogic;
rst : in std_ulogic;
ursti : in std_ulogic;
-- EHC apb_slv_in_type unwrapped
ehc_apbsi_psel : in std_ulogic;
ehc_apbsi_penable : in std_ulogic;
ehc_apbsi_paddr : in std_logic_vector(31 downto 0);
ehc_apbsi_pwrite : in std_ulogic;
ehc_apbsi_pwdata : in std_logic_vector(31 downto 0);
ehc_apbsi_testen : in std_ulogic;
ehc_apbsi_testrst : in std_ulogic;
ehc_apbsi_scanen : in std_ulogic;
-- EHC apb_slv_out_type unwrapped
ehc_apbso_prdata : out std_logic_vector(31 downto 0);
ehc_apbso_pirq : out std_ulogic;
-- EHC/UHC ahb_mst_in_type unwrapped
ahbmi_hgrant : in std_logic_vector(1*1 downto 0);
ahbmi_hready : in std_ulogic;
ahbmi_hresp : in std_logic_vector(1 downto 0);
ahbmi_hrdata : in std_logic_vector(31 downto 0);
ahbmi_hcache : in std_ulogic;
ahbmi_testen : in std_ulogic;
ahbmi_testrst : in std_ulogic;
ahbmi_scanen : in std_ulogic;
-- UHC ahb_slv_in_type unwrapped
uhc_ahbsi_hsel : in std_logic_vector(1*1 downto 1*1);
uhc_ahbsi_haddr : in std_logic_vector(31 downto 0);
uhc_ahbsi_hwrite : in std_ulogic;
uhc_ahbsi_htrans : in std_logic_vector(1 downto 0);
uhc_ahbsi_hsize : in std_logic_vector(2 downto 0);
uhc_ahbsi_hwdata : in std_logic_vector(31 downto 0);
uhc_ahbsi_hready : in std_ulogic;
uhc_ahbsi_testen : in std_ulogic;
uhc_ahbsi_testrst : in std_ulogic;
uhc_ahbsi_scanen : in std_ulogic;
-- EHC ahb_mst_out_type_unwrapped
ehc_ahbmo_hbusreq : out std_ulogic;
ehc_ahbmo_hlock : out std_ulogic;
ehc_ahbmo_htrans : out std_logic_vector(1 downto 0);
ehc_ahbmo_haddr : out std_logic_vector(31 downto 0);
ehc_ahbmo_hwrite : out std_ulogic;
ehc_ahbmo_hsize : out std_logic_vector(2 downto 0);
ehc_ahbmo_hburst : out std_logic_vector(2 downto 0);
ehc_ahbmo_hprot : out std_logic_vector(3 downto 0);
ehc_ahbmo_hwdata : out std_logic_vector(31 downto 0);
-- UHC ahb_mst_out_vector_type unwrapped
uhc_ahbmo_hbusreq : out std_logic_vector(1*1 downto 1*1);
uhc_ahbmo_hlock : out std_logic_vector(1*1 downto 1*1);
uhc_ahbmo_htrans : out std_logic_vector((1*2)*1 downto 1*1);
uhc_ahbmo_haddr : out std_logic_vector((1*32)*1 downto 1*1);
uhc_ahbmo_hwrite : out std_logic_vector(1*1 downto 1*1);
uhc_ahbmo_hsize : out std_logic_vector((1*3)*1 downto 1*1);
uhc_ahbmo_hburst : out std_logic_vector((1*3)*1 downto 1*1);
uhc_ahbmo_hprot : out std_logic_vector((1*4)*1 downto 1*1);
uhc_ahbmo_hwdata : out std_logic_vector((1*32)*1 downto 1*1);
-- UHC ahb_slv_out_vector_type unwrapped
uhc_ahbso_hready : out std_logic_vector(1*1 downto 1*1);
uhc_ahbso_hresp : out std_logic_vector((1*2)*1 downto 1*1);
uhc_ahbso_hrdata : out std_logic_vector((1*32)*1 downto 1*1);
uhc_ahbso_hsplit : out std_logic_vector((1*16)*1 downto 1*1);
uhc_ahbso_hcache : out std_logic_vector(1*1 downto 1*1);
uhc_ahbso_hirq : out std_logic_vector(1*1 downto 1*1);
-- usbhc_out_type_vector unwrapped
xcvrsel : out std_logic_vector(((1*2)-1) downto 0);
termsel : out std_logic_vector((1-1) downto 0);
suspendm : out std_logic_vector((1-1) downto 0);
opmode : out std_logic_vector(((1*2)-1) downto 0);
txvalid : out std_logic_vector((1-1) downto 0);
drvvbus : out std_logic_vector((1-1) downto 0);
dataho : out std_logic_vector(((1*8)-1) downto 0);
validho : out std_logic_vector((1-1) downto 0);
host : out std_logic_vector((1-1) downto 0);
stp : out std_logic_vector((1-1) downto 0);
datao : out std_logic_vector(((1*8)-1) downto 0);
utm_rst : out std_logic_vector((1-1) downto 0);
dctrlo : out std_logic_vector((1-1) downto 0);
-- usbhc_in_type_vector unwrapped
linestate : in std_logic_vector(((1*2)-1) downto 0);
txready : in std_logic_vector((1-1) downto 0);
rxvalid : in std_logic_vector((1-1) downto 0);
rxactive : in std_logic_vector((1-1) downto 0);
rxerror : in std_logic_vector((1-1) downto 0);
vbusvalid : in std_logic_vector((1-1) downto 0);
datahi : in std_logic_vector(((1*8)-1) downto 0);
validhi : in std_logic_vector((1-1) downto 0);
hostdisc : in std_logic_vector((1-1) downto 0);
nxt : in std_logic_vector((1-1) downto 0);
dir : in std_logic_vector((1-1) downto 0);
datai : in std_logic_vector(((1*8)-1) downto 0);
-- EHC transaction buffer signals
mbc20_tb_addr : out std_logic_vector(8 downto 0);
mbc20_tb_data : out std_logic_vector(31 downto 0);
mbc20_tb_en : out std_ulogic;
mbc20_tb_wel : out std_ulogic;
mbc20_tb_weh : out std_ulogic;
tb_mbc20_data : in std_logic_vector(31 downto 0);
pe20_tb_addr : out std_logic_vector(8 downto 0);
pe20_tb_data : out std_logic_vector(31 downto 0);
pe20_tb_en : out std_ulogic;
pe20_tb_wel : out std_ulogic;
pe20_tb_weh : out std_ulogic;
tb_pe20_data : in std_logic_vector(31 downto 0);
-- EHC packet buffer signals
mbc20_pb_addr : out std_logic_vector(8 downto 0);
mbc20_pb_data : out std_logic_vector(31 downto 0);
mbc20_pb_en : out std_ulogic;
mbc20_pb_we : out std_ulogic;
pb_mbc20_data : in std_logic_vector(31 downto 0);
sie20_pb_addr : out std_logic_vector(8 downto 0);
sie20_pb_data : out std_logic_vector(31 downto 0);
sie20_pb_en : out std_ulogic;
sie20_pb_we : out std_ulogic;
pb_sie20_data : in std_logic_vector(31 downto 0);
-- UHC packet buffer signals
sie11_pb_addr : out std_logic_vector((1*9)*1 downto 1*1);
sie11_pb_data : out std_logic_vector((1*32)*1 downto 1*1);
sie11_pb_en : out std_logic_vector(1*1 downto 1*1);
sie11_pb_we : out std_logic_vector(1*1 downto 1*1);
pb_sie11_data : in std_logic_vector((1*32)*1 downto 1*1);
mbc11_pb_addr : out std_logic_vector((1*9)*1 downto 1*1);
mbc11_pb_data : out std_logic_vector((1*32)*1 downto 1*1);
mbc11_pb_en : out std_logic_vector(1*1 downto 1*1);
mbc11_pb_we : out std_logic_vector(1*1 downto 1*1);
pb_mbc11_data : in std_logic_vector((1*32)*1 downto 1*1);
bufsel : out std_ulogic);
end component;
component usbhc_stratixii_comb1
port (
clk : in std_ulogic;
uclk : in std_ulogic;
rst : in std_ulogic;
ursti : in std_ulogic;
-- EHC apb_slv_in_type unwrapped
ehc_apbsi_psel : in std_ulogic;
ehc_apbsi_penable : in std_ulogic;
ehc_apbsi_paddr : in std_logic_vector(31 downto 0);
ehc_apbsi_pwrite : in std_ulogic;
ehc_apbsi_pwdata : in std_logic_vector(31 downto 0);
ehc_apbsi_testen : in std_ulogic;
ehc_apbsi_testrst : in std_ulogic;
ehc_apbsi_scanen : in std_ulogic;
-- EHC apb_slv_out_type unwrapped
ehc_apbso_prdata : out std_logic_vector(31 downto 0);
ehc_apbso_pirq : out std_ulogic;
-- EHC/UHC ahb_mst_in_type unwrapped
ahbmi_hgrant : in std_logic_vector(1*0 downto 0);
ahbmi_hready : in std_ulogic;
ahbmi_hresp : in std_logic_vector(1 downto 0);
ahbmi_hrdata : in std_logic_vector(31 downto 0);
ahbmi_hcache : in std_ulogic;
ahbmi_testen : in std_ulogic;
ahbmi_testrst : in std_ulogic;
ahbmi_scanen : in std_ulogic;
-- UHC ahb_slv_in_type unwrapped
uhc_ahbsi_hsel : in std_logic_vector(1*0 downto 1*0);
uhc_ahbsi_haddr : in std_logic_vector(31 downto 0);
uhc_ahbsi_hwrite : in std_ulogic;
uhc_ahbsi_htrans : in std_logic_vector(1 downto 0);
uhc_ahbsi_hsize : in std_logic_vector(2 downto 0);
uhc_ahbsi_hwdata : in std_logic_vector(31 downto 0);
uhc_ahbsi_hready : in std_ulogic;
uhc_ahbsi_testen : in std_ulogic;
uhc_ahbsi_testrst : in std_ulogic;
uhc_ahbsi_scanen : in std_ulogic;
-- EHC ahb_mst_out_type_unwrapped
ehc_ahbmo_hbusreq : out std_ulogic;
ehc_ahbmo_hlock : out std_ulogic;
ehc_ahbmo_htrans : out std_logic_vector(1 downto 0);
ehc_ahbmo_haddr : out std_logic_vector(31 downto 0);
ehc_ahbmo_hwrite : out std_ulogic;
ehc_ahbmo_hsize : out std_logic_vector(2 downto 0);
ehc_ahbmo_hburst : out std_logic_vector(2 downto 0);
ehc_ahbmo_hprot : out std_logic_vector(3 downto 0);
ehc_ahbmo_hwdata : out std_logic_vector(31 downto 0);
-- UHC ahb_mst_out_vector_type unwrapped
uhc_ahbmo_hbusreq : out std_logic_vector(1*0 downto 1*0);
uhc_ahbmo_hlock : out std_logic_vector(1*0 downto 1*0);
uhc_ahbmo_htrans : out std_logic_vector((1*2)*0 downto 1*0);
uhc_ahbmo_haddr : out std_logic_vector((1*32)*0 downto 1*0);
uhc_ahbmo_hwrite : out std_logic_vector(1*0 downto 1*0);
uhc_ahbmo_hsize : out std_logic_vector((1*3)*0 downto 1*0);
uhc_ahbmo_hburst : out std_logic_vector((1*3)*0 downto 1*0);
uhc_ahbmo_hprot : out std_logic_vector((1*4)*0 downto 1*0);
uhc_ahbmo_hwdata : out std_logic_vector((1*32)*0 downto 1*0);
-- UHC ahb_slv_out_vector_type unwrapped
uhc_ahbso_hready : out std_logic_vector(1*0 downto 1*0);
uhc_ahbso_hresp : out std_logic_vector((1*2)*0 downto 1*0);
uhc_ahbso_hrdata : out std_logic_vector((1*32)*0 downto 1*0);
uhc_ahbso_hsplit : out std_logic_vector((1*16)*0 downto 1*0);
uhc_ahbso_hcache : out std_logic_vector(1*0 downto 1*0);
uhc_ahbso_hirq : out std_logic_vector(1*0 downto 1*0);
-- usbhc_out_type_vector unwrapped
xcvrsel : out std_logic_vector(((1*2)-1) downto 0);
termsel : out std_logic_vector((1-1) downto 0);
suspendm : out std_logic_vector((1-1) downto 0);
opmode : out std_logic_vector(((1*2)-1) downto 0);
txvalid : out std_logic_vector((1-1) downto 0);
drvvbus : out std_logic_vector((1-1) downto 0);
dataho : out std_logic_vector(((1*8)-1) downto 0);
validho : out std_logic_vector((1-1) downto 0);
host : out std_logic_vector((1-1) downto 0);
stp : out std_logic_vector((1-1) downto 0);
datao : out std_logic_vector(((1*8)-1) downto 0);
utm_rst : out std_logic_vector((1-1) downto 0);
dctrlo : out std_logic_vector((1-1) downto 0);
-- usbhc_in_type_vector unwrapped
linestate : in std_logic_vector(((1*2)-1) downto 0);
txready : in std_logic_vector((1-1) downto 0);
rxvalid : in std_logic_vector((1-1) downto 0);
rxactive : in std_logic_vector((1-1) downto 0);
rxerror : in std_logic_vector((1-1) downto 0);
vbusvalid : in std_logic_vector((1-1) downto 0);
datahi : in std_logic_vector(((1*8)-1) downto 0);
validhi : in std_logic_vector((1-1) downto 0);
hostdisc : in std_logic_vector((1-1) downto 0);
nxt : in std_logic_vector((1-1) downto 0);
dir : in std_logic_vector((1-1) downto 0);
datai : in std_logic_vector(((1*8)-1) downto 0);
-- EHC transaction buffer signals
mbc20_tb_addr : out std_logic_vector(8 downto 0);
mbc20_tb_data : out std_logic_vector(31 downto 0);
mbc20_tb_en : out std_ulogic;
mbc20_tb_wel : out std_ulogic;
mbc20_tb_weh : out std_ulogic;
tb_mbc20_data : in std_logic_vector(31 downto 0);
pe20_tb_addr : out std_logic_vector(8 downto 0);
pe20_tb_data : out std_logic_vector(31 downto 0);
pe20_tb_en : out std_ulogic;
pe20_tb_wel : out std_ulogic;
pe20_tb_weh : out std_ulogic;
tb_pe20_data : in std_logic_vector(31 downto 0);
-- EHC packet buffer signals
mbc20_pb_addr : out std_logic_vector(8 downto 0);
mbc20_pb_data : out std_logic_vector(31 downto 0);
mbc20_pb_en : out std_ulogic;
mbc20_pb_we : out std_ulogic;
pb_mbc20_data : in std_logic_vector(31 downto 0);
sie20_pb_addr : out std_logic_vector(8 downto 0);
sie20_pb_data : out std_logic_vector(31 downto 0);
sie20_pb_en : out std_ulogic;
sie20_pb_we : out std_ulogic;
pb_sie20_data : in std_logic_vector(31 downto 0);
-- UHC packet buffer signals
sie11_pb_addr : out std_logic_vector((1*9)*0 downto 1*0);
sie11_pb_data : out std_logic_vector((1*32)*0 downto 1*0);
sie11_pb_en : out std_logic_vector(1*0 downto 1*0);
sie11_pb_we : out std_logic_vector(1*0 downto 1*0);
pb_sie11_data : in std_logic_vector((1*32)*0 downto 1*0);
mbc11_pb_addr : out std_logic_vector((1*9)*0 downto 1*0);
mbc11_pb_data : out std_logic_vector((1*32)*0 downto 1*0);
mbc11_pb_en : out std_logic_vector(1*0 downto 1*0);
mbc11_pb_we : out std_logic_vector(1*0 downto 1*0);
pb_mbc11_data : in std_logic_vector((1*32)*0 downto 1*0);
bufsel : out std_ulogic);
end component;
component usbhc_stratixii_comb2
port (
clk : in std_ulogic;
uclk : in std_ulogic;
rst : in std_ulogic;
ursti : in std_ulogic;
-- EHC apb_slv_in_type unwrapped
ehc_apbsi_psel : in std_ulogic;
ehc_apbsi_penable : in std_ulogic;
ehc_apbsi_paddr : in std_logic_vector(31 downto 0);
ehc_apbsi_pwrite : in std_ulogic;
ehc_apbsi_pwdata : in std_logic_vector(31 downto 0);
ehc_apbsi_testen : in std_ulogic;
ehc_apbsi_testrst : in std_ulogic;
ehc_apbsi_scanen : in std_ulogic;
-- EHC apb_slv_out_type unwrapped
ehc_apbso_prdata : out std_logic_vector(31 downto 0);
ehc_apbso_pirq : out std_ulogic;
-- EHC/UHC ahb_mst_in_type unwrapped
ahbmi_hgrant : in std_logic_vector(1*1 downto 0);
ahbmi_hready : in std_ulogic;
ahbmi_hresp : in std_logic_vector(1 downto 0);
ahbmi_hrdata : in std_logic_vector(31 downto 0);
ahbmi_hcache : in std_ulogic;
ahbmi_testen : in std_ulogic;
ahbmi_testrst : in std_ulogic;
ahbmi_scanen : in std_ulogic;
-- UHC ahb_slv_in_type unwrapped
uhc_ahbsi_hsel : in std_logic_vector(1*1 downto 1*1);
uhc_ahbsi_haddr : in std_logic_vector(31 downto 0);
uhc_ahbsi_hwrite : in std_ulogic;
uhc_ahbsi_htrans : in std_logic_vector(1 downto 0);
uhc_ahbsi_hsize : in std_logic_vector(2 downto 0);
uhc_ahbsi_hwdata : in std_logic_vector(31 downto 0);
uhc_ahbsi_hready : in std_ulogic;
uhc_ahbsi_testen : in std_ulogic;
uhc_ahbsi_testrst : in std_ulogic;
uhc_ahbsi_scanen : in std_ulogic;
-- EHC ahb_mst_out_type_unwrapped
ehc_ahbmo_hbusreq : out std_ulogic;
ehc_ahbmo_hlock : out std_ulogic;
ehc_ahbmo_htrans : out std_logic_vector(1 downto 0);
ehc_ahbmo_haddr : out std_logic_vector(31 downto 0);
ehc_ahbmo_hwrite : out std_ulogic;
ehc_ahbmo_hsize : out std_logic_vector(2 downto 0);
ehc_ahbmo_hburst : out std_logic_vector(2 downto 0);
ehc_ahbmo_hprot : out std_logic_vector(3 downto 0);
ehc_ahbmo_hwdata : out std_logic_vector(31 downto 0);
-- UHC ahb_mst_out_vector_type unwrapped
uhc_ahbmo_hbusreq : out std_logic_vector(1*1 downto 1*1);
uhc_ahbmo_hlock : out std_logic_vector(1*1 downto 1*1);
uhc_ahbmo_htrans : out std_logic_vector((1*2)*1 downto 1*1);
uhc_ahbmo_haddr : out std_logic_vector((1*32)*1 downto 1*1);
uhc_ahbmo_hwrite : out std_logic_vector(1*1 downto 1*1);
uhc_ahbmo_hsize : out std_logic_vector((1*3)*1 downto 1*1);
uhc_ahbmo_hburst : out std_logic_vector((1*3)*1 downto 1*1);
uhc_ahbmo_hprot : out std_logic_vector((1*4)*1 downto 1*1);
uhc_ahbmo_hwdata : out std_logic_vector((1*32)*1 downto 1*1);
-- UHC ahb_slv_out_vector_type unwrapped
uhc_ahbso_hready : out std_logic_vector(1*1 downto 1*1);
uhc_ahbso_hresp : out std_logic_vector((1*2)*1 downto 1*1);
uhc_ahbso_hrdata : out std_logic_vector((1*32)*1 downto 1*1);
uhc_ahbso_hsplit : out std_logic_vector((1*16)*1 downto 1*1);
uhc_ahbso_hcache : out std_logic_vector(1*1 downto 1*1);
uhc_ahbso_hirq : out std_logic_vector(1*1 downto 1*1);
-- usbhc_out_type_vector unwrapped
xcvrsel : out std_logic_vector(((1*2)-1) downto 0);
termsel : out std_logic_vector((1-1) downto 0);
suspendm : out std_logic_vector((1-1) downto 0);
opmode : out std_logic_vector(((1*2)-1) downto 0);
txvalid : out std_logic_vector((1-1) downto 0);
drvvbus : out std_logic_vector((1-1) downto 0);
dataho : out std_logic_vector(((1*8)-1) downto 0);
validho : out std_logic_vector((1-1) downto 0);
host : out std_logic_vector((1-1) downto 0);
stp : out std_logic_vector((1-1) downto 0);
datao : out std_logic_vector(((1*8)-1) downto 0);
utm_rst : out std_logic_vector((1-1) downto 0);
dctrlo : out std_logic_vector((1-1) downto 0);
-- usbhc_in_type_vector unwrapped
linestate : in std_logic_vector(((1*2)-1) downto 0);
txready : in std_logic_vector((1-1) downto 0);
rxvalid : in std_logic_vector((1-1) downto 0);
rxactive : in std_logic_vector((1-1) downto 0);
rxerror : in std_logic_vector((1-1) downto 0);
vbusvalid : in std_logic_vector((1-1) downto 0);
datahi : in std_logic_vector(((1*8)-1) downto 0);
validhi : in std_logic_vector((1-1) downto 0);
hostdisc : in std_logic_vector((1-1) downto 0);
nxt : in std_logic_vector((1-1) downto 0);
dir : in std_logic_vector((1-1) downto 0);
datai : in std_logic_vector(((1*8)-1) downto 0);
-- EHC transaction buffer signals
mbc20_tb_addr : out std_logic_vector(8 downto 0);
mbc20_tb_data : out std_logic_vector(31 downto 0);
mbc20_tb_en : out std_ulogic;
mbc20_tb_wel : out std_ulogic;
mbc20_tb_weh : out std_ulogic;
tb_mbc20_data : in std_logic_vector(31 downto 0);
pe20_tb_addr : out std_logic_vector(8 downto 0);
pe20_tb_data : out std_logic_vector(31 downto 0);
pe20_tb_en : out std_ulogic;
pe20_tb_wel : out std_ulogic;
pe20_tb_weh : out std_ulogic;
tb_pe20_data : in std_logic_vector(31 downto 0);
-- EHC packet buffer signals
mbc20_pb_addr : out std_logic_vector(8 downto 0);
mbc20_pb_data : out std_logic_vector(31 downto 0);
mbc20_pb_en : out std_ulogic;
mbc20_pb_we : out std_ulogic;
pb_mbc20_data : in std_logic_vector(31 downto 0);
sie20_pb_addr : out std_logic_vector(8 downto 0);
sie20_pb_data : out std_logic_vector(31 downto 0);
sie20_pb_en : out std_ulogic;
sie20_pb_we : out std_ulogic;
pb_sie20_data : in std_logic_vector(31 downto 0);
-- UHC packet buffer signals
sie11_pb_addr : out std_logic_vector((1*9)*1 downto 1*1);
sie11_pb_data : out std_logic_vector((1*32)*1 downto 1*1);
sie11_pb_en : out std_logic_vector(1*1 downto 1*1);
sie11_pb_we : out std_logic_vector(1*1 downto 1*1);
pb_sie11_data : in std_logic_vector((1*32)*1 downto 1*1);
mbc11_pb_addr : out std_logic_vector((1*9)*1 downto 1*1);
mbc11_pb_data : out std_logic_vector((1*32)*1 downto 1*1);
mbc11_pb_en : out std_logic_vector(1*1 downto 1*1);
mbc11_pb_we : out std_logic_vector(1*1 downto 1*1);
pb_mbc11_data : in std_logic_vector((1*32)*1 downto 1*1);
bufsel : out std_ulogic);
end component;
component usbhc_stratixii_comb3
port (
clk : in std_ulogic;
uclk : in std_ulogic;
rst : in std_ulogic;
ursti : in std_ulogic;
-- EHC apb_slv_in_type unwrapped
ehc_apbsi_psel : in std_ulogic;
ehc_apbsi_penable : in std_ulogic;
ehc_apbsi_paddr : in std_logic_vector(31 downto 0);
ehc_apbsi_pwrite : in std_ulogic;
ehc_apbsi_pwdata : in std_logic_vector(31 downto 0);
ehc_apbsi_testen : in std_ulogic;
ehc_apbsi_testrst : in std_ulogic;
ehc_apbsi_scanen : in std_ulogic;
-- EHC apb_slv_out_type unwrapped
ehc_apbso_prdata : out std_logic_vector(31 downto 0);
ehc_apbso_pirq : out std_ulogic;
-- EHC/UHC ahb_mst_in_type unwrapped
ahbmi_hgrant : in std_logic_vector(1*1 downto 0);
ahbmi_hready : in std_ulogic;
ahbmi_hresp : in std_logic_vector(1 downto 0);
ahbmi_hrdata : in std_logic_vector(31 downto 0);
ahbmi_hcache : in std_ulogic;
ahbmi_testen : in std_ulogic;
ahbmi_testrst : in std_ulogic;
ahbmi_scanen : in std_ulogic;
-- UHC ahb_slv_in_type unwrapped
uhc_ahbsi_hsel : in std_logic_vector(1*1 downto 1*1);
uhc_ahbsi_haddr : in std_logic_vector(31 downto 0);
uhc_ahbsi_hwrite : in std_ulogic;
uhc_ahbsi_htrans : in std_logic_vector(1 downto 0);
uhc_ahbsi_hsize : in std_logic_vector(2 downto 0);
uhc_ahbsi_hwdata : in std_logic_vector(31 downto 0);
uhc_ahbsi_hready : in std_ulogic;
uhc_ahbsi_testen : in std_ulogic;
uhc_ahbsi_testrst : in std_ulogic;
uhc_ahbsi_scanen : in std_ulogic;
-- EHC ahb_mst_out_type_unwrapped
ehc_ahbmo_hbusreq : out std_ulogic;
ehc_ahbmo_hlock : out std_ulogic;
ehc_ahbmo_htrans : out std_logic_vector(1 downto 0);
ehc_ahbmo_haddr : out std_logic_vector(31 downto 0);
ehc_ahbmo_hwrite : out std_ulogic;
ehc_ahbmo_hsize : out std_logic_vector(2 downto 0);
ehc_ahbmo_hburst : out std_logic_vector(2 downto 0);
ehc_ahbmo_hprot : out std_logic_vector(3 downto 0);
ehc_ahbmo_hwdata : out std_logic_vector(31 downto 0);
-- UHC ahb_mst_out_vector_type unwrapped
uhc_ahbmo_hbusreq : out std_logic_vector(1*1 downto 1*1);
uhc_ahbmo_hlock : out std_logic_vector(1*1 downto 1*1);
uhc_ahbmo_htrans : out std_logic_vector((1*2)*1 downto 1*1);
uhc_ahbmo_haddr : out std_logic_vector((1*32)*1 downto 1*1);
uhc_ahbmo_hwrite : out std_logic_vector(1*1 downto 1*1);
uhc_ahbmo_hsize : out std_logic_vector((1*3)*1 downto 1*1);
uhc_ahbmo_hburst : out std_logic_vector((1*3)*1 downto 1*1);
uhc_ahbmo_hprot : out std_logic_vector((1*4)*1 downto 1*1);
uhc_ahbmo_hwdata : out std_logic_vector((1*32)*1 downto 1*1);
-- UHC ahb_slv_out_vector_type unwrapped
uhc_ahbso_hready : out std_logic_vector(1*1 downto 1*1);
uhc_ahbso_hresp : out std_logic_vector((1*2)*1 downto 1*1);
uhc_ahbso_hrdata : out std_logic_vector((1*32)*1 downto 1*1);
uhc_ahbso_hsplit : out std_logic_vector((1*16)*1 downto 1*1);
uhc_ahbso_hcache : out std_logic_vector(1*1 downto 1*1);
uhc_ahbso_hirq : out std_logic_vector(1*1 downto 1*1);
-- usbhc_out_type_vector unwrapped
xcvrsel : out std_logic_vector(((2*2)-1) downto 0);
termsel : out std_logic_vector((2-1) downto 0);
suspendm : out std_logic_vector((2-1) downto 0);
opmode : out std_logic_vector(((2*2)-1) downto 0);
txvalid : out std_logic_vector((2-1) downto 0);
drvvbus : out std_logic_vector((2-1) downto 0);
dataho : out std_logic_vector(((2*8)-1) downto 0);
validho : out std_logic_vector((2-1) downto 0);
host : out std_logic_vector((2-1) downto 0);
stp : out std_logic_vector((2-1) downto 0);
datao : out std_logic_vector(((2*8)-1) downto 0);
utm_rst : out std_logic_vector((2-1) downto 0);
dctrlo : out std_logic_vector((2-1) downto 0);
-- usbhc_in_type_vector unwrapped
linestate : in std_logic_vector(((2*2)-1) downto 0);
txready : in std_logic_vector((2-1) downto 0);
rxvalid : in std_logic_vector((2-1) downto 0);
rxactive : in std_logic_vector((2-1) downto 0);
rxerror : in std_logic_vector((2-1) downto 0);
vbusvalid : in std_logic_vector((2-1) downto 0);
datahi : in std_logic_vector(((2*8)-1) downto 0);
validhi : in std_logic_vector((2-1) downto 0);
hostdisc : in std_logic_vector((2-1) downto 0);
nxt : in std_logic_vector((2-1) downto 0);
dir : in std_logic_vector((2-1) downto 0);
datai : in std_logic_vector(((2*8)-1) downto 0);
-- EHC transaction buffer signals
mbc20_tb_addr : out std_logic_vector(8 downto 0);
mbc20_tb_data : out std_logic_vector(31 downto 0);
mbc20_tb_en : out std_ulogic;
mbc20_tb_wel : out std_ulogic;
mbc20_tb_weh : out std_ulogic;
tb_mbc20_data : in std_logic_vector(31 downto 0);
pe20_tb_addr : out std_logic_vector(8 downto 0);
pe20_tb_data : out std_logic_vector(31 downto 0);
pe20_tb_en : out std_ulogic;
pe20_tb_wel : out std_ulogic;
pe20_tb_weh : out std_ulogic;
tb_pe20_data : in std_logic_vector(31 downto 0);
-- EHC packet buffer signals
mbc20_pb_addr : out std_logic_vector(8 downto 0);
mbc20_pb_data : out std_logic_vector(31 downto 0);
mbc20_pb_en : out std_ulogic;
mbc20_pb_we : out std_ulogic;
pb_mbc20_data : in std_logic_vector(31 downto 0);
sie20_pb_addr : out std_logic_vector(8 downto 0);
sie20_pb_data : out std_logic_vector(31 downto 0);
sie20_pb_en : out std_ulogic;
sie20_pb_we : out std_ulogic;
pb_sie20_data : in std_logic_vector(31 downto 0);
-- UHC packet buffer signals
sie11_pb_addr : out std_logic_vector((1*9)*1 downto 1*1);
sie11_pb_data : out std_logic_vector((1*32)*1 downto 1*1);
sie11_pb_en : out std_logic_vector(1*1 downto 1*1);
sie11_pb_we : out std_logic_vector(1*1 downto 1*1);
pb_sie11_data : in std_logic_vector((1*32)*1 downto 1*1);
mbc11_pb_addr : out std_logic_vector((1*9)*1 downto 1*1);
mbc11_pb_data : out std_logic_vector((1*32)*1 downto 1*1);
mbc11_pb_en : out std_logic_vector(1*1 downto 1*1);
mbc11_pb_we : out std_logic_vector(1*1 downto 1*1);
pb_mbc11_data : in std_logic_vector((1*32)*1 downto 1*1);
bufsel : out std_ulogic);
end component;
function valid_comb (
nports : integer range 1 to 15 := 1;
ehcgen : integer range 0 to 1 := 1;
uhcgen : integer range 0 to 1 := 1;
n_cc : integer range 1 to 15 := 1;
n_pcc : integer range 1 to 15 := 1;
prr : integer range 0 to 1 := 0;
portroute1 : integer := 0;
portroute2 : integer := 0;
endian_conv : integer range 0 to 1 := 1;
be_regs : integer range 0 to 1 := 0;
be_desc : integer range 0 to 1 := 0;
uhcblo : integer range 0 to 255 := 2;
bwrd : integer range 1 to 256 := 16;
utm_type : integer range 0 to 2 := 2;
vbusconf : integer range 0 to 3 := 3;
ramtest : integer range 0 to 1 := 0;
urst_time : integer := 250;
oepol : integer rangeo 0 to 1 := 0)
return boolean;
end usbhc_stratixiipkg;
package body usbhc_stratixiipkg is
function valid_comb (
nports : integer range 1 to 15 := 1;
ehcgen : integer range 0 to 1 := 1;
uhcgen : integer range 0 to 1 := 1;
n_cc : integer range 1 to 15 := 1;
n_pcc : integer range 1 to 15 := 1;
prr : integer range 0 to 1 := 0;
portroute1 : integer := 0;
portroute2 : integer := 0;
endian_conv : integer range 0 to 1 := 1;
be_regs : integer range 0 to 1 := 0;
be_desc : integer range 0 to 1 := 0;
uhcblo : integer range 0 to 255 := 2;
bwrd : integer range 1 to 256 := 16;
utm_type : integer range 0 to 2 := 2;
vbusconf : integer range 0 to 3 := 3;
ramtest : integer range 0 to 1 := 0;
urst_time : integer := 250;
oepol : integer range 0 to 1 := 0)
return boolean is
begin
-- comb0
if nports = 1 and ehcgen = 0 and uhcgen = 1 and n_cc = 1 and
n_pcc = 1 and prr = 0 and portroute1 = 0 and portroute2 = 0 and
endian_conv = 1 and be_regs = 0 and be_desc = 0 and uhcblo = 2 and
bwrd = 16 and utm_type = 2 and vbusconf = 3 and ramtest = 0 and
urst_time = 250 and oepol = 0 then
return true;
end if;
-- comb1
if nports = 1 and ehcgen = 1 and uhcgen = 0 and n_cc = 1 and
n_pcc = 1 and prr = 0 and portroute1 = 0 and portroute2 = 0 and
endian_conv = 1 and be_regs = 0 and be_desc = 0 and uhcblo = 2 and
bwrd = 16 and utm_type = 2 and vbusconf = 3 and ramtest = 0 and
urst_time = 250 and oepol = 0 then
return true;
end if;
-- comb2
if nports = 1 and ehcgen = 1 and uhcgen = 1 and n_cc = 1 and
n_pcc = 1 and prr = 0 and portroute1 = 0 and portroute2 = 0 and
endian_conv = 1 and be_regs = 0 and be_desc = 0 and uhcblo = 2 and
bwrd = 16 and utm_type = 2 and vbusconf = 3 and ramtest = 0 and
urst_time = 250 and oepol = 0 then
return true;
end if;
-- comb3
if nports = 2 and ehcgen = 1 and uhcgen = 1 and n_cc = 1 and
n_pcc = 2 and prr = 0 and portroute1 = 0 and portroute2 = 0 and
endian_conv = 1 and be_regs = 0 and be_desc = 0 and uhcblo = 2 and
bwrd = 16 and utm_type = 2 and vbusconf = 3 and ramtest = 0 and
urst_time = 250 and oepol = 0 then
return true;
end if;
return false;
end valid_comb;
end usbhc_stratixiipkg;
| mit | 1273ac69b1559a0bd168194343b22aba | 0.61292 | 3.085616 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/leon3/mmuconfig.vhd | 2 | 16,283 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: mmuconfig
-- File: mmuconfig.vhd
-- Author: Konrad Eisele, Jiri Gaisler, Gaisler Research
-- Description: MMU types and constants
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library gaisler;
package mmuconfig is
constant M_CTX_SZ : integer := 8;
constant M_ENT_MAX : integer := 64;
constant XM_ENT_MAX_LOG : integer := log2(M_ENT_MAX);
constant M_ENT_MAX_LOG : integer := XM_ENT_MAX_LOG;
type mmu_idcache is (id_icache, id_dcache);
-- ##############################################################
-- 1.0 virtual address [sparc V8: p.243,Appx.H,Figure H-4]
-- +--------+--------+--------+---------------+
-- a) | INDEX1 | INDEX2 | INDEX3 | OFFSET |
-- +--------+--------+--------+---------------+
-- 31 24 23 18 17 12 11 0
constant VA_I1_SZ : integer := 8;
constant VA_I2_SZ : integer := 6;
constant VA_I3_SZ : integer := 6;
constant VA_I_SZ : integer := VA_I1_SZ+VA_I2_SZ+VA_I3_SZ;
constant VA_I_MAX : integer := 8;
constant VA_I1_U : integer := 31;
constant VA_I1_D : integer := 32-VA_I1_SZ;
constant VA_I2_U : integer := 31-VA_I1_SZ;
constant VA_I2_D : integer := 32-VA_I1_SZ-VA_I2_SZ;
constant VA_I3_U : integer := 31-VA_I1_SZ-VA_I2_SZ;
constant VA_I3_D : integer := 32-VA_I_SZ;
constant VA_I_U : integer := 31;
constant VA_I_D : integer := 32-VA_I_SZ;
constant VA_OFF_U : integer := 31-VA_I_SZ;
constant VA_OFF_D : integer := 0;
constant VA_OFFCTX_U : integer := 31;
constant VA_OFFCTX_D : integer := 0;
constant VA_OFFREG_U : integer := 31-VA_I1_SZ;
constant VA_OFFREG_D : integer := 0;
constant VA_OFFSEG_U : integer := 31-VA_I1_SZ-VA_I2_SZ;
constant VA_OFFSEG_D : integer := 0;
constant VA_OFFPAG_U : integer := 31-VA_I_SZ;
constant VA_OFFPAG_D : integer := 0;
-- ##############################################################
-- 2.0 PAGE TABE DESCRIPTOR (PTD) [sparc V8: p.247,Appx.H,Figure H-7]
--
-- +-------------------------------------------------+---+---+
-- | Page Table Pointer (PTP) | 0 | 0 |
-- +-------------------------------------------------+---+---+
-- 31 2 1 0
--
-- 2.1 PAGE TABE ENTRY (PTE) [sparc V8: p.247,Appx.H,Figure H-8]
--
-- +-----------------------------+---+---+---+-----------+---+
-- |Physical Page Number (PPN) | C | M | R | ACC | ET¦
-- +-----------------------------+---+---+---+-----------+---+
-- 31 8 7 6 5 4 2 1 0
--
constant PTD_PTP_U : integer := 31; -- PTD: page table pointer
constant PTD_PTP_D : integer := 2;
constant PTD_PTP32_U : integer := 27; -- PTD: page table pointer 32 bit
constant PTD_PTP32_D : integer := 2;
constant PTE_PPN_U : integer := 31; -- PTE: physical page number
constant PTE_PPN_D : integer := 8;
constant PTE_PPN_S : integer := (PTE_PPN_U+1)-PTE_PPN_D; -- PTE: pysical page number size
constant PTE_PPN32_U : integer := 27; -- PTE: physical page number 32 bit addr
constant PTE_PPN32_D : integer := 8;
constant PTE_PPN32_S : integer := (PTE_PPN32_U+1)-PTE_PPN32_D; -- PTE: pysical page number 32 bit size
constant PTE_PPN32REG_U : integer := PTE_PPN32_U; -- PTE: pte part of merged result address
constant PTE_PPN32REG_D : integer := PTE_PPN32_U+1-VA_I1_SZ;
constant PTE_PPN32SEG_U : integer := PTE_PPN32_U;
constant PTE_PPN32SEG_D : integer := PTE_PPN32_U+1-VA_I1_SZ-VA_I2_SZ;
constant PTE_PPN32PAG_U : integer := PTE_PPN32_U;
constant PTE_PPN32PAG_D : integer := PTE_PPN32_U+1-VA_I_SZ;
constant PTE_C : integer := 7; -- PTE: Cacheable bit
constant PTE_M : integer := 6; -- PTE: Modified bit
constant PTE_R : integer := 5; -- PTE: Reference Bit - a "1" indicates an PTE
constant PTE_ACC_U : integer := 4; -- PTE: Access field
constant PTE_ACC_D : integer := 2;
constant ACC_W : integer := 2; -- PTE::ACC : write permission
constant ACC_E : integer := 3; -- PTE::ACC : exec permission
constant ACC_SU : integer := 4; -- PTE::ACC : privileged
constant PT_ET_U : integer := 1; -- PTD/PTE: PTE Type
constant PT_ET_D : integer := 0;
constant ET_INV : std_logic_vector(1 downto 0) := "00";
constant ET_PTD : std_logic_vector(1 downto 0) := "01";
constant ET_PTE : std_logic_vector(1 downto 0) := "10";
constant ET_RVD : std_logic_vector(1 downto 0) := "11";
constant PADDR_PTD_U : integer := 31;
constant PADDR_PTD_D : integer := 6;
-- ##############################################################
-- 3.0 TLBCAM TAG hardware representation (TTG)
--
type tlbcam_reg is record
ET : std_logic_vector(1 downto 0); -- et field
ACC : std_logic_vector(2 downto 0); -- on flush/probe this will become FPTY
M : std_logic; -- modified
R : std_logic; -- referenced
SU : std_logic; -- equal ACC >= 6
VALID : std_logic;
LVL : std_logic_vector(1 downto 0); -- level in pth
I1 : std_logic_vector(7 downto 0); -- vaddr
I2 : std_logic_vector(5 downto 0);
I3 : std_logic_vector(5 downto 0);
CTX : std_logic_vector(M_CTX_SZ-1 downto 0); -- ctx number
PPN : std_logic_vector(PTE_PPN_S-1 downto 0); -- physical page number
C : std_logic; -- cachable
end record;
constant tlbcam_reg_none : tlbcam_reg := ("00", "000", '0', '0', '0', '0',
"00", "00000000", "000000", "000000", "00000000", (others => '0'), '0');
-- tlbcam_reg::LVL
constant LVL_PAGE : std_logic_vector(1 downto 0) := "00"; -- equal tlbcam_tfp::TYP FPTY_PAGE
constant LVL_SEGMENT : std_logic_vector(1 downto 0) := "01"; -- equal tlbcam_tfp::TYP FPTY_SEGMENT
constant LVL_REGION : std_logic_vector(1 downto 0) := "10"; -- equal tlbcam_tfp::TYP FPTY_REGION
constant LVL_CTX : std_logic_vector(1 downto 0) := "11"; -- equal tlbcam_tfp::TYP FPTY_CTX
-- ##############################################################
-- 4.0 TLBCAM tag i/o for translation/flush/(probe)
--
type tlbcam_tfp is record
TYP : std_logic_vector(2 downto 0); -- f/(p) type
I1 : std_logic_vector(7 downto 0); -- vaddr
I2 : std_logic_vector(5 downto 0);
I3 : std_logic_vector(5 downto 0);
CTX : std_logic_vector(M_CTX_SZ-1 downto 0); -- ctx number
M : std_logic;
end record;
constant tlbcam_tfp_none : tlbcam_tfp := ("000", "00000000", "000000", "000000", "00000000", '0');
--tlbcam_tfp::TYP
constant FPTY_PAGE : std_logic_vector(2 downto 0) := "000"; -- level 3 PTE match I1+I2+I3
constant FPTY_SEGMENT : std_logic_vector(2 downto 0) := "001"; -- level 2/3 PTE/PTD match I1+I2
constant FPTY_REGION : std_logic_vector(2 downto 0) := "010"; -- level 1/2/3 PTE/PTD match I1
constant FPTY_CTX : std_logic_vector(2 downto 0) := "011"; -- level 0/1/2/3 PTE/PTD ctx
constant FPTY_N : std_logic_vector(2 downto 0) := "100"; -- entire tlb
-- ##############################################################
-- 5.0 MMU Control Register [sparc V8: p.253,Appx.H,Figure H-10]
--
-- +-------+-----+------------------+-----+-------+--+--+
-- | IMPL | VER | SC | PSO | resvd |NF|E |
-- +-------+-----+------------------+-----+-------+--+--+
-- 31 28 27 24 23 8 7 6 2 1 0
--
-- MMU Context Pointer [sparc V8: p.254,Appx.H,Figure H-11]
-- +-------------------------------------------+--------+
-- | Context Table Pointer | resvd |
-- +-------------------------------------------+--------+
-- 31 2 1 0
--
-- MMU Context Number [sparc V8: p.255,Appx.H,Figure H-12]
-- +----------------------------------------------------+
-- | Context Table Pointer |
-- +----------------------------------------------------+
-- 31 0
--
-- fault status/address register [sparc V8: p.256,Appx.H,Table H-13/14]
-- +------------+-----+---+----+----+-----+----+
-- | reserved | EBE | L | AT | FT | FAV | OW |
-- +------------+-----+---+----+----+-----+----+
-- 31 18 17 10 9 8 7 5 4 2 1 0
--
-- +----------------------------------------------------+
-- | fault address register |
-- +----------------------------------------------------+
-- 31 0
constant MMCTRL_CTXP_SZ : integer := 30;
constant MMCTRL_PTP32_U : integer := 25;
constant MMCTRL_PTP32_D : integer := 0;
constant MMCTRL_E : integer := 0;
constant MMCTRL_NF : integer := 1;
constant MMCTRL_PSO : integer := 7;
constant MMCTRL_SC_U : integer := 23;
constant MMCTRL_SC_D : integer := 8;
constant MMCTRL_VER_U : integer := 27;
constant MMCTRL_VER_D : integer := 24;
constant MMCTRL_IMPL_U : integer := 31;
constant MMCTRL_IMPL_D : integer := 28;
constant MMCTRL_TLBDIS : integer := 31;
constant MMCTXP_U : integer := 31;
constant MMCTXP_D : integer := 2;
constant MMCTXNR_U : integer := M_CTX_SZ-1;
constant MMCTXNR_D : integer := 0;
constant FS_SZ : integer := 18; -- fault status size
constant FS_EBE_U : integer := 17;
constant FS_EBE_D : integer := 10;
constant FS_L_U : integer := 9;
constant FS_L_D : integer := 8;
constant FS_L_CTX : std_logic_vector(1 downto 0) := "00";
constant FS_L_L1 : std_logic_vector(1 downto 0) := "01";
constant FS_L_L2 : std_logic_vector(1 downto 0) := "10";
constant FS_L_L3 : std_logic_vector(1 downto 0) := "11";
constant FS_AT_U : integer := 7;
constant FS_AT_D : integer := 5;
constant FS_AT_LS : natural := 7; --L=0 S=1
constant FS_AT_ID : natural := 6; --D=0 I=1
constant FS_AT_SU : natural := 5; --U=0 SU=1
constant FS_AT_LUDS : std_logic_vector(2 downto 0) := "000";
constant FS_AT_LSDS : std_logic_vector(2 downto 0) := "001";
constant FS_AT_LUIS : std_logic_vector(2 downto 0) := "010";
constant FS_AT_LSIS : std_logic_vector(2 downto 0) := "011";
constant FS_AT_SUDS : std_logic_vector(2 downto 0) := "100";
constant FS_AT_SSDS : std_logic_vector(2 downto 0) := "101";
constant FS_AT_SUIS : std_logic_vector(2 downto 0) := "110";
constant FS_AT_SSIS : std_logic_vector(2 downto 0) := "111";
constant FS_FT_U : integer := 4;
constant FS_FT_D : integer := 2;
constant FS_FT_NONE : std_logic_vector(2 downto 0) := "000";
constant FS_FT_INV : std_logic_vector(2 downto 0) := "001";
constant FS_FT_PRO : std_logic_vector(2 downto 0) := "010";
constant FS_FT_PRI : std_logic_vector(2 downto 0) := "011";
constant FS_FT_TRANS : std_logic_vector(2 downto 0):= "110";
constant FS_FT_BUS : std_logic_vector(2 downto 0) := "101";
constant FS_FT_INT : std_logic_vector(2 downto 0) := "110";
constant FS_FT_RVD : std_logic_vector(2 downto 0) := "111";
constant FS_FAV : natural := 1;
constant FS_OW : natural := 0;
--# mmu ctrl reg
type mmctrl_type1 is record
e : std_logic; -- enable
nf : std_logic; -- no fault
pso : std_logic; -- partial store order
-- pre : std_logic; -- pretranslation source
-- pri : std_logic; -- i/d priority
ctx : std_logic_vector(M_CTX_SZ-1 downto 0);-- context nr
ctxp : std_logic_vector(MMCTRL_CTXP_SZ-1 downto 0); -- context table pointer
tlbdis : std_logic; -- tlb disabled
bar : std_logic_vector(1 downto 0); -- preplace barrier
end record;
--# fault status reg
type mmctrl_fs_type is record
ow : std_logic;
fav : std_logic;
ft : std_logic_vector(2 downto 0); -- fault type
at_ls : std_logic; -- access type, load/store
at_id : std_logic; -- access type, i/dcache
at_su : std_logic; -- access type, su/user
l : std_logic_vector(1 downto 0); -- level
ebe : std_logic_vector(7 downto 0);
end record;
type mmctrl_type2 is record
fs : mmctrl_fs_type;
valid : std_logic;
fa : std_logic_vector(VA_I_SZ-1 downto 0); -- fault address register
end record;
-- ##############################################################
-- 6. Virtual Flush/Probe address [sparc V8: p.249,Appx.H,Figure H-9]
-- +---------------------------------------+--------+-------+
-- | VIRTUAL FLUSH&Probe Address (VFPA) | type | rvd |
-- +---------------------------------------+--------+-------+
-- 31 12 11 8 7 0
--
--
subtype FPA is natural range 31 downto 12;
constant FPA_I1_U : integer := 31;
constant FPA_I1_D : integer := 24;
constant FPA_I2_U : integer := 23;
constant FPA_I2_D : integer := 18;
constant FPA_I3_U : integer := 17;
constant FPA_I3_D : integer := 12;
constant FPTY_U : integer := 10; -- only 3 bits
constant FPTY_D : integer := 8;
-- ##############################################################
-- 7. control register virtual address [sparc V8: p.253,Appx.H,Table H-5]
-- +---------------------------------+-----+--------+
-- | | CNR | rsvd |
-- +---------------------------------+-----+--------+
-- 31 10 8 7 0
constant CNR_U : integer := 10;
constant CNR_D : integer := 8;
constant CNR_CTRL : std_logic_vector(2 downto 0) := "000";
constant CNR_CTXP : std_logic_vector(2 downto 0) := "001";
constant CNR_CTX : std_logic_vector(2 downto 0) := "010";
constant CNR_F : std_logic_vector(2 downto 0) := "011";
constant CNR_FADDR : std_logic_vector(2 downto 0) := "100";
-- ##############################################################
-- 8. Precise flush (ASI 0x10-14) [sparc V8: p.266,Appx.I]
-- supported: ASI_FLUSH_PAGE
-- ASI_FLUSH_CTX
constant PFLUSH_PAGE : std_logic := '0';
constant PFLUSH_CTX : std_logic := '1';
-- ##############################################################
-- 9. Diagnostic access
--
constant DIAGF_LVL_U : integer := 1;
constant DIAGF_LVL_D : integer := 0;
constant DIAGF_WR : integer := 3;
constant DIAGF_HIT : integer := 4;
constant DIAGF_CTX_U : integer := 12;
constant DIAGF_CTX_D : integer := 5;
constant DIAGF_VALID : integer := 13;
end mmuconfig;
| mit | 8d4204faac895b145141ca16e4319133 | 0.48916 | 3.507755 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | VhdlParser/test/iu3PreLoad.vhd | 1 | 21,304 | package iu3PreLoad is
TYPE log2arr IS ARRAY(0 TO 512) OF integer;
-- CONSTANT log2 : log2arr := (
-- 0,0,1,2,2,3,3,3,3,4,4,4,4,4,4,4,4,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,
-- 6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,
-- 7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,
-- 7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,
-- 8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
-- 8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
-- 8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
-- 8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
-- OTHERS => 9);
-- CONSTANT log2x : log2arr := (
-- 0,1,1,2,2,3,3,3,3,4,4,4,4,4,4,4,4,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,
-- 6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,
-- 7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,
-- 7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,
-- 8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
-- 8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
-- 8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
-- 8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
-- OTHERS => 9);
CONSTANT NTECH : integer := 32;
TYPE tech_ability_type IS ARRAY(0 TO NTECH) OF integer;
CONSTANT inferred : integer := 0;
CONSTANT virtex : integer := 1;
CONSTANT virtex2 : integer := 2;
CONSTANT memvirage : integer := 3;
CONSTANT axcel : integer := 4;
CONSTANT proasic : integer := 5;
CONSTANT atc18s : integer := 6;
CONSTANT altera : integer := 7;
CONSTANT umc : integer := 8;
CONSTANT rhumc : integer := 9;
CONSTANT apa3 : integer := 10;
CONSTANT spartan3 : integer := 11;
CONSTANT ihp25 : integer := 12;
CONSTANT rhlib18t : integer := 13;
CONSTANT virtex4 : integer := 14;
CONSTANT lattice : integer := 15;
CONSTANT ut25 : integer := 16;
CONSTANT spartan3e : integer := 17;
CONSTANT peregrine : integer := 18;
CONSTANT memartisan : integer := 19;
CONSTANT virtex5 : integer := 20;
CONSTANT custom1 : integer := 21;
CONSTANT ihp25rh : integer := 22;
CONSTANT stratix1 : integer := 23;
CONSTANT stratix2 : integer := 24;
CONSTANT eclipse : integer := 25;
CONSTANT stratix3 : integer := 26;
CONSTANT cyclone3 : integer := 27;
CONSTANT memvirage90 : integer := 28;
CONSTANT tsmc90 : integer := 29;
CONSTANT easic90 : integer := 30;
CONSTANT atc18rha : integer := 31;
CONSTANT smic013 : integer := 32;
-- CONSTANT is_fpga : tech_ability_type :=
-- (inferred => 1,
-- virtex => 1,
-- virtex2 => 1,
-- axcel => 1,
-- proasic => 1,
-- altera => 1,
-- apa3 => 1,
-- spartan3 => 1,
-- virtex4 => 1,
-- lattice => 1,
-- spartan3e => 1,
-- virtex5 => 1,
-- stratix1 => 1,
-- stratix2 => 1,
-- eclipse => 1,
-- stratix3 => 1,
-- cyclone3 => 1,
-- others => 0);
Constant zero32 : std_logic_vector(31 downto 0) := X"0000_0000";
CONSTANT zero64 : std_logic_vector(63 downto 0) := X"0000_0000_0000_0000";
CONSTANT one32 : std_logic_vector(31 downto 0) := X"FFFF_FFFF";
-- op decoding (inst(31 downto 30))
subtype op_type is std_logic_vector(1 downto 0);
constant FMT2 : op_type := "00";
constant CALL : op_type := "01";
constant FMT3 : op_type := "10";
constant LDST : op_type := "11";
-- op2 decoding (inst(24 downto 22))
subtype op2_type is std_logic_vector(2 downto 0);
constant UNIMP : op2_type := "000";
constant BICC : op2_type := "010";
constant SETHI : op2_type := "100";
constant FBFCC : op2_type := "110";
constant CBCCC : op2_type := "111";
-- op3 decoding (inst(24 downto 19))
subtype op3_type is std_logic_vector(5 downto 0);
constant IADD : op3_type := "000000";
constant IAND : op3_type := "000001";
constant IOR : op3_type := "000010";
constant IXOR : op3_type := "000011";
constant ISUB : op3_type := "000100";
constant ANDN : op3_type := "000101";
constant ORN : op3_type := "000110";
constant IXNOR : op3_type := "000111";
constant ADDX : op3_type := "001000";
constant UMUL : op3_type := "001010";
constant SMUL : op3_type := "001011";
constant SUBX : op3_type := "001100";
constant UDIV : op3_type := "001110";
constant SDIV : op3_type := "001111";
constant ADDCC : op3_type := "010000";
constant ANDCC : op3_type := "010001";
constant ORCC : op3_type := "010010";
constant XORCC : op3_type := "010011";
constant SUBCC : op3_type := "010100";
constant ANDNCC : op3_type := "010101";
constant ORNCC : op3_type := "010110";
constant XNORCC : op3_type := "010111";
constant ADDXCC : op3_type := "011000";
constant UMULCC : op3_type := "011010";
constant SMULCC : op3_type := "011011";
constant SUBXCC : op3_type := "011100";
constant UDIVCC : op3_type := "011110";
constant SDIVCC : op3_type := "011111";
constant TADDCC : op3_type := "100000";
constant TSUBCC : op3_type := "100001";
constant TADDCCTV : op3_type := "100010";
constant TSUBCCTV : op3_type := "100011";
constant MULSCC : op3_type := "100100";
constant ISLL : op3_type := "100101";
constant ISRL : op3_type := "100110";
constant ISRA : op3_type := "100111";
constant RDY : op3_type := "101000";
constant RDPSR : op3_type := "101001";
constant RDWIM : op3_type := "101010";
constant RDTBR : op3_type := "101011";
constant WRY : op3_type := "110000";
constant WRPSR : op3_type := "110001";
constant WRWIM : op3_type := "110010";
constant WRTBR : op3_type := "110011";
constant FPOP1 : op3_type := "110100";
constant FPOP2 : op3_type := "110101";
constant CPOP1 : op3_type := "110110";
constant CPOP2 : op3_type := "110111";
constant JMPL : op3_type := "111000";
constant TICC : op3_type := "111010";
constant FLUSH : op3_type := "111011";
constant RETT : op3_type := "111001";
constant SAVE : op3_type := "111100";
constant RESTORE : op3_type := "111101";
constant UMAC : op3_type := "111110";
constant SMAC : op3_type := "111111";
constant LD : op3_type := "000000";
constant LDUB : op3_type := "000001";
constant LDUH : op3_type := "000010";
constant LDD : op3_type := "000011";
constant LDSB : op3_type := "001001";
constant LDSH : op3_type := "001010";
constant LDSTUB : op3_type := "001101";
constant SWAP : op3_type := "001111";
constant LDA : op3_type := "010000";
constant LDUBA : op3_type := "010001";
constant LDUHA : op3_type := "010010";
constant LDDA : op3_type := "010011";
constant LDSBA : op3_type := "011001";
constant LDSHA : op3_type := "011010";
constant LDSTUBA : op3_type := "011101";
constant SWAPA : op3_type := "011111";
constant LDF : op3_type := "100000";
constant LDFSR : op3_type := "100001";
constant LDDF : op3_type := "100011";
constant LDC : op3_type := "110000";
constant LDCSR : op3_type := "110001";
constant LDDC : op3_type := "110011";
constant ST : op3_type := "000100";
constant STB : op3_type := "000101";
constant STH : op3_type := "000110";
constant ISTD : op3_type := "000111";
constant STA : op3_type := "010100";
constant STBA : op3_type := "010101";
constant STHA : op3_type := "010110";
constant STDA : op3_type := "010111";
constant STF : op3_type := "100100";
constant STFSR : op3_type := "100101";
constant STDFQ : op3_type := "100110";
constant STDF : op3_type := "100111";
constant STC : op3_type := "110100";
constant STCSR : op3_type := "110101";
constant STDCQ : op3_type := "110110";
constant STDC : op3_type := "110111";
-- bicc decoding (inst(27 downto 25))
constant BA : std_logic_vector(3 downto 0) := "1000";
-- fpop1 decoding
subtype fpop_type is std_logic_vector(8 downto 0);
constant FITOS : fpop_type := "011000100";
constant FITOD : fpop_type := "011001000";
constant FSTOI : fpop_type := "011010001";
constant FDTOI : fpop_type := "011010010";
constant FSTOD : fpop_type := "011001001";
constant FDTOS : fpop_type := "011000110";
constant FMOVS : fpop_type := "000000001";
constant FNEGS : fpop_type := "000000101";
constant FABSS : fpop_type := "000001001";
constant FSQRTS : fpop_type := "000101001";
constant FSQRTD : fpop_type := "000101010";
constant FADDS : fpop_type := "001000001";
constant FADDD : fpop_type := "001000010";
constant FSUBS : fpop_type := "001000101";
constant FSUBD : fpop_type := "001000110";
constant FMULS : fpop_type := "001001001";
constant FMULD : fpop_type := "001001010";
constant FSMULD : fpop_type := "001101001";
constant FDIVS : fpop_type := "001001101";
constant FDIVD : fpop_type := "001001110";
-- fpop2 decoding
constant FCMPS : fpop_type := "001010001";
constant FCMPD : fpop_type := "001010010";
constant FCMPES : fpop_type := "001010101";
constant FCMPED : fpop_type := "001010110";
-- trap type decoding
subtype trap_type is std_logic_vector(5 downto 0);
constant TT_IAEX : trap_type := "000001";
constant TT_IINST : trap_type := "000010";
constant TT_PRIV : trap_type := "000011";
constant TT_FPDIS : trap_type := "000100";
constant TT_WINOF : trap_type := "000101";
constant TT_WINUF : trap_type := "000110";
constant TT_UNALA : trap_type := "000111";
constant TT_FPEXC : trap_type := "001000";
constant TT_DAEX : trap_type := "001001";
constant TT_TAG : trap_type := "001010";
constant TT_WATCH : trap_type := "001011";
constant TT_DSU : trap_type := "010000";
constant TT_PWD : trap_type := "010001";
constant TT_RFERR : trap_type := "100000";
constant TT_IAERR : trap_type := "100001";
constant TT_CPDIS : trap_type := "100100";
constant TT_CPEXC : trap_type := "101000";
constant TT_DIV : trap_type := "101010";
constant TT_DSEX : trap_type := "101011";
constant TT_TICC : trap_type := "111111";
-- Alternate address space identifiers (only 5 lsb bist are used)
subtype asi_type is std_logic_vector(4 downto 0);
constant ASI_SYSR : asi_type := "00010"; -- 0x02
constant ASI_UINST : asi_type := "01000"; -- 0x08
constant ASI_SINST : asi_type := "01001"; -- 0x09
constant ASI_UDATA : asi_type := "01010"; -- 0x0A
constant ASI_SDATA : asi_type := "01011"; -- 0x0B
constant ASI_ITAG : asi_type := "01100"; -- 0x0C
constant ASI_IDATA : asi_type := "01101"; -- 0x0D
constant ASI_DTAG : asi_type := "01110"; -- 0x0E
constant ASI_DDATA : asi_type := "01111"; -- 0x0F
constant ASI_IFLUSH : asi_type := "10000"; -- 0x10
constant ASI_DFLUSH : asi_type := "10001"; -- 0x11
constant ASI_FLUSH_PAGE : std_logic_vector(4 downto 0) := "10000"; -- 0x10 i/dcache flush page
constant ASI_FLUSH_CTX : std_logic_vector(4 downto 0) := "10011"; -- 0x13 i/dcache flush ctx
constant ASI_DCTX : std_logic_vector(4 downto 0) := "10100"; -- 0x14 dcache ctx
constant ASI_ICTX : std_logic_vector(4 downto 0) := "10101"; -- 0x15 icache ctx
constant ASI_MMUFLUSHPROBE : std_logic_vector(4 downto 0) := "11000"; -- 0x18 i/dtlb flush/(probe)
constant ASI_MMUREGS : std_logic_vector(4 downto 0) := "11001"; -- 0x19 mmu regs access
constant ASI_MMU_BP : std_logic_vector(4 downto 0) := "11100"; -- 0x1c mmu Bypass
constant ASI_MMU_DIAG : std_logic_vector(4 downto 0) := "11101"; -- 0x1d mmu diagnostic
--constant ASI_MMU_DSU : std_logic_vector(4 downto 0) := "11111"; -- 0x1f mmu diagnostic
constant ASI_MMUSNOOP_DTAG : std_logic_vector(4 downto 0) := "11110"; -- 0x1e mmusnoop physical dtag
-- ftt decoding
subtype ftt_type is std_logic_vector(2 downto 0);
constant FPIEEE_ERR : ftt_type := "001";
constant FPSEQ_ERR : ftt_type := "100";
constant FPHW_ERR : ftt_type := "101";
SUBTYPE cword IS std_logic_vector ( 32 - 1 downto 0 );
TYPE cdatatype IS ARRAY ( 0 to 3 ) OF cword;
TYPE cpartype IS ARRAY ( 0 to 3 ) OF std_logic_vector ( 3 downto 0 );
TYPE iregfile_in_type IS RECORD
raddr1 : std_logic_vector ( 9 downto 0 );
raddr2 : std_logic_vector ( 9 downto 0 );
waddr : std_logic_vector ( 9 downto 0 );
wdata : std_logic_vector ( 31 downto 0 );
ren1 : std_ulogic;
ren2 : std_ulogic;
wren : std_ulogic;
diag : std_logic_vector ( 3 downto 0 );
END RECORD;
TYPE iregfile_out_type IS RECORD
data1 : std_logic_vector ( 32 - 1 downto 0 );
data2 : std_logic_vector ( 32 - 1 downto 0 );
END RECORD;
TYPE cctrltype IS RECORD
burst : std_ulogic;
dfrz : std_ulogic;
ifrz : std_ulogic;
dsnoop : std_ulogic;
dcs : std_logic_vector ( 1 downto 0 );
ics : std_logic_vector ( 1 downto 0 );
END RECORD;
TYPE icache_in_type IS RECORD
rpc : std_logic_vector ( 31 downto 0 );
fpc : std_logic_vector ( 31 downto 0 );
dpc : std_logic_vector ( 31 downto 0 );
rbranch : std_ulogic;
fbranch : std_ulogic;
inull : std_ulogic;
su : std_ulogic;
flush : std_ulogic;
flushl : std_ulogic;
fline : std_logic_vector ( 31 downto 3 );
pnull : std_ulogic;
END RECORD;
TYPE icache_out_type IS RECORD
data : cdatatype;
set : std_logic_vector ( 1 downto 0 );
mexc : std_ulogic;
hold : std_ulogic;
flush : std_ulogic;
diagrdy : std_ulogic;
diagdata : std_logic_vector ( 32 - 1 downto 0 );
mds : std_ulogic;
cfg : std_logic_vector ( 31 downto 0 );
idle : std_ulogic;
END RECORD;
TYPE icdiag_in_type IS RECORD
addr : std_logic_vector ( 31 downto 0 );
enable : std_ulogic;
read : std_ulogic;
tag : std_ulogic;
ctx : std_ulogic;
flush : std_ulogic;
ilramen : std_ulogic;
cctrl : cctrltype;
pflush : std_ulogic;
pflushaddr : std_logic_vector ( 31 downto 11 );
pflushtyp : std_ulogic;
ilock : std_logic_vector ( 0 to 3 );
scanen : std_ulogic;
END RECORD;
TYPE dcache_in_type IS RECORD
asi : std_logic_vector ( 7 downto 0 );
maddress : std_logic_vector ( 31 downto 0 );
eaddress : std_logic_vector ( 31 downto 0 );
edata : std_logic_vector ( 31 downto 0 );
size : std_logic_vector ( 1 downto 0 );
enaddr : std_ulogic;
eenaddr : std_ulogic;
nullify : std_ulogic;
lock : std_ulogic;
read : std_ulogic;
write : std_ulogic;
flush : std_ulogic;
flushl : std_ulogic;
dsuen : std_ulogic;
msu : std_ulogic;
esu : std_ulogic;
intack : std_ulogic;
END RECORD;
TYPE dcache_out_type IS RECORD
data : cdatatype;
set : std_logic_vector ( 1 downto 0 );
mexc : std_ulogic;
hold : std_ulogic;
mds : std_ulogic;
werr : std_ulogic;
icdiag : icdiag_in_type;
cache : std_ulogic;
idle : std_ulogic;
scanen : std_ulogic;
testen : std_ulogic;
END RECORD;
TYPE tracebuf_in_type IS RECORD
addr : std_logic_vector ( 11 downto 0 );
data : std_logic_vector ( 127 downto 0 );
enable : std_logic;
write : std_logic_vector ( 3 downto 0 );
diag : std_logic_vector ( 3 downto 0 );
END RECORD;
TYPE tracebuf_out_type IS RECORD
data : std_logic_vector ( 127 downto 0 );
END RECORD;
TYPE l3_irq_in_type IS RECORD
irl : std_logic_vector ( 3 downto 0 );
rst : std_ulogic;
run : std_ulogic;
END RECORD;
TYPE l3_irq_out_type IS RECORD
intack : std_ulogic;
irl : std_logic_vector ( 3 downto 0 );
pwd : std_ulogic;
END RECORD;
TYPE l3_debug_in_type IS RECORD
dsuen : std_ulogic;
denable : std_ulogic;
dbreak : std_ulogic;
step : std_ulogic;
halt : std_ulogic;
reset : std_ulogic;
dwrite : std_ulogic;
daddr : std_logic_vector ( 23 downto 2 );
ddata : std_logic_vector ( 31 downto 0 );
btrapa : std_ulogic;
btrape : std_ulogic;
berror : std_ulogic;
bwatch : std_ulogic;
bsoft : std_ulogic;
tenable : std_ulogic;
timer : std_logic_vector ( 30 downto 0 );
END RECORD;
TYPE l3_debug_out_type IS RECORD
data : std_logic_vector ( 31 downto 0 );
crdy : std_ulogic;
dsu : std_ulogic;
dsumode : std_ulogic;
error : std_ulogic;
halt : std_ulogic;
pwd : std_ulogic;
idle : std_ulogic;
ipend : std_ulogic;
icnt : std_ulogic;
END RECORD;
TYPE l3_debug_in_vector IS ARRAY ( natural RANGE <> ) OF l3_debug_in_type;
TYPE l3_debug_out_vector IS ARRAY ( natural RANGE <> ) OF l3_debug_out_type;
TYPE div32_in_type IS RECORD
y : std_logic_vector ( 32 downto 0 );
op1 : std_logic_vector ( 32 downto 0 );
op2 : std_logic_vector ( 32 downto 0 );
flush : std_logic;
signed : std_logic;
start : std_logic;
END RECORD;
TYPE div32_out_type IS RECORD
ready : std_logic;
nready : std_logic;
icc : std_logic_vector ( 3 downto 0 );
result : std_logic_vector ( 31 downto 0 );
END RECORD;
TYPE mul32_in_type IS RECORD
op1 : std_logic_vector ( 32 downto 0 );
op2 : std_logic_vector ( 32 downto 0 );
flush : std_logic;
signed : std_logic;
start : std_logic;
mac : std_logic;
acc : std_logic_vector ( 39 downto 0 );
END RECORD;
TYPE mul32_out_type IS RECORD
ready : std_logic;
nready : std_logic;
icc : std_logic_vector ( 3 downto 0 );
result : std_logic_vector ( 63 downto 0 );
END RECORD;
TYPE fp_rf_in_type IS RECORD
rd1addr : std_logic_vector ( 3 downto 0 );
rd2addr : std_logic_vector ( 3 downto 0 );
wraddr : std_logic_vector ( 3 downto 0 );
wrdata : std_logic_vector ( 31 downto 0 );
ren1 : std_ulogic;
ren2 : std_ulogic;
wren : std_ulogic;
END RECORD;
TYPE fp_rf_out_type IS RECORD
data1 : std_logic_vector ( 31 downto 0 );
data2 : std_logic_vector ( 31 downto 0 );
END RECORD;
TYPE fpc_pipeline_control_type IS RECORD
pc : std_logic_vector ( 31 downto 0 );
inst : std_logic_vector ( 31 downto 0 );
cnt : std_logic_vector ( 1 downto 0 );
trap : std_ulogic;
annul : std_ulogic;
pv : std_ulogic;
END RECORD;
TYPE fpc_debug_in_type IS RECORD
enable : std_ulogic;
write : std_ulogic;
fsr : std_ulogic;
addr : std_logic_vector ( 4 downto 0 );
data : std_logic_vector ( 31 downto 0 );
END RECORD;
TYPE fpc_debug_out_type IS RECORD
data : std_logic_vector ( 31 downto 0 );
END RECORD;
TYPE fpc_in_type IS RECORD
flush : std_ulogic;
exack : std_ulogic;
a_rs1 : std_logic_vector ( 4 downto 0 );
d : fpc_pipeline_control_type;
a : fpc_pipeline_control_type;
e : fpc_pipeline_control_type;
m : fpc_pipeline_control_type;
x : fpc_pipeline_control_type;
lddata : std_logic_vector ( 31 downto 0 );
dbg : fpc_debug_in_type;
END RECORD;
TYPE fpc_out_type IS RECORD
data : std_logic_vector ( 31 downto 0 );
exc : std_logic;
cc : std_logic_vector ( 1 downto 0 );
ccv : std_ulogic;
ldlock : std_logic;
holdn : std_ulogic;
dbg : fpc_debug_out_type;
END RECORD;
TYPE grfpu_in_type IS RECORD
start : std_logic;
nonstd : std_logic;
flop : std_logic_vector ( 8 downto 0 );
op1 : std_logic_vector ( 63 downto 0 );
op2 : std_logic_vector ( 63 downto 0 );
opid : std_logic_vector ( 7 downto 0 );
flush : std_logic;
flushid : std_logic_vector ( 5 downto 0 );
rndmode : std_logic_vector ( 1 downto 0 );
req : std_logic;
END RECORD;
TYPE grfpu_out_type IS RECORD
res : std_logic_vector ( 63 downto 0 );
exc : std_logic_vector ( 5 downto 0 );
allow : std_logic_vector ( 2 downto 0 );
rdy : std_logic;
cc : std_logic_vector ( 1 downto 0 );
idout : std_logic_vector ( 7 downto 0 );
END RECORD;
TYPE grfpu_out_vector_type IS ARRAY ( integer RANGE 0 to 7 ) OF grfpu_out_type;
TYPE grfpu_in_vector_type IS ARRAY ( integer RANGE 0 to 7 ) OF grfpu_in_type;
end package iu3PreLoad; | mit | 2b2863feb52202f30c3d55ff446baa5a | 0.569658 | 2.990035 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/leon3/mmu_dcache.vhd | 2 | 60,138 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: dcache
-- File: dcache.vhd
-- Author: Jiri Gaisler, Konrad Eisele - Gaisler Research
-- Description: This unit implements the data cache controller.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
library grlib;
use grlib.amba.all;
use grlib.sparc.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.libiu.all;
use gaisler.libcache.all;
use gaisler.mmuconfig.all;
use gaisler.mmuiface.all;
entity mmu_dcache is
generic (
dsu : integer range 0 to 1 := 0;
drepl : integer range 0 to 2 := 0;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
memtech : integer range 0 to NTECH := 0;
cached : integer := 0);
port (
rst : in std_logic;
clk : in std_logic;
dci : in dcache_in_type;
dco : out dcache_out_type;
ico : in icache_out_type;
mcdi : out memory_dc_in_type;
mcdo : in memory_dc_out_type;
ahbsi : in ahb_slv_in_type;
dcrami : out dcram_in_type;
dcramo : in dcram_out_type;
fpuholdn : in std_logic;
mmudci : out mmudc_in_type;
mmudco : in mmudc_out_type;
sclk : in std_ulogic
);
end;
architecture rtl of mmu_dcache is
constant DSNOOP2 : integer := conv_integer(conv_std_logic_vector(dsnoop,3) and conv_std_logic_vector(3,3));
constant DSNOOP4 : integer := conv_integer(conv_std_logic_vector(dsnoop,3) and conv_std_logic_vector(4,3));
constant M_TLB_TYPE : integer range 0 to 1 := conv_integer(conv_std_logic_vector(tlb_type,2) and conv_std_logic_vector(1,2)); -- eather split or combined
constant M_TLB_FASTWRITE : integer range 0 to 3 := conv_integer(conv_std_logic_vector(tlb_type,2) and conv_std_logic_vector(2,2)); -- fast writebuffer
constant M_ENT_I : integer range 2 to 64 := itlbnum; -- icache tlb entries: number
constant M_ENT_ILOG : integer := log2(M_ENT_I); -- icache tlb entries: address bits
constant M_ENT_D : integer range 2 to 64 := dtlbnum; -- dcache tlb entries: number
constant M_ENT_DLOG : integer := log2(M_ENT_D); -- dcache tlb entries: address bits
constant M_ENT_C : integer range 2 to 64 := M_ENT_I; -- i/dcache tlb entries: number
constant M_ENT_CLOG : integer := M_ENT_ILOG; -- i/dcache tlb entries: address bits
constant DLINE_BITS : integer := log2(dlinesize);
constant DOFFSET_BITS : integer := 8 +log2(dsetsize) - DLINE_BITS;
constant LRR_BIT : integer := TAG_HIGH + 1;
constant TAG_LOW : integer := DOFFSET_BITS + DLINE_BITS + 2;
constant OFFSET_HIGH: integer := TAG_LOW - 1;
constant OFFSET_LOW : integer := DLINE_BITS + 2;
constant LINE_HIGH : integer := OFFSET_LOW - 1;
constant LINE_LOW : integer := 2;
constant LINE_ZERO : std_logic_vector(DLINE_BITS-1 downto 0) := (others => '0');
constant SETBITS : integer := log2x(DSETS);
constant DLRUBITS : integer := lru_table(DSETS);
constant lram : integer range 0 to 1 := 0;
constant lramsize : integer range 1 to 64 := 1;
constant lramstart : integer range 0 to 255 := 16#00#;
constant LOCAL_RAM_START : std_logic_vector(7 downto 0) := conv_std_logic_vector(lramstart, 8);
constant DREAD_FAST : boolean := false;
constant DWRITE_FAST : boolean := false;
constant DCLOCK_BIT : integer := dsetlock;
constant M_EN : boolean := true;
constant DCREPLACE : integer range 0 to 2 := drepl;
constant DLINE_SIZE : integer := dlinesize;
constant DEST_RW : boolean := (syncram_dp_dest_rw_collision(memtech) = 1);
type rdatatype is (dtag, ddata, dddata, dctx, icache, memory, sysr , misc, mmusnoop_dtag); -- sources during cache read
type vmasktype is (clearone, clearall, merge, tnew); -- valid bits operation
type valid_type is array (0 to DSETS-1) of std_logic_vector(dlinesize - 1 downto 0);
type write_buffer_type is record -- write buffer
addr, data1, data2 : std_logic_vector(31 downto 0);
size : std_logic_vector(1 downto 0);
asi : std_logic_vector(3 downto 0);
read : std_logic;
lock : std_logic;
end record;
type dstatetype is (idle, wread, rtrans, wwrite, wtrans, wflush,
asi_idtag,dblwrite, loadpend);
type dcache_control_type is record -- all registers
read : std_logic; -- access direction
size : std_logic_vector(1 downto 0); -- access size
req, burst, holdn, nomds, stpend : std_logic;
xaddress : std_logic_vector(31 downto 0); -- common address buffer
paddress : std_logic_vector(31 downto 0); -- physical address buffer
faddr : std_logic_vector(DOFFSET_BITS - 1 downto 0); -- flush address
valid : valid_type; --std_logic_vector(DLINE_SIZE - 1 downto 0); -- registered valid bits
dstate : dstatetype; -- FSM
hit : std_logic;
flush : std_logic; -- flush in progress
flush2 : std_logic; -- flush in progress
mexc : std_logic; -- latched mexc
wb : write_buffer_type; -- write buffer
asi : std_logic_vector(4 downto 0);
icenable : std_logic; -- icache diag access
rndcnt : std_logic_vector(log2x(DSETS)-1 downto 0); -- replace counter
setrepl : std_logic_vector(log2x(DSETS)-1 downto 0); -- set to replace
lrr : std_logic;
dsuset : std_logic_vector(log2x(DSETS)-1 downto 0);
lock : std_logic;
lramrd : std_ulogic;
cctrl : cctrltype;
cctrlwr : std_ulogic;
mmctrl1 : mmctrl_type1;
mmctrl1wr : std_ulogic;
pflush : std_logic;
pflushr : std_logic;
pflushaddr : std_logic_vector(VA_I_U downto VA_I_D);
pflushtyp : std_logic;
vaddr : std_logic_vector(31 downto 0);
ready : std_logic;
wbinit : std_logic;
cache : std_logic;
su : std_logic;
dblwdata : std_logic;
trans_op : std_logic;
flush_op : std_logic;
diag_op : std_logic;
end record;
type snoop_reg_type is record -- snoop control registers
snoop : std_logic; -- snoop access to tags
writebp : std_logic_vector(0 to DSETS-1); -- snoop write bypass
addr : std_logic_vector(TAG_HIGH downto OFFSET_LOW);-- snoop tag
readbpx : std_logic_vector(0 to DSETS-1); -- possible write/read contention
end record;
type snoop_hit_bits_type is array (0 to 2**DOFFSET_BITS-1) of std_logic_vector(0 to DSETS-1);
type snoop_hit_reg_type is record
hit : snoop_hit_bits_type; -- snoop hit bits
taddr : std_logic_vector(OFFSET_HIGH downto OFFSET_LOW); -- saved tag address
set : std_logic_vector(log2x(DSETS)-1 downto 0); -- saved set
end record;
subtype lru_type is std_logic_vector(DLRUBITS-1 downto 0);
type lru_array is array (0 to 2**DOFFSET_BITS-1) of lru_type; -- lru registers
type par_type is array (0 to DSETS-1) of std_logic_vector(1 downto 0);
type lru_reg_type is record
write : std_logic;
waddr : std_logic_vector(DOFFSET_BITS-1 downto 0);
set : std_logic_vector(SETBITS-1 downto 0); --integer range 0 to DSETS-1;
lru : lru_array;
end record;
subtype lock_type is std_logic_vector(0 to DSETS-1);
function lru_set (lru : lru_type; lock : lock_type) return std_logic_vector is
variable xlru : std_logic_vector(4 downto 0);
variable set : std_logic_vector(SETBITS-1 downto 0);
variable xset : std_logic_vector(1 downto 0);
variable unlocked : integer range 0 to DSETS-1;
begin
set := (others => '0'); xlru := (others => '0'); xset := (others => '0');
xlru(DLRUBITS-1 downto 0) := lru;
if dsetlock = 1 then
unlocked := DSETS-1;
for i in DSETS-1 downto 0 loop
if lock(i) = '0' then unlocked := i; end if;
end loop;
end if;
case DSETS is
when 2 =>
if dsetlock = 1 then
if lock(0) = '1' then xset(0) := '1'; else xset(0) := xlru(0); end if;
else xset(0) := xlru(0); end if;
when 3 =>
if dsetlock = 1 then
xset := conv_std_logic_vector(lru3_repl_table(conv_integer(xlru)) (unlocked), 2);
else
xset := conv_std_logic_vector(lru3_repl_table(conv_integer(xlru)) (0), 2);
end if;
when 4 =>
if dsetlock = 1 then
xset := conv_std_logic_vector(lru4_repl_table(conv_integer(xlru)) (unlocked), 2);
else
xset := conv_std_logic_vector(lru4_repl_table(conv_integer(xlru)) (0), 2);
end if;
when others =>
end case;
set := xset(SETBITS-1 downto 0);
return(set);
end;
function lru_calc (lru : lru_type; set : integer) return lru_type is
variable new_lru : lru_type;
variable xnew_lru: std_logic_vector(4 downto 0);
variable xlru : std_logic_vector(4 downto 0);
begin
new_lru := (others => '0'); xnew_lru := (others => '0');
xlru := (others => '0'); xlru(DLRUBITS-1 downto 0) := lru;
case DSETS is
when 2 =>
if set = 0 then xnew_lru(0) := '1'; else xnew_lru(0) := '0'; end if;
when 3 =>
xnew_lru(2 downto 0) := lru_3set_table(conv_integer(lru))(set);
when 4 =>
xnew_lru(4 downto 0) := lru_4set_table(conv_integer(lru))(set);
when others =>
end case;
new_lru := xnew_lru(DLRUBITS-1 downto 0);
return(new_lru);
end;
subtype word is std_logic_vector(31 downto 0);
signal r, c : dcache_control_type; -- r is registers, c is combinational
signal rs, cs : snoop_reg_type; -- rs is registers, cs is combinational
signal rh, ch : snoop_hit_reg_type; -- rs is registers, cs is combinational
signal rl, cl : lru_reg_type; -- rl is registers, cl is combinational
constant ctbl : std_logic_vector(15 downto 0) := conv_std_logic_vector(cached, 16);
begin
dctrl : process(rst, r, rs, rh, rl, dci, mcdo, ico, dcramo, ahbsi, fpuholdn, mmudco)
variable dcramov : dcram_out_type;
variable rdatasel : rdatatype;
variable maddress : std_logic_vector(31 downto 0);
variable maddrlow : std_logic_vector(1 downto 0);
variable edata : std_logic_vector(31 downto 0);
variable size : std_logic_vector(1 downto 0);
variable read : std_logic;
variable twrite, tpwrite, tdiagwrite, ddiagwrite, dwrite : std_logic;
variable taddr : std_logic_vector(OFFSET_HIGH downto LINE_LOW); -- tag address
variable newtag : std_logic_vector(TAG_HIGH downto TAG_LOW); -- new tag
variable newptag : std_logic_vector(TAG_HIGH downto TAG_LOW); -- new tag
variable align_data : std_logic_vector(31 downto 0); -- aligned data
variable ddatainv, rdatav, align_datav : cdatatype;
variable rdata : std_logic_vector(31 downto 0);
variable vmaskraw : std_logic_vector((dlinesize -1) downto 0);
variable vmask : valid_type; --std_logic_vector((dlinesize -1) downto 0);
variable ivalid : std_logic_vector((dlinesize -1) downto 0);
variable vmaskdbl : std_logic_vector((dlinesize/2 -1) downto 0);
variable enable, senable, scanen : std_logic_vector(0 to 3);
variable mds : std_logic;
variable mexc : std_logic;
variable hit, valid, validraw, forcemiss : std_logic;
variable flush : std_logic;
variable iflush : std_logic;
variable v : dcache_control_type;
variable eholdn : std_logic; -- external hold
variable tparerr, dparerr : std_logic_vector(0 to DSETS-1);
variable snoopwe : std_logic;
variable hcache : std_logic;
variable snoopaddr: std_logic_vector(OFFSET_HIGH downto OFFSET_LOW);
variable vs : snoop_reg_type;
variable vh : snoop_hit_reg_type;
variable dsudata : std_logic_vector(31 downto 0);
variable set : integer range 0 to DSETS-1;
variable ddset : integer range 0 to MAXSETS-1;
variable snoopset : integer range 0 to DSETS-1;
variable validv, hitv, validrawv : std_logic_vector(0 to MAXSETS-1);
variable csnoopwe : std_logic_vector(0 to MAXSETS-1);
variable ctwrite, ctpwrite, cdwrite : std_logic_vector(0 to MAXSETS-1);
variable vset, setrepl : std_logic_vector(log2x(DSETS)-1 downto 0);
variable wlrr : std_logic_vector(0 to MAXSETS-1);
variable vl : lru_reg_type;
variable diagset : std_logic_vector(TAG_LOW + SETBITS -1 downto TAG_LOW);
variable lock : std_logic_vector(0 to DSETS-1);
variable wlock : std_logic_vector(0 to MAXSETS-1);
variable snoopset2, rdsuset : integer range 0 to DSETS-1;
variable snoophit : std_logic_vector(0 to DSETS-1);
variable snoopval : std_logic;
variable tag : cdatatype; --std_logic_vector(31 downto 0);
variable ptag : cdatatype; --std_logic_vector(31 downto 0);
variable ctx : ctxdatatype;
variable miscdata : std_logic_vector(31 downto 0);
variable mmudiagaddr : std_logic_vector(2 downto 0);
variable pflush : std_logic;
variable pflushaddr : std_logic_vector(VA_I_U downto VA_I_D);
variable pflushtyp : std_logic;
variable pftag : std_logic_vector(31 downto 2);
variable mmuwdata : std_logic_vector(31 downto 0);
variable mmudci_fsread, tagclear : std_logic;
variable mmudci_trans_op : std_logic;
variable mmudci_flush_op : std_logic;
variable mmudci_wb_op : std_logic;
variable mmudci_diag_op : std_logic;
variable mmudci_su : std_logic;
variable mmudci_read : std_logic;
variable mmuregw, su : std_logic;
variable mmuisdis : std_logic;
variable readbp : std_logic_vector(0 to DSETS-1);
variable rbphit, sidle : std_logic;
variable mmudci_transdata_data : std_logic_vector(31 downto 0);
variable paddress : std_logic_vector(31 downto 0); -- physical address buffer
begin
-- init local variables
v := r; vs := rs; vh := rh; dcramov := dcramo; vl := rl;
vl.write := '0'; v.cctrlwr := '0'; v.mmctrl1wr := '0';
v.flush2 := r.flush; sidle := '0';
if ((dci.eenaddr or dci.enaddr) = '1') or (r.dstate /= idle) or
((dsu = 1) and (dci.dsuen = '1')) or (r.flush = '1') or
(is_fpga(memtech) = 1)
then
enable := (others => '1');
else enable := (others => '0'); end if;
tagclear := '0'; mmuisdis := '0';
if (not M_EN) or ((r.asi(4 downto 0) = ASI_MMU_BP) or (r.mmctrl1.e = '0')) then
mmuisdis := '1';
end if;
if (mmuisdis = '1') then paddress := r.xaddress;
else paddress := r.paddress; end if;
mds := '1'; dwrite := '0'; twrite := '0'; tpwrite := '0';
ddiagwrite := '0'; tdiagwrite := '0'; v.holdn := '1'; mexc := '0';
flush := '0'; v.icenable := '0'; iflush := '0';
eholdn := ico.hold and fpuholdn; ddset := 0; vset := (others => '0');
tparerr := (others => '0'); dparerr := (others => '0');
vs.snoop := '0'; vs.writebp := (others => '0'); snoopwe := '0';
snoopaddr := ahbsi.haddr(OFFSET_HIGH downto OFFSET_LOW);
hcache := '0'; rdsuset := 0;
validv := (others => '0'); validrawv := (others => '0');
hitv := (others => '0'); ivalid := (others => '0');
miscdata := (others => '0'); pflush := '0';
pflushaddr := dci.maddress(VA_I_U downto VA_I_D); pflushtyp := PFLUSH_PAGE;
pftag := (others => '0');
mmudiagaddr := (others => '0'); mmuregw := '0'; mmuwdata := (others => '0');
mmudci_fsread := '0';
ddatainv := (others => (others => '0')); tag := (others => (others => '0')); ptag := (others => (others => '0'));
ctx := (others => (others => '0')); vs.readbpx := (others => '0'); rbphit := '0';
newptag(TAG_HIGH downto TAG_LOW) := (others => '0');
v.trans_op := r.trans_op and (not mmudco.grant);
v.flush_op := r.flush_op and (not mmudco.grant);
v.diag_op := r.diag_op and (not mmudco.grant);
mmudci_trans_op := r.trans_op;
mmudci_flush_op := r.flush_op;
mmudci_diag_op := r.diag_op;
mmudci_wb_op := '0';
mmudci_transdata_data := r.vaddr;
mmudci_su := '0'; mmudci_read := '0'; su := '0';
if (not M_EN) or (r.mmctrl1.e = '0') then v.cache := '1'; end if;
rdatasel := ddata; -- read data from cache as default
senable := (others => '0'); scanen := (others => mcdo.scanen);
set := 0; snoopset := 0; csnoopwe := (others => '0');
ctwrite := (others => '0'); ctpwrite := (others => '0'); cdwrite := (others => '0');
wlock := (others => '0');
for i in 0 to DSETS-1 loop wlock(i) := dcramov.tag(i)(CTAG_LOCKPOS); end loop;
wlrr := (others => '0');
for i in 0 to 3 loop wlrr(i) := dcramov.tag(i)(CTAG_LRRPOS); end loop;
if (DSETS > 1) then setrepl := r.setrepl; else setrepl := (others => '0'); end if;
-- random replacement counter
if DSETS > 1 then
if conv_integer(r.rndcnt) = (DSETS - 1) then v.rndcnt := (others => '0');
else v.rndcnt := r.rndcnt + 1; end if;
end if;
-- generate lock bits
lock := (others => '0');
if DCLOCK_BIT = 1 then
for i in 0 to DSETS-1 loop lock(i) := dcramov.tag(i)(CTAG_LOCKPOS); end loop;
end if;
-- AHB snoop handling
if DSNOOP2 /= 0 then
-- snoop on NONSEQ or SEQ and first word in cache line
-- do not snoop during own transfers or during cache flush
if (ahbsi.hready and ahbsi.hwrite and not mcdo.bg) = '1' and
((ahbsi.htrans = HTRANS_NONSEQ) or
((ahbsi.htrans = HTRANS_SEQ) and
(ahbsi.haddr(LINE_HIGH downto LINE_LOW) = LINE_ZERO)))
then
vs.snoop := r.cctrl.dsnoop;-- and not r.mmctrl1.e;
vs.addr := ahbsi.haddr(TAG_HIGH downto OFFSET_LOW);
end if;
for i in 0 to DSETS-1 loop senable(i) := vs.snoop or rs.snoop; end loop;
readbp := (others => '0');
if (paddress(TAG_HIGH downto OFFSET_LOW) = rs.addr(TAG_HIGH downto OFFSET_LOW)) then rbphit := '1'; end if;
for i in 0 to DSETS-1 loop
if (rs.readbpx(i) and rbphit) = '1' then readbp(i) := '1'; end if;
end loop;
-- clear valid bits on snoop hit (or set hit bits)
for i in DSETS-1 downto 0 loop
if ((rs.snoop and (not mcdo.ba) and not r.flush) = '1')
and ((dcramov.stag(i)(TAG_HIGH downto TAG_LOW) = rs.addr(TAG_HIGH downto TAG_LOW)) or (readbp(i) = '1'))
then
if DSNOOP2 = 2 then
vh.hit(conv_integer(rs.addr(OFFSET_HIGH downto OFFSET_LOW)))(i) := '1';
else
snoopaddr := rs.addr(OFFSET_HIGH downto OFFSET_LOW);
snoopwe := '1'; snoopset := i;
end if;
end if;
-- bypass tag data on read/write contention
if (DSNOOP2 /= 2) and (rs.writebp(i) = '1') then
dcramov.tag(i)(TAG_HIGH downto TAG_LOW) := rs.addr(TAG_HIGH downto TAG_LOW);
dcramov.tag(i)(dlinesize-1 downto 0) := zero32(dlinesize-1 downto 0);
end if;
end loop;
end if;
-- generate access parameters during pipeline stall
if ((r.holdn) = '0') or ((dsu = 1) and (dci.dsuen = '1')) then
taddr := r.xaddress(OFFSET_HIGH downto LINE_LOW);
elsif ((dci.enaddr and not dci.read) = '1') or (eholdn = '0')
then
taddr := dci.maddress(OFFSET_HIGH downto LINE_LOW);
else
taddr := dci.eaddress(OFFSET_HIGH downto LINE_LOW);
end if;
if (dci.write or not r.holdn) = '1' then
maddress := r.xaddress(31 downto 0); --signed := r.signed;
read := r.read; size := r.size; edata := dci.maddress;
mmudci_su := r.su; mmudci_read := r.read;
else
maddress := dci.maddress(31 downto 0); --signed := dci.signed;
read := dci.read; size := dci.size; edata := dci.edata;
mmudci_su := dci.msu; mmudci_read := dci.read;
end if;
newtag := dci.maddress(TAG_HIGH downto TAG_LOW);
newptag := dci.maddress(TAG_HIGH downto TAG_LOW);
vl.waddr := maddress(OFFSET_HIGH downto OFFSET_LOW); -- lru write address
-- generate cache hit and valid bits
if cached /= 0 then hcache := ctbl(conv_integer(dci.maddress(31 downto 28)));
else hcache := '1'; end if;
forcemiss := not dci.asi(3); hit := '0'; set := 0;
snoophit := (others => '0'); snoopval := '1';
for i in DSETS-1 downto 0 loop
if DSNOOP2 = 2 then
snoophit(i) := rh.hit(conv_integer(rh.taddr))(i);
end if;
if (dcramov.tag(i)(TAG_HIGH downto TAG_LOW) = dci.maddress(TAG_HIGH downto TAG_LOW))
and ((dcramov.ctx(i) = r.mmctrl1.ctx) or (r.mmctrl1.e = '0'))
then hitv(i) := hcache; end if;
validrawv(i) := hitv(i) and (not r.flush) and (not r.flush2) and (not snoophit(i)) and
genmux(dci.maddress(LINE_HIGH downto LINE_LOW), dcramov.tag(i)(dlinesize-1 downto 0));
validv(i) := validrawv(i);
snoopval := snoopval and not snoophit(i);
end loop;
hit := orv(hitv) and not r.flush and (not r.flush2);
-- cache hit disabled if mmu-enabled but off or BYPASS
if (M_EN) and (dci.asi(4 downto 0) = ASI_MMU_BP) then -- or (r.mmctrl1.e = '0')
hit := '0';
end if;
validraw := orv(validrawv);
valid := orv(validv);
if DSETS > 1 then
for i in DSETS-1 downto 0 loop
if hitv(i) = '1' then
vset := vset or conv_std_logic_vector(i, SETBITS);
end if;
end loop;
set := conv_integer(vset);
else set := 0; end if;
if (dci.dsuen = '1') then diagset := r.xaddress(TAG_LOW+SETBITS-1 downto TAG_LOW);
else diagset := maddress(TAG_LOW + SETBITS - 1 downto TAG_LOW); end if;
case DSETS is
when 1 => ddset := 0;
when 3 => if conv_integer(diagset) < 3 then ddset := conv_integer(diagset); end if;
when others => ddset := conv_integer(diagset);
end case;
if ((r.holdn and dci.enaddr) = '1') and (r.dstate = idle) then
v.hit := hit; v.xaddress := dci.maddress;
v.read := dci.read; v.size := dci.size;
v.asi := dci.asi(4 downto 0);
--v.signed := dci.signed;
v.su := dci.msu;
end if;
-- Store buffer
if mcdo.ready = '1' then
v.wb.addr(2) := r.wb.addr(2) or (r.wb.size(0) and r.wb.size(1));
if r.stpend = '1' then
v.stpend := r.req; v.wb.data1 := r.wb.data2;
v.wb.lock := r.wb.lock and r.req;
end if;
end if;
if mcdo.grant = '1' then v.req := r.burst; v.burst := '0'; end if;
if (mcdo.grant and not r.wb.read and r.req) = '1' then v.wb.lock := '0'; end if;
-- cache freeze operation
if (r.cctrl.ifrz and dci.intack and r.cctrl.ics(0)) = '1' then
v.cctrl.ics := "01";
end if;
if (r.cctrl.dfrz and dci.intack and r.cctrl.dcs(0)) = '1' then
v.cctrl.dcs := "01";
end if;
if r.cctrlwr = '1' then
if (r.xaddress(7 downto 2) = "000000") and (dci.read = '0') then
v.cctrl.dsnoop := dci.maddress(23);
flush := dci.maddress(22);
iflush := dci.maddress(21);
v.cctrl.burst:= dci.maddress(16);
v.cctrl.dfrz := dci.maddress(5);
v.cctrl.ifrz := dci.maddress(4);
v.cctrl.dcs := dci.maddress(3 downto 2);
v.cctrl.ics := dci.maddress(1 downto 0);
end if;
end if;
if (dsu = 1) and (dci.dsuen = '1') then
mmuwdata := dci.maddress;
else
mmuwdata := dci.edata;
end if;
mmudiagaddr := dci.maddress(CNR_U downto CNR_D);
if r.mmctrl1wr = '1' then
mmudiagaddr := r.xaddress(CNR_U downto CNR_D); -- defer match sram out
if (dci.read = '0') then
mmuwdata := dci.maddress;
mmuregw := '1';
end if;
end if;
-- main Dcache state machine
case r.dstate is
when idle => -- Idle state
if (M_TLB_FASTWRITE /= 0) then
mmudci_transdata_data := dci.maddress;
end if;
sidle := '1';
if (snoopval = '1') then
for i in 0 to DSETS-1 loop
v.valid(i) := dcramov.tag(i)(dlinesize-1 downto 0);
end loop;
else v.valid := (others => (others => '0')); end if;
v.nomds := r.nomds and not eholdn; --v.valid := dcramov.dtramout(set).valid;
if (r.stpend = '0') or ((mcdo.ready and not r.req)= '1') then -- wait for store queue
v.wb.addr := dci.maddress; v.wb.size := dci.size;
v.wb.read := dci.read; v.wb.data1 := dci.edata; v.wb.lock := dci.lock;
v.wb.asi := dci.asi(3 downto 0);
if ((M_EN) and (dci.asi(4 downto 0) /= ASI_MMU_BP) and (r.mmctrl1.e = '1') and (M_TLB_FASTWRITE /= 0) ) then
v.wb.addr := mmudco.wbtransdata.data;
newptag := mmudco.wbtransdata.data(TAG_HIGH downto TAG_LOW);
end if;
end if;
if (eholdn and (not r.nomds)) = '1' then -- avoid false path through nullify
case dci.asi(4 downto 0) is
when ASI_SYSR => rdatasel := sysr;
when ASI_DTAG => rdatasel := dtag;
when ASI_DDATA => rdatasel := dddata;
when ASI_DCTX => rdatasel := dctx;
when ASI_MMUREGS => rdatasel := misc;
when ASI_MMUSNOOP_DTAG => rdatasel := mmusnoop_dtag;
when others =>
end case;
end if;
if (dci.enaddr and eholdn and (not r.nomds) and not dci.nullify) = '1' then
case dci.asi(4 downto 0) is
when ASI_SYSR => -- system registers
if (dsu = 0) or (dci.dsuen = '0') then
if (dci.maddress(7 downto 2) = "000000") and (dci.read = '0') then
v.cctrl.dsnoop := dci.edata(23);
flush := dci.edata(22);
iflush := dci.edata(21);
v.cctrl.burst:= dci.edata(16);
v.cctrl.dfrz := dci.edata(5);
v.cctrl.ifrz := dci.edata(4);
v.cctrl.dcs := dci.edata(3 downto 2);
v.cctrl.ics := dci.edata(1 downto 0);
end if;
else
v.cctrlwr := not dci.read;
end if;
when ASI_MMUREGS =>
if (dsu = 0) or dci.dsuen = '0' then
if M_EN then
-- rdatasel := misc;
-- clean fault valid bit
if dci.read = '1' then
case dci.maddress(CNR_U downto CNR_D) is
when CNR_F =>
mmudci_fsread := '1';
when others => null;
end case;
else
mmuregw := '1';
end if;
end if;
else
v.mmctrl1wr := not dci.read and not (r.mmctrl1wr and dci.dsuen);
end if;
when ASI_ITAG | ASI_IDATA | ASI_ICTX => -- Read/write Icache tags
-- CTX write has to be done through ctxnr & ASI_ITAG
if (ico.flush = '1') or (dci.asi(4) = '1') then mexc := '1';
else v.dstate := asi_idtag; v.holdn := '0'; end if;
when ASI_DFLUSH => -- flush data cache
if dci.read = '0' then flush := '1'; end if;
when ASI_DDATA => -- Read/write Dcache data
if (dci.size /= "10") or (r.flush = '1') then -- only word access is allowed
mexc := '1';
elsif (dci.read = '0') then
dwrite := '1'; ddiagwrite := '1';
end if;
when ASI_DTAG => -- Read/write Dcache tags
if (dci.size /= "10") or (r.flush = '1') then -- allow only word access
mexc := '1';
elsif (dci.read = '0') then
twrite := '1'; tdiagwrite := '1';
end if;
when ASI_MMUSNOOP_DTAG => -- Read/write MMU physical snoop tags
if M_EN then
snoopaddr := taddr(OFFSET_HIGH downto OFFSET_LOW);
if (dci.size /= "10") or (r.flush = '1') then -- allow only word access
mexc := '1';
elsif (dci.read = '0') then
tpwrite := '1'; tdiagwrite := '1';
end if;
end if;
when ASI_DCTX =>
-- write has to be done through ctxnr & ASI_DTAG
if (dci.size /= "10") or (r.flush = '1') or (dci.read = '0') then -- allow only word access
mexc := '1';
end if;
when ASI_FLUSH_PAGE => -- i/dcache flush page
if M_EN then
if dci.read = '0' then
flush := '1'; iflush := '1'; --pflush := '1'; pflushtyp := PFLUSH_PAGE;
end if;
end if;
when ASI_FLUSH_CTX => -- i/dcache flush ctx
if M_EN then
if dci.read = '0' then
flush := '1'; iflush := '1'; --pflush := '1'; pflushtyp := PFLUSH_CTX;
end if;
end if;
when ASI_MMUFLUSHPROBE =>
if M_EN then
if dci.read = '0' then -- flush
mmudci_flush_op := '1';
v.flush_op := not mmudco.grant;
v.dstate := wflush;
v.vaddr := dci.maddress; v.holdn := '0'; flush := '1'; iflush := '1';
end if;
end if;
when ASI_MMU_DIAG =>
if dci.read = '0' then -- diag access
mmudci_diag_op := '1';
v.diag_op := not mmudco.grant;
v.vaddr := dci.maddress;
end if;
when others =>
if dci.read = '1' then -- read access
--if (not ((mcdo.dcs(0) = '1')
if (not ((r.cctrl.dcs(0) = '1')
and ((hit and valid and not forcemiss) = '1')))
then -- read miss
v.holdn := '0'; v.dstate := wread; v.ready := '0'; v.cache := '1';
if (not M_EN) or
((dci.asi(4 downto 0) = ASI_MMU_BP) or (r.mmctrl1.e = '0'))
then
-- cache disabled if mmu-enabled but off or BYPASS
if (M_EN) then v.cache := '0'; end if;
if ((r.stpend = '0') or ((mcdo.ready and not r.req) = '1'))
then -- wait for store queue
v.req := '1';
v.burst := dci.size(1) and dci.size(0) and not dci.maddress(2);
end if;
else
-- ## mmu case >
if (r.stpend = '0') or ((mcdo.ready and not r.req)= '1')
then
v.wbinit := '1'; -- wb init in idle
v.burst := dci.size(1) and dci.size(0) and not dci.maddress(2);
else
v.wbinit := '0';
end if;
mmudci_trans_op := '1'; -- start translation
v.trans_op := not mmudco.grant;
v.vaddr := dci.maddress;
v.dstate := rtrans;
-- ## < mmu case
end if;
else -- read hit
if (DSETS > 1) and (DCREPLACE = lru) then vl.write := '1'; end if;
end if;
else -- write access
v.ready := '0';
if (not M_EN) or
((dci.asi(4 downto 0) = ASI_MMU_BP) or (r.mmctrl1.e = '0')) then
if (r.stpend = '0') or ((mcdo.ready and not r.req)= '1') then
v.req := '1'; v.stpend := '1';
v.burst := dci.size(1) and dci.size(0);
if (dci.size = "11") then v.dstate := dblwrite; end if; -- double store
else -- wait for store queue
v.dstate := wwrite; v.holdn := '0';
end if;
else
-- ## mmu case > false and
--if ((r.stpend = '0') or ((mcdo.ready and not r.req)= '1')) and ( mmudco.wbtransdata.accexc = '0' ) and (dci.size /= "11") and (M_TLB_FASTWRITE /= 0)
if ((r.stpend = '0') or ((mcdo.ready and not r.req)= '1')) and ( mmudco.wbtransdata.accexc = '0' ) and (M_TLB_FASTWRITE /= 0)
then
v.req := '1'; v.stpend := '1';
v.burst := dci.size(1) and dci.size(0);
if (dci.size = "11") then v.dstate := dblwrite; end if; -- double store
else
if (r.stpend = '0') or ((mcdo.ready and not r.req)= '1')
then
v.wbinit := '1'; -- wb init in idle
v.burst := dci.size(1) and dci.size(0);
else
v.wbinit := '0';
end if;
mmudci_trans_op := '1'; -- start translation
v.trans_op := not mmudco.grant;
v.vaddr := dci.maddress; v.holdn := '0';
v.dstate := wtrans;
v.dblwdata := dci.size(0) or dci.size(1); -- "11"
-- ## < mmu case
end if;
end if;
-- note: cache hit disabled if BYPASS
if (r.cctrl.dcs(0) = '1') and ((hit and (dci.size(1) or validraw)) = '1')
then -- write hit
twrite := '1'; dwrite := '1';
if (DSETS > 1) and (DCREPLACE = lru) then vl.write := '1'; end if;
setrepl := conv_std_logic_vector(set, SETBITS);
if DSNOOP2 /= 0 then
if ((dci.enaddr and not dci.read) = '1') or (eholdn = '0')
then v.xaddress := dci.maddress; else v.xaddress := dci.eaddress; end if;
vs.readbpx(set) := '1';
end if;
end if;
if (dci.size = "11") then v.xaddress(2) := '1'; end if;
end if;
if (DSETS > 1) then
vl.set := conv_std_logic_vector(set, SETBITS);
v.setrepl := conv_std_logic_vector(set, SETBITS);
if ((not hit) and (not dparerr(set)) and (not r.flush)) = '1' then
case DCREPLACE is
when rnd =>
if DCLOCK_BIT = 1 then
if lock(conv_integer(r.rndcnt)) = '0' then v.setrepl := r.rndcnt;
else
v.setrepl := conv_std_logic_vector(DSETS-1, SETBITS);
for i in DSETS-1 downto 0 loop
if (lock(i) = '0') and (i>conv_integer(r.rndcnt)) then
v.setrepl := conv_std_logic_vector(i, SETBITS);
end if;
end loop;
end if;
else
v.setrepl := r.rndcnt;
end if;
when lru =>
v.setrepl := lru_set(rl.lru(conv_integer(dci.maddress(OFFSET_HIGH downto OFFSET_LOW))), lock(0 to DSETS-1));
when lrr =>
v.setrepl := (others => '0');
if DCLOCK_BIT = 1 then
if lock(0) = '1' then v.setrepl(0) := '1';
else
v.setrepl(0) := dcramov.tag(0)(CTAG_LRRPOS) xor dcramov.tag(1)(CTAG_LRRPOS);
end if;
else
v.setrepl(0) := dcramov.tag(0)(CTAG_LRRPOS) xor dcramov.tag(1)(CTAG_LRRPOS);
end if;
if v.setrepl(0) = '0' then
v.lrr := not dcramov.tag(0)(CTAG_LRRPOS);
else
v.lrr := dcramov.tag(0)(CTAG_LRRPOS);
end if;
end case;
end if;
if (DCLOCK_BIT = 1) then
if (hit and (not dparerr(set)) and lock(set)) = '1' then v.lock := '1';
else v.lock := '0'; end if;
end if;
end if;
end case;
end if;
when rtrans =>
if M_EN then
if r.stpend = '1' then
if ((mcdo.ready and not r.req) = '1') then
v.ready := '1'; -- buffer store finish
end if;
end if;
v.holdn := '0';
if mmudco.transdata.finish = '1' then
-- translation error, i.e. page fault
if (mmudco.transdata.accexc) = '1' then
v.holdn := '1'; v.dstate := idle;
mds := '0'; mexc := not r.mmctrl1.nf;
else
v.dstate := wread;
v.cache := r.cache and mmudco.transdata.cache;
--v.xaddress := mmudco.data;
v.paddress := mmudco.transdata.data;
if v.wbinit = '1' then
v.wb.addr := mmudco.transdata.data;
v.req := '1';
end if;
end if;
end if;
end if;
when wread => -- read miss, wait for memory data
taddr := r.xaddress(OFFSET_HIGH downto LINE_LOW);
newtag := r.xaddress(TAG_HIGH downto TAG_LOW);
newptag := paddress(TAG_HIGH downto TAG_LOW);
v.nomds := r.nomds and not eholdn;
v.holdn := v.nomds; rdatasel := memory;
for i in 0 to DSETS-1 loop wlock(i) := r.lock; end loop;
for i in 0 to 1 loop wlrr(i) := r.lrr; end loop;
if (r.stpend = '0') and (r.ready = '0') then
if mcdo.ready = '1' then
mds := r.holdn or r.nomds; v.xaddress(2) := '1'; v.holdn := '1';
if (r.cctrl.dcs = "01") then
v.hit := mcdo.cache and r.hit and r.cache; twrite := v.hit;
elsif (r.cctrl.dcs(1) = '1') then
v.hit := mcdo.cache and (r.hit or (r.asi(3) and not r.asi(2))) and r.cache; twrite := v.hit;
end if;
dwrite := twrite; rdatasel := memory;
mexc := mcdo.mexc;
tpwrite := twrite;
if r.req = '0' then
if (((dci.enaddr and not mds) = '1') or
((dci.eenaddr and mds and eholdn) = '1')) and (r.cctrl.dcs(0) = '1') then
v.dstate := loadpend; v.holdn := '0';
else v.dstate := idle; end if;
else v.nomds := '1'; end if;
end if;
v.mexc := mcdo.mexc; v.wb.data2 := mcdo.data;
else
if (r.ready or (mcdo.ready and not r.req)) = '1' then -- wait for store queue
v.burst := r.size(1) and r.size(0) and not r.xaddress(2);
v.wb.addr := paddress;
v.wb.size := r.size;
v.wb.read := r.read; v.wb.data1 := dci.maddress; v.req := '1';
v.wb.lock := dci.lock; v.wb.asi := r.asi(3 downto 0); v.ready := '0';
end if;
end if;
if DSNOOP2 /= 0 then vs.readbpx(conv_integer(setrepl)) := '1'; end if;
when loadpend => -- return from read miss with load pending
taddr := dci.maddress(OFFSET_HIGH downto LINE_LOW);
v.dstate := idle;
when dblwrite => -- second part of double store cycle
v.dstate := idle; v.wb.data2 := dci.edata;
edata := dci.edata; -- needed for STD store hit
taddr := r.xaddress(OFFSET_HIGH downto LINE_LOW);
if (r.cctrl.dcs(0) = '1') and (r.hit = '1') then dwrite := '1'; end if;
when asi_idtag => -- icache diag access
rdatasel := icache; v.icenable := '1'; v.holdn := dci.dsuen;
if ico.diagrdy = '1' then
v.dstate := loadpend; v.icenable := '0'; mds := not r.read;
end if;
when wtrans =>
edata := dci.edata; -- needed for STD store hit
taddr := r.xaddress(OFFSET_HIGH downto LINE_LOW);
newtag := r.xaddress(TAG_HIGH downto TAG_LOW);
if M_EN then
if r.stpend = '1' then
if ((mcdo.ready and not r.req) = '1') then
v.ready := '1'; -- buffer store finish
end if;
end if;
-- fetch dblwrite data 2, does the same as state dblwrite,
-- except that init of data2 is omitted to end of translation or in wwrite
if ((r.dblwdata) = '1') and ((r.size) = "11") then
v.dblwdata := '0';
end if;
v.holdn := '0';
if mmudco.transdata.finish = '1' then
if (mmudco.transdata.accexc) = '1' then
v.holdn := '1'; v.dstate := idle;
mds := '0'; mexc := not r.mmctrl1.nf;
tagclear := r.cctrl.dcs(0) and r.hit;
twrite := tagclear;
if (twrite = '1') and (((dci.enaddr and not mds) = '1') or
((dci.eenaddr and mds and eholdn) = '1')) and (r.cctrl.dcs(0) = '1') then
v.dstate := loadpend; v.holdn := '0';
end if;
else
v.dstate := wwrite;
v.cache := mmudco.transdata.cache;
v.paddress := mmudco.transdata.data;
if (r.wbinit) = '1' then
v.wb.data2 := dci.edata;
v.wb.addr := mmudco.transdata.data;
v.dstate := idle; v.holdn := '1';
v.req := '1'; v.stpend := '1';
v.burst := r.size(1) and r.size(0) and not v.wb.addr(2);
--if (mcdo.dcs(0) = '1') and (r.hit = '1') and (r.size = "11") then -- write hit
if (r.cctrl.dcs(0) = '1') and (r.hit = '1') and (r.size = "11") then -- write hit
dwrite := '1';
end if;
end if;
end if;
else
-- mmudci_trans_op := '1'; -- start translation
end if;
end if;
when wwrite => -- wait for store buffer to empty (store access)
edata := dci.edata; -- needed for STD store hit
if (v.ready or (mcdo.ready and not r.req)) = '1' then -- store queue emptied
if (r.cctrl.dcs(0) = '1') and (r.hit = '1') and (r.size = "11") then -- write hit
taddr := r.xaddress(OFFSET_HIGH downto LINE_LOW); dwrite := '1';
end if;
v.dstate := idle;
v.req := '1'; v.burst := r.size(1) and r.size(0); v.stpend := '1';
v.wb.addr := paddress;
v.wb.size := r.size;
v.wb.read := r.read; v.wb.data1 := dci.maddress;
v.wb.lock := dci.lock; v.wb.data2 := dci.edata;
v.wb.asi := r.asi(3 downto 0);
if r.size = "11" then v.wb.addr(2) := '0'; end if;
else -- hold cpu until buffer empty
v.holdn := '0';
end if;
when wflush =>
v.holdn := '0';
if mmudco.transdata.finish = '1' then
v.dstate := idle; v.holdn := '1';
end if;
when others => v.dstate := idle;
end case;
-- select data to return on read access
-- align if byte/half word read from cache or memory.
--mmudiagaddr := dci.maddress(CNR_U downto CNR_D); mmuwdata := dci.edata;
if (dsu = 1) and (dci.dsuen = '1') then
v.dsuset := conv_std_logic_vector(ddset, SETBITS);
case dci.asi(4 downto 0) is
when ASI_ITAG | ASI_IDATA =>
v.icenable := not ico.diagrdy;
rdatasel := icache;
when ASI_DTAG =>
tdiagwrite := not dci.eenaddr and dci.enaddr and dci.write;
twrite := not dci.eenaddr and dci.enaddr and dci.write;
rdatasel := dtag;
when ASI_MMUSNOOP_DTAG =>
if M_EN then
tdiagwrite := not dci.eenaddr and dci.enaddr and dci.write;
tpwrite := not dci.eenaddr and dci.enaddr and dci.write;
rdatasel := mmusnoop_dtag;
end if;
when ASI_DDATA =>
ddiagwrite := not dci.eenaddr and dci.enaddr and dci.write;
dwrite := not dci.eenaddr and dci.enaddr and dci.write;
rdatasel := dddata;
when ASI_MMUREGS =>
mmuregw := not dci.eenaddr and dci.enaddr and dci.write;
rdatasel := misc;
when others =>
end case;
end if;
-- note: mmudiagaddr is (10 downto 8) (000,001, ...)
-- read
case mmudiagaddr is
when CNR_CTRL =>
miscdata(MMCTRL_E) := r.mmctrl1.e;
miscdata(MMCTRL_NF) := r.mmctrl1.nf;
miscdata(MMCTRL_PSO) := r.mmctrl1.pso;
miscdata(MMCTRL_VER_U downto MMCTRL_VER_D) := "0000";
miscdata(MMCTRL_IMPL_U downto MMCTRL_IMPL_D) := "0000";
miscdata(23 downto 21) := conv_std_logic_vector(M_ENT_ILOG,3);
miscdata(20 downto 18) := conv_std_logic_vector(M_ENT_DLOG,3);
if M_TLB_TYPE = 0 then miscdata(17) := '1'; else
miscdata(23 downto 21) := conv_std_logic_vector(M_ENT_CLOG,3);
miscdata(20 downto 18) := (others => '0');
end if;
miscdata(MMCTRL_TLBDIS) := r.mmctrl1.tlbdis;
--custom
when CNR_CTXP =>
miscdata(MMCTXP_U downto MMCTXP_D) := r.mmctrl1.ctxp;
when CNR_CTX =>
miscdata(MMCTXNR_U downto MMCTXNR_D) := r.mmctrl1.ctx;
when CNR_F =>
miscdata(FS_OW) := mmudco.mmctrl2.fs.ow;
miscdata(FS_FAV) := mmudco.mmctrl2.fs.fav;
miscdata(FS_FT_U downto FS_FT_D) := mmudco.mmctrl2.fs.ft;
miscdata(FS_AT_LS) := mmudco.mmctrl2.fs.at_ls;
miscdata(FS_AT_ID) := mmudco.mmctrl2.fs.at_id;
miscdata(FS_AT_SU) := mmudco.mmctrl2.fs.at_su;
miscdata(FS_L_U downto FS_L_D) := mmudco.mmctrl2.fs.l;
miscdata(FS_EBE_U downto FS_EBE_D) := mmudco.mmctrl2.fs.ebe;
when CNR_FADDR =>
miscdata(VA_I_U downto VA_I_D) := mmudco.mmctrl2.fa;
when others => null;
end case;
rdata := (others => '0'); rdatav := (others => (others => '0'));
align_data := (others => '0'); align_datav := (others => (others => '0'));
maddrlow := maddress(1 downto 0); -- stupid Synopsys VSS bug ...
case rdatasel is
when misc =>
set := 0;
rdatav(0) := miscdata;
when dddata =>
rdatav := dcramov.data;
if dci.dsuen = '1' then set := conv_integer(r.dsuset);
else set := ddset; end if;
when dtag =>
rdatav := dcramov.tag;
if dci.dsuen = '1' then set := conv_integer(r.dsuset);
else set := ddset; end if;
when mmusnoop_dtag =>
rdatav := dcramov.stag;
if dci.dsuen = '1' then set := conv_integer(r.dsuset);
else set := ddset; end if;
when dctx =>
--rdata(M_CTX_SZ-1 downto 0) := dcramov.dtramout(ddset).ctx;
when icache =>
rdatav(0) := ico.diagdata; set := 0;
when ddata | memory =>
if rdatasel = memory then
rdatav(0) := mcdo.data; set := 0; --FIXME
else
for i in 0 to DSETS-1 loop rdatav(i) := dcramov.data(i); end loop;
end if;
when sysr =>
set := 0;
case dci.maddress(3 downto 2) is
when "00" | "01" =>
rdatav(0)(23) := r.cctrl.dsnoop;
rdatav(0)(16 downto 14) := r.cctrl.burst & ico.flush & r.flush;
rdatav(0)(5 downto 0) :=
r.cctrl.dfrz & r.cctrl.ifrz & r.cctrl.dcs & r.cctrl.ics;
when "10" =>
rdatav(0) := ico.cfg;
when others =>
rdatav(0) := cache_cfg(drepl, dsets, dlinesize, dsetsize, dsetlock,
dsnoop, lram, lramsize, lramstart, 1);
end case;
end case;
-- select which data to update the data cache with
for i in 0 to DSETS-1 loop
case size is -- merge data during partial write
when "00" =>
case maddrlow is
when "00" =>
ddatainv(i) := edata(7 downto 0) & dcramov.data(i)(23 downto 0);
when "01" =>
ddatainv(i) := dcramov.data(i)(31 downto 24) & edata(7 downto 0) &
dcramov.data(i)(15 downto 0);
when "10" =>
ddatainv(i) := dcramov.data(i)(31 downto 16) & edata(7 downto 0) &
dcramov.data(i)(7 downto 0);
when others =>
ddatainv(i) := dcramov.data(i)(31 downto 8) & edata(7 downto 0);
end case;
when "01" =>
if maddress(1) = '0' then
ddatainv(i) := edata(15 downto 0) & dcramov.data(i)(15 downto 0);
else
ddatainv(i) := dcramov.data(i)(31 downto 16) & edata(15 downto 0);
end if;
when others =>
ddatainv(i) := edata;
end case;
end loop;
-- handle double load with pipeline hold
if (r.dstate = idle) and (r.nomds = '1') then
rdatav(0) := r.wb.data2; mexc := r.mexc; set := 0; --FIXME
end if;
-- Handle AHB retry. Re-generate bus request and burst
if mcdo.retry = '1' then
v.req := '1';
v.burst := r.wb.size(0) and r.wb.size(1) and not r.wb.addr(2);
end if;
-- Generate new valid bits
vmaskdbl := decode(maddress(LINE_HIGH downto LINE_LOW+1));
if (size = "11") and (read = '0') then
for i in 0 to (DLINE_SIZE - 1) loop vmaskraw(i) := vmaskdbl(i/2); end loop;
else
vmaskraw := decode(maddress(LINE_HIGH downto LINE_LOW));
end if;
vmask := (others => vmaskraw);
if r.hit = '1' then
for i in 0 to DSETS-1 loop vmask(i) := r.valid(i) or vmaskraw; end loop;
end if;
if r.dstate = idle then
for i in 0 to DSETS-1 loop
vmask(i) := dcramov.tag(i)(dlinesize-1 downto 0) or vmaskraw;
end loop;
end if;
if (mcdo.mexc or r.flush) = '1' then twrite := '0'; dwrite := '0'; end if;
if twrite = '1' then
if tagclear = '1' then vmask := (others => (others => '0')); end if;
v.valid := vmask;
if (DSETS>1) and (DCREPLACE = lru) and (tdiagwrite = '0') then
vl.write := '1'; vl.set := setrepl;
end if;
end if;
if (DSETS>1) and (DCREPLACE = lru) and (rl.write = '1') then
vl.lru(conv_integer(rl.waddr)) :=
lru_calc(rl.lru(conv_integer(rl.waddr)), conv_integer(rl.set));
end if;
if tdiagwrite = '1' then -- diagnostic tag write
if (dsu = 1) and (dci.dsuen = '1') then
vmask := (others => dci.maddress(dlinesize - 1 downto 0));
else
vmask := (others => dci.edata(dlinesize - 1 downto 0));
newtag(TAG_HIGH downto TAG_LOW) := dci.edata(TAG_HIGH downto TAG_LOW);
newptag(TAG_HIGH downto TAG_LOW) := dci.edata(TAG_HIGH downto TAG_LOW);
for i in 0 to 3 loop wlrr(i) := dci.edata(CTAG_LRRPOS); end loop;
for i in 0 to DSETS-1 loop wlock(i) := dci.edata(CTAG_LOCKPOS); end loop;
end if;
end if;
-- mmureg write
if mmuregw = '1' then
case mmudiagaddr is
when CNR_CTRL =>
v.mmctrl1.e := mmuwdata(MMCTRL_E);
v.mmctrl1.nf := mmuwdata(MMCTRL_NF);
v.mmctrl1.pso := mmuwdata(MMCTRL_PSO);
v.mmctrl1.tlbdis := mmuwdata(MMCTRL_TLBDIS);
--custom
-- Note: before tlb disable tlb flush is required !!!
when CNR_CTXP =>
v.mmctrl1.ctxp := mmuwdata(MMCTXP_U downto MMCTXP_D);
when CNR_CTX =>
v.mmctrl1.ctx := mmuwdata(MMCTXNR_U downto MMCTXNR_D);
when CNR_F => null;
when CNR_FADDR => null;
when others => null;
end case;
end if;
-- cache flush
--if (dci.flush or flush or mcdo.dflush) = '1' then
if (dci.flush or flush ) = '1' then
v.flush := '1'; v.faddr := (others => '0'); v.pflush := pflush;
v.pflushr := '1';
v.pflushaddr := pflushaddr;
v.pflushtyp := pflushtyp;
end if;
if r.flush = '1' then
twrite := '1'; vmask := (others=>(others => '0')); v.faddr := r.faddr +1;
newtag(TAG_HIGH downto TAG_LOW) := (others => '0');
newptag(TAG_HIGH downto TAG_LOW) := (others => '0');
taddr(OFFSET_HIGH downto OFFSET_LOW) := r.faddr;
wlrr := (others => '0'); v.lrr := '0';
if (r.faddr(DOFFSET_BITS -1) and not v.faddr(DOFFSET_BITS -1)) = '1' then
v.flush := '0';
end if;
if DSNOOP2 = 2 then
vh.hit(conv_integer(taddr(OFFSET_HIGH downto OFFSET_LOW))) := (others => '0');
end if;
end if;
-- AHB snoop handling (2), bypass write data on read/write contention
if DSNOOP2 /= 0 then
if tdiagwrite = '1' then snoopset2 := ddset;
else snoopset2 := conv_integer(setrepl); end if;
if DSNOOP2 = 2 then
vh.taddr := taddr(OFFSET_HIGH downto OFFSET_LOW);
vh.set := conv_std_logic_vector(set, SETBITS);
if (twrite = '1') and (r.dstate /= idle) then
vh.hit(conv_integer(taddr(OFFSET_HIGH downto OFFSET_LOW)))(snoopset2) := '0';
end if;
else
if rs.addr(OFFSET_HIGH downto OFFSET_LOW) =
taddr(OFFSET_HIGH downto OFFSET_LOW)
then
if twrite = '0' then
if snoopwe = '1' then
vs.writebp(snoopset) := '1';
if DEST_RW then enable(snoopset) := '0'; end if;
end if;
else
if (snoopwe = '1') and (conv_integer(setrepl) = snoopset) then -- avoid write/write contention
twrite := '0';
if DEST_RW then enable(snoopset) := '0'; end if;
end if;
end if;
end if;
end if;
if (r.dstate = wread) and ((rbphit and rs.snoop) = '1') then v.hit := '0'; end if;
if DEST_RW then
-- disable snoop read enable on write/read contention
if taddr(OFFSET_HIGH downto OFFSET_LOW) = ahbsi.haddr(OFFSET_HIGH downto OFFSET_LOW) then
for i in 0 to DSETS-1 loop
if (twrite and senable(i)) = '1' then senable(i) := '0'; end if;
end loop;
end if;
end if;
end if;
-- update cache with memory data during read miss
if read = '1' then
for i in 0 to DSETS-1 loop ddatainv(i) := mcdo.data; end loop;
end if;
-- cache write signals
if twrite = '1' then
if tdiagwrite = '1' then ctwrite(ddset) := '1';
else ctwrite(conv_integer(setrepl)) := '1'; end if;
end if;
if M_EN then
if tpwrite = '1' then
if tdiagwrite = '1' then ctpwrite(ddset) := '1';
else ctpwrite(conv_integer(setrepl)) := '1'; end if;
end if;
end if;
if dwrite = '1' then
if ddiagwrite = '1' then cdwrite(ddset) := '1';
else cdwrite(conv_integer(setrepl)) := '1'; end if;
end if;
csnoopwe := (others => '0');
if ((snoopwe and not mcdo.scanen) = '1') then csnoopwe(snoopset) := '1'; end if;
if (r.flush and twrite) = '1' then -- flush
ctwrite := (others => '1'); wlrr := (others => '0'); wlock := (others => '0');
if M_EN then
ctpwrite := (others => '1');
end if;
-- precise flush, ASI_FLUSH_PAGE & ASI_FLUSH_CTX
if false then --
if M_EN then
if r.pflush = '1' then
twrite := '0'; ctwrite := (others => '0');
for i in DSETS-1 downto 0 loop
wlrr(i) := dcramov.tag(i)(CTAG_LRRPOS);
wlock(i) := dcramov.tag(i)(CTAG_LOCKPOS);
end loop;
if r.pflushr = '0' then
for i in DSETS-1 downto 0 loop
pftag(OFFSET_HIGH downto OFFSET_LOW) := r.faddr;
pftag(TAG_HIGH downto TAG_LOW) := dcramov.tag(i)(TAG_HIGH downto TAG_LOW);
if ((pftag(VA_I_U downto VA_I_D) = r.pflushaddr(VA_I_U downto VA_I_D)) or
(r.pflushtyp = '1')) then
ctwrite(i) := '1';
wlrr(i) := '0';
wlock(i) := '0';
end if;
end loop;
else
v.faddr := r.faddr;
end if;
v.pflushr := not r.pflushr;
end if;
end if;
end if;
end if;
if r.flush2 = '1' then
vl.lru := (others => (others => '0'));
end if;
-- reset
if rst = '0' then
v.dstate := idle; v.stpend := '0'; v.req := '0'; v.burst := '0';
v.read := '0'; v.flush := '0'; v.nomds := '0'; v.holdn := '1';
v.rndcnt := (others => '0'); v.setrepl := (others => '0');
v.dsuset := (others => '0');
v.lrr := '0'; v.lock := '0'; v.flush2 := '1';
v.cctrl.dcs := "00"; v.cctrl.ics := "00";
v.cctrl.burst := '0'; v.cctrl.dsnoop := '0';
v.mmctrl1.e := '0'; v.mmctrl1.nf := '0'; v.mmctrl1.ctx := (others => '0');
v.mmctrl1.tlbdis := '0';
v.mmctrl1.pso := '0';
v.trans_op := '0';
v.flush_op := '0';
v.diag_op := '0';
v.pflush := '0';
v.pflushr := '0';
v.mmctrl1.bar := (others => '0');
end if;
if dsnoop = 0 then v.cctrl.dsnoop := '0'; end if;
-- Drive signals
c <= v; cs <= vs; ch <= vh; -- register inputs
cl <= vl;
-- tag ram inputs
senable := senable and not scanen; enable := enable and not scanen;
if mcdo.scanen = '1' then ctpwrite := (others => '0'); end if;
for i in 0 to DSETS-1 loop
tag(i)(dlinesize-1 downto 0) := vmask(i);
tag(i)(TAG_HIGH downto TAG_LOW) := newtag(TAG_HIGH downto TAG_LOW);
tag(i)(CTAG_LRRPOS) := wlrr(i);
tag(i)(CTAG_LOCKPOS) := wlock(i);
ctx(i) := r.mmctrl1.ctx;
ptag(i)(TAG_HIGH downto TAG_LOW) := newptag(TAG_HIGH downto TAG_LOW);
end loop;
dcrami.tag <= tag;
dcrami.ptag <= ptag;
dcrami.ctx <= ctx;
dcrami.tenable <= enable;
dcrami.twrite <= ctwrite;
dcrami.tpwrite <= ctpwrite;
dcrami.flush <= r.flush;
dcrami.senable <= senable; --vs.snoop or rs.snoop;
dcrami.swrite <= csnoopwe;
dcrami.saddress(19 downto (OFFSET_HIGH - OFFSET_LOW +1)) <=
zero32(19 downto (OFFSET_HIGH - OFFSET_LOW +1));
dcrami.saddress(OFFSET_HIGH - OFFSET_LOW downto 0) <= snoopaddr;
dcrami.stag(31 downto (TAG_HIGH - TAG_LOW +1)) <=
zero32(31 downto (TAG_HIGH - TAG_LOW +1));
dcrami.stag(TAG_HIGH - TAG_LOW downto 0) <= rs.addr(TAG_HIGH downto TAG_LOW);
dcrami.tdiag <= mcdo.testen & "000";
dcrami.ddiag <= mcdo.testen & "000";
-- data ram inputs
dcrami.denable <= enable;
dcrami.address(19 downto (OFFSET_HIGH - LINE_LOW + 1)) <= zero32(19 downto (OFFSET_HIGH - LINE_LOW + 1));
dcrami.address(OFFSET_HIGH - LINE_LOW downto 0) <= taddr;
dcrami.data <= ddatainv;
dcrami.dwrite <= cdwrite;
-- memory controller inputs
mcdi.address <= r.wb.addr;
mcdi.data <= r.wb.data1;
mcdi.burst <= r.burst;
mcdi.size <= r.wb.size;
mcdi.read <= r.wb.read;
mcdi.asi <= r.wb.asi;
mcdi.lock <= r.wb.lock;
mcdi.req <= r.req;
mcdi.cache <= orv(r.cctrl.dcs);
--mcdi.flush <= r.flush;
-- diagnostic instruction cache access
dco.icdiag.flush <= iflush;-- or mcdo.iflush;
dco.icdiag.pflush <= pflush;
dco.icdiag.pflushaddr <= pflushaddr;
dco.icdiag.pflushtyp <= pflushtyp;
dco.icdiag.read <= read;
dco.icdiag.tag <= (not r.asi(0));-- and (not r.asi(4));
dco.icdiag.ctx <= r.asi(4); --ASI_ICTX "10101"
dco.icdiag.addr <= r.xaddress;
dco.icdiag.enable <= r.icenable;
dco.icdiag.cctrl <= r.cctrl;
dco.icdiag.scanen <= mcdo.scanen;
-- IU data cache inputs
dco.data <= rdatav;
dco.mexc <= mexc;
dco.set <= conv_std_logic_vector(set, 2);
dco.hold <= r.holdn;
dco.mds <= mds;
dco.werr <= mcdo.werr;
dco.idle <= sidle and not r.stpend;
dco.scanen <= mcdo.scanen;
dco.testen <= mcdo.testen;
-- MMU
mmudci.trans_op <= mmudci_trans_op;
mmudci.transdata.data <= mmudci_transdata_data; --r.vaddr;
mmudci.transdata.su <= mmudci_su;
mmudci.transdata.read <= mmudci_read;
mmudci.transdata.isid <= id_dcache;
mmudci.transdata.wb_data <= dci.maddress;
mmudci.flush_op <= mmudci_flush_op;
mmudci.wb_op <= mmudci_wb_op;
mmudci.diag_op <= mmudci_diag_op;
mmudci.fsread <= mmudci_fsread;
mmudci.mmctrl1 <= r.mmctrl1;
end process;
-- Local registers
reg1 : process(clk)
begin if rising_edge(clk ) then r <= c; end if; end process;
sn2 : if DSNOOP2 /= 0 generate
reg2 : process(sclk)
begin if rising_edge(sclk ) then rs <= cs; end if; end process;
end generate;
nosn2 : if DSNOOP2 = 0 generate
rs.snoop <= '0'; rs.writebp <= (others => '0');
rs.addr <= (others => '0'); rs.readbpx <= (others => '0');
end generate;
sn3 : if DSNOOP2 = 2 generate
reg3 : process(sclk)
begin if rising_edge(sclk ) then rh <= ch; end if; end process;
end generate;
sn3no : if DSNOOP2 /= 2 generate
rh.hit <= (others => (others => '0'));
rh.taddr <= (others => '0');
rh.set <= (others => '0');
end generate;
reg2 : if (DSETS>1) and (DCREPLACE = lru) generate
reg2 : process(clk)
begin if rising_edge(clk ) then rl <= cl; end if; end process;
end generate;
noreg2 : if (DSETS = 1) or (drepl /= lru) generate
rl.write <= '0'; rl.waddr <= (others => '0');
rl.set <= (others => '0'); rl.lru <= (others => (others => '0'));
end generate;
-- pragma translate_off
chk : process
begin
assert not ((DSETS > 2) and (DCREPLACE = lrr)) report
"Wrong data cache configuration detected: LRR replacement requires 2 sets"
severity failure;
wait;
end process;
-- pragma translate_on
end ;
| mit | 7a9a6de5796df0ccf625198aad820ed3 | 0.55203 | 3.340258 | false | false | false | false |
cafe-alpha/wascafe | v13/wasca_10m08sc_20191205_abus_divide/wasca/synthesis/submodules/abus_slave.vhd | 2 | 37,036 | -- abus_slave.vhd
library IEEE;
use IEEE.numeric_std.all;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity abus_slave is
port (
clock : in std_logic := '0'; -- clock.clk
-- Demuxed signals
-- Note : naming is Saturn-centered, ie readdata = read from Saturn = output from A-Bus side = input from demux side
demux_writeaddress : in std_logic_vector(27 downto 0) := (others => '0');
demux_writedata : in std_logic_vector(15 downto 0) := (others => '0');
demux_writepulse : in std_logic := '0';
demux_write_byteenable : in std_logic_vector( 1 downto 0) := (others => '0');
demux_readaddress : in std_logic_vector(27 downto 0) := (others => '0');
demux_readdata : out std_logic_vector(15 downto 0) := (others => '0');
demux_readpulse : in std_logic := '0';
demux_readdatavalid : out std_logic := '0';
avalon_read : out std_logic; -- avalon_master.read
avalon_write : out std_logic; -- .write
avalon_waitrequest : in std_logic := '0'; -- .waitrequest
avalon_address : out std_logic_vector(27 downto 0); -- .address
avalon_readdata : in std_logic_vector(15 downto 0) := (others => '0'); -- .readdata
avalon_writedata : out std_logic_vector(15 downto 0); -- .writedata
avalon_byteenable : out std_logic_vector( 1 downto 0); -- .byteenable
avalon_burstcount : out std_logic; -- .burstcount
avalon_readdatavalid : in std_logic := '0'; -- .readdatavalid
avalon_nios_read : in std_logic := '0'; -- avalon_master.read
avalon_nios_write : in std_logic := '0'; -- .write
avalon_nios_waitrequest : out std_logic := '0'; -- .waitrequest
avalon_nios_address : in std_logic_vector( 7 downto 0) := (others => '0'); -- .address
avalon_nios_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
avalon_nios_burstcount : in std_logic; -- .burstcount
avalon_nios_readdata : out std_logic_vector(31 downto 0) := (others => '0'); -- .readdata
avalon_nios_readdatavalid : out std_logic := '0'; -- .readdatavalid
reset : in std_logic := '0' -- reset.reset
);
end entity abus_slave;
architecture rtl of abus_slave is
-- Avalon/register selection
TYPE transaction_type IS (TYPE_REG, TYPE_AVALON);
SIGNAL my_transaction_type : transaction_type := TYPE_REG;
TYPE wasca_mode_type IS (MODE_INIT,
MODE_POWER_MEMORY_05M, MODE_POWER_MEMORY_1M, MODE_POWER_MEMORY_2M, MODE_POWER_MEMORY_4M,
MODE_RAM_1M, MODE_RAM_4M,
MODE_ROM_KOF95,
MODE_ROM_ULTRAMAN,
MODE_BOOT);
SIGNAL wasca_mode : wasca_mode_type := MODE_INIT;
signal avalon_readdatavalid_p1 : std_logic := '0';
signal demux_readdatavalid_p1 : std_logic := '0';
signal demux_readdata_p1 : std_logic_vector(15 downto 0) := (others => '0');
signal REG_PCNTR : std_logic_vector(15 downto 0) := (others => '0');
signal REG_STATUS : std_logic_vector(15 downto 0) := (others => '0');
signal REG_MODE : std_logic_vector(15 downto 0) := (others => '0');
signal REG_HWVER : std_logic_vector(15 downto 0) := X"0002";
signal REG_SWVER : std_logic_vector(15 downto 0) := (others => '0');
-- For Rd/Wr access debug
signal rd_access_cntr : std_logic_vector( 7 downto 0) := x"01";
signal wr_access_cntr : std_logic_vector( 7 downto 0) := x"01";
signal last_rd_addr : std_logic_vector(27 downto 0) := x"ABCDEF1"; -- Last avalon read addr
signal last_rd_addr1 : std_logic_vector(27 downto 0) := x"A1A1A11"; -- Demux read addr full 28 bits, last access
signal last_rd_addr2 : std_logic_vector(27 downto 0) := x"A2A2A22"; -- Demux read addr full 28 bits, last access - 1
signal last_rd_addr3 : std_logic_vector(27 downto 0) := x"A3A3A33"; -- Demux read addr full 28 bits, last access - 2
signal last_rd_addr4 : std_logic_vector(27 downto 0) := x"A4A4A44"; -- Demux read addr full 28 bits, last access - 3
signal last_wr_addr : std_logic_vector(27 downto 0) := x"0001231";
signal last_wr_data : std_logic_vector(15 downto 0) := x"5678";
-- Access test stuff, added 2019/11/04 vvv
signal rdwr_access_buff : std_logic_vector(127 downto 0) := x"CAFE0304050607080910111213141516";
-- Access test stuff, added 2019/11/04 ^^^
begin
---------------------------------------------------------------------------------------
-- T.B.D.
process (clock)
begin
if rising_edge(clock) then
avalon_readdatavalid_p1 <= avalon_readdatavalid;
demux_readdata_p1 <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8);
end if;
end process;
process (clock)
begin
if rising_edge(clock) then
if demux_readdatavalid_p1 = '1' then
-- Indicate that data was valid on previous clock.
demux_readdatavalid <= '0';
demux_readdatavalid_p1 <= '0';
elsif((my_transaction_type = TYPE_AVALON) and (avalon_waitrequest = '0')) then
-- Terminate request to Avalon.
my_transaction_type <= TYPE_REG;
avalon_read <= '0';
avalon_write <= '0';
elsif((avalon_readdatavalid_p1 = '1') and (avalon_readdatavalid = '0')) then
-- Pass data read back from Avalon to A-Bus demultiplexer.
demux_readdata <= demux_readdata_p1;
demux_readdatavalid <= '1';
demux_readdatavalid_p1 <= '1';
elsif demux_readpulse = '1' then
-- Debug stuff around Rd/Wr access
--rd_access_cntr <= rd_access_cntr + x"01";
last_rd_addr1 <= demux_readaddress;
last_rd_addr2 <= last_rd_addr1;
last_rd_addr3 <= last_rd_addr2;
last_rd_addr4 <= last_rd_addr3;
if demux_readaddress(25 downto 24) = "00" then
--CS0 access
if demux_readaddress(23 downto 0) = X"FF0FFE" then
--wasca specific SD card control register
demux_readdata <= X"CDCD";
demux_readdatavalid <= '1';
demux_readdatavalid_p1 <= '1';
my_transaction_type <= TYPE_REG;
-- Access test stuff, added 2019/11/04 vvv
elsif demux_readaddress(23 downto 0) = X"FFFFD0" then -- 0x23FFFFA0
demux_readdata <= x"A" & last_rd_addr(27 downto 16);
demux_readdatavalid <= '1';
demux_readdatavalid_p1 <= '1';
my_transaction_type <= TYPE_REG;
elsif demux_readaddress(23 downto 0) = X"FFFFD1" then -- 0x23FFFFA2
demux_readdata <= last_rd_addr(15 downto 0);
demux_readdatavalid <= '1';
demux_readdatavalid_p1 <= '1';
my_transaction_type <= TYPE_REG;
elsif demux_readaddress(23 downto 0) = X"FFFFD8" then -- 0x23FFFFB0
demux_readdata <= x"0" & last_rd_addr1(27 downto 16);
demux_readdatavalid <= '1';
demux_readdatavalid_p1 <= '1';
my_transaction_type <= TYPE_REG;
elsif demux_readaddress(23 downto 0) = X"FFFFD9" then -- 0x23FFFFB2
demux_readdata <= last_rd_addr1(15 downto 0);
demux_readdatavalid <= '1';
demux_readdatavalid_p1 <= '1';
my_transaction_type <= TYPE_REG;
elsif demux_readaddress(23 downto 0) = X"FFFFDA" then -- 0x23FFFFB4
demux_readdata <= x"0" & last_rd_addr2(27 downto 16);
demux_readdatavalid <= '1';
demux_readdatavalid_p1 <= '1';
my_transaction_type <= TYPE_REG;
elsif demux_readaddress(23 downto 0) = X"FFFFDB" then -- 0x23FFFFB6
demux_readdata <= last_rd_addr2(15 downto 0);
demux_readdatavalid <= '1';
demux_readdatavalid_p1 <= '1';
my_transaction_type <= TYPE_REG;
elsif demux_readaddress(23 downto 0) = X"FFFFDC" then -- 0x23FFFFB8
demux_readdata <= x"0" & last_rd_addr3(27 downto 16);
demux_readdatavalid <= '1';
demux_readdatavalid_p1 <= '1';
my_transaction_type <= TYPE_REG;
elsif demux_readaddress(23 downto 0) = X"FFFFDD" then -- 0x23FFFFBA
demux_readdata <= last_rd_addr3(15 downto 0);
demux_readdatavalid <= '1';
demux_readdatavalid_p1 <= '1';
my_transaction_type <= TYPE_REG;
elsif demux_readaddress(23 downto 0) = X"FFFFDE" then -- 0x23FFFFBC
demux_readdata <= x"0" & last_rd_addr4(27 downto 16);
demux_readdatavalid <= '1';
demux_readdatavalid_p1 <= '1';
my_transaction_type <= TYPE_REG;
elsif demux_readaddress(23 downto 0) = X"FFFFDF" then -- 0x23FFFFBE
demux_readdata <= last_rd_addr4(15 downto 0);
demux_readdatavalid <= '1';
demux_readdatavalid_p1 <= '1';
my_transaction_type <= TYPE_REG;
elsif demux_readaddress(23 downto 0) = X"FFFFE0" then -- 0x23FFFFC0
demux_readdata <= rdwr_access_buff(127 downto 112);
demux_readdatavalid <= '1';
demux_readdatavalid_p1 <= '1';
my_transaction_type <= TYPE_REG;
elsif demux_readaddress(23 downto 0) = X"FFFFE1" then -- 0x23FFFFC2
demux_readdata <= rdwr_access_buff(111 downto 96);
demux_readdatavalid <= '1';
demux_readdatavalid_p1 <= '1';
my_transaction_type <= TYPE_REG;
elsif demux_readaddress(23 downto 0) = X"FFFFE2" then -- 0x23FFFFC4
demux_readdata <= rdwr_access_buff( 95 downto 80);
demux_readdatavalid <= '1';
demux_readdatavalid_p1 <= '1';
my_transaction_type <= TYPE_REG;
elsif demux_readaddress(23 downto 0) = X"FFFFE3" then -- 0x23FFFFC6
demux_readdata <= rdwr_access_buff( 79 downto 64);
demux_readdatavalid <= '1';
demux_readdatavalid_p1 <= '1';
my_transaction_type <= TYPE_REG;
elsif demux_readaddress(23 downto 0) = X"FFFFE4" then -- 0x23FFFFC8
demux_readdata <= rdwr_access_buff( 63 downto 48);
demux_readdatavalid <= '1';
demux_readdatavalid_p1 <= '1';
my_transaction_type <= TYPE_REG;
elsif demux_readaddress(23 downto 0) = X"FFFFE5" then -- 0x23FFFFCA
demux_readdata <= rdwr_access_buff( 47 downto 32);
demux_readdatavalid <= '1';
demux_readdatavalid_p1 <= '1';
my_transaction_type <= TYPE_REG;
elsif demux_readaddress(23 downto 0) = X"FFFFE6" then -- 0x23FFFFCC
demux_readdata <= rdwr_access_buff( 31 downto 16);
demux_readdatavalid <= '1';
demux_readdatavalid_p1 <= '1';
my_transaction_type <= TYPE_REG;
elsif demux_readaddress(23 downto 0) = X"FFFFE7" then -- 0x23FFFFCE
demux_readdata <= rdwr_access_buff( 15 downto 0);
demux_readdatavalid <= '1';
demux_readdatavalid_p1 <= '1';
my_transaction_type <= TYPE_REG;
elsif demux_readaddress(23 downto 0) = X"FFFFE8" then -- 0x23FFFFD0
demux_readdata <= x"5445"; -- "TE"
demux_readdatavalid <= '1';
demux_readdatavalid_p1 <= '1';
my_transaction_type <= TYPE_REG;
elsif demux_readaddress(23 downto 0) = X"FFFFE9" then -- 0x23FFFFD2
demux_readdata <= x"5354"; -- "ST"
demux_readdatavalid <= '1';
demux_readdatavalid_p1 <= '1';
my_transaction_type <= TYPE_REG;
elsif demux_readaddress(23 downto 0) = X"FFFFEA" then -- 0x23FFFFD4
demux_readdata <= X"FFFF";
demux_readdatavalid <= '1';
demux_readdatavalid_p1 <= '1';
my_transaction_type <= TYPE_REG;
elsif demux_readaddress(23 downto 0) = X"FFFFEB" then -- 0x23FFFFD6
demux_readdata <= X"5A5A";
demux_readdatavalid <= '1';
demux_readdatavalid_p1 <= '1';
my_transaction_type <= TYPE_REG;
elsif demux_readaddress(23 downto 0) = X"FFFFEC" then -- 0x23FFFFD8
demux_readdata <= X"FFFF";
demux_readdatavalid <= '1';
demux_readdatavalid_p1 <= '1';
my_transaction_type <= TYPE_REG;
elsif demux_readaddress(23 downto 0) = X"FFFFED" then -- 0x23FFFFDA
demux_readdata <= X"FFFF";
demux_readdatavalid <= '1';
demux_readdatavalid_p1 <= '1';
my_transaction_type <= TYPE_REG;
elsif demux_readaddress(23 downto 0) = X"FFFFEE" then -- 0x23FFFFDC
demux_readdata <= X"FFFF";
demux_readdatavalid <= '1';
demux_readdatavalid_p1 <= '1';
my_transaction_type <= TYPE_REG;
elsif demux_readaddress(23 downto 0) = X"FFFFEF" then -- 0x23FFFFDE
demux_readdata <= X"FFFF";
demux_readdatavalid <= '1';
demux_readdatavalid_p1 <= '1';
my_transaction_type <= TYPE_REG;
-- Access test stuff, added 2019/11/04 ^^^
elsif demux_readaddress(23 downto 0) = X"FFFFF0" then -- 0x23FFFFE0
demux_readdata <= X"FFFF"; -- Test for cartridge assembly
demux_readdatavalid <= '1';
demux_readdatavalid_p1 <= '1';
my_transaction_type <= TYPE_REG;
elsif demux_readaddress(23 downto 0) = X"FFFFF1" then -- 0x23FFFFE2
demux_readdata <= X"0000"; -- Test for cartridge assembly
demux_readdatavalid <= '1';
demux_readdatavalid_p1 <= '1';
my_transaction_type <= TYPE_REG;
elsif demux_readaddress(23 downto 0) = X"FFFFF2" then -- 0x23FFFFE4
demux_readdata <= X"A5A5"; -- Test for cartridge assembly
demux_readdatavalid <= '1';
demux_readdatavalid_p1 <= '1';
my_transaction_type <= TYPE_REG;
elsif demux_readaddress(23 downto 0) = X"FFFFF3" then -- 0x23FFFFE6
demux_readdata <= X"5A5A"; -- Test for cartridge assembly
demux_readdatavalid <= '1';
demux_readdatavalid_p1 <= '1';
my_transaction_type <= TYPE_REG;
elsif demux_readaddress(23 downto 0) = X"FFFFF4" then -- 0x23FFFFE8
demux_readdata <= x"CA" & rd_access_cntr;
demux_readdatavalid <= '1';
demux_readdatavalid_p1 <= '1';
my_transaction_type <= TYPE_REG;
elsif demux_readaddress(23 downto 0) = X"FFFFF5" then -- 0x23FFFFEA
demux_readdata <= x"AC" & rd_access_cntr;
demux_readdatavalid <= '1';
demux_readdatavalid_p1 <= '1';
my_transaction_type <= TYPE_REG;
elsif demux_readaddress(23 downto 0) = X"FFFFF6" then -- 0x23FFFFEC
demux_readdata <= x"FE" & wr_access_cntr;
demux_readdatavalid <= '1';
demux_readdatavalid_p1 <= '1';
my_transaction_type <= TYPE_REG;
elsif demux_readaddress(23 downto 0) = X"FFFFF7" then -- 0x23FFFFEE
demux_readdata <= x"EF" & wr_access_cntr;
demux_readdatavalid <= '1';
demux_readdatavalid_p1 <= '1';
my_transaction_type <= TYPE_REG;
elsif demux_readaddress(23 downto 0) = X"FFFFF8" then -- 0x23FFFFF0
--wasca prepare counter
demux_readdata <= REG_PCNTR;
demux_readdatavalid <= '1';
demux_readdatavalid_p1 <= '1';
my_transaction_type <= TYPE_REG;
elsif demux_readaddress(23 downto 0) = X"FFFFF9" then -- 0x23FFFFF2
--wasca status register
demux_readdata <= REG_STATUS;
demux_readdatavalid <= '1';
demux_readdatavalid_p1 <= '1';
my_transaction_type <= TYPE_REG;
elsif demux_readaddress(23 downto 0) = X"FFFFFA" then -- 0x23FFFFF4
--wasca mode register
demux_readdata <= REG_MODE;
demux_readdatavalid <= '1';
demux_readdatavalid_p1 <= '1';
my_transaction_type <= TYPE_REG;
elsif demux_readaddress(23 downto 0) = X"FFFFFB" then -- 0x23FFFFF6
--wasca hwver register
demux_readdata <= REG_HWVER;
demux_readdatavalid <= '1';
demux_readdatavalid_p1 <= '1';
my_transaction_type <= TYPE_REG;
elsif demux_readaddress(23 downto 0) = X"FFFFFC" then -- 0x23FFFFF8
--wasca swver register
demux_readdata <= REG_SWVER;
demux_readdatavalid <= '1';
demux_readdatavalid_p1 <= '1';
my_transaction_type <= TYPE_REG;
elsif demux_readaddress(23 downto 0) = X"FFFFFD" then -- 0x23FFFFFA
--wasca signature "wa"
demux_readdata <= X"7761";
demux_readdatavalid <= '1';
demux_readdatavalid_p1 <= '1';
my_transaction_type <= TYPE_REG;
elsif demux_readaddress(23 downto 0) = X"FFFFFE" then
--wasca signature "sc"
demux_readdata <= X"7363";
demux_readdatavalid <= '1';
demux_readdatavalid_p1 <= '1';
my_transaction_type <= TYPE_REG;
elsif demux_readaddress(23 downto 0) = X"FFFFFF" then
--wasca signature "a "
demux_readdata <= X"6120";
demux_readdatavalid <= '1';
demux_readdatavalid_p1 <= '1';
my_transaction_type <= TYPE_REG;
else
--normal CS0 read access
avalon_read <= '1';
--demux_readdata <= X"FF0A";
demux_readdatavalid <= '0';
my_transaction_type <= TYPE_AVALON;
avalon_address <= "1" & demux_readaddress(23) & "00" & demux_readaddress(22 downto 0) & "0"; -- SDRAM and OCRAM available from A-Bus
-- Set the data masks to read all bytes
avalon_byteenable <= "11";
rd_access_cntr <= rd_access_cntr + x"01";
last_rd_addr <= demux_readaddress;
-- case wasca_mode is
-- when MODE_INIT => demux_readdata <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
-- when MODE_POWER_MEMORY_05M => demux_readdata <= X"FFFF";
-- when MODE_POWER_MEMORY_1M => demux_readdata <= X"FFFF";
-- when MODE_POWER_MEMORY_2M => demux_readdata <= X"FFFF";
-- when MODE_POWER_MEMORY_4M => demux_readdata <= X"FFFF";
-- when MODE_RAM_1M => demux_readdata <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
-- when MODE_RAM_4M => demux_readdata <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
-- when MODE_ROM_KOF95 => demux_readdata <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
-- when MODE_ROM_ULTRAMAN => demux_readdata <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
-- when MODE_BOOT => demux_readdata <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
-- end case;
end if;
elsif demux_readaddress(25 downto 24) = "01" then
--CS1 access
if ( demux_readaddress(23 downto 0) = X"FFFFFF" or demux_readaddress(23 downto 0) = X"FFFFFD" ) then
--saturn cart id register
case wasca_mode is
when MODE_INIT => demux_readdata <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_05M => demux_readdata <= X"FF21";
when MODE_POWER_MEMORY_1M => demux_readdata <= X"FF22";
when MODE_POWER_MEMORY_2M => demux_readdata <= X"FF23";
when MODE_POWER_MEMORY_4M => demux_readdata <= X"FF24";
when MODE_RAM_1M => demux_readdata <= X"FF5A";
when MODE_RAM_4M => demux_readdata <= X"FF5C";
when MODE_ROM_KOF95 => demux_readdata <= X"FFFD";
when MODE_ROM_ULTRAMAN => demux_readdata <= X"FFFE";
when MODE_BOOT => demux_readdata <= X"FFAA";
end case;
demux_readdatavalid <= '1';
demux_readdatavalid_p1 <= '1';
my_transaction_type <= TYPE_REG;
else
--normal CS1 access
avalon_read <= '1';
--demux_readdata <= X"FF0A";
demux_readdatavalid <= '0';
my_transaction_type <= TYPE_AVALON;
avalon_address <= "1" & demux_readaddress(23) & "00" & demux_readaddress(22 downto 0) & "0"; -- SDRAM and OCRAM available from A-Bus
-- Set the data masks to read all bytes
avalon_byteenable <= "11";
rd_access_cntr <= rd_access_cntr + x"01";
last_rd_addr <= demux_readaddress;
-- case wasca_mode is
--
-- -- [DEBUG]Show which address is being accessed,
-- -- [DEBUG]in order to verify multiplexer wiring.
-- --when MODE_INIT => demux_readdata <= demux_readaddress(15 downto 0);
--
-- when MODE_INIT => demux_readdata <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
-- when MODE_POWER_MEMORY_05M => demux_readdata <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
-- when MODE_POWER_MEMORY_1M => demux_readdata <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
-- when MODE_POWER_MEMORY_2M => demux_readdata <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
-- when MODE_POWER_MEMORY_4M => demux_readdata <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
-- when MODE_RAM_1M => demux_readdata <= X"FFF1";
-- when MODE_RAM_4M => demux_readdata <= X"FFF2";
-- when MODE_ROM_KOF95 => demux_readdata <= X"FFF3";
-- when MODE_ROM_ULTRAMAN => demux_readdata <= X"FFF4";
-- when MODE_BOOT => demux_readdata <= X"FFF5";
-- end case;
end if;
else
--CS2 access
demux_readdata <= X"EEEE";
demux_readdatavalid <= '1';
my_transaction_type <= TYPE_REG;
end if;
elsif demux_writepulse = '1' then
-- Debug stuff around Rd/Wr access
wr_access_cntr <= wr_access_cntr + x"01";
last_wr_addr <= demux_writeaddress;
last_wr_data <= demux_writedata;
--if demux_writeaddress(25 downto 24) = "00" then <-- Don't care about CS for now.
if demux_writeaddress(23 downto 0) = X"FFFFFA" then -- 0x23FFFFF4
--wasca mode register
REG_MODE <= demux_writedata;
case (demux_writedata (3 downto 0)) is
when X"1" => wasca_mode <= MODE_POWER_MEMORY_05M;
when X"2" => wasca_mode <= MODE_POWER_MEMORY_1M;
when X"3" => wasca_mode <= MODE_POWER_MEMORY_2M;
when X"4" => wasca_mode <= MODE_POWER_MEMORY_4M;
when others =>
case (demux_writedata (7 downto 4)) is
when X"1" => wasca_mode <= MODE_RAM_1M;
when X"2" => wasca_mode <= MODE_RAM_4M;
when others =>
case (demux_writedata (11 downto 8)) is
when X"1" => wasca_mode <= MODE_ROM_KOF95;
when X"2" => wasca_mode <= MODE_ROM_ULTRAMAN;
when others => null;-- wasca_mode <= MODE_INIT;
end case;
end case;
end case;
my_transaction_type <= TYPE_REG;
-- Access test stuff, added 2019/11/04 vvv
elsif demux_writeaddress(23 downto 0) = X"FFFFE0" then -- 0x23FFFFC0
if(demux_write_byteenable(1) = '1') then rdwr_access_buff(127 downto 120) <= demux_writedata(15 downto 8); end if;
if(demux_write_byteenable(0) = '1') then rdwr_access_buff(119 downto 112) <= demux_writedata( 7 downto 0); end if;
my_transaction_type <= TYPE_REG;
elsif demux_writeaddress(23 downto 0) = X"FFFFE1" then -- 0x23FFFFC2
if(demux_write_byteenable(1) = '1') then rdwr_access_buff(111 downto 104) <= demux_writedata(15 downto 8); end if;
if(demux_write_byteenable(0) = '1') then rdwr_access_buff(103 downto 96) <= demux_writedata( 7 downto 0); end if;
my_transaction_type <= TYPE_REG;
elsif demux_writeaddress(23 downto 0) = X"FFFFE2" then -- 0x23FFFFC4
if(demux_write_byteenable(1) = '1') then rdwr_access_buff( 95 downto 88) <= demux_writedata(15 downto 8); end if;
if(demux_write_byteenable(0) = '1') then rdwr_access_buff( 87 downto 80) <= demux_writedata( 7 downto 0); end if;
my_transaction_type <= TYPE_REG;
elsif demux_writeaddress(23 downto 0) = X"FFFFE3" then -- 0x23FFFFC6
if(demux_write_byteenable(1) = '1') then rdwr_access_buff( 79 downto 72) <= demux_writedata(15 downto 8); end if;
if(demux_write_byteenable(0) = '1') then rdwr_access_buff( 71 downto 64) <= demux_writedata( 7 downto 0); end if;
my_transaction_type <= TYPE_REG;
elsif demux_writeaddress(23 downto 0) = X"FFFFE4" then -- 0x23FFFFC8
if(demux_write_byteenable(1) = '1') then rdwr_access_buff( 63 downto 56) <= demux_writedata(15 downto 8); end if;
if(demux_write_byteenable(0) = '1') then rdwr_access_buff( 55 downto 48) <= demux_writedata( 7 downto 0); end if;
my_transaction_type <= TYPE_REG;
elsif demux_writeaddress(23 downto 0) = X"FFFFE5" then -- 0x23FFFFCA
if(demux_write_byteenable(1) = '1') then rdwr_access_buff( 47 downto 40) <= demux_writedata(15 downto 8); end if;
if(demux_write_byteenable(0) = '1') then rdwr_access_buff( 39 downto 32) <= demux_writedata( 7 downto 0); end if;
my_transaction_type <= TYPE_REG;
elsif demux_writeaddress(23 downto 0) = X"FFFFE6" then -- 0x23FFFFCC
if(demux_write_byteenable(1) = '1') then rdwr_access_buff( 31 downto 24) <= demux_writedata(15 downto 8); end if;
if(demux_write_byteenable(0) = '1') then rdwr_access_buff( 23 downto 16) <= demux_writedata( 7 downto 0); end if;
my_transaction_type <= TYPE_REG;
elsif demux_writeaddress(23 downto 0) = X"FFFFE7" then -- 0x23FFFFCE
if(demux_write_byteenable(1) = '1') then rdwr_access_buff( 15 downto 8) <= demux_writedata(15 downto 8); end if;
if(demux_write_byteenable(0) = '1') then rdwr_access_buff( 7 downto 0) <= demux_writedata( 7 downto 0); end if;
my_transaction_type <= TYPE_REG;
-- Access test stuff, added 2019/11/04 ^^^
else
-- avalon-to-abus mapping
-- SDRAM is mapped to both CS0 and CS1
--
-- Note about address : from NIOS side, SDRAM is mapped to 0x0800_0000,
-- | so that the prefix at upper bits of the address passed to avalon.
-- | And A-Bus data width is 16 bits so that lower address bit is zeroed.
--
-- Additionally, extra OCRAM is mapped to 0x0C00_0000 from NIOS side,
-- and is (temporarily) available from A-Bus' second half of CS0.
--avalon_address <= "010" & demux_writeaddress(23 downto 0) & "0"; -- SDRAM available from A-Bus (old mapping, just here for reference)
avalon_writedata <= demux_writedata(7 downto 0) & demux_writedata(15 downto 8);
avalon_byteenable(0) <= demux_write_byteenable(0);
avalon_byteenable(1) <= demux_write_byteenable(1);
avalon_burstcount <= '1';
avalon_write <= '1';
my_transaction_type <= TYPE_AVALON;
avalon_address <= "1" & demux_writeaddress(23) & "00" & demux_writeaddress(22 downto 0) & "0"; -- SDRAM and OCRAM available from A-Bus
end if;
end if;
end if;
end process;
---------------------------------------------------------------------------------------
--Nios II read interface
process (clock)
begin
if rising_edge(clock) then
if avalon_nios_read = '1' then
avalon_nios_readdatavalid <= '1';
case avalon_nios_address is
-- Debug stuff around Rd/Wr access
when X"00" =>
avalon_nios_readdata <= x"0" & last_rd_addr;
when X"02" =>
avalon_nios_readdata <= x"0" & last_rd_addr1;
when X"03" =>
avalon_nios_readdata <= x"0" & last_rd_addr2;
when X"04" =>
avalon_nios_readdata <= x"0" & last_rd_addr3;
when X"05" =>
avalon_nios_readdata <= x"0" & last_rd_addr4;
when X"08" =>
avalon_nios_readdata <= x"0000CA" & rd_access_cntr;
when X"09" =>
avalon_nios_readdata <= x"0000FE" & wr_access_cntr;
when X"10" =>
avalon_nios_readdata <= x"0" & last_wr_addr;
when X"11" =>
avalon_nios_readdata <= x"0000" & last_wr_data;
--when X"F0" =>
-- avalon_nios_readdata <= REG_PCNTR;
--when X"F2" =>
-- avalon_nios_readdata <= REG_STATUS;
--when X"F4" =>
-- avalon_nios_readdata <= REG_MODE;
--when X"F6" =>
-- avalon_nios_readdata <= REG_HWVER;
--when X"F8" =>
-- avalon_nios_readdata <= REG_SWVER;
when others =>
avalon_nios_readdata <= X"00000000";
end case;
else
avalon_nios_readdatavalid <= '0';
end if;
end if;
end process;
---------------------------------------------------------------------------------------
--Nios II write interface
process (clock)
begin
if rising_edge(clock) then
if avalon_nios_write= '1' then
case avalon_nios_address is
--when X"F0" =>
-- REG_PCNTR <= avalon_nios_writedata(15 downto 0);
--when X"F2" =>
-- REG_STATUS <= avalon_nios_writedata(15 downto 0);
--when X"F4" =>
-- null;
--when X"F6" =>
-- null;
--when X"F8" =>
-- REG_SWVER <= avalon_nios_writedata(15 downto 0);
when others =>
null;
end case;
end if;
end if;
end process;
--Nios system interface is only regs, so always ready to write.
avalon_nios_waitrequest <= '0';
end architecture rtl; -- of abus_slave
| gpl-2.0 | 48bfa510ce8a85438b11bb881a143f37 | 0.459877 | 4.442898 | false | false | false | false |
michaelfivez/ascon_hardware_implementation | ascon12864_unrolled3/Kernel/Ascon_block_control.vhd | 1 | 7,055 | -------------------------------------------------------------------------------
--! @project Unrolled (3) hardware implementation of Asconv1286
--! @author Michael Fivez
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is an hardware implementation made for my graduation thesis
--! at the KULeuven, in the COSIC department (year 2015-2016)
--! The thesis is titled 'Energy efficient hardware implementations of CAESAR submissions',
--! and can be found on the COSIC website (www.esat.kuleuven.be/cosic/publications)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Ascon_StateUpdate_control is
port(
Clk : in std_logic; -- Clock
Reset : in std_logic; -- Reset (synchronous)
-- Control signals
RoundNr : out std_logic_vector(3 downto 0); -- biggest round is 12
sel1,sel2,sel3,sel4 : out std_logic_vector(1 downto 0);
sel0 : out std_logic_vector(2 downto 0);
selout : out std_logic;
Reg0En,Reg1En,Reg2En,Reg3En,Reg4En,RegOutEn : out std_logic;
ActivateGen : out std_logic;
GenSize : out std_logic_vector(2 downto 0);
-- External control signals
Start : in std_logic;
Mode : in std_logic_vector(3 downto 0);
Size : in std_logic_vector(2 downto 0); -- only matters for last block decryption
Busy : out std_logic
);
end entity Ascon_StateUpdate_control;
architecture structural of Ascon_StateUpdate_control is
begin
-----------------------------------------
------ The Finite state machine --------
-----------------------------------------
-- Modes: initialization, associative data, encryption, decryption, tag generation, final encryption, final decryption, seperation constant
-- 0010 0000 0110 0100 0001 0111 0101, 0011
-- case1 1000, case2 1001
fsm: process(Clk, Reset) is
type state_type is (IDLE,LOADNEW,CRYPT,TAG);
variable CurrState : state_type := IDLE;
variable RoundNrVar : std_logic_vector(3 downto 0);
begin
if Clk'event and Clk = '1' then
-- default values
sel0 <= "000";
sel1 <= "00";
sel2 <= "00";
sel3 <= "00";
sel4 <= "00";
selout <= '0';
Reg0En <= '0';
Reg1En <= '0';
Reg2En <= '0';
Reg3En <= '0';
Reg4En <= '0';
RegOutEn <= '0';
ActivateGen <= '0';
GenSize <= "000";
Busy <= '0';
if Reset = '1' then -- synchronous reset active high
-- registers used by fsm:
RoundNrVar := "0000";
CurrState := IDLE;
else
FSMlogic : case CurrState is
when IDLE =>
if Start = '1' then
Busy <= '1';
if Mode = "0000" then -- AD mode
RoundNrVar := "1101"; -- so starts at 0 next cycle
-- set Sel and Enables signal (Xor with DataIn)
sel0 <= "010";
Reg0En <= '1';
CurrState := CRYPT;
elsif Mode = "0100" then -- Decryption mode
RoundNrVar := "1101"; -- so starts at 0 next cycle
-- set Sel and Enables signal (Generate output and xor state)
ActivateGen <= '1';
sel0 <= "010";
Reg0En <= '1';
RegOutEn <= '1';
CurrState := CRYPT;
elsif Mode = "0110" then -- Encryption
RoundNrVar := "1101"; -- so starts at 0 next cycle
-- set Sel and Enables signal (Generate output and xor state)
sel0 <= "010";
Reg0En <= '1';
RegOutEn <= '1';
CurrState := CRYPT;
elsif Mode = "0001" then -- Tag mode
RoundNrVar := "1101"; -- so starts at 0 next cycle
-- set Sel and Enables signal (XOR middle with key)
sel1 <= "10";
sel2 <= "11";
Reg1En <= '1';
Reg2En <= '1';
CurrState := TAG;
elsif Mode = "0111" then -- Last block encryption
-- set Sel and Enables signal (Generate output and xor state)
sel0 <= "010";
Reg0En <= '1';
RegOutEn <= '1';
CurrState := IDLE;
elsif Mode = "0101" then -- Last block decryption
-- set Sel and Enables signal (Generate output and xor state)
ActivateGen <= '1';
GenSize <= Size;
sel0 <= "010";
Reg0En <= '1';
RegOutEn <= '1';
CurrState := IDLE;
elsif Mode = "0011" then -- Seperation constant
sel4 <= "11";
Reg4En <= '1';
CurrState := IDLE;
elsif Mode = "0010" then -- Initialization mode
RoundNrVar := "1101"; -- so starts at 0 next cycle
-- set Sel and Enables signal (Load in key and IV)
sel0 <= "001";
sel1 <= "01";
sel2 <= "01";
sel3 <= "01";
sel4 <= "01";
Reg0En <= '1';
Reg1En <= '1';
Reg2En <= '1';
Reg3En <= '1';
Reg4En <= '1';
CurrState := LOADNEW;
elsif Mode = "1000" then -- case1
sel0 <= "100";
Reg0En <= '1';
CurrState := IDLE;
else -- case2
sel0 <= "100";
Reg0En <= '1';
RoundNrVar := "1101"; -- so starts at 0 next cycle
CurrState := CRYPT;
end if;
else
Busy <= '0';
CurrState := IDLE;
end if;
when LOADNEW =>
if RoundNrVar = "1001" then -- RoundNrVar = 11
-- set Sel and Enables signal (Xor at the end)
sel3 <= "10";
sel4 <= "10";
Reg3En <= '1';
Reg4En <= '1';
CurrState := IDLE;
Busy <= '0';
else
RoundNrVar := std_logic_vector(unsigned(RoundNrVar) + 3);
-- set Sel and Enables signal (execute a round)
Reg0En <= '1';
Reg1En <= '1';
Reg2En <= '1';
Reg3En <= '1';
Reg4En <= '1';
CurrState := LOADNEW;
Busy <= '1';
end if;
when CRYPT =>
if RoundNrVar = "0000" then -- RoundNrVar = 4
RoundNrVar := std_logic_vector(unsigned(RoundNrVar) + 3);
-- set Sel and Enables signal (execute a round)
Reg0En <= '1';
Reg1En <= '1';
Reg2En <= '1';
Reg3En <= '1';
Reg4En <= '1';
CurrState := IDLE;
Busy <= '0';
else
RoundNrVar := std_logic_vector(unsigned(RoundNrVar) + 3);
-- set Sel and Enables signal (execute a round)
Reg0En <= '1';
Reg1En <= '1';
Reg2En <= '1';
Reg3En <= '1';
Reg4En <= '1';
CurrState := CRYPT;
Busy <= '1';
end if;
when TAG =>
if RoundNrVar = "1001" then -- RoundNrVar = 11
-- set Sel and Enables signal (connect tag to output)
selout <= '1';
RegOutEn <= '1';
CurrState := IDLE;
Busy <= '0';
else
RoundNrVar := std_logic_vector(unsigned(RoundNrVar) + 3);
-- set Sel and Enables signal (execute a round)
Reg0En <= '1';
Reg1En <= '1';
Reg2En <= '1';
Reg3En <= '1';
Reg4En <= '1';
CurrState := TAG;
Busy <= '1';
end if;
end case FSMlogic;
RoundNr <= RoundNrVar;
end if;
end if;
end process fsm;
end architecture structural;
| gpl-3.0 | 08331e742acccb89dbd7d4470aae9084 | 0.540609 | 3.222933 | false | false | false | false |
cafe-alpha/wascafe | v13/wasca_10m08scv4k_no_spi_20190420/wasca/synthesis/submodules/sega_saturn_abus_slave.vhd | 3 | 27,894 | -- sega_saturn_abus_slave.vhd
library IEEE;
use IEEE.numeric_std.all;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sega_saturn_abus_slave is
port (
clock : in std_logic := '0'; -- clock.clk
abus_address : in std_logic_vector(9 downto 0) := (others => '0'); -- abus.address
abus_addressdata : inout std_logic_vector(15 downto 0) := (others => '0'); -- abus.addressdata
abus_chipselect : in std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
abus_read : in std_logic := '0'; -- .read
abus_write : in std_logic_vector(1 downto 0) := (others => '0'); -- .write
--abus_functioncode : in std_logic_vector(1 downto 0) := (others => '0'); -- .functioncode
--abus_timing : in std_logic_vector(2 downto 0) := (others => '0'); -- .timing
abus_waitrequest : out std_logic := '1'; -- .waitrequest
--abus_addressstrobe : in std_logic := '0'; -- .addressstrobe
abus_interrupt : out std_logic := '0'; -- .interrupt
abus_direction : out std_logic := '0'; -- .direction
abus_muxing : out std_logic_vector(1 downto 0) := "01"; -- .muxing
abus_disable_out : out std_logic := '0'; -- .disableout
avalon_read : out std_logic; -- avalon_master.read
avalon_write : out std_logic; -- .write
avalon_waitrequest : in std_logic := '0'; -- .waitrequest
avalon_address : out std_logic_vector(27 downto 0); -- .address
avalon_readdata : in std_logic_vector(15 downto 0) := (others => '0'); -- .readdata
avalon_writedata : out std_logic_vector(15 downto 0); -- .writedata
avalon_burstcount : out std_logic; -- .burstcount
avalon_readdatavalid : in std_logic := '0'; -- .readdatavalid
avalon_nios_read : in std_logic := '0'; -- avalon_master.read
avalon_nios_write : in std_logic := '0'; -- .write
avalon_nios_waitrequest : out std_logic := '0'; -- .waitrequest
avalon_nios_address : in std_logic_vector(7 downto 0) := (others => '0'); -- .address
avalon_nios_writedata : in std_logic_vector(15 downto 0) := (others => '0'); -- .writedata
avalon_nios_burstcount : in std_logic; -- .burstcount
avalon_nios_readdata : out std_logic_vector(15 downto 0) := (others => '0'); -- .readdata
avalon_nios_readdatavalid : out std_logic := '0'; -- .readdatavalid
saturn_reset : in std_logic := '0'; -- .saturn_reset
reset : in std_logic := '0' -- reset.reset
);
end entity sega_saturn_abus_slave;
architecture rtl of sega_saturn_abus_slave is
signal abus_address_ms : std_logic_vector(9 downto 0) := (others => '0'); -- abus.address
signal abus_address_buf : std_logic_vector(9 downto 0) := (others => '0'); -- abus.address
signal abus_addressdata_ms : std_logic_vector(15 downto 0) := (others => '0'); -- .data
signal abus_addressdata_buf : std_logic_vector(15 downto 0) := (others => '0'); -- .data
signal abus_chipselect_ms : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_chipselect_buf : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_read_ms : std_logic := '0'; -- .read
signal abus_read_buf : std_logic := '0'; -- .read
signal abus_write_ms : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_write_buf : std_logic_vector(1 downto 0) := (others => '0'); -- .write
--signal abus_functioncode_ms : std_logic_vector(1 downto 0) := (others => '0'); -- .functioncode
--signal abus_functioncode_buf : std_logic_vector(1 downto 0) := (others => '0'); -- .functioncode
--signal abus_timing_ms : std_logic_vector(2 downto 0) := (others => '0'); -- .timing
--signal abus_timing_buf : std_logic_vector(2 downto 0) := (others => '0'); -- .timing
--signal abus_addressstrobe_ms : std_logic := '0'; -- .addressstrobe
--signal abus_addressstrobe_buf : std_logic := '0'; -- .addressstrobe
signal abus_read_buf2 : std_logic := '0'; -- .read
signal abus_read_buf3 : std_logic := '0'; -- .read
signal abus_read_buf4 : std_logic := '0'; -- .read
signal abus_read_buf5 : std_logic := '0'; -- .read
signal abus_read_buf6 : std_logic := '0'; -- .read
signal abus_read_buf7 : std_logic := '0'; -- .read
signal abus_write_buf2 : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_chipselect_buf2 : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_read_pulse : std_logic := '0'; -- .read
signal abus_write_pulse : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_chipselect_pulse : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_read_pulse_off : std_logic := '0'; -- .read
signal abus_write_pulse_off : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_chipselect_pulse_off : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_anypulse : std_logic := '0';
signal abus_anypulse2 : std_logic := '0';
signal abus_anypulse3 : std_logic := '0';
signal abus_anypulse_off : std_logic := '0';
signal abus_cspulse : std_logic := '0';
signal abus_cspulse2 : std_logic := '0';
signal abus_cspulse3 : std_logic := '0';
signal abus_cspulse4 : std_logic := '0';
signal abus_cspulse5 : std_logic := '0';
signal abus_cspulse6 : std_logic := '0';
signal abus_cspulse7 : std_logic := '0';
signal abus_cspulse_off : std_logic := '0';
signal abus_address_latched : std_logic_vector(25 downto 0) := (others => '0'); -- abus.address
signal abus_chipselect_latched : std_logic_vector(1 downto 0) := (others => '1'); -- abus.address
signal abus_direction_internal : std_logic := '0';
signal abus_muxing_internal : std_logic_vector(1 downto 0) := (others => '0'); -- abus.address
signal abus_data_out : std_logic_vector(15 downto 0) := (others => '0');
signal abus_data_in : std_logic_vector(15 downto 0) := (others => '0');
signal abus_waitrequest_read : std_logic := '0';
signal abus_waitrequest_write : std_logic := '0';
signal abus_waitrequest_read2 : std_logic := '0';
signal abus_waitrequest_write2 : std_logic := '0';
--signal abus_waitrequest_read3 : std_logic := '0';
--signal abus_waitrequest_write3 : std_logic := '0';
--signal abus_waitrequest_read4 : std_logic := '0';
--signal abus_waitrequest_write4 : std_logic := '0';
signal abus_waitrequest_read_off : std_logic := '0';
signal abus_waitrequest_write_off : std_logic := '0';
-- For Rd/Wr access debug
signal rd_access_cntr : std_logic_vector( 7 downto 0) := x"01";
signal wr_access_cntr : std_logic_vector( 7 downto 0) := x"01";
signal last_rd_addr : std_logic_vector(15 downto 0) := x"1230"; -- lower 16 bits only
signal last_wr_addr : std_logic_vector(15 downto 0) := x"1231"; -- lower 16 bits only
signal last_wr_data : std_logic_vector(15 downto 0) := x"5678";
signal REG_PCNTR : std_logic_vector(15 downto 0) := (others => '0');
signal REG_STATUS : std_logic_vector(15 downto 0) := (others => '0');
signal REG_MODE : std_logic_vector(15 downto 0) := (others => '0');
signal REG_HWVER : std_logic_vector(15 downto 0) := X"0002";
signal REG_SWVER : std_logic_vector(15 downto 0) := (others => '0');
TYPE transaction_dir IS (DIR_NONE,DIR_WRITE,DIR_READ);
SIGNAL my_little_transaction_dir : transaction_dir := DIR_NONE;
TYPE wasca_mode_type IS (MODE_INIT,
MODE_POWER_MEMORY_05M, MODE_POWER_MEMORY_1M, MODE_POWER_MEMORY_2M, MODE_POWER_MEMORY_4M,
MODE_RAM_1M, MODE_RAM_4M,
MODE_ROM_KOF95,
MODE_ROM_ULTRAMAN,
MODE_BOOT);
SIGNAL wasca_mode : wasca_mode_type := MODE_INIT;
begin
abus_direction <= abus_direction_internal;
abus_muxing <= not abus_muxing_internal;
--ignoring functioncode, timing and addressstrobe for now
--abus transactions are async, so first we must latch incoming signals
--to get rid of metastability
process (clock)
begin
if rising_edge(clock) then
--1st stage
abus_address_ms <= abus_address;
abus_addressdata_ms <= abus_addressdata;
abus_chipselect_ms <= abus_chipselect; --work only with CS1 for now
abus_read_ms <= abus_read;
abus_write_ms <= abus_write;
--abus_functioncode_ms <= abus_functioncode;
--abus_timing_ms <= abus_timing;
--abus_addressstrobe_ms <= abus_addressstrobe;
--2nd stage
abus_address_buf <= abus_address_ms;
abus_addressdata_buf <= abus_addressdata_ms;
abus_chipselect_buf <= abus_chipselect_ms;
abus_read_buf <= abus_read_ms;
abus_write_buf <= abus_write_ms;
--abus_functioncode_buf <= abus_functioncode_ms;
--abus_timing_buf <= abus_timing_ms;
--abus_addressstrobe_buf <= abus_addressstrobe_ms;
end if;
end process;
--excluding metastability protection is a bad behavior
--but it lloks like we're out of more options to optimize read pipeline
--abus_read_ms <= abus_read;
--abus_read_buf <= abus_read_ms;
--abus read/write latch
process (clock)
begin
if rising_edge(clock) then
abus_write_buf2 <= abus_write_buf;
abus_read_buf2 <= abus_read_buf;
abus_read_buf3 <= abus_read_buf2;
abus_read_buf4 <= abus_read_buf3;
abus_read_buf5 <= abus_read_buf4;
abus_read_buf6 <= abus_read_buf5;
abus_read_buf7 <= abus_read_buf6;
abus_chipselect_buf2 <= abus_chipselect_buf;
abus_anypulse2 <= abus_anypulse;
abus_anypulse3 <= abus_anypulse2;
abus_cspulse2 <= abus_cspulse;
abus_cspulse3 <= abus_cspulse2;
abus_cspulse4 <= abus_cspulse3;
abus_cspulse5 <= abus_cspulse4;
abus_cspulse6 <= abus_cspulse5;
abus_cspulse7 <= abus_cspulse6;
end if;
end process;
--abus write/read pulse is a falling edge since read and write signals are negative polarity
abus_write_pulse <= abus_write_buf2 and not abus_write_buf;
abus_read_pulse <= abus_read_buf2 and not abus_read_buf;
--abus_chipselect_pulse <= abus_chipselect_buf2 and not abus_chipselect_buf;
abus_chipselect_pulse <= abus_chipselect_buf and not abus_chipselect_ms;
abus_write_pulse_off <= abus_write_buf and not abus_write_buf2;
abus_read_pulse_off <= abus_read_buf and not abus_read_buf2;
abus_chipselect_pulse_off <= abus_chipselect_buf and not abus_chipselect_buf2;
abus_anypulse <= abus_write_pulse(0) or abus_write_pulse(1) or abus_read_pulse or
abus_chipselect_pulse(0) or abus_chipselect_pulse(1) or abus_chipselect_pulse(2);
abus_anypulse_off <= abus_write_pulse_off(0) or abus_write_pulse_off(1) or abus_read_pulse_off or
abus_chipselect_pulse_off(0) or abus_chipselect_pulse_off(1) or abus_chipselect_pulse_off(2);
abus_cspulse <= abus_chipselect_pulse(0) or abus_chipselect_pulse(1) or abus_chipselect_pulse(2);
abus_cspulse_off <= abus_chipselect_pulse_off(0) or abus_chipselect_pulse_off(1) or abus_chipselect_pulse_off(2);
--whatever pulse we've got, latch address
--it might be latched twice per transaction, but it's not a problem
--multiplexer was switched to address after previous transaction or after boot,
--so we have address ready to latch
process (clock)
begin
if rising_edge(clock) then
if abus_anypulse = '1' then
--if abus_read_pulse = '1' or abus_write_pulse(0) = '1' or abus_write_pulse(1)='1' then
abus_address_latched <= abus_address & abus_addressdata_buf(0) & abus_addressdata_buf(12) & abus_addressdata_buf(2) & abus_addressdata_buf(1)
& abus_addressdata_buf(9) & abus_addressdata_buf(10) & abus_addressdata_buf(8) & abus_addressdata_buf(3)
& abus_addressdata_buf(13) & abus_addressdata_buf(14) & abus_addressdata_buf(15) & abus_addressdata_buf(4)
& abus_addressdata_buf(5) & abus_addressdata_buf(6) & abus_addressdata_buf(11) & abus_addressdata_buf(7);
end if;
end if;
end process;
--latch transaction direction
process (clock)
begin
if rising_edge(clock) then
if abus_write_pulse(0) = '1' or abus_write_pulse(1) = '1' then
my_little_transaction_dir <= DIR_WRITE;
elsif abus_read_pulse = '1' then
my_little_transaction_dir <= DIR_READ;
elsif abus_anypulse_off = '1' and abus_cspulse_off = '0' then --ending anything but not cs
my_little_transaction_dir <= DIR_NONE;
end if;
end if;
end process;
--latch chipselect number
process (clock)
begin
if rising_edge(clock) then
if abus_chipselect_pulse(0) = '1' then
abus_chipselect_latched <= "00";
elsif abus_chipselect_pulse(1) = '1' then
abus_chipselect_latched <= "01";
elsif abus_chipselect_pulse(2) = '1' then
abus_chipselect_latched <= "10";
elsif abus_cspulse_off = '1' then
abus_chipselect_latched <= "11";
end if;
end if;
end process;
--if valid transaction captured, switch to corresponding multiplex mode
process (clock)
begin
if rising_edge(clock) then
if abus_chipselect_latched = "11" then
--chipselect deasserted
abus_direction_internal <= '0'; --high-z
abus_muxing_internal <= "01"; --address
else
--chipselect asserted
case (my_little_transaction_dir) is
when DIR_NONE =>
abus_direction_internal <= '0'; --high-z
abus_muxing_internal <= "10"; --data
when DIR_READ =>
abus_direction_internal <= '1'; --active
abus_muxing_internal <= "10"; --data
when DIR_WRITE =>
abus_direction_internal <= '0'; --high-z
abus_muxing_internal <= "10"; --data
end case;
end if;
end if;
end process;
abus_disable_out <= '1' when abus_chipselect_latched(1) = '1' else
'0';
--if abus read access is detected, issue avalon read transaction
--wait until readdatavalid, then disable read and abus wait
process (clock)
begin
if rising_edge(clock) then
--if my_little_transaction_dir = DIR_READ and abus_chipselect_latched(1) = '0' and abus_anypulse2 = '1' then
--starting read transaction at either RD pulse or (CS pulse while RD is on)
--but if CS arrives less than 7 clocks after RD, then we ignore this CS
--this will get us 2 additional clocks at read pipeline
if abus_read_pulse = '1' or (abus_cspulse='1' and abus_read_buf = '0' and abus_read_buf7 = '0') then
avalon_read <= '1';
abus_waitrequest_read <= '1';
elsif avalon_readdatavalid = '1' then
-- Debug stuff around Rd/Wr access
rd_access_cntr <= rd_access_cntr + x"01";
last_rd_addr <= abus_address_latched(15 downto 0);
avalon_read <= '0';
abus_waitrequest_read <= '0';
if abus_chipselect_latched = "00" then
--CS0 access
if abus_address_latched(24 downto 0) = "1"&X"FF0FFE" then
--wasca specific SD card control register
abus_data_out <= X"CDCD";
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFE0" then
abus_data_out <= X"FFFF"; -- Test for cartridge assembly
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFE2" then
abus_data_out <= X"0000"; -- Test for cartridge assembly
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFE4" then
abus_data_out <= X"A5A5"; -- Test for cartridge assembly
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFE6" then
abus_data_out <= X"5A5A"; -- Test for cartridge assembly
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFE8" then
abus_data_out <= x"CA" & rd_access_cntr;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFEA" then
abus_data_out <= x"CA" & rd_access_cntr;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFEC" then
abus_data_out <= x"FE" & wr_access_cntr;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFEE" then
abus_data_out <= x"FE" & wr_access_cntr;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF0" then
--wasca prepare counter
abus_data_out <= REG_PCNTR;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF2" then
--wasca status register
abus_data_out <= REG_STATUS;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF4" then
--wasca mode register
abus_data_out <= REG_MODE;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF6" then
--wasca hwver register
abus_data_out <= REG_HWVER;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF8" then
--wasca swver register
abus_data_out <= REG_SWVER;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFFA" then
--wasca signature "wa"
abus_data_out <= X"7761";
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFFC" then
--wasca signature "sc"
abus_data_out <= X"7363";
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFFE" then
--wasca signature "a "
abus_data_out <= X"6120";
else
--normal CS0 read access
case wasca_mode is
when MODE_INIT => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_05M => abus_data_out <= X"FFFF";
when MODE_POWER_MEMORY_1M => abus_data_out <= X"FFFF";
when MODE_POWER_MEMORY_2M => abus_data_out <= X"FFFF";
when MODE_POWER_MEMORY_4M => abus_data_out <= X"FFFF";
when MODE_RAM_1M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_RAM_4M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_ROM_KOF95 => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_ROM_ULTRAMAN => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_BOOT => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
end case;
end if;
elsif abus_chipselect_latched = "01" then
--CS1 access
if ( abus_address_latched(23 downto 0) = X"FFFFFE" or abus_address_latched(23 downto 0) = X"FFFFFC" ) then
--saturn cart id register
case wasca_mode is
when MODE_INIT => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_05M => abus_data_out <= X"FF21";
when MODE_POWER_MEMORY_1M => abus_data_out <= X"FF22";
when MODE_POWER_MEMORY_2M => abus_data_out <= X"FF23";
when MODE_POWER_MEMORY_4M => abus_data_out <= X"FF24";
when MODE_RAM_1M => abus_data_out <= X"FF5A";
when MODE_RAM_4M => abus_data_out <= X"FF5C";
when MODE_ROM_KOF95 => abus_data_out <= X"FFFF";
when MODE_ROM_ULTRAMAN => abus_data_out <= X"FFFF";
when MODE_BOOT => abus_data_out <= X"FFFF";
end case;
else
--normal CS1 access
case wasca_mode is
when MODE_INIT => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_05M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_1M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_2M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_4M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_RAM_1M => abus_data_out <= X"FFFF";
when MODE_RAM_4M => abus_data_out <= X"FFFF";
when MODE_ROM_KOF95 => abus_data_out <= X"FFFF";
when MODE_ROM_ULTRAMAN => abus_data_out <= X"FFFF";
when MODE_BOOT => abus_data_out <= X"FFFF";
end case;
end if;
else
--CS2 access
abus_data_out <= X"EEEE";
end if;
end if;
end if;
end process;
--if abus write access is detected, issue avalon write transaction
--disable abus wait immediately
--TODO: check if avalon_writedata is already valid at this moment
process (clock)
begin
if rising_edge(clock) then
if my_little_transaction_dir = DIR_WRITE and abus_chipselect_latched /= "11" and abus_cspulse7 = '1' then
--pass write to avalon
avalon_write <= '1';
abus_waitrequest_write <= '1';
elsif avalon_waitrequest = '0' then
avalon_write <= '0';
abus_waitrequest_write <= '0';
end if;
end if;
end process;
--wasca mode register write
--reset
process (clock)
begin
if rising_edge(clock) then
--if saturn_reset='0' then wasca_mode <= MODE_INIT;
--els
-- Debug stuff around Rd/Wr access
if my_little_transaction_dir = DIR_WRITE and abus_chipselect_latched = "00" and abus_cspulse7 = '1' then
wr_access_cntr <= wr_access_cntr + x"01";
last_wr_addr <= abus_address_latched(15 downto 0);
last_wr_data <= abus_data_in;
end if;
if my_little_transaction_dir = DIR_WRITE and abus_chipselect_latched = "00" and abus_cspulse7 = '1' and
abus_address_latched(23 downto 0) = X"FFFFF4" then
--wasca mode register
REG_MODE <= abus_data_in;
case (abus_data_in (3 downto 0)) is
when X"1" => wasca_mode <= MODE_POWER_MEMORY_05M;
when X"2" => wasca_mode <= MODE_POWER_MEMORY_1M;
when X"3" => wasca_mode <= MODE_POWER_MEMORY_2M;
when X"4" => wasca_mode <= MODE_POWER_MEMORY_4M;
when others =>
case (abus_data_in (7 downto 4)) is
when X"1" => wasca_mode <= MODE_RAM_1M;
when X"2" => wasca_mode <= MODE_RAM_4M;
when others =>
case (abus_data_in (11 downto 8)) is
when X"1" => wasca_mode <= MODE_ROM_KOF95;
when X"2" => wasca_mode <= MODE_ROM_ULTRAMAN;
when others => null;-- wasca_mode <= MODE_INIT;
end case;
end case;
end case;
end if;
end if;
end process;
abus_data_in <= abus_addressdata_buf;
--working only if direction is 1
abus_addressdata <= (others => 'Z') when abus_direction_internal='0' else
abus_data_out;
process (clock)
begin
if rising_edge(clock) then
abus_waitrequest_read2 <= abus_waitrequest_read;
--abus_waitrequest_read3 <= abus_waitrequest_read2;
--abus_waitrequest_read4 <= abus_waitrequest_read3;
abus_waitrequest_write2 <= abus_waitrequest_write;
--abus_waitrequest_write3 <= abus_waitrequest_write3;
--abus_waitrequest_write4 <= abus_waitrequest_write4;
end if;
end process;
process (clock)
begin
if rising_edge(clock) then
abus_waitrequest_read_off <= '0';
abus_waitrequest_write_off <= '0';
if abus_waitrequest_read = '0' and abus_waitrequest_read2 = '1' then
abus_waitrequest_read_off <= '1';
end if;
if abus_waitrequest_write = '0' and abus_waitrequest_write2 = '1' then
abus_waitrequest_write_off <= '1';
end if;
end if;
end process;
--process (clock)
--begin
-- if rising_edge(clock) then
-- --if abus_read_pulse='1' or abus_write_pulse(0)='1' or abus_write_pulse(1)='1' then
-- --if abus_anypulse = '1' then
-- if abus_chipselect_pulse(0) = '1' or abus_chipselect_pulse(1) = '1' then
-- abus_waitrequest <= '0';
-- elsif abus_waitrequest_read_off='1' or abus_waitrequest_write_off='1' then
-- abus_waitrequest <= '1';
-- end if;
-- end if;
--end process;
--avalon-to-abus mapping
--SDRAM is mapped to both CS0 and CS1
avalon_address <= "010" & abus_address_latched(24 downto 0);
avalon_writedata <= abus_data_in(7 downto 0) & abus_data_in (15 downto 8) ;
avalon_burstcount <= '0';
abus_waitrequest <= not (abus_waitrequest_read or abus_waitrequest_write);
--Nios II read interface
process (clock)
begin
if rising_edge(clock) then
avalon_nios_readdatavalid <= '0';
if avalon_nios_read = '1' then
avalon_nios_readdatavalid <= '1';
case avalon_nios_address is
-- Debug stuff around Rd/Wr access
when X"E0" =>
avalon_nios_readdata <= x"CA" & rd_access_cntr;
when X"E2" =>
avalon_nios_readdata <= x"FE" & wr_access_cntr;
when X"E4" =>
avalon_nios_readdata <= last_rd_addr;
when X"E6" =>
avalon_nios_readdata <= last_wr_addr;
when X"E8" =>
avalon_nios_readdata <= last_wr_data;
when X"F0" =>
avalon_nios_readdata <= REG_PCNTR;
when X"F2" =>
avalon_nios_readdata <= REG_STATUS;
when X"F4" =>
avalon_nios_readdata <= REG_MODE;
when X"F6" =>
avalon_nios_readdata <= REG_HWVER;
when X"F8" =>
avalon_nios_readdata <= REG_SWVER;
when X"FA" =>
avalon_nios_readdata <= X"ABCD"; --for debug, remove later
when others =>
avalon_nios_readdata <= REG_HWVER; --to simplify mux
end case;
end if;
end if;
end process;
--Nios II write interface
process (clock)
begin
if rising_edge(clock) then
if avalon_nios_write= '1' then
case avalon_nios_address is
when X"F0" =>
REG_PCNTR <= avalon_nios_writedata;
when X"F2" =>
REG_STATUS <= avalon_nios_writedata;
when X"F4" =>
null;
when X"F6" =>
null;
when X"F8" =>
REG_SWVER <= avalon_nios_writedata;
when others =>
null;
end case;
end if;
end if;
end process;
--Nios system interface is only regs, so always ready to write.
avalon_nios_waitrequest <= '0';
end architecture rtl; -- of sega_saturn_abus_slave
| gpl-2.0 | 09a508ef9cbcc9b6f49478d5fa07f585 | 0.571951 | 3.318344 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/opencores/ata/ud_cnt.vhd | 2 | 4,365 | ---------------------------------------------------------------------
---- ----
---- Generic Up/Down counter (ripple carry architecture) ----
---- ----
---- Author: Richard Herveille ----
---- [email protected] ----
---- www.asics.ws ----
---- ----
---------------------------------------------------------------------
---- ----
---- Copyright (C) 2001, 2002 Richard Herveille ----
---- [email protected] ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
---- ----
---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
---- POSSIBILITY OF SUCH DAMAGE. ----
---- ----
---------------------------------------------------------------------
--
-- CVS Log
--
-- $Id: ud_cnt.vhd,v 1.1 2002/03/01 03:49:03 rherveille Exp $
--
-- $Date: 2002/03/01 03:49:03 $
-- $Revision: 1.1 $
-- $Author: rherveille $
-- $Locker: $
-- $State: Exp $
--
-- Change History:
-- $Log: ud_cnt.vhd,v $
-- Revision 1.1 2002/03/01 03:49:03 rherveille
-- Changed internal counter libraries.
-- Split counter.vhd into separate files.
-- Core is in same state as Verilog version now.
--
library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_arith.all;
library grlib;
use grlib.stdlib.all;
entity ud_cnt is
generic(
SIZE : natural := 8;
RESD : natural := 0
);
port(
clk : in std_logic; -- master clock
nReset : in std_logic := '1'; -- asynchronous active low reset
rst : in std_logic := '0'; -- synchronous active high reset
cnt_en : in std_logic := '1'; -- count enable
ud : in std_logic := '0'; -- up / not down
nld : in std_logic := '1'; -- synchronous active low load
d : in std_logic_vector(SIZE -1 downto 0); -- load counter value
q : out std_logic_vector(SIZE -1 downto 0); -- current counter value
rci : in std_logic := '1'; -- carry input
rco : out std_logic -- carry output
);
end entity ud_cnt;
architecture structural of ud_cnt is
signal Qi : std_logic_vector(SIZE -1 downto 0);
signal val : std_logic_vector(SIZE downto 0);
begin
val <= ( ('0' & Qi) + rci) when (ud = '1') else ( ('0' & Qi) - rci);
regs: process(clk, nReset)
begin
if (nReset = '0') then
Qi <= conv_std_logic_vector(RESD, SIZE);
elsif (clk'event and clk = '1') then
if (rst = '1') then
Qi <= conv_std_logic_vector(RESD, SIZE);
else
if (nld = '0') then
Qi <= D;
elsif (cnt_en = '1') then
Qi <= val(SIZE -1 downto 0);
end if;
end if;
end if;
end process regs;
-- assign outputs
Q <= Qi;
rco <= val(SIZE);
end architecture structural;
| mit | ab63b043a6b6cf5047e400aa035b10a6 | 0.464834 | 4.229651 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/memctrl/sdmctrl.vhd | 2 | 18,379 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: sdmctrl
-- File: sdmctrl.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: SDRAM memory controller to fit with LEON2 memory controller.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.memctrl.all;
entity sdmctrl is
generic (
pindex : integer := 0;
invclk : integer := 0;
fast : integer := 0;
wprot : integer := 0;
sdbits : integer := 32;
pageburst : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
sdi : in sdram_in_type;
sdo : out sdram_out_type;
apbi : in apb_slv_in_type;
wpo : in wprot_out_type;
sdmo : out sdram_mctrl_out_type
);
end;
architecture rtl of sdmctrl is
constant WPROTEN : boolean := (wprot /= 0);
constant SDINVCLK : boolean := (invclk /= 0);
constant BUS64 : boolean := (sdbits = 64);
type mcycletype is (midle, active, leadout);
type sdcycletype is (act1, act2, act3, rd1, rd2, rd3, rd4, rd5, rd6, rd7, rd8,
wr1, wr2, wr3, wr4, wr5, sidle);
type icycletype is (iidle, pre, ref, lmode, finish);
-- sdram configuration register
type sdram_cfg_type is record
command : std_logic_vector(1 downto 0);
csize : std_logic_vector(1 downto 0);
bsize : std_logic_vector(2 downto 0);
casdel : std_ulogic; -- CAS to data delay: 2/3 clock cycles
trfc : std_logic_vector(2 downto 0);
trp : std_ulogic; -- precharge to activate: 2/3 clock cycles
refresh : std_logic_vector(14 downto 0);
renable : std_ulogic;
pageburst : std_ulogic;
end record;
-- local registers
type reg_type is record
hready : std_ulogic;
hsel : std_ulogic;
bdrive : std_ulogic;
burst : std_ulogic;
busy : std_ulogic;
bdelay : std_ulogic;
wprothit : std_ulogic;
startsd : std_ulogic;
aload : std_ulogic;
mstate : mcycletype;
sdstate : sdcycletype;
cmstate : mcycletype;
istate : icycletype;
icnt : std_logic_vector(2 downto 0);
cfg : sdram_cfg_type;
trfc : std_logic_vector(2 downto 0);
refresh : std_logic_vector(14 downto 0);
sdcsn : std_logic_vector(1 downto 0);
sdwen : std_ulogic;
rasn : std_ulogic;
casn : std_ulogic;
dqm : std_logic_vector(7 downto 0);
bsel : std_ulogic;
haddr : std_logic_vector(31 downto 10);
-- only needed to keep address lines from switch too much
address : std_logic_vector(16 downto 2); -- memory address
end record;
signal r, ri : reg_type;
begin
ctrl : process(rst, apbi, sdi, wpo, r)
variable v : reg_type; -- local variables for registers
variable startsd : std_ulogic;
variable dataout : std_logic_vector(31 downto 0); -- data from memory
variable haddr : std_logic_vector(31 downto 0);
variable regsd : std_logic_vector(31 downto 0); -- data from registers
variable dqm : std_logic_vector(7 downto 0);
variable raddr : std_logic_vector(12 downto 0);
variable adec : std_ulogic;
variable busy : std_ulogic;
variable aload : std_ulogic;
variable rams : std_logic_vector(1 downto 0);
variable hresp : std_logic_vector(1 downto 0);
variable ba : std_logic_vector(1 downto 0);
variable lline : std_logic_vector(2 downto 0);
variable rline : std_logic_vector(2 downto 0);
variable lineburst : boolean;
begin
-- Variable default settings to avoid latches
v := r; startsd := '0'; v.busy := '0'; hresp := HRESP_OKAY;
lline := not r.cfg.casdel & r.cfg.casdel & r.cfg.casdel;
rline := not r.cfg.casdel & r.cfg.casdel & r.cfg.casdel;
if sdi.hready = '1' then v.hsel := sdi.hsel; end if;
if (sdi.hready and sdi.hsel ) = '1' then
if sdi.htrans(1) = '1' then v.hready := '0'; end if;
end if;
if fast = 1 then haddr := sdi.rhaddr; else haddr := sdi.haddr; end if;
if (pageburst = 0) or ((pageburst = 2) and r.cfg.pageburst = '0') then
lineburst := true;
else lineburst := false; end if;
-- main state
case sdi.hsize is
when "00" =>
case sdi.rhaddr(1 downto 0) is
when "00" => dqm := "11110111";
when "01" => dqm := "11111011";
when "10" => dqm := "11111101";
when others => dqm := "11111110";
end case;
when "01" =>
if sdi.rhaddr(1) = '0' then dqm := "11110011"; else dqm := "11111100"; end if;
when others => dqm := "11110000";
end case;
if BUS64 and (r.bsel = '1') then
dqm := dqm(3 downto 0) & "1111";
end if;
-- main FSM
case r.mstate is
when midle =>
if (v.hsel and sdi.nhtrans(1)) = '1' then
if (r.sdstate = sidle) and (r.cfg.command = "00") and
(r.cmstate = midle) and (sdi.idle = '1')
then
if fast = 1 then v.startsd := '1'; else startsd := '1'; end if;
v.mstate := active;
end if;
end if;
when others => null;
end case;
startsd := r.startsd or startsd;
-- generate row and column address size
case r.cfg.csize is
when "00" => raddr := haddr(22 downto 10);
when "01" => raddr := haddr(23 downto 11);
when "10" => raddr := haddr(24 downto 12);
when others =>
if r.cfg.bsize = "111" then raddr := haddr(26 downto 14);
else raddr := haddr(25 downto 13); end if;
end case;
-- generate bank address
ba := genmux(r.cfg.bsize, haddr(28 downto 21)) &
genmux(r.cfg.bsize, haddr(27 downto 20));
-- generate chip select
if BUS64 then
adec := genmux(r.cfg.bsize, haddr(30 downto 23));
v.bsel := genmux(r.cfg.bsize, sdi.rhaddr(29 downto 22));
else
adec := genmux(r.cfg.bsize, haddr(29 downto 22)); v.bsel := '0';
end if;
if (sdi.srdis = '0') and (r.cfg.bsize = "111") then adec := not adec; end if;
rams := adec & not adec;
if r.trfc /= "000" then v.trfc := r.trfc - 1; end if;
-- sdram access FSM
case r.sdstate is
when sidle =>
v.bdelay := '0';
if (startsd = '1') and (r.cfg.command = "00") and (r.cmstate = midle) then
v.address(16 downto 2) := ba & raddr;
v.sdcsn := not rams(1 downto 0); v.rasn := '0'; v.sdstate := act1;
v.startsd := '0';
end if;
when act1 =>
v.rasn := '1'; v.trfc := r.cfg.trfc; v.haddr := sdi.rhaddr(31 downto 10);
if r.cfg.casdel = '1' then v.sdstate := act2; else
v.sdstate := act3;
v.hready := sdi.hwrite and sdi.htrans(0) and sdi.htrans(1);
end if;
if WPROTEN then
v.wprothit := wpo.wprothit;
if wpo.wprothit = '1' then hresp := HRESP_ERROR; end if;
end if;
when act2 =>
v.sdstate := act3;
v.hready := sdi.hwrite and sdi.htrans(0) and sdi.htrans(1);
if WPROTEN and (r.wprothit = '1') then
hresp := HRESP_ERROR; v.hready := '0';
end if;
when act3 =>
v.casn := '0';
v.address(14 downto 2) := sdi.rhaddr(13 downto 12) & '0' & sdi.rhaddr(11 downto 2);
v.dqm := dqm; v.burst := r.hready;
if sdi.hwrite = '1' then
v.sdstate := wr1; v.sdwen := '0'; v.bdrive := '1';
if sdi.htrans = "11" or (r.hready = '0') then v.hready := '1'; end if;
if WPROTEN and (r.wprothit = '1') then
hresp := HRESP_ERROR; v.hready := '1';
v.sdstate := wr1; v.sdwen := '1'; v.bdrive := '0'; v.casn := '1';
end if;
else v.sdstate := rd1; end if;
when wr1 =>
v.address(14 downto 2) := sdi.rhaddr(13 downto 12) & '0' & sdi.rhaddr(11 downto 2);
if (((r.burst and r.hready) = '1') and (sdi.rhtrans = "11"))
and not (WPROTEN and (r.wprothit = '1'))
then
v.hready := sdi.htrans(0) and sdi.htrans(1) and r.hready;
if ((sdi.rhaddr(5 downto 2) = "1111") and (r.cfg.command = "10")) then -- exit on refresh
v.hready := '0';
end if;
else
v.sdstate := wr2; v.bdrive := '0'; v.casn := '1'; v.sdwen := '1';
v.dqm := (others => '1');
end if;
when wr2 =>
if (sdi.rhtrans = "10") and (sdi.rhaddr(31 downto 10) = r.haddr) and (r.hsel = '1') then
if sdi.hwrite = '1' then v.hready := '1'; end if; v.sdstate := act3;
elsif (r.trfc(2 downto 1) = "00") then
if (r.cfg.trp = '0') then v.rasn := '0'; v.sdwen := '0'; end if;
v.sdstate := wr3;
end if;
when wr3 =>
if (sdi.rhtrans = "10") and (sdi.rhaddr(31 downto 10) = r.haddr) and (r.sdwen = '1') and (r.hsel = '1') then
if sdi.hwrite = '1' then v.hready := '1'; end if; v.sdstate := act3;
elsif (r.cfg.trp = '1') then
v.rasn := '0'; v.sdwen := '0'; v.sdstate := wr4;
else
v.sdcsn := "11"; v.rasn := '1'; v.sdwen := '1';
if r.trfc = "000" then v.sdstate := sidle; end if;
end if;
when wr4 =>
v.sdcsn := "11"; v.rasn := '1'; v.sdwen := '1';
if (r.cfg.trp = '1') then v.sdstate := wr5;
else
if r.trfc = "000" then v.sdstate := sidle; end if;
end if;
when wr5 =>
if r.trfc = "000" then v.sdstate := sidle; end if;
when rd1 =>
v.casn := '1'; v.sdstate := rd7;
if lineburst and (sdi.htrans = "11") then
if sdi.rhaddr(4 downto 2) = "111" then
v.address(9 downto 5) := r.address(9 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
when rd7 =>
v.casn := '1';
if r.cfg.casdel = '1' then
v.sdstate := rd2;
if lineburst and (sdi.htrans = "11") then
if sdi.rhaddr(4 downto 2) = "110" then
v.address(9 downto 5) := r.address(9 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
else
v.sdstate := rd3;
if sdi.htrans /= "11" then
if (r.trfc(2 downto 1) = "00") then v.rasn := '0'; v.sdwen := '0'; end if;
elsif lineburst then
if sdi.rhaddr(4 downto 2) = "110" then
v.address(9 downto 5) := r.address(9 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
end if;
when rd2 =>
v.casn := '1'; v.sdstate := rd3;
if sdi.htrans /= "11" then -- v.rasn := '0'; v.sdwen := '0';
if (r.trfc(2 downto 1) = "00") then v.rasn := '0'; v.sdwen := '0'; end if;
elsif lineburst then
if sdi.rhaddr(4 downto 2) = "101" then
v.address(9 downto 5) := r.address(9 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
if v.sdwen = '0' then v.dqm := (others => '1'); end if;
when rd3 =>
v.sdstate := rd4; v.hready := '1'; v.casn := '1';
if r.sdwen = '0' then
v.rasn := '1'; v.sdwen := '1'; v.sdcsn := "11"; v.dqm := (others => '1');
elsif lineburst and (sdi.htrans = "11") and (r.casn = '1') then
if sdi.rhaddr(4 downto 2) = ("10" & not r.cfg.casdel) then
v.address(9 downto 5) := r.address(9 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
when rd4 =>
v.hready := '1'; v.casn := '1';
if (sdi.htrans /= "11") or (r.sdcsn = "11") or
((sdi.rhaddr(5 downto 2) = "1111") and (r.cfg.command = "10")) -- exit on refresh
then
v.hready := '0'; v.dqm := (others => '1');
if (r.sdcsn /= "11") then
v.rasn := '0'; v.sdwen := '0'; v.sdstate := rd5;
else
if r.cfg.trp = '1' then v.sdstate := rd6;
else v.sdstate := sidle; end if;
end if;
elsif lineburst then
if (sdi.rhaddr(4 downto 2) = lline) and (r.casn = '1') then
v.address(9 downto 5) := r.address(9 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
when rd5 =>
if r.cfg.trp = '1' then v.sdstate := rd6; else v.sdstate := sidle; end if;
v.sdcsn := (others => '1'); v.rasn := '1'; v.sdwen := '1'; v.dqm := (others => '1');
v.casn := '1';
when rd6 =>
v.sdstate := sidle; v.dqm := (others => '1');
v.sdcsn := (others => '1'); v.rasn := '1'; v.sdwen := '1';
when others =>
v.sdstate := sidle;
end case;
-- sdram commands
case r.cmstate is
when midle =>
if r.sdstate = sidle then
case r.cfg.command is
when "01" => -- precharge
if (sdi.idle = '1') then
v.busy := '1';
v.sdcsn := (others => '0'); v.rasn := '0'; v.sdwen := '0';
v.address(12) := '1'; v.cmstate := active;
end if;
when "10" => -- auto-refresh
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.cmstate := active;
when "11" =>
if (sdi.idle = '1') then
v.busy := '1';
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.sdwen := '0'; v.cmstate := active;
if lineburst then
v.address(15 downto 2) := "000010001" & r.cfg.casdel & "0011";
else
v.address(15 downto 2) := "000010001" & r.cfg.casdel & "0111";
end if;
end if;
when others => null;
end case;
end if;
when active =>
v.sdcsn := (others => '1'); v.rasn := '1'; v.casn := '1';
v.sdwen := '1'; v.cfg.command := "00";
v.cmstate := leadout; v.trfc := r.cfg.trfc;
when leadout =>
if r.trfc = "000" then v.cmstate := midle; end if;
end case;
-- sdram init
case r.istate is
when iidle =>
if (sdi.idle and sdi.enable) = '1' then
v.cfg.command := "01"; v.istate := pre;
end if;
when pre =>
if r.cfg.command = "00" then
v.cfg.command := "10"; v.istate := ref; v.icnt := "111";
end if;
when ref =>
if r.cfg.command = "00" then
v.cfg.command := "10"; v.icnt := r.icnt - 1;
if r.icnt = "000" then v.istate := lmode; v.cfg.command := "11"; end if;
end if;
when lmode =>
if r.cfg.command = "00" then
v.istate := finish;
end if;
when others =>
if sdi.enable = '0' then
v.istate := iidle;
end if;
end case;
if (sdi.hready and sdi.hsel ) = '1' then
if sdi.htrans(1) = '0' then v.hready := '1'; end if;
end if;
-- second part of main fsm
case r.mstate is
when active =>
if v.hready = '1' then
v.mstate := midle;
end if;
when others => null;
end case;
-- sdram refresh counter
if (r.cfg.renable = '1') and (r.istate = finish) then
v.refresh := r.refresh - 1;
if (v.refresh(14) and not r.refresh(14)) = '1' then
v.refresh := r.cfg.refresh;
v.cfg.command := "10";
end if;
end if;
-- APB register access
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(3 downto 2) is
when "01" =>
if pageburst = 2 then v.cfg.pageburst := apbi.pwdata(17); end if;
if sdi.enable = '1' then
v.cfg.command := apbi.pwdata(20 downto 19);
end if;
v.cfg.csize := apbi.pwdata(22 downto 21);
v.cfg.bsize := apbi.pwdata(25 downto 23);
v.cfg.casdel := apbi.pwdata(26);
v.cfg.trfc := apbi.pwdata(29 downto 27);
v.cfg.trp := apbi.pwdata(30);
v.cfg.renable := apbi.pwdata(31);
when "10" =>
v.cfg.refresh := apbi.pwdata(26 downto 12);
v.refresh := (others => '0');
when others =>
end case;
end if;
regsd := (others => '0');
case apbi.paddr(3 downto 2) is
when "01" =>
regsd(31 downto 19) := r.cfg.renable & r.cfg.trp & r.cfg.trfc &
r.cfg.casdel & r.cfg.bsize & r.cfg.csize & r.cfg.command;
if not lineburst then regsd(17) := '1'; end if;
when others =>
regsd(26 downto 12) := r.cfg.refresh;
end case;
sdmo.prdata <= regsd;
-- synchronise with sram/prom controller
if fast = 0 then
if (r.sdstate < wr4) or (v.hsel = '1') then v.busy := '1';end if;
else
if (r.sdstate < wr4) or (r.startsd = '1') then v.busy := '1';end if;
end if;
v.busy := v.busy or r.bdelay;
busy := v.busy or r.busy;
v.aload := r.busy and not v.busy;
aload := v.aload;
-- generate memory address
sdmo.address <= v.address;
-- reset
if rst = '0' then
v.sdstate := sidle;
v.mstate := midle;
v.istate := iidle;
v.cmstate := midle;
v.hsel := '0';
v.cfg.command := "00";
v.cfg.csize := "10";
v.cfg.bsize := "000";
v.cfg.casdel := '1';
v.cfg.trfc := "111";
v.cfg.renable := '0';
v.cfg.trp := '1';
v.dqm := (others => '1');
v.sdwen := '1';
v.rasn := '1';
v.casn := '1';
v.hready := '1';
v.startsd := '0';
if (pageburst = 2) then
v.cfg.pageburst := '0';
end if;
end if;
ri <= v;
sdmo.bdrive <= v.bdrive;
sdo.sdcke <= (others => '1');
sdo.sdcsn <= r.sdcsn;
sdo.sdwen <= r.sdwen;
sdo.dqm <= r.dqm;
sdo.rasn <= r.rasn;
sdo.casn <= r.casn;
sdmo.busy <= busy;
sdmo.aload <= aload;
sdmo.hready <= r.hready;
sdmo.hresp <= hresp;
sdmo.hsel <= r.hsel;
sdmo.bsel <= r.bsel;
end process;
regs : process(clk,rst)
begin
if rising_edge(clk) then
r <= ri;
if rst = '0' then
r.icnt <= (others => '0');
end if;
end if;
if rst = '0' then
r.bdrive <= '0';
r.sdcsn <= (others => '1');
end if;
end process;
end;
| mit | 8b8dab8656e081a08d7d4240689101a2 | 0.535938 | 3.12568 | false | false | false | false |
michaelfivez/ascon_hardware_implementation | ascon12864_unrolled2/Kernel/Ascon_block_datapath.vhd | 1 | 6,170 | -------------------------------------------------------------------------------
--! @project Unrolled (2) hardware implementation of Asconv1286
--! @author Michael Fivez
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is an hardware implementation made for my graduation thesis
--! at the KULeuven, in the COSIC department (year 2015-2016)
--! The thesis is titled 'Energy efficient hardware implementations of CAESAR submissions',
--! and can be found on the COSIC website (www.esat.kuleuven.be/cosic/publications)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Ascon_StateUpdate_datapath is
port(
Clk : in std_logic; -- Clock
Reset : in std_logic; -- Reset (synchronous)
-- Control signals
RoundNr : in std_logic_vector(2 downto 0); -- biggest round is 12
sel1,sel2,sel3,sel4 : in std_logic_vector(1 downto 0);
sel0 : in std_logic_vector(2 downto 0);
selout : in std_logic;
Reg0En,Reg1En,Reg2En,Reg3En,Reg4En,RegOutEn : in std_logic;
ActivateGen : in std_logic;
GenSize : in std_logic_vector(2 downto 0);
-- Data signals
IV : in std_logic_vector(127 downto 0);
Key : in std_logic_vector(127 downto 0);
DataIn : in std_logic_vector(63 downto 0);
DataOut : out std_logic_vector(127 downto 0)
);
end entity Ascon_StateUpdate_datapath;
architecture structural of Ascon_StateUpdate_datapath is
-- constants
constant EXTRAIV : std_logic_vector(63 downto 0) := x"80400c0600000000"; -- used in the initialization
constant SEPCONSTANT : std_logic_vector(63 downto 0) := x"0000000000000001";
constant ADCONSTANT : std_logic_vector(63 downto 0) := x"8000000000000000";
-- Register signals
signal Reg0In,Reg1In,Reg2In,Reg3In,Reg4In : std_logic_vector(63 downto 0);
signal Reg0Out,Reg1Out,Reg2Out,Reg3Out,Reg4Out : std_logic_vector(63 downto 0);
signal RegOutIn,RegOutOut : std_logic_vector(127 downto 0);
-- Internal signals on datapath
signal DiffOut0,DiffOut1,DiffOut2,DiffOut3,DiffOut4 : std_logic_vector(63 downto 0);
signal XorReg01,XorReg02,XorReg12,XorReg13,XorReg22 : std_logic_vector(63 downto 0);
signal XorReg2,XorReg31,XorReg4 : std_logic_vector(63 downto 0);
signal OutSig0: std_logic_vector(63 downto 0);
signal OutSig1: std_logic_vector(127 downto 0);
begin
-- declare and connect all sub entities
rounds: entity work.Fullrounds port map(Reg0Out,Reg1Out,Reg2Out,Reg3Out,Reg4Out,RoundNr,DiffOut0,DiffOut1,DiffOut2,DiffOut3,DiffOut4);
outpgen: entity work.OutputGenerator port map(Reg0Out,DataIn,GenSize,ActivateGen,XorReg01,OutSig0); -- ActivateGen is a bit that indicates decryption or not
---------------------------------------------
------ Combinatorial logic for a round ------
---------------------------------------------
datapath: process(IV,Key,DataIn,Reg0Out,Reg1Out,Reg2Out,Reg3Out,Reg4Out,RegOutOut, -- inputs blocks and registers
DiffOut0,DiffOut1,DiffOut2,DiffOut3,DiffOut4, -- internal signals
XorReg01,XorReg02,XorReg12,XorReg13,XorReg22,XorReg2,XorReg31,XorReg4,OutSig0,OutSig1, -- internal signals
RoundNr,sel0,sel1,sel2,sel3,sel4,ActivateGen,selout,GenSize) is -- control signals
begin
-- Set correct inputs in registers
if sel0 = "000" then
Reg0In <= DiffOut0;
elsif sel0 = "001" then
Reg0In <= EXTRAIV;
elsif sel0 = "010" then
Reg0In <= XorReg01;
elsif sel0 = "011" then
Reg0In <= XorReg02;
else
Reg0In <= Reg0Out xor ADCONSTANT;
end if;
if sel1 = "00" then
Reg1In <= DiffOut1;
elsif sel1 = "01" then
Reg1In <= Key(127 downto 64);
elsif sel1 = "10" then
Reg1In <= XorReg13;
else
Reg1In <= XorReg12;
end if;
if sel2 = "00" then
Reg2In <= DiffOut2;
elsif sel2 = "01" then
Reg2In <= Key(63 downto 0);
elsif sel2 = "10" then
Reg2In <= XorReg2;
else
Reg2In <= XorReg22;
end if;
if sel3 = "00" then
Reg3In <= DiffOut3;
elsif sel3 = "01" then
Reg3In <= IV(127 downto 64);
else
Reg3In <= XorReg31;
end if;
if sel4 = "00" then
Reg4In <= DiffOut4;
elsif sel4 = "01" then
Reg4In <= IV(63 downto 0);
elsif sel4 = "10" then
Reg4In <= XorReg4;
else
Reg4In <= Reg4Out xor SEPCONSTANT;
end if;
XorReg02 <= Reg0Out xor Key(127 downto 64);
XorReg12 <= Reg1Out xor Key(63 downto 0);
XorReg13 <= Reg1Out xor Key(127 downto 64);
XorReg22 <= Reg2Out xor Key(63 downto 0);
XorReg31 <= Reg3Out xor Key(127 downto 64);
XorReg4 <= Reg4Out xor Key(63 downto 0);
-- Set output
OutSig1(127 downto 64) <= XorReg31;
OutSig1(63 downto 0) <= XorReg4;
if selout = '0' then
RegOutIn(127 downto 64) <= (others => '0');
RegOutIn(63 downto 0) <= OutSig0;
else
RegOutIn <= OutSig1;
end if;
DataOut <= RegOutOut;
end process datapath;
---------------------------------------------
------ The registers in the datapath --------
---------------------------------------------
registerdatapath : process(Clk,Reset) is
begin
if(Clk = '1' and Clk'event) then
if Reset = '1' then -- synchronous reset
Reg0Out <= (others => '0');
Reg1Out <= (others => '0');
Reg2Out <= (others => '0');
Reg3Out <= (others => '0');
Reg4Out <= (others => '0');
RegOutOut <= (others => '0');
else
-- update registers with enable
if Reg0En = '1' then
Reg0Out <= Reg0In;
end if;
if Reg1En = '1' then
Reg1Out <= Reg1In;
end if;
if Reg2En = '1' then
Reg2Out <= Reg2In;
end if;
if Reg3En = '1' then
Reg3Out <= Reg3In;
end if;
if Reg4En = '1' then
Reg4Out <= Reg4In;
end if;
if RegOutEn = '1' then
RegOutOut <= RegOutIn;
end if;
end if;
end if;
end process registerdatapath;
end architecture structural;
| gpl-3.0 | 60bfa2e925f7b909e68486c850f265c8 | 0.619935 | 3.089634 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/grlib/amba/amba.vhd | 2 | 21,797 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: amba
-- File: amba.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: AMBA 2.0 bus signal definitions + support for plug&play
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- pragma translate_off
use std.textio.all;
-- pragma translate_on
library grlib;
use grlib.stdlib.all;
package amba is
constant NAHBMST : integer := 16; -- maximum AHB masters
constant NAHBSLV : integer := 16; -- maximum AHB slaves
constant NAPBSLV : integer := 16; -- maximum APB slaves
constant NAHBIRQ : integer := 32; -- maximum interrupts
constant NAHBAMR : integer := 4; -- maximum address mapping registers
constant NAHBIR : integer := 4; -- maximum AHB identification registers
constant NAHBCFG : integer := NAHBIR + NAHBAMR; -- words in AHB config block
constant NAPBIR : integer := 1; -- maximum APB configuration words
constant NAPBAMR : integer := 1; -- maximum APB configuration words
constant NAPBCFG : integer := NAPBIR + NAPBAMR; -- words in APB config block
constant NBUS : integer := 4;
subtype amba_config_word is std_logic_vector(31 downto 0);
type ahb_config_type is array (0 to NAHBCFG-1) of amba_config_word;
type apb_config_type is array (0 to NAPBCFG-1) of amba_config_word;
-- AHB master inputs
type ahb_mst_in_type is record
hgrant : std_logic_vector(0 to NAHBMST-1); -- bus grant
hready : std_ulogic; -- transfer done
hresp : std_logic_vector(1 downto 0); -- response type
hrdata : std_logic_vector(31 downto 0); -- read data bus
hcache : std_ulogic; -- cacheable
hirq : std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt result bus
testen : std_ulogic; -- scan test enable
testrst : std_ulogic; -- scan test reset
scanen : std_ulogic; -- scan enable
testoen : std_ulogic; -- test output enable
end record;
-- AHB master outputs
type ahb_mst_out_type is record
hbusreq : std_ulogic; -- bus request
hlock : std_ulogic; -- lock request
htrans : std_logic_vector(1 downto 0); -- transfer type
haddr : std_logic_vector(31 downto 0); -- address bus (byte)
hwrite : std_ulogic; -- read/write
hsize : std_logic_vector(2 downto 0); -- transfer size
hburst : std_logic_vector(2 downto 0); -- burst type
hprot : std_logic_vector(3 downto 0); -- protection control
hwdata : std_logic_vector(31 downto 0); -- write data bus
hirq : std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt bus
hconfig : ahb_config_type; -- memory access reg.
hindex : integer range 0 to NAHBMST-1; -- diagnostic use only
end record;
-- AHB slave inputs
type ahb_slv_in_type is record
hsel : std_logic_vector(0 to NAHBSLV-1); -- slave select
haddr : std_logic_vector(31 downto 0); -- address bus (byte)
hwrite : std_ulogic; -- read/write
htrans : std_logic_vector(1 downto 0); -- transfer type
hsize : std_logic_vector(2 downto 0); -- transfer size
hburst : std_logic_vector(2 downto 0); -- burst type
hwdata : std_logic_vector(31 downto 0); -- write data bus
hprot : std_logic_vector(3 downto 0); -- protection control
hready : std_ulogic; -- transfer done
hmaster : std_logic_vector(3 downto 0); -- current master
hmastlock : std_ulogic; -- locked access
hmbsel : std_logic_vector(0 to NAHBAMR-1); -- memory bank select
hcache : std_ulogic; -- cacheable
hirq : std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt result bus
testen : std_ulogic; -- scan test enable
testrst : std_ulogic; -- scan test reset
scanen : std_ulogic; -- scan enable
testoen : std_ulogic; -- test output enable
end record;
-- AHB slave outputs
type ahb_slv_out_type is record
hready : std_ulogic; -- transfer done
hresp : std_logic_vector(1 downto 0); -- response type
hrdata : std_logic_vector(31 downto 0); -- read data bus
hsplit : std_logic_vector(15 downto 0); -- split completion
hcache : std_ulogic; -- cacheable
hirq : std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt bus
hconfig : ahb_config_type; -- memory access reg.
hindex : integer range 0 to NAHBSLV-1; -- diagnostic use only
end record;
-- array types
type ahb_mst_out_vector_type is array (natural range <>) of ahb_mst_out_type;
type ahb_slv_out_vector_type is array (natural range <>) of ahb_slv_out_type;
subtype ahb_mst_out_vector is ahb_mst_out_vector_type(NAHBMST-1 downto 0);
subtype ahb_slv_out_vector is ahb_slv_out_vector_type(NAHBSLV-1 downto 0);
type ahb_mst_out_bus_vector is array (0 to NBUS-1) of ahb_mst_out_vector;
type ahb_slv_out_bus_vector is array (0 to NBUS-1) of ahb_slv_out_vector;
-- constants
constant HTRANS_IDLE: std_logic_vector(1 downto 0) := "00";
constant HTRANS_BUSY: std_logic_vector(1 downto 0) := "01";
constant HTRANS_NONSEQ: std_logic_vector(1 downto 0) := "10";
constant HTRANS_SEQ: std_logic_vector(1 downto 0) := "11";
constant HBURST_SINGLE: std_logic_vector(2 downto 0) := "000";
constant HBURST_INCR: std_logic_vector(2 downto 0) := "001";
constant HBURST_WRAP4: std_logic_vector(2 downto 0) := "010";
constant HBURST_INCR4: std_logic_vector(2 downto 0) := "011";
constant HBURST_WRAP8: std_logic_vector(2 downto 0) := "100";
constant HBURST_INCR8: std_logic_vector(2 downto 0) := "101";
constant HBURST_WRAP16: std_logic_vector(2 downto 0) := "110";
constant HBURST_INCR16: std_logic_vector(2 downto 0) := "111";
constant HSIZE_BYTE: std_logic_vector(2 downto 0) := "000";
constant HSIZE_HWORD: std_logic_vector(2 downto 0) := "001";
constant HSIZE_WORD: std_logic_vector(2 downto 0) := "010";
constant HSIZE_DWORD: std_logic_vector(2 downto 0) := "011";
constant HSIZE_4WORD: std_logic_vector(2 downto 0) := "100";
constant HSIZE_8WORD: std_logic_vector(2 downto 0) := "101";
constant HSIZE_16WORD: std_logic_vector(2 downto 0) := "110";
constant HSIZE_32WORD: std_logic_vector(2 downto 0) := "111";
constant HRESP_OKAY: std_logic_vector(1 downto 0) := "00";
constant HRESP_ERROR: std_logic_vector(1 downto 0) := "01";
constant HRESP_RETRY: std_logic_vector(1 downto 0) := "10";
constant HRESP_SPLIT: std_logic_vector(1 downto 0) := "11";
-- APB slave inputs
type apb_slv_in_type is record
psel : std_logic_vector(0 to NAPBSLV-1); -- slave select
penable : std_ulogic; -- strobe
paddr : std_logic_vector(31 downto 0); -- address bus (byte)
pwrite : std_ulogic; -- write
pwdata : std_logic_vector(31 downto 0); -- write data bus
pirq : std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt result bus
testen : std_ulogic; -- scan test enable
testrst : std_ulogic; -- scan test reset
scanen : std_ulogic; -- scan enable
testoen : std_ulogic; -- test output enable
end record;
-- APB slave outputs
type apb_slv_out_type is record
prdata : std_logic_vector(31 downto 0); -- read data bus
pirq : std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt bus
pconfig : apb_config_type; -- memory access reg.
pindex : integer range 0 to NAPBSLV -1; -- diag use only
end record;
-- array types
type apb_slv_out_vector is array (0 to NAPBSLV-1) of apb_slv_out_type;
-- support for plug&play configuration
constant AMBA_CONFIG_VER0 : std_logic_vector(1 downto 0) := "00";
subtype amba_vendor_type is integer range 0 to 16#ff#;
subtype amba_device_type is integer range 0 to 16#3ff#;
subtype amba_version_type is integer range 0 to 16#3f#;
subtype amba_cfgver_type is integer range 0 to 3;
subtype amba_irq_type is integer range 0 to NAHBIRQ-1;
subtype ahb_addr_type is integer range 0 to 16#fff#;
constant zx : std_logic_vector(31 downto 0) := (others => '0');
constant zxirq : std_logic_vector(NAHBIRQ-1 downto 0) := (others => '0');
constant zy : std_logic_vector(0 to 31) := (others => '0');
constant apb_none : apb_slv_out_type :=
(zx, zxirq(NAHBIRQ-1 downto 0), (others => zx), 0);
constant ahbm_none : ahb_mst_out_type := ( '0', '0', "00", zx,
'0', "000", "000", "0000", zx, zxirq(NAHBIRQ-1 downto 0), (others => zx), 0);
constant ahbs_none : ahb_slv_out_type := (
'1', "00", zx, zx(15 downto 0), '0', zxirq(NAHBIRQ-1 downto 0), (others => zx), 0);
constant ahbs_in_none : ahb_slv_in_type := (
zy(0 to NAHBSLV-1), zx, '0', "00", "000", "000", zx,
"0000", '1', "0000", '0', zy(0 to NAHBAMR-1), '0', zxirq(NAHBIRQ-1 downto 0),
'0', '0', '0', '0');
constant ahbsv_none : ahb_slv_out_vector := (others => ahbs_none);
function ahb_device_reg(vendor : amba_vendor_type; device : amba_device_type;
cfgver : amba_cfgver_type; version : amba_version_type;
interrupt : amba_irq_type)
return std_logic_vector;
function ahb_membar(memaddr : ahb_addr_type; prefetch, cache : std_ulogic;
addrmask : ahb_addr_type)
return std_logic_vector;
function ahb_membar_opt(memaddr : ahb_addr_type; prefetch, cache : std_ulogic;
addrmask : ahb_addr_type; enable : integer)
return std_logic_vector;
function ahb_iobar(memaddr : ahb_addr_type; addrmask : ahb_addr_type)
return std_logic_vector;
function apb_iobar(memaddr : ahb_addr_type; addrmask : ahb_addr_type)
return std_logic_vector;
function ahb_slv_dec_cache(haddr : std_logic_vector(31 downto 0);
ahbso : ahb_slv_out_vector; cached : integer)
return std_ulogic;
function ahb_slv_dec_pfetch(haddr : std_logic_vector(31 downto 0);
ahbso : ahb_slv_out_vector)
return std_ulogic;
component ahbctrl
generic (
defmast : integer := 0; -- default master
split : integer := 0; -- split support
rrobin : integer := 0; -- round-robin arbitration
timeout : integer range 0 to 255 := 0; -- HREADY timeout
ioaddr : ahb_addr_type := 16#fff#; -- I/O area MSB address
iomask : ahb_addr_type := 16#fff#; -- I/O area address mask
cfgaddr : ahb_addr_type := 16#ff0#; -- config area MSB address
cfgmask : ahb_addr_type := 16#ff0#; -- config area address mask
nahbm : integer range 1 to NAHBMST := NAHBMST; -- number of masters
nahbs : integer range 1 to NAHBSLV := NAHBSLV; -- number of slaves
ioen : integer range 0 to 15 := 1; -- enable I/O area
disirq : integer range 0 to 1 := 0; -- disable interrupt routing
fixbrst : integer range 0 to 1 := 0; -- support fix-length bursts
debug : integer range 0 to 2 := 2; -- print config to console
fpnpen : integer range 0 to 1 := 0; -- full PnP configuration decoding
icheck : integer range 0 to 1 := 1;
devid : integer := 0; -- unique device ID
enbusmon : integer range 0 to 1 := 0; --enable bus monitor
assertwarn : integer range 0 to 1 := 0; --enable assertions for warnings
asserterr : integer range 0 to 1 := 0; --enable assertions for errors
hmstdisable : integer := 0; --disable master checks
hslvdisable : integer := 0; --disable slave checks
arbdisable : integer := 0; --disable arbiter checks
mprio : integer := 0 --master with highest priority
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
msti : out ahb_mst_in_type;
msto : in ahb_mst_out_vector;
slvi : out ahb_slv_in_type;
slvo : in ahb_slv_out_vector;
testen : in std_ulogic := '0';
testrst : in std_ulogic := '1';
scanen : in std_ulogic := '0';
testoen : in std_ulogic := '1'
);
end component;
component apbctrl
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
nslaves : integer range 1 to NAPBSLV := NAPBSLV;
debug : integer range 0 to 2 := 2; -- print config to console
icheck : integer range 0 to 1 := 1;
enbusmon : integer range 0 to 1 := 0;
asserterr : integer range 0 to 1 := 0;
assertwarn : integer range 0 to 1 := 0;
pslvdisable : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbi : in ahb_slv_in_type;
ahbo : out ahb_slv_out_type;
apbi : out apb_slv_in_type;
apbo : in apb_slv_out_vector
);
end component;
component ahbctrl_mb
generic (
defmast : integer := 0; -- default master
split : integer := 0; -- split support
rrobin : integer := 0; -- round-robin arbitration
timeout : integer range 0 to 255 := 0; -- HREADY timeout
ioaddr : ahb_addr_type := 16#fff#; -- I/O area MSB address
iomask : ahb_addr_type := 16#fff#; -- I/O area address mask
cfgaddr : ahb_addr_type := 16#ff0#; -- config area MSB address
cfgmask : ahb_addr_type := 16#ff0#; -- config area address mask
nahbm : integer range 1 to NAHBMST := NAHBMST; -- number of masters
nahbs : integer range 1 to NAHBSLV := NAHBSLV; -- number of slaves
ioen : integer range 0 to 15 := 1; -- enable I/O area
disirq : integer range 0 to 1 := 0; -- disable interrupt routing
fixbrst : integer range 0 to 1 := 0; -- support fix-length bursts
debug : integer range 0 to 2 := 2; -- report cores to console
fpnpen : integer range 0 to 1 := 0; -- full PnP configuration decoding
busndx : integer range 0 to 3 := 0;
icheck : integer range 0 to 1 := 1;
devid : integer := 0 -- unique device ID
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
msti : out ahb_mst_in_type;
msto : in ahb_mst_out_bus_vector;
slvi : out ahb_slv_in_type;
slvo : in ahb_slv_out_bus_vector;
testen : in std_ulogic := '0';
testrst : in std_ulogic := '1';
scanen : in std_ulogic := '0';
testoen : in std_ulogic := '1'
);
end component;
component ahbdefmst
generic ( hindex : integer range 0 to NAHBMST-1 := 0);
port ( ahbmo : out ahb_mst_out_type);
end component;
-- pragma translate_off
component ahbmon is
generic(
asserterr : integer range 0 to 1 := 1;
assertwarn : integer range 0 to 1 := 1;
hmstdisable : integer := 0;
hslvdisable : integer := 0;
arbdisable : integer := 0;
nahbm : integer range 0 to NAHBMST := NAHBMST;
nahbs : integer range 0 to NAHBSLV := NAHBSLV
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : in ahb_mst_out_vector;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
err : out std_ulogic);
end component;
component apbmon is
generic(
asserterr : integer range 0 to 1 := 1;
assertwarn : integer range 0 to 1 := 1;
pslvdisable : integer := 0;
napb : integer range 0 to NAPBSLV := NAPBSLV
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : in apb_slv_out_vector;
err : out std_ulogic);
end component;
component ambamon is
generic(
asserterr : integer range 0 to 1 := 1;
assertwarn : integer range 0 to 1 := 1;
hmstdisable : integer := 0;
hslvdisable : integer := 0;
pslvdisable : integer := 0;
arbdisable : integer := 0;
nahbm : integer range 0 to NAHBMST := NAHBMST;
nahbs : integer range 0 to NAHBSLV := NAHBSLV;
napb : integer range 0 to NAPBSLV := NAPBSLV
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : in ahb_mst_out_vector;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
apbi : in apb_slv_in_type;
apbo : in apb_slv_out_vector;
err : out std_ulogic);
end component;
subtype vendor_description is string(1 to 24);
subtype device_description is string(1 to 31);
type device_table_type is array (0 to 1023) of device_description;
type vendor_library_type is record
vendorid : amba_vendor_type;
vendordesc : vendor_description;
device_table : device_table_type;
end record;
type device_array is array (0 to 255) of vendor_library_type;
-- pragma translate_on
end;
package body amba is
function ahb_device_reg(vendor : amba_vendor_type; device : amba_device_type;
cfgver : amba_cfgver_type; version : amba_version_type;
interrupt : amba_irq_type)
return std_logic_vector is
variable cfg : std_logic_vector(31 downto 0);
begin
case cfgver is
when 0 =>
cfg(31 downto 24) := std_logic_vector(to_unsigned(vendor, 8));
cfg(23 downto 12) := std_logic_vector(to_unsigned(device, 12));
cfg(11 downto 10) := std_logic_vector(to_unsigned(cfgver, 2));
cfg( 9 downto 5) := std_logic_vector(to_unsigned(version, 5));
cfg( 4 downto 0) := std_logic_vector(to_unsigned(interrupt, 5));
when others => cfg := (others => '0');
end case;
return(cfg);
end;
function ahb_membar(memaddr : ahb_addr_type; prefetch, cache : std_ulogic;
addrmask : ahb_addr_type)
return std_logic_vector is
variable cfg : std_logic_vector(31 downto 0);
begin
cfg(31 downto 20) := std_logic_vector(to_unsigned(memaddr, 12));
cfg(19 downto 16) := "00" & prefetch & cache;
cfg(15 downto 4) := std_logic_vector(to_unsigned(addrmask, 12));
cfg( 3 downto 0) := "0010";
return(cfg);
end;
function ahb_membar_opt(memaddr : ahb_addr_type; prefetch, cache : std_ulogic;
addrmask : ahb_addr_type; enable : integer)
return std_logic_vector is
variable cfg : std_logic_vector(31 downto 0);
begin
cfg := (others => '0');
if enable /= 0 then
return (ahb_membar(memaddr, prefetch, cache, addrmask));
else return(cfg); end if;
end;
function ahb_iobar(memaddr : ahb_addr_type; addrmask : ahb_addr_type)
return std_logic_vector is
variable cfg : std_logic_vector(31 downto 0);
begin
cfg(31 downto 20) := std_logic_vector(to_unsigned(memaddr, 12));
cfg(19 downto 16) := "0000";
cfg(15 downto 4) := std_logic_vector(to_unsigned(addrmask, 12));
cfg( 3 downto 0) := "0011";
return(cfg);
end;
function apb_iobar(memaddr : ahb_addr_type; addrmask : ahb_addr_type)
return std_logic_vector is
variable cfg : std_logic_vector(31 downto 0);
begin
cfg(31 downto 20) := std_logic_vector(to_unsigned(memaddr, 12));
cfg(19 downto 16) := "0000";
cfg(15 downto 4) := std_logic_vector(to_unsigned(addrmask, 12));
cfg( 3 downto 0) := "0001";
return(cfg);
end;
function ahb_slv_dec_cache(haddr : std_logic_vector(31 downto 0);
ahbso : ahb_slv_out_vector; cached : integer)
return std_ulogic is
variable hcache : std_ulogic;
variable ctbl : std_logic_vector(15 downto 0);
begin
hcache := '0'; ctbl := (others => '0');
if cached = 0 then
for i in 0 to NAHBSLV-1 loop
for j in NAHBAMR to NAHBCFG-1 loop
if (ahbso(i).hconfig(j)(16) = '1') and
(ahbso(i).hconfig(j)(15 downto 4) /= "000000000000")
then
if (haddr(31 downto 20) and ahbso(i).hconfig(j)(15 downto 4)) =
(ahbso(i).hconfig(j)(31 downto 20) and ahbso(i).hconfig(j)(15 downto 4)) then
hcache := '1';
end if;
end if;
end loop;
end loop;
else
ctbl := conv_std_logic_vector(cached, 16);
hcache := ctbl(conv_integer(haddr(31 downto 28)));
end if;
return(hcache);
end;
function ahb_slv_dec_pfetch(haddr : std_logic_vector(31 downto 0);
ahbso : ahb_slv_out_vector)
return std_ulogic is
variable pfetch : std_ulogic;
begin
pfetch := '0';
for i in 0 to NAHBSLV-1 loop
for j in NAHBAMR to NAHBCFG-1 loop
if ahbso(i).hconfig(j)(17) = '1' then
if (haddr(31 downto 20) and ahbso(i).hconfig(j)(15 downto 4)) =
(ahbso(i).hconfig(j)(31 downto 20) and ahbso(i).hconfig(j)(15 downto 4)) then
pfetch := '1';
end if;
end if;
end loop;
end loop;
return(pfetch);
end;
end;
| mit | 1844b804f5a9f460e212ea28a430f956 | 0.606093 | 3.518483 | false | true | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/techmap/maps/grlfpw_net.vhd | 2 | 15,984 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: grlfpw
-- File: grlfpw.vhd
-- Author: Edvin Catovic - Gaisler Research
-- Description: GRFPU LITE / GRLFPC wrapper
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.gencomp.all;
entity grlfpw_net is
generic (tech : integer := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer range 0 to 1 := 1;
disas : integer range 0 to 1 := 0;
pipe : integer range 0 to 2 := 0
);
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi_flush : in std_ulogic; -- pipeline flush
cpi_exack : in std_ulogic; -- FP exception acknowledge
cpi_a_rs1 : in std_logic_vector(4 downto 0);
cpi_d_pc : in std_logic_vector(31 downto 0);
cpi_d_inst : in std_logic_vector(31 downto 0);
cpi_d_cnt : in std_logic_vector(1 downto 0);
cpi_d_trap : in std_ulogic;
cpi_d_annul : in std_ulogic;
cpi_d_pv : in std_ulogic;
cpi_a_pc : in std_logic_vector(31 downto 0);
cpi_a_inst : in std_logic_vector(31 downto 0);
cpi_a_cnt : in std_logic_vector(1 downto 0);
cpi_a_trap : in std_ulogic;
cpi_a_annul : in std_ulogic;
cpi_a_pv : in std_ulogic;
cpi_e_pc : in std_logic_vector(31 downto 0);
cpi_e_inst : in std_logic_vector(31 downto 0);
cpi_e_cnt : in std_logic_vector(1 downto 0);
cpi_e_trap : in std_ulogic;
cpi_e_annul : in std_ulogic;
cpi_e_pv : in std_ulogic;
cpi_m_pc : in std_logic_vector(31 downto 0);
cpi_m_inst : in std_logic_vector(31 downto 0);
cpi_m_cnt : in std_logic_vector(1 downto 0);
cpi_m_trap : in std_ulogic;
cpi_m_annul : in std_ulogic;
cpi_m_pv : in std_ulogic;
cpi_x_pc : in std_logic_vector(31 downto 0);
cpi_x_inst : in std_logic_vector(31 downto 0);
cpi_x_cnt : in std_logic_vector(1 downto 0);
cpi_x_trap : in std_ulogic;
cpi_x_annul : in std_ulogic;
cpi_x_pv : in std_ulogic;
cpi_lddata : in std_logic_vector(31 downto 0); -- load data
cpi_dbg_enable : in std_ulogic;
cpi_dbg_write : in std_ulogic;
cpi_dbg_fsr : in std_ulogic; -- FSR access
cpi_dbg_addr : in std_logic_vector(4 downto 0);
cpi_dbg_data : in std_logic_vector(31 downto 0);
cpo_data : out std_logic_vector(31 downto 0); -- store data
cpo_exc : out std_logic; -- FP exception
cpo_cc : out std_logic_vector(1 downto 0); -- FP condition codes
cpo_ccv : out std_ulogic; -- FP condition codes valid
cpo_ldlock : out std_logic; -- FP pipeline hold
cpo_holdn : out std_ulogic;
cpo_dbg_data : out std_logic_vector(31 downto 0);
rfi1_rd1addr : out std_logic_vector(3 downto 0);
rfi1_rd2addr : out std_logic_vector(3 downto 0);
rfi1_wraddr : out std_logic_vector(3 downto 0);
rfi1_wrdata : out std_logic_vector(31 downto 0);
rfi1_ren1 : out std_ulogic;
rfi1_ren2 : out std_ulogic;
rfi1_wren : out std_ulogic;
rfi2_rd1addr : out std_logic_vector(3 downto 0);
rfi2_rd2addr : out std_logic_vector(3 downto 0);
rfi2_wraddr : out std_logic_vector(3 downto 0);
rfi2_wrdata : out std_logic_vector(31 downto 0);
rfi2_ren1 : out std_ulogic;
rfi2_ren2 : out std_ulogic;
rfi2_wren : out std_ulogic;
rfo1_data1 : in std_logic_vector(31 downto 0);
rfo1_data2 : in std_logic_vector(31 downto 0);
rfo2_data1 : in std_logic_vector(31 downto 0);
rfo2_data2 : in std_logic_vector(31 downto 0)
);
end;
architecture rtl of grlfpw_net is
component grlfpw_0_axcelerator is
port(
rst : in std_logic;
clk : in std_logic;
holdn : in std_logic;
cpi_flush : in std_logic;
cpi_exack : in std_logic;
cpi_a_rs1 : in std_logic_vector (4 downto 0);
cpi_d_pc : in std_logic_vector (31 downto 0);
cpi_d_inst : in std_logic_vector (31 downto 0);
cpi_d_cnt : in std_logic_vector (1 downto 0);
cpi_d_trap : in std_logic;
cpi_d_annul : in std_logic;
cpi_d_pv : in std_logic;
cpi_a_pc : in std_logic_vector (31 downto 0);
cpi_a_inst : in std_logic_vector (31 downto 0);
cpi_a_cnt : in std_logic_vector (1 downto 0);
cpi_a_trap : in std_logic;
cpi_a_annul : in std_logic;
cpi_a_pv : in std_logic;
cpi_e_pc : in std_logic_vector (31 downto 0);
cpi_e_inst : in std_logic_vector (31 downto 0);
cpi_e_cnt : in std_logic_vector (1 downto 0);
cpi_e_trap : in std_logic;
cpi_e_annul : in std_logic;
cpi_e_pv : in std_logic;
cpi_m_pc : in std_logic_vector (31 downto 0);
cpi_m_inst : in std_logic_vector (31 downto 0);
cpi_m_cnt : in std_logic_vector (1 downto 0);
cpi_m_trap : in std_logic;
cpi_m_annul : in std_logic;
cpi_m_pv : in std_logic;
cpi_x_pc : in std_logic_vector (31 downto 0);
cpi_x_inst : in std_logic_vector (31 downto 0);
cpi_x_cnt : in std_logic_vector (1 downto 0);
cpi_x_trap : in std_logic;
cpi_x_annul : in std_logic;
cpi_x_pv : in std_logic;
cpi_lddata : in std_logic_vector (31 downto 0);
cpi_dbg_enable : in std_logic;
cpi_dbg_write : in std_logic;
cpi_dbg_fsr : in std_logic;
cpi_dbg_addr : in std_logic_vector (4 downto 0);
cpi_dbg_data : in std_logic_vector (31 downto 0);
cpo_data : out std_logic_vector (31 downto 0);
cpo_exc : out std_logic;
cpo_cc : out std_logic_vector (1 downto 0);
cpo_ccv : out std_logic;
cpo_ldlock : out std_logic;
cpo_holdn : out std_logic;
cpo_dbg_data : out std_logic_vector (31 downto 0);
rfi1_rd1addr : out std_logic_vector (3 downto 0);
rfi1_rd2addr : out std_logic_vector (3 downto 0);
rfi1_wraddr : out std_logic_vector (3 downto 0);
rfi1_wrdata : out std_logic_vector (31 downto 0);
rfi1_ren1 : out std_logic;
rfi1_ren2 : out std_logic;
rfi1_wren : out std_logic;
rfi2_rd1addr : out std_logic_vector (3 downto 0);
rfi2_rd2addr : out std_logic_vector (3 downto 0);
rfi2_wraddr : out std_logic_vector (3 downto 0);
rfi2_wrdata : out std_logic_vector (31 downto 0);
rfi2_ren1 : out std_logic;
rfi2_ren2 : out std_logic;
rfi2_wren : out std_logic;
rfo1_data1 : in std_logic_vector (31 downto 0);
rfo1_data2 : in std_logic_vector (31 downto 0);
rfo2_data1 : in std_logic_vector (31 downto 0);
rfo2_data2 : in std_logic_vector (31 downto 0));
end component;
component grlfpw_0_unisim
port(
rst : in std_logic;
clk : in std_logic;
holdn : in std_logic;
cpi_flush : in std_logic;
cpi_exack : in std_logic;
cpi_a_rs1 : in std_logic_vector (4 downto 0);
cpi_d_pc : in std_logic_vector (31 downto 0);
cpi_d_inst : in std_logic_vector (31 downto 0);
cpi_d_cnt : in std_logic_vector (1 downto 0);
cpi_d_trap : in std_logic;
cpi_d_annul : in std_logic;
cpi_d_pv : in std_logic;
cpi_a_pc : in std_logic_vector (31 downto 0);
cpi_a_inst : in std_logic_vector (31 downto 0);
cpi_a_cnt : in std_logic_vector (1 downto 0);
cpi_a_trap : in std_logic;
cpi_a_annul : in std_logic;
cpi_a_pv : in std_logic;
cpi_e_pc : in std_logic_vector (31 downto 0);
cpi_e_inst : in std_logic_vector (31 downto 0);
cpi_e_cnt : in std_logic_vector (1 downto 0);
cpi_e_trap : in std_logic;
cpi_e_annul : in std_logic;
cpi_e_pv : in std_logic;
cpi_m_pc : in std_logic_vector (31 downto 0);
cpi_m_inst : in std_logic_vector (31 downto 0);
cpi_m_cnt : in std_logic_vector (1 downto 0);
cpi_m_trap : in std_logic;
cpi_m_annul : in std_logic;
cpi_m_pv : in std_logic;
cpi_x_pc : in std_logic_vector (31 downto 0);
cpi_x_inst : in std_logic_vector (31 downto 0);
cpi_x_cnt : in std_logic_vector (1 downto 0);
cpi_x_trap : in std_logic;
cpi_x_annul : in std_logic;
cpi_x_pv : in std_logic;
cpi_lddata : in std_logic_vector (31 downto 0);
cpi_dbg_enable : in std_logic;
cpi_dbg_write : in std_logic;
cpi_dbg_fsr : in std_logic;
cpi_dbg_addr : in std_logic_vector (4 downto 0);
cpi_dbg_data : in std_logic_vector (31 downto 0);
cpo_data : out std_logic_vector (31 downto 0);
cpo_exc : out std_logic;
cpo_cc : out std_logic_vector (1 downto 0);
cpo_ccv : out std_logic;
cpo_ldlock : out std_logic;
cpo_holdn : out std_logic;
cpo_dbg_data : out std_logic_vector (31 downto 0);
rfi1_rd1addr : out std_logic_vector (3 downto 0);
rfi1_rd2addr : out std_logic_vector (3 downto 0);
rfi1_wraddr : out std_logic_vector (3 downto 0);
rfi1_wrdata : out std_logic_vector (31 downto 0);
rfi1_ren1 : out std_logic;
rfi1_ren2 : out std_logic;
rfi1_wren : out std_logic;
rfi2_rd1addr : out std_logic_vector (3 downto 0);
rfi2_rd2addr : out std_logic_vector (3 downto 0);
rfi2_wraddr : out std_logic_vector (3 downto 0);
rfi2_wrdata : out std_logic_vector (31 downto 0);
rfi2_ren1 : out std_logic;
rfi2_ren2 : out std_logic;
rfi2_wren : out std_logic;
rfo1_data1 : in std_logic_vector (31 downto 0);
rfo1_data2 : in std_logic_vector (31 downto 0);
rfo2_data1 : in std_logic_vector (31 downto 0);
rfo2_data2 : in std_logic_vector (31 downto 0));
end component;
component grlfpw_2_stratixii
port(
rst : in std_logic;
clk : in std_logic;
holdn : in std_logic;
cpi_flush : in std_logic;
cpi_exack : in std_logic;
cpi_a_rs1 : in std_logic_vector (4 downto 0);
cpi_d_pc : in std_logic_vector (31 downto 0);
cpi_d_inst : in std_logic_vector (31 downto 0);
cpi_d_cnt : in std_logic_vector (1 downto 0);
cpi_d_trap : in std_logic;
cpi_d_annul : in std_logic;
cpi_d_pv : in std_logic;
cpi_a_pc : in std_logic_vector (31 downto 0);
cpi_a_inst : in std_logic_vector (31 downto 0);
cpi_a_cnt : in std_logic_vector (1 downto 0);
cpi_a_trap : in std_logic;
cpi_a_annul : in std_logic;
cpi_a_pv : in std_logic;
cpi_e_pc : in std_logic_vector (31 downto 0);
cpi_e_inst : in std_logic_vector (31 downto 0);
cpi_e_cnt : in std_logic_vector (1 downto 0);
cpi_e_trap : in std_logic;
cpi_e_annul : in std_logic;
cpi_e_pv : in std_logic;
cpi_m_pc : in std_logic_vector (31 downto 0);
cpi_m_inst : in std_logic_vector (31 downto 0);
cpi_m_cnt : in std_logic_vector (1 downto 0);
cpi_m_trap : in std_logic;
cpi_m_annul : in std_logic;
cpi_m_pv : in std_logic;
cpi_x_pc : in std_logic_vector (31 downto 0);
cpi_x_inst : in std_logic_vector (31 downto 0);
cpi_x_cnt : in std_logic_vector (1 downto 0);
cpi_x_trap : in std_logic;
cpi_x_annul : in std_logic;
cpi_x_pv : in std_logic;
cpi_lddata : in std_logic_vector (31 downto 0);
cpi_dbg_enable : in std_logic;
cpi_dbg_write : in std_logic;
cpi_dbg_fsr : in std_logic;
cpi_dbg_addr : in std_logic_vector (4 downto 0);
cpi_dbg_data : in std_logic_vector (31 downto 0);
cpo_data : out std_logic_vector (31 downto 0);
cpo_exc : out std_logic;
cpo_cc : out std_logic_vector (1 downto 0);
cpo_ccv : out std_logic;
cpo_ldlock : out std_logic;
cpo_holdn : out std_logic;
cpo_dbg_data : out std_logic_vector (31 downto 0);
rfi1_rd1addr : out std_logic_vector (3 downto 0);
rfi1_rd2addr : out std_logic_vector (3 downto 0);
rfi1_wraddr : out std_logic_vector (3 downto 0);
rfi1_wrdata : out std_logic_vector (31 downto 0);
rfi1_ren1 : out std_logic;
rfi1_ren2 : out std_logic;
rfi1_wren : out std_logic;
rfi2_rd1addr : out std_logic_vector (3 downto 0);
rfi2_rd2addr : out std_logic_vector (3 downto 0);
rfi2_wraddr : out std_logic_vector (3 downto 0);
rfi2_wrdata : out std_logic_vector (31 downto 0);
rfi2_ren1 : out std_logic;
rfi2_ren2 : out std_logic;
rfi2_wren : out std_logic;
rfo1_data1 : in std_logic_vector (31 downto 0);
rfo1_data2 : in std_logic_vector (31 downto 0);
rfo2_data1 : in std_logic_vector (31 downto 0);
rfo2_data2 : in std_logic_vector (31 downto 0));
end component;
begin
strtxii : if (tech = stratix2) or (tech = stratix3) or (tech = cyclone3) generate
grlfpw0 : grlfpw_2_stratixii
port map (rst, clk, holdn, cpi_flush, cpi_exack, cpi_a_rs1, cpi_d_pc,
cpi_d_inst, cpi_d_cnt, cpi_d_trap, cpi_d_annul, cpi_d_pv, cpi_a_pc,
cpi_a_inst, cpi_a_cnt, cpi_a_trap, cpi_a_annul, cpi_a_pv, cpi_e_pc,
cpi_e_inst, cpi_e_cnt, cpi_e_trap, cpi_e_annul, cpi_e_pv, cpi_m_pc,
cpi_m_inst, cpi_m_cnt, cpi_m_trap, cpi_m_annul, cpi_m_pv, cpi_x_pc,
cpi_x_inst, cpi_x_cnt, cpi_x_trap, cpi_x_annul, cpi_x_pv, cpi_lddata,
cpi_dbg_enable, cpi_dbg_write, cpi_dbg_fsr, cpi_dbg_addr, cpi_dbg_data,
cpo_data, cpo_exc, cpo_cc, cpo_ccv, cpo_ldlock, cpo_holdn, cpo_dbg_data,
rfi1_rd1addr, rfi1_rd2addr, rfi1_wraddr, rfi1_wrdata, rfi1_ren1,
rfi1_ren2, rfi1_wren, rfi2_rd1addr, rfi2_rd2addr, rfi2_wraddr,
rfi2_wrdata, rfi2_ren1, rfi2_ren2, rfi2_wren, rfo1_data1,
rfo1_data2, rfo2_data1, rfo2_data2 );
end generate;
ax : if tech = axcel generate
grlfpw0 : grlfpw_0_axcelerator
port map (rst, clk, holdn, cpi_flush, cpi_exack, cpi_a_rs1, cpi_d_pc,
cpi_d_inst, cpi_d_cnt, cpi_d_trap, cpi_d_annul, cpi_d_pv, cpi_a_pc,
cpi_a_inst, cpi_a_cnt, cpi_a_trap, cpi_a_annul, cpi_a_pv, cpi_e_pc,
cpi_e_inst, cpi_e_cnt, cpi_e_trap, cpi_e_annul, cpi_e_pv, cpi_m_pc,
cpi_m_inst, cpi_m_cnt, cpi_m_trap, cpi_m_annul, cpi_m_pv, cpi_x_pc,
cpi_x_inst, cpi_x_cnt, cpi_x_trap, cpi_x_annul, cpi_x_pv, cpi_lddata,
cpi_dbg_enable, cpi_dbg_write, cpi_dbg_fsr, cpi_dbg_addr, cpi_dbg_data,
cpo_data, cpo_exc, cpo_cc, cpo_ccv, cpo_ldlock, cpo_holdn, cpo_dbg_data,
rfi1_rd1addr, rfi1_rd2addr, rfi1_wraddr, rfi1_wrdata, rfi1_ren1,
rfi1_ren2, rfi1_wren, rfi2_rd1addr, rfi2_rd2addr, rfi2_wraddr,
rfi2_wrdata, rfi2_ren1, rfi2_ren2, rfi2_wren, rfo1_data1,
rfo1_data2, rfo2_data1, rfo2_data2 );
end generate;
uni : if (tech = virtex2) or (tech = virtex4) or (tech = virtex5) or
(tech = spartan3) or (tech = spartan3e)
generate
grlfpw0 : grlfpw_0_unisim
port map (rst, clk, holdn, cpi_flush, cpi_exack, cpi_a_rs1, cpi_d_pc,
cpi_d_inst, cpi_d_cnt, cpi_d_trap, cpi_d_annul, cpi_d_pv, cpi_a_pc,
cpi_a_inst, cpi_a_cnt, cpi_a_trap, cpi_a_annul, cpi_a_pv, cpi_e_pc,
cpi_e_inst, cpi_e_cnt, cpi_e_trap, cpi_e_annul, cpi_e_pv, cpi_m_pc,
cpi_m_inst, cpi_m_cnt, cpi_m_trap, cpi_m_annul, cpi_m_pv, cpi_x_pc,
cpi_x_inst, cpi_x_cnt, cpi_x_trap, cpi_x_annul, cpi_x_pv, cpi_lddata,
cpi_dbg_enable, cpi_dbg_write, cpi_dbg_fsr, cpi_dbg_addr, cpi_dbg_data,
cpo_data, cpo_exc, cpo_cc, cpo_ccv, cpo_ldlock, cpo_holdn, cpo_dbg_data,
rfi1_rd1addr, rfi1_rd2addr, rfi1_wraddr, rfi1_wrdata, rfi1_ren1,
rfi1_ren2, rfi1_wren, rfi2_rd1addr, rfi2_rd2addr, rfi2_wraddr,
rfi2_wrdata, rfi2_ren1, rfi2_ren2, rfi2_wren, rfo1_data1,
rfo1_data2, rfo2_data1, rfo2_data2 );
end generate;
end;
| mit | c58064477541e3a2bfc45e2358f01fc2 | 0.623749 | 2.728576 | false | false | false | false |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/gaisler/can/can.vhd | 2 | 5,489 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: can
-- File: can.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: CAN component declartions
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library techmap;
use techmap.gencomp.all;
package can is
component can_mod
generic (memtech : integer := DEFMEMTECH; syncrst : integer := 0;
ft : integer := 0);
port (
reset : in std_logic;
clk : in std_logic;
cs : in std_logic;
we : in std_logic;
addr : in std_logic_vector(7 downto 0);
data_in : in std_logic_vector(7 downto 0);
data_out: out std_logic_vector(7 downto 0);
irq : out std_logic;
rxi : in std_logic;
txo : out std_logic);
end component;
component can_oc
generic (
slvndx : integer := 0;
ioaddr : integer := 16#000#;
iomask : integer := 16#FF0#;
irq : integer := 0;
memtech : integer := DEFMEMTECH;
syncrst : integer := 0;
ft : integer := 0);
port (
resetn : in std_logic;
clk : in std_logic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
can_rxi : in std_logic;
can_txo : out std_logic
);
end component;
component can_mc
generic (
slvndx : integer := 0;
ioaddr : integer := 16#000#;
iomask : integer := 16#FF0#;
irq : integer := 0;
memtech : integer := DEFMEMTECH;
ncores : integer range 1 to 8 := 1;
sepirq : integer range 0 to 1 := 0;
syncrst : integer range 0 to 1 := 0;
ft : integer range 0 to 1 := 0);
port (
resetn : in std_logic;
clk : in std_logic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
can_rxi : in std_logic_vector(0 to 7);
can_txo : out std_logic_vector(0 to 7)
);
end component;
component can_rd
generic (
slvndx : integer := 0;
ioaddr : integer := 16#000#;
iomask : integer := 16#FF0#;
irq : integer := 0;
memtech : integer := DEFMEMTECH;
syncrst : integer := 0;
dmap : integer := 0);
port (
resetn : in std_logic;
clk : in std_logic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
can_rxi : in std_logic_vector(1 downto 0);
can_txo : out std_logic_vector(1 downto 0)
);
end component;
component canmux
port(
sel : in std_logic;
canrx : out std_logic;
cantx : in std_logic;
canrxv : in std_logic_vector(0 to 1);
cantxv : out std_logic_vector(0 to 1)
);
end component;
-----------------------------------------------------------------------------
-- interface type declarations for can controller
-----------------------------------------------------------------------------
type can_in_type is record
rx: std_logic_vector(1 downto 0); -- receive lines
end record;
type can_out_type is record
tx: std_logic_vector(1 downto 0); -- transmit lines
en: std_logic_vector(1 downto 0); -- transmit enables
end record;
-----------------------------------------------------------------------------
-- component declaration for grcan controller
-----------------------------------------------------------------------------
component grcan is
generic (
hindex: integer := 0;
pindex: integer := 0;
paddr: integer := 0;
pmask: integer := 16#ffc#;
pirq: integer := 1; -- index of first irq
singleirq: integer := 0; -- single irq output
txchannels: integer range 1 to 16 := 1; -- 1 to 16 channels
rxchannels: integer range 1 to 16 := 1; -- 1 to 16 channels
ptrwidth: integer range 4 to 16 := 16); -- 16 to 64k messages
-- 2k to 8M bits
port (
rstn: in std_ulogic;
clk: in std_ulogic;
apbi: in apb_slv_in_type;
apbo: out apb_slv_out_type;
ahbi: in ahb_mst_in_type;
ahbo: out ahb_mst_out_type;
cani: in can_in_type;
cano: out can_out_type);
end component;
end;
| mit | fb8a9c7d34cdb326f81da51624938c69 | 0.498816 | 4.050923 | false | false | false | false |
cafe-alpha/wascafe | v13/r07c_de10_20201014_abus4/wasca/synthesis/wasca_rst_controller_001.vhd | 6 | 9,079 | -- wasca_rst_controller_001.vhd
-- Generated using ACDS version 15.0 145
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity wasca_rst_controller_001 is
generic (
NUM_RESET_INPUTS : integer := 1;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 1;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := '0'; -- reset_in0.reset
clk : in std_logic := '0'; -- clk.clk
reset_out : out std_logic; -- reset_out.reset
reset_req : out std_logic; -- .reset_req
reset_in1 : in std_logic := '0';
reset_in10 : in std_logic := '0';
reset_in11 : in std_logic := '0';
reset_in12 : in std_logic := '0';
reset_in13 : in std_logic := '0';
reset_in14 : in std_logic := '0';
reset_in15 : in std_logic := '0';
reset_in2 : in std_logic := '0';
reset_in3 : in std_logic := '0';
reset_in4 : in std_logic := '0';
reset_in5 : in std_logic := '0';
reset_in6 : in std_logic := '0';
reset_in7 : in std_logic := '0';
reset_in8 : in std_logic := '0';
reset_in9 : in std_logic := '0';
reset_req_in0 : in std_logic := '0';
reset_req_in1 : in std_logic := '0';
reset_req_in10 : in std_logic := '0';
reset_req_in11 : in std_logic := '0';
reset_req_in12 : in std_logic := '0';
reset_req_in13 : in std_logic := '0';
reset_req_in14 : in std_logic := '0';
reset_req_in15 : in std_logic := '0';
reset_req_in2 : in std_logic := '0';
reset_req_in3 : in std_logic := '0';
reset_req_in4 : in std_logic := '0';
reset_req_in5 : in std_logic := '0';
reset_req_in6 : in std_logic := '0';
reset_req_in7 : in std_logic := '0';
reset_req_in8 : in std_logic := '0';
reset_req_in9 : in std_logic := '0'
);
end entity wasca_rst_controller_001;
architecture rtl of wasca_rst_controller_001 is
component altera_reset_controller is
generic (
NUM_RESET_INPUTS : integer := 6;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 0;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := 'X'; -- reset
clk : in std_logic := 'X'; -- clk
reset_out : out std_logic; -- reset
reset_req : out std_logic; -- reset_req
reset_req_in0 : in std_logic := 'X'; -- reset_req
reset_in1 : in std_logic := 'X'; -- reset
reset_req_in1 : in std_logic := 'X'; -- reset_req
reset_in2 : in std_logic := 'X'; -- reset
reset_req_in2 : in std_logic := 'X'; -- reset_req
reset_in3 : in std_logic := 'X'; -- reset
reset_req_in3 : in std_logic := 'X'; -- reset_req
reset_in4 : in std_logic := 'X'; -- reset
reset_req_in4 : in std_logic := 'X'; -- reset_req
reset_in5 : in std_logic := 'X'; -- reset
reset_req_in5 : in std_logic := 'X'; -- reset_req
reset_in6 : in std_logic := 'X'; -- reset
reset_req_in6 : in std_logic := 'X'; -- reset_req
reset_in7 : in std_logic := 'X'; -- reset
reset_req_in7 : in std_logic := 'X'; -- reset_req
reset_in8 : in std_logic := 'X'; -- reset
reset_req_in8 : in std_logic := 'X'; -- reset_req
reset_in9 : in std_logic := 'X'; -- reset
reset_req_in9 : in std_logic := 'X'; -- reset_req
reset_in10 : in std_logic := 'X'; -- reset
reset_req_in10 : in std_logic := 'X'; -- reset_req
reset_in11 : in std_logic := 'X'; -- reset
reset_req_in11 : in std_logic := 'X'; -- reset_req
reset_in12 : in std_logic := 'X'; -- reset
reset_req_in12 : in std_logic := 'X'; -- reset_req
reset_in13 : in std_logic := 'X'; -- reset
reset_req_in13 : in std_logic := 'X'; -- reset_req
reset_in14 : in std_logic := 'X'; -- reset
reset_req_in14 : in std_logic := 'X'; -- reset_req
reset_in15 : in std_logic := 'X'; -- reset
reset_req_in15 : in std_logic := 'X' -- reset_req
);
end component altera_reset_controller;
begin
rst_controller_001 : component altera_reset_controller
generic map (
NUM_RESET_INPUTS => NUM_RESET_INPUTS,
OUTPUT_RESET_SYNC_EDGES => OUTPUT_RESET_SYNC_EDGES,
SYNC_DEPTH => SYNC_DEPTH,
RESET_REQUEST_PRESENT => RESET_REQUEST_PRESENT,
RESET_REQ_WAIT_TIME => RESET_REQ_WAIT_TIME,
MIN_RST_ASSERTION_TIME => MIN_RST_ASSERTION_TIME,
RESET_REQ_EARLY_DSRT_TIME => RESET_REQ_EARLY_DSRT_TIME,
USE_RESET_REQUEST_IN0 => USE_RESET_REQUEST_IN0,
USE_RESET_REQUEST_IN1 => USE_RESET_REQUEST_IN1,
USE_RESET_REQUEST_IN2 => USE_RESET_REQUEST_IN2,
USE_RESET_REQUEST_IN3 => USE_RESET_REQUEST_IN3,
USE_RESET_REQUEST_IN4 => USE_RESET_REQUEST_IN4,
USE_RESET_REQUEST_IN5 => USE_RESET_REQUEST_IN5,
USE_RESET_REQUEST_IN6 => USE_RESET_REQUEST_IN6,
USE_RESET_REQUEST_IN7 => USE_RESET_REQUEST_IN7,
USE_RESET_REQUEST_IN8 => USE_RESET_REQUEST_IN8,
USE_RESET_REQUEST_IN9 => USE_RESET_REQUEST_IN9,
USE_RESET_REQUEST_IN10 => USE_RESET_REQUEST_IN10,
USE_RESET_REQUEST_IN11 => USE_RESET_REQUEST_IN11,
USE_RESET_REQUEST_IN12 => USE_RESET_REQUEST_IN12,
USE_RESET_REQUEST_IN13 => USE_RESET_REQUEST_IN13,
USE_RESET_REQUEST_IN14 => USE_RESET_REQUEST_IN14,
USE_RESET_REQUEST_IN15 => USE_RESET_REQUEST_IN15,
ADAPT_RESET_REQUEST => ADAPT_RESET_REQUEST
)
port map (
reset_in0 => reset_in0, -- reset_in0.reset
clk => clk, -- clk.clk
reset_out => reset_out, -- reset_out.reset
reset_req => reset_req, -- .reset_req
reset_req_in0 => '0', -- (terminated)
reset_in1 => '0', -- (terminated)
reset_req_in1 => '0', -- (terminated)
reset_in2 => '0', -- (terminated)
reset_req_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_req_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_req_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_req_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_req_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_req_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_req_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_req_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_req_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_req_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_req_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_req_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_req_in14 => '0', -- (terminated)
reset_in15 => '0', -- (terminated)
reset_req_in15 => '0' -- (terminated)
);
end architecture rtl; -- of wasca_rst_controller_001
| gpl-2.0 | ffac9440fba81e46021a3dd99606fb5a | 0.546536 | 2.728885 | false | false | false | false |
christakissgeo/Matrix-Vector-Multiplication | VHDL Files/project2.vhd | 1 | 11,178 | -- Project 2
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.Numeric_Std.all;
------------------------------------
entity project2 is
port (
clock : in std_logic;
reset : in std_logic;
valid : in std_logic;
hold_me : in std_logic;
data_in : in std_logic_vector (7 downto 0);
data_out : out std_logic_vector (18 downto 0);
hold_prev : out std_logic
);
end entity project2;
-------------------------------------
architecture project_2 of project2 is
-------------counter address generator----------------
component counter_address_generator is
port (
clock : in std_logic;
reset : in std_logic;
need_to_reset : in std_logic;
enable : in std_logic;
read_enable : in std_logic;
address : out std_logic_vector (7 downto 0)
);
end component;
-------------ramA----------------
component ramA is
port(
clock : in std_logic;
write_enable : in std_logic;
read_enable : in std_logic;
address : in std_logic_vector (2 downto 0);
datain : in std_logic_vector (7 downto 0);
dataout : out std_logic_vector (7 downto 0)
);
end component;
-------------ramR----------------
component ramR is
port(
clock : in std_logic;
write_enable : in std_logic;
read_enable : in std_logic;
address : in std_logic_vector (2 downto 0);
datain : in std_logic_vector (18 downto 0);
dataout : out std_logic_vector (18 downto 0)
);
end component;
-------------rom-----------------
component rom is
port (
clock : in std_logic;
address : in std_logic_vector (5 downto 0);
rom_enable : in std_logic;
data : out std_logic_vector (7 downto 0)
);
end component;
-------------fsm-----------------
component fsm
port (
clock : in std_logic;
reset : in std_logic;
ramA_address : in std_logic_vector (4 downto 0);
ramR_address : in std_logic_vector (7 downto 0);
rom_address : in std_logic_vector (7 downto 0);
hold_me : in std_logic;
ramR_readEnable : out std_logic;
ramA_writeEnable : out std_logic;
ramA_readEnable : out std_logic;
ramR_writeEnable : out std_logic;
rom_enable : out std_logic;
counterAddressGen_H_enable : out std_logic;
counterAddressGen_R_enable : out std_logic;
counterAddressGen_A_restart : out std_logic;
counterAddressGen_R_restart : out std_logic;
counterAddressGen_H_restart : out std_logic;
mac_clean : out std_logic;
reset_fsm : out std_logic;
hold_prev : out std_logic
);
end component fsm;
-------------mac-----------------
component mac is
port (
clock : in std_logic;
ai : in std_logic_vector(7 downto 0);
xi : in std_logic_vector(7 downto 0);
mac_clean : in std_logic;
data_out : out std_logic_vector (18 downto 0)
);
end component;
-------------------------------------
signal Ai : std_logic_vector (7 downto 0);
signal Hi : std_logic_vector (7 downto 0);
signal Ri : std_logic_vector (18 downto 0);
signal addressA : std_logic_vector (7 downto 0);
signal addressH : std_logic_vector (7 downto 0);
signal addressR : std_logic_vector (7 downto 0);
signal CAG_A_restart : std_logic;
signal CAG_H_restart : std_logic;
signal CAG_R_restart : std_logic;
signal ramA_write_enable : std_logic;
signal ramA_read_enable : std_logic;
signal ramR_write_enable : std_logic;
signal ramR_read_enable : std_logic;
signal romH_enable : std_logic;
signal clear_register : std_logic;
signal CAG_H_enable : std_logic;
signal CAG_R_enable : std_logic;
signal reset_fsm : std_logic;
begin
counterAddressGenA : counter_address_generator port map ( clock => clock,
reset => reset_fsm,
need_to_reset => CAG_A_restart,
enable => valid,
read_enable => ramA_read_enable,
address => addressA
);
-------------------------------
RAMA_UNIT : ramA port map ( clock => clock,
write_enable => ramA_write_enable,
read_enable => ramA_read_enable,
address => addressA(2 downto 0),
datain => data_in,
dataout => Ai
);
-------------------------------
counterAddressGenH : counter_address_generator port map ( clock => clock,
reset => reset_fsm,
need_to_reset => CAG_H_restart,
enable => CAG_H_enable,
read_enable => CAG_H_enable,
address => addressH
);
--------------------------------
ROMH : rom port map ( clock => clock,
address => addressH(5 downto 0),
rom_enable => romH_enable,
data => Hi
);
--------------------------------
MAC_UNIT : mac port map ( clock => clock,
ai => Ai,
xi => Hi,
mac_clean => clear_register,
data_out => Ri
);
---------------------------------
FSM_UNIT : fsm port map ( clock => clock,
reset => reset,
ramA_address => addressA(7 downto 3),
ramR_address => addressR,
rom_address => addressH,
hold_me => hold_me,
ramR_readEnable => ramR_read_enable,
ramA_writeEnable => ramA_write_enable,
ramA_readEnable => ramA_read_enable,
ramR_writeEnable => ramR_write_enable,
rom_enable => romH_enable,
counterAddressGen_H_enable => CAG_H_enable,
counterAddressGen_R_enable => CAG_R_enable,
counterAddressGen_A_restart => CAG_A_restart,
counterAddressGen_R_restart => CAG_R_restart,
counterAddressGen_H_restart => CAG_H_restart,
mac_clean => clear_register,
reset_fsm => reset_fsm,
hold_prev => hold_prev
);
---------------------------------
counterAddressGenR : counter_address_generator port map ( clock => clock,
reset => reset_fsm,
need_to_reset => CAG_R_restart,
enable => CAG_R_enable,
read_enable => ramR_read_enable,
address => addressR
);
----------------------------------
RAMR_UNIT : ramR port map ( clock => clock,
write_enable => ramR_write_enable,
read_enable => ramR_read_enable,
address => addressR(2 downto 0),
datain => Ri,
dataout => data_out
);
end architecture project_2;
| mit | efd0ad989778c3f17a5a2d52703625e5 | 0.311952 | 4.841057 | false | false | false | false |
michaelfivez/ascon_hardware_implementation | ascon12864_unrolled6/API_plus_CipherCore/CypherCore.vhd | 1 | 14,259 | -------------------------------------------------------------------------------
--! @project Unrolled (6) hardware implementation of Asconv1286
--! @author Michael Fivez
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is an hardware implementation made for my graduation thesis
--! at the KULeuven, in the COSIC department (year 2015-2016)
--! The thesis is titled 'Energy efficient hardware implementations of CAESAR submissions',
--! and can be found on the COSIC website (www.esat.kuleuven.be/cosic/publications)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
entity CipherCore is
generic (
G_NPUB_SIZE : integer := 128; --! Npub size (bits)
G_NSEC_SIZE : integer := 128; --! Nsec size (bits)
G_DBLK_SIZE : integer := 64; --! Data Block size (bits)
G_KEY_SIZE : integer := 128; --! Key size (bits)
G_RDKEY_SIZE : integer := 128; --! Round Key size (bits)
G_TAG_SIZE : integer := 128; --! Tag size (bits)
G_BS_BYTES : integer := 3; --! The number of bits required to hold block size expressed in bytes = log2_ceil(max(G_ABLK_SIZE,G_DBLK_SIZE)/8)
G_CTR_AD_SIZE : integer := 64; --! Maximum size for the counter that keeps track of authenticated data
G_CTR_D_SIZE : integer := 64 --! Maximum size for the counter that keeps track of data
);
port (
clk : in std_logic;
rst : in std_logic;
npub : in std_logic_vector(G_NPUB_SIZE -1 downto 0);
nsec : in std_logic_vector(G_NSEC_SIZE -1 downto 0);
key : in std_logic_vector(G_KEY_SIZE -1 downto 0);
rdkey : in std_logic_vector(G_RDKEY_SIZE -1 downto 0);
bdi : in std_logic_vector(G_DBLK_SIZE -1 downto 0);
exp_tag : in std_logic_vector(G_TAG_SIZE -1 downto 0);
len_a : in std_logic_vector(G_CTR_AD_SIZE -1 downto 0);
len_d : in std_logic_vector(G_CTR_D_SIZE -1 downto 0);
key_ready : in std_logic;
key_updated : out std_logic;
key_needs_update : in std_logic;
rdkey_ready : in std_logic;
rdkey_read : out std_logic;
npub_ready : in std_logic;
npub_read : out std_logic;
nsec_ready : in std_logic;
nsec_read : out std_logic;
bdi_ready : in std_logic;
bdi_proc : in std_logic;
bdi_ad : in std_logic;
bdi_nsec : in std_logic;
bdi_pad : in std_logic;
bdi_decrypt : in std_logic;
bdi_eot : in std_logic;
bdi_eoi : in std_logic;
bdi_read : out std_logic;
bdi_size : in std_logic_vector(G_BS_BYTES -1 downto 0);
bdi_valid_bytes : in std_logic_vector(G_DBLK_SIZE/8 -1 downto 0);
bdi_pad_loc : in std_logic_vector(G_DBLK_SIZE/8 -1 downto 0);
bdi_nodata : in std_logic;
exp_tag_ready : in std_logic;
bdo_ready : in std_logic;
bdo_write : out std_logic;
bdo : out std_logic_vector(G_DBLK_SIZE -1 downto 0);
bdo_size : out std_logic_vector(G_BS_BYTES+1 -1 downto 0);
bdo_nsec : out std_logic;
tag_ready : in std_logic;
tag_write : out std_logic;
tag : out std_logic_vector(G_TAG_SIZE -1 downto 0);
msg_auth_done : out std_logic;
msg_auth_valid : out std_logic
);
end entity CipherCore;
architecture structure of CipherCore is
-- Registers
signal keyreg,npubreg : std_logic_vector(127 downto 0);
-- Control signals AsconCore
signal AsconStart : std_logic;
signal AsconMode : std_logic_vector(3 downto 0);
signal AsconBusy : std_logic;
signal AsconSize : std_logic_vector(2 downto 0);
signal AsconInput : std_logic_vector(63 downto 0);
-- Internal Datapath signals
signal AsconOutput : std_logic_vector(127 downto 0);
begin
-- Morus_core entity
AsconCore : entity work.Ascon_StateUpdate port map(clk,rst,AsconStart,AsconMode,AsconSize,npubreg,keyreg,AsconInput,AsconBusy,AsconOutput);
----------------------------------------
------ DataPath for CipherCore ---------
----------------------------------------
datapath: process(AsconOutput,exp_tag,bdi,AsconInput) is
begin
-- Connect signals to the MorusCore
AsconInput <= bdi;
tag <= AsconOutput;
bdo <= AsconOutput(63 downto 0);
if AsconOutput = exp_tag then
msg_auth_valid <= '1';
else
msg_auth_valid <= '0';
end if;
end process datapath;
----------------------------------------
------ ControlPath for CipherCore ------
----------------------------------------
fsm: process(clk, rst) is
type state_type is (IDLE,INIT_1,INIT_2,PROCESSING,RUN_CIPHER_1,RUN_CIPHER_2,RUN_CIPHER_3,RUN_CIPHER_4,TAG_1,TAG_2);
variable CurrState : state_type := IDLE;
variable firstblock : std_logic;
variable lastblock : std_logic_vector(1 downto 0);
variable afterRunning : std_logic_vector(2 downto 0);
begin
if(clk = '1' and clk'event) then
if rst = '1' then -- synchornous reset
key_updated <= '0';
CurrState := IDLE;
firstblock := '0';
keyreg <= (others => '0');
npubreg <= (others => '0');
AsconMode <= (others => '0'); -- the mode is a register
afterRunning := (others => '0');
else
-- registers above in reset are used
-- Standard values of the control signals are zero
AsconStart <= '0';
bdi_read <= '0';
msg_auth_done <= '0';
bdo_write <= '0';
bdo_size <= "1000";
tag_write <= '0';
npub_read <= '0';
AsconSize <= (others => '0');
FsmLogic: case CurrState is
when IDLE =>
-- if key_needs_update = '1' then -- Key needs updating
-- if key_ready = '1' then
-- key_updated <= '1';
-- keyreg <= key;
-- CurrState := IDLE;
-- else
-- CurrState := IDLE;
-- end if;
if key_needs_update = '1' and key_ready = '1' then -- Key needs updating
key_updated <= '1';
keyreg <= key;
CurrState := IDLE;
elsif bdi_proc = '1' and npub_ready = '1' then -- start of processing
CurrState := INIT_1;
npubreg <= npub;
npub_read <= '1';
AsconMode <= "0010"; -- Mode: initialization
AsconStart <= '1';
else
CurrState := IDLE;
end if;
when INIT_1 =>
if AsconBusy = '1' then
CurrState := INIT_2; -- to INIT_2
else
AsconStart <= '1';
CurrState := INIT_1; -- to INIT_1
end if;
when INIT_2 =>
if AsconBusy = '0' then
CurrState := PROCESSING; -- to PROCESSING
firstblock := '1';
lastblock := "00";
else
CurrState := INIT_2; -- to INIT_2
end if;
-- EVEN SIMPLIFY THIS AFTER YOU SEE IF WORKS
when PROCESSING =>
if lastblock(1) = '1' then -- Generate the Tag
AsconMode <= "0001";
AsconStart <= '1';
CurrState := TAG_1;
elsif bdi_ready = '1' then
if firstblock = '1' and bdi_ad = '0' then -- No associative data (and return in function)
-- SEP_CONST
AsconMode <= "0011";
AsconStart <= '1';
CurrState := PROCESSING;
elsif bdi_ad = '1' then
if bdi_eot = '0' then
-- AD_PROCESS
AsconMode <= "0000";
AsconStart <= '1';
afterRunning := "000";
CurrState := RUN_CIPHER_1;
elsif bdi_eoi = '0' then
if bdi_size = "000" then
-- AD_PROCESS + case2 + SEP_CONST
AsconMode <= "0000";
AsconStart <= '1';
afterRunning := "001";
CurrState := RUN_CIPHER_1;
else
-- AD_PROCESS + SEP_CONST
AsconMode <= "0000";
AsconStart <= '1';
afterRunning := "010";
CurrState := RUN_CIPHER_1;
end if;
else
if bdi_size = "000" then
-- AD_PROCESS + case2 + SEP_CONST + case1
AsconMode <= "0000";
AsconStart <= '1';
afterRunning := "101";
CurrState := RUN_CIPHER_1;
else
-- AD_PROCESS + SEP_CONST + case1
AsconMode <= "0000";
AsconStart <= '1';
afterRunning := "110";
CurrState := RUN_CIPHER_1;
end if;
end if;
else
if bdi_decrypt = '0' then
if bdi_eot = '0' then
-- ENCRYPT
AsconMode <= "0110";
AsconStart <= '1';
afterRunning := "011";
CurrState := RUN_CIPHER_1;
elsif bdi_size = "000" then
-- ENCRYPT + case1
AsconMode <= "0110";
AsconStart <= '1';
afterRunning := "100";
CurrState := RUN_CIPHER_1;
else
-- LAST_BLOCK_ENCRYPT
bdi_read <= '1';
AsconMode <= "0111";
AsconStart <= '1';
afterRunning := "011";
CurrState := RUN_CIPHER_4;
end if;
else
if bdi_eot = '0' then
-- DECRYPT
AsconMode <= "0100";
AsconStart <= '1';
afterRunning := "011";
CurrState := RUN_CIPHER_1;
elsif bdi_size = "000" then
-- DECRYPT + case1
AsconMode <= "0100";
AsconStart <= '1';
afterRunning := "100";
CurrState := RUN_CIPHER_1;
else
-- LAST_BLOCK_DECRYPT
bdi_read <= '1';
AsconMode <= "0101";
AsconStart <= '1';
AsconSize <= bdi_size;
afterRunning := "011";
CurrState := RUN_CIPHER_4;
end if;
end if;
end if;
-- check if tag after (eoi, with special case when no associative data:
-- This is needed, because if no associative data, it will do it's thing and then still the message block is
-- left to be processed
if firstblock = '1' and bdi_ad = '0' then -- lastblock will be set next return in the function
lastblock := "00";
elsif bdi_eoi = '1' and bdi_decrypt = '0' then -- the one after is tag encryption
lastblock := "10";
elsif bdi_eoi = '1' then -- the one after is tag decryption
lastblock := "11";
end if;
-- not firstblock anymore :
firstblock := '0';
end if;
when RUN_CIPHER_1 =>
if AsconBusy = '1' then
CurrState := RUN_CIPHER_2;
bdi_read <= '1';
else
AsconStart <= '1';
CurrState := RUN_CIPHER_1;
end if;
when RUN_CIPHER_3 =>
if AsconBusy = '1' then
CurrState := RUN_CIPHER_2;
else
AsconStart <= '1';
CurrState := RUN_CIPHER_3;
end if;
when RUN_CIPHER_4 =>
if AsconBusy = '1' then
CurrState := RUN_CIPHER_2;
else
CurrState := RUN_CIPHER_4;
end if;
when RUN_CIPHER_2 =>
if AsconBusy = '0' then
-- logic here:
-- a simple variable is used for the cases where after the cipher something special has to be done:
-- activating authregister after associative data = 1
-- resetting of blocknumber after last associative data = 2 (so also do 1's job)
-- giving of output after encryption/decryption = 3 for encryption, 4 for decryption
-- activating checksum after decription of message = 4
-- special giving of output after padded encryption/decryption = 5 and 6 (determines output_sel), also wait with bdi_read
AfterRunLogic: case afterRunning is
when "000" => -- return to IDLE
CurrState := PROCESSING;
when "001" => -- case2 and sep_cont after
AsconMode <= "1001";
AsconStart <= '1';
CurrState := RUN_CIPHER_3;
afterRunning := "010";
when "010" => -- SEPCONSTANT and return to IDLE
AsconMode <= "0011";
AsconStart <= '1';
CurrState := PROCESSING;
when "011" => -- GIVE OUTPUT and return to IDLE
if bdo_ready = '1' then
bdo_write <= '1';
CurrState := PROCESSING;
else
CurrState := RUN_CIPHER_2;
end if;
when "100" => -- GIVE OUTPUT & case1 and return to IDLE
if bdo_ready = '1' then
bdo_write <= '1';
CurrState := PROCESSING;
AsconMode <= "1000";
AsconStart <= '1';
else
CurrState := RUN_CIPHER_2;
end if;
when "101" => -- case2 and case1 and sep_cont after
AsconMode <= "1001";
AsconStart <= '1';
CurrState := RUN_CIPHER_3;
afterRunning := "110";
when "110" => -- case1 and sep_cont after
AsconMode <= "1000";
AsconStart <= '1';
CurrState := RUN_CIPHER_2;
afterRunning := "010";
when others =>
end case AfterRunLogic;
else
CurrState := RUN_CIPHER_2;
end if;
when TAG_1 =>
if AsconBusy = '1' then
CurrState := TAG_2;
else
AsconStart <= '1';
CurrState := TAG_1;
end if;
when TAG_2 =>
if AsconBusy = '0' and lastblock(0) = '0' then -- Generate Tag
if tag_ready = '1' then
tag_write <= '1';
key_updated <= '0';
CurrState := IDLE;
else
CurrState := TAG_2;
end if;
elsif AsconBusy = '0' then -- Compare Tag
if exp_tag_ready = '1' then
msg_auth_done <= '1';
key_updated <= '0';
CurrState := IDLE;
else
CurrState := TAG_2;
end if;
else
CurrState := TAG_2;
end if;
when others =>
end case FsmLogic;
end if;
end if;
end process fsm;
end architecture structure;
| gpl-3.0 | 7ea8e6d01d6d9e888a5e659178f267c7 | 0.519461 | 3.387741 | false | false | false | false |
mgiacomini/mips-monocycle | ULA.vhd | 2 | 2,478 | -- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- Complete implementation of Patterson and Hennessy single cycle MIPS processor
-- Copyright (C) 2015 Darci Luiz Tomasi Junior
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, version 3.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- Engineer: Darci Luiz Tomasi Junior
-- E-mail: [email protected]
-- Date : 18/06/2015 - 20:12
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_SIGNED.ALL;
ENTITY ULA IS
PORT(
IN_A : IN STD_LOGIC_VECTOR (31 downto 0); --RS
IN_B : IN STD_LOGIC_VECTOR (31 downto 0); --RT
IN_C : IN STD_LOGIC_VECTOR (2 downto 0);
OUT_A : OUT STD_LOGIC_VECTOR (31 downto 0);
ZERO : OUT STD_LOGIC
);
END ULA;
ARCHITECTURE ARC_ULA OF ULA IS
SIGNAL DATA_RS : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL DATA_RT : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL ULA_CTRL : STD_LOGIC_VECTOR (2 downto 0);
SIGNAL DATA_ALU_RESULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
BEGIN
DATA_RS <= IN_A;
DATA_RT <= IN_B;
ULA_CTRL <= IN_C;
ZERO <= '1' WHEN (DATA_ALU_RESULT = X"00000000") else '0';
--PARA A INSTRUO SLT, PEGA O SINAL DO RESULTADO DA SUBTRAO E ADICIONA AO FINAL DO VETOR
OUT_A <= (X"0000000" & "000" & DATA_ALU_RESULT(31)) WHEN ULA_CTRL = "111" ELSE
DATA_ALU_RESULT;
PROCESS(ULA_CTRL, DATA_RS, DATA_RT)
BEGIN
CASE ULA_CTRL IS
WHEN "000" => DATA_ALU_RESULT <= DATA_RS AND DATA_RT; --AND
WHEN "001" => DATA_ALU_RESULT <= DATA_RS OR DATA_RT; --OR
WHEN "010" => DATA_ALU_RESULT <= DATA_RS + DATA_RT; --ADD
WHEN "110" => DATA_ALU_RESULT <= DATA_RS - DATA_RT; --SUB
WHEN "111" => DATA_ALU_RESULT <= DATA_RS - DATA_RT; --SLT
WHEN OTHERS => DATA_ALU_RESULT <= X"00000000";
END CASE;
END PROCESS;
END ARC_ULA;
| gpl-3.0 | b670ed202a5bd59823037adeaf1da4b8 | 0.609766 | 3.120907 | false | false | false | false |
franz/pocl | examples/accel/rtl/vhdl/fu_alu_comp.vhd | 2 | 19,381 | -- Module generated by TTA Codesign Environment
--
-- Generated on Sun Jul 7 16:19:19 2019
--
-- Function Unit: alu_comp
--
-- Operations:
-- add : 0
-- and : 1
-- eq : 2
-- gt : 3
-- gtu : 4
-- ior : 5
-- mul : 6
-- shl : 7
-- shr : 8
-- shru : 9
-- sub : 10
-- xor : 11
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
entity fu_alu_comp is
port (
clk : in std_logic;
rstx : in std_logic;
glock_in : in std_logic;
glockreq_out : out std_logic;
operation_in : in std_logic_vector(4-1 downto 0);
data_in1t_in : in std_logic_vector(32-1 downto 0);
load_in1t_in : in std_logic;
data_in2_in : in std_logic_vector(32-1 downto 0);
load_in2_in : in std_logic;
data_out1_out : out std_logic_vector(32-1 downto 0);
data_out2_out : out std_logic_vector(32-1 downto 0);
data_out3_out : out std_logic_vector(32-1 downto 0));
end entity fu_alu_comp;
architecture rtl of fu_alu_comp is
constant op_add_c : std_logic_vector(3 downto 0) := "0000";
constant op_and_c : std_logic_vector(3 downto 0) := "0001";
constant op_eq_c : std_logic_vector(3 downto 0) := "0010";
constant op_gt_c : std_logic_vector(3 downto 0) := "0011";
constant op_gtu_c : std_logic_vector(3 downto 0) := "0100";
constant op_ior_c : std_logic_vector(3 downto 0) := "0101";
constant op_mul_c : std_logic_vector(3 downto 0) := "0110";
constant op_shl_c : std_logic_vector(3 downto 0) := "0111";
constant op_shr_c : std_logic_vector(3 downto 0) := "1000";
constant op_shru_c : std_logic_vector(3 downto 0) := "1001";
constant op_sub_c : std_logic_vector(3 downto 0) := "1010";
constant op_xor_c : std_logic_vector(3 downto 0) := "1011";
signal operation : std_logic_vector(3 downto 0);
signal mul_dsp_2cycle_1_clk : std_logic;
signal mul_dsp_2cycle_1_rstx : std_logic;
signal mul_dsp_2cycle_1_glock_in : std_logic;
signal mul_dsp_2cycle_1_load_in : std_logic;
signal mul_dsp_2cycle_1_operand_a_in : std_logic_vector(31+1-1 downto 0);
signal mul_dsp_2cycle_1_operand_b_in : std_logic_vector(31+1-1 downto 0);
signal mul_dsp_2cycle_1_operand_c_in : std_logic_vector(31+1-1 downto 0);
signal mul_dsp_2cycle_1_result_out : std_logic_vector(31+1-1 downto 0);
signal generic_sru_1_clk : std_logic;
signal generic_sru_1_opa_i : std_logic_vector(31+1-1 downto 0);
signal generic_sru_1_opb_i : std_logic_vector(31+1-1 downto 0);
signal generic_sru_1_shift_dir_i : std_logic;
signal generic_sru_1_arith_shift_i : std_logic;
signal generic_sru_1_rnd_en_i : std_logic;
signal generic_sru_1_rnd_mode_i : std_logic;
signal generic_sru_1_data_o : std_logic_vector(31+1-1 downto 0);
signal add_op1 : std_logic_vector(31 downto 0);
signal add_op2 : std_logic_vector(31 downto 0);
signal add_op3 : std_logic_vector(31 downto 0);
signal and_op1 : std_logic_vector(31 downto 0);
signal and_op2 : std_logic_vector(31 downto 0);
signal and_op3 : std_logic_vector(31 downto 0);
signal eq_op1 : std_logic_vector(31 downto 0);
signal eq_op2 : std_logic_vector(31 downto 0);
signal eq_op3 : std_logic;
signal gt_op1 : std_logic_vector(31 downto 0);
signal gt_op2 : std_logic_vector(31 downto 0);
signal gt_op3 : std_logic;
signal gtu_op1 : std_logic_vector(31 downto 0);
signal gtu_op2 : std_logic_vector(31 downto 0);
signal gtu_op3 : std_logic;
signal ior_op1 : std_logic_vector(31 downto 0);
signal ior_op2 : std_logic_vector(31 downto 0);
signal ior_op3 : std_logic_vector(31 downto 0);
signal mul_op1 : std_logic_vector(31 downto 0);
signal mul_op2 : std_logic_vector(31 downto 0);
signal mul_op3 : std_logic_vector(31 downto 0);
signal shl_op1 : std_logic_vector(31 downto 0);
signal shl_op2 : std_logic_vector(4 downto 0);
signal shl_op3 : std_logic_vector(31 downto 0);
signal shr_op1 : std_logic_vector(31 downto 0);
signal shr_op2 : std_logic_vector(4 downto 0);
signal shr_op3 : std_logic_vector(31 downto 0);
signal shru_op1 : std_logic_vector(31 downto 0);
signal shru_op2 : std_logic_vector(4 downto 0);
signal shru_op3 : std_logic_vector(31 downto 0);
signal sub_op1 : std_logic_vector(31 downto 0);
signal sub_op2 : std_logic_vector(31 downto 0);
signal sub_op3 : std_logic_vector(31 downto 0);
signal xor_op1 : std_logic_vector(31 downto 0);
signal xor_op2 : std_logic_vector(31 downto 0);
signal xor_op3 : std_logic_vector(31 downto 0);
signal data_in1t : std_logic_vector(31 downto 0);
signal data_in2 : std_logic_vector(31 downto 0);
signal shadow_in2_r : std_logic_vector(31 downto 0);
signal operation_1_r : std_logic_vector(3 downto 0);
signal optrig_1_r : std_logic;
signal operation_2_r : std_logic_vector(3 downto 0);
signal optrig_2_r : std_logic;
signal data_in1t_1_r : std_logic_vector(31 downto 0);
signal data_in2_1_r : std_logic_vector(31 downto 0);
signal trigger_in1t_1_r : std_logic;
signal trigger_in2_1_r : std_logic;
signal data_in1t_2_r : std_logic_vector(31 downto 0);
signal data_in1t_3_r : std_logic_vector(31 downto 0);
signal trigger_in1t_2_r : std_logic;
signal data_in2_2_r : std_logic_vector(31 downto 0);
signal data_in2_3_r : std_logic_vector(31 downto 0);
signal trigger_in2_2_r : std_logic;
signal optrig_3_r : std_logic;
signal operation_3_r : std_logic_vector(3 downto 0);
signal data_out1_out_r : std_logic_vector(31 downto 0);
signal data_out2_out_r : std_logic_vector(31 downto 0);
signal data_out3_out_r : std_logic_vector(31 downto 0);
component mul_dsp48 is
generic (
latency_g : integer);
port (
clk : in std_logic;
rstx : in std_logic;
glock_in : in std_logic;
load_in : in std_logic;
operand_a_in : in std_logic_vector(31+1-1 downto 0);
operand_b_in : in std_logic_vector(31+1-1 downto 0);
operand_c_in : in std_logic_vector(31+1-1 downto 0);
result_out : out std_logic_vector(31+1-1 downto 0));
end component mul_dsp48;
component generic_sru is
port (
clk : in std_logic;
opa_i : in std_logic_vector(31+1-1 downto 0);
opb_i : in std_logic_vector(31+1-1 downto 0);
shift_dir_i : in std_logic;
arith_shift_i : in std_logic;
rnd_en_i : in std_logic;
rnd_mode_i : in std_logic;
data_o : out std_logic_vector(31+1-1 downto 0));
end component generic_sru;
begin
mul_dsp_2cycle_1 : mul_dsp48
generic map (
latency_g => 2)
port map (
clk => clk,
rstx => rstx,
glock_in => mul_dsp_2cycle_1_glock_in,
load_in => mul_dsp_2cycle_1_load_in,
operand_a_in => mul_dsp_2cycle_1_operand_a_in,
operand_b_in => mul_dsp_2cycle_1_operand_b_in,
operand_c_in => mul_dsp_2cycle_1_operand_c_in,
result_out => mul_dsp_2cycle_1_result_out);
generic_sru_1 : generic_sru
port map (
clk => clk,
opa_i => generic_sru_1_opa_i,
opb_i => generic_sru_1_opb_i,
shift_dir_i => generic_sru_1_shift_dir_i,
arith_shift_i => generic_sru_1_arith_shift_i,
rnd_en_i => generic_sru_1_rnd_en_i,
rnd_mode_i => generic_sru_1_rnd_mode_i,
data_o => generic_sru_1_data_o);
add_op1 <= data_in1t_1_r;
add_op2 <= data_in2_1_r;
and_op1 <= data_in2_1_r;
and_op2 <= data_in1t_1_r;
eq_op1 <= data_in1t_1_r;
eq_op2 <= data_in2_1_r;
gt_op1 <= data_in1t_1_r;
gt_op2 <= data_in2_1_r;
gtu_op1 <= data_in1t_1_r;
gtu_op2 <= data_in2_1_r;
ior_op1 <= data_in2_1_r;
ior_op2 <= data_in1t_1_r;
mul_op1 <= data_in2_1_r;
mul_op2 <= data_in1t_1_r;
shl_op1 <= data_in1t_2_r;
shl_op2 <= data_in2_2_r(4 downto 0);
shr_op1 <= data_in1t_2_r;
shr_op2 <= data_in2_2_r(4 downto 0);
shru_op1 <= data_in1t_2_r;
shru_op2 <= data_in2_2_r(4 downto 0);
sub_op1 <= data_in1t_1_r;
sub_op2 <= data_in2_1_r;
xor_op1 <= data_in2_1_r;
xor_op2 <= data_in1t_1_r;
data_in1t <= data_in1t_in;
shadow_in2_sp : process(clk, rstx)
begin
if rstx = '0' then
shadow_in2_r <= (others => '0');
elsif clk = '1' and clk'event then
if ((glock_in = '0') and (load_in2_in = '1')) then
shadow_in2_r <= data_in2_in;
end if;
end if;
end process shadow_in2_sp;
shadow_in2_cp : process(shadow_in2_r, data_in2_in, load_in2_in, load_in1t_in)
begin
if ((load_in1t_in = '1') and (load_in2_in = '1')) then
data_in2 <= data_in2_in;
else
data_in2 <= shadow_in2_r;
end if;
end process shadow_in2_cp;
operations_actual_cp : process(operation_2_r, shru_op2, shr_op2, generic_sru_1_data_o, shl_op2, eq_op2, eq_op1, ior_op2, and_op2, and_op1, add_op2, add_op1, gt_op2, xor_op2, glock_in, mul_op1, operation_1_r, mul_dsp_2cycle_1_result_out, mul_op2, xor_op1, gt_op1, gtu_op1, shru_op1, gtu_op2, ior_op1, sub_op2, sub_op1, shr_op1, shl_op1)
begin
add_op3 <= (others => '-');
and_op3 <= (others => '-');
eq_op3 <= '-';
gt_op3 <= '-';
gtu_op3 <= '-';
ior_op3 <= (others => '-');
mul_op3 <= (others => '-');
shl_op3 <= (others => '-');
shr_op3 <= (others => '-');
shru_op3 <= (others => '-');
sub_op3 <= (others => '-');
xor_op3 <= (others => '-');
add_op3 <= (others => '-');
and_op3 <= (others => '-');
eq_op3 <= '-';
eq_op3 <= '-';
gt_op3 <= '-';
gt_op3 <= '-';
gtu_op3 <= '-';
gtu_op3 <= '-';
ior_op3 <= (others => '-');
mul_dsp_2cycle_1_glock_in <= '-';
mul_op3 <= (others => '-');
mul_dsp_2cycle_1_load_in <= '-';
mul_dsp_2cycle_1_operand_a_in <= (others => '-');
mul_dsp_2cycle_1_operand_b_in <= (others => '-');
mul_dsp_2cycle_1_operand_c_in <= (others => '-');
mul_dsp_2cycle_1_load_in <= '-';
mul_dsp_2cycle_1_glock_in <= glock_in;
mul_op3 <= mul_dsp_2cycle_1_result_out;
mul_dsp_2cycle_1_load_in <= '0';
sub_op3 <= (others => '-');
xor_op3 <= (others => '-');
case operation_1_r is
when op_add_c =>
add_op3 <= std_logic_vector(signed(add_op1) + signed(add_op2));
when op_and_c =>
and_op3 <= and_op1 and and_op2;
when op_eq_c =>
if eq_op1 = eq_op2 then
eq_op3 <= '1';
else
eq_op3 <= '0';
end if;
when op_gt_c =>
if signed(gt_op1) > signed(gt_op2) then
gt_op3 <= '1';
else
gt_op3 <= '0';
end if;
when op_gtu_c =>
if unsigned(gtu_op1) > unsigned(gtu_op2) then
gtu_op3 <= '1';
else
gtu_op3 <= '0';
end if;
when op_ior_c =>
ior_op3 <= ior_op1 or ior_op2;
when op_mul_c =>
mul_dsp_2cycle_1_operand_a_in <= mul_op1;
mul_dsp_2cycle_1_operand_b_in <= mul_op2;
mul_dsp_2cycle_1_operand_c_in <= (others => '0');
mul_dsp_2cycle_1_load_in <= '1';
when op_sub_c =>
sub_op3 <= std_logic_vector(signed(sub_op1) - signed(sub_op2));
when op_xor_c =>
xor_op3 <= xor_op1 xor xor_op2;
when others =>
end case;
generic_sru_1_opa_i <= (others => '-');
generic_sru_1_opb_i <= (others => '-');
generic_sru_1_shift_dir_i <= '-';
generic_sru_1_arith_shift_i <= '-';
generic_sru_1_rnd_en_i <= '-';
generic_sru_1_rnd_mode_i <= '-';
shl_op3 <= (others => '-');
generic_sru_1_opa_i <= (others => '-');
generic_sru_1_opb_i <= (others => '-');
generic_sru_1_shift_dir_i <= '-';
generic_sru_1_arith_shift_i <= '-';
generic_sru_1_rnd_en_i <= '-';
generic_sru_1_rnd_mode_i <= '-';
shr_op3 <= (others => '-');
generic_sru_1_opa_i <= (others => '-');
generic_sru_1_opb_i <= (others => '-');
generic_sru_1_shift_dir_i <= '-';
generic_sru_1_arith_shift_i <= '-';
generic_sru_1_rnd_en_i <= '-';
generic_sru_1_rnd_mode_i <= '-';
shru_op3 <= (others => '-');
case operation_2_r is
when op_shl_c =>
generic_sru_1_opa_i <= shl_op1;
generic_sru_1_opb_i <= "000000000000000000000000000" & shl_op2;
generic_sru_1_shift_dir_i <= '1'; -- 0: right, 1: left (shift dreiction)
generic_sru_1_arith_shift_i <= '0'; -- 0: logical, 1: arithmetical (only for right shifts)
generic_sru_1_rnd_en_i <= '0';
generic_sru_1_rnd_mode_i <= '0';
shl_op3 <= generic_sru_1_data_o;
when op_shr_c =>
generic_sru_1_opa_i <= shr_op1;
generic_sru_1_opb_i <= "000000000000000000000000000" & shr_op2;
generic_sru_1_shift_dir_i <= '0'; -- 0: right, 1: left (shift dreiction)
generic_sru_1_arith_shift_i <= '1'; -- 0: logical, 1: arithmetical (only for right shifts)
generic_sru_1_rnd_en_i <= '0';
generic_sru_1_rnd_mode_i <= '0';
shr_op3 <= generic_sru_1_data_o;
when op_shru_c =>
generic_sru_1_opa_i <= shru_op1;
generic_sru_1_opb_i <= "000000000000000000000000000" & shru_op2;
generic_sru_1_shift_dir_i <= '0'; -- 0: right, 1: left (shift dreiction)
generic_sru_1_arith_shift_i <= '0'; -- 0: logical, 1: arithmetical (only for right shifts)
generic_sru_1_rnd_en_i <= '0';
generic_sru_1_rnd_mode_i <= '0';
shru_op3 <= generic_sru_1_data_o;
when others =>
end case;
end process operations_actual_cp;
operation <= operation_3_r;
operation_input_sp : process(clk, rstx)
begin
if rstx = '0' then
data_in2_1_r <= (others => '0');
data_in1t_1_r <= (others => '0');
operation_1_r <= (others => '0');
operation_3_r <= (others => '0');
optrig_3_r <= '0';
trigger_in2_2_r <= '0';
data_in1t_2_r <= (others => '0');
data_in2_3_r <= (others => '0');
trigger_in2_1_r <= '0';
trigger_in1t_2_r <= '0';
data_in2_2_r <= (others => '0');
operation_2_r <= (others => '0');
trigger_in1t_1_r <= '0';
data_in1t_3_r <= (others => '0');
optrig_1_r <= '0';
optrig_2_r <= '0';
elsif clk = '1' and clk'event then
if (glock_in = '0') then
trigger_in1t_1_r <= load_in1t_in;
trigger_in1t_2_r <= trigger_in1t_1_r;
trigger_in2_1_r <= load_in1t_in;
trigger_in2_2_r <= trigger_in2_1_r;
if (trigger_in1t_1_r = '1') then
data_in1t_2_r <= data_in1t_1_r;
end if;
if (trigger_in1t_2_r = '1') then
data_in1t_3_r <= data_in1t_2_r;
end if;
if (trigger_in2_1_r = '1') then
data_in2_2_r <= data_in2_1_r;
end if;
if (trigger_in2_2_r = '1') then
data_in2_3_r <= data_in2_2_r;
end if;
optrig_1_r <= '0';
optrig_2_r <= optrig_1_r;
if (optrig_1_r = '1') then
operation_2_r <= operation_1_r;
end if;
optrig_3_r <= optrig_2_r;
if (optrig_2_r = '1') then
operation_3_r <= operation_2_r;
end if;
end if;
if ((glock_in = '0') and (load_in1t_in = '1')) then
case operation_in is
when op_add_c =>
operation_1_r <= operation_in;
data_in1t_1_r <= data_in1t;
optrig_1_r <= '1';
data_in2_1_r <= data_in2;
optrig_1_r <= '1';
when op_and_c =>
operation_1_r <= operation_in;
data_in2_1_r <= data_in2;
optrig_1_r <= '1';
data_in1t_1_r <= data_in1t;
optrig_1_r <= '1';
when op_eq_c =>
operation_1_r <= operation_in;
data_in1t_1_r <= data_in1t;
optrig_1_r <= '1';
data_in2_1_r <= data_in2;
optrig_1_r <= '1';
when op_gt_c =>
operation_1_r <= operation_in;
data_in1t_1_r <= data_in1t;
optrig_1_r <= '1';
data_in2_1_r <= data_in2;
optrig_1_r <= '1';
when op_gtu_c =>
operation_1_r <= operation_in;
data_in1t_1_r <= data_in1t;
optrig_1_r <= '1';
data_in2_1_r <= data_in2;
optrig_1_r <= '1';
when op_ior_c =>
operation_1_r <= operation_in;
data_in2_1_r <= data_in2;
optrig_1_r <= '1';
data_in1t_1_r <= data_in1t;
optrig_1_r <= '1';
when op_mul_c =>
operation_1_r <= operation_in;
data_in2_1_r <= data_in2;
optrig_1_r <= '1';
data_in1t_1_r <= data_in1t;
optrig_1_r <= '1';
when op_shl_c =>
operation_1_r <= operation_in;
data_in1t_1_r <= data_in1t;
optrig_1_r <= '1';
data_in2_1_r <= data_in2;
optrig_1_r <= '1';
when op_shr_c =>
operation_1_r <= operation_in;
data_in1t_1_r <= data_in1t;
optrig_1_r <= '1';
data_in2_1_r <= data_in2;
optrig_1_r <= '1';
when op_shru_c =>
operation_1_r <= operation_in;
data_in1t_1_r <= data_in1t;
optrig_1_r <= '1';
data_in2_1_r <= data_in2;
optrig_1_r <= '1';
when op_sub_c =>
operation_1_r <= operation_in;
data_in1t_1_r <= data_in1t;
optrig_1_r <= '1';
data_in2_1_r <= data_in2;
optrig_1_r <= '1';
when op_xor_c =>
operation_1_r <= operation_in;
data_in2_1_r <= data_in2;
optrig_1_r <= '1';
data_in1t_1_r <= data_in1t;
optrig_1_r <= '1';
when others =>
end case;
end if;
end if;
end process operation_input_sp;
data_out1_out <= data_out1_out_r;
data_out2_out <= data_out2_out_r;
data_out3_out <= data_out3_out_r;
operations_output_sp : process(clk, rstx)
begin
if rstx = '0' then
data_out3_out_r <= (others => '0');
data_out2_out_r <= (others => '0');
data_out1_out_r <= (others => '0');
elsif clk = '1' and clk'event then
if ((glock_in = '0') and (optrig_1_r = '1')) then
case operation_1_r is
when op_add_c =>
data_out1_out_r <= add_op3;
when op_and_c =>
data_out1_out_r <= and_op3;
when op_eq_c =>
data_out1_out_r <= ((32-1 downto 1 => '0') & eq_op3);
when op_gt_c =>
data_out1_out_r <= ((32-1 downto 1 => '0') & gt_op3);
when op_gtu_c =>
data_out1_out_r <= ((32-1 downto 1 => '0') & gtu_op3);
when op_ior_c =>
data_out1_out_r <= ior_op3;
when op_sub_c =>
data_out1_out_r <= sub_op3;
when op_xor_c =>
data_out1_out_r <= xor_op3;
when others =>
end case;
end if;
if ((glock_in = '0') and (optrig_2_r = '1')) then
case operation_2_r is
when op_shl_c =>
data_out2_out_r <= shl_op3;
when op_shr_c =>
data_out2_out_r <= shr_op3;
when op_shru_c =>
data_out2_out_r <= shru_op3;
when others =>
end case;
end if;
if ((glock_in = '0') and (optrig_3_r = '1')) then
case operation_3_r is
when op_mul_c =>
data_out3_out_r <= mul_op3;
when others =>
end case;
end if;
end if;
end process operations_output_sp;
glockreq_out <= '0';
end architecture rtl;
| mit | 57ffc86a90dd0edbcc1eaa9dfdc8946e | 0.541613 | 2.69968 | false | false | false | false |
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