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GLADICOS/SPACEWIRESYSTEMC | rtl/RTL_VJ/SpaceWireCODECIPStateMachine.vhdl | 1 | 18,143 | ------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) <2013> <Shimafuji Electric Inc., Osaka University, JAXA>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity SpaceWireCODECIPStateMachine is
port (
Clock : in std_logic;
receiveClock : in std_logic;
reset : in std_logic;
after12p8us : in std_logic;
after6p4us : in std_logic;
linkStart : in std_logic;
linkDisable : in std_logic;
autoStart : in std_logic;
enableTransmit : out std_logic;
sendNulls : out std_logic;
sendFCTs : out std_logic;
sendNCharacter : out std_logic;
sendTimeCodes : out std_logic;
gotFCT : in std_logic;
gotTimeCode : in std_logic;
gotNCharacter : in std_logic;
gotNull : in std_logic;
gotBit : in std_logic;
creditError : in std_logic;
receiveError : in std_logic;
enableReceive : out std_logic;
characterSequenceError : out std_logic;
spaceWireResetOut : out std_logic;
FIFOAvailable : in std_logic;
timer6p4usReset : out std_logic;
timer12p8usStart : out std_logic;
linkUpTransitionSynchronize : out std_logic;
linkDownTransitionSynchronize : out std_logic;
linkUpEnable : out std_logic;
nullSynchronize : out std_logic;
fctSynchronize : out std_logic
);
end SpaceWireCODECIPStateMachine;
architecture Behavioral of SpaceWireCODECIPStateMachine is
component SpaceWireCODECIPSynchronizeOnePulse is
port (
clock : in std_logic;
asynchronousClock : in std_logic;
reset : in std_logic;
asynchronousIn : in std_logic;
synchronizedOut : out std_logic
);
end component;
type linkStateMachine is (
linkStateErrorReset,
linkStateErrorWait,
linkStateReady,
linkStateStarted,
linkStateConnecting,
linkStateRun
);
signal linkState : linkStateMachine;
signal gotNullSynchronize : std_logic;
signal gotFCTSynchronize : std_logic;
signal gotTimeCodeSynchronize : std_logic;
signal gotNCharacterSynchronize : std_logic;
signal iAsynchronousError : std_logic;
signal receiveErrorsSynchronize : std_logic;
signal iCharacterSequenceError : std_logic;
signal iEnableTransmit : std_logic;
signal iSendNulls : std_logic;
signal iSendFCTs : std_logic;
signal iSendNCharacter : std_logic;
signal iSendTimeCodes : std_logic;
signal iEnableReceive : std_logic;
signal iSpaceWireResetOut : std_logic;
signal iTimer6p4usReset : std_logic;
signal iTimer12p8usStart : std_logic;
--
signal iLinkUpTransition : std_logic;
signal iLinkDownTransition : std_logic;
signal iLinkUpEnable : std_logic;
signal creditSynchronize : std_logic;
begin
gotNullPulse : SpaceWireCODECIPSynchronizeOnePulse
port map (
clock => Clock,
asynchronousClock => receiveClock,
reset => reset,
asynchronousIn => gotNull,
synchronizedOut => gotNullSynchronize
);
gotFCTPulse : SpaceWireCODECIPSynchronizeOnePulse
port map (
clock => Clock,
asynchronousClock => receiveClock,
reset => reset,
asynchronousIn => gotFCT,
synchronizedOut => gotFCTSynchronize
);
gotTimeCodePulse : SpaceWireCODECIPSynchronizeOnePulse
port map (
clock => Clock,
asynchronousClock => receiveClock,
reset => reset,
asynchronousIn => gotTimeCode,
synchronizedOut => gotTimeCodeSynchronize
);
gotNCharacterPulse : SpaceWireCODECIPSynchronizeOnePulse
port map (
clock => Clock,
asynchronousClock => receiveClock,
reset => reset,
asynchronousIn => gotNCharacter,
synchronizedOut => gotNCharacterSynchronize
);
iAsynchronousError <= receiveErrorsSynchronize; --
errorPulse : SpaceWireCODECIPSynchronizeOnePulse
port map (
clock => Clock,
asynchronousClock => receiveClock,
reset => reset,
asynchronousIn => receiveError,
synchronizedOut => receiveErrorsSynchronize
);
characterSequenceError <= iCharacterSequenceError;
enableTransmit <= iEnableTransmit;
sendNulls <= iSendNulls;
sendFCTs <= iSendFCTs;
sendNCharacter <= iSendNCharacter;
sendTimeCodes <= iSendTimeCodes;
enableReceive <= iEnableReceive;
spaceWireResetOut <= iSpaceWireResetOut;
timer6p4usReset <= iTimer6p4usReset;
timer12p8usStart <= iTimer12p8usStart;
linkUpTransitionSynchronize <= iLinkUpTransition;
linkDownTransitionSynchronize <= iLinkDownTransition;
linkUpEnable <= iLinkUpEnable;
nullSynchronize <= gotNullSynchronize;
fctSynchronize <= gotFCTSynchronize;
----------------------------------------------------------------------
-- ECSS-E-ST-50-12C 8.4.6 StateMachine.
-- ECSS-E-ST-50-12C 8.5.3.7 RxErr.
-- ECSS-E-ST-50-12C 8.5.3.8 CreditError.
----------------------------------------------------------------------
process (Clock, reset, creditError)
begin
if (reset = '1' or creditError = '1') then
linkState <= linkStateErrorReset;
iSpaceWireResetOut <= '1';
iEnableReceive <= '0';
iEnableTransmit <= '0';
iSendNulls <= '0';
iSendFCTs <= '0';
iSendNCharacter <= '0';
iSendTimeCodes <= '0';
iCharacterSequenceError <= '0';
iTimer6p4usReset <= '1';
iTimer12p8usStart <= '0';
iLinkDownTransition <= '0';
iLinkUpTransition <= '0';
iLinkUpEnable <= '0';
elsif (Clock'event and Clock = '1') then
case linkState is
----------------------------------------------------------------------
-- ECSS-E-ST-50-12C 8.5.2.2 ErrorReset.
-- When the reset signal is de-asserted the ErrorReset state shall be left
-- unconditionally after a delay of 6,4 us (nominal) and the state machine
-- shall move to the ErrorWait state.
----------------------------------------------------------------------
when linkStateErrorReset =>
iLinkUpEnable <= '0';
if (iSendTimeCodes = '1') then
iLinkDownTransition <= '1';
else
iLinkDownTransition <= '0';
end if;
if (FIFOAvailable = '1') then
iTimer6p4usReset <= '0';
end if;
iSpaceWireResetOut <= '1';
iEnableReceive <= '0';
iEnableTransmit <= '0';
iSendNulls <= '0';
iSendFCTs <= '0';
iSendNCharacter <= '0';
iSendTimeCodes <= '0';
iCharacterSequenceError <= '0';
if (receiveErrorsSynchronize = '1') then
linkState <= linkStateErrorReset;
elsif (after6p4us = '1') then
iTimer12p8usStart <= '1';
linkState <= linkStateErrorWait;
end if;
----------------------------------------------------------------------
-- ECSS-E-ST-50-12C 8.5.2.3 ErrorWait.
-- The ErrorWait state shall be left unconditionally after a delay of 12,8 us
-- (nominal) and the state machine shall move to the Ready state.
-- If, while in the ErrorWait state, a disconnection error is detected
-- the state machine shall move back to the ErrorReset state.
----------------------------------------------------------------------
when linkStateErrorWait =>
iSpaceWireResetOut <= '0';
iTimer12p8usStart <= '0';
iEnableReceive <= '1';
if (receiveErrorsSynchronize = '1') then
iTimer6p4usReset <= '1';
linkState <= linkStateErrorReset;
elsif (gotTimeCodeSynchronize = '1' or gotFCTSynchronize = '1' or gotNCharacterSynchronize = '1') then
iCharacterSequenceError <= '1';
iTimer6p4usReset <= '1';
linkState <= linkStateErrorReset;
elsif (after12p8us = '1') then
linkState <= linkStateReady;
end if;
----------------------------------------------------------------------
-- ECSS-E-ST-50-12C 8.5.2.4 Ready.
-- The state machine shall wait in the Ready state until the [Link Enabled]
-- guard becomes true and then it shall move on into the Started state.
-- If, while in the Ready state, a disconnection error is detected, or if
-- after thegotNULL condition is set, a parity error or escape error occurs,
-- or any character other than a NULL is received, then the state machine
-- shall move to the ErrorReset state.
----------------------------------------------------------------------
when linkStateReady =>
iEnableReceive <= '1';
if (receiveErrorsSynchronize = '1') then
iTimer6p4usReset <= '1';
linkState <= linkStateErrorReset;
elsif (gotFCTSynchronize = '1' or gotNCharacterSynchronize = '1' or gotTimeCodeSynchronize = '1') then
iCharacterSequenceError <= '1';
iTimer6p4usReset <= '1';
linkState <= linkStateErrorReset;
elsif (autoStart = '1' and gotNullSynchronize = '1') then
iTimer12p8usStart <= '1';
linkState <= linkStateStarted;
elsif (linkStart = '1') then
iTimer12p8usStart <= '1';
linkState <= linkStateStarted;
end if;
----------------------------------------------------------------------
-- ECSS-E-ST-50-12C 8.5.2.5 Started.
-- The state machine shall move to the Connecting state if the gotNULL
-- condition is set.
-- If, while in the Started state, a disconnection error is detected, or if
-- after the gotNULL condition is set, a parity error or escape error occurs,
-- or any character other than a NULL is received, then the state machine shall
-- move to the ErrorReset state.
----------------------------------------------------------------------
when linkStateStarted =>
iEnableTransmit <= '1';
iEnableReceive <= '1';
iSendNulls <= '1';
iTimer12p8usStart <= '0';
if (receiveErrorsSynchronize = '1') then
iTimer6p4usReset <= '1';
linkState <= linkStateErrorReset;
elsif (linkDisable = '1') then
iTimer6p4usReset <= '1';
linkState <= linkStateErrorReset;
elsif (gotFCTSynchronize = '1' or gotNCharacterSynchronize = '1' or gotTimeCodeSynchronize = '1') then
iCharacterSequenceError <= '1';
iTimer6p4usReset <= '1';
linkState <= linkStateErrorReset;
elsif (after12p8us = '1') then
iTimer6p4usReset <= '1';
linkState <= linkStateErrorReset;
elsif (gotNullSynchronize = '1') then
iTimer12p8usStart <= '1';
linkState <= linkStateConnecting;
end if;
----------------------------------------------------------------------
-- ECSS-E-ST-50-12C 8.5.2.6 Connecting
-- If an FCT is received (gotFCT condition true) the state machine shall
-- move to the Run state.
-- If, while in the Connecting state, a disconnect error, parity error or
-- escape error is detected, or if any character other than NULL or
-- FCT is received, then the state machine shall move to the ErrorReset
-- state.
----------------------------------------------------------------------
when linkStateConnecting =>
iTimer12p8usStart <= '0';
iEnableTransmit <= '1';
iEnableReceive <= '1';
iSendFCTs <= '1';
if (receiveErrorsSynchronize = '1') then
iTimer6p4usReset <= '1';
linkState <= linkStateErrorReset;
elsif (linkDisable = '1') then
iTimer6p4usReset <= '1';
linkState <= linkStateErrorReset;
elsif (after12p8us = '1') then
iTimer6p4usReset <= '1';
linkState <= linkStateErrorReset;
elsif (gotNCharacterSynchronize = '1') then
iCharacterSequenceError <= '1';
iTimer6p4usReset <= '1';
linkState <= linkStateErrorReset;
elsif (gotFCTSynchronize = '1') then
linkState <= linkStateRun;
end if;
----------------------------------------------------------------------
-- ECSS-E-ST-50-12C 8.5.2.7 Run
-- In the Run state the receiver is enabled and the transmitter is
-- enabled to send Time-Codes, FCTs, N-Chars and NULLs.
-- If a disconnection error, parity error, ESC error occur, then the state machine
-- shall move to the ErrorResetState.
----------------------------------------------------------------------
when linkStateRun =>
iEnableTransmit <= '1';
iEnableReceive <= '1';
iSendNCharacter <= '1';
iSendTimeCodes <= '1';
iLinkUpEnable <= '1';
if (iSendTimeCodes = '0') then
iLinkUpTransition <= '1';
else
iLinkUpTransition <= '0';
end if;
if (linkDisable = '1' or receiveErrorsSynchronize = '1') then
iTimer6p4usReset <= '1';
linkState <= linkStateErrorReset;
end if;
when others => null;
end case;
end if;
end process;
end Behavioral;
| gpl-3.0 | 04d8d863330935c8ca773aaaad92c442 | 0.465634 | 5.128038 | false | false | false | false |
pwsoft/fpga_examples | rtl/ttl/ttl_7474.vhd | 1 | 3,338 | -- -----------------------------------------------------------------------
--
-- Syntiac VHDL support files.
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2018 by Peter Wendrich ([email protected])
-- http://www.syntiac.com
--
-- This source file is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- -----------------------------------------------------------------------
-- Dual positive-edge triggered D-type flip-flop with set and reset
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use work.ttl_pkg.all;
-- -----------------------------------------------------------------------
entity ttl_7474 is
generic (
latency : integer := 2
);
port (
emuclk : in std_logic;
p1 : in ttl_t; -- Async nReset FF1
p2 : in ttl_t; -- D FF1
p3 : in ttl_t; -- CP clock FF1
p4 : in ttl_t; -- Async nSet FF1
p5 : out ttl_t; -- Q FF1
p6 : out ttl_t; -- nQ FF1
p8 : out ttl_t; -- nQ FF2
p9 : out ttl_t; -- Q FF2
p10 : in ttl_t; -- Async nSet FF2
p11 : in ttl_t; -- CP clock FF2
p12 : in ttl_t; -- D FF2
p13 : in ttl_t -- Aync nReset FF2
);
end entity;
architecture rtl of ttl_7474 is
signal p5_loc : ttl_t := ZERO;
signal p6_loc : ttl_t := ONE;
signal p8_loc : ttl_t := ONE;
signal p9_loc : ttl_t := ZERO;
signal cp1 : std_logic;
signal cp1_dly : std_logic;
signal cp2 : std_logic;
signal cp2_dly : std_logic;
begin
p5_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p5_loc, q => p5);
p6_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p6_loc, q => p6);
p8_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p8_loc, q => p8);
p9_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p9_loc, q => p9);
cp1 <= ttl2std(p3);
cp2 <= ttl2std(p11);
process(emuclk)
begin
if rising_edge(emuclk) then
cp1_dly <= cp1;
if cp1 = '1' and cp1_dly = '0' then
p5_loc <= p2;
p6_loc <= not(p2);
end if;
if is_low(p4) then
p5_loc <= ONE;
p6_loc <= ZERO;
end if;
if is_low(p1) then
if not is_low(p4) then
p5_loc <= ZERO;
end if;
p6_loc <= ONE;
end if;
cp2_dly <= cp2;
if cp2 = '1' and cp2_dly = '0' then
p9_loc <= p12;
p8_loc <= not(p12);
end if;
if is_low(p10) then
p9_loc <= ONE;
p8_loc <= ZERO;
end if;
if is_low(p13) then
if not is_low(p10) then
p9_loc <= ZERO;
end if;
p8_loc <= ONE;
end if;
end if;
end process;
end architecture;
| lgpl-2.1 | ba246089226a3f45d297effbff98033e | 0.559017 | 2.953982 | false | false | false | false |
pwsoft/fpga_examples | rtl/ps2/io_ps2_keyboard.vhd | 1 | 7,217 | -- -----------------------------------------------------------------------
--
-- Syntiac VHDL support files.
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2010 by Peter Wendrich ([email protected])
-- http://www.syntiac.com
--
-- This source file is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- -----------------------------------------------------------------------
--
-- PS/2 keyboard driver
--
-- Uses: io_ps2_com
--
-- -----------------------------------------------------------------------
-- ledStatusSupport - Enables transmission of LED states. When disbled the
-- caps_lock, num_lock and scroll_lock inputs are unused.
-- This reduces the size of the design.
-- clockFilter - Filter length of the clock in number of system-clock ticks.
-- ticksPerUsec - System clock speed in Mhz. Used in timer calibration.
-- clk - System clock
-- ps2_clk_in - ps/2 clock input
-- ps2_dat_in - ps/2 data input
-- ps2_clk_out - ps/2 clock output
-- ps2_dat_out - ps/2 data output
-- The ps2_xxx_out outputs need a tristate driver.
-- When 0 the line should be driven low.
-- When 1 the line should be not be driven, but tri-stated (input)
-- caps_lock - Caps-lock state input (LED). It is transmitted when changed.
-- num_lock - Num-lock state input (LED). It is transmitted when changed.
-- scroll_lock - Scroll-lock state input (LED). It is transmitted when changed.
-- trigger - One clock high when a new scancode is received
-- scancode - Value of the last scancode received
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
-- -----------------------------------------------------------------------
entity io_ps2_keyboard is
generic (
-- Include code for LED status updates
ledStatusSupport : boolean := true;
-- Number of system-cycles used for PS/2 clock filtering
clockFilter : integer := 15;
-- Timer calibration
ticksPerUsec : integer := 33 -- 33 Mhz clock
);
port (
clk: in std_logic;
reset : in std_logic := '0';
-- PS/2 connector
ps2_clk_in: in std_logic;
ps2_dat_in: in std_logic;
ps2_clk_out: out std_logic;
ps2_dat_out: out std_logic;
-- LED status
caps_lock : in std_logic := '0';
num_lock : in std_logic := '0';
scroll_lock : in std_logic := '0';
-- Read scancode
trigger : out std_logic;
scancode : out unsigned(7 downto 0)
);
end entity;
-- -----------------------------------------------------------------------
architecture rtl of io_ps2_keyboard is
constant ticksPer100Usec : integer := ticksPerUsec * 100;
constant tickTimeout : integer := ticksPerUsec * 3500000;
type mainStateDef is (
stateInit, stateInitAA,
stateReset, stateReset2, stateResetAck,
stateWaitScanCode,
stateWaitAckED1, stateWaitAckED2);
signal masterState : mainStateDef := stateInit;
signal timeoutCount : integer range 0 to tickTimeout := 0;
signal resetCom : std_logic;
signal inIdle : std_logic;
signal recvTrigger : std_logic := '0';
signal sendTrigger : std_logic := '0';
signal sendBusy : std_logic;
signal sendByte : unsigned(7 downto 0);
signal recvByte : unsigned(10 downto 0);
-- Current LED states
signal caps_lock_state : std_logic := '0';
signal num_lock_state : std_logic := '0';
signal scroll_lock_state : std_logic := '0';
begin
myPs2Com : entity work.io_ps2_com
generic map (
clockFilter => clockFilter,
ticksPerUsec => ticksPerUsec
)
port map (
clk => clk,
reset => resetCom,
ps2_clk_in => ps2_clk_in,
ps2_dat_in => ps2_dat_in,
ps2_clk_out => ps2_clk_out,
ps2_dat_out => ps2_dat_out,
inIdle => inIdle,
sendTrigger => sendTrigger,
sendByte => sendByte,
sendBusy => sendBusy,
recvTrigger => recvTrigger,
recvByte => recvByte
);
--
-- Keyboard state machine
process(clk)
begin
if rising_edge(clk) then
resetCom <= '0';
trigger <= '0';
sendTrigger <= '0';
if timeoutCount /= 0 then
timeoutCount <= timeoutCount - 1;
else
masterState <= stateReset;
end if;
case masterState is
--
-- Reset sequence states
--
when stateReset =>
resetCom <= '1';
timeoutCount <= tickTimeout;
masterState <= stateReset2;
when stateReset2 =>
-- Reset keyboard
if sendBusy = '0' then
sendByte <= X"FF";
sendTrigger <= '1';
masterState <= stateResetAck;
end if;
when stateResetAck =>
if recvTrigger = '1' then
masterState <= stateInit;
end if;
--
-- Keyboard BAT handling states
-- (Basic assurance test)
--
when stateInit =>
-- Wait for keyboard to perform self-test
timeoutCount <= tickTimeout;
masterState <= stateInitAA;
-- Force update of LEDs after (re-)init
caps_lock_state <= not caps_lock;
num_lock_state <= not num_lock;
scroll_lock_state <= not scroll_lock;
when stateInitAA =>
-- Receive selftest result. It should be AAh.
if recvTrigger = '1' then
if recvByte(8 downto 1) = X"AA" then
masterState <= stateWaitScanCode;
end if;
end if;
--
-- Receive scan-codes
--
when stateWaitScanCode =>
if inIdle = '1' then
timeoutCount <= tickTimeout;
end if;
-- New scancode received
if recvTrigger = '1' then
trigger <= '1';
scancode <= recvByte(8 downto 1);
end if;
-- If LED status changes, send update to keyboard.
-- This is done by sending EDh byte followed by a data byte with the status of the LEDs.
if ledStatusSupport and (inIdle = '1') and
((num_lock /= num_lock_state) or (caps_lock /= caps_lock_state) or (scroll_lock /= scroll_lock_state)) then
sendByte <= X"ED";
sendTrigger <= '1';
masterState <= stateWaitAckED1;
end if;
--
-- Wait for ack on ED command
when stateWaitAckED1 =>
if recvTrigger = '1' then
if recvByte(8 downto 1) = X"FA" then
sendByte <= "00000" & caps_lock & num_lock & scroll_lock;
sendTrigger <= '1';
num_lock_state <= num_lock;
caps_lock_state <= caps_lock;
scroll_lock_state <= scroll_lock;
masterState <= stateWaitAckED2;
end if;
end if;
--
-- Wait for ack on ED data byte
when stateWaitAckED2 =>
if recvTrigger = '1' then
if recvByte(8 downto 1) = X"FA" then
masterState <= stateWaitScanCode;
end if;
end if;
end case;
if reset = '1' then
masterState <= stateReset;
end if;
end if;
end process;
end architecture;
| lgpl-2.1 | 00e4ae1b003f33e5c4848da793118fa0 | 0.601774 | 3.488159 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/techmap/maps/allmul.vhd | 1 | 3,200 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: allmul
-- File: allmul.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Multiplier components
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package allmul is
component mul_dw is
generic (
a_width : positive := 2; -- multiplier word width
b_width : positive := 2; -- multiplicand word width
num_stages : positive := 2; -- number of pipeline stages
stall_mode : natural range 0 to 1 := 1 -- '0': non-stallable; '1': stallable
);
port(a : in std_logic_vector(a_width-1 downto 0);
b : in std_logic_vector(b_width-1 downto 0);
clk : in std_logic;
en : in std_logic;
sign : in std_logic;
product : out std_logic_vector(a_width+b_width-1 downto 0));
end component;
component gen_mult_pipe
generic (
a_width : positive; -- multiplier word width
b_width : positive; -- multiplicand word width
num_stages : positive := 2; -- number of pipeline stages
stall_mode : natural range 0 to 1 := 1); -- '0': non-stallable; '1': stallable
port (
clk : in std_logic; -- register clock
en : in std_logic; -- register enable
tc : in std_logic; -- '0' : unsigned, '1' : signed
a : in std_logic_vector(a_width-1 downto 0); -- multiplier
b : in std_logic_vector(b_width-1 downto 0); -- multiplicand
product : out std_logic_vector(a_width+b_width-1 downto 0)); -- product
end component;
component axcel_mul_33x33_signed
generic (
pipe: Integer := 0);
port (
a: in Std_Logic_Vector(32 downto 0);
b: in Std_Logic_Vector(32 downto 0);
en: in Std_Logic;
clk: in Std_Logic;
p: out Std_Logic_Vector(65 downto 0));
end component;
end;
| gpl-3.0 | 1a7106bdf5c449151cb4fd445a01199f | 0.542813 | 4.113111 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-altera-de2-ep2c35/testbench.vhd | 1 | 8,607 | ------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
use work.debug.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
library grlib;
use grlib.stdlib.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20; -- system clock period
romdepth : integer := 22 -- rom address depth (flash 4 MB)
-- sramwidth : integer := 32; -- ram data width (8/16/32)
-- sramdepth : integer := 20; -- ram address depth
-- srambanks : integer := 2 -- number of ram banks
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal clk : std_logic := '0';
signal Rst : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal address : std_logic_vector(21 downto 0);
signal data : std_logic_vector(31 downto 24);
signal romsn : std_logic;
signal oen : std_logic;
signal writen : std_logic;
signal dsuen, dsutx, dsurx, dsubre, dsuact : std_logic;
signal dsurst : std_logic;
signal error : std_logic;
signal gpio_0 : std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
signal gpio_1 : std_logic_vector(CFG_GRGPIO2_WIDTH-1 downto 0);
signal sdcke : std_logic;
signal sdcsn : std_logic;
signal sdwen : std_logic; -- write en
signal sdrasn : std_logic; -- row addr stb
signal sdcasn : std_logic; -- col addr stb
signal dram_ldqm : std_logic;
signal dram_udqm : std_logic;
signal sdclk : std_logic;
signal sw : std_logic_vector(0 to 2);
signal ps2_clk : std_logic;
signal ps2_dat : std_logic;
signal vga_clk : std_ulogic;
signal vga_blank : std_ulogic;
signal vga_sync : std_ulogic;
signal vga_hs : std_ulogic;
signal vga_vs : std_ulogic;
signal vga_r : std_logic_vector(9 downto 0);
signal vga_g : std_logic_vector(9 downto 0);
signal vga_b : std_logic_vector(9 downto 0);
constant lresp : boolean := false;
signal sa : std_logic_vector(13 downto 0);
signal sd : std_logic_vector(15 downto 0);
begin
clk <= not clk after ct * 1 ns; --50 MHz clk
rst <= dsurst; --reset
dsuen <= '1';
dsubre <= '1'; -- inverted on the board
sw(0) <= '1';
gpio_0(CFG_GRGPIO_WIDTH-1 downto 0) <= (others => 'H');
gpio_1(CFG_GRGPIO2_WIDTH-1 downto 0) <= (others => 'H');
d3 : entity work.leon3mp
generic map ( fabtech, memtech, padtech, clktech, disas, dbguart, pclow )
port map (rst, clk, error, address(21 downto 0), data,
sa(11 downto 0), sa(12), sa(13), sd, sdclk, sdcke, sdcsn, sdwen,
sdrasn, sdcasn, dram_ldqm, dram_udqm, dsutx, dsurx, dsubre, dsuact,
oen, writen, open, romsn, open, open, open, open, open, open, gpio_0, gpio_1,
ps2_clk, ps2_dat, vga_clk, vga_blank, vga_sync, vga_hs, vga_vs, vga_r,
vga_g, vga_b, sw);
sd1 : if (CFG_SDCTRL = 1) generate
u1: entity work.mt48lc16m16a2 generic map (addr_bits => 12, col_bits => 8, index => 1024, fname => sdramfile)
PORT MAP(
Dq => sd(15 downto 0), Addr => sa(11 downto 0),
Ba => sa(13 downto 12), Clk => sdclk, Cke => sdcke,
Cs_n => sdcsn, Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm(0) => dram_ldqm, Dqm(1) => dram_udqm );
end generate;
prom0 : sram generic map (index => 6, abits => romdepth, fname => promfile)
port map (address(romdepth-1 downto 0), data(31 downto 24), romsn,
writen, oen);
error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 2500 ns;
if to_x01(error) = '1' then wait on error; end if;
assert (to_x01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
data <= buskeep(data) after 5 ns;
sd <= buskeep(sd) after 5 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_logic; signal dsutx : out std_logic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0'; --reset low
wait for 500 ns;
dsurst <= '1'; --reset high
wait; --evig w8
wait for 5000 ns;
txc(dsutx, 16#55#, txp);
-- txc(dsutx, 16#c0#, txp); --control byte
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp); --adress
-- txa(dsutx, 16#00#, 16#00#, 16#02#, 16#ae#, txp); --write data
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#24#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#03#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#fc#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#6f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#11#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#04#, txp);
txa(dsutx, 16#00#, 16#02#, 16#20#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#02#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#43#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end ;
| gpl-3.0 | 1d2fbf56218eec24c5e8e99764ae3065 | 0.579877 | 3.08053 | false | false | false | false |
freecores/cryptopan_core | rtl/round_unit.vhd | 1 | 4,632 | --
-- This file is part of the Crypto-PAn core.
--
-- Copyright (c) 2007 The University of Waikato, Hamilton, New Zealand.
-- Authors: Anthony Blake ([email protected])
--
-- All rights reserved.
--
-- This code has been developed by the University of Waikato WAND
-- research group. For further information please see http://www.wand.net.nz/
--
-- This source file is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This source is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with libtrace; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.cryptopan.all;
entity round_unit is
generic (
do_mixcolumns : boolean := true);
port (
bytes_in : in s_vector;
bytes_out : out s_vector;
in_en : in std_logic;
out_en : out std_logic;
load_en : in std_logic;
load_data : in std_logic_vector(31 downto 0);
load_clk : in std_logic;
clk : in std_logic;
reset : in std_logic
);
end round_unit;
architecture rtl of round_unit is
component mixcolumns
port (
bytes_in : in s_vector;
bytes_out : out s_vector;
in_en : in std_logic;
out_en : out std_logic;
clk : in std_logic;
reset : in std_logic);
end component;
component subbytesshiftrows
port (
bytes_in : in s_vector;
bytes_out : out s_vector;
in_en : in std_logic;
out_en : out std_logic;
clk : in std_logic;
reset : in std_logic);
end component;
signal sbsr_out : s_vector;
signal mix_out : s_vector;
signal round_key : s_vector;
signal round_out : s_vector;
signal load_counter : std_logic_vector(1 downto 0);
signal sbsr_out_en : std_logic;
signal mix_out_en : std_logic;
begin
bytes_out <= round_out;
LOAD_LOGIC : process (load_clk, reset)
begin
if reset = '1' then
for i in 0 to 15 loop
round_key(i) <= (others => '0');
end loop;
load_counter <= "00";
elsif load_clk'event and load_clk = '1' then
if load_en = '1' then
if load_counter = "00" then
round_key(12) <= load_data(7 downto 0);
round_key(8) <= load_data(15 downto 8);
round_key(4) <= load_data(23 downto 16);
round_key(0) <= load_data(31 downto 24);
elsif load_counter = "01" then
round_key(13) <= load_data(7 downto 0);
round_key(9) <= load_data(15 downto 8);
round_key(5) <= load_data(23 downto 16);
round_key(1) <= load_data(31 downto 24);
elsif load_counter = "10" then
round_key(14) <= load_data(7 downto 0);
round_key(10) <= load_data(15 downto 8);
round_key(6) <= load_data(23 downto 16);
round_key(2) <= load_data(31 downto 24);
elsif load_counter = "11" then
round_key(15) <= load_data(7 downto 0);
round_key(11) <= load_data(15 downto 8);
round_key(7) <= load_data(23 downto 16);
round_key(3) <= load_data(31 downto 24);
end if;
load_counter <= load_counter + 1;
else
load_counter <= "00";
end if;
end if;
end process LOAD_LOGIC;
SBSR0 : subbytesshiftrows
port map (
bytes_in => bytes_in,
bytes_out => sbsr_out,
in_en => in_en,
out_en => sbsr_out_en,
clk => clk,
reset => reset);
out_en <= mix_out_en;
GENMIXCOLUMNS : if do_mixcolumns = true generate
MIX0 : mixcolumns
port map (
bytes_in => sbsr_out,
bytes_out => mix_out,
in_en => sbsr_out_en,
out_en => mix_out_en,
clk => clk,
reset => reset);
end generate GENMIXCOLUMNS;
NO_GENMIXCOLUMNS : if do_mixcolumns = false generate
mix_out <= sbsr_out;
mix_out_en <= sbsr_out_en;
end generate NO_GENMIXCOLUMNS;
ROUND_XOR : for i in 0 to 15 generate
round_out(i) <= round_key(i) xor mix_out(i);
end generate ROUND_XOR;
end rtl;
| gpl-2.0 | eb6342257868444ec061216cf22fc7f6 | 0.589378 | 3.313305 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/work/debug/cpu_disas.vhd | 1 | 4,287 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: cpu_disas
-- File: cpu_disas.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: Module for disassembly
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- pragma translate_off
library grlib;
use grlib.stdlib.all;
use grlib.sparc.all;
use std.textio.all;
use grlib.sparc_disas.all;
-- pragma translate_on
entity cpu_disas is
port (
clk : in std_ulogic;
rstn : in std_ulogic;
dummy : out std_ulogic;
inst : in std_logic_vector(31 downto 0);
pc : in std_logic_vector(31 downto 2);
result: in std_logic_vector(31 downto 0);
index : in std_logic_vector(3 downto 0);
wreg : in std_ulogic;
annul : in std_ulogic;
holdn : in std_ulogic;
pv : in std_ulogic;
trap : in std_ulogic);
end;
architecture behav of cpu_disas is
begin
dummy <= '1';
-- pragma translate_off
trc : process(clk)
variable valid : boolean;
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable fpins, fpld : boolean;
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
fpins := (op = FMT3) and ((op3 = FPOP1) or (op3 = FPOP2));
fpld := (op = LDST) and ((op3 = LDF) or (op3 = LDDF) or (op3 = LDFSR));
valid := (((not annul) and pv) = '1') and (not ((fpins or fpld) and (trap = '0')));
valid := valid and (holdn = '1');
if rising_edge(clk) and (rstn = '1') then
print_insn (conv_integer(index), pc(31 downto 2) & "00", inst,
result, valid, trap = '1', wreg = '1'
);
end if;
end process;
-- pragma translate_on
end;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- pragma translate_off
library grlib;
use grlib.stdlib.all;
use grlib.sparc.all;
use std.textio.all;
use grlib.sparc_disas.all;
-- pragma translate_on
entity gaisler_cpu_disas is
port (
clk : in std_ulogic;
rstn : in std_ulogic;
dummy : out std_ulogic;
inst : in std_logic_vector(31 downto 0);
pc : in std_logic_vector(31 downto 2);
result: in std_logic_vector(31 downto 0);
index : in std_logic_vector(3 downto 0);
wreg : in std_ulogic;
annul : in std_ulogic;
holdn : in std_ulogic;
pv : in std_ulogic;
trap : in std_ulogic);
end;
architecture behav of gaisler_cpu_disas is
begin
dummy <= '1';
-- pragma translate_off
trc : process(clk)
variable valid : boolean;
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable fpins, fpld : boolean;
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
fpins := (op = FMT3) and ((op3 = FPOP1) or (op3 = FPOP2));
fpld := (op = LDST) and ((op3 = LDF) or (op3 = LDDF) or (op3 = LDFSR));
valid := (((not annul) and pv) = '1') and (not ((fpins or fpld) and (trap = '0')));
valid := valid and (holdn = '1');
if rising_edge(clk) and (rstn = '1') then
print_insn (conv_integer(index), pc(31 downto 2) & "00", inst,
result, valid, trap = '1', wreg = '1'
);
end if;
end process;
-- pragma translate_on
end;
| gpl-3.0 | 74f98b7c80506b3d5021dd88e1b218da | 0.603919 | 3.476886 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-asic/testbench.vhd | 1 | 14,784 | ------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2013 Aeroflex Gaisler AB
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
use work.debug.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
use gaisler.jtagtst.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20; -- system clock period
romwidth : integer := 32; -- rom data width (8/32)
romdepth : integer := 20; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 20; -- ram address depth
srambanks : integer := 2; -- number of ram banks
testen : integer := 0;
scanen : integer := 0;
testrst : integer := 0;
testoen : integer := 0
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal clk : std_logic := '0';
signal Rst : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal address : std_logic_vector(27 downto 0);
signal data : std_logic_vector(31 downto 0);
signal cb : std_logic_vector(15 downto 0);
signal ramsn : std_logic_vector(4 downto 0);
signal ramoen : std_logic_vector(4 downto 0);
signal rwen : std_logic_vector(3 downto 0);
signal rwenx : std_logic_vector(3 downto 0);
signal romsn : std_logic_vector(1 downto 0);
signal iosn : std_ulogic;
signal oen : std_ulogic;
signal read : std_ulogic;
signal writen : std_ulogic;
signal brdyn : std_ulogic;
signal bexcn : std_ulogic;
signal wdogn : std_logic;
signal dsuen, dsutx, dsurx, dsubre, dsuact : std_ulogic;
signal dsurst : std_ulogic;
signal test : std_ulogic;
signal error : std_logic;
signal gpio : std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal clk2 : std_ulogic := '1';
signal sdcke : std_logic_vector ( 1 downto 0); -- clk en
signal sdcsn : std_logic_vector ( 1 downto 0); -- chip sel
signal sdwen : std_ulogic; -- write en
signal sdrasn : std_ulogic; -- row addr stb
signal sdcasn : std_ulogic; -- col addr stb
signal sddqm : std_logic_vector ( 3 downto 0); -- data i/o mask
signal sdclk : std_ulogic := '0';
signal lock : std_ulogic;
signal txd1, rxd1 : std_ulogic;
signal txd2, rxd2 : std_ulogic;
signal roen, roout, nandout, promedac : std_ulogic;
constant lresp : boolean := false;
signal gnd : std_logic_vector(3 downto 0);
signal clksel : std_logic_vector(1 downto 0);
signal prom32 : std_ulogic;
signal spw_clksel : std_logic_vector(1 downto 0);
signal spw_clk : std_ulogic := '0';
signal spw_rxd : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_rxs : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_txd : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_txs : std_logic_vector(0 to CFG_SPW_NUM-1);
signal i2c_scl : std_ulogic;
signal i2c_sda : std_ulogic;
signal spi_miso : std_logic;
signal spi_mosi : std_logic;
signal spi_sck : std_logic;
signal spi_slvsel : std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0);
signal trst,tck,tms,tdi,tdo: std_ulogic;
signal gtx_clk : std_ulogic := '0';
signal erx_clk : std_ulogic;
signal erxd : std_logic_vector(7 downto 0);
signal erx_dv : std_ulogic;
signal etx_clk : std_ulogic;
signal etxd : std_logic_vector(7 downto 0);
signal etx_en : std_ulogic;
signal etx_er : std_ulogic;
signal erx_er : std_ulogic;
signal erx_col : std_ulogic;
signal erx_crs : std_ulogic;
signal emdint : std_ulogic;
signal emdio : std_logic;
signal emdc : std_ulogic;
begin
-- clock and reset
test <= '0' when testen = 0 else '1';
rxd1 <= '1' when (testen = 1) and (testoen = 1) else
'0' when (testen = 1) and (testoen = 0) else txd1;
dsuen <= '1' when (testen = 1) and (testrst = 1) else
'0' when (testen = 1) and (testrst = 0) else '1', '0' after 1500 ns;
dsubre <= '1' when (testen = 1) and (scanen = 1) else
-- '0' when (testen = 1) and (scanen = 0) else '1';
'0' when (testen = 1) and (scanen = 0) else '0';
clksel <= "00";
spw_clksel <= "00";
error <= 'H';
gnd <= "0000";
clk <= not clk after ct * 1 ns;
spw_clk <= not spw_clk after ct * 1 ns;
gtx_clk <= not gtx_clk after 8 ns;
rst <= dsurst;
bexcn <= '1'; wdogn <= 'H';
-- gpio(2 downto 0) <= "HHL";
gpio(CFG_GRGPIO_WIDTH-1 downto 0) <= (others => 'Z');
-- gpio(15 downto 11) <= "HLLHH"; --19
-- gpio(10 downto 8) <= "HLL"; --4
-- gpio(7 downto 0) <= (others => 'L');
cb(15 downto 8) <= "HHHHHHHH";
spw_rxd <= spw_txd; spw_rxs <= spw_txs;
roen <= '0';
promedac <= '0';
prom32 <= '1';
rxd2 <= txd2;
d3 : entity work.leon3mp
generic map (
fabtech, memtech, padtech, clktech, disas, dbguart, pclow )
port map (
rst, clksel, clk, lock, error, wdogn, address, data,
cb(7 downto 0), sdclk, sdcsn, sdwen,
sdrasn, sdcasn, sddqm, dsutx, dsurx, dsuen, dsubre, dsuact,
txd1, rxd1, txd2, rxd2,
ramsn, ramoen, rwen, oen, writen, read, iosn, romsn, brdyn, bexcn, gpio,
i2c_scl, i2c_sda,
spi_miso, spi_mosi, spi_sck, spi_slvsel,
prom32,
spw_clksel, spw_clk, spw_rxd, spw_rxs, spw_txd, spw_txs,
gtx_clk, erx_clk, erxd, erx_dv, etx_clk, etxd, etx_en, etx_er, erx_er, erx_col, erx_crs, emdint, emdio, emdc ,
test, trst, tck, tms, tdi, tdo);
-- optional sdram
sdcke <= "11";
sd0 : if (CFG_MCTRL_SDEN = 1) and (CFG_MCTRL_SEPBUS = 0) generate
u0: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => data(31 downto 16), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u1: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => data(15 downto 0), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
u2: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => data(31 downto 16), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u3: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => data(15 downto 0), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
end generate;
prom0 : for i in 0 to (romwidth/8)-1 generate
sr0 : sram generic map (index => i, abits => romdepth, fname => promfile)
port map (address(romdepth+1 downto 2), data(31-i*8 downto 24-i*8), romsn(0),
rwen(i), oen);
end generate;
sram0 : for i in 0 to (sramwidth/8)-1 generate
sr0 : sram generic map (index => i, abits => sramdepth, fname => sramfile)
port map (address(sramdepth+1 downto 2), data(31-i*8 downto 24-i*8), ramsn(0),
rwen(0), ramoen(0));
end generate;
phy0 : if (CFG_GRETH = 1) generate
emdio <= 'H';
emdint <= '0';
p0: phy
generic map (
address => 7,
extended_regs => 1,
aneg => 1,
base100_t4 => 1,
base100_x_fd => 1,
base100_x_hd => 1,
fd_10 => 1,
hd_10 => 1,
base100_t2_fd => 1,
base100_t2_hd => 1,
base1000_x_fd => 0,
base1000_x_hd => 0,
base1000_t_fd => 0,
base1000_t_hd => 0,
rmii => 0,
rgmii => 0
)
port map(rst, emdio, etx_clk, erx_clk, erxd,
erx_dv, erx_er, erx_col, erx_crs, etxd,
etx_en, etx_er, emdc, gtx_clk);
end generate;
spimem0: if (CFG_SPICTRL_ENABLE = 1) generate
s0 : spi_flash generic map (ftype => 4, debug => 0, fname => promfile,
readcmd => CFG_SPIMCTRL_READCMD,
dummybyte => CFG_SPIMCTRL_DUMMYBYTE,
dualoutput => 0)
port map (spi_sck, spi_mosi, spi_miso, spi_slvsel(0));
end generate spimem0;
iuerr : process
begin
wait for 2500 ns;
if to_x01(error) = '1' then wait on error; end if;
assert (to_x01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
bst0: process
begin
trst <= '0';
tck <= '0';
tms <= '1';
tdi <= '0';
wait for 2500 ns;
trst <= '1';
if to_x01(error) = '1' then wait on error; end if;
if CFG_BOUNDSCAN_EN /= 0 then bscantest(tdo,tck,tms,tdi,10); end if;
assert false
report "*** IU in error mode, simulation halted ***"
severity failure ;
wait;
end process;
test0 : grtestmod
port map ( rst, clk, error, address(21 downto 2), data,
iosn, oen, writen, brdyn);
data <= buskeep(data) after 5 ns;
cb <= buskeep(cb) after 5 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := clkperiod*16 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
wait for 500 ns;
dsurst <= '1';
wait; -- remove to run the DSU UART
wait for 5010 ns;
txc(dsutx, 16#55#, txp); -- sync uart
txc(dsutx, 16#55#, txp); -- sync uart
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#02#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#24#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#03#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#fc#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
wait;
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#40#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0e#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#30#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#40#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#06#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#30#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#40#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#02#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#30#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#43#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end ;
| gpl-3.0 | d042ea04d0bb0dbe3031239056dcdeec | 0.560674 | 3.12426 | false | true | false | false |
EliasLuiz/TCC | Leon3/lib/techmap/maps/toutpad_tm.vhd | 1 | 3,537 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: toutpad_tm, toutpad_tmvv
-- File: toutpad_tm.vhd
-- Author: Magnus Hjorth - Aeroflex Gaisler
-- Description: Tech map for IO pad with built-in test mux
------------------------------------------------------------------------------
-- This is implemented recursively by passing in the test signals via the cfgi
-- input for technologies that support it, and muxing manually for others.
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
use techmap.allpads.all;
entity toutpad_tm is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12;
oepol : integer := 0);
port (pad : out std_ulogic; i, en : in std_ulogic;
test: in std_ulogic; ti,ten : in std_ulogic;
cfgi: in std_logic_vector(19 downto 0) := "00000000000000000000");
end;
architecture rtl of toutpad_tm is
signal mi,men: std_ulogic;
signal mcfgi: std_logic_vector(19 downto 0);
begin
notm: if has_tm_pads(tech)=0 generate
mi <= ti when test='1' else i;
men <= ten when test='1' else en;
mcfgi <= cfgi;
end generate;
hastm: if has_tm_pads(tech)/=0 generate
mi <= i;
men <= en;
mcfgi <= cfgi(19 downto 3) & ti & ten & test;
end generate;
p: toutpad
generic map (tech => tech, level => level, slew => slew,
voltage => voltage, strength => strength,
oepol => oepol)
port map (pad => pad, i => mi, en => men, cfgi => mcfgi);
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity toutpad_tmvv is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (
pad : out std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_logic_vector(width-1 downto 0);
test: in std_ulogic;
ti : in std_logic_vector(width-1 downto 0);
ten : in std_logic_vector(width-1 downto 0);
cfgi: in std_logic_vector(19 downto 0) := "00000000000000000000");
end;
architecture rtl of toutpad_tmvv is
begin
v : for j in width-1 downto 0 generate
x0 : toutpad_tm generic map (tech, level, slew, voltage, strength, oepol)
port map (pad(j), i(j), en(j), test, ti(j), ten(j), cfgi);
end generate;
end;
| gpl-3.0 | 62a1e1cad1eec6f50f41e851ded2ad7e | 0.614362 | 3.790997 | false | true | false | false |
GLADICOS/SPACEWIRESYSTEMC | rtl/RTL_SL/streamtest.vhd | 2 | 16,127 | --
-- Test application for spwstream.
--
-- This entity implements one spwstream instance with SpaceWire signals
-- routed to external ports. The SpaceWire port is assumed to be looped back
-- to itself externally, either directly (tx pins wired to rx pins) or
-- through a remote SpaceWire device which is programmed to echo anything
-- it receives.
--
-- This entity submits a series of test patterns to the transmit side of
-- spwstream. At the same time it monitors the receive side of spwstream
-- and verifies that received data matches the transmitted data pattern.
--
-- Link mode and tx bit rate may be programmed through digital inputs
-- (presumably connected to switches or buttons). Link state and progress of
-- the test are reported through digital outputs (presumably connected to
-- LEDs).
--
-- Note: there is no check on the integrity of the first packet received
-- after the link goes up.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.spwpkg.all;
entity streamtest is
generic (
-- System clock frequency in Hz.
sysfreq: real;
-- txclk frequency in Hz (if tximpl = impl_fast).
txclkfreq: real;
-- 2-log of division factor from system clock freq to timecode freq.
tickdiv: integer range 12 to 24 := 20;
-- Receiver front-end implementation.
rximpl: spw_implementation_type := impl_generic;
-- Maximum number of bits received per system clock (impl_fast only).
rxchunk: integer range 1 to 4 := 1;
-- Transmitter implementation.
tximpl: spw_implementation_type := impl_generic;
-- Size of receive FIFO.
rxfifosize_bits: integer range 6 to 14 := 11;
-- Size of transmit FIFO.
txfifosize_bits: integer range 2 to 14 := 11 );
port (
-- System clock.
clk: in std_logic;
-- Receiver sample clock (only for impl_fast).
rxclk: in std_logic;
-- Transmit clock (only for impl_fast).
txclk: in std_logic;
-- Synchronous reset (active-high).
rst: in std_logic;
-- Enables spontaneous link start.
linkstart: in std_logic;
-- Enables automatic link start on receipt of a NULL token.
autostart: in std_logic;
-- Do not start link and/or disconnect current link.
linkdisable: in std_logic;
-- Enable sending test patterns to spwstream.
senddata: in std_logic;
-- Enable sending time codes to spwstream.
sendtick: in std_logic;
-- Scaling factor minus 1 for TX bitrate.
txdivcnt: in std_logic_vector(7 downto 0);
-- Link in state Started.
linkstarted: out std_logic;
-- Link in state Connecting.
linkconnecting: out std_logic;
-- Link in state Run.
linkrun: out std_logic;
-- Link error (one cycle pulse, not directly suitable for LED)
linkerror: out std_logic;
-- High when taking a byte from the receive FIFO.
gotdata: out std_logic;
-- Incorrect or unexpected data received (sticky).
dataerror: out std_logic;
-- Incorrect or unexpected time code received (sticky).
tickerror: out std_logic;
-- SpaceWire signals.
spw_di: in std_logic;
spw_si: in std_logic;
spw_do: out std_logic;
spw_so: out std_logic );
end entity streamtest;
architecture streamtest_arch of streamtest is
-- Update 16-bit maximum length LFSR by 8 steps
function lfsr16(x: in std_logic_vector) return std_logic_vector is
variable y: std_logic_vector(15 downto 0);
begin
-- poly = x^16 + x^14 + x^13 + x^11 + 1
-- tap positions = x(0), x(2), x(3), x(5)
y(7 downto 0) := x(15 downto 8);
y(15 downto 8) := x(7 downto 0) xor x(9 downto 2) xor x(10 downto 3) xor x(12 downto 5);
return y;
end function;
-- Sending side state.
type tx_state_type is ( txst_idle, txst_prepare, txst_data );
-- Receiving side state.
type rx_state_type is ( rxst_idle, rxst_data );
-- Registers.
type regs_type is record
tx_state: tx_state_type;
tx_timecnt: std_logic_vector((tickdiv-1) downto 0);
tx_quietcnt: std_logic_vector(15 downto 0);
tx_pktlen: std_logic_vector(15 downto 0);
tx_lfsr: std_logic_vector(15 downto 0);
tx_enabledata: std_ulogic;
rx_state: rx_state_type;
rx_quietcnt: std_logic_vector(15 downto 0);
rx_enabledata: std_ulogic;
rx_gottick: std_ulogic;
rx_expecttick: std_ulogic;
rx_expectglitch: unsigned(5 downto 0);
rx_badpacket: std_ulogic;
rx_pktlen: std_logic_vector(15 downto 0);
rx_prev: std_logic_vector(15 downto 0);
rx_lfsr: std_logic_vector(15 downto 0);
running: std_ulogic;
tick_in: std_ulogic;
time_in: std_logic_vector(5 downto 0);
txwrite: std_ulogic;
txflag: std_ulogic;
txdata: std_logic_vector(7 downto 0);
rxread: std_ulogic;
gotdata: std_ulogic;
dataerror: std_ulogic;
tickerror: std_ulogic;
end record;
-- Reset state.
constant regs_reset: regs_type := (
tx_state => txst_idle,
tx_timecnt => (others => '0'),
tx_quietcnt => (others => '0'),
tx_pktlen => (others => '0'),
tx_lfsr => (1 => '1', others => '0'),
tx_enabledata => '0',
rx_state => rxst_idle,
rx_quietcnt => (others => '0'),
rx_enabledata => '0',
rx_gottick => '0',
rx_expecttick => '0',
rx_expectglitch => "000001",
rx_badpacket => '0',
rx_pktlen => (others => '0'),
rx_prev => (others => '0'),
rx_lfsr => (others => '0'),
running => '0',
tick_in => '0',
time_in => (others => '0'),
txwrite => '0',
txflag => '0',
txdata => (others => '0'),
rxread => '0',
gotdata => '0',
dataerror => '0',
tickerror => '0' );
signal r: regs_type := regs_reset;
signal rin: regs_type;
-- Interface signals.
signal s_txrdy: std_logic;
signal s_tickout: std_logic;
signal s_timeout: std_logic_vector(5 downto 0);
signal s_rxvalid: std_logic;
signal s_rxflag: std_logic;
signal s_rxdata: std_logic_vector(7 downto 0);
signal s_running: std_logic;
signal s_errdisc: std_logic;
signal s_errpar: std_logic;
signal s_erresc: std_logic;
signal s_errcred: std_logic;
begin
-- spwstream instance
spwstream_inst: spwstream
generic map (
sysfreq => sysfreq,
txclkfreq => txclkfreq,
rximpl => rximpl,
rxchunk => rxchunk,
tximpl => tximpl,
rxfifosize_bits => rxfifosize_bits,
txfifosize_bits => txfifosize_bits )
port map (
clk => clk,
rxclk => rxclk,
txclk => txclk,
rst => rst,
autostart => autostart,
linkstart => linkstart,
linkdis => linkdisable,
txdivcnt => txdivcnt,
tick_in => r.tick_in,
ctrl_in => (others => '0'),
time_in => r.time_in,
txwrite => r.txwrite,
txflag => r.txflag,
txdata => r.txdata,
txrdy => s_txrdy,
txhalff => open,
tick_out => s_tickout,
ctrl_out => open,
time_out => s_timeout,
rxvalid => s_rxvalid,
rxhalff => open,
rxflag => s_rxflag,
rxdata => s_rxdata,
rxread => r.rxread,
started => linkstarted,
connecting => linkconnecting,
running => s_running,
errdisc => s_errdisc,
errpar => s_errpar,
erresc => s_erresc,
errcred => s_errcred,
spw_di => spw_di,
spw_si => spw_si,
spw_do => spw_do,
spw_so => spw_so );
-- Drive status indications.
linkrun <= s_running;
linkerror <= s_errdisc or s_errpar or s_erresc or s_errcred;
gotdata <= r.gotdata;
dataerror <= r.dataerror;
tickerror <= r.tickerror;
process (r, rst, senddata, sendtick, s_txrdy, s_tickout, s_timeout, s_rxvalid, s_rxflag, s_rxdata, s_running) is
variable v: regs_type;
begin
v := r;
-- Initiate timecode transmissions.
v.tx_timecnt := std_logic_vector(unsigned(r.tx_timecnt) + 1);
if unsigned(v.tx_timecnt) = 0 then
v.tick_in := sendtick;
else
v.tick_in := '0';
end if;
if r.tick_in = '1' then
v.time_in := std_logic_vector(unsigned(r.time_in) + 1);
v.rx_expecttick := '1';
v.rx_gottick := '0';
end if;
-- Turn data generator on/off at regular intervals.
v.tx_quietcnt := std_logic_vector(unsigned(r.tx_quietcnt) + 1);
if unsigned(r.tx_quietcnt) = 61000 then
v.tx_quietcnt := (others => '0');
end if;
v.tx_enabledata := senddata and (not r.tx_quietcnt(15));
-- Generate data packets.
case r.tx_state is
when txst_idle =>
-- generate packet length
v.tx_state := txst_prepare;
v.tx_pktlen := r.tx_lfsr;
v.txwrite := '0';
v.tx_lfsr := lfsr16(r.tx_lfsr);
when txst_prepare =>
-- generate first byte of packet
v.tx_state := txst_data;
v.txwrite := r.tx_enabledata;
v.txflag := '0';
v.txdata := r.tx_lfsr(15 downto 8);
v.tx_lfsr := lfsr16(r.tx_lfsr);
when txst_data =>
-- generate data bytes and EOP
v.txwrite := r.tx_enabledata;
if r.txwrite = '1' and s_txrdy = '1' then
-- just sent one byte
v.tx_pktlen := std_logic_vector(unsigned(r.tx_pktlen) - 1);
if unsigned(r.tx_pktlen) = 0 then
-- done with packet
v.tx_state := txst_idle;
v.txwrite := '0';
elsif unsigned(r.tx_pktlen) = 1 then
-- generate EOP
v.txwrite := r.tx_enabledata;
v.txflag := '1';
v.txdata := (others => '0');
v.tx_lfsr := lfsr16(r.tx_lfsr);
else
-- generate next data byte
v.txwrite := r.tx_enabledata;
v.txflag := '0';
v.txdata := r.tx_lfsr(15 downto 8);
v.tx_lfsr := lfsr16(r.tx_lfsr);
end if;
end if;
end case;
-- Blink light when receiving data.
v.gotdata := s_rxvalid and r.rxread;
-- Detect missing timecodes.
if r.tick_in = '1' and r.rx_expecttick = '1' then
-- This is bad; a new timecode is being generated while
-- we have not even received the previous one yet.
v.tickerror := '1';
end if;
-- Receive and check incoming timecodes.
if s_tickout = '1' then
if unsigned(s_timeout) + 1 /= unsigned(r.time_in) then
-- Received time code does not match last transmitted code.
v.tickerror := '1';
end if;
if r.rx_gottick = '1' then
-- Already received the last transmitted time code.
v.tickerror := '1';
end if;
v.rx_expecttick := '0';
v.rx_gottick := '1';
end if;
-- Turn data receiving on/off at regular intervals
v.rx_quietcnt := std_logic_vector(unsigned(r.rx_quietcnt) + 1);
if unsigned(r.rx_quietcnt) = 55000 then
v.rx_quietcnt := (others => '0');
end if;
v.rx_enabledata := not r.rx_quietcnt(15);
case r.rx_state is
when rxst_idle =>
-- get expected packet length
v.rx_state := rxst_data;
v.rx_pktlen := r.rx_lfsr;
v.rx_lfsr := lfsr16(r.rx_lfsr);
v.rx_prev := (others => '0');
when rxst_data =>
v.rxread := r.rx_enabledata;
if r.rxread = '1' and s_rxvalid = '1' then
-- got next byte
v.rx_pktlen := std_logic_vector(unsigned(r.rx_pktlen) - 1);
v.rx_prev := s_rxdata & r.rx_prev(15 downto 8);
if s_rxflag = '1' then
-- got EOP or EEP
v.rxread := '0';
v.rx_state := rxst_idle;
if s_rxdata = "00000000" then
-- got EOP
if unsigned(r.rx_pktlen) /= 0 then
-- unexpected EOP
v.rx_badpacket := '1';
end if;
-- count errors against expected glitches
if v.rx_badpacket = '1' then
-- got glitch
if r.rx_expectglitch = 0 then
v.dataerror := '1';
else
v.rx_expectglitch := r.rx_expectglitch - 1;
end if;
end if;
-- resynchronize LFSR
v.rx_lfsr := lfsr16(lfsr16(r.rx_prev));
else
-- got EEP
v.rx_badpacket := '1';
end if;
v.rx_badpacket := '0';
else
-- got next byte
v.rx_lfsr := lfsr16(r.rx_lfsr);
if unsigned(r.rx_pktlen) = 0 then
-- missing EOP
v.rx_badpacket := '1';
end if;
if s_rxdata /= r.rx_lfsr(15 downto 8) then
-- bad data
v.rx_badpacket := '1';
end if;
end if;
end if;
end case;
-- If the link goes away, we should expect inconsistency on the receiving side.
v.running := s_running;
if r.running = '1' and s_running = '0' then
if r.rx_expectglitch /= "111111" then
v.rx_expectglitch := r.rx_expectglitch + 1;
end if;
end if;
-- If there is no link, we should not expect to receive time codes.
if s_running = '0' then
v.rx_expecttick := '0';
end if;
-- Synchronous reset.
if rst = '1' then
v := regs_reset;
end if;
-- Update registers.
rin <= v;
end process;
-- Update registers.
process (clk) is
begin
if rising_edge(clk) then
r <= rin;
end if;
end process;
end architecture streamtest_arch;
| gpl-3.0 | 228253acb8fc48be78267e2cb333c3f1 | 0.478266 | 3.971189 | false | false | false | false |
yishinli/emc2 | src/hal/drivers/mesa-hostmot2/firmware/src/timestamp.vhd | 1 | 4,010 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
-- http://www.mesanet.com
--
-- This program is is licensed under a disjunctive dual license giving you
-- the choice of one of the two following sets of free software/open source
-- licensing terms:
--
-- * GNU General Public License (GPL), version 2.0 or later
-- * 3-clause BSD License
--
--
-- The GNU GPL License:
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
--
--
-- The 3-clause BSD License:
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- * Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- * Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- * Neither the name of Mesa Electronics nor the names of its
-- contributors may be used to endorse or promote products
-- derived from this software without specific prior written
-- permission.
--
--
-- Disclaimer:
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
entity timestamp is
Port ( ibus : in std_logic_vector(15 downto 0);
obus : out std_logic_vector(15 downto 0);
loadtsdiv : in std_logic;
readts : in std_logic;
readtsdiv : in std_logic;
tscount : out std_logic_vector (15 downto 0);
clk : in std_logic);
end timestamp;
architecture Behavioral of timestamp is
signal counter: std_logic_vector (15 downto 0);
signal div: std_logic_vector(15 downto 0);
alias divmsb: std_logic is div(15);
signal divlatch: std_logic_vector (15 downto 0);
begin
atimestamp: process (clk,readts, counter, readtsdiv, divlatch)
begin
if rising_edge(clk) then
div <= div -1;
if divmsb = '1' then
div <= divlatch;
counter <= counter + 1;
end if;
if loadtsdiv = '1' then
divlatch <= ibus;
end if;
end if; -- clk
obus <= (others => 'Z');
if readts = '1' then
obus <= counter;
end if;
if readtsdiv = '1' then
obus <= divlatch;
end if;
tscount <= counter;
end process;
end Behavioral;
| lgpl-2.1 | 63904e1802477c3a970e7a38a3fa5459 | 0.678304 | 3.896987 | false | false | false | false |
pwsoft/fpga_examples | rtl/ttl/ttl_7485.vhd | 1 | 2,896 | -- -----------------------------------------------------------------------
--
-- Syntiac VHDL support files.
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2018 by Peter Wendrich ([email protected])
-- http://www.syntiac.com
--
-- This source file is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- -----------------------------------------------------------------------
-- 4-bit magnitude comparator
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use work.ttl_pkg.all;
-- -----------------------------------------------------------------------
entity ttl_7485 is
generic (
latency : integer := 3
);
port (
emuclk : in std_logic;
p2 : in ttl_t; -- I A<B
p3 : in ttl_t; -- I A=B
p4 : in ttl_t; -- I A>B
p5 : out ttl_t; -- Q A>B
p6 : out ttl_t; -- Q A=B
p7 : out ttl_t; -- Q A<B
p10 : in ttl_t; -- A0
p12 : in ttl_t; -- A1
p13 : in ttl_t; -- A2
p15 : in ttl_t; -- A3
p9 : in ttl_t; -- B0
p11 : in ttl_t; -- B1
p14 : in ttl_t; -- B2
p1 : in ttl_t -- B3
);
end entity;
architecture rtl of ttl_7485 is
signal p5_loc : ttl_t;
signal p6_loc : ttl_t;
signal p7_loc : ttl_t;
signal a : unsigned(3 downto 0);
signal b : unsigned(3 downto 0);
begin
p5_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p5_loc, q => p5);
p6_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p6_loc, q => p6);
p7_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p7_loc, q => p7);
a <= ttl2std(p15) & ttl2std(p13) & ttl2std(p12) & ttl2std(p10);
b <= ttl2std(p1) & ttl2std(p14) & ttl2std(p11) & ttl2std(p9);
p5_loc <=
ONE when a>b else
ONE when (a=b) and (is_low(p2) and is_low(p3) and is_high(p4)) else
ONE when (a=b) and (is_low(p2) and is_low(p3) and is_low(p4)) else
ZERO;
p6_loc <=
ONE when (a=b) and is_high(p3) else
ZERO;
p7_loc <=
ONE when a<b else
ONE when (a=b) and (is_high(p2) and is_low(p3) and is_low(p4)) else
ONE when (a=b) and (is_low(p2) and is_low(p3) and is_low(p4)) else
ZERO;
end architecture;
| lgpl-2.1 | 4e447c5599bb48d244016d7c954cbb4f | 0.556975 | 2.898899 | false | false | false | false |
yishinli/emc2 | src/hal/drivers/mesa-hostmot2/firmware/src/qcounterate.vhd | 1 | 3,758 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
-- http://www.mesanet.com
--
-- This program is is licensed under a disjunctive dual license giving you
-- the choice of one of the two following sets of free software/open source
-- licensing terms:
--
-- * GNU General Public License (GPL), version 2.0 or later
-- * 3-clause BSD License
--
--
-- The GNU GPL License:
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
--
--
-- The 3-clause BSD License:
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- * Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- * Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- * Neither the name of Mesa Electronics nor the names of its
-- contributors may be used to endorse or promote products
-- derived from this software without specific prior written
-- permission.
--
--
-- Disclaimer:
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
entity qcounterate is
generic ( defaultrate : std_logic_vector(11 downto 0));
port ( ibus : in std_logic_vector (11 downto 0);
loadrate : in std_logic;
rateout : out std_logic;
clk : in std_logic);
end qcounterate;
architecture Behavioral of qcounterate is
signal rate: std_logic_vector (11 downto 0) := defaultrate; -- divides by n+2, 0x800 for divide by 1
signal count: std_logic_vector (11 downto 0);
alias countmsb: std_logic is count(11);
begin
arate: process (clk,count)
begin
if rising_edge(clk) then
if countmsb= '0' then
count <= count -1;
else
count <= rate;
end if;
if loadrate = '1' then
rate <= ibus;
end if;
end if;
rateout <= countmsb;
end process;
end Behavioral;
| lgpl-2.1 | 2ed8d2920e9adeba5287dc9352af91fb | 0.684939 | 3.959958 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/techmap/inferred/mul_inferred.vhd | 1 | 4,290 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: gen_mul_61x61
-- File: mul_inferred.vhd
-- Author: Edvin Catovic - Gaisler Research
-- Description: Generic 61x61 multplier
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
entity gen_mul_61x61 is
port(A : in std_logic_vector(60 downto 0);
B : in std_logic_vector(60 downto 0);
EN : in std_logic;
CLK : in std_logic;
PRODUCT : out std_logic_vector(121 downto 0));
end;
architecture rtl of gen_mul_61x61 is
signal r1, r1in, r2, r2in : std_logic_vector(121 downto 0);
begin
comb : process(A, B, r1)
begin
-- pragma translate_off
if not (is_x(A) or is_x(B)) then
-- pragma translate_on
r1in <= std_logic_vector(unsigned(A) * unsigned(B));
-- pragma translate_off
end if;
-- pragma translate_on
r2in <= r1;
end process;
reg : process(clk)
begin
if rising_edge(clk) then
if EN = '1' then
r1 <= r1in;
r2 <= r2in;
end if;
end if;
end process;
PRODUCT <= r2;
end;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library grlib;
use grlib.stdlib.all;
entity gen_mult_pipe is
generic (
a_width : positive; -- multiplier word width
b_width : positive; -- multiplicand word width
num_stages : positive := 2; -- number of pipeline stages
stall_mode : natural range 0 to 1 := 1); -- '0': non-stallable; '1': stallable
port (
clk : in std_logic; -- register clock
en : in std_logic; -- register enable
tc : in std_logic; -- '0' : unsigned, '1' : signed
a : in std_logic_vector(a_width-1 downto 0); -- multiplier
b : in std_logic_vector(b_width-1 downto 0); -- multiplicand
product : out std_logic_vector(a_width+b_width-1 downto 0)); -- product
end ;
architecture simple of gen_mult_pipe is
subtype resw is std_logic_vector(A_width+B_width-1 downto 0);
type pipet is array (num_stages-1 downto 1) of resw;
signal p_i : pipet;
signal prod : resw;
begin
comb : process(A, B, TC)
begin
-- pragma translate_off
if notx(A) and notx(B) and notx(tc) then
-- pragma translate_on
if TC = '1' then
prod <= signed(A) * signed(B);
else
prod <= unsigned(A) * unsigned(B);
end if;
-- pragma translate_off
else
prod <= (others => 'X');
end if;
-- pragma translate_on
end process;
w2 : if num_stages = 2 generate
reg : process(clk)
begin
if rising_edge(clk) then
if (stall_mode = 0) or (en = '1') then
p_i(1) <= prod;
end if;
end if;
end process;
end generate;
w3 : if num_stages > 2 generate
reg : process(clk)
begin
if rising_edge(clk) then
if (stall_mode = 0) or (en = '1') then
p_i <= p_i(num_stages-2 downto 1) & prod;
end if;
end if;
end process;
end generate;
product <= p_i(num_stages-1);
end;
| gpl-3.0 | e88277a22f845541360b3a6fba959118 | 0.570629 | 3.566085 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/spi/spi2ahb_apb.vhd | 1 | 6,864 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: spi2ahb_apb
-- File: spi2ahb_apb.vhd
-- Author: Jan Andersson - Aeroflex Gaisler AB
-- Contact: [email protected]
-- Description: Simple SPI slave providing a bridge to AMBA AHB
-- This entity provides an APB interface for setting defining the
-- AHB address window that can be accessed from SPI.
-- See spi2ahbx.vhd and GRIP for documentation
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.spi.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.conv_std_logic;
use grlib.stdlib.conv_std_logic_vector;
entity spi2ahb_apb is
generic (
-- AHB Configuration
hindex : integer := 0;
--
ahbaddrh : integer := 0;
ahbaddrl : integer := 0;
ahbmaskh : integer := 0;
ahbmaskl : integer := 0;
resen : integer := 0;
-- APB configuration
pindex : integer := 0; -- slave bus index
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
--
oepol : integer range 0 to 1 := 0;
--
filter : integer range 2 to 512 := 2;
--
cpol : integer range 0 to 1 := 0;
cpha : integer range 0 to 1 := 0
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- AHB master interface
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
--
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
-- SPI signals
spii : in spi_in_type;
spio : out spi_out_type
);
end entity spi2ahb_apb;
architecture rtl of spi2ahb_apb is
-- Register offsets
constant CTRL_OFF : std_logic_vector(4 downto 2) := "000";
constant STS_OFF : std_logic_vector(4 downto 2) := "001";
constant ADDR_OFF : std_logic_vector(4 downto 2) := "010";
constant MASK_OFF : std_logic_vector(4 downto 2) := "011";
-- AMBA PnP
constant PCONFIG : apb_config_type := (
0 => ahb_device_reg(VENDOR_GAISLER, GAISLER_SPI2AHB, 0, 0, 0),
1 => apb_iobar(paddr, pmask));
type apb_reg_type is record
spi2ahbi : spi2ahb_in_type;
irq : std_ulogic;
irqen : std_ulogic;
prot : std_ulogic;
protx : std_ulogic;
wr : std_ulogic;
dma : std_ulogic;
dmax : std_ulogic;
end record;
signal r, rin : apb_reg_type;
signal spi2ahbo : spi2ahb_out_type;
begin
bridge : spi2ahbx
generic map (hindex => hindex, oepol => oepol, filter => filter,
cpol => cpol, cpha => cpha)
port map (rstn => rstn, clk => clk, ahbi => ahbi, ahbo => ahbo,
spii => spii, spio => spio, spi2ahbi => r.spi2ahbi,
spi2ahbo => spi2ahbo);
comb: process (r, rstn, apbi, spi2ahbo)
variable v : apb_reg_type;
variable apbaddr : std_logic_vector(4 downto 2);
variable apbout : std_logic_vector(31 downto 0);
variable irqout : std_logic_vector(NAHBIRQ-1 downto 0);
begin
v := r; apbaddr := apbi.paddr(apbaddr'range); apbout := (others => '0');
v.irq := '0'; irqout := (others => '0'); irqout(pirq) := r.irq;
v.protx := spi2ahbo.prot; v.dmax := spi2ahbo.dma;
---------------------------------------------------------------------------
-- APB register interface
---------------------------------------------------------------------------
-- read registers
if (apbi.psel(pindex) and apbi.penable) = '1' then
case apbaddr is
when CTRL_OFF => apbout(1 downto 0) := r.irqen & r.spi2ahbi.en;
when STS_OFF => apbout(2 downto 0) := r.prot & r.wr & r.dma;
when ADDR_OFF => apbout := r.spi2ahbi.haddr;
when MASK_OFF => apbout := r.spi2ahbi.hmask;
when others => null;
end case;
end if;
-- write registers
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbaddr is
when CTRL_OFF => v.irqen := apbi.pwdata(1); v.spi2ahbi.en := apbi.pwdata(0);
when STS_OFF => v.dma := r.dma and not apbi.pwdata(0);
v.prot := r.prot and not apbi.pwdata(2);
when ADDR_OFF => v.spi2ahbi.haddr := apbi.pwdata;
when MASK_OFF => v.spi2ahbi.hmask := apbi.pwdata;
when others => null;
end case;
end if;
-- interrupt and status register handling
if ((spi2ahbo.dma and not r.dmax) or
(spi2ahbo.prot and not r.protx)) = '1' then
v.dma := '1'; v.prot := r.prot or spi2ahbo.prot; v.wr := spi2ahbo.wr;
if (r.irqen and not r.dma) = '1' then v.irq := '1'; end if;
end if;
---------------------------------------------------------------------------
-- reset
---------------------------------------------------------------------------
if rstn = '0' then
v.spi2ahbi.en := conv_std_logic(resen = 1);
v.spi2ahbi.haddr := conv_std_logic_vector(ahbaddrh, 16) &
conv_std_logic_vector(ahbaddrl, 16);
v.spi2ahbi.hmask := conv_std_logic_vector(ahbmaskh, 16) &
conv_std_logic_vector(ahbmaskl, 16);
v.irqen := '0'; v.prot := '0'; v.wr := '0'; v.dma := '0';
end if;
---------------------------------------------------------------------------
-- signal assignments
---------------------------------------------------------------------------
-- update registers
rin <= v;
-- update outputs
apbo.prdata <= apbout;
apbo.pirq <= irqout;
apbo.pconfig <= PCONFIG;
apbo.pindex <= pindex;
end process comb;
reg: process(clk)
begin
if rising_edge(clk) then r <= rin; end if;
end process reg;
-- Boot message provided in spi2ahbx...
end architecture rtl;
| gpl-3.0 | 623f0b3eb7a1767df6beb4141114b2ca | 0.536276 | 3.79646 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/ddr/ddrphy_wrap.vhd | 1 | 58,150 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ddr_phy
-- File: ddr_phy.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: Wrapper entities for techmap ddrphy/ddr2phy
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.ddrpkg.all;
------------------------------------------------------------------
-- DDR1 PHY wrapper -------------------------------------------------------
------------------------------------------------------------------
entity ddrphy_wrap is
generic (tech : integer := virtex2; MHz : integer := 100;
rstdelay : integer := 200; dbits : integer := 16;
clk_mul : integer := 2 ; clk_div : integer := 2;
rskew : integer :=0; mobile : integer := 0;
scantest : integer := 0; phyiconf : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic;
clkread : out std_ulogic; -- read clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
sdi : out ddrctrl_in_type;
sdo : in ddrctrl_out_type;
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic);
end;
architecture rtl of ddrphy_wrap is
begin
ddr_phy0 : ddrphy
generic map (tech => tech, MHz => MHz, rstdelay => rstdelay
-- reduce 200 us start-up delay during simulation
-- pragma translate_off
/ 200
-- pragma translate_on
, dbits => dbits, clk_mul => clk_mul, clk_div => clk_div,
rskew => rskew, mobile => mobile, scantest => scantest,
phyiconf => phyiconf)
port map (
rst, clk, clkout, clkoutret, clkread, lock,
ddr_clk, ddr_clkb, ddr_clk_fb_out, ddr_clk_fb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_ad, ddr_ba, ddr_dq,
sdo.address(13 downto 0), sdo.ba(1 downto 0),
sdi.data(dbits*2-1 downto 0), sdo.data(dbits*2-1 downto 0),
sdo.dqm(dbits/4-1 downto 0), sdo.bdrive, sdo.bdrive, sdo.qdrive,
sdo.rasn, sdo.casn, sdo.sdwen, sdo.sdcsn, sdo.sdcke, sdo.sdck(2 downto 0), sdo.moben,
sdi.datavalid, testen, testrst, scanen, testoen);
drvdata : if dbits < 64 generate
sdi.data(127 downto dbits*2) <= (others => '0');
end generate;
sdi.cb <= (others => '0'); sdi.regrdata <= (others => '0');
sdi.writereq <= '0';
end;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.ddrpkg.all;
------------------------------------------------------------------
-- DDR1 PHY with checkbits merged on data bus --------------------
------------------------------------------------------------------
entity ddrphy_wrap_cbd is
generic (tech : integer := virtex2; MHz : integer := 100;
rstdelay : integer := 200; dbits : integer := 16;
chkbits: integer := 0; padbits : integer := 0;
clk_mul : integer := 2 ; clk_div : integer := 2;
rskew : integer :=0; mobile : integer := 0;
abits: integer := 14; nclk: integer := 3; ncs: integer := 2;
scantest: integer := 0; phyiconf : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic; -- system clock return
clkread : out std_ulogic;
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits+padbits+chkbits-1 downto 0); -- ddr data
sdi : out ddrctrl_in_type;
sdo : in ddrctrl_out_type;
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic);
end;
architecture rtl of ddrphy_wrap_cbd is
function ddr_widthconv(x: std_logic_vector; ow: integer) return std_logic_vector is
variable r: std_logic_vector(2*ow-1 downto 0);
constant iw: integer := x'length/2;
begin
r := (others => '0');
if iw <= ow then
r(iw+ow-1 downto ow) := x(2*iw-1 downto iw);
r(iw-1 downto 0) := x(iw-1 downto 0);
else
r := x(iw+ow-1 downto iw) & x(ow-1 downto 0);
end if;
return r;
end;
function sdr_widthconv(x: std_logic_vector; ow: integer) return std_logic_vector is
variable r: std_logic_vector(ow-1 downto 0);
constant iw: integer := x'length;
variable xd : std_logic_vector(iw-1 downto 0);
begin
r := (others => '0'); xd := x;
if iw >= ow then
r := xd(ow-1 downto 0);
else
r(iw-1 downto 0) := xd;
end if;
return r;
end;
function ddrmerge(a,b: std_logic_vector) return std_logic_vector is
constant aw: integer := a'length/2;
constant bw: integer := b'length/2;
begin
return a(2*aw-1 downto aw) & b(2*bw-1 downto bw) & a(aw-1 downto 0) & b(bw-1 downto 0);
end;
signal dqin: std_logic_vector(2*(chkbits+dbits+padbits)-1 downto 0);
signal dqout: std_logic_vector(2*(chkbits+dbits+padbits)-1 downto 0);
signal dqm: std_logic_vector((chkbits+dbits+padbits)/4-1 downto 0);
signal cal_en: std_logic_vector((chkbits+dbits+padbits)/8-1 downto 0);
signal cal_inc: std_logic_vector((chkbits+dbits+padbits)/8-1 downto 0);
signal odt,csn,cke: std_logic_vector(ncs-1 downto 0);
signal sdck: std_logic_vector(nclk-1 downto 0);
begin
-- Merge checkbit and data buses
comb: process(sdo,dqin)
variable dq: std_logic_vector(2*dbits-1 downto 0);
variable dqpad: std_logic_vector(2*(dbits+padbits)-1 downto 0);
variable cb: std_logic_vector(dbits-1 downto 0);
variable cbpad: std_logic_vector(2*chkbits downto 0); -- Extra bit to handle chkbits=0
variable dqcb: std_logic_vector(2*(dbits+padbits+chkbits)-1 downto 0);
variable dm: std_logic_vector(dbits/4-1 downto 0);
variable dmpad: std_logic_vector((dbits+padbits)/4-1 downto 0);
variable cbdm: std_logic_vector(dbits/8-1 downto 0);
variable cbdmpad: std_logic_vector(chkbits/4 downto 0);
variable dqcbdm: std_logic_vector((dbits+padbits+chkbits)/4-1 downto 0);
variable vcsn,vcke: std_logic_vector(ncs-1 downto 0);
variable vsdck: std_logic_vector(nclk-1 downto 0);
begin
dq := sdo.data(2*dbits-1 downto 0);
dqpad := ddr_widthconv(dq, dbits+padbits );
if chkbits > 0 then
cb := sdo.cb(dbits-1 downto 0);
cbpad := '0' & ddr_widthconv(cb, chkbits);
dqcb := ddrmerge(cbpad(2*chkbits-1 downto 0), dqpad);
else
dqcb := dqpad;
end if;
dqout <= dqcb;
dqcb := dqin;
if chkbits > 0 then
cbpad := '0' & dqin(2*(chkbits+dbits+padbits)-1 downto 2*(dbits+padbits)+chkbits) &
dqin(chkbits+dbits+padbits-1 downto dbits+padbits);
cb := ddr_widthconv(cbpad(2*chkbits-1 downto 0), dbits/2);
else
cb := (others => '0');
end if;
dq := dqcb(2*dbits+chkbits+padbits-1 downto dbits+chkbits+padbits) &
dqcb(dbits-1 downto 0);
sdi.cb(dbits-1 downto 0) <= cb;
sdi.data(2*dbits-1 downto 0) <= dq;
if sdi.cb'length > dbits then
sdi.cb(sdi.cb'length-1 downto dbits) <= (others => '0');
end if;
if sdi.data'length > 2*dbits then
sdi.data(sdi.data'length-1 downto 2*dbits) <= (others => '0');
end if;
dm := sdo.dqm(dbits/4-1 downto 0);
dmpad := ddr_widthconv(dm, (dbits+padbits)/8);
if chkbits > 0 then
cbdm := sdo.cbdqm(dbits/8-1 downto 0);
cbdmpad := '0' & ddr_widthconv(cbdm(dbits/8-1 downto 0), chkbits/8);
dqcbdm := ddrmerge(cbdmpad(chkbits/4-1 downto 0), dmpad);
else
dqcbdm := dmpad;
end if;
dqm <= dqcbdm;
cal_en <= sdr_widthconv(sdo.cbcal_en (dbits/16-1 downto 0) &
sdo.cal_en (dbits/8-1 downto 0), (dbits+padbits+chkbits)/8 );
cal_inc <= sdr_widthconv(sdo.cbcal_inc(dbits/16-1 downto 0) &
sdo.cal_inc(dbits/8-1 downto 0), (dbits+padbits+chkbits)/8 );
vcsn := (others => '1');
for x in 0 to ncs-1 loop
if x<2 then
vcsn(x) := sdo.sdcsn(x);
end if;
vcke(x) := sdo.sdcke(x mod 2);
end loop;
for x in 0 to nclk-1 loop
vsdck(x) := sdo.sdck(x mod 2);
end loop;
csn <= vcsn;
cke <= vcke;
sdck <= vsdck;
end process;
-- Phy instantiation
ddr_phy0 : ddrphy
generic map (tech => tech, MHz => MHz, rstdelay => rstdelay
-- reduce 200 us start-up delay during simulation
-- pragma translate_off
/ 200
-- pragma translate_on
, dbits => dbits+padbits+chkbits,clk_mul => clk_mul, clk_div => clk_div,
rskew => rskew, mobile => mobile,
abits => abits, nclk => nclk, ncs => ncs, scantest => scantest,
phyiconf => phyiconf)
port map (
rst, clk, clkout, clkoutret, clkread, lock,
ddr_clk, ddr_clkb, ddr_clk_fb_out, ddr_clk_fb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_ad, ddr_ba, ddr_dq,
sdo.address(abits-1 downto 0), sdo.ba(1 downto 0),
dqin, dqout,
dqm, sdo.bdrive, sdo.bdrive, sdo.qdrive,
sdo.rasn, sdo.casn, sdo.sdwen, csn, cke, sdck, sdo.moben,sdi.datavalid,
testen,testrst,scanen,testoen);
sdi.regrdata <= (others => '0');
sdi.writereq <= '0';
end;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.ddrpkg.all;
------------------------------------------------------------------
-- DDR1 PHY with checkbits merged on data bus, pads not in phy --
------------------------------------------------------------------
entity ddrphy_wrap_cbd_wo_pads is
generic (tech : integer := virtex2; MHz : integer := 100;
rstdelay : integer := 200; dbits : integer := 16; padbits : integer := 0;
clk_mul : integer := 2 ; clk_div : integer := 2;
rskew : integer := 0; mobile : integer := 0;
abits : integer := 14; nclk : integer := 3; ncs : integer := 2;
chkbits : integer := 0;
scantest : integer := 0; phyiconf : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic; -- system clock return
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dm
ddr_dqs_in : in std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs
ddr_dqs_out : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs
ddr_dqs_oen : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq_in : in std_logic_vector (dbits+padbits+chkbits-1 downto 0); -- ddr data
ddr_dq_out : out std_logic_vector (dbits+padbits+chkbits-1 downto 0); -- ddr data
ddr_dq_oen : out std_logic_vector (dbits+padbits+chkbits-1 downto 0);
sdi : out ddrctrl_in_type;
sdo : in ddrctrl_out_type;
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic);
end;
architecture rtl of ddrphy_wrap_cbd_wo_pads is
function ddr_widthconv(x: std_logic_vector; ow: integer) return std_logic_vector is
variable r: std_logic_vector(2*ow-1 downto 0);
constant iw: integer := x'length/2;
begin
r := (others => '0');
if iw <= ow then
r(iw+ow-1 downto ow) := x(2*iw-1 downto iw);
r(iw-1 downto 0) := x(iw-1 downto 0);
else
r := x(iw+ow-1 downto iw) & x(ow-1 downto 0);
end if;
return r;
end;
function sdr_widthconv(x: std_logic_vector; ow: integer) return std_logic_vector is
variable r: std_logic_vector(ow-1 downto 0);
constant iw: integer := x'length;
variable xd : std_logic_vector(iw-1 downto 0);
begin
r := (others => '0'); xd := x;
if iw >= ow then
r := xd(ow-1 downto 0);
else
r(iw-1 downto 0) := xd;
end if;
return r;
end;
function ddrmerge(a,b: std_logic_vector) return std_logic_vector is
constant aw: integer := a'length/2;
constant bw: integer := b'length/2;
begin
return a(2*aw-1 downto aw) & b(2*bw-1 downto bw) & a(aw-1 downto 0) & b(bw-1 downto 0);
end;
signal dqin: std_logic_vector(2*(chkbits+dbits+padbits)-1 downto 0);
signal dqout: std_logic_vector(2*(chkbits+dbits+padbits)-1 downto 0);
signal dqm: std_logic_vector((chkbits+dbits+padbits)/4-1 downto 0);
signal odt,csn,cke: std_logic_vector(ncs-1 downto 0);
signal sdck: std_logic_vector(nclk-1 downto 0);
signal gnd : std_logic_vector(chkbits*2-1 downto 0);
begin
gnd <= (others => '0');
-- Merge checkbit and data buses
comb: process(sdo,dqin)
variable dq: std_logic_vector(2*dbits-1 downto 0);
variable dqpad: std_logic_vector(2*(dbits+padbits)-1 downto 0);
variable cb: std_logic_vector(dbits-1 downto 0);
variable cbpad: std_logic_vector(2*chkbits downto 0); -- Extra bit to handle chkbits=0
variable dqcb: std_logic_vector(2*(dbits+padbits+chkbits)-1 downto 0);
variable dm: std_logic_vector(dbits/4-1 downto 0);
variable dmpad: std_logic_vector((dbits+padbits)/4-1 downto 0);
variable cbdm: std_logic_vector(dbits/8-1 downto 0);
variable cbdmpad: std_logic_vector(chkbits/4 downto 0);
variable dqcbdm: std_logic_vector((dbits+padbits+chkbits)/4-1 downto 0);
variable vcsn,vodt,vcke: std_logic_vector(ncs-1 downto 0);
variable vsdck: std_logic_vector(nclk-1 downto 0);
begin
dq := sdo.data(2*dbits-1 downto 0);
dqpad := ddr_widthconv(dq, dbits+padbits );
if chkbits > 0 then
cb := sdo.cb(dbits-1 downto 0);
cbpad := '0' & ddr_widthconv(cb, chkbits);
dqcb := ddrmerge(cbpad(2*chkbits-1 downto 0), dqpad);
else
dqcb := dqpad;
end if;
dqout <= dqcb;
dqcb := dqin;
if chkbits > 0 then
cbpad := '0' & dqin(2*(chkbits+dbits+padbits)-1 downto 2*(dbits+padbits)+chkbits) &
dqin(chkbits+dbits+padbits-1 downto dbits+padbits);
cb := ddr_widthconv(cbpad(2*chkbits-1 downto 0), dbits/2);
else
cb := (others => '0');
end if;
dq := dqcb(2*dbits+chkbits+padbits-1 downto dbits+chkbits+padbits) &
dqcb(dbits-1 downto 0);
sdi.cb(dbits-1 downto 0) <= cb;
sdi.data(2*dbits-1 downto 0) <= dq;
if sdi.cb'length > dbits then
sdi.cb(sdi.cb'length-1 downto dbits) <= (others => '0');
end if;
if sdi.data'length > 2*dbits then
sdi.data(sdi.data'length-1 downto 2*dbits) <= (others => '0');
end if;
dm := sdo.dqm(dbits/4-1 downto 0);
dmpad := ddr_widthconv(dm, (dbits+padbits)/8);
if chkbits > 0 then
cbdm := sdo.cbdqm(dbits/8-1 downto 0);
cbdmpad := '0' & ddr_widthconv(cbdm(dbits/8-1 downto 0), chkbits/8);
dqcbdm := ddrmerge(cbdmpad(chkbits/4-1 downto 0), dmpad);
else
dqcbdm := dmpad;
end if;
dqm <= dqcbdm;
vcsn := (others => '1');
for x in 0 to ncs-1 loop
if x<2 then
vcsn(x) := sdo.sdcsn(x);
end if;
vodt(x) := sdo.odt(x mod 2);
vcke(x) := sdo.sdcke(x mod 2);
end loop;
for x in 0 to nclk-1 loop
vsdck(x) := sdo.sdck(x mod 2);
end loop;
csn <= vcsn;
cke <= vcke;
sdck <= vsdck;
end process;
-- Phy instantiation
ddr_phy0 : ddrphy_wo_pads
generic map (
tech => tech, MHz => MHz, rstdelay => rstdelay
-- reduce 200 us start-up delay during simulation
-- pragma translate_off
/ 200
-- pragma translate_on
, dbits => dbits+padbits+chkbits, clk_mul => clk_mul, clk_div => clk_div,
rskew => rskew,
abits => abits, nclk => nclk, ncs => ncs, mobile => mobile, scantest => scantest, phyiconf => phyiconf)
port map (
rst => rst, clk => clk, clkout => clkout, clkoutret => clkoutret,
lock => lock,
ddr_clk => ddr_clk, ddr_clkb => ddr_clkb, ddr_clk_fb_out => ddr_clk_fb_out, ddr_clk_fb => ddr_clk_fb,
ddr_cke => ddr_cke, ddr_csb => ddr_csb, ddr_web => ddr_web, ddr_rasb => ddr_rasb, ddr_casb => ddr_casb,
ddr_dm => ddr_dm, ddr_dqs_in => ddr_dqs_in, ddr_dqs_out => ddr_dqs_out, ddr_dqs_oen => ddr_dqs_oen,
ddr_ad => ddr_ad, ddr_ba => ddr_ba, ddr_dq_in => ddr_dq_in, ddr_dq_out => ddr_dq_out, ddr_dq_oen => ddr_dq_oen,
addr => sdo.address(abits-1 downto 0), ba => sdo.ba(1 downto 0), dqin => dqin, dqout => dqout, dm => dqm,
oen => sdo.bdrive,
dqs => sdo.bdrive, dqsoen => sdo.qdrive, rasn => sdo.rasn, casn => sdo.casn, wen => sdo.sdwen, csn => csn,
cke => cke, ck => sdck, moben => sdo.moben, dqvalid => sdi.datavalid,
testen => testen, testrst => testrst, scanen => scanen, testoen => testoen
);
sdi.regrdata <= (others => '0');
sdi.writereq <= '0';
end;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.ddrpkg.all;
------------------------------------------------------------------
-- DDR2 PHY wrapper -----------------------------------------------
------------------------------------------------------------------
-------------------------------------------------------------------------------
-- There are three variants of the PHY wrapper depending on pads/checkbits:
-- 1. ddr2phy_wrap:
-- This provides pads and outputs checkbits on separate vectors
-- 2. ddr2phy_wrap_cbd:
-- This provides pads and merges checkbits+data on same vector
-- 3. ddr2phy_wrap_cbd_wo_pads:
-- This does not provide pads and merges checkbits+data on same vectors
--
-- Variants (1),(3) can not be used when ddr2phy_builtin_pads(tech)=1
-------------------------------------------------------------------------------
entity ddr2phy_wrap is
generic (tech : integer := virtex2; MHz : integer := 100;
rstdelay : integer := 200; dbits : integer := 16; padbits : integer := 0;
clk_mul : integer := 2 ; clk_div : integer := 2;
ddelayb0 : integer := 0; ddelayb1 : integer := 0; ddelayb2 : integer := 0;
ddelayb3 : integer := 0; ddelayb4 : integer := 0; ddelayb5 : integer := 0;
ddelayb6 : integer := 0; ddelayb7 : integer := 0;
cbdelayb0 : integer := 0; cbdelayb1: integer := 0; cbdelayb2: integer := 0;
cbdelayb3 : integer := 0;
numidelctrl : integer := 4; norefclk : integer := 0; odten : integer := 0;
rskew : integer := 0; eightbanks : integer range 0 to 1 := 0;
dqsse : integer range 0 to 1 := 0;
abits : integer := 14; nclk : integer := 3; ncs : integer := 2;
cben : integer := 0; chkbits : integer := 8; ctrl2en : integer := 0;
resync : integer := 0; custombits: integer := 8;
scantest : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkref200 : in std_logic; -- input 200MHz clock
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic; -- system clock return
clkresync : in std_ulogic; -- resync clock (if resync/=0)
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector ((dbits+padbits)/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector ((dbits+padbits)/8-1 downto 0); -- ddr dqs
ddr_dqsn : inout std_logic_vector ((dbits+padbits)/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector ((dbits+padbits)-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(ncs-1 downto 0);
ddr_cbdm : out std_logic_vector(chkbits/8-1 downto 0);
ddr_cbdqs : inout std_logic_vector(chkbits/8-1 downto 0);
ddr_cbdqsn : inout std_logic_vector(chkbits/8-1 downto 0);
ddr_cbdq : inout std_logic_vector(chkbits-1 downto 0);
ddr_web2 : out std_ulogic; -- ddr write enable
ddr_rasb2 : out std_ulogic; -- ddr ras
ddr_casb2 : out std_ulogic; -- ddr cas
ddr_ad2 : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba2 : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
sdi : out ddrctrl_in_type;
sdo : in ddrctrl_out_type;
customclk : in std_ulogic;
customdin : in std_logic_vector(custombits-1 downto 0);
customdout : out std_logic_vector(custombits-1 downto 0);
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic
);
end;
architecture rtl of ddr2phy_wrap is
signal lddr_clk,lddr_clkb: std_logic_vector(nclk-1 downto 0);
signal lddr_clk_fb_out,lddr_clk_fb: std_ulogic;
signal lddr_cke,lddr_csb,lddr_odt: std_logic_vector(ncs-1 downto 0);
signal lddr_web,lddr_rasb,lddr_casb: std_ulogic;
signal lddr_dm,lddr_dqs_in,lddr_dqs_out,lddr_dqs_oen: std_logic_vector((dbits+padbits+chkbits)/8-1 downto 0);
signal lddr_ad: std_logic_vector(abits-1 downto 0);
signal lddr_ba: std_logic_vector(1+eightbanks downto 0);
signal lddr_dq_in,lddr_dq_out,lddr_dq_oen: std_logic_vector(dbits+padbits+chkbits-1 downto 0);
begin
-- Instantiate PHY without pads via other wrapper
w0: ddr2phy_wrap_cbd_wo_pads
generic map (tech,MHz,rstdelay,dbits,padbits,clk_mul,clk_div,
ddelayb0,ddelayb1,ddelayb2,ddelayb3,ddelayb4,ddelayb5,ddelayb6,ddelayb7,
cbdelayb0,cbdelayb1,cbdelayb2,cbdelayb3,
numidelctrl,norefclk,odten,rskew,
eightbanks,dqsse,abits,nclk,ncs,chkbits,resync,custombits,scantest)
port map (
rst,clk,clkref200,clkout,clkoutret,clkresync,lock,
lddr_clk,lddr_clkb,lddr_clk_fb_out,lddr_clk_fb,
lddr_cke,lddr_csb,lddr_web,lddr_rasb,lddr_casb,lddr_dm,
lddr_dqs_in,lddr_dqs_out,lddr_dqs_oen,
lddr_ad,lddr_ba,lddr_dq_in,lddr_dq_out,lddr_dq_oen,
lddr_odt,
sdi,sdo,customclk,customdin,customdout,testen,testrst,scanen,testoen);
-- Instantiate pads for control signals and data bus
p0: ddr2pads
generic map (tech,dbits+padbits,eightbanks,dqsse,abits,nclk,ncs,ctrl2en)
port map (
ddr_clk,ddr_clkb,ddr_clk_fb_out,ddr_clk_fb,
ddr_cke,ddr_csb,ddr_web,ddr_rasb,ddr_casb,
ddr_dm,ddr_dqs,ddr_dqsn,ddr_ad,ddr_ba,ddr_dq,ddr_odt,
ddr_web2,ddr_rasb2,ddr_casb2,ddr_ad2,ddr_ba2,
lddr_clk,lddr_clkb,lddr_clk_fb_out,lddr_clk_fb,
lddr_cke,lddr_csb,lddr_web,lddr_rasb,lddr_casb,
lddr_dm(dbits/8+padbits/8-1 downto 0),
lddr_dqs_in(dbits/8+padbits/8-1 downto 0),
lddr_dqs_out(dbits/8+padbits/8-1 downto 0),
lddr_dqs_oen(dbits/8+padbits/8-1 downto 0),
lddr_ad,lddr_ba,
lddr_dq_in(dbits+padbits-1 downto 0),
lddr_dq_out(dbits+padbits-1 downto 0),
lddr_dq_oen(dbits+padbits-1 downto 0),
lddr_odt);
-- Instantiate pads for checkbit bus
cbdqpad: iopadvv
generic map (tech => tech, slew => 1, level => sstl18_ii, width => chkbits)
port map (pad => ddr_cbdq,
i => lddr_dq_out(dbits+padbits+chkbits-1 downto dbits+padbits),
en => lddr_dq_oen(dbits+padbits+chkbits-1 downto dbits+padbits),
o => lddr_dq_in(dbits+padbits+chkbits-1 downto dbits+padbits));
cbdqmpad: outpadv
generic map (tech => tech, slew => 1, level => sstl18_i, width => chkbits/8)
port map (pad => ddr_cbdm,
i => lddr_dm(dbits/8+padbits/8+chkbits/8-1 downto dbits/8+padbits/8));
cbdqspad: iopad_dsvv
generic map (tech => tech, slew => 1, level => sstl18_ii, width => chkbits/8)
port map (padp => ddr_cbdqs, padn => ddr_cbdqsn,
i => lddr_dqs_out(dbits/8+padbits/8+chkbits/8-1 downto dbits/8+padbits/8),
en => lddr_dqs_oen(dbits/8+padbits/8+chkbits/8-1 downto dbits/8+padbits/8),
o => lddr_dqs_in(dbits/8+padbits/8+chkbits/8-1 downto dbits/8+padbits/8));
end;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.ddrpkg.all;
------------------------------------------------------------------
-- DDR2 PHY with checkbits merged on data bus --------------------
------------------------------------------------------------------
entity ddr2phy_wrap_cbd is
generic (tech : integer := virtex2; MHz : integer := 100;
rstdelay : integer := 200; dbits : integer := 16; padbits : integer := 0;
clk_mul : integer := 2 ; clk_div : integer := 2;
ddelayb0 : integer := 0; ddelayb1 : integer := 0; ddelayb2 : integer := 0;
ddelayb3 : integer := 0; ddelayb4 : integer := 0; ddelayb5 : integer := 0;
ddelayb6 : integer := 0; ddelayb7 : integer := 0;
cbdelayb0 : integer := 0; cbdelayb1: integer := 0; cbdelayb2: integer := 0;
cbdelayb3 : integer := 0;
numidelctrl : integer := 4; norefclk : integer := 0; odten : integer := 0;
rskew : integer := 0; eightbanks : integer range 0 to 1 := 0;
dqsse : integer range 0 to 1 := 0;
abits : integer := 14; nclk : integer := 3; ncs : integer := 2;
chkbits : integer := 0; ctrl2en : integer := 0;
resync : integer := 0; custombits: integer := 8; extraio : integer := 0;
scantest : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkref200 : in std_logic; -- input 200MHz clock
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic; -- system clock return
clkresync : in std_ulogic;
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (extraio+(dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs
ddr_dqsn : inout std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits+padbits+chkbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(ncs-1 downto 0);
ddr_web2 : out std_ulogic; -- ddr write enable
ddr_rasb2 : out std_ulogic; -- ddr ras
ddr_casb2 : out std_ulogic; -- ddr cas
ddr_ad2 : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba2 : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
sdi : out ddrctrl_in_type;
sdo : in ddrctrl_out_type;
customclk : in std_ulogic;
customdin : in std_logic_vector(custombits-1 downto 0);
customdout : out std_logic_vector(custombits-1 downto 0);
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic;
oct_rdn : in std_logic := '0';
oct_rup : in std_logic := '0'
);
end;
architecture rtl of ddr2phy_wrap_cbd is
function ddr_widthconv(x: std_logic_vector; ow: integer) return std_logic_vector is
variable r: std_logic_vector(2*ow-1 downto 0);
constant iw: integer := x'length/2;
begin
r := (others => '0');
if iw <= ow then
r(iw+ow-1 downto ow) := x(2*iw-1 downto iw);
r(iw-1 downto 0) := x(iw-1 downto 0);
else
r := x(iw+ow-1 downto iw) & x(ow-1 downto 0);
end if;
return r;
end;
function sdr_widthconv(x: std_logic_vector; ow: integer) return std_logic_vector is
variable r: std_logic_vector(ow-1 downto 0);
constant iw: integer := x'length;
variable xd : std_logic_vector(iw-1 downto 0);
begin
r := (others => '0'); xd := x;
if iw >= ow then
r := xd(ow-1 downto 0);
else
r(iw-1 downto 0) := xd;
end if;
return r;
end;
function ddrmerge(a,b: std_logic_vector) return std_logic_vector is
constant aw: integer := a'length/2;
constant bw: integer := b'length/2;
begin
return a(2*aw-1 downto aw) & b(2*bw-1 downto bw) & a(aw-1 downto 0) & b(bw-1 downto 0);
end;
type int_array is array (natural range <>) of integer;
constant delays: int_array(0 to 7) := (ddelayb0,ddelayb1,ddelayb2,ddelayb3,
ddelayb4,ddelayb5,ddelayb6,ddelayb7);
constant cbdelays: int_array(0 to 11) := (cbdelayb0,cbdelayb1,cbdelayb2,cbdelayb3,0,0,0,0,0,0,0,0);
constant cbddelays: int_array(0 to 11) :=
delays(0 to (dbits+padbits)/8-1) & cbdelays(0 to 11-(dbits+padbits)/8);
signal dqin: std_logic_vector(2*(chkbits+dbits+padbits)-1 downto 0);
signal dqout: std_logic_vector(2*(chkbits+dbits+padbits)-1 downto 0);
signal dqm: std_logic_vector((chkbits+dbits+padbits)/4-1 downto 0);
signal cal_en: std_logic_vector((chkbits+dbits+padbits)/8-1 downto 0);
signal cal_inc: std_logic_vector((chkbits+dbits+padbits)/8-1 downto 0);
signal odt,csn,cke: std_logic_vector(ncs-1 downto 0);
begin
-- Merge checkbit and data buses
comb: process(sdo,dqin)
variable dq: std_logic_vector(2*dbits-1 downto 0);
variable dqpad: std_logic_vector(2*(dbits+padbits)-1 downto 0);
variable cb: std_logic_vector(dbits-1 downto 0);
variable cbpad: std_logic_vector(2*chkbits downto 0); -- Extra bit to handle chkbits=0
variable dqcb: std_logic_vector(2*(dbits+padbits+chkbits)-1 downto 0);
variable dm: std_logic_vector(dbits/4-1 downto 0);
variable dmpad: std_logic_vector((dbits+padbits)/4-1 downto 0);
variable cbdm: std_logic_vector(dbits/8-1 downto 0);
variable cbdmpad: std_logic_vector(chkbits/4 downto 0);
variable dqcbdm: std_logic_vector((dbits+padbits+chkbits)/4-1 downto 0);
variable vcsn,vodt,vcke: std_logic_vector(ncs-1 downto 0);
begin
dq := sdo.data(2*dbits-1 downto 0);
dqpad := ddr_widthconv(dq, dbits+padbits );
if chkbits > 0 then
cb := sdo.cb(dbits-1 downto 0);
cbpad := '0' & ddr_widthconv(cb, chkbits);
dqcb := ddrmerge(cbpad(2*chkbits-1 downto 0), dqpad);
else
dqcb := dqpad;
end if;
dqout <= dqcb;
dqcb := dqin;
if chkbits > 0 then
cbpad := '0' & dqin(2*(chkbits+dbits+padbits)-1 downto 2*(dbits+padbits)+chkbits) &
dqin(chkbits+dbits+padbits-1 downto dbits+padbits);
cb := ddr_widthconv(cbpad(2*chkbits-1 downto 0), dbits/2);
else
cb := (others => '0');
end if;
dq := dqcb(2*dbits+chkbits+padbits-1 downto dbits+chkbits+padbits) &
dqcb(dbits-1 downto 0);
sdi.cb(dbits-1 downto 0) <= cb;
sdi.data(2*dbits-1 downto 0) <= dq;
if sdi.cb'length > dbits then
sdi.cb(sdi.cb'length-1 downto dbits) <= (others => '0');
end if;
if sdi.data'length > 2*dbits then
sdi.data(sdi.data'length-1 downto 2*dbits) <= (others => '0');
end if;
dm := sdo.dqm(dbits/4-1 downto 0);
dmpad := ddr_widthconv(dm, (dbits+padbits)/8);
if chkbits > 0 then
cbdm := sdo.cbdqm(dbits/8-1 downto 0);
cbdmpad := '0' & ddr_widthconv(cbdm(dbits/8-1 downto 0), chkbits/8);
dqcbdm := ddrmerge(cbdmpad(chkbits/4-1 downto 0), dmpad);
else
dqcbdm := dmpad;
end if;
dqm <= dqcbdm;
cal_en <= sdr_widthconv(sdo.cbcal_en (dbits/16-1 downto 0) &
sdo.cal_en (dbits/8-1 downto 0), (dbits+padbits+chkbits)/8 );
cal_inc <= sdr_widthconv(sdo.cbcal_inc(dbits/16-1 downto 0) &
sdo.cal_inc(dbits/8-1 downto 0), (dbits+padbits+chkbits)/8 );
vcsn := (others => '1');
for x in 0 to ncs-1 loop
if x<2 then
vcsn(x) := sdo.sdcsn(x);
end if;
vodt(x) := sdo.odt(x mod 2);
vcke(x) := sdo.sdcke(x mod 2);
end loop;
csn <= vcsn;
odt <= vodt;
cke <= vcke;
end process;
-- Phy instantiation
ddr_phy0 : ddr2phy
generic map (tech => tech, MHz => MHz, rstdelay => rstdelay
-- reduce 200 us start-up delay during simulation
-- pragma translate_off
/ 200
-- pragma translate_on
, dbits => dbits+padbits+chkbits,clk_mul => clk_mul, clk_div => clk_div,
ddelayb0 => cbddelays(0), ddelayb1 => cbddelays(1), ddelayb2 => cbddelays(2),
ddelayb3 => cbddelays(3), ddelayb4 => cbddelays(4), ddelayb5 => cbddelays(5),
ddelayb6 => cbddelays(6), ddelayb7 => cbddelays(7), ddelayb8 => cbddelays(8),
ddelayb9 => cbddelays(9), ddelayb10 => cbddelays(10), ddelayb11 => cbddelays(11),
numidelctrl => numidelctrl, norefclk => norefclk, rskew => rskew,
eightbanks => eightbanks, dqsse => dqsse,
abits => abits, nclk => nclk, ncs => ncs,
ctrl2en => ctrl2en, resync => resync, custombits => custombits, extraio => extraio,
scantest => scantest)
port map (
rst, clk, clkref200, clkout, clkoutret, clkresync, lock,
ddr_clk, ddr_clkb, ddr_clk_fb_out, ddr_clk_fb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_dqsn, ddr_ad, ddr_ba, ddr_dq, ddr_odt,
sdo.address(abits-1 downto 0), sdo.ba,
dqin, dqout,
dqm, sdo.bdrive, sdo.nbdrive, sdo.bdrive, sdo.qdrive,
sdo.rasn, sdo.casn, sdo.sdwen, csn, cke,
cal_en, cal_inc,
sdo.cal_pll, sdo.cal_rst, odt, sdo.oct, sdo.read_pend,
sdo.regwdata, sdo.regwrite, sdi.regrdata, sdi.datavalid,
customclk, customdin, customdout,
ddr_web2, ddr_rasb2, ddr_casb2, ddr_ad2, ddr_ba2,
testen, testrst, scanen, testoen,
oct_rdn, oct_rup
);
sdi.writereq <= '0';
end;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.ddrpkg.all;
------------------------------------------------------------------
-- DDR2 PHY with checkbits merged on data bus, pads not in phy --
------------------------------------------------------------------
entity ddr2phy_wrap_cbd_wo_pads is
generic (tech : integer := virtex2; MHz : integer := 100;
rstdelay : integer := 200; dbits : integer := 16; padbits : integer := 0;
clk_mul : integer := 2 ; clk_div : integer := 2;
ddelayb0 : integer := 0; ddelayb1 : integer := 0; ddelayb2 : integer := 0;
ddelayb3 : integer := 0; ddelayb4 : integer := 0; ddelayb5 : integer := 0;
ddelayb6 : integer := 0; ddelayb7 : integer := 0;
cbdelayb0 : integer := 0; cbdelayb1: integer := 0; cbdelayb2: integer := 0;
cbdelayb3 : integer := 0;
numidelctrl : integer := 4; norefclk : integer := 0; odten : integer := 0;
rskew : integer := 0; eightbanks : integer range 0 to 1 := 0;
dqsse : integer range 0 to 1 := 0;
abits : integer := 14; nclk : integer := 3; ncs : integer := 2;
chkbits : integer := 0; resync : integer := 0; custombits: integer := 8;
scantest : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkref200 : in std_logic; -- input 200MHz clock
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic; -- system clock return
clkresync : in std_ulogic;
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dm
ddr_dqs_in : in std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs
ddr_dqs_out : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs
ddr_dqs_oen : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq_in : in std_logic_vector (dbits+padbits+chkbits-1 downto 0); -- ddr data
ddr_dq_out : out std_logic_vector (dbits+padbits+chkbits-1 downto 0); -- ddr data
ddr_dq_oen : out std_logic_vector (dbits+padbits+chkbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(ncs-1 downto 0);
sdi : out ddrctrl_in_type;
sdo : in ddrctrl_out_type;
customclk : in std_ulogic;
customdin : in std_logic_vector(custombits-1 downto 0);
customdout : out std_logic_vector(custombits-1 downto 0);
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic);
end;
architecture rtl of ddr2phy_wrap_cbd_wo_pads is
function ddr_widthconv(x: std_logic_vector; ow: integer) return std_logic_vector is
variable r: std_logic_vector(2*ow-1 downto 0);
constant iw: integer := x'length/2;
begin
r := (others => '0');
if iw <= ow then
r(iw+ow-1 downto ow) := x(2*iw-1 downto iw);
r(iw-1 downto 0) := x(iw-1 downto 0);
else
r := x(iw+ow-1 downto iw) & x(ow-1 downto 0);
end if;
return r;
end;
function sdr_widthconv(x: std_logic_vector; ow: integer) return std_logic_vector is
variable r: std_logic_vector(ow-1 downto 0);
constant iw: integer := x'length;
variable xd : std_logic_vector(iw-1 downto 0);
begin
r := (others => '0'); xd := x;
if iw >= ow then
r := xd(ow-1 downto 0);
else
r(iw-1 downto 0) := xd;
end if;
return r;
end;
function ddrmerge(a,b: std_logic_vector) return std_logic_vector is
constant aw: integer := a'length/2;
constant bw: integer := b'length/2;
begin
return a(2*aw-1 downto aw) & b(2*bw-1 downto bw) & a(aw-1 downto 0) & b(bw-1 downto 0);
end;
type int_array is array (natural range <>) of integer;
constant delays: int_array(0 to 7) := (ddelayb0,ddelayb1,ddelayb2,ddelayb3,
ddelayb4,ddelayb5,ddelayb6,ddelayb7);
constant cbdelays: int_array(0 to 11) := (cbdelayb0,cbdelayb1,cbdelayb2,cbdelayb3,0,0,0,0,0,0,0,0);
constant cbddelays: int_array(0 to 11) :=
delays(0 to (dbits+padbits)/8-1) & cbdelays(0 to 11-(dbits+padbits)/8);
signal dqin: std_logic_vector(2*(chkbits+dbits+padbits)-1 downto 0);
signal dqout: std_logic_vector(2*(chkbits+dbits+padbits)-1 downto 0);
signal dqm: std_logic_vector((chkbits+dbits+padbits)/4-1 downto 0);
signal cal_en: std_logic_vector((chkbits+dbits+padbits)/8-1 downto 0);
signal cal_inc: std_logic_vector((chkbits+dbits+padbits)/8-1 downto 0);
signal odt,csn,cke: std_logic_vector(ncs-1 downto 0);
signal gnd : std_logic_vector(chkbits*2-1 downto 0);
begin
gnd <= (others => '0');
-- Merge checkbit and data buses
comb: process(sdo,dqin)
variable dq: std_logic_vector(2*dbits-1 downto 0);
variable dqpad: std_logic_vector(2*(dbits+padbits)-1 downto 0);
variable cb: std_logic_vector(dbits-1 downto 0);
variable cbpad: std_logic_vector(2*chkbits downto 0); -- Extra bit to handle chkbits=0
variable dqcb: std_logic_vector(2*(dbits+padbits+chkbits)-1 downto 0);
variable dm: std_logic_vector(dbits/4-1 downto 0);
variable dmpad: std_logic_vector((dbits+padbits)/4-1 downto 0);
variable cbdm: std_logic_vector(dbits/8-1 downto 0);
variable cbdmpad: std_logic_vector(chkbits/4 downto 0);
variable dqcbdm: std_logic_vector((dbits+padbits+chkbits)/4-1 downto 0);
variable vcsn,vodt,vcke: std_logic_vector(ncs-1 downto 0);
begin
dq := sdo.data(2*dbits-1 downto 0);
dqpad := ddr_widthconv(dq, dbits+padbits );
if chkbits > 0 then
cb := sdo.cb(dbits-1 downto 0);
cbpad := '0' & ddr_widthconv(cb, chkbits);
dqcb := ddrmerge(cbpad(2*chkbits-1 downto 0), dqpad);
else
dqcb := dqpad;
end if;
dqout <= dqcb;
dqcb := dqin;
if chkbits > 0 then
cbpad := '0' & dqin(2*(chkbits+dbits+padbits)-1 downto 2*(dbits+padbits)+chkbits) &
dqin(chkbits+dbits+padbits-1 downto dbits+padbits);
cb := ddr_widthconv(cbpad(2*chkbits-1 downto 0), dbits/2);
else
cb := (others => '0');
end if;
dq := dqcb(2*dbits+chkbits+padbits-1 downto dbits+chkbits+padbits) &
dqcb(dbits-1 downto 0);
sdi.cb(dbits-1 downto 0) <= cb;
sdi.data(2*dbits-1 downto 0) <= dq;
if sdi.cb'length > dbits then
sdi.cb(sdi.cb'length-1 downto dbits) <= (others => '0');
end if;
if sdi.data'length > 2*dbits then
sdi.data(sdi.data'length-1 downto 2*dbits) <= (others => '0');
end if;
dm := sdo.dqm(dbits/4-1 downto 0);
dmpad := ddr_widthconv(dm, (dbits+padbits)/8);
if chkbits > 0 then
cbdm := sdo.cbdqm(dbits/8-1 downto 0);
cbdmpad := '0' & ddr_widthconv(cbdm(dbits/8-1 downto 0), chkbits/8);
dqcbdm := ddrmerge(cbdmpad(chkbits/4-1 downto 0), dmpad);
else
dqcbdm := dmpad;
end if;
dqm <= dqcbdm;
cal_en <= sdr_widthconv(sdo.cbcal_en (dbits/16-1 downto 0) &
sdo.cal_en (dbits/8-1 downto 0), (dbits+padbits+chkbits)/8 );
cal_inc <= sdr_widthconv(sdo.cbcal_inc(dbits/16-1 downto 0) &
sdo.cal_inc(dbits/8-1 downto 0), (dbits+padbits+chkbits)/8 );
vcsn := (others => '1');
for x in 0 to ncs-1 loop
if x<2 then
vcsn(x) := sdo.sdcsn(x);
end if;
vodt(x) := sdo.odt(x mod 2);
vcke(x) := sdo.sdcke(x mod 2);
end loop;
csn <= vcsn;
odt <= vodt;
cke <= vcke;
end process;
-- Phy instantiation
ddr_phy0 : ddr2phy_wo_pads
generic map (tech => tech, MHz => MHz, rstdelay => rstdelay
-- reduce 200 us start-up delay during simulation
-- pragma translate_off
/ 200
-- pragma translate_on
, dbits => dbits+padbits+chkbits,clk_mul => clk_mul, clk_div => clk_div,
ddelayb0 => cbddelays(0), ddelayb1 => cbddelays(1), ddelayb2 => cbddelays(2),
ddelayb3 => cbddelays(3), ddelayb4 => cbddelays(4), ddelayb5 => cbddelays(5),
ddelayb6 => cbddelays(6), ddelayb7 => cbddelays(7), ddelayb8 => cbddelays(8),
ddelayb9 => cbddelays(9), ddelayb10 => cbddelays(10), ddelayb11 => cbddelays(11),
numidelctrl => numidelctrl, norefclk => norefclk, rskew => rskew,
eightbanks => eightbanks, dqsse => dqsse,
abits => abits, nclk => nclk, ncs => ncs, resync => resync, custombits => custombits,
scantest => scantest)
port map (
rst => rst, clk => clk, clkref => clkref200, clkout => clkout, clkoutret => clkoutret,
clkresync => clkresync, lock => lock,
ddr_clk => ddr_clk, ddr_clkb => ddr_clkb, ddr_clk_fb_out => ddr_clk_fb_out, ddr_clk_fb => ddr_clk_fb,
ddr_cke => ddr_cke, ddr_csb => ddr_csb, ddr_web => ddr_web, ddr_rasb => ddr_rasb, ddr_casb => ddr_casb,
ddr_dm => ddr_dm, ddr_dqs_in => ddr_dqs_in, ddr_dqs_out => ddr_dqs_out, ddr_dqs_oen => ddr_dqs_oen,
ddr_ad => ddr_ad, ddr_ba => ddr_ba, ddr_dq_in => ddr_dq_in, ddr_dq_out => ddr_dq_out, ddr_dq_oen => ddr_dq_oen,
ddr_odt => ddr_odt,
addr => sdo.address(abits-1 downto 0), ba => sdo.ba, dqin => dqin, dqout => dqout, dm => dqm,
oen => sdo.bdrive, noen => sdo.nbdrive,
dqs => sdo.bdrive, dqsoen => sdo.qdrive, rasn => sdo.rasn, casn => sdo.casn, wen => sdo.sdwen, csn => csn,
cke => cke, cal_en => cal_en, cal_inc => cal_inc, cal_pll => sdo.cal_pll, cal_rst => sdo.cal_rst, odt => odt,
oct => sdo.oct, read_pend => sdo.read_pend, regwdata => sdo.regwdata, regwrite => sdo.regwrite,
regrdata => sdi.regrdata, dqin_valid => sdi.datavalid,
customclk => customclk, customdin => customdin, customdout => customdout,
testen => testen, testrst => testrst, scanen => scanen, testoen => testoen
);
sdi.writereq <= '0';
end;
------------------------------------------------------------------
-- LPDDR2/LPDDR3 PHY with checkbits merged on data bus, no pads --
------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.ddrpkg.all;
entity lpddr2phy_wrap_cbd_wo_pads is
generic (tech : integer := virtex2;
dbits : integer := 16;
nclk : integer := 3;
ncs : integer := 2;
chkbits : integer := 0;
padbits : integer := 0;
scantest : integer := 0);
port (
rst : in std_ulogic;
clkin : in std_ulogic; -- input clock
clkin2 : in std_ulogic; -- input clock
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic; -- system clock return
clkout2 : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_ca : out std_logic_vector(9 downto 0); -- ddr cmd/addr
ddr_dm : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dm
ddr_dqs_in : in std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs
ddr_dqs_out : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs
ddr_dqs_oen : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs
ddr_dq_in : in std_logic_vector (dbits+padbits+chkbits-1 downto 0); -- ddr data
ddr_dq_out : out std_logic_vector (dbits+padbits+chkbits-1 downto 0); -- ddr data
ddr_dq_oen : out std_logic_vector (dbits+padbits+chkbits-1 downto 0);
sdi : out ddrctrl_in_type;
sdo : in ddrctrl_out_type;
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic);
end;
architecture rtl of lpddr2phy_wrap_cbd_wo_pads is
function ddr_widthconv(x: std_logic_vector; ow: integer) return std_logic_vector is
variable r: std_logic_vector(2*ow-1 downto 0);
constant iw: integer := x'length/2;
begin
r := (others => '0');
if iw <= ow then
r(iw+ow-1 downto ow) := x(2*iw-1 downto iw);
r(iw-1 downto 0) := x(iw-1 downto 0);
else
r := x(iw+ow-1 downto iw) & x(ow-1 downto 0);
end if;
return r;
end;
function sdr_widthconv(x: std_logic_vector; ow: integer) return std_logic_vector is
variable r: std_logic_vector(ow-1 downto 0);
constant iw: integer := x'length;
variable xd : std_logic_vector(iw-1 downto 0);
begin
r := (others => '0'); xd := x;
if iw >= ow then
r := xd(ow-1 downto 0);
else
r(iw-1 downto 0) := xd;
end if;
return r;
end;
function ddrmerge(a,b: std_logic_vector) return std_logic_vector is
constant aw: integer := a'length/2;
constant bw: integer := b'length/2;
begin
return a(2*aw-1 downto aw) & b(2*bw-1 downto bw) & a(aw-1 downto 0) & b(bw-1 downto 0);
end;
signal dqin: std_logic_vector(2*(chkbits+dbits+padbits)-1 downto 0);
signal dqout: std_logic_vector(2*(chkbits+dbits+padbits)-1 downto 0);
signal dqm: std_logic_vector((chkbits+dbits+padbits)/4-1 downto 0);
signal odt,csn,cke: std_logic_vector(ncs-1 downto 0);
signal sdck: std_logic_vector(nclk-1 downto 0);
signal gnd : std_logic_vector(chkbits*2-1 downto 0);
begin
gnd <= (others => '0');
-- Merge checkbit and data buses
comb: process(sdo,dqin)
variable dq: std_logic_vector(2*dbits-1 downto 0);
variable dqpad: std_logic_vector(2*(dbits+padbits)-1 downto 0);
variable cb: std_logic_vector(dbits-1 downto 0);
variable cbpad: std_logic_vector(2*chkbits downto 0); -- Extra bit to handle chkbits=0
variable dqcb: std_logic_vector(2*(dbits+padbits+chkbits)-1 downto 0);
variable dm: std_logic_vector(dbits/4-1 downto 0);
variable dmpad: std_logic_vector((dbits+padbits)/4-1 downto 0);
variable cbdm: std_logic_vector(dbits/8-1 downto 0);
variable cbdmpad: std_logic_vector(chkbits/4 downto 0);
variable dqcbdm: std_logic_vector((dbits+padbits+chkbits)/4-1 downto 0);
variable vcsn,vcke: std_logic_vector(ncs-1 downto 0);
variable vsdck: std_logic_vector(nclk-1 downto 0);
begin
dq := sdo.data(2*dbits-1 downto 0);
dqpad := ddr_widthconv(dq, dbits+padbits );
if chkbits > 0 then
cb := sdo.cb(dbits-1 downto 0);
cbpad := '0' & ddr_widthconv(cb, chkbits);
dqcb := ddrmerge(cbpad(2*chkbits-1 downto 0), dqpad);
else
dqcb := dqpad;
end if;
dqout <= dqcb;
dqcb := dqin;
if chkbits > 0 then
cbpad := '0' & dqin(2*(chkbits+dbits+padbits)-1 downto 2*(dbits+padbits)+chkbits) &
dqin(chkbits+dbits+padbits-1 downto dbits+padbits);
cb := ddr_widthconv(cbpad(2*chkbits-1 downto 0), dbits/2);
else
cb := (others => '0');
end if;
dq := dqcb(2*dbits+chkbits+padbits-1 downto dbits+chkbits+padbits) &
dqcb(dbits-1 downto 0);
sdi.cb(dbits-1 downto 0) <= cb;
sdi.data(2*dbits-1 downto 0) <= dq;
if sdi.cb'length > dbits then
sdi.cb(sdi.cb'length-1 downto dbits) <= (others => '0');
end if;
if sdi.data'length > 2*dbits then
sdi.data(sdi.data'length-1 downto 2*dbits) <= (others => '0');
end if;
dm := sdo.dqm(dbits/4-1 downto 0);
dmpad := ddr_widthconv(dm, (dbits+padbits)/8);
if chkbits > 0 then
cbdm := sdo.cbdqm(dbits/8-1 downto 0);
cbdmpad := '0' & ddr_widthconv(cbdm(dbits/8-1 downto 0), chkbits/8);
dqcbdm := ddrmerge(cbdmpad(chkbits/4-1 downto 0), dmpad);
else
dqcbdm := dmpad;
end if;
dqm <= dqcbdm;
vcsn := (others => '1');
for x in 0 to ncs-1 loop
if x<2 then
vcsn(x) := sdo.sdcsn(x);
end if;
vcke(x) := sdo.sdcke(x mod 2);
end loop;
for x in 0 to nclk-1 loop
vsdck(x) := sdo.sdck(x mod 2);
end loop;
csn <= vcsn;
cke <= vcke;
sdck <= vsdck;
end process;
-- Phy instantiation
ddr_phy0 : lpddr2phy_wo_pads
generic map (
tech => tech,
dbits => dbits+padbits+chkbits,
nclk => nclk,
ncs => ncs,
clkratio => 1,
scantest => scantest)
port map (
rst => rst,
clkin => clkin,
clkin2 => clkin2,
clkout => clkout,
clkoutret => clkoutret,
clkout2 => clkout2,
lock => lock,
ddr_clk => ddr_clk,
ddr_clkb => ddr_clkb,
ddr_cke => ddr_cke,
ddr_csb => ddr_csb,
ddr_ca => ddr_ca,
ddr_dm => ddr_dm,
ddr_dqs_in => ddr_dqs_in,
ddr_dqs_out => ddr_dqs_out,
ddr_dqs_oen => ddr_dqs_oen,
ddr_dq_in => ddr_dq_in,
ddr_dq_out => ddr_dq_out,
ddr_dq_oen => ddr_dq_oen,
ca => sdo.ca,
cke => cke,
csn => csn,
dqin => dqin,
dqout => dqout,
dm => dqm,
ckstop => sdo.sdck(0),
boot => sdo.boot,
wrpend => sdo.wrpend,
rdpend => sdo.read_pend,
wrreq(0) => sdi.writereq,
rdvalid(0) => sdi.datavalid,
refcal => '0',
refcalwu => '0',
refcaldone => open,
phycmd => "00000000",
phycmden => '0',
phycmdin => x"00000000",
phycmdout => open,
testen => '0',
testrst => '1',
scanen => '0',
testoen => '0'
);
sdi.regrdata <= (others => '0');
end;
| gpl-3.0 | 0397a6fb83ccb94a7542ea9706bfe547 | 0.570129 | 3.390275 | false | false | false | false |
pwsoft/fpga_examples | rtl/chameleon/chameleon_autofire.vhd | 1 | 2,632 | -- -----------------------------------------------------------------------
--
-- Turbo Chameleon
--
-- Multi purpose FPGA expansion for the Commodore 64 computer
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2017 by Peter Wendrich ([email protected])
-- http://www.syntiac.com/chameleon.html
--
-- This source file is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- -----------------------------------------------------------------------
--
-- Joystick autofire logic
--
-- -----------------------------------------------------------------------
-- autofire_period - Number of micro-seconds between toggling of output.
-- Autofire rate in Hz is 1000000/(2*autofire_period)
-- -----------------------------------------------------------------------
-- clk - system clock input
-- ena_1mhz - Enable must be high for one clk cycle each microsecond
-- button_n - Fire button input from joystick (low active)
-- autofire_n - Auto-fire outout (low active)
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
-- -----------------------------------------------------------------------
entity chameleon_autofire is
generic (
autofire_period : integer := 75000
);
port (
clk : in std_logic;
ena_1mhz : in std_logic;
button_n : in std_logic;
autofire_n : out std_logic
);
end entity;
-- -----------------------------------------------------------------------
architecture rtl of chameleon_autofire is
signal counter : integer range 0 to autofire_period;
signal autofire_reg : std_logic := '1';
begin
autofire_n <= autofire_reg;
process(clk)
begin
if rising_edge(clk) then
if button_n = '1' then
counter <= 0;
autofire_reg <= '1';
elsif counter = 0 then
counter <= autofire_period;
autofire_reg <= not autofire_reg;
elsif ena_1mhz = '1' then
counter <= counter - 1;
end if;
end if;
end process;
end architecture;
| lgpl-2.1 | 85b95a2bd3e0196a1cc9bd0e41c2d693 | 0.540274 | 4.224719 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/leon3v3/mmu_dcache.vhd | 1 | 68,554 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: mmu_dcache
-- File: mmu_dcache.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Modified: Edvin Catovic - Gaisler Research
-- Description: This unit implements the data cache controller.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.amba.all;
use grlib.sparc.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.libiu.all;
use gaisler.libcache.all;
use gaisler.libmmu.all;
use gaisler.mmuconfig.all;
use gaisler.mmuiface.all;
entity mmu_dcache is
generic (
dsu : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 0;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 7 := 0;
dlram : integer range 0 to 2 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
ilram : integer range 0 to 2 := 0;
ilramstart : integer range 0 to 255 := 16#8e#;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
memtech : integer range 0 to NTECH := 0;
cached : integer := 0;
mmupgsz : integer range 0 to 5 := 0;
smp : integer := 0;
mmuen : integer := 0;
icen : integer range 0 to 1 := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
dci : in dcache_in_type;
dco : out dcache_out_type;
ico : in icache_out_type;
mcdi : out memory_dc_in_type;
mcdo : in memory_dc_out_type;
ahbsi : in ahb_slv_in_type;
dcrami : out dcram_in_type;
dcramo : in dcram_out_type;
fpuholdn : in std_ulogic;
mmudci : out mmudc_in_type;
mmudco : in mmudc_out_type;
sclk : in std_ulogic;
ahbso : in ahb_slv_out_vector
);
end;
architecture rtl of mmu_dcache is
constant M_EN : boolean := (mmuen = 1);
constant DSNOOP2 : integer := dsnoop mod 4;
constant DSNOOPSEP : boolean := (dsnoop > 3);
constant M_TLB_TYPE : integer range 0 to 1 := -- either split or combined
conv_integer(conv_std_logic_vector(tlb_type, 2) and conv_std_logic_vector(1, 2));
constant M_TLB_FASTWRITE : integer range 0 to 3 := -- fast writebuffer
conv_integer(conv_std_logic_vector(tlb_type, 2) and conv_std_logic_vector(2, 2));
constant M_ENT_I : integer range 2 to 64 := itlbnum; -- icache tlb entries: number
constant M_ENT_ILOG : integer := log2(M_ENT_I); -- icache tlb entries: address bits
constant M_ENT_D : integer range 2 to 64 := dtlbnum; -- dcache tlb entries: number
constant M_ENT_DLOG : integer := log2(M_ENT_D); -- dcache tlb entries: address bits
constant M_ENT_C : integer range 2 to 64 := M_ENT_I; -- i/dcache tlb entries: number
constant M_ENT_CLOG : integer := M_ENT_ILOG; -- i/dcache tlb entries: address bits
constant DLINE_BITS : integer := log2(dlinesize);
constant DOFFSET_BITS : integer := 8 +log2(dsetsize) - DLINE_BITS;
constant LRR_BIT : integer := TAG_HIGH + 1;
constant TAG_LOW : integer := DOFFSET_BITS + DLINE_BITS + 2;
constant OFFSET_HIGH : integer := TAG_LOW - 1;
constant OFFSET_LOW : integer := DLINE_BITS + 2;
constant LINE_HIGH : integer := OFFSET_LOW - 1;
constant LINE_LOW : integer := 2;
constant LINE_ZERO : std_logic_vector(DLINE_BITS-1 downto 0) := (others => '0');
constant SETBITS : integer := log2x(DSETS);
constant DLRUBITS : integer := lru_table(DSETS);
constant LOCAL_RAM_START : std_logic_vector(7 downto 0) :=
conv_std_logic_vector(dlramstart, 8);
constant ILRAM_START : std_logic_vector(7 downto 0) :=
conv_std_logic_vector(ilramstart, 8);
constant DIR_BITS : integer := log2x(DSETS);
constant bend : std_logic_vector(4 downto 2) := "101";
constant DLRAM_EN : integer := conv_integer(conv_std_logic(dlram /= 0));
type rdatatype is (dtag, ddata, dddata, dctx, icache, memory,
sysr , misc, mmusnoop_dtag); -- sources during cache read
type vmasktype is (clearone, clearall, merge, tnew); -- valid bits operation
type valid_type is array (0 to DSETS-1) of std_logic_vector(dlinesize - 1 downto 0);
type write_buffer_type is record -- write buffer
addr, data1, data2 : std_logic_vector(31 downto 0);
size : std_logic_vector(1 downto 0);
asi : std_logic_vector(3 downto 0);
read : std_ulogic;
lock : std_ulogic;
lock2 : std_ulogic;
smask : std_logic_vector(DSETS-1 downto 0);-- snoop mask
end record;
type dstatetype is (idle, wread, rtrans, wwrite, wtrans, wflush,
asi_idtag, dblwrite, loadpend);
type dcache_control_type is record -- all registers
read : std_ulogic; -- access direction
size : std_logic_vector(1 downto 0); -- access size
req, burst, rburst, holdn, nomds, stpend : std_ulogic;
xaddress : std_logic_vector(31 downto 0); -- common address buffer
paddress : std_logic_vector(31 downto 0); -- physical address buffer
faddr : std_logic_vector(DOFFSET_BITS - 1 downto 0); -- flush address
efaddr : std_logic_vector(DOFFSET_BITS - 1 downto 0); -- error flush address
dstate : dstatetype; -- FSM vector
hit, valid : std_ulogic;
flush : std_ulogic; -- flush in progress
flush2 : std_ulogic; -- flush in progress
fflush : std_ulogic; -- first flush
mexc : std_ulogic; -- latched mexc
bmexc : std_ulogic; -- latched mexc from burst read
wb : write_buffer_type; -- write buffer
asi : std_logic_vector(4 downto 0);
icenable : std_ulogic; -- icache diag access
rndcnt : std_logic_vector(log2x(DSETS)-1 downto 0); -- replace counter
setrepl : std_logic_vector(log2x(DSETS)-1 downto 0); -- set to replace
lrr : std_ulogic;
dsuset : std_logic_vector(log2x(DSETS)-1 downto 0);
lock : std_ulogic;
lramrd : std_ulogic;
ilramen : std_ulogic;
cctrl : cctrltype;
cctrlwr : std_ulogic;
flushl2 : std_ulogic;
tadj, dadj, sadj : std_logic_vector(1 downto 0);
mmctrl1 : mmctrl_type1;
mmctrl1wr : std_ulogic;
pflush : std_logic;
pflushr : std_logic;
pflushaddr : std_logic_vector(VA_I_U downto VA_I_D);
pflushtyp : std_logic;
vaddr : std_logic_vector(31 downto 0);
ready : std_logic;
wbinit : std_logic;
cache : std_logic;
dlock : std_logic;
su : std_logic;
trans_op : std_logic;
flush_op : std_logic;
diag_op : std_logic;
reqst : std_logic;
set : integer range 0 to DSETS-1;
noflush : std_logic;
cmiss : std_ulogic;
end record;
type snoop_reg_type is record -- snoop control registers
snoop : std_ulogic; -- snoop access to tags
addr : std_logic_vector(TAG_HIGH downto OFFSET_LOW);-- snoop tag address
mask : std_logic_vector(DSETS-1 downto 0);-- snoop mask
snhit : std_logic_vector(0 to MAXSETS-1);
end record;
subtype lru_type is std_logic_vector(DLRUBITS-1 downto 0);
type lru_array is array (0 to 2**DOFFSET_BITS-1) of lru_type; -- lru registers
type lru_reg_type is record
write : std_ulogic;
waddr : std_logic_vector(DOFFSET_BITS-1 downto 0);
set : std_logic_vector(SETBITS-1 downto 0);
lru : lru_array;
end record;
subtype lock_type is std_logic_vector(0 to DSETS-1);
function lru_set (lru : lru_type; lock : lock_type) return std_logic_vector is
variable xlru : std_logic_vector(4 downto 0);
variable set : std_logic_vector(SETBITS-1 downto 0);
variable xset : std_logic_vector(1 downto 0);
variable unlocked : integer range 0 to DSETS-1;
begin
set := (others => '0'); xlru := (others => '0'); xset := (others => '0');
xlru(DLRUBITS-1 downto 0) := lru;
if dsetlock = 1 then
unlocked := DSETS-1;
for i in DSETS-1 downto 0 loop
if lock(i) = '0' then unlocked := i; end if;
end loop;
end if;
case DSETS is
when 2 =>
if dsetlock = 1 then
if lock(0) = '1' then xset(0) := '1'; else xset(0) := xlru(0); end if;
else
xset(0) := xlru(0);
end if;
when 3 =>
if dsetlock = 1 then
xset := conv_std_logic_vector(lru3_repl_table(conv_integer(xlru)) (unlocked), 2);
else
-- xset := conv_std_logic_vector(lru3_repl_table(conv_integer(xlru)) (0), 2);
xset := xlru(2) & (xlru(1) and not xlru(2));
end if;
when 4 =>
if dsetlock = 1 then
xset := conv_std_logic_vector(lru4_repl_table(conv_integer(xlru)) (unlocked), 2);
else
-- xset := conv_std_logic_vector(lru4_repl_table(conv_integer(xlru)) (0), 2);
xset := xlru(4 downto 3);
end if;
when others =>
end case;
set := xset(SETBITS-1 downto 0);
return(set);
end;
function lru_calc (lru : lru_type; xset : std_logic_vector) return lru_type is
variable new_lru : lru_type;
variable xnew_lru: std_logic_vector(4 downto 0);
variable xlru : std_logic_vector(4 downto 0);
variable vset: std_logic_vector(SETBITS-1 downto 0);
variable set: integer;
begin
vset := xset; set := conv_integer(vset);
new_lru := (others => '0'); xnew_lru := (others => '0');
xlru := (others => '0'); xlru(DLRUBITS-1 downto 0) := lru;
case DSETS is
when 2 =>
if set = 0 then xnew_lru(0) := '1'; else xnew_lru(0) := '0'; end if;
when 3 =>
xnew_lru(2 downto 0) := lru_3set_table(conv_integer(lru))(set);
when 4 =>
xnew_lru(4 downto 0) := lru_4set_table(conv_integer(lru))(set);
xnew_lru(SETBITS-1 downto 0) := vset;
when others =>
end case;
new_lru := xnew_lru(DLRUBITS-1 downto 0);
return(new_lru);
end;
subtype word is std_logic_vector(31 downto 0);
constant write_buffer_none : write_buffer_type := (
addr => (others => '0'),
data1 => (others => '0'),
data2 => (others => '0'),
size => (others => '0'),
asi => (others => '0'),
read => '0',
lock => '0',
lock2 => '0',
smask => (others => '0')
);
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant RRES : dcache_control_type := (
read => '0',
size => (others => '0'),
req => '0',
burst => '0',
rburst => '0',
holdn => '1',
nomds => '0',
stpend => '0',
xaddress => (others => '0'),
paddress => (others => '0'),
faddr => (others => '0'),
efaddr => (others => '0'),
dstate => idle,
hit => '0',
valid => '0',
flush => '0',
flush2 => '1',
fflush => '1',
mexc => '0',
bmexc => '0',
wb => write_buffer_none,
asi => (others => '0'),
icenable => '0',
rndcnt => (others => '0'),
setrepl => (others => '0'),
lrr => '0',
dsuset => (others => '0'),
lock => '0',
lramrd => '0',
ilramen => '0',
cctrl => cctrl_none,
cctrlwr => '0',
flushl2 => '0',
tadj => (others => '0'),
dadj => (others => '0'),
sadj => (others => '0'),
mmctrl1 => mmctrl_type1_none,
mmctrl1wr => '0',
pflush => '0',
pflushr => '0',
pflushaddr => (others => '0'),
pflushtyp => '0',
vaddr => (others => '0'),
ready => '0',
wbinit => '0',
cache => '0',
dlock => '0',
su => '0',
trans_op => '0',
flush_op => '0',
diag_op => '0',
reqst => '0',
set => 0,
noflush => '0',
cmiss => '0'
);
constant SRES : snoop_reg_type := (
snoop => '0',
addr => (others => '0'),
mask => (others => '0'),
snhit => (others => '0')
);
constant LRES : lru_reg_type := (
write => '0',
waddr => (others => '0'),
set => (others => '0'),
lru => (others => (others => '0'))
);
signal r, c : dcache_control_type; -- r is registers, c is combinational
signal rs, cs : snoop_reg_type; -- rs is registers, cs is combinational
signal rl, cl : lru_reg_type; -- rl is registers, cl is combinational
begin
dctrl : process(rst, r, rs, rl, dci, mcdo, ico, dcramo, ahbsi, fpuholdn, mmudco, ahbso)
variable dcramov : dcram_out_type;
variable rdatasel : rdatatype;
variable maddress : std_logic_vector(31 downto 0);
variable maddrlow : std_logic_vector(1 downto 0);
variable edata : std_logic_vector(31 downto 0);
variable size : std_logic_vector(1 downto 0);
variable read : std_ulogic;
variable twrite, tpwrite, tdiagwrite, ddiagwrite, dwrite : std_ulogic;
variable taddr : std_logic_vector(OFFSET_HIGH downto LINE_LOW); -- tag address
variable newtag : std_logic_vector(TAG_HIGH downto TAG_LOW); -- new tag
variable newptag : std_logic_vector(TAG_HIGH downto TAG_LOW); -- new tag
variable align_data : std_logic_vector(31 downto 0); -- aligned data
variable ddatainv, rdatav, align_datav : cdatatype;
variable rdata : std_logic_vector(31 downto 0);
variable vmask : valid_type; --std_logic_vector((dlinesize -1) downto 0);
variable enable, senable, scanen : std_logic_vector(0 to 3);
variable mds : std_ulogic;
variable mexc : std_ulogic;
variable hit, valid, forcemiss : std_ulogic;
variable flush : std_ulogic;
variable iflush : std_ulogic;
variable v : dcache_control_type;
variable eholdn : std_ulogic; -- external hold
variable snoopwe : std_ulogic;
variable hcache : std_ulogic;
variable lramcs, lramen, lramrd, lramwr, ilramen : std_ulogic;
variable snoopaddr : std_logic_vector(OFFSET_HIGH downto OFFSET_LOW);
variable flushaddr : std_logic_vector(OFFSET_HIGH downto OFFSET_LOW);
variable vs : snoop_reg_type;
variable dsudata : std_logic_vector(31 downto 0);
variable set, eset : integer range 0 to DSETS-1;
variable ddset : integer range 0 to MAXSETS-1;
variable snoopset : integer range 0 to DSETS-1;
variable validraw : std_logic_vector(0 to DSETS-1);
variable validv, hitv : std_logic_vector(0 to MAXSETS-1);
variable csnoopwe, snhit : std_logic_vector(0 to MAXSETS-1);
variable ctwrite, ctpwrite, cdwrite : std_logic_vector(0 to MAXSETS-1);
variable setrepl : std_logic_vector(log2x(DSETS)-1 downto 0);
variable lrusetval: std_logic_vector(SETBITS-1 downto 0);
variable wlrr : std_logic_vector(0 to 3);
variable vl : lru_reg_type;
variable diagset : std_logic_vector(TAG_LOW + SETBITS -1 downto TAG_LOW);
variable lock : std_logic_vector(0 to DSETS-1);
variable wlock : std_logic_vector(0 to MAXSETS-1);
variable laddr : std_logic_vector(31 downto 0); -- local ram addr
variable tag : cdatatype; --std_logic_vector(31 downto 0);
variable ptag : cdatatype; --std_logic_vector(31 downto 0);
variable rlramrd : std_ulogic;
variable cache : std_ulogic;
variable ctx : ctxdatatype;
variable flushl : std_ulogic;
variable flushlv : std_logic_vector(0 to MAXSETS-1);
variable miscdata : std_logic_vector(31 downto 0);
variable pflush : std_logic;
variable pflushaddr : std_logic_vector(VA_I_U downto VA_I_D);
variable pflushtyp : std_logic;
variable pftag : std_logic_vector(31 downto 2);
variable mmudci_fsread, tagclear : std_logic;
variable mmudci_trans_op : std_logic;
variable mmudci_flush_op : std_logic;
variable mmudci_wb_op : std_logic;
variable mmudci_diag_op : std_logic;
variable mmudci_su : std_logic;
variable mmudci_read : std_logic;
variable su : std_logic;
variable mmudci_transdata_data : std_logic_vector(31 downto 0);
variable paddress : std_logic_vector(31 downto 0); -- physical address buffer
variable pagesize : integer range 0 to 3;
variable mhold : std_logic; -- MMU hold
variable wbhold : std_logic; -- write-buffer hold
begin
-- init local variables
v := r; vs := rs; dcramov := dcramo; vl := rl;
vl.write := '0'; lramen := '0'; lramrd := '0'; lramwr := '0';
lramcs := '0'; laddr := (others => '0'); v.cctrlwr := '0';
ilramen := '0'; v.flush2 := r.flush;
snhit := (others => '0'); v.cmiss := '0'; mhold := '0'; wbhold := '0';
pagesize := MMU_getpagesize(mmupgsz,r.mmctrl1);
if ((dci.eenaddr or dci.enaddr) = '1') or (r.dstate /= idle) or
((dsu = 1) and (dci.dsuen = '1')) or (r.flush = '1') or
(is_fpga(memtech) = 1)
then
enable := (others => '1');
else enable := (others => '0'); end if;
v.mmctrl1wr := '0';
tagclear := '0'; paddress := r.paddress;
if (not M_EN) or ((r.asi(4 downto 0) = ASI_MMU_BP) or (r.mmctrl1.e = '0')) then
paddress := r.xaddress;
end if;
mds := '1'; dwrite := '0'; twrite := '0'; tpwrite := '0';
ddiagwrite := '0'; tdiagwrite := '0'; v.holdn := '1'; mexc := '0';
flush := '0'; v.icenable := '0'; iflush := '0';
eholdn := ico.hold and fpuholdn; ddset := 0;
vs.snoop := '0'; snoopwe := '0';
snoopaddr := ahbsi.haddr(OFFSET_HIGH downto OFFSET_LOW);
flushaddr := r.xaddress(OFFSET_HIGH downto OFFSET_LOW);
hcache := '0';
validv := (others => '0'); hitv := (others => '0'); cache := '0';
if (dlram /= 0) then rlramrd := r.lramrd; else rlramrd := '0'; end if;
miscdata := (others => '0'); pflush := '0';
pflushaddr := dci.maddress(VA_I_U downto VA_I_D); pflushtyp := PFLUSH_PAGE;
pftag := (others => '0');
ctx := (others => (others => '0'));
mmudci_fsread := '0';
ddatainv := (others => (others => '0')); tag := (others => (others => '0')); ptag := (others => (others => '0'));
v.flushl2 := dci.flushl and not r.flush;
newptag := (others => '0');
v.trans_op := r.trans_op and (not mmudco.grant);
v.flush_op := r.flush_op and (not mmudco.grant);
v.diag_op := r.diag_op and (not mmudco.grant);
mmudci_trans_op := r.trans_op;
mmudci_flush_op := r.flush_op;
mmudci_diag_op := r.diag_op;
mmudci_wb_op := '0';
mmudci_transdata_data := r.vaddr;
mmudci_su := '0'; mmudci_read := '0'; su := '0';
rdatasel := ddata; -- read data from cache as default
senable := (others => '0'); scanen := (others => '0'); -- scanen no longer handled here
set := 0; snoopset := 0; csnoopwe := (others => '0');
ctwrite := (others => '0'); ctpwrite := (others => '0'); cdwrite := (others => '0');
wlock := (others => '0');
for i in 0 to DSETS-1 loop wlock(i) := dcramov.tag(i)(CTAG_LOCKPOS); end loop;
wlrr := (others => '0');
for i in 0 to 3 loop wlrr(i) := dcramov.tag(i)(CTAG_LRRPOS); end loop;
if (DSETS > 1) then setrepl := r.setrepl; else setrepl := (others => '0'); end if;
-- random replacement counter
if DSETS > 1 then
if conv_integer(r.rndcnt) = (DSETS - 1) then v.rndcnt := (others => '0');
else v.rndcnt := r.rndcnt + 1; end if;
end if;
-- generate lock bits
lock := (others => '0');
if dsetlock = 1 then
for i in 0 to DSETS-1 loop lock(i) := dcramov.tag(i)(CTAG_LOCKPOS); end loop;
end if;
-- AHB snoop handling
if (DSNOOP2 /= 0) then
-- snoop on NONSEQ or SEQ and first word in cache line
-- do not snoop during own transfers or during cache flush
if (ahbsi.hready and ahbsi.hwrite and (not mcdo.bg or r.mmctrl1.e)) = '1' and
((ahbsi.htrans = HTRANS_NONSEQ) or
((ahbsi.htrans = HTRANS_SEQ) and
(ahbsi.haddr(LINE_HIGH downto LINE_LOW) = LINE_ZERO)))
then
vs.snoop := r.cctrl.dsnoop;
vs.addr := ahbsi.haddr(TAG_HIGH downto OFFSET_LOW);
if (r.mmctrl1.e = '1') and (mcdo.bg = '1') then vs.mask := r.wb.smask;
else vs.mask := (others => '1'); end if;
end if;
if DSNOOP /= 0 then
for i in 0 to DSETS-1 loop senable(i) := vs.snoop or rs.snoop; end loop;
end if;
for i in DSETS-1 downto 0 loop
if ((rs.snoop and not (r.flush or r.flush2)) = '1') then
if (DSNOOP2 /= 0) and (rs.mask(i) = '1') and
((dcramov.stag(i)(TAG_HIGH downto TAG_LOW) = rs.addr(TAG_HIGH downto TAG_LOW))
)
then
if DSNOOP2 /= 3 then
if DSNOOPSEP then flushaddr := rs.addr(OFFSET_HIGH downto OFFSET_LOW);
else snoopaddr := rs.addr(OFFSET_HIGH downto OFFSET_LOW); end if;
end if;
snoopwe := '1'; snoopset := i; snhit(i) := '1';
end if;
end if;
end loop;
end if;
vs.snhit := snhit;
if DSNOOP2=3 then
snhit := (others => '0');
snoopwe := '0';
end if;
-- generate access parameters during pipeline stall
if ((r.holdn) = '0') or ((dsu = 1) and (dci.dsuen = '1')) then
taddr := r.xaddress(OFFSET_HIGH downto LINE_LOW);
elsif ((dci.enaddr and not dci.read) = '1') or (eholdn = '0')
then
taddr := dci.maddress(OFFSET_HIGH downto LINE_LOW);
else
taddr := dci.eaddress(OFFSET_HIGH downto LINE_LOW);
end if;
if (dci.write or not r.holdn) = '1' then
maddress := r.xaddress(31 downto 0);
read := r.read; size := r.size; edata := dci.maddress;
mmudci_su := r.su; mmudci_read := r.read and not r.dlock;
else
maddress := dci.maddress(31 downto 0);
read := dci.read; size := dci.size; edata := dci.edata;
mmudci_su := dci.msu; mmudci_read := dci.read and not dci.lock;
end if;
newtag := dci.maddress(TAG_HIGH downto TAG_LOW);
newptag := dci.maddress(TAG_HIGH downto TAG_LOW);
vl.waddr := maddress(OFFSET_HIGH downto OFFSET_LOW); -- lru write address
if (dsnoop = 6) and (r.cctrl.dsnoop = '0') then
snoopaddr := taddr(OFFSET_HIGH downto OFFSET_LOW);
senable := enable;
end if;
lrusetval := lru_set(rl.lru(conv_integer(maddress(OFFSET_HIGH downto OFFSET_LOW))), lock(0 to DSETS-1));
-- generate cache hit and valid bits
if (r.mmctrl1.e = '0') then hcache := ahb_slv_dec_cache(dci.maddress, ahbso, cached);
else hcache := '1'; end if;
forcemiss := (not dci.asi(3)) or dci.lock;
if (dci.asi(4 downto 0) = ASI_MMU_BP) or (r.cctrl.dcs(0) = '0') or
((r.flush or r.flush2) = '1')
then hcache := '0'; end if;
hit := '0'; set := 0;
for i in DSETS-1 downto 0 loop
if (dcramov.tag(i)(TAG_HIGH downto TAG_LOW) = dci.maddress(TAG_HIGH downto TAG_LOW))
and ((dcramov.ctx(i) = r.mmctrl1.ctx) or (r.mmctrl1.e = '0'))
then hitv(i) := '1'; end if;
validv(i) := hcache and hitv(i) and (not r.flush) and (not r.flush2) and dcramov.tag(i)(dlinesize-1);
validraw(i) := dcramov.tag(i)(dlinesize-1);
end loop;
if drepl = dir then
hit := hitv(conv_integer(dci.maddress(OFFSET_HIGH+DIR_BITS downto OFFSET_HIGH+1))) and not r.flush and (not r.flush2);
valid := validv(conv_integer(dci.maddress(OFFSET_HIGH+DIR_BITS downto OFFSET_HIGH+1)));
else
hit := orv(hitv) and not r.flush and (not r.flush2);
valid := orv(validv);
end if;
-- force cache miss if mmu-enabled but off or BYPASS, or on flush
if (dci.asi(4 downto 0) = ASI_MMU_BP) or (r.cctrl.dcs(0) = '0') or ((r.flush or r.flush2) = '1')
then hit := '0'; end if;
if DSETS > 1 then
if drepl = dir then
set := conv_integer(dci.maddress(OFFSET_HIGH+DIR_BITS downto OFFSET_HIGH+1));
else
for i in DSETS-1 downto 0 loop
if (hitv(i) = '1') then set := i; end if;
end loop;
end if;
if rlramrd = '1' then set := 1; end if;
else set := 0; end if;
if (dci.dsuen = '1') then diagset := r.xaddress(TAG_LOW+SETBITS-1 downto TAG_LOW);
else diagset := maddress(TAG_LOW + SETBITS - 1 downto TAG_LOW); end if;
case DSETS is
when 1 => ddset := 0;
when 3 => if conv_integer(diagset) < 3 then ddset := conv_integer(diagset); end if;
when others => ddset := conv_integer(diagset);
end case;
if ((r.holdn and dci.enaddr) = '1') and (r.dstate = idle) then
v.hit := hit; v.xaddress := dci.maddress;
v.read := dci.read; v.size := dci.size;
v.asi := dci.asi(4 downto 0);
v.su := dci.msu; v.set := set;
v.valid := valid; v.dlock := dci.lock;
end if;
-- Store buffer
if mcdo.ready = '1' then
v.wb.addr(LINE_HIGH downto 2) := r.wb.addr(LINE_HIGH downto 2) + 1;
if r.stpend = '1' then
v.stpend := r.req; v.wb.data1 := r.wb.data2;
v.wb.lock := r.wb.lock and r.req;
end if;
end if;
if mcdo.grant = '1' then v.req := r.burst; v.burst := '0'; end if;
if (mcdo.grant and not r.wb.read and r.req) = '1' then v.wb.lock := '0'; end if;
if (mcdo.grant and r.req) = '1' then v.wb.lock2 := r.wb.lock; end if;
if (dlram /= 0) then
if ((r.holdn) = '0') or ((dsu = 1) and (dci.dsuen = '1')) then
laddr := r.xaddress;
elsif ((dci.enaddr and not dci.read) = '1') or (eholdn = '0') then
laddr := dci.maddress;
else laddr := dci.eaddress; end if;
if (dci.enaddr = '1') and (dci.maddress(31 downto 24) = LOCAL_RAM_START)
then lramen := '1'; end if;
if ((laddr(31 downto 24) = LOCAL_RAM_START)) or ((dci.dsuen = '1') and (dci.asi(4 downto 1) = "0101"))
then lramcs := '1'; end if;
end if;
if (ilram /= 0) then
if (dci.enaddr = '1') and (dci.maddress(31 downto 24) = ILRAM_START) then ilramen := '1'; end if;
end if;
-- cache freeze operation
if (r.cctrl.ifrz and dci.intack and r.cctrl.ics(0)) = '1' then
v.cctrl.ics := "01";
end if;
if (r.cctrl.dfrz and dci.intack and r.cctrl.dcs(0)) = '1' then
v.cctrl.dcs := "01";
end if;
if (r.cctrlwr and not dci.nullify) = '1' then
if (r.xaddress(7 downto 2) = "000000") and (dci.read = '0') then
v.noflush := dci.maddress(30);
v.cctrl.dsnoop := dci.maddress(23);
flush := dci.maddress(22);
iflush := dci.maddress(21);
v.cctrl.burst:= dci.maddress(16);
v.cctrl.dfrz := dci.maddress(5);
v.cctrl.ifrz := dci.maddress(4);
v.cctrl.dcs := dci.maddress(3 downto 2);
v.cctrl.ics := dci.maddress(1 downto 0);
end if;
if (memtech = rhlib18t) and (r.xaddress(7 downto 2) = "000001") and (dci.read = '0') then
v.tadj := dci.maddress(5 downto 4);
v.sadj := dci.maddress(3 downto 2);
v.dadj := dci.maddress(1 downto 0);
end if;
end if;
-- main Dcache state machine
case r.dstate is
when idle => -- Idle state
if (M_TLB_FASTWRITE /= 0) then
mmudci_transdata_data := dci.maddress;
end if;
v.nomds := r.nomds and not eholdn; v.bmexc := '0';
if ((r.reqst = '0') and (r.stpend = '0')) or ((mcdo.ready and not r.req)= '1') then -- wait for store queue
v.wb.addr := dci.maddress; v.wb.size := dci.size;
v.wb.read := dci.read; v.wb.data1 := dci.edata; v.wb.lock := dci.lock and not dci.nullify and ico.hold;
v.wb.asi := dci.asi(3 downto 0);
if ((M_EN) and (dci.asi(4 downto 0) /= ASI_MMU_BP) and (r.mmctrl1.e = '1') and
((M_TLB_FASTWRITE /= 0) or ((dci.enaddr and eholdn and dci.lock and not dci.read) = '1')))
then
if (dci.enaddr and eholdn and dci.lock and not dci.read) = '1' then -- skip address translation on store in LDST
v.wb.addr := r.wb.addr(31 downto 8) & dci.maddress(7 downto 0);
newptag := r.wb.addr(TAG_HIGH downto TAG_LOW);
else
v.wb.addr := mmudco.wbtransdata.data;
newptag := mmudco.wbtransdata.data(TAG_HIGH downto TAG_LOW);
end if;
end if;
if (dci.read and hcache and andv(r.cctrl.dcs)) = '1' then v.wb.addr(LINE_HIGH downto 0) := (others => '0'); end if;
end if;
if (eholdn and (not r.nomds)) = '1' then -- avoid false path through nullify
case dci.asi(4 downto 0) is
when ASI_SYSR => rdatasel := sysr;
when ASI_DTAG => rdatasel := dtag;
when ASI_DDATA => rdatasel := dddata;
when ASI_DCTX => if M_EN then rdatasel := dctx; end if;
when ASI_MMUREGS | ASI_MMUREGS_V8 => if M_EN then rdatasel := misc; end if;
when ASI_MMUSNOOP_DTAG => rdatasel := mmusnoop_dtag;
when others =>
end case;
end if;
if (dci.enaddr and eholdn and (not r.nomds) and not dci.nullify) = '1' then
case dci.asi(4 downto 0) is
when ASI_SYSR => -- system registers
v.cctrlwr := not dci.read and not (dci.dsuen and not dci.eenaddr);
when ASI_MMUREGS | ASI_MMUREGS_V8 =>
if M_EN then
if (dsu = 0) or dci.dsuen = '0' then
-- clean fault valid bit
if dci.read = '1' then
case dci.maddress(CNR_U downto CNR_D) is
when CNR_F =>
mmudci_fsread := '1';
when others => null;
end case;
end if;
end if;
v.mmctrl1wr := not dci.read and not (r.mmctrl1wr and dci.dsuen);
end if;
when ASI_ITAG | ASI_IDATA | ASI_ICTX => -- Read/write Icache tags
-- CTX write has to be done through ctxnr & ASI_ITAG
if (ico.flush = '1') or (dci.asi(4) = '1') then mexc := '1';
else v.dstate := asi_idtag; v.holdn := dci.dsuen; end if;
when ASI_UINST | ASI_SINST =>
if (ilram /= 0) then v.dstate := asi_idtag; v.ilramen := '1'; end if;
when ASI_DFLUSH => -- flush data cache
if dci.read = '0' then flush := '1'; end if;
when ASI_DDATA => -- Read/write Dcache data
if DSNOOPSEP then flushaddr := taddr(OFFSET_HIGH downto OFFSET_LOW); end if;
if (r.flush = '1') then -- No access on flush
mexc := '1';
elsif (dci.read = '0') then
dwrite := '1'; ddiagwrite := '1';
end if;
when ASI_DTAG => -- Read/write Dcache tags
if DSNOOPSEP then flushaddr := taddr(OFFSET_HIGH downto OFFSET_LOW); end if;
if (dci.size /= "10") or (r.flush = '1') then -- allow only word access
mexc := '1';
elsif (dci.read = '0') then
twrite := '1'; tdiagwrite := '1';
end if;
when ASI_MMUSNOOP_DTAG => -- Read/write MMU physical snoop tags
if DSNOOPSEP then
snoopaddr := taddr(OFFSET_HIGH downto OFFSET_LOW);
if (dci.size /= "10") or (r.flush = '1') then -- allow only word access
mexc := '1';
elsif (dci.read = '0') then
tpwrite := '1'; tdiagwrite := '1';
end if;
end if;
when ASI_DCTX =>
-- write has to be done through ctxnr & ASI_DTAG
if DSNOOPSEP then flushaddr := taddr(OFFSET_HIGH downto OFFSET_LOW); end if;
if (dci.size /= "10") or (r.flush = '1') or (dci.read = '0') then -- allow only word access
mexc := '1';
end if;
when ASI_FLUSH_PAGE => -- i/dcache flush page
if dci.read = '0' then iflush := '1'; end if;
if M_EN then
if dci.read = '0' then
flush := '1'; --pflush := '1'; pflushtyp := PFLUSH_PAGE;
end if;
end if;
when ASI_FLUSH_CTX => -- i/dcache flush ctx
if M_EN then
if dci.read = '0' then
flush := '1'; iflush := '1'; --pflush := '1'; pflushtyp := PFLUSH_CTX;
end if;
end if;
when ASI_MMUFLUSHPROBE | ASI_MMUFLUSHPROBE_V8 =>
if M_EN then
if dci.read = '0' then -- flush
mmudci_flush_op := '1';
v.flush_op := not mmudco.grant;
v.dstate := wflush;
v.vaddr := dci.maddress; v.holdn := '0'; flush := '1'; iflush := '1';
end if;
end if;
when ASI_MMU_DIAG =>
if dci.read = '0' then -- diag access
mmudci_diag_op := '1';
v.diag_op := not mmudco.grant;
v.vaddr := dci.maddress;
end if;
when others =>
if dci.read = '1' then -- read access
v.rburst := hcache and andv(r.cctrl.dcs); -- and not forcemiss;
if (dlram /= 0) and (lramen = '1') then
lramrd := '1';
elsif (ilram /= 0) and (ilramen = '1') then
if (ico.flush = '1') or (dci.size /= "10") then mexc := '1';
else v.dstate := asi_idtag; v.holdn := dci.dsuen; v.ilramen := '1'; end if;
elsif dci.dsuen = '0' then
if not ((hit and valid and not forcemiss) = '1') then -- read miss
v.holdn := '0'; v.dstate := wread; v.ready := '0'; v.cmiss := hcache;
v.cache := hcache and andv(r.cctrl.dcs);
if (not M_EN) or ((dci.asi(4 downto 0) = ASI_MMU_BP) or (r.mmctrl1.e = '0')) then
-- cache disabled if mmu-enabled but off or BYPASS
if ((r.stpend = '0') or ((mcdo.ready and not r.req) = '1')) then
v.req := '1'; v.burst := v.rburst or (andv(dci.size) and not dci.maddress(2));
end if;
else
-- ## mmu case >
if (r.stpend = '0') or ((mcdo.ready and not r.req)= '1') then
v.wbinit := '1'; -- wb init in idle
-- defer or:in in rburst to after mmu lookup since it
-- might get cleared
v.burst := (andv(dci.size) and not dci.maddress(2));
else
v.wbinit := '0';
end if;
mmudci_trans_op := '1'; -- start translation
v.trans_op := not mmudco.grant;
v.vaddr := dci.maddress;
v.dstate := rtrans;
-- ## < mmu case
end if;
else -- read hit
if (DSETS > 1) and (drepl = lru) then vl.write := '1'; end if;
cache := '1';
end if;
end if;
else -- write access
if (dlram /= 0) and (lramen = '1') then
lramwr := '1';
if (dci.size = "11") then -- double store
v.dstate := dblwrite; v.xaddress(2) := '1';
end if;
elsif (ilram /= 0) and (ilramen = '1') then
if (ico.flush = '1') or (dci.size /= "10") then mexc := '1';
else v.dstate := asi_idtag; v.holdn := dci.dsuen; v.ilramen := '1'; end if;
elsif dci.dsuen = '0' then
v.ready := '0';
if (not M_EN) or
((dci.asi(4 downto 0) = ASI_MMU_BP) or (r.mmctrl1.e = '0')) then
if ((r.stpend = '0') or ((mcdo.ready and not r.req)= '1'))
then -- wait for store queue
v.reqst := '1';
v.burst := dci.size(1) and dci.size(0);
if (dci.size = "11") then v.dstate := dblwrite; end if; -- double store
v.wb.smask := (others => '1');
else -- wait for store queue
v.dstate := wwrite; v.holdn := '0'; v.wb.read := r.wb.read;
end if;
else
-- ## mmu case > false and
if ((r.stpend = '0') or ((mcdo.ready and not r.req)= '1')) and
(((mmudco.wbtransdata.accexc = '0') and (M_TLB_FASTWRITE /= 0)) or (dci.lock = '1'))
then
v.reqst := '1';
v.burst := dci.size(1) and dci.size(0);
if (dci.size = "11") then v.dstate := dblwrite; end if; -- double store
v.wb.smask := (others => '1');
if hit = '1' then v.wb.smask(set) := '0'; end if;
else
if (r.stpend = '0') or ((mcdo.ready and not r.req)= '1')
then
v.wbinit := '1'; -- wb init in idle
v.burst := dci.size(1) and dci.size(0);
v.wb.smask := (others => '1');
if hit = '1' then v.wb.smask(set) := '0'; end if;
else
v.wbinit := '0';
end if;
mmudci_trans_op := '1'; -- start translation
v.trans_op := not mmudco.grant;
v.vaddr := dci.maddress; v.holdn := '0';
v.dstate := wtrans;
-- ## < mmu case
end if;
end if;
if (hit and valid) = '1' then -- write hit
dwrite := '1';
if (DSETS > 1) and (drepl = lru) then vl.write := '1'; end if;
setrepl := conv_std_logic_vector(set, SETBITS);
if DSNOOP2 /= 0 then
if ((dci.enaddr and not dci.read) = '1') or (eholdn = '0')
then v.xaddress := dci.maddress; else v.xaddress := dci.eaddress; end if;
end if;
end if;
if (dci.size = "11") then v.xaddress(2) := '1'; end if;
end if;
end if;
eset := set;
if (DSETS > 1) then
vl.set := conv_std_logic_vector(set, SETBITS);
v.setrepl := conv_std_logic_vector(set, SETBITS);
if (andv(validraw) = '0') and (drepl /= dir) and false then
for i in DSETS-1 downto 0 loop
if validraw(i) = '0' then eset := i; end if;
end loop;
v.setrepl := conv_std_logic_vector(eset, SETBITS);
elsif ((not hit) and (not r.flush)) = '1' then
case drepl is
when rnd =>
if dsetlock = 1 then
if lock(conv_integer(r.rndcnt)) = '0' then v.setrepl := r.rndcnt;
else
v.setrepl := conv_std_logic_vector(DSETS-1, SETBITS);
for i in DSETS-1 downto 0 loop
if (lock(i) = '0') and (i>conv_integer(r.rndcnt)) then
v.setrepl := conv_std_logic_vector(i, SETBITS);
end if;
end loop;
end if;
else
v.setrepl := r.rndcnt;
end if;
when dir =>
v.setrepl := dci.maddress(OFFSET_HIGH+log2x(DSETS) downto OFFSET_HIGH+1);
when lru =>
v.setrepl := lrusetval;
when lrr =>
v.setrepl := (others => '0');
if dsetlock = 1 then
if lock(0) = '1' then v.setrepl(0) := '1';
else
v.setrepl(0) := dcramov.tag(0)(CTAG_LRRPOS) xor dcramov.tag(1)(CTAG_LRRPOS);
end if;
else
v.setrepl(0) := dcramov.tag(0)(CTAG_LRRPOS) xor dcramov.tag(1)(CTAG_LRRPOS);
end if;
if v.setrepl(0) = '0' then
v.lrr := not dcramov.tag(0)(CTAG_LRRPOS);
else
v.lrr := dcramov.tag(0)(CTAG_LRRPOS);
end if;
end case;
end if;
if (dsetlock = 1) then
if (hit and lock(set)) = '1' then v.lock := '1';
else v.lock := '0'; end if;
end if;
end if;
end case;
end if;
when rtrans =>
if M_EN then
if r.stpend = '1' then
if ((mcdo.ready and not r.req) = '1') then
v.ready := '1'; -- buffer store finish
end if;
end if;
v.holdn := '0';
if mmudco.transdata.finish = '1' then
-- translation error, i.e. page fault
if (mmudco.transdata.accexc) = '1' then
v.holdn := '1'; v.dstate := idle;
mds := '0'; mexc := not r.mmctrl1.nf;
else
v.dstate := wread;
v.cache := r.cache and mmudco.transdata.cache;
v.paddress := mmudco.transdata.data;
v.rburst := r.rburst and v.cache;
if r.wbinit = '1' then
v.wb.addr := v.paddress; --mmudco.transdata.data;
v.req := '1';
v.burst := r.burst or v.rburst;
if v.rburst = '1' then
v.wb.addr(LINE_HIGH downto 0) := (others => '0');
end if;
end if;
end if;
end if;
mhold := '1';
end if;
when wread => -- read miss, wait for memory data
if drepl=lru and mcdo.ready='0' and r.hit='0' then
v.setrepl := lrusetval;
end if;
taddr := r.wb.addr(OFFSET_HIGH downto LINE_LOW);
newtag := r.xaddress(TAG_HIGH downto TAG_LOW);
newptag := paddress(TAG_HIGH downto TAG_LOW);
v.nomds := r.nomds and not eholdn;
v.holdn := v.nomds; rdatasel := memory;
for i in 0 to DSETS-1 loop wlock(i) := r.lock; end loop;
for i in 0 to 3 loop wlrr(i) := r.lrr; end loop;
if (r.stpend = '0') and (r.ready = '0') then
if (r.rburst) = '1' then
if (mcdo.grant = '1') and ((r.cctrl.dcs = "01") or
((r.wb.addr(LINE_HIGH downto LINE_LOW) >= bend(LINE_HIGH downto LINE_LOW)) and not
((r.wb.addr(LINE_HIGH downto LINE_LOW) = bend(LINE_HIGH downto LINE_LOW)) and (mcdo.ready = '0')))) then
v.burst := '0';
else v.burst := r.burst; end if;
end if;
if mcdo.ready = '1' then
if r.rburst = '0' then
mds := r.holdn or r.nomds; v.xaddress(2) := '1'; v.holdn := '1';
else
if r.wb.addr(LINE_HIGH downto LINE_LOW) = r.xaddress(LINE_HIGH downto LINE_LOW) then
mds := '0';
end if;
end if;
dwrite := r.cache; rdatasel := memory;
mexc := mcdo.mexc;
v.bmexc := r.bmexc or mcdo.mexc or dci.flushl;
if r.req = '0' then
twrite := r.cache; tagclear := v.bmexc;
if (((dci.enaddr and not r.holdn) = '1') or (dci.flushl = '1') or ((dci.eenaddr and r.holdn and eholdn) = '1'))
and ((r.cctrl.dcs(0) = '1') or (dlram /= 0))
then v.dstate := loadpend; v.holdn := '0';
else v.dstate := idle; v.holdn := '1'; end if;
else v.nomds := not r.rburst; end if;
if DSNOOP2/=3 then
tpwrite := twrite;
end if;
if DSNOOP2=3 and r.req='1' and r.cache='1' then
tpwrite := '1';
end if;
end if;
v.mexc := mcdo.mexc and not r.rburst; v.wb.data2 := mcdo.data;
else
if (r.ready or (mcdo.ready and not r.req)) = '1' then -- wait for store queue
v.wb.addr := paddress;
v.wb.size := r.size;
v.burst := r.rburst or (r.size(1) and r.size(0) and not r.xaddress(2));
if r.rburst = '1' then
v.wb.addr(LINE_HIGH downto 0) := (others => '0');
end if;
v.wb.read := r.read; v.wb.data1 := dci.maddress; v.req := '1';
v.wb.lock := dci.lock; v.wb.asi := r.asi(3 downto 0); v.ready := '0';
end if;
wbhold := '1';
end if;
when loadpend => -- return from read miss with load pending
taddr := dci.maddress(OFFSET_HIGH downto LINE_LOW);
if (dlram /= 0) then
laddr := dci.maddress;
if laddr(31 downto 24) = LOCAL_RAM_START then lramcs := '1'; end if;
end if;
if (r.flushl2 and dci.enaddr) = '1' then
v.holdn := '0';
else
v.dstate := idle;
end if;
when dblwrite => -- second part of double store cycle
edata := dci.edata; -- needed for STD store hit
taddr := r.xaddress(OFFSET_HIGH downto LINE_LOW);
if (dlram /= 0) and (rlramrd = '1') then
laddr := r.xaddress; lramwr := '1';
else
if r.hit = '1' then dwrite := r.valid; end if;
v.wb.data2 := dci.edata;
end if;
if (dci.flushl and ico.hold) = '1' then
v.dstate := loadpend; v.holdn := '0';
elsif ico.hold = '0' then v.reqst := '0';
else v.dstate := idle; end if;
when asi_idtag => -- icache diag and inst local ram access
rdatasel := icache; v.icenable := '1'; v.holdn := dci.dsuen;
if ico.diagrdy = '1' then
v.dstate := loadpend; v.icenable := '0'; v.ilramen := '0';
if (dsu = 0) or ((dsu = 1) and (dci.dsuen = '0')) then
mds := not r.read;
end if;
end if;
when wtrans =>
edata := dci.edata; -- needed for STD store hit
taddr := r.xaddress(OFFSET_HIGH downto LINE_LOW);
newtag := r.xaddress(TAG_HIGH downto TAG_LOW);
if M_EN then
if r.stpend = '1' then
if ((mcdo.ready and not r.req) = '1') then
v.ready := '1'; -- buffer store finish
end if;
end if;
v.holdn := '0';
if mmudco.transdata.finish = '1' then
if (mmudco.transdata.accexc) = '1' then
v.holdn := '1'; v.dstate := idle;
mds := '0'; mexc := not r.mmctrl1.nf;
tagclear := r.hit;
twrite := tagclear;
if (twrite = '1') and (((dci.enaddr and not mds) = '1') or
((dci.eenaddr and mds and eholdn) = '1')) and (r.cctrl.dcs(0) = '1') then
v.dstate := loadpend; v.holdn := '0';
end if;
else
v.dstate := wwrite;
v.cache := mmudco.transdata.cache;
v.paddress := mmudco.transdata.data;
if (r.wbinit) = '1' then
v.wb.data2 := dci.edata;
v.wb.addr := mmudco.transdata.data;
v.dstate := idle; v.holdn := '1';
if (dci.nullify = '0')
then
v.req := '1'; v.stpend := '1';
else v.reqst := '1'; end if;
v.burst := r.size(1) and r.size(0) and not v.wb.addr(2);
if (r.hit = '1') and (r.size = "11") then -- write hit
dwrite := r.valid;
end if;
end if;
end if;
end if;
end if;
mhold := '1';
when wwrite => -- wait for store buffer to empty (store access)
edata := dci.edata; -- needed for STD store hit
if (
(dci.lock = '1')) and (dci.nullify = '1') then
v.dstate := idle; v.wb.lock := '0';
elsif ((v.ready or (mcdo.ready and not r.req)) = '1') or (
(dci.lock = '1')) then -- store queue emptied
if (r.hit = '1') and (r.size = "11") then -- write hit
taddr := r.xaddress(OFFSET_HIGH downto LINE_LOW); dwrite := r.valid;
end if;
v.dstate := idle;
v.burst := r.size(1) and r.size(0);
if (dci.nullify = '0') then v.reqst := '1'; end if;
v.wb.addr := paddress;
v.wb.size := r.size;
v.wb.read := r.read; v.wb.data1 := dci.maddress;
v.wb.lock := dci.lock; v.wb.data2 := dci.edata;
v.wb.asi := r.asi(3 downto 0);
if r.size = "11" then v.wb.addr(2) := '0'; end if;
v.wb.smask := (others => '1');
if r.hit = '1' then v.wb.smask(r.set) := '0'; end if;
else -- hold cpu until buffer empty
v.holdn := '0';
end if;
wbhold := '1';
when wflush =>
v.holdn := '0';
if mmudco.transdata.finish = '1' then
v.dstate := idle; v.holdn := '1';
end if;
when others => v.dstate := idle;
end case;
v.req := v.req or v.reqst; v.stpend := v.stpend or v.reqst; v.reqst := '0';
if (dlram /= 0) then v.lramrd := lramcs; end if; -- read local ram data
-- select data to return on read access
-- align if byte/half word read from cache or memory.
if (dsu = 1) and (dci.dsuen = '1') then
v.dsuset := conv_std_logic_vector(ddset, SETBITS);
case dci.asi(4 downto 0) is
when ASI_ITAG | ASI_IDATA =>
v.icenable := not ico.diagrdy;
rdatasel := icache;
when ASI_DTAG =>
tdiagwrite := dci.write;
twrite := not dci.eenaddr and dci.enaddr and dci.write;
rdatasel := dtag;
when ASI_MMUSNOOP_DTAG =>
if DSNOOPSEP then snoopaddr := taddr(OFFSET_HIGH downto OFFSET_LOW); end if;
tdiagwrite := dci.write;
tpwrite := not dci.eenaddr and dci.enaddr and dci.write;
rdatasel := mmusnoop_dtag; senable := (others => '1');
when ASI_DDATA =>
if M_EN then
ddiagwrite := dci.write;
dwrite := not dci.eenaddr and dci.enaddr and dci.write;
rdatasel := dddata;
end if;
when ASI_UDATA | ASI_SDATA =>
lramwr := not dci.eenaddr and dci.enaddr and dci.write;
when ASI_MMUREGS | ASI_MMUREGS_V8 =>
rdatasel := misc;
when others =>
end case;
end if;
-- read
if M_EN then
case dci.maddress(CNR_U downto CNR_D) is
when CNR_CTRL =>
miscdata(MMCTRL_E) := r.mmctrl1.e;
miscdata(MMCTRL_NF) := r.mmctrl1.nf;
miscdata(MMCTRL_PSO) := r.mmctrl1.pso;
miscdata(MMCTRL_VER_U downto MMCTRL_VER_D) := "0001";
miscdata(MMCTRL_IMPL_U downto MMCTRL_IMPL_D) := "0000";
miscdata(23 downto 21) := conv_std_logic_vector(M_ENT_ILOG,3);
miscdata(20 downto 18) := conv_std_logic_vector(M_ENT_DLOG,3);
if M_TLB_TYPE = 0 then miscdata(MMCTRL_TLBSEP) := '1'; else
miscdata(23 downto 21) := conv_std_logic_vector(M_ENT_CLOG,3);
miscdata(20 downto 18) := (others => '0');
end if;
miscdata(MMCTRL_TLBDIS) := r.mmctrl1.tlbdis;
miscdata(MMCTRL_PGSZ_U downto MMCTRL_PGSZ_D) := conv_std_logic_vector(pagesize,2); -- r.mmctrl1.pagesize;
--custom
when CNR_CTXP =>
miscdata(MMCTXP_U downto MMCTXP_D) := r.mmctrl1.ctxp;
when CNR_CTX =>
miscdata(MMCTXNR_U downto MMCTXNR_D) := r.mmctrl1.ctx;
when CNR_F =>
miscdata(FS_OW) := mmudco.mmctrl2.fs.ow;
miscdata(FS_FAV) := mmudco.mmctrl2.fs.fav;
miscdata(FS_FT_U downto FS_FT_D) := mmudco.mmctrl2.fs.ft;
miscdata(FS_AT_LS) := mmudco.mmctrl2.fs.at_ls;
miscdata(FS_AT_ID) := mmudco.mmctrl2.fs.at_id;
miscdata(FS_AT_SU) := mmudco.mmctrl2.fs.at_su;
miscdata(FS_L_U downto FS_L_D) := mmudco.mmctrl2.fs.l;
miscdata(FS_EBE_U downto FS_EBE_D) := mmudco.mmctrl2.fs.ebe;
when CNR_FADDR =>
miscdata(VA_I_U downto VA_I_D) := mmudco.mmctrl2.fa;
when others => null;
end case;
end if;
rdata := (others => '0'); rdatav := (others => (others => '0'));
align_data := (others => '0'); align_datav := (others => (others => '0'));
maddrlow := maddress(1 downto 0); -- stupid Synopsys VSS bug ...
case rdatasel is
when misc =>
if M_EN then set := 0; rdatav(0) := miscdata; end if;
when dddata =>
rdatav := dcramov.data;
if dci.dsuen = '1' then set := conv_integer(r.dsuset);
else set := ddset; end if;
when dtag =>
rdatav := dcramov.tag;
if dci.dsuen = '1' then set := conv_integer(r.dsuset);
else set := ddset; end if;
when mmusnoop_dtag =>
rdatav := dcramov.stag;
if dci.dsuen = '1' then set := conv_integer(r.dsuset);
else set := ddset; end if;
when dctx =>
--rdata(M_CTX_SZ-1 downto 0) := dcramov.dtramout(ddset).ctx;
when icache =>
rdatav(0) := ico.diagdata; set := 0;
when ddata | memory =>
if rdatasel = memory then
rdatav(0) := mcdo.data; set := 0;
else
for i in 0 to DSETS-1 loop rdatav(i) := dcramov.data(i); end loop;
end if;
when sysr =>
set := 0;
case dci.maddress(3 downto 2) is
when "00" =>
rdatav(0)(30) := r.noflush;
rdatav(0)(23) := r.cctrl.dsnoop;
if dsnoop > 4 then rdatav(0)(17) := '1'; end if;
rdatav(0)(16 downto 14) := r.cctrl.burst & ico.flush & r.flush;
rdatav(0)(5 downto 0) :=
r.cctrl.dfrz & r.cctrl.ifrz & r.cctrl.dcs & r.cctrl.ics;
when "01" =>
rdatav(0)(7 downto 0) := "00" & r.tadj & r.sadj & r.dadj;
when "10" =>
rdatav(0) := ico.cfg;
when others =>
rdatav(0) := cache_cfg(drepl, dsets, dlinesize, dsetsize, dsetlock,
dsnoop, DLRAM_EN, dlramsize, dlramstart, mmuen);
end case;
end case;
-- select which data to update the data cache with
for i in 0 to DSETS-1 loop
case size is -- merge data during partial write
when "00" =>
case maddrlow is
when "00" =>
ddatainv(i) := edata(7 downto 0) & dcramov.data(i)(23 downto 0);
when "01" =>
ddatainv(i) := dcramov.data(i)(31 downto 24) & edata(7 downto 0) &
dcramov.data(i)(15 downto 0);
when "10" =>
ddatainv(i) := dcramov.data(i)(31 downto 16) & edata(7 downto 0) &
dcramov.data(i)(7 downto 0);
when others =>
ddatainv(i) := dcramov.data(i)(31 downto 8) & edata(7 downto 0);
end case;
when "01" =>
if maddress(1) = '0' then
ddatainv(i) := edata(15 downto 0) & dcramov.data(i)(15 downto 0);
else
ddatainv(i) := dcramov.data(i)(31 downto 16) & edata(15 downto 0);
end if;
when others =>
ddatainv(i) := edata;
end case;
end loop;
-- handle double load with pipeline hold
if (r.dstate = idle) and (r.nomds = '1') then
rdatav(0) := r.wb.data2; mexc := r.mexc; set := 0;
end if;
-- Handle AHB retry. Re-generate bus request and burst
if mcdo.retry = '1' then
v.req := '1';
if r.wb.read = '0' then
v.burst := r.wb.size(0) and r.wb.size(1) and not r.wb.addr(2);
else
v.burst := ((r.rburst) and not andv(r.wb.addr(LINE_HIGH downto LINE_LOW))) or
(not r.rburst and r.wb.size(0) and r.wb.size(1) and not r.wb.addr(2));
end if;
v.wb.lock := r.wb.lock2;
end if;
-- Generate new valid bits
if r.flush = '1' then twrite := '0'; dwrite := '0'; end if;
vmask := (others => (others => '1'));
if twrite = '1' then
if tagclear = '1' then vmask := (others => (others => '0')); end if;
if (DSETS>1) and (drepl = lru) and (tdiagwrite = '0') then
vl.write := '1'; vl.set := setrepl;
end if;
end if;
if (DSETS>1) and (drepl = lru) and (rl.write = '1') then
vl.lru(conv_integer(rl.waddr)) :=
lru_calc(rl.lru(conv_integer(rl.waddr)), rl.set);
end if;
if tdiagwrite = '1' then -- diagnostic tag write
if (dsu = 1) and (dci.dsuen = '1') then
vmask := (others => dci.maddress(dlinesize - 1 downto 0));
else
vmask := (others => dci.edata(dlinesize - 1 downto 0));
newtag(TAG_HIGH downto TAG_LOW) := dci.edata(TAG_HIGH downto TAG_LOW);
newptag(TAG_HIGH downto TAG_LOW) := dci.edata(TAG_HIGH downto TAG_LOW);
for i in 0 to 3 loop wlrr(i) := dci.edata(CTAG_LRRPOS); end loop;
for i in 0 to DSETS-1 loop wlock(i) := dci.edata(CTAG_LOCKPOS); end loop;
end if;
end if;
-- mmureg write
if r.mmctrl1wr = '1' then
case r.xaddress(CNR_U downto CNR_D) is
when CNR_CTRL =>
v.mmctrl1.e := dci.maddress(MMCTRL_E);
v.mmctrl1.nf := dci.maddress(MMCTRL_NF);
v.mmctrl1.pso := dci.maddress(MMCTRL_PSO);
v.mmctrl1.tlbdis := dci.maddress(MMCTRL_TLBDIS);
v.mmctrl1.pagesize := dci.maddress(MMCTRL_PGSZ_U downto MMCTRL_PGSZ_D);
--custom
-- Note: before tlb disable tlb flush is required !!!
when CNR_CTXP =>
v.mmctrl1.ctxp := dci.maddress(MMCTXP_U downto MMCTXP_D);
when CNR_CTX =>
v.mmctrl1.ctx := dci.maddress(MMCTXNR_U downto MMCTXNR_D);
when CNR_F => null;
when CNR_FADDR => null;
when others => null;
end case;
end if;
-- cache flush
if ((dci.flush or dci.flushl or flush) = '1') and (dcen /= 0) then
v.flush := not r.noflush; v.faddr := (others => '0');
if (dci.flushl = '1') then v.flush := '1'; v.faddr := r.efaddr; end if;
end if;
if eholdn = '1' then v.efaddr := v.xaddress(OFFSET_HIGH downto OFFSET_LOW); end if;
if (r.flush = '1') and (dcen /= 0) then
twrite := '1'; vmask := (others => (others => '0'));
v.faddr := r.faddr +1; newtag(TAG_HIGH downto TAG_LOW) := (others => '0');
newptag := (others => '0');
if DSNOOPSEP then flushaddr := r.faddr; end if;
taddr(OFFSET_HIGH downto OFFSET_LOW) := r.faddr;
wlrr := (others => '0');
if ((r.faddr(DOFFSET_BITS -1) and not v.faddr(DOFFSET_BITS -1)) or r.flushl2) = '1' and (DSNOOP2/=3 or r.fflush='1')
then
v.flush := '0';
v.fflush := '0';
end if;
end if;
if DSNOOP2=3 and DCEN/=0 and r.fflush='0' and r.flush='1' and r.flush2='1' and dci.flush='0' and dci.flushl='0' then
v.flush:='0';
v.flush2:='0';
end if;
-- update cache with memory data during read miss
if read = '1' then
for i in 0 to DSETS-1 loop
ddatainv(i) := mcdo.data;
end loop;
end if;
-- cache write signals
if twrite = '1' then
if tdiagwrite = '1' then ctwrite(ddset) := '1';
else ctwrite(conv_integer(setrepl)) := '1'; end if;
end if;
if DSNOOPSEP then
if tpwrite = '1' then
if tdiagwrite = '1' then ctpwrite(ddset) := '1';
else ctpwrite(conv_integer(setrepl)) := '1'; end if;
end if;
end if;
if dwrite = '1' then
if ddiagwrite = '1' then cdwrite(ddset) := '1';
else cdwrite(conv_integer(setrepl)) := '1'; end if;
end if;
if (r.flush and twrite) = '1' then -- flush
ctwrite := (others => '1'); wlrr := (others => '0'); wlock := (others => '0');
if DSNOOPSEP then
ctpwrite := (others => '1');
end if;
end if;
csnoopwe := (others => '0'); flushl := '0';
flushlv := (others => r.flush);
if (snoopwe = '1') then csnoopwe := snhit; end if;
if DSNOOPSEP then
csnoopwe := csnoopwe or ctwrite;
flushlv := flushlv or snhit; -- flush tag on snoop hit
end if;
if r.flush2 = '1' then
vl.lru := (others => (others => '0'));
end if;
if dci.mmucacheclr='1' then
v.cctrl.dcs := "00";
v.cctrl.ics := "00";
v.cctrl.burst := '0';
v.mmctrl1.e := '0';
end if;
-- reset
if (not RESET_ALL) and (rst = '0') then
v.dstate := idle; v.stpend := '0'; v.req := '0'; v.burst := '0';
v.read := '0'; v.flush := '0'; v.nomds := '0'; v.holdn := '1';
v.rndcnt := (others => '0'); v.setrepl := (others => '0');
v.dsuset := (others => '0'); v.flush2 := '1'; v.fflush:='1';
v.lrr := '0'; v.lock := '0'; v.ilramen := '0';
v.cctrl.dcs := "00"; v.cctrl.ics := "00";
v.cctrl.burst := '0'; v.cctrl.dsnoop := '0';
v.tadj := (others => '0'); v.dadj := (others => '0');
v.sadj := (others => '0');
--if M_EN then
v.mmctrl1.e := '0'; v.mmctrl1.nf := '0'; v.mmctrl1.ctx := (others => '0');
v.mmctrl1.tlbdis := '0';
v.mmctrl1.pso := '0';
v.trans_op := '0';
v.flush_op := '0';
v.diag_op := '0';
v.pflush := '0';
v.pflushr := '0';
v.mmctrl1.pagesize := (others => '0');
--end if;
v.mmctrl1.bar := (others => '0');
v.faddr := (others => '0');
v.reqst := '0';
v.cache := '0'; v.wb.lock := '0'; v.wb.lock2 := '0';
v.wb.data1 := (others => '0'); v.wb.data2 := (others => '0');
v.noflush := '0'; v.mexc := '0';
end if;
if dsnoop = 0 then v.cctrl.dsnoop := '0'; end if;
if not M_EN then v.mmctrl1 := mmctrl_type1_none; end if; -- kill MMU regs if not enabled
-- Force cache control reg to off state if disabled
if dcen=0 then v.cctrl.dcs := "00"; end if;
if icen=0 then v.cctrl.ics := "00"; end if;
-- Drive signals
c <= v; cs <= vs; -- register inputs
cl <= vl;
-- tag ram inputs
senable := senable and not scanen; enable := enable and not scanen;
for i in 0 to DSETS-1 loop
tag(i)(dlinesize-1 downto 0) := vmask(i);
tag(i)(TAG_HIGH downto TAG_LOW) := newtag(TAG_HIGH downto TAG_LOW);
tag(i)(CTAG_LRRPOS) := wlrr(i);
tag(i)(CTAG_LOCKPOS) := wlock(i);
ctx(i) := r.mmctrl1.ctx;
ptag(i)(TAG_HIGH downto TAG_LOW) := newptag(TAG_HIGH downto TAG_LOW);
end loop;
dcrami.tag <= tag; -- virtual tag
dcrami.ptag <= ptag; -- physical tag
dcrami.ctx <= ctx; -- context
dcrami.tenable <= enable; -- virtual tag ram enable
dcrami.twrite <= ctwrite; -- virtual tag ram write (port 1)
dcrami.tpwrite <= ctpwrite; -- virtual tag ram write (port 2)
dcrami.flush <= flushlv;
dcrami.senable <= senable; -- physical tag ram enable
dcrami.swrite <= csnoopwe; -- physical tag ram write
dcrami.saddress(19 downto (OFFSET_HIGH - OFFSET_LOW +1)) <=
zero32(19 downto (OFFSET_HIGH - OFFSET_LOW +1));
dcrami.saddress(OFFSET_HIGH - OFFSET_LOW downto 0) <= snoopaddr;
dcrami.faddress(19 downto (OFFSET_HIGH - OFFSET_LOW +1)) <=
zero32(19 downto (OFFSET_HIGH - OFFSET_LOW +1));
dcrami.faddress(OFFSET_HIGH - OFFSET_LOW downto 0) <= flushaddr;
dcrami.snhit <= rs.snhit;
dcrami.snhitaddr(19 downto (OFFSET_HIGH - OFFSET_LOW +1)) <=
zero32(19 downto (OFFSET_HIGH - OFFSET_LOW +1));
dcrami.snhitaddr(OFFSET_HIGH - OFFSET_LOW downto 0) <= rs.addr(OFFSET_HIGH downto OFFSET_LOW);
dcrami.flushall <= r.flush2;
-- data ram inputs
dcrami.denable <= enable;
dcrami.address(19 downto (OFFSET_HIGH - LINE_LOW + 1)) <= zero32(19 downto (OFFSET_HIGH - LINE_LOW + 1));
dcrami.address(OFFSET_HIGH - LINE_LOW downto 0) <= taddr;
dcrami.data <= ddatainv;
dcrami.dwrite <= cdwrite;
dcrami.ldramin.address(23 downto 2) <= laddr(23 downto 2);
dcrami.ldramin.enable <= (lramcs or lramwr);
dcrami.ldramin.read <= rlramrd;
dcrami.ldramin.write <= lramwr;
-- memory controller inputs
mcdi.address <= r.wb.addr;
mcdi.data <= r.wb.data1;
mcdi.burst <= r.burst;
mcdi.size <= r.wb.size;
mcdi.read <= r.wb.read;
mcdi.asi <= r.wb.asi;
mcdi.lock <= r.wb.lock;
mcdi.req <= r.req;
mcdi.cache <= r.cache;
-- diagnostic instruction cache access
dco.icdiag.flush <= iflush;
dco.icdiag.pflush <= pflush;
dco.icdiag.pflushaddr <= pflushaddr;
dco.icdiag.pflushtyp <= pflushtyp;
dco.icdiag.read <= read;
dco.icdiag.tag <= not r.asi(0);
dco.icdiag.ctx <= r.asi(4); --ASI_ICTX "10101"
dco.icdiag.addr <= r.xaddress;
dco.icdiag.enable <= r.icenable;
dco.icdiag.ilramen <= r.ilramen;
dco.icdiag.cctrl <= r.cctrl;
-- IU data cache inputs
dco.data <= rdatav;
dco.mexc <= mexc;
dco.set <= conv_std_logic_vector(set, 2);
dco.hold <= r.holdn;
dco.mds <= mds;
dco.werr <= mcdo.werr;
dco.cache <= cache;
dco.hit <= r.hit;
if r.dstate = idle then dco.idle <= not r.stpend;
else dco.idle <= '0'; end if;
dco.cstat.cmiss <= r.cmiss;
dco.cstat.chold <= not r.holdn;
dco.cstat.tmiss <= mmudco.tlbmiss;
dco.cstat.mhold <= mhold;
dco.wbhold <= wbhold;
-- MMU
mmudci.trans_op <= mmudci_trans_op;
mmudci.transdata.data <= mmudci_transdata_data; --r.vaddr;
mmudci.transdata.su <= mmudci_su;
mmudci.transdata.read <= mmudci_read;
mmudci.transdata.isid <= id_dcache;
mmudci.transdata.wb_data <= dci.maddress;
mmudci.flush_op <= mmudci_flush_op;
mmudci.wb_op <= mmudci_wb_op;
mmudci.diag_op <= mmudci_diag_op;
mmudci.fsread <= mmudci_fsread;
mmudci.mmctrl1 <= r.mmctrl1;
end process;
-- Local registers
reg1 : process(clk)
begin
if rising_edge(clk) then
r <= c;
if RESET_ALL and (rst = '0') then r <= RRES; end if;
end if;
end process;
sn2 : if DSNOOP2 /= 0 generate
reg2 : process(sclk)
begin
if rising_edge(sclk) then
rs <= cs;
if RESET_ALL and (rst = '0') then rs <= SRES; end if;
end if;
end process;
end generate;
nosn2 : if DSNOOP2 = 0 generate
rs.snoop <= '0'; rs.addr <= (others => '0');
rs.snhit <= (others => '0'); rs.mask <= (others => '0');
end generate;
reg2 : if (DSETS>1) and (drepl = lru) generate
reg2 : process(clk)
begin
if rising_edge(clk) then
rl <= cl;
if RESET_ALL and (rst = '0') then rl <= LRES; end if;
end if;
end process;
end generate;
noreg2 : if (DSETS = 1) or (drepl /= lru) generate
rl.write <= '0'; rl.waddr <= (others => '0');
rl.set <= (others => '0'); rl.lru <= (others => (others => '0'));
end generate;
-- pragma translate_off
chk : process
begin
assert not ((DSETS > 2) and (drepl = lrr)) report
"Wrong data cache configuration detected: LRR replacement requires 2 ways"
severity failure;
assert not ((DSETS = 3) and (drepl = dir)) report
"Wrong data cache configuration detected: Direct replacement requires 2 or 4 ways"
severity failure;
wait;
end process;
-- pragma translate_on
end ;
| gpl-3.0 | 408c3c906719037aa5d07747d008caf6 | 0.524681 | 3.451342 | false | false | false | false |
GLADICOS/SPACEWIRESYSTEMC | rtl/RTL_SL/spwambapkg.vhd | 1 | 6,424 | --
-- VHDL package for SpaceWire AMBA interface.
--
-- This package depends on Gaisler GRLIB.
--
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library techmap;
use techmap.gencomp.all;
use work.spwpkg.all;
package spwambapkg is
-- AMBA plug&play device id
constant DEVICE_SPACEWIRELIGHT: amba_device_type := 16#131#;
-- Signals from SpaceWire core to AHB master.
type spw_ahbmst_in_type is record
-- Pulse high to start the RX DMA engine.
rxdma_start: std_ulogic;
-- Pulse high to start the TX DMA engine.
txdma_start: std_ulogic;
-- Stop TX DMA engine (at end of current burst).
txdma_cancel: std_ulogic;
-- Address of current RX descriptor (8-byte aligned).
rxdesc_ptr: std_logic_vector(31 downto 3);
-- Address of current TX descriptor (8-byte aligned).
txdesc_ptr: std_logic_vector(31 downto 3);
-- Read port of RX FIFO.
rxfifo_rdata: std_logic_vector(35 downto 0);
-- High if RX FIFO is empty.
rxfifo_empty: std_ulogic;
-- High if RX FIFO will be empty after one read.
-- May combinatorially depend on spw_ahbmst_out_type.rxfifo_read.
rxfifo_nxempty: std_ulogic;
-- High if TX FIFO is full or has room for at most one word.
txfifo_nxfull: std_ulogic;
-- High if TX FIFO is close to full (blocks refill).
txfifo_highw: std_ulogic;
end record;
-- Signals from AHB master to SpaceWire core.
type spw_ahbmst_out_type is record
-- High if the RX DMA engine is enabled.
rxdma_act: std_ulogic;
-- High if the TX DMA engine is enabled.
txdma_act: std_ulogic;
-- High if an error occurred on the AHB bus.
ahberror: std_ulogic;
-- Pulsed high to trigger an RX descriptor interrupt.
int_rxdesc: std_ulogic;
-- Pulsed high to trigger a TX descriptor interrupt.
int_txdesc: std_ulogic;
-- Pulsed high when a complete packet has been received.
int_rxpacket: std_ulogic;
-- Pulsed high to request the next RX descriptor address.
-- (rxdesc_ptr must be updated in the next clock cycle).
rxdesc_next: std_ulogic;
-- Pulsed high together with rxdesc_next to wrap the RX descriptor pointer.
rxdesc_wrap: std_ulogic;
-- Pulsed high to request the next TX descriptor address.
-- (txdesc_ptr must be updated in the next clock cycle).
txdesc_next: std_ulogic;
-- Pulsed high together with txdesc_next to wrap the TX descriptor pointer.
txdesc_wrap: std_ulogic;
-- Read strobe to RX fifo.
rxfifo_read: std_ulogic;
-- Write enable to TX fifo.
txfifo_write: std_ulogic;
-- Input port of TX fifo.
txfifo_wdata: std_logic_vector(35 downto 0);
end record;
-- SpaceWire core with AMBA interface.
component spwamba is
generic (
tech: integer range 0 to NTECH := DEFFABTECH;
hindex: integer; -- AHB master index
pindex: integer; -- APB slave index
paddr: integer; -- APB address range
pmask: integer := 16#fff#; -- APB address mask
pirq: integer; -- interrupt number
sysfreq: real; -- system clock frequency in Hz
txclkfreq: real := 0.0; -- txclk frequency in Hz
rximpl: spw_implementation_type := impl_generic;
rxchunk: integer range 1 to 4 := 1;
tximpl: spw_implementation_type := impl_generic;
timecodegen: boolean := true; -- support timecode generation
rxfifosize: integer range 6 to 12 := 8; -- size of receive FIFO (2-log of words)
txfifosize: integer range 2 to 12 := 8; -- size of transmit FIFO (2-log of words)
desctablesize: integer range 4 to 14 := 10; -- size of the DMA descriptor tables (2-log of descriptors)
maxburst: integer range 1 to 8 := 3 -- max burst length (2-log of words)
);
port (
clk: in std_logic; -- system clock.
rxclk: in std_logic; -- receiver sample clock
txclk: in std_logic; -- transmit clock
rstn: in std_logic; -- synchronous reset (active-low)
apbi: in apb_slv_in_type; -- APB slave input signals
apbo: out apb_slv_out_type; -- APB slave output signals
ahbi: in ahb_mst_in_type; -- AHB master input signals
ahbo: out ahb_mst_out_type; -- AHB master output signals
tick_in: in std_logic; -- pulse for timecode generation
tick_out: out std_logic; -- timecode received
spw_di: in std_logic; -- Data In signal from SpaceWire bus
spw_si: in std_logic; -- Strobe In signal from SpaceWire bus
spw_do: out std_logic; -- Data Out signal to SpaceWire bus
spw_so: out std_logic -- Strobe Out signal to SpaceWire bus
);
end component spwamba;
-- AHB master for AMBA interface.
component spwahbmst is
generic (
hindex: integer; -- AHB master index
hconfig: ahb_config_type; -- AHB plug&play information
maxburst: integer range 1 to 8 -- 2log of max burst length
);
port (
clk: in std_logic; -- system clock
rstn: in std_logic; -- synchronous reset (active-low)
msti: in spw_ahbmst_in_type; -- inputs from SpaceWire core
msto: out spw_ahbmst_out_type; -- outputs to SpaceWire core
ahbi: in ahb_mst_in_type; -- AHB master input signals
ahbo: out ahb_mst_out_type -- AHB master output signals
);
end component spwahbmst;
end package;
| gpl-3.0 | fe12a2700aa7662aaf5bb8d56cb75153 | 0.547167 | 4.294118 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/greth/ethernet_mac.vhd | 1 | 5,154 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.net.all;
library grlib;
use grlib.amba.all;
library techmap;
use techmap.gencomp.all;
package ethernet_mac is
type eth_tx_in_type is record
start : std_ulogic;
valid : std_ulogic;
data : std_logic_vector(31 downto 0);
full_duplex : std_ulogic;
length : std_logic_vector(10 downto 0);
col : std_ulogic;
crs : std_ulogic;
read_ack : std_ulogic;
end record;
type eth_tx_out_type is record
status : std_logic_vector(1 downto 0);
done : std_ulogic;
restart : std_ulogic;
read : std_ulogic;
tx_er : std_ulogic;
tx_en : std_ulogic;
txd : std_logic_vector(3 downto 0);
end record;
type eth_rx_in_type is record
writeok : std_ulogic;
rxen : std_ulogic;
rx_dv : std_ulogic;
rx_er : std_ulogic;
rxd : std_logic_vector(3 downto 0);
done_ack : std_ulogic;
write_ack : std_ulogic;
end record;
type eth_rx_out_type is record
write : std_ulogic;
data : std_logic_vector(31 downto 0);
done : std_ulogic;
length : std_logic_vector(10 downto 0);
status : std_logic_vector(2 downto 0);
start : std_ulogic;
end record;
type eth_mdio_in_type is record
mdioi : std_ulogic;
write : std_ulogic;
read : std_ulogic;
mdiostart : std_ulogic;
regadr : std_logic_vector(4 downto 0);
phyadr : std_logic_vector(4 downto 0);
data : std_logic_vector(15 downto 0);
end record;
type eth_mdio_out_type is record
mdc : std_ulogic;
mdioo : std_ulogic;
mdioen : std_ulogic;
data : std_logic_vector(15 downto 0);
done : std_ulogic;
error : std_ulogic;
end record;
type eth_tx_ahb_in_type is record
req : std_ulogic;
write : std_ulogic;
addr : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
end record;
type eth_tx_ahb_out_type is record
grant : std_ulogic;
data : std_logic_vector(31 downto 0);
ready : std_ulogic;
error : std_ulogic;
retry : std_ulogic;
end record;
type eth_rx_ahb_in_type is record
req : std_ulogic;
write : std_ulogic;
addr : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
end record;
type eth_rx_ahb_out_type is record
grant : std_ulogic;
ready : std_ulogic;
error : std_ulogic;
retry : std_ulogic;
data : std_logic_vector(31 downto 0);
end record;
type eth_rx_gbit_ahb_in_type is record
req : std_ulogic;
write : std_ulogic;
addr : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
size : std_logic_vector(1 downto 0);
end record;
component eth_ahb_mst is
generic(
hindex : integer := 0;
revision : integer := 0;
irq : integer := 0);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
tmsti : in eth_tx_ahb_in_type;
tmsto : out eth_tx_ahb_out_type;
rmsti : in eth_rx_ahb_in_type;
rmsto : out eth_rx_ahb_out_type
);
end component;
component eth_ahb_mst_gbit is
generic(
hindex : integer := 0;
revision : integer := 0;
irq : integer := 0);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
tmsti : in eth_tx_ahb_in_type;
tmsto : out eth_tx_ahb_out_type;
rmsti : in eth_rx_gbit_ahb_in_type;
rmsto : out eth_rx_ahb_out_type
);
end component;
end package;
| gpl-3.0 | eda736784b281445ad788fcf133e35d1 | 0.556073 | 3.571726 | false | false | false | false |
yishinli/emc2 | src/hal/drivers/m5i20/hostmot5_src/pwmref.vhd | 1 | 1,957 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity pwmref is
Port (
clk: in STD_LOGIC;
refcount: out STD_LOGIC_VECTOR (9 downto 0);
irqgen: out STD_LOGIC;
ibus: in STD_LOGIC_VECTOR (15 downto 0);
obus: out STD_LOGIC_VECTOR (15 downto 0);
irqdivload: in STD_LOGIC;
irqdivread: in STD_LOGIC;
phaseload: in STD_LOGIC;
phaseread: in STD_LOGIC
);
end pwmref;
architecture behavioral of pwmref is
signal count: STD_LOGIC_VECTOR (9 downto 0);
signal irqdivisor: STD_LOGIC_VECTOR (7 downto 0);
signal irqcounter: STD_LOGIC_VECTOR (7 downto 0);
signal phaseacc: STD_LOGIC_VECTOR (16 downto 0);
alias phasemsb: std_logic is phaseacc(16);
signal oldphasemsb: std_logic;
signal phaselatch: STD_LOGIC_VECTOR (15 downto 0);
begin
apwmref: process (clk,
irqdivload,
count,
irqcounter,
irqdivisor,
ibus,
irqdivread,
phaseread)
begin
if clk'event and clk = '1' then
phaseacc <= phaseacc + phaselatch;
oldphasemsb <= phasemsb;
if oldphasemsb /= phasemsb then
count <= count + 1;
if count = 0 then
irqcounter <= irqcounter -1;
if irqcounter = 0 then
irqgen <= '1';
irqcounter <= irqdivisor;
else
irqgen <= '0';
end if; -- irqcounter = 0
end if; -- count = 0
end if; -- old /= new
if irqdivload = '1' then
irqdivisor <= ibus(7 downto 0);
irqcounter <= irqdivisor;
end if;
if phaseload = '1' then
phaselatch <= ibus;
end if;
end if; -- clk
if irqdivread = '1' and phaseread = '0' then
obus(7 downto 0) <= irqdivisor;
obus(15 downto 8) <= x"00";
elsif phaseread = '1' and irqdivread = '0' then
obus <= phaselatch;
else
obus <= "ZZZZZZZZZZZZZZZZ";
end if;
refcount <= count;
end process;
end behavioral;
| lgpl-2.1 | 6b12661b667d5a09b0cd2f50a09a8245 | 0.605008 | 3.053042 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/i2c/i2c.vhd | 1 | 10,270 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: i2c
-- File: i2c.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: I2C interface package
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
package i2c is
type i2c_in_type is record
scl : std_ulogic;
sda : std_ulogic;
end record;
type i2c_out_type is record
scl : std_ulogic;
scloen : std_ulogic;
sda : std_ulogic;
sdaoen : std_ulogic;
enable : std_ulogic;
end record;
-- AMBA wrapper for OC I2C-master
component i2cmst
generic (
pindex : integer;
paddr : integer;
pmask : integer;
pirq : integer;
oepol : integer range 0 to 1 := 0;
filter : integer range 2 to 512 := 2;
dynfilt : integer range 0 to 1 := 0
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
i2ci : in i2c_in_type;
i2co : out i2c_out_type
);
end component;
component i2cmst_gen
generic (
oepol : integer range 0 to 1 := 0;
filter : integer range 2 to 512 := 2;
dynfilt : integer range 0 to 1 := 0
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
prdata : out std_logic_vector(31 downto 0);
irq : out std_logic;
i2ci_scl : in std_ulogic;
i2ci_sda : in std_ulogic;
i2co_scl : out std_ulogic;
i2co_scloen : out std_ulogic;
i2co_sda : out std_ulogic;
i2co_sdaoen : out std_ulogic;
i2co_enable : out std_ulogic
);
end component;
-- I2C slave
component i2cslv
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
hardaddr : integer range 0 to 1 := 0;
tenbit : integer range 0 to 1 := 0;
i2caddr : integer range 0 to 1023 := 0;
oepol : integer range 0 to 1 := 0;
filter : integer range 2 to 512 := 2
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
i2ci : in i2c_in_type;
i2co : out i2c_out_type
);
end component;
-- I2C to AHB bridge
type i2c2ahb_in_type is record
haddr : std_logic_vector(31 downto 0);
hmask : std_logic_vector(31 downto 0);
slvaddr : std_logic_vector(6 downto 0);
cfgaddr : std_logic_vector(6 downto 0);
en : std_ulogic;
end record;
type i2c2ahb_out_type is record
dma : std_ulogic;
wr : std_ulogic;
prot : std_ulogic;
end record;
component i2c2ahb
generic (
-- AHB Configuration
hindex : integer := 0;
--
ahbaddrh : integer := 0;
ahbaddrl : integer := 0;
ahbmaskh : integer := 0;
ahbmaskl : integer := 0;
-- I2C configuration
i2cslvaddr : integer range 0 to 127 := 0;
i2ccfgaddr : integer range 0 to 127 := 0;
oepol : integer range 0 to 1 := 0;
--
filter : integer range 2 to 512 := 2
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- AHB master interface
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
-- I2C signals
i2ci : in i2c_in_type;
i2co : out i2c_out_type
);
end component;
component i2c2ahb_apb
generic (
-- AHB Configuration
hindex : integer := 0;
--
ahbaddrh : integer := 0;
ahbaddrl : integer := 0;
ahbmaskh : integer := 0;
ahbmaskl : integer := 0;
resen : integer := 0;
-- APB configuration
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
-- I2C configuration
i2cslvaddr : integer range 0 to 127 := 0;
i2ccfgaddr : integer range 0 to 127 := 0;
oepol : integer range 0 to 1 := 0;
--
filter : integer range 2 to 512 := 2
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- AHB master interface
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
--
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
-- I2C signals
i2ci : in i2c_in_type;
i2co : out i2c_out_type
);
end component;
component i2c2ahbx
generic (
-- AHB configuration
hindex : integer := 0;
oepol : integer range 0 to 1 := 0;
filter : integer range 2 to 512 := 2
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- AHB master interface
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
-- I2C signals
i2ci : in i2c_in_type;
i2co : out i2c_out_type;
--
i2c2ahbi : in i2c2ahb_in_type;
i2c2ahbo : out i2c2ahb_out_type
);
end component;
component i2c2ahb_gen
generic (
ahbaddrh : integer := 0;
ahbaddrl : integer := 0;
ahbmaskh : integer := 0;
ahbmaskl : integer := 0;
-- I2C configuration
i2cslvaddr : integer range 0 to 127 := 0;
i2ccfgaddr : integer range 0 to 127 := 0;
oepol : integer range 0 to 1 := 0;
--
filter : integer range 2 to 512 := 2
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- AHB master interface
ahbi_hgrant : in std_ulogic;
ahbi_hready : in std_ulogic;
ahbi_hresp : in std_logic_vector(1 downto 0);
ahbi_hrdata : in std_logic_vector(31 downto 0);
--ahbo : out ahb_mst_out_type;
ahbo_hbusreq : out std_ulogic;
ahbo_hlock : out std_ulogic;
ahbo_htrans : out std_logic_vector(1 downto 0);
ahbo_haddr : out std_logic_vector(31 downto 0);
ahbo_hwrite : out std_ulogic;
ahbo_hsize : out std_logic_vector(2 downto 0);
ahbo_hburst : out std_logic_vector(2 downto 0);
ahbo_hprot : out std_logic_vector(3 downto 0);
ahbo_hwdata : out std_logic_vector(31 downto 0);
-- I2C signals
--i2ci : in i2c_in_type;
i2ci_scl : in std_ulogic;
i2ci_sda : in std_ulogic;
--i2co : out i2c_out_type
i2co_scl : out std_ulogic;
i2co_scloen : out std_ulogic;
i2co_sda : out std_ulogic;
i2co_sdaoen : out std_ulogic;
i2co_enable : out std_ulogic
);
end component;
component i2c2ahb_apb_gen
generic (
ahbaddrh : integer := 0;
ahbaddrl : integer := 0;
ahbmaskh : integer := 0;
ahbmaskl : integer := 0;
resen : integer := 0;
-- APB configuration
pindex : integer := 0; -- slave bus index
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
-- I2C configuration
i2cslvaddr : integer range 0 to 127 := 0;
i2ccfgaddr : integer range 0 to 127 := 0;
oepol : integer range 0 to 1 := 0;
--
filter : integer range 2 to 512 := 2
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- AHB master interface
--ahbi : in ahb_mst_in_type;
ahbi_hgrant : in std_ulogic;
ahbi_hready : in std_ulogic;
ahbi_hresp : in std_logic_vector(1 downto 0);
ahbi_hrdata : in std_logic_vector(31 downto 0);
--ahbo : out ahb_mst_out_type;
ahbo_hbusreq : out std_ulogic;
ahbo_hlock : out std_ulogic;
ahbo_htrans : out std_logic_vector(1 downto 0);
ahbo_haddr : out std_logic_vector(31 downto 0);
ahbo_hwrite : out std_ulogic;
ahbo_hsize : out std_logic_vector(2 downto 0);
ahbo_hburst : out std_logic_vector(2 downto 0);
ahbo_hprot : out std_logic_vector(3 downto 0);
ahbo_hwdata : out std_logic_vector(31 downto 0);
-- APB slave interface
apbi_psel : in std_ulogic;
apbi_penable : in std_ulogic;
apbi_paddr : in std_logic_vector(31 downto 0);
apbi_pwrite : in std_ulogic;
apbi_pwdata : in std_logic_vector(31 downto 0);
apbo_prdata : out std_logic_vector(31 downto 0);
apbo_irq : out std_logic;
-- I2C signals
--i2ci : in i2c_in_type;
i2ci_scl : in std_ulogic;
i2ci_sda : in std_ulogic;
--i2co : out i2c_out_type
i2co_scl : out std_ulogic;
i2co_scloen : out std_ulogic;
i2co_sda : out std_ulogic;
i2co_sdaoen : out std_ulogic;
i2co_enable : out std_ulogic
);
end component;
end;
| gpl-3.0 | 62dc576a35d1bb45d915802de192ced2 | 0.534859 | 3.461409 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/greth/adapters/elastic_buffer.vhd | 1 | 5,499 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: elastic_buffer
-- File: elastic_buffer.vhd
-- Author: Andrea Gianarro - Aeroflex Gaisler AB
-- Description: SGMII's elastic buffer
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
entity elastic_buffer is
generic (
tech : integer := 0;
abits : integer := 7
);
port (
wr_clk : in std_logic;
wr_rst : in std_logic;
wr_data : in std_logic_vector(9 downto 0);
rd_clk : in std_logic;
rd_rst : in std_logic;
rd_data : out std_logic_vector(9 downto 0)
) ;
end entity ;
architecture arch of elastic_buffer is
type rd_reg_type is record
fifo_out_d0 : std_logic_vector(9 downto 0);
fifo_out_d1 : std_logic_vector(9 downto 0);
insert_d0 : std_logic;
insert_d1 : std_logic;
start_reading : std_logic;
end record;
type wr_reg_type is record
fifo_in_d0 : std_logic_vector(9 downto 0);
fifo_in_d1 : std_logic_vector(9 downto 0);
delete_d0 : std_logic;
delete_d1 : std_logic;
end record;
constant rd_reg_none : rd_reg_type := (
fifo_out_d0 => (others => '0'),
fifo_out_d1 => (others => '0'),
insert_d0 => '0',
insert_d1 => '0',
start_reading => '0'
);
constant wr_reg_none : wr_reg_type := (
fifo_in_d0 => (others => '0'),
fifo_in_d1 => (others => '0'),
delete_d0 => '0',
delete_d1 => '0'
);
-- 8/10b encoding sequences
constant COMMAP : std_logic_vector(6 downto 0) := "0011111";
constant COMMAN : std_logic_vector(6 downto 0) := "1100000";
constant D16_2P : std_logic_vector(9 downto 0) := "0110110101";
constant D16_2N : std_logic_vector(9 downto 0) := "1001000101";
signal rd_r, rd_rin : rd_reg_type;
signal wr_r, wr_rin : wr_reg_type;
signal rd_en, wr_en : std_logic;
signal wrusedw_int, rdusedw_int : std_logic_vector(abits-1 downto 0);
signal fifo_out : std_logic_vector(9 downto 0);
signal rd_rstn, wr_rstn : std_logic;
begin
comb : process(rd_r, wr_r, fifo_out, wr_data, rdusedw_int, wrusedw_int, rd_rin, wr_rin, rd_rst, wr_rst)
variable rd_v : rd_reg_type;
variable wr_v : wr_reg_type;
variable insert : std_logic;
begin
rd_v := rd_rin;
wr_v := wr_rin;
rd_v.fifo_out_d0 := fifo_out;
rd_v.fifo_out_d1 := rd_r.fifo_out_d0;
rd_v.insert_d0 := '0';
rd_v.insert_d1 := rd_r.insert_d0;
rd_v.start_reading := rd_r.start_reading or rdusedw_int(rdusedw_int'left);
wr_v.fifo_in_d0 := wr_data;
wr_v.fifo_in_d1 := wr_r.fifo_in_d0;
wr_v.delete_d0 := '0';
wr_v.delete_d1 := wr_r.delete_d0;
if rdusedw_int(abits-1 downto abits-6) < "011111" and
((rd_r.fifo_out_d1(9 downto 3) = COMMAP and rd_r.fifo_out_d0 = D16_2N ) or (rd_r.fifo_out_d1(9 downto 3) = COMMAN and rd_r.fifo_out_d0 = D16_2P)) then
rd_v.insert_d0 := '1';
end if;
if wrusedw_int(abits-1 downto abits-6) > "100000" and
((wr_r.fifo_in_d1(9 downto 3) = COMMAP and wr_r.fifo_in_d0 = D16_2N ) or (wr_r.fifo_in_d1(9 downto 3) = COMMAN and wr_r.fifo_in_d0 = D16_2P)) then
wr_v.delete_d0 := '1';
end if;
-- inserting /I2/ when needed
if (rd_r.insert_d0 or rd_r.insert_d1) = '1' then
rd_v.fifo_out_d0 := rd_r.fifo_out_d1;
end if;
rd_en <= rd_r.start_reading and (not rd_rst) and not (rd_r.insert_d0 or rd_v.insert_d0);
-- deleting /I2/ when needed
wr_en <= (not wr_rst) and not (wr_r.delete_d0 or wr_v.delete_d0);
rd_data <= rd_r.fifo_out_d1;
rd_rin <= rd_v;
wr_rin <= wr_v;
end process;
rd_seq : process(rd_clk, rd_rst)
begin
if rd_rst = '1' then
rd_r <= rd_reg_none;
elsif rising_edge(rd_clk) then
rd_r <= rd_rin;
end if;
end process;
wr_seq : process(wr_clk, wr_rst)
begin
if wr_rst = '1' then
wr_r <= wr_reg_none;
elsif rising_edge(wr_clk) then
wr_r <= wr_rin;
end if;
end process;
-- Active low sync resets for the fifo
rd_rstn <= not(rd_rst);
wr_rstn <= not(wr_rst);
fifo0: syncfifo_2p
generic map(
tech => tech,
abits => abits,
dbits => 10
)
port map(
rclk => rd_clk,
rrstn => rd_rstn,
wrstn => wr_rstn,
renable => rd_en,
rfull => open,
rempty => open,
aempty => open,
rusedw => rdusedw_int,
dataout => fifo_out,
wclk => wr_clk,
write => wr_en,
wfull => open,
afull => open,
wempty => open,
wusedw => wrusedw_int,
datain => wr_r.fifo_in_d1
);
end architecture ;
| gpl-3.0 | eeed0e1df790ef78d4df525afa673143 | 0.607019 | 2.629842 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/techmap/maps/iopad_ddr.vhd | 1 | 4,955 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: iopad_ddr, iopad_ddrv, iopad_ddrvv
-- File: iopad_ddr.vhd
-- Author: Jan Andersson - Aeroflex Gaisler
-- Description: Wrapper that instantiates an iopad connected to DDR register.
-- Special case for easic90 tech since this tech requires that
-- oe is directly connected between DDR register and pad.
------------------------------------------------------------------------------
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allddr.all;
use techmap.allpads.all;
entity iopad_ddr is
generic (
tech : integer := 0;
level : integer := 0;
slew : integer := 0;
voltage : integer := x33v;
strength : integer := 12;
oepol : integer := 0);
port (
pad : inout std_ulogic;
i1, i2 : in std_ulogic; -- Input H and L
en : in std_ulogic; -- Output enable
o1, o2 : out std_ulogic; -- Output H and L
c1, c2 : in std_ulogic;
ce : in std_ulogic;
r : in std_ulogic;
s : in std_ulogic);
end;
architecture rtl of iopad_ddr is
signal oe, oen, d, q : std_ulogic;
begin
def: if (tech /= easic90) generate
p : iopad generic map (tech, level, slew, voltage, strength, oepol)
port map (pad, q, en, d);
ddrregi : ddr_ireg generic map (tech)
port map (o1, o2, c1, c2, ce, d, r, s);
ddrrego : ddr_oreg generic map (tech)
port map (q, c1, c2, ce, i1, i2, r, s);
oe <= '0'; oen <= '0'; -- Not used in this configuration
end generate def;
nex : if (tech = easic90) generate
oen <= not en when oepol /= padoen_polarity(tech) else en;
p : nextreme_iopad generic map (level, slew, voltage, strength)
port map (pad, q, oe, d);
ddrregi : nextreme_iddr_reg
port map (ck => c1, d => d, qh => o1, ql => o2, rstb => r);
ddrrego : nextreme_oddr_reg
port map (ck => c1, dh => i1, dl => i2, doe => oen, q => q,
oe => oe, rstb => r);
end generate;
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity iopad_ddrv is
generic (
tech : integer := 0;
level : integer := 0;
slew : integer := 0;
voltage : integer := x33v;
strength : integer := 12;
width : integer := 1;
oepol : integer := 0);
port (
pad : inout std_logic_vector(width-1 downto 0);
i1, i2 : in std_logic_vector(width-1 downto 0);
en : in std_ulogic;
o1, o2 : out std_logic_vector(width-1 downto 0);
c1, c2 : in std_ulogic;
ce : in std_ulogic;
r : in std_ulogic;
s : in std_ulogic);
end;
architecture rtl of iopad_ddrv is
begin
v : for j in width-1 downto 0 generate
x0 : iopad_ddr generic map (tech, level, slew, voltage, strength, oepol)
port map (pad(j), i1(j), i2(j), en, o1(j), o2(j), c1, c2, ce, r, s);
end generate;
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity iopad_ddrvv is
generic (
tech : integer := 0;
level : integer := 0;
slew : integer := 0;
voltage : integer := x33v;
strength : integer := 12;
width : integer := 1;
oepol : integer := 0);
port (
pad : inout std_logic_vector(width-1 downto 0);
i1, i2 : in std_logic_vector(width-1 downto 0);
en : in std_logic_vector(width-1 downto 0);
o1, o2 : out std_logic_vector(width-1 downto 0);
c1, c2 : in std_ulogic;
ce : in std_ulogic;
r : in std_ulogic;
s : in std_ulogic);
end;
architecture rtl of iopad_ddrvv is
begin
v : for j in width-1 downto 0 generate
x0 : iopad_ddr generic map (tech, level, slew, voltage, strength, oepol)
port map (pad(j), i1(j), i2(j), en(j), o1(j), o2(j), c1, c2, ce, r, s);
end generate;
end;
| gpl-3.0 | 04e03e6036733ae859f537ddf8a9a9cd | 0.581029 | 3.382253 | false | false | false | false |
kdgwill/VHDL_Framer_Example | VHDL_Framer_Example/Example2/Add.vhd | 1 | 6,569 | -- megafunction wizard: %PARALLEL_ADD%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: parallel_add
-- ============================================================
-- File Name: Add.vhd
-- Megafunction Name(s):
-- parallel_add
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 11.1 Build 173 11/01/2011 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2011 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
ENTITY Add IS
PORT
(
data0x : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
data1x : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END Add;
ARCHITECTURE SYN OF add IS
-- type ALTERA_MF_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC;
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL sub_wire2 : ALTERA_MF_LOGIC_2D (1 DOWNTO 0, 31 DOWNTO 0);
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (31 DOWNTO 0);
BEGIN
sub_wire3 <= data0x(31 DOWNTO 0);
result <= sub_wire0(31 DOWNTO 0);
sub_wire1 <= data1x(31 DOWNTO 0);
sub_wire2(1, 0) <= sub_wire1(0);
sub_wire2(1, 1) <= sub_wire1(1);
sub_wire2(1, 2) <= sub_wire1(2);
sub_wire2(1, 3) <= sub_wire1(3);
sub_wire2(1, 4) <= sub_wire1(4);
sub_wire2(1, 5) <= sub_wire1(5);
sub_wire2(1, 6) <= sub_wire1(6);
sub_wire2(1, 7) <= sub_wire1(7);
sub_wire2(1, 8) <= sub_wire1(8);
sub_wire2(1, 9) <= sub_wire1(9);
sub_wire2(1, 10) <= sub_wire1(10);
sub_wire2(1, 11) <= sub_wire1(11);
sub_wire2(1, 12) <= sub_wire1(12);
sub_wire2(1, 13) <= sub_wire1(13);
sub_wire2(1, 14) <= sub_wire1(14);
sub_wire2(1, 15) <= sub_wire1(15);
sub_wire2(1, 16) <= sub_wire1(16);
sub_wire2(1, 17) <= sub_wire1(17);
sub_wire2(1, 18) <= sub_wire1(18);
sub_wire2(1, 19) <= sub_wire1(19);
sub_wire2(1, 20) <= sub_wire1(20);
sub_wire2(1, 21) <= sub_wire1(21);
sub_wire2(1, 22) <= sub_wire1(22);
sub_wire2(1, 23) <= sub_wire1(23);
sub_wire2(1, 24) <= sub_wire1(24);
sub_wire2(1, 25) <= sub_wire1(25);
sub_wire2(1, 26) <= sub_wire1(26);
sub_wire2(1, 27) <= sub_wire1(27);
sub_wire2(1, 28) <= sub_wire1(28);
sub_wire2(1, 29) <= sub_wire1(29);
sub_wire2(1, 30) <= sub_wire1(30);
sub_wire2(1, 31) <= sub_wire1(31);
sub_wire2(0, 0) <= sub_wire3(0);
sub_wire2(0, 1) <= sub_wire3(1);
sub_wire2(0, 2) <= sub_wire3(2);
sub_wire2(0, 3) <= sub_wire3(3);
sub_wire2(0, 4) <= sub_wire3(4);
sub_wire2(0, 5) <= sub_wire3(5);
sub_wire2(0, 6) <= sub_wire3(6);
sub_wire2(0, 7) <= sub_wire3(7);
sub_wire2(0, 8) <= sub_wire3(8);
sub_wire2(0, 9) <= sub_wire3(9);
sub_wire2(0, 10) <= sub_wire3(10);
sub_wire2(0, 11) <= sub_wire3(11);
sub_wire2(0, 12) <= sub_wire3(12);
sub_wire2(0, 13) <= sub_wire3(13);
sub_wire2(0, 14) <= sub_wire3(14);
sub_wire2(0, 15) <= sub_wire3(15);
sub_wire2(0, 16) <= sub_wire3(16);
sub_wire2(0, 17) <= sub_wire3(17);
sub_wire2(0, 18) <= sub_wire3(18);
sub_wire2(0, 19) <= sub_wire3(19);
sub_wire2(0, 20) <= sub_wire3(20);
sub_wire2(0, 21) <= sub_wire3(21);
sub_wire2(0, 22) <= sub_wire3(22);
sub_wire2(0, 23) <= sub_wire3(23);
sub_wire2(0, 24) <= sub_wire3(24);
sub_wire2(0, 25) <= sub_wire3(25);
sub_wire2(0, 26) <= sub_wire3(26);
sub_wire2(0, 27) <= sub_wire3(27);
sub_wire2(0, 28) <= sub_wire3(28);
sub_wire2(0, 29) <= sub_wire3(29);
sub_wire2(0, 30) <= sub_wire3(30);
sub_wire2(0, 31) <= sub_wire3(31);
parallel_add_component : parallel_add
GENERIC MAP (
msw_subtract => "NO",
pipeline => 0,
representation => "UNSIGNED",
result_alignment => "LSB",
shift => 0,
size => 2,
width => 32,
widthr => 32,
lpm_type => "parallel_add"
)
PORT MAP (
data => sub_wire2,
result => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: MSW_SUBTRACT STRING "NO"
-- Retrieval info: CONSTANT: PIPELINE NUMERIC "0"
-- Retrieval info: CONSTANT: REPRESENTATION STRING "UNSIGNED"
-- Retrieval info: CONSTANT: RESULT_ALIGNMENT STRING "LSB"
-- Retrieval info: CONSTANT: SHIFT NUMERIC "0"
-- Retrieval info: CONSTANT: SIZE NUMERIC "2"
-- Retrieval info: CONSTANT: WIDTH NUMERIC "32"
-- Retrieval info: CONSTANT: WIDTHR NUMERIC "32"
-- Retrieval info: USED_PORT: data0x 0 0 32 0 INPUT NODEFVAL "data0x[31..0]"
-- Retrieval info: USED_PORT: data1x 0 0 32 0 INPUT NODEFVAL "data1x[31..0]"
-- Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL "result[31..0]"
-- Retrieval info: CONNECT: @data 1 0 32 0 data0x 0 0 32 0
-- Retrieval info: CONNECT: @data 1 1 32 0 data1x 0 0 32 0
-- Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL Add.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Add.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Add.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Add.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Add_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
| gpl-3.0 | 2bd2de7a78731ab871188d86a78a839a | 0.585782 | 2.746237 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/i2c/i2cmst_gen.vhd | 1 | 3,431 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: i2cmst_gen
-- File: i2cmst_gen.vhd
-- Author: Jan Andersson - Aeroflex Gaisler
-- Contact: [email protected]
-- Description: Generic I2CMST, see i2cmst.vhd
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.i2c.all;
entity i2cmst_gen is
generic (
oepol : integer range 0 to 1 := 0; -- output enable polarity
filter : integer range 2 to 512 := 2; -- filter bit size
dynfilt : integer range 0 to 1 := 0);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- APB signals
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
prdata : out std_logic_vector(31 downto 0);
irq : out std_logic;
-- I2C signals
--i2ci : in i2c_in_type;
i2ci_scl : in std_ulogic;
i2ci_sda : in std_ulogic;
--i2co : out i2c_out_type
i2co_scl : out std_ulogic;
i2co_scloen : out std_ulogic;
i2co_sda : out std_ulogic;
i2co_sdaoen : out std_ulogic;
i2co_enable : out std_ulogic
);
end entity i2cmst_gen;
architecture rtl of i2cmst_gen is
-- APB signals
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_type;
-- I2C signals
signal i2ci : i2c_in_type;
signal i2co : i2c_out_type;
begin
apbi.psel(0) <= psel;
apbi.psel(1 to NAPBSLV-1) <= (others => '0');
apbi.penable <= penable;
apbi.paddr <= paddr;
apbi.pwrite <= pwrite;
apbi.pwdata <= pwdata;
apbi.pirq <= (others => '0');
apbi.testen <= '0';
apbi.testrst <= '0';
apbi.scanen <= '0';
apbi.testoen <= '0';
prdata <= apbo.prdata;
irq <= apbo.pirq(0);
i2ci.scl <= i2ci_scl;
i2ci.sda <= i2ci_sda;
i2co_scl <= i2co.scl;
i2co_scloen <= i2co.scloen;
i2co_sda <= i2co.sda;
i2co_sdaoen <= i2co.sdaoen;
i2co_enable <= i2co.enable;
i2c0 : i2cmst
generic map (pindex => 0, paddr => 0, pmask => 0, pirq => 0,
oepol => oepol, filter => filter, dynfilt => dynfilt)
port map (rstn, clk, apbi, apbo, i2ci, i2co);
end architecture rtl;
| gpl-3.0 | 290e06022e3d56dbaede403a5500d5ee | 0.595453 | 3.295869 | false | false | false | false |
pwsoft/fpga_examples | quartus/chameleon/chameleon_v5_hwtest/pll8.vhd | 2 | 19,665 | -- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: pll8.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2009 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY pll8 IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
c2 : OUT STD_LOGIC ;
c3 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END pll8;
ARCHITECTURE SYN OF pll8 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC ;
SIGNAL sub_wire6 : STD_LOGIC ;
SIGNAL sub_wire7 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire8_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire8 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
clk2_divide_by : NATURAL;
clk2_duty_cycle : NATURAL;
clk2_multiply_by : NATURAL;
clk2_phase_shift : STRING;
clk3_divide_by : NATURAL;
clk3_duty_cycle : NATURAL;
clk3_multiply_by : NATURAL;
clk3_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
self_reset_on_loss_lock : STRING;
width_clock : NATURAL
);
PORT (
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
locked : OUT STD_LOGIC ;
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire8_bv(0 DOWNTO 0) <= "0";
sub_wire8 <= To_stdlogicvector(sub_wire8_bv);
sub_wire4 <= sub_wire0(3);
sub_wire3 <= sub_wire0(2);
sub_wire2 <= sub_wire0(1);
sub_wire1 <= sub_wire0(0);
c0 <= sub_wire1;
c1 <= sub_wire2;
c2 <= sub_wire3;
c3 <= sub_wire4;
locked <= sub_wire5;
sub_wire6 <= inclk0;
sub_wire7 <= sub_wire8(0 DOWNTO 0) & sub_wire6;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 2,
clk0_duty_cycle => 50,
clk0_multiply_by => 25,
clk0_phase_shift => "0",
clk1_divide_by => 2,
clk1_duty_cycle => 50,
clk1_multiply_by => 25,
clk1_phase_shift => "5000",
clk2_divide_by => 4,
clk2_duty_cycle => 50,
clk2_multiply_by => 75,
clk2_phase_shift => "0",
clk3_divide_by => 4,
clk3_duty_cycle => 50,
clk3_multiply_by => 75,
clk3_phase_shift => "3333",
compensate_clock => "CLK0",
inclk0_input_frequency => 125000,
intended_device_family => "Cyclone III",
lpm_hint => "CBX_MODULE_PREFIX=pll8",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_USED",
port_clk3 => "PORT_USED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
self_reset_on_loss_lock => "ON",
width_clock => 5
)
PORT MAP (
inclk => sub_wire7,
clk => sub_wire0,
locked => sub_wire5
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "2"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "2"
-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "100.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "100.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "150.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "150.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "8.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "304.000"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "25"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "25"
-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "150.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "150.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "180.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "180.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll8.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "1"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK3 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "25"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "25"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "5000"
-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "4"
-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "75"
-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "4"
-- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "75"
-- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "3333"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "125000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "ON"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
-- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll8.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll8.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll8.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll8.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll8.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll8_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll8_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll8_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
| lgpl-2.1 | 333d97e32dc74a06e64a2cf87211d838 | 0.700686 | 3.2639 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-terasic-de4/leon3mp.vhd | 1 | 47,331 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- LEON3 Demonstration design
-- Copyright (C) 2014 Aeroflex Gaisler
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.all;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.spi.all;
use gaisler.can.all;
use gaisler.net.all;
use gaisler.jtag.all;
use gaisler.ddrpkg.all;
use gaisler.l2cache.all;
-- pragma translate_off
use gaisler.sim.all;
-- pragma translate_on
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
-- clocks
OSC_50_BANK2 : in std_logic;
OSC_50_BANK3 : in std_logic;
OSC_50_BANK4 : in std_logic;
OSC_50_BANK5 : in std_logic;
OSC_50_BANK6 : in std_logic;
OSC_50_BANK7 : in std_logic;
PLL_CLKIN_p : in std_logic;
SMA_CLKIN_p : in std_logic;
-- SMA_GXBCLK_p : in std_logic;
GCLKIN : in std_logic;
-- GCLKOUT_FPGA : out std_logic;
-- SMA_CLKOUT_p : out std_logic;
-- cpu reset
CPU_RESET_n : in std_ulogic;
-- max i/o
-- MAX_CONF_D : inout std_logic_vector(3 downto 0);
-- MAX_I2C_SCLK : out std_logic;
-- MAX_I2C_SDAT : inout std_logic;
-- LEDs
LED : out std_logic_vector(7 downto 0);
-- buttons
BUTTON : in std_logic_vector(3 downto 0);
-- switches
SW : in std_logic_vector(3 downto 0);
-- slide switches
SLIDE_SW : in std_logic_vector(3 downto 0);
-- temperature
-- TEMP_SMCLK : out std_logic;
-- TEMP_SMDAT : inout std_logic;
-- TEMP_INT_n : in std_logic;
-- current
CSENSE_ADC_FO : out std_logic;
CSENSE_SCK : inout std_logic;
CSENSE_SDI : out std_logic;
CSENSE_SDO : in std_logic;
CSENSE_CS_n : out std_logic_vector(1 downto 0);
-- fan
FAN_CTRL : out std_logic;
-- eeprom
EEP_SCL : out std_logic;
EEP_SDA : inout std_logic;
-- sdcard
-- SD_CLK : out std_logic;
-- SD_CMD : inout std_logic;
-- SD_DAT : inout std_logic_vector(3 downto 0);
-- SD_WP_n : in std_logic;
-- Ethernet interfaces
ETH_INT_n : in std_logic_vector(3 downto 0);
ETH_MDC : out std_logic_vector(3 downto 0);
ETH_MDIO : inout std_logic_vector(3 downto 0);
ETH_RST_n : out std_ulogic;
ETH_RX_p : in std_logic_vector(3 downto 0);
ETH_TX_p : out std_logic_vector(3 downto 0);
-- PCIe interfaces
-- PCIE_PREST_n : in std_ulogic;
-- PCIE_REFCLK_p : in std_ulogic;
-- PCIE_RX_p : in std_logic_vector(7 downto 0);
-- PCIE_SMBCLK : in std_logic;
-- PCIE_SMBDAT : inout std_logic;
-- PCIE_TX_p : out std_logic_vector(7 downto 0);
-- PCIE_WAKE_n : out std_logic;
-- Flash and SRAM, shared signals
FSM_A : out std_logic_vector(25 downto 1);
FSM_D : inout std_logic_vector(15 downto 0);
-- Flash control
FLASH_ADV_n : out std_ulogic;
FLASH_CE_n : out std_ulogic;
FLASH_CLK : out std_ulogic;
FLASH_OE_n : out std_ulogic;
FLASH_RESET_n : out std_ulogic;
FLASH_RYBY_n : in std_ulogic;
FLASH_WE_n : out std_ulogic;
-- SSRAM control
SSRAM_ADV : out std_ulogic;
SSRAM_BWA_n : out std_ulogic;
SSRAM_BWB_n : out std_ulogic;
SSRAM_CE_n : out std_ulogic;
SSRAM_CKE_n : out std_ulogic;
SSRAM_CLK : out std_ulogic;
SSRAM_OE_n : out std_ulogic;
SSRAM_WE_n : out std_ulogic;
-- USB OTG
-- OTG_A : out std_logic_vector(17 downto 1);
-- OTG_CS_n : out std_ulogic;
-- OTG_D : inout std_logic_vector(31 downto 0);
-- OTG_DC_DACK : out std_ulogic;
-- OTG_DC_DREQ : in std_ulogic;
-- OTG_DC_IRQ : in std_ulogic;
-- OTG_HC_DACK : out std_ulogic;
-- OTG_HC_DREQ : in std_ulogic;
-- OTG_HC_IRQ : in std_ulogic;
-- OTG_OE_n : out std_ulogic;
-- OTG_RESET_n : out std_ulogic;
-- OTG_WE_n : out std_ulogic;
-- SATA
-- SATA_REFCLK_p : in std_logic;
-- SATA_HOST_RX_p : in std_logic_vector(1 downto 0);
-- SATA_HOST_TX_p : out std_logic_vector(1 downto 0);
-- SATA_DEVICE_RX_p : in std_logic_vector(1 downto 0);
-- SATA_DEVICE_TX_p : out std_logic_vector(1 downto 0);
-- DDR2 SODIMM
M1_DDR2_addr : out std_logic_vector(15 downto 0);
M1_DDR2_ba : out std_logic_vector(2 downto 0);
M1_DDR2_cas_n : out std_logic;
M1_DDR2_cke : out std_logic_vector(1 downto 0);
M1_DDR2_clk : out std_logic_vector(1 downto 0);
M1_DDR2_clk_n : out std_logic_vector(1 downto 0);
M1_DDR2_cs_n : out std_logic_vector(1 downto 0);
M1_DDR2_dm : out std_logic_vector(7 downto 0);
M1_DDR2_dq : inout std_logic_vector(63 downto 0);
M1_DDR2_dqs : inout std_logic_vector(7 downto 0);
M1_DDR2_dqsn : inout std_logic_vector(7 downto 0);
M1_DDR2_odt : out std_logic_vector(1 downto 0);
M1_DDR2_ras_n : out std_logic;
-- M1_DDR2_SA : out std_logic_vector(1 downto 0);
-- M1_DDR2_SCL : out std_logic;
-- M1_DDR2_SDA : inout std_logic;
M1_DDR2_we_n : out std_logic;
M1_DDR2_oct_rdn : in std_logic;
M1_DDR2_oct_rup : in std_logic;
-- DDR2 SODIMM
-- M2_DDR2_addr : out std_logic_vector(15 downto 0);
-- M2_DDR2_ba : out std_logic_vector(2 downto 0);
-- M2_DDR2_cas_n : out std_logic;
-- M2_DDR2_cke : out std_logic_vector(1 downto 0);
-- M2_DDR2_clk : out std_logic_vector(1 downto 0);
-- M2_DDR2_clk_n : out std_logic_vector(1 downto 0);
-- M2_DDR2_cs_n : out std_logic_vector(1 downto 0);
-- M2_DDR2_dm : out std_logic_vector(7 downto 0);
-- M2_DDR2_dq : inout std_logic_vector(63 downto 0);
-- M2_DDR2_dqs : inout std_logic_vector(7 downto 0);
-- M2_DDR2_dqsn : inout std_logic_vector(7 downto 0);
-- M2_DDR2_odt : out std_logic_vector(1 downto 0);
-- M2_DDR2_ras_n : out std_logic;
-- M2_DDR2_SA : out std_logic_vector(1 downto 0);
-- M2_DDR2_SCL : out std_logic;
-- M2_DDR2_SDA : inout std_logic;
-- M2_DDR2_we_n : out std_logic;
-- GPIO
GPIO0_D : inout std_logic_vector(35 downto 0);
-- GPIO1_D : inout std_logic_vector(35 downto 0);
-- Ext I/O
-- EXT_IO : inout std_logic;
-- HSMC A
-- HSMA_CLKIN_n1 : in std_logic;
-- HSMA_CLKIN_n2 : in std_logic;
-- HSMA_CLKIN_p1 : in std_logic;
-- HSMA_CLKIN_p2 : in std_logic;
-- HSMA_CLKIN0 : in std_logic;
HSMA_CLKOUT_n2 : out std_logic;
HSMA_CLKOUT_p2 : out std_logic;
-- HSMA_D : inout std_logic_vector(3 downto 0);
-- HSMA_GXB_RX_p : in std_logic_vector(3 downto 0);
-- HSMA_GXB_TX_p : out std_logic_vector(3 downto 0);
-- HSMA_OUT_n1 : inout std_logic;
-- HSMA_OUT_p1 : inout std_logic;
-- HSMA_OUT0 : inout std_logic;
-- HSMA_REFCLK_p : in std_logic;
-- HSMA_RX_n : inout std_logic_vector(16 downto 0);
-- HSMA_RX_p : inout std_logic_vector(16 downto 0);
-- HSMA_TX_n : inout std_logic_vector(16 downto 0);
-- HSMA_TX_p : inout std_logic_vector(16 downto 0);
-- HSMC_B
-- HSMB_CLKIN_n1 : in std_logic;
-- HSMB_CLKIN_n2 : in std_logic;
-- HSMB_CLKIN_p1 : in std_logic;
-- HSMB_CLKIN_p2 : in std_logic;
-- HSMB_CLKIN0 : in std_logic;
-- HSMB_CLKOUT_n2 : out std_logic;
-- HSMB_CLKOUT_p2 : out std_logic;
-- HSMB_D : inout std_logic_vector(3 downto 0);
-- HSMB_GXB_RX_p : in std_logic_vector(3 downto 0);
-- HSMB_GXB_TX_p : out std_logic_vector(3 downto 0);
-- HSMB_OUT_n1 : inout std_logic;
-- HSMB_OUT_p1 : inout std_logic;
-- HSMB_OUT0 : inout std_logic;
-- HSMB_REFCLK_p : in std_logic;
-- HSMB_RX_n : inout std_logic_vector(16 downto 0);
-- HSMB_RX_p : inout std_logic_vector(16 downto 0);
-- HSMB_TX_n : inout std_logic_vector(16 downto 0);
-- HSMB_TX_p : inout std_logic_vector(16 downto 0);
-- HSMC i2c
-- HSMC_SCL : out std_logic;
-- HSMC_SDA : inout std_logic;
-- Display
-- SEG0_D : out std_logic_vector(6 downto 0);
-- SEG1_D : out std_logic_vector(6 downto 0);
-- SEG0_DP : out std_ulogic;
-- SEG1_DP : out std_ulogic;
-- UART
UART_CTS : out std_ulogic;
UART_RTS : in std_ulogic;
UART_RXD : in std_ulogic;
UART_TXD : out std_ulogic
);
end;
architecture rtl of leon3mp is
constant blength : integer := 12;
constant fifodepth : integer := 8;
constant burstlen : integer := 16; -- burst length in 32-bit words
signal vcc, gnd : std_logic_vector(7 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal del_addr : std_logic_vector(25 downto 1);
signal del_ce, del_we: std_logic;
signal del_bwa_n, del_bwb_n: std_logic_vector(1 downto 0);
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal edcl_ahbmi : ahb_mst_in_type;
signal edcl_ahbmo : ahb_mst_out_vector_type(1 downto 0);
signal mem_ahbsi : ahb_slv_in_type;
signal mem_ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal mem_ahbmi : ahb_mst_in_type;
signal mem_ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, rstraw : std_logic;
signal cgi, cgi_125 : clkgen_in_type;
signal cgo, cgo_125 : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal spii, spislvi : spi_in_type;
signal spio, spislvo : spi_out_type;
signal slvsel : std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0);
signal stati : ahbstat_in_type;
signal gpti : gptimer_in_type;
signal gpto : gptimer_out_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal dsubren : std_logic;
signal tck, tms, tdi, tdo : std_logic;
signal fpi : grfpu_in_vector_type;
signal fpo : grfpu_out_vector_type;
signal nolock : ahb2ahb_ctrl_type;
signal noifctrl : ahb2ahb_ifctrl_type;
signal e0_reset, e1_reset : std_logic;
signal e0_mdio_o, e1_mdio_o : std_logic;
signal e0_mdio_oe, e1_mdio_oe : std_logic;
signal e0_mdio_i, e1_mdio_i : std_logic;
signal e0_mdc, e1_mdc : std_logic;
signal e0_mdint, e1_mdint : std_logic;
signal ref_clk, ref_rstn, ref_rst: std_logic;
signal led_crs1, led_link1, led_col1, led_an1, led_char_err1, led_disp_err1 : std_logic;
signal led_crs2, led_link2, led_col2, led_an2, led_char_err2, led_disp_err2 : std_logic;
signal led1_int, led2_int, led3_int, led4_int, led5_int, led6_int, led7_int : std_logic;
constant BOARD_FREQ : integer := 100000; -- Board frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
constant IOAEN : integer := 1;
constant OEPOL : integer := padoen_polarity(padtech);
constant DEBUG_BUS : integer := CFG_L2_EN;
constant EDCL_SEP_AHB : integer := CFG_L2_EN;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute keep : boolean;
signal ddr_clkv : std_logic_vector(2 downto 0);
signal ddr_clkbv : std_logic_vector(2 downto 0);
signal ddr_ckev : std_logic_vector(1 downto 0);
signal ddr_csbv : std_logic_vector(1 downto 0);
signal ddr_clk_fb : std_ulogic;
signal clkm125 : std_logic;
signal clklock, lock, clkml : std_logic;
signal gprego : std_logic_vector(15 downto 0);
signal slide_switch: std_logic_vector(3 downto 0);
signal counter1 : std_logic_vector(26 downto 0);
signal counter2 : std_logic_vector(3 downto 0);
signal bitslip_int : std_logic;
signal tx_rstn0, tx_rstn1, rx_rstn0, rx_rstn1 : std_logic;
signal clkddr_l : std_logic;
begin
nolock <= ahb2ahb_ctrl_none;
noifctrl <= ahb2ahb_ifctrl_none;
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1');
gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
clklock <= cgo.clklock and lock;
clkgen0 : clkgen -- clock generator using toplevel generic 'freq'
generic map (tech => CFG_CLKTECH, clk_mul => CFG_CLKMUL,
clk_div => CFG_CLKDIV, sdramen => 0,
noclkfb => CFG_CLK_NOFB, freq => BOARD_FREQ)
port map (clkin => PLL_CLKIN_p, pciclkin => gnd(0), clk => clkm, clkn => open,
clk2x => open, sdclk => open, pciclk => open,
cgi => cgi, cgo => cgo);
-- clk125_pad : clkpad generic map (tech => padtech) port map (clk125, lclk125);
-- clkm125 <= clk125;
rst0 : rstgen -- reset generator
port map (CPU_RESET_n, clkm, clklock, rstn, rstraw);
led2_pad : outpad generic map (tech => padtech) port map (LED(2), lock);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT, fpnpen => CFG_FPNPEN,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => IOAEN,
nahbm => CFG_NCPU+(CFG_AHB_UART+CFG_AHB_JTAG)*(1-DEBUG_BUS)+
DEBUG_BUS+CFG_GRETH+CFG_GRETH2,
nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor -----------------------------------------
----------------------------------------------------------------------
cpu : for i in 0 to CFG_NCPU-1 generate
nosh : if CFG_GRFPUSH = 0 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU*(1-CFG_GRFPUSH), CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
0, 0, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
end generate;
sh : if CFG_GRFPUSH = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3sh -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
0, 0, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), fpi(i), fpo(i));
end generate;
grfpush0 : grfpushwx generic map ((CFG_FPU-1), CFG_NCPU, fabtech)
port map (clkm, rstn, fpi, fpo);
end generate;
errorn_pad : odpad generic map (tech => padtech) port map (LED(0), dbgo(0).error);
----------------------------------------------------------------------
--- Debug -----------------------------------------
----------------------------------------------------------------------
-- Debug DSU and debug links can be connected to the system on two
-- ways:
--
-- a) Directly to the main AHB bus
-- b) Connected via a dedicated debug AHB bus that is connected to
-- the main AHB bus via a AHB/AHB bridge.
dsui.enable <= '1';
dsubre_pad : inpad generic map (tech => padtech) port map (BUTTON(0), dsubren);
dsui.break <= not dsubren;
dsuact_pad : outpad generic map (tech => padtech) port map (LED(1), dsuo.active);
dui.rxd <= uart_rxd when slide_sw(0) = '0' else '1';
nodbgbus : if DEBUG_BUS /= 1 generate
-- DSU and debug links directly connected to main bus
edcl_ahbmi <= ahbmi;
-- EDCL ahbmo interfaces are not used in this configuration
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#E00#, hmask => 16#FC0#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0: ahbuart -- Debug UART
generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
end generate;
-- nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
end generate;
dbgbus : if DEBUG_BUS = 1 generate
-- DSU and debug links connected via AHB/AHB bridge to process
dbgsubsys : block
constant DBG_AHBIO : integer := 16#EFF#;
signal dbg_ahbsi : ahb_slv_in_type;
signal dbg_ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal dbg_ahbmi : ahb_mst_in_type;
signal dbg_ahbmo : ahb_mst_out_vector := (others => ahbm_none);
begin
edcl_ahbmi <= dbg_ahbmi;
dbg_ahbmo(CFG_AHB_UART+CFG_AHB_JTAG) <= edcl_ahbmo(0);
dbg_ahbmo(CFG_AHB_UART+CFG_AHB_JTAG+1) <= edcl_ahbmo(1);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3_mb -- LEON3 Debug Support Unit
generic map (hindex => 0, haddr => 16#E00#, hmask => 16#FC0#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, dbg_ahbsi, dbg_ahbso(0), ahbsi, dbgo, dbgi, dsui, dsuo);
end generate;
nodsu : if CFG_DSU = 0 generate
dbg_ahbso(0) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
membustrc : if true generate
ahbtrace0: ahbtrace_mb
generic map (
hindex => 2,
ioaddr => 16#000#,
iomask => 16#E00#,
tech => memtech,
irq => 0,
kbytes => 8,
ahbfilt => 2)
port map(
rst => rstn,
clk => clkm,
ahbsi => dbg_ahbsi,
ahbso => dbg_ahbso(2),
tahbmi => mem_ahbmi,
tahbsi => mem_ahbsi);
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0: ahbuart -- Debug UART
generic map (hindex => 0, pindex => 7, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(7), dbg_ahbmi, dbg_ahbmo(0));
end generate;
-- nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, dbg_ahbmi, dbg_ahbmo(CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => 0, fpnpen => CFG_FPNPEN,
rrobin => CFG_RROBIN, ioaddr => DBG_AHBIO,
ioen => 1,
nahbm => CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+CFG_GRETH2,
nahbs => 3)
port map (rstn, clkm, dbg_ahbmi, dbg_ahbmo, dbg_ahbsi, dbg_ahbso);
-- Bridge connecting debug bus -> processor bus
-- Configuration:
-- Prefetching with a maximum burst length of 8 words
-- No interrupt synchronisation
-- Debug cores cannot make locked accesses => lckdac = 0
-- Slave maximum access size: 32
-- Master maximum access size: 128
-- Read and write combining
-- No special handling for instruction bursts
debug_bridge: ahb2ahb
generic map (
memtech => 0,
hsindex => 1,
hmindex => CFG_NCPU+CFG_GRETH+CFG_GRETH2,
slv => 0,
dir => 1,
ffact => 1,
pfen => 1,
wburst => burstlen,
iburst => 8,
rburst => burstlen,
irqsync => 0,
bar0 => ahb2ahb_membar(16#000#, '1', '1', 16#800#),
bar1 => ahb2ahb_membar(16#800#, '0', '0', 16#C00#),
bar2 => ahb2ahb_membar(16#C00#, '0', '0', 16#E00#),
bar3 => ahb2ahb_membar(16#F00#, '0', '0', 16#F00#),
sbus => 2,
mbus => 0,
ioarea => 16#FFF#,
ibrsten => 0,
lckdac => 0,
slvmaccsz => 32,
mstmaccsz => 32,
rdcomb => 0,
wrcomb => 0,
combmask => 0,
allbrst => 0,
ifctrlen => 0,
fcfs => 0,
fcfsmtech => 0,
scantest => 0,
split => 0,
pipe => 0)
port map (
rstn => rstn,
hclkm => clkm,
hclks => clkm,
ahbsi => dbg_ahbsi,
ahbso => dbg_ahbso(1),
ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_GRETH+CFG_GRETH2),
ahbso2 => ahbso,
lcki => nolock,
lcko => open,
ifctrl => noifctrl);
end block dbgsubsys;
end generate;
----------------------------------------------------------------------
--- Memory subsystem ----------------------------------------------
----------------------------------------------------------------------
data_pad : iopadvv generic map (tech => padtech, width => 16, oepol => OEPOL)
port map (FSM_D, memo.data(31 downto 16), memo.vbdrive(31 downto 16), memi.data(31 downto 16));
FSM_A <= memo.address(25 downto 1);
FLASH_CLK <= clkm;
FLASH_RESET_n <= rstn;
FLASH_CE_n <= memo.romsn(0);
FLASH_OE_n <= memo.oen;
FLASH_WE_n <= memo.writen;
FLASH_ADV_n <= '0';
memi.brdyn <= '1';
memi.bexcn <= '1';
memi.writen <= '1';
memi.wrn <= (others => '1');
memi.bwidth <= "01";
memi.sd <= (others => '0');
memi.cb <= (others => '0');
memi.scb <= (others => '0');
memi.edac <= '0';
mctrl0 : if CFG_MCTRL_LEON2 = 1 generate
mctrl0 : mctrl generic map (hindex => 0, pindex => 0,
romaddr => 16#000#, rommask => 16#fc0#,
ioaddr => 0, iomask => 0,
ramaddr => 0, rammask => 0,
ram8 => CFG_MCTRL_RAM8BIT,
ram16 => CFG_MCTRL_RAM16BIT,
sden => CFG_MCTRL_SDEN,
invclk => CFG_MCTRL_INVCLK,
sepbus => CFG_MCTRL_SEPBUS)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, open);
end generate;
nomctrl0: if CFG_MCTRL_LEON2 = 0 generate
ahbso(0) <= ahbs_none;
apbo(0) <= apb_none;
memo <= memory_out_none;
end generate;
-----------------------------------------------------------------------------
-- DDR2 SDRAM memory controller
-----------------------------------------------------------------------------
l2cdis : if CFG_L2_EN = 0 generate
ddr2cen: if CFG_DDR2SP /= 0 generate
ddr2c : ddr2spa
generic map (
fabtech => stratix4, cbdelayb0 => 0,
memtech => memtech, cbdelayb1 => 0,
rskew => 0, cbdelayb2 => 0,
hindex => 3, cbdelayb3 => 0,
haddr => 16#400#, numidelctrl => 0,
hmask => 16#C00#, norefclk => 0,
ioaddr => 1, odten => 3,
iomask => 16#fff#, octen => 1,
MHz => CFG_DDR2SP_FREQ, dqsgating => 0,
TRFC => CFG_DDR2SP_TRFC, nosync => CFG_DDR2SP_NOSYNC,
clkmul => 16, eightbanks => 1,
clkdiv => 3, dqsse => 0,
col => 10, burstlen => burstlen,
Mbyte => 1024, ahbbits => ahbdw,
rstdel => 0, ft => CFG_DDR2SP_FTEN,
pwron => CFG_DDR2SP_INIT, ftbits => CFG_DDR2SP_FTWIDTH,
oepol => 0, bigmem => 0,
ddrbits => CFG_DDR2SP_DATAWIDTH, raspipe => 0,
ahbfreq => CPU_FREQ/1000, nclk => 2,
readdly => 0, scantest => 0,
ddelayb0 => CFG_DDR2SP_DELAY0, ncs => 1,
ddelayb1 => CFG_DDR2SP_DELAY1, cke_rst => 1,
ddelayb2 => CFG_DDR2SP_DELAY2, pipe_ctrl => 1,
ddelayb3 => CFG_DDR2SP_DELAY3,
ddelayb4 => CFG_DDR2SP_DELAY4,
ddelayb5 => CFG_DDR2SP_DELAY5,
ddelayb6 => CFG_DDR2SP_DELAY6,
ddelayb7 => CFG_DDR2SP_DELAY7
)
port map (
rst_ddr => CPU_RESET_n,
rst_ahb => rstn,
clk_ddr => OSC_50_BANK4,
clk_ahb => clkm,
clkref200 => clkm,
lock => lock,
clkddro => clkddr_l,
clkddri => clkddr_l,
ahbsi => ahbsi,
ahbso => ahbso(3),
ddr_ad => M1_DDR2_addr(13 downto 0),
ddr_ba => M1_DDR2_ba,
ddr_clk => M1_DDR2_clk,
ddr_clkb => M1_DDR2_clk_n,
ddr_cke => M1_DDR2_cke,
ddr_csb => M1_DDR2_cs_n,
ddr_dm => M1_DDR2_dm,
ddr_rasb => M1_DDR2_ras_n,
ddr_casb => M1_DDR2_cas_n,
ddr_web => M1_DDR2_we_n,
ddr_dq => M1_DDR2_dq,
ddr_dqs => M1_DDR2_dqs,
ddr_dqsn => M1_DDR2_dqsn,
ddr_odt => M1_DDR2_odt,
ddr_clk_fb_out => open,
ddr_clk_fb => '0',
ce => open,
oct_rdn => M1_DDR2_oct_rdn,
oct_rup => M1_DDR2_oct_rup
);
end generate;
ddr2cdis: if CFG_DDR2SP = 0 generate
ahbso(3) <= ahbs_none;
lock <= '1';
end generate;
end generate;
-----------------------------------------------------------------------------
-- L2 cache covering DDR2 SDRAM memory controller
-----------------------------------------------------------------------------
l2cen : if CFG_L2_EN /= 0 generate
memorysubsys : block
constant MEM_AHBIO : integer := 16#FFE#;
begin
l2c0 : l2c
generic map(hslvidx => 3, hmstidx => 0, cen => CFG_L2_PEN,
haddr => 16#400#, hmask => 16#c00#, ioaddr => 16#FF0#,
cached => CFG_L2_MAP, repl => CFG_L2_RAN, ways => CFG_L2_WAYS,
linesize => CFG_L2_LSZ, waysize => CFG_L2_SIZE,
memtech => memtech, bbuswidth => AHBDW,
bioaddr => MEM_AHBIO, biomask => 16#fff#,
sbus => 0, mbus => 1, arch => CFG_L2_SHARE,
ft => CFG_L2_EDAC)
port map(rst => rstn, clk => clkm, ahbsi => ahbsi, ahbso => ahbso(3),
ahbmi => mem_ahbmi, ahbmo => mem_ahbmo(0), ahbsov => mem_ahbso);
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => MEM_AHBIO,
ioen => IOAEN, nahbm => 1, nahbs => 1)
port map (rstn, clkm, mem_ahbmi, mem_ahbmo, mem_ahbsi, mem_ahbso);
ddr2cen: if CFG_DDR2SP /= 0 generate
ddr2c : ddr2spa
generic map (
fabtech => stratix4, cbdelayb0 => 0,
memtech => memtech, cbdelayb1 => 0,
rskew => 0, cbdelayb2 => 0,
hindex => 3, cbdelayb3 => 0,
haddr => 16#400#, numidelctrl => 0,
hmask => 16#C00#, norefclk => 0,
ioaddr => 1, odten => 3,
iomask => 16#fff#, octen => 1,
MHz => CFG_DDR2SP_FREQ, dqsgating => 0,
TRFC => CFG_DDR2SP_TRFC, nosync => CFG_DDR2SP_NOSYNC,
clkmul => 16, eightbanks => 1,
clkdiv => 3, dqsse => 0,
col => 10, burstlen => burstlen,
Mbyte => 1024, ahbbits => ahbdw,
rstdel => 0, ft => CFG_DDR2SP_FTEN,
pwron => CFG_DDR2SP_INIT, ftbits => CFG_DDR2SP_FTWIDTH,
oepol => 0, bigmem => 0,
ddrbits => CFG_DDR2SP_DATAWIDTH, raspipe => 0,
ahbfreq => CPU_FREQ/1000, nclk => 2,
readdly => 0, scantest => 0,
ddelayb0 => CFG_DDR2SP_DELAY0, ncs => 1,
ddelayb1 => CFG_DDR2SP_DELAY1, cke_rst => 1,
ddelayb2 => CFG_DDR2SP_DELAY2, pipe_ctrl => 1,
ddelayb3 => CFG_DDR2SP_DELAY3,
ddelayb4 => CFG_DDR2SP_DELAY4,
ddelayb5 => CFG_DDR2SP_DELAY5,
ddelayb6 => CFG_DDR2SP_DELAY6,
ddelayb7 => CFG_DDR2SP_DELAY7
)
port map (
rst_ddr => CPU_RESET_n,
rst_ahb => rstn,
clk_ddr => OSC_50_BANK4,
clk_ahb => clkm,
clkref200 => clkm,
lock => lock,
clkddro => clkddr_l,
clkddri => clkddr_l,
ahbsi => mem_ahbsi,
ahbso => mem_ahbso(0),
ddr_ad => M1_DDR2_addr(13 downto 0),
ddr_ba => M1_DDR2_ba,
ddr_clk => M1_DDR2_clk,
ddr_clkb => M1_DDR2_clk_n,
ddr_cke => M1_DDR2_cke,
ddr_csb => M1_DDR2_cs_n,
ddr_dm => M1_DDR2_dm,
ddr_rasb => M1_DDR2_ras_n,
ddr_casb => M1_DDR2_cas_n,
ddr_web => M1_DDR2_we_n,
ddr_dq => M1_DDR2_dq,
ddr_dqs => M1_DDR2_dqs,
ddr_dqsn => M1_DDR2_dqsn,
ddr_odt => M1_DDR2_odt,
ddr_clk_fb_out => open,
ddr_clk_fb => '0',
ce => open,
oct_rdn => M1_DDR2_oct_rdn,
oct_rup => M1_DDR2_oct_rup
);
end generate;
ddr2cdis: if CFG_DDR2SP = 0 generate
mem_ahbso(0) <= ahbs_none;
lock <= '1';
end generate;
end block memorysubsys;
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= '1' when slide_sw(0) = '0' else uart_rxd;
u1i.ctsn <= uart_rts; u1i.extclk <= '0';
end generate;
uart_txd <= u1o.txd when slide_sw(0) = '1' else duo.txd;
uart_cts <= u1o.rtsn;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti <= gpti_dhalt_drive(dsuo.tstop);
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit
grgpio0: grgpio
generic map( pindex => 9, paddr => 9, imask => CFG_GRGPIO_IMASK,
nbits => CFG_GRGPIO_WIDTH)
port map( rstn, clkm, apbi, apbo(9), gpioi, gpioo);
pio_pads : for i in 0 to CFG_GRGPIO_WIDTH-1 generate
pio_pad : iopad generic map (tech => padtech)
port map (GPIO0_D(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
unused_pio_pads : for i in (CFG_GRGPIO_WIDTH*CFG_GRGPIO_ENABLE) to 35 generate
GPIO0_D(i) <= '0';
end generate;
spic: if CFG_SPICTRL_ENABLE = 1 generate -- SPI controller
spi1 : spictrl
generic map (pindex => 10, paddr => 10, pmask => 16#fff#, pirq => 10,
fdepth => CFG_SPICTRL_FIFO, slvselen => CFG_SPICTRL_SLVREG,
slvselsz => CFG_SPICTRL_SLVS, odmode => 0, netlist => 0,
syncram => CFG_SPICTRL_SYNCRAM, ft => CFG_SPICTRL_FT)
port map (rstn, clkm, apbi, apbo(10), spii, spio, slvsel);
spii.spisel <= '1'; -- Master only
miso_pad : inpad generic map (tech => padtech)
port map (CSENSE_SDO, spii.miso);
mosi_pad : outpad generic map (tech => padtech)
port map (CSENSE_SDI, spio.mosi);
sck_pad : outpad generic map (tech => padtech)
port map (CSENSE_SCK, spio.sck);
slvsel_pad : outpad generic map (tech => padtech)
port map (CSENSE_CS_n(0), slvsel(0));
slvseladc_pad : outpad generic map (tech => padtech)
port map (CSENSE_ADC_FO, slvsel(1));
end generate spic;
ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
stati.cerror(0) <= memo.ce;
ahbstat0 : ahbstat
generic map (pindex => 15, paddr => 15, pirq => 1,
nftslv => CFG_AHBSTATN)
port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15));
end generate;
nop2 : if CFG_AHBSTAT = 0 generate apbo(15) <= apb_none; end generate;
fan_pad : outpad generic map (tech => padtech) port map (FAN_CTRL, vcc(0));
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
-- 125 MHz Gigabit ethernet clock generator from 50 MHz input
sgmii_pll0 : clkgen
generic map (
tech => CFG_CLKTECH,
clk_mul => 5,
clk_div => 2,
sdramen => 0,
freq => 50000
)
port map (
clkin => OSC_50_BANK3,
pciclkin => gnd(0),
clk => ref_clk,
clkn => open,
clk2x => open,
sdclk => open,
pciclk => open,
cgi => cgi_125,
cgo => cgo_125
);
-- 125 MHz clock reset synchronizer
rst2 : rstgen
generic map (acthigh => 0)
port map (e0_reset, ref_clk, cgo_125.clklock, ref_rstn, open);
ref_rst <= not ref_rstn;
e0 : greths_mb -- Gaisler Ethernet MAC 0
generic map (
hindex => CFG_NCPU+(CFG_AHB_UART+CFG_AHB_JTAG)*(1-DEBUG_BUS),
ehindex => CFG_AHB_UART+CFG_AHB_JTAG,
pindex => 11,
paddr => 11,
pirq => 6,
fabtech => fabtech,
memtech => memtech,
mdcscaler => CPU_FREQ/1000,
enable_mdio => 1,
nsync => 2,
edcl => CFG_DSU_ETH,
edclbufsz => CFG_ETH_BUF,
burstlength => burstlen,
macaddrh => CFG_ETH_ENM,
macaddrl => CFG_ETH_ENL,
phyrstadr => 0,
ipaddrh => CFG_ETH_IPM,
ipaddrl => CFG_ETH_IPL,
edclsepahbg => EDCL_SEP_AHB,
giga => CFG_GRETH1G,
sim => 1
)
port map (
rst => rstn,
clk => clkm,
ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+(CFG_AHB_UART+CFG_AHB_JTAG)*(1-DEBUG_BUS)),
ahbmi2 => edcl_ahbmi,
ahbmo2 => edcl_ahbmo(0),
apbi => apbi,
apbo => apbo(11),
-- High-speed Serial Interface
clk_125 => ref_clk,
rst_125 => ref_rst,
eth_rx_p => ETH_RX_p(0),
eth_tx_p => ETH_TX_p(0),
-- MDIO interface
reset => e0_reset,
mdio_o => e0_mdio_o,
mdio_oe => e0_mdio_oe,
mdio_i => e0_mdio_i,
mdc => e0_mdc,
mdint => e0_mdint,
-- Control signals
phyrstaddr => "00000",
edcladdr => "0001",
edclsepahb => '1',
edcldisable => slide_switch(1),
debug_pcs_mdio => gprego(0)
);
ethrst_pad : outpad generic map (tech => padtech)
port map (ETH_RST_n, e0_reset);
emdio0_pad : iopad generic map (tech => padtech)
port map (ETH_MDIO(0), e0_mdio_o, e0_mdio_oe, e0_mdio_i);
emdc0_pad : outpad generic map (tech => padtech)
port map (ETH_MDC(0), e0_mdc);
eint0_pad : inpad generic map (tech => padtech)
port map (ETH_INT_n(0), e0_mdint);
grgpreg0 : grgpreg
generic map (
pindex => 8,
paddr => 4,
rstval => 0
)
port map (
rst => rstn,
clk => clkm,
apbi => apbi,
apbo => apbo(8),
gprego => gprego
);
-- LEDs
led3_pad : outpad generic map (tech => padtech) port map (LED(3), vcc(0));
led4_pad : outpad generic map (tech => padtech) port map (LED(4), vcc(0));
led5_pad : outpad generic map (tech => padtech) port map (LED(5), vcc(0));
led6_pad : outpad generic map (tech => padtech) port map (LED(6), vcc(0));
led7_pad : outpad generic map (tech => padtech) port map (LED(7), vcc(0));
end generate;
noeth0 : if CFG_GRETH = 0 generate
edcl_ahbmo(0) <= ahbm_none;
end generate;
eth1: if CFG_GRETH2 = 1 generate -- Gaisler ethernet MAC
e1 : greths_mb -- Gaisler Ethernet MAC 1
generic map (
hindex => CFG_NCPU+(CFG_AHB_UART+CFG_AHB_JTAG)*(1-DEBUG_BUS)+CFG_GRETH,
ehindex => CFG_AHB_UART+CFG_AHB_JTAG+1,
pindex => 12,
paddr => 12,
pirq => 7,
fabtech => fabtech,
memtech => memtech,
mdcscaler => CPU_FREQ/1000,
enable_mdio => 1,
nsync => 2,
edcl => CFG_DSU_ETH,
edclbufsz => CFG_ETH_BUF,
burstlength => burstlen,
macaddrh => CFG_ETH_ENM,
macaddrl => CFG_ETH_ENL,
phyrstadr => 1,
ipaddrh => CFG_ETH_IPM,
ipaddrl => CFG_ETH_IPL,
edclsepahbg => EDCL_SEP_AHB,
giga => CFG_GRETH21G,
sim => 1
)
port map (
rst => rstn,
clk => clkm,
ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+(CFG_AHB_UART+CFG_AHB_JTAG)*(1-DEBUG_BUS)+CFG_GRETH),
ahbmi2 => edcl_ahbmi,
ahbmo2 => edcl_ahbmo(1),
apbi => apbi,
apbo => apbo(12),
-- High-speed Serial Interface
clk_125 => ref_clk,
rst_125 => ref_rst,
eth_rx_p => ETH_RX_p(1),
eth_tx_p => ETH_TX_p(1),
-- MDIO interface
reset => e1_reset,
mdio_o => e1_mdio_o,
mdio_oe => e1_mdio_oe,
mdio_i => e1_mdio_i,
mdc => e1_mdc,
mdint => e1_mdint,
-- Control signals
phyrstaddr => "00001",
edcladdr => "0010",
edclsepahb => '1',
edcldisable => slide_switch(1)
);
-- MDIO interface setup
emdio1_pad : iopad generic map (tech => padtech)
port map (ETH_MDIO(1), e1_mdio_o, e1_mdio_oe, e1_mdio_i);
emdc1_pad : outpad generic map (tech => padtech)
port map (ETH_MDC(1), e1_mdc);
eint1_pad : inpad generic map (tech => padtech)
port map (ETH_INT_n(1), e1_mdint);
end generate;
noeth2 : if CFG_GRETH2 = 0 generate
edcl_ahbmo(1) <= ahbm_none;
end generate;
edcl_pad : inpad
generic map (tech => padtech)
port map (SLIDE_SW(1), slide_switch(1));
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 5, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ)
port map ( rstn, clkm, ahbsi, ahbso(5));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(5) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam : for i in (CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+CFG_GRETH2) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
-- nap0 : for i in 11 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
-- apbo(6) <= apb_none;
--ahbmo(ahbmo'high downto nahbm) <= (others => ahbm_none);
ahbso(ahbso'high downto 6) <= (others => ahbs_none);
--apbo(napbs to apbo'high) <= (others => apb_none);
-----------------------------------------------------------------------
--- Test report module ----------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
test0 : ahbrep generic map (hindex => 4, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(4));
-- pragma translate_on
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => system_table(ALTERA_DE4),
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
| gpl-3.0 | 38226010ccbabecbf2593acfc2c66293 | 0.491602 | 3.597948 | false | false | false | false |
ggaray/nicsim-vhd | dmactrl.vhd | 1 | 15,301 | -- NICSim-vhd: A VHDL-based modelling and simulation of NIC's buffers
-- Copyright (C) 2013 Godofredo R. Garay <godofredo.garay (-at-) gmail.com>
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
entity dmactrl is
port (
payload_transfer_req : in bit;
descriptor_transfer_req : in bit;
payload_transfer_end : out bit := '0';
descriptor_transfer_end : out bit := '0';
payload_transfer_aborted : out bit := '0';
descriptor_transfer_aborted : out bit := '0';
resume_aborted_payload_transfer : in bit;
resume_aborted_descriptor_transfer : in bit;
irdy : in bit;
trdy : in bit;
gnt : in bit;
payload_size_in_data_blocks : in integer;
dma_cycles_counter_out : out integer := 0;
burst_cycles_counter_out : out integer := 0;
pciclk : in bit
);
end dmactrl;
architecture V1 of dmactrl is
--------------- Bus width configuration ---------------
--constant bus_width_in_bits : integer := 32; -- PCI 33/32
constant bus_width_in_bits : integer := 64; -- PCI 66/64, PCI-X 133/64
constant bus_width_in_bytes : integer := bus_width_in_bits/8;
-- ***To be removed
--constant bus_width_in_bytes : integer := 4; -- PCI bus
--constant bus_width_in_bytes : integer := 8; -- PCI-X bus
--------------- Burst size configuration ---------------
constant dma_burst_size_in_bytes : integer := 256; -- DMA busrt size = 256 bytes
--constant dma_burst_size_in_bytes : integer := 512; -- DMA busrt size = 512 bytes
--constant dma_burst_size_in_bytes : integer := 1024; -- DMA busrt size = 1024 bytes
--constant dma_burst_size_in_bytes : integer := 2048; -- DMA busrt size = 2048 bytes
--constant dma_burst_size_in_bytes : integer := 2048; -- DMA busrt size = 4096 bytes
constant dma_burst_size_in_cycles : integer := dma_burst_size_in_bytes/bus_width_in_bytes;
--constant dma_burst_size_in_cycles : integer := 64; -- DMA busrt size = 512 bytes (PCI-X bus)
--constant dma_burst_size_in_cycles : integer := 128; -- DMA busrt size = 1024 bytes (PCI-X bus)
--constant dma_burst_size_in_cycles : integer := 256; -- DMA busrt size = 2048 bytes (PCI-X bus)
--constant dma_burst_size_in_cycles : integer := 512; -- DMA busrt size = 4096 bytes (PCI-X bus)
--------------- Descriptor size configuration ---------------
--constant descriptor_size_in_data_blocks : integer := 2; -- Descriptor size in data blocks (PCI-X bus)
--constant descriptor_size_in_data_blocks : integer := 4; -- Descriptor size in data blocks (PCI bus)
constant descriptor_size_in_bytes : integer := 16; -- Descriptor size in bytes
constant descriptor_size_in_data_blocks : integer := descriptor_size_in_bytes/bus_width_in_bytes;
--------------- Injection rate configuration ---------------
-- ******* To be used in the future, not implemented yet...
--constant nic_injection_rate : natural := 1; -- NIC/PCI bus bandwidth ratio
constant nic_injection_rate : natural := 1; -- NIC/PCI bus bandwidth ratio
-- ****** In the future, constant pcilck_period should be removed a function based on the pciclk signal should be implemented
--constant pciclk_period : time := 0.03030303 us; -- PCI 33
--constant pciclk_period : time := 0.015151515 us; -- PCI 66
constant pciclk_period : time := 0.007518797 us; -- PCI-X 133
--constant pciclk_period : time := 0.003759398 us; -- PCI-X 266
--constant pciclk_period : time := 0.001876173 us; -- PCI-X 533
--------------- Variables Declarations ---------------
shared variable burst_cycles_counter : integer;
-- A variable is declared for each output signal.
shared variable payload_transfer_end_value : bit := '0';
shared variable descriptor_transfer_end_value : bit := '0';
shared variable payload_transfer_aborted_value : bit := '0';
shared variable descriptor_transfer_aborted_value : bit := '0';
shared variable dma_cycles_counter : integer := 0;
begin
dma_controller_fsm: process
type controller_state is (idle,
transferring_payload,
transferring_descriptor,
transferring_payload_stalled,
transferring_descriptor_stalled);
variable state : controller_state := idle;
variable next_state : controller_state := idle;
begin
wait until pciclk'event and pciclk = '1';
case state is
when idle =>
payload_transfer_end_value := '0';
descriptor_transfer_end_value := '0';
payload_transfer_aborted_value := '0';
descriptor_transfer_aborted_value := '0';
burst_cycles_counter := 0;
if payload_transfer_req = '1'
and descriptor_transfer_req = '1'
and resume_aborted_payload_transfer = '1'
and resume_aborted_descriptor_transfer = '1'
then next_state := idle;
elsif payload_transfer_req = '0'
--and descriptor_transfer_req = '1'
and irdy = '0'
and trdy = '0'
--and dma_cycles_counter = 0
then dma_cycles_counter := payload_size_in_data_blocks;
burst_cycles_counter := dma_burst_size_in_cycles;
assert false
report "dma_controller_fsm: transferring_payload"
severity note;
next_state := transferring_payload;
elsif payload_transfer_req = '0'
--and dma_cycles_counter > 0
and (irdy = '1'
or trdy = '1')
then assert false
report "dma_controller_fsm: transferring_payload_stalled"
severity note;
next_state := transferring_payload_stalled;
-- Descriptor transfer
elsif descriptor_transfer_req = '0'
and payload_transfer_req = '1'
and irdy = '0'
and trdy = '0'
and dma_cycles_counter = 0
then dma_cycles_counter := descriptor_size_in_data_blocks;
burst_cycles_counter := dma_burst_size_in_cycles;
assert false
report "dma_controller_fsm: transferring_descriptor"
severity note;
next_state := transferring_descriptor;
elsif descriptor_transfer_req = '0'
and payload_transfer_req = '1'
and dma_cycles_counter > 0
and (irdy = '1'
or trdy = '1')
then assert false
report "dma_controller_fsm: transferring_descriptor_stalled"
severity note;
next_state := transferring_descriptor_stalled;
-- Aborted payload transfer
elsif resume_aborted_payload_transfer = '0'
and payload_transfer_req = '1'
and descriptor_transfer_req = '1'
and resume_aborted_descriptor_transfer = '1'
and gnt = '0'
and irdy = '0'
and trdy = '0'
and dma_cycles_counter > 0
then assert false
report "Aborted payload transfer, resume_aborted_payload_transfer = 0"
severity note;
burst_cycles_counter := dma_burst_size_in_cycles;
next_state := transferring_payload;
elsif resume_aborted_payload_transfer = '0'
and payload_transfer_req = '1'
and descriptor_transfer_req = '1'
and resume_aborted_descriptor_transfer = '1'
and irdy = '0'
and dma_cycles_counter > 0
and (irdy = '1'
or trdy = '1')
then assert false
report "dma_controller_fsm: transferring_payload_stalled"
severity note;
next_state := transferring_payload_stalled;
elsif resume_aborted_payload_transfer = '0'
and dma_cycles_counter = 0
then assert false
report "Illegal resume_aborted_payload_transfer at this moment because dma_cycles_counter = 0. Ignoring signal "
severity warning;
next_state := idle;
-- Aborted descriptor transfer
elsif resume_aborted_descriptor_transfer = '0'
and dma_cycles_counter > 0
and irdy = '0'
and trdy = '0'
then assert false
report "dma_controller_fsm: transferring_descriptor"
severity note;
next_state := transferring_descriptor;
elsif resume_aborted_payload_transfer = '0'
and dma_cycles_counter > 0
and (irdy = '1'
and trdy = '1')
then assert false
report "dma_controller_fsm: transferring_payload_stalled"
severity note;
next_state := transferring_payload_stalled;
elsif resume_aborted_descriptor_transfer = '0'
and dma_cycles_counter > 0
and (irdy = '0'
and trdy = '0')
then assert false
report "dma_controller_fsm: transferring_descriptor_stalled"
severity note;
next_state := transferring_descriptor_stalled;
elsif resume_aborted_descriptor_transfer = '0'
and dma_cycles_counter = 0
then assert false
report "Illegal resume_aborted_descriptor_transfer signal at this moment. Ignoring signal"
severity warning;
next_state := idle;
end if;
when transferring_payload =>
if burst_cycles_counter = 0
then payload_transfer_aborted_value := '1';
wait for pciclk_period * 8;
assert false
report "dma_controller_fsm: idle"
severity note;
next_state := idle;
elsif (payload_transfer_req = '0'
or resume_aborted_payload_transfer = '0')
and gnt = '0'
and irdy = '0'
and trdy = '0'
and dma_cycles_counter > 0
then --assert false
--report "decrementing payload cycles counter"
--severity warning;
dma_cycles_counter := dma_cycles_counter - 1;
burst_cycles_counter := burst_cycles_counter - 1;
assert false
report "dma_controller_fsm: decrementing dma_cycles_counter"
severity note;
next_state := transferring_payload;
elsif (payload_transfer_req = '0'
or resume_aborted_payload_transfer = '0')
--and gnt = '0'
--and irdy = '0'
--and trdy = '0'
and dma_cycles_counter = 0
then payload_transfer_end_value := '1';
wait for pciclk_period * 8;
assert false
report "dma_controller_fsm: idle"
severity note;
next_state := idle;
elsif payload_transfer_req = '0'
and gnt = '0'
and dma_cycles_counter > 0
and (trdy = '1'
or irdy = '1')
then assert false
report "dma_controller_fsm: transferring_payload_stalled"
severity note;
next_state := transferring_payload_stalled;
elsif (payload_transfer_req = '0'
or resume_aborted_payload_transfer = '0')
and gnt = '1'
and dma_cycles_counter > 0
then payload_transfer_aborted_value := '1';
wait for pciclk_period * 8;
next_state := idle;
end if;
when transferring_payload_stalled =>
if burst_cycles_counter = 0
then payload_transfer_aborted_value := '1';
wait for pciclk_period * 8;
next_state := idle;
elsif payload_transfer_req = '0'
and gnt = '0'
and dma_cycles_counter > 0
and (irdy = '1'
or trdy = '1')
then burst_cycles_counter := burst_cycles_counter - 1;
assert false
report "dma_controller_fsm: transferring_payload_stalled"
severity note;
next_state := transferring_payload_stalled;
elsif payload_transfer_req = '0'
and gnt = '0'
and irdy = '0'
and trdy = '0'
and dma_cycles_counter > 0
then burst_cycles_counter := burst_cycles_counter - 1;
assert false
report "dma_controller_fsm: decrementing burst_cycles_counter"
severity note;
next_state := transferring_payload;
elsif gnt = '1'
--and dma_cycles_counter > 0
then payload_transfer_aborted_value := '1';
wait for pciclk_period * 8;
--descriptor_transfer_aborted <= '0';
next_state := idle;
end if;
when transferring_descriptor =>
if (descriptor_transfer_req = '0'
or resume_aborted_descriptor_transfer = '0')
and gnt = '0'
and irdy = '0'
and trdy = '0'
and dma_cycles_counter > 0
then dma_cycles_counter := dma_cycles_counter - 1;
burst_cycles_counter := burst_cycles_counter - 1;
assert false
report "dma_controller_fsm: decrementing dma_cycles_counter"
severity note;
next_state := transferring_descriptor;
elsif (descriptor_transfer_req = '0'
or resume_aborted_payload_transfer = '0')
--and gnt = '0'
--and irdy = '0'
--and trdy = '0'
and dma_cycles_counter = 0
then descriptor_transfer_end_value := '1';
wait for pciclk_period * 8;
assert false
report "dma_controller_fsm: idle"
severity note;
next_state := idle;
elsif descriptor_transfer_req = '0'
and gnt = '0'
and dma_cycles_counter > 0
and (trdy = '1'
or irdy = '1')
then assert false
report "dma_controller_fsm: transferring_descriptor_stalled"
severity note;
next_state := transferring_descriptor_stalled;
elsif (descriptor_transfer_req = '0'
or resume_aborted_descriptor_transfer = '0')
and gnt = '1'
and dma_cycles_counter > 0
then descriptor_transfer_aborted_value := '1';
wait for pciclk_period * 8;
next_state := idle;
end if;
when transferring_descriptor_stalled =>
if descriptor_transfer_req = '0'
and gnt = '0'
and dma_cycles_counter > 0
and (irdy = '1'
or trdy = '1')
then assert false
report "dma_controller_fsm: transferring_descriptor_stalled"
severity note;
next_state := transferring_descriptor_stalled;
elsif descriptor_transfer_req = '0'
and gnt = '0'
and irdy = '0'
and trdy = '0'
and dma_cycles_counter > 0
then next_state := transferring_descriptor;
elsif gnt = '1'
-- and dma_cycles_counter > 0
then descriptor_transfer_aborted_value := '1';
wait for pciclk_period * 8;
next_state := idle;
end if;
end case;
state := next_state;
end process dma_controller_fsm;
output_signals_driver: process
begin
wait until pciclk'event and pciclk = '1';
payload_transfer_end <= payload_transfer_end_value;
descriptor_transfer_end <= descriptor_transfer_end_value;
payload_transfer_aborted <= payload_transfer_aborted_value;
descriptor_transfer_aborted <= descriptor_transfer_aborted_value;
end process output_signals_driver;
dma_cycles_counter_out_driver: process
begin
wait until pciclk'event and pciclk = '0';
dma_cycles_counter_out <= dma_cycles_counter;
burst_cycles_counter_out <= burst_cycles_counter;
end process dma_cycles_counter_out_driver;
end V1;
| gpl-3.0 | 3163a34305c7d3ce3b38a548223b3b19 | 0.618783 | 3.311188 | false | false | false | false |
ggaray/nicsim-vhd | othermaster.vhd | 1 | 8,733 | -- NICSim-vhd: A VHDL-based modelling and simulation of NIC's buffers
-- Copyright (C) 2013 Godofredo R. Garay <godofredo.garay (-at-) gmail.com>
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
use std.textio.all;
library ieee;
use ieee.math_real.all; -- for uniform
use ieee.std_logic_1164.all;
entity othermaster is
port (
frame : inout std_logic := 'Z';
pciclk : in bit
);
end othermaster;
architecture V1 of othermaster is
--------------- Random number generator configuration ---------------
--Baseline
constant othermaster_seed1_value : positive := 6;
constant othermaster_seed2_value : positive := 31;
--Run 1
--constant othermaster_seed1_value : positive := 680;
--constant othermaster_seed2_value : positive := 613;
--Run 2
--constant othermaster_seed1_value : positive := 700;
--constant othermaster_seed2_value : positive := 88;
--Run 3
--constant othermaster_seed1_value : positive := 47;
--constant othermaster_seed2_value : positive := 92;
--Run 4
--constant othermaster_seed1_value : positive := 72;
--constant othermaster_seed2_value : positive := 1;
--Run 5
--constant othermaster_seed1_value : positive := 37;
--constant othermaster_seed2_value : positive := 41;
--Run 6
--constant othermaster_seed1_value : positive := 1;
--constant othermaster_seed2_value : positive := 500;
--Run 7
--constant othermaster_seed1_value : positive := 2000;
--constant othermaster_seed2_value : positive := 2001;
--constant othermaster_seed1_value : positive := 2030;
--constant othermaster_seed2_value : positive := 2101;
--constant othermaster_seed1_value : positive := 2011;
--constant othermaster_seed2_value : positive := 1970;
--constant othermaster_seed1_value : positive := 1933;
--constant othermaster_seed2_value : positive := 1937;
--constant othermaster_seed1_value : positive := 73;
--constant othermaster_seed2_value : positive := 194;
--constant othermaster_seed1_value : positive := 3;
--constant othermaster_seed2_value : positive := 101;
--constant othermaster_seed1_value : positive := 1356;
--constant othermaster_seed2_value : positive := 4;
--constant othermaster_seed1_value : positive := 9;
--constant othermaster_seed2_value : positive := 884;
--------------- Bus arbitration latency configuration ---------------
constant min_transaction_in_progress_latency : positive := 1;
constant max_transaction_in_progress_latency : positive := 80;
--------------- Variables Declarations ---------------
shared variable trdy_value : bit := '1';
shared variable random_cycles_count : integer := 0;
shared variable latency_cycles_count : integer := 0;
shared variable total_acquisition_cycles : integer := 0;
shared variable total_bus_transfer_cycles : integer := 0;
shared variable current_transaction_cycles_count : integer := 0;
--shared variable acquisition_cycles_count : integer := 0;
-- Variables needed for Memsub FSM
type othermaster_fsm_state is (watching_bus_state,
bus_acquired,
bus_idle);
shared variable state : othermaster_fsm_state := watching_bus_state; --Initial state = watching_bus_state
shared variable next_state : othermaster_fsm_state := watching_bus_state;
-- These signals are used to handle frame bidirectional port
signal dir : std_logic := '0'; -- '0' reading, '1' driving
signal frame_out : std_logic := 'Z';
-- ****** In the future, constant pcilck_period should be removed a function based on the pciclk signal should be implemented
--constant pciclk_period : time := 0.03030303 us; -- PCI 33
--constant pciclk_period : time := 0.015151515 us; -- PCI-X 66
constant pciclk_period : time := 0.007518797 us; -- PCI-X 133
--constant pciclk_period : time := 0.003759398 us; -- PCI-X 266
--constant pciclk_period : time := 0.001876173 us; -- PCI-X 533
--constant tpd : time := 1 ns; ****** To be removed
begin
frame <= frame_out when (dir = '1') else 'Z';
othermaster_fsm: process
begin
wait until pciclk'event and pciclk = '1';
case state is
when watching_bus_state =>
--gnt_value := '1';
--bus_transfer_cycles_counter := 0;
--latency_cycles_count := 0;
--This wait cycle allows us avoiding bus contention among the NIC and othermaster
wait for pciclk_period;
dir <= '0';
if frame = '0'
then --dir <= '0' ;
next_state := watching_bus_state;
elsif frame = 'Z'
then dir <= '1';
frame_out <= '0';
current_transaction_cycles_count := random_cycles_count;
--latency_cycles_count := generate_random_latency_in_cycles;
--acquisition_cycles_count := random_cycles_count;
--total_acquisition_cycles := total_acquisition_cycles + acquisition_cycles_count;
--bus_transfer_cycles_counter := dma_burst_size_in_cycles;
--total_bus_transfer_cycles = total_bus_transfer_cycles + bus_transfer_cycles_counter;
assert false
report "othermaster_fsm: bus_acquired"
severity note;
next_state := bus_acquired;
elsif frame = '1'
then dir <= '0';
assert false
report "othermaster_fsm: bus_acquired"
severity note;
next_state := bus_acquired;
end if;
when bus_acquired =>
dir <= '1';
frame_out <= '0';
if current_transaction_cycles_count > 0
then current_transaction_cycles_count := current_transaction_cycles_count - 1;
next_state := bus_acquired;
elsif current_transaction_cycles_count = 0
then dir <= '1';
frame_out <= '1';
assert false
report "othermaster_fsm: bus_idle"
severity note;
next_state := bus_idle;
end if;
when bus_idle =>
dir <= '0';
assert false
report "othermaster_fsm: watching_bus_state"
severity note;
next_state := watching_bus_state;
end case;
state := next_state;
end process othermaster_fsm;
random_number_generator_fsm: process
type generator_state is (generating_random_number, waiting);
variable state : generator_state := generating_random_number;
variable next_state : generator_state := generating_random_number;
variable random_number : integer := 1;
variable seed1 : positive := othermaster_seed1_value;
variable seed2 : positive := othermaster_seed2_value;
variable rand : real;
file random_current_transaction_cycles_count_file : text open write_mode is "random_current_transaction_cycles_count.out";
variable output_line : line;
begin
case state is
when generating_random_number =>
-- Since rand values are in the interval 0..1, the values are multiplicated by 1000 and rounded.
-- This way, an integer random value in the interval 1..1000 is obtained
uniform(seed1, seed2, rand);
random_number := integer(round(rand*1000.0));
--random_number := 5;
if random_number >= min_transaction_in_progress_latency
and random_number <= max_transaction_in_progress_latency
then random_cycles_count := random_number;
write(output_line, random_cycles_count);
writeline(random_current_transaction_cycles_count_file, output_line);
assert false
report "random_number_generator_fsm: waiting"
severity note;
next_state := waiting;
else next_state := generating_random_number;
end if;
when waiting =>
wait until frame_out'event and frame_out = '0';
assert false
report "random_number_generator_fsm: generating random acquisition latency"
severity note;
next_state := generating_random_number;
end case;
state := next_state;
end process random_number_generator_fsm;
-- output_signals_driver: process
-- begin
-- wait until pciclk'event and pciclk = '1';
-- frame <= frame_value;
-- end process output_signals_driver;
end V1;
| gpl-3.0 | 9a3482849de2619e767036d08d109704 | 0.65075 | 3.19072 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-avnet-3s1500/leon3mp.vhd | 1 | 30,423 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design for AVNET Spartan3 Evaluation Board
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.pci.all;
use gaisler.net.all;
use gaisler.jtag.all;
use gaisler.can.all;
library esa;
use esa.memoryctrl.all;
use esa.pcicomp.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
mezz : integer := CFG_ADS_DAU_MEZZ
);
port (
clk_66mhz : in std_logic;
clk_socket : in std_logic;
leds : out std_logic_vector(7 downto 0);
switches : in std_logic_vector(5 downto 0);
sram_a : out std_logic_vector(24 downto 0);
sram_ben_l : out std_logic_vector(0 to 3);
sram_cs_l : out std_logic_vector(1 downto 0);
sram_oe_l : out std_logic;
sram_we_l : out std_logic;
sram_dq : inout std_logic_vector(31 downto 0);
flash_cs_l : out std_logic;
flash_rst_l : out std_logic;
iosn : out std_logic;
sdclk : out std_logic;
rasn : out std_logic;
casn : out std_logic;
sdcke : out std_logic;
sdcsn : out std_logic;
tx : out std_logic;
rx : in std_logic;
can_txd : out std_logic;
can_rxd : in std_logic;
phy_txck : in std_logic;
phy_rxck : in std_logic;
phy_rxd : in std_logic_vector(3 downto 0);
phy_rxdv : in std_logic;
phy_rxer : in std_logic;
phy_col : in std_logic;
phy_crs : in std_logic;
phy_txd : out std_logic_vector(3 downto 0);
phy_txen : out std_logic;
phy_txer : out std_logic;
phy_mdc : out std_logic;
phy_mdio : inout std_logic; -- ethernet PHY interface
phy_reset_l : inout std_logic;
video_clk : in std_logic;
comp_sync : out std_logic;
horiz_sync : out std_logic;
vert_sync : out std_logic;
blank : out std_logic;
video_out : out std_logic_vector(23 downto 0);
msclk : inout std_logic;
msdata : inout std_logic;
kbclk : inout std_logic;
kbdata : inout std_logic;
disp_seg1 : out std_logic_vector(7 downto 0);
disp_seg2 : out std_logic_vector(7 downto 0);
pci_clk : in std_logic;
pci_gnt : in std_logic;
pci_idsel : in std_logic;
pci_lock : inout std_logic;
pci_ad : inout std_logic_vector(31 downto 0);
pci_cbe : inout std_logic_vector(3 downto 0);
pci_frame : inout std_logic;
pci_irdy : inout std_logic;
pci_trdy : inout std_logic;
pci_devsel : inout std_logic;
pci_stop : inout std_logic;
pci_perr : inout std_logic;
pci_par : inout std_logic;
pci_req : inout std_logic;
pci_serr : inout std_logic;
pci_host : in std_logic;
pci_66 : in std_logic
);
end;
architecture rtl of leon3mp is
constant blength : integer := 12;
constant fifodepth : integer := 8;
constant mahbmax : integer := CFG_NCPU+CFG_AHB_UART+CFG_GRPCI2_TARGET+CFG_GRPCI2_DMA+
CFG_SVGA_ENABLE + CFG_GRETH+CFG_AHB_JTAG;
signal vcc, gnd : std_logic_vector(23 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal abus : std_logic_vector(17 downto 0);
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clk, rstn, rstraw, pciclk, sdclkl : std_logic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, u2i, dui : uart_in_type;
signal u1o, u2o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal kbdi : ps2_in_type;
signal kbdo : ps2_out_type;
signal moui : ps2_in_type;
signal mouo : ps2_out_type;
signal vgao : apbvga_out_type;
signal pcii : pci_in_type;
signal pcio : pci_out_type;
signal ethi, ethi1, ethi2 : eth_in_type;
signal etho, etho1, etho2 : eth_out_type;
signal gpti : gptimer_in_type;
signal tck, tms, tdi, tdo : std_logic;
signal pllref, errorn, pci_rst : std_logic;
signal pci_arb_req_n, pci_arb_gnt_n : std_logic_vector(0 to 3);
signal pci_dirq : std_logic_vector(3 downto 0);
signal dac_clk, clk25, clk_66mhzl, pci_lclk : std_logic;
signal can_ltx, can_lrx : std_logic;
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of clk : signal is true;
attribute syn_preserve of clk : signal is true;
attribute keep of clk : signal is true;
signal switchesl : std_logic_vector(5 downto 0);
constant padlevel : integer := 0;
constant IOAEN : integer := CFG_CAN+CFG_GRPCI2_MASTER;
constant BOARD_FREQ : integer := 66667; -- input frequency in KHz
constant CPU_FREQ : integer := (BOARD_FREQ * CFG_CLKMUL) / CFG_CLKDIV;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
---------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0'); pllref <= '0';
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw; cgi.pllref <= pllref;
clkgen0 : clkgen -- clock generator
generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
CFG_CLK_NOFB, CFG_GRPCI2_MASTER+CFG_GRPCI2_TARGET, CFG_PCIDLL, CFG_PCISYSCLK, 66000)
port map (clk_66mhzl, pci_lclk, clk, open, open, sdclkl, pciclk, cgi, cgo);
sdclk_pad : outpad generic map (tech => padtech, slew => 1, strength => 8)
port map (sdclk, sdclkl);
clk_pad : clkpad generic map (tech => padtech, level => padlevel)
port map (clk_66mhz, clk_66mhzl);
clk2_pad : clkpad generic map (tech => padtech, level => padlevel)
port map (clk_socket, open);
pci_clk_pad : clkpad generic map (tech => padtech, level => pci33)
port map (pci_clk, pci_lclk);
rst0 : rstgen generic map (acthigh => 1)
port map (switchesl(4), clk, cgo.clklock, rstn, rstraw);
flash_rst_l_pad : outpad generic map (level => padlevel, tech => padtech)
port map (flash_rst_l, rstraw);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
nahbm => mahbmax, nahbs => 8, ioen => IOAEN)
port map (rstn, clk, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1, 0, 0,
CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clk, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clk, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
end generate;
dsui.break <= switchesl(5);
dsui.enable <= '1';
dsuact_pad : outpad generic map (tech => padtech, level => padlevel)
port map (leds(1), dsuo.active);
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0: ahbuart -- Debug UART
generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
port map (rstn, clk, dui, duo, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clk, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
dcompads : if CFG_AHB_UART = 1 generate
dsurx_pad : inpad generic map (tech => padtech, level => padlevel)
port map (rx, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech, level => padlevel)
port map (tx, duo.txd);
u1i.rxd <= '1';
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 : entity work.mctrl_avnet generic map (hindex => 0, pindex => 0, paddr => 0,
srbanks => 4, sden => CFG_MCTRL_SDEN, invclk => CFG_MCTRL_INVCLK,
pageburst => CFG_MCTRL_PAGE, avnetmezz => mezz)
port map (rstn, clk, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
sdpads : if CFG_MCTRL_SDEN = 1 generate -- no SDRAM controller
-- sdwen_pad : outpad generic map (tech => padtech)
-- port map (sdwen, sdo.sdwen);
sdras_pad : outpad generic map (tech => padtech)
port map (rasn, sdo.rasn);
sdcas_pad : outpad generic map (tech => padtech)
port map (casn, sdo.casn);
-- sddqm_pad : outpadv generic map (width =>4, tech => padtech)
-- port map (sddqm, sdo.dqm);
end generate;
sdcke_pad : outpad generic map (tech => padtech)
port map (sdcke, sdo.sdcke(0));
sdcsn_pad : outpad generic map (tech => padtech)
port map (sdcsn, sdo.sdcsn(0));
end generate;
nosd0 : if (CFG_MCTRL_SDEN = 0) generate -- no SDRAM controller
sdcke_pad : outpad generic map (tech => padtech)
port map (sdcke, vcc(0));
sdcsn_pad : outpad generic map (tech => padtech)
port map (sdcsn, vcc(0));
end generate;
memi.brdyn <= '1'; memi.bexcn <= '1';
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "10";
mg0 : if CFG_MCTRL_LEON2 = 0 generate -- None PROM/SRAM controller
apbo(0) <= apb_none; ahbso(0) <= ahbs_none;
rams_pad : outpadv generic map (level => padlevel, tech => padtech, width => 2)
port map (sram_cs_l, vcc(1 downto 0));
end generate;
mgpads : if CFG_MCTRL_LEON2 /= 0 generate -- prom/sram pads
addr_pad : outpadv generic map (level => padlevel, width => 25, tech => padtech)
port map (sram_a, memo.address(24 downto 0));
rams_pad : outpadv generic map (level => padlevel, tech => padtech, width => 2)
port map (sram_cs_l, memo.ramsn(1 downto 0));
flash_pad : outpad generic map (level => padlevel, tech => padtech)
port map (flash_cs_l, memo.romsn(0));
oen_pad : outpad generic map (level => padlevel, tech => padtech)
port map (sram_oe_l, memo.oen);
iosn_pad : outpad generic map (level => padlevel, tech => padtech)
port map (iosn, memo.iosn);
wri_pad : outpad generic map (level => padlevel, tech => padtech)
port map (sram_we_l, memo.writen);
bdr : for i in 0 to 3 generate
data_pad : iopadv generic map (level => padlevel, tech => padtech, width => 8)
port map (sram_dq(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.data(31-i*8 downto 24-i*8));
end generate;
ben_pad : outpadv generic map (level => padlevel, width => 4, tech => padtech)
port map (sram_ben_l, memo.mben);
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clk, ahbsi, ahbso(1), apbi, apbo );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clk, apbi, apbo(1), u1i, u1o);
u1i.ctsn <= '0'; u1i.extclk <= '0';
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
ua1pads : if CFG_AHB_UART = 0 generate
rx_pad : inpad generic map (tech => padtech, level => padlevel)
port map (rx, u1i.rxd);
tx_pad : outpad generic map (tech => padtech, level => padlevel)
port map (tx, u1o.txd);
end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clk, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
pci_dirq(3 downto 1) <= (others => '0');
pci_dirq(0) <= orv(irqi(0).irl);
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clk, apbi, apbo(3), gpti, open);
gpti <= gpti_dhalt_drive(dsuo.tstop);
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
kbd : if CFG_KBD_ENABLE /= 0 generate
ps21 : apbps2 generic map(pindex => 4, paddr => 4, pirq => 4)
port map(rstn, clk, apbi, apbo(4), moui, mouo);
ps20 : apbps2 generic map(pindex => 5, paddr => 5, pirq => 5)
port map(rstn, clk, apbi, apbo(5), kbdi, kbdo);
end generate;
nokbd : if CFG_KBD_ENABLE = 0 generate
apbo(4) <= apb_none; mouo <= ps2o_none;
apbo(5) <= apb_none; kbdo <= ps2o_none;
end generate;
kbdclk_pad : iopad generic map (tech => padtech)
port map (kbclk,kbdo.ps2_clk_o, kbdo.ps2_clk_oe, kbdi.ps2_clk_i);
kbdata_pad : iopad generic map (tech => padtech)
port map (kbdata, kbdo.ps2_data_o, kbdo.ps2_data_oe, kbdi.ps2_data_i);
mouclk_pad : iopad generic map (tech => padtech)
port map (msclk,mouo.ps2_clk_o, mouo.ps2_clk_oe, moui.ps2_clk_i);
mouata_pad : iopad generic map (tech => padtech)
port map (msdata, mouo.ps2_data_o, mouo.ps2_data_oe, moui.ps2_data_i);
vga : if CFG_VGA_ENABLE /= 0 generate
vga0 : apbvga generic map(memtech => memtech, pindex => 6, paddr => 6)
port map(rstn, clk, clk25, apbi, apbo(6), vgao);
vgaclk0 : entity techmap.clkmul_virtex2 generic map (3, 8) -- 25 MHz video clock
port map (rstn, clk, dac_clk, open);
end generate;
svga : if CFG_SVGA_ENABLE /= 0 generate
svga0 : svgactrl generic map(memtech => memtech, pindex => 6, paddr => 6,
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
clk0 => 39722, clk1 => 0, clk2 => 0, clk3 => 0, burstlen => 5)
port map(rstn, clk, clk25, apbi, apbo(6), vgao, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), open);
clk25 <= not dac_clk;
end generate;
novga : if (CFG_VGA_ENABLE = 0 and CFG_SVGA_ENABLE = 0) generate
apbo(6) <= apb_none; vgao <= vgao_none;
end generate;
video_clk_pad : inpad generic map (tech => padtech)
port map (video_clk, dac_clk);
blank_pad : outpad generic map (tech => padtech)
port map (blank, vgao.blank);
comp_sync_pad : outpad generic map (tech => padtech)
port map (comp_sync, vgao.comp_sync);
vert_sync_pad : outpad generic map (tech => padtech)
port map (vert_sync, vgao.vsync);
horiz_sync_pad : outpad generic map (tech => padtech)
port map (horiz_sync, vgao.hsync);
video_out_r_pad : outpadv generic map (width => 8, tech => padtech)
port map (video_out(23 downto 16), vgao.video_out_r);
video_out_g_pad : outpadv generic map (width => 8, tech => padtech)
port map (video_out(15 downto 8), vgao.video_out_g);
video_out_b_pad : outpadv generic map (width => 8, tech => padtech)
port map (video_out(7 downto 0), vgao.video_out_b);
-----------------------------------------------------------------------
--- PCI ------------------------------------------------------------
-----------------------------------------------------------------------
pp : if (CFG_GRPCI2_MASTER+CFG_GRPCI2_TARGET) /= 0 generate
grpci2xt : if (CFG_GRPCI2_TARGET) /= 0 and (CFG_GRPCI2_MASTER+CFG_GRPCI2_DMA) = 0 generate
pci0 : grpci2
generic map (
memtech => memtech,
hmindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE,
hdmindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE+1,
hsindex => 4, haddr => 16#C00#, hmask => 16#E00#, ioaddr => 16#400#,
pindex => 9, paddr => 9, irq => 4, irqmode => 0,
master => CFG_GRPCI2_MASTER, target => CFG_GRPCI2_TARGET,
dma => CFG_GRPCI2_DMA, tracebuffer => CFG_GRPCI2_TRACE,
vendorid => CFG_GRPCI2_VID, deviceid => CFG_GRPCI2_DID,
classcode => CFG_GRPCI2_CLASS, revisionid => CFG_GRPCI2_RID,
cap_pointer => CFG_GRPCI2_CAP, ext_cap_pointer => CFG_GRPCI2_NCAP,
iobase => CFG_AHBIO, extcfg => CFG_GRPCI2_EXTCFG,
bar0 => CFG_GRPCI2_BAR0, bar1 => CFG_GRPCI2_BAR1,
bar2 => CFG_GRPCI2_BAR2, bar3 => CFG_GRPCI2_BAR3,
bar4 => CFG_GRPCI2_BAR4, bar5 => CFG_GRPCI2_BAR5,
fifo_depth => CFG_GRPCI2_FDEPTH, fifo_count => CFG_GRPCI2_FCOUNT,
conv_endian => CFG_GRPCI2_ENDIAN, deviceirq => CFG_GRPCI2_DEVINT,
deviceirqmask => CFG_GRPCI2_DEVINTMSK, hostirq => CFG_GRPCI2_HOSTINT,
hostirqmask => CFG_GRPCI2_HOSTINTMSK,
nsync => 2, hostrst => 1, bypass => CFG_GRPCI2_BYPASS,
debug => 0, tbapben => 0, tbpindex => 5, tbpaddr => 16#400#, tbpmask => 16#C00#
)
port map (
rstn, clk, pciclk, pci_dirq, pcii, pcio, apbi, apbo(9), ahbsi, open, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE), ahbmi,
open, open, open, open, open);
end generate;
grpci2xmt : if (CFG_GRPCI2_MASTER+CFG_GRPCI2_TARGET) > 1 and (CFG_GRPCI2_DMA) = 0 generate
pci0 : grpci2
generic map (
memtech => memtech,
hmindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE,
hdmindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE+1,
hsindex => 4, haddr => 16#C00#, hmask => 16#E00#, ioaddr => 16#400#,
pindex => 9, paddr => 9, irq => 4, irqmode => 0,
master => CFG_GRPCI2_MASTER, target => CFG_GRPCI2_TARGET,
dma => CFG_GRPCI2_DMA, tracebuffer => CFG_GRPCI2_TRACE,
vendorid => CFG_GRPCI2_VID, deviceid => CFG_GRPCI2_DID,
classcode => CFG_GRPCI2_CLASS, revisionid => CFG_GRPCI2_RID,
cap_pointer => CFG_GRPCI2_CAP, ext_cap_pointer => CFG_GRPCI2_NCAP,
iobase => CFG_AHBIO, extcfg => CFG_GRPCI2_EXTCFG,
bar0 => CFG_GRPCI2_BAR0, bar1 => CFG_GRPCI2_BAR1,
bar2 => CFG_GRPCI2_BAR2, bar3 => CFG_GRPCI2_BAR3,
bar4 => CFG_GRPCI2_BAR4, bar5 => CFG_GRPCI2_BAR5,
fifo_depth => CFG_GRPCI2_FDEPTH, fifo_count => CFG_GRPCI2_FCOUNT,
conv_endian => CFG_GRPCI2_ENDIAN, deviceirq => CFG_GRPCI2_DEVINT,
deviceirqmask => CFG_GRPCI2_DEVINTMSK, hostirq => CFG_GRPCI2_HOSTINT,
hostirqmask => CFG_GRPCI2_HOSTINTMSK,
nsync => 2, hostrst => 1, bypass => CFG_GRPCI2_BYPASS,
debug => 0, tbapben => 0, tbpindex => 5, tbpaddr => 16#400#, tbpmask => 16#C00#
)
port map (
rstn, clk, pciclk, pci_dirq, pcii, pcio, apbi, apbo(9), ahbsi, ahbso(4), ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE), ahbmi,
open, open, open, open, open);
end generate;
grpci2xd : if (CFG_GRPCI2_MASTER+CFG_GRPCI2_TARGET) /= 0 and CFG_GRPCI2_DMA /= 0 generate
pci0 : grpci2
generic map (
memtech => memtech,
hmindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE,
hdmindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE+1,
hsindex => 4, haddr => 16#C00#, hmask => 16#E00#, ioaddr => 16#400#,
pindex => 9, paddr => 9, irq => 4, irqmode => 0,
master => CFG_GRPCI2_MASTER, target => CFG_GRPCI2_TARGET,
dma => CFG_GRPCI2_DMA, tracebuffer => CFG_GRPCI2_TRACE,
vendorid => CFG_GRPCI2_VID, deviceid => CFG_GRPCI2_DID,
classcode => CFG_GRPCI2_CLASS, revisionid => CFG_GRPCI2_RID,
cap_pointer => CFG_GRPCI2_CAP, ext_cap_pointer => CFG_GRPCI2_NCAP,
iobase => CFG_AHBIO, extcfg => CFG_GRPCI2_EXTCFG,
bar0 => CFG_GRPCI2_BAR0, bar1 => CFG_GRPCI2_BAR1,
bar2 => CFG_GRPCI2_BAR2, bar3 => CFG_GRPCI2_BAR3,
bar4 => CFG_GRPCI2_BAR4, bar5 => CFG_GRPCI2_BAR5,
fifo_depth => CFG_GRPCI2_FDEPTH, fifo_count => CFG_GRPCI2_FCOUNT,
conv_endian => CFG_GRPCI2_ENDIAN, deviceirq => CFG_GRPCI2_DEVINT,
deviceirqmask => CFG_GRPCI2_DEVINTMSK, hostirq => CFG_GRPCI2_HOSTINT,
hostirqmask => CFG_GRPCI2_HOSTINTMSK,
nsync => 2, hostrst => 1, bypass => CFG_GRPCI2_BYPASS,
debug => 0, tbapben => 0, tbpindex => 5, tbpaddr => 16#400#, tbpmask => 16#C00#
)
port map (
rstn, clk, pciclk, pci_dirq, pcii, pcio, apbi, apbo(9), ahbsi, ahbso(4), ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE), ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE+1),
open, open, open, open);
end generate;
end generate;
pcipads0 : pcipads
generic map (padtech => padtech, noreset => 1, host => 0)-- PCI pads
port map ( pci_rst, pci_gnt, pci_idsel, pci_lock, pci_ad, pci_cbe,
pci_frame, pci_irdy, pci_trdy, pci_devsel, pci_stop, pci_perr,
pci_par, pci_req, pci_serr, pci_host, pci_66, pcii, pcio );
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : greth generic map(hindex => CFG_NCPU+CFG_AHB_UART+CFG_GRPCI2_TARGET+CFG_GRPCI2_DMA+CFG_AHB_JTAG+CFG_SVGA_ENABLE,
pindex => 11, paddr => 11, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL)
port map( rst => rstn, clk => clk, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRPCI2_TARGET+CFG_GRPCI2_DMA+CFG_AHB_JTAG+CFG_SVGA_ENABLE), apbi => apbi,
apbo => apbo(11), ethi => ethi, etho => etho);
end generate;
ethpads : if (CFG_GRETH = 0) generate -- no eth
etho <= eth_out_none;
end generate;
emdio_pad : iopad generic map (tech => padtech, level => padlevel)
port map (phy_mdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, level => padlevel, arch => 1)
port map (phy_txck, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, level => padlevel, arch => 1)
port map (phy_rxck, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, level => padlevel, width => 4)
port map (phy_rxd, ethi.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech, level => padlevel)
port map (phy_rxdv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech, level => padlevel)
port map (phy_rxer, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech, level => padlevel)
port map (phy_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech, level => padlevel)
port map (phy_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, level => padlevel, width => 4)
port map (phy_txd, etho.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech, level => padlevel)
port map ( phy_txen, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech, level => padlevel)
port map (phy_txer, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech, level => padlevel)
port map (phy_mdc, etho.mdc);
phy_reset_pad : iodpad generic map (tech => padtech, level => padlevel)
port map (phy_reset_l, rstn, pci_rst);
can0 : if CFG_CAN = 1 generate
can0 : can_oc generic map (slvndx => 6, ioaddr => CFG_CANIO,
iomask => 16#FF0#, irq => CFG_CANIRQ, memtech => memtech)
port map (rstn, clk, ahbsi, ahbso(6), can_lrx, can_ltx );
can_tx_pad : outpad generic map (tech => padtech)
port map (can_txd, can_ltx);
can_rx_pad : inpad generic map (tech => padtech)
port map (can_rxd, can_lrx);
end generate;
ncan : if CFG_CAN = 0 generate ahbso(6) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map (rstn, clk, ahbsi, ahbso(7));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(7) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Misc ----------------------------------------------------------
-----------------------------------------------------------------------
errorn <= not dbgo(0).error;
led0_pad : outpad generic map (level => padlevel, tech => padtech)
port map (leds(0), errorn);
led2_7_pad : outpadv generic map (level => padlevel, width => 6, tech => padtech)
port map (leds(7 downto 2), gnd(5 downto 0));
disp_seg1_pad : outpadv generic map (level => padlevel, width => 8, tech => padtech)
port map (disp_seg1, gnd(7 downto 0));
disp_seg2_pad : outpadv generic map (level => padlevel, width => 8, tech => padtech)
port map (disp_seg2, gnd(7 downto 0));
switche_pad : inpadv generic map (tech => padtech, level => padlevel, width => 6)
port map (switches, switchesl);
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_GRPCI2_TARGET+CFG_GRPCI2_DMA+CFG_AHB_JTAG+CFG_GRETH+CFG_SVGA_ENABLE) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
-- nam2 : if CFG_PCI > 1 generate
-- ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_PCI+CFG_AHB_JTAG-1+CFG_SVGA_ENABLE) <= ahbm_none;
-- end generate;
nap0 : for i in 12 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
-- nah0 : for i in 8 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Avnet Spartan3-1500 Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
| gpl-3.0 | 126832eb4f862fafe52027c86730fb7c | 0.57279 | 3.440348 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/techmap/maps/grlfpw_net.vhd | 1 | 41,459 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: grlfpw
-- File: grlfpw.vhd
-- Author: Edvin Catovic - Gaisler Research
-- Description: GRFPU LITE / GRLFPC wrapper
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.gencomp.all;
entity grlfpw_net is
generic (tech : integer := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer range 0 to 1 := 1;
disas : integer range 0 to 1 := 0;
pipe : integer range 0 to 2 := 0
);
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi_flush : in std_ulogic; -- pipeline flush
cpi_exack : in std_ulogic; -- FP exception acknowledge
cpi_a_rs1 : in std_logic_vector(4 downto 0);
cpi_d_pc : in std_logic_vector(31 downto 0);
cpi_d_inst : in std_logic_vector(31 downto 0);
cpi_d_cnt : in std_logic_vector(1 downto 0);
cpi_d_trap : in std_ulogic;
cpi_d_annul : in std_ulogic;
cpi_d_pv : in std_ulogic;
cpi_a_pc : in std_logic_vector(31 downto 0);
cpi_a_inst : in std_logic_vector(31 downto 0);
cpi_a_cnt : in std_logic_vector(1 downto 0);
cpi_a_trap : in std_ulogic;
cpi_a_annul : in std_ulogic;
cpi_a_pv : in std_ulogic;
cpi_e_pc : in std_logic_vector(31 downto 0);
cpi_e_inst : in std_logic_vector(31 downto 0);
cpi_e_cnt : in std_logic_vector(1 downto 0);
cpi_e_trap : in std_ulogic;
cpi_e_annul : in std_ulogic;
cpi_e_pv : in std_ulogic;
cpi_m_pc : in std_logic_vector(31 downto 0);
cpi_m_inst : in std_logic_vector(31 downto 0);
cpi_m_cnt : in std_logic_vector(1 downto 0);
cpi_m_trap : in std_ulogic;
cpi_m_annul : in std_ulogic;
cpi_m_pv : in std_ulogic;
cpi_x_pc : in std_logic_vector(31 downto 0);
cpi_x_inst : in std_logic_vector(31 downto 0);
cpi_x_cnt : in std_logic_vector(1 downto 0);
cpi_x_trap : in std_ulogic;
cpi_x_annul : in std_ulogic;
cpi_x_pv : in std_ulogic;
cpi_lddata : in std_logic_vector(31 downto 0); -- load data
cpi_dbg_enable : in std_ulogic;
cpi_dbg_write : in std_ulogic;
cpi_dbg_fsr : in std_ulogic; -- FSR access
cpi_dbg_addr : in std_logic_vector(4 downto 0);
cpi_dbg_data : in std_logic_vector(31 downto 0);
cpo_data : out std_logic_vector(31 downto 0); -- store data
cpo_exc : out std_logic; -- FP exception
cpo_cc : out std_logic_vector(1 downto 0); -- FP condition codes
cpo_ccv : out std_ulogic; -- FP condition codes valid
cpo_ldlock : out std_logic; -- FP pipeline hold
cpo_holdn : out std_ulogic;
cpo_dbg_data : out std_logic_vector(31 downto 0);
rfi1_rd1addr : out std_logic_vector(3 downto 0);
rfi1_rd2addr : out std_logic_vector(3 downto 0);
rfi1_wraddr : out std_logic_vector(3 downto 0);
rfi1_wrdata : out std_logic_vector(31 downto 0);
rfi1_ren1 : out std_ulogic;
rfi1_ren2 : out std_ulogic;
rfi1_wren : out std_ulogic;
rfi2_rd1addr : out std_logic_vector(3 downto 0);
rfi2_rd2addr : out std_logic_vector(3 downto 0);
rfi2_wraddr : out std_logic_vector(3 downto 0);
rfi2_wrdata : out std_logic_vector(31 downto 0);
rfi2_ren1 : out std_ulogic;
rfi2_ren2 : out std_ulogic;
rfi2_wren : out std_ulogic;
rfo1_data1 : in std_logic_vector(31 downto 0);
rfo1_data2 : in std_logic_vector(31 downto 0);
rfo2_data1 : in std_logic_vector(31 downto 0);
rfo2_data2 : in std_logic_vector(31 downto 0)
);
end;
architecture rtl of grlfpw_net is
component grlfpw_0_axcelerator is
port(
rst : in std_logic;
clk : in std_logic;
holdn : in std_logic;
cpi_flush : in std_logic;
cpi_exack : in std_logic;
cpi_a_rs1 : in std_logic_vector (4 downto 0);
cpi_d_pc : in std_logic_vector (31 downto 0);
cpi_d_inst : in std_logic_vector (31 downto 0);
cpi_d_cnt : in std_logic_vector (1 downto 0);
cpi_d_trap : in std_logic;
cpi_d_annul : in std_logic;
cpi_d_pv : in std_logic;
cpi_a_pc : in std_logic_vector (31 downto 0);
cpi_a_inst : in std_logic_vector (31 downto 0);
cpi_a_cnt : in std_logic_vector (1 downto 0);
cpi_a_trap : in std_logic;
cpi_a_annul : in std_logic;
cpi_a_pv : in std_logic;
cpi_e_pc : in std_logic_vector (31 downto 0);
cpi_e_inst : in std_logic_vector (31 downto 0);
cpi_e_cnt : in std_logic_vector (1 downto 0);
cpi_e_trap : in std_logic;
cpi_e_annul : in std_logic;
cpi_e_pv : in std_logic;
cpi_m_pc : in std_logic_vector (31 downto 0);
cpi_m_inst : in std_logic_vector (31 downto 0);
cpi_m_cnt : in std_logic_vector (1 downto 0);
cpi_m_trap : in std_logic;
cpi_m_annul : in std_logic;
cpi_m_pv : in std_logic;
cpi_x_pc : in std_logic_vector (31 downto 0);
cpi_x_inst : in std_logic_vector (31 downto 0);
cpi_x_cnt : in std_logic_vector (1 downto 0);
cpi_x_trap : in std_logic;
cpi_x_annul : in std_logic;
cpi_x_pv : in std_logic;
cpi_lddata : in std_logic_vector (31 downto 0);
cpi_dbg_enable : in std_logic;
cpi_dbg_write : in std_logic;
cpi_dbg_fsr : in std_logic;
cpi_dbg_addr : in std_logic_vector (4 downto 0);
cpi_dbg_data : in std_logic_vector (31 downto 0);
cpo_data : out std_logic_vector (31 downto 0);
cpo_exc : out std_logic;
cpo_cc : out std_logic_vector (1 downto 0);
cpo_ccv : out std_logic;
cpo_ldlock : out std_logic;
cpo_holdn : out std_logic;
cpo_dbg_data : out std_logic_vector (31 downto 0);
rfi1_rd1addr : out std_logic_vector (3 downto 0);
rfi1_rd2addr : out std_logic_vector (3 downto 0);
rfi1_wraddr : out std_logic_vector (3 downto 0);
rfi1_wrdata : out std_logic_vector (31 downto 0);
rfi1_ren1 : out std_logic;
rfi1_ren2 : out std_logic;
rfi1_wren : out std_logic;
rfi2_rd1addr : out std_logic_vector (3 downto 0);
rfi2_rd2addr : out std_logic_vector (3 downto 0);
rfi2_wraddr : out std_logic_vector (3 downto 0);
rfi2_wrdata : out std_logic_vector (31 downto 0);
rfi2_ren1 : out std_logic;
rfi2_ren2 : out std_logic;
rfi2_wren : out std_logic;
rfo1_data1 : in std_logic_vector (31 downto 0);
rfo1_data2 : in std_logic_vector (31 downto 0);
rfo2_data1 : in std_logic_vector (31 downto 0);
rfo2_data2 : in std_logic_vector (31 downto 0));
end component;
component grlfpw_0_proasic3 is
port(
rst : in std_logic;
clk : in std_logic;
holdn : in std_logic;
cpi_flush : in std_logic;
cpi_exack : in std_logic;
cpi_a_rs1 : in std_logic_vector (4 downto 0);
cpi_d_pc : in std_logic_vector (31 downto 0);
cpi_d_inst : in std_logic_vector (31 downto 0);
cpi_d_cnt : in std_logic_vector (1 downto 0);
cpi_d_trap : in std_logic;
cpi_d_annul : in std_logic;
cpi_d_pv : in std_logic;
cpi_a_pc : in std_logic_vector (31 downto 0);
cpi_a_inst : in std_logic_vector (31 downto 0);
cpi_a_cnt : in std_logic_vector (1 downto 0);
cpi_a_trap : in std_logic;
cpi_a_annul : in std_logic;
cpi_a_pv : in std_logic;
cpi_e_pc : in std_logic_vector (31 downto 0);
cpi_e_inst : in std_logic_vector (31 downto 0);
cpi_e_cnt : in std_logic_vector (1 downto 0);
cpi_e_trap : in std_logic;
cpi_e_annul : in std_logic;
cpi_e_pv : in std_logic;
cpi_m_pc : in std_logic_vector (31 downto 0);
cpi_m_inst : in std_logic_vector (31 downto 0);
cpi_m_cnt : in std_logic_vector (1 downto 0);
cpi_m_trap : in std_logic;
cpi_m_annul : in std_logic;
cpi_m_pv : in std_logic;
cpi_x_pc : in std_logic_vector (31 downto 0);
cpi_x_inst : in std_logic_vector (31 downto 0);
cpi_x_cnt : in std_logic_vector (1 downto 0);
cpi_x_trap : in std_logic;
cpi_x_annul : in std_logic;
cpi_x_pv : in std_logic;
cpi_lddata : in std_logic_vector (31 downto 0);
cpi_dbg_enable : in std_logic;
cpi_dbg_write : in std_logic;
cpi_dbg_fsr : in std_logic;
cpi_dbg_addr : in std_logic_vector (4 downto 0);
cpi_dbg_data : in std_logic_vector (31 downto 0);
cpo_data : out std_logic_vector (31 downto 0);
cpo_exc : out std_logic;
cpo_cc : out std_logic_vector (1 downto 0);
cpo_ccv : out std_logic;
cpo_ldlock : out std_logic;
cpo_holdn : out std_logic;
cpo_dbg_data : out std_logic_vector (31 downto 0);
rfi1_rd1addr : out std_logic_vector (3 downto 0);
rfi1_rd2addr : out std_logic_vector (3 downto 0);
rfi1_wraddr : out std_logic_vector (3 downto 0);
rfi1_wrdata : out std_logic_vector (31 downto 0);
rfi1_ren1 : out std_logic;
rfi1_ren2 : out std_logic;
rfi1_wren : out std_logic;
rfi2_rd1addr : out std_logic_vector (3 downto 0);
rfi2_rd2addr : out std_logic_vector (3 downto 0);
rfi2_wraddr : out std_logic_vector (3 downto 0);
rfi2_wrdata : out std_logic_vector (31 downto 0);
rfi2_ren1 : out std_logic;
rfi2_ren2 : out std_logic;
rfi2_wren : out std_logic;
rfo1_data1 : in std_logic_vector (31 downto 0);
rfo1_data2 : in std_logic_vector (31 downto 0);
rfo2_data1 : in std_logic_vector (31 downto 0);
rfo2_data2 : in std_logic_vector (31 downto 0));
end component;
component grlfpw_0_unisim
port(
rst : in std_logic;
clk : in std_logic;
holdn : in std_logic;
cpi_flush : in std_logic;
cpi_exack : in std_logic;
cpi_a_rs1 : in std_logic_vector (4 downto 0);
cpi_d_pc : in std_logic_vector (31 downto 0);
cpi_d_inst : in std_logic_vector (31 downto 0);
cpi_d_cnt : in std_logic_vector (1 downto 0);
cpi_d_trap : in std_logic;
cpi_d_annul : in std_logic;
cpi_d_pv : in std_logic;
cpi_a_pc : in std_logic_vector (31 downto 0);
cpi_a_inst : in std_logic_vector (31 downto 0);
cpi_a_cnt : in std_logic_vector (1 downto 0);
cpi_a_trap : in std_logic;
cpi_a_annul : in std_logic;
cpi_a_pv : in std_logic;
cpi_e_pc : in std_logic_vector (31 downto 0);
cpi_e_inst : in std_logic_vector (31 downto 0);
cpi_e_cnt : in std_logic_vector (1 downto 0);
cpi_e_trap : in std_logic;
cpi_e_annul : in std_logic;
cpi_e_pv : in std_logic;
cpi_m_pc : in std_logic_vector (31 downto 0);
cpi_m_inst : in std_logic_vector (31 downto 0);
cpi_m_cnt : in std_logic_vector (1 downto 0);
cpi_m_trap : in std_logic;
cpi_m_annul : in std_logic;
cpi_m_pv : in std_logic;
cpi_x_pc : in std_logic_vector (31 downto 0);
cpi_x_inst : in std_logic_vector (31 downto 0);
cpi_x_cnt : in std_logic_vector (1 downto 0);
cpi_x_trap : in std_logic;
cpi_x_annul : in std_logic;
cpi_x_pv : in std_logic;
cpi_lddata : in std_logic_vector (31 downto 0);
cpi_dbg_enable : in std_logic;
cpi_dbg_write : in std_logic;
cpi_dbg_fsr : in std_logic;
cpi_dbg_addr : in std_logic_vector (4 downto 0);
cpi_dbg_data : in std_logic_vector (31 downto 0);
cpo_data : out std_logic_vector (31 downto 0);
cpo_exc : out std_logic;
cpo_cc : out std_logic_vector (1 downto 0);
cpo_ccv : out std_logic;
cpo_ldlock : out std_logic;
cpo_holdn : out std_logic;
cpo_dbg_data : out std_logic_vector (31 downto 0);
rfi1_rd1addr : out std_logic_vector (3 downto 0);
rfi1_rd2addr : out std_logic_vector (3 downto 0);
rfi1_wraddr : out std_logic_vector (3 downto 0);
rfi1_wrdata : out std_logic_vector (31 downto 0);
rfi1_ren1 : out std_logic;
rfi1_ren2 : out std_logic;
rfi1_wren : out std_logic;
rfi2_rd1addr : out std_logic_vector (3 downto 0);
rfi2_rd2addr : out std_logic_vector (3 downto 0);
rfi2_wraddr : out std_logic_vector (3 downto 0);
rfi2_wrdata : out std_logic_vector (31 downto 0);
rfi2_ren1 : out std_logic;
rfi2_ren2 : out std_logic;
rfi2_wren : out std_logic;
rfo1_data1 : in std_logic_vector (31 downto 0);
rfo1_data2 : in std_logic_vector (31 downto 0);
rfo2_data1 : in std_logic_vector (31 downto 0);
rfo2_data2 : in std_logic_vector (31 downto 0));
end component;
component grlfpw_0_altera
port(
rst : in std_logic;
clk : in std_logic;
holdn : in std_logic;
cpi_flush : in std_logic;
cpi_exack : in std_logic;
cpi_a_rs1 : in std_logic_vector (4 downto 0);
cpi_d_pc : in std_logic_vector (31 downto 0);
cpi_d_inst : in std_logic_vector (31 downto 0);
cpi_d_cnt : in std_logic_vector (1 downto 0);
cpi_d_trap : in std_logic;
cpi_d_annul : in std_logic;
cpi_d_pv : in std_logic;
cpi_a_pc : in std_logic_vector (31 downto 0);
cpi_a_inst : in std_logic_vector (31 downto 0);
cpi_a_cnt : in std_logic_vector (1 downto 0);
cpi_a_trap : in std_logic;
cpi_a_annul : in std_logic;
cpi_a_pv : in std_logic;
cpi_e_pc : in std_logic_vector (31 downto 0);
cpi_e_inst : in std_logic_vector (31 downto 0);
cpi_e_cnt : in std_logic_vector (1 downto 0);
cpi_e_trap : in std_logic;
cpi_e_annul : in std_logic;
cpi_e_pv : in std_logic;
cpi_m_pc : in std_logic_vector (31 downto 0);
cpi_m_inst : in std_logic_vector (31 downto 0);
cpi_m_cnt : in std_logic_vector (1 downto 0);
cpi_m_trap : in std_logic;
cpi_m_annul : in std_logic;
cpi_m_pv : in std_logic;
cpi_x_pc : in std_logic_vector (31 downto 0);
cpi_x_inst : in std_logic_vector (31 downto 0);
cpi_x_cnt : in std_logic_vector (1 downto 0);
cpi_x_trap : in std_logic;
cpi_x_annul : in std_logic;
cpi_x_pv : in std_logic;
cpi_lddata : in std_logic_vector (31 downto 0);
cpi_dbg_enable : in std_logic;
cpi_dbg_write : in std_logic;
cpi_dbg_fsr : in std_logic;
cpi_dbg_addr : in std_logic_vector (4 downto 0);
cpi_dbg_data : in std_logic_vector (31 downto 0);
cpo_data : out std_logic_vector (31 downto 0);
cpo_exc : out std_logic;
cpo_cc : out std_logic_vector (1 downto 0);
cpo_ccv : out std_logic;
cpo_ldlock : out std_logic;
cpo_holdn : out std_logic;
cpo_dbg_data : out std_logic_vector (31 downto 0);
rfi1_rd1addr : out std_logic_vector (3 downto 0);
rfi1_rd2addr : out std_logic_vector (3 downto 0);
rfi1_wraddr : out std_logic_vector (3 downto 0);
rfi1_wrdata : out std_logic_vector (31 downto 0);
rfi1_ren1 : out std_logic;
rfi1_ren2 : out std_logic;
rfi1_wren : out std_logic;
rfi2_rd1addr : out std_logic_vector (3 downto 0);
rfi2_rd2addr : out std_logic_vector (3 downto 0);
rfi2_wraddr : out std_logic_vector (3 downto 0);
rfi2_wrdata : out std_logic_vector (31 downto 0);
rfi2_ren1 : out std_logic;
rfi2_ren2 : out std_logic;
rfi2_wren : out std_logic;
rfo1_data1 : in std_logic_vector (31 downto 0);
rfo1_data2 : in std_logic_vector (31 downto 0);
rfo2_data1 : in std_logic_vector (31 downto 0);
rfo2_data2 : in std_logic_vector (31 downto 0));
end component;
component grlfpw_0_stratixii
port(
rst : in std_logic;
clk : in std_logic;
holdn : in std_logic;
cpi_flush : in std_logic;
cpi_exack : in std_logic;
cpi_a_rs1 : in std_logic_vector (4 downto 0);
cpi_d_pc : in std_logic_vector (31 downto 0);
cpi_d_inst : in std_logic_vector (31 downto 0);
cpi_d_cnt : in std_logic_vector (1 downto 0);
cpi_d_trap : in std_logic;
cpi_d_annul : in std_logic;
cpi_d_pv : in std_logic;
cpi_a_pc : in std_logic_vector (31 downto 0);
cpi_a_inst : in std_logic_vector (31 downto 0);
cpi_a_cnt : in std_logic_vector (1 downto 0);
cpi_a_trap : in std_logic;
cpi_a_annul : in std_logic;
cpi_a_pv : in std_logic;
cpi_e_pc : in std_logic_vector (31 downto 0);
cpi_e_inst : in std_logic_vector (31 downto 0);
cpi_e_cnt : in std_logic_vector (1 downto 0);
cpi_e_trap : in std_logic;
cpi_e_annul : in std_logic;
cpi_e_pv : in std_logic;
cpi_m_pc : in std_logic_vector (31 downto 0);
cpi_m_inst : in std_logic_vector (31 downto 0);
cpi_m_cnt : in std_logic_vector (1 downto 0);
cpi_m_trap : in std_logic;
cpi_m_annul : in std_logic;
cpi_m_pv : in std_logic;
cpi_x_pc : in std_logic_vector (31 downto 0);
cpi_x_inst : in std_logic_vector (31 downto 0);
cpi_x_cnt : in std_logic_vector (1 downto 0);
cpi_x_trap : in std_logic;
cpi_x_annul : in std_logic;
cpi_x_pv : in std_logic;
cpi_lddata : in std_logic_vector (31 downto 0);
cpi_dbg_enable : in std_logic;
cpi_dbg_write : in std_logic;
cpi_dbg_fsr : in std_logic;
cpi_dbg_addr : in std_logic_vector (4 downto 0);
cpi_dbg_data : in std_logic_vector (31 downto 0);
cpo_data : out std_logic_vector (31 downto 0);
cpo_exc : out std_logic;
cpo_cc : out std_logic_vector (1 downto 0);
cpo_ccv : out std_logic;
cpo_ldlock : out std_logic;
cpo_holdn : out std_logic;
cpo_dbg_data : out std_logic_vector (31 downto 0);
rfi1_rd1addr : out std_logic_vector (3 downto 0);
rfi1_rd2addr : out std_logic_vector (3 downto 0);
rfi1_wraddr : out std_logic_vector (3 downto 0);
rfi1_wrdata : out std_logic_vector (31 downto 0);
rfi1_ren1 : out std_logic;
rfi1_ren2 : out std_logic;
rfi1_wren : out std_logic;
rfi2_rd1addr : out std_logic_vector (3 downto 0);
rfi2_rd2addr : out std_logic_vector (3 downto 0);
rfi2_wraddr : out std_logic_vector (3 downto 0);
rfi2_wrdata : out std_logic_vector (31 downto 0);
rfi2_ren1 : out std_logic;
rfi2_ren2 : out std_logic;
rfi2_wren : out std_logic;
rfo1_data1 : in std_logic_vector (31 downto 0);
rfo1_data2 : in std_logic_vector (31 downto 0);
rfo2_data1 : in std_logic_vector (31 downto 0);
rfo2_data2 : in std_logic_vector (31 downto 0));
end component;
component grlfpw_0_stratixiii
port(
rst : in std_logic;
clk : in std_logic;
holdn : in std_logic;
cpi_flush : in std_logic;
cpi_exack : in std_logic;
cpi_a_rs1 : in std_logic_vector (4 downto 0);
cpi_d_pc : in std_logic_vector (31 downto 0);
cpi_d_inst : in std_logic_vector (31 downto 0);
cpi_d_cnt : in std_logic_vector (1 downto 0);
cpi_d_trap : in std_logic;
cpi_d_annul : in std_logic;
cpi_d_pv : in std_logic;
cpi_a_pc : in std_logic_vector (31 downto 0);
cpi_a_inst : in std_logic_vector (31 downto 0);
cpi_a_cnt : in std_logic_vector (1 downto 0);
cpi_a_trap : in std_logic;
cpi_a_annul : in std_logic;
cpi_a_pv : in std_logic;
cpi_e_pc : in std_logic_vector (31 downto 0);
cpi_e_inst : in std_logic_vector (31 downto 0);
cpi_e_cnt : in std_logic_vector (1 downto 0);
cpi_e_trap : in std_logic;
cpi_e_annul : in std_logic;
cpi_e_pv : in std_logic;
cpi_m_pc : in std_logic_vector (31 downto 0);
cpi_m_inst : in std_logic_vector (31 downto 0);
cpi_m_cnt : in std_logic_vector (1 downto 0);
cpi_m_trap : in std_logic;
cpi_m_annul : in std_logic;
cpi_m_pv : in std_logic;
cpi_x_pc : in std_logic_vector (31 downto 0);
cpi_x_inst : in std_logic_vector (31 downto 0);
cpi_x_cnt : in std_logic_vector (1 downto 0);
cpi_x_trap : in std_logic;
cpi_x_annul : in std_logic;
cpi_x_pv : in std_logic;
cpi_lddata : in std_logic_vector (31 downto 0);
cpi_dbg_enable : in std_logic;
cpi_dbg_write : in std_logic;
cpi_dbg_fsr : in std_logic;
cpi_dbg_addr : in std_logic_vector (4 downto 0);
cpi_dbg_data : in std_logic_vector (31 downto 0);
cpo_data : out std_logic_vector (31 downto 0);
cpo_exc : out std_logic;
cpo_cc : out std_logic_vector (1 downto 0);
cpo_ccv : out std_logic;
cpo_ldlock : out std_logic;
cpo_holdn : out std_logic;
cpo_dbg_data : out std_logic_vector (31 downto 0);
rfi1_rd1addr : out std_logic_vector (3 downto 0);
rfi1_rd2addr : out std_logic_vector (3 downto 0);
rfi1_wraddr : out std_logic_vector (3 downto 0);
rfi1_wrdata : out std_logic_vector (31 downto 0);
rfi1_ren1 : out std_logic;
rfi1_ren2 : out std_logic;
rfi1_wren : out std_logic;
rfi2_rd1addr : out std_logic_vector (3 downto 0);
rfi2_rd2addr : out std_logic_vector (3 downto 0);
rfi2_wraddr : out std_logic_vector (3 downto 0);
rfi2_wrdata : out std_logic_vector (31 downto 0);
rfi2_ren1 : out std_logic;
rfi2_ren2 : out std_logic;
rfi2_wren : out std_logic;
rfo1_data1 : in std_logic_vector (31 downto 0);
rfo1_data2 : in std_logic_vector (31 downto 0);
rfo2_data1 : in std_logic_vector (31 downto 0);
rfo2_data2 : in std_logic_vector (31 downto 0));
end component;
component grlfpw_0_cycloneiii
port(
rst : in std_logic;
clk : in std_logic;
holdn : in std_logic;
cpi_flush : in std_logic;
cpi_exack : in std_logic;
cpi_a_rs1 : in std_logic_vector (4 downto 0);
cpi_d_pc : in std_logic_vector (31 downto 0);
cpi_d_inst : in std_logic_vector (31 downto 0);
cpi_d_cnt : in std_logic_vector (1 downto 0);
cpi_d_trap : in std_logic;
cpi_d_annul : in std_logic;
cpi_d_pv : in std_logic;
cpi_a_pc : in std_logic_vector (31 downto 0);
cpi_a_inst : in std_logic_vector (31 downto 0);
cpi_a_cnt : in std_logic_vector (1 downto 0);
cpi_a_trap : in std_logic;
cpi_a_annul : in std_logic;
cpi_a_pv : in std_logic;
cpi_e_pc : in std_logic_vector (31 downto 0);
cpi_e_inst : in std_logic_vector (31 downto 0);
cpi_e_cnt : in std_logic_vector (1 downto 0);
cpi_e_trap : in std_logic;
cpi_e_annul : in std_logic;
cpi_e_pv : in std_logic;
cpi_m_pc : in std_logic_vector (31 downto 0);
cpi_m_inst : in std_logic_vector (31 downto 0);
cpi_m_cnt : in std_logic_vector (1 downto 0);
cpi_m_trap : in std_logic;
cpi_m_annul : in std_logic;
cpi_m_pv : in std_logic;
cpi_x_pc : in std_logic_vector (31 downto 0);
cpi_x_inst : in std_logic_vector (31 downto 0);
cpi_x_cnt : in std_logic_vector (1 downto 0);
cpi_x_trap : in std_logic;
cpi_x_annul : in std_logic;
cpi_x_pv : in std_logic;
cpi_lddata : in std_logic_vector (31 downto 0);
cpi_dbg_enable : in std_logic;
cpi_dbg_write : in std_logic;
cpi_dbg_fsr : in std_logic;
cpi_dbg_addr : in std_logic_vector (4 downto 0);
cpi_dbg_data : in std_logic_vector (31 downto 0);
cpo_data : out std_logic_vector (31 downto 0);
cpo_exc : out std_logic;
cpo_cc : out std_logic_vector (1 downto 0);
cpo_ccv : out std_logic;
cpo_ldlock : out std_logic;
cpo_holdn : out std_logic;
cpo_dbg_data : out std_logic_vector (31 downto 0);
rfi1_rd1addr : out std_logic_vector (3 downto 0);
rfi1_rd2addr : out std_logic_vector (3 downto 0);
rfi1_wraddr : out std_logic_vector (3 downto 0);
rfi1_wrdata : out std_logic_vector (31 downto 0);
rfi1_ren1 : out std_logic;
rfi1_ren2 : out std_logic;
rfi1_wren : out std_logic;
rfi2_rd1addr : out std_logic_vector (3 downto 0);
rfi2_rd2addr : out std_logic_vector (3 downto 0);
rfi2_wraddr : out std_logic_vector (3 downto 0);
rfi2_wrdata : out std_logic_vector (31 downto 0);
rfi2_ren1 : out std_logic;
rfi2_ren2 : out std_logic;
rfi2_wren : out std_logic;
rfo1_data1 : in std_logic_vector (31 downto 0);
rfo1_data2 : in std_logic_vector (31 downto 0);
rfo2_data1 : in std_logic_vector (31 downto 0);
rfo2_data2 : in std_logic_vector (31 downto 0));
end component;
component grlfpw_0_actfus is
port(
rst : in std_logic;
clk : in std_logic;
holdn : in std_logic;
cpi_flush : in std_logic;
cpi_exack : in std_logic;
cpi_a_rs1 : in std_logic_vector (4 downto 0);
cpi_d_pc : in std_logic_vector (31 downto 0);
cpi_d_inst : in std_logic_vector (31 downto 0);
cpi_d_cnt : in std_logic_vector (1 downto 0);
cpi_d_trap : in std_logic;
cpi_d_annul : in std_logic;
cpi_d_pv : in std_logic;
cpi_a_pc : in std_logic_vector (31 downto 0);
cpi_a_inst : in std_logic_vector (31 downto 0);
cpi_a_cnt : in std_logic_vector (1 downto 0);
cpi_a_trap : in std_logic;
cpi_a_annul : in std_logic;
cpi_a_pv : in std_logic;
cpi_e_pc : in std_logic_vector (31 downto 0);
cpi_e_inst : in std_logic_vector (31 downto 0);
cpi_e_cnt : in std_logic_vector (1 downto 0);
cpi_e_trap : in std_logic;
cpi_e_annul : in std_logic;
cpi_e_pv : in std_logic;
cpi_m_pc : in std_logic_vector (31 downto 0);
cpi_m_inst : in std_logic_vector (31 downto 0);
cpi_m_cnt : in std_logic_vector (1 downto 0);
cpi_m_trap : in std_logic;
cpi_m_annul : in std_logic;
cpi_m_pv : in std_logic;
cpi_x_pc : in std_logic_vector (31 downto 0);
cpi_x_inst : in std_logic_vector (31 downto 0);
cpi_x_cnt : in std_logic_vector (1 downto 0);
cpi_x_trap : in std_logic;
cpi_x_annul : in std_logic;
cpi_x_pv : in std_logic;
cpi_lddata : in std_logic_vector (31 downto 0);
cpi_dbg_enable : in std_logic;
cpi_dbg_write : in std_logic;
cpi_dbg_fsr : in std_logic;
cpi_dbg_addr : in std_logic_vector (4 downto 0);
cpi_dbg_data : in std_logic_vector (31 downto 0);
cpo_data : out std_logic_vector (31 downto 0);
cpo_exc : out std_logic;
cpo_cc : out std_logic_vector (1 downto 0);
cpo_ccv : out std_logic;
cpo_ldlock : out std_logic;
cpo_holdn : out std_logic;
cpo_dbg_data : out std_logic_vector (31 downto 0);
rfi1_rd1addr : out std_logic_vector (3 downto 0);
rfi1_rd2addr : out std_logic_vector (3 downto 0);
rfi1_wraddr : out std_logic_vector (3 downto 0);
rfi1_wrdata : out std_logic_vector (31 downto 0);
rfi1_ren1 : out std_logic;
rfi1_ren2 : out std_logic;
rfi1_wren : out std_logic;
rfi2_rd1addr : out std_logic_vector (3 downto 0);
rfi2_rd2addr : out std_logic_vector (3 downto 0);
rfi2_wraddr : out std_logic_vector (3 downto 0);
rfi2_wrdata : out std_logic_vector (31 downto 0);
rfi2_ren1 : out std_logic;
rfi2_ren2 : out std_logic;
rfi2_wren : out std_logic;
rfo1_data1 : in std_logic_vector (31 downto 0);
rfo1_data2 : in std_logic_vector (31 downto 0);
rfo2_data1 : in std_logic_vector (31 downto 0);
rfo2_data2 : in std_logic_vector (31 downto 0));
end component;
component grlfpw_0_proasic3e is
port(
rst : in std_logic;
clk : in std_logic;
holdn : in std_logic;
cpi_flush : in std_logic;
cpi_exack : in std_logic;
cpi_a_rs1 : in std_logic_vector (4 downto 0);
cpi_d_pc : in std_logic_vector (31 downto 0);
cpi_d_inst : in std_logic_vector (31 downto 0);
cpi_d_cnt : in std_logic_vector (1 downto 0);
cpi_d_trap : in std_logic;
cpi_d_annul : in std_logic;
cpi_d_pv : in std_logic;
cpi_a_pc : in std_logic_vector (31 downto 0);
cpi_a_inst : in std_logic_vector (31 downto 0);
cpi_a_cnt : in std_logic_vector (1 downto 0);
cpi_a_trap : in std_logic;
cpi_a_annul : in std_logic;
cpi_a_pv : in std_logic;
cpi_e_pc : in std_logic_vector (31 downto 0);
cpi_e_inst : in std_logic_vector (31 downto 0);
cpi_e_cnt : in std_logic_vector (1 downto 0);
cpi_e_trap : in std_logic;
cpi_e_annul : in std_logic;
cpi_e_pv : in std_logic;
cpi_m_pc : in std_logic_vector (31 downto 0);
cpi_m_inst : in std_logic_vector (31 downto 0);
cpi_m_cnt : in std_logic_vector (1 downto 0);
cpi_m_trap : in std_logic;
cpi_m_annul : in std_logic;
cpi_m_pv : in std_logic;
cpi_x_pc : in std_logic_vector (31 downto 0);
cpi_x_inst : in std_logic_vector (31 downto 0);
cpi_x_cnt : in std_logic_vector (1 downto 0);
cpi_x_trap : in std_logic;
cpi_x_annul : in std_logic;
cpi_x_pv : in std_logic;
cpi_lddata : in std_logic_vector (31 downto 0);
cpi_dbg_enable : in std_logic;
cpi_dbg_write : in std_logic;
cpi_dbg_fsr : in std_logic;
cpi_dbg_addr : in std_logic_vector (4 downto 0);
cpi_dbg_data : in std_logic_vector (31 downto 0);
cpo_data : out std_logic_vector (31 downto 0);
cpo_exc : out std_logic;
cpo_cc : out std_logic_vector (1 downto 0);
cpo_ccv : out std_logic;
cpo_ldlock : out std_logic;
cpo_holdn : out std_logic;
cpo_dbg_data : out std_logic_vector (31 downto 0);
rfi1_rd1addr : out std_logic_vector (3 downto 0);
rfi1_rd2addr : out std_logic_vector (3 downto 0);
rfi1_wraddr : out std_logic_vector (3 downto 0);
rfi1_wrdata : out std_logic_vector (31 downto 0);
rfi1_ren1 : out std_logic;
rfi1_ren2 : out std_logic;
rfi1_wren : out std_logic;
rfi2_rd1addr : out std_logic_vector (3 downto 0);
rfi2_rd2addr : out std_logic_vector (3 downto 0);
rfi2_wraddr : out std_logic_vector (3 downto 0);
rfi2_wrdata : out std_logic_vector (31 downto 0);
rfi2_ren1 : out std_logic;
rfi2_ren2 : out std_logic;
rfi2_wren : out std_logic;
rfo1_data1 : in std_logic_vector (31 downto 0);
rfo1_data2 : in std_logic_vector (31 downto 0);
rfo2_data1 : in std_logic_vector (31 downto 0);
rfo2_data2 : in std_logic_vector (31 downto 0));
end component;
component grlfpw_0_proasic3l is
port(
rst : in std_logic;
clk : in std_logic;
holdn : in std_logic;
cpi_flush : in std_logic;
cpi_exack : in std_logic;
cpi_a_rs1 : in std_logic_vector (4 downto 0);
cpi_d_pc : in std_logic_vector (31 downto 0);
cpi_d_inst : in std_logic_vector (31 downto 0);
cpi_d_cnt : in std_logic_vector (1 downto 0);
cpi_d_trap : in std_logic;
cpi_d_annul : in std_logic;
cpi_d_pv : in std_logic;
cpi_a_pc : in std_logic_vector (31 downto 0);
cpi_a_inst : in std_logic_vector (31 downto 0);
cpi_a_cnt : in std_logic_vector (1 downto 0);
cpi_a_trap : in std_logic;
cpi_a_annul : in std_logic;
cpi_a_pv : in std_logic;
cpi_e_pc : in std_logic_vector (31 downto 0);
cpi_e_inst : in std_logic_vector (31 downto 0);
cpi_e_cnt : in std_logic_vector (1 downto 0);
cpi_e_trap : in std_logic;
cpi_e_annul : in std_logic;
cpi_e_pv : in std_logic;
cpi_m_pc : in std_logic_vector (31 downto 0);
cpi_m_inst : in std_logic_vector (31 downto 0);
cpi_m_cnt : in std_logic_vector (1 downto 0);
cpi_m_trap : in std_logic;
cpi_m_annul : in std_logic;
cpi_m_pv : in std_logic;
cpi_x_pc : in std_logic_vector (31 downto 0);
cpi_x_inst : in std_logic_vector (31 downto 0);
cpi_x_cnt : in std_logic_vector (1 downto 0);
cpi_x_trap : in std_logic;
cpi_x_annul : in std_logic;
cpi_x_pv : in std_logic;
cpi_lddata : in std_logic_vector (31 downto 0);
cpi_dbg_enable : in std_logic;
cpi_dbg_write : in std_logic;
cpi_dbg_fsr : in std_logic;
cpi_dbg_addr : in std_logic_vector (4 downto 0);
cpi_dbg_data : in std_logic_vector (31 downto 0);
cpo_data : out std_logic_vector (31 downto 0);
cpo_exc : out std_logic;
cpo_cc : out std_logic_vector (1 downto 0);
cpo_ccv : out std_logic;
cpo_ldlock : out std_logic;
cpo_holdn : out std_logic;
cpo_dbg_data : out std_logic_vector (31 downto 0);
rfi1_rd1addr : out std_logic_vector (3 downto 0);
rfi1_rd2addr : out std_logic_vector (3 downto 0);
rfi1_wraddr : out std_logic_vector (3 downto 0);
rfi1_wrdata : out std_logic_vector (31 downto 0);
rfi1_ren1 : out std_logic;
rfi1_ren2 : out std_logic;
rfi1_wren : out std_logic;
rfi2_rd1addr : out std_logic_vector (3 downto 0);
rfi2_rd2addr : out std_logic_vector (3 downto 0);
rfi2_wraddr : out std_logic_vector (3 downto 0);
rfi2_wrdata : out std_logic_vector (31 downto 0);
rfi2_ren1 : out std_logic;
rfi2_ren2 : out std_logic;
rfi2_wren : out std_logic;
rfo1_data1 : in std_logic_vector (31 downto 0);
rfo1_data2 : in std_logic_vector (31 downto 0);
rfo2_data1 : in std_logic_vector (31 downto 0);
rfo2_data2 : in std_logic_vector (31 downto 0));
end component;
begin
alt : if (tech = altera) generate -- Cyclone, Stratix V, Cyclone V
grlfpw0 : grlfpw_0_altera
port map (rst, clk, holdn, cpi_flush, cpi_exack, cpi_a_rs1, cpi_d_pc,
cpi_d_inst, cpi_d_cnt, cpi_d_trap, cpi_d_annul, cpi_d_pv, cpi_a_pc,
cpi_a_inst, cpi_a_cnt, cpi_a_trap, cpi_a_annul, cpi_a_pv, cpi_e_pc,
cpi_e_inst, cpi_e_cnt, cpi_e_trap, cpi_e_annul, cpi_e_pv, cpi_m_pc,
cpi_m_inst, cpi_m_cnt, cpi_m_trap, cpi_m_annul, cpi_m_pv, cpi_x_pc,
cpi_x_inst, cpi_x_cnt, cpi_x_trap, cpi_x_annul, cpi_x_pv, cpi_lddata,
cpi_dbg_enable, cpi_dbg_write, cpi_dbg_fsr, cpi_dbg_addr, cpi_dbg_data,
cpo_data, cpo_exc, cpo_cc, cpo_ccv, cpo_ldlock, cpo_holdn, cpo_dbg_data,
rfi1_rd1addr, rfi1_rd2addr, rfi1_wraddr, rfi1_wrdata, rfi1_ren1,
rfi1_ren2, rfi1_wren, rfi2_rd1addr, rfi2_rd2addr, rfi2_wraddr,
rfi2_wrdata, rfi2_ren1, rfi2_ren2, rfi2_wren, rfo1_data1,
rfo1_data2, rfo2_data1, rfo2_data2 );
end generate;
strtx : if (tech = stratix1) or (tech = stratix2) generate
grlfpw0 : grlfpw_0_stratixii
port map (rst, clk, holdn, cpi_flush, cpi_exack, cpi_a_rs1, cpi_d_pc,
cpi_d_inst, cpi_d_cnt, cpi_d_trap, cpi_d_annul, cpi_d_pv, cpi_a_pc,
cpi_a_inst, cpi_a_cnt, cpi_a_trap, cpi_a_annul, cpi_a_pv, cpi_e_pc,
cpi_e_inst, cpi_e_cnt, cpi_e_trap, cpi_e_annul, cpi_e_pv, cpi_m_pc,
cpi_m_inst, cpi_m_cnt, cpi_m_trap, cpi_m_annul, cpi_m_pv, cpi_x_pc,
cpi_x_inst, cpi_x_cnt, cpi_x_trap, cpi_x_annul, cpi_x_pv, cpi_lddata,
cpi_dbg_enable, cpi_dbg_write, cpi_dbg_fsr, cpi_dbg_addr, cpi_dbg_data,
cpo_data, cpo_exc, cpo_cc, cpo_ccv, cpo_ldlock, cpo_holdn, cpo_dbg_data,
rfi1_rd1addr, rfi1_rd2addr, rfi1_wraddr, rfi1_wrdata, rfi1_ren1,
rfi1_ren2, rfi1_wren, rfi2_rd1addr, rfi2_rd2addr, rfi2_wraddr,
rfi2_wrdata, rfi2_ren1, rfi2_ren2, rfi2_wren, rfo1_data1,
rfo1_data2, rfo2_data1, rfo2_data2 );
end generate;
strtxiii : if (tech = stratix3) or (tech = stratix4) generate
grlfpw40 : grlfpw_0_stratixiii
port map (rst, clk, holdn, cpi_flush, cpi_exack, cpi_a_rs1, cpi_d_pc,
cpi_d_inst, cpi_d_cnt, cpi_d_trap, cpi_d_annul, cpi_d_pv, cpi_a_pc,
cpi_a_inst, cpi_a_cnt, cpi_a_trap, cpi_a_annul, cpi_a_pv, cpi_e_pc,
cpi_e_inst, cpi_e_cnt, cpi_e_trap, cpi_e_annul, cpi_e_pv, cpi_m_pc,
cpi_m_inst, cpi_m_cnt, cpi_m_trap, cpi_m_annul, cpi_m_pv, cpi_x_pc,
cpi_x_inst, cpi_x_cnt, cpi_x_trap, cpi_x_annul, cpi_x_pv, cpi_lddata,
cpi_dbg_enable, cpi_dbg_write, cpi_dbg_fsr, cpi_dbg_addr, cpi_dbg_data,
cpo_data, cpo_exc, cpo_cc, cpo_ccv, cpo_ldlock, cpo_holdn, cpo_dbg_data,
rfi1_rd1addr, rfi1_rd2addr, rfi1_wraddr, rfi1_wrdata, rfi1_ren1,
rfi1_ren2, rfi1_wren, rfi2_rd1addr, rfi2_rd2addr, rfi2_wraddr,
rfi2_wrdata, rfi2_ren1, rfi2_ren2, rfi2_wren, rfo1_data1,
rfo1_data2, rfo2_data1, rfo2_data2 );
end generate;
cyc3 : if (tech = cyclone3) generate
grlfpw40 : grlfpw_0_cycloneiii
port map (rst, clk, holdn, cpi_flush, cpi_exack, cpi_a_rs1, cpi_d_pc,
cpi_d_inst, cpi_d_cnt, cpi_d_trap, cpi_d_annul, cpi_d_pv, cpi_a_pc,
cpi_a_inst, cpi_a_cnt, cpi_a_trap, cpi_a_annul, cpi_a_pv, cpi_e_pc,
cpi_e_inst, cpi_e_cnt, cpi_e_trap, cpi_e_annul, cpi_e_pv, cpi_m_pc,
cpi_m_inst, cpi_m_cnt, cpi_m_trap, cpi_m_annul, cpi_m_pv, cpi_x_pc,
cpi_x_inst, cpi_x_cnt, cpi_x_trap, cpi_x_annul, cpi_x_pv, cpi_lddata,
cpi_dbg_enable, cpi_dbg_write, cpi_dbg_fsr, cpi_dbg_addr, cpi_dbg_data,
cpo_data, cpo_exc, cpo_cc, cpo_ccv, cpo_ldlock, cpo_holdn, cpo_dbg_data,
rfi1_rd1addr, rfi1_rd2addr, rfi1_wraddr, rfi1_wrdata, rfi1_ren1,
rfi1_ren2, rfi1_wren, rfi2_rd1addr, rfi2_rd2addr, rfi2_wraddr,
rfi2_wrdata, rfi2_ren1, rfi2_ren2, rfi2_wren, rfo1_data1,
rfo1_data2, rfo2_data1, rfo2_data2 );
end generate;
ax : if (tech = axcel) or (tech = axdsp) generate
grlfpw0 : grlfpw_0_axcelerator
port map (rst, clk, holdn, cpi_flush, cpi_exack, cpi_a_rs1, cpi_d_pc,
cpi_d_inst, cpi_d_cnt, cpi_d_trap, cpi_d_annul, cpi_d_pv, cpi_a_pc,
cpi_a_inst, cpi_a_cnt, cpi_a_trap, cpi_a_annul, cpi_a_pv, cpi_e_pc,
cpi_e_inst, cpi_e_cnt, cpi_e_trap, cpi_e_annul, cpi_e_pv, cpi_m_pc,
cpi_m_inst, cpi_m_cnt, cpi_m_trap, cpi_m_annul, cpi_m_pv, cpi_x_pc,
cpi_x_inst, cpi_x_cnt, cpi_x_trap, cpi_x_annul, cpi_x_pv, cpi_lddata,
cpi_dbg_enable, cpi_dbg_write, cpi_dbg_fsr, cpi_dbg_addr, cpi_dbg_data,
cpo_data, cpo_exc, cpo_cc, cpo_ccv, cpo_ldlock, cpo_holdn, cpo_dbg_data,
rfi1_rd1addr, rfi1_rd2addr, rfi1_wraddr, rfi1_wrdata, rfi1_ren1,
rfi1_ren2, rfi1_wren, rfi2_rd1addr, rfi2_rd2addr, rfi2_wraddr,
rfi2_wrdata, rfi2_ren1, rfi2_ren2, rfi2_wren, rfo1_data1,
rfo1_data2, rfo2_data1, rfo2_data2 );
end generate;
fus : if (tech = actfus) generate
grlfpw0 : grlfpw_0_actfus
port map (rst, clk, holdn, cpi_flush, cpi_exack, cpi_a_rs1, cpi_d_pc,
cpi_d_inst, cpi_d_cnt, cpi_d_trap, cpi_d_annul, cpi_d_pv, cpi_a_pc,
cpi_a_inst, cpi_a_cnt, cpi_a_trap, cpi_a_annul, cpi_a_pv, cpi_e_pc,
cpi_e_inst, cpi_e_cnt, cpi_e_trap, cpi_e_annul, cpi_e_pv, cpi_m_pc,
cpi_m_inst, cpi_m_cnt, cpi_m_trap, cpi_m_annul, cpi_m_pv, cpi_x_pc,
cpi_x_inst, cpi_x_cnt, cpi_x_trap, cpi_x_annul, cpi_x_pv, cpi_lddata,
cpi_dbg_enable, cpi_dbg_write, cpi_dbg_fsr, cpi_dbg_addr, cpi_dbg_data,
cpo_data, cpo_exc, cpo_cc, cpo_ccv, cpo_ldlock, cpo_holdn, cpo_dbg_data,
rfi1_rd1addr, rfi1_rd2addr, rfi1_wraddr, rfi1_wrdata, rfi1_ren1,
rfi1_ren2, rfi1_wren, rfi2_rd1addr, rfi2_rd2addr, rfi2_wraddr,
rfi2_wrdata, rfi2_ren1, rfi2_ren2, rfi2_wren, rfo1_data1,
rfo1_data2, rfo2_data1, rfo2_data2 );
end generate;
pa3 : if (tech = apa3) generate
grlfpw0 : grlfpw_0_proasic3
port map (rst, clk, holdn, cpi_flush, cpi_exack, cpi_a_rs1, cpi_d_pc,
cpi_d_inst, cpi_d_cnt, cpi_d_trap, cpi_d_annul, cpi_d_pv, cpi_a_pc,
cpi_a_inst, cpi_a_cnt, cpi_a_trap, cpi_a_annul, cpi_a_pv, cpi_e_pc,
cpi_e_inst, cpi_e_cnt, cpi_e_trap, cpi_e_annul, cpi_e_pv, cpi_m_pc,
cpi_m_inst, cpi_m_cnt, cpi_m_trap, cpi_m_annul, cpi_m_pv, cpi_x_pc,
cpi_x_inst, cpi_x_cnt, cpi_x_trap, cpi_x_annul, cpi_x_pv, cpi_lddata,
cpi_dbg_enable, cpi_dbg_write, cpi_dbg_fsr, cpi_dbg_addr, cpi_dbg_data,
cpo_data, cpo_exc, cpo_cc, cpo_ccv, cpo_ldlock, cpo_holdn, cpo_dbg_data,
rfi1_rd1addr, rfi1_rd2addr, rfi1_wraddr, rfi1_wrdata, rfi1_ren1,
rfi1_ren2, rfi1_wren, rfi2_rd1addr, rfi2_rd2addr, rfi2_wraddr,
rfi2_wrdata, rfi2_ren1, rfi2_ren2, rfi2_wren, rfo1_data1,
rfo1_data2, rfo2_data1, rfo2_data2 );
end generate;
pa3l : if (tech = apa3l) generate
grlfpw0 : grlfpw_0_proasic3l
port map (rst, clk, holdn, cpi_flush, cpi_exack, cpi_a_rs1, cpi_d_pc,
cpi_d_inst, cpi_d_cnt, cpi_d_trap, cpi_d_annul, cpi_d_pv, cpi_a_pc,
cpi_a_inst, cpi_a_cnt, cpi_a_trap, cpi_a_annul, cpi_a_pv, cpi_e_pc,
cpi_e_inst, cpi_e_cnt, cpi_e_trap, cpi_e_annul, cpi_e_pv, cpi_m_pc,
cpi_m_inst, cpi_m_cnt, cpi_m_trap, cpi_m_annul, cpi_m_pv, cpi_x_pc,
cpi_x_inst, cpi_x_cnt, cpi_x_trap, cpi_x_annul, cpi_x_pv, cpi_lddata,
cpi_dbg_enable, cpi_dbg_write, cpi_dbg_fsr, cpi_dbg_addr, cpi_dbg_data,
cpo_data, cpo_exc, cpo_cc, cpo_ccv, cpo_ldlock, cpo_holdn, cpo_dbg_data,
rfi1_rd1addr, rfi1_rd2addr, rfi1_wraddr, rfi1_wrdata, rfi1_ren1,
rfi1_ren2, rfi1_wren, rfi2_rd1addr, rfi2_rd2addr, rfi2_wraddr,
rfi2_wrdata, rfi2_ren1, rfi2_ren2, rfi2_wren, rfo1_data1,
rfo1_data2, rfo2_data1, rfo2_data2 );
end generate;
pa3e : if (tech = apa3e) generate
grlfpw0 : grlfpw_0_proasic3e
port map (rst, clk, holdn, cpi_flush, cpi_exack, cpi_a_rs1, cpi_d_pc,
cpi_d_inst, cpi_d_cnt, cpi_d_trap, cpi_d_annul, cpi_d_pv, cpi_a_pc,
cpi_a_inst, cpi_a_cnt, cpi_a_trap, cpi_a_annul, cpi_a_pv, cpi_e_pc,
cpi_e_inst, cpi_e_cnt, cpi_e_trap, cpi_e_annul, cpi_e_pv, cpi_m_pc,
cpi_m_inst, cpi_m_cnt, cpi_m_trap, cpi_m_annul, cpi_m_pv, cpi_x_pc,
cpi_x_inst, cpi_x_cnt, cpi_x_trap, cpi_x_annul, cpi_x_pv, cpi_lddata,
cpi_dbg_enable, cpi_dbg_write, cpi_dbg_fsr, cpi_dbg_addr, cpi_dbg_data,
cpo_data, cpo_exc, cpo_cc, cpo_ccv, cpo_ldlock, cpo_holdn, cpo_dbg_data,
rfi1_rd1addr, rfi1_rd2addr, rfi1_wraddr, rfi1_wrdata, rfi1_ren1,
rfi1_ren2, rfi1_wren, rfi2_rd1addr, rfi2_rd2addr, rfi2_wraddr,
rfi2_wrdata, rfi2_ren1, rfi2_ren2, rfi2_wren, rfo1_data1,
rfo1_data2, rfo2_data1, rfo2_data2 );
end generate;
uni : if (is_unisim(tech) = 1) generate
grlfpw0 : grlfpw_0_unisim
port map (rst, clk, holdn, cpi_flush, cpi_exack, cpi_a_rs1, cpi_d_pc,
cpi_d_inst, cpi_d_cnt, cpi_d_trap, cpi_d_annul, cpi_d_pv, cpi_a_pc,
cpi_a_inst, cpi_a_cnt, cpi_a_trap, cpi_a_annul, cpi_a_pv, cpi_e_pc,
cpi_e_inst, cpi_e_cnt, cpi_e_trap, cpi_e_annul, cpi_e_pv, cpi_m_pc,
cpi_m_inst, cpi_m_cnt, cpi_m_trap, cpi_m_annul, cpi_m_pv, cpi_x_pc,
cpi_x_inst, cpi_x_cnt, cpi_x_trap, cpi_x_annul, cpi_x_pv, cpi_lddata,
cpi_dbg_enable, cpi_dbg_write, cpi_dbg_fsr, cpi_dbg_addr, cpi_dbg_data,
cpo_data, cpo_exc, cpo_cc, cpo_ccv, cpo_ldlock, cpo_holdn, cpo_dbg_data,
rfi1_rd1addr, rfi1_rd2addr, rfi1_wraddr, rfi1_wrdata, rfi1_ren1,
rfi1_ren2, rfi1_wren, rfi2_rd1addr, rfi2_rd2addr, rfi2_wraddr,
rfi2_wrdata, rfi2_ren1, rfi2_ren2, rfi2_wren, rfo1_data1,
rfo1_data2, rfo2_data1, rfo2_data2 );
end generate;
end;
| gpl-3.0 | a2d1812012013b392f2e53a80e858e7e | 0.640271 | 2.588599 | false | false | false | false |
EliasLuiz/TCC | Teste/MemoTableTInput.vhd | 1 | 1,246 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
use work.Constants.all;
use work.DefTypes.all;
ENTITY MemoTableTInput IS
--ENTITY TraceMemory IS
PORT
(
Clock : IN STD_LOGIC := '1';
WAddress : IN STD_LOGIC_VECTOR (MemoTableTWayAddressLenght-1 DOWNTO 0);
WData : IN MemoTableTInputBus;
WEnable : IN STD_LOGIC := '0';
RAddress : IN STD_LOGIC_VECTOR (MemoTableTWayAddressLenght-1 DOWNTO 0);
RData : OUT MemoTableTInputBus
);
END MemoTableTInput;
--END TraceMemory;
ARCHITECTURE SYN OF MemoTableTInput IS
--ARCHITECTURE SYN OF TraceMemory IS
COMPONENT MemoTableTInputWay
PORT (
Clock : IN STD_LOGIC := '1';
WAddress : IN STD_LOGIC_VECTOR (MemoTableTWayAddressLenght-1 DOWNTO 0);
WData : IN MemoTableTInputEntry;
WEnable : IN STD_LOGIC := '0';
RAddress : IN STD_LOGIC_VECTOR (MemoTableTWayAddressLenght-1 DOWNTO 0);
RData : OUT MemoTableTInputEntry
);
END COMPONENT;
BEGIN
mem: FOR i IN 0 TO MemoTableTAssociativity-1 GENERATE
MemoTableTInputWay_cmp : MemoTableTInputWay
PORT MAP (
WAddress => WAddress,
Clock => Clock,
WData => WData(i),
WEnable => WEnable,
RAddress => RAddress,
RData => RData(i)
);
END GENERATE mem;
END SYN;
| gpl-3.0 | e56336994f3be6770d551a3f5ae64b74 | 0.708668 | 2.612159 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-digilent-xc3s1000/config.vhd | 1 | 5,672 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := spartan3;
constant CFG_MEMTECH : integer := spartan3;
constant CFG_PADTECH : integer := spartan3;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := spartan3;
constant CFG_CLKMUL : integer := (4);
constant CFG_CLKDIV : integer := (5);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 2 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 0;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (0);
constant CFG_PWD : integer := 0*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 1;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 1;
constant CFG_DSETSZ : integer := 8;
constant CFG_DLINE : integer := 8;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0 + 0*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 0;
constant CFG_ITLBNUM : integer := 2;
constant CFG_DTLBNUM : integer := 2;
constant CFG_TLB_TYPE : integer := 1 + 0*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2 + 64*0;
constant CFG_ATBSZ : integer := 2;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_STAT_ENABLE : integer := 0;
constant CFG_STAT_CNT : integer := 1;
constant CFG_STAT_NMAX : integer := 0;
constant CFG_STAT_DSUEN : integer := 0;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
constant CFG_ALTWIN : integer := 0;
constant CFG_REX : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- AHB ROM
constant CFG_AHBROMEN : integer := 1;
constant CFG_AHBROPIP : integer := 1;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#100#;
constant CFG_ROMMASK : integer := 16#E00# + 16#100#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#00F0#;
constant CFG_GRGPIO_WIDTH : integer := (18);
-- VGA and PS2/ interface
constant CFG_KBD_ENABLE : integer := 1;
constant CFG_VGA_ENABLE : integer := 1;
constant CFG_SVGA_ENABLE : integer := 0;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-3.0 | 0ee56f49b887fab20de5d4c79c8c44f3 | 0.643865 | 3.63823 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/techmap/maps/syncram128bw.vhd | 1 | 5,745 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: syncram128bw
-- File: syncram128bw.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: 128-bit syncronous 1-port ram with 8-bit write strobes
-- and tech selection
------------------------------------------------------------------------------
library ieee;
library techmap;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
library grlib;
use grlib.config.all;
use grlib.config_types.all;
use grlib.stdlib.all;
entity syncram128bw is
generic (tech : integer := 0; abits : integer := 6; testen : integer := 0; custombits: integer := 1);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (127 downto 0);
dataout : out std_logic_vector (127 downto 0);
enable : in std_logic_vector (15 downto 0);
write : in std_logic_vector (15 downto 0);
testin : in std_logic_vector (TESTIN_WIDTH-1 downto 0) := testin_none
);
end;
architecture rtl of syncram128bw is
component unisim_syncram128bw
generic ( abits : integer := 9);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (127 downto 0);
dataout : out std_logic_vector (127 downto 0);
enable : in std_logic_vector (15 downto 0);
write : in std_logic_vector (15 downto 0)
);
end component;
component altera_syncram128bw
generic ( abits : integer := 9);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (127 downto 0);
dataout : out std_logic_vector (127 downto 0);
enable : in std_logic_vector (15 downto 0);
write : in std_logic_vector (15 downto 0)
);
end component;
component tm65gplus_syncram128bw
generic ( abits : integer := 9);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (127 downto 0);
dataout : out std_logic_vector (127 downto 0);
enable : in std_logic_vector (15 downto 0);
write : in std_logic_vector (15 downto 0);
testin : in std_logic_vector (3 downto 0) := "0000"
);
end component;
component ut90nhbd_syncram128bw
generic ( abits : integer := 9);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (127 downto 0);
dataout : out std_logic_vector (127 downto 0);
enable : in std_logic_vector (15 downto 0);
write : in std_logic_vector (15 downto 0);
tdbn : in std_ulogic
);
end component;
signal xenable, xwrite : std_logic_vector(15 downto 0);
signal custominx,customoutx: std_logic_vector(syncram_customif_maxwidth downto 0);
begin
xenable <= enable when testen=0 or testin(TESTIN_WIDTH-2)='0' else (others => '0');
xwrite <= write when testen=0 or testin(TESTIN_WIDTH-2)='0' else (others => '0');
custominx <= (others => '0');
nocust: if syncram_has_customif(tech)=0 or has_sram128bw(tech)=0 generate
customoutx <= (others => '0');
end generate;
s64 : if has_sram128bw(tech) = 1 generate
xc2v : if (is_unisim(tech) = 1) generate
x0 : unisim_syncram128bw generic map (abits)
port map (clk, address, datain, dataout, xenable, xwrite);
end generate;
alt : if (tech = stratix2) or (tech = stratix3) or (tech = stratix4) or
(tech = cyclone3) or (tech = altera) generate
x0 : altera_syncram128bw generic map (abits)
port map (clk, address, datain, dataout, xenable, xwrite);
end generate;
tm65: if tech = tm65gplus generate
x0 : tm65gplus_syncram128bw generic map (abits)
port map (clk, address, datain, dataout, xenable, xwrite, testin);
end generate;
ut09: if tech = ut90 generate
x0 : ut90nhbd_syncram128bw generic map (abits)
port map (clk, address, datain, dataout, xenable, xwrite, testin(TESTIN_WIDTH-3));
end generate;
-- pragma translate_off
dmsg : if GRLIB_CONFIG_ARRAY(grlib_debug_level) >= 2 generate
x : process
begin
assert false report "syncram128bw: " & tost(2**abits) & "x128" &
" (" & tech_table(tech) & ")"
severity note;
wait;
end process;
end generate;
-- pragma translate_on
end generate;
nos64 : if has_sram128bw(tech) = 0 generate
rx : for i in 0 to 15 generate
x0 : syncram generic map (tech, abits, 8, testen, custombits)
port map (clk, address, datain(i*8+7 downto i*8),
dataout(i*8+7 downto i*8), enable(i), write(i), testin
);
end generate;
end generate;
end;
| gpl-3.0 | dbccfc7982bc27d5a45359740742ff5e | 0.62698 | 3.649936 | false | true | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/leon4/leon4.vhd | 1 | 27,196 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: leon4
-- File: leon4.vhd
-- Author: Cobham Gaisler AB
-- Description: LEON4 types and components
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library techmap;
use techmap.gencomp.all;
use work.leon3.l3_cstat_type;
use work.leon3.cstat_none;
use work.leon3.dsu_astat_type;
use work.leon3.dsu_astat_none;
use work.leon3.l3stat_in_type;
use work.leon3.l3stat_in_none;
use work.leon3.l3_irq_in_type;
use work.leon3.l3_irq_out_type;
use work.leon3.grfpu_in_type;
use work.leon3.grfpu_out_type;
package leon4 is
constant LEON4_VERSION : integer := 0;
type l4_debug_in_type is record
dsuen : std_ulogic; -- DSU enable
denable : std_ulogic; -- diagnostic register access enable
dbreak : std_ulogic; -- debug break-in
step : std_ulogic; -- single step
halt : std_ulogic; -- halt processor
reset : std_ulogic; -- reset processor
dwrite : std_ulogic; -- read/write
daddr : std_logic_vector(23 downto 2); -- diagnostic address
ddata : std_logic_vector(31 downto 0); -- diagnostic data
btrapa : std_ulogic; -- break on IU trap
btrape : std_ulogic; -- break on IU trap
berror : std_ulogic; -- break on IU error mode
bwatch : std_ulogic; -- break on IU watchpoint
bsoft : std_ulogic; -- break on software breakpoint (TA 1)
tenable : std_ulogic;
timer : std_logic_vector(63 downto 0); --
end record;
type l4_debug_out_type is record
data : std_logic_vector(31 downto 0);
crdy : std_ulogic;
dsu : std_ulogic;
dsumode : std_ulogic;
error : std_ulogic;
halt : std_ulogic;
pwd : std_ulogic;
idle : std_ulogic;
ipend : std_ulogic;
icnt : std_ulogic;
fcnt : std_ulogic;
optype : std_logic_vector(5 downto 0); -- instruction type
bpmiss : std_ulogic; -- branch predict miss
istat : l3_cstat_type;
dstat : l3_cstat_type;
wbhold : std_ulogic; -- write buffer hold
su : std_ulogic; -- supervisor state
ducnt : std_ulogic; -- disable timer
end record;
type l4_debug_in_vector is array (natural range <>) of l4_debug_in_type;
type l4_debug_out_vector is array (natural range <>) of l4_debug_out_type;
constant l4_dbgi_none : l4_debug_in_type := ('0', '0', '0', '0', '0', '0',
'0', (others => '0'), (others => '0'), '0', '0', '0', '0', '0', '0',
(others => '0'));
constant l4_dbgo_none : l4_debug_out_type := (X"00000000", '0', '0', '0', '0',
'0', '0', '0', '0', '0', '0', "000000", '0', cstat_none, cstat_none, '0',
'0', '0');
component leon4s
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 63 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 2 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 2 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart: integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart: integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 128 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 16#00000#; -- reset vector address [31:12]
smp : integer range 0 to 31 := 0; -- support SMP systems
cached : integer := 0; -- cacheability table
scantest : integer := 0;
wbmask : integer := 0; -- Wide-bus mask
busw : integer := 64; -- AHB/Cache data width (64/128)
netlist : integer := 0;
ft : integer := 0;
npasi : integer range 0 to 1 := 0;
pwrpsr : integer range 0 to 1 := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l4_debug_in_type;
dbgo : out l4_debug_out_type
);
end component;
component leon4x
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 63 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 2 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 2 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 128 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 31 := 0; -- support SMP systems
cached : integer := 0; -- cacheability table
clk2x : integer := 0;
scantest : integer := 0;
wbmask : integer := 0; -- Wide-bus mask
busw : integer := 64; -- AHB/Cache data width (64/128)
netlist : integer := 0; -- Use netlist
ft : integer := 0; -- FT option
npasi : integer range 0 to 1 := 0;
pwrpsr : integer range 0 to 1 := 0;
ahbpipe : integer := 0
);
port (
ahbclk : in std_ulogic; -- bus clock
cpuclk : in std_ulogic; -- cpu clock
gcpuclk: in std_ulogic; -- gated cpu clock
fpuclk : in std_ulogic;
hclken : in std_ulogic; -- bus clock enable qualifier
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l4_debug_in_type;
dbgo : out l4_debug_out_type;
fpui : out grfpu_in_type;
fpuo : in grfpu_out_type
);
end component;
component leon4sh
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 63 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 2 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 2 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 128 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 31 := 0; -- support SMP systems
cached : integer := 0; -- cacheability table
scantest : integer := 0;
wbmask : integer := 0; -- Wide-bus mask
busw : integer := 64; -- AHB/Cache data width (64/128)
netlist : integer := 0;
ft : integer := 0;
npasi : integer range 0 to 1 := 0;
pwrpsr : integer range 0 to 1 := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l4_debug_in_type;
dbgo : out l4_debug_out_type;
fpui : out grfpu_in_type;
fpuo : in grfpu_out_type
);
end component;
component leon4cg
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 63 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 2 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 2 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart: integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart: integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 128 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 16#00000#; -- reset vector address [31:12]
smp : integer range 0 to 31 := 0; -- support SMP systems
cached : integer := 0; -- cacheability table
scantest : integer := 0;
wbmask : integer := 0; -- Wide-bus mask
busw : integer := 64; -- AHB/Cache data width (64/128)
netlist : integer := 0;
ft : integer := 0;
npasi : integer range 0 to 1 := 0;
pwrpsr : integer range 0 to 1 := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l4_debug_in_type;
dbgo : out l4_debug_out_type;
gclk : in std_ulogic
);
end component;
component leon4s2x
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 31 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 2 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 2 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 128 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0; -- support SMP systems
cached : integer := 0; -- cacheability table
clk2x : integer := 1;
scantest : integer := 0;
wbmask : integer := 0; -- Wide-bus mask
busw : integer := 64; -- AHB/Cache data width (64/128)
netlist : integer := 0;
ft : integer := 0;
npasi : integer range 0 to 1 := 0;
pwrpsr : integer range 0 to 1 := 0
);
port (
clk : in std_ulogic;
gclk2 : in std_ulogic;
clk2 : in std_ulogic; -- snoop clock
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l4_debug_in_type;
dbgo : out l4_debug_out_type;
clken : in std_ulogic
);
end component;
component leon4ft
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 63 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 2 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 2 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 128 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 31 := 0; -- support SMP systems
cached : integer := 0; -- cacheability table
scantest : integer := 0;
wbmask : integer := 0; -- Wide-bus mask
busw : integer := 64; -- AHB/Cache data width (64/128)
netlist : integer := 0; -- Netlist option
ft : integer := 0; -- FT option
npasi : integer range 0 to 1 := 0;
pwrpsr : integer range 0 to 1 := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l4_debug_in_type;
dbgo : out l4_debug_out_type;
fpui : out grfpu_in_type;
fpuo : in grfpu_out_type;
gclk : in std_ulogic -- gated clock
);
end component;
type dsu4_in_type is record
enable : std_ulogic;
break : std_ulogic;
end record;
constant dsu4_astat_none : dsu_astat_type := dsu_astat_none;
type dsu4_out_type is record
active : std_ulogic;
tstop : std_ulogic;
pwd : std_logic_vector(15 downto 0);
astat : dsu_astat_type;
end record;
constant dsu4_out_none : dsu4_out_type :=
('0', '0', (others => '0'), dsu_astat_none);
component dsu4
generic (
hindex : integer := 0;
haddr : integer := 16#900#;
hmask : integer := 16#f00#;
ncpu : integer := 1;
tbits : integer := 30; -- timer bits (instruction trace time tag)
tech : integer := DEFMEMTECH;
irq : integer := 0;
kbytes : integer := 0;
bwidth : integer := 64;
ahbpf : integer := 0;
ahbwp : integer := 2;
scantest: integer := 0;
pipedbg : integer range 0 to 1 := 0;
pipeahbt: integer range 0 to 1 := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
dbgi : in l4_debug_out_vector(0 to NCPU-1);
dbgo : out l4_debug_in_vector(0 to NCPU-1);
dsui : in dsu4_in_type;
dsuo : out dsu4_out_type
);
end component;
component dsu4_2x
generic (
hindex : integer := 0;
haddr : integer := 16#900#;
hmask : integer := 16#f00#;
ncpu : integer := 1;
tbits : integer := 30; -- timer bits (instruction trace time tag)
tech : integer := DEFMEMTECH;
irq : integer := 0;
kbytes : integer := 0;
bwidth : integer := 64;
ahbpf : integer := 0;
ahbwp : integer := 2;
scantest: integer := 0;
pipedbg : integer range 0 to 1 := 0;
pipeahbt: integer range 0 to 1 := 0
);
port (
rst : in std_ulogic;
hclk : in std_ulogic;
cpuclk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
dbgi : in l4_debug_out_vector(0 to NCPU-1);
dbgo : out l4_debug_in_vector(0 to NCPU-1);
dsui : in dsu4_in_type;
dsuo : out dsu4_out_type;
hclken : in std_ulogic
);
end component;
component dsu4_mb
generic (
hindex : integer := 0;
haddr : integer := 16#900#;
hmask : integer := 16#f00#;
ncpu : integer := 1;
tbits : integer := 30; -- timer bits (instruction trace time tag)
tech : integer := DEFMEMTECH;
irq : integer := 0;
kbytes : integer := 0;
bwidth : integer := 64;
ahbpf : integer := 0;
ahbwp : integer := 2;
scantest: integer := 0;
pipedbg : integer range 0 to 1 := 0;
pipeahbt: integer range 0 to 1 := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
tahbsi : in ahb_slv_in_type;
dbgi : in l4_debug_out_vector(0 to NCPU-1);
dbgo : out l4_debug_in_vector(0 to NCPU-1);
dsui : in dsu4_in_type;
dsuo : out dsu4_out_type
);
end component;
component dsu4x
generic (
hindex : integer := 0;
haddr : integer := 16#900#;
hmask : integer := 16#f00#;
ncpu : integer := 1;
tbits : integer := 30; -- timer bits (instruction trace time tag)
tech : integer := DEFMEMTECH;
irq : integer := 0;
kbytes : integer := 0;
clk2x : integer range 0 to 1 := 0;
bwidth : integer := 64;
ahbpf : integer := 0;
ahbwp : integer := 2;
scantest: integer := 0;
pipedbg : integer := 0;
pipeahbt: integer := 0
);
port (
rst : in std_ulogic;
hclk : in std_ulogic;
cpuclk : in std_ulogic;
fcpuclk: in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
tahbsi : in ahb_slv_in_type;
dbgi : in l4_debug_out_vector(0 to NCPU-1);
dbgo : out l4_debug_in_vector(0 to NCPU-1);
dsui : in dsu4_in_type;
dsuo : out dsu4_out_type;
hclken : in std_ulogic
);
end component;
constant l4stat_in_none : l3stat_in_type := l3stat_in_none;
component l4stat
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
ncnt : integer range 1 to 64 := 4;
ncpu : integer := 1;
nmax : integer := 0;
lahben : integer := 0;
dsuen : integer := 0;
nextev : integer range 0 to 16 := 0;
apb2en : integer := 0;
pindex2 : integer := 0;
paddr2 : integer := 0;
pmask2 : integer := 16#fff#;
astaten : integer := 0;
selreq : integer := 0;
clatch : integer := 0;
forcer0 : integer range 0 to 1 := 0
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbsi : in ahb_slv_in_type;
dbgo : in l4_debug_out_vector(0 to NCPU-1);
dsuo : in dsu4_out_type := dsu4_out_none;
stati : in l3stat_in_type := l4stat_in_none;
apb2i : in apb_slv_in_type := apb_slv_in_none;
apb2o : out apb_slv_out_type;
astat : in amba_stat_type := amba_stat_none);
end component;
end;
| gpl-3.0 | 925b2bee2681b7606ba92df11cda40fa | 0.529931 | 3.421311 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-ztex-ufm-115/leon3mp.vhd | 1 | 16,962 | ------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2011 Aeroflex Gaisler AB
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
-- Patched for ZTEX: Oleg Belousov <[email protected]>
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.spi.all;
use gaisler.jtag.all;
--pragma translate_off
use gaisler.sim.all;
--pragma translate_on
use work.config.all;
library unisim;
use unisim.vcomponents.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
reset : in std_ulogic;
clk48 : in std_ulogic;
errorn : out std_logic;
-- DDR SDRAM
mcb3_dram_dq : inout std_logic_vector(15 downto 0);
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n: inout std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_a : out std_logic_vector(12 downto 0);
mcb3_dram_ba : out std_logic_vector(2 downto 0);
mcb3_dram_cke : out std_logic;
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udm : out std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
-- Debug support unit
dsubre : in std_ulogic; -- Debug Unit break (connect to button)
dsuact : out std_ulogic; -- Debug Unit break (connect to button)
-- AHB UART (debug link)
dsurx : in std_ulogic;
dsutx : out std_ulogic;
-- UART
rxd1 : in std_ulogic;
txd1 : out std_ulogic;
-- SD card
sd_dat : inout std_logic;
sd_cmd : inout std_logic;
sd_sck : inout std_logic;
sd_dat3 : out std_logic
);
end;
architecture rtl of leon3mp is
signal vcc : std_logic;
signal gnd : std_logic;
signal clk200 : std_logic;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal cgo_ddr : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal gpti : gptimer_in_type;
signal spii : spi_in_type;
signal spio : spi_out_type;
signal slvsel : std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0);
signal lclk, lclk200 : std_ulogic;
signal clkm, rstn, clkml : std_ulogic;
signal tck, tms, tdi, tdo : std_ulogic;
signal rstraw : std_logic;
signal lock : std_logic;
-- Used for connecting input/output signals to the DDR2 controller
signal core_ddr_clk : std_logic_vector(2 downto 0);
signal core_ddr_clkb : std_logic_vector(2 downto 0);
signal core_ddr_cke : std_logic_vector(1 downto 0);
signal core_ddr_csb : std_logic_vector(1 downto 0);
signal core_ddr_ad : std_logic_vector(13 downto 0);
signal core_ddr_odt : std_logic_vector(1 downto 0);
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of lock : signal is true;
attribute syn_keep of clkml : signal is true;
attribute syn_keep of clkm : signal is true;
attribute syn_preserve of clkml : signal is true;
attribute syn_preserve of clkm : signal is true;
attribute keep of lock : signal is true;
attribute keep of clkml : signal is true;
attribute keep of clkm : signal is true;
constant BOARD_FREQ : integer := 48000; -- CLK input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= '1';
gnd <= '0';
cgi.pllctrl <= "00";
cgi.pllrst <= rstraw;
rst0 : rstgen generic map (acthigh => 1)
port map (reset, clkm, lock, rstn, rstraw);
clk48_pad : clkpad generic map (tech => padtech) port map (clk48, lclk);
-- clock generator
clkgen0 : clkgen
generic map (fabtech, CFG_CLKMUL, CFG_CLKDIV, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (lclk, gnd, clkm, open, open, open, open, cgi, cgo, open, open, open);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => 1,
nahbm => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
-- LEON3 processor
leon3gen : if CFG_LEON3 = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3s
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR,
CFG_NCPU-1, CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
errorn_pad : outpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
-- LEON3 Debug Support Unit
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
dsui.enable <= '1';
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
-- Debug UART
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart
generic map (hindex => CFG_NCPU, pindex => 4, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(CFG_NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (dsurx, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (dsutx, duo.txd);
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(4) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd);
end generate;
----------------------------------------------------------------------
--- DDR2 memory controller ------------------------------------------
----------------------------------------------------------------------
mig_gen : if (CFG_MIG_DDR2 = 1) generate
clkgen_ddr : clkgen
generic map (fabtech, 25, 6, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (lclk, gnd, clk200, open, open, open, open, cgi, cgo_ddr, open, open, open);
ddrc : entity work.ahb2mig_ztex generic map(
hindex => 4, haddr => 16#400#, hmask => CFG_MIG_HMASK,
pindex => 5, paddr => 5)
port map(
mcb3_dram_dq => mcb3_dram_dq,
mcb3_rzq => mcb3_rzq,
mcb3_zio => mcb3_zio,
mcb3_dram_udqs => mcb3_dram_udqs,
mcb3_dram_udqs_n => mcb3_dram_udqs_n,
mcb3_dram_dqs => mcb3_dram_dqs,
mcb3_dram_dqs_n => mcb3_dram_dqs_n,
mcb3_dram_a => mcb3_dram_a,
mcb3_dram_ba => mcb3_dram_ba,
mcb3_dram_cke => mcb3_dram_cke,
mcb3_dram_ras_n => mcb3_dram_ras_n,
mcb3_dram_cas_n => mcb3_dram_cas_n,
mcb3_dram_we_n => mcb3_dram_we_n,
mcb3_dram_dm => mcb3_dram_dm,
mcb3_dram_udm => mcb3_dram_udm,
mcb3_dram_ck => mcb3_dram_ck,
mcb3_dram_ck_n => mcb3_dram_ck_n,
ahbsi => ahbsi,
ahbso => ahbso(4),
apbi => apbi,
apbo => apbo(5),
calib_done => lock,
rst_n_syn => rstn,
rst_n_async => rstraw,
clk_amba => clkm,
clk_mem => clk200,
test_error => open
);
end generate;
noddr : if CFG_MIG_DDR2 = 0 generate lock <= '1'; end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
-- APB Bridge
apb0 : apbctrl
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
-- Interrupt controller
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
-- General purpose timer unit
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW,
ntimers => CFG_GPT_NTIM, nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti <= gpti_dhalt_drive(dsuo.tstop);
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
-- GPIO Unit
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate
grgpio0: grgpio
generic map(pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK, nbits => 12)
port map(rstn, clkm, apbi, apbo(11), gpioi, gpioo);
end generate;
-- NOTE:
-- GPIO pads are not instantiated here. If you want to use
-- GPIO then add a top-level port, update the UCF and
-- instantiate pads for the GPIO lines as is done in other
-- template designs.
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart, fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd1;
u1i.ctsn <= '0';
u1i.extclk <= '0';
txd1 <= u1o.txd;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
spic: if CFG_SPICTRL_ENABLE = 1 generate -- SPI controller
spi1 : spictrl
generic map (pindex => 9, paddr => 9, pmask => 16#fff#, pirq => 10,
fdepth => CFG_SPICTRL_FIFO, slvselen => CFG_SPICTRL_SLVREG,
slvselsz => CFG_SPICTRL_SLVS, odmode => CFG_SPICTRL_ODMODE,
syncram => CFG_SPICTRL_SYNCRAM, ft => CFG_SPICTRL_FT)
port map (rstn, clkm, apbi, apbo(9), spii, spio, slvsel);
miso_pad : iopad generic map (tech => padtech)
port map (sd_dat, spio.miso, spio.misooen, spii.miso);
mosi_pad : iopad generic map (tech => padtech)
port map (sd_cmd, spio.mosi, spio.mosioen, spii.mosi);
sck_pad : iopad generic map (tech => padtech)
port map (sd_sck, spio.sck, spio.sckoen, spii.sck);
slvsel_pad : outpad generic map (tech => padtech)
port map (sd_dat3, slvsel(0));
spii.spisel <= '1'; -- Master only
end generate spic;
nospic: if CFG_SPICTRL_ENABLE = 0 generate apbo(9) <= apb_none; end generate;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(6) <= ahbs_none;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ahbramgen : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram
generic map (hindex => 3, haddr => CFG_AHBRADDR, tech => CFG_MEMTECH,
kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map (rstn, clkm, ahbsi, ahbso(3));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(3) <= ahbs_none; end generate;
-----------------------------------------------------------------------
-- Test report module, only used for simulation ----------------------
-----------------------------------------------------------------------
--pragma translate_off
test0 : ahbrep generic map (hindex => 5, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(5));
--pragma translate_on
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Demonstration design for ZTEX USB-FPGA Module 1.15",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end rtl;
| gpl-3.0 | d84aed30d6344af8262d96a15d5d0e2d | 0.533605 | 3.766822 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/techmap/maps/clkpad_ds.vhd | 1 | 3,159 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: clkpad
-- File: clkpad_ds.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: DS clock pad with technology wrapper
------------------------------------------------------------------------------
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allpads.all;
entity clkpad_ds is
generic (tech : integer := 0; level : integer := lvds;
voltage : integer := x33v; term : integer := 0);
port (padp, padn : in std_ulogic; o : out std_ulogic);
end;
architecture rtl of clkpad_ds is
signal gnd : std_ulogic;
begin
gnd <= '0';
gen0 : if has_ds_pads(tech) = 0 generate
o <= to_X01(padp)
-- pragma translate_off
after 1 ns
-- pragma translate_on
;
end generate;
xcv : if (tech = virtex2) or (tech = spartan3) or (tech = virtex7) or (tech = kintex7) or (tech =artix7) or (tech =zynq7000) generate
u0 : unisim_clkpad_ds generic map (level, voltage) port map (padp, padn, o);
end generate;
xc4v : if (tech = virtex4) or (tech = spartan3e) or (tech = virtex5) or
(tech = spartan6) or (tech = virtex6) generate
u0 : virtex4_clkpad_ds generic map (level, voltage) port map (padp, padn, o);
end generate;
axc : if (tech = axcel) or (tech = axdsp) generate
u0 : axcel_inpad_ds generic map (level, voltage) port map (padp, padn, o);
end generate;
pa3 : if (tech = apa3) generate
u0 : apa3_clkpad_ds generic map (level) port map (padp, padn, o);
end generate;
igl2 : if (tech = igloo2) or (tech = rtg4) generate
u0 : igloo2_clkpad_ds port map (padp, padn, o);
end generate;
pa3e : if (tech = apa3e) generate
u0 : apa3e_clkpad_ds generic map (level) port map (padp, padn, o);
end generate;
pa3l : if (tech = apa3l) generate
u0 : apa3l_clkpad_ds generic map (level) port map (padp, padn, o);
end generate;
fus : if (tech = actfus) generate
u0 : fusion_clkpad_ds generic map (level) port map (padp, padn, o);
end generate;
rht : if (tech = rhlib18t) generate
u0 : rh_lib18t_inpad_ds port map (padp, padn, o, gnd);
end generate;
end;
| gpl-3.0 | c51042bf31174777a8463f642d5be684 | 0.631212 | 3.557432 | false | false | false | false |
pwsoft/fpga_examples | rtl/general/gen_register.vhd | 1 | 1,981 | -- -----------------------------------------------------------------------
--
-- Syntiac's generic VHDL support files.
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2008 by Peter Wendrich ([email protected])
-- http://www.syntiac.com/fpga64.html
--
-- This source file is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- -----------------------------------------------------------------------
--
-- gen_register.vhd
--
-- -----------------------------------------------------------------------
--
-- D register
--
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
-- -----------------------------------------------------------------------
entity gen_register is
generic (
width : integer := 8
);
port (
clk : in std_logic;
rst : in std_logic := '0';
ena : in std_logic;
d : in unsigned(width-1 downto 0);
q : out unsigned(width-1 downto 0)
);
end entity;
-- -----------------------------------------------------------------------
architecture rtl of gen_register is
signal qReg : unsigned(d'range);
begin
q <= qReg;
process(clk) is
begin
if rising_edge(clk) then
if ena = '1' then
qReg <= d;
end if;
if rst = '1' then
qReg <= (others => '0');
end if;
end if;
end process;
end architecture;
| lgpl-2.1 | d6d44cb6117258dc41b90135a4f3bb3c | 0.503281 | 4.170526 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/grlib/sparc/cpu_disas.vhd | 1 | 4,365 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: cpu_disas
-- File: cpu_disas.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: SPARC disassembler according to SPARC V8 manual
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
use grlib.sparc.all;
use grlib.sparc_disas.all;
entity cpu_disas is
port (
clk : in std_ulogic;
rstn : in std_ulogic;
dummy : out std_ulogic;
inst : in std_logic_vector(31 downto 0);
pc : in std_logic_vector(31 downto 2);
result: in std_logic_vector(31 downto 0);
index : in std_logic_vector(3 downto 0);
wreg : in std_ulogic;
annul : in std_ulogic;
holdn : in std_ulogic;
pv : in std_ulogic;
trap : in std_ulogic;
disas : in std_ulogic);
end;
architecture behav of cpu_disas is
begin
dummy <= '1';
trc : process(clk)
variable valid : boolean;
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable fpins, fpld : boolean;
variable iindex : integer;
begin
iindex := conv_integer(index);
op := inst(31 downto 30); op3 := inst(24 downto 19);
fpins := (op = FMT3) and ((op3 = FPOP1) or (op3 = FPOP2));
fpld := (op = LDST) and ((op3 = LDF) or (op3 = LDDF) or (op3 = LDFSR));
valid := (((not annul) and pv) = '1'); --and (not ((fpins or fpld) and (trap = '0')));
valid := valid and (holdn = '1');
if rising_edge(clk) and (rstn = '1') then
print_insn (iindex, pc(31 downto 2) & "00", inst,
result, valid, trap = '1', wreg = '1'
);
end if;
end process;
end;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
use grlib.sparc.all;
use grlib.sparc_disas.all;
entity fpu_disas is
port (
clk : in std_ulogic;
rstn : in std_ulogic;
dummy : out std_ulogic;
wr2inst : in std_logic_vector(31 downto 0);
wr2pc : in std_logic_vector(31 downto 2);
divinst : in std_logic_vector(31 downto 0);
divpc : in std_logic_vector(31 downto 2);
dbg_wrdata: in std_logic_vector(63 downto 0);
index : in std_logic_vector(3 downto 0);
dbg_wren : in std_logic_vector(1 downto 0);
resv : in std_ulogic;
ld : in std_ulogic;
rdwr : in std_ulogic;
ccwr : in std_ulogic;
rdd : in std_ulogic;
div_valid : in std_ulogic;
holdn : in std_ulogic;
disas : in std_ulogic);
end;
architecture behav of fpu_disas is
begin
dummy <= '1';
trc : process(clk)
variable valid : boolean;
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable fpins, fpld : boolean;
variable iindex : integer;
begin
iindex := conv_integer(index);
if rising_edge(clk) and (rstn = '1') then
valid := ((((rdwr and not ld) or ccwr or (ld and resv)) and holdn) = '1');
print_fpinsn(0, wr2pc(31 downto 2) & "00", wr2inst, dbg_wrdata,
(rdd = '1'), valid, false, (dbg_wren /= "00"));
print_fpinsn(0, divpc(31 downto 2) & "00", divinst, dbg_wrdata,
(rdd = '1'), (div_valid and holdn) = '1', false, (dbg_wren /= "00"));
end if;
end process;
end;
-- pragma translate_on
| gpl-3.0 | e915d4cffb8abceec63c2284572dc219 | 0.601145 | 3.456057 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/gr1553b/gr1553b_pkg.vhd | 1 | 16,288 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: gr1553b_pkg
-- File: gr1553b_pkg.vhd
-- Author: Magnus Hjorth - Aeroflex Gaisler
-- Description: Package for GR1553B top-level component and user-visible types
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.ahb_mst_in_type;
use grlib.amba.ahb_mst_out_type;
use grlib.amba.apb_slv_in_type;
use grlib.amba.apb_slv_out_type;
library techmap;
use techmap.gencomp.all;
package gr1553b_pkg is
constant gr1553b_version: integer := 0;
constant gr1553b_cfgver: integer := 0;
-----------------------------------------------------------------------------
-- Types and top level component
type gr1553b_txout_type is record
busA_txP: std_logic;
busA_txN: std_logic;
busA_txen: std_logic;
busA_rxen: std_logic;
busB_txP: std_logic;
busB_txN: std_logic;
busB_txen: std_logic;
busB_rxen: std_logic;
-- For convenience, inverted versions of txen
busA_txin: std_logic;
busB_txin: std_logic;
end record;
type gr1553b_rxin_type is record
busA_rxP: std_logic;
busA_rxN: std_logic;
busB_rxP: std_logic;
busB_rxN: std_logic;
end record;
type gr1553b_auxin_type is record
extsync: std_logic;
rtaddr: std_logic_vector(4 downto 0);
rtpar: std_logic;
end record;
type gr1553b_auxout_type is record
rtsync: std_logic;
busreset: std_logic;
validcmdA: std_logic;
validcmdB: std_logic;
timedoutA: std_logic;
timedoutB: std_logic;
badreg: std_logic;
irqvec: std_logic_vector(7 downto 0);
end record;
constant gr1553b_rxin_zero: gr1553b_rxin_type :=
(busA_rxP=>'0', busA_rxN=>'0', busB_rxP=>'0', busB_rxN=>'0');
constant gr1553b_txout_zero: gr1553b_txout_type :=
('0','0','0','0','0','0','0','0','1','1');
constant gr1553b_auxin_zero: gr1553b_auxin_type :=
(extsync => '0', rtaddr => "11111", rtpar => '1');
constant gr1553b_auxout_zero: gr1553b_auxout_type :=
('0','0','0','0','0','0','0',x"00");
constant gr1553b_rxin_none: gr1553b_rxin_type := gr1553b_rxin_zero;
constant gr1553b_txout_none: gr1553b_txout_type := gr1553b_txout_zero;
constant gr1553b_auxin_none: gr1553b_auxin_type := gr1553b_auxin_zero;
constant gr1553b_auxout_none: gr1553b_auxout_type := gr1553b_auxout_zero;
component gr1553b is
generic(
hindex: integer := 0;
pindex : integer := 0;
paddr: integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
bc_enable: integer range 0 to 1 := 1;
rt_enable: integer range 0 to 1 := 1;
bm_enable: integer range 0 to 1 := 1;
bc_timer: integer range 0 to 2 := 1;
bc_rtbusmask: integer range 0 to 1 := 1;
extra_regkeys: integer range 0 to 1 := 0;
syncrst: integer range 0 to 2 := 1;
ahbendian: integer range 0 to 1 := 0;
bm_filters: integer range 0 to 1 := 1;
codecfreq: integer := 20;
sameclk: integer range 0 to 1 := 0;
codecver: integer range 0 to 2 := 0
);
port(
clk: in std_logic;
rst: in std_logic;
ahbmi: in ahb_mst_in_type;
ahbmo: out ahb_mst_out_type;
apbsi: in apb_slv_in_type;
apbso: out apb_slv_out_type;
auxin: in gr1553b_auxin_type;
auxout: out gr1553b_auxout_type;
codec_clk: in std_logic;
codec_rst: in std_logic;
txout: out gr1553b_txout_type;
txout_fb: in gr1553b_txout_type;
rxin: in gr1553b_rxin_type
);
end component;
-----------------------------------------------------------------------------
-- Pads convenience component
component gr1553b_pads is
generic (
padtech: integer;
outen_pol: integer range 0 to 1;
level: integer := ttl;
slew: integer := 0;
voltage: integer := x33v;
strength: integer := 12;
filter: integer := 0
);
port (
txout: in gr1553b_txout_type;
rxin: out gr1553b_rxin_type;
busainen : out std_logic;
busainp : in std_logic;
busainn : in std_logic;
busaoutenin : out std_logic;
busaoutp : out std_logic;
busaoutn : out std_logic;
busbinen : out std_logic;
busbinp : in std_logic;
busbinn : in std_logic;
busboutenin : out std_logic;
busboutp : out std_logic;
busboutn : out std_logic
);
end component;
-----------------------------------------------------------------------------
-- Wrappers for netlists etc.
component gr1553b_stdlogic is
generic (
bc_enable: integer range 0 to 1 := 1;
rt_enable: integer range 0 to 1 := 1;
bm_enable: integer range 0 to 1 := 1;
bc_timer: integer range 0 to 2 := 1;
bc_rtbusmask: integer range 0 to 1 := 1;
extra_regkeys: integer range 0 to 1 := 0;
syncrst: integer range 0 to 2 := 1;
ahbendian: integer range 0 to 1 := 0;
bm_filters: integer range 0 to 1 := 1;
codecfreq: integer := 20;
sameclk: integer range 0 to 1 := 0;
codecver: integer range 0 to 2 := 0
);
port (
clk: in std_logic;
rst: in std_logic;
codec_clk: in std_logic;
codec_rst: in std_logic;
-- AHB interface
mi_hgrant : in std_logic; -- bus grant
mi_hready : in std_ulogic; -- transfer done
mi_hresp : in std_logic_vector(1 downto 0); -- response type
mi_hrdata : in std_logic_vector(31 downto 0); -- read data bus
mo_hbusreq: out std_ulogic; -- bus request
mo_htrans : out std_logic_vector(1 downto 0); -- transfer type
mo_haddr : out std_logic_vector(31 downto 0); -- address bus (byte)
mo_hwrite : out std_ulogic; -- read/write
mo_hsize : out std_logic_vector(2 downto 0); -- transfer size
mo_hburst : out std_logic_vector(2 downto 0); -- burst type
mo_hwdata : out std_logic_vector(31 downto 0); -- write data bus
-- APB interface
si_psel : in std_logic; -- slave select
si_penable: in std_ulogic; -- strobe
si_paddr : in std_logic_vector(7 downto 0); -- address bus (byte addr)
si_pwrite : in std_ulogic; -- write
si_pwdata : in std_logic_vector(31 downto 0); -- write data bus
so_prdata : out std_logic_vector(31 downto 0); -- read data bus
so_pirq : out std_logic; -- interrupt bus
-- Aux signals
bcsync : in std_logic;
rtsync : out std_logic;
busreset : out std_logic;
rtaddr : in std_logic_vector(4 downto 0);
rtaddrp : in std_logic;
-- 1553 transceiver interface
busainen : out std_logic;
busainp : in std_logic;
busainn : in std_logic;
busaouten : out std_logic;
busaoutp : out std_logic;
busaoutn : out std_logic;
busbinen : out std_logic;
busbinp : in std_logic;
busbinn : in std_logic;
busbouten : out std_logic;
busboutp : out std_logic;
busboutn : out std_logic
);
end component;
component gr1553b_nlw is
generic(
tech: integer := 0;
hindex: integer := 0;
pindex : integer := 0;
paddr: integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
bc_enable: integer range 0 to 1 := 1;
rt_enable: integer range 0 to 1 := 1;
bm_enable: integer range 0 to 1 := 1;
bc_timer: integer range 0 to 2 := 1;
bc_rtbusmask: integer range 0 to 1 := 1;
extra_regkeys: integer range 0 to 1 := 0;
syncrst: integer range 0 to 2 := 1;
ahbendian: integer := 0;
bm_filters: integer range 0 to 1 := 1;
codecfreq: integer := 20;
sameclk: integer range 0 to 1 := 0;
codecver: integer range 0 to 2 := 0
);
port(
clk: in std_logic;
rst: in std_logic;
ahbmi: in ahb_mst_in_type;
ahbmo: out ahb_mst_out_type;
apbsi: in apb_slv_in_type;
apbso: out apb_slv_out_type;
auxin: in gr1553b_auxin_type;
auxout: out gr1553b_auxout_type;
codec_clk: in std_logic;
codec_rst: in std_logic;
txout: out gr1553b_txout_type;
txout_fb: in gr1553b_txout_type;
rxin: in gr1553b_rxin_type
);
end component;
-----------------------------------------------------------------------------
-- APB Register definitions
constant REG_IRQSTATUS: std_logic_vector := x"00";
constant REG_IRQENABLE: std_logic_vector := x"04";
constant REG_BCSTATUS: std_logic_vector := x"40";
constant REG_BCACTION: std_logic_vector := x"44";
constant REG_BCSCHEMADDR: std_logic_vector := x"48";
constant REG_BCASYNCADDR: std_logic_vector := x"4C";
constant REG_BCTIME: std_logic_vector := x"50";
constant REG_BCWAKEUP: std_logic_vector := x"54";
constant REG_BCIRQSRC: std_logic_vector := x"58";
constant REG_BCRTBUSMASK: std_logic_vector := x"5C";
constant REG_BCSCHEMSLOT: std_logic_vector := x"68";
constant REG_BCASYNCSLOT: std_logic_vector := x"6C";
constant REG_RTSTATUS: std_logic_vector := x"80";
constant REG_RTCONFIG: std_logic_vector := x"84";
constant REG_RTBUSSTAT: std_logic_vector := x"88";
constant REG_RTBUSWORDS: std_logic_vector := x"8C";
constant REG_RTSYNC: std_logic_vector := x"90";
constant REG_RTTABLEADDR: std_logic_vector := x"94";
constant REG_RTMODECONFIG: std_logic_vector := x"98";
constant REG_RTTIMETAG: std_logic_vector := x"A4";
constant REG_RTLOGMASK: std_logic_vector := x"AC";
constant REG_RTLOGPOS: std_logic_vector := x"B0";
constant REG_RTIRQSRC: std_logic_vector := x"B4";
constant REG_BMSTATUS: std_logic_vector := x"C0";
constant REG_BMCONFIG: std_logic_vector := x"C4";
constant REG_BMADDRFILT: std_logic_vector := x"C8";
constant REG_BMSAFILT: std_logic_vector := x"CC";
constant REG_BMMCFILT: std_logic_vector := x"D0";
constant REG_BMBUFSTART: std_logic_vector := x"D4";
constant REG_BMBUFEND: std_logic_vector := x"D8";
constant REG_BMBUFPOS: std_logic_vector := x"DC";
constant REG_BMTIMETAG: std_logic_vector := x"E0";
-----------------------------------------------------------------------------
-- Embedded RT core
component grrt is
generic (
codecfreq: integer := 20;
sameclk : integer := 1;
syncrst : integer range 0 to 1 := 1
);
port (
-- Clock and reset
clk : in std_ulogic;
rst : in std_ulogic;
clk1553 : in std_ulogic;
rst1553 : in std_ulogic;
-- Control signals
rtaddr : in std_logic_vector(4 downto 0);
rtaddrp : in std_ulogic;
rtstat : in std_logic_vector(3 downto 0); -- 3=SR, 2=busy 1=SSF 0=TF
ad31en : in std_ulogic; -- 1=RT31 is normal addr, 0=RT31 is broadcast
rtsync : out std_ulogic;
rtreset : out std_ulogic;
stamp : out std_ulogic;
-- Front-end interface
phase : out std_logic_vector(1 downto 0);
transfer : out std_logic_vector(11 downto 0);
resp : in std_logic_vector(1 downto 0);
tfrerror : out std_ulogic;
txdata : in std_logic_vector(15 downto 0);
rxdata : out std_logic_vector(15 downto 0);
datardy : in std_ulogic;
datarw : out std_ulogic;
-- 1553 transceiver interface
aoutin : out std_ulogic;
aoutp : out std_ulogic;
aoutn : out std_ulogic;
ainen : out std_ulogic;
ainp : in std_ulogic;
ainn : in std_ulogic;
boutin : out std_ulogic;
boutp : out std_ulogic;
boutn : out std_ulogic;
binen : out std_ulogic;
binp : in std_ulogic;
binn : in std_ulogic;
-- Fail-safe timer feedback
aoutp_fb : in std_logic;
aoutn_fb : in std_logic;
boutp_fb : in std_logic;
boutn_fb : in std_logic
);
end component;
-----------------------------------------------------------------------------
-- Test signal generators
component gr1553b_tgapb is
generic(
pindex : integer := 0;
paddr: integer := 0;
pmask : integer := 16#fff#;
codecfreq: integer := 20;
extmodeen: integer range 0 to 1 := 0;
rawmodeen: integer range 0 to 1 := 0;
rawmemtech: integer := 0
);
port(
clk: in std_logic;
rst: in std_logic;
codec_clk: in std_logic;
codec_rst: in std_logic;
apbsi: in apb_slv_in_type;
apbso: out apb_slv_out_type;
txout_core: in gr1553b_txout_type;
rxin_core: out gr1553b_rxin_type;
txout_bus: out gr1553b_txout_type;
rxin_bus: in gr1553b_rxin_type;
testing: out std_logic
);
end component;
-----------------------------------------------------------------------------
-- Simulation types and components for test bench
-- U=Undefined, X=Unknown, 0=Zero, +=High, -=Low
type uwire1553 is ('U','X','0','+','-');
type uwire1553_array is array(natural range <>) of uwire1553;
function resolved (a: uwire1553_array) return uwire1553;
subtype wire1553 is resolved uwire1553;
component simtrans1553_single is
generic (
txdelay: time := 200 ns;
rxdelay: time := 450 ns
);
port (
buswire: inout wire1553;
rxen: in std_logic;
txin: in std_logic;
txP: in std_logic;
txN: in std_logic;
rxP: out std_logic;
rxN: out std_logic
);
end component;
component simtrans1553 is
generic (
txdelay: time := 200 ns;
rxdelay: time := 450 ns
);
port (
busA: inout wire1553;
busB: inout wire1553;
rxenA: in std_logic;
txinA: in std_logic;
txAP: in std_logic;
txAN: in std_logic;
rxAP: out std_logic;
rxAN: out std_logic;
rxenB: in std_logic;
txinB: in std_logic;
txBP: in std_logic;
txBN: in std_logic;
rxBP: out std_logic;
rxBN: out std_logic
);
end component;
component combine1553 is
port (
clk: in std_ulogic;
txin1,rxen1: in std_ulogic;
tx1P,tx1N: in std_ulogic;
rx1P,rx1N: out std_ulogic;
txin2,rxen2: in std_ulogic;
tx2P,tx2N: in std_ulogic;
rx2P,rx2N: out std_ulogic;
txin,rxen: out std_ulogic;
txP,txN: out std_ulogic;
rxP,rxN: in std_ulogic
);
end component;
end package;
package body gr1553b_pkg is
function resolved (a: uwire1553_array) return uwire1553 is
variable w,w2: uwire1553;
begin
w := a(a'left);
for q in a'range loop
w2 := a(q);
if w /= w2 then
case w is
when 'U' => w := 'X';
when 'X' => null;
when '0' => w := w2;
when '+' | '-' => if w2 /= '0' then w:='X'; end if;
end case;
end if;
end loop;
return w;
end;
end package body;
| gpl-3.0 | d28e63685308dc4969c91d6dd948ba87 | 0.561272 | 3.494529 | false | false | false | false |
firecake/IRIS | FPGA/VHDL/ipcore_dir/RAM/example_design/RAM_prod.vhd | 1 | 10,791 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: RAM_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : spartan3a
-- C_XDEVICEFAMILY : spartan3a
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 2
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 0
-- C_INIT_FILE_NAME : no_coe_file_loaded
-- C_USE_DEFAULT_DATA : 1
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 32
-- C_READ_WIDTH_A : 32
-- C_WRITE_DEPTH_A : 4096
-- C_READ_DEPTH_A : 4096
-- C_ADDRA_WIDTH : 12
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 32
-- C_READ_WIDTH_B : 32
-- C_WRITE_DEPTH_B : 4096
-- C_READ_DEPTH_B : 4096
-- C_ADDRB_WIDTH : 12
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 1
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY RAM_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END RAM_prod;
ARCHITECTURE xilinx OF RAM_prod IS
COMPONENT RAM_exdes IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Port B
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : RAM_exdes
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA,
--Port B
WEB => WEB,
ADDRB => ADDRB,
DINB => DINB,
DOUTB => DOUTB,
CLKB => CLKB
);
END xilinx;
| gpl-3.0 | 86930c28a5da95b4bc94e2194f429c36 | 0.476601 | 3.837482 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/ambatest/ahbtbp.vhd | 1 | 37,055 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ahbtbp
-- File: ahbtbp.vhd
-- Author: Nils-Johan Wessman - Gaisler Research
-- Description: AHB Testbench package
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
package ahbtbp is
type ahbtbm_ctrl_type is record
delay : std_logic_vector(7 downto 0);
dbgl : integer;
reset : std_logic;
use128 : integer;
end record;
type ahbtbm_access_type is record
haddr : std_logic_vector(31 downto 0);
hdata : std_logic_vector(31 downto 0);
hdata128 : std_logic_vector(127 downto 0);
htrans : std_logic_vector(1 downto 0);
hburst : std_logic_vector(2 downto 0);
hsize : std_logic_vector(2 downto 0);
hprot : std_logic_vector(3 downto 0);
hwrite : std_logic;
ctrl : ahbtbm_ctrl_type;
end record;
type ahbtbm_status_type is record
err : std_logic;
ecount : std_logic_vector(15 downto 0);
eaddr : std_logic_vector(31 downto 0);
edatac : std_logic_vector(31 downto 0);
edatar : std_logic_vector(31 downto 0);
hresp : std_logic_vector(1 downto 0);
end record;
type ahbtbm_access_array_type is array (0 to 1) of ahbtbm_access_type;
type ahbtbm_ctrl_in_type is record
ac : ahbtbm_access_type;
end record;
type ahbtbm_ctrl_out_type is record
rst : std_logic;
clk : std_logic;
update : std_logic;
dvalid : std_logic;
hrdata : std_logic_vector(31 downto 0);
hrdata128 : std_logic_vector(127 downto 0);
status : ahbtbm_status_type;
end record;
type ahbtb_ctrl_type is record
i : ahbtbm_ctrl_in_type;
o : ahbtbm_ctrl_out_type;
end record;
constant ac_idle : ahbtbm_access_type :=
(haddr => x"00000000", hdata => x"00000000",
hdata128 => x"00000000000000000000000000000000",
htrans => "00", hburst =>"000", hsize => "000", hprot => "0000", hwrite => '0',
ctrl => (delay => x"00", dbgl => 100, reset =>'0', use128 => 0));
constant ctrli_idle : ahbtbm_ctrl_in_type :=(ac => ac_idle);
constant ctrlo_nodrive : ahbtbm_ctrl_out_type :=(rst => 'H', clk => 'H',
update => 'H', dvalid => 'H', hrdata => (others => 'H'), hrdata128 => (others => 'H'),
status => (err => 'H', ecount => (others => 'H'), eaddr => (others => 'H'),
edatac => (others => 'H'), edatar => (others => 'H'),
hresp => (others => 'H')));
impure function ptime return string;
-- pragma translate_off
-----------------------------------------------------------------------------
-- AHB testbench Master
-----------------------------------------------------------------------------
component ahbtbm is
generic (
hindex : integer := 0;
hirq : integer := 0;
venid : integer := 0;
devid : integer := 0;
version : integer := 0;
chprot : integer := 3;
incaddr : integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ctrli : in ahbtbm_ctrl_in_type;
ctrlo : out ahbtbm_ctrl_out_type;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type
);
end component;
-----------------------------------------------------------------------------
-- AHB testbench Slave
-----------------------------------------------------------------------------
component ahbtbs is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end component;
-----------------------------------------------------------------------------
-- dprint (Debug print)
-----------------------------------------------------------------------------
procedure dprint(
constant doprint : in boolean := true;
constant s : in string);
procedure dprint(
constant s : in string);
-----------------------------------------------------------------------------
-- AMBATB Init
-----------------------------------------------------------------------------
procedure ahbtbminit(
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBATB DONE
-----------------------------------------------------------------------------
procedure ahbtbmdone(
constant stop: in integer;
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBATB Idle
-----------------------------------------------------------------------------
procedure ahbtbmidle(
constant sync: in boolean;
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure ahbwrite(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(31 downto 0);
constant size : in std_logic_vector(1 downto 0);
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB write access (htrans)
-----------------------------------------------------------------------------
procedure ahbwrite(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(31 downto 0);
constant size : in std_logic_vector(1 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB write access (htrans,hprot)
-----------------------------------------------------------------------------
procedure ahbwrite(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(31 downto 0);
constant size : in std_logic_vector(1 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
constant hprot : in std_logic_vector(3 downto 0);
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB write access (Inc Burst)
-----------------------------------------------------------------------------
procedure ahbwrite(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(31 downto 0);
constant size : in std_logic_vector(1 downto 0);
constant count : in integer;
constant debug : in integer;
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure ahbread(
constant address : in std_logic_vector(31 downto 0); -- Address
constant data : in std_logic_vector(31 downto 0); -- Data
constant size : in std_logic_vector(1 downto 0);
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB read access (htrans)
-----------------------------------------------------------------------------
procedure ahbread(
constant address : in std_logic_vector(31 downto 0); -- Address
constant data : in std_logic_vector(31 downto 0); -- Data
constant size : in std_logic_vector(1 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB read access (htrans,hprot)
-----------------------------------------------------------------------------
procedure ahbread(
constant address : in std_logic_vector(31 downto 0); -- Address
constant data : in std_logic_vector(31 downto 0); -- Data
constant size : in std_logic_vector(1 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
constant hprot : in std_logic_vector(3 downto 0);
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB read access (Inc Burst)
-----------------------------------------------------------------------------
procedure ahbread(
constant address : in std_logic_vector(31 downto 0); -- Start address
constant data : in std_logic_vector(31 downto 0); -- Start data
constant size : in std_logic_vector(1 downto 0);
constant count : in integer;
constant debug : in integer;
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB(128) write access (htrans)
-----------------------------------------------------------------------------
procedure ahb128write(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(127 downto 0);
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB(128) write access (htrans,hprot)
-----------------------------------------------------------------------------
procedure ahb128write(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(127 downto 0);
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
constant hprot : in std_logic_vector(3 downto 0);
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB(128) read access (htrans)
-----------------------------------------------------------------------------
procedure ahb128read(
constant address : in std_logic_vector(31 downto 0); -- Address
constant data : in std_logic_vector(127 downto 0); -- Data
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB(128) read access (htrans,hprot)
-----------------------------------------------------------------------------
procedure ahb128read(
constant address : in std_logic_vector(31 downto 0); -- Address
constant data : in std_logic_vector(127 downto 0); -- Data
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
constant hprot : in std_logic_vector(3 downto 0);
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB(64) write access (htrans)
-----------------------------------------------------------------------------
procedure ahb64write(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(63 downto 0);
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB(64) write access (htrans,hprot)
-----------------------------------------------------------------------------
procedure ahb64write(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(63 downto 0);
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
constant hprot : in std_logic_vector(3 downto 0);
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB(64) read access (htrans)
-----------------------------------------------------------------------------
procedure ahb64read(
constant address : in std_logic_vector(31 downto 0); -- Address
constant data : in std_logic_vector(63 downto 0); -- Data
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type);
-----------------------------------------------------------------------------
-- AMBA AHB(64) read access (htrans,hprot)
-----------------------------------------------------------------------------
procedure ahb64read(
constant address : in std_logic_vector(31 downto 0); -- Address
constant data : in std_logic_vector(63 downto 0); -- Data
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
constant hprot : in std_logic_vector(3 downto 0);
signal ctrl : inout ahbtb_ctrl_type);
end ahbtbp;
package body ahbtbp is
impure function ptime return string is
variable s : string(1 to 20);
variable length : integer := tost(NOW / 1 ns)'length;
begin
s(1 to length + 9) :="Time: " & tost(NOW / 1 ns) & "ns ";
return s(1 to length + 9);
end function ptime;
-----------------------------------------------------------------------------
-- dprint (Debug print)
-----------------------------------------------------------------------------
procedure dprint(
constant doprint : in boolean := true;
constant s : in string) is
begin
if doprint = true then
print(s);
end if;
end procedure dprint;
procedure dprint(
constant s : in string) is
begin
print(s);
end procedure dprint;
-----------------------------------------------------------------------------
-- AHBTB init
-----------------------------------------------------------------------------
procedure ahbtbminit(
signal ctrl : inout ahbtb_ctrl_type) is
begin
ctrl.o <= ctrlo_nodrive;
ctrl.i <= ctrli_idle;
--ctrli.ac.hburst <= "000"; ctrli.ac.hsize <= "010";
--ctrli.ac.haddr <= x"00000000"; ctrli.ac.hdata <= x"00000000";
--ctrli.ac.htrans <= "00"; ctrli.ac.hwrite <= '0';
wait until ctrl.o.rst = '1';
print("**********************************************************");
print(" AHBTBM Testbench Init");
print("**********************************************************");
end procedure ahbtbminit;
-----------------------------------------------------------------------------
-- AMBTB DONE
-----------------------------------------------------------------------------
procedure ahbtbmdone(
constant stop: in integer;
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
print("**********************************************************");
print(" AHBTBM Testbench Done");
print("**********************************************************");
wait for 100 ns;
assert stop = 0
report "ahbtb testbench done!"
severity FAILURE;
end procedure ahbtbmdone;
-----------------------------------------------------------------------------
-- AMBTB Idle
-----------------------------------------------------------------------------
procedure ahbtbmidle(
constant sync: in boolean;
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
if sync = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
end if;
end procedure ahbtbmidle;
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure ahbwrite(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(31 downto 0);
constant size : in std_logic_vector(1 downto 0);
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 0;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hburst <= "000"; ctrl.i.ac.hsize <= '0' & size;
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata <= data;
ctrl.i.ac.htrans <= "10"; ctrl.i.ac.hwrite <= '1'; ctrl.i.ac.hburst <= "000";
ctrl.i.ac.hprot <= "1110";
if appidle = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
end if;
end procedure ahbwrite;
-----------------------------------------------------------------------------
-- AMBA AHB write access (htrans)
-----------------------------------------------------------------------------
procedure ahbwrite(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(31 downto 0);
constant size : in std_logic_vector(1 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 0;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hburst <= "000"; ctrl.i.ac.hsize <= '0' & size;
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata <= data;
ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '1';
ctrl.i.ac.hburst <= "00" & hburst;
ctrl.i.ac.hprot <= "1110";
if appidle = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
end if;
end procedure ahbwrite;
-----------------------------------------------------------------------------
-- AMBA AHB write access (Inc Burst)
-----------------------------------------------------------------------------
procedure ahbwrite(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(31 downto 0);
constant size : in std_logic_vector(1 downto 0);
constant count : in integer;
constant debug : in integer;
signal ctrl : inout ahbtb_ctrl_type) is
variable vaddr : std_logic_vector(31 downto 0);
variable vdata : std_logic_vector(31 downto 0);
variable vhtrans : std_logic_vector(1 downto 0);
begin
--ctrl.o <= ctrlo_nodrive;
vaddr := address; vdata := data; vhtrans := "10";
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 0;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hburst <= "000"; ctrl.i.ac.hsize <= '0' & size;
ctrl.i.ac.hwrite <= '1'; ctrl.i.ac.hburst <= "001";
ctrl.i.ac.hprot <= "1110";
for i in 0 to count - 1 loop
ctrl.i.ac.haddr <= vaddr; ctrl.i.ac.hdata <= vdata;
ctrl.i.ac.htrans <= vhtrans;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
vaddr := vaddr + x"4"; vdata := vdata + 1;
vhtrans := "11";
end loop;
ctrl.i <= ctrli_idle;
end procedure ahbwrite;
-----------------------------------------------------------------------------
-- AMBA AHB write access (htrans,hprot)
-----------------------------------------------------------------------------
procedure ahbwrite(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(31 downto 0);
constant size : in std_logic_vector(1 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
constant hprot : in std_logic_vector(3 downto 0);
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 0;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hburst <= "000"; ctrl.i.ac.hsize <= '0' & size;
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata <= data;
ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '1';
ctrl.i.ac.hburst <= "00" & hburst;
ctrl.i.ac.hprot <= hprot;
if appidle = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
end if;
end procedure ahbwrite;
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure ahbread(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(31 downto 0);
constant size : in std_logic_vector(1 downto 0);
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 0;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hsize <= '0' & size;
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata <= data;
ctrl.i.ac.htrans <= "10"; ctrl.i.ac.hwrite <= '0'; ctrl.i.ac.hburst <= "000";
ctrl.i.ac.hprot <= "1110";
if appidle = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
end if;
end procedure ahbread;
-----------------------------------------------------------------------------
-- AMBA AHB read access (htrans)
-----------------------------------------------------------------------------
procedure ahbread(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(31 downto 0);
constant size : in std_logic_vector(1 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 0;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hsize <= '0' & size;
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata <= data;
ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '0';
ctrl.i.ac.hburst <= "00" & hburst;
ctrl.i.ac.hprot <= "1110";
if appidle = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
end if;
end procedure ahbread;
-----------------------------------------------------------------------------
-- AMBA AHB read access (Inc Burst)
-----------------------------------------------------------------------------
procedure ahbread(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(31 downto 0);
constant size : in std_logic_vector(1 downto 0);
constant count : in integer;
constant debug : in integer;
signal ctrl : inout ahbtb_ctrl_type) is
variable vaddr : std_logic_vector(31 downto 0);
variable vdata : std_logic_vector(31 downto 0);
variable vhtrans : std_logic_vector(1 downto 0);
begin
--ctrl.o <= ctrlo_nodrive;
vaddr := address; vdata := data; vhtrans := "10";
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 0;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hburst <= "000"; ctrl.i.ac.hsize <= '0' & size;
ctrl.i.ac.hwrite <= '0'; ctrl.i.ac.hburst <= "001";
ctrl.i.ac.hprot <= "1110";
for i in 0 to count - 1 loop
ctrl.i.ac.haddr <= vaddr; ctrl.i.ac.hdata <= vdata;
ctrl.i.ac.htrans <= vhtrans;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
vaddr := vaddr + x"4"; vdata := vdata + 1;
vhtrans := "11";
end loop;
ctrl.i <= ctrli_idle;
end procedure ahbread;
-----------------------------------------------------------------------------
-- AMBA AHB read access (htrans)
-----------------------------------------------------------------------------
procedure ahbread(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(31 downto 0);
constant size : in std_logic_vector(1 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
constant hprot : in std_logic_vector(3 downto 0);
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 0;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hsize <= '0' & size;
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata <= data;
ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '0';
ctrl.i.ac.hburst <= "00" & hburst;
ctrl.i.ac.hprot <= hprot;
if appidle = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
end if;
end procedure ahbread;
-----------------------------------------------------------------------------
-- AMBA AHB(128) write access (htrans)
-----------------------------------------------------------------------------
procedure ahb128write(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(127 downto 0);
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 1;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hsize <= size;
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata128 <= data;
ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '1';
ctrl.i.ac.hburst <= "00" & hburst;
ctrl.i.ac.hprot <= "1110";
if appidle = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
end if;
end procedure ahb128write;
-----------------------------------------------------------------------------
-- AMBA AHB(128) write access (htrans,hprot)
-----------------------------------------------------------------------------
procedure ahb128write(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(127 downto 0);
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
constant hprot : in std_logic_vector(3 downto 0);
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 1;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hsize <= size;
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata128 <= data;
ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '1';
ctrl.i.ac.hburst <= "00" & hburst;
ctrl.i.ac.hprot <= hprot;
if appidle = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
end if;
end procedure ahb128write;
-----------------------------------------------------------------------------
-- AMBA AHB(128) read access (htrans)
-----------------------------------------------------------------------------
procedure ahb128read(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(127 downto 0);
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 1;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hsize <= size;
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata128 <= data;
ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '0';
ctrl.i.ac.hburst <= "00" & hburst;
ctrl.i.ac.hprot <= "1110";
if appidle = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
end if;
end procedure ahb128read;
-----------------------------------------------------------------------------
-- AMBA AHB(128) read access (htrans,hprot)
-----------------------------------------------------------------------------
procedure ahb128read(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(127 downto 0);
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
constant hprot : in std_logic_vector(3 downto 0);
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 1;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hsize <= size;
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata128 <= data;
ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '0';
ctrl.i.ac.hburst <= "00" & hburst;
ctrl.i.ac.hprot <= hprot;
if appidle = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
end if;
end procedure ahb128read;
-----------------------------------------------------------------------------
-- AMBA AHB(64) write access (htrans)
-----------------------------------------------------------------------------
procedure ahb64write(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(63 downto 0);
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 1;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hsize <= size;
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata128 <= data & data;
ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '1';
ctrl.i.ac.hburst <= "00" & hburst;
ctrl.i.ac.hprot <= "1110";
if appidle = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
end if;
end procedure ahb64write;
-----------------------------------------------------------------------------
-- AMBA AHB(64) write access (htrans,hprot)
-----------------------------------------------------------------------------
procedure ahb64write(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(63 downto 0);
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
constant hprot : in std_logic_vector(3 downto 0);
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 1;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hsize <= size;
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata128 <= data & data;
ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '1';
ctrl.i.ac.hburst <= "00" & hburst;
ctrl.i.ac.hprot <= hprot;
if appidle = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
end if;
end procedure ahb64write;
-----------------------------------------------------------------------------
-- AMBA AHB(64) read access (htrans)
-----------------------------------------------------------------------------
procedure ahb64read(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(63 downto 0);
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 1;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hsize <= size;
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata128 <= data & data;
ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '0';
ctrl.i.ac.hburst <= "00" & hburst;
ctrl.i.ac.hprot <= "1110";
if appidle = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
end if;
end procedure ahb64read;
-----------------------------------------------------------------------------
-- AMBA AHB(64) read access (htrans,hprot)
-----------------------------------------------------------------------------
procedure ahb64read(
constant address : in std_logic_vector(31 downto 0);
constant data : in std_logic_vector(63 downto 0);
constant size : in std_logic_vector(2 downto 0);
constant htrans : in std_logic_vector(1 downto 0);
constant hburst : in std_logic;
constant debug : in integer;
constant appidle : in boolean;
constant hprot : in std_logic_vector(3 downto 0);
signal ctrl : inout ahbtb_ctrl_type) is
begin
--ctrl.o <= ctrlo_nodrive;
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i.ac.ctrl.use128 <= 1;
ctrl.i.ac.ctrl.dbgl <= debug;
ctrl.i.ac.hsize <= size;
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata128 <= data & data;
ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '0';
ctrl.i.ac.hburst <= "00" & hburst;
ctrl.i.ac.hprot <= hprot;
if appidle = true then
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
ctrl.i <= ctrli_idle;
end if;
end procedure ahb64read;
-- pragma translate_on
end ahbtbp;
| gpl-3.0 | bf7be972b67b8e1fcacd11fa966f63a6 | 0.525624 | 3.838305 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/srmmu/libmmu.vhd | 1 | 11,193 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: leon3
-- File: leon3.vhd
-- Author: Konrad Eisele, Jiri Gaisler, Gaisler Research
-- Description: MMU component declaration
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.mmuconfig.all;
use gaisler.mmuiface.all;
package libmmu is
component mmu
generic (
tech : integer range 0 to NTECH := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
mmupgsz : integer range 0 to 5 := 0;
ramcbits : integer := 1
);
port (
rst : in std_logic;
clk : in std_logic;
mmudci : in mmudc_in_type;
mmudco : out mmudc_out_type;
mmuici : in mmuic_in_type;
mmuico : out mmuic_out_type;
mcmmo : in memory_mm_out_type;
mcmmi : out memory_mm_in_type;
testin : in std_logic_vector(TESTIN_WIDTH-1 downto 0) := testin_none
);
end component;
function TLB_CreateCamWrite( two_data : std_logic_vector(31 downto 0);
read : std_logic;
lvl : std_logic_vector(1 downto 0);
ctx : std_logic_vector(M_CTX_SZ-1 downto 0);
vaddr : std_logic_vector(31 downto 0)
) return tlbcam_reg;
procedure TLB_CheckFault( ACC : in std_logic_vector(2 downto 0);
isid : in mmu_idcache;
su : in std_logic;
read : in std_logic;
fault_pro : out std_logic;
fault_pri : out std_logic );
procedure TLB_MergeData( mmupgsz : in integer range 0 to 5;
mmctrl : in mmctrl_type1;
LVL : in std_logic_vector(1 downto 0);
PTE : in std_logic_vector(31 downto 0);
data : in std_logic_vector(31 downto 0);
transdata : out std_logic_vector(31 downto 0));
function TLB_CreateCamTrans( vaddr : std_logic_vector(31 downto 0);
read : std_logic;
ctx : std_logic_vector(M_CTX_SZ-1 downto 0)
) return tlbcam_tfp;
function TLB_CreateCamFlush( data : std_logic_vector(31 downto 0);
ctx : std_logic_vector(M_CTX_SZ-1 downto 0)
) return tlbcam_tfp;
subtype mmu_gpsz_typ is integer range 0 to 3;
function MMU_getpagesize( mmupgsz : in integer range 0 to 4;
mmctrl : in mmctrl_type1
) return mmu_gpsz_typ;
end;
package body libmmu is
procedure TLB_CheckFault( ACC : in std_logic_vector(2 downto 0);
isid : in mmu_idcache;
su : in std_logic;
read : in std_logic;
fault_pro : out std_logic;
fault_pri : out std_logic ) is
variable c_isd : std_logic;
begin
fault_pro := '0';
fault_pri := '0';
-- use '0' == icache '1' == dcache
if isid = id_icache then
c_isd := '0';
else
c_isd := '1';
end if;
case ACC is
when "000" => fault_pro := (not c_isd) or (not read);
when "001" => fault_pro := (not c_isd);
when "010" => fault_pro := (not read);
when "011" => null;
when "100" => fault_pro := (c_isd);
when "101" => fault_pro := (not c_isd) or ((not read) and (not su));
when "110" => fault_pri := (not su);
fault_pro := (not read);
when "111" => fault_pri := (not su);
when others => null;
end case;
end;
procedure TLB_MergeData( mmupgsz : in integer range 0 to 5;
mmctrl : in mmctrl_type1;
LVL : in std_logic_vector(1 downto 0);
PTE : in std_logic_vector(31 downto 0);
data : in std_logic_vector(31 downto 0);
transdata : out std_logic_vector(31 downto 0) ) is
variable pagesize : integer range 0 to 3;
begin
--# merge data
transdata := (others => '0');
pagesize := MMU_getpagesize(mmupgsz, mmctrl);
case pagesize is
when 1 =>
-- 8k
case LVL is
when LVL_PAGE => transdata := PTE(P8K_PTE_PPN32PAG_U downto P8K_PTE_PPN32PAG_D) & data(P8K_VA_OFFPAG_U downto P8K_VA_OFFPAG_D);
when LVL_SEGMENT => transdata := PTE(P8K_PTE_PPN32SEG_U downto P8K_PTE_PPN32SEG_D) & data(P8K_VA_OFFSEG_U downto P8K_VA_OFFSEG_D);
when LVL_REGION => transdata := PTE(P8K_PTE_PPN32REG_U downto P8K_PTE_PPN32REG_D) & data(P8K_VA_OFFREG_U downto P8K_VA_OFFREG_D);
when LVL_CTX => transdata := data(P8K_VA_OFFCTX_U downto P8K_VA_OFFCTX_D);
when others => transdata := (others => 'X');
end case;
when 2 =>
-- 16k
case LVL is
when LVL_PAGE => transdata := PTE(P16K_PTE_PPN32PAG_U downto P16K_PTE_PPN32PAG_D) & data(P16K_VA_OFFPAG_U downto P16K_VA_OFFPAG_D);
when LVL_SEGMENT => transdata := PTE(P16K_PTE_PPN32SEG_U downto P16K_PTE_PPN32SEG_D) & data(P16K_VA_OFFSEG_U downto P16K_VA_OFFSEG_D);
when LVL_REGION => transdata := PTE(P16K_PTE_PPN32REG_U downto P16K_PTE_PPN32REG_D) & data(P16K_VA_OFFREG_U downto P16K_VA_OFFREG_D);
when LVL_CTX => transdata := data(P16K_VA_OFFCTX_U downto P16K_VA_OFFCTX_D);
when others => transdata := (others => 'X');
end case;
when 3 =>
-- 32k
case LVL is
when LVL_PAGE => transdata := PTE(P32K_PTE_PPN32PAG_U downto P32K_PTE_PPN32PAG_D) & data(P32K_VA_OFFPAG_U downto P32K_VA_OFFPAG_D);
when LVL_SEGMENT => transdata := PTE(P32K_PTE_PPN32SEG_U downto P32K_PTE_PPN32SEG_D) & data(P32K_VA_OFFSEG_U downto P32K_VA_OFFSEG_D);
when LVL_REGION => transdata := PTE(P32K_PTE_PPN32REG_U downto P32K_PTE_PPN32REG_D) & data(P32K_VA_OFFREG_U downto P32K_VA_OFFREG_D);
when LVL_CTX => transdata := data(P32K_VA_OFFCTX_U downto P32K_VA_OFFCTX_D);
when others => transdata := (others => 'X');
end case;
when others =>
-- 4k
case LVL is
when LVL_PAGE => transdata := PTE(PTE_PPN32PAG_U downto PTE_PPN32PAG_D) & data(VA_OFFPAG_U downto VA_OFFPAG_D);
when LVL_SEGMENT => transdata := PTE(PTE_PPN32SEG_U downto PTE_PPN32SEG_D) & data(VA_OFFSEG_U downto VA_OFFSEG_D);
when LVL_REGION => transdata := PTE(PTE_PPN32REG_U downto PTE_PPN32REG_D) & data(VA_OFFREG_U downto VA_OFFREG_D);
when LVL_CTX => transdata := data(VA_OFFCTX_U downto VA_OFFCTX_D);
when others => transdata := (others => 'X');
end case;
end case;
end;
function TLB_CreateCamWrite( two_data : std_logic_vector(31 downto 0);
read : std_logic;
lvl : std_logic_vector(1 downto 0);
ctx : std_logic_vector(M_CTX_SZ-1 downto 0);
vaddr : std_logic_vector(31 downto 0)
) return tlbcam_reg is
variable tlbcam_tagwrite : tlbcam_reg;
begin
tlbcam_tagwrite.ET := two_data(PT_ET_U downto PT_ET_D);
tlbcam_tagwrite.ACC := two_data(PTE_ACC_U downto PTE_ACC_D);
tlbcam_tagwrite.M := two_data(PTE_M) or (not read); -- tw : p-update modified
tlbcam_tagwrite.R := '1';
case tlbcam_tagwrite.ACC is -- tw : p-su ACC >= 6
when "110" | "111" => tlbcam_tagwrite.SU := '1';
when others => tlbcam_tagwrite.SU := '0';
end case;
tlbcam_tagwrite.VALID := '1';
tlbcam_tagwrite.LVL := lvl;
tlbcam_tagwrite.I1 := vaddr(VA_I1_U downto VA_I1_D);
tlbcam_tagwrite.I2 := vaddr(VA_I2_U downto VA_I2_D);
tlbcam_tagwrite.I3 := vaddr(VA_I3_U downto VA_I3_D);
tlbcam_tagwrite.CTX := ctx;
tlbcam_tagwrite.PPN := two_data(PTE_PPN_U downto PTE_PPN_D);
tlbcam_tagwrite.C := two_data(PTE_C);
return tlbcam_tagwrite;
end;
function MMU_getpagesize( mmupgsz : in integer range 0 to 4;
mmctrl : in mmctrl_type1
) return mmu_gpsz_typ is
variable pagesize : mmu_gpsz_typ;
begin
if mmupgsz = 4 then pagesize := conv_integer(mmctrl.pagesize); -- variable
else pagesize := mmupgsz; end if;
return pagesize;
end;
function TLB_CreateCamTrans( vaddr : std_logic_vector(31 downto 0);
read : std_logic;
ctx : std_logic_vector(M_CTX_SZ-1 downto 0)
) return tlbcam_tfp is
variable mtag : tlbcam_tfp;
begin
mtag.TYP := (others => '0');
mtag.I1 := vaddr(VA_I1_U downto VA_I1_D);
mtag.I2 := vaddr(VA_I2_U downto VA_I2_D);
mtag.I3 := vaddr(VA_I3_U downto VA_I3_D);
mtag.CTX := ctx;
mtag.M := not (read);
return mtag;
end;
function TLB_CreateCamFlush( data : std_logic_vector(31 downto 0);
ctx : std_logic_vector(M_CTX_SZ-1 downto 0)
) return tlbcam_tfp is
variable ftag : tlbcam_tfp;
begin
ftag.TYP := data(FPTY_U downto FPTY_D);
ftag.I1 := data(FPA_I1_U downto FPA_I1_D);
ftag.I2 := data(FPA_I2_U downto FPA_I2_D);
ftag.I3 := data(FPA_I3_U downto FPA_I3_D);
ftag.CTX := ctx;
ftag.M := '0';
return ftag;
end;
end;
| gpl-3.0 | 96f0926dffec0d5d53c13611740b5be6 | 0.530063 | 3.585202 | false | false | false | false |
GLADICOS/SPACEWIRESYSTEMC | rtl/RTL_SL/spwxmit_fast.vhd | 2 | 28,908 | --
-- SpaceWire Transmitter
--
-- This entity translates outgoing characters and tokens into
-- data-strobe signalling.
--
-- The output stage is driven by a separate transmission clock "txclk" which
-- will typically be faster than the system clock. The actual transmission
-- rate is determined by dividing the transmission clock by an integer factor.
--
-- The code is tuned for implementation on Xilinx Spartan-3.
--
-- Concept
-- -------
--
-- Logic in the system clock domain generates a stream of tokens to be
-- transmitted. These tokens are encoded as instances of the token_type
-- record. Tokens are queued in a two-slot FIFO buffer (r.token0 and r.token1)
-- with a 1-bit pointer (r.tokmux) pointing to the head of the queue.
-- When a token is pushed into the buffer, a flag register is flipped
-- (r.sysflip0 and r.sysflip1) to indicate to the txclk domain that the
-- buffer slot has been refilled.
--
-- The txclk domain pulls tokens from the FIFO buffer, flipping flag
-- registers (rtx.txflip0 and rtx.txflip1) to indicate to the system clock
-- domain that a token has been pulled. When the system clock domain detects
-- that a token has been consumed, it refills the buffer slot with a new
-- token (assuming that there are tokens waiting to be transmitted).
-- Whenever the FIFO buffer is empty, the txclk domain sends NULLs instead.
-- This can happen either when there are no tokens to send, or when the
-- system clock domain is late to refill the buffer.
--
-- Details
-- -------
--
-- Logic in the system clock domain accepts transmission requests through
-- the external interface of the entity. Pending requests are translated
-- into a stream of tokens. The tokens are pushed to the txclk domain through
-- the FIFO buffer as described above.
--
-- The data path through the txclk domain is divided into stages B through F
-- in a half-hearted attempt to keep things simple.
--
-- Stage B takes a token from the FIFO buffer and updates a buffer status
-- flag to indicate that the buffer slot needs to be refilled. If the FIFO
-- is empty, a NULL is inserted. Stage B is triggered one clock after
-- stage E switches to a new token. If the previous token was ESC, stage B
-- skips a turn because stage C will already know what to do.
--
-- Stage C takes a token from stage B and translates it into a bit pattern.
-- Time codes and NULL tokens are broken into two separate tokens starting
-- with ESC. Stage C is triggered one clock after the shift buffer in
-- stage E drops to 3 tokens.
--
-- Stage D completes the task of translating tokens to bit patterns and
-- distinguishes between 10-bit and 4-bit tokens. It is not explicitly
-- triggered but simply follows stage C.
--
-- Stage E is the bit shift register. It shifts when "txclken" is high.
-- A one-hot counter keeps track of the number of bits remaining in
-- the register. When the register falls empty, it loads a new 10-bit or
-- 4-bit pattern as prepared by stage D. Stage E also computes parity.
--
-- Stage F performs data strobe encoding. When the transmitter is disabled,
-- the outputs of stage F fall to zero in a controlled way.
--
-- To generate the transmission bit clock, the txclk is divided by an
-- integer factor (divcnt+1) using an 8-bit down counter. The implementation
-- of this counter has become quite complicated in order to meet timing goals.
-- The counter consists of 4 blocks of two bits each (txclkcnt), with a
-- carry-save concept used between blocks (txclkcy). Detection of terminal
-- count (txclkdone) has a pipeline delay of two cycles. Therefore a separate
-- concept is used if the initial count is less than 2 (txdivnorm). This is
-- all glued together in the final assignment to txclken.
--
-- The initial count for txclk division (divcnt) comes from the system clock
-- domain and thus needs to be synchronized for use in the txclk domain.
-- To facilitate this, the system clock domain latches the value of divcnt
-- once every 6 sysclk cycles and sets a flag to indicate when the latched
-- value can safely be used by the txclk domain.
--
-- A tricky aspect of the design is the initial state of the txclk logic.
-- When the transmitter is enabled (txen goes high), the txclk logic starts
-- with the first ESC pattern already set up in stage D, and stage C ready
-- to produce the FCT part of the first NULL.
--
-- The following guidelines are used to get good timing for the txclk domain:
-- * The new value of a register depends on at most 4 inputs (single LUT),
-- or in a few cases on 5 inputs (two LUTs and F5MUX).
-- * Synchronous resets may be used, but only if the reset signal comes
-- directly from a register (no logic in set/reset path);
-- * Clock enables may be used, but only if the enable signal comes directly
-- from a register (no logic in clock enable path).
--
-- Synchronization issues
-- ----------------------
--
-- There is a two-slot FIFO buffer between the system and txclk domains.
-- After the txclk domain pulls a token from the buffer, the system clock
-- domain should ideally refill the buffer before the txclk domain again
-- tries to pull from the same buffer slot. If the refill occurs late,
-- the txclk domain needs to insert a NULL token which is inefficient
-- use of bandwidth.
--
-- Assuming the transmission consists of a stream of data characters,
-- 10 bits per character, there are exactly 2*10 bit periods between
-- successive reads from the same buffer slot by the txclk logic.
--
-- The time needed for the system clock logic to refill a buffer slot =
-- 1 txclk period (update of rtx.txflipN)
-- + 1 txclk period (routing delay between domains)
-- + 2 sysclk periods (synchronizer for txflipN)
-- + 1 sysclk period (refill buffer slot and update r.sysflipN)
-- + 1 txclk period (routing delay between domains)
-- + 2 txclk periods (synchronizer for sysflipN)
-- = 5 txclk periods + 3 sysclk periods
--
-- If for example txclk is 4 times as fast as sysclk, this amounts to
-- 5 txclk + 3 sysclk = 5 + 3*4 txclk = 17 txclk
-- is less than 20 bit periods even at maximum transmission rate, so
-- no problem there.
--
-- This is different when the data stream includes 4-bit tokens.
-- See the manual for further comments.
--
-- Implementation guidelines
-- -------------------------
--
-- To minimize clock skew, IOB flip-flops should be used to drive
-- spw_do and spw_so.
--
-- "txclk" must be at least as fast as the system clock;
-- "txclk" does not need to be phase-related to the system clock;
-- it is allowed for "txclk" to be equal to "clk".
--
-- The following timing constraints are needed:
-- * PERIOD constraint on the system clock;
-- * PERIOD constraint on "txclk";
-- * FROM-TO constraint from "txclk" to the system clock, equal to
-- one "txclk" period;
-- * FROM-TO constraint from the system clock to "txclk", equal to
-- one "txclk" period.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.spwpkg.all;
entity spwxmit_fast is
port (
-- System clock.
clk: in std_logic;
-- Transmit clock.
txclk: in std_logic;
-- Synchronous reset (active-high)
-- Used asynchronously by fast clock domain (must be glitch-free).
rst: in std_logic;
-- Scaling factor minus 1, used to scale the system clock into the
-- transmission bit rate. The system clock is divided by
-- (unsigned(divcnt) + 1). Changing this signal will immediately
-- change the transmission rate.
divcnt: in std_logic_vector(7 downto 0);
-- Input signals from spwlink.
xmiti: in spw_xmit_in_type;
-- Output signals to spwlink.
xmito: out spw_xmit_out_type;
-- Data Out signal to SpaceWire bus.
spw_do: out std_logic;
-- Strobe Out signal to SpaceWire bus.
spw_so: out std_logic
);
-- Turn off FSM extraction to avoid synchronization problems.
attribute FSM_EXTRACT: string;
attribute FSM_EXTRACT of spwxmit_fast: entity is "NO";
end entity spwxmit_fast;
architecture spwxmit_fast_arch of spwxmit_fast is
-- Convert boolean to std_logic.
type bool_to_logic_type is array(boolean) of std_ulogic;
constant bool_to_logic: bool_to_logic_type := (false => '0', true => '1');
-- Data records passed between clock domains.
type token_type is record
tick: std_ulogic; -- send time code
fct: std_ulogic; -- send FCT
fctpiggy: std_ulogic; -- send FCT and N-char
flag: std_ulogic; -- send EOP or EEP
char: std_logic_vector(7 downto 0); -- character or time code
end record;
-- Registers in txclk domain
type txregs_type is record
-- sync to system clock domain
txflip0: std_ulogic;
txflip1: std_ulogic;
-- stage B
b_update: std_ulogic;
b_mux: std_ulogic;
b_txflip: std_ulogic;
b_valid: std_ulogic;
b_token: token_type;
-- stage C
c_update: std_ulogic;
c_busy: std_ulogic;
c_esc: std_ulogic;
c_fct: std_ulogic;
c_bits: std_logic_vector(8 downto 0);
-- stage D
d_bits: std_logic_vector(8 downto 0);
d_cnt4: std_ulogic;
d_cnt10: std_ulogic;
-- stage E
e_valid: std_ulogic;
e_shift: std_logic_vector(9 downto 0);
e_count: std_logic_vector(9 downto 0);
e_parity: std_ulogic;
-- stage F
f_spwdo: std_ulogic;
f_spwso: std_ulogic;
-- tx clock enable logic
txclken: std_ulogic;
txclkpre: std_ulogic;
txclkcnt: std_logic_vector(7 downto 0);
txclkcy: std_logic_vector(2 downto 0);
txclkdone: std_logic_vector(1 downto 0);
txclkdiv: std_logic_vector(7 downto 0);
txdivnorm: std_ulogic;
end record;
-- Registers in system clock domain
type regs_type is record
-- sync status to txclk domain
txenreg: std_ulogic;
txdivreg: std_logic_vector(7 downto 0);
txdivnorm: std_ulogic;
txdivtmp: std_logic_vector(1 downto 0);
txdivsafe: std_ulogic;
-- data stream to txclk domain
sysflip0: std_ulogic;
sysflip1: std_ulogic;
token0: token_type;
token1: token_type;
tokmux: std_ulogic;
-- transmitter management
pend_fct: std_ulogic; -- '1' if an outgoing FCT is pending
pend_char: std_ulogic; -- '1' if an outgoing N-Char is pending
pend_data: std_logic_vector(8 downto 0); -- control flag and data bits of pending char
pend_tick: std_ulogic; -- '1' if an outgoing time tick is pending
pend_time: std_logic_vector(7 downto 0); -- data bits of pending time tick
allow_fct: std_ulogic; -- '1' when allowed to send FCTs
allow_char: std_ulogic; -- '1' when allowed to send data and time
sent_fct: std_ulogic; -- '1' when at least one FCT token was sent
end record;
-- Initial state of system clock domain
constant token_reset: token_type := (
tick => '0',
fct => '0',
fctpiggy => '0',
flag => '0',
char => (others => '0') );
constant regs_reset: regs_type := (
txenreg => '0',
txdivreg => (others => '0'),
txdivnorm => '0',
txdivtmp => "00",
txdivsafe => '0',
sysflip0 => '0',
sysflip1 => '0',
token0 => token_reset,
token1 => token_reset,
tokmux => '0',
pend_fct => '0',
pend_char => '0',
pend_data => (others => '0'),
pend_tick => '0',
pend_time => (others => '0'),
allow_fct => '0',
allow_char => '0',
sent_fct => '0' );
-- Signals that are re-synchronized from system clock to txclk domain.
type synctx_type is record
rstn: std_ulogic;
sysflip0: std_ulogic;
sysflip1: std_ulogic;
txen: std_ulogic;
txdivsafe: std_ulogic;
end record;
-- Signals that are re-synchronized from txclk to system clock domain.
type syncsys_type is record
txflip0: std_ulogic;
txflip1: std_ulogic;
end record;
-- Registers
signal rtx: txregs_type;
signal rtxin: txregs_type;
signal r: regs_type := regs_reset;
signal rin: regs_type;
-- Synchronized signals after crossing clock domains.
signal synctx: synctx_type;
signal syncsys: syncsys_type;
-- Output flip-flops
signal s_spwdo: std_logic;
signal s_spwso: std_logic;
-- Force use of IOB flip-flops
attribute IOB: string;
attribute IOB of s_spwdo: signal is "TRUE";
attribute IOB of s_spwso: signal is "TRUE";
begin
-- Reset synchronizer for txclk domain.
synctx_rst: syncdff
port map ( clk => txclk, rst => rst, di => '1', do => synctx.rstn );
-- Synchronize signals from system clock domain to txclk domain.
synctx_sysflip0: syncdff
port map ( clk => txclk, rst => rst, di => r.sysflip0, do => synctx.sysflip0 );
synctx_sysflip1: syncdff
port map ( clk => txclk, rst => rst, di => r.sysflip1, do => synctx.sysflip1 );
synctx_txen: syncdff
port map ( clk => txclk, rst => rst, di => r.txenreg, do => synctx.txen );
synctx_txdivsafe: syncdff
port map ( clk => txclk, rst => rst, di => r.txdivsafe, do => synctx.txdivsafe );
-- Synchronize signals from txclk domain to system clock domain.
syncsys_txflip0: syncdff
port map ( clk => clk, rst => rst, di => rtx.txflip0, do => syncsys.txflip0 );
syncsys_txflip1: syncdff
port map ( clk => clk, rst => rst, di => rtx.txflip1, do => syncsys.txflip1 );
-- Drive SpaceWire output signals
spw_do <= s_spwdo;
spw_so <= s_spwso;
-- Combinatorial process
process (r, rtx, rst, divcnt, xmiti, synctx, syncsys) is
variable v: regs_type;
variable vtx: txregs_type;
variable v_needtoken: std_ulogic;
variable v_havetoken: std_ulogic;
variable v_token: token_type;
begin
v := r;
vtx := rtx;
v_needtoken := '0';
v_havetoken := '0';
v_token := token_reset;
-- ---- FAST CLOCK DOMAIN ----
-- Stage B: Multiplex tokens from system clock domain.
-- Update stage B three bit periods after updating stage C
-- (i.e. in time for the next update of stage C).
-- Do not update stage B if stage C is indicating that it needs to
-- send a second token to complete its task.
vtx.b_update := rtx.txclken and rtx.e_count(0) and (not rtx.c_busy);
if rtx.b_mux = '0' then
vtx.b_txflip := rtx.txflip0;
else
vtx.b_txflip := rtx.txflip1;
end if;
if rtx.b_update = '1' then
if rtx.b_mux = '0' then
-- get token from slot 0
vtx.b_valid := synctx.sysflip0 xor rtx.b_txflip;
vtx.b_token := r.token0;
-- update mux flag if we got a valid token
vtx.b_mux := synctx.sysflip0 xor rtx.b_txflip;
vtx.txflip0 := synctx.sysflip0;
vtx.txflip1 := rtx.txflip1;
else
-- get token from slot 1
vtx.b_valid := synctx.sysflip1 xor rtx.b_txflip;
vtx.b_token := r.token1;
-- update mux flag if we got a valid token
vtx.b_mux := not (synctx.sysflip1 xor rtx.b_txflip);
vtx.txflip0 := rtx.txflip0;
vtx.txflip1 := synctx.sysflip1;
end if;
end if;
-- Stage C: Prepare to transmit EOP, EEP or a data character.
vtx.c_update := rtx.txclken and rtx.e_count(3);
if rtx.c_update = '1' then
-- NULL is broken into two tokens: ESC + FCT.
-- Time-codes are broken into two tokens: ESC + char.
-- Enable c_esc on the first pass of a NULL or a time-code.
vtx.c_esc := (rtx.b_token.tick or (not rtx.b_valid)) and
(not rtx.c_esc);
-- Enable c_fct on the first pass of an FCT and on
-- the second pass of a NULL (also the first pass, but c_esc
-- is stronger than c_fct).
vtx.c_fct := (rtx.b_token.fct and (not rtx.c_busy)) or
(not rtx.b_valid);
-- Enable c_busy on the first pass of a NULL or a time-code
-- or a piggy-backed FCT. This will tell stage B that we are
-- not done yet.
vtx.c_busy := (rtx.b_token.tick or (not rtx.b_valid) or
rtx.b_token.fctpiggy) and (not rtx.c_busy);
if rtx.b_token.flag = '1' then
if rtx.b_token.char(0) = '0' then
-- prepare to send EOP
vtx.c_bits := "000000101"; -- EOP = P101
else
-- prepare to send EEP
vtx.c_bits := "000000011"; -- EEP = P110
end if;
else
-- prepare to send data char
vtx.c_bits := rtx.b_token.char & '0';
end if;
end if;
-- Stage D: Prepare to transmit FCT, ESC, or the stuff from stage C.
if rtx.c_esc = '1' then
-- prepare to send ESC
vtx.d_bits := "000000111"; -- ESC = P111
vtx.d_cnt4 := '1'; -- 3 bits + implicit parity bit
vtx.d_cnt10 := '0';
elsif rtx.c_fct = '1' then
-- prepare to send FCT
vtx.d_bits := "000000001"; -- FCT = P100
vtx.d_cnt4 := '1'; -- 3 bits + implicit parity bit
vtx.d_cnt10 := '0';
else
-- send the stuff from stage C.
vtx.d_bits := rtx.c_bits;
vtx.d_cnt4 := rtx.c_bits(0);
vtx.d_cnt10 := not rtx.c_bits(0);
end if;
-- Stage E: Shift register.
if rtx.txclken = '1' then
if rtx.e_count(0) = '1' then
-- reload shift register; output parity bit
vtx.e_valid := '1';
vtx.e_shift(vtx.e_shift'high downto 1) := rtx.d_bits;
vtx.e_shift(0) := not (rtx.e_parity xor rtx.d_bits(0));
vtx.e_count := rtx.d_cnt10 & "00000" & rtx.d_cnt4 & "000";
vtx.e_parity := rtx.d_bits(0);
else
-- shift bits to output; update parity bit
vtx.e_shift := '0' & rtx.e_shift(rtx.e_shift'high downto 1);
vtx.e_count := '0' & rtx.e_count(rtx.e_count'high downto 1);
vtx.e_parity := rtx.e_parity xor rtx.e_shift(1);
end if;
end if;
-- Stage F: Data/strobe encoding.
if rtx.txclken = '1' then
if rtx.e_valid = '1' then
-- output next data/strobe bits
vtx.f_spwdo := rtx.e_shift(0);
vtx.f_spwso := not (rtx.e_shift(0) xor rtx.f_spwdo xor rtx.f_spwso);
else
-- gentle reset of spacewire signals
vtx.f_spwdo := rtx.f_spwdo and rtx.f_spwso;
vtx.f_spwso := '0';
end if;
end if;
-- Generate tx clock enable
-- An 8-bit counter decrements on every clock. A txclken pulse is
-- produced 2 cycles after the counter reaches value 2. Counter reload
-- values of 0 and 1 are handled as special cases.
-- count down in blocks of two bits
vtx.txclkcnt(1 downto 0) := std_logic_vector(unsigned(rtx.txclkcnt(1 downto 0)) - 1);
vtx.txclkcnt(3 downto 2) := std_logic_vector(unsigned(rtx.txclkcnt(3 downto 2)) - unsigned(rtx.txclkcy(0 downto 0)));
vtx.txclkcnt(5 downto 4) := std_logic_vector(unsigned(rtx.txclkcnt(5 downto 4)) - unsigned(rtx.txclkcy(1 downto 1)));
vtx.txclkcnt(7 downto 6) := std_logic_vector(unsigned(rtx.txclkcnt(7 downto 6)) - unsigned(rtx.txclkcy(2 downto 2)));
-- propagate carry in blocks of two bits
vtx.txclkcy(0) := bool_to_logic(rtx.txclkcnt(1 downto 0) = "00");
vtx.txclkcy(1) := rtx.txclkcy(0) and bool_to_logic(rtx.txclkcnt(3 downto 2) = "00");
vtx.txclkcy(2) := rtx.txclkcy(1) and bool_to_logic(rtx.txclkcnt(5 downto 4) = "00");
-- detect value 2 in counter
vtx.txclkdone(0) := bool_to_logic(rtx.txclkcnt(3 downto 0) = "0010");
vtx.txclkdone(1) := bool_to_logic(rtx.txclkcnt(7 downto 4) = "0000");
-- trigger txclken
vtx.txclken := (rtx.txclkdone(0) and rtx.txclkdone(1)) or rtx.txclkpre;
vtx.txclkpre := (not rtx.txdivnorm) and ((not rtx.txclkpre) or (not rtx.txclkdiv(0)));
-- reload counter
if rtx.txclken = '1' then
vtx.txclkcnt := rtx.txclkdiv;
vtx.txclkcy := "000";
vtx.txclkdone := "00";
end if;
-- Synchronize txclkdiv
if synctx.txdivsafe = '1' then
vtx.txclkdiv := r.txdivreg;
vtx.txdivnorm := r.txdivnorm;
end if;
-- Transmitter disabled.
if synctx.txen = '0' then
vtx.txflip0 := '0';
vtx.txflip1 := '0';
vtx.b_update := '0';
vtx.b_mux := '0';
vtx.b_valid := '0';
vtx.c_update := '0';
vtx.c_busy := '1';
vtx.c_esc := '1'; -- need to send 2nd part of NULL
vtx.c_fct := '1';
vtx.d_bits := "000000111"; -- ESC = P111
vtx.d_cnt4 := '1'; -- 3 bits + implicit parity bit
vtx.d_cnt10 := '0';
vtx.e_valid := '0';
vtx.e_parity := '0';
vtx.e_count := (0 => '1', others => '0');
end if;
-- Reset.
if synctx.rstn = '0' then
vtx.f_spwdo := '0';
vtx.f_spwso := '0';
vtx.txclken := '0';
vtx.txclkpre := '1';
vtx.txclkcnt := (others => '0');
vtx.txclkdiv := (others => '0');
vtx.txdivnorm := '0';
end if;
-- ---- SYSTEM CLOCK DOMAIN ----
-- Hold divcnt and txen for use by txclk domain.
v.txdivtmp := std_logic_vector(unsigned(r.txdivtmp) - 1);
if r.txdivtmp = "00" then
if r.txdivsafe = '0' then
-- Latch the current value of divcnt and txen.
v.txdivsafe := '1';
v.txdivtmp := "01";
v.txdivreg := divcnt;
if unsigned(divcnt(divcnt'high downto 1)) = 0 then
v.txdivnorm := '0';
else
v.txdivnorm := '1';
end if;
v.txenreg := xmiti.txen;
else
-- Drop the txdivsafe flag but keep latched values.
v.txdivsafe := '0';
end if;
end if;
-- Pass falling edge of txen signal as soon as possible.
if xmiti.txen = '0' then
v.txenreg := '0';
end if;
-- Store requests for FCT transmission.
if xmiti.fct_in = '1' and r.allow_fct = '1' then
v.pend_fct := '1';
end if;
if xmiti.txen = '0' then
-- Transmitter disabled; reset state.
v.sysflip0 := '0';
v.sysflip1 := '0';
v.tokmux := '0';
v.pend_fct := '0';
v.pend_char := '0';
v.pend_tick := '0';
v.allow_fct := '0';
v.allow_char := '0';
v.sent_fct := '0';
else
-- Determine if a new token is needed.
if r.tokmux = '0' then
if r.sysflip0 = syncsys.txflip0 then
v_needtoken := '1';
end if;
else
if r.sysflip1 = syncsys.txflip1 then
v_needtoken := '1';
end if;
end if;
-- Prepare new token.
if r.allow_char = '1' and r.pend_tick = '1' then
-- prepare to send time code
v_token.tick := '1';
v_token.fct := '0';
v_token.fctpiggy := '0';
v_token.flag := '0';
v_token.char := r.pend_time;
v_havetoken := '1';
if v_needtoken = '1' then
v.pend_tick := '0';
end if;
else
if r.allow_fct = '1' and (xmiti.fct_in = '1' or r.pend_fct = '1') then
-- prepare to send FCT
v_token.fct := '1';
v_havetoken := '1';
if v_needtoken = '1' then
v.pend_fct := '0';
v.sent_fct := '1';
end if;
end if;
if r.allow_char = '1' and r.pend_char = '1' then
-- prepare to send N-Char
-- Note: it is possible to send an FCT and an N-Char
-- together by enabling the fctpiggy flag.
v_token.fctpiggy := v_token.fct;
v_token.flag := r.pend_data(8);
v_token.char := r.pend_data(7 downto 0);
v_havetoken := '1';
if v_needtoken = '1' then
v.pend_char := '0';
end if;
end if;
end if;
-- Put new token in slot.
if v_havetoken = '1' then
if r.tokmux = '0' then
if r.sysflip0 = syncsys.txflip0 then
v.sysflip0 := not r.sysflip0;
v.token0 := v_token;
v.tokmux := '1';
end if;
else
if r.sysflip1 = syncsys.txflip1 then
v.sysflip1 := not r.sysflip1;
v.token1 := v_token;
v.tokmux := '0';
end if;
end if;
end if;
-- Determine whether we are allowed to send FCTs and characters
v.allow_fct := not xmiti.stnull;
v.allow_char := (not xmiti.stnull) and (not xmiti.stfct) and r.sent_fct;
-- Store request for data transmission.
if xmiti.txwrite = '1' and r.allow_char = '1' and r.pend_char = '0' then
v.pend_char := '1';
v.pend_data := xmiti.txflag & xmiti.txdata;
end if;
-- Store requests for time tick transmission.
if xmiti.tick_in = '1' then
v.pend_tick := '1';
v.pend_time := xmiti.ctrl_in & xmiti.time_in;
end if;
end if;
-- Synchronous reset of system clock domain.
if rst = '1' then
v := regs_reset;
end if;
-- Drive outputs.
-- Note: the outputs are combinatorially dependent on certain inputs.
-- Set fctack high if (FCT requested) and (FCTs allowed) AND
-- (no FCT pending)
xmito.fctack <= xmiti.fct_in and xmiti.txen and r.allow_fct and
(not r.pend_fct);
-- Set txrdy high if (character requested) AND (characters allowed) AND
-- (no character pending)
xmito.txack <= xmiti.txwrite and xmiti.txen and r.allow_char and
(not r.pend_char);
-- Update registers.
rin <= v;
rtxin <= vtx;
end process;
-- Synchronous process in txclk domain
process (txclk) is
begin
if rising_edge(txclk) then
-- drive spacewire output signals
s_spwdo <= rtx.f_spwdo;
s_spwso <= rtx.f_spwso;
-- update registers
rtx <= rtxin;
end if;
end process;
-- Synchronous process in system clock domain
process (clk) is
begin
if rising_edge(clk) then
-- update registers
r <= rin;
end if;
end process;
end architecture spwxmit_fast_arch;
| gpl-3.0 | 27cf2d7eb9dd4a2e904596483a839400 | 0.54715 | 3.70378 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/arith/arith.vhd | 1 | 4,818 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: arith
-- File: arith.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: Declaration of mul/div components
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package arith is
type div32_in_type is record
y : std_logic_vector(32 downto 0); -- Y (MSB divident)
op1 : std_logic_vector(32 downto 0); -- operand 1 (LSB divident)
op2 : std_logic_vector(32 downto 0); -- operand 2 (divisor)
flush : std_logic;
signed : std_logic;
start : std_logic;
end record;
type div32_out_type is record
ready : std_logic;
nready : std_logic;
icc : std_logic_vector(3 downto 0); -- ICC
result : std_logic_vector(31 downto 0); -- div result
end record;
type mul32_in_type is record
op1 : std_logic_vector(32 downto 0); -- operand 1
op2 : std_logic_vector(32 downto 0); -- operand 2
flush : std_logic;
signed : std_logic;
start : std_logic;
mac : std_logic;
acc : std_logic_vector(39 downto 0);
--y : std_logic_vector(7 downto 0); -- Y (MSB MAC register)
--asr18 : std_logic_vector(31 downto 0); -- LSB MAC register
end record;
type mul32_out_type is record
ready : std_logic;
nready : std_logic;
icc : std_logic_vector(3 downto 0); -- ICC
result : std_logic_vector(63 downto 0); -- mul result
end record;
component div32
generic (scantest : integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
holdn : in std_ulogic;
divi : in div32_in_type;
divo : out div32_out_type;
testen : in std_ulogic := '0';
testrst : in std_ulogic := '1'
);
end component;
component mul32
generic (
tech : integer := 0;
multype : integer := 0;
pipe : integer := 0;
mac : integer := 0;
arch : integer range 0 to 3 := 0;
scantest: integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
holdn : in std_ulogic;
muli : in mul32_in_type;
mulo : out mul32_out_type;
testen : in std_ulogic := '0';
testrst : in std_ulogic := '1'
);
end component;
function smult ( a, b : in std_logic_vector) return std_logic_vector;
function umult ( a, b : in std_logic_vector) return std_logic_vector;
end;
package body arith is
function smult ( a, b : in std_logic_vector) return std_logic_vector is
variable sa : signed (a'length-1 downto 0);
variable sb : signed (b'length-1 downto 0);
variable sc : signed ((a'length + b'length) -1 downto 0);
variable res : std_logic_vector ((a'length + b'length) -1 downto 0);
begin
sa := signed(a); sb := signed(b);
-- pragma translate_off
if is_x(a) or is_x(b) then
sc := (others => 'X');
else
-- pragma translate_on
sc := sa * sb;
-- pragma translate_off
end if;
-- pragma translate_on
res := std_logic_vector(sc);
return(res);
end;
function umult ( a, b : in std_logic_vector) return std_logic_vector is
variable sa : unsigned (a'length-1 downto 0);
variable sb : unsigned (b'length-1 downto 0);
variable sc : unsigned ((a'length + b'length) -1 downto 0);
variable res : std_logic_vector ((a'length + b'length) -1 downto 0);
begin
sa := unsigned(a); sb := unsigned(b);
-- pragma translate_off
if is_x(a) or is_x(b) then
sc := (others => 'X');
else
-- pragma translate_on
sc := sa * sb;
-- pragma translate_off
end if;
-- pragma translate_on
res := std_logic_vector(sc);
return(res);
end;
end;
| gpl-3.0 | 69d7b10cb99cb7b7db8ca6448bc3295b | 0.58406 | 3.50655 | false | false | false | false |
pwsoft/fpga_examples | rtl/general/gen_button.vhd | 1 | 2,655 | -- -----------------------------------------------------------------------
--
-- Syntiac VHDL support files.
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2009 by Peter Wendrich ([email protected])
-- http://www.syntiac.com
--
-- This source file is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- -----------------------------------------------------------------------
--
-- Button debounce routine with detection of short and long presses.
--
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
-- -----------------------------------------------------------------------
entity gen_button is
generic (
pressed_polarity : std_logic := '1';
short_press_ms : integer := 50;
long_press_ms : integer := 700
);
port (
clk : in std_logic;
ena_1khz : in std_logic;
button : in std_logic;
keyboard : in std_logic;
short_trig : out std_logic;
long_trig : out std_logic
);
end entity;
-- -----------------------------------------------------------------------
architecture rtl of gen_button is
signal cnt : integer range 0 to long_press_ms;
signal dly1 : std_logic;
signal dly2 : std_logic;
signal short_reg : std_logic := '0';
signal long_reg : std_logic := '0';
begin
assert(short_press_ms < long_press_ms);
short_trig <= short_reg;
long_trig <= long_reg;
-- Syncronise button to clock (double registered for async inputs)
process(clk)
begin
if rising_edge(clk) then
dly1 <= button;
dly2 <= dly1;
end if;
end process;
process(clk)
begin
if rising_edge(clk) then
short_reg <= '0';
long_reg <= '0';
if (keyboard = '1') or (dly2 = pressed_polarity) then
if ena_1khz = '1'then
if cnt /= long_press_ms then
cnt <= cnt + 1;
end if;
end if;
else
if cnt = long_press_ms then
long_reg <= '1';
elsif cnt >= short_press_ms then
short_reg <= '1';
end if;
cnt <= 0;
end if;
end if;
end process;
end architecture;
| lgpl-2.1 | 926be13e3d6bf568772e10d335b9795b | 0.556309 | 3.662069 | false | false | false | false |
hoglet67/CoPro6502 | src/T80/T80_Pack.vhd | 1 | 9,109 | -- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible microprocessor core
--
-- Version : 0242
--
-- Copyright (c) 2001-2002 Daniel Wallner ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
library IEEE;
use IEEE.std_logic_1164.all;
package T80_Pack is
constant aNone : std_logic_vector(2 downto 0) := "111";
constant aBC : std_logic_vector(2 downto 0) := "000";
constant aDE : std_logic_vector(2 downto 0) := "001";
constant aXY : std_logic_vector(2 downto 0) := "010";
constant aIOA : std_logic_vector(2 downto 0) := "100";
constant aSP : std_logic_vector(2 downto 0) := "101";
constant aZI : std_logic_vector(2 downto 0) := "110";
component T80
generic(
Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
RESET_n : in std_logic;
CLK_n : in std_logic;
CEN : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
IORQ : out std_logic;
NoRead : out std_logic;
Write : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
DInst : in std_logic_vector(7 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0);
MC : out std_logic_vector(2 downto 0);
TS : out std_logic_vector(2 downto 0);
IntCycle_n : out std_logic;
IntE : out std_logic;
Stop : out std_logic
);
end component;
component T80_Reg
port(
Clk : in std_logic;
CEN : in std_logic;
WEH : in std_logic;
WEL : in std_logic;
AddrA : in std_logic_vector(2 downto 0);
AddrB : in std_logic_vector(2 downto 0);
AddrC : in std_logic_vector(2 downto 0);
DIH : in std_logic_vector(7 downto 0);
DIL : in std_logic_vector(7 downto 0);
DOAH : out std_logic_vector(7 downto 0);
DOAL : out std_logic_vector(7 downto 0);
DOBH : out std_logic_vector(7 downto 0);
DOBL : out std_logic_vector(7 downto 0);
DOCH : out std_logic_vector(7 downto 0);
DOCL : out std_logic_vector(7 downto 0)
);
end component;
component T80_MCode
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
IR : in std_logic_vector(7 downto 0);
ISet : in std_logic_vector(1 downto 0);
MCycle : in std_logic_vector(2 downto 0);
F : in std_logic_vector(7 downto 0);
NMICycle : in std_logic;
IntCycle : in std_logic;
XY_State : in std_logic_vector(1 downto 0);
MCycles : out std_logic_vector(2 downto 0);
TStates : out std_logic_vector(2 downto 0);
Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
Inc_PC : out std_logic;
Inc_WZ : out std_logic;
IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc
Read_To_Reg : out std_logic;
Read_To_Acc : out std_logic;
Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
ALU_Op : out std_logic_vector(3 downto 0);
-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
Save_ALU : out std_logic;
PreserveC : out std_logic;
Arith16 : out std_logic;
Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
IORQ : out std_logic;
Jump : out std_logic;
JumpE : out std_logic;
JumpXY : out std_logic;
Call : out std_logic;
RstP : out std_logic;
LDZ : out std_logic;
LDW : out std_logic;
LDSPHL : out std_logic;
Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
ExchangeDH : out std_logic;
ExchangeRp : out std_logic;
ExchangeAF : out std_logic;
ExchangeRS : out std_logic;
I_DJNZ : out std_logic;
I_CPL : out std_logic;
I_CCF : out std_logic;
I_SCF : out std_logic;
I_RETN : out std_logic;
I_BT : out std_logic;
I_BC : out std_logic;
I_BTR : out std_logic;
I_RLD : out std_logic;
I_RRD : out std_logic;
I_INRC : out std_logic;
SetDI : out std_logic;
SetEI : out std_logic;
IMode : out std_logic_vector(1 downto 0);
Halt : out std_logic;
NoRead : out std_logic;
Write : out std_logic;
XYbit_undoc : out std_logic
);
end component;
component T80_ALU
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
Arith16 : in std_logic;
Z16 : in std_logic;
ALU_Op : in std_logic_vector(3 downto 0);
IR : in std_logic_vector(5 downto 0);
ISet : in std_logic_vector(1 downto 0);
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
F_In : in std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0);
F_Out : out std_logic_vector(7 downto 0)
);
end component;
end;
| gpl-3.0 | 440b05741ab7268ee614fcfe97a44726 | 0.532111 | 3.424436 | false | false | false | false |
ARC-Lab-UF/UAA | src/add_wrapper.vhd | 1 | 4,999 | -- Copyright (c) 2015 University of Florida
--
-- This file is part of uaa.
--
-- uaa is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- uaa is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with uaa. If not, see <http://www.gnu.org/licenses/>.
-- Greg Stitt
-- University of Florida
-- Description:
-- The add_wrapper entity wraps the add_flt entity to implement a pipelined
-- floating-point adder that specifies when the output is valid based on the
-- pipeline latency of the specified adder core, while also outputting the
-- number of adds in the pipeline.
-- Used entities:
-- add_flt, delay
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.flt_pkg.all;
use work.math_custom.all;
-------------------------------------------------------------------------------
-- Generics Description
-- width : The width of the adder input/output. This should match
-- the precision of the adder (e.g. single precision=32,
-- double precision=64) (required)
-- core_name : A string specifying the optimization strategy, or just
-- a name for the adder core. This string should be one of
-- the possible user-defined values defined in flt_pkg
-- for any corresponding adder cores.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Port Description:
-- clk : clock input
-- rst : reset input (active high)
-- en : enable input (active high), stalls the pipeline when '0'
-- input1 : the first input to the add
-- input2 : the second input to the add
-- output : the sum
-- valid_in : user should assert when input is valid (active high)
-- valid_out : asserted by entity when output is valid after the adder core's
-- pipeline latency (active high)
-- count : the number of pending adds within the adder core's pipeline
-------------------------------------------------------------------------------
entity add_wrapper is
generic (
width : positive;
core_name : string := "");
port (
clk : in std_logic;
rst : in std_logic;
en : in std_logic;
input1 : in std_logic_vector(width-1 downto 0);
input2 : in std_logic_vector(width-1 downto 0);
output : out std_logic_vector(width-1 downto 0);
valid_in : in std_logic;
valid_out : out std_logic;
count : out std_logic_vector(bitsNeeded(add_flt_latency(core_name))-1 downto 0)
);
end add_wrapper;
architecture RTL of add_wrapper is
constant COUNT_WIDTH : positive := bitsNeeded(add_flt_latency(core_name));
signal count_s : unsigned(COUNT_WIDTH-1 downto 0);
signal valid_out_s : std_logic;
begin
-- track the number of adds in the pipeline
process(clk, rst)
begin
if (rst = '1') then
count_s <= to_unsigned(0, COUNT_WIDTH);
elsif (rising_edge(clk)) then
if (en = '1') then
if (en = '1' and valid_in = '1' and valid_out_s = '0') then
-- the number of pending adds increases when a valid
-- input enters and there isn't an output
count_s <= count_s + 1;
elsif (en = '1' and valid_in = '0' and valid_out_s = '1') then
-- the number of pending adds decreases when output leaves
-- with no valid input
count_s <= count_s - 1;
end if;
end if;
end if;
end process;
count <= std_logic_vector(count_s);
-- instantiate the floating-point adder
U_ADD_FLT : entity work.add_flt
generic map (core_name => core_name)
port map (clk => clk,
en => en,
input1 => input1,
input2 => input2,
output => output);
-- delay enable signal (valid_in) to determine when adder output is valid
U_DELAY : entity work.delay
generic map (cycles => add_flt_latency(core_name),
width => 1,
init => "0")
port map (clk => clk,
rst => rst,
en => en,
input(0) => valid_in,
output(0) => valid_out_s);
valid_out <= valid_out_s;
end RTL;
| gpl-3.0 | 04f41f33d3ad735f7ff9e98288d87d86 | 0.544109 | 4.225697 | false | false | false | false |
yishinli/emc2 | src/hal/drivers/mesa-hostmot2/firmware/src/boutreg.vhd | 1 | 4,024 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
-- http://www.mesanet.com
--
-- This program is is licensed under a disjunctive dual license giving you
-- the choice of one of the two following sets of free software/open source
-- licensing terms:
--
-- * GNU General Public License (GPL), version 2.0 or later
-- * 3-clause BSD License
--
--
-- The GNU GPL License:
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
--
--
-- The 3-clause BSD License:
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- * Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- * Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- * Neither the name of Mesa Electronics nor the names of its
-- contributors may be used to endorse or promote products
-- derived from this software without specific prior written
-- permission.
--
--
-- Disclaimer:
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
entity boutreg is -- basic output register
generic (
size : integer;
buswidth : integer;
invert : boolean
);
port (
clk : in std_logic;
ibus : in std_logic_vector(buswidth-1 downto 0);
obus : out std_logic_vector(buswidth-1 downto 0);
load : in std_logic;
read : in std_logic;
clear : in std_logic;
dout : out std_logic_vector(size -1 downto 0)
);
end boutreg;
architecture Behavioral of boutreg is
signal oreg : std_logic_vector(size -1 downto 0);
begin
a_basic_out_reg: process (clk,read,oreg)
begin
if clk'event and clk = '1' then
if load = '1' then
oreg <= ibus (size -1 downto 0);
end if;
if clear = '1' then
oreg <= (others => '0');
end if;
end if; -- clk
obus <= (others => 'Z');
if read = '1' then
obus(size -1 downto 0) <= oreg; -- port data is right justified
obus(buswidth -1 downto size) <= (others => '0');
end if;
if invert then
dout <= not oreg;
else
dout <= oreg;
end if;
end process;
end Behavioral;
| lgpl-2.1 | 9e6b8c89995674900c128798204cd98f | 0.67172 | 3.832381 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/greth/adapters/word_aligner.vhd | 1 | 3,947 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: word_aligner
-- File: word_aligner.vhd
-- Author: Pascal Trotta
-- Description: generic SGMII comma detector and word aligner for serdes
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity word_aligner is
generic(
comma : std_logic_vector(9 downto 3) := "0011111");
port(
clk : in std_logic; -- rx clock
rstn : in std_logic; -- synchronous reset
rx_in : in std_logic_vector(9 downto 0); -- Data in
rx_out : out std_logic_vector(9 downto 0)); -- Data out
end entity;
architecture word_arch of word_aligner is
type state_type is (idle, fill_second, find_align, fix_align);
type mux_sel is (S0,S1,S2,S3,S4,S5,S6,S7,S8,S9);
type reg is record
alignment_sel : mux_sel;
q0 : std_logic_vector(9 downto 0);
q1 : std_logic_vector(9 downto 0);
end record;
signal regs, regin : reg;
begin
combp: process(regs, rx_in)
variable regv : reg;
variable q1q0 : std_logic_vector(19 downto 0);
begin
regv := regs;
q1q0 := regv.q1 & regv.q0;
if q1q0(18 downto 12) = comma then
regv.alignment_sel:=S0;
elsif q1q0(17 downto 11) = comma then
regv.alignment_sel:=S1;
elsif q1q0(16 downto 10) = comma then
regv.alignment_sel:=S2;
elsif q1q0(15 downto 9) = comma then
regv.alignment_sel:=S3;
elsif q1q0(14 downto 8) = comma then
regv.alignment_sel:=S4;
elsif q1q0(13 downto 7) = comma then
regv.alignment_sel:=S5;
elsif q1q0(12 downto 6) = comma then
regv.alignment_sel:=S6;
elsif q1q0(11 downto 5) = comma then
regv.alignment_sel:=S7;
elsif q1q0(10 downto 4) = comma then
regv.alignment_sel:=S8;
elsif q1q0(9 downto 3) = comma then
regv.alignment_sel:=S9;
end if;
case regs.alignment_sel is
when S0 =>
rx_out <= q1q0(18 downto 9);
when S1 =>
rx_out <= q1q0(17 downto 8);
when S2 =>
rx_out <= q1q0(16 downto 7);
when S3 =>
rx_out <= q1q0(15 downto 6);
when S4 =>
rx_out <= q1q0(14 downto 5);
when S5 =>
rx_out <= q1q0(13 downto 4);
when S6 =>
rx_out <= q1q0(12 downto 3);
when S7 =>
rx_out <= q1q0(11 downto 2);
when S8 =>
rx_out <= q1q0(10 downto 1);
when others => --S9 and other states
rx_out <= q1q0(9 downto 0);
end case;
regv.q1 := regv.q0;
regv.q0 := rx_in;
regin <= regv;
end process;
regp: process(clk)
begin
if rising_edge(clk) then
regs <= regin;
if rstn = '0' then
regs.alignment_sel <= S0;
regs.q0 <= (others =>'0');
regs.q1 <= (others =>'0');
end if;
end if;
end process;
end architecture;
| gpl-3.0 | ab2f94577b5a71bfca6f36160f2211f3 | 0.576894 | 3.444154 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/techmap/saed32/memory_saed32.vhd | 1 | 5,578 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: various
-- File: memory_saed32.vhd
-- Author: Fredrik Ringhage - Aeroflex Gaisler AB
-- Description: Memory generators for SAED32
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library saed32;
use saed32.SRAM1RW64x32;
use saed32.SRAM1RW128x48;
use saed32.SRAM1RW128x48;
-- pragma translate_on
entity saed32_syncram is
generic ( abits : integer := 10; dbits : integer := 8);
port (
clk : in std_ulogic;
address : in std_logic_vector(abits -1 downto 0);
datain : in std_logic_vector(dbits -1 downto 0);
dataout : out std_logic_vector(dbits -1 downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end;
architecture rtl of saed32_syncram is
component SRAM1RW64x32 is
port (
A : in std_logic_vector( 5 downto 0 );
CE : in std_logic;
WEB : in std_logic;
OEB : in std_logic;
CSB : in std_logic;
I : in std_logic_vector( 31 downto 0 );
O : out std_logic_vector( 31 downto 0 )
);
end component;
component SRAM1RW128x48 is
port (
A : in std_logic_vector( 6 downto 0 );
CE : in std_logic;
WEB : in std_logic;
OEB : in std_logic;
CSB : in std_logic;
I : in std_logic_vector( 47 downto 0 );
O : out std_logic_vector( 47 downto 0 )
);
end component;
component SRAM1RW1024x8 is
port (
A : in std_logic_vector( 9 downto 0 );
CE : in std_logic;
WEB : in std_logic;
OEB : in std_logic;
CSB : in std_logic;
I : in std_logic_vector( 7 downto 0 );
O : out std_logic_vector( 7 downto 0 )
);
end component;
signal d, q, gnd : std_logic_vector(48 downto 0);
signal a : std_logic_vector(17 downto 0);
signal vcc, csn, wen : std_ulogic;
--constant synopsys_bug : std_logic_vector(31 downto 0) := (others => '0');
begin
csn <= not enable; wen <= not write;
gnd <= (others => '0'); vcc <= '1';
a(17 downto abits) <= (others => '0');
d(48 downto dbits) <= (others => '0');
a(abits -1 downto 0) <= address;
d(dbits -1 downto 0) <= datain(dbits -1 downto 0);
a6 : if (abits <= 6) generate
id0 : SRAM1RW64x32 port map (A => a(5 downto 0), CE => clk, WEB => wen, OEB => gnd(0), CSB => csn, I => d(31 downto 0), O => q(31 downto 0));
end generate;
a7 : if (abits = 7) generate
id0 : SRAM1RW128x48 port map (A => a(6 downto 0), CE => clk, WEB => wen, OEB => gnd(0), CSB => csn, I => d(47 downto 0), O => q(47 downto 0));
end generate;
a10 : if (abits >= 8 and abits <= 10) generate
x : for i in 0 to ((dbits-1)/8) generate
id0 : SRAM1RW1024x8 port map (A => a(9 downto 0), CE => clk, WEB => wen, OEB => gnd(0), CSB => csn, I => d(((i+1)*8)-1 downto i*8), O => q(((i+1)*8)-1 downto i*8));
end generate;
end generate;
dataout <= q(dbits -1 downto 0);
-- pragma translate_off
a_to_high : if (abits > 10) or (dbits > 32) generate
x : process
begin
assert false
report "Unsupported memory size (saed32)"
severity failure;
wait;
end process;
end generate;
-- pragma translate_on
end;
library ieee;
use ieee.std_logic_1164.all;
entity saed32_syncram_dp is
generic ( abits : integer := 6; dbits : integer := 8 );
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic
);
end;
architecture rtl of saed32_syncram_dp is
begin
end;
library ieee;
use ieee.std_logic_1164.all;
entity saed32_syncram_2p is
generic ( abits : integer := 8; dbits : integer := 32; sepclk : integer := 0);
port (
rclk : in std_ulogic;
rena : in std_ulogic;
raddr : in std_logic_vector (abits -1 downto 0);
dout : out std_logic_vector (dbits -1 downto 0);
wclk : in std_ulogic;
waddr : in std_logic_vector (abits -1 downto 0);
din : in std_logic_vector (dbits -1 downto 0);
write : in std_ulogic);
end;
architecture rtl of saed32_syncram_2p is
begin
end;
| gpl-3.0 | 9d6b9abc7285fa41fe979e317fbad32a | 0.596271 | 3.294743 | false | false | false | false |
hoglet67/CoPro6502 | src/ROM/tuberom_z80.vhd | 1 | 172,742 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tuberom_z80 is
port (
CLK : in std_logic;
ADDR : in std_logic_vector(11 downto 0);
DATA : out std_logic_vector(7 downto 0)
);
end;
architecture RTL of tuberom_z80 is
signal rom_addr : std_logic_vector(11 downto 0);
begin
p_addr : process(ADDR)
begin
rom_addr <= (others => '0');
rom_addr(11 downto 0) <= ADDR;
end process;
p_rom : process
begin
wait until rising_edge(CLK);
DATA <= (others => '0');
case rom_addr is
when x"000" => DATA <= x"F3";
when x"001" => DATA <= x"11";
when x"002" => DATA <= x"00";
when x"003" => DATA <= x"F0";
when x"004" => DATA <= x"21";
when x"005" => DATA <= x"00";
when x"006" => DATA <= x"00";
when x"007" => DATA <= x"01";
when x"008" => DATA <= x"00";
when x"009" => DATA <= x"10";
when x"00A" => DATA <= x"ED";
when x"00B" => DATA <= x"B0";
when x"00C" => DATA <= x"C3";
when x"00D" => DATA <= x"80";
when x"00E" => DATA <= x"F2";
when x"00F" => DATA <= x"43";
when x"010" => DATA <= x"6F";
when x"011" => DATA <= x"70";
when x"012" => DATA <= x"79";
when x"013" => DATA <= x"72";
when x"014" => DATA <= x"69";
when x"015" => DATA <= x"67";
when x"016" => DATA <= x"68";
when x"017" => DATA <= x"74";
when x"018" => DATA <= x"20";
when x"019" => DATA <= x"41";
when x"01A" => DATA <= x"63";
when x"01B" => DATA <= x"6F";
when x"01C" => DATA <= x"72";
when x"01D" => DATA <= x"6E";
when x"01E" => DATA <= x"20";
when x"01F" => DATA <= x"43";
when x"020" => DATA <= x"6F";
when x"021" => DATA <= x"6D";
when x"022" => DATA <= x"70";
when x"023" => DATA <= x"75";
when x"024" => DATA <= x"74";
when x"025" => DATA <= x"65";
when x"026" => DATA <= x"72";
when x"027" => DATA <= x"73";
when x"028" => DATA <= x"20";
when x"029" => DATA <= x"4C";
when x"02A" => DATA <= x"74";
when x"02B" => DATA <= x"64";
when x"02C" => DATA <= x"2E";
when x"02D" => DATA <= x"20";
when x"02E" => DATA <= x"31";
when x"02F" => DATA <= x"39";
when x"030" => DATA <= x"38";
when x"031" => DATA <= x"34";
when x"032" => DATA <= x"0D";
when x"033" => DATA <= x"48";
when x"034" => DATA <= x"3A";
when x"035" => DATA <= x"7D";
when x"036" => DATA <= x"3C";
when x"037" => DATA <= x"B7";
when x"038" => DATA <= x"C4";
when x"039" => DATA <= x"C0";
when x"03A" => DATA <= x"2C";
when x"03B" => DATA <= x"3A";
when x"03C" => DATA <= x"22";
when x"03D" => DATA <= x"3A";
when x"03E" => DATA <= x"B7";
when x"03F" => DATA <= x"C4";
when x"040" => DATA <= x"F1";
when x"041" => DATA <= x"2C";
when x"042" => DATA <= x"F1";
when x"043" => DATA <= x"21";
when x"044" => DATA <= x"1B";
when x"045" => DATA <= x"3A";
when x"046" => DATA <= x"34";
when x"047" => DATA <= x"7E";
when x"048" => DATA <= x"3D";
when x"049" => DATA <= x"C2";
when x"04A" => DATA <= x"AB";
when x"04B" => DATA <= x"2B";
when x"04C" => DATA <= x"21";
when x"04D" => DATA <= x"EC";
when x"04E" => DATA <= x"3B";
when x"04F" => DATA <= x"7E";
when x"050" => DATA <= x"B7";
when x"051" => DATA <= x"C2";
when x"052" => DATA <= x"34";
when x"053" => DATA <= x"2B";
when x"054" => DATA <= x"21";
when x"055" => DATA <= x"4A";
when x"056" => DATA <= x"3B";
when x"057" => DATA <= x"7E";
when x"058" => DATA <= x"B7";
when x"059" => DATA <= x"C2";
when x"05A" => DATA <= x"34";
when x"05B" => DATA <= x"2B";
when x"05C" => DATA <= x"21";
when x"05D" => DATA <= x"58";
when x"05E" => DATA <= x"3D";
when x"05F" => DATA <= x"23";
when x"060" => DATA <= x"01";
when x"061" => DATA <= x"06";
when x"062" => DATA <= x"00";
when x"063" => DATA <= x"11";
when x"064" => DATA <= x"EC";
when x"065" => DATA <= x"3B";
when x"066" => DATA <= x"C3";
when x"067" => DATA <= x"61";
when x"068" => DATA <= x"FC";
when x"069" => DATA <= x"54";
when x"06A" => DATA <= x"68";
when x"06B" => DATA <= x"65";
when x"06C" => DATA <= x"20";
when x"06D" => DATA <= x"42";
when x"06E" => DATA <= x"75";
when x"06F" => DATA <= x"73";
when x"070" => DATA <= x"69";
when x"071" => DATA <= x"6E";
when x"072" => DATA <= x"65";
when x"073" => DATA <= x"73";
when x"074" => DATA <= x"73";
when x"075" => DATA <= x"20";
when x"076" => DATA <= x"53";
when x"077" => DATA <= x"79";
when x"078" => DATA <= x"73";
when x"079" => DATA <= x"74";
when x"07A" => DATA <= x"65";
when x"07B" => DATA <= x"6D";
when x"07C" => DATA <= x"73";
when x"07D" => DATA <= x"20";
when x"07E" => DATA <= x"47";
when x"07F" => DATA <= x"72";
when x"080" => DATA <= x"6F";
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when x"299" => DATA <= x"54";
when x"29A" => DATA <= x"55";
when x"29B" => DATA <= x"42";
when x"29C" => DATA <= x"45";
when x"29D" => DATA <= x"20";
when x"29E" => DATA <= x"5A";
when x"29F" => DATA <= x"38";
when x"2A0" => DATA <= x"30";
when x"2A1" => DATA <= x"20";
when x"2A2" => DATA <= x"36";
when x"2A3" => DATA <= x"34";
when x"2A4" => DATA <= x"4B";
when x"2A5" => DATA <= x"20";
when x"2A6" => DATA <= x"31";
when x"2A7" => DATA <= x"2E";
when x"2A8" => DATA <= x"32";
when x"2A9" => DATA <= x"31";
when x"2AA" => DATA <= x"0D";
when x"2AB" => DATA <= x"0D";
when x"2AC" => DATA <= x"00";
when x"2AD" => DATA <= x"CD";
when x"2AE" => DATA <= x"9A";
when x"2AF" => DATA <= x"F6";
when x"2B0" => DATA <= x"CD";
when x"2B1" => DATA <= x"AE";
when x"2B2" => DATA <= x"F5";
when x"2B3" => DATA <= x"3E";
when x"2B4" => DATA <= x"FD";
when x"2B5" => DATA <= x"21";
when x"2B6" => DATA <= x"00";
when x"2B7" => DATA <= x"FF";
when x"2B8" => DATA <= x"CD";
when x"2B9" => DATA <= x"8E";
when x"2BA" => DATA <= x"F8";
when x"2BB" => DATA <= x"7D";
when x"2BC" => DATA <= x"B7";
when x"2BD" => DATA <= x"CA";
when x"2BE" => DATA <= x"CE";
when x"2BF" => DATA <= x"F2";
when x"2C0" => DATA <= x"3E";
when x"2C1" => DATA <= x"0F";
when x"2C2" => DATA <= x"21";
when x"2C3" => DATA <= x"01";
when x"2C4" => DATA <= x"00";
when x"2C5" => DATA <= x"CD";
when x"2C6" => DATA <= x"8E";
when x"2C7" => DATA <= x"F8";
when x"2C8" => DATA <= x"C3";
when x"2C9" => DATA <= x"EB";
when x"2CA" => DATA <= x"F7";
when x"2CB" => DATA <= x"CD";
when x"2CC" => DATA <= x"E7";
when x"2CD" => DATA <= x"FF";
when x"2CE" => DATA <= x"31";
when x"2CF" => DATA <= x"80";
when x"2D0" => DATA <= x"FF";
when x"2D1" => DATA <= x"3A";
when x"2D2" => DATA <= x"80";
when x"2D3" => DATA <= x"FF";
when x"2D4" => DATA <= x"CB";
when x"2D5" => DATA <= x"7F";
when x"2D6" => DATA <= x"28";
when x"2D7" => DATA <= x"08";
when x"2D8" => DATA <= x"3E";
when x"2D9" => DATA <= x"7E";
when x"2DA" => DATA <= x"21";
when x"2DB" => DATA <= x"00";
when x"2DC" => DATA <= x"00";
when x"2DD" => DATA <= x"CD";
when x"2DE" => DATA <= x"8E";
when x"2DF" => DATA <= x"F8";
when x"2E0" => DATA <= x"3E";
when x"2E1" => DATA <= x"2A";
when x"2E2" => DATA <= x"CD";
when x"2E3" => DATA <= x"71";
when x"2E4" => DATA <= x"F6";
when x"2E5" => DATA <= x"21";
when x"2E6" => DATA <= x"9D";
when x"2E7" => DATA <= x"FC";
when x"2E8" => DATA <= x"AF";
when x"2E9" => DATA <= x"CD";
when x"2EA" => DATA <= x"EF";
when x"2EB" => DATA <= x"F8";
when x"2EC" => DATA <= x"DA";
when x"2ED" => DATA <= x"FA";
when x"2EE" => DATA <= x"F2";
when x"2EF" => DATA <= x"21";
when x"2F0" => DATA <= x"B0";
when x"2F1" => DATA <= x"FC";
when x"2F2" => DATA <= x"CD";
when x"2F3" => DATA <= x"B7";
when x"2F4" => DATA <= x"F6";
when x"2F5" => DATA <= x"18";
when x"2F6" => DATA <= x"D7";
when x"2F7" => DATA <= x"CD";
when x"2F8" => DATA <= x"E7";
when x"2F9" => DATA <= x"FF";
when x"2FA" => DATA <= x"3E";
when x"2FB" => DATA <= x"7E";
when x"2FC" => DATA <= x"CD";
when x"2FD" => DATA <= x"8E";
when x"2FE" => DATA <= x"F8";
when x"2FF" => DATA <= x"FF";
when x"300" => DATA <= x"11";
when x"301" => DATA <= x"45";
when x"302" => DATA <= x"73";
when x"303" => DATA <= x"63";
when x"304" => DATA <= x"61";
when x"305" => DATA <= x"70";
when x"306" => DATA <= x"65";
when x"307" => DATA <= x"00";
when x"308" => DATA <= x"13";
when x"309" => DATA <= x"1A";
when x"30A" => DATA <= x"E6";
when x"30B" => DATA <= x"DF";
when x"30C" => DATA <= x"FE";
when x"30D" => DATA <= x"4F";
when x"30E" => DATA <= x"C2";
when x"30F" => DATA <= x"CC";
when x"310" => DATA <= x"F7";
when x"311" => DATA <= x"CD";
when x"312" => DATA <= x"76";
when x"313" => DATA <= x"F8";
when x"314" => DATA <= x"06";
when x"315" => DATA <= x"00";
when x"316" => DATA <= x"CD";
when x"317" => DATA <= x"39";
when x"318" => DATA <= x"F4";
when x"319" => DATA <= x"CD";
when x"31A" => DATA <= x"77";
when x"31B" => DATA <= x"F8";
when x"31C" => DATA <= x"FE";
when x"31D" => DATA <= x"0D";
when x"31E" => DATA <= x"C2";
when x"31F" => DATA <= x"CC";
when x"320" => DATA <= x"F7";
when x"321" => DATA <= x"3A";
when x"322" => DATA <= x"AA";
when x"323" => DATA <= x"FC";
when x"324" => DATA <= x"32";
when x"325" => DATA <= x"A8";
when x"326" => DATA <= x"FC";
when x"327" => DATA <= x"3A";
when x"328" => DATA <= x"AB";
when x"329" => DATA <= x"FC";
when x"32A" => DATA <= x"32";
when x"32B" => DATA <= x"A9";
when x"32C" => DATA <= x"FC";
when x"32D" => DATA <= x"C3";
when x"32E" => DATA <= x"DF";
when x"32F" => DATA <= x"F7";
when x"330" => DATA <= x"CD";
when x"331" => DATA <= x"76";
when x"332" => DATA <= x"F8";
when x"333" => DATA <= x"06";
when x"334" => DATA <= x"00";
when x"335" => DATA <= x"CD";
when x"336" => DATA <= x"39";
when x"337" => DATA <= x"F4";
when x"338" => DATA <= x"CD";
when x"339" => DATA <= x"77";
when x"33A" => DATA <= x"F8";
when x"33B" => DATA <= x"FE";
when x"33C" => DATA <= x"0D";
when x"33D" => DATA <= x"C2";
when x"33E" => DATA <= x"CC";
when x"33F" => DATA <= x"F7";
when x"340" => DATA <= x"3E";
when x"341" => DATA <= x"04";
when x"342" => DATA <= x"21";
when x"343" => DATA <= x"01";
when x"344" => DATA <= x"00";
when x"345" => DATA <= x"CD";
when x"346" => DATA <= x"F4";
when x"347" => DATA <= x"FF";
when x"348" => DATA <= x"7D";
when x"349" => DATA <= x"32";
when x"34A" => DATA <= x"AE";
when x"34B" => DATA <= x"FC";
when x"34C" => DATA <= x"2A";
when x"34D" => DATA <= x"AA";
when x"34E" => DATA <= x"FC";
when x"34F" => DATA <= x"CD";
when x"350" => DATA <= x"E7";
when x"351" => DATA <= x"FF";
when x"352" => DATA <= x"CD";
when x"353" => DATA <= x"71";
when x"354" => DATA <= x"F4";
when x"355" => DATA <= x"CD";
when x"356" => DATA <= x"1D";
when x"357" => DATA <= x"F4";
when x"358" => DATA <= x"7E";
when x"359" => DATA <= x"CD";
when x"35A" => DATA <= x"0D";
when x"35B" => DATA <= x"F4";
when x"35C" => DATA <= x"CD";
when x"35D" => DATA <= x"1D";
when x"35E" => DATA <= x"F4";
when x"35F" => DATA <= x"7E";
when x"360" => DATA <= x"CD";
when x"361" => DATA <= x"76";
when x"362" => DATA <= x"F4";
when x"363" => DATA <= x"E5";
when x"364" => DATA <= x"06";
when x"365" => DATA <= x"01";
when x"366" => DATA <= x"21";
when x"367" => DATA <= x"00";
when x"368" => DATA <= x"00";
when x"369" => DATA <= x"CD";
when x"36A" => DATA <= x"E0";
when x"36B" => DATA <= x"FF";
when x"36C" => DATA <= x"CD";
when x"36D" => DATA <= x"40";
when x"36E" => DATA <= x"F4";
when x"36F" => DATA <= x"06";
when x"370" => DATA <= x"00";
when x"371" => DATA <= x"5D";
when x"372" => DATA <= x"E1";
when x"373" => DATA <= x"FE";
when x"374" => DATA <= x"8A";
when x"375" => DATA <= x"28";
when x"376" => DATA <= x"27";
when x"377" => DATA <= x"FE";
when x"378" => DATA <= x"8B";
when x"379" => DATA <= x"28";
when x"37A" => DATA <= x"20";
when x"37B" => DATA <= x"FE";
when x"37C" => DATA <= x"01";
when x"37D" => DATA <= x"C2";
when x"37E" => DATA <= x"A1";
when x"37F" => DATA <= x"F3";
when x"380" => DATA <= x"7E";
when x"381" => DATA <= x"CB";
when x"382" => DATA <= x"27";
when x"383" => DATA <= x"CB";
when x"384" => DATA <= x"27";
when x"385" => DATA <= x"CB";
when x"386" => DATA <= x"27";
when x"387" => DATA <= x"CB";
when x"388" => DATA <= x"27";
when x"389" => DATA <= x"83";
when x"38A" => DATA <= x"77";
when x"38B" => DATA <= x"3E";
when x"38C" => DATA <= x"08";
when x"38D" => DATA <= x"CD";
when x"38E" => DATA <= x"71";
when x"38F" => DATA <= x"F6";
when x"390" => DATA <= x"CD";
when x"391" => DATA <= x"71";
when x"392" => DATA <= x"F6";
when x"393" => DATA <= x"CD";
when x"394" => DATA <= x"71";
when x"395" => DATA <= x"F6";
when x"396" => DATA <= x"CD";
when x"397" => DATA <= x"71";
when x"398" => DATA <= x"F6";
when x"399" => DATA <= x"18";
when x"39A" => DATA <= x"BD";
when x"39B" => DATA <= x"23";
when x"39C" => DATA <= x"18";
when x"39D" => DATA <= x"B1";
when x"39E" => DATA <= x"2B";
when x"39F" => DATA <= x"18";
when x"3A0" => DATA <= x"AE";
when x"3A1" => DATA <= x"3A";
when x"3A2" => DATA <= x"AE";
when x"3A3" => DATA <= x"FC";
when x"3A4" => DATA <= x"6F";
when x"3A5" => DATA <= x"26";
when x"3A6" => DATA <= x"00";
when x"3A7" => DATA <= x"3E";
when x"3A8" => DATA <= x"04";
when x"3A9" => DATA <= x"CD";
when x"3AA" => DATA <= x"F4";
when x"3AB" => DATA <= x"FF";
when x"3AC" => DATA <= x"CD";
when x"3AD" => DATA <= x"E7";
when x"3AE" => DATA <= x"FF";
when x"3AF" => DATA <= x"D1";
when x"3B0" => DATA <= x"C1";
when x"3B1" => DATA <= x"F1";
when x"3B2" => DATA <= x"C9";
when x"3B3" => DATA <= x"CD";
when x"3B4" => DATA <= x"76";
when x"3B5" => DATA <= x"F8";
when x"3B6" => DATA <= x"06";
when x"3B7" => DATA <= x"00";
when x"3B8" => DATA <= x"CD";
when x"3B9" => DATA <= x"39";
when x"3BA" => DATA <= x"F4";
when x"3BB" => DATA <= x"FE";
when x"3BC" => DATA <= x"0D";
when x"3BD" => DATA <= x"28";
when x"3BE" => DATA <= x"10";
when x"3BF" => DATA <= x"FE";
when x"3C0" => DATA <= x"20";
when x"3C1" => DATA <= x"C2";
when x"3C2" => DATA <= x"CC";
when x"3C3" => DATA <= x"F7";
when x"3C4" => DATA <= x"2A";
when x"3C5" => DATA <= x"AA";
when x"3C6" => DATA <= x"FC";
when x"3C7" => DATA <= x"CD";
when x"3C8" => DATA <= x"77";
when x"3C9" => DATA <= x"F8";
when x"3CA" => DATA <= x"CD";
when x"3CB" => DATA <= x"39";
when x"3CC" => DATA <= x"F4";
when x"3CD" => DATA <= x"18";
when x"3CE" => DATA <= x"03";
when x"3CF" => DATA <= x"2A";
when x"3D0" => DATA <= x"AA";
when x"3D1" => DATA <= x"FC";
when x"3D2" => DATA <= x"ED";
when x"3D3" => DATA <= x"5B";
when x"3D4" => DATA <= x"AA";
when x"3D5" => DATA <= x"FC";
when x"3D6" => DATA <= x"3A";
when x"3D7" => DATA <= x"80";
when x"3D8" => DATA <= x"FF";
when x"3D9" => DATA <= x"CB";
when x"3DA" => DATA <= x"7F";
when x"3DB" => DATA <= x"C2";
when x"3DC" => DATA <= x"F7";
when x"3DD" => DATA <= x"F2";
when x"3DE" => DATA <= x"CD";
when x"3DF" => DATA <= x"E7";
when x"3E0" => DATA <= x"FF";
when x"3E1" => DATA <= x"CD";
when x"3E2" => DATA <= x"71";
when x"3E3" => DATA <= x"F4";
when x"3E4" => DATA <= x"06";
when x"3E5" => DATA <= x"08";
when x"3E6" => DATA <= x"E5";
when x"3E7" => DATA <= x"CD";
when x"3E8" => DATA <= x"1D";
when x"3E9" => DATA <= x"F4";
when x"3EA" => DATA <= x"7E";
when x"3EB" => DATA <= x"CD";
when x"3EC" => DATA <= x"76";
when x"3ED" => DATA <= x"F4";
when x"3EE" => DATA <= x"23";
when x"3EF" => DATA <= x"10";
when x"3F0" => DATA <= x"F6";
when x"3F1" => DATA <= x"06";
when x"3F2" => DATA <= x"08";
when x"3F3" => DATA <= x"E1";
when x"3F4" => DATA <= x"CD";
when x"3F5" => DATA <= x"1D";
when x"3F6" => DATA <= x"F4";
when x"3F7" => DATA <= x"7E";
when x"3F8" => DATA <= x"CD";
when x"3F9" => DATA <= x"0D";
when x"3FA" => DATA <= x"F4";
when x"3FB" => DATA <= x"23";
when x"3FC" => DATA <= x"10";
when x"3FD" => DATA <= x"F9";
when x"3FE" => DATA <= x"CD";
when x"3FF" => DATA <= x"23";
when x"400" => DATA <= x"F4";
when x"401" => DATA <= x"D2";
when x"402" => DATA <= x"06";
when x"403" => DATA <= x"F4";
when x"404" => DATA <= x"18";
when x"405" => DATA <= x"D0";
when x"406" => DATA <= x"CD";
when x"407" => DATA <= x"E7";
when x"408" => DATA <= x"FF";
when x"409" => DATA <= x"D1";
when x"40A" => DATA <= x"C1";
when x"40B" => DATA <= x"F1";
when x"40C" => DATA <= x"C9";
when x"40D" => DATA <= x"FE";
when x"40E" => DATA <= x"20";
when x"40F" => DATA <= x"38";
when x"410" => DATA <= x"06";
when x"411" => DATA <= x"FE";
when x"412" => DATA <= x"7F";
when x"413" => DATA <= x"30";
when x"414" => DATA <= x"02";
when x"415" => DATA <= x"18";
when x"416" => DATA <= x"02";
when x"417" => DATA <= x"3E";
when x"418" => DATA <= x"2E";
when x"419" => DATA <= x"CD";
when x"41A" => DATA <= x"71";
when x"41B" => DATA <= x"F6";
when x"41C" => DATA <= x"C9";
when x"41D" => DATA <= x"3E";
when x"41E" => DATA <= x"20";
when x"41F" => DATA <= x"CD";
when x"420" => DATA <= x"71";
when x"421" => DATA <= x"F6";
when x"422" => DATA <= x"C9";
when x"423" => DATA <= x"E5";
when x"424" => DATA <= x"01";
when x"425" => DATA <= x"08";
when x"426" => DATA <= x"00";
when x"427" => DATA <= x"BF";
when x"428" => DATA <= x"ED";
when x"429" => DATA <= x"42";
when x"42A" => DATA <= x"30";
when x"42B" => DATA <= x"06";
when x"42C" => DATA <= x"21";
when x"42D" => DATA <= x"00";
when x"42E" => DATA <= x"00";
when x"42F" => DATA <= x"BF";
when x"430" => DATA <= x"18";
when x"431" => DATA <= x"02";
when x"432" => DATA <= x"E1";
when x"433" => DATA <= x"E5";
when x"434" => DATA <= x"2B";
when x"435" => DATA <= x"ED";
when x"436" => DATA <= x"52";
when x"437" => DATA <= x"E1";
when x"438" => DATA <= x"C9";
when x"439" => DATA <= x"22";
when x"43A" => DATA <= x"AC";
when x"43B" => DATA <= x"FC";
when x"43C" => DATA <= x"21";
when x"43D" => DATA <= x"00";
when x"43E" => DATA <= x"00";
when x"43F" => DATA <= x"1A";
when x"440" => DATA <= x"CB";
when x"441" => DATA <= x"77";
when x"442" => DATA <= x"28";
when x"443" => DATA <= x"02";
when x"444" => DATA <= x"E6";
when x"445" => DATA <= x"DF";
when x"446" => DATA <= x"FE";
when x"447" => DATA <= x"30";
when x"448" => DATA <= x"FA";
when x"449" => DATA <= x"6D";
when x"44A" => DATA <= x"F4";
when x"44B" => DATA <= x"FE";
when x"44C" => DATA <= x"47";
when x"44D" => DATA <= x"F2";
when x"44E" => DATA <= x"6D";
when x"44F" => DATA <= x"F4";
when x"450" => DATA <= x"FE";
when x"451" => DATA <= x"3A";
when x"452" => DATA <= x"38";
when x"453" => DATA <= x"07";
when x"454" => DATA <= x"FE";
when x"455" => DATA <= x"41";
when x"456" => DATA <= x"FA";
when x"457" => DATA <= x"6D";
when x"458" => DATA <= x"F4";
when x"459" => DATA <= x"C6";
when x"45A" => DATA <= x"09";
when x"45B" => DATA <= x"E6";
when x"45C" => DATA <= x"0F";
when x"45D" => DATA <= x"29";
when x"45E" => DATA <= x"29";
when x"45F" => DATA <= x"29";
when x"460" => DATA <= x"29";
when x"461" => DATA <= x"B5";
when x"462" => DATA <= x"6F";
when x"463" => DATA <= x"3E";
when x"464" => DATA <= x"01";
when x"465" => DATA <= x"B8";
when x"466" => DATA <= x"C8";
when x"467" => DATA <= x"13";
when x"468" => DATA <= x"22";
when x"469" => DATA <= x"AA";
when x"46A" => DATA <= x"FC";
when x"46B" => DATA <= x"18";
when x"46C" => DATA <= x"D2";
when x"46D" => DATA <= x"2A";
when x"46E" => DATA <= x"AC";
when x"46F" => DATA <= x"FC";
when x"470" => DATA <= x"C9";
when x"471" => DATA <= x"7C";
when x"472" => DATA <= x"CD";
when x"473" => DATA <= x"76";
when x"474" => DATA <= x"F4";
when x"475" => DATA <= x"7D";
when x"476" => DATA <= x"F5";
when x"477" => DATA <= x"0F";
when x"478" => DATA <= x"0F";
when x"479" => DATA <= x"0F";
when x"47A" => DATA <= x"0F";
when x"47B" => DATA <= x"CD";
when x"47C" => DATA <= x"7F";
when x"47D" => DATA <= x"F4";
when x"47E" => DATA <= x"F1";
when x"47F" => DATA <= x"E6";
when x"480" => DATA <= x"0F";
when x"481" => DATA <= x"C6";
when x"482" => DATA <= x"30";
when x"483" => DATA <= x"FE";
when x"484" => DATA <= x"3A";
when x"485" => DATA <= x"FA";
when x"486" => DATA <= x"71";
when x"487" => DATA <= x"F6";
when x"488" => DATA <= x"C6";
when x"489" => DATA <= x"07";
when x"48A" => DATA <= x"C3";
when x"48B" => DATA <= x"71";
when x"48C" => DATA <= x"F6";
when x"48D" => DATA <= x"13";
when x"48E" => DATA <= x"1A";
when x"48F" => DATA <= x"E6";
when x"490" => DATA <= x"DF";
when x"491" => DATA <= x"FE";
when x"492" => DATA <= x"50";
when x"493" => DATA <= x"C2";
when x"494" => DATA <= x"CC";
when x"495" => DATA <= x"F7";
when x"496" => DATA <= x"13";
when x"497" => DATA <= x"1A";
when x"498" => DATA <= x"E6";
when x"499" => DATA <= x"DF";
when x"49A" => DATA <= x"FE";
when x"49B" => DATA <= x"4D";
when x"49C" => DATA <= x"C2";
when x"49D" => DATA <= x"CC";
when x"49E" => DATA <= x"F7";
when x"49F" => DATA <= x"CD";
when x"4A0" => DATA <= x"76";
when x"4A1" => DATA <= x"F8";
when x"4A2" => DATA <= x"FE";
when x"4A3" => DATA <= x"0D";
when x"4A4" => DATA <= x"C2";
when x"4A5" => DATA <= x"CC";
when x"4A6" => DATA <= x"F7";
when x"4A7" => DATA <= x"18";
when x"4A8" => DATA <= x"26";
when x"4A9" => DATA <= x"CD";
when x"4AA" => DATA <= x"0E";
when x"4AB" => DATA <= x"F6";
when x"4AC" => DATA <= x"49";
when x"4AD" => DATA <= x"6E";
when x"4AE" => DATA <= x"73";
when x"4AF" => DATA <= x"65";
when x"4B0" => DATA <= x"72";
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when x"4B3" => DATA <= x"43";
when x"4B4" => DATA <= x"50";
when x"4B5" => DATA <= x"2F";
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when x"4B8" => DATA <= x"53";
when x"4B9" => DATA <= x"79";
when x"4BA" => DATA <= x"73";
when x"4BB" => DATA <= x"74";
when x"4BC" => DATA <= x"65";
when x"4BD" => DATA <= x"6D";
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when x"4C0" => DATA <= x"69";
when x"4C1" => DATA <= x"73";
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when x"4C3" => DATA <= x"20";
when x"4C4" => DATA <= x"69";
when x"4C5" => DATA <= x"6E";
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when x"4C7" => DATA <= x"64";
when x"4C8" => DATA <= x"72";
when x"4C9" => DATA <= x"69";
when x"4CA" => DATA <= x"76";
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when x"4CC" => DATA <= x"20";
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when x"4CE" => DATA <= x"00";
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when x"4D2" => DATA <= x"01";
when x"4D3" => DATA <= x"00";
when x"4D4" => DATA <= x"CD";
when x"4D5" => DATA <= x"8E";
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when x"4D7" => DATA <= x"21";
when x"4D8" => DATA <= x"82";
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when x"4DB" => DATA <= x"4A";
when x"4DC" => DATA <= x"F5";
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when x"4E0" => DATA <= x"11";
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when x"4E3" => DATA <= x"01";
when x"4E4" => DATA <= x"F0";
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when x"4E6" => DATA <= x"ED";
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when x"4E9" => DATA <= x"F0";
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when x"4EB" => DATA <= x"11";
when x"4EC" => DATA <= x"E0";
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when x"4EE" => DATA <= x"01";
when x"4EF" => DATA <= x"00";
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when x"4F2" => DATA <= x"B0";
when x"4F3" => DATA <= x"CD";
when x"4F4" => DATA <= x"3B";
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when x"4F6" => DATA <= x"3A";
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when x"4F8" => DATA <= x"D4";
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when x"4FA" => DATA <= x"C3";
when x"4FB" => DATA <= x"CA";
when x"4FC" => DATA <= x"22";
when x"4FD" => DATA <= x"F5";
when x"4FE" => DATA <= x"3E";
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when x"500" => DATA <= x"21";
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when x"502" => DATA <= x"00";
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when x"505" => DATA <= x"F8";
when x"506" => DATA <= x"CD";
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when x"50A" => DATA <= x"C8";
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when x"50E" => DATA <= x"20";
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when x"512" => DATA <= x"50";
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when x"515" => DATA <= x"20";
when x"516" => DATA <= x"53";
when x"517" => DATA <= x"79";
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when x"51A" => DATA <= x"65";
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when x"51F" => DATA <= x"73";
when x"520" => DATA <= x"63";
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when x"525" => DATA <= x"22";
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when x"527" => DATA <= x"FF";
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when x"530" => DATA <= x"CD";
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when x"533" => DATA <= x"CD";
when x"534" => DATA <= x"0E";
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when x"536" => DATA <= x"16";
when x"537" => DATA <= x"00";
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when x"53F" => DATA <= x"4A";
when x"540" => DATA <= x"F5";
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when x"542" => DATA <= x"98";
when x"543" => DATA <= x"F5";
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when x"546" => DATA <= x"F5";
when x"547" => DATA <= x"21";
when x"548" => DATA <= x"A3";
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when x"54A" => DATA <= x"CD";
when x"54B" => DATA <= x"5C";
when x"54C" => DATA <= x"F5";
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when x"54E" => DATA <= x"C8";
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when x"550" => DATA <= x"C7";
when x"551" => DATA <= x"44";
when x"552" => DATA <= x"69";
when x"553" => DATA <= x"73";
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when x"555" => DATA <= x"20";
when x"556" => DATA <= x"66";
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when x"558" => DATA <= x"75";
when x"559" => DATA <= x"6C";
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when x"55F" => DATA <= x"06";
when x"560" => DATA <= x"0A";
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when x"563" => DATA <= x"CD";
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when x"566" => DATA <= x"11";
when x"567" => DATA <= x"0A";
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when x"56A" => DATA <= x"19";
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when x"56D" => DATA <= x"A7";
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when x"570" => DATA <= x"FE";
when x"571" => DATA <= x"12";
when x"572" => DATA <= x"C8";
when x"573" => DATA <= x"B7";
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when x"575" => DATA <= x"10";
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when x"578" => DATA <= x"CD";
when x"579" => DATA <= x"1B";
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when x"57B" => DATA <= x"41";
when x"57C" => DATA <= x"10";
when x"57D" => DATA <= x"E0";
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when x"57F" => DATA <= x"A7";
when x"580" => DATA <= x"FC";
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when x"582" => DATA <= x"00";
when x"583" => DATA <= x"F0";
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when x"585" => DATA <= x"00";
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when x"589" => DATA <= x"00";
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when x"590" => DATA <= x"00";
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when x"5A3" => DATA <= x"00";
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when x"5A5" => DATA <= x"E0";
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when x"5B6" => DATA <= x"AA";
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when x"5BA" => DATA <= x"21";
when x"5BB" => DATA <= x"00";
when x"5BC" => DATA <= x"02";
when x"5BD" => DATA <= x"11";
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when x"5C0" => DATA <= x"06";
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when x"5C6" => DATA <= x"03";
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when x"5C8" => DATA <= x"11";
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when x"5CB" => DATA <= x"06";
when x"5CC" => DATA <= x"02";
when x"5CD" => DATA <= x"CD";
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when x"5D3" => DATA <= x"11";
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when x"5DC" => DATA <= x"C9";
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when x"600" => DATA <= x"CD";
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when x"622" => DATA <= x"F6";
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when x"626" => DATA <= x"73";
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when x"62A" => DATA <= x"80";
when x"62B" => DATA <= x"FF";
when x"62C" => DATA <= x"CD";
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when x"62F" => DATA <= x"ED";
when x"630" => DATA <= x"7B";
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when x"632" => DATA <= x"FC";
when x"633" => DATA <= x"E1";
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when x"636" => DATA <= x"00";
when x"637" => DATA <= x"00";
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when x"63C" => DATA <= x"69";
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when x"648" => DATA <= x"7D";
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when x"64A" => DATA <= x"28";
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when x"64C" => DATA <= x"18";
when x"64D" => DATA <= x"0C";
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when x"650" => DATA <= x"21";
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when x"652" => DATA <= x"FF";
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when x"656" => DATA <= x"7D";
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when x"658" => DATA <= x"28";
when x"659" => DATA <= x"02";
when x"65A" => DATA <= x"3E";
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when x"65C" => DATA <= x"E1";
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when x"65E" => DATA <= x"C5";
when x"65F" => DATA <= x"D5";
when x"660" => DATA <= x"E5";
when x"661" => DATA <= x"21";
when x"662" => DATA <= x"BC";
when x"663" => DATA <= x"FF";
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when x"665" => DATA <= x"38";
when x"666" => DATA <= x"00";
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when x"668" => DATA <= x"03";
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when x"66A" => DATA <= x"ED";
when x"66B" => DATA <= x"B0";
when x"66C" => DATA <= x"E1";
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when x"66E" => DATA <= x"C1";
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when x"670" => DATA <= x"C9";
when x"671" => DATA <= x"F5";
when x"672" => DATA <= x"DB";
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when x"676" => DATA <= x"28";
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when x"678" => DATA <= x"F1";
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when x"67A" => DATA <= x"01";
when x"67B" => DATA <= x"C9";
when x"67C" => DATA <= x"DB";
when x"67D" => DATA <= x"00";
when x"67E" => DATA <= x"CB";
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when x"680" => DATA <= x"20";
when x"681" => DATA <= x"0B";
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when x"683" => DATA <= x"06";
when x"684" => DATA <= x"CB";
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when x"686" => DATA <= x"28";
when x"687" => DATA <= x"F4";
when x"688" => DATA <= x"CD";
when x"689" => DATA <= x"0B";
when x"68A" => DATA <= x"FB";
when x"68B" => DATA <= x"18";
when x"68C" => DATA <= x"EF";
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when x"68F" => DATA <= x"C9";
when x"690" => DATA <= x"3E";
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when x"692" => DATA <= x"CD";
when x"693" => DATA <= x"A3";
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when x"695" => DATA <= x"CD";
when x"696" => DATA <= x"9A";
when x"697" => DATA <= x"F6";
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when x"699" => DATA <= x"27";
when x"69A" => DATA <= x"DB";
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when x"69C" => DATA <= x"CB";
when x"69D" => DATA <= x"7F";
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when x"69F" => DATA <= x"FA";
when x"6A0" => DATA <= x"DB";
when x"6A1" => DATA <= x"03";
when x"6A2" => DATA <= x"C9";
when x"6A3" => DATA <= x"F5";
when x"6A4" => DATA <= x"DB";
when x"6A5" => DATA <= x"02";
when x"6A6" => DATA <= x"CB";
when x"6A7" => DATA <= x"77";
when x"6A8" => DATA <= x"28";
when x"6A9" => DATA <= x"FA";
when x"6AA" => DATA <= x"F1";
when x"6AB" => DATA <= x"D3";
when x"6AC" => DATA <= x"03";
when x"6AD" => DATA <= x"C9";
when x"6AE" => DATA <= x"DB";
when x"6AF" => DATA <= x"06";
when x"6B0" => DATA <= x"CB";
when x"6B1" => DATA <= x"7F";
when x"6B2" => DATA <= x"28";
when x"6B3" => DATA <= x"FA";
when x"6B4" => DATA <= x"DB";
when x"6B5" => DATA <= x"07";
when x"6B6" => DATA <= x"C9";
when x"6B7" => DATA <= x"F5";
when x"6B8" => DATA <= x"C5";
when x"6B9" => DATA <= x"D5";
when x"6BA" => DATA <= x"54";
when x"6BB" => DATA <= x"5D";
when x"6BC" => DATA <= x"CD";
when x"6BD" => DATA <= x"7E";
when x"6BE" => DATA <= x"F8";
when x"6BF" => DATA <= x"CD";
when x"6C0" => DATA <= x"77";
when x"6C1" => DATA <= x"F8";
when x"6C2" => DATA <= x"FE";
when x"6C3" => DATA <= x"2A";
when x"6C4" => DATA <= x"28";
when x"6C5" => DATA <= x"F6";
when x"6C6" => DATA <= x"E6";
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when x"6C9" => DATA <= x"48";
when x"6CA" => DATA <= x"28";
when x"6CB" => DATA <= x"20";
when x"6CC" => DATA <= x"4F";
when x"6CD" => DATA <= x"3A";
when x"6CE" => DATA <= x"A3";
when x"6CF" => DATA <= x"FC";
when x"6D0" => DATA <= x"B7";
when x"6D1" => DATA <= x"79";
when x"6D2" => DATA <= x"C2";
when x"6D3" => DATA <= x"CC";
when x"6D4" => DATA <= x"F7";
when x"6D5" => DATA <= x"FE";
when x"6D6" => DATA <= x"47";
when x"6D7" => DATA <= x"CA";
when x"6D8" => DATA <= x"08";
when x"6D9" => DATA <= x"F3";
when x"6DA" => DATA <= x"FE";
when x"6DB" => DATA <= x"44";
when x"6DC" => DATA <= x"CA";
when x"6DD" => DATA <= x"B3";
when x"6DE" => DATA <= x"F3";
when x"6DF" => DATA <= x"FE";
when x"6E0" => DATA <= x"53";
when x"6E1" => DATA <= x"CA";
when x"6E2" => DATA <= x"30";
when x"6E3" => DATA <= x"F3";
when x"6E4" => DATA <= x"FE";
when x"6E5" => DATA <= x"43";
when x"6E6" => DATA <= x"CA";
when x"6E7" => DATA <= x"8D";
when x"6E8" => DATA <= x"F4";
when x"6E9" => DATA <= x"C3";
when x"6EA" => DATA <= x"CC";
when x"6EB" => DATA <= x"F7";
when x"6EC" => DATA <= x"13";
when x"6ED" => DATA <= x"1A";
when x"6EE" => DATA <= x"FE";
when x"6EF" => DATA <= x"2E";
when x"6F0" => DATA <= x"28";
when x"6F1" => DATA <= x"2E";
when x"6F2" => DATA <= x"E6";
when x"6F3" => DATA <= x"DF";
when x"6F4" => DATA <= x"FE";
when x"6F5" => DATA <= x"45";
when x"6F6" => DATA <= x"C2";
when x"6F7" => DATA <= x"CC";
when x"6F8" => DATA <= x"F7";
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when x"6FA" => DATA <= x"1A";
when x"6FB" => DATA <= x"FE";
when x"6FC" => DATA <= x"2E";
when x"6FD" => DATA <= x"28";
when x"6FE" => DATA <= x"21";
when x"6FF" => DATA <= x"E6";
when x"700" => DATA <= x"DF";
when x"701" => DATA <= x"FE";
when x"702" => DATA <= x"4C";
when x"703" => DATA <= x"C2";
when x"704" => DATA <= x"CC";
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when x"706" => DATA <= x"13";
when x"707" => DATA <= x"1A";
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when x"70C" => DATA <= x"E6";
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when x"70F" => DATA <= x"50";
when x"710" => DATA <= x"C2";
when x"711" => DATA <= x"CC";
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when x"713" => DATA <= x"13";
when x"714" => DATA <= x"1A";
when x"715" => DATA <= x"CD";
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when x"718" => DATA <= x"D2";
when x"719" => DATA <= x"CC";
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when x"71B" => DATA <= x"CD";
when x"71C" => DATA <= x"77";
when x"71D" => DATA <= x"F8";
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when x"71F" => DATA <= x"03";
when x"720" => DATA <= x"CD";
when x"721" => DATA <= x"76";
when x"722" => DATA <= x"F8";
when x"723" => DATA <= x"CD";
when x"724" => DATA <= x"B3";
when x"725" => DATA <= x"FF";
when x"726" => DATA <= x"0D";
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when x"728" => DATA <= x"38";
when x"729" => DATA <= x"30";
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when x"72B" => DATA <= x"54";
when x"72C" => DATA <= x"55";
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when x"72E" => DATA <= x"45";
when x"72F" => DATA <= x"20";
when x"730" => DATA <= x"31";
when x"731" => DATA <= x"2E";
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when x"733" => DATA <= x"31";
when x"734" => DATA <= x"0D";
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when x"736" => DATA <= x"4F";
when x"737" => DATA <= x"3A";
when x"738" => DATA <= x"A3";
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when x"73A" => DATA <= x"B7";
when x"73B" => DATA <= x"79";
when x"73C" => DATA <= x"C2";
when x"73D" => DATA <= x"CC";
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when x"73F" => DATA <= x"FE";
when x"740" => DATA <= x"0D";
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when x"742" => DATA <= x"29";
when x"743" => DATA <= x"E6";
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when x"745" => DATA <= x"FE";
when x"746" => DATA <= x"4D";
when x"747" => DATA <= x"28";
when x"748" => DATA <= x"09";
when x"749" => DATA <= x"FE";
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when x"74B" => DATA <= x"CA";
when x"74C" => DATA <= x"CC";
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when x"74E" => DATA <= x"13";
when x"74F" => DATA <= x"1A";
when x"750" => DATA <= x"18";
when x"751" => DATA <= x"F1";
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when x"753" => DATA <= x"1A";
when x"754" => DATA <= x"E6";
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when x"75A" => DATA <= x"13";
when x"75B" => DATA <= x"1A";
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when x"75E" => DATA <= x"FE";
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when x"761" => DATA <= x"EC";
when x"762" => DATA <= x"13";
when x"763" => DATA <= x"1A";
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when x"765" => DATA <= x"6D";
when x"766" => DATA <= x"F8";
when x"767" => DATA <= x"D2";
when x"768" => DATA <= x"4E";
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when x"76A" => DATA <= x"18";
when x"76B" => DATA <= x"0C";
when x"76C" => DATA <= x"CD";
when x"76D" => DATA <= x"0E";
when x"76E" => DATA <= x"F6";
when x"76F" => DATA <= x"20";
when x"770" => DATA <= x"20";
when x"771" => DATA <= x"4D";
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when x"773" => DATA <= x"4E";
when x"774" => DATA <= x"0D";
when x"775" => DATA <= x"00";
when x"776" => DATA <= x"18";
when x"777" => DATA <= x"54";
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when x"77B" => DATA <= x"20";
when x"77C" => DATA <= x"20";
when x"77D" => DATA <= x"43";
when x"77E" => DATA <= x"50";
when x"77F" => DATA <= x"4D";
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when x"781" => DATA <= x"20";
when x"782" => DATA <= x"20";
when x"783" => DATA <= x"44";
when x"784" => DATA <= x"75";
when x"785" => DATA <= x"6D";
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when x"787" => DATA <= x"20";
when x"788" => DATA <= x"3C";
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when x"78A" => DATA <= x"74";
when x"78B" => DATA <= x"61";
when x"78C" => DATA <= x"72";
when x"78D" => DATA <= x"74";
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when x"78F" => DATA <= x"61";
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when x"791" => DATA <= x"64";
when x"792" => DATA <= x"72";
when x"793" => DATA <= x"65";
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when x"795" => DATA <= x"73";
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when x"79F" => DATA <= x"64";
when x"7A0" => DATA <= x"72";
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when x"7A2" => DATA <= x"73";
when x"7A3" => DATA <= x"73";
when x"7A4" => DATA <= x"3E";
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when x"7A7" => DATA <= x"20";
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when x"7AA" => DATA <= x"20";
when x"7AB" => DATA <= x"3C";
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when x"7AD" => DATA <= x"64";
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when x"7B0" => DATA <= x"65";
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when x"7B2" => DATA <= x"73";
when x"7B3" => DATA <= x"3E";
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when x"7B6" => DATA <= x"20";
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when x"7D1" => DATA <= x"CD";
when x"7D2" => DATA <= x"84";
when x"7D3" => DATA <= x"F8";
when x"7D4" => DATA <= x"CD";
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when x"7D9" => DATA <= x"28";
when x"7DA" => DATA <= x"04";
when x"7DB" => DATA <= x"D1";
when x"7DC" => DATA <= x"C1";
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when x"7E2" => DATA <= x"AF";
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when x"7E5" => DATA <= x"EB";
when x"7E6" => DATA <= x"F7";
when x"7E7" => DATA <= x"D1";
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when x"7F2" => DATA <= x"E5";
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when x"7F5" => DATA <= x"A8";
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when x"7FC" => DATA <= x"7E";
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when x"80D" => DATA <= x"AF";
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when x"816" => DATA <= x"40";
when x"817" => DATA <= x"38";
when x"818" => DATA <= x"09";
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when x"81F" => DATA <= x"A8";
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when x"825" => DATA <= x"F4";
when x"826" => DATA <= x"E1";
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when x"828" => DATA <= x"F4";
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when x"82D" => DATA <= x"7E";
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when x"82F" => DATA <= x"4F";
when x"830" => DATA <= x"FE";
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when x"832" => DATA <= x"38";
when x"833" => DATA <= x"09";
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when x"83A" => DATA <= x"18";
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when x"83E" => DATA <= x"F9";
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when x"840" => DATA <= x"68";
when x"841" => DATA <= x"69";
when x"842" => DATA <= x"73";
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when x"844" => DATA <= x"69";
when x"845" => DATA <= x"73";
when x"846" => DATA <= x"20";
when x"847" => DATA <= x"6E";
when x"848" => DATA <= x"6F";
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when x"84A" => DATA <= x"20";
when x"84B" => DATA <= x"61";
when x"84C" => DATA <= x"20";
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when x"84F" => DATA <= x"6E";
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when x"851" => DATA <= x"75";
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when x"85A" => DATA <= x"69";
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when x"866" => DATA <= x"30";
when x"867" => DATA <= x"20";
when x"868" => DATA <= x"63";
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when x"86B" => DATA <= x"65";
when x"86C" => DATA <= x"00";
when x"86D" => DATA <= x"E6";
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when x"86F" => DATA <= x"FE";
when x"870" => DATA <= x"41";
when x"871" => DATA <= x"D8";
when x"872" => DATA <= x"FE";
when x"873" => DATA <= x"5B";
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when x"875" => DATA <= x"C9";
when x"876" => DATA <= x"13";
when x"877" => DATA <= x"1A";
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when x"87A" => DATA <= x"28";
when x"87B" => DATA <= x"FA";
when x"87C" => DATA <= x"C9";
when x"87D" => DATA <= x"13";
when x"87E" => DATA <= x"1A";
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when x"880" => DATA <= x"2A";
when x"881" => DATA <= x"28";
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when x"884" => DATA <= x"7E";
when x"885" => DATA <= x"CD";
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when x"888" => DATA <= x"23";
when x"889" => DATA <= x"FE";
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when x"88C" => DATA <= x"F7";
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when x"88F" => DATA <= x"80";
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when x"891" => DATA <= x"15";
when x"892" => DATA <= x"F5";
when x"893" => DATA <= x"3E";
when x"894" => DATA <= x"04";
when x"895" => DATA <= x"CD";
when x"896" => DATA <= x"A3";
when x"897" => DATA <= x"F6";
when x"898" => DATA <= x"7D";
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when x"89A" => DATA <= x"A3";
when x"89B" => DATA <= x"F6";
when x"89C" => DATA <= x"F1";
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when x"89E" => DATA <= x"CD";
when x"89F" => DATA <= x"A3";
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when x"8A1" => DATA <= x"CD";
when x"8A2" => DATA <= x"9A";
when x"8A3" => DATA <= x"F6";
when x"8A4" => DATA <= x"6F";
when x"8A5" => DATA <= x"F1";
when x"8A6" => DATA <= x"C9";
when x"8A7" => DATA <= x"FE";
when x"8A8" => DATA <= x"82";
when x"8A9" => DATA <= x"28";
when x"8AA" => DATA <= x"31";
when x"8AB" => DATA <= x"FE";
when x"8AC" => DATA <= x"83";
when x"8AD" => DATA <= x"28";
when x"8AE" => DATA <= x"31";
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when x"8B0" => DATA <= x"84";
when x"8B1" => DATA <= x"28";
when x"8B2" => DATA <= x"31";
when x"8B3" => DATA <= x"F5";
when x"8B4" => DATA <= x"3E";
when x"8B5" => DATA <= x"06";
when x"8B6" => DATA <= x"CD";
when x"8B7" => DATA <= x"A3";
when x"8B8" => DATA <= x"F6";
when x"8B9" => DATA <= x"7D";
when x"8BA" => DATA <= x"CD";
when x"8BB" => DATA <= x"A3";
when x"8BC" => DATA <= x"F6";
when x"8BD" => DATA <= x"7C";
when x"8BE" => DATA <= x"CD";
when x"8BF" => DATA <= x"A3";
when x"8C0" => DATA <= x"F6";
when x"8C1" => DATA <= x"F1";
when x"8C2" => DATA <= x"F5";
when x"8C3" => DATA <= x"CD";
when x"8C4" => DATA <= x"A3";
when x"8C5" => DATA <= x"F6";
when x"8C6" => DATA <= x"FE";
when x"8C7" => DATA <= x"9D";
when x"8C8" => DATA <= x"28";
when x"8C9" => DATA <= x"10";
when x"8CA" => DATA <= x"CD";
when x"8CB" => DATA <= x"9A";
when x"8CC" => DATA <= x"F6";
when x"8CD" => DATA <= x"6F";
when x"8CE" => DATA <= x"F1";
when x"8CF" => DATA <= x"CB";
when x"8D0" => DATA <= x"25";
when x"8D1" => DATA <= x"F5";
when x"8D2" => DATA <= x"CD";
when x"8D3" => DATA <= x"9A";
when x"8D4" => DATA <= x"F6";
when x"8D5" => DATA <= x"67";
when x"8D6" => DATA <= x"CD";
when x"8D7" => DATA <= x"9A";
when x"8D8" => DATA <= x"F6";
when x"8D9" => DATA <= x"6F";
when x"8DA" => DATA <= x"F1";
when x"8DB" => DATA <= x"C9";
when x"8DC" => DATA <= x"21";
when x"8DD" => DATA <= x"00";
when x"8DE" => DATA <= x"00";
when x"8DF" => DATA <= x"C9";
when x"8E0" => DATA <= x"21";
when x"8E1" => DATA <= x"03";
when x"8E2" => DATA <= x"3B";
when x"8E3" => DATA <= x"C9";
when x"8E4" => DATA <= x"21";
when x"8E5" => DATA <= x"00";
when x"8E6" => DATA <= x"DC";
when x"8E7" => DATA <= x"C9";
when x"8E8" => DATA <= x"F5";
when x"8E9" => DATA <= x"3E";
when x"8EA" => DATA <= x"01";
when x"8EB" => DATA <= x"32";
when x"8EC" => DATA <= x"A4";
when x"8ED" => DATA <= x"FC";
when x"8EE" => DATA <= x"F1";
when x"8EF" => DATA <= x"B7";
when x"8F0" => DATA <= x"28";
when x"8F1" => DATA <= x"6B";
when x"8F2" => DATA <= x"C5";
when x"8F3" => DATA <= x"E5";
when x"8F4" => DATA <= x"DD";
when x"8F5" => DATA <= x"E5";
when x"8F6" => DATA <= x"F5";
when x"8F7" => DATA <= x"3E";
when x"8F8" => DATA <= x"08";
when x"8F9" => DATA <= x"CD";
when x"8FA" => DATA <= x"A3";
when x"8FB" => DATA <= x"F6";
when x"8FC" => DATA <= x"F1";
when x"8FD" => DATA <= x"F5";
when x"8FE" => DATA <= x"CD";
when x"8FF" => DATA <= x"A3";
when x"900" => DATA <= x"F6";
when x"901" => DATA <= x"06";
when x"902" => DATA <= x"00";
when x"903" => DATA <= x"4F";
when x"904" => DATA <= x"FE";
when x"905" => DATA <= x"80";
when x"906" => DATA <= x"38";
when x"907" => DATA <= x"06";
when x"908" => DATA <= x"46";
when x"909" => DATA <= x"23";
when x"90A" => DATA <= x"4E";
when x"90B" => DATA <= x"2B";
when x"90C" => DATA <= x"18";
when x"90D" => DATA <= x"15";
when x"90E" => DATA <= x"FE";
when x"90F" => DATA <= x"15";
when x"910" => DATA <= x"38";
when x"911" => DATA <= x"05";
when x"912" => DATA <= x"01";
when x"913" => DATA <= x"10";
when x"914" => DATA <= x"10";
when x"915" => DATA <= x"18";
when x"916" => DATA <= x"0C";
when x"917" => DATA <= x"DD";
when x"918" => DATA <= x"21";
when x"919" => DATA <= x"75";
when x"91A" => DATA <= x"FC";
when x"91B" => DATA <= x"DD";
when x"91C" => DATA <= x"09";
when x"91D" => DATA <= x"DD";
when x"91E" => DATA <= x"46";
when x"91F" => DATA <= x"FF";
when x"920" => DATA <= x"DD";
when x"921" => DATA <= x"4E";
when x"922" => DATA <= x"13";
when x"923" => DATA <= x"E5";
when x"924" => DATA <= x"C5";
when x"925" => DATA <= x"48";
when x"926" => DATA <= x"06";
when x"927" => DATA <= x"00";
when x"928" => DATA <= x"09";
when x"929" => DATA <= x"C1";
when x"92A" => DATA <= x"78";
when x"92B" => DATA <= x"CD";
when x"92C" => DATA <= x"A3";
when x"92D" => DATA <= x"F6";
when x"92E" => DATA <= x"B7";
when x"92F" => DATA <= x"28";
when x"930" => DATA <= x"07";
when x"931" => DATA <= x"2B";
when x"932" => DATA <= x"7E";
when x"933" => DATA <= x"CD";
when x"934" => DATA <= x"A3";
when x"935" => DATA <= x"F6";
when x"936" => DATA <= x"10";
when x"937" => DATA <= x"F9";
when x"938" => DATA <= x"79";
when x"939" => DATA <= x"CD";
when x"93A" => DATA <= x"A3";
when x"93B" => DATA <= x"F6";
when x"93C" => DATA <= x"E1";
when x"93D" => DATA <= x"F5";
when x"93E" => DATA <= x"3A";
when x"93F" => DATA <= x"A4";
when x"940" => DATA <= x"FC";
when x"941" => DATA <= x"B7";
when x"942" => DATA <= x"28";
when x"943" => DATA <= x"06";
when x"944" => DATA <= x"62";
when x"945" => DATA <= x"6B";
when x"946" => DATA <= x"AF";
when x"947" => DATA <= x"32";
when x"948" => DATA <= x"A4";
when x"949" => DATA <= x"FC";
when x"94A" => DATA <= x"F1";
when x"94B" => DATA <= x"B7";
when x"94C" => DATA <= x"28";
when x"94D" => DATA <= x"09";
when x"94E" => DATA <= x"09";
when x"94F" => DATA <= x"41";
when x"950" => DATA <= x"2B";
when x"951" => DATA <= x"CD";
when x"952" => DATA <= x"9A";
when x"953" => DATA <= x"F6";
when x"954" => DATA <= x"77";
when x"955" => DATA <= x"10";
when x"956" => DATA <= x"F9";
when x"957" => DATA <= x"F1";
when x"958" => DATA <= x"DD";
when x"959" => DATA <= x"E1";
when x"95A" => DATA <= x"E1";
when x"95B" => DATA <= x"C1";
when x"95C" => DATA <= x"C9";
when x"95D" => DATA <= x"C5";
when x"95E" => DATA <= x"F5";
when x"95F" => DATA <= x"3E";
when x"960" => DATA <= x"0A";
when x"961" => DATA <= x"CD";
when x"962" => DATA <= x"A3";
when x"963" => DATA <= x"F6";
when x"964" => DATA <= x"23";
when x"965" => DATA <= x"23";
when x"966" => DATA <= x"23";
when x"967" => DATA <= x"23";
when x"968" => DATA <= x"06";
when x"969" => DATA <= x"03";
when x"96A" => DATA <= x"7E";
when x"96B" => DATA <= x"CD";
when x"96C" => DATA <= x"A3";
when x"96D" => DATA <= x"F6";
when x"96E" => DATA <= x"2B";
when x"96F" => DATA <= x"10";
when x"970" => DATA <= x"F9";
when x"971" => DATA <= x"3E";
when x"972" => DATA <= x"07";
when x"973" => DATA <= x"CD";
when x"974" => DATA <= x"A3";
when x"975" => DATA <= x"F6";
when x"976" => DATA <= x"97";
when x"977" => DATA <= x"CD";
when x"978" => DATA <= x"A3";
when x"979" => DATA <= x"F6";
when x"97A" => DATA <= x"CD";
when x"97B" => DATA <= x"9A";
when x"97C" => DATA <= x"F6";
when x"97D" => DATA <= x"07";
when x"97E" => DATA <= x"38";
when x"97F" => DATA <= x"18";
when x"980" => DATA <= x"7E";
when x"981" => DATA <= x"2B";
when x"982" => DATA <= x"6E";
when x"983" => DATA <= x"67";
when x"984" => DATA <= x"06";
when x"985" => DATA <= x"FF";
when x"986" => DATA <= x"CD";
when x"987" => DATA <= x"9A";
when x"988" => DATA <= x"F6";
when x"989" => DATA <= x"77";
when x"98A" => DATA <= x"23";
when x"98B" => DATA <= x"04";
when x"98C" => DATA <= x"FE";
when x"98D" => DATA <= x"0D";
when x"98E" => DATA <= x"20";
when x"98F" => DATA <= x"F6";
when x"990" => DATA <= x"2E";
when x"991" => DATA <= x"00";
when x"992" => DATA <= x"60";
when x"993" => DATA <= x"F1";
when x"994" => DATA <= x"C1";
when x"995" => DATA <= x"37";
when x"996" => DATA <= x"3F";
when x"997" => DATA <= x"C9";
when x"998" => DATA <= x"21";
when x"999" => DATA <= x"FF";
when x"99A" => DATA <= x"00";
when x"99B" => DATA <= x"F1";
when x"99C" => DATA <= x"C1";
when x"99D" => DATA <= x"37";
when x"99E" => DATA <= x"C9";
when x"99F" => DATA <= x"E5";
when x"9A0" => DATA <= x"D5";
when x"9A1" => DATA <= x"C5";
when x"9A2" => DATA <= x"F5";
when x"9A3" => DATA <= x"3E";
when x"9A4" => DATA <= x"0C";
when x"9A5" => DATA <= x"CD";
when x"9A6" => DATA <= x"A3";
when x"9A7" => DATA <= x"F6";
when x"9A8" => DATA <= x"7B";
when x"9A9" => DATA <= x"CD";
when x"9AA" => DATA <= x"A3";
when x"9AB" => DATA <= x"F6";
when x"9AC" => DATA <= x"23";
when x"9AD" => DATA <= x"23";
when x"9AE" => DATA <= x"23";
when x"9AF" => DATA <= x"06";
when x"9B0" => DATA <= x"04";
when x"9B1" => DATA <= x"7E";
when x"9B2" => DATA <= x"CD";
when x"9B3" => DATA <= x"A3";
when x"9B4" => DATA <= x"F6";
when x"9B5" => DATA <= x"2B";
when x"9B6" => DATA <= x"10";
when x"9B7" => DATA <= x"F9";
when x"9B8" => DATA <= x"23";
when x"9B9" => DATA <= x"F1";
when x"9BA" => DATA <= x"CD";
when x"9BB" => DATA <= x"A3";
when x"9BC" => DATA <= x"F6";
when x"9BD" => DATA <= x"CD";
when x"9BE" => DATA <= x"9A";
when x"9BF" => DATA <= x"F6";
when x"9C0" => DATA <= x"F5";
when x"9C1" => DATA <= x"23";
when x"9C2" => DATA <= x"23";
when x"9C3" => DATA <= x"23";
when x"9C4" => DATA <= x"06";
when x"9C5" => DATA <= x"04";
when x"9C6" => DATA <= x"CD";
when x"9C7" => DATA <= x"9A";
when x"9C8" => DATA <= x"F6";
when x"9C9" => DATA <= x"77";
when x"9CA" => DATA <= x"2B";
when x"9CB" => DATA <= x"10";
when x"9CC" => DATA <= x"F9";
when x"9CD" => DATA <= x"F1";
when x"9CE" => DATA <= x"C1";
when x"9CF" => DATA <= x"D1";
when x"9D0" => DATA <= x"E1";
when x"9D1" => DATA <= x"C9";
when x"9D2" => DATA <= x"F5";
when x"9D3" => DATA <= x"3E";
when x"9D4" => DATA <= x"12";
when x"9D5" => DATA <= x"CD";
when x"9D6" => DATA <= x"A3";
when x"9D7" => DATA <= x"F6";
when x"9D8" => DATA <= x"F1";
when x"9D9" => DATA <= x"CD";
when x"9DA" => DATA <= x"A3";
when x"9DB" => DATA <= x"F6";
when x"9DC" => DATA <= x"FE";
when x"9DD" => DATA <= x"00";
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when x"9DF" => DATA <= x"0A";
when x"9E0" => DATA <= x"F5";
when x"9E1" => DATA <= x"7C";
when x"9E2" => DATA <= x"CD";
when x"9E3" => DATA <= x"A3";
when x"9E4" => DATA <= x"F6";
when x"9E5" => DATA <= x"CD";
when x"9E6" => DATA <= x"9A";
when x"9E7" => DATA <= x"F6";
when x"9E8" => DATA <= x"F1";
when x"9E9" => DATA <= x"C9";
when x"9EA" => DATA <= x"CD";
when x"9EB" => DATA <= x"84";
when x"9EC" => DATA <= x"F8";
when x"9ED" => DATA <= x"C3";
when x"9EE" => DATA <= x"9A";
when x"9EF" => DATA <= x"F6";
when x"9F0" => DATA <= x"3E";
when x"9F1" => DATA <= x"0E";
when x"9F2" => DATA <= x"CD";
when x"9F3" => DATA <= x"A3";
when x"9F4" => DATA <= x"F6";
when x"9F5" => DATA <= x"7C";
when x"9F6" => DATA <= x"CD";
when x"9F7" => DATA <= x"A3";
when x"9F8" => DATA <= x"F6";
when x"9F9" => DATA <= x"C3";
when x"9FA" => DATA <= x"95";
when x"9FB" => DATA <= x"F6";
when x"9FC" => DATA <= x"F5";
when x"9FD" => DATA <= x"3E";
when x"9FE" => DATA <= x"10";
when x"9FF" => DATA <= x"CD";
when x"A00" => DATA <= x"A3";
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when x"A02" => DATA <= x"7C";
when x"A03" => DATA <= x"CD";
when x"A04" => DATA <= x"A3";
when x"A05" => DATA <= x"F6";
when x"A06" => DATA <= x"F1";
when x"A07" => DATA <= x"CD";
when x"A08" => DATA <= x"A3";
when x"A09" => DATA <= x"F6";
when x"A0A" => DATA <= x"F5";
when x"A0B" => DATA <= x"CD";
when x"A0C" => DATA <= x"9A";
when x"A0D" => DATA <= x"F6";
when x"A0E" => DATA <= x"F1";
when x"A0F" => DATA <= x"C9";
when x"A10" => DATA <= x"C5";
when x"A11" => DATA <= x"F5";
when x"A12" => DATA <= x"22";
when x"A13" => DATA <= x"AC";
when x"A14" => DATA <= x"FC";
when x"A15" => DATA <= x"3E";
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when x"A17" => DATA <= x"CD";
when x"A18" => DATA <= x"A3";
when x"A19" => DATA <= x"F6";
when x"A1A" => DATA <= x"01";
when x"A1B" => DATA <= x"11";
when x"A1C" => DATA <= x"00";
when x"A1D" => DATA <= x"09";
when x"A1E" => DATA <= x"06";
when x"A1F" => DATA <= x"10";
when x"A20" => DATA <= x"7E";
when x"A21" => DATA <= x"CD";
when x"A22" => DATA <= x"A3";
when x"A23" => DATA <= x"F6";
when x"A24" => DATA <= x"2B";
when x"A25" => DATA <= x"10";
when x"A26" => DATA <= x"F9";
when x"A27" => DATA <= x"7E";
when x"A28" => DATA <= x"2B";
when x"A29" => DATA <= x"6E";
when x"A2A" => DATA <= x"67";
when x"A2B" => DATA <= x"CD";
when x"A2C" => DATA <= x"84";
when x"A2D" => DATA <= x"F8";
when x"A2E" => DATA <= x"F1";
when x"A2F" => DATA <= x"CD";
when x"A30" => DATA <= x"A3";
when x"A31" => DATA <= x"F6";
when x"A32" => DATA <= x"CD";
when x"A33" => DATA <= x"9A";
when x"A34" => DATA <= x"F6";
when x"A35" => DATA <= x"E6";
when x"A36" => DATA <= x"FF";
when x"A37" => DATA <= x"F5";
when x"A38" => DATA <= x"2A";
when x"A39" => DATA <= x"AC";
when x"A3A" => DATA <= x"FC";
when x"A3B" => DATA <= x"01";
when x"A3C" => DATA <= x"11";
when x"A3D" => DATA <= x"00";
when x"A3E" => DATA <= x"09";
when x"A3F" => DATA <= x"06";
when x"A40" => DATA <= x"10";
when x"A41" => DATA <= x"CD";
when x"A42" => DATA <= x"9A";
when x"A43" => DATA <= x"F6";
when x"A44" => DATA <= x"77";
when x"A45" => DATA <= x"2B";
when x"A46" => DATA <= x"10";
when x"A47" => DATA <= x"F9";
when x"A48" => DATA <= x"2A";
when x"A49" => DATA <= x"AC";
when x"A4A" => DATA <= x"FC";
when x"A4B" => DATA <= x"F1";
when x"A4C" => DATA <= x"C1";
when x"A4D" => DATA <= x"C9";
when x"A4E" => DATA <= x"C5";
when x"A4F" => DATA <= x"F5";
when x"A50" => DATA <= x"22";
when x"A51" => DATA <= x"AC";
when x"A52" => DATA <= x"FC";
when x"A53" => DATA <= x"3E";
when x"A54" => DATA <= x"16";
when x"A55" => DATA <= x"CD";
when x"A56" => DATA <= x"A3";
when x"A57" => DATA <= x"F6";
when x"A58" => DATA <= x"01";
when x"A59" => DATA <= x"0C";
when x"A5A" => DATA <= x"00";
when x"A5B" => DATA <= x"09";
when x"A5C" => DATA <= x"06";
when x"A5D" => DATA <= x"0D";
when x"A5E" => DATA <= x"7E";
when x"A5F" => DATA <= x"CD";
when x"A60" => DATA <= x"A3";
when x"A61" => DATA <= x"F6";
when x"A62" => DATA <= x"2B";
when x"A63" => DATA <= x"10";
when x"A64" => DATA <= x"F9";
when x"A65" => DATA <= x"F1";
when x"A66" => DATA <= x"CD";
when x"A67" => DATA <= x"A3";
when x"A68" => DATA <= x"F6";
when x"A69" => DATA <= x"2A";
when x"A6A" => DATA <= x"AC";
when x"A6B" => DATA <= x"FC";
when x"A6C" => DATA <= x"01";
when x"A6D" => DATA <= x"0C";
when x"A6E" => DATA <= x"00";
when x"A6F" => DATA <= x"09";
when x"A70" => DATA <= x"06";
when x"A71" => DATA <= x"0D";
when x"A72" => DATA <= x"CD";
when x"A73" => DATA <= x"9A";
when x"A74" => DATA <= x"F6";
when x"A75" => DATA <= x"77";
when x"A76" => DATA <= x"2B";
when x"A77" => DATA <= x"10";
when x"A78" => DATA <= x"F9";
when x"A79" => DATA <= x"2A";
when x"A7A" => DATA <= x"AC";
when x"A7B" => DATA <= x"FC";
when x"A7C" => DATA <= x"C1";
when x"A7D" => DATA <= x"C3";
when x"A7E" => DATA <= x"95";
when x"A7F" => DATA <= x"F6";
when x"A80" => DATA <= x"00";
when x"A81" => DATA <= x"00";
when x"A82" => DATA <= x"ED";
when x"A83" => DATA <= x"73";
when x"A84" => DATA <= x"80";
when x"A85" => DATA <= x"FA";
when x"A86" => DATA <= x"31";
when x"A87" => DATA <= x"60";
when x"A88" => DATA <= x"FF";
when x"A89" => DATA <= x"CD";
when x"A8A" => DATA <= x"93";
when x"A8B" => DATA <= x"FA";
when x"A8C" => DATA <= x"ED";
when x"A8D" => DATA <= x"7B";
when x"A8E" => DATA <= x"80";
when x"A8F" => DATA <= x"FA";
when x"A90" => DATA <= x"FB";
when x"A91" => DATA <= x"ED";
when x"A92" => DATA <= x"4D";
when x"A93" => DATA <= x"F5";
when x"A94" => DATA <= x"DB";
when x"A95" => DATA <= x"06";
when x"A96" => DATA <= x"CB";
when x"A97" => DATA <= x"7F";
when x"A98" => DATA <= x"20";
when x"A99" => DATA <= x"71";
when x"A9A" => DATA <= x"DB";
when x"A9B" => DATA <= x"00";
when x"A9C" => DATA <= x"CB";
when x"A9D" => DATA <= x"7F";
when x"A9E" => DATA <= x"20";
when x"A9F" => DATA <= x"39";
when x"AA0" => DATA <= x"F1";
when x"AA1" => DATA <= x"C3";
when x"AA2" => DATA <= x"B0";
when x"AA3" => DATA <= x"FF";
when x"AA4" => DATA <= x"E1";
when x"AA5" => DATA <= x"22";
when x"AA6" => DATA <= x"82";
when x"AA7" => DATA <= x"FF";
when x"AA8" => DATA <= x"2A";
when x"AA9" => DATA <= x"FA";
when x"AAA" => DATA <= x"FF";
when x"AAB" => DATA <= x"E9";
when x"AAC" => DATA <= x"CD";
when x"AAD" => DATA <= x"C6";
when x"AAE" => DATA <= x"FA";
when x"AAF" => DATA <= x"C3";
when x"AB0" => DATA <= x"CB";
when x"AB1" => DATA <= x"F2";
when x"AB2" => DATA <= x"3E";
when x"AB3" => DATA <= x"03";
when x"AB4" => DATA <= x"2E";
when x"AB5" => DATA <= x"00";
when x"AB6" => DATA <= x"CD";
when x"AB7" => DATA <= x"8E";
when x"AB8" => DATA <= x"F8";
when x"AB9" => DATA <= x"3E";
when x"ABA" => DATA <= x"02";
when x"ABB" => DATA <= x"2E";
when x"ABC" => DATA <= x"02";
when x"ABD" => DATA <= x"CD";
when x"ABE" => DATA <= x"8E";
when x"ABF" => DATA <= x"F8";
when x"AC0" => DATA <= x"CD";
when x"AC1" => DATA <= x"C6";
when x"AC2" => DATA <= x"FA";
when x"AC3" => DATA <= x"C3";
when x"AC4" => DATA <= x"00";
when x"AC5" => DATA <= x"00";
when x"AC6" => DATA <= x"2A";
when x"AC7" => DATA <= x"82";
when x"AC8" => DATA <= x"FF";
when x"AC9" => DATA <= x"3E";
when x"ACA" => DATA <= x"0D";
when x"ACB" => DATA <= x"CD";
when x"ACC" => DATA <= x"71";
when x"ACD" => DATA <= x"F6";
when x"ACE" => DATA <= x"3E";
when x"ACF" => DATA <= x"0A";
when x"AD0" => DATA <= x"CD";
when x"AD1" => DATA <= x"71";
when x"AD2" => DATA <= x"F6";
when x"AD3" => DATA <= x"23";
when x"AD4" => DATA <= x"7E";
when x"AD5" => DATA <= x"B7";
when x"AD6" => DATA <= x"20";
when x"AD7" => DATA <= x"F8";
when x"AD8" => DATA <= x"C9";
when x"AD9" => DATA <= x"DB";
when x"ADA" => DATA <= x"01";
when x"ADB" => DATA <= x"CB";
when x"ADC" => DATA <= x"7F";
when x"ADD" => DATA <= x"20";
when x"ADE" => DATA <= x"25";
when x"ADF" => DATA <= x"3E";
when x"AE0" => DATA <= x"01";
when x"AE1" => DATA <= x"32";
when x"AE2" => DATA <= x"A2";
when x"AE3" => DATA <= x"FC";
when x"AE4" => DATA <= x"E5";
when x"AE5" => DATA <= x"DD";
when x"AE6" => DATA <= x"E5";
when x"AE7" => DATA <= x"CD";
when x"AE8" => DATA <= x"7C";
when x"AE9" => DATA <= x"F6";
when x"AEA" => DATA <= x"67";
when x"AEB" => DATA <= x"CD";
when x"AEC" => DATA <= x"7C";
when x"AED" => DATA <= x"F6";
when x"AEE" => DATA <= x"6F";
when x"AEF" => DATA <= x"CD";
when x"AF0" => DATA <= x"7C";
when x"AF1" => DATA <= x"F6";
when x"AF2" => DATA <= x"CD";
when x"AF3" => DATA <= x"FE";
when x"AF4" => DATA <= x"FA";
when x"AF5" => DATA <= x"AF";
when x"AF6" => DATA <= x"32";
when x"AF7" => DATA <= x"A2";
when x"AF8" => DATA <= x"FC";
when x"AF9" => DATA <= x"DD";
when x"AFA" => DATA <= x"E1";
when x"AFB" => DATA <= x"E1";
when x"AFC" => DATA <= x"F1";
when x"AFD" => DATA <= x"C9";
when x"AFE" => DATA <= x"DD";
when x"AFF" => DATA <= x"2A";
when x"B00" => DATA <= x"FC";
when x"B01" => DATA <= x"FF";
when x"B02" => DATA <= x"DD";
when x"B03" => DATA <= x"E9";
when x"B04" => DATA <= x"CB";
when x"B05" => DATA <= x"27";
when x"B06" => DATA <= x"32";
when x"B07" => DATA <= x"80";
when x"B08" => DATA <= x"FF";
when x"B09" => DATA <= x"F1";
when x"B0A" => DATA <= x"C9";
when x"B0B" => DATA <= x"DB";
when x"B0C" => DATA <= x"07";
when x"B0D" => DATA <= x"CB";
when x"B0E" => DATA <= x"7F";
when x"B0F" => DATA <= x"28";
when x"B10" => DATA <= x"45";
when x"B11" => DATA <= x"DB";
when x"B12" => DATA <= x"02";
when x"B13" => DATA <= x"CB";
when x"B14" => DATA <= x"7F";
when x"B15" => DATA <= x"28";
when x"B16" => DATA <= x"FA";
when x"B17" => DATA <= x"DB";
when x"B18" => DATA <= x"03";
when x"B19" => DATA <= x"FB";
when x"B1A" => DATA <= x"21";
when x"B1B" => DATA <= x"B0";
when x"B1C" => DATA <= x"FC";
when x"B1D" => DATA <= x"36";
when x"B1E" => DATA <= x"CD";
when x"B1F" => DATA <= x"23";
when x"B20" => DATA <= x"3A";
when x"B21" => DATA <= x"BD";
when x"B22" => DATA <= x"FF";
when x"B23" => DATA <= x"77";
when x"B24" => DATA <= x"23";
when x"B25" => DATA <= x"3A";
when x"B26" => DATA <= x"BE";
when x"B27" => DATA <= x"FF";
when x"B28" => DATA <= x"77";
when x"B29" => DATA <= x"23";
when x"B2A" => DATA <= x"CD";
when x"B2B" => DATA <= x"9A";
when x"B2C" => DATA <= x"F6";
when x"B2D" => DATA <= x"77";
when x"B2E" => DATA <= x"B7";
when x"B2F" => DATA <= x"20";
when x"B30" => DATA <= x"1A";
when x"B31" => DATA <= x"CD";
when x"B32" => DATA <= x"0E";
when x"B33" => DATA <= x"F6";
when x"B34" => DATA <= x"0D";
when x"B35" => DATA <= x"46";
when x"B36" => DATA <= x"61";
when x"B37" => DATA <= x"74";
when x"B38" => DATA <= x"61";
when x"B39" => DATA <= x"6C";
when x"B3A" => DATA <= x"20";
when x"B3B" => DATA <= x"65";
when x"B3C" => DATA <= x"72";
when x"B3D" => DATA <= x"72";
when x"B3E" => DATA <= x"6F";
when x"B3F" => DATA <= x"72";
when x"B40" => DATA <= x"00";
when x"B41" => DATA <= x"3A";
when x"B42" => DATA <= x"A3";
when x"B43" => DATA <= x"FC";
when x"B44" => DATA <= x"B7";
when x"B45" => DATA <= x"C2";
when x"B46" => DATA <= x"00";
when x"B47" => DATA <= x"00";
when x"B48" => DATA <= x"C3";
when x"B49" => DATA <= x"CB";
when x"B4A" => DATA <= x"F2";
when x"B4B" => DATA <= x"23";
when x"B4C" => DATA <= x"CD";
when x"B4D" => DATA <= x"9A";
when x"B4E" => DATA <= x"F6";
when x"B4F" => DATA <= x"77";
when x"B50" => DATA <= x"B7";
when x"B51" => DATA <= x"20";
when x"B52" => DATA <= x"F8";
when x"B53" => DATA <= x"C3";
when x"B54" => DATA <= x"B0";
when x"B55" => DATA <= x"FC";
when x"B56" => DATA <= x"C5";
when x"B57" => DATA <= x"D5";
when x"B58" => DATA <= x"E5";
when x"B59" => DATA <= x"F5";
when x"B5A" => DATA <= x"07";
when x"B5B" => DATA <= x"5F";
when x"B5C" => DATA <= x"07";
when x"B5D" => DATA <= x"07";
when x"B5E" => DATA <= x"83";
when x"B5F" => DATA <= x"07";
when x"B60" => DATA <= x"5F";
when x"B61" => DATA <= x"16";
when x"B62" => DATA <= x"00";
when x"B63" => DATA <= x"21";
when x"B64" => DATA <= x"C1";
when x"B65" => DATA <= x"FB";
when x"B66" => DATA <= x"19";
when x"B67" => DATA <= x"11";
when x"B68" => DATA <= x"61";
when x"B69" => DATA <= x"FC";
when x"B6A" => DATA <= x"01";
when x"B6B" => DATA <= x"14";
when x"B6C" => DATA <= x"00";
when x"B6D" => DATA <= x"ED";
when x"B6E" => DATA <= x"B0";
when x"B6F" => DATA <= x"CD";
when x"B70" => DATA <= x"AE";
when x"B71" => DATA <= x"F6";
when x"B72" => DATA <= x"F1";
when x"B73" => DATA <= x"FE";
when x"B74" => DATA <= x"05";
when x"B75" => DATA <= x"28";
when x"B76" => DATA <= x"33";
when x"B77" => DATA <= x"F5";
when x"B78" => DATA <= x"CD";
when x"B79" => DATA <= x"AE";
when x"B7A" => DATA <= x"F6";
when x"B7B" => DATA <= x"CD";
when x"B7C" => DATA <= x"AE";
when x"B7D" => DATA <= x"F6";
when x"B7E" => DATA <= x"CD";
when x"B7F" => DATA <= x"AE";
when x"B80" => DATA <= x"F6";
when x"B81" => DATA <= x"67";
when x"B82" => DATA <= x"CD";
when x"B83" => DATA <= x"AE";
when x"B84" => DATA <= x"F6";
when x"B85" => DATA <= x"6F";
when x"B86" => DATA <= x"22";
when x"B87" => DATA <= x"A8";
when x"B88" => DATA <= x"FC";
when x"B89" => DATA <= x"0E";
when x"B8A" => DATA <= x"05";
when x"B8B" => DATA <= x"06";
when x"B8C" => DATA <= x"00";
when x"B8D" => DATA <= x"CD";
when x"B8E" => DATA <= x"AE";
when x"B8F" => DATA <= x"F6";
when x"B90" => DATA <= x"F1";
when x"B91" => DATA <= x"FE";
when x"B92" => DATA <= x"06";
when x"B93" => DATA <= x"38";
when x"B94" => DATA <= x"15";
when x"B95" => DATA <= x"20";
when x"B96" => DATA <= x"1D";
when x"B97" => DATA <= x"DB";
when x"B98" => DATA <= x"04";
when x"B99" => DATA <= x"B7";
when x"B9A" => DATA <= x"F2";
when x"B9B" => DATA <= x"97";
when x"B9C" => DATA <= x"FB";
when x"B9D" => DATA <= x"ED";
when x"B9E" => DATA <= x"A3";
when x"B9F" => DATA <= x"C2";
when x"BA0" => DATA <= x"97";
when x"BA1" => DATA <= x"FB";
when x"BA2" => DATA <= x"DB";
when x"BA3" => DATA <= x"04";
when x"BA4" => DATA <= x"B7";
when x"BA5" => DATA <= x"F2";
when x"BA6" => DATA <= x"A2";
when x"BA7" => DATA <= x"FB";
when x"BA8" => DATA <= x"D3";
when x"BA9" => DATA <= x"05";
when x"BAA" => DATA <= x"E1";
when x"BAB" => DATA <= x"D1";
when x"BAC" => DATA <= x"C1";
when x"BAD" => DATA <= x"3A";
when x"BAE" => DATA <= x"A2";
when x"BAF" => DATA <= x"FC";
when x"BB0" => DATA <= x"B7";
when x"BB1" => DATA <= x"C0";
when x"BB2" => DATA <= x"F1";
when x"BB3" => DATA <= x"C9";
when x"BB4" => DATA <= x"DB";
when x"BB5" => DATA <= x"04";
when x"BB6" => DATA <= x"B7";
when x"BB7" => DATA <= x"F2";
when x"BB8" => DATA <= x"B4";
when x"BB9" => DATA <= x"FB";
when x"BBA" => DATA <= x"ED";
when x"BBB" => DATA <= x"A2";
when x"BBC" => DATA <= x"C2";
when x"BBD" => DATA <= x"B4";
when x"BBE" => DATA <= x"FB";
when x"BBF" => DATA <= x"18";
when x"BC0" => DATA <= x"E9";
when x"BC1" => DATA <= x"E5";
when x"BC2" => DATA <= x"F5";
when x"BC3" => DATA <= x"2A";
when x"BC4" => DATA <= x"A8";
when x"BC5" => DATA <= x"FC";
when x"BC6" => DATA <= x"7E";
when x"BC7" => DATA <= x"D3";
when x"BC8" => DATA <= x"05";
when x"BC9" => DATA <= x"23";
when x"BCA" => DATA <= x"22";
when x"BCB" => DATA <= x"A8";
when x"BCC" => DATA <= x"FC";
when x"BCD" => DATA <= x"F1";
when x"BCE" => DATA <= x"E1";
when x"BCF" => DATA <= x"ED";
when x"BD0" => DATA <= x"45";
when x"BD1" => DATA <= x"3A";
when x"BD2" => DATA <= x"12";
when x"BD3" => DATA <= x"3B";
when x"BD4" => DATA <= x"B7";
when x"BD5" => DATA <= x"E5";
when x"BD6" => DATA <= x"F5";
when x"BD7" => DATA <= x"DB";
when x"BD8" => DATA <= x"05";
when x"BD9" => DATA <= x"2A";
when x"BDA" => DATA <= x"A8";
when x"BDB" => DATA <= x"FC";
when x"BDC" => DATA <= x"77";
when x"BDD" => DATA <= x"23";
when x"BDE" => DATA <= x"22";
when x"BDF" => DATA <= x"A8";
when x"BE0" => DATA <= x"FC";
when x"BE1" => DATA <= x"F1";
when x"BE2" => DATA <= x"E1";
when x"BE3" => DATA <= x"ED";
when x"BE4" => DATA <= x"45";
when x"BE5" => DATA <= x"01";
when x"BE6" => DATA <= x"3B";
when x"BE7" => DATA <= x"EB";
when x"BE8" => DATA <= x"CD";
when x"BE9" => DATA <= x"E5";
when x"BEA" => DATA <= x"F5";
when x"BEB" => DATA <= x"2A";
when x"BEC" => DATA <= x"A8";
when x"BED" => DATA <= x"FC";
when x"BEE" => DATA <= x"7E";
when x"BEF" => DATA <= x"D3";
when x"BF0" => DATA <= x"05";
when x"BF1" => DATA <= x"23";
when x"BF2" => DATA <= x"7E";
when x"BF3" => DATA <= x"D3";
when x"BF4" => DATA <= x"05";
when x"BF5" => DATA <= x"23";
when x"BF6" => DATA <= x"22";
when x"BF7" => DATA <= x"A8";
when x"BF8" => DATA <= x"FC";
when x"BF9" => DATA <= x"F1";
when x"BFA" => DATA <= x"E1";
when x"BFB" => DATA <= x"ED";
when x"BFC" => DATA <= x"45";
when x"BFD" => DATA <= x"E5";
when x"BFE" => DATA <= x"F5";
when x"BFF" => DATA <= x"DB";
when x"C00" => DATA <= x"05";
when x"C01" => DATA <= x"2A";
when x"C02" => DATA <= x"A8";
when x"C03" => DATA <= x"FC";
when x"C04" => DATA <= x"77";
when x"C05" => DATA <= x"23";
when x"C06" => DATA <= x"DB";
when x"C07" => DATA <= x"05";
when x"C08" => DATA <= x"77";
when x"C09" => DATA <= x"23";
when x"C0A" => DATA <= x"22";
when x"C0B" => DATA <= x"A8";
when x"C0C" => DATA <= x"FC";
when x"C0D" => DATA <= x"F1";
when x"C0E" => DATA <= x"E1";
when x"C0F" => DATA <= x"ED";
when x"C10" => DATA <= x"45";
when x"C11" => DATA <= x"D3";
when x"C12" => DATA <= x"05";
when x"C13" => DATA <= x"ED";
when x"C14" => DATA <= x"45";
when x"C15" => DATA <= x"23";
when x"C16" => DATA <= x"56";
when x"C17" => DATA <= x"2B";
when x"C18" => DATA <= x"C9";
when x"C19" => DATA <= x"2A";
when x"C1A" => DATA <= x"A0";
when x"C1B" => DATA <= x"3C";
when x"C1C" => DATA <= x"19";
when x"C1D" => DATA <= x"23";
when x"C1E" => DATA <= x"23";
when x"C1F" => DATA <= x"5E";
when x"C20" => DATA <= x"23";
when x"C21" => DATA <= x"56";
when x"C22" => DATA <= x"2B";
when x"C23" => DATA <= x"C9";
when x"C24" => DATA <= x"2A";
when x"C25" => DATA <= x"D3";
when x"C26" => DATA <= x"05";
when x"C27" => DATA <= x"ED";
when x"C28" => DATA <= x"45";
when x"C29" => DATA <= x"CA";
when x"C2A" => DATA <= x"0D";
when x"C2B" => DATA <= x"37";
when x"C2C" => DATA <= x"EB";
when x"C2D" => DATA <= x"D5";
when x"C2E" => DATA <= x"CD";
when x"C2F" => DATA <= x"ED";
when x"C30" => DATA <= x"36";
when x"C31" => DATA <= x"EB";
when x"C32" => DATA <= x"22";
when x"C33" => DATA <= x"A4";
when x"C34" => DATA <= x"3C";
when x"C35" => DATA <= x"D1";
when x"C36" => DATA <= x"C3";
when x"C37" => DATA <= x"39";
when x"C38" => DATA <= x"37";
when x"C39" => DATA <= x"D3";
when x"C3A" => DATA <= x"05";
when x"C3B" => DATA <= x"ED";
when x"C3C" => DATA <= x"45";
when x"C3D" => DATA <= x"20";
when x"C3E" => DATA <= x"00";
when x"C3F" => DATA <= x"EB";
when x"C40" => DATA <= x"19";
when x"C41" => DATA <= x"22";
when x"C42" => DATA <= x"A2";
when x"C43" => DATA <= x"3C";
when x"C44" => DATA <= x"D5";
when x"C45" => DATA <= x"EB";
when x"C46" => DATA <= x"2A";
when x"C47" => DATA <= x"AC";
when x"C48" => DATA <= x"3C";
when x"C49" => DATA <= x"CD";
when x"C4A" => DATA <= x"82";
when x"C4B" => DATA <= x"0D";
when x"C4C" => DATA <= x"D1";
when x"C4D" => DATA <= x"D3";
when x"C4E" => DATA <= x"05";
when x"C4F" => DATA <= x"ED";
when x"C50" => DATA <= x"45";
when x"C51" => DATA <= x"7B";
when x"C52" => DATA <= x"3C";
when x"C53" => DATA <= x"25";
when x"C54" => DATA <= x"3A";
when x"C55" => DATA <= x"7D";
when x"C56" => DATA <= x"3C";
when x"C57" => DATA <= x"B7";
when x"C58" => DATA <= x"CD";
when x"C59" => DATA <= x"82";
when x"C5A" => DATA <= x"0D";
when x"C5B" => DATA <= x"DA";
when x"C5C" => DATA <= x"87";
when x"C5D" => DATA <= x"38";
when x"C5E" => DATA <= x"2A";
when x"C5F" => DATA <= x"A0";
when x"C60" => DATA <= x"3C";
when x"C61" => DATA <= x"D3";
when x"C62" => DATA <= x"05";
when x"C63" => DATA <= x"ED";
when x"C64" => DATA <= x"45";
when x"C65" => DATA <= x"D5";
when x"C66" => DATA <= x"CD";
when x"C67" => DATA <= x"E4";
when x"C68" => DATA <= x"36";
when x"C69" => DATA <= x"EB";
when x"C6A" => DATA <= x"2A";
when x"C6B" => DATA <= x"A8";
when x"C6C" => DATA <= x"3C";
when x"C6D" => DATA <= x"EB";
when x"C6E" => DATA <= x"7B";
when x"C6F" => DATA <= x"E6";
when x"C70" => DATA <= x"E0";
when x"C71" => DATA <= x"5F";
when x"C72" => DATA <= x"7B";
when x"C73" => DATA <= x"B2";
when x"C74" => DATA <= x"C2";
when x"C75" => DATA <= x"00";
when x"C76" => DATA <= x"05";
when x"C77" => DATA <= x"00";
when x"C78" => DATA <= x"05";
when x"C79" => DATA <= x"04";
when x"C7A" => DATA <= x"05";
when x"C7B" => DATA <= x"08";
when x"C7C" => DATA <= x"0E";
when x"C7D" => DATA <= x"04";
when x"C7E" => DATA <= x"01";
when x"C7F" => DATA <= x"01";
when x"C80" => DATA <= x"05";
when x"C81" => DATA <= x"00";
when x"C82" => DATA <= x"20";
when x"C83" => DATA <= x"20";
when x"C84" => DATA <= x"10";
when x"C85" => DATA <= x"0D";
when x"C86" => DATA <= x"00";
when x"C87" => DATA <= x"08";
when x"C88" => DATA <= x"80";
when x"C89" => DATA <= x"05";
when x"C8A" => DATA <= x"00";
when x"C8B" => DATA <= x"05";
when x"C8C" => DATA <= x"00";
when x"C8D" => DATA <= x"05";
when x"C8E" => DATA <= x"00";
when x"C8F" => DATA <= x"00";
when x"C90" => DATA <= x"00";
when x"C91" => DATA <= x"05";
when x"C92" => DATA <= x"09";
when x"C93" => DATA <= x"05";
when x"C94" => DATA <= x"00";
when x"C95" => DATA <= x"08";
when x"C96" => DATA <= x"20";
when x"C97" => DATA <= x"10";
when x"C98" => DATA <= x"01";
when x"C99" => DATA <= x"0D";
when x"C9A" => DATA <= x"80";
when x"C9B" => DATA <= x"08";
when x"C9C" => DATA <= x"80";
when x"C9D" => DATA <= x"B0";
when x"C9E" => DATA <= x"FC";
when x"C9F" => DATA <= x"80";
when x"CA0" => DATA <= x"20";
when x"CA1" => DATA <= x"FF";
when x"CA2" => DATA <= x"00";
when x"CA3" => DATA <= x"00";
when x"CA4" => DATA <= x"00";
when x"CA5" => DATA <= x"D5";
when x"CA6" => DATA <= x"F5";
when x"CA7" => DATA <= x"2A";
when x"CA8" => DATA <= x"A8";
when x"CA9" => DATA <= x"FC";
when x"CAA" => DATA <= x"00";
when x"CAB" => DATA <= x"00";
when x"CAC" => DATA <= x"B0";
when x"CAD" => DATA <= x"FC";
when x"CAE" => DATA <= x"00";
when x"CAF" => DATA <= x"00";
when x"CB0" => DATA <= x"36";
when x"CB1" => DATA <= x"2A";
when x"CB2" => DATA <= x"A0";
when x"CB3" => DATA <= x"3C";
when x"CB4" => DATA <= x"19";
when x"CB5" => DATA <= x"F1";
when x"CB6" => DATA <= x"F5";
when x"CB7" => DATA <= x"77";
when x"CB8" => DATA <= x"7B";
when x"CB9" => DATA <= x"E6";
when x"CBA" => DATA <= x"1F";
when x"CBB" => DATA <= x"FE";
when x"CBC" => DATA <= x"1F";
when x"CBD" => DATA <= x"CA";
when x"CBE" => DATA <= x"95";
when x"CBF" => DATA <= x"37";
when x"CC0" => DATA <= x"13";
when x"CC1" => DATA <= x"CC";
when x"CC2" => DATA <= x"9F";
when x"CC3" => DATA <= x"37";
when x"CC4" => DATA <= x"EB";
when x"CC5" => DATA <= x"22";
when x"CC6" => DATA <= x"A8";
when x"CC7" => DATA <= x"3C";
when x"CC8" => DATA <= x"F1";
when x"CC9" => DATA <= x"D1";
when x"CCA" => DATA <= x"C9";
when x"CCB" => DATA <= x"7B";
when x"CCC" => DATA <= x"E6";
when x"CCD" => DATA <= x"E0";
when x"CCE" => DATA <= x"5F";
when x"CCF" => DATA <= x"CD";
when x"CD0" => DATA <= x"ED";
when x"CD1" => DATA <= x"36";
when x"CD2" => DATA <= x"7A";
when x"CD3" => DATA <= x"B3";
when x"CD4" => DATA <= x"CA";
when x"CD5" => DATA <= x"F8";
when x"CD6" => DATA <= x"36";
when x"CD7" => DATA <= x"13";
when x"CD8" => DATA <= x"13";
when x"CD9" => DATA <= x"13";
when x"CDA" => DATA <= x"13";
when x"CDB" => DATA <= x"C9";
when x"CDC" => DATA <= x"D5";
when x"CDD" => DATA <= x"EB";
when x"CDE" => DATA <= x"2A";
when x"CDF" => DATA <= x"A0";
when x"CE0" => DATA <= x"3C";
when x"CE1" => DATA <= x"EB";
when x"CE2" => DATA <= x"7D";
when x"CE3" => DATA <= x"E6";
when x"CE4" => DATA <= x"1F";
when x"CE5" => DATA <= x"C2";
when x"CE6" => DATA <= x"C0";
when x"CE7" => DATA <= x"37";
when x"CE8" => DATA <= x"7D";
when x"CE9" => DATA <= x"F6";
when x"CEA" => DATA <= x"04";
when x"CEB" => DATA <= x"6F";
when x"CEC" => DATA <= x"EB";
when x"CED" => DATA <= x"19";
when x"CEE" => DATA <= x"7E";
when x"CEF" => DATA <= x"EB";
when x"CF0" => DATA <= x"D1";
when x"CF1" => DATA <= x"C9";
when x"CF2" => DATA <= x"CD";
when x"CF3" => DATA <= x"B0";
when x"CF4" => DATA <= x"37";
when x"CF5" => DATA <= x"F5";
when x"CF6" => DATA <= x"D5";
when x"CF7" => DATA <= x"EB";
when x"CF8" => DATA <= x"7B";
when x"CF9" => DATA <= x"E6";
when x"CFA" => DATA <= x"1F";
when x"CFB" => DATA <= x"FE";
when x"CFC" => DATA <= x"1F";
when x"CFD" => DATA <= x"CA";
when x"CFE" => DATA <= x"D5";
when x"CFF" => DATA <= x"37";
when x"D00" => DATA <= x"13";
when x"D01" => DATA <= x"CC";
when x"D02" => DATA <= x"9F";
when x"D03" => DATA <= x"37";
when x"D04" => DATA <= x"EB";
when x"D05" => DATA <= x"D1";
when x"D06" => DATA <= x"F1";
when x"D07" => DATA <= x"C9";
when x"D08" => DATA <= x"EB";
when x"D09" => DATA <= x"7B";
when x"D0A" => DATA <= x"E6";
when x"D0B" => DATA <= x"E0";
when x"D0C" => DATA <= x"5F";
when x"D0D" => DATA <= x"D5";
when x"D0E" => DATA <= x"CD";
when x"D0F" => DATA <= x"ED";
when x"D10" => DATA <= x"36";
when x"D11" => DATA <= x"7B";
when x"D12" => DATA <= x"B2";
when x"D13" => DATA <= x"C1";
when x"D14" => DATA <= x"C8";
when x"D15" => DATA <= x"AF";
when x"D16" => DATA <= x"77";
when x"D17" => DATA <= x"23";
when x"D18" => DATA <= x"77";
when x"D19" => DATA <= x"2A";
when x"D1A" => DATA <= x"A0";
when x"D1B" => DATA <= x"3C";
when x"D1C" => DATA <= x"19";
when x"D1D" => DATA <= x"73";
when x"D1E" => DATA <= x"23";
when x"D1F" => DATA <= x"72";
when x"D20" => DATA <= x"C5";
when x"D21" => DATA <= x"CD";
when x"D22" => DATA <= x"D2";
when x"D23" => DATA <= x"36";
when x"D24" => DATA <= x"C1";
when x"D25" => DATA <= x"2A";
when x"D26" => DATA <= x"A6";
when x"D27" => DATA <= x"3C";
when x"D28" => DATA <= x"EB";
when x"D29" => DATA <= x"CD";
when x"D2A" => DATA <= x"E4";
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when x"D2C" => DATA <= x"71";
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when x"D2F" => DATA <= x"C9";
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when x"D31" => DATA <= x"05";
when x"D32" => DATA <= x"25";
when x"D33" => DATA <= x"10";
when x"D34" => DATA <= x"E3";
when x"D35" => DATA <= x"C9";
when x"D36" => DATA <= x"FF";
when x"D37" => DATA <= x"F0";
when x"D38" => DATA <= x"03";
when x"D39" => DATA <= x"6C";
when x"D3A" => DATA <= x"03";
when x"D3B" => DATA <= x"25";
when x"D3C" => DATA <= x"86";
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when x"D3E" => DATA <= x"84";
when x"D3F" => DATA <= x"71";
when x"D40" => DATA <= x"85";
when x"D41" => DATA <= x"72";
when x"D42" => DATA <= x"A0";
when x"D43" => DATA <= x"02";
when x"D44" => DATA <= x"B1";
when x"D45" => DATA <= x"70";
when x"D46" => DATA <= x"85";
when x"D47" => DATA <= x"74";
when x"D48" => DATA <= x"C8";
when x"D49" => DATA <= x"B1";
when x"D4A" => DATA <= x"70";
when x"D4B" => DATA <= x"85";
when x"D4C" => DATA <= x"75";
when x"D4D" => DATA <= x"20";
when x"D4E" => DATA <= x"9C";
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when x"D50" => DATA <= x"A0";
when x"D51" => DATA <= x"0C";
when x"D52" => DATA <= x"B1";
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when x"D54" => DATA <= x"48";
when x"D55" => DATA <= x"A5";
when x"D56" => DATA <= x"70";
when x"D57" => DATA <= x"18";
when x"D58" => DATA <= x"69";
when x"D59" => DATA <= x"06";
when x"D5A" => DATA <= x"AA";
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when x"D5C" => DATA <= x"00";
when x"D5D" => DATA <= x"65";
when x"D5E" => DATA <= x"71";
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when x"D61" => DATA <= x"48";
when x"D62" => DATA <= x"20";
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when x"D64" => DATA <= x"04";
when x"D65" => DATA <= x"A0";
when x"D66" => DATA <= x"0A";
when x"D67" => DATA <= x"B1";
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when x"D69" => DATA <= x"AA";
when x"D6A" => DATA <= x"C8";
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when x"D6D" => DATA <= x"85";
when x"D6E" => DATA <= x"76";
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when x"D75" => DATA <= x"F0";
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when x"D79" => DATA <= x"68";
when x"D7A" => DATA <= x"6A";
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when x"D7C" => DATA <= x"28";
when x"D7D" => DATA <= x"20";
when x"D7E" => DATA <= x"9B";
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when x"D80" => DATA <= x"20";
when x"D81" => DATA <= x"9B";
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when x"D83" => DATA <= x"20";
when x"D84" => DATA <= x"9B";
when x"D85" => DATA <= x"25";
when x"D86" => DATA <= x"A0";
when x"D87" => DATA <= x"00";
when x"D88" => DATA <= x"AD";
when x"D89" => DATA <= x"E5";
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when x"D8B" => DATA <= x"91";
when x"D8C" => DATA <= x"74";
when x"D8D" => DATA <= x"20";
when x"D8E" => DATA <= x"9B";
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when x"D90" => DATA <= x"20";
when x"D91" => DATA <= x"9B";
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when x"D93" => DATA <= x"20";
when x"D94" => DATA <= x"9B";
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when x"D96" => DATA <= x"E6";
when x"D97" => DATA <= x"74";
when x"D98" => DATA <= x"D0";
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when x"D9A" => DATA <= x"E6";
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when x"D9C" => DATA <= x"CA";
when x"D9D" => DATA <= x"D0";
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when x"D9F" => DATA <= x"C6";
when x"DA0" => DATA <= x"76";
when x"DA1" => DATA <= x"D0";
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when x"DA3" => DATA <= x"F0";
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when x"DA5" => DATA <= x"A0";
when x"DA6" => DATA <= x"00";
when x"DA7" => DATA <= x"B1";
when x"DA8" => DATA <= x"74";
when x"DA9" => DATA <= x"8D";
when x"DAA" => DATA <= x"E5";
when x"DAB" => DATA <= x"FE";
when x"DAC" => DATA <= x"20";
when x"DAD" => DATA <= x"9B";
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when x"DAF" => DATA <= x"20";
when x"DB0" => DATA <= x"9B";
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when x"DB2" => DATA <= x"20";
when x"DB3" => DATA <= x"9B";
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when x"DB6" => DATA <= x"74";
when x"DB7" => DATA <= x"D0";
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when x"DBC" => DATA <= x"D0";
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when x"DC0" => DATA <= x"D0";
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when x"DCA" => DATA <= x"72";
when x"DCB" => DATA <= x"60";
when x"DCC" => DATA <= x"A9";
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when x"DCE" => DATA <= x"20";
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when x"DD0" => DATA <= x"04";
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when x"DD2" => DATA <= x"F9";
when x"DD3" => DATA <= x"60";
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when x"DDD" => DATA <= x"42";
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when x"DED" => DATA <= x"81";
when x"DEE" => DATA <= x"FF";
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when x"DF4" => DATA <= x"F6";
when x"DF5" => DATA <= x"22";
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when x"DFD" => DATA <= x"22";
when x"DFE" => DATA <= x"9F";
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when x"E00" => DATA <= x"3A";
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when x"E05" => DATA <= x"FF";
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when x"E1D" => DATA <= x"C9";
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when x"E30" => DATA <= x"FE";
when x"E31" => DATA <= x"79";
when x"E32" => DATA <= x"FE";
when x"E33" => DATA <= x"3D";
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when x"E35" => DATA <= x"15";
when x"E36" => DATA <= x"FE";
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when x"E39" => DATA <= x"1A";
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when x"E3B" => DATA <= x"3F";
when x"E3C" => DATA <= x"28";
when x"E3D" => DATA <= x"1F";
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when x"E3F" => DATA <= x"40";
when x"E40" => DATA <= x"28";
when x"E41" => DATA <= x"3E";
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when x"E43" => DATA <= x"81";
when x"E44" => DATA <= x"FF";
when x"E45" => DATA <= x"CB";
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when x"E48" => DATA <= x"81";
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when x"E4C" => DATA <= x"81";
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when x"E50" => DATA <= x"32";
when x"E51" => DATA <= x"81";
when x"E52" => DATA <= x"FF";
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when x"E54" => DATA <= x"3A";
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when x"E56" => DATA <= x"FF";
when x"E57" => DATA <= x"CB";
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when x"E59" => DATA <= x"32";
when x"E5A" => DATA <= x"81";
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when x"E5C" => DATA <= x"C9";
when x"E5D" => DATA <= x"CD";
when x"E5E" => DATA <= x"EC";
when x"E5F" => DATA <= x"FE";
when x"E60" => DATA <= x"28";
when x"E61" => DATA <= x"08";
when x"E62" => DATA <= x"FE";
when x"E63" => DATA <= x"00";
when x"E64" => DATA <= x"20";
when x"E65" => DATA <= x"DC";
when x"E66" => DATA <= x"3E";
when x"E67" => DATA <= x"1F";
when x"E68" => DATA <= x"18";
when x"E69" => DATA <= x"02";
when x"E6A" => DATA <= x"3E";
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when x"E6C" => DATA <= x"32";
when x"E6D" => DATA <= x"18";
when x"E6E" => DATA <= x"FF";
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when x"E70" => DATA <= x"F5";
when x"E71" => DATA <= x"FE";
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when x"E73" => DATA <= x"10";
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when x"E75" => DATA <= x"10";
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when x"E79" => DATA <= x"71";
when x"E7A" => DATA <= x"F6";
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when x"E7C" => DATA <= x"10";
when x"E7D" => DATA <= x"F9";
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when x"E7F" => DATA <= x"C2";
when x"E80" => DATA <= x"CD";
when x"E81" => DATA <= x"EC";
when x"E82" => DATA <= x"FE";
when x"E83" => DATA <= x"28";
when x"E84" => DATA <= x"04";
when x"E85" => DATA <= x"FE";
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when x"E87" => DATA <= x"20";
when x"E88" => DATA <= x"B9";
when x"E89" => DATA <= x"CD";
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when x"E8B" => DATA <= x"FE";
when x"E8C" => DATA <= x"06";
when x"E8D" => DATA <= x"06";
when x"E8E" => DATA <= x"21";
when x"E8F" => DATA <= x"10";
when x"E90" => DATA <= x"FF";
when x"E91" => DATA <= x"7E";
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when x"E93" => DATA <= x"71";
when x"E94" => DATA <= x"F6";
when x"E95" => DATA <= x"23";
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when x"E97" => DATA <= x"F9";
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when x"E99" => DATA <= x"05";
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when x"E9B" => DATA <= x"1B";
when x"E9C" => DATA <= x"FF";
when x"E9D" => DATA <= x"7E";
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when x"E9F" => DATA <= x"71";
when x"EA0" => DATA <= x"F6";
when x"EA1" => DATA <= x"23";
when x"EA2" => DATA <= x"10";
when x"EA3" => DATA <= x"F9";
when x"EA4" => DATA <= x"18";
when x"EA5" => DATA <= x"9C";
when x"EA6" => DATA <= x"CB";
when x"EA7" => DATA <= x"67";
when x"EA8" => DATA <= x"20";
when x"EA9" => DATA <= x"0F";
when x"EAA" => DATA <= x"79";
when x"EAB" => DATA <= x"D6";
when x"EAC" => DATA <= x"20";
when x"EAD" => DATA <= x"32";
when x"EAE" => DATA <= x"21";
when x"EAF" => DATA <= x"FF";
when x"EB0" => DATA <= x"3A";
when x"EB1" => DATA <= x"81";
when x"EB2" => DATA <= x"FF";
when x"EB3" => DATA <= x"CB";
when x"EB4" => DATA <= x"E7";
when x"EB5" => DATA <= x"32";
when x"EB6" => DATA <= x"81";
when x"EB7" => DATA <= x"FF";
when x"EB8" => DATA <= x"C9";
when x"EB9" => DATA <= x"79";
when x"EBA" => DATA <= x"D6";
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when x"EBC" => DATA <= x"32";
when x"EBD" => DATA <= x"20";
when x"EBE" => DATA <= x"FF";
when x"EBF" => DATA <= x"3E";
when x"EC0" => DATA <= x"1F";
when x"EC1" => DATA <= x"CD";
when x"EC2" => DATA <= x"71";
when x"EC3" => DATA <= x"F6";
when x"EC4" => DATA <= x"3A";
when x"EC5" => DATA <= x"20";
when x"EC6" => DATA <= x"FF";
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when x"EC8" => DATA <= x"71";
when x"EC9" => DATA <= x"F6";
when x"ECA" => DATA <= x"3A";
when x"ECB" => DATA <= x"21";
when x"ECC" => DATA <= x"FF";
when x"ECD" => DATA <= x"CD";
when x"ECE" => DATA <= x"71";
when x"ECF" => DATA <= x"F6";
when x"ED0" => DATA <= x"3A";
when x"ED1" => DATA <= x"81";
when x"ED2" => DATA <= x"FF";
when x"ED3" => DATA <= x"E6";
when x"ED4" => DATA <= x"01";
when x"ED5" => DATA <= x"32";
when x"ED6" => DATA <= x"81";
when x"ED7" => DATA <= x"FF";
when x"ED8" => DATA <= x"C9";
when x"ED9" => DATA <= x"79";
when x"EDA" => DATA <= x"B7";
when x"EDB" => DATA <= x"28";
when x"EDC" => DATA <= x"06";
when x"EDD" => DATA <= x"D6";
when x"EDE" => DATA <= x"20";
when x"EDF" => DATA <= x"CD";
when x"EE0" => DATA <= x"71";
when x"EE1" => DATA <= x"F6";
when x"EE2" => DATA <= x"C9";
when x"EE3" => DATA <= x"3A";
when x"EE4" => DATA <= x"81";
when x"EE5" => DATA <= x"FF";
when x"EE6" => DATA <= x"E6";
when x"EE7" => DATA <= x"01";
when x"EE8" => DATA <= x"32";
when x"EE9" => DATA <= x"81";
when x"EEA" => DATA <= x"FF";
when x"EEB" => DATA <= x"C9";
when x"EEC" => DATA <= x"3E";
when x"EED" => DATA <= x"87";
when x"EEE" => DATA <= x"CD";
when x"EEF" => DATA <= x"8E";
when x"EF0" => DATA <= x"F8";
when x"EF1" => DATA <= x"7C";
when x"EF2" => DATA <= x"FE";
when x"EF3" => DATA <= x"03";
when x"EF4" => DATA <= x"C9";
when x"EF5" => DATA <= x"3E";
when x"EF6" => DATA <= x"86";
when x"EF7" => DATA <= x"CD";
when x"EF8" => DATA <= x"8E";
when x"EF9" => DATA <= x"F8";
when x"EFA" => DATA <= x"7D";
when x"EFB" => DATA <= x"32";
when x"EFC" => DATA <= x"11";
when x"EFD" => DATA <= x"FF";
when x"EFE" => DATA <= x"32";
when x"EFF" => DATA <= x"1E";
when x"F00" => DATA <= x"FF";
when x"F01" => DATA <= x"7C";
when x"F02" => DATA <= x"32";
when x"F03" => DATA <= x"12";
when x"F04" => DATA <= x"FF";
when x"F05" => DATA <= x"32";
when x"F06" => DATA <= x"14";
when x"F07" => DATA <= x"FF";
when x"F08" => DATA <= x"32";
when x"F09" => DATA <= x"1F";
when x"F0A" => DATA <= x"FF";
when x"F0B" => DATA <= x"3C";
when x"F0C" => DATA <= x"32";
when x"F0D" => DATA <= x"1A";
when x"F0E" => DATA <= x"FF";
when x"F0F" => DATA <= x"C9";
when x"F10" => DATA <= x"1C";
when x"F11" => DATA <= x"C4";
when x"F12" => DATA <= x"48";
when x"F13" => DATA <= x"4F";
when x"F14" => DATA <= x"C1";
when x"F15" => DATA <= x"0C";
when x"F16" => DATA <= x"1C";
when x"F17" => DATA <= x"00";
when x"F18" => DATA <= x"1F";
when x"F19" => DATA <= x"4F";
when x"F1A" => DATA <= x"48";
when x"F1B" => DATA <= x"0C";
when x"F1C" => DATA <= x"1A";
when x"F1D" => DATA <= x"1F";
when x"F1E" => DATA <= x"22";
when x"F1F" => DATA <= x"28";
when x"F20" => DATA <= x"00";
when x"F21" => DATA <= x"00";
when x"F22" => DATA <= x"00";
when x"F23" => DATA <= x"28";
when x"F24" => DATA <= x"43";
when x"F25" => DATA <= x"29";
when x"F26" => DATA <= x"3B";
when x"F27" => DATA <= x"36";
when x"F28" => DATA <= x"00";
when x"F29" => DATA <= x"21";
when x"F2A" => DATA <= x"2A";
when x"F2B" => DATA <= x"3B";
when x"F2C" => DATA <= x"C3";
when x"F2D" => DATA <= x"77";
when x"F2E" => DATA <= x"19";
when x"F2F" => DATA <= x"C5";
when x"F30" => DATA <= x"E5";
when x"F31" => DATA <= x"7E";
when x"F32" => DATA <= x"E6";
when x"F33" => DATA <= x"03";
when x"F34" => DATA <= x"47";
when x"F35" => DATA <= x"0E";
when x"F36" => DATA <= x"06";
when x"F37" => DATA <= x"23";
when x"F38" => DATA <= x"5E";
when x"F39" => DATA <= x"23";
when x"F3A" => DATA <= x"56";
when x"F3B" => DATA <= x"CD";
when x"F3C" => DATA <= x"48";
when x"F3D" => DATA <= x"1A";
when x"F3E" => DATA <= x"E1";
when x"F3F" => DATA <= x"C1";
when x"F40" => DATA <= x"C9";
when x"F41" => DATA <= x"53";
when x"F42" => DATA <= x"00";
when x"F43" => DATA <= x"00";
when x"F44" => DATA <= x"00";
when x"F45" => DATA <= x"00";
when x"F46" => DATA <= x"00";
when x"F47" => DATA <= x"02";
when x"F48" => DATA <= x"00";
when x"F49" => DATA <= x"00";
when x"F4A" => DATA <= x"00";
when x"F4B" => DATA <= x"00";
when x"F4C" => DATA <= x"0A";
when x"F4D" => DATA <= x"00";
when x"F4E" => DATA <= x"00";
when x"F4F" => DATA <= x"00";
when x"F50" => DATA <= x"00";
when x"F51" => DATA <= x"00";
when x"F52" => DATA <= x"00";
when x"F53" => DATA <= x"00";
when x"F54" => DATA <= x"00";
when x"F55" => DATA <= x"00";
when x"F56" => DATA <= x"00";
when x"F57" => DATA <= x"00";
when x"F58" => DATA <= x"00";
when x"F59" => DATA <= x"00";
when x"F5A" => DATA <= x"00";
when x"F5B" => DATA <= x"00";
when x"F5C" => DATA <= x"00";
when x"F5D" => DATA <= x"00";
when x"F5E" => DATA <= x"00";
when x"F5F" => DATA <= x"00";
when x"F60" => DATA <= x"00";
when x"F61" => DATA <= x"00";
when x"F62" => DATA <= x"00";
when x"F63" => DATA <= x"00";
when x"F64" => DATA <= x"00";
when x"F65" => DATA <= x"00";
when x"F66" => DATA <= x"00";
when x"F67" => DATA <= x"00";
when x"F68" => DATA <= x"00";
when x"F69" => DATA <= x"00";
when x"F6A" => DATA <= x"00";
when x"F6B" => DATA <= x"00";
when x"F6C" => DATA <= x"00";
when x"F6D" => DATA <= x"00";
when x"F6E" => DATA <= x"00";
when x"F6F" => DATA <= x"00";
when x"F70" => DATA <= x"00";
when x"F71" => DATA <= x"00";
when x"F72" => DATA <= x"00";
when x"F73" => DATA <= x"00";
when x"F74" => DATA <= x"00";
when x"F75" => DATA <= x"00";
when x"F76" => DATA <= x"00";
when x"F77" => DATA <= x"00";
when x"F78" => DATA <= x"00";
when x"F79" => DATA <= x"00";
when x"F7A" => DATA <= x"00";
when x"F7B" => DATA <= x"00";
when x"F7C" => DATA <= x"00";
when x"F7D" => DATA <= x"00";
when x"F7E" => DATA <= x"00";
when x"F7F" => DATA <= x"00";
when x"F80" => DATA <= x"00";
when x"F81" => DATA <= x"00";
when x"F82" => DATA <= x"00";
when x"F83" => DATA <= x"01";
when x"F84" => DATA <= x"B2";
when x"F85" => DATA <= x"FA";
when x"F86" => DATA <= x"02";
when x"F87" => DATA <= x"14";
when x"F88" => DATA <= x"95";
when x"F89" => DATA <= x"00";
when x"F8A" => DATA <= x"01";
when x"F8B" => DATA <= x"00";
when x"F8C" => DATA <= x"00";
when x"F8D" => DATA <= x"3C";
when x"F8E" => DATA <= x"1A";
when x"F8F" => DATA <= x"FF";
when x"F90" => DATA <= x"FF";
when x"F91" => DATA <= x"01";
when x"F92" => DATA <= x"00";
when x"F93" => DATA <= x"00";
when x"F94" => DATA <= x"00";
when x"F95" => DATA <= x"00";
when x"F96" => DATA <= x"00";
when x"F97" => DATA <= x"00";
when x"F98" => DATA <= x"00";
when x"F99" => DATA <= x"00";
when x"F9A" => DATA <= x"74";
when x"F9B" => DATA <= x"4C";
when x"F9C" => DATA <= x"D6";
when x"F9D" => DATA <= x"5E";
when x"F9E" => DATA <= x"C3";
when x"F9F" => DATA <= x"71";
when x"FA0" => DATA <= x"F6";
when x"FA1" => DATA <= x"C3";
when x"FA2" => DATA <= x"AE";
when x"FA3" => DATA <= x"F5";
when x"FA4" => DATA <= x"C3";
when x"FA5" => DATA <= x"5C";
when x"FA6" => DATA <= x"F5";
when x"FA7" => DATA <= x"C3";
when x"FA8" => DATA <= x"3B";
when x"FA9" => DATA <= x"F5";
when x"FAA" => DATA <= x"C3";
when x"FAB" => DATA <= x"76";
when x"FAC" => DATA <= x"F4";
when x"FAD" => DATA <= x"C3";
when x"FAE" => DATA <= x"71";
when x"FAF" => DATA <= x"F4";
when x"FB0" => DATA <= x"C3";
when x"FB1" => DATA <= x"FD";
when x"FB2" => DATA <= x"FA";
when x"FB3" => DATA <= x"C3";
when x"FB4" => DATA <= x"0E";
when x"FB5" => DATA <= x"F6";
when x"FB6" => DATA <= x"C3";
when x"FB7" => DATA <= x"0E";
when x"FB8" => DATA <= x"FE";
when x"FB9" => DATA <= x"C3";
when x"FBA" => DATA <= x"CE";
when x"FBB" => DATA <= x"F2";
when x"FBC" => DATA <= x"C3";
when x"FBD" => DATA <= x"A4";
when x"FBE" => DATA <= x"FA";
when x"FBF" => DATA <= x"C3";
when x"FC0" => DATA <= x"5E";
when x"FC1" => DATA <= x"F6";
when x"FC2" => DATA <= x"C3";
when x"FC3" => DATA <= x"1B";
when x"FC4" => DATA <= x"F6";
when x"FC5" => DATA <= x"C3";
when x"FC6" => DATA <= x"3F";
when x"FC7" => DATA <= x"F6";
when x"FC8" => DATA <= x"C3";
when x"FC9" => DATA <= x"DE";
when x"FCA" => DATA <= x"FD";
when x"FCB" => DATA <= x"C3";
when x"FCC" => DATA <= x"E8";
when x"FCD" => DATA <= x"F8";
when x"FCE" => DATA <= x"C3";
when x"FCF" => DATA <= x"D2";
when x"FD0" => DATA <= x"F9";
when x"FD1" => DATA <= x"C3";
when x"FD2" => DATA <= x"4E";
when x"FD3" => DATA <= x"FA";
when x"FD4" => DATA <= x"C3";
when x"FD5" => DATA <= x"FC";
when x"FD6" => DATA <= x"F9";
when x"FD7" => DATA <= x"C3";
when x"FD8" => DATA <= x"F0";
when x"FD9" => DATA <= x"F9";
when x"FDA" => DATA <= x"C3";
when x"FDB" => DATA <= x"9F";
when x"FDC" => DATA <= x"F9";
when x"FDD" => DATA <= x"C3";
when x"FDE" => DATA <= x"10";
when x"FDF" => DATA <= x"FA";
when x"FE0" => DATA <= x"C3";
when x"FE1" => DATA <= x"90";
when x"FE2" => DATA <= x"F6";
when x"FE3" => DATA <= x"FE";
when x"FE4" => DATA <= x"0D";
when x"FE5" => DATA <= x"20";
when x"FE6" => DATA <= x"07";
when x"FE7" => DATA <= x"3E";
when x"FE8" => DATA <= x"0A";
when x"FE9" => DATA <= x"CD";
when x"FEA" => DATA <= x"EE";
when x"FEB" => DATA <= x"FF";
when x"FEC" => DATA <= x"3E";
when x"FED" => DATA <= x"0D";
when x"FEE" => DATA <= x"C3";
when x"FEF" => DATA <= x"71";
when x"FF0" => DATA <= x"F6";
when x"FF1" => DATA <= x"C3";
when x"FF2" => DATA <= x"EF";
when x"FF3" => DATA <= x"F8";
when x"FF4" => DATA <= x"C3";
when x"FF5" => DATA <= x"8E";
when x"FF6" => DATA <= x"F8";
when x"FF7" => DATA <= x"C3";
when x"FF8" => DATA <= x"B7";
when x"FF9" => DATA <= x"F6";
when x"FFA" => DATA <= x"AC";
when x"FFB" => DATA <= x"FA";
when x"FFC" => DATA <= x"70";
when x"FFD" => DATA <= x"F6";
when x"FFE" => DATA <= x"82";
when x"FFF" => DATA <= x"FA";
when others => DATA <= (others => '0');
end case;
end process;
end RTL;
| gpl-3.0 | f5a3ff43ce2c1298a1fd356b14d754b7 | 0.357933 | 2.931209 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/leon3v3/leon3cg.vhd | 1 | 6,994 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: leon3cg
-- File: leon3cg.vhd
-- Author: Jan Andersson, Aeroflex Gaisler
-- Description: Top-level LEON3 component with clock gating
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.leon3.all;
entity leon3cg is
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 31 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 128 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0; -- support SMP systems
cached : integer := 0; -- cacheability table
scantest : integer := 0;
mmupgsz : integer range 0 to 5 := 0;
bp : integer := 1;
npasi : integer range 0 to 1 := 0;
pwrpsr : integer range 0 to 1 := 0;
rex : integer range 0 to 1 := 0;
altwin : integer range 0 to 1 := 0
);
port (
clk : in std_ulogic; -- AHB clock (free-running)
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
gclk : in std_ulogic -- gated clock
);
end;
architecture rtl of leon3cg is
signal gnd, vcc : std_logic;
signal fpuo : grfpu_out_type;
begin
gnd <= '0'; vcc <= '1';
fpuo <= grfpu_out_none;
leon3x0 : leon3x
generic map (
hindex => hindex,
fabtech => fabtech,
memtech => memtech,
nwindows => nwindows,
dsu => dsu,
fpu => fpu,
v8 => v8,
cp => cp,
mac => mac,
pclow => pclow,
notag => notag,
nwp => nwp,
icen => icen,
irepl => irepl,
isets => isets,
ilinesize => ilinesize,
isetsize => isetsize,
isetlock => isetlock,
dcen => dcen,
drepl => drepl,
dsets => dsets,
dlinesize => dlinesize,
dsetsize => dsetsize,
dsetlock => dsetlock,
dsnoop => dsnoop,
ilram => ilram,
ilramsize => ilramsize,
ilramstart => ilramstart,
dlram => dlram,
dlramsize => dlramsize,
dlramstart => dlramstart,
mmuen => mmuen,
itlbnum => itlbnum,
dtlbnum => dtlbnum,
tlb_type => tlb_type,
tlb_rep => tlb_rep,
lddel => lddel,
disas => disas,
tbuf => tbuf,
pwd => pwd,
svt => svt,
rstaddr => rstaddr,
smp => smp,
iuft => 0,
fpft => 0,
cmft => 0,
iuinj => 0,
ceinj => 0,
cached => cached,
clk2x => 0,
netlist => 0,
scantest => scantest,
mmupgsz => mmupgsz,
bp => bp,
npasi => npasi,
pwrpsr => pwrpsr,
rex => rex,
altwin => altwin)
port map (
clk => gnd,
gclk2 => gclk,
gfclk2 => clk,
clk2 => clk,
rstn => rstn,
ahbi => ahbi,
ahbo => ahbo,
ahbsi => ahbsi,
ahbso => ahbso,
irqi => irqi,
irqo => irqo,
dbgi => dbgi,
dbgo => dbgo,
fpui => open,
fpuo => fpuo,
clken => vcc
);
end;
| gpl-3.0 | 6cc78570afec490e9a89c1002910c937 | 0.466543 | 3.982916 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/gr1553b/gr1553b_stdlogic.vhd | 1 | 6,602 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: gr1553b_stdlogic
-- File: gr1553b_stdlogic.vhd
-- Author: Magnus Hjorth - Aeroflex Gaisler
-- Description: Wrapper for GR1553B with std_logic ports
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library gaisler;
use gaisler.gr1553b_pkg.all;
entity gr1553b_stdlogic is
generic (
bc_enable: integer range 0 to 1 := 1;
rt_enable: integer range 0 to 1 := 1;
bm_enable: integer range 0 to 1 := 1;
bc_timer: integer range 0 to 2 := 1;
bc_rtbusmask: integer range 0 to 1 := 1;
extra_regkeys: integer range 0 to 1 := 0;
syncrst: integer range 0 to 2 := 1;
ahbendian: integer := 0;
bm_filters: integer range 0 to 1 := 1;
codecfreq: integer := 20;
sameclk: integer range 0 to 1 := 0;
codecver: integer range 0 to 2 := 0
);
port (
clk: in std_logic;
rst: in std_logic;
codec_clk: in std_logic;
codec_rst: in std_logic;
-- AHB interface
mi_hgrant : in std_logic; -- bus grant
mi_hready : in std_ulogic; -- transfer done
mi_hresp : in std_logic_vector(1 downto 0); -- response type
mi_hrdata : in std_logic_vector(31 downto 0); -- read data bus
mo_hbusreq : out std_ulogic; -- bus request
mo_htrans : out std_logic_vector(1 downto 0); -- transfer type
mo_haddr : out std_logic_vector(31 downto 0); -- address bus (byte)
mo_hwrite : out std_ulogic; -- read/write
mo_hsize : out std_logic_vector(2 downto 0); -- transfer size
mo_hburst : out std_logic_vector(2 downto 0); -- burst type
mo_hwdata : out std_logic_vector(31 downto 0); -- write data bus
-- APB interface
si_psel : in std_logic; -- slave select
si_penable : in std_ulogic; -- strobe
si_paddr : in std_logic_vector(7 downto 0); -- address bus (byte addr)
si_pwrite : in std_ulogic; -- write
si_pwdata : in std_logic_vector(31 downto 0); -- write data bus
so_prdata : out std_logic_vector(31 downto 0); -- read data bus
so_pirq : out std_logic; -- interrupt bus
-- Aux signals
bcsync : in std_logic;
rtsync : out std_logic;
busreset : out std_logic;
rtaddr : in std_logic_vector(4 downto 0);
rtaddrp : in std_logic;
-- 1553 transceiver interface
busainen : out std_logic;
busainp : in std_logic;
busainn : in std_logic;
busaouten : out std_logic;
busaoutp : out std_logic;
busaoutn : out std_logic;
busbinen : out std_logic;
busbinp : in std_logic;
busbinn : in std_logic;
busbouten : out std_logic;
busboutp : out std_logic;
busboutn : out std_logic
);
end;
architecture rtl of gr1553b_stdlogic is
signal gr1553b_txout: gr1553b_txout_type;
signal gr1553b_rxin: gr1553b_rxin_type;
signal mi: ahb_mst_in_type;
signal mo: ahb_mst_out_type;
signal si: apb_slv_in_type;
signal so: apb_slv_out_type;
signal auxin: gr1553b_auxin_type;
signal auxout: gr1553b_auxout_type;
begin
x: gr1553b
generic map (
hindex => 0,
pindex => 0,
paddr => 0,
pmask => 0,
pirq => 0,
bc_enable => bc_enable,
rt_enable => rt_enable,
bm_enable => bm_enable,
bc_timer => bc_timer,
bc_rtbusmask => bc_rtbusmask,
syncrst => syncrst,
extra_regkeys => extra_regkeys,
ahbendian => ahbendian,
bm_filters => bm_filters,
codecfreq => codecfreq,
sameclk => sameclk,
codecver => codecver
)
port map (
clk => clk,
rst => rst,
ahbmi => mi,
ahbmo => mo,
apbsi => si,
apbso => so,
codec_clk => codec_clk,
codec_rst => codec_rst,
txout => gr1553b_txout,
txout_fb => gr1553b_txout,
rxin => gr1553b_rxin,
auxin => auxin,
auxout => auxout
);
mi.hgrant(0) <= mi_hgrant;
mi.hgrant(1 to NAHBMST-1) <= (others => '0');
mi.hready <= mi_hready;
mi.hresp <= mi_hresp;
mi.hrdata <= ahbdrivedata(mi_hrdata);
mi.hirq <= (others => '0');
mi.testen <= '0';
mi.testrst <= '0';
mi.scanen <= '0';
mi.testoen <= '0';
mo_hbusreq <= mo.hbusreq;
mo_htrans <= mo.htrans;
mo_haddr <= mo.haddr;
mo_hwrite <= mo.hwrite;
mo_hsize <= mo.hsize;
mo_hburst <= mo.hburst;
mo_hwdata <= ahbreadword(mo.hwdata);
si.psel(0) <= si_psel;
si.psel(1 to NAPBSLV-1) <= (others => '0');
si.penable <= si_penable;
si.paddr <= x"000000" & si_paddr;
si.pwrite <= si_pwrite;
si.pwdata <= si_pwdata;
si.pirq <= (others => '0');
si.testen <= '0';
si.testrst <= '0';
si.scanen <= '0';
si.testoen <= '0';
so_prdata <= so.prdata;
so_pirq <= so.pirq(0);
auxin.extsync <= bcsync;
auxin.rtaddr <= rtaddr;
auxin.rtpar <= rtaddrp;
rtsync <= auxout.rtsync;
busreset <= auxout.busreset;
busainen <= gr1553b_txout.busA_rxen;
gr1553b_rxin.busA_rxP <= busainp;
gr1553b_rxin.busA_rxN <= busainn;
busaouten <= gr1553b_txout.busA_txen;
busaoutp <= gr1553b_txout.busA_txP;
busaoutn <= gr1553b_txout.busA_txN;
busBinen <= gr1553b_txout.busB_rxen;
gr1553b_rxin.busB_rxP <= busBinp;
gr1553b_rxin.busB_rxN <= busBinn;
busBouten <= gr1553b_txout.busB_txen;
busBoutp <= gr1553b_txout.busB_txP;
busBoutn <= gr1553b_txout.busB_txN;
end;
| gpl-3.0 | ec8775ac2a81a24e4606079507bbe065 | 0.584671 | 3.385641 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/spw/wrapper/grspw_gen.vhd | 1 | 11,158 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: grspw_gen
-- File: grspw_gen.vhd
-- Author: Marko Isomaki - Gaisler Research
-- Description: Generic GRSPW core
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library spw;
use spw.spwcomp.all;
entity grspw_gen is
generic(
tech : integer := 0;
sysfreq : integer := 10000;
usegen : integer range 0 to 1 := 1;
nsync : integer range 1 to 2 := 1;
rmap : integer range 0 to 2 := 0;
rmapcrc : integer range 0 to 1 := 0;
fifosize1 : integer range 4 to 32 := 32;
fifosize2 : integer range 16 to 64 := 64;
rxclkbuftype : integer range 0 to 2 := 0;
rxunaligned : integer range 0 to 1 := 0;
rmapbufs : integer range 2 to 8 := 4;
ft : integer range 0 to 2 := 0;
scantest : integer range 0 to 1 := 0;
techfifo : integer range 0 to 1 := 1;
ports : integer range 1 to 2 := 1;
memtech : integer := 0;
nodeaddr : integer range 0 to 255 := 254;
destkey : integer range 0 to 255 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
txclk : in std_ulogic;
rxclk : in std_logic_vector(1 downto 0);
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--spw in
d : in std_logic_vector(1 downto 0);
nd : in std_logic_vector(9 downto 0);
dconnect : in std_logic_vector(3 downto 0);
--spw out
do : out std_logic_vector(1 downto 0);
so : out std_logic_vector(1 downto 0);
rxrsto : out std_ulogic;
--time iface
tickin : in std_ulogic;
tickout : out std_ulogic;
--irq
irq : out std_logic;
--misc
clkdiv10 : in std_logic_vector(7 downto 0);
dcrstval : in std_logic_vector(9 downto 0);
timerrstval : in std_logic_vector(11 downto 0);
--rmapen
rmapen : in std_ulogic;
rmapnodeaddr : in std_logic_vector(7 downto 0);
linkdis : out std_ulogic;
testclk : in std_ulogic := '0';
testrst : in std_ulogic := '0';
testen : in std_ulogic := '0'
);
end entity;
architecture rtl of grspw_gen is
constant fabits1 : integer := log2(fifosize1);
constant fabits2 : integer := log2(fifosize2);
constant rfifo : integer := 5 + log2(rmapbufs);
--rx ahb fifo
signal rxrenable : std_ulogic;
signal rxraddress : std_logic_vector(4 downto 0);
signal rxwrite : std_ulogic;
signal rxwdata : std_logic_vector(31 downto 0);
signal rxwaddress : std_logic_vector(4 downto 0);
signal rxrdata : std_logic_vector(31 downto 0);
--tx ahb fifo
signal txrenable : std_ulogic;
signal txraddress : std_logic_vector(4 downto 0);
signal txwrite : std_ulogic;
signal txwdata : std_logic_vector(31 downto 0);
signal txwaddress : std_logic_vector(4 downto 0);
signal txrdata : std_logic_vector(31 downto 0);
--nchar fifo
signal ncrenable : std_ulogic;
signal ncraddress : std_logic_vector(5 downto 0);
signal ncwrite : std_ulogic;
signal ncwdata : std_logic_vector(8 downto 0);
signal ncwaddress : std_logic_vector(5 downto 0);
signal ncrdata : std_logic_vector(8 downto 0);
--rmap buf
signal rmrenable : std_ulogic;
signal rmrenablex : std_ulogic;
signal rmraddress : std_logic_vector(7 downto 0);
signal rmwrite : std_ulogic;
signal rmwdata : std_logic_vector(7 downto 0);
signal rmwaddress : std_logic_vector(7 downto 0);
signal rmrdata : std_logic_vector(7 downto 0);
attribute syn_netlist_hierarchy : boolean;
attribute syn_netlist_hierarchy of rtl : architecture is false;
begin
grspwc0 : grspwc
generic map(
sysfreq => sysfreq,
usegen => usegen,
nsync => nsync,
rmap => rmap,
rmapcrc => rmapcrc,
fifosize1 => fifosize1,
fifosize2 => fifosize2,
rxunaligned => rxunaligned,
rmapbufs => rmapbufs,
scantest => scantest,
ports => ports,
tech => tech,
nodeaddr => nodeaddr,
destkey => destkey)
port map(
rst => rst,
clk => clk,
txclk => txclk,
--ahb mst in
hgrant => hgrant,
hready => hready,
hresp => hresp,
hrdata => hrdata,
--ahb mst out
hbusreq => hbusreq,
hlock => hlock,
htrans => htrans,
haddr => haddr,
hwrite => hwrite,
hsize => hsize,
hburst => hburst,
hprot => hprot,
hwdata => hwdata,
--apb slv in
psel => psel,
penable => penable,
paddr => paddr,
pwrite => pwrite,
pwdata => pwdata,
--apb slv out
prdata => prdata,
--spw in
d => d,
nd => nd,
dconnect => dconnect,
--spw out
do => do,
so => so,
rxrsto => rxrsto,
--time iface
tickin => tickin,
tickout => tickout,
--clk bufs
rxclki => rxclk,
--irq
irq => irq,
--misc
clkdiv10 => clkdiv10,
dcrstval => dcrstval,
timerrstval => timerrstval,
--rmapen
rmapen => rmapen,
rmapnodeaddr => rmapnodeaddr,
--rx ahb fifo
rxrenable => rxrenable,
rxraddress => rxraddress,
rxwrite => rxwrite,
rxwdata => rxwdata,
rxwaddress => rxwaddress,
rxrdata => rxrdata,
--tx ahb fifo
txrenable => txrenable,
txraddress => txraddress,
txwrite => txwrite,
txwdata => txwdata,
txwaddress => txwaddress,
txrdata => txrdata,
--nchar fifo
ncrenable => ncrenable,
ncraddress => ncraddress,
ncwrite => ncwrite,
ncwdata => ncwdata,
ncwaddress => ncwaddress,
ncrdata => ncrdata,
--rmap buf
rmrenable => rmrenable,
rmraddress => rmraddress,
rmwrite => rmwrite,
rmwdata => rmwdata,
rmwaddress => rmwaddress,
rmrdata => rmrdata,
linkdis => linkdis,
testclk => clk,
testrst => testrst,
testen => testen
);
ntst: if scantest = 0 generate
rmrenablex <= rmrenable;
end generate;
tst: if scantest = 1 generate
rmrenablex <= rmrenable and not testen;
end generate;
------------------------------------------------------------------------------
-- FIFOS ---------------------------------------------------------------------
------------------------------------------------------------------------------
nft : if ft = 0 generate
--receiver AHB FIFO
rx_ram0 : syncram_2p generic map(memtech*techfifo, fabits1, 32)
port map(clk, rxrenable, rxraddress(fabits1-1 downto 0),
rxrdata, clk, rxwrite,
rxwaddress(fabits1-1 downto 0), rxwdata);
--receiver nchar FIFO
rx_ram1 : syncram_2p generic map(memtech*techfifo, fabits2, 9)
port map(clk, ncrenable, ncraddress(fabits2-1 downto 0),
ncrdata, clk, ncwrite,
ncwaddress(fabits2-1 downto 0), ncwdata);
--transmitter FIFO
tx_ram0 : syncram_2p generic map(memtech*techfifo, fabits1, 32)
port map(clk, txrenable, txraddress(fabits1-1 downto 0),
txrdata, clk, txwrite, txwaddress(fabits1-1 downto 0), txwdata);
--RMAP Buffer
rmap_ram : if (rmap /= 0) generate
ram0 : syncram_2p generic map(memtech, rfifo, 8)
port map(clk, rmrenablex, rmraddress(rfifo-1 downto 0),
rmrdata, clk, rmwrite, rmwaddress(rfifo-1 downto 0),
rmwdata);
end generate;
end generate;
ft1 : if ft /= 0 generate
--receiver AHB FIFO
rx_ram0 : syncram_2pft generic map(memtech*techfifo, fabits1, 32, 0, 0, ft*techfifo)
port map(clk, rxrenable, rxraddress(fabits1-1 downto 0),
rxrdata, clk, rxwrite,
rxwaddress(fabits1-1 downto 0), rxwdata);
--receiver nchar FIFO
rx_ram1 : syncram_2pft generic map(memtech*techfifo, fabits2, 9, 0, 0, 2*techfifo)
port map(clk, ncrenable, ncraddress(fabits2-1 downto 0),
ncrdata, clk, ncwrite,
ncwaddress(fabits2-1 downto 0), ncwdata);
--transmitter FIFO
tx_ram0 : syncram_2pft generic map(memtech*techfifo, fabits1, 32, 0, 0, ft*techfifo)
port map(clk, txrenable, txraddress(fabits1-1 downto 0),
txrdata, clk, txwrite, txwaddress(fabits1-1 downto 0), txwdata);
--RMAP Buffer
rmap_ram : if (rmap /= 0) generate
ram0 : syncram_2pft generic map(memtech, rfifo, 8, 0, 0, 2)
port map(clk, rmrenablex, rmraddress(rfifo-1 downto 0),
rmrdata, clk, rmwrite, rmwaddress(rfifo-1 downto 0),
rmwdata);
end generate;
end generate;
end architecture;
| gpl-3.0 | 25dfdc0d0f5ce139e2d95e8c6952eba5 | 0.551981 | 4.063365 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/spi/spi_flash.vhd | 1 | 20,172 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: spi_flash
-- File: spi_flash.vhd
-- Author: Jan Andersson - Aeroflex Gaisler AB
-- [email protected]
--
-- Description:
--
-- SPI flash simulation models.
--
-- +--------------------------------------------------------+
-- | ftype | Memory device |
-- +--------+-----------------------------------------------+
-- | 1 | SD card |
-- +--------+-----------------------------------------------+
-- | 3 | Simple SPI |
-- +--------+-----------------------------------------------+
-- | 4 | SPI memory device |
-- +--------+-----------------------------------------------+
--
-- For ftype => 4, the memoffset generic can be used to specify an address
-- offset that till be automatically be removed by the memory model. For
-- instance, memoffset => 16#1000# and an access to 0x1000 will read the
-- internal memory array at offset 0x0. This is a quick hack to support booting
-- from SPIMCTRL that has an offset specified and not having to modify the
-- SREC.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
library grlib, gaisler;
use grlib.stdlib.all;
use grlib.stdio.all;
--use gaisler.sim.all;
entity spi_flash is
generic (
ftype : integer := 0; -- Flash type
debug : integer := 0; -- Debug output
fname : string := "prom.srec"; -- File to read from
readcmd : integer := 16#0B#; -- SPI memory device read command
dummybyte : integer := 1;
dualoutput : integer := 0;
memoffset : integer := 0); -- Addr. offset automatically removed
-- by Flash model
port (
sck : in std_ulogic;
di : inout std_logic;
do : inout std_logic;
csn : inout std_logic;
-- Test control inputs
sd_cmd_timeout : in std_ulogic := '0';
sd_data_timeout : in std_ulogic := '0'
);
end spi_flash;
architecture sim of spi_flash is
-- Description: Simple, incomplete, model of SD card
procedure simple_sd_model (
constant dbg : in integer;
signal sck : in std_ulogic;
signal di : in std_ulogic;
signal do : out std_ulogic;
signal csn : in std_ulogic;
-- Test control inputs
signal cmd_to : in std_ulogic; -- force command response timeout
signal data_to : in std_ulogic) is -- force data token timeout
type sd_state_type is (idle, wait_cmd55, wait_acmd41, wait_cmd16,
wait_cmd17);
type response_type is array (0 to 10) of std_logic_vector(7 downto 0);
variable state : sd_state_type := idle;
variable received_command : std_ulogic := '0';
variable respond : std_ulogic := '0';
variable response : response_type;
variable resp_size : integer;
variable indata : std_logic_vector(7 downto 0);
variable command : std_logic_vector(47 downto 0);
variable index : integer;
variable bcnt : integer;
constant CMD0 : std_logic_vector(5 downto 0) := "000000";
constant CMD16 : std_logic_vector(5 downto 0) := "010000";
constant CMD17 : std_logic_vector(5 downto 0) := "010001";
constant CMD55 : std_logic_vector(5 downto 0) := "110111";
constant ACMD41 : std_logic_vector(5 downto 0) := "101001";
constant R1 : std_logic_vector(7 downto 0) := X"00";
constant DATA_TOKEN : std_logic_vector(7 downto 0) := X"FE";
constant DATA_ERR_TOKEN : std_logic_vector(7 downto 0) := X"01";
begin -- simple_sd_model
loop
if csn /= '0' then wait until csn = '0'; end if;
index := 0; command := (others => '0');
-- Receive data
do <= '1';
while received_command = '0' and csn = '0' loop
wait until rising_edge(sck);
indata := indata(6 downto 0) & di;
index := index + 1;
if index = 8 then -- Received a byte
command := command(39 downto 0) & indata;
if dbg /= 0 then
Print(time'image(now) & ": simple_sd_model: received byte: " &
tost(indata));
end if;
if (command(47 downto 46) = "01" and command(7 downto 0) = X"95") then
received_command := '1';
end if;
index := 0;
end if;
end loop;
if received_command = '1' then
case state is
when idle =>
if command(45 downto 40) = CMD0 then
if dbg /= 0 then
Print(time'image(now) & ": simple_sd_model: received CMD0");
end if;
if cmd_to = '0' then
state := wait_cmd55;
end if;
response(0) := R1;
response(1) := (others => '1');
resp_size := 2;
respond := not cmd_to;
else
if dbg /= 0 then
Print(time'image(now) & ": simple_sd_model: received unexpected CMD" &
tost(conv_integer(command(45 downto 40))));
end if;
end if;
when wait_cmd55 =>
if command(45 downto 40) = CMD55 then
if dbg /= 0 then
Print(time'image(now) & ": simple_sd_model: received CMD55");
end if;
state := wait_acmd41;
response(0) := R1;
response(1) := (others => '1');
resp_size := 2;
respond := not cmd_to;
else
if dbg /= 0 then
Print(time'image(now) & ": simple_sd_model: received unexpected CMD" &
tost(conv_integer(command(45 downto 40))));
end if;
end if;
when wait_acmd41 =>
if command(45 downto 40) = ACMD41 then
if dbg /= 0 then
Print(time'image(now) & ": simple_sd_model: received CMD41");
end if;
if cmd_to = '0' then
state := wait_cmd16;
else
state := idle;
end if;
response(0) := R1;
response(1) := (others => '1');
resp_size := 2;
respond := not cmd_to;
else
if dbg /= 0 then
Print(time'image(now) & ": simple_sd_model: received unexpected CMD" &
tost(conv_integer(command(45 downto 40))));
end if;
end if;
when wait_cmd16 =>
if command(45 downto 40) = CMD16 then
if dbg /= 0 then
Print(time'image(now) & ": simple_sd_model: received CMD16");
Print(time'image(now) & ": simple_sd_model: BLOCKLEN set to " &
tost(conv_integer(command(39 downto 8))));
end if;
state := wait_cmd17;
response(0) := R1;
response(1) := (others => '1');
resp_size := 2;
respond := not cmd_to;
else
if dbg /= 0 then
Print(time'image(now) & ": simple_sd_model: received unexpected CMD" &
tost(conv_integer(command(45 downto 40))));
end if;
end if;
when wait_cmd17 =>
if command(45 downto 40) = CMD17 then
if dbg /= 0 then
Print(time'image(now) & ": simple_sd_model: received CMD17");
Print(time'image(now) & ": simple_sd_model: Read from address " &
tost(conv_integer(command(39 downto 8))));
end if;
response(0) := R1;
response(1) := (others => '1');
response(2) := (others => '1');
response(3) := DATA_TOKEN;
-- Data response is address
response(4) := command(39 downto 32);
response(5) := command(31 downto 24);
response(6) := command(23 downto 16);
response(7) := command(15 downto 8);
if data_to = '1' then
resp_size := 1;
else
resp_size := 8;
end if;
respond := not cmd_to;
elsif command(45 downto 40) = CMD0 then
if dbg /= 0 then
Print(time'image(now) & ": simple_sd_model: received CMD0");
end if;
if cmd_to = '0' then
state := wait_cmd55;
end if;
response(0) := R1;
response(1) := (others => '1');
resp_size := 2;
respond := not cmd_to;
else
if dbg /= 0 then
Print(time'image(now) & ": simple_sd_model: received unexpected CMD" &
tost(conv_integer(command(45 downto 40))));
end if;
end if;
end case;
received_command := '0';
end if;
if respond = '1' then
bcnt := 0;
while resp_size > bcnt loop
if dbg /= 0 then
Print(time'image(now) & ": simple_sd_model: Responding with " &
tost(response(bcnt)));
end if;
index := 0;
while index < 8 loop
wait until falling_edge(sck);
do <= response(bcnt)(7);
response(bcnt)(7 downto 1) := response(bcnt)(6 downto 0);
index := index + 1;
end loop;
bcnt := bcnt + 1;
end loop;
respond := '0';
wait until rising_edge(sck);
else
do <= '1';
end if;
end loop;
end simple_sd_model;
-- purpose: Simple, incomplete, model of SPI Flash device
procedure simple_spi_flash_model (
constant dbg : in integer;
constant readcmd : in integer;
constant dummybyte : in boolean;
constant dualoutput : in boolean;
signal sck : in std_ulogic;
signal di : inout std_ulogic;
signal do : out std_ulogic;
signal csn : in std_ulogic) is
constant readinst : std_logic_vector(7 downto 0) :=
conv_std_logic_vector(readcmd, 8);
variable received_command : std_ulogic := '0';
variable respond : std_ulogic := '0';
variable response : std_logic_vector(31 downto 0);
variable indata : std_logic_vector(7 downto 0);
variable command : std_logic_vector(39 downto 0);
variable index : integer;
begin -- simple_spi_flash_model
di <= 'Z'; do <= 'Z';
loop
if csn /= '0' then wait until csn = '0'; end if;
index := 0; command := (others => '0');
while received_command = '0' and csn = '0' loop
wait until rising_edge(sck);
indata := indata(6 downto 0) & di;
index := index + 1;
if index = 8 then
command := command(31 downto 0) & indata;
if dbg /= 0 then
Print(time'image(now) & ": simple_spi_flash_model: received byte: " &
tost(indata));
end if;
if ((dummybyte and command(39 downto 32) = readinst) or
(not dummybyte and command(31 downto 24) = readinst)) then
received_command := '1';
end if;
index := 0;
end if;
end loop;
if received_command = '1' then
response := (others => '0');
if dummybyte then
response(23 downto 0) := command(31 downto 8);
else
response(23 downto 0) := command(23 downto 0);
end if;
index := 31 - conv_integer(response(1 downto 0)) * 8;
response(1 downto 0) := (others => '0');
while csn = '0' loop
while index >= 0 and csn = '0' loop
wait until falling_edge(sck) or csn = '1';
if dualoutput then
do <= response(index);
di <= response(index-1);
index := index - 2;
else
do <= response(index);
index := index - 1;
end if;
end loop;
index := 31;
response := response + 4;
end loop;
if dualoutput then
di <= 'Z';
end if;
received_command := '0';
else
do <= '1';
end if;
end loop;
end simple_spi_flash_model;
-- purpose: SPI memory device that reads input from prom.srec
procedure spi_memory_model (
constant dbg : in integer;
constant readcmd : in integer;
constant dummybyte : in boolean;
constant dualoutput : in boolean;
signal sck : in std_ulogic;
signal di : inout std_ulogic;
signal do : inout std_ulogic;
signal csn : in std_ulogic) is
constant readinst : std_logic_vector(7 downto 0) :=
conv_std_logic_vector(readcmd, 8);
variable received_command : std_ulogic := '0';
variable respond : std_ulogic := '0';
variable response : std_logic_vector(31 downto 0);
variable address : std_logic_vector(23 downto 0);
variable indata : std_logic_vector(7 downto 0);
variable command : std_logic_vector(39 downto 0);
variable index : integer;
file fload : text open read_mode is fname;
variable fline : line;
variable fchar : character;
variable rtype : std_logic_vector(3 downto 0);
variable raddr : std_logic_vector(31 downto 0);
variable rlen : std_logic_vector(7 downto 0);
variable rdata : std_logic_vector(0 to 127);
variable wordaddr : integer;
type mem_type is array (0 to 8388607) of std_logic_vector(31 downto 0);
variable mem : mem_type := (others => (others => '1'));
begin -- spi_memory_model
di <= 'Z'; do <= 'Z';
-- Load memory data from file
while not endfile(fload) loop
readline(fload, fline);
read(fline, fchar);
if fchar /= 'S' or fchar /= 's' then
hread(fline, rtype);
hread(fline, rlen);
raddr := (others => '0');
case rtype is
when "0001" =>
hread(fline, raddr(15 downto 0));
when "0010" =>
hread(fline, raddr(23 downto 0));
when "0011" =>
hread(fline, raddr);
raddr(31 downto 24) := (others => '0');
when others => next;
end case;
hread(fline, rdata);
for i in 0 to 3 loop
mem(conv_integer(raddr(31 downto 2)+i)) :=
rdata(i*32 to i*32+31);
end loop;
end if;
end loop;
loop
if csn /= '0' then wait until csn = '0'; end if;
index := 0; command := (others => '0');
while received_command = '0' and csn = '0' loop
wait until rising_edge(sck);
indata := indata(6 downto 0) & di;
index := index + 1;
if index = 8 then
command := command(31 downto 0) & indata;
if dbg /= 0 then
Print(time'image(now) & ": spi_memory_model: received byte: " &
tost(indata));
end if;
if ((dummybyte and command(39 downto 32) = readinst) or
(not dummybyte and command(31 downto 24) = readinst)) then
received_command := '1';
end if;
index := 0;
end if;
end loop;
if received_command = '1' then
response := (others => '0');
if dummybyte then
address := command(31 downto 8);
else
address := command(23 downto 0);
end if;
if dbg /= 0 then
Print(time'image(now) & ": spi_memory_model: received address: " &
tost(address));
if memoffset /= 0 then
Print(time'image(now) & ": spi_memory_model: address after removed offset " &
tost(address-memoffset));
end if;
end if;
if memoffset /= 0 then
address := address - memoffset;
end if;
index := 31 - conv_integer(address(1 downto 0)) * 8;
while csn = '0' loop
response := mem(conv_integer(address(23 downto 2)));
if dbg /= 0 then
Print(time'image(now) & ": spi_memory_model: responding with data: " &
tost(response(index downto 0)));
end if;
while index >= 0 and csn = '0' loop
wait until falling_edge(sck) or csn = '1';
if dualoutput then
do <= response(index);
di <= response(index-1);
index := index - 2;
else
do <= response(index);
index := index - 1;
end if;
end loop;
index := 31;
address := address + 4;
end loop;
if dualoutput then
di <= 'Z';
end if;
do <= 'Z';
received_command := '0';
else
do <= 'Z';
end if;
end loop;
end spi_memory_model;
signal vdd : std_ulogic := '1';
signal gnd : std_ulogic := '0';
begin -- sim
-- ftype0: if ftype = 0 generate
-- csn <= 'Z';
-- di <= 'Z';
-- flash0 : s25fl064a
-- generic map (tdevice_PU => 1 us,
-- TimingChecksOn => true,
-- MsgOn => debug = 1,
-- UserPreLoad => true)
-- port map (SCK => sck, SI => di, CSNeg => csn, HOLDNeg => vdd,
-- WNeg => vdd, SO => do);
-- end generate ftype0;
ftype1: if ftype = 1 generate
csn <= 'H';
di <= 'Z';
simple_sd_model(debug, sck, di, do, csn, sd_cmd_timeout, sd_data_timeout);
end generate ftype1;
-- ftype2: if ftype = 2 generate
-- csn <= 'Z';
-- di <= 'Z';
-- flash0 : m25p80
-- generic map (TimingChecksOn => false,
-- MsgOn => debug = 1,
-- UserPreLoad => true)
-- port map (C => sck, D => di, SNeg => csn, HOLDNeg => vdd,
-- WNeg => vdd, Q => do);
-- end generate ftype2;
ftype3: if ftype = 3 generate
csn <= 'Z';
simple_spi_flash_model (
dbg => debug,
readcmd => readcmd,
dummybyte => dummybyte /= 0,
dualoutput => dualoutput /= 0,
sck => sck,
di => di,
do => do,
csn => csn);
end generate ftype3;
ftype4: if ftype = 4 generate
spi_memory_model (
dbg => debug,
readcmd => readcmd,
dummybyte => dummybyte /= 0,
dualoutput => dualoutput /= 0,
sck => sck,
di => di,
do => do,
csn => csn);
csn <= 'Z';
end generate ftype4;
notsupported: if ftype > 4 generate
assert false report "spi_flash: no model" severity failure;
end generate notsupported;
end sim;
| gpl-3.0 | a29b2551566c866c267990187760454e | 0.489342 | 4.127686 | false | false | false | false |
pwsoft/fpga_examples | rtl/ttl/ttl_74161.vhd | 1 | 3,685 | -- -----------------------------------------------------------------------
--
-- Syntiac VHDL support files.
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2018 by Peter Wendrich ([email protected])
-- http://www.syntiac.com
--
-- This source file is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- -----------------------------------------------------------------------
-- Presettable synchronous 4-bit binary counter with asynchronous reset
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use work.ttl_pkg.all;
-- -----------------------------------------------------------------------
entity ttl_74161 is
generic (
latency : integer := 3
);
port (
emuclk : in std_logic;
p1 : in ttl_t; -- MRn
p2 : in ttl_t; -- CP
p3 : in ttl_t; -- D0
p4 : in ttl_t; -- D1
p5 : in ttl_t; -- D2
p6 : in ttl_t; -- D3
p7 : in ttl_t; -- CEP
p9 : in ttl_t; -- PEn
p10 : in ttl_t; -- CET
p11 : out ttl_t; -- Q3
p12 : out ttl_t; -- Q2
p13 : out ttl_t; -- Q1
p14 : out ttl_t; -- Q0
p15 : out ttl_t -- TC
);
end entity;
architecture rtl of ttl_74161 is
signal q0_reg : ttl_t := ZERO;
signal q1_reg : ttl_t := ZERO;
signal q2_reg : ttl_t := ZERO;
signal q3_reg : ttl_t := ZERO;
signal tc_reg : ttl_t := ZERO;
signal cp : std_logic;
signal cp_dly : std_logic := '0';
begin
p11_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => q3_reg, q => p11);
p12_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => q2_reg, q => p12);
p13_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => q1_reg, q => p13);
p14_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => q0_reg, q => p14);
p15_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => tc_reg, q => p15);
cp <= ttl2std(p2);
process(emuclk)
begin
if rising_edge(emuclk) then
cp_dly <= cp;
if is_low(p1) then
-- Asynchronous reset
q0_reg <= ZERO;
q1_reg <= ZERO;
q2_reg <= ZERO;
q3_reg <= ZERO;
elsif (cp = '1') and (cp_dly = '0') then
if is_low(p9) then
-- Load constant
q0_reg <= buffered(p3);
q1_reg <= buffered(p4);
q2_reg <= buffered(p5);
q3_reg <= buffered(p6);
elsif is_high(p7) and is_high(p10) then
-- Count
q0_reg <= not q0_reg;
if is_high(q0_reg) then
q1_reg <= not q1_reg;
end if;
if is_high(q0_reg) and is_high(q1_reg) then
q2_reg <= not q2_reg;
end if;
if is_high(q0_reg) and is_high(q1_reg) and is_high(q2_reg) then
q3_reg <= not q3_reg;
end if;
tc_reg <= ZERO;
if is_low(q0_reg) and is_high(q1_reg) and is_high(q2_reg) and is_high(q3_reg) then
tc_reg <= ONE;
end if;
end if;
end if;
end if;
end process;
end architecture;
| lgpl-2.1 | 8ba21197ae8e5c4f25a602dd1587c161 | 0.560109 | 2.957464 | false | false | false | false |
pwsoft/fpga_examples | rtl/general/gen_reset.vhd | 1 | 2,930 | -- -----------------------------------------------------------------------
--
-- Syntiac VHDL support files.
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2009 by Peter Wendrich ([email protected])
-- http://www.syntiac.com
--
-- This source file is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- -----------------------------------------------------------------------
--
-- Power-on reset circuit with manual reset button input.
--
-- -----------------------------------------------------------------------
--
-- reset = 1 (nreset = 0) on power-on or after pressing button. After
-- resetCycles number of clocks have passed the reset line is released.
-- If a longer reset period is required the enable input can be connected
-- to a slow clock signal (like the video vertical blanking interrupt).
-- The enable input should be one clock cycle high each video frame.
-- Then resetCycles is specified in the number of video frames iso clock cycles.
--
-- Initial reset is only active after power-on. It will not be retriggered by
-- the reset button.
--
-- If button is connected and set to '1' a new reset cycle if started.
--
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
-- -----------------------------------------------------------------------
entity gen_reset is
generic (
resetCycles: integer := 4095
);
port (
clk : in std_logic;
enable : in std_logic := '1';
button : in std_logic := '0';
initial_reset : out std_logic;
reset : out std_logic;
nreset : out std_logic
);
end entity;
-- -----------------------------------------------------------------------
architecture rtl of gen_reset is
signal cnt : integer range 0 to resetCycles := 0;
signal initial_nreset_reg : std_logic := '0';
signal reset_n_reg : std_logic := '0';
begin
initial_reset <= not initial_nreset_reg;
reset <= not reset_n_reg;
nreset <= reset_n_reg;
process(clk)
begin
if rising_edge(clk) then
reset_n_reg <= '1';
if cnt < resetCycles then
reset_n_reg <= '0';
if enable = '1' then
cnt <= cnt + 1;
end if;
else
initial_nreset_reg <= '1';
end if;
if button = '1' then
cnt <= 0;
end if;
end if;
end process;
end architecture;
| lgpl-2.1 | ca2aa40e3a0e5d309ccd7cb89baf71e1 | 0.569283 | 4.030261 | false | false | false | false |
pwsoft/fpga_examples | rtl/audio/audio_sigmadelta_dac_tb.vhd | 1 | 1,903 | -- -----------------------------------------------------------------------
--
-- Syntiac VHDL support files.
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2009 by Peter Wendrich ([email protected])
-- http://www.syntiac.com
--
-- This source file is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- -----------------------------------------------------------------------
--
-- Test bench for audio_sigmadelta_dac
--
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
-- -----------------------------------------------------------------------
entity audio_sigmadelta_dac_tb is
end entity;
-- -----------------------------------------------------------------------
architecture rtl of audio_sigmadelta_dac_tb is
signal clk : std_logic;
signal audio : signed(15 downto 0) := (others => '0');
signal singlebit : std_logic;
begin
mySigmaDelta : entity work.audio_sigmadelta_dac
port map (
clk => clk,
d => audio,
q => singlebit
);
process
begin
clk <= '0';
wait for 10 ns;
clk <= '1';
wait for 10 ns;
end process;
process(clk)
begin
if rising_edge(clk) then
audio <= audio + 1;
end if;
end process;
end architecture;
| lgpl-2.1 | ac1ee25a6c4c180f373088f50014af49 | 0.53547 | 4.164114 | false | false | false | false |
pwsoft/fpga_examples | rtl/general/gen_filter.vhd | 1 | 2,369 | -- -----------------------------------------------------------------------
--
-- Syntiac's generic VHDL support files.
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2010 by Peter Wendrich ([email protected])
-- http://www.syntiac.com/fpga64.html
--
-- This source file is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- -----------------------------------------------------------------------
--
-- gen_filter.vhd
--
-- -----------------------------------------------------------------------
--
-- Signal filter to detect stable digital signal.
-- Output only changes when the input signal is stable for specified steps.
--
-- -----------------------------------------------------------------------
-- steps - filter steps
-- -----------------------------------------------------------------------
-- clk - clock input
-- d - signal input
-- q - signal output
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
-- -----------------------------------------------------------------------
entity gen_filter is
generic (
steps : integer := 4
);
port (
clk : in std_logic;
d : in std_logic;
q : out std_logic
);
end entity;
-- -----------------------------------------------------------------------
architecture rtl of gen_filter is
signal shift_reg : unsigned(steps-1 downto 0) := (others => '0');
signal q_reg : std_logic := '0';
begin
q <= q_reg;
process(clk)
begin
if rising_edge(clk) then
shift_reg <= shift_reg(shift_reg'high-1 downto 0) & d;
if shift_reg = 0 then
q_reg <= '0';
elsif (not shift_reg) = 0 then
q_reg <= '1';
end if;
end if;
end process;
end architecture;
| lgpl-2.1 | 9d5bacca25eca3abfb5c82b3b84f887a | 0.489236 | 4.354779 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/techmap/maps/sdram_phy.vhd | 1 | 7,947 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: sdram_phy
-- File: sdram_phy.vhd
-- Author: Jan Andersson - Aeroflex Gaisler
-- Description: SDRAM PHY with tech mapping, includes pads and can be
-- implemented with registers on all signals.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
use techmap.allpads.all;
entity sdram_phy is
generic (
tech : integer := spartan3;
oepol : integer := 0;
level : integer := 0;
voltage : integer := x33v;
strength : integer := 12;
aw : integer := 15; -- # address bits
dw : integer := 32; -- # data bits
ncs : integer := 2;
reg : integer := 0); -- 1: include registers on all signals
port (
-- SDRAM interface
addr : out std_logic_vector(aw-1 downto 0);
dq : inout std_logic_vector(dw-1 downto 0);
cke : out std_logic_vector(ncs-1 downto 0);
sn : out std_logic_vector(ncs-1 downto 0);
wen : out std_ulogic;
rasn : out std_ulogic;
casn : out std_ulogic;
dqm : out std_logic_vector(dw/8-1 downto 0);
-- Interface toward memory controller
laddr : in std_logic_vector(aw-1 downto 0);
ldq_din : out std_logic_vector(dw-1 downto 0);
ldq_dout : in std_logic_vector(dw-1 downto 0);
ldq_oen : in std_logic_vector(dw-1 downto 0);
lcke : in std_logic_vector(ncs-1 downto 0);
lsn : in std_logic_vector(ncs-1 downto 0);
lwen : in std_ulogic;
lrasn : in std_ulogic;
lcasn : in std_ulogic;
ldqm : in std_logic_vector(dw/8-1 downto 0);
-- Only used when reg generic is non-zero
rstn : in std_ulogic; -- Registered pads reset
clk : in std_ulogic; -- SDRAM clock for registered pads
-- Optional pad configuration inputs
cfgi_cmd : in std_logic_vector(19 downto 0) := "00000000000000000000"; -- CMD pads
cfgi_dq : in std_logic_vector(19 downto 0) := "00000000000000000000" -- DQ pads
);
end;
architecture rtl of sdram_phy is
signal laddrx : std_logic_vector(aw-1 downto 0);
signal ldq_dinx : std_logic_vector(dw-1 downto 0);
signal ldq_doutx : std_logic_vector(dw-1 downto 0);
signal ldq_oenx : std_logic_vector(dw-1 downto 0);
signal lckex : std_logic_vector(ncs-1 downto 0);
signal lsnx : std_logic_vector(ncs-1 downto 0);
signal lwenx : std_ulogic;
signal lrasnx : std_ulogic;
signal lcasnx : std_ulogic;
signal ldqmx : std_logic_vector(dw/8-1 downto 0);
signal oen : std_ulogic;
signal voen : std_logic_vector(dw-1 downto 0);
-- Determines if there is a customized phy available for target tech,
-- otherwise a generic PHY will be built
constant has_sdram_phy : tech_ability_type :=
(easic45 => 1, others => 0);
-- Determines if target tech has pads with built in registers (or rather if
-- target technology requires special pad instantiations in order to get
-- registers into pad ring).
constant tech_has_padregs : tech_ability_type :=
(easic45 => 1, others => 0);
begin
oen <= not ldq_oen(0) when padoen_polarity(tech) /= oepol else ldq_oen(0);
voen <= not ldq_oen when padoen_polarity(tech) /= oepol else ldq_oen;
nopadregs : if (reg = 0) or (tech_has_padregs(tech) /= 0) generate
laddrx <= laddr;
ldq_din <= ldq_dinx;
ldq_doutx <= ldq_dout;
ldq_oenx <= voen;
lckex <= lcke;
lsnx <= lsn;
lwenx <= lwen;
lrasnx <= lrasn;
lcasnx <= lcasn;
ldqmx <= ldqm;
end generate;
padregs : if (reg /= 0) and (tech_has_padregs(tech) = 0) generate
regproc : process(clk, rstn)
begin
if rising_edge(clk) then
laddrx <= laddr;
ldq_din <= ldq_dinx;
ldq_doutx <= ldq_dout;
ldq_oenx <= (others => oen);
lckex <= lcke;
lsnx <= lsn;
lwenx <= lwen;
lrasnx <= lrasn;
lcasnx <= lcasn;
ldqmx <= ldqm;
end if;
if rstn = '0' then
lsnx <= (others => '1');
for i in ldq_oenx'range loop
ldq_oenx(i) <= conv_std_logic(padoen_polarity(tech) = 0);
end loop;
end if;
end process;
end generate;
gen : if has_sdram_phy(tech) = 0 generate
-- SDRAM address
sa_pad : outpadv
generic map (
width => aw,
tech => tech,
level => level,
voltage => voltage,
strength => strength)
port map (addr, laddrx, cfgi_cmd);
-- SDRAM data
sd_pad : iopadvv
generic map (
width => dw,
tech => tech,
level => level,
voltage => voltage,
strength => strength,
oepol => padoen_polarity(tech))
port map (dq, ldq_doutx, ldq_oenx, ldq_dinx, cfgi_dq);
-- SDRAM clock enable
sdcke_pad : outpadv
generic map (
width => ncs,
tech => tech,
level => level,
voltage => voltage,
strength => strength)
port map (cke, lckex, cfgi_cmd);
-- SDRAM write enable
sdwen_pad : outpad generic map (
tech => tech,
level => level,
voltage => voltage,
strength => strength)
port map (wen, lwenx, cfgi_cmd);
-- SDRAM chip select
sdcsn_pad : outpadv
generic map (
width => ncs,
tech => tech,
level => level,
voltage => voltage,
strength => strength)
port map (sn, lsnx, cfgi_cmd);
-- SDRAM ras
sdras_pad : outpad
generic map (
tech => tech,
level => level,
voltage => voltage,
strength => strength)
port map (rasn, lrasnx, cfgi_cmd);
-- SDRAM cas
sdcas_pad : outpad
generic map (
tech => tech,
level => level,
voltage => voltage,
strength => strength)
port map (casn, lcasnx, cfgi_cmd);
-- SDRAM dqm
sddqm_pad : outpadv
generic map (
width => dw/8,
level => level,
voltage => voltage,
tech => tech,
strength => strength)
port map (dqm, ldqmx, cfgi_cmd);
end generate;
n2x : if (tech = easic45) generate
phy0 : n2x_sdram_phy
generic map (
level => level, voltage => voltage, strength => strength,
aw => aw, dw => dw, ncs => ncs, reg => reg)
port map (
addr, dq, cke, sn, wen, rasn, casn, dqm,
laddrx, ldq_dinx, ldq_doutx, ldq_oenx, lckex,
lsnx, lwenx, lrasnx, lcasnx, ldqmx,
rstn, clk,
cfgi_cmd, cfgi_dq);
end generate;
end;
| gpl-3.0 | 0ba220538fd38dce7b9601dbc9837d7c | 0.555556 | 3.694561 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/techmap/stratixii/clkgen_stratixii.vhd | 1 | 6,749 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
library altera_mf;
-- pragma translate_off
use altera_mf.altpll;
-- pragma translate_on
entity stratix2_pll is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
clk_freq : integer := 25000;
clk2xen : integer := 0;
sdramen : integer := 0
);
port (
inclk0 : in std_ulogic;
c0 : out std_ulogic;
c0_2x : out std_ulogic;
e0 : out std_ulogic;
locked : out std_ulogic
);
end;
architecture rtl of stratix2_pll is
component altpll
generic (
intended_device_family : string := "Stratix" ;
operation_mode : string := "NORMAL" ;
compensate_clock : string := "CLK0" ;
inclk0_input_frequency : positive;
width_clock : positive := 6;
clk0_multiply_by : positive := 1;
clk0_divide_by : positive := 1;
clk1_multiply_by : positive := 1;
clk1_divide_by : positive := 1;
clk2_multiply_by : positive := 1;
clk2_divide_by : positive := 1
);
port (
inclk : in std_logic_vector(1 downto 0);
clk : out std_logic_vector(width_clock-1 downto 0);
locked : out std_logic
);
end component;
signal clkout : std_logic_vector (5 downto 0);
signal inclk : std_logic_vector (1 downto 0);
constant clk_period : integer := 1000000000/clk_freq;
constant CLK_MUL2X : integer := clk_mul * 2;
begin
inclk <= '0' & inclk0;
c0 <= clkout(0); c0_2x <= clkout(1);
sden : if sdramen = 1 generate
altpll0 : altpll
generic map (
intended_device_family => "Stratix II",
operation_mode => "ZERO_DELAY_BUFFER",
compensate_clock => "CLK2",
inclk0_input_frequency => clk_period,
clk0_multiply_by => clk_mul, clk0_divide_by => clk_div,
clk1_multiply_by => CLK_MUL2X, clk1_divide_by => clk_div,
clk2_multiply_by => clk_mul, clk2_divide_by => clk_div)
port map (inclk => inclk, clk => clkout, locked => locked);
e0 <= clkout(2);
end generate;
nosd : if sdramen = 0 generate
altpll0 : altpll
generic map (
intended_device_family => "Stratix II",
operation_mode => "NORMAL",
inclk0_input_frequency => clk_period,
clk0_multiply_by => clk_mul, clk0_divide_by => clk_div,
clk1_multiply_by => CLK_MUL2X, clk1_divide_by => clk_div)
port map (inclk => inclk, clk => clkout, locked => locked);
e0 <= '0';
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library altera_mf;
library grlib;
use grlib.stdlib.all;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity clkgen_stratixii is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
sdinvclk : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000;
clk2xen : integer := 0);
port (
clkin : in std_logic;
pciclkin: in std_logic;
clk : out std_logic; -- main clock
clkn : out std_logic; -- inverted main clock
clk2x : out std_logic; -- double clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type);
end;
architecture rtl of clkgen_stratixii is
constant VERSION : integer := 1;
constant CLKIN_PERIOD : integer := 20;
signal clk_i : std_logic;
signal clkint, pciclkint : std_logic;
signal pllclk, pllclkn : std_logic; -- generated clocks
signal s_clk : std_logic;
-- altera pll
component stratix2_pll
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
clk_freq : integer := 25000;
clk2xen : integer := 0;
sdramen : integer := 0
);
port (
inclk0 : in std_ulogic;
e0 : out std_ulogic;
c0 : out std_ulogic;
c0_2x : out std_ulogic;
locked : out std_ulogic);
end component;
begin
cgo.pcilock <= '1';
-- c0 : if (PCISYSCLK = 0) generate
-- Clkint <= Clkin;
-- end generate;
-- c1 : if (PCISYSCLK = 1) generate
-- Clkint <= pciclkin;
-- end generate;
-- c2 : if (PCIEN = 1) generate
-- p0 : if (PCIDLL = 1) generate
-- pciclkint <= pciclkin;
-- pciclk <= pciclkint;
-- end generate;
-- p1 : if (PCIDLL = 0) generate
-- u0 : if (PCISYSCLK = 0) generate
-- pciclkint <= pciclkin;
-- end generate;
-- pciclk <= clk_i when (PCISYSCLK = 1) else pciclkint;
-- end generate;
-- end generate;
-- c3 : if (PCIEN = 0) generate
-- pciclk <= Clkint;
-- end generate;
c0: if (PCISYSCLK = 0) or (PCIEN = 0) generate
clkint <= clkin;
end generate c0;
c1: if PCIEN /= 0 generate
d0: if PCISYSCLK = 1 generate
clkint <= pciclkin;
end generate d0;
pciclk <= pciclkin;
end generate c1;
c2: if PCIEN = 0 generate
pciclk <= '0';
end generate c2;
sdclk_pll : stratix2_pll
generic map (clk_mul, clk_div, freq, clk2xen, sdramen)
port map ( inclk0 => clkint, e0 => sdclk, c0 => s_clk, c0_2x => clk2x,
locked => cgo.clklock);
clk <= s_clk;
clkn <= not s_clk;
-- pragma translate_off
bootmsg : report_version
generic map (
"clkgen_stratixii" & ": altpll sdram/pci clock generator, version " & tost(VERSION),
"clkgen_stratixii" & ": Frequency " & tost(freq) & " KHz, PLL scaler " & tost(clk_mul) & "/" & tost(clk_div));
-- pragma translate_on
end;
| gpl-3.0 | b420a64a7f53bdc766ee187b4b8259de | 0.585568 | 3.513274 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/techmap/maps/scanreg.vhd | 1 | 7,585 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: scanregi, scanrego, scanregio
-- File: scanreg.vhd
-- Author: Magnus Hjorth - Aeroflex Gaisler
-- Description: Technology wrapper for boundary scan registers
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
use techmap.alltap.all;
entity scanregi is
generic (
tech : integer := 0;
intesten: integer := 1
);
port (
pad : in std_ulogic;
core : out std_ulogic;
tck : in std_ulogic;
tckn : in std_ulogic;
tdi : in std_ulogic;
tdo : out std_ulogic;
bsshft : in std_ulogic;
bscapt : in std_ulogic;
bsupd : in std_ulogic;
bsdrive : in std_ulogic;
bshighz : in std_ulogic
);
end;
architecture tmap of scanregi is
signal d1, d2, q1, q2, m3i, o1o : std_ulogic;
begin
gen0: if tech = 0 generate
x: scanregi_inf generic map (intesten) port map (pad,core,tck,tckn,tdi,tdo,bsshft,bscapt,bsupd,bsdrive,bshighz);
end generate;
map0: if tech /= 0 generate
iten: if intesten /= 0 generate
m1 : grmux2 generic map (tech) port map (pad, q1, bsdrive, core);
f1 : grdff generic map (tech) port map (tckn, d1, q1);
m2 : grmux2 generic map (tech) port map (q1, q2, bsupd, d1);
end generate;
itdis: if intesten = 0 generate
core <= pad;
q1 <= '0';
d1 <= '0';
end generate;
m3 : grmux2 generic map (tech) port map (m3i, tdi, bsshft, d2);
m4 : grmux2 generic map (tech) port map (q2, o1o, bscapt, m3i);
o1 : gror2 generic map (tech) port map (pad, bshighz, o1o);
f2 : grdff generic map (tech) port map (tck, d2, q2);
tdo <= q2;
end generate;
end;
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
use techmap.alltap.all;
entity scanrego is
generic (
tech : integer := 0
);
port (
pad : out std_ulogic;
core : in std_ulogic;
samp : in std_ulogic;
tck : in std_ulogic;
tckn : in std_ulogic;
tdi : in std_ulogic;
tdo : out std_ulogic;
bsshft : in std_ulogic;
bscapt : in std_ulogic;
bsupd : in std_ulogic;
bsdrive : in std_ulogic
);
end;
architecture tmap of scanrego is
signal d1, d2, q1, q2, m3i, o1o : std_ulogic;
begin
gen0: if tech = 0 generate
x: scanrego_inf port map (pad,core,samp,tck,tckn,tdi,tdo,bsshft,bscapt,bsupd,bsdrive);
end generate;
map0: if tech /= 0 generate
m1 : grmux2 generic map (tech) port map (core, q1, bsdrive, pad);
m2 : grmux2 generic map (tech) port map (q1, q2, bsupd, d1);
m3 : grmux2 generic map (tech) port map (m3i, tdi, bsshft, d2);
m4 : grmux2 generic map (tech) port map (q2, samp, bscapt, m3i);
f1 : grdff generic map (tech) port map (tckn, d1, q1);
f2 : grdff generic map (tech) port map (tck, d2, q2);
tdo <= q2;
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
use techmap.alltap.all;
entity scanregto is
generic (
tech : integer := 0;
hzsup: integer range 0 to 1 := 1;
oepol: integer range 0 to 1 := 1;
scantest: integer range 0 to 1 := 0
);
port (
pado : out std_ulogic;
padoen : out std_ulogic;
samp : in std_ulogic;
coreo : in std_ulogic;
coreoen : in std_ulogic;
tck : in std_ulogic;
tckn : in std_ulogic;
tdi : in std_ulogic;
tdo : out std_ulogic;
bsshft : in std_ulogic;
bscapto : in std_ulogic;
bscaptoe: in std_ulogic;
bsupdo : in std_ulogic;
bsdrive : in std_ulogic;
bshighz : in std_ulogic;
testen : in std_ulogic;
testoen : in std_ulogic
);
end;
architecture tmap of scanregto is
signal tdo1, padoenx,padoenxx : std_ulogic;
begin
x1: scanrego generic map (tech)
port map (pado, coreo, samp, tck, tckn, tdo1, tdo, bsshft, bscapto, bsupdo, bsdrive);
x2: scanrego generic map (tech)
port map (padoenx, coreoen, coreoen, tck, tckn, tdi, tdo1, bsshft, bscaptoe, bsupdo, bsdrive);
hz : if hzsup = 1 generate
x3 : if oepol = 0 generate
x33 : gror2 generic map (tech) port map (padoenx, bshighz, padoenxx);
end generate;
x4 : if oepol = 1 generate
x33 : grand12 generic map (tech) port map (padoenx, bshighz, padoenxx);
end generate;
end generate;
nohz : if hzsup = 0 generate
padoenxx <= padoenx;
end generate;
oem: if scantest /= 0 generate
x4: grmux2 generic map (tech) port map (padoenxx, testoen, testen, padoen);
end generate;
nooem: if scantest = 0 generate
padoen <= padoenxx;
end generate;
end;
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
use techmap.alltap.all;
entity scanregio is
generic (
tech : integer := 0;
hzsup: integer range 0 to 1 := 1;
oepol: integer range 0 to 1 := 1;
intesten: integer range 0 to 1 := 1;
scantest: integer range 0 to 1 := 0
);
port (
pado : out std_ulogic;
padoen : out std_ulogic;
padi : in std_ulogic;
coreo : in std_ulogic;
coreoen : in std_ulogic;
corei : out std_ulogic;
tck : in std_ulogic;
tckn : in std_ulogic;
tdi : in std_ulogic;
tdo : out std_ulogic;
bsshft : in std_ulogic;
bscapti : in std_ulogic;
bscapto : in std_ulogic;
bscaptoe: in std_ulogic;
bsupdi : in std_ulogic;
bsupdo : in std_ulogic;
bsdrive : in std_ulogic;
bshighz : in std_ulogic;
testen : in std_ulogic;
testoen : in std_ulogic
);
end;
architecture tmap of scanregio is
signal tdo1, tdo2, padoenx : std_ulogic;
begin
gen0: if tech = 0 generate
x: scanregio_inf
generic map (hzsup,intesten)
port map (pado,padoen,padi,coreo,coreoen,corei,tck,tckn,tdi,tdo,
bsshft,bscapti,bsupdi,bsupdo,bsdrive,bshighz);
end generate;
map0: if tech /= 0 generate
x0: scanregi generic map (tech,intesten)
port map (padi, corei, tck, tckn, tdo1, tdo, bsshft, bscapti, bsupdi, bsdrive, bshighz);
x1: scanregto generic map (tech, hzsup, oepol, scantest)
port map (pado, padoen, coreo, coreo, coreoen,
tck, tckn, tdi, tdo1, bsshft, bscapto, bscaptoe, bsupdo, bsdrive, bshighz, testen, testoen);
end generate;
end;
| gpl-3.0 | f5b9e855d9b5bb550eb15cf552982ddb | 0.606196 | 3.439909 | false | true | false | false |
EliasLuiz/TCC | Leon3/lib/techmap/virage/memory_virage.vhd | 1 | 16,196 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: various
-- File: mem_virage_gen.vhd
-- Author: Jiri Gaisler Gaisler Research
-- Description: Memory generators for Virage rams
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library virage;
use virage.hdss1_128x32cm4sw0ab;
use virage.hdss1_256x32cm4sw0ab;
use virage.hdss1_512x32cm4sw0ab;
use virage.hdss1_512x38cm4sw0ab;
use virage.hdss1_1024x32cm4sw0ab;
use virage.hdss1_2048x32cm8sw0ab;
use virage.hdss1_4096x36cm8sw0ab;
use virage.hdss1_16384x8cm16sw0;
-- pragma translate_on
entity virage_syncram is
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector(abits -1 downto 0);
datain : in std_logic_vector(dbits -1 downto 0);
dataout : out std_logic_vector(dbits -1 downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end;
architecture rtl of virage_syncram is
component hdss1_128x32cm4sw0ab
port (
addr, taddr : in std_logic_vector(6 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(31 downto 0);
do : out std_logic_vector(31 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end component;
component hdss1_256x32cm4sw0ab
port (
addr, taddr : in std_logic_vector(7 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(31 downto 0);
do : out std_logic_vector(31 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end component;
component hdss1_512x32cm4sw0ab
port (
addr, taddr : in std_logic_vector(8 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(31 downto 0);
do : out std_logic_vector(31 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end component;
component hdss1_512x38cm4sw0ab
port (
addr, taddr : in std_logic_vector(8 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(37 downto 0);
do : out std_logic_vector(37 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end component;
component hdss1_1024x32cm4sw0ab
port (
addr, taddr : in std_logic_vector(9 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(31 downto 0);
do : out std_logic_vector(31 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end component;
component hdss1_2048x32cm8sw0ab
port (
addr, taddr : in std_logic_vector(10 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(31 downto 0);
do : out std_logic_vector(31 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end component;
component hdss1_4096x36cm8sw0ab is
port (
addr, taddr : in std_logic_vector(11 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(35 downto 0);
do : out std_logic_vector(35 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end component;
component hdss1_16384x8cm16sw0 is
port (
addr : in std_logic_vector(13 downto 0);
clk : in std_logic;
di : in std_logic_vector(7 downto 0);
do : out std_logic_vector(7 downto 0);
me, oe, we : in std_logic
);
end component;
signal d, q, gnd : std_logic_vector(40 downto 0);
signal a : std_logic_vector(17 downto 0);
signal vcc : std_ulogic;
constant synopsys_bug : std_logic_vector(40 downto 0) := (others => '0');
begin
gnd <= (others => '0'); vcc <= '1';
a(abits -1 downto 0) <= address;
d(dbits -1 downto 0) <= datain(dbits -1 downto 0);
a(17 downto abits) <= synopsys_bug(17 downto abits);
d(40 downto dbits) <= synopsys_bug(40 downto dbits);
dataout <= q(dbits -1 downto 0);
a7d32 : if (abits <= 7) and (dbits <= 32) generate
id0 : hdss1_128x32cm4sw0ab
port map (a(6 downto 0), gnd(6 downto 0),clk,
d(31 downto 0), gnd(31 downto 0), q(31 downto 0),
enable, vcc, write, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0));
end generate;
a8d32 : if (abits = 8) and (dbits <= 32) generate
id0 : hdss1_256x32cm4sw0ab
port map (a(7 downto 0), gnd(7 downto 0),clk,
d(31 downto 0), gnd(31 downto 0), q(31 downto 0),
enable, vcc, write, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0));
end generate;
a9d32 : if (abits = 9) and (dbits <= 32) generate
id0 : hdss1_512x32cm4sw0ab
port map (address(8 downto 0), gnd(8 downto 0),clk,
d(31 downto 0), gnd(31 downto 0), q(31 downto 0),
enable, vcc, write, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0));
end generate;
a9d38 : if (abits = 9) and (dbits > 32) and (dbits <= 38) generate
id0 : hdss1_512x38cm4sw0ab
port map (address(8 downto 0), gnd(8 downto 0),clk,
d(37 downto 0), gnd(37 downto 0), q(37 downto 0),
enable, vcc, write, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0));
end generate;
a10d32 : if (abits = 10) and (dbits <= 32) generate
id0 : hdss1_1024x32cm4sw0ab
port map (address(9 downto 0), gnd(9 downto 0), clk,
d(31 downto 0), gnd(31 downto 0), q(31 downto 0),
enable, vcc, write, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0));
end generate;
a11d32 : if (abits = 11) and (dbits <= 32) generate
id0 : hdss1_2048x32cm8sw0ab
port map (address(10 downto 0), gnd(10 downto 0), clk,
d(31 downto 0), gnd(31 downto 0), q(31 downto 0),
enable, vcc, write, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0));
end generate;
a12d36 : if (abits = 12) and (dbits <= 36) generate
id0 : hdss1_4096x36cm8sw0ab
port map (address(11 downto 0), gnd(11 downto 0), clk,
d(35 downto 0), gnd(35 downto 0), q(35 downto 0),
enable, vcc, write, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0));
end generate;
a14d8 : if (abits = 14) and (dbits <= 8) generate
id0 : hdss1_16384x8cm16sw0
port map (address(13 downto 0), clk,
d(7 downto 0), q(7 downto 0),
enable, vcc, Write);
end generate;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library virage;
use virage.hdss2_64x32cm4sw0ab;
use virage.hdss2_128x32cm4sw0ab;
use virage.hdss2_256x32cm4sw0ab;
use virage.hdss2_512x32cm4sw0ab;
use virage.hdss2_512x38cm4sw0ab;
use virage.hdss2_8192x8cm16sw0ab;
-- pragma translate_on
entity virage_syncram_dp is
generic ( abits : integer := 10; dbits : integer := 8);
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic
);
end;
architecture rtl of virage_syncram_dp is
component hdss2_64x32cm4sw0ab
port (
addra, taddra : in std_logic_vector(5 downto 0);
addrb, taddrb : in std_logic_vector(5 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(31 downto 0);
dib, tdib : in std_logic_vector(31 downto 0);
doa, dob : out std_logic_vector(31 downto 0);
mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
);
end component;
component hdss2_128x32cm4sw0ab
port (
addra, taddra : in std_logic_vector(6 downto 0);
addrb, taddrb : in std_logic_vector(6 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(31 downto 0);
dib, tdib : in std_logic_vector(31 downto 0);
doa, dob : out std_logic_vector(31 downto 0);
mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
);
end component;
component hdss2_256x32cm4sw0ab
port (
addra, taddra : in std_logic_vector(7 downto 0);
addrb, taddrb : in std_logic_vector(7 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(31 downto 0);
dib, tdib : in std_logic_vector(31 downto 0);
doa, dob : out std_logic_vector(31 downto 0);
mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
);
end component;
component hdss2_512x32cm4sw0ab
port (
addra, taddra : in std_logic_vector(8 downto 0);
addrb, taddrb : in std_logic_vector(8 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(31 downto 0);
dib, tdib : in std_logic_vector(31 downto 0);
doa, dob : out std_logic_vector(31 downto 0);
mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
);
end component;
component hdss2_512x38cm4sw0ab
port (
addra, taddra : in std_logic_vector(8 downto 0);
addrb, taddrb : in std_logic_vector(8 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(37 downto 0);
dib, tdib : in std_logic_vector(37 downto 0);
doa, dob : out std_logic_vector(37 downto 0);
mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
);
end component;
component hdss2_8192x8cm16sw0ab
port (
addra, taddra : in std_logic_vector(12 downto 0);
addrb, taddrb : in std_logic_vector(12 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(7 downto 0);
dib, tdib : in std_logic_vector(7 downto 0);
doa, dob : out std_logic_vector(7 downto 0);
mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
);
end component;
signal vcc : std_ulogic;
signal d1, d2, a1, a2, q1, q2, gnd : std_logic_vector(40 downto 0);
begin
vcc <= '1'; gnd <= (others => '0');
d1(dbits-1 downto 0) <= datain1; d1(40 downto dbits) <= (others => '0');
d2(dbits-1 downto 0) <= datain2; d2(40 downto dbits) <= (others => '0');
a1(abits-1 downto 0) <= address1; a1(40 downto abits) <= (others => '0');
a2(abits-1 downto 0) <= address2; a2(40 downto abits) <= (others => '0');
dataout1 <= q1(dbits-1 downto 0); dataout2 <= q2(dbits-1 downto 0);
a6d32 : if (abits <= 6) and (dbits <= 32) generate
id0 : hdss2_64x32cm4sw0ab
port map (a1(5 downto 0), gnd(5 downto 0), a2(5 downto 0),
gnd(5 downto 0), clk1, clk2,
d1(31 downto 0), gnd(31 downto 0), d2(31 downto 0), gnd(31 downto 0),
q1(31 downto 0), q2(31 downto 0),
enable1, vcc, write1, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0),
enable2, vcc, write2, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0));
end generate;
a7d32 : if (abits = 7) and (dbits <= 32) generate
id0 : hdss2_128x32cm4sw0ab
port map (a1(6 downto 0), gnd(6 downto 0), a2(6 downto 0),
gnd(6 downto 0), clk1, clk2,
d1(31 downto 0), gnd(31 downto 0), d2(31 downto 0), gnd(31 downto 0),
q1(31 downto 0), q2(31 downto 0),
enable1, vcc, write1, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0),
enable2, vcc, write2, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0));
end generate;
a8d32 : if (abits = 8) and (dbits <= 32) generate
id0 : hdss2_256x32cm4sw0ab
port map (a1(7 downto 0), gnd(7 downto 0), a2(7 downto 0),
gnd(7 downto 0), clk1, clk2,
d1(31 downto 0), gnd(31 downto 0), d2(31 downto 0), gnd(31 downto 0),
q1(31 downto 0), q2(31 downto 0),
enable1, vcc, write1, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0),
enable2, vcc, write2, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0));
end generate;
a9d32 : if (abits = 9) and (dbits <= 32) generate
id0 : hdss2_512x32cm4sw0ab
port map (a1(8 downto 0), gnd(8 downto 0), a2(8 downto 0),
gnd(8 downto 0), clk1, clk2,
d1(31 downto 0), gnd(31 downto 0), d2(31 downto 0), gnd(31 downto 0),
q1(31 downto 0), q2(31 downto 0),
enable1, vcc, write1, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0),
enable2, vcc, write2, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0));
end generate;
a9d38 : if (abits = 9) and (dbits > 32) and (dbits <= 38) generate
id0 : hdss2_512x38cm4sw0ab
port map (a1(8 downto 0), gnd(8 downto 0), a2(8 downto 0),
gnd(8 downto 0), clk1, clk2,
d1(37 downto 0), gnd(37 downto 0), d2(37 downto 0), gnd(37 downto 0),
q1(37 downto 0), q2(37 downto 0),
enable1, vcc, write1, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0),
enable2, vcc, write2, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0));
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library virage;
use virage.rfss2_136x32cm2sw0ab;
use virage.rfss2_136x40cm2sw0ab;
use virage.rfss2_168x32cm2sw0ab;
use virage.hdss2_64x32cm4sw0ab;
use virage.hdss2_128x32cm4sw0ab;
use virage.hdss2_256x32cm4sw0ab;
use virage.hdss2_512x32cm4sw0ab;
use virage.hdss2_8192x8cm16sw0ab;
-- pragma translate_on
entity virage_syncram_2p is
generic ( abits : integer := 6; dbits : integer := 8;
sepclk : integer := 0; wrfst : integer := 0);
port (
rclk : in std_ulogic;
renable : in std_ulogic;
raddress : in std_logic_vector((abits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
wclk : in std_ulogic;
write : in std_ulogic;
waddress : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0));
end;
architecture rtl of virage_syncram_2p is
component rfss2_136x32cm2sw0ab
port (
addra, taddra : in std_logic_vector(7 downto 0);
addrb, taddrb : in std_logic_vector(7 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(31 downto 0);
dob : out std_logic_vector(31 downto 0);
mea, wea, tmea, twea, bistea : in std_logic;
meb, oeb, tmeb, awtb, bisteb, toeb : in std_logic
);
end component;
component rfss2_136x40cm2sw0ab
port (
addra, taddra : in std_logic_vector(7 downto 0);
addrb, taddrb : in std_logic_vector(7 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(39 downto 0);
dob : out std_logic_vector(39 downto 0);
mea, wea, tmea, twea, bistea : in std_logic;
meb, oeb, tmeb, awtb, bisteb, toeb : in std_logic
);
end component;
signal vcc : std_ulogic;
signal d1, a1, a2, q1, gnd : std_logic_vector(40 downto 0);
begin
vcc <= '1'; gnd <= (others => '0');
d1(dbits-1 downto 0) <= datain; d1(40 downto dbits) <= (others => '0');
a1(abits-1 downto 0) <= waddress; a1(40 downto abits) <= (others => '0');
a2(abits-1 downto 0) <= raddress; a2(40 downto abits) <= (others => '0');
dataout <= q1(dbits-1 downto 0);
id0 : rfss2_136x40cm2sw0ab
port map (
a1(7 downto 0), gnd(7 downto 0), a2(7 downto 0), gnd(7 downto 0),
wclk, rclk, d1(39 downto 0), gnd(39 downto 0),
q1(39 downto 0),
vcc, write, gnd(0), gnd(0), gnd(0),
renable, vcc, gnd(0), gnd(0), gnd(0), gnd(0));
end;
| gpl-3.0 | 543d071c5bdd9b68ccc2b7938d995a68 | 0.621388 | 2.916622 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-terasic-sockit/config.vhd | 1 | 5,561 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := altera;
constant CFG_MEMTECH : integer := altera;
constant CFG_PADTECH : integer := altera;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := altera;
constant CFG_CLKMUL : integer := (7);
constant CFG_CLKDIV : integer := (5);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 2 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 0;
constant CFG_SVT : integer := 0;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (0);
constant CFG_PWD : integer := 0*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 8;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0 + 1*2 + 4*1;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 16;
constant CFG_DTLBNUM : integer := 16;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 1 + 64*0;
constant CFG_ATBSZ : integer := 1;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_STAT_ENABLE : integer := 0;
constant CFG_STAT_CNT : integer := 1;
constant CFG_STAT_NMAX : integer := 0;
constant CFG_STAT_DSUEN : integer := 0;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
constant CFG_ALTWIN : integer := 0;
constant CFG_REX : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 0;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 0 + 0 + 0;
constant CFG_ETH_BUF : integer := 1;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000009#;
-- AHB ROM
constant CFG_AHBROMEN : integer := 1;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#100#;
constant CFG_ROMMASK : integer := 16#E00# + 16#100#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 0;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := 1;
-- HPS
constant CFG_HPS2FPGA : integer := 1;
constant CFG_FPGA2HPS : integer := 1;
constant CFG_HPS_RESET : integer := 0;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-3.0 | 0c456b1899b457e64a17631a1bf838d0 | 0.640352 | 3.629896 | false | false | false | false |
EliasLuiz/TCC | Teste/MemoTableTOutputWay.vhd | 1 | 10,381 | -- megafunction wizard: %RAM: 2-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: MemoTableTOutput.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any Output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
use work.Constants.all;
use work.DefTypes.all;
ENTITY MemoTableTOutputWay IS
--ENTITY TraceMemory IS
PORT
(
Clock : IN STD_LOGIC := '1';
WAddress : IN STD_LOGIC_VECTOR (MemoTableTWayAddressLenght-1 DOWNTO 0);
WData : IN MemoTableTOutputEntry;
--WData : IN STD_LOGIC_VECTOR (MemoTableTOutputEntryWidth-1 DOWNTO 0);
WEnable : IN STD_LOGIC := '0';
RAddress : IN STD_LOGIC_VECTOR (MemoTableTWayAddressLenght-1 DOWNTO 0);
RData : OUT MemoTableTOutputEntry
--RData : OUT STD_LOGIC_VECTOR (MemoTableTOutputEntryWidth-1 DOWNTO 0)
);
END MemoTableTOutputWay;
--END TraceMemory;
ARCHITECTURE SYN OF MemoTableTOutputWay IS
--ARCHITECTURE SYN OF TraceMemory IS
SIGNAL RAuxVector : STD_LOGIC_VECTOR (MemoTableTOutputEntryWidth-1 DOWNTO 0);
SIGNAL WAuxObject : MemoTableTOutputEntry;
SIGNAL WAuxVector : STD_LOGIC_VECTOR (MemoTableTOutputEntryWidth-1 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
address_reg_b : STRING;
clock_enable_input_a : STRING;
clock_enable_input_b : STRING;
clock_enable_output_a : STRING;
clock_enable_output_b : STRING;
intended_device_family : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
numwords_b : NATURAL;
operation_mode : STRING;
outdata_aclr_b : STRING;
outdata_reg_b : STRING;
power_up_uninitialized : STRING;
read_during_write_mode_mixed_ports : STRING;
widthad_a : NATURAL;
widthad_b : NATURAL;
width_a : NATURAL;
width_b : NATURAL;
width_byteena_a : NATURAL
);
PORT (
address_a: IN STD_LOGIC_VECTOR (MemoTableTWayAddressLenght-1 DOWNTO 0);
clock0 : IN STD_LOGIC;
data_a : IN STD_LOGIC_VECTOR (MemoTableTOutputEntryWidth-1 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (MemoTableTOutputEntryWidth-1 DOWNTO 0);
wren_a : IN STD_LOGIC;
address_b: IN STD_LOGIC_VECTOR (MemoTableTWayAddressLenght-1 DOWNTO 0)
);
END COMPONENT;
BEGIN
--RData <= RAuxVector;
RData <= StdLogicToOutput(RAuxVector);
--WAuxVector <= WData;
WAuxObject <= WData;
WAuxVector <= OutputToStdLogic(WAuxObject);
altsyncram_component : altsyncram
GENERIC MAP (
address_reg_b => "CLOCK0",
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
intended_device_family => "Cyclone II",
lpm_type => "altsyncram",
numwords_a => MemoTableTWayLenght,
numwords_b => MemoTableTWayLenght,
operation_mode => "DUAL_PORT",
outdata_aclr_b => "NONE",
outdata_reg_b => "CLOCK0",
power_up_uninitialized => "FALSE",
read_during_write_mode_mixed_ports => "DONT_CARE",
widthad_a => MemoTableTWayAddressLenght,
widthad_b => MemoTableTWayAddressLenght,
width_a => MemoTableTOutputEntryWidth,
width_b => MemoTableTOutputEntryWidth,
width_byteena_a => 1
)
PORT MAP (
address_a => WAddress,
clock0 => Clock,
data_a => WAuxVector,
wren_a => WEnable,
address_b => RAddress,
q_b => RAuxVector
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_Output_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_Output_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
-- Retrieval info: PRIVATE: CLRq NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "4096"
-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "1"
-- Retrieval info: PRIVATE: MIFfilename STRING ""
-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
-- Retrieval info: PRIVATE: REGq NUMERIC "1"
-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGrren NUMERIC "1"
-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "1"
-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
-- Retrieval info: PRIVATE: VarWidth NUMERIC "0"
-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "64"
-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "64"
-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "64"
-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "64"
-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: enable NUMERIC "0"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_Output_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_Output_B STRING "BYPASS"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "64"
-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "64"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "6"
-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "6"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "64"
-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "64"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: data 0 0 64 0 INPUT NODEFVAL "data[MemoTableTOutputEntryWidth-1..0]"
-- Retrieval info: USED_PORT: q 0 0 64 0 Output NODEFVAL "q[MemoTableTOutputEntryWidth-1..0]"
-- Retrieval info: USED_PORT: rdaddress 0 0 6 0 INPUT NODEFVAL "rdaddress[MemoTableTWayAddressLenght-1..0]"
-- Retrieval info: USED_PORT: wraddress 0 0 6 0 INPUT NODEFVAL "wraddress[MemoTableTWayAddressLenght-1..0]"
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
-- Retrieval info: CONNECT: @address_a 0 0 6 0 wraddress 0 0 6 0
-- Retrieval info: CONNECT: @address_b 0 0 6 0 rdaddress 0 0 6 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 64 0 data 0 0 64 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 64 0 @q_b 0 0 64 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL MemoTableTOutput.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL MemoTableTOutput.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL MemoTableTOutput.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL MemoTableTOutput.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL MemoTableTOutput_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL MemoTableTOutput_syn.v TRUE
-- Retrieval info: LIB_FILE: altera_mf
| gpl-3.0 | a265d69b18fe25afe4418d302df083a7 | 0.698584 | 3.380332 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-clock-gate/leon3mp.vhd | 1 | 36,141 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.can.all;
use gaisler.pci.all;
use gaisler.net.all;
use gaisler.jtag.all;
use gaisler.spacewire.all;
library esa;
use esa.memoryctrl.all;
use esa.pcicomp.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
resetn : in std_logic;
clk : in std_logic;
pllref : in std_logic;
errorn : out std_logic;
address : out std_logic_vector(27 downto 0);
data : inout std_logic_vector(31 downto 0);
sa : out std_logic_vector(14 downto 0);
sd : inout std_logic_vector(63 downto 0);
sdclk : out std_logic;
sdcke : out std_logic_vector (1 downto 0); -- sdram clock enable
sdcsn : out std_logic_vector (1 downto 0); -- sdram chip select
sdwen : out std_logic; -- sdram write enable
sdrasn : out std_logic; -- sdram ras
sdcasn : out std_logic; -- sdram cas
sddqm : out std_logic_vector (7 downto 0); -- sdram dqm
dsutx : out std_logic; -- DSU tx data
dsurx : in std_logic; -- DSU rx data
dsuen : in std_logic;
dsubre : in std_logic;
dsuact : out std_logic;
txd1 : out std_logic; -- UART1 tx data
rxd1 : in std_logic; -- UART1 rx data
txd2 : out std_logic; -- UART2 tx data
rxd2 : in std_logic; -- UART2 rx data
ramsn : out std_logic_vector (4 downto 0);
ramoen : out std_logic_vector (4 downto 0);
rwen : out std_logic_vector (3 downto 0);
oen : out std_logic;
writen : out std_logic;
read : out std_logic;
iosn : out std_logic;
romsn : out std_logic_vector (1 downto 0);
gpio : inout std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- I/O port
emdio : inout std_logic; -- ethernet PHY interface
etx_clk : in std_logic;
erx_clk : in std_logic;
erxd : in std_logic_vector(3 downto 0);
erx_dv : in std_logic;
erx_er : in std_logic;
erx_col : in std_logic;
erx_crs : in std_logic;
etxd : out std_logic_vector(3 downto 0);
etx_en : out std_logic;
etx_er : out std_logic;
emdc : out std_logic;
emddis : out std_logic;
epwrdwn : out std_logic;
ereset : out std_logic;
esleep : out std_logic;
epause : out std_logic;
pci_rst : inout std_logic; -- PCI bus
pci_clk : in std_logic;
pci_gnt : in std_logic;
pci_idsel : in std_logic;
pci_lock : inout std_logic;
pci_ad : inout std_logic_vector(31 downto 0);
pci_cbe : inout std_logic_vector(3 downto 0);
pci_frame : inout std_logic;
pci_irdy : inout std_logic;
pci_trdy : inout std_logic;
pci_devsel : inout std_logic;
pci_stop : inout std_logic;
pci_perr : inout std_logic;
pci_par : inout std_logic;
pci_req : inout std_logic;
pci_serr : inout std_logic;
pci_host : in std_logic;
pci_66 : in std_logic;
pci_arb_req : in std_logic_vector(0 to 3);
pci_arb_gnt : out std_logic_vector(0 to 3);
can_txd : out std_logic;
can_rxd : in std_logic;
can_stb : out std_logic;
spw_clk : in std_logic;
spw_rxd : in std_logic_vector(0 to 2);
spw_rxdn : in std_logic_vector(0 to 2);
spw_rxs : in std_logic_vector(0 to 2);
spw_rxsn : in std_logic_vector(0 to 2);
spw_txd : out std_logic_vector(0 to 2);
spw_txdn : out std_logic_vector(0 to 2);
spw_txs : out std_logic_vector(0 to 2);
spw_txsn : out std_logic_vector(0 to 2);
tck, tms, tdi : in std_logic;
tdo : out std_logic
);
end;
architecture rtl of leon3mp is
constant blength : integer := 12;
constant maxahbmsp : integer := NCPU+CFG_AHB_UART+
CFG_GRETH+CFG_AHB_JTAG+CFG_GRPCI2_TARGET+CFG_GRPCI2_DMA;
constant maxahbm : integer := (CFG_SPW_NUM*CFG_SPW_EN) + maxahbmsp;
signal vcc, gnd : std_logic_vector(4 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal sdo2, sdo3 : sdctrl_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkx, clkm, rstn, rstraw, pciclk, sdclkl, spw_lclk : std_logic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, u2i, dui : uart_in_type;
signal u1o, u2o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to NCPU-1);
signal irqo : irq_out_vector(0 to NCPU-1);
signal dbgi : l3_debug_in_vector(0 to NCPU-1);
signal dbgo : l3_debug_out_vector(0 to NCPU-1);
signal gclk : std_logic_vector(NCPU-1 downto 0);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal pcii : pci_in_type;
signal pcio : pci_out_type;
signal ethi, ethi1, ethi2 : eth_in_type;
signal etho, etho1, etho2 : eth_out_type;
signal gpti : gptimer_in_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal can_lrx, can_ltx : std_logic;
signal lclk, pci_lclk : std_logic;
signal pci_arb_req_n, pci_arb_gnt_n : std_logic_vector(0 to 3);
signal pci_dirq : std_logic_vector(3 downto 0);
signal spwi : grspw_in_type_vector(0 to 2);
signal spwo : grspw_out_type_vector(0 to 2);
signal spw_rxclk : std_logic_vector(0 to CFG_SPW_NUM-1);
signal dtmp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal stmp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_rxtxclk : std_ulogic;
signal spw_rxclkn : std_ulogic;
constant BOARD_FREQ : integer := 40000; -- Board frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV;
constant IOAEN : integer := CFG_SDCTRL + CFG_CAN + CFG_GRPCI2_MASTER;
constant CFG_SDEN : integer := CFG_SDCTRL + CFG_MCTRL_SDEN ;
constant sysfreq : integer := (CFG_CLKMUL/CFG_CLKDIV)*40000;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
pllref_pad : clkpad generic map (tech => padtech) port map (pllref, cgi.pllref);
clk_pad : clkpad generic map (tech => padtech) port map (clk, lclk);
pci_clk_pad : clkpad generic map (tech => padtech, level => pci33)
port map (pci_clk, pci_lclk);
clkgen0 : clkgen -- clock generator
generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_SDEN,
CFG_CLK_NOFB, (CFG_GRPCI2_MASTER+CFG_GRPCI2_TARGET), CFG_PCIDLL, CFG_PCISYSCLK)
port map (lclk, pci_lclk, clkx, open, open, sdclkl, pciclk, cgi, cgo);
clkpwd : entity work.clkgate generic map (fabtech, NCPU, CFG_DSU)
port map (rstn, clkx, dsuo.pwd(NCPU-1 downto 0), clkm, gclk);
sdclk_pad : outpad generic map (tech => padtech, slew => 1, strength => 24)
port map (sdclk, sdclkl);
rst0 : rstgen -- reset generator
port map (resetn, clkm, cgo.clklock, rstn, rstraw);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to NCPU-1 generate
u0 : leon3cg -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, NCPU-1, CFG_DFIXED,
CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), gclk(i));
nodsu : if CFG_DSU = 0 generate
dsuo.pwd(i) <= dbgo(i).pwd and not dbgo(i).ipend;
end generate;
end generate;
errorn_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable);
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
dbgi <= (others => dbgi_none);
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0: ahbuart -- Debug UART
generic map (hindex => NCPU, pindex => 7, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (dsurx, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (dsutx, duo.txd);
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
src : if CFG_SRCTRL = 1 generate -- 32-bit PROM/SRAM controller
sr0 : srctrl generic map (hindex => 0, ramws => CFG_SRCTRL_RAMWS,
romws => CFG_SRCTRL_PROMWS, ramaddr => 16#400#,
prom8en => CFG_SRCTRL_8BIT, rmw => CFG_SRCTRL_RMW)
port map (rstn, clkm, ahbsi, ahbso(0), memi, memo, sdo3);
apbo(0) <= apb_none;
end generate;
sdc : if CFG_SDCTRL = 1 generate
sdc : sdctrl generic map (hindex => 3, haddr => 16#600#, hmask => 16#F00#,
ioaddr => 1, fast => 0, pwron => 0, invclk => CFG_SDCTRL_INVCLK,
sdbits => 32 + 32*CFG_SDCTRL_SD64)
port map (rstn, clkm, ahbsi, ahbso(3), sdi, sdo2);
sa_pad : outpadv generic map (width => 15, tech => padtech)
port map (sa, sdo2.address);
sd_pad : iopadv generic map (width => 32, tech => padtech)
port map (sd(31 downto 0), sdo2.data, sdo2.bdrive, sdi.data(31 downto 0));
sd2 : if CFG_SDCTRL_SD64 = 1 generate
sd_pad2 : iopadv generic map (width => 32)
port map (sd(63 downto 32), sdo2.data, sdo2.bdrive, sdi.data(63 downto 32));
end generate;
sdcke_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcke, sdo2.sdcke);
sdwen_pad : outpad generic map (tech => padtech)
port map (sdwen, sdo2.sdwen);
sdcsn_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcsn, sdo2.sdcsn);
sdras_pad : outpad generic map (tech => padtech)
port map (sdrasn, sdo2.rasn);
sdcas_pad : outpad generic map (tech => padtech)
port map (sdcasn, sdo2.casn);
sddqm_pad : outpadv generic map (width =>8, tech => padtech)
port map (sddqm, sdo2.dqm);
end generate;
mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 : mctrl generic map (hindex => 0, pindex => 0, paddr => 0,
srbanks => 4+CFG_MCTRL_5CS, sden => CFG_MCTRL_SDEN,
ram8 => CFG_MCTRL_RAM8BIT, ram16 => CFG_MCTRL_RAM16BIT,
invclk => CFG_MCTRL_INVCLK, sepbus => CFG_MCTRL_SEPBUS,
sdbits => 32 + 32*CFG_MCTRL_SD64)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
sdpads : if CFG_MCTRL_SDEN = 1 generate -- SDRAM controller
sd2 : if CFG_MCTRL_SEPBUS = 1 generate
sa_pad : outpadv generic map (width => 15) port map (sa, memo.sa);
bdr : for i in 0 to 3 generate
sd_pad : iopadv generic map (tech => padtech, width => 8)
port map (sd(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.sd(31-i*8 downto 24-i*8));
sd2 : if CFG_MCTRL_SD64 = 1 generate
sd_pad2 : iopadv generic map (tech => padtech, width => 8)
port map (sd(31-i*8+32 downto 24-i*8+32), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.sd(31-i*8+32 downto 24-i*8+32));
end generate;
end generate;
end generate;
sdwen_pad : outpad generic map (tech => padtech)
port map (sdwen, sdo.sdwen);
sdras_pad : outpad generic map (tech => padtech)
port map (sdrasn, sdo.rasn);
sdcas_pad : outpad generic map (tech => padtech)
port map (sdcasn, sdo.casn);
sddqm_pad : outpadv generic map (width =>8, tech => padtech)
port map (sddqm, sdo.dqm);
sdcke_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcke, sdo.sdcke);
sdcsn_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcsn, sdo.sdcsn);
end generate;
end generate;
nosd0 : if (CFG_MCTRL_SDEN = 0) and (CFG_SDCTRL = 0) generate -- no SDRAM controller
sdcke_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcke, vcc(1 downto 0));
sdcsn_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcsn, vcc(1 downto 0));
end generate;
memi.brdyn <= '1'; memi.bexcn <= '1';
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "10";
mgpads : if (CFG_SRCTRL = 1) or (CFG_MCTRL_LEON2 = 1) generate -- prom/sram pads
addr_pad : outpadv generic map (width => 28, tech => padtech)
port map (address, memo.address(27 downto 0));
rams_pad : outpadv generic map (width => 5, tech => padtech)
port map (ramsn, memo.ramsn(4 downto 0));
roms_pad : outpadv generic map (width => 2, tech => padtech)
port map (romsn, memo.romsn(1 downto 0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.oen);
rwen_pad : outpadv generic map (width => 4, tech => padtech)
port map (rwen, memo.wrn);
roen_pad : outpadv generic map (width => 5, tech => padtech)
port map (ramoen, memo.ramoen(4 downto 0));
wri_pad : outpad generic map (tech => padtech)
port map (writen, memo.writen);
read_pad : outpad generic map (tech => padtech)
port map (read, memo.read);
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
bdr : for i in 0 to 3 generate
data_pad : iopadv generic map (tech => padtech, width => 8)
port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.data(31-i*8 downto 24-i*8));
end generate;
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 5, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(5));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(5) <= ahbs_none;
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd1; u1i.ctsn <= '0'; u1i.extclk <= '0'; txd1 <= u1o.txd;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
ua2 : if CFG_UART2_ENABLE /= 0 generate
uart2 : apbuart -- UART 2
generic map (pindex => 9, paddr => 9, pirq => 3, fifosize => CFG_UART2_FIFO)
port map (rstn, clkm, apbi, apbo(9), u2i, u2o);
u2i.rxd <= rxd2; u2i.ctsn <= '0'; u2i.extclk <= '0'; txd2 <= u2o.txd;
end generate;
noua1 : if CFG_UART2_ENABLE = 0 generate apbo(9) <= apb_none; end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
pci_dirq(3 downto 1) <= (others => '0');
pci_dirq(0) <= orv(irqi(0).irl);
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW, wdog => CFG_GPT_WDOG)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti <= gpti_dhalt_drive(dsuo.tstop);
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit
grgpio0: grgpio
generic map( pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK,
nbits => CFG_GRGPIO_WIDTH)
port map( rstn, clkm, apbi, apbo(11), gpioi, gpioo);
pio_pads : for i in 0 to CFG_GRGPIO_WIDTH-1 generate
pio_pad : iopad generic map (tech => padtech)
port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
-----------------------------------------------------------------------
--- PCI ------------------------------------------------------------
-----------------------------------------------------------------------
pp0 : if (CFG_GRPCI2_MASTER+CFG_GRPCI2_TARGET) /= 0 generate
grpci2xt : if (CFG_GRPCI2_TARGET) /= 0 and (CFG_GRPCI2_MASTER+CFG_GRPCI2_DMA) = 0 generate
pci0 : grpci2
generic map (
memtech => memtech,
hmindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
hdmindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1,
hsindex => 4, haddr => 16#C00#, hmask => 16#E00#, ioaddr => 16#400#,
pindex => 4, paddr => 4, irq => 4, irqmode => 0,
master => CFG_GRPCI2_MASTER, target => CFG_GRPCI2_TARGET,
dma => CFG_GRPCI2_DMA, tracebuffer => CFG_GRPCI2_TRACE,
vendorid => CFG_GRPCI2_VID, deviceid => CFG_GRPCI2_DID,
classcode => CFG_GRPCI2_CLASS, revisionid => CFG_GRPCI2_RID,
cap_pointer => CFG_GRPCI2_CAP, ext_cap_pointer => CFG_GRPCI2_NCAP,
iobase => CFG_AHBIO, extcfg => CFG_GRPCI2_EXTCFG,
bar0 => CFG_GRPCI2_BAR0, bar1 => CFG_GRPCI2_BAR1,
bar2 => CFG_GRPCI2_BAR2, bar3 => CFG_GRPCI2_BAR3,
bar4 => CFG_GRPCI2_BAR4, bar5 => CFG_GRPCI2_BAR5,
fifo_depth => CFG_GRPCI2_FDEPTH, fifo_count => CFG_GRPCI2_FCOUNT,
conv_endian => CFG_GRPCI2_ENDIAN, deviceirq => CFG_GRPCI2_DEVINT,
deviceirqmask => CFG_GRPCI2_DEVINTMSK, hostirq => CFG_GRPCI2_HOSTINT,
hostirqmask => CFG_GRPCI2_HOSTINTMSK,
nsync => 2, hostrst => 1, bypass => CFG_GRPCI2_BYPASS,
debug => 0, tbapben => 0, tbpindex => 5, tbpaddr => 16#400#, tbpmask => 16#C00#
)
port map (
rstn, clkm, pciclk, pci_dirq, pcii, pcio, apbi, apbo(4), ahbsi, open, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), ahbmi,
open, open, open, open, open);
end generate;
grpci2xmt : if (CFG_GRPCI2_MASTER+CFG_GRPCI2_TARGET) > 1 and (CFG_GRPCI2_DMA) = 0 generate
pci0 : grpci2
generic map (
memtech => memtech,
hmindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
hdmindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1,
hsindex => 4, haddr => 16#C00#, hmask => 16#E00#, ioaddr => 16#400#,
pindex => 4, paddr => 4, irq => 4, irqmode => 0,
master => CFG_GRPCI2_MASTER, target => CFG_GRPCI2_TARGET,
dma => CFG_GRPCI2_DMA, tracebuffer => CFG_GRPCI2_TRACE,
vendorid => CFG_GRPCI2_VID, deviceid => CFG_GRPCI2_DID,
classcode => CFG_GRPCI2_CLASS, revisionid => CFG_GRPCI2_RID,
cap_pointer => CFG_GRPCI2_CAP, ext_cap_pointer => CFG_GRPCI2_NCAP,
iobase => CFG_AHBIO, extcfg => CFG_GRPCI2_EXTCFG,
bar0 => CFG_GRPCI2_BAR0, bar1 => CFG_GRPCI2_BAR1,
bar2 => CFG_GRPCI2_BAR2, bar3 => CFG_GRPCI2_BAR3,
bar4 => CFG_GRPCI2_BAR4, bar5 => CFG_GRPCI2_BAR5,
fifo_depth => CFG_GRPCI2_FDEPTH, fifo_count => CFG_GRPCI2_FCOUNT,
conv_endian => CFG_GRPCI2_ENDIAN, deviceirq => CFG_GRPCI2_DEVINT,
deviceirqmask => CFG_GRPCI2_DEVINTMSK, hostirq => CFG_GRPCI2_HOSTINT,
hostirqmask => CFG_GRPCI2_HOSTINTMSK,
nsync => 2, hostrst => 1, bypass => CFG_GRPCI2_BYPASS,
debug => 0, tbapben => 0, tbpindex => 5, tbpaddr => 16#400#, tbpmask => 16#C00#
)
port map (
rstn, clkm, pciclk, pci_dirq, pcii, pcio, apbi, apbo(4), ahbsi, ahbso(4), ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), ahbmi,
open, open, open, open, open);
end generate;
grpci2xd : if (CFG_GRPCI2_MASTER+CFG_GRPCI2_TARGET) /= 0 and CFG_GRPCI2_DMA /= 0 generate
pci0 : grpci2
generic map (
memtech => memtech,
hmindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
hdmindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1,
hsindex => 4, haddr => 16#C00#, hmask => 16#E00#, ioaddr => 16#400#,
pindex => 4, paddr => 4, irq => 4, irqmode => 0,
master => CFG_GRPCI2_MASTER, target => CFG_GRPCI2_TARGET,
dma => CFG_GRPCI2_DMA, tracebuffer => CFG_GRPCI2_TRACE,
vendorid => CFG_GRPCI2_VID, deviceid => CFG_GRPCI2_DID,
classcode => CFG_GRPCI2_CLASS, revisionid => CFG_GRPCI2_RID,
cap_pointer => CFG_GRPCI2_CAP, ext_cap_pointer => CFG_GRPCI2_NCAP,
iobase => CFG_AHBIO, extcfg => CFG_GRPCI2_EXTCFG,
bar0 => CFG_GRPCI2_BAR0, bar1 => CFG_GRPCI2_BAR1,
bar2 => CFG_GRPCI2_BAR2, bar3 => CFG_GRPCI2_BAR3,
bar4 => CFG_GRPCI2_BAR4, bar5 => CFG_GRPCI2_BAR5,
fifo_depth => CFG_GRPCI2_FDEPTH, fifo_count => CFG_GRPCI2_FCOUNT,
conv_endian => CFG_GRPCI2_ENDIAN, deviceirq => CFG_GRPCI2_DEVINT,
deviceirqmask => CFG_GRPCI2_DEVINTMSK, hostirq => CFG_GRPCI2_HOSTINT,
hostirqmask => CFG_GRPCI2_HOSTINTMSK,
nsync => 2, hostrst => 1, bypass => CFG_GRPCI2_BYPASS,
debug => 0, tbapben => 0, tbpindex => 5, tbpaddr => 16#400#, tbpmask => 16#C00#
)
port map (
rstn, clkm, pciclk, pci_dirq, pcii, pcio, apbi, apbo(4), ahbsi, ahbso(4), ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1),
open, open, open, open);
end generate;
pcia0 : if CFG_PCI_ARB = 1 generate -- PCI arbiter
pciarb0 : pciarb generic map (pindex => 10, paddr => 10,
apb_en => CFG_PCI_ARBAPB)
port map ( clk => pciclk, rst_n => pcii.rst,
req_n => pci_arb_req_n, frame_n => pcii.frame,
gnt_n => pci_arb_gnt_n, pclk => clkm,
prst_n => rstn, apbi => apbi, apbo => apbo(10)
);
pgnt_pad : outpadv generic map (tech => padtech, width => 4)
port map (pci_arb_gnt, pci_arb_gnt_n);
preq_pad : inpadv generic map (tech => padtech, width => 4)
port map (pci_arb_req, pci_arb_req_n);
end generate;
pcipads0 : pcipads generic map (padtech => padtech) -- PCI pads
port map ( pci_rst, pci_gnt, pci_idsel, pci_lock, pci_ad, pci_cbe,
pci_frame, pci_irdy, pci_trdy, pci_devsel, pci_stop, pci_perr,
pci_par, pci_req, pci_serr, pci_host, pci_66, pcii, pcio );
end generate;
nop1 : if CFG_GRPCI2_MASTER = 0 generate ahbso(4) <= ahbs_none; end generate;
nop2 : if CFG_GRPCI2_MASTER+CFG_GRPCI2_TARGET = 0 generate
apbo(4) <= apb_none; apbo(5) <= apb_none; end generate;
noarb : if CFG_PCI_ARB = 0 generate apbo(10) <= apb_none; end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : greth generic map(hindex => NCPU+CFG_AHB_UART+CFG_GRPCI2_TARGET+CFG_GRPCI2_DMA+CFG_AHB_JTAG,
pindex => 15, paddr => 15, pirq => 7, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(NCPU+CFG_AHB_UART+CFG_GRPCI2_TARGET+CFG_GRPCI2_DMA+CFG_AHB_JTAG), apbi => apbi,
apbo => apbo(15), ethi => ethi, etho => etho);
emdio_pad : iopad generic map (tech => padtech)
port map (emdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 1)
port map (etx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 1)
port map (erx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 4)
port map (erxd, ethi.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (erx_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (erx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (erx_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (erx_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 4)
port map (etxd, etho.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map ( etx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (etx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (emdc, etho.mdc);
emdis_pad : outpad generic map (tech => padtech)
port map (emddis, vcc(0));
eepwrdwn_pad : outpad generic map (tech => padtech)
port map (epwrdwn, gnd(0));
esleep_pad : outpad generic map (tech => padtech)
port map (esleep, gnd(0));
epause_pad : outpad generic map (tech => padtech)
port map (epause, gnd(0));
ereset_pad : outpad generic map (tech => padtech)
port map (ereset, gnd(0));
end generate;
-----------------------------------------------------------------------
--- CAN --------------------------------------------------------------
-----------------------------------------------------------------------
can0 : if CFG_CAN = 1 generate
can0 : can_oc generic map (slvndx => 6, ioaddr => CFG_CANIO,
iomask => 16#FFF#, irq => CFG_CANIRQ, memtech => memtech)
port map (rstn, clkm, ahbsi, ahbso(6), can_lrx, can_ltx );
end generate;
ncan : if CFG_CAN = 0 generate ahbso(6) <= ahbs_none; end generate;
can_stb <= '0'; -- no standby
can_loopback : if CFG_CANLOOP = 1 generate
can_lrx <= can_ltx;
end generate;
can_pads : if CFG_CANLOOP = 0 generate
can_tx_pad : outpad generic map (tech => padtech)
port map (can_txd, can_ltx);
can_rx_pad : inpad generic map (tech => padtech)
port map (can_rxd, can_lrx);
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map ( rstn, clkm, ahbsi, ahbso(7));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(7) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- SPACEWIRE -------------------------------------------------------
-----------------------------------------------------------------------
spw : if CFG_SPW_EN > 0 generate
spw_clk_pad : clkpad generic map (tech => padtech) port map (spw_clk, spw_lclk);
spw_rxtxclk <= spw_lclk;
spw_rxclkn <= not spw_rxtxclk;
swloop : for i in 0 to CFG_SPW_NUM-1 generate
-- GRSPW2 PHY
spw2_input : if CFG_SPW_GRSPW = 2 generate
spw_phy0 : grspw2_phy
generic map(
scantest => 0,
tech => fabtech,
input_type => CFG_SPW_INPUT,
rxclkbuftype => 1)
port map(
rstn => rstn,
rxclki => spw_rxtxclk,
rxclkin => spw_rxclkn,
nrxclki => spw_rxtxclk,
di => dtmp(i),
si => stmp(i),
do => spwi(i).d(1 downto 0),
dov => spwi(i).dv(1 downto 0),
dconnect => spwi(i).dconnect(1 downto 0),
rxclko => spw_rxclk(i));
spwi(i).nd <= (others => '0'); -- Only used in GRSPW
spwi(i).dv(3 downto 2) <= "00"; -- For second port
end generate spw2_input;
-- GRSPW PHY
spw1_input: if CFG_SPW_GRSPW = 1 generate
spw_phy0 : grspw_phy
generic map(
tech => fabtech,
rxclkbuftype => 1,
scantest => 0)
port map(
rxrst => spwo(i).rxrst,
di => dtmp(i),
si => stmp(i),
rxclko => spw_rxclk(i),
do => spwi(i).d(0),
ndo => spwi(i).nd(4 downto 0),
dconnect => spwi(i).dconnect(1 downto 0));
spwi(i).d(1) <= '0'; -- For second port
spwi(i).dv <= (others => '0'); -- Only used in GRSPW2
spwi(i).nd(9 downto 5) <= "00000"; -- For second port
end generate spw1_input;
spwi(i).d(3 downto 2) <= "00"; -- For second port
spwi(i).dconnect(3 downto 2) <= "00"; -- For GRSPW2 second port
spwi(i).s(1 downto 0) <= "00"; -- Only used in PHY
sw0 : grspwm generic map(tech => memtech,
hindex => maxahbmsp+i, pindex => 12+i, paddr => 12+i, pirq => 10+i,
sysfreq => sysfreq, nsync => 1, ports => 1, rmap => CFG_SPW_RMAP,
rmapcrc => CFG_SPW_RMAPCRC,rmapbufs => CFG_SPW_RMAPBUF,
dmachan => CFG_SPW_DMACHAN,
fifosize1 => CFG_SPW_AHBFIFO, fifosize2 => CFG_SPW_RXFIFO,
rxclkbuftype => 1, spwcore => CFG_SPW_GRSPW,
input_type => CFG_SPW_INPUT,
output_type => CFG_SPW_OUTPUT, rxtx_sameclk => CFG_SPW_RTSAME)
port map(resetn, clkm, spw_rxclk(i), spw_rxclk(i), spw_rxtxclk, spw_rxtxclk,
ahbmi, ahbmo(maxahbmsp+i),
apbi, apbo(12+i), spwi(i), spwo(i));
spwi(i).tickin <= '0'; spwi(i).rmapen <= '1';
spwi(i).clkdiv10 <= conv_std_logic_vector(sysfreq/10000-1, 8);
spwi(i).dcrstval <= (others => '0');
spwi(i).timerrstval <= (others => '0');
spw_rxd_pad : inpad_ds generic map (padtech, lvds, x25v)
port map (spw_rxd(i), spw_rxdn(i), dtmp(i));
spw_rxs_pad : inpad_ds generic map (padtech, lvds, x25v)
port map (spw_rxs(i), spw_rxsn(i), stmp(i));
spw_txd_pad : outpad_ds generic map (padtech, lvds, x25v)
port map (spw_txd(i), spw_txdn(i), spwo(i).d(0), gnd(0));
spw_txs_pad : outpad_ds generic map (padtech, lvds, x25v)
port map (spw_txs(i), spw_txsn(i), spwo(i).s(0), gnd(0));
end generate;
end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
-- nam1 : for i in maxahbm to NAHBMST-1 generate
-- ahbmo(i) <= ahbm_none;
-- end generate;
-- nam2 : if CFG_PCI > 1 generate
-- ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_PCI-1) <= ahbm_none;
-- end generate;
-- nap0 : for i in 12+(CFG_SPW_NUM*CFG_SPW_EN) to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
-- apbo(6) <= apb_none;
-- nah0 : for i in 9 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 MP Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
| gpl-3.0 | fbf3d9b48d0f503b2507f354365b8c66 | 0.554716 | 3.470091 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-altera-ep2s60-sdr/leon3mp.vhd | 1 | 20,764 | ------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.jtag.all;
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
freq : integer := 50000 -- frequency of main clock (used for PLLs)
);
port (
resetn : in std_ulogic;
clk : in std_ulogic;
errorn : out std_ulogic;
-- Shared bus
address : out std_logic_vector(23 downto 0);
data : inout std_logic_vector(31 downto 0);
-- SRAM
ramsn : out std_ulogic;
ramoen : out std_ulogic;
rwen : out std_ulogic;
mben : out std_logic_vector(3 downto 0);
-- pragma translate_off
iosn : out std_ulogic;
-- pragma translate_on
-- FLASH
romsn : out std_ulogic;
oen : out std_ulogic;
writen : out std_ulogic;
byten : out std_ulogic;
wpn : out std_ulogic;
sa : out std_logic_vector(11 downto 0);
sd : inout std_logic_vector(31 downto 0);
sdclk : out std_ulogic;
sdcke : out std_logic; -- sdram clock enable
sdcsn : out std_logic; -- sdram chip select
sdwen : out std_ulogic; -- sdram write enable
sdrasn : out std_ulogic; -- sdram ras
sdcasn : out std_ulogic; -- sdram cas
sddqm : out std_logic_vector (3 downto 0); -- sdram dqm
sdba : out std_logic_vector(1 downto 0); -- sdram bank address
-- debug support unit
dsutx : out std_ulogic; -- DSU tx data
dsurx : in std_ulogic; -- DSU rx data
dsubren : in std_ulogic;
dsuact : out std_ulogic;
-- console UART
rxd1 : in std_ulogic;
txd1 : out std_ulogic;
-- for smsc lan chip
eth_aen : out std_logic;
eth_readn : out std_logic;
eth_writen: out std_logic;
eth_nbe : out std_logic_vector(3 downto 0);
eth_lclk : out std_ulogic;
eth_nads : out std_logic;
eth_ncycle : out std_logic;
eth_wnr : out std_logic;
eth_nvlbus : out std_logic;
eth_nrdyrtn : out std_logic;
eth_ndatacs : out std_logic;
gpio : inout std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0) -- I/O port
);
end;
architecture rtl of leon3mp is
constant blength : integer := 12;
constant fifodepth : integer := 8;
constant maxahbm : integer := NCPU+CFG_AHB_UART+CFG_AHB_JTAG;
signal vcc, gnd : std_logic_vector(7 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal sdo2 : sdctrl_out_type;
--for smc lan chip
signal s_eth_aen : std_logic;
signal s_eth_readn : std_logic;
signal s_eth_writen: std_logic;
signal s_eth_nbe : std_logic_vector(3 downto 0);
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, sdclkl : std_ulogic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to NCPU-1);
signal irqo : irq_out_vector(0 to NCPU-1);
signal dbgi : l3_debug_in_vector(0 to NCPU-1);
signal dbgo : l3_debug_out_vector(0 to NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal gpti : gptimer_in_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
constant IOAEN : integer := 1;
constant CFG_SDEN : integer := CFG_MCTRL_SDEN ;
constant CFG_INVCLK : integer := CFG_MCTRL_INVCLK;
signal dsubre : std_ulogic;
component smc_mctrl
generic (
hindex : integer := 0;
pindex : integer := 0;
romaddr : integer := 16#000#;
rommask : integer := 16#E00#;
ioaddr : integer := 16#200#;
iomask : integer := 16#E00#;
ramaddr : integer := 16#400#;
rammask : integer := 16#C00#;
paddr : integer := 0;
pmask : integer := 16#fff#;
wprot : integer := 0;
invclk : integer := 0;
fast : integer := 0;
romasel : integer := 28;
sdrasel : integer := 29;
srbanks : integer := 4;
ram8 : integer := 0;
ram16 : integer := 0;
sden : integer := 0;
sepbus : integer := 0;
sdbits : integer := 32;
sdlsb : integer := 2;
oepol : integer := 0;
syncrst : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
memi : in memory_in_type;
memo : out memory_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
wpo : in wprot_out_type;
sdo : out sdram_out_type;
eth_aen : out std_ulogic; -- for smsc lan chip
eth_readn : out std_ulogic; -- for smsc lan chip
eth_writen: out std_ulogic; -- for smsc lan chip
eth_nbe : out std_logic_vector(3 downto 0) -- for smsc lan chip
);
end component;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= not resetn; cgi.pllref <= '0';
clkgen0 : clkgen -- clock generator using toplevel generic 'freq'
generic map (tech => CFG_CLKTECH, clk_mul => CFG_CLKMUL,
clk_div => CFG_CLKDIV, sdramen => CFG_MCTRL_SDEN,
noclkfb => CFG_CLK_NOFB, freq => freq)
port map (clkin => clk, pciclkin => gnd(0), clk => clkm, clkn => open,
clk2x => open, sdclk => sdclkl, pciclk => open,
cgi => cgi, cgo => cgo);
sdclk_pad : outpad generic map (tech => padtech, slew => 1, strength => 24) port map (sdclk, sdclkl);
rst0 : rstgen -- reset generator
port map (resetn, clkm, cgo.clklock, rstn);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
errorn_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart -- Debug UART
generic map (hindex => NCPU, pindex => 4, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (dsurx, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (dsutx, duo.txd);
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(4) <= apb_none; end generate;
ahbjtaggen0 : if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, gnd(0), gnd(0), gnd(0), open, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
src : if CFG_SRCTRL = 1 generate -- 32-bit PROM/SRAM controller
sr0 : srctrl generic map (hindex => 0, ramws => CFG_SRCTRL_RAMWS,
romws => CFG_SRCTRL_PROMWS, ramaddr => 16#400#,
prom8en => CFG_SRCTRL_8BIT, rmw => CFG_SRCTRL_RMW)
port map (rstn, clkm, ahbsi, ahbso(0), memi, memo, sdo2);
apbo(0) <= apb_none;
end generate;
mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 : smc_mctrl generic map (hindex => 0, pindex => 0, paddr => 0,
srbanks => 2, sden => CFG_MCTRL_SDEN, ram8 => CFG_MCTRL_RAM8BIT,
ram16 => CFG_MCTRL_RAM16BIT, invclk => CFG_MCTRL_INVCLK,
sepbus => CFG_MCTRL_SEPBUS, sdbits => 32 + 32*CFG_MCTRL_SD64)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo,
s_eth_aen, s_eth_readn, s_eth_writen, s_eth_nbe);
sdpads : if CFG_MCTRL_SDEN = 1 generate -- SDRAM controller
sd2 : if CFG_MCTRL_SEPBUS = 1 generate
sa_pad : outpadv generic map (width => 12) port map (sa, memo.sa(11 downto 0));
sdba_pad : outpadv generic map (width => 2) port map (sdba, memo.sa(14 downto 13));
bdr : for i in 0 to 3 generate
sd_pad : iopadv generic map (tech => padtech, width => 8)
port map (sd(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.sd(31-i*8 downto 24-i*8));
sd2 : if CFG_MCTRL_SD64 = 1 generate
sd_pad2 : iopadv generic map (tech => padtech, width => 8)
port map (sd(31-i*8+32 downto 24-i*8+32), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.sd(31-i*8+32 downto 24-i*8+32));
end generate;
end generate;
end generate;
sdwen_pad : outpad generic map (tech => padtech)
port map (sdwen, sdo.sdwen);
sdras_pad : outpad generic map (tech => padtech)
port map (sdrasn, sdo.rasn);
sdcas_pad : outpad generic map (tech => padtech)
port map (sdcasn, sdo.casn);
sddqm_pad : outpadv generic map (width =>4, tech => padtech)
port map (sddqm, sdo.dqm(3 downto 0));
end generate;
sdcke_pad : outpad generic map (tech => padtech) port map (sdcke, sdo.sdcke(0));
sdcsn_pad : outpad generic map (tech => padtech) port map (sdcsn, sdo.sdcsn(0));
end generate;
wpn <= '1'; byten <= '0';
nosd0 : if (CFG_MCTRL_LEON2 = 0) generate -- no SDRAM controller
sdcke_pad : outpad generic map (tech => padtech) port map (sdcke, vcc(0));
sdcsn_pad : outpad generic map (tech => padtech) port map (sdcsn, vcc(0));
end generate;
memi.brdyn <= '1'; memi.bexcn <= '1';
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "00";
mg0 : if not ((CFG_SRCTRL = 1) or (CFG_MCTRL_LEON2 = 1)) generate -- no prom/sram pads
apbo(0) <= apb_none; ahbso(0) <= ahbs_none;
rams_pad : outpad generic map (tech => padtech)
port map (ramsn, vcc(0));
roms_pad : outpad generic map (tech => padtech)
port map (romsn, vcc(0));
end generate;
mgpads : if (CFG_SRCTRL = 1) or (CFG_MCTRL_LEON2 = 1) generate -- prom/sram pads
addr_pad : outpadv generic map (width => 24, tech => padtech)
port map (address, memo.address(23 downto 0));
memb_pad : outpadv generic map (width => 4, tech => padtech)
port map (mben, memo.mben);
rams_pad : outpad generic map (tech => padtech)
port map (ramsn, memo.ramsn(0));
roms_pad : outpad generic map (tech => padtech)
port map (romsn, memo.romsn(0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.oen);
rwen_pad : outpad generic map (tech => padtech)
port map (rwen, memo.wrn(0));
roen_pad : outpad generic map (tech => padtech)
port map (ramoen, memo.ramoen(0));
wri_pad : outpad generic map (tech => padtech)
port map (writen, memo.writen);
-- pragma translate_off
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
-- pragma translate_on
-- for smc lan chip
eth_aen_pad : outpad generic map (tech => padtech)
port map (eth_aen, s_eth_aen);
eth_readn_pad : outpad generic map (tech => padtech)
port map (eth_readn, s_eth_readn);
eth_writen_pad : outpad generic map (tech => padtech)
port map (eth_writen, s_eth_writen);
eth_nbe_pad : outpadv generic map (width => 4, tech => padtech)
port map (eth_nbe, s_eth_nbe);
bdr : for i in 0 to 3 generate
data_pad : iopadv generic map (tech => padtech, width => 8)
port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.data(31-i*8 downto 24-i*8));
end generate;
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd1; u1i.ctsn <= '0'; u1i.extclk <= '0'; txd1 <= u1o.txd;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti <= gpti_dhalt_drive(dsuo.tstop);
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map(pindex => 5, paddr => 5, imask => CFG_GRGPIO_IMASK, nbits => CFG_GRGPIO_WIDTH)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(5),
gpioi => gpioi, gpioo => gpioo);
pio_pads : for i in 0 to CFG_GRGPIO_WIDTH-1 generate
pio_pad : iopad generic map (tech => padtech)
port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(6) <= ahbs_none;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ahbramgen : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 3, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map (rstn, clkm, ahbsi, ahbso(3));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(3) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (NCPU+CFG_AHB_UART+CFG_AHB_JTAG) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
nap0 : for i in 6 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
nah0 : for i in 7 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
-- invert signal for input via a key
dsubre <= not dsubren;
-- for smc lan chip
eth_lclk <= vcc(0);
eth_nads <= gnd(0);
eth_ncycle <= vcc(0);
eth_wnr <= vcc(0);
eth_nvlbus <= vcc(0);
eth_nrdyrtn <= vcc(0);
eth_ndatacs <= vcc(0);
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Altera EP2C60 SDR Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
| gpl-3.0 | a9016380d6e6b65527ca4a564c86f0e0 | 0.538576 | 3.754113 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/net/net.vhd | 1 | 27,047 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: net
-- File: net.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Package with component and type declarations for network cores
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library techmap;
use techmap.gencomp.all;
package net is
type eth_in_type is record
gtx_clk : std_ulogic;
rmii_clk : std_ulogic;
tx_clk : std_ulogic;
tx_clk_90 : std_ulogic;
tx_dv : std_ulogic;
rx_clk : std_ulogic;
rxd : std_logic_vector(7 downto 0);
rx_dv : std_ulogic;
rx_er : std_ulogic;
rx_col : std_ulogic;
rx_crs : std_ulogic;
rx_en : std_ulogic;
mdio_i : std_ulogic;
mdint : std_ulogic;
phyrstaddr : std_logic_vector(4 downto 0);
edcladdr : std_logic_vector(3 downto 0);
edclsepahb : std_ulogic;
edcldisable: std_ulogic;
end record;
constant eth_in_none : eth_in_type :=
('0', '0', '0', '0', '0', '0', (others => '0'), '0', '0', '0', '0', '0',
'0', '0', (others => '0'), (others => '0'), '0', '0');
type eth_in_vector is array (natural range <>) of eth_in_type;
type eth_out_type is record
reset : std_ulogic;
txd : std_logic_vector(7 downto 0);
tx_en : std_ulogic;
tx_er : std_ulogic;
tx_clk : std_ulogic;
mdc : std_ulogic;
mdio_o : std_ulogic;
mdio_oe : std_ulogic;
gbit : std_ulogic;
speed : std_ulogic;
end record;
constant eth_out_none : eth_out_type :=
('0', (others => '0'), '0', '0', '0', '0', '0', '1', '0', '0');
type eth_out_vector is array (natural range <>) of eth_out_type;
type eth_sgmii_in_type is record
clkp : std_ulogic;
clkn : std_ulogic;
rxp : std_ulogic;
rxn : std_ulogic;
mdio_i : std_ulogic;
mdint : std_ulogic;
end record;
type eth_sgmii_out_type is record
reset : std_ulogic;
txp : std_ulogic;
txn : std_ulogic;
mdc : std_ulogic;
mdio_o : std_ulogic;
mdio_oe : std_ulogic;
end record;
type greth_mdiochain_down_type is record
first : std_ulogic;
tick : std_ulogic;
mdio_i : std_ulogic;
end record;
type greth_mdiochain_up_type is record
lock : std_ulogic;
mdio_o : std_ulogic;
mdio_oe: std_ulogic;
end record;
constant greth_mdiochain_down_first: greth_mdiochain_down_type :=
(first => '1', tick => '0', mdio_i => '0');
constant greth_mdiochain_up_last: greth_mdiochain_up_type :=
(lock => '0', mdio_o => '0', mdio_oe => '0');
component eth_arb
generic(
fullduplex : integer := 0;
mdiomaster : integer := 0);
port(
rst : in std_logic;
clk : in std_logic;
ethi : in eth_in_type;
etho : out eth_out_type;
methi : in eth_out_type;
metho : out eth_in_type;
dethi : in eth_out_type;
detho : out eth_in_type
);
end component;
component greth is
generic(
hindex : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#FFF#;
pirq : integer := 0;
memtech : integer := 0;
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
slot_time : integer := 128;
mdcscaler : integer range 0 to 255 := 25;
enable_mdio : integer range 0 to 1 := 0;
fifosize : integer range 4 to 512 := 8;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 3 := 0;
edclbufsz : integer range 1 to 64 := 1;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0035#;
phyrstadr : integer range 0 to 32 := 0;
rmii : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0;
scanen : integer range 0 to 1 := 0;
ft : integer range 0 to 2 := 0;
edclft : integer range 0 to 2 := 0;
mdint_pol : integer range 0 to 1 := 0;
enable_mdint : integer range 0 to 1 := 0;
multicast : integer range 0 to 1 := 0;
ramdebug : integer range 0 to 2 := 0;
mdiohold : integer := 1;
maxsize : integer := 1500;
gmiimode : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ethi : in eth_in_type;
etho : out eth_out_type
);
end component;
component greth_mb is
generic(
hindex : integer := 0;
ehindex : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#FFF#;
pirq : integer := 0;
memtech : integer := 0;
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
slot_time : integer := 128;
mdcscaler : integer range 0 to 255 := 25;
enable_mdio : integer range 0 to 1 := 0;
fifosize : integer range 4 to 512 := 8;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 3 := 0;
edclbufsz : integer range 1 to 64 := 1;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0035#;
phyrstadr : integer range 0 to 32 := 0;
rmii : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0;
scanen : integer range 0 to 1 := 0;
ft : integer range 0 to 2 := 0;
edclft : integer range 0 to 2 := 0;
mdint_pol : integer range 0 to 1 := 0;
enable_mdint : integer range 0 to 1 := 0;
multicast : integer range 0 to 1 := 0;
edclsepahb : integer range 0 to 1 := 0;
ramdebug : integer range 0 to 2 := 0;
mdiohold : integer := 1;
maxsize : integer := 1500;
gmiimode : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
ahbmi2 : in ahb_mst_in_type;
ahbmo2 : out ahb_mst_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ethi : in eth_in_type;
etho : out eth_out_type
);
end component;
component greth_gbit_mb is
generic(
hindex : integer := 0;
ehindex : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#FFF#;
pirq : integer := 0;
memtech : integer := 0;
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
slot_time : integer := 128;
mdcscaler : integer range 0 to 255 := 25;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 3 := 0;
edclbufsz : integer range 1 to 64 := 1;
burstlength : integer range 4 to 128 := 32;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0035#;
phyrstadr : integer range 0 to 32 := 0;
sim : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0;
scanen : integer range 0 to 1 := 0;
ft : integer range 0 to 2 := 0;
edclft : integer range 0 to 2 := 0;
mdint_pol : integer range 0 to 1 := 0;
enable_mdint : integer range 0 to 1 := 0;
multicast : integer range 0 to 1 := 0;
edclsepahb : integer range 0 to 1 := 0;
ramdebug : integer range 0 to 2 := 0;
mdiohold : integer := 1;
gmiimode : integer range 0 to 1 := 0;
mdiochain : integer range 0 to 1 := 0;
iotest : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
ahbmi2 : in ahb_mst_in_type;
ahbmo2 : out ahb_mst_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ethi : in eth_in_type;
etho : out eth_out_type;
mdchain_ui : in greth_mdiochain_down_type := greth_mdiochain_down_first;
mdchain_uo : out greth_mdiochain_up_type;
mdchain_di : out greth_mdiochain_down_type;
mdchain_do : in greth_mdiochain_up_type := greth_mdiochain_up_last
);
end component;
component greth_gbit is
generic(
hindex : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#FFF#;
pirq : integer := 0;
memtech : integer := 0;
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
slot_time : integer := 128;
mdcscaler : integer range 0 to 255 := 25;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 3 := 0;
edclbufsz : integer range 1 to 64 := 1;
burstlength : integer range 4 to 128 := 32;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0035#;
phyrstadr : integer range 0 to 32 := 0;
sim : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0;
scanen : integer range 0 to 1 := 0;
ft : integer range 0 to 2 := 0;
edclft : integer range 0 to 2 := 0;
mdint_pol : integer range 0 to 1 := 0;
enable_mdint : integer range 0 to 1 := 0;
multicast : integer range 0 to 1 := 0;
ramdebug : integer range 0 to 2 := 0;
mdiohold : integer := 1;
gmiimode : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ethi : in eth_in_type;
etho : out eth_out_type
);
end component;
component grethm
generic(
hindex : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#FFF#;
pirq : integer := 0;
memtech : integer := 0;
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
slot_time : integer := 128;
mdcscaler : integer range 0 to 255 := 25;
enable_mdio : integer range 0 to 1 := 0;
fifosize : integer range 4 to 64 := 8;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 3 := 0;
edclbufsz : integer range 1 to 64 := 1;
burstlength : integer range 4 to 128 := 32;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0035#;
phyrstadr : integer range 0 to 32 := 0;
rmii : integer range 0 to 1 := 0;
sim : integer range 0 to 1 := 0;
giga : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0;
scanen : integer range 0 to 1 := 0;
ft : integer range 0 to 2 := 0;
edclft : integer range 0 to 1 := 0;
mdint_pol : integer range 0 to 1 := 0;
enable_mdint : integer range 0 to 1 := 0;
multicast : integer range 0 to 1 := 0;
ramdebug : integer range 0 to 2 := 0;
mdiohold : integer := 1;
maxsize : integer := 1500;
gmiimode : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ethi : in eth_in_type;
etho : out eth_out_type
);
end component;
component grethm_mb
generic (
hindex : integer := 0;
ehindex : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#FFF#;
pirq : integer := 0;
memtech : integer := 0;
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
slot_time : integer := 128;
mdcscaler : integer range 0 to 255 := 25;
enable_mdio : integer range 0 to 1 := 0;
fifosize : integer range 4 to 64 := 8;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 3 := 0;
edclbufsz : integer range 1 to 64 := 1;
burstlength : integer range 4 to 128 := 32;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0035#;
phyrstadr : integer range 0 to 32 := 0;
rmii : integer range 0 to 1 := 0;
sim : integer range 0 to 1 := 0;
giga : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0;
scanen : integer range 0 to 1 := 0;
ft : integer range 0 to 2 := 0;
edclft : integer range 0 to 1 := 1;
mdint_pol : integer range 0 to 1 := 0;
enable_mdint : integer range 0 to 1 := 0;
multicast : integer range 0 to 1 := 0;
edclsepahb : integer range 0 to 1 := 0;
ramdebug : integer range 0 to 2 := 0;
mdiohold : integer := 1;
maxsize : integer := 1500;
gmiimode : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
ahbmi2 : in ahb_mst_in_type;
ahbmo2 : out ahb_mst_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ethi : in eth_in_type;
etho : out eth_out_type
);
end component;
component greths is
generic(
hindex : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#FFF#;
pirq : integer := 0;
fabtech : integer := 0;
memtech : integer := 0;
transtech : integer := 0;
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
slot_time : integer := 128;
mdcscaler : integer range 0 to 255 := 25;
enable_mdio : integer range 0 to 1 := 0;
fifosize : integer range 4 to 64 := 8;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 3 := 0;
edclbufsz : integer range 1 to 64 := 1;
burstlength : integer range 4 to 128 := 32;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0035#;
phyrstadr : integer range 0 to 32 := 0;
rmii : integer range 0 to 1 := 0;
sim : integer range 0 to 1 := 0;
giga : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0;
scanen : integer range 0 to 1 := 0;
ft : integer range 0 to 2 := 0;
edclft : integer range 0 to 2 := 0;
mdint_pol : integer range 0 to 1 := 0;
enable_mdint : integer range 0 to 1 := 0;
multicast : integer range 0 to 1 := 0;
ramdebug : integer range 0 to 2 := 0;
mdiohold : integer := 1;
maxsize : integer := 1500;
pcs_phyaddr : integer range 0 to 32 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
-- High-speed Serial Interface
clk_125 : in std_logic;
rst_125 : in std_logic;
eth_rx_p : in std_logic;
eth_rx_n : in std_logic := '0';
eth_tx_p : out std_logic;
eth_tx_n : out std_logic;
-- MDIO interface
reset : out std_logic;
mdio_o : out std_logic;
mdio_oe : out std_logic;
mdio_i : in std_logic;
mdc : out std_logic;
mdint : in std_logic;
-- Control signals
phyrstaddr : in std_logic_vector(4 downto 0);
edcladdr : in std_logic_vector(3 downto 0);
edclsepahb : in std_logic;
edcldisable : in std_logic;
debug_pcs_mdio : in std_logic := '0';
-- added for igloo2_serdes
apbin : in apb_in_serdes := apb_in_serdes_none;
apbout : out apb_out_serdes;
m2gl_padin : in pad_in_serdes := pad_in_serdes_none;
m2gl_padout : out pad_out_serdes;
serdes_clk125 : out std_logic;
rx_aligned : out std_logic
);
end component;
component greths_mb is
generic(
hindex : integer := 0;
ehindex : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#FFF#;
pirq : integer := 0;
fabtech : integer := 0;
memtech : integer := 0;
transtech : integer := 0;
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
slot_time : integer := 128;
mdcscaler : integer range 0 to 255 := 25;
enable_mdio : integer range 0 to 1 := 0;
fifosize : integer range 4 to 64 := 8;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 3 := 0;
edclbufsz : integer range 1 to 64 := 1;
burstlength : integer range 4 to 128 := 32;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0035#;
phyrstadr : integer range 0 to 32 := 0;
rmii : integer range 0 to 1 := 0;
sim : integer range 0 to 1 := 0;
giga : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0;
scanen : integer range 0 to 1 := 0;
ft : integer range 0 to 2 := 0;
edclft : integer range 0 to 2 := 0;
mdint_pol : integer range 0 to 1 := 0;
enable_mdint : integer range 0 to 1 := 0;
multicast : integer range 0 to 1 := 0;
edclsepahbg : integer range 0 to 1 := 0;
ramdebug : integer range 0 to 2 := 0;
mdiohold : integer := 1;
maxsize : integer := 1500;
pcs_phyaddr : integer range 0 to 32 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
ahbmi2 : in ahb_mst_in_type;
ahbmo2 : out ahb_mst_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
-- High-speed Serial Interface
clk_125 : in std_logic;
rst_125 : in std_logic;
eth_rx_p : in std_logic;
eth_rx_n : in std_logic := '0';
eth_tx_p : out std_logic;
eth_tx_n : out std_logic;
-- MDIO interface
reset : out std_logic;
mdio_o : out std_logic;
mdio_oe : out std_logic;
mdio_i : in std_logic;
mdc : out std_logic;
mdint : in std_logic;
-- Control signals
phyrstaddr : in std_logic_vector(4 downto 0);
edcladdr : in std_logic_vector(3 downto 0);
edclsepahb : in std_logic;
edcldisable : in std_logic;
debug_pcs_mdio : in std_logic := '0';
-- added for igloo2_serdes
apbin : in apb_in_serdes := apb_in_serdes_none;
apbout : out apb_out_serdes;
m2gl_padin : in pad_in_serdes := pad_in_serdes_none;
m2gl_padout : out pad_out_serdes;
serdes_clk125 : out std_logic;
rx_aligned : out std_logic
);
end component;
component rgmii is
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
tech : integer := 0;
gmii : integer := 0;
debugmem : integer := 0;
abits : integer := 8;
no_clk_mux : integer := 0;
pirq : integer := 0;
use90degtxclk : integer := 0;
mode100 : integer := 0
);
port (
rstn : in std_ulogic;
gmiii : out eth_in_type;
gmiio : in eth_out_type;
rgmiii : in eth_in_type;
rgmiio : out eth_out_type ;
-- APB Status bus
apb_clk : in std_logic;
apb_rstn : in std_logic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type
);
end component;
component sgmii is
generic (
fabtech : integer := 0;
memtech : integer := 0;
transtech : integer := 0;
phy_addr : integer := 0;
mode : integer := 0 -- unused
);
port (
clk_125 : in std_logic;
rst_125 : in std_logic;
ser_rx_p : in std_logic;
ser_rx_n : in std_logic;
ser_tx_p : out std_logic;
ser_tx_n : out std_logic;
txd : in std_logic_vector(7 downto 0);
tx_en : in std_logic;
tx_er : in std_logic;
tx_clk : out std_logic;
tx_rstn : out std_logic;
rxd : out std_logic_vector(7 downto 0);
rx_dv : out std_logic;
rx_er : out std_logic;
rx_col : out std_logic;
rx_crs : out std_logic;
rx_clk : out std_logic;
rx_rstn : out std_logic;
-- optional MDIO interface to PCS
mdc : in std_logic;
mdio_o : in std_logic := '0';
mdio_oe : in std_logic := '1';
mdio_i : out std_logic;
-- added for igloo2_serdes
apbin : in apb_in_serdes := apb_in_serdes_none;
apbout : out apb_out_serdes;
m2gl_padin : in pad_in_serdes := pad_in_serdes_none;
m2gl_padout : out pad_out_serdes;
serdes_clk125 : out std_logic;
rx_aligned : out std_logic
);
end component ;
component comma_detect is
generic (
bsbreak : integer range 0 to 31 := 0; -- number of extra deassertion cycles between bitslip assertions in a sequence
bswait : integer range 0 to 127 := 7 -- number of cycles to pause recognition after a sequence is issued
);
port (
clk : in std_logic;
rstn : in std_logic;
indata : in std_logic_vector(9 downto 0);
bitslip : out std_logic
);
end component;
component word_aligner is
generic(
comma : std_logic_vector(9 downto 3) := "0011111");
port(
clk : in std_logic; -- rx clock
rstn : in std_logic; -- asynchronous reset
rx_in : in std_logic_vector(9 downto 0); -- Data in
rx_out : out std_logic_vector(9 downto 0) -- Data out
);
end component;
component elastic_buffer is
generic (
tech : integer := 0;
abits : integer := 7
);
port (
wr_clk : in std_logic;
wr_rst : in std_logic;
wr_data : in std_logic_vector(9 downto 0);
rd_clk : in std_logic;
rd_rst : in std_logic;
rd_data : out std_logic_vector(9 downto 0)
) ;
end component ;
component gmii_to_mii is
port (
tx_rstn : in std_logic;
rx_rstn : in std_logic;
-- MAC SIDE
gmiii : out eth_in_type;
gmiio : in eth_out_type;
-- PHY SIDE
miii : in eth_in_type;
miio : out eth_out_type
) ;
end component ;
end;
| gpl-3.0 | 82e8ddf5baab75ac24223a88e7588d10 | 0.484897 | 3.766467 | false | false | false | false |
pwsoft/fpga_examples | rtl/chameleon/chameleon_1mhz.vhd | 1 | 2,652 | -- -----------------------------------------------------------------------
--
-- Turbo Chameleon
--
-- Multi purpose FPGA expansion for the Commodore 64 computer
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2017 by Peter Wendrich ([email protected])
-- http://www.syntiac.com/chameleon.html
--
-- This source file is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- -----------------------------------------------------------------------
--
-- 1 Mhz clock source
--
-- -----------------------------------------------------------------------
-- clk_ticks_per_usec - Specifies clockspeed of clk in MHz, calibrates timer.
-- -----------------------------------------------------------------------
-- clk - system clock input
-- ena_1mhz - 1 Mhz output. Signal is one cycle '1' each micro-second.
-- ena_1mhz_2 - One cycle trigger output that shifted by 0.5 micro-second against ena_1mhz
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
-- -----------------------------------------------------------------------
entity chameleon_1mhz is
generic (
clk_ticks_per_usec : integer
);
port (
clk : in std_logic;
ena_1mhz : out std_logic;
ena_1mhz_2 : out std_logic
);
end entity;
-- -----------------------------------------------------------------------
architecture rtl of chameleon_1mhz is
constant maxcount : integer := clk_ticks_per_usec-1;
signal cnt : integer range 0 to maxcount := maxcount;
signal ena_out : std_logic := '0';
signal ena2_out : std_logic := '0';
begin
ena_1mhz <= ena_out;
ena_1mhz_2 <= ena2_out;
process(clk)
begin
if rising_edge(clk) then
ena_out <= '0';
if cnt = 0 then
cnt <= maxcount;
ena_out <= '1';
else
cnt <= cnt - 1;
end if;
end if;
end process;
process(clk)
begin
if rising_edge(clk) then
ena2_out <= '0';
if cnt = (maxcount / 2) then
ena2_out <= '1';
end if;
end if;
end process;
end architecture;
| lgpl-2.1 | d60f39d980923441dff0e667f6e20e47 | 0.530543 | 3.928889 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/techmap/virtex/memory_virtex.vhd | 1 | 14,276 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: various
-- File: memory_virtex.vhd
-- Author: Aeroflex Gaisler AB
-- Description: Memory generators for Xilinx Virtex rams
------------------------------------------------------------------------------
-- parametrisable sync ram generator using UNISIM RAMB4 block rams
library ieee;
use ieee.std_logic_1164.all;
--pragma translate_off
library unisim;
use unisim.RAMB4_S1;
use unisim.RAMB4_S2;
use unisim.RAMB4_S4;
use unisim.RAMB4_S8;
use unisim.RAMB4_S16;
use unisim.RAMB4_S16_S16;
--pragma translate_on
library grlib;
use grlib.config_types.all;
use grlib.config.all;
library techmap;
use techmap.gencomp.all;
entity virtex_syncram is
generic ( abits : integer := 6; dbits : integer := 8);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (dbits -1 downto 0);
dataout : out std_logic_vector (dbits -1 downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end;
architecture behav of virtex_syncram is
component generic_syncram
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
write : in std_ulogic);
end component;
component ramb4_s16 port (
do : out std_logic_vector (15 downto 0);
addr : in std_logic_vector (7 downto 0);
clk : in std_ulogic;
di : in std_logic_vector (15 downto 0);
en, rst, we : in std_ulogic);
end component;
component RAMB4_S8
port (do : out std_logic_vector (7 downto 0);
addr : in std_logic_vector (8 downto 0);
clk : in std_ulogic;
di : in std_logic_vector (7 downto 0);
en, rst, we : in std_ulogic);
end component;
component RAMB4_S4
port (do : out std_logic_vector (3 downto 0);
addr : in std_logic_vector (9 downto 0);
clk : in std_ulogic;
di : in std_logic_vector (3 downto 0);
en, rst, we : in std_ulogic);
end component;
component RAMB4_S2
port (do : out std_logic_vector (1 downto 0);
addr : in std_logic_vector (10 downto 0);
clk : in std_ulogic;
di : in std_logic_vector (1 downto 0);
en, rst, we : in std_ulogic);
end component;
component RAMB4_S1
port (do : out std_logic_vector (0 downto 0);
addr : in std_logic_vector (11 downto 0);
clk : in std_ulogic;
di : in std_logic_vector (0 downto 0);
en, rst, we : in std_ulogic);
end component;
component RAMB4_S16_S16
generic (SIM_COLLISION_CHECK : string := "ALL");
port (
doa : out std_logic_vector (15 downto 0);
dob : out std_logic_vector (15 downto 0);
addra : in std_logic_vector (7 downto 0);
addrb : in std_logic_vector (7 downto 0);
clka : in std_ulogic;
clkb : in std_ulogic;
dia : in std_logic_vector (15 downto 0);
dib : in std_logic_vector (15 downto 0);
ena : in std_ulogic;
enb : in std_ulogic;
rsta : in std_ulogic;
rstb : in std_ulogic;
wea : in std_ulogic;
web : in std_ulogic
);
end component;
signal gnd : std_ulogic;
signal do, di : std_logic_vector(dbits+32 downto 0);
signal xa, ya : std_logic_vector(19 downto 0);
begin
gnd <= '0';
dataout <= do(dbits-1 downto 0);
di(dbits-1 downto 0) <= datain; di(dbits+32 downto dbits) <= (others => '0');
xa(abits-1 downto 0) <= address; xa(19 downto abits) <= (others => '0');
ya(abits-1 downto 0) <= address; ya(19 downto abits) <= (others => '1');
a0 : if (abits <= 5) and (GRLIB_CONFIG_ARRAY(grlib_techmap_strict_ram) = 0) generate
r0 : generic_syncram generic map (abits, dbits)
port map (clk, address, datain, do(dbits-1 downto 0), write);
do(dbits+32 downto dbits) <= (others => '0');
end generate;
a7 : if ((abits > 5 or GRLIB_CONFIG_ARRAY(grlib_techmap_strict_ram) /= 0) and
(abits <= 7) and (dbits <= 32)) generate
r0 : RAMB4_S16_S16
generic map(SIM_COLLISION_CHECK => "GENERATE_X_ONLY")
port map ( do(31 downto 16), do(15 downto 0),
xa(7 downto 0), ya(7 downto 0), clk, clk, di(31 downto 16),
di(15 downto 0), enable, enable, gnd, gnd, write, write);
do(dbits+32 downto 32) <= (others => '0');
end generate;
a8 : if (((abits > 5 or GRLIB_CONFIG_ARRAY(grlib_techmap_strict_ram) /= 0) and
(abits <= 7) and (dbits > 32)) or (abits = 8)) generate
x : for i in 0 to ((dbits-1)/16) generate
r : RAMB4_S16 port map ( do (((i+1)*16)-1 downto i*16), xa(7 downto 0),
clk, di (((i+1)*16)-1 downto i*16), enable, gnd, write );
end generate;
do(dbits+32 downto 16*(((dbits-1)/16)+1)) <= (others => '0');
end generate;
a9 : if abits = 9 generate
x : for i in 0 to ((dbits-1)/8) generate
r : RAMB4_S8 port map ( do (((i+1)*8)-1 downto i*8), xa(8 downto 0),
clk, di (((i+1)*8)-1 downto i*8), enable, gnd, write );
end generate;
do(dbits+32 downto 8*(((dbits-1)/8)+1)) <= (others => '0');
end generate;
a10 : if abits = 10 generate
x : for i in 0 to ((dbits-1)/4) generate
r : RAMB4_S4 port map ( do (((i+1)*4)-1 downto i*4), xa(9 downto 0),
clk, di (((i+1)*4)-1 downto i*4), enable, gnd, write );
end generate;
do(dbits+32 downto 4*(((dbits-1)/4)+1)) <= (others => '0');
end generate;
a11 : if abits = 11 generate
x : for i in 0 to ((dbits-1)/2) generate
r : RAMB4_S2 port map ( do (((i+1)*2)-1 downto i*2), xa(10 downto 0),
clk, di (((i+1)*2)-1 downto i*2), enable, gnd, write );
end generate;
do(dbits+32 downto 2*(((dbits-1)/2)+1)) <= (others => '0');
end generate;
a12 : if abits = 12 generate
x : for i in 0 to (dbits-1) generate
r : RAMB4_S1 port map ( do (i downto i), xa(11 downto 0),
clk, di(i downto i), enable, gnd, write );
end generate;
do(dbits+32 downto dbits) <= (others => '0');
end generate;
a13 : if abits > 12 generate
x: generic_syncram generic map (abits, dbits)
port map (clk, address, datain, do(dbits-1 downto 0), write);
do(dbits+32 downto dbits) <= (others => '0');
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
--pragma translate_off
library unisim;
use unisim.RAMB4_S1_S1;
use unisim.RAMB4_S2_S2;
use unisim.RAMB4_S4_S4;
use unisim.RAMB4_S8_S8;
use unisim.RAMB4_S16_S16;
--pragma translate_on
entity virtex_syncram_dp is
generic (
abits : integer := 6; dbits : integer := 8
);
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic);
end;
architecture behav of virtex_syncram_dp is
component RAMB4_S1_S1
generic (SIM_COLLISION_CHECK : string := "ALL");
port (
doa : out std_logic_vector (0 downto 0);
dob : out std_logic_vector (0 downto 0);
addra : in std_logic_vector (11 downto 0);
addrb : in std_logic_vector (11 downto 0);
clka : in std_ulogic;
clkb : in std_ulogic;
dia : in std_logic_vector (0 downto 0);
dib : in std_logic_vector (0 downto 0);
ena : in std_ulogic;
enb : in std_ulogic;
rsta : in std_ulogic;
rstb : in std_ulogic;
wea : in std_ulogic;
web : in std_ulogic
);
end component;
component RAMB4_S2_S2
generic (SIM_COLLISION_CHECK : string := "ALL");
port (
doa : out std_logic_vector (1 downto 0);
dob : out std_logic_vector (1 downto 0);
addra : in std_logic_vector (10 downto 0);
addrb : in std_logic_vector (10 downto 0);
clka : in std_ulogic;
clkb : in std_ulogic;
dia : in std_logic_vector (1 downto 0);
dib : in std_logic_vector (1 downto 0);
ena : in std_ulogic;
enb : in std_ulogic;
rsta : in std_ulogic;
rstb : in std_ulogic;
wea : in std_ulogic;
web : in std_ulogic
);
end component;
component RAMB4_S4_S4
generic (SIM_COLLISION_CHECK : string := "ALL");
port (
doa : out std_logic_vector (3 downto 0);
dob : out std_logic_vector (3 downto 0);
addra : in std_logic_vector (9 downto 0);
addrb : in std_logic_vector (9 downto 0);
clka : in std_ulogic;
clkb : in std_ulogic;
dia : in std_logic_vector (3 downto 0);
dib : in std_logic_vector (3 downto 0);
ena : in std_ulogic;
enb : in std_ulogic;
rsta : in std_ulogic;
rstb : in std_ulogic;
wea : in std_ulogic;
web : in std_ulogic
);
end component;
component RAMB4_S8_S8
generic (SIM_COLLISION_CHECK : string := "ALL");
port (
doa : out std_logic_vector (7 downto 0);
dob : out std_logic_vector (7 downto 0);
addra : in std_logic_vector (8 downto 0);
addrb : in std_logic_vector (8 downto 0);
clka : in std_ulogic;
clkb : in std_ulogic;
dia : in std_logic_vector (7 downto 0);
dib : in std_logic_vector (7 downto 0);
ena : in std_ulogic;
enb : in std_ulogic;
rsta : in std_ulogic;
rstb : in std_ulogic;
wea : in std_ulogic;
web : in std_ulogic
);
end component;
component RAMB4_S16_S16
generic (SIM_COLLISION_CHECK : string := "ALL");
port (
doa : out std_logic_vector (15 downto 0);
dob : out std_logic_vector (15 downto 0);
addra : in std_logic_vector (7 downto 0);
addrb : in std_logic_vector (7 downto 0);
clka : in std_ulogic;
clkb : in std_ulogic;
dia : in std_logic_vector (15 downto 0);
dib : in std_logic_vector (15 downto 0);
ena : in std_ulogic;
enb : in std_ulogic;
rsta : in std_ulogic;
rstb : in std_ulogic;
wea : in std_ulogic;
web : in std_ulogic
);
end component;
signal gnd, vcc : std_ulogic;
signal do1, do2, di1, di2 : std_logic_vector(dbits+16 downto 0);
signal addr1, addr2 : std_logic_vector(19 downto 0);
begin
gnd <= '0'; vcc <= '1';
dataout1 <= do1(dbits-1 downto 0); dataout2 <= do2(dbits-1 downto 0);
di1(dbits-1 downto 0) <= datain1; di1(dbits+16 downto dbits) <= (others => '0');
di2(dbits-1 downto 0) <= datain2; di2(dbits+16 downto dbits) <= (others => '0');
addr1(abits-1 downto 0) <= address1; addr1(19 downto abits) <= (others => '0');
addr2(abits-1 downto 0) <= address2; addr2(19 downto abits) <= (others => '0');
a8 : if abits <= 8 generate
x : for i in 0 to ((dbits-1)/16) generate
r0 : RAMB4_S16_S16
generic map (SIM_COLLISION_CHECK => "GENERATE_X_ONLY")
port map (
do1(((i+1)*16)-1 downto i*16), do2(((i+1)*16)-1 downto i*16),
addr1(7 downto 0), addr2(7 downto 0), clk1, clk2,
di1(((i+1)*16)-1 downto i*16), di2(((i+1)*16)-1 downto i*16),
enable1, enable2, gnd, gnd, write1, write2);
end generate;
end generate;
a9 : if abits = 9 generate
x : for i in 0 to ((dbits-1)/8) generate
r0 : RAMB4_S8_S8
generic map (SIM_COLLISION_CHECK => "GENERATE_X_ONLY")
port map (
do1(((i+1)*8)-1 downto i*8), do2(((i+1)*8)-1 downto i*8),
addr1(8 downto 0), addr2(8 downto 0), clk1, clk2,
di1(((i+1)*8)-1 downto i*8), di2(((i+1)*8)-1 downto i*8),
enable1, enable2, gnd, gnd, write1, write2);
end generate;
end generate;
a10: if abits = 10 generate
x : for i in 0 to ((dbits-1)/4) generate
r0 : RAMB4_S4_S4
generic map (SIM_COLLISION_CHECK => "GENERATE_X_ONLY")
port map (
do1(((i+1)*4)-1 downto i*4), do2(((i+1)*4)-1 downto i*4),
addr1(9 downto 0), addr2(9 downto 0), clk1, clk2,
di1(((i+1)*4)-1 downto i*4), di2(((i+1)*4)-1 downto i*4),
enable1, enable2, gnd, gnd, write1, write2);
end generate;
end generate;
a11: if abits = 11 generate
x : for i in 0 to ((dbits-1)/2) generate
r0 : RAMB4_S2_S2
generic map (SIM_COLLISION_CHECK => "GENERATE_X_ONLY")
port map (
do1(((i+1)*2)-1 downto i*2), do2(((i+1)*2)-1 downto i*2),
addr1(10 downto 0), addr2(10 downto 0), clk1, clk2,
di1(((i+1)*2)-1 downto i*2), di2(((i+1)*2)-1 downto i*2),
enable1, enable2, gnd, gnd, write1, write2);
end generate;
end generate;
a12: if abits = 12 generate
x : for i in 0 to ((dbits-1)/1) generate
r0 : RAMB4_S1_S1
generic map (SIM_COLLISION_CHECK => "GENERATE_X_ONLY")
port map (
do1(((i+1)*1)-1 downto i*1), do2(((i+1)*1)-1 downto i*1),
addr1(11 downto 0), addr2(11 downto 0), clk1, clk2,
di1(((i+1)*1)-1 downto i*1), di2(((i+1)*1)-1 downto i*1),
enable1, enable2, gnd, gnd, write1, write2);
end generate;
end generate;
-- pragma translate_off
a_to_high : if abits > 12 generate
x : process
begin
assert false
report "Address depth larger than 12 not supported for virtex_syncram_dp"
severity failure;
wait;
end process;
end generate;
-- pragma translate_on
end;
| gpl-3.0 | 72f1506f00a987b69fc405bff63a38e1 | 0.600238 | 2.977889 | false | false | false | false |
pwsoft/fpga_examples | rtl/general/gen_fifo_tb.vhd | 1 | 4,081 | -- -----------------------------------------------------------------------
--
-- Syntiac's generic VHDL support files.
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2010 by Peter Wendrich ([email protected])
-- http://www.syntiac.com/fpga64.html
--
-- This source file is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- -----------------------------------------------------------------------
--
-- gen_fifo_tb.vhd
--
-- -----------------------------------------------------------------------
--
-- Testbench for gen_fifo
--
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
-- -----------------------------------------------------------------------
entity gen_fifo_tb is
end entity;
-- -----------------------------------------------------------------------
architecture rtl of gen_fifo_tb is
signal clk : std_logic := '0';
signal stop : std_logic := '0';
signal d_ena : std_logic := '0';
signal d : unsigned(7 downto 0) := (others => '0');
signal q_ena : std_logic := '0';
signal q : unsigned(7 downto 0);
signal empty : std_logic;
signal full : std_logic;
function tohex(value : in unsigned) return string is
constant hex_digit : string(1 to 16) := "0123456789ABCDEF";
variable input : unsigned(value'high downto value'low);
variable rlen : integer;
variable output : string(1 to 16) := (others => '0');
begin
input := value;
rlen := value'length / 4;
for i in output'range loop
if i <= rlen then
output(i) := hex_digit(to_integer(input(input'high-(i-1)*4 downto input'high-(i*4-1))) + 1);
end if;
end loop;
return output(1 to rlen);
end function;
procedure waitRisingEdge is
begin
wait until clk = '0';
wait until clk = '1';
wait for 0.5 ns;
end procedure;
procedure waitCheck(
expected_empty:std_logic;
expected_full:std_logic) is
begin
waitRisingEdge;
assert(expected_empty = empty) report "q output " & tohex("000" & empty) & " expected " & tohex("000" & expected_empty);
assert(expected_full = full) report "q output " & tohex("000" & full) & " expected " & tohex("000" & expected_full);
end procedure;
procedure waitCheck(
expected_q:unsigned(7 downto 0);
expected_empty:std_logic;
expected_full:std_logic) is
begin
waitRisingEdge;
assert(expected_q = q) report "q output " & tohex(q) & " expected " & tohex(expected_q);
assert(expected_empty = empty) report "q output " & tohex("000" & empty) & " expected " & tohex("000" & expected_empty);
assert(expected_full = full) report "q output " & tohex("000" & full) & " expected " & tohex("000" & expected_full);
end procedure;
begin
gen_fifo_inst : entity work.gen_fifo
generic map (
width => 8,
depth => 4
)
port map (
clk => clk,
d_ena => d_ena,
d => d,
q_ena => q_ena,
q => q,
empty => empty,
full => full
);
clk <= (not stop) and (not clk) after 5 ns;
process
begin
waitCheck(X"00", '1', '0');
d_ena <= '1';
d <= X"55";
waitCheck(X"55", '0', '0');
d_ena <= '1';
d <= X"66";
waitCheck(X"55", '0', '0');
d_ena <= '1';
d <= X"77";
waitCheck(X"55", '0', '0');
d_ena <= '1';
d <= X"88";
waitCheck(X"55", '0', '1');
d_ena <= '0';
q_ena <= '1';
waitCheck(X"66", '0', '0');
waitCheck(X"77", '0', '0');
waitCheck(X"88", '0', '0');
waitCheck('1', '0');
stop <= '1';
wait;
end process;
end architecture;
| lgpl-2.1 | 010e003974b2daf1d267d383c77292e1 | 0.552071 | 3.293785 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/leon3v3/mmu_icache.vhd | 1 | 30,245 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: mmu_icache
-- File: mmu_icache.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Modified: Edvin Catovic - Gaisler Research
-- Description: This unit implements the instruction cache controller.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.config_types.all;
use grlib.config.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.libiu.all;
use gaisler.libcache.all;
use gaisler.mmuconfig.all;
use gaisler.mmuiface.all;
use gaisler.leon3.all;
entity mmu_icache is
generic (
fabtech : integer := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 0;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
lram : integer range 0 to 2 := 0;
lramsize : integer range 1 to 512 := 1;
lramstart : integer range 0 to 255 := 16#8e#;
mmuen : integer range 0 to 1 := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ici : in icache_in_type;
ico : out icache_out_type;
dci : in dcache_in_type;
dco : in dcache_out_type;
mcii : out memory_ic_in_type;
mcio : in memory_ic_out_type;
icrami : out icram_in_type;
icramo : in icram_out_type;
fpuholdn : in std_ulogic;
mmudci : in mmudc_in_type;
mmuici : out mmuic_in_type;
mmuico : in mmuic_out_type
);
end;
architecture rtl of mmu_icache is
constant MUXDATA : boolean := (is_fpga(fabtech) = 1);
constant M_EN : boolean := (mmuen = 1);
constant ILINE_BITS : integer := log2(ilinesize);
constant IOFFSET_BITS : integer := 8 +log2(isetsize) - ILINE_BITS;
constant TAG_LOW : integer := IOFFSET_BITS + ILINE_BITS + 2;
constant OFFSET_HIGH : integer := TAG_LOW - 1;
constant OFFSET_LOW : integer := ILINE_BITS + 2;
constant LINE_HIGH : integer := OFFSET_LOW - 1;
constant LINE_LOW : integer := 2;
constant LRR_BIT : integer := TAG_HIGH + 1;
constant lline : std_logic_vector((ILINE_BITS -1) downto 0) := (others => '1');
constant fline : std_logic_vector((ILINE_BITS -1) downto 0) := (others => '0');
constant SETBITS : integer := log2x(ISETS);
constant ILRUBITS : integer := lru_table(ISETS);
constant LRAM_START : std_logic_vector(7 downto 0) := conv_std_logic_vector(lramstart, 8);
constant LRAM_BITS : integer := log2(lramsize) + 10;
constant LRAMCS_EN : boolean := false;
subtype lru_type is std_logic_vector(ILRUBITS-1 downto 0);
type lru_array is array (0 to 2**IOFFSET_BITS-1) of lru_type; -- lru registers
type rdatatype is (itag, idata, memory); -- sources during cache read
type lru_table_vector_type is array(0 to 3) of std_logic_vector(4 downto 0);
type lru_table_type is array (0 to 2**IOFFSET_BITS-1) of lru_table_vector_type;
type valid_type is array (0 to ISETS-1) of std_logic_vector(ilinesize - 1 downto 0);
subtype lock_type is std_logic_vector(0 to ISETS-1);
function lru_set (lru : lru_type; lock : lock_type) return std_logic_vector is
variable xlru : std_logic_vector(4 downto 0);
variable set : std_logic_vector(SETBITS-1 downto 0);
variable xset : std_logic_vector(1 downto 0);
variable unlocked : integer range 0 to ISETS-1;
begin
set := (others => '0'); xlru := (others => '0'); xset := (others => '0');
xlru(ILRUBITS-1 downto 0) := lru;
if isetlock = 1 then
unlocked := ISETS-1;
for i in ISETS-1 downto 0 loop
if lock(i) = '0' then unlocked := i; end if;
end loop;
end if;
case ISETS is
when 2 =>
if isetlock = 1 then
if lock(0) = '1' then xset(0) := '1'; else xset(0) := xlru(0); end if;
else xset(0) := xlru(0); end if;
when 3 =>
if isetlock = 1 then
xset := conv_std_logic_vector(lru3_repl_table(conv_integer(xlru)) (unlocked), 2);
else
-- xset := conv_std_logic_vector(lru3_repl_table(conv_integer(xlru)) (0), 2);
xset := xlru(2) & (xlru(1) and not xlru(2));
end if;
when 4 =>
if isetlock = 1 then
xset := conv_std_logic_vector(lru4_repl_table(conv_integer(xlru)) (unlocked), 2);
else
-- xset := conv_std_logic_vector(lru4_repl_table(conv_integer(xlru)) (0), 2);
xset := xlru(4 downto 3);
end if;
when others =>
end case;
set := xset(SETBITS-1 downto 0);
return(set);
end;
function lru_calc (lru : lru_type; xset : std_logic_vector) return lru_type is
variable new_lru : lru_type;
variable xnew_lru: std_logic_vector(4 downto 0);
variable xlru : std_logic_vector(4 downto 0);
variable vset : std_logic_vector(SETBITS-1 downto 0);
variable set: integer;
begin
vset := xset; set := conv_integer(vset);
new_lru := (others => '0'); xnew_lru := (others => '0');
xlru := (others => '0'); xlru(ILRUBITS-1 downto 0) := lru;
case ISETS is
when 2 =>
if set = 0 then xnew_lru(0) := '1'; else xnew_lru(0) := '0'; end if;
when 3 =>
xnew_lru(2 downto 0) := lru_3set_table(conv_integer(lru))(set);
when 4 =>
xnew_lru(4 downto 0) := lru_4set_table(conv_integer(lru))(set);
xnew_lru(SETBITS-1 downto 0) := vset;
when others =>
end case;
new_lru := xnew_lru(ILRUBITS-1 downto 0);
return(new_lru);
end;
type istatetype is (idle, trans, streaming, stop);
type icache_control_type is record -- all registers
req, burst, holdn : std_ulogic;
overrun : std_ulogic;
underrun : std_ulogic;
istate : istatetype; -- FSM vector
waddress : std_logic_vector(31 downto 2); -- write address buffer
vaddress : std_logic_vector(31 downto 2); -- virtual address buffer
valid : valid_type; --std_logic_vector(ilinesize-1 downto 0); -- valid bits
hit : std_ulogic;
su : std_ulogic;
flush : std_ulogic; -- flush in progress
flush2 : std_ulogic; -- flush in progress
faddr : std_logic_vector(IOFFSET_BITS - 1 downto 0); -- flush address
diagrdy : std_ulogic;
rndcnt : std_logic_vector(log2x(ISETS)-1 downto 0); -- replace counter
lrr : std_ulogic;
setrepl : std_logic_vector(log2x(ISETS)-1 downto 0); -- set to replace
diagset : std_logic_vector(log2x(ISETS)-1 downto 0);
lock : std_ulogic;
pflush : std_logic;
pflushr : std_logic;
pflushaddr : std_logic_vector(VA_I_U downto VA_I_D);
pflushtyp : std_logic;
cache : std_logic;
trans_op : std_logic;
cmiss : std_ulogic;
bpmiss : std_ulogic;
eocl : std_ulogic;
end record;
type lru_reg_type is record
write : std_ulogic;
waddr : std_logic_vector(IOFFSET_BITS-1 downto 0);
set : std_logic_vector(SETBITS-1 downto 0); --integer range 0 to ISETS-1;
lru : lru_array;
end record;
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant RRES : icache_control_type := (
req => '0',
burst => '0',
holdn => '1',
overrun => '0',
underrun => '0',
istate => idle,
waddress => (others => '0'), -- has special handling
vaddress => (others => '0'), -- has special handling
valid => (others => (others => '0')),
hit => '0',
su => '0',
flush => '0',
flush2 => '0',
faddr => (others => '0'),
diagrdy => '0',
rndcnt => (others => '0'),
lrr => '0',
setrepl => (others => '0'),
diagset => (others => '0'),
lock => '0',
pflush => '0',
pflushr => '0',
pflushaddr => (others => '0'),
pflushtyp => '0',
cache => '0',
trans_op => '0',
cmiss => '0',
bpmiss => '0',
eocl => '0'
);
constant LRES : lru_reg_type := (
write => '0',
waddr => (others => '0'),
set => (others => '0'),
lru => (others => (others => '0'))
);
signal r, c : icache_control_type; -- r is registers, c is combinational
signal rl, cl : lru_reg_type; -- rl is registers, cl is combinational
constant LRAM_EN : integer := conv_integer(conv_std_logic(lram /= 0));
constant icfg : std_logic_vector(31 downto 0) :=
cache_cfg(irepl, isets, ilinesize, isetsize, isetlock, 0,
LRAM_EN, lramsize, lramstart, mmuen);
begin
ictrl : process(rst, r, rl, mcio, ici, dci, dco, icramo, fpuholdn, mmuico, mmudci)
variable rdatasel : rdatatype;
variable twrite, diagen, dwrite : std_ulogic;
variable taddr : std_logic_vector(TAG_HIGH downto LINE_LOW); -- tag address
variable wtag : std_logic_vector(TAG_HIGH downto TAG_LOW); -- write tag value
variable ddatain : std_logic_vector(31 downto 0);
variable rdata : cdatatype;
variable diagdata : std_logic_vector(31 downto 0);
variable vmaskraw : std_logic_vector((ilinesize -1) downto 0);
variable vmask : valid_type;
variable xaddr_inc : std_logic_vector((ILINE_BITS -1) downto 0);
variable lastline, nlastline, nnlastline : std_ulogic;
variable enable : std_ulogic;
variable error : std_ulogic;
variable whit, hit, valid, nvalid : std_ulogic;
variable cacheon : std_ulogic;
variable v : icache_control_type;
variable branch : std_ulogic;
variable eholdn : std_ulogic;
variable mds, write : std_ulogic;
variable memaddr : std_logic_vector(31 downto 2);
variable set : integer range 0 to MAXSETS-1;
variable setrepl : std_logic_vector(log2x(ISETS)-1 downto 0); -- set to replace
variable ctwrite, cdwrite, validv, nvalidv : std_logic_vector(0 to MAXSETS-1);
variable wlrr : std_ulogic;
variable vl : lru_reg_type;
variable vdiagset, rdiagset : integer range 0 to ISETS-1;
variable lock : std_logic_vector(0 to ISETS-1);
variable wlock : std_ulogic;
variable tag : cdatatype;
variable lramacc, ilramwr, lramcs : std_ulogic;
variable iladdr : std_logic_vector(TAG_HIGH downto LINE_LOW);
variable pftag : std_logic_vector(31 downto 2);
variable mmuici_trans_op : std_logic;
variable mmuici_su : std_logic;
variable mhold : std_ulogic;
variable shtag : std_logic_vector(ilinesize-1 downto 0);
begin
-- init local variables
v := r; vl := rl; vl.write := '0'; vl.set := r.setrepl;
vl.waddr := r.waddress(OFFSET_HIGH downto OFFSET_LOW);
v.cmiss := '0'; mhold := '0';
mds := '1'; dwrite := '0'; twrite := '0'; diagen := '0'; error := '0';
write := mcio.ready; v.diagrdy := '0'; v.holdn := '1';
if icen /= 0 then
cacheon := dco.icdiag.cctrl.ics(0) and not (r.flush
);
else cacheon := '0'; end if;
enable := '1'; branch := '0';
eholdn := dco.hold and fpuholdn;
rdatasel := idata; -- read data from cache as default
ddatain := mcio.data; -- load full word from memory
wtag(TAG_HIGH downto TAG_LOW) := r.vaddress(TAG_HIGH downto TAG_LOW);
wlrr := r.lrr; wlock := r.lock;
set := 0; ctwrite := (others => '0'); cdwrite := (others => '0');
vdiagset := 0; rdiagset := 0; lock := (others => '0'); ilramwr := '0';
lramacc := '0'; lramcs := '0'; iladdr := (others => '0');
vdiagset := 0; rdiagset := 0; lock := (others => '0');
pftag := (others => '0'); validv := (others => '0');
v.trans_op := r.trans_op and (not mmuico.grant);
mmuici_trans_op := r.trans_op;
mmuici_su := ici.su;
-- random replacement counter
if ISETS > 1 then
if conv_integer(r.rndcnt) = (ISETS - 1) then v.rndcnt := (others => '0');
else v.rndcnt := r.rndcnt + 1; end if;
end if;
-- generate lock bits
if isetlock = 1 then
for i in 0 to ISETS-1 loop lock(i) := icramo.tag(i)(CTAG_LOCKPOS); end loop;
end if;
--local ram access
if (lram /= 0) and (ici.fpc(31 downto 24) = LRAM_START) then lramacc := '1'; end if;
-- generate cache hit and valid bits
hit := '0';
if irepl = dir then
set := conv_integer(ici.fpc(OFFSET_HIGH + SETBITS downto OFFSET_HIGH+1));
if (icramo.tag(set)(TAG_HIGH downto TAG_LOW) = ici.fpc(TAG_HIGH downto TAG_LOW))
and ((icramo.ctx(set) = mmudci.mmctrl1.ctx) or (mmudci.mmctrl1.e = '0') or not M_EN)
then hit := not r.flush; end if;
validv(set) := genmux(ici.fpc(LINE_HIGH downto LINE_LOW),
icramo.tag(set)(ilinesize -1 downto 0));
else
for i in ISETS-1 downto 0 loop
if (icramo.tag(i)(TAG_HIGH downto TAG_LOW) = ici.fpc(TAG_HIGH downto TAG_LOW))
and ((icramo.ctx(i) = mmudci.mmctrl1.ctx) or (mmudci.mmctrl1.e = '0') or not M_EN)
then hit := not r.flush; set := i; end if;
validv(i) := genmux(ici.fpc(LINE_HIGH downto LINE_LOW),
icramo.tag(i)(ilinesize -1 downto 0));
end loop;
end if;
for i in ISETS-1 downto 0 loop
shtag := (others => '0');
shtag(ilinesize-2 downto 0) := icramo.tag(i)(ilinesize-1 downto 1);
nvalidv(i) := genmux(ici.fpc(LINE_HIGH downto LINE_LOW), shtag);
end loop;
if (lramacc = '1') and (ISETS > 1) then set := 1; end if;
if ici.fpc(LINE_HIGH downto LINE_LOW) = lline then lastline := '1';
else lastline := '0'; end if;
if r.waddress(LINE_HIGH downto LINE_LOW) = lline((ILINE_BITS -1) downto 0) then
nlastline := '1';
else nlastline := '0'; end if;
if r.waddress(LINE_HIGH downto LINE_LOW+1) = lline((ILINE_BITS -1) downto 1) then
nnlastline := '1';
else nnlastline := '0'; end if;
valid := validv(set);
nvalid := nvalidv(set);
xaddr_inc := r.waddress(LINE_HIGH downto LINE_LOW) + 1;
if mcio.ready = '1' then
v.waddress(LINE_HIGH downto LINE_LOW) := xaddr_inc;
end if;
xaddr_inc := r.vaddress(LINE_HIGH downto LINE_LOW) + 1;
if mcio.ready = '1' then
v.vaddress(LINE_HIGH downto LINE_LOW) := xaddr_inc;
end if;
taddr := ici.rpc(TAG_HIGH downto LINE_LOW);
-- main state machine
case r.istate is
when idle => -- main state and cache hit
for i in 0 to ISETS-1 loop
v.valid(i) := icramo.tag(i)(ilinesize-1 downto 0);
end loop;
--v.hit := '0';
v.hit := hit;
v.su := ici.su;
-- if (ici.inull or eholdn) = '0' then
if eholdn = '0' then
taddr := ici.fpc(TAG_HIGH downto LINE_LOW);
else taddr := ici.rpc(TAG_HIGH downto LINE_LOW); end if;
v.burst := dco.icdiag.cctrl.burst and not lastline;
if (eholdn and lramacc)='1' then v.bpmiss:='0'; v.eocl:='0'; end if;
if (eholdn and not (ici.inull or lramacc)) = '1' then
v.bpmiss := not (cacheon and hit and valid) and ici.nobpmiss;
v.eocl := not nvalid;
if not (cacheon and hit and valid) = '1' and ici.nobpmiss='0' then
v.istate := streaming;
v.holdn := '0'; v.overrun := '1'; v.cmiss := '1';
if M_EN and (mmudci.mmctrl1.e = '1') then
v.istate := trans;
mmuici_trans_op := '1';
v.trans_op := not mmuico.grant;
v.cache := '0';
--v.req := '0';
else
v.req := '1';
v.cache := '1';
end if;
else
if (ISETS > 1) and (irepl = lru) then vl.write := '1'; end if;
end if;
v.waddress := ici.fpc(31 downto 2);
v.vaddress := ici.fpc(31 downto 2);
end if;
if dco.icdiag.enable = '1' then
diagen := '1';
end if;
ddatain := dci.maddress;
if (ISETS > 1) then
if (irepl = lru) then
vl.set := conv_std_logic_vector(set, SETBITS);
vl.waddr := ici.fpc(OFFSET_HIGH downto OFFSET_LOW);
end if;
v.setrepl := conv_std_logic_vector(set, SETBITS);
if (((not hit) and (not r.flush)) = '1') then
case irepl is
when rnd =>
if isetlock = 1 then
if lock(conv_integer(r.rndcnt)) = '0' then v.setrepl := r.rndcnt;
else
v.setrepl := conv_std_logic_vector(ISETS-1, SETBITS);
for i in ISETS-1 downto 0 loop
if (lock(i) = '0') and (i>conv_integer(r.rndcnt)) then
v.setrepl := conv_std_logic_vector(i, SETBITS);
end if;
end loop;
end if;
else
v.setrepl := r.rndcnt;
end if;
when dir =>
v.setrepl := ici.fpc(OFFSET_HIGH+SETBITS downto OFFSET_HIGH+1);
when lru =>
v.setrepl := lru_set(rl.lru(conv_integer(ici.fpc(OFFSET_HIGH downto OFFSET_LOW))), lock(0 to ISETS-1));
when lrr =>
v.setrepl := (others => '0');
if isetlock = 1 then
if lock(0) = '1' then v.setrepl(0) := '1';
else
v.setrepl(0) := icramo.tag(0)(CTAG_LRRPOS) xor icramo.tag(1)(CTAG_LRRPOS);
end if;
else
v.setrepl(0) := icramo.tag(0)(CTAG_LRRPOS) xor icramo.tag(1)(CTAG_LRRPOS);
end if;
if v.setrepl(0) = '0' then v.lrr := not icramo.tag(0)(CTAG_LRRPOS);
else v.lrr := icramo.tag(0)(CTAG_LRRPOS); end if;
end case;
end if;
if (isetlock = 1) then
if (hit and lock(set)) = '1' then v.lock := '1';
else v.lock := '0'; end if;
end if;
end if;
when trans =>
if M_EN then
v.holdn := '0';
if (mmuico.transdata.finish = '1') then
if mmuico.transdata.accexc = '1' then
-- if su then always do mexc
error := r.su or not mmudci.mmctrl1.nf; mds := '0';
v.holdn := '0'; v.istate := stop; v.burst := '0';
else
v.cache := mmuico.transdata.cache;
v.waddress := mmuico.transdata.data(31 downto 2);
v.istate := streaming; v.req := '1';
end if;
end if;
mhold := '1';
end if;
when streaming => -- streaming: update cache and send data to IU
rdatasel := memory;
taddr(TAG_HIGH downto LINE_LOW) := r.vaddress(TAG_HIGH downto LINE_LOW);
branch := (ici.fbranch and r.overrun) or
(ici.rbranch and (not r.overrun));
v.underrun := r.underrun or
(write and ((ici.inull or not eholdn) and (mcio.ready and not (r.overrun and not r.underrun))));
v.overrun := (r.overrun or (eholdn and not ici.inull)) and
not (write or r.underrun);
if mcio.ready = '1' then
-- mds := not (v.overrun and not r.underrun);
mds := not (r.overrun and not r.underrun);
-- v.req := r.burst;
v.burst := v.req and not (nnlastline and mcio.ready);
end if;
if mcio.grant = '1' then
v.req := dco.icdiag.cctrl.burst and r.burst and
(not (nnlastline and mcio.ready)) and (dco.icdiag.cctrl.burst or (not branch)) and
not (v.underrun and not cacheon);
v.burst := v.req and not (nnlastline and mcio.ready);
end if;
v.underrun := (v.underrun or branch) and not v.overrun;
v.holdn := not (v.overrun or v.underrun);
if (mcio.ready = '1') and (r.req = '0') then --(v.burst = '0') then
v.underrun := '0'; v.overrun := '0';
v.istate := stop; v.holdn := '0';
end if;
when stop => -- return to main
taddr := ici.fpc(TAG_HIGH downto LINE_LOW);
v.istate := idle; v.flush := r.flush2;
when others => v.istate := idle;
end case;
if mcio.retry = '1' then v.req := '1'; end if;
if lram /= 0 then
if LRAMCS_EN then
if taddr(31 downto 24) = LRAM_START then lramcs := '1'; else lramcs := '0'; end if;
else
lramcs := '1';
end if;
end if;
-- Generate new valid bits write strobe
vmaskraw := decode(r.waddress(LINE_HIGH downto LINE_LOW));
twrite := write;
if cacheon = '0' then
twrite := '0'; vmask := (others => (others => '0'));
elsif (dco.icdiag.cctrl.ics = "01") then
twrite := twrite and r.hit;
for i in 0 to ISETS-1 loop
vmask(i) := icramo.tag(i)(ilinesize-1 downto 0) or vmaskraw;
end loop;
else
for i in 0 to ISETS-1 loop
if r.hit = '1' then vmask(i) := r.valid(i) or vmaskraw;
else vmask(i) := vmaskraw; end if;
end loop;
end if;
if (mcio.mexc or not mcio.cache) = '1' then
twrite := '0'; dwrite := '0';
else dwrite := twrite; end if;
if twrite = '1' then
v.valid := vmask; v.hit := '1';
if (ISETS > 1) and (irepl = lru) then vl.write := '1'; end if;
end if;
if (ISETS > 1) and (irepl = lru) and (rl.write = '1') then
vl.lru(conv_integer(rl.waddr)) :=
lru_calc(rl.lru(conv_integer(rl.waddr)), rl.set);
end if;
-- cache write signals
if ISETS > 1 then setrepl := r.setrepl; else setrepl := (others => '0'); end if;
if twrite = '1' then ctwrite(conv_integer(setrepl)) := '1'; end if;
if dwrite = '1' then cdwrite(conv_integer(setrepl)) := '1'; end if;
-- diagnostic cache access
if diagen = '1' then
if (ISETS /= 1) then
if (dco.icdiag.ilramen = '1') and (lram /= 0) then
v.diagset := conv_std_logic_vector(1, SETBITS);
else
v.diagset := dco.icdiag.addr(SETBITS -1 + TAG_LOW downto TAG_LOW);
end if;
end if;
end if;
case ISETS is
when 1 =>
vdiagset := 0; rdiagset := 0;
when 3 =>
if conv_integer(v.diagset) < 3 then vdiagset := conv_integer(v.diagset); end if;
if conv_integer(r.diagset) < 3 then rdiagset := conv_integer(r.diagset); end if;
when others =>
vdiagset := conv_integer(v.diagset);
rdiagset := conv_integer(r.diagset);
end case;
diagdata := icramo.data(rdiagset);
if diagen = '1' then -- diagnostic or local ram access
taddr(TAG_HIGH downto LINE_LOW) := dco.icdiag.addr(TAG_HIGH downto LINE_LOW);
wtag(TAG_HIGH downto TAG_LOW) := dci.maddress(TAG_HIGH downto TAG_LOW);
wlrr := dci.maddress(CTAG_LRRPOS);
wlock := dci.maddress(CTAG_LOCKPOS);
if (dco.icdiag.ilramen = '1') and (lram /= 0) then
ilramwr := not dco.icdiag.read;
elsif dco.icdiag.tag = '1' then
twrite := not dco.icdiag.read; dwrite := '0';
ctwrite := (others => '0'); cdwrite := (others => '0');
ctwrite(vdiagset) := not dco.icdiag.read;
diagdata := icramo.tag(rdiagset);
else
dwrite := not dco.icdiag.read; twrite := '0';
cdwrite := (others => '0'); cdwrite(vdiagset) := not dco.icdiag.read;
ctwrite := (others => '0');
end if;
vmask := (others => dci.maddress(ilinesize -1 downto 0));
v.diagrdy := '1';
end if;
-- select data to return on read access
rdata := icramo.data;
case rdatasel is
when memory => rdata(0) := mcio.data; set := 0;
when others =>
end case;
if MUXDATA then
rdata(0) := rdata(set); set := 0;
end if;
-- cache flush
if ((ici.flush or
dco.icdiag.flush) = '1') and (icen /= 0)
then
v.flush := '1'; v.flush2 := '1'; v.faddr := (others => '0');
v.pflush := dco.icdiag.pflush; wtag := (others => '0');
v.pflushr := '1';
v.pflushaddr := dco.icdiag.pflushaddr;
v.pflushtyp := dco.icdiag.pflushtyp;
end if;
if lram /= 0 then iladdr := taddr; end if;
if (r.flush2 = '1') and (icen /= 0) then
twrite := '1'; ctwrite := (others => '1'); vmask := (others => (others => '0'));
v.faddr := r.faddr + 1;
taddr(OFFSET_HIGH downto OFFSET_LOW) := r.faddr;
wlrr := '0'; wlock := '0'; wtag := (others => '0'); v.lrr := '0';
if ((r.faddr(IOFFSET_BITS -1) and not v.faddr(IOFFSET_BITS -1))
) = '1' then
v.flush2 := '0';
end if;
-- precise flush, ASI_FLUSH_PAGE & ASI_FLUSH_CTX
if M_EN then
if r.pflush = '1' then
twrite := '0'; ctwrite := (others => '0');
v.pflushr := not r.pflushr;
if r.pflushr = '0' then
for i in ISETS-1 downto 0 loop
pftag(OFFSET_HIGH downto OFFSET_LOW) := r.faddr;
pftag(TAG_HIGH downto TAG_LOW) := icramo.tag(i)(TAG_HIGH downto TAG_LOW); --icramo.itramout(i).tag;
--if (icramo.itramout(i).ctx = mmudci.mmctrl1.ctx) and
-- ((pftag(VA_I_U downto VA_I_D) = r.pflushaddr(VA_I_U downto VA_I_D)) or
-- (r.pflushtyp = '1')) then
ctwrite(i) := '1';
--end if;
end loop;
end if;
end if;
end if;
end if;
-- reset
if (not RESET_ALL) and (rst = '0') then
v.istate := idle; v.req := '0'; v.burst := '0'; v.holdn := '1';
v.flush := '0'; v.flush2 := '0'; v.overrun := '0'; v.underrun := '0';
v.rndcnt := (others => '0'); v.lrr := '0'; v.setrepl := (others => '0');
v.diagset := (others => '0'); v.lock := '0';
v.waddress := ici.fpc(31 downto 2);
v.vaddress := ici.fpc(31 downto 2);
v.trans_op := '0';
v.bpmiss := '0';
end if;
if (not RESET_ALL and rst = '0') or (r.flush = '1') then
vl.lru := (others => (others => '0'));
end if;
-- Drive signals
c <= v; -- register inputs
cl <= vl; -- lru register inputs
-- tag ram inputs
enable := enable;
for i in 0 to ISETS-1 loop
tag(i) := (others => '0');
tag(i)(ilinesize-1 downto 0) := vmask(i);
tag(i)(TAG_HIGH downto TAG_LOW) := wtag;
tag(i)(CTAG_LRRPOS) := wlrr;
tag(i)(CTAG_LOCKPOS) := wlock;
end loop;
icrami.tag <= tag;
icrami.tenable <= enable;
icrami.twrite <= ctwrite;
icrami.flush <= r.flush2;
icrami.ctx <= mmudci.mmctrl1.ctx;
-- data ram inputs
icrami.denable <= enable;
icrami.address <= taddr(19+LINE_LOW downto LINE_LOW);
icrami.data <= ddatain;
icrami.dwrite <= cdwrite;
-- local ram inputs
icrami.ldramin.address <= iladdr(19+LINE_LOW downto LINE_LOW);
icrami.ldramin.enable <= (dco.icdiag.ilramen or lramcs or lramacc);
icrami.ldramin.read <= dco.icdiag.ilramen or lramacc;
icrami.ldramin.write <= ilramwr;
-- memory controller inputs
mcii.address(31 downto 2) <= r.waddress(31 downto 2);
mcii.address(1 downto 0) <= "00";
mcii.su <= r.su;
mcii.burst <= r.burst and r.req;
mcii.req <= r.req;
mcii.flush <= r.flush;
-- mmu <-> icache
mmuici.trans_op <= mmuici_trans_op;
mmuici.transdata.data <= r.waddress(31 downto 2) & "00";
mmuici.transdata.su <= r.su;
mmuici.transdata.isid <= id_icache;
mmuici.transdata.read <= '1';
mmuici.transdata.wb_data <= (others => '0');
-- IU data cache inputs
ico.data <= rdata;
ico.mexc <= mcio.mexc or error;
ico.hold <= r.holdn;
ico.mds <= mds;
ico.flush <= r.flush;
ico.diagdata <= diagdata;
ico.diagrdy <= r.diagrdy;
ico.set <= conv_std_logic_vector(set, 2);
ico.cfg <= icfg;
ico.bpmiss <= r.bpmiss;
ico.eocl <= r.eocl;
ico.cstat.chold <= not r.holdn;
ico.cstat.mhold <= mhold;
ico.cstat.tmiss <= mmuico.tlbmiss;
ico.cstat.cmiss <= r.cmiss;
if r.istate = idle then ico.idle <= '1'; else ico.idle <= '0'; end if;
end process;
-- Local registers
regs1 : process(clk)
begin
if rising_edge(clk) then
r <= c;
if RESET_ALL and (rst = '0') then
r <= RRES;
r.waddress <= ici.fpc(31 downto 2);
r.vaddress <= ici.fpc(31 downto 2);
end if;
end if;
end process;
regs2 : if (ISETS > 1) and (irepl = lru) generate
regs2 : process(clk)
begin
if rising_edge(clk) then
rl <= cl;
if RESET_ALL and (rst = '0') then
rl <= LRES;
end if;
end if;
end process;
end generate;
nolru : if (ISETS = 1) or (irepl /= lru) generate
rl.write <= '0'; rl.waddr <= (others => '0');
rl.set <= (others => '0'); rl.lru <= (others => (others => '0'));
end generate;
-- pragma translate_off
chk : process
begin
assert not ((ISETS > 2) and (irepl = lrr)) report
"Wrong instruction cache configuration detected: LRR replacement requires 2 sets"
severity failure;
wait;
end process;
-- pragma translate_on
end ;
| gpl-3.0 | 370119ff2b7f0aae33beb2ba67f5fc46 | 0.550967 | 3.465681 | false | false | false | false |
ARC-Lab-UF/UAA | src/ram.vhd | 1 | 4,993 | -- Copyright (c) 2015 University of Florida
--
-- This file is part of uaa.
--
-- uaa is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- uaa is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with uaa. If not, see <http://www.gnu.org/licenses/>.
-- Greg Stitt
-- University of Florida
-- Description:
-- The ram entity implements a ram with a standard 1-read port, 1-write port
-- interface. The ram is configurable in terms of data width (width of each
-- word), the address width, and the number of words. The ram has a write
-- enable for writes, but does not contain a read enable. Instead, the ram
-- reads from the read address every cycle.
--
-- The entity contains several different architectures that implement different
-- ram behaviors. e.g. synchronous reads, asynchronous reads, synchronoous
-- reads during writes.
--
-- Notes:
-- Asychronous reads are not supported by all FPGAs.
--
-------------------------------------------------------------------------------
-- Generics Description
-- word_width : The width in bits of a single word (required)
-- addr_width : The width in bits of an address, which also defines the
-- number of words (required)
-- num_words : The number of words in the memory. This generic will
-- usually be 2**addr_width, but the entity supports
-- non-powers of 2 (required)
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Port Description:
-- clk : clock input
-- wen : write enable (active high)
-- waddr : write address
-- wdata : write data
-- raddr : read address
-- rdata : read data
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ram is
generic (
num_words : positive;
word_width : positive;
addr_width : positive
);
port (
clk : in std_logic;
-- write port
wen : in std_logic;
waddr : in std_logic_vector(addr_width-1 downto 0);
wdata : in std_logic_vector(word_width-1 downto 0);
-- read port
raddr : in std_logic_vector(addr_width-1 downto 0);
rdata : out std_logic_vector(word_width-1 downto 0)
);
end entity;
-- This architecture uses asynchronous reads that return the read data in the
-- same cycle.
architecture ASYNC_READ of ram is
type memory_type is array (natural range <>) of std_logic_vector(word_width-1 downto 0);
signal memory : memory_type(num_words-1 downto 0) := (others => (others => '0'));
begin
process(clk)
begin
if clk'event and clk = '1' then
if wen = '1' then
memory(to_integer(unsigned(waddr))) <= wdata;
end if;
end if;
end process;
rdata <= memory(to_integer(unsigned(raddr)));
end ASYNC_READ;
-- This architecture uses synchronous reads with a one-cycle delay. In the case
-- of reading and writing to the same address, the read returns the new data
-- that was written.
architecture SYNC_READ_DURING_WRITE of ram is
type memory_type is array (natural range <>) of std_logic_vector(word_width-1 downto 0);
signal memory : memory_type(num_words-1 downto 0) := (others => (others => '0'));
signal raddr_reg : std_logic_vector(addr_width-1 downto 0);
begin
process(clk)
begin
if clk'event and clk = '1' then
if wen = '1' then
memory(to_integer(unsigned(waddr))) <= wdata;
end if;
raddr_reg <= raddr;
end if;
end process;
rdata <= memory(to_integer(unsigned(raddr_reg)));
end SYNC_READ_DURING_WRITE;
-- This architecture uses synchronous reads with a one-cycle delay. In the case
-- of reading and writing to the same address, the read returns the data at
-- the address before the write.
architecture SYNC_READ of ram is
type memory_type is array (natural range <>) of std_logic_vector(word_width-1 downto 0);
signal memory : memory_type(num_words-1 downto 0) := (others => (others => '0'));
begin
process(clk)
begin
if clk'event and clk = '1' then
if wen = '1' then
memory(to_integer(unsigned(waddr))) <= wdata;
end if;
rdata <= memory(to_integer(unsigned(raddr)));
end if;
end process;
end SYNC_READ;
| gpl-3.0 | c7b77cf4b9eda11ffda210c7f0765c67 | 0.601442 | 4.09598 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/ddr/ddrpkg.vhd | 1 | 40,578 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: ddrpkg
-- File: ddrpkg.vhd
-- Author: Magnus Hjorth - Aeroflex Gaisler
-- Description: Components and types for DDR SDRAM controllers
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library techmap;
use techmap.gencomp.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
package ddrpkg is
type ddrctrl_in_type is record
-- Data signals
data : std_logic_vector (127 downto 0);-- data in
cb : std_logic_vector(63 downto 0); -- checkbits in
-- Bus/timing control signals
datavalid : std_logic; -- Data-valid signal (DDR2,LPDDR2,LPDDR3)
writereq : std_logic; -- Write-data request (LPDDR2,LPDDR3)
-- Calibration and configuration
regrdata : std_logic_vector(63 downto 0); -- PHY-specific reg in (DDR2)
end record;
constant ddrctrl_in_none : ddrctrl_in_type :=
((others => '0'), (others => '0'), '0', '0', (others => '0'));
type ddrctrl_out_type is record
-- Control signals to memory
sdcke : std_logic_vector ( 1 downto 0); -- clk en
sdcsn : std_logic_vector ( 1 downto 0); -- chip sel
sdwen : std_ulogic; -- write en (DDR1,DDR2,LPDDR1)
rasn : std_ulogic; -- row addr stb (DDR1,DDR2,LPDDR1)
casn : std_ulogic; -- col addr stb (DDR1,DDR2,LPDDR1)
address : std_logic_vector(14 downto 0); -- address out (DDR1,DDR2,LPDDR1)
ba : std_logic_vector (2 downto 0); -- bank address (DDR1,DDR2,LPDDR1)
odt : std_logic_vector(1 downto 0); -- On Die Termination (DDR2,LPDDR3)
ca : std_logic_vector(19 downto 0); -- Ctrl/Addr bus (LPDDR2,LPDDR3)
-- Data signals
data : std_logic_vector(127 downto 0); -- data out
dqm : std_logic_vector(15 downto 0); -- data i/o mask
cb : std_logic_vector(63 downto 0); -- checkbits
cbdqm : std_logic_vector(7 downto 0); -- checkbits data mask
-- Bus/timing control signals
bdrive : std_ulogic; -- bus drive (DDR1,DDR2,LPDDR1)
qdrive : std_ulogic; -- bus drive (DDR1,DDR2,LPDDR1)
nbdrive : std_ulogic; -- bdrive 1 cycle early (DDR2)
sdck : std_logic_vector(2 downto 0); -- Clock enable (DDR1,LPDDR1,LPDDR2,LPDDR3)
moben : std_logic; -- Mobile DDR mode (DDR1/LPDDR1)
oct : std_logic; -- On Chip Termination (DDR2)
dqs_gate : std_logic; -- DQS gate control (DDR2)
read_pend : std_logic_vector(7 downto 0); -- Read pending within 7...0
-- cycles (not including phy
-- delays) (DDR2,LPDDR2,LPDDR3)
wrpend : std_logic_vector(7 downto 0); -- Write pending (LPDDR2,LPDDR3)
boot : std_ulogic; -- Boot clock selection (LPDDR2,LPDDR3)
-- Calibration and configuration
cal_en : std_logic_vector(7 downto 0); -- enable delay calibration (DDR2)
cal_inc : std_logic_vector(7 downto 0); -- inc/dec delay (DDR2)
cal_pll : std_logic_vector(1 downto 0); -- (enable,inc/dec) pll phase (DDR2)
cal_rst : std_logic; -- calibration reset (DDR2)
conf : std_logic_vector(63 downto 0); -- Conf. interface (DDR1,LPDDR1)
cbcal_en : std_logic_vector(3 downto 0); -- CB enable delay calib (DDR2)
cbcal_inc : std_logic_vector(3 downto 0); -- CB inc/dec delay (DDR2)
regwdata : std_logic_vector(63 downto 0); -- Reg Write data (DDR2)
regwrite : std_logic_vector(1 downto 0); -- Reg write strobe (DDR2)
-- Status outputs to front-end
ce : std_ulogic; -- Error corrected
end record;
constant ddrctrl_out_none : ddrctrl_out_type :=
((others => '0'), (others => '0'), '0', '0', '0', (others => '0'), (others => '0'),
(others => '0'), (others => '0'), (others => '0'), (others => '0'),
(others => '0'), (others => '0'), '0', '0', '0', (others => '0'),
'0', '0', '0', (others => '0'), (others => '0'), '0', (others => '0'),
(others => '0'), (others => '0'), '0', (others => '0'),
(others => '0'), (others => '0'), (others => '0'), (others => '0'), '0' );
-----------------------------------------------------------------------------
-- DDR2SPA types and components
-----------------------------------------------------------------------------
-- DDR2 controller without PHY
component ddr2spax is
generic (
memtech : integer := 0;
phytech : integer := 0;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
ddrbits : integer := 32;
burstlen : integer := 8;
MHz : integer := 100;
TRFC : integer := 130;
col : integer := 9;
Mbyte : integer := 8;
pwron : integer := 0;
oepol : integer := 0;
readdly : integer := 1;
odten : integer := 0;
octen : integer := 0;
dqsgating : integer := 0;
nosync : integer := 0;
eightbanks : integer range 0 to 1 := 0; -- Set to 1 if 8 banks instead of 4
dqsse : integer range 0 to 1 := 0; -- single ended DQS
ddr_syncrst: integer range 0 to 1 := 0;
ahbbits : integer := ahbdw;
ft : integer range 0 to 1 := 0;
bigmem : integer range 0 to 1 := 0;
raspipe : integer range 0 to 1 := 0;
hwidthen : integer range 0 to 1 := 0;
rstdel : integer := 200;
scantest : integer := 0;
cke_rst : integer := 0;
pipe_ctrl : integer := 0
);
port (
ddr_rst : in std_ulogic;
ahb_rst : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in ddrctrl_in_type;
sdo : out ddrctrl_out_type;
hwidth : in std_ulogic
);
end component;
-- DDR2 controller with PHY
component ddr2spa
generic (
fabtech : integer := 0;
memtech : integer := 0;
rskew : integer := 0;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
MHz : integer := 100;
TRFC : integer := 130;
clkmul : integer := 2;
clkdiv : integer := 2;
col : integer := 9;
Mbyte : integer := 16;
rstdel : integer := 200;
pwron : integer := 0;
oepol : integer := 0;
ddrbits : integer := 16;
ahbfreq : integer := 50;
readdly : integer := 1;
ddelayb0 : integer := 0;
ddelayb1 : integer := 0;
ddelayb2 : integer := 0;
ddelayb3 : integer := 0;
ddelayb4 : integer := 0;
ddelayb5 : integer := 0;
ddelayb6 : integer := 0;
ddelayb7 : integer := 0;
cbdelayb0 : integer := 0;
cbdelayb1 : integer := 0;
cbdelayb2 : integer := 0;
cbdelayb3 : integer := 0;
numidelctrl : integer := 4;
norefclk : integer := 0;
odten : integer := 0;
octen : integer := 0;
dqsgating : integer := 0;
nosync : integer := 0;
eightbanks : integer := 0;
dqsse : integer range 0 to 1 := 0;
burstlen : integer range 4 to 128 := 8;
ahbbits : integer := ahbdw;
ft : integer range 0 to 1 := 0;
ftbits : integer := 0;
bigmem : integer range 0 to 1 := 0;
raspipe : integer range 0 to 1 := 0;
nclk : integer range 1 to 3 := 3;
scantest : integer := 0;
ncs : integer := 2;
cke_rst : integer := 0;
pipe_ctrl : integer := 0
);
port (
rst_ddr : in std_ulogic;
rst_ahb : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
clkref200 : in std_ulogic;
lock : out std_ulogic; -- DCM locked
clkddro : out std_ulogic; -- DCM locked
clkddri : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector ((ddrbits+ftbits)/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector ((ddrbits+ftbits)/8-1 downto 0); -- ddr dqs
ddr_dqsn : inout std_logic_vector ((ddrbits+ftbits)/8-1 downto 0); -- ddr dqsn
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (ddrbits+ftbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(1 downto 0);
ce : out std_logic;
oct_rdn : in std_logic := '0';
oct_rup : in std_logic := '0'
);
end component;
-- DDR2 PHY with just data or checkbits+data on same bus, including pads
component ddr2phy_wrap_cbd is
generic (
tech : integer := virtex2;
MHz : integer := 100;
rstdelay : integer := 200;
dbits : integer := 16;
padbits : integer := 0;
clk_mul : integer := 2 ;
clk_div : integer := 2;
ddelayb0 : integer := 0;
ddelayb1 : integer := 0;
ddelayb2 : integer := 0;
ddelayb3 : integer := 0;
ddelayb4 : integer := 0;
ddelayb5 : integer := 0;
ddelayb6 : integer := 0;
ddelayb7 : integer := 0;
cbdelayb0 : integer := 0;
cbdelayb1 : integer := 0;
cbdelayb2 : integer := 0;
cbdelayb3 : integer := 0;
numidelctrl : integer := 4;
norefclk : integer := 0;
odten : integer := 0;
rskew : integer := 0;
eightbanks : integer range 0 to 1 := 0;
dqsse : integer range 0 to 1 := 0;
abits : integer := 14;
nclk : integer := 3;
ncs : integer := 2;
chkbits : integer := 0;
ctrl2en : integer := 0;
resync : integer := 0;
custombits : integer := 8;
extraio : integer := 0;
scantest : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkref200 : in std_logic; -- input 200MHz clock
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic; -- system clock returned
clkresync : in std_ulogic;
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (extraio+(dbits+padbits+chkbits)/8-1 downto 0);-- ddr dqs
ddr_dqsn : inout std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits+padbits+chkbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(ncs-1 downto 0);
ddr_web2 : out std_ulogic; -- ddr write enable
ddr_rasb2 : out std_ulogic; -- ddr ras
ddr_casb2 : out std_ulogic; -- ddr cas
ddr_ad2 : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba2 : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
sdi : out ddrctrl_in_type;
sdo : in ddrctrl_out_type;
customclk : in std_ulogic;
customdin : in std_logic_vector(custombits-1 downto 0);
customdout : out std_logic_vector(custombits-1 downto 0);
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic;
oct_rdn : in std_logic := '0';
oct_rup : in std_logic := '0'
);
end component;
-- DDR2 PHY with just data or checkbits+data on same bus, not including pads
component ddr2phy_wrap_cbd_wo_pads is
generic (
tech : integer := virtex2;
MHz : integer := 100;
rstdelay : integer := 200;
dbits : integer := 16;
padbits : integer := 0;
clk_mul : integer := 2 ;
clk_div : integer := 2;
ddelayb0 : integer := 0;
ddelayb1 : integer := 0;
ddelayb2 : integer := 0;
ddelayb3 : integer := 0;
ddelayb4 : integer := 0;
ddelayb5 : integer := 0;
ddelayb6 : integer := 0;
ddelayb7 : integer := 0;
cbdelayb0 : integer := 0;
cbdelayb1: integer := 0;
cbdelayb2: integer := 0;
cbdelayb3 : integer := 0;
numidelctrl : integer := 4;
norefclk : integer := 0;
odten : integer := 0;
rskew : integer := 0;
eightbanks : integer range 0 to 1 := 0;
dqsse : integer range 0 to 1 := 0;
abits : integer := 14;
nclk : integer := 3;
ncs : integer := 2;
chkbits : integer := 0;
resync : integer := 0;
custombits : integer := 8;
scantest : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkref200 : in std_logic; -- input 200MHz clock
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic; -- system clock return
clkresync : in std_ulogic;
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dm
ddr_dqs_in : in std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs
ddr_dqs_out : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs
ddr_dqs_oen : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq_in : in std_logic_vector (dbits+padbits+chkbits-1 downto 0); -- ddr data
ddr_dq_out : out std_logic_vector (dbits+padbits+chkbits-1 downto 0); -- ddr data
ddr_dq_oen : out std_logic_vector (dbits+padbits+chkbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(ncs-1 downto 0);
sdi : out ddrctrl_in_type;
sdo : in ddrctrl_out_type;
customclk : in std_ulogic;
customdin : in std_logic_vector(custombits-1 downto 0);
customdout : out std_logic_vector(custombits-1 downto 0);
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic
);
end component;
-- DDR2 PHY with separate checkbit and data buses, including pads
component ddr2phy_wrap
generic (
tech : integer := virtex2;
MHz : integer := 100;
rstdelay : integer := 200;
dbits : integer := 16;
padbits : integer := 0;
clk_mul : integer := 2;
clk_div : integer := 2;
ddelayb0 : integer := 0;
ddelayb1 : integer := 0;
ddelayb2 : integer := 0;
ddelayb3 : integer := 0;
ddelayb4 : integer := 0;
ddelayb5 : integer := 0;
ddelayb6 : integer := 0;
ddelayb7 : integer := 0;
cbdelayb0 : integer := 0;
cbdelayb1 : integer := 0;
cbdelayb2 : integer := 0;
cbdelayb3 : integer := 0;
numidelctrl : integer := 4;
norefclk : integer := 0;
rskew : integer := 0;
eightbanks : integer range 0 to 1 := 0;
dqsse : integer range 0 to 1 := 0;
abits : integer := 14;
nclk : integer := 3;
ncs : integer := 2;
cben : integer := 0;
chkbits : integer := 8;
ctrl2en : integer := 0;
resync : integer := 0;
custombits : integer := 8;
scantest : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkref200 : in std_logic; -- input 200MHz clock
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic; -- system clock returned
clkresync : in std_ulogic;
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector ((dbits+padbits)/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector ((dbits+padbits)/8-1 downto 0); -- ddr dqs
ddr_dqsn : inout std_logic_vector ((dbits+padbits)/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits+padbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(ncs-1 downto 0);
ddr_cbdm : out std_logic_vector(chkbits/8-1 downto 0);
ddr_cbdqs : inout std_logic_vector(chkbits/8-1 downto 0);
ddr_cbdqsn : inout std_logic_vector(chkbits/8-1 downto 0);
ddr_cbdq : inout std_logic_vector(chkbits-1 downto 0);
ddr_web2 : out std_ulogic; -- ddr write enable
ddr_rasb2 : out std_ulogic; -- ddr ras
ddr_casb2 : out std_ulogic; -- ddr cas
ddr_ad2 : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba2 : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
sdi : out ddrctrl_in_type;
sdo : in ddrctrl_out_type;
customclk : in std_ulogic;
customdin : in std_logic_vector(custombits-1 downto 0);
customdout : out std_logic_vector(custombits-1 downto 0);
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic
);
end component;
-----------------------------------------------------------------------------
-- DDRSPA types and components
-----------------------------------------------------------------------------
-- DDR/LPDDR controller, without PHY
component ddr1spax is
generic (
memtech : integer := 0;
phytech : integer := 0;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
ddrbits : integer := 32;
burstlen : integer := 8;
MHz : integer := 100;
col : integer := 9;
Mbyte : integer := 8;
pwron : integer := 0;
oepol : integer := 0;
nosync : integer := 0;
ddr_syncrst: integer range 0 to 1 := 0;
ahbbits : integer := ahbdw;
mobile : integer := 0;
confapi : integer := 0;
conf0 : integer := 0;
conf1 : integer := 0;
regoutput : integer := 0;
ft : integer := 0;
ddr400 : integer := 1;
rstdel : integer := 200;
scantest : integer := 0
);
port (
ddr_rst : in std_ulogic;
ahb_rst : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in ddrctrl_in_type;
sdo : out ddrctrl_out_type
);
end component;
-- DDR/LPDDR controller with PHY
component ddrspa
generic (
fabtech : integer := 0;
memtech : integer := 0;
rskew : integer := 0;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
MHz : integer := 100;
clkmul : integer := 2;
clkdiv : integer := 2;
col : integer := 9;
Mbyte : integer := 16;
rstdel : integer := 200;
pwron : integer := 0;
oepol : integer := 0;
ddrbits : integer := 16;
ahbfreq : integer := 50;
mobile : integer := 0;
confapi : integer := 0;
conf0 : integer := 0;
conf1 : integer := 0;
regoutput : integer range 0 to 1 := 0;
ddr400 : integer := 1;
scantest : integer := 0;
phyiconf : integer := 0
);
port (
rst_ddr : in std_ulogic;
rst_ahb : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
lock : out std_ulogic; -- DCM locked
clkddro : out std_ulogic; -- DCM locked
clkddri : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (ddrbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (ddrbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (ddrbits-1 downto 0) -- ddr data
);
end component;
-- DDR/LPDDR PHY, including pads
component ddrphy_wrap
generic (
tech : integer := virtex2;
MHz : integer := 100;
rstdelay : integer := 200;
dbits : integer := 16;
clk_mul : integer := 2;
clk_div : integer := 2;
rskew : integer := 0;
mobile : integer := 0;
scantest : integer := 0;
phyiconf : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic;
clkread : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0);-- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
sdi : out ddrctrl_in_type;
sdo : in ddrctrl_out_type;
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic);
end component;
-- DDR/LPDDR PHY with data and checkbits on same bus, including pads
component ddrphy_wrap_cbd is
generic (
tech : integer := virtex2;
MHz : integer := 100;
rstdelay : integer := 200;
dbits : integer := 16;
chkbits : integer := 0;
padbits : integer := 0;
clk_mul : integer := 2;
clk_div : integer := 2;
rskew : integer := 0;
mobile : integer := 0;
abits : integer := 14;
nclk : integer := 3;
ncs : integer := 2;
scantest : integer := 0;
phyiconf : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic; -- system clock return
clkread : out std_ulogic;
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits+padbits+chkbits-1 downto 0); -- ddr data
sdi : out ddrctrl_in_type;
sdo : in ddrctrl_out_type;
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic
);
end component;
-- DDR/LPDDR PHY with data and checkbits on same bus, without pads
component ddrphy_wrap_cbd_wo_pads is
generic (
tech : integer := virtex2;
MHz : integer := 100;
rstdelay : integer := 200;
dbits : integer := 16;
padbits : integer := 0;
clk_mul : integer := 2;
clk_div : integer := 2;
rskew : integer := 0;
mobile : integer := 0;
abits : integer := 14;
nclk : integer := 3;
ncs : integer := 2;
chkbits : integer := 0;
scantest : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic; -- system clock return
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dm
ddr_dqs_in : in std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs
ddr_dqs_out : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs
ddr_dqs_oen : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq_in : in std_logic_vector (dbits+padbits+chkbits-1 downto 0); -- ddr data
ddr_dq_out : out std_logic_vector (dbits+padbits+chkbits-1 downto 0); -- ddr data
ddr_dq_oen : out std_logic_vector (dbits+padbits+chkbits-1 downto 0); -- ddr data
sdi : out ddrctrl_in_type;
sdo : in ddrctrl_out_type;
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic
);
end component;
component lpddr2phy_wrap_cbd_wo_pads is
generic (
tech : integer := virtex2;
dbits : integer := 16;
nclk : integer := 3;
ncs : integer := 2;
chkbits : integer := 0;
padbits : integer := 0;
scantest : integer := 0);
port (
rst : in std_ulogic;
clkin : in std_ulogic; -- input clock
clkin2 : in std_ulogic; -- input clock
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic; -- system clock return
clkout2 : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_ca : out std_logic_vector(9 downto 0); -- ddr cmd/addr
ddr_dm : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dm
ddr_dqs_in : in std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs
ddr_dqs_out : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs
ddr_dqs_oen : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs
ddr_dq_in : in std_logic_vector (dbits+padbits+chkbits-1 downto 0); -- ddr data
ddr_dq_out : out std_logic_vector (dbits+padbits+chkbits-1 downto 0); -- ddr data
ddr_dq_oen : out std_logic_vector (dbits+padbits+chkbits-1 downto 0);
sdi : out ddrctrl_in_type;
sdo : in ddrctrl_out_type;
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic);
end component;
-----------------------------------------------------------------------------
-- Other components using DDRxSPA sub-components
-----------------------------------------------------------------------------
type ddravl_slv_in_type is record
burstbegin : std_ulogic;
addr : std_logic_vector(31 downto 0);
wdata : std_logic_vector(256 downto 0);
be : std_logic_vector(32 downto 0);
read_req : std_ulogic;
write_req : std_ulogic;
size : std_logic_vector(3 downto 0);
end record;
type ddravl_slv_out_type is record
ready : std_ulogic;
rdata_valid : std_ulogic;
rdata : std_logic_vector(256 downto 0);
end record;
constant ddravl_slv_in_none: ddravl_slv_in_type :=
('0',(others => '0'),(others => '0'),(others => '0'),'0','0',(others => '0'));
component ahb2avl_async is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
burstlen : integer := 8;
nosync : integer := 0;
ahbbits : integer := ahbdw;
avldbits : integer := 32;
avlabits : integer := 20
);
port (
rst_ahb : in std_ulogic;
clk_ahb : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
rst_avl : in std_ulogic;
clk_avl : in std_ulogic;
avlsi : out ddravl_slv_in_type;
avlso : in ddravl_slv_out_type
);
end component;
-----------------------------------------------------------------------------
-- MIG wrappers / bridges
-----------------------------------------------------------------------------
component ahb2mig_7series_ddr2_dq16_ad13_ba3
generic(
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
SIM_BYPASS_INIT_CAL : string := "OFF";
SIMULATION : string := "FALSE";
USE_MIG_INTERFACE_MODEL : boolean := false);
port(
ddr2_dq : inout std_logic_vector(15 downto 0);
ddr2_dqs_p : inout std_logic_vector(1 downto 0);
ddr2_dqs_n : inout std_logic_vector(1 downto 0);
ddr2_addr : out std_logic_vector(12 downto 0);
ddr2_ba : out std_logic_vector(2 downto 0);
ddr2_ras_n : out std_logic;
ddr2_cas_n : out std_logic;
ddr2_we_n : out std_logic;
ddr2_reset_n : out std_logic;
ddr2_ck_p : out std_logic_vector(0 downto 0);
ddr2_ck_n : out std_logic_vector(0 downto 0);
ddr2_cke : out std_logic_vector(0 downto 0);
ddr2_cs_n : out std_logic_vector(0 downto 0);
ddr2_dm : out std_logic_vector(1 downto 0);
ddr2_odt : out std_logic_vector(0 downto 0);
ahbso : out ahb_slv_out_type;
ahbsi : in ahb_slv_in_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
calib_done : out std_logic;
rst_n_syn : in std_logic;
rst_n_async : in std_logic;
clk_amba : in std_logic;
sys_clk_i : in std_logic;
clk_ref_i : in std_logic;
ui_clk : out std_logic;
ui_clk_sync_rst : out std_logic);
end component ;
component ahb2mig_7series_ddr3_dq16_ad15_ba3
generic(
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
maxwriteburst : integer := 8;
maxreadburst : integer := 8;
SIM_BYPASS_INIT_CAL : string := "OFF";
SIMULATION : string := "FALSE";
USE_MIG_INTERFACE_MODEL : boolean := false
);
port(
ddr3_dq : inout std_logic_vector(15 downto 0);
ddr3_dqs_p : inout std_logic_vector(1 downto 0);
ddr3_dqs_n : inout std_logic_vector(1 downto 0);
ddr3_addr : out std_logic_vector(14 downto 0);
ddr3_ba : out std_logic_vector(2 downto 0);
ddr3_ras_n : out std_logic;
ddr3_cas_n : out std_logic;
ddr3_we_n : out std_logic;
ddr3_reset_n : out std_logic;
ddr3_ck_p : out std_logic_vector(0 downto 0);
ddr3_ck_n : out std_logic_vector(0 downto 0);
ddr3_cke : out std_logic_vector(0 downto 0);
ddr3_dm : out std_logic_vector(1 downto 0);
ddr3_odt : out std_logic_vector(0 downto 0);
ahbso : out ahb_slv_out_type;
ahbsi : in ahb_slv_in_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
calib_done : out std_logic;
rst_n_syn : in std_logic;
rst_n_async : in std_logic;
clk_amba : in std_logic;
sys_clk_i : in std_logic;
-- clk_ref_i : in std_logic;
ui_clk : out std_logic;
ui_clk_sync_rst : out std_logic
);
end component ;
end package;
| gpl-3.0 | c247b0b4b7208eef95ddb54c697c11ad | 0.491941 | 3.756527 | false | false | false | false |
firecake/IRIS | FPGA/VHDL/vhdl/IRIS_Pack.vhd | 1 | 2,756 | --
-- Package File Template
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions
--
-- To use any of the example code shown below, uncomment the lines and modify as necessary
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package IRIS_Pack is
attribute box_type : string;
constant NB_PIXELS : integer := 3694;
component RAM
port(
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
clkb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
end component;
attribute box_type of RAM : COMPONENT IS "black_box";
component Clk_Manager
port(
CLKIN_IN : IN std_logic;
CLKIN_IBUFG_OUT : OUT std_logic;
CLK0_OUT : OUT std_logic;
LOCKED_OUT : OUT std_logic
);
end component;
component ItoA
Port ( I : in STD_LOGIC_VECTOR (7 downto 0);
A : out STD_LOGIC_VECTOR (31 downto 0);
l : out integer);
end component;
procedure FT_Send_Byte ( signal Data : in std_logic_vector(7 downto 0);
signal FSCLK : in std_logic;
signal FSDO : out std_logic );
procedure FT_Read_Byte ( signal Data : out std_logic_vector(7 downto 0);
signal Rdy : out std_logic;
signal FSCLK : in std_logic;
signal FSDI : in std_logic );
end IRIS_Pack;
package body IRIS_Pack is
procedure FT_Send_Byte ( signal Data : in std_logic_vector(7 downto 0);
signal FSCLK : in std_logic;
signal FSDO : out std_logic ) is
variable iData : std_logic_vector(10 downto 0);
begin
iData := '0' & Data & '0' & '1';
for i in 10 downto 0 loop
wait until FSCLK='0' and FSCLK'event;
FSDO <= iData(i);
end loop ;
end FT_Send_Byte ;
procedure FT_Read_Byte ( signal Data : out std_logic_vector(7 downto 0);
signal Rdy : out std_logic;
signal FSCLK : in std_logic;
signal FSDI : in std_logic ) is
variable iData : std_logic_vector(7 downto 0);
begin
Rdy <= '0';
while FSDI = '1' loop
wait until FSCLK='1' and FSCLK'event;
end loop;
Rdy <= '1';
for i in 7 downto 0 loop
wait until FSCLK='1' and FSCLK'event;
iData(i) := FSDI;
end loop ;
Rdy <= '0';
Data <= iData;
wait until FSCLK='1' and FSCLK'event;
wait until FSCLK='1' and FSCLK'event;
end FT_Read_Byte ;
end IRIS_Pack;
| gpl-3.0 | 42740b7894721c813978cd61ec812cb5 | 0.593251 | 3.138952 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-asic/spw_lvttl_pads.vhd | 1 | 4,478 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Copyright (C) 2009-2013, Aeroflex Gaisler AB
-------------------------------------------------------------------------------
-- Entity: spw_2x_lvttl_pads
-- File: spw_2x_lvttl_pads.vhd
-- Author: Marko Isomaki, Aeroflex Gaisler
-- Contact: [email protected]
-- Description: pads for SpW signals in router ASIC LVTTL ports
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.config.all;
library techmap;
use techmap.gencomp.all;
library grlib;
use grlib.stdlib.conv_std_logic;
entity spw_lvttl_pads is
generic (
padtech : integer := 0;
oepol : integer := 0;
level : integer := 0;
voltage : integer := 0;
filter : integer := 0;
strength : integer := 4;
slew : integer := 0;
input_type : integer := 0
);
port (
---------------------------------------------------------------------------
-- Signals going off-chip
---------------------------------------------------------------------------
spw_rxd : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_rxs : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txd : out std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txs : out std_logic_vector(0 to CFG_SPW_NUM-1);
---------------------------------------------------------------------------
-- Signals to core
---------------------------------------------------------------------------
lspw_rxd : out std_logic_vector(0 to CFG_SPW_NUM-1);
lspw_rxs : out std_logic_vector(0 to CFG_SPW_NUM-1);
lspw_txd : in std_logic_vector(0 to CFG_SPW_NUM-1);
lspw_txs : in std_logic_vector(0 to CFG_SPW_NUM-1)
);
end entity;
architecture rtl of spw_lvttl_pads is
begin
------------------------------------------------------------------------------
-- SpW port pads
------------------------------------------------------------------------------
spw_pads : for i in 0 to CFG_SPW_NUM-1 generate
spw_pad_input: if input_type <= 3 generate
spw_rxd_pad : inpad
generic map (
tech => padtech,
level => level,
voltage => voltage,
filter => filter,
strength => strength)
port map (
pad => spw_rxd(i),
o => lspw_rxd(i));
spw_rxs_pad : inpad
generic map (
tech => padtech,
level => level,
voltage => voltage,
filter => filter,
strength => strength)
port map (
pad => spw_rxs(i),
o => lspw_rxs(i));
end generate;
spw_no_pad_input: if input_type >= 4 generate
lspw_rxd(i) <= spw_rxd(i);
lspw_rxs(i) <= spw_rxs(i);
end generate;
spw_txd_pad : outpad
generic map (
tech => padtech,
level => level,
slew => slew,
voltage => voltage,
strength => strength)
port map (
pad => spw_txd(i),
i => lspw_txd(i));
spw_txs_pad : outpad
generic map (
tech => padtech,
level => level,
slew => slew,
voltage => voltage,
strength => strength)
port map (
pad => spw_txs(i),
i => lspw_txs(i));
end generate;
end;
| gpl-3.0 | 08bd947fb95c8d14edbdbe5dd6ca0032 | 0.473426 | 4.276982 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-xilinx-ml510/testbench.vhd | 1 | 19,632 | -----------------------------------------------------------------------------
-- LEON Demonstration design test bench
-- Copyright (C) 2008 - 2015 Cobham Gaisler AB
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library cypress;
use cypress.components.all;
use work.debug.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
transtech : integer := CFG_TRANSTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 10; -- system clock period
romwidth : integer := 32; -- rom data width (8/32)
romdepth : integer := 16 -- rom address depth
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal sys_clk : std_logic := '0';
signal sys_rst_in : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal clk_125_p : std_ulogic := '0';
signal clk_125_n : std_ulogic := '1';
constant slips : integer := 11;
signal rst_125 : std_ulogic;
signal sysace_fpga_clk : std_ulogic := '0';
signal flash_we_b : std_ulogic;
signal flash_wait : std_ulogic;
signal flash_reset_b : std_ulogic;
signal flash_oe_b : std_ulogic;
signal flash_d : std_logic_vector(15 downto 0);
signal flash_clk : std_ulogic;
signal flash_ce_b : std_ulogic;
signal flash_adv_b : std_logic;
signal flash_a : std_logic_vector(21 downto 0);
signal sram_bw : std_ulogic;
signal sim_d : std_logic_vector(15 downto 0);
signal iosn : std_ulogic;
signal dimm1_ddr2_we_b : std_ulogic;
signal dimm1_ddr2_s_b : std_logic_vector(1 downto 0);
signal dimm1_ddr2_ras_b : std_ulogic;
signal dimm1_ddr2_pll_clkin_p : std_ulogic;
signal dimm1_ddr2_pll_clkin_n : std_ulogic;
signal dimm1_ddr2_odt : std_logic_vector(1 downto 0);
signal dimm1_ddr2_dqs_p : std_logic_vector(8 downto 0);
signal dimm1_ddr2_dqs_n : std_logic_vector(8 downto 0);
signal dimm1_ddr2_dqm : std_logic_vector(8 downto 0);
signal dimm1_ddr2_dq : std_logic_vector(71 downto 0);
signal dimm1_ddr2_dq2 : std_logic_vector(71 downto 0);
signal dimm1_ddr2_cke : std_logic_vector(1 downto 0);
signal dimm1_ddr2_cas_b : std_ulogic;
signal dimm1_ddr2_ba : std_logic_vector(2 downto 0);
signal dimm1_ddr2_a : std_logic_vector(13 downto 0);
signal dimm0_ddr2_we_b : std_ulogic;
signal dimm0_ddr2_s_b : std_logic_vector(1 downto 0);
signal dimm0_ddr2_ras_b : std_ulogic;
signal dimm0_ddr2_pll_clkin_p : std_ulogic;
signal dimm0_ddr2_pll_clkin_n : std_ulogic;
signal dimm0_ddr2_odt : std_logic_vector(1 downto 0);
signal dimm0_ddr2_dqs_p : std_logic_vector(8 downto 0);
signal dimm0_ddr2_dqs_n : std_logic_vector(8 downto 0);
signal dimm0_ddr2_dqm : std_logic_vector(8 downto 0);
signal dimm0_ddr2_dq : std_logic_vector(71 downto 0);
signal dimm0_ddr2_dq2 : std_logic_vector(71 downto 0);
signal dimm0_ddr2_cke : std_logic_vector(1 downto 0);
signal dimm0_ddr2_cas_b : std_ulogic;
signal dimm0_ddr2_ba : std_logic_vector(2 downto 0);
signal dimm0_ddr2_a : std_logic_vector(13 downto 0);
signal phy0_txer : std_ulogic;
signal phy0_txd : std_logic_vector(3 downto 0);
signal phy0_txctl_txen : std_ulogic;
signal phy0_txclk : std_ulogic;
signal phy0_rxer : std_ulogic;
signal phy0_rxd : std_logic_vector(3 downto 0);
signal phy0_rxctl_rxdv : std_ulogic;
signal phy0_rxclk : std_ulogic;
signal phy0_reset : std_ulogic;
signal phy0_mdio : std_logic;
signal phy0_mdc : std_ulogic;
signal phy1_reset : std_logic;
signal phy1_mdio : std_logic;
signal phy1_mdc : std_logic;
signal phy1_sgmii_tx_p : std_logic;
signal phy1_sgmii_tx_n : std_logic;
signal phy1_sgmii_rx_p : std_logic;
signal phy1_sgmii_rx_n : std_logic;
signal phy1_sgmii_rx_p_d : std_logic;
signal phy1_sgmii_rx_n_d : std_logic;
signal sysace_mpa : std_logic_vector(6 downto 0);
signal sysace_mpce : std_ulogic;
signal sysace_mpirq : std_ulogic;
signal sysace_mpoe : std_ulogic;
signal sysace_mpwe : std_ulogic;
signal sysace_mpd : std_logic_vector(15 downto 0);
signal dbg_led : std_logic_vector(3 downto 0);
signal opb_bus_error : std_ulogic;
signal plb_bus_error : std_ulogic;
signal dvi_xclk_p : std_ulogic;
signal dvi_xclk_n : std_ulogic;
signal dvi_v : std_ulogic;
signal dvi_reset_b : std_ulogic;
signal dvi_h : std_ulogic;
signal dvi_gpio1 : std_logic;
signal dvi_de : std_ulogic;
signal dvi_d : std_logic_vector(11 downto 0);
signal pci_p_trdy_b : std_logic;
signal pci_p_stop_b : std_logic;
signal pci_p_serr_b : std_logic;
signal pci_p_rst_b : std_logic;
signal pci_p_req_b : std_logic_vector(0 to 4);
signal pci_p_perr_b : std_logic;
signal pci_p_par : std_logic;
signal pci_p_lock_b : std_logic;
signal pci_p_irdy_b : std_logic;
signal pci_p_intd_b : std_logic;
signal pci_p_intc_b : std_logic;
signal pci_p_intb_b : std_logic;
signal pci_p_inta_b : std_logic;
signal pci_p_gnt_b : std_logic_vector(0 to 4);
signal pci_p_frame_b : std_logic;
signal pci_p_devsel_b : std_logic;
signal pci_p_clk5_r : std_ulogic;
signal pci_p_clk5 : std_ulogic;
signal pci_p_clk4_r : std_ulogic;
signal pci_p_clk3_r : std_ulogic;
signal pci_p_clk1_r : std_ulogic;
signal pci_p_clk0_r : std_ulogic;
signal pci_p_cbe_b : std_logic_vector(3 downto 0);
signal pci_p_ad : std_logic_vector(31 downto 0);
--signal pci_fpga_idsel : std_ulogic;
signal sbr_pwg_rsm_rstj : std_logic;
signal sbr_nmi_r : std_ulogic;
signal sbr_intr_r : std_ulogic;
signal sbr_ide_rst_b : std_logic;
signal iic_sda_dvi : std_logic;
signal iic_scl_dvi : std_logic;
signal fpga_sda : std_logic;
signal fpga_scl : std_logic;
signal iic_therm_b : std_ulogic;
signal iic_reset_b : std_ulogic;
signal iic_irq_b : std_ulogic;
signal iic_alert_b : std_ulogic;
signal spi_data_out : std_logic;
signal spi_data_in : std_logic;
signal spi_data_cs_b : std_ulogic;
signal spi_clk : std_ulogic;
signal uart1_txd : std_ulogic;
signal uart1_rxd : std_ulogic;
signal uart1_rts_b : std_ulogic;
signal uart1_cts_b : std_ulogic;
signal uart0_txd : std_ulogic;
signal uart0_rxd : std_ulogic;
signal uart0_rts_b : std_ulogic;
--signal uart0_cts_b : std_ulogic;
--signal test_mon_vrefp : std_ulogic;
signal test_mon_vp0_p : std_ulogic;
signal test_mon_vn0_n : std_ulogic;
--signal test_mon_avdd : std_ulogic;
signal data : std_logic_vector(31 downto 0);
signal phy0_rxdl : std_logic_vector(7 downto 0);
signal phy0_txdl : std_logic_vector(7 downto 0);
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
constant lresp : boolean := false;
begin
-- clock and reset
sys_clk <= not sys_clk after ct * 1 ns;
sys_rst_in <= '0', '1' after 200 ns;
sysace_fpga_clk <= not sysace_fpga_clk after 15 ns;
pci_p_clk5 <= pci_p_clk5_r;
clk_125_p <= not clk_125_p after 4 ns;
clk_125_n <= not clk_125_n after 4 ns;
flash_wait <= 'L';
phy0_txdl <= "0000" & phy0_txd; phy0_rxd <= phy0_rxdl(3 downto 0);
sysace_mpd <= (others => 'H'); sysace_mpirq <= 'L';
dbg_led <= (others => 'H');
dvi_gpio1 <= 'H';
pci_p_trdy_b <= 'H'; pci_p_stop_b <= 'H';
pci_p_serr_b <= 'H'; pci_p_rst_b <= 'H';
pci_p_req_b <= (others => 'H'); pci_p_perr_b <= 'H';
pci_p_par <= 'H'; pci_p_lock_b <= 'H';
pci_p_irdy_b <= 'H'; pci_p_intd_b <= 'H';
pci_p_intc_b <= 'H'; pci_p_intb_b <= 'H';
pci_p_inta_b <= 'H'; pci_p_gnt_b <= (others => 'H');
pci_p_frame_b <= 'H'; pci_p_devsel_b <= 'H';
pci_p_cbe_b <= (others => 'H'); pci_p_ad <= (others => 'H');
-- pci_fpga_idsel <= 'H';
sbr_pwg_rsm_rstj <= 'H'; sbr_nmi_r <= 'H';
sbr_intr_r <= 'L'; sbr_ide_rst_b <= 'H';
iic_sda_dvi <= 'H'; iic_scl_dvi <= 'H';
fpga_sda <= 'H'; fpga_scl <= 'H';
iic_therm_b <= 'L'; iic_irq_b <= 'L'; iic_alert_b <= 'L';
spi_data_out <= 'H';
uart1_rxd <= 'H'; uart1_cts_b <= uart1_rts_b;
uart0_rxd <= 'H'; --uart0_cts_b <= uart0_rts_b;
test_mon_vp0_p <= 'H'; test_mon_vn0_n <= 'H';
cpu : entity work.leon3mp
generic map ( fabtech, memtech, padtech, transtech, ncpu, disas, dbguart, pclow )
port map (sys_rst_in, sys_clk, sysace_fpga_clk,
-- Flash
flash_we_b, flash_wait, flash_reset_b, flash_oe_b,
flash_d, flash_clk, flash_ce_b, flash_adv_b, flash_a,
sram_bw, sim_d, iosn,
-- DDR2 slot 1
dimm1_ddr2_we_b, dimm1_ddr2_s_b, dimm1_ddr2_ras_b,
dimm1_ddr2_pll_clkin_p, dimm1_ddr2_pll_clkin_n,
dimm1_ddr2_odt, dimm1_ddr2_dqs_p, dimm1_ddr2_dqs_n,
dimm1_ddr2_dqm, dimm1_ddr2_dq, dimm1_ddr2_cke,
dimm1_ddr2_cas_b, dimm1_ddr2_ba, dimm1_ddr2_a,
-- DDR2 slot 0
dimm0_ddr2_we_b, dimm0_ddr2_s_b, dimm0_ddr2_ras_b,
dimm0_ddr2_pll_clkin_p, dimm0_ddr2_pll_clkin_n,
dimm0_ddr2_odt, dimm0_ddr2_dqs_p, dimm0_ddr2_dqs_n,
dimm0_ddr2_dqm, dimm0_ddr2_dq, dimm0_ddr2_cke,
dimm0_ddr2_cas_b, dimm0_ddr2_ba, dimm0_ddr2_a,
open,
-- Ethernet PHY0
phy0_txer, phy0_txd, phy0_txctl_txen, phy0_txclk,
phy0_rxer, phy0_rxd, phy0_rxctl_rxdv, phy0_rxclk,
phy0_reset, phy0_mdio, phy0_mdc,
-- Ethernet PHY1
clk_125_p, clk_125_n,
phy1_reset, phy1_mdio, phy1_mdc, open,
phy1_sgmii_tx_p, phy1_sgmii_tx_n, phy1_sgmii_rx_p, phy1_sgmii_rx_n,
-- System ACE MPU
sysace_mpa, sysace_mpce, sysace_mpirq, sysace_mpoe,
sysace_mpwe, sysace_mpd,
-- GPIO/Green LEDs
dbg_led,
-- Red/Green LEDs
opb_bus_error, plb_bus_error,
-- LCD
-- fpga_lcd_rw, fpga_lcd_rs, fpga_lcd_e, fpga_lcd_db,
-- DVI
dvi_xclk_p, dvi_xclk_n, dvi_v, dvi_reset_b, dvi_h,
dvi_gpio1, dvi_de, dvi_d,
-- PCI
pci_p_trdy_b, pci_p_stop_b, pci_p_serr_b, pci_p_rst_b,
pci_p_req_b, pci_p_perr_b, pci_p_par, pci_p_lock_b,
pci_p_irdy_b, pci_p_intd_b, pci_p_intc_b, pci_p_intb_b,
pci_p_inta_b, pci_p_gnt_b, pci_p_frame_b, pci_p_devsel_b,
pci_p_clk5_r, pci_p_clk5, pci_p_clk4_r, pci_p_clk3_r,
pci_p_clk1_r, pci_p_clk0_r, pci_p_cbe_b, pci_p_ad,
-- pci_fpga_idsel,
sbr_pwg_rsm_rstj, sbr_nmi_r, sbr_intr_r, sbr_ide_rst_b,
-- IIC/SMBus and sideband signals
iic_sda_dvi, iic_scl_dvi, fpga_sda, fpga_scl, iic_therm_b,
iic_reset_b, iic_irq_b, iic_alert_b,
-- SPI
spi_data_out, spi_data_in, spi_data_cs_b, spi_clk,
-- UARTs
uart1_txd, uart1_rxd, uart1_rts_b, uart1_cts_b,
uart0_txd, uart0_rxd, uart0_rts_b--, --uart0_cts_b
-- System monitor
-- test_mon_vp0_p, test_mon_vn0_n
);
-- ddr2mem0: for i in 0 to (1 + 2*(CFG_DDR2SP_DATAWIDTH/64)) generate
-- u1 : HY5PS121621F
-- generic map (TimingCheckFlag => true, PUSCheckFlag => false,
-- index => (1 + 2*(CFG_DDR2SP_DATAWIDTH/64))-i, bbits => CFG_DDR2SP_DATAWIDTH,
-- fname => sdramfile, fdelay => 0)
-- port map (DQ => dimm0_ddr2_dq2(i*16+15+32*(32/CFG_DDR2SP_DATAWIDTH) downto i*16+32*(32/CFG_DDR2SP_DATAWIDTH)),
-- LDQS => dimm0_ddr2_dqs_p(i*2+4*(32/CFG_DDR2SP_DATAWIDTH)),
-- LDQSB => dimm0_ddr2_dqs_n(i*2+4*(32/CFG_DDR2SP_DATAWIDTH)),
-- UDQS => dimm0_ddr2_dqs_p(i*2+1+4*(32/CFG_DDR2SP_DATAWIDTH)),
-- UDQSB => dimm0_ddr2_dqs_n(i*2+1+4*(32/CFG_DDR2SP_DATAWIDTH)),
-- LDM => dimm0_ddr2_dqm(i*2+4*(32/CFG_DDR2SP_DATAWIDTH)),
-- WEB => dimm0_ddr2_we_b, CASB => dimm0_ddr2_cas_b,
-- RASB => dimm0_ddr2_ras_b, CSB => dimm0_ddr2_s_b(0),
-- BA => dimm0_ddr2_ba(1 downto 0), ADDR => dimm0_ddr2_a(12 downto 0),
-- CKE => dimm0_ddr2_cke(0), CLK => dimm0_ddr2_pll_clkin_p,
-- CLKB => dimm0_ddr2_pll_clkin_n,
-- UDM => dimm0_ddr2_dqm(i*2+1+4*(32/CFG_DDR2SP_DATAWIDTH)));
-- end generate;
ddr2mem0 : ddr2ram
generic map(width => CFG_DDR2SP_DATAWIDTH, abits => 14, babits => 3, colbits => 10, rowbits => 13,
implbanks => 1, fname => sdramfile, speedbin=>1, density => 2)
port map (ck => dimm0_ddr2_pll_clkin_p, ckn => dimm0_ddr2_pll_clkin_n,
cke => dimm0_ddr2_cke(0), csn => dimm0_ddr2_s_b(0),
odt => gnd, rasn => dimm0_ddr2_ras_b,
casn => dimm0_ddr2_cas_b, wen => dimm0_ddr2_we_b,
dm => dimm0_ddr2_dqm(7 downto 8-CFG_DDR2SP_DATAWIDTH/8), ba => dimm0_ddr2_ba,
a => dimm0_ddr2_a, dq => dimm0_ddr2_dq2(63 downto 64-CFG_DDR2SP_DATAWIDTH),
dqs => dimm0_ddr2_dqs_p(7 downto 8-CFG_DDR2SP_DATAWIDTH/8),
dqsn =>dimm0_ddr2_dqs_n(7 downto 8-CFG_DDR2SP_DATAWIDTH/8));
-- ddr2mem1: for i in 0 to (1 + 2*(CFG_DDR2SP_DATAWIDTH/64)) generate
-- u1 : HY5PS121621F
-- generic map (TimingCheckFlag => true, PUSCheckFlag => false,
-- index => (1 + 2*(CFG_DDR2SP_DATAWIDTH/64))-i, bbits => CFG_DDR2SP_DATAWIDTH,
-- fname => sdramfile, fdelay => 0)
-- port map (DQ => dimm1_ddr2_dq2(i*16+15+32*(32/CFG_DDR2SP_DATAWIDTH) downto i*16+32*(32/CFG_DDR2SP_DATAWIDTH)),
-- LDQS => dimm1_ddr2_dqs_p(i*2+4*(32/CFG_DDR2SP_DATAWIDTH)),
-- LDQSB => dimm1_ddr2_dqs_n(i*2+4*(32/CFG_DDR2SP_DATAWIDTH)),
-- UDQS => dimm1_ddr2_dqs_p(i*2+1+4*(32/CFG_DDR2SP_DATAWIDTH)),
-- UDQSB => dimm1_ddr2_dqs_n(i*2+1+4*(32/CFG_DDR2SP_DATAWIDTH)),
-- LDM => dimm1_ddr2_dqm(i*2+4*(32/CFG_DDR2SP_DATAWIDTH)),
-- WEB => dimm1_ddr2_we_b, CASB => dimm1_ddr2_cas_b,
-- RASB => dimm1_ddr2_ras_b, CSB => dimm1_ddr2_s_b(0),
-- BA => dimm1_ddr2_ba(1 downto 0), ADDR => dimm1_ddr2_a(12 downto 0),
-- CKE => dimm1_ddr2_cke(0), CLK => dimm1_ddr2_pll_clkin_p,
-- CLKB => dimm1_ddr2_pll_clkin_n,
-- UDM => dimm1_ddr2_dqm(i*2+1+4*(32/CFG_DDR2SP_DATAWIDTH)));
-- end generate;
ddr2mem1 : ddr2ram
generic map(width => CFG_DDR2SP_DATAWIDTH, abits => 13, babits =>2, colbits => 10, rowbits => 13,
implbanks => 1, fname => sdramfile, speedbin=>1, density => 2)
port map (ck => dimm1_ddr2_pll_clkin_p, ckn => dimm1_ddr2_pll_clkin_n,
cke => dimm1_ddr2_cke(0), csn => dimm1_ddr2_s_b(0),
odt => gnd, rasn => dimm1_ddr2_ras_b,
casn => dimm1_ddr2_cas_b, wen => dimm1_ddr2_we_b,
dm => dimm1_ddr2_dqm(CFG_DDR2SP_DATAWIDTH/8-1 downto 0), ba => dimm1_ddr2_ba(1 downto 0),
a => dimm1_ddr2_a(12 downto 0), dq => dimm1_ddr2_dq2(CFG_DDR2SP_DATAWIDTH-1 downto 0),
dqs => dimm1_ddr2_dqs_p(CFG_DDR2SP_DATAWIDTH/8-1 downto 0),
dqsn =>dimm1_ddr2_dqs_n(CFG_DDR2SP_DATAWIDTH/8-1 downto 0));
ddr2delay0 : delay_wire
generic map(data_width => dimm0_ddr2_dq'length, delay_atob => 0.0, delay_btoa => 5.5)
port map(a => dimm0_ddr2_dq, b => dimm0_ddr2_dq2);
ddr2delay1 : delay_wire
generic map(data_width => dimm1_ddr2_dq'length, delay_atob => 0.0, delay_btoa => 5.5)
port map(a => dimm1_ddr2_dq, b => dimm1_ddr2_dq2);
prom0 : sram16 generic map (index => 4, abits => romdepth, fname => promfile)
port map (flash_a(romdepth-1 downto 0), flash_d(15 downto 0),
gnd, gnd, flash_ce_b, flash_we_b, flash_oe_b);
phy0_mdio <= 'H';
p0: phy
generic map (address => 7)
port map(phy0_reset, phy0_mdio, phy0_txclk, phy0_rxclk, phy0_rxdl,
phy0_rxctl_rxdv, phy0_rxer, open, open, phy0_txdl,
phy0_txctl_txen, phy0_txer, phy0_mdc, '0');
rst_125 <= not phy1_reset;
phy1_sgmii_rx_p <= transport phy1_sgmii_rx_p_d after 0.8 ns * slips;
phy1_sgmii_rx_n <= transport phy1_sgmii_rx_n_d after 0.8 ns * slips;
sp0: ser_phy
generic map(
address => 7,
extended_regs => 1,
aneg => 1,
fd_10 => 1,
hd_10 => 1,
base100_t4 => 1,
base100_x_fd => 1,
base100_x_hd => 1,
base100_t2_fd => 1,
base100_t2_hd => 1,
base1000_x_fd => 1,
base1000_x_hd => 1,
base1000_t_fd => 1,
base1000_t_hd => 1,
fabtech => CFG_FABTECH,
memtech => CFG_MEMTECH,
transtech => CFG_TRANSTECH
)
port map(
rstn => phy1_reset,
clk_125 => clk_125_p,
rst_125 => rst_125,
eth_rx_p => phy1_sgmii_rx_p_d,
eth_rx_n => phy1_sgmii_rx_n_d,
eth_tx_p => phy1_sgmii_tx_p,
eth_tx_n => phy1_sgmii_tx_n,
mdio => phy1_mdio,
mdc => phy1_mdc
);
i0: i2c_slave_model
port map (iic_scl_dvi, iic_sda_dvi);
i1: i2c_slave_model
port map (fpga_scl, fpga_sda);
iuerr : process
begin
wait for 5000 ns;
if to_x01(opb_bus_error) = '0' then wait on opb_bus_error; end if;
assert (to_x01(opb_bus_error) = '0')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
data <= flash_d & sim_d;
test0 : grtestmod
port map ( sys_rst_in, sys_clk, opb_bus_error, flash_a(20 downto 1), data,
iosn, flash_oe_b, sram_bw, open);
flash_d <= buskeep(flash_d), (others => 'H') after 250 ns;
data <= buskeep(data), (others => 'H') after 250 ns;
end ;
| gpl-3.0 | cd021edd7c4f4ff3e3fbda317cb18ffc | 0.574725 | 2.847281 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-altera-ep2s60-ddr/config.vhd | 1 | 5,851 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := stratix2;
constant CFG_MEMTECH : integer := stratix2;
constant CFG_PADTECH : integer := stratix2;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := stratix2;
constant CFG_CLKMUL : integer := (8);
constant CFG_CLKDIV : integer := (5);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 0;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 4;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 4;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0 + 1*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2 + 64*0;
constant CFG_ATBSZ : integer := 2;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_STAT_ENABLE : integer := 0;
constant CFG_STAT_CNT : integer := 1;
constant CFG_STAT_NMAX : integer := 0;
constant CFG_STAT_DSUEN : integer := 0;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
constant CFG_ALTWIN : integer := 0;
constant CFG_REX : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 0;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 1;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- DDR controller
constant CFG_DDRSP : integer := 1;
constant CFG_DDRSP_INIT : integer := 1;
constant CFG_DDRSP_FREQ : integer := (100);
constant CFG_DDRSP_COL : integer := (9);
constant CFG_DDRSP_SIZE : integer := (32);
constant CFG_DDRSP_RSKEW : integer := 0;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 8;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#FFFF#;
constant CFG_GRGPIO_WIDTH : integer := (32);
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-3.0 | 698b79f62f69a71d6ac10c61b2b80835 | 0.64348 | 3.634161 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-terasic-sockit/leon3mp.vhd | 1 | 66,521 | -----------------------------------------------------------------------------
-- LEON3 Terasic Sockit demonstration design
-- By Martin George
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.all;
--library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.jtag.all;
use gaisler.spi.all;
use gaisler.i2c.all;
use gaisler.net.all;
--pragma translate_off
use gaisler.sim.all;
--pragma translate_on
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
-- --DDR3--
DDR3_A : out std_logic_vector(14 downto 0);
DDR3_BA : out std_logic_vector(2 downto 0);
DDR3_CAS_n : out std_logic;
DDR3_CKE : out std_logic;
DDR_CK_n : out std_logic;
DDR3_CK_p : out std_logic;
DDR3_CS_n : out std_logic;
DDR3_DM : out std_logic_vector(3 downto 0);
DDR3_DQ : inout std_logic_vector(31 downto 0);
DDR3_DQS_n : inout std_logic_vector(3 downto 0);
DDR3_DQS_p : inout std_logic_vector(3 downto 0);
DDR3_ODT : out std_logic;
DDR3_RAS_n : out std_logic;
DDR3_RESET_n : out std_logic;
DDR3_RZQ : in std_logic;
DDR3_WE_n : out std_logic;
--
--
-- --FAN CONTROL--
-- FAN_CTRL : out std_logic;
--
--
---- --HPS--
HPS_CONV_USB_n : inout std_logic;
HPS_DDR3_A : out std_logic_vector(14 downto 0);
HPS_DDR3_BA : out std_logic_vector(2 downto 0);
HPS_DDR3_CAS_n : out std_logic;
HPS_DDR3_CKE : out std_logic;
HPS_DDR3_CK_n : out std_logic;
HPS_DDR3_CK_p : out std_logic;
HPS_DDR3_CS_n : out std_logic;
HPS_DDR3_DM : out std_logic_vector(3 downto 0);
HPS_DDR3_DQ : inout std_logic_vector(31 downto 0);
HPS_DDR3_DQS_n : inout std_logic_vector(3 downto 0);
HPS_DDR3_DQS_p : inout std_logic_vector(3 downto 0);
HPS_DDR3_ODT : out std_logic; --output HPS_DDR3_ODT,
HPS_DDR3_RAS_n : out std_logic; --output HPS_DDR3_RAS_n,
HPS_DDR3_RESET_n : out std_logic; --output HPS_DDR3_RESET_n,
HPS_DDR3_RZQ : in std_logic; --input HPS_DDR3_RZQ,
HPS_DDR3_WE_n : out std_logic; --output
HPS_ENET_GTX_CLK : out std_logic; --output HPS_ENET_GTX_CLK,
HPS_ENET_INT_n : inout std_logic; --inout HPS_ENET_INT_n,
HPS_ENET_MDC : out std_logic; --output HPS_ENET_MDC,
HPS_ENET_MDIO : inout std_logic; --inout HPS_ENET_MDIO,
HPS_ENET_RX_CLK : in std_logic; --input HPS_ENET_RX_CLK,
HPS_ENET_RX_DATA : in std_logic_vector(3 downto 0); --input [3:0] HPS_ENET_RX_DATA,
HPS_ENET_RX_DV : in std_logic; --input HPS_ENET_RX_DV,
HPS_ENET_TX_DATA : out std_logic_vector(3 downto 0); --output [3:0] HPS_ENET_TX_DATA,
HPS_ENET_TX_EN : out std_logic; --output HPS_ENET_TX_EN,
HPS_FLASH_DATA : inout std_logic_vector(3 downto 0); --inout [3:0] HPS_FLASH_DATA,
HPS_FLASH_DCLK : out std_logic; --output HPS_FLASH_DCLK,
HPS_FLASH_NCSO : out std_logic; --output HPS_FLASH_NCSO,
HPS_GSENSOR_INT : inout std_logic; --inout HPS_GSENSOR_INT,
HPS_I2C_CLK : inout std_logic; --inout HPS_I2C_CLK,
HPS_I2C_SDA : inout std_logic; --inout HPS_I2C_SDA,
-- HPS_KEY : inout std_logic_vector(3 downto 0); --inout [3:0] HPS_KEY,
HPS_LCM_BK : inout std_logic; --inout HPS_LCM_BK,
HPS_LCM_D_C : inout std_logic; --output HPS_LCM_D_C,
HPS_LCM_RST_N : inout std_logic; --output HPS_LCM_RST_N,
HPS_LCM_SPIM_CLK : out std_logic; --input HPS_LCM_SPIM_CLK,
HPS_LCM_SPIM_MOSI : out std_logic; --output HPS_LCM_SPIM_MOSI,
HPS_LCM_SPIM_SS : out std_logic; --output HPS_LCM_SPIM_SS,
HPS_LCM_SPIM_MISO : in std_logic;
HPS_LED : inout std_logic_vector(3 downto 0); --output [3:0] HPS_LED,
HPS_LTC_GPIO : inout std_logic; --inout HPS_LTC_GPIO,
HPS_SD_CLK : out std_logic; --output HPS_SD_CLK,
HPS_SD_CMD : inout std_logic; --inout HPS_SD_CMD,
HPS_SD_DATA : inout std_logic_vector(3 downto 0); --inout [3:0] HPS_SD_DATA,
HPS_SPIM_CLK : out std_logic; --output HPS_SPIM_CLK,
HPS_SPIM_MISO : in std_logic; --input HPS_SPIM_MISO,
HPS_SPIM_MOSI : out std_logic; --output HPS_SPIM_MOSI,
HPS_SPIM_SS : out std_logic; --output HPS_SPIM_SS,
-- HPS_SW : in std_logic_vector(3 downto 0); --input [3:0] HPS_SW,
HPS_UART_RX : in std_logic; --input HPS_UART_RX,
HPS_UART_TX : out std_logic; --output HPS_UART_TX,
HPS_USB_CLKOUT : in std_logic; --input HPS_USB_CLKOUT,
HPS_USB_DATA : inout std_logic_vector(7 downto 0); --inout [7:0] HPS_USB_DATA,
HPS_USB_DIR : in std_logic; --input HPS_USB_DIR,
HPS_USB_NXT : in std_logic; --input HPS_USB_NXT,
HPS_USB_STP : out std_logic; --output HPS_USB_STP,
--
-- --Audio--
-- AUD_ADCDAT : in std_logic; --input AUD_ADCDAT,
-- AUD_ADCLRCK : inout std_logic; --inout AUD_ADCLRCK,
-- AUD_BCLK : inout std_logic; --inout AUD_BCLK,
-- AUD_DACDAT : out std_logic; --output AUD_DACDAT,
-- AUD_DACLRCK : inout std_logic; --inout AUD_DACLRCK,
-- AUD_I2C_SCLK : out std_logic; --output AUD_I2C_SCLK,
-- AUD_I2C_SDAT : inout std_logic; --inout AUD_I2C_SDAT,
-- AUD_MUTE : out std_logic; --output AUD_MUTE,
-- AUD_XCK : out std_logic; --output AUD_XCK,
--
-- --HSMC--
-- HSMC_CLKIN_n : in std_logic_vector(2 downto 1); --input [2:1] HSMC_CLKIN_n,
-- HSMC_CLKIN_p : in std_logic_vector(2 downto 1); --input [2:1] HSMC_CLKIN_p,
-- HSMC_CLKOUT_n : out std_logic_vector(2 downto 1); --output [2:1] HSMC_CLKOUT_n,
-- HSMC_CLKOUT_p : out std_logic_vector(2 downto 1); --output [2:1] HSMC_CLKOUT_p,
-- HSMC_CLK_IN0 : out std_logic; --output HSMC_CLK_IN0,
-- HSMC_CLK_OUT0 : out std_logic; --output HSMC_CLK_OUT0,
-- HSMC_D : inout std_logic_vector(3 downto 0); --inout [3:0] HSMC_D,
-- HSMC_GXB_RX_p : in std_logic_vector(7 downto 0); --input [7:0] HSMC_GXB_RX_p,
-- HSMC_GXB_TX_p : out std_logic_vector(7 downto 0); --output [7:0] HSMC_GXB_TX_p,
-- HSMC_REF_CLK_p : in std_logic; --input HSMC_REF_CLK_p,
-- HSMC_RX_n : inout std_logic_vector(16 downto 0); --inout [16:0] HSMC_RX_n,
-- HSMC_RX_p : inout std_logic_vector(16 downto 0); --inout [16:0] HSMC_RX_p,
-- HSMC_SCL : out std_logic; --output HSMC_SCL,
-- HSMC_SDA : inout std_logic; --inout HSMC_SDA,
-- HSMC_TX_n : inout std_logic_vector(16 downto 0); --inout [16:0] HSMC_TX_n,
-- HSMC_TX_p : inout std_logic_vector(16 downto 0); --inout [16:0] HSMC_TX_p,
--
-- --IRDA--
-- IRDA_RXD : in std_logic; --input IRDA_RXD,
--
-- --PCIE--
-- PCIE_PERST_n : in std_logic; --input PCIE_PERST_n,
-- PCIE_WAKE_n : out std_logic; --output PCIE_WAKE_n,
--
-- --SI5338--
-- SI5338_SCL : in std_logic; --inout SI5338_SCL,
-- SI5338_SDA : in std_logic; --inout SI5338_SDA,
--
--TEMP--
-- TEMP_CS_n : out std_logic; --output TEMP_CS_n,
-- TEMP_DIN : out std_logic; --output TEMP_DIN,
-- TEMP_DOUT : in std_logic; --input TEMP_DOUT,
-- TEMP_SCLK : out std_logic; --output TEMP_SCLK,
--
-- --USB--
-- USB_B2_CLK : in std_logic; --input USB_B2_CLK,
-- USB_B2_DATA : inout std_logic_vector(7 downto 0); --inout [7:0] USB_B2_DATA,
-- USB_EMPTY : out std_logic; --output USB_EMPTY,
-- USB_FULL : out std_logic; --output USB_FULL,
-- USB_OE_n : in std_logic; --input USB_OE_n,
-- USB_RD_n : in std_logic; --input USB_RD_n,
-- USB_RESET_n : in std_logic; --input USB_RESET_n,
-- USB_SCL : inout std_logic; --inout USB_SCL,
-- USB_SDA : inout std_logic; --inout USB_SDA,
-- USB_WR_n : in std_logic; --input USB_WR_n,
--
-- --VGA--
-- VGA_B : out std_logic_vector(7 downto 0); --output [7:0] VGA_B,
-- VGA_BLANK_n : out std_logic; --output VGA_BLANK_n,
-- VGA_CLK : out std_logic; --output VGA_CLK,
-- VGA_G : out std_logic_vector(7 downto 0); --output [7:0] VGA_G,
-- VGA_HS : out std_logic; --output VGA_HS,
-- VGA_R : out std_logic_vector(7 downto 0); --output [7:0] VGA_R,
-- VGA_SYNC_n : out std_logic; --output VGA_SYNC_n,
-- VGA_VS : out std_logic; --output VGA_VS
--OSC (CLOCKS)--
OSC_50_B3B : in std_logic;
OSC_50_B4A : in std_logic;
OSC_50_B5B : in std_logic;
OSC_50_B8A : in std_logic;
--RESET--
RESET_n : in std_logic;
--KEY (PUSHBUTTONS)--
KEY : in std_logic_vector(3 downto 0);
--LED--
LED : out std_logic_vector(3 downto 0);
--SW (SWITCHES)--
SW : in std_logic_vector(3 downto 0)
);
end;
architecture rtl of leon3mp is
constant USE_AHBREP: integer := 0
--pragma translate_off
+1
--pragma translate_on
;
-- Bus indexes
constant hmi_cpu : integer := 0;
constant hmi_ahbuart : integer := hmi_cpu + CFG_NCPU;
constant hmi_ahbjtag : integer := hmi_ahbuart + CFG_AHB_UART;
constant hmi_axi2ahb : integer := hmi_ahbjtag + CFG_AHB_JTAG;
constant nahbm : integer := hmi_axi2ahb + CFG_HPS2FPGA;
constant hsi_ahbrom : integer := 0;
constant hsi_apbctrl : integer := hsi_ahbrom + CFG_AHBROMEN;
constant hsi_dsu : integer := hsi_apbctrl + 1;
constant hsi_ddr3 : integer := hsi_dsu + CFG_DSU;
constant hsi_ahb2axi : integer := hsi_ddr3 + 1;
constant hsi_ahbrep : integer := hsi_ahb2axi + CFG_FPGA2HPS;
constant nahbs : integer := hsi_ahbrep + USE_AHBREP;
constant pi_apbuart : integer := 0;
constant pi_irqmp : integer := pi_apbuart + CFG_UART1_ENABLE;
constant pi_gpt : integer := pi_irqmp + CFG_IRQ3_ENABLE;
constant pi_ahbuart : integer := pi_gpt + CFG_GPT_ENABLE;
constant napbs : integer := pi_ahbuart + CFG_AHB_UART;
signal clklock: std_ulogic;
signal clkm: std_ulogic;
signal ssclk: std_ulogic;
signal rstn: std_ulogic;
signal rstraw: std_ulogic;
signal ahbmi: ahb_mst_in_type;
signal ahbmo: ahb_mst_out_vector;
signal ahbsi: ahb_slv_in_type;
signal ahbso: ahb_slv_out_vector;
signal apbi: apb_slv_in_type;
signal apbo: apb_slv_out_vector;
signal irqi: irq_in_vector(CFG_NCPU-1 downto 0);
signal irqo: irq_out_vector(CFG_NCPU-1 downto 0);
signal dbgi: l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo: l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui: dsu_in_type;
signal dsuo: dsu_out_type;
signal gpti: gptimer_in_type;
signal sri: memory_in_type;
signal sro: memory_out_type;
signal del_addr: std_logic_vector(26 downto 1);
signal del_ce: std_logic;
signal del_bwe, del_bwa, del_bwb: std_logic_vector(1 downto 0);
signal dui, ui: uart_in_type;
signal duo, uo: uart_out_type;
signal vcc, gnd: std_ulogic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
-----------------------------------------------------------------------------
-- HPS signals and component
-----------------------------------------------------------------------------
constant idsize : integer := 8;
constant lensize : integer := 4;
constant periph_addrsize : integer := 28;
type f2h_axi is record
araddr : STD_LOGIC_VECTOR ( 31 downto 0 );
arburst : STD_LOGIC_VECTOR ( 1 downto 0 );
arcache : STD_LOGIC_VECTOR ( 3 downto 0 );
arid : STD_LOGIC_VECTOR ( 11 downto 0 );
arlen : STD_LOGIC_VECTOR ( 3 downto 0 );
arlock : STD_LOGIC_VECTOR ( 1 downto 0 ); --
arprot : STD_LOGIC_VECTOR ( 2 downto 0 );
arqos : STD_LOGIC_VECTOR ( 3 downto 0 ); --
awqos : STD_LOGIC_VECTOR ( 3 downto 0 ); --
arready : STD_LOGIC;
arsize : STD_LOGIC_VECTOR ( 2 downto 0 );
arvalid : STD_LOGIC;
awaddr : STD_LOGIC_VECTOR ( 31 downto 0 );
awburst : STD_LOGIC_VECTOR ( 1 downto 0 );
awcache : STD_LOGIC_VECTOR ( 3 downto 0 );
awid : STD_LOGIC_VECTOR ( 11 downto 0 );
awlen : STD_LOGIC_VECTOR ( 3 downto 0 );
awlock : STD_LOGIC_VECTOR ( 1 downto 0 ); --
awprot : STD_LOGIC_VECTOR ( 2 downto 0 );
awready : STD_LOGIC;
awsize : STD_LOGIC_VECTOR ( 2 downto 0 );
awvalid : STD_LOGIC;
bid : STD_LOGIC_VECTOR ( 11 downto 0 );
bready : STD_LOGIC;
bresp : STD_LOGIC_VECTOR ( 1 downto 0 );
bvalid : STD_LOGIC;
rdata : STD_LOGIC_VECTOR ( 31 downto 0 );
rid : STD_LOGIC_VECTOR ( 11 downto 0 );
rlast : STD_LOGIC;
rready : STD_LOGIC;
rresp : STD_LOGIC_VECTOR ( 1 downto 0 );
rvalid : STD_LOGIC;
wdata : STD_LOGIC_VECTOR ( 31 downto 0 );
wlast : STD_LOGIC;
wready : STD_LOGIC;
wstrb : STD_LOGIC_VECTOR ( 3 downto 0 );
wvalid : STD_LOGIC;
wid : STD_LOGIC_VECTOR ( 11 downto 0 ); --
end record;
signal h2f, f2h : f2h_axi;
component hps is
port (
clk_clk : in std_logic := 'X'; -- clk
hps_hps_io_emac1_inst_TX_CLK : out std_logic; -- hps_io_emac1_inst_TX_CLK
hps_hps_io_emac1_inst_TXD0 : out std_logic; -- hps_io_emac1_inst_TXD0
hps_hps_io_emac1_inst_TXD1 : out std_logic; -- hps_io_emac1_inst_TXD1
hps_hps_io_emac1_inst_TXD2 : out std_logic; -- hps_io_emac1_inst_TXD2
hps_hps_io_emac1_inst_TXD3 : out std_logic; -- hps_io_emac1_inst_TXD3
hps_hps_io_emac1_inst_RXD0 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD0
hps_hps_io_emac1_inst_MDIO : inout std_logic := 'X'; -- hps_io_emac1_inst_MDIO
hps_hps_io_emac1_inst_MDC : out std_logic; -- hps_io_emac1_inst_MDC
hps_hps_io_emac1_inst_RX_CTL : in std_logic := 'X'; -- hps_io_emac1_inst_RX_CTL
hps_hps_io_emac1_inst_TX_CTL : out std_logic; -- hps_io_emac1_inst_TX_CTL
hps_hps_io_emac1_inst_RX_CLK : in std_logic := 'X'; -- hps_io_emac1_inst_RX_CLK
hps_hps_io_emac1_inst_RXD1 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD1
hps_hps_io_emac1_inst_RXD2 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD2
hps_hps_io_emac1_inst_RXD3 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD3
hps_hps_io_qspi_inst_IO0 : inout std_logic := 'X'; -- hps_io_qspi_inst_IO0
hps_hps_io_qspi_inst_IO1 : inout std_logic := 'X'; -- hps_io_qspi_inst_IO1
hps_hps_io_qspi_inst_IO2 : inout std_logic := 'X'; -- hps_io_qspi_inst_IO2
hps_hps_io_qspi_inst_IO3 : inout std_logic := 'X'; -- hps_io_qspi_inst_IO3
hps_hps_io_qspi_inst_SS0 : out std_logic; -- hps_io_qspi_inst_SS0
hps_hps_io_qspi_inst_CLK : out std_logic; -- hps_io_qspi_inst_CLK
hps_hps_io_sdio_inst_CMD : inout std_logic := 'X'; -- hps_io_sdio_inst_CMD
hps_hps_io_sdio_inst_D0 : inout std_logic := 'X'; -- hps_io_sdio_inst_D0
hps_hps_io_sdio_inst_D1 : inout std_logic := 'X'; -- hps_io_sdio_inst_D1
hps_hps_io_sdio_inst_CLK : out std_logic; -- hps_io_sdio_inst_CLK
hps_hps_io_sdio_inst_D2 : inout std_logic := 'X'; -- hps_io_sdio_inst_D2
hps_hps_io_sdio_inst_D3 : inout std_logic := 'X'; -- hps_io_sdio_inst_D3
hps_hps_io_usb1_inst_D0 : inout std_logic := 'X'; -- hps_io_usb1_inst_D0
hps_hps_io_usb1_inst_D1 : inout std_logic := 'X'; -- hps_io_usb1_inst_D1
hps_hps_io_usb1_inst_D2 : inout std_logic := 'X'; -- hps_io_usb1_inst_D2
hps_hps_io_usb1_inst_D3 : inout std_logic := 'X'; -- hps_io_usb1_inst_D3
hps_hps_io_usb1_inst_D4 : inout std_logic := 'X'; -- hps_io_usb1_inst_D4
hps_hps_io_usb1_inst_D5 : inout std_logic := 'X'; -- hps_io_usb1_inst_D5
hps_hps_io_usb1_inst_D6 : inout std_logic := 'X'; -- hps_io_usb1_inst_D6
hps_hps_io_usb1_inst_D7 : inout std_logic := 'X'; -- hps_io_usb1_inst_D7
hps_hps_io_usb1_inst_CLK : in std_logic := 'X'; -- hps_io_usb1_inst_CLK
hps_hps_io_usb1_inst_STP : out std_logic; -- hps_io_usb1_inst_STP
hps_hps_io_usb1_inst_DIR : in std_logic := 'X'; -- hps_io_usb1_inst_DIR
hps_hps_io_usb1_inst_NXT : in std_logic := 'X'; -- hps_io_usb1_inst_NXT
hps_hps_io_spim0_inst_CLK : out std_logic; -- hps_io_spim0_inst_CLK
hps_hps_io_spim0_inst_MOSI : out std_logic; -- hps_io_spim0_inst_MOSI
hps_hps_io_spim0_inst_MISO : in std_logic := 'X'; -- hps_io_spim0_inst_MISO
hps_hps_io_spim0_inst_SS0 : out std_logic; -- hps_io_spim0_inst_SS0
hps_hps_io_spim1_inst_CLK : out std_logic; -- hps_io_spim1_inst_CLK
hps_hps_io_spim1_inst_MOSI : out std_logic; -- hps_io_spim1_inst_MOSI
hps_hps_io_spim1_inst_MISO : in std_logic := 'X'; -- hps_io_spim1_inst_MISO
hps_hps_io_spim1_inst_SS0 : out std_logic; -- hps_io_spim1_inst_SS0
hps_hps_io_uart0_inst_RX : in std_logic := 'X'; -- hps_io_uart0_inst_RX
hps_hps_io_uart0_inst_TX : out std_logic; -- hps_io_uart0_inst_TX
hps_hps_io_i2c1_inst_SDA : inout std_logic := 'X'; -- hps_io_i2c1_inst_SDA
hps_hps_io_i2c1_inst_SCL : inout std_logic := 'X'; -- hps_io_i2c1_inst_SCL
hps_hps_io_gpio_inst_GPIO00 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO00
hps_hps_io_gpio_inst_GPIO09 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO09
hps_hps_io_gpio_inst_GPIO35 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO35
hps_hps_io_gpio_inst_GPIO40 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO40
hps_hps_io_gpio_inst_GPIO48 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO48
hps_hps_io_gpio_inst_GPIO53 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO53
hps_hps_io_gpio_inst_GPIO54 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO54
hps_hps_io_gpio_inst_GPIO55 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO55
hps_hps_io_gpio_inst_GPIO56 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO56
hps_hps_io_gpio_inst_GPIO61 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO61
hps_hps_io_gpio_inst_GPIO62 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO62
hps_ddr_mem_a : out std_logic_vector(14 downto 0); -- mem_a
hps_ddr_mem_ba : out std_logic_vector(2 downto 0); -- mem_ba
hps_ddr_mem_ck : out std_logic; -- mem_ck
hps_ddr_mem_ck_n : out std_logic; -- mem_ck_n
hps_ddr_mem_cke : out std_logic; -- mem_cke
hps_ddr_mem_cs_n : out std_logic; -- mem_cs_n
hps_ddr_mem_ras_n : out std_logic; -- mem_ras_n
hps_ddr_mem_cas_n : out std_logic; -- mem_cas_n
hps_ddr_mem_we_n : out std_logic; -- mem_we_n
hps_ddr_mem_reset_n : out std_logic; -- mem_reset_n
hps_ddr_mem_dq : inout std_logic_vector(31 downto 0) := (others => 'X'); -- mem_dq
hps_ddr_mem_dqs : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs
hps_ddr_mem_dqs_n : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs_n
hps_ddr_mem_odt : out std_logic; -- mem_odt
hps_ddr_mem_dm : out std_logic_vector(3 downto 0); -- mem_dm
hps_ddr_oct_rzqin : in std_logic := 'X'; -- oct_rzqin
hps_f2h_axi_slave_awid : in std_logic_vector(7 downto 0) := (others => 'X'); -- awid
hps_f2h_axi_slave_awaddr : in std_logic_vector(31 downto 0) := (others => 'X'); -- awaddr
hps_f2h_axi_slave_awlen : in std_logic_vector(3 downto 0) := (others => 'X'); -- awlen
hps_f2h_axi_slave_awsize : in std_logic_vector(2 downto 0) := (others => 'X'); -- awsize
hps_f2h_axi_slave_awburst : in std_logic_vector(1 downto 0) := (others => 'X'); -- awburst
hps_f2h_axi_slave_awlock : in std_logic_vector(1 downto 0) := (others => 'X'); -- awlock
hps_f2h_axi_slave_awcache : in std_logic_vector(3 downto 0) := (others => 'X'); -- awcache
hps_f2h_axi_slave_awprot : in std_logic_vector(2 downto 0) := (others => 'X'); -- awprot
hps_f2h_axi_slave_awvalid : in std_logic := 'X'; -- awvalid
hps_f2h_axi_slave_awready : out std_logic; -- awready
hps_f2h_axi_slave_awuser : in std_logic_vector(4 downto 0) := (others => 'X'); -- awuser
hps_f2h_axi_slave_wid : in std_logic_vector(7 downto 0) := (others => 'X'); -- wid
hps_f2h_axi_slave_wdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- wdata
hps_f2h_axi_slave_wstrb : in std_logic_vector(3 downto 0) := (others => 'X'); -- wstrb
hps_f2h_axi_slave_wlast : in std_logic := 'X'; -- wlast
hps_f2h_axi_slave_wvalid : in std_logic := 'X'; -- wvalid
hps_f2h_axi_slave_wready : out std_logic; -- wready
hps_f2h_axi_slave_bid : out std_logic_vector(7 downto 0); -- bid
hps_f2h_axi_slave_bresp : out std_logic_vector(1 downto 0); -- bresp
hps_f2h_axi_slave_bvalid : out std_logic; -- bvalid
hps_f2h_axi_slave_bready : in std_logic := 'X'; -- bready
hps_f2h_axi_slave_arid : in std_logic_vector(7 downto 0) := (others => 'X'); -- arid
hps_f2h_axi_slave_araddr : in std_logic_vector(31 downto 0) := (others => 'X'); -- araddr
hps_f2h_axi_slave_arlen : in std_logic_vector(3 downto 0) := (others => 'X'); -- arlen
hps_f2h_axi_slave_arsize : in std_logic_vector(2 downto 0) := (others => 'X'); -- arsize
hps_f2h_axi_slave_arburst : in std_logic_vector(1 downto 0) := (others => 'X'); -- arburst
hps_f2h_axi_slave_arlock : in std_logic_vector(1 downto 0) := (others => 'X'); -- arlock
hps_f2h_axi_slave_arcache : in std_logic_vector(3 downto 0) := (others => 'X'); -- arcache
hps_f2h_axi_slave_arprot : in std_logic_vector(2 downto 0) := (others => 'X'); -- arprot
hps_f2h_axi_slave_arvalid : in std_logic := 'X'; -- arvalid
hps_f2h_axi_slave_arready : out std_logic; -- arready
hps_f2h_axi_slave_aruser : in std_logic_vector(4 downto 0) := (others => 'X'); -- aruser
hps_f2h_axi_slave_rid : out std_logic_vector(7 downto 0); -- rid
hps_f2h_axi_slave_rdata : out std_logic_vector(31 downto 0); -- rdata
hps_f2h_axi_slave_rresp : out std_logic_vector(1 downto 0); -- rresp
hps_f2h_axi_slave_rlast : out std_logic; -- rlast
hps_f2h_axi_slave_rvalid : out std_logic; -- rvalid
hps_f2h_axi_slave_rready : in std_logic := 'X'; -- rready
hps_f2h_irq0_irq : in std_logic_vector(31 downto 0) := (others => 'X'); -- irq
hps_f2h_irq1_irq : in std_logic_vector(31 downto 0) := (others => 'X'); -- irq
hps_f2h_stm_hw_events_stm_hwevents : in std_logic_vector(27 downto 0) := (others => 'X'); -- stm_hwevents
hps_h2f_lw_axi_master_awid : out std_logic_vector(11 downto 0); -- awid
hps_h2f_lw_axi_master_awaddr : out std_logic_vector(20 downto 0); -- awaddr
hps_h2f_lw_axi_master_awlen : out std_logic_vector(3 downto 0); -- awlen
hps_h2f_lw_axi_master_awsize : out std_logic_vector(2 downto 0); -- awsize
hps_h2f_lw_axi_master_awburst : out std_logic_vector(1 downto 0); -- awburst
hps_h2f_lw_axi_master_awlock : out std_logic_vector(1 downto 0); -- awlock
hps_h2f_lw_axi_master_awcache : out std_logic_vector(3 downto 0); -- awcache
hps_h2f_lw_axi_master_awprot : out std_logic_vector(2 downto 0); -- awprot
hps_h2f_lw_axi_master_awvalid : out std_logic; -- awvalid
hps_h2f_lw_axi_master_awready : in std_logic := 'X'; -- awready
hps_h2f_lw_axi_master_wid : out std_logic_vector(11 downto 0); -- wid
hps_h2f_lw_axi_master_wdata : out std_logic_vector(31 downto 0); -- wdata
hps_h2f_lw_axi_master_wstrb : out std_logic_vector(3 downto 0); -- wstrb
hps_h2f_lw_axi_master_wlast : out std_logic; -- wlast
hps_h2f_lw_axi_master_wvalid : out std_logic; -- wvalid
hps_h2f_lw_axi_master_wready : in std_logic := 'X'; -- wready
hps_h2f_lw_axi_master_bid : in std_logic_vector(11 downto 0) := (others => 'X'); -- bid
hps_h2f_lw_axi_master_bresp : in std_logic_vector(1 downto 0) := (others => 'X'); -- bresp
hps_h2f_lw_axi_master_bvalid : in std_logic := 'X'; -- bvalid
hps_h2f_lw_axi_master_bready : out std_logic; -- bready
hps_h2f_lw_axi_master_arid : out std_logic_vector(11 downto 0); -- arid
hps_h2f_lw_axi_master_araddr : out std_logic_vector(20 downto 0); -- araddr
hps_h2f_lw_axi_master_arlen : out std_logic_vector(3 downto 0); -- arlen
hps_h2f_lw_axi_master_arsize : out std_logic_vector(2 downto 0); -- arsize
hps_h2f_lw_axi_master_arburst : out std_logic_vector(1 downto 0); -- arburst
hps_h2f_lw_axi_master_arlock : out std_logic_vector(1 downto 0); -- arlock
hps_h2f_lw_axi_master_arcache : out std_logic_vector(3 downto 0); -- arcache
hps_h2f_lw_axi_master_arprot : out std_logic_vector(2 downto 0); -- arprot
hps_h2f_lw_axi_master_arvalid : out std_logic; -- arvalid
hps_h2f_lw_axi_master_arready : in std_logic := 'X'; -- arready
hps_h2f_lw_axi_master_rid : in std_logic_vector(11 downto 0) := (others => 'X'); -- rid
hps_h2f_lw_axi_master_rdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- rdata
hps_h2f_lw_axi_master_rresp : in std_logic_vector(1 downto 0) := (others => 'X'); -- rresp
hps_h2f_lw_axi_master_rlast : in std_logic := 'X'; -- rlast
hps_h2f_lw_axi_master_rvalid : in std_logic := 'X'; -- rvalid
hps_h2f_lw_axi_master_rready : out std_logic; -- rready
hps_h2f_reset_reset_n : out std_logic; -- reset_n
reset_reset_n : in std_logic := 'X'; -- reset_n
hps_h2f_axi_master_awid : out std_logic_vector(11 downto 0); -- awid
hps_h2f_axi_master_awaddr : out std_logic_vector(29 downto 0); -- awaddr
hps_h2f_axi_master_awlen : out std_logic_vector(3 downto 0); -- awlen
hps_h2f_axi_master_awsize : out std_logic_vector(2 downto 0); -- awsize
hps_h2f_axi_master_awburst : out std_logic_vector(1 downto 0); -- awburst
hps_h2f_axi_master_awlock : out std_logic_vector(1 downto 0); -- awlock
hps_h2f_axi_master_awcache : out std_logic_vector(3 downto 0); -- awcache
hps_h2f_axi_master_awprot : out std_logic_vector(2 downto 0); -- awprot
hps_h2f_axi_master_awvalid : out std_logic; -- awvalid
hps_h2f_axi_master_awready : in std_logic := 'X'; -- awready
hps_h2f_axi_master_wid : out std_logic_vector(11 downto 0); -- wid
hps_h2f_axi_master_wdata : out std_logic_vector(31 downto 0); -- wdata
hps_h2f_axi_master_wstrb : out std_logic_vector(3 downto 0); -- wstrb
hps_h2f_axi_master_wlast : out std_logic; -- wlast
hps_h2f_axi_master_wvalid : out std_logic; -- wvalid
hps_h2f_axi_master_wready : in std_logic := 'X'; -- wready
hps_h2f_axi_master_bid : in std_logic_vector(11 downto 0) := (others => 'X'); -- bid
hps_h2f_axi_master_bresp : in std_logic_vector(1 downto 0) := (others => 'X'); -- bresp
hps_h2f_axi_master_bvalid : in std_logic := 'X'; -- bvalid
hps_h2f_axi_master_bready : out std_logic; -- bready
hps_h2f_axi_master_arid : out std_logic_vector(11 downto 0); -- arid
hps_h2f_axi_master_araddr : out std_logic_vector(29 downto 0); -- araddr
hps_h2f_axi_master_arlen : out std_logic_vector(3 downto 0); -- arlen
hps_h2f_axi_master_arsize : out std_logic_vector(2 downto 0); -- arsize
hps_h2f_axi_master_arburst : out std_logic_vector(1 downto 0); -- arburst
hps_h2f_axi_master_arlock : out std_logic_vector(1 downto 0); -- arlock
hps_h2f_axi_master_arcache : out std_logic_vector(3 downto 0); -- arcache
hps_h2f_axi_master_arprot : out std_logic_vector(2 downto 0); -- arprot
hps_h2f_axi_master_arvalid : out std_logic; -- arvalid
hps_h2f_axi_master_arready : in std_logic := 'X'; -- arready
hps_h2f_axi_master_rid : in std_logic_vector(11 downto 0) := (others => 'X'); -- rid
hps_h2f_axi_master_rdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- rdata
hps_h2f_axi_master_rresp : in std_logic_vector(1 downto 0) := (others => 'X'); -- rresp
hps_h2f_axi_master_rlast : in std_logic := 'X'; -- rlast
hps_h2f_axi_master_rvalid : in std_logic := 'X'; -- rvalid
hps_h2f_axi_master_rready : out std_logic -- rready
);
end component hps;
--
constant BOARD_FREQ : integer := 50000; -- Board frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
signal hpsrst : std_logic;
signal sys_rst_n : std_logic;
begin
vcc <= '1';
gnd <= '0';
-----------------------------------------------------------------------------
-- Clocking and reset
-----------------------------------------------------------------------------
LED(1) <= not clklock;
rstgen0: if CFG_HPS_RESET = 1 generate
sys_rst_n <= RESET_n and hpsrst;
end generate;
nohps: if CFG_HPS_RESET /= 1 generate
sys_rst_n <= RESET_n;
end generate;
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
clklock <= cgo.clklock;
clkgen0 : clkgen -- clock generator using toplevel generic 'freq'
generic map (tech => altera, clk_mul => 7,
clk_div => 5, sdramen => 0,
noclkfb => 0, freq => 50000)
port map (clkin => OSC_50_B3B, pciclkin => gnd, clk => clkm, clkn => open,
clk2x => open, sdclk => open, pciclk => open,
cgi => cgi, cgo => cgo);
rstgen1: rstgen
generic map (syncrst => CFG_NOASYNC)
port map (sys_rst_n, clkm, clklock, rstn, rstraw);
-----------------------------------------------------------------------------
-- AMBA bus fabric
-----------------------------------------------------------------------------
ahbctrl0: ahbctrl
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN,ioaddr => CFG_AHBIO, fpnpen => CFG_FPNPEN,
enbusmon => CFG_AHB_MON, assertwarn => CFG_AHB_MONWAR,
asserterr => CFG_AHB_MONERR, ahbtrace => CFG_AHB_DTRACE,
nahbm => nahbm, nahbs => nahbs)
port map (rstn,clkm,ahbmi,ahbmo,ahbsi,ahbso);
apbctrl0: apbctrl
generic map (hindex => hsi_apbctrl, haddr => CFG_APBADDR, nslaves => napbs)
port map (rstn,clkm,ahbsi,ahbso(hsi_apbctrl),apbi,apbo);
ahbmo(ahbmo'high downto nahbm) <= (others => ahbm_none);
ahbso(ahbso'high downto nahbs) <= (others => ahbs_none);
apbo(napbs to apbo'high) <= (others => apb_none);
-----------------------------------------------------------------------------
-- LEON3 Processor(s), DSU
-----------------------------------------------------------------------------
errorn_pad : outpad generic map (tech => padtech) port map (LED(3), dbgo(0).error);
dsubre_pad : inpad generic map (tech => padtech) port map (KEY(3), dsui.break);
LED(2) <= not dsuo.active;
dsui.enable <= '1';
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => hsi_dsu, haddr => 16#D00#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(hsi_dsu), dbgo, dbgi, dsui, dsuo);
end generate;
end generate;
noleon: if CFG_LEON3 = 0 generate
irqo <= (others => ('0',"0000",'0','0','0'));
dbgo <= (others => dbgo_none);
end generate;
nodsu : if CFG_DSU = 0 or CFG_LEON3 = 0 generate
dsuo.tstop <= '0'; dsuo.active <= '0'; dsuo.pwd <= (others => '0');
end generate;
-----------------------------------------------------------------------------
-- APB Slaves
-----------------------------------------------------------------------------
ua0 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart
generic map (pindex => pi_apbuart, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(pi_apbuart), ui, uo);
end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => pi_irqmp, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(pi_irqmp), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
irqi(i).rst <= '1';
irqi(i).run <= '1';
irqi(i).rstvec <= (others => '0');
irqi(i).iact <= '0';
irqi(i).index <= (others => '0');
irqi(i).hrdrst <= '1';
end generate;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => pi_gpt, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(pi_gpt), gpti, open);
gpti <= gpti_dhalt_drive(dsuo.tstop);
end generate;
-----------------------------------------------------------------------------
-- Debug links
-----------------------------------------------------------------------------
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart -- Debug UART
generic map (hindex => hmi_ahbuart, pindex => pi_ahbuart, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(pi_ahbuart), ahbmi, ahbmo(hmi_ahbuart));
end generate;
nouah : if CFG_AHB_UART = 0 generate
duo.rtsn <= '0'; duo.txd <= '0';
duo.scaler <= (others => '0'); duo.txen <= '0';
duo.flow <= '0'; duo.rxen <= '0';
end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => hmi_ahbjtag, nsync => 2, versel => 0)
port map(rstn, clkm, gnd, gnd, gnd, open, ahbmi, ahbmo(hmi_ahbjtag),
open, open, open, open, open, open, open, gnd);
end generate;
-----------------------------------------------------------------------------
-- Memory controllers
-----------------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => hsi_ahbrom, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(hsi_ahbrom));
end generate;
ddr3if0: entity work.ddr3if
generic map (
hindex => hsi_ddr3,
haddr => 16#400#, hmask => 16#C00#
) port map (
pll_ref_clk => OSC_50_B5B,
global_reset_n => RESET_n,
mem_a => DDR3_A,
mem_ba => DDR3_BA,
mem_ck => DDR3_CK_p,
mem_ck_n => DDR_CK_n,
mem_cke => DDR3_CKE,
mem_reset_n => DDR3_RESET_n,
mem_cs_n => DDR3_CS_n,
mem_dm => DDR3_DM,
mem_ras_n => DDR3_RAS_n,
mem_cas_n => DDR3_CAS_n,
mem_we_n => DDR3_WE_n,
mem_dq => DDR3_DQ,
mem_dqs => DDR3_DQS_p,
mem_dqs_n => DDR3_DQS_n,
mem_odt => DDR3_ODT,
oct_rzqin => DDR3_RZQ,
ahb_clk => clkm,
ahb_rst => rstn,
ahbsi => ahbsi,
ahbso => ahbso(hsi_ddr3)
);
-----------------------------------------------------------------------------
-- Hard Processor System
-----------------------------------------------------------------------------
-- FPGA2HPS Bridge
fpga2hps: if CFG_FPGA2HPS = 1 generate
ahb2axi0 : entity work.ahb2axi
generic map(
hindex => hsi_ahb2axi, haddr => 16#CF0#, hmask => 16#FF0#,
idsize => idsize, lensize => lensize, addrsize => periph_addrsize)
port map(
rstn => rstn,
clk => clkm,
ahbsi => ahbsi,
ahbso => ahbso(hsi_ahb2axi),
M_AXI_araddr => f2h.araddr(periph_addrsize-1 downto 0),
M_AXI_arburst(1 downto 0) => f2h.arburst(1 downto 0),
M_AXI_arcache(3 downto 0) => f2h.arcache(3 downto 0),
M_AXI_arid => f2h.arid(7 downto 0),
M_AXI_arlen => f2h.arlen,
M_AXI_arlock => f2h.arlock,
M_AXI_arprot(2 downto 0) => f2h.arprot(2 downto 0),
M_AXI_arqos => f2h.arqos,
M_AXI_arready => f2h.arready,
M_AXI_arsize(2 downto 0) => f2h.arsize(2 downto 0),
M_AXI_arvalid => f2h.arvalid,
M_AXI_awaddr => f2h.awaddr(periph_addrsize-1 downto 0),
M_AXI_awburst(1 downto 0) => f2h.awburst(1 downto 0),
M_AXI_awcache(3 downto 0) => f2h.awcache(3 downto 0),
M_AXI_awid => f2h.awid(7 downto 0),
M_AXI_awlen => f2h.awlen,
M_AXI_awlock => f2h.awlock,
M_AXI_awprot(2 downto 0) => f2h.awprot(2 downto 0),
M_AXI_awqos => f2h.awqos,
M_AXI_awready => f2h.awready,
M_AXI_awsize(2 downto 0) => f2h.awsize(2 downto 0),
M_AXI_awvalid => f2h.awvalid,
M_AXI_bid => f2h.bid(7 downto 0),
M_AXI_bready => f2h.bready,
M_AXI_bresp(1 downto 0) => f2h.bresp(1 downto 0),
M_AXI_bvalid => f2h.bvalid,
M_AXI_rdata(31 downto 0) => f2h.rdata(31 downto 0),
M_AXI_rid => f2h.rid(7 downto 0),
M_AXI_rlast => f2h.rlast,
M_AXI_rready => f2h.rready,
M_AXI_rresp(1 downto 0) => f2h.rresp(1 downto 0),
M_AXI_rvalid => f2h.rvalid,
M_AXI_wdata(31 downto 0) => f2h.wdata(31 downto 0),
M_AXI_wlast => f2h.wlast,
M_AXI_wready => f2h.wready,
M_AXI_wstrb(3 downto 0) => f2h.wstrb(3 downto 0),
M_AXI_wvalid => f2h.wvalid
);
f2h.araddr(31 downto periph_addrsize) <= (others => '1');
f2h.awaddr(31 downto periph_addrsize) <= (others => '1');
end generate;
--HPS2FPGA bridge
hps2fpga: if CFG_HPS2FPGA = 1 generate
axi2ahb : entity work.axi2ahb
generic map(
hindex => hmi_axi2ahb,
idsize => 12,
lensize => lensize,
fifo_depth => 16
)
port map(
ahb_clk => clkm,
axi_clk => clkm,
resetn => rstn,
ahbi => ahbmi,
ahbo => ahbmo(hmi_axi2ahb),
s_axi_araddr => h2f.araddr,
s_axi_arburst => h2f.arburst,
s_axi_arcache => h2f.arcache,
s_axi_arid => h2f.arid(11 downto 0),
s_axi_arlen => h2f.arlen,
s_axi_arlock => h2f.arlock,
s_axi_arprot => h2f.arprot,
s_axi_arqos => h2f.arqos,
s_axi_arready => h2f.arready,
s_axi_arsize => h2f.arsize,
s_axi_arvalid => h2f.arvalid,
s_axi_awaddr => h2f.awaddr,
s_axi_awburst => h2f.awburst,
s_axi_awcache => h2f.awcache,
s_axi_awid => h2f.awid(11 downto 0),
s_axi_awlen => h2f.awlen,
s_axi_awlock => h2f.awlock,
s_axi_awprot => h2f.awprot,
s_axi_awqos => h2f.awqos,
s_axi_awready => h2f.awready,
s_axi_awsize => h2f.awsize,
s_axi_awvalid => h2f.awvalid,
s_axi_bid => h2f.bid(11 downto 0),
s_axi_bready => h2f.bready,
s_axi_bresp => h2f.bresp,
s_axi_bvalid => h2f.bvalid,
s_axi_rdata => h2f.rdata(31 downto 0),
s_axi_rid => h2f.rid(11 downto 0),
s_axi_rlast => h2f.rlast,
s_axi_rready => h2f.rready,
s_axi_rresp => h2f.rresp,
s_axi_rvalid => h2f.rvalid,
s_axi_wdata => h2f.wdata(31 downto 0),
s_axi_wid => h2f.wid(11 downto 0),
s_axi_wlast => h2f.wlast,
s_axi_wready => h2f.wready,
s_axi_wstrb => h2f.wstrb(3 downto 0),
s_axi_wvalid => h2f.wvalid
);
h2f.araddr(31 downto 30) <= "10";
h2f.awaddr(31 downto 30) <= "10";
end generate;
hps_inst : component hps
port map (
clk_clk => clkm,
hps_hps_io_emac1_inst_TX_CLK => HPS_ENET_GTX_CLK,
hps_hps_io_emac1_inst_TXD0 => HPS_ENET_TX_DATA(0),
hps_hps_io_emac1_inst_TXD1 => HPS_ENET_TX_DATA(1),
hps_hps_io_emac1_inst_TXD2 => HPS_ENET_TX_DATA(2),
hps_hps_io_emac1_inst_TXD3 => HPS_ENET_TX_DATA(3),
hps_hps_io_emac1_inst_RXD0 => HPS_ENET_RX_DATA(0),
hps_hps_io_emac1_inst_MDIO => HPS_ENET_MDIO,
hps_hps_io_emac1_inst_MDC => HPS_ENET_MDC,
hps_hps_io_emac1_inst_RX_CTL => HPS_ENET_RX_DV,
hps_hps_io_emac1_inst_TX_CTL => HPS_ENET_TX_EN,
hps_hps_io_emac1_inst_RX_CLK => HPS_ENET_RX_CLK,
hps_hps_io_emac1_inst_RXD1 => HPS_ENET_RX_DATA(1),
hps_hps_io_emac1_inst_RXD2 => HPS_ENET_RX_DATA(2),
hps_hps_io_emac1_inst_RXD3 => HPS_ENET_RX_DATA(3),
hps_hps_io_qspi_inst_IO0 => HPS_FLASH_DATA(0),
hps_hps_io_qspi_inst_IO1 => HPS_FLASH_DATA(1),
hps_hps_io_qspi_inst_IO2 => HPS_FLASH_DATA(2),
hps_hps_io_qspi_inst_IO3 => HPS_FLASH_DATA(3),
hps_hps_io_qspi_inst_SS0 => HPS_FLASH_NCSO,
hps_hps_io_qspi_inst_CLK => HPS_FLASH_DCLK,
hps_hps_io_sdio_inst_CMD => HPS_SD_CMD,
hps_hps_io_sdio_inst_D0 => HPS_SD_DATA(0),
hps_hps_io_sdio_inst_D1 => HPS_SD_DATA(1),
hps_hps_io_sdio_inst_CLK => HPS_SD_CLK,
hps_hps_io_sdio_inst_D2 => HPS_SD_DATA(2),
hps_hps_io_sdio_inst_D3 => HPS_SD_DATA(3),
hps_hps_io_usb1_inst_D0 => HPS_USB_DATA(0),
hps_hps_io_usb1_inst_D1 => HPS_USB_DATA(1),
hps_hps_io_usb1_inst_D2 => HPS_USB_DATA(2),
hps_hps_io_usb1_inst_D3 => HPS_USB_DATA(3),
hps_hps_io_usb1_inst_D4 => HPS_USB_DATA(4),
hps_hps_io_usb1_inst_D5 => HPS_USB_DATA(5),
hps_hps_io_usb1_inst_D6 => HPS_USB_DATA(6),
hps_hps_io_usb1_inst_D7 => HPS_USB_DATA(7),
hps_hps_io_usb1_inst_CLK => HPS_USB_CLKOUT,
hps_hps_io_usb1_inst_STP => HPS_USB_STP,
hps_hps_io_usb1_inst_DIR => HPS_USB_DIR,
hps_hps_io_usb1_inst_NXT => HPS_USB_NXT,
hps_hps_io_spim0_inst_CLK => HPS_SPIM_CLK,
hps_hps_io_spim0_inst_MOSI => HPS_SPIM_MOSI,
hps_hps_io_spim0_inst_MISO => HPS_SPIM_MISO,
hps_hps_io_spim0_inst_SS0 => HPS_SPIM_SS,
hps_hps_io_spim1_inst_CLK => HPS_LCM_SPIM_CLK,
hps_hps_io_spim1_inst_MOSI => HPS_LCM_SPIM_MOSI,
hps_hps_io_spim1_inst_MISO => HPS_LCM_SPIM_MISO,
hps_hps_io_spim1_inst_SS0 => HPS_LCM_SPIM_SS,
hps_hps_io_uart0_inst_RX => HPS_UART_RX,
hps_hps_io_uart0_inst_TX => HPS_UART_TX,
hps_hps_io_i2c1_inst_SDA => HPS_I2C_SDA,
hps_hps_io_i2c1_inst_SCL => HPS_I2C_CLK,
hps_hps_io_gpio_inst_GPIO00 => HPS_LTC_GPIO,
hps_hps_io_gpio_inst_GPIO09 => HPS_CONV_USB_n,
hps_hps_io_gpio_inst_GPIO35 => HPS_ENET_INT_n,
hps_hps_io_gpio_inst_GPIO40 => HPS_LCM_BK,
hps_hps_io_gpio_inst_GPIO48 => HPS_LCM_RST_N,
hps_hps_io_gpio_inst_GPIO53 => HPS_LED(0),
hps_hps_io_gpio_inst_GPIO54 => HPS_LED(1),
hps_hps_io_gpio_inst_GPIO55 => HPS_LED(2),
hps_hps_io_gpio_inst_GPIO56 => HPS_LED(3),
hps_hps_io_gpio_inst_GPIO61 => HPS_GSENSOR_INT,
hps_hps_io_gpio_inst_GPIO62 => HPS_LCM_D_C,
hps_ddr_mem_a => HPS_DDR3_A,
hps_ddr_mem_ba => HPS_DDR3_BA,
hps_ddr_mem_ck => HPS_DDR3_CK_p,
hps_ddr_mem_ck_n => HPS_DDR3_CK_n,
hps_ddr_mem_cke => HPS_DDR3_CKE,
hps_ddr_mem_cs_n => HPS_DDR3_CS_n,
hps_ddr_mem_ras_n => HPS_DDR3_RAS_n,
hps_ddr_mem_cas_n => HPS_DDR3_CAS_n,
hps_ddr_mem_we_n => HPS_DDR3_WE_n,
hps_ddr_mem_reset_n => HPS_DDR3_RESET_n,
hps_ddr_mem_dq => HPS_DDR3_DQ,
hps_ddr_mem_dqs => HPS_DDR3_DQS_p,
hps_ddr_mem_dqs_n => HPS_DDR3_DQS_n,
hps_ddr_mem_odt => HPS_DDR3_ODT,
hps_ddr_mem_dm => HPS_DDR3_DM,
hps_ddr_oct_rzqin => HPS_DDR3_RZQ,
hps_f2h_irq0_irq => (others => 'X'),
hps_f2h_irq1_irq => (others => 'X'),
hps_f2h_stm_hw_events_stm_hwevents => (others => 'X'),
hps_h2f_axi_master_awid => h2f.awid(11 downto 0),--er.awid
hps_h2f_axi_master_awaddr => h2f.awaddr(29 downto 0),--.awaddr
hps_h2f_axi_master_awlen => h2f.awlen,-- .awlen
hps_h2f_axi_master_awsize => h2f.awsize,--.awsize
hps_h2f_axi_master_awburst => h2f.awburst,--awburst
hps_h2f_axi_master_awlock => h2f.awlock,--.awlock
hps_h2f_axi_master_awcache => h2f.awcache,--awcache
hps_h2f_axi_master_awprot => h2f.awprot,--.awprot
hps_h2f_axi_master_awvalid => h2f.awvalid,--awvalid
hps_h2f_axi_master_awready => h2f.wready,--wready
hps_h2f_axi_master_wid => h2f.wid(11 downto 0),-- .wid
hps_h2f_axi_master_wdata => h2f.wdata(31 downto 0),-- .wdata
hps_h2f_axi_master_wstrb => h2f.wstrb(3 downto 0),-- .wstrb
hps_h2f_axi_master_wlast => h2f.wlast,-- .wlast
hps_h2f_axi_master_wvalid => h2f.wvalid,--.wvalid
hps_h2f_axi_master_wready => h2f.wready,--wready
hps_h2f_axi_master_bid => h2f.bid(11 downto 0),-- .bid
hps_h2f_axi_master_bresp => h2f.bresp,-- .bresp
hps_h2f_axi_master_bvalid => h2f.bvalid,--bvalid
hps_h2f_axi_master_bready => h2f.bready,--.bready
hps_h2f_axi_master_arid => h2f.arid(11 downto 0),-- .arid
hps_h2f_axi_master_araddr => h2f.araddr(29 downto 0),--.araddr
hps_h2f_axi_master_arlen => h2f.arlen,-- .arlen
hps_h2f_axi_master_arsize => h2f.arsize,--.arsize
hps_h2f_axi_master_arburst => h2f.arburst,--arburst
hps_h2f_axi_master_arlock => h2f.arlock,-- .arlock
hps_h2f_axi_master_arcache => h2f.arcache,--arcache
hps_h2f_axi_master_arprot => h2f.arprot,--.arprot
hps_h2f_axi_master_arvalid => h2f.arvalid,--arvalid
hps_h2f_axi_master_arready => h2f.rready,--rready
hps_h2f_axi_master_rid => h2f.rid(11 downto 0),-- .rid
hps_h2f_axi_master_rdata => h2f.rdata(31 downto 0),-- .rdata
hps_h2f_axi_master_rresp => h2f.rresp,-- .rresp
hps_h2f_axi_master_rlast => h2f.rlast,--.rlast
hps_h2f_axi_master_rvalid => h2f.rvalid,--rvalid
hps_h2f_axi_master_rready => h2f.rready, --rready
hps_h2f_lw_axi_master_awid => open,
hps_h2f_lw_axi_master_awaddr => open,
hps_h2f_lw_axi_master_awlen => open,
hps_h2f_lw_axi_master_awsize => open,
hps_h2f_lw_axi_master_awburst => open,
hps_h2f_lw_axi_master_awlock => open,
hps_h2f_lw_axi_master_awcache => open,
hps_h2f_lw_axi_master_awprot => open,
hps_h2f_lw_axi_master_awvalid => open,
hps_h2f_lw_axi_master_awready => '0',
hps_h2f_lw_axi_master_wid => open,
hps_h2f_lw_axi_master_wdata => open,
hps_h2f_lw_axi_master_wstrb => open,
hps_h2f_lw_axi_master_wlast => open,
hps_h2f_lw_axi_master_wvalid => open,
hps_h2f_lw_axi_master_wready => '0',
hps_h2f_lw_axi_master_bid => (others => '0'),
hps_h2f_lw_axi_master_bresp => (others => '0'),
hps_h2f_lw_axi_master_bvalid => '0',
hps_h2f_lw_axi_master_bready => open,
hps_h2f_lw_axi_master_arid => open,
hps_h2f_lw_axi_master_araddr => open,
hps_h2f_lw_axi_master_arlen => open,
hps_h2f_lw_axi_master_arsize => open,
hps_h2f_lw_axi_master_arburst => open,
hps_h2f_lw_axi_master_arlock => open,
hps_h2f_lw_axi_master_arcache => open,
hps_h2f_lw_axi_master_arprot => open,
hps_h2f_lw_axi_master_arvalid => open,
hps_h2f_lw_axi_master_arready => '0',
hps_h2f_lw_axi_master_rid => (others => '0'),
hps_h2f_lw_axi_master_rdata => (others => '0'),
hps_h2f_lw_axi_master_rresp => (others => '0'),
hps_h2f_lw_axi_master_rlast => '0',
hps_h2f_lw_axi_master_rvalid => '0',
hps_h2f_lw_axi_master_rready => open,
hps_h2f_reset_reset_n => hpsrst,
reset_reset_n => rstn,
hps_f2h_axi_slave_awid => f2h.awid(7 downto 0),--er.awid
hps_f2h_axi_slave_awaddr => f2h.awaddr(31 downto 0),--.awaddr
hps_f2h_axi_slave_awlen => f2h.awlen,-- .awlen
hps_f2h_axi_slave_awsize => f2h.awsize,--.awsize
hps_f2h_axi_slave_awburst => f2h.awburst,--awburst
hps_f2h_axi_slave_awlock => f2h.awlock,--.awlock
hps_f2h_axi_slave_awcache => f2h.awcache,--awcache
hps_f2h_axi_slave_awprot => f2h.awprot,--.awprot
hps_f2h_axi_slave_awvalid => f2h.awvalid,--awvalid
hps_f2h_axi_slave_awready => f2h.awready,--wready
hps_f2h_axi_slave_wid => f2h.wid(7 downto 0),-- .wid
hps_f2h_axi_slave_wdata => f2h.wdata,-- .wdata
hps_f2h_axi_slave_wstrb => f2h.wstrb,-- .wstrb
hps_f2h_axi_slave_wlast => f2h.wlast,-- .wlast
hps_f2h_axi_slave_wvalid => f2h.wvalid,--.wvalid
hps_f2h_axi_slave_wready => f2h.wready,--wready
hps_f2h_axi_slave_bid => f2h.bid(7 downto 0),-- .bid
hps_f2h_axi_slave_bresp => f2h.bresp,-- .bresp
hps_f2h_axi_slave_bvalid => f2h.bvalid,--bvalid
hps_f2h_axi_slave_bready => f2h.bready,--.bready
hps_f2h_axi_slave_arid => f2h.arid(7 downto 0),-- .arid
hps_f2h_axi_slave_araddr => f2h.araddr(31 downto 0),--.araddr
hps_f2h_axi_slave_arlen => f2h.arlen,-- .arlen
hps_f2h_axi_slave_arsize => f2h.arsize,--.arsize
hps_f2h_axi_slave_arburst => f2h.arburst,--arburst
hps_f2h_axi_slave_arlock => f2h.arlock,-- .arlock
hps_f2h_axi_slave_arcache => f2h.arcache,--arcache
hps_f2h_axi_slave_arprot => f2h.arprot,--.arprot
hps_f2h_axi_slave_arvalid => f2h.arvalid,--arvalid
hps_f2h_axi_slave_arready => f2h.arready,--rready
hps_f2h_axi_slave_rid => f2h.rid(7 downto 0),-- .rid
hps_f2h_axi_slave_rdata => f2h.rdata,-- .rdata
hps_f2h_axi_slave_rresp => f2h.rresp,-- .rresp
hps_f2h_axi_slave_rlast => f2h.rlast,--.rlast
hps_f2h_axi_slave_rvalid => f2h.rvalid,--rvalid
hps_f2h_axi_slave_rready => f2h.rready --rready
);
-----------------------------------------------------------------------------
-- Other
-----------------------------------------------------------------------------
-- pragma translate_off
rep: if USE_AHBREP/=0 generate
ahbrep0: ahbrep
generic map (hindex => hsi_ahbrep, haddr => 16#200#)
port map (rstn,clkm,ahbsi,ahbso(hsi_ahbrep));
end generate;
x : report_version
generic map (
msg1 => "LEON3 Altera Cyclone V SX SoC Terasic Sockit Demonstration design",
msg2 => "GRLIB Version " & tost(LIBVHDL_VERSION/1000) & "." & tost((LIBVHDL_VERSION mod 1000)/100)
& "." & tost(LIBVHDL_VERSION mod 100) & ", build " & tost(LIBVHDL_BUILD),
msg3 => "Target technology: " & tech_table(fabtech) & ", memory library: " & tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
| gpl-3.0 | 3008cd128306c9076e0e971e3819770a | 0.454939 | 3.432279 | false | false | false | false |
EliasLuiz/TCC | Teste/MemoTableTNPCTagWay.vhd | 1 | 10,445 | -- megafunction wizard: %RAM: 2-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: MemoTableTNPCTag.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
use work.Constants.all;
use work.DefTypes.all;
ENTITY MemoTableTNPCTagWay IS
--ENTITY TraceMemory IS
PORT
(
Clock : IN STD_LOGIC := '1';
WAddress : IN STD_LOGIC_VECTOR (MemoTableTWayAddressLenght-1 DOWNTO 0);
WData : IN MemoTableTNPCTagEntry;
--WData : IN STD_LOGIC_VECTOR (MemoTableTNPCTagEntryWidth-1 DOWNTO 0);
WEnable : IN STD_LOGIC := '0';
RAddress : IN STD_LOGIC_VECTOR (MemoTableTWayAddressLenght-1 DOWNTO 0);
RData : OUT MemoTableTNPCTagEntry
--RData : OUT STD_LOGIC_VECTOR (MemoTableTNPCTagEntryWidth-1 DOWNTO 0)
);
END MemoTableTNPCTagWay;
--END TraceMemory;
ARCHITECTURE SYN OF MemoTableTNPCTagWay IS
--ARCHITECTURE SYN OF TraceMemory IS
SIGNAL RAuxVector : STD_LOGIC_VECTOR (MemoTableTNPCTagEntryWidth-1 DOWNTO 0);
SIGNAL WAuxObject : MemoTableTNPCTagEntry;
SIGNAL WAuxVector : STD_LOGIC_VECTOR (MemoTableTNPCTagEntryWidth-1 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
address_reg_b : STRING;
clock_enable_input_a : STRING;
clock_enable_input_b : STRING;
clock_enable_output_a : STRING;
clock_enable_output_b : STRING;
intended_device_family : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
numwords_b : NATURAL;
operation_mode : STRING;
outdata_aclr_b : STRING;
outdata_reg_b : STRING;
power_up_uninitialized : STRING;
read_during_write_mode_mixed_ports : STRING;
widthad_a : NATURAL;
widthad_b : NATURAL;
width_a : NATURAL;
width_b : NATURAL;
width_byteena_a : NATURAL
);
PORT (
address_a: IN STD_LOGIC_VECTOR (MemoTableTWayAddressLenght-1 DOWNTO 0);
clock0 : IN STD_LOGIC;
data_a : IN STD_LOGIC_VECTOR (MemoTableTNPCTagEntryWidth-1 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (MemoTableTNPCTagEntryWidth-1 DOWNTO 0);
wren_a : IN STD_LOGIC;
address_b: IN STD_LOGIC_VECTOR (MemoTableTWayAddressLenght-1 DOWNTO 0)
);
END COMPONENT;
BEGIN
--RData <= RAuxVector;
RData <= StdLogicToNPCTag(RAuxVector);
--WAuxVector <= WData;
WAuxObject.Valid <= '1';
WAuxObject.NPC <= WData.NPC;
WAuxObject.Tag <= WData.Tag;
WAuxVector <= NPCTagToStdLogic(WAuxObject);
altsyncram_component : altsyncram
GENERIC MAP (
address_reg_b => "CLOCK0",
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
intended_device_family => "Cyclone II",
lpm_type => "altsyncram",
numwords_a => MemoTableTWayLenght,
numwords_b => MemoTableTWayLenght,
operation_mode => "DUAL_PORT",
outdata_aclr_b => "NONE",
outdata_reg_b => "CLOCK0",
power_up_uninitialized => "FALSE",
read_during_write_mode_mixed_ports => "DONT_CARE",
widthad_a => MemoTableTWayAddressLenght,
widthad_b => MemoTableTWayAddressLenght,
width_a => MemoTableTNPCTagEntryWidth,
width_b => MemoTableTNPCTagEntryWidth,
width_byteena_a => 1
)
PORT MAP (
address_a => WAddress,
clock0 => Clock,
data_a => WAuxVector,
wren_a => WEnable,
address_b => RAddress,
q_b => RAuxVector
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
-- Retrieval info: PRIVATE: CLRq NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "4096"
-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "1"
-- Retrieval info: PRIVATE: MIFfilename STRING ""
-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
-- Retrieval info: PRIVATE: REGq NUMERIC "1"
-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGrren NUMERIC "1"
-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "1"
-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
-- Retrieval info: PRIVATE: VarWidth NUMERIC "0"
-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "64"
-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "64"
-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "64"
-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "64"
-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: enable NUMERIC "0"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "64"
-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "64"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "6"
-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "6"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "64"
-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "64"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: data 0 0 64 0 INPUT NODEFVAL "data[MemoTableTNPCTagEntryWidth-1..0]"
-- Retrieval info: USED_PORT: q 0 0 64 0 OUTPUT NODEFVAL "q[MemoTableTNPCTagEntryWidth-1..0]"
-- Retrieval info: USED_PORT: rdaddress 0 0 6 0 INPUT NODEFVAL "rdaddress[MemoTableTWayAddressLenght-1..0]"
-- Retrieval info: USED_PORT: wraddress 0 0 6 0 INPUT NODEFVAL "wraddress[MemoTableTWayAddressLenght-1..0]"
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
-- Retrieval info: CONNECT: @address_a 0 0 6 0 wraddress 0 0 6 0
-- Retrieval info: CONNECT: @address_b 0 0 6 0 rdaddress 0 0 6 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 64 0 data 0 0 64 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 64 0 @q_b 0 0 64 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL MemoTableTNPCTag.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL MemoTableTNPCTag.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL MemoTableTNPCTag.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL MemoTableTNPCTag.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL MemoTableTNPCTag_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL MemoTableTNPCTag_syn.v TRUE
-- Retrieval info: LIB_FILE: altera_mf
| gpl-3.0 | 41cc9f18548d78d495eddfcece82ec5d | 0.69842 | 3.340262 | false | false | false | false |
NeuroML/org.neuroml.export | src/main/resources/vhdl/ParamPow_TB.vhd | 1 | 2,223 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library ieee_proposed;
use ieee_proposed.fixed_pkg.all;
use ieee_proposed.fixed_float_types.ALL;
use std.textio.all;
use ieee.std_logic_textio.all; -- if you're saving this type of signal
entity parampow_tb is
end parampow_tb;
architecture tb of parampow_tb is
component ParamPow is
generic(
BIT_TOP : integer := 11;
BIT_BOTTOM : integer := -12);
port(
clk : In Std_logic;
rst : In Std_logic;
Start : In Std_logic;
Done : Out Std_logic;
A : In sfixed(BIT_TOP downto BIT_BOTTOM);
X : In sfixed(BIT_TOP downto BIT_BOTTOM);
Output : Out sfixed(BIT_TOP downto BIT_BOTTOM)
);
end component;
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal Start : std_logic := '0';
signal Done : std_logic := '0';
signal X : sfixed(11 downto -12);
signal A : sfixed(11 downto -12);
signal Output : sfixed(11 downto -12);
begin
ParamPow_uut : ParamPow
generic map(
BIT_TOP => 11,
BIT_BOTTOM => -12
)
port map ( clk => clk,
rst => rst,
Start => Start,
Done => Done,
X => X,
A => A,
Output => Output
);
process
begin
wait for 10ns;
clk <= not(clk);
wait for 10ns;
clk <= not(clk);
end process;
process (Done)
begin
if Done'event and Done = '1' then
report "The value of " & real'image(to_real(A)) & "^" & real'image(to_real(X))& " = " & real'image(to_real(Output));
end if;
end process;
process
begin
-- wait for Reset to complete
-- wait until rst='1';
rst<='1';
wait for 40 ns;
rst<='0';
wait for 40 ns;
A <= to_sfixed(2.5,11,-12);
X <= to_sfixed(1,11,-12);
Start <= '1';
wait for 20 ns;
Start <= '0';
wait for 200 ns;
X <= to_sfixed(2,11,-12);
Start <= '1';
wait for 20 ns;
Start <= '0';
wait for 200 ns;
X <= to_sfixed(3,11,-12);
Start <= '1';
wait for 20 ns;
Start <= '0';
wait for 200 ns;
X <= to_sfixed(4,11,-12);
Start <= '1';
wait for 20 ns;
Start <= '0';
wait for 200 ns;
X <= to_sfixed(5,11,-12);
Start <= '1';
wait for 20 ns;
Start <= '0';
wait for 200 ns;
end process;
end tb;
| lgpl-3.0 | 066485db4b608927d48f2701e3cc815f | 0.577148 | 2.688029 | false | false | false | false |
pwsoft/fpga_examples | rtl/ttl/ttl_7408.vhd | 1 | 2,371 | -- -----------------------------------------------------------------------
--
-- Syntiac VHDL support files.
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2018 by Peter Wendrich ([email protected])
-- http://www.syntiac.com
--
-- This source file is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- -----------------------------------------------------------------------
-- Quad 2-input AND gate
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use work.ttl_pkg.all;
-- -----------------------------------------------------------------------
entity ttl_7408 is
generic (
latency : integer := 1
);
port (
emuclk : in std_logic;
p1 : in ttl_t;
p2 : in ttl_t;
p3 : out ttl_t;
p4 : in ttl_t;
p5 : in ttl_t;
p6 : out ttl_t;
p8 : out ttl_t;
p9 : in ttl_t;
p10 : in ttl_t;
p11 : out ttl_t;
p12 : in ttl_t;
p13 : in ttl_t
);
end entity;
architecture rtl of ttl_7408 is
signal p3_loc : ttl_t;
signal p6_loc : ttl_t;
signal p8_loc : ttl_t;
signal p11_loc : ttl_t;
begin
p3_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p3_loc, q => p3);
p6_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p6_loc, q => p6);
p8_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p8_loc, q => p8);
p11_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p11_loc, q => p11);
p3_loc <= p1 and p2;
p6_loc <= p4 and p5;
p8_loc <= p9 and p10;
p11_loc <= p12 and p13;
end architecture;
| lgpl-2.1 | 8ec8fa98a7645f935aea725949032317 | 0.561788 | 3.283934 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-digilent-nexys3/config.vhd | 1 | 8,129 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := spartan6;
constant CFG_MEMTECH : integer := spartan6;
constant CFG_PADTECH : integer := spartan6;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := spartan6;
constant CFG_CLKMUL : integer := (5);
constant CFG_CLKDIV : integer := (10);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 0;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 1;
constant CFG_NWP : integer := (0);
constant CFG_PWD : integer := 0*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 4;
constant CFG_IREPL : integer := 2;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 2;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0 + 0*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 0;
constant CFG_ITLBNUM : integer := 2;
constant CFG_DTLBNUM : integer := 2;
constant CFG_TLB_TYPE : integer := 1 + 0*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2 + 64*0;
constant CFG_ATBSZ : integer := 2;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_STAT_ENABLE : integer := 0;
constant CFG_STAT_CNT : integer := 1;
constant CFG_STAT_NMAX : integer := 0;
constant CFG_STAT_DSUEN : integer := 0;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
constant CFG_ALTWIN : integer := 0;
constant CFG_REX : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 1;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000000#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 1;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- DDR controller
constant CFG_DDR2SP : integer := 0;
constant CFG_DDR2SP_INIT : integer := 0;
constant CFG_DDR2SP_FREQ : integer := 100;
constant CFG_DDR2SP_TRFC : integer := 130;
constant CFG_DDR2SP_DATAWIDTH : integer := 64;
constant CFG_DDR2SP_FTEN : integer := 0;
constant CFG_DDR2SP_FTWIDTH : integer := 0;
constant CFG_DDR2SP_COL : integer := 9;
constant CFG_DDR2SP_SIZE : integer := 8;
constant CFG_DDR2SP_DELAY0 : integer := 0;
constant CFG_DDR2SP_DELAY1 : integer := 0;
constant CFG_DDR2SP_DELAY2 : integer := 0;
constant CFG_DDR2SP_DELAY3 : integer := 0;
constant CFG_DDR2SP_DELAY4 : integer := 0;
constant CFG_DDR2SP_DELAY5 : integer := 0;
constant CFG_DDR2SP_DELAY6 : integer := 0;
constant CFG_DDR2SP_DELAY7 : integer := 0;
constant CFG_DDR2SP_NOSYNC : integer := 0;
-- Xilinx MIG
constant CFG_MIG_DDR2 : integer := 1;
constant CFG_MIG_RANKS : integer := (1);
constant CFG_MIG_COLBITS : integer := (10);
constant CFG_MIG_ROWBITS : integer := (13);
constant CFG_MIG_BANKBITS: integer := (2);
constant CFG_MIG_HMASK : integer := 16#F00#;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 4;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 1;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 0;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := 1;
-- SPI memory controller
constant CFG_SPIMCTRL : integer := 0;
constant CFG_SPIMCTRL_SDCARD : integer := 0;
constant CFG_SPIMCTRL_READCMD : integer := 16#0#;
constant CFG_SPIMCTRL_DUMMYBYTE : integer := 0;
constant CFG_SPIMCTRL_DUALOUTPUT : integer := 0;
constant CFG_SPIMCTRL_SCALER : integer := 1;
constant CFG_SPIMCTRL_ASCALER : integer := 1;
constant CFG_SPIMCTRL_PWRUPCNT : integer := 0;
constant CFG_SPIMCTRL_OFFSET : integer := 16#0#;
-- SPI controller
constant CFG_SPICTRL_ENABLE : integer := 0;
constant CFG_SPICTRL_NUM : integer := 1;
constant CFG_SPICTRL_SLVS : integer := 1;
constant CFG_SPICTRL_FIFO : integer := 1;
constant CFG_SPICTRL_SLVREG : integer := 0;
constant CFG_SPICTRL_ODMODE : integer := 0;
constant CFG_SPICTRL_AM : integer := 0;
constant CFG_SPICTRL_ASEL : integer := 0;
constant CFG_SPICTRL_TWEN : integer := 0;
constant CFG_SPICTRL_MAXWLEN : integer := 0;
constant CFG_SPICTRL_SYNCRAM : integer := 0;
constant CFG_SPICTRL_FT : integer := 0;
-- GRLIB debugging
constant CFG_DUART : integer := 1;
end;
| gpl-3.0 | e7ab44ec1dd533c3cd8adb519219dd83 | 0.653955 | 3.571617 | false | false | false | false |
hoglet67/CoPro6502 | src/DCM/dcm_32_12.vhd | 1 | 2,065 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity dcm_32_12 is
port (CLKIN_IN : in std_logic;
CLK0_OUT : out std_logic;
CLK0_OUT1 : out std_logic;
CLK2X_OUT : out std_logic);
end dcm_32_12;
architecture BEHAVIORAL of dcm_32_12 is
signal CLKFX_BUF : std_logic;
signal CLKIN_IBUFG : std_logic;
signal GND_BIT : std_logic;
begin
GND_BIT <= '0';
CLKFX_BUFG_INST : BUFG
port map (I => CLKFX_BUF, O => CLK0_OUT);
DCM_INST : DCM
generic map(CLK_FEEDBACK => "NONE",
CLKDV_DIVIDE => 4.0, -- 12.000 = 32.000 * 6/16
CLKFX_DIVIDE => 16,
CLKFX_MULTIPLY => 6,
CLKIN_DIVIDE_BY_2 => false,
CLKIN_PERIOD => 31.25,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => true,
FACTORY_JF => x"C080",
PHASE_SHIFT => 0,
STARTUP_WAIT => false)
port map (CLKFB => GND_BIT,
CLKIN => CLKIN_IN,
DSSEN => GND_BIT,
PSCLK => GND_BIT,
PSEN => GND_BIT,
PSINCDEC => GND_BIT,
RST => GND_BIT,
CLKDV => open,
CLKFX => CLKFX_BUF,
CLKFX180 => open,
CLK0 => open,
CLK2X => open,
CLK2X180 => open,
CLK90 => open,
CLK180 => open,
CLK270 => open,
LOCKED => open,
PSDONE => open,
STATUS => open);
end BEHAVIORAL;
| gpl-3.0 | a262b725328df4ddf20272a0a352f093 | 0.404843 | 4.231557 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-gr-cpci-xc4v/testbench.vhd | 1 | 17,742 | ------------------------------------------------------------------------------
-- LEON Demonstration design test bench
-- Copyright (C) 2004 - 2015 Cobham Gaisler AB
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
use work.debug.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20; -- system clock period
romwidth : integer := 32; -- rom data width (8/32)
romdepth : integer := 16; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 20; -- ram address depth
srambanks : integer := 2 -- number of ram banks
);
port (
pci_rst : inout std_logic; -- PCI bus
pci_clk : in std_logic;
pci_gnt : in std_logic;
pci_idsel : in std_logic;
pci_lock : inout std_logic;
pci_ad : inout std_logic_vector(31 downto 0);
pci_cbe : inout std_logic_vector(3 downto 0);
pci_frame : inout std_logic;
pci_irdy : inout std_logic;
pci_trdy : inout std_logic;
pci_devsel : inout std_logic;
pci_stop : inout std_logic;
pci_perr : inout std_logic;
pci_par : inout std_logic;
pci_req : inout std_logic;
pci_serr : inout std_logic;
pci_host : in std_logic := '1';
pci_int : inout std_logic_vector(3 downto 0);
pci_66 : in std_logic := '0'
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal clk : std_logic := '0';
signal rst : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal address : std_logic_vector(27 downto 0);
signal data : std_logic_vector(31 downto 0);
signal cb, scb : std_logic_vector(15 downto 0);
signal ramsn : std_logic_vector(4 downto 0);
signal ramoen : std_logic_vector(4 downto 0);
signal rwen : std_logic_vector(3 downto 0);
signal rwenx : std_logic_vector(3 downto 0);
signal romsn : std_logic_vector(1 downto 0);
signal iosn : std_logic;
signal oen : std_logic;
signal read : std_logic;
signal writen : std_logic;
signal brdyn : std_logic;
signal bexcn : std_logic;
signal wdogn : std_logic;
signal dsuen, dsutx, dsurx, dsubre, dsuact : std_logic;
signal dsurst : std_logic;
signal test : std_logic;
signal error : std_logic;
signal gpio : std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
signal GND : std_logic := '0';
signal VCC : std_logic := '1';
signal NC : std_logic := 'Z';
signal clk2 : std_logic := '1';
signal sdcke : std_logic_vector ( 1 downto 0); -- clk en
signal sdcsn : std_logic_vector ( 1 downto 0); -- chip sel
signal sdwen : std_logic; -- write en
signal sdrasn : std_logic; -- row addr stb
signal sdcasn : std_logic; -- col addr stb
signal sddqm : std_logic_vector ( 7 downto 0); -- data i/o mask
signal sdclk : std_logic;
signal plllock : std_logic;
signal txd1, rxd1, cts1, rts1 : std_ulogic;
signal txd2, rxd2, cts2, rts2 : std_ulogic;
signal etx_clk, erx_clk, erx_dv, erx_er, erx_col, erx_crs, etx_en, etx_er : std_logic:='0';
signal erxd, etxd: std_logic_vector(3 downto 0):=(others=>'0');
signal erxdt, etxdt: std_logic_vector(7 downto 0):=(others=>'0');
signal emdc, emdio: std_logic;
signal gtx_clk : std_logic := '0';
signal emdintn : std_logic;
signal emddis : std_logic;
signal epwrdwn : std_logic;
signal ereset : std_logic;
signal esleep : std_logic;
signal epause : std_logic;
signal led_cfg: std_logic_vector(2 downto 0);
constant lresp : boolean := false;
signal sa : std_logic_vector(14 downto 0);
signal sd : std_logic_vector(63 downto 0);
signal pci_arb_req, pci_arb_gnt : std_logic_vector(0 to 3);
signal can_txd : std_logic_vector(0 to CFG_CAN_NUM-1);
signal can_rxd : std_logic_vector(0 to CFG_CAN_NUM-1);
signal can_stb : std_logic;
signal spw_clk : std_logic := '0';
signal spw_rxdp : std_logic_vector(0 to CFG_SPW_NUM-1) := (others => '0');
signal spw_rxdn : std_logic_vector(0 to CFG_SPW_NUM-1) := (others => '0');
signal spw_rxsp : std_logic_vector(0 to CFG_SPW_NUM-1) := (others => '0');
signal spw_rxsn : std_logic_vector(0 to CFG_SPW_NUM-1) := (others => '0');
signal spw_txdp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_txdn : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_txsp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_txsn : std_logic_vector(0 to CFG_SPW_NUM-1);
begin
-- clock and reset
clk <= not clk after ct * 1 ns;
spw_clk <= not spw_clk after 10 ns;
rst <= dsurst;
dsuen <= '1'; dsubre <= '0'; rxd1 <= '1';
led_cfg<="000"; --put the phy in base10h mode
can_rxd <= (others => 'H'); bexcn <= '1'; wdogn <= 'H';
gpio(2 downto 0) <= "LHL";
gpio(CFG_GRGPIO_WIDTH-1 downto 3) <= (others => 'H');
pci_arb_req <= "HHHH";
-- spacewire loop-back
spw_rxdp <= spw_txdp; spw_rxdn <= spw_txdn;
spw_rxsp <= spw_txsp; spw_rxsn <= spw_txsn;
d3 : entity work.leon3mp
generic map ( fabtech, memtech, padtech, clktech, disas, dbguart, pclow )
port map (rst, clk, sdclk, error, wdogn, address(27 downto 0), data,
cb(7 downto 0), sa, sd,
-- scb(7 downto 0),
sdclk, sdcke, sdcsn, sdwen,
sdrasn, sdcasn, sddqm, dsutx, dsurx, dsuen, dsubre, dsuact,
txd1, rxd1, rts1, cts1, txd2, rxd2, rts2, cts2,
ramsn, ramoen, rwen, oen, writen, read, iosn, romsn, brdyn, bexcn, gpio,
emdio, etx_clk, erx_clk, erxd, erx_dv, erx_er, erx_col, erx_crs,
etxd, etx_en, etx_er, emdc, emdintn,
pci_rst, pci_clk, pci_gnt, pci_idsel, pci_lock, pci_ad, pci_cbe,
pci_frame, pci_irdy, pci_trdy, pci_devsel, pci_stop, pci_perr, pci_par,
pci_req, pci_serr, pci_host, pci_int, pci_66, pci_arb_req, pci_arb_gnt,
can_txd, can_rxd,
spw_clk, spw_rxdp, spw_rxdn, spw_rxsp, spw_rxsn, spw_txdp,
spw_txdn, spw_txsp, spw_txsn
);
-- optional sdram
sd0 : if ((CFG_MCTRL_SDEN = 1) and (CFG_MCTRL_SEPBUS = 0)) or ((CFG_MCTRLFT_SDEN = 1) and (CFG_MCTRLFT_SEPBUS = 0)) generate
u0: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => data(31 downto 16), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u1: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => data(15 downto 0), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
cb0: ftmt48lc16m16a2 generic map (index => 8, fname => sdramfile)
PORT MAP(
Dq => cb(15 downto 0), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
u2: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => data(31 downto 16), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u3: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => data(15 downto 0), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
cb1: ftmt48lc16m16a2 generic map (index => 8, fname => sdramfile)
PORT MAP(
Dq => cb(15 downto 0), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
end generate;
sd1 : if ((CFG_MCTRL_SDEN = 1) and (CFG_MCTRL_SEPBUS = 1)) or ((CFG_MCTRLFT_SDEN = 1) and (CFG_MCTRLFT_SEPBUS = 1)) generate
u0: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sd(31 downto 16), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u1: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sd(15 downto 0), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
cb0: ftmt48lc16m16a2 generic map (index => 8, fname => sdramfile)
PORT MAP(
Dq => sd(47 downto 32), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
u2: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sd(31 downto 16), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(1),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u3: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sd(15 downto 0), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(1),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
cb1: ftmt48lc16m16a2 generic map (index => 8, fname => sdramfile)
PORT MAP(
Dq => sd(47 downto 32), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(1),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
sd64 : if (CFG_MCTRL_SD64 = 1) generate
u4: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sd(63 downto 48), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(7 downto 6));
u5: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sd(47 downto 32), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(5 downto 4));
u6: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sd(63 downto 48), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(7 downto 6));
u7: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sd(47 downto 32), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(5 downto 4));
end generate;
end generate;
prom0 : for i in 0 to (romwidth/8)-1 generate
sr0 : sram generic map (index => i, abits => romdepth, fname => promfile)
port map (address(romdepth+1 downto 2), data(31-i*8 downto 24-i*8), romsn(0),
rwen(i), oen);
end generate;
sram0 : for i in 0 to (sramwidth/8)-1 generate
sr0 : sram generic map (index => i, abits => sramdepth, fname => sramfile)
port map (address(sramdepth+1 downto 2), data(31-i*8 downto 24-i*8), ramsn(0),
rwen(0), ramoen(0));
end generate;
sramcb0 : sramft generic map (index => 7, abits => sramdepth, fname => sramfile)
port map (address(sramdepth+1 downto 2), cb(7 downto 0), ramsn(0), rwen(0), ramoen(0));
phy0 : if (CFG_GRETH = 1) generate
emdio <= 'H';
erxd <= erxdt(3 downto 0);
etxdt <= "0000" & etxd;
p0: phy
generic map(base1000_t_fd => 0, base1000_t_hd => 0)
port map(rst, emdio, etx_clk, erx_clk, erxdt, erx_dv,
erx_er, erx_col, erx_crs, etxdt, etx_en, etx_er, emdc, gtx_clk);
end generate;
error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 2500 ns;
if to_x01(error) = '1' then wait on error; end if;
assert (to_x01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
test0 : grtestmod
port map ( rst, clk, error, address(21 downto 2), data,
iosn, oen, writen, brdyn);
-- data <= buskeep(data), (others => 'H') after 250 ns;
data <= buskeep(data) after 5 ns;
-- sd <= buskeep(sd), (others => 'H') after 250 ns;
sd <= buskeep(sd) after 5 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_logic; signal dsutx : out std_logic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
wait for 500 ns;
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#02#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#24#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#03#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#fc#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#6f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#11#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#04#, txp);
txa(dsutx, 16#00#, 16#02#, 16#20#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#02#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#43#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end ;
| gpl-3.0 | ca58878597dfc3bee1e66c61e1e107a7 | 0.570849 | 3.061077 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/misc/charrom.vhd | 1 | 119,270 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: charrom
-- File: charrom.vhd
-- Author: Marcus Hellqvist
-- Description: Character ROM for video controller
-----------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
entity charrom is
port(
clk : in std_ulogic;
addr : in std_logic_vector(11 downto 0);
data : out std_logic_vector(7 downto 0)
);
end entity;
architecture rtl of charrom is
signal romdata : std_logic_vector(7 downto 0);
signal romaddr : std_logic_vector(11 downto 0);
begin
data <= romdata;
p0: process(clk)
begin
if rising_edge(clk) then
romaddr <= addr;
end if;
end process;
p1: process(romaddr)
begin
case conv_integer(romaddr) is
when 16#000# => romdata <= X"00"; --
when 16#100# => romdata <= X"00"; --
when 16#200# => romdata <= X"00"; --
when 16#300# => romdata <= X"00"; --
when 16#400# => romdata <= X"00"; --
when 16#500# => romdata <= X"00"; --
when 16#600# => romdata <= X"00"; --
when 16#700# => romdata <= X"00"; --
when 16#800# => romdata <= X"00"; --
when 16#900# => romdata <= X"00"; --
when 16#a00# => romdata <= X"00"; --
when 16#b00# => romdata <= X"00"; --
when 16#c00# => romdata <= X"00"; --
when 16#020# => romdata <= X"00"; --
when 16#120# => romdata <= X"00"; --
when 16#220# => romdata <= X"00"; --
when 16#320# => romdata <= X"00"; --
when 16#420# => romdata <= X"00"; --
when 16#520# => romdata <= X"00"; --
when 16#620# => romdata <= X"00"; --
when 16#720# => romdata <= X"00"; --
when 16#820# => romdata <= X"00"; --
when 16#920# => romdata <= X"00"; --
when 16#a20# => romdata <= X"00"; --
when 16#b20# => romdata <= X"00"; --
when 16#c20# => romdata <= X"00"; --
when 16#021# => romdata <= X"00"; -- !
when 16#121# => romdata <= X"00"; -- !
when 16#221# => romdata <= X"10"; -- !
when 16#321# => romdata <= X"10"; -- !
when 16#421# => romdata <= X"10"; -- !
when 16#521# => romdata <= X"10"; -- !
when 16#621# => romdata <= X"10"; -- !
when 16#721# => romdata <= X"10"; -- !
when 16#821# => romdata <= X"10"; -- !
when 16#921# => romdata <= X"00"; -- !
when 16#a21# => romdata <= X"10"; -- !
when 16#b21# => romdata <= X"00"; -- !
when 16#c21# => romdata <= X"00"; -- !
when 16#022# => romdata <= X"00"; -- "
when 16#122# => romdata <= X"00"; -- "
when 16#222# => romdata <= X"24"; -- "
when 16#322# => romdata <= X"24"; -- "
when 16#422# => romdata <= X"24"; -- "
when 16#522# => romdata <= X"00"; -- "
when 16#622# => romdata <= X"00"; -- "
when 16#722# => romdata <= X"00"; -- "
when 16#822# => romdata <= X"00"; -- "
when 16#922# => romdata <= X"00"; -- "
when 16#a22# => romdata <= X"00"; -- "
when 16#b22# => romdata <= X"00"; -- "
when 16#c22# => romdata <= X"00"; -- "
when 16#023# => romdata <= X"00"; -- #
when 16#123# => romdata <= X"00"; -- #
when 16#223# => romdata <= X"00"; -- #
when 16#323# => romdata <= X"24"; -- #
when 16#423# => romdata <= X"24"; -- #
when 16#523# => romdata <= X"7e"; -- #
when 16#623# => romdata <= X"24"; -- #
when 16#723# => romdata <= X"7e"; -- #
when 16#823# => romdata <= X"24"; -- #
when 16#923# => romdata <= X"24"; -- #
when 16#a23# => romdata <= X"00"; -- #
when 16#b23# => romdata <= X"00"; -- #
when 16#c23# => romdata <= X"00"; -- #
when 16#024# => romdata <= X"00"; -- $
when 16#124# => romdata <= X"00"; -- $
when 16#224# => romdata <= X"10"; -- $
when 16#324# => romdata <= X"3c"; -- $
when 16#424# => romdata <= X"50"; -- $
when 16#524# => romdata <= X"50"; -- $
when 16#624# => romdata <= X"38"; -- $
when 16#724# => romdata <= X"14"; -- $
when 16#824# => romdata <= X"14"; -- $
when 16#924# => romdata <= X"78"; -- $
when 16#a24# => romdata <= X"10"; -- $
when 16#b24# => romdata <= X"00"; -- $
when 16#c24# => romdata <= X"00"; -- $
when 16#025# => romdata <= X"00"; -- %
when 16#125# => romdata <= X"00"; -- %
when 16#225# => romdata <= X"22"; -- %
when 16#325# => romdata <= X"52"; -- %
when 16#425# => romdata <= X"24"; -- %
when 16#525# => romdata <= X"08"; -- %
when 16#625# => romdata <= X"08"; -- %
when 16#725# => romdata <= X"10"; -- %
when 16#825# => romdata <= X"24"; -- %
when 16#925# => romdata <= X"2a"; -- %
when 16#a25# => romdata <= X"44"; -- %
when 16#b25# => romdata <= X"00"; -- %
when 16#c25# => romdata <= X"00"; -- %
when 16#026# => romdata <= X"00"; -- &
when 16#126# => romdata <= X"00"; -- &
when 16#226# => romdata <= X"00"; -- &
when 16#326# => romdata <= X"00"; -- &
when 16#426# => romdata <= X"30"; -- &
when 16#526# => romdata <= X"48"; -- &
when 16#626# => romdata <= X"48"; -- &
when 16#726# => romdata <= X"30"; -- &
when 16#826# => romdata <= X"4a"; -- &
when 16#926# => romdata <= X"44"; -- &
when 16#a26# => romdata <= X"3a"; -- &
when 16#b26# => romdata <= X"00"; -- &
when 16#c26# => romdata <= X"00"; -- &
when 16#027# => romdata <= X"00"; -- '
when 16#127# => romdata <= X"00"; -- '
when 16#227# => romdata <= X"10"; -- '
when 16#327# => romdata <= X"10"; -- '
when 16#427# => romdata <= X"10"; -- '
when 16#527# => romdata <= X"00"; -- '
when 16#627# => romdata <= X"00"; -- '
when 16#727# => romdata <= X"00"; -- '
when 16#827# => romdata <= X"00"; -- '
when 16#927# => romdata <= X"00"; -- '
when 16#a27# => romdata <= X"00"; -- '
when 16#b27# => romdata <= X"00"; -- '
when 16#c27# => romdata <= X"00"; -- '
when 16#028# => romdata <= X"00"; -- (
when 16#128# => romdata <= X"00"; -- (
when 16#228# => romdata <= X"04"; -- (
when 16#328# => romdata <= X"08"; -- (
when 16#428# => romdata <= X"08"; -- (
when 16#528# => romdata <= X"10"; -- (
when 16#628# => romdata <= X"10"; -- (
when 16#728# => romdata <= X"10"; -- (
when 16#828# => romdata <= X"08"; -- (
when 16#928# => romdata <= X"08"; -- (
when 16#a28# => romdata <= X"04"; -- (
when 16#b28# => romdata <= X"00"; -- (
when 16#c28# => romdata <= X"00"; -- (
when 16#029# => romdata <= X"00"; -- )
when 16#129# => romdata <= X"00"; -- )
when 16#229# => romdata <= X"20"; -- )
when 16#329# => romdata <= X"10"; -- )
when 16#429# => romdata <= X"10"; -- )
when 16#529# => romdata <= X"08"; -- )
when 16#629# => romdata <= X"08"; -- )
when 16#729# => romdata <= X"08"; -- )
when 16#829# => romdata <= X"10"; -- )
when 16#929# => romdata <= X"10"; -- )
when 16#a29# => romdata <= X"20"; -- )
when 16#b29# => romdata <= X"00"; -- )
when 16#c29# => romdata <= X"00"; -- )
when 16#02a# => romdata <= X"00"; -- *
when 16#12a# => romdata <= X"00"; -- *
when 16#22a# => romdata <= X"24"; -- *
when 16#32a# => romdata <= X"18"; -- *
when 16#42a# => romdata <= X"7e"; -- *
when 16#52a# => romdata <= X"18"; -- *
when 16#62a# => romdata <= X"24"; -- *
when 16#72a# => romdata <= X"00"; -- *
when 16#82a# => romdata <= X"00"; -- *
when 16#92a# => romdata <= X"00"; -- *
when 16#a2a# => romdata <= X"00"; -- *
when 16#b2a# => romdata <= X"00"; -- *
when 16#c2a# => romdata <= X"00"; -- *
when 16#02b# => romdata <= X"00"; -- +
when 16#12b# => romdata <= X"00"; -- +
when 16#22b# => romdata <= X"00"; -- +
when 16#32b# => romdata <= X"00"; -- +
when 16#42b# => romdata <= X"10"; -- +
when 16#52b# => romdata <= X"10"; -- +
when 16#62b# => romdata <= X"7c"; -- +
when 16#72b# => romdata <= X"10"; -- +
when 16#82b# => romdata <= X"10"; -- +
when 16#92b# => romdata <= X"00"; -- +
when 16#a2b# => romdata <= X"00"; -- +
when 16#b2b# => romdata <= X"00"; -- +
when 16#c2b# => romdata <= X"00"; -- +
when 16#02c# => romdata <= X"00"; -- ,
when 16#12c# => romdata <= X"00"; -- ,
when 16#22c# => romdata <= X"00"; -- ,
when 16#32c# => romdata <= X"00"; -- ,
when 16#42c# => romdata <= X"00"; -- ,
when 16#52c# => romdata <= X"00"; -- ,
when 16#62c# => romdata <= X"00"; -- ,
when 16#72c# => romdata <= X"00"; -- ,
when 16#82c# => romdata <= X"00"; -- ,
when 16#92c# => romdata <= X"38"; -- ,
when 16#a2c# => romdata <= X"30"; -- ,
when 16#b2c# => romdata <= X"40"; -- ,
when 16#c2c# => romdata <= X"00"; -- ,
when 16#02d# => romdata <= X"00"; -- -
when 16#12d# => romdata <= X"00"; -- -
when 16#22d# => romdata <= X"00"; -- -
when 16#32d# => romdata <= X"00"; -- -
when 16#42d# => romdata <= X"00"; -- -
when 16#52d# => romdata <= X"00"; -- -
when 16#62d# => romdata <= X"7c"; -- -
when 16#72d# => romdata <= X"00"; -- -
when 16#82d# => romdata <= X"00"; -- -
when 16#92d# => romdata <= X"00"; -- -
when 16#a2d# => romdata <= X"00"; -- -
when 16#b2d# => romdata <= X"00"; -- -
when 16#c2d# => romdata <= X"00"; -- -
when 16#02e# => romdata <= X"00"; -- .
when 16#12e# => romdata <= X"00"; -- .
when 16#22e# => romdata <= X"00"; -- .
when 16#32e# => romdata <= X"00"; -- .
when 16#42e# => romdata <= X"00"; -- .
when 16#52e# => romdata <= X"00"; -- .
when 16#62e# => romdata <= X"00"; -- .
when 16#72e# => romdata <= X"00"; -- .
when 16#82e# => romdata <= X"00"; -- .
when 16#92e# => romdata <= X"10"; -- .
when 16#a2e# => romdata <= X"38"; -- .
when 16#b2e# => romdata <= X"10"; -- .
when 16#c2e# => romdata <= X"00"; -- .
when 16#02f# => romdata <= X"00"; -- /
when 16#12f# => romdata <= X"00"; -- /
when 16#22f# => romdata <= X"02"; -- /
when 16#32f# => romdata <= X"02"; -- /
when 16#42f# => romdata <= X"04"; -- /
when 16#52f# => romdata <= X"08"; -- /
when 16#62f# => romdata <= X"10"; -- /
when 16#72f# => romdata <= X"20"; -- /
when 16#82f# => romdata <= X"40"; -- /
when 16#92f# => romdata <= X"80"; -- /
when 16#a2f# => romdata <= X"80"; -- /
when 16#b2f# => romdata <= X"00"; -- /
when 16#c2f# => romdata <= X"00"; -- /
when 16#030# => romdata <= X"00"; -- 0
when 16#130# => romdata <= X"00"; -- 0
when 16#230# => romdata <= X"18"; -- 0
when 16#330# => romdata <= X"24"; -- 0
when 16#430# => romdata <= X"42"; -- 0
when 16#530# => romdata <= X"42"; -- 0
when 16#630# => romdata <= X"42"; -- 0
when 16#730# => romdata <= X"42"; -- 0
when 16#830# => romdata <= X"42"; -- 0
when 16#930# => romdata <= X"24"; -- 0
when 16#a30# => romdata <= X"18"; -- 0
when 16#b30# => romdata <= X"00"; -- 0
when 16#c30# => romdata <= X"00"; -- 0
when 16#031# => romdata <= X"00"; -- 1
when 16#131# => romdata <= X"00"; -- 1
when 16#231# => romdata <= X"10"; -- 1
when 16#331# => romdata <= X"30"; -- 1
when 16#431# => romdata <= X"50"; -- 1
when 16#531# => romdata <= X"10"; -- 1
when 16#631# => romdata <= X"10"; -- 1
when 16#731# => romdata <= X"10"; -- 1
when 16#831# => romdata <= X"10"; -- 1
when 16#931# => romdata <= X"10"; -- 1
when 16#a31# => romdata <= X"7c"; -- 1
when 16#b31# => romdata <= X"00"; -- 1
when 16#c31# => romdata <= X"00"; -- 1
when 16#032# => romdata <= X"00"; -- 2
when 16#132# => romdata <= X"00"; -- 2
when 16#232# => romdata <= X"3c"; -- 2
when 16#332# => romdata <= X"42"; -- 2
when 16#432# => romdata <= X"42"; -- 2
when 16#532# => romdata <= X"02"; -- 2
when 16#632# => romdata <= X"04"; -- 2
when 16#732# => romdata <= X"18"; -- 2
when 16#832# => romdata <= X"20"; -- 2
when 16#932# => romdata <= X"40"; -- 2
when 16#a32# => romdata <= X"7e"; -- 2
when 16#b32# => romdata <= X"00"; -- 2
when 16#c32# => romdata <= X"00"; -- 2
when 16#033# => romdata <= X"00"; -- 3
when 16#133# => romdata <= X"00"; -- 3
when 16#233# => romdata <= X"7e"; -- 3
when 16#333# => romdata <= X"02"; -- 3
when 16#433# => romdata <= X"04"; -- 3
when 16#533# => romdata <= X"08"; -- 3
when 16#633# => romdata <= X"1c"; -- 3
when 16#733# => romdata <= X"02"; -- 3
when 16#833# => romdata <= X"02"; -- 3
when 16#933# => romdata <= X"42"; -- 3
when 16#a33# => romdata <= X"3c"; -- 3
when 16#b33# => romdata <= X"00"; -- 3
when 16#c33# => romdata <= X"00"; -- 3
when 16#034# => romdata <= X"00"; -- 4
when 16#134# => romdata <= X"00"; -- 4
when 16#234# => romdata <= X"04"; -- 4
when 16#334# => romdata <= X"0c"; -- 4
when 16#434# => romdata <= X"14"; -- 4
when 16#534# => romdata <= X"24"; -- 4
when 16#634# => romdata <= X"44"; -- 4
when 16#734# => romdata <= X"44"; -- 4
when 16#834# => romdata <= X"7e"; -- 4
when 16#934# => romdata <= X"04"; -- 4
when 16#a34# => romdata <= X"04"; -- 4
when 16#b34# => romdata <= X"00"; -- 4
when 16#c34# => romdata <= X"00"; -- 4
when 16#035# => romdata <= X"00"; -- 5
when 16#135# => romdata <= X"00"; -- 5
when 16#235# => romdata <= X"7e"; -- 5
when 16#335# => romdata <= X"40"; -- 5
when 16#435# => romdata <= X"40"; -- 5
when 16#535# => romdata <= X"5c"; -- 5
when 16#635# => romdata <= X"62"; -- 5
when 16#735# => romdata <= X"02"; -- 5
when 16#835# => romdata <= X"02"; -- 5
when 16#935# => romdata <= X"42"; -- 5
when 16#a35# => romdata <= X"3c"; -- 5
when 16#b35# => romdata <= X"00"; -- 5
when 16#c35# => romdata <= X"00"; -- 5
when 16#036# => romdata <= X"00"; -- 6
when 16#136# => romdata <= X"00"; -- 6
when 16#236# => romdata <= X"1c"; -- 6
when 16#336# => romdata <= X"20"; -- 6
when 16#436# => romdata <= X"40"; -- 6
when 16#536# => romdata <= X"40"; -- 6
when 16#636# => romdata <= X"5c"; -- 6
when 16#736# => romdata <= X"62"; -- 6
when 16#836# => romdata <= X"42"; -- 6
when 16#936# => romdata <= X"42"; -- 6
when 16#a36# => romdata <= X"3c"; -- 6
when 16#b36# => romdata <= X"00"; -- 6
when 16#c36# => romdata <= X"00"; -- 6
when 16#037# => romdata <= X"00"; -- 7
when 16#137# => romdata <= X"00"; -- 7
when 16#237# => romdata <= X"7e"; -- 7
when 16#337# => romdata <= X"02"; -- 7
when 16#437# => romdata <= X"04"; -- 7
when 16#537# => romdata <= X"08"; -- 7
when 16#637# => romdata <= X"08"; -- 7
when 16#737# => romdata <= X"10"; -- 7
when 16#837# => romdata <= X"10"; -- 7
when 16#937# => romdata <= X"20"; -- 7
when 16#a37# => romdata <= X"20"; -- 7
when 16#b37# => romdata <= X"00"; -- 7
when 16#c37# => romdata <= X"00"; -- 7
when 16#038# => romdata <= X"00"; -- 8
when 16#138# => romdata <= X"00"; -- 8
when 16#238# => romdata <= X"3c"; -- 8
when 16#338# => romdata <= X"42"; -- 8
when 16#438# => romdata <= X"42"; -- 8
when 16#538# => romdata <= X"42"; -- 8
when 16#638# => romdata <= X"3c"; -- 8
when 16#738# => romdata <= X"42"; -- 8
when 16#838# => romdata <= X"42"; -- 8
when 16#938# => romdata <= X"42"; -- 8
when 16#a38# => romdata <= X"3c"; -- 8
when 16#b38# => romdata <= X"00"; -- 8
when 16#c38# => romdata <= X"00"; -- 8
when 16#039# => romdata <= X"00"; -- 9
when 16#139# => romdata <= X"00"; -- 9
when 16#239# => romdata <= X"3c"; -- 9
when 16#339# => romdata <= X"42"; -- 9
when 16#439# => romdata <= X"42"; -- 9
when 16#539# => romdata <= X"46"; -- 9
when 16#639# => romdata <= X"3a"; -- 9
when 16#739# => romdata <= X"02"; -- 9
when 16#839# => romdata <= X"02"; -- 9
when 16#939# => romdata <= X"04"; -- 9
when 16#a39# => romdata <= X"38"; -- 9
when 16#b39# => romdata <= X"00"; -- 9
when 16#c39# => romdata <= X"00"; -- 9
when 16#03a# => romdata <= X"00"; -- :
when 16#13a# => romdata <= X"00"; -- :
when 16#23a# => romdata <= X"00"; -- :
when 16#33a# => romdata <= X"00"; -- :
when 16#43a# => romdata <= X"10"; -- :
when 16#53a# => romdata <= X"38"; -- :
when 16#63a# => romdata <= X"10"; -- :
when 16#73a# => romdata <= X"00"; -- :
when 16#83a# => romdata <= X"00"; -- :
when 16#93a# => romdata <= X"10"; -- :
when 16#a3a# => romdata <= X"38"; -- :
when 16#b3a# => romdata <= X"10"; -- :
when 16#c3a# => romdata <= X"00"; -- :
when 16#03b# => romdata <= X"00"; -- ;
when 16#13b# => romdata <= X"00"; -- ;
when 16#23b# => romdata <= X"00"; -- ;
when 16#33b# => romdata <= X"00"; -- ;
when 16#43b# => romdata <= X"10"; -- ;
when 16#53b# => romdata <= X"38"; -- ;
when 16#63b# => romdata <= X"10"; -- ;
when 16#73b# => romdata <= X"00"; -- ;
when 16#83b# => romdata <= X"00"; -- ;
when 16#93b# => romdata <= X"38"; -- ;
when 16#a3b# => romdata <= X"30"; -- ;
when 16#b3b# => romdata <= X"40"; -- ;
when 16#c3b# => romdata <= X"00"; -- ;
when 16#03c# => romdata <= X"00"; -- <
when 16#13c# => romdata <= X"00"; -- <
when 16#23c# => romdata <= X"02"; -- <
when 16#33c# => romdata <= X"04"; -- <
when 16#43c# => romdata <= X"08"; -- <
when 16#53c# => romdata <= X"10"; -- <
when 16#63c# => romdata <= X"20"; -- <
when 16#73c# => romdata <= X"10"; -- <
when 16#83c# => romdata <= X"08"; -- <
when 16#93c# => romdata <= X"04"; -- <
when 16#a3c# => romdata <= X"02"; -- <
when 16#b3c# => romdata <= X"00"; -- <
when 16#c3c# => romdata <= X"00"; -- <
when 16#03d# => romdata <= X"00"; -- =
when 16#13d# => romdata <= X"00"; -- =
when 16#23d# => romdata <= X"00"; -- =
when 16#33d# => romdata <= X"00"; -- =
when 16#43d# => romdata <= X"00"; -- =
when 16#53d# => romdata <= X"7e"; -- =
when 16#63d# => romdata <= X"00"; -- =
when 16#73d# => romdata <= X"00"; -- =
when 16#83d# => romdata <= X"7e"; -- =
when 16#93d# => romdata <= X"00"; -- =
when 16#a3d# => romdata <= X"00"; -- =
when 16#b3d# => romdata <= X"00"; -- =
when 16#c3d# => romdata <= X"00"; -- =
when 16#03e# => romdata <= X"00"; -- >
when 16#13e# => romdata <= X"00"; -- >
when 16#23e# => romdata <= X"40"; -- >
when 16#33e# => romdata <= X"20"; -- >
when 16#43e# => romdata <= X"10"; -- >
when 16#53e# => romdata <= X"08"; -- >
when 16#63e# => romdata <= X"04"; -- >
when 16#73e# => romdata <= X"08"; -- >
when 16#83e# => romdata <= X"10"; -- >
when 16#93e# => romdata <= X"20"; -- >
when 16#a3e# => romdata <= X"40"; -- >
when 16#b3e# => romdata <= X"00"; -- >
when 16#c3e# => romdata <= X"00"; -- >
when 16#03f# => romdata <= X"00"; -- ?
when 16#13f# => romdata <= X"00"; -- ?
when 16#23f# => romdata <= X"3c"; -- ?
when 16#33f# => romdata <= X"42"; -- ?
when 16#43f# => romdata <= X"42"; -- ?
when 16#53f# => romdata <= X"02"; -- ?
when 16#63f# => romdata <= X"04"; -- ?
when 16#73f# => romdata <= X"08"; -- ?
when 16#83f# => romdata <= X"08"; -- ?
when 16#93f# => romdata <= X"00"; -- ?
when 16#a3f# => romdata <= X"08"; -- ?
when 16#b3f# => romdata <= X"00"; -- ?
when 16#c3f# => romdata <= X"00"; -- ?
when 16#040# => romdata <= X"00"; -- @
when 16#140# => romdata <= X"00"; -- @
when 16#240# => romdata <= X"3c"; -- @
when 16#340# => romdata <= X"42"; -- @
when 16#440# => romdata <= X"42"; -- @
when 16#540# => romdata <= X"4e"; -- @
when 16#640# => romdata <= X"52"; -- @
when 16#740# => romdata <= X"56"; -- @
when 16#840# => romdata <= X"4a"; -- @
when 16#940# => romdata <= X"40"; -- @
when 16#a40# => romdata <= X"3c"; -- @
when 16#b40# => romdata <= X"00"; -- @
when 16#c40# => romdata <= X"00"; -- @
when 16#041# => romdata <= X"00"; -- A
when 16#141# => romdata <= X"00"; -- A
when 16#241# => romdata <= X"18"; -- A
when 16#341# => romdata <= X"24"; -- A
when 16#441# => romdata <= X"42"; -- A
when 16#541# => romdata <= X"42"; -- A
when 16#641# => romdata <= X"42"; -- A
when 16#741# => romdata <= X"7e"; -- A
when 16#841# => romdata <= X"42"; -- A
when 16#941# => romdata <= X"42"; -- A
when 16#a41# => romdata <= X"42"; -- A
when 16#b41# => romdata <= X"00"; -- A
when 16#c41# => romdata <= X"00"; -- A
when 16#042# => romdata <= X"00"; -- B
when 16#142# => romdata <= X"00"; -- B
when 16#242# => romdata <= X"78"; -- B
when 16#342# => romdata <= X"44"; -- B
when 16#442# => romdata <= X"42"; -- B
when 16#542# => romdata <= X"44"; -- B
when 16#642# => romdata <= X"78"; -- B
when 16#742# => romdata <= X"44"; -- B
when 16#842# => romdata <= X"42"; -- B
when 16#942# => romdata <= X"44"; -- B
when 16#a42# => romdata <= X"78"; -- B
when 16#b42# => romdata <= X"00"; -- B
when 16#c42# => romdata <= X"00"; -- B
when 16#043# => romdata <= X"00"; -- C
when 16#143# => romdata <= X"00"; -- C
when 16#243# => romdata <= X"3c"; -- C
when 16#343# => romdata <= X"42"; -- C
when 16#443# => romdata <= X"40"; -- C
when 16#543# => romdata <= X"40"; -- C
when 16#643# => romdata <= X"40"; -- C
when 16#743# => romdata <= X"40"; -- C
when 16#843# => romdata <= X"40"; -- C
when 16#943# => romdata <= X"42"; -- C
when 16#a43# => romdata <= X"3c"; -- C
when 16#b43# => romdata <= X"00"; -- C
when 16#c43# => romdata <= X"00"; -- C
when 16#044# => romdata <= X"00"; -- D
when 16#144# => romdata <= X"00"; -- D
when 16#244# => romdata <= X"78"; -- D
when 16#344# => romdata <= X"44"; -- D
when 16#444# => romdata <= X"42"; -- D
when 16#544# => romdata <= X"42"; -- D
when 16#644# => romdata <= X"42"; -- D
when 16#744# => romdata <= X"42"; -- D
when 16#844# => romdata <= X"42"; -- D
when 16#944# => romdata <= X"44"; -- D
when 16#a44# => romdata <= X"78"; -- D
when 16#b44# => romdata <= X"00"; -- D
when 16#c44# => romdata <= X"00"; -- D
when 16#045# => romdata <= X"00"; -- E
when 16#145# => romdata <= X"00"; -- E
when 16#245# => romdata <= X"7e"; -- E
when 16#345# => romdata <= X"40"; -- E
when 16#445# => romdata <= X"40"; -- E
when 16#545# => romdata <= X"40"; -- E
when 16#645# => romdata <= X"78"; -- E
when 16#745# => romdata <= X"40"; -- E
when 16#845# => romdata <= X"40"; -- E
when 16#945# => romdata <= X"40"; -- E
when 16#a45# => romdata <= X"7e"; -- E
when 16#b45# => romdata <= X"00"; -- E
when 16#c45# => romdata <= X"00"; -- E
when 16#046# => romdata <= X"00"; -- F
when 16#146# => romdata <= X"00"; -- F
when 16#246# => romdata <= X"7e"; -- F
when 16#346# => romdata <= X"40"; -- F
when 16#446# => romdata <= X"40"; -- F
when 16#546# => romdata <= X"40"; -- F
when 16#646# => romdata <= X"78"; -- F
when 16#746# => romdata <= X"40"; -- F
when 16#846# => romdata <= X"40"; -- F
when 16#946# => romdata <= X"40"; -- F
when 16#a46# => romdata <= X"40"; -- F
when 16#b46# => romdata <= X"00"; -- F
when 16#c46# => romdata <= X"00"; -- F
when 16#047# => romdata <= X"00"; -- G
when 16#147# => romdata <= X"00"; -- G
when 16#247# => romdata <= X"3c"; -- G
when 16#347# => romdata <= X"42"; -- G
when 16#447# => romdata <= X"40"; -- G
when 16#547# => romdata <= X"40"; -- G
when 16#647# => romdata <= X"40"; -- G
when 16#747# => romdata <= X"4e"; -- G
when 16#847# => romdata <= X"42"; -- G
when 16#947# => romdata <= X"46"; -- G
when 16#a47# => romdata <= X"3a"; -- G
when 16#b47# => romdata <= X"00"; -- G
when 16#c47# => romdata <= X"00"; -- G
when 16#048# => romdata <= X"00"; -- H
when 16#148# => romdata <= X"00"; -- H
when 16#248# => romdata <= X"42"; -- H
when 16#348# => romdata <= X"42"; -- H
when 16#448# => romdata <= X"42"; -- H
when 16#548# => romdata <= X"42"; -- H
when 16#648# => romdata <= X"7e"; -- H
when 16#748# => romdata <= X"42"; -- H
when 16#848# => romdata <= X"42"; -- H
when 16#948# => romdata <= X"42"; -- H
when 16#a48# => romdata <= X"42"; -- H
when 16#b48# => romdata <= X"00"; -- H
when 16#c48# => romdata <= X"00"; -- H
when 16#049# => romdata <= X"00"; -- I
when 16#149# => romdata <= X"00"; -- I
when 16#249# => romdata <= X"7c"; -- I
when 16#349# => romdata <= X"10"; -- I
when 16#449# => romdata <= X"10"; -- I
when 16#549# => romdata <= X"10"; -- I
when 16#649# => romdata <= X"10"; -- I
when 16#749# => romdata <= X"10"; -- I
when 16#849# => romdata <= X"10"; -- I
when 16#949# => romdata <= X"10"; -- I
when 16#a49# => romdata <= X"7c"; -- I
when 16#b49# => romdata <= X"00"; -- I
when 16#c49# => romdata <= X"00"; -- I
when 16#04a# => romdata <= X"00"; -- J
when 16#14a# => romdata <= X"00"; -- J
when 16#24a# => romdata <= X"1f"; -- J
when 16#34a# => romdata <= X"04"; -- J
when 16#44a# => romdata <= X"04"; -- J
when 16#54a# => romdata <= X"04"; -- J
when 16#64a# => romdata <= X"04"; -- J
when 16#74a# => romdata <= X"04"; -- J
when 16#84a# => romdata <= X"04"; -- J
when 16#94a# => romdata <= X"44"; -- J
when 16#a4a# => romdata <= X"38"; -- J
when 16#b4a# => romdata <= X"00"; -- J
when 16#c4a# => romdata <= X"00"; -- J
when 16#04b# => romdata <= X"00"; -- K
when 16#14b# => romdata <= X"00"; -- K
when 16#24b# => romdata <= X"42"; -- K
when 16#34b# => romdata <= X"44"; -- K
when 16#44b# => romdata <= X"48"; -- K
when 16#54b# => romdata <= X"50"; -- K
when 16#64b# => romdata <= X"60"; -- K
when 16#74b# => romdata <= X"50"; -- K
when 16#84b# => romdata <= X"48"; -- K
when 16#94b# => romdata <= X"44"; -- K
when 16#a4b# => romdata <= X"42"; -- K
when 16#b4b# => romdata <= X"00"; -- K
when 16#c4b# => romdata <= X"00"; -- K
when 16#04c# => romdata <= X"00"; -- L
when 16#14c# => romdata <= X"00"; -- L
when 16#24c# => romdata <= X"40"; -- L
when 16#34c# => romdata <= X"40"; -- L
when 16#44c# => romdata <= X"40"; -- L
when 16#54c# => romdata <= X"40"; -- L
when 16#64c# => romdata <= X"40"; -- L
when 16#74c# => romdata <= X"40"; -- L
when 16#84c# => romdata <= X"40"; -- L
when 16#94c# => romdata <= X"40"; -- L
when 16#a4c# => romdata <= X"7e"; -- L
when 16#b4c# => romdata <= X"00"; -- L
when 16#c4c# => romdata <= X"00"; -- L
when 16#04d# => romdata <= X"00"; -- M
when 16#14d# => romdata <= X"00"; -- M
when 16#24d# => romdata <= X"82"; -- M
when 16#34d# => romdata <= X"82"; -- M
when 16#44d# => romdata <= X"c6"; -- M
when 16#54d# => romdata <= X"aa"; -- M
when 16#64d# => romdata <= X"92"; -- M
when 16#74d# => romdata <= X"92"; -- M
when 16#84d# => romdata <= X"82"; -- M
when 16#94d# => romdata <= X"82"; -- M
when 16#a4d# => romdata <= X"82"; -- M
when 16#b4d# => romdata <= X"00"; -- M
when 16#c4d# => romdata <= X"00"; -- M
when 16#04e# => romdata <= X"00"; -- N
when 16#14e# => romdata <= X"00"; -- N
when 16#24e# => romdata <= X"42"; -- N
when 16#34e# => romdata <= X"42"; -- N
when 16#44e# => romdata <= X"62"; -- N
when 16#54e# => romdata <= X"52"; -- N
when 16#64e# => romdata <= X"4a"; -- N
when 16#74e# => romdata <= X"46"; -- N
when 16#84e# => romdata <= X"42"; -- N
when 16#94e# => romdata <= X"42"; -- N
when 16#a4e# => romdata <= X"42"; -- N
when 16#b4e# => romdata <= X"00"; -- N
when 16#c4e# => romdata <= X"00"; -- N
when 16#04f# => romdata <= X"00"; -- O
when 16#14f# => romdata <= X"00"; -- O
when 16#24f# => romdata <= X"3c"; -- O
when 16#34f# => romdata <= X"42"; -- O
when 16#44f# => romdata <= X"42"; -- O
when 16#54f# => romdata <= X"42"; -- O
when 16#64f# => romdata <= X"42"; -- O
when 16#74f# => romdata <= X"42"; -- O
when 16#84f# => romdata <= X"42"; -- O
when 16#94f# => romdata <= X"42"; -- O
when 16#a4f# => romdata <= X"3c"; -- O
when 16#b4f# => romdata <= X"00"; -- O
when 16#c4f# => romdata <= X"00"; -- O
when 16#050# => romdata <= X"00"; -- P
when 16#150# => romdata <= X"00"; -- P
when 16#250# => romdata <= X"7c"; -- P
when 16#350# => romdata <= X"42"; -- P
when 16#450# => romdata <= X"42"; -- P
when 16#550# => romdata <= X"42"; -- P
when 16#650# => romdata <= X"7c"; -- P
when 16#750# => romdata <= X"40"; -- P
when 16#850# => romdata <= X"40"; -- P
when 16#950# => romdata <= X"40"; -- P
when 16#a50# => romdata <= X"40"; -- P
when 16#b50# => romdata <= X"00"; -- P
when 16#c50# => romdata <= X"00"; -- P
when 16#051# => romdata <= X"00"; -- Q
when 16#151# => romdata <= X"00"; -- Q
when 16#251# => romdata <= X"3c"; -- Q
when 16#351# => romdata <= X"42"; -- Q
when 16#451# => romdata <= X"42"; -- Q
when 16#551# => romdata <= X"42"; -- Q
when 16#651# => romdata <= X"42"; -- Q
when 16#751# => romdata <= X"42"; -- Q
when 16#851# => romdata <= X"52"; -- Q
when 16#951# => romdata <= X"4a"; -- Q
when 16#a51# => romdata <= X"3c"; -- Q
when 16#b51# => romdata <= X"02"; -- Q
when 16#c51# => romdata <= X"00"; -- Q
when 16#052# => romdata <= X"00"; -- R
when 16#152# => romdata <= X"00"; -- R
when 16#252# => romdata <= X"7c"; -- R
when 16#352# => romdata <= X"42"; -- R
when 16#452# => romdata <= X"42"; -- R
when 16#552# => romdata <= X"42"; -- R
when 16#652# => romdata <= X"7c"; -- R
when 16#752# => romdata <= X"50"; -- R
when 16#852# => romdata <= X"48"; -- R
when 16#952# => romdata <= X"44"; -- R
when 16#a52# => romdata <= X"42"; -- R
when 16#b52# => romdata <= X"00"; -- R
when 16#c52# => romdata <= X"00"; -- R
when 16#053# => romdata <= X"00"; -- S
when 16#153# => romdata <= X"00"; -- S
when 16#253# => romdata <= X"3c"; -- S
when 16#353# => romdata <= X"42"; -- S
when 16#453# => romdata <= X"40"; -- S
when 16#553# => romdata <= X"40"; -- S
when 16#653# => romdata <= X"3c"; -- S
when 16#753# => romdata <= X"02"; -- S
when 16#853# => romdata <= X"02"; -- S
when 16#953# => romdata <= X"42"; -- S
when 16#a53# => romdata <= X"3c"; -- S
when 16#b53# => romdata <= X"00"; -- S
when 16#c53# => romdata <= X"00"; -- S
when 16#054# => romdata <= X"00"; -- T
when 16#154# => romdata <= X"00"; -- T
when 16#254# => romdata <= X"fe"; -- T
when 16#354# => romdata <= X"10"; -- T
when 16#454# => romdata <= X"10"; -- T
when 16#554# => romdata <= X"10"; -- T
when 16#654# => romdata <= X"10"; -- T
when 16#754# => romdata <= X"10"; -- T
when 16#854# => romdata <= X"10"; -- T
when 16#954# => romdata <= X"10"; -- T
when 16#a54# => romdata <= X"10"; -- T
when 16#b54# => romdata <= X"00"; -- T
when 16#c54# => romdata <= X"00"; -- T
when 16#055# => romdata <= X"00"; -- U
when 16#155# => romdata <= X"00"; -- U
when 16#255# => romdata <= X"42"; -- U
when 16#355# => romdata <= X"42"; -- U
when 16#455# => romdata <= X"42"; -- U
when 16#555# => romdata <= X"42"; -- U
when 16#655# => romdata <= X"42"; -- U
when 16#755# => romdata <= X"42"; -- U
when 16#855# => romdata <= X"42"; -- U
when 16#955# => romdata <= X"42"; -- U
when 16#a55# => romdata <= X"3c"; -- U
when 16#b55# => romdata <= X"00"; -- U
when 16#c55# => romdata <= X"00"; -- U
when 16#056# => romdata <= X"00"; -- V
when 16#156# => romdata <= X"00"; -- V
when 16#256# => romdata <= X"82"; -- V
when 16#356# => romdata <= X"82"; -- V
when 16#456# => romdata <= X"44"; -- V
when 16#556# => romdata <= X"44"; -- V
when 16#656# => romdata <= X"44"; -- V
when 16#756# => romdata <= X"28"; -- V
when 16#856# => romdata <= X"28"; -- V
when 16#956# => romdata <= X"28"; -- V
when 16#a56# => romdata <= X"10"; -- V
when 16#b56# => romdata <= X"00"; -- V
when 16#c56# => romdata <= X"00"; -- V
when 16#057# => romdata <= X"00"; -- W
when 16#157# => romdata <= X"00"; -- W
when 16#257# => romdata <= X"82"; -- W
when 16#357# => romdata <= X"82"; -- W
when 16#457# => romdata <= X"82"; -- W
when 16#557# => romdata <= X"82"; -- W
when 16#657# => romdata <= X"92"; -- W
when 16#757# => romdata <= X"92"; -- W
when 16#857# => romdata <= X"92"; -- W
when 16#957# => romdata <= X"aa"; -- W
when 16#a57# => romdata <= X"44"; -- W
when 16#b57# => romdata <= X"00"; -- W
when 16#c57# => romdata <= X"00"; -- W
when 16#058# => romdata <= X"00"; -- X
when 16#158# => romdata <= X"00"; -- X
when 16#258# => romdata <= X"82"; -- X
when 16#358# => romdata <= X"82"; -- X
when 16#458# => romdata <= X"44"; -- X
when 16#558# => romdata <= X"28"; -- X
when 16#658# => romdata <= X"10"; -- X
when 16#758# => romdata <= X"28"; -- X
when 16#858# => romdata <= X"44"; -- X
when 16#958# => romdata <= X"82"; -- X
when 16#a58# => romdata <= X"82"; -- X
when 16#b58# => romdata <= X"00"; -- X
when 16#c58# => romdata <= X"00"; -- X
when 16#059# => romdata <= X"00"; -- Y
when 16#159# => romdata <= X"00"; -- Y
when 16#259# => romdata <= X"82"; -- Y
when 16#359# => romdata <= X"82"; -- Y
when 16#459# => romdata <= X"44"; -- Y
when 16#559# => romdata <= X"28"; -- Y
when 16#659# => romdata <= X"10"; -- Y
when 16#759# => romdata <= X"10"; -- Y
when 16#859# => romdata <= X"10"; -- Y
when 16#959# => romdata <= X"10"; -- Y
when 16#a59# => romdata <= X"10"; -- Y
when 16#b59# => romdata <= X"00"; -- Y
when 16#c59# => romdata <= X"00"; -- Y
when 16#05a# => romdata <= X"00"; -- Z
when 16#15a# => romdata <= X"00"; -- Z
when 16#25a# => romdata <= X"7e"; -- Z
when 16#35a# => romdata <= X"02"; -- Z
when 16#45a# => romdata <= X"04"; -- Z
when 16#55a# => romdata <= X"08"; -- Z
when 16#65a# => romdata <= X"10"; -- Z
when 16#75a# => romdata <= X"20"; -- Z
when 16#85a# => romdata <= X"40"; -- Z
when 16#95a# => romdata <= X"40"; -- Z
when 16#a5a# => romdata <= X"7e"; -- Z
when 16#b5a# => romdata <= X"00"; -- Z
when 16#c5a# => romdata <= X"00"; -- Z
when 16#05b# => romdata <= X"00"; -- [
when 16#15b# => romdata <= X"00"; -- [
when 16#25b# => romdata <= X"3c"; -- [
when 16#35b# => romdata <= X"20"; -- [
when 16#45b# => romdata <= X"20"; -- [
when 16#55b# => romdata <= X"20"; -- [
when 16#65b# => romdata <= X"20"; -- [
when 16#75b# => romdata <= X"20"; -- [
when 16#85b# => romdata <= X"20"; -- [
when 16#95b# => romdata <= X"20"; -- [
when 16#a5b# => romdata <= X"3c"; -- [
when 16#b5b# => romdata <= X"00"; -- [
when 16#c5b# => romdata <= X"00"; -- [
when 16#05c# => romdata <= X"00"; -- \
when 16#15c# => romdata <= X"00"; -- \
when 16#25c# => romdata <= X"80"; -- \
when 16#35c# => romdata <= X"80"; -- \
when 16#45c# => romdata <= X"40"; -- \
when 16#55c# => romdata <= X"20"; -- \
when 16#65c# => romdata <= X"10"; -- \
when 16#75c# => romdata <= X"08"; -- \
when 16#85c# => romdata <= X"04"; -- \
when 16#95c# => romdata <= X"02"; -- \
when 16#a5c# => romdata <= X"02"; -- \
when 16#b5c# => romdata <= X"00"; -- \
when 16#c5c# => romdata <= X"00"; -- \
when 16#05d# => romdata <= X"00"; -- ]
when 16#15d# => romdata <= X"00"; -- ]
when 16#25d# => romdata <= X"78"; -- ]
when 16#35d# => romdata <= X"08"; -- ]
when 16#45d# => romdata <= X"08"; -- ]
when 16#55d# => romdata <= X"08"; -- ]
when 16#65d# => romdata <= X"08"; -- ]
when 16#75d# => romdata <= X"08"; -- ]
when 16#85d# => romdata <= X"08"; -- ]
when 16#95d# => romdata <= X"08"; -- ]
when 16#a5d# => romdata <= X"78"; -- ]
when 16#b5d# => romdata <= X"00"; -- ]
when 16#c5d# => romdata <= X"00"; -- ]
when 16#05e# => romdata <= X"00"; -- ^
when 16#15e# => romdata <= X"00"; -- ^
when 16#25e# => romdata <= X"10"; -- ^
when 16#35e# => romdata <= X"28"; -- ^
when 16#45e# => romdata <= X"44"; -- ^
when 16#55e# => romdata <= X"00"; -- ^
when 16#65e# => romdata <= X"00"; -- ^
when 16#75e# => romdata <= X"00"; -- ^
when 16#85e# => romdata <= X"00"; -- ^
when 16#95e# => romdata <= X"00"; -- ^
when 16#a5e# => romdata <= X"00"; -- ^
when 16#b5e# => romdata <= X"00"; -- ^
when 16#c5e# => romdata <= X"00"; -- ^
when 16#05f# => romdata <= X"00"; -- _
when 16#15f# => romdata <= X"00"; -- _
when 16#25f# => romdata <= X"00"; -- _
when 16#35f# => romdata <= X"00"; -- _
when 16#45f# => romdata <= X"00"; -- _
when 16#55f# => romdata <= X"00"; -- _
when 16#65f# => romdata <= X"00"; -- _
when 16#75f# => romdata <= X"00"; -- _
when 16#85f# => romdata <= X"00"; -- _
when 16#95f# => romdata <= X"00"; -- _
when 16#a5f# => romdata <= X"00"; -- _
when 16#b5f# => romdata <= X"fe"; -- _
when 16#c5f# => romdata <= X"00"; -- _
when 16#060# => romdata <= X"00"; -- `
when 16#160# => romdata <= X"10"; -- `
when 16#260# => romdata <= X"08"; -- `
when 16#360# => romdata <= X"00"; -- `
when 16#460# => romdata <= X"00"; -- `
when 16#560# => romdata <= X"00"; -- `
when 16#660# => romdata <= X"00"; -- `
when 16#760# => romdata <= X"00"; -- `
when 16#860# => romdata <= X"00"; -- `
when 16#960# => romdata <= X"00"; -- `
when 16#a60# => romdata <= X"00"; -- `
when 16#b60# => romdata <= X"00"; -- `
when 16#c60# => romdata <= X"00"; -- `
when 16#061# => romdata <= X"00"; -- a
when 16#161# => romdata <= X"00"; -- a
when 16#261# => romdata <= X"00"; -- a
when 16#361# => romdata <= X"00"; -- a
when 16#461# => romdata <= X"00"; -- a
when 16#561# => romdata <= X"3c"; -- a
when 16#661# => romdata <= X"02"; -- a
when 16#761# => romdata <= X"3e"; -- a
when 16#861# => romdata <= X"42"; -- a
when 16#961# => romdata <= X"46"; -- a
when 16#a61# => romdata <= X"3a"; -- a
when 16#b61# => romdata <= X"00"; -- a
when 16#c61# => romdata <= X"00"; -- a
when 16#062# => romdata <= X"00"; -- b
when 16#162# => romdata <= X"00"; -- b
when 16#262# => romdata <= X"40"; -- b
when 16#362# => romdata <= X"40"; -- b
when 16#462# => romdata <= X"40"; -- b
when 16#562# => romdata <= X"5c"; -- b
when 16#662# => romdata <= X"62"; -- b
when 16#762# => romdata <= X"42"; -- b
when 16#862# => romdata <= X"42"; -- b
when 16#962# => romdata <= X"62"; -- b
when 16#a62# => romdata <= X"5c"; -- b
when 16#b62# => romdata <= X"00"; -- b
when 16#c62# => romdata <= X"00"; -- b
when 16#063# => romdata <= X"00"; -- c
when 16#163# => romdata <= X"00"; -- c
when 16#263# => romdata <= X"00"; -- c
when 16#363# => romdata <= X"00"; -- c
when 16#463# => romdata <= X"00"; -- c
when 16#563# => romdata <= X"3c"; -- c
when 16#663# => romdata <= X"42"; -- c
when 16#763# => romdata <= X"40"; -- c
when 16#863# => romdata <= X"40"; -- c
when 16#963# => romdata <= X"42"; -- c
when 16#a63# => romdata <= X"3c"; -- c
when 16#b63# => romdata <= X"00"; -- c
when 16#c63# => romdata <= X"00"; -- c
when 16#064# => romdata <= X"00"; -- d
when 16#164# => romdata <= X"00"; -- d
when 16#264# => romdata <= X"02"; -- d
when 16#364# => romdata <= X"02"; -- d
when 16#464# => romdata <= X"02"; -- d
when 16#564# => romdata <= X"3a"; -- d
when 16#664# => romdata <= X"46"; -- d
when 16#764# => romdata <= X"42"; -- d
when 16#864# => romdata <= X"42"; -- d
when 16#964# => romdata <= X"46"; -- d
when 16#a64# => romdata <= X"3a"; -- d
when 16#b64# => romdata <= X"00"; -- d
when 16#c64# => romdata <= X"00"; -- d
when 16#065# => romdata <= X"00"; -- e
when 16#165# => romdata <= X"00"; -- e
when 16#265# => romdata <= X"00"; -- e
when 16#365# => romdata <= X"00"; -- e
when 16#465# => romdata <= X"00"; -- e
when 16#565# => romdata <= X"3c"; -- e
when 16#665# => romdata <= X"42"; -- e
when 16#765# => romdata <= X"7e"; -- e
when 16#865# => romdata <= X"40"; -- e
when 16#965# => romdata <= X"42"; -- e
when 16#a65# => romdata <= X"3c"; -- e
when 16#b65# => romdata <= X"00"; -- e
when 16#c65# => romdata <= X"00"; -- e
when 16#066# => romdata <= X"00"; -- f
when 16#166# => romdata <= X"00"; -- f
when 16#266# => romdata <= X"1c"; -- f
when 16#366# => romdata <= X"22"; -- f
when 16#466# => romdata <= X"20"; -- f
when 16#566# => romdata <= X"20"; -- f
when 16#666# => romdata <= X"7c"; -- f
when 16#766# => romdata <= X"20"; -- f
when 16#866# => romdata <= X"20"; -- f
when 16#966# => romdata <= X"20"; -- f
when 16#a66# => romdata <= X"20"; -- f
when 16#b66# => romdata <= X"00"; -- f
when 16#c66# => romdata <= X"00"; -- f
when 16#067# => romdata <= X"00"; -- g
when 16#167# => romdata <= X"00"; -- g
when 16#267# => romdata <= X"00"; -- g
when 16#367# => romdata <= X"00"; -- g
when 16#467# => romdata <= X"00"; -- g
when 16#567# => romdata <= X"3a"; -- g
when 16#667# => romdata <= X"44"; -- g
when 16#767# => romdata <= X"44"; -- g
when 16#867# => romdata <= X"38"; -- g
when 16#967# => romdata <= X"40"; -- g
when 16#a67# => romdata <= X"3c"; -- g
when 16#b67# => romdata <= X"42"; -- g
when 16#c67# => romdata <= X"3c"; -- g
when 16#068# => romdata <= X"00"; -- h
when 16#168# => romdata <= X"00"; -- h
when 16#268# => romdata <= X"40"; -- h
when 16#368# => romdata <= X"40"; -- h
when 16#468# => romdata <= X"40"; -- h
when 16#568# => romdata <= X"5c"; -- h
when 16#668# => romdata <= X"62"; -- h
when 16#768# => romdata <= X"42"; -- h
when 16#868# => romdata <= X"42"; -- h
when 16#968# => romdata <= X"42"; -- h
when 16#a68# => romdata <= X"42"; -- h
when 16#b68# => romdata <= X"00"; -- h
when 16#c68# => romdata <= X"00"; -- h
when 16#069# => romdata <= X"00"; -- i
when 16#169# => romdata <= X"00"; -- i
when 16#269# => romdata <= X"00"; -- i
when 16#369# => romdata <= X"10"; -- i
when 16#469# => romdata <= X"00"; -- i
when 16#569# => romdata <= X"30"; -- i
when 16#669# => romdata <= X"10"; -- i
when 16#769# => romdata <= X"10"; -- i
when 16#869# => romdata <= X"10"; -- i
when 16#969# => romdata <= X"10"; -- i
when 16#a69# => romdata <= X"7c"; -- i
when 16#b69# => romdata <= X"00"; -- i
when 16#c69# => romdata <= X"00"; -- i
when 16#06a# => romdata <= X"00"; -- j
when 16#16a# => romdata <= X"00"; -- j
when 16#26a# => romdata <= X"00"; -- j
when 16#36a# => romdata <= X"04"; -- j
when 16#46a# => romdata <= X"00"; -- j
when 16#56a# => romdata <= X"0c"; -- j
when 16#66a# => romdata <= X"04"; -- j
when 16#76a# => romdata <= X"04"; -- j
when 16#86a# => romdata <= X"04"; -- j
when 16#96a# => romdata <= X"04"; -- j
when 16#a6a# => romdata <= X"44"; -- j
when 16#b6a# => romdata <= X"44"; -- j
when 16#c6a# => romdata <= X"38"; -- j
when 16#06b# => romdata <= X"00"; -- k
when 16#16b# => romdata <= X"00"; -- k
when 16#26b# => romdata <= X"40"; -- k
when 16#36b# => romdata <= X"40"; -- k
when 16#46b# => romdata <= X"40"; -- k
when 16#56b# => romdata <= X"44"; -- k
when 16#66b# => romdata <= X"48"; -- k
when 16#76b# => romdata <= X"70"; -- k
when 16#86b# => romdata <= X"48"; -- k
when 16#96b# => romdata <= X"44"; -- k
when 16#a6b# => romdata <= X"42"; -- k
when 16#b6b# => romdata <= X"00"; -- k
when 16#c6b# => romdata <= X"00"; -- k
when 16#06c# => romdata <= X"00"; -- l
when 16#16c# => romdata <= X"00"; -- l
when 16#26c# => romdata <= X"30"; -- l
when 16#36c# => romdata <= X"10"; -- l
when 16#46c# => romdata <= X"10"; -- l
when 16#56c# => romdata <= X"10"; -- l
when 16#66c# => romdata <= X"10"; -- l
when 16#76c# => romdata <= X"10"; -- l
when 16#86c# => romdata <= X"10"; -- l
when 16#96c# => romdata <= X"10"; -- l
when 16#a6c# => romdata <= X"7c"; -- l
when 16#b6c# => romdata <= X"00"; -- l
when 16#c6c# => romdata <= X"00"; -- l
when 16#06d# => romdata <= X"00"; -- m
when 16#16d# => romdata <= X"00"; -- m
when 16#26d# => romdata <= X"00"; -- m
when 16#36d# => romdata <= X"00"; -- m
when 16#46d# => romdata <= X"00"; -- m
when 16#56d# => romdata <= X"ec"; -- m
when 16#66d# => romdata <= X"92"; -- m
when 16#76d# => romdata <= X"92"; -- m
when 16#86d# => romdata <= X"92"; -- m
when 16#96d# => romdata <= X"92"; -- m
when 16#a6d# => romdata <= X"82"; -- m
when 16#b6d# => romdata <= X"00"; -- m
when 16#c6d# => romdata <= X"00"; -- m
when 16#06e# => romdata <= X"00"; -- n
when 16#16e# => romdata <= X"00"; -- n
when 16#26e# => romdata <= X"00"; -- n
when 16#36e# => romdata <= X"00"; -- n
when 16#46e# => romdata <= X"00"; -- n
when 16#56e# => romdata <= X"5c"; -- n
when 16#66e# => romdata <= X"62"; -- n
when 16#76e# => romdata <= X"42"; -- n
when 16#86e# => romdata <= X"42"; -- n
when 16#96e# => romdata <= X"42"; -- n
when 16#a6e# => romdata <= X"42"; -- n
when 16#b6e# => romdata <= X"00"; -- n
when 16#c6e# => romdata <= X"00"; -- n
when 16#06f# => romdata <= X"00"; -- o
when 16#16f# => romdata <= X"00"; -- o
when 16#26f# => romdata <= X"00"; -- o
when 16#36f# => romdata <= X"00"; -- o
when 16#46f# => romdata <= X"00"; -- o
when 16#56f# => romdata <= X"3c"; -- o
when 16#66f# => romdata <= X"42"; -- o
when 16#76f# => romdata <= X"42"; -- o
when 16#86f# => romdata <= X"42"; -- o
when 16#96f# => romdata <= X"42"; -- o
when 16#a6f# => romdata <= X"3c"; -- o
when 16#b6f# => romdata <= X"00"; -- o
when 16#c6f# => romdata <= X"00"; -- o
when 16#070# => romdata <= X"00"; -- p
when 16#170# => romdata <= X"00"; -- p
when 16#270# => romdata <= X"00"; -- p
when 16#370# => romdata <= X"00"; -- p
when 16#470# => romdata <= X"00"; -- p
when 16#570# => romdata <= X"5c"; -- p
when 16#670# => romdata <= X"62"; -- p
when 16#770# => romdata <= X"42"; -- p
when 16#870# => romdata <= X"62"; -- p
when 16#970# => romdata <= X"5c"; -- p
when 16#a70# => romdata <= X"40"; -- p
when 16#b70# => romdata <= X"40"; -- p
when 16#c70# => romdata <= X"40"; -- p
when 16#071# => romdata <= X"00"; -- q
when 16#171# => romdata <= X"00"; -- q
when 16#271# => romdata <= X"00"; -- q
when 16#371# => romdata <= X"00"; -- q
when 16#471# => romdata <= X"00"; -- q
when 16#571# => romdata <= X"3a"; -- q
when 16#671# => romdata <= X"46"; -- q
when 16#771# => romdata <= X"42"; -- q
when 16#871# => romdata <= X"46"; -- q
when 16#971# => romdata <= X"3a"; -- q
when 16#a71# => romdata <= X"02"; -- q
when 16#b71# => romdata <= X"02"; -- q
when 16#c71# => romdata <= X"02"; -- q
when 16#072# => romdata <= X"00"; -- r
when 16#172# => romdata <= X"00"; -- r
when 16#272# => romdata <= X"00"; -- r
when 16#372# => romdata <= X"00"; -- r
when 16#472# => romdata <= X"00"; -- r
when 16#572# => romdata <= X"5c"; -- r
when 16#672# => romdata <= X"22"; -- r
when 16#772# => romdata <= X"20"; -- r
when 16#872# => romdata <= X"20"; -- r
when 16#972# => romdata <= X"20"; -- r
when 16#a72# => romdata <= X"20"; -- r
when 16#b72# => romdata <= X"00"; -- r
when 16#c72# => romdata <= X"00"; -- r
when 16#073# => romdata <= X"00"; -- s
when 16#173# => romdata <= X"00"; -- s
when 16#273# => romdata <= X"00"; -- s
when 16#373# => romdata <= X"00"; -- s
when 16#473# => romdata <= X"00"; -- s
when 16#573# => romdata <= X"3c"; -- s
when 16#673# => romdata <= X"42"; -- s
when 16#773# => romdata <= X"30"; -- s
when 16#873# => romdata <= X"0c"; -- s
when 16#973# => romdata <= X"42"; -- s
when 16#a73# => romdata <= X"3c"; -- s
when 16#b73# => romdata <= X"00"; -- s
when 16#c73# => romdata <= X"00"; -- s
when 16#074# => romdata <= X"00"; -- t
when 16#174# => romdata <= X"00"; -- t
when 16#274# => romdata <= X"00"; -- t
when 16#374# => romdata <= X"20"; -- t
when 16#474# => romdata <= X"20"; -- t
when 16#574# => romdata <= X"7c"; -- t
when 16#674# => romdata <= X"20"; -- t
when 16#774# => romdata <= X"20"; -- t
when 16#874# => romdata <= X"20"; -- t
when 16#974# => romdata <= X"22"; -- t
when 16#a74# => romdata <= X"1c"; -- t
when 16#b74# => romdata <= X"00"; -- t
when 16#c74# => romdata <= X"00"; -- t
when 16#075# => romdata <= X"00"; -- u
when 16#175# => romdata <= X"00"; -- u
when 16#275# => romdata <= X"00"; -- u
when 16#375# => romdata <= X"00"; -- u
when 16#475# => romdata <= X"00"; -- u
when 16#575# => romdata <= X"44"; -- u
when 16#675# => romdata <= X"44"; -- u
when 16#775# => romdata <= X"44"; -- u
when 16#875# => romdata <= X"44"; -- u
when 16#975# => romdata <= X"44"; -- u
when 16#a75# => romdata <= X"3a"; -- u
when 16#b75# => romdata <= X"00"; -- u
when 16#c75# => romdata <= X"00"; -- u
when 16#076# => romdata <= X"00"; -- v
when 16#176# => romdata <= X"00"; -- v
when 16#276# => romdata <= X"00"; -- v
when 16#376# => romdata <= X"00"; -- v
when 16#476# => romdata <= X"00"; -- v
when 16#576# => romdata <= X"44"; -- v
when 16#676# => romdata <= X"44"; -- v
when 16#776# => romdata <= X"44"; -- v
when 16#876# => romdata <= X"28"; -- v
when 16#976# => romdata <= X"28"; -- v
when 16#a76# => romdata <= X"10"; -- v
when 16#b76# => romdata <= X"00"; -- v
when 16#c76# => romdata <= X"00"; -- v
when 16#077# => romdata <= X"00"; -- w
when 16#177# => romdata <= X"00"; -- w
when 16#277# => romdata <= X"00"; -- w
when 16#377# => romdata <= X"00"; -- w
when 16#477# => romdata <= X"00"; -- w
when 16#577# => romdata <= X"82"; -- w
when 16#677# => romdata <= X"82"; -- w
when 16#777# => romdata <= X"92"; -- w
when 16#877# => romdata <= X"92"; -- w
when 16#977# => romdata <= X"aa"; -- w
when 16#a77# => romdata <= X"44"; -- w
when 16#b77# => romdata <= X"00"; -- w
when 16#c77# => romdata <= X"00"; -- w
when 16#078# => romdata <= X"00"; -- x
when 16#178# => romdata <= X"00"; -- x
when 16#278# => romdata <= X"00"; -- x
when 16#378# => romdata <= X"00"; -- x
when 16#478# => romdata <= X"00"; -- x
when 16#578# => romdata <= X"42"; -- x
when 16#678# => romdata <= X"24"; -- x
when 16#778# => romdata <= X"18"; -- x
when 16#878# => romdata <= X"18"; -- x
when 16#978# => romdata <= X"24"; -- x
when 16#a78# => romdata <= X"42"; -- x
when 16#b78# => romdata <= X"00"; -- x
when 16#c78# => romdata <= X"00"; -- x
when 16#079# => romdata <= X"00"; -- y
when 16#179# => romdata <= X"00"; -- y
when 16#279# => romdata <= X"00"; -- y
when 16#379# => romdata <= X"00"; -- y
when 16#479# => romdata <= X"00"; -- y
when 16#579# => romdata <= X"42"; -- y
when 16#679# => romdata <= X"42"; -- y
when 16#779# => romdata <= X"42"; -- y
when 16#879# => romdata <= X"46"; -- y
when 16#979# => romdata <= X"3a"; -- y
when 16#a79# => romdata <= X"02"; -- y
when 16#b79# => romdata <= X"42"; -- y
when 16#c79# => romdata <= X"3c"; -- y
when 16#07a# => romdata <= X"00"; -- z
when 16#17a# => romdata <= X"00"; -- z
when 16#27a# => romdata <= X"00"; -- z
when 16#37a# => romdata <= X"00"; -- z
when 16#47a# => romdata <= X"00"; -- z
when 16#57a# => romdata <= X"7e"; -- z
when 16#67a# => romdata <= X"04"; -- z
when 16#77a# => romdata <= X"08"; -- z
when 16#87a# => romdata <= X"10"; -- z
when 16#97a# => romdata <= X"20"; -- z
when 16#a7a# => romdata <= X"7e"; -- z
when 16#b7a# => romdata <= X"00"; -- z
when 16#c7a# => romdata <= X"00"; -- z
when 16#07b# => romdata <= X"00"; -- {
when 16#17b# => romdata <= X"00"; -- {
when 16#27b# => romdata <= X"0e"; -- {
when 16#37b# => romdata <= X"10"; -- {
when 16#47b# => romdata <= X"10"; -- {
when 16#57b# => romdata <= X"08"; -- {
when 16#67b# => romdata <= X"30"; -- {
when 16#77b# => romdata <= X"08"; -- {
when 16#87b# => romdata <= X"10"; -- {
when 16#97b# => romdata <= X"10"; -- {
when 16#a7b# => romdata <= X"0e"; -- {
when 16#b7b# => romdata <= X"00"; -- {
when 16#c7b# => romdata <= X"00"; -- {
when 16#07c# => romdata <= X"00"; -- |
when 16#17c# => romdata <= X"00"; -- |
when 16#27c# => romdata <= X"10"; -- |
when 16#37c# => romdata <= X"10"; -- |
when 16#47c# => romdata <= X"10"; -- |
when 16#57c# => romdata <= X"10"; -- |
when 16#67c# => romdata <= X"10"; -- |
when 16#77c# => romdata <= X"10"; -- |
when 16#87c# => romdata <= X"10"; -- |
when 16#97c# => romdata <= X"10"; -- |
when 16#a7c# => romdata <= X"10"; -- |
when 16#b7c# => romdata <= X"00"; -- |
when 16#c7c# => romdata <= X"00"; -- |
when 16#07d# => romdata <= X"00"; -- }
when 16#17d# => romdata <= X"00"; -- }
when 16#27d# => romdata <= X"70"; -- }
when 16#37d# => romdata <= X"08"; -- }
when 16#47d# => romdata <= X"08"; -- }
when 16#57d# => romdata <= X"10"; -- }
when 16#67d# => romdata <= X"0c"; -- }
when 16#77d# => romdata <= X"10"; -- }
when 16#87d# => romdata <= X"08"; -- }
when 16#97d# => romdata <= X"08"; -- }
when 16#a7d# => romdata <= X"70"; -- }
when 16#b7d# => romdata <= X"00"; -- }
when 16#c7d# => romdata <= X"00"; -- }
when 16#07e# => romdata <= X"00"; -- ~
when 16#17e# => romdata <= X"00"; -- ~
when 16#27e# => romdata <= X"24"; -- ~
when 16#37e# => romdata <= X"54"; -- ~
when 16#47e# => romdata <= X"48"; -- ~
when 16#57e# => romdata <= X"00"; -- ~
when 16#67e# => romdata <= X"00"; -- ~
when 16#77e# => romdata <= X"00"; -- ~
when 16#87e# => romdata <= X"00"; -- ~
when 16#97e# => romdata <= X"00"; -- ~
when 16#a7e# => romdata <= X"00"; -- ~
when 16#b7e# => romdata <= X"00"; -- ~
when 16#c7e# => romdata <= X"00"; -- ~
when 16#0a0# => romdata <= X"00"; --
when 16#1a0# => romdata <= X"00"; --
when 16#2a0# => romdata <= X"00"; --
when 16#3a0# => romdata <= X"00"; --
when 16#4a0# => romdata <= X"00"; --
when 16#5a0# => romdata <= X"00"; --
when 16#6a0# => romdata <= X"00"; --
when 16#7a0# => romdata <= X"00"; --
when 16#8a0# => romdata <= X"00"; --
when 16#9a0# => romdata <= X"00"; --
when 16#aa0# => romdata <= X"00"; --
when 16#ba0# => romdata <= X"00"; --
when 16#ca0# => romdata <= X"00"; --
when 16#0a1# => romdata <= X"00"; -- ¡
when 16#1a1# => romdata <= X"00"; -- ¡
when 16#2a1# => romdata <= X"10"; -- ¡
when 16#3a1# => romdata <= X"00"; -- ¡
when 16#4a1# => romdata <= X"10"; -- ¡
when 16#5a1# => romdata <= X"10"; -- ¡
when 16#6a1# => romdata <= X"10"; -- ¡
when 16#7a1# => romdata <= X"10"; -- ¡
when 16#8a1# => romdata <= X"10"; -- ¡
when 16#9a1# => romdata <= X"10"; -- ¡
when 16#aa1# => romdata <= X"10"; -- ¡
when 16#ba1# => romdata <= X"00"; -- ¡
when 16#ca1# => romdata <= X"00"; -- ¡
when 16#0a2# => romdata <= X"00"; -- ¢
when 16#1a2# => romdata <= X"00"; -- ¢
when 16#2a2# => romdata <= X"10"; -- ¢
when 16#3a2# => romdata <= X"38"; -- ¢
when 16#4a2# => romdata <= X"54"; -- ¢
when 16#5a2# => romdata <= X"50"; -- ¢
when 16#6a2# => romdata <= X"50"; -- ¢
when 16#7a2# => romdata <= X"54"; -- ¢
when 16#8a2# => romdata <= X"38"; -- ¢
when 16#9a2# => romdata <= X"10"; -- ¢
when 16#aa2# => romdata <= X"00"; -- ¢
when 16#ba2# => romdata <= X"00"; -- ¢
when 16#ca2# => romdata <= X"00"; -- ¢
when 16#0a3# => romdata <= X"00"; -- £
when 16#1a3# => romdata <= X"00"; -- £
when 16#2a3# => romdata <= X"1c"; -- £
when 16#3a3# => romdata <= X"22"; -- £
when 16#4a3# => romdata <= X"20"; -- £
when 16#5a3# => romdata <= X"70"; -- £
when 16#6a3# => romdata <= X"20"; -- £
when 16#7a3# => romdata <= X"20"; -- £
when 16#8a3# => romdata <= X"20"; -- £
when 16#9a3# => romdata <= X"62"; -- £
when 16#aa3# => romdata <= X"dc"; -- £
when 16#ba3# => romdata <= X"00"; -- £
when 16#ca3# => romdata <= X"00"; -- £
when 16#0a4# => romdata <= X"00"; -- ¤
when 16#1a4# => romdata <= X"00"; -- ¤
when 16#2a4# => romdata <= X"00"; -- ¤
when 16#3a4# => romdata <= X"00"; -- ¤
when 16#4a4# => romdata <= X"42"; -- ¤
when 16#5a4# => romdata <= X"3c"; -- ¤
when 16#6a4# => romdata <= X"24"; -- ¤
when 16#7a4# => romdata <= X"24"; -- ¤
when 16#8a4# => romdata <= X"3c"; -- ¤
when 16#9a4# => romdata <= X"42"; -- ¤
when 16#aa4# => romdata <= X"00"; -- ¤
when 16#ba4# => romdata <= X"00"; -- ¤
when 16#ca4# => romdata <= X"00"; -- ¤
when 16#0a5# => romdata <= X"00"; -- ¥
when 16#1a5# => romdata <= X"00"; -- ¥
when 16#2a5# => romdata <= X"82"; -- ¥
when 16#3a5# => romdata <= X"82"; -- ¥
when 16#4a5# => romdata <= X"44"; -- ¥
when 16#5a5# => romdata <= X"28"; -- ¥
when 16#6a5# => romdata <= X"7c"; -- ¥
when 16#7a5# => romdata <= X"10"; -- ¥
when 16#8a5# => romdata <= X"7c"; -- ¥
when 16#9a5# => romdata <= X"10"; -- ¥
when 16#aa5# => romdata <= X"10"; -- ¥
when 16#ba5# => romdata <= X"00"; -- ¥
when 16#ca5# => romdata <= X"00"; -- ¥
when 16#0a6# => romdata <= X"00"; -- ¦
when 16#1a6# => romdata <= X"00"; -- ¦
when 16#2a6# => romdata <= X"10"; -- ¦
when 16#3a6# => romdata <= X"10"; -- ¦
when 16#4a6# => romdata <= X"10"; -- ¦
when 16#5a6# => romdata <= X"10"; -- ¦
when 16#6a6# => romdata <= X"00"; -- ¦
when 16#7a6# => romdata <= X"10"; -- ¦
when 16#8a6# => romdata <= X"10"; -- ¦
when 16#9a6# => romdata <= X"10"; -- ¦
when 16#aa6# => romdata <= X"10"; -- ¦
when 16#ba6# => romdata <= X"00"; -- ¦
when 16#ca6# => romdata <= X"00"; -- ¦
when 16#0a7# => romdata <= X"00"; -- §
when 16#1a7# => romdata <= X"18"; -- §
when 16#2a7# => romdata <= X"24"; -- §
when 16#3a7# => romdata <= X"20"; -- §
when 16#4a7# => romdata <= X"18"; -- §
when 16#5a7# => romdata <= X"24"; -- §
when 16#6a7# => romdata <= X"24"; -- §
when 16#7a7# => romdata <= X"18"; -- §
when 16#8a7# => romdata <= X"04"; -- §
when 16#9a7# => romdata <= X"24"; -- §
when 16#aa7# => romdata <= X"18"; -- §
when 16#ba7# => romdata <= X"00"; -- §
when 16#ca7# => romdata <= X"00"; -- §
when 16#0a8# => romdata <= X"00"; -- ¨
when 16#1a8# => romdata <= X"24"; -- ¨
when 16#2a8# => romdata <= X"24"; -- ¨
when 16#3a8# => romdata <= X"00"; -- ¨
when 16#4a8# => romdata <= X"00"; -- ¨
when 16#5a8# => romdata <= X"00"; -- ¨
when 16#6a8# => romdata <= X"00"; -- ¨
when 16#7a8# => romdata <= X"00"; -- ¨
when 16#8a8# => romdata <= X"00"; -- ¨
when 16#9a8# => romdata <= X"00"; -- ¨
when 16#aa8# => romdata <= X"00"; -- ¨
when 16#ba8# => romdata <= X"00"; -- ¨
when 16#ca8# => romdata <= X"00"; -- ¨
when 16#0a9# => romdata <= X"00"; -- ©
when 16#1a9# => romdata <= X"38"; -- ©
when 16#2a9# => romdata <= X"44"; -- ©
when 16#3a9# => romdata <= X"92"; -- ©
when 16#4a9# => romdata <= X"aa"; -- ©
when 16#5a9# => romdata <= X"a2"; -- ©
when 16#6a9# => romdata <= X"aa"; -- ©
when 16#7a9# => romdata <= X"92"; -- ©
when 16#8a9# => romdata <= X"44"; -- ©
when 16#9a9# => romdata <= X"38"; -- ©
when 16#aa9# => romdata <= X"00"; -- ©
when 16#ba9# => romdata <= X"00"; -- ©
when 16#ca9# => romdata <= X"00"; -- ©
when 16#0aa# => romdata <= X"00"; -- ª
when 16#1aa# => romdata <= X"00"; -- ª
when 16#2aa# => romdata <= X"38"; -- ª
when 16#3aa# => romdata <= X"04"; -- ª
when 16#4aa# => romdata <= X"3c"; -- ª
when 16#5aa# => romdata <= X"44"; -- ª
when 16#6aa# => romdata <= X"3c"; -- ª
when 16#7aa# => romdata <= X"00"; -- ª
when 16#8aa# => romdata <= X"7c"; -- ª
when 16#9aa# => romdata <= X"00"; -- ª
when 16#aaa# => romdata <= X"00"; -- ª
when 16#baa# => romdata <= X"00"; -- ª
when 16#caa# => romdata <= X"00"; -- ª
when 16#0ab# => romdata <= X"00"; -- «
when 16#1ab# => romdata <= X"00"; -- «
when 16#2ab# => romdata <= X"00"; -- «
when 16#3ab# => romdata <= X"12"; -- «
when 16#4ab# => romdata <= X"24"; -- «
when 16#5ab# => romdata <= X"48"; -- «
when 16#6ab# => romdata <= X"90"; -- «
when 16#7ab# => romdata <= X"48"; -- «
when 16#8ab# => romdata <= X"24"; -- «
when 16#9ab# => romdata <= X"12"; -- «
when 16#aab# => romdata <= X"00"; -- «
when 16#bab# => romdata <= X"00"; -- «
when 16#cab# => romdata <= X"00"; -- «
when 16#0ac# => romdata <= X"00"; -- ¬
when 16#1ac# => romdata <= X"00"; -- ¬
when 16#2ac# => romdata <= X"00"; -- ¬
when 16#3ac# => romdata <= X"00"; -- ¬
when 16#4ac# => romdata <= X"00"; -- ¬
when 16#5ac# => romdata <= X"00"; -- ¬
when 16#6ac# => romdata <= X"7e"; -- ¬
when 16#7ac# => romdata <= X"02"; -- ¬
when 16#8ac# => romdata <= X"02"; -- ¬
when 16#9ac# => romdata <= X"02"; -- ¬
when 16#aac# => romdata <= X"00"; -- ¬
when 16#bac# => romdata <= X"00"; -- ¬
when 16#cac# => romdata <= X"00"; -- ¬
when 16#0ad# => romdata <= X"00"; --
when 16#1ad# => romdata <= X"00"; --
when 16#2ad# => romdata <= X"00"; --
when 16#3ad# => romdata <= X"00"; --
when 16#4ad# => romdata <= X"00"; --
when 16#5ad# => romdata <= X"00"; --
when 16#6ad# => romdata <= X"3c"; --
when 16#7ad# => romdata <= X"00"; --
when 16#8ad# => romdata <= X"00"; --
when 16#9ad# => romdata <= X"00"; --
when 16#aad# => romdata <= X"00"; --
when 16#bad# => romdata <= X"00"; --
when 16#cad# => romdata <= X"00"; --
when 16#0ae# => romdata <= X"00"; -- ®
when 16#1ae# => romdata <= X"38"; -- ®
when 16#2ae# => romdata <= X"44"; -- ®
when 16#3ae# => romdata <= X"92"; -- ®
when 16#4ae# => romdata <= X"aa"; -- ®
when 16#5ae# => romdata <= X"aa"; -- ®
when 16#6ae# => romdata <= X"b2"; -- ®
when 16#7ae# => romdata <= X"aa"; -- ®
when 16#8ae# => romdata <= X"44"; -- ®
when 16#9ae# => romdata <= X"38"; -- ®
when 16#aae# => romdata <= X"00"; -- ®
when 16#bae# => romdata <= X"00"; -- ®
when 16#cae# => romdata <= X"00"; -- ®
when 16#0af# => romdata <= X"00"; -- ¯
when 16#1af# => romdata <= X"00"; -- ¯
when 16#2af# => romdata <= X"7e"; -- ¯
when 16#3af# => romdata <= X"00"; -- ¯
when 16#4af# => romdata <= X"00"; -- ¯
when 16#5af# => romdata <= X"00"; -- ¯
when 16#6af# => romdata <= X"00"; -- ¯
when 16#7af# => romdata <= X"00"; -- ¯
when 16#8af# => romdata <= X"00"; -- ¯
when 16#9af# => romdata <= X"00"; -- ¯
when 16#aaf# => romdata <= X"00"; -- ¯
when 16#baf# => romdata <= X"00"; -- ¯
when 16#caf# => romdata <= X"00"; -- ¯
when 16#0b0# => romdata <= X"00"; -- °
when 16#1b0# => romdata <= X"00"; -- °
when 16#2b0# => romdata <= X"18"; -- °
when 16#3b0# => romdata <= X"24"; -- °
when 16#4b0# => romdata <= X"24"; -- °
when 16#5b0# => romdata <= X"18"; -- °
when 16#6b0# => romdata <= X"00"; -- °
when 16#7b0# => romdata <= X"00"; -- °
when 16#8b0# => romdata <= X"00"; -- °
when 16#9b0# => romdata <= X"00"; -- °
when 16#ab0# => romdata <= X"00"; -- °
when 16#bb0# => romdata <= X"00"; -- °
when 16#cb0# => romdata <= X"00"; -- °
when 16#0b1# => romdata <= X"00"; -- ±
when 16#1b1# => romdata <= X"00"; -- ±
when 16#2b1# => romdata <= X"00"; -- ±
when 16#3b1# => romdata <= X"10"; -- ±
when 16#4b1# => romdata <= X"10"; -- ±
when 16#5b1# => romdata <= X"7c"; -- ±
when 16#6b1# => romdata <= X"10"; -- ±
when 16#7b1# => romdata <= X"10"; -- ±
when 16#8b1# => romdata <= X"00"; -- ±
when 16#9b1# => romdata <= X"7c"; -- ±
when 16#ab1# => romdata <= X"00"; -- ±
when 16#bb1# => romdata <= X"00"; -- ±
when 16#cb1# => romdata <= X"00"; -- ±
when 16#0b2# => romdata <= X"00"; -- ²
when 16#1b2# => romdata <= X"30"; -- ²
when 16#2b2# => romdata <= X"48"; -- ²
when 16#3b2# => romdata <= X"08"; -- ²
when 16#4b2# => romdata <= X"30"; -- ²
when 16#5b2# => romdata <= X"40"; -- ²
when 16#6b2# => romdata <= X"78"; -- ²
when 16#7b2# => romdata <= X"00"; -- ²
when 16#8b2# => romdata <= X"00"; -- ²
when 16#9b2# => romdata <= X"00"; -- ²
when 16#ab2# => romdata <= X"00"; -- ²
when 16#bb2# => romdata <= X"00"; -- ²
when 16#cb2# => romdata <= X"00"; -- ²
when 16#0b3# => romdata <= X"00"; -- ³
when 16#1b3# => romdata <= X"30"; -- ³
when 16#2b3# => romdata <= X"48"; -- ³
when 16#3b3# => romdata <= X"10"; -- ³
when 16#4b3# => romdata <= X"08"; -- ³
when 16#5b3# => romdata <= X"48"; -- ³
when 16#6b3# => romdata <= X"30"; -- ³
when 16#7b3# => romdata <= X"00"; -- ³
when 16#8b3# => romdata <= X"00"; -- ³
when 16#9b3# => romdata <= X"00"; -- ³
when 16#ab3# => romdata <= X"00"; -- ³
when 16#bb3# => romdata <= X"00"; -- ³
when 16#cb3# => romdata <= X"00"; -- ³
when 16#0b4# => romdata <= X"00"; -- ´
when 16#1b4# => romdata <= X"08"; -- ´
when 16#2b4# => romdata <= X"10"; -- ´
when 16#3b4# => romdata <= X"00"; -- ´
when 16#4b4# => romdata <= X"00"; -- ´
when 16#5b4# => romdata <= X"00"; -- ´
when 16#6b4# => romdata <= X"00"; -- ´
when 16#7b4# => romdata <= X"00"; -- ´
when 16#8b4# => romdata <= X"00"; -- ´
when 16#9b4# => romdata <= X"00"; -- ´
when 16#ab4# => romdata <= X"00"; -- ´
when 16#bb4# => romdata <= X"00"; -- ´
when 16#cb4# => romdata <= X"00"; -- ´
when 16#0b5# => romdata <= X"00"; -- µ
when 16#1b5# => romdata <= X"00"; -- µ
when 16#2b5# => romdata <= X"00"; -- µ
when 16#3b5# => romdata <= X"00"; -- µ
when 16#4b5# => romdata <= X"00"; -- µ
when 16#5b5# => romdata <= X"42"; -- µ
when 16#6b5# => romdata <= X"42"; -- µ
when 16#7b5# => romdata <= X"42"; -- µ
when 16#8b5# => romdata <= X"42"; -- µ
when 16#9b5# => romdata <= X"66"; -- µ
when 16#ab5# => romdata <= X"5a"; -- µ
when 16#bb5# => romdata <= X"40"; -- µ
when 16#cb5# => romdata <= X"00"; -- µ
when 16#0b6# => romdata <= X"00"; -- ¶
when 16#1b6# => romdata <= X"00"; -- ¶
when 16#2b6# => romdata <= X"3e"; -- ¶
when 16#3b6# => romdata <= X"74"; -- ¶
when 16#4b6# => romdata <= X"74"; -- ¶
when 16#5b6# => romdata <= X"74"; -- ¶
when 16#6b6# => romdata <= X"34"; -- ¶
when 16#7b6# => romdata <= X"14"; -- ¶
when 16#8b6# => romdata <= X"14"; -- ¶
when 16#9b6# => romdata <= X"14"; -- ¶
when 16#ab6# => romdata <= X"14"; -- ¶
when 16#bb6# => romdata <= X"00"; -- ¶
when 16#cb6# => romdata <= X"00"; -- ¶
when 16#0b7# => romdata <= X"00"; -- ·
when 16#1b7# => romdata <= X"00"; -- ·
when 16#2b7# => romdata <= X"00"; -- ·
when 16#3b7# => romdata <= X"00"; -- ·
when 16#4b7# => romdata <= X"00"; -- ·
when 16#5b7# => romdata <= X"00"; -- ·
when 16#6b7# => romdata <= X"18"; -- ·
when 16#7b7# => romdata <= X"00"; -- ·
when 16#8b7# => romdata <= X"00"; -- ·
when 16#9b7# => romdata <= X"00"; -- ·
when 16#ab7# => romdata <= X"00"; -- ·
when 16#bb7# => romdata <= X"00"; -- ·
when 16#cb7# => romdata <= X"00"; -- ·
when 16#0b8# => romdata <= X"00"; -- ¸
when 16#1b8# => romdata <= X"00"; -- ¸
when 16#2b8# => romdata <= X"00"; -- ¸
when 16#3b8# => romdata <= X"00"; -- ¸
when 16#4b8# => romdata <= X"00"; -- ¸
when 16#5b8# => romdata <= X"00"; -- ¸
when 16#6b8# => romdata <= X"00"; -- ¸
when 16#7b8# => romdata <= X"00"; -- ¸
when 16#8b8# => romdata <= X"00"; -- ¸
when 16#9b8# => romdata <= X"00"; -- ¸
when 16#ab8# => romdata <= X"00"; -- ¸
when 16#bb8# => romdata <= X"08"; -- ¸
when 16#cb8# => romdata <= X"18"; -- ¸
when 16#0b9# => romdata <= X"00"; -- ¹
when 16#1b9# => romdata <= X"20"; -- ¹
when 16#2b9# => romdata <= X"60"; -- ¹
when 16#3b9# => romdata <= X"20"; -- ¹
when 16#4b9# => romdata <= X"20"; -- ¹
when 16#5b9# => romdata <= X"20"; -- ¹
when 16#6b9# => romdata <= X"70"; -- ¹
when 16#7b9# => romdata <= X"00"; -- ¹
when 16#8b9# => romdata <= X"00"; -- ¹
when 16#9b9# => romdata <= X"00"; -- ¹
when 16#ab9# => romdata <= X"00"; -- ¹
when 16#bb9# => romdata <= X"00"; -- ¹
when 16#cb9# => romdata <= X"00"; -- ¹
when 16#0ba# => romdata <= X"00"; -- º
when 16#1ba# => romdata <= X"00"; -- º
when 16#2ba# => romdata <= X"30"; -- º
when 16#3ba# => romdata <= X"48"; -- º
when 16#4ba# => romdata <= X"48"; -- º
when 16#5ba# => romdata <= X"30"; -- º
when 16#6ba# => romdata <= X"00"; -- º
when 16#7ba# => romdata <= X"78"; -- º
when 16#8ba# => romdata <= X"00"; -- º
when 16#9ba# => romdata <= X"00"; -- º
when 16#aba# => romdata <= X"00"; -- º
when 16#bba# => romdata <= X"00"; -- º
when 16#cba# => romdata <= X"00"; -- º
when 16#0bb# => romdata <= X"00"; -- »
when 16#1bb# => romdata <= X"00"; -- »
when 16#2bb# => romdata <= X"00"; -- »
when 16#3bb# => romdata <= X"90"; -- »
when 16#4bb# => romdata <= X"48"; -- »
when 16#5bb# => romdata <= X"24"; -- »
when 16#6bb# => romdata <= X"12"; -- »
when 16#7bb# => romdata <= X"24"; -- »
when 16#8bb# => romdata <= X"48"; -- »
when 16#9bb# => romdata <= X"90"; -- »
when 16#abb# => romdata <= X"00"; -- »
when 16#bbb# => romdata <= X"00"; -- »
when 16#cbb# => romdata <= X"00"; -- »
when 16#0bc# => romdata <= X"00"; -- ¼
when 16#1bc# => romdata <= X"40"; -- ¼
when 16#2bc# => romdata <= X"c0"; -- ¼
when 16#3bc# => romdata <= X"40"; -- ¼
when 16#4bc# => romdata <= X"40"; -- ¼
when 16#5bc# => romdata <= X"42"; -- ¼
when 16#6bc# => romdata <= X"e6"; -- ¼
when 16#7bc# => romdata <= X"0a"; -- ¼
when 16#8bc# => romdata <= X"12"; -- ¼
when 16#9bc# => romdata <= X"1a"; -- ¼
when 16#abc# => romdata <= X"06"; -- ¼
when 16#bbc# => romdata <= X"00"; -- ¼
when 16#cbc# => romdata <= X"00"; -- ¼
when 16#0bd# => romdata <= X"00"; -- ½
when 16#1bd# => romdata <= X"40"; -- ½
when 16#2bd# => romdata <= X"c0"; -- ½
when 16#3bd# => romdata <= X"40"; -- ½
when 16#4bd# => romdata <= X"40"; -- ½
when 16#5bd# => romdata <= X"4c"; -- ½
when 16#6bd# => romdata <= X"f2"; -- ½
when 16#7bd# => romdata <= X"02"; -- ½
when 16#8bd# => romdata <= X"0c"; -- ½
when 16#9bd# => romdata <= X"10"; -- ½
when 16#abd# => romdata <= X"1e"; -- ½
when 16#bbd# => romdata <= X"00"; -- ½
when 16#cbd# => romdata <= X"00"; -- ½
when 16#0be# => romdata <= X"00"; -- ¾
when 16#1be# => romdata <= X"60"; -- ¾
when 16#2be# => romdata <= X"90"; -- ¾
when 16#3be# => romdata <= X"20"; -- ¾
when 16#4be# => romdata <= X"10"; -- ¾
when 16#5be# => romdata <= X"92"; -- ¾
when 16#6be# => romdata <= X"66"; -- ¾
when 16#7be# => romdata <= X"0a"; -- ¾
when 16#8be# => romdata <= X"12"; -- ¾
when 16#9be# => romdata <= X"1a"; -- ¾
when 16#abe# => romdata <= X"06"; -- ¾
when 16#bbe# => romdata <= X"00"; -- ¾
when 16#cbe# => romdata <= X"00"; -- ¾
when 16#0bf# => romdata <= X"00"; -- ¿
when 16#1bf# => romdata <= X"00"; -- ¿
when 16#2bf# => romdata <= X"10"; -- ¿
when 16#3bf# => romdata <= X"00"; -- ¿
when 16#4bf# => romdata <= X"10"; -- ¿
when 16#5bf# => romdata <= X"10"; -- ¿
when 16#6bf# => romdata <= X"20"; -- ¿
when 16#7bf# => romdata <= X"40"; -- ¿
when 16#8bf# => romdata <= X"42"; -- ¿
when 16#9bf# => romdata <= X"42"; -- ¿
when 16#abf# => romdata <= X"3c"; -- ¿
when 16#bbf# => romdata <= X"00"; -- ¿
when 16#cbf# => romdata <= X"00"; -- ¿
when 16#0c0# => romdata <= X"00"; -- À
when 16#1c0# => romdata <= X"10"; -- À
when 16#2c0# => romdata <= X"08"; -- À
when 16#3c0# => romdata <= X"00"; -- À
when 16#4c0# => romdata <= X"18"; -- À
when 16#5c0# => romdata <= X"24"; -- À
when 16#6c0# => romdata <= X"42"; -- À
when 16#7c0# => romdata <= X"42"; -- À
when 16#8c0# => romdata <= X"7e"; -- À
when 16#9c0# => romdata <= X"42"; -- À
when 16#ac0# => romdata <= X"42"; -- À
when 16#bc0# => romdata <= X"00"; -- À
when 16#cc0# => romdata <= X"00"; -- À
when 16#0c1# => romdata <= X"00"; -- Á
when 16#1c1# => romdata <= X"08"; -- Á
when 16#2c1# => romdata <= X"10"; -- Á
when 16#3c1# => romdata <= X"00"; -- Á
when 16#4c1# => romdata <= X"18"; -- Á
when 16#5c1# => romdata <= X"24"; -- Á
when 16#6c1# => romdata <= X"42"; -- Á
when 16#7c1# => romdata <= X"42"; -- Á
when 16#8c1# => romdata <= X"7e"; -- Á
when 16#9c1# => romdata <= X"42"; -- Á
when 16#ac1# => romdata <= X"42"; -- Á
when 16#bc1# => romdata <= X"00"; -- Á
when 16#cc1# => romdata <= X"00"; -- Á
when 16#0c2# => romdata <= X"00"; -- Â
when 16#1c2# => romdata <= X"18"; -- Â
when 16#2c2# => romdata <= X"24"; -- Â
when 16#3c2# => romdata <= X"00"; -- Â
when 16#4c2# => romdata <= X"18"; -- Â
when 16#5c2# => romdata <= X"24"; -- Â
when 16#6c2# => romdata <= X"42"; -- Â
when 16#7c2# => romdata <= X"42"; -- Â
when 16#8c2# => romdata <= X"7e"; -- Â
when 16#9c2# => romdata <= X"42"; -- Â
when 16#ac2# => romdata <= X"42"; -- Â
when 16#bc2# => romdata <= X"00"; -- Â
when 16#cc2# => romdata <= X"00"; -- Â
when 16#0c3# => romdata <= X"00"; -- Ã
when 16#1c3# => romdata <= X"32"; -- Ã
when 16#2c3# => romdata <= X"4c"; -- Ã
when 16#3c3# => romdata <= X"00"; -- Ã
when 16#4c3# => romdata <= X"18"; -- Ã
when 16#5c3# => romdata <= X"24"; -- Ã
when 16#6c3# => romdata <= X"42"; -- Ã
when 16#7c3# => romdata <= X"42"; -- Ã
when 16#8c3# => romdata <= X"7e"; -- Ã
when 16#9c3# => romdata <= X"42"; -- Ã
when 16#ac3# => romdata <= X"42"; -- Ã
when 16#bc3# => romdata <= X"00"; -- Ã
when 16#cc3# => romdata <= X"00"; -- Ã
when 16#0c4# => romdata <= X"00"; -- Ä
when 16#1c4# => romdata <= X"24"; -- Ä
when 16#2c4# => romdata <= X"24"; -- Ä
when 16#3c4# => romdata <= X"00"; -- Ä
when 16#4c4# => romdata <= X"18"; -- Ä
when 16#5c4# => romdata <= X"24"; -- Ä
when 16#6c4# => romdata <= X"42"; -- Ä
when 16#7c4# => romdata <= X"42"; -- Ä
when 16#8c4# => romdata <= X"7e"; -- Ä
when 16#9c4# => romdata <= X"42"; -- Ä
when 16#ac4# => romdata <= X"42"; -- Ä
when 16#bc4# => romdata <= X"00"; -- Ä
when 16#cc4# => romdata <= X"00"; -- Ä
when 16#0c5# => romdata <= X"00"; -- Å
when 16#1c5# => romdata <= X"18"; -- Å
when 16#2c5# => romdata <= X"24"; -- Å
when 16#3c5# => romdata <= X"18"; -- Å
when 16#4c5# => romdata <= X"18"; -- Å
when 16#5c5# => romdata <= X"24"; -- Å
when 16#6c5# => romdata <= X"42"; -- Å
when 16#7c5# => romdata <= X"42"; -- Å
when 16#8c5# => romdata <= X"7e"; -- Å
when 16#9c5# => romdata <= X"42"; -- Å
when 16#ac5# => romdata <= X"42"; -- Å
when 16#bc5# => romdata <= X"00"; -- Å
when 16#cc5# => romdata <= X"00"; -- Å
when 16#0c6# => romdata <= X"00"; -- Æ
when 16#1c6# => romdata <= X"00"; -- Æ
when 16#2c6# => romdata <= X"6e"; -- Æ
when 16#3c6# => romdata <= X"90"; -- Æ
when 16#4c6# => romdata <= X"90"; -- Æ
when 16#5c6# => romdata <= X"90"; -- Æ
when 16#6c6# => romdata <= X"9c"; -- Æ
when 16#7c6# => romdata <= X"f0"; -- Æ
when 16#8c6# => romdata <= X"90"; -- Æ
when 16#9c6# => romdata <= X"90"; -- Æ
when 16#ac6# => romdata <= X"9e"; -- Æ
when 16#bc6# => romdata <= X"00"; -- Æ
when 16#cc6# => romdata <= X"00"; -- Æ
when 16#0c7# => romdata <= X"00"; -- Ç
when 16#1c7# => romdata <= X"00"; -- Ç
when 16#2c7# => romdata <= X"3c"; -- Ç
when 16#3c7# => romdata <= X"42"; -- Ç
when 16#4c7# => romdata <= X"40"; -- Ç
when 16#5c7# => romdata <= X"40"; -- Ç
when 16#6c7# => romdata <= X"40"; -- Ç
when 16#7c7# => romdata <= X"40"; -- Ç
when 16#8c7# => romdata <= X"40"; -- Ç
when 16#9c7# => romdata <= X"42"; -- Ç
when 16#ac7# => romdata <= X"3c"; -- Ç
when 16#bc7# => romdata <= X"08"; -- Ç
when 16#cc7# => romdata <= X"10"; -- Ç
when 16#0c8# => romdata <= X"00"; -- È
when 16#1c8# => romdata <= X"10"; -- È
when 16#2c8# => romdata <= X"08"; -- È
when 16#3c8# => romdata <= X"00"; -- È
when 16#4c8# => romdata <= X"7e"; -- È
when 16#5c8# => romdata <= X"40"; -- È
when 16#6c8# => romdata <= X"40"; -- È
when 16#7c8# => romdata <= X"78"; -- È
when 16#8c8# => romdata <= X"40"; -- È
when 16#9c8# => romdata <= X"40"; -- È
when 16#ac8# => romdata <= X"7e"; -- È
when 16#bc8# => romdata <= X"00"; -- È
when 16#cc8# => romdata <= X"00"; -- È
when 16#0c9# => romdata <= X"00"; -- É
when 16#1c9# => romdata <= X"08"; -- É
when 16#2c9# => romdata <= X"10"; -- É
when 16#3c9# => romdata <= X"00"; -- É
when 16#4c9# => romdata <= X"7e"; -- É
when 16#5c9# => romdata <= X"40"; -- É
when 16#6c9# => romdata <= X"40"; -- É
when 16#7c9# => romdata <= X"78"; -- É
when 16#8c9# => romdata <= X"40"; -- É
when 16#9c9# => romdata <= X"40"; -- É
when 16#ac9# => romdata <= X"7e"; -- É
when 16#bc9# => romdata <= X"00"; -- É
when 16#cc9# => romdata <= X"00"; -- É
when 16#0ca# => romdata <= X"00"; -- Ê
when 16#1ca# => romdata <= X"18"; -- Ê
when 16#2ca# => romdata <= X"24"; -- Ê
when 16#3ca# => romdata <= X"00"; -- Ê
when 16#4ca# => romdata <= X"7e"; -- Ê
when 16#5ca# => romdata <= X"40"; -- Ê
when 16#6ca# => romdata <= X"40"; -- Ê
when 16#7ca# => romdata <= X"78"; -- Ê
when 16#8ca# => romdata <= X"40"; -- Ê
when 16#9ca# => romdata <= X"40"; -- Ê
when 16#aca# => romdata <= X"7e"; -- Ê
when 16#bca# => romdata <= X"00"; -- Ê
when 16#cca# => romdata <= X"00"; -- Ê
when 16#0cb# => romdata <= X"00"; -- Ë
when 16#1cb# => romdata <= X"24"; -- Ë
when 16#2cb# => romdata <= X"24"; -- Ë
when 16#3cb# => romdata <= X"00"; -- Ë
when 16#4cb# => romdata <= X"7e"; -- Ë
when 16#5cb# => romdata <= X"40"; -- Ë
when 16#6cb# => romdata <= X"40"; -- Ë
when 16#7cb# => romdata <= X"78"; -- Ë
when 16#8cb# => romdata <= X"40"; -- Ë
when 16#9cb# => romdata <= X"40"; -- Ë
when 16#acb# => romdata <= X"7e"; -- Ë
when 16#bcb# => romdata <= X"00"; -- Ë
when 16#ccb# => romdata <= X"00"; -- Ë
when 16#0cc# => romdata <= X"00"; -- Ì
when 16#1cc# => romdata <= X"20"; -- Ì
when 16#2cc# => romdata <= X"10"; -- Ì
when 16#3cc# => romdata <= X"00"; -- Ì
when 16#4cc# => romdata <= X"7c"; -- Ì
when 16#5cc# => romdata <= X"10"; -- Ì
when 16#6cc# => romdata <= X"10"; -- Ì
when 16#7cc# => romdata <= X"10"; -- Ì
when 16#8cc# => romdata <= X"10"; -- Ì
when 16#9cc# => romdata <= X"10"; -- Ì
when 16#acc# => romdata <= X"7c"; -- Ì
when 16#bcc# => romdata <= X"00"; -- Ì
when 16#ccc# => romdata <= X"00"; -- Ì
when 16#0cd# => romdata <= X"00"; -- Í
when 16#1cd# => romdata <= X"08"; -- Í
when 16#2cd# => romdata <= X"10"; -- Í
when 16#3cd# => romdata <= X"00"; -- Í
when 16#4cd# => romdata <= X"7c"; -- Í
when 16#5cd# => romdata <= X"10"; -- Í
when 16#6cd# => romdata <= X"10"; -- Í
when 16#7cd# => romdata <= X"10"; -- Í
when 16#8cd# => romdata <= X"10"; -- Í
when 16#9cd# => romdata <= X"10"; -- Í
when 16#acd# => romdata <= X"7c"; -- Í
when 16#bcd# => romdata <= X"00"; -- Í
when 16#ccd# => romdata <= X"00"; -- Í
when 16#0ce# => romdata <= X"00"; -- Î
when 16#1ce# => romdata <= X"18"; -- Î
when 16#2ce# => romdata <= X"24"; -- Î
when 16#3ce# => romdata <= X"00"; -- Î
when 16#4ce# => romdata <= X"7c"; -- Î
when 16#5ce# => romdata <= X"10"; -- Î
when 16#6ce# => romdata <= X"10"; -- Î
when 16#7ce# => romdata <= X"10"; -- Î
when 16#8ce# => romdata <= X"10"; -- Î
when 16#9ce# => romdata <= X"10"; -- Î
when 16#ace# => romdata <= X"7c"; -- Î
when 16#bce# => romdata <= X"00"; -- Î
when 16#cce# => romdata <= X"00"; -- Î
when 16#0cf# => romdata <= X"00"; -- Ï
when 16#1cf# => romdata <= X"44"; -- Ï
when 16#2cf# => romdata <= X"44"; -- Ï
when 16#3cf# => romdata <= X"00"; -- Ï
when 16#4cf# => romdata <= X"7c"; -- Ï
when 16#5cf# => romdata <= X"10"; -- Ï
when 16#6cf# => romdata <= X"10"; -- Ï
when 16#7cf# => romdata <= X"10"; -- Ï
when 16#8cf# => romdata <= X"10"; -- Ï
when 16#9cf# => romdata <= X"10"; -- Ï
when 16#acf# => romdata <= X"7c"; -- Ï
when 16#bcf# => romdata <= X"00"; -- Ï
when 16#ccf# => romdata <= X"00"; -- Ï
when 16#0d0# => romdata <= X"00"; -- Ð
when 16#1d0# => romdata <= X"00"; -- Ð
when 16#2d0# => romdata <= X"78"; -- Ð
when 16#3d0# => romdata <= X"44"; -- Ð
when 16#4d0# => romdata <= X"42"; -- Ð
when 16#5d0# => romdata <= X"42"; -- Ð
when 16#6d0# => romdata <= X"e2"; -- Ð
when 16#7d0# => romdata <= X"42"; -- Ð
when 16#8d0# => romdata <= X"42"; -- Ð
when 16#9d0# => romdata <= X"44"; -- Ð
when 16#ad0# => romdata <= X"78"; -- Ð
when 16#bd0# => romdata <= X"00"; -- Ð
when 16#cd0# => romdata <= X"00"; -- Ð
when 16#0d1# => romdata <= X"00"; -- Ñ
when 16#1d1# => romdata <= X"64"; -- Ñ
when 16#2d1# => romdata <= X"98"; -- Ñ
when 16#3d1# => romdata <= X"00"; -- Ñ
when 16#4d1# => romdata <= X"82"; -- Ñ
when 16#5d1# => romdata <= X"c2"; -- Ñ
when 16#6d1# => romdata <= X"a2"; -- Ñ
when 16#7d1# => romdata <= X"92"; -- Ñ
when 16#8d1# => romdata <= X"8a"; -- Ñ
when 16#9d1# => romdata <= X"86"; -- Ñ
when 16#ad1# => romdata <= X"82"; -- Ñ
when 16#bd1# => romdata <= X"00"; -- Ñ
when 16#cd1# => romdata <= X"00"; -- Ñ
when 16#0d2# => romdata <= X"00"; -- Ò
when 16#1d2# => romdata <= X"20"; -- Ò
when 16#2d2# => romdata <= X"10"; -- Ò
when 16#3d2# => romdata <= X"00"; -- Ò
when 16#4d2# => romdata <= X"7c"; -- Ò
when 16#5d2# => romdata <= X"82"; -- Ò
when 16#6d2# => romdata <= X"82"; -- Ò
when 16#7d2# => romdata <= X"82"; -- Ò
when 16#8d2# => romdata <= X"82"; -- Ò
when 16#9d2# => romdata <= X"82"; -- Ò
when 16#ad2# => romdata <= X"7c"; -- Ò
when 16#bd2# => romdata <= X"00"; -- Ò
when 16#cd2# => romdata <= X"00"; -- Ò
when 16#0d3# => romdata <= X"00"; -- Ó
when 16#1d3# => romdata <= X"08"; -- Ó
when 16#2d3# => romdata <= X"10"; -- Ó
when 16#3d3# => romdata <= X"00"; -- Ó
when 16#4d3# => romdata <= X"7c"; -- Ó
when 16#5d3# => romdata <= X"82"; -- Ó
when 16#6d3# => romdata <= X"82"; -- Ó
when 16#7d3# => romdata <= X"82"; -- Ó
when 16#8d3# => romdata <= X"82"; -- Ó
when 16#9d3# => romdata <= X"82"; -- Ó
when 16#ad3# => romdata <= X"7c"; -- Ó
when 16#bd3# => romdata <= X"00"; -- Ó
when 16#cd3# => romdata <= X"00"; -- Ó
when 16#0d4# => romdata <= X"00"; -- Ô
when 16#1d4# => romdata <= X"18"; -- Ô
when 16#2d4# => romdata <= X"24"; -- Ô
when 16#3d4# => romdata <= X"00"; -- Ô
when 16#4d4# => romdata <= X"7c"; -- Ô
when 16#5d4# => romdata <= X"82"; -- Ô
when 16#6d4# => romdata <= X"82"; -- Ô
when 16#7d4# => romdata <= X"82"; -- Ô
when 16#8d4# => romdata <= X"82"; -- Ô
when 16#9d4# => romdata <= X"82"; -- Ô
when 16#ad4# => romdata <= X"7c"; -- Ô
when 16#bd4# => romdata <= X"00"; -- Ô
when 16#cd4# => romdata <= X"00"; -- Ô
when 16#0d5# => romdata <= X"00"; -- Õ
when 16#1d5# => romdata <= X"64"; -- Õ
when 16#2d5# => romdata <= X"98"; -- Õ
when 16#3d5# => romdata <= X"00"; -- Õ
when 16#4d5# => romdata <= X"7c"; -- Õ
when 16#5d5# => romdata <= X"82"; -- Õ
when 16#6d5# => romdata <= X"82"; -- Õ
when 16#7d5# => romdata <= X"82"; -- Õ
when 16#8d5# => romdata <= X"82"; -- Õ
when 16#9d5# => romdata <= X"82"; -- Õ
when 16#ad5# => romdata <= X"7c"; -- Õ
when 16#bd5# => romdata <= X"00"; -- Õ
when 16#cd5# => romdata <= X"00"; -- Õ
when 16#0d6# => romdata <= X"00"; -- Ö
when 16#1d6# => romdata <= X"44"; -- Ö
when 16#2d6# => romdata <= X"44"; -- Ö
when 16#3d6# => romdata <= X"00"; -- Ö
when 16#4d6# => romdata <= X"7c"; -- Ö
when 16#5d6# => romdata <= X"82"; -- Ö
when 16#6d6# => romdata <= X"82"; -- Ö
when 16#7d6# => romdata <= X"82"; -- Ö
when 16#8d6# => romdata <= X"82"; -- Ö
when 16#9d6# => romdata <= X"82"; -- Ö
when 16#ad6# => romdata <= X"7c"; -- Ö
when 16#bd6# => romdata <= X"00"; -- Ö
when 16#cd6# => romdata <= X"00"; -- Ö
when 16#0d7# => romdata <= X"00"; -- ×
when 16#1d7# => romdata <= X"00"; -- ×
when 16#2d7# => romdata <= X"00"; -- ×
when 16#3d7# => romdata <= X"00"; -- ×
when 16#4d7# => romdata <= X"42"; -- ×
when 16#5d7# => romdata <= X"24"; -- ×
when 16#6d7# => romdata <= X"18"; -- ×
when 16#7d7# => romdata <= X"18"; -- ×
when 16#8d7# => romdata <= X"24"; -- ×
when 16#9d7# => romdata <= X"42"; -- ×
when 16#ad7# => romdata <= X"00"; -- ×
when 16#bd7# => romdata <= X"00"; -- ×
when 16#cd7# => romdata <= X"00"; -- ×
when 16#0d8# => romdata <= X"00"; -- Ø
when 16#1d8# => romdata <= X"02"; -- Ø
when 16#2d8# => romdata <= X"3c"; -- Ø
when 16#3d8# => romdata <= X"46"; -- Ø
when 16#4d8# => romdata <= X"4a"; -- Ø
when 16#5d8# => romdata <= X"4a"; -- Ø
when 16#6d8# => romdata <= X"52"; -- Ø
when 16#7d8# => romdata <= X"52"; -- Ø
when 16#8d8# => romdata <= X"52"; -- Ø
when 16#9d8# => romdata <= X"62"; -- Ø
when 16#ad8# => romdata <= X"3c"; -- Ø
when 16#bd8# => romdata <= X"40"; -- Ø
when 16#cd8# => romdata <= X"00"; -- Ø
when 16#0d9# => romdata <= X"00"; -- Ù
when 16#1d9# => romdata <= X"20"; -- Ù
when 16#2d9# => romdata <= X"10"; -- Ù
when 16#3d9# => romdata <= X"00"; -- Ù
when 16#4d9# => romdata <= X"42"; -- Ù
when 16#5d9# => romdata <= X"42"; -- Ù
when 16#6d9# => romdata <= X"42"; -- Ù
when 16#7d9# => romdata <= X"42"; -- Ù
when 16#8d9# => romdata <= X"42"; -- Ù
when 16#9d9# => romdata <= X"42"; -- Ù
when 16#ad9# => romdata <= X"3c"; -- Ù
when 16#bd9# => romdata <= X"00"; -- Ù
when 16#cd9# => romdata <= X"00"; -- Ù
when 16#0da# => romdata <= X"00"; -- Ú
when 16#1da# => romdata <= X"08"; -- Ú
when 16#2da# => romdata <= X"10"; -- Ú
when 16#3da# => romdata <= X"00"; -- Ú
when 16#4da# => romdata <= X"42"; -- Ú
when 16#5da# => romdata <= X"42"; -- Ú
when 16#6da# => romdata <= X"42"; -- Ú
when 16#7da# => romdata <= X"42"; -- Ú
when 16#8da# => romdata <= X"42"; -- Ú
when 16#9da# => romdata <= X"42"; -- Ú
when 16#ada# => romdata <= X"3c"; -- Ú
when 16#bda# => romdata <= X"00"; -- Ú
when 16#cda# => romdata <= X"00"; -- Ú
when 16#0db# => romdata <= X"00"; -- Û
when 16#1db# => romdata <= X"18"; -- Û
when 16#2db# => romdata <= X"24"; -- Û
when 16#3db# => romdata <= X"00"; -- Û
when 16#4db# => romdata <= X"42"; -- Û
when 16#5db# => romdata <= X"42"; -- Û
when 16#6db# => romdata <= X"42"; -- Û
when 16#7db# => romdata <= X"42"; -- Û
when 16#8db# => romdata <= X"42"; -- Û
when 16#9db# => romdata <= X"42"; -- Û
when 16#adb# => romdata <= X"3c"; -- Û
when 16#bdb# => romdata <= X"00"; -- Û
when 16#cdb# => romdata <= X"00"; -- Û
when 16#0dc# => romdata <= X"00"; -- Ü
when 16#1dc# => romdata <= X"24"; -- Ü
when 16#2dc# => romdata <= X"24"; -- Ü
when 16#3dc# => romdata <= X"00"; -- Ü
when 16#4dc# => romdata <= X"42"; -- Ü
when 16#5dc# => romdata <= X"42"; -- Ü
when 16#6dc# => romdata <= X"42"; -- Ü
when 16#7dc# => romdata <= X"42"; -- Ü
when 16#8dc# => romdata <= X"42"; -- Ü
when 16#9dc# => romdata <= X"42"; -- Ü
when 16#adc# => romdata <= X"3c"; -- Ü
when 16#bdc# => romdata <= X"00"; -- Ü
when 16#cdc# => romdata <= X"00"; -- Ü
when 16#0dd# => romdata <= X"00"; -- Ý
when 16#1dd# => romdata <= X"08"; -- Ý
when 16#2dd# => romdata <= X"10"; -- Ý
when 16#3dd# => romdata <= X"00"; -- Ý
when 16#4dd# => romdata <= X"44"; -- Ý
when 16#5dd# => romdata <= X"44"; -- Ý
when 16#6dd# => romdata <= X"28"; -- Ý
when 16#7dd# => romdata <= X"10"; -- Ý
when 16#8dd# => romdata <= X"10"; -- Ý
when 16#9dd# => romdata <= X"10"; -- Ý
when 16#add# => romdata <= X"10"; -- Ý
when 16#bdd# => romdata <= X"00"; -- Ý
when 16#cdd# => romdata <= X"00"; -- Ý
when 16#0de# => romdata <= X"00"; -- Þ
when 16#1de# => romdata <= X"00"; -- Þ
when 16#2de# => romdata <= X"40"; -- Þ
when 16#3de# => romdata <= X"7c"; -- Þ
when 16#4de# => romdata <= X"42"; -- Þ
when 16#5de# => romdata <= X"42"; -- Þ
when 16#6de# => romdata <= X"42"; -- Þ
when 16#7de# => romdata <= X"7c"; -- Þ
when 16#8de# => romdata <= X"40"; -- Þ
when 16#9de# => romdata <= X"40"; -- Þ
when 16#ade# => romdata <= X"40"; -- Þ
when 16#bde# => romdata <= X"00"; -- Þ
when 16#cde# => romdata <= X"00"; -- Þ
when 16#0df# => romdata <= X"00"; -- ß
when 16#1df# => romdata <= X"00"; -- ß
when 16#2df# => romdata <= X"38"; -- ß
when 16#3df# => romdata <= X"44"; -- ß
when 16#4df# => romdata <= X"44"; -- ß
when 16#5df# => romdata <= X"48"; -- ß
when 16#6df# => romdata <= X"50"; -- ß
when 16#7df# => romdata <= X"4c"; -- ß
when 16#8df# => romdata <= X"42"; -- ß
when 16#9df# => romdata <= X"42"; -- ß
when 16#adf# => romdata <= X"5c"; -- ß
when 16#bdf# => romdata <= X"00"; -- ß
when 16#cdf# => romdata <= X"00"; -- ß
when 16#0e0# => romdata <= X"00"; -- à
when 16#1e0# => romdata <= X"00"; -- à
when 16#2e0# => romdata <= X"10"; -- à
when 16#3e0# => romdata <= X"08"; -- à
when 16#4e0# => romdata <= X"00"; -- à
when 16#5e0# => romdata <= X"3c"; -- à
when 16#6e0# => romdata <= X"02"; -- à
when 16#7e0# => romdata <= X"3e"; -- à
when 16#8e0# => romdata <= X"42"; -- à
when 16#9e0# => romdata <= X"46"; -- à
when 16#ae0# => romdata <= X"3a"; -- à
when 16#be0# => romdata <= X"00"; -- à
when 16#ce0# => romdata <= X"00"; -- à
when 16#0e1# => romdata <= X"00"; -- á
when 16#1e1# => romdata <= X"00"; -- á
when 16#2e1# => romdata <= X"04"; -- á
when 16#3e1# => romdata <= X"08"; -- á
when 16#4e1# => romdata <= X"00"; -- á
when 16#5e1# => romdata <= X"3c"; -- á
when 16#6e1# => romdata <= X"02"; -- á
when 16#7e1# => romdata <= X"3e"; -- á
when 16#8e1# => romdata <= X"42"; -- á
when 16#9e1# => romdata <= X"46"; -- á
when 16#ae1# => romdata <= X"3a"; -- á
when 16#be1# => romdata <= X"00"; -- á
when 16#ce1# => romdata <= X"00"; -- á
when 16#0e2# => romdata <= X"00"; -- â
when 16#1e2# => romdata <= X"00"; -- â
when 16#2e2# => romdata <= X"18"; -- â
when 16#3e2# => romdata <= X"24"; -- â
when 16#4e2# => romdata <= X"00"; -- â
when 16#5e2# => romdata <= X"3c"; -- â
when 16#6e2# => romdata <= X"02"; -- â
when 16#7e2# => romdata <= X"3e"; -- â
when 16#8e2# => romdata <= X"42"; -- â
when 16#9e2# => romdata <= X"46"; -- â
when 16#ae2# => romdata <= X"3a"; -- â
when 16#be2# => romdata <= X"00"; -- â
when 16#ce2# => romdata <= X"00"; -- â
when 16#0e3# => romdata <= X"00"; -- ã
when 16#1e3# => romdata <= X"00"; -- ã
when 16#2e3# => romdata <= X"32"; -- ã
when 16#3e3# => romdata <= X"4c"; -- ã
when 16#4e3# => romdata <= X"00"; -- ã
when 16#5e3# => romdata <= X"3c"; -- ã
when 16#6e3# => romdata <= X"02"; -- ã
when 16#7e3# => romdata <= X"3e"; -- ã
when 16#8e3# => romdata <= X"42"; -- ã
when 16#9e3# => romdata <= X"46"; -- ã
when 16#ae3# => romdata <= X"3a"; -- ã
when 16#be3# => romdata <= X"00"; -- ã
when 16#ce3# => romdata <= X"00"; -- ã
when 16#0e4# => romdata <= X"00"; -- ä
when 16#1e4# => romdata <= X"00"; -- ä
when 16#2e4# => romdata <= X"24"; -- ä
when 16#3e4# => romdata <= X"24"; -- ä
when 16#4e4# => romdata <= X"00"; -- ä
when 16#5e4# => romdata <= X"3c"; -- ä
when 16#6e4# => romdata <= X"02"; -- ä
when 16#7e4# => romdata <= X"3e"; -- ä
when 16#8e4# => romdata <= X"42"; -- ä
when 16#9e4# => romdata <= X"46"; -- ä
when 16#ae4# => romdata <= X"3a"; -- ä
when 16#be4# => romdata <= X"00"; -- ä
when 16#ce4# => romdata <= X"00"; -- ä
when 16#0e5# => romdata <= X"00"; -- å
when 16#1e5# => romdata <= X"18"; -- å
when 16#2e5# => romdata <= X"24"; -- å
when 16#3e5# => romdata <= X"18"; -- å
when 16#4e5# => romdata <= X"00"; -- å
when 16#5e5# => romdata <= X"3c"; -- å
when 16#6e5# => romdata <= X"02"; -- å
when 16#7e5# => romdata <= X"3e"; -- å
when 16#8e5# => romdata <= X"42"; -- å
when 16#9e5# => romdata <= X"46"; -- å
when 16#ae5# => romdata <= X"3a"; -- å
when 16#be5# => romdata <= X"00"; -- å
when 16#ce5# => romdata <= X"00"; -- å
when 16#0e6# => romdata <= X"00"; -- æ
when 16#1e6# => romdata <= X"00"; -- æ
when 16#2e6# => romdata <= X"00"; -- æ
when 16#3e6# => romdata <= X"00"; -- æ
when 16#4e6# => romdata <= X"00"; -- æ
when 16#5e6# => romdata <= X"6c"; -- æ
when 16#6e6# => romdata <= X"12"; -- æ
when 16#7e6# => romdata <= X"7c"; -- æ
when 16#8e6# => romdata <= X"90"; -- æ
when 16#9e6# => romdata <= X"92"; -- æ
when 16#ae6# => romdata <= X"6c"; -- æ
when 16#be6# => romdata <= X"00"; -- æ
when 16#ce6# => romdata <= X"00"; -- æ
when 16#0e7# => romdata <= X"00"; -- ç
when 16#1e7# => romdata <= X"00"; -- ç
when 16#2e7# => romdata <= X"00"; -- ç
when 16#3e7# => romdata <= X"00"; -- ç
when 16#4e7# => romdata <= X"00"; -- ç
when 16#5e7# => romdata <= X"3c"; -- ç
when 16#6e7# => romdata <= X"42"; -- ç
when 16#7e7# => romdata <= X"40"; -- ç
when 16#8e7# => romdata <= X"40"; -- ç
when 16#9e7# => romdata <= X"42"; -- ç
when 16#ae7# => romdata <= X"3c"; -- ç
when 16#be7# => romdata <= X"08"; -- ç
when 16#ce7# => romdata <= X"10"; -- ç
when 16#0e8# => romdata <= X"00"; -- è
when 16#1e8# => romdata <= X"00"; -- è
when 16#2e8# => romdata <= X"10"; -- è
when 16#3e8# => romdata <= X"08"; -- è
when 16#4e8# => romdata <= X"00"; -- è
when 16#5e8# => romdata <= X"3c"; -- è
when 16#6e8# => romdata <= X"42"; -- è
when 16#7e8# => romdata <= X"7e"; -- è
when 16#8e8# => romdata <= X"40"; -- è
when 16#9e8# => romdata <= X"42"; -- è
when 16#ae8# => romdata <= X"3c"; -- è
when 16#be8# => romdata <= X"00"; -- è
when 16#ce8# => romdata <= X"00"; -- è
when 16#0e9# => romdata <= X"00"; -- é
when 16#1e9# => romdata <= X"00"; -- é
when 16#2e9# => romdata <= X"08"; -- é
when 16#3e9# => romdata <= X"10"; -- é
when 16#4e9# => romdata <= X"00"; -- é
when 16#5e9# => romdata <= X"3c"; -- é
when 16#6e9# => romdata <= X"42"; -- é
when 16#7e9# => romdata <= X"7e"; -- é
when 16#8e9# => romdata <= X"40"; -- é
when 16#9e9# => romdata <= X"42"; -- é
when 16#ae9# => romdata <= X"3c"; -- é
when 16#be9# => romdata <= X"00"; -- é
when 16#ce9# => romdata <= X"00"; -- é
when 16#0ea# => romdata <= X"00"; -- ê
when 16#1ea# => romdata <= X"00"; -- ê
when 16#2ea# => romdata <= X"18"; -- ê
when 16#3ea# => romdata <= X"24"; -- ê
when 16#4ea# => romdata <= X"00"; -- ê
when 16#5ea# => romdata <= X"3c"; -- ê
when 16#6ea# => romdata <= X"42"; -- ê
when 16#7ea# => romdata <= X"7e"; -- ê
when 16#8ea# => romdata <= X"40"; -- ê
when 16#9ea# => romdata <= X"42"; -- ê
when 16#aea# => romdata <= X"3c"; -- ê
when 16#bea# => romdata <= X"00"; -- ê
when 16#cea# => romdata <= X"00"; -- ê
when 16#0eb# => romdata <= X"00"; -- ë
when 16#1eb# => romdata <= X"00"; -- ë
when 16#2eb# => romdata <= X"24"; -- ë
when 16#3eb# => romdata <= X"24"; -- ë
when 16#4eb# => romdata <= X"00"; -- ë
when 16#5eb# => romdata <= X"3c"; -- ë
when 16#6eb# => romdata <= X"42"; -- ë
when 16#7eb# => romdata <= X"7e"; -- ë
when 16#8eb# => romdata <= X"40"; -- ë
when 16#9eb# => romdata <= X"42"; -- ë
when 16#aeb# => romdata <= X"3c"; -- ë
when 16#beb# => romdata <= X"00"; -- ë
when 16#ceb# => romdata <= X"00"; -- ë
when 16#0ec# => romdata <= X"00"; -- ì
when 16#1ec# => romdata <= X"00"; -- ì
when 16#2ec# => romdata <= X"20"; -- ì
when 16#3ec# => romdata <= X"10"; -- ì
when 16#4ec# => romdata <= X"00"; -- ì
when 16#5ec# => romdata <= X"30"; -- ì
when 16#6ec# => romdata <= X"10"; -- ì
when 16#7ec# => romdata <= X"10"; -- ì
when 16#8ec# => romdata <= X"10"; -- ì
when 16#9ec# => romdata <= X"10"; -- ì
when 16#aec# => romdata <= X"7c"; -- ì
when 16#bec# => romdata <= X"00"; -- ì
when 16#cec# => romdata <= X"00"; -- ì
when 16#0ed# => romdata <= X"00"; -- í
when 16#1ed# => romdata <= X"00"; -- í
when 16#2ed# => romdata <= X"10"; -- í
when 16#3ed# => romdata <= X"20"; -- í
when 16#4ed# => romdata <= X"00"; -- í
when 16#5ed# => romdata <= X"30"; -- í
when 16#6ed# => romdata <= X"10"; -- í
when 16#7ed# => romdata <= X"10"; -- í
when 16#8ed# => romdata <= X"10"; -- í
when 16#9ed# => romdata <= X"10"; -- í
when 16#aed# => romdata <= X"7c"; -- í
when 16#bed# => romdata <= X"00"; -- í
when 16#ced# => romdata <= X"00"; -- í
when 16#0ee# => romdata <= X"00"; -- î
when 16#1ee# => romdata <= X"00"; -- î
when 16#2ee# => romdata <= X"30"; -- î
when 16#3ee# => romdata <= X"48"; -- î
when 16#4ee# => romdata <= X"00"; -- î
when 16#5ee# => romdata <= X"30"; -- î
when 16#6ee# => romdata <= X"10"; -- î
when 16#7ee# => romdata <= X"10"; -- î
when 16#8ee# => romdata <= X"10"; -- î
when 16#9ee# => romdata <= X"10"; -- î
when 16#aee# => romdata <= X"7c"; -- î
when 16#bee# => romdata <= X"00"; -- î
when 16#cee# => romdata <= X"00"; -- î
when 16#0ef# => romdata <= X"00"; -- ï
when 16#1ef# => romdata <= X"00"; -- ï
when 16#2ef# => romdata <= X"48"; -- ï
when 16#3ef# => romdata <= X"48"; -- ï
when 16#4ef# => romdata <= X"00"; -- ï
when 16#5ef# => romdata <= X"30"; -- ï
when 16#6ef# => romdata <= X"10"; -- ï
when 16#7ef# => romdata <= X"10"; -- ï
when 16#8ef# => romdata <= X"10"; -- ï
when 16#9ef# => romdata <= X"10"; -- ï
when 16#aef# => romdata <= X"7c"; -- ï
when 16#bef# => romdata <= X"00"; -- ï
when 16#cef# => romdata <= X"00"; -- ï
when 16#0f0# => romdata <= X"00"; -- ð
when 16#1f0# => romdata <= X"24"; -- ð
when 16#2f0# => romdata <= X"18"; -- ð
when 16#3f0# => romdata <= X"28"; -- ð
when 16#4f0# => romdata <= X"04"; -- ð
when 16#5f0# => romdata <= X"3c"; -- ð
when 16#6f0# => romdata <= X"42"; -- ð
when 16#7f0# => romdata <= X"42"; -- ð
when 16#8f0# => romdata <= X"42"; -- ð
when 16#9f0# => romdata <= X"42"; -- ð
when 16#af0# => romdata <= X"3c"; -- ð
when 16#bf0# => romdata <= X"00"; -- ð
when 16#cf0# => romdata <= X"00"; -- ð
when 16#0f1# => romdata <= X"00"; -- ñ
when 16#1f1# => romdata <= X"00"; -- ñ
when 16#2f1# => romdata <= X"32"; -- ñ
when 16#3f1# => romdata <= X"4c"; -- ñ
when 16#4f1# => romdata <= X"00"; -- ñ
when 16#5f1# => romdata <= X"5c"; -- ñ
when 16#6f1# => romdata <= X"62"; -- ñ
when 16#7f1# => romdata <= X"42"; -- ñ
when 16#8f1# => romdata <= X"42"; -- ñ
when 16#9f1# => romdata <= X"42"; -- ñ
when 16#af1# => romdata <= X"42"; -- ñ
when 16#bf1# => romdata <= X"00"; -- ñ
when 16#cf1# => romdata <= X"00"; -- ñ
when 16#0f2# => romdata <= X"00"; -- ò
when 16#1f2# => romdata <= X"00"; -- ò
when 16#2f2# => romdata <= X"20"; -- ò
when 16#3f2# => romdata <= X"10"; -- ò
when 16#4f2# => romdata <= X"00"; -- ò
when 16#5f2# => romdata <= X"3c"; -- ò
when 16#6f2# => romdata <= X"42"; -- ò
when 16#7f2# => romdata <= X"42"; -- ò
when 16#8f2# => romdata <= X"42"; -- ò
when 16#9f2# => romdata <= X"42"; -- ò
when 16#af2# => romdata <= X"3c"; -- ò
when 16#bf2# => romdata <= X"00"; -- ò
when 16#cf2# => romdata <= X"00"; -- ò
when 16#0f3# => romdata <= X"00"; -- ó
when 16#1f3# => romdata <= X"00"; -- ó
when 16#2f3# => romdata <= X"08"; -- ó
when 16#3f3# => romdata <= X"10"; -- ó
when 16#4f3# => romdata <= X"00"; -- ó
when 16#5f3# => romdata <= X"3c"; -- ó
when 16#6f3# => romdata <= X"42"; -- ó
when 16#7f3# => romdata <= X"42"; -- ó
when 16#8f3# => romdata <= X"42"; -- ó
when 16#9f3# => romdata <= X"42"; -- ó
when 16#af3# => romdata <= X"3c"; -- ó
when 16#bf3# => romdata <= X"00"; -- ó
when 16#cf3# => romdata <= X"00"; -- ó
when 16#0f4# => romdata <= X"00"; -- ô
when 16#1f4# => romdata <= X"00"; -- ô
when 16#2f4# => romdata <= X"18"; -- ô
when 16#3f4# => romdata <= X"24"; -- ô
when 16#4f4# => romdata <= X"00"; -- ô
when 16#5f4# => romdata <= X"3c"; -- ô
when 16#6f4# => romdata <= X"42"; -- ô
when 16#7f4# => romdata <= X"42"; -- ô
when 16#8f4# => romdata <= X"42"; -- ô
when 16#9f4# => romdata <= X"42"; -- ô
when 16#af4# => romdata <= X"3c"; -- ô
when 16#bf4# => romdata <= X"00"; -- ô
when 16#cf4# => romdata <= X"00"; -- ô
when 16#0f5# => romdata <= X"00"; -- õ
when 16#1f5# => romdata <= X"00"; -- õ
when 16#2f5# => romdata <= X"32"; -- õ
when 16#3f5# => romdata <= X"4c"; -- õ
when 16#4f5# => romdata <= X"00"; -- õ
when 16#5f5# => romdata <= X"3c"; -- õ
when 16#6f5# => romdata <= X"42"; -- õ
when 16#7f5# => romdata <= X"42"; -- õ
when 16#8f5# => romdata <= X"42"; -- õ
when 16#9f5# => romdata <= X"42"; -- õ
when 16#af5# => romdata <= X"3c"; -- õ
when 16#bf5# => romdata <= X"00"; -- õ
when 16#cf5# => romdata <= X"00"; -- õ
when 16#0f6# => romdata <= X"00"; -- ö
when 16#1f6# => romdata <= X"00"; -- ö
when 16#2f6# => romdata <= X"24"; -- ö
when 16#3f6# => romdata <= X"24"; -- ö
when 16#4f6# => romdata <= X"00"; -- ö
when 16#5f6# => romdata <= X"3c"; -- ö
when 16#6f6# => romdata <= X"42"; -- ö
when 16#7f6# => romdata <= X"42"; -- ö
when 16#8f6# => romdata <= X"42"; -- ö
when 16#9f6# => romdata <= X"42"; -- ö
when 16#af6# => romdata <= X"3c"; -- ö
when 16#bf6# => romdata <= X"00"; -- ö
when 16#cf6# => romdata <= X"00"; -- ö
when 16#0f7# => romdata <= X"00"; -- ÷
when 16#1f7# => romdata <= X"00"; -- ÷
when 16#2f7# => romdata <= X"00"; -- ÷
when 16#3f7# => romdata <= X"10"; -- ÷
when 16#4f7# => romdata <= X"10"; -- ÷
when 16#5f7# => romdata <= X"00"; -- ÷
when 16#6f7# => romdata <= X"7c"; -- ÷
when 16#7f7# => romdata <= X"00"; -- ÷
when 16#8f7# => romdata <= X"10"; -- ÷
when 16#9f7# => romdata <= X"10"; -- ÷
when 16#af7# => romdata <= X"00"; -- ÷
when 16#bf7# => romdata <= X"00"; -- ÷
when 16#cf7# => romdata <= X"00"; -- ÷
when 16#0f8# => romdata <= X"00"; -- ø
when 16#1f8# => romdata <= X"00"; -- ø
when 16#2f8# => romdata <= X"00"; -- ø
when 16#3f8# => romdata <= X"00"; -- ø
when 16#4f8# => romdata <= X"02"; -- ø
when 16#5f8# => romdata <= X"3c"; -- ø
when 16#6f8# => romdata <= X"46"; -- ø
when 16#7f8# => romdata <= X"4a"; -- ø
when 16#8f8# => romdata <= X"52"; -- ø
when 16#9f8# => romdata <= X"62"; -- ø
when 16#af8# => romdata <= X"3c"; -- ø
when 16#bf8# => romdata <= X"40"; -- ø
when 16#cf8# => romdata <= X"00"; -- ø
when 16#0f9# => romdata <= X"00"; -- ù
when 16#1f9# => romdata <= X"00"; -- ù
when 16#2f9# => romdata <= X"20"; -- ù
when 16#3f9# => romdata <= X"10"; -- ù
when 16#4f9# => romdata <= X"00"; -- ù
when 16#5f9# => romdata <= X"44"; -- ù
when 16#6f9# => romdata <= X"44"; -- ù
when 16#7f9# => romdata <= X"44"; -- ù
when 16#8f9# => romdata <= X"44"; -- ù
when 16#9f9# => romdata <= X"44"; -- ù
when 16#af9# => romdata <= X"3a"; -- ù
when 16#bf9# => romdata <= X"00"; -- ù
when 16#cf9# => romdata <= X"00"; -- ù
when 16#0fa# => romdata <= X"00"; -- ú
when 16#1fa# => romdata <= X"00"; -- ú
when 16#2fa# => romdata <= X"08"; -- ú
when 16#3fa# => romdata <= X"10"; -- ú
when 16#4fa# => romdata <= X"00"; -- ú
when 16#5fa# => romdata <= X"44"; -- ú
when 16#6fa# => romdata <= X"44"; -- ú
when 16#7fa# => romdata <= X"44"; -- ú
when 16#8fa# => romdata <= X"44"; -- ú
when 16#9fa# => romdata <= X"44"; -- ú
when 16#afa# => romdata <= X"3a"; -- ú
when 16#bfa# => romdata <= X"00"; -- ú
when 16#cfa# => romdata <= X"00"; -- ú
when 16#0fb# => romdata <= X"00"; -- û
when 16#1fb# => romdata <= X"00"; -- û
when 16#2fb# => romdata <= X"18"; -- û
when 16#3fb# => romdata <= X"24"; -- û
when 16#4fb# => romdata <= X"00"; -- û
when 16#5fb# => romdata <= X"44"; -- û
when 16#6fb# => romdata <= X"44"; -- û
when 16#7fb# => romdata <= X"44"; -- û
when 16#8fb# => romdata <= X"44"; -- û
when 16#9fb# => romdata <= X"44"; -- û
when 16#afb# => romdata <= X"3a"; -- û
when 16#bfb# => romdata <= X"00"; -- û
when 16#cfb# => romdata <= X"00"; -- û
when 16#0fc# => romdata <= X"00"; -- ü
when 16#1fc# => romdata <= X"00"; -- ü
when 16#2fc# => romdata <= X"28"; -- ü
when 16#3fc# => romdata <= X"28"; -- ü
when 16#4fc# => romdata <= X"00"; -- ü
when 16#5fc# => romdata <= X"44"; -- ü
when 16#6fc# => romdata <= X"44"; -- ü
when 16#7fc# => romdata <= X"44"; -- ü
when 16#8fc# => romdata <= X"44"; -- ü
when 16#9fc# => romdata <= X"44"; -- ü
when 16#afc# => romdata <= X"3a"; -- ü
when 16#bfc# => romdata <= X"00"; -- ü
when 16#cfc# => romdata <= X"00"; -- ü
when 16#0fd# => romdata <= X"00"; -- ý
when 16#1fd# => romdata <= X"00"; -- ý
when 16#2fd# => romdata <= X"08"; -- ý
when 16#3fd# => romdata <= X"10"; -- ý
when 16#4fd# => romdata <= X"00"; -- ý
when 16#5fd# => romdata <= X"42"; -- ý
when 16#6fd# => romdata <= X"42"; -- ý
when 16#7fd# => romdata <= X"42"; -- ý
when 16#8fd# => romdata <= X"46"; -- ý
when 16#9fd# => romdata <= X"3a"; -- ý
when 16#afd# => romdata <= X"02"; -- ý
when 16#bfd# => romdata <= X"42"; -- ý
when 16#cfd# => romdata <= X"3c"; -- ý
when 16#0fe# => romdata <= X"00"; -- þ
when 16#1fe# => romdata <= X"00"; -- þ
when 16#2fe# => romdata <= X"00"; -- þ
when 16#3fe# => romdata <= X"40"; -- þ
when 16#4fe# => romdata <= X"40"; -- þ
when 16#5fe# => romdata <= X"5c"; -- þ
when 16#6fe# => romdata <= X"62"; -- þ
when 16#7fe# => romdata <= X"42"; -- þ
when 16#8fe# => romdata <= X"42"; -- þ
when 16#9fe# => romdata <= X"62"; -- þ
when 16#afe# => romdata <= X"5c"; -- þ
when 16#bfe# => romdata <= X"40"; -- þ
when 16#cfe# => romdata <= X"40"; -- þ
when 16#0ff# => romdata <= X"00"; -- ÿ
when 16#1ff# => romdata <= X"00"; -- ÿ
when 16#2ff# => romdata <= X"24"; -- ÿ
when 16#3ff# => romdata <= X"24"; -- ÿ
when 16#4ff# => romdata <= X"00"; -- ÿ
when 16#5ff# => romdata <= X"42"; -- ÿ
when 16#6ff# => romdata <= X"42"; -- ÿ
when 16#7ff# => romdata <= X"42"; -- ÿ
when 16#8ff# => romdata <= X"46"; -- ÿ
when 16#9ff# => romdata <= X"3a"; -- ÿ
when 16#aff# => romdata <= X"02"; -- ÿ
when 16#bff# => romdata <= X"42"; -- ÿ
when 16#cff# => romdata <= X"3c"; -- ÿ
when others => romdata <= (others => '0');
end case;
end process;
end architecture;
| gpl-3.0 | 9d2e251c9e7a3e98e2d35e86320f3a06 | 0.422177 | 2.936166 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/techmap/maps/toutpad_ds.vhd | 1 | 4,694 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: toutpad_ds
-- File: toutpad_ds.vhd
-- Author: Jonas Ekergarn - Aeroflex Gaisler
-- Description: tri-state differential output pad with technology wrapper
------------------------------------------------------------------------------
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allpads.all;
entity toutpad_ds is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12;
oepol : integer := 0);
port (padp, padn : out std_ulogic; i, en : in std_ulogic);
end;
architecture rtl of toutpad_ds is
signal oen : std_ulogic;
signal padx, gnd : std_ulogic;
begin
gnd <= '0';
oen <= not en when oepol /= padoen_polarity(tech) else en;
gen0 : if has_ds_pads(tech) = 0 or (is_unisim(tech) = 1) or
tech = axcel or tech = axdsp or tech = rhlib18t or
tech = ut25 or tech = ut130
generate
padp <= i
-- pragma translate_off
after 2 ns
-- pragma translate_on
when oen = '0'
-- pragma translate_off
else 'X' after 2 ns when is_x(en)
-- pragma translate_on
else 'Z'
-- pragma translate_off
after 2 ns
-- pragma translate_on
;
padn <= not i
-- pragma translate_off
after 2 ns
-- pragma translate_on
when oen = '0'
-- pragma translate_off
else 'X' after 2 ns when is_x(en)
-- pragma translate_on
else 'Z'
-- pragma translate_off
after 2 ns
-- pragma translate_on
;
end generate;
pa3 : if (tech = apa3) generate
u0 : apa3_toutpad_ds generic map (level)
port map (padp, padn, i, oen);
end generate;
pa3e : if (tech = apa3e) generate
u0 : apa3e_toutpad_ds generic map (level)
port map (padp, padn, i, oen);
end generate;
igl2 : if (tech = igloo2) or (tech = rtg4) generate
u0 : igloo2_toutpad_ds port map (padp, padn, i, oen);
end generate;
pa3l : if (tech = apa3l) generate
u0 : apa3l_toutpad_ds generic map (level)
port map (padp, padn, i, oen);
end generate;
fus : if (tech = actfus) generate
u0 : fusion_toutpad_ds generic map (level)
port map (padp, padn, i, oen);
end generate;
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity toutpad_dsv is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (
padp : out std_logic_vector(width-1 downto 0);
padn : out std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_ulogic);
end;
architecture rtl of toutpad_dsv is
begin
v : for j in width-1 downto 0 generate
u0 : toutpad_ds generic map (tech, level, slew, voltage, strength, oepol)
port map (padp(j), padn(j), i(j), en);
end generate;
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity toutpad_dsvv is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (
padp : out std_logic_vector(width-1 downto 0);
padn : out std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_logic_vector(width-1 downto 0));
end;
architecture rtl of toutpad_dsvv is
begin
v : for j in width-1 downto 0 generate
u0 : toutpad_ds generic map (tech, level, slew, voltage, strength, oepol)
port map (padp(j), padn(j), i(j), en(j));
end generate;
end;
| gpl-3.0 | cac9730e699813a5cb7f88fd4c146fb7 | 0.627823 | 3.479615 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/grlib/amba/dma2ahb_pkg.vhd | 1 | 6,047 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
--============================================================================--
-- Design unit : DMA2AHB_Package (package declaration)
--
-- File name : dma2ahb_pkg.vhd
--
-- Purpose : Interface package for AMBA AHB master interface with DMA input
--
-- Reference : AMBA(TM) Specification (Rev 2.0), ARM IHI 0011A,
-- 13th May 1999, issue A, first release, ARM Limited
-- The document can be retrieved from http://www.arm.com
-- AMBA is a trademark of ARM Limited.
-- ARM is a registered trademark of ARM Limited.
--
-- Note : Naming convention according to AMBA(TM) Specification:
-- Signal names are in upper case, except for the following:
-- A lower case 'n' in the name indicates that the signal
-- is active low.
-- Constant names are in upper case.
-- The least significant bit of an array is located to the right,
-- carrying the index number zero.
--
-- Limitations : See DMA2AHB VHDL core
--
-- Library : gaisler
--
-- Authors : Aeroflex Gaisler AB
--
-- Contact : mailto:[email protected]
-- http://www.gaisler.com
--
-- Disclaimer : All information is provided "as is", there is no warranty that
-- the information is correct or suitable for any purpose,
-- neither implicit nor explicit.
--
--------------------------------------------------------------------------------
-- Version Author Date Changes
--
-- 1.4 SH 1 Jul 2005 Support for fixed length incrementing bursts
-- Support for record types
-- 1.5 SH 1 Sep 2005 New library gaisler
-- 1.6 SH 20 Sep 2005 Added transparent HSIZE support
-- 1.7 SH 6 Dec 2007 Added syncrst generic
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
package DMA2AHB_Package is
-----------------------------------------------------------------------------
-- Direct Memory Access to AMBA AHB Master Interface Types
-----------------------------------------------------------------------------
type DMA_In_Type is record
Reset: Std_Logic;
Address: Std_Logic_Vector(32-1 downto 0);
Data: Std_Logic_Vector(32-1 downto 0);
Request: Std_Logic; -- access requested
Burst: Std_Logic; -- burst requested
Beat: Std_Logic_Vector(1 downto 0); -- incrementing beat
Size: Std_Logic_Vector(1 downto 0); -- size
Store: Std_Logic; -- data write requested
Lock: Std_Logic; -- locked Transfer
end record;
type DMA_Out_Type is record
Grant: Std_Logic; -- access accepted
OKAY: Std_Logic; -- write access ready
Ready: Std_Logic; -- read data ready
Retry: Std_Logic; -- retry
Fault: Std_Logic; -- error occured
Data: Std_Logic_Vector(32-1 downto 0);
end record;
-- constants for HBURST definition (used with dma_in_type.Beat)
constant HINCR: Std_Logic_Vector(1 downto 0) := "00";
constant HINCR4: Std_Logic_Vector(1 downto 0) := "01";
constant HINCR8: Std_Logic_Vector(1 downto 0) := "10";
constant HINCR16: Std_Logic_Vector(1 downto 0) := "11";
-- constants for HSIZE definition (used with dma_in_type.Size)
constant HSIZE8: Std_Logic_Vector(1 downto 0) := "00";
constant HSIZE16: Std_Logic_Vector(1 downto 0) := "01";
constant HSIZE32: Std_Logic_Vector(1 downto 0) := "10";
-----------------------------------------------------------------------------
-- Direct Memory Access to AMBA AHB Master Interface
-----------------------------------------------------------------------------
component DMA2AHB is
generic(
hindex: in Integer := 0;
vendorid: in Integer := 0;
deviceid: in Integer := 0;
version: in Integer := 0;
syncrst: in Integer := 1;
boundary: in Integer := 1);
port(
-- AMBA AHB system signals
HCLK: in Std_ULogic;
HRESETn: in Std_ULogic;
-- Direct Memory Access Interface
DMAIn: in DMA_In_Type;
DMAOut: out DMA_OUt_Type;
-- AMBA AHB Master Interface
AHBIn: in AHB_Mst_In_Type;
AHBOut: out AHB_Mst_Out_Type);
end component DMA2AHB;
end package DMA2AHB_Package; --===============================================--
| gpl-3.0 | 02a711f0a0a9d1a6606c63d0579227b2 | 0.503059 | 4.705837 | false | false | false | false |
yishinli/emc2 | src/hal/drivers/m5i20/hostmot5_src/new3phd.vhd | 1 | 6,528 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity new3phd is
Port (
clk: in STD_LOGIC;
pwmrefcnt: in STD_LOGIC_VECTOR(9 downto 0);
ibus: in STD_LOGIC_VECTOR (31 downto 0);
obus: out STD_LOGIC_VECTOR (31 downto 0);
writestb: in STD_LOGIC;
readstb: in STD_LOGIC;
addr: in STD_LOGIC_VECTOR (1 downto 0);
outa: out STD_LOGIC;
outb: out STD_LOGIC;
outc: out STD_LOGIC
);
end new3phd;
architecture behavioral of new3phd is
signal creg: STD_LOGIC_VECTOR (2 downto 0);
alias refmsb: std_logic is pwmrefcnt(9);
signal oldrefmsb: std_logic;
signal FIFORead: std_logic;
signal Start: std_logic;
signal HostStart: std_logic;
signal PopData: STD_LOGIC_VECTOR (31 downto 0);
alias PWMPtr: STD_LOGIC_VECTOR (1 downto 0) is PopData(1 downto 0);
alias Aflag: std_logic is PopData(4);
signal PushData: STD_LOGIC_VECTOR (31 downto 0);
signal FIFOdatawr: STD_LOGIC;
signal IncDataCount: STD_LOGIC;
signal IncDataCountp: STD_LOGIC;
signal PushPtr: STD_LOGIC_VECTOR (7 downto 0);
signal PopPtr: STD_LOGIC_VECTOR (7 downto 0);
signal FPopPtr: STD_LOGIC_VECTOR (7 downto 0);
signal DataCount: STD_LOGIC_VECTOR (8 downto 0);
signal pwmas: STD_LOGIC_VECTOR (9 downto 0);
signal pwmbs: STD_LOGIC_VECTOR (9 downto 0);
signal pwmcs: STD_LOGIC_VECTOR (9 downto 0);
signal pwmae: STD_LOGIC_VECTOR (9 downto 0);
signal pwmbe: STD_LOGIC_VECTOR (9 downto 0);
signal pwmce: STD_LOGIC_VECTOR (9 downto 0);
signal pwmapol: STD_LOGIC;
signal pwmbpol: STD_LOGIC;
signal pwmcpol: STD_LOGIC;
signal pwmouta: STD_LOGIC;
signal pwmoutb: STD_LOGIC;
signal pwmoutc: STD_LOGIC;
component FIFOMem32 IS
port (
addra: IN std_logic_VECTOR(7 downto 0);
addrb: IN std_logic_VECTOR(7 downto 0);
clka: IN std_logic;
clkb: IN std_logic;
dina: IN std_logic_VECTOR(31 downto 0);
dinb: IN std_logic_VECTOR(31 downto 0);
douta: OUT std_logic_VECTOR(31 downto 0);
doutb: OUT std_logic_VECTOR(31 downto 0);
wea: IN std_logic;
web: IN std_logic);
end component FIFOMem32;
begin
AFIFO: FIFOMem32 port map (
addra => FPopPtr,
addrb => PushPtr,
clka => clk,
clkb => clk,
dina => x"00000000",
dinb => ibus,
douta => PopData,
doutb => PushData,
wea => '0',
web => FIFOdatawr
);
athreephase: process (clk,addr,readstb,writestb,
creg, pwmouta, pwmoutb, pwmoutc
)
begin
if clk'event and clk = '1' then
IncDataCount <= IncDataCountP;
if (IncDataCount = '1') and (FIFOREAD = '0') then
IncDataCount <= '0';
IncDataCountP <= '0';
DataCount <= DataCount + 1;
end if;
if (UNSIGNED(pwmrefcnt) >= UNSIGNED(pwmas)) and (UNSIGNED(pwmrefcnt) <= UNSIGNED(pwmae)) then
pwmouta <= '1' xor pwmapol;
else
pwmouta <= '0' xor pwmapol;
end if;
if (UNSIGNED(pwmrefcnt) >= UNSIGNED(pwmbs)) and (UNSIGNED(pwmrefcnt) <= UNSIGNED(pwmbe)) then
pwmoutb <= '1' xor pwmbpol;
else
pwmoutb <= '0' xor pwmbpol;
end if;
if (UNSIGNED(pwmrefcnt) >= UNSIGNED(pwmcs)) and (UNSIGNED(pwmrefcnt) <= UNSIGNED(pwmce)) then
pwmoutc <= '1' xor pwmcpol;
else
pwmoutc <= '0' xor pwmcpol;
end if;
oldrefmsb <= refmsb;
if FIFORead = '1' and DataCount /= 0 then
case PWMPtr is
when "00" =>
pwmas <= PopData(14 downto 5);
pwmae <= PopData(30 downto 21);
pwmapol <= PopData(31);
when "01" =>
pwmbs <= PopData(14 downto 5);
pwmbe <= PopData(30 downto 21);
pwmbpol <= PopData(31);
when "10" =>
pwmcs <= PopData(14 downto 5);
pwmce <= PopData(30 downto 21);
pwmcpol <= PopData(31);
when others => null;
end case;
PopPtr <= FPopPtr;
DataCount <= DataCount -1;
end if;
if writestb = '1' then
case addr is
when "00" => PushPtr <= PushPtr + 1;
IncDataCountp <= '1';
when "01" => creg <= ibus(2 downto 0);
when "10" => Datacount <= (others => '0');
PopPtr <= (others => '0');
PushPtr <= (others => '0');
when others => null;
end case;
end if;
end if; -- clk
if ((Start = '1') or (AFlag = '0')) and (DataCount /= 0) then
FIFORead <= '1';
FPopPtr <= PopPtr +1;
else
FIFORead <= '0';
FPopPtr <= PopPtr;
end if;
if writestb = '1' and addr = "11" then
HostStart <= '1';
else
HostStart <= '0';
end if;
if writestb = '1' and addr = "00" then
FIFOdataWr <= '1';
else
FIFODataWr <= '0';
end if;
if (oldrefmsb = '1' and refmsb = '0' and AFlag = '1' and creg(0) = '1') or (Hoststart = '1' ) then
Start <= '1';
else
Start <= '0';
end if;
obus <= (others => 'Z');
if readstb = '1' then
case addr is
when "00" => obus <= PopData;
when "01" => obus <= (2 => creg(2),1 => creg(1),0 =>creg(0), others => '0');
when "10" => obus(8 downto 0) <= DataCount;
when others => obus <= (others => 'Z');
end case;
else
obus <= (others => 'Z');
end if;
if creg(1) = '1' then
if creg(2) = '0' then
outa <= pwmouta;
outb <= pwmoutb;
outc <= pwmoutc;
else
outa <= pwmoutb;
outb <= pwmouta;
outc <= pwmoutc;
end if;
else
outa <= 'Z';
outb <= 'Z';
outc <= 'Z';
end if;
end process;
end behavioral;
| lgpl-2.1 | 5e4a047f78306532c364f792232678ad | 0.489737 | 3.412441 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/grlib/stdlib/stdlib.vhd | 1 | 20,618 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: stdlib
-- File: stdlib.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Package for common VHDL functions
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- pragma translate_off
use std.textio.all;
-- pragma translate_on
library grlib;
use grlib.version.all;
package stdlib is
constant LIBVHDL_VERSION : integer := grlib_version;
constant LIBVHDL_BUILD : integer := grlib_build;
constant zero32 : std_logic_vector(31 downto 0) := (others => '0');
constant zero64 : std_logic_vector(63 downto 0) := (others => '0');
constant zero128 : std_logic_vector(127 downto 0) := (others => '0');
constant one32 : std_logic_vector(31 downto 0) := (others => '1');
constant one64 : std_logic_vector(63 downto 0) := (others => '1');
constant one128 : std_logic_vector(127 downto 0) := (others => '1');
type log2arr is array(0 to 512) of integer;
constant log2 : log2arr := (
0,0,1,2,2,3,3,3,3,4,4,4,4,4,4,4,4,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,
6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,
7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,
7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,
8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
others => 9);
constant log2x : log2arr := (
0,1,1,2,2,3,3,3,3,4,4,4,4,4,4,4,4,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,
6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,
7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,
7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,
8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
others => 9);
function log2ext(i: integer) return integer;
function decode(v : std_logic_vector) return std_logic_vector;
function genmux(s,v : std_logic_vector) return std_ulogic;
function xorv(d : std_logic_vector) return std_ulogic;
function orv(d : std_logic_vector) return std_ulogic;
function andv(d : std_logic_vector) return std_ulogic;
function notx(d : std_logic_vector) return boolean;
function notx(d : std_ulogic) return boolean;
function "-" (d : std_logic_vector; i : integer) return std_logic_vector;
function "-" (i : integer; d : std_logic_vector) return std_logic_vector;
function "+" (d : std_logic_vector; i : integer) return std_logic_vector;
function "+" (i : integer; d : std_logic_vector) return std_logic_vector;
function "-" (d : std_logic_vector; i : std_ulogic) return std_logic_vector;
function "+" (d : std_logic_vector; i : std_ulogic) return std_logic_vector;
function "-" (a, b : std_logic_vector) return std_logic_vector;
function "+" (a, b : std_logic_vector) return std_logic_vector;
function "*" (a, b : std_logic_vector) return std_logic_vector;
function unsigned_mul (a, b : std_logic_vector) return std_logic_vector;
function signed_mul (a, b : std_logic_vector) return std_logic_vector;
function mixed_mul (a, b : std_logic_vector; sign : std_logic) return std_logic_vector;
--function ">" (a, b : std_logic_vector) return boolean;
function "<" (i : integer; b : std_logic_vector) return boolean;
function conv_integer(v : std_logic_vector) return integer;
function conv_integer(v : std_logic) return integer;
function conv_std_logic_vector(i : integer; w : integer) return std_logic_vector;
function conv_std_logic_vector_signed(i : integer; w : integer) return std_logic_vector;
function conv_std_logic(b : boolean) return std_ulogic;
attribute sync_set_reset : string;
attribute async_set_reset : string;
-- Reporting and diagnostics
-- pragma translate_off
function tost(v:std_logic_vector) return string;
function tost(v:std_logic) return string;
function tost(i : integer) return string;
function tost_any(s: std_ulogic) return string;
function tost_bits(s: std_logic_vector) return string;
function tost(b: boolean) return string;
function tost(r: real) return string;
procedure print(s : string);
component report_version
generic (msg1, msg2, msg3, msg4 : string := ""; mdel : integer := 4);
end component;
component report_design
generic (msg1, fabtech, memtech : string := ""; mdel : integer := 4);
end component;
-- pragma translate_on
function unary_to_slv(i: std_logic_vector) return std_logic_vector;
function gray_encoder(idata : in std_logic_vector) return std_logic_vector;
function gray_decoder(idata : in std_logic_vector) return std_logic_vector;
end;
package body stdlib is
function notx(d : std_logic_vector) return boolean is
variable res : boolean;
begin
res := true;
-- pragma translate_off
res := not is_x(d);
-- pragma translate_on
return (res);
end;
function notx(d : std_ulogic) return boolean is
variable res : boolean;
begin
res := true;
-- pragma translate_off
res := not is_x(d);
-- pragma translate_on
return (res);
end;
-- generic decoder
function decode(v : std_logic_vector) return std_logic_vector is
variable res : std_logic_vector((2**v'length)-1 downto 0);
variable i : integer range res'range;
begin
res := (others => '0'); i := 0;
if notx(v) then i := to_integer(unsigned(v)); end if;
res(i) := '1';
return(res);
end;
-- generic multiplexer
function genmux(s,v : std_logic_vector) return std_ulogic is
variable res : std_logic_vector(v'length-1 downto 0);
variable i : integer range res'range;
begin
res := v; i := 0;
if notx(s) then i := to_integer(unsigned(s)); end if;
return(res(i));
end;
-- vector XOR
function xorv(d : std_logic_vector) return std_ulogic is
variable tmp : std_ulogic;
begin
tmp := '0';
for i in d'range loop tmp := tmp xor d(i); end loop;
return(tmp);
end;
-- vector OR
function orv(d : std_logic_vector) return std_ulogic is
variable tmp : std_ulogic;
begin
tmp := '0';
for i in d'range loop tmp := tmp or d(i); end loop;
return(tmp);
end;
-- vector AND
function andv(d : std_logic_vector) return std_ulogic is
variable tmp : std_ulogic;
begin
tmp := '1';
for i in d'range loop tmp := tmp and d(i); end loop;
return(tmp);
end;
-- unsigned multiplication
function "*" (a, b : std_logic_vector) return std_logic_vector is
variable z : std_logic_vector(a'length+b'length-1 downto 0);
begin
-- pragma translate_off
if notx(a&b) then
-- pragma translate_on
return(std_logic_vector(unsigned(a) * unsigned(b)));
-- pragma translate_off
else
z := (others =>'X'); return(z);
end if;
-- pragma translate_on
end;
-- signed multiplication
function signed_mul (a, b : std_logic_vector) return std_logic_vector is
variable z : std_logic_vector(a'length+b'length-1 downto 0);
begin
-- pragma translate_off
if notx(a&b) then
-- pragma translate_on
return(std_logic_vector(signed(a) * signed(b)));
-- pragma translate_off
else
z := (others =>'X'); return(z);
end if;
-- pragma translate_on
end;
-- unsigned multiplication
function unsigned_mul (a, b : std_logic_vector) return std_logic_vector is
variable z : std_logic_vector(a'length+b'length-1 downto 0);
begin
-- pragma translate_off
if notx(a&b) then
-- pragma translate_on
return(std_logic_vector(unsigned(a) * unsigned(b)));
-- pragma translate_off
else
z := (others =>'X'); return(z);
end if;
-- pragma translate_on
end;
-- signed/unsigned multiplication
function mixed_mul (a, b : std_logic_vector; sign : std_logic) return std_logic_vector is
variable z : std_logic_vector(a'length+b'length-1 downto 0);
begin
-- pragma translate_off
if notx(a&b) then
-- pragma translate_on
if sign = '0' then
return(std_logic_vector(unsigned(a) * unsigned(b)));
else
return(std_logic_vector(signed(a) * signed(b)));
end if;
-- pragma translate_off
else
z := (others =>'X'); return(z);
end if;
-- pragma translate_on
end;
-- unsigned addition
function "+" (a, b : std_logic_vector) return std_logic_vector is
variable x : std_logic_vector(a'length-1 downto 0);
variable y : std_logic_vector(b'length-1 downto 0);
begin
-- pragma translate_off
if notx(a&b) then
-- pragma translate_on
return(std_logic_vector(unsigned(a) + unsigned(b)));
-- pragma translate_off
else
x := (others =>'X'); y := (others =>'X');
if (x'length > y'length) then return(x); else return(y); end if;
end if;
-- pragma translate_on
end;
function "+" (i : integer; d : std_logic_vector) return std_logic_vector is
variable x : std_logic_vector(d'length-1 downto 0);
begin
-- pragma translate_off
if notx(d) then
-- pragma translate_on
return(std_logic_vector(unsigned(d) + i));
-- pragma translate_off
else x := (others =>'X'); return(x);
end if;
-- pragma translate_on
end;
function "+" (d : std_logic_vector; i : integer) return std_logic_vector is
variable x : std_logic_vector(d'length-1 downto 0);
begin
-- pragma translate_off
if notx(d) then
-- pragma translate_on
return(std_logic_vector(unsigned(d) + i));
-- pragma translate_off
else x := (others =>'X'); return(x);
end if;
-- pragma translate_on
end;
function "+" (d : std_logic_vector; i : std_ulogic) return std_logic_vector is
variable x : std_logic_vector(d'length-1 downto 0);
variable y : std_logic_vector(0 downto 0);
begin
y(0) := i;
-- pragma translate_off
if notx(d) then
-- pragma translate_on
return(std_logic_vector(unsigned(d) + unsigned(y)));
-- pragma translate_off
else x := (others =>'X'); return(x);
end if;
-- pragma translate_on
end;
-- unsigned subtraction
function "-" (a, b : std_logic_vector) return std_logic_vector is
variable x : std_logic_vector(a'length-1 downto 0);
variable y : std_logic_vector(b'length-1 downto 0);
begin
-- pragma translate_off
if notx(a&b) then
-- pragma translate_on
return(std_logic_vector(unsigned(a) - unsigned(b)));
-- pragma translate_off
else
x := (others =>'X'); y := (others =>'X');
if (x'length > y'length) then return(x); else return(y); end if;
end if;
-- pragma translate_on
end;
function "-" (d : std_logic_vector; i : integer) return std_logic_vector is
variable x : std_logic_vector(d'length-1 downto 0);
begin
-- pragma translate_off
if notx(d) then
-- pragma translate_on
return(std_logic_vector(unsigned(d) - i));
-- pragma translate_off
else x := (others =>'X'); return(x);
end if;
-- pragma translate_on
end;
function "-" (i : integer; d : std_logic_vector) return std_logic_vector is
variable x : std_logic_vector(d'length-1 downto 0);
begin
-- pragma translate_off
if notx(d) then
-- pragma translate_on
return(std_logic_vector(i - unsigned(d)));
-- pragma translate_off
else x := (others =>'X'); return(x);
end if;
-- pragma translate_on
end;
function "-" (d : std_logic_vector; i : std_ulogic) return std_logic_vector is
variable x : std_logic_vector(d'length-1 downto 0);
variable y : std_logic_vector(0 downto 0);
begin
y(0) := i;
-- pragma translate_off
if notx(d) then
-- pragma translate_on
return(std_logic_vector(unsigned(d) - unsigned(y)));
-- pragma translate_off
else x := (others =>'X'); return(x);
end if;
-- pragma translate_on
end;
function ">=" (a, b : std_logic_vector) return boolean is
begin
return(unsigned(a) >= unsigned(b));
end;
function "<" (i : integer; b : std_logic_vector) return boolean is
begin
return( i < to_integer(unsigned(b)));
end;
function ">" (a, b : std_logic_vector) return boolean is
begin
return(unsigned(a) > unsigned(b));
end;
function conv_integer(v : std_logic_vector) return integer is
begin
if notx(v) then return(to_integer(unsigned(v)));
else return(0); end if;
end;
function conv_integer(v : std_logic) return integer is
begin
if notx(v) then
if v = '1' then return(1);
else return(0); end if;
else return(0); end if;
end;
function conv_std_logic_vector(i : integer; w : integer) return std_logic_vector is
variable tmp : std_logic_vector(w-1 downto 0);
begin
tmp := std_logic_vector(to_unsigned(i, w));
return(tmp);
end;
function conv_std_logic_vector_signed(i : integer; w : integer) return std_logic_vector is
variable tmp : std_logic_vector(w-1 downto 0);
begin
tmp := std_logic_vector(to_signed(i, w));
return(tmp);
end;
function conv_std_logic(b : boolean) return std_ulogic is
begin
if b then return('1'); else return('0'); end if;
end;
function log2ext(i: integer) return integer is
-- variable v: std_logic_vector(31 downto 0);
begin
-- workaround for DC bug
-- if i=0 then return 0; end if;
-- v := std_logic_vector(to_unsigned((i-1),v'length));
-- for x in v'high downto v'low loop
-- if v(x)='1' then return x+1; end if;
-- end loop;
-- return 0;
for x in 1 to 32 loop
if (2**x > i) then return (x-1); end if;
end loop;
return 32;
end;
-- pragma translate_off
subtype nibble is std_logic_vector(3 downto 0);
function todec(i:integer) return character is
begin
case i is
when 0 => return('0');
when 1 => return('1');
when 2 => return('2');
when 3 => return('3');
when 4 => return('4');
when 5 => return('5');
when 6 => return('6');
when 7 => return('7');
when 8 => return('8');
when 9 => return('9');
when others => return('0');
end case;
end;
function tohex(n:nibble) return character is
begin
case n is
when "0000" => return('0');
when "0001" => return('1');
when "0010" => return('2');
when "0011" => return('3');
when "0100" => return('4');
when "0101" => return('5');
when "0110" => return('6');
when "0111" => return('7');
when "1000" => return('8');
when "1001" => return('9');
when "1010" => return('a');
when "1011" => return('b');
when "1100" => return('c');
when "1101" => return('d');
when "1110" => return('e');
when "1111" => return('f');
when others => return('X');
end case;
end;
function tost(v:std_logic_vector) return string is
constant vlen : natural := v'length; --'
constant slen : natural := (vlen+3)/4;
variable vv : std_logic_vector(0 to slen*4-1) := (others => '0');
variable s : string(1 to slen);
variable nz : boolean := false;
variable index : integer := -1;
begin
vv(slen*4-vlen to slen*4-1) := v;
for i in 0 to slen-1 loop
if (vv(i*4 to i*4+3) = "0000") and nz and (i /= (slen-1)) then
index := i;
else
nz := false;
s(i+1) := tohex(vv(i*4 to i*4+3));
end if;
end loop;
if ((index +2) = slen) then return(s(slen to slen));
else return(string'("0x") & s(index+2 to slen)); end if; --'
end;
function tost(v:std_logic) return string is
begin
if to_x01(v) = '1' then return("1"); else return("0"); end if;
end;
function tost_any(s: std_ulogic) return string is
begin
case s is
when '1' => return "1";
when '0' => return "0";
when '-' => return "-";
when 'U' => return "U";
when 'X' => return "X";
when 'Z' => return "Z";
when 'H' => return "H";
when 'L' => return "L";
when 'W' => return "W";
end case;
end;
function tost_bits(s: std_logic_vector) return string is
constant len: natural := s'length;
variable str: string(1 to len);
variable i: integer;
begin
i := 1;
for x in s'range loop
str(i to i) := tost_any(s(x));
i := i+1;
end loop;
return str;
end;
function tost(b: boolean) return string is
begin
if b then return "true"; else return "false"; end if;
end tost;
function tost(i : integer) return string is
variable L : line;
variable s, x : string(1 to 128);
variable n, tmp : integer := 0;
begin
tmp := i;
if i < 0 then tmp := -i; end if;
loop
s(128-n) := todec(tmp mod 10);
tmp := tmp / 10;
n := n+1;
if tmp = 0 then exit; end if;
end loop;
x(1 to n) := s(129-n to 128);
if i < 0 then return "-" & x(1 to n); end if;
return(x(1 to n));
end;
function tost(r: real) return string is
variable x: real;
variable i,j: integer;
variable s: string(1 to 30);
variable c: character;
begin
if r = 0.0 then
return "0.0000";
elsif r < 0.0 then
return "-" & tost(-r);
elsif r < 0.001 then
x:=r; i:=0;
while x<1.0 loop x:=x*10.0; i:=i+1; end loop;
return tost(x) & "e-" & tost(i);
elsif r >= 1000000.0 then
x:=10000000.0; i:=6;
while r>=x loop x:=x*10.0; i:=i+1; end loop;
return tost(10.0*r/x) & "e+" & tost(i);
else
i:=0; x:=r+0.00005;
while x >= 10.0 loop x:=x/10.0; i:=i+1; end loop;
j := 1;
while i > -5 loop
if x >= 9.0 then c:='9'; x:=x-9.0;
elsif x >= 8.0 then c:='8'; x:=x-8.0;
elsif x >= 7.0 then c:='7'; x:=x-7.0;
elsif x >= 6.0 then c:='6'; x:=x-6.0;
elsif x >= 5.0 then c:='5'; x:=x-5.0;
elsif x >= 4.0 then c:='4'; x:=x-4.0;
elsif x >= 3.0 then c:='3'; x:=x-3.0;
elsif x >= 2.0 then c:='2'; x:=x-2.0;
elsif x >= 1.0 then c:='1'; x:=x-1.0;
else c:='0';
end if;
s(j) := c;
j:=j+1;
if i=0 then s(j):='.'; j:=j+1; end if;
i:=i-1;
x := x * 10.0;
end loop;
return s(1 to j-1);
end if;
end tost;
procedure print(s : string) is
variable L : line;
begin
L := new string'(s); writeline(output, L);
end;
-- pragma translate_on
function unary_to_slv(i: std_logic_vector) return std_logic_vector is
variable o : std_logic_vector(log2(i'length)-1 downto 0);
begin
-- -- 16 bits unary to binary conversion
-- o(0) := i(1) or i(3) or i(5) or i(7) or i(9) or i(11) or i(13) or i(15);
-- o(1) := i(2) or i(3) or i(6) or i(7) or i(10) or i(11) or i(14) or i(15);
-- o(2) := i(4) or i(5) or i(6) or i(7) or i(12) or i(13) or i(14) or i(15);
-- o(3) := i(8) or i(9) or i(10) or i(11) or i(12) or i(13) or i(14) or i(15);
--
-- -- parametrized conversion
--
-- o(0) := i(1);
--
-- o(0) := unary_to_slv(i(3 downto 2)) or unary_to_slv(i(1 downto 0));
-- o(1) := orv(i(3 downto 2));
--
-- o(1 downto 0) := unary_to_slv(i(7 downto 4)) or unary_to_slv(i(3 downto 0));
-- o(2) := orv(i(7 downto 4));
--
-- o(2 downto 0) := unary_to_slv(i(15 downto 8)) or unary_to_slv(i(7 downto 0));
-- o(3) := orv(i(15 downto 8));
--
assert i'length = 0 or i'length = 2**log2(i'length)
report "unary_to_slv: input vector size must be power of 2"
severity failure;
if i'length > 2 then
-- recursion on left and right halves
o(log2(i'length)-2 downto 0) := unary_to_slv(i(i'left downto (i'left-i'length/2+1))) or unary_to_slv(i((i'left-i'length/2) downto i'right));
o(log2(i'length)-1) := orv(i(i'left downto (i'left-i'length/2+1)));
else
o(0 downto 0) := ( 0 => i(i'left));
end if;
return o;
end unary_to_slv;
function gray_encoder(idata : in std_logic_vector) return std_logic_vector is
variable vdata : std_logic_vector(idata'left downto idata'right);
begin
for i in idata'right to (idata'left)-1 loop
vdata(i) := idata(i) xor idata(i+1);
end loop;
vdata(vdata'left) := idata(idata'left);
return vdata;
end gray_encoder;
function gray_decoder(idata : in std_logic_vector) return std_logic_vector is
variable vdata : std_logic_vector(idata'left downto idata'right);
begin
vdata(vdata'left) := idata(idata'left);
for i in (idata'left)-1 downto idata'right loop
vdata(i) := idata(i) xor vdata(i+1);
end loop;
return vdata;
end gray_decoder;
end;
| gpl-3.0 | 977da5b93840c266afc79c12add20069 | 0.626734 | 2.757154 | false | false | false | false |
pedabraham/MDSM | crs/Contador.vhd | 1 | 1,062 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
---------------------------------------------------
entity Contador is
generic(
n : INTEGER := 4
);
port(
Clk : IN STD_LOGIC;
Clr : IN STD_LOGIC;
CE: in STD_LOGIC;
Count : OUT STD_LOGIC_VECTOR(n-1 downto 0) --Indica el turno en que se detecto un sensor.
);
end Contador;
---------------------------------------------------
architecture Behavioral of Contador is
-------------------SIGNALS-------------------------
signal N_S : std_logic_vector(n-1 downto 0);
signal P_S : std_logic_vector(n-1 downto 0);
-------------------PROCESS-------------------------
begin
comb : process(P_S)
begin
if ( P_S = "1001" ) then
N_S <= "0000";
else
N_S <= P_S + 1;
end if;
Count <= P_S;
end process comb;
sequ : process(clk,clr)
begin
if(Clr = '1') then
P_S <= "0000";
elsif (clk'event AND clk = '1' AND CE='1') then
P_S <= N_S;
end if;
end process sequ;
end Behavioral; | mit | f03142d91a4d5da9cf68d89f5a6eb7bf | 0.492467 | 3.105263 | false | false | false | false |
yishinli/emc2 | src/hal/drivers/mesa-hostmot2/firmware/src/qcountersf.vhd | 1 | 11,404 | library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.std_logic_ARITH.ALL;
use IEEE.std_logic_UNSIGNED.ALL;
--
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
-- http://www.mesanet.com
--
-- This program is is licensed under a disjunctive dual license giving you
-- the choice of one of the two following sets of free software/open source
-- licensing terms:
--
-- * GNU General Public License (GPL), version 2.0 or later
-- * 3-clause BSD License
--
--
-- The GNU GPL License:
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
--
--
-- The 3-clause BSD License:
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- * Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- * Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- * Neither the name of Mesa Electronics nor the names of its
-- contributors may be used to endorse or promote products
-- derived from this software without specific prior written
-- permission.
--
--
-- Disclaimer:
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
entity qcounter is
generic (
buswidth : integer := 32
);
port (
obus: out std_logic_vector (buswidth-1 downto 0);
ibus: in std_logic_vector (buswidth-1 downto 0);
quada: in std_logic;
quadb: in std_logic;
index: in std_logic;
loadccr: in std_logic;
readccr: in std_logic;
readcount: in std_logic;
countclear: in std_logic;
timestamp: in std_logic_vector (15 downto 0);
indexmask: in std_logic;
filterrate: in std_logic;
clk: in std_logic
);
end qcounter;
architecture behavioral of qcounter is
signal count: std_logic_vector (15 downto 0);
signal up: std_logic;
signal down: std_logic;
signal countlatch: std_logic_vector (15 downto 0);
signal timestamplatch: std_logic_vector (15 downto 0);
signal quadadel: std_logic;
signal quada1: std_logic;
signal quada2: std_logic;
signal quadacnt: std_logic_vector (3 downto 0);
signal quadafilt: std_logic;
signal quadbdel: std_logic;
signal quadb1: std_logic;
signal quadb2: std_logic;
signal quadbcnt: std_logic_vector (3 downto 0);
signal quadbfilt: std_logic;
signal indexdel: std_logic;
signal index1: std_logic;
signal index2: std_logic;
signal indexdet: std_logic;
signal indexcnt: std_logic_vector (3 downto 0);
signal indexfilt: std_logic;
signal qcountup: std_logic;
signal qcountdown: std_logic;
signal udcountup: std_logic;
signal udcountdown: std_logic;
signal doclear: std_logic;
signal clearonindex: std_logic; -- ccr register bits...
signal latchonindex:std_logic;
signal justonce: std_logic;
signal abgateindex: std_logic;
signal indexsrc: std_logic;
signal quadfilter: std_logic;
signal countermode: std_logic;
signal quaderror: std_logic;
signal indexpol: std_logic;
signal fixedindexmask: std_logic;
signal indexmaskpol: std_logic;
signal useindexmask: std_logic;
signal abmaskpol: std_logic;
signal flimit: std_logic_vector(3 downto 0);
begin
aqcounter: process (clk,abgateindex, indexpol, indexdel, abmaskpol,
quadadel, quadbdel, indexmaskpol, indexmask,
quadfilter, countermode, doclear, quada2,
quada1, quadb2, quadb1, index1, index2,
useindexmask, readcount, timestamplatch, count,
readccr, countlatch, quaderror, justonce,
clearonindex, latchonindex)
begin
-- new index logic 02/09/2006 PCW
if abgateindex = '0' then -- not gated by A,B
if indexpol = '1' then
indexsrc <= indexdel;
else
indexsrc <= not indexdel;
end if;
else -- gated by A,B
if indexpol = '1' then -- normal index
if abmaskpol = '1' then
indexsrc <= quadadel and quadbdel and indexdel; -- enable by A,B high
else
indexsrc <= (not (quadadel or quadbdel)) and indexdel; -- enable by A,B low
end if;
else -- inverted index
if abmaskpol = '1' then
indexsrc <= quadadel and quadbdel and (not indexdel); -- enable by A,B high
else
indexsrc <= (not (quadadel or quadbdel)) and (not indexdel);-- enable by A,B low
end if;
end if;
end if;
if indexmaskpol = '1' then
fixedindexmask <= indexmask;
else
fixedindexmask <= not indexmask;
end if;
if quadfilter = '1' then
flimit <= "1111";
else
flimit <= "0011";
end if;
if countermode = '0' and doclear = '0' and (
(quada2 = '0' and quada1 = '1' and quadb2 = '0' and quadb1 = '0') or
(quada2 = '0' and quada1 = '0' and quadb2 = '1' and quadb1 = '0') or
(quada2 = '1' and quada1 = '1' and quadb2 = '0' and quadb1 = '1') or
(quada2 = '1' and quada1 = '0' and quadb2 = '1' and quadb1 = '1')) then
qcountup <= '1';
else
qcountup <= '0';
end if;
if (countermode = '1' and doclear = '0' and
quadb2 = '1' and quada2 = '0' and quada1 = '1') then -- up down mode: count up on rising edge of A when B is high
udcountup <= '1';
else
udcountup <= '0';
end if;
if countermode = '0' and doclear = '0' and (
(quada2 = '0' and quada1 = '0' and quadb2 = '0' and quadb1 = '1') or
(quada2 = '0' and quada1 = '1' and quadb2 = '1' and quadb1 = '1') or
(quada2 = '1' and quada1 = '0' and quadb2 = '0' and quadb1 = '0') or
(quada2 = '1' and quada1 = '1' and quadb2 = '1' and quadb1 = '0')) then
qcountdown <= '1';
else
qcountdown <= '0';
end if;
if (countermode = '1' and doclear = '0' and
quadb2 = '0' and quada2 = '0' and quada1 = '1') then
udcountdown <= '1';
else
udcountdown <= '0';
end if;
if rising_edge(clk) then
quadadel <= quada;
quada1 <= quadafilt;
quada2 <= quada1;
quadbdel <= quadb;
quadb1 <= quadbfilt;
quadb2 <= quadb1;
indexdel <= index;
index1 <= indexfilt;
index2 <= index1;
if filterrate = '1' then
-- deadended counter for A input filter --
if (quadadel = '1') and (quadacnt < flimit) then
quadacnt <= quadacnt + 1;
end if;
if (quadadel = '0') and (quadacnt /= 0) then
quadacnt <= quadacnt -1;
end if;
if quadacnt >= flimit then
quadafilt<= '1';
end if;
if quadacnt = 0 then
quadafilt<= '0';
end if;
-- deadended counter for A input filter --
if (quadbdel = '1') and (quadbcnt < flimit ) then
quadbcnt <= quadbcnt + 1;
end if;
if (quadbdel = '0') and (quadbcnt /= 0) then
quadbcnt <= quadbcnt -1;
end if;
if quadbcnt >= flimit then
quadbfilt<= '1';
end if;
if quadbcnt = 0 then
quadbfilt <= '0';
end if;
-- deadended counter for index input filter --
if (indexsrc = '1') and (indexcnt < flimit ) then
indexcnt <= indexcnt + 1;
end if;
if (indexsrc = '0') and (indexcnt /= 0) then
indexcnt <= indexcnt -1;
end if;
if indexcnt >= flimit then
indexfilt<= '1';
end if;
if indexcnt = 0 then
indexfilt<= '0';
end if;
end if;
if (countclear = '1') or
((clearonindex = '1') and (indexdet = '1')) then -- rising edge of conditioned index
doclear <= '1';
if justonce = '1' then
clearonindex <= '0';
end if;
else
doclear <= '0';
end if;
if ((latchonindex = '1') and (indexdet = '1') ) then -- rising edge of conditioned index
countlatch <= count;
if justonce = '1' then
latchonindex <= '0';
end if;
end if;
if countermode = '0' and (
(quada2 = '0' and quada1 = '1' and quadb2 = '0' and quadb1 = '1') or -- any time both a,b change at same time
(quada2 = '1' and quada1 = '0' and quadb2 = '1' and quadb1 = '0') or -- indicates a quadrature count error
(quada2 = '0' and quada1 = '1' and quadb2 = '1' and quadb1 = '0') or
(quada2 = '1' and quada1 = '0' and quadb2 = '0' and quadb1 = '1')) then
quaderror <= '1';
end if;
if up /= down then
timestamplatch <= timestamp; -- time stamp whenever we count
if up = '1' then
count <= count + 1;
else
count <= count - 1;
end if;
end if;
if doclear = '1' then
count <= x"0000";
end if;
if loadccr = '1' then
quaderror <= ibus(15);
abmaskpol <= ibus(14);
-- latchonprobe (bit 13);
-- probepol (bit 12);
quadfilter <= ibus(11);
countermode <= ibus(10);
useindexmask <= ibus(9);
indexmaskpol <= ibus(8);
abgateindex <= ibus(7);
justonce <= ibus(6);
clearonindex <= ibus(5);
latchonindex <= ibus(4);
indexpol <= ibus(3);
end if;
end if; --(clock edge)
if (index1 = '1') and (index2 = '0') and ((fixedindexmask = '1') or (useindexmask = '0')) then
indexdet <= '1';
else
indexdet <= '0';
end if;
if (qcountup = '1' or udcountup = '1' ) and doclear = '0' then
up <= '1';
else
up <= '0';
end if;
if (qcountdown = '1' or udcountdown = '1' ) and doclear = '0' then
down <= '1';
else
down <= '0';
end if;
obus <= (others => 'Z');
if (readcount = '1') then
obus(31 downto 16) <= timestamplatch;
obus(15 downto 0) <= count;
end if;
if (readccr = '1') then
obus(31 downto 16) <= countlatch;
obus(15) <= quaderror;
obus(14) <= abmaskpol;
obus(11) <= quadfilter;
obus(10) <= countermode;
obus(9) <= useindexmask;
obus(8) <= indexmaskpol;
obus(7) <= abgateindex;
obus(6) <= justonce;
obus(5) <= clearonindex;
obus(4) <= latchonindex;
obus(3) <= indexpol;
obus(2) <= index1;
obus(1) <= quadb1;
obus(0) <= quada1;
end if;
end process;
end behavioral;
| lgpl-2.1 | ce9a5be3edcd384b8fb072bc1525659f | 0.624167 | 3.020127 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/greth/greth_gbit.vhd | 1 | 12,300 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: greth_gbit
-- File: greth_gbit.vhd
-- Author: Marko Isomaki
-- Description: Gigabit Ethernet Media Access Controller with Ethernet Debug
-- Communication Link
------------------------------------------------------------------------------
library ieee;
library grlib;
library gaisler;
use ieee.std_logic_1164.all;
use grlib.stdlib.all;
use grlib.amba.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use gaisler.net.all;
use gaisler.ethernet_mac.all;
library eth;
use eth.ethcomp.all;
entity greth_gbit is
generic(
hindex : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#FFF#;
pirq : integer := 0;
memtech : integer := 0;
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
slot_time : integer := 128;
mdcscaler : integer range 0 to 255 := 25;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 3 := 0;
edclbufsz : integer range 1 to 64 := 1;
burstlength : integer range 4 to 128 := 32;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0035#;
phyrstadr : integer range 0 to 32 := 0;
sim : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0;
scanen : integer range 0 to 1 := 0;
ft : integer range 0 to 2 := 0;
edclft : integer range 0 to 2 := 0;
mdint_pol : integer range 0 to 1 := 0;
enable_mdint : integer range 0 to 1 := 0;
multicast : integer range 0 to 1 := 0;
ramdebug : integer range 0 to 2 := 0;
mdiohold : integer := 1;
gmiimode : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ethi : in eth_in_type;
etho : out eth_out_type
);
end entity;
architecture rtl of greth_gbit is
--host constants
constant fifosize : integer := 512;
constant fabits : integer := log2(fifosize);
constant fsize : std_logic_vector(fabits downto 0) :=
conv_std_logic_vector(fifosize, fabits+1);
constant REVISION : amba_version_type := 0;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_ETHMAC, 0, REVISION, pirq),
1 => apb_iobar(paddr, pmask));
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_ETHMAC, 0, REVISION, 0),
others => zero32);
constant ehconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_EDCLMST, 0, REVISION, 0),
others => zero32);
--edcl constants
type szvct is array (0 to 6) of integer;
constant ebuf : szvct := (64, 128, 128, 256, 256, 256, 256);
constant eabits: integer := log2(edclbufsz) + 8;
constant ebufsize : integer := ebuf(log2(edclbufsz));
signal irq : std_ulogic;
signal gnd : std_ulogic;
--rx ahb fifo
signal rxrenable : std_ulogic;
signal rxraddress : std_logic_vector(8 downto 0);
signal rxwrite : std_ulogic;
signal rxwdata : std_logic_vector(31 downto 0);
signal rxwaddress : std_logic_vector(8 downto 0);
signal rxrdata : std_logic_vector(31 downto 0);
--tx ahb fifo
signal txrenable : std_ulogic;
signal txraddress : std_logic_vector(8 downto 0);
signal txwrite : std_ulogic;
signal txwdata : std_logic_vector(31 downto 0);
signal txwaddress : std_logic_vector(8 downto 0);
signal txrdata : std_logic_vector(31 downto 0);
--edcl buf
signal erenable : std_ulogic;
signal eraddress : std_logic_vector(15 downto 0);
signal ewritem : std_ulogic;
signal ewritel : std_ulogic;
signal ewaddressm : std_logic_vector(15 downto 0);
signal ewaddressl : std_logic_vector(15 downto 0);
signal ewdata : std_logic_vector(31 downto 0);
signal erdata : std_logic_vector(31 downto 0);
-- Fix for wider bus
signal hwdata : std_logic_vector(31 downto 0);
signal hrdata : std_logic_vector(31 downto 0);
begin
gnd <= '0';
gtxc0: greth_gbitc
generic map(
ifg_gap => ifg_gap,
attempt_limit => attempt_limit,
backoff_limit => backoff_limit,
slot_time => slot_time,
mdcscaler => mdcscaler,
nsync => nsync,
edcl => edcl,
edclbufsz => edclbufsz,
burstlength => burstlength,
macaddrh => macaddrh,
macaddrl => macaddrl,
ipaddrh => ipaddrh,
ipaddrl => ipaddrl,
phyrstadr => phyrstadr,
sim => sim,
oepol => oepol,
scanen => scanen,
mdint_pol => mdint_pol,
enable_mdint => enable_mdint,
multicast => multicast,
edclsepahbg => 0,
ramdebug => ramdebug,
mdiohold => mdiohold,
gmiimode => gmiimode
)
port map(
rst => rst,
clk => clk,
--ahb mst in
hgrant => ahbmi.hgrant(hindex),
hready => ahbmi.hready,
hresp => ahbmi.hresp,
hrdata => hrdata,
--ahb mst out
hbusreq => ahbmo.hbusreq,
hlock => ahbmo.hlock,
htrans => ahbmo.htrans,
haddr => ahbmo.haddr,
hwrite => ahbmo.hwrite,
hsize => ahbmo.hsize,
hburst => ahbmo.hburst,
hprot => ahbmo.hprot,
hwdata => hwdata,
--edcl ahb mst in
ehgrant => ahbmi.hgrant(hindex),
ehready => ahbmi.hready,
ehresp => ahbmi.hresp,
ehrdata => hrdata,
--edcl ahb mst out
ehbusreq => open,
ehlock => open,
ehtrans => open,
ehaddr => open,
ehwrite => open,
ehsize => open,
ehburst => open,
ehprot => open,
ehwdata => open,
--apb slv in
psel => apbi.psel(pindex),
penable => apbi.penable,
paddr => apbi.paddr,
pwrite => apbi.pwrite,
pwdata => apbi.pwdata,
--apb slv out
prdata => apbo.prdata,
--irq
irq => irq,
--rx ahb fifo
rxrenable => rxrenable,
rxraddress => rxraddress,
rxwrite => rxwrite,
rxwdata => rxwdata,
rxwaddress => rxwaddress,
rxrdata => rxrdata,
--tx ahb fifo
txrenable => txrenable,
txraddress => txraddress,
txwrite => txwrite,
txwdata => txwdata,
txwaddress => txwaddress,
txrdata => txrdata,
--edcl buf
erenable => erenable,
eraddress => eraddress,
ewritem => ewritem,
ewritel => ewritel,
ewaddressm => ewaddressm,
ewaddressl => ewaddressl,
ewdata => ewdata,
erdata => erdata,
--ethernet input signals
gtx_clk => ethi.gtx_clk,
tx_clk => ethi.tx_clk,
tx_dv => ethi.tx_dv,
rx_clk => ethi.rx_clk,
rxd => ethi.rxd,
rx_dv => ethi.rx_dv,
rx_er => ethi.rx_er,
rx_col => ethi.rx_col,
rx_crs => ethi.rx_crs,
rx_en => ethi.rx_en,
mdio_i => ethi.mdio_i,
phyrstaddr => ethi.phyrstaddr,
mdint => ethi.mdint,
--ethernet output signals
reset => etho.reset,
txd => etho.txd,
tx_en => etho.tx_en,
tx_er => etho.tx_er,
mdc => etho.mdc,
mdio_o => etho.mdio_o,
mdio_oe => etho.mdio_oe,
--scantest
testrst => ahbmi.testrst,
testen => ahbmi.testen,
testoen => ahbmi.testoen,
gbit => etho.gbit,
speed => etho.speed,
--cfg
edcladdr => ethi.edcladdr,
edclsepahb => ethi.edclsepahb,
edcldisable => ethi.edcldisable,
mdiochain_first => '1',
mdiochain_ticki => '0',
mdiochain_datai => '0',
mdiochain_locki => '0',
mdiochain_o => '0',
mdiochain_oe => '0');
etho.tx_clk <= '0'; -- driven in rgmii component
irqdrv : process(irq)
begin
apbo.pirq <= (others => '0');
apbo.pirq(pirq) <= irq;
end process;
hrdata <= ahbreadword(ahbmi.hrdata);
ahbmo.hwdata <= ahbdrivedata(hwdata);
ahbmo.hconfig <= hconfig;
ahbmo.hindex <= hindex;
ahbmo.hirq <= (others => '0');
apbo.pconfig <= pconfig;
apbo.pindex <= pindex;
-------------------------------------------------------------------------------
-- FIFOS ----------------------------------------------------------------------
-------------------------------------------------------------------------------
nft : if ft = 0 generate
tx_fifo0 : syncram_2p generic map(tech => memtech, abits => fabits,
dbits => 32, sepclk => 0, testen => scanen)
port map(clk, txrenable, txraddress(fabits-1 downto 0), txrdata, clk,
txwrite, txwaddress(fabits-1 downto 0), txwdata, ahbmi.testin);
rx_fifo0 : syncram_2p generic map(tech => memtech, abits => fabits,
dbits => 32, sepclk => 0, testen => scanen)
port map(clk, rxrenable, rxraddress(fabits-1 downto 0), rxrdata, clk,
rxwrite, rxwaddress(fabits-1 downto 0), rxwdata, ahbmi.testin);
end generate;
-------------------------------------------------------------------------------
-- EDCL buffer ram ------------------------------------------------------------
-------------------------------------------------------------------------------
edclramnft : if (edcl /= 0) and (edclft = 0) generate
r0 : syncram_2p generic map (memtech, eabits, 16, 0, 0, scanen) port map (
clk, erenable, eraddress(eabits-1 downto 0), erdata(31 downto 16), clk,
ewritem, ewaddressm(eabits-1 downto 0), ewdata(31 downto 16), ahbmi.testin);
r1 : syncram_2p generic map (memtech, eabits, 16, 0, 0, scanen) port map (
clk, erenable, eraddress(eabits-1 downto 0), erdata(15 downto 0), clk,
ewritel, ewaddressl(eabits-1 downto 0), ewdata(15 downto 0), ahbmi.testin);
end generate;
-- pragma translate_off
bootmsg : report_version
generic map (
"greth" & tost(hindex) & ": 10/100/1000 Mbit Ethernet MAC rev " &
tost(REVISION) & tost(hindex) & ", EDCL " & tost(edcl) & ", buffer " &
tost(edclbufsz*edcl) & " kbyte " & tost(fifosize) & " txfifo, " &
" irq " & tost(pirq)
);
-- pragma translate_on
end architecture;
| gpl-3.0 | 3de82709a6eafbae5b49a4e31ccccc7d | 0.516748 | 4.186521 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-altera-ep2s60-ddr/testbench.vhd | 1 | 10,622 | ------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library cypress;
use cypress.components.all;
use work.debug.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20; -- system clock period
romwidth : integer := 8; -- rom data width (8/32)
romdepth : integer := 23; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 20; -- ram address depth
srambanks : integer := 1 -- number of ram banks
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal clk : std_logic := '0';
signal clkout, pllref : std_ulogic;
signal Rst : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal address : std_logic_vector(23 downto 0);
signal data : std_logic_vector(31 downto 0);
signal romsn : std_ulogic;
signal iosn : std_ulogic;
signal oen : std_ulogic;
signal writen : std_ulogic;
signal dsuen, dsutx, dsurx, dsubren, dsuact : std_ulogic;
signal dsurst : std_ulogic;
signal test : std_ulogic;
signal error : std_logic;
signal gpio : std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal clk2 : std_ulogic := '1';
signal ssram_ce1n : std_logic;
signal ssram_ce2 : std_logic;
signal ssram_ce3n : std_logic;
signal ssram_wen : std_logic;
signal ssram_bw : std_logic_vector (0 to 3);
signal ssram_oen : std_ulogic;
signal ssaddr : std_logic_vector(20 downto 2);
signal ssdata : std_logic_vector(31 downto 0);
signal ssram_clk : std_ulogic;
signal ssram_adscn : std_ulogic;
signal ssram_adsp_n : std_ulogic;
signal ssram_adv_n : std_ulogic;
signal datazz : std_logic_vector(3 downto 0);
-- ddr memory
signal ddr_clk : std_logic;
signal ddr_clkb : std_logic;
signal ddr_clkin : std_logic;
signal ddr_cke : std_logic;
signal ddr_csb : std_logic;
signal ddr_web : std_ulogic; -- ddr write enable
signal ddr_rasb : std_ulogic; -- ddr ras
signal ddr_casb : std_ulogic; -- ddr cas
signal ddr_dm : std_logic_vector (1 downto 0); -- ddr dm
signal ddr_dqs : std_logic_vector (1 downto 0); -- ddr dqs
signal ddr_dqs2 : std_logic_vector (1 downto 0); -- ddr dqs
signal ddr_ad : std_logic_vector (12 downto 0); -- ddr address
signal ddr_ba : std_logic_vector (1 downto 0); -- ddr bank address
signal ddr_dq, ddr_dq2 : std_logic_vector (15 downto 0); -- ddr data
signal plllock : std_ulogic;
signal txd1, rxd1 : std_ulogic;
--signal txd2, rxd2 : std_ulogic;
-- for smc lan chip
signal eth_aen : std_ulogic; -- for smsc eth
signal eth_readn : std_ulogic; -- for smsc eth
signal eth_writen : std_ulogic; -- for smsc eth
signal eth_nbe : std_logic_vector(3 downto 0); -- for smsc eth
signal eth_datacsn : std_ulogic;
constant lresp : boolean := false;
signal sa : std_logic_vector(14 downto 0);
signal sd : std_logic_vector(31 downto 0);
begin
-- clock and reset
clk <= not clk after ct * 1 ns;
ddr_clkin <= not clk after ct * 1 ns;
rst <= dsurst;
dsubren <= '1'; rxd1 <= '1';
dqs2delay : delay_wire
generic map(data_width => ddr_dqs'length, delay_atob => 3.0, delay_btoa => 1.0)
port map(a => ddr_dqs, b => ddr_dqs2);
ddr2delay : delay_wire
generic map(data_width => ddr_dq'length, delay_atob => 3.0, delay_btoa => 1.0)
port map(a => ddr_dq, b => ddr_dq2);
-- ddr_dqs <= (others => 'L');
d3 : entity work.leon3mp generic map (fabtech, memtech, padtech, clktech,
ncpu, disas, dbguart, pclow )
port map (rst, clk, error,
address, data, romsn, oen, writen, open, open,
ssram_ce1n, ssram_ce2, ssram_ce3n, ssram_wen, ssram_bw, ssram_oen, ssaddr, ssdata,
ssram_clk, ssram_adscn, ssram_adsp_n, ssram_adv_n, iosn,
ddr_clkin, ddr_clk, ddr_clkb, ddr_cke, ddr_csb, ddr_web, ddr_rasb,
ddr_casb, ddr_dm, ddr_dqs2, ddr_ad, ddr_ba, ddr_dq2,
dsubren, dsuact, rxd1, txd1,
eth_aen, eth_readn, eth_writen, eth_nbe);
ddr2: ddrram
generic map (width => 16, abits => 13,
colbits => 9, rowbits => 12, implbanks => 1,
fname => sdramfile, igndqs => 1)
port map (
ck => ddr_clk, cke => ddr_cke, csn => ddr_csb,
rasn => ddr_rasb, casn => ddr_casb, wen => ddr_web,
dm => ddr_dm, ba => ddr_ba, a => ddr_ad, dq => ddr_dq, dqs => ddr_dqs);
datazz <= "HHHH";
ssram0 : cy7c1380d generic map (fname => sramfile)
port map(
ioDq(35 downto 32) => datazz, ioDq(31 downto 0) => ssdata,
iAddr => ssaddr(20 downto 2), iMode => gnd,
inGW => vcc, inBWE => ssram_wen, inADV => ssram_adv_n,
inADSP => ssram_adsp_n, inADSC => ssram_adscn,
iClk => ssram_clk,
inBwa => ssram_bw(3), inBwb => ssram_bw(2),
inBwc => ssram_bw(1), inBwd => ssram_bw(0),
inOE => ssram_oen, inCE1 => ssram_ce1n,
iCE2 => ssram_ce2, inCE3 => ssram_ce3n, iZz => gnd);
-- 8 bit prom
prom0 : sram generic map (index => 6, abits => romdepth, fname => promfile)
port map (address(romdepth-1 downto 0), data(31 downto 24),
romsn, writen, oen);
error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 2500 ns;
if to_x01(error) = '1' then wait on error; end if;
assert (to_x01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
data <= buskeep(data), (others => 'H') after 250 ns;
sd <= buskeep(sd), (others => 'H') after 250 ns;
test0 : grtestmod
port map ( rst, clk, error, address(21 downto 2), data,
iosn, oen, writen, open);
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
wait for 500 ns;
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#02#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#24#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#03#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#fc#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#6f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#11#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#04#, txp);
txa(dsutx, 16#00#, 16#02#, 16#20#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#02#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#43#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end ;
| gpl-3.0 | 0ac7b7d1727e44d581a6e161444b1382 | 0.582941 | 3.065512 | false | false | false | false |
hoglet67/CoPro6502 | src/ROM/tuberom_68000.vhd | 1 | 836,299 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tuberom_68000 is
port (
CLK : in std_logic;
ADDR : in std_logic_vector(13 downto 0);
DATA : out std_logic_vector(15 downto 0)
);
end;
architecture RTL of tuberom_68000 is
signal rom_addr : std_logic_vector(13 downto 0);
begin
p_addr : process(ADDR)
begin
rom_addr <= (others => '0');
rom_addr(13 downto 0) <= ADDR;
end process;
p_rom : process
begin
wait until rising_edge(CLK);
DATA <= (others => '0');
case rom_addr is
when "00" & x"000" => DATA <= x"0000";
when "00" & x"001" => DATA <= x"0620";
when "00" & x"002" => DATA <= x"003f";
when "00" & x"003" => DATA <= x"0200";
when "00" & x"004" => DATA <= x"003f";
when "00" & x"005" => DATA <= x"062a";
when "00" & x"006" => DATA <= x"003f";
when "00" & x"007" => DATA <= x"0732";
when "00" & x"008" => DATA <= x"003f";
when "00" & x"009" => DATA <= x"0740";
when "00" & x"00a" => DATA <= x"003f";
when "00" & x"00b" => DATA <= x"074c";
when "00" & x"00c" => DATA <= x"003f";
when "00" & x"00d" => DATA <= x"0764";
when "00" & x"00e" => DATA <= x"003f";
when "00" & x"00f" => DATA <= x"0764";
when "00" & x"010" => DATA <= x"003f";
when "00" & x"011" => DATA <= x"0758";
when "00" & x"012" => DATA <= x"003f";
when "00" & x"013" => DATA <= x"0764";
when "00" & x"014" => DATA <= x"003f";
when "00" & x"015" => DATA <= x"0764";
when "00" & x"016" => DATA <= x"003f";
when "00" & x"017" => DATA <= x"0764";
when "00" & x"018" => DATA <= x"003f";
when "00" & x"019" => DATA <= x"0764";
when "00" & x"01a" => DATA <= x"003f";
when "00" & x"01b" => DATA <= x"0764";
when "00" & x"01c" => DATA <= x"003f";
when "00" & x"01d" => DATA <= x"0764";
when "00" & x"01e" => DATA <= x"003f";
when "00" & x"01f" => DATA <= x"0764";
when "00" & x"020" => DATA <= x"003f";
when "00" & x"021" => DATA <= x"0764";
when "00" & x"022" => DATA <= x"003f";
when "00" & x"023" => DATA <= x"0764";
when "00" & x"024" => DATA <= x"003f";
when "00" & x"025" => DATA <= x"0764";
when "00" & x"026" => DATA <= x"003f";
when "00" & x"027" => DATA <= x"0764";
when "00" & x"028" => DATA <= x"003f";
when "00" & x"029" => DATA <= x"0764";
when "00" & x"02a" => DATA <= x"003f";
when "00" & x"02b" => DATA <= x"0764";
when "00" & x"02c" => DATA <= x"003f";
when "00" & x"02d" => DATA <= x"0764";
when "00" & x"02e" => DATA <= x"003f";
when "00" & x"02f" => DATA <= x"0764";
when "00" & x"030" => DATA <= x"003f";
when "00" & x"031" => DATA <= x"0764";
when "00" & x"032" => DATA <= x"003f";
when "00" & x"033" => DATA <= x"25b2";
when "00" & x"034" => DATA <= x"003f";
when "00" & x"035" => DATA <= x"0450";
when "00" & x"036" => DATA <= x"003f";
when "00" & x"037" => DATA <= x"25b2";
when "00" & x"038" => DATA <= x"003f";
when "00" & x"039" => DATA <= x"25b2";
when "00" & x"03a" => DATA <= x"003f";
when "00" & x"03b" => DATA <= x"0602";
when "00" & x"03c" => DATA <= x"003f";
when "00" & x"03d" => DATA <= x"25b2";
when "00" & x"03e" => DATA <= x"003f";
when "00" & x"03f" => DATA <= x"25b2";
when "00" & x"040" => DATA <= x"003f";
when "00" & x"041" => DATA <= x"0764";
when "00" & x"042" => DATA <= x"003f";
when "00" & x"043" => DATA <= x"0764";
when "00" & x"044" => DATA <= x"003f";
when "00" & x"045" => DATA <= x"0764";
when "00" & x"046" => DATA <= x"003f";
when "00" & x"047" => DATA <= x"0764";
when "00" & x"048" => DATA <= x"003f";
when "00" & x"049" => DATA <= x"0764";
when "00" & x"04a" => DATA <= x"003f";
when "00" & x"04b" => DATA <= x"0764";
when "00" & x"04c" => DATA <= x"003f";
when "00" & x"04d" => DATA <= x"0764";
when "00" & x"04e" => DATA <= x"003f";
when "00" & x"04f" => DATA <= x"0764";
when "00" & x"050" => DATA <= x"003f";
when "00" & x"051" => DATA <= x"0764";
when "00" & x"052" => DATA <= x"003f";
when "00" & x"053" => DATA <= x"0764";
when "00" & x"054" => DATA <= x"003f";
when "00" & x"055" => DATA <= x"0764";
when "00" & x"056" => DATA <= x"003f";
when "00" & x"057" => DATA <= x"0764";
when "00" & x"058" => DATA <= x"003f";
when "00" & x"059" => DATA <= x"0900";
when "00" & x"05a" => DATA <= x"003f";
when "00" & x"05b" => DATA <= x"0764";
when "00" & x"05c" => DATA <= x"003f";
when "00" & x"05d" => DATA <= x"0764";
when "00" & x"05e" => DATA <= x"003f";
when "00" & x"05f" => DATA <= x"0764";
when "00" & x"060" => DATA <= x"003f";
when "00" & x"061" => DATA <= x"0764";
when "00" & x"062" => DATA <= x"003f";
when "00" & x"063" => DATA <= x"0764";
when "00" & x"064" => DATA <= x"003f";
when "00" & x"065" => DATA <= x"0764";
when "00" & x"066" => DATA <= x"003f";
when "00" & x"067" => DATA <= x"0764";
when "00" & x"068" => DATA <= x"003f";
when "00" & x"069" => DATA <= x"0764";
when "00" & x"06a" => DATA <= x"003f";
when "00" & x"06b" => DATA <= x"0764";
when "00" & x"06c" => DATA <= x"003f";
when "00" & x"06d" => DATA <= x"0764";
when "00" & x"06e" => DATA <= x"003f";
when "00" & x"06f" => DATA <= x"0764";
when "00" & x"070" => DATA <= x"003f";
when "00" & x"071" => DATA <= x"0764";
when "00" & x"072" => DATA <= x"003f";
when "00" & x"073" => DATA <= x"0764";
when "00" & x"074" => DATA <= x"003f";
when "00" & x"075" => DATA <= x"0764";
when "00" & x"076" => DATA <= x"003f";
when "00" & x"077" => DATA <= x"0764";
when "00" & x"078" => DATA <= x"003f";
when "00" & x"079" => DATA <= x"0764";
when "00" & x"07a" => DATA <= x"003f";
when "00" & x"07b" => DATA <= x"0764";
when "00" & x"07c" => DATA <= x"003f";
when "00" & x"07d" => DATA <= x"0764";
when "00" & x"07e" => DATA <= x"003f";
when "00" & x"07f" => DATA <= x"0764";
when "00" & x"080" => DATA <= x"003f";
when "00" & x"081" => DATA <= x"077a";
when "00" & x"082" => DATA <= x"003f";
when "00" & x"083" => DATA <= x"2570";
when "00" & x"084" => DATA <= x"003f";
when "00" & x"085" => DATA <= x"25b2";
when "00" & x"086" => DATA <= x"003f";
when "00" & x"087" => DATA <= x"25ca";
when "00" & x"088" => DATA <= x"003f";
when "00" & x"089" => DATA <= x"0a24";
when "00" & x"08a" => DATA <= x"003f";
when "00" & x"08b" => DATA <= x"0a34";
when "00" & x"08c" => DATA <= x"003f";
when "00" & x"08d" => DATA <= x"0ad6";
when "00" & x"08e" => DATA <= x"003f";
when "00" & x"08f" => DATA <= x"0be8";
when "00" & x"090" => DATA <= x"003f";
when "00" & x"091" => DATA <= x"0cce";
when "00" & x"092" => DATA <= x"003f";
when "00" & x"093" => DATA <= x"0d1e";
when "00" & x"094" => DATA <= x"003f";
when "00" & x"095" => DATA <= x"0d4a";
when "00" & x"096" => DATA <= x"003f";
when "00" & x"097" => DATA <= x"0d60";
when "00" & x"098" => DATA <= x"003f";
when "00" & x"099" => DATA <= x"0d7e";
when "00" & x"09a" => DATA <= x"003f";
when "00" & x"09b" => DATA <= x"0dc2";
when "00" & x"09c" => DATA <= x"003f";
when "00" & x"09d" => DATA <= x"0df0";
when "00" & x"09e" => DATA <= x"003f";
when "00" & x"09f" => DATA <= x"10da";
when "00" & x"0a0" => DATA <= x"003f";
when "00" & x"0a1" => DATA <= x"25dc";
when "00" & x"0a2" => DATA <= x"003f";
when "00" & x"0a3" => DATA <= x"077a";
when "00" & x"0a4" => DATA <= x"003f";
when "00" & x"0a5" => DATA <= x"077a";
when "00" & x"0a6" => DATA <= x"003f";
when "00" & x"0a7" => DATA <= x"077a";
when "00" & x"0a8" => DATA <= x"003f";
when "00" & x"0a9" => DATA <= x"077a";
when "00" & x"0aa" => DATA <= x"003f";
when "00" & x"0ab" => DATA <= x"077a";
when "00" & x"0ac" => DATA <= x"003f";
when "00" & x"0ad" => DATA <= x"077a";
when "00" & x"0ae" => DATA <= x"003f";
when "00" & x"0af" => DATA <= x"077a";
when "00" & x"0b0" => DATA <= x"003f";
when "00" & x"0b1" => DATA <= x"25de";
when "00" & x"0b2" => DATA <= x"003f";
when "00" & x"0b3" => DATA <= x"077a";
when "00" & x"0b4" => DATA <= x"003f";
when "00" & x"0b5" => DATA <= x"0f0e";
when "00" & x"0b6" => DATA <= x"003f";
when "00" & x"0b7" => DATA <= x"077a";
when "00" & x"0b8" => DATA <= x"003f";
when "00" & x"0b9" => DATA <= x"077a";
when "00" & x"0ba" => DATA <= x"003f";
when "00" & x"0bb" => DATA <= x"077a";
when "00" & x"0bc" => DATA <= x"003f";
when "00" & x"0bd" => DATA <= x"25ee";
when "00" & x"0be" => DATA <= x"003f";
when "00" & x"0bf" => DATA <= x"077a";
when "00" & x"0c0" => DATA <= x"003f";
when "00" & x"0c1" => DATA <= x"077a";
when "00" & x"0c2" => DATA <= x"003f";
when "00" & x"0c3" => DATA <= x"077a";
when "00" & x"0c4" => DATA <= x"003f";
when "00" & x"0c5" => DATA <= x"077a";
when "00" & x"0c6" => DATA <= x"003f";
when "00" & x"0c7" => DATA <= x"077a";
when "00" & x"0c8" => DATA <= x"003f";
when "00" & x"0c9" => DATA <= x"077a";
when "00" & x"0ca" => DATA <= x"003f";
when "00" & x"0cb" => DATA <= x"077a";
when "00" & x"0cc" => DATA <= x"003f";
when "00" & x"0cd" => DATA <= x"077a";
when "00" & x"0ce" => DATA <= x"003f";
when "00" & x"0cf" => DATA <= x"077a";
when "00" & x"0d0" => DATA <= x"003f";
when "00" & x"0d1" => DATA <= x"077a";
when "00" & x"0d2" => DATA <= x"003f";
when "00" & x"0d3" => DATA <= x"077a";
when "00" & x"0d4" => DATA <= x"003f";
when "00" & x"0d5" => DATA <= x"077a";
when "00" & x"0d6" => DATA <= x"003f";
when "00" & x"0d7" => DATA <= x"077a";
when "00" & x"0d8" => DATA <= x"0000";
when "00" & x"0d9" => DATA <= x"0000";
when "00" & x"0da" => DATA <= x"0000";
when "00" & x"0db" => DATA <= x"0000";
when "00" & x"0dc" => DATA <= x"0000";
when "00" & x"0dd" => DATA <= x"0000";
when "00" & x"0de" => DATA <= x"0000";
when "00" & x"0df" => DATA <= x"0000";
when "00" & x"0e0" => DATA <= x"0000";
when "00" & x"0e1" => DATA <= x"0000";
when "00" & x"0e2" => DATA <= x"003f";
when "00" & x"0e3" => DATA <= x"265a";
when "00" & x"0e4" => DATA <= x"003f";
when "00" & x"0e5" => DATA <= x"265e";
when "00" & x"0e6" => DATA <= x"003f";
when "00" & x"0e7" => DATA <= x"2662";
when "00" & x"0e8" => DATA <= x"003f";
when "00" & x"0e9" => DATA <= x"266c";
when "00" & x"0ea" => DATA <= x"0000";
when "00" & x"0eb" => DATA <= x"0000";
when "00" & x"0ec" => DATA <= x"0000";
when "00" & x"0ed" => DATA <= x"0000";
when "00" & x"0ee" => DATA <= x"0000";
when "00" & x"0ef" => DATA <= x"0000";
when "00" & x"0f0" => DATA <= x"0000";
when "00" & x"0f1" => DATA <= x"0000";
when "00" & x"0f2" => DATA <= x"0000";
when "00" & x"0f3" => DATA <= x"0000";
when "00" & x"0f4" => DATA <= x"0000";
when "00" & x"0f5" => DATA <= x"0000";
when "00" & x"0f6" => DATA <= x"0000";
when "00" & x"0f7" => DATA <= x"0000";
when "00" & x"0f8" => DATA <= x"0000";
when "00" & x"0f9" => DATA <= x"0000";
when "00" & x"0fa" => DATA <= x"0000";
when "00" & x"0fb" => DATA <= x"0700";
when "00" & x"0fc" => DATA <= x"0000";
when "00" & x"0fd" => DATA <= x"0000";
when "00" & x"0fe" => DATA <= x"0000";
when "00" & x"0ff" => DATA <= x"0000";
when "00" & x"100" => DATA <= x"207c";
when "00" & x"101" => DATA <= x"0000";
when "00" & x"102" => DATA <= x"0000";
when "00" & x"103" => DATA <= x"227c";
when "00" & x"104" => DATA <= x"003f";
when "00" & x"105" => DATA <= x"0000";
when "00" & x"106" => DATA <= x"303c";
when "00" & x"107" => DATA <= x"003f";
when "00" & x"108" => DATA <= x"20d9";
when "00" & x"109" => DATA <= x"51c8";
when "00" & x"10a" => DATA <= x"fffc";
when "00" & x"10b" => DATA <= x"303c";
when "00" & x"10c" => DATA <= x"00bf";
when "00" & x"10d" => DATA <= x"20fc";
when "00" & x"10e" => DATA <= x"003f";
when "00" & x"10f" => DATA <= x"0764";
when "00" & x"110" => DATA <= x"51c8";
when "00" & x"111" => DATA <= x"fff8";
when "00" & x"112" => DATA <= x"303c";
when "00" & x"113" => DATA <= x"003f";
when "00" & x"114" => DATA <= x"207c";
when "00" & x"115" => DATA <= x"0000";
when "00" & x"116" => DATA <= x"0400";
when "00" & x"117" => DATA <= x"227c";
when "00" & x"118" => DATA <= x"003f";
when "00" & x"119" => DATA <= x"0100";
when "00" & x"11a" => DATA <= x"20d9";
when "00" & x"11b" => DATA <= x"51c8";
when "00" & x"11c" => DATA <= x"fffc";
when "00" & x"11d" => DATA <= x"203c";
when "00" & x"11e" => DATA <= x"0001";
when "00" & x"11f" => DATA <= x"fedf";
when "00" & x"120" => DATA <= x"207c";
when "00" & x"121" => DATA <= x"0000";
when "00" & x"122" => DATA <= x"0500";
when "00" & x"123" => DATA <= x"20fc";
when "00" & x"124" => DATA <= x"0000";
when "00" & x"125" => DATA <= x"0000";
when "00" & x"126" => DATA <= x"51c8";
when "00" & x"127" => DATA <= x"fff8";
when "00" & x"128" => DATA <= x"6100";
when "00" & x"129" => DATA <= x"0678";
when "00" & x"12a" => DATA <= x"21c0";
when "00" & x"12b" => DATA <= x"0508";
when "00" & x"12c" => DATA <= x"2e40";
when "00" & x"12d" => DATA <= x"0480";
when "00" & x"12e" => DATA <= x"0000";
when "00" & x"12f" => DATA <= x"0200";
when "00" & x"130" => DATA <= x"2c40";
when "00" & x"131" => DATA <= x"4e66";
when "00" & x"132" => DATA <= x"0480";
when "00" & x"133" => DATA <= x"0000";
when "00" & x"134" => DATA <= x"0200";
when "00" & x"135" => DATA <= x"23c0";
when "00" & x"136" => DATA <= x"0000";
when "00" & x"137" => DATA <= x"0500";
when "00" & x"138" => DATA <= x"33fc";
when "00" & x"139" => DATA <= x"0000";
when "00" & x"13a" => DATA <= x"0000";
when "00" & x"13b" => DATA <= x"0524";
when "00" & x"13c" => DATA <= x"23fc";
when "00" & x"13d" => DATA <= x"0000";
when "00" & x"13e" => DATA <= x"0800";
when "00" & x"13f" => DATA <= x"0000";
when "00" & x"140" => DATA <= x"0504";
when "00" & x"141" => DATA <= x"6100";
when "00" & x"142" => DATA <= x"0506";
when "00" & x"143" => DATA <= x"11c0";
when "00" & x"144" => DATA <= x"0532";
when "00" & x"145" => DATA <= x"6100";
when "00" & x"146" => DATA <= x"057c";
when "00" & x"147" => DATA <= x"11c0";
when "00" & x"148" => DATA <= x"0533";
when "00" & x"149" => DATA <= x"6100";
when "00" & x"14a" => DATA <= x"0596";
when "00" & x"14b" => DATA <= x"11c0";
when "00" & x"14c" => DATA <= x"0534";
when "00" & x"14d" => DATA <= x"11fc";
when "00" & x"14e" => DATA <= x"0000";
when "00" & x"14f" => DATA <= x"0535";
when "00" & x"150" => DATA <= x"6100";
when "00" & x"151" => DATA <= x"0bfc";
when "00" & x"152" => DATA <= x"027c";
when "00" & x"153" => DATA <= x"dfff";
when "00" & x"154" => DATA <= x"203c";
when "00" & x"155" => DATA <= x"003f";
when "00" & x"156" => DATA <= x"27e6";
when "00" & x"157" => DATA <= x"6100";
when "00" & x"158" => DATA <= x"0752";
when "00" & x"159" => DATA <= x"1038";
when "00" & x"15a" => DATA <= x"0532";
when "00" & x"15b" => DATA <= x"b07c";
when "00" & x"15c" => DATA <= x"0009";
when "00" & x"15d" => DATA <= x"6500";
when "00" & x"15e" => DATA <= x"0004";
when "00" & x"15f" => DATA <= x"7000";
when "00" & x"160" => DATA <= x"0c38";
when "00" & x"161" => DATA <= x"00ff";
when "00" & x"162" => DATA <= x"0532";
when "00" & x"163" => DATA <= x"6700";
when "00" & x"164" => DATA <= x"001e";
when "00" & x"165" => DATA <= x"203c";
when "00" & x"166" => DATA <= x"003f";
when "00" & x"167" => DATA <= x"2804";
when "00" & x"168" => DATA <= x"d038";
when "00" & x"169" => DATA <= x"0532";
when "00" & x"16a" => DATA <= x"d038";
when "00" & x"16b" => DATA <= x"0532";
when "00" & x"16c" => DATA <= x"d038";
when "00" & x"16d" => DATA <= x"0532";
when "00" & x"16e" => DATA <= x"7203";
when "00" & x"16f" => DATA <= x"6100";
when "00" & x"170" => DATA <= x"1092";
when "00" & x"171" => DATA <= x"6000";
when "00" & x"172" => DATA <= x"000a";
when "00" & x"173" => DATA <= x"103c";
when "00" & x"174" => DATA <= x"004b";
when "00" & x"175" => DATA <= x"6100";
when "00" & x"176" => DATA <= x"06fe";
when "00" & x"177" => DATA <= x"203c";
when "00" & x"178" => DATA <= x"003f";
when "00" & x"179" => DATA <= x"27f1";
when "00" & x"17a" => DATA <= x"6100";
when "00" & x"17b" => DATA <= x"070c";
when "00" & x"17c" => DATA <= x"2038";
when "00" & x"17d" => DATA <= x"0508";
when "00" & x"17e" => DATA <= x"ea88";
when "00" & x"17f" => DATA <= x"ea88";
when "00" & x"180" => DATA <= x"223c";
when "00" & x"181" => DATA <= x"0000";
when "00" & x"182" => DATA <= x"0600";
when "00" & x"183" => DATA <= x"243c";
when "00" & x"184" => DATA <= x"0000";
when "00" & x"185" => DATA <= x"00ff";
when "00" & x"186" => DATA <= x"6100";
when "00" & x"187" => DATA <= x"1484";
when "00" & x"188" => DATA <= x"203c";
when "00" & x"189" => DATA <= x"0000";
when "00" & x"18a" => DATA <= x"0600";
when "00" & x"18b" => DATA <= x"6100";
when "00" & x"18c" => DATA <= x"06ea";
when "00" & x"18d" => DATA <= x"203c";
when "00" & x"18e" => DATA <= x"003f";
when "00" & x"18f" => DATA <= x"281f";
when "00" & x"190" => DATA <= x"7207";
when "00" & x"191" => DATA <= x"6100";
when "00" & x"192" => DATA <= x"104e";
when "00" & x"193" => DATA <= x"7227";
when "00" & x"194" => DATA <= x"6100";
when "00" & x"195" => DATA <= x"0e2a";
when "00" & x"196" => DATA <= x"6100";
when "00" & x"197" => DATA <= x"00a6";
when "00" & x"198" => DATA <= x"2f00";
when "00" & x"199" => DATA <= x"7001";
when "00" & x"19a" => DATA <= x"223c";
when "00" & x"19b" => DATA <= x"0000";
when "00" & x"19c" => DATA <= x"0528";
when "00" & x"19d" => DATA <= x"6100";
when "00" & x"19e" => DATA <= x"08ac";
when "00" & x"19f" => DATA <= x"11fc";
when "00" & x"1a0" => DATA <= x"0000";
when "00" & x"1a1" => DATA <= x"052d";
when "00" & x"1a2" => DATA <= x"11fc";
when "00" & x"1a3" => DATA <= x"0000";
when "00" & x"1a4" => DATA <= x"052e";
when "00" & x"1a5" => DATA <= x"11fc";
when "00" & x"1a6" => DATA <= x"0000";
when "00" & x"1a7" => DATA <= x"052f";
when "00" & x"1a8" => DATA <= x"11fc";
when "00" & x"1a9" => DATA <= x"0000";
when "00" & x"1aa" => DATA <= x"0530";
when "00" & x"1ab" => DATA <= x"11fc";
when "00" & x"1ac" => DATA <= x"0000";
when "00" & x"1ad" => DATA <= x"0531";
when "00" & x"1ae" => DATA <= x"201f";
when "00" & x"1af" => DATA <= x"b03c";
when "00" & x"1b0" => DATA <= x"0080";
when "00" & x"1b1" => DATA <= x"103c";
when "00" & x"1b2" => DATA <= x"002a";
when "00" & x"1b3" => DATA <= x"6100";
when "00" & x"1b4" => DATA <= x"0682";
when "00" & x"1b5" => DATA <= x"203c";
when "00" & x"1b6" => DATA <= x"0000";
when "00" & x"1b7" => DATA <= x"0600";
when "00" & x"1b8" => DATA <= x"223c";
when "00" & x"1b9" => DATA <= x"0000";
when "00" & x"1ba" => DATA <= x"00ff";
when "00" & x"1bb" => DATA <= x"143c";
when "00" & x"1bc" => DATA <= x"0020";
when "00" & x"1bd" => DATA <= x"163c";
when "00" & x"1be" => DATA <= x"00ff";
when "00" & x"1bf" => DATA <= x"207c";
when "00" & x"1c0" => DATA <= x"0000";
when "00" & x"1c1" => DATA <= x"007d";
when "00" & x"1c2" => DATA <= x"4e4c";
when "00" & x"1c3" => DATA <= x"6500";
when "00" & x"1c4" => DATA <= x"0012";
when "00" & x"1c5" => DATA <= x"203c";
when "00" & x"1c6" => DATA <= x"0000";
when "00" & x"1c7" => DATA <= x"0600";
when "00" & x"1c8" => DATA <= x"207c";
when "00" & x"1c9" => DATA <= x"0000";
when "00" & x"1ca" => DATA <= x"0005";
when "00" & x"1cb" => DATA <= x"4e4c";
when "00" & x"1cc" => DATA <= x"60c8";
when "00" & x"1cd" => DATA <= x"707e";
when "00" & x"1ce" => DATA <= x"6100";
when "00" & x"1cf" => DATA <= x"0738";
when "00" & x"1d0" => DATA <= x"203c";
when "00" & x"1d1" => DATA <= x"003f";
when "00" & x"1d2" => DATA <= x"2d7c";
when "00" & x"1d3" => DATA <= x"207c";
when "00" & x"1d4" => DATA <= x"0000";
when "00" & x"1d5" => DATA <= x"002b";
when "00" & x"1d6" => DATA <= x"4e4c";
when "00" & x"1d7" => DATA <= x"60b2";
when "00" & x"1d8" => DATA <= x"0839";
when "00" & x"1d9" => DATA <= x"0007";
when "00" & x"1da" => DATA <= x"fffe";
when "00" & x"1db" => DATA <= x"0000";
when "00" & x"1dc" => DATA <= x"6600";
when "00" & x"1dd" => DATA <= x"0012";
when "00" & x"1de" => DATA <= x"0839";
when "00" & x"1df" => DATA <= x"0007";
when "00" & x"1e0" => DATA <= x"fffe";
when "00" & x"1e1" => DATA <= x"0006";
when "00" & x"1e2" => DATA <= x"67ea";
when "00" & x"1e3" => DATA <= x"6100";
when "00" & x"1e4" => DATA <= x"00f0";
when "00" & x"1e5" => DATA <= x"60e4";
when "00" & x"1e6" => DATA <= x"1039";
when "00" & x"1e7" => DATA <= x"fffe";
when "00" & x"1e8" => DATA <= x"0001";
when "00" & x"1e9" => DATA <= x"4e75";
when "00" & x"1ea" => DATA <= x"0839";
when "00" & x"1eb" => DATA <= x"0007";
when "00" & x"1ec" => DATA <= x"fffe";
when "00" & x"1ed" => DATA <= x"0002";
when "00" & x"1ee" => DATA <= x"67f6";
when "00" & x"1ef" => DATA <= x"1039";
when "00" & x"1f0" => DATA <= x"fffe";
when "00" & x"1f1" => DATA <= x"0003";
when "00" & x"1f2" => DATA <= x"4e75";
when "00" & x"1f3" => DATA <= x"0839";
when "00" & x"1f4" => DATA <= x"0006";
when "00" & x"1f5" => DATA <= x"fffe";
when "00" & x"1f6" => DATA <= x"0002";
when "00" & x"1f7" => DATA <= x"67f6";
when "00" & x"1f8" => DATA <= x"13c0";
when "00" & x"1f9" => DATA <= x"fffe";
when "00" & x"1fa" => DATA <= x"0003";
when "00" & x"1fb" => DATA <= x"4e75";
when "00" & x"1fc" => DATA <= x"0839";
when "00" & x"1fd" => DATA <= x"0007";
when "00" & x"1fe" => DATA <= x"fffe";
when "00" & x"1ff" => DATA <= x"0006";
when "00" & x"200" => DATA <= x"67f6";
when "00" & x"201" => DATA <= x"1039";
when "00" & x"202" => DATA <= x"fffe";
when "00" & x"203" => DATA <= x"0007";
when "00" & x"204" => DATA <= x"4e75";
when "00" & x"205" => DATA <= x"4280";
when "00" & x"206" => DATA <= x"61c6";
when "00" & x"207" => DATA <= x"e198";
when "00" & x"208" => DATA <= x"61c2";
when "00" & x"209" => DATA <= x"e198";
when "00" & x"20a" => DATA <= x"61be";
when "00" & x"20b" => DATA <= x"e198";
when "00" & x"20c" => DATA <= x"60ba";
when "00" & x"20d" => DATA <= x"e198";
when "00" & x"20e" => DATA <= x"61c8";
when "00" & x"20f" => DATA <= x"e198";
when "00" & x"210" => DATA <= x"61c4";
when "00" & x"211" => DATA <= x"e198";
when "00" & x"212" => DATA <= x"61c0";
when "00" & x"213" => DATA <= x"e198";
when "00" & x"214" => DATA <= x"60bc";
when "00" & x"215" => DATA <= x"4280";
when "00" & x"216" => DATA <= x"61ca";
when "00" & x"217" => DATA <= x"e198";
when "00" & x"218" => DATA <= x"61c6";
when "00" & x"219" => DATA <= x"e198";
when "00" & x"21a" => DATA <= x"61c2";
when "00" & x"21b" => DATA <= x"e198";
when "00" & x"21c" => DATA <= x"60be";
when "00" & x"21d" => DATA <= x"0839";
when "00" & x"21e" => DATA <= x"0006";
when "00" & x"21f" => DATA <= x"fffe";
when "00" & x"220" => DATA <= x"0002";
when "00" & x"221" => DATA <= x"67f6";
when "00" & x"222" => DATA <= x"101e";
when "00" & x"223" => DATA <= x"619e";
when "00" & x"224" => DATA <= x"b03c";
when "00" & x"225" => DATA <= x"000d";
when "00" & x"226" => DATA <= x"66ec";
when "00" & x"227" => DATA <= x"4e75";
when "00" & x"228" => DATA <= x"0839";
when "00" & x"229" => DATA <= x"0007";
when "00" & x"22a" => DATA <= x"fffe";
when "00" & x"22b" => DATA <= x"0006";
when "00" & x"22c" => DATA <= x"6600";
when "00" & x"22d" => DATA <= x"005e";
when "00" & x"22e" => DATA <= x"0839";
when "00" & x"22f" => DATA <= x"0007";
when "00" & x"230" => DATA <= x"fffe";
when "00" & x"231" => DATA <= x"0000";
when "00" & x"232" => DATA <= x"6600";
when "00" & x"233" => DATA <= x"0010";
when "00" & x"234" => DATA <= x"2f0e";
when "00" & x"235" => DATA <= x"2c79";
when "00" & x"236" => DATA <= x"0000";
when "00" & x"237" => DATA <= x"0408";
when "00" & x"238" => DATA <= x"4e96";
when "00" & x"239" => DATA <= x"2c5f";
when "00" & x"23a" => DATA <= x"4e73";
when "00" & x"23b" => DATA <= x"2f00";
when "00" & x"23c" => DATA <= x"1039";
when "00" & x"23d" => DATA <= x"fffe";
when "00" & x"23e" => DATA <= x"0001";
when "00" & x"23f" => DATA <= x"6b00";
when "00" & x"240" => DATA <= x"0028";
when "00" & x"241" => DATA <= x"2f01";
when "00" & x"242" => DATA <= x"4280";
when "00" & x"243" => DATA <= x"6100";
when "00" & x"244" => DATA <= x"ff28";
when "00" & x"245" => DATA <= x"e158";
when "00" & x"246" => DATA <= x"6100";
when "00" & x"247" => DATA <= x"ff22";
when "00" & x"248" => DATA <= x"3200";
when "00" & x"249" => DATA <= x"6100";
when "00" & x"24a" => DATA <= x"ff1c";
when "00" & x"24b" => DATA <= x"2f0e";
when "00" & x"24c" => DATA <= x"2c79";
when "00" & x"24d" => DATA <= x"0000";
when "00" & x"24e" => DATA <= x"0440";
when "00" & x"24f" => DATA <= x"4e96";
when "00" & x"250" => DATA <= x"2c5f";
when "00" & x"251" => DATA <= x"221f";
when "00" & x"252" => DATA <= x"201f";
when "00" & x"253" => DATA <= x"4e73";
when "00" & x"254" => DATA <= x"2f0e";
when "00" & x"255" => DATA <= x"2c79";
when "00" & x"256" => DATA <= x"0000";
when "00" & x"257" => DATA <= x"04cc";
when "00" & x"258" => DATA <= x"4e96";
when "00" & x"259" => DATA <= x"2c5f";
when "00" & x"25a" => DATA <= x"201f";
when "00" & x"25b" => DATA <= x"4e73";
when "00" & x"25c" => DATA <= x"1039";
when "00" & x"25d" => DATA <= x"fffe";
when "00" & x"25e" => DATA <= x"0007";
when "00" & x"25f" => DATA <= x"6a00";
when "00" & x"260" => DATA <= x"003c";
when "00" & x"261" => DATA <= x"2f00";
when "00" & x"262" => DATA <= x"2f0e";
when "00" & x"263" => DATA <= x"2c7c";
when "00" & x"264" => DATA <= x"0000";
when "00" & x"265" => DATA <= x"0700";
when "00" & x"266" => DATA <= x"6100";
when "00" & x"267" => DATA <= x"ff06";
when "00" & x"268" => DATA <= x"4280";
when "00" & x"269" => DATA <= x"6100";
when "00" & x"26a" => DATA <= x"ff00";
when "00" & x"26b" => DATA <= x"2cc0";
when "00" & x"26c" => DATA <= x"6100";
when "00" & x"26d" => DATA <= x"fefa";
when "00" & x"26e" => DATA <= x"1cc0";
when "00" & x"26f" => DATA <= x"66f8";
when "00" & x"270" => DATA <= x"2c5f";
when "00" & x"271" => DATA <= x"203c";
when "00" & x"272" => DATA <= x"0000";
when "00" & x"273" => DATA <= x"0700";
when "00" & x"274" => DATA <= x"21c0";
when "00" & x"275" => DATA <= x"0514";
when "00" & x"276" => DATA <= x"21fc";
when "00" & x"277" => DATA <= x"ffff";
when "00" & x"278" => DATA <= x"6502";
when "00" & x"279" => DATA <= x"0510";
when "00" & x"27a" => DATA <= x"6100";
when "00" & x"27b" => DATA <= x"0c2e";
when "00" & x"27c" => DATA <= x"201f";
when "00" & x"27d" => DATA <= x"4e73";
when "00" & x"27e" => DATA <= x"2f08";
when "00" & x"27f" => DATA <= x"2f00";
when "00" & x"280" => DATA <= x"0280";
when "00" & x"281" => DATA <= x"0000";
when "00" & x"282" => DATA <= x"00ff";
when "00" & x"283" => DATA <= x"e588";
when "00" & x"284" => DATA <= x"41f9";
when "00" & x"285" => DATA <= x"003f";
when "00" & x"286" => DATA <= x"060a";
when "00" & x"287" => DATA <= x"d1c0";
when "00" & x"288" => DATA <= x"21d0";
when "00" & x"289" => DATA <= x"0074";
when "00" & x"28a" => DATA <= x"6100";
when "00" & x"28b" => DATA <= x"fee2";
when "00" & x"28c" => DATA <= x"2017";
when "00" & x"28d" => DATA <= x"b03c";
when "00" & x"28e" => DATA <= x"0005";
when "00" & x"28f" => DATA <= x"6700";
when "00" & x"290" => DATA <= x"005c";
when "00" & x"291" => DATA <= x"6100";
when "00" & x"292" => DATA <= x"ff06";
when "00" & x"293" => DATA <= x"23c0";
when "00" & x"294" => DATA <= x"0000";
when "00" & x"295" => DATA <= x"0520";
when "00" & x"296" => DATA <= x"1039";
when "00" & x"297" => DATA <= x"fffe";
when "00" & x"298" => DATA <= x"0005";
when "00" & x"299" => DATA <= x"1039";
when "00" & x"29a" => DATA <= x"fffe";
when "00" & x"29b" => DATA <= x"0005";
when "00" & x"29c" => DATA <= x"6100";
when "00" & x"29d" => DATA <= x"febe";
when "00" & x"29e" => DATA <= x"2017";
when "00" & x"29f" => DATA <= x"b03c";
when "00" & x"2a0" => DATA <= x"0006";
when "00" & x"2a1" => DATA <= x"6500";
when "00" & x"2a2" => DATA <= x"0038";
when "00" & x"2a3" => DATA <= x"6600";
when "00" & x"2a4" => DATA <= x"003a";
when "00" & x"2a5" => DATA <= x"2f0e";
when "00" & x"2a6" => DATA <= x"2c78";
when "00" & x"2a7" => DATA <= x"0520";
when "00" & x"2a8" => DATA <= x"203c";
when "00" & x"2a9" => DATA <= x"0000";
when "00" & x"2aa" => DATA <= x"00ff";
when "00" & x"2ab" => DATA <= x"0839";
when "00" & x"2ac" => DATA <= x"0007";
when "00" & x"2ad" => DATA <= x"fffe";
when "00" & x"2ae" => DATA <= x"0004";
when "00" & x"2af" => DATA <= x"67f6";
when "00" & x"2b0" => DATA <= x"13de";
when "00" & x"2b1" => DATA <= x"fffe";
when "00" & x"2b2" => DATA <= x"0005";
when "00" & x"2b3" => DATA <= x"51c8";
when "00" & x"2b4" => DATA <= x"ffee";
when "00" & x"2b5" => DATA <= x"0839";
when "00" & x"2b6" => DATA <= x"0007";
when "00" & x"2b7" => DATA <= x"fffe";
when "00" & x"2b8" => DATA <= x"0004";
when "00" & x"2b9" => DATA <= x"67f6";
when "00" & x"2ba" => DATA <= x"13e6";
when "00" & x"2bb" => DATA <= x"fffe";
when "00" & x"2bc" => DATA <= x"0005";
when "00" & x"2bd" => DATA <= x"2c5f";
when "00" & x"2be" => DATA <= x"201f";
when "00" & x"2bf" => DATA <= x"205f";
when "00" & x"2c0" => DATA <= x"4e73";
when "00" & x"2c1" => DATA <= x"2f0e";
when "00" & x"2c2" => DATA <= x"2c78";
when "00" & x"2c3" => DATA <= x"0520";
when "00" & x"2c4" => DATA <= x"203c";
when "00" & x"2c5" => DATA <= x"0000";
when "00" & x"2c6" => DATA <= x"00ff";
when "00" & x"2c7" => DATA <= x"0839";
when "00" & x"2c8" => DATA <= x"0007";
when "00" & x"2c9" => DATA <= x"fffe";
when "00" & x"2ca" => DATA <= x"0004";
when "00" & x"2cb" => DATA <= x"67f6";
when "00" & x"2cc" => DATA <= x"1cf9";
when "00" & x"2cd" => DATA <= x"fffe";
when "00" & x"2ce" => DATA <= x"0005";
when "00" & x"2cf" => DATA <= x"51c8";
when "00" & x"2d0" => DATA <= x"ffee";
when "00" & x"2d1" => DATA <= x"2c5f";
when "00" & x"2d2" => DATA <= x"60d6";
when "00" & x"2d3" => DATA <= x"2f0e";
when "00" & x"2d4" => DATA <= x"2c78";
when "00" & x"2d5" => DATA <= x"0520";
when "00" & x"2d6" => DATA <= x"13de";
when "00" & x"2d7" => DATA <= x"fffe";
when "00" & x"2d8" => DATA <= x"0005";
when "00" & x"2d9" => DATA <= x"21ce";
when "00" & x"2da" => DATA <= x"0520";
when "00" & x"2db" => DATA <= x"2c5f";
when "00" & x"2dc" => DATA <= x"4e73";
when "00" & x"2dd" => DATA <= x"2f0e";
when "00" & x"2de" => DATA <= x"2c78";
when "00" & x"2df" => DATA <= x"0520";
when "00" & x"2e0" => DATA <= x"1cf9";
when "00" & x"2e1" => DATA <= x"fffe";
when "00" & x"2e2" => DATA <= x"0005";
when "00" & x"2e3" => DATA <= x"21ce";
when "00" & x"2e4" => DATA <= x"0520";
when "00" & x"2e5" => DATA <= x"2c5f";
when "00" & x"2e6" => DATA <= x"4e73";
when "00" & x"2e7" => DATA <= x"2f0e";
when "00" & x"2e8" => DATA <= x"2c78";
when "00" & x"2e9" => DATA <= x"0520";
when "00" & x"2ea" => DATA <= x"13de";
when "00" & x"2eb" => DATA <= x"fffe";
when "00" & x"2ec" => DATA <= x"0005";
when "00" & x"2ed" => DATA <= x"13de";
when "00" & x"2ee" => DATA <= x"fffe";
when "00" & x"2ef" => DATA <= x"0005";
when "00" & x"2f0" => DATA <= x"21ce";
when "00" & x"2f1" => DATA <= x"0520";
when "00" & x"2f2" => DATA <= x"2c5f";
when "00" & x"2f3" => DATA <= x"4e73";
when "00" & x"2f4" => DATA <= x"2f0e";
when "00" & x"2f5" => DATA <= x"2c78";
when "00" & x"2f6" => DATA <= x"0520";
when "00" & x"2f7" => DATA <= x"1cf9";
when "00" & x"2f8" => DATA <= x"fffe";
when "00" & x"2f9" => DATA <= x"0005";
when "00" & x"2fa" => DATA <= x"1cf9";
when "00" & x"2fb" => DATA <= x"fffe";
when "00" & x"2fc" => DATA <= x"0005";
when "00" & x"2fd" => DATA <= x"21ce";
when "00" & x"2fe" => DATA <= x"0520";
when "00" & x"2ff" => DATA <= x"2c5f";
when "00" & x"300" => DATA <= x"4e73";
when "00" & x"301" => DATA <= x"13c0";
when "00" & x"302" => DATA <= x"fffe";
when "00" & x"303" => DATA <= x"0005";
when "00" & x"304" => DATA <= x"4e73";
when "00" & x"305" => DATA <= x"003f";
when "00" & x"306" => DATA <= x"05a6";
when "00" & x"307" => DATA <= x"003f";
when "00" & x"308" => DATA <= x"05ba";
when "00" & x"309" => DATA <= x"003f";
when "00" & x"30a" => DATA <= x"05ce";
when "00" & x"30b" => DATA <= x"003f";
when "00" & x"30c" => DATA <= x"05e8";
when "00" & x"30d" => DATA <= x"003f";
when "00" & x"30e" => DATA <= x"0602";
when "00" & x"30f" => DATA <= x"003f";
when "00" & x"310" => DATA <= x"0602";
when "00" & x"311" => DATA <= x"003f";
when "00" & x"312" => DATA <= x"0602";
when "00" & x"313" => DATA <= x"003f";
when "00" & x"314" => DATA <= x"0602";
when "00" & x"315" => DATA <= x"203c";
when "00" & x"316" => DATA <= x"003f";
when "00" & x"317" => DATA <= x"2c4d";
when "00" & x"318" => DATA <= x"6100";
when "00" & x"319" => DATA <= x"03d0";
when "00" & x"31a" => DATA <= x"31df";
when "00" & x"31b" => DATA <= x"0544";
when "00" & x"31c" => DATA <= x"21df";
when "00" & x"31d" => DATA <= x"0540";
when "00" & x"31e" => DATA <= x"31df";
when "00" & x"31f" => DATA <= x"053e";
when "00" & x"320" => DATA <= x"31df";
when "00" & x"321" => DATA <= x"053c";
when "00" & x"322" => DATA <= x"21d7";
when "00" & x"323" => DATA <= x"0538";
when "00" & x"324" => DATA <= x"223c";
when "00" & x"325" => DATA <= x"0000";
when "00" & x"326" => DATA <= x"0600";
when "00" & x"327" => DATA <= x"143c";
when "00" & x"328" => DATA <= x"00ff";
when "00" & x"329" => DATA <= x"7000";
when "00" & x"32a" => DATA <= x"2038";
when "00" & x"32b" => DATA <= x"0538";
when "00" & x"32c" => DATA <= x"6100";
when "00" & x"32d" => DATA <= x"1090";
when "00" & x"32e" => DATA <= x"6100";
when "00" & x"32f" => DATA <= x"03a4";
when "00" & x"330" => DATA <= x"6100";
when "00" & x"331" => DATA <= x"03b4";
when "00" & x"332" => DATA <= x"203c";
when "00" & x"333" => DATA <= x"003f";
when "00" & x"334" => DATA <= x"2c7d";
when "00" & x"335" => DATA <= x"6100";
when "00" & x"336" => DATA <= x"0396";
when "00" & x"337" => DATA <= x"223c";
when "00" & x"338" => DATA <= x"0000";
when "00" & x"339" => DATA <= x"0600";
when "00" & x"33a" => DATA <= x"143c";
when "00" & x"33b" => DATA <= x"00ff";
when "00" & x"33c" => DATA <= x"7000";
when "00" & x"33d" => DATA <= x"3038";
when "00" & x"33e" => DATA <= x"0544";
when "00" & x"33f" => DATA <= x"6100";
when "00" & x"340" => DATA <= x"1030";
when "00" & x"341" => DATA <= x"6100";
when "00" & x"342" => DATA <= x"037e";
when "00" & x"343" => DATA <= x"6100";
when "00" & x"344" => DATA <= x"038e";
when "00" & x"345" => DATA <= x"203c";
when "00" & x"346" => DATA <= x"003f";
when "00" & x"347" => DATA <= x"2c94";
when "00" & x"348" => DATA <= x"6100";
when "00" & x"349" => DATA <= x"0370";
when "00" & x"34a" => DATA <= x"223c";
when "00" & x"34b" => DATA <= x"0000";
when "00" & x"34c" => DATA <= x"0600";
when "00" & x"34d" => DATA <= x"143c";
when "00" & x"34e" => DATA <= x"00ff";
when "00" & x"34f" => DATA <= x"7000";
when "00" & x"350" => DATA <= x"2038";
when "00" & x"351" => DATA <= x"0540";
when "00" & x"352" => DATA <= x"6100";
when "00" & x"353" => DATA <= x"1044";
when "00" & x"354" => DATA <= x"6100";
when "00" & x"355" => DATA <= x"0358";
when "00" & x"356" => DATA <= x"6100";
when "00" & x"357" => DATA <= x"0368";
when "00" & x"358" => DATA <= x"203c";
when "00" & x"359" => DATA <= x"003f";
when "00" & x"35a" => DATA <= x"2cab";
when "00" & x"35b" => DATA <= x"6100";
when "00" & x"35c" => DATA <= x"034a";
when "00" & x"35d" => DATA <= x"223c";
when "00" & x"35e" => DATA <= x"0000";
when "00" & x"35f" => DATA <= x"0600";
when "00" & x"360" => DATA <= x"143c";
when "00" & x"361" => DATA <= x"00ff";
when "00" & x"362" => DATA <= x"7000";
when "00" & x"363" => DATA <= x"3038";
when "00" & x"364" => DATA <= x"053e";
when "00" & x"365" => DATA <= x"6100";
when "00" & x"366" => DATA <= x"0fe4";
when "00" & x"367" => DATA <= x"6100";
when "00" & x"368" => DATA <= x"0332";
when "00" & x"369" => DATA <= x"103c";
when "00" & x"36a" => DATA <= x"0020";
when "00" & x"36b" => DATA <= x"6100";
when "00" & x"36c" => DATA <= x"0312";
when "00" & x"36d" => DATA <= x"103c";
when "00" & x"36e" => DATA <= x"005b";
when "00" & x"36f" => DATA <= x"6100";
when "00" & x"370" => DATA <= x"030a";
when "00" & x"371" => DATA <= x"303c";
when "00" & x"372" => DATA <= x"053e";
when "00" & x"373" => DATA <= x"223c";
when "00" & x"374" => DATA <= x"0000";
when "00" & x"375" => DATA <= x"0600";
when "00" & x"376" => DATA <= x"6100";
when "00" & x"377" => DATA <= x"1422";
when "00" & x"378" => DATA <= x"2001";
when "00" & x"379" => DATA <= x"6100";
when "00" & x"37a" => DATA <= x"030e";
when "00" & x"37b" => DATA <= x"103c";
when "00" & x"37c" => DATA <= x"005d";
when "00" & x"37d" => DATA <= x"6100";
when "00" & x"37e" => DATA <= x"02ee";
when "00" & x"37f" => DATA <= x"6100";
when "00" & x"380" => DATA <= x"0316";
when "00" & x"381" => DATA <= x"203c";
when "00" & x"382" => DATA <= x"003f";
when "00" & x"383" => DATA <= x"2cc2";
when "00" & x"384" => DATA <= x"6100";
when "00" & x"385" => DATA <= x"02f8";
when "00" & x"386" => DATA <= x"223c";
when "00" & x"387" => DATA <= x"0000";
when "00" & x"388" => DATA <= x"0600";
when "00" & x"389" => DATA <= x"143c";
when "00" & x"38a" => DATA <= x"00ff";
when "00" & x"38b" => DATA <= x"7000";
when "00" & x"38c" => DATA <= x"3038";
when "00" & x"38d" => DATA <= x"053c";
when "00" & x"38e" => DATA <= x"6100";
when "00" & x"38f" => DATA <= x"120e";
when "00" & x"390" => DATA <= x"6100";
when "00" & x"391" => DATA <= x"02e0";
when "00" & x"392" => DATA <= x"6100";
when "00" & x"393" => DATA <= x"02f0";
when "00" & x"394" => DATA <= x"60fe";
when "00" & x"395" => DATA <= x"6100";
when "00" & x"396" => DATA <= x"02f8";
when "00" & x"397" => DATA <= x"6000";
when "00" & x"398" => DATA <= x"fc32";
when "00" & x"399" => DATA <= x"203c";
when "00" & x"39a" => DATA <= x"003f";
when "00" & x"39b" => DATA <= x"2c5e";
when "00" & x"39c" => DATA <= x"6100";
when "00" & x"39d" => DATA <= x"02c8";
when "00" & x"39e" => DATA <= x"6000";
when "00" & x"39f" => DATA <= x"fef6";
when "00" & x"3a0" => DATA <= x"2f00";
when "00" & x"3a1" => DATA <= x"203c";
when "00" & x"3a2" => DATA <= x"003f";
when "00" & x"3a3" => DATA <= x"2d04";
when "00" & x"3a4" => DATA <= x"6000";
when "00" & x"3a5" => DATA <= x"0022";
when "00" & x"3a6" => DATA <= x"2f00";
when "00" & x"3a7" => DATA <= x"203c";
when "00" & x"3a8" => DATA <= x"003f";
when "00" & x"3a9" => DATA <= x"2d34";
when "00" & x"3aa" => DATA <= x"6000";
when "00" & x"3ab" => DATA <= x"0016";
when "00" & x"3ac" => DATA <= x"2f00";
when "00" & x"3ad" => DATA <= x"203c";
when "00" & x"3ae" => DATA <= x"003f";
when "00" & x"3af" => DATA <= x"2d50";
when "00" & x"3b0" => DATA <= x"6000";
when "00" & x"3b1" => DATA <= x"000a";
when "00" & x"3b2" => DATA <= x"2f00";
when "00" & x"3b3" => DATA <= x"203c";
when "00" & x"3b4" => DATA <= x"003f";
when "00" & x"3b5" => DATA <= x"2dc0";
when "00" & x"3b6" => DATA <= x"21ef";
when "00" & x"3b7" => DATA <= x"0006";
when "00" & x"3b8" => DATA <= x"0510";
when "00" & x"3b9" => DATA <= x"6100";
when "00" & x"3ba" => DATA <= x"09b0";
when "00" & x"3bb" => DATA <= x"201f";
when "00" & x"3bc" => DATA <= x"4e73";
when "00" & x"3bd" => DATA <= x"203c";
when "00" & x"3be" => DATA <= x"003f";
when "00" & x"3bf" => DATA <= x"2dd8";
when "00" & x"3c0" => DATA <= x"207c";
when "00" & x"3c1" => DATA <= x"0000";
when "00" & x"3c2" => DATA <= x"002b";
when "00" & x"3c3" => DATA <= x"4e4c";
when "00" & x"3c4" => DATA <= x"4e75";
when "00" & x"3c5" => DATA <= x"7000";
when "00" & x"3c6" => DATA <= x"2a40";
when "00" & x"3c7" => DATA <= x"206d";
when "00" & x"3c8" => DATA <= x"000c";
when "00" & x"3c9" => DATA <= x"43fa";
when "00" & x"3ca" => DATA <= x"000e";
when "00" & x"3cb" => DATA <= x"2b49";
when "00" & x"3cc" => DATA <= x"000c";
when "00" & x"3cd" => DATA <= x"2e0f";
when "00" & x"3ce" => DATA <= x"2c07";
when "00" & x"3cf" => DATA <= x"4efa";
when "00" & x"3d0" => DATA <= x"0003";
when "00" & x"3d1" => DATA <= x"2b48";
when "00" & x"3d2" => DATA <= x"000c";
when "00" & x"3d3" => DATA <= x"9e8f";
when "00" & x"3d4" => DATA <= x"7001";
when "00" & x"3d5" => DATA <= x"0c07";
when "00" & x"3d6" => DATA <= x"0012";
when "00" & x"3d7" => DATA <= x"6754";
when "00" & x"3d8" => DATA <= x"7002";
when "00" & x"3d9" => DATA <= x"0c07";
when "00" & x"3da" => DATA <= x"003e";
when "00" & x"3db" => DATA <= x"674c";
when "00" & x"3dc" => DATA <= x"7007";
when "00" & x"3dd" => DATA <= x"0c07";
when "00" & x"3de" => DATA <= x"0026";
when "00" & x"3df" => DATA <= x"6744";
when "00" & x"3e0" => DATA <= x"7008";
when "00" & x"3e1" => DATA <= x"0c07";
when "00" & x"3e2" => DATA <= x"001c";
when "00" & x"3e3" => DATA <= x"673c";
when "00" & x"3e4" => DATA <= x"7005";
when "00" & x"3e5" => DATA <= x"0c07";
when "00" & x"3e6" => DATA <= x"0010";
when "00" & x"3e7" => DATA <= x"6734";
when "00" & x"3e8" => DATA <= x"70ff";
when "00" & x"3e9" => DATA <= x"0c07";
when "00" & x"3ea" => DATA <= x"0024";
when "00" & x"3eb" => DATA <= x"662c";
when "00" & x"3ec" => DATA <= x"206d";
when "00" & x"3ed" => DATA <= x"001a";
when "00" & x"3ee" => DATA <= x"226d";
when "00" & x"3ef" => DATA <= x"007e";
when "00" & x"3f0" => DATA <= x"45fa";
when "00" & x"3f1" => DATA <= x"001a";
when "00" & x"3f2" => DATA <= x"2b4a";
when "00" & x"3f3" => DATA <= x"007e";
when "00" & x"3f4" => DATA <= x"45fa";
when "00" & x"3f5" => DATA <= x"0010";
when "00" & x"3f6" => DATA <= x"2b4a";
when "00" & x"3f7" => DATA <= x"001a";
when "00" & x"3f8" => DATA <= x"7003";
when "00" & x"3f9" => DATA <= x"06fa";
when "00" & x"3fa" => DATA <= x"0000";
when "00" & x"3fb" => DATA <= x"0002";
when "00" & x"3fc" => DATA <= x"ffff";
when "00" & x"3fd" => DATA <= x"7004";
when "00" & x"3fe" => DATA <= x"2b49";
when "00" & x"3ff" => DATA <= x"007e";
when "00" & x"400" => DATA <= x"2b48";
when "00" & x"401" => DATA <= x"001a";
when "00" & x"402" => DATA <= x"2e46";
when "00" & x"403" => DATA <= x"4e75";
when "00" & x"404" => DATA <= x"7000";
when "00" & x"405" => DATA <= x"2a40";
when "00" & x"406" => DATA <= x"206d";
when "00" & x"407" => DATA <= x"002c";
when "00" & x"408" => DATA <= x"43fa";
when "00" & x"409" => DATA <= x"000e";
when "00" & x"40a" => DATA <= x"2b49";
when "00" & x"40b" => DATA <= x"002c";
when "00" & x"40c" => DATA <= x"2e0f";
when "00" & x"40d" => DATA <= x"70ff";
when "00" & x"40e" => DATA <= x"6000";
when "00" & x"40f" => DATA <= x"0004";
when "00" & x"410" => DATA <= x"7000";
when "00" & x"411" => DATA <= x"2e47";
when "00" & x"412" => DATA <= x"2b48";
when "00" & x"413" => DATA <= x"002c";
when "00" & x"414" => DATA <= x"4e75";
when "00" & x"415" => DATA <= x"7000";
when "00" & x"416" => DATA <= x"4e75";
when "00" & x"417" => DATA <= x"13fc";
when "00" & x"418" => DATA <= x"00f0";
when "00" & x"419" => DATA <= x"003f";
when "00" & x"41a" => DATA <= x"0000";
when "00" & x"41b" => DATA <= x"13fc";
when "00" & x"41c" => DATA <= x"00ff";
when "00" & x"41d" => DATA <= x"003f";
when "00" & x"41e" => DATA <= x"0000";
when "00" & x"41f" => DATA <= x"4e75";
when "00" & x"420" => DATA <= x"13fc";
when "00" & x"421" => DATA <= x"00aa";
when "00" & x"422" => DATA <= x"003f";
when "00" & x"423" => DATA <= x"5555";
when "00" & x"424" => DATA <= x"13fc";
when "00" & x"425" => DATA <= x"0055";
when "00" & x"426" => DATA <= x"003f";
when "00" & x"427" => DATA <= x"aaaa";
when "00" & x"428" => DATA <= x"13fc";
when "00" & x"429" => DATA <= x"0090";
when "00" & x"42a" => DATA <= x"003f";
when "00" & x"42b" => DATA <= x"5555";
when "00" & x"42c" => DATA <= x"13c0";
when "00" & x"42d" => DATA <= x"003f";
when "00" & x"42e" => DATA <= x"0000";
when "00" & x"42f" => DATA <= x"e140";
when "00" & x"430" => DATA <= x"61cc";
when "00" & x"431" => DATA <= x"13fc";
when "00" & x"432" => DATA <= x"00aa";
when "00" & x"433" => DATA <= x"003f";
when "00" & x"434" => DATA <= x"5555";
when "00" & x"435" => DATA <= x"13fc";
when "00" & x"436" => DATA <= x"0055";
when "00" & x"437" => DATA <= x"003f";
when "00" & x"438" => DATA <= x"aaaa";
when "00" & x"439" => DATA <= x"13fc";
when "00" & x"43a" => DATA <= x"0090";
when "00" & x"43b" => DATA <= x"003f";
when "00" & x"43c" => DATA <= x"5555";
when "00" & x"43d" => DATA <= x"13c0";
when "00" & x"43e" => DATA <= x"003f";
when "00" & x"43f" => DATA <= x"0001";
when "00" & x"440" => DATA <= x"61ac";
when "00" & x"441" => DATA <= x"4e75";
when "00" & x"442" => DATA <= x"be3c";
when "00" & x"443" => DATA <= x"0008";
when "00" & x"444" => DATA <= x"6400";
when "00" & x"445" => DATA <= x"0012";
when "00" & x"446" => DATA <= x"e147";
when "00" & x"447" => DATA <= x"e147";
when "00" & x"448" => DATA <= x"223c";
when "00" & x"449" => DATA <= x"0000";
when "00" & x"44a" => DATA <= x"ffff";
when "00" & x"44b" => DATA <= x"1015";
when "00" & x"44c" => DATA <= x"6100";
when "00" & x"44d" => DATA <= x"0004";
when "00" & x"44e" => DATA <= x"4e75";
when "00" & x"44f" => DATA <= x"b016";
when "00" & x"450" => DATA <= x"6700";
when "00" & x"451" => DATA <= x"0026";
when "00" & x"452" => DATA <= x"13fc";
when "00" & x"453" => DATA <= x"00aa";
when "00" & x"454" => DATA <= x"003f";
when "00" & x"455" => DATA <= x"5555";
when "00" & x"456" => DATA <= x"13fc";
when "00" & x"457" => DATA <= x"0055";
when "00" & x"458" => DATA <= x"003f";
when "00" & x"459" => DATA <= x"aaaa";
when "00" & x"45a" => DATA <= x"13fc";
when "00" & x"45b" => DATA <= x"00a0";
when "00" & x"45c" => DATA <= x"003f";
when "00" & x"45d" => DATA <= x"5555";
when "00" & x"45e" => DATA <= x"1016";
when "00" & x"45f" => DATA <= x"0c16";
when "00" & x"460" => DATA <= x"0002";
when "00" & x"461" => DATA <= x"66fa";
when "00" & x"462" => DATA <= x"6100";
when "00" & x"463" => DATA <= x"ff68";
when "00" & x"464" => DATA <= x"4e75";
when "00" & x"465" => DATA <= x"2f08";
when "00" & x"466" => DATA <= x"2f38";
when "00" & x"467" => DATA <= x"0000";
when "00" & x"468" => DATA <= x"207c";
when "00" & x"469" => DATA <= x"0000";
when "00" & x"46a" => DATA <= x"0000";
when "00" & x"46b" => DATA <= x"21fc";
when "00" & x"46c" => DATA <= x"dead";
when "00" & x"46d" => DATA <= x"beef";
when "00" & x"46e" => DATA <= x"0000";
when "00" & x"46f" => DATA <= x"d1fc";
when "00" & x"470" => DATA <= x"0000";
when "00" & x"471" => DATA <= x"0400";
when "00" & x"472" => DATA <= x"0c90";
when "00" & x"473" => DATA <= x"dead";
when "00" & x"474" => DATA <= x"beef";
when "00" & x"475" => DATA <= x"6700";
when "00" & x"476" => DATA <= x"000a";
when "00" & x"477" => DATA <= x"b1fc";
when "00" & x"478" => DATA <= x"0030";
when "00" & x"479" => DATA <= x"0000";
when "00" & x"47a" => DATA <= x"65e8";
when "00" & x"47b" => DATA <= x"2008";
when "00" & x"47c" => DATA <= x"21df";
when "00" & x"47d" => DATA <= x"0000";
when "00" & x"47e" => DATA <= x"205f";
when "00" & x"47f" => DATA <= x"4e75";
when "00" & x"480" => DATA <= x"2f0e";
when "00" & x"481" => DATA <= x"2f09";
when "00" & x"482" => DATA <= x"2f08";
when "00" & x"483" => DATA <= x"2f01";
when "00" & x"484" => DATA <= x"c188";
when "00" & x"485" => DATA <= x"0280";
when "00" & x"486" => DATA <= x"00fd";
when "00" & x"487" => DATA <= x"ffff";
when "00" & x"488" => DATA <= x"43f9";
when "00" & x"489" => DATA <= x"003f";
when "00" & x"48a" => DATA <= x"2f54";
when "00" & x"48b" => DATA <= x"b099";
when "00" & x"48c" => DATA <= x"6700";
when "00" & x"48d" => DATA <= x"0014";
when "00" & x"48e" => DATA <= x"2219";
when "00" & x"48f" => DATA <= x"b23c";
when "00" & x"490" => DATA <= x"00ff";
when "00" & x"491" => DATA <= x"6700";
when "00" & x"492" => DATA <= x"0082";
when "00" & x"493" => DATA <= x"b23c";
when "00" & x"494" => DATA <= x"0000";
when "00" & x"495" => DATA <= x"66f0";
when "00" & x"496" => DATA <= x"60e8";
when "00" & x"497" => DATA <= x"2c59";
when "00" & x"498" => DATA <= x"c188";
when "00" & x"499" => DATA <= x"bdfc";
when "00" & x"49a" => DATA <= x"0000";
when "00" & x"49b" => DATA <= x"0504";
when "00" & x"49c" => DATA <= x"6400";
when "00" & x"49d" => DATA <= x"0004";
when "00" & x"49e" => DATA <= x"2c56";
when "00" & x"49f" => DATA <= x"221f";
when "00" & x"4a0" => DATA <= x"205f";
when "00" & x"4a1" => DATA <= x"225f";
when "00" & x"4a2" => DATA <= x"4e96";
when "00" & x"4a3" => DATA <= x"6900";
when "00" & x"4a4" => DATA <= x"001a";
when "00" & x"4a5" => DATA <= x"6500";
when "00" & x"4a6" => DATA <= x"000a";
when "00" & x"4a7" => DATA <= x"2c5f";
when "00" & x"4a8" => DATA <= x"0257";
when "00" & x"4a9" => DATA <= x"fffc";
when "00" & x"4aa" => DATA <= x"4e73";
when "00" & x"4ab" => DATA <= x"2c5f";
when "00" & x"4ac" => DATA <= x"0257";
when "00" & x"4ad" => DATA <= x"fffd";
when "00" & x"4ae" => DATA <= x"0057";
when "00" & x"4af" => DATA <= x"0001";
when "00" & x"4b0" => DATA <= x"4e73";
when "00" & x"4b1" => DATA <= x"6500";
when "00" & x"4b2" => DATA <= x"000e";
when "00" & x"4b3" => DATA <= x"0057";
when "00" & x"4b4" => DATA <= x"0002";
when "00" & x"4b5" => DATA <= x"0257";
when "00" & x"4b6" => DATA <= x"fffe";
when "00" & x"4b7" => DATA <= x"6000";
when "00" & x"4b8" => DATA <= x"0006";
when "00" & x"4b9" => DATA <= x"0057";
when "00" & x"4ba" => DATA <= x"0003";
when "00" & x"4bb" => DATA <= x"2c5f";
when "00" & x"4bc" => DATA <= x"c188";
when "00" & x"4bd" => DATA <= x"0800";
when "00" & x"4be" => DATA <= x"0011";
when "00" & x"4bf" => DATA <= x"6700";
when "00" & x"4c0" => DATA <= x"0006";
when "00" & x"4c1" => DATA <= x"c188";
when "00" & x"4c2" => DATA <= x"4e73";
when "00" & x"4c3" => DATA <= x"c188";
when "00" & x"4c4" => DATA <= x"2f01";
when "00" & x"4c5" => DATA <= x"7206";
when "00" & x"4c6" => DATA <= x"6100";
when "00" & x"4c7" => DATA <= x"07c6";
when "00" & x"4c8" => DATA <= x"221f";
when "00" & x"4c9" => DATA <= x"21c0";
when "00" & x"4ca" => DATA <= x"0514";
when "00" & x"4cb" => DATA <= x"21ef";
when "00" & x"4cc" => DATA <= x"0002";
when "00" & x"4cd" => DATA <= x"0510";
when "00" & x"4ce" => DATA <= x"2f79";
when "00" & x"4cf" => DATA <= x"0000";
when "00" & x"4d0" => DATA <= x"0404";
when "00" & x"4d1" => DATA <= x"0002";
when "00" & x"4d2" => DATA <= x"4e73";
when "00" & x"4d3" => DATA <= x"221f";
when "00" & x"4d4" => DATA <= x"205f";
when "00" & x"4d5" => DATA <= x"225f";
when "00" & x"4d6" => DATA <= x"2040";
when "00" & x"4d7" => DATA <= x"c0bc";
when "00" & x"4d8" => DATA <= x"00fd";
when "00" & x"4d9" => DATA <= x"ff00";
when "00" & x"4da" => DATA <= x"b0bc";
when "00" & x"4db" => DATA <= x"0000";
when "00" & x"4dc" => DATA <= x"0100";
when "00" & x"4dd" => DATA <= x"6600";
when "00" & x"4de" => DATA <= x"0012";
when "00" & x"4df" => DATA <= x"2008";
when "00" & x"4e0" => DATA <= x"4eb9";
when "00" & x"4e1" => DATA <= x"003f";
when "00" & x"4e2" => DATA <= x"09e4";
when "00" & x"4e3" => DATA <= x"2c5f";
when "00" & x"4e4" => DATA <= x"0257";
when "00" & x"4e5" => DATA <= x"fffc";
when "00" & x"4e6" => DATA <= x"4e73";
when "00" & x"4e7" => DATA <= x"2008";
when "00" & x"4e8" => DATA <= x"2c78";
when "00" & x"4e9" => DATA <= x"0460";
when "00" & x"4ea" => DATA <= x"21ef";
when "00" & x"4eb" => DATA <= x"0006";
when "00" & x"4ec" => DATA <= x"0510";
when "00" & x"4ed" => DATA <= x"4e96";
when "00" & x"4ee" => DATA <= x"2c5f";
when "00" & x"4ef" => DATA <= x"0057";
when "00" & x"4f0" => DATA <= x"0002";
when "00" & x"4f1" => DATA <= x"4e73";
when "00" & x"4f2" => DATA <= x"201f";
when "00" & x"4f3" => DATA <= x"6000";
when "00" & x"4f4" => DATA <= x"0002";
when "00" & x"4f5" => DATA <= x"2f38";
when "00" & x"4f6" => DATA <= x"040c";
when "00" & x"4f7" => DATA <= x"4e75";
when "00" & x"4f8" => DATA <= x"2f00";
when "00" & x"4f9" => DATA <= x"202f";
when "00" & x"4fa" => DATA <= x"0004";
when "00" & x"4fb" => DATA <= x"6100";
when "00" & x"4fc" => DATA <= x"000a";
when "00" & x"4fd" => DATA <= x"2f40";
when "00" & x"4fe" => DATA <= x"0004";
when "00" & x"4ff" => DATA <= x"201f";
when "00" & x"500" => DATA <= x"4e75";
when "00" & x"501" => DATA <= x"2f08";
when "00" & x"502" => DATA <= x"2040";
when "00" & x"503" => DATA <= x"1018";
when "00" & x"504" => DATA <= x"6700";
when "00" & x"505" => DATA <= x"0006";
when "00" & x"506" => DATA <= x"61dc";
when "00" & x"507" => DATA <= x"60f6";
when "00" & x"508" => DATA <= x"2008";
when "00" & x"509" => DATA <= x"205f";
when "00" & x"50a" => DATA <= x"4e75";
when "00" & x"50b" => DATA <= x"2f00";
when "00" & x"50c" => DATA <= x"700a";
when "00" & x"50d" => DATA <= x"61ce";
when "00" & x"50e" => DATA <= x"700d";
when "00" & x"50f" => DATA <= x"61ca";
when "00" & x"510" => DATA <= x"201f";
when "00" & x"511" => DATA <= x"4e75";
when "00" & x"512" => DATA <= x"7000";
when "00" & x"513" => DATA <= x"6100";
when "00" & x"514" => DATA <= x"f9be";
when "00" & x"515" => DATA <= x"6100";
when "00" & x"516" => DATA <= x"f9a8";
when "00" & x"517" => DATA <= x"e000";
when "00" & x"518" => DATA <= x"6000";
when "00" & x"519" => DATA <= x"f9a2";
when "00" & x"51a" => DATA <= x"2f0e";
when "00" & x"51b" => DATA <= x"2f00";
when "00" & x"51c" => DATA <= x"2c40";
when "00" & x"51d" => DATA <= x"6100";
when "00" & x"51e" => DATA <= x"1ce8";
when "00" & x"51f" => DATA <= x"101e";
when "00" & x"520" => DATA <= x"b03c";
when "00" & x"521" => DATA <= x"002a";
when "00" & x"522" => DATA <= x"67f4";
when "00" & x"523" => DATA <= x"1026";
when "00" & x"524" => DATA <= x"43f9";
when "00" & x"525" => DATA <= x"003f";
when "00" & x"526" => DATA <= x"35d0";
when "00" & x"527" => DATA <= x"2f0e";
when "00" & x"528" => DATA <= x"2459";
when "00" & x"529" => DATA <= x"b4fc";
when "00" & x"52a" => DATA <= x"ffff";
when "00" & x"52b" => DATA <= x"6700";
when "00" & x"52c" => DATA <= x"0050";
when "00" & x"52d" => DATA <= x"101e";
when "00" & x"52e" => DATA <= x"0200";
when "00" & x"52f" => DATA <= x"00df";
when "00" & x"530" => DATA <= x"b019";
when "00" & x"531" => DATA <= x"6600";
when "00" & x"532" => DATA <= x"003a";
when "00" & x"533" => DATA <= x"0c16";
when "00" & x"534" => DATA <= x"002e";
when "00" & x"535" => DATA <= x"6700";
when "00" & x"536" => DATA <= x"0010";
when "00" & x"537" => DATA <= x"0c11";
when "00" & x"538" => DATA <= x"0020";
when "00" & x"539" => DATA <= x"6700";
when "00" & x"53a" => DATA <= x"0008";
when "00" & x"53b" => DATA <= x"0c11";
when "00" & x"53c" => DATA <= x"0000";
when "00" & x"53d" => DATA <= x"66de";
when "00" & x"53e" => DATA <= x"0c16";
when "00" & x"53f" => DATA <= x"000d";
when "00" & x"540" => DATA <= x"6700";
when "00" & x"541" => DATA <= x"000a";
when "00" & x"542" => DATA <= x"0c16";
when "00" & x"543" => DATA <= x"0020";
when "00" & x"544" => DATA <= x"6600";
when "00" & x"545" => DATA <= x"0014";
when "00" & x"546" => DATA <= x"6100";
when "00" & x"547" => DATA <= x"1c96";
when "00" & x"548" => DATA <= x"225f";
when "00" & x"549" => DATA <= x"4e92";
when "00" & x"54a" => DATA <= x"201f";
when "00" & x"54b" => DATA <= x"2c5f";
when "00" & x"54c" => DATA <= x"6500";
when "00" & x"54d" => DATA <= x"0012";
when "00" & x"54e" => DATA <= x"4e75";
when "00" & x"54f" => DATA <= x"0c19";
when "00" & x"550" => DATA <= x"0000";
when "00" & x"551" => DATA <= x"66fa";
when "00" & x"552" => DATA <= x"2c5f";
when "00" & x"553" => DATA <= x"60a6";
when "00" & x"554" => DATA <= x"2c5f";
when "00" & x"555" => DATA <= x"201f";
when "00" & x"556" => DATA <= x"2f01";
when "00" & x"557" => DATA <= x"7204";
when "00" & x"558" => DATA <= x"6100";
when "00" & x"559" => DATA <= x"06a2";
when "00" & x"55a" => DATA <= x"221f";
when "00" & x"55b" => DATA <= x"2c40";
when "00" & x"55c" => DATA <= x"7002";
when "00" & x"55d" => DATA <= x"6100";
when "00" & x"55e" => DATA <= x"f92a";
when "00" & x"55f" => DATA <= x"6100";
when "00" & x"560" => DATA <= x"f97a";
when "00" & x"561" => DATA <= x"6100";
when "00" & x"562" => DATA <= x"f910";
when "00" & x"563" => DATA <= x"2c5f";
when "00" & x"564" => DATA <= x"b03c";
when "00" & x"565" => DATA <= x"0080";
when "00" & x"566" => DATA <= x"6700";
when "00" & x"567" => DATA <= x"00b6";
when "00" & x"568" => DATA <= x"023c";
when "00" & x"569" => DATA <= x"00fd";
when "00" & x"56a" => DATA <= x"4e75";
when "00" & x"56b" => DATA <= x"b03c";
when "00" & x"56c" => DATA <= x"0080";
when "00" & x"56d" => DATA <= x"6400";
when "00" & x"56e" => DATA <= x"002a";
when "00" & x"56f" => DATA <= x"b03c";
when "00" & x"570" => DATA <= x"007e";
when "00" & x"571" => DATA <= x"6600";
when "00" & x"572" => DATA <= x"0002";
when "00" & x"573" => DATA <= x"2f00";
when "00" & x"574" => DATA <= x"103c";
when "00" & x"575" => DATA <= x"0004";
when "00" & x"576" => DATA <= x"6100";
when "00" & x"577" => DATA <= x"f8f8";
when "00" & x"578" => DATA <= x"1001";
when "00" & x"579" => DATA <= x"6100";
when "00" & x"57a" => DATA <= x"f8f2";
when "00" & x"57b" => DATA <= x"2017";
when "00" & x"57c" => DATA <= x"6100";
when "00" & x"57d" => DATA <= x"f8ec";
when "00" & x"57e" => DATA <= x"6100";
when "00" & x"57f" => DATA <= x"f8d6";
when "00" & x"580" => DATA <= x"1200";
when "00" & x"581" => DATA <= x"201f";
when "00" & x"582" => DATA <= x"4e75";
when "00" & x"583" => DATA <= x"b03c";
when "00" & x"584" => DATA <= x"0082";
when "00" & x"585" => DATA <= x"6700";
when "00" & x"586" => DATA <= x"005a";
when "00" & x"587" => DATA <= x"b03c";
when "00" & x"588" => DATA <= x"0083";
when "00" & x"589" => DATA <= x"6700";
when "00" & x"58a" => DATA <= x"005c";
when "00" & x"58b" => DATA <= x"b03c";
when "00" & x"58c" => DATA <= x"0084";
when "00" & x"58d" => DATA <= x"6700";
when "00" & x"58e" => DATA <= x"005e";
when "00" & x"58f" => DATA <= x"2f00";
when "00" & x"590" => DATA <= x"103c";
when "00" & x"591" => DATA <= x"0006";
when "00" & x"592" => DATA <= x"6100";
when "00" & x"593" => DATA <= x"f8c0";
when "00" & x"594" => DATA <= x"1001";
when "00" & x"595" => DATA <= x"6100";
when "00" & x"596" => DATA <= x"f8ba";
when "00" & x"597" => DATA <= x"1002";
when "00" & x"598" => DATA <= x"6100";
when "00" & x"599" => DATA <= x"f8b4";
when "00" & x"59a" => DATA <= x"201f";
when "00" & x"59b" => DATA <= x"6100";
when "00" & x"59c" => DATA <= x"f8ae";
when "00" & x"59d" => DATA <= x"b03c";
when "00" & x"59e" => DATA <= x"008e";
when "00" & x"59f" => DATA <= x"6700";
when "00" & x"5a0" => DATA <= x"0044";
when "00" & x"5a1" => DATA <= x"b03c";
when "00" & x"5a2" => DATA <= x"009d";
when "00" & x"5a3" => DATA <= x"6700";
when "00" & x"5a4" => DATA <= x"009e";
when "00" & x"5a5" => DATA <= x"2f00";
when "00" & x"5a6" => DATA <= x"6100";
when "00" & x"5a7" => DATA <= x"f886";
when "00" & x"5a8" => DATA <= x"3f00";
when "00" & x"5a9" => DATA <= x"6100";
when "00" & x"5aa" => DATA <= x"f880";
when "00" & x"5ab" => DATA <= x"1400";
when "00" & x"5ac" => DATA <= x"6100";
when "00" & x"5ad" => DATA <= x"f87a";
when "00" & x"5ae" => DATA <= x"1200";
when "00" & x"5af" => DATA <= x"201f";
when "00" & x"5b0" => DATA <= x"e000";
when "00" & x"5b1" => DATA <= x"201f";
when "00" & x"5b2" => DATA <= x"4e75";
when "00" & x"5b3" => DATA <= x"3238";
when "00" & x"5b4" => DATA <= x"0524";
when "00" & x"5b5" => DATA <= x"2401";
when "00" & x"5b6" => DATA <= x"e082";
when "00" & x"5b7" => DATA <= x"4e75";
when "00" & x"5b8" => DATA <= x"2238";
when "00" & x"5b9" => DATA <= x"0504";
when "00" & x"5ba" => DATA <= x"2401";
when "00" & x"5bb" => DATA <= x"e082";
when "00" & x"5bc" => DATA <= x"4e75";
when "00" & x"5bd" => DATA <= x"2238";
when "00" & x"5be" => DATA <= x"0500";
when "00" & x"5bf" => DATA <= x"2401";
when "00" & x"5c0" => DATA <= x"e082";
when "00" & x"5c1" => DATA <= x"4e75";
when "00" & x"5c2" => DATA <= x"2c78";
when "00" & x"5c3" => DATA <= x"0520";
when "00" & x"5c4" => DATA <= x"122e";
when "00" & x"5c5" => DATA <= x"0006";
when "00" & x"5c6" => DATA <= x"7000";
when "00" & x"5c7" => DATA <= x"102e";
when "00" & x"5c8" => DATA <= x"0007";
when "00" & x"5c9" => DATA <= x"ddc0";
when "00" & x"5ca" => DATA <= x"4a1e";
when "00" & x"5cb" => DATA <= x"6600";
when "00" & x"5cc" => DATA <= x"0026";
when "00" & x"5cd" => DATA <= x"0c1e";
when "00" & x"5ce" => DATA <= x"0028";
when "00" & x"5cf" => DATA <= x"6600";
when "00" & x"5d0" => DATA <= x"001e";
when "00" & x"5d1" => DATA <= x"0c1e";
when "00" & x"5d2" => DATA <= x"0043";
when "00" & x"5d3" => DATA <= x"6600";
when "00" & x"5d4" => DATA <= x"0016";
when "00" & x"5d5" => DATA <= x"0c1e";
when "00" & x"5d6" => DATA <= x"0029";
when "00" & x"5d7" => DATA <= x"6600";
when "00" & x"5d8" => DATA <= x"000e";
when "00" & x"5d9" => DATA <= x"0201";
when "00" & x"5da" => DATA <= x"000f";
when "00" & x"5db" => DATA <= x"0c01";
when "00" & x"5dc" => DATA <= x"0003";
when "00" & x"5dd" => DATA <= x"6600";
when "00" & x"5de" => DATA <= x"0018";
when "00" & x"5df" => DATA <= x"2c78";
when "00" & x"5e0" => DATA <= x"0520";
when "00" & x"5e1" => DATA <= x"7001";
when "00" & x"5e2" => DATA <= x"223c";
when "00" & x"5e3" => DATA <= x"0000";
when "00" & x"5e4" => DATA <= x"052d";
when "00" & x"5e5" => DATA <= x"6100";
when "00" & x"5e6" => DATA <= x"001c";
when "00" & x"5e7" => DATA <= x"7001";
when "00" & x"5e8" => DATA <= x"4ed6";
when "00" & x"5e9" => DATA <= x"4e75";
when "00" & x"5ea" => DATA <= x"203c";
when "00" & x"5eb" => DATA <= x"003f";
when "00" & x"5ec" => DATA <= x"2da4";
when "00" & x"5ed" => DATA <= x"21fc";
when "00" & x"5ee" => DATA <= x"0000";
when "00" & x"5ef" => DATA <= x"0000";
when "00" & x"5f0" => DATA <= x"0510";
when "00" & x"5f1" => DATA <= x"6000";
when "00" & x"5f2" => DATA <= x"0540";
when "00" & x"5f3" => DATA <= x"4e75";
when "00" & x"5f4" => DATA <= x"b0bc";
when "00" & x"5f5" => DATA <= x"0000";
when "00" & x"5f6" => DATA <= x"00ff";
when "00" & x"5f7" => DATA <= x"6200";
when "00" & x"5f8" => DATA <= x"00d8";
when "00" & x"5f9" => DATA <= x"2f0e";
when "00" & x"5fa" => DATA <= x"2f00";
when "00" & x"5fb" => DATA <= x"2f01";
when "00" & x"5fc" => DATA <= x"2f02";
when "00" & x"5fd" => DATA <= x"2c41";
when "00" & x"5fe" => DATA <= x"4a40";
when "00" & x"5ff" => DATA <= x"6600";
when "00" & x"600" => DATA <= x"003c";
when "00" & x"601" => DATA <= x"2f03";
when "00" & x"602" => DATA <= x"2f04";
when "00" & x"603" => DATA <= x"3038";
when "00" & x"604" => DATA <= x"0524";
when "00" & x"605" => DATA <= x"4840";
when "00" & x"606" => DATA <= x"3016";
when "00" & x"607" => DATA <= x"7200";
when "00" & x"608" => DATA <= x"122e";
when "00" & x"609" => DATA <= x"0002";
when "00" & x"60a" => DATA <= x"7400";
when "00" & x"60b" => DATA <= x"142e";
when "00" & x"60c" => DATA <= x"0003";
when "00" & x"60d" => DATA <= x"7600";
when "00" & x"60e" => DATA <= x"162e";
when "00" & x"60f" => DATA <= x"0004";
when "00" & x"610" => DATA <= x"7800";
when "00" & x"611" => DATA <= x"6100";
when "00" & x"612" => DATA <= x"08cc";
when "00" & x"613" => DATA <= x"281f";
when "00" & x"614" => DATA <= x"261f";
when "00" & x"615" => DATA <= x"241f";
when "00" & x"616" => DATA <= x"2401";
when "00" & x"617" => DATA <= x"5242";
when "00" & x"618" => DATA <= x"221f";
when "00" & x"619" => DATA <= x"201f";
when "00" & x"61a" => DATA <= x"2c5f";
when "00" & x"61b" => DATA <= x"023c";
when "00" & x"61c" => DATA <= x"00fd";
when "00" & x"61d" => DATA <= x"4e75";
when "00" & x"61e" => DATA <= x"7200";
when "00" & x"61f" => DATA <= x"7400";
when "00" & x"620" => DATA <= x"b03c";
when "00" & x"621" => DATA <= x"0014";
when "00" & x"622" => DATA <= x"6200";
when "00" & x"623" => DATA <= x"001e";
when "00" & x"624" => DATA <= x"207c";
when "00" & x"625" => DATA <= x"003f";
when "00" & x"626" => DATA <= x"2f2c";
when "00" & x"627" => DATA <= x"d1c0";
when "00" & x"628" => DATA <= x"5348";
when "00" & x"629" => DATA <= x"1210";
when "00" & x"62a" => DATA <= x"207c";
when "00" & x"62b" => DATA <= x"003f";
when "00" & x"62c" => DATA <= x"2f40";
when "00" & x"62d" => DATA <= x"d1c0";
when "00" & x"62e" => DATA <= x"5348";
when "00" & x"62f" => DATA <= x"1410";
when "00" & x"630" => DATA <= x"6000";
when "00" & x"631" => DATA <= x"0018";
when "00" & x"632" => DATA <= x"b03c";
when "00" & x"633" => DATA <= x"007f";
when "00" & x"634" => DATA <= x"6200";
when "00" & x"635" => DATA <= x"000a";
when "00" & x"636" => DATA <= x"7210";
when "00" & x"637" => DATA <= x"7410";
when "00" & x"638" => DATA <= x"6000";
when "00" & x"639" => DATA <= x"0008";
when "00" & x"63a" => DATA <= x"1216";
when "00" & x"63b" => DATA <= x"142e";
when "00" & x"63c" => DATA <= x"0001";
when "00" & x"63d" => DATA <= x"2f00";
when "00" & x"63e" => DATA <= x"103c";
when "00" & x"63f" => DATA <= x"0008";
when "00" & x"640" => DATA <= x"6100";
when "00" & x"641" => DATA <= x"f764";
when "00" & x"642" => DATA <= x"201f";
when "00" & x"643" => DATA <= x"6100";
when "00" & x"644" => DATA <= x"f75e";
when "00" & x"645" => DATA <= x"1001";
when "00" & x"646" => DATA <= x"6100";
when "00" & x"647" => DATA <= x"f758";
when "00" & x"648" => DATA <= x"5341";
when "00" & x"649" => DATA <= x"6b00";
when "00" & x"64a" => DATA <= x"000e";
when "00" & x"64b" => DATA <= x"1036";
when "00" & x"64c" => DATA <= x"1000";
when "00" & x"64d" => DATA <= x"6100";
when "00" & x"64e" => DATA <= x"f74a";
when "00" & x"64f" => DATA <= x"51c9";
when "00" & x"650" => DATA <= x"fff6";
when "00" & x"651" => DATA <= x"1002";
when "00" & x"652" => DATA <= x"6100";
when "00" & x"653" => DATA <= x"f740";
when "00" & x"654" => DATA <= x"5342";
when "00" & x"655" => DATA <= x"6b00";
when "00" & x"656" => DATA <= x"000e";
when "00" & x"657" => DATA <= x"6100";
when "00" & x"658" => DATA <= x"f724";
when "00" & x"659" => DATA <= x"1d80";
when "00" & x"65a" => DATA <= x"2000";
when "00" & x"65b" => DATA <= x"51ca";
when "00" & x"65c" => DATA <= x"fff6";
when "00" & x"65d" => DATA <= x"241f";
when "00" & x"65e" => DATA <= x"221f";
when "00" & x"65f" => DATA <= x"201f";
when "00" & x"660" => DATA <= x"2c5f";
when "00" & x"661" => DATA <= x"023c";
when "00" & x"662" => DATA <= x"00fd";
when "00" & x"663" => DATA <= x"4e75";
when "00" & x"664" => DATA <= x"003c";
when "00" & x"665" => DATA <= x"0002";
when "00" & x"666" => DATA <= x"4e75";
when "00" & x"667" => DATA <= x"2f00";
when "00" & x"668" => DATA <= x"103c";
when "00" & x"669" => DATA <= x"0014";
when "00" & x"66a" => DATA <= x"6100";
when "00" & x"66b" => DATA <= x"f710";
when "00" & x"66c" => DATA <= x"2005";
when "00" & x"66d" => DATA <= x"6100";
when "00" & x"66e" => DATA <= x"f73e";
when "00" & x"66f" => DATA <= x"2004";
when "00" & x"670" => DATA <= x"6100";
when "00" & x"671" => DATA <= x"f738";
when "00" & x"672" => DATA <= x"2003";
when "00" & x"673" => DATA <= x"6100";
when "00" & x"674" => DATA <= x"f732";
when "00" & x"675" => DATA <= x"2002";
when "00" & x"676" => DATA <= x"6100";
when "00" & x"677" => DATA <= x"f72c";
when "00" & x"678" => DATA <= x"2c41";
when "00" & x"679" => DATA <= x"6100";
when "00" & x"67a" => DATA <= x"f746";
when "00" & x"67b" => DATA <= x"201f";
when "00" & x"67c" => DATA <= x"6100";
when "00" & x"67d" => DATA <= x"f6ec";
when "00" & x"67e" => DATA <= x"6100";
when "00" & x"67f" => DATA <= x"f6d6";
when "00" & x"680" => DATA <= x"2f00";
when "00" & x"681" => DATA <= x"6100";
when "00" & x"682" => DATA <= x"f706";
when "00" & x"683" => DATA <= x"2a00";
when "00" & x"684" => DATA <= x"6100";
when "00" & x"685" => DATA <= x"f700";
when "00" & x"686" => DATA <= x"2800";
when "00" & x"687" => DATA <= x"6100";
when "00" & x"688" => DATA <= x"f6fa";
when "00" & x"689" => DATA <= x"2600";
when "00" & x"68a" => DATA <= x"6100";
when "00" & x"68b" => DATA <= x"f6f4";
when "00" & x"68c" => DATA <= x"2400";
when "00" & x"68d" => DATA <= x"201f";
when "00" & x"68e" => DATA <= x"4e75";
when "00" & x"68f" => DATA <= x"2f00";
when "00" & x"690" => DATA <= x"103c";
when "00" & x"691" => DATA <= x"000c";
when "00" & x"692" => DATA <= x"6100";
when "00" & x"693" => DATA <= x"f6c0";
when "00" & x"694" => DATA <= x"1001";
when "00" & x"695" => DATA <= x"6100";
when "00" & x"696" => DATA <= x"f6ba";
when "00" & x"697" => DATA <= x"2002";
when "00" & x"698" => DATA <= x"6100";
when "00" & x"699" => DATA <= x"f6e8";
when "00" & x"69a" => DATA <= x"201f";
when "00" & x"69b" => DATA <= x"6100";
when "00" & x"69c" => DATA <= x"f6ae";
when "00" & x"69d" => DATA <= x"6100";
when "00" & x"69e" => DATA <= x"f698";
when "00" & x"69f" => DATA <= x"2f00";
when "00" & x"6a0" => DATA <= x"6100";
when "00" & x"6a1" => DATA <= x"f6c8";
when "00" & x"6a2" => DATA <= x"2400";
when "00" & x"6a3" => DATA <= x"201f";
when "00" & x"6a4" => DATA <= x"4e75";
when "00" & x"6a5" => DATA <= x"103c";
when "00" & x"6a6" => DATA <= x"000e";
when "00" & x"6a7" => DATA <= x"4eb9";
when "00" & x"6a8" => DATA <= x"003f";
when "00" & x"6a9" => DATA <= x"03e6";
when "00" & x"6aa" => DATA <= x"1001";
when "00" & x"6ab" => DATA <= x"4eb9";
when "00" & x"6ac" => DATA <= x"003f";
when "00" & x"6ad" => DATA <= x"03e6";
when "00" & x"6ae" => DATA <= x"6000";
when "00" & x"6af" => DATA <= x"fccc";
when "00" & x"6b0" => DATA <= x"2f00";
when "00" & x"6b1" => DATA <= x"103c";
when "00" & x"6b2" => DATA <= x"0010";
when "00" & x"6b3" => DATA <= x"6100";
when "00" & x"6b4" => DATA <= x"f67e";
when "00" & x"6b5" => DATA <= x"1001";
when "00" & x"6b6" => DATA <= x"6100";
when "00" & x"6b7" => DATA <= x"f678";
when "00" & x"6b8" => DATA <= x"2017";
when "00" & x"6b9" => DATA <= x"6100";
when "00" & x"6ba" => DATA <= x"f672";
when "00" & x"6bb" => DATA <= x"6100";
when "00" & x"6bc" => DATA <= x"f65c";
when "00" & x"6bd" => DATA <= x"201f";
when "00" & x"6be" => DATA <= x"4e75";
when "00" & x"6bf" => DATA <= x"2f00";
when "00" & x"6c0" => DATA <= x"103c";
when "00" & x"6c1" => DATA <= x"0016";
when "00" & x"6c2" => DATA <= x"6100";
when "00" & x"6c3" => DATA <= x"f660";
when "00" & x"6c4" => DATA <= x"2004";
when "00" & x"6c5" => DATA <= x"6100";
when "00" & x"6c6" => DATA <= x"f68e";
when "00" & x"6c7" => DATA <= x"2003";
when "00" & x"6c8" => DATA <= x"6100";
when "00" & x"6c9" => DATA <= x"f688";
when "00" & x"6ca" => DATA <= x"2002";
when "00" & x"6cb" => DATA <= x"6100";
when "00" & x"6cc" => DATA <= x"f682";
when "00" & x"6cd" => DATA <= x"2001";
when "00" & x"6ce" => DATA <= x"6100";
when "00" & x"6cf" => DATA <= x"f648";
when "00" & x"6d0" => DATA <= x"201f";
when "00" & x"6d1" => DATA <= x"6100";
when "00" & x"6d2" => DATA <= x"f676";
when "00" & x"6d3" => DATA <= x"6100";
when "00" & x"6d4" => DATA <= x"f62c";
when "00" & x"6d5" => DATA <= x"2800";
when "00" & x"6d6" => DATA <= x"6100";
when "00" & x"6d7" => DATA <= x"f65c";
when "00" & x"6d8" => DATA <= x"2600";
when "00" & x"6d9" => DATA <= x"6100";
when "00" & x"6da" => DATA <= x"f656";
when "00" & x"6db" => DATA <= x"2400";
when "00" & x"6dc" => DATA <= x"6100";
when "00" & x"6dd" => DATA <= x"f61a";
when "00" & x"6de" => DATA <= x"2200";
when "00" & x"6df" => DATA <= x"6000";
when "00" & x"6e0" => DATA <= x"fc6a";
when "00" & x"6e1" => DATA <= x"2f00";
when "00" & x"6e2" => DATA <= x"103c";
when "00" & x"6e3" => DATA <= x"0012";
when "00" & x"6e4" => DATA <= x"6100";
when "00" & x"6e5" => DATA <= x"f61c";
when "00" & x"6e6" => DATA <= x"201f";
when "00" & x"6e7" => DATA <= x"6100";
when "00" & x"6e8" => DATA <= x"f616";
when "00" & x"6e9" => DATA <= x"4a40";
when "00" & x"6ea" => DATA <= x"6600";
when "00" & x"6eb" => DATA <= x"0012";
when "00" & x"6ec" => DATA <= x"2f00";
when "00" & x"6ed" => DATA <= x"1001";
when "00" & x"6ee" => DATA <= x"6100";
when "00" & x"6ef" => DATA <= x"f608";
when "00" & x"6f0" => DATA <= x"6100";
when "00" & x"6f1" => DATA <= x"f5f2";
when "00" & x"6f2" => DATA <= x"201f";
when "00" & x"6f3" => DATA <= x"4e75";
when "00" & x"6f4" => DATA <= x"6100";
when "00" & x"6f5" => DATA <= x"f650";
when "00" & x"6f6" => DATA <= x"6000";
when "00" & x"6f7" => DATA <= x"f5e6";
when "00" & x"6f8" => DATA <= x"2800";
when "00" & x"6f9" => DATA <= x"c8bc";
when "00" & x"6fa" => DATA <= x"d000";
when "00" & x"6fb" => DATA <= x"0000";
when "00" & x"6fc" => DATA <= x"6000";
when "00" & x"6fd" => DATA <= x"06f6";
when "00" & x"6fe" => DATA <= x"2f05";
when "00" & x"6ff" => DATA <= x"2f04";
when "00" & x"700" => DATA <= x"2f01";
when "00" & x"701" => DATA <= x"2f00";
when "00" & x"702" => DATA <= x"2203";
when "00" & x"703" => DATA <= x"700a";
when "00" & x"704" => DATA <= x"6100";
when "00" & x"705" => DATA <= x"04fa";
when "00" & x"706" => DATA <= x"2801";
when "00" & x"707" => DATA <= x"2202";
when "00" & x"708" => DATA <= x"7009";
when "00" & x"709" => DATA <= x"6100";
when "00" & x"70a" => DATA <= x"04f0";
when "00" & x"70b" => DATA <= x"2a01";
when "00" & x"70c" => DATA <= x"221f";
when "00" & x"70d" => DATA <= x"261f";
when "00" & x"70e" => DATA <= x"7006";
when "00" & x"70f" => DATA <= x"6100";
when "00" & x"710" => DATA <= x"04e4";
when "00" & x"711" => DATA <= x"2001";
when "00" & x"712" => DATA <= x"2203";
when "00" & x"713" => DATA <= x"2604";
when "00" & x"714" => DATA <= x"2405";
when "00" & x"715" => DATA <= x"281f";
when "00" & x"716" => DATA <= x"2a1f";
when "00" & x"717" => DATA <= x"023c";
when "00" & x"718" => DATA <= x"00fd";
when "00" & x"719" => DATA <= x"4e75";
when "00" & x"71a" => DATA <= x"203c";
when "00" & x"71b" => DATA <= x"0000";
when "00" & x"71c" => DATA <= x"0600";
when "00" & x"71d" => DATA <= x"223c";
when "00" & x"71e" => DATA <= x"0000";
when "00" & x"71f" => DATA <= x"0500";
when "00" & x"720" => DATA <= x"243c";
when "00" & x"721" => DATA <= x"0000";
when "00" & x"722" => DATA <= x"052d";
when "00" & x"723" => DATA <= x"4e75";
when "00" & x"724" => DATA <= x"2f38";
when "00" & x"725" => DATA <= x"04d0";
when "00" & x"726" => DATA <= x"4e75";
when "00" & x"727" => DATA <= x"2f03";
when "00" & x"728" => DATA <= x"2f02";
when "00" & x"729" => DATA <= x"2f01";
when "00" & x"72a" => DATA <= x"2f00";
when "00" & x"72b" => DATA <= x"2207";
when "00" & x"72c" => DATA <= x"7004";
when "00" & x"72d" => DATA <= x"6100";
when "00" & x"72e" => DATA <= x"04a8";
when "00" & x"72f" => DATA <= x"2e01";
when "00" & x"730" => DATA <= x"2206";
when "00" & x"731" => DATA <= x"7003";
when "00" & x"732" => DATA <= x"6100";
when "00" & x"733" => DATA <= x"049e";
when "00" & x"734" => DATA <= x"2c01";
when "00" & x"735" => DATA <= x"2205";
when "00" & x"736" => DATA <= x"7002";
when "00" & x"737" => DATA <= x"6100";
when "00" & x"738" => DATA <= x"0494";
when "00" & x"739" => DATA <= x"2a01";
when "00" & x"73a" => DATA <= x"2204";
when "00" & x"73b" => DATA <= x"7001";
when "00" & x"73c" => DATA <= x"6100";
when "00" & x"73d" => DATA <= x"048a";
when "00" & x"73e" => DATA <= x"2801";
when "00" & x"73f" => DATA <= x"221f";
when "00" & x"740" => DATA <= x"700b";
when "00" & x"741" => DATA <= x"6100";
when "00" & x"742" => DATA <= x"0480";
when "00" & x"743" => DATA <= x"2001";
when "00" & x"744" => DATA <= x"221f";
when "00" & x"745" => DATA <= x"2f00";
when "00" & x"746" => DATA <= x"7000";
when "00" & x"747" => DATA <= x"6100";
when "00" & x"748" => DATA <= x"0474";
when "00" & x"749" => DATA <= x"201f";
when "00" & x"74a" => DATA <= x"241f";
when "00" & x"74b" => DATA <= x"261f";
when "00" & x"74c" => DATA <= x"023c";
when "00" & x"74d" => DATA <= x"00fd";
when "00" & x"74e" => DATA <= x"4e75";
when "00" & x"74f" => DATA <= x"027c";
when "00" & x"750" => DATA <= x"f8ff";
when "00" & x"751" => DATA <= x"4e75";
when "00" & x"752" => DATA <= x"007c";
when "00" & x"753" => DATA <= x"0700";
when "00" & x"754" => DATA <= x"4e75";
when "00" & x"755" => DATA <= x"2f03";
when "00" & x"756" => DATA <= x"2f02";
when "00" & x"757" => DATA <= x"4282";
when "00" & x"758" => DATA <= x"c343";
when "00" & x"759" => DATA <= x"2200";
when "00" & x"75a" => DATA <= x"103c";
when "00" & x"75b" => DATA <= x"0007";
when "00" & x"75c" => DATA <= x"6100";
when "00" & x"75d" => DATA <= x"044a";
when "00" & x"75e" => DATA <= x"c340";
when "00" & x"75f" => DATA <= x"c741";
when "00" & x"760" => DATA <= x"241f";
when "00" & x"761" => DATA <= x"261f";
when "00" & x"762" => DATA <= x"023c";
when "00" & x"763" => DATA <= x"00fd";
when "00" & x"764" => DATA <= x"4e75";
when "00" & x"765" => DATA <= x"007c";
when "00" & x"766" => DATA <= x"2000";
when "00" & x"767" => DATA <= x"4e75";
when "00" & x"768" => DATA <= x"2f03";
when "00" & x"769" => DATA <= x"2f02";
when "00" & x"76a" => DATA <= x"4282";
when "00" & x"76b" => DATA <= x"c343";
when "00" & x"76c" => DATA <= x"2200";
when "00" & x"76d" => DATA <= x"103c";
when "00" & x"76e" => DATA <= x"0008";
when "00" & x"76f" => DATA <= x"6100";
when "00" & x"770" => DATA <= x"0424";
when "00" & x"771" => DATA <= x"c340";
when "00" & x"772" => DATA <= x"c741";
when "00" & x"773" => DATA <= x"241f";
when "00" & x"774" => DATA <= x"261f";
when "00" & x"775" => DATA <= x"023c";
when "00" & x"776" => DATA <= x"00fd";
when "00" & x"777" => DATA <= x"4e75";
when "00" & x"778" => DATA <= x"2f03";
when "00" & x"779" => DATA <= x"2f02";
when "00" & x"77a" => DATA <= x"2f01";
when "00" & x"77b" => DATA <= x"2200";
when "00" & x"77c" => DATA <= x"103c";
when "00" & x"77d" => DATA <= x"000c";
when "00" & x"77e" => DATA <= x"6100";
when "00" & x"77f" => DATA <= x"0406";
when "00" & x"780" => DATA <= x"2001";
when "00" & x"781" => DATA <= x"221f";
when "00" & x"782" => DATA <= x"241f";
when "00" & x"783" => DATA <= x"261f";
when "00" & x"784" => DATA <= x"023c";
when "00" & x"785" => DATA <= x"00fd";
when "00" & x"786" => DATA <= x"4e75";
when "00" & x"787" => DATA <= x"6100";
when "00" & x"788" => DATA <= x"03fa";
when "00" & x"789" => DATA <= x"2600";
when "00" & x"78a" => DATA <= x"7040";
when "00" & x"78b" => DATA <= x"2238";
when "00" & x"78c" => DATA <= x"0600";
when "00" & x"78d" => DATA <= x"6100";
when "00" & x"78e" => DATA <= x"fccc";
when "00" & x"78f" => DATA <= x"4280";
when "00" & x"790" => DATA <= x"4281";
when "00" & x"791" => DATA <= x"3038";
when "00" & x"792" => DATA <= x"0600";
when "00" & x"793" => DATA <= x"3238";
when "00" & x"794" => DATA <= x"0600";
when "00" & x"795" => DATA <= x"0480";
when "00" & x"796" => DATA <= x"0000";
when "00" & x"797" => DATA <= x"0280";
when "00" & x"798" => DATA <= x"0481";
when "00" & x"799" => DATA <= x"0000";
when "00" & x"79a" => DATA <= x"0200";
when "00" & x"79b" => DATA <= x"c1fc";
when "00" & x"79c" => DATA <= x"0033";
when "00" & x"79d" => DATA <= x"ed89";
when "00" & x"79e" => DATA <= x"4282";
when "00" & x"79f" => DATA <= x"0838";
when "00" & x"7a0" => DATA <= x"0007";
when "00" & x"7a1" => DATA <= x"0606";
when "00" & x"7a2" => DATA <= x"6700";
when "00" & x"7a3" => DATA <= x"0006";
when "00" & x"7a4" => DATA <= x"08c2";
when "00" & x"7a5" => DATA <= x"0000";
when "00" & x"7a6" => DATA <= x"0838";
when "00" & x"7a7" => DATA <= x"0006";
when "00" & x"7a8" => DATA <= x"0606";
when "00" & x"7a9" => DATA <= x"6700";
when "00" & x"7aa" => DATA <= x"0006";
when "00" & x"7ab" => DATA <= x"08c2";
when "00" & x"7ac" => DATA <= x"0001";
when "00" & x"7ad" => DATA <= x"0838";
when "00" & x"7ae" => DATA <= x"0005";
when "00" & x"7af" => DATA <= x"0606";
when "00" & x"7b0" => DATA <= x"6700";
when "00" & x"7b1" => DATA <= x"0006";
when "00" & x"7b2" => DATA <= x"08c2";
when "00" & x"7b3" => DATA <= x"0002";
when "00" & x"7b4" => DATA <= x"023c";
when "00" & x"7b5" => DATA <= x"00fd";
when "00" & x"7b6" => DATA <= x"4e75";
when "00" & x"7b7" => DATA <= x"103c";
when "00" & x"7b8" => DATA <= x"0080";
when "00" & x"7b9" => DATA <= x"123c";
when "00" & x"7ba" => DATA <= x"0007";
when "00" & x"7bb" => DATA <= x"143c";
when "00" & x"7bc" => DATA <= x"0000";
when "00" & x"7bd" => DATA <= x"6100";
when "00" & x"7be" => DATA <= x"fb5a";
when "00" & x"7bf" => DATA <= x"103c";
when "00" & x"7c0" => DATA <= x"0080";
when "00" & x"7c1" => DATA <= x"123c";
when "00" & x"7c2" => DATA <= x"0008";
when "00" & x"7c3" => DATA <= x"143c";
when "00" & x"7c4" => DATA <= x"0000";
when "00" & x"7c5" => DATA <= x"6100";
when "00" & x"7c6" => DATA <= x"fb4a";
when "00" & x"7c7" => DATA <= x"103c";
when "00" & x"7c8" => DATA <= x"0080";
when "00" & x"7c9" => DATA <= x"123c";
when "00" & x"7ca" => DATA <= x"0009";
when "00" & x"7cb" => DATA <= x"143c";
when "00" & x"7cc" => DATA <= x"0000";
when "00" & x"7cd" => DATA <= x"6100";
when "00" & x"7ce" => DATA <= x"fb3a";
when "00" & x"7cf" => DATA <= x"103c";
when "00" & x"7d0" => DATA <= x"0081";
when "00" & x"7d1" => DATA <= x"123c";
when "00" & x"7d2" => DATA <= x"00f6";
when "00" & x"7d3" => DATA <= x"143c";
when "00" & x"7d4" => DATA <= x"00ff";
when "00" & x"7d5" => DATA <= x"6100";
when "00" & x"7d6" => DATA <= x"fb2a";
when "00" & x"7d7" => DATA <= x"103c";
when "00" & x"7d8" => DATA <= x"0081";
when "00" & x"7d9" => DATA <= x"123c";
when "00" & x"7da" => DATA <= x"00f5";
when "00" & x"7db" => DATA <= x"143c";
when "00" & x"7dc" => DATA <= x"00ff";
when "00" & x"7dd" => DATA <= x"6100";
when "00" & x"7de" => DATA <= x"fb1a";
when "00" & x"7df" => DATA <= x"103c";
when "00" & x"7e0" => DATA <= x"0081";
when "00" & x"7e1" => DATA <= x"123c";
when "00" & x"7e2" => DATA <= x"00f4";
when "00" & x"7e3" => DATA <= x"143c";
when "00" & x"7e4" => DATA <= x"00ff";
when "00" & x"7e5" => DATA <= x"6100";
when "00" & x"7e6" => DATA <= x"fb0a";
when "00" & x"7e7" => DATA <= x"4e75";
when "00" & x"7e8" => DATA <= x"2f0e";
when "00" & x"7e9" => DATA <= x"2f07";
when "00" & x"7ea" => DATA <= x"2f06";
when "00" & x"7eb" => DATA <= x"2f04";
when "00" & x"7ec" => DATA <= x"2f03";
when "00" & x"7ed" => DATA <= x"2f00";
when "00" & x"7ee" => DATA <= x"7eff";
when "00" & x"7ef" => DATA <= x"0800";
when "00" & x"7f0" => DATA <= x"001d";
when "00" & x"7f1" => DATA <= x"6700";
when "00" & x"7f2" => DATA <= x"0004";
when "00" & x"7f3" => DATA <= x"2e02";
when "00" & x"7f4" => DATA <= x"0280";
when "00" & x"7f5" => DATA <= x"0000";
when "00" & x"7f6" => DATA <= x"00ff";
when "00" & x"7f7" => DATA <= x"4a80";
when "00" & x"7f8" => DATA <= x"6600";
when "00" & x"7f9" => DATA <= x"0004";
when "00" & x"7fa" => DATA <= x"700a";
when "00" & x"7fb" => DATA <= x"b0bc";
when "00" & x"7fc" => DATA <= x"0000";
when "00" & x"7fd" => DATA <= x"0002";
when "00" & x"7fe" => DATA <= x"6500";
when "00" & x"7ff" => DATA <= x"00a0";
when "00" & x"800" => DATA <= x"b0bc";
when "00" & x"801" => DATA <= x"0000";
when "00" & x"802" => DATA <= x"0024";
when "00" & x"803" => DATA <= x"6200";
when "00" & x"804" => DATA <= x"0096";
when "00" & x"805" => DATA <= x"2c00";
when "00" & x"806" => DATA <= x"4282";
when "00" & x"807" => DATA <= x"2c41";
when "00" & x"808" => DATA <= x"6100";
when "00" & x"809" => DATA <= x"1712";
when "00" & x"80a" => DATA <= x"528e";
when "00" & x"80b" => DATA <= x"b03c";
when "00" & x"80c" => DATA <= x"0026";
when "00" & x"80d" => DATA <= x"6600";
when "00" & x"80e" => DATA <= x"000a";
when "00" & x"80f" => DATA <= x"7c10";
when "00" & x"810" => DATA <= x"528e";
when "00" & x"811" => DATA <= x"6000";
when "00" & x"812" => DATA <= x"000e";
when "00" & x"813" => DATA <= x"b03c";
when "00" & x"814" => DATA <= x"0024";
when "00" & x"815" => DATA <= x"6600";
when "00" & x"816" => DATA <= x"0006";
when "00" & x"817" => DATA <= x"7c10";
when "00" & x"818" => DATA <= x"528e";
when "00" & x"819" => DATA <= x"0c00";
when "00" & x"81a" => DATA <= x"0039";
when "00" & x"81b" => DATA <= x"6300";
when "00" & x"81c" => DATA <= x"0008";
when "00" & x"81d" => DATA <= x"0200";
when "00" & x"81e" => DATA <= x"00df";
when "00" & x"81f" => DATA <= x"5f00";
when "00" & x"820" => DATA <= x"0400";
when "00" & x"821" => DATA <= x"0030";
when "00" & x"822" => DATA <= x"6b00";
when "00" & x"823" => DATA <= x"0030";
when "00" & x"824" => DATA <= x"b006";
when "00" & x"825" => DATA <= x"6200";
when "00" & x"826" => DATA <= x"002a";
when "00" & x"827" => DATA <= x"bcbc";
when "00" & x"828" => DATA <= x"0000";
when "00" & x"829" => DATA <= x"0010";
when "00" & x"82a" => DATA <= x"6600";
when "00" & x"82b" => DATA <= x"000a";
when "00" & x"82c" => DATA <= x"e98a";
when "00" & x"82d" => DATA <= x"d480";
when "00" & x"82e" => DATA <= x"101e";
when "00" & x"82f" => DATA <= x"60d2";
when "00" & x"830" => DATA <= x"2606";
when "00" & x"831" => DATA <= x"5583";
when "00" & x"832" => DATA <= x"2802";
when "00" & x"833" => DATA <= x"d484";
when "00" & x"834" => DATA <= x"6500";
when "00" & x"835" => DATA <= x"0048";
when "00" & x"836" => DATA <= x"51cb";
when "00" & x"837" => DATA <= x"fff8";
when "00" & x"838" => DATA <= x"d480";
when "00" & x"839" => DATA <= x"101e";
when "00" & x"83a" => DATA <= x"60bc";
when "00" & x"83b" => DATA <= x"4a82";
when "00" & x"83c" => DATA <= x"6700";
when "00" & x"83d" => DATA <= x"002e";
when "00" & x"83e" => DATA <= x"4a87";
when "00" & x"83f" => DATA <= x"6700";
when "00" & x"840" => DATA <= x"0008";
when "00" & x"841" => DATA <= x"b087";
when "00" & x"842" => DATA <= x"6200";
when "00" & x"843" => DATA <= x"002c";
when "00" & x"844" => DATA <= x"220e";
when "00" & x"845" => DATA <= x"5381";
when "00" & x"846" => DATA <= x"201f";
when "00" & x"847" => DATA <= x"261f";
when "00" & x"848" => DATA <= x"281f";
when "00" & x"849" => DATA <= x"2c1f";
when "00" & x"84a" => DATA <= x"2e1f";
when "00" & x"84b" => DATA <= x"2c5f";
when "00" & x"84c" => DATA <= x"023c";
when "00" & x"84d" => DATA <= x"00fd";
when "00" & x"84e" => DATA <= x"4e75";
when "00" & x"84f" => DATA <= x"203c";
when "00" & x"850" => DATA <= x"003f";
when "00" & x"851" => DATA <= x"2dec";
when "00" & x"852" => DATA <= x"6000";
when "00" & x"853" => DATA <= x"0012";
when "00" & x"854" => DATA <= x"203c";
when "00" & x"855" => DATA <= x"003f";
when "00" & x"856" => DATA <= x"2dfc";
when "00" & x"857" => DATA <= x"6000";
when "00" & x"858" => DATA <= x"0008";
when "00" & x"859" => DATA <= x"203c";
when "00" & x"85a" => DATA <= x"003f";
when "00" & x"85b" => DATA <= x"2e0c";
when "00" & x"85c" => DATA <= x"261f";
when "00" & x"85d" => DATA <= x"261f";
when "00" & x"85e" => DATA <= x"281f";
when "00" & x"85f" => DATA <= x"2c1f";
when "00" & x"860" => DATA <= x"2e1f";
when "00" & x"861" => DATA <= x"2c5f";
when "00" & x"862" => DATA <= x"003c";
when "00" & x"863" => DATA <= x"0002";
when "00" & x"864" => DATA <= x"4e75";
when "00" & x"865" => DATA <= x"2f00";
when "00" & x"866" => DATA <= x"2f01";
when "00" & x"867" => DATA <= x"6100";
when "00" & x"868" => DATA <= x"07bc";
when "00" & x"869" => DATA <= x"2401";
when "00" & x"86a" => DATA <= x"221f";
when "00" & x"86b" => DATA <= x"201f";
when "00" & x"86c" => DATA <= x"4e75";
when "00" & x"86d" => DATA <= x"b03c";
when "00" & x"86e" => DATA <= x"003a";
when "00" & x"86f" => DATA <= x"6200";
when "00" & x"870" => DATA <= x"001c";
when "00" & x"871" => DATA <= x"2f0e";
when "00" & x"872" => DATA <= x"d040";
when "00" & x"873" => DATA <= x"d040";
when "00" & x"874" => DATA <= x"2c79";
when "00" & x"875" => DATA <= x"003f";
when "00" & x"876" => DATA <= x"36fc";
when "00" & x"877" => DATA <= x"ddc0";
when "00" & x"878" => DATA <= x"4dd6";
when "00" & x"879" => DATA <= x"4e96";
when "00" & x"87a" => DATA <= x"2c5f";
when "00" & x"87b" => DATA <= x"023c";
when "00" & x"87c" => DATA <= x"00fd";
when "00" & x"87d" => DATA <= x"4e75";
when "00" & x"87e" => DATA <= x"203c";
when "00" & x"87f" => DATA <= x"003f";
when "00" & x"880" => DATA <= x"2ef8";
when "00" & x"881" => DATA <= x"003c";
when "00" & x"882" => DATA <= x"0002";
when "00" & x"883" => DATA <= x"4e75";
when "00" & x"884" => DATA <= x"103c";
when "00" & x"885" => DATA <= x"008b";
when "00" & x"886" => DATA <= x"6100";
when "00" & x"887" => DATA <= x"f9c8";
when "00" & x"888" => DATA <= x"103c";
when "00" & x"889" => DATA <= x"0010";
when "00" & x"88a" => DATA <= x"4e75";
when "00" & x"88b" => DATA <= x"7000";
when "00" & x"88c" => DATA <= x"7200";
when "00" & x"88d" => DATA <= x"6100";
when "00" & x"88e" => DATA <= x"fbb2";
when "00" & x"88f" => DATA <= x"103c";
when "00" & x"890" => DATA <= x"0016";
when "00" & x"891" => DATA <= x"4e75";
when "00" & x"892" => DATA <= x"2f38";
when "00" & x"893" => DATA <= x"0404";
when "00" & x"894" => DATA <= x"4e75";
when "00" & x"895" => DATA <= x"0838";
when "00" & x"896" => DATA <= x"0006";
when "00" & x"897" => DATA <= x"0535";
when "00" & x"898" => DATA <= x"6600";
when "00" & x"899" => DATA <= x"0008";
when "00" & x"89a" => DATA <= x"023c";
when "00" & x"89b" => DATA <= x"00fe";
when "00" & x"89c" => DATA <= x"4e75";
when "00" & x"89d" => DATA <= x"003c";
when "00" & x"89e" => DATA <= x"0001";
when "00" & x"89f" => DATA <= x"4e75";
when "00" & x"8a0" => DATA <= x"2f04";
when "00" & x"8a1" => DATA <= x"7801";
when "00" & x"8a2" => DATA <= x"2f0e";
when "00" & x"8a3" => DATA <= x"2c79";
when "00" & x"8a4" => DATA <= x"0000";
when "00" & x"8a5" => DATA <= x"048c";
when "00" & x"8a6" => DATA <= x"4e96";
when "00" & x"8a7" => DATA <= x"2c5f";
when "00" & x"8a8" => DATA <= x"281f";
when "00" & x"8a9" => DATA <= x"4e75";
when "00" & x"8aa" => DATA <= x"4e75";
when "00" & x"8ab" => DATA <= x"b0bc";
when "00" & x"8ac" => DATA <= x"0000";
when "00" & x"8ad" => DATA <= x"04ff";
when "00" & x"8ae" => DATA <= x"6200";
when "00" & x"8af" => DATA <= x"0040";
when "00" & x"8b0" => DATA <= x"b2bc";
when "00" & x"8b1" => DATA <= x"0000";
when "00" & x"8b2" => DATA <= x"03ff";
when "00" & x"8b3" => DATA <= x"6200";
when "00" & x"8b4" => DATA <= x"0036";
when "00" & x"8b5" => DATA <= x"2f00";
when "00" & x"8b6" => DATA <= x"2f01";
when "00" & x"8b7" => DATA <= x"31c0";
when "00" & x"8b8" => DATA <= x"0600";
when "00" & x"8b9" => DATA <= x"31c1";
when "00" & x"8ba" => DATA <= x"0602";
when "00" & x"8bb" => DATA <= x"223c";
when "00" & x"8bc" => DATA <= x"0000";
when "00" & x"8bd" => DATA <= x"0600";
when "00" & x"8be" => DATA <= x"7009";
when "00" & x"8bf" => DATA <= x"6100";
when "00" & x"8c0" => DATA <= x"fa68";
when "00" & x"8c1" => DATA <= x"7400";
when "00" & x"8c2" => DATA <= x"7600";
when "00" & x"8c3" => DATA <= x"1438";
when "00" & x"8c4" => DATA <= x"0604";
when "00" & x"8c5" => DATA <= x"221f";
when "00" & x"8c6" => DATA <= x"201f";
when "00" & x"8c7" => DATA <= x"b43c";
when "00" & x"8c8" => DATA <= x"00ff";
when "00" & x"8c9" => DATA <= x"6700";
when "00" & x"8ca" => DATA <= x"000a";
when "00" & x"8cb" => DATA <= x"7800";
when "00" & x"8cc" => DATA <= x"023c";
when "00" & x"8cd" => DATA <= x"00fd";
when "00" & x"8ce" => DATA <= x"4e75";
when "00" & x"8cf" => DATA <= x"203c";
when "00" & x"8d0" => DATA <= x"003f";
when "00" & x"8d1" => DATA <= x"2d68";
when "00" & x"8d2" => DATA <= x"78ff";
when "00" & x"8d3" => DATA <= x"003c";
when "00" & x"8d4" => DATA <= x"0002";
when "00" & x"8d5" => DATA <= x"4e75";
when "00" & x"8d6" => DATA <= x"b5fc";
when "00" & x"8d7" => DATA <= x"0000";
when "00" & x"8d8" => DATA <= x"002f";
when "00" & x"8d9" => DATA <= x"6200";
when "00" & x"8da" => DATA <= x"0018";
when "00" & x"8db" => DATA <= x"2f0a";
when "00" & x"8dc" => DATA <= x"d4ca";
when "00" & x"8dd" => DATA <= x"d4ca";
when "00" & x"8de" => DATA <= x"d5f8";
when "00" & x"8df" => DATA <= x"0000";
when "00" & x"8e0" => DATA <= x"45d2";
when "00" & x"8e1" => DATA <= x"4e92";
when "00" & x"8e2" => DATA <= x"245f";
when "00" & x"8e3" => DATA <= x"023c";
when "00" & x"8e4" => DATA <= x"00fd";
when "00" & x"8e5" => DATA <= x"4e75";
when "00" & x"8e6" => DATA <= x"203c";
when "00" & x"8e7" => DATA <= x"003f";
when "00" & x"8e8" => DATA <= x"2e4c";
when "00" & x"8e9" => DATA <= x"003c";
when "00" & x"8ea" => DATA <= x"0002";
when "00" & x"8eb" => DATA <= x"4e75";
when "00" & x"8ec" => DATA <= x"2f00";
when "00" & x"8ed" => DATA <= x"2f01";
when "00" & x"8ee" => DATA <= x"203c";
when "00" & x"8ef" => DATA <= x"003f";
when "00" & x"8f0" => DATA <= x"2826";
when "00" & x"8f1" => DATA <= x"720b";
when "00" & x"8f2" => DATA <= x"6100";
when "00" & x"8f3" => DATA <= x"018c";
when "00" & x"8f4" => DATA <= x"221f";
when "00" & x"8f5" => DATA <= x"201f";
when "00" & x"8f6" => DATA <= x"023c";
when "00" & x"8f7" => DATA <= x"00fd";
when "00" & x"8f8" => DATA <= x"4e75";
when "00" & x"8f9" => DATA <= x"2f00";
when "00" & x"8fa" => DATA <= x"2f01";
when "00" & x"8fb" => DATA <= x"203c";
when "00" & x"8fc" => DATA <= x"003f";
when "00" & x"8fd" => DATA <= x"2831";
when "00" & x"8fe" => DATA <= x"720b";
when "00" & x"8ff" => DATA <= x"6100";
when "00" & x"900" => DATA <= x"0172";
when "00" & x"901" => DATA <= x"221f";
when "00" & x"902" => DATA <= x"201f";
when "00" & x"903" => DATA <= x"023c";
when "00" & x"904" => DATA <= x"00fd";
when "00" & x"905" => DATA <= x"4e75";
when "00" & x"906" => DATA <= x"2f0e";
when "00" & x"907" => DATA <= x"2f09";
when "00" & x"908" => DATA <= x"2f01";
when "00" & x"909" => DATA <= x"2f00";
when "00" & x"90a" => DATA <= x"2c41";
when "00" & x"90b" => DATA <= x"0280";
when "00" & x"90c" => DATA <= x"0002";
when "00" & x"90d" => DATA <= x"0000";
when "00" & x"90e" => DATA <= x"6700";
when "00" & x"90f" => DATA <= x"000c";
when "00" & x"910" => DATA <= x"5382";
when "00" & x"911" => DATA <= x"6b00";
when "00" & x"912" => DATA <= x"005c";
when "00" & x"913" => DATA <= x"1cfc";
when "00" & x"914" => DATA <= x"0058";
when "00" & x"915" => DATA <= x"43f9";
when "00" & x"916" => DATA <= x"003f";
when "00" & x"917" => DATA <= x"2f54";
when "00" & x"918" => DATA <= x"b099";
when "00" & x"919" => DATA <= x"6700";
when "00" & x"91a" => DATA <= x"0014";
when "00" & x"91b" => DATA <= x"2219";
when "00" & x"91c" => DATA <= x"b23c";
when "00" & x"91d" => DATA <= x"00ff";
when "00" & x"91e" => DATA <= x"6700";
when "00" & x"91f" => DATA <= x"0020";
when "00" & x"920" => DATA <= x"b23c";
when "00" & x"921" => DATA <= x"0000";
when "00" & x"922" => DATA <= x"66f0";
when "00" & x"923" => DATA <= x"60e8";
when "00" & x"924" => DATA <= x"2019";
when "00" & x"925" => DATA <= x"5382";
when "00" & x"926" => DATA <= x"6b00";
when "00" & x"927" => DATA <= x"0032";
when "00" & x"928" => DATA <= x"1cd9";
when "00" & x"929" => DATA <= x"66f6";
when "00" & x"92a" => DATA <= x"201f";
when "00" & x"92b" => DATA <= x"221f";
when "00" & x"92c" => DATA <= x"225f";
when "00" & x"92d" => DATA <= x"2c5f";
when "00" & x"92e" => DATA <= x"4e75";
when "00" & x"92f" => DATA <= x"0c81";
when "00" & x"930" => DATA <= x"0000";
when "00" & x"931" => DATA <= x"000d";
when "00" & x"932" => DATA <= x"6500";
when "00" & x"933" => DATA <= x"001a";
when "00" & x"934" => DATA <= x"2cfc";
when "00" & x"935" => DATA <= x"4f53";
when "00" & x"936" => DATA <= x"5f55";
when "00" & x"937" => DATA <= x"2cfc";
when "00" & x"938" => DATA <= x"6e64";
when "00" & x"939" => DATA <= x"6566";
when "00" & x"93a" => DATA <= x"2cfc";
when "00" & x"93b" => DATA <= x"696e";
when "00" & x"93c" => DATA <= x"6564";
when "00" & x"93d" => DATA <= x"1cfc";
when "00" & x"93e" => DATA <= x"0000";
when "00" & x"93f" => DATA <= x"60d4";
when "00" & x"940" => DATA <= x"003c";
when "00" & x"941" => DATA <= x"0002";
when "00" & x"942" => DATA <= x"2ebc";
when "00" & x"943" => DATA <= x"003f";
when "00" & x"944" => DATA <= x"2e84";
when "00" & x"945" => DATA <= x"60c8";
when "00" & x"946" => DATA <= x"2f0e";
when "00" & x"947" => DATA <= x"2f0d";
when "00" & x"948" => DATA <= x"2f01";
when "00" & x"949" => DATA <= x"4bf9";
when "00" & x"94a" => DATA <= x"003f";
when "00" & x"94b" => DATA <= x"2f54";
when "00" & x"94c" => DATA <= x"2c57";
when "00" & x"94d" => DATA <= x"201d";
when "00" & x"94e" => DATA <= x"588d";
when "00" & x"94f" => DATA <= x"bd8d";
when "00" & x"950" => DATA <= x"6600";
when "00" & x"951" => DATA <= x"0010";
when "00" & x"952" => DATA <= x"4a2d";
when "00" & x"953" => DATA <= x"ffff";
when "00" & x"954" => DATA <= x"66f4";
when "00" & x"955" => DATA <= x"221f";
when "00" & x"956" => DATA <= x"2a5f";
when "00" & x"957" => DATA <= x"2c5f";
when "00" & x"958" => DATA <= x"4e75";
when "00" & x"959" => DATA <= x"201d";
when "00" & x"95a" => DATA <= x"4a00";
when "00" & x"95b" => DATA <= x"66fa";
when "00" & x"95c" => DATA <= x"b03c";
when "00" & x"95d" => DATA <= x"00ff";
when "00" & x"95e" => DATA <= x"66da";
when "00" & x"95f" => DATA <= x"221f";
when "00" & x"960" => DATA <= x"2a5f";
when "00" & x"961" => DATA <= x"2c5f";
when "00" & x"962" => DATA <= x"203c";
when "00" & x"963" => DATA <= x"003f";
when "00" & x"964" => DATA <= x"2e98";
when "00" & x"965" => DATA <= x"003c";
when "00" & x"966" => DATA <= x"0002";
when "00" & x"967" => DATA <= x"4e75";
when "00" & x"968" => DATA <= x"4a80";
when "00" & x"969" => DATA <= x"6d00";
when "00" & x"96a" => DATA <= x"0010";
when "00" & x"96b" => DATA <= x"b2b8";
when "00" & x"96c" => DATA <= x"0508";
when "00" & x"96d" => DATA <= x"6200";
when "00" & x"96e" => DATA <= x"0008";
when "00" & x"96f" => DATA <= x"023c";
when "00" & x"970" => DATA <= x"00fe";
when "00" & x"971" => DATA <= x"4e75";
when "00" & x"972" => DATA <= x"003c";
when "00" & x"973" => DATA <= x"0001";
when "00" & x"974" => DATA <= x"4e75";
when "00" & x"975" => DATA <= x"0c80";
when "00" & x"976" => DATA <= x"0000";
when "00" & x"977" => DATA <= x"0007";
when "00" & x"978" => DATA <= x"6200";
when "00" & x"979" => DATA <= x"0008";
when "00" & x"97a" => DATA <= x"023c";
when "00" & x"97b" => DATA <= x"00fe";
when "00" & x"97c" => DATA <= x"4e75";
when "00" & x"97d" => DATA <= x"70ff";
when "00" & x"97e" => DATA <= x"72fe";
when "00" & x"97f" => DATA <= x"003c";
when "00" & x"980" => DATA <= x"0001";
when "00" & x"981" => DATA <= x"4e75";
when "00" & x"982" => DATA <= x"2f38";
when "00" & x"983" => DATA <= x"0478";
when "00" & x"984" => DATA <= x"4e75";
when "00" & x"985" => DATA <= x"2f01";
when "00" & x"986" => DATA <= x"7001";
when "00" & x"987" => DATA <= x"223c";
when "00" & x"988" => DATA <= x"0000";
when "00" & x"989" => DATA <= x"0600";
when "00" & x"98a" => DATA <= x"6100";
when "00" & x"98b" => DATA <= x"f8d2";
when "00" & x"98c" => DATA <= x"2038";
when "00" & x"98d" => DATA <= x"0600";
when "00" & x"98e" => DATA <= x"90b8";
when "00" & x"98f" => DATA <= x"0528";
when "00" & x"990" => DATA <= x"221f";
when "00" & x"991" => DATA <= x"4e75";
when "00" & x"992" => DATA <= x"b0bc";
when "00" & x"993" => DATA <= x"0000";
when "00" & x"994" => DATA <= x"04ff";
when "00" & x"995" => DATA <= x"6200";
when "00" & x"996" => DATA <= x"0038";
when "00" & x"997" => DATA <= x"b2bc";
when "00" & x"998" => DATA <= x"0000";
when "00" & x"999" => DATA <= x"03ff";
when "00" & x"99a" => DATA <= x"6200";
when "00" & x"99b" => DATA <= x"002e";
when "00" & x"99c" => DATA <= x"2f00";
when "00" & x"99d" => DATA <= x"7019";
when "00" & x"99e" => DATA <= x"6100";
when "00" & x"99f" => DATA <= x"f6ac";
when "00" & x"9a0" => DATA <= x"201f";
when "00" & x"9a1" => DATA <= x"6100";
when "00" & x"9a2" => DATA <= x"f6a6";
when "00" & x"9a3" => DATA <= x"3001";
when "00" & x"9a4" => DATA <= x"6100";
when "00" & x"9a5" => DATA <= x"f6a0";
when "00" & x"9a6" => DATA <= x"e088";
when "00" & x"9a7" => DATA <= x"6100";
when "00" & x"9a8" => DATA <= x"f69a";
when "00" & x"9a9" => DATA <= x"3002";
when "00" & x"9aa" => DATA <= x"6100";
when "00" & x"9ab" => DATA <= x"f694";
when "00" & x"9ac" => DATA <= x"e088";
when "00" & x"9ad" => DATA <= x"6100";
when "00" & x"9ae" => DATA <= x"f68e";
when "00" & x"9af" => DATA <= x"023c";
when "00" & x"9b0" => DATA <= x"00fd";
when "00" & x"9b1" => DATA <= x"4e75";
when "00" & x"9b2" => DATA <= x"203c";
when "00" & x"9b3" => DATA <= x"003f";
when "00" & x"9b4" => DATA <= x"2d68";
when "00" & x"9b5" => DATA <= x"78ff";
when "00" & x"9b6" => DATA <= x"003c";
when "00" & x"9b7" => DATA <= x"0002";
when "00" & x"9b8" => DATA <= x"4e75";
when "00" & x"9b9" => DATA <= x"0c81";
when "00" & x"9ba" => DATA <= x"0000";
when "00" & x"9bb" => DATA <= x"0000";
when "00" & x"9bc" => DATA <= x"6700";
when "00" & x"9bd" => DATA <= x"001c";
when "00" & x"9be" => DATA <= x"5341";
when "00" & x"9bf" => DATA <= x"2f08";
when "00" & x"9c0" => DATA <= x"2f00";
when "00" & x"9c1" => DATA <= x"2f01";
when "00" & x"9c2" => DATA <= x"2040";
when "00" & x"9c3" => DATA <= x"1018";
when "00" & x"9c4" => DATA <= x"6100";
when "00" & x"9c5" => DATA <= x"f660";
when "00" & x"9c6" => DATA <= x"51c9";
when "00" & x"9c7" => DATA <= x"fff8";
when "00" & x"9c8" => DATA <= x"221f";
when "00" & x"9c9" => DATA <= x"201f";
when "00" & x"9ca" => DATA <= x"205f";
when "00" & x"9cb" => DATA <= x"4e75";
when "00" & x"9cc" => DATA <= x"2f0e";
when "00" & x"9cd" => DATA <= x"2f0d";
when "00" & x"9ce" => DATA <= x"4a80";
when "00" & x"9cf" => DATA <= x"6700";
when "00" & x"9d0" => DATA <= x"000e";
when "00" & x"9d1" => DATA <= x"2c40";
when "00" & x"9d2" => DATA <= x"2a7c";
when "00" & x"9d3" => DATA <= x"0000";
when "00" & x"9d4" => DATA <= x"0600";
when "00" & x"9d5" => DATA <= x"1ade";
when "00" & x"9d6" => DATA <= x"66fc";
when "00" & x"9d7" => DATA <= x"4a81";
when "00" & x"9d8" => DATA <= x"6700";
when "00" & x"9d9" => DATA <= x"0016";
when "00" & x"9da" => DATA <= x"2f02";
when "00" & x"9db" => DATA <= x"7404";
when "00" & x"9dc" => DATA <= x"2c41";
when "00" & x"9dd" => DATA <= x"2a7c";
when "00" & x"9de" => DATA <= x"0000";
when "00" & x"9df" => DATA <= x"052d";
when "00" & x"9e0" => DATA <= x"1ade";
when "00" & x"9e1" => DATA <= x"5382";
when "00" & x"9e2" => DATA <= x"6afa";
when "00" & x"9e3" => DATA <= x"241f";
when "00" & x"9e4" => DATA <= x"2a5f";
when "00" & x"9e5" => DATA <= x"2c5f";
when "00" & x"9e6" => DATA <= x"4e75";
when "00" & x"9e7" => DATA <= x"2f02";
when "00" & x"9e8" => DATA <= x"2f01";
when "00" & x"9e9" => DATA <= x"2f00";
when "00" & x"9ea" => DATA <= x"2203";
when "00" & x"9eb" => DATA <= x"7004";
when "00" & x"9ec" => DATA <= x"6100";
when "00" & x"9ed" => DATA <= x"fbf4";
when "00" & x"9ee" => DATA <= x"201f";
when "00" & x"9ef" => DATA <= x"221f";
when "00" & x"9f0" => DATA <= x"241f";
when "00" & x"9f1" => DATA <= x"6000";
when "00" & x"9f2" => DATA <= x"fa64";
when "00" & x"9f3" => DATA <= x"b07c";
when "00" & x"9f4" => DATA <= x"0010";
when "00" & x"9f5" => DATA <= x"6300";
when "00" & x"9f6" => DATA <= x"000e";
when "00" & x"9f7" => DATA <= x"203c";
when "00" & x"9f8" => DATA <= x"003f";
when "00" & x"9f9" => DATA <= x"2e20";
when "00" & x"9fa" => DATA <= x"003c";
when "00" & x"9fb" => DATA <= x"0002";
when "00" & x"9fc" => DATA <= x"4e75";
when "00" & x"9fd" => DATA <= x"41f9";
when "00" & x"9fe" => DATA <= x"003f";
when "00" & x"9ff" => DATA <= x"3630";
when "00" & x"a00" => DATA <= x"e588";
when "00" & x"a01" => DATA <= x"d1c0";
when "00" & x"a02" => DATA <= x"d1c0";
when "00" & x"a03" => DATA <= x"d1c0";
when "00" & x"a04" => DATA <= x"2218";
when "00" & x"a05" => DATA <= x"6700";
when "00" & x"a06" => DATA <= x"11ea";
when "00" & x"a07" => DATA <= x"0681";
when "00" & x"a08" => DATA <= x"003f";
when "00" & x"a09" => DATA <= x"0000";
when "00" & x"a0a" => DATA <= x"2418";
when "00" & x"a0b" => DATA <= x"6700";
when "00" & x"a0c" => DATA <= x"0008";
when "00" & x"a0d" => DATA <= x"0682";
when "00" & x"a0e" => DATA <= x"003f";
when "00" & x"a0f" => DATA <= x"0000";
when "00" & x"a10" => DATA <= x"2618";
when "00" & x"a11" => DATA <= x"6700";
when "00" & x"a12" => DATA <= x"0008";
when "00" & x"a13" => DATA <= x"0683";
when "00" & x"a14" => DATA <= x"003f";
when "00" & x"a15" => DATA <= x"0000";
when "00" & x"a16" => DATA <= x"4e75";
when "00" & x"a17" => DATA <= x"b0bc";
when "00" & x"a18" => DATA <= x"0000";
when "00" & x"a19" => DATA <= x"04ff";
when "00" & x"a1a" => DATA <= x"6200";
when "00" & x"a1b" => DATA <= x"005c";
when "00" & x"a1c" => DATA <= x"b2bc";
when "00" & x"a1d" => DATA <= x"0000";
when "00" & x"a1e" => DATA <= x"03ff";
when "00" & x"a1f" => DATA <= x"6200";
when "00" & x"a20" => DATA <= x"0052";
when "00" & x"a21" => DATA <= x"2f00";
when "00" & x"a22" => DATA <= x"2f01";
when "00" & x"a23" => DATA <= x"103c";
when "00" & x"a24" => DATA <= x"0017";
when "00" & x"a25" => DATA <= x"6100";
when "00" & x"a26" => DATA <= x"f59e";
when "00" & x"a27" => DATA <= x"103c";
when "00" & x"a28" => DATA <= x"0011";
when "00" & x"a29" => DATA <= x"6100";
when "00" & x"a2a" => DATA <= x"f596";
when "00" & x"a2b" => DATA <= x"103c";
when "00" & x"a2c" => DATA <= x"0006";
when "00" & x"a2d" => DATA <= x"6100";
when "00" & x"a2e" => DATA <= x"f58e";
when "00" & x"a2f" => DATA <= x"201f";
when "00" & x"a30" => DATA <= x"e098";
when "00" & x"a31" => DATA <= x"6100";
when "00" & x"a32" => DATA <= x"f586";
when "00" & x"a33" => DATA <= x"e198";
when "00" & x"a34" => DATA <= x"6100";
when "00" & x"a35" => DATA <= x"f580";
when "00" & x"a36" => DATA <= x"2001";
when "00" & x"a37" => DATA <= x"e098";
when "00" & x"a38" => DATA <= x"6100";
when "00" & x"a39" => DATA <= x"f578";
when "00" & x"a3a" => DATA <= x"e198";
when "00" & x"a3b" => DATA <= x"6100";
when "00" & x"a3c" => DATA <= x"f572";
when "00" & x"a3d" => DATA <= x"7000";
when "00" & x"a3e" => DATA <= x"6100";
when "00" & x"a3f" => DATA <= x"f56c";
when "00" & x"a40" => DATA <= x"6100";
when "00" & x"a41" => DATA <= x"f568";
when "00" & x"a42" => DATA <= x"6100";
when "00" & x"a43" => DATA <= x"f564";
when "00" & x"a44" => DATA <= x"221f";
when "00" & x"a45" => DATA <= x"201f";
when "00" & x"a46" => DATA <= x"023c";
when "00" & x"a47" => DATA <= x"00fe";
when "00" & x"a48" => DATA <= x"4e75";
when "00" & x"a49" => DATA <= x"203c";
when "00" & x"a4a" => DATA <= x"003f";
when "00" & x"a4b" => DATA <= x"2d68";
when "00" & x"a4c" => DATA <= x"003c";
when "00" & x"a4d" => DATA <= x"0002";
when "00" & x"a4e" => DATA <= x"4e75";
when "00" & x"a4f" => DATA <= x"6100";
when "00" & x"a50" => DATA <= x"f584";
when "00" & x"a51" => DATA <= x"0000";
when "00" & x"a52" => DATA <= x"0020";
when "00" & x"a53" => DATA <= x"b03c";
when "00" & x"a54" => DATA <= x"0079";
when "00" & x"a55" => DATA <= x"4e75";
when "00" & x"a56" => DATA <= x"2f0e";
when "00" & x"a57" => DATA <= x"2f04";
when "00" & x"a58" => DATA <= x"2c41";
when "00" & x"a59" => DATA <= x"8643";
when "00" & x"a5a" => DATA <= x"6700";
when "00" & x"a5b" => DATA <= x"001e";
when "00" & x"a5c" => DATA <= x"1816";
when "00" & x"a5d" => DATA <= x"e144";
when "00" & x"a5e" => DATA <= x"b940";
when "00" & x"a5f" => DATA <= x"7807";
when "00" & x"a60" => DATA <= x"e340";
when "00" & x"a61" => DATA <= x"6400";
when "00" & x"a62" => DATA <= x"0006";
when "00" & x"a63" => DATA <= x"0a40";
when "00" & x"a64" => DATA <= x"1021";
when "00" & x"a65" => DATA <= x"51cc";
when "00" & x"a66" => DATA <= x"fff4";
when "00" & x"a67" => DATA <= x"dcc3";
when "00" & x"a68" => DATA <= x"b48e";
when "00" & x"a69" => DATA <= x"65e4";
when "00" & x"a6a" => DATA <= x"281f";
when "00" & x"a6b" => DATA <= x"2c5f";
when "00" & x"a6c" => DATA <= x"023c";
when "00" & x"a6d" => DATA <= x"00fd";
when "00" & x"a6e" => DATA <= x"4e75";
when "00" & x"a6f" => DATA <= x"1400";
when "00" & x"a70" => DATA <= x"708a";
when "00" & x"a71" => DATA <= x"7203";
when "00" & x"a72" => DATA <= x"6100";
when "00" & x"a73" => DATA <= x"f5f0";
when "00" & x"a74" => DATA <= x"4e75";
when "00" & x"a75" => DATA <= x"027c";
when "00" & x"a76" => DATA <= x"dfff";
when "00" & x"a77" => DATA <= x"4e75";
when "00" & x"a78" => DATA <= x"b2bc";
when "00" & x"a79" => DATA <= x"0000";
when "00" & x"a7a" => DATA <= x"00ff";
when "00" & x"a7b" => DATA <= x"6200";
when "00" & x"a7c" => DATA <= x"0060";
when "00" & x"a7d" => DATA <= x"2f08";
when "00" & x"a7e" => DATA <= x"2040";
when "00" & x"a7f" => DATA <= x"103c";
when "00" & x"a80" => DATA <= x"000a";
when "00" & x"a81" => DATA <= x"6100";
when "00" & x"a82" => DATA <= x"eee2";
when "00" & x"a83" => DATA <= x"1003";
when "00" & x"a84" => DATA <= x"6100";
when "00" & x"a85" => DATA <= x"eedc";
when "00" & x"a86" => DATA <= x"1002";
when "00" & x"a87" => DATA <= x"6100";
when "00" & x"a88" => DATA <= x"eed6";
when "00" & x"a89" => DATA <= x"1001";
when "00" & x"a8a" => DATA <= x"6100";
when "00" & x"a8b" => DATA <= x"eed0";
when "00" & x"a8c" => DATA <= x"103c";
when "00" & x"a8d" => DATA <= x"0007";
when "00" & x"a8e" => DATA <= x"6100";
when "00" & x"a8f" => DATA <= x"eec8";
when "00" & x"a90" => DATA <= x"103c";
when "00" & x"a91" => DATA <= x"0000";
when "00" & x"a92" => DATA <= x"6100";
when "00" & x"a93" => DATA <= x"eec0";
when "00" & x"a94" => DATA <= x"6100";
when "00" & x"a95" => DATA <= x"eeaa";
when "00" & x"a96" => DATA <= x"b03c";
when "00" & x"a97" => DATA <= x"0080";
when "00" & x"a98" => DATA <= x"6400";
when "00" & x"a99" => DATA <= x"001c";
when "00" & x"a9a" => DATA <= x"7200";
when "00" & x"a9b" => DATA <= x"6100";
when "00" & x"a9c" => DATA <= x"ee9c";
when "00" & x"a9d" => DATA <= x"10c0";
when "00" & x"a9e" => DATA <= x"5241";
when "00" & x"a9f" => DATA <= x"b03c";
when "00" & x"aa0" => DATA <= x"000d";
when "00" & x"aa1" => DATA <= x"66f2";
when "00" & x"aa2" => DATA <= x"5341";
when "00" & x"aa3" => DATA <= x"205f";
when "00" & x"aa4" => DATA <= x"023c";
when "00" & x"aa5" => DATA <= x"00fe";
when "00" & x"aa6" => DATA <= x"4e75";
when "00" & x"aa7" => DATA <= x"205f";
when "00" & x"aa8" => DATA <= x"5341";
when "00" & x"aa9" => DATA <= x"003c";
when "00" & x"aaa" => DATA <= x"0001";
when "00" & x"aab" => DATA <= x"4e75";
when "00" & x"aac" => DATA <= x"003c";
when "00" & x"aad" => DATA <= x"0002";
when "00" & x"aae" => DATA <= x"4e75";
when "00" & x"aaf" => DATA <= x"2f03";
when "00" & x"ab0" => DATA <= x"2639";
when "00" & x"ab1" => DATA <= x"003f";
when "00" & x"ab2" => DATA <= x"3ede";
when "00" & x"ab3" => DATA <= x"6100";
when "00" & x"ab4" => DATA <= x"0006";
when "00" & x"ab5" => DATA <= x"261f";
when "00" & x"ab6" => DATA <= x"4e75";
when "00" & x"ab7" => DATA <= x"2f0e";
when "00" & x"ab8" => DATA <= x"2f0d";
when "00" & x"ab9" => DATA <= x"2c41";
when "00" & x"aba" => DATA <= x"2a43";
when "00" & x"abb" => DATA <= x"101e";
when "00" & x"abc" => DATA <= x"b03c";
when "00" & x"abd" => DATA <= x"0025";
when "00" & x"abe" => DATA <= x"6700";
when "00" & x"abf" => DATA <= x"0010";
when "00" & x"ac0" => DATA <= x"1ac0";
when "00" & x"ac1" => DATA <= x"b03c";
when "00" & x"ac2" => DATA <= x"0000";
when "00" & x"ac3" => DATA <= x"66ee";
when "00" & x"ac4" => DATA <= x"2a5f";
when "00" & x"ac5" => DATA <= x"2c5f";
when "00" & x"ac6" => DATA <= x"4e75";
when "00" & x"ac7" => DATA <= x"101e";
when "00" & x"ac8" => DATA <= x"b03c";
when "00" & x"ac9" => DATA <= x"0030";
when "00" & x"aca" => DATA <= x"6600";
when "00" & x"acb" => DATA <= x"0008";
when "00" & x"acc" => DATA <= x"1afc";
when "00" & x"acd" => DATA <= x"0000";
when "00" & x"ace" => DATA <= x"60d8";
when "00" & x"acf" => DATA <= x"c03c";
when "00" & x"ad0" => DATA <= x"00df";
when "00" & x"ad1" => DATA <= x"b03c";
when "00" & x"ad2" => DATA <= x"0025";
when "00" & x"ad3" => DATA <= x"6600";
when "00" & x"ad4" => DATA <= x"0008";
when "00" & x"ad5" => DATA <= x"1afc";
when "00" & x"ad6" => DATA <= x"0025";
when "00" & x"ad7" => DATA <= x"60c6";
when "00" & x"ad8" => DATA <= x"b03c";
when "00" & x"ad9" => DATA <= x"005a";
when "00" & x"ada" => DATA <= x"6600";
when "00" & x"adb" => DATA <= x"0006";
when "00" & x"adc" => DATA <= x"123c";
when "00" & x"add" => DATA <= x"005a";
when "00" & x"ade" => DATA <= x"e158";
when "00" & x"adf" => DATA <= x"101e";
when "00" & x"ae0" => DATA <= x"c07c";
when "00" & x"ae1" => DATA <= x"dfdf";
when "00" & x"ae2" => DATA <= x"b07c";
when "00" & x"ae3" => DATA <= x"4353";
when "00" & x"ae4" => DATA <= x"6700";
when "00" & x"ae5" => DATA <= x"00aa";
when "00" & x"ae6" => DATA <= x"b07c";
when "00" & x"ae7" => DATA <= x"5345";
when "00" & x"ae8" => DATA <= x"6700";
when "00" & x"ae9" => DATA <= x"00a2";
when "00" & x"aea" => DATA <= x"b07c";
when "00" & x"aeb" => DATA <= x"4d49";
when "00" & x"aec" => DATA <= x"6700";
when "00" & x"aed" => DATA <= x"009a";
when "00" & x"aee" => DATA <= x"b07c";
when "00" & x"aef" => DATA <= x"3132";
when "00" & x"af0" => DATA <= x"6700";
when "00" & x"af1" => DATA <= x"0092";
when "00" & x"af2" => DATA <= x"b07c";
when "00" & x"af3" => DATA <= x"3234";
when "00" & x"af4" => DATA <= x"6700";
when "00" & x"af5" => DATA <= x"008a";
when "00" & x"af6" => DATA <= x"b07c";
when "00" & x"af7" => DATA <= x"414d";
when "00" & x"af8" => DATA <= x"6700";
when "00" & x"af9" => DATA <= x"0082";
when "00" & x"afa" => DATA <= x"b07c";
when "00" & x"afb" => DATA <= x"504d";
when "00" & x"afc" => DATA <= x"6700";
when "00" & x"afd" => DATA <= x"007a";
when "00" & x"afe" => DATA <= x"b07c";
when "00" & x"aff" => DATA <= x"5745";
when "00" & x"b00" => DATA <= x"6700";
when "00" & x"b01" => DATA <= x"0072";
when "00" & x"b02" => DATA <= x"b07c";
when "00" & x"b03" => DATA <= x"5733";
when "00" & x"b04" => DATA <= x"6700";
when "00" & x"b05" => DATA <= x"006a";
when "00" & x"b06" => DATA <= x"b07c";
when "00" & x"b07" => DATA <= x"574e";
when "00" & x"b08" => DATA <= x"6700";
when "00" & x"b09" => DATA <= x"0062";
when "00" & x"b0a" => DATA <= x"b07c";
when "00" & x"b0b" => DATA <= x"4459";
when "00" & x"b0c" => DATA <= x"6700";
when "00" & x"b0d" => DATA <= x"005a";
when "00" & x"b0e" => DATA <= x"b07c";
when "00" & x"b0f" => DATA <= x"5354";
when "00" & x"b10" => DATA <= x"6700";
when "00" & x"b11" => DATA <= x"0052";
when "00" & x"b12" => DATA <= x"b07c";
when "00" & x"b13" => DATA <= x"4d4f";
when "00" & x"b14" => DATA <= x"6700";
when "00" & x"b15" => DATA <= x"004a";
when "00" & x"b16" => DATA <= x"b07c";
when "00" & x"b17" => DATA <= x"4d33";
when "00" & x"b18" => DATA <= x"6700";
when "00" & x"b19" => DATA <= x"0042";
when "00" & x"b1a" => DATA <= x"b07c";
when "00" & x"b1b" => DATA <= x"4d4e";
when "00" & x"b1c" => DATA <= x"6700";
when "00" & x"b1d" => DATA <= x"003a";
when "00" & x"b1e" => DATA <= x"b07c";
when "00" & x"b1f" => DATA <= x"4345";
when "00" & x"b20" => DATA <= x"6700";
when "00" & x"b21" => DATA <= x"0032";
when "00" & x"b22" => DATA <= x"b07c";
when "00" & x"b23" => DATA <= x"5952";
when "00" & x"b24" => DATA <= x"6700";
when "00" & x"b25" => DATA <= x"002a";
when "00" & x"b26" => DATA <= x"b07c";
when "00" & x"b27" => DATA <= x"574b";
when "00" & x"b28" => DATA <= x"6700";
when "00" & x"b29" => DATA <= x"0022";
when "00" & x"b2a" => DATA <= x"b07c";
when "00" & x"b2b" => DATA <= x"444e";
when "00" & x"b2c" => DATA <= x"6700";
when "00" & x"b2d" => DATA <= x"001a";
when "00" & x"b2e" => DATA <= x"b07c";
when "00" & x"b2f" => DATA <= x"545a";
when "00" & x"b30" => DATA <= x"6700";
when "00" & x"b31" => DATA <= x"0012";
when "00" & x"b32" => DATA <= x"2a5f";
when "00" & x"b33" => DATA <= x"2c5f";
when "00" & x"b34" => DATA <= x"203c";
when "00" & x"b35" => DATA <= x"003f";
when "00" & x"b36" => DATA <= x"2eb0";
when "00" & x"b37" => DATA <= x"003c";
when "00" & x"b38" => DATA <= x"0002";
when "00" & x"b39" => DATA <= x"4e75";
when "00" & x"b3a" => DATA <= x"6000";
when "00" & x"b3b" => DATA <= x"ff00";
when "00" & x"b3c" => DATA <= x"b4bc";
when "00" & x"b3d" => DATA <= x"0000";
when "00" & x"b3e" => DATA <= x"0002";
when "00" & x"b3f" => DATA <= x"6f00";
when "00" & x"b40" => DATA <= x"0484";
when "00" & x"b41" => DATA <= x"5582";
when "00" & x"b42" => DATA <= x"2f0e";
when "00" & x"b43" => DATA <= x"48e7";
when "00" & x"b44" => DATA <= x"7000";
when "00" & x"b45" => DATA <= x"343c";
when "00" & x"b46" => DATA <= x"0000";
when "00" & x"b47" => DATA <= x"e898";
when "00" & x"b48" => DATA <= x"6000";
when "00" & x"b49" => DATA <= x"0072";
when "00" & x"b4a" => DATA <= x"b4bc";
when "00" & x"b4b" => DATA <= x"0000";
when "00" & x"b4c" => DATA <= x"0003";
when "00" & x"b4d" => DATA <= x"6f00";
when "00" & x"b4e" => DATA <= x"0468";
when "00" & x"b4f" => DATA <= x"5782";
when "00" & x"b50" => DATA <= x"2f0e";
when "00" & x"b51" => DATA <= x"48e7";
when "00" & x"b52" => DATA <= x"7000";
when "00" & x"b53" => DATA <= x"343c";
when "00" & x"b54" => DATA <= x"0001";
when "00" & x"b55" => DATA <= x"e098";
when "00" & x"b56" => DATA <= x"6000";
when "00" & x"b57" => DATA <= x"0056";
when "00" & x"b58" => DATA <= x"b4bc";
when "00" & x"b59" => DATA <= x"0000";
when "00" & x"b5a" => DATA <= x"0005";
when "00" & x"b5b" => DATA <= x"6f00";
when "00" & x"b5c" => DATA <= x"044c";
when "00" & x"b5d" => DATA <= x"5b82";
when "00" & x"b5e" => DATA <= x"2f0e";
when "00" & x"b5f" => DATA <= x"48e7";
when "00" & x"b60" => DATA <= x"7000";
when "00" & x"b61" => DATA <= x"343c";
when "00" & x"b62" => DATA <= x"0003";
when "00" & x"b63" => DATA <= x"e198";
when "00" & x"b64" => DATA <= x"e198";
when "00" & x"b65" => DATA <= x"6000";
when "00" & x"b66" => DATA <= x"0038";
when "00" & x"b67" => DATA <= x"b4bc";
when "00" & x"b68" => DATA <= x"0000";
when "00" & x"b69" => DATA <= x"0007";
when "00" & x"b6a" => DATA <= x"6f00";
when "00" & x"b6b" => DATA <= x"042e";
when "00" & x"b6c" => DATA <= x"5f82";
when "00" & x"b6d" => DATA <= x"2f0e";
when "00" & x"b6e" => DATA <= x"48e7";
when "00" & x"b6f" => DATA <= x"7000";
when "00" & x"b70" => DATA <= x"343c";
when "00" & x"b71" => DATA <= x"0005";
when "00" & x"b72" => DATA <= x"e098";
when "00" & x"b73" => DATA <= x"6000";
when "00" & x"b74" => DATA <= x"001c";
when "00" & x"b75" => DATA <= x"b4bc";
when "00" & x"b76" => DATA <= x"0000";
when "00" & x"b77" => DATA <= x"0009";
when "00" & x"b78" => DATA <= x"6f00";
when "00" & x"b79" => DATA <= x"0412";
when "00" & x"b7a" => DATA <= x"0482";
when "00" & x"b7b" => DATA <= x"0000";
when "00" & x"b7c" => DATA <= x"0009";
when "00" & x"b7d" => DATA <= x"2f0e";
when "00" & x"b7e" => DATA <= x"48e7";
when "00" & x"b7f" => DATA <= x"7000";
when "00" & x"b80" => DATA <= x"343c";
when "00" & x"b81" => DATA <= x"0007";
when "00" & x"b82" => DATA <= x"2c41";
when "00" & x"b83" => DATA <= x"2200";
when "00" & x"b84" => DATA <= x"e999";
when "00" & x"b85" => DATA <= x"1001";
when "00" & x"b86" => DATA <= x"c03c";
when "00" & x"b87" => DATA <= x"000f";
when "00" & x"b88" => DATA <= x"163c";
when "00" & x"b89" => DATA <= x"0009";
when "00" & x"b8a" => DATA <= x"9600";
when "00" & x"b8b" => DATA <= x"0600";
when "00" & x"b8c" => DATA <= x"0030";
when "00" & x"b8d" => DATA <= x"0c00";
when "00" & x"b8e" => DATA <= x"003a";
when "00" & x"b8f" => DATA <= x"6500";
when "00" & x"b90" => DATA <= x"0004";
when "00" & x"b91" => DATA <= x"5e00";
when "00" & x"b92" => DATA <= x"1cc0";
when "00" & x"b93" => DATA <= x"51ca";
when "00" & x"b94" => DATA <= x"ffe0";
when "00" & x"b95" => DATA <= x"1cbc";
when "00" & x"b96" => DATA <= x"0000";
when "00" & x"b97" => DATA <= x"4cdf";
when "00" & x"b98" => DATA <= x"000e";
when "00" & x"b99" => DATA <= x"2001";
when "00" & x"b9a" => DATA <= x"220e";
when "00" & x"b9b" => DATA <= x"2c5f";
when "00" & x"b9c" => DATA <= x"023c";
when "00" & x"b9d" => DATA <= x"00fd";
when "00" & x"b9e" => DATA <= x"4e75";
when "00" & x"b9f" => DATA <= x"003c";
when "00" & x"ba0" => DATA <= x"0002";
when "00" & x"ba1" => DATA <= x"4e75";
when "00" & x"ba2" => DATA <= x"b4bc";
when "00" & x"ba3" => DATA <= x"0000";
when "00" & x"ba4" => DATA <= x"0004";
when "00" & x"ba5" => DATA <= x"6500";
when "00" & x"ba6" => DATA <= x"03b8";
when "00" & x"ba7" => DATA <= x"b0bc";
when "00" & x"ba8" => DATA <= x"0000";
when "00" & x"ba9" => DATA <= x"0100";
when "00" & x"baa" => DATA <= x"6400";
when "00" & x"bab" => DATA <= x"01b2";
when "00" & x"bac" => DATA <= x"7c03";
when "00" & x"bad" => DATA <= x"6000";
when "00" & x"bae" => DATA <= x"0042";
when "00" & x"baf" => DATA <= x"b4bc";
when "00" & x"bb0" => DATA <= x"0000";
when "00" & x"bb1" => DATA <= x"0006";
when "00" & x"bb2" => DATA <= x"6500";
when "00" & x"bb3" => DATA <= x"039e";
when "00" & x"bb4" => DATA <= x"b0bc";
when "00" & x"bb5" => DATA <= x"0001";
when "00" & x"bb6" => DATA <= x"0000";
when "00" & x"bb7" => DATA <= x"6400";
when "00" & x"bb8" => DATA <= x"0198";
when "00" & x"bb9" => DATA <= x"7c05";
when "00" & x"bba" => DATA <= x"6000";
when "00" & x"bbb" => DATA <= x"0028";
when "00" & x"bbc" => DATA <= x"b4bc";
when "00" & x"bbd" => DATA <= x"0000";
when "00" & x"bbe" => DATA <= x"0009";
when "00" & x"bbf" => DATA <= x"6500";
when "00" & x"bc0" => DATA <= x"0384";
when "00" & x"bc1" => DATA <= x"b0bc";
when "00" & x"bc2" => DATA <= x"0100";
when "00" & x"bc3" => DATA <= x"0000";
when "00" & x"bc4" => DATA <= x"6400";
when "00" & x"bc5" => DATA <= x"017e";
when "00" & x"bc6" => DATA <= x"7c08";
when "00" & x"bc7" => DATA <= x"6000";
when "00" & x"bc8" => DATA <= x"000e";
when "00" & x"bc9" => DATA <= x"b4bc";
when "00" & x"bca" => DATA <= x"0000";
when "00" & x"bcb" => DATA <= x"000b";
when "00" & x"bcc" => DATA <= x"6500";
when "00" & x"bcd" => DATA <= x"036a";
when "00" & x"bce" => DATA <= x"7c0a";
when "00" & x"bcf" => DATA <= x"c38d";
when "00" & x"bd0" => DATA <= x"48e7";
when "00" & x"bd1" => DATA <= x"ff00";
when "00" & x"bd2" => DATA <= x"2e00";
when "00" & x"bd3" => DATA <= x"6700";
when "00" & x"bd4" => DATA <= x"0058";
when "00" & x"bd5" => DATA <= x"6000";
when "00" & x"bd6" => DATA <= x"0002";
when "00" & x"bd7" => DATA <= x"4244";
when "00" & x"bd8" => DATA <= x"7401";
when "00" & x"bd9" => DATA <= x"2206";
when "00" & x"bda" => DATA <= x"5381";
when "00" & x"bdb" => DATA <= x"6700";
when "00" & x"bdc" => DATA <= x"001c";
when "00" & x"bdd" => DATA <= x"3602";
when "00" & x"bde" => DATA <= x"c6fc";
when "00" & x"bdf" => DATA <= x"000a";
when "00" & x"be0" => DATA <= x"4842";
when "00" & x"be1" => DATA <= x"c4fc";
when "00" & x"be2" => DATA <= x"000a";
when "00" & x"be3" => DATA <= x"4843";
when "00" & x"be4" => DATA <= x"d443";
when "00" & x"be5" => DATA <= x"4842";
when "00" & x"be6" => DATA <= x"4843";
when "00" & x"be7" => DATA <= x"3403";
when "00" & x"be8" => DATA <= x"5381";
when "00" & x"be9" => DATA <= x"66e6";
when "00" & x"bea" => DATA <= x"4280";
when "00" & x"beb" => DATA <= x"be82";
when "00" & x"bec" => DATA <= x"6500";
when "00" & x"bed" => DATA <= x"0008";
when "00" & x"bee" => DATA <= x"5280";
when "00" & x"bef" => DATA <= x"9e82";
when "00" & x"bf0" => DATA <= x"60f4";
when "00" & x"bf1" => DATA <= x"4a00";
when "00" & x"bf2" => DATA <= x"6600";
when "00" & x"bf3" => DATA <= x"0008";
when "00" & x"bf4" => DATA <= x"4a44";
when "00" & x"bf5" => DATA <= x"6700";
when "00" & x"bf6" => DATA <= x"000a";
when "00" & x"bf7" => DATA <= x"0600";
when "00" & x"bf8" => DATA <= x"0030";
when "00" & x"bf9" => DATA <= x"1ac0";
when "00" & x"bfa" => DATA <= x"1800";
when "00" & x"bfb" => DATA <= x"5386";
when "00" & x"bfc" => DATA <= x"66b6";
when "00" & x"bfd" => DATA <= x"4a44";
when "00" & x"bfe" => DATA <= x"6600";
when "00" & x"bff" => DATA <= x"0006";
when "00" & x"c00" => DATA <= x"1afc";
when "00" & x"c01" => DATA <= x"0030";
when "00" & x"c02" => DATA <= x"1abc";
when "00" & x"c03" => DATA <= x"0000";
when "00" & x"c04" => DATA <= x"4cdf";
when "00" & x"c05" => DATA <= x"00ff";
when "00" & x"c06" => DATA <= x"c38d";
when "00" & x"c07" => DATA <= x"023c";
when "00" & x"c08" => DATA <= x"00fd";
when "00" & x"c09" => DATA <= x"4e75";
when "00" & x"c0a" => DATA <= x"b4bc";
when "00" & x"c0b" => DATA <= x"0000";
when "00" & x"c0c" => DATA <= x"0005";
when "00" & x"c0d" => DATA <= x"6500";
when "00" & x"c0e" => DATA <= x"02e8";
when "00" & x"c0f" => DATA <= x"b0bc";
when "00" & x"c10" => DATA <= x"0000";
when "00" & x"c11" => DATA <= x"0100";
when "00" & x"c12" => DATA <= x"6400";
when "00" & x"c13" => DATA <= x"00e2";
when "00" & x"c14" => DATA <= x"0800";
when "00" & x"c15" => DATA <= x"0007";
when "00" & x"c16" => DATA <= x"6700";
when "00" & x"c17" => DATA <= x"0008";
when "00" & x"c18" => DATA <= x"0080";
when "00" & x"c19" => DATA <= x"ffff";
when "00" & x"c1a" => DATA <= x"ff00";
when "00" & x"c1b" => DATA <= x"7c03";
when "00" & x"c1c" => DATA <= x"6000";
when "00" & x"c1d" => DATA <= x"005e";
when "00" & x"c1e" => DATA <= x"b4bc";
when "00" & x"c1f" => DATA <= x"0000";
when "00" & x"c20" => DATA <= x"0007";
when "00" & x"c21" => DATA <= x"6500";
when "00" & x"c22" => DATA <= x"02c0";
when "00" & x"c23" => DATA <= x"b0bc";
when "00" & x"c24" => DATA <= x"0001";
when "00" & x"c25" => DATA <= x"0000";
when "00" & x"c26" => DATA <= x"6400";
when "00" & x"c27" => DATA <= x"00ba";
when "00" & x"c28" => DATA <= x"0800";
when "00" & x"c29" => DATA <= x"000f";
when "00" & x"c2a" => DATA <= x"6700";
when "00" & x"c2b" => DATA <= x"0008";
when "00" & x"c2c" => DATA <= x"0080";
when "00" & x"c2d" => DATA <= x"ffff";
when "00" & x"c2e" => DATA <= x"0000";
when "00" & x"c2f" => DATA <= x"7c05";
when "00" & x"c30" => DATA <= x"6000";
when "00" & x"c31" => DATA <= x"0036";
when "00" & x"c32" => DATA <= x"b4bc";
when "00" & x"c33" => DATA <= x"0000";
when "00" & x"c34" => DATA <= x"000b";
when "00" & x"c35" => DATA <= x"6500";
when "00" & x"c36" => DATA <= x"0298";
when "00" & x"c37" => DATA <= x"b0bc";
when "00" & x"c38" => DATA <= x"0100";
when "00" & x"c39" => DATA <= x"0000";
when "00" & x"c3a" => DATA <= x"6400";
when "00" & x"c3b" => DATA <= x"0092";
when "00" & x"c3c" => DATA <= x"0800";
when "00" & x"c3d" => DATA <= x"0017";
when "00" & x"c3e" => DATA <= x"6700";
when "00" & x"c3f" => DATA <= x"0008";
when "00" & x"c40" => DATA <= x"0080";
when "00" & x"c41" => DATA <= x"ff00";
when "00" & x"c42" => DATA <= x"0000";
when "00" & x"c43" => DATA <= x"7c08";
when "00" & x"c44" => DATA <= x"6000";
when "00" & x"c45" => DATA <= x"000e";
when "00" & x"c46" => DATA <= x"b4bc";
when "00" & x"c47" => DATA <= x"0000";
when "00" & x"c48" => DATA <= x"000d";
when "00" & x"c49" => DATA <= x"6500";
when "00" & x"c4a" => DATA <= x"0270";
when "00" & x"c4b" => DATA <= x"7c0a";
when "00" & x"c4c" => DATA <= x"c38d";
when "00" & x"c4d" => DATA <= x"48e7";
when "00" & x"c4e" => DATA <= x"ff00";
when "00" & x"c4f" => DATA <= x"2e00";
when "00" & x"c50" => DATA <= x"6a08";
when "00" & x"c51" => DATA <= x"4487";
when "00" & x"c52" => DATA <= x"6b4e";
when "00" & x"c53" => DATA <= x"1afc";
when "00" & x"c54" => DATA <= x"002d";
when "00" & x"c55" => DATA <= x"4244";
when "00" & x"c56" => DATA <= x"7a01";
when "00" & x"c57" => DATA <= x"2206";
when "00" & x"c58" => DATA <= x"5381";
when "00" & x"c59" => DATA <= x"671a";
when "00" & x"c5a" => DATA <= x"3605";
when "00" & x"c5b" => DATA <= x"c6fc";
when "00" & x"c5c" => DATA <= x"000a";
when "00" & x"c5d" => DATA <= x"4845";
when "00" & x"c5e" => DATA <= x"cafc";
when "00" & x"c5f" => DATA <= x"000a";
when "00" & x"c60" => DATA <= x"4843";
when "00" & x"c61" => DATA <= x"da43";
when "00" & x"c62" => DATA <= x"4845";
when "00" & x"c63" => DATA <= x"4843";
when "00" & x"c64" => DATA <= x"3a03";
when "00" & x"c65" => DATA <= x"5381";
when "00" & x"c66" => DATA <= x"66e6";
when "00" & x"c67" => DATA <= x"4280";
when "00" & x"c68" => DATA <= x"be85";
when "00" & x"c69" => DATA <= x"6d06";
when "00" & x"c6a" => DATA <= x"5280";
when "00" & x"c6b" => DATA <= x"9e85";
when "00" & x"c6c" => DATA <= x"60f6";
when "00" & x"c6d" => DATA <= x"4a00";
when "00" & x"c6e" => DATA <= x"6604";
when "00" & x"c6f" => DATA <= x"4a44";
when "00" & x"c70" => DATA <= x"6708";
when "00" & x"c71" => DATA <= x"0600";
when "00" & x"c72" => DATA <= x"0030";
when "00" & x"c73" => DATA <= x"1ac0";
when "00" & x"c74" => DATA <= x"1800";
when "00" & x"c75" => DATA <= x"5386";
when "00" & x"c76" => DATA <= x"66be";
when "00" & x"c77" => DATA <= x"4a44";
when "00" & x"c78" => DATA <= x"6600";
when "00" & x"c79" => DATA <= x"0006";
when "00" & x"c7a" => DATA <= x"1afc";
when "00" & x"c7b" => DATA <= x"0030";
when "00" & x"c7c" => DATA <= x"1abc";
when "00" & x"c7d" => DATA <= x"0000";
when "00" & x"c7e" => DATA <= x"4cdf";
when "00" & x"c7f" => DATA <= x"00ff";
when "00" & x"c80" => DATA <= x"c38d";
when "00" & x"c81" => DATA <= x"023c";
when "00" & x"c82" => DATA <= x"00fd";
when "00" & x"c83" => DATA <= x"4e75";
when "00" & x"c84" => DATA <= x"003c";
when "00" & x"c85" => DATA <= x"0002";
when "00" & x"c86" => DATA <= x"4e75";
when "00" & x"c87" => DATA <= x"b4bc";
when "00" & x"c88" => DATA <= x"0000";
when "00" & x"c89" => DATA <= x"0009";
when "00" & x"c8a" => DATA <= x"6f00";
when "00" & x"c8b" => DATA <= x"01ee";
when "00" & x"c8c" => DATA <= x"0482";
when "00" & x"c8d" => DATA <= x"0000";
when "00" & x"c8e" => DATA <= x"0009";
when "00" & x"c8f" => DATA <= x"2f0e";
when "00" & x"c90" => DATA <= x"48e7";
when "00" & x"c91" => DATA <= x"7000";
when "00" & x"c92" => DATA <= x"7407";
when "00" & x"c93" => DATA <= x"e098";
when "00" & x"c94" => DATA <= x"6000";
when "00" & x"c95" => DATA <= x"0058";
when "00" & x"c96" => DATA <= x"b4bc";
when "00" & x"c97" => DATA <= x"0000";
when "00" & x"c98" => DATA <= x"0011";
when "00" & x"c99" => DATA <= x"6f00";
when "00" & x"c9a" => DATA <= x"01d0";
when "00" & x"c9b" => DATA <= x"0482";
when "00" & x"c9c" => DATA <= x"0000";
when "00" & x"c9d" => DATA <= x"0011";
when "00" & x"c9e" => DATA <= x"2f0e";
when "00" & x"c9f" => DATA <= x"48e7";
when "00" & x"ca0" => DATA <= x"7000";
when "00" & x"ca1" => DATA <= x"740f";
when "00" & x"ca2" => DATA <= x"e198";
when "00" & x"ca3" => DATA <= x"e198";
when "00" & x"ca4" => DATA <= x"6000";
when "00" & x"ca5" => DATA <= x"0038";
when "00" & x"ca6" => DATA <= x"b4bc";
when "00" & x"ca7" => DATA <= x"0000";
when "00" & x"ca8" => DATA <= x"0019";
when "00" & x"ca9" => DATA <= x"6f00";
when "00" & x"caa" => DATA <= x"01b0";
when "00" & x"cab" => DATA <= x"0482";
when "00" & x"cac" => DATA <= x"0000";
when "00" & x"cad" => DATA <= x"0019";
when "00" & x"cae" => DATA <= x"2f0e";
when "00" & x"caf" => DATA <= x"48e7";
when "00" & x"cb0" => DATA <= x"7000";
when "00" & x"cb1" => DATA <= x"7417";
when "00" & x"cb2" => DATA <= x"e098";
when "00" & x"cb3" => DATA <= x"6000";
when "00" & x"cb4" => DATA <= x"001a";
when "00" & x"cb5" => DATA <= x"b4bc";
when "00" & x"cb6" => DATA <= x"0000";
when "00" & x"cb7" => DATA <= x"0021";
when "00" & x"cb8" => DATA <= x"6f00";
when "00" & x"cb9" => DATA <= x"0192";
when "00" & x"cba" => DATA <= x"0482";
when "00" & x"cbb" => DATA <= x"0000";
when "00" & x"cbc" => DATA <= x"0021";
when "00" & x"cbd" => DATA <= x"2f0e";
when "00" & x"cbe" => DATA <= x"48e7";
when "00" & x"cbf" => DATA <= x"7000";
when "00" & x"cc0" => DATA <= x"741f";
when "00" & x"cc1" => DATA <= x"2c41";
when "00" & x"cc2" => DATA <= x"7600";
when "00" & x"cc3" => DATA <= x"7230";
when "00" & x"cc4" => DATA <= x"e380";
when "00" & x"cc5" => DATA <= x"c303";
when "00" & x"cc6" => DATA <= x"1cc1";
when "00" & x"cc7" => DATA <= x"51ca";
when "00" & x"cc8" => DATA <= x"fff6";
when "00" & x"cc9" => DATA <= x"1cbc";
when "00" & x"cca" => DATA <= x"0000";
when "00" & x"ccb" => DATA <= x"4cdf";
when "00" & x"ccc" => DATA <= x"000e";
when "00" & x"ccd" => DATA <= x"2001";
when "00" & x"cce" => DATA <= x"220e";
when "00" & x"ccf" => DATA <= x"2c5f";
when "00" & x"cd0" => DATA <= x"023c";
when "00" & x"cd1" => DATA <= x"00fd";
when "00" & x"cd2" => DATA <= x"4e75";
when "00" & x"cd3" => DATA <= x"6100";
when "00" & x"cd4" => DATA <= x"fe6c";
when "00" & x"cd5" => DATA <= x"2f07";
when "00" & x"cd6" => DATA <= x"7e05";
when "00" & x"cd7" => DATA <= x"6100";
when "00" & x"cd8" => DATA <= x"0122";
when "00" & x"cd9" => DATA <= x"2e1f";
when "00" & x"cda" => DATA <= x"4e75";
when "00" & x"cdb" => DATA <= x"6100";
when "00" & x"cdc" => DATA <= x"fe84";
when "00" & x"cdd" => DATA <= x"2f07";
when "00" & x"cde" => DATA <= x"7e07";
when "00" & x"cdf" => DATA <= x"6100";
when "00" & x"ce0" => DATA <= x"0112";
when "00" & x"ce1" => DATA <= x"2e1f";
when "00" & x"ce2" => DATA <= x"4e75";
when "00" & x"ce3" => DATA <= x"6100";
when "00" & x"ce4" => DATA <= x"fe9c";
when "00" & x"ce5" => DATA <= x"2f07";
when "00" & x"ce6" => DATA <= x"7e09";
when "00" & x"ce7" => DATA <= x"6100";
when "00" & x"ce8" => DATA <= x"0102";
when "00" & x"ce9" => DATA <= x"2e1f";
when "00" & x"cea" => DATA <= x"4e75";
when "00" & x"ceb" => DATA <= x"6100";
when "00" & x"cec" => DATA <= x"feb4";
when "00" & x"ced" => DATA <= x"2f07";
when "00" & x"cee" => DATA <= x"7e0c";
when "00" & x"cef" => DATA <= x"6100";
when "00" & x"cf0" => DATA <= x"00f2";
when "00" & x"cf1" => DATA <= x"2e1f";
when "00" & x"cf2" => DATA <= x"4e75";
when "00" & x"cf3" => DATA <= x"2f01";
when "00" & x"cf4" => DATA <= x"2f06";
when "00" & x"cf5" => DATA <= x"2f07";
when "00" & x"cf6" => DATA <= x"2f0e";
when "00" & x"cf7" => DATA <= x"2c40";
when "00" & x"cf8" => DATA <= x"2c1e";
when "00" & x"cf9" => DATA <= x"2e1e";
when "00" & x"cfa" => DATA <= x"0c87";
when "00" & x"cfb" => DATA <= x"0000";
when "00" & x"cfc" => DATA <= x"0100";
when "00" & x"cfd" => DATA <= x"6400";
when "00" & x"cfe" => DATA <= x"003a";
when "00" & x"cff" => DATA <= x"0c86";
when "00" & x"d00" => DATA <= x"0000";
when "00" & x"d01" => DATA <= x"0100";
when "00" & x"d02" => DATA <= x"6400";
when "00" & x"d03" => DATA <= x"003e";
when "00" & x"d04" => DATA <= x"4a47";
when "00" & x"d05" => DATA <= x"6700";
when "00" & x"d06" => DATA <= x"0016";
when "00" & x"d07" => DATA <= x"1007";
when "00" & x"d08" => DATA <= x"6100";
when "00" & x"d09" => DATA <= x"fd32";
when "00" & x"d0a" => DATA <= x"4a41";
when "00" & x"d0b" => DATA <= x"6700";
when "00" & x"d0c" => DATA <= x"00ec";
when "00" & x"d0d" => DATA <= x"2c41";
when "00" & x"d0e" => DATA <= x"1cfc";
when "00" & x"d0f" => DATA <= x"002e";
when "00" & x"d10" => DATA <= x"220e";
when "00" & x"d11" => DATA <= x"1006";
when "00" & x"d12" => DATA <= x"6100";
when "00" & x"d13" => DATA <= x"fd1e";
when "00" & x"d14" => DATA <= x"2c5f";
when "00" & x"d15" => DATA <= x"2e1f";
when "00" & x"d16" => DATA <= x"2c1f";
when "00" & x"d17" => DATA <= x"201f";
when "00" & x"d18" => DATA <= x"023c";
when "00" & x"d19" => DATA <= x"00fd";
when "00" & x"d1a" => DATA <= x"4e75";
when "00" & x"d1b" => DATA <= x"2f7c";
when "00" & x"d1c" => DATA <= x"003f";
when "00" & x"d1d" => DATA <= x"2ee0";
when "00" & x"d1e" => DATA <= x"000c";
when "00" & x"d1f" => DATA <= x"003c";
when "00" & x"d20" => DATA <= x"0002";
when "00" & x"d21" => DATA <= x"60e4";
when "00" & x"d22" => DATA <= x"2f7c";
when "00" & x"d23" => DATA <= x"003f";
when "00" & x"d24" => DATA <= x"2ec8";
when "00" & x"d25" => DATA <= x"000c";
when "00" & x"d26" => DATA <= x"003c";
when "00" & x"d27" => DATA <= x"0002";
when "00" & x"d28" => DATA <= x"60d6";
when "00" & x"d29" => DATA <= x"2f07";
when "00" & x"d2a" => DATA <= x"2f01";
when "00" & x"d2b" => DATA <= x"2200";
when "00" & x"d2c" => DATA <= x"0281";
when "00" & x"d2d" => DATA <= x"c000";
when "00" & x"d2e" => DATA <= x"0000";
when "00" & x"d2f" => DATA <= x"6700";
when "00" & x"d30" => DATA <= x"0014";
when "00" & x"d31" => DATA <= x"e089";
when "00" & x"d32" => DATA <= x"e089";
when "00" & x"d33" => DATA <= x"e089";
when "00" & x"d34" => DATA <= x"ec89";
when "00" & x"d35" => DATA <= x"2001";
when "00" & x"d36" => DATA <= x"1e38";
when "00" & x"d37" => DATA <= x"004d";
when "00" & x"d38" => DATA <= x"6000";
when "00" & x"d39" => DATA <= x"0034";
when "00" & x"d3a" => DATA <= x"2200";
when "00" & x"d3b" => DATA <= x"0281";
when "00" & x"d3c" => DATA <= x"fff0";
when "00" & x"d3d" => DATA <= x"0000";
when "00" & x"d3e" => DATA <= x"6700";
when "00" & x"d3f" => DATA <= x"0012";
when "00" & x"d40" => DATA <= x"e089";
when "00" & x"d41" => DATA <= x"e089";
when "00" & x"d42" => DATA <= x"e889";
when "00" & x"d43" => DATA <= x"2001";
when "00" & x"d44" => DATA <= x"1e38";
when "00" & x"d45" => DATA <= x"004b";
when "00" & x"d46" => DATA <= x"6000";
when "00" & x"d47" => DATA <= x"0018";
when "00" & x"d48" => DATA <= x"2200";
when "00" & x"d49" => DATA <= x"0281";
when "00" & x"d4a" => DATA <= x"ffff";
when "00" & x"d4b" => DATA <= x"fc00";
when "00" & x"d4c" => DATA <= x"6700";
when "00" & x"d4d" => DATA <= x"000c";
when "00" & x"d4e" => DATA <= x"e089";
when "00" & x"d4f" => DATA <= x"e489";
when "00" & x"d50" => DATA <= x"2001";
when "00" & x"d51" => DATA <= x"1e3c";
when "00" & x"d52" => DATA <= x"0000";
when "00" & x"d53" => DATA <= x"221f";
when "00" & x"d54" => DATA <= x"6100";
when "00" & x"d55" => DATA <= x"fce8";
when "00" & x"d56" => DATA <= x"2c41";
when "00" & x"d57" => DATA <= x"1cfc";
when "00" & x"d58" => DATA <= x"0020";
when "00" & x"d59" => DATA <= x"1cc7";
when "00" & x"d5a" => DATA <= x"1cfc";
when "00" & x"d5b" => DATA <= x"0062";
when "00" & x"d5c" => DATA <= x"1cfc";
when "00" & x"d5d" => DATA <= x"0079";
when "00" & x"d5e" => DATA <= x"1cfc";
when "00" & x"d5f" => DATA <= x"0074";
when "00" & x"d60" => DATA <= x"1cfc";
when "00" & x"d61" => DATA <= x"0065";
when "00" & x"d62" => DATA <= x"1cfc";
when "00" & x"d63" => DATA <= x"0073";
when "00" & x"d64" => DATA <= x"1cfc";
when "00" & x"d65" => DATA <= x"0000";
when "00" & x"d66" => DATA <= x"023c";
when "00" & x"d67" => DATA <= x"00fd";
when "00" & x"d68" => DATA <= x"4e75";
when "00" & x"d69" => DATA <= x"2f0e";
when "00" & x"d6a" => DATA <= x"2f00";
when "00" & x"d6b" => DATA <= x"2f01";
when "00" & x"d6c" => DATA <= x"2c40";
when "00" & x"d6d" => DATA <= x"9280";
when "00" & x"d6e" => DATA <= x"1dbc";
when "00" & x"d6f" => DATA <= x"0000";
when "00" & x"d70" => DATA <= x"7000";
when "00" & x"d71" => DATA <= x"5387";
when "00" & x"d72" => DATA <= x"1db6";
when "00" & x"d73" => DATA <= x"1000";
when "00" & x"d74" => DATA <= x"7000";
when "00" & x"d75" => DATA <= x"5387";
when "00" & x"d76" => DATA <= x"51c9";
when "00" & x"d77" => DATA <= x"fff6";
when "00" & x"d78" => DATA <= x"9487";
when "00" & x"d79" => DATA <= x"1dbc";
when "00" & x"d7a" => DATA <= x"0020";
when "00" & x"d7b" => DATA <= x"7000";
when "00" & x"d7c" => DATA <= x"51cf";
when "00" & x"d7d" => DATA <= x"fff8";
when "00" & x"d7e" => DATA <= x"201f";
when "00" & x"d7f" => DATA <= x"221f";
when "00" & x"d80" => DATA <= x"2c5f";
when "00" & x"d81" => DATA <= x"4e75";
when "00" & x"d82" => DATA <= x"203c";
when "00" & x"d83" => DATA <= x"003f";
when "00" & x"d84" => DATA <= x"2e84";
when "00" & x"d85" => DATA <= x"003c";
when "00" & x"d86" => DATA <= x"0002";
when "00" & x"d87" => DATA <= x"4e75";
when "00" & x"d88" => DATA <= x"2f03";
when "00" & x"d89" => DATA <= x"2f00";
when "00" & x"d8a" => DATA <= x"0280";
when "00" & x"d8b" => DATA <= x"0000";
when "00" & x"d8c" => DATA <= x"0001";
when "00" & x"d8d" => DATA <= x"6600";
when "00" & x"d8e" => DATA <= x"002c";
when "00" & x"d8f" => DATA <= x"201f";
when "00" & x"d90" => DATA <= x"c188";
when "00" & x"d91" => DATA <= x"c389";
when "00" & x"d92" => DATA <= x"2c7c";
when "00" & x"d93" => DATA <= x"003f";
when "00" & x"d94" => DATA <= x"39e4";
when "00" & x"d95" => DATA <= x"3610";
when "00" & x"d96" => DATA <= x"c66e";
when "00" & x"d97" => DATA <= x"0002";
when "00" & x"d98" => DATA <= x"b656";
when "00" & x"d99" => DATA <= x"6700";
when "00" & x"d9a" => DATA <= x"000a";
when "00" & x"d9b" => DATA <= x"ddfc";
when "00" & x"d9c" => DATA <= x"0000";
when "00" & x"d9d" => DATA <= x"000e";
when "00" & x"d9e" => DATA <= x"60ec";
when "00" & x"d9f" => DATA <= x"588e";
when "00" & x"da0" => DATA <= x"12de";
when "00" & x"da1" => DATA <= x"66fc";
when "00" & x"da2" => DATA <= x"261f";
when "00" & x"da3" => DATA <= x"4e75";
when "00" & x"da4" => DATA <= x"261f";
when "00" & x"da5" => DATA <= x"203c";
when "00" & x"da6" => DATA <= x"003f";
when "00" & x"da7" => DATA <= x"2f10";
when "00" & x"da8" => DATA <= x"003c";
when "00" & x"da9" => DATA <= x"0002";
when "00" & x"daa" => DATA <= x"4e75";
when "00" & x"dab" => DATA <= x"0c16";
when "00" & x"dac" => DATA <= x"000d";
when "00" & x"dad" => DATA <= x"6700";
when "00" & x"dae" => DATA <= x"004c";
when "00" & x"daf" => DATA <= x"2f0e";
when "00" & x"db0" => DATA <= x"7010";
when "00" & x"db1" => DATA <= x"220e";
when "00" & x"db2" => DATA <= x"6100";
when "00" & x"db3" => DATA <= x"f46a";
when "00" & x"db4" => DATA <= x"6800";
when "00" & x"db5" => DATA <= x"0010";
when "00" & x"db6" => DATA <= x"21fc";
when "00" & x"db7" => DATA <= x"0000";
when "00" & x"db8" => DATA <= x"0000";
when "00" & x"db9" => DATA <= x"0700";
when "00" & x"dba" => DATA <= x"2c5f";
when "00" & x"dbb" => DATA <= x"6000";
when "00" & x"dbc" => DATA <= x"000a";
when "00" & x"dbd" => DATA <= x"2c41";
when "00" & x"dbe" => DATA <= x"21c2";
when "00" & x"dbf" => DATA <= x"0700";
when "00" & x"dc0" => DATA <= x"241f";
when "00" & x"dc1" => DATA <= x"6100";
when "00" & x"dc2" => DATA <= x"0ba0";
when "00" & x"dc3" => DATA <= x"6500";
when "00" & x"dc4" => DATA <= x"0020";
when "00" & x"dc5" => DATA <= x"2a7c";
when "00" & x"dc6" => DATA <= x"0000";
when "00" & x"dc7" => DATA <= x"0704";
when "00" & x"dc8" => DATA <= x"1a9e";
when "00" & x"dc9" => DATA <= x"0c1d";
when "00" & x"dca" => DATA <= x"000d";
when "00" & x"dcb" => DATA <= x"66f8";
when "00" & x"dcc" => DATA <= x"1b3c";
when "00" & x"dcd" => DATA <= x"0000";
when "00" & x"dce" => DATA <= x"203c";
when "00" & x"dcf" => DATA <= x"0000";
when "00" & x"dd0" => DATA <= x"0700";
when "00" & x"dd1" => DATA <= x"6100";
when "00" & x"dd2" => DATA <= x"f580";
when "00" & x"dd3" => DATA <= x"4e75";
when "00" & x"dd4" => DATA <= x"203c";
when "00" & x"dd5" => DATA <= x"003f";
when "00" & x"dd6" => DATA <= x"28fc";
when "00" & x"dd7" => DATA <= x"6100";
when "00" & x"dd8" => DATA <= x"ee52";
when "00" & x"dd9" => DATA <= x"4e75";
when "00" & x"dda" => DATA <= x"2f0e";
when "00" & x"ddb" => DATA <= x"6100";
when "00" & x"ddc" => DATA <= x"0b6c";
when "00" & x"ddd" => DATA <= x"0c16";
when "00" & x"dde" => DATA <= x"000d";
when "00" & x"ddf" => DATA <= x"6700";
when "00" & x"de0" => DATA <= x"0010";
when "00" & x"de1" => DATA <= x"0c16";
when "00" & x"de2" => DATA <= x"000d";
when "00" & x"de3" => DATA <= x"6700";
when "00" & x"de4" => DATA <= x"0016";
when "00" & x"de5" => DATA <= x"0c1e";
when "00" & x"de6" => DATA <= x"0020";
when "00" & x"de7" => DATA <= x"66f2";
when "00" & x"de8" => DATA <= x"203c";
when "00" & x"de9" => DATA <= x"003f";
when "00" & x"dea" => DATA <= x"2c02";
when "00" & x"deb" => DATA <= x"6100";
when "00" & x"dec" => DATA <= x"ee2a";
when "00" & x"ded" => DATA <= x"2c5f";
when "00" & x"dee" => DATA <= x"4e75";
when "00" & x"def" => DATA <= x"2c5f";
when "00" & x"df0" => DATA <= x"220e";
when "00" & x"df1" => DATA <= x"7005";
when "00" & x"df2" => DATA <= x"6100";
when "00" & x"df3" => DATA <= x"f0e8";
when "00" & x"df4" => DATA <= x"b8bc";
when "00" & x"df5" => DATA <= x"0000";
when "00" & x"df6" => DATA <= x"8000";
when "00" & x"df7" => DATA <= x"6600";
when "00" & x"df8" => DATA <= x"0078";
when "00" & x"df9" => DATA <= x"2a78";
when "00" & x"dfa" => DATA <= x"0504";
when "00" & x"dfb" => DATA <= x"dbfc";
when "00" & x"dfc" => DATA <= x"0000";
when "00" & x"dfd" => DATA <= x"8000";
when "00" & x"dfe" => DATA <= x"dbfc";
when "00" & x"dff" => DATA <= x"0000";
when "00" & x"e00" => DATA <= x"0100";
when "00" & x"e01" => DATA <= x"bbf8";
when "00" & x"e02" => DATA <= x"0508";
when "00" & x"e03" => DATA <= x"6300";
when "00" & x"e04" => DATA <= x"006c";
when "00" & x"e05" => DATA <= x"220e";
when "00" & x"e06" => DATA <= x"243c";
when "00" & x"e07" => DATA <= x"0000";
when "00" & x"e08" => DATA <= x"0400";
when "00" & x"e09" => DATA <= x"7600";
when "00" & x"e0a" => DATA <= x"203c";
when "00" & x"e0b" => DATA <= x"0000";
when "00" & x"e0c" => DATA <= x"00ff";
when "00" & x"e0d" => DATA <= x"6100";
when "00" & x"e0e" => DATA <= x"f0b2";
when "00" & x"e0f" => DATA <= x"203c";
when "00" & x"e10" => DATA <= x"003f";
when "00" & x"e11" => DATA <= x"2b61";
when "00" & x"e12" => DATA <= x"6100";
when "00" & x"e13" => DATA <= x"eddc";
when "00" & x"e14" => DATA <= x"7015";
when "00" & x"e15" => DATA <= x"7200";
when "00" & x"e16" => DATA <= x"6100";
when "00" & x"e17" => DATA <= x"eea8";
when "00" & x"e18" => DATA <= x"6100";
when "00" & x"e19" => DATA <= x"f86c";
when "00" & x"e1a" => DATA <= x"6100";
when "00" & x"e1b" => DATA <= x"edb4";
when "00" & x"e1c" => DATA <= x"66a0";
when "00" & x"e1d" => DATA <= x"223c";
when "00" & x"e1e" => DATA <= x"0000";
when "00" & x"e1f" => DATA <= x"0600";
when "00" & x"e20" => DATA <= x"74ff";
when "00" & x"e21" => DATA <= x"203c";
when "00" & x"e22" => DATA <= x"003f";
when "00" & x"e23" => DATA <= x"2bce";
when "00" & x"e24" => DATA <= x"6100";
when "00" & x"e25" => DATA <= x"edb8";
when "00" & x"e26" => DATA <= x"1007";
when "00" & x"e27" => DATA <= x"0600";
when "00" & x"e28" => DATA <= x"0030";
when "00" & x"e29" => DATA <= x"6100";
when "00" & x"e2a" => DATA <= x"ed96";
when "00" & x"e2b" => DATA <= x"6100";
when "00" & x"e2c" => DATA <= x"edbe";
when "00" & x"e2d" => DATA <= x"203c";
when "00" & x"e2e" => DATA <= x"003f";
when "00" & x"e2f" => DATA <= x"2be3";
when "00" & x"e30" => DATA <= x"6100";
when "00" & x"e31" => DATA <= x"eda0";
when "00" & x"e32" => DATA <= x"6000";
when "00" & x"e33" => DATA <= x"ff74";
when "00" & x"e34" => DATA <= x"203c";
when "00" & x"e35" => DATA <= x"003f";
when "00" & x"e36" => DATA <= x"2b3b";
when "00" & x"e37" => DATA <= x"6100";
when "00" & x"e38" => DATA <= x"ed92";
when "00" & x"e39" => DATA <= x"4e75";
when "00" & x"e3a" => DATA <= x"203c";
when "00" & x"e3b" => DATA <= x"003f";
when "00" & x"e3c" => DATA <= x"2b57";
when "00" & x"e3d" => DATA <= x"6100";
when "00" & x"e3e" => DATA <= x"ed86";
when "00" & x"e3f" => DATA <= x"4e75";
when "00" & x"e40" => DATA <= x"203c";
when "00" & x"e41" => DATA <= x"003f";
when "00" & x"e42" => DATA <= x"291f";
when "00" & x"e43" => DATA <= x"6100";
when "00" & x"e44" => DATA <= x"ed7a";
when "00" & x"e45" => DATA <= x"4e75";
when "00" & x"e46" => DATA <= x"7010";
when "00" & x"e47" => DATA <= x"220e";
when "00" & x"e48" => DATA <= x"6100";
when "00" & x"e49" => DATA <= x"f33e";
when "00" & x"e4a" => DATA <= x"6900";
when "00" & x"e4b" => DATA <= x"0018";
when "00" & x"e4c" => DATA <= x"6100";
when "00" & x"e4d" => DATA <= x"0a98";
when "00" & x"e4e" => DATA <= x"6600";
when "00" & x"e4f" => DATA <= x"0010";
when "00" & x"e50" => DATA <= x"21c2";
when "00" & x"e51" => DATA <= x"0520";
when "00" & x"e52" => DATA <= x"6100";
when "00" & x"e53" => DATA <= x"eee2";
when "00" & x"e54" => DATA <= x"023c";
when "00" & x"e55" => DATA <= x"00fe";
when "00" & x"e56" => DATA <= x"4e75";
when "00" & x"e57" => DATA <= x"203c";
when "00" & x"e58" => DATA <= x"003f";
when "00" & x"e59" => DATA <= x"2935";
when "00" & x"e5a" => DATA <= x"6100";
when "00" & x"e5b" => DATA <= x"ed4c";
when "00" & x"e5c" => DATA <= x"4e75";
when "00" & x"e5d" => DATA <= x"2f0e";
when "00" & x"e5e" => DATA <= x"0c16";
when "00" & x"e5f" => DATA <= x"000d";
when "00" & x"e60" => DATA <= x"6600";
when "00" & x"e61" => DATA <= x"001a";
when "00" & x"e62" => DATA <= x"203c";
when "00" & x"e63" => DATA <= x"003f";
when "00" & x"e64" => DATA <= x"283c";
when "00" & x"e65" => DATA <= x"6100";
when "00" & x"e66" => DATA <= x"ed36";
when "00" & x"e67" => DATA <= x"203c";
when "00" & x"e68" => DATA <= x"003f";
when "00" & x"e69" => DATA <= x"285d";
when "00" & x"e6a" => DATA <= x"6100";
when "00" & x"e6b" => DATA <= x"ed2c";
when "00" & x"e6c" => DATA <= x"6000";
when "00" & x"e6d" => DATA <= x"00ca";
when "00" & x"e6e" => DATA <= x"0216";
when "00" & x"e6f" => DATA <= x"00df";
when "00" & x"e70" => DATA <= x"0c1e";
when "00" & x"e71" => DATA <= x"0054";
when "00" & x"e72" => DATA <= x"6600";
when "00" & x"e73" => DATA <= x"0042";
when "00" & x"e74" => DATA <= x"0216";
when "00" & x"e75" => DATA <= x"00df";
when "00" & x"e76" => DATA <= x"0c1e";
when "00" & x"e77" => DATA <= x"0055";
when "00" & x"e78" => DATA <= x"6600";
when "00" & x"e79" => DATA <= x"00b2";
when "00" & x"e7a" => DATA <= x"0216";
when "00" & x"e7b" => DATA <= x"00df";
when "00" & x"e7c" => DATA <= x"0c1e";
when "00" & x"e7d" => DATA <= x"0042";
when "00" & x"e7e" => DATA <= x"6600";
when "00" & x"e7f" => DATA <= x"00a6";
when "00" & x"e80" => DATA <= x"0216";
when "00" & x"e81" => DATA <= x"00df";
when "00" & x"e82" => DATA <= x"0c1e";
when "00" & x"e83" => DATA <= x"0045";
when "00" & x"e84" => DATA <= x"6600";
when "00" & x"e85" => DATA <= x"009a";
when "00" & x"e86" => DATA <= x"0c16";
when "00" & x"e87" => DATA <= x"000d";
when "00" & x"e88" => DATA <= x"6600";
when "00" & x"e89" => DATA <= x"0092";
when "00" & x"e8a" => DATA <= x"203c";
when "00" & x"e8b" => DATA <= x"003f";
when "00" & x"e8c" => DATA <= x"283c";
when "00" & x"e8d" => DATA <= x"6100";
when "00" & x"e8e" => DATA <= x"ece6";
when "00" & x"e8f" => DATA <= x"203c";
when "00" & x"e90" => DATA <= x"003f";
when "00" & x"e91" => DATA <= x"286f";
when "00" & x"e92" => DATA <= x"6100";
when "00" & x"e93" => DATA <= x"ecdc";
when "00" & x"e94" => DATA <= x"0226";
when "00" & x"e95" => DATA <= x"00df";
when "00" & x"e96" => DATA <= x"0c1e";
when "00" & x"e97" => DATA <= x"0053";
when "00" & x"e98" => DATA <= x"6600";
when "00" & x"e99" => DATA <= x"0072";
when "00" & x"e9a" => DATA <= x"0216";
when "00" & x"e9b" => DATA <= x"00df";
when "00" & x"e9c" => DATA <= x"0c1e";
when "00" & x"e9d" => DATA <= x"0057";
when "00" & x"e9e" => DATA <= x"6600";
when "00" & x"e9f" => DATA <= x"0066";
when "00" & x"ea0" => DATA <= x"0216";
when "00" & x"ea1" => DATA <= x"00df";
when "00" & x"ea2" => DATA <= x"0c1e";
when "00" & x"ea3" => DATA <= x"0049";
when "00" & x"ea4" => DATA <= x"6600";
when "00" & x"ea5" => DATA <= x"005a";
when "00" & x"ea6" => DATA <= x"0c16";
when "00" & x"ea7" => DATA <= x"000d";
when "00" & x"ea8" => DATA <= x"6600";
when "00" & x"ea9" => DATA <= x"0052";
when "00" & x"eaa" => DATA <= x"203c";
when "00" & x"eab" => DATA <= x"003f";
when "00" & x"eac" => DATA <= x"283c";
when "00" & x"ead" => DATA <= x"6100";
when "00" & x"eae" => DATA <= x"eca6";
when "00" & x"eaf" => DATA <= x"4df9";
when "00" & x"eb0" => DATA <= x"003f";
when "00" & x"eb1" => DATA <= x"2f54";
when "00" & x"eb2" => DATA <= x"103c";
when "00" & x"eb3" => DATA <= x"0020";
when "00" & x"eb4" => DATA <= x"6100";
when "00" & x"eb5" => DATA <= x"ec80";
when "00" & x"eb6" => DATA <= x"6100";
when "00" & x"eb7" => DATA <= x"ec7c";
when "00" & x"eb8" => DATA <= x"6100";
when "00" & x"eb9" => DATA <= x"ec78";
when "00" & x"eba" => DATA <= x"201e";
when "00" & x"ebb" => DATA <= x"201e";
when "00" & x"ebc" => DATA <= x"0c80";
when "00" & x"ebd" => DATA <= x"ffff";
when "00" & x"ebe" => DATA <= x"ffff";
when "00" & x"ebf" => DATA <= x"6700";
when "00" & x"ec0" => DATA <= x"0024";
when "00" & x"ec1" => DATA <= x"200e";
when "00" & x"ec2" => DATA <= x"6100";
when "00" & x"ec3" => DATA <= x"ec7c";
when "00" & x"ec4" => DATA <= x"2c40";
when "00" & x"ec5" => DATA <= x"0c26";
when "00" & x"ec6" => DATA <= x"0000";
when "00" & x"ec7" => DATA <= x"6100";
when "00" & x"ec8" => DATA <= x"ec86";
when "00" & x"ec9" => DATA <= x"0c1e";
when "00" & x"eca" => DATA <= x"00ff";
when "00" & x"ecb" => DATA <= x"6700";
when "00" & x"ecc" => DATA <= x"000c";
when "00" & x"ecd" => DATA <= x"200e";
when "00" & x"ece" => DATA <= x"0200";
when "00" & x"ecf" => DATA <= x"0003";
when "00" & x"ed0" => DATA <= x"66f0";
when "00" & x"ed1" => DATA <= x"60c0";
when "00" & x"ed2" => DATA <= x"2f01";
when "00" & x"ed3" => DATA <= x"7209";
when "00" & x"ed4" => DATA <= x"6100";
when "00" & x"ed5" => DATA <= x"f3aa";
when "00" & x"ed6" => DATA <= x"221f";
when "00" & x"ed7" => DATA <= x"2c5f";
when "00" & x"ed8" => DATA <= x"003c";
when "00" & x"ed9" => DATA <= x"0001";
when "00" & x"eda" => DATA <= x"4e75";
when "00" & x"edb" => DATA <= x"0c16";
when "00" & x"edc" => DATA <= x"000d";
when "00" & x"edd" => DATA <= x"6600";
when "00" & x"ede" => DATA <= x"06b8";
when "00" & x"edf" => DATA <= x"203c";
when "00" & x"ee0" => DATA <= x"003f";
when "00" & x"ee1" => DATA <= x"29a3";
when "00" & x"ee2" => DATA <= x"6100";
when "00" & x"ee3" => DATA <= x"ec3c";
when "00" & x"ee4" => DATA <= x"6100";
when "00" & x"ee5" => DATA <= x"ec4c";
when "00" & x"ee6" => DATA <= x"103c";
when "00" & x"ee7" => DATA <= x"003a";
when "00" & x"ee8" => DATA <= x"6100";
when "00" & x"ee9" => DATA <= x"ec18";
when "00" & x"eea" => DATA <= x"203c";
when "00" & x"eeb" => DATA <= x"0000";
when "00" & x"eec" => DATA <= x"0600";
when "00" & x"eed" => DATA <= x"223c";
when "00" & x"eee" => DATA <= x"0000";
when "00" & x"eef" => DATA <= x"00ff";
when "00" & x"ef0" => DATA <= x"143c";
when "00" & x"ef1" => DATA <= x"0020";
when "00" & x"ef2" => DATA <= x"163c";
when "00" & x"ef3" => DATA <= x"00ff";
when "00" & x"ef4" => DATA <= x"207c";
when "00" & x"ef5" => DATA <= x"0000";
when "00" & x"ef6" => DATA <= x"007d";
when "00" & x"ef7" => DATA <= x"4e4c";
when "00" & x"ef8" => DATA <= x"6500";
when "00" & x"ef9" => DATA <= x"00b8";
when "00" & x"efa" => DATA <= x"2c7c";
when "00" & x"efb" => DATA <= x"0000";
when "00" & x"efc" => DATA <= x"0600";
when "00" & x"efd" => DATA <= x"101e";
when "00" & x"efe" => DATA <= x"b03c";
when "00" & x"eff" => DATA <= x"003f";
when "00" & x"f00" => DATA <= x"6700";
when "00" & x"f01" => DATA <= x"02c6";
when "00" & x"f02" => DATA <= x"b03c";
when "00" & x"f03" => DATA <= x"002a";
when "00" & x"f04" => DATA <= x"6700";
when "00" & x"f05" => DATA <= x"03b0";
when "00" & x"f06" => DATA <= x"0200";
when "00" & x"f07" => DATA <= x"00df";
when "00" & x"f08" => DATA <= x"b03c";
when "00" & x"f09" => DATA <= x"0042";
when "00" & x"f0a" => DATA <= x"6700";
when "00" & x"f0b" => DATA <= x"009e";
when "00" & x"f0c" => DATA <= x"b03c";
when "00" & x"f0d" => DATA <= x"0044";
when "00" & x"f0e" => DATA <= x"6700";
when "00" & x"f0f" => DATA <= x"0060";
when "00" & x"f10" => DATA <= x"b03c";
when "00" & x"f11" => DATA <= x"0045";
when "00" & x"f12" => DATA <= x"6700";
when "00" & x"f13" => DATA <= x"00f2";
when "00" & x"f14" => DATA <= x"b03c";
when "00" & x"f15" => DATA <= x"0046";
when "00" & x"f16" => DATA <= x"6700";
when "00" & x"f17" => DATA <= x"019e";
when "00" & x"f18" => DATA <= x"b03c";
when "00" & x"f19" => DATA <= x"0047";
when "00" & x"f1a" => DATA <= x"6700";
when "00" & x"f1b" => DATA <= x"01d0";
when "00" & x"f1c" => DATA <= x"b03c";
when "00" & x"f1d" => DATA <= x"0048";
when "00" & x"f1e" => DATA <= x"6700";
when "00" & x"f1f" => DATA <= x"01e4";
when "00" & x"f20" => DATA <= x"b03c";
when "00" & x"f21" => DATA <= x"004d";
when "00" & x"f22" => DATA <= x"6700";
when "00" & x"f23" => DATA <= x"0290";
when "00" & x"f24" => DATA <= x"b03c";
when "00" & x"f25" => DATA <= x"0051";
when "00" & x"f26" => DATA <= x"6700";
when "00" & x"f27" => DATA <= x"02be";
when "00" & x"f28" => DATA <= x"b03c";
when "00" & x"f29" => DATA <= x"0052";
when "00" & x"f2a" => DATA <= x"6700";
when "00" & x"f2b" => DATA <= x"02bc";
when "00" & x"f2c" => DATA <= x"b03c";
when "00" & x"f2d" => DATA <= x"0053";
when "00" & x"f2e" => DATA <= x"6700";
when "00" & x"f2f" => DATA <= x"0012";
when "00" & x"f30" => DATA <= x"b03c";
when "00" & x"f31" => DATA <= x"0054";
when "00" & x"f32" => DATA <= x"6700";
when "00" & x"f33" => DATA <= x"000a";
when "00" & x"f34" => DATA <= x"b03c";
when "00" & x"f35" => DATA <= x"0056";
when "00" & x"f36" => DATA <= x"6700";
when "00" & x"f37" => DATA <= x"0356";
when "00" & x"f38" => DATA <= x"203c";
when "00" & x"f39" => DATA <= x"003f";
when "00" & x"f3a" => DATA <= x"2b07";
when "00" & x"f3b" => DATA <= x"6100";
when "00" & x"f3c" => DATA <= x"eb8a";
when "00" & x"f3d" => DATA <= x"6000";
when "00" & x"f3e" => DATA <= x"ff4c";
when "00" & x"f3f" => DATA <= x"6100";
when "00" & x"f40" => DATA <= x"08a4";
when "00" & x"f41" => DATA <= x"7010";
when "00" & x"f42" => DATA <= x"220e";
when "00" & x"f43" => DATA <= x"6100";
when "00" & x"f44" => DATA <= x"f148";
when "00" & x"f45" => DATA <= x"6900";
when "00" & x"f46" => DATA <= x"023c";
when "00" & x"f47" => DATA <= x"2c41";
when "00" & x"f48" => DATA <= x"2002";
when "00" & x"f49" => DATA <= x"223c";
when "00" & x"f4a" => DATA <= x"0000";
when "00" & x"f4b" => DATA <= x"0600";
when "00" & x"f4c" => DATA <= x"6100";
when "00" & x"f4d" => DATA <= x"fc76";
when "00" & x"f4e" => DATA <= x"2001";
when "00" & x"f4f" => DATA <= x"6100";
when "00" & x"f50" => DATA <= x"eb62";
when "00" & x"f51" => DATA <= x"6100";
when "00" & x"f52" => DATA <= x"eb72";
when "00" & x"f53" => DATA <= x"6000";
when "00" & x"f54" => DATA <= x"ff20";
when "00" & x"f55" => DATA <= x"707e";
when "00" & x"f56" => DATA <= x"6100";
when "00" & x"f57" => DATA <= x"ec28";
when "00" & x"f58" => DATA <= x"6000";
when "00" & x"f59" => DATA <= x"ff16";
when "00" & x"f5a" => DATA <= x"6100";
when "00" & x"f5b" => DATA <= x"086e";
when "00" & x"f5c" => DATA <= x"7010";
when "00" & x"f5d" => DATA <= x"220e";
when "00" & x"f5e" => DATA <= x"6100";
when "00" & x"f5f" => DATA <= x"f112";
when "00" & x"f60" => DATA <= x"6900";
when "00" & x"f61" => DATA <= x"0206";
when "00" & x"f62" => DATA <= x"2842";
when "00" & x"f63" => DATA <= x"6100";
when "00" & x"f64" => DATA <= x"086a";
when "00" & x"f65" => DATA <= x"7010";
when "00" & x"f66" => DATA <= x"6100";
when "00" & x"f67" => DATA <= x"f102";
when "00" & x"f68" => DATA <= x"6900";
when "00" & x"f69" => DATA <= x"01f6";
when "00" & x"f6a" => DATA <= x"2a42";
when "00" & x"f6b" => DATA <= x"6100";
when "00" & x"f6c" => DATA <= x"085a";
when "00" & x"f6d" => DATA <= x"7010";
when "00" & x"f6e" => DATA <= x"6100";
when "00" & x"f6f" => DATA <= x"f0f2";
when "00" & x"f70" => DATA <= x"6900";
when "00" & x"f71" => DATA <= x"01e6";
when "00" & x"f72" => DATA <= x"2c41";
when "00" & x"f73" => DATA <= x"1e02";
when "00" & x"f74" => DATA <= x"be1c";
when "00" & x"f75" => DATA <= x"6600";
when "00" & x"f76" => DATA <= x"0024";
when "00" & x"f77" => DATA <= x"200c";
when "00" & x"f78" => DATA <= x"223c";
when "00" & x"f79" => DATA <= x"0000";
when "00" & x"f7a" => DATA <= x"0600";
when "00" & x"f7b" => DATA <= x"243c";
when "00" & x"f7c" => DATA <= x"0000";
when "00" & x"f7d" => DATA <= x"00ff";
when "00" & x"f7e" => DATA <= x"6100";
when "00" & x"f7f" => DATA <= x"f7ec";
when "00" & x"f80" => DATA <= x"21fc";
when "00" & x"f81" => DATA <= x"2020";
when "00" & x"f82" => DATA <= x"0000";
when "00" & x"f83" => DATA <= x"0608";
when "00" & x"f84" => DATA <= x"303c";
when "00" & x"f85" => DATA <= x"0600";
when "00" & x"f86" => DATA <= x"6100";
when "00" & x"f87" => DATA <= x"eaf4";
when "00" & x"f88" => DATA <= x"bbcc";
when "00" & x"f89" => DATA <= x"64d4";
when "00" & x"f8a" => DATA <= x"6000";
when "00" & x"f8b" => DATA <= x"feb2";
when "00" & x"f8c" => DATA <= x"6100";
when "00" & x"f8d" => DATA <= x"080a";
when "00" & x"f8e" => DATA <= x"7010";
when "00" & x"f8f" => DATA <= x"220e";
when "00" & x"f90" => DATA <= x"6100";
when "00" & x"f91" => DATA <= x"f0ae";
when "00" & x"f92" => DATA <= x"6900";
when "00" & x"f93" => DATA <= x"01a2";
when "00" & x"f94" => DATA <= x"2842";
when "00" & x"f95" => DATA <= x"11fc";
when "00" & x"f96" => DATA <= x"0020";
when "00" & x"f97" => DATA <= x"0609";
when "00" & x"f98" => DATA <= x"11fc";
when "00" & x"f99" => DATA <= x"0020";
when "00" & x"f9a" => DATA <= x"060d";
when "00" & x"f9b" => DATA <= x"11fc";
when "00" & x"f9c" => DATA <= x"0028";
when "00" & x"f9d" => DATA <= x"060e";
when "00" & x"f9e" => DATA <= x"21fc";
when "00" & x"f9f" => DATA <= x"2920";
when "00" & x"fa0" => DATA <= x"2000";
when "00" & x"fa1" => DATA <= x"0610";
when "00" & x"fa2" => DATA <= x"200c";
when "00" & x"fa3" => DATA <= x"223c";
when "00" & x"fa4" => DATA <= x"0000";
when "00" & x"fa5" => DATA <= x"0600";
when "00" & x"fa6" => DATA <= x"243c";
when "00" & x"fa7" => DATA <= x"0000";
when "00" & x"fa8" => DATA <= x"00ff";
when "00" & x"fa9" => DATA <= x"6100";
when "00" & x"faa" => DATA <= x"f796";
when "00" & x"fab" => DATA <= x"11fc";
when "00" & x"fac" => DATA <= x"0020";
when "00" & x"fad" => DATA <= x"0608";
when "00" & x"fae" => DATA <= x"5441";
when "00" & x"faf" => DATA <= x"1014";
when "00" & x"fb0" => DATA <= x"243c";
when "00" & x"fb1" => DATA <= x"0000";
when "00" & x"fb2" => DATA <= x"00ff";
when "00" & x"fb3" => DATA <= x"6100";
when "00" & x"fb4" => DATA <= x"f72c";
when "00" & x"fb5" => DATA <= x"2a41";
when "00" & x"fb6" => DATA <= x"1afc";
when "00" & x"fb7" => DATA <= x"0020";
when "00" & x"fb8" => DATA <= x"2c4c";
when "00" & x"fb9" => DATA <= x"6100";
when "00" & x"fba" => DATA <= x"084a";
when "00" & x"fbb" => DATA <= x"11c0";
when "00" & x"fbc" => DATA <= x"060f";
when "00" & x"fbd" => DATA <= x"203c";
when "00" & x"fbe" => DATA <= x"0000";
when "00" & x"fbf" => DATA <= x"0600";
when "00" & x"fc0" => DATA <= x"6100";
when "00" & x"fc1" => DATA <= x"ea80";
when "00" & x"fc2" => DATA <= x"203c";
when "00" & x"fc3" => DATA <= x"0000";
when "00" & x"fc4" => DATA <= x"0680";
when "00" & x"fc5" => DATA <= x"7202";
when "00" & x"fc6" => DATA <= x"143c";
when "00" & x"fc7" => DATA <= x"0020";
when "00" & x"fc8" => DATA <= x"163c";
when "00" & x"fc9" => DATA <= x"0046";
when "00" & x"fca" => DATA <= x"207c";
when "00" & x"fcb" => DATA <= x"0000";
when "00" & x"fcc" => DATA <= x"007d";
when "00" & x"fcd" => DATA <= x"4e4c";
when "00" & x"fce" => DATA <= x"6500";
when "00" & x"fcf" => DATA <= x"0024";
when "00" & x"fd0" => DATA <= x"0c38";
when "00" & x"fd1" => DATA <= x"000d";
when "00" & x"fd2" => DATA <= x"0680";
when "00" & x"fd3" => DATA <= x"6600";
when "00" & x"fd4" => DATA <= x"0006";
when "00" & x"fd5" => DATA <= x"524c";
when "00" & x"fd6" => DATA <= x"6096";
when "00" & x"fd7" => DATA <= x"2c7c";
when "00" & x"fd8" => DATA <= x"0000";
when "00" & x"fd9" => DATA <= x"0680";
when "00" & x"fda" => DATA <= x"7010";
when "00" & x"fdb" => DATA <= x"220e";
when "00" & x"fdc" => DATA <= x"6100";
when "00" & x"fdd" => DATA <= x"f016";
when "00" & x"fde" => DATA <= x"6986";
when "00" & x"fdf" => DATA <= x"18c2";
when "00" & x"fe0" => DATA <= x"6082";
when "00" & x"fe1" => DATA <= x"707e";
when "00" & x"fe2" => DATA <= x"6100";
when "00" & x"fe3" => DATA <= x"eb10";
when "00" & x"fe4" => DATA <= x"6000";
when "00" & x"fe5" => DATA <= x"fdfe";
when "00" & x"fe6" => DATA <= x"220e";
when "00" & x"fe7" => DATA <= x"6100";
when "00" & x"fe8" => DATA <= x"0762";
when "00" & x"fe9" => DATA <= x"7010";
when "00" & x"fea" => DATA <= x"6100";
when "00" & x"feb" => DATA <= x"effa";
when "00" & x"fec" => DATA <= x"6900";
when "00" & x"fed" => DATA <= x"00ee";
when "00" & x"fee" => DATA <= x"2842";
when "00" & x"fef" => DATA <= x"6100";
when "00" & x"ff0" => DATA <= x"0752";
when "00" & x"ff1" => DATA <= x"7010";
when "00" & x"ff2" => DATA <= x"6100";
when "00" & x"ff3" => DATA <= x"efea";
when "00" & x"ff4" => DATA <= x"6900";
when "00" & x"ff5" => DATA <= x"00de";
when "00" & x"ff6" => DATA <= x"2a42";
when "00" & x"ff7" => DATA <= x"6100";
when "00" & x"ff8" => DATA <= x"0742";
when "00" & x"ff9" => DATA <= x"7010";
when "00" & x"ffa" => DATA <= x"6100";
when "00" & x"ffb" => DATA <= x"efda";
when "00" & x"ffc" => DATA <= x"6900";
when "00" & x"ffd" => DATA <= x"00ce";
when "00" & x"ffe" => DATA <= x"18c2";
when "00" & x"fff" => DATA <= x"bbcc";
when "01" & x"000" => DATA <= x"64fa";
when "01" & x"001" => DATA <= x"6000";
when "01" & x"002" => DATA <= x"fdc4";
when "01" & x"003" => DATA <= x"6100";
when "01" & x"004" => DATA <= x"071c";
when "01" & x"005" => DATA <= x"6700";
when "01" & x"006" => DATA <= x"00bc";
when "01" & x"007" => DATA <= x"7010";
when "01" & x"008" => DATA <= x"220e";
when "01" & x"009" => DATA <= x"6100";
when "01" & x"00a" => DATA <= x"efbc";
when "01" & x"00b" => DATA <= x"6900";
when "01" & x"00c" => DATA <= x"00b0";
when "01" & x"00d" => DATA <= x"2c42";
when "01" & x"00e" => DATA <= x"4e96";
when "01" & x"00f" => DATA <= x"6000";
when "01" & x"010" => DATA <= x"fda8";
when "01" & x"011" => DATA <= x"6100";
when "01" & x"012" => DATA <= x"0700";
when "01" & x"013" => DATA <= x"0c16";
when "01" & x"014" => DATA <= x"000d";
when "01" & x"015" => DATA <= x"6600";
when "01" & x"016" => DATA <= x"0008";
when "01" & x"017" => DATA <= x"4282";
when "01" & x"018" => DATA <= x"6000";
when "01" & x"019" => DATA <= x"0016";
when "01" & x"01a" => DATA <= x"7010";
when "01" & x"01b" => DATA <= x"220e";
when "01" & x"01c" => DATA <= x"6100";
when "01" & x"01d" => DATA <= x"ef96";
when "01" & x"01e" => DATA <= x"6900";
when "01" & x"01f" => DATA <= x"008a";
when "01" & x"020" => DATA <= x"6100";
when "01" & x"021" => DATA <= x"06f0";
when "01" & x"022" => DATA <= x"6600";
when "01" & x"023" => DATA <= x"0082";
when "01" & x"024" => DATA <= x"0282";
when "01" & x"025" => DATA <= x"ffff";
when "01" & x"026" => DATA <= x"fffc";
when "01" & x"027" => DATA <= x"2c42";
when "01" & x"028" => DATA <= x"103c";
when "01" & x"029" => DATA <= x"000e";
when "01" & x"02a" => DATA <= x"6100";
when "01" & x"02b" => DATA <= x"e994";
when "01" & x"02c" => DATA <= x"200e";
when "01" & x"02d" => DATA <= x"223c";
when "01" & x"02e" => DATA <= x"0000";
when "01" & x"02f" => DATA <= x"0600";
when "01" & x"030" => DATA <= x"243c";
when "01" & x"031" => DATA <= x"0000";
when "01" & x"032" => DATA <= x"00ff";
when "01" & x"033" => DATA <= x"6100";
when "01" & x"034" => DATA <= x"f682";
when "01" & x"035" => DATA <= x"31fc";
when "01" & x"036" => DATA <= x"2020";
when "01" & x"037" => DATA <= x"0608";
when "01" & x"038" => DATA <= x"5441";
when "01" & x"039" => DATA <= x"760f";
when "01" & x"03a" => DATA <= x"287c";
when "01" & x"03b" => DATA <= x"0000";
when "01" & x"03c" => DATA <= x"063b";
when "01" & x"03d" => DATA <= x"11fc";
when "01" & x"03e" => DATA <= x"0020";
when "01" & x"03f" => DATA <= x"063a";
when "01" & x"040" => DATA <= x"11fc";
when "01" & x"041" => DATA <= x"0000";
when "01" & x"042" => DATA <= x"064b";
when "01" & x"043" => DATA <= x"1016";
when "01" & x"044" => DATA <= x"243c";
when "01" & x"045" => DATA <= x"0000";
when "01" & x"046" => DATA <= x"00ff";
when "01" & x"047" => DATA <= x"6100";
when "01" & x"048" => DATA <= x"f604";
when "01" & x"049" => DATA <= x"2a41";
when "01" & x"04a" => DATA <= x"1abc";
when "01" & x"04b" => DATA <= x"0020";
when "01" & x"04c" => DATA <= x"5241";
when "01" & x"04d" => DATA <= x"6100";
when "01" & x"04e" => DATA <= x"0722";
when "01" & x"04f" => DATA <= x"18c0";
when "01" & x"050" => DATA <= x"51cb";
when "01" & x"051" => DATA <= x"ffe4";
when "01" & x"052" => DATA <= x"303c";
when "01" & x"053" => DATA <= x"0600";
when "01" & x"054" => DATA <= x"6100";
when "01" & x"055" => DATA <= x"e958";
when "01" & x"056" => DATA <= x"6100";
when "01" & x"057" => DATA <= x"e968";
when "01" & x"058" => DATA <= x"6100";
when "01" & x"059" => DATA <= x"f078";
when "01" & x"05a" => DATA <= x"64a2";
when "01" & x"05b" => DATA <= x"707e";
when "01" & x"05c" => DATA <= x"6100";
when "01" & x"05d" => DATA <= x"ea1c";
when "01" & x"05e" => DATA <= x"103c";
when "01" & x"05f" => DATA <= x"000f";
when "01" & x"060" => DATA <= x"6100";
when "01" & x"061" => DATA <= x"e928";
when "01" & x"062" => DATA <= x"6000";
when "01" & x"063" => DATA <= x"fd02";
when "01" & x"064" => DATA <= x"203c";
when "01" & x"065" => DATA <= x"003f";
when "01" & x"066" => DATA <= x"29b2";
when "01" & x"067" => DATA <= x"6100";
when "01" & x"068" => DATA <= x"e932";
when "01" & x"069" => DATA <= x"6000";
when "01" & x"06a" => DATA <= x"fcf4";
when "01" & x"06b" => DATA <= x"6100";
when "01" & x"06c" => DATA <= x"064c";
when "01" & x"06d" => DATA <= x"7010";
when "01" & x"06e" => DATA <= x"220e";
when "01" & x"06f" => DATA <= x"6100";
when "01" & x"070" => DATA <= x"eef0";
when "01" & x"071" => DATA <= x"69e4";
when "01" & x"072" => DATA <= x"2842";
when "01" & x"073" => DATA <= x"6100";
when "01" & x"074" => DATA <= x"064a";
when "01" & x"075" => DATA <= x"7010";
when "01" & x"076" => DATA <= x"6100";
when "01" & x"077" => DATA <= x"eee2";
when "01" & x"078" => DATA <= x"69d6";
when "01" & x"079" => DATA <= x"2a42";
when "01" & x"07a" => DATA <= x"6100";
when "01" & x"07b" => DATA <= x"063c";
when "01" & x"07c" => DATA <= x"7010";
when "01" & x"07d" => DATA <= x"6100";
when "01" & x"07e" => DATA <= x"eed4";
when "01" & x"07f" => DATA <= x"69c8";
when "01" & x"080" => DATA <= x"5382";
when "01" & x"081" => DATA <= x"1adc";
when "01" & x"082" => DATA <= x"51ca";
when "01" & x"083" => DATA <= x"fffc";
when "01" & x"084" => DATA <= x"6000";
when "01" & x"085" => DATA <= x"fcbe";
when "01" & x"086" => DATA <= x"6100";
when "01" & x"087" => DATA <= x"e908";
when "01" & x"088" => DATA <= x"4e75";
when "01" & x"089" => DATA <= x"6100";
when "01" & x"08a" => DATA <= x"0610";
when "01" & x"08b" => DATA <= x"2f0d";
when "01" & x"08c" => DATA <= x"2f02";
when "01" & x"08d" => DATA <= x"2f01";
when "01" & x"08e" => DATA <= x"2f00";
when "01" & x"08f" => DATA <= x"4280";
when "01" & x"090" => DATA <= x"101e";
when "01" & x"091" => DATA <= x"0200";
when "01" & x"092" => DATA <= x"00df";
when "01" & x"093" => DATA <= x"0c00";
when "01" & x"094" => DATA <= x"0041";
when "01" & x"095" => DATA <= x"6700";
when "01" & x"096" => DATA <= x"0008";
when "01" & x"097" => DATA <= x"0c00";
when "01" & x"098" => DATA <= x"0044";
when "01" & x"099" => DATA <= x"6694";
when "01" & x"09a" => DATA <= x"0200";
when "01" & x"09b" => DATA <= x"00be";
when "01" & x"09c" => DATA <= x"e380";
when "01" & x"09d" => DATA <= x"1400";
when "01" & x"09e" => DATA <= x"101e";
when "01" & x"09f" => DATA <= x"0c00";
when "01" & x"0a0" => DATA <= x"0030";
when "01" & x"0a1" => DATA <= x"6584";
when "01" & x"0a2" => DATA <= x"0c00";
when "01" & x"0a3" => DATA <= x"0037";
when "01" & x"0a4" => DATA <= x"6200";
when "01" & x"0a5" => DATA <= x"ff7e";
when "01" & x"0a6" => DATA <= x"0400";
when "01" & x"0a7" => DATA <= x"0030";
when "01" & x"0a8" => DATA <= x"d002";
when "01" & x"0a9" => DATA <= x"e580";
when "01" & x"0aa" => DATA <= x"2a7c";
when "01" & x"0ab" => DATA <= x"003f";
when "01" & x"0ac" => DATA <= x"217a";
when "01" & x"0ad" => DATA <= x"dbc0";
when "01" & x"0ae" => DATA <= x"6100";
when "01" & x"0af" => DATA <= x"05c6";
when "01" & x"0b0" => DATA <= x"7010";
when "01" & x"0b1" => DATA <= x"220e";
when "01" & x"0b2" => DATA <= x"6100";
when "01" & x"0b3" => DATA <= x"ee6a";
when "01" & x"0b4" => DATA <= x"6900";
when "01" & x"0b5" => DATA <= x"ff5e";
when "01" & x"0b6" => DATA <= x"4ed5";
when "01" & x"0b7" => DATA <= x"201f";
when "01" & x"0b8" => DATA <= x"221f";
when "01" & x"0b9" => DATA <= x"241f";
when "01" & x"0ba" => DATA <= x"2a5f";
when "01" & x"0bb" => DATA <= x"6000";
when "01" & x"0bc" => DATA <= x"fc50";
when "01" & x"0bd" => DATA <= x"2042";
when "01" & x"0be" => DATA <= x"60f0";
when "01" & x"0bf" => DATA <= x"2242";
when "01" & x"0c0" => DATA <= x"60ec";
when "01" & x"0c1" => DATA <= x"2442";
when "01" & x"0c2" => DATA <= x"60e8";
when "01" & x"0c3" => DATA <= x"2642";
when "01" & x"0c4" => DATA <= x"60e4";
when "01" & x"0c5" => DATA <= x"2842";
when "01" & x"0c6" => DATA <= x"60e0";
when "01" & x"0c7" => DATA <= x"2a42";
when "01" & x"0c8" => DATA <= x"60dc";
when "01" & x"0c9" => DATA <= x"2c42";
when "01" & x"0ca" => DATA <= x"60d8";
when "01" & x"0cb" => DATA <= x"2e42";
when "01" & x"0cc" => DATA <= x"60d4";
when "01" & x"0cd" => DATA <= x"2002";
when "01" & x"0ce" => DATA <= x"60d0";
when "01" & x"0cf" => DATA <= x"2202";
when "01" & x"0d0" => DATA <= x"60cc";
when "01" & x"0d1" => DATA <= x"4e71";
when "01" & x"0d2" => DATA <= x"60c8";
when "01" & x"0d3" => DATA <= x"2602";
when "01" & x"0d4" => DATA <= x"60c4";
when "01" & x"0d5" => DATA <= x"2802";
when "01" & x"0d6" => DATA <= x"60c0";
when "01" & x"0d7" => DATA <= x"2a02";
when "01" & x"0d8" => DATA <= x"60bc";
when "01" & x"0d9" => DATA <= x"2c02";
when "01" & x"0da" => DATA <= x"60b8";
when "01" & x"0db" => DATA <= x"2e02";
when "01" & x"0dc" => DATA <= x"60b4";
when "01" & x"0dd" => DATA <= x"200e";
when "01" & x"0de" => DATA <= x"6100";
when "01" & x"0df" => DATA <= x"e876";
when "01" & x"0e0" => DATA <= x"6000";
when "01" & x"0e1" => DATA <= x"fc06";
when "01" & x"0e2" => DATA <= x"103c";
when "01" & x"0e3" => DATA <= x"0020";
when "01" & x"0e4" => DATA <= x"323c";
when "01" & x"0e5" => DATA <= x"0032";
when "01" & x"0e6" => DATA <= x"6100";
when "01" & x"0e7" => DATA <= x"e81c";
when "01" & x"0e8" => DATA <= x"51c9";
when "01" & x"0e9" => DATA <= x"fffa";
when "01" & x"0ea" => DATA <= x"203c";
when "01" & x"0eb" => DATA <= x"003f";
when "01" & x"0ec" => DATA <= x"2b2a";
when "01" & x"0ed" => DATA <= x"6100";
when "01" & x"0ee" => DATA <= x"e826";
when "01" & x"0ef" => DATA <= x"6100";
when "01" & x"0f0" => DATA <= x"e836";
when "01" & x"0f1" => DATA <= x"21fc";
when "01" & x"0f2" => DATA <= x"4430";
when "01" & x"0f3" => DATA <= x"3a00";
when "01" & x"0f4" => DATA <= x"0600";
when "01" & x"0f5" => DATA <= x"223c";
when "01" & x"0f6" => DATA <= x"0000";
when "01" & x"0f7" => DATA <= x"0603";
when "01" & x"0f8" => DATA <= x"243c";
when "01" & x"0f9" => DATA <= x"0000";
when "01" & x"0fa" => DATA <= x"00fc";
when "01" & x"0fb" => DATA <= x"6100";
when "01" & x"0fc" => DATA <= x"f4f2";
when "01" & x"0fd" => DATA <= x"11fc";
when "01" & x"0fe" => DATA <= x"0020";
when "01" & x"0ff" => DATA <= x"060b";
when "01" & x"100" => DATA <= x"21fc";
when "01" & x"101" => DATA <= x"4431";
when "01" & x"102" => DATA <= x"3a00";
when "01" & x"103" => DATA <= x"060c";
when "01" & x"104" => DATA <= x"2001";
when "01" & x"105" => DATA <= x"223c";
when "01" & x"106" => DATA <= x"0000";
when "01" & x"107" => DATA <= x"060f";
when "01" & x"108" => DATA <= x"243c";
when "01" & x"109" => DATA <= x"0000";
when "01" & x"10a" => DATA <= x"00f4";
when "01" & x"10b" => DATA <= x"6100";
when "01" & x"10c" => DATA <= x"f4d2";
when "01" & x"10d" => DATA <= x"11fc";
when "01" & x"10e" => DATA <= x"0020";
when "01" & x"10f" => DATA <= x"0617";
when "01" & x"110" => DATA <= x"21fc";
when "01" & x"111" => DATA <= x"4432";
when "01" & x"112" => DATA <= x"3a00";
when "01" & x"113" => DATA <= x"0618";
when "01" & x"114" => DATA <= x"2002";
when "01" & x"115" => DATA <= x"223c";
when "01" & x"116" => DATA <= x"0000";
when "01" & x"117" => DATA <= x"061b";
when "01" & x"118" => DATA <= x"243c";
when "01" & x"119" => DATA <= x"0000";
when "01" & x"11a" => DATA <= x"00e8";
when "01" & x"11b" => DATA <= x"6100";
when "01" & x"11c" => DATA <= x"f4b2";
when "01" & x"11d" => DATA <= x"11fc";
when "01" & x"11e" => DATA <= x"0020";
when "01" & x"11f" => DATA <= x"0623";
when "01" & x"120" => DATA <= x"21fc";
when "01" & x"121" => DATA <= x"4433";
when "01" & x"122" => DATA <= x"3a00";
when "01" & x"123" => DATA <= x"0624";
when "01" & x"124" => DATA <= x"2003";
when "01" & x"125" => DATA <= x"223c";
when "01" & x"126" => DATA <= x"0000";
when "01" & x"127" => DATA <= x"0627";
when "01" & x"128" => DATA <= x"243c";
when "01" & x"129" => DATA <= x"0000";
when "01" & x"12a" => DATA <= x"00dc";
when "01" & x"12b" => DATA <= x"6100";
when "01" & x"12c" => DATA <= x"f492";
when "01" & x"12d" => DATA <= x"11fc";
when "01" & x"12e" => DATA <= x"0020";
when "01" & x"12f" => DATA <= x"062f";
when "01" & x"130" => DATA <= x"21fc";
when "01" & x"131" => DATA <= x"5352";
when "01" & x"132" => DATA <= x"3a00";
when "01" & x"133" => DATA <= x"0630";
when "01" & x"134" => DATA <= x"223c";
when "01" & x"135" => DATA <= x"0000";
when "01" & x"136" => DATA <= x"0633";
when "01" & x"137" => DATA <= x"243c";
when "01" & x"138" => DATA <= x"0000";
when "01" & x"139" => DATA <= x"00cd";
when "01" & x"13a" => DATA <= x"40c0";
when "01" & x"13b" => DATA <= x"6100";
when "01" & x"13c" => DATA <= x"f6b4";
when "01" & x"13d" => DATA <= x"11fc";
when "01" & x"13e" => DATA <= x"0020";
when "01" & x"13f" => DATA <= x"0643";
when "01" & x"140" => DATA <= x"21fc";
when "01" & x"141" => DATA <= x"2020";
when "01" & x"142" => DATA <= x"0a0d";
when "01" & x"143" => DATA <= x"0644";
when "01" & x"144" => DATA <= x"21fc";
when "01" & x"145" => DATA <= x"4434";
when "01" & x"146" => DATA <= x"3a00";
when "01" & x"147" => DATA <= x"0648";
when "01" & x"148" => DATA <= x"2004";
when "01" & x"149" => DATA <= x"223c";
when "01" & x"14a" => DATA <= x"0000";
when "01" & x"14b" => DATA <= x"064b";
when "01" & x"14c" => DATA <= x"243c";
when "01" & x"14d" => DATA <= x"0000";
when "01" & x"14e" => DATA <= x"00b8";
when "01" & x"14f" => DATA <= x"6100";
when "01" & x"150" => DATA <= x"f44a";
when "01" & x"151" => DATA <= x"11fc";
when "01" & x"152" => DATA <= x"0020";
when "01" & x"153" => DATA <= x"0653";
when "01" & x"154" => DATA <= x"21fc";
when "01" & x"155" => DATA <= x"4435";
when "01" & x"156" => DATA <= x"3a00";
when "01" & x"157" => DATA <= x"0654";
when "01" & x"158" => DATA <= x"2005";
when "01" & x"159" => DATA <= x"223c";
when "01" & x"15a" => DATA <= x"0000";
when "01" & x"15b" => DATA <= x"0657";
when "01" & x"15c" => DATA <= x"243c";
when "01" & x"15d" => DATA <= x"0000";
when "01" & x"15e" => DATA <= x"00ac";
when "01" & x"15f" => DATA <= x"6100";
when "01" & x"160" => DATA <= x"f42a";
when "01" & x"161" => DATA <= x"11fc";
when "01" & x"162" => DATA <= x"0020";
when "01" & x"163" => DATA <= x"065f";
when "01" & x"164" => DATA <= x"21fc";
when "01" & x"165" => DATA <= x"4436";
when "01" & x"166" => DATA <= x"3a00";
when "01" & x"167" => DATA <= x"0660";
when "01" & x"168" => DATA <= x"2006";
when "01" & x"169" => DATA <= x"223c";
when "01" & x"16a" => DATA <= x"0000";
when "01" & x"16b" => DATA <= x"0663";
when "01" & x"16c" => DATA <= x"243c";
when "01" & x"16d" => DATA <= x"0000";
when "01" & x"16e" => DATA <= x"00a0";
when "01" & x"16f" => DATA <= x"6100";
when "01" & x"170" => DATA <= x"f40a";
when "01" & x"171" => DATA <= x"11fc";
when "01" & x"172" => DATA <= x"0020";
when "01" & x"173" => DATA <= x"066b";
when "01" & x"174" => DATA <= x"21fc";
when "01" & x"175" => DATA <= x"4437";
when "01" & x"176" => DATA <= x"3a00";
when "01" & x"177" => DATA <= x"066c";
when "01" & x"178" => DATA <= x"2007";
when "01" & x"179" => DATA <= x"223c";
when "01" & x"17a" => DATA <= x"0000";
when "01" & x"17b" => DATA <= x"066f";
when "01" & x"17c" => DATA <= x"243c";
when "01" & x"17d" => DATA <= x"0000";
when "01" & x"17e" => DATA <= x"0094";
when "01" & x"17f" => DATA <= x"6100";
when "01" & x"180" => DATA <= x"f3ea";
when "01" & x"181" => DATA <= x"11fc";
when "01" & x"182" => DATA <= x"0020";
when "01" & x"183" => DATA <= x"0677";
when "01" & x"184" => DATA <= x"21fc";
when "01" & x"185" => DATA <= x"5553";
when "01" & x"186" => DATA <= x"3a00";
when "01" & x"187" => DATA <= x"0678";
when "01" & x"188" => DATA <= x"4e68";
when "01" & x"189" => DATA <= x"2008";
when "01" & x"18a" => DATA <= x"223c";
when "01" & x"18b" => DATA <= x"0000";
when "01" & x"18c" => DATA <= x"067b";
when "01" & x"18d" => DATA <= x"243c";
when "01" & x"18e" => DATA <= x"0000";
when "01" & x"18f" => DATA <= x"0094";
when "01" & x"190" => DATA <= x"6100";
when "01" & x"191" => DATA <= x"f3c8";
when "01" & x"192" => DATA <= x"11fc";
when "01" & x"193" => DATA <= x"0020";
when "01" & x"194" => DATA <= x"0683";
when "01" & x"195" => DATA <= x"21fc";
when "01" & x"196" => DATA <= x"2020";
when "01" & x"197" => DATA <= x"0a0d";
when "01" & x"198" => DATA <= x"0684";
when "01" & x"199" => DATA <= x"21fc";
when "01" & x"19a" => DATA <= x"4130";
when "01" & x"19b" => DATA <= x"3a00";
when "01" & x"19c" => DATA <= x"0688";
when "01" & x"19d" => DATA <= x"2008";
when "01" & x"19e" => DATA <= x"223c";
when "01" & x"19f" => DATA <= x"0000";
when "01" & x"1a0" => DATA <= x"068b";
when "01" & x"1a1" => DATA <= x"243c";
when "01" & x"1a2" => DATA <= x"0000";
when "01" & x"1a3" => DATA <= x"0094";
when "01" & x"1a4" => DATA <= x"6100";
when "01" & x"1a5" => DATA <= x"f3a0";
when "01" & x"1a6" => DATA <= x"11fc";
when "01" & x"1a7" => DATA <= x"0020";
when "01" & x"1a8" => DATA <= x"0693";
when "01" & x"1a9" => DATA <= x"21fc";
when "01" & x"1aa" => DATA <= x"4131";
when "01" & x"1ab" => DATA <= x"3a00";
when "01" & x"1ac" => DATA <= x"0694";
when "01" & x"1ad" => DATA <= x"2009";
when "01" & x"1ae" => DATA <= x"223c";
when "01" & x"1af" => DATA <= x"0000";
when "01" & x"1b0" => DATA <= x"0697";
when "01" & x"1b1" => DATA <= x"243c";
when "01" & x"1b2" => DATA <= x"0000";
when "01" & x"1b3" => DATA <= x"0094";
when "01" & x"1b4" => DATA <= x"6100";
when "01" & x"1b5" => DATA <= x"f380";
when "01" & x"1b6" => DATA <= x"11fc";
when "01" & x"1b7" => DATA <= x"0020";
when "01" & x"1b8" => DATA <= x"069f";
when "01" & x"1b9" => DATA <= x"21fc";
when "01" & x"1ba" => DATA <= x"4132";
when "01" & x"1bb" => DATA <= x"3a00";
when "01" & x"1bc" => DATA <= x"06a0";
when "01" & x"1bd" => DATA <= x"200a";
when "01" & x"1be" => DATA <= x"223c";
when "01" & x"1bf" => DATA <= x"0000";
when "01" & x"1c0" => DATA <= x"06a3";
when "01" & x"1c1" => DATA <= x"243c";
when "01" & x"1c2" => DATA <= x"0000";
when "01" & x"1c3" => DATA <= x"0094";
when "01" & x"1c4" => DATA <= x"6100";
when "01" & x"1c5" => DATA <= x"f360";
when "01" & x"1c6" => DATA <= x"11fc";
when "01" & x"1c7" => DATA <= x"0020";
when "01" & x"1c8" => DATA <= x"06ab";
when "01" & x"1c9" => DATA <= x"21fc";
when "01" & x"1ca" => DATA <= x"4133";
when "01" & x"1cb" => DATA <= x"3a00";
when "01" & x"1cc" => DATA <= x"06ac";
when "01" & x"1cd" => DATA <= x"200b";
when "01" & x"1ce" => DATA <= x"223c";
when "01" & x"1cf" => DATA <= x"0000";
when "01" & x"1d0" => DATA <= x"06af";
when "01" & x"1d1" => DATA <= x"243c";
when "01" & x"1d2" => DATA <= x"0000";
when "01" & x"1d3" => DATA <= x"0094";
when "01" & x"1d4" => DATA <= x"6100";
when "01" & x"1d5" => DATA <= x"f340";
when "01" & x"1d6" => DATA <= x"11fc";
when "01" & x"1d7" => DATA <= x"0020";
when "01" & x"1d8" => DATA <= x"06b7";
when "01" & x"1d9" => DATA <= x"21fc";
when "01" & x"1da" => DATA <= x"5353";
when "01" & x"1db" => DATA <= x"3a00";
when "01" & x"1dc" => DATA <= x"06b8";
when "01" & x"1dd" => DATA <= x"200f";
when "01" & x"1de" => DATA <= x"223c";
when "01" & x"1df" => DATA <= x"0000";
when "01" & x"1e0" => DATA <= x"06bb";
when "01" & x"1e1" => DATA <= x"243c";
when "01" & x"1e2" => DATA <= x"0000";
when "01" & x"1e3" => DATA <= x"0094";
when "01" & x"1e4" => DATA <= x"6100";
when "01" & x"1e5" => DATA <= x"f320";
when "01" & x"1e6" => DATA <= x"11fc";
when "01" & x"1e7" => DATA <= x"0020";
when "01" & x"1e8" => DATA <= x"06c3";
when "01" & x"1e9" => DATA <= x"21fc";
when "01" & x"1ea" => DATA <= x"2020";
when "01" & x"1eb" => DATA <= x"0a0d";
when "01" & x"1ec" => DATA <= x"06c4";
when "01" & x"1ed" => DATA <= x"21fc";
when "01" & x"1ee" => DATA <= x"4134";
when "01" & x"1ef" => DATA <= x"3a00";
when "01" & x"1f0" => DATA <= x"06c8";
when "01" & x"1f1" => DATA <= x"200c";
when "01" & x"1f2" => DATA <= x"223c";
when "01" & x"1f3" => DATA <= x"0000";
when "01" & x"1f4" => DATA <= x"06cb";
when "01" & x"1f5" => DATA <= x"243c";
when "01" & x"1f6" => DATA <= x"0000";
when "01" & x"1f7" => DATA <= x"0094";
when "01" & x"1f8" => DATA <= x"6100";
when "01" & x"1f9" => DATA <= x"f2f8";
when "01" & x"1fa" => DATA <= x"11fc";
when "01" & x"1fb" => DATA <= x"0020";
when "01" & x"1fc" => DATA <= x"06d3";
when "01" & x"1fd" => DATA <= x"21fc";
when "01" & x"1fe" => DATA <= x"4135";
when "01" & x"1ff" => DATA <= x"3a00";
when "01" & x"200" => DATA <= x"06d4";
when "01" & x"201" => DATA <= x"200d";
when "01" & x"202" => DATA <= x"223c";
when "01" & x"203" => DATA <= x"0000";
when "01" & x"204" => DATA <= x"06d7";
when "01" & x"205" => DATA <= x"243c";
when "01" & x"206" => DATA <= x"0000";
when "01" & x"207" => DATA <= x"0094";
when "01" & x"208" => DATA <= x"6100";
when "01" & x"209" => DATA <= x"f2d8";
when "01" & x"20a" => DATA <= x"11fc";
when "01" & x"20b" => DATA <= x"0020";
when "01" & x"20c" => DATA <= x"06df";
when "01" & x"20d" => DATA <= x"21fc";
when "01" & x"20e" => DATA <= x"4136";
when "01" & x"20f" => DATA <= x"3a00";
when "01" & x"210" => DATA <= x"06e0";
when "01" & x"211" => DATA <= x"200e";
when "01" & x"212" => DATA <= x"223c";
when "01" & x"213" => DATA <= x"0000";
when "01" & x"214" => DATA <= x"06e3";
when "01" & x"215" => DATA <= x"243c";
when "01" & x"216" => DATA <= x"0000";
when "01" & x"217" => DATA <= x"0094";
when "01" & x"218" => DATA <= x"6100";
when "01" & x"219" => DATA <= x"f2b8";
when "01" & x"21a" => DATA <= x"11fc";
when "01" & x"21b" => DATA <= x"0020";
when "01" & x"21c" => DATA <= x"06eb";
when "01" & x"21d" => DATA <= x"21fc";
when "01" & x"21e" => DATA <= x"4137";
when "01" & x"21f" => DATA <= x"3a00";
when "01" & x"220" => DATA <= x"06ec";
when "01" & x"221" => DATA <= x"200f";
when "01" & x"222" => DATA <= x"223c";
when "01" & x"223" => DATA <= x"0000";
when "01" & x"224" => DATA <= x"06ef";
when "01" & x"225" => DATA <= x"243c";
when "01" & x"226" => DATA <= x"0000";
when "01" & x"227" => DATA <= x"0094";
when "01" & x"228" => DATA <= x"6100";
when "01" & x"229" => DATA <= x"f298";
when "01" & x"22a" => DATA <= x"11fc";
when "01" & x"22b" => DATA <= x"0020";
when "01" & x"22c" => DATA <= x"06f7";
when "01" & x"22d" => DATA <= x"21fc";
when "01" & x"22e" => DATA <= x"5043";
when "01" & x"22f" => DATA <= x"3a00";
when "01" & x"230" => DATA <= x"06f8";
when "01" & x"231" => DATA <= x"203c";
when "01" & x"232" => DATA <= x"0000";
when "01" & x"233" => DATA <= x"0600";
when "01" & x"234" => DATA <= x"6100";
when "01" & x"235" => DATA <= x"e598";
when "01" & x"236" => DATA <= x"6100";
when "01" & x"237" => DATA <= x"e5a8";
when "01" & x"238" => DATA <= x"6000";
when "01" & x"239" => DATA <= x"f956";
when "01" & x"23a" => DATA <= x"203c";
when "01" & x"23b" => DATA <= x"003f";
when "01" & x"23c" => DATA <= x"2949";
when "01" & x"23d" => DATA <= x"6100";
when "01" & x"23e" => DATA <= x"e586";
when "01" & x"23f" => DATA <= x"4e75";
when "01" & x"240" => DATA <= x"6000";
when "01" & x"241" => DATA <= x"e9c6";
when "01" & x"242" => DATA <= x"6000";
when "01" & x"243" => DATA <= x"e2f4";
when "01" & x"244" => DATA <= x"7010";
when "01" & x"245" => DATA <= x"220e";
when "01" & x"246" => DATA <= x"6100";
when "01" & x"247" => DATA <= x"eb42";
when "01" & x"248" => DATA <= x"6900";
when "01" & x"249" => DATA <= x"00d2";
when "01" & x"24a" => DATA <= x"2e02";
when "01" & x"24b" => DATA <= x"6100";
when "01" & x"24c" => DATA <= x"029a";
when "01" & x"24d" => DATA <= x"7010";
when "01" & x"24e" => DATA <= x"6100";
when "01" & x"24f" => DATA <= x"eb32";
when "01" & x"250" => DATA <= x"6900";
when "01" & x"251" => DATA <= x"00c2";
when "01" & x"252" => DATA <= x"2c02";
when "01" & x"253" => DATA <= x"6100";
when "01" & x"254" => DATA <= x"028a";
when "01" & x"255" => DATA <= x"7010";
when "01" & x"256" => DATA <= x"6100";
when "01" & x"257" => DATA <= x"eb22";
when "01" & x"258" => DATA <= x"6900";
when "01" & x"259" => DATA <= x"00b2";
when "01" & x"25a" => DATA <= x"2c41";
when "01" & x"25b" => DATA <= x"2a02";
when "01" & x"25c" => DATA <= x"6100";
when "01" & x"25d" => DATA <= x"026a";
when "01" & x"25e" => DATA <= x"101e";
when "01" & x"25f" => DATA <= x"0200";
when "01" & x"260" => DATA <= x"00df";
when "01" & x"261" => DATA <= x"b03c";
when "01" & x"262" => DATA <= x"0052";
when "01" & x"263" => DATA <= x"6700";
when "01" & x"264" => DATA <= x"0012";
when "01" & x"265" => DATA <= x"b03c";
when "01" & x"266" => DATA <= x"0057";
when "01" & x"267" => DATA <= x"6600";
when "01" & x"268" => DATA <= x"0094";
when "01" & x"269" => DATA <= x"183c";
when "01" & x"26a" => DATA <= x"0006";
when "01" & x"26b" => DATA <= x"6000";
when "01" & x"26c" => DATA <= x"0006";
when "01" & x"26d" => DATA <= x"183c";
when "01" & x"26e" => DATA <= x"0007";
when "01" & x"26f" => DATA <= x"6100";
when "01" & x"270" => DATA <= x"0244";
when "01" & x"271" => DATA <= x"6700";
when "01" & x"272" => DATA <= x"0020";
when "01" & x"273" => DATA <= x"101e";
when "01" & x"274" => DATA <= x"0200";
when "01" & x"275" => DATA <= x"00df";
when "01" & x"276" => DATA <= x"b03c";
when "01" & x"277" => DATA <= x"0053";
when "01" & x"278" => DATA <= x"6700";
when "01" & x"279" => DATA <= x"001a";
when "01" & x"27a" => DATA <= x"b03c";
when "01" & x"27b" => DATA <= x"004d";
when "01" & x"27c" => DATA <= x"6600";
when "01" & x"27d" => DATA <= x"006a";
when "01" & x"27e" => DATA <= x"163c";
when "01" & x"27f" => DATA <= x"0040";
when "01" & x"280" => DATA <= x"6000";
when "01" & x"281" => DATA <= x"000e";
when "01" & x"282" => DATA <= x"103c";
when "01" & x"283" => DATA <= x"0010";
when "01" & x"284" => DATA <= x"6000";
when "01" & x"285" => DATA <= x"0006";
when "01" & x"286" => DATA <= x"163c";
when "01" & x"287" => DATA <= x"0020";
when "01" & x"288" => DATA <= x"6100";
when "01" & x"289" => DATA <= x"0212";
when "01" & x"28a" => DATA <= x"6600";
when "01" & x"28b" => DATA <= x"f798";
when "01" & x"28c" => DATA <= x"11fc";
when "01" & x"28d" => DATA <= x"000e";
when "01" & x"28e" => DATA <= x"0600";
when "01" & x"28f" => DATA <= x"11fc";
when "01" & x"290" => DATA <= x"0010";
when "01" & x"291" => DATA <= x"0601";
when "01" & x"292" => DATA <= x"21c7";
when "01" & x"293" => DATA <= x"0602";
when "01" & x"294" => DATA <= x"21c6";
when "01" & x"295" => DATA <= x"0606";
when "01" & x"296" => DATA <= x"31c5";
when "01" & x"297" => DATA <= x"060a";
when "01" & x"298" => DATA <= x"11c4";
when "01" & x"299" => DATA <= x"060c";
when "01" & x"29a" => DATA <= x"11c3";
when "01" & x"29b" => DATA <= x"060d";
when "01" & x"29c" => DATA <= x"223c";
when "01" & x"29d" => DATA <= x"0000";
when "01" & x"29e" => DATA <= x"0600";
when "01" & x"29f" => DATA <= x"203c";
when "01" & x"2a0" => DATA <= x"0000";
when "01" & x"2a1" => DATA <= x"00fa";
when "01" & x"2a2" => DATA <= x"6100";
when "01" & x"2a3" => DATA <= x"e6a2";
when "01" & x"2a4" => DATA <= x"0c04";
when "01" & x"2a5" => DATA <= x"0006";
when "01" & x"2a6" => DATA <= x"6600";
when "01" & x"2a7" => DATA <= x"000c";
when "01" & x"2a8" => DATA <= x"2a47";
when "01" & x"2a9" => DATA <= x"2c46";
when "01" & x"2aa" => DATA <= x"2405";
when "01" & x"2ab" => DATA <= x"6000";
when "01" & x"2ac" => DATA <= x"014c";
when "01" & x"2ad" => DATA <= x"2a46";
when "01" & x"2ae" => DATA <= x"2c47";
when "01" & x"2af" => DATA <= x"2405";
when "01" & x"2b0" => DATA <= x"6000";
when "01" & x"2b1" => DATA <= x"015c";
when "01" & x"2b2" => DATA <= x"203c";
when "01" & x"2b3" => DATA <= x"003f";
when "01" & x"2b4" => DATA <= x"296d";
when "01" & x"2b5" => DATA <= x"6100";
when "01" & x"2b6" => DATA <= x"e496";
when "01" & x"2b7" => DATA <= x"4e75";
when "01" & x"2b8" => DATA <= x"6100";
when "01" & x"2b9" => DATA <= x"e4a4";
when "01" & x"2ba" => DATA <= x"5880";
when "01" & x"2bb" => DATA <= x"6100";
when "01" & x"2bc" => DATA <= x"e48a";
when "01" & x"2bd" => DATA <= x"0cb8";
when "01" & x"2be" => DATA <= x"0000";
when "01" & x"2bf" => DATA <= x"0000";
when "01" & x"2c0" => DATA <= x"0510";
when "01" & x"2c1" => DATA <= x"6700";
when "01" & x"2c2" => DATA <= x"0022";
when "01" & x"2c3" => DATA <= x"203c";
when "01" & x"2c4" => DATA <= x"003f";
when "01" & x"2c5" => DATA <= x"2c58";
when "01" & x"2c6" => DATA <= x"6100";
when "01" & x"2c7" => DATA <= x"e474";
when "01" & x"2c8" => DATA <= x"2038";
when "01" & x"2c9" => DATA <= x"0510";
when "01" & x"2ca" => DATA <= x"223c";
when "01" & x"2cb" => DATA <= x"0000";
when "01" & x"2cc" => DATA <= x"0600";
when "01" & x"2cd" => DATA <= x"143c";
when "01" & x"2ce" => DATA <= x"00ff";
when "01" & x"2cf" => DATA <= x"6100";
when "01" & x"2d0" => DATA <= x"f14a";
when "01" & x"2d1" => DATA <= x"6100";
when "01" & x"2d2" => DATA <= x"e45e";
when "01" & x"2d3" => DATA <= x"6100";
when "01" & x"2d4" => DATA <= x"e46e";
when "01" & x"2d5" => DATA <= x"2e78";
when "01" & x"2d6" => DATA <= x"0508";
when "01" & x"2d7" => DATA <= x"6000";
when "01" & x"2d8" => DATA <= x"ddb2";
when "01" & x"2d9" => DATA <= x"2f00";
when "01" & x"2da" => DATA <= x"203c";
when "01" & x"2db" => DATA <= x"003f";
when "01" & x"2dc" => DATA <= x"2d1c";
when "01" & x"2dd" => DATA <= x"21fc";
when "01" & x"2de" => DATA <= x"0000";
when "01" & x"2df" => DATA <= x"0000";
when "01" & x"2e0" => DATA <= x"0510";
when "01" & x"2e1" => DATA <= x"6100";
when "01" & x"2e2" => DATA <= x"eb60";
when "01" & x"2e3" => DATA <= x"201f";
when "01" & x"2e4" => DATA <= x"4e75";
when "01" & x"2e5" => DATA <= x"0839";
when "01" & x"2e6" => DATA <= x"0006";
when "01" & x"2e7" => DATA <= x"fffe";
when "01" & x"2e8" => DATA <= x"0000";
when "01" & x"2e9" => DATA <= x"67f6";
when "01" & x"2ea" => DATA <= x"13c0";
when "01" & x"2eb" => DATA <= x"fffe";
when "01" & x"2ec" => DATA <= x"0001";
when "01" & x"2ed" => DATA <= x"4e75";
when "01" & x"2ee" => DATA <= x"4e75";
when "01" & x"2ef" => DATA <= x"2f00";
when "01" & x"2f0" => DATA <= x"203c";
when "01" & x"2f1" => DATA <= x"003f";
when "01" & x"2f2" => DATA <= x"2e3c";
when "01" & x"2f3" => DATA <= x"6100";
when "01" & x"2f4" => DATA <= x"eb3c";
when "01" & x"2f5" => DATA <= x"201f";
when "01" & x"2f6" => DATA <= x"4e75";
when "01" & x"2f7" => DATA <= x"b07c";
when "01" & x"2f8" => DATA <= x"0010";
when "01" & x"2f9" => DATA <= x"6300";
when "01" & x"2fa" => DATA <= x"000e";
when "01" & x"2fb" => DATA <= x"203c";
when "01" & x"2fc" => DATA <= x"003f";
when "01" & x"2fd" => DATA <= x"2e20";
when "01" & x"2fe" => DATA <= x"003c";
when "01" & x"2ff" => DATA <= x"0002";
when "01" & x"300" => DATA <= x"4e75";
when "01" & x"301" => DATA <= x"41f9";
when "01" & x"302" => DATA <= x"003f";
when "01" & x"303" => DATA <= x"3630";
when "01" & x"304" => DATA <= x"e588";
when "01" & x"305" => DATA <= x"d1c0";
when "01" & x"306" => DATA <= x"d1c0";
when "01" & x"307" => DATA <= x"d1c0";
when "01" & x"308" => DATA <= x"2258";
when "01" & x"309" => DATA <= x"b3fc";
when "01" & x"30a" => DATA <= x"0000";
when "01" & x"30b" => DATA <= x"0000";
when "01" & x"30c" => DATA <= x"67dc";
when "01" & x"30d" => DATA <= x"2f04";
when "01" & x"30e" => DATA <= x"2458";
when "01" & x"30f" => DATA <= x"2658";
when "01" & x"310" => DATA <= x"4a81";
when "01" & x"311" => DATA <= x"6600";
when "01" & x"312" => DATA <= x"0008";
when "01" & x"313" => DATA <= x"2211";
when "01" & x"314" => DATA <= x"6000";
when "01" & x"315" => DATA <= x"0008";
when "01" & x"316" => DATA <= x"2811";
when "01" & x"317" => DATA <= x"2281";
when "01" & x"318" => DATA <= x"c941";
when "01" & x"319" => DATA <= x"4a82";
when "01" & x"31a" => DATA <= x"6600";
when "01" & x"31b" => DATA <= x"0008";
when "01" & x"31c" => DATA <= x"2412";
when "01" & x"31d" => DATA <= x"6000";
when "01" & x"31e" => DATA <= x"0008";
when "01" & x"31f" => DATA <= x"2812";
when "01" & x"320" => DATA <= x"2482";
when "01" & x"321" => DATA <= x"c942";
when "01" & x"322" => DATA <= x"4a83";
when "01" & x"323" => DATA <= x"6600";
when "01" & x"324" => DATA <= x"0008";
when "01" & x"325" => DATA <= x"2612";
when "01" & x"326" => DATA <= x"6000";
when "01" & x"327" => DATA <= x"0008";
when "01" & x"328" => DATA <= x"2813";
when "01" & x"329" => DATA <= x"2681";
when "01" & x"32a" => DATA <= x"c941";
when "01" & x"32b" => DATA <= x"281f";
when "01" & x"32c" => DATA <= x"4e75";
when "01" & x"32d" => DATA <= x"6000";
when "01" & x"32e" => DATA <= x"e11e";
when "01" & x"32f" => DATA <= x"6000";
when "01" & x"330" => DATA <= x"e11a";
when "01" & x"331" => DATA <= x"0200";
when "01" & x"332" => DATA <= x"0040";
when "01" & x"333" => DATA <= x"11c0";
when "01" & x"334" => DATA <= x"0535";
when "01" & x"335" => DATA <= x"4e75";
when "01" & x"336" => DATA <= x"21fc";
when "01" & x"337" => DATA <= x"0000";
when "01" & x"338" => DATA <= x"0000";
when "01" & x"339" => DATA <= x"0518";
when "01" & x"33a" => DATA <= x"b2bc";
when "01" & x"33b" => DATA <= x"4142";
when "01" & x"33c" => DATA <= x"4558";
when "01" & x"33d" => DATA <= x"6600";
when "01" & x"33e" => DATA <= x"0018";
when "01" & x"33f" => DATA <= x"21c2";
when "01" & x"340" => DATA <= x"0518";
when "01" & x"341" => DATA <= x"b4b8";
when "01" & x"342" => DATA <= x"051c";
when "01" & x"343" => DATA <= x"6300";
when "01" & x"344" => DATA <= x"000c";
when "01" & x"345" => DATA <= x"203c";
when "01" & x"346" => DATA <= x"003f";
when "01" & x"347" => DATA <= x"2e64";
when "01" & x"348" => DATA <= x"6100";
when "01" & x"349" => DATA <= x"ea92";
when "01" & x"34a" => DATA <= x"2e78";
when "01" & x"34b" => DATA <= x"0508";
when "01" & x"34c" => DATA <= x"6000";
when "01" & x"34d" => DATA <= x"dcc8";
when "01" & x"34e" => DATA <= x"6000";
when "01" & x"34f" => DATA <= x"e0dc";
when "01" & x"350" => DATA <= x"6000";
when "01" & x"351" => DATA <= x"e0d8";
when "01" & x"352" => DATA <= x"21cd";
when "01" & x"353" => DATA <= x"0600";
when "01" & x"354" => DATA <= x"223c";
when "01" & x"355" => DATA <= x"0000";
when "01" & x"356" => DATA <= x"0600";
when "01" & x"357" => DATA <= x"7005";
when "01" & x"358" => DATA <= x"6100";
when "01" & x"359" => DATA <= x"e536";
when "01" & x"35a" => DATA <= x"1cf8";
when "01" & x"35b" => DATA <= x"0605";
when "01" & x"35c" => DATA <= x"51ca";
when "01" & x"35d" => DATA <= x"ffee";
when "01" & x"35e" => DATA <= x"4e75";
when "01" & x"35f" => DATA <= x"21cd";
when "01" & x"360" => DATA <= x"0600";
when "01" & x"361" => DATA <= x"223c";
when "01" & x"362" => DATA <= x"0000";
when "01" & x"363" => DATA <= x"0600";
when "01" & x"364" => DATA <= x"11de";
when "01" & x"365" => DATA <= x"0605";
when "01" & x"366" => DATA <= x"7006";
when "01" & x"367" => DATA <= x"6100";
when "01" & x"368" => DATA <= x"e518";
when "01" & x"369" => DATA <= x"51ca";
when "01" & x"36a" => DATA <= x"ffee";
when "01" & x"36b" => DATA <= x"4e75";
when "01" & x"36c" => DATA <= x"2a7c";
when "01" & x"36d" => DATA <= x"003f";
when "01" & x"36e" => DATA <= x"37e8";
when "01" & x"36f" => DATA <= x"2c7c";
when "01" & x"370" => DATA <= x"ffff";
when "01" & x"371" => DATA <= x"2500";
when "01" & x"372" => DATA <= x"243c";
when "01" & x"373" => DATA <= x"0000";
when "01" & x"374" => DATA <= x"01fb";
when "01" & x"375" => DATA <= x"61d2";
when "01" & x"376" => DATA <= x"2a7c";
when "01" & x"377" => DATA <= x"ffff";
when "01" & x"378" => DATA <= x"0200";
when "01" & x"379" => DATA <= x"2c7c";
when "01" & x"37a" => DATA <= x"0000";
when "01" & x"37b" => DATA <= x"0600";
when "01" & x"37c" => DATA <= x"7402";
when "01" & x"37d" => DATA <= x"61a8";
when "01" & x"37e" => DATA <= x"2a7c";
when "01" & x"37f" => DATA <= x"0000";
when "01" & x"380" => DATA <= x"0600";
when "01" & x"381" => DATA <= x"2c7c";
when "01" & x"382" => DATA <= x"ffff";
when "01" & x"383" => DATA <= x"2503";
when "01" & x"384" => DATA <= x"7402";
when "01" & x"385" => DATA <= x"61b2";
when "01" & x"386" => DATA <= x"31fc";
when "01" & x"387" => DATA <= x"2500";
when "01" & x"388" => DATA <= x"0600";
when "01" & x"389" => DATA <= x"2a7c";
when "01" & x"38a" => DATA <= x"0000";
when "01" & x"38b" => DATA <= x"0600";
when "01" & x"38c" => DATA <= x"2c7c";
when "01" & x"38d" => DATA <= x"ffff";
when "01" & x"38e" => DATA <= x"0200";
when "01" & x"38f" => DATA <= x"7402";
when "01" & x"390" => DATA <= x"619c";
when "01" & x"391" => DATA <= x"4e75";
when "01" & x"392" => DATA <= x"0c1e";
when "01" & x"393" => DATA <= x"0020";
when "01" & x"394" => DATA <= x"67fa";
when "01" & x"395" => DATA <= x"1026";
when "01" & x"396" => DATA <= x"b03c";
when "01" & x"397" => DATA <= x"000d";
when "01" & x"398" => DATA <= x"4e75";
when "01" & x"399" => DATA <= x"c38e";
when "01" & x"39a" => DATA <= x"0c1e";
when "01" & x"39b" => DATA <= x"0020";
when "01" & x"39c" => DATA <= x"67fa";
when "01" & x"39d" => DATA <= x"1026";
when "01" & x"39e" => DATA <= x"c38e";
when "01" & x"39f" => DATA <= x"b03c";
when "01" & x"3a0" => DATA <= x"000d";
when "01" & x"3a1" => DATA <= x"4e75";
when "01" & x"3a2" => DATA <= x"7010";
when "01" & x"3a3" => DATA <= x"220e";
when "01" & x"3a4" => DATA <= x"6100";
when "01" & x"3a5" => DATA <= x"e886";
when "01" & x"3a6" => DATA <= x"6900";
when "01" & x"3a7" => DATA <= x"000c";
when "01" & x"3a8" => DATA <= x"2c41";
when "01" & x"3a9" => DATA <= x"2202";
when "01" & x"3aa" => DATA <= x"023c";
when "01" & x"3ab" => DATA <= x"00fe";
when "01" & x"3ac" => DATA <= x"4e75";
when "01" & x"3ad" => DATA <= x"2c41";
when "01" & x"3ae" => DATA <= x"2202";
when "01" & x"3af" => DATA <= x"003c";
when "01" & x"3b0" => DATA <= x"0001";
when "01" & x"3b1" => DATA <= x"4e75";
when "01" & x"3b2" => DATA <= x"4281";
when "01" & x"3b3" => DATA <= x"101e";
when "01" & x"3b4" => DATA <= x"2f00";
when "01" & x"3b5" => DATA <= x"0c00";
when "01" & x"3b6" => DATA <= x"0030";
when "01" & x"3b7" => DATA <= x"6500";
when "01" & x"3b8" => DATA <= x"002c";
when "01" & x"3b9" => DATA <= x"0c00";
when "01" & x"3ba" => DATA <= x"0039";
when "01" & x"3bb" => DATA <= x"6300";
when "01" & x"3bc" => DATA <= x"0018";
when "01" & x"3bd" => DATA <= x"0200";
when "01" & x"3be" => DATA <= x"00df";
when "01" & x"3bf" => DATA <= x"0c00";
when "01" & x"3c0" => DATA <= x"0041";
when "01" & x"3c1" => DATA <= x"6500";
when "01" & x"3c2" => DATA <= x"0018";
when "01" & x"3c3" => DATA <= x"0c00";
when "01" & x"3c4" => DATA <= x"0046";
when "01" & x"3c5" => DATA <= x"6200";
when "01" & x"3c6" => DATA <= x"0010";
when "01" & x"3c7" => DATA <= x"5f00";
when "01" & x"3c8" => DATA <= x"0200";
when "01" & x"3c9" => DATA <= x"000f";
when "01" & x"3ca" => DATA <= x"e981";
when "01" & x"3cb" => DATA <= x"d200";
when "01" & x"3cc" => DATA <= x"201f";
when "01" & x"3cd" => DATA <= x"60ca";
when "01" & x"3ce" => DATA <= x"201f";
when "01" & x"3cf" => DATA <= x"0c00";
when "01" & x"3d0" => DATA <= x"000d";
when "01" & x"3d1" => DATA <= x"6700";
when "01" & x"3d2" => DATA <= x"0012";
when "01" & x"3d3" => DATA <= x"0c00";
when "01" & x"3d4" => DATA <= x"0020";
when "01" & x"3d5" => DATA <= x"6700";
when "01" & x"3d6" => DATA <= x"000a";
when "01" & x"3d7" => DATA <= x"534e";
when "01" & x"3d8" => DATA <= x"003c";
when "01" & x"3d9" => DATA <= x"0001";
when "01" & x"3da" => DATA <= x"4e75";
when "01" & x"3db" => DATA <= x"534e";
when "01" & x"3dc" => DATA <= x"023c";
when "01" & x"3dd" => DATA <= x"00fe";
when "01" & x"3de" => DATA <= x"4e75";
when "01" & x"3df" => DATA <= x"101e";
when "01" & x"3e0" => DATA <= x"0c00";
when "01" & x"3e1" => DATA <= x"0020";
when "01" & x"3e2" => DATA <= x"6500";
when "01" & x"3e3" => DATA <= x"000a";
when "01" & x"3e4" => DATA <= x"0c00";
when "01" & x"3e5" => DATA <= x"007f";
when "01" & x"3e6" => DATA <= x"6500";
when "01" & x"3e7" => DATA <= x"0006";
when "01" & x"3e8" => DATA <= x"103c";
when "01" & x"3e9" => DATA <= x"002e";
when "01" & x"3ea" => DATA <= x"4e75";
when "01" & x"3eb" => DATA <= x"0280";
when "01" & x"3ec" => DATA <= x"0000";
when "01" & x"3ed" => DATA <= x"0007";
when "01" & x"3ee" => DATA <= x"e140";
when "01" & x"3ef" => DATA <= x"027c";
when "01" & x"3f0" => DATA <= x"f8ff";
when "01" & x"3f1" => DATA <= x"221f";
when "01" & x"3f2" => DATA <= x"4e75";
when "01" & x"3f3" => DATA <= x"0d0a";
when "01" & x"3f4" => DATA <= x"4163";
when "01" & x"3f5" => DATA <= x"6f72";
when "01" & x"3f6" => DATA <= x"6e20";
when "01" & x"3f7" => DATA <= x"3638";
when "01" & x"3f8" => DATA <= x"0020";
when "01" & x"3f9" => DATA <= x"7365";
when "01" & x"3fa" => DATA <= x"636f";
when "01" & x"3fb" => DATA <= x"6e64";
when "01" & x"3fc" => DATA <= x"2070";
when "01" & x"3fd" => DATA <= x"726f";
when "01" & x"3fe" => DATA <= x"6365";
when "01" & x"3ff" => DATA <= x"7373";
when "01" & x"400" => DATA <= x"6f72";
when "01" & x"401" => DATA <= x"2000";
when "01" & x"402" => DATA <= x"3030";
when "01" & x"403" => DATA <= x"3830";
when "01" & x"404" => DATA <= x"3030";
when "01" & x"405" => DATA <= x"3031";
when "01" & x"406" => DATA <= x"3030";
when "01" & x"407" => DATA <= x"3230";
when "01" & x"408" => DATA <= x"3033";
when "01" & x"409" => DATA <= x"3030";
when "01" & x"40a" => DATA <= x"3430";
when "01" & x"40b" => DATA <= x"3036";
when "01" & x"40c" => DATA <= x"3030";
when "01" & x"40d" => DATA <= x"3730";
when "01" & x"40e" => DATA <= x"3330";
when "01" & x"40f" => DATA <= x"304b";
when "01" & x"410" => DATA <= x"070d";
when "01" & x"411" => DATA <= x"0a0d";
when "01" & x"412" => DATA <= x"0a00";
when "01" & x"413" => DATA <= x"1701";
when "01" & x"414" => DATA <= x"0000";
when "01" & x"415" => DATA <= x"0000";
when "01" & x"416" => DATA <= x"0000";
when "01" & x"417" => DATA <= x"0000";
when "01" & x"418" => DATA <= x"0017";
when "01" & x"419" => DATA <= x"0101";
when "01" & x"41a" => DATA <= x"0000";
when "01" & x"41b" => DATA <= x"0000";
when "01" & x"41c" => DATA <= x"0000";
when "01" & x"41d" => DATA <= x"0000";
when "01" & x"41e" => DATA <= x"0a0d";
when "01" & x"41f" => DATA <= x"4369";
when "01" & x"420" => DATA <= x"7363";
when "01" & x"421" => DATA <= x"4f53";
when "01" & x"422" => DATA <= x"2076";
when "01" & x"423" => DATA <= x"322e";
when "01" & x"424" => DATA <= x"3031";
when "01" & x"425" => DATA <= x"2028";
when "01" & x"426" => DATA <= x"4a75";
when "01" & x"427" => DATA <= x"6c79";
when "01" & x"428" => DATA <= x"2033";
when "01" & x"429" => DATA <= x"312c";
when "01" & x"42a" => DATA <= x"2032";
when "01" & x"42b" => DATA <= x"3031";
when "01" & x"42c" => DATA <= x"3529";
when "01" & x"42d" => DATA <= x"0a0d";
when "01" & x"42e" => DATA <= x"0020";
when "01" & x"42f" => DATA <= x"2020";
when "01" & x"430" => DATA <= x"5357";
when "01" & x"431" => DATA <= x"490a";
when "01" & x"432" => DATA <= x"0d20";
when "01" & x"433" => DATA <= x"2020";
when "01" & x"434" => DATA <= x"5455";
when "01" & x"435" => DATA <= x"4245";
when "01" & x"436" => DATA <= x"0a0d";
when "01" & x"437" => DATA <= x"0020";
when "01" & x"438" => DATA <= x"2020";
when "01" & x"439" => DATA <= x"4552";
when "01" & x"43a" => DATA <= x"524f";
when "01" & x"43b" => DATA <= x"5220";
when "01" & x"43c" => DATA <= x"286e";
when "01" & x"43d" => DATA <= x"756d";
when "01" & x"43e" => DATA <= x"6265";
when "01" & x"43f" => DATA <= x"7229";
when "01" & x"440" => DATA <= x"203c";
when "01" & x"441" => DATA <= x"6d65";
when "01" & x"442" => DATA <= x"7373";
when "01" & x"443" => DATA <= x"6167";
when "01" & x"444" => DATA <= x"653e";
when "01" & x"445" => DATA <= x"0a0d";
when "01" & x"446" => DATA <= x"2020";
when "01" & x"447" => DATA <= x"2046";
when "01" & x"448" => DATA <= x"4c41";
when "01" & x"449" => DATA <= x"5348";
when "01" & x"44a" => DATA <= x"203c";
when "01" & x"44b" => DATA <= x"6673";
when "01" & x"44c" => DATA <= x"703e";
when "01" & x"44d" => DATA <= x"0a0d";
when "01" & x"44e" => DATA <= x"2020";
when "01" & x"44f" => DATA <= x"2047";
when "01" & x"450" => DATA <= x"4f20";
when "01" & x"451" => DATA <= x"3c61";
when "01" & x"452" => DATA <= x"6464";
when "01" & x"453" => DATA <= x"723e";
when "01" & x"454" => DATA <= x"0a0d";
when "01" & x"455" => DATA <= x"2020";
when "01" & x"456" => DATA <= x"204d";
when "01" & x"457" => DATA <= x"4f4e";
when "01" & x"458" => DATA <= x"0a0d";
when "01" & x"459" => DATA <= x"2020";
when "01" & x"45a" => DATA <= x"2051";
when "01" & x"45b" => DATA <= x"5549";
when "01" & x"45c" => DATA <= x"540a";
when "01" & x"45d" => DATA <= x"0d20";
when "01" & x"45e" => DATA <= x"2020";
when "01" & x"45f" => DATA <= x"545a";
when "01" & x"460" => DATA <= x"4150";
when "01" & x"461" => DATA <= x"2028";
when "01" & x"462" => DATA <= x"6164";
when "01" & x"463" => DATA <= x"6472";
when "01" & x"464" => DATA <= x"290a";
when "01" & x"465" => DATA <= x"0d20";
when "01" & x"466" => DATA <= x"2020";
when "01" & x"467" => DATA <= x"5846";
when "01" & x"468" => DATA <= x"4552";
when "01" & x"469" => DATA <= x"203c";
when "01" & x"46a" => DATA <= x"696f";
when "01" & x"46b" => DATA <= x"2061";
when "01" & x"46c" => DATA <= x"6464";
when "01" & x"46d" => DATA <= x"722e";
when "01" & x"46e" => DATA <= x"3e20";
when "01" & x"46f" => DATA <= x"3c61";
when "01" & x"470" => DATA <= x"6464";
when "01" & x"471" => DATA <= x"723e";
when "01" & x"472" => DATA <= x"203c";
when "01" & x"473" => DATA <= x"6c65";
when "01" & x"474" => DATA <= x"6e67";
when "01" & x"475" => DATA <= x"7468";
when "01" & x"476" => DATA <= x"3e20";
when "01" & x"477" => DATA <= x"2852";
when "01" & x"478" => DATA <= x"7c57";
when "01" & x"479" => DATA <= x"2920";
when "01" & x"47a" => DATA <= x"2853";
when "01" & x"47b" => DATA <= x"7c4d";
when "01" & x"47c" => DATA <= x"290a";
when "01" & x"47d" => DATA <= x"0d00";
when "01" & x"47e" => DATA <= x"5379";
when "01" & x"47f" => DATA <= x"6e74";
when "01" & x"480" => DATA <= x"6178";
when "01" & x"481" => DATA <= x"3a20";
when "01" & x"482" => DATA <= x"4552";
when "01" & x"483" => DATA <= x"524f";
when "01" & x"484" => DATA <= x"5220";
when "01" & x"485" => DATA <= x"286e";
when "01" & x"486" => DATA <= x"756d";
when "01" & x"487" => DATA <= x"6265";
when "01" & x"488" => DATA <= x"7229";
when "01" & x"489" => DATA <= x"203c";
when "01" & x"48a" => DATA <= x"6d65";
when "01" & x"48b" => DATA <= x"7373";
when "01" & x"48c" => DATA <= x"6167";
when "01" & x"48d" => DATA <= x"653e";
when "01" & x"48e" => DATA <= x"0a0d";
when "01" & x"48f" => DATA <= x"0053";
when "01" & x"490" => DATA <= x"796e";
when "01" & x"491" => DATA <= x"7461";
when "01" & x"492" => DATA <= x"783a";
when "01" & x"493" => DATA <= x"2046";
when "01" & x"494" => DATA <= x"4c41";
when "01" & x"495" => DATA <= x"5348";
when "01" & x"496" => DATA <= x"203c";
when "01" & x"497" => DATA <= x"6673";
when "01" & x"498" => DATA <= x"703e";
when "01" & x"499" => DATA <= x"0a0d";
when "01" & x"49a" => DATA <= x"0053";
when "01" & x"49b" => DATA <= x"796e";
when "01" & x"49c" => DATA <= x"7461";
when "01" & x"49d" => DATA <= x"783a";
when "01" & x"49e" => DATA <= x"2047";
when "01" & x"49f" => DATA <= x"4f20";
when "01" & x"4a0" => DATA <= x"3c61";
when "01" & x"4a1" => DATA <= x"6464";
when "01" & x"4a2" => DATA <= x"723e";
when "01" & x"4a3" => DATA <= x"0a0d";
when "01" & x"4a4" => DATA <= x"0053";
when "01" & x"4a5" => DATA <= x"796e";
when "01" & x"4a6" => DATA <= x"7461";
when "01" & x"4a7" => DATA <= x"783a";
when "01" & x"4a8" => DATA <= x"204d";
when "01" & x"4a9" => DATA <= x"4f4e";
when "01" & x"4aa" => DATA <= x"0a0d";
when "01" & x"4ab" => DATA <= x"0053";
when "01" & x"4ac" => DATA <= x"796e";
when "01" & x"4ad" => DATA <= x"7461";
when "01" & x"4ae" => DATA <= x"783a";
when "01" & x"4af" => DATA <= x"2054";
when "01" & x"4b0" => DATA <= x"5a41";
when "01" & x"4b1" => DATA <= x"5020";
when "01" & x"4b2" => DATA <= x"2861";
when "01" & x"4b3" => DATA <= x"6464";
when "01" & x"4b4" => DATA <= x"7229";
when "01" & x"4b5" => DATA <= x"0a0d";
when "01" & x"4b6" => DATA <= x"0053";
when "01" & x"4b7" => DATA <= x"796e";
when "01" & x"4b8" => DATA <= x"7461";
when "01" & x"4b9" => DATA <= x"783a";
when "01" & x"4ba" => DATA <= x"2058";
when "01" & x"4bb" => DATA <= x"4645";
when "01" & x"4bc" => DATA <= x"5220";
when "01" & x"4bd" => DATA <= x"3c69";
when "01" & x"4be" => DATA <= x"6f20";
when "01" & x"4bf" => DATA <= x"6164";
when "01" & x"4c0" => DATA <= x"6472";
when "01" & x"4c1" => DATA <= x"2e3e";
when "01" & x"4c2" => DATA <= x"203c";
when "01" & x"4c3" => DATA <= x"6164";
when "01" & x"4c4" => DATA <= x"6472";
when "01" & x"4c5" => DATA <= x"3e20";
when "01" & x"4c6" => DATA <= x"3c6c";
when "01" & x"4c7" => DATA <= x"656e";
when "01" & x"4c8" => DATA <= x"6774";
when "01" & x"4c9" => DATA <= x"683e";
when "01" & x"4ca" => DATA <= x"2028";
when "01" & x"4cb" => DATA <= x"527c";
when "01" & x"4cc" => DATA <= x"5729";
when "01" & x"4cd" => DATA <= x"2028";
when "01" & x"4ce" => DATA <= x"537c";
when "01" & x"4cf" => DATA <= x"4d29";
when "01" & x"4d0" => DATA <= x"0a0d";
when "01" & x"4d1" => DATA <= x"0043";
when "01" & x"4d2" => DATA <= x"6973";
when "01" & x"4d3" => DATA <= x"634f";
when "01" & x"4d4" => DATA <= x"5320";
when "01" & x"4d5" => DATA <= x"4d6f";
when "01" & x"4d6" => DATA <= x"6e69";
when "01" & x"4d7" => DATA <= x"746f";
when "01" & x"4d8" => DATA <= x"7200";
when "01" & x"4d9" => DATA <= x"4220";
when "01" & x"4da" => DATA <= x"2042";
when "01" & x"4db" => DATA <= x"7974";
when "01" & x"4dc" => DATA <= x"6520";
when "01" & x"4dd" => DATA <= x"7365";
when "01" & x"4de" => DATA <= x"6172";
when "01" & x"4df" => DATA <= x"6368";
when "01" & x"4e0" => DATA <= x"203c";
when "01" & x"4e1" => DATA <= x"7374";
when "01" & x"4e2" => DATA <= x"6172";
when "01" & x"4e3" => DATA <= x"743e";
when "01" & x"4e4" => DATA <= x"203c";
when "01" & x"4e5" => DATA <= x"656e";
when "01" & x"4e6" => DATA <= x"643e";
when "01" & x"4e7" => DATA <= x"203c";
when "01" & x"4e8" => DATA <= x"6279";
when "01" & x"4e9" => DATA <= x"7465";
when "01" & x"4ea" => DATA <= x"3e0a";
when "01" & x"4eb" => DATA <= x"0d44";
when "01" & x"4ec" => DATA <= x"2020";
when "01" & x"4ed" => DATA <= x"4469";
when "01" & x"4ee" => DATA <= x"7361";
when "01" & x"4ef" => DATA <= x"7373";
when "01" & x"4f0" => DATA <= x"656d";
when "01" & x"4f1" => DATA <= x"626c";
when "01" & x"4f2" => DATA <= x"6520";
when "01" & x"4f3" => DATA <= x"3c61";
when "01" & x"4f4" => DATA <= x"6464";
when "01" & x"4f5" => DATA <= x"723e";
when "01" & x"4f6" => DATA <= x"0a0d";
when "01" & x"4f7" => DATA <= x"4520";
when "01" & x"4f8" => DATA <= x"2045";
when "01" & x"4f9" => DATA <= x"6469";
when "01" & x"4fa" => DATA <= x"7420";
when "01" & x"4fb" => DATA <= x"6d65";
when "01" & x"4fc" => DATA <= x"6d6f";
when "01" & x"4fd" => DATA <= x"7279";
when "01" & x"4fe" => DATA <= x"203c";
when "01" & x"4ff" => DATA <= x"6164";
when "01" & x"500" => DATA <= x"6472";
when "01" & x"501" => DATA <= x"3e0a";
when "01" & x"502" => DATA <= x"0d46";
when "01" & x"503" => DATA <= x"2020";
when "01" & x"504" => DATA <= x"4669";
when "01" & x"505" => DATA <= x"6c6c";
when "01" & x"506" => DATA <= x"203c";
when "01" & x"507" => DATA <= x"7374";
when "01" & x"508" => DATA <= x"6172";
when "01" & x"509" => DATA <= x"743e";
when "01" & x"50a" => DATA <= x"203c";
when "01" & x"50b" => DATA <= x"656e";
when "01" & x"50c" => DATA <= x"643e";
when "01" & x"50d" => DATA <= x"203c";
when "01" & x"50e" => DATA <= x"6279";
when "01" & x"50f" => DATA <= x"7465";
when "01" & x"510" => DATA <= x"3e0a";
when "01" & x"511" => DATA <= x"0d47";
when "01" & x"512" => DATA <= x"2020";
when "01" & x"513" => DATA <= x"476f";
when "01" & x"514" => DATA <= x"203c";
when "01" & x"515" => DATA <= x"6164";
when "01" & x"516" => DATA <= x"6472";
when "01" & x"517" => DATA <= x"3e0a";
when "01" & x"518" => DATA <= x"0d48";
when "01" & x"519" => DATA <= x"2020";
when "01" & x"51a" => DATA <= x"4865";
when "01" & x"51b" => DATA <= x"7820";
when "01" & x"51c" => DATA <= x"6475";
when "01" & x"51d" => DATA <= x"6d70";
when "01" & x"51e" => DATA <= x"207b";
when "01" & x"51f" => DATA <= x"6164";
when "01" & x"520" => DATA <= x"6472";
when "01" & x"521" => DATA <= x"7d0a";
when "01" & x"522" => DATA <= x"0d4d";
when "01" & x"523" => DATA <= x"2020";
when "01" & x"524" => DATA <= x"4d6f";
when "01" & x"525" => DATA <= x"7665";
when "01" & x"526" => DATA <= x"206d";
when "01" & x"527" => DATA <= x"656d";
when "01" & x"528" => DATA <= x"6f72";
when "01" & x"529" => DATA <= x"7920";
when "01" & x"52a" => DATA <= x"3c73";
when "01" & x"52b" => DATA <= x"6f75";
when "01" & x"52c" => DATA <= x"7263";
when "01" & x"52d" => DATA <= x"653e";
when "01" & x"52e" => DATA <= x"203c";
when "01" & x"52f" => DATA <= x"6465";
when "01" & x"530" => DATA <= x"7374";
when "01" & x"531" => DATA <= x"6e3e";
when "01" & x"532" => DATA <= x"203c";
when "01" & x"533" => DATA <= x"6c65";
when "01" & x"534" => DATA <= x"6e67";
when "01" & x"535" => DATA <= x"7468";
when "01" & x"536" => DATA <= x"3e0a";
when "01" & x"537" => DATA <= x"0d51";
when "01" & x"538" => DATA <= x"2020";
when "01" & x"539" => DATA <= x"5175";
when "01" & x"53a" => DATA <= x"6974";
when "01" & x"53b" => DATA <= x"0a0d";
when "01" & x"53c" => DATA <= x"5220";
when "01" & x"53d" => DATA <= x"2053";
when "01" & x"53e" => DATA <= x"6574";
when "01" & x"53f" => DATA <= x"2072";
when "01" & x"540" => DATA <= x"6567";
when "01" & x"541" => DATA <= x"6973";
when "01" & x"542" => DATA <= x"7465";
when "01" & x"543" => DATA <= x"7220";
when "01" & x"544" => DATA <= x"636f";
when "01" & x"545" => DATA <= x"6e74";
when "01" & x"546" => DATA <= x"656e";
when "01" & x"547" => DATA <= x"7473";
when "01" & x"548" => DATA <= x"203c";
when "01" & x"549" => DATA <= x"7265";
when "01" & x"54a" => DATA <= x"673e";
when "01" & x"54b" => DATA <= x"203c";
when "01" & x"54c" => DATA <= x"7661";
when "01" & x"54d" => DATA <= x"6c75";
when "01" & x"54e" => DATA <= x"653e";
when "01" & x"54f" => DATA <= x"0a0d";
when "01" & x"550" => DATA <= x"5320";
when "01" & x"551" => DATA <= x"2053";
when "01" & x"552" => DATA <= x"7472";
when "01" & x"553" => DATA <= x"696e";
when "01" & x"554" => DATA <= x"6720";
when "01" & x"555" => DATA <= x"7365";
when "01" & x"556" => DATA <= x"6172";
when "01" & x"557" => DATA <= x"6368";
when "01" & x"558" => DATA <= x"203c";
when "01" & x"559" => DATA <= x"7374";
when "01" & x"55a" => DATA <= x"6172";
when "01" & x"55b" => DATA <= x"743e";
when "01" & x"55c" => DATA <= x"203c";
when "01" & x"55d" => DATA <= x"656e";
when "01" & x"55e" => DATA <= x"643e";
when "01" & x"55f" => DATA <= x"203c";
when "01" & x"560" => DATA <= x"7374";
when "01" & x"561" => DATA <= x"7269";
when "01" & x"562" => DATA <= x"6e67";
when "01" & x"563" => DATA <= x"3e0a";
when "01" & x"564" => DATA <= x"0d54";
when "01" & x"565" => DATA <= x"2020";
when "01" & x"566" => DATA <= x"5472";
when "01" & x"567" => DATA <= x"6163";
when "01" & x"568" => DATA <= x"650a";
when "01" & x"569" => DATA <= x"0d56";
when "01" & x"56a" => DATA <= x"2020";
when "01" & x"56b" => DATA <= x"5669";
when "01" & x"56c" => DATA <= x"6577";
when "01" & x"56d" => DATA <= x"2072";
when "01" & x"56e" => DATA <= x"6567";
when "01" & x"56f" => DATA <= x"6973";
when "01" & x"570" => DATA <= x"7465";
when "01" & x"571" => DATA <= x"7220";
when "01" & x"572" => DATA <= x"636f";
when "01" & x"573" => DATA <= x"6e74";
when "01" & x"574" => DATA <= x"656e";
when "01" & x"575" => DATA <= x"7473";
when "01" & x"576" => DATA <= x"0a0d";
when "01" & x"577" => DATA <= x"2a20";
when "01" & x"578" => DATA <= x"204f";
when "01" & x"579" => DATA <= x"5320";
when "01" & x"57a" => DATA <= x"636f";
when "01" & x"57b" => DATA <= x"6d6d";
when "01" & x"57c" => DATA <= x"616e";
when "01" & x"57d" => DATA <= x"640a";
when "01" & x"57e" => DATA <= x"0d3f";
when "01" & x"57f" => DATA <= x"2020";
when "01" & x"580" => DATA <= x"4865";
when "01" & x"581" => DATA <= x"6c70";
when "01" & x"582" => DATA <= x"0a0d";
when "01" & x"583" => DATA <= x"0055";
when "01" & x"584" => DATA <= x"6e6b";
when "01" & x"585" => DATA <= x"6e6f";
when "01" & x"586" => DATA <= x"776e";
when "01" & x"587" => DATA <= x"2063";
when "01" & x"588" => DATA <= x"6f6d";
when "01" & x"589" => DATA <= x"6d61";
when "01" & x"58a" => DATA <= x"6e64";
when "01" & x"58b" => DATA <= x"2c20";
when "01" & x"58c" => DATA <= x"7573";
when "01" & x"58d" => DATA <= x"6520";
when "01" & x"58e" => DATA <= x"3f20";
when "01" & x"58f" => DATA <= x"666f";
when "01" & x"590" => DATA <= x"7220";
when "01" & x"591" => DATA <= x"6865";
when "01" & x"592" => DATA <= x"6c70";
when "01" & x"593" => DATA <= x"2e0a";
when "01" & x"594" => DATA <= x"0d00";
when "01" & x"595" => DATA <= x"542d";
when "01" & x"596" => DATA <= x"532d";
when "01" & x"597" => DATA <= x"2d49";
when "01" & x"598" => DATA <= x"4e54";
when "01" & x"599" => DATA <= x"2d2d";
when "01" & x"59a" => DATA <= x"2d58";
when "01" & x"59b" => DATA <= x"4e5a";
when "01" & x"59c" => DATA <= x"5643";
when "01" & x"59d" => DATA <= x"0046";
when "01" & x"59e" => DATA <= x"696c";
when "01" & x"59f" => DATA <= x"6520";
when "01" & x"5a0" => DATA <= x"6973";
when "01" & x"5a1" => DATA <= x"206e";
when "01" & x"5a2" => DATA <= x"6f74";
when "01" & x"5a3" => DATA <= x"2061";
when "01" & x"5a4" => DATA <= x"2043";
when "01" & x"5a5" => DATA <= x"6973";
when "01" & x"5a6" => DATA <= x"634f";
when "01" & x"5a7" => DATA <= x"5320";
when "01" & x"5a8" => DATA <= x"6669";
when "01" & x"5a9" => DATA <= x"6c65";
when "01" & x"5aa" => DATA <= x"0a0d";
when "01" & x"5ab" => DATA <= x"004e";
when "01" & x"5ac" => DATA <= x"6f20";
when "01" & x"5ad" => DATA <= x"726f";
when "01" & x"5ae" => DATA <= x"6f6d";
when "01" & x"5af" => DATA <= x"0a0d";
when "01" & x"5b0" => DATA <= x"0057";
when "01" & x"5b1" => DATA <= x"4152";
when "01" & x"5b2" => DATA <= x"4e49";
when "01" & x"5b3" => DATA <= x"4e47";
when "01" & x"5b4" => DATA <= x"2120";
when "01" & x"5b5" => DATA <= x"5448";
when "01" & x"5b6" => DATA <= x"4953";
when "01" & x"5b7" => DATA <= x"2057";
when "01" & x"5b8" => DATA <= x"494c";
when "01" & x"5b9" => DATA <= x"4c20";
when "01" & x"5ba" => DATA <= x"464c";
when "01" & x"5bb" => DATA <= x"4153";
when "01" & x"5bc" => DATA <= x"4820";
when "01" & x"5bd" => DATA <= x"5448";
when "01" & x"5be" => DATA <= x"4520";
when "01" & x"5bf" => DATA <= x"4249";
when "01" & x"5c0" => DATA <= x"4f53";
when "01" & x"5c1" => DATA <= x"0a0d";
when "01" & x"5c2" => DATA <= x"5553";
when "01" & x"5c3" => DATA <= x"4520";
when "01" & x"5c4" => DATA <= x"4154";
when "01" & x"5c5" => DATA <= x"2059";
when "01" & x"5c6" => DATA <= x"4f55";
when "01" & x"5c7" => DATA <= x"5220";
when "01" & x"5c8" => DATA <= x"4f57";
when "01" & x"5c9" => DATA <= x"4e20";
when "01" & x"5ca" => DATA <= x"5249";
when "01" & x"5cb" => DATA <= x"534b";
when "01" & x"5cc" => DATA <= x"210a";
when "01" & x"5cd" => DATA <= x"0d0a";
when "01" & x"5ce" => DATA <= x"0d44";
when "01" & x"5cf" => DATA <= x"6f20";
when "01" & x"5d0" => DATA <= x"796f";
when "01" & x"5d1" => DATA <= x"7520";
when "01" & x"5d2" => DATA <= x"7761";
when "01" & x"5d3" => DATA <= x"6e74";
when "01" & x"5d4" => DATA <= x"2074";
when "01" & x"5d5" => DATA <= x"6f20";
when "01" & x"5d6" => DATA <= x"636f";
when "01" & x"5d7" => DATA <= x"6e74";
when "01" & x"5d8" => DATA <= x"696e";
when "01" & x"5d9" => DATA <= x"7565";
when "01" & x"5da" => DATA <= x"3f20";
when "01" & x"5db" => DATA <= x"2859";
when "01" & x"5dc" => DATA <= x"2f4e";
when "01" & x"5dd" => DATA <= x"2920";
when "01" & x"5de" => DATA <= x"3a20";
when "01" & x"5df" => DATA <= x"0046";
when "01" & x"5e0" => DATA <= x"6c61";
when "01" & x"5e1" => DATA <= x"7368";
when "01" & x"5e2" => DATA <= x"2052";
when "01" & x"5e3" => DATA <= x"4f4d";
when "01" & x"5e4" => DATA <= x"2049";
when "01" & x"5e5" => DATA <= x"443d";
when "01" & x"5e6" => DATA <= x"2400";
when "01" & x"5e7" => DATA <= x"0a0d";
when "01" & x"5e8" => DATA <= x"466c";
when "01" & x"5e9" => DATA <= x"6173";
when "01" & x"5ea" => DATA <= x"6869";
when "01" & x"5eb" => DATA <= x"6e67";
when "01" & x"5ec" => DATA <= x"2073";
when "01" & x"5ed" => DATA <= x"6563";
when "01" & x"5ee" => DATA <= x"746f";
when "01" & x"5ef" => DATA <= x"7220";
when "01" & x"5f0" => DATA <= x"0a0d";
when "01" & x"5f1" => DATA <= x"0046";
when "01" & x"5f2" => DATA <= x"6c61";
when "01" & x"5f3" => DATA <= x"7368";
when "01" & x"5f4" => DATA <= x"2063";
when "01" & x"5f5" => DATA <= x"6f6d";
when "01" & x"5f6" => DATA <= x"706c";
when "01" & x"5f7" => DATA <= x"6574";
when "01" & x"5f8" => DATA <= x"6564";
when "01" & x"5f9" => DATA <= x"2073";
when "01" & x"5fa" => DATA <= x"7563";
when "01" & x"5fb" => DATA <= x"6365";
when "01" & x"5fc" => DATA <= x"7373";
when "01" & x"5fd" => DATA <= x"6675";
when "01" & x"5fe" => DATA <= x"6c6c";
when "01" & x"5ff" => DATA <= x"790a";
when "01" & x"600" => DATA <= x"0d00";
when "01" & x"601" => DATA <= x"466c";
when "01" & x"602" => DATA <= x"6173";
when "01" & x"603" => DATA <= x"6820";
when "01" & x"604" => DATA <= x"6572";
when "01" & x"605" => DATA <= x"726f";
when "01" & x"606" => DATA <= x"7220";
when "01" & x"607" => DATA <= x"6174";
when "01" & x"608" => DATA <= x"2000";
when "01" & x"609" => DATA <= x"4d6f";
when "01" & x"60a" => DATA <= x"6e54";
when "01" & x"60b" => DATA <= x"7565";
when "01" & x"60c" => DATA <= x"5765";
when "01" & x"60d" => DATA <= x"6454";
when "01" & x"60e" => DATA <= x"6875";
when "01" & x"60f" => DATA <= x"4672";
when "01" & x"610" => DATA <= x"6953";
when "01" & x"611" => DATA <= x"6174";
when "01" & x"612" => DATA <= x"5375";
when "01" & x"613" => DATA <= x"6e00";
when "01" & x"614" => DATA <= x"4a61";
when "01" & x"615" => DATA <= x"6e46";
when "01" & x"616" => DATA <= x"6562";
when "01" & x"617" => DATA <= x"4d61";
when "01" & x"618" => DATA <= x"7241";
when "01" & x"619" => DATA <= x"7072";
when "01" & x"61a" => DATA <= x"4d61";
when "01" & x"61b" => DATA <= x"794a";
when "01" & x"61c" => DATA <= x"756e";
when "01" & x"61d" => DATA <= x"4a75";
when "01" & x"61e" => DATA <= x"6c41";
when "01" & x"61f" => DATA <= x"7567";
when "01" & x"620" => DATA <= x"5365";
when "01" & x"621" => DATA <= x"704f";
when "01" & x"622" => DATA <= x"6374";
when "01" & x"623" => DATA <= x"4e6f";
when "01" & x"624" => DATA <= x"7644";
when "01" & x"625" => DATA <= x"6563";
when "01" & x"626" => DATA <= x"000a";
when "01" & x"627" => DATA <= x"0d42";
when "01" & x"628" => DATA <= x"7573";
when "01" & x"629" => DATA <= x"2065";
when "01" & x"62a" => DATA <= x"7272";
when "01" & x"62b" => DATA <= x"6f72";
when "01" & x"62c" => DATA <= x"2061";
when "01" & x"62d" => DATA <= x"7420";
when "01" & x"62e" => DATA <= x"2400";
when "01" & x"62f" => DATA <= x"0a0d";
when "01" & x"630" => DATA <= x"4164";
when "01" & x"631" => DATA <= x"6472";
when "01" & x"632" => DATA <= x"6573";
when "01" & x"633" => DATA <= x"7320";
when "01" & x"634" => DATA <= x"6572";
when "01" & x"635" => DATA <= x"726f";
when "01" & x"636" => DATA <= x"7220";
when "01" & x"637" => DATA <= x"6578";
when "01" & x"638" => DATA <= x"6365";
when "01" & x"639" => DATA <= x"7074";
when "01" & x"63a" => DATA <= x"696f";
when "01" & x"63b" => DATA <= x"6e20";
when "01" & x"63c" => DATA <= x"6174";
when "01" & x"63d" => DATA <= x"2024";
when "01" & x"63e" => DATA <= x"0020";
when "01" & x"63f" => DATA <= x"4163";
when "01" & x"640" => DATA <= x"6365";
when "01" & x"641" => DATA <= x"7373";
when "01" & x"642" => DATA <= x"2074";
when "01" & x"643" => DATA <= x"7970";
when "01" & x"644" => DATA <= x"6526";
when "01" & x"645" => DATA <= x"6675";
when "01" & x"646" => DATA <= x"6e63";
when "01" & x"647" => DATA <= x"7469";
when "01" & x"648" => DATA <= x"6f6e";
when "01" & x"649" => DATA <= x"3a00";
when "01" & x"64a" => DATA <= x"2041";
when "01" & x"64b" => DATA <= x"6363";
when "01" & x"64c" => DATA <= x"6573";
when "01" & x"64d" => DATA <= x"7320";
when "01" & x"64e" => DATA <= x"6164";
when "01" & x"64f" => DATA <= x"6472";
when "01" & x"650" => DATA <= x"6573";
when "01" & x"651" => DATA <= x"7320";
when "01" & x"652" => DATA <= x"2020";
when "01" & x"653" => DATA <= x"2020";
when "01" & x"654" => DATA <= x"203a";
when "01" & x"655" => DATA <= x"0020";
when "01" & x"656" => DATA <= x"496e";
when "01" & x"657" => DATA <= x"7374";
when "01" & x"658" => DATA <= x"7275";
when "01" & x"659" => DATA <= x"6374";
when "01" & x"65a" => DATA <= x"696f";
when "01" & x"65b" => DATA <= x"6e20";
when "01" & x"65c" => DATA <= x"7265";
when "01" & x"65d" => DATA <= x"6769";
when "01" & x"65e" => DATA <= x"7374";
when "01" & x"65f" => DATA <= x"6572";
when "01" & x"660" => DATA <= x"3a00";
when "01" & x"661" => DATA <= x"2053";
when "01" & x"662" => DATA <= x"7461";
when "01" & x"663" => DATA <= x"7475";
when "01" & x"664" => DATA <= x"7320";
when "01" & x"665" => DATA <= x"7265";
when "01" & x"666" => DATA <= x"6769";
when "01" & x"667" => DATA <= x"7374";
when "01" & x"668" => DATA <= x"6572";
when "01" & x"669" => DATA <= x"2020";
when "01" & x"66a" => DATA <= x"2020";
when "01" & x"66b" => DATA <= x"203a";
when "01" & x"66c" => DATA <= x"5452";
when "01" & x"66d" => DATA <= x"534d";
when "01" & x"66e" => DATA <= x"2d49";
when "01" & x"66f" => DATA <= x"4e54";
when "01" & x"670" => DATA <= x"2d2d";
when "01" & x"671" => DATA <= x"2d58";
when "01" & x"672" => DATA <= x"4e5a";
when "01" & x"673" => DATA <= x"5643";
when "01" & x"674" => DATA <= x"0a0d";
when "01" & x"675" => DATA <= x"2020";
when "01" & x"676" => DATA <= x"2020";
when "01" & x"677" => DATA <= x"2020";
when "01" & x"678" => DATA <= x"2020";
when "01" & x"679" => DATA <= x"2020";
when "01" & x"67a" => DATA <= x"2020";
when "01" & x"67b" => DATA <= x"2020";
when "01" & x"67c" => DATA <= x"2020";
when "01" & x"67d" => DATA <= x"2020";
when "01" & x"67e" => DATA <= x"2020";
when "01" & x"67f" => DATA <= x"2020";
when "01" & x"680" => DATA <= x"0000";
when "01" & x"681" => DATA <= x"0000";
when "01" & x"682" => DATA <= x"8000";
when "01" & x"683" => DATA <= x"0100";
when "01" & x"684" => DATA <= x"496c";
when "01" & x"685" => DATA <= x"6c65";
when "01" & x"686" => DATA <= x"6761";
when "01" & x"687" => DATA <= x"6c20";
when "01" & x"688" => DATA <= x"696e";
when "01" & x"689" => DATA <= x"7374";
when "01" & x"68a" => DATA <= x"7275";
when "01" & x"68b" => DATA <= x"6374";
when "01" & x"68c" => DATA <= x"696f";
when "01" & x"68d" => DATA <= x"6e00";
when "01" & x"68e" => DATA <= x"8000";
when "01" & x"68f" => DATA <= x"0104";
when "01" & x"690" => DATA <= x"556e";
when "01" & x"691" => DATA <= x"6b6e";
when "01" & x"692" => DATA <= x"6f77";
when "01" & x"693" => DATA <= x"6e20";
when "01" & x"694" => DATA <= x"4952";
when "01" & x"695" => DATA <= x"5120";
when "01" & x"696" => DATA <= x"6174";
when "01" & x"697" => DATA <= x"2026";
when "01" & x"698" => DATA <= x"0000";
when "01" & x"699" => DATA <= x"0000";
when "01" & x"69a" => DATA <= x"8000";
when "01" & x"69b" => DATA <= x"0169";
when "01" & x"69c" => DATA <= x"496e";
when "01" & x"69d" => DATA <= x"7465";
when "01" & x"69e" => DATA <= x"6765";
when "01" & x"69f" => DATA <= x"7220";
when "01" & x"6a0" => DATA <= x"6469";
when "01" & x"6a1" => DATA <= x"7669";
when "01" & x"6a2" => DATA <= x"6465";
when "01" & x"6a3" => DATA <= x"2062";
when "01" & x"6a4" => DATA <= x"7920";
when "01" & x"6a5" => DATA <= x"7a65";
when "01" & x"6a6" => DATA <= x"726f";
when "01" & x"6a7" => DATA <= x"0000";
when "01" & x"6a8" => DATA <= x"8000";
when "01" & x"6a9" => DATA <= x"0008";
when "01" & x"6aa" => DATA <= x"5072";
when "01" & x"6ab" => DATA <= x"6976";
when "01" & x"6ac" => DATA <= x"696c";
when "01" & x"6ad" => DATA <= x"6567";
when "01" & x"6ae" => DATA <= x"6520";
when "01" & x"6af" => DATA <= x"7669";
when "01" & x"6b0" => DATA <= x"6f6c";
when "01" & x"6b1" => DATA <= x"6174";
when "01" & x"6b2" => DATA <= x"696f";
when "01" & x"6b3" => DATA <= x"6e00";
when "01" & x"6b4" => DATA <= x"0000";
when "01" & x"6b5" => DATA <= x"0001";
when "01" & x"6b6" => DATA <= x"4f75";
when "01" & x"6b7" => DATA <= x"7420";
when "01" & x"6b8" => DATA <= x"6f66";
when "01" & x"6b9" => DATA <= x"2072";
when "01" & x"6ba" => DATA <= x"616e";
when "01" & x"6bb" => DATA <= x"6765";
when "01" & x"6bc" => DATA <= x"0000";
when "01" & x"6bd" => DATA <= x"0000";
when "01" & x"6be" => DATA <= x"0000";
when "01" & x"6bf" => DATA <= x"0011";
when "01" & x"6c0" => DATA <= x"4573";
when "01" & x"6c1" => DATA <= x"6361";
when "01" & x"6c2" => DATA <= x"7065";
when "01" & x"6c3" => DATA <= x"0000";
when "01" & x"6c4" => DATA <= x"0000";
when "01" & x"6c5" => DATA <= x"00ff";
when "01" & x"6c6" => DATA <= x"5468";
when "01" & x"6c7" => DATA <= x"6973";
when "01" & x"6c8" => DATA <= x"2069";
when "01" & x"6c9" => DATA <= x"7320";
when "01" & x"6ca" => DATA <= x"6e6f";
when "01" & x"6cb" => DATA <= x"7420";
when "01" & x"6cc" => DATA <= x"6120";
when "01" & x"6cd" => DATA <= x"6c61";
when "01" & x"6ce" => DATA <= x"6e67";
when "01" & x"6cf" => DATA <= x"7561";
when "01" & x"6d0" => DATA <= x"6765";
when "01" & x"6d1" => DATA <= x"0000";
when "01" & x"6d2" => DATA <= x"0000";
when "01" & x"6d3" => DATA <= x"00ff";
when "01" & x"6d4" => DATA <= x"4920";
when "01" & x"6d5" => DATA <= x"6361";
when "01" & x"6d6" => DATA <= x"6e6e";
when "01" & x"6d7" => DATA <= x"6f74";
when "01" & x"6d8" => DATA <= x"2072";
when "01" & x"6d9" => DATA <= x"756e";
when "01" & x"6da" => DATA <= x"2074";
when "01" & x"6db" => DATA <= x"6869";
when "01" & x"6dc" => DATA <= x"7320";
when "01" & x"6dd" => DATA <= x"636f";
when "01" & x"6de" => DATA <= x"6465";
when "01" & x"6df" => DATA <= x"0000";
when "01" & x"6e0" => DATA <= x"0000";
when "01" & x"6e1" => DATA <= x"00ff";
when "01" & x"6e2" => DATA <= x"556e";
when "01" & x"6e3" => DATA <= x"6b6e";
when "01" & x"6e4" => DATA <= x"6f77";
when "01" & x"6e5" => DATA <= x"6e20";
when "01" & x"6e6" => DATA <= x"6578";
when "01" & x"6e7" => DATA <= x"6365";
when "01" & x"6e8" => DATA <= x"7074";
when "01" & x"6e9" => DATA <= x"696f";
when "01" & x"6ea" => DATA <= x"6e00";
when "01" & x"6eb" => DATA <= x"0000";
when "01" & x"6ec" => DATA <= x"0000";
when "01" & x"6ed" => DATA <= x"00ff";
when "01" & x"6ee" => DATA <= x"4e6f";
when "01" & x"6ef" => DATA <= x"7420";
when "01" & x"6f0" => DATA <= x"7375";
when "01" & x"6f1" => DATA <= x"7070";
when "01" & x"6f2" => DATA <= x"6f72";
when "01" & x"6f3" => DATA <= x"7465";
when "01" & x"6f4" => DATA <= x"6400";
when "01" & x"6f5" => DATA <= x"0000";
when "01" & x"6f6" => DATA <= x"0000";
when "01" & x"6f7" => DATA <= x"016a";
when "01" & x"6f8" => DATA <= x"4261";
when "01" & x"6f9" => DATA <= x"6420";
when "01" & x"6fa" => DATA <= x"6261";
when "01" & x"6fb" => DATA <= x"7365";
when "01" & x"6fc" => DATA <= x"0000";
when "01" & x"6fd" => DATA <= x"0000";
when "01" & x"6fe" => DATA <= x"0000";
when "01" & x"6ff" => DATA <= x"016b";
when "01" & x"700" => DATA <= x"4261";
when "01" & x"701" => DATA <= x"6420";
when "01" & x"702" => DATA <= x"6e75";
when "01" & x"703" => DATA <= x"6d62";
when "01" & x"704" => DATA <= x"6572";
when "01" & x"705" => DATA <= x"0000";
when "01" & x"706" => DATA <= x"0000";
when "01" & x"707" => DATA <= x"016c";
when "01" & x"708" => DATA <= x"4e75";
when "01" & x"709" => DATA <= x"6d62";
when "01" & x"70a" => DATA <= x"6572";
when "01" & x"70b" => DATA <= x"2074";
when "01" & x"70c" => DATA <= x"6f6f";
when "01" & x"70d" => DATA <= x"2062";
when "01" & x"70e" => DATA <= x"6967";
when "01" & x"70f" => DATA <= x"0000";
when "01" & x"710" => DATA <= x"0000";
when "01" & x"711" => DATA <= x"01b0";
when "01" & x"712" => DATA <= x"4261";
when "01" & x"713" => DATA <= x"6420";
when "01" & x"714" => DATA <= x"656e";
when "01" & x"715" => DATA <= x"7669";
when "01" & x"716" => DATA <= x"726f";
when "01" & x"717" => DATA <= x"6e6d";
when "01" & x"718" => DATA <= x"656e";
when "01" & x"719" => DATA <= x"7420";
when "01" & x"71a" => DATA <= x"6e75";
when "01" & x"71b" => DATA <= x"6d62";
when "01" & x"71c" => DATA <= x"6572";
when "01" & x"71d" => DATA <= x"0000";
when "01" & x"71e" => DATA <= x"0000";
when "01" & x"71f" => DATA <= x"01e6";
when "01" & x"720" => DATA <= x"4e6f";
when "01" & x"721" => DATA <= x"2073";
when "01" & x"722" => DATA <= x"7563";
when "01" & x"723" => DATA <= x"6820";
when "01" & x"724" => DATA <= x"5357";
when "01" & x"725" => DATA <= x"4900";
when "01" & x"726" => DATA <= x"0000";
when "01" & x"727" => DATA <= x"01a0";
when "01" & x"728" => DATA <= x"4261";
when "01" & x"729" => DATA <= x"6420";
when "01" & x"72a" => DATA <= x"7665";
when "01" & x"72b" => DATA <= x"6374";
when "01" & x"72c" => DATA <= x"6f72";
when "01" & x"72d" => DATA <= x"206e";
when "01" & x"72e" => DATA <= x"756d";
when "01" & x"72f" => DATA <= x"6265";
when "01" & x"730" => DATA <= x"7200";
when "01" & x"731" => DATA <= x"0000";
when "01" & x"732" => DATA <= x"0000";
when "01" & x"733" => DATA <= x"01e2";
when "01" & x"734" => DATA <= x"5265";
when "01" & x"735" => DATA <= x"7475";
when "01" & x"736" => DATA <= x"726e";
when "01" & x"737" => DATA <= x"2063";
when "01" & x"738" => DATA <= x"6f64";
when "01" & x"739" => DATA <= x"6520";
when "01" & x"73a" => DATA <= x"6c69";
when "01" & x"73b" => DATA <= x"6d69";
when "01" & x"73c" => DATA <= x"7420";
when "01" & x"73d" => DATA <= x"6578";
when "01" & x"73e" => DATA <= x"6365";
when "01" & x"73f" => DATA <= x"6564";
when "01" & x"740" => DATA <= x"6564";
when "01" & x"741" => DATA <= x"0000";
when "01" & x"742" => DATA <= x"0000";
when "01" & x"743" => DATA <= x"01e4";
when "01" & x"744" => DATA <= x"4275";
when "01" & x"745" => DATA <= x"6666";
when "01" & x"746" => DATA <= x"6572";
when "01" & x"747" => DATA <= x"206f";
when "01" & x"748" => DATA <= x"7665";
when "01" & x"749" => DATA <= x"7266";
when "01" & x"74a" => DATA <= x"6c6f";
when "01" & x"74b" => DATA <= x"7700";
when "01" & x"74c" => DATA <= x"0000";
when "01" & x"74d" => DATA <= x"01e6";
when "01" & x"74e" => DATA <= x"5357";
when "01" & x"74f" => DATA <= x"4920";
when "01" & x"750" => DATA <= x"6e61";
when "01" & x"751" => DATA <= x"6d65";
when "01" & x"752" => DATA <= x"206e";
when "01" & x"753" => DATA <= x"6f74";
when "01" & x"754" => DATA <= x"206b";
when "01" & x"755" => DATA <= x"6e6f";
when "01" & x"756" => DATA <= x"776e";
when "01" & x"757" => DATA <= x"0000";
when "01" & x"758" => DATA <= x"0000";
when "01" & x"759" => DATA <= x"02c2";
when "01" & x"75a" => DATA <= x"556e";
when "01" & x"75b" => DATA <= x"6b6e";
when "01" & x"75c" => DATA <= x"6f77";
when "01" & x"75d" => DATA <= x"6e20";
when "01" & x"75e" => DATA <= x"2725";
when "01" & x"75f" => DATA <= x"2720";
when "01" & x"760" => DATA <= x"6669";
when "01" & x"761" => DATA <= x"656c";
when "01" & x"762" => DATA <= x"6400";
when "01" & x"763" => DATA <= x"0000";
when "01" & x"764" => DATA <= x"0000";
when "01" & x"765" => DATA <= x"0306";
when "01" & x"766" => DATA <= x"4261";
when "01" & x"767" => DATA <= x"6420";
when "01" & x"768" => DATA <= x"7374";
when "01" & x"769" => DATA <= x"6174";
when "01" & x"76a" => DATA <= x"696f";
when "01" & x"76b" => DATA <= x"6e20";
when "01" & x"76c" => DATA <= x"6e75";
when "01" & x"76d" => DATA <= x"6d62";
when "01" & x"76e" => DATA <= x"6572";
when "01" & x"76f" => DATA <= x"0000";
when "01" & x"770" => DATA <= x"0000";
when "01" & x"771" => DATA <= x"0307";
when "01" & x"772" => DATA <= x"4261";
when "01" & x"773" => DATA <= x"6420";
when "01" & x"774" => DATA <= x"6e65";
when "01" & x"775" => DATA <= x"7477";
when "01" & x"776" => DATA <= x"6f72";
when "01" & x"777" => DATA <= x"6b20";
when "01" & x"778" => DATA <= x"6e75";
when "01" & x"779" => DATA <= x"6d62";
when "01" & x"77a" => DATA <= x"6572";
when "01" & x"77b" => DATA <= x"0000";
when "01" & x"77c" => DATA <= x"0000";
when "01" & x"77d" => DATA <= x"0401";
when "01" & x"77e" => DATA <= x"4261";
when "01" & x"77f" => DATA <= x"6420";
when "01" & x"780" => DATA <= x"4653";
when "01" & x"781" => DATA <= x"436f";
when "01" & x"782" => DATA <= x"6e74";
when "01" & x"783" => DATA <= x"726f";
when "01" & x"784" => DATA <= x"6c20";
when "01" & x"785" => DATA <= x"6361";
when "01" & x"786" => DATA <= x"6c6c";
when "01" & x"787" => DATA <= x"0000";
when "01" & x"788" => DATA <= x"0000";
when "01" & x"789" => DATA <= x"0807";
when "01" & x"78a" => DATA <= x"556e";
when "01" & x"78b" => DATA <= x"616c";
when "01" & x"78c" => DATA <= x"6967";
when "01" & x"78d" => DATA <= x"6e65";
when "01" & x"78e" => DATA <= x"6420";
when "01" & x"78f" => DATA <= x"6164";
when "01" & x"790" => DATA <= x"6472";
when "01" & x"791" => DATA <= x"6573";
when "01" & x"792" => DATA <= x"7300";
when "01" & x"793" => DATA <= x"0000";
when "01" & x"794" => DATA <= x"0000";
when "01" & x"795" => DATA <= x"0000";
when "01" & x"796" => DATA <= x"0005";
when "01" & x"797" => DATA <= x"0005";
when "01" & x"798" => DATA <= x"0205";
when "01" & x"799" => DATA <= x"080e";
when "01" & x"79a" => DATA <= x"0401";
when "01" & x"79b" => DATA <= x"0105";
when "01" & x"79c" => DATA <= x"0001";
when "01" & x"79d" => DATA <= x"2010";
when "01" & x"79e" => DATA <= x"0d00";
when "01" & x"79f" => DATA <= x"0480";
when "01" & x"7a0" => DATA <= x"0500";
when "01" & x"7a1" => DATA <= x"0500";
when "01" & x"7a2" => DATA <= x"0500";
when "01" & x"7a3" => DATA <= x"0000";
when "01" & x"7a4" => DATA <= x"0509";
when "01" & x"7a5" => DATA <= x"0500";
when "01" & x"7a6" => DATA <= x"0818";
when "01" & x"7a7" => DATA <= x"0001";
when "01" & x"7a8" => DATA <= x"0d80";
when "01" & x"7a9" => DATA <= x"0480";
when "01" & x"7aa" => DATA <= x"0000";
when "01" & x"7ab" => DATA <= x"0000";
when "01" & x"7ac" => DATA <= x"003f";
when "01" & x"7ad" => DATA <= x"09ea";
when "01" & x"7ae" => DATA <= x"4f53";
when "01" & x"7af" => DATA <= x"5f57";
when "01" & x"7b0" => DATA <= x"7269";
when "01" & x"7b1" => DATA <= x"7465";
when "01" & x"7b2" => DATA <= x"4300";
when "01" & x"7b3" => DATA <= x"0000";
when "01" & x"7b4" => DATA <= x"0000";
when "01" & x"7b5" => DATA <= x"0001";
when "01" & x"7b6" => DATA <= x"003f";
when "01" & x"7b7" => DATA <= x"09f0";
when "01" & x"7b8" => DATA <= x"4f53";
when "01" & x"7b9" => DATA <= x"5f57";
when "01" & x"7ba" => DATA <= x"7269";
when "01" & x"7bb" => DATA <= x"7465";
when "01" & x"7bc" => DATA <= x"5300";
when "01" & x"7bd" => DATA <= x"0000";
when "01" & x"7be" => DATA <= x"0000";
when "01" & x"7bf" => DATA <= x"0002";
when "01" & x"7c0" => DATA <= x"003f";
when "01" & x"7c1" => DATA <= x"0a02";
when "01" & x"7c2" => DATA <= x"4f53";
when "01" & x"7c3" => DATA <= x"5f57";
when "01" & x"7c4" => DATA <= x"7269";
when "01" & x"7c5" => DATA <= x"7465";
when "01" & x"7c6" => DATA <= x"3000";
when "01" & x"7c7" => DATA <= x"0000";
when "01" & x"7c8" => DATA <= x"0000";
when "01" & x"7c9" => DATA <= x"0003";
when "01" & x"7ca" => DATA <= x"003f";
when "01" & x"7cb" => DATA <= x"0a16";
when "01" & x"7cc" => DATA <= x"4f53";
when "01" & x"7cd" => DATA <= x"5f4e";
when "01" & x"7ce" => DATA <= x"6577";
when "01" & x"7cf" => DATA <= x"4c69";
when "01" & x"7d0" => DATA <= x"6e65";
when "01" & x"7d1" => DATA <= x"0000";
when "01" & x"7d2" => DATA <= x"0000";
when "01" & x"7d3" => DATA <= x"0004";
when "01" & x"7d4" => DATA <= x"0000";
when "01" & x"7d5" => DATA <= x"0410";
when "01" & x"7d6" => DATA <= x"4f53";
when "01" & x"7d7" => DATA <= x"5f52";
when "01" & x"7d8" => DATA <= x"6561";
when "01" & x"7d9" => DATA <= x"6443";
when "01" & x"7da" => DATA <= x"0000";
when "01" & x"7db" => DATA <= x"0000";
when "01" & x"7dc" => DATA <= x"0000";
when "01" & x"7dd" => DATA <= x"0005";
when "01" & x"7de" => DATA <= x"0000";
when "01" & x"7df" => DATA <= x"0414";
when "01" & x"7e0" => DATA <= x"4f53";
when "01" & x"7e1" => DATA <= x"5f43";
when "01" & x"7e2" => DATA <= x"4c49";
when "01" & x"7e3" => DATA <= x"0000";
when "01" & x"7e4" => DATA <= x"0000";
when "01" & x"7e5" => DATA <= x"0006";
when "01" & x"7e6" => DATA <= x"0000";
when "01" & x"7e7" => DATA <= x"0418";
when "01" & x"7e8" => DATA <= x"4f53";
when "01" & x"7e9" => DATA <= x"5f42";
when "01" & x"7ea" => DATA <= x"7974";
when "01" & x"7eb" => DATA <= x"6500";
when "01" & x"7ec" => DATA <= x"0000";
when "01" & x"7ed" => DATA <= x"0007";
when "01" & x"7ee" => DATA <= x"0000";
when "01" & x"7ef" => DATA <= x"041c";
when "01" & x"7f0" => DATA <= x"4f53";
when "01" & x"7f1" => DATA <= x"5f57";
when "01" & x"7f2" => DATA <= x"6f72";
when "01" & x"7f3" => DATA <= x"6400";
when "01" & x"7f4" => DATA <= x"0000";
when "01" & x"7f5" => DATA <= x"0008";
when "01" & x"7f6" => DATA <= x"0000";
when "01" & x"7f7" => DATA <= x"0420";
when "01" & x"7f8" => DATA <= x"4f53";
when "01" & x"7f9" => DATA <= x"5f46";
when "01" & x"7fa" => DATA <= x"696c";
when "01" & x"7fb" => DATA <= x"6500";
when "01" & x"7fc" => DATA <= x"0000";
when "01" & x"7fd" => DATA <= x"0009";
when "01" & x"7fe" => DATA <= x"0000";
when "01" & x"7ff" => DATA <= x"0424";
when "01" & x"800" => DATA <= x"4f53";
when "01" & x"801" => DATA <= x"5f41";
when "01" & x"802" => DATA <= x"7267";
when "01" & x"803" => DATA <= x"7300";
when "01" & x"804" => DATA <= x"0000";
when "01" & x"805" => DATA <= x"000a";
when "01" & x"806" => DATA <= x"0000";
when "01" & x"807" => DATA <= x"0428";
when "01" & x"808" => DATA <= x"4f53";
when "01" & x"809" => DATA <= x"5f42";
when "01" & x"80a" => DATA <= x"4765";
when "01" & x"80b" => DATA <= x"7400";
when "01" & x"80c" => DATA <= x"0000";
when "01" & x"80d" => DATA <= x"000b";
when "01" & x"80e" => DATA <= x"0000";
when "01" & x"80f" => DATA <= x"042c";
when "01" & x"810" => DATA <= x"4f53";
when "01" & x"811" => DATA <= x"5f42";
when "01" & x"812" => DATA <= x"5075";
when "01" & x"813" => DATA <= x"7400";
when "01" & x"814" => DATA <= x"0000";
when "01" & x"815" => DATA <= x"000c";
when "01" & x"816" => DATA <= x"0000";
when "01" & x"817" => DATA <= x"0430";
when "01" & x"818" => DATA <= x"4f53";
when "01" & x"819" => DATA <= x"5f47";
when "01" & x"81a" => DATA <= x"4250";
when "01" & x"81b" => DATA <= x"4200";
when "01" & x"81c" => DATA <= x"0000";
when "01" & x"81d" => DATA <= x"000d";
when "01" & x"81e" => DATA <= x"0000";
when "01" & x"81f" => DATA <= x"0434";
when "01" & x"820" => DATA <= x"4f53";
when "01" & x"821" => DATA <= x"5f46";
when "01" & x"822" => DATA <= x"696e";
when "01" & x"823" => DATA <= x"6400";
when "01" & x"824" => DATA <= x"0000";
when "01" & x"825" => DATA <= x"000e";
when "01" & x"826" => DATA <= x"0000";
when "01" & x"827" => DATA <= x"0438";
when "01" & x"828" => DATA <= x"4f53";
when "01" & x"829" => DATA <= x"5f52";
when "01" & x"82a" => DATA <= x"6561";
when "01" & x"82b" => DATA <= x"644c";
when "01" & x"82c" => DATA <= x"696e";
when "01" & x"82d" => DATA <= x"6500";
when "01" & x"82e" => DATA <= x"0000";
when "01" & x"82f" => DATA <= x"000f";
when "01" & x"830" => DATA <= x"003f";
when "01" & x"831" => DATA <= x"0dfc";
when "01" & x"832" => DATA <= x"4f53";
when "01" & x"833" => DATA <= x"5f43";
when "01" & x"834" => DATA <= x"6f6e";
when "01" & x"835" => DATA <= x"7472";
when "01" & x"836" => DATA <= x"6f6c";
when "01" & x"837" => DATA <= x"0000";
when "01" & x"838" => DATA <= x"0000";
when "01" & x"839" => DATA <= x"0010";
when "01" & x"83a" => DATA <= x"003f";
when "01" & x"83b" => DATA <= x"0e34";
when "01" & x"83c" => DATA <= x"4f53";
when "01" & x"83d" => DATA <= x"5f47";
when "01" & x"83e" => DATA <= x"6574";
when "01" & x"83f" => DATA <= x"456e";
when "01" & x"840" => DATA <= x"7600";
when "01" & x"841" => DATA <= x"0000";
when "01" & x"842" => DATA <= x"0000";
when "01" & x"843" => DATA <= x"0011";
when "01" & x"844" => DATA <= x"003f";
when "01" & x"845" => DATA <= x"0e48";
when "01" & x"846" => DATA <= x"4f53";
when "01" & x"847" => DATA <= x"5f45";
when "01" & x"848" => DATA <= x"7869";
when "01" & x"849" => DATA <= x"7400";
when "01" & x"84a" => DATA <= x"0000";
when "01" & x"84b" => DATA <= x"0012";
when "01" & x"84c" => DATA <= x"003f";
when "01" & x"84d" => DATA <= x"0e4e";
when "01" & x"84e" => DATA <= x"4f53";
when "01" & x"84f" => DATA <= x"5f53";
when "01" & x"850" => DATA <= x"6574";
when "01" & x"851" => DATA <= x"456e";
when "01" & x"852" => DATA <= x"7600";
when "01" & x"853" => DATA <= x"0000";
when "01" & x"854" => DATA <= x"0000";
when "01" & x"855" => DATA <= x"0013";
when "01" & x"856" => DATA <= x"003f";
when "01" & x"857" => DATA <= x"0e9e";
when "01" & x"858" => DATA <= x"4f53";
when "01" & x"859" => DATA <= x"5f49";
when "01" & x"85a" => DATA <= x"6e74";
when "01" & x"85b" => DATA <= x"4f6e";
when "01" & x"85c" => DATA <= x"0000";
when "01" & x"85d" => DATA <= x"0000";
when "01" & x"85e" => DATA <= x"0000";
when "01" & x"85f" => DATA <= x"0014";
when "01" & x"860" => DATA <= x"003f";
when "01" & x"861" => DATA <= x"0ea4";
when "01" & x"862" => DATA <= x"4f53";
when "01" & x"863" => DATA <= x"5f49";
when "01" & x"864" => DATA <= x"6e74";
when "01" & x"865" => DATA <= x"4f66";
when "01" & x"866" => DATA <= x"6600";
when "01" & x"867" => DATA <= x"0000";
when "01" & x"868" => DATA <= x"0000";
when "01" & x"869" => DATA <= x"0015";
when "01" & x"86a" => DATA <= x"003f";
when "01" & x"86b" => DATA <= x"0eaa";
when "01" & x"86c" => DATA <= x"4f53";
when "01" & x"86d" => DATA <= x"5f43";
when "01" & x"86e" => DATA <= x"616c";
when "01" & x"86f" => DATA <= x"6c42";
when "01" & x"870" => DATA <= x"6163";
when "01" & x"871" => DATA <= x"6b00";
when "01" & x"872" => DATA <= x"0000";
when "01" & x"873" => DATA <= x"0016";
when "01" & x"874" => DATA <= x"003f";
when "01" & x"875" => DATA <= x"0eca";
when "01" & x"876" => DATA <= x"4f53";
when "01" & x"877" => DATA <= x"5f45";
when "01" & x"878" => DATA <= x"6e74";
when "01" & x"879" => DATA <= x"6572";
when "01" & x"87a" => DATA <= x"4f53";
when "01" & x"87b" => DATA <= x"0000";
when "01" & x"87c" => DATA <= x"0000";
when "01" & x"87d" => DATA <= x"0018";
when "01" & x"87e" => DATA <= x"003f";
when "01" & x"87f" => DATA <= x"0ed0";
when "01" & x"880" => DATA <= x"4f53";
when "01" & x"881" => DATA <= x"5f42";
when "01" & x"882" => DATA <= x"7265";
when "01" & x"883" => DATA <= x"616b";
when "01" & x"884" => DATA <= x"4374";
when "01" & x"885" => DATA <= x"726c";
when "01" & x"886" => DATA <= x"0000";
when "01" & x"887" => DATA <= x"0000";
when "01" & x"888" => DATA <= x"0000";
when "01" & x"889" => DATA <= x"0019";
when "01" & x"88a" => DATA <= x"003f";
when "01" & x"88b" => DATA <= x"0ef0";
when "01" & x"88c" => DATA <= x"4f53";
when "01" & x"88d" => DATA <= x"5f55";
when "01" & x"88e" => DATA <= x"6e75";
when "01" & x"88f" => DATA <= x"7365";
when "01" & x"890" => DATA <= x"6453";
when "01" & x"891" => DATA <= x"5749";
when "01" & x"892" => DATA <= x"0000";
when "01" & x"893" => DATA <= x"0000";
when "01" & x"894" => DATA <= x"0000";
when "01" & x"895" => DATA <= x"001c";
when "01" & x"896" => DATA <= x"0000";
when "01" & x"897" => DATA <= x"0468";
when "01" & x"898" => DATA <= x"4f53";
when "01" & x"899" => DATA <= x"5f4d";
when "01" & x"89a" => DATA <= x"6f75";
when "01" & x"89b" => DATA <= x"7365";
when "01" & x"89c" => DATA <= x"0000";
when "01" & x"89d" => DATA <= x"0000";
when "01" & x"89e" => DATA <= x"0000";
when "01" & x"89f" => DATA <= x"0021";
when "01" & x"8a0" => DATA <= x"003f";
when "01" & x"8a1" => DATA <= x"0fd0";
when "01" & x"8a2" => DATA <= x"4f53";
when "01" & x"8a3" => DATA <= x"5f52";
when "01" & x"8a4" => DATA <= x"6561";
when "01" & x"8a5" => DATA <= x"6455";
when "01" & x"8a6" => DATA <= x"6e73";
when "01" & x"8a7" => DATA <= x"6967";
when "01" & x"8a8" => DATA <= x"6e65";
when "01" & x"8a9" => DATA <= x"6400";
when "01" & x"8aa" => DATA <= x"0000";
when "01" & x"8ab" => DATA <= x"0028";
when "01" & x"8ac" => DATA <= x"003f";
when "01" & x"8ad" => DATA <= x"10ca";
when "01" & x"8ae" => DATA <= x"4f53";
when "01" & x"8af" => DATA <= x"5f42";
when "01" & x"8b0" => DATA <= x"696e";
when "01" & x"8b1" => DATA <= x"6172";
when "01" & x"8b2" => DATA <= x"7954";
when "01" & x"8b3" => DATA <= x"6f44";
when "01" & x"8b4" => DATA <= x"6563";
when "01" & x"8b5" => DATA <= x"696d";
when "01" & x"8b6" => DATA <= x"616c";
when "01" & x"8b7" => DATA <= x"0000";
when "01" & x"8b8" => DATA <= x"0000";
when "01" & x"8b9" => DATA <= x"0029";
when "01" & x"8ba" => DATA <= x"0000";
when "01" & x"8bb" => DATA <= x"043c";
when "01" & x"8bc" => DATA <= x"4f53";
when "01" & x"8bd" => DATA <= x"5f46";
when "01" & x"8be" => DATA <= x"5343";
when "01" & x"8bf" => DATA <= x"6f6e";
when "01" & x"8c0" => DATA <= x"7472";
when "01" & x"8c1" => DATA <= x"6f6c";
when "01" & x"8c2" => DATA <= x"0000";
when "01" & x"8c3" => DATA <= x"0000";
when "01" & x"8c4" => DATA <= x"0000";
when "01" & x"8c5" => DATA <= x"002b";
when "01" & x"8c6" => DATA <= x"003f";
when "01" & x"8c7" => DATA <= x"1124";
when "01" & x"8c8" => DATA <= x"4f53";
when "01" & x"8c9" => DATA <= x"5f47";
when "01" & x"8ca" => DATA <= x"656e";
when "01" & x"8cb" => DATA <= x"6572";
when "01" & x"8cc" => DATA <= x"6174";
when "01" & x"8cd" => DATA <= x"6545";
when "01" & x"8ce" => DATA <= x"7272";
when "01" & x"8cf" => DATA <= x"6f72";
when "01" & x"8d0" => DATA <= x"0000";
when "01" & x"8d1" => DATA <= x"0000";
when "01" & x"8d2" => DATA <= x"0000";
when "01" & x"8d3" => DATA <= x"002c";
when "01" & x"8d4" => DATA <= x"003f";
when "01" & x"8d5" => DATA <= x"112a";
when "01" & x"8d6" => DATA <= x"4f53";
when "01" & x"8d7" => DATA <= x"5f52";
when "01" & x"8d8" => DATA <= x"6561";
when "01" & x"8d9" => DATA <= x"6445";
when "01" & x"8da" => DATA <= x"7363";
when "01" & x"8db" => DATA <= x"6170";
when "01" & x"8dc" => DATA <= x"6553";
when "01" & x"8dd" => DATA <= x"7461";
when "01" & x"8de" => DATA <= x"7465";
when "01" & x"8df" => DATA <= x"0000";
when "01" & x"8e0" => DATA <= x"0000";
when "01" & x"8e1" => DATA <= x"002f";
when "01" & x"8e2" => DATA <= x"003f";
when "01" & x"8e3" => DATA <= x"1140";
when "01" & x"8e4" => DATA <= x"4f53";
when "01" & x"8e5" => DATA <= x"5f52";
when "01" & x"8e6" => DATA <= x"6561";
when "01" & x"8e7" => DATA <= x"6450";
when "01" & x"8e8" => DATA <= x"616c";
when "01" & x"8e9" => DATA <= x"6574";
when "01" & x"8ea" => DATA <= x"7465";
when "01" & x"8eb" => DATA <= x"0000";
when "01" & x"8ec" => DATA <= x"0000";
when "01" & x"8ed" => DATA <= x"0032";
when "01" & x"8ee" => DATA <= x"003f";
when "01" & x"8ef" => DATA <= x"1156";
when "01" & x"8f0" => DATA <= x"4f53";
when "01" & x"8f1" => DATA <= x"5f52";
when "01" & x"8f2" => DATA <= x"6561";
when "01" & x"8f3" => DATA <= x"6450";
when "01" & x"8f4" => DATA <= x"6f69";
when "01" & x"8f5" => DATA <= x"6e74";
when "01" & x"8f6" => DATA <= x"0000";
when "01" & x"8f7" => DATA <= x"0000";
when "01" & x"8f8" => DATA <= x"0000";
when "01" & x"8f9" => DATA <= x"0034";
when "01" & x"8fa" => DATA <= x"003f";
when "01" & x"8fb" => DATA <= x"11ac";
when "01" & x"8fc" => DATA <= x"4f53";
when "01" & x"8fd" => DATA <= x"5f43";
when "01" & x"8fe" => DATA <= x"616c";
when "01" & x"8ff" => DATA <= x"6c41";
when "01" & x"900" => DATA <= x"5665";
when "01" & x"901" => DATA <= x"6374";
when "01" & x"902" => DATA <= x"6f72";
when "01" & x"903" => DATA <= x"0000";
when "01" & x"904" => DATA <= x"0000";
when "01" & x"905" => DATA <= x"0036";
when "01" & x"906" => DATA <= x"003f";
when "01" & x"907" => DATA <= x"11d8";
when "01" & x"908" => DATA <= x"4f53";
when "01" & x"909" => DATA <= x"5f52";
when "01" & x"90a" => DATA <= x"656d";
when "01" & x"90b" => DATA <= x"6f76";
when "01" & x"90c" => DATA <= x"6543";
when "01" & x"90d" => DATA <= x"7572";
when "01" & x"90e" => DATA <= x"736f";
when "01" & x"90f" => DATA <= x"7273";
when "01" & x"910" => DATA <= x"0000";
when "01" & x"911" => DATA <= x"0000";
when "01" & x"912" => DATA <= x"0000";
when "01" & x"913" => DATA <= x"0037";
when "01" & x"914" => DATA <= x"003f";
when "01" & x"915" => DATA <= x"11f2";
when "01" & x"916" => DATA <= x"4f53";
when "01" & x"917" => DATA <= x"5f52";
when "01" & x"918" => DATA <= x"6573";
when "01" & x"919" => DATA <= x"746f";
when "01" & x"91a" => DATA <= x"7265";
when "01" & x"91b" => DATA <= x"4375";
when "01" & x"91c" => DATA <= x"7273";
when "01" & x"91d" => DATA <= x"6f72";
when "01" & x"91e" => DATA <= x"7300";
when "01" & x"91f" => DATA <= x"0000";
when "01" & x"920" => DATA <= x"0000";
when "01" & x"921" => DATA <= x"0038";
when "01" & x"922" => DATA <= x"003f";
when "01" & x"923" => DATA <= x"120c";
when "01" & x"924" => DATA <= x"4f53";
when "01" & x"925" => DATA <= x"5f53";
when "01" & x"926" => DATA <= x"5749";
when "01" & x"927" => DATA <= x"4e75";
when "01" & x"928" => DATA <= x"6d62";
when "01" & x"929" => DATA <= x"6572";
when "01" & x"92a" => DATA <= x"546f";
when "01" & x"92b" => DATA <= x"5374";
when "01" & x"92c" => DATA <= x"7269";
when "01" & x"92d" => DATA <= x"6e67";
when "01" & x"92e" => DATA <= x"0000";
when "01" & x"92f" => DATA <= x"0000";
when "01" & x"930" => DATA <= x"0000";
when "01" & x"931" => DATA <= x"0039";
when "01" & x"932" => DATA <= x"003f";
when "01" & x"933" => DATA <= x"128c";
when "01" & x"934" => DATA <= x"4f53";
when "01" & x"935" => DATA <= x"5f53";
when "01" & x"936" => DATA <= x"5749";
when "01" & x"937" => DATA <= x"4e75";
when "01" & x"938" => DATA <= x"6d62";
when "01" & x"939" => DATA <= x"6572";
when "01" & x"93a" => DATA <= x"4672";
when "01" & x"93b" => DATA <= x"6f6d";
when "01" & x"93c" => DATA <= x"5374";
when "01" & x"93d" => DATA <= x"7269";
when "01" & x"93e" => DATA <= x"6e67";
when "01" & x"93f" => DATA <= x"0000";
when "01" & x"940" => DATA <= x"0000";
when "01" & x"941" => DATA <= x"003a";
when "01" & x"942" => DATA <= x"003f";
when "01" & x"943" => DATA <= x"12d0";
when "01" & x"944" => DATA <= x"4f53";
when "01" & x"945" => DATA <= x"5f56";
when "01" & x"946" => DATA <= x"616c";
when "01" & x"947" => DATA <= x"6964";
when "01" & x"948" => DATA <= x"6174";
when "01" & x"949" => DATA <= x"6541";
when "01" & x"94a" => DATA <= x"6464";
when "01" & x"94b" => DATA <= x"7265";
when "01" & x"94c" => DATA <= x"7373";
when "01" & x"94d" => DATA <= x"0000";
when "01" & x"94e" => DATA <= x"0000";
when "01" & x"94f" => DATA <= x"003f";
when "01" & x"950" => DATA <= x"003f";
when "01" & x"951" => DATA <= x"12ea";
when "01" & x"952" => DATA <= x"4f53";
when "01" & x"953" => DATA <= x"5f43";
when "01" & x"954" => DATA <= x"6865";
when "01" & x"955" => DATA <= x"636b";
when "01" & x"956" => DATA <= x"4d6f";
when "01" & x"957" => DATA <= x"6465";
when "01" & x"958" => DATA <= x"5661";
when "01" & x"959" => DATA <= x"6c69";
when "01" & x"95a" => DATA <= x"6400";
when "01" & x"95b" => DATA <= x"0000";
when "01" & x"95c" => DATA <= x"0000";
when "01" & x"95d" => DATA <= x"0040";
when "01" & x"95e" => DATA <= x"003f";
when "01" & x"95f" => DATA <= x"1304";
when "01" & x"960" => DATA <= x"4f53";
when "01" & x"961" => DATA <= x"5f43";
when "01" & x"962" => DATA <= x"6861";
when "01" & x"963" => DATA <= x"6e67";
when "01" & x"964" => DATA <= x"6545";
when "01" & x"965" => DATA <= x"6e76";
when "01" & x"966" => DATA <= x"6972";
when "01" & x"967" => DATA <= x"6f6e";
when "01" & x"968" => DATA <= x"6d65";
when "01" & x"969" => DATA <= x"6e74";
when "01" & x"96a" => DATA <= x"0000";
when "01" & x"96b" => DATA <= x"0000";
when "01" & x"96c" => DATA <= x"0000";
when "01" & x"96d" => DATA <= x"0042";
when "01" & x"96e" => DATA <= x"003f";
when "01" & x"96f" => DATA <= x"130a";
when "01" & x"970" => DATA <= x"4f53";
when "01" & x"971" => DATA <= x"5f52";
when "01" & x"972" => DATA <= x"6561";
when "01" & x"973" => DATA <= x"644d";
when "01" & x"974" => DATA <= x"6f6e";
when "01" & x"975" => DATA <= x"6f74";
when "01" & x"976" => DATA <= x"6f6e";
when "01" & x"977" => DATA <= x"6963";
when "01" & x"978" => DATA <= x"5469";
when "01" & x"979" => DATA <= x"6d65";
when "01" & x"97a" => DATA <= x"0000";
when "01" & x"97b" => DATA <= x"0000";
when "01" & x"97c" => DATA <= x"0000";
when "01" & x"97d" => DATA <= x"0045";
when "01" & x"97e" => DATA <= x"003f";
when "01" & x"97f" => DATA <= x"1324";
when "01" & x"980" => DATA <= x"4f53";
when "01" & x"981" => DATA <= x"5f50";
when "01" & x"982" => DATA <= x"6c6f";
when "01" & x"983" => DATA <= x"7400";
when "01" & x"984" => DATA <= x"0000";
when "01" & x"985" => DATA <= x"0046";
when "01" & x"986" => DATA <= x"003f";
when "01" & x"987" => DATA <= x"1372";
when "01" & x"988" => DATA <= x"4f53";
when "01" & x"989" => DATA <= x"5f57";
when "01" & x"98a" => DATA <= x"7269";
when "01" & x"98b" => DATA <= x"7465";
when "01" & x"98c" => DATA <= x"4e00";
when "01" & x"98d" => DATA <= x"0000";
when "01" & x"98e" => DATA <= x"0000";
when "01" & x"98f" => DATA <= x"0048";
when "01" & x"990" => DATA <= x"003f";
when "01" & x"991" => DATA <= x"1398";
when "01" & x"992" => DATA <= x"4f53";
when "01" & x"993" => DATA <= x"5f57";
when "01" & x"994" => DATA <= x"7269";
when "01" & x"995" => DATA <= x"7465";
when "01" & x"996" => DATA <= x"456e";
when "01" & x"997" => DATA <= x"7600";
when "01" & x"998" => DATA <= x"0000";
when "01" & x"999" => DATA <= x"0050";
when "01" & x"99a" => DATA <= x"003f";
when "01" & x"99b" => DATA <= x"13ce";
when "01" & x"99c" => DATA <= x"4f53";
when "01" & x"99d" => DATA <= x"5f45";
when "01" & x"99e" => DATA <= x"7869";
when "01" & x"99f" => DATA <= x"7441";
when "01" & x"9a0" => DATA <= x"6e64";
when "01" & x"9a1" => DATA <= x"4469";
when "01" & x"9a2" => DATA <= x"6500";
when "01" & x"9a3" => DATA <= x"0000";
when "01" & x"9a4" => DATA <= x"0000";
when "01" & x"9a5" => DATA <= x"0055";
when "01" & x"9a6" => DATA <= x"003f";
when "01" & x"9a7" => DATA <= x"13e6";
when "01" & x"9a8" => DATA <= x"4f53";
when "01" & x"9a9" => DATA <= x"5f52";
when "01" & x"9aa" => DATA <= x"6561";
when "01" & x"9ab" => DATA <= x"6444";
when "01" & x"9ac" => DATA <= x"6566";
when "01" & x"9ad" => DATA <= x"6175";
when "01" & x"9ae" => DATA <= x"6c74";
when "01" & x"9af" => DATA <= x"4861";
when "01" & x"9b0" => DATA <= x"6e64";
when "01" & x"9b1" => DATA <= x"6c65";
when "01" & x"9b2" => DATA <= x"7200";
when "01" & x"9b3" => DATA <= x"0000";
when "01" & x"9b4" => DATA <= x"0000";
when "01" & x"9b5" => DATA <= x"0056";
when "01" & x"9b6" => DATA <= x"003f";
when "01" & x"9b7" => DATA <= x"142e";
when "01" & x"9b8" => DATA <= x"4f53";
when "01" & x"9b9" => DATA <= x"5f53";
when "01" & x"9ba" => DATA <= x"6574";
when "01" & x"9bb" => DATA <= x"4543";
when "01" & x"9bc" => DATA <= x"464f";
when "01" & x"9bd" => DATA <= x"7269";
when "01" & x"9be" => DATA <= x"6769";
when "01" & x"9bf" => DATA <= x"6e00";
when "01" & x"9c0" => DATA <= x"0000";
when "01" & x"9c1" => DATA <= x"005d";
when "01" & x"9c2" => DATA <= x"003f";
when "01" & x"9c3" => DATA <= x"14de";
when "01" & x"9c4" => DATA <= x"4f53";
when "01" & x"9c5" => DATA <= x"5f50";
when "01" & x"9c6" => DATA <= x"7269";
when "01" & x"9c7" => DATA <= x"6e74";
when "01" & x"9c8" => DATA <= x"4368";
when "01" & x"9c9" => DATA <= x"6172";
when "01" & x"9ca" => DATA <= x"0000";
when "01" & x"9cb" => DATA <= x"0000";
when "01" & x"9cc" => DATA <= x"0000";
when "01" & x"9cd" => DATA <= x"005b";
when "01" & x"9ce" => DATA <= x"003f";
when "01" & x"9cf" => DATA <= x"14ac";
when "01" & x"9d0" => DATA <= x"4f53";
when "01" & x"9d1" => DATA <= x"5f43";
when "01" & x"9d2" => DATA <= x"5243";
when "01" & x"9d3" => DATA <= x"0000";
when "01" & x"9d4" => DATA <= x"0000";
when "01" & x"9d5" => DATA <= x"0059";
when "01" & x"9d6" => DATA <= x"003f";
when "01" & x"9d7" => DATA <= x"149e";
when "01" & x"9d8" => DATA <= x"4f53";
when "01" & x"9d9" => DATA <= x"5f43";
when "01" & x"9da" => DATA <= x"6f6e";
when "01" & x"9db" => DATA <= x"6669";
when "01" & x"9dc" => DATA <= x"726d";
when "01" & x"9dd" => DATA <= x"0000";
when "01" & x"9de" => DATA <= x"0000";
when "01" & x"9df" => DATA <= x"007c";
when "01" & x"9e0" => DATA <= x"003f";
when "01" & x"9e1" => DATA <= x"14ea";
when "01" & x"9e2" => DATA <= x"4f53";
when "01" & x"9e3" => DATA <= x"5f4c";
when "01" & x"9e4" => DATA <= x"6561";
when "01" & x"9e5" => DATA <= x"7665";
when "01" & x"9e6" => DATA <= x"4f53";
when "01" & x"9e7" => DATA <= x"0000";
when "01" & x"9e8" => DATA <= x"0000";
when "01" & x"9e9" => DATA <= x"007d";
when "01" & x"9ea" => DATA <= x"003f";
when "01" & x"9eb" => DATA <= x"14f0";
when "01" & x"9ec" => DATA <= x"4f53";
when "01" & x"9ed" => DATA <= x"5f52";
when "01" & x"9ee" => DATA <= x"6561";
when "01" & x"9ef" => DATA <= x"644c";
when "01" & x"9f0" => DATA <= x"696e";
when "01" & x"9f1" => DATA <= x"6533";
when "01" & x"9f2" => DATA <= x"3200";
when "01" & x"9f3" => DATA <= x"0000";
when "01" & x"9f4" => DATA <= x"0000";
when "01" & x"9f5" => DATA <= x"00d0";
when "01" & x"9f6" => DATA <= x"003f";
when "01" & x"9f7" => DATA <= x"1678";
when "01" & x"9f8" => DATA <= x"4f53";
when "01" & x"9f9" => DATA <= x"5f43";
when "01" & x"9fa" => DATA <= x"6f6e";
when "01" & x"9fb" => DATA <= x"7665";
when "01" & x"9fc" => DATA <= x"7274";
when "01" & x"9fd" => DATA <= x"4865";
when "01" & x"9fe" => DATA <= x"7831";
when "01" & x"9ff" => DATA <= x"0000";
when "01" & x"a00" => DATA <= x"0000";
when "01" & x"a01" => DATA <= x"00d1";
when "01" & x"a02" => DATA <= x"003f";
when "01" & x"a03" => DATA <= x"1694";
when "01" & x"a04" => DATA <= x"4f53";
when "01" & x"a05" => DATA <= x"5f43";
when "01" & x"a06" => DATA <= x"6f6e";
when "01" & x"a07" => DATA <= x"7665";
when "01" & x"a08" => DATA <= x"7274";
when "01" & x"a09" => DATA <= x"4865";
when "01" & x"a0a" => DATA <= x"7832";
when "01" & x"a0b" => DATA <= x"0000";
when "01" & x"a0c" => DATA <= x"0000";
when "01" & x"a0d" => DATA <= x"00d2";
when "01" & x"a0e" => DATA <= x"003f";
when "01" & x"a0f" => DATA <= x"16b0";
when "01" & x"a10" => DATA <= x"4f53";
when "01" & x"a11" => DATA <= x"5f43";
when "01" & x"a12" => DATA <= x"6f6e";
when "01" & x"a13" => DATA <= x"7665";
when "01" & x"a14" => DATA <= x"7274";
when "01" & x"a15" => DATA <= x"4865";
when "01" & x"a16" => DATA <= x"7834";
when "01" & x"a17" => DATA <= x"0000";
when "01" & x"a18" => DATA <= x"0000";
when "01" & x"a19" => DATA <= x"00d3";
when "01" & x"a1a" => DATA <= x"003f";
when "01" & x"a1b" => DATA <= x"16ce";
when "01" & x"a1c" => DATA <= x"4f53";
when "01" & x"a1d" => DATA <= x"5f43";
when "01" & x"a1e" => DATA <= x"6f6e";
when "01" & x"a1f" => DATA <= x"7665";
when "01" & x"a20" => DATA <= x"7274";
when "01" & x"a21" => DATA <= x"4865";
when "01" & x"a22" => DATA <= x"7836";
when "01" & x"a23" => DATA <= x"0000";
when "01" & x"a24" => DATA <= x"0000";
when "01" & x"a25" => DATA <= x"00d4";
when "01" & x"a26" => DATA <= x"003f";
when "01" & x"a27" => DATA <= x"16ea";
when "01" & x"a28" => DATA <= x"4f53";
when "01" & x"a29" => DATA <= x"5f43";
when "01" & x"a2a" => DATA <= x"6f6e";
when "01" & x"a2b" => DATA <= x"7665";
when "01" & x"a2c" => DATA <= x"7274";
when "01" & x"a2d" => DATA <= x"4865";
when "01" & x"a2e" => DATA <= x"7838";
when "01" & x"a2f" => DATA <= x"0000";
when "01" & x"a30" => DATA <= x"0000";
when "01" & x"a31" => DATA <= x"00d5";
when "01" & x"a32" => DATA <= x"003f";
when "01" & x"a33" => DATA <= x"1744";
when "01" & x"a34" => DATA <= x"4f53";
when "01" & x"a35" => DATA <= x"5f43";
when "01" & x"a36" => DATA <= x"6f6e";
when "01" & x"a37" => DATA <= x"7665";
when "01" & x"a38" => DATA <= x"7274";
when "01" & x"a39" => DATA <= x"4361";
when "01" & x"a3a" => DATA <= x"7264";
when "01" & x"a3b" => DATA <= x"696e";
when "01" & x"a3c" => DATA <= x"616c";
when "01" & x"a3d" => DATA <= x"3100";
when "01" & x"a3e" => DATA <= x"0000";
when "01" & x"a3f" => DATA <= x"00d6";
when "01" & x"a40" => DATA <= x"003f";
when "01" & x"a41" => DATA <= x"175e";
when "01" & x"a42" => DATA <= x"4f53";
when "01" & x"a43" => DATA <= x"5f43";
when "01" & x"a44" => DATA <= x"6f6e";
when "01" & x"a45" => DATA <= x"7665";
when "01" & x"a46" => DATA <= x"7274";
when "01" & x"a47" => DATA <= x"4361";
when "01" & x"a48" => DATA <= x"7264";
when "01" & x"a49" => DATA <= x"696e";
when "01" & x"a4a" => DATA <= x"616c";
when "01" & x"a4b" => DATA <= x"3200";
when "01" & x"a4c" => DATA <= x"0000";
when "01" & x"a4d" => DATA <= x"00d7";
when "01" & x"a4e" => DATA <= x"003f";
when "01" & x"a4f" => DATA <= x"1778";
when "01" & x"a50" => DATA <= x"4f53";
when "01" & x"a51" => DATA <= x"5f43";
when "01" & x"a52" => DATA <= x"6f6e";
when "01" & x"a53" => DATA <= x"7665";
when "01" & x"a54" => DATA <= x"7274";
when "01" & x"a55" => DATA <= x"4361";
when "01" & x"a56" => DATA <= x"7264";
when "01" & x"a57" => DATA <= x"696e";
when "01" & x"a58" => DATA <= x"616c";
when "01" & x"a59" => DATA <= x"3300";
when "01" & x"a5a" => DATA <= x"0000";
when "01" & x"a5b" => DATA <= x"00d8";
when "01" & x"a5c" => DATA <= x"003f";
when "01" & x"a5d" => DATA <= x"1792";
when "01" & x"a5e" => DATA <= x"4f53";
when "01" & x"a5f" => DATA <= x"5f43";
when "01" & x"a60" => DATA <= x"6f6e";
when "01" & x"a61" => DATA <= x"7665";
when "01" & x"a62" => DATA <= x"7274";
when "01" & x"a63" => DATA <= x"4361";
when "01" & x"a64" => DATA <= x"7264";
when "01" & x"a65" => DATA <= x"696e";
when "01" & x"a66" => DATA <= x"616c";
when "01" & x"a67" => DATA <= x"3400";
when "01" & x"a68" => DATA <= x"0000";
when "01" & x"a69" => DATA <= x"00d9";
when "01" & x"a6a" => DATA <= x"003f";
when "01" & x"a6b" => DATA <= x"1814";
when "01" & x"a6c" => DATA <= x"4f53";
when "01" & x"a6d" => DATA <= x"5f43";
when "01" & x"a6e" => DATA <= x"6f6e";
when "01" & x"a6f" => DATA <= x"7665";
when "01" & x"a70" => DATA <= x"7274";
when "01" & x"a71" => DATA <= x"496e";
when "01" & x"a72" => DATA <= x"7465";
when "01" & x"a73" => DATA <= x"6765";
when "01" & x"a74" => DATA <= x"7231";
when "01" & x"a75" => DATA <= x"0000";
when "01" & x"a76" => DATA <= x"0000";
when "01" & x"a77" => DATA <= x"00da";
when "01" & x"a78" => DATA <= x"003f";
when "01" & x"a79" => DATA <= x"183c";
when "01" & x"a7a" => DATA <= x"4f53";
when "01" & x"a7b" => DATA <= x"5f43";
when "01" & x"a7c" => DATA <= x"6f6e";
when "01" & x"a7d" => DATA <= x"7665";
when "01" & x"a7e" => DATA <= x"7274";
when "01" & x"a7f" => DATA <= x"496e";
when "01" & x"a80" => DATA <= x"7465";
when "01" & x"a81" => DATA <= x"6765";
when "01" & x"a82" => DATA <= x"7232";
when "01" & x"a83" => DATA <= x"0000";
when "01" & x"a84" => DATA <= x"0000";
when "01" & x"a85" => DATA <= x"00db";
when "01" & x"a86" => DATA <= x"003f";
when "01" & x"a87" => DATA <= x"1864";
when "01" & x"a88" => DATA <= x"4f53";
when "01" & x"a89" => DATA <= x"5f43";
when "01" & x"a8a" => DATA <= x"6f6e";
when "01" & x"a8b" => DATA <= x"7665";
when "01" & x"a8c" => DATA <= x"7274";
when "01" & x"a8d" => DATA <= x"496e";
when "01" & x"a8e" => DATA <= x"7465";
when "01" & x"a8f" => DATA <= x"6765";
when "01" & x"a90" => DATA <= x"7233";
when "01" & x"a91" => DATA <= x"0000";
when "01" & x"a92" => DATA <= x"0000";
when "01" & x"a93" => DATA <= x"00dc";
when "01" & x"a94" => DATA <= x"003f";
when "01" & x"a95" => DATA <= x"188c";
when "01" & x"a96" => DATA <= x"4f53";
when "01" & x"a97" => DATA <= x"5f43";
when "01" & x"a98" => DATA <= x"6f6e";
when "01" & x"a99" => DATA <= x"7665";
when "01" & x"a9a" => DATA <= x"7274";
when "01" & x"a9b" => DATA <= x"496e";
when "01" & x"a9c" => DATA <= x"7465";
when "01" & x"a9d" => DATA <= x"6765";
when "01" & x"a9e" => DATA <= x"7234";
when "01" & x"a9f" => DATA <= x"0000";
when "01" & x"aa0" => DATA <= x"0000";
when "01" & x"aa1" => DATA <= x"00dd";
when "01" & x"aa2" => DATA <= x"003f";
when "01" & x"aa3" => DATA <= x"190e";
when "01" & x"aa4" => DATA <= x"4f53";
when "01" & x"aa5" => DATA <= x"5f43";
when "01" & x"aa6" => DATA <= x"6f6e";
when "01" & x"aa7" => DATA <= x"7665";
when "01" & x"aa8" => DATA <= x"7274";
when "01" & x"aa9" => DATA <= x"4269";
when "01" & x"aaa" => DATA <= x"6e61";
when "01" & x"aab" => DATA <= x"7279";
when "01" & x"aac" => DATA <= x"3100";
when "01" & x"aad" => DATA <= x"0000";
when "01" & x"aae" => DATA <= x"0000";
when "01" & x"aaf" => DATA <= x"00de";
when "01" & x"ab0" => DATA <= x"003f";
when "01" & x"ab1" => DATA <= x"192c";
when "01" & x"ab2" => DATA <= x"4f53";
when "01" & x"ab3" => DATA <= x"5f43";
when "01" & x"ab4" => DATA <= x"6f6e";
when "01" & x"ab5" => DATA <= x"7665";
when "01" & x"ab6" => DATA <= x"7274";
when "01" & x"ab7" => DATA <= x"4269";
when "01" & x"ab8" => DATA <= x"6e61";
when "01" & x"ab9" => DATA <= x"7279";
when "01" & x"aba" => DATA <= x"3200";
when "01" & x"abb" => DATA <= x"0000";
when "01" & x"abc" => DATA <= x"0000";
when "01" & x"abd" => DATA <= x"00df";
when "01" & x"abe" => DATA <= x"003f";
when "01" & x"abf" => DATA <= x"194c";
when "01" & x"ac0" => DATA <= x"4f53";
when "01" & x"ac1" => DATA <= x"5f43";
when "01" & x"ac2" => DATA <= x"6f6e";
when "01" & x"ac3" => DATA <= x"7665";
when "01" & x"ac4" => DATA <= x"7274";
when "01" & x"ac5" => DATA <= x"4269";
when "01" & x"ac6" => DATA <= x"6e61";
when "01" & x"ac7" => DATA <= x"7279";
when "01" & x"ac8" => DATA <= x"3300";
when "01" & x"ac9" => DATA <= x"0000";
when "01" & x"aca" => DATA <= x"0000";
when "01" & x"acb" => DATA <= x"00e0";
when "01" & x"acc" => DATA <= x"003f";
when "01" & x"acd" => DATA <= x"196a";
when "01" & x"ace" => DATA <= x"4f53";
when "01" & x"acf" => DATA <= x"5f43";
when "01" & x"ad0" => DATA <= x"6f6e";
when "01" & x"ad1" => DATA <= x"7665";
when "01" & x"ad2" => DATA <= x"7274";
when "01" & x"ad3" => DATA <= x"4269";
when "01" & x"ad4" => DATA <= x"6e61";
when "01" & x"ad5" => DATA <= x"7279";
when "01" & x"ad6" => DATA <= x"3400";
when "01" & x"ad7" => DATA <= x"0000";
when "01" & x"ad8" => DATA <= x"0000";
when "01" & x"ad9" => DATA <= x"00ea";
when "01" & x"ada" => DATA <= x"003f";
when "01" & x"adb" => DATA <= x"19e6";
when "01" & x"adc" => DATA <= x"4f53";
when "01" & x"add" => DATA <= x"5f43";
when "01" & x"ade" => DATA <= x"6f6e";
when "01" & x"adf" => DATA <= x"7665";
when "01" & x"ae0" => DATA <= x"7274";
when "01" & x"ae1" => DATA <= x"4e65";
when "01" & x"ae2" => DATA <= x"7453";
when "01" & x"ae3" => DATA <= x"7461";
when "01" & x"ae4" => DATA <= x"7469";
when "01" & x"ae5" => DATA <= x"6f6e";
when "01" & x"ae6" => DATA <= x"0000";
when "01" & x"ae7" => DATA <= x"00ff";
when "01" & x"ae8" => DATA <= x"003f";
when "01" & x"ae9" => DATA <= x"1b56";
when "01" & x"aea" => DATA <= x"4552";
when "01" & x"aeb" => DATA <= x"524f";
when "01" & x"aec" => DATA <= x"5220";
when "01" & x"aed" => DATA <= x"2000";
when "01" & x"aee" => DATA <= x"003f";
when "01" & x"aef" => DATA <= x"1bb4";
when "01" & x"af0" => DATA <= x"464c";
when "01" & x"af1" => DATA <= x"4153";
when "01" & x"af2" => DATA <= x"4820";
when "01" & x"af3" => DATA <= x"2000";
when "01" & x"af4" => DATA <= x"003f";
when "01" & x"af5" => DATA <= x"1c8c";
when "01" & x"af6" => DATA <= x"474f";
when "01" & x"af7" => DATA <= x"2000";
when "01" & x"af8" => DATA <= x"003f";
when "01" & x"af9" => DATA <= x"1cba";
when "01" & x"afa" => DATA <= x"4845";
when "01" & x"afb" => DATA <= x"4c50";
when "01" & x"afc" => DATA <= x"2020";
when "01" & x"afd" => DATA <= x"2000";
when "01" & x"afe" => DATA <= x"003f";
when "01" & x"aff" => DATA <= x"1db6";
when "01" & x"b00" => DATA <= x"4d4f";
when "01" & x"b01" => DATA <= x"4e00";
when "01" & x"b02" => DATA <= x"003f";
when "01" & x"b03" => DATA <= x"2480";
when "01" & x"b04" => DATA <= x"5155";
when "01" & x"b05" => DATA <= x"4954";
when "01" & x"b06" => DATA <= x"2020";
when "01" & x"b07" => DATA <= x"2000";
when "01" & x"b08" => DATA <= x"003f";
when "01" & x"b09" => DATA <= x"2484";
when "01" & x"b0a" => DATA <= x"545a";
when "01" & x"b0b" => DATA <= x"4150";
when "01" & x"b0c" => DATA <= x"2020";
when "01" & x"b0d" => DATA <= x"2000";
when "01" & x"b0e" => DATA <= x"003f";
when "01" & x"b0f" => DATA <= x"2488";
when "01" & x"b10" => DATA <= x"5846";
when "01" & x"b11" => DATA <= x"4552";
when "01" & x"b12" => DATA <= x"2020";
when "01" & x"b13" => DATA <= x"2000";
when "01" & x"b14" => DATA <= x"ffff";
when "01" & x"b15" => DATA <= x"ffff";
when "01" & x"b16" => DATA <= x"0000";
when "01" & x"b17" => DATA <= x"0000";
when "01" & x"b18" => DATA <= x"0000";
when "01" & x"b19" => DATA <= x"0508";
when "01" & x"b1a" => DATA <= x"0000";
when "01" & x"b1b" => DATA <= x"0000";
when "01" & x"b1c" => DATA <= x"0000";
when "01" & x"b1d" => DATA <= x"0000";
when "01" & x"b1e" => DATA <= x"0000";
when "01" & x"b1f" => DATA <= x"0010";
when "01" & x"b20" => DATA <= x"0000";
when "01" & x"b21" => DATA <= x"0000";
when "01" & x"b22" => DATA <= x"0000";
when "01" & x"b23" => DATA <= x"0000";
when "01" & x"b24" => DATA <= x"0000";
when "01" & x"b25" => DATA <= x"0000";
when "01" & x"b26" => DATA <= x"0000";
when "01" & x"b27" => DATA <= x"0000";
when "01" & x"b28" => DATA <= x"0000";
when "01" & x"b29" => DATA <= x"0000";
when "01" & x"b2a" => DATA <= x"0000";
when "01" & x"b2b" => DATA <= x"0000";
when "01" & x"b2c" => DATA <= x"0000";
when "01" & x"b2d" => DATA <= x"0000";
when "01" & x"b2e" => DATA <= x"0000";
when "01" & x"b2f" => DATA <= x"0000";
when "01" & x"b30" => DATA <= x"0000";
when "01" & x"b31" => DATA <= x"000c";
when "01" & x"b32" => DATA <= x"0000";
when "01" & x"b33" => DATA <= x"0000";
when "01" & x"b34" => DATA <= x"0000";
when "01" & x"b35" => DATA <= x"0000";
when "01" & x"b36" => DATA <= x"0000";
when "01" & x"b37" => DATA <= x"04c0";
when "01" & x"b38" => DATA <= x"0000";
when "01" & x"b39" => DATA <= x"0000";
when "01" & x"b3a" => DATA <= x"0000";
when "01" & x"b3b" => DATA <= x"0000";
when "01" & x"b3c" => DATA <= x"0000";
when "01" & x"b3d" => DATA <= x"0404";
when "01" & x"b3e" => DATA <= x"0000";
when "01" & x"b3f" => DATA <= x"04d4";
when "01" & x"b40" => DATA <= x"0000";
when "01" & x"b41" => DATA <= x"04f4";
when "01" & x"b42" => DATA <= x"0000";
when "01" & x"b43" => DATA <= x"04c4";
when "01" & x"b44" => DATA <= x"0000";
when "01" & x"b45" => DATA <= x"04d8";
when "01" & x"b46" => DATA <= x"0000";
when "01" & x"b47" => DATA <= x"04f8";
when "01" & x"b48" => DATA <= x"0000";
when "01" & x"b49" => DATA <= x"04c8";
when "01" & x"b4a" => DATA <= x"0000";
when "01" & x"b4b" => DATA <= x"04dc";
when "01" & x"b4c" => DATA <= x"0000";
when "01" & x"b4d" => DATA <= x"04fc";
when "01" & x"b4e" => DATA <= x"0000";
when "01" & x"b4f" => DATA <= x"04cc";
when "01" & x"b50" => DATA <= x"0000";
when "01" & x"b51" => DATA <= x"04e0";
when "01" & x"b52" => DATA <= x"0000";
when "01" & x"b53" => DATA <= x"0000";
when "01" & x"b54" => DATA <= x"0000";
when "01" & x"b55" => DATA <= x"0440";
when "01" & x"b56" => DATA <= x"0000";
when "01" & x"b57" => DATA <= x"04e4";
when "01" & x"b58" => DATA <= x"0000";
when "01" & x"b59" => DATA <= x"0000";
when "01" & x"b5a" => DATA <= x"0000";
when "01" & x"b5b" => DATA <= x"04d0";
when "01" & x"b5c" => DATA <= x"0000";
when "01" & x"b5d" => DATA <= x"04e8";
when "01" & x"b5e" => DATA <= x"0000";
when "01" & x"b5f" => DATA <= x"0000";
when "01" & x"b60" => DATA <= x"0000";
when "01" & x"b61" => DATA <= x"0460";
when "01" & x"b62" => DATA <= x"0000";
when "01" & x"b63" => DATA <= x"04ec";
when "01" & x"b64" => DATA <= x"0000";
when "01" & x"b65" => DATA <= x"0000";
when "01" & x"b66" => DATA <= x"0000";
when "01" & x"b67" => DATA <= x"0538";
when "01" & x"b68" => DATA <= x"0000";
when "01" & x"b69" => DATA <= x"0000";
when "01" & x"b6a" => DATA <= x"0000";
when "01" & x"b6b" => DATA <= x"0000";
when "01" & x"b6c" => DATA <= x"0000";
when "01" & x"b6d" => DATA <= x"050c";
when "01" & x"b6e" => DATA <= x"0000";
when "01" & x"b6f" => DATA <= x"0000";
when "01" & x"b70" => DATA <= x"0000";
when "01" & x"b71" => DATA <= x"0000";
when "01" & x"b72" => DATA <= x"0000";
when "01" & x"b73" => DATA <= x"0000";
when "01" & x"b74" => DATA <= x"0000";
when "01" & x"b75" => DATA <= x"0000";
when "01" & x"b76" => DATA <= x"0000";
when "01" & x"b77" => DATA <= x"0000";
when "01" & x"b78" => DATA <= x"0000";
when "01" & x"b79" => DATA <= x"0474";
when "01" & x"b7a" => DATA <= x"0000";
when "01" & x"b7b" => DATA <= x"04f0";
when "01" & x"b7c" => DATA <= x"0000";
when "01" & x"b7d" => DATA <= x"0000";
when "01" & x"b7e" => DATA <= x"003f";
when "01" & x"b7f" => DATA <= x"077a";
when "01" & x"b80" => DATA <= x"003f";
when "01" & x"b81" => DATA <= x"077a";
when "01" & x"b82" => DATA <= x"003f";
when "01" & x"b83" => DATA <= x"077a";
when "01" & x"b84" => DATA <= x"003f";
when "01" & x"b85" => DATA <= x"077a";
when "01" & x"b86" => DATA <= x"003f";
when "01" & x"b87" => DATA <= x"077a";
when "01" & x"b88" => DATA <= x"003f";
when "01" & x"b89" => DATA <= x"077a";
when "01" & x"b8a" => DATA <= x"003f";
when "01" & x"b8b" => DATA <= x"077a";
when "01" & x"b8c" => DATA <= x"003f";
when "01" & x"b8d" => DATA <= x"077a";
when "01" & x"b8e" => DATA <= x"003f";
when "01" & x"b8f" => DATA <= x"077a";
when "01" & x"b90" => DATA <= x"003f";
when "01" & x"b91" => DATA <= x"077a";
when "01" & x"b92" => DATA <= x"003f";
when "01" & x"b93" => DATA <= x"1108";
when "01" & x"b94" => DATA <= x"003f";
when "01" & x"b95" => DATA <= x"077a";
when "01" & x"b96" => DATA <= x"003f";
when "01" & x"b97" => DATA <= x"077a";
when "01" & x"b98" => DATA <= x"003f";
when "01" & x"b99" => DATA <= x"077a";
when "01" & x"b9a" => DATA <= x"003f";
when "01" & x"b9b" => DATA <= x"077a";
when "01" & x"b9c" => DATA <= x"003f";
when "01" & x"b9d" => DATA <= x"077a";
when "01" & x"b9e" => DATA <= x"003f";
when "01" & x"b9f" => DATA <= x"077a";
when "01" & x"ba0" => DATA <= x"003f";
when "01" & x"ba1" => DATA <= x"077a";
when "01" & x"ba2" => DATA <= x"003f";
when "01" & x"ba3" => DATA <= x"077a";
when "01" & x"ba4" => DATA <= x"003f";
when "01" & x"ba5" => DATA <= x"077a";
when "01" & x"ba6" => DATA <= x"003f";
when "01" & x"ba7" => DATA <= x"077a";
when "01" & x"ba8" => DATA <= x"003f";
when "01" & x"ba9" => DATA <= x"077a";
when "01" & x"baa" => DATA <= x"003f";
when "01" & x"bab" => DATA <= x"1116";
when "01" & x"bac" => DATA <= x"003f";
when "01" & x"bad" => DATA <= x"077a";
when "01" & x"bae" => DATA <= x"003f";
when "01" & x"baf" => DATA <= x"077a";
when "01" & x"bb0" => DATA <= x"003f";
when "01" & x"bb1" => DATA <= x"077a";
when "01" & x"bb2" => DATA <= x"003f";
when "01" & x"bb3" => DATA <= x"077a";
when "01" & x"bb4" => DATA <= x"003f";
when "01" & x"bb5" => DATA <= x"077a";
when "01" & x"bb6" => DATA <= x"003f";
when "01" & x"bb7" => DATA <= x"077a";
when "01" & x"bb8" => DATA <= x"003f";
when "01" & x"bb9" => DATA <= x"077a";
when "01" & x"bba" => DATA <= x"003f";
when "01" & x"bbb" => DATA <= x"077a";
when "01" & x"bbc" => DATA <= x"003f";
when "01" & x"bbd" => DATA <= x"077a";
when "01" & x"bbe" => DATA <= x"003f";
when "01" & x"bbf" => DATA <= x"077a";
when "01" & x"bc0" => DATA <= x"003f";
when "01" & x"bc1" => DATA <= x"077a";
when "01" & x"bc2" => DATA <= x"003f";
when "01" & x"bc3" => DATA <= x"077a";
when "01" & x"bc4" => DATA <= x"003f";
when "01" & x"bc5" => DATA <= x"077a";
when "01" & x"bc6" => DATA <= x"003f";
when "01" & x"bc7" => DATA <= x"077a";
when "01" & x"bc8" => DATA <= x"003f";
when "01" & x"bc9" => DATA <= x"077a";
when "01" & x"bca" => DATA <= x"003f";
when "01" & x"bcb" => DATA <= x"077a";
when "01" & x"bcc" => DATA <= x"003f";
when "01" & x"bcd" => DATA <= x"077a";
when "01" & x"bce" => DATA <= x"003f";
when "01" & x"bcf" => DATA <= x"077a";
when "01" & x"bd0" => DATA <= x"003f";
when "01" & x"bd1" => DATA <= x"077a";
when "01" & x"bd2" => DATA <= x"003f";
when "01" & x"bd3" => DATA <= x"077a";
when "01" & x"bd4" => DATA <= x"003f";
when "01" & x"bd5" => DATA <= x"077a";
when "01" & x"bd6" => DATA <= x"003f";
when "01" & x"bd7" => DATA <= x"077a";
when "01" & x"bd8" => DATA <= x"003f";
when "01" & x"bd9" => DATA <= x"077a";
when "01" & x"bda" => DATA <= x"003f";
when "01" & x"bdb" => DATA <= x"077a";
when "01" & x"bdc" => DATA <= x"003f";
when "01" & x"bdd" => DATA <= x"077a";
when "01" & x"bde" => DATA <= x"003f";
when "01" & x"bdf" => DATA <= x"077a";
when "01" & x"be0" => DATA <= x"003f";
when "01" & x"be1" => DATA <= x"077a";
when "01" & x"be2" => DATA <= x"003f";
when "01" & x"be3" => DATA <= x"077a";
when "01" & x"be4" => DATA <= x"003f";
when "01" & x"be5" => DATA <= x"077a";
when "01" & x"be6" => DATA <= x"003f";
when "01" & x"be7" => DATA <= x"077a";
when "01" & x"be8" => DATA <= x"003f";
when "01" & x"be9" => DATA <= x"077a";
when "01" & x"bea" => DATA <= x"003f";
when "01" & x"beb" => DATA <= x"077a";
when "01" & x"bec" => DATA <= x"003f";
when "01" & x"bed" => DATA <= x"077a";
when "01" & x"bee" => DATA <= x"003f";
when "01" & x"bef" => DATA <= x"077a";
when "01" & x"bf0" => DATA <= x"003f";
when "01" & x"bf1" => DATA <= x"077a";
when "01" & x"bf2" => DATA <= x"003f";
when "01" & x"bf3" => DATA <= x"077a";
when "01" & x"bf4" => DATA <= x"1890";
when "01" & x"bf5" => DATA <= x"0210";
when "01" & x"bf6" => DATA <= x"e3c9";
when "01" & x"bf7" => DATA <= x"faf0";
when "01" & x"bf8" => DATA <= x"036c";
when "01" & x"bf9" => DATA <= x"0325";
when "01" & x"bfa" => DATA <= x"8670";
when "01" & x"bfb" => DATA <= x"8471";
when "01" & x"bfc" => DATA <= x"48a9";
when "01" & x"bfd" => DATA <= x"fba2";
when "01" & x"bfe" => DATA <= x"00a0";
when "01" & x"bff" => DATA <= x"ff20";
when "01" & x"c00" => DATA <= x"f4ff";
when "01" & x"c01" => DATA <= x"8673";
when "01" & x"c02" => DATA <= x"ad34";
when "01" & x"c03" => DATA <= x"fe48";
when "01" & x"c04" => DATA <= x"a9c7";
when "01" & x"c05" => DATA <= x"2006";
when "01" & x"c06" => DATA <= x"0490";
when "01" & x"c07" => DATA <= x"f9a0";
when "01" & x"c08" => DATA <= x"00b1";
when "01" & x"c09" => DATA <= x"70c9";
when "01" & x"c0a" => DATA <= x"0d08";
when "01" & x"c0b" => DATA <= x"a5f4";
when "01" & x"c0c" => DATA <= x"8572";
when "01" & x"c0d" => DATA <= x"a00d";
when "01" & x"c0e" => DATA <= x"b170";
when "01" & x"c0f" => DATA <= x"aaa0";
when "01" & x"c10" => DATA <= x"02b1";
when "01" & x"c11" => DATA <= x"7085";
when "01" & x"c12" => DATA <= x"74c8";
when "01" & x"c13" => DATA <= x"b170";
when "01" & x"c14" => DATA <= x"8575";
when "01" & x"c15" => DATA <= x"28f0";
when "01" & x"c16" => DATA <= x"408a";
when "01" & x"c17" => DATA <= x"4829";
when "01" & x"c18" => DATA <= x"40d0";
when "01" & x"c19" => DATA <= x"138a";
when "01" & x"c1a" => DATA <= x"2920";
when "01" & x"c1b" => DATA <= x"d004";
when "01" & x"c1c" => DATA <= x"a200";
when "01" & x"c1d" => DATA <= x"f002";
when "01" & x"c1e" => DATA <= x"a201";
when "01" & x"c1f" => DATA <= x"a96c";
when "01" & x"c20" => DATA <= x"20f4";
when "01" & x"c21" => DATA <= x"ff4c";
when "01" & x"c22" => DATA <= x"7725";
when "01" & x"c23" => DATA <= x"a984";
when "01" & x"c24" => DATA <= x"20f4";
when "01" & x"c25" => DATA <= x"ffc0";
when "01" & x"c26" => DATA <= x"80d0";
when "01" & x"c27" => DATA <= x"08a9";
when "01" & x"c28" => DATA <= x"01c5";
when "01" & x"c29" => DATA <= x"73d0";
when "01" & x"c2a" => DATA <= x"e7f0";
when "01" & x"c2b" => DATA <= x"e1a9";
when "01" & x"c2c" => DATA <= x"02c5";
when "01" & x"c2d" => DATA <= x"73d0";
when "01" & x"c2e" => DATA <= x"dbf0";
when "01" & x"c2f" => DATA <= x"dd68";
when "01" & x"c30" => DATA <= x"aa29";
when "01" & x"c31" => DATA <= x"10d0";
when "01" & x"c32" => DATA <= x"088a";
when "01" & x"c33" => DATA <= x"290f";
when "01" & x"c34" => DATA <= x"85f4";
when "01" & x"c35" => DATA <= x"8d30";
when "01" & x"c36" => DATA <= x"fea0";
when "01" & x"c37" => DATA <= x"0ab1";
when "01" & x"c38" => DATA <= x"7085";
when "01" & x"c39" => DATA <= x"77c8";
when "01" & x"c3a" => DATA <= x"b170";
when "01" & x"c3b" => DATA <= x"8576";
when "01" & x"c3c" => DATA <= x"0577";
when "01" & x"c3d" => DATA <= x"d002";
when "01" & x"c3e" => DATA <= x"f06e";
when "01" & x"c3f" => DATA <= x"a577";
when "01" & x"c40" => DATA <= x"f002";
when "01" & x"c41" => DATA <= x"e676";
when "01" & x"c42" => DATA <= x"c8b1";
when "01" & x"c43" => DATA <= x"7048";
when "01" & x"c44" => DATA <= x"a577";
when "01" & x"c45" => DATA <= x"f011";
when "01" & x"c46" => DATA <= x"a576";
when "01" & x"c47" => DATA <= x"c901";
when "01" & x"c48" => DATA <= x"d00b";
when "01" & x"c49" => DATA <= x"6848";
when "01" & x"c4a" => DATA <= x"c906";
when "01" & x"c4b" => DATA <= x"9005";
when "01" & x"c4c" => DATA <= x"6838";
when "01" & x"c4d" => DATA <= x"e906";
when "01" & x"c4e" => DATA <= x"48a5";
when "01" & x"c4f" => DATA <= x"7018";
when "01" & x"c50" => DATA <= x"6906";
when "01" & x"c51" => DATA <= x"aaa9";
when "01" & x"c52" => DATA <= x"0065";
when "01" & x"c53" => DATA <= x"71a8";
when "01" & x"c54" => DATA <= x"6848";
when "01" & x"c55" => DATA <= x"2006";
when "01" & x"c56" => DATA <= x"04a6";
when "01" & x"c57" => DATA <= x"7768";
when "01" & x"c58" => DATA <= x"a000";
when "01" & x"c59" => DATA <= x"c900";
when "01" & x"c5a" => DATA <= x"f01e";
when "01" & x"c5b" => DATA <= x"c901";
when "01" & x"c5c" => DATA <= x"f035";
when "01" & x"c5d" => DATA <= x"c902";
when "01" & x"c5e" => DATA <= x"f049";
when "01" & x"c5f" => DATA <= x"c903";
when "01" & x"c60" => DATA <= x"f070";
when "01" & x"c61" => DATA <= x"c906";
when "01" & x"c62" => DATA <= x"f008";
when "01" & x"c63" => DATA <= x"c907";
when "01" & x"c64" => DATA <= x"f007";
when "01" & x"c65" => DATA <= x"a900";
when "01" & x"c66" => DATA <= x"f01e";
when "01" & x"c67" => DATA <= x"4c75";
when "01" & x"c68" => DATA <= x"264c";
when "01" & x"c69" => DATA <= x"a326";
when "01" & x"c6a" => DATA <= x"20f4";
when "01" & x"c6b" => DATA <= x"26ad";
when "01" & x"c6c" => DATA <= x"e5fe";
when "01" & x"c6d" => DATA <= x"9174";
when "01" & x"c6e" => DATA <= x"20f4";
when "01" & x"c6f" => DATA <= x"26e6";
when "01" & x"c70" => DATA <= x"74d0";
when "01" & x"c71" => DATA <= x"02e6";
when "01" & x"c72" => DATA <= x"75ca";
when "01" & x"c73" => DATA <= x"d0ef";
when "01" & x"c74" => DATA <= x"c676";
when "01" & x"c75" => DATA <= x"d0eb";
when "01" & x"c76" => DATA <= x"4cda";
when "01" & x"c77" => DATA <= x"26b1";
when "01" & x"c78" => DATA <= x"748d";
when "01" & x"c79" => DATA <= x"e5fe";
when "01" & x"c7a" => DATA <= x"20f4";
when "01" & x"c7b" => DATA <= x"26e6";
when "01" & x"c7c" => DATA <= x"74d0";
when "01" & x"c7d" => DATA <= x"02e6";
when "01" & x"c7e" => DATA <= x"75ca";
when "01" & x"c7f" => DATA <= x"d0ef";
when "01" & x"c80" => DATA <= x"c676";
when "01" & x"c81" => DATA <= x"d0eb";
when "01" & x"c82" => DATA <= x"4cda";
when "01" & x"c83" => DATA <= x"2620";
when "01" & x"c84" => DATA <= x"f426";
when "01" & x"c85" => DATA <= x"ade5";
when "01" & x"c86" => DATA <= x"fe91";
when "01" & x"c87" => DATA <= x"74e6";
when "01" & x"c88" => DATA <= x"74d0";
when "01" & x"c89" => DATA <= x"02e6";
when "01" & x"c8a" => DATA <= x"75ea";
when "01" & x"c8b" => DATA <= x"eaad";
when "01" & x"c8c" => DATA <= x"e5fe";
when "01" & x"c8d" => DATA <= x"9174";
when "01" & x"c8e" => DATA <= x"e674";
when "01" & x"c8f" => DATA <= x"d002";
when "01" & x"c90" => DATA <= x"e675";
when "01" & x"c91" => DATA <= x"20f3";
when "01" & x"c92" => DATA <= x"26ea";
when "01" & x"c93" => DATA <= x"eaca";
when "01" & x"c94" => DATA <= x"cad0";
when "01" & x"c95" => DATA <= x"dfc6";
when "01" & x"c96" => DATA <= x"76d0";
when "01" & x"c97" => DATA <= x"db4c";
when "01" & x"c98" => DATA <= x"da26";
when "01" & x"c99" => DATA <= x"b174";
when "01" & x"c9a" => DATA <= x"8de5";
when "01" & x"c9b" => DATA <= x"fee6";
when "01" & x"c9c" => DATA <= x"74f0";
when "01" & x"c9d" => DATA <= x"03ea";
when "01" & x"c9e" => DATA <= x"d002";
when "01" & x"c9f" => DATA <= x"e675";
when "01" & x"ca0" => DATA <= x"a573";
when "01" & x"ca1" => DATA <= x"b174";
when "01" & x"ca2" => DATA <= x"8de5";
when "01" & x"ca3" => DATA <= x"fee6";
when "01" & x"ca4" => DATA <= x"74f0";
when "01" & x"ca5" => DATA <= x"03ea";
when "01" & x"ca6" => DATA <= x"d002";
when "01" & x"ca7" => DATA <= x"e675";
when "01" & x"ca8" => DATA <= x"20f3";
when "01" & x"ca9" => DATA <= x"26ca";
when "01" & x"caa" => DATA <= x"cad0";
when "01" & x"cab" => DATA <= x"dbc6";
when "01" & x"cac" => DATA <= x"76d0";
when "01" & x"cad" => DATA <= x"d7f0";
when "01" & x"cae" => DATA <= x"6520";
when "01" & x"caf" => DATA <= x"f426";
when "01" & x"cb0" => DATA <= x"ade5";
when "01" & x"cb1" => DATA <= x"fe91";
when "01" & x"cb2" => DATA <= x"74ea";
when "01" & x"cb3" => DATA <= x"eaea";
when "01" & x"cb4" => DATA <= x"c8d0";
when "01" & x"cb5" => DATA <= x"f5e0";
when "01" & x"cb6" => DATA <= x"00d0";
when "01" & x"cb7" => DATA <= x"0cc6";
when "01" & x"cb8" => DATA <= x"76f0";
when "01" & x"cb9" => DATA <= x"4f20";
when "01" & x"cba" => DATA <= x"ce26";
when "01" & x"cbb" => DATA <= x"a906";
when "01" & x"cbc" => DATA <= x"4c9f";
when "01" & x"cbd" => DATA <= x"25c6";
when "01" & x"cbe" => DATA <= x"76a5";
when "01" & x"cbf" => DATA <= x"76c9";
when "01" & x"cc0" => DATA <= x"01d0";
when "01" & x"cc1" => DATA <= x"f020";
when "01" & x"cc2" => DATA <= x"ce26";
when "01" & x"cc3" => DATA <= x"a900";
when "01" & x"cc4" => DATA <= x"4c9f";
when "01" & x"cc5" => DATA <= x"25b1";
when "01" & x"cc6" => DATA <= x"748d";
when "01" & x"cc7" => DATA <= x"e5fe";
when "01" & x"cc8" => DATA <= x"eaea";
when "01" & x"cc9" => DATA <= x"eac8";
when "01" & x"cca" => DATA <= x"d0f5";
when "01" & x"ccb" => DATA <= x"e000";
when "01" & x"ccc" => DATA <= x"d00c";
when "01" & x"ccd" => DATA <= x"c676";
when "01" & x"cce" => DATA <= x"f024";
when "01" & x"ccf" => DATA <= x"20ce";
when "01" & x"cd0" => DATA <= x"26a9";
when "01" & x"cd1" => DATA <= x"074c";
when "01" & x"cd2" => DATA <= x"9f25";
when "01" & x"cd3" => DATA <= x"c676";
when "01" & x"cd4" => DATA <= x"a576";
when "01" & x"cd5" => DATA <= x"c901";
when "01" & x"cd6" => DATA <= x"d0f0";
when "01" & x"cd7" => DATA <= x"20ce";
when "01" & x"cd8" => DATA <= x"26a9";
when "01" & x"cd9" => DATA <= x"014c";
when "01" & x"cda" => DATA <= x"9f25";
when "01" & x"cdb" => DATA <= x"e675";
when "01" & x"cdc" => DATA <= x"a007";
when "01" & x"cdd" => DATA <= x"b170";
when "01" & x"cde" => DATA <= x"1869";
when "01" & x"cdf" => DATA <= x"0191";
when "01" & x"ce0" => DATA <= x"7060";
when "01" & x"ce1" => DATA <= x"a987";
when "01" & x"ce2" => DATA <= x"2006";
when "01" & x"ce3" => DATA <= x"04a5";
when "01" & x"ce4" => DATA <= x"72c5";
when "01" & x"ce5" => DATA <= x"f4f0";
when "01" & x"ce6" => DATA <= x"0585";
when "01" & x"ce7" => DATA <= x"f48d";
when "01" & x"ce8" => DATA <= x"30fe";
when "01" & x"ce9" => DATA <= x"688d";
when "01" & x"cea" => DATA <= x"34fe";
when "01" & x"ceb" => DATA <= x"a670";
when "01" & x"cec" => DATA <= x"a471";
when "01" & x"ced" => DATA <= x"6860";
when "01" & x"cee" => DATA <= x"20f3";
when "01" & x"cef" => DATA <= x"2620";
when "01" & x"cf0" => DATA <= x"f326";
when "01" & x"cf1" => DATA <= x"6000";
when "01" & x"cf2" => DATA <= x"003c";
when "01" & x"cf3" => DATA <= x"ffff";
when "01" & x"cf4" => DATA <= x"4f52";
when "01" & x"cf5" => DATA <= x"4920";
when "01" & x"cf6" => DATA <= x"2000";
when "01" & x"cf7" => DATA <= x"003f";
when "01" & x"cf8" => DATA <= x"39e4";
when "01" & x"cf9" => DATA <= x"007c";
when "01" & x"cfa" => DATA <= x"ffff";
when "01" & x"cfb" => DATA <= x"4f52";
when "01" & x"cfc" => DATA <= x"4920";
when "01" & x"cfd" => DATA <= x"2000";
when "01" & x"cfe" => DATA <= x"003f";
when "01" & x"cff" => DATA <= x"39e4";
when "01" & x"d00" => DATA <= x"023c";
when "01" & x"d01" => DATA <= x"ffff";
when "01" & x"d02" => DATA <= x"414e";
when "01" & x"d03" => DATA <= x"4449";
when "01" & x"d04" => DATA <= x"2000";
when "01" & x"d05" => DATA <= x"003f";
when "01" & x"d06" => DATA <= x"39e4";
when "01" & x"d07" => DATA <= x"027c";
when "01" & x"d08" => DATA <= x"ffff";
when "01" & x"d09" => DATA <= x"414e";
when "01" & x"d0a" => DATA <= x"4449";
when "01" & x"d0b" => DATA <= x"2000";
when "01" & x"d0c" => DATA <= x"003f";
when "01" & x"d0d" => DATA <= x"39e4";
when "01" & x"d0e" => DATA <= x"0a3c";
when "01" & x"d0f" => DATA <= x"ffff";
when "01" & x"d10" => DATA <= x"454f";
when "01" & x"d11" => DATA <= x"5249";
when "01" & x"d12" => DATA <= x"2000";
when "01" & x"d13" => DATA <= x"003f";
when "01" & x"d14" => DATA <= x"39e4";
when "01" & x"d15" => DATA <= x"0a7c";
when "01" & x"d16" => DATA <= x"ffff";
when "01" & x"d17" => DATA <= x"454f";
when "01" & x"d18" => DATA <= x"5249";
when "01" & x"d19" => DATA <= x"2000";
when "01" & x"d1a" => DATA <= x"003f";
when "01" & x"d1b" => DATA <= x"39e4";
when "01" & x"d1c" => DATA <= x"0800";
when "01" & x"d1d" => DATA <= x"ffc0";
when "01" & x"d1e" => DATA <= x"4254";
when "01" & x"d1f" => DATA <= x"5354";
when "01" & x"d20" => DATA <= x"2000";
when "01" & x"d21" => DATA <= x"003f";
when "01" & x"d22" => DATA <= x"39e4";
when "01" & x"d23" => DATA <= x"0840";
when "01" & x"d24" => DATA <= x"ffc0";
when "01" & x"d25" => DATA <= x"4243";
when "01" & x"d26" => DATA <= x"4847";
when "01" & x"d27" => DATA <= x"2000";
when "01" & x"d28" => DATA <= x"003f";
when "01" & x"d29" => DATA <= x"39e4";
when "01" & x"d2a" => DATA <= x"0880";
when "01" & x"d2b" => DATA <= x"ffc0";
when "01" & x"d2c" => DATA <= x"4243";
when "01" & x"d2d" => DATA <= x"4c52";
when "01" & x"d2e" => DATA <= x"2000";
when "01" & x"d2f" => DATA <= x"003f";
when "01" & x"d30" => DATA <= x"39e4";
when "01" & x"d31" => DATA <= x"08c0";
when "01" & x"d32" => DATA <= x"ffc0";
when "01" & x"d33" => DATA <= x"4253";
when "01" & x"d34" => DATA <= x"4554";
when "01" & x"d35" => DATA <= x"2000";
when "01" & x"d36" => DATA <= x"003f";
when "01" & x"d37" => DATA <= x"39e4";
when "01" & x"d38" => DATA <= x"0000";
when "01" & x"d39" => DATA <= x"ff00";
when "01" & x"d3a" => DATA <= x"4f52";
when "01" & x"d3b" => DATA <= x"4920";
when "01" & x"d3c" => DATA <= x"2000";
when "01" & x"d3d" => DATA <= x"003f";
when "01" & x"d3e" => DATA <= x"39e4";
when "01" & x"d3f" => DATA <= x"0200";
when "01" & x"d40" => DATA <= x"ff00";
when "01" & x"d41" => DATA <= x"414e";
when "01" & x"d42" => DATA <= x"4449";
when "01" & x"d43" => DATA <= x"2000";
when "01" & x"d44" => DATA <= x"003f";
when "01" & x"d45" => DATA <= x"39e4";
when "01" & x"d46" => DATA <= x"0400";
when "01" & x"d47" => DATA <= x"ff00";
when "01" & x"d48" => DATA <= x"5355";
when "01" & x"d49" => DATA <= x"4249";
when "01" & x"d4a" => DATA <= x"2000";
when "01" & x"d4b" => DATA <= x"003f";
when "01" & x"d4c" => DATA <= x"39e4";
when "01" & x"d4d" => DATA <= x"0600";
when "01" & x"d4e" => DATA <= x"ff00";
when "01" & x"d4f" => DATA <= x"4144";
when "01" & x"d50" => DATA <= x"4449";
when "01" & x"d51" => DATA <= x"2000";
when "01" & x"d52" => DATA <= x"003f";
when "01" & x"d53" => DATA <= x"39e4";
when "01" & x"d54" => DATA <= x"0a00";
when "01" & x"d55" => DATA <= x"ff00";
when "01" & x"d56" => DATA <= x"454f";
when "01" & x"d57" => DATA <= x"5249";
when "01" & x"d58" => DATA <= x"2000";
when "01" & x"d59" => DATA <= x"003f";
when "01" & x"d5a" => DATA <= x"39e4";
when "01" & x"d5b" => DATA <= x"0c00";
when "01" & x"d5c" => DATA <= x"ff00";
when "01" & x"d5d" => DATA <= x"434d";
when "01" & x"d5e" => DATA <= x"5049";
when "01" & x"d5f" => DATA <= x"2000";
when "01" & x"d60" => DATA <= x"003f";
when "01" & x"d61" => DATA <= x"39e4";
when "01" & x"d62" => DATA <= x"0108";
when "01" & x"d63" => DATA <= x"f138";
when "01" & x"d64" => DATA <= x"4d4f";
when "01" & x"d65" => DATA <= x"5645";
when "01" & x"d66" => DATA <= x"5000";
when "01" & x"d67" => DATA <= x"003f";
when "01" & x"d68" => DATA <= x"39e4";
when "01" & x"d69" => DATA <= x"0100";
when "01" & x"d6a" => DATA <= x"f1c0";
when "01" & x"d6b" => DATA <= x"4254";
when "01" & x"d6c" => DATA <= x"5354";
when "01" & x"d6d" => DATA <= x"2000";
when "01" & x"d6e" => DATA <= x"003f";
when "01" & x"d6f" => DATA <= x"39e4";
when "01" & x"d70" => DATA <= x"0140";
when "01" & x"d71" => DATA <= x"f1c0";
when "01" & x"d72" => DATA <= x"4243";
when "01" & x"d73" => DATA <= x"4847";
when "01" & x"d74" => DATA <= x"2000";
when "01" & x"d75" => DATA <= x"003f";
when "01" & x"d76" => DATA <= x"39e4";
when "01" & x"d77" => DATA <= x"0180";
when "01" & x"d78" => DATA <= x"f1c0";
when "01" & x"d79" => DATA <= x"4243";
when "01" & x"d7a" => DATA <= x"4c52";
when "01" & x"d7b" => DATA <= x"2000";
when "01" & x"d7c" => DATA <= x"003f";
when "01" & x"d7d" => DATA <= x"39e4";
when "01" & x"d7e" => DATA <= x"01c0";
when "01" & x"d7f" => DATA <= x"f1c0";
when "01" & x"d80" => DATA <= x"4253";
when "01" & x"d81" => DATA <= x"4554";
when "01" & x"d82" => DATA <= x"2000";
when "01" & x"d83" => DATA <= x"003f";
when "01" & x"d84" => DATA <= x"39e4";
when "01" & x"d85" => DATA <= x"0040";
when "01" & x"d86" => DATA <= x"c1c0";
when "01" & x"d87" => DATA <= x"4d4f";
when "01" & x"d88" => DATA <= x"5645";
when "01" & x"d89" => DATA <= x"4100";
when "01" & x"d8a" => DATA <= x"003f";
when "01" & x"d8b" => DATA <= x"39e4";
when "01" & x"d8c" => DATA <= x"0000";
when "01" & x"d8d" => DATA <= x"c000";
when "01" & x"d8e" => DATA <= x"4d4f";
when "01" & x"d8f" => DATA <= x"5645";
when "01" & x"d90" => DATA <= x"2000";
when "01" & x"d91" => DATA <= x"003f";
when "01" & x"d92" => DATA <= x"39e4";
when "01" & x"d93" => DATA <= x"4afc";
when "01" & x"d94" => DATA <= x"ffff";
when "01" & x"d95" => DATA <= x"494c";
when "01" & x"d96" => DATA <= x"4c45";
when "01" & x"d97" => DATA <= x"4700";
when "01" & x"d98" => DATA <= x"003f";
when "01" & x"d99" => DATA <= x"39e4";
when "01" & x"d9a" => DATA <= x"4e70";
when "01" & x"d9b" => DATA <= x"ffff";
when "01" & x"d9c" => DATA <= x"5245";
when "01" & x"d9d" => DATA <= x"5345";
when "01" & x"d9e" => DATA <= x"5400";
when "01" & x"d9f" => DATA <= x"003f";
when "01" & x"da0" => DATA <= x"39e4";
when "01" & x"da1" => DATA <= x"4e71";
when "01" & x"da2" => DATA <= x"ffff";
when "01" & x"da3" => DATA <= x"4e4f";
when "01" & x"da4" => DATA <= x"5020";
when "01" & x"da5" => DATA <= x"2000";
when "01" & x"da6" => DATA <= x"003f";
when "01" & x"da7" => DATA <= x"39e4";
when "01" & x"da8" => DATA <= x"4e72";
when "01" & x"da9" => DATA <= x"ffff";
when "01" & x"daa" => DATA <= x"5354";
when "01" & x"dab" => DATA <= x"4f50";
when "01" & x"dac" => DATA <= x"2000";
when "01" & x"dad" => DATA <= x"003f";
when "01" & x"dae" => DATA <= x"39e4";
when "01" & x"daf" => DATA <= x"4e73";
when "01" & x"db0" => DATA <= x"ffff";
when "01" & x"db1" => DATA <= x"5254";
when "01" & x"db2" => DATA <= x"4520";
when "01" & x"db3" => DATA <= x"2000";
when "01" & x"db4" => DATA <= x"003f";
when "01" & x"db5" => DATA <= x"39e4";
when "01" & x"db6" => DATA <= x"4e75";
when "01" & x"db7" => DATA <= x"ffff";
when "01" & x"db8" => DATA <= x"5254";
when "01" & x"db9" => DATA <= x"5320";
when "01" & x"dba" => DATA <= x"2000";
when "01" & x"dbb" => DATA <= x"003f";
when "01" & x"dbc" => DATA <= x"39e4";
when "01" & x"dbd" => DATA <= x"4e76";
when "01" & x"dbe" => DATA <= x"ffff";
when "01" & x"dbf" => DATA <= x"5452";
when "01" & x"dc0" => DATA <= x"4150";
when "01" & x"dc1" => DATA <= x"5600";
when "01" & x"dc2" => DATA <= x"003f";
when "01" & x"dc3" => DATA <= x"39e4";
when "01" & x"dc4" => DATA <= x"4e77";
when "01" & x"dc5" => DATA <= x"ffff";
when "01" & x"dc6" => DATA <= x"5254";
when "01" & x"dc7" => DATA <= x"5220";
when "01" & x"dc8" => DATA <= x"2000";
when "01" & x"dc9" => DATA <= x"003f";
when "01" & x"dca" => DATA <= x"39e4";
when "01" & x"dcb" => DATA <= x"4840";
when "01" & x"dcc" => DATA <= x"fff8";
when "01" & x"dcd" => DATA <= x"5357";
when "01" & x"dce" => DATA <= x"4150";
when "01" & x"dcf" => DATA <= x"2000";
when "01" & x"dd0" => DATA <= x"003f";
when "01" & x"dd1" => DATA <= x"39e4";
when "01" & x"dd2" => DATA <= x"4e50";
when "01" & x"dd3" => DATA <= x"fff8";
when "01" & x"dd4" => DATA <= x"4c49";
when "01" & x"dd5" => DATA <= x"4e4b";
when "01" & x"dd6" => DATA <= x"2000";
when "01" & x"dd7" => DATA <= x"003f";
when "01" & x"dd8" => DATA <= x"39e4";
when "01" & x"dd9" => DATA <= x"4e58";
when "01" & x"dda" => DATA <= x"fff8";
when "01" & x"ddb" => DATA <= x"554e";
when "01" & x"ddc" => DATA <= x"4c4b";
when "01" & x"ddd" => DATA <= x"2000";
when "01" & x"dde" => DATA <= x"003f";
when "01" & x"ddf" => DATA <= x"39e4";
when "01" & x"de0" => DATA <= x"4e60";
when "01" & x"de1" => DATA <= x"fff0";
when "01" & x"de2" => DATA <= x"4d4f";
when "01" & x"de3" => DATA <= x"5645";
when "01" & x"de4" => DATA <= x"2000";
when "01" & x"de5" => DATA <= x"003f";
when "01" & x"de6" => DATA <= x"39e4";
when "01" & x"de7" => DATA <= x"4e40";
when "01" & x"de8" => DATA <= x"fff0";
when "01" & x"de9" => DATA <= x"5452";
when "01" & x"dea" => DATA <= x"4150";
when "01" & x"deb" => DATA <= x"2000";
when "01" & x"dec" => DATA <= x"003f";
when "01" & x"ded" => DATA <= x"39e4";
when "01" & x"dee" => DATA <= x"4e80";
when "01" & x"def" => DATA <= x"ffc0";
when "01" & x"df0" => DATA <= x"4a53";
when "01" & x"df1" => DATA <= x"5220";
when "01" & x"df2" => DATA <= x"2000";
when "01" & x"df3" => DATA <= x"003f";
when "01" & x"df4" => DATA <= x"39e4";
when "01" & x"df5" => DATA <= x"4ec0";
when "01" & x"df6" => DATA <= x"ffc0";
when "01" & x"df7" => DATA <= x"4a4d";
when "01" & x"df8" => DATA <= x"5020";
when "01" & x"df9" => DATA <= x"2000";
when "01" & x"dfa" => DATA <= x"003f";
when "01" & x"dfb" => DATA <= x"39e4";
when "01" & x"dfc" => DATA <= x"4880";
when "01" & x"dfd" => DATA <= x"feb8";
when "01" & x"dfe" => DATA <= x"4558";
when "01" & x"dff" => DATA <= x"5420";
when "01" & x"e00" => DATA <= x"2000";
when "01" & x"e01" => DATA <= x"003f";
when "01" & x"e02" => DATA <= x"39e4";
when "01" & x"e03" => DATA <= x"40c0";
when "01" & x"e04" => DATA <= x"ffc0";
when "01" & x"e05" => DATA <= x"4d4f";
when "01" & x"e06" => DATA <= x"5645";
when "01" & x"e07" => DATA <= x"2000";
when "01" & x"e08" => DATA <= x"003f";
when "01" & x"e09" => DATA <= x"39e4";
when "01" & x"e0a" => DATA <= x"44c0";
when "01" & x"e0b" => DATA <= x"ffc0";
when "01" & x"e0c" => DATA <= x"4d4f";
when "01" & x"e0d" => DATA <= x"5645";
when "01" & x"e0e" => DATA <= x"2000";
when "01" & x"e0f" => DATA <= x"003f";
when "01" & x"e10" => DATA <= x"39e4";
when "01" & x"e11" => DATA <= x"46c0";
when "01" & x"e12" => DATA <= x"ffc0";
when "01" & x"e13" => DATA <= x"4d4f";
when "01" & x"e14" => DATA <= x"5645";
when "01" & x"e15" => DATA <= x"2000";
when "01" & x"e16" => DATA <= x"003f";
when "01" & x"e17" => DATA <= x"39e4";
when "01" & x"e18" => DATA <= x"4800";
when "01" & x"e19" => DATA <= x"ffc0";
when "01" & x"e1a" => DATA <= x"4e42";
when "01" & x"e1b" => DATA <= x"4344";
when "01" & x"e1c" => DATA <= x"2000";
when "01" & x"e1d" => DATA <= x"003f";
when "01" & x"e1e" => DATA <= x"39e4";
when "01" & x"e1f" => DATA <= x"4840";
when "01" & x"e20" => DATA <= x"ffc0";
when "01" & x"e21" => DATA <= x"5045";
when "01" & x"e22" => DATA <= x"4120";
when "01" & x"e23" => DATA <= x"2000";
when "01" & x"e24" => DATA <= x"003f";
when "01" & x"e25" => DATA <= x"39e4";
when "01" & x"e26" => DATA <= x"4ac0";
when "01" & x"e27" => DATA <= x"ffc0";
when "01" & x"e28" => DATA <= x"5441";
when "01" & x"e29" => DATA <= x"5320";
when "01" & x"e2a" => DATA <= x"2000";
when "01" & x"e2b" => DATA <= x"003f";
when "01" & x"e2c" => DATA <= x"39e4";
when "01" & x"e2d" => DATA <= x"4000";
when "01" & x"e2e" => DATA <= x"ff00";
when "01" & x"e2f" => DATA <= x"4e45";
when "01" & x"e30" => DATA <= x"4758";
when "01" & x"e31" => DATA <= x"2000";
when "01" & x"e32" => DATA <= x"003f";
when "01" & x"e33" => DATA <= x"39e4";
when "01" & x"e34" => DATA <= x"4200";
when "01" & x"e35" => DATA <= x"ff00";
when "01" & x"e36" => DATA <= x"434c";
when "01" & x"e37" => DATA <= x"5220";
when "01" & x"e38" => DATA <= x"2000";
when "01" & x"e39" => DATA <= x"003f";
when "01" & x"e3a" => DATA <= x"39e4";
when "01" & x"e3b" => DATA <= x"4400";
when "01" & x"e3c" => DATA <= x"ff00";
when "01" & x"e3d" => DATA <= x"4e45";
when "01" & x"e3e" => DATA <= x"4720";
when "01" & x"e3f" => DATA <= x"2000";
when "01" & x"e40" => DATA <= x"003f";
when "01" & x"e41" => DATA <= x"39e4";
when "01" & x"e42" => DATA <= x"4600";
when "01" & x"e43" => DATA <= x"ff00";
when "01" & x"e44" => DATA <= x"4e4f";
when "01" & x"e45" => DATA <= x"5420";
when "01" & x"e46" => DATA <= x"2000";
when "01" & x"e47" => DATA <= x"003f";
when "01" & x"e48" => DATA <= x"39e4";
when "01" & x"e49" => DATA <= x"4a00";
when "01" & x"e4a" => DATA <= x"ff00";
when "01" & x"e4b" => DATA <= x"5453";
when "01" & x"e4c" => DATA <= x"5420";
when "01" & x"e4d" => DATA <= x"2000";
when "01" & x"e4e" => DATA <= x"003f";
when "01" & x"e4f" => DATA <= x"39e4";
when "01" & x"e50" => DATA <= x"4880";
when "01" & x"e51" => DATA <= x"fb80";
when "01" & x"e52" => DATA <= x"4d4f";
when "01" & x"e53" => DATA <= x"5645";
when "01" & x"e54" => DATA <= x"4d00";
when "01" & x"e55" => DATA <= x"003f";
when "01" & x"e56" => DATA <= x"39e4";
when "01" & x"e57" => DATA <= x"41c0";
when "01" & x"e58" => DATA <= x"f1c0";
when "01" & x"e59" => DATA <= x"4c45";
when "01" & x"e5a" => DATA <= x"4120";
when "01" & x"e5b" => DATA <= x"2000";
when "01" & x"e5c" => DATA <= x"003f";
when "01" & x"e5d" => DATA <= x"39e4";
when "01" & x"e5e" => DATA <= x"4000";
when "01" & x"e5f" => DATA <= x"f040";
when "01" & x"e60" => DATA <= x"4348";
when "01" & x"e61" => DATA <= x"4b20";
when "01" & x"e62" => DATA <= x"2000";
when "01" & x"e63" => DATA <= x"003f";
when "01" & x"e64" => DATA <= x"39e4";
when "01" & x"e65" => DATA <= x"50c8";
when "01" & x"e66" => DATA <= x"f0f8";
when "01" & x"e67" => DATA <= x"4442";
when "01" & x"e68" => DATA <= x"2020";
when "01" & x"e69" => DATA <= x"2000";
when "01" & x"e6a" => DATA <= x"003f";
when "01" & x"e6b" => DATA <= x"39e4";
when "01" & x"e6c" => DATA <= x"50c0";
when "01" & x"e6d" => DATA <= x"f0c0";
when "01" & x"e6e" => DATA <= x"5320";
when "01" & x"e6f" => DATA <= x"2020";
when "01" & x"e70" => DATA <= x"2000";
when "01" & x"e71" => DATA <= x"003f";
when "01" & x"e72" => DATA <= x"39e4";
when "01" & x"e73" => DATA <= x"5000";
when "01" & x"e74" => DATA <= x"f100";
when "01" & x"e75" => DATA <= x"4144";
when "01" & x"e76" => DATA <= x"4451";
when "01" & x"e77" => DATA <= x"2000";
when "01" & x"e78" => DATA <= x"003f";
when "01" & x"e79" => DATA <= x"39e4";
when "01" & x"e7a" => DATA <= x"5100";
when "01" & x"e7b" => DATA <= x"f100";
when "01" & x"e7c" => DATA <= x"5355";
when "01" & x"e7d" => DATA <= x"4251";
when "01" & x"e7e" => DATA <= x"2000";
when "01" & x"e7f" => DATA <= x"003f";
when "01" & x"e80" => DATA <= x"39e4";
when "01" & x"e81" => DATA <= x"6000";
when "01" & x"e82" => DATA <= x"ff00";
when "01" & x"e83" => DATA <= x"4252";
when "01" & x"e84" => DATA <= x"4120";
when "01" & x"e85" => DATA <= x"2000";
when "01" & x"e86" => DATA <= x"003f";
when "01" & x"e87" => DATA <= x"39e4";
when "01" & x"e88" => DATA <= x"6100";
when "01" & x"e89" => DATA <= x"ff00";
when "01" & x"e8a" => DATA <= x"4253";
when "01" & x"e8b" => DATA <= x"5220";
when "01" & x"e8c" => DATA <= x"2000";
when "01" & x"e8d" => DATA <= x"003f";
when "01" & x"e8e" => DATA <= x"39e4";
when "01" & x"e8f" => DATA <= x"6000";
when "01" & x"e90" => DATA <= x"f000";
when "01" & x"e91" => DATA <= x"4200";
when "01" & x"e92" => DATA <= x"0000";
when "01" & x"e93" => DATA <= x"0000";
when "01" & x"e94" => DATA <= x"003f";
when "01" & x"e95" => DATA <= x"39e4";
when "01" & x"e96" => DATA <= x"7000";
when "01" & x"e97" => DATA <= x"f100";
when "01" & x"e98" => DATA <= x"4d4f";
when "01" & x"e99" => DATA <= x"5645";
when "01" & x"e9a" => DATA <= x"5100";
when "01" & x"e9b" => DATA <= x"003f";
when "01" & x"e9c" => DATA <= x"39e4";
when "01" & x"e9d" => DATA <= x"8100";
when "01" & x"e9e" => DATA <= x"f1f0";
when "01" & x"e9f" => DATA <= x"5342";
when "01" & x"ea0" => DATA <= x"4344";
when "01" & x"ea1" => DATA <= x"2000";
when "01" & x"ea2" => DATA <= x"003f";
when "01" & x"ea3" => DATA <= x"39e4";
when "01" & x"ea4" => DATA <= x"80c0";
when "01" & x"ea5" => DATA <= x"f1c0";
when "01" & x"ea6" => DATA <= x"4449";
when "01" & x"ea7" => DATA <= x"5655";
when "01" & x"ea8" => DATA <= x"2000";
when "01" & x"ea9" => DATA <= x"003f";
when "01" & x"eaa" => DATA <= x"39e4";
when "01" & x"eab" => DATA <= x"81c0";
when "01" & x"eac" => DATA <= x"f1c0";
when "01" & x"ead" => DATA <= x"4449";
when "01" & x"eae" => DATA <= x"5653";
when "01" & x"eaf" => DATA <= x"2000";
when "01" & x"eb0" => DATA <= x"003f";
when "01" & x"eb1" => DATA <= x"39e4";
when "01" & x"eb2" => DATA <= x"8000";
when "01" & x"eb3" => DATA <= x"f000";
when "01" & x"eb4" => DATA <= x"4f52";
when "01" & x"eb5" => DATA <= x"2020";
when "01" & x"eb6" => DATA <= x"2000";
when "01" & x"eb7" => DATA <= x"003f";
when "01" & x"eb8" => DATA <= x"39e4";
when "01" & x"eb9" => DATA <= x"9100";
when "01" & x"eba" => DATA <= x"f130";
when "01" & x"ebb" => DATA <= x"5355";
when "01" & x"ebc" => DATA <= x"4258";
when "01" & x"ebd" => DATA <= x"2000";
when "01" & x"ebe" => DATA <= x"003f";
when "01" & x"ebf" => DATA <= x"39e4";
when "01" & x"ec0" => DATA <= x"90c0";
when "01" & x"ec1" => DATA <= x"f0c0";
when "01" & x"ec2" => DATA <= x"5355";
when "01" & x"ec3" => DATA <= x"4241";
when "01" & x"ec4" => DATA <= x"2000";
when "01" & x"ec5" => DATA <= x"003f";
when "01" & x"ec6" => DATA <= x"39e4";
when "01" & x"ec7" => DATA <= x"9000";
when "01" & x"ec8" => DATA <= x"f000";
when "01" & x"ec9" => DATA <= x"5355";
when "01" & x"eca" => DATA <= x"4220";
when "01" & x"ecb" => DATA <= x"2000";
when "01" & x"ecc" => DATA <= x"003f";
when "01" & x"ecd" => DATA <= x"39e4";
when "01" & x"ece" => DATA <= x"b108";
when "01" & x"ecf" => DATA <= x"f138";
when "01" & x"ed0" => DATA <= x"434d";
when "01" & x"ed1" => DATA <= x"504d";
when "01" & x"ed2" => DATA <= x"2000";
when "01" & x"ed3" => DATA <= x"003f";
when "01" & x"ed4" => DATA <= x"39e4";
when "01" & x"ed5" => DATA <= x"b0c0";
when "01" & x"ed6" => DATA <= x"f0c0";
when "01" & x"ed7" => DATA <= x"434d";
when "01" & x"ed8" => DATA <= x"5041";
when "01" & x"ed9" => DATA <= x"2000";
when "01" & x"eda" => DATA <= x"003f";
when "01" & x"edb" => DATA <= x"39e4";
when "01" & x"edc" => DATA <= x"b100";
when "01" & x"edd" => DATA <= x"f100";
when "01" & x"ede" => DATA <= x"454f";
when "01" & x"edf" => DATA <= x"5220";
when "01" & x"ee0" => DATA <= x"2000";
when "01" & x"ee1" => DATA <= x"003f";
when "01" & x"ee2" => DATA <= x"39e4";
when "01" & x"ee3" => DATA <= x"b000";
when "01" & x"ee4" => DATA <= x"f000";
when "01" & x"ee5" => DATA <= x"434d";
when "01" & x"ee6" => DATA <= x"5020";
when "01" & x"ee7" => DATA <= x"2000";
when "01" & x"ee8" => DATA <= x"003f";
when "01" & x"ee9" => DATA <= x"39e4";
when "01" & x"eea" => DATA <= x"c140";
when "01" & x"eeb" => DATA <= x"f1f8";
when "01" & x"eec" => DATA <= x"4558";
when "01" & x"eed" => DATA <= x"4720";
when "01" & x"eee" => DATA <= x"2000";
when "01" & x"eef" => DATA <= x"003f";
when "01" & x"ef0" => DATA <= x"39e4";
when "01" & x"ef1" => DATA <= x"c148";
when "01" & x"ef2" => DATA <= x"f1f8";
when "01" & x"ef3" => DATA <= x"4558";
when "01" & x"ef4" => DATA <= x"4720";
when "01" & x"ef5" => DATA <= x"2000";
when "01" & x"ef6" => DATA <= x"003f";
when "01" & x"ef7" => DATA <= x"39e4";
when "01" & x"ef8" => DATA <= x"c188";
when "01" & x"ef9" => DATA <= x"f1f8";
when "01" & x"efa" => DATA <= x"4558";
when "01" & x"efb" => DATA <= x"4720";
when "01" & x"efc" => DATA <= x"2000";
when "01" & x"efd" => DATA <= x"003f";
when "01" & x"efe" => DATA <= x"39e4";
when "01" & x"eff" => DATA <= x"c100";
when "01" & x"f00" => DATA <= x"f1f0";
when "01" & x"f01" => DATA <= x"4142";
when "01" & x"f02" => DATA <= x"4344";
when "01" & x"f03" => DATA <= x"2000";
when "01" & x"f04" => DATA <= x"003f";
when "01" & x"f05" => DATA <= x"39e4";
when "01" & x"f06" => DATA <= x"c1c0";
when "01" & x"f07" => DATA <= x"f1c0";
when "01" & x"f08" => DATA <= x"4d55";
when "01" & x"f09" => DATA <= x"4c53";
when "01" & x"f0a" => DATA <= x"2000";
when "01" & x"f0b" => DATA <= x"003f";
when "01" & x"f0c" => DATA <= x"39e4";
when "01" & x"f0d" => DATA <= x"c0c0";
when "01" & x"f0e" => DATA <= x"f1c0";
when "01" & x"f0f" => DATA <= x"4d55";
when "01" & x"f10" => DATA <= x"4c55";
when "01" & x"f11" => DATA <= x"2000";
when "01" & x"f12" => DATA <= x"003f";
when "01" & x"f13" => DATA <= x"39e4";
when "01" & x"f14" => DATA <= x"c000";
when "01" & x"f15" => DATA <= x"f000";
when "01" & x"f16" => DATA <= x"414e";
when "01" & x"f17" => DATA <= x"4420";
when "01" & x"f18" => DATA <= x"2000";
when "01" & x"f19" => DATA <= x"003f";
when "01" & x"f1a" => DATA <= x"39e4";
when "01" & x"f1b" => DATA <= x"d100";
when "01" & x"f1c" => DATA <= x"f130";
when "01" & x"f1d" => DATA <= x"4144";
when "01" & x"f1e" => DATA <= x"4458";
when "01" & x"f1f" => DATA <= x"2000";
when "01" & x"f20" => DATA <= x"003f";
when "01" & x"f21" => DATA <= x"39e4";
when "01" & x"f22" => DATA <= x"d0c0";
when "01" & x"f23" => DATA <= x"f0c0";
when "01" & x"f24" => DATA <= x"4144";
when "01" & x"f25" => DATA <= x"4441";
when "01" & x"f26" => DATA <= x"2000";
when "01" & x"f27" => DATA <= x"003f";
when "01" & x"f28" => DATA <= x"39e4";
when "01" & x"f29" => DATA <= x"d000";
when "01" & x"f2a" => DATA <= x"f000";
when "01" & x"f2b" => DATA <= x"4144";
when "01" & x"f2c" => DATA <= x"4420";
when "01" & x"f2d" => DATA <= x"2000";
when "01" & x"f2e" => DATA <= x"003f";
when "01" & x"f2f" => DATA <= x"39e4";
when "01" & x"f30" => DATA <= x"e0c0";
when "01" & x"f31" => DATA <= x"fec0";
when "01" & x"f32" => DATA <= x"4153";
when "01" & x"f33" => DATA <= x"2020";
when "01" & x"f34" => DATA <= x"2000";
when "01" & x"f35" => DATA <= x"003f";
when "01" & x"f36" => DATA <= x"39e4";
when "01" & x"f37" => DATA <= x"e2c0";
when "01" & x"f38" => DATA <= x"fec0";
when "01" & x"f39" => DATA <= x"4c53";
when "01" & x"f3a" => DATA <= x"2020";
when "01" & x"f3b" => DATA <= x"2000";
when "01" & x"f3c" => DATA <= x"003f";
when "01" & x"f3d" => DATA <= x"39e4";
when "01" & x"f3e" => DATA <= x"e4c0";
when "01" & x"f3f" => DATA <= x"fec0";
when "01" & x"f40" => DATA <= x"524f";
when "01" & x"f41" => DATA <= x"5820";
when "01" & x"f42" => DATA <= x"2000";
when "01" & x"f43" => DATA <= x"003f";
when "01" & x"f44" => DATA <= x"39e4";
when "01" & x"f45" => DATA <= x"e6c0";
when "01" & x"f46" => DATA <= x"fec0";
when "01" & x"f47" => DATA <= x"524f";
when "01" & x"f48" => DATA <= x"2020";
when "01" & x"f49" => DATA <= x"2000";
when "01" & x"f4a" => DATA <= x"003f";
when "01" & x"f4b" => DATA <= x"39e4";
when "01" & x"f4c" => DATA <= x"e000";
when "01" & x"f4d" => DATA <= x"f018";
when "01" & x"f4e" => DATA <= x"4153";
when "01" & x"f4f" => DATA <= x"2020";
when "01" & x"f50" => DATA <= x"2000";
when "01" & x"f51" => DATA <= x"003f";
when "01" & x"f52" => DATA <= x"39e4";
when "01" & x"f53" => DATA <= x"e008";
when "01" & x"f54" => DATA <= x"f018";
when "01" & x"f55" => DATA <= x"4c53";
when "01" & x"f56" => DATA <= x"2020";
when "01" & x"f57" => DATA <= x"2000";
when "01" & x"f58" => DATA <= x"003f";
when "01" & x"f59" => DATA <= x"39e4";
when "01" & x"f5a" => DATA <= x"e010";
when "01" & x"f5b" => DATA <= x"f018";
when "01" & x"f5c" => DATA <= x"524f";
when "01" & x"f5d" => DATA <= x"5820";
when "01" & x"f5e" => DATA <= x"2000";
when "01" & x"f5f" => DATA <= x"003f";
when "01" & x"f60" => DATA <= x"39e4";
when "01" & x"f61" => DATA <= x"e018";
when "01" & x"f62" => DATA <= x"f018";
when "01" & x"f63" => DATA <= x"524f";
when "01" & x"f64" => DATA <= x"2020";
when "01" & x"f65" => DATA <= x"2000";
when "01" & x"f66" => DATA <= x"003f";
when "01" & x"f67" => DATA <= x"39e4";
when "01" & x"f68" => DATA <= x"0000";
when "01" & x"f69" => DATA <= x"0000";
when "01" & x"f6a" => DATA <= x"3f3f";
when "01" & x"f6b" => DATA <= x"3f3f";
when "01" & x"f6c" => DATA <= x"3f00";
when "01" & x"f6d" => DATA <= x"003f";
when "01" & x"f6e" => DATA <= x"39e4";
when "01" & x"f6f" => DATA <= x"2532";
when "01" & x"f70" => DATA <= x"343a";
when "01" & x"f71" => DATA <= x"256d";
when "01" & x"f72" => DATA <= x"693a";
when "01" & x"f73" => DATA <= x"2573";
when "01" & x"f74" => DATA <= x"6520";
when "01" & x"f75" => DATA <= x"2564";
when "01" & x"f76" => DATA <= x"792d";
when "01" & x"f77" => DATA <= x"256d";
when "01" & x"f78" => DATA <= x"332d";
when "01" & x"f79" => DATA <= x"2563";
when "01" & x"f7a" => DATA <= x"6525";
when "01" & x"f7b" => DATA <= x"7972";
when "01" & x"f7c" => DATA <= x"0000";
when "01" & x"f7d" => DATA <= x"7c00";
when "01" & x"f7e" => DATA <= x"5206";
when "01" & x"f7f" => DATA <= x"bcbc";
when "01" & x"f80" => DATA <= x"0010";
when "01" & x"f81" => DATA <= x"0000";
when "01" & x"f82" => DATA <= x"66f6";
when "01" & x"f83" => DATA <= x"103c";
when "01" & x"f84" => DATA <= x"002a";
when "01" & x"f85" => DATA <= x"6100";
when "01" & x"f86" => DATA <= x"cade";
when "01" & x"f87" => DATA <= x"60e9";
when "01" & x"f88" => DATA <= x"0000";
when "01" & x"f89" => DATA <= x"0000";
when "01" & x"f8a" => DATA <= x"0000";
when "01" & x"f8b" => DATA <= x"0000";
when "01" & x"f8c" => DATA <= x"0000";
when "01" & x"f8d" => DATA <= x"0000";
when "01" & x"f8e" => DATA <= x"0000";
when "01" & x"f8f" => DATA <= x"0000";
when "01" & x"f90" => DATA <= x"0000";
when "01" & x"f91" => DATA <= x"0000";
when "01" & x"f92" => DATA <= x"0000";
when "01" & x"f93" => DATA <= x"0000";
when "01" & x"f94" => DATA <= x"0000";
when "01" & x"f95" => DATA <= x"0000";
when "01" & x"f96" => DATA <= x"0000";
when "01" & x"f97" => DATA <= x"0000";
when "01" & x"f98" => DATA <= x"0000";
when "01" & x"f99" => DATA <= x"0000";
when "01" & x"f9a" => DATA <= x"0000";
when "01" & x"f9b" => DATA <= x"0000";
when "01" & x"f9c" => DATA <= x"0000";
when "01" & x"f9d" => DATA <= x"0000";
when "01" & x"f9e" => DATA <= x"0000";
when "01" & x"f9f" => DATA <= x"0000";
when "01" & x"fa0" => DATA <= x"0000";
when "01" & x"fa1" => DATA <= x"0000";
when "01" & x"fa2" => DATA <= x"0000";
when "01" & x"fa3" => DATA <= x"0000";
when "01" & x"fa4" => DATA <= x"0000";
when "01" & x"fa5" => DATA <= x"0000";
when "01" & x"fa6" => DATA <= x"0000";
when "01" & x"fa7" => DATA <= x"0000";
when "01" & x"fa8" => DATA <= x"0000";
when "01" & x"fa9" => DATA <= x"0000";
when "01" & x"faa" => DATA <= x"0000";
when "01" & x"fab" => DATA <= x"0000";
when "01" & x"fac" => DATA <= x"0000";
when "01" & x"fad" => DATA <= x"0000";
when "01" & x"fae" => DATA <= x"0000";
when "01" & x"faf" => DATA <= x"0000";
when "01" & x"fb0" => DATA <= x"0000";
when "01" & x"fb1" => DATA <= x"0000";
when "01" & x"fb2" => DATA <= x"0000";
when "01" & x"fb3" => DATA <= x"0000";
when "01" & x"fb4" => DATA <= x"0000";
when "01" & x"fb5" => DATA <= x"0000";
when "01" & x"fb6" => DATA <= x"0000";
when "01" & x"fb7" => DATA <= x"0000";
when "01" & x"fb8" => DATA <= x"0000";
when "01" & x"fb9" => DATA <= x"0000";
when "01" & x"fba" => DATA <= x"0000";
when "01" & x"fbb" => DATA <= x"0000";
when "01" & x"fbc" => DATA <= x"0000";
when "01" & x"fbd" => DATA <= x"0000";
when "01" & x"fbe" => DATA <= x"0000";
when "01" & x"fbf" => DATA <= x"0000";
when "01" & x"fc0" => DATA <= x"0000";
when "01" & x"fc1" => DATA <= x"0000";
when "01" & x"fc2" => DATA <= x"0000";
when "01" & x"fc3" => DATA <= x"0000";
when "01" & x"fc4" => DATA <= x"0000";
when "01" & x"fc5" => DATA <= x"0000";
when "01" & x"fc6" => DATA <= x"0000";
when "01" & x"fc7" => DATA <= x"0000";
when "01" & x"fc8" => DATA <= x"0000";
when "01" & x"fc9" => DATA <= x"0000";
when "01" & x"fca" => DATA <= x"0000";
when "01" & x"fcb" => DATA <= x"0000";
when "01" & x"fcc" => DATA <= x"0000";
when "01" & x"fcd" => DATA <= x"0000";
when "01" & x"fce" => DATA <= x"0000";
when "01" & x"fcf" => DATA <= x"0000";
when "01" & x"fd0" => DATA <= x"0000";
when "01" & x"fd1" => DATA <= x"0000";
when "01" & x"fd2" => DATA <= x"0000";
when "01" & x"fd3" => DATA <= x"0000";
when "01" & x"fd4" => DATA <= x"0000";
when "01" & x"fd5" => DATA <= x"0000";
when "01" & x"fd6" => DATA <= x"0000";
when "01" & x"fd7" => DATA <= x"0000";
when "01" & x"fd8" => DATA <= x"0000";
when "01" & x"fd9" => DATA <= x"0000";
when "01" & x"fda" => DATA <= x"0000";
when "01" & x"fdb" => DATA <= x"0000";
when "01" & x"fdc" => DATA <= x"0000";
when "01" & x"fdd" => DATA <= x"0000";
when "01" & x"fde" => DATA <= x"0000";
when "01" & x"fdf" => DATA <= x"0000";
when "01" & x"fe0" => DATA <= x"0000";
when "01" & x"fe1" => DATA <= x"0000";
when "01" & x"fe2" => DATA <= x"0000";
when "01" & x"fe3" => DATA <= x"0000";
when "01" & x"fe4" => DATA <= x"0000";
when "01" & x"fe5" => DATA <= x"0000";
when "01" & x"fe6" => DATA <= x"0000";
when "01" & x"fe7" => DATA <= x"0000";
when "01" & x"fe8" => DATA <= x"0000";
when "01" & x"fe9" => DATA <= x"0000";
when "01" & x"fea" => DATA <= x"0000";
when "01" & x"feb" => DATA <= x"0000";
when "01" & x"fec" => DATA <= x"0000";
when "01" & x"fed" => DATA <= x"0000";
when "01" & x"fee" => DATA <= x"0000";
when "01" & x"fef" => DATA <= x"0000";
when "01" & x"ff0" => DATA <= x"0000";
when "01" & x"ff1" => DATA <= x"0000";
when "01" & x"ff2" => DATA <= x"0000";
when "01" & x"ff3" => DATA <= x"0000";
when "01" & x"ff4" => DATA <= x"0000";
when "01" & x"ff5" => DATA <= x"0000";
when "01" & x"ff6" => DATA <= x"0000";
when "01" & x"ff7" => DATA <= x"0000";
when "01" & x"ff8" => DATA <= x"0000";
when "01" & x"ff9" => DATA <= x"0000";
when "01" & x"ffa" => DATA <= x"0000";
when "01" & x"ffb" => DATA <= x"0000";
when "01" & x"ffc" => DATA <= x"0000";
when "01" & x"ffd" => DATA <= x"0000";
when "01" & x"ffe" => DATA <= x"0000";
when "01" & x"fff" => DATA <= x"0000";
when "10" & x"000" => DATA <= x"0000";
when "10" & x"001" => DATA <= x"0000";
when "10" & x"002" => DATA <= x"0000";
when "10" & x"003" => DATA <= x"0000";
when "10" & x"004" => DATA <= x"0000";
when "10" & x"005" => DATA <= x"0000";
when "10" & x"006" => DATA <= x"0000";
when "10" & x"007" => DATA <= x"0000";
when "10" & x"008" => DATA <= x"0000";
when "10" & x"009" => DATA <= x"0000";
when "10" & x"00a" => DATA <= x"0000";
when "10" & x"00b" => DATA <= x"0000";
when "10" & x"00c" => DATA <= x"0000";
when "10" & x"00d" => DATA <= x"0000";
when "10" & x"00e" => DATA <= x"0000";
when "10" & x"00f" => DATA <= x"0000";
when "10" & x"010" => DATA <= x"0000";
when "10" & x"011" => DATA <= x"0000";
when "10" & x"012" => DATA <= x"0000";
when "10" & x"013" => DATA <= x"0000";
when "10" & x"014" => DATA <= x"0000";
when "10" & x"015" => DATA <= x"0000";
when "10" & x"016" => DATA <= x"0000";
when "10" & x"017" => DATA <= x"0000";
when "10" & x"018" => DATA <= x"0000";
when "10" & x"019" => DATA <= x"0000";
when "10" & x"01a" => DATA <= x"0000";
when "10" & x"01b" => DATA <= x"0000";
when "10" & x"01c" => DATA <= x"0000";
when "10" & x"01d" => DATA <= x"0000";
when "10" & x"01e" => DATA <= x"0000";
when "10" & x"01f" => DATA <= x"0000";
when "10" & x"020" => DATA <= x"0000";
when "10" & x"021" => DATA <= x"0000";
when "10" & x"022" => DATA <= x"0000";
when "10" & x"023" => DATA <= x"0000";
when "10" & x"024" => DATA <= x"0000";
when "10" & x"025" => DATA <= x"0000";
when "10" & x"026" => DATA <= x"0000";
when "10" & x"027" => DATA <= x"0000";
when "10" & x"028" => DATA <= x"0000";
when "10" & x"029" => DATA <= x"0000";
when "10" & x"02a" => DATA <= x"0000";
when "10" & x"02b" => DATA <= x"0000";
when "10" & x"02c" => DATA <= x"0000";
when "10" & x"02d" => DATA <= x"0000";
when "10" & x"02e" => DATA <= x"0000";
when "10" & x"02f" => DATA <= x"0000";
when "10" & x"030" => DATA <= x"0000";
when "10" & x"031" => DATA <= x"0000";
when "10" & x"032" => DATA <= x"0000";
when "10" & x"033" => DATA <= x"0000";
when "10" & x"034" => DATA <= x"0000";
when "10" & x"035" => DATA <= x"0000";
when "10" & x"036" => DATA <= x"0000";
when "10" & x"037" => DATA <= x"0000";
when "10" & x"038" => DATA <= x"0000";
when "10" & x"039" => DATA <= x"0000";
when "10" & x"03a" => DATA <= x"0000";
when "10" & x"03b" => DATA <= x"0000";
when "10" & x"03c" => DATA <= x"0000";
when "10" & x"03d" => DATA <= x"0000";
when "10" & x"03e" => DATA <= x"0000";
when "10" & x"03f" => DATA <= x"0000";
when "10" & x"040" => DATA <= x"0000";
when "10" & x"041" => DATA <= x"0000";
when "10" & x"042" => DATA <= x"0000";
when "10" & x"043" => DATA <= x"0000";
when "10" & x"044" => DATA <= x"0000";
when "10" & x"045" => DATA <= x"0000";
when "10" & x"046" => DATA <= x"0000";
when "10" & x"047" => DATA <= x"0000";
when "10" & x"048" => DATA <= x"0000";
when "10" & x"049" => DATA <= x"0000";
when "10" & x"04a" => DATA <= x"0000";
when "10" & x"04b" => DATA <= x"0000";
when "10" & x"04c" => DATA <= x"0000";
when "10" & x"04d" => DATA <= x"0000";
when "10" & x"04e" => DATA <= x"0000";
when "10" & x"04f" => DATA <= x"0000";
when "10" & x"050" => DATA <= x"0000";
when "10" & x"051" => DATA <= x"0000";
when "10" & x"052" => DATA <= x"0000";
when "10" & x"053" => DATA <= x"0000";
when "10" & x"054" => DATA <= x"0000";
when "10" & x"055" => DATA <= x"0000";
when "10" & x"056" => DATA <= x"0000";
when "10" & x"057" => DATA <= x"0000";
when "10" & x"058" => DATA <= x"0000";
when "10" & x"059" => DATA <= x"0000";
when "10" & x"05a" => DATA <= x"0000";
when "10" & x"05b" => DATA <= x"0000";
when "10" & x"05c" => DATA <= x"0000";
when "10" & x"05d" => DATA <= x"0000";
when "10" & x"05e" => DATA <= x"0000";
when "10" & x"05f" => DATA <= x"0000";
when "10" & x"060" => DATA <= x"0000";
when "10" & x"061" => DATA <= x"0000";
when "10" & x"062" => DATA <= x"0000";
when "10" & x"063" => DATA <= x"0000";
when "10" & x"064" => DATA <= x"0000";
when "10" & x"065" => DATA <= x"0000";
when "10" & x"066" => DATA <= x"0000";
when "10" & x"067" => DATA <= x"0000";
when "10" & x"068" => DATA <= x"0000";
when "10" & x"069" => DATA <= x"0000";
when "10" & x"06a" => DATA <= x"0000";
when "10" & x"06b" => DATA <= x"0000";
when "10" & x"06c" => DATA <= x"0000";
when "10" & x"06d" => DATA <= x"0000";
when "10" & x"06e" => DATA <= x"0000";
when "10" & x"06f" => DATA <= x"0000";
when "10" & x"070" => DATA <= x"0000";
when "10" & x"071" => DATA <= x"0000";
when "10" & x"072" => DATA <= x"0000";
when "10" & x"073" => DATA <= x"0000";
when "10" & x"074" => DATA <= x"0000";
when "10" & x"075" => DATA <= x"0000";
when "10" & x"076" => DATA <= x"0000";
when "10" & x"077" => DATA <= x"0000";
when "10" & x"078" => DATA <= x"0000";
when "10" & x"079" => DATA <= x"0000";
when "10" & x"07a" => DATA <= x"0000";
when "10" & x"07b" => DATA <= x"0000";
when "10" & x"07c" => DATA <= x"0000";
when "10" & x"07d" => DATA <= x"0000";
when "10" & x"07e" => DATA <= x"0000";
when "10" & x"07f" => DATA <= x"0000";
when "10" & x"080" => DATA <= x"0000";
when "10" & x"081" => DATA <= x"0000";
when "10" & x"082" => DATA <= x"0000";
when "10" & x"083" => DATA <= x"0000";
when "10" & x"084" => DATA <= x"0000";
when "10" & x"085" => DATA <= x"0000";
when "10" & x"086" => DATA <= x"0000";
when "10" & x"087" => DATA <= x"0000";
when "10" & x"088" => DATA <= x"0000";
when "10" & x"089" => DATA <= x"0000";
when "10" & x"08a" => DATA <= x"0000";
when "10" & x"08b" => DATA <= x"0000";
when "10" & x"08c" => DATA <= x"0000";
when "10" & x"08d" => DATA <= x"0000";
when "10" & x"08e" => DATA <= x"0000";
when "10" & x"08f" => DATA <= x"0000";
when "10" & x"090" => DATA <= x"0000";
when "10" & x"091" => DATA <= x"0000";
when "10" & x"092" => DATA <= x"0000";
when "10" & x"093" => DATA <= x"0000";
when "10" & x"094" => DATA <= x"0000";
when "10" & x"095" => DATA <= x"0000";
when "10" & x"096" => DATA <= x"0000";
when "10" & x"097" => DATA <= x"0000";
when "10" & x"098" => DATA <= x"0000";
when "10" & x"099" => DATA <= x"0000";
when "10" & x"09a" => DATA <= x"0000";
when "10" & x"09b" => DATA <= x"0000";
when "10" & x"09c" => DATA <= x"0000";
when "10" & x"09d" => DATA <= x"0000";
when "10" & x"09e" => DATA <= x"0000";
when "10" & x"09f" => DATA <= x"0000";
when "10" & x"0a0" => DATA <= x"0000";
when "10" & x"0a1" => DATA <= x"0000";
when "10" & x"0a2" => DATA <= x"0000";
when "10" & x"0a3" => DATA <= x"0000";
when "10" & x"0a4" => DATA <= x"0000";
when "10" & x"0a5" => DATA <= x"0000";
when "10" & x"0a6" => DATA <= x"0000";
when "10" & x"0a7" => DATA <= x"0000";
when "10" & x"0a8" => DATA <= x"0000";
when "10" & x"0a9" => DATA <= x"0000";
when "10" & x"0aa" => DATA <= x"0000";
when "10" & x"0ab" => DATA <= x"0000";
when "10" & x"0ac" => DATA <= x"0000";
when "10" & x"0ad" => DATA <= x"0000";
when "10" & x"0ae" => DATA <= x"0000";
when "10" & x"0af" => DATA <= x"0000";
when "10" & x"0b0" => DATA <= x"0000";
when "10" & x"0b1" => DATA <= x"0000";
when "10" & x"0b2" => DATA <= x"0000";
when "10" & x"0b3" => DATA <= x"0000";
when "10" & x"0b4" => DATA <= x"0000";
when "10" & x"0b5" => DATA <= x"0000";
when "10" & x"0b6" => DATA <= x"0000";
when "10" & x"0b7" => DATA <= x"0000";
when "10" & x"0b8" => DATA <= x"0000";
when "10" & x"0b9" => DATA <= x"0000";
when "10" & x"0ba" => DATA <= x"0000";
when "10" & x"0bb" => DATA <= x"0000";
when "10" & x"0bc" => DATA <= x"0000";
when "10" & x"0bd" => DATA <= x"0000";
when "10" & x"0be" => DATA <= x"0000";
when "10" & x"0bf" => DATA <= x"0000";
when "10" & x"0c0" => DATA <= x"0000";
when "10" & x"0c1" => DATA <= x"0000";
when "10" & x"0c2" => DATA <= x"0000";
when "10" & x"0c3" => DATA <= x"0000";
when "10" & x"0c4" => DATA <= x"0000";
when "10" & x"0c5" => DATA <= x"0000";
when "10" & x"0c6" => DATA <= x"0000";
when "10" & x"0c7" => DATA <= x"0000";
when "10" & x"0c8" => DATA <= x"0000";
when "10" & x"0c9" => DATA <= x"0000";
when "10" & x"0ca" => DATA <= x"0000";
when "10" & x"0cb" => DATA <= x"0000";
when "10" & x"0cc" => DATA <= x"0000";
when "10" & x"0cd" => DATA <= x"0000";
when "10" & x"0ce" => DATA <= x"0000";
when "10" & x"0cf" => DATA <= x"0000";
when "10" & x"0d0" => DATA <= x"0000";
when "10" & x"0d1" => DATA <= x"0000";
when "10" & x"0d2" => DATA <= x"0000";
when "10" & x"0d3" => DATA <= x"0000";
when "10" & x"0d4" => DATA <= x"0000";
when "10" & x"0d5" => DATA <= x"0000";
when "10" & x"0d6" => DATA <= x"0000";
when "10" & x"0d7" => DATA <= x"0000";
when "10" & x"0d8" => DATA <= x"0000";
when "10" & x"0d9" => DATA <= x"0000";
when "10" & x"0da" => DATA <= x"0000";
when "10" & x"0db" => DATA <= x"0000";
when "10" & x"0dc" => DATA <= x"0000";
when "10" & x"0dd" => DATA <= x"0000";
when "10" & x"0de" => DATA <= x"0000";
when "10" & x"0df" => DATA <= x"0000";
when "10" & x"0e0" => DATA <= x"0000";
when "10" & x"0e1" => DATA <= x"0000";
when "10" & x"0e2" => DATA <= x"0000";
when "10" & x"0e3" => DATA <= x"0000";
when "10" & x"0e4" => DATA <= x"0000";
when "10" & x"0e5" => DATA <= x"0000";
when "10" & x"0e6" => DATA <= x"0000";
when "10" & x"0e7" => DATA <= x"0000";
when "10" & x"0e8" => DATA <= x"0000";
when "10" & x"0e9" => DATA <= x"0000";
when "10" & x"0ea" => DATA <= x"0000";
when "10" & x"0eb" => DATA <= x"0000";
when "10" & x"0ec" => DATA <= x"0000";
when "10" & x"0ed" => DATA <= x"0000";
when "10" & x"0ee" => DATA <= x"0000";
when "10" & x"0ef" => DATA <= x"0000";
when "10" & x"0f0" => DATA <= x"0000";
when "10" & x"0f1" => DATA <= x"0000";
when "10" & x"0f2" => DATA <= x"0000";
when "10" & x"0f3" => DATA <= x"0000";
when "10" & x"0f4" => DATA <= x"0000";
when "10" & x"0f5" => DATA <= x"0000";
when "10" & x"0f6" => DATA <= x"0000";
when "10" & x"0f7" => DATA <= x"0000";
when "10" & x"0f8" => DATA <= x"0000";
when "10" & x"0f9" => DATA <= x"0000";
when "10" & x"0fa" => DATA <= x"0000";
when "10" & x"0fb" => DATA <= x"0000";
when "10" & x"0fc" => DATA <= x"0000";
when "10" & x"0fd" => DATA <= x"0000";
when "10" & x"0fe" => DATA <= x"0000";
when "10" & x"0ff" => DATA <= x"0000";
when "10" & x"100" => DATA <= x"0000";
when "10" & x"101" => DATA <= x"0000";
when "10" & x"102" => DATA <= x"0000";
when "10" & x"103" => DATA <= x"0000";
when "10" & x"104" => DATA <= x"0000";
when "10" & x"105" => DATA <= x"0000";
when "10" & x"106" => DATA <= x"0000";
when "10" & x"107" => DATA <= x"0000";
when "10" & x"108" => DATA <= x"0000";
when "10" & x"109" => DATA <= x"0000";
when "10" & x"10a" => DATA <= x"0000";
when "10" & x"10b" => DATA <= x"0000";
when "10" & x"10c" => DATA <= x"0000";
when "10" & x"10d" => DATA <= x"0000";
when "10" & x"10e" => DATA <= x"0000";
when "10" & x"10f" => DATA <= x"0000";
when "10" & x"110" => DATA <= x"0000";
when "10" & x"111" => DATA <= x"0000";
when "10" & x"112" => DATA <= x"0000";
when "10" & x"113" => DATA <= x"0000";
when "10" & x"114" => DATA <= x"0000";
when "10" & x"115" => DATA <= x"0000";
when "10" & x"116" => DATA <= x"0000";
when "10" & x"117" => DATA <= x"0000";
when "10" & x"118" => DATA <= x"0000";
when "10" & x"119" => DATA <= x"0000";
when "10" & x"11a" => DATA <= x"0000";
when "10" & x"11b" => DATA <= x"0000";
when "10" & x"11c" => DATA <= x"0000";
when "10" & x"11d" => DATA <= x"0000";
when "10" & x"11e" => DATA <= x"0000";
when "10" & x"11f" => DATA <= x"0000";
when "10" & x"120" => DATA <= x"0000";
when "10" & x"121" => DATA <= x"0000";
when "10" & x"122" => DATA <= x"0000";
when "10" & x"123" => DATA <= x"0000";
when "10" & x"124" => DATA <= x"0000";
when "10" & x"125" => DATA <= x"0000";
when "10" & x"126" => DATA <= x"0000";
when "10" & x"127" => DATA <= x"0000";
when "10" & x"128" => DATA <= x"0000";
when "10" & x"129" => DATA <= x"0000";
when "10" & x"12a" => DATA <= x"0000";
when "10" & x"12b" => DATA <= x"0000";
when "10" & x"12c" => DATA <= x"0000";
when "10" & x"12d" => DATA <= x"0000";
when "10" & x"12e" => DATA <= x"0000";
when "10" & x"12f" => DATA <= x"0000";
when "10" & x"130" => DATA <= x"0000";
when "10" & x"131" => DATA <= x"0000";
when "10" & x"132" => DATA <= x"0000";
when "10" & x"133" => DATA <= x"0000";
when "10" & x"134" => DATA <= x"0000";
when "10" & x"135" => DATA <= x"0000";
when "10" & x"136" => DATA <= x"0000";
when "10" & x"137" => DATA <= x"0000";
when "10" & x"138" => DATA <= x"0000";
when "10" & x"139" => DATA <= x"0000";
when "10" & x"13a" => DATA <= x"0000";
when "10" & x"13b" => DATA <= x"0000";
when "10" & x"13c" => DATA <= x"0000";
when "10" & x"13d" => DATA <= x"0000";
when "10" & x"13e" => DATA <= x"0000";
when "10" & x"13f" => DATA <= x"0000";
when "10" & x"140" => DATA <= x"0000";
when "10" & x"141" => DATA <= x"0000";
when "10" & x"142" => DATA <= x"0000";
when "10" & x"143" => DATA <= x"0000";
when "10" & x"144" => DATA <= x"0000";
when "10" & x"145" => DATA <= x"0000";
when "10" & x"146" => DATA <= x"0000";
when "10" & x"147" => DATA <= x"0000";
when "10" & x"148" => DATA <= x"0000";
when "10" & x"149" => DATA <= x"0000";
when "10" & x"14a" => DATA <= x"0000";
when "10" & x"14b" => DATA <= x"0000";
when "10" & x"14c" => DATA <= x"0000";
when "10" & x"14d" => DATA <= x"0000";
when "10" & x"14e" => DATA <= x"0000";
when "10" & x"14f" => DATA <= x"0000";
when "10" & x"150" => DATA <= x"0000";
when "10" & x"151" => DATA <= x"0000";
when "10" & x"152" => DATA <= x"0000";
when "10" & x"153" => DATA <= x"0000";
when "10" & x"154" => DATA <= x"0000";
when "10" & x"155" => DATA <= x"0000";
when "10" & x"156" => DATA <= x"0000";
when "10" & x"157" => DATA <= x"0000";
when "10" & x"158" => DATA <= x"0000";
when "10" & x"159" => DATA <= x"0000";
when "10" & x"15a" => DATA <= x"0000";
when "10" & x"15b" => DATA <= x"0000";
when "10" & x"15c" => DATA <= x"0000";
when "10" & x"15d" => DATA <= x"0000";
when "10" & x"15e" => DATA <= x"0000";
when "10" & x"15f" => DATA <= x"0000";
when "10" & x"160" => DATA <= x"0000";
when "10" & x"161" => DATA <= x"0000";
when "10" & x"162" => DATA <= x"0000";
when "10" & x"163" => DATA <= x"0000";
when "10" & x"164" => DATA <= x"0000";
when "10" & x"165" => DATA <= x"0000";
when "10" & x"166" => DATA <= x"0000";
when "10" & x"167" => DATA <= x"0000";
when "10" & x"168" => DATA <= x"0000";
when "10" & x"169" => DATA <= x"0000";
when "10" & x"16a" => DATA <= x"0000";
when "10" & x"16b" => DATA <= x"0000";
when "10" & x"16c" => DATA <= x"0000";
when "10" & x"16d" => DATA <= x"0000";
when "10" & x"16e" => DATA <= x"0000";
when "10" & x"16f" => DATA <= x"0000";
when "10" & x"170" => DATA <= x"0000";
when "10" & x"171" => DATA <= x"0000";
when "10" & x"172" => DATA <= x"0000";
when "10" & x"173" => DATA <= x"0000";
when "10" & x"174" => DATA <= x"0000";
when "10" & x"175" => DATA <= x"0000";
when "10" & x"176" => DATA <= x"0000";
when "10" & x"177" => DATA <= x"0000";
when "10" & x"178" => DATA <= x"0000";
when "10" & x"179" => DATA <= x"0000";
when "10" & x"17a" => DATA <= x"0000";
when "10" & x"17b" => DATA <= x"0000";
when "10" & x"17c" => DATA <= x"0000";
when "10" & x"17d" => DATA <= x"0000";
when "10" & x"17e" => DATA <= x"0000";
when "10" & x"17f" => DATA <= x"0000";
when "10" & x"180" => DATA <= x"0000";
when "10" & x"181" => DATA <= x"0000";
when "10" & x"182" => DATA <= x"0000";
when "10" & x"183" => DATA <= x"0000";
when "10" & x"184" => DATA <= x"0000";
when "10" & x"185" => DATA <= x"0000";
when "10" & x"186" => DATA <= x"0000";
when "10" & x"187" => DATA <= x"0000";
when "10" & x"188" => DATA <= x"0000";
when "10" & x"189" => DATA <= x"0000";
when "10" & x"18a" => DATA <= x"0000";
when "10" & x"18b" => DATA <= x"0000";
when "10" & x"18c" => DATA <= x"0000";
when "10" & x"18d" => DATA <= x"0000";
when "10" & x"18e" => DATA <= x"0000";
when "10" & x"18f" => DATA <= x"0000";
when "10" & x"190" => DATA <= x"0000";
when "10" & x"191" => DATA <= x"0000";
when "10" & x"192" => DATA <= x"0000";
when "10" & x"193" => DATA <= x"0000";
when "10" & x"194" => DATA <= x"0000";
when "10" & x"195" => DATA <= x"0000";
when "10" & x"196" => DATA <= x"0000";
when "10" & x"197" => DATA <= x"0000";
when "10" & x"198" => DATA <= x"0000";
when "10" & x"199" => DATA <= x"0000";
when "10" & x"19a" => DATA <= x"0000";
when "10" & x"19b" => DATA <= x"0000";
when "10" & x"19c" => DATA <= x"0000";
when "10" & x"19d" => DATA <= x"0000";
when "10" & x"19e" => DATA <= x"0000";
when "10" & x"19f" => DATA <= x"0000";
when "10" & x"1a0" => DATA <= x"0000";
when "10" & x"1a1" => DATA <= x"0000";
when "10" & x"1a2" => DATA <= x"0000";
when "10" & x"1a3" => DATA <= x"0000";
when "10" & x"1a4" => DATA <= x"0000";
when "10" & x"1a5" => DATA <= x"0000";
when "10" & x"1a6" => DATA <= x"0000";
when "10" & x"1a7" => DATA <= x"0000";
when "10" & x"1a8" => DATA <= x"0000";
when "10" & x"1a9" => DATA <= x"0000";
when "10" & x"1aa" => DATA <= x"0000";
when "10" & x"1ab" => DATA <= x"0000";
when "10" & x"1ac" => DATA <= x"0000";
when "10" & x"1ad" => DATA <= x"0000";
when "10" & x"1ae" => DATA <= x"0000";
when "10" & x"1af" => DATA <= x"0000";
when "10" & x"1b0" => DATA <= x"0000";
when "10" & x"1b1" => DATA <= x"0000";
when "10" & x"1b2" => DATA <= x"0000";
when "10" & x"1b3" => DATA <= x"0000";
when "10" & x"1b4" => DATA <= x"0000";
when "10" & x"1b5" => DATA <= x"0000";
when "10" & x"1b6" => DATA <= x"0000";
when "10" & x"1b7" => DATA <= x"0000";
when "10" & x"1b8" => DATA <= x"0000";
when "10" & x"1b9" => DATA <= x"0000";
when "10" & x"1ba" => DATA <= x"0000";
when "10" & x"1bb" => DATA <= x"0000";
when "10" & x"1bc" => DATA <= x"0000";
when "10" & x"1bd" => DATA <= x"0000";
when "10" & x"1be" => DATA <= x"0000";
when "10" & x"1bf" => DATA <= x"0000";
when "10" & x"1c0" => DATA <= x"0000";
when "10" & x"1c1" => DATA <= x"0000";
when "10" & x"1c2" => DATA <= x"0000";
when "10" & x"1c3" => DATA <= x"0000";
when "10" & x"1c4" => DATA <= x"0000";
when "10" & x"1c5" => DATA <= x"0000";
when "10" & x"1c6" => DATA <= x"0000";
when "10" & x"1c7" => DATA <= x"0000";
when "10" & x"1c8" => DATA <= x"0000";
when "10" & x"1c9" => DATA <= x"0000";
when "10" & x"1ca" => DATA <= x"0000";
when "10" & x"1cb" => DATA <= x"0000";
when "10" & x"1cc" => DATA <= x"0000";
when "10" & x"1cd" => DATA <= x"0000";
when "10" & x"1ce" => DATA <= x"0000";
when "10" & x"1cf" => DATA <= x"0000";
when "10" & x"1d0" => DATA <= x"0000";
when "10" & x"1d1" => DATA <= x"0000";
when "10" & x"1d2" => DATA <= x"0000";
when "10" & x"1d3" => DATA <= x"0000";
when "10" & x"1d4" => DATA <= x"0000";
when "10" & x"1d5" => DATA <= x"0000";
when "10" & x"1d6" => DATA <= x"0000";
when "10" & x"1d7" => DATA <= x"0000";
when "10" & x"1d8" => DATA <= x"0000";
when "10" & x"1d9" => DATA <= x"0000";
when "10" & x"1da" => DATA <= x"0000";
when "10" & x"1db" => DATA <= x"0000";
when "10" & x"1dc" => DATA <= x"0000";
when "10" & x"1dd" => DATA <= x"0000";
when "10" & x"1de" => DATA <= x"0000";
when "10" & x"1df" => DATA <= x"0000";
when "10" & x"1e0" => DATA <= x"0000";
when "10" & x"1e1" => DATA <= x"0000";
when "10" & x"1e2" => DATA <= x"0000";
when "10" & x"1e3" => DATA <= x"0000";
when "10" & x"1e4" => DATA <= x"0000";
when "10" & x"1e5" => DATA <= x"0000";
when "10" & x"1e6" => DATA <= x"0000";
when "10" & x"1e7" => DATA <= x"0000";
when "10" & x"1e8" => DATA <= x"0000";
when "10" & x"1e9" => DATA <= x"0000";
when "10" & x"1ea" => DATA <= x"0000";
when "10" & x"1eb" => DATA <= x"0000";
when "10" & x"1ec" => DATA <= x"0000";
when "10" & x"1ed" => DATA <= x"0000";
when "10" & x"1ee" => DATA <= x"0000";
when "10" & x"1ef" => DATA <= x"0000";
when "10" & x"1f0" => DATA <= x"0000";
when "10" & x"1f1" => DATA <= x"0000";
when "10" & x"1f2" => DATA <= x"0000";
when "10" & x"1f3" => DATA <= x"0000";
when "10" & x"1f4" => DATA <= x"0000";
when "10" & x"1f5" => DATA <= x"0000";
when "10" & x"1f6" => DATA <= x"0000";
when "10" & x"1f7" => DATA <= x"0000";
when "10" & x"1f8" => DATA <= x"0000";
when "10" & x"1f9" => DATA <= x"0000";
when "10" & x"1fa" => DATA <= x"0000";
when "10" & x"1fb" => DATA <= x"0000";
when "10" & x"1fc" => DATA <= x"0000";
when "10" & x"1fd" => DATA <= x"0000";
when "10" & x"1fe" => DATA <= x"0000";
when "10" & x"1ff" => DATA <= x"0000";
when "10" & x"200" => DATA <= x"0000";
when "10" & x"201" => DATA <= x"0000";
when "10" & x"202" => DATA <= x"0000";
when "10" & x"203" => DATA <= x"0000";
when "10" & x"204" => DATA <= x"0000";
when "10" & x"205" => DATA <= x"0000";
when "10" & x"206" => DATA <= x"0000";
when "10" & x"207" => DATA <= x"0000";
when "10" & x"208" => DATA <= x"0000";
when "10" & x"209" => DATA <= x"0000";
when "10" & x"20a" => DATA <= x"0000";
when "10" & x"20b" => DATA <= x"0000";
when "10" & x"20c" => DATA <= x"0000";
when "10" & x"20d" => DATA <= x"0000";
when "10" & x"20e" => DATA <= x"0000";
when "10" & x"20f" => DATA <= x"0000";
when "10" & x"210" => DATA <= x"0000";
when "10" & x"211" => DATA <= x"0000";
when "10" & x"212" => DATA <= x"0000";
when "10" & x"213" => DATA <= x"0000";
when "10" & x"214" => DATA <= x"0000";
when "10" & x"215" => DATA <= x"0000";
when "10" & x"216" => DATA <= x"0000";
when "10" & x"217" => DATA <= x"0000";
when "10" & x"218" => DATA <= x"0000";
when "10" & x"219" => DATA <= x"0000";
when "10" & x"21a" => DATA <= x"0000";
when "10" & x"21b" => DATA <= x"0000";
when "10" & x"21c" => DATA <= x"0000";
when "10" & x"21d" => DATA <= x"0000";
when "10" & x"21e" => DATA <= x"0000";
when "10" & x"21f" => DATA <= x"0000";
when "10" & x"220" => DATA <= x"0000";
when "10" & x"221" => DATA <= x"0000";
when "10" & x"222" => DATA <= x"0000";
when "10" & x"223" => DATA <= x"0000";
when "10" & x"224" => DATA <= x"0000";
when "10" & x"225" => DATA <= x"0000";
when "10" & x"226" => DATA <= x"0000";
when "10" & x"227" => DATA <= x"0000";
when "10" & x"228" => DATA <= x"0000";
when "10" & x"229" => DATA <= x"0000";
when "10" & x"22a" => DATA <= x"0000";
when "10" & x"22b" => DATA <= x"0000";
when "10" & x"22c" => DATA <= x"0000";
when "10" & x"22d" => DATA <= x"0000";
when "10" & x"22e" => DATA <= x"0000";
when "10" & x"22f" => DATA <= x"0000";
when "10" & x"230" => DATA <= x"0000";
when "10" & x"231" => DATA <= x"0000";
when "10" & x"232" => DATA <= x"0000";
when "10" & x"233" => DATA <= x"0000";
when "10" & x"234" => DATA <= x"0000";
when "10" & x"235" => DATA <= x"0000";
when "10" & x"236" => DATA <= x"0000";
when "10" & x"237" => DATA <= x"0000";
when "10" & x"238" => DATA <= x"0000";
when "10" & x"239" => DATA <= x"0000";
when "10" & x"23a" => DATA <= x"0000";
when "10" & x"23b" => DATA <= x"0000";
when "10" & x"23c" => DATA <= x"0000";
when "10" & x"23d" => DATA <= x"0000";
when "10" & x"23e" => DATA <= x"0000";
when "10" & x"23f" => DATA <= x"0000";
when "10" & x"240" => DATA <= x"0000";
when "10" & x"241" => DATA <= x"0000";
when "10" & x"242" => DATA <= x"0000";
when "10" & x"243" => DATA <= x"0000";
when "10" & x"244" => DATA <= x"0000";
when "10" & x"245" => DATA <= x"0000";
when "10" & x"246" => DATA <= x"0000";
when "10" & x"247" => DATA <= x"0000";
when "10" & x"248" => DATA <= x"0000";
when "10" & x"249" => DATA <= x"0000";
when "10" & x"24a" => DATA <= x"0000";
when "10" & x"24b" => DATA <= x"0000";
when "10" & x"24c" => DATA <= x"0000";
when "10" & x"24d" => DATA <= x"0000";
when "10" & x"24e" => DATA <= x"0000";
when "10" & x"24f" => DATA <= x"0000";
when "10" & x"250" => DATA <= x"0000";
when "10" & x"251" => DATA <= x"1000";
when "10" & x"252" => DATA <= x"e0e0";
when "10" & x"253" => DATA <= x"e0e0";
when "10" & x"254" => DATA <= x"e0e0";
when "10" & x"255" => DATA <= x"e0e0";
when "10" & x"256" => DATA <= x"80c0";
when "10" & x"257" => DATA <= x"0004";
when "10" & x"258" => DATA <= x"2400";
when "10" & x"259" => DATA <= x"081e";
when "10" & x"25a" => DATA <= x"a00a";
when "10" & x"25b" => DATA <= x"ff74";
when "10" & x"25c" => DATA <= x"5000";
when "10" & x"25d" => DATA <= x"3e80";
when "10" & x"25e" => DATA <= x"1fe0";
when "10" & x"25f" => DATA <= x"6aff";
when "10" & x"260" => DATA <= x"7c20";
when "10" & x"261" => DATA <= x"2801";
when "10" & x"262" => DATA <= x"fe00";
when "10" & x"263" => DATA <= x"6f8b";
when "10" & x"264" => DATA <= x"ebfe";
when "10" & x"265" => DATA <= x"801f";
when "10" & x"266" => DATA <= x"ec00";
when "10" & x"267" => DATA <= x"f980";
when "10" & x"268" => DATA <= x"1e3f";
when "10" & x"269" => DATA <= x"a007";
when "10" & x"26a" => DATA <= x"fb6d";
when "10" & x"26b" => DATA <= x"fce0";
when "10" & x"26c" => DATA <= x"9007";
when "10" & x"26d" => DATA <= x"f802";
when "10" & x"26e" => DATA <= x"bfeb";
when "10" & x"26f" => DATA <= x"e280";
when "10" & x"270" => DATA <= x"1fe0";
when "10" & x"271" => DATA <= x"07f8";
when "10" & x"272" => DATA <= x"1cbe";
when "10" & x"273" => DATA <= x"ffa0";
when "10" & x"274" => DATA <= x"07fb";
when "10" & x"275" => DATA <= x"81fe";
when "10" & x"276" => DATA <= x"ac00";
when "10" & x"277" => DATA <= x"27e8";
when "10" & x"278" => DATA <= x"03bf";
when "10" & x"279" => DATA <= x"de35";
when "10" & x"27a" => DATA <= x"8140";
when "10" & x"27b" => DATA <= x"17ff";
when "10" & x"27c" => DATA <= x"400f";
when "10" & x"27d" => DATA <= x"f014";
when "10" & x"27e" => DATA <= x"ffd0";
when "10" & x"27f" => DATA <= x"03fd";
when "10" & x"280" => DATA <= x"e0ff";
when "10" & x"281" => DATA <= x"7800";
when "10" & x"282" => DATA <= x"c1f4";
when "10" & x"283" => DATA <= x"00ff";
when "10" & x"284" => DATA <= x"00bf";
when "10" & x"285" => DATA <= x"d408";
when "10" & x"286" => DATA <= x"071d";
when "10" & x"287" => DATA <= x"005f";
when "10" & x"288" => DATA <= x"fd00";
when "10" & x"289" => DATA <= x"3fd7";
when "10" & x"28a" => DATA <= x"f3ff";
when "10" & x"28b" => DATA <= x"400f";
when "10" & x"28c" => DATA <= x"f7d4";
when "10" & x"28d" => DATA <= x"ffd0";
when "10" & x"28e" => DATA <= x"03fc";
when "10" & x"28f" => DATA <= x"00ff";
when "10" & x"290" => DATA <= x"080c";
when "10" & x"291" => DATA <= x"c474";
when "10" & x"292" => DATA <= x"00ff";
when "10" & x"293" => DATA <= x"403f";
when "10" & x"294" => DATA <= x"df8f";
when "10" & x"295" => DATA <= x"f7f5";
when "10" & x"296" => DATA <= x"003f";
when "10" & x"297" => DATA <= x"dfd3";
when "10" & x"298" => DATA <= x"ff40";
when "10" & x"299" => DATA <= x"0ff7";
when "10" & x"29a" => DATA <= x"ecff";
when "10" & x"29b" => DATA <= x"d003";
when "10" & x"29c" => DATA <= x"fc00";
when "10" & x"29d" => DATA <= x"ff20";
when "10" & x"29e" => DATA <= x"bbd9";
when "10" & x"29f" => DATA <= x"f400";
when "10" & x"2a0" => DATA <= x"ff00";
when "10" & x"2a1" => DATA <= x"3fde";
when "10" & x"2a2" => DATA <= x"0fe7";
when "10" & x"2a3" => DATA <= x"e500";
when "10" & x"2a4" => DATA <= x"5ffd";
when "10" & x"2a5" => DATA <= x"003f";
when "10" & x"2a6" => DATA <= x"cff3";
when "10" & x"2a7" => DATA <= x"ff40";
when "10" & x"2a8" => DATA <= x"0ff0";
when "10" & x"2a9" => DATA <= x"03fc";
when "10" & x"2aa" => DATA <= x"82e7";
when "10" & x"2ab" => DATA <= x"23d0";
when "10" & x"2ac" => DATA <= x"03fc";
when "10" & x"2ad" => DATA <= x"00ff";
when "10" & x"2ae" => DATA <= x"7057";
when "10" & x"2af" => DATA <= x"e500";
when "10" & x"2b0" => DATA <= x"3fdf";
when "10" & x"2b1" => DATA <= x"13ff";
when "10" & x"2b2" => DATA <= x"4017";
when "10" & x"2b3" => DATA <= x"ff40";
when "10" & x"2b4" => DATA <= x"0ff0";
when "10" & x"2b5" => DATA <= x"3bfc";
when "10" & x"2b6" => DATA <= x"7eff";
when "10" & x"2b7" => DATA <= x"3fd0";
when "10" & x"2b8" => DATA <= x"03fc";
when "10" & x"2b9" => DATA <= x"00ff";
when "10" & x"2ba" => DATA <= x"0033";
when "10" & x"2bb" => DATA <= x"9814";
when "10" & x"2bc" => DATA <= x"00ff";
when "10" & x"2bd" => DATA <= x"003f";
when "10" & x"2be" => DATA <= x"df95";
when "10" & x"2bf" => DATA <= x"ff40";
when "10" & x"2c0" => DATA <= x"0ff7";
when "10" & x"2c1" => DATA <= x"f4ff";
when "10" & x"2c2" => DATA <= x"d005";
when "10" & x"2c3" => DATA <= x"ffd0";
when "10" & x"2c4" => DATA <= x"05ff";
when "10" & x"2c5" => DATA <= x"d005";
when "10" & x"2c6" => DATA <= x"ffd0";
when "10" & x"2c7" => DATA <= x"05ff";
when "10" & x"2c8" => DATA <= x"d005";
when "10" & x"2c9" => DATA <= x"ffd0";
when "10" & x"2ca" => DATA <= x"077f";
when "10" & x"2cb" => DATA <= x"d3f8";
when "10" & x"2cc" => DATA <= x"fe80";
when "10" & x"2cd" => DATA <= x"27fd";
when "10" & x"2ce" => DATA <= x"9ce0";
when "10" & x"2cf" => DATA <= x"a00b";
when "10" & x"2d0" => DATA <= x"ffa0";
when "10" & x"2d1" => DATA <= x"0eff";
when "10" & x"2d2" => DATA <= x"3fa7";
when "10" & x"2d3" => DATA <= x"c1f4";
when "10" & x"2d4" => DATA <= x"013f";
when "10" & x"2d5" => DATA <= x"efb7";
when "10" & x"2d6" => DATA <= x"cd00";
when "10" & x"2d7" => DATA <= x"6ff9";
when "10" & x"2d8" => DATA <= x"7e80";
when "10" & x"2d9" => DATA <= x"37fd";
when "10" & x"2da" => DATA <= x"ed40";
when "10" & x"2db" => DATA <= x"1bfe";
when "10" & x"2dc" => DATA <= x"17a0";
when "10" & x"2dd" => DATA <= x"0dff";
when "10" & x"2de" => DATA <= x"7ed0";
when "10" & x"2df" => DATA <= x"06ff";
when "10" & x"2e0" => DATA <= x"9fe8";
when "10" & x"2e1" => DATA <= x"037f";
when "10" & x"2e2" => DATA <= x"f803";
when "10" & x"2e3" => DATA <= x"bfdf";
when "10" & x"2e4" => DATA <= x"ad84";
when "10" & x"2e5" => DATA <= x"0500";
when "10" & x"2e6" => DATA <= x"4ffb";
when "10" & x"2e7" => DATA <= x"01bb";
when "10" & x"2e8" => DATA <= x"400f";
when "10" & x"2e9" => DATA <= x"f3fc";
when "10" & x"2ea" => DATA <= x"ffd0";
when "10" & x"2eb" => DATA <= x"03fc";
when "10" & x"2ec" => DATA <= x"ffdf";
when "10" & x"2ed" => DATA <= x"e2fa";
when "10" & x"2ee" => DATA <= x"007f";
when "10" & x"2ef" => DATA <= x"801f";
when "10" & x"2f0" => DATA <= x"e417";
when "10" & x"2f1" => DATA <= x"3f00";
when "10" & x"2f2" => DATA <= x"3fc0";
when "10" & x"2f3" => DATA <= x"0ff6";
when "10" & x"2f4" => DATA <= x"03f9";
when "10" & x"2f5" => DATA <= x"f140";
when "10" & x"2f6" => DATA <= x"17ff";
when "10" & x"2f7" => DATA <= x"400f";
when "10" & x"2f8" => DATA <= x"f6fc";
when "10" & x"2f9" => DATA <= x"ffd0";
when "10" & x"2fa" => DATA <= x"03fc";
when "10" & x"2fb" => DATA <= x"3fdf";
when "10" & x"2fc" => DATA <= x"e7fa";
when "10" & x"2fd" => DATA <= x"007f";
when "10" & x"2fe" => DATA <= x"a01f";
when "10" & x"2ff" => DATA <= x"e876";
when "10" & x"300" => DATA <= x"ff00";
when "10" & x"301" => DATA <= x"3fc0";
when "10" & x"302" => DATA <= x"eff7";
when "10" & x"303" => DATA <= x"5bfd";
when "10" & x"304" => DATA <= x"c140";
when "10" & x"305" => DATA <= x"0ff7";
when "10" & x"306" => DATA <= x"44ff";
when "10" & x"307" => DATA <= x"d003";
when "10" & x"308" => DATA <= x"fc00";
when "10" & x"309" => DATA <= x"ff1f";
when "10" & x"30a" => DATA <= x"bfc7";
when "10" & x"30b" => DATA <= x"f400";
when "10" & x"30c" => DATA <= x"ff40";
when "10" & x"30d" => DATA <= x"3fc9";
when "10" & x"30e" => DATA <= x"0ec7";
when "10" & x"30f" => DATA <= x"2500";
when "10" & x"310" => DATA <= x"3fc0";
when "10" & x"311" => DATA <= x"f3ff";
when "10" & x"312" => DATA <= x"400f";
when "10" & x"313" => DATA <= x"f5ac";
when "10" & x"314" => DATA <= x"ffd0";
when "10" & x"315" => DATA <= x"03fc";
when "10" & x"316" => DATA <= x"02ff";
when "10" & x"317" => DATA <= x"03b7";
when "10" & x"318" => DATA <= x"cc74";
when "10" & x"319" => DATA <= x"00ff";
when "10" & x"31a" => DATA <= x"603f";
when "10" & x"31b" => DATA <= x"d82f";
when "10" & x"31c" => DATA <= x"f6e5";
when "10" & x"31d" => DATA <= x"003f";
when "10" & x"31e" => DATA <= x"c06f";
when "10" & x"31f" => DATA <= x"f7dd";
when "10" & x"320" => DATA <= x"7fd0";
when "10" & x"321" => DATA <= x"03fd";
when "10" & x"322" => DATA <= x"f93f";
when "10" & x"323" => DATA <= x"f400";
when "10" & x"324" => DATA <= x"ff1f";
when "10" & x"325" => DATA <= x"bfe8";
when "10" & x"326" => DATA <= x"3c0f";
when "10" & x"327" => DATA <= x"400f";
when "10" & x"328" => DATA <= x"f503";
when "10" & x"329" => DATA <= x"fd10";
when "10" & x"32a" => DATA <= x"d778";
when "10" & x"32b" => DATA <= x"5003";
when "10" & x"32c" => DATA <= x"fc06";
when "10" & x"32d" => DATA <= x"ff7d";
when "10" & x"32e" => DATA <= x"d7fd";
when "10" & x"32f" => DATA <= x"003f";
when "10" & x"330" => DATA <= x"dc13";
when "10" & x"331" => DATA <= x"ff40";
when "10" & x"332" => DATA <= x"0ff1";
when "10" & x"333" => DATA <= x"fbfc";
when "10" & x"334" => DATA <= x"1e07";
when "10" & x"335" => DATA <= x"e007";
when "10" & x"336" => DATA <= x"f8c1";
when "10" & x"337" => DATA <= x"8610";
when "10" & x"338" => DATA <= x"00bc";
when "10" & x"339" => DATA <= x"2801";
when "10" & x"33a" => DATA <= x"fe00";
when "10" & x"33b" => DATA <= x"78bc";
when "10" & x"33c" => DATA <= x"2bfe";
when "10" & x"33d" => DATA <= x"801f";
when "10" & x"33e" => DATA <= x"af0e";
when "10" & x"33f" => DATA <= x"ff3f";
when "10" & x"340" => DATA <= x"d007";
when "10" & x"341" => DATA <= x"7f97";
when "10" & x"342" => DATA <= x"c07c";
when "10" & x"343" => DATA <= x"00ff";
when "10" & x"344" => DATA <= x"1fa0";
when "10" & x"345" => DATA <= x"c20c";
when "10" & x"346" => DATA <= x"07a5";
when "10" & x"347" => DATA <= x"0000";
when "10" & x"348" => DATA <= x"4000";
when "10" & x"349" => DATA <= x"1205";
when "10" & x"34a" => DATA <= x"3887";
when "10" & x"34b" => DATA <= x"8381";
when "10" & x"34c" => DATA <= x"e0e0";
when "10" & x"34d" => DATA <= x"7839";
when "10" & x"34e" => DATA <= x"43db";
when "10" & x"34f" => DATA <= x"df5f";
when "10" & x"350" => DATA <= x"eef0";
when "10" & x"351" => DATA <= x"051f";
when "10" & x"352" => DATA <= x"0fc7";
when "10" & x"353" => DATA <= x"d47e";
when "10" & x"354" => DATA <= x"3e78";
when "10" & x"355" => DATA <= x"3000";
when "10" & x"356" => DATA <= x"0181";
when "10" & x"357" => DATA <= x"c57c";
when "10" & x"358" => DATA <= x"5000";
when "10" & x"359" => DATA <= x"0dfc";
when "10" & x"35a" => DATA <= x"f060";
when "10" & x"35b" => DATA <= x"20df";
when "10" & x"35c" => DATA <= x"f401";
when "10" & x"35d" => DATA <= x"c61d";
when "10" & x"35e" => DATA <= x"6090";
when "10" & x"35f" => DATA <= x"6020";
when "10" & x"360" => DATA <= x"0003";
when "10" & x"361" => DATA <= x"0385";
when "10" & x"362" => DATA <= x"7800";
when "10" & x"363" => DATA <= x"0020";
when "10" & x"364" => DATA <= x"77e3";
when "10" & x"365" => DATA <= x"8100";
when "10" & x"366" => DATA <= x"8107";
when "10" & x"367" => DATA <= x"8008";
when "10" & x"368" => DATA <= x"0607";
when "10" & x"369" => DATA <= x"0cb0";
when "10" & x"36a" => DATA <= x"8838";
when "10" & x"36b" => DATA <= x"00c1";
when "10" & x"36c" => DATA <= x"dc00";
when "10" & x"36d" => DATA <= x"0010";
when "10" & x"36e" => DATA <= x"39f0";
when "10" & x"36f" => DATA <= x"c040";
when "10" & x"370" => DATA <= x"00c1";
when "10" & x"371" => DATA <= x"e00a";
when "10" & x"372" => DATA <= x"c09c";
when "10" & x"373" => DATA <= x"341f";
when "10" & x"374" => DATA <= x"0030";
when "10" & x"375" => DATA <= x"502c";
when "10" & x"376" => DATA <= x"0403";
when "10" & x"377" => DATA <= x"0380";
when "10" & x"378" => DATA <= x"1820";
when "10" & x"379" => DATA <= x"3038";
when "10" & x"37a" => DATA <= x"3c7f";
when "10" & x"37b" => DATA <= x"c014";
when "10" & x"37c" => DATA <= x"1e0e";
when "10" & x"37d" => DATA <= x"a0c0";
when "10" & x"37e" => DATA <= x"073f";
when "10" & x"37f" => DATA <= x"90f8";
when "10" & x"380" => DATA <= x"4c22";
when "10" & x"381" => DATA <= x"f500";
when "10" & x"382" => DATA <= x"5080";
when "10" & x"383" => DATA <= x"02b8";
when "10" & x"384" => DATA <= x"1e00";
when "10" & x"385" => DATA <= x"7000";
when "10" & x"386" => DATA <= x"7c1e";
when "10" & x"387" => DATA <= x"1f1f";
when "10" & x"388" => DATA <= x"9fc3";
when "10" & x"389" => DATA <= x"fdfc";
when "10" & x"38a" => DATA <= x"fca3";
when "10" & x"38b" => DATA <= x"81e0";
when "10" & x"38c" => DATA <= x"01fe";
when "10" & x"38d" => DATA <= x"2b41";
when "10" & x"38e" => DATA <= x"80fa";
when "10" & x"38f" => DATA <= x"0004";
when "10" & x"390" => DATA <= x"ff50";
when "10" & x"391" => DATA <= x"0428";
when "10" & x"392" => DATA <= x"0021";
when "10" & x"393" => DATA <= x"4000";
when "10" & x"394" => DATA <= x"707f";
when "10" & x"395" => DATA <= x"0f87";
when "10" & x"396" => DATA <= x"87e8";
when "10" & x"397" => DATA <= x"07e0";
when "10" & x"398" => DATA <= x"028f";
when "10" & x"399" => DATA <= x"28e0";
when "10" & x"39a" => DATA <= x"78ff";
when "10" & x"39b" => DATA <= x"7ef6";
when "10" & x"39c" => DATA <= x"0309";
when "10" & x"39d" => DATA <= x"00c0";
when "10" & x"39e" => DATA <= x"21d0";
when "10" & x"39f" => DATA <= x"0ef0";
when "10" & x"3a0" => DATA <= x"8068";
when "10" & x"3a1" => DATA <= x"000e";
when "10" & x"3a2" => DATA <= x"83a8";
when "10" & x"3a3" => DATA <= x"1618";
when "10" & x"3a4" => DATA <= x"0180";
when "10" & x"3a5" => DATA <= x"c163";
when "10" & x"3a6" => DATA <= x"d43a";
when "10" & x"3a7" => DATA <= x"7dfe";
when "10" & x"3a8" => DATA <= x"00ef";
when "10" & x"3a9" => DATA <= x"f5a5";
when "10" & x"3aa" => DATA <= x"4a00";
when "10" & x"3ab" => DATA <= x"0edc";
when "10" & x"3ac" => DATA <= x"1e07";
when "10" & x"3ad" => DATA <= x"0257";
when "10" & x"3ae" => DATA <= x"2804";
when "10" & x"3af" => DATA <= x"3c3e";
when "10" & x"3b0" => DATA <= x"1f87";
when "10" & x"3b1" => DATA <= x"f83f";
when "10" & x"3b2" => DATA <= x"8038";
when "10" & x"3b3" => DATA <= x"603c";
when "10" & x"3b4" => DATA <= x"1f00";
when "10" & x"3b5" => DATA <= x"7830";
when "10" & x"3b6" => DATA <= x"0820";
when "10" & x"3b7" => DATA <= x"7eaf";
when "10" & x"3b8" => DATA <= x"e3f5";
when "10" & x"3b9" => DATA <= x"7f70";
when "10" & x"3ba" => DATA <= x"057f";
when "10" & x"3bb" => DATA <= x"f1f8";
when "10" & x"3bc" => DATA <= x"02bf";
when "10" & x"3bd" => DATA <= x"1faf";
when "10" & x"3be" => DATA <= x"f005";
when "10" & x"3bf" => DATA <= x"0400";
when "10" & x"3c0" => DATA <= x"2bfd";
when "10" & x"3c1" => DATA <= x"ee37";
when "10" & x"3c2" => DATA <= x"1408";
when "10" & x"3c3" => DATA <= x"4041";
when "10" & x"3c4" => DATA <= x"0aff";
when "10" & x"3c5" => DATA <= x"7f00";
when "10" & x"3c6" => DATA <= x"40a9";
when "10" & x"3c7" => DATA <= x"9038";
when "10" & x"3c8" => DATA <= x"21fe";
when "10" & x"3c9" => DATA <= x"3f0f";
when "10" & x"3ca" => DATA <= x"f008";
when "10" & x"3cb" => DATA <= x"1444";
when "10" & x"3cc" => DATA <= x"3fa3";
when "10" & x"3cd" => DATA <= x"e0f0";
when "10" & x"3ce" => DATA <= x"3a83";
when "10" & x"3cf" => DATA <= x"000e";
when "10" & x"3d0" => DATA <= x"0381";
when "10" & x"3d1" => DATA <= x"e1f8";
when "10" & x"3d2" => DATA <= x"f87e";
when "10" & x"3d3" => DATA <= x"1f80";
when "10" & x"3d4" => DATA <= x"0ffa";
when "10" & x"3d5" => DATA <= x"00ef";
when "10" & x"3d6" => DATA <= x"fa00";
when "10" & x"3d7" => DATA <= x"e1f0";
when "10" & x"3d8" => DATA <= x"7f03";
when "10" & x"3d9" => DATA <= x"801e";
when "10" & x"3da" => DATA <= x"0180";
when "10" & x"3db" => DATA <= x"e70f";
when "10" & x"3dc" => DATA <= x"07c0";
when "10" & x"3dd" => DATA <= x"07fb";
when "10" & x"3de" => DATA <= x"0030";
when "10" & x"3df" => DATA <= x"2da8";
when "10" & x"3e0" => DATA <= x"c340";
when "10" & x"3e1" => DATA <= x"02b4";
when "10" & x"3e2" => DATA <= x"0806";
when "10" & x"3e3" => DATA <= x"9007";
when "10" & x"3e4" => DATA <= x"ef00";
when "10" & x"3e5" => DATA <= x"0400";
when "10" & x"3e6" => DATA <= x"9400";
when "10" & x"3e7" => DATA <= x"bfb0";
when "10" & x"3e8" => DATA <= x"0008";
when "10" & x"3e9" => DATA <= x"fde0";
when "10" & x"3ea" => DATA <= x"f83c";
when "10" & x"3eb" => DATA <= x"71c7";
when "10" & x"3ec" => DATA <= x"0077";
when "10" & x"3ed" => DATA <= x"03c1";
when "10" & x"3ee" => DATA <= x"f200";
when "10" & x"3ef" => DATA <= x"2058";
when "10" & x"3f0" => DATA <= x"8001";
when "10" & x"3f1" => DATA <= x"faf8";
when "10" & x"3f2" => DATA <= x"4870";
when "10" & x"3f3" => DATA <= x"0004";
when "10" & x"3f4" => DATA <= x"00f7";
when "10" & x"3f5" => DATA <= x"0057";
when "10" & x"3f6" => DATA <= x"8538";
when "10" & x"3f7" => DATA <= x"0c0e";
when "10" & x"3f8" => DATA <= x"1406";
when "10" & x"3f9" => DATA <= x"c160";
when "10" & x"3fa" => DATA <= x"5703";
when "10" & x"3fb" => DATA <= x"e5f8";
when "10" & x"3fc" => DATA <= x"fa70";
when "10" & x"3fd" => DATA <= x"5f1b";
when "10" & x"3fe" => DATA <= x"ff7c";
when "10" & x"3ff" => DATA <= x"deef";
when "10" & x"400" => DATA <= x"37ff";
when "10" & x"401" => DATA <= x"bfb7";
when "10" & x"402" => DATA <= x"c013";
when "10" & x"403" => DATA <= x"0150";
when "10" & x"404" => DATA <= x"4070";
when "10" & x"405" => DATA <= x"407c";
when "10" & x"406" => DATA <= x"1f40";
when "10" & x"407" => DATA <= x"e0f5";
when "10" & x"408" => DATA <= x"fb20";
when "10" & x"409" => DATA <= x"0141";
when "10" & x"40a" => DATA <= x"c0c0";
when "10" & x"40b" => DATA <= x"7707";
when "10" & x"40c" => DATA <= x"f800";
when "10" & x"40d" => DATA <= x"4060";
when "10" & x"40e" => DATA <= x"3f0f";
when "10" & x"40f" => DATA <= x"d07a";
when "10" & x"410" => DATA <= x"1f80";
when "10" & x"411" => DATA <= x"0314";
when "10" & x"412" => DATA <= x"381e";
when "10" & x"413" => DATA <= x"0f80";
when "10" & x"414" => DATA <= x"3c18";
when "10" & x"415" => DATA <= x"04a0";
when "10" & x"416" => DATA <= x"703f";
when "10" & x"417" => DATA <= x"87c1";
when "10" & x"418" => DATA <= x"e070";
when "10" & x"419" => DATA <= x"1a80";
when "10" & x"41a" => DATA <= x"0022";
when "10" & x"41b" => DATA <= x"0380";
when "10" & x"41c" => DATA <= x"e078";
when "10" & x"41d" => DATA <= x"3f00";
when "10" & x"41e" => DATA <= x"2228";
when "10" & x"41f" => DATA <= x"6018";
when "10" & x"420" => DATA <= x"1c04";
when "10" & x"421" => DATA <= x"0602";
when "10" & x"422" => DATA <= x"0fd0";
when "10" & x"423" => DATA <= x"1389";
when "10" & x"424" => DATA <= x"c0e2";
when "10" & x"425" => DATA <= x"7038";
when "10" & x"426" => DATA <= x"9fcf";
when "10" & x"427" => DATA <= x"f3c0";
when "10" & x"428" => DATA <= x"fc0e";
when "10" & x"429" => DATA <= x"0140";
when "10" & x"42a" => DATA <= x"b801";
when "10" & x"42b" => DATA <= x"a01a";
when "10" & x"42c" => DATA <= x"0003";
when "10" & x"42d" => DATA <= x"01c8";
when "10" & x"42e" => DATA <= x"e070";
when "10" & x"42f" => DATA <= x"0010";
when "10" & x"430" => DATA <= x"0084";
when "10" & x"431" => DATA <= x"a804";
when "10" & x"432" => DATA <= x"2200";
when "10" & x"433" => DATA <= x"000f";
when "10" & x"434" => DATA <= x"1fbf";
when "10" & x"435" => DATA <= x"c3e0";
when "10" & x"436" => DATA <= x"701b";
when "10" & x"437" => DATA <= x"8640";
when "10" & x"438" => DATA <= x"0100";
when "10" & x"439" => DATA <= x"ca0f";
when "10" & x"43a" => DATA <= x"e004";
when "10" & x"43b" => DATA <= x"1d01";
when "10" & x"43c" => DATA <= x"a0c0";
when "10" & x"43d" => DATA <= x"601a";
when "10" & x"43e" => DATA <= x"ffaf";
when "10" & x"43f" => DATA <= x"81c0";
when "10" & x"440" => DATA <= x"6110";
when "10" & x"441" => DATA <= x"007f";
when "10" & x"442" => DATA <= x"80c1";
when "10" & x"443" => DATA <= x"e006";
when "10" & x"444" => DATA <= x"03c1";
when "10" & x"445" => DATA <= x"fefe";
when "10" & x"446" => DATA <= x"03d0";
when "10" & x"447" => DATA <= x"0480";
when "10" & x"448" => DATA <= x"9fd8";
when "10" & x"449" => DATA <= x"0de9";
when "10" & x"44a" => DATA <= x"dfaf";
when "10" & x"44b" => DATA <= x"fbf7";
when "10" & x"44c" => DATA <= x"afff";
when "10" & x"44d" => DATA <= x"7138";
when "10" & x"44e" => DATA <= x"87a8";
when "10" & x"44f" => DATA <= x"703c";
when "10" & x"450" => DATA <= x"1ca0";
when "10" & x"451" => DATA <= x"0026";
when "10" & x"452" => DATA <= x"f7bb";
when "10" & x"453" => DATA <= x"8000";
when "10" & x"454" => DATA <= x"74f5";
when "10" & x"455" => DATA <= x"5d2f";
when "10" & x"456" => DATA <= x"9fc1";
when "10" & x"457" => DATA <= x"ea00";
when "10" & x"458" => DATA <= x"2857";
when "10" & x"459" => DATA <= x"fbed";
when "10" & x"45a" => DATA <= x"fe00";
when "10" & x"45b" => DATA <= x"7e50";
when "10" & x"45c" => DATA <= x"02fc";
when "10" & x"45d" => DATA <= x"fcff";
when "10" & x"45e" => DATA <= x"6780";
when "10" & x"45f" => DATA <= x"0fef";
when "10" & x"460" => DATA <= x"f48f";
when "10" & x"461" => DATA <= x"7fbd";
when "10" & x"462" => DATA <= x"1e0e";
when "10" & x"463" => DATA <= x"0780";
when "10" & x"464" => DATA <= x"03bf";
when "10" & x"465" => DATA <= x"c7e7";
when "10" & x"466" => DATA <= x"f3e8";
when "10" & x"467" => DATA <= x"fc04";
when "10" & x"468" => DATA <= x"ff7e";
when "10" & x"469" => DATA <= x"bfd0";
when "10" & x"46a" => DATA <= x"8637";
when "10" & x"46b" => DATA <= x"9a40";
when "10" & x"46c" => DATA <= x"415f";
when "10" & x"46d" => DATA <= x"d47e";
when "10" & x"46e" => DATA <= x"0203";
when "10" & x"46f" => DATA <= x"a218";
when "10" & x"470" => DATA <= x"35fe";
when "10" & x"471" => DATA <= x"fe4f";
when "10" & x"472" => DATA <= x"1000";
when "10" & x"473" => DATA <= x"0040";
when "10" & x"474" => DATA <= x"2afd";
when "10" & x"475" => DATA <= x"feef";
when "10" & x"476" => DATA <= x"1d80";
when "10" & x"477" => DATA <= x"a800";
when "10" & x"478" => DATA <= x"c15f";
when "10" & x"479" => DATA <= x"aff7";
when "10" & x"47a" => DATA <= x"f235";
when "10" & x"47b" => DATA <= x"98c4";
when "10" & x"47c" => DATA <= x"0157";
when "10" & x"47d" => DATA <= x"fafd";
when "10" & x"47e" => DATA <= x"fe14";
when "10" & x"47f" => DATA <= x"0008";
when "10" & x"480" => DATA <= x"0167";
when "10" & x"481" => DATA <= x"f77a";
when "10" & x"482" => DATA <= x"fc66";
when "10" & x"483" => DATA <= x"0024";
when "10" & x"484" => DATA <= x"1018";
when "10" & x"485" => DATA <= x"0fb7";
when "10" & x"486" => DATA <= x"bbfd";
when "10" & x"487" => DATA <= x"f800";
when "10" & x"488" => DATA <= x"45b2";
when "10" & x"489" => DATA <= x"c21d";
when "10" & x"48a" => DATA <= x"fe8f";
when "10" & x"48b" => DATA <= x"4000";
when "10" & x"48c" => DATA <= x"1000";
when "10" & x"48d" => DATA <= x"077d";
when "10" & x"48e" => DATA <= x"7fa9";
when "10" & x"48f" => DATA <= x"c0e0";
when "10" & x"490" => DATA <= x"0020";
when "10" & x"491" => DATA <= x"03bf";
when "10" & x"492" => DATA <= x"dee0";
when "10" & x"493" => DATA <= x"4000";
when "10" & x"494" => DATA <= x"9009";
when "10" & x"495" => DATA <= x"3fe0";
when "10" & x"496" => DATA <= x"0641";
when "10" & x"497" => DATA <= x"0d00";
when "10" & x"498" => DATA <= x"ff77";
when "10" & x"499" => DATA <= x"bfcf";
when "10" & x"49a" => DATA <= x"e000";
when "10" & x"49b" => DATA <= x"1098";
when "10" & x"49c" => DATA <= x"00ef";
when "10" & x"49d" => DATA <= x"aff7";
when "10" & x"49e" => DATA <= x"0000";
when "10" & x"49f" => DATA <= x"0844";
when "10" & x"4a0" => DATA <= x"003f";
when "10" & x"4a1" => DATA <= x"5eaf";
when "10" & x"4a2" => DATA <= x"d7fb";
when "10" & x"4a3" => DATA <= x"0000";
when "10" & x"4a4" => DATA <= x"0a02";
when "10" & x"4a5" => DATA <= x"77fb";
when "10" & x"4a6" => DATA <= x"e480";
when "10" & x"4a7" => DATA <= x"0700";
when "10" & x"4a8" => DATA <= x"007b";
when "10" & x"4a9" => DATA <= x"fd02";
when "10" & x"4aa" => DATA <= x"4800";
when "10" & x"4ab" => DATA <= x"1202";
when "10" & x"4ac" => DATA <= x"6bf6";
when "10" & x"4ad" => DATA <= x"fbfc";
when "10" & x"4ae" => DATA <= x"661a";
when "10" & x"4af" => DATA <= x"a007";
when "10" & x"4b0" => DATA <= x"03f5";
when "10" & x"4b1" => DATA <= x"deff";
when "10" & x"4b2" => DATA <= x"7d00";
when "10" & x"4b3" => DATA <= x"0482";
when "10" & x"4b4" => DATA <= x"1211";
when "10" & x"4b5" => DATA <= x"bebf";
when "10" & x"4b6" => DATA <= x"c720";
when "10" & x"4b7" => DATA <= x"0009";
when "10" & x"4b8" => DATA <= x"4408";
when "10" & x"4b9" => DATA <= x"ff33";
when "10" & x"4ba" => DATA <= x"3ff8";
when "10" & x"4bb" => DATA <= x"0124";
when "10" & x"4bc" => DATA <= x"88ef";
when "10" & x"4bd" => DATA <= x"f03d";
when "10" & x"4be" => DATA <= x"0001";
when "10" & x"4bf" => DATA <= x"03fd";
when "10" & x"4c0" => DATA <= x"fe5e";
when "10" & x"4c1" => DATA <= x"603f";
when "10" & x"4c2" => DATA <= x"00ca";
when "10" & x"4c3" => DATA <= x"07fb";
when "10" & x"4c4" => DATA <= x"bdfe";
when "10" & x"4c5" => DATA <= x"f079";
when "10" & x"4c6" => DATA <= x"bfc1";
when "10" & x"4c7" => DATA <= x"2f9e";
when "10" & x"4c8" => DATA <= x"ff04";
when "10" & x"4c9" => DATA <= x"805f";
when "10" & x"4ca" => DATA <= x"e009";
when "10" & x"4cb" => DATA <= x"ff00";
when "10" & x"4cc" => DATA <= x"3f2f";
when "10" & x"4cd" => DATA <= x"fc00";
when "10" & x"4ce" => DATA <= x"0f7f";
when "10" & x"4cf" => DATA <= x"a067";
when "10" & x"4d0" => DATA <= x"fc00";
when "10" & x"4d1" => DATA <= x"fc7f";
when "10" & x"4d2" => DATA <= x"80e7";
when "10" & x"4d3" => DATA <= x"fc01";
when "10" & x"4d4" => DATA <= x"5fe0";
when "10" & x"4d5" => DATA <= x"02a7";
when "10" & x"4d6" => DATA <= x"7f80";
when "10" & x"4d7" => DATA <= x"2bfc";
when "10" & x"4d8" => DATA <= x"24ed";
when "10" & x"4d9" => DATA <= x"eff7";
when "10" & x"4da" => DATA <= x"01f9";
when "10" & x"4db" => DATA <= x"fe00";
when "10" & x"4dc" => DATA <= x"dff7";
when "10" & x"4dd" => DATA <= x"e3fd";
when "10" & x"4de" => DATA <= x"fdbf";
when "10" & x"4df" => DATA <= x"ef17";
when "10" & x"4e0" => DATA <= x"f807";
when "10" & x"4e1" => DATA <= x"7fde";
when "10" & x"4e2" => DATA <= x"eff0";
when "10" & x"4e3" => DATA <= x"3cff";
when "10" & x"4e4" => DATA <= x"a5df";
when "10" & x"4e5" => DATA <= x"c4f2";
when "10" & x"4e6" => DATA <= x"023f";
when "10" & x"4e7" => DATA <= x"bfdd";
when "10" & x"4e8" => DATA <= x"e000";
when "10" & x"4e9" => DATA <= x"3281";
when "10" & x"4ea" => DATA <= x"31df";
when "10" & x"4eb" => DATA <= x"e087";
when "10" & x"4ec" => DATA <= x"0200";
when "10" & x"4ed" => DATA <= x"0a80";
when "10" & x"4ee" => DATA <= x"eff4";
when "10" & x"4ef" => DATA <= x"c3fd";
when "10" & x"4f0" => DATA <= x"1e09";
when "10" & x"4f1" => DATA <= x"20f7";
when "10" & x"4f2" => DATA <= x"f801";
when "10" & x"4f3" => DATA <= x"fe6d";
when "10" & x"4f4" => DATA <= x"1220";
when "10" & x"4f5" => DATA <= x"3bfc";
when "10" & x"4f6" => DATA <= x"007f";
when "10" & x"4f7" => DATA <= x"0005";
when "10" & x"4f8" => DATA <= x"166d";
when "10" & x"4f9" => DATA <= x"b7eb";
when "10" & x"4fa" => DATA <= x"fc00";
when "10" & x"4fb" => DATA <= x"f878";
when "10" & x"4fc" => DATA <= x"1027";
when "10" & x"4fd" => DATA <= x"fde0";
when "10" & x"4fe" => DATA <= x"ff28";
when "10" & x"4ff" => DATA <= x"9827";
when "10" & x"500" => DATA <= x"fc38";
when "10" & x"501" => DATA <= x"df77";
when "10" & x"502" => DATA <= x"8413";
when "10" & x"503" => DATA <= x"e6fa";
when "10" & x"504" => DATA <= x"ff00";
when "10" & x"505" => DATA <= x"d7fb";
when "10" & x"506" => DATA <= x"ac01";
when "10" & x"507" => DATA <= x"dfe0";
when "10" & x"508" => DATA <= x"03fb";
when "10" & x"509" => DATA <= x"fc42";
when "10" & x"50a" => DATA <= x"f0ef";
when "10" & x"50b" => DATA <= x"f005";
when "10" & x"50c" => DATA <= x"7f80";
when "10" & x"50d" => DATA <= x"67fc";
when "10" & x"50e" => DATA <= x"000f";
when "10" & x"50f" => DATA <= x"7780";
when "10" & x"510" => DATA <= x"2b8c";
when "10" & x"511" => DATA <= x"c6e3";
when "10" & x"512" => DATA <= x"7628";
when "10" & x"513" => DATA <= x"07e4";
when "10" & x"514" => DATA <= x"0793";
when "10" & x"515" => DATA <= x"e5e3";
when "10" & x"516" => DATA <= x"5f8f";
when "10" & x"517" => DATA <= x"f703";
when "10" & x"518" => DATA <= x"fedf";
when "10" & x"519" => DATA <= x"dfe7";
when "10" & x"51a" => DATA <= x"f432";
when "10" & x"51b" => DATA <= x"2aa7";
when "10" & x"51c" => DATA <= x"9ed5";
when "10" & x"51d" => DATA <= x"fe40";
when "10" & x"51e" => DATA <= x"fff0";
when "10" & x"51f" => DATA <= x"05ff";
when "10" & x"520" => DATA <= x"bb40";
when "10" & x"521" => DATA <= x"085e";
when "10" & x"522" => DATA <= x"ff16";
when "10" & x"523" => DATA <= x"229f";
when "10" & x"524" => DATA <= x"e100";
when "10" & x"525" => DATA <= x"e77f";
when "10" & x"526" => DATA <= x"8007";
when "10" & x"527" => DATA <= x"effa";
when "10" & x"528" => DATA <= x"00ae";
when "10" & x"529" => DATA <= x"f7f8";
when "10" & x"52a" => DATA <= x"107c";
when "10" & x"52b" => DATA <= x"ff00";
when "10" & x"52c" => DATA <= x"27bb";
when "10" & x"52d" => DATA <= x"fc00";
when "10" & x"52e" => DATA <= x"e27f";
when "10" & x"52f" => DATA <= x"800b";
when "10" & x"530" => DATA <= x"9dfe";
when "10" & x"531" => DATA <= x"c047";
when "10" & x"532" => DATA <= x"bfe8";
when "10" & x"533" => DATA <= x"01b6";
when "10" & x"534" => DATA <= x"df7f";
when "10" & x"535" => DATA <= x"8011";
when "10" & x"536" => DATA <= x"eff0";
when "10" & x"537" => DATA <= x"008b";
when "10" & x"538" => DATA <= x"bfc2";
when "10" & x"539" => DATA <= x"0e77";
when "10" & x"53a" => DATA <= x"f801";
when "10" & x"53b" => DATA <= x"80f7";
when "10" & x"53c" => DATA <= x"aff0";
when "10" & x"53d" => DATA <= x"057f";
when "10" & x"53e" => DATA <= x"8027";
when "10" & x"53f" => DATA <= x"fd78";
when "10" & x"540" => DATA <= x"033f";
when "10" & x"541" => DATA <= x"8800";
when "10" & x"542" => DATA <= x"6efa";
when "10" & x"543" => DATA <= x"ff0b";
when "10" & x"544" => DATA <= x"8807";
when "10" & x"545" => DATA <= x"8602";
when "10" & x"546" => DATA <= x"377f";
when "10" & x"547" => DATA <= x"9e5e";
when "10" & x"548" => DATA <= x"2491";
when "10" & x"549" => DATA <= x"405f";
when "10" & x"54a" => DATA <= x"bfc8";
when "10" & x"54b" => DATA <= x"0df0";
when "10" & x"54c" => DATA <= x"d180";
when "10" & x"54d" => DATA <= x"80fb";
when "10" & x"54e" => DATA <= x"7bbf";
when "10" & x"54f" => DATA <= x"c700";
when "10" & x"550" => DATA <= x"05b8";
when "10" & x"551" => DATA <= x"f810";
when "10" & x"552" => DATA <= x"ff7b";
when "10" & x"553" => DATA <= x"bfeb";
when "10" & x"554" => DATA <= x"f1fa";
when "10" & x"555" => DATA <= x"f104";
when "10" & x"556" => DATA <= x"3eeb";
when "10" & x"557" => DATA <= x"fc86";
when "10" & x"558" => DATA <= x"e30b";
when "10" & x"559" => DATA <= x"88c6";
when "10" & x"55a" => DATA <= x"03fa";
when "10" & x"55b" => DATA <= x"ff40";
when "10" & x"55c" => DATA <= x"2051";
when "10" & x"55d" => DATA <= x"0002";
when "10" & x"55e" => DATA <= x"0143";
when "10" & x"55f" => DATA <= x"5381";
when "10" & x"560" => DATA <= x"ddb9";
when "10" & x"561" => DATA <= x"bbff";
when "10" & x"562" => DATA <= x"eef7";
when "10" & x"563" => DATA <= x"f713";
when "10" & x"564" => DATA <= x"8f0e";
when "10" & x"565" => DATA <= x"0783";
when "10" & x"566" => DATA <= x"81e0";
when "10" & x"567" => DATA <= x"e07b";
when "10" & x"568" => DATA <= x"bff7";
when "10" & x"569" => DATA <= x"bd1e";
when "10" & x"56a" => DATA <= x"ef7f";
when "10" & x"56b" => DATA <= x"87a7";
when "10" & x"56c" => DATA <= x"f802";
when "10" & x"56d" => DATA <= x"3f7f";
when "10" & x"56e" => DATA <= x"d000";
when "10" & x"56f" => DATA <= x"042a";
when "10" & x"570" => DATA <= x"0138";
when "10" & x"571" => DATA <= x"0001";
when "10" & x"572" => DATA <= x"fc00";
when "10" & x"573" => DATA <= x"1000";
when "10" & x"574" => DATA <= x"382b";
when "10" & x"575" => DATA <= x"c2b8";
when "10" & x"576" => DATA <= x"11ca";
when "10" & x"577" => DATA <= x"8570";
when "10" & x"578" => DATA <= x"fcff";
when "10" & x"579" => DATA <= x"47ef";
when "10" & x"57a" => DATA <= x"f3fb";
when "10" & x"57b" => DATA <= x"fdbe";
when "10" & x"57c" => DATA <= x"0106";
when "10" & x"57d" => DATA <= x"b841";
when "10" & x"57e" => DATA <= x"2e13";
when "10" & x"57f" => DATA <= x"d9f0";
when "10" & x"580" => DATA <= x"e080";
when "10" & x"581" => DATA <= x"000f";
when "10" & x"582" => DATA <= x"d00c";
when "10" & x"583" => DATA <= x"f07d";
when "10" & x"584" => DATA <= x"0e81";
when "10" & x"585" => DATA <= x"0004";
when "10" & x"586" => DATA <= x"976b";
when "10" & x"587" => DATA <= x"ff80";
when "10" & x"588" => DATA <= x"0400";
when "10" & x"589" => DATA <= x"04d2";
when "10" & x"58a" => DATA <= x"7dbe";
when "10" & x"58b" => DATA <= x"c040";
when "10" & x"58c" => DATA <= x"0018";
when "10" & x"58d" => DATA <= x"a216";
when "10" & x"58e" => DATA <= x"8079";
when "10" & x"58f" => DATA <= x"eefd";
when "10" & x"590" => DATA <= x"003f";
when "10" & x"591" => DATA <= x"4400";
when "10" & x"592" => DATA <= x"1028";
when "10" & x"593" => DATA <= x"02bf";
when "10" & x"594" => DATA <= x"dc0f";
when "10" & x"595" => DATA <= x"f102";
when "10" & x"596" => DATA <= x"49e0";
when "10" & x"597" => DATA <= x"007f";
when "10" & x"598" => DATA <= x"bdc0";
when "10" & x"599" => DATA <= x"6ff0";
when "10" & x"59a" => DATA <= x"0010";
when "10" & x"59b" => DATA <= x"3e80";
when "10" & x"59c" => DATA <= x"6f87";
when "10" & x"59d" => DATA <= x"d80b";
when "10" & x"59e" => DATA <= x"f400";
when "10" & x"59f" => DATA <= x"0800";
when "10" & x"5a0" => DATA <= x"8069";
when "10" & x"5a1" => DATA <= x"91c0";
when "10" & x"5a2" => DATA <= x"2fc0";
when "10" & x"5a3" => DATA <= x"2000";
when "10" & x"5a4" => DATA <= x"915f";
when "10" & x"5a5" => DATA <= x"e125";
when "10" & x"5a6" => DATA <= x"2010";
when "10" & x"5a7" => DATA <= x"4140";
when "10" & x"5a8" => DATA <= x"15fe";
when "10" & x"5a9" => DATA <= x"0912";
when "10" & x"5aa" => DATA <= x"8808";
when "10" & x"5ab" => DATA <= x"a047";
when "10" & x"5ac" => DATA <= x"e08d";
when "10" & x"5ad" => DATA <= x"86fe";
when "10" & x"5ae" => DATA <= x"023c";
when "10" & x"5af" => DATA <= x"0442";
when "10" & x"5b0" => DATA <= x"10f8";
when "10" & x"5b1" => DATA <= x"02bf";
when "10" & x"5b2" => DATA <= x"d80f";
when "10" & x"5b3" => DATA <= x"f422";
when "10" & x"5b4" => DATA <= x"01dc";
when "10" & x"5b5" => DATA <= x"0171";
when "10" & x"5b6" => DATA <= x"bbc1";
when "10" & x"5b7" => DATA <= x"eff0";
when "10" & x"5b8" => DATA <= x"8090";
when "10" & x"5b9" => DATA <= x"fe00";
when "10" & x"5ba" => DATA <= x"5f9f";
when "10" & x"5bb" => DATA <= x"d007";
when "10" & x"5bc" => DATA <= x"fa00";
when "10" & x"5bd" => DATA <= x"42ba";
when "10" & x"5be" => DATA <= x"80cc";
when "10" & x"5bf" => DATA <= x"6038";
when "10" & x"5c0" => DATA <= x"f091";
when "10" & x"5c1" => DATA <= x"400f";
when "10" & x"5c2" => DATA <= x"f003";
when "10" & x"5c3" => DATA <= x"fc96";
when "10" & x"5c4" => DATA <= x"48a0";
when "10" & x"5c5" => DATA <= x"0121";
when "10" & x"5c6" => DATA <= x"fd80";
when "10" & x"5c7" => DATA <= x"9f09";
when "10" & x"5c8" => DATA <= x"0005";
when "10" & x"5c9" => DATA <= x"4ca7";
when "10" & x"5ca" => DATA <= x"f061";
when "10" & x"5cb" => DATA <= x"e2ff";
when "10" & x"5cc" => DATA <= x"013f";
when "10" & x"5cd" => DATA <= x"0a25";
when "10" & x"5ce" => DATA <= x"023a";
when "10" & x"5cf" => DATA <= x"12bf";
when "10" & x"5d0" => DATA <= x"dc0f";
when "10" & x"5d1" => DATA <= x"f311";
when "10" & x"5d2" => DATA <= x"01fc";
when "10" & x"5d3" => DATA <= x"0079";
when "10" & x"5d4" => DATA <= x"3ec1";
when "10" & x"5d5" => DATA <= x"6ff0";
when "10" & x"5d6" => DATA <= x"5825";
when "10" & x"5d7" => DATA <= x"be80";
when "10" & x"5d8" => DATA <= x"0f97";
when "10" & x"5d9" => DATA <= x"c801";
when "10" & x"5da" => DATA <= x"fa00";
when "10" & x"5db" => DATA <= x"01bc";
when "10" & x"5dc" => DATA <= x"002f";
when "10" & x"5dd" => DATA <= x"1008";
when "10" & x"5de" => DATA <= x"fc10";
when "10" & x"5df" => DATA <= x"0040";
when "10" & x"5e0" => DATA <= x"3fc0";
when "10" & x"5e1" => DATA <= x"0ffa";
when "10" & x"5e2" => DATA <= x"4900";
when "10" & x"5e3" => DATA <= x"2004";
when "10" & x"5e4" => DATA <= x"80f4";
when "10" & x"5e5" => DATA <= x"02dd";
when "10" & x"5e6" => DATA <= x"06c0";
when "10" & x"5e7" => DATA <= x"0404";
when "10" & x"5e8" => DATA <= x"0483";
when "10" & x"5e9" => DATA <= x"a003";
when "10" & x"5ea" => DATA <= x"fc00";
when "10" & x"5eb" => DATA <= x"ffa0";
when "10" & x"5ec" => DATA <= x"4003";
when "10" & x"5ed" => DATA <= x"f400";
when "10" & x"5ee" => DATA <= x"ff40";
when "10" & x"5ef" => DATA <= x"bfc0";
when "10" & x"5f0" => DATA <= x"66c3";
when "10" & x"5f1" => DATA <= x"4bfc";
when "10" & x"5f2" => DATA <= x"00ff";
when "10" & x"5f3" => DATA <= x"04bf";
when "10" & x"5f4" => DATA <= x"c014";
when "10" & x"5f5" => DATA <= x"02ff";
when "10" & x"5f6" => DATA <= x"0036";
when "10" & x"5f7" => DATA <= x"c386";
when "10" & x"5f8" => DATA <= x"3085";
when "10" & x"5f9" => DATA <= x"003f";
when "10" & x"5fa" => DATA <= x"c00f";
when "10" & x"5fb" => DATA <= x"f480";
when "10" & x"5fc" => DATA <= x"4840";
when "10" & x"5fd" => DATA <= x"0024";
when "10" & x"5fe" => DATA <= x"87c0";
when "10" & x"5ff" => DATA <= x"0770";
when "10" & x"600" => DATA <= x"3201";
when "10" & x"601" => DATA <= x"6021";
when "10" & x"602" => DATA <= x"241d";
when "10" & x"603" => DATA <= x"002f";
when "10" & x"604" => DATA <= x"f00b";
when "10" & x"605" => DATA <= x"fc10";
when "10" & x"606" => DATA <= x"2830";
when "10" & x"607" => DATA <= x"3e80";
when "10" & x"608" => DATA <= x"0ff0";
when "10" & x"609" => DATA <= x"03fc";
when "10" & x"60a" => DATA <= x"0d5b";
when "10" & x"60b" => DATA <= x"0ff0";
when "10" & x"60c" => DATA <= x"03fc";
when "10" & x"60d" => DATA <= x"20ff";
when "10" & x"60e" => DATA <= x"2050";
when "10" & x"60f" => DATA <= x"13fd";
when "10" & x"610" => DATA <= x"e037";
when "10" & x"611" => DATA <= x"7031";
when "10" & x"612" => DATA <= x"c802";
when "10" & x"613" => DATA <= x"0401";
when "10" & x"614" => DATA <= x"4dfe";
when "10" & x"615" => DATA <= x"fd7f";
when "10" & x"616" => DATA <= x"00d0";
when "10" & x"617" => DATA <= x"04b0";
when "10" & x"618" => DATA <= x"0015";
when "10" & x"619" => DATA <= x"fc3e";
when "10" & x"61a" => DATA <= x"7f80";
when "10" & x"61b" => DATA <= x"1108";
when "10" & x"61c" => DATA <= x"200b";
when "10" & x"61d" => DATA <= x"c0fe";
when "10" & x"61e" => DATA <= x"fd7f";
when "10" & x"61f" => DATA <= x"d000";
when "10" & x"620" => DATA <= x"4804";
when "10" & x"621" => DATA <= x"bfa7";
when "10" & x"622" => DATA <= x"e7fd";
when "10" & x"623" => DATA <= x"000c";
when "10" & x"624" => DATA <= x"8104";
when "10" & x"625" => DATA <= x"2eff";
when "10" & x"626" => DATA <= x"0010";
when "10" & x"627" => DATA <= x"08a0";
when "10" & x"628" => DATA <= x"0600";
when "10" & x"629" => DATA <= x"1ebf";
when "10" & x"62a" => DATA <= x"c006";
when "10" & x"62b" => DATA <= x"c6a2";
when "10" & x"62c" => DATA <= x"113c";
when "10" & x"62d" => DATA <= x"8e5f";
when "10" & x"62e" => DATA <= x"bfc0";
when "10" & x"62f" => DATA <= x"15fd";
when "10" & x"630" => DATA <= x"dfef";
when "10" & x"631" => DATA <= x"77f8";
when "10" & x"632" => DATA <= x"02bf";
when "10" & x"633" => DATA <= x"e401";
when "10" & x"634" => DATA <= x"f000";
when "10" & x"635" => DATA <= x"aff0";
when "10" & x"636" => DATA <= x"03f1";
when "10" & x"637" => DATA <= x"181c";
when "10" & x"638" => DATA <= x"3e9f";
when "10" & x"639" => DATA <= x"2bfd";
when "10" & x"63a" => DATA <= x"e1de";
when "10" & x"63b" => DATA <= x"35e6";
when "10" & x"63c" => DATA <= x"ef9f";
when "10" & x"63d" => DATA <= x"f638";
when "10" & x"63e" => DATA <= x"1d4f";
when "10" & x"63f" => DATA <= x"3fef";
when "10" & x"640" => DATA <= x"47b0";
when "10" & x"641" => DATA <= x"01e6";
when "10" & x"642" => DATA <= x"f7ef";
when "10" & x"643" => DATA <= x"f773";
when "10" & x"644" => DATA <= x"fc00";
when "10" & x"645" => DATA <= x"2e97";
when "10" & x"646" => DATA <= x"f3d8";
when "10" & x"647" => DATA <= x"8068";
when "10" & x"648" => DATA <= x"3e6c";
when "10" & x"649" => DATA <= x"a048";
when "10" & x"64a" => DATA <= x"a016";
when "10" & x"64b" => DATA <= x"2916";
when "10" & x"64c" => DATA <= x"8159";
when "10" & x"64d" => DATA <= x"4404";
when "10" & x"64e" => DATA <= x"1761";
when "10" & x"64f" => DATA <= x"d001";
when "10" & x"650" => DATA <= x"cc00";
when "10" & x"651" => DATA <= x"2011";
when "10" & x"652" => DATA <= x"0c82";
when "10" & x"653" => DATA <= x"4800";
when "10" & x"654" => DATA <= x"011c";
when "10" & x"655" => DATA <= x"8642";
when "10" & x"656" => DATA <= x"1988";
when "10" & x"657" => DATA <= x"d064";
when "10" & x"658" => DATA <= x"33fa";
when "10" & x"659" => DATA <= x"fdd0";
when "10" & x"65a" => DATA <= x"0401";
when "10" & x"65b" => DATA <= x"5000";
when "10" & x"65c" => DATA <= x"a000";
when "10" & x"65d" => DATA <= x"ff09";
when "10" & x"65e" => DATA <= x"8001";
when "10" & x"65f" => DATA <= x"286e";
when "10" & x"660" => DATA <= x"003f";
when "10" & x"661" => DATA <= x"8424";
when "10" & x"662" => DATA <= x"0100";
when "10" & x"663" => DATA <= x"005f";
when "10" & x"664" => DATA <= x"0040";
when "10" & x"665" => DATA <= x"802a";
when "10" & x"666" => DATA <= x"0009";
when "10" & x"667" => DATA <= x"8315";
when "10" & x"668" => DATA <= x"ebc0";
when "10" & x"669" => DATA <= x"0200";
when "10" & x"66a" => DATA <= x"0208";
when "10" & x"66b" => DATA <= x"1002";
when "10" & x"66c" => DATA <= x"1c41";
when "10" & x"66d" => DATA <= x"5100";
when "10" & x"66e" => DATA <= x"0400";
when "10" & x"66f" => DATA <= x"0ca4";
when "10" & x"670" => DATA <= x"07cb";
when "10" & x"671" => DATA <= x"3240";
when "10" & x"672" => DATA <= x"0440";
when "10" & x"673" => DATA <= x"12c1";
when "10" & x"674" => DATA <= x"e840";
when "10" & x"675" => DATA <= x"0fa8";
when "10" & x"676" => DATA <= x"0000";
when "10" & x"677" => DATA <= x"81b6";
when "10" & x"678" => DATA <= x"9068";
when "10" & x"679" => DATA <= x"07d8";
when "10" & x"67a" => DATA <= x"1480";
when "10" & x"67b" => DATA <= x"c0a0";
when "10" & x"67c" => DATA <= x"0418";
when "10" & x"67d" => DATA <= x"000e";
when "10" & x"67e" => DATA <= x"a069";
when "10" & x"67f" => DATA <= x"01dc";
when "10" & x"680" => DATA <= x"0617";
when "10" & x"681" => DATA <= x"1380";
when "10" & x"682" => DATA <= x"c062";
when "10" & x"683" => DATA <= x"0138";
when "10" & x"684" => DATA <= x"2801";
when "10" & x"685" => DATA <= x"00f0";
when "10" & x"686" => DATA <= x"002c";
when "10" & x"687" => DATA <= x"57cf";
when "10" & x"688" => DATA <= x"4afc";
when "10" & x"689" => DATA <= x"7a3e";
when "10" & x"68a" => DATA <= x"5f8f";
when "10" & x"68b" => DATA <= x"d7cb";
when "10" & x"68c" => DATA <= x"d026";
when "10" & x"68d" => DATA <= x"0311";
when "10" & x"68e" => DATA <= x"81e8";
when "10" & x"68f" => DATA <= x"5e81";
when "10" & x"690" => DATA <= x"d88c";
when "10" & x"691" => DATA <= x"0702";
when "10" & x"692" => DATA <= x"0120";
when "10" & x"693" => DATA <= x"d000";
when "10" & x"694" => DATA <= x"0101";
when "10" & x"695" => DATA <= x"c0da";
when "10" & x"696" => DATA <= x"0c7f";
when "10" & x"697" => DATA <= x"3e2b";
when "10" & x"698" => DATA <= x"f9bf";
when "10" & x"699" => DATA <= x"5ffb";
when "10" & x"69a" => DATA <= x"bef7";
when "10" & x"69b" => DATA <= x"affd";
when "10" & x"69c" => DATA <= x"f718";
when "10" & x"69d" => DATA <= x"db88";
when "10" & x"69e" => DATA <= x"0687";
when "10" & x"69f" => DATA <= x"a870";
when "10" & x"6a0" => DATA <= x"3d43";
when "10" & x"6a1" => DATA <= x"81ee";
when "10" & x"6a2" => DATA <= x"efaf";
when "10" & x"6a3" => DATA <= x"feef";
when "10" & x"6a4" => DATA <= x"afe7";
when "10" & x"6a5" => DATA <= x"b3dd";
when "10" & x"6a6" => DATA <= x"ff5f";
when "10" & x"6a7" => DATA <= x"c7e0";
when "10" & x"6a8" => DATA <= x"0944";
when "10" & x"6a9" => DATA <= x"2271";
when "10" & x"6aa" => DATA <= x"0880";
when "10" & x"6ab" => DATA <= x"4a74";
when "10" & x"6ac" => DATA <= x"0010";
when "10" & x"6ad" => DATA <= x"0008";
when "10" & x"6ae" => DATA <= x"000f";
when "10" & x"6af" => DATA <= x"c408";
when "10" & x"6b0" => DATA <= x"0114";
when "10" & x"6b1" => DATA <= x"8202";
when "10" & x"6b2" => DATA <= x"5043";
when "10" & x"6b3" => DATA <= x"0102";
when "10" & x"6b4" => DATA <= x"807e";
when "10" & x"6b5" => DATA <= x"aff7";
when "10" & x"6b6" => DATA <= x"fdfa";
when "10" & x"6b7" => DATA <= x"7c3c";
when "10" & x"6b8" => DATA <= x"804c";
when "10" & x"6b9" => DATA <= x"3cf8";
when "10" & x"6ba" => DATA <= x"fc4e";
when "10" & x"6bb" => DATA <= x"87c3";
when "10" & x"6bc" => DATA <= x"c5d4";
when "10" & x"6bd" => DATA <= x"e8f4";
when "10" & x"6be" => DATA <= x"3a4d";
when "10" & x"6bf" => DATA <= x"0250";
when "10" & x"6c0" => DATA <= x"0121";
when "10" & x"6c1" => DATA <= x"fef4";
when "10" & x"6c2" => DATA <= x"1300";
when "10" & x"6c3" => DATA <= x"b801";
when "10" & x"6c4" => DATA <= x"04ff";
when "10" & x"6c5" => DATA <= x"0200";
when "10" & x"6c6" => DATA <= x"01ef";
when "10" & x"6c7" => DATA <= x"c7e8";
when "10" & x"6c8" => DATA <= x"0400";
when "10" & x"6c9" => DATA <= x"eb00";
when "10" & x"6ca" => DATA <= x"200f";
when "10" & x"6cb" => DATA <= x"55ff";
when "10" & x"6cc" => DATA <= x"400f";
when "10" & x"6cd" => DATA <= x"f3a0";
when "10" & x"6ce" => DATA <= x"e4d1";
when "10" & x"6cf" => DATA <= x"5fe0";
when "10" & x"6d0" => DATA <= x"1003";
when "10" & x"6d1" => DATA <= x"fc02";
when "10" & x"6d2" => DATA <= x"3101";
when "10" & x"6d3" => DATA <= x"07d7";
when "10" & x"6d4" => DATA <= x"e800";
when "10" & x"6d5" => DATA <= x"03fd";
when "10" & x"6d6" => DATA <= x"34da";
when "10" & x"6d7" => DATA <= x"003f";
when "10" & x"6d8" => DATA <= x"29f0";
when "10" & x"6d9" => DATA <= x"faff";
when "10" & x"6da" => DATA <= x"a010";
when "10" & x"6db" => DATA <= x"8013";
when "10" & x"6dc" => DATA <= x"801f";
when "10" & x"6dd" => DATA <= x"f400";
when "10" & x"6de" => DATA <= x"2a90";
when "10" & x"6df" => DATA <= x"07fd";
when "10" & x"6e0" => DATA <= x"002c";
when "10" & x"6e1" => DATA <= x"9f55";
when "10" & x"6e2" => DATA <= x"f0a0";
when "10" & x"6e3" => DATA <= x"7f80";
when "10" & x"6e4" => DATA <= x"0085";
when "10" & x"6e5" => DATA <= x"3eff";
when "10" & x"6e6" => DATA <= x"3f3f";
when "10" & x"6e7" => DATA <= x"c002";
when "10" & x"6e8" => DATA <= x"627e";
when "10" & x"6e9" => DATA <= x"ffd1";
when "10" & x"6ea" => DATA <= x"c0bf";
when "10" & x"6eb" => DATA <= x"9fcd";
when "10" & x"6ec" => DATA <= x"aff0";
when "10" & x"6ed" => DATA <= x"0004";
when "10" & x"6ee" => DATA <= x"0039";
when "10" & x"6ef" => DATA <= x"1c2e";
when "10" & x"6f0" => DATA <= x"178e";
when "10" & x"6f1" => DATA <= x"f7f1";
when "10" & x"6f2" => DATA <= x"f800";
when "10" & x"6f3" => DATA <= x"08e0";
when "10" & x"6f4" => DATA <= x"07fb";
when "10" & x"6f5" => DATA <= x"e400";
when "10" & x"6f6" => DATA <= x"7090";
when "10" & x"6f7" => DATA <= x"07f8";
when "10" & x"6f8" => DATA <= x"0008";
when "10" & x"6f9" => DATA <= x"067e";
when "10" & x"6fa" => DATA <= x"d7e2";
when "10" & x"6fb" => DATA <= x"a9f2";
when "10" & x"6fc" => DATA <= x"ff07";
when "10" & x"6fd" => DATA <= x"803b";
when "10" & x"6fe" => DATA <= x"fd54";
when "10" & x"6ff" => DATA <= x"d77f";
when "10" & x"700" => DATA <= x"d007";
when "10" & x"701" => DATA <= x"7faa";
when "10" & x"702" => DATA <= x"abfe";
when "10" & x"703" => DATA <= x"8017";
when "10" & x"704" => DATA <= x"f47e";
when "10" & x"705" => DATA <= x"2aaf";
when "10" & x"706" => DATA <= x"fa00";
when "10" & x"707" => DATA <= x"e3c6";
when "10" & x"708" => DATA <= x"e870";
when "10" & x"709" => DATA <= x"3fa0";
when "10" & x"70a" => DATA <= x"0ffa";
when "10" & x"70b" => DATA <= x"80a0";
when "10" & x"70c" => DATA <= x"0403";
when "10" & x"70d" => DATA <= x"0010";
when "10" & x"70e" => DATA <= x"ff00";
when "10" & x"70f" => DATA <= x"0fc0";
when "10" & x"710" => DATA <= x"0c07";
when "10" & x"711" => DATA <= x"fafc";
when "10" & x"712" => DATA <= x"00ff";
when "10" & x"713" => DATA <= x"003f";
when "10" & x"714" => DATA <= x"0c15";
when "10" & x"715" => DATA <= x"fefb";
when "10" & x"716" => DATA <= x"003f";
when "10" & x"717" => DATA <= x"c00f";
when "10" & x"718" => DATA <= x"f77f";
when "10" & x"719" => DATA <= x"7f80";
when "10" & x"71a" => DATA <= x"1fe0";
when "10" & x"71b" => DATA <= x"0eff";
when "10" & x"71c" => DATA <= x"2590";
when "10" & x"71d" => DATA <= x"ca0f";
when "10" & x"71e" => DATA <= x"f003";
when "10" & x"71f" => DATA <= x"fdbe";
when "10" & x"720" => DATA <= x"ffe0";
when "10" & x"721" => DATA <= x"07f8";
when "10" & x"722" => DATA <= x"01fe";
when "10" & x"723" => DATA <= x"f37f";
when "10" & x"724" => DATA <= x"8828";
when "10" & x"725" => DATA <= x"01fe";
when "10" & x"726" => DATA <= x"007f";
when "10" & x"727" => DATA <= x"8045";
when "10" & x"728" => DATA <= x"35fe";
when "10" & x"729" => DATA <= x"007f";
when "10" & x"72a" => DATA <= x"801f";
when "10" & x"72b" => DATA <= x"e115";
when "10" & x"72c" => DATA <= x"abfc";
when "10" & x"72d" => DATA <= x"fe00";
when "10" & x"72e" => DATA <= x"7f80";
when "10" & x"72f" => DATA <= x"1fe0";
when "10" & x"730" => DATA <= x"04f5";
when "10" & x"731" => DATA <= x"7f80";
when "10" & x"732" => DATA <= x"1fe0";
when "10" & x"733" => DATA <= x"0038";
when "10" & x"734" => DATA <= x"01fc";
when "10" & x"735" => DATA <= x"1343";
when "10" & x"736" => DATA <= x"a81f";
when "10" & x"737" => DATA <= x"f400";
when "10" & x"738" => DATA <= x"c67f";
when "10" & x"739" => DATA <= x"82e8";
when "10" & x"73a" => DATA <= x"0c46";
when "10" & x"73b" => DATA <= x"1800";
when "10" & x"73c" => DATA <= x"0e47";
when "10" & x"73d" => DATA <= x"e005";
when "10" & x"73e" => DATA <= x"00e2";
when "10" & x"73f" => DATA <= x"8004";
when "10" & x"740" => DATA <= x"0030";
when "10" & x"741" => DATA <= x"1001";
when "10" & x"742" => DATA <= x"d4ff";
when "10" & x"743" => DATA <= x"a001";
when "10" & x"744" => DATA <= x"1700";
when "10" & x"745" => DATA <= x"17cf";
when "10" & x"746" => DATA <= x"e002";
when "10" & x"747" => DATA <= x"028b";
when "10" & x"748" => DATA <= x"8000";
when "10" & x"749" => DATA <= x"6e00";
when "10" & x"74a" => DATA <= x"a0d0";
when "10" & x"74b" => DATA <= x"409e";
when "10" & x"74c" => DATA <= x"2180";
when "10" & x"74d" => DATA <= x"0f6b";
when "10" & x"74e" => DATA <= x"9582";
when "10" & x"74f" => DATA <= x"ec30";
when "10" & x"750" => DATA <= x"e750";
when "10" & x"751" => DATA <= x"8017";
when "10" & x"752" => DATA <= x"8fea";
when "10" & x"753" => DATA <= x"fc1f";
when "10" & x"754" => DATA <= x"2fdf";
when "10" & x"755" => DATA <= x"e006";
when "10" & x"756" => DATA <= x"bbfc";
when "10" & x"757" => DATA <= x"4aff";
when "10" & x"758" => DATA <= x"101e";
when "10" & x"759" => DATA <= x"1fe0";
when "10" & x"75a" => DATA <= x"069b";
when "10" & x"75b" => DATA <= x"fc80";
when "10" & x"75c" => DATA <= x"ff00";
when "10" & x"75d" => DATA <= x"0d1f";
when "10" & x"75e" => DATA <= x"e000";
when "10" & x"75f" => DATA <= x"3bfc";
when "10" & x"760" => DATA <= x"02ff";
when "10" & x"761" => DATA <= x"0002";
when "10" & x"762" => DATA <= x"07ef";
when "10" & x"763" => DATA <= x"0af3";
when "10" & x"764" => DATA <= x"793c";
when "10" & x"765" => DATA <= x"de0f";
when "10" & x"766" => DATA <= x"f415";
when "10" & x"767" => DATA <= x"03d4";
when "10" & x"768" => DATA <= x"381d";
when "10" & x"769" => DATA <= x"0e3f";
when "10" & x"76a" => DATA <= x"7f80";
when "10" & x"76b" => DATA <= x"0580";
when "10" & x"76c" => DATA <= x"e900";
when "10" & x"76d" => DATA <= x"4080";
when "10" & x"76e" => DATA <= x"0a25";
when "10" & x"76f" => DATA <= x"0e00";
when "10" & x"770" => DATA <= x"57be";
when "10" & x"771" => DATA <= x"c00f";
when "10" & x"772" => DATA <= x"65a0";
when "10" & x"773" => DATA <= x"3280";
when "10" & x"774" => DATA <= x"1e4f";
when "10" & x"775" => DATA <= x"a02b";
when "10" & x"776" => DATA <= x"8abf";
when "10" & x"777" => DATA <= x"df00";
when "10" & x"778" => DATA <= x"0038";
when "10" & x"779" => DATA <= x"7c00";
when "10" & x"77a" => DATA <= x"f7af";
when "10" & x"77b" => DATA <= x"f378";
when "10" & x"77c" => DATA <= x"01fe";
when "10" & x"77d" => DATA <= x"8700";
when "10" & x"77e" => DATA <= x"06ab";
when "10" & x"77f" => DATA <= x"fc06";
when "10" & x"780" => DATA <= x"f87f";
when "10" & x"781" => DATA <= x"820e";
when "10" & x"782" => DATA <= x"0749";
when "10" & x"783" => DATA <= x"703f";
when "10" & x"784" => DATA <= x"83d0";
when "10" & x"785" => DATA <= x"e100";
when "10" & x"786" => DATA <= x"03e0";
when "10" & x"787" => DATA <= x"40bc";
when "10" & x"788" => DATA <= x"5f00";
when "10" & x"789" => DATA <= x"0600";
when "10" & x"78a" => DATA <= x"0011";
when "10" & x"78b" => DATA <= x"fca4";
when "10" & x"78c" => DATA <= x"030a";
when "10" & x"78d" => DATA <= x"5000";
when "10" & x"78e" => DATA <= x"6800";
when "10" & x"78f" => DATA <= x"1026";
when "10" & x"790" => DATA <= x"0381";
when "10" & x"791" => DATA <= x"f200";
when "10" & x"792" => DATA <= x"8100";
when "10" & x"793" => DATA <= x"2006";
when "10" & x"794" => DATA <= x"eb92";
when "10" & x"795" => DATA <= x"0500";
when "10" & x"796" => DATA <= x"3c10";
when "10" & x"797" => DATA <= x"0241";
when "10" & x"798" => DATA <= x"100c";
when "10" & x"799" => DATA <= x"0006";
when "10" & x"79a" => DATA <= x"00d0";
when "10" & x"79b" => DATA <= x"002c";
when "10" & x"79c" => DATA <= x"4608";
when "10" & x"79d" => DATA <= x"0094";
when "10" & x"79e" => DATA <= x"4420";
when "10" & x"79f" => DATA <= x"7389";
when "10" & x"7a0" => DATA <= x"44e2";
when "10" & x"7a1" => DATA <= x"f140";
when "10" & x"7a2" => DATA <= x"0004";
when "10" & x"7a3" => DATA <= x"8103";
when "10" & x"7a4" => DATA <= x"8809";
when "10" & x"7a5" => DATA <= x"1048";
when "10" & x"7a6" => DATA <= x"0011";
when "10" & x"7a7" => DATA <= x"9204";
when "10" & x"7a8" => DATA <= x"e200";
when "10" & x"7a9" => DATA <= x"001e";
when "10" & x"7aa" => DATA <= x"4000";
when "10" & x"7ab" => DATA <= x"30c0";
when "10" & x"7ac" => DATA <= x"5400";
when "10" & x"7ad" => DATA <= x"08a8";
when "10" & x"7ae" => DATA <= x"2302";
when "10" & x"7af" => DATA <= x"48c0";
when "10" & x"7b0" => DATA <= x"9068";
when "10" & x"7b1" => DATA <= x"001c";
when "10" & x"7b2" => DATA <= x"0600";
when "10" & x"7b3" => DATA <= x"0089";
when "10" & x"7b4" => DATA <= x"c061";
when "10" & x"7b5" => DATA <= x"5e28";
when "10" & x"7b6" => DATA <= x"9f8f";
when "10" & x"7b7" => DATA <= x"37e3";
when "10" & x"7b8" => DATA <= x"c5e8";
when "10" & x"7b9" => DATA <= x"7daf";
when "10" & x"7ba" => DATA <= x"8743";
when "10" & x"7bb" => DATA <= x"e02e";
when "10" & x"7bc" => DATA <= x"d775";
when "10" & x"7bd" => DATA <= x"a080";
when "10" & x"7be" => DATA <= x"607a";
when "10" & x"7bf" => DATA <= x"c752";
when "10" & x"7c0" => DATA <= x"385e";
when "10" & x"7c1" => DATA <= x"f400";
when "10" & x"7c2" => DATA <= x"fe7f";
when "10" & x"7c3" => DATA <= x"83df";
when "10" & x"7c4" => DATA <= x"ce77";
when "10" & x"7c5" => DATA <= x"fd00";
when "10" & x"7c6" => DATA <= x"0040";
when "10" & x"7c7" => DATA <= x"680e";
when "10" & x"7c8" => DATA <= x"df2f";
when "10" & x"7c9" => DATA <= x"80c0";
when "10" & x"7ca" => DATA <= x"0d06";
when "10" & x"7cb" => DATA <= x"fd7b";
when "10" & x"7cc" => DATA <= x"81e8";
when "10" & x"7cd" => DATA <= x"01f9";
when "10" & x"7ce" => DATA <= x"5ee0";
when "10" & x"7cf" => DATA <= x"1e00";
when "10" & x"7d0" => DATA <= x"2073";
when "10" & x"7d1" => DATA <= x"8d0e";
when "10" & x"7d2" => DATA <= x"70f0";
when "10" & x"7d3" => DATA <= x"7287";
when "10" & x"7d4" => DATA <= x"afbe";
when "10" & x"7d5" => DATA <= x"bfe7";
when "10" & x"7d6" => DATA <= x"fa8f";
when "10" & x"7d7" => DATA <= x"a8ff";
when "10" & x"7d8" => DATA <= x"805f";
when "10" & x"7d9" => DATA <= x"e032";
when "10" & x"7da" => DATA <= x"0984";
when "10" & x"7db" => DATA <= x"0744";
when "10" & x"7dc" => DATA <= x"0000";
when "10" & x"7dd" => DATA <= x"1c80";
when "10" & x"7de" => DATA <= x"2058";
when "10" & x"7df" => DATA <= x"0807";
when "10" & x"7e0" => DATA <= x"4181";
when "10" & x"7e1" => DATA <= x"d55c";
when "10" & x"7e2" => DATA <= x"15fe";
when "10" & x"7e3" => DATA <= x"dd7f";
when "10" & x"7e4" => DATA <= x"c8fb";
when "10" & x"7e5" => DATA <= x"f0c6";
when "10" & x"7e6" => DATA <= x"7c7e";
when "10" & x"7e7" => DATA <= x"1888";
when "10" & x"7e8" => DATA <= x"0f87";
when "10" & x"7e9" => DATA <= x"e3f5";
when "10" & x"7ea" => DATA <= x"3efd";
when "10" & x"7eb" => DATA <= x"7a9f";
when "10" & x"7ec" => DATA <= x"4f67";
when "10" & x"7ed" => DATA <= x"93d1";
when "10" & x"7ee" => DATA <= x"fc92";
when "10" & x"7ef" => DATA <= x"0200";
when "10" & x"7f0" => DATA <= x"b800";
when "10" & x"7f1" => DATA <= x"00a3";
when "10" & x"7f2" => DATA <= x"2480";
when "10" & x"7f3" => DATA <= x"3fc0";
when "10" & x"7f4" => DATA <= x"0424";
when "10" & x"7f5" => DATA <= x"6180";
when "10" & x"7f6" => DATA <= x"f048";
when "10" & x"7f7" => DATA <= x"383f";
when "10" & x"7f8" => DATA <= x"e800";
when "10" & x"7f9" => DATA <= x"6067";
when "10" & x"7fa" => DATA <= x"141e";
when "10" & x"7fb" => DATA <= x"0dcf";
when "10" & x"7fc" => DATA <= x"b023";
when "10" & x"7fd" => DATA <= x"8c00";
when "10" & x"7fe" => DATA <= x"02ac";
when "10" & x"7ff" => DATA <= x"0700";
when "10" & x"800" => DATA <= x"fc21";
when "10" & x"801" => DATA <= x"4000";
when "10" & x"802" => DATA <= x"e7f8";
when "10" & x"803" => DATA <= x"0680";
when "10" & x"804" => DATA <= x"0094";
when "10" & x"805" => DATA <= x"0050";
when "10" & x"806" => DATA <= x"7fa1";
when "10" & x"807" => DATA <= x"9001";
when "10" & x"808" => DATA <= x"0507";
when "10" & x"809" => DATA <= x"003f";
when "10" & x"80a" => DATA <= x"c007";
when "10" & x"80b" => DATA <= x"f280";
when "10" & x"80c" => DATA <= x"8000";
when "10" & x"80d" => DATA <= x"8000";
when "10" & x"80e" => DATA <= x"35c6";
when "10" & x"80f" => DATA <= x"00f0";
when "10" & x"810" => DATA <= x"39c0";
when "10" & x"811" => DATA <= x"0007";
when "10" & x"812" => DATA <= x"003f";
when "10" & x"813" => DATA <= x"c80c";
when "10" & x"814" => DATA <= x"6703";
when "10" & x"815" => DATA <= x"89c8";
when "10" & x"816" => DATA <= x"cc00";
when "10" & x"817" => DATA <= x"1fda";
when "10" & x"818" => DATA <= x"93fe";
when "10" & x"819" => DATA <= x"2400";
when "10" & x"81a" => DATA <= x"3fcf";
when "10" & x"81b" => DATA <= x"f3fe";
when "10" & x"81c" => DATA <= x"fc00";
when "10" & x"81d" => DATA <= x"3fe8";
when "10" & x"81e" => DATA <= x"0106";
when "10" & x"81f" => DATA <= x"8700";
when "10" & x"820" => DATA <= x"2000";
when "10" & x"821" => DATA <= x"00ba";
when "10" & x"822" => DATA <= x"0040";
when "10" & x"823" => DATA <= x"2601";
when "10" & x"824" => DATA <= x"0297";
when "10" & x"825" => DATA <= x"f006";
when "10" & x"826" => DATA <= x"8000";
when "10" & x"827" => DATA <= x"6fda";
when "10" & x"828" => DATA <= x"027f";
when "10" & x"829" => DATA <= x"c803";
when "10" & x"82a" => DATA <= x"fe80";
when "10" & x"82b" => DATA <= x"1ff2";
when "10" & x"82c" => DATA <= x"00ff";
when "10" & x"82d" => DATA <= x"a017";
when "10" & x"82e" => DATA <= x"fd78";
when "10" & x"82f" => DATA <= x"1e11";
when "10" & x"830" => DATA <= x"0ffa";
when "10" & x"831" => DATA <= x"00af";
when "10" & x"832" => DATA <= x"f3f9";
when "10" & x"833" => DATA <= x"584a";
when "10" & x"834" => DATA <= x"ff00";
when "10" & x"835" => DATA <= x"081f";
when "10" & x"836" => DATA <= x"f5fc";
when "10" & x"837" => DATA <= x"004f";
when "10" & x"838" => DATA <= x"bfc0";
when "10" & x"839" => DATA <= x"0f37";
when "10" & x"83a" => DATA <= x"f804";
when "10" & x"83b" => DATA <= x"febe";
when "10" & x"83c" => DATA <= x"aff1";
when "10" & x"83d" => DATA <= x"c009";
when "10" & x"83e" => DATA <= x"fe00";
when "10" & x"83f" => DATA <= x"013f";
when "10" & x"840" => DATA <= x"12a5";
when "10" & x"841" => DATA <= x"f020";
when "10" & x"842" => DATA <= x"01ff";
when "10" & x"843" => DATA <= x"400f";
when "10" & x"844" => DATA <= x"f571";
when "10" & x"845" => DATA <= x"f000";
when "10" & x"846" => DATA <= x"20a0";
when "10" & x"847" => DATA <= x"05c3";
when "10" & x"848" => DATA <= x"e402";
when "10" & x"849" => DATA <= x"c700";
when "10" & x"84a" => DATA <= x"011e";
when "10" & x"84b" => DATA <= x"000a";
when "10" & x"84c" => DATA <= x"ff70";
when "10" & x"84d" => DATA <= x"2140";
when "10" & x"84e" => DATA <= x"4007";
when "10" & x"84f" => DATA <= x"f801";
when "10" & x"850" => DATA <= x"f6bf";
when "10" & x"851" => DATA <= x"7780";
when "10" & x"852" => DATA <= x"1f40";
when "10" & x"853" => DATA <= x"07f8";
when "10" & x"854" => DATA <= x"01fa";
when "10" & x"855" => DATA <= x"257f";
when "10" & x"856" => DATA <= x"be9f";
when "10" & x"857" => DATA <= x"ee03";
when "10" & x"858" => DATA <= x"f800";
when "10" & x"859" => DATA <= x"7ef1";
when "10" & x"85a" => DATA <= x"7f87";
when "10" & x"85b" => DATA <= x"cfe8";
when "10" & x"85c" => DATA <= x"7e00";
when "10" & x"85d" => DATA <= x"0e93";
when "10" & x"85e" => DATA <= x"df8e";
when "10" & x"85f" => DATA <= x"6707";
when "10" & x"860" => DATA <= x"0007";
when "10" & x"861" => DATA <= x"2c02";
when "10" & x"862" => DATA <= x"8200";
when "10" & x"863" => DATA <= x"0f87";
when "10" & x"864" => DATA <= x"8006";
when "10" & x"865" => DATA <= x"802b";
when "10" & x"866" => DATA <= x"f800";
when "10" & x"867" => DATA <= x"dc20";
when "10" & x"868" => DATA <= x"2728";
when "10" & x"869" => DATA <= x"01fe";
when "10" & x"86a" => DATA <= x"fe00";
when "10" & x"86b" => DATA <= x"3cde";
when "10" & x"86c" => DATA <= x"2020";
when "10" & x"86d" => DATA <= x"0311";
when "10" & x"86e" => DATA <= x"8e07";
when "10" & x"86f" => DATA <= x"000f";
when "10" & x"870" => DATA <= x"c394";
when "10" & x"871" => DATA <= x"0001";
when "10" & x"872" => DATA <= x"3fd2";
when "10" & x"873" => DATA <= x"0107";
when "10" & x"874" => DATA <= x"8005";
when "10" & x"875" => DATA <= x"1400";
when "10" & x"876" => DATA <= x"40a0";
when "10" & x"877" => DATA <= x"0010";
when "10" & x"878" => DATA <= x"0007";
when "10" & x"879" => DATA <= x"6002";
when "10" & x"87a" => DATA <= x"0030";
when "10" & x"87b" => DATA <= x"0020";
when "10" & x"87c" => DATA <= x"0078";
when "10" & x"87d" => DATA <= x"5002";
when "10" & x"87e" => DATA <= x"4e40";
when "10" & x"87f" => DATA <= x"1ce8";
when "10" & x"880" => DATA <= x"2400";
when "10" & x"881" => DATA <= x"0801";
when "10" & x"882" => DATA <= x"4020";
when "10" & x"883" => DATA <= x"2758";
when "10" & x"884" => DATA <= x"0004";
when "10" & x"885" => DATA <= x"4000";
when "10" & x"886" => DATA <= x"1028";
when "10" & x"887" => DATA <= x"008d";
when "10" & x"888" => DATA <= x"4000";
when "10" & x"889" => DATA <= x"1900";
when "10" & x"88a" => DATA <= x"7ad0";
when "10" & x"88b" => DATA <= x"02c2";
when "10" & x"88c" => DATA <= x"b010";
when "10" & x"88d" => DATA <= x"0887";
when "10" & x"88e" => DATA <= x"7001";
when "10" & x"88f" => DATA <= x"e002";
when "10" & x"890" => DATA <= x"9000";
when "10" & x"891" => DATA <= x"0998";
when "10" & x"892" => DATA <= x"00fe";
when "10" & x"893" => DATA <= x"7ccf";
when "10" & x"894" => DATA <= x"f9fc";
when "10" & x"895" => DATA <= x"f150";
when "10" & x"896" => DATA <= x"7c06";
when "10" & x"897" => DATA <= x"4341";
when "10" & x"898" => DATA <= x"80c7";
when "10" & x"899" => DATA <= x"e079";
when "10" & x"89a" => DATA <= x"000c";
when "10" & x"89b" => DATA <= x"1f9e";
when "10" & x"89c" => DATA <= x"0720";
when "10" & x"89d" => DATA <= x"5020";
when "10" & x"89e" => DATA <= x"0006";
when "10" & x"89f" => DATA <= x"7082";
when "10" & x"8a0" => DATA <= x"0072";
when "10" & x"8a1" => DATA <= x"0080";
when "10" & x"8a2" => DATA <= x"0688";
when "10" & x"8a3" => DATA <= x"2c1d";
when "10" & x"8a4" => DATA <= x"7ef7";
when "10" & x"8a5" => DATA <= x"7803";
when "10" & x"8a6" => DATA <= x"2b12";
when "10" & x"8a7" => DATA <= x"8017";
when "10" & x"8a8" => DATA <= x"d5fe";
when "10" & x"8a9" => DATA <= x"2423";
when "10" & x"8aa" => DATA <= x"31a8";
when "10" & x"8ab" => DATA <= x"016d";
when "10" & x"8ac" => DATA <= x"5fe0";
when "10" & x"8ad" => DATA <= x"2001";
when "10" & x"8ae" => DATA <= x"9a80";
when "10" & x"8af" => DATA <= x"1ed5";
when "10" & x"8b0" => DATA <= x"fe00";
when "10" & x"8b1" => DATA <= x"5f70";
when "10" & x"8b2" => DATA <= x"03d9";
when "10" & x"8b3" => DATA <= x"febf";
when "10" & x"8b4" => DATA <= x"0020";
when "10" & x"8b5" => DATA <= x"d08a";
when "10" & x"8b6" => DATA <= x"0003";
when "10" & x"8b7" => DATA <= x"b9de";
when "10" & x"8b8" => DATA <= x"3308";
when "10" & x"8b9" => DATA <= x"0480";
when "10" & x"8ba" => DATA <= x"9c00";
when "10" & x"8bb" => DATA <= x"0770";
when "10" & x"8bc" => DATA <= x"5003";
when "10" & x"8bd" => DATA <= x"9a80";
when "10" & x"8be" => DATA <= x"0404";
when "10" & x"8bf" => DATA <= x"0140";
when "10" & x"8c0" => DATA <= x"2012";
when "10" & x"8c1" => DATA <= x"6801";
when "10" & x"8c2" => DATA <= x"1298";
when "10" & x"8c3" => DATA <= x"0004";
when "10" & x"8c4" => DATA <= x"7a05";
when "10" & x"8c5" => DATA <= x"fe77";
when "10" & x"8c6" => DATA <= x"42bd";
when "10" & x"8c7" => DATA <= x"c060";
when "10" & x"8c8" => DATA <= x"0240";
when "10" & x"8c9" => DATA <= x"201e";
when "10" & x"8ca" => DATA <= x"4231";
when "10" & x"8cb" => DATA <= x"bfce";
when "10" & x"8cc" => DATA <= x"0000";
when "10" & x"8cd" => DATA <= x"c380";
when "10" & x"8ce" => DATA <= x"0046";
when "10" & x"8cf" => DATA <= x"603f";
when "10" & x"8d0" => DATA <= x"db80";
when "10" & x"8d1" => DATA <= x"0402";
when "10" & x"8d2" => DATA <= x"4dbe";
when "10" & x"8d3" => DATA <= x"8c44";
when "10" & x"8d4" => DATA <= x"2244";
when "10" & x"8d5" => DATA <= x"2807";
when "10" & x"8d6" => DATA <= x"9b0e";
when "10" & x"8d7" => DATA <= x"bc07";
when "10" & x"8d8" => DATA <= x"03f4";
when "10" & x"8d9" => DATA <= x"181d";
when "10" & x"8da" => DATA <= x"40b0";
when "10" & x"8db" => DATA <= x"0198";
when "10" & x"8dc" => DATA <= x"1402";
when "10" & x"8dd" => DATA <= x"407b";
when "10" & x"8de" => DATA <= x"91f0";
when "10" & x"8df" => DATA <= x"f0ef";
when "10" & x"8e0" => DATA <= x"87eb";
when "10" & x"8e1" => DATA <= x"f1fe";
when "10" & x"8e2" => DATA <= x"c723";
when "10" & x"8e3" => DATA <= x"81c0";
when "10" & x"8e4" => DATA <= x"607e";
when "10" & x"8e5" => DATA <= x"0300";
when "10" & x"8e6" => DATA <= x"a02b";
when "10" & x"8e7" => DATA <= x"fa40";
when "10" & x"8e8" => DATA <= x"11d5";
when "10" & x"8e9" => DATA <= x"1e81";
when "10" & x"8ea" => DATA <= x"a80a";
when "10" & x"8eb" => DATA <= x"00fd";
when "10" & x"8ec" => DATA <= x"f7fd";
when "10" & x"8ed" => DATA <= x"fb85";
when "10" & x"8ee" => DATA <= x"c032";
when "10" & x"8ef" => DATA <= x"e340";
when "10" & x"8f0" => DATA <= x"2000";
when "10" & x"8f1" => DATA <= x"0d0e";
when "10" & x"8f2" => DATA <= x"0783";
when "10" & x"8f3" => DATA <= x"9c00";
when "10" & x"8f4" => DATA <= x"1cde";
when "10" & x"8f5" => DATA <= x"f000";
when "10" & x"8f6" => DATA <= x"0ddf";
when "10" & x"8f7" => DATA <= x"47d4";
when "10" & x"8f8" => DATA <= x"3c3e";
when "10" & x"8f9" => DATA <= x"a001";
when "10" & x"8fa" => DATA <= x"f006";
when "10" & x"8fb" => DATA <= x"4007";
when "10" & x"8fc" => DATA <= x"880a";
when "10" & x"8fd" => DATA <= x"0040";
when "10" & x"8fe" => DATA <= x"4803";
when "10" & x"8ff" => DATA <= x"fde0";
when "10" & x"900" => DATA <= x"c0ae";
when "10" & x"901" => DATA <= x"0525";
when "10" & x"902" => DATA <= x"7257";
when "10" & x"903" => DATA <= x"3a74";
when "10" & x"904" => DATA <= x"3e5f";
when "10" & x"905" => DATA <= x"2f17";
when "10" & x"906" => DATA <= x"c3e9";
when "10" & x"907" => DATA <= x"f0eb";
when "10" & x"908" => DATA <= x"b240";
when "10" & x"909" => DATA <= x"2a00";
when "10" & x"90a" => DATA <= x"00fa";
when "10" & x"90b" => DATA <= x"72b8";
when "10" & x"90c" => DATA <= x"1f8f";
when "10" & x"90d" => DATA <= x"77a3";
when "10" & x"90e" => DATA <= x"d5e8";
when "10" & x"90f" => DATA <= x"b640";
when "10" & x"910" => DATA <= x"8041";
when "10" & x"911" => DATA <= x"a150";
when "10" & x"912" => DATA <= x"2820";
when "10" & x"913" => DATA <= x"0081";
when "10" & x"914" => DATA <= x"420a";
when "10" & x"915" => DATA <= x"0005";
when "10" & x"916" => DATA <= x"4e00";
when "10" & x"917" => DATA <= x"0108";
when "10" & x"918" => DATA <= x"8920";
when "10" & x"919" => DATA <= x"0380";
when "10" & x"91a" => DATA <= x"0426";
when "10" & x"91b" => DATA <= x"8804";
when "10" & x"91c" => DATA <= x"0415";
when "10" & x"91d" => DATA <= x"6002";
when "10" & x"91e" => DATA <= x"bd00";
when "10" & x"91f" => DATA <= x"1802";
when "10" & x"920" => DATA <= x"0002";
when "10" & x"921" => DATA <= x"e240";
when "10" & x"922" => DATA <= x"d140";
when "10" & x"923" => DATA <= x"00ca";
when "10" & x"924" => DATA <= x"004a";
when "10" & x"925" => DATA <= x"0107";
when "10" & x"926" => DATA <= x"cc0a";
when "10" & x"927" => DATA <= x"0060";
when "10" & x"928" => DATA <= x"2016";
when "10" & x"929" => DATA <= x"a006";
when "10" & x"92a" => DATA <= x"6001";
when "10" & x"92b" => DATA <= x"2010";
when "10" & x"92c" => DATA <= x"a000";
when "10" & x"92d" => DATA <= x"9001";
when "10" & x"92e" => DATA <= x"bfc0";
when "10" & x"92f" => DATA <= x"0c03";
when "10" & x"930" => DATA <= x"0300";
when "10" & x"931" => DATA <= x"0038";
when "10" & x"932" => DATA <= x"0051";
when "10" & x"933" => DATA <= x"0190";
when "10" & x"934" => DATA <= x"88ff";
when "10" & x"935" => DATA <= x"0004";
when "10" & x"936" => DATA <= x"7800";
when "10" & x"937" => DATA <= x"02f0";
when "10" & x"938" => DATA <= x"6d00";
when "10" & x"939" => DATA <= x"0ae0";
when "10" & x"93a" => DATA <= x"0a80";
when "10" & x"93b" => DATA <= x"0018";
when "10" & x"93c" => DATA <= x"4e02";
when "10" & x"93d" => DATA <= x"05e8";
when "10" & x"93e" => DATA <= x"0008";
when "10" & x"93f" => DATA <= x"0040";
when "10" & x"940" => DATA <= x"29c7";
when "10" & x"941" => DATA <= x"2134";
when "10" & x"942" => DATA <= x"7700";
when "10" & x"943" => DATA <= x"220b";
when "10" & x"944" => DATA <= x"a3f0";
when "10" & x"945" => DATA <= x"0958";
when "10" & x"946" => DATA <= x"0011";
when "10" & x"947" => DATA <= x"a030";
when "10" & x"948" => DATA <= x"1101";
when "10" & x"949" => DATA <= x"8200";
when "10" & x"94a" => DATA <= x"0870";
when "10" & x"94b" => DATA <= x"075e";
when "10" & x"94c" => DATA <= x"bf45";
when "10" & x"94d" => DATA <= x"0240";
when "10" & x"94e" => DATA <= x"20a1";
when "10" & x"94f" => DATA <= x"ccc0";
when "10" & x"950" => DATA <= x"64bb";
when "10" & x"951" => DATA <= x"cc34";
when "10" & x"952" => DATA <= x"0010";
when "10" & x"953" => DATA <= x"2000";
when "10" & x"954" => DATA <= x"02e0";
when "10" & x"955" => DATA <= x"1033";
when "10" & x"956" => DATA <= x"e190";
when "10" & x"957" => DATA <= x"a80f";
when "10" & x"958" => DATA <= x"4800";
when "10" & x"959" => DATA <= x"5002";
when "10" & x"95a" => DATA <= x"c003";
when "10" & x"95b" => DATA <= x"b808";
when "10" & x"95c" => DATA <= x"0100";
when "10" & x"95d" => DATA <= x"037c";
when "10" & x"95e" => DATA <= x"0080";
when "10" & x"95f" => DATA <= x"00a0";
when "10" & x"960" => DATA <= x"530f";
when "10" & x"961" => DATA <= x"c002";
when "10" & x"962" => DATA <= x"fb80";
when "10" & x"963" => DATA <= x"17c9";
when "10" & x"964" => DATA <= x"a578";
when "10" & x"965" => DATA <= x"017e";
when "10" & x"966" => DATA <= x"3038";
when "10" & x"967" => DATA <= x"021b";
when "10" & x"968" => DATA <= x"0fd7";
when "10" & x"969" => DATA <= x"f00c";
when "10" & x"96a" => DATA <= x"3c80";
when "10" & x"96b" => DATA <= x"a000";
when "10" & x"96c" => DATA <= x"081d";
when "10" & x"96d" => DATA <= x"6090";
when "10" & x"96e" => DATA <= x"0800";
when "10" & x"96f" => DATA <= x"6400";
when "10" & x"970" => DATA <= x"220f";
when "10" & x"971" => DATA <= x"d000";
when "10" & x"972" => DATA <= x"1018";
when "10" & x"973" => DATA <= x"0404";
when "10" & x"974" => DATA <= x"063e";
when "10" & x"975" => DATA <= x"2800";
when "10" & x"976" => DATA <= x"c000";
when "10" & x"977" => DATA <= x"7850";
when "10" & x"978" => DATA <= x"03fc";
when "10" & x"979" => DATA <= x"1c10";
when "10" & x"97a" => DATA <= x"0250";
when "10" & x"97b" => DATA <= x"0260";
when "10" & x"97c" => DATA <= x"61dc";
when "10" & x"97d" => DATA <= x"6fc7";
when "10" & x"97e" => DATA <= x"8b82";
when "10" & x"97f" => DATA <= x"8018";
when "10" & x"980" => DATA <= x"1440";
when "10" & x"981" => DATA <= x"0804";
when "10" & x"982" => DATA <= x"bbc0";
when "10" & x"983" => DATA <= x"0200";
when "10" & x"984" => DATA <= x"0801";
when "10" & x"985" => DATA <= x"0000";
when "10" & x"986" => DATA <= x"4005";
when "10" & x"987" => DATA <= x"c03c";
when "10" & x"988" => DATA <= x"0088";
when "10" & x"989" => DATA <= x"403e";
when "10" & x"98a" => DATA <= x"000c";
when "10" & x"98b" => DATA <= x"0407";
when "10" & x"98c" => DATA <= x"241b";
when "10" & x"98d" => DATA <= x"9fe3";
when "10" & x"98e" => DATA <= x"2020";
when "10" & x"98f" => DATA <= x"0002";
when "10" & x"990" => DATA <= x"2108";
when "10" & x"991" => DATA <= x"001f";
when "10" & x"992" => DATA <= x"e0ee";
when "10" & x"993" => DATA <= x"0023";
when "10" & x"994" => DATA <= x"9201";
when "10" & x"995" => DATA <= x"0ff0";
when "10" & x"996" => DATA <= x"0024";
when "10" & x"997" => DATA <= x"07c1";
when "10" & x"998" => DATA <= x"00a0";
when "10" & x"999" => DATA <= x"0a82";
when "10" & x"99a" => DATA <= x"8014";
when "10" & x"99b" => DATA <= x"1400";
when "10" & x"99c" => DATA <= x"c000";
when "10" & x"99d" => DATA <= x"0044";
when "10" & x"99e" => DATA <= x"c042";
when "10" & x"99f" => DATA <= x"1d00";
when "10" & x"9a0" => DATA <= x"3fe4";
when "10" & x"9a1" => DATA <= x"0025";
when "10" & x"9a2" => DATA <= x"200c";
when "10" & x"9a3" => DATA <= x"0240";
when "10" & x"9a4" => DATA <= x"2000";
when "10" & x"9a5" => DATA <= x"0ee0";
when "10" & x"9a6" => DATA <= x"01a5";
when "10" & x"9a7" => DATA <= x"0010";
when "10" & x"9a8" => DATA <= x"827c";
when "10" & x"9a9" => DATA <= x"007d";
when "10" & x"9aa" => DATA <= x"580c";
when "10" & x"9ab" => DATA <= x"000d";
when "10" & x"9ac" => DATA <= x"5125";
when "10" & x"9ad" => DATA <= x"0032";
when "10" & x"9ae" => DATA <= x"4008";
when "10" & x"9af" => DATA <= x"0623";
when "10" & x"9b0" => DATA <= x"7f80";
when "10" & x"9b1" => DATA <= x"1c4e";
when "10" & x"9b2" => DATA <= x"061b";
when "10" & x"9b3" => DATA <= x"f501";
when "10" & x"9b4" => DATA <= x"c01c";
when "10" & x"9b5" => DATA <= x"3eff";
when "10" & x"9b6" => DATA <= x"7cd7";
when "10" & x"9b7" => DATA <= x"c578";
when "10" & x"9b8" => DATA <= x"3e1e";
when "10" & x"9b9" => DATA <= x"0231";
when "10" & x"9ba" => DATA <= x"ef0e";
when "10" & x"9bb" => DATA <= x"80c5";
when "10" & x"9bc" => DATA <= x"609f";
when "10" & x"9bd" => DATA <= x"00a0";
when "10" & x"9be" => DATA <= x"0024";
when "10" & x"9bf" => DATA <= x"8001";
when "10" & x"9c0" => DATA <= x"3c02";
when "10" & x"9c1" => DATA <= x"803c";
when "10" & x"9c2" => DATA <= x"1c0e";
when "10" & x"9c3" => DATA <= x"0e27";
when "10" & x"9c4" => DATA <= x"0780";
when "10" & x"9c5" => DATA <= x"406a";
when "10" & x"9c6" => DATA <= x"0e05";
when "10" & x"9c7" => DATA <= x"7805";
when "10" & x"9c8" => DATA <= x"0051";
when "10" & x"9c9" => DATA <= x"4500";
when "10" & x"9ca" => DATA <= x"0a94";
when "10" & x"9cb" => DATA <= x"1c00";
when "10" & x"9cc" => DATA <= x"42a0";
when "10" & x"9cd" => DATA <= x"0204";
when "10" & x"9ce" => DATA <= x"8004";
when "10" & x"9cf" => DATA <= x"2800";
when "10" & x"9d0" => DATA <= x"2140";
when "10" & x"9d1" => DATA <= x"0040";
when "10" & x"9d2" => DATA <= x"6012";
when "10" & x"9d3" => DATA <= x"8300";
when "10" & x"9d4" => DATA <= x"9419";
when "10" & x"9d5" => DATA <= x"e000";
when "10" & x"9d6" => DATA <= x"0b01";
when "10" & x"9d7" => DATA <= x"0180";
when "10" & x"9d8" => DATA <= x"6800";
when "10" & x"9d9" => DATA <= x"83c0";
when "10" & x"9da" => DATA <= x"010e";
when "10" & x"9db" => DATA <= x"0000";
when "10" & x"9dc" => DATA <= x"e801";
when "10" & x"9dd" => DATA <= x"8000";
when "10" & x"9de" => DATA <= x"02e0";
when "10" & x"9df" => DATA <= x"0040";
when "10" & x"9e0" => DATA <= x"0103";
when "10" & x"9e1" => DATA <= x"a00c";
when "10" & x"9e2" => DATA <= x"0005";
when "10" & x"9e3" => DATA <= x"71bf";
when "10" & x"9e4" => DATA <= x"dde8";
when "10" & x"9e5" => DATA <= x"f7fa";
when "10" & x"9e6" => DATA <= x"7dfe";
when "10" & x"9e7" => DATA <= x"ef37";
when "10" & x"9e8" => DATA <= x"bbdf";
when "10" & x"9e9" => DATA <= x"e0f3";
when "10" & x"9ea" => DATA <= x"7950";
when "10" & x"9eb" => DATA <= x"6ef8";
when "10" & x"9ec" => DATA <= x"7c8c";
when "10" & x"9ed" => DATA <= x"9f13";
when "10" & x"9ee" => DATA <= x"f340";
when "10" & x"9ef" => DATA <= x"7586";
when "10" & x"9f0" => DATA <= x"c7a0";
when "10" & x"9f1" => DATA <= x"303b";
when "10" & x"9f2" => DATA <= x"edfc";
when "10" & x"9f3" => DATA <= x"ff07";
when "10" & x"9f4" => DATA <= x"8058";
when "10" & x"9f5" => DATA <= x"15fc";
when "10" & x"9f6" => DATA <= x"9200";
when "10" & x"9f7" => DATA <= x"80d0";
when "10" & x"9f8" => DATA <= x"08e4";
when "10" & x"9f9" => DATA <= x"7a1d";
when "10" & x"9fa" => DATA <= x"0007";
when "10" & x"9fb" => DATA <= x"0030";
when "10" & x"9fc" => DATA <= x"377c";
when "10" & x"9fd" => DATA <= x"00f0";
when "10" & x"9fe" => DATA <= x"bf70";
when "10" & x"9ff" => DATA <= x"0146";
when "10" & x"a00" => DATA <= x"dc43";
when "10" & x"a01" => DATA <= x"943c";
when "10" & x"a02" => DATA <= x"1c0f";
when "10" & x"a03" => DATA <= x"70e3";
when "10" & x"a04" => DATA <= x"bebf";
when "10" & x"a05" => DATA <= x"f7bc";
when "10" & x"a06" => DATA <= x"7d47";
when "10" & x"a07" => DATA <= x"fa7c";
when "10" & x"a08" => DATA <= x"1f7f";
when "10" & x"a09" => DATA <= x"f00a";
when "10" & x"a0a" => DATA <= x"e280";
when "10" & x"a0b" => DATA <= x"4c00";
when "10" & x"a0c" => DATA <= x"3e00";
when "10" & x"a0d" => DATA <= x"66d0";
when "10" & x"a0e" => DATA <= x"0570";
when "10" & x"a0f" => DATA <= x"301c";
when "10" & x"a10" => DATA <= x"0804";
when "10" & x"a11" => DATA <= x"ea01";
when "10" & x"a12" => DATA <= x"c123";
when "10" & x"a13" => DATA <= x"e1b0";
when "10" & x"a14" => DATA <= x"fb6d";
when "10" & x"a15" => DATA <= x"be00";
when "10" & x"a16" => DATA <= x"4000";
when "10" & x"a17" => DATA <= x"008d";
when "10" & x"a18" => DATA <= x"4edc";
when "10" & x"a19" => DATA <= x"7fbd";
when "10" & x"a1a" => DATA <= x"3bf1";
when "10" & x"a1b" => DATA <= x"faf4";
when "10" & x"a1c" => DATA <= x"7a81";
when "10" & x"a1d" => DATA <= x"000f";
when "10" & x"a1e" => DATA <= x"f017";
when "10" & x"a1f" => DATA <= x"0180";
when "10" & x"a20" => DATA <= x"0040";
when "10" & x"a21" => DATA <= x"073b";
when "10" & x"a22" => DATA <= x"c2c0";
when "10" & x"a23" => DATA <= x"1fa0";
when "10" & x"a24" => DATA <= x"5a04";
when "10" & x"a25" => DATA <= x"0101";
when "10" & x"a26" => DATA <= x"00c0";
when "10" & x"a27" => DATA <= x"01b9";
when "10" & x"a28" => DATA <= x"02c0";
when "10" & x"a29" => DATA <= x"17e1";
when "10" & x"a2a" => DATA <= x"ba08";
when "10" & x"a2b" => DATA <= x"0270";
when "10" & x"a2c" => DATA <= x"013d";
when "10" & x"a2d" => DATA <= x"0160";
when "10" & x"a2e" => DATA <= x"0ee1";
when "10" & x"a2f" => DATA <= x"7d10";
when "10" & x"a30" => DATA <= x"0404";
when "10" & x"a31" => DATA <= x"0300";
when "10" & x"a32" => DATA <= x"02fc";
when "10" & x"a33" => DATA <= x"0022";
when "10" & x"a34" => DATA <= x"0008";
when "10" & x"a35" => DATA <= x"3801";
when "10" & x"a36" => DATA <= x"b8da";
when "10" & x"a37" => DATA <= x"2110";
when "10" & x"a38" => DATA <= x"045c";
when "10" & x"a39" => DATA <= x"007d";
when "10" & x"a3a" => DATA <= x"f003";
when "10" & x"a3b" => DATA <= x"d892";
when "10" & x"a3c" => DATA <= x"8010";
when "10" & x"a3d" => DATA <= x"0004";
when "10" & x"a3e" => DATA <= x"0001";
when "10" & x"a3f" => DATA <= x"efc0";
when "10" & x"a40" => DATA <= x"2000";
when "10" & x"a41" => DATA <= x"0d00";
when "10" & x"a42" => DATA <= x"3d5a";
when "10" & x"a43" => DATA <= x"1400";
when "10" & x"a44" => DATA <= x"11e0";
when "10" & x"a45" => DATA <= x"07f8";
when "10" & x"a46" => DATA <= x"1a80";
when "10" & x"a47" => DATA <= x"8020";
when "10" & x"a48" => DATA <= x"0010";
when "10" & x"a49" => DATA <= x"0136";
when "10" & x"a4a" => DATA <= x"e0b0";
when "10" & x"a4b" => DATA <= x"07d8";
when "10" & x"a4c" => DATA <= x"2682";
when "10" & x"a4d" => DATA <= x"0080";
when "10" & x"a4e" => DATA <= x"8020";
when "10" & x"a4f" => DATA <= x"005e";
when "10" & x"a50" => DATA <= x"c0b0";
when "10" & x"a51" => DATA <= x"07b8";
when "10" & x"a52" => DATA <= x"5a84";
when "10" & x"a53" => DATA <= x"1d01";
when "10" & x"a54" => DATA <= x"000a";
when "10" & x"a55" => DATA <= x"a002";
when "10" & x"a56" => DATA <= x"0701";
when "10" & x"a57" => DATA <= x"0000";
when "10" & x"a58" => DATA <= x"2000";
when "10" & x"a59" => DATA <= x"8060";
when "10" & x"a5a" => DATA <= x"07c0";
when "10" & x"a5b" => DATA <= x"0ff1";
when "10" & x"a5c" => DATA <= x"cd80";
when "10" & x"a5d" => DATA <= x"3fc0";
when "10" & x"a5e" => DATA <= x"4007";
when "10" & x"a5f" => DATA <= x"09e4";
when "10" & x"a60" => DATA <= x"5143";
when "10" & x"a61" => DATA <= x"0732";
when "10" & x"a62" => DATA <= x"61c0";
when "10" & x"a63" => DATA <= x"e280";
when "10" & x"a64" => DATA <= x"380c";
when "10" & x"a65" => DATA <= x"0e0f";
when "10" & x"a66" => DATA <= x"0e00";
when "10" & x"a67" => DATA <= x"7ff0";
when "10" & x"a68" => DATA <= x"200c";
when "10" & x"a69" => DATA <= x"0802";
when "10" & x"a6a" => DATA <= x"0025";
when "10" & x"a6b" => DATA <= x"c814";
when "10" & x"a6c" => DATA <= x"0040";
when "10" & x"a6d" => DATA <= x"e005";
when "10" & x"a6e" => DATA <= x"d86e";
when "10" & x"a6f" => DATA <= x"8200";
when "10" & x"a70" => DATA <= x"808a";
when "10" & x"a71" => DATA <= x"0027";
when "10" & x"a72" => DATA <= x"a02c";
when "10" & x"a73" => DATA <= x"01dc";
when "10" & x"a74" => DATA <= x"2fa2";
when "10" & x"a75" => DATA <= x"0080";
when "10" & x"a76" => DATA <= x"0060";
when "10" & x"a77" => DATA <= x"007f";
when "10" & x"a78" => DATA <= x"d801";
when "10" & x"a79" => DATA <= x"01f8";
when "10" & x"a7a" => DATA <= x"dba4";
when "10" & x"a7b" => DATA <= x"0101";
when "10" & x"a7c" => DATA <= x"0280";
when "10" & x"a7d" => DATA <= x"0fbe";
when "10" & x"a7e" => DATA <= x"00f3";
when "10" & x"a7f" => DATA <= x"5a50";
when "10" & x"a80" => DATA <= x"0200";
when "10" & x"a81" => DATA <= x"0080";
when "10" & x"a82" => DATA <= x"003f";
when "10" & x"a83" => DATA <= x"f806";
when "10" & x"a84" => DATA <= x"8000";
when "10" & x"a85" => DATA <= x"2007";
when "10" & x"a86" => DATA <= x"2b62";
when "10" & x"a87" => DATA <= x"c01f";
when "10" & x"a88" => DATA <= x"fc04";
when "10" & x"a89" => DATA <= x"0501";
when "10" & x"a8a" => DATA <= x"0040";
when "10" & x"a8b" => DATA <= x"0fb5";
when "10" & x"a8c" => DATA <= x"0580";
when "10" & x"a8d" => DATA <= x"36c1";
when "10" & x"a8e" => DATA <= x"b410";
when "10" & x"a8f" => DATA <= x"04e0";
when "10" & x"a90" => DATA <= x"01f9";
when "10" & x"a91" => DATA <= x"02c0";
when "10" & x"a92" => DATA <= x"1ee1";
when "10" & x"a93" => DATA <= x"6a10";
when "10" & x"a94" => DATA <= x"0404";
when "10" & x"a95" => DATA <= x"0300";
when "10" & x"a96" => DATA <= x"06ff";
when "10" & x"a97" => DATA <= x"803f";
when "10" & x"a98" => DATA <= x"cdb4";
when "10" & x"a99" => DATA <= x"4120";
when "10" & x"a9a" => DATA <= x"0ffd";
when "10" & x"a9b" => DATA <= x"0006";
when "10" & x"a9c" => DATA <= x"0017";
when "10" & x"a9d" => DATA <= x"3501";
when "10" & x"a9e" => DATA <= x"4008";
when "10" & x"a9f" => DATA <= x"04f0";
when "10" & x"aa0" => DATA <= x"7bbf";
when "10" & x"aa1" => DATA <= x"a9f8";
when "10" & x"aa2" => DATA <= x"eaf0";
when "10" & x"aa3" => DATA <= x"7f1f";
when "10" & x"aa4" => DATA <= x"c1e0";
when "10" & x"aa5" => DATA <= x"1e00";
when "10" & x"aa6" => DATA <= x"a69a";
when "10" & x"aa7" => DATA <= x"0834";
when "10" & x"aa8" => DATA <= x"0200";
when "10" & x"aa9" => DATA <= x"030f";
when "10" & x"aaa" => DATA <= x"0000";
when "10" & x"aab" => DATA <= x"5025";
when "10" & x"aac" => DATA <= x"0001";
when "10" & x"aad" => DATA <= x"3801";
when "10" & x"aae" => DATA <= x"81c0";
when "10" & x"aaf" => DATA <= x"040e";
when "10" & x"ab0" => DATA <= x"0007";
when "10" & x"ab1" => DATA <= x"f839";
when "10" & x"ab2" => DATA <= x"203d";
when "10" & x"ab3" => DATA <= x"41c0";
when "10" & x"ab4" => DATA <= x"a0f5";
when "10" & x"ab5" => DATA <= x"0778";
when "10" & x"ab6" => DATA <= x"0000";
when "10" & x"ab7" => DATA <= x"54aa";
when "10" & x"ab8" => DATA <= x"0008";
when "10" & x"ab9" => DATA <= x"000a";
when "10" & x"aba" => DATA <= x"8a00";
when "10" & x"abb" => DATA <= x"2006";
when "10" & x"abc" => DATA <= x"3800";
when "10" & x"abd" => DATA <= x"8140";
when "10" & x"abe" => DATA <= x"0140";
when "10" & x"abf" => DATA <= x"8700";
when "10" & x"ac0" => DATA <= x"0428";
when "10" & x"ac1" => DATA <= x"000d";
when "10" & x"ac2" => DATA <= x"4180";
when "10" & x"ac3" => DATA <= x"4a0c";
when "10" & x"ac4" => DATA <= x"0203";
when "10" & x"ac5" => DATA <= x"3c00";
when "10" & x"ac6" => DATA <= x"0140";
when "10" & x"ac7" => DATA <= x"203d";
when "10" & x"ac8" => DATA <= x"0128";
when "10" & x"ac9" => DATA <= x"7000";
when "10" & x"aca" => DATA <= x"07c0";
when "10" & x"acb" => DATA <= x"2400";
when "10" & x"acc" => DATA <= x"0540";
when "10" & x"acd" => DATA <= x"0081";
when "10" & x"ace" => DATA <= x"1680";
when "10" & x"acf" => DATA <= x"2024";
when "10" & x"ad0" => DATA <= x"0101";
when "10" & x"ad1" => DATA <= x"5fe9";
when "10" & x"ad2" => DATA <= x"f7ff";
when "10" & x"ad3" => DATA <= x"6fa7";
when "10" & x"ad4" => DATA <= x"def4";
when "10" & x"ad5" => DATA <= x"2fbe";
when "10" & x"ad6" => DATA <= x"ef6a";
when "10" & x"ad7" => DATA <= x"ff7f";
when "10" & x"ad8" => DATA <= x"3e1b";
when "10" & x"ad9" => DATA <= x"0187";
when "10" & x"ada" => DATA <= x"c681";
when "10" & x"adb" => DATA <= x"d61b";
when "10" & x"adc" => DATA <= x"1e40";
when "10" & x"add" => DATA <= x"1fcf";
when "10" & x"ade" => DATA <= x"f078";
when "10" & x"adf" => DATA <= x"0100";
when "10" & x"ae0" => DATA <= x"00a8";
when "10" & x"ae1" => DATA <= x"0408";
when "10" & x"ae2" => DATA <= x"0c00";
when "10" & x"ae3" => DATA <= x"8cad";
when "10" & x"ae4" => DATA <= x"faff";
when "10" & x"ae5" => DATA <= x"0180";
when "10" & x"ae6" => DATA <= x"1a0d";
when "10" & x"ae7" => DATA <= x"faf7";
when "10" & x"ae8" => DATA <= x"7f80";
when "10" & x"ae9" => DATA <= x"d800";
when "10" & x"aea" => DATA <= x"0af7";
when "10" & x"aeb" => DATA <= x"38d0";
when "10" & x"aec" => DATA <= x"0800";
when "10" & x"aed" => DATA <= x"0200";
when "10" & x"aee" => DATA <= x"009c";
when "10" & x"aef" => DATA <= x"7800";
when "10" & x"af0" => DATA <= x"3c1c";
when "10" & x"af1" => DATA <= x"e1e7";
when "10" & x"af2" => DATA <= x"7d00";
when "10" & x"af3" => DATA <= x"3beb";
when "10" & x"af4" => DATA <= x"febb";
when "10" & x"af5" => DATA <= x"c7d4";
when "10" & x"af6" => DATA <= x"01c7";
when "10" & x"af7" => DATA <= x"e3e0";
when "10" & x"af8" => DATA <= x"f005";
when "10" & x"af9" => DATA <= x"8000";
when "10" & x"afa" => DATA <= x"1e3f";
when "10" & x"afb" => DATA <= x"2401";
when "10" & x"afc" => DATA <= x"fe70";
when "10" & x"afd" => DATA <= x"4003";
when "10" & x"afe" => DATA <= x"f801";
when "10" & x"aff" => DATA <= x"815c";
when "10" & x"b00" => DATA <= x"0e77";
when "10" & x"b01" => DATA <= x"3572";
when "10" & x"b02" => DATA <= x"292b";
when "10" & x"b03" => DATA <= x"7c3e";
when "10" & x"b04" => DATA <= x"dde1";
when "10" & x"b05" => DATA <= x"f4f5";
when "10" & x"b06" => DATA <= x"7a3f";
when "10" & x"b07" => DATA <= x"2a70";
when "10" & x"b08" => DATA <= x"2815";
when "10" & x"b09" => DATA <= x"4a3f";
when "10" & x"b0a" => DATA <= x"5ecf";
when "10" & x"b0b" => DATA <= x"faf7";
when "10" & x"b0c" => DATA <= x"7ed7";
when "10" & x"b0d" => DATA <= x"ff80";
when "10" & x"b0e" => DATA <= x"7804";
when "10" & x"b0f" => DATA <= x"8050";
when "10" & x"b10" => DATA <= x"2002";
when "10" & x"b11" => DATA <= x"813c";
when "10" & x"b12" => DATA <= x"03c0";
when "10" & x"b13" => DATA <= x"3c02";
when "10" & x"b14" => DATA <= x"c004";
when "10" & x"b15" => DATA <= x"1401";
when "10" & x"b16" => DATA <= x"441e";
when "10" & x"b17" => DATA <= x"01e0";
when "10" & x"b18" => DATA <= x"1e01";
when "10" & x"b19" => DATA <= x"e01e";
when "10" & x"b1a" => DATA <= x"01c0";
when "10" & x"b1b" => DATA <= x"001f";
when "10" & x"b1c" => DATA <= x"00f0";
when "10" & x"b1d" => DATA <= x"0f00";
when "10" & x"b1e" => DATA <= x"f000";
when "10" & x"b1f" => DATA <= x"4780";
when "10" & x"b20" => DATA <= x"7800";
when "10" & x"b21" => DATA <= x"0021";
when "10" & x"b22" => DATA <= x"4001";
when "10" & x"b23" => DATA <= x"0b00";
when "10" & x"b24" => DATA <= x"0470";
when "10" & x"b25" => DATA <= x"0064";
when "10" & x"b26" => DATA <= x"6239";
when "10" & x"b27" => DATA <= x"04d1";
when "10" & x"b28" => DATA <= x"c864";
when "10" & x"b29" => DATA <= x"3b20";
when "10" & x"b2a" => DATA <= x"040e";
when "10" & x"b2b" => DATA <= x"0022";
when "10" & x"b2c" => DATA <= x"5269";
when "10" & x"b2d" => DATA <= x"1293";
when "10" & x"b2e" => DATA <= x"4884";
when "10" & x"b2f" => DATA <= x"df00";
when "10" & x"b30" => DATA <= x"f00f";
when "10" & x"b31" => DATA <= x"00f0";
when "10" & x"b32" => DATA <= x"0000";
when "10" & x"b33" => DATA <= x"23c0";
when "10" & x"b34" => DATA <= x"3400";
when "10" & x"b35" => DATA <= x"4140";
when "10" & x"b36" => DATA <= x"020f";
when "10" & x"b37" => DATA <= x"00f0";
when "10" & x"b38" => DATA <= x"0001";
when "10" & x"b39" => DATA <= x"03c0";
when "10" & x"b3a" => DATA <= x"3c03";
when "10" & x"b3b" => DATA <= x"c03c";
when "10" & x"b3c" => DATA <= x"03c0";
when "10" & x"b3d" => DATA <= x"0000";
when "10" & x"b3e" => DATA <= x"2a00";
when "10" & x"b3f" => DATA <= x"0178";
when "10" & x"b40" => DATA <= x"0780";
when "10" & x"b41" => DATA <= x"7807";
when "10" & x"b42" => DATA <= x"8004";
when "10" & x"b43" => DATA <= x"2802";
when "10" & x"b44" => DATA <= x"843c";
when "10" & x"b45" => DATA <= x"03c0";
when "10" & x"b46" => DATA <= x"3c02";
when "10" & x"b47" => DATA <= x"403e";
when "10" & x"b48" => DATA <= x"0101";
when "10" & x"b49" => DATA <= x"2f94";
when "10" & x"b4a" => DATA <= x"fa7c";
when "10" & x"b4b" => DATA <= x"3ed6";
when "10" & x"b4c" => DATA <= x"03e1";
when "10" & x"b4d" => DATA <= x"b0f8";
when "10" & x"b4e" => DATA <= x"7857";
when "10" & x"b4f" => DATA <= x"c06c";
when "10" & x"b50" => DATA <= x"f743";
when "10" & x"b51" => DATA <= x"74f6";
when "10" & x"b52" => DATA <= x"1b1d";
when "10" & x"b53" => DATA <= x"f805";
when "10" & x"b54" => DATA <= x"0001";
when "10" & x"b55" => DATA <= x"2802";
when "10" & x"b56" => DATA <= x"8100";
when "10" & x"b57" => DATA <= x"0040";
when "10" & x"b58" => DATA <= x"0103";
when "10" & x"b59" => DATA <= x"8008";
when "10" & x"b5a" => DATA <= x"1400";
when "10" & x"b5b" => DATA <= x"0707";
when "10" & x"b5c" => DATA <= x"f038";
when "10" & x"b5d" => DATA <= x"3e81";
when "10" & x"b5e" => DATA <= x"c1d4";
when "10" & x"b5f" => DATA <= x"0002";
when "10" & x"b60" => DATA <= x"2f10";
when "10" & x"b61" => DATA <= x"0040";
when "10" & x"b62" => DATA <= x"ef00";
when "10" & x"b63" => DATA <= x"008a";
when "10" & x"b64" => DATA <= x"a801";
when "10" & x"b65" => DATA <= x"4028";
when "10" & x"b66" => DATA <= x"5500";
when "10" & x"b67" => DATA <= x"1504";
when "10" & x"b68" => DATA <= x"0e00";
when "10" & x"b69" => DATA <= x"a400";
when "10" & x"b6a" => DATA <= x"0100";
when "10" & x"b6b" => DATA <= x"ab40";
when "10" & x"b6c" => DATA <= x"0140";
when "10" & x"b6d" => DATA <= x"8054";
when "10" & x"b6e" => DATA <= x"0054";
when "10" & x"b6f" => DATA <= x"0203";
when "10" & x"b70" => DATA <= x"b830";
when "10" & x"b71" => DATA <= x"1c04";
when "10" & x"b72" => DATA <= x"0670";
when "10" & x"b73" => DATA <= x"0202";
when "10" & x"b74" => DATA <= x"4028";
when "10" & x"b75" => DATA <= x"0400";
when "10" & x"b76" => DATA <= x"03a0";
when "10" & x"b77" => DATA <= x"1005";
when "10" & x"b78" => DATA <= x"0080";
when "10" & x"b79" => DATA <= x"0025";
when "10" & x"b7a" => DATA <= x"4a00";
when "10" & x"b7b" => DATA <= x"0080";
when "10" & x"b7c" => DATA <= x"0020";
when "10" & x"b7d" => DATA <= x"000a";
when "10" & x"b7e" => DATA <= x"8280";
when "10" & x"b7f" => DATA <= x"0020";
when "10" & x"b80" => DATA <= x"0510";
when "10" & x"b81" => DATA <= x"0104";
when "10" & x"b82" => DATA <= x"2a10";
when "10" & x"b83" => DATA <= x"0000";
when "10" & x"b84" => DATA <= x"4000";
when "10" & x"b85" => DATA <= x"8000";
when "10" & x"b86" => DATA <= x"20c0";
when "10" & x"b87" => DATA <= x"a000";
when "10" & x"b88" => DATA <= x"8203";
when "10" & x"b89" => DATA <= x"8fc3";
when "10" & x"b8a" => DATA <= x"f47e";
when "10" & x"b8b" => DATA <= x"bf4f";
when "10" & x"b8c" => DATA <= x"810e";
when "10" & x"b8d" => DATA <= x"e040";
when "10" & x"b8e" => DATA <= x"ba5c";
when "10" & x"b8f" => DATA <= x"2cc5";
when "10" & x"b90" => DATA <= x"47be";
when "10" & x"b91" => DATA <= x"5f0f";
when "10" & x"b92" => DATA <= x"9048";
when "10" & x"b93" => DATA <= x"1dfc";
when "10" & x"b94" => DATA <= x"ff3f";
when "10" & x"b95" => DATA <= x"80d8";
when "10" & x"b96" => DATA <= x"740e";
when "10" & x"b97" => DATA <= x"4001";
when "10" & x"b98" => DATA <= x"81c4";
when "10" & x"b99" => DATA <= x"0c07";
when "10" & x"b9a" => DATA <= x"fbf9";
when "10" & x"b9b" => DATA <= x"bc00";
when "10" & x"b9c" => DATA <= x"0230";
when "10" & x"b9d" => DATA <= x"1c15";
when "10" & x"b9e" => DATA <= x"1e81";
when "10" & x"b9f" => DATA <= x"4900";
when "10" & x"ba0" => DATA <= x"100f";
when "10" & x"ba1" => DATA <= x"77fe";
when "10" & x"ba2" => DATA <= x"efbf";
when "10" & x"ba3" => DATA <= x"d40f";
when "10" & x"ba4" => DATA <= x"fdf7";
when "10" & x"ba5" => DATA <= x"7f80";
when "10" & x"ba6" => DATA <= x"1fe7";
when "10" & x"ba7" => DATA <= x"118c";
when "10" & x"ba8" => DATA <= x"b89c";
when "10" & x"ba9" => DATA <= x"0e34";
when "10" & x"baa" => DATA <= x"3d43";
when "10" & x"bab" => DATA <= x"9c00";
when "10" & x"bac" => DATA <= x"1e9e";
when "10" & x"bad" => DATA <= x"fa00";
when "10" & x"bae" => DATA <= x"77bf";
when "10" & x"baf" => DATA <= x"d3c1";
when "10" & x"bb0" => DATA <= x"ea3e";
when "10" & x"bb1" => DATA <= x"a001";
when "10" & x"bb2" => DATA <= x"f0fc";
when "10" & x"bb3" => DATA <= x"77c0";
when "10" & x"bb4" => DATA <= x"0f80";
when "10" & x"bb5" => DATA <= x"003d";
when "10" & x"bb6" => DATA <= x"feef";
when "10" & x"bb7" => DATA <= x"e007";
when "10" & x"bb8" => DATA <= x"fbc0";
when "10" & x"bb9" => DATA <= x"8007";
when "10" & x"bba" => DATA <= x"7629";
when "10" & x"bbb" => DATA <= x"2b92";
when "10" & x"bbc" => DATA <= x"b9dc";
when "10" & x"bbd" => DATA <= x"0f00";
when "10" & x"bbe" => DATA <= x"fa78";
when "10" & x"bbf" => DATA <= x"3e9f";
when "10" & x"bc0" => DATA <= x"0f87";
when "10" & x"bc1" => DATA <= x"13e1";
when "10" & x"bc2" => DATA <= x"f4a2";
when "10" & x"bc3" => DATA <= x"543a";
when "10" & x"bc4" => DATA <= x"15a9";
when "10" & x"bc5" => DATA <= x"448a";
when "10" & x"bc6" => DATA <= x"51fe";
when "10" & x"bc7" => DATA <= x"fdaf";
when "10" & x"bc8" => DATA <= x"f7a3";
when "10" & x"bc9" => DATA <= x"c1ea";
when "10" & x"bca" => DATA <= x"f490";
when "10" & x"bcb" => DATA <= x"0187";
when "10" & x"bcc" => DATA <= x"8020";
when "10" & x"bcd" => DATA <= x"3800";
when "10" & x"bce" => DATA <= x"09a0";
when "10" & x"bcf" => DATA <= x"004f";
when "10" & x"bd0" => DATA <= x"00f0";
when "10" & x"bd1" => DATA <= x"0f00";
when "10" & x"bd2" => DATA <= x"9001";
when "10" & x"bd3" => DATA <= x"0680";
when "10" & x"bd4" => DATA <= x"0834";
when "10" & x"bd5" => DATA <= x"0005";
when "10" & x"bd6" => DATA <= x"e000";
when "10" & x"bd7" => DATA <= x"8f00";
when "10" & x"bd8" => DATA <= x"f00f";
when "10" & x"bd9" => DATA <= x"00f0";
when "10" & x"bda" => DATA <= x"0e00";
when "10" & x"bdb" => DATA <= x"2078";
when "10" & x"bdc" => DATA <= x"0043";
when "10" & x"bdd" => DATA <= x"c03c";
when "10" & x"bde" => DATA <= x"0380";
when "10" & x"bdf" => DATA <= x"011e";
when "10" & x"be0" => DATA <= x"01e0";
when "10" & x"be1" => DATA <= x"0000";
when "10" & x"be2" => DATA <= x"8780";
when "10" & x"be3" => DATA <= x"5000";
when "10" & x"be4" => DATA <= x"26a6";
when "10" & x"be5" => DATA <= x"4320";
when "10" & x"be6" => DATA <= x"1a39";
when "10" & x"be7" => DATA <= x"04d8";
when "10" & x"be8" => DATA <= x"0008";
when "10" & x"be9" => DATA <= x"0045";
when "10" & x"bea" => DATA <= x"a4c2";
when "10" & x"beb" => DATA <= x"6902";
when "10" & x"bec" => DATA <= x"9348";
when "10" & x"bed" => DATA <= x"9200";
when "10" & x"bee" => DATA <= x"0ff0";
when "10" & x"bef" => DATA <= x"0a00";
when "10" & x"bf0" => DATA <= x"0278";
when "10" & x"bf1" => DATA <= x"0500";
when "10" & x"bf2" => DATA <= x"5045";
when "10" & x"bf3" => DATA <= x"0006";
when "10" & x"bf4" => DATA <= x"3c03";
when "10" & x"bf5" => DATA <= x"c000";
when "10" & x"bf6" => DATA <= x"030f";
when "10" & x"bf7" => DATA <= x"00f0";
when "10" & x"bf8" => DATA <= x"0003";
when "10" & x"bf9" => DATA <= x"0000";
when "10" & x"bfa" => DATA <= x"40f0";
when "10" & x"bfb" => DATA <= x"0b00";
when "10" & x"bfc" => DATA <= x"4078";
when "10" & x"bfd" => DATA <= x"0007";
when "10" & x"bfe" => DATA <= x"c024";
when "10" & x"bff" => DATA <= x"0280";
when "10" & x"c00" => DATA <= x"a800";
when "10" & x"c01" => DATA <= x"0c00";
when "10" & x"c02" => DATA <= x"0178";
when "10" & x"c03" => DATA <= x"0580";
when "10" & x"c04" => DATA <= x"033c";
when "10" & x"c05" => DATA <= x"0240";
when "10" & x"c06" => DATA <= x"021c";
when "10" & x"c07" => DATA <= x"0038";
when "10" & x"c08" => DATA <= x"0004";
when "10" & x"c09" => DATA <= x"3c02";
when "10" & x"c0a" => DATA <= x"c00c";
when "10" & x"c0b" => DATA <= x"1e01";
when "10" & x"c0c" => DATA <= x"201f";
when "10" & x"c0d" => DATA <= x"0080";
when "10" & x"c0e" => DATA <= x"3e9f";
when "10" & x"c0f" => DATA <= x"0e9c";
when "10" & x"c10" => DATA <= x"f94f";
when "10" & x"c11" => DATA <= x"b5f1";
when "10" & x"c12" => DATA <= x"5b15";
when "10" & x"c13" => DATA <= x"f0f0";
when "10" & x"c14" => DATA <= x"6c50";
when "10" & x"c15" => DATA <= x"d82c";
when "10" & x"c16" => DATA <= x"363b";
when "10" & x"c17" => DATA <= x"159a";
when "10" & x"c18" => DATA <= x"c77e";
when "10" & x"c19" => DATA <= x"01a0";
when "10" & x"c1a" => DATA <= x"0040";
when "10" & x"c1b" => DATA <= x"0502";
when "10" & x"c1c" => DATA <= x"5801";
when "10" & x"c1d" => DATA <= x"0001";
when "10" & x"c1e" => DATA <= x"60e0";
when "10" & x"c1f" => DATA <= x"f33e";
when "10" & x"c20" => DATA <= x"8000";
when "10" & x"c21" => DATA <= x"881e";
when "10" & x"c22" => DATA <= x"0140";
when "10" & x"c23" => DATA <= x"0a0a";
when "10" & x"c24" => DATA <= x"0040";
when "10" & x"c25" => DATA <= x"5000";
when "10" & x"c26" => DATA <= x"a800";
when "10" & x"c27" => DATA <= x"40b0";
when "10" & x"c28" => DATA <= x"0200";
when "10" & x"c29" => DATA <= x"1280";
when "10" & x"c2a" => DATA <= x"0034";
when "10" & x"c2b" => DATA <= x"0015";
when "10" & x"c2c" => DATA <= x"0081";
when "10" & x"c2d" => DATA <= x"3430";
when "10" & x"c2e" => DATA <= x"0c0c";
when "10" & x"c2f" => DATA <= x"f00a";
when "10" & x"c30" => DATA <= x"00a0";
when "10" & x"c31" => DATA <= x"1000";
when "10" & x"c32" => DATA <= x"0f80";
when "10" & x"c33" => DATA <= x"6800";
when "10" & x"c34" => DATA <= x"2140";
when "10" & x"c35" => DATA <= x"010f";
when "10" & x"c36" => DATA <= x"0000";
when "10" & x"c37" => DATA <= x"0068";
when "10" & x"c38" => DATA <= x"0050";
when "10" & x"c39" => DATA <= x"0ae0";
when "10" & x"c3a" => DATA <= x"0547";
when "10" & x"c3b" => DATA <= x"0004";
when "10" & x"c3c" => DATA <= x"000c";
when "10" & x"c3d" => DATA <= x"0000";
when "10" & x"c3e" => DATA <= x"4100";
when "10" & x"c3f" => DATA <= x"9f5f";
when "10" & x"c40" => DATA <= x"a7d7";
when "10" & x"c41" => DATA <= x"e9fa";
when "10" & x"c42" => DATA <= x"bf4f";
when "10" & x"c43" => DATA <= x"ab74";
when "10" & x"c44" => DATA <= x"b43a";
when "10" & x"c45" => DATA <= x"9d7f";
when "10" & x"c46" => DATA <= x"9f0f";
when "10" & x"c47" => DATA <= x"d2f8";
when "10" & x"c48" => DATA <= x"fca0";
when "10" & x"c49" => DATA <= x"07c2";
when "10" & x"c4a" => DATA <= x"2801";
when "10" & x"c4b" => DATA <= x"4201";
when "10" & x"c4c" => DATA <= x"37ab";
when "10" & x"c4d" => DATA <= x"3008";
when "10" & x"c4e" => DATA <= x"3400";
when "10" & x"c4f" => DATA <= x"1fce";
when "10" & x"c50" => DATA <= x"47fa";
when "10" & x"c51" => DATA <= x"ff7e";
when "10" & x"c52" => DATA <= x"6ff7";
when "10" & x"c53" => DATA <= x"ffff";
when "10" & x"c54" => DATA <= x"fd7f";
when "10" & x"c55" => DATA <= x"d388";
when "10" & x"c56" => DATA <= x"c75c";
when "10" & x"c57" => DATA <= x"43d4";
when "10" & x"c58" => DATA <= x"381e";
when "10" & x"c59" => DATA <= x"a1ca";
when "10" & x"c5a" => DATA <= x"1eff";
when "10" & x"c5b" => DATA <= x"f7fc";
when "10" & x"c5c" => DATA <= x"9fcf";
when "10" & x"c5d" => DATA <= x"ff00";
when "10" & x"c5e" => DATA <= x"bf00";
when "10" & x"c5f" => DATA <= x"6010";
when "10" & x"c60" => DATA <= x"0083";
when "10" & x"c61" => DATA <= x"801f";
when "10" & x"c62" => DATA <= x"e800";
when "10" & x"c63" => DATA <= x"2098";
when "10" & x"c64" => DATA <= x"18c0";
when "10" & x"c65" => DATA <= x"7020";
when "10" & x"c66" => DATA <= x"13b3";
when "10" & x"c67" => DATA <= x"815b";
when "10" & x"c68" => DATA <= x"edb0";
when "10" & x"c69" => DATA <= x"fa7f";
when "10" & x"c6a" => DATA <= x"87da";
when "10" & x"c6b" => DATA <= x"89c6";
when "10" & x"c6c" => DATA <= x"a362";
when "10" & x"c6d" => DATA <= x"b41e";
when "10" & x"c6e" => DATA <= x"8d4f";
when "10" & x"c6f" => DATA <= x"f77a";
when "10" & x"c70" => DATA <= x"f807";
when "10" & x"c71" => DATA <= x"8070";
when "10" & x"c72" => DATA <= x"0502";
when "10" & x"c73" => DATA <= x"0000";
when "10" & x"c74" => DATA <= x"9400";
when "10" & x"c75" => DATA <= x"04f0";
when "10" & x"c76" => DATA <= x"0f00";
when "10" & x"c77" => DATA <= x"f009";
when "10" & x"c78" => DATA <= x"0010";
when "10" & x"c79" => DATA <= x"5005";
when "10" & x"c7a" => DATA <= x"1000";
when "10" & x"c7b" => DATA <= x"041e";
when "10" & x"c7c" => DATA <= x"01e0";
when "10" & x"c7d" => DATA <= x"1e01";
when "10" & x"c7e" => DATA <= x"e01e";
when "10" & x"c7f" => DATA <= x"01e0";
when "10" & x"c80" => DATA <= x"1e01";
when "10" & x"c81" => DATA <= x"e01e";
when "10" & x"c82" => DATA <= x"01e0";
when "10" & x"c83" => DATA <= x"1e01";
when "10" & x"c84" => DATA <= x"2001";
when "10" & x"c85" => DATA <= x"0f00";
when "10" & x"c86" => DATA <= x"f00a";
when "10" & x"c87" => DATA <= x"3900";
when "10" & x"c88" => DATA <= x"8e68";
when "10" & x"c89" => DATA <= x"6472";
when "10" & x"c8a" => DATA <= x"0900";
when "10" & x"c8b" => DATA <= x"1000";
when "10" & x"c8c" => DATA <= x"0029";
when "10" & x"c8d" => DATA <= x"0026";
when "10" & x"c8e" => DATA <= x"9308";
when "10" & x"c8f" => DATA <= x"84c2";
when "10" & x"c90" => DATA <= x"6f26";
when "10" & x"c91" => DATA <= x"7805";
when "10" & x"c92" => DATA <= x"0001";
when "10" & x"c93" => DATA <= x"3c03";
when "10" & x"c94" => DATA <= x"c03c";
when "10" & x"c95" => DATA <= x"03c0";
when "10" & x"c96" => DATA <= x"3c03";
when "10" & x"c97" => DATA <= x"c03c";
when "10" & x"c98" => DATA <= x"0000";
when "10" & x"c99" => DATA <= x"40f0";
when "10" & x"c9a" => DATA <= x"0f00";
when "10" & x"c9b" => DATA <= x"f00f";
when "10" & x"c9c" => DATA <= x"00f0";
when "10" & x"c9d" => DATA <= x"0000";
when "10" & x"c9e" => DATA <= x"0b40";
when "10" & x"c9f" => DATA <= x"005e";
when "10" & x"ca0" => DATA <= x"01e0";
when "10" & x"ca1" => DATA <= x"1e01";
when "10" & x"ca2" => DATA <= x"2001";
when "10" & x"ca3" => DATA <= x"0e00";
when "10" & x"ca4" => DATA <= x"0878";
when "10" & x"ca5" => DATA <= x"0780";
when "10" & x"ca6" => DATA <= x"7806";
when "10" & x"ca7" => DATA <= x"807c";
when "10" & x"ca8" => DATA <= x"0200";
when "10" & x"ca9" => DATA <= x"fa1c";
when "10" & x"caa" => DATA <= x"2e0f";
when "10" & x"cab" => DATA <= x"5faf";
when "10" & x"cac" => DATA <= x"c7eb";
when "10" & x"cad" => DATA <= x"7420";
when "10" & x"cae" => DATA <= x"60a0";
when "10" & x"caf" => DATA <= x"0a01";
when "10" & x"cb0" => DATA <= x"0401";
when "10" & x"cb1" => DATA <= x"0343";
when "10" & x"cb2" => DATA <= x"a181";
when "10" & x"cb3" => DATA <= x"61f0";
when "10" & x"cb4" => DATA <= x"002a";
when "10" & x"cb5" => DATA <= x"4803";
when "10" & x"cb6" => DATA <= x"3d7e";
when "10" & x"cb7" => DATA <= x"005e";
when "10" & x"cb8" => DATA <= x"c803";
when "10" & x"cb9" => DATA <= x"fc62";
when "10" & x"cba" => DATA <= x"307d";
when "10" & x"cbb" => DATA <= x"c801";
when "10" & x"cbc" => DATA <= x"e400";
when "10" & x"cbd" => DATA <= x"701e";
when "10" & x"cbe" => DATA <= x"8100";
when "10" & x"cbf" => DATA <= x"e470";
when "10" & x"cc0" => DATA <= x"387c";
when "10" & x"cc1" => DATA <= x"1f43";
when "10" & x"cc2" => DATA <= x"e3ff";
when "10" & x"cc3" => DATA <= x"0028";
when "10" & x"cc4" => DATA <= x"7804";
when "10" & x"cc5" => DATA <= x"802a";
when "10" & x"cc6" => DATA <= x"3800";
when "10" & x"cc7" => DATA <= x"41c0";
when "10" & x"cc8" => DATA <= x"042e";
when "10" & x"cc9" => DATA <= x"0020";
when "10" & x"cca" => DATA <= x"7001";
when "10" & x"ccb" => DATA <= x"5000";
when "10" & x"ccc" => DATA <= x"01a0";
when "10" & x"ccd" => DATA <= x"0060";
when "10" & x"cce" => DATA <= x"1283";
when "10" & x"ccf" => DATA <= x"0080";
when "10" & x"cd0" => DATA <= x"c020";
when "10" & x"cd1" => DATA <= x"33c0";
when "10" & x"cd2" => DATA <= x"0012";
when "10" & x"cd3" => DATA <= x"0200";
when "10" & x"cd4" => DATA <= x"e01a";
when "10" & x"cd5" => DATA <= x"0000";
when "10" & x"cd6" => DATA <= x"8000";
when "10" & x"cd7" => DATA <= x"3a00";
when "10" & x"cd8" => DATA <= x"a1d0";
when "10" & x"cd9" => DATA <= x"0045";
when "10" & x"cda" => DATA <= x"0170";
when "10" & x"cdb" => DATA <= x"0008";
when "10" & x"cdc" => DATA <= x"0080";
when "10" & x"cdd" => DATA <= x"0004";
when "10" & x"cde" => DATA <= x"2801";
when "10" & x"cdf" => DATA <= x"0140";
when "10" & x"ce0" => DATA <= x"01fe";
when "10" & x"ce1" => DATA <= x"3f07";
when "10" & x"ce2" => DATA <= x"b9eb";
when "10" & x"ce3" => DATA <= x"3d3a";
when "10" & x"ce4" => DATA <= x"9b4f";
when "10" & x"ce5" => DATA <= x"83d1";
when "10" & x"ce6" => DATA <= x"ead7";
when "10" & x"ce7" => DATA <= x"0a04";
when "10" & x"ce8" => DATA <= x"01df";
when "10" & x"ce9" => DATA <= x"94fe";
when "10" & x"cea" => DATA <= x"5f3f";
when "10" & x"ceb" => DATA <= x"a028";
when "10" & x"cec" => DATA <= x"0ce7";
when "10" & x"ced" => DATA <= x"2009";
when "10" & x"cee" => DATA <= x"6693";
when "10" & x"cef" => DATA <= x"696c";
when "10" & x"cf0" => DATA <= x"0400";
when "10" & x"cf1" => DATA <= x"57e3";
when "10" & x"cf2" => DATA <= x"fdf0";
when "10" & x"cf3" => DATA <= x"fa7d";
when "10" & x"cf4" => DATA <= x"a000";
when "10" & x"cf5" => DATA <= x"0850";
when "10" & x"cf6" => DATA <= x"1dff";
when "10" & x"cf7" => DATA <= x"83c0";
when "10" & x"cf8" => DATA <= x"1bfe";
when "10" & x"cf9" => DATA <= x"0768";
when "10" & x"cfa" => DATA <= x"0029";
when "10" & x"cfb" => DATA <= x"c4a3";
when "10" & x"cfc" => DATA <= x"4020";
when "10" & x"cfd" => DATA <= x"0008";
when "10" & x"cfe" => DATA <= x"0287";
when "10" & x"cff" => DATA <= x"b872";
when "10" & x"d00" => DATA <= x"8783";
when "10" & x"d01" => DATA <= x"9fff";
when "10" & x"d02" => DATA <= x"bff4";
when "10" & x"d03" => DATA <= x"7f57";
when "10" & x"d04" => DATA <= x"e210";
when "10" & x"d05" => DATA <= x"3d00";
when "10" & x"d06" => DATA <= x"f003";
when "10" & x"d07" => DATA <= x"fe82";
when "10" & x"d08" => DATA <= x"150e";
when "10" & x"d09" => DATA <= x"8e00";
when "10" & x"d0a" => DATA <= x"7fd6";
when "10" & x"d0b" => DATA <= x"033d";
when "10" & x"d0c" => DATA <= x"8ce4";
when "10" & x"d0d" => DATA <= x"6138";
when "10" & x"d0e" => DATA <= x"1812";
when "10" & x"d0f" => DATA <= x"3e9f";
when "10" & x"d10" => DATA <= x"a1f0";
when "10" & x"d11" => DATA <= x"f341";
when "10" & x"d12" => DATA <= x"295a";
when "10" & x"d13" => DATA <= x"0d56";
when "10" & x"d14" => DATA <= x"2d6a";
when "10" & x"d15" => DATA <= x"3dfb";
when "10" & x"d16" => DATA <= x"d5ee";
when "10" & x"d17" => DATA <= x"f5af";
when "10" & x"d18" => DATA <= x"7f00";
when "10" & x"d19" => DATA <= x"f00a";
when "10" & x"d1a" => DATA <= x"0002";
when "10" & x"d1b" => DATA <= x"5000";
when "10" & x"d1c" => DATA <= x"1380";
when "10" & x"d1d" => DATA <= x"009e";
when "10" & x"d1e" => DATA <= x"01e0";
when "10" & x"d1f" => DATA <= x"1e01";
when "10" & x"d20" => DATA <= x"c002";
when "10" & x"d21" => DATA <= x"0a00";
when "10" & x"d22" => DATA <= x"1000";
when "10" & x"d23" => DATA <= x"0400";
when "10" & x"d24" => DATA <= x"0107";
when "10" & x"d25" => DATA <= x"8078";
when "10" & x"d26" => DATA <= x"0780";
when "10" & x"d27" => DATA <= x"7807";
when "10" & x"d28" => DATA <= x"8078";
when "10" & x"d29" => DATA <= x"0580";
when "10" & x"d2a" => DATA <= x"00bc";
when "10" & x"d2b" => DATA <= x"03c0";
when "10" & x"d2c" => DATA <= x"2400";
when "10" & x"d2d" => DATA <= x"11e0";
when "10" & x"d2e" => DATA <= x"1e00";
when "10" & x"d2f" => DATA <= x"0008";
when "10" & x"d30" => DATA <= x"7800";
when "10" & x"d31" => DATA <= x"0010";
when "10" & x"d32" => DATA <= x"0004";
when "10" & x"d33" => DATA <= x"0028";
when "10" & x"d34" => DATA <= x"e412";
when "10" & x"d35" => DATA <= x"1904";
when "10" & x"d36" => DATA <= x"f0cf";
when "10" & x"d37" => DATA <= x"8000";
when "10" & x"d38" => DATA <= x"2930";
when "10" & x"d39" => DATA <= x"9a4c";
when "10" & x"d3a" => DATA <= x"2252";
when "10" & x"d3b" => DATA <= x"6137";
when "10" & x"d3c" => DATA <= x"c03c";
when "10" & x"d3d" => DATA <= x"03c0";
when "10" & x"d3e" => DATA <= x"3800";
when "10" & x"d3f" => DATA <= x"1140";
when "10" & x"d40" => DATA <= x"008e";
when "10" & x"d41" => DATA <= x"0004";
when "10" & x"d42" => DATA <= x"7804";
when "10" & x"d43" => DATA <= x"8008";
when "10" & x"d44" => DATA <= x"3c03";
when "10" & x"d45" => DATA <= x"4008";
when "10" & x"d46" => DATA <= x"1400";
when "10" & x"d47" => DATA <= x"40f0";
when "10" & x"d48" => DATA <= x"0f00";
when "10" & x"d49" => DATA <= x"f00f";
when "10" & x"d4a" => DATA <= x"00f0";
when "10" & x"d4b" => DATA <= x"0000";
when "10" & x"d4c" => DATA <= x"0a80";
when "10" & x"d4d" => DATA <= x"0040";
when "10" & x"d4e" => DATA <= x"0017";
when "10" & x"d4f" => DATA <= x"8078";
when "10" & x"d50" => DATA <= x"0780";
when "10" & x"d51" => DATA <= x"6800";
when "10" & x"d52" => DATA <= x"4280";
when "10" & x"d53" => DATA <= x"021e";
when "10" & x"d54" => DATA <= x"01e0";
when "10" & x"d55" => DATA <= x"1e01";
when "10" & x"d56" => DATA <= x"e01f";
when "10" & x"d57" => DATA <= x"0080";
when "10" & x"d58" => DATA <= x"7e9f";
when "10" & x"d59" => DATA <= x"5a8d";
when "10" & x"d5a" => DATA <= x"d2a1";
when "10" & x"d5b" => DATA <= x"70f8";
when "10" & x"d5c" => DATA <= x"dc20";
when "10" & x"d5d" => DATA <= x"5002";
when "10" & x"d5e" => DATA <= x"cbc0";
when "10" & x"d5f" => DATA <= x"2c00";
when "10" & x"d60" => DATA <= x"a1c0";
when "10" & x"d61" => DATA <= x"14a0";
when "10" & x"d62" => DATA <= x"007f";
when "10" & x"d63" => DATA <= x"8178";
when "10" & x"d64" => DATA <= x"0003";
when "10" & x"d65" => DATA <= x"4007";
when "10" & x"d66" => DATA <= x"f057";
when "10" & x"d67" => DATA <= x"0002";
when "10" & x"d68" => DATA <= x"2802";
when "10" & x"d69" => DATA <= x"8311";
when "10" & x"d6a" => DATA <= x"9419";
when "10" & x"d6b" => DATA <= x"c580";
when "10" & x"d6c" => DATA <= x"0380";
when "10" & x"d6d" => DATA <= x"1ce0";
when "10" & x"d6e" => DATA <= x"0020";
when "10" & x"d6f" => DATA <= x"153c";
when "10" & x"d70" => DATA <= x"0380";
when "10" & x"d71" => DATA <= x"040a";
when "10" & x"d72" => DATA <= x"a100";
when "10" & x"d73" => DATA <= x"0010";
when "10" & x"d74" => DATA <= x"0010";
when "10" & x"d75" => DATA <= x"0008";
when "10" & x"d76" => DATA <= x"1c00";
when "10" & x"d77" => DATA <= x"02e0";
when "10" & x"d78" => DATA <= x"0200";
when "10" & x"d79" => DATA <= x"5403";
when "10" & x"d7a" => DATA <= x"c000";
when "10" & x"d7b" => DATA <= x"4a0c";
when "10" & x"d7c" => DATA <= x"0703";
when "10" & x"d7d" => DATA <= x"0080";
when "10" & x"d7e" => DATA <= x"ca04";
when "10" & x"d7f" => DATA <= x"0020";
when "10" & x"d80" => DATA <= x"2c00";
when "10" & x"d81" => DATA <= x"0203";
when "10" & x"d82" => DATA <= x"a010";
when "10" & x"d83" => DATA <= x"0700";
when "10" & x"d84" => DATA <= x"d085";
when "10" & x"d85" => DATA <= x"0010";
when "10" & x"d86" => DATA <= x"6400";
when "10" & x"d87" => DATA <= x"03e0";
when "10" & x"d88" => DATA <= x"028f";
when "10" & x"d89" => DATA <= x"0060";
when "10" & x"d8a" => DATA <= x"5803";
when "10" & x"d8b" => DATA <= x"bd8e";
when "10" & x"d8c" => DATA <= x"cf77";
when "10" & x"d8d" => DATA <= x"f67a";
when "10" & x"d8e" => DATA <= x"9d46";
when "10" & x"d8f" => DATA <= x"ab54";
when "10" & x"d90" => DATA <= x"a26a";
when "10" & x"d91" => DATA <= x"8556";
when "10" & x"d92" => DATA <= x"893f";
when "10" & x"d93" => DATA <= x"9df9";
when "10" & x"d94" => DATA <= x"fcbe";
when "10" & x"d95" => DATA <= x"7f27";
when "10" & x"d96" => DATA <= x"d608";
when "10" & x"d97" => DATA <= x"e018";
when "10" & x"d98" => DATA <= x"f800";
when "10" & x"d99" => DATA <= x"0400";
when "10" & x"d9a" => DATA <= x"03f0";
when "10" & x"d9b" => DATA <= x"0a01";
when "10" & x"d9c" => DATA <= x"f857";
when "10" & x"d9d" => DATA <= x"9004";
when "10" & x"d9e" => DATA <= x"277f";
when "10" & x"d9f" => DATA <= x"b800";
when "10" & x"da0" => DATA <= x"0c00";
when "10" & x"da1" => DATA <= x"07ff";
when "10" & x"da2" => DATA <= x"bfbf";
when "10" & x"da3" => DATA <= x"fc03";
when "10" & x"da4" => DATA <= x"6e21";
when "10" & x"da5" => DATA <= x"10f0";
when "10" & x"da6" => DATA <= x"72cd";
when "10" & x"da7" => DATA <= x"3ffd";
when "10" & x"da8" => DATA <= x"ff57";
when "10" & x"da9" => DATA <= x"fc7e";
when "10" & x"daa" => DATA <= x"0fa3";
when "10" & x"dab" => DATA <= x"faff";
when "10" & x"dac" => DATA <= x"afc9";
when "10" & x"dad" => DATA <= x"003f";
when "10" & x"dae" => DATA <= x"f7fc";
when "10" & x"daf" => DATA <= x"8030";
when "10" & x"db0" => DATA <= x"2b9d";
when "10" & x"db1" => DATA <= x"9ee6";
when "10" & x"db2" => DATA <= x"0057";
when "10" & x"db3" => DATA <= x"005d";
when "10" & x"db4" => DATA <= x"3e1b";
when "10" & x"db5" => DATA <= x"0fa7";
when "10" & x"db6" => DATA <= x"c3f5";
when "10" & x"db7" => DATA <= x"3ed4";
when "10" & x"db8" => DATA <= x"6ab5";
when "10" & x"db9" => DATA <= x"198c";
when "10" & x"dba" => DATA <= x"a64a";
when "10" & x"dbb" => DATA <= x"2593";
when "10" & x"dbc" => DATA <= x"feaf";
when "10" & x"dbd" => DATA <= x"5f00";
when "10" & x"dbe" => DATA <= x"f00a";
when "10" & x"dbf" => DATA <= x"0002";
when "10" & x"dc0" => DATA <= x"5000";
when "10" & x"dc1" => DATA <= x"1280";
when "10" & x"dc2" => DATA <= x"009e";
when "10" & x"dc3" => DATA <= x"01e0";
when "10" & x"dc4" => DATA <= x"1e01";
when "10" & x"dc5" => DATA <= x"2002";
when "10" & x"dc6" => DATA <= x"0a00";
when "10" & x"dc7" => DATA <= x"1050";
when "10" & x"dc8" => DATA <= x"0083";
when "10" & x"dc9" => DATA <= x"c03c";
when "10" & x"dca" => DATA <= x"03c0";
when "10" & x"dcb" => DATA <= x"3c03";
when "10" & x"dcc" => DATA <= x"c000";
when "10" & x"dcd" => DATA <= x"001f";
when "10" & x"dce" => DATA <= x"00f0";
when "10" & x"dcf" => DATA <= x"0900";
when "10" & x"dd0" => DATA <= x"0178";
when "10" & x"dd1" => DATA <= x"0780";
when "10" & x"dd2" => DATA <= x"0001";
when "10" & x"dd3" => DATA <= x"1e01";
when "10" & x"dd4" => DATA <= x"a001";
when "10" & x"dd5" => DATA <= x"0a00";
when "10" & x"dd6" => DATA <= x"0878";
when "10" & x"dd7" => DATA <= x"0000";
when "10" & x"dd8" => DATA <= x"1143";
when "10" & x"dd9" => DATA <= x"209e";
when "10" & x"dda" => DATA <= x"194c";
when "10" & x"ddb" => DATA <= x"867c";
when "10" & x"ddc" => DATA <= x"0001";
when "10" & x"ddd" => DATA <= x"4984";
when "10" & x"dde" => DATA <= x"4261";
when "10" & x"ddf" => DATA <= x"108a";
when "10" & x"de0" => DATA <= x"4c22";
when "10" & x"de1" => DATA <= x"7807";
when "10" & x"de2" => DATA <= x"8001";
when "10" & x"de3" => DATA <= x"3c02";
when "10" & x"de4" => DATA <= x"8001";
when "10" & x"de5" => DATA <= x"1a00";
when "10" & x"de6" => DATA <= x"08f0";
when "10" & x"de7" => DATA <= x"0d00";
when "10" & x"de8" => DATA <= x"1078";
when "10" & x"de9" => DATA <= x"0780";
when "10" & x"dea" => DATA <= x"0008";
when "10" & x"deb" => DATA <= x"1e01";
when "10" & x"dec" => DATA <= x"e01e";
when "10" & x"ded" => DATA <= x"01e0";
when "10" & x"dee" => DATA <= x"1e00";
when "10" & x"def" => DATA <= x"0001";
when "10" & x"df0" => DATA <= x"5000";
when "10" & x"df1" => DATA <= x"0a80";
when "10" & x"df2" => DATA <= x"005e";
when "10" & x"df3" => DATA <= x"01e0";
when "10" & x"df4" => DATA <= x"1e01";
when "10" & x"df5" => DATA <= x"2001";
when "10" & x"df6" => DATA <= x"0a00";
when "10" & x"df7" => DATA <= x"0850";
when "10" & x"df8" => DATA <= x"0043";
when "10" & x"df9" => DATA <= x"c03c";
when "10" & x"dfa" => DATA <= x"03c0";
when "10" & x"dfb" => DATA <= x"2403";
when "10" & x"dfc" => DATA <= x"e010";
when "10" & x"dfd" => DATA <= x"0dc7";
when "10" & x"dfe" => DATA <= x"e371";
when "10" & x"dff" => DATA <= x"f81c";
when "10" & x"e00" => DATA <= x"7a3f";
when "10" & x"e01" => DATA <= x"1b80";
when "10" & x"e02" => DATA <= x"0010";
when "10" & x"e03" => DATA <= x"0004";
when "10" & x"e04" => DATA <= x"6000";
when "10" & x"e05" => DATA <= x"5207";
when "10" & x"e06" => DATA <= x"8050";
when "10" & x"e07" => DATA <= x"0050";
when "10" & x"e08" => DATA <= x"8800";
when "10" & x"e09" => DATA <= x"2800";
when "10" & x"e0a" => DATA <= x"0a94";
when "10" & x"e0b" => DATA <= x"0140";
when "10" & x"e0c" => DATA <= x"200e";
when "10" & x"e0d" => DATA <= x"01a0";
when "10" & x"e0e" => DATA <= x"0100";
when "10" & x"e0f" => DATA <= x"a000";
when "10" & x"e10" => DATA <= x"0800";
when "10" & x"e11" => DATA <= x"0880";
when "10" & x"e12" => DATA <= x"02c0";
when "10" & x"e13" => DATA <= x"40b1";
when "10" & x"e14" => DATA <= x"580c";
when "10" & x"e15" => DATA <= x"1603";
when "10" & x"e16" => DATA <= x"0581";
when "10" & x"e17" => DATA <= x"0a30";
when "10" & x"e18" => DATA <= x"210c";
when "10" & x"e19" => DATA <= x"2800";
when "10" & x"e1a" => DATA <= x"0da0";
when "10" & x"e1b" => DATA <= x"080e";
when "10" & x"e1c" => DATA <= x"0051";
when "10" & x"e1d" => DATA <= x"0204";
when "10" & x"e1e" => DATA <= x"0000";
when "10" & x"e1f" => DATA <= x"4000";
when "10" & x"e20" => DATA <= x"41a0";
when "10" & x"e21" => DATA <= x"040e";
when "10" & x"e22" => DATA <= x"0028";
when "10" & x"e23" => DATA <= x"0000";
when "10" & x"e24" => DATA <= x"801e";
when "10" & x"e25" => DATA <= x"00e0";
when "10" & x"e26" => DATA <= x"c070";
when "10" & x"e27" => DATA <= x"1283";
when "10" & x"e28" => DATA <= x"00de";
when "10" & x"e29" => DATA <= x"0000";
when "10" & x"e2a" => DATA <= x"0480";
when "10" & x"e2b" => DATA <= x"4060";
when "10" & x"e2c" => DATA <= x"1007";
when "10" & x"e2d" => DATA <= x"0095";
when "10" & x"e2e" => DATA <= x"4005";
when "10" & x"e2f" => DATA <= x"0020";
when "10" & x"e30" => DATA <= x"0780";
when "10" & x"e31" => DATA <= x"1400";
when "10" & x"e32" => DATA <= x"0408";
when "10" & x"e33" => DATA <= x"0003";
when "10" & x"e34" => DATA <= x"4000";
when "10" & x"e35" => DATA <= x"1050";
when "10" & x"e36" => DATA <= x"0054";
when "10" & x"e37" => DATA <= x"0041";
when "10" & x"e38" => DATA <= x"5002";
when "10" & x"e39" => DATA <= x"8000";
when "10" & x"e3a" => DATA <= x"8060";
when "10" & x"e3b" => DATA <= x"7002";
when "10" & x"e3c" => DATA <= x"0001";
when "10" & x"e3d" => DATA <= x"5cee";
when "10" & x"e3e" => DATA <= x"36bb";
when "10" & x"e3f" => DATA <= x"8d8e";
when "10" & x"e40" => DATA <= x"e363";
when "10" & x"e41" => DATA <= x"a2d0";
when "10" & x"e42" => DATA <= x"0aa5";
when "10" & x"e43" => DATA <= x"132b";
when "10" & x"e44" => DATA <= x"aa9f";
when "10" & x"e45" => DATA <= x"e7f3";
when "10" & x"e46" => DATA <= x"dbfe";
when "10" & x"e47" => DATA <= x"9fce";
when "10" & x"e48" => DATA <= x"e7e7";
when "10" & x"e49" => DATA <= x"0001";
when "10" & x"e4a" => DATA <= x"1002";
when "10" & x"e4b" => DATA <= x"7e3e";
when "10" & x"e4c" => DATA <= x"0000";
when "10" & x"e4d" => DATA <= x"102f";
when "10" & x"e4e" => DATA <= x"003f";
when "10" & x"e4f" => DATA <= x"c060";
when "10" & x"e50" => DATA <= x"0705";
when "10" & x"e51" => DATA <= x"4038";
when "10" & x"e52" => DATA <= x"0c00";
when "10" & x"e53" => DATA <= x"3002";
when "10" & x"e54" => DATA <= x"391f";
when "10" & x"e55" => DATA <= x"dfe0";
when "10" & x"e56" => DATA <= x"1a00";
when "10" & x"e57" => DATA <= x"9ff0";
when "10" & x"e58" => DATA <= x"5b80";
when "10" & x"e59" => DATA <= x"01df";
when "10" & x"e5a" => DATA <= x"f402";
when "10" & x"e5b" => DATA <= x"0000";
when "10" & x"e5c" => DATA <= x"8038";
when "10" & x"e5d" => DATA <= x"068d";
when "10" & x"e5e" => DATA <= x"0614";
when "10" & x"e5f" => DATA <= x"01c6";
when "10" & x"e60" => DATA <= x"9dfe";
when "10" & x"e61" => DATA <= x"0060";
when "10" & x"e62" => DATA <= x"77ff";
when "10" & x"e63" => DATA <= x"1f80";
when "10" & x"e64" => DATA <= x"07fd";
when "10" & x"e65" => DATA <= x"7f40";
when "10" & x"e66" => DATA <= x"0fca";
when "10" & x"e67" => DATA <= x"001f";
when "10" & x"e68" => DATA <= x"bff8";
when "10" & x"e69" => DATA <= x"02bf";
when "10" & x"e6a" => DATA <= x"dc00";
when "10" & x"e6b" => DATA <= x"07f8";
when "10" & x"e6c" => DATA <= x"0080";
when "10" & x"e6d" => DATA <= x"e667";
when "10" & x"e6e" => DATA <= x"b1dc";
when "10" & x"e6f" => DATA <= x"ec0a";
when "10" & x"e70" => DATA <= x"e00f";
when "10" & x"e71" => DATA <= x"a7c3";
when "10" & x"e72" => DATA <= x"c1b4";
when "10" & x"e73" => DATA <= x"f87c";
when "10" & x"e74" => DATA <= x"3c1f";
when "10" & x"e75" => DATA <= x"64b2";
when "10" & x"e76" => DATA <= x"990c";
when "10" & x"e77" => DATA <= x"062d";
when "10" & x"e78" => DATA <= x"6230";
when "10" & x"e79" => DATA <= x"27d5";
when "10" & x"e7a" => DATA <= x"eef5";
when "10" & x"e7b" => DATA <= x"af7b";
when "10" & x"e7c" => DATA <= x"0022";
when "10" & x"e7d" => DATA <= x"3cac";
when "10" & x"e7e" => DATA <= x"0088";
when "10" & x"e7f" => DATA <= x"f090";
when "10" & x"e80" => DATA <= x"0e04";
when "10" & x"e81" => DATA <= x"7078";
when "10" & x"e82" => DATA <= x"0207";
when "10" & x"e83" => DATA <= x"4028";
when "10" & x"e84" => DATA <= x"2103";
when "10" & x"e85" => DATA <= x"e008";
when "10" & x"e86" => DATA <= x"6000";
when "10" & x"e87" => DATA <= x"8280";
when "10" & x"e88" => DATA <= x"3880";
when "10" & x"e89" => DATA <= x"0760";
when "10" & x"e8a" => DATA <= x"0400";
when "10" & x"e8b" => DATA <= x"7e80";
when "10" & x"e8c" => DATA <= x"5200";
when "10" & x"e8d" => DATA <= x"3ec0";
when "10" & x"e8e" => DATA <= x"0021";
when "10" & x"e8f" => DATA <= x"cf00";
when "10" & x"e90" => DATA <= x"0868";
when "10" & x"e91" => DATA <= x"0500";
when "10" & x"e92" => DATA <= x"9e2c";
when "10" & x"e93" => DATA <= x"0044";
when "10" & x"e94" => DATA <= x"78d0";
when "10" & x"e95" => DATA <= x"0a02";
when "10" & x"e96" => DATA <= x"7878";
when "10" & x"e97" => DATA <= x"0383";
when "10" & x"e98" => DATA <= x"4028";
when "10" & x"e99" => DATA <= x"2181";
when "10" & x"e9a" => DATA <= x"6000";
when "10" & x"e9b" => DATA <= x"1018";
when "10" & x"e9c" => DATA <= x"0021";
when "10" & x"e9d" => DATA <= x"c001";
when "10" & x"e9e" => DATA <= x"0088";
when "10" & x"e9f" => DATA <= x"0f40";
when "10" & x"ea0" => DATA <= x"1108";
when "10" & x"ea1" => DATA <= x"e715";
when "10" & x"ea2" => DATA <= x"0c82";
when "10" & x"ea3" => DATA <= x"6865";
when "10" & x"ea4" => DATA <= x"f8c0";
when "10" & x"ea5" => DATA <= x"67e8";
when "10" & x"ea6" => DATA <= x"03fc";
when "10" & x"ea7" => DATA <= x"fe3f";
when "10" & x"ea8" => DATA <= x"2693";
when "10" & x"ea9" => DATA <= x"0884";
when "10" & x"eaa" => DATA <= x"c26d";
when "10" & x"eab" => DATA <= x"5f87";
when "10" & x"eac" => DATA <= x"f400";
when "10" & x"ead" => DATA <= x"0673";
when "10" & x"eae" => DATA <= x"00e8";
when "10" & x"eaf" => DATA <= x"0011";
when "10" & x"eb0" => DATA <= x"0804";
when "10" & x"eb1" => DATA <= x"b004";
when "10" & x"eb2" => DATA <= x"4207";
when "10" & x"eb3" => DATA <= x"4028";
when "10" & x"eb4" => DATA <= x"2133";
when "10" & x"eb5" => DATA <= x"e000";
when "10" & x"eb6" => DATA <= x"3d00";
when "10" & x"eb7" => DATA <= x"a201";
when "10" & x"eb8" => DATA <= x"9580";
when "10" & x"eb9" => DATA <= x"1001";
when "10" & x"eba" => DATA <= x"a002";
when "10" & x"ebb" => DATA <= x"0700";
when "10" & x"ebc" => DATA <= x"7207";
when "10" & x"ebd" => DATA <= x"8078";
when "10" & x"ebe" => DATA <= x"0001";
when "10" & x"ebf" => DATA <= x"21a0";
when "10" & x"ec0" => DATA <= x"0011";
when "10" & x"ec1" => DATA <= x"1966";
when "10" & x"ec2" => DATA <= x"c004";
when "10" & x"ec3" => DATA <= x"4600";
when "10" & x"ec4" => DATA <= x"000a";
when "10" & x"ec5" => DATA <= x"8038";
when "10" & x"ec6" => DATA <= x"0905";
when "10" & x"ec7" => DATA <= x"e008";
when "10" & x"ec8" => DATA <= x"0d00";
when "10" & x"ec9" => DATA <= x"0400";
when "10" & x"eca" => DATA <= x"0196";
when "10" & x"ecb" => DATA <= x"0011";
when "10" & x"ecc" => DATA <= x"a000";
when "10" & x"ecd" => DATA <= x"8500";
when "10" & x"ece" => DATA <= x"5085";
when "10" & x"ecf" => DATA <= x"08f8";
when "10" & x"ed0" => DATA <= x"021f";
when "10" & x"ed1" => DATA <= x"4004";
when "10" & x"ed2" => DATA <= x"0aa3";
when "10" & x"ed3" => DATA <= x"3580";
when "10" & x"ed4" => DATA <= x"2000";
when "10" & x"ed5" => DATA <= x"1b00";
when "10" & x"ed6" => DATA <= x"40a8";
when "10" & x"ed7" => DATA <= x"07e7";
when "10" & x"ed8" => DATA <= x"6e07";
when "10" & x"ed9" => DATA <= x"1bc9";
when "10" & x"eda" => DATA <= x"e1f2";
when "10" & x"edb" => DATA <= x"e000";
when "10" & x"edc" => DATA <= x"0400";
when "10" & x"edd" => DATA <= x"0d13";
when "10" & x"ede" => DATA <= x"022a";
when "10" & x"edf" => DATA <= x"00e8";
when "10" & x"ee0" => DATA <= x"0601";
when "10" & x"ee1" => DATA <= x"014b";
when "10" & x"ee2" => DATA <= x"401c";
when "10" & x"ee3" => DATA <= x"0200";
when "10" & x"ee4" => DATA <= x"1494";
when "10" & x"ee5" => DATA <= x"b800";
when "10" & x"ee6" => DATA <= x"0340";
when "10" & x"ee7" => DATA <= x"0016";
when "10" & x"ee8" => DATA <= x"9700";
when "10" & x"ee9" => DATA <= x"0838";
when "10" & x"eea" => DATA <= x"0004";
when "10" & x"eeb" => DATA <= x"8016";
when "10" & x"eec" => DATA <= x"0338";
when "10" & x"eed" => DATA <= x"b056";
when "10" & x"eee" => DATA <= x"0804";
when "10" & x"eef" => DATA <= x"8006";
when "10" & x"ef0" => DATA <= x"0001";
when "10" & x"ef1" => DATA <= x"8152";
when "10" & x"ef2" => DATA <= x"8004";
when "10" & x"ef3" => DATA <= x"1e00";
when "10" & x"ef4" => DATA <= x"0045";
when "10" & x"ef5" => DATA <= x"2200";
when "10" & x"ef6" => DATA <= x"0a00";
when "10" & x"ef7" => DATA <= x"0280";
when "10" & x"ef8" => DATA <= x"008a";
when "10" & x"ef9" => DATA <= x"f000";
when "10" & x"efa" => DATA <= x"1004";
when "10" & x"efb" => DATA <= x"2bc0";
when "10" & x"efc" => DATA <= x"0050";
when "10" & x"efd" => DATA <= x"0006";
when "10" & x"efe" => DATA <= x"8300";
when "10" & x"eff" => DATA <= x"80ca";
when "10" & x"f00" => DATA <= x"04a0";
when "10" & x"f01" => DATA <= x"cf00";
when "10" & x"f02" => DATA <= x"4048";
when "10" & x"f03" => DATA <= x"0802";
when "10" & x"f04" => DATA <= x"8040";
when "10" & x"f05" => DATA <= x"7200";
when "10" & x"f06" => DATA <= x"0400";
when "10" & x"f07" => DATA <= x"054a";
when "10" & x"f08" => DATA <= x"9400";
when "10" & x"f09" => DATA <= x"21e0";
when "10" & x"f0a" => DATA <= x"0400";
when "10" & x"f0b" => DATA <= x"0680";
when "10" & x"f0c" => DATA <= x"0440";
when "10" & x"f0d" => DATA <= x"0050";
when "10" & x"f0e" => DATA <= x"0282";
when "10" & x"f0f" => DATA <= x"b801";
when "10" & x"f10" => DATA <= x"0140";
when "10" & x"f11" => DATA <= x"0106";
when "10" & x"f12" => DATA <= x"031d";
when "10" & x"f13" => DATA <= x"86c7";
when "10" & x"f14" => DATA <= x"61b1";
when "10" & x"f15" => DATA <= x"daeb";
when "10" & x"f16" => DATA <= x"f39a";
when "10" & x"f17" => DATA <= x"0ba0";
when "10" & x"f18" => DATA <= x"2a29";
when "10" & x"f19" => DATA <= x"5080";
when "10" & x"f1a" => DATA <= x"f7f2";
when "10" & x"f1b" => DATA <= x"fb07";
when "10" & x"f1c" => DATA <= x"c01f";
when "10" & x"f1d" => DATA <= x"efce";
when "10" & x"f1e" => DATA <= x"0002";
when "10" & x"f1f" => DATA <= x"001f";
when "10" & x"f20" => DATA <= x"88f4";
when "10" & x"f21" => DATA <= x"1a00";
when "10" & x"f22" => DATA <= x"0150";
when "10" & x"f23" => DATA <= x"0004";
when "10" & x"f24" => DATA <= x"2fff";
when "10" & x"f25" => DATA <= x"fffd";
when "10" & x"f26" => DATA <= x"7ff8";
when "10" & x"f27" => DATA <= x"0807";
when "10" & x"f28" => DATA <= x"4d28";
when "10" & x"f29" => DATA <= x"d801";
when "10" & x"f2a" => DATA <= x"7fe7";
when "10" & x"f2b" => DATA <= x"f005";
when "10" & x"f2c" => DATA <= x"5fd1";
when "10" & x"f2d" => DATA <= x"fd5f";
when "10" & x"f2e" => DATA <= x"f803";
when "10" & x"f2f" => DATA <= x"ffc0";
when "10" & x"f30" => DATA <= x"0fe7";
when "10" & x"f31" => DATA <= x"8a00";
when "10" & x"f32" => DATA <= x"ae26";
when "10" & x"f33" => DATA <= x"1382";
when "10" & x"f34" => DATA <= x"b01c";
when "10" & x"f35" => DATA <= x"f43e";
when "10" & x"f36" => DATA <= x"9fa1";
when "10" & x"f37" => DATA <= x"f0f0";
when "10" & x"f38" => DATA <= x"5d3e";
when "10" & x"f39" => DATA <= x"01a8";
when "10" & x"f3a" => DATA <= x"100a";
when "10" & x"f3b" => DATA <= x"2068";
when "10" & x"f3c" => DATA <= x"d06a";
when "10" & x"f3d" => DATA <= x"bf1f";
when "10" & x"f3e" => DATA <= x"afc7";
when "10" & x"f3f" => DATA <= x"a4f8";
when "10" & x"f40" => DATA <= x"0000";
when "10" & x"f41" => DATA <= x"4001";
when "10" & x"f42" => DATA <= x"e3f1";
when "10" & x"f43" => DATA <= x"5600";
when "10" & x"f44" => DATA <= x"0470";
when "10" & x"f45" => DATA <= x"007d";
when "10" & x"f46" => DATA <= x"feaf";
when "10" & x"f47" => DATA <= x"a00a";
when "10" & x"f48" => DATA <= x"0400";
when "10" & x"f49" => DATA <= x"26df";
when "10" & x"f4a" => DATA <= x"ebfd";
when "10" & x"f4b" => DATA <= x"000e";
when "10" & x"f4c" => DATA <= x"3fde";
when "10" & x"f4d" => DATA <= x"7400";
when "10" & x"f4e" => DATA <= x"100c";
when "10" & x"f4f" => DATA <= x"0007";
when "10" & x"f50" => DATA <= x"cff6";
when "10" & x"f51" => DATA <= x"de80";
when "10" & x"f52" => DATA <= x"0e1f";
when "10" & x"f53" => DATA <= x"e6da";
when "10" & x"f54" => DATA <= x"0010";
when "10" & x"f55" => DATA <= x"0c00";
when "10" & x"f56" => DATA <= x"0dda";
when "10" & x"f57" => DATA <= x"ffd0";
when "10" & x"f58" => DATA <= x"0723";
when "10" & x"f59" => DATA <= x"fde3";
when "10" & x"f5a" => DATA <= x"4004";
when "10" & x"f5b" => DATA <= x"0600";
when "10" & x"f5c" => DATA <= x"01e8";
when "10" & x"f5d" => DATA <= x"ff78";
when "10" & x"f5e" => DATA <= x"e803";
when "10" & x"f5f" => DATA <= x"21fe";
when "10" & x"f60" => DATA <= x"ead0";
when "10" & x"f61" => DATA <= x"061b";
when "10" & x"f62" => DATA <= x"fd77";
when "10" & x"f63" => DATA <= x"4014";
when "10" & x"f64" => DATA <= x"0200";
when "10" & x"f65" => DATA <= x"433f";
when "10" & x"f66" => DATA <= x"d9fa";
when "10" & x"f67" => DATA <= x"0087";
when "10" & x"f68" => DATA <= x"7fb3";
when "10" & x"f69" => DATA <= x"e802";
when "10" & x"f6a" => DATA <= x"8180";
when "10" & x"f6b" => DATA <= x"04d7";
when "10" & x"f6c" => DATA <= x"f97e";
when "10" & x"f6d" => DATA <= x"80b8";
when "10" & x"f6e" => DATA <= x"009c";
when "10" & x"f6f" => DATA <= x"ff2f";
when "10" & x"f70" => DATA <= x"d000";
when "10" & x"f71" => DATA <= x"2018";
when "10" & x"f72" => DATA <= x"0013";
when "10" & x"f73" => DATA <= x"bfcf";
when "10" & x"f74" => DATA <= x"fa00";
when "10" & x"f75" => DATA <= x"1c7f";
when "10" & x"f76" => DATA <= x"bba8";
when "10" & x"f77" => DATA <= x"0284";
when "10" & x"f78" => DATA <= x"000e";
when "10" & x"f79" => DATA <= x"c7fb";
when "10" & x"f7a" => DATA <= x"df80";
when "10" & x"f7b" => DATA <= x"1814";
when "10" & x"f7c" => DATA <= x"0002";
when "10" & x"f7d" => DATA <= x"7fd0";
when "10" & x"f7e" => DATA <= x"0031";
when "10" & x"f7f" => DATA <= x"0208";
when "10" & x"f80" => DATA <= x"1000";
when "10" & x"f81" => DATA <= x"1ff4";
when "10" & x"f82" => DATA <= x"0010";
when "10" & x"f83" => DATA <= x"0388";
when "10" & x"f84" => DATA <= x"2801";
when "10" & x"f85" => DATA <= x"ffc0";
when "10" & x"f86" => DATA <= x"07e7";
when "10" & x"f87" => DATA <= x"0500";
when "10" & x"f88" => DATA <= x"3fe8";
when "10" & x"f89" => DATA <= x"0006";
when "10" & x"f8a" => DATA <= x"e000";
when "10" & x"f8b" => DATA <= x"5403";
when "10" & x"f8c" => DATA <= x"fe98";
when "10" & x"f8d" => DATA <= x"00c0";
when "10" & x"f8e" => DATA <= x"7000";
when "10" & x"f8f" => DATA <= x"6dfe";
when "10" & x"f90" => DATA <= x"f7d0";
when "10" & x"f91" => DATA <= x"02f3";
when "10" & x"f92" => DATA <= x"fd37";
when "10" & x"f93" => DATA <= x"4000";
when "10" & x"f94" => DATA <= x"80c0";
when "10" & x"f95" => DATA <= x"002c";
when "10" & x"f96" => DATA <= x"ff6d";
when "10" & x"f97" => DATA <= x"e800";
when "10" & x"f98" => DATA <= x"e1fe";
when "10" & x"f99" => DATA <= x"e5a0";
when "10" & x"f9a" => DATA <= x"0100";
when "10" & x"f9b" => DATA <= x"c000";
when "10" & x"f9c" => DATA <= x"dd7f";
when "10" & x"f9d" => DATA <= x"bf74";
when "10" & x"f9e" => DATA <= x"01e6";
when "10" & x"f9f" => DATA <= x"ff78";
when "10" & x"fa0" => DATA <= x"f001";
when "10" & x"fa1" => DATA <= x"0000";
when "10" & x"fa2" => DATA <= x"b07f";
when "10" & x"fa3" => DATA <= x"be34";
when "10" & x"fa4" => DATA <= x"0190";
when "10" & x"fa5" => DATA <= x"ff75";
when "10" & x"fa6" => DATA <= x"f002";
when "10" & x"fa7" => DATA <= x"0000";
when "10" & x"fa8" => DATA <= x"c97f";
when "10" & x"fa9" => DATA <= x"bae8";
when "10" & x"faa" => DATA <= x"0280";
when "10" & x"fab" => DATA <= x"400d";
when "10" & x"fac" => DATA <= x"27fb";
when "10" & x"fad" => DATA <= x"3f40";
when "10" & x"fae" => DATA <= x"10ef";
when "10" & x"faf" => DATA <= x"f6ed";
when "10" & x"fb0" => DATA <= x"0050";
when "10" & x"fb1" => DATA <= x"1000";
when "10" & x"fb2" => DATA <= x"1aff";
when "10" & x"fb3" => DATA <= x"3de8";
when "10" & x"fb4" => DATA <= x"003d";
when "10" & x"fb5" => DATA <= x"fe1f";
when "10" & x"fb6" => DATA <= x"e000";
when "10" & x"fb7" => DATA <= x"6000";
when "10" & x"fb8" => DATA <= x"1cff";
when "10" & x"fb9" => DATA <= x"5ee8";
when "10" & x"fba" => DATA <= x"02f1";
when "10" & x"fbb" => DATA <= x"feae";
when "10" & x"fbc" => DATA <= x"a00a";
when "10" & x"fbd" => DATA <= x"1000";
when "10" & x"fbe" => DATA <= x"1b1f";
when "10" & x"fbf" => DATA <= x"efe0";
when "10" & x"fc0" => DATA <= x"00c3";
when "10" & x"fc1" => DATA <= x"800e";
when "10" & x"fc2" => DATA <= x"4ff7";
when "10" & x"fc3" => DATA <= x"d800";
when "10" & x"fc4" => DATA <= x"2620";
when "10" & x"fc5" => DATA <= x"3000";
when "10" & x"fc6" => DATA <= x"1e4f";
when "10" & x"fc7" => DATA <= x"f7d6";
when "10" & x"fc8" => DATA <= x"8039";
when "10" & x"fc9" => DATA <= x"1fef";
when "10" & x"fca" => DATA <= x"1d00";
when "10" & x"fcb" => DATA <= x"203f";
when "10" & x"fcc" => DATA <= x"d2a9";
when "10" & x"fcd" => DATA <= x"8000";
when "10" & x"fce" => DATA <= x"fa9f";
when "10" & x"fcf" => DATA <= x"a9fc";
when "10" & x"fd0" => DATA <= x"fcaf";
when "10" & x"fd1" => DATA <= x"1f80";
when "10" & x"fd2" => DATA <= x"41a4";
when "10" & x"fd3" => DATA <= x"0070";
when "10" & x"fd4" => DATA <= x"0120";
when "10" & x"fd5" => DATA <= x"ff00";
when "10" & x"fd6" => DATA <= x"809e";
when "10" & x"fd7" => DATA <= x"e000";
when "10" & x"fd8" => DATA <= x"1500";
when "10" & x"fd9" => DATA <= x"3fe8";
when "10" & x"fda" => DATA <= x"0033";
when "10" & x"fdb" => DATA <= x"4000";
when "10" & x"fdc" => DATA <= x"4203";
when "10" & x"fdd" => DATA <= x"fc88";
when "10" & x"fde" => DATA <= x"807f";
when "10" & x"fdf" => DATA <= x"8198";
when "10" & x"fe0" => DATA <= x"6f80";
when "10" & x"fe1" => DATA <= x"03fc";
when "10" & x"fe2" => DATA <= x"0080";
when "10" & x"fe3" => DATA <= x"013b";
when "10" & x"fe4" => DATA <= x"41e0";
when "10" & x"fe5" => DATA <= x"300b";
when "10" & x"fe6" => DATA <= x"fc00";
when "10" & x"fe7" => DATA <= x"88a0";
when "10" & x"fe8" => DATA <= x"f182";
when "10" & x"fe9" => DATA <= x"d1e2";
when "10" & x"fea" => DATA <= x"0f00";
when "10" & x"feb" => DATA <= x"11c0";
when "10" & x"fec" => DATA <= x"8000";
when "10" & x"fed" => DATA <= x"8700";
when "10" & x"fee" => DATA <= x"0228";
when "10" & x"fef" => DATA <= x"06c0";
when "10" & x"ff0" => DATA <= x"1542";
when "10" & x"ff1" => DATA <= x"8d00";
when "10" & x"ff2" => DATA <= x"1000";
when "10" & x"ff3" => DATA <= x"0800";
when "10" & x"ff4" => DATA <= x"000d";
when "10" & x"ff5" => DATA <= x"0007";
when "10" & x"ff6" => DATA <= x"8094";
when "10" & x"ff7" => DATA <= x"2ba0";
when "10" & x"ff8" => DATA <= x"0040";
when "10" & x"ff9" => DATA <= x"7031";
when "10" & x"ffa" => DATA <= x"f9e0";
when "10" & x"ffb" => DATA <= x"0ffe";
when "10" & x"ffc" => DATA <= x"00a8";
when "10" & x"ffd" => DATA <= x"0a01";
when "10" & x"ffe" => DATA <= x"02c8";
when "10" & x"fff" => DATA <= x"000c";
when "11" & x"000" => DATA <= x"a010";
when "11" & x"001" => DATA <= x"4078";
when "11" & x"002" => DATA <= x"000b";
when "11" & x"003" => DATA <= x"8000";
when "11" & x"004" => DATA <= x"4000";
when "11" & x"005" => DATA <= x"5700";
when "11" & x"006" => DATA <= x"2815";
when "11" & x"007" => DATA <= x"5200";
when "11" & x"008" => DATA <= x"a0ae";
when "11" & x"009" => DATA <= x"a742";
when "11" & x"00a" => DATA <= x"0000";
when "11" & x"00b" => DATA <= x"f339";
when "11" & x"00c" => DATA <= x"d799";
when "11" & x"00d" => DATA <= x"cde6";
when "11" & x"00e" => DATA <= x"6321";
when "11" & x"00f" => DATA <= x"a094";
when "11" & x"010" => DATA <= x"5d54";
when "11" & x"011" => DATA <= x"8a44";
when "11" & x"012" => DATA <= x"202d";
when "11" & x"013" => DATA <= x"fc8e";
when "11" & x"014" => DATA <= x"7f00";
when "11" & x"015" => DATA <= x"3158";
when "11" & x"016" => DATA <= x"2380";
when "11" & x"017" => DATA <= x"c3e0";
when "11" & x"018" => DATA <= x"0010";
when "11" & x"019" => DATA <= x"7e3f";
when "11" & x"01a" => DATA <= x"c060";
when "11" & x"01b" => DATA <= x"0783";
when "11" & x"01c" => DATA <= x"fe80";
when "11" & x"01d" => DATA <= x"1020";
when "11" & x"01e" => DATA <= x"7003";
when "11" & x"01f" => DATA <= x"fabf";
when "11" & x"020" => DATA <= x"dc08";
when "11" & x"021" => DATA <= x"007b";
when "11" & x"022" => DATA <= x"8001";
when "11" & x"023" => DATA <= x"bfe8";
when "11" & x"024" => DATA <= x"07fb";
when "11" & x"025" => DATA <= x"437f";
when "11" & x"026" => DATA <= x"ec06";
when "11" & x"027" => DATA <= x"9040";
when "11" & x"028" => DATA <= x"1468";
when "11" & x"029" => DATA <= x"36a3";
when "11" & x"02a" => DATA <= x"4a36";
when "11" & x"02b" => DATA <= x"7a7f";
when "11" & x"02c" => DATA <= x"ff1f";
when "11" & x"02d" => DATA <= x"83e4";
when "11" & x"02e" => DATA <= x"febf";
when "11" & x"02f" => DATA <= x"3c01";
when "11" & x"030" => DATA <= x"ff60";
when "11" & x"031" => DATA <= x"0e66";
when "11" & x"032" => DATA <= x"7b98";
when "11" & x"033" => DATA <= x"015c";
when "11" & x"034" => DATA <= x"0407";
when "11" & x"035" => DATA <= x"706c";
when "11" & x"036" => DATA <= x"3e9f";
when "11" & x"037" => DATA <= x"0fd4";
when "11" & x"038" => DATA <= x"f87d";
when "11" & x"039" => DATA <= x"3ed5";
when "11" & x"03a" => DATA <= x"6837";
when "11" & x"03b" => DATA <= x"1baf";
when "11" & x"03c" => DATA <= x"53eb";
when "11" & x"03d" => DATA <= x"e4e0";
when "11" & x"03e" => DATA <= x"f4ef";
when "11" & x"03f" => DATA <= x"078b";
when "11" & x"040" => DATA <= x"cebf";
when "11" & x"041" => DATA <= x"d803";
when "11" & x"042" => DATA <= x"0002";
when "11" & x"043" => DATA <= x"0160";
when "11" & x"044" => DATA <= x"340a";
when "11" & x"045" => DATA <= x"031a";
when "11" & x"046" => DATA <= x"c00a";
when "11" & x"047" => DATA <= x"1049";
when "11" & x"048" => DATA <= x"b416";
when "11" & x"049" => DATA <= x"0e30";
when "11" & x"04a" => DATA <= x"08d0";
when "11" & x"04b" => DATA <= x"e844";
when "11" & x"04c" => DATA <= x"002e";
when "11" & x"04d" => DATA <= x"2bfe";
when "11" & x"04e" => DATA <= x"8100";
when "11" & x"04f" => DATA <= x"0fc0";
when "11" & x"050" => DATA <= x"03de";
when "11" & x"051" => DATA <= x"bff8";
when "11" & x"052" => DATA <= x"01fc";
when "11" & x"053" => DATA <= x"b87f";
when "11" & x"054" => DATA <= x"aede";
when "11" & x"055" => DATA <= x"5400";
when "11" & x"056" => DATA <= x"8006";
when "11" & x"057" => DATA <= x"9e88";
when "11" & x"058" => DATA <= x"04a6";
when "11" & x"059" => DATA <= x"5001";
when "11" & x"05a" => DATA <= x"2efe";
when "11" & x"05b" => DATA <= x"4438";
when "11" & x"05c" => DATA <= x"7bbc";
when "11" & x"05d" => DATA <= x"00b4";
when "11" & x"05e" => DATA <= x"7abf";
when "11" & x"05f" => DATA <= x"eaf4";
when "11" & x"060" => DATA <= x"7e3d";
when "11" & x"061" => DATA <= x"a002";
when "11" & x"062" => DATA <= x"dd3d";
when "11" & x"063" => DATA <= x"8280";
when "11" & x"064" => DATA <= x"5c00";
when "11" & x"065" => DATA <= x"07d0";
when "11" & x"066" => DATA <= x"0aa0";
when "11" & x"067" => DATA <= x"583e";
when "11" & x"068" => DATA <= x"2400";
when "11" & x"069" => DATA <= x"8280";
when "11" & x"06a" => DATA <= x"1800";
when "11" & x"06b" => DATA <= x"5a1c";
when "11" & x"06c" => DATA <= x"0004";
when "11" & x"06d" => DATA <= x"04b0";
when "11" & x"06e" => DATA <= x"0000";
when "11" & x"06f" => DATA <= x"a415";
when "11" & x"070" => DATA <= x"0000";
when "11" & x"071" => DATA <= x"814d";
when "11" & x"072" => DATA <= x"0602";
when "11" & x"073" => DATA <= x"8421";
when "11" & x"074" => DATA <= x"c00d";
when "11" & x"075" => DATA <= x"00bb";
when "11" & x"076" => DATA <= x"0000";
when "11" & x"077" => DATA <= x"04e0";
when "11" & x"078" => DATA <= x"0398";
when "11" & x"079" => DATA <= x"55c0";
when "11" & x"07a" => DATA <= x"0390";
when "11" & x"07b" => DATA <= x"0728";
when "11" & x"07c" => DATA <= x"d454";
when "11" & x"07d" => DATA <= x"fbe0";
when "11" & x"07e" => DATA <= x"0300";
when "11" & x"07f" => DATA <= x"e380";
when "11" & x"080" => DATA <= x"7800";
when "11" & x"081" => DATA <= x"1415";
when "11" & x"082" => DATA <= x"e001";
when "11" & x"083" => DATA <= x"4700";
when "11" & x"084" => DATA <= x"0228";
when "11" & x"085" => DATA <= x"0281";
when "11" & x"086" => DATA <= x"2800";
when "11" & x"087" => DATA <= x"1415";
when "11" & x"088" => DATA <= x"e000";
when "11" & x"089" => DATA <= x"2500";
when "11" & x"08a" => DATA <= x"0a8a";
when "11" & x"08b" => DATA <= x"b600";
when "11" & x"08c" => DATA <= x"3c18";
when "11" & x"08d" => DATA <= x"0a0c";
when "11" & x"08e" => DATA <= x"0c27";
when "11" & x"08f" => DATA <= x"d508";
when "11" & x"090" => DATA <= x"7001";
when "11" & x"091" => DATA <= x"5280";
when "11" & x"092" => DATA <= x"6c00";
when "11" & x"093" => DATA <= x"de0e";
when "11" & x"094" => DATA <= x"2718";
when "11" & x"095" => DATA <= x"3801";
when "11" & x"096" => DATA <= x"fe03";
when "11" & x"097" => DATA <= x"0080";
when "11" & x"098" => DATA <= x"005c";
when "11" & x"099" => DATA <= x"00ff";
when "11" & x"09a" => DATA <= x"a04d";
when "11" & x"09b" => DATA <= x"007f";
when "11" & x"09c" => DATA <= x"e800";
when "11" & x"09d" => DATA <= x"8004";
when "11" & x"09e" => DATA <= x"ffb0";
when "11" & x"09f" => DATA <= x"0183";
when "11" & x"0a0" => DATA <= x"fe82";
when "11" & x"0a1" => DATA <= x"3801";
when "11" & x"0a2" => DATA <= x"800d";
when "11" & x"0a3" => DATA <= x"7f88";
when "11" & x"0a4" => DATA <= x"2401";
when "11" & x"0a5" => DATA <= x"8e00";
when "11" & x"0a6" => DATA <= x"7fe8";
when "11" & x"0a7" => DATA <= x"000c";
when "11" & x"0a8" => DATA <= x"84ff";
when "11" & x"0a9" => DATA <= x"0091";
when "11" & x"0aa" => DATA <= x"3800";
when "11" & x"0ab" => DATA <= x"c000";
when "11" & x"0ac" => DATA <= x"7ff0";
when "11" & x"0ad" => DATA <= x"0008";
when "11" & x"0ae" => DATA <= x"0003";
when "11" & x"0af" => DATA <= x"003f";
when "11" & x"0b0" => DATA <= x"e800";
when "11" & x"0b1" => DATA <= x"0200";
when "11" & x"0b2" => DATA <= x"0110";
when "11" & x"0b3" => DATA <= x"900f";
when "11" & x"0b4" => DATA <= x"fd00";
when "11" & x"0b5" => DATA <= x"00b0";
when "11" & x"0b6" => DATA <= x"5ff3";
when "11" & x"0b7" => DATA <= x"c140";
when "11" & x"0b8" => DATA <= x"0c9e";
when "11" & x"0b9" => DATA <= x"cb25";
when "11" & x"0ba" => DATA <= x"0228";
when "11" & x"0bb" => DATA <= x"0004";
when "11" & x"0bc" => DATA <= x"05a0";
when "11" & x"0bd" => DATA <= x"1027";
when "11" & x"0be" => DATA <= x"003c";
when "11" & x"0bf" => DATA <= x"1815";
when "11" & x"0c0" => DATA <= x"0010";
when "11" & x"0c1" => DATA <= x"e00a";
when "11" & x"0c2" => DATA <= x"0100";
when "11" & x"0c3" => DATA <= x"560b";
when "11" & x"0c4" => DATA <= x"0380";
when "11" & x"0c5" => DATA <= x"2a03";
when "11" & x"0c6" => DATA <= x"403a";
when "11" & x"0c7" => DATA <= x"0180";
when "11" & x"0c8" => DATA <= x"f07b";
when "11" & x"0c9" => DATA <= x"af47";
when "11" & x"0ca" => DATA <= x"c8f0";
when "11" & x"0cb" => DATA <= x"1b7d";
when "11" & x"0cc" => DATA <= x"a2e3";
when "11" & x"0cd" => DATA <= x"3416";
when "11" & x"0ce" => DATA <= x"432f";
when "11" & x"0cf" => DATA <= x"900b";
when "11" & x"0d0" => DATA <= x"f5e0";
when "11" & x"0d1" => DATA <= x"f13f";
when "11" & x"0d2" => DATA <= x"9bc5";
when "11" & x"0d3" => DATA <= x"6efe";
when "11" & x"0d4" => DATA <= x"f070";
when "11" & x"0d5" => DATA <= x"3c01";
when "11" & x"0d6" => DATA <= x"a100";
when "11" & x"0d7" => DATA <= x"2702";
when "11" & x"0d8" => DATA <= x"bd87";
when "11" & x"0d9" => DATA <= x"f608";
when "11" & x"0da" => DATA <= x"b400";
when "11" & x"0db" => DATA <= x"0438";
when "11" & x"0dc" => DATA <= x"0283";
when "11" & x"0dd" => DATA <= x"0afa";
when "11" & x"0de" => DATA <= x"0141";
when "11" & x"0df" => DATA <= x"03b0";
when "11" & x"0e0" => DATA <= x"1821";
when "11" & x"0e1" => DATA <= x"71d5";
when "11" & x"0e2" => DATA <= x"0081";
when "11" & x"0e3" => DATA <= x"7830";
when "11" & x"0e4" => DATA <= x"00f7";
when "11" & x"0e5" => DATA <= x"6abd";
when "11" & x"0e6" => DATA <= x"1fe0";
when "11" & x"0e7" => DATA <= x"07a3";
when "11" & x"0e8" => DATA <= x"e040";
when "11" & x"0e9" => DATA <= x"2ba2";
when "11" & x"0ea" => DATA <= x"f379";
when "11" & x"0eb" => DATA <= x"009e";
when "11" & x"0ec" => DATA <= x"7f60";
when "11" & x"0ed" => DATA <= x"0025";
when "11" & x"0ee" => DATA <= x"00b2";
when "11" & x"0ef" => DATA <= x"5c20";
when "11" & x"0f0" => DATA <= x"0448";
when "11" & x"0f1" => DATA <= x"000a";
when "11" & x"0f2" => DATA <= x"402c";
when "11" & x"0f3" => DATA <= x"9600";
when "11" & x"0f4" => DATA <= x"001a";
when "11" & x"0f5" => DATA <= x"00a4";
when "11" & x"0f6" => DATA <= x"07d8";
when "11" & x"0f7" => DATA <= x"52e0";
when "11" & x"0f8" => DATA <= x"164b";
when "11" & x"0f9" => DATA <= x"1b01";
when "11" & x"0fa" => DATA <= x"0180";
when "11" & x"0fb" => DATA <= x"7800";
when "11" & x"0fc" => DATA <= x"2140";
when "11" & x"0fd" => DATA <= x"0552";
when "11" & x"0fe" => DATA <= x"0580";
when "11" & x"0ff" => DATA <= x"2850";
when "11" & x"100" => DATA <= x"2001";
when "11" & x"101" => DATA <= x"0000";
when "11" & x"102" => DATA <= x"0400";
when "11" & x"103" => DATA <= x"050a";
when "11" & x"104" => DATA <= x"9456";
when "11" & x"105" => DATA <= x"0040";
when "11" & x"106" => DATA <= x"0030";
when "11" & x"107" => DATA <= x"9048";
when "11" & x"108" => DATA <= x"3015";
when "11" & x"109" => DATA <= x"4122";
when "11" & x"10a" => DATA <= x"d068";
when "11" & x"10b" => DATA <= x"8457";
when "11" & x"10c" => DATA <= x"4054";
when "11" & x"10d" => DATA <= x"52a8";
when "11" & x"10e" => DATA <= x"9f4f";
when "11" & x"10f" => DATA <= x"e7b7";
when "11" & x"110" => DATA <= x"fd3f";
when "11" & x"111" => DATA <= x"95c0";
when "11" & x"112" => DATA <= x"0f10";
when "11" & x"113" => DATA <= x"0a20";
when "11" & x"114" => DATA <= x"04fc";
when "11" & x"115" => DATA <= x"7c50";
when "11" & x"116" => DATA <= x"000c";
when "11" & x"117" => DATA <= x"0001";
when "11" & x"118" => DATA <= x"003f";
when "11" & x"119" => DATA <= x"c1e0";
when "11" & x"11a" => DATA <= x"0202";
when "11" & x"11b" => DATA <= x"0000";
when "11" & x"11c" => DATA <= x"e970";
when "11" & x"11d" => DATA <= x"1fe8";
when "11" & x"11e" => DATA <= x"037f";
when "11" & x"11f" => DATA <= x"c066";
when "11" & x"120" => DATA <= x"0006";
when "11" & x"121" => DATA <= x"ffb8";
when "11" & x"122" => DATA <= x"1fa5";
when "11" & x"123" => DATA <= x"8009";
when "11" & x"124" => DATA <= x"06c0";
when "11" & x"125" => DATA <= x"4683";
when "11" & x"126" => DATA <= x"6e00";
when "11" & x"127" => DATA <= x"1851";
when "11" & x"128" => DATA <= x"b57f";
when "11" & x"129" => DATA <= x"d004";
when "11" & x"12a" => DATA <= x"ff8f";
when "11" & x"12b" => DATA <= x"c020";
when "11" & x"12c" => DATA <= x"05f4";
when "11" & x"12d" => DATA <= x"dfbf";
when "11" & x"12e" => DATA <= x"2802";
when "11" & x"12f" => DATA <= x"bff8";
when "11" & x"130" => DATA <= x"01fe";
when "11" & x"131" => DATA <= x"fc40";
when "11" & x"132" => DATA <= x"001f";
when "11" & x"133" => DATA <= x"fc00";
when "11" & x"134" => DATA <= x"cf63";
when "11" & x"135" => DATA <= x"b9d8";
when "11" & x"136" => DATA <= x"15c0";
when "11" & x"137" => DATA <= x"0070";
when "11" & x"138" => DATA <= x"07c3";
when "11" & x"139" => DATA <= x"69f0";
when "11" & x"13a" => DATA <= x"f878";
when "11" & x"13b" => DATA <= x"3e1e";
when "11" & x"13c" => DATA <= x"0f86";
when "11" & x"13d" => DATA <= x"0a80";
when "11" & x"13e" => DATA <= x"5a46";
when "11" & x"13f" => DATA <= x"2456";
when "11" & x"140" => DATA <= x"2be5";
when "11" & x"141" => DATA <= x"fee0";
when "11" & x"142" => DATA <= x"0400";
when "11" & x"143" => DATA <= x"1ff5";
when "11" & x"144" => DATA <= x"7e01";
when "11" & x"145" => DATA <= x"659f";
when "11" & x"146" => DATA <= x"cf07";
when "11" & x"147" => DATA <= x"07e3";
when "11" & x"148" => DATA <= x"ddec";
when "11" & x"149" => DATA <= x"4c7f";
when "11" & x"14a" => DATA <= x"d803";
when "11" & x"14b" => DATA <= x"89fd";
when "11" & x"14c" => DATA <= x"200e";
when "11" & x"14d" => DATA <= x"0783";
when "11" & x"14e" => DATA <= x"5ddf";
when "11" & x"14f" => DATA <= x"c00e";
when "11" & x"150" => DATA <= x"a351";
when "11" & x"151" => DATA <= x"2ea1";
when "11" & x"152" => DATA <= x"b808";
when "11" & x"153" => DATA <= x"0cfe";
when "11" & x"154" => DATA <= x"6552";
when "11" & x"155" => DATA <= x"5c80";
when "11" & x"156" => DATA <= x"0040";
when "11" & x"157" => DATA <= x"15df";
when "11" & x"158" => DATA <= x"21c0";
when "11" & x"159" => DATA <= x"3005";
when "11" & x"15a" => DATA <= x"1ed8";
when "11" & x"15b" => DATA <= x"0032";
when "11" & x"15c" => DATA <= x"4010";
when "11" & x"15d" => DATA <= x"0f00";
when "11" & x"15e" => DATA <= x"2700";
when "11" & x"15f" => DATA <= x"3004";
when "11" & x"160" => DATA <= x"0007";
when "11" & x"161" => DATA <= x"79e8";
when "11" & x"162" => DATA <= x"403c";
when "11" & x"163" => DATA <= x"000e";
when "11" & x"164" => DATA <= x"47e0";
when "11" & x"165" => DATA <= x"07fb";
when "11" & x"166" => DATA <= x"0780";
when "11" & x"167" => DATA <= x"1014";
when "11" & x"168" => DATA <= x"0080";
when "11" & x"169" => DATA <= x"0020";
when "11" & x"16a" => DATA <= x"2801";
when "11" & x"16b" => DATA <= x"0140";
when "11" & x"16c" => DATA <= x"0800";
when "11" & x"16d" => DATA <= x"0143";
when "11" & x"16e" => DATA <= x"c028";
when "11" & x"16f" => DATA <= x"0009";
when "11" & x"170" => DATA <= x"a000";
when "11" & x"171" => DATA <= x"8f00";
when "11" & x"172" => DATA <= x"f00f";
when "11" & x"173" => DATA <= x"00f0";
when "11" & x"174" => DATA <= x"0e00";
when "11" & x"175" => DATA <= x"2250";
when "11" & x"176" => DATA <= x"0012";
when "11" & x"177" => DATA <= x"8000";
when "11" & x"178" => DATA <= x"8000";
when "11" & x"179" => DATA <= x"2780";
when "11" & x"17a" => DATA <= x"017c";
when "11" & x"17b" => DATA <= x"0030";
when "11" & x"17c" => DATA <= x"1048";
when "11" & x"17d" => DATA <= x"0628";
when "11" & x"17e" => DATA <= x"4030";
when "11" & x"17f" => DATA <= x"10a0";
when "11" & x"180" => DATA <= x"0058";
when "11" & x"181" => DATA <= x"0a80";
when "11" & x"182" => DATA <= x"0600";
when "11" & x"183" => DATA <= x"0140";
when "11" & x"184" => DATA <= x"0002";
when "11" & x"185" => DATA <= x"13f0";
when "11" & x"186" => DATA <= x"0d00";
when "11" & x"187" => DATA <= x"0250";
when "11" & x"188" => DATA <= x"0012";
when "11" & x"189" => DATA <= x"8000";
when "11" & x"18a" => DATA <= x"9e01";
when "11" & x"18b" => DATA <= x"4002";
when "11" & x"18c" => DATA <= x"0f00";
when "11" & x"18d" => DATA <= x"e000";
when "11" & x"18e" => DATA <= x"4500";
when "11" & x"18f" => DATA <= x"023c";
when "11" & x"190" => DATA <= x"0041";
when "11" & x"191" => DATA <= x"e014";
when "11" & x"192" => DATA <= x"0095";
when "11" & x"193" => DATA <= x"0004";
when "11" & x"194" => DATA <= x"0234";
when "11" & x"195" => DATA <= x"0001";
when "11" & x"196" => DATA <= x"f00e";
when "11" & x"197" => DATA <= x"0010";
when "11" & x"198" => DATA <= x"807c";
when "11" & x"199" => DATA <= x"0340";
when "11" & x"19a" => DATA <= x"021d";
when "11" & x"19b" => DATA <= x"c000";
when "11" & x"19c" => DATA <= x"1050";
when "11" & x"19d" => DATA <= x"0081";
when "11" & x"19e" => DATA <= x"f8fd";
when "11" & x"19f" => DATA <= x"7f80";
when "11" & x"1a0" => DATA <= x"0214";
when "11" & x"1a1" => DATA <= x"0010";
when "11" & x"1a2" => DATA <= x"4fd7";
when "11" & x"1a3" => DATA <= x"fe80";
when "11" & x"1a4" => DATA <= x"3993";
when "11" & x"1a5" => DATA <= x"eff0";
when "11" & x"1a6" => DATA <= x"0013";
when "11" & x"1a7" => DATA <= x"803b";
when "11" & x"1a8" => DATA <= x"fc00";
when "11" & x"1a9" => DATA <= x"20a0";
when "11" & x"1aa" => DATA <= x"0100";
when "11" & x"1ab" => DATA <= x"02bf";
when "11" & x"1ac" => DATA <= x"f401";
when "11" & x"1ad" => DATA <= x"cebf";
when "11" & x"1ae" => DATA <= x"7fc8";
when "11" & x"1af" => DATA <= x"0009";
when "11" & x"1b0" => DATA <= x"da9f";
when "11" & x"1b1" => DATA <= x"7fe8";
when "11" & x"1b2" => DATA <= x"010d";
when "11" & x"1b3" => DATA <= x"067f";
when "11" & x"1b4" => DATA <= x"d60a";
when "11" & x"1b5" => DATA <= x"007a";
when "11" & x"1b6" => DATA <= x"f802";
when "11" & x"1b7" => DATA <= x"f740";
when "11" & x"1b8" => DATA <= x"0040";
when "11" & x"1b9" => DATA <= x"001f";
when "11" & x"1ba" => DATA <= x"8058";
when "11" & x"1bb" => DATA <= x"00f0";
when "11" & x"1bc" => DATA <= x"005f";
when "11" & x"1bd" => DATA <= x"d000";
when "11" & x"1be" => DATA <= x"63b0";
when "11" & x"1bf" => DATA <= x"1741";
when "11" & x"1c0" => DATA <= x"0f8a";
when "11" & x"1c1" => DATA <= x"007e";
when "11" & x"1c2" => DATA <= x"bff8";
when "11" & x"1c3" => DATA <= x"01fe";
when "11" & x"1c4" => DATA <= x"0040";
when "11" & x"1c5" => DATA <= x"1fcb";
when "11" & x"1c6" => DATA <= x"fc00";
when "11" & x"1c7" => DATA <= x"ff00";
when "11" & x"1c8" => DATA <= x"0fc3";
when "11" & x"1c9" => DATA <= x"8783";
when "11" & x"1ca" => DATA <= x"e500";
when "11" & x"1cb" => DATA <= x"3fc0";
when "11" & x"1cc" => DATA <= x"0f46";
when "11" & x"1cd" => DATA <= x"c0a2";
when "11" & x"1ce" => DATA <= x"be00";
when "11" & x"1cf" => DATA <= x"03f1";
when "11" & x"1d0" => DATA <= x"c1e5";
when "11" & x"1d1" => DATA <= x"e8b0";
when "11" & x"1d2" => DATA <= x"5a3d";
when "11" & x"1d3" => DATA <= x"1e14";
when "11" & x"1d4" => DATA <= x"008e";
when "11" & x"1d5" => DATA <= x"48a0";
when "11" & x"1d6" => DATA <= x"5e07";
when "11" & x"1d7" => DATA <= x"1700";
when "11" & x"1d8" => DATA <= x"c280";
when "11" & x"1d9" => DATA <= x"002f";
when "11" & x"1da" => DATA <= x"f008";
when "11" & x"1db" => DATA <= x"0006";
when "11" & x"1dc" => DATA <= x"0200";
when "11" & x"1dd" => DATA <= x"0880";
when "11" & x"1de" => DATA <= x"0ffa";
when "11" & x"1df" => DATA <= x"0070";
when "11" & x"1e0" => DATA <= x"3e38";
when "11" & x"1e1" => DATA <= x"01ff";
when "11" & x"1e2" => DATA <= x"4014";
when "11" & x"1e3" => DATA <= x"fe00";
when "11" & x"1e4" => DATA <= x"7a00";
when "11" & x"1e5" => DATA <= x"1ff4";
when "11" & x"1e6" => DATA <= x"0040";
when "11" & x"1e7" => DATA <= x"0052";
when "11" & x"1e8" => DATA <= x"0001";
when "11" & x"1e9" => DATA <= x"ff50";
when "11" & x"1ea" => DATA <= x"0143";
when "11" & x"1eb" => DATA <= x"2210";
when "11" & x"1ec" => DATA <= x"a80a";
when "11" & x"1ed" => DATA <= x"47b4";
when "11" & x"1ee" => DATA <= x"5128";
when "11" & x"1ef" => DATA <= x"8402";
when "11" & x"1f0" => DATA <= x"2582";
when "11" & x"1f1" => DATA <= x"aa41";
when "11" & x"1f2" => DATA <= x"206a";
when "11" & x"1f3" => DATA <= x"aaa0";
when "11" & x"1f4" => DATA <= x"9567";
when "11" & x"1f5" => DATA <= x"ef7f";
when "11" & x"1f6" => DATA <= x"00b1";
when "11" & x"1f7" => DATA <= x"6800";
when "11" & x"1f8" => DATA <= x"05c0";
when "11" & x"1f9" => DATA <= x"0e07";
when "11" & x"1fa" => DATA <= x"fbf0";
when "11" & x"1fb" => DATA <= x"0940";
when "11" & x"1fc" => DATA <= x"0040";
when "11" & x"1fd" => DATA <= x"0547";
when "11" & x"1fe" => DATA <= x"a0ea";
when "11" & x"1ff" => DATA <= x"0001";
when "11" & x"200" => DATA <= x"501f";
when "11" & x"201" => DATA <= x"ffff";
when "11" & x"202" => DATA <= x"f5fe";
when "11" & x"203" => DATA <= x"0194";
when "11" & x"204" => DATA <= x"1a01";
when "11" & x"205" => DATA <= x"20f9";
when "11" & x"206" => DATA <= x"b002";
when "11" & x"207" => DATA <= x"ffc0";
when "11" & x"208" => DATA <= x"600a";
when "11" & x"209" => DATA <= x"3feb";
when "11" & x"20a" => DATA <= x"f008";
when "11" & x"20b" => DATA <= x"007d";
when "11" & x"20c" => DATA <= x"c00f";
when "11" & x"20d" => DATA <= x"f1f8";
when "11" & x"20e" => DATA <= x"0078";
when "11" & x"20f" => DATA <= x"fce0";
when "11" & x"210" => DATA <= x"03f9";
when "11" & x"211" => DATA <= x"f900";
when "11" & x"212" => DATA <= x"007f";
when "11" & x"213" => DATA <= x"b888";
when "11" & x"214" => DATA <= x"0e06";
when "11" & x"215" => DATA <= x"0381";
when "11" & x"216" => DATA <= x"c6e7";
when "11" & x"217" => DATA <= x"77a7";
when "11" & x"218" => DATA <= x"e87c";
when "11" & x"219" => DATA <= x"3c17";
when "11" & x"21a" => DATA <= x"4f86";
when "11" & x"21b" => DATA <= x"c3f4";
when "11" & x"21c" => DATA <= x"8ac4";
when "11" & x"21d" => DATA <= x"a446";
when "11" & x"21e" => DATA <= x"2915";
when "11" & x"21f" => DATA <= x"81f7";
when "11" & x"220" => DATA <= x"ebf7";
when "11" & x"221" => DATA <= x"b9dd";
when "11" & x"222" => DATA <= x"eb5e";
when "11" & x"223" => DATA <= x"e777";
when "11" & x"224" => DATA <= x"bbf0";
when "11" & x"225" => DATA <= x"3cff";
when "11" & x"226" => DATA <= x"0f00";
when "11" & x"227" => DATA <= x"120b";
when "11" & x"228" => DATA <= x"caff";
when "11" & x"229" => DATA <= x"7838";
when "11" & x"22a" => DATA <= x"5f0f";
when "11" & x"22b" => DATA <= x"07f8";
when "11" & x"22c" => DATA <= x"1cbe";
when "11" & x"22d" => DATA <= x"ff0b";
when "11" & x"22e" => DATA <= x"8028";
when "11" & x"22f" => DATA <= x"05fe";
when "11" & x"230" => DATA <= x"007e";
when "11" & x"231" => DATA <= x"bfc0";
when "11" & x"232" => DATA <= x"0200";
when "11" & x"233" => DATA <= x"0200";
when "11" & x"234" => DATA <= x"0e00";
when "11" & x"235" => DATA <= x"2fbf";
when "11" & x"236" => DATA <= x"c000";
when "11" & x"237" => DATA <= x"4000";
when "11" & x"238" => DATA <= x"15fc";
when "11" & x"239" => DATA <= x"0ea0";
when "11" & x"23a" => DATA <= x"f000";
when "11" & x"23b" => DATA <= x"1280";
when "11" & x"23c" => DATA <= x"1fe0";
when "11" & x"23d" => DATA <= x"4a00";
when "11" & x"23e" => DATA <= x"4050";
when "11" & x"23f" => DATA <= x"0081";
when "11" & x"240" => DATA <= x"fe48";
when "11" & x"241" => DATA <= x"a000";
when "11" & x"242" => DATA <= x"0d00";
when "11" & x"243" => DATA <= x"081f";
when "11" & x"244" => DATA <= x"e02a";
when "11" & x"245" => DATA <= x"0048";
when "11" & x"246" => DATA <= x"0810";
when "11" & x"247" => DATA <= x"0c07";
when "11" & x"248" => DATA <= x"f9b0";
when "11" & x"249" => DATA <= x"042f";
when "11" & x"24a" => DATA <= x"5800";
when "11" & x"24b" => DATA <= x"5c0f";
when "11" & x"24c" => DATA <= x"17ed";
when "11" & x"24d" => DATA <= x"0200";
when "11" & x"24e" => DATA <= x"c00b";
when "11" & x"24f" => DATA <= x"f1f9";
when "11" & x"250" => DATA <= x"fdfe";
when "11" & x"251" => DATA <= x"0404";
when "11" & x"252" => DATA <= x"5003";
when "11" & x"253" => DATA <= x"ec00";
when "11" & x"254" => DATA <= x"100f";
when "11" & x"255" => DATA <= x"8207";
when "11" & x"256" => DATA <= x"4420";
when "11" & x"257" => DATA <= x"03fc";
when "11" & x"258" => DATA <= x"0080";
when "11" & x"259" => DATA <= x"7a00";
when "11" & x"25a" => DATA <= x"2820";
when "11" & x"25b" => DATA <= x"00ff";
when "11" & x"25c" => DATA <= x"402f";
when "11" & x"25d" => DATA <= x"dff2";
when "11" & x"25e" => DATA <= x"00ff";
when "11" & x"25f" => DATA <= x"1800";
when "11" & x"260" => DATA <= x"1832";
when "11" & x"261" => DATA <= x"00ff";
when "11" & x"262" => DATA <= x"a001";
when "11" & x"263" => DATA <= x"dc80";
when "11" & x"264" => DATA <= x"3fc4";
when "11" & x"265" => DATA <= x"4047";
when "11" & x"266" => DATA <= x"da03";
when "11" & x"267" => DATA <= x"801b";
when "11" & x"268" => DATA <= x"f400";
when "11" & x"269" => DATA <= x"017f";
when "11" & x"26a" => DATA <= x"f003";
when "11" & x"26b" => DATA <= x"7e80";
when "11" & x"26c" => DATA <= x"018f";
when "11" & x"26d" => DATA <= x"fe00";
when "11" & x"26e" => DATA <= x"7f90";
when "11" & x"26f" => DATA <= x"1000";
when "11" & x"270" => DATA <= x"07f8";
when "11" & x"271" => DATA <= x"014c";
when "11" & x"272" => DATA <= x"007f";
when "11" & x"273" => DATA <= x"8002";
when "11" & x"274" => DATA <= x"0003";
when "11" & x"275" => DATA <= x"f800";
when "11" & x"276" => DATA <= x"1010";
when "11" & x"277" => DATA <= x"0fb0";
when "11" & x"278" => DATA <= x"580f";
when "11" & x"279" => DATA <= x"f56f";
when "11" & x"27a" => DATA <= x"003f";
when "11" & x"27b" => DATA <= x"1fe7";
when "11" & x"27c" => DATA <= x"f67b";
when "11" & x"27d" => DATA <= x"f380";
when "11" & x"27e" => DATA <= x"0a65";
when "11" & x"27f" => DATA <= x"b058";
when "11" & x"280" => DATA <= x"10fc";
when "11" & x"281" => DATA <= x"01a0";
when "11" & x"282" => DATA <= x"007d";
when "11" & x"283" => DATA <= x"7f88";
when "11" & x"284" => DATA <= x"0944";
when "11" & x"285" => DATA <= x"0080";
when "11" & x"286" => DATA <= x"0130";
when "11" & x"287" => DATA <= x"6379";
when "11" & x"288" => DATA <= x"3c00";
when "11" & x"289" => DATA <= x"2004";
when "11" & x"28a" => DATA <= x"0000";
when "11" & x"28b" => DATA <= x"0340";
when "11" & x"28c" => DATA <= x"0070";
when "11" & x"28d" => DATA <= x"1800";
when "11" & x"28e" => DATA <= x"0740";
when "11" & x"28f" => DATA <= x"0274";
when "11" & x"290" => DATA <= x"187d";
when "11" & x"291" => DATA <= x"fe00";
when "11" & x"292" => DATA <= x"0800";
when "11" & x"293" => DATA <= x"0102";
when "11" & x"294" => DATA <= x"5060";
when "11" & x"295" => DATA <= x"1002";
when "11" & x"296" => DATA <= x"0464";
when "11" & x"297" => DATA <= x"8015";
when "11" & x"298" => DATA <= x"0043";
when "11" & x"299" => DATA <= x"5021";
when "11" & x"29a" => DATA <= x"e26c";
when "11" & x"29b" => DATA <= x"4000";
when "11" & x"29c" => DATA <= x"0049";
when "11" & x"29d" => DATA <= x"9a00";
when "11" & x"29e" => DATA <= x"7fd6";
when "11" & x"29f" => DATA <= x"f801";
when "11" & x"2a0" => DATA <= x"ead4";
when "11" & x"2a1" => DATA <= x"6850";
when "11" & x"2a2" => DATA <= x"057a";
when "11" & x"2a3" => DATA <= x"0001";
when "11" & x"2a4" => DATA <= x"6110";
when "11" & x"2a5" => DATA <= x"c070";
when "11" & x"2a6" => DATA <= x"0cf0";
when "11" & x"2a7" => DATA <= x"0378";
when "11" & x"2a8" => DATA <= x"0302";
when "11" & x"2a9" => DATA <= x"800f";
when "11" & x"2aa" => DATA <= x"80d0";
when "11" & x"2ab" => DATA <= x"0040";
when "11" & x"2ac" => DATA <= x"00ff";
when "11" & x"2ad" => DATA <= x"a001";
when "11" & x"2ae" => DATA <= x"1500";
when "11" & x"2af" => DATA <= x"0800";
when "11" & x"2b0" => DATA <= x"007a";
when "11" & x"2b1" => DATA <= x"0008";
when "11" & x"2b2" => DATA <= x"4800";
when "11" & x"2b3" => DATA <= x"83c0";
when "11" & x"2b4" => DATA <= x"081e";
when "11" & x"2b5" => DATA <= x"0054";
when "11" & x"2b6" => DATA <= x"a004";
when "11" & x"2b7" => DATA <= x"0480";
when "11" & x"2b8" => DATA <= x"1068";
when "11" & x"2b9" => DATA <= x"0081";
when "11" & x"2ba" => DATA <= x"c004";
when "11" & x"2bb" => DATA <= x"030d";
when "11" & x"2bc" => DATA <= x"0000";
when "11" & x"2bd" => DATA <= x"a800";
when "11" & x"2be" => DATA <= x"0400";
when "11" & x"2bf" => DATA <= x"1850";
when "11" & x"2c0" => DATA <= x"0006";
when "11" & x"2c1" => DATA <= x"4003";
when "11" & x"2c2" => DATA <= x"dec0";
when "11" & x"2c3" => DATA <= x"6af0";
when "11" & x"2c4" => DATA <= x"0026";
when "11" & x"2c5" => DATA <= x"8010";
when "11" & x"2c6" => DATA <= x"0082";
when "11" & x"2c7" => DATA <= x"07f7";
when "11" & x"2c8" => DATA <= x"0e27";
when "11" & x"2c9" => DATA <= x"03c1";
when "11" & x"2ca" => DATA <= x"a0e3";
when "11" & x"2cb" => DATA <= x"ff80";
when "11" & x"2cc" => DATA <= x"03bc";
when "11" & x"2cd" => DATA <= x"00ff";
when "11" & x"2ce" => DATA <= x"d000";
when "11" & x"2cf" => DATA <= x"0801";
when "11" & x"2d0" => DATA <= x"ffe0";
when "11" & x"2d1" => DATA <= x"0ffb";
when "11" & x"2d2" => DATA <= x"0010";
when "11" & x"2d3" => DATA <= x"bfec";
when "11" & x"2d4" => DATA <= x"0020";
when "11" & x"2d5" => DATA <= x"fff0";
when "11" & x"2d6" => DATA <= x"07ff";
when "11" & x"2d7" => DATA <= x"0001";
when "11" & x"2d8" => DATA <= x"3801";
when "11" & x"2d9" => DATA <= x"fe00";
when "11" & x"2da" => DATA <= x"4068";
when "11" & x"2db" => DATA <= x"03fe";
when "11" & x"2dc" => DATA <= x"4000";
when "11" & x"2dd" => DATA <= x"5400";
when "11" & x"2de" => DATA <= x"ffb0";
when "11" & x"2df" => DATA <= x"0603";
when "11" & x"2e0" => DATA <= x"fff0";
when "11" & x"2e1" => DATA <= x"00e2";
when "11" & x"2e2" => DATA <= x"95d0";
when "11" & x"2e3" => DATA <= x"e576";
when "11" & x"2e4" => DATA <= x"2900";
when "11" & x"2e5" => DATA <= x"aee9";
when "11" & x"2e6" => DATA <= x"0082";
when "11" & x"2e7" => DATA <= x"4002";
when "11" & x"2e8" => DATA <= x"d000";
when "11" & x"2e9" => DATA <= x"5c28";
when "11" & x"2ea" => DATA <= x"806b";
when "11" & x"2eb" => DATA <= x"2000";
when "11" & x"2ec" => DATA <= x"0d57";
when "11" & x"2ed" => DATA <= x"ab55";
when "11" & x"2ee" => DATA <= x"51d5";
when "11" & x"2ef" => DATA <= x"2a85";
when "11" & x"2f0" => DATA <= x"7aad";
when "11" & x"2f1" => DATA <= x"9f50";
when "11" & x"2f2" => DATA <= x"0835";
when "11" & x"2f3" => DATA <= x"8a8d";
when "11" & x"2f4" => DATA <= x"e6a7";
when "11" & x"2f5" => DATA <= x"4597";
when "11" & x"2f6" => DATA <= x"edfc";
when "11" & x"2f7" => DATA <= x"8f40";
when "11" & x"2f8" => DATA <= x"0c56";
when "11" & x"2f9" => DATA <= x"0821";
when "11" & x"2fa" => DATA <= x"f8f8";
when "11" & x"2fb" => DATA <= x"0036";
when "11" & x"2fc" => DATA <= x"1f8f";
when "11" & x"2fd" => DATA <= x"f008";
when "11" & x"2fe" => DATA <= x"02bf";
when "11" & x"2ff" => DATA <= x"c000";
when "11" & x"300" => DATA <= x"4408";
when "11" & x"301" => DATA <= x"3e80";
when "11" & x"302" => DATA <= x"2bfd";
when "11" & x"303" => DATA <= x"c15f";
when "11" & x"304" => DATA <= x"eefa";
when "11" & x"305" => DATA <= x"005f";
when "11" & x"306" => DATA <= x"effb";
when "11" & x"307" => DATA <= x"e9f9";
when "11" & x"308" => DATA <= x"dfe4";
when "11" & x"309" => DATA <= x"1f01";
when "11" & x"30a" => DATA <= x"f000";
when "11" & x"30b" => DATA <= x"03c3";
when "11" & x"30c" => DATA <= x"ffc7";
when "11" & x"30d" => DATA <= x"e2fb";
when "11" & x"30e" => DATA <= x"3fb0";
when "11" & x"30f" => DATA <= x"0afc";
when "11" & x"310" => DATA <= x"b00a";
when "11" & x"311" => DATA <= x"ff73";
when "11" & x"312" => DATA <= x"002b";
when "11" & x"313" => DATA <= x"8080";
when "11" & x"314" => DATA <= x"e667";
when "11" & x"315" => DATA <= x"b1d3";
when "11" & x"316" => DATA <= x"f43e";
when "11" & x"317" => DATA <= x"9f0f";
when "11" & x"318" => DATA <= x"a7c3";
when "11" & x"319" => DATA <= x"e1b6";
when "11" & x"31a" => DATA <= x"2314";
when "11" & x"31b" => DATA <= x"0a45";
when "11" & x"31c" => DATA <= x"20d2";
when "11" & x"31d" => DATA <= x"0110";
when "11" & x"31e" => DATA <= x"ff57";
when "11" & x"31f" => DATA <= x"f4ff";
when "11" & x"320" => DATA <= x"dfe3";
when "11" & x"321" => DATA <= x"ca37";
when "11" & x"322" => DATA <= x"0c1f";
when "11" & x"323" => DATA <= x"1c60";
when "11" & x"324" => DATA <= x"7428";
when "11" & x"325" => DATA <= x"b380";
when "11" & x"326" => DATA <= x"090b";
when "11" & x"327" => DATA <= x"7401";
when "11" & x"328" => DATA <= x"041e";
when "11" & x"329" => DATA <= x"0008";
when "11" & x"32a" => DATA <= x"0004";
when "11" & x"32b" => DATA <= x"8f70";
when "11" & x"32c" => DATA <= x"2001";
when "11" & x"32d" => DATA <= x"fef8";
when "11" & x"32e" => DATA <= x"7e34";
when "11" & x"32f" => DATA <= x"1060";
when "11" & x"330" => DATA <= x"6430";
when "11" & x"331" => DATA <= x"027f";
when "11" & x"332" => DATA <= x"c3c0";
when "11" & x"333" => DATA <= x"0010";
when "11" & x"334" => DATA <= x"002e";
when "11" & x"335" => DATA <= x"02e1";
when "11" & x"336" => DATA <= x"f000";
when "11" & x"337" => DATA <= x"7838";
when "11" & x"338" => DATA <= x"1000";
when "11" & x"339" => DATA <= x"0104";
when "11" & x"33a" => DATA <= x"1e00";
when "11" & x"33b" => DATA <= x"f010";
when "11" & x"33c" => DATA <= x"8040";
when "11" & x"33d" => DATA <= x"6b80";
when "11" & x"33e" => DATA <= x"03fc";
when "11" & x"33f" => DATA <= x"00ff";
when "11" & x"340" => DATA <= x"2204";
when "11" & x"341" => DATA <= x"4021";
when "11" & x"342" => DATA <= x"1101";
when "11" & x"343" => DATA <= x"fc00";
when "11" & x"344" => DATA <= x"7e04";
when "11" & x"345" => DATA <= x"0880";
when "11" & x"346" => DATA <= x"4c30";
when "11" & x"347" => DATA <= x"80d0";
when "11" & x"348" => DATA <= x"00f4";
when "11" & x"349" => DATA <= x"e000";
when "11" & x"34a" => DATA <= x"1002";
when "11" & x"34b" => DATA <= x"805f";
when "11" & x"34c" => DATA <= x"bc00";
when "11" & x"34d" => DATA <= x"0300";
when "11" & x"34e" => DATA <= x"9040";
when "11" & x"34f" => DATA <= x"0ffa";
when "11" & x"350" => DATA <= x"0008";
when "11" & x"351" => DATA <= x"0481";
when "11" & x"352" => DATA <= x"8b87";
when "11" & x"353" => DATA <= x"600e";
when "11" & x"354" => DATA <= x"8000";
when "11" & x"355" => DATA <= x"4120";
when "11" & x"356" => DATA <= x"231c";
when "11" & x"357" => DATA <= x"4c08";
when "11" & x"358" => DATA <= x"e000";
when "11" & x"359" => DATA <= x"4000";
when "11" & x"35a" => DATA <= x"88f0";
when "11" & x"35b" => DATA <= x"0810";
when "11" & x"35c" => DATA <= x"0015";
when "11" & x"35d" => DATA <= x"0140";
when "11" & x"35e" => DATA <= x"0fa2";
when "11" & x"35f" => DATA <= x"03e0";
when "11" & x"360" => DATA <= x"00f0";
when "11" & x"361" => DATA <= x"e005";
when "11" & x"362" => DATA <= x"5808";
when "11" & x"363" => DATA <= x"0200";
when "11" & x"364" => DATA <= x"7fa3";
when "11" & x"365" => DATA <= x"2801";
when "11" & x"366" => DATA <= x"fe00";
when "11" & x"367" => DATA <= x"100d";
when "11" & x"368" => DATA <= x"100e";
when "11" & x"369" => DATA <= x"6101";
when "11" & x"36a" => DATA <= x"a1f2";
when "11" & x"36b" => DATA <= x"0062";
when "11" & x"36c" => DATA <= x"3440";
when "11" & x"36d" => DATA <= x"2627";
when "11" & x"36e" => DATA <= x"c001";
when "11" & x"36f" => DATA <= x"fe00";
when "11" & x"370" => DATA <= x"00af";
when "11" & x"371" => DATA <= x"6800";
when "11" & x"372" => DATA <= x"0208";
when "11" & x"373" => DATA <= x"7f80";
when "11" & x"374" => DATA <= x"0408";
when "11" & x"375" => DATA <= x"0000";
when "11" & x"376" => DATA <= x"4280";
when "11" & x"377" => DATA <= x"1fe0";
when "11" & x"378" => DATA <= x"0008";
when "11" & x"379" => DATA <= x"9240";
when "11" & x"37a" => DATA <= x"1fe0";
when "11" & x"37b" => DATA <= x"0008";
when "11" & x"37c" => DATA <= x"4421";
when "11" & x"37d" => DATA <= x"c00f";
when "11" & x"37e" => DATA <= x"f782";
when "11" & x"37f" => DATA <= x"c288";
when "11" & x"380" => DATA <= x"3800";
when "11" & x"381" => DATA <= x"2201";
when "11" & x"382" => DATA <= x"7b82";
when "11" & x"383" => DATA <= x"6801";
when "11" & x"384" => DATA <= x"00bc";
when "11" & x"385" => DATA <= x"5fa0";
when "11" & x"386" => DATA <= x"1fef";
when "11" & x"387" => DATA <= x"ba18";
when "11" & x"388" => DATA <= x"9030";
when "11" & x"389" => DATA <= x"3bbe";
when "11" & x"38a" => DATA <= x"4018";
when "11" & x"38b" => DATA <= x"0206";
when "11" & x"38c" => DATA <= x"e3f6";
when "11" & x"38d" => DATA <= x"8000";
when "11" & x"38e" => DATA <= x"2c00";
when "11" & x"38f" => DATA <= x"287c";
when "11" & x"390" => DATA <= x"aef7";
when "11" & x"391" => DATA <= x"138d";
when "11" & x"392" => DATA <= x"6401";
when "11" & x"393" => DATA <= x"9cff";
when "11" & x"394" => DATA <= x"0703";
when "11" & x"395" => DATA <= x"2b7d";
when "11" & x"396" => DATA <= x"80d0";
when "11" & x"397" => DATA <= x"aff7";
when "11" & x"398" => DATA <= x"b111";
when "11" & x"399" => DATA <= x"e8fc";
when "11" & x"39a" => DATA <= x"024f";
when "11" & x"39b" => DATA <= x"f8d1";
when "11" & x"39c" => DATA <= x"1ccf";
when "11" & x"39d" => DATA <= x"0057";
when "11" & x"39e" => DATA <= x"fa7c";
when "11" & x"39f" => DATA <= x"1a00";
when "11" & x"3a0" => DATA <= x"783f";
when "11" & x"3a1" => DATA <= x"c015";
when "11" & x"3a2" => DATA <= x"fe1f";
when "11" & x"3a3" => DATA <= x"0008";
when "11" & x"3a4" => DATA <= x"abfc";
when "11" & x"3a5" => DATA <= x"015f";
when "11" & x"3a6" => DATA <= x"ec04";
when "11" & x"3a7" => DATA <= x"0304";
when "11" & x"3a8" => DATA <= x"868f";
when "11" & x"3a9" => DATA <= x"003f";
when "11" & x"3aa" => DATA <= x"e47c";
when "11" & x"3ab" => DATA <= x"1000";
when "11" & x"3ac" => DATA <= x"083f";
when "11" & x"3ad" => DATA <= x"f400";
when "11" & x"3ae" => DATA <= x"0400";
when "11" & x"3af" => DATA <= x"7fc8";
when "11" & x"3b0" => DATA <= x"0281";
when "11" & x"3b1" => DATA <= x"5201";
when "11" & x"3b2" => DATA <= x"7f80";
when "11" & x"3b3" => DATA <= x"f806";
when "11" & x"3b4" => DATA <= x"a284";
when "11" & x"3b5" => DATA <= x"0ff1";
when "11" & x"3b6" => DATA <= x"8710";
when "11" & x"3b7" => DATA <= x"2108";
when "11" & x"3b8" => DATA <= x"4007";
when "11" & x"3b9" => DATA <= x"fc80";
when "11" & x"3ba" => DATA <= x"280a";
when "11" & x"3bb" => DATA <= x"2027";
when "11" & x"3bc" => DATA <= x"ff03";
when "11" & x"3bd" => DATA <= x"0081";
when "11" & x"3be" => DATA <= x"4050";
when "11" & x"3bf" => DATA <= x"03fe";
when "11" & x"3c0" => DATA <= x"400c";
when "11" & x"3c1" => DATA <= x"06a3";
when "11" & x"3c2" => DATA <= x"41fc";
when "11" & x"3c3" => DATA <= x"614e";
when "11" & x"3c4" => DATA <= x"0740";
when "11" & x"3c5" => DATA <= x"2d00";
when "11" & x"3c6" => DATA <= x"0428";
when "11" & x"3c7" => DATA <= x"0009";
when "11" & x"3c8" => DATA <= x"2000";
when "11" & x"3c9" => DATA <= x"c200";
when "11" & x"3ca" => DATA <= x"0140";
when "11" & x"3cb" => DATA <= x"c00f";
when "11" & x"3cc" => DATA <= x"50e1";
when "11" & x"3cd" => DATA <= x"783c";
when "11" & x"3ce" => DATA <= x"3c0e";
when "11" & x"3cf" => DATA <= x"07e8";
when "11" & x"3d0" => DATA <= x"0022";
when "11" & x"3d1" => DATA <= x"1000";
when "11" & x"3d2" => DATA <= x"0400";
when "11" & x"3d3" => DATA <= x"5200";
when "11" & x"3d4" => DATA <= x"11b0";
when "11" & x"3d5" => DATA <= x"0400";
when "11" & x"3d6" => DATA <= x"2800";
when "11" & x"3d7" => DATA <= x"80a0";
when "11" & x"3d8" => DATA <= x"0082";
when "11" & x"3d9" => DATA <= x"0005";
when "11" & x"3da" => DATA <= x"6000";
when "11" & x"3db" => DATA <= x"1061";
when "11" & x"3dc" => DATA <= x"4280";
when "11" & x"3dd" => DATA <= x"021c";
when "11" & x"3de" => DATA <= x"0002";
when "11" & x"3df" => DATA <= x"3070";
when "11" & x"3e0" => DATA <= x"0200";
when "11" & x"3e1" => DATA <= x"3024";
when "11" & x"3e2" => DATA <= x"e000";
when "11" & x"3e3" => DATA <= x"1480";
when "11" & x"3e4" => DATA <= x"182c";
when "11" & x"3e5" => DATA <= x"0004";
when "11" & x"3e6" => DATA <= x"fc02";
when "11" & x"3e7" => DATA <= x"3480";
when "11" & x"3e8" => DATA <= x"042e";
when "11" & x"3e9" => DATA <= x"0046";
when "11" & x"3ea" => DATA <= x"8012";
when "11" & x"3eb" => DATA <= x"c001";
when "11" & x"3ec" => DATA <= x"1500";
when "11" & x"3ed" => DATA <= x"1009";
when "11" & x"3ee" => DATA <= x"8004";
when "11" & x"3ef" => DATA <= x"b000";
when "11" & x"3f0" => DATA <= x"2400";
when "11" & x"3f1" => DATA <= x"1d2e";
when "11" & x"3f2" => DATA <= x"a8e9";
when "11" & x"3f3" => DATA <= x"743a";
when "11" & x"3f4" => DATA <= x"1d8e";
when "11" & x"3f5" => DATA <= x"801e";
when "11" & x"3f6" => DATA <= x"abfa";
when "11" & x"3f7" => DATA <= x"ad59";
when "11" & x"3f8" => DATA <= x"ab9a";
when "11" & x"3f9" => DATA <= x"9552";
when "11" & x"3fa" => DATA <= x"b516";
when "11" & x"3fb" => DATA <= x"8175";
when "11" & x"3fc" => DATA <= x"3ad5";
when "11" & x"3fd" => DATA <= x"4ea3";
when "11" & x"3fe" => DATA <= x"f9bd";
when "11" & x"3ff" => DATA <= x"fe5f";
when "11" & x"400" => DATA <= x"3fbd";
when "11" & x"401" => DATA <= x"e9fc";
when "11" & x"402" => DATA <= x"2000";
when "11" & x"403" => DATA <= x"7c80";
when "11" & x"404" => DATA <= x"0100";
when "11" & x"405" => DATA <= x"27e3";
when "11" & x"406" => DATA <= x"e280";
when "11" & x"407" => DATA <= x"007c";
when "11" & x"408" => DATA <= x"00ff";
when "11" & x"409" => DATA <= x"07a0";
when "11" & x"40a" => DATA <= x"0015";
when "11" & x"40b" => DATA <= x"00c0";
when "11" & x"40c" => DATA <= x"703f";
when "11" & x"40d" => DATA <= x"c1ff";
when "11" & x"40e" => DATA <= x"fe00";
when "11" & x"40f" => DATA <= x"fff7";
when "11" & x"410" => DATA <= x"b500";
when "11" & x"411" => DATA <= x"9c74";
when "11" & x"412" => DATA <= x"07c0";
when "11" & x"413" => DATA <= x"0015";
when "11" & x"414" => DATA <= x"fe07";
when "11" & x"415" => DATA <= x"0030";
when "11" & x"416" => DATA <= x"1f95";
when "11" & x"417" => DATA <= x"fe3f";
when "11" & x"418" => DATA <= x"0020";
when "11" & x"419" => DATA <= x"1795";
when "11" & x"41a" => DATA <= x"7e3f";
when "11" & x"41b" => DATA <= x"5fd0";
when "11" & x"41c" => DATA <= x"03ff";
when "11" & x"41d" => DATA <= x"c00f";
when "11" & x"41e" => DATA <= x"fa00";
when "11" & x"41f" => DATA <= x"e7ee";
when "11" & x"420" => DATA <= x"0005";
when "11" & x"421" => DATA <= x"7130";
when "11" & x"422" => DATA <= x"13e1";
when "11" & x"423" => DATA <= x"f0f7";
when "11" & x"424" => DATA <= x"0fa7";
when "11" & x"425" => DATA <= x"c3e4";
when "11" & x"426" => DATA <= x"5a44";
when "11" & x"427" => DATA <= x"2011";
when "11" & x"428" => DATA <= x"6934";
when "11" & x"429" => DATA <= x"0b5f";
when "11" & x"42a" => DATA <= x"f2fe";
when "11" & x"42b" => DATA <= x"7e3f";
when "11" & x"42c" => DATA <= x"f009";
when "11" & x"42d" => DATA <= x"cd26";
when "11" & x"42e" => DATA <= x"c329";
when "11" & x"42f" => DATA <= x"9ec4";
when "11" & x"430" => DATA <= x"1480";
when "11" & x"431" => DATA <= x"912c";
when "11" & x"432" => DATA <= x"1918";
when "11" & x"433" => DATA <= x"0000";
when "11" & x"434" => DATA <= x"1500";
when "11" & x"435" => DATA <= x"3dc8";
when "11" & x"436" => DATA <= x"4020";
when "11" & x"437" => DATA <= x"2023";
when "11" & x"438" => DATA <= x"801f";
when "11" & x"439" => DATA <= x"ede1";
when "11" & x"43a" => DATA <= x"0000";
when "11" & x"43b" => DATA <= x"1140";
when "11" & x"43c" => DATA <= x"0087";
when "11" & x"43d" => DATA <= x"f800";
when "11" & x"43e" => DATA <= x"0209";
when "11" & x"43f" => DATA <= x"1087";
when "11" & x"440" => DATA <= x"0e08";
when "11" & x"441" => DATA <= x"a25a";
when "11" & x"442" => DATA <= x"91c8";
when "11" & x"443" => DATA <= x"05e0";
when "11" & x"444" => DATA <= x"009a";
when "11" & x"445" => DATA <= x"71c6";
when "11" & x"446" => DATA <= x"011f";
when "11" & x"447" => DATA <= x"3803";
when "11" & x"448" => DATA <= x"080a";
when "11" & x"449" => DATA <= x"00af";
when "11" & x"44a" => DATA <= x"f3f8";
when "11" & x"44b" => DATA <= x"6000";
when "11" & x"44c" => DATA <= x"f7a0";
when "11" & x"44d" => DATA <= x"0aff";
when "11" & x"44e" => DATA <= x"e007";
when "11" & x"44f" => DATA <= x"bd00";
when "11" & x"450" => DATA <= x"57ff";
when "11" & x"451" => DATA <= x"003f";
when "11" & x"452" => DATA <= x"e800";
when "11" & x"453" => DATA <= x"3eff";
when "11" & x"454" => DATA <= x"6614";
when "11" & x"455" => DATA <= x"1000";
when "11" & x"456" => DATA <= x"e36b";
when "11" & x"457" => DATA <= x"8100";
when "11" & x"458" => DATA <= x"0000";
when "11" & x"459" => DATA <= x"8ec3";
when "11" & x"45a" => DATA <= x"e782";
when "11" & x"45b" => DATA <= x"c02c";
when "11" & x"45c" => DATA <= x"6214";
when "11" & x"45d" => DATA <= x"6000";
when "11" & x"45e" => DATA <= x"0049";
when "11" & x"45f" => DATA <= x"2090";
when "11" & x"460" => DATA <= x"1cc4";
when "11" & x"461" => DATA <= x"667f";
when "11" & x"462" => DATA <= x"bf81";
when "11" & x"463" => DATA <= x"04d0";
when "11" & x"464" => DATA <= x"0831";
when "11" & x"465" => DATA <= x"1880";
when "11" & x"466" => DATA <= x"0302";
when "11" & x"467" => DATA <= x"1015";
when "11" & x"468" => DATA <= x"8087";
when "11" & x"469" => DATA <= x"4b8b";
when "11" & x"46a" => DATA <= x"df80";
when "11" & x"46b" => DATA <= x"00f0";
when "11" & x"46c" => DATA <= x"01e0";
when "11" & x"46d" => DATA <= x"000f";
when "11" & x"46e" => DATA <= x"801f";
when "11" & x"46f" => DATA <= x"e000";
when "11" & x"470" => DATA <= x"6230";
when "11" & x"471" => DATA <= x"1f5f";
when "11" & x"472" => DATA <= x"85c1";
when "11" & x"473" => DATA <= x"fd00";
when "11" & x"474" => DATA <= x"5603";
when "11" & x"475" => DATA <= x"1c02";
when "11" & x"476" => DATA <= x"8007";
when "11" & x"477" => DATA <= x"7002";
when "11" & x"478" => DATA <= x"812c";
when "11" & x"479" => DATA <= x"0103";
when "11" & x"47a" => DATA <= x"1010";
when "11" & x"47b" => DATA <= x"000a";
when "11" & x"47c" => DATA <= x"405b";
when "11" & x"47d" => DATA <= x"a103";
when "11" & x"47e" => DATA <= x"0010";
when "11" & x"47f" => DATA <= x"9000";
when "11" & x"480" => DATA <= x"1800";
when "11" & x"481" => DATA <= x"7f85";
when "11" & x"482" => DATA <= x"8a1c";
when "11" & x"483" => DATA <= x"0040";
when "11" & x"484" => DATA <= x"001f";
when "11" & x"485" => DATA <= x"d834";
when "11" & x"486" => DATA <= x"0009";
when "11" & x"487" => DATA <= x"e003";
when "11" & x"488" => DATA <= x"e001";
when "11" & x"489" => DATA <= x"0481";
when "11" & x"48a" => DATA <= x"4150";
when "11" & x"48b" => DATA <= x"01f9";
when "11" & x"48c" => DATA <= x"8000";
when "11" & x"48d" => DATA <= x"6010";
when "11" & x"48e" => DATA <= x"041c";
when "11" & x"48f" => DATA <= x"0080";
when "11" & x"490" => DATA <= x"a40a";
when "11" & x"491" => DATA <= x"c0a0";
when "11" & x"492" => DATA <= x"8025";
when "11" & x"493" => DATA <= x"00f8";
when "11" & x"494" => DATA <= x"0680";
when "11" & x"495" => DATA <= x"0a29";
when "11" & x"496" => DATA <= x"0011";
when "11" & x"497" => DATA <= x"4008";
when "11" & x"498" => DATA <= x"0001";
when "11" & x"499" => DATA <= x"0000";
when "11" & x"49a" => DATA <= x"2504";
when "11" & x"49b" => DATA <= x"5091";
when "11" & x"49c" => DATA <= x"8800";
when "11" & x"49d" => DATA <= x"0d4c";
when "11" & x"49e" => DATA <= x"0000";
when "11" & x"49f" => DATA <= x"5400";
when "11" & x"4a0" => DATA <= x"1800";
when "11" & x"4a1" => DATA <= x"1028";
when "11" & x"4a2" => DATA <= x"0011";
when "11" & x"4a3" => DATA <= x"4001";
when "11" & x"4a4" => DATA <= x"8001";
when "11" & x"4a5" => DATA <= x"4802";
when "11" & x"4a6" => DATA <= x"0030";
when "11" & x"4a7" => DATA <= x"0000";
when "11" & x"4a8" => DATA <= x"4080";
when "11" & x"4a9" => DATA <= x"0014";
when "11" & x"4aa" => DATA <= x"10d0";
when "11" & x"4ab" => DATA <= x"6701";
when "11" & x"4ac" => DATA <= x"2800";
when "11" & x"4ad" => DATA <= x"0408";
when "11" & x"4ae" => DATA <= x"5829";
when "11" & x"4af" => DATA <= x"122a";
when "11" & x"4b0" => DATA <= x"8640";
when "11" & x"4b1" => DATA <= x"02bc";
when "11" & x"4b2" => DATA <= x"3bfd";
when "11" & x"4b3" => DATA <= x"c0c0";
when "11" & x"4b4" => DATA <= x"0170";
when "11" & x"4b5" => DATA <= x"f83c";
when "11" & x"4b6" => DATA <= x"3e0f";
when "11" & x"4b7" => DATA <= x"7f80";
when "11" & x"4b8" => DATA <= x"121a";
when "11" & x"4b9" => DATA <= x"003f";
when "11" & x"4ba" => DATA <= x"1c02";
when "11" & x"4bb" => DATA <= x"bc00";
when "11" & x"4bc" => DATA <= x"0200";
when "11" & x"4bd" => DATA <= x"00e8";
when "11" & x"4be" => DATA <= x"00c0";
when "11" & x"4bf" => DATA <= x"0020";
when "11" & x"4c0" => DATA <= x"f00b";
when "11" & x"4c1" => DATA <= x"0003";
when "11" & x"4c2" => DATA <= x"0000";
when "11" & x"4c3" => DATA <= x"8f04";
when "11" & x"4c4" => DATA <= x"8143";
when "11" & x"4c5" => DATA <= x"4028";
when "11" & x"4c6" => DATA <= x"0c00";
when "11" & x"4c7" => DATA <= x"027f";
when "11" & x"4c8" => DATA <= x"1c69";
when "11" & x"4c9" => DATA <= x"c000";
when "11" & x"4ca" => DATA <= x"e0a0";
when "11" & x"4cb" => DATA <= x"07fd";
when "11" & x"4cc" => DATA <= x"0010";
when "11" & x"4cd" => DATA <= x"1c0b";
when "11" & x"4ce" => DATA <= x"7700";
when "11" & x"4cf" => DATA <= x"01fe";
when "11" & x"4d0" => DATA <= x"086c";
when "11" & x"4d1" => DATA <= x"aa5f";
when "11" & x"4d2" => DATA <= x"c061";
when "11" & x"4d3" => DATA <= x"f861";
when "11" & x"4d4" => DATA <= x"fe1c";
when "11" & x"4d5" => DATA <= x"e1f3";
when "11" & x"4d6" => DATA <= x"e074";
when "11" & x"4d7" => DATA <= x"3c1f";
when "11" & x"4d8" => DATA <= x"a000";
when "11" & x"4d9" => DATA <= x"1000";
when "11" & x"4da" => DATA <= x"91a0";
when "11" & x"4db" => DATA <= x"0420";
when "11" & x"4dc" => DATA <= x"0203";
when "11" & x"4dd" => DATA <= x"c02c";
when "11" & x"4de" => DATA <= x"0012";
when "11" & x"4df" => DATA <= x"0023";
when "11" & x"4e0" => DATA <= x"0424";
when "11" & x"4e1" => DATA <= x"0006";
when "11" & x"4e2" => DATA <= x"0840";
when "11" & x"4e3" => DATA <= x"d000";
when "11" & x"4e4" => DATA <= x"9070";
when "11" & x"4e5" => DATA <= x"0003";
when "11" & x"4e6" => DATA <= x"040a";
when "11" & x"4e7" => DATA <= x"0000";
when "11" & x"4e8" => DATA <= x"880c";
when "11" & x"4e9" => DATA <= x"10c0";
when "11" & x"4ea" => DATA <= x"a004";
when "11" & x"4eb" => DATA <= x"8001";
when "11" & x"4ec" => DATA <= x"8140";
when "11" & x"4ed" => DATA <= x"0294";
when "11" & x"4ee" => DATA <= x"0000";
when "11" & x"4ef" => DATA <= x"4003";
when "11" & x"4f0" => DATA <= x"0e3b";
when "11" & x"4f1" => DATA <= x"0001";
when "11" & x"4f2" => DATA <= x"1d00";
when "11" & x"4f3" => DATA <= x"0380";
when "11" & x"4f4" => DATA <= x"1412";
when "11" & x"4f5" => DATA <= x"0004";
when "11" & x"4f6" => DATA <= x"9006";
when "11" & x"4f7" => DATA <= x"0391";
when "11" & x"4f8" => DATA <= x"48e2";
when "11" & x"4f9" => DATA <= x"602e";
when "11" & x"4fa" => DATA <= x"aaed";
when "11" & x"4fb" => DATA <= x"7b5d";
when "11" & x"4fc" => DATA <= x"d4dd";
when "11" & x"4fd" => DATA <= x"2aa5";
when "11" & x"4fe" => DATA <= x"77ed";
when "11" & x"4ff" => DATA <= x"2ab5";
when "11" & x"500" => DATA <= x"52ad";
when "11" & x"501" => DATA <= x"54ad";
when "11" & x"502" => DATA <= x"6aaf";
when "11" & x"503" => DATA <= x"deaa";
when "11" & x"504" => DATA <= x"957c";
when "11" & x"505" => DATA <= x"d5aa";
when "11" & x"506" => DATA <= x"5755";
when "11" & x"507" => DATA <= x"5482";
when "11" & x"508" => DATA <= x"40d5";
when "11" & x"509" => DATA <= x"5229";
when "11" & x"50a" => DATA <= x"1677";
when "11" & x"50b" => DATA <= x"f7f0";
when "11" & x"50c" => DATA <= x"0205";
when "11" & x"50d" => DATA <= x"8b40";
when "11" & x"50e" => DATA <= x"002e";
when "11" & x"50f" => DATA <= x"0040";
when "11" & x"510" => DATA <= x"3fdf";
when "11" & x"511" => DATA <= x"804a";
when "11" & x"512" => DATA <= x"0002";
when "11" & x"513" => DATA <= x"0001";
when "11" & x"514" => DATA <= x"e8f4";
when "11" & x"515" => DATA <= x"1d40";
when "11" & x"516" => DATA <= x"0010";
when "11" & x"517" => DATA <= x"0e00";
when "11" & x"518" => DATA <= x"07ff";
when "11" & x"519" => DATA <= x"b82f";
when "11" & x"51a" => DATA <= x"ffc0";
when "11" & x"51b" => DATA <= x"403e";
when "11" & x"51c" => DATA <= x"0000";
when "11" & x"51d" => DATA <= x"dff0";
when "11" & x"51e" => DATA <= x"3800";
when "11" & x"51f" => DATA <= x"09d7";
when "11" & x"520" => DATA <= x"e3f0";
when "11" & x"521" => DATA <= x"0800";
when "11" & x"522" => DATA <= x"603e";
when "11" & x"523" => DATA <= x"003f";
when "11" & x"524" => DATA <= x"cff4";
when "11" & x"525" => DATA <= x"00fc";
when "11" & x"526" => DATA <= x"e003";
when "11" & x"527" => DATA <= x"fbe0";
when "11" & x"528" => DATA <= x"00fc";
when "11" & x"529" => DATA <= x"7fd0";
when "11" & x"52a" => DATA <= x"0560";
when "11" & x"52b" => DATA <= x"381c";
when "11" & x"52c" => DATA <= x"6e76";
when "11" & x"52d" => DATA <= x"7b98";
when "11" & x"52e" => DATA <= x"001f";
when "11" & x"52f" => DATA <= x"0f05";
when "11" & x"530" => DATA <= x"d3e1";
when "11" & x"531" => DATA <= x"b0fa";
when "11" & x"532" => DATA <= x"7c3c";
when "11" & x"533" => DATA <= x"4423";
when "11" & x"534" => DATA <= x"7229";
when "11" & x"535" => DATA <= x"0088";
when "11" & x"536" => DATA <= x"45f7";
when "11" & x"537" => DATA <= x"f3e9";
when "11" & x"538" => DATA <= x"ce8c";
when "11" & x"539" => DATA <= x"d67c";
when "11" & x"53a" => DATA <= x"a6d3";
when "11" & x"53b" => DATA <= x"001c";
when "11" & x"53c" => DATA <= x"000e";
when "11" & x"53d" => DATA <= x"b09d";
when "11" & x"53e" => DATA <= x"0080";
when "11" & x"53f" => DATA <= x"0640";
when "11" & x"540" => DATA <= x"1000";
when "11" & x"541" => DATA <= x"3e80";
when "11" & x"542" => DATA <= x"1000";
when "11" & x"543" => DATA <= x"02b5";
when "11" & x"544" => DATA <= x"0020";
when "11" & x"545" => DATA <= x"2800";
when "11" & x"546" => DATA <= x"8000";
when "11" & x"547" => DATA <= x"193f";
when "11" & x"548" => DATA <= x"8026";
when "11" & x"549" => DATA <= x"1070";
when "11" & x"54a" => DATA <= x"0041";
when "11" & x"54b" => DATA <= x"4000";
when "11" & x"54c" => DATA <= x"f7e1";
when "11" & x"54d" => DATA <= x"8418";
when "11" & x"54e" => DATA <= x"0018";
when "11" & x"54f" => DATA <= x"5003";
when "11" & x"550" => DATA <= x"f07e";
when "11" & x"551" => DATA <= x"3001";
when "11" & x"552" => DATA <= x"8002";
when "11" & x"553" => DATA <= x"1400";
when "11" & x"554" => DATA <= x"2b00";
when "11" & x"555" => DATA <= x"0f3c";
when "11" & x"556" => DATA <= x"0000";
when "11" & x"557" => DATA <= x"0840";
when "11" & x"558" => DATA <= x"7800";
when "11" & x"559" => DATA <= x"0100";
when "11" & x"55a" => DATA <= x"0840";
when "11" & x"55b" => DATA <= x"0084";
when "11" & x"55c" => DATA <= x"0040";
when "11" & x"55d" => DATA <= x"9822";
when "11" & x"55e" => DATA <= x"a25b";
when "11" & x"55f" => DATA <= x"440a";
when "11" & x"560" => DATA <= x"c064";
when "11" & x"561" => DATA <= x"3380";
when "11" & x"562" => DATA <= x"6470";
when "11" & x"563" => DATA <= x"0018";
when "11" & x"564" => DATA <= x"661f";
when "11" & x"565" => DATA <= x"aff0";
when "11" & x"566" => DATA <= x"00a2";
when "11" & x"567" => DATA <= x"402b";
when "11" & x"568" => DATA <= x"fd00";
when "11" & x"569" => DATA <= x"de7c";
when "11" & x"56a" => DATA <= x"7003";
when "11" & x"56b" => DATA <= x"fc02";
when "11" & x"56c" => DATA <= x"c13f";
when "11" & x"56d" => DATA <= x"f000";
when "11" & x"56e" => DATA <= x"2d32";
when "11" & x"56f" => DATA <= x"010f";
when "11" & x"570" => DATA <= x"8528";
when "11" & x"571" => DATA <= x"003c";
when "11" & x"572" => DATA <= x"0000";
when "11" & x"573" => DATA <= x"851f";
when "11" & x"574" => DATA <= x"c90a";
when "11" & x"575" => DATA <= x"007e";
when "11" & x"576" => DATA <= x"802a";
when "11" & x"577" => DATA <= x"01a2";
when "11" & x"578" => DATA <= x"ff40";
when "11" & x"579" => DATA <= x"0001";
when "11" & x"57a" => DATA <= x"e706";
when "11" & x"57b" => DATA <= x"0d00";
when "11" & x"57c" => DATA <= x"07c0";
when "11" & x"57d" => DATA <= x"e04a";
when "11" & x"57e" => DATA <= x"0001";
when "11" & x"57f" => DATA <= x"8008";
when "11" & x"580" => DATA <= x"880e";
when "11" & x"581" => DATA <= x"0008";
when "11" & x"582" => DATA <= x"0010";
when "11" & x"583" => DATA <= x"ef80";
when "11" & x"584" => DATA <= x"0015";
when "11" & x"585" => DATA <= x"83c0";
when "11" & x"586" => DATA <= x"0072";
when "11" & x"587" => DATA <= x"980c";
when "11" & x"588" => DATA <= x"10c0";
when "11" & x"589" => DATA <= x"e003";
when "11" & x"58a" => DATA <= x"8008";
when "11" & x"58b" => DATA <= x"0080";
when "11" & x"58c" => DATA <= x"7fd0";
when "11" & x"58d" => DATA <= x"013d";
when "11" & x"58e" => DATA <= x"9e8f";
when "11" & x"58f" => DATA <= x"0030";
when "11" & x"590" => DATA <= x"5ff4";
when "11" & x"591" => DATA <= x"0141";
when "11" & x"592" => DATA <= x"23b0";
when "11" & x"593" => DATA <= x"0381";
when "11" & x"594" => DATA <= x"fec0";
when "11" & x"595" => DATA <= x"2002";
when "11" & x"596" => DATA <= x"000c";
when "11" & x"597" => DATA <= x"8207";
when "11" & x"598" => DATA <= x"0000";
when "11" & x"599" => DATA <= x"c300";
when "11" & x"59a" => DATA <= x"02ef";
when "11" & x"59b" => DATA <= x"8000";
when "11" & x"59c" => DATA <= x"6402";
when "11" & x"59d" => DATA <= x"9802";
when "11" & x"59e" => DATA <= x"0006";
when "11" & x"59f" => DATA <= x"04c0";
when "11" & x"5a0" => DATA <= x"7000";
when "11" & x"5a1" => DATA <= x"1fc0";
when "11" & x"5a2" => DATA <= x"3400";
when "11" & x"5a3" => DATA <= x"0460";
when "11" & x"5a4" => DATA <= x"a000";
when "11" & x"5a5" => DATA <= x"8700";
when "11" & x"5a6" => DATA <= x"0874";
when "11" & x"5a7" => DATA <= x"0005";
when "11" & x"5a8" => DATA <= x"4004";
when "11" & x"5a9" => DATA <= x"f405";
when "11" & x"5aa" => DATA <= x"8010";
when "11" & x"5ab" => DATA <= x"3400";
when "11" & x"5ac" => DATA <= x"05e0";
when "11" & x"5ad" => DATA <= x"1200";
when "11" & x"5ae" => DATA <= x"04a3";
when "11" & x"5af" => DATA <= x"87c1";
when "11" & x"5b0" => DATA <= x"82c0";
when "11" & x"5b1" => DATA <= x"1fe5";
when "11" & x"5b2" => DATA <= x"8d00";
when "11" & x"5b3" => DATA <= x"083f";
when "11" & x"5b4" => DATA <= x"dbfa";
when "11" & x"5b5" => DATA <= x"0010";
when "11" & x"5b6" => DATA <= x"7faf";
when "11" & x"5b7" => DATA <= x"ec01";
when "11" & x"5b8" => DATA <= x"fe10";
when "11" & x"5b9" => DATA <= x"e080";
when "11" & x"5ba" => DATA <= x"0570";
when "11" & x"5bb" => DATA <= x"3ff4";
when "11" & x"5bc" => DATA <= x"00be";
when "11" & x"5bd" => DATA <= x"ac38";
when "11" & x"5be" => DATA <= x"6803";
when "11" & x"5bf" => DATA <= x"e063";
when "11" & x"5c0" => DATA <= x"600e";
when "11" & x"5c1" => DATA <= x"f575";
when "11" & x"5c2" => DATA <= x"8000";
when "11" & x"5c3" => DATA <= x"db76";
when "11" & x"5c4" => DATA <= x"00cf";
when "11" & x"5c5" => DATA <= x"0700";
when "11" & x"5c6" => DATA <= x"1012";
when "11" & x"5c7" => DATA <= x"0017";
when "11" & x"5c8" => DATA <= x"0f00";
when "11" & x"5c9" => DATA <= x"0040";
when "11" & x"5ca" => DATA <= x"0025";
when "11" & x"5cb" => DATA <= x"0001";
when "11" & x"5cc" => DATA <= x"9880";
when "11" & x"5cd" => DATA <= x"0008";
when "11" & x"5ce" => DATA <= x"0007";
when "11" & x"5cf" => DATA <= x"4004";
when "11" & x"5d0" => DATA <= x"43e2";
when "11" & x"5d1" => DATA <= x"5280";
when "11" & x"5d2" => DATA <= x"020a";
when "11" & x"5d3" => DATA <= x"9003";
when "11" & x"5d4" => DATA <= x"05f6";
when "11" & x"5d5" => DATA <= x"f2e0";
when "11" & x"5d6" => DATA <= x"0008";
when "11" & x"5d7" => DATA <= x"01c8";
when "11" & x"5d8" => DATA <= x"ff53";
when "11" & x"5d9" => DATA <= x"f003";
when "11" & x"5da" => DATA <= x"0030";
when "11" & x"5db" => DATA <= x"017f";
when "11" & x"5dc" => DATA <= x"9958";
when "11" & x"5dd" => DATA <= x"0100";
when "11" & x"5de" => DATA <= x"f80e";
when "11" & x"5df" => DATA <= x"801f";
when "11" & x"5e0" => DATA <= x"e1f9";
when "11" & x"5e1" => DATA <= x"0000";
when "11" & x"5e2" => DATA <= x"b428";
when "11" & x"5e3" => DATA <= x"01b9";
when "11" & x"5e4" => DATA <= x"2000";
when "11" & x"5e5" => DATA <= x"fa00";
when "11" & x"5e6" => DATA <= x"6348";
when "11" & x"5e7" => DATA <= x"0202";
when "11" & x"5e8" => DATA <= x"8000";
when "11" & x"5e9" => DATA <= x"8800";
when "11" & x"5ea" => DATA <= x"002c";
when "11" & x"5eb" => DATA <= x"01dc";
when "11" & x"5ec" => DATA <= x"0804";
when "11" & x"5ed" => DATA <= x"8341";
when "11" & x"5ee" => DATA <= x"00d0";
when "11" & x"5ef" => DATA <= x"aee2";
when "11" & x"5f0" => DATA <= x"71ba";
when "11" & x"5f1" => DATA <= x"938d";
when "11" & x"5f2" => DATA <= x"e6e2";
when "11" & x"5f3" => DATA <= x"bfaa";
when "11" & x"5f4" => DATA <= x"dfab";
when "11" & x"5f5" => DATA <= x"94ca";
when "11" & x"5f6" => DATA <= x"caba";
when "11" & x"5f7" => DATA <= x"a75a";
when "11" & x"5f8" => DATA <= x"a914";
when "11" & x"5f9" => DATA <= x"8041";
when "11" & x"5fa" => DATA <= x"2a95";
when "11" & x"5fb" => DATA <= x"6aa5";
when "11" & x"5fc" => DATA <= x"5fbf";
when "11" & x"5fd" => DATA <= x"9ff8";
when "11" & x"5fe" => DATA <= x"018a";
when "11" & x"5ff" => DATA <= x"c10c";
when "11" & x"600" => DATA <= x"57c0";
when "11" & x"601" => DATA <= x"11b0";
when "11" & x"602" => DATA <= x"fc7f";
when "11" & x"603" => DATA <= x"80c0";
when "11" & x"604" => DATA <= x"0c77";
when "11" & x"605" => DATA <= x"fa01";
when "11" & x"606" => DATA <= x"0881";
when "11" & x"607" => DATA <= x"4781";
when "11" & x"608" => DATA <= x"c003";
when "11" & x"609" => DATA <= x"fdff";
when "11" & x"60a" => DATA <= x"7dd0";
when "11" & x"60b" => DATA <= x"033f";
when "11" & x"60c" => DATA <= x"7fda";
when "11" & x"60d" => DATA <= x"0fb7";
when "11" & x"60e" => DATA <= x"9f80";
when "11" & x"60f" => DATA <= x"807c";
when "11" & x"610" => DATA <= x"0000";
when "11" & x"611" => DATA <= x"e076";
when "11" & x"612" => DATA <= x"77fb";
when "11" & x"613" => DATA <= x"bebf";
when "11" & x"614" => DATA <= x"ecf9";
when "11" & x"615" => DATA <= x"7e0f";
when "11" & x"616" => DATA <= x"0008";
when "11" & x"617" => DATA <= x"a802";
when "11" & x"618" => DATA <= x"bf10";
when "11" & x"619" => DATA <= x"3400";
when "11" & x"61a" => DATA <= x"04a0";
when "11" & x"61b" => DATA <= x"0aff";
when "11" & x"61c" => DATA <= x"401e";
when "11" & x"61d" => DATA <= x"1c0e";
when "11" & x"61e" => DATA <= x"1603";
when "11" & x"61f" => DATA <= x"b99e";
when "11" & x"620" => DATA <= x"c773";
when "11" & x"621" => DATA <= x"b838";
when "11" & x"622" => DATA <= x"7d3e";
when "11" & x"623" => DATA <= x"1f0d";
when "11" & x"624" => DATA <= x"a7c3";
when "11" & x"625" => DATA <= x"e052";
when "11" & x"626" => DATA <= x"2904";
when "11" & x"627" => DATA <= x"8000";
when "11" & x"628" => DATA <= x"2211";
when "11" & x"629" => DATA <= x"4892";
when "11" & x"62a" => DATA <= x"fb3f";
when "11" & x"62b" => DATA <= x"bda6";
when "11" & x"62c" => DATA <= x"e573";
when "11" & x"62d" => DATA <= x"3d8c";
when "11" & x"62e" => DATA <= x"c7ea";
when "11" & x"62f" => DATA <= x"0020";
when "11" & x"630" => DATA <= x"adc9";
when "11" & x"631" => DATA <= x"8ff0";
when "11" & x"632" => DATA <= x"02ce";
when "11" & x"633" => DATA <= x"8000";
when "11" & x"634" => DATA <= x"4af1";
when "11" & x"635" => DATA <= x"33fc";
when "11" & x"636" => DATA <= x"00d9";
when "11" & x"637" => DATA <= x"a004";
when "11" & x"638" => DATA <= x"0b7d";
when "11" & x"639" => DATA <= x"66ff";
when "11" & x"63a" => DATA <= x"0033";
when "11" & x"63b" => DATA <= x"3800";
when "11" & x"63c" => DATA <= x"de99";
when "11" & x"63d" => DATA <= x"7f80";
when "11" & x"63e" => DATA <= x"04dc";
when "11" & x"63f" => DATA <= x"00b3";
when "11" & x"640" => DATA <= x"263f";
when "11" & x"641" => DATA <= x"c00b";
when "11" & x"642" => DATA <= x"3e00";
when "11" & x"643" => DATA <= x"6a99";
when "11" & x"644" => DATA <= x"9fe0";
when "11" & x"645" => DATA <= x"04cf";
when "11" & x"646" => DATA <= x"001e";
when "11" & x"647" => DATA <= x"866f";
when "11" & x"648" => DATA <= x"f003";
when "11" & x"649" => DATA <= x"3400";
when "11" & x"64a" => DATA <= x"6000";
when "11" & x"64b" => DATA <= x"1b53";
when "11" & x"64c" => DATA <= x"2ff0";
when "11" & x"64d" => DATA <= x"0198";
when "11" & x"64e" => DATA <= x"0004";
when "11" & x"64f" => DATA <= x"1037";
when "11" & x"650" => DATA <= x"8d8f";
when "11" & x"651" => DATA <= x"f001";
when "11" & x"652" => DATA <= x"be80";
when "11" & x"653" => DATA <= x"0807";
when "11" & x"654" => DATA <= x"f613";
when "11" & x"655" => DATA <= x"fc00";
when "11" & x"656" => DATA <= x"fe00";
when "11" & x"657" => DATA <= x"3418";
when "11" & x"658" => DATA <= x"0ef0";
when "11" & x"659" => DATA <= x"b3fc";
when "11" & x"65a" => DATA <= x"00b6";
when "11" & x"65b" => DATA <= x"2850";
when "11" & x"65c" => DATA <= x"03fd";
when "11" & x"65d" => DATA <= x"f0ff";
when "11" & x"65e" => DATA <= x"0024";
when "11" & x"65f" => DATA <= x"4000";
when "11" & x"660" => DATA <= x"8243";
when "11" & x"661" => DATA <= x"fdde";
when "11" & x"662" => DATA <= x"1d7c";
when "11" & x"663" => DATA <= x"00c0";
when "11" & x"664" => DATA <= x"0040";
when "11" & x"665" => DATA <= x"3365";
when "11" & x"666" => DATA <= x"fefe";
when "11" & x"667" => DATA <= x"6f85";
when "11" & x"668" => DATA <= x"4042";
when "11" & x"669" => DATA <= x"0002";
when "11" & x"66a" => DATA <= x"ffbf";
when "11" & x"66b" => DATA <= x"f801";
when "11" & x"66c" => DATA <= x"00f7";
when "11" & x"66d" => DATA <= x"5fbf";
when "11" & x"66e" => DATA <= x"d7f2";
when "11" & x"66f" => DATA <= x"00fe";
when "11" & x"670" => DATA <= x"7d8f";
when "11" & x"671" => DATA <= x"dbe0";
when "11" & x"672" => DATA <= x"07e0";
when "11" & x"673" => DATA <= x"0c04";
when "11" & x"674" => DATA <= x"ff7d";
when "11" & x"675" => DATA <= x"bf03";
when "11" & x"676" => DATA <= x"8001";
when "11" & x"677" => DATA <= x"7811";
when "11" & x"678" => DATA <= x"00d7";
when "11" & x"679" => DATA <= x"7bb3";
when "11" & x"67a" => DATA <= x"e800";
when "11" & x"67b" => DATA <= x"04cc";
when "11" & x"67c" => DATA <= x"003f";
when "11" & x"67d" => DATA <= x"dfcf";
when "11" & x"67e" => DATA <= x"b3e5";
when "11" & x"67f" => DATA <= x"0004";
when "11" & x"680" => DATA <= x"060f";
when "11" & x"681" => DATA <= x"daff";
when "11" & x"682" => DATA <= x"77d0";
when "11" & x"683" => DATA <= x"0081";
when "11" & x"684" => DATA <= x"467f";
when "11" & x"685" => DATA <= x"7f83";
when "11" & x"686" => DATA <= x"dff4";
when "11" & x"687" => DATA <= x"00aa";
when "11" & x"688" => DATA <= x"59d7";
when "11" & x"689" => DATA <= x"f805";
when "11" & x"68a" => DATA <= x"de00";
when "11" & x"68b" => DATA <= x"782e";
when "11" & x"68c" => DATA <= x"1166";
when "11" & x"68d" => DATA <= x"b7f0";
when "11" & x"68e" => DATA <= x"01ee";
when "11" & x"68f" => DATA <= x"007f";
when "11" & x"690" => DATA <= x"b058";
when "11" & x"691" => DATA <= x"0fe7";
when "11" & x"692" => DATA <= x"f801";
when "11" & x"693" => DATA <= x"ea00";
when "11" & x"694" => DATA <= x"7fb7";
when "11" & x"695" => DATA <= x"0a0f";
when "11" & x"696" => DATA <= x"f6f8";
when "11" & x"697" => DATA <= x"01fe";
when "11" & x"698" => DATA <= x"007f";
when "11" & x"699" => DATA <= x"d003";
when "11" & x"69a" => DATA <= x"fdfc";
when "11" & x"69b" => DATA <= x"007f";
when "11" & x"69c" => DATA <= x"8018";
when "11" & x"69d" => DATA <= x"0011";
when "11" & x"69e" => DATA <= x"057f";
when "11" & x"69f" => DATA <= x"8017";
when "11" & x"6a0" => DATA <= x"f400";
when "11" & x"6a1" => DATA <= x"0200";
when "11" & x"6a2" => DATA <= x"d7f8";
when "11" & x"6a3" => DATA <= x"01fc";
when "11" & x"6a4" => DATA <= x"40e0";
when "11" & x"6a5" => DATA <= x"0aff";
when "11" & x"6a6" => DATA <= x"003f";
when "11" & x"6a7" => DATA <= x"f800";
when "11" & x"6a8" => DATA <= x"415f";
when "11" & x"6a9" => DATA <= x"e007";
when "11" & x"6aa" => DATA <= x"ff00";
when "11" & x"6ab" => DATA <= x"006b";
when "11" & x"6ac" => DATA <= x"fc00";
when "11" & x"6ad" => DATA <= x"ffe0";
when "11" & x"6ae" => DATA <= x"0013";
when "11" & x"6af" => DATA <= x"fd06";
when "11" & x"6b0" => DATA <= x"005f";
when "11" & x"6b1" => DATA <= x"d010";
when "11" & x"6b2" => DATA <= x"00e0";
when "11" & x"6b3" => DATA <= x"ff04";
when "11" & x"6b4" => DATA <= x"a013";
when "11" & x"6b5" => DATA <= x"e000";
when "11" & x"6b6" => DATA <= x"6044";
when "11" & x"6b7" => DATA <= x"8cff";
when "11" & x"6b8" => DATA <= x"1980";
when "11" & x"6b9" => DATA <= x"1f7c";
when "11" & x"6ba" => DATA <= x"0050";
when "11" & x"6bb" => DATA <= x"7f80";
when "11" & x"6bc" => DATA <= x"080c";
when "11" & x"6bd" => DATA <= x"fe00";
when "11" & x"6be" => DATA <= x"0237";
when "11" & x"6bf" => DATA <= x"c60f";
when "11" & x"6c0" => DATA <= x"800b";
when "11" & x"6c1" => DATA <= x"2380";
when "11" & x"6c2" => DATA <= x"1d89";
when "11" & x"6c3" => DATA <= x"97f8";
when "11" & x"6c4" => DATA <= x"00c9";
when "11" & x"6c5" => DATA <= x"4002";
when "11" & x"6c6" => DATA <= x"03b3";
when "11" & x"6c7" => DATA <= x"25fe";
when "11" & x"6c8" => DATA <= x"0019";
when "11" & x"6c9" => DATA <= x"5000";
when "11" & x"6ca" => DATA <= x"8176";
when "11" & x"6cb" => DATA <= x"647f";
when "11" & x"6cc" => DATA <= x"8013";
when "11" & x"6cd" => DATA <= x"6800";
when "11" & x"6ce" => DATA <= x"0161";
when "11" & x"6cf" => DATA <= x"fe56";
when "11" & x"6d0" => DATA <= x"7fbc";
when "11" & x"6d1" => DATA <= x"08b4";
when "11" & x"6d2" => DATA <= x"00ad";
when "11" & x"6d3" => DATA <= x"1ab2";
when "11" & x"6d4" => DATA <= x"5bef";
when "11" & x"6d5" => DATA <= x"f23d";
when "11" & x"6d6" => DATA <= x"0001";
when "11" & x"6d7" => DATA <= x"9fe8";
when "11" & x"6d8" => DATA <= x"47fb";
when "11" & x"6d9" => DATA <= x"3803";
when "11" & x"6da" => DATA <= x"c00f";
when "11" & x"6db" => DATA <= x"f093";
when "11" & x"6dc" => DATA <= x"cd77";
when "11" & x"6dd" => DATA <= x"c000";
when "11" & x"6de" => DATA <= x"44a8";
when "11" & x"6df" => DATA <= x"90fe";
when "11" & x"6e0" => DATA <= x"fb00";
when "11" & x"6e1" => DATA <= x"2400";
when "11" & x"6e2" => DATA <= x"0807";
when "11" & x"6e3" => DATA <= x"e822";
when "11" & x"6e4" => DATA <= x"bfc0";
when "11" & x"6e5" => DATA <= x"0420";
when "11" & x"6e6" => DATA <= x"0045";
when "11" & x"6e7" => DATA <= x"ee00";
when "11" & x"6e8" => DATA <= x"7fbe";
when "11" & x"6e9" => DATA <= x"4000";
when "11" & x"6ea" => DATA <= x"8000";
when "11" & x"6eb" => DATA <= x"99fe";
when "11" & x"6ec" => DATA <= x"067f";
when "11" & x"6ed" => DATA <= x"bbe4";
when "11" & x"6ee" => DATA <= x"01fe";
when "11" & x"6ef" => DATA <= x"247f";
when "11" & x"6f0" => DATA <= x"bf38";
when "11" & x"6f1" => DATA <= x"0100";
when "11" & x"6f2" => DATA <= x"ff50";
when "11" & x"6f3" => DATA <= x"57ff";
when "11" & x"6f4" => DATA <= x"000e";
when "11" & x"6f5" => DATA <= x"1fe0";
when "11" & x"6f6" => DATA <= x"0aff";
when "11" & x"6f7" => DATA <= x"0000";
when "11" & x"6f8" => DATA <= x"8002";
when "11" & x"6f9" => DATA <= x"0338";
when "11" & x"6fa" => DATA <= x"01ec";
when "11" & x"6fb" => DATA <= x"7690";
when "11" & x"6fc" => DATA <= x"07f9";
when "11" & x"6fd" => DATA <= x"41fe";
when "11" & x"6fe" => DATA <= x"7fe0";
when "11" & x"6ff" => DATA <= x"0061";
when "11" & x"700" => DATA <= x"fc08";
when "11" & x"701" => DATA <= x"7f77";
when "11" & x"702" => DATA <= x"c803";
when "11" & x"703" => DATA <= x"dc00";
when "11" & x"704" => DATA <= x"fb5b";
when "11" & x"705" => DATA <= x"c803";
when "11" & x"706" => DATA <= x"6c44";
when "11" & x"707" => DATA <= x"f77f";
when "11" & x"708" => DATA <= x"f003";
when "11" & x"709" => DATA <= x"91fe";
when "11" & x"70a" => DATA <= x"007f";
when "11" & x"70b" => DATA <= x"ae40";
when "11" & x"70c" => DATA <= x"14e0";
when "11" & x"70d" => DATA <= x"7e3e";
when "11" & x"70e" => DATA <= x"802b";
when "11" & x"70f" => DATA <= x"fde0";
when "11" & x"710" => DATA <= x"0f37";
when "11" & x"711" => DATA <= x"93cd";
when "11" & x"712" => DATA <= x"eef0";
when "11" & x"713" => DATA <= x"fbfc";
when "11" & x"714" => DATA <= x"7e55";
when "11" & x"715" => DATA <= x"2a72";
when "11" & x"716" => DATA <= x"a800";
when "11" & x"717" => DATA <= x"ae00";
when "11" & x"718" => DATA <= x"3ab9";
when "11" & x"719" => DATA <= x"4ca7";
when "11" & x"71a" => DATA <= x"57aa";
when "11" & x"71b" => DATA <= x"c15e";
when "11" & x"71c" => DATA <= x"0045";
when "11" & x"71d" => DATA <= x"0294";
when "11" & x"71e" => DATA <= x"0f05";
when "11" & x"71f" => DATA <= x"331c";
when "11" & x"720" => DATA <= x"4f55";
when "11" & x"721" => DATA <= x"eb05";
when "11" & x"722" => DATA <= x"6a2d";
when "11" & x"723" => DATA <= x"56af";
when "11" & x"724" => DATA <= x"7f3a";
when "11" & x"725" => DATA <= x"48f4";
when "11" & x"726" => DATA <= x"feff";
when "11" & x"727" => DATA <= x"a7f6";
when "11" & x"728" => DATA <= x"39fc";
when "11" & x"729" => DATA <= x"0010";
when "11" & x"72a" => DATA <= x"003e";
when "11" & x"72b" => DATA <= x"c000";
when "11" & x"72c" => DATA <= x"8013";
when "11" & x"72d" => DATA <= x"e380";
when "11" & x"72e" => DATA <= x"007c";
when "11" & x"72f" => DATA <= x"00ff";
when "11" & x"730" => DATA <= x"7000";
when "11" & x"731" => DATA <= x"2a02";
when "11" & x"732" => DATA <= x"801c";
when "11" & x"733" => DATA <= x"1fff";
when "11" & x"734" => DATA <= x"5ff5";
when "11" & x"735" => DATA <= x"f77f";
when "11" & x"736" => DATA <= x"fe02";
when "11" & x"737" => DATA <= x"01f0";
when "11" & x"738" => DATA <= x"0001";
when "11" & x"739" => DATA <= x"bc0e";
when "11" & x"73a" => DATA <= x"e103";
when "11" & x"73b" => DATA <= x"b85d";
when "11" & x"73c" => DATA <= x"8ef7";
when "11" & x"73d" => DATA <= x"f801";
when "11" & x"73e" => DATA <= x"00a0";
when "11" & x"73f" => DATA <= x"5e0f";
when "11" & x"740" => DATA <= x"baf9";
when "11" & x"741" => DATA <= x"fd60";
when "11" & x"742" => DATA <= x"15ff";
when "11" & x"743" => DATA <= x"600f";
when "11" & x"744" => DATA <= x"f603";
when "11" & x"745" => DATA <= x"8001";
when "11" & x"746" => DATA <= x"5c4c";
when "11" & x"747" => DATA <= x"2703";
when "11" & x"748" => DATA <= x"003d";
when "11" & x"749" => DATA <= x"c3e9";
when "11" & x"74a" => DATA <= x"fa1f";
when "11" & x"74b" => DATA <= x"0f11";
when "11" & x"74c" => DATA <= x"081c";
when "11" & x"74d" => DATA <= x"8a05";
when "11" & x"74e" => DATA <= x"2215";
when "11" & x"74f" => DATA <= x"abf6";
when "11" & x"750" => DATA <= x"8078";
when "11" & x"751" => DATA <= x"0080";
when "11" & x"752" => DATA <= x"007f";
when "11" & x"753" => DATA <= x"bf8f";
when "11" & x"754" => DATA <= x"d3fc";
when "11" & x"755" => DATA <= x"2d5d";
when "11" & x"756" => DATA <= x"c802";
when "11" & x"757" => DATA <= x"e000";
when "11" & x"758" => DATA <= x"eb6c";
when "11" & x"759" => DATA <= x"c803";
when "11" & x"75a" => DATA <= x"7400";
when "11" & x"75b" => DATA <= x"5876";
when "11" & x"75c" => DATA <= x"4803";
when "11" & x"75d" => DATA <= x"bc00";
when "11" & x"75e" => DATA <= x"a933";
when "11" & x"75f" => DATA <= x"4801";
when "11" & x"760" => DATA <= x"f800";
when "11" & x"761" => DATA <= x"da5b";
when "11" & x"762" => DATA <= x"c802";
when "11" & x"763" => DATA <= x"fc00";
when "11" & x"764" => DATA <= x"bd4c";
when "11" & x"765" => DATA <= x"c803";
when "11" & x"766" => DATA <= x"7c00";
when "11" & x"767" => DATA <= x"7f66";
when "11" & x"768" => DATA <= x"c803";
when "11" & x"769" => DATA <= x"f400";
when "11" & x"76a" => DATA <= x"bd33";
when "11" & x"76b" => DATA <= x"4801";
when "11" & x"76c" => DATA <= x"1800";
when "11" & x"76d" => DATA <= x"563f";
when "11" & x"76e" => DATA <= x"c800";
when "11" & x"76f" => DATA <= x"4400";
when "11" & x"770" => DATA <= x"6776";
when "11" & x"771" => DATA <= x"5800";
when "11" & x"772" => DATA <= x"7477";
when "11" & x"773" => DATA <= x"6008";
when "11" & x"774" => DATA <= x"0678";
when "11" & x"775" => DATA <= x"8280";
when "11" & x"776" => DATA <= x"0400";
when "11" & x"777" => DATA <= x"0080";
when "11" & x"778" => DATA <= x"1059";
when "11" & x"779" => DATA <= x"e00f";
when "11" & x"77a" => DATA <= x"f000";
when "11" & x"77b" => DATA <= x"4240";
when "11" & x"77c" => DATA <= x"092f";
when "11" & x"77d" => DATA <= x"f000";
when "11" & x"77e" => DATA <= x"8240";
when "11" & x"77f" => DATA <= x"0681";
when "11" & x"780" => DATA <= x"c000";
when "11" & x"781" => DATA <= x"5680";
when "11" & x"782" => DATA <= x"0600";
when "11" & x"783" => DATA <= x"0022";
when "11" & x"784" => DATA <= x"0400";
when "11" & x"785" => DATA <= x"20a0";
when "11" & x"786" => DATA <= x"0510";
when "11" & x"787" => DATA <= x"0806";
when "11" & x"788" => DATA <= x"dbb0";
when "11" & x"789" => DATA <= x"0021";
when "11" & x"78a" => DATA <= x"d440";
when "11" & x"78b" => DATA <= x"4001";
when "11" & x"78c" => DATA <= x"0808";
when "11" & x"78d" => DATA <= x"0030";
when "11" & x"78e" => DATA <= x"e3aa";
when "11" & x"78f" => DATA <= x"80a8";
when "11" & x"790" => DATA <= x"0004";
when "11" & x"791" => DATA <= x"0017";
when "11" & x"792" => DATA <= x"16c4";
when "11" & x"793" => DATA <= x"5600";
when "11" & x"794" => DATA <= x"6fb0";
when "11" & x"795" => DATA <= x"0403";
when "11" & x"796" => DATA <= x"7f40";
when "11" & x"797" => DATA <= x"0020";
when "11" & x"798" => DATA <= x"37e2";
when "11" & x"799" => DATA <= x"0240";
when "11" & x"79a" => DATA <= x"0422";
when "11" & x"79b" => DATA <= x"0338";
when "11" & x"79c" => DATA <= x"0d00";
when "11" & x"79d" => DATA <= x"0000";
when "11" & x"79e" => DATA <= x"a000";
when "11" & x"79f" => DATA <= x"0166";
when "11" & x"7a0" => DATA <= x"3f80";
when "11" & x"7a1" => DATA <= x"28e4";
when "11" & x"7a2" => DATA <= x"01e4";
when "11" & x"7a3" => DATA <= x"0040";
when "11" & x"7a4" => DATA <= x"1fa4";
when "11" & x"7a5" => DATA <= x"00fe";
when "11" & x"7a6" => DATA <= x"0036";
when "11" & x"7a7" => DATA <= x"0ce4";
when "11" & x"7a8" => DATA <= x"017e";
when "11" & x"7a9" => DATA <= x"0057";
when "11" & x"7aa" => DATA <= x"b664";
when "11" & x"7ab" => DATA <= x"01fe";
when "11" & x"7ac" => DATA <= x"002d";
when "11" & x"7ad" => DATA <= x"3364";
when "11" & x"7ae" => DATA <= x"01fa";
when "11" & x"7af" => DATA <= x"0052";
when "11" & x"7b0" => DATA <= x"99a4";
when "11" & x"7b1" => DATA <= x"007c";
when "11" & x"7b2" => DATA <= x"0003";
when "11" & x"7b3" => DATA <= x"3efc";
when "11" & x"7b4" => DATA <= x"01f7";
when "11" & x"7b5" => DATA <= x"200a";
when "11" & x"7b6" => DATA <= x"0a00";
when "11" & x"7b7" => DATA <= x"2980";
when "11" & x"7b8" => DATA <= x"0214";
when "11" & x"7b9" => DATA <= x"0010";
when "11" & x"7ba" => DATA <= x"0008";
when "11" & x"7bb" => DATA <= x"0ec0";
when "11" & x"7bc" => DATA <= x"000c";
when "11" & x"7bd" => DATA <= x"8014";
when "11" & x"7be" => DATA <= x"19f2";
when "11" & x"7bf" => DATA <= x"0084";
when "11" & x"7c0" => DATA <= x"0021";
when "11" & x"7c1" => DATA <= x"4c92";
when "11" & x"7c2" => DATA <= x"006e";
when "11" & x"7c3" => DATA <= x"0012";
when "11" & x"7c4" => DATA <= x"86f2";
when "11" & x"7c5" => DATA <= x"00f7";
when "11" & x"7c6" => DATA <= x"0025";
when "11" & x"7c7" => DATA <= x"5372";
when "11" & x"7c8" => DATA <= x"00fb";
when "11" & x"7c9" => DATA <= x"001e";
when "11" & x"7ca" => DATA <= x"8fb4";
when "11" & x"7cb" => DATA <= x"0080";
when "11" & x"7cc" => DATA <= x"0001";
when "11" & x"7cd" => DATA <= x"400f";
when "11" & x"7ce" => DATA <= x"c3ed";
when "11" & x"7cf" => DATA <= x"0600";
when "11" & x"7d0" => DATA <= x"4294";
when "11" & x"7d1" => DATA <= x"0850";
when "11" & x"7d2" => DATA <= x"42d0";
when "11" & x"7d3" => DATA <= x"0013";
when "11" & x"7d4" => DATA <= x"8019";
when "11" & x"7d5" => DATA <= x"0fd0";
when "11" & x"7d6" => DATA <= x"00f0";
when "11" & x"7d7" => DATA <= x"0014";
when "11" & x"7d8" => DATA <= x"120f";
when "11" & x"7d9" => DATA <= x"022f";
when "11" & x"7da" => DATA <= x"bb00";
when "11" & x"7db" => DATA <= x"6837";
when "11" & x"7dc" => DATA <= x"821c";
when "11" & x"7dd" => DATA <= x"0010";
when "11" & x"7de" => DATA <= x"002e";
when "11" & x"7df" => DATA <= x"5bf2";
when "11" & x"7e0" => DATA <= x"0008";
when "11" & x"7e1" => DATA <= x"000c";
when "11" & x"7e2" => DATA <= x"59cc";
when "11" & x"7e3" => DATA <= x"00c0";
when "11" & x"7e4" => DATA <= x"0101";
when "11" & x"7e5" => DATA <= x"4000";
when "11" & x"7e6" => DATA <= x"14b5";
when "11" & x"7e7" => DATA <= x"800c";
when "11" & x"7e8" => DATA <= x"00fc";
when "11" & x"7e9" => DATA <= x"0080";
when "11" & x"7ea" => DATA <= x"a006";
when "11" & x"7eb" => DATA <= x"3b00";
when "11" & x"7ec" => DATA <= x"0340";
when "11" & x"7ed" => DATA <= x"020a";
when "11" & x"7ee" => DATA <= x"0020";
when "11" & x"7ef" => DATA <= x"6800";
when "11" & x"7f0" => DATA <= x"6000";
when "11" & x"7f1" => DATA <= x"46a0";
when "11" & x"7f2" => DATA <= x"010c";
when "11" & x"7f3" => DATA <= x"8011";
when "11" & x"7f4" => DATA <= x"1e60";
when "11" & x"7f5" => DATA <= x"8008";
when "11" & x"7f6" => DATA <= x"0011";
when "11" & x"7f7" => DATA <= x"400c";
when "11" & x"7f8" => DATA <= x"05f8";
when "11" & x"7f9" => DATA <= x"103c";
when "11" & x"7fa" => DATA <= x"0006";
when "11" & x"7fb" => DATA <= x"0780";
when "11" & x"7fc" => DATA <= x"02b1";
when "11" & x"7fd" => DATA <= x"7780";
when "11" & x"7fe" => DATA <= x"0216";
when "11" & x"7ff" => DATA <= x"0080";
when "11" & x"800" => DATA <= x"0282";
when "11" & x"801" => DATA <= x"802b";
when "11" & x"802" => DATA <= x"c1fc";
when "11" & x"803" => DATA <= x"e8af";
when "11" & x"804" => DATA <= x"8773";
when "11" & x"805" => DATA <= x"f17f";
when "11" & x"806" => DATA <= x"e7e0";
when "11" & x"807" => DATA <= x"e3f0";
when "11" & x"808" => DATA <= x"0168";
when "11" & x"809" => DATA <= x"ff00";
when "11" & x"80a" => DATA <= x"57fb";
when "11" & x"80b" => DATA <= x"81e8";
when "11" & x"80c" => DATA <= x"10ae";
when "11" & x"80d" => DATA <= x"b005";
when "11" & x"80e" => DATA <= x"55af";
when "11" & x"80f" => DATA <= x"15ca";
when "11" & x"810" => DATA <= x"8670";
when "11" & x"811" => DATA <= x"b950";
when "11" & x"812" => DATA <= x"b244";
when "11" & x"813" => DATA <= x"3a55";
when "11" & x"814" => DATA <= x"0aa4";
when "11" & x"815" => DATA <= x"1201";
when "11" & x"816" => DATA <= x"c551";
when "11" & x"817" => DATA <= x"54fe";
when "11" & x"818" => DATA <= x"3fd7";
when "11" & x"819" => DATA <= x"fa08";
when "11" & x"81a" => DATA <= x"60b1";
when "11" & x"81b" => DATA <= x"6800";
when "11" & x"81c" => DATA <= x"05c0";
when "11" & x"81d" => DATA <= x"15fe";
when "11" & x"81e" => DATA <= x"fc00";
when "11" & x"81f" => DATA <= x"0100";
when "11" & x"820" => DATA <= x"03e0";
when "11" & x"821" => DATA <= x"001d";
when "11" & x"822" => DATA <= x"1e81";
when "11" & x"823" => DATA <= x"a800";
when "11" & x"824" => DATA <= x"03bd";
when "11" & x"825" => DATA <= x"00c0";
when "11" & x"826" => DATA <= x"65bb";
when "11" & x"827" => DATA <= x"fbfd";
when "11" & x"828" => DATA <= x"f6f3";
when "11" & x"829" => DATA <= x"69d7";
when "11" & x"82a" => DATA <= x"9d7d";
when "11" & x"82b" => DATA <= x"bffc";
when "11" & x"82c" => DATA <= x"0403";
when "11" & x"82d" => DATA <= x"4001";
when "11" & x"82e" => DATA <= x"8d00";
when "11" & x"82f" => DATA <= x"eff1";
when "11" & x"830" => DATA <= x"7a1c";
when "11" & x"831" => DATA <= x"db5c";
when "11" & x"832" => DATA <= x"ebe5";
when "11" & x"833" => DATA <= x"f81f";
when "11" & x"834" => DATA <= x"8007";
when "11" & x"835" => DATA <= x"83e3";
when "11" & x"836" => DATA <= x"f80c";
when "11" & x"837" => DATA <= x"00fc";
when "11" & x"838" => DATA <= x"900a";
when "11" & x"839" => DATA <= x"c07f";
when "11" & x"83a" => DATA <= x"3fe4";
when "11" & x"83b" => DATA <= x"01c0";
when "11" & x"83c" => DATA <= x"e373";
when "11" & x"83d" => DATA <= x"b3dc";
when "11" & x"83e" => DATA <= x"c02a";
when "11" & x"83f" => DATA <= x"e00b";
when "11" & x"840" => DATA <= x"a7c3";
when "11" & x"841" => DATA <= x"61f4";
when "11" & x"842" => DATA <= x"f83e";
when "11" & x"843" => DATA <= x"a7f9";
when "11" & x"844" => DATA <= x"54a8";
when "11" & x"845" => DATA <= x"56e5";
when "11" & x"846" => DATA <= x"5a00";
when "11" & x"847" => DATA <= x"2018";
when "11" & x"848" => DATA <= x"0900";
when "11" & x"849" => DATA <= x"0381";
when "11" & x"84a" => DATA <= x"537f";
when "11" & x"84b" => DATA <= x"8fd5";
when "11" & x"84c" => DATA <= x"fdc0";
when "11" & x"84d" => DATA <= x"001a";
when "11" & x"84e" => DATA <= x"0008";
when "11" & x"84f" => DATA <= x"4802";
when "11" & x"850" => DATA <= x"0680";
when "11" & x"851" => DATA <= x"0114";
when "11" & x"852" => DATA <= x"00a1";
when "11" & x"853" => DATA <= x"0010";
when "11" & x"854" => DATA <= x"2800";
when "11" & x"855" => DATA <= x"0940";
when "11" & x"856" => DATA <= x"0d00";
when "11" & x"857" => DATA <= x"0082";
when "11" & x"858" => DATA <= x"8000";
when "11" & x"859" => DATA <= x"9400";
when "11" & x"85a" => DATA <= x"6800";
when "11" & x"85b" => DATA <= x"0428";
when "11" & x"85c" => DATA <= x"0005";
when "11" & x"85d" => DATA <= x"4002";
when "11" & x"85e" => DATA <= x"c000";
when "11" & x"85f" => DATA <= x"2280";
when "11" & x"860" => DATA <= x"1034";
when "11" & x"861" => DATA <= x"0002";
when "11" & x"862" => DATA <= x"0002";
when "11" & x"863" => DATA <= x"2800";
when "11" & x"864" => DATA <= x"8140";
when "11" & x"865" => DATA <= x"00a0";
when "11" & x"866" => DATA <= x"0012";
when "11" & x"867" => DATA <= x"8004";
when "11" & x"868" => DATA <= x"1400";
when "11" & x"869" => DATA <= x"1000";
when "11" & x"86a" => DATA <= x"00bc";
when "11" & x"86b" => DATA <= x"0000";
when "11" & x"86c" => DATA <= x"20b0";
when "11" & x"86d" => DATA <= x"0015";
when "11" & x"86e" => DATA <= x"0000";
when "11" & x"86f" => DATA <= x"8000";
when "11" & x"870" => DATA <= x"2a00";
when "11" & x"871" => DATA <= x"0970";
when "11" & x"872" => DATA <= x"0083";
when "11" & x"873" => DATA <= x"8018";
when "11" & x"874" => DATA <= x"1400";
when "11" & x"875" => DATA <= x"4490";
when "11" & x"876" => DATA <= x"0087";
when "11" & x"877" => DATA <= x"8020";
when "11" & x"878" => DATA <= x"3400";
when "11" & x"879" => DATA <= x"2000";
when "11" & x"87a" => DATA <= x"0248";
when "11" & x"87b" => DATA <= x"0088";
when "11" & x"87c" => DATA <= x"0002";
when "11" & x"87d" => DATA <= x"1150";
when "11" & x"87e" => DATA <= x"0202";
when "11" & x"87f" => DATA <= x"4002";
when "11" & x"880" => DATA <= x"1400";
when "11" & x"881" => DATA <= x"18a0";
when "11" & x"882" => DATA <= x"0100";
when "11" & x"883" => DATA <= x"0005";
when "11" & x"884" => DATA <= x"4000";
when "11" & x"885" => DATA <= x"1580";
when "11" & x"886" => DATA <= x"0005";
when "11" & x"887" => DATA <= x"c000";
when "11" & x"888" => DATA <= x"2f00";
when "11" & x"889" => DATA <= x"0000";
when "11" & x"88a" => DATA <= x"bc00";
when "11" & x"88b" => DATA <= x"0520";
when "11" & x"88c" => DATA <= x"008a";
when "11" & x"88d" => DATA <= x"0040";
when "11" & x"88e" => DATA <= x"7000";
when "11" & x"88f" => DATA <= x"8c07";
when "11" & x"890" => DATA <= x"e008";
when "11" & x"891" => DATA <= x"a040";
when "11" & x"892" => DATA <= x"01c4";
when "11" & x"893" => DATA <= x"23e0";
when "11" & x"894" => DATA <= x"0205";
when "11" & x"895" => DATA <= x"8001";
when "11" & x"896" => DATA <= x"3c02";
when "11" & x"897" => DATA <= x"4004";
when "11" & x"898" => DATA <= x"1400";
when "11" & x"899" => DATA <= x"8490";
when "11" & x"89a" => DATA <= x"0085";
when "11" & x"89b" => DATA <= x"0010";
when "11" & x"89c" => DATA <= x"8008";
when "11" & x"89d" => DATA <= x"1a00";
when "11" & x"89e" => DATA <= x"0450";
when "11" & x"89f" => DATA <= x"02cc";
when "11" & x"8a0" => DATA <= x"0040";
when "11" & x"8a1" => DATA <= x"d000";
when "11" & x"8a2" => DATA <= x"0800";
when "11" & x"8a3" => DATA <= x"4140";
when "11" & x"8a4" => DATA <= x"0049";
when "11" & x"8a5" => DATA <= x"0012";
when "11" & x"8a6" => DATA <= x"5000";
when "11" & x"8a7" => DATA <= x"8240";
when "11" & x"8a8" => DATA <= x"003a";
when "11" & x"8a9" => DATA <= x"0010";
when "11" & x"8aa" => DATA <= x"f00a";
when "11" & x"8ab" => DATA <= x"0001";
when "11" & x"8ac" => DATA <= x"6802";
when "11" & x"8ad" => DATA <= x"0000";
when "11" & x"8ae" => DATA <= x"40d0";
when "11" & x"8af" => DATA <= x"058c";
when "11" & x"8b0" => DATA <= x"8001";
when "11" & x"8b1" => DATA <= x"2800";
when "11" & x"8b2" => DATA <= x"b200";
when "11" & x"8b3" => DATA <= x"1050";
when "11" & x"8b4" => DATA <= x"000a";
when "11" & x"8b5" => DATA <= x"8009";
when "11" & x"8b6" => DATA <= x"8000";
when "11" & x"8b7" => DATA <= x"8500";
when "11" & x"8b8" => DATA <= x"2068";
when "11" & x"8b9" => DATA <= x"0009";
when "11" & x"8ba" => DATA <= x"4112";
when "11" & x"8bb" => DATA <= x"0001";
when "11" & x"8bc" => DATA <= x"d000";
when "11" & x"8bd" => DATA <= x"0f80";
when "11" & x"8be" => DATA <= x"0100";
when "11" & x"8bf" => DATA <= x"0080";
when "11" & x"8c0" => DATA <= x"80e0";
when "11" & x"8c1" => DATA <= x"0020";
when "11" & x"8c2" => DATA <= x"a003";
when "11" & x"8c3" => DATA <= x"8700";
when "11" & x"8c4" => DATA <= x"10a8";
when "11" & x"8c5" => DATA <= x"0084";
when "11" & x"8c6" => DATA <= x"0040";
when "11" & x"8c7" => DATA <= x"0004";
when "11" & x"8c8" => DATA <= x"040e";
when "11" & x"8c9" => DATA <= x"0008";
when "11" & x"8ca" => DATA <= x"7800";
when "11" & x"8cb" => DATA <= x"4380";
when "11" & x"8cc" => DATA <= x"1894";
when "11" & x"8cd" => DATA <= x"0080";
when "11" & x"8ce" => DATA <= x"6078";
when "11" & x"8cf" => DATA <= x"0700";
when "11" & x"8d0" => DATA <= x"1001";
when "11" & x"8d1" => DATA <= x"5c00";
when "11" & x"8d2" => DATA <= x"01e0";
when "11" & x"8d3" => DATA <= x"041f";
when "11" & x"8d4" => DATA <= x"0000";
when "11" & x"8d5" => DATA <= x"7c01";
when "11" & x"8d6" => DATA <= x"4140";
when "11" & x"8d7" => DATA <= x"0203";
when "11" & x"8d8" => DATA <= x"0000";
when "11" & x"8d9" => DATA <= x"0340";
when "11" & x"8da" => DATA <= x"0080";
when "11" & x"8db" => DATA <= x"0004";
when "11" & x"8dc" => DATA <= x"4000";
when "11" & x"8dd" => DATA <= x"0080";
when "11" & x"8de" => DATA <= x"011c";
when "11" & x"8df" => DATA <= x"001e";
when "11" & x"8e0" => DATA <= x"0050";
when "11" & x"8e1" => DATA <= x"7012";
when "11" & x"8e2" => DATA <= x"c001";
when "11" & x"8e3" => DATA <= x"1200";
when "11" & x"8e4" => DATA <= x"28a0";
when "11" & x"8e5" => DATA <= x"8145";
when "11" & x"8e6" => DATA <= x"7c3f";
when "11" & x"8e7" => DATA <= x"abe1";
when "11" & x"8e8" => DATA <= x"fce8";
when "11" & x"8e9" => DATA <= x"7c3f";
when "11" & x"8ea" => DATA <= x"f4fd";
when "11" & x"8eb" => DATA <= x"7f47";
when "11" & x"8ec" => DATA <= x"e00a";
when "11" & x"8ed" => DATA <= x"ff00";
when "11" & x"8ee" => DATA <= x"3feb";
when "11" & x"8ef" => DATA <= x"fa80";
when "11" & x"8f0" => DATA <= x"01ee";
when "11" & x"8f1" => DATA <= x"f601";
when "11" & x"8f2" => DATA <= x"2cde";
when "11" & x"8f3" => DATA <= x"6b00";
when "11" & x"8f4" => DATA <= x"5141";
when "11" & x"8f5" => DATA <= x"228a";
when "11" & x"8f6" => DATA <= x"05e0";
when "11" & x"8f7" => DATA <= x"000a";
when "11" & x"8f8" => DATA <= x"2aaa";
when "11" & x"8f9" => DATA <= x"aa05";
when "11" & x"8fa" => DATA <= x"54a3";
when "11" & x"8fb" => DATA <= x"547b";
when "11" & x"8fc" => DATA <= x"f9fc";
when "11" & x"8fd" => DATA <= x"41c0";
when "11" & x"8fe" => DATA <= x"0c50";
when "11" & x"8ff" => DATA <= x"0861";
when "11" & x"900" => DATA <= x"f000";
when "11" & x"901" => DATA <= x"0212";
when "11" & x"902" => DATA <= x"1f8f";
when "11" & x"903" => DATA <= x"f400";
when "11" & x"904" => DATA <= x"000f";
when "11" & x"905" => DATA <= x"d008";
when "11" & x"906" => DATA <= x"1a8f";
when "11" & x"907" => DATA <= x"a00b";
when "11" & x"908" => DATA <= x"ff64";
when "11" & x"909" => DATA <= x"002f";
when "11" & x"90a" => DATA <= x"fdf6";
when "11" & x"90b" => DATA <= x"f300";
when "11" & x"90c" => DATA <= x"eb8d";
when "11" & x"90d" => DATA <= x"00e8";
when "11" & x"90e" => DATA <= x"0508";
when "11" & x"90f" => DATA <= x"003b";
when "11" & x"910" => DATA <= x"bfbf";
when "11" & x"911" => DATA <= x"dde2";
when "11" & x"912" => DATA <= x"793e";
when "11" & x"913" => DATA <= x"5f8f";
when "11" & x"914" => DATA <= x"e402";
when "11" & x"915" => DATA <= x"bf00";
when "11" & x"916" => DATA <= x"e007";
when "11" & x"917" => DATA <= x"8700";
when "11" & x"918" => DATA <= x"3fd9";
when "11" & x"919" => DATA <= x"ec03";
when "11" & x"91a" => DATA <= x"e3fc";
when "11" & x"91b" => DATA <= x"0080";
when "11" & x"91c" => DATA <= x"7332";
when "11" & x"91d" => DATA <= x"d8ee";
when "11" & x"91e" => DATA <= x"7703";
when "11" & x"91f" => DATA <= x"01c0";
when "11" & x"920" => DATA <= x"1f4f";
when "11" & x"921" => DATA <= x"87c3";
when "11" & x"922" => DATA <= x"69f0";
when "11" & x"923" => DATA <= x"b878";
when "11" & x"924" => DATA <= x"3e51";
when "11" & x"925" => DATA <= x"2914";
when "11" & x"926" => DATA <= x"0281";
when "11" & x"927" => DATA <= x"5a14";
when "11" & x"928" => DATA <= x"a002";
when "11" & x"929" => DATA <= x"8500";
when "11" & x"92a" => DATA <= x"1528";
when "11" & x"92b" => DATA <= x"00a9";
when "11" & x"92c" => DATA <= x"ffcf";
when "11" & x"92d" => DATA <= x"ee00";
when "11" & x"92e" => DATA <= x"5c78";
when "11" & x"92f" => DATA <= x"037f";
when "11" & x"930" => DATA <= x"c01f";
when "11" & x"931" => DATA <= x"fe00";
when "11" & x"932" => DATA <= x"7fa0";
when "11" & x"933" => DATA <= x"0084";
when "11" & x"934" => DATA <= x"802f";
when "11" & x"935" => DATA <= x"e800";
when "11" & x"936" => DATA <= x"1120";
when "11" & x"937" => DATA <= x"0dff";
when "11" & x"938" => DATA <= x"007e";
when "11" & x"939" => DATA <= x"f803";
when "11" & x"93a" => DATA <= x"fbc0";
when "11" & x"93b" => DATA <= x"0234";
when "11" & x"93c" => DATA <= x"0010";
when "11" & x"93d" => DATA <= x"f00f";
when "11" & x"93e" => DATA <= x"00d0";
when "11" & x"93f" => DATA <= x"0010";
when "11" & x"940" => DATA <= x"0020";
when "11" & x"941" => DATA <= x"0210";
when "11" & x"942" => DATA <= x"7002";
when "11" & x"943" => DATA <= x"03c0";
when "11" & x"944" => DATA <= x"3c03";
when "11" & x"945" => DATA <= x"c002";
when "11" & x"946" => DATA <= x"3400";
when "11" & x"947" => DATA <= x"10a0";
when "11" & x"948" => DATA <= x"0080";
when "11" & x"949" => DATA <= x"0041";
when "11" & x"94a" => DATA <= x"400a";
when "11" & x"94b" => DATA <= x"2010";
when "11" & x"94c" => DATA <= x"8bc0";
when "11" & x"94d" => DATA <= x"3400";
when "11" & x"94e" => DATA <= x"4000";
when "11" & x"94f" => DATA <= x"1000";
when "11" & x"950" => DATA <= x"041e";
when "11" & x"951" => DATA <= x"0020";
when "11" & x"952" => DATA <= x"f00f";
when "11" & x"953" => DATA <= x"0000";
when "11" & x"954" => DATA <= x"00bc";
when "11" & x"955" => DATA <= x"02c0";
when "11" & x"956" => DATA <= x"0434";
when "11" & x"957" => DATA <= x"0003";
when "11" & x"958" => DATA <= x"a001";
when "11" & x"959" => DATA <= x"4a02";
when "11" & x"95a" => DATA <= x"8001";
when "11" & x"95b" => DATA <= x"1e00";
when "11" & x"95c" => DATA <= x"0020";
when "11" & x"95d" => DATA <= x"7800";
when "11" & x"95e" => DATA <= x"0821";
when "11" & x"95f" => DATA <= x"4007";
when "11" & x"960" => DATA <= x"aa00";
when "11" & x"961" => DATA <= x"0848";
when "11" & x"962" => DATA <= x"03ff";
when "11" & x"963" => DATA <= x"c01f";
when "11" & x"964" => DATA <= x"fe00";
when "11" & x"965" => DATA <= x"fff0";
when "11" & x"966" => DATA <= x"01fd";
when "11" & x"967" => DATA <= x"0004";
when "11" & x"968" => DATA <= x"3c03";
when "11" & x"969" => DATA <= x"4004";
when "11" & x"96a" => DATA <= x"1200";
when "11" & x"96b" => DATA <= x"10a0";
when "11" & x"96c" => DATA <= x"0085";
when "11" & x"96d" => DATA <= x"0004";
when "11" & x"96e" => DATA <= x"3c03";
when "11" & x"96f" => DATA <= x"4010";
when "11" & x"970" => DATA <= x"1e00";
when "11" & x"971" => DATA <= x"fff0";
when "11" & x"972" => DATA <= x"07bf";
when "11" & x"973" => DATA <= x"803e";
when "11" & x"974" => DATA <= x"ec00";
when "11" & x"975" => DATA <= x"c005";
when "11" & x"976" => DATA <= x"a001";
when "11" & x"977" => DATA <= x"0700";
when "11" & x"978" => DATA <= x"007c";
when "11" & x"979" => DATA <= x"02c0";
when "11" & x"97a" => DATA <= x"0600";
when "11" & x"97b" => DATA <= x"0300";
when "11" & x"97c" => DATA <= x"0041";
when "11" & x"97d" => DATA <= x"e014";
when "11" & x"97e" => DATA <= x"0040";
when "11" & x"97f" => DATA <= x"9000";
when "11" & x"980" => DATA <= x"8700";
when "11" & x"981" => DATA <= x"0801";
when "11" & x"982" => DATA <= x"1400";
when "11" & x"983" => DATA <= x"08e0";
when "11" & x"984" => DATA <= x"006d";
when "11" & x"985" => DATA <= x"0020";
when "11" & x"986" => DATA <= x"3c03";
when "11" & x"987" => DATA <= x"c03c";
when "11" & x"988" => DATA <= x"0280";
when "11" & x"989" => DATA <= x"041e";
when "11" & x"98a" => DATA <= x"0020";
when "11" & x"98b" => DATA <= x"0c70";
when "11" & x"98c" => DATA <= x"0004";
when "11" & x"98d" => DATA <= x"4160";
when "11" & x"98e" => DATA <= x"0200";
when "11" & x"98f" => DATA <= x"0800";
when "11" & x"990" => DATA <= x"1140";
when "11" & x"991" => DATA <= x"0080";
when "11" & x"992" => DATA <= x"0004";
when "11" & x"993" => DATA <= x"3c00";
when "11" & x"994" => DATA <= x"a0ef";
when "11" & x"995" => DATA <= x"00d0";
when "11" & x"996" => DATA <= x"0040";
when "11" & x"997" => DATA <= x"0141";
when "11" & x"998" => DATA <= x"a00e";
when "11" & x"999" => DATA <= x"c7e3";
when "11" & x"99a" => DATA <= x"e1d8";
when "11" & x"99b" => DATA <= x"fc7c";
when "11" & x"99c" => DATA <= x"3f9f";
when "11" & x"99d" => DATA <= x"167e";
when "11" & x"99e" => DATA <= x"bf1f";
when "11" & x"99f" => DATA <= x"d7f8";
when "11" & x"9a0" => DATA <= x"02bf";
when "11" & x"9a1" => DATA <= x"8015";
when "11" & x"9a2" => DATA <= x"fe2b";
when "11" & x"9a3" => DATA <= x"1780";
when "11" & x"9a4" => DATA <= x"0560";
when "11" & x"9a5" => DATA <= x"a200";
when "11" & x"9a6" => DATA <= x"b42e";
when "11" & x"9a7" => DATA <= x"01b0";
when "11" & x"9a8" => DATA <= x"0482";
when "11" & x"9a9" => DATA <= x"2900";
when "11" & x"9aa" => DATA <= x"8b44";
when "11" & x"9ab" => DATA <= x"a210";
when "11" & x"9ac" => DATA <= x"08a5";
when "11" & x"9ad" => DATA <= x"51fc";
when "11" & x"9ae" => DATA <= x"8f4f";
when "11" & x"9af" => DATA <= x"effa";
when "11" & x"9b0" => DATA <= x"7f23";
when "11" & x"9b1" => DATA <= x"be00";
when "11" & x"9b2" => DATA <= x"5400";
when "11" & x"9b3" => DATA <= x"fb00";
when "11" & x"9b4" => DATA <= x"0200";
when "11" & x"9b5" => DATA <= x"4ffe";
when "11" & x"9b6" => DATA <= x"0001";
when "11" & x"9b7" => DATA <= x"f000";
when "11" & x"9b8" => DATA <= x"fdc0";
when "11" & x"9b9" => DATA <= x"0098";
when "11" & x"9ba" => DATA <= x"0702";
when "11" & x"9bb" => DATA <= x"001f";
when "11" & x"9bc" => DATA <= x"7ffd";
when "11" & x"9bd" => DATA <= x"e6fb";
when "11" & x"9be" => DATA <= x"eff7";
when "11" & x"9bf" => DATA <= x"df80";
when "11" & x"9c0" => DATA <= x"847c";
when "11" & x"9c1" => DATA <= x"0000";
when "11" & x"9c2" => DATA <= x"e777";
when "11" & x"9c3" => DATA <= x"b9e7";
when "11" & x"9c4" => DATA <= x"bdfe";
when "11" & x"9c5" => DATA <= x"805c";
when "11" & x"9c6" => DATA <= x"0eb6";
when "11" & x"9c7" => DATA <= x"fb40";
when "11" & x"9c8" => DATA <= x"2bfc";
when "11" & x"9c9" => DATA <= x"1fa0";
when "11" & x"9ca" => DATA <= x"0ff6";
when "11" & x"9cb" => DATA <= x"0380";
when "11" & x"9cc" => DATA <= x"00e0";
when "11" & x"9cd" => DATA <= x"7130";
when "11" & x"9ce" => DATA <= x"9c0c";
when "11" & x"9cf" => DATA <= x"0703";
when "11" & x"9d0" => DATA <= x"8e87";
when "11" & x"9d1" => DATA <= x"d3f4";
when "11" & x"9d2" => DATA <= x"3e1e";
when "11" & x"9d3" => DATA <= x"09a7";
when "11" & x"9d4" => DATA <= x"c2b4";
when "11" & x"9d5" => DATA <= x"0a0d";
when "11" & x"9d6" => DATA <= x"0050";
when "11" & x"9d7" => DATA <= x"2014";
when "11" & x"9d8" => DATA <= x"fc54";
when "11" & x"9d9" => DATA <= x"0017";
when "11" & x"9da" => DATA <= x"c21c";
when "11" & x"9db" => DATA <= x"a9bf";
when "11" & x"9dc" => DATA <= x"d5fe";
when "11" & x"9dd" => DATA <= x"fe00";
when "11" & x"9de" => DATA <= x"d000";
when "11" & x"9df" => DATA <= x"4000";
when "11" & x"9e0" => DATA <= x"b8d0";
when "11" & x"9e1" => DATA <= x"0040";
when "11" & x"9e2" => DATA <= x"01bf";
when "11" & x"9e3" => DATA <= x"e00e";
when "11" & x"9e4" => DATA <= x"fa00";
when "11" & x"9e5" => DATA <= x"1048";
when "11" & x"9e6" => DATA <= x"01fa";
when "11" & x"9e7" => DATA <= x"8002";
when "11" & x"9e8" => DATA <= x"1400";
when "11" & x"9e9" => DATA <= x"0200";
when "11" & x"9ea" => DATA <= x"2df4";
when "11" & x"9eb" => DATA <= x"0102";
when "11" & x"9ec" => DATA <= x"006d";
when "11" & x"9ed" => DATA <= x"e801";
when "11" & x"9ee" => DATA <= x"0000";
when "11" & x"9ef" => DATA <= x"edf0";
when "11" & x"9f0" => DATA <= x"03f7";
when "11" & x"9f1" => DATA <= x"8006";
when "11" & x"9f2" => DATA <= x"fc03";
when "11" & x"9f3" => DATA <= x"c024";
when "11" & x"9f4" => DATA <= x"0021";
when "11" & x"9f5" => DATA <= x"a001";
when "11" & x"9f6" => DATA <= x"0031";
when "11" & x"9f7" => DATA <= x"0280";
when "11" & x"9f8" => DATA <= x"009c";
when "11" & x"9f9" => DATA <= x"0080";
when "11" & x"9fa" => DATA <= x"0878";
when "11" & x"9fb" => DATA <= x"0780";
when "11" & x"9fc" => DATA <= x"5800";
when "11" & x"9fd" => DATA <= x"4280";
when "11" & x"9fe" => DATA <= x"0412";
when "11" & x"9ff" => DATA <= x"0020";
when "11" & x"a00" => DATA <= x"0008";
when "11" & x"a01" => DATA <= x"b801";
when "11" & x"a02" => DATA <= x"01c0";
when "11" & x"a03" => DATA <= x"001f";
when "11" & x"a04" => DATA <= x"00f0";
when "11" & x"a05" => DATA <= x"0000";
when "11" & x"a06" => DATA <= x"07c0";
when "11" & x"a07" => DATA <= x"3803";
when "11" & x"a08" => DATA <= x"80bc";
when "11" & x"a09" => DATA <= x"02c0";
when "11" & x"a0a" => DATA <= x"1012";
when "11" & x"a0b" => DATA <= x"0008";
when "11" & x"a0c" => DATA <= x"1500";
when "11" & x"a0d" => DATA <= x"1008";
when "11" & x"a0e" => DATA <= x"221a";
when "11" & x"a0f" => DATA <= x"0000";
when "11" & x"a10" => DATA <= x"61f0";
when "11" & x"a11" => DATA <= x"0e00";
when "11" & x"a12" => DATA <= x"0168";
when "11" & x"a13" => DATA <= x"000a";
when "11" & x"a14" => DATA <= x"8004";
when "11" & x"a15" => DATA <= x"6001";
when "11" & x"a16" => DATA <= x"d800";
when "11" & x"a17" => DATA <= x"05c0";
when "11" & x"a18" => DATA <= x"0100";
when "11" & x"a19" => DATA <= x"0282";
when "11" & x"a1a" => DATA <= x"8010";
when "11" & x"a1b" => DATA <= x"3400";
when "11" & x"a1c" => DATA <= x"0800";
when "11" & x"a1d" => DATA <= x"0228";
when "11" & x"a1e" => DATA <= x"0081";
when "11" & x"a1f" => DATA <= x"2008";
when "11" & x"a20" => DATA <= x"da00";
when "11" & x"a21" => DATA <= x"1050";
when "11" & x"a22" => DATA <= x"0010";
when "11" & x"a23" => DATA <= x"000c";
when "11" & x"a24" => DATA <= x"f00f";
when "11" & x"a25" => DATA <= x"00b0";
when "11" & x"a26" => DATA <= x"0085";
when "11" & x"a27" => DATA <= x"0004";
when "11" & x"a28" => DATA <= x"2400";
when "11" & x"a29" => DATA <= x"41c0";
when "11" & x"a2a" => DATA <= x"010b";
when "11" & x"a2b" => DATA <= x"0040";
when "11" & x"a2c" => DATA <= x"6800";
when "11" & x"a2d" => DATA <= x"1000";
when "11" & x"a2e" => DATA <= x"66d0";
when "11" & x"a2f" => DATA <= x"0010";
when "11" & x"a30" => DATA <= x"0029";
when "11" & x"a31" => DATA <= x"4001";
when "11" & x"a32" => DATA <= x"0a00";
when "11" & x"a33" => DATA <= x"4080";
when "11" & x"a34" => DATA <= x"1154";
when "11" & x"a35" => DATA <= x"0018";
when "11" & x"a36" => DATA <= x"0810";
when "11" & x"a37" => DATA <= x"0e00";
when "11" & x"a38" => DATA <= x"0381";
when "11" & x"a39" => DATA <= x"40e1";
when "11" & x"a3a" => DATA <= x"c000";
when "11" & x"a3b" => DATA <= x"1000";
when "11" & x"a3c" => DATA <= x"0400";
when "11" & x"a3d" => DATA <= x"01e0";
when "11" & x"a3e" => DATA <= x"0027";
when "11" & x"a3f" => DATA <= x"8050";
when "11" & x"a40" => DATA <= x"000c";
when "11" & x"a41" => DATA <= x"0200";
when "11" & x"a42" => DATA <= x"2150";
when "11" & x"a43" => DATA <= x"0108";
when "11" & x"a44" => DATA <= x"01c0";
when "11" & x"a45" => DATA <= x"440e";
when "11" & x"a46" => DATA <= x"0008";
when "11" & x"a47" => DATA <= x"6800";
when "11" & x"a48" => DATA <= x"2340";
when "11" & x"a49" => DATA <= x"0080";
when "11" & x"a4a" => DATA <= x"0085";
when "11" & x"a4b" => DATA <= x"4050";
when "11" & x"a4c" => DATA <= x"0202";
when "11" & x"a4d" => DATA <= x"4008";
when "11" & x"a4e" => DATA <= x"1400";
when "11" & x"a4f" => DATA <= x"f0a0";
when "11" & x"a50" => DATA <= x"0024";
when "11" & x"a51" => DATA <= x"8030";
when "11" & x"a52" => DATA <= x"0056";
when "11" & x"a53" => DATA <= x"0029";
when "11" & x"a54" => DATA <= x"d000";
when "11" & x"a55" => DATA <= x"8000";
when "11" & x"a56" => DATA <= x"4140";
when "11" & x"a57" => DATA <= x"021f";
when "11" & x"a58" => DATA <= x"0000";
when "11" & x"a59" => DATA <= x"8001";
when "11" & x"a5a" => DATA <= x"0010";
when "11" & x"a5b" => DATA <= x"0063";
when "11" & x"a5c" => DATA <= x"c008";
when "11" & x"a5d" => DATA <= x"1e00";
when "11" & x"a5e" => DATA <= x"0014";
when "11" & x"a5f" => DATA <= x"2201";
when "11" & x"a60" => DATA <= x"0007";
when "11" & x"a61" => DATA <= x"c700";
when "11" & x"a62" => DATA <= x"3e1f";
when "11" & x"a63" => DATA <= x"ce87";
when "11" & x"a64" => DATA <= x"c3fd";
when "11" & x"a65" => DATA <= x"d8fc";
when "11" & x"a66" => DATA <= x"7c51";
when "11" & x"a67" => DATA <= x"fd5f";
when "11" & x"a68" => DATA <= x"d1fa";
when "11" & x"a69" => DATA <= x"fc7f";
when "11" & x"a6a" => DATA <= x"4015";
when "11" & x"a6b" => DATA <= x"fe00";
when "11" & x"a6c" => DATA <= x"7f9f";
when "11" & x"a6d" => DATA <= x"c001";
when "11" & x"a6e" => DATA <= x"c005";
when "11" & x"a6f" => DATA <= x"0300";
when "11" & x"a70" => DATA <= x"0034";
when "11" & x"a71" => DATA <= x"015e";
when "11" & x"a72" => DATA <= x"0e0a";
when "11" & x"a73" => DATA <= x"f048";
when "11" & x"a74" => DATA <= x"001e";
when "11" & x"a75" => DATA <= x"0a8a";
when "11" & x"a76" => DATA <= x"aa51";
when "11" & x"a77" => DATA <= x"2090";
when "11" & x"a78" => DATA <= x"08a7";
when "11" & x"a79" => DATA <= x"57bf";
when "11" & x"a7a" => DATA <= x"9fdf";
when "11" & x"a7b" => DATA <= x"8b80";
when "11" & x"a7c" => DATA <= x"c305";
when "11" & x"a7d" => DATA <= x"8b40";
when "11" & x"a7e" => DATA <= x"0227";
when "11" & x"a7f" => DATA <= x"fb84";
when "11" & x"a80" => DATA <= x"0007";
when "11" & x"a81" => DATA <= x"7fbf";
when "11" & x"a82" => DATA <= x"0000";
when "11" & x"a83" => DATA <= x"4aff";
when "11" & x"a84" => DATA <= x"7800";
when "11" & x"a85" => DATA <= x"01e0";
when "11" & x"a86" => DATA <= x"1a80";
when "11" & x"a87" => DATA <= x"eff6";
when "11" & x"a88" => DATA <= x"0001";
when "11" & x"a89" => DATA <= x"800f";
when "11" & x"a8a" => DATA <= x"3ff7";
when "11" & x"a8b" => DATA <= x"fbed";
when "11" & x"a8c" => DATA <= x"e0e3";
when "11" & x"a8d" => DATA <= x"5934";
when "11" & x"a8e" => DATA <= x"e5c6";
when "11" & x"a8f" => DATA <= x"4040";
when "11" & x"a90" => DATA <= x"010b";
when "11" & x"a91" => DATA <= x"007f";
when "11" & x"a92" => DATA <= x"bbcd";
when "11" & x"a93" => DATA <= x"e077";
when "11" & x"a94" => DATA <= x"3abd";
when "11" & x"a95" => DATA <= x"daef";
when "11" & x"a96" => DATA <= x"1f80";
when "11" & x"a97" => DATA <= x"8000";
when "11" & x"a98" => DATA <= x"2000";
when "11" & x"a99" => DATA <= x"a86c";
when "11" & x"a9a" => DATA <= x"3e00";
when "11" & x"a9b" => DATA <= x"3c2c";
when "11" & x"a9c" => DATA <= x"01f8";
when "11" & x"a9d" => DATA <= x"ffb0";
when "11" & x"a9e" => DATA <= x"073b";
when "11" & x"a9f" => DATA <= x"3dcc";
when "11" & x"aa0" => DATA <= x"02ae";
when "11" & x"aa1" => DATA <= x"0603";
when "11" & x"aa2" => DATA <= x"f836";
when "11" & x"aa3" => DATA <= x"1f4f";
when "11" & x"aa4" => DATA <= x"83c3";
when "11" & x"aa5" => DATA <= x"e9f0";
when "11" & x"aa6" => DATA <= x"fa7c";
when "11" & x"aa7" => DATA <= x"0800";
when "11" & x"aa8" => DATA <= x"0201";
when "11" & x"aa9" => DATA <= x"7804";
when "11" & x"aaa" => DATA <= x"0800";
when "11" & x"aab" => DATA <= x"2a10";
when "11" & x"aac" => DATA <= x"0000";
when "11" & x"aad" => DATA <= x"40a0";
when "11" & x"aae" => DATA <= x"00ab";
when "11" & x"aaf" => DATA <= x"dfc7";
when "11" & x"ab0" => DATA <= x"eefe";
when "11" & x"ab1" => DATA <= x"7fbe";
when "11" & x"ab2" => DATA <= x"2400";
when "11" & x"ab3" => DATA <= x"0200";
when "11" & x"ab4" => DATA <= x"5c37";
when "11" & x"ab5" => DATA <= x"6c01";
when "11" & x"ab6" => DATA <= x"aabf";
when "11" & x"ab7" => DATA <= x"e000";
when "11" & x"ab8" => DATA <= x"1500";
when "11" & x"ab9" => DATA <= x"3fcd";
when "11" & x"aba" => DATA <= x"b600";
when "11" & x"abb" => DATA <= x"ef5f";
when "11" & x"abc" => DATA <= x"f000";
when "11" & x"abd" => DATA <= x"1280";
when "11" & x"abe" => DATA <= x"16ef";
when "11" & x"abf" => DATA <= x"bb00";
when "11" & x"ac0" => DATA <= x"6dbf";
when "11" & x"ac1" => DATA <= x"6c01";
when "11" & x"ac2" => DATA <= x"fa4e";
when "11" & x"ac3" => DATA <= x"b007";
when "11" & x"ac4" => DATA <= x"f846";
when "11" & x"ac5" => DATA <= x"8002";
when "11" & x"ac6" => DATA <= x"014a";
when "11" & x"ac7" => DATA <= x"001f";
when "11" & x"ac8" => DATA <= x"f000";
when "11" & x"ac9" => DATA <= x"07c0";
when "11" & x"aca" => DATA <= x"041a";
when "11" & x"acb" => DATA <= x"0010";
when "11" & x"acc" => DATA <= x"0308";
when "11" & x"acd" => DATA <= x"3800";
when "11" & x"ace" => DATA <= x"09a0";
when "11" & x"acf" => DATA <= x"040f";
when "11" & x"ad0" => DATA <= x"00f0";
when "11" & x"ad1" => DATA <= x"0900";
when "11" & x"ad2" => DATA <= x"0850";
when "11" & x"ad3" => DATA <= x"0043";
when "11" & x"ad4" => DATA <= x"8002";
when "11" & x"ad5" => DATA <= x"2200";
when "11" & x"ad6" => DATA <= x"008a";
when "11" & x"ad7" => DATA <= x"8004";
when "11" & x"ad8" => DATA <= x"1e01";
when "11" & x"ad9" => DATA <= x"6003";
when "11" & x"ada" => DATA <= x"0f00";
when "11" & x"adb" => DATA <= x"f00b";
when "11" & x"adc" => DATA <= x"0001";
when "11" & x"add" => DATA <= x"5000";
when "11" & x"ade" => DATA <= x"4804";
when "11" & x"adf" => DATA <= x"00a0";
when "11" & x"ae0" => DATA <= x"2f00";
when "11" & x"ae1" => DATA <= x"a001";
when "11" & x"ae2" => DATA <= x"0d80";
when "11" & x"ae3" => DATA <= x"2000";
when "11" & x"ae4" => DATA <= x"1500";
when "11" & x"ae5" => DATA <= x"0060";
when "11" & x"ae6" => DATA <= x"1011";
when "11" & x"ae7" => DATA <= x"0002";
when "11" & x"ae8" => DATA <= x"0580";
when "11" & x"ae9" => DATA <= x"2000";
when "11" & x"aea" => DATA <= x"1501";
when "11" & x"aeb" => DATA <= x"c00c";
when "11" & x"aec" => DATA <= x"27dd";
when "11" & x"aed" => DATA <= x"0004";
when "11" & x"aee" => DATA <= x"4000";
when "11" & x"aef" => DATA <= x"2000";
when "11" & x"af0" => DATA <= x"45ff";
when "11" & x"af1" => DATA <= x"e00f";
when "11" & x"af2" => DATA <= x"ef00";
when "11" & x"af3" => DATA <= x"7ff8";
when "11" & x"af4" => DATA <= x"00ff";
when "11" & x"af5" => DATA <= x"c03c";
when "11" & x"af6" => DATA <= x"0000";
when "11" & x"af7" => DATA <= x"20f0";
when "11" & x"af8" => DATA <= x"0085";
when "11" & x"af9" => DATA <= x"0004";
when "11" & x"afa" => DATA <= x"3802";
when "11" & x"afb" => DATA <= x"8428";
when "11" & x"afc" => DATA <= x"0021";
when "11" & x"afd" => DATA <= x"c001";
when "11" & x"afe" => DATA <= x"1407";
when "11" & x"aff" => DATA <= x"803b";
when "11" & x"b00" => DATA <= x"fc01";
when "11" & x"b01" => DATA <= x"efe0";
when "11" & x"b02" => DATA <= x"0fff";
when "11" & x"b03" => DATA <= x"003b";
when "11" & x"b04" => DATA <= x"8001";
when "11" & x"b05" => DATA <= x"0100";
when "11" & x"b06" => DATA <= x"0102";
when "11" & x"b07" => DATA <= x"8000";
when "11" & x"b08" => DATA <= x"3e01";
when "11" & x"b09" => DATA <= x"e000";
when "11" & x"b0a" => DATA <= x"0012";
when "11" & x"b0b" => DATA <= x"0000";
when "11" & x"b0c" => DATA <= x"0640";
when "11" & x"b0d" => DATA <= x"5000";
when "11" & x"b0e" => DATA <= x"0404";
when "11" & x"b0f" => DATA <= x"0001";
when "11" & x"b10" => DATA <= x"1080";
when "11" & x"b11" => DATA <= x"0420";
when "11" & x"b12" => DATA <= x"0008";
when "11" & x"b13" => DATA <= x"21a0";
when "11" & x"b14" => DATA <= x"010f";
when "11" & x"b15" => DATA <= x"0000";
when "11" & x"b16" => DATA <= x"0228";
when "11" & x"b17" => DATA <= x"0009";
when "11" & x"b18" => DATA <= x"4000";
when "11" & x"b19" => DATA <= x"4200";
when "11" & x"b1a" => DATA <= x"6240";
when "11" & x"b1b" => DATA <= x"1c06";
when "11" & x"b1c" => DATA <= x"0183";
when "11" & x"b1d" => DATA <= x"c240";
when "11" & x"b1e" => DATA <= x"0805";
when "11" & x"b1f" => DATA <= x"e401";
when "11" & x"b20" => DATA <= x"4340";
when "11" & x"b21" => DATA <= x"0060";
when "11" & x"b22" => DATA <= x"1000";
when "11" & x"b23" => DATA <= x"6380";
when "11" & x"b24" => DATA <= x"003e";
when "11" & x"b25" => DATA <= x"0001";
when "11" & x"b26" => DATA <= x"a001";
when "11" & x"b27" => DATA <= x"0c80";
when "11" & x"b28" => DATA <= x"0068";
when "11" & x"b29" => DATA <= x"0002";
when "11" & x"b2a" => DATA <= x"6190";
when "11" & x"b2b" => DATA <= x"0100";
when "11" & x"b2c" => DATA <= x"00c9";
when "11" & x"b2d" => DATA <= x"a000";
when "11" & x"b2e" => DATA <= x"8b00";
when "11" & x"b2f" => DATA <= x"a085";
when "11" & x"b30" => DATA <= x"4021";
when "11" & x"b31" => DATA <= x"fcfc";
when "11" & x"b32" => DATA <= x"7c3f";
when "11" & x"b33" => DATA <= x"abe1";
when "11" & x"b34" => DATA <= x"fce8";
when "11" & x"b35" => DATA <= x"e3f5";
when "11" & x"b36" => DATA <= x"ff1f";
when "11" & x"b37" => DATA <= x"afd7";
when "11" & x"b38" => DATA <= x"cbf0";
when "11" & x"b39" => DATA <= x"027c";
when "11" & x"b3a" => DATA <= x"bf48";
when "11" & x"b3b" => DATA <= x"03f0";
when "11" & x"b3c" => DATA <= x"2228";
when "11" & x"b3d" => DATA <= x"6140";
when "11" & x"b3e" => DATA <= x"0161";
when "11" & x"b3f" => DATA <= x"0098";
when "11" & x"b40" => DATA <= x"0010";
when "11" & x"b41" => DATA <= x"6380";
when "11" & x"b42" => DATA <= x"1800";
when "11" & x"b43" => DATA <= x"0600";
when "11" & x"b44" => DATA <= x"0110";
when "11" & x"b45" => DATA <= x"8a61";
when "11" & x"b46" => DATA <= x"2290";
when "11" & x"b47" => DATA <= x"2825";
when "11" & x"b48" => DATA <= x"42aa";
when "11" & x"b49" => DATA <= x"5fcd";
when "11" & x"b4a" => DATA <= x"fcfe";
when "11" & x"b4b" => DATA <= x"0002";
when "11" & x"b4c" => DATA <= x"7003";
when "11" & x"b4d" => DATA <= x"1402";
when "11" & x"b4e" => DATA <= x"f8a0";
when "11" & x"b4f" => DATA <= x"0020";
when "11" & x"b50" => DATA <= x"01f8";
when "11" & x"b51" => DATA <= x"ff90";
when "11" & x"b52" => DATA <= x"0a80";
when "11" & x"b53" => DATA <= x"40d4";
when "11" & x"b54" => DATA <= x"7b83";
when "11" & x"b55" => DATA <= x"ffeb";
when "11" & x"b56" => DATA <= x"febe";
when "11" & x"b57" => DATA <= x"dfef";
when "11" & x"b58" => DATA <= x"beff";
when "11" & x"b59" => DATA <= x"0048";
when "11" & x"b5a" => DATA <= x"0f38";
when "11" & x"b5b" => DATA <= x"e800";
when "11" & x"b5c" => DATA <= x"4280";
when "11" & x"b5d" => DATA <= x"1df3";
when "11" & x"b5e" => DATA <= x"feef";
when "11" & x"b5f" => DATA <= x"03b9";
when "11" & x"b60" => DATA <= x"e8f9";
when "11" & x"b61" => DATA <= x"7cbf";
when "11" & x"b62" => DATA <= x"07d0";
when "11" & x"b63" => DATA <= x"0081";
when "11" & x"b64" => DATA <= x"f87c";
when "11" & x"b65" => DATA <= x"2780";
when "11" & x"b66" => DATA <= x"5c1c";
when "11" & x"b67" => DATA <= x"00ff";
when "11" & x"b68" => DATA <= x"603c";
when "11" & x"b69" => DATA <= x"0f8f";
when "11" & x"b6a" => DATA <= x"fe00";
when "11" & x"b6b" => DATA <= x"77b0";
when "11" & x"b6c" => DATA <= x"dcfd";
when "11" & x"b6d" => DATA <= x"c000";
when "11" & x"b6e" => DATA <= x"7107";
when "11" & x"b6f" => DATA <= x"c369";
when "11" & x"b70" => DATA <= x"f0f8";
when "11" & x"b71" => DATA <= x"7b87";
when "11" & x"b72" => DATA <= x"c000";
when "11" & x"b73" => DATA <= x"412d";
when "11" & x"b74" => DATA <= x"0200";
when "11" & x"b75" => DATA <= x"2914";
when "11" & x"b76" => DATA <= x"2940";
when "11" & x"b77" => DATA <= x"054a";
when "11" & x"b78" => DATA <= x"002a";
when "11" & x"b79" => DATA <= x"143b";
when "11" & x"b7a" => DATA <= x"f9ff";
when "11" & x"b7b" => DATA <= x"3fc1";
when "11" & x"b7c" => DATA <= x"0002";
when "11" & x"b7d" => DATA <= x"e280";
when "11" & x"b7e" => DATA <= x"1514";
when "11" & x"b7f" => DATA <= x"0008";
when "11" & x"b80" => DATA <= x"0037";
when "11" & x"b81" => DATA <= x"e800";
when "11" & x"b82" => DATA <= x"8400";
when "11" & x"b83" => DATA <= x"40d0";
when "11" & x"b84" => DATA <= x"03fe";
when "11" & x"b85" => DATA <= x"8017";
when "11" & x"b86" => DATA <= x"6002";
when "11" & x"b87" => DATA <= x"0500";
when "11" & x"b88" => DATA <= x"1fe8";
when "11" & x"b89" => DATA <= x"00a0";
when "11" & x"b8a" => DATA <= x"0010";
when "11" & x"b8b" => DATA <= x"5002";
when "11" & x"b8c" => DATA <= x"fe80";
when "11" & x"b8d" => DATA <= x"0114";
when "11" & x"b8e" => DATA <= x"0081";
when "11" & x"b8f" => DATA <= x"0036";
when "11" & x"b90" => DATA <= x"f400";
when "11" & x"b91" => DATA <= x"8000";
when "11" & x"b92" => DATA <= x"7ed0";
when "11" & x"b93" => DATA <= x"0282";
when "11" & x"b94" => DATA <= x"400d";
when "11" & x"b95" => DATA <= x"d400";
when "11" & x"b96" => DATA <= x"4a00";
when "11" & x"b97" => DATA <= x"0128";
when "11" & x"b98" => DATA <= x"0037";
when "11" & x"b99" => DATA <= x"4001";
when "11" & x"b9a" => DATA <= x"1000";
when "11" & x"b9b" => DATA <= x"0bc0";
when "11" & x"b9c" => DATA <= x"3c02";
when "11" & x"b9d" => DATA <= x"8000";
when "11" & x"b9e" => DATA <= x"400a";
when "11" & x"b9f" => DATA <= x"011b";
when "11" & x"ba0" => DATA <= x"8000";
when "11" & x"ba1" => DATA <= x"21fe";
when "11" & x"ba2" => DATA <= x"0001";
when "11" & x"ba3" => DATA <= x"7002";
when "11" & x"ba4" => DATA <= x"03c0";
when "11" & x"ba5" => DATA <= x"021e";
when "11" & x"ba6" => DATA <= x"01c0";
when "11" & x"ba7" => DATA <= x"010a";
when "11" & x"ba8" => DATA <= x"0008";
when "11" & x"ba9" => DATA <= x"4800";
when "11" & x"baa" => DATA <= x"8804";
when "11" & x"bab" => DATA <= x"2210";
when "11" & x"bac" => DATA <= x"0084";
when "11" & x"bad" => DATA <= x"480f";
when "11" & x"bae" => DATA <= x"00e0";
when "11" & x"baf" => DATA <= x"0107";
when "11" & x"bb0" => DATA <= x"0020";
when "11" & x"bb1" => DATA <= x"2400";
when "11" & x"bb2" => DATA <= x"0340";
when "11" & x"bb3" => DATA <= x"001f";
when "11" & x"bb4" => DATA <= x"0000";
when "11" & x"bb5" => DATA <= x"0080";
when "11" & x"bb6" => DATA <= x"002f";
when "11" & x"bb7" => DATA <= x"0000";
when "11" & x"bb8" => DATA <= x"0078";
when "11" & x"bb9" => DATA <= x"0011";
when "11" & x"bba" => DATA <= x"c002";
when "11" & x"bbb" => DATA <= x"0040";
when "11" & x"bbc" => DATA <= x"0042";
when "11" & x"bbd" => DATA <= x"0060";
when "11" & x"bbe" => DATA <= x"101c";
when "11" & x"bbf" => DATA <= x"0003";
when "11" & x"bc0" => DATA <= x"4d00";
when "11" & x"bc1" => DATA <= x"30ec";
when "11" & x"bc2" => DATA <= x"0080";
when "11" & x"bc3" => DATA <= x"0060";
when "11" & x"bc4" => DATA <= x"001c";
when "11" & x"bc5" => DATA <= x"1200";
when "11" & x"bc6" => DATA <= x"f001";
when "11" & x"bc7" => DATA <= x"800f";
when "11" & x"bc8" => DATA <= x"7400";
when "11" & x"bc9" => DATA <= x"f000";
when "11" & x"bca" => DATA <= x"00e8";
when "11" & x"bcb" => DATA <= x"0163";
when "11" & x"bcc" => DATA <= x"400b";
when "11" & x"bcd" => DATA <= x"7a00";
when "11" & x"bce" => DATA <= x"0400";
when "11" & x"bcf" => DATA <= x"1b34";
when "11" & x"bd0" => DATA <= x"0057";
when "11" & x"bd1" => DATA <= x"0020";
when "11" & x"bd2" => DATA <= x"6801";
when "11" & x"bd3" => DATA <= x"db40";
when "11" & x"bd4" => DATA <= x"0bd0";
when "11" & x"bd5" => DATA <= x"0100";
when "11" & x"bd6" => DATA <= x"0800";
when "11" & x"bd7" => DATA <= x"1750";
when "11" & x"bd8" => DATA <= x"006c";
when "11" & x"bd9" => DATA <= x"0020";
when "11" & x"bda" => DATA <= x"f00e";
when "11" & x"bdb" => DATA <= x"0010";
when "11" & x"bdc" => DATA <= x"7800";
when "11" & x"bdd" => DATA <= x"43c0";
when "11" & x"bde" => DATA <= x"2442";
when "11" & x"bdf" => DATA <= x"4010";
when "11" & x"be0" => DATA <= x"1400";
when "11" & x"be1" => DATA <= x"8000";
when "11" & x"be2" => DATA <= x"1000";
when "11" & x"be3" => DATA <= x"8003";
when "11" & x"be4" => DATA <= x"7500";
when "11" & x"be5" => DATA <= x"3bc0";
when "11" & x"be6" => DATA <= x"0200";
when "11" & x"be7" => DATA <= x"1001";
when "11" & x"be8" => DATA <= x"6f40";
when "11" & x"be9" => DATA <= x"0ff0";
when "11" & x"bea" => DATA <= x"0080";
when "11" & x"beb" => DATA <= x"0200";
when "11" & x"bec" => DATA <= x"4dd0";
when "11" & x"bed" => DATA <= x"03b8";
when "11" & x"bee" => DATA <= x"0010";
when "11" & x"bef" => DATA <= x"3800";
when "11" & x"bf0" => DATA <= x"0f25";
when "11" & x"bf1" => DATA <= x"0381";
when "11" & x"bf2" => DATA <= x"5400";
when "11" & x"bf3" => DATA <= x"7800";
when "11" & x"bf4" => DATA <= x"8000";
when "11" & x"bf5" => DATA <= x"6000";
when "11" & x"bf6" => DATA <= x"1d00";
when "11" & x"bf7" => DATA <= x"03c0";
when "11" & x"bf8" => DATA <= x"9e00";
when "11" & x"bf9" => DATA <= x"0100";
when "11" & x"bfa" => DATA <= x"07c1";
when "11" & x"bfb" => DATA <= x"e1c0";
when "11" & x"bfc" => DATA <= x"0540";
when "11" & x"bfd" => DATA <= x"1080";
when "11" & x"bfe" => DATA <= x"1404";
when "11" & x"bff" => DATA <= x"0001";
when "11" & x"c00" => DATA <= x"0008";
when "11" & x"c01" => DATA <= x"400a";
when "11" & x"c02" => DATA <= x"10e0";
when "11" & x"c03" => DATA <= x"0100";
when "11" & x"c04" => DATA <= x"0a80";
when "11" & x"c05" => DATA <= x"011e";
when "11" & x"c06" => DATA <= x"0140";
when "11" & x"c07" => DATA <= x"080a";
when "11" & x"c08" => DATA <= x"0002";
when "11" & x"c09" => DATA <= x"4803";
when "11" & x"c0a" => DATA <= x"4020";
when "11" & x"c0b" => DATA <= x"000a";
when "11" & x"c0c" => DATA <= x"4802";
when "11" & x"c0d" => DATA <= x"2e80";
when "11" & x"c0e" => DATA <= x"1012";
when "11" & x"c0f" => DATA <= x"0039";
when "11" & x"c10" => DATA <= x"a004";
when "11" & x"c11" => DATA <= x"3d00";
when "11" & x"c12" => DATA <= x"0600";
when "11" & x"c13" => DATA <= x"0210";
when "11" & x"c14" => DATA <= x"c000";
when "11" & x"c15" => DATA <= x"0320";
when "11" & x"c16" => DATA <= x"020f";
when "11" & x"c17" => DATA <= x"000c";
when "11" & x"c18" => DATA <= x"0000";
when "11" & x"c19" => DATA <= x"2409";
when "11" & x"c1a" => DATA <= x"0020";
when "11" & x"c1b" => DATA <= x"5001";
when "11" & x"c1c" => DATA <= x"97c0";
when "11" & x"c1d" => DATA <= x"2801";
when "11" & x"c1e" => DATA <= x"6560";
when "11" & x"c1f" => DATA <= x"0fc7";
when "11" & x"c20" => DATA <= x"dbb1";
when "11" & x"c21" => DATA <= x"f8f8";
when "11" & x"c22" => DATA <= x"7f57";
when "11" & x"c23" => DATA <= x"c2fc";
when "11" & x"c24" => DATA <= x"7f57";
when "11" & x"c25" => DATA <= x"e3f5";
when "11" & x"c26" => DATA <= x"ff1f";
when "11" & x"c27" => DATA <= x"802a";
when "11" & x"c28" => DATA <= x"5d00";
when "11" & x"c29" => DATA <= x"b709";
when "11" & x"c2a" => DATA <= x"0400";
when "11" & x"c2b" => DATA <= x"2261";
when "11" & x"c2c" => DATA <= x"0a85";
when "11" & x"c2d" => DATA <= x"cc00";
when "11" & x"c2e" => DATA <= x"6338";
when "11" & x"c2f" => DATA <= x"2b00";
when "11" & x"c30" => DATA <= x"00ef";
when "11" & x"c31" => DATA <= x"0600";
when "11" & x"c32" => DATA <= x"0fa7";
when "11" & x"c33" => DATA <= x"9452";
when "11" & x"c34" => DATA <= x"a994";
when "11" & x"c35" => DATA <= x"e840";
when "11" & x"c36" => DATA <= x"2290";
when "11" & x"c37" => DATA <= x"2eaa";
when "11" & x"c38" => DATA <= x"7f23";
when "11" & x"c39" => DATA <= x"d3fb";
when "11" & x"c3a" => DATA <= x"fe9f";
when "11" & x"c3b" => DATA <= x"df0f";
when "11" & x"c3c" => DATA <= x"d010";
when "11" & x"c3d" => DATA <= x"2000";
when "11" & x"c3e" => DATA <= x"ffa0";
when "11" & x"c3f" => DATA <= x"077b";
when "11" & x"c40" => DATA <= x"ff80";
when "11" & x"c41" => DATA <= x"0074";
when "11" & x"c42" => DATA <= x"0001";
when "11" & x"c43" => DATA <= x"0798";
when "11" & x"c44" => DATA <= x"0013";
when "11" & x"c45" => DATA <= x"00fc";
when "11" & x"c46" => DATA <= x"4000";
when "11" & x"c47" => DATA <= x"00e5";
when "11" & x"c48" => DATA <= x"f9ff";
when "11" & x"c49" => DATA <= x"7dbc";
when "11" & x"c4a" => DATA <= x"0827";
when "11" & x"c4b" => DATA <= x"0418";
when "11" & x"c4c" => DATA <= x"edf7";
when "11" & x"c4d" => DATA <= x"ce20";
when "11" & x"c4e" => DATA <= x"1000";
when "11" & x"c4f" => DATA <= x"0400";
when "11" & x"c50" => DATA <= x"01f0";
when "11" & x"c51" => DATA <= x"0003";
when "11" & x"c52" => DATA <= x"beb9";
when "11" & x"c53" => DATA <= x"fbbe";
when "11" & x"c54" => DATA <= x"bfc6";
when "11" & x"c55" => DATA <= x"03e9";
when "11" & x"c56" => DATA <= x"be1f";
when "11" & x"c57" => DATA <= x"83f8";
when "11" & x"c58" => DATA <= x"01fe";
when "11" & x"c59" => DATA <= x"3f07";
when "11" & x"c5a" => DATA <= x"801c";
when "11" & x"c5b" => DATA <= x"1c00";
when "11" & x"c5c" => DATA <= x"ff30";
when "11" & x"c5d" => DATA <= x"3c1f";
when "11" & x"c5e" => DATA <= x"cff7";
when "11" & x"c5f" => DATA <= x"1109";
when "11" & x"c60" => DATA <= x"c0c0";
when "11" & x"c61" => DATA <= x"7057";
when "11" & x"c62" => DATA <= x"3b3f";
when "11" & x"c63" => DATA <= x"87c3";
when "11" & x"c64" => DATA <= x"c174";
when "11" & x"c65" => DATA <= x"f86c";
when "11" & x"c66" => DATA <= x"3f44";
when "11" & x"c67" => DATA <= x"a000";
when "11" & x"c68" => DATA <= x"2210";
when "11" & x"c69" => DATA <= x"02a5";
when "11" & x"c6a" => DATA <= x"a002";
when "11" & x"c6b" => DATA <= x"252a";
when "11" & x"c6c" => DATA <= x"37c0";
when "11" & x"c6d" => DATA <= x"0542";
when "11" & x"c6e" => DATA <= x"c1fb";
when "11" & x"c6f" => DATA <= x"bf8f";
when "11" & x"c70" => DATA <= x"67e7";
when "11" & x"c71" => DATA <= x"fbf4";
when "11" & x"c72" => DATA <= x"0008";
when "11" & x"c73" => DATA <= x"900a";
when "11" & x"c74" => DATA <= x"ff00";
when "11" & x"c75" => DATA <= x"0124";
when "11" & x"c76" => DATA <= x"02bf";
when "11" & x"c77" => DATA <= x"c001";
when "11" & x"c78" => DATA <= x"2900";
when "11" & x"c79" => DATA <= x"aff0";
when "11" & x"c7a" => DATA <= x"0026";
when "11" & x"c7b" => DATA <= x"402b";
when "11" & x"c7c" => DATA <= x"fc00";
when "11" & x"c7d" => DATA <= x"0490";
when "11" & x"c7e" => DATA <= x"0aff";
when "11" & x"c7f" => DATA <= x"0010";
when "11" & x"c80" => DATA <= x"2402";
when "11" & x"c81" => DATA <= x"bfc0";
when "11" & x"c82" => DATA <= x"0a09";
when "11" & x"c83" => DATA <= x"00af";
when "11" & x"c84" => DATA <= x"f002";
when "11" & x"c85" => DATA <= x"4240";
when "11" & x"c86" => DATA <= x"2bfc";
when "11" & x"c87" => DATA <= x"2018";
when "11" & x"c88" => DATA <= x"900a";
when "11" & x"c89" => DATA <= x"ff10";
when "11" & x"c8a" => DATA <= x"e805";
when "11" & x"c8b" => DATA <= x"7fd8";
when "11" & x"c8c" => DATA <= x"057f";
when "11" & x"c8d" => DATA <= x"8fc0";
when "11" & x"c8e" => DATA <= x"2001";
when "11" & x"c8f" => DATA <= x"fd00";
when "11" & x"c90" => DATA <= x"57fc";
when "11" & x"c91" => DATA <= x"8002";
when "11" & x"c92" => DATA <= x"0015";
when "11" & x"c93" => DATA <= x"ff20";
when "11" & x"c94" => DATA <= x"0040";
when "11" & x"c95" => DATA <= x"057f";
when "11" & x"c96" => DATA <= x"d805";
when "11" & x"c97" => DATA <= x"7f84";
when "11" & x"c98" => DATA <= x"3800";
when "11" & x"c99" => DATA <= x"2200";
when "11" & x"c9a" => DATA <= x"affb";
when "11" & x"c9b" => DATA <= x"00af";
when "11" & x"c9c" => DATA <= x"fb00";
when "11" & x"c9d" => DATA <= x"aff0";
when "11" & x"c9e" => DATA <= x"8680";
when "11" & x"c9f" => DATA <= x"07df";
when "11" & x"ca0" => DATA <= x"f600";
when "11" & x"ca1" => DATA <= x"167f";
when "11" & x"ca2" => DATA <= x"d803";
when "11" & x"ca3" => DATA <= x"e1fe";
when "11" & x"ca4" => DATA <= x"12d0";
when "11" & x"ca5" => DATA <= x"0aff";
when "11" & x"ca6" => DATA <= x"b00a";
when "11" & x"ca7" => DATA <= x"ffb0";
when "11" & x"ca8" => DATA <= x"07fb";
when "11" & x"ca9" => DATA <= x"dd01";
when "11" & x"caa" => DATA <= x"4001";
when "11" & x"cab" => DATA <= x"25c0";
when "11" & x"cac" => DATA <= x"02bf";
when "11" & x"cad" => DATA <= x"ec02";
when "11" & x"cae" => DATA <= x"bfde";
when "11" & x"caf" => DATA <= x"1400";
when "11" & x"cb0" => DATA <= x"8845";
when "11" & x"cb1" => DATA <= x"022b";
when "11" & x"cb2" => DATA <= x"fc03";
when "11" & x"cb3" => DATA <= x"4000";
when "11" & x"cb4" => DATA <= x"f038";
when "11" & x"cb5" => DATA <= x"018e";
when "11" & x"cb6" => DATA <= x"87b0";
when "11" & x"cb7" => DATA <= x"0aff";
when "11" & x"cb8" => DATA <= x"b00a";
when "11" & x"cb9" => DATA <= x"ffb0";
when "11" & x"cba" => DATA <= x"0aff";
when "11" & x"cbb" => DATA <= x"b00a";
when "11" & x"cbc" => DATA <= x"ffb0";
when "11" & x"cbd" => DATA <= x"07f3";
when "11" & x"cbe" => DATA <= x"fec0";
when "11" & x"cbf" => DATA <= x"0fef";
when "11" & x"cc0" => DATA <= x"f087";
when "11" & x"cc1" => DATA <= x"0004";
when "11" & x"cc2" => DATA <= x"000f";
when "11" & x"cc3" => DATA <= x"c7f8";
when "11" & x"cc4" => DATA <= x"4380";
when "11" & x"cc5" => DATA <= x"0220";
when "11" & x"cc6" => DATA <= x"079b";
when "11" & x"cc7" => DATA <= x"fec0";
when "11" & x"cc8" => DATA <= x"1cef";
when "11" & x"cc9" => DATA <= x"fb00";
when "11" & x"cca" => DATA <= x"affb";
when "11" & x"ccb" => DATA <= x"00af";
when "11" & x"ccc" => DATA <= x"fb00";
when "11" & x"ccd" => DATA <= x"aff0";
when "11" & x"cce" => DATA <= x"8700";
when "11" & x"ccf" => DATA <= x"1800";
when "11" & x"cd0" => DATA <= x"15ff";
when "11" & x"cd1" => DATA <= x"2001";
when "11" & x"cd2" => DATA <= x"f105";
when "11" & x"cd3" => DATA <= x"7f84";
when "11" & x"cd4" => DATA <= x"2400";
when "11" & x"cd5" => DATA <= x"083f";
when "11" & x"cd6" => DATA <= x"7f8f";
when "11" & x"cd7" => DATA <= x"b800";
when "11" & x"cd8" => DATA <= x"fe53";
when "11" & x"cd9" => DATA <= x"aff0";
when "11" & x"cda" => DATA <= x"1700";
when "11" & x"cdb" => DATA <= x"5011";
when "11" & x"cdc" => DATA <= x"7dff";
when "11" & x"cdd" => DATA <= x"c001";
when "11" & x"cde" => DATA <= x"0a00";
when "11" & x"cdf" => DATA <= x"7e3f";
when "11" & x"ce0" => DATA <= x"c09c";
when "11" & x"ce1" => DATA <= x"0020";
when "11" & x"ce2" => DATA <= x"0057";
when "11" & x"ce3" => DATA <= x"ff00";
when "11" & x"ce4" => DATA <= x"1000";
when "11" & x"ce5" => DATA <= x"4003";
when "11" & x"ce6" => DATA <= x"fbfe";
when "11" & x"ce7" => DATA <= x"4000";
when "11" & x"ce8" => DATA <= x"c00a";
when "11" & x"ce9" => DATA <= x"ffd0";
when "11" & x"cea" => DATA <= x"0405";
when "11" & x"ceb" => DATA <= x"7ff0";
when "11" & x"cec" => DATA <= x"0006";
when "11" & x"ced" => DATA <= x"802b";
when "11" & x"cee" => DATA <= x"fe40";
when "11" & x"cef" => DATA <= x"0200";
when "11" & x"cf0" => DATA <= x"0aff";
when "11" & x"cf1" => DATA <= x"0000";
when "11" & x"cf2" => DATA <= x"4000";
when "11" & x"cf3" => DATA <= x"8008";
when "11" & x"cf4" => DATA <= x"02bf";
when "11" & x"cf5" => DATA <= x"c000";
when "11" & x"cf6" => DATA <= x"1a00";
when "11" & x"cf7" => DATA <= x"0080";
when "11" & x"cf8" => DATA <= x"2bfe";
when "11" & x"cf9" => DATA <= x"400b";
when "11" & x"cfa" => DATA <= x"602a";
when "11" & x"cfb" => DATA <= x"ff90";
when "11" & x"cfc" => DATA <= x"0600";
when "11" & x"cfd" => DATA <= x"02bf";
when "11" & x"cfe" => DATA <= x"e820";
when "11" & x"cff" => DATA <= x"00b8";
when "11" & x"d00" => DATA <= x"0400";
when "11" & x"d01" => DATA <= x"2bfd";
when "11" & x"d02" => DATA <= x"fd5f";
when "11" & x"d03" => DATA <= x"0ff7";
when "11" & x"d04" => DATA <= x"43f2";
when "11" & x"d05" => DATA <= x"bfec";
when "11" & x"d06" => DATA <= x"fd7e";
when "11" & x"d07" => DATA <= x"3f06";
when "11" & x"d08" => DATA <= x"3110";
when "11" & x"d09" => DATA <= x"8c26";
when "11" & x"d0a" => DATA <= x"2001";
when "11" & x"d0b" => DATA <= x"8a00";
when "11" & x"d0c" => DATA <= x"043b";
when "11" & x"d0d" => DATA <= x"dcf5";
when "11" & x"d0e" => DATA <= x"ee00";
when "11" & x"d0f" => DATA <= x"73d0";
when "11" & x"d10" => DATA <= x"04bc";
when "11" & x"d11" => DATA <= x"800f";
when "11" & x"d12" => DATA <= x"2104";
when "11" & x"d13" => DATA <= x"5555";
when "11" & x"d14" => DATA <= x"2815";
when "11" & x"d15" => DATA <= x"4824";
when "11" & x"d16" => DATA <= x"0ba4";
when "11" & x"d17" => DATA <= x"8fef";
when "11" & x"d18" => DATA <= x"e027";
when "11" & x"d19" => DATA <= x"e1e1";
when "11" & x"d1a" => DATA <= x"f0c1";
when "11" & x"d1b" => DATA <= x"6280";
when "11" & x"d1c" => DATA <= x"0020";
when "11" & x"d1d" => DATA <= x"07fb";
when "11" & x"d1e" => DATA <= x"0000";
when "11" & x"d1f" => DATA <= x"077f";
when "11" & x"d20" => DATA <= x"bf09";
when "11" & x"d21" => DATA <= x"0e0a";
when "11" & x"d22" => DATA <= x"ff7e";
when "11" & x"d23" => DATA <= x"2000";
when "11" & x"d24" => DATA <= x"6010";
when "11" & x"d25" => DATA <= x"06ff";
when "11" & x"d26" => DATA <= x"bf18";
when "11" & x"d27" => DATA <= x"000f";
when "11" & x"d28" => DATA <= x"ff7c";
when "11" & x"d29" => DATA <= x"5008";
when "11" & x"d2a" => DATA <= x"475c";
when "11" & x"d2b" => DATA <= x"4001";
when "11" & x"d2c" => DATA <= x"0b00";
when "11" & x"d2d" => DATA <= x"fef7";
when "11" & x"d2e" => DATA <= x"7808";
when "11" & x"d2f" => DATA <= x"0002";
when "11" & x"d30" => DATA <= x"073f";
when "11" & x"d31" => DATA <= x"a8f9";
when "11" & x"d32" => DATA <= x"7dc0";
when "11" & x"d33" => DATA <= x"0fe7";
when "11" & x"d34" => DATA <= x"f843";
when "11" & x"d35" => DATA <= x"402b";
when "11" & x"d36" => DATA <= x"fc3b";
when "11" & x"d37" => DATA <= x"400e";
when "11" & x"d38" => DATA <= x"6003";
when "11" & x"d39" => DATA <= x"81da";
when "11" & x"d3a" => DATA <= x"ef7a";
when "11" & x"d3b" => DATA <= x"309c";
when "11" & x"d3c" => DATA <= x"09f9";
when "11" & x"d3d" => DATA <= x"1fef";
when "11" & x"d3e" => DATA <= x"f005";
when "11" & x"d3f" => DATA <= x"0094";
when "11" & x"d40" => DATA <= x"0e1d";
when "11" & x"d41" => DATA <= x"ffc0";
when "11" & x"d42" => DATA <= x"0a04";
when "11" & x"d43" => DATA <= x"057f";
when "11" & x"d44" => DATA <= x"bbdf";
when "11" & x"d45" => DATA <= x"0c00";
when "11" & x"d46" => DATA <= x"03e0";
when "11" & x"d47" => DATA <= x"015f";
when "11" & x"d48" => DATA <= x"ef77";
when "11" & x"d49" => DATA <= x"fbbc";
when "11" & x"d4a" => DATA <= x"147d";
when "11" & x"d4b" => DATA <= x"003f";
when "11" & x"d4c" => DATA <= x"d9ef";
when "11" & x"d4d" => DATA <= x"f6f8";
when "11" & x"d4e" => DATA <= x"9097";
when "11" & x"d4f" => DATA <= x"4015";
when "11" & x"d50" => DATA <= x"fefb";
when "11" & x"d51" => DATA <= x"7fd0";
when "11" & x"d52" => DATA <= x"0200";
when "11" & x"d53" => DATA <= x"015f";
when "11" & x"d54" => DATA <= x"ef74";
when "11" & x"d55" => DATA <= x"fd00";
when "11" & x"d56" => DATA <= x"2bc0";
when "11" & x"d57" => DATA <= x"0ff7";
when "11" & x"d58" => DATA <= x"ed7f";
when "11" & x"d59" => DATA <= x"8802";
when "11" & x"d5a" => DATA <= x"80f2";
when "11" & x"d5b" => DATA <= x"057f";
when "11" & x"d5c" => DATA <= x"bcc0";
when "11" & x"d5d" => DATA <= x"7201";
when "11" & x"d5e" => DATA <= x"5fef";
when "11" & x"d5f" => DATA <= x"d003";
when "11" & x"d60" => DATA <= x"0110";
when "11" & x"d61" => DATA <= x"4010";
when "11" & x"d62" => DATA <= x"57fb";
when "11" & x"d63" => DATA <= x"ec00";
when "11" & x"d64" => DATA <= x"7637";
when "11" & x"d65" => DATA <= x"3fc0";
when "11" & x"d66" => DATA <= x"15fe";
when "11" & x"d67" => DATA <= x"fd00";
when "11" & x"d68" => DATA <= x"1080";
when "11" & x"d69" => DATA <= x"81f0";
when "11" & x"d6a" => DATA <= x"03fd";
when "11" & x"d6b" => DATA <= x"eeff";
when "11" & x"d6c" => DATA <= x"0003";
when "11" & x"d6d" => DATA <= x"0034";
when "11" & x"d6e" => DATA <= x"015f";
when "11" & x"d6f" => DATA <= x"efee";
when "11" & x"d70" => DATA <= x"0052";
when "11" & x"d71" => DATA <= x"005f";
when "11" & x"d72" => DATA <= x"e7f7";
when "11" & x"d73" => DATA <= x"cb02";
when "11" & x"d74" => DATA <= x"801f";
when "11" & x"d75" => DATA <= x"c00a";
when "11" & x"d76" => DATA <= x"ff7f";
when "11" & x"d77" => DATA <= x"0dd6";
when "11" & x"d78" => DATA <= x"0040";
when "11" & x"d79" => DATA <= x"1842";
when "11" & x"d7a" => DATA <= x"bfcf";
when "11" & x"d7b" => DATA <= x"c007";
when "11" & x"d7c" => DATA <= x"9182";
when "11" & x"d7d" => DATA <= x"803b";
when "11" & x"d7e" => DATA <= x"fc02";
when "11" & x"d7f" => DATA <= x"6751";
when "11" & x"d80" => DATA <= x"b700";
when "11" & x"d81" => DATA <= x"15fe";
when "11" & x"d82" => DATA <= x"7f02";
when "11" & x"d83" => DATA <= x"09eb";
when "11" & x"d84" => DATA <= x"fc01";
when "11" & x"d85" => DATA <= x"dfe0";
when "11" & x"d86" => DATA <= x"0109";
when "11" & x"d87" => DATA <= x"fc0e";
when "11" & x"d88" => DATA <= x"007f";
when "11" & x"d89" => DATA <= x"bf57";
when "11" & x"d8a" => DATA <= x"e000";
when "11" & x"d8b" => DATA <= x"0afc";
when "11" & x"d8c" => DATA <= x"0001";
when "11" & x"d8d" => DATA <= x"eff7";
when "11" & x"d8e" => DATA <= x"c001";
when "11" & x"d8f" => DATA <= x"fefa";
when "11" & x"d90" => DATA <= x"003f";
when "11" & x"d91" => DATA <= x"dbef";
when "11" & x"d92" => DATA <= x"e018";
when "11" & x"d93" => DATA <= x"006e";
when "11" & x"d94" => DATA <= x"ff00";
when "11" & x"d95" => DATA <= x"57fa";
when "11" & x"d96" => DATA <= x"fcd8";
when "11" & x"d97" => DATA <= x"d409";
when "11" & x"d98" => DATA <= x"5005";
when "11" & x"d99" => DATA <= x"7fb7";
when "11" & x"d9a" => DATA <= x"df2b";
when "11" & x"d9b" => DATA <= x"f495";
when "11" & x"d9c" => DATA <= x"0057";
when "11" & x"d9d" => DATA <= x"f9fd";
when "11" & x"d9e" => DATA <= x"fefb";
when "11" & x"d9f" => DATA <= x"2e39";
when "11" & x"da0" => DATA <= x"0015";
when "11" & x"da1" => DATA <= x"fedf";
when "11" & x"da2" => DATA <= x"7f8b";
when "11" & x"da3" => DATA <= x"c84f";
when "11" & x"da4" => DATA <= x"f003";
when "11" & x"da5" => DATA <= x"fcff";
when "11" & x"da6" => DATA <= x"5fe4";
when "11" & x"da7" => DATA <= x"2048";
when "11" & x"da8" => DATA <= x"0c01";
when "11" & x"da9" => DATA <= x"5fee";
when "11" & x"daa" => DATA <= x"e7fc";
when "11" & x"dab" => DATA <= x"e07f";
when "11" & x"dac" => DATA <= x"fcff";
when "11" & x"dad" => DATA <= x"f43b";
when "11" & x"dae" => DATA <= x"1e61";
when "11" & x"daf" => DATA <= x"ffff";
when "11" & x"db0" => DATA <= x"bffb";
when "11" & x"db1" => DATA <= x"cfb8";
when "11" & x"db2" => DATA <= x"ebfc";
when "11" & x"db3" => DATA <= x"6bff";
when "11" & x"db4" => DATA <= x"e007";
when "11" & x"db5" => DATA <= x"38ff";
when "11" & x"db6" => DATA <= x"7fc0";
when "11" & x"db7" => DATA <= x"0782";
when "11" & x"db8" => DATA <= x"057f";
when "11" & x"db9" => DATA <= x"bdeb";
when "11" & x"dba" => DATA <= x"fc42";
when "11" & x"dbb" => DATA <= x"fe00";
when "11" & x"dbc" => DATA <= x"57fb";
when "11" & x"dbd" => DATA <= x"eebf";
when "11" & x"dbe" => DATA <= x"d483";
when "11" & x"dbf" => DATA <= x"f003";
when "11" & x"dc0" => DATA <= x"fdcf";
when "11" & x"dc1" => DATA <= x"dfe0";
when "11" & x"dc2" => DATA <= x"b7f8";
when "11" & x"dc3" => DATA <= x"12bf";
when "11" & x"dc4" => DATA <= x"dfb5";
when "11" & x"dc5" => DATA <= x"fe00";
when "11" & x"dc6" => DATA <= x"6780";
when "11" & x"dc7" => DATA <= x"2bfd";
when "11" & x"dc8" => DATA <= x"f75f";
when "11" & x"dc9" => DATA <= x"e007";
when "11" & x"dca" => DATA <= x"f803";
when "11" & x"dcb" => DATA <= x"7fc0";
when "11" & x"dcc" => DATA <= x"0270";
when "11" & x"dcd" => DATA <= x"057f";
when "11" & x"dce" => DATA <= x"bf7b";
when "11" & x"dcf" => DATA <= x"fdce";
when "11" & x"dd0" => DATA <= x"00af";
when "11" & x"dd1" => DATA <= x"f7f5";
when "11" & x"dd2" => DATA <= x"7faf";
when "11" & x"dd3" => DATA <= x"d3c1";
when "11" & x"dd4" => DATA <= x"0aff";
when "11" & x"dd5" => DATA <= x"7ecf";
when "11" & x"dd6" => DATA <= x"f802";
when "11" & x"dd7" => DATA <= x"bfdf";
when "11" & x"dd8" => DATA <= x"ddfe";
when "11" & x"dd9" => DATA <= x"0f00";
when "11" & x"dda" => DATA <= x"3fdf";
when "11" & x"ddb" => DATA <= x"27fe";
when "11" & x"ddc" => DATA <= x"ff20";
when "11" & x"ddd" => DATA <= x"382f";
when "11" & x"dde" => DATA <= x"fdf0";
when "11" & x"ddf" => DATA <= x"f0ff";
when "11" & x"de0" => DATA <= x"ffff";
when "11" & x"de1" => DATA <= x"fff1";
when "11" & x"de2" => DATA <= x"fafe";
when "11" & x"de3" => DATA <= x"ffcb";
when "11" & x"de4" => DATA <= x"200b";
when "11" & x"de5" => DATA <= x"ff01";
when "11" & x"de6" => DATA <= x"803b";
when "11" & x"de7" => DATA <= x"fc01";
when "11" & x"de8" => DATA <= x"5fef";
when "11" & x"de9" => DATA <= x"c707";
when "11" & x"dea" => DATA <= x"7f80";
when "11" & x"deb" => DATA <= x"2bfc";
when "11" & x"dec" => DATA <= x"fb3f";
when "11" & x"ded" => DATA <= x"e01a";
when "11" & x"dee" => DATA <= x"ff01";
when "11" & x"def" => DATA <= x"1feb";
when "11" & x"df0" => DATA <= x"fdf6";
when "11" & x"df1" => DATA <= x"04af";
when "11" & x"df2" => DATA <= x"fa00";
when "11" & x"df3" => DATA <= x"aff6";
when "11" & x"df4" => DATA <= x"6831";
when "11" & x"df5" => DATA <= x"fefe";
when "11" & x"df6" => DATA <= x"1077";
when "11" & x"df7" => DATA <= x"fbdc";
when "11" & x"df8" => DATA <= x"015f";
when "11" & x"df9" => DATA <= x"e7d9";
when "11" & x"dfa" => DATA <= x"ff00";
when "11" & x"dfb" => DATA <= x"57fb";
when "11" & x"dfc" => DATA <= x"91c3";
when "11" & x"dfd" => DATA <= x"dfe0";
when "11" & x"dfe" => DATA <= x"0eff";
when "11" & x"dff" => DATA <= x"03f7";
when "11" & x"e00" => DATA <= x"f902";
when "11" & x"e01" => DATA <= x"afc7";
when "11" & x"e02" => DATA <= x"f3ff";
when "11" & x"e03" => DATA <= x"c00f";
when "11" & x"e04" => DATA <= x"6787";
when "11" & x"e05" => DATA <= x"7fa0";
when "11" & x"e06" => DATA <= x"1f00";
when "11" & x"e07" => DATA <= x"04b9";
when "11" & x"e08" => DATA <= x"57bf";
when "11" & x"e09" => DATA <= x"c000";
when "11" & x"e0a" => DATA <= x"3000";
when "11" & x"e0b" => DATA <= x"183c";
when "11" & x"e0c" => DATA <= x"ff7b";
when "11" & x"e0d" => DATA <= x"bf40";
when "11" & x"e0e" => DATA <= x"0a94";
when "11" & x"e0f" => DATA <= x"6a01";
when "11" & x"e10" => DATA <= x"047f";
when "11" & x"e11" => DATA <= x"7fbd";
when "11" & x"e12" => DATA <= x"80da";
when "11" & x"e13" => DATA <= x"fe7e";
when "11" & x"e14" => DATA <= x"7dd0";
when "11" & x"e15" => DATA <= x"0180";
when "11" & x"e16" => DATA <= x"0840";
when "11" & x"e17" => DATA <= x"0200";
when "11" & x"e18" => DATA <= x"002f";
when "11" & x"e19" => DATA <= x"f025";
when "11" & x"e1a" => DATA <= x"0001";
when "11" & x"e1b" => DATA <= x"2801";
when "11" & x"e1c" => DATA <= x"803f";
when "11" & x"e1d" => DATA <= x"a800";
when "11" & x"e1e" => DATA <= x"0200";
when "11" & x"e1f" => DATA <= x"0040";
when "11" & x"e20" => DATA <= x"2110";
when "11" & x"e21" => DATA <= x"00e0";
when "11" & x"e22" => DATA <= x"f9ff";
when "11" & x"e23" => DATA <= x"afe7";
when "11" & x"e24" => DATA <= x"0000";
when "11" & x"e25" => DATA <= x"c003";
when "11" & x"e26" => DATA <= x"3df7";
when "11" & x"e27" => DATA <= x"f9c4";
when "11" & x"e28" => DATA <= x"c200";
when "11" & x"e29" => DATA <= x"0080";
when "11" & x"e2a" => DATA <= x"3807";
when "11" & x"e2b" => DATA <= x"c003";
when "11" & x"e2c" => DATA <= x"8efb";
when "11" & x"e2d" => DATA <= x"ff77";
when "11" & x"e2e" => DATA <= x"afaa";
when "11" & x"e2f" => DATA <= x"ff8f";
when "11" & x"e30" => DATA <= x"80c3";
when "11" & x"e31" => DATA <= x"27f8";
when "11" & x"e32" => DATA <= x"7c4e";
when "11" & x"e33" => DATA <= x"0060";
when "11" & x"e34" => DATA <= x"7005";
when "11" & x"e35" => DATA <= x"3e3e";
when "11" & x"e36" => DATA <= x"2bfc";
when "11" & x"e37" => DATA <= x"0150";
when "11" & x"e38" => DATA <= x"0c07";
when "11" & x"e39" => DATA <= x"038d";
when "11" & x"e3a" => DATA <= x"cedf";
when "11" & x"e3b" => DATA <= x"6391";
when "11" & x"e3c" => DATA <= x"dfe1";
when "11" & x"e3d" => DATA <= x"f0ba";
when "11" & x"e3e" => DATA <= x"7f87";
when "11" & x"e3f" => DATA <= x"c1cf";
when "11" & x"e40" => DATA <= x"f780";
when "11" & x"e41" => DATA <= x"0807";
when "11" & x"e42" => DATA <= x"4054";
when "11" & x"e43" => DATA <= x"0027";
when "11" & x"e44" => DATA <= x"0080";
when "11" & x"e45" => DATA <= x"0020";
when "11" & x"e46" => DATA <= x"0008";
when "11" & x"e47" => DATA <= x"0280";
when "11" & x"e48" => DATA <= x"4015";
when "11" & x"e49" => DATA <= x"fc1e";
when "11" & x"e4a" => DATA <= x"a06a";
when "11" & x"e4b" => DATA <= x"80a0";
when "11" & x"e4c" => DATA <= x"03c0";
when "11" & x"e4d" => DATA <= x"e0f8";
when "11" & x"e4e" => DATA <= x"7e3f";
when "11" & x"e4f" => DATA <= x"bfd0";
when "11" & x"e50" => DATA <= x"004d";
when "11" & x"e51" => DATA <= x"001b";
when "11" & x"e52" => DATA <= x"8000";
when "11" & x"e53" => DATA <= x"5a00";
when "11" & x"e54" => DATA <= x"1200";
when "11" & x"e55" => DATA <= x"3003";
when "11" & x"e56" => DATA <= x"e030";
when "11" & x"e57" => DATA <= x"0b05";
when "11" & x"e58" => DATA <= x"e070";
when "11" & x"e59" => DATA <= x"0007";
when "11" & x"e5a" => DATA <= x"e87b";
when "11" & x"e5b" => DATA <= x"87c0";
when "11" & x"e5c" => DATA <= x"1480";
when "11" & x"e5d" => DATA <= x"4800";
when "11" & x"e5e" => DATA <= x"7201";
when "11" & x"e5f" => DATA <= x"2001";
when "11" & x"e60" => DATA <= x"b01c";
when "11" & x"e61" => DATA <= x"003f";
when "11" & x"e62" => DATA <= x"0780";
when "11" & x"e63" => DATA <= x"d02c";
when "11" & x"e64" => DATA <= x"1ae0";
when "11" & x"e65" => DATA <= x"a00d";
when "11" & x"e66" => DATA <= x"1f7f";
when "11" & x"e67" => DATA <= x"8828";
when "11" & x"e68" => DATA <= x"0101";
when "11" & x"e69" => DATA <= x"c008";
when "11" & x"e6a" => DATA <= x"da00";
when "11" & x"e6b" => DATA <= x"9c02";
when "11" & x"e6c" => DATA <= x"00f8";
when "11" & x"e6d" => DATA <= x"00f0";
when "11" & x"e6e" => DATA <= x"61a0";
when "11" & x"e6f" => DATA <= x"180e";
when "11" & x"e70" => DATA <= x"0780";
when "11" & x"e71" => DATA <= x"4001";
when "11" & x"e72" => DATA <= x"60e0";
when "11" & x"e73" => DATA <= x"0e10";
when "11" & x"e74" => DATA <= x"0048";
when "11" & x"e75" => DATA <= x"8001";
when "11" & x"e76" => DATA <= x"c060";
when "11" & x"e77" => DATA <= x"a203";
when "11" & x"e78" => DATA <= x"0082";
when "11" & x"e79" => DATA <= x"8002";
when "11" & x"e7a" => DATA <= x"0f0a";
when "11" & x"e7b" => DATA <= x"e0ef";
when "11" & x"e7c" => DATA <= x"0001";
when "11" & x"e7d" => DATA <= x"000e";
when "11" & x"e7e" => DATA <= x"47e0";
when "11" & x"e7f" => DATA <= x"73f8";
when "11" & x"e80" => DATA <= x"22c0";
when "11" & x"e81" => DATA <= x"0c60";
when "11" & x"e82" => DATA <= x"0009";
when "11" & x"e83" => DATA <= x"c29c";
when "11" & x"e84" => DATA <= x"6bc0";
when "11" & x"e85" => DATA <= x"7e00";
when "11" & x"e86" => DATA <= x"7c3c";
when "11" & x"e87" => DATA <= x"2b81";
when "11" & x"e88" => DATA <= x"e0e0";
when "11" & x"e89" => DATA <= x"a00d";
when "11" & x"e8a" => DATA <= x"0300";
when "11" & x"e8b" => DATA <= x"8000";
when "11" & x"e8c" => DATA <= x"8440";
when "11" & x"e8d" => DATA <= x"2002";
when "11" & x"e8e" => DATA <= x"4100";
when "11" & x"e8f" => DATA <= x"0b8e";
when "11" & x"e90" => DATA <= x"181c";
when "11" & x"e91" => DATA <= x"1e28";
when "11" & x"e92" => DATA <= x"000e";
when "11" & x"e93" => DATA <= x"fc7c";
when "11" & x"e94" => DATA <= x"7783";
when "11" & x"e95" => DATA <= x"8280";
when "11" & x"e96" => DATA <= x"3405";
when "11" & x"e97" => DATA <= x"bf5c";
when "11" & x"e98" => DATA <= x"460a";
when "11" & x"e99" => DATA <= x"e270";
when "11" & x"e9a" => DATA <= x"3000";
when "11" & x"e9b" => DATA <= x"15fe";
when "11" & x"e9c" => DATA <= x"f870";
when "11" & x"e9d" => DATA <= x"3010";
when "11" & x"e9e" => DATA <= x"2830";
when "11" & x"e9f" => DATA <= x"17c3";
when "11" & x"ea0" => DATA <= x"a03f";
when "11" & x"ea1" => DATA <= x"fdff";
when "11" & x"ea2" => DATA <= x"fc60";
when "11" & x"ea3" => DATA <= x"3aff";
when "11" & x"ea4" => DATA <= x"70a0";
when "11" & x"ea5" => DATA <= x"4060";
when "11" & x"ea6" => DATA <= x"7078";
when "11" & x"ea7" => DATA <= x"188e";
when "11" & x"ea8" => DATA <= x"0723";
when "11" & x"ea9" => DATA <= x"81e9";
when "11" & x"eaa" => DATA <= x"1c8c";
when "11" & x"eab" => DATA <= x"40a0";
when "11" & x"eac" => DATA <= x"0010";
when "11" & x"ead" => DATA <= x"0005";
when "11" & x"eae" => DATA <= x"4000";
when "11" & x"eaf" => DATA <= x"2001";
when "11" & x"eb0" => DATA <= x"fd8e";
when "11" & x"eb1" => DATA <= x"071b";
when "11" & x"eb2" => DATA <= x"83c7";
when "11" & x"eb3" => DATA <= x"e40a";
when "11" & x"eb4" => DATA <= x"000f";
when "11" & x"eb5" => DATA <= x"87a8";
when "11" & x"eb6" => DATA <= x"7030";
when "11" & x"eb7" => DATA <= x"f030";
when "11" & x"eb8" => DATA <= x"5800";
when "11" & x"eb9" => DATA <= x"2d20";
when "11" & x"eba" => DATA <= x"0440";
when "11" & x"ebb" => DATA <= x"5425";
when "11" & x"ebc" => DATA <= x"403f";
when "11" & x"ebd" => DATA <= x"400e";
when "11" & x"ebe" => DATA <= x"070d";
when "11" & x"ebf" => DATA <= x"0183";
when "11" & x"ec0" => DATA <= x"e8fc";
when "11" & x"ec1" => DATA <= x"11c1";
when "11" & x"ec2" => DATA <= x"e0e0";
when "11" & x"ec3" => DATA <= x"6020";
when "11" & x"ec4" => DATA <= x"0030";
when "11" & x"ec5" => DATA <= x"082c";
when "11" & x"ec6" => DATA <= x"000b";
when "11" & x"ec7" => DATA <= x"4080";
when "11" & x"ec8" => DATA <= x"c168";
when "11" & x"ec9" => DATA <= x"0060";
when "11" & x"eca" => DATA <= x"0008";
when "11" & x"ecb" => DATA <= x"1d81";
when "11" & x"ecc" => DATA <= x"4001";
when "11" & x"ecd" => DATA <= x"f7c3";
when "11" & x"ece" => DATA <= x"0002";
when "11" & x"ecf" => DATA <= x"070f";
when "11" & x"ed0" => DATA <= x"f004";
when "11" & x"ed1" => DATA <= x"8381";
when "11" & x"ed2" => DATA <= x"1f8f";
when "11" & x"ed3" => DATA <= x"8080";
when "11" & x"ed4" => DATA <= x"0284";
when "11" & x"ed5" => DATA <= x"2800";
when "11" & x"ed6" => DATA <= x"04ff";
when "11" & x"ed7" => DATA <= x"0030";
when "11" & x"ed8" => DATA <= x"c0e0";
when "11" & x"ed9" => DATA <= x"f3ff";
when "11" & x"eda" => DATA <= x"7f80";
when "11" & x"edb" => DATA <= x"07ef";
when "11" & x"edc" => DATA <= x"c783";
when "11" & x"edd" => DATA <= x"8002";
when "11" & x"ede" => DATA <= x"037f";
when "11" & x"edf" => DATA <= x"8018";
when "11" & x"ee0" => DATA <= x"1dff";
when "11" & x"ee1" => DATA <= x"580f";
when "11" & x"ee2" => DATA <= x"f003";
when "11" & x"ee3" => DATA <= x"c102";
when "11" & x"ee4" => DATA <= x"0307";
when "11" & x"ee5" => DATA <= x"9fdf";
when "11" & x"ee6" => DATA <= x"e7f4";
when "11" & x"ee7" => DATA <= x"001c";
when "11" & x"ee8" => DATA <= x"1e0e";
when "11" & x"ee9" => DATA <= x"4670";
when "11" & x"eea" => DATA <= x"0028";
when "11" & x"eeb" => DATA <= x"0080";
when "11" & x"eec" => DATA <= x"9000";
when "11" & x"eed" => DATA <= x"8001";
when "11" & x"eee" => DATA <= x"301f";
when "11" & x"eef" => DATA <= x"1fbf";
when "11" & x"ef0" => DATA <= x"df00";
when "11" & x"ef1" => DATA <= x"0603";
when "11" & x"ef2" => DATA <= x"f1fe";
when "11" & x"ef3" => DATA <= x"f060";
when "11" & x"ef4" => DATA <= x"2001";
when "11" & x"ef5" => DATA <= x"e1c0";
when "11" & x"ef6" => DATA <= x"0004";
when "11" & x"ef7" => DATA <= x"23c0";
when "11" & x"ef8" => DATA <= x"2006";
when "11" & x"ef9" => DATA <= x"e022";
when "11" & x"efa" => DATA <= x"8324";
when "11" & x"efb" => DATA <= x"0147";
when "11" & x"efc" => DATA <= x"5800";
when "11" & x"efd" => DATA <= x"2607";
when "11" & x"efe" => DATA <= x"613f";
when "11" & x"eff" => DATA <= x"8020";
when "11" & x"f00" => DATA <= x"f7c2";
when "11" & x"f01" => DATA <= x"0002";
when "11" & x"f02" => DATA <= x"1f3f";
when "11" & x"f03" => DATA <= x"87c0";
when "11" & x"f04" => DATA <= x"4000";
when "11" & x"f05" => DATA <= x"39fc";
when "11" & x"f06" => DATA <= x"fc78";
when "11" & x"f07" => DATA <= x"a005";
when "11" & x"f08" => DATA <= x"0043";
when "11" & x"f09" => DATA <= x"8002";
when "11" & x"f0a" => DATA <= x"1c00";
when "11" & x"f0b" => DATA <= x"0500";
when "11" & x"f0c" => DATA <= x"7605";
when "11" & x"f0d" => DATA <= x"0002";
when "11" & x"f0e" => DATA <= x"000c";
when "11" & x"f0f" => DATA <= x"4078";
when "11" & x"f10" => DATA <= x"fdfe";
when "11" & x"f11" => DATA <= x"fc00";
when "11" & x"f12" => DATA <= x"1c1f";
when "11" & x"f13" => DATA <= x"cff7";
when "11" & x"f14" => DATA <= x"8300";
when "11" & x"f15" => DATA <= x"021f";
when "11" & x"f16" => DATA <= x"1f50";
when "11" & x"f17" => DATA <= x"0022";
when "11" & x"f18" => DATA <= x"4010";
when "11" & x"f19" => DATA <= x"000a";
when "11" & x"f1a" => DATA <= x"0690";
when "11" & x"f1b" => DATA <= x"0285";
when "11" & x"f1c" => DATA <= x"0020";
when "11" & x"f1d" => DATA <= x"4006";
when "11" & x"f1e" => DATA <= x"170b";
when "11" & x"f1f" => DATA <= x"c5ff";
when "11" & x"f20" => DATA <= x"400f";
when "11" & x"f21" => DATA <= x"f600";
when "11" & x"f22" => DATA <= x"007e";
when "11" & x"f23" => DATA <= x"ff03";
when "11" & x"f24" => DATA <= x"d000";
when "11" & x"f25" => DATA <= x"0c3e";
when "11" & x"f26" => DATA <= x"fe70";
when "11" & x"f27" => DATA <= x"0040";
when "11" & x"f28" => DATA <= x"0403";
when "11" & x"f29" => DATA <= x"83c1";
when "11" & x"f2a" => DATA <= x"fd5f";
when "11" & x"f2b" => DATA <= x"f501";
when "11" & x"f2c" => DATA <= x"ffff";
when "11" & x"f2d" => DATA <= x"ff5f";
when "11" & x"f2e" => DATA <= x"fee2";
when "11" & x"f2f" => DATA <= x"710e";
when "11" & x"f30" => DATA <= x"7804";
when "11" & x"f31" => DATA <= x"f7d7";
when "11" & x"f32" => DATA <= x"fd00";
when "11" & x"f33" => DATA <= x"2f1f";
when "11" & x"f34" => DATA <= x"d3fe";
when "11" & x"f35" => DATA <= x"0060";
when "11" & x"f36" => DATA <= x"5ff8";
when "11" & x"f37" => DATA <= x"03ff";
when "11" & x"f38" => DATA <= x"c01f";
when "11" & x"f39" => DATA <= x"fe00";
when "11" & x"f3a" => DATA <= x"0fdf";
when "11" & x"f3b" => DATA <= x"fd00";
when "11" & x"f3c" => DATA <= x"36f7";
when "11" & x"f3d" => DATA <= x"fe80";
when "11" & x"f3e" => DATA <= x"0042";
when "11" & x"f3f" => DATA <= x"11ff";
when "11" & x"f40" => DATA <= x"7fd0";
when "11" & x"f41" => DATA <= x"03c1";
when "11" & x"f42" => DATA <= x"f0fe";
when "11" & x"f43" => DATA <= x"effa";
when "11" & x"f44" => DATA <= x"00bf";
when "11" & x"f45" => DATA <= x"fa00";
when "11" & x"f46" => DATA <= x"bffa";
when "11" & x"f47" => DATA <= x"0002";
when "11" & x"f48" => DATA <= x"9ce7";
when "11" & x"f49" => DATA <= x"fe80";
when "11" & x"f4a" => DATA <= x"1f0f";
when "11" & x"f4b" => DATA <= x"e9ff";
when "11" & x"f4c" => DATA <= x"003f";
when "11" & x"f4d" => DATA <= x"2ffc";
when "11" & x"f4e" => DATA <= x"0001";
when "11" & x"f4f" => DATA <= x"5ad7";
when "11" & x"f50" => DATA <= x"f9fc";
when "11" & x"f51" => DATA <= x"7ec7";
when "11" & x"f52" => DATA <= x"a000";
when "11" & x"f53" => DATA <= x"1004";
when "11" & x"f54" => DATA <= x"0084";
when "11" & x"f55" => DATA <= x"61bc";
when "11" & x"f56" => DATA <= x"4008";
when "11" & x"f57" => DATA <= x"07c3";
when "11" & x"f58" => DATA <= x"fa7f";
when "11" & x"f59" => DATA <= x"c01f";
when "11" & x"f5a" => DATA <= x"fe00";
when "11" & x"f5b" => DATA <= x"07df";
when "11" & x"f5c" => DATA <= x"fd00";
when "11" & x"f5d" => DATA <= x"07db";
when "11" & x"f5e" => DATA <= x"f3ff";
when "11" & x"f5f" => DATA <= x"400f";
when "11" & x"f60" => DATA <= x"07cc";
when "11" & x"f61" => DATA <= x"ffd0";
when "11" & x"f62" => DATA <= x"01ff";
when "11" & x"f63" => DATA <= x"7fc0";
when "11" & x"f64" => DATA <= x"0ff3";
when "11" & x"f65" => DATA <= x"6eff";
when "11" & x"f66" => DATA <= x"8000";
when "11" & x"f67" => DATA <= x"20d4";
when "11" & x"f68" => DATA <= x"7b3f";
when "11" & x"f69" => DATA <= x"bfe8";
when "11" & x"f6a" => DATA <= x"01e0";
when "11" & x"f6b" => DATA <= x"f17d";
when "11" & x"f6c" => DATA <= x"bf6b";
when "11" & x"f6d" => DATA <= x"fe80";
when "11" & x"f6e" => DATA <= x"2ffc";
when "11" & x"f6f" => DATA <= x"00f0";
when "11" & x"f70" => DATA <= x"bff0";
when "11" & x"f71" => DATA <= x"007c";
when "11" & x"f72" => DATA <= x"7fcf";
when "11" & x"f73" => DATA <= x"f5ff";
when "11" & x"f74" => DATA <= x"400e";
when "11" & x"f75" => DATA <= x"0733";
when "11" & x"f76" => DATA <= x"1ddf";
when "11" & x"f77" => DATA <= x"5ff4";
when "11" & x"f78" => DATA <= x"005f";
when "11" & x"f79" => DATA <= x"dffa";
when "11" & x"f7a" => DATA <= x"002d";
when "11" & x"f7b" => DATA <= x"6ff8";
when "11" & x"f7c" => DATA <= x"001f";
when "11" & x"f7d" => DATA <= x"47e7";
when "11" & x"f7e" => DATA <= x"feff";
when "11" & x"f7f" => DATA <= x"a007";
when "11" & x"f80" => DATA <= x"038a";
when "11" & x"f81" => DATA <= x"bdeb";
when "11" & x"f82" => DATA <= x"fe80";
when "11" & x"f83" => DATA <= x"2ffc";
when "11" & x"f84" => DATA <= x"00e0";
when "11" & x"f85" => DATA <= x"77ef";
when "11" & x"f86" => DATA <= x"f802";
when "11" & x"f87" => DATA <= x"80c0";
when "11" & x"f88" => DATA <= x"2311";
when "11" & x"f89" => DATA <= x"99cc";
when "11" & x"f8a" => DATA <= x"ff40";
when "11" & x"f8b" => DATA <= x"0efa";
when "11" & x"f8c" => DATA <= x"feef";
when "11" & x"f8d" => DATA <= x"fa00";
when "11" & x"f8e" => DATA <= x"bff0";
when "11" & x"f8f" => DATA <= x"03f9";
when "11" & x"f90" => DATA <= x"dfbf";
when "11" & x"f91" => DATA <= x"f401";
when "11" & x"f92" => DATA <= x"4063";
when "11" & x"f93" => DATA <= x"31da";
when "11" & x"f94" => DATA <= x"edff";
when "11" & x"f95" => DATA <= x"400e";
when "11" & x"f96" => DATA <= x"e7e3";
when "11" & x"f97" => DATA <= x"fbbf";
when "11" & x"f98" => DATA <= x"c008";
when "11" & x"f99" => DATA <= x"07ae";
when "11" & x"f9a" => DATA <= x"ff80";
when "11" & x"f9b" => DATA <= x"1fe7";
when "11" & x"f9c" => DATA <= x"fa3f";
when "11" & x"f9d" => DATA <= x"0f8f";
when "11" & x"f9e" => DATA <= x"c3f4";
when "11" & x"f9f" => DATA <= x"00f0";
when "11" & x"fa0" => DATA <= x"9e06";
when "11" & x"fa1" => DATA <= x"1d00";
when "11" & x"fa2" => DATA <= x"5ff8";
when "11" & x"fa3" => DATA <= x"01f1";
when "11" & x"fa4" => DATA <= x"7fe0";
when "11" & x"fa5" => DATA <= x"07ff";
when "11" & x"fa6" => DATA <= x"1ff0";
when "11" & x"fa7" => DATA <= x"fd00";
when "11" & x"fa8" => DATA <= x"1c3b";
when "11" & x"fa9" => DATA <= x"c1e2";
when "11" & x"faa" => DATA <= x"f0a0";
when "11" & x"fab" => DATA <= x"03de";
when "11" & x"fac" => DATA <= x"ff80";
when "11" & x"fad" => DATA <= x"1fef";
when "11" & x"fae" => DATA <= x"bdff";
when "11" & x"faf" => DATA <= x"003f";
when "11" & x"fb0" => DATA <= x"c1f4";
when "11" & x"fb1" => DATA <= x"3fc1";
when "11" & x"fb2" => DATA <= x"e000";
when "11" & x"fb3" => DATA <= x"0d7c";
when "11" & x"fb4" => DATA <= x"7783";
when "11" & x"fb5" => DATA <= x"8680";
when "11" & x"fb6" => DATA <= x"2ffc";
when "11" & x"fb7" => DATA <= x"00fe";
when "11" & x"fb8" => DATA <= x"bff0";
when "11" & x"fb9" => DATA <= x"03fc";
when "11" & x"fba" => DATA <= x"0740";
when "11" & x"fbb" => DATA <= x"fc1e";
when "11" & x"fbc" => DATA <= x"0001";
when "11" & x"fbd" => DATA <= x"bfeb";
when "11" & x"fbe" => DATA <= x"f9f8";
when "11" & x"fbf" => DATA <= x"f878";
when "11" & x"fc0" => DATA <= x"5005";
when "11" & x"fc1" => DATA <= x"ff80";
when "11" & x"fc2" => DATA <= x"1fec";
when "11" & x"fc3" => DATA <= x"040d";
when "11" & x"fc4" => DATA <= x"01d0";
when "11" & x"fc5" => DATA <= x"3800";
when "11" & x"fc6" => DATA <= x"03df";
when "11" & x"fc7" => DATA <= x"efe7";
when "11" & x"fc8" => DATA <= x"e3e0";
when "11" & x"fc9" => DATA <= x"0080";
when "11" & x"fca" => DATA <= x"bff0";
when "11" & x"fcb" => DATA <= x"03fe";
when "11" & x"fcc" => DATA <= x"8fcf";
when "11" & x"fcd" => DATA <= x"fdfe";
when "11" & x"fce" => DATA <= x"007f";
when "11" & x"fcf" => DATA <= x"be1e";
when "11" & x"fd0" => DATA <= x"0e06";
when "11" & x"fd1" => DATA <= x"0200";
when "11" & x"fd2" => DATA <= x"0340";
when "11" & x"fd3" => DATA <= x"1bfe";
when "11" & x"fd4" => DATA <= x"fe00";
when "11" & x"fd5" => DATA <= x"382f";
when "11" & x"fd6" => DATA <= x"fc01";
when "11" & x"fd7" => DATA <= x"ffe0";
when "11" & x"fd8" => DATA <= x"07f8";
when "11" & x"fd9" => DATA <= x"0c0f";
when "11" & x"fda" => DATA <= x"41f4";
when "11" & x"fdb" => DATA <= x"7e00";
when "11" & x"fdc" => DATA <= x"1fbf";
when "11" & x"fdd" => DATA <= x"dfcf";
when "11" & x"fde" => DATA <= x"c783";
when "11" & x"fdf" => DATA <= x"8189";
when "11" & x"fe0" => DATA <= x"4017";
when "11" & x"fe1" => DATA <= x"fe00";
when "11" & x"fe2" => DATA <= x"785f";
when "11" & x"fe3" => DATA <= x"f803";
when "11" & x"fe4" => DATA <= x"ffc0";
when "11" & x"fe5" => DATA <= x"0ff6";
when "11" & x"fe6" => DATA <= x"0004";
when "11" & x"fe7" => DATA <= x"060f";
when "11" & x"fe8" => DATA <= x"0f8f";
when "11" & x"fe9" => DATA <= x"c01d";
when "11" & x"fea" => DATA <= x"fefe";
when "11" & x"feb" => DATA <= x"7c3c";
when "11" & x"fec" => DATA <= x"5800";
when "11" & x"fed" => DATA <= x"07f5";
when "11" & x"fee" => DATA <= x"ff80";
when "11" & x"fef" => DATA <= x"3ffc";
when "11" & x"ff0" => DATA <= x"00ff";
when "11" & x"ff1" => DATA <= x"1fef";
when "11" & x"ff2" => DATA <= x"f801";
when "11" & x"ff3" => DATA <= x"fee0";
when "11" & x"ff4" => DATA <= x"0000";
when "11" & x"ff5" => DATA <= x"c1e7";
when "11" & x"ff6" => DATA <= x"f7f8";
when "11" & x"ff7" => DATA <= x"03bf";
when "11" & x"ff8" => DATA <= x"df8e";
when "11" & x"ff9" => DATA <= x"1460";
when "11" & x"ffa" => DATA <= x"c401";
when "11" & x"ffb" => DATA <= x"7fef";
when "11" & x"ffc" => DATA <= x"c003";
when "11" & x"ffd" => DATA <= x"dedc";
when "11" & x"ffe" => DATA <= x"4e07";
when "11" & x"fff" => DATA <= x"b0ff";
when others => DATA <= (others => '0');
end case;
end process;
end RTL;
| gpl-3.0 | 7b19c09bcdff6d3b15eab67066085e24 | 0.372703 | 2.707302 | false | false | false | false |
pwsoft/fpga_examples | rtl/chameleon/chameleon_cdtv_remote.vhd | 1 | 9,569 | -- -----------------------------------------------------------------------
--
-- Turbo Chameleon
--
-- Multi purpose FPGA expansion for the Commodore 64 computer
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2019 by Peter Wendrich ([email protected])
-- http://www.syntiac.com/chameleon.html
--
-- This source file is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- -----------------------------------------------------------------------
--
-- CDTV IR remote
--
-- -----------------------------------------------------------------------
-- clk - system clock input
-- ena_1mhz - Enable must be high for one clk cycle each microsecond.
-- ir - signal from infra-red detector.
--
-- trigger - pulsed one clk high when new code is received from the CDTV remote.
--
-- key_1 - high when "1" is pressed on remote
-- key_2 - high when "2" is pressed on remote
-- key_3 - high when "3" is pressed on remote
-- key_4 - high when "4" is pressed on remote
-- key_5 - high when "5" is pressed on remote
-- key_6 - high when "6" is pressed on remote
-- key_7 - high when "7" is pressed on remote
-- key_8 - high when "8" is pressed on remote
-- key_9 - high when "9" is pressed on remote
-- key_0 - high when "0" is pressed on remote
-- key_escape - high when "ESCAPE" is pressed on remote
-- key_enter - high when "ENTER" is pressed on remote
-- key_genlock - high when "GENLOCK" is pressed on remote
-- key_cdtv - high when "CD/TV" is pressed on remote
-- key_power - high when "POWER" is pressed on remote
-- key_rew - high when "REW" is pressed on remote
-- key_play - high when "PLAY/PAUSE" is pressed on remote
-- key_ff - high when "FF" is pressed on remote
-- key_stop - high when "STOP" is pressed on remote
-- key_vol_up - high when "VOL up" is pressed on remote
-- key_vol_dn - high when "VOL dn" is pressed on remote
-- joystick_a - first joystick emulation output (bits are '1' when idle).
-- This output is active when remote is in MOUSE mode.
-- joystick_b - second joystick emulation output (bits are '1' when idle).
-- This output is active when remote is in JOY mode.
-- debug_code - Last received raw code from the CDTV remote
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
-- -----------------------------------------------------------------------
entity chameleon_cdtv_remote is
port (
clk : in std_logic;
ena_1mhz : in std_logic;
ir : in std_logic := '1';
trigger : out std_logic;
key_1 : out std_logic;
key_2 : out std_logic;
key_3 : out std_logic;
key_4 : out std_logic;
key_5 : out std_logic;
key_6 : out std_logic;
key_7 : out std_logic;
key_8 : out std_logic;
key_9 : out std_logic;
key_0 : out std_logic;
key_escape : out std_logic;
key_enter : out std_logic;
key_genlock : out std_logic;
key_cdtv : out std_logic;
key_power : out std_logic;
key_rew : out std_logic;
key_play : out std_logic;
key_ff : out std_logic;
key_stop : out std_logic;
key_vol_up : out std_logic;
key_vol_dn : out std_logic;
joystick_a : out unsigned(5 downto 0);
joystick_b : out unsigned(5 downto 0);
debug_code : out unsigned(11 downto 0)
);
end entity;
-- -----------------------------------------------------------------------
architecture rtl of chameleon_cdtv_remote is
constant long_timeout : integer := 110000; -- 110 msec, this timeout is used while receiving a code (timeout is extended)
constant short_timeout : integer := 75000; -- 75 msec, this timeout is used while waiting
type state_t is (
STATE_IDLE, -- Nothing received
STATE_END_CODE, -- Code received, reseting timeouts
STATE_WAIT_REPEAT, -- Waiting for new code or key-held code (for 75 ms)
STATE_START, -- Start of new code
STATE_LOW, -- receive ir signal is low
STATE_HIGH -- receive ir signal is high
);
signal state : state_t := STATE_IDLE;
signal ir_sync_reg : std_logic := '1';
signal ir_reg : std_logic := '1';
signal pre_trigger : std_logic := '0'; -- trigger out 1 clock later to sync with decoding logic
signal timer : integer range 0 to long_timeout := 0;
signal bitlength : integer range 0 to 16000 := 0;
signal bitcount : integer range 0 to 24 := 0;
signal shiftreg : unsigned(23 downto 0) := (others => '0');
signal current_code : unsigned(11 downto 0) := (others => '1');
begin
debug_code <= current_code;
process(clk)
begin
if rising_edge(clk) then
ir_sync_reg <= ir;
ir_reg <= ir_sync_reg;
end if;
end process;
process(clk)
begin
if rising_edge(clk) then
pre_trigger <= '0';
-- State machine
case state is
when STATE_IDLE =>
if (ir_reg = '1') and (bitlength > 8500) then
state <= STATE_START;
end if;
bitcount <= 0;
when STATE_END_CODE =>
-- Transient state to reset timer.
-- Wait for next repeat or new code until timeout.
state <= STATE_WAIT_REPEAT;
bitcount <= 0;
when STATE_WAIT_REPEAT =>
if (ir_reg = '1') and (bitlength > 8500) then
state <= STATE_START;
end if;
bitcount <= 0;
when STATE_START =>
if (ir_reg = '0') and (bitlength > 1500) and (bitlength < 3000) then
-- It is a key-held code. No further processing.
state <= STATE_END_CODE;
end if;
if (ir_reg = '0') and (bitlength >= 3000) then
state <= STATE_LOW;
end if;
bitcount <= 0;
when STATE_LOW =>
if ir_reg = '1' then
state <= STATE_HIGH;
end if;
if bitcount = 24 then
state <= STATE_END_CODE;
if shiftreg(23 downto 12) = (not shiftreg(11 downto 0)) then
-- Valid code
current_code <= shiftreg(23 downto 12);
pre_trigger <= '1';
end if;
end if;
when STATE_HIGH =>
if ir_reg = '0' then
state <= STATE_LOW;
bitcount <= bitcount + 1;
if bitlength > 800 then
-- Long bit (1100)
shiftreg <= shiftreg(shiftreg'high-1 downto shiftreg'low) & '1';
else
-- short bit (420)
shiftreg <= shiftreg(shiftreg'high-1 downto shiftreg'low) & '0';
end if;
end if;
end case;
-- Determine bit-length
if (ir_reg = '1' and ((state = STATE_IDLE) or (state = STATE_WAIT_REPEAT) or (state = STATE_LOW)))
or (ir_reg = '0' and ((state = STATE_START) or (state = STATE_HIGH))) then
bitlength <= 0;
elsif ena_1mhz = '1' then
bitlength <= bitlength + 1;
end if;
-- Process timeout
if (state = STATE_IDLE) or (state = STATE_END_CODE) then
timer <= 0;
elsif timer = long_timeout then
-- Timeout occured, reset statemachine
state <= STATE_IDLE;
bitlength <= 0;
current_code <= (others => '1');
elsif (timer >= short_timeout) and (state = STATE_WAIT_REPEAT) then
-- Timeout occured, reset statemachine
state <= STATE_IDLE;
bitlength <= 0;
current_code <= (others => '1');
elsif ena_1mhz = '1' then
timer <= timer + 1;
end if;
end if;
end process;
decode_ir_code: process(clk)
begin
if rising_edge(clk) then
trigger <= pre_trigger;
key_1 <= '0';
key_2 <= '0';
key_3 <= '0';
key_4 <= '0';
key_5 <= '0';
key_6 <= '0';
key_7 <= '0';
key_8 <= '0';
key_9 <= '0';
key_0 <= '0';
key_escape <= '0';
key_enter <= '0';
key_genlock <= '0';
key_cdtv <= '0';
key_power <= '0';
key_rew <= '0';
key_play <= '0';
key_ff <= '0';
key_stop <= '0';
key_vol_up <= '0';
key_vol_dn <= '0';
joystick_a <= (others => '1');
joystick_b <= (others => '1');
case current_code(5 downto 0) is
when "000001" => key_1 <= '1';
when "100001" => key_2 <= '1';
when "010001" => key_3 <= '1';
when "001001" => key_4 <= '1';
when "101001" => key_5 <= '1';
when "011001" => key_6 <= '1';
when "000101" => key_7 <= '1';
when "100101" => key_8 <= '1';
when "010101" => key_9 <= '1';
when "111001" => key_0 <= '1';
when "110001" => key_escape <= '1';
when "110101" => key_enter <= '1';
when "100010" => key_genlock <= '1';
when "000010" => key_cdtv <= '1';
when "010010" => key_power <= '1';
when "110010" => key_rew <= '1';
when "001010" => key_play <= '1';
when "011010" => key_ff <= '1';
when "101010" => key_stop <= '1';
when "000110" => key_vol_up <= '1';
when "111010" => key_vol_dn <= '1';
when others =>
null;
end case;
if (current_code(11) = '0') and (current_code(1 downto 0) = "00") then
joystick_a <= not (current_code(6) & current_code(7) & current_code(2) & current_code(3) & current_code(4) & current_code(5));
end if;
if (current_code(11) = '1') and (current_code(1 downto 0) = "00") then
joystick_b <= not (current_code(6) & current_code(7) & current_code(2) & current_code(3) & current_code(4) & current_code(5));
end if;
end if;
end process;
end architecture;
| lgpl-2.1 | b1facaa468ee376da64045fe1004cd64 | 0.574877 | 3.165399 | false | false | false | false |
hoglet67/CoPro6502 | src/T6502/T65_MCode.vhd | 1 | 43,817 | -- ****
-- T65(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 303 ost(ML) July 2014
-- (Sorry for some scratchpad comments that may make little sense)
-- Mods and some 6502 undocumented instructions.
-- Undoc opcodes learnt from:
-- "Extra Instructions Of The 65XX Series CPU"
-- By: Adam Vardy ([email protected])
-- [File created: 22, Aug. 1995... 27, Sept. 1996]
-- Ver 302 minor timing fixes
-- Ver 301 Jump timing fixed
-- Ver 300 Bugfixes by ehenciak added
-- Wolfgang January 2014
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- 65xx compatible microprocessor core
--
-- Version : 0246 + fix
--
-- Copyright (c) 2002 Daniel Wallner ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t65/
--
-- Limitations :
--
-- 65C02
-- supported : inc, dec, phx, plx, phy, ply
-- missing : bra, ora, lda, cmp, sbc, tsb*2, trb*2, stz*2, bit*2, wai, stp, jmp, bbr*8, bbs*8
--
-- File history :
--
-- 0246 : First release
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use ieee.std_logic_unsigned.all;
use work.T65_Pack.all;
entity T65_MCode is
port(
Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65816
IR : in std_logic_vector(7 downto 0);
MCycle : in std_logic_vector(2 downto 0);
P : in std_logic_vector(7 downto 0);
LCycle : out std_logic_vector(2 downto 0);
ALU_Op : out T_ALU_Op;
Set_BusA_To : out T_Set_BusA_To;-- DI,A,X,Y,S,P
Set_Addr_To : out T_Set_Addr_To;-- PC Adder,S,AD,BA
Write_Data : out T_Write_Data;-- DL,A,X,Y,S,P,PCL,PCH,A&X
Jump : out std_logic_vector(1 downto 0); -- PC,++,DIDL,Rel
BAAdd : out std_logic_vector(1 downto 0); -- None,DB Inc,BA Add,BA Adj
BreakAtNA : out std_logic;
ADAdd : out std_logic;
AddY : out std_logic;
PCAdd : out std_logic;
Inc_S : out std_logic;
Dec_S : out std_logic;
LDA : out std_logic;
LDP : out std_logic;
LDX : out std_logic;
LDY : out std_logic;
LDS : out std_logic;
LDDI : out std_logic;
LDALU : out std_logic;
LDAD : out std_logic;
LDBAL : out std_logic;
LDBAH : out std_logic;
SaveP : out std_logic;
ALUmore : out std_logic;
Write : out std_logic
);
end T65_MCode;
architecture rtl of T65_MCode is
signal Branch : std_logic;
--ML:I need the Lcycle locally, so I made it a signal.
signal tLcycle:std_logic_vector(Lcycle'range);
signal tALUmore:std_logic;
--Some simulation debug values. Put an unique number for each assignment and identify it in simulation.
signal dbg_Set_BusA_To :integer:=0; --sim debug value to find where Set_BusA_To gets set.
signal dbg_LCycle :integer:=0; --sim debug value to fin where tLCycle gets set.
signal dbg_Set_Addr_To :integer:=0; --sim debug value to fin where Set_Addr_To gets set.
begin
with IR(7 downto 5) select
Branch <= not P(Flag_N) when "000",
P(Flag_N) when "001",
not P(Flag_V) when "010",
P(Flag_V) when "011",
not P(Flag_C) when "100",
P(Flag_C) when "101",
not P(Flag_Z) when "110",
P(Flag_Z) when others;
LCycle<=tLCycle;
ALUmore<=tALUmore;
process (IR, MCycle, P, Branch, Mode,tALUmore)
begin
tLCycle <= "001";
Set_BusA_To <= Set_BusA_To_ABC;
Set_Addr_To <= Set_Addr_To_PBR;
Write_Data <= Write_Data_DL;
Jump <= (others => '0');
BAAdd <= "00";
BreakAtNA <= '0';
ADAdd <= '0';
PCAdd <= '0';
Inc_S <= '0';
Dec_S <= '0';
LDA <= '0';
LDP <= '0';
LDX <= '0';
LDY <= '0';
LDS <= '0';
LDDI <= '0';
LDALU <= '0';
LDAD <= '0';
LDBAL <= '0';
LDBAH <= '0';
SaveP <= '0';
Write <= '0';
AddY <= '0';
tALUmore <='0';
case IR(7 downto 5) is
when "100" =>--covers 8x,9x
--{{{
case IR(1 downto 0) is
when "00" =>
Set_BusA_To <= Set_BusA_To_Y;
dbg_Set_BusA_To<=1;
Write_Data <= Write_Data_Y;
when "10" =>
Set_BusA_To <= Set_BusA_To_X;
dbg_Set_BusA_To<=2;
Write_Data <= Write_Data_X;
when others =>
Write_Data <= Write_Data_ABC;
end case;
--}}}
when "101" =>--covers ax,bx
--{{{
case IR(1 downto 0) is
when "00" =>
if IR(4) /= '1' or IR(2) /= '0' then--only for ax or b4,bc
LDY <= '1';
end if;
when "10" =>
LDX <= '1';
when "11" =>--undoc (beware OAL(ab),LAS(bb)=>Dont know what will happen)
LDX<='1';
LDA<='1';
when others =>
LDA <= '1';
end case;
Set_BusA_To <= Set_BusA_To_DI;
dbg_Set_BusA_To<=4;
--}}}
when "110" =>--covers cx,dx
--{{{
case IR(1 downto 0) is
when "00" =>
if IR(4) = '0' then--only for cx
LDY <= '1';
end if;
Set_BusA_To <= Set_BusA_To_Y;
dbg_Set_BusA_To<=5;
when others =>
Set_BusA_To <= Set_BusA_To_ABC;
dbg_Set_BusA_To<=6;
end case;
--}}}
when "111" =>--covers ex,fx
--{{{
case IR(1 downto 0) is
when "00" =>
if IR(4) = '0' then--only ex
LDX <= '1';
end if;
Set_BusA_To <= Set_BusA_To_X;
dbg_Set_BusA_To<=7;
when others =>
Set_BusA_To <= Set_BusA_To_ABC;
dbg_Set_BusA_To<=8;
end case;
--}}}
when others =>
end case;
-- if IR(7 downto 6) /= "10" and IR(1 downto 0) = "10" then--covers 0x-7x,cx-fx x=2,6,a,e
if IR(7 downto 6) /= "10" and IR(1) = '1' and (mode="00" or IR(0)='0') then--covers 0x-7x,cx-fx x=2,3,6,7,a,b,e,f, for 6502 undocs
-- if Mode="00" and IR(0)='1' and ((IR(3 downto 2)="11" and MCycle = "101") or (IR(3 downto 2)="01" and MCycle = "100"))then
--if Mode="00" and IR(0)='1' and MCycle+1 = tLCycle then
if tALUmore='1' then
Set_BusA_To <= Set_BusA_To_ABC;--For added compare to DCP/DCM
dbg_Set_BusA_To<=99;
else
Set_BusA_To <= Set_BusA_To_DI;
dbg_Set_BusA_To<=9;
end if;
end if;
case IR(4 downto 0) is
when "00000" | "01000" | "01010" | "11000" | "11010" =>
--{{{
-- Implied
case IR is
when "00000000" =>
-- BRK
tLCycle <= "110";
dbg_LCycle<=1;
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= Set_Addr_To_S;
dbg_Set_Addr_To<=1;
Write_Data <= Write_Data_PCH;
Write <= '1';
when 2 =>
Dec_S <= '1';
Set_Addr_To <= Set_Addr_To_S;
dbg_Set_Addr_To<=2;
Write_Data <= Write_Data_PCL;
Write <= '1';
when 3 =>
Dec_S <= '1';
Set_Addr_To <= Set_Addr_To_S;
dbg_Set_Addr_To<=3;
Write_Data <= Write_Data_P;
Write <= '1';
when 4 =>
Dec_S <= '1';
Set_Addr_To <= Set_Addr_To_BA;
dbg_Set_Addr_To<=4;
when 5 =>
LDDI <= '1';
Set_Addr_To <= Set_Addr_To_BA;
dbg_Set_Addr_To<=5;
when 6 =>
Jump <= "10"; -- DIDL
when others =>
end case;
when "00100000" =>
-- JSR
tLCycle <= "101";
dbg_LCycle<=2;
case to_integer(unsigned(MCycle)) is
when 1 =>
Jump <= "01";
LDDI <= '1';
Set_Addr_To <= Set_Addr_To_S;
dbg_Set_Addr_To<=6;
when 2 =>
Set_Addr_To <= Set_Addr_To_S;
dbg_Set_Addr_To<=7;
Write_Data <= Write_Data_PCH;
Write <= '1';
when 3 =>
Dec_S <= '1';
Set_Addr_To <= Set_Addr_To_S;
dbg_Set_Addr_To<=8;
Write_Data <= Write_Data_PCL;
Write <= '1';
when 4 =>
Dec_S <= '1';
when 5 =>
Jump <= "10"; -- DIDL
when others =>
end case;
when "01000000" =>
-- RTI
tLCycle <= "101";
dbg_LCycle<=3;
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= Set_Addr_To_S;
dbg_Set_Addr_To<=9;
when 2 =>
Inc_S <= '1';
Set_Addr_To <= Set_Addr_To_S;
dbg_Set_Addr_To<=10;
when 3 =>
Inc_S <= '1';
Set_Addr_To <= Set_Addr_To_S;
dbg_Set_Addr_To<=11;
Set_BusA_To <= Set_BusA_To_DI;
dbg_Set_BusA_To<=10;
when 4 =>
LDP <= '1';
Inc_S <= '1';
LDDI <= '1';
Set_Addr_To <= Set_Addr_To_S;
dbg_Set_Addr_To<=12;
when 5 =>
Jump <= "10"; -- DIDL
when others =>
end case;
when "01100000" =>
-- RTS
tLCycle <= "101";
dbg_LCycle<=4;
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= Set_Addr_To_S;
dbg_Set_Addr_To<=13;
when 2 =>
Inc_S <= '1';
Set_Addr_To <= Set_Addr_To_S;
dbg_Set_Addr_To<=14;
when 3 =>
Inc_S <= '1';
LDDI <= '1';
Set_Addr_To <= Set_Addr_To_S;
dbg_Set_Addr_To<=15;
when 4 =>
Jump <= "10"; -- DIDL
when 5 =>
Jump <= "01";
when others =>
end case;
when "00001000" | "01001000" | "01011010" | "11011010" =>
-- PHP, PHA, PHY*, PHX*
tLCycle <= "010";
dbg_LCycle<=5;
if Mode = "00" and IR(1) = '1' then--2 cycle nop
tLCycle <= "001";
dbg_LCycle<=6;
end if;
case to_integer(unsigned(MCycle)) is
when 1 =>
if mode/="00" or IR(1)='0' then --wrong on 6502
Write <= '1';
case IR(7 downto 4) is
when "0000" =>
Write_Data <= Write_Data_P;
when "0100" =>
Write_Data <= Write_Data_ABC;
when "0101" => --not correct unsupporte
if Mode /= "00" then
Write_Data <= Write_Data_Y;
else
Write <= '0';
end if;
when "1101" =>
if Mode /= "00" then
Write_Data <= Write_Data_X;
else
Write <= '0';
end if;
when others =>
end case;
Set_Addr_To <= Set_Addr_To_S;
dbg_Set_Addr_To<=16;
end if;
when 2 =>
Dec_S <= '1';
when others =>
end case;
when "00101000" | "01101000" | "01111010" | "11111010" =>
-- PLP, PLA, PLY*, PLX*
tLCycle <= "011";
dbg_LCycle<=7;
if Mode = "00" and IR(1) = '1' then--2 cycle nop
tLCycle <= "001";
dbg_LCycle<=8;
end if;
case IR(7 downto 4) is
when "0010" =>--plp
LDP <= '1';
when "0110" =>--pla
LDA <= '1';
when "0111" =>--ply not for 6502
if Mode /= "00" then
LDY <= '1';
end if;
when "1111" =>--plx not for 6502
if Mode /= "00" then
LDX <= '1';
end if;
when others =>
end case;
case to_integer(unsigned(MCycle)) is
when 0 =>
if Mode /= "00" or IR(1) = '0' then--wrong on 6502
SaveP <= '1';
end if;
when 1 =>
if Mode /= "00" or IR(1) = '0' then--wrong on 6502
Set_Addr_To <= Set_Addr_To_S;
dbg_Set_Addr_To<=17;
-- MWW This is wrong, ALU_OP is not populated yet, so previous op's P_out can be saved (This was caused by ROL followed by PLA - THE ISSUE MAY BE DEEPER!)
--SaveP <= '1'; --MWW
LDP <= '0';--MWW
end if;
when 2 =>
Inc_S <= '1';
Set_Addr_To <= Set_Addr_To_S;
dbg_Set_Addr_To<=18;
--SaveP <= '1';--MWW
LDP <= '0'; --MWW
when 3 =>
Set_BusA_To <= Set_BusA_To_DI;
dbg_Set_BusA_To<=11;
when others =>
end case;
when "10100000" | "11000000" | "11100000" =>
-- LDY, CPY, CPX
-- Immediate
case to_integer(unsigned(MCycle)) is
when 0 =>
when 1 =>
Jump <= "01";
when others =>
end case;
when "10001000" =>
-- DEY
LDY <= '1';
case to_integer(unsigned(MCycle)) is
when 0 =>
when 1 =>
Set_BusA_To <= Set_BusA_To_Y;
dbg_Set_BusA_To<=12;
when others =>
end case;
when "11001010" =>
-- DEX
LDX <= '1';
case to_integer(unsigned(MCycle)) is
when 0 =>
when 1 =>
Set_BusA_To <= Set_BusA_To_X;
dbg_Set_BusA_To<=13;
when others =>
end case;
when "00011010" | "00111010" =>
-- INC*, DEC*
if Mode /= "00" then
LDA <= '1'; -- A
else
tLCycle <= "001";--undoc 2 cycle nop..can I just load tLCycle counter like this?
dbg_LCycle<=9;
end if;
case to_integer(unsigned(MCycle)) is
when 0 =>
when 1 =>
Set_BusA_To <= Set_BusA_To_S;
dbg_Set_BusA_To<=14;
when others =>
end case;
when "00001010" | "00101010" | "01001010" | "01101010" =>
-- ASL, ROL, LSR, ROR
LDA <= '1'; -- A
Set_BusA_To <= Set_BusA_To_ABC;
dbg_Set_BusA_To<=15;
case to_integer(unsigned(MCycle)) is
when 0 =>
when 1 =>
when others =>
end case;
when "10001010" | "10011000" =>
-- TYA, TXA
LDA <= '1'; -- A
case to_integer(unsigned(MCycle)) is
when 0 =>
when 1 =>
when others =>
end case;
when "10101010" | "10101000" =>
-- TAX, TAY
case to_integer(unsigned(MCycle)) is
when 0 =>
when 1 =>
Set_BusA_To <= Set_BusA_To_ABC;
dbg_Set_BusA_To<=16;
when others =>
end case;
when "10011010" =>
-- TXS
case to_integer(unsigned(MCycle)) is
when 0 =>
LDS <= '1';
when 1 =>
when others =>
end case;
when "10111010" =>
-- TSX
LDX <= '1';
case to_integer(unsigned(MCycle)) is
when 0 =>
when 1 =>
Set_BusA_To <= Set_BusA_To_S;
dbg_Set_BusA_To<=17;
when others =>
end case;
-- when "00011000" | "00111000" | "01011000" | "01111000" | "10111000" | "11011000" | "11111000" | "11001000" | "11101000" =>
-- -- CLC, SEC, CLI, SEI, CLV, CLD, SED, INY, INX
-- case to_integer(unsigned(MCycle)) is
-- when 1 =>
-- when others =>
-- end case;
when others =>
case to_integer(unsigned(MCycle)) is
when 0 =>
when others =>
end case;
end case;
--}}}
when "00001" | "00011" =>
--{{{
-- Zero Page Indexed Indirect (d,x)
tLCycle <= "101";
dbg_LCycle<=10;
if IR(7 downto 6) /= "10" then
LDA <= '1';
if Mode="00" and IR(1)='1' then--b3
LDX <= '1';--undoc, can load both A and X
end if;
end if;
case to_integer(unsigned(MCycle)) is
when 1 =>
Jump <= "01";
LDAD <= '1';
Set_Addr_To <= Set_Addr_To_AD;
dbg_Set_Addr_To<=19;
when 2 =>
ADAdd <= '1';
Set_Addr_To <= Set_Addr_To_AD;
dbg_Set_Addr_To<=20;
when 3 =>
BAAdd <= "01"; -- DB Inc
LDBAL <= '1';
Set_Addr_To <= Set_Addr_To_AD;
dbg_Set_Addr_To<=21;
when 4 =>
LDBAH <= '1';
if IR(7 downto 5) = "100" then
Write <= '1';
end if;
Set_Addr_To <= Set_Addr_To_BA;
dbg_Set_Addr_To<=22;
when 5 =>
if Mode="00" and IR(1)='1' then
tALUmore <= '1';--ML:For undoc ASO support
end if;
when 0 =>
if Mode="00" and IR(1)='1' then
SaveP <= '1';--ML:For undoc DCP/DCM support, save again after compare
end if;
when others =>
end case;
--}}}
when "01001" | "01011" =>
--{{{
-- Immediate
LDA <= '1';
case to_integer(unsigned(MCycle)) is
when 0 =>
when 1 =>
Jump <= "01";
when others =>
end case;
--}}}
when "00010" | "10010" =>
--{{{
-- Immediate, SKB, KIL
case to_integer(unsigned(MCycle)) is
when 0 =>
when 1 =>
if IR = "10100010" then
-- LDX
Jump <= "01";
LDX <= '1';--ML:Moved, Lorenz test showed X changing on SKB (NOPx)
elsif IR(7 downto 4)="1000" or IR(7 downto 4)="1100" or IR(7 downto 4)="1110" then
-- SKB skip next byte undoc
else
-- KIL !!!!!!!!!!!!!!!!!!!!!!!!!!!!!
end if;
when others =>
end case;
--}}}
when "00100" =>
--{{{
-- Zero Page
tLCycle <= "010";
dbg_LCycle<=11;
case to_integer(unsigned(MCycle)) is
when 0 =>
if IR(7 downto 5) = "001" then--24=BIT zpg
SaveP <= '1';
end if;
when 1 =>
Jump <= "01";
LDAD <= '1';
if IR(7 downto 5) = "100" then--84=sty zpg (the only write in this group)
Write <= '1';
end if;
Set_Addr_To <= Set_Addr_To_AD;
dbg_Set_Addr_To<=23;
when 2 =>
when others =>
end case;
--}}}
when "00101" | "00110" | "00111" =>
--{{{
-- Zero Page
-- if IR(7 downto 6) /= "10" and IR(1 downto 0) = "10" then--0x-7x,cx-fx, x=2,6,a,e
if IR(7 downto 6) /= "10" and IR(1) = '1' and (mode="00" or IR(0)='0') then--covers 0x-7x,cx-fx x=2,3,6,7,a,b,e,f, for 6502 undocs
-- Read-Modify-Write
if Mode="00" and IR(0)='1' then
LDA<='1';
end if;
tLCycle <= "100";
dbg_LCycle<=12;
case to_integer(unsigned(MCycle)) is
when 1 =>
Jump <= "01";
LDAD <= '1';
Set_Addr_To <= Set_Addr_To_AD;
dbg_Set_Addr_To<=24;
when 2 =>
LDDI <= '1';
if Mode="00" then--The old 6500 writes back what is just read, before changing. The 65c does another read
Write <= '1';
end if;
Set_Addr_To <= Set_Addr_To_AD;
dbg_Set_Addr_To<=25;
when 3 =>
LDALU <= '1';
SaveP <= '1';
Write <= '1';
Set_Addr_To <= Set_Addr_To_AD;
dbg_Set_Addr_To<=26;
when 4 =>
if Mode="00" and IR(0)='1' then
tALUmore <= '1';--ML:For undoc DCP/DCM support
end if;
when 0 =>
if Mode="00" and IR(0)='1' then
SaveP <= '1';--ML:For undoc DCP/DCM support, save again after compare
end if;
when others =>
end case;
else
tLCycle <= "010";
dbg_LCycle<=13;
if IR(7 downto 6) /= "10" then
LDA <= '1';
if Mode="00" and IR(1)='1' then--b3
LDX <= '1';--undoc, can load both A and X
end if;
end if;
case to_integer(unsigned(MCycle)) is
when 0 =>
when 1 =>
Jump <= "01";
LDAD <= '1';
if IR(7 downto 5) = "100" then
Write <= '1';
end if;
Set_Addr_To <= Set_Addr_To_AD;
dbg_Set_Addr_To<=27;
when 2 =>
when others =>
end case;
end if;
--}}}
when "01100" =>
--{{{
-- Absolute
if IR(7 downto 6) = "01" and IR(4 downto 0) = "01100" then--4c,6c
-- JMP
if IR(5) = '0' then
--tLCycle <= "011";
tLCycle <= "010";
dbg_LCycle<=14;
case to_integer(unsigned(MCycle)) is
when 1 =>
Jump <= "01";
LDDI <= '1';
when 2 =>
Jump <= "10"; -- DIDL
when others =>
end case;
else
--tLCycle <= "101";
tLCycle <= "100"; -- mikej
dbg_LCycle<=15;
case to_integer(unsigned(MCycle)) is
when 1 =>
Jump <= "01";
LDDI <= '1';
LDBAL <= '1';
when 2 =>
LDBAH <= '1';
if Mode /= "00" then
Jump <= "10"; -- DIDL
end if;
if Mode = "00" then
Set_Addr_To <= Set_Addr_To_BA;
dbg_Set_Addr_To<=28;
end if;
when 3 =>
LDDI <= '1';
if Mode = "00" then
Set_Addr_To <= Set_Addr_To_BA;
dbg_Set_Addr_To<=29;
BAAdd <= "01"; -- DB Inc
else
Jump <= "01";
end if;
when 4 =>
Jump <= "10"; -- DIDL
when others =>
end case;
end if;
else
tLCycle <= "011";
dbg_LCycle<=16;
case to_integer(unsigned(MCycle)) is
when 0 =>
if IR(7 downto 5) = "001" then--2c-BIT
SaveP <= '1';
end if;
when 1 =>
Jump <= "01";
LDBAL <= '1';
when 2 =>
Jump <= "01";
LDBAH <= '1';
if IR(7 downto 5) = "100" then--80, sty, the only write in this group
Write <= '1';
end if;
Set_Addr_To <= Set_Addr_To_BA;
dbg_Set_Addr_To<=30;
when 3 =>
when others =>
end case;
end if;
--}}}
when "01101" | "01110" | "01111" =>
--{{{
-- Absolute
-- if IR(7 downto 6) /= "10" and IR(1 downto 0) = "10" then--0x-7x,cx-fx, x=2,6,a,e
if IR(7 downto 6) /= "10" and IR(1) = '1' and (mode="00" or IR(0)='0') then--covers 0x-7x,cx-fx x=2,3,6,7,a,b,e,f, for 6502 undocs
-- Read-Modify-Write
tLCycle <= "101";
dbg_LCycle<=17;
case to_integer(unsigned(MCycle)) is
when 1 =>
Jump <= "01";
LDBAL <= '1';
when 2 =>
Jump <= "01";
LDBAH <= '1';
Set_Addr_To <= Set_Addr_To_BA;
dbg_Set_Addr_To<=31;
when 3 =>
LDDI <= '1';
if Mode="00" then--The old 6500 writes back what is just read, before changing. The 65c does another read
Write <= '1';
end if;
Set_Addr_To <= Set_Addr_To_BA;
dbg_Set_Addr_To<=32;
when 4 =>
Write <= '1';
LDALU <= '1';
SaveP <= '1';
Set_Addr_To <= Set_Addr_To_BA;
dbg_Set_Addr_To<=33;
when 5 =>
--SaveP <= '0'; -- MIKEJ was 1
if Mode="00" and IR(0)='1' then
tALUmore <= '1';--ML:For undoc DCP/DCM support
end if;
when 0 =>
if Mode="00" and IR(0)='1' then
SaveP <= '1';--ML:For undoc DCP/DCM support, save again after compare
end if;
when others =>
end case;
else
tLCycle <= "011";
dbg_LCycle<=18;
if IR(7 downto 6) /= "10" then
LDA <= '1';
if Mode="00" and IR(1)='1' then--b3
LDX <= '1';--undoc, can load both A and X
end if;
end if;
case to_integer(unsigned(MCycle)) is
when 0 =>
when 1 =>
Jump <= "01";
LDBAL <= '1';
when 2 =>
Jump <= "01";
LDBAH <= '1';
if IR(7 downto 5) = "100" then
Write <= '1';
end if;
Set_Addr_To <= Set_Addr_To_BA;
dbg_Set_Addr_To<=34;
when 3 =>
when others =>
end case;
end if;
--}}}
when "10000" =>
--{{{
-- Relative
-- This circuit dictates when the last
-- microcycle occurs for the branch depending on
-- whether or not the branch is taken and if a page
-- is crossed...
if (Branch = '1') then
tLCycle <= "011"; -- We're done @ T3 if branching...upper
-- level logic will stop at T2 if no page cross
-- (See the Break signal)
dbg_LCycle<=19;
else
tLCycle <= "001";
dbg_LCycle<=20;
end if;
-- This decodes the current microcycle and takes the
-- proper course of action...
case to_integer(unsigned(MCycle)) is
-- On the T1 microcycle, increment the program counter
-- and instruct the upper level logic to fetch the offset
-- from the Din bus and store it in the data latches. This
-- will be the last microcycle if the branch isn't taken.
when 1 =>
Jump <= "01"; -- Increments the PC by one (PC will now be PC+2)
-- from microcycle T0.
LDDI <= '1'; -- Tells logic in top level (T65.vhd) to route
-- the Din bus to the memory data latch (DL)
-- so that the branch offset is fetched.
-- In microcycle T2, tell the logic in the top level to
-- add the offset. If the most significant byte of the
-- program counter (i.e. the current "page") does not need
-- updating, we are done here...the Break signal at the
-- T65.vhd level takes care of that...
when 2 =>
Jump <= "11"; -- Tell the PC Jump logic to use relative mode.
PCAdd <= '1'; -- This tells the PC adder to update itself with
-- the current offset recently fetched from
-- memory.
-- The following is microcycle T3 :
-- The program counter should be completely updated
-- on this cycle after the page cross is detected.
-- We don't need to do anything here...
when 3 =>
when others => null; -- Do nothing.
end case;
--}}}
when "10001" | "10011" =>
--{{{
-- Zero Page Indirect Indexed (d),y
tLCycle <= "101";
dbg_LCycle<=21;
if IR(7 downto 6) /= "10" then--91,b1,93,b3 only
LDA <= '1';
if Mode="00" and IR(1)='1' then--b3
LDX <= '1';--undoc, can load both A and X
end if;
end if;
case to_integer(unsigned(MCycle)) is
when 1 =>
Jump <= "01";
LDAD <= '1';
Set_Addr_To <= Set_Addr_To_AD;
dbg_Set_Addr_To<=35;
when 2 =>
LDBAL <= '1';
BAAdd <= "01"; -- DB Inc
Set_Addr_To <= Set_Addr_To_AD;
dbg_Set_Addr_To<=36;
when 3 =>
Set_BusA_To <= Set_BusA_To_Y;
dbg_Set_BusA_To<=18;
BAAdd <= "10"; -- BA Add
LDBAH <= '1';
Set_Addr_To <= Set_Addr_To_BA;
dbg_Set_Addr_To<=37;
when 4 =>
BAAdd <= "11"; -- BA Adj
if IR(7 downto 5) = "100" or IR(1)='1' then
Write <= '1';
else
BreakAtNA <= '1';
if Mode="00" and IR(1)='1' then
tALUmore <= '1';--ML:For undoc
end if;
end if;
Set_Addr_To <= Set_Addr_To_BA;
dbg_Set_Addr_To<=38;
when 5 =>
if Mode="00" and IR(1)='1' then
tALUmore <= '1';--ML:For undoc
end if;
when 0 =>
if Mode="00" and IR(1)='1' then
SaveP <= '1';--ML:For undoc
end if;
when others =>
end case;
--}}}
when "10100" | "10101" | "10110" | "10111" =>
--{{{
-- Zero Page, X
-- if IR(7 downto 6) /= "10" and IR(1 downto 0) = "10" then--16,36,56,76,d6,f6
if IR(7 downto 6) /= "10" and IR(1) = '1' and (Mode="00" or IR(0)='0') then--covers 0x-7x,cx-fx x=2,3,6,7,a,b,e,f, for 6502 undocs
-- Read-Modify-Write
if Mode="00" and IR(0)='1' then
LDA<='1';
end if;
tLCycle <= "101";
dbg_LCycle<=22;
case to_integer(unsigned(MCycle)) is
when 1 =>
Jump <= "01";
LDAD <= '1';
Set_Addr_To <= Set_Addr_To_AD;
dbg_Set_Addr_To<=39;
when 2 =>
ADAdd <= '1';
Set_Addr_To <= Set_Addr_To_AD;
dbg_Set_Addr_To<=40;
when 3 =>
LDDI <= '1';
if Mode="00" then--The old 6500 writes back what is just read, before changing. The 65c does another read
Write <= '1';
end if;
Set_Addr_To <= Set_Addr_To_AD;
dbg_Set_Addr_To<=41;
when 4 =>
LDALU <= '1';
SaveP <= '1';
Write <= '1';
Set_Addr_To <= Set_Addr_To_AD;
dbg_Set_Addr_To<=42;
when 5 =>
if Mode="00" and IR(0)='1' then
tALUmore <= '1';--ML:For undoc DCP/DCM support
end if;
when 0 =>
if Mode="00" and IR(0)='1' then
SaveP <= '1';--ML:For undoc DCP/DCM support, save again after compare
end if;
when others =>
end case;
elsif Mode="00" and IR(7 downto 6)/="10" and IR(4)='1' and IR(1 downto 0)="00" then --covers 1x,3x,5x,7x,dx,fx, for skb/nopzx 6502 undocs
tLCycle <= "011";--SKB's at x4
dbg_LCycle<=222;
case to_integer(unsigned(MCycle)) is
when 1 =>
Jump <= "01";--skip a byte
when others=>
end case;
else
tLCycle <= "011";
dbg_LCycle<=23;
if IR(7 downto 6) /= "10" then
LDA <= '1';
if Mode="00" and IR(1 downto 0)="11" then--x7
LDX <= '1';--undoc, can load both A and X
end if;
end if;
case to_integer(unsigned(MCycle)) is
when 0 =>
when 1 =>
Jump <= "01";
LDAD <= '1';
Set_Addr_To <= Set_Addr_To_AD;
dbg_Set_Addr_To<=43;
when 2 =>
ADAdd <= '1';
-- Added this check for Y reg. use...
if (IR(3 downto 0) = "0110") then--96,b6
AddY <= '1';
end if;
if IR(7 downto 5) = "100" then--94,95,96,97 the only write instruction
Write <= '1';
end if;
Set_Addr_To <= Set_Addr_To_AD;
dbg_Set_Addr_To<=44;
when 3 => null;
when others =>
end case;
end if;
--}}}
when "11001" | "11011" =>
--{{{
-- Absolute Y
tLCycle <= "100";
dbg_LCycle<=24;
if IR(7 downto 6) /= "10" then
LDA <= '1';
if Mode="00" and IR(1 downto 0)="11" then--xb
LDX <= '1';--undoc, can load both A and X
end if;
end if;
case to_integer(unsigned(MCycle)) is
when 1 =>
Jump <= "01";
LDBAL <= '1';
when 2 =>
Jump <= "01";
Set_BusA_To <= Set_BusA_To_Y;
dbg_Set_BusA_To<=19;
BAAdd <= "10"; -- BA Add
LDBAH <= '1';
Set_Addr_To <= Set_Addr_To_BA;
dbg_Set_Addr_To<=45;
when 3 =>
BAAdd <= "11"; -- BA adj
-- if IR(7 downto 5) = "100" then--99/9b
if IR(7 downto 5) = "100" or IR(1)='1' then
Write <= '1';
else
BreakAtNA <= '1';
end if;
Set_Addr_To <= Set_Addr_To_BA;
dbg_Set_Addr_To<=46;
when 4 =>
if Mode="00" and IR(1)='1' then
tALUmore <= '1';--ML:For undoc
end if;
when 0 =>
if Mode="00" and IR(1)='1' then
SaveP <= '1';--ML:For undoc
end if;
when others =>
end case;
--}}}
when "11100" | "11101" | "11110" | "11111" =>
--{{{
-- Absolute X
-- if IR(7 downto 6) /= "10" and IR(1 downto 0) = "10" then--1x,3x,5x,7x,dx,fx, x=c,d,e,f
if IR(7 downto 6) /= "10" and IR(1) = '1' and (Mode="00" or IR(0)='0') then--covers 0x-7x,cx-fx x=2,3,6,7,a,b,e,f, for 6502 undocs
-- Read-Modify-Write
tLCycle <= "110";
dbg_LCycle<=25;
case to_integer(unsigned(MCycle)) is
when 1 =>
Jump <= "01";
LDBAL <= '1';
when 2 =>
Jump <= "01";
Set_BusA_To <= Set_BusA_To_X;
dbg_Set_BusA_To<=20;
BAAdd <= "10"; -- BA Add
LDBAH <= '1';
Set_Addr_To <= Set_Addr_To_BA;
dbg_Set_Addr_To<=47;
when 3 =>
BAAdd <= "11"; -- BA adj
Set_Addr_To <= Set_Addr_To_BA;
dbg_Set_Addr_To<=48;
when 4 =>
LDDI <= '1';
if Mode="00" then--The old 6500 writes back what is just read, before changing. The 65c does another read
Write <= '1';
end if;
Set_Addr_To <= Set_Addr_To_BA;
dbg_Set_Addr_To<=49;
when 5 =>
LDALU <= '1';
SaveP <= '1';
Write <= '1';
Set_Addr_To <= Set_Addr_To_BA;
dbg_Set_Addr_To<=50;
when 6 =>
if Mode="00" and IR(0)='1' then
tALUmore <= '1';--ML:For undoc DCP/DCM support
end if;
when 0 =>
if Mode="00" and IR(0)='1' then
SaveP <= '1';--ML:For undoc DCP/DCM support, save again after compare
end if;
when others =>
end case;
-- elsif Mode="00" and IR(7 downto 6)/="10" and IR(4)='1' and IR(1 downto 0)="00" then --covers 1x,3x,5x,7x,dx,fx, for 6502 skw/nopax undocs
-- tLCycle <= "100";--SKW's at xc
-- dbg_LCycle<=260;
-- case to_integer(unsigned(MCycle)) is
-- when 1 =>
-- Jump <= "01";--skip a byte
-- when 2 =>
-- Jump <= "01";--skip a byte
-- when 3 =>
-- BreakAtNA <= '1';
-- when others=>
-- end case;
else--9c,9d,9e,9f,bc,bd,be,bf
tLCycle <= "100";
dbg_LCycle<=26;
if IR(7 downto 6) /= "10" then
if Mode/="00" or IR(4)='0' or IR(1 downto 0)/="00" then --covers 1x,3x,5x,7x,dx,fx, for 6502 skw/nopax undocs
LDA <= '1';
if Mode="00" and IR(1 downto 0)="11" then--9f,bf
LDX <= '1';--undoc, can load both A and X
end if;
end if;
end if;
case to_integer(unsigned(MCycle)) is
when 0 =>
when 1 =>
Jump <= "01";
LDBAL <= '1';
when 2 =>
Jump <= "01";
-- mikej
-- special case 0xBE which uses Y reg as index!! (added undoc 9e,9f,bf)
-- if (IR = "10-1111-") then
if(IR(7 downto 6)="10" and IR(4 downto 1)="1111") then
Set_BusA_To <= Set_BusA_To_Y;
dbg_Set_BusA_To<=21;
else
Set_BusA_To <= Set_BusA_To_X;
dbg_Set_BusA_To<=22;
end if;
BAAdd <= "10"; -- BA Add
LDBAH <= '1';
Set_Addr_To <= Set_Addr_To_BA;
dbg_Set_Addr_To<=51;
when 3 =>
BAAdd <= "11"; -- BA adj
if IR(7 downto 5) = "100" then--9x
Write <= '1';
else
BreakAtNA <= '1';
end if;
Set_Addr_To <= Set_Addr_To_BA;
dbg_Set_Addr_To<=52;
when 4 =>
when others =>
end case;
end if;
--}}}
when others =>
end case;
end process;
process (IR, MCycle, Mode,tALUmore)
begin
-- ORA, AND, EOR, ADC, NOP, LD, CMP, SBC
-- ASL, ROL, LSR, ROR, BIT, LD, DEC, INC
case IR(1 downto 0) is
when "00" =>
--{{{
case IR(4 downto 2) is
when "000" | "001" | "011" =>-- "---0 xx00", xx!="10"
case IR(7 downto 5) is
when "110" | "111" =>--c0,c4,cc,e0,e5,ec
-- CP
ALU_Op <= ALU_OP_CMP;
when "101" =>--a0,a4,ac
-- LD
ALU_Op <= ALU_OP_EQ2;
when "001" =>--20,24,2c (20 is ignored, as its a jmp)
-- BIT
ALU_Op <= ALU_OP_BIT;
when others =>--other x0,x4,xc
-- NOP/ST
ALU_Op <= ALU_OP_EQ1;
end case;
when "010" =>-- "---0 1000"
case IR(7 downto 5) is
when "111" | "110" =>--c8,e8
-- IN
ALU_Op <= ALU_OP_INC;
when "100" =>--88
-- DEY
ALU_Op <= ALU_OP_DEC;
when others =>
-- LD
ALU_Op <= ALU_OP_EQ3;
end case;
when "110" =>-- "---1 1000"
case IR(7 downto 5) is
when "100" =>--98
-- TYA
ALU_Op <= ALU_OP_EQ3;
when others =>
ALU_Op <= ALU_OP_UNDEF;
end case;
when others =>-- "---x xx00"
case IR(7 downto 5) is
when "101" =>--ax,bx
-- LD
ALU_Op <= ALU_OP_EQ3;
when others =>
ALU_Op <= ALU_OP_EQ1;
end case;
end case;
--}}}
when "01" => -- OR
--{{{
case(to_integer(unsigned(IR(7 downto 5)))) is
when 0=>
ALU_Op<=ALU_OP_OR;
when 1=>
ALU_Op<=ALU_OP_AND;
when 2=>
ALU_Op<=ALU_OP_EOR;
when 3=>
ALU_Op<=ALU_OP_ADC;
when 4=>
ALU_Op<=ALU_OP_EQ1;--sta
when 5=>
ALU_Op<=ALU_OP_EQ2;--lda
when 6=>
ALU_Op<=ALU_OP_CMP;
when others=>
ALU_Op<=ALU_OP_SBC;
end case;
--ML:replaced by above case()
-- ALU_Op(3) <= '0';
-- ALU_Op(2 downto 0) <= IR(7 downto 5);
--}}}
when "10" =>
--{{{
case(to_integer(unsigned(IR(7 downto 5)))) is
when 0=>
ALU_Op<=ALU_OP_ASL;
when 1=>
ALU_Op<=ALU_OP_ROL;
when 2=>
ALU_Op<=ALU_OP_LSR;
when 3=>
ALU_Op<=ALU_OP_ROR;
when 4=>
ALU_Op<=ALU_OP_BIT;
when 5=>
ALU_Op<=ALU_OP_EQ3;--ldx
when 6=>
ALU_Op<=ALU_OP_DEC;
when others=>
ALU_Op<=ALU_OP_INC;
end case;
--ML:replaced by above case()
-- ALU_Op(3) <= '1';
-- ALU_Op(2 downto 0) <= IR(7 downto 5);
case IR(7 downto 5) is
when "000" =>
if IR(4 downto 2) = "110" and Mode/="00" then--ML:00011010,1a->inc acc, not on 6502
-- INC
ALU_Op <= ALU_OP_INC;
end if;
when "001" =>
if IR(4 downto 2) = "110" and Mode/="00" then--ML:00111010,3a->dec acc, not on 6502
-- DEC
ALU_Op <= ALU_OP_DEC;
end if;
when "100" =>
if IR(4 downto 2) = "010" then --10001010,8a->TXA
-- TXA
ALU_Op <= ALU_OP_EQ2;
else --100xxx10, 82,86,8e,92,96,9a,9e
ALU_Op <= ALU_OP_EQ1;
end if;
when others =>
end case;
--}}}
when others =>--"11" undoc double alu ops
--{{{
case IR(7 downto 5) is
when "101" =>--ax,bx
ALU_Op <= ALU_OP_EQ1;
when others =>
-- if MCycle >= tLCycle then
if tALUmore='1' then
case(to_integer(unsigned(IR(7 downto 5)))) is
when 0=>
ALU_Op<=ALU_OP_OR;
when 1=>
ALU_Op<=ALU_OP_AND;
when 2=>
ALU_Op<=ALU_OP_EOR;
when 3=>
ALU_Op<=ALU_OP_ADC;
when 4=>
ALU_Op<=ALU_OP_EQ1;--sta
when 5=>
ALU_Op<=ALU_OP_EQ2;--lda
when 6=>
ALU_Op<=ALU_OP_CMP;
when others=>
ALU_Op<=ALU_OP_SBC;
end case;
--replaced by above case()
-- ALU_Op(3) <= '0';
-- ALU_Op(2 downto 0) <= IR(7 downto 5);
else
case(to_integer(unsigned(IR(7 downto 5)))) is
when 0=>
ALU_Op<=ALU_OP_ASL;
when 1=>
ALU_Op<=ALU_OP_ROL;
when 2=>
ALU_Op<=ALU_OP_LSR;
when 3=>
ALU_Op<=ALU_OP_ROR;
when 4=>
ALU_Op<=ALU_OP_BIT;
when 5=>
ALU_Op<=ALU_OP_EQ3;--ldx
when 6=>
ALU_Op<=ALU_OP_DEC;
when others=>
ALU_Op<=ALU_OP_INC;
end case;
--replaced by above case()
-- ALU_Op(3) <= '1';
-- ALU_Op(2 downto 0) <= IR(7 downto 5);
end if;
end case;
--}}}
end case;
end process;
end;
| gpl-3.0 | c485b301611770bdc16e88d4f970ac28 | 0.440103 | 3.498084 | false | false | false | false |
pwsoft/fpga_examples | rtl/ttl/ttl_7404.vhd | 1 | 2,701 | -- -----------------------------------------------------------------------
--
-- Syntiac VHDL support files.
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2018 by Peter Wendrich ([email protected])
-- http://www.syntiac.com
--
-- This source file is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- -----------------------------------------------------------------------
-- Hex inverter
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use work.ttl_pkg.all;
-- -----------------------------------------------------------------------
entity ttl_7404 is
generic (
latency : integer := 1
);
port (
emuclk : in std_logic;
p1 : in ttl_t;
p2 : out ttl_t;
p3 : in ttl_t;
p4 : out ttl_t;
p5 : in ttl_t;
p6 : out ttl_t;
p8 : out ttl_t;
p9 : in ttl_t;
p10 : out ttl_t;
p11 : in ttl_t;
p12 : out ttl_t;
p13 : in ttl_t
);
end entity;
architecture rtl of ttl_7404 is
signal p2_loc : ttl_t;
signal p4_loc : ttl_t;
signal p6_loc : ttl_t;
signal p8_loc : ttl_t;
signal p10_loc : ttl_t;
signal p12_loc : ttl_t;
begin
p2_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p2_loc, q => p2);
p4_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p4_loc, q => p4);
p6_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p6_loc, q => p6);
p8_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p8_loc, q => p8);
p10_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p10_loc, q => p10);
p12_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p12_loc, q => p12);
p2_loc <= not(p1);
p4_loc <= not(p3);
p6_loc <= not(p5);
p8_loc <= not(p9);
p10_loc <= not(p11);
p12_loc <= not(p13);
end architecture;
| lgpl-2.1 | fa31c006de4c20842768dfc7e0ac79ab | 0.569419 | 3.155374 | false | false | false | false |
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