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NeuroML/org.neuroml.export | src/main/resources/vhdl/ParamMux.vhd | 1 | 1,019 | --
-- Parameterisable N to M mux.
--
LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ParamMux is
generic(
NSpikeSources : integer := 32; -- The number of spike sources.
NOutputs : integer := 16; -- The number of Synapses in the neuron model.
NSelectBits : integer := 5); -- Log2(NSpikeSources), rounded up.
port(
SpikeIn : In Std_logic_vector((NSpikeSources-1) downto 0);
SelectIn : In Std_logic_vector(((NOutputs*NSelectBits)-1) downto 0);
SpikeOut : Out Std_logic_vector((NOutputs-1) downto 0));
end ParamMux;
architecture RTL of ParamMux is
begin
--
-- Convert the incoming select signals to integer so we can use them as an index,
-- then use them as an index into SpikeIn to make a mux.
--
process(SelectIn,SpikeIn)
variable Sel : integer;
begin
for i in 0 to (NOutputs-1) loop
Sel:= conv_integer(SelectIn((i*NSelectBits+NSelectBits-1) downto (i*NSelectBits)));
SpikeOut(i) <= SpikeIn(Sel);
end loop;
end process;
end RTL;
| lgpl-3.0 | 6eb9e4c6c6cb65ec282d5d31d2d5aefa | 0.692836 | 2.886686 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-asic/config.vhd | 1 | 7,928 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2013 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := saed32;
constant CFG_MEMTECH : integer := saed32;
constant CFG_PADTECH : integer := saed32;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 1;
constant CFG_SCAN : integer := 1;
-- JTAG boundary-scan chain
constant CFG_BOUNDSCAN_EN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := saed32;
constant CFG_CLKMUL : integer := 2;
constant CFG_CLKDIV : integer := 2;
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (4);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 4;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0 + 1*2 + 4*1;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 0;
constant CFG_ITLBNUM : integer := 2;
constant CFG_DTLBNUM : integer := 2;
constant CFG_TLB_TYPE : integer := 1 + 0*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 4 + 64*0;
constant CFG_ATBSZ : integer := 0;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_STAT_ENABLE : integer := 0;
constant CFG_STAT_CNT : integer := 1;
constant CFG_STAT_NMAX : integer := 0;
constant CFG_STAT_DSUEN : integer := 0;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
constant CFG_ALTWIN : integer := 0;
constant CFG_REX : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 8;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000000#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 1;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 1;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- AHB status register
constant CFG_AHBSTAT : integer := 1;
constant CFG_AHBSTATN : integer := (1);
-- Spacewire interface
constant CFG_SPW_EN : integer := 0;
constant CFG_SPW_NUM : integer := 1;
constant CFG_SPW_AHBFIFO : integer := 4;
constant CFG_SPW_RXFIFO : integer := 16;
constant CFG_SPW_RMAP : integer := 0;
constant CFG_SPW_RMAPBUF : integer := 4;
constant CFG_SPW_RMAPCRC : integer := 0;
constant CFG_SPW_NETLIST : integer := 0;
constant CFG_SPW_FT : integer := 0;
constant CFG_SPW_GRSPW : integer := 2;
constant CFG_SPW_RXUNAL : integer := 0;
constant CFG_SPW_DMACHAN : integer := 1;
constant CFG_SPW_PORTS : integer := 1;
constant CFG_SPW_INPUT : integer := 2;
constant CFG_SPW_OUTPUT : integer := 0;
constant CFG_SPW_RTSAME : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 8;
-- SPI memory controller
constant CFG_SPIMCTRL : integer := 0;
constant CFG_SPIMCTRL_SDCARD : integer := 0;
constant CFG_SPIMCTRL_READCMD : integer := 16#0#;
constant CFG_SPIMCTRL_DUMMYBYTE : integer := 0;
constant CFG_SPIMCTRL_DUALOUTPUT : integer := 0;
constant CFG_SPIMCTRL_SCALER : integer := 1;
constant CFG_SPIMCTRL_ASCALER : integer := 1;
constant CFG_SPIMCTRL_PWRUPCNT : integer := 0;
constant CFG_SPIMCTRL_OFFSET : integer := 16#0#;
-- SPI controller
constant CFG_SPICTRL_ENABLE : integer := 1;
constant CFG_SPICTRL_NUM : integer := (1);
constant CFG_SPICTRL_SLVS : integer := (6);
constant CFG_SPICTRL_FIFO : integer := (4);
constant CFG_SPICTRL_SLVREG : integer := 1;
constant CFG_SPICTRL_ODMODE : integer := 0;
constant CFG_SPICTRL_AM : integer := 0;
constant CFG_SPICTRL_ASEL : integer := 0;
constant CFG_SPICTRL_TWEN : integer := 0;
constant CFG_SPICTRL_MAXWLEN : integer := (0);
constant CFG_SPICTRL_SYNCRAM : integer := 0;
constant CFG_SPICTRL_FT : integer := 0;
-- CAN 2.0 interface
constant CFG_CAN : integer := 0;
constant CFG_CAN_NUM : integer := 1;
constant CFG_CANIO : integer := 16#0#;
constant CFG_CANIRQ : integer := 0;
constant CFG_CANSEPIRQ: integer := 0;
constant CFG_CAN_SYNCRST : integer := 0;
constant CFG_CANFT : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- UART 2
constant CFG_UART2_ENABLE : integer := 1;
constant CFG_UART2_FIFO : integer := 4;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (4);
constant CFG_GPT_SW : integer := (12);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 0;
constant CFG_GPT_WDOGEN : integer := 1;
constant CFG_GPT_WDOG : integer := 16#FFFFF#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#FE#;
constant CFG_GRGPIO_WIDTH : integer := (16);
-- I2C master
constant CFG_I2C_ENABLE : integer := 1;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-3.0 | b4c4639feee3ac11e9170c6768e27b00 | 0.651488 | 3.608557 | false | false | false | false |
GLADICOS/SPACEWIRESYSTEMC | rtl/RTL_VJ/SpaceWireCODECIPTimeCodeControl.vhdl | 1 | 4,660 | ------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) <2013> <Shimafuji Electric Inc., Osaka University, JAXA>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity SpaceWireCODECIPTimeCodeControl is
port (
clock : in std_logic;
reset : in std_logic;
receiveClock : in std_logic;
gotTimeCode : in std_logic;
receiveTimeCodeOut : in std_logic_vector(7 downto 0);
timeOut : out std_logic_vector(5 downto 0);
controlFlagsOut : out std_logic_vector(1 downto 0);
tickOut : out std_logic
);
end SpaceWireCODECIPTimeCodeControl;
architecture Behavioral of SpaceWireCODECIPTimeCodeControl is
component SpaceWireCODECIPSynchronizeOnePulse is
port (
clock : in std_logic;
asynchronousClock : in std_logic;
reset : in std_logic;
asynchronousIn : in std_logic;
synchronizedOut : out std_logic
);
end component;
signal iReceiveTimeCodeOutRegister : std_logic_vector (7 downto 0);
signal iControlFlags : std_logic_vector(1 downto 0);
signal iReceiveTimeCode : std_logic_vector(5 downto 0);
signal iReceiveTimeCodePlus1 : std_logic_vector(5 downto 0);
signal iTickOutSignal : std_logic;
signal gotTimeCodeSynchronized : std_logic;
begin
timeOut <= iReceiveTimeCode;
controlFlagsOut <= iControlFlags;
tickOut <= iTickOutSignal;
----------------------------------------------------------------------
-- ECSS-E-ST-50-12C 8.12 System time distribution (normative)
-- ECSS-E-ST-50-12C 7.3 Control characters and control codes
-- The new time should be one more than the time-counter's previous
-- time-value.
----------------------------------------------------------------------
process (clock, reset)
begin
if (reset = '1') then
iReceiveTimeCode <= (others => '0');
iReceiveTimeCodePlus1 <= "000001";
iTickOutSignal <= '0';
iControlFlags <= "00";
iReceiveTimeCodeOutRegister <= (others => '0');
else
if (clock'event and clock = '1') then
if (gotTimeCodeSynchronized = '1') then
iControlFlags <= iReceiveTimeCodeOutRegister (7 downto 6);
iReceiveTimeCode <= iReceiveTimeCodeOutRegister (5 downto 0);
iReceiveTimeCodePlus1 <= iReceiveTimeCodeOutRegister (5 downto 0) + 1;
if (iReceiveTimeCodePlus1 = iReceiveTimeCodeOutRegister (5 downto 0)) then
iTickOutSignal <= '1';
end if;
else
iTickOutSignal <= '0';
end if;
iReceiveTimeCodeOutRegister <= receiveTimeCodeOut;
end if;
end if;
end process;
timeCodePulse : SpaceWireCODECIPSynchronizeOnePulse
port map (
clock => clock,
asynchronousClock => receiveClock,
reset => reset,
asynchronousIn => gotTimeCode,
synchronizedOut => gotTimeCodeSynchronized
);
end Behavioral;
| gpl-3.0 | e9af0dcb0149cea9083760fc5dd7fbcd | 0.575751 | 4.609298 | false | false | false | false |
yishinli/emc2 | src/hal/drivers/mesa-hostmot2/firmware/src/uartx8.vhd | 1 | 8,985 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
-- http://www.mesanet.com
--
-- This program is is licensed under a disjunctive dual license giving you
-- the choice of one of the two following sets of free software/open source
-- licensing terms:
--
-- * GNU General Public License (GPL), version 2.0 or later
-- * 3-clause BSD License
--
--
-- The GNU GPL License:
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
--
--
-- The 3-clause BSD License:
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- * Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- * Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- * Neither the name of Mesa Electronics nor the names of its
-- contributors may be used to endorse or promote products
-- derived from this software without specific prior written
-- permission.
--
--
-- Disclaimer:
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
entity uartx8 is
Port ( clk : in std_logic;
ibus : in std_logic_vector(7 downto 0);
obus : out std_logic_vector(7 downto 0);
pushfifo : in std_logic;
loadbitratel : in std_logic;
loadbitrateh : in std_logic;
readbitratel : in std_logic;
readbitrateh : in std_logic;
clrfifo : in std_logic;
readfifocount : in std_logic;
loadmode : in std_logic;
readmode : in std_logic;
fifoempty : out std_logic;
txen : in std_logic;
drven : out std_logic;
txdata : out std_logic
);
end uartx8;
architecture Behavioral of uartx8 is
-- FIFO related signals
signal pushdata: std_logic_vector(7 downto 0);
signal popadd: std_logic_vector(3 downto 0) := x"f";
signal popdata: std_logic_vector(7 downto 0);
signal datacounter: std_logic_vector(4 downto 0);
signal push: std_logic;
signal pop: std_logic;
signal clear: std_logic;
signal lfifoempty: std_logic;
signal fifohasdata: std_logic;
-- uart interface related signals
constant DDSWidth : integer := 16;
signal BitrateDDSReg : std_logic_vector(DDSWidth-1 downto 0);
signal BitrateDDSAccum : std_logic_vector(DDSWidth-1 downto 0);
alias DDSMSB : std_logic is BitrateDDSAccum(15);
signal OldDDSMSB: std_logic;
signal SampleTime: std_logic;
signal BitCount : std_logic_vector(3 downto 0);
signal SReg: std_logic_vector(10 downto 0);
alias SregData: std_logic_vector(7 downto 0)is SReg(9 downto 2);
alias StartBit: std_logic is Sreg(1);
alias StopBit: std_logic is Sreg(10);
alias IdleBit: std_logic is Sreg(0);
signal Go: std_logic := '0';
signal ModeReg: std_logic_vector(5 downto 0);
alias DriveEnDelay: std_logic_vector(3 downto 0) is ModeReg (3 downto 0);
alias DriveEnAuto: std_logic is ModeReg(4);
alias DriveEnBit: std_logic is ModeReg(5);
signal DriveEnable: std_logic;
signal DriveEnHold: std_logic;
signal WaitingForDrive: std_logic;
signal DriveDelayCount: std_logic_vector(3 downto 0);
component SRL16E
--
generic (INIT : bit_vector);
--
port (D : in std_logic;
CE : in std_logic;
CLK : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
Q : out std_logic);
end component;
begin
fifosrl: for i in 0 to 7 generate
asr16e: SRL16E generic map (x"0000") port map(
D => pushdata(i),
CE => push,
CLK => clk,
A0 => popadd(0),
A1 => popadd(1),
A2 => popadd(2),
A3 => popadd(3),
Q => popdata(i)
);
end generate;
afifo: process (clk,popdata,datacounter)
begin
if rising_edge(clk) then
if push = '1' and pop = '0' and datacounter /= 16 then -- a push
-- always increment the data counter if not full
datacounter <= datacounter +1;
popadd <= popadd +1; -- popadd must follow data down shiftreg
end if;
if (pop = '1') and (push = '0') and (lfifoempty = '0') then -- a pop
-- always decrement the data counter if not empty
datacounter <= datacounter -1;
popadd <= popadd -1;
end if;
-- if both push and pop are asserted we dont change either counter
if clear = '1' then -- a clear fifo
popadd <= (others => '1');
datacounter <= (others => '0');
end if;
end if; -- clk rise
if datacounter = 0 then
lfifoempty <= '1';
else
lfifoempty <= '0';
end if;
fifohasdata <= not lfifoempty;
end process afifo;
asimpleuarttx: process (clk)
begin
if rising_edge(clk) then
if Go = '1' then
BitRateDDSAccum <= BitRateDDSAccum - BitRateDDSReg;
if SampleTime = '1' then
SReg <= '1' & SReg(10 downto 1); -- right shift = LSb first
BitCount <= BitCount -1;
if BitCount = 0 then
Go <= '0';
end if;
end if;
else
BitRateDDSAccum <= (others => '0');
end if;
if pop = '1' then -- just one clock
pop <= '0';
end if;
if Go = '0' then
StartBit <= '0';
StopBit <= '1';
IdleBit <= '1';
BitCount <= "1010";
if fifohasdata = '1' and pop = '0' and txen = '1' and DriveEnHold = '0' then -- UART SReg not busy and we have data
pop <= '1';
SRegData <= popdata;
Go <= '1';
end if;
end if;
if DriveEnable = '0' then
DriveDelayCount <= DriveEnDelay;
else
if WaitingForDrive = '1' then
DriveDelayCount <= DriveDelayCount -1;
end if;
end if;
OldDDSMSB <= DDSMSB;
if loadbitratel = '1' then
BitRateDDSReg(7 downto 0) <= ibus;
end if;
if loadbitrateh = '1' then
BitRateDDSReg(15 downto 8) <= ibus;
end if;
if loadmode = '1' then
ModeReg<= ibus(5 downto 0);
end if;
end if; -- clk
SampleTime <= (not OldDDSMSB) and DDSMSB;
pushdata <= ibus;
push <= pushfifo;
clear <= clrfifo;
if DriveDelayCount /= 0 then
WaitingForDrive <= '1';
else
WaitingForDrive <= '0';
end if;
DriveEnHold <= (not DriveEnable) or WaitingForDrive;
if DriveEnAuto = '1' then
DriveEnable <= (Go or Pop or FIFOHasData) and txen; -- note that this means txen should never be removed -- when there is data to xmit
else -- in the middle of a block transmission
DriveEnable <= DriveEnBit;
end if;
obus <= (others => 'Z');
if readfifocount = '1' then
obus(4 downto 0) <= datacounter;
obus(7 downto 5) <= (others => '0');
end if;
if readbitratel = '1' then
obus <= BitRateDDSReg(7 downto 0);
end if;
if readbitrateh = '1' then
obus <= BitRateDDSReg(15 downto 8);
end if;
if readmode = '1' then
obus(5 downto 0) <= ModeReg;
obus(6) <= txen;
obus(7) <= Go or Pop or FIFOHasData;
end if;
txdata<= SReg(0);
fifoempty <= lfifoempty;
drven <= DriveEnable;
end process asimpleuarttx;
end Behavioral;
| lgpl-2.1 | fac7f007d546425005f74c2d2117459a | 0.629048 | 3.380361 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/leon3v3/grlfpwx.vhd | 1 | 4,556 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: grlfpwx
-- File: grlfpwx.vhd
-- Author: Edvin Catovic - Gaisler Research
-- Description: GRFPU LITE / GRFPC wrapper and FP register file
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library gaisler;
use gaisler.leon3.all;
use gaisler.libleon3.all;
use gaisler.libfpu.all;
library techmap;
use techmap.gencomp.all;
use techmap.netcomp.all;
entity grlfpwx is
generic (
tech : integer := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer range 0 to 1 := 0;
disas : integer range 0 to 2 := 0;
pipe : integer := 0;
netlist : integer := 0;
index : integer := 0;
scantest : integer := 0);
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi : in fpc_in_type;
cpo : out fpc_out_type;
testin : in std_logic_vector(TESTIN_WIDTH-1 downto 0)
);
end;
architecture rtl of grlfpwx is
signal rfi1, rfi2 : fp_rf_in_type;
signal rfo1, rfo2 : fp_rf_out_type;
begin
x1 : if true generate
grlfpw0 : grlfpw_net generic map (tech, pclow, dsu, disas, pipe)
port map (
rst ,
clk ,
holdn ,
cpi.flush ,
cpi.exack ,
cpi.a_rs1 ,
cpi.d.pc ,
cpi.d.inst ,
cpi.d.cnt ,
cpi.d.trap ,
cpi.d.annul ,
cpi.d.pv ,
cpi.a.pc ,
cpi.a.inst ,
cpi.a.cnt ,
cpi.a.trap ,
cpi.a.annul ,
cpi.a.pv ,
cpi.e.pc ,
cpi.e.inst ,
cpi.e.cnt ,
cpi.e.trap ,
cpi.e.annul ,
cpi.e.pv ,
cpi.m.pc ,
cpi.m.inst ,
cpi.m.cnt ,
cpi.m.trap ,
cpi.m.annul ,
cpi.m.pv ,
cpi.x.pc ,
cpi.x.inst ,
cpi.x.cnt ,
cpi.x.trap ,
cpi.x.annul ,
cpi.x.pv ,
cpi.lddata ,
cpi.dbg.enable ,
cpi.dbg.write ,
cpi.dbg.fsr ,
cpi.dbg.addr ,
cpi.dbg.data ,
cpo.data ,
cpo.exc ,
cpo.cc ,
cpo.ccv ,
cpo.ldlock ,
cpo.holdn ,
cpo.dbg.data ,
rfi1.rd1addr ,
rfi1.rd2addr ,
rfi1.wraddr ,
rfi1.wrdata ,
rfi1.ren1 ,
rfi1.ren2 ,
rfi1.wren ,
rfi2.rd1addr ,
rfi2.rd2addr ,
rfi2.wraddr ,
rfi2.wrdata ,
rfi2.ren1 ,
rfi2.ren2 ,
rfi2.wren ,
rfo1.data1 ,
rfo1.data2 ,
rfo2.data1 ,
rfo2.data2
);
end generate;
rf1 : regfile_3p_l3 generic map (tech, 4, 32, 1, 16,
scantest
)
port map (clk, rfi1.wraddr, rfi1.wrdata, rfi1.wren, clk, rfi1.rd1addr,
rfi1.ren1, rfo1.data1, rfi1.rd2addr, rfi1.ren2, rfo1.data2,
testin
);
rf2 : regfile_3p_l3 generic map (tech, 4, 32, 1, 16,
scantest
)
port map (clk, rfi2.wraddr, rfi2.wrdata, rfi2.wren, clk, rfi2.rd1addr,
rfi2.ren1, rfo2.data1, rfi2.rd2addr, rfi2.ren2, rfo2.data2,
testin
);
end;
| gpl-3.0 | 649af01883beb0126e7f6174e224d730 | 0.494074 | 3.472561 | false | false | false | false |
yishinli/emc2 | src/hal/drivers/mesa-hostmot2/firmware/src/idrom.vhd | 1 | 13,048 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
-- http://www.mesanet.com
--
-- This program is is licensed under a disjunctive dual license giving you
-- the choice of one of the two following sets of free software/open source
-- licensing terms:
--
-- * GNU General Public License (GPL), version 2.0 or later
-- * 3-clause BSD License
--
--
-- The GNU GPL License:
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
--
--
-- The 3-clause BSD License:
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- * Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- * Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- * Neither the name of Mesa Electronics nor the names of its
-- contributors may be used to endorse or promote products
-- derived from this software without specific prior written
-- permission.
--
--
-- Disclaimer:
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
use work.IDROMConst.all;
entity IDROM is
generic (
idromtype : integer;
offsettomodules : integer;
offsettopindesc : integer;
boardnamelow : std_logic_vector(31 downto 0);
boardnamehigh : std_logic_vector(31 downto 0);
fpgasize : integer;
fpgapins : integer;
ioports : integer;
iowidth : integer;
portwidth : integer;
clocklow : integer;
clockhigh : integer;
inststride0 : integer;
inststride1 : integer;
regstride0 : integer;
regstride1 : integer;
pindesc : PinDescType;
moduleid : moduleIDType );
port (
clk : in std_logic;
we : in std_logic;
re : in std_logic;
radd : in std_logic_vector(7 downto 0);
wadd : in std_logic_vector(7 downto 0);
din : in std_logic_vector(31 downto 0);
dout : out std_logic_vector(31 downto 0)
);
end IDROM;
architecture syn of IDROM is -- 256 x 32 spram
constant empty : std_logic_vector(31 downto 0) := x"00000000";
type ram_type is array (0 to 255) of std_logic_vector(31 downto 0);
signal RAM : ram_type :=
(
CONV_STD_LOGIC_VECTOR(idromtype,32),
CONV_STD_LOGIC_VECTOR(offsettomodules,32),
CONV_STD_LOGIC_VECTOR(offsettopindesc,32),
boardnamelow,
boardnamehigh,
CONV_STD_LOGIC_VECTOR(fpgasize,32),
CONV_STD_LOGIC_VECTOR(fpgapins,32),
CONV_STD_LOGIC_VECTOR(ioports,32),
CONV_STD_LOGIC_VECTOR(iowidth,32),
CONV_STD_LOGIC_VECTOR(portwidth,32),
CONV_STD_LOGIC_VECTOR(clocklow,32),
CONV_STD_LOGIC_VECTOR(clockhigh,32),
CONV_STD_LOGIC_VECTOR(inststride0,32),
CONV_STD_LOGIC_VECTOR(inststride1,32),
CONV_STD_LOGIC_VECTOR(regstride0,32),
CONV_STD_LOGIC_VECTOR(regstride1,32),
-- module IDs starting at doubleword 16
-- 32 module id records = 96 doubles total
moduleid(0).NumInstances&moduleid(0).Clock&moduleid(0).Version&moduleid(0).GTag,
moduleid(0).Strides&moduleid(0).NumRegisters&moduleid(0).BaseAddr,
moduleid(0).MultRegs,
moduleid(1).NumInstances&moduleid(1).Clock&moduleid(1).Version&moduleid(1).GTag,
moduleid(1).Strides&moduleid(1).NumRegisters&moduleid(1).BaseAddr,
moduleid(1).MultRegs,
moduleid(2).NumInstances&moduleid(2).Clock&moduleid(2).Version&moduleid(2).GTag,
moduleid(2).Strides&moduleid(2).NumRegisters&moduleid(2).BaseAddr,
moduleid(2).MultRegs,
moduleid(3).NumInstances&moduleid(3).Clock&moduleid(3).Version&moduleid(3).GTag,
moduleid(3).Strides&moduleid(3).NumRegisters&moduleid(3).BaseAddr,
moduleid(3).MultRegs,
moduleid(4).NumInstances&moduleid(4).Clock&moduleid(4).Version&moduleid(4).GTag,
moduleid(4).Strides&moduleid(4).NumRegisters&moduleid(4).BaseAddr,
moduleid(4).MultRegs,
moduleid(5).NumInstances&moduleid(5).Clock&moduleid(5).Version&moduleid(5).GTag,
moduleid(5).Strides&moduleid(5).NumRegisters&moduleid(5).BaseAddr,
moduleid(5).MultRegs,
moduleid(6).NumInstances&moduleid(6).Clock&moduleid(6).Version&moduleid(6).GTag,
moduleid(6).Strides&moduleid(6).NumRegisters&moduleid(6).BaseAddr,
moduleid(6).MultRegs,
moduleid(7).NumInstances&moduleid(7).Clock&moduleid(7).Version&moduleid(7).GTag,
moduleid(7).Strides&moduleid(7).NumRegisters&moduleid(7).BaseAddr,
moduleid(7).MultRegs,
moduleid(8).NumInstances&moduleid(8).Clock&moduleid(8).Version&moduleid(8).GTag,
moduleid(8).Strides&moduleid(8).NumRegisters&moduleid(8).BaseAddr,
moduleid(8).MultRegs,
moduleid(9).NumInstances&moduleid(9).Clock&moduleid(9).Version&moduleid(9).GTag,
moduleid(9).Strides&moduleid(9).NumRegisters&moduleid(9).BaseAddr,
moduleid(9).MultRegs,
moduleid(10).NumInstances&moduleid(10).Clock&moduleid(10).Version&moduleid(10).GTag,
moduleid(10).Strides&moduleid(10).NumRegisters&moduleid(10).BaseAddr,
moduleid(10).MultRegs,
moduleid(11).NumInstances&moduleid(11).Clock&moduleid(11).Version&moduleid(11).GTag,
moduleid(11).Strides&moduleid(11).NumRegisters&moduleid(11).BaseAddr,
moduleid(11).MultRegs,
moduleid(12).NumInstances&moduleid(12).Clock&moduleid(12).Version&moduleid(12).GTag,
moduleid(12).Strides&moduleid(12).NumRegisters&moduleid(12).BaseAddr,
moduleid(12).MultRegs,
moduleid(13).NumInstances&moduleid(13).Clock&moduleid(13).Version&moduleid(13).GTag,
moduleid(13).Strides&moduleid(13).NumRegisters&moduleid(13).BaseAddr,
moduleid(13).MultRegs,
moduleid(14).NumInstances&moduleid(14).Clock&moduleid(14).Version&moduleid(14).GTag,
moduleid(14).Strides&moduleid(14).NumRegisters&moduleid(14).BaseAddr,
moduleid(14).MultRegs,
moduleid(15).NumInstances&moduleid(15).Clock&moduleid(15).Version&moduleid(15).GTag,
moduleid(15).Strides&moduleid(15).NumRegisters&moduleid(15).BaseAddr,
moduleid(15).MultRegs,
moduleid(16).NumInstances&moduleid(16).Clock&moduleid(16).Version&moduleid(16).GTag,
moduleid(16).Strides&moduleid(16).NumRegisters&moduleid(16).BaseAddr,
moduleid(16).MultRegs,
moduleid(17).NumInstances&moduleid(17).Clock&moduleid(17).Version&moduleid(17).GTag,
moduleid(17).Strides&moduleid(17).NumRegisters&moduleid(17).BaseAddr,
moduleid(17).MultRegs,
moduleid(18).NumInstances&moduleid(18).Clock&moduleid(18).Version&moduleid(18).GTag,
moduleid(18).Strides&moduleid(18).NumRegisters&moduleid(18).BaseAddr,
moduleid(18).MultRegs,
moduleid(19).NumInstances&moduleid(19).Clock&moduleid(19).Version&moduleid(19).GTag,
moduleid(19).Strides&moduleid(19).NumRegisters&moduleid(19).BaseAddr,
moduleid(19).MultRegs,
moduleid(20).NumInstances&moduleid(20).Clock&moduleid(20).Version&moduleid(20).GTag,
moduleid(20).Strides&moduleid(20).NumRegisters&moduleid(20).BaseAddr,
moduleid(20).MultRegs,
moduleid(21).NumInstances&moduleid(21).Clock&moduleid(21).Version&moduleid(21).GTag,
moduleid(21).Strides&moduleid(21).NumRegisters&moduleid(21).BaseAddr,
moduleid(21).MultRegs,
moduleid(22).NumInstances&moduleid(22).Clock&moduleid(22).Version&moduleid(22).GTag,
moduleid(22).Strides&moduleid(22).NumRegisters&moduleid(22).BaseAddr,
moduleid(22).MultRegs,
moduleid(23).NumInstances&moduleid(23).Clock&moduleid(23).Version&moduleid(23).GTag,
moduleid(23).Strides&moduleid(23).NumRegisters&moduleid(23).BaseAddr,
moduleid(23).MultRegs,
moduleid(24).NumInstances&moduleid(24).Clock&moduleid(24).Version&moduleid(24).GTag,
moduleid(24).Strides&moduleid(24).NumRegisters&moduleid(24).BaseAddr,
moduleid(24).MultRegs,
moduleid(25).NumInstances&moduleid(25).Clock&moduleid(25).Version&moduleid(25).GTag,
moduleid(25).Strides&moduleid(25).NumRegisters&moduleid(25).BaseAddr,
moduleid(25).MultRegs,
moduleid(26).NumInstances&moduleid(26).Clock&moduleid(26).Version&moduleid(26).GTag,
moduleid(26).Strides&moduleid(26).NumRegisters&moduleid(26).BaseAddr,
moduleid(26).MultRegs,
moduleid(27).NumInstances&moduleid(27).Clock&moduleid(27).Version&moduleid(27).GTag,
moduleid(27).Strides&moduleid(27).NumRegisters&moduleid(27).BaseAddr,
moduleid(27).MultRegs,
moduleid(28).NumInstances&moduleid(28).Clock&moduleid(28).Version&moduleid(28).GTag,
moduleid(28).Strides&moduleid(28).NumRegisters&moduleid(28).BaseAddr,
moduleid(28).MultRegs,
moduleid(29).NumInstances&moduleid(29).Clock&moduleid(29).Version&moduleid(29).GTag,
moduleid(29).Strides&moduleid(29).NumRegisters&moduleid(29).BaseAddr,
moduleid(29).MultRegs,
moduleid(30).NumInstances&moduleid(30).Clock&moduleid(30).Version&moduleid(30).GTag,
moduleid(30).Strides&moduleid(30).NumRegisters&moduleid(30).BaseAddr,
moduleid(30).MultRegs,
moduleid(31).NumInstances&moduleid(31).Clock&moduleid(31).Version&moduleid(31).GTag,
moduleid(31).Strides&moduleid(31).NumRegisters&moduleid(31).BaseAddr,
moduleid(31).MultRegs,
-- 16 empty doublewords from 112 through 127
-- may eventually delete this to allow 144 pin cards
empty,empty,empty,empty,empty,empty,empty,empty,
empty,empty,empty,empty,empty,empty,empty,empty,
-- pindesc starting at doubleword 128
pindesc(0),pindesc(1),pindesc(2),pindesc(3),pindesc(4),pindesc(5),pindesc(6),pindesc(7),
pindesc(8),pindesc(9),pindesc(10),pindesc(11),pindesc(12),pindesc(13),pindesc(14),pindesc(15),
pindesc(16),pindesc(17),pindesc(18),pindesc(19),pindesc(20),pindesc(21),pindesc(22),pindesc(23),
pindesc(24),pindesc(25),pindesc(26),pindesc(27),pindesc(28),pindesc(29),pindesc(30),pindesc(31),
pindesc(32),pindesc(33),pindesc(34),pindesc(35),pindesc(36),pindesc(37),pindesc(38),pindesc(39),
pindesc(40),pindesc(41),pindesc(42),pindesc(43),pindesc(44),pindesc(45),pindesc(46),pindesc(47),
pindesc(48),pindesc(49),pindesc(50),pindesc(51),pindesc(52),pindesc(53),pindesc(54),pindesc(55),
pindesc(56),pindesc(57),pindesc(58),pindesc(59),pindesc(60),pindesc(61),pindesc(62),pindesc(63),
pindesc(64),pindesc(65),pindesc(66),pindesc(67),pindesc(68),pindesc(69),pindesc(70),pindesc(71),
pindesc(72),pindesc(73),pindesc(74),pindesc(75),pindesc(76),pindesc(77),pindesc(78),pindesc(79),
pindesc(80),pindesc(81),pindesc(82),pindesc(83),pindesc(84),pindesc(85),pindesc(86),pindesc(87),
pindesc(88),pindesc(89),pindesc(90),pindesc(91),pindesc(92),pindesc(93),pindesc(94),pindesc(95),
pindesc(96),pindesc(97),pindesc(98),pindesc(99),pindesc(100),pindesc(101),pindesc(102),pindesc(103),
pindesc(104),pindesc(105),pindesc(106),pindesc(107),pindesc(108),pindesc(109),pindesc(110),pindesc(111),
pindesc(112),pindesc(113),pindesc(114),pindesc(115),pindesc(116),pindesc(117),pindesc(118),pindesc(119),
pindesc(120),pindesc(121),pindesc(122),pindesc(123),pindesc(124),pindesc(124),pindesc(126),pindesc(127)
);
signal dradd : std_logic_vector(7 downto 0);
signal readout : std_logic_vector(31 downto 0);
begin
process (clk,RAM, re)
begin
if (clk'event and clk = '1') then
if (we = '1') then
RAM(conv_integer(wadd)) <= din;
end if;
dradd <= radd;
end if;
readout <= RAM(conv_integer(dradd));
dout <= (others => 'Z');
if re = '1' then
dout <= readout;
end if;
end process;
end;
| lgpl-2.1 | 6007bbfd72e97a7f4177e1a75aa42761 | 0.717964 | 2.886087 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-digilent-atlys/testbench.vhd | 1 | 8,503 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
--
-- Modified by Joris van Rantwijk to support Digilent Atlys board.
-- Modified by Aeroflex Gaisler
--
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
use work.debug.all;
library grlib;
use grlib.stdlib.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20 -- system clock period
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal clk : std_logic := '0';
signal rst : std_logic := '0'; -- Reset
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
-- DDR2 memory
signal ddr_clk : std_logic;
signal ddr_clkb : std_logic;
signal ddr_cke : std_logic;
signal ddr_we : std_ulogic; -- write enable
signal ddr_ras : std_ulogic; -- ras
signal ddr_cas : std_ulogic; -- cas
signal ddr_dm : std_logic_vector(1 downto 0); -- dm
signal ddr_dqs : std_logic_vector(1 downto 0); -- dqs
signal ddr_dqsn : std_logic_vector(1 downto 0); -- dqsn
signal ddr_ad : std_logic_vector(12 downto 0); -- address
signal ddr_ba : std_logic_vector(2 downto 0); -- bank address
signal ddr_dq : std_logic_vector(15 downto 0); -- data
signal ddr_dq2 : std_logic_vector(15 downto 0); -- data
signal ddr_odt : std_logic;
signal ddr_rzq : std_logic;
signal ddr_zio : std_logic;
signal ddr_csb : std_ulogic := '0';
signal txd1, rxd1 : std_logic;
signal genio : std_logic_vector(7 downto 0) := (others => '0');
signal switch : std_logic_vector(7 downto 0) := (others => '0');
signal led : std_logic_vector(7 downto 0);
signal button : std_logic_vector(4 downto 0) := (others => '0');
-- Ethernet
signal erx_clk : std_ulogic;
signal erxd : std_logic_vector(7 downto 0);
signal erx_dv : std_ulogic;
signal erx_er : std_ulogic;
signal erx_col : std_ulogic;
signal erx_crs : std_ulogic;
signal etx_clk : std_ulogic;
signal etxd : std_logic_vector(7 downto 0);
signal etx_en : std_ulogic;
signal etx_er : std_ulogic;
signal egtxclk : std_ulogic;
signal emdc : std_ulogic;
signal emdio : std_logic;
signal emdint : std_ulogic;
signal ps2clk : std_logic_vector(1 downto 0);
signal ps2data : std_logic_vector(1 downto 0);
-- SPI flash
signal spi_sel_n : std_logic;
signal spi_clk : std_ulogic;
signal spi_mosi : std_logic;
signal spi_miso : std_logic;
signal errorn : std_logic;
begin
-- system clock
clk <= (not clk) after clkperiod * 0.5 ns;
-- reset
rst <= '0', '1' after 2500 ns;
rxd1 <= 'H';
ps2clk <= "HH"; ps2data <= "HH";
-- enable DSU
switch(7) <= '1';
switch(6) <= '0';
cpu : entity work.leon3mp
generic map (
fabtech => fabtech,
memtech => memtech,
padtech => padtech,
clktech => clktech,
disas => disas,
dbguart => dbguart,
pclow => pclow )
port map (
resetn => rst,
clk => clk,
ddr_clk => ddr_clk,
ddr_clkb => ddr_clkb,
ddr_cke => ddr_cke,
ddr_odt => ddr_odt,
ddr_we => ddr_we,
ddr_ras => ddr_ras,
ddr_cas => ddr_cas,
ddr_dm => ddr_dm,
ddr_dqs => ddr_dqs,
ddr_dqsn => ddr_dqsn,
ddr_ad => ddr_ad,
ddr_ba => ddr_ba,
ddr_dq => ddr_dq,
ddr_rzq => ddr_rzq,
ddr_zio => ddr_zio,
txd1 => txd1,
rxd1 => rxd1,
pmoda => genio,
switch => switch,
led => led,
button => button,
erx_clk => erx_clk,
erxd => erxd,
erx_dv => erx_dv,
erx_er => erx_er,
erx_col => erx_col,
erx_crs => erx_crs,
etx_clk => etx_clk,
etxd => etxd,
etx_en => etx_en,
etx_er => etx_er,
erst => open,
egtxclk => egtxclk,
emdc => emdc,
emdio => emdio,
emdint => emdint,
kbd_clk => ps2clk(0),
kbd_data => ps2data(0),
mou_clk => ps2clk(1),
mou_data => ps2data(1),
spi_sel_n => spi_sel_n,
spi_clk => spi_clk,
spi_miso => spi_miso,
spi_mosi => spi_mosi,
tmdstx_clk_p => open,
tmdstx_clk_n => open,
tmdstx_dat_p => open,
tmdstx_dat_n => open );
prom0 : spi_flash
generic map (
ftype => 4,
debug => 0,
fname => promfile,
readcmd => CFG_SPIMCTRL_READCMD,
dummybyte => CFG_SPIMCTRL_DUMMYBYTE,
dualoutput => CFG_SPIMCTRL_DUALOUTPUT,
memoffset => CFG_SPIMCTRL_OFFSET)
port map (
sck => spi_clk,
di => spi_mosi,
do => spi_miso,
csn => spi_sel_n );
u1: ddr2ram
generic map (width => 16, abits => 13, babits => 3,
colbits => 10, rowbits => 13, implbanks => 8,
fname => sdramfile, speedbin => 1)
port map (ck => ddr_clk, ckn => ddr_clkb, cke => ddr_cke, csn => ddr_csb,
odt => ddr_odt, rasn => ddr_ras, casn => ddr_cas, wen => ddr_we,
dm => ddr_dm, ba => ddr_ba, a => ddr_ad,
dq => ddr_dq2, dqs => ddr_dqs, dqsn => ddr_dqsn);
ddr2delay0 : delay_wire
generic map(data_width => ddr_dq'length, delay_atob => 0.0, delay_btoa => 13.5)
port map(a => ddr_dq, b => ddr_dq2);
ps2devs: for i in 0 to 1 generate
ps2_device(ps2clk(i), ps2data(i));
end generate ps2devs;
phy0 : if (CFG_GRETH = 1) generate
emdio <= 'H';
p0: phy
generic map (base1000_t_fd => 0, base1000_t_hd => 0, address => 7)
port map (rst, emdio, etx_clk, erx_clk, erxd, erx_dv,
erx_er, erx_col, erx_crs, etxd, etx_en, etx_er, emdc, egtxclk);
end generate;
-- Monitor error indication.
errorn <= not led(7);
iuerr: process
begin
wait for 5000 ns;
if to_x01(errorn) = '1' then wait on errorn; end if;
assert (to_x01(errorn) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
-- Write serial port output to stdout.
--uart0: process
-- constant bit_interval : time := 1 sec / 38400.0;
-- variable d : std_logic_vector(7 downto 0);
-- variable c : character;
-- variable lin : line;
--begin
-- rxc(txd1, d, bit_interval);
-- c := character'val(conv_integer(d));
-- if c = LF then
-- std.textio.writeline(output, lin);
-- elsif c /= CR then
-- std.textio.write(lin, c);
-- end if;
--end process;
end;
| gpl-3.0 | 7678b104d7f6ab04a734a5857247ca9a | 0.550629 | 3.443904 | false | false | false | false |
yishinli/emc2 | src/hal/drivers/mesa-hostmot2/firmware/src/pwmpdmgenh.vhd | 1 | 7,961 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
-- http://www.mesanet.com
--
-- This program is is licensed under a disjunctive dual license giving you
-- the choice of one of the two following sets of free software/open source
-- licensing terms:
--
-- * GNU General Public License (GPL), version 2.0 or later
-- * 3-clause BSD License
--
--
-- The GNU GPL License:
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
--
--
-- The 3-clause BSD License:
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- * Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- * Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- * Neither the name of Mesa Electronics nor the names of its
-- contributors may be used to endorse or promote products
-- derived from this software without specific prior written
-- permission.
--
--
-- Disclaimer:
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
entity pwmpdmgenh is
generic (
buswidth : integer;
refwidth : integer
);
port (
clk: in std_logic;
hclk: in std_logic;
refcount: in std_logic_vector (refwidth-1 downto 0);
ibus: in std_logic_vector (buswidth -1 downto 0);
loadpwmval: in std_logic;
pcrloadcmd: std_logic;
pdmrate : in std_logic;
pwmouta: out std_logic;
pwmoutb: out std_logic
);
end pwmpdmgenh;
architecture behavioral of pwmpdmgenh is
signal pwmval: std_logic_vector (refwidth-2 downto 0);
signal prepwmval: std_logic_vector (refwidth-2 downto 0);
signal fixedrefcount: std_logic_vector (refwidth-2 downto 0);
signal pdmaccum: std_logic_vector (refwidth-1 downto 0);
alias pdmbit: std_logic is pdmaccum(refwidth-1);
signal maskedrefcount: std_logic_vector (refwidth-2 downto 0);
signal pwm: std_logic;
signal dir: std_logic;
signal toggle: std_logic;
signal mask: std_logic_vector (refwidth-2 downto 0);
signal predir: std_logic;
signal premodereg: std_logic_vector(5 downto 0);
signal modereg: std_logic_vector(5 downto 0);
alias pwmwidth: std_logic_vector(1 downto 0) is modereg(1 downto 0);
alias pwmmode: std_logic is modereg(2);
alias pwmoutmode: std_logic_vector(1 downto 0) is modereg(4 downto 3);
alias doublebuf: std_logic is modereg(5);
signal loadpwmreq: std_logic;
signal oldloadpwmreq: std_logic;
signal olderloadpwmreq: std_logic;
signal loadpcrreq: std_logic;
signal oldloadpcrreq: std_logic;
signal olderloadpcrreq: std_logic;
signal oldtoggle: std_logic;
signal cyclestart: std_logic;
begin
apwmgen: process (clk,hclk,refcount,ibus,loadpwmval,pwmval,pwm,
fixedrefcount,mask,pwmmode,toggle,oldtoggle,
pwmwidth,olderloadpwmreq,olderloadpcrreq,
pwmoutmode,dir,pdmaccum
)
begin
if rising_edge(hclk) then
if pdmrate = '1' then
pdmaccum <= ('0'&pdmaccum(refwidth-2 downto 0)) + ('0'&pwmval);
end if;
if oldloadpwmreq = '1' and olderloadpwmreq = '1' then
pwmval <= prepwmval;
dir <= predir;
oldloadpwmreq <= '0';
end if;
if oldloadpcrreq = '1' and olderloadpcrreq ='1' then
modereg <= premodereg;
end if;
olderloadpwmreq <= oldloadpwmreq;
olderloadpcrreq <= oldloadpcrreq;
if (loadpwmreq and (cyclestart or (not doublebuf))) = '1' then
oldloadpwmreq <= '1';
end if;
-- oldloadpwmreq <= loadpwmreq and (cyclestartflag or (not doublebuf));
oldloadpcrreq <= loadpcrreq;
-- was combinatorial but now pipelined to meet 100 MHz timing
if (UNSIGNED(maskedrefcount) < UNSIGNED(pwmval)) then
pwm <= '1';
else
pwm <= '0';
end if;
case pwmmode is
when '0' => fixedrefcount <= refcount(refwidth-2 downto 0);
when '1' =>
if toggle = '1' then -- symmetrical mode
fixedrefcount <= (not refcount(refwidth-2 downto 0));
else
fixedrefcount <= refcount(refwidth-2 downto 0);
end if;
when others => null;
end case;
oldtoggle <= toggle;
end if; -- hclk
maskedrefcount <= fixedrefcount and mask;
if pwmmode = '1' then
cyclestart <= ((not toggle) and oldtoggle); -- falling edge of toggle sym mode
else
cyclestart <= toggle xor oldtoggle; -- both edges of toggle ramp mode
end if;
case pwmwidth is
when "00" =>
mask(refwidth-2 downto refwidth-4) <= "000";
mask(refwidth-5 downto 0) <= ( others => '1');
toggle <= refcount(refwidth-4);
when "01" =>
mask(refwidth-2 downto refwidth-3) <= "00";
mask(refwidth-4 downto 0) <= ( others => '1');
toggle <= refcount(refwidth-3);
when "10" =>
mask(refwidth-2) <= '0';
mask(refwidth-3 downto 0) <= ( others => '1');
toggle <= refcount(refwidth-2);
when "11" =>
mask <= (others => '1');
toggle <= refcount(refwidth-1);
when others => null;
end case;
if rising_edge(clk) then -- 33/48/50 mhz local bus clock
if loadpwmval = '1' then
prepwmval <= ibus((refwidth-2)+16 downto 16); -- Fixme! only works for buswidth 32
predir <= ibus(BusWidth -1);
loadpwmreq <= '1';
end if;
if pcrloadcmd = '1' then
premodereg <= ibus(5 downto 0);
loadpcrreq <= '1';
end if;
end if; -- clk
if olderloadpwmreq = '1' then -- asynchronous request clear, could use flancter but dont need async clear
loadpwmreq <= '0';
end if;
if olderloadpcrreq = '1' then -- asynchronous request clear ""
loadpcrreq <= '0';
end if;
case pwmoutmode is
when "00" =>
pwmouta <= pwm; -- normal sign magnitude
pwmoutb <= dir;
when "01" =>
pwmouta <= dir; -- reversed pwm/dir = locked antiphase
pwmoutb <= pwm;
when "10" =>
if dir = '1' then -- up/down mode
pwmouta <= pwm;
pwmoutb <= '0';
else
pwmouta <= '0';
pwmoutb <= pwm;
end if;
when "11" =>
pwmouta <= pdmbit;
pwmoutb <= dir;
when others => null;
end case;
-- pwmoutc <= ena;
end process;
end behavioral;
| lgpl-2.1 | 889edadd14327fd6029d3c2967ac7190 | 0.659339 | 3.386219 | false | false | false | false |
yishinli/emc2 | src/hal/drivers/mesa-hostmot2/firmware/src/bufferedspi.vhd | 1 | 12,832 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
-- http://www.mesanet.com
--
-- This program is is licensed under a disjunctive dual license giving you
-- the choice of one of the two following sets of free software/open source
-- licensing terms:
--
-- * GNU General Public License (GPL), version 2.0 or later
-- * 3-clause BSD License
--
--
-- The GNU GPL License:
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
--
--
-- The 3-clause BSD License:
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- * Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- * Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- * Neither the name of Mesa Electronics nor the names of its
-- contributors may be used to endorse or promote products
-- derived from this software without specific prior written
-- permission.
--
--
-- Disclaimer:
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
entity bufferedspi is
generic (
cswidth : integer := 4;
gatedcs : boolean
);
port (
clk : in std_logic;
ibus : in std_logic_vector(31 downto 0);
obus : out std_logic_vector(31 downto 0);
addr : in std_logic_vector(3 downto 0);
hostpush : in std_logic;
hostpop : in std_logic;
loadasend : in std_logic;
loaddesc : in std_logic;
clear : in std_logic;
readcount : in std_logic;
spiclk : out std_logic;
spiin : in std_logic;
spiout: out std_logic;
spiframe: out std_logic;
spicsout: out std_logic_vector(cswidth-1 downto 0)
);
end bufferedspi;
architecture behavioral of bufferedspi is
constant DivWidth: integer := 8;
-- spi interface related signals
signal RateDiv : std_logic_vector(DivWidth -1 downto 0);
signal ModeReg : std_logic_vector(31 downto 0);
signal LoadData : std_logic;
signal StartCycle : std_logic;
alias BitcountReg : std_logic_vector(5 downto 0) is ModeReg(5 downto 0);
alias CPOL : std_logic is ModeReg(6);
alias CPHA : std_logic is ModeReg(7);
alias RateDivReg : std_logic_vector(DivWidth -1 downto 0) is ModeReg(15 downto 8);
alias CSReg : std_logic_vector(cswidth -1 downto 0) is ModeReg(cswidth-1 +16 downto 16);
alias CSTimerReg : std_logic_vector(4 downto 0) is ModeReg(28 downto 24);
alias DontEcho : std_logic is ModeReg(31);
alias DontClearFrame : std_logic is ModeReg(30);
signal BitCount : std_logic_vector(5 downto 0);
signal ClockFF: std_logic;
signal SPISreg: std_logic_vector(31 downto 0);
signal LFrame: std_logic;
signal EFrame: std_logic;
signal Dav: std_logic;
signal SPIInLatch: std_logic;
signal FirstLeadingEdge: std_logic;
signal CSTimer: std_logic_vector(4 downto 0);
alias CSTimerDone: std_logic is CSTimer(4);
-- input FIFO related signals
signal ipopadd: std_logic_vector(3 downto 0) := x"f";
signal ipopdata: std_logic_vector(31 downto 0);
signal idatacounter: std_logic_vector(4 downto 0);
signal ipush: std_logic;
signal ififohasdata: std_logic;
-- output FIFO related signals
signal opushdata: std_logic_vector(35 downto 0);
signal opopadd: std_logic_vector(3 downto 0) := x"f";
signal opopdata: std_logic_vector(35 downto 0);
signal odatacounter: std_logic_vector(4 downto 0);
signal opop: std_logic;
signal ofifohasdata: std_logic;
-- autosend table related signals
signal autosenddata: std_logic_vector(35 downto 0);
signal autosendadd: std_logic_vector(3 downto 0);
signal autosendlength: std_logic_vector(3 downto 0);
-- channel descriptor related signals
signal desc: std_logic_vector(31 downto 0);
alias CSTimerFromDesc : std_logic_vector(4 downto 0) is desc(28 downto 24);
signal descptr: std_logic_vector(3 downto 0);
component SRL16E
--
generic (INIT : bit_vector);
--
port (D : in std_logic;
CE : in std_logic;
CLK : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
Q : out std_logic);
end component;
begin
ofifo: for i in 0 to 35 generate
asr16e: SRL16E generic map (x"0000") port map(
D => opushdata(i),
CE => hostpush,
CLK => clk,
A0 => opopadd(0),
A1 => opopadd(1),
A2 => opopadd(2),
A3 => opopadd(3),
Q => opopdata(i)
);
end generate;
ififo: for i in 0 to 31 generate
asr16e: SRL16E generic map (x"0000") port map(
D => SPISReg(i),
CE => ipush,
CLK => clk,
A0 => ipopadd(0),
A1 => ipopadd(1),
A2 => ipopadd(2),
A3 => ipopadd(3),
Q => ipopdata(i)
);
end generate;
autosendtable: for i in 0 to 35 generate
asr16e: SRL16E generic map (x"0000") port map(
D => opushdata(i),
CE => loadasend,
CLK => clk,
A0 => autosendadd(0),
A1 => autosendadd(1),
A2 => autosendadd(2),
A3 => autosendadd(3),
Q => autosenddata(i)
);
end generate;
chandesc: for i in 0 to 31 generate
asr16e: SRL16E generic map (x"0000") port map(
D => ibus(i),
CE => loaddesc,
CLK => clk,
A0 => descptr(0), -- the address that was pushed
A1 => descptr(1),
A2 => descptr(2),
A3 => descptr(3),
Q => desc(i)
);
end generate;
outfifo: process (clk,opopdata,odatacounter)
begin
if rising_edge(clk) then
if hostpush = '1' and opop = '0' then
if odatacounter /= 16 then -- a push
-- always increment the data counter if not full
odatacounter <= odatacounter +1;
opopadd <= opopadd +1; -- popadd must follow data down shiftreg
end if;
end if;
if (opop = '1') and (hostpush = '0') and (ofifohasdata = '1') then -- a pop
-- always decrement the data counter if not empty
odatacounter <= odatacounter -1;
opopadd <= opopadd -1;
end if;
-- if both push and pop are asserted we dont change either counter
if clear = '1' then -- a clear fifo
opopadd <= (others => '1');
odatacounter <= (others => '0');
end if;
end if; -- clk rise
if odatacounter = 0 then
ofifohasdata <= '0';
else
ofifohasdata <= '1';
end if;
end process outfifo;
infifo: process (clk,ipopdata,odatacounter)
begin
if rising_edge(clk) then
if ipush = '1' and hostpop = '0' then
if idatacounter /= 16 then -- a push
-- always increment the data counter if not full
idatacounter <= idatacounter +1;
ipopadd <= ipopadd +1; -- popadd must follow data down shiftreg
end if;
end if;
if (hostpop = '1') and (ipush = '0') and (ififohasdata = '1') then -- a pop
-- always decrement the data counter if not empty
idatacounter <= idatacounter -1;
ipopadd <= ipopadd -1;
end if;
-- if both push and pop are asserted we dont change either counter
if clear = '1' then -- a clear fifo
ipopadd <= (others => '1');
idatacounter <= (others => '0');
end if;
end if; -- clk rise
if idatacounter = 0 then
ififohasdata <= '0';
else
ififohasdata <= '1';
end if;
end process infifo;
aspiinterface: process (clk, ModeReg, ClockFF, LFrame,
SPISreg, BitcountReg, opopdata,
Dav,RateDivReg,addr, ibus,
hostpop, ipopdata, readcount,
idatacounter, odatacounter)
begin
if rising_edge(clk) then
if StartCycle = '0' and ofifohasdata = '1' and opop = '0'
and CSTimerDone= '1' and LFrame = '0' and Dav = '0' and loaddata = '0' then
-- if SPI shift register is free and we have data and CS setup/hold time is passed
ModeReg <= desc;
CSTimer <= CSTimerFromDesc; -- load early for pre-LFrame delay
StartCycle <= '1';
end if;
if StartCycle = '1' then
if CSTimerDone = '1' then
StartCycle <= '0';
LoadData <= '1';
end if;
end if;
if Dav = '1' then
if DontEcho = '0' then
ipush <= '1'; -- push SPI recieve data on ififo
end if;
Dav <= '0';
end if;
if ipush = '1' then
ipush <= '0';
end if;
if loaddata = '1' then
SPISreg <= opopdata(31 downto 0);
BitCount <= BitCountReg;
LFrame <= '1';
EFrame <= '1';
ClockFF <= '0';
FirstLeadingEdge <= '1';
RateDiv <= RateDivReg;
loaddata <= '0';
opop <= '1';
end if;
if opop = '1' then
opop <= '0';
end if;
if CSTimerDone = '0' then
CSTimer <= CSTimer -1;
end if;
if LFrame = '1' then -- single shift register SPI
if RateDiv = 0 then -- maybe update to dual later to allow
RateDiv <= RateDivReg; -- receive data skew adjustment
SPIInLatch <= spiin;
if ClockFF = '0' then
if BitCount(5) = '1' then
LFrame <= '0'; -- LFrame cleared 1/2 SPI clock after GO
if DontClearFrame = '0' then
EFrame <= '0'; -- EFrame only cleared if DontClearFrame is false
end if;
Dav <= '1';
CSTimer <= CSTimerReg; -- load timer from copy for post LFrame delay
else
ClockFF <= '1';
end if;
if CPHA = '1' and FirstLeadingEdge = '0' then -- shift out on leading edge for CPHA = 1 case
SPISreg <= SPISreg(30 downto 0) & (SPIInLatch);
end if;
FirstLeadingEdge <= '0';
else -- clock was high
ClockFF <= '0';
BitCount <= BitCount -1;
if CPHA = '0' then -- shift out on trailing edge for CPHA = 0 case
SPISreg <= SPISreg(30 downto 0) & (SPIInLatch);
end if;
end if;
else
RateDiv <= RateDiv -1;
end if;
end if;
if clear = '1' then
LFrame <= '0';
EFrame <= '0';
ClockFF <= '0';
Dav <= '0';
LoadData <= '0';
StartCycle <= '0';
CSTimerDone <= '0';
ipush <= '0';
end if;
end if; -- clk
opushdata <= addr & ibus; -- push address to select descriptor at far end of FIFO
descptr <= opopdata(35 downto 32); -- here!
obus <= (others => 'Z');
if hostpop = '1' then
obus <= ipopdata;
end if;
if readcount = '1' then
obus(4 downto 0) <= idatacounter;
obus(7 downto 5) <= (others => '0');
obus(12 downto 8) <= odatacounter;
obus(31 downto 13) <= (others => '0');
end if;
spiclk <= ClockFF xor CPOL;
spiframe <= not EFrame;
if gatedcs then -- gated/decoded CS/frame = DBSPI
for i in CSwidth-1 downto 0 loop
if i = conv_integer(CSReg) then
spicsout(i) <= not EFrame;
else
spicsout(i) <= '1';
end if;
end loop;
else
spicsout <= CSReg; -- decoded select with separate frame = BSPI
end if;
spiout <= SPISReg(conv_integer(BitCountReg(4 downto 0)));
end process aspiinterface;
end Behavioral;
| lgpl-2.1 | ab2ca2b0a1f3e8eca1d500f916bf998c | 0.615103 | 3.262649 | false | false | false | false |
yishinli/emc2 | src/hal/drivers/mesa-hostmot2/firmware/src/watchdog.vhd | 1 | 4,813 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
-- http://www.mesanet.com
--
-- This program is is licensed under a disjunctive dual license giving you
-- the choice of one of the two following sets of free software/open source
-- licensing terms:
--
-- * GNU General Public License (GPL), version 2.0 or later
-- * 3-clause BSD License
--
--
-- The GNU GPL License:
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
--
--
-- The 3-clause BSD License:
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- * Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- * Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- * Neither the name of Mesa Electronics nor the names of its
-- contributors may be used to endorse or promote products
-- derived from this software without specific prior written
-- permission.
--
--
-- Disclaimer:
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
entity watchdog is
generic (
buswidth : integer
);
port ( clk : in std_logic;
ibus : in std_logic_vector (buswidth-1 downto 0);
obus : out std_logic_vector (buswidth-1 downto 0);
loadtime : in std_logic;
readtime : in std_logic;
loadstatus: in std_logic;
readstatus: in std_logic;
cookie: in std_logic;
wdbite : out std_logic;
wdlatchedbite : out std_logic );
end watchdog;
architecture Behavioral of watchdog is
constant otherz: std_logic_vector (buswidth-2 downto 0) := (others => '0');
signal wdtimer: std_logic_vector (buswidth-1 downto 0) := '1' & otherz;
signal wdtime: std_logic_vector (buswidth-1 downto 0);
alias wdtimermsb: std_logic is wdtimer(buswidth-1);
signal wdstatus: std_logic := '0';
signal oldwdtimermsb: std_logic := '0';
begin
atimeout: process (clk,wdtimer,wdstatus,
readtime, readstatus,
wdtimermsb, oldwdtimermsb)
begin
if rising_edge(clk) then
oldwdtimermsb <= wdtimermsb;
if wdtimermsb /= '1' then
wdtimer <= wdtimer -1;
end if;
if loadtime = '1' then
wdtimer <= ibus;
wdtime <= ibus;
end if;
if cookie = '1' then
if ibus(buswidth-1 downto buswidth-8) = x"5A" then
wdtimer <= wdtime;
end if;
end if;
if loadstatus = '1' then
wdstatus <= ibus(0);
end if;
if wdtimermsb = '1' and oldwdtimermsb = '0' then -- edge triggered
wdbite <= '1';
wdstatus <= '1';
else
wdbite <= '0';
end if;
end if; -- clk
obus <= (others =>'Z');
if readtime = '1' then
obus <= wdtimer;
end if;
if readstatus = '1' then
obus(0) <= wdstatus;
obus(buswidth -1 downto 1) <= (others => '0');
end if;
wdlatchedbite <= wdstatus;
end process;
end Behavioral;
| lgpl-2.1 | 324d71c4af9197a7d7b90bc795fb603c | 0.658425 | 3.671243 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/techmap/maps/clkinv.vhd | 1 | 2,042 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: clkinv
-- File: clkinv.vhd
-- Author: Fredrik Ringhage - Aeroflex Gaisler Research
-- Description: SET protected inverters for clock tree
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.gencomp.all;
use work.allclkgen.all;
entity clkinv is
generic(tech : integer := 0);
port(
i : in std_ulogic;
o : out std_ulogic
);
end entity;
architecture rtl of clkinv is
begin
tec : if has_clkinv(tech) = 1 generate
saed : if (tech = saed32) generate
x0 : clkinv_saed32 port map (i => i, o => o);
end generate;
dar : if (tech = dare) generate
x0 : clkinv_dare port map (i => i, o => o);
end generate;
rhs : if (tech = rhs65) generate
x0 : clkinv_rhs65 port map (i => i, o => o);
end generate;
end generate;
gen : if has_clkinv(tech) = 0 generate
o <= not i;
end generate;
end architecture;
| gpl-3.0 | a86ce463f176433c0cc06ae4db7abed4 | 0.599412 | 4.019685 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/spi/spictrlx.vhd | 1 | 73,549 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: spictrlx
-- File: spictrlx.vhd
-- Author: Jan Andersson - Aeroflex Gaisler AB
-- Auto mode: J. Andersson, J. Ekergarn - Aeroflex Gaisler AB
-- Contact: [email protected]
--
-- Description: SPI controller with an interface compatible with MPC83xx SPI.
-- Relies on APB's wait state between back-to-back transfers.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.spi.all;
entity spictrlx is
generic (
rev : integer := 0; -- Core revision
fdepth : integer range 1 to 7 := 1; -- FIFO depth is 2^fdepth
slvselen : integer range 0 to 1 := 0; -- Slave select register enable
slvselsz : integer range 1 to 32 := 1; -- Number of slave select signals
oepol : integer range 0 to 1 := 0; -- Output enable polarity
odmode : integer range 0 to 1 := 0; -- Support open drain mode, only
-- set if pads are i/o or od pads.
automode : integer range 0 to 1 := 0; -- Enable automated transfer mode
acntbits : integer range 1 to 32 := 32; -- # Bits in am period counter
aslvsel : integer range 0 to 1 := 0; -- Automatic slave select
twen : integer range 0 to 1 := 1; -- Enable three wire mode
maxwlen : integer range 0 to 15 := 0; -- Maximum word length;
syncram : integer range 0 to 1 := 1; -- Use SYNCRAM for buffers
memtech : integer range 0 to NTECH := 0; -- Memory technology
ft : integer range 0 to 2 := 0; -- Fault-Tolerance
scantest : integer range 0 to 1 := 0; -- Scan test support
syncrst : integer range 0 to 1 := 0; -- Use only sync reset
automask0 : integer := 0; -- Mask 0 for automated transfers
automask1 : integer := 0; -- Mask 1 for automated transfers
automask2 : integer := 0; -- Mask 2 for automated transfers
automask3 : integer := 0; -- Mask 3 for automated transfers
ignore : integer range 0 to 1 := 0 -- Ignore samples
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- APB signals
apbi_psel : in std_ulogic;
apbi_penable : in std_ulogic;
apbi_paddr : in std_logic_vector(31 downto 0);
apbi_pwrite : in std_ulogic;
apbi_pwdata : in std_logic_vector(31 downto 0);
apbi_testen : in std_ulogic;
apbi_testrst : in std_ulogic;
apbi_scanen : in std_ulogic;
apbi_testoen : in std_ulogic;
apbo_prdata : out std_logic_vector(31 downto 0);
apbo_pirq : out std_ulogic;
-- SPI signals
spii_miso : in std_ulogic;
spii_mosi : in std_ulogic;
spii_sck : in std_ulogic;
spii_spisel : in std_ulogic;
spii_astart : in std_ulogic;
spii_cstart : in std_ulogic;
spii_ignore : in std_ulogic;
spio_miso : out std_ulogic;
spio_misooen : out std_ulogic;
spio_mosi : out std_ulogic;
spio_mosioen : out std_ulogic;
spio_sck : out std_ulogic;
spio_sckoen : out std_ulogic;
spio_enable : out std_ulogic;
spio_astart : out std_ulogic;
spio_aready : out std_ulogic;
slvsel : out std_logic_vector((slvselsz-1) downto 0)
);
attribute sync_set_reset of rstn : signal is "true";
end entity spictrlx;
architecture rtl of spictrlx is
-----------------------------------------------------------------------------
-- Constants
-----------------------------------------------------------------------------
constant OEPOL_LEVEL : std_ulogic := conv_std_logic(oepol = 1);
constant OUTPUT : std_ulogic := OEPOL_LEVEL; -- Enable outputs
constant INPUT : std_ulogic := not OEPOL_LEVEL; -- Tri-state outputs
constant FIFO_DEPTH : integer := 2**fdepth;
constant SLVSEL_EN : integer := slvselen;
constant SLVSEL_SZ : integer := slvselsz;
constant ASEL_EN : integer := aslvsel * slvselen;
constant AM_EN : integer := automode;
constant AM_CNT_BITS : integer := acntbits;
constant OD_EN : integer := odmode;
constant TW_EN : integer := twen;
constant MAX_WLEN : integer := maxwlen;
constant AM_MSK1_EN : boolean := AM_EN = 1 and FIFO_DEPTH > 32;
constant AM_MSK2_EN : boolean := AM_EN = 1 and FIFO_DEPTH > 64;
constant AM_MSK3_EN : boolean := AM_EN = 1 and FIFO_DEPTH > 96;
constant FIFO_BITS : integer := fdepth;
constant APBBITS : integer := 6+3*AM_EN;
constant APBH : integer := 2+APBBITS-1;
constant CAP_ADDR : std_logic_vector(APBH downto 2) := conv_std_logic_vector(0, APBBITS);
constant MODE_ADDR : std_logic_vector(APBH downto 2) := conv_std_logic_vector(8, APBBITS);
constant EVENT_ADDR : std_logic_vector(APBH downto 2) := conv_std_logic_vector(9, APBBITS);
constant MASK_ADDR : std_logic_vector(APBH downto 2) := conv_std_logic_vector(10, APBBITS);
constant COM_ADDR : std_logic_vector(APBH downto 2) := conv_std_logic_vector(11, APBBITS);
constant TD_ADDR : std_logic_vector(APBH downto 2) := conv_std_logic_vector(12, APBBITS);
constant RD_ADDR : std_logic_vector(APBH downto 2) := conv_std_logic_vector(13, APBBITS);
constant SLVSEL_ADDR : std_logic_vector(APBH downto 2) := conv_std_logic_vector(14, APBBITS);
constant ASEL_ADDR : std_logic_vector(APBH downto 2) := conv_std_logic_vector(15, APBBITS);
constant AMCFG_ADDR : std_logic_vector(APBH downto 2) := conv_std_logic_vector(16, APBBITS);
constant AMPER_ADDR : std_logic_vector(APBH downto 2) := conv_std_logic_vector(17, APBBITS);
constant AMMSK0_ADDR : std_logic_vector(10 downto 2) := "000010100"; -- 0x050
constant AMMSK1_ADDR : std_logic_vector(10 downto 2) := "000010101"; -- 0x054
constant AMMSK2_ADDR : std_logic_vector(10 downto 2) := "000010110"; -- 0x058
constant AMMSK3_ADDR : std_logic_vector(10 downto 2) := "000010111"; -- 0x05C
constant AMTX_ADDR : std_logic_vector(10 downto 2) := "010000000"; -- 0x200
constant AMRX_ADDR : std_logic_vector(10 downto 2) := "100000000"; -- 0x40
constant SPICTRLCAPREG : std_logic_vector(31 downto 0) :=
conv_std_logic_vector(SLVSEL_SZ, 8) & conv_std_logic_vector(MAX_WLEN, 4) &
conv_std_logic_vector(TW_EN, 1) & conv_std_logic_vector(AM_EN, 1) &
conv_std_logic_vector(ASEL_EN, 1) & conv_std_logic_vector(SLVSEL_EN, 1) &
conv_std_logic_vector(FIFO_DEPTH, 8) & conv_std_logic(syncram = 1) &
conv_std_logic_vector(ft, 2) & conv_std_logic_vector(rev, 5);
-- Returns an integer containing the maximum characted length - 1 as
-- restricted by the maxwlen VHDL generic.
function wlen return integer is
begin -- maxwlen
if MAX_WLEN = 0 then return 31; end if;
return MAX_WLEN;
end wlen;
constant PROG_AM_MASK : boolean :=
AM_EN = 1 and automask0 = 0 and (automask1 = 0 or FIFO_DEPTH <= 32) and
(automask2 = 0 or FIFO_DEPTH <= 64) and (automask3 = 0 or FIFO_DEPTH <= 96);
constant AM_MASK : std_logic_vector(127 downto 0) :=
conv_std_logic_vector_signed(automask3,32) &
conv_std_logic_vector_signed(automask2,32) &
conv_std_logic_vector_signed(automask1,32) &
conv_std_logic_vector_signed(automask0,32);
function check_discont_am_mask return boolean is
variable foundzero : boolean;
begin
if AM_EN = 0 then
return false;
elsif PROG_AM_MASK then
return true;
else
foundzero := false;
for i in 0 to FIFO_DEPTH-1 loop
if AM_MASK(i) = '0' then
foundzero := true;
else
if foundzero then
return true;
end if;
end if;
end loop;
return false;
end if;
end function;
constant DISCONT_AM_MASK : boolean := check_discont_am_mask;
function check_am_mask_end return integer is
variable ret : integer;
begin
ret := 0;
for i in 0 to FIFO_DEPTH-1 loop
if AM_MASK(i) = '1' then
ret := i;
end if;
end loop;
return ret;
end function;
constant AM_MASK_END : integer := check_am_mask_end;
-----------------------------------------------------------------------------
-- Types
-----------------------------------------------------------------------------
type spi_mode_rec is record -- SPI Mode register
amen : std_ulogic;
loopb : std_ulogic; -- loopback mode
cpol : std_ulogic; -- clock polarity
cpha : std_ulogic; -- clock phase
div16 : std_ulogic; -- Divide by 16
rev : std_ulogic; -- Reverse data mode
ms : std_ulogic; -- Master/slave
en : std_ulogic; -- Enable SPI
len : std_logic_vector(3 downto 0); -- Bits per character
pm : std_logic_vector(3 downto 0); -- Prescale modulus
tw : std_ulogic; -- 3-wire mode
asel : std_ulogic; -- Automatic slave select
fact : std_ulogic; -- PM multiplication factor
od : std_ulogic; -- Open drain mode
cg : std_logic_vector(4 downto 0); -- Clock gap
aseldel : std_logic_vector(1 downto 0); -- Asel delay
tac : std_ulogic;
tto : std_ulogic; -- Three-wire mode word order
igsel : std_ulogic; -- Ignore spisel input
cite : std_ulogic; -- Require SCK = CPOL for TIP end
end record;
type spi_em_rec is record -- SPI Event and Mask registers
tip : std_ulogic; -- Transfer in progress/Clock generated
lt : std_ulogic; -- last character transmitted
ov : std_ulogic; -- slave/master overrun
un : std_ulogic; -- slave/master underrun
mme : std_ulogic; -- Multiple-master error
ne : std_ulogic; -- Not empty
nf : std_ulogic; -- Not full
at : std_ulogic; -- Automated transfer
end record;
type spi_fifo is array (0 to (1-syncram)*(FIFO_DEPTH-1)) of std_logic_vector(wlen downto 0);
type spi_amcfg_rec is record -- AM config register
seq : std_ulogic; -- Data must always be read out of receive queue
strict : std_ulogic; -- Strict period
ovtb : std_ulogic; -- Perform transfer on OV
ovdb : std_ulogic; -- Skip data on OV
act : std_ulogic; -- Start immediately
eact : std_ulogic; -- Activate on external event
erpt : std_ulogic; -- Repeat on external event, not on period done
lock : std_ulogic; -- Lock receive registers when reading data
ecgc : std_ulogic; -- External clock gap control
end record;
type spi_am_rec is record -- Automode state
-- Register interface
cfg : spi_amcfg_rec; -- AM config register
per : std_logic_vector((AM_CNT_BITS-1)*AM_EN downto 0); -- AM period
--
active : std_ulogic; -- Auto mode active
lock : std_ulogic;
cnt : unsigned((AM_CNT_BITS-1)*AM_EN downto 0);
--
skipdata : std_ulogic;
rxfull : std_ulogic; -- AM RX FIFO is filled
rxfifo : spi_fifo; -- Receive data FIFO
txfifo : spi_fifo; -- Transmit data FIFO
rfreecnt : integer range 0 to FIFO_DEPTH; -- free rx fifo slots
mask : std_logic_vector(FIFO_DEPTH-1 downto 0);
mask_shdw : std_logic_vector(FIFO_DEPTH-1 downto 0);
unread : std_logic_vector(FIFO_DEPTH-1 downto 0);
at : std_ulogic;
--
rxread : std_ulogic;
txwrite : std_ulogic;
txread : std_ulogic;
apbaddr : std_logic_vector(FIFO_BITS-1 downto 0);
rxsel : std_ulogic;
end record;
-- Two stage synchronizers on each input coming from off-chip
type spi_in_local_type is record
miso : std_ulogic;
mosi : std_ulogic;
sck : std_ulogic;
spisel : std_ulogic;
end record;
type spi_in_array is array (1 downto 0) of spi_in_local_type;
-- Local spi out type without ssn
type spi_out_local_type is record
miso : std_ulogic;
misooen : std_ulogic;
mosi : std_ulogic;
mosioen : std_ulogic;
sck : std_ulogic;
sckoen : std_ulogic;
enable : std_ulogic;
astart : std_ulogic;
aready : std_ulogic;
end record;
-- Yet another subset of out type to make it easier for certain tools to
-- place registers near pads.
type spi_out_local_lb_type is record
mosi : std_ulogic;
sck : std_ulogic;
end record;
type spi_reg_type is record
-- SPI registers
mode : spi_mode_rec; -- Mode register
event : spi_em_rec; -- Event register
mask : spi_em_rec; -- Mask register
lst : std_ulogic; -- Only field on command register
td : std_logic_vector(31 downto 0); -- Transmit register
rd : std_logic_vector(31 downto 0); -- Receive register
slvsel : std_logic_vector((SLVSEL_SZ-1) downto 0); -- Slave select register
aslvsel : std_logic_vector((SLVSEL_SZ-1) downto 0); -- Automatic slave select
--
uf : std_ulogic; -- Slave in underflow condition
ov : std_ulogic; -- Receive overflow condition
td_occ : std_ulogic; -- Transmit register occupied
rd_free : std_ulogic; -- Receive register free (empty)
txfifo : spi_fifo; -- Transmit data FIFO
rxfifo : spi_fifo; -- Receive data FIFO
rxd : std_logic_vector(wlen downto 0); -- Receive shift register
txd : std_logic_vector(wlen downto 0); -- Transmit shift register
txdupd : std_ulogic; -- Update txd
txdbyp : std_ulogic; -- txd update bypass
toggle : std_ulogic; -- SCK has toggled
samp : std_ulogic; -- Sample
chng : std_ulogic; -- Change
psck : std_ulogic; -- Previous value of SC
twdir : std_ulogic; -- Direction in 3-wire mode
syncsamp : std_logic_vector(1 downto 0); -- Sample synchronized input
incrdli : std_ulogic;
rxdone : std_ulogic;
rxdone2 : std_ulogic;
running : std_ulogic;
ov2 : std_ulogic;
-- counters
tfreecnt : integer range 0 to FIFO_DEPTH; -- free td fifo slots
rfreecnt : integer range 0 to FIFO_DEPTH; -- free td fifo slots
tdfi : std_logic_vector(fdepth-1 downto 0); -- First tx queue element
rdfi : std_logic_vector(fdepth-1 downto 0); -- First rx queue element
tdli : std_logic_vector(fdepth-1 downto 0); -- Last tx queue element
rdli : std_logic_vector(fdepth-1 downto 0); -- Last rx queue element
rbitcnt : std_logic_vector(log2(wlen+1)-1 downto 0); -- Current receive bit
tbitcnt : std_logic_vector(log2(wlen+1)-1 downto 0); -- Current transmit bit
divcnt : unsigned(9 downto 0); -- Clock scaler
cgcnt : unsigned(5 downto 0); -- Clock gap counter
cgcntblock: std_ulogic;
aselcnt : unsigned(1 downto 0); -- ASEL delay
cgasel : std_ulogic; -- ASEL when entering CG
--
irq : std_ulogic;
--
-- Automode
am : spi_am_rec;
-- Sync registers for inputs
spii : spi_in_array;
-- Output
spio : spi_out_local_type;
spiolb : spi_out_local_lb_type;
--
astart : std_ulogic;
cstart : std_ulogic;
txdupd2 : std_ulogic;
twdir2 : std_ulogic;
end record;
-----------------------------------------------------------------------------
-- Sub programs
-----------------------------------------------------------------------------
-- Returns a vector containing the character length - 1 in bits as selected
-- by the Mode field LEN.
function spilen (
len : std_logic_vector(3 downto 0))
return std_logic_vector is
begin -- spilen
if len = zero32(3 downto 0) then
return "11111";
else
return "0" & len;
end if;
end spilen;
-- Write clear
procedure wc (
reg_o : out std_ulogic;
reg_i : in std_ulogic;
b : in std_ulogic) is
begin
reg_o := reg_i and not b;
end procedure wc;
-- Reverses string. After this function has been called the first bit
-- to send is always at position 0.
function reverse(
data : std_logic_vector)
return std_logic_vector is
variable rdata: std_logic_vector(data'reverse_range);
begin
for i in data'range loop
rdata(i) := data(i);
end loop;
return rdata;
end function reverse;
-- Performs a HWORD swap if len /= 0
function condhwordswap (
data : std_logic_vector(31 downto 0);
len : std_logic_vector(4 downto 0))
return std_logic_vector is
variable rdata : std_logic_vector(31 downto 0);
begin -- condhwordswap
if len = one32(4 downto 0) then
rdata := data;
else
rdata := data(15 downto 0) & data(31 downto 16);
end if;
return rdata;
end condhwordswap;
-- Zeroes out unused part of receive vector.
function select_data (
data : std_logic_vector(wlen downto 0);
len : std_logic_vector(4 downto 0))
return std_logic_vector is
variable rdata : std_logic_vector(31 downto 0) := (others => '0');
variable length : integer range 0 to 31 := conv_integer(len);
variable sdata : std_logic_vector(31 downto 0) := (others => '0');
begin -- select_data
-- Quartus can not handle variable ranges
-- rdata(conv_integer(len) downto 0) := data(conv_integer(len) downto 0);
sdata := (others => '0'); sdata(wlen downto 0) := data;
case length is
when 15 => rdata(15 downto 0) := sdata(15 downto 0);
when 14 => rdata(14 downto 0) := sdata(14 downto 0);
when 13 => rdata(13 downto 0) := sdata(13 downto 0);
when 12 => rdata(12 downto 0) := sdata(12 downto 0);
when 11 => rdata(11 downto 0) := sdata(11 downto 0);
when 10 => rdata(10 downto 0) := sdata(10 downto 0);
when 9 => rdata(9 downto 0) := sdata(9 downto 0);
when 8 => rdata(8 downto 0) := sdata(8 downto 0);
when 7 => rdata(7 downto 0) := sdata(7 downto 0);
when 6 => rdata(6 downto 0) := sdata(6 downto 0);
when 5 => rdata(5 downto 0) := sdata(5 downto 0);
when 4 => rdata(4 downto 0) := sdata(4 downto 0);
when 3 => rdata(3 downto 0) := sdata(3 downto 0);
when others => rdata := sdata;
end case;
return rdata;
end select_data;
-- purpose: Returns true when a slave is selected and the clock starts
function slv_start (
spisel : std_ulogic;
cpol : std_ulogic;
sck : std_ulogic;
fsck_chg : std_ulogic)
return boolean is
begin -- slv_start
if spisel = '0' then -- Slave is selected
if fsck_chg = '1' then -- The clock has changed
return (cpol xor sck) = '1'; -- The clock is not idle
end if;
end if;
return false;
end slv_start;
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
function spictrl_resval return spi_reg_type is
variable v : spi_reg_type;
begin
v.mode := ('0','0','0','0','0','0','0','0',"0000","0000",
'0','0','0','0',"00000","00", '0', '0', '0', '0');
v.event := ('0', '0', '0', '0', '0', '0', '0', '0');
v.mask := ('0', '0', '0', '0', '0', '0', '0', '0');
v.lst := '0';
v.td := (others => '0');
v.rd := (others => '0');
v.slvsel := (others => '1');
v.aslvsel := (others => '0');
v.uf := '0';
v.ov := '0';
v.td_occ := '0';
v.rd_free := '1';
for i in 0 to (1-syncram)*(FIFO_DEPTH-1) loop
v.txfifo(i) := (others => '0');
v.rxfifo(i) := (others => '0');
end loop;
v.rxd := (others => '0');
v.txd := (others => '0'); v.txd(0) := '1';
v.txdupd := '0';
v.txdbyp := '0';
v.toggle := '0';
v.samp := '1';
v.chng := '0';
v.psck := '0';
v.twdir := INPUT;
v.syncsamp := (others => '0');
v.incrdli := '0';
v.rxdone := '0';
v.rxdone2 := '0';
v.running := '0';
v.ov2 := '0';
v.tfreecnt := FIFO_DEPTH;
v.rfreecnt := FIFO_DEPTH;
v.tdfi := (others => '0');
v.rdfi := (others => '0');
v.tdli := (others => '0');
v.rdli := (others => '0');
v.rbitcnt := (others => '0');
v.tbitcnt := (others => '0');
v.divcnt := (others => '0');
v.cgcnt := (others => '0');
v.cgcntblock := '0';
v.aselcnt := (others => '0');
v.cgasel := '0';
v.irq := '0';
v.am.cfg := ('0', '0', '0', '0', '0', '0', '0', '0', '0');
v.am.per := (others => '0');
v.am.active := '0';
v.am.lock := '0';
v.am.cnt := (others => '0');
v.am.skipdata := '0';
v.am.rxfull := '0';
for i in 0 to (1-syncram)*(FIFO_DEPTH-1) loop
v.am.rxfifo := (others => (others => '0'));
v.am.txfifo := (others => (others => '0'));
end loop;
v.am.rfreecnt := 0;
v.am.mask := (others => '0');
v.am.mask_shdw := (others => '1');
v.am.unread := (others => '0');
v.am.at := '0';
v.am.rxread := '0';
v.am.txwrite := '0';
v.am.txread := '0';
v.am.apbaddr := (others => '0');
v.am.rxsel := '0';
for i in 1 downto 0 loop
v.spii(i).miso := '1';
v.spii(i).mosi := '1';
v.spii(i).sck := '0';
v.spii(i).spisel := '1';
end loop;
v.spio.miso := '1';
v.spio.misooen := INPUT;
v.spio.mosi := '1';
v.spio.mosioen := INPUT;
v.spio.sck := '0';
v.spio.sckoen := INPUT;
v.spio.enable := '0';
v.spio.astart := '0';
v.spio.aready := '0';
v.spiolb.mosi := '1';
v.spiolb.sck := '1';
v.astart := '0';
v.cstart := '0';
v.txdupd2 := '0';
v.twdir2 := '0';
return v;
end spictrl_resval;
constant RES : spi_reg_type := spictrl_resval;
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
signal r, rin : spi_reg_type;
type fifo_data_vector_array is array (automode downto 0) of std_logic_vector(wlen downto 0);
type fifo_addr_vector_array is array (automode downto 0) of std_logic_vector(fdepth-1 downto 0);
signal rx_di, rx_do, tx_di, tx_do : fifo_data_vector_array;
signal rx_ra, rx_wa, tx_ra, tx_wa : fifo_addr_vector_array;
signal rx_read, tx_read, rx_write, tx_write : std_logic_vector(automode downto 0);
signal arstn : std_ulogic;
begin
arstn <= apbi_testrst when (scantest = 1) and (apbi_testen = '1') else rstn;
-- SPI controller, register interface and related logic
comb: process (r, rstn, apbi_psel, apbi_penable, apbi_paddr, apbi_pwrite,
apbi_pwdata, apbi_testen, apbi_testrst, apbi_scanen,
apbi_testoen, spii_miso, spii_mosi, spii_sck, spii_spisel,
spii_astart, rx_do, tx_do, spii_cstart, spii_ignore)
variable v : spi_reg_type;
variable apbaddr : std_logic_vector(APBH downto 2);
variable apbout : std_logic_vector(31 downto 0);
variable len : std_logic_vector(4 downto 0);
variable indata : std_ulogic;
variable change : std_ulogic;
variable update : std_ulogic;
variable sample : std_ulogic;
variable reload : std_ulogic;
variable cgasel : std_ulogic;
variable txshift : std_ulogic;
-- automode
variable rstop1 : std_ulogic;
variable rstop2 : std_ulogic;
variable rstop3 : std_ulogic;
variable tstop1 : std_ulogic;
variable tstop2 : std_ulogic;
variable tstop3 : std_ulogic;
variable astart : std_ulogic;
-- fifos
variable rx_rd : std_ulogic;
variable tx_rd : std_ulogic;
variable rx_wr : std_ulogic;
variable tx_wr : std_ulogic;
--
variable fsck : std_ulogic;
variable fsck_chg : std_ulogic;
--
variable spisel : std_ulogic;
--
variable rntxd : std_logic_vector(0 to 31);
variable ntxd : std_logic_vector(wlen downto 0);
variable amask : std_logic_vector(FIFO_DEPTH-1 downto 0);
variable aloop : integer;
begin -- process comb
v := r; v.irq := '0';
apbaddr := apbi_paddr(APBH downto 2); apbout := (others => '0');
len := spilen(r.mode.len); v.toggle := '0'; v.txdupd := '0';
v.syncsamp := r.syncsamp(0) & '0'; update := '0'; v.rxdone := '0';
indata := '0'; sample := '0'; change := '0'; reload := '0';
v.spio.astart := '0'; cgasel := '0'; v.ov2 := r.ov; txshift := '0';
fsck := '0'; fsck_chg := '0'; v.txdbyp := '0';
spisel := r.spii(1).spisel or r.mode.igsel;
ntxd := r.td(wlen downto 0); rntxd := reverse(r.td);
if r.mode.rev = '1' then ntxd := rntxd(31-wlen to 31); end if;
v.spio.aready := '0';
if AM_EN = 1 then
v.txdupd2 := '0';
v.cstart := '0';
if TW_EN = 1 then
v.twdir2 := r.twdir;
end if;
end if;
if PROG_AM_MASK then
amask := r.am.mask;
aloop := FIFO_DEPTH-1;
else
amask := AM_MASK(FIFO_DEPTH-1 downto 0);
aloop := AM_MASK_END;
end if;
rx_rd := '0'; tx_rd := '0'; rx_wr := '0'; tx_wr := '0';
rstop1 := '0'; rstop2 := '0'; rstop3 := '0';
tstop1 := '0'; tstop2 := '0'; tstop3 := '0';
astart := '0'; v.am.txwrite := '0'; v.am.txwrite := '0'; v.am.rxread := '0';
if AM_EN = 1 then
v.am.at := r.event.at;
v.astart := spii_astart;
if r.event.at = '0' then
astart := spii_astart and (not r.astart);
if PROG_AM_MASK then
v.am.mask := r.am.mask_shdw;
end if;
end if;
if spii_cstart = '1' then v.cstart := '1'; end if;
end if;
if (apbi_psel and apbi_penable and (not apbi_pwrite)) = '1' then
if apbaddr = CAP_ADDR then
apbout := SPICTRLCAPREG;
elsif apbaddr = MODE_ADDR then
apbout := r.mode.amen & r.mode.loopb & r.mode.cpol & r.mode.cpha &
r.mode.div16 & r.mode.rev & r.mode.ms & r.mode.en &
r.mode.len & r.mode.pm & r.mode.tw & r.mode.asel &
r.mode.fact & r.mode.od & r.mode.cg & r.mode.aseldel &
r.mode.tac & r.mode.tto & r.mode.igsel & r.mode.cite &
zero32(0);
elsif apbaddr = EVENT_ADDR then
apbout := r.event.tip & zero32(30 downto 16) & r.event.at &
r.event.lt & zero32(13) & r.event.ov & r.event.un &
r.event.mme & r.event.ne & r.event.nf & zero32(7 downto 0);
elsif apbaddr = MASK_ADDR then
apbout := r.mask.tip & zero32(30 downto 16) & r.mask.at &
r.mask.lt & zero32(13) & r.mask.ov & r.mask.un &
r.mask.mme & r.mask.ne & r.mask.nf & zero32(7 downto 0);
elsif apbaddr = RD_ADDR then
apbout := condhwordswap(r.rd, len);
if AM_EN = 0 or r.mode.amen = '0' then
v.rd_free := '1';
end if;
elsif apbaddr = SLVSEL_ADDR then
if SLVSEL_EN /= 0 then apbout((SLVSEL_SZ-1) downto 0) := r.slvsel;
else null; end if;
elsif apbaddr = ASEL_ADDR then
if ASEL_EN /= 0 then
apbout((SLVSEL_SZ-1) downto 0) := r.aslvsel;
else null; end if;
end if;
end if;
-- write registers
if (apbi_psel and apbi_penable and apbi_pwrite) = '1' then
if apbaddr = MODE_ADDR then
if AM_EN = 1 then v.mode.amen := apbi_pwdata(31); end if;
v.mode.loopb := apbi_pwdata(30);
v.mode.cpol := apbi_pwdata(29);
v.mode.cpha := apbi_pwdata(28);
v.mode.div16 := apbi_pwdata(27);
v.mode.rev := apbi_pwdata(26);
v.mode.ms := apbi_pwdata(25);
v.mode.en := apbi_pwdata(24);
v.mode.len := apbi_pwdata(23 downto 20);
v.mode.pm := apbi_pwdata(19 downto 16);
if TW_EN = 1 then v.mode.tw := apbi_pwdata(15); end if;
if ASEL_EN = 1 then v.mode.asel := apbi_pwdata(14); end if;
v.mode.fact := apbi_pwdata(13);
if OD_EN = 1 then v.mode.od := apbi_pwdata(12); end if;
v.mode.cg := apbi_pwdata(11 downto 7);
if ASEL_EN = 1 then
v.mode.aseldel := apbi_pwdata(6 downto 5);
v.mode.tac := apbi_pwdata(4);
end if;
if TW_EN = 1 then v.mode.tto := apbi_pwdata(3); end if;
v.mode.igsel := apbi_pwdata(2);
v.mode.cite := apbi_pwdata(1);
elsif apbaddr = EVENT_ADDR then
wc(v.event.lt, r.event.lt, apbi_pwdata(14));
wc(v.event.ov, r.event.ov, apbi_pwdata(12));
wc(v.event.un, r.event.un, apbi_pwdata(11));
wc(v.event.mme, r.event.mme, apbi_pwdata(10));
elsif apbaddr = MASK_ADDR then
v.mask.tip := apbi_pwdata(31);
if AM_EN = 1 then
v.mask.at := apbi_pwdata(15);
end if;
v.mask.lt := apbi_pwdata(14);
v.mask.ov := apbi_pwdata(12);
v.mask.un := apbi_pwdata(11);
v.mask.mme := apbi_pwdata(10);
v.mask.ne := apbi_pwdata(9);
v.mask.nf := apbi_pwdata(8);
elsif apbaddr = COM_ADDR then
v.lst := apbi_pwdata(22);
elsif apbaddr = TD_ADDR then
-- The write is lost if the transmit register is written when
-- the not full bit is zero.
if r.event.nf = '1' then
v.td := apbi_pwdata;
if AM_EN = 0 or r.mode.amen = '0' then
v.td_occ := '1';
end if;
end if;
elsif apbaddr = SLVSEL_ADDR then
if SLVSEL_EN /= 0 then v.slvsel := apbi_pwdata((SLVSEL_SZ-1) downto 0);
else null; end if;
elsif apbaddr = ASEL_ADDR then
if ASEL_EN /= 0 then
v.aslvsel := apbi_pwdata((SLVSEL_SZ-1) downto 0);
else null; end if;
end if;
end if;
-- Automode register interface
if AM_EN /= 0 then
if apbi_psel = '1' then
v.am.apbaddr := apbaddr(FIFO_BITS+1 downto 2);
if syncram /= 0 then
-- Check if tx queue will be read
if apbaddr(10 downto 9) = AMTX_ADDR(10 downto 9) then
v.am.txread := apbi_pwrite and not r.am.txread;
end if;
if apbaddr(10 downto 9) = AMRX_ADDR(10 downto 9) then
v.am.rxread := not r.am.rxread;
end if;
end if;
end if;
if (apbi_psel and apbi_penable) = '1' then
if apbaddr = AMCFG_ADDR then
apbout := zero32(31 downto 9) & r.am.cfg.ecgc & r.am.cfg.lock &
r.am.cfg.erpt & r.am.cfg.seq & r.am.cfg.strict &
r.am.cfg.ovtb & r.am.cfg.ovdb & r.am.active &
r.am.cfg.eact;
if apbi_pwrite = '1' then
v.am.cfg.ecgc := apbi_pwdata(8);
v.am.cfg.lock := apbi_pwdata(7);
v.am.cfg.erpt := apbi_pwdata(6);
v.am.cfg.seq := apbi_pwdata(5);
v.am.cfg.strict := apbi_pwdata(4);
v.am.cfg.ovtb := apbi_pwdata(3);
v.am.cfg.ovdb := apbi_pwdata(2);
v.am.cfg.act := apbi_pwdata(1);
v.spio.astart := apbi_pwdata(1);
v.am.cfg.eact := apbi_pwdata(0);
end if;
elsif apbaddr = AMPER_ADDR then
apbout((AM_CNT_BITS-1)*AM_EN downto 0) := r.am.per;
if apbi_pwrite = '1' then
v.am.per := apbi_pwdata((AM_CNT_BITS-1)*AM_EN downto 0);
end if;
elsif apbaddr = AMMSK0_ADDR then
if FIFO_DEPTH > 32 then
apbout := amask(31 downto 0);
if PROG_AM_MASK then
if apbi_pwrite = '1' then
v.am.mask_shdw(31 downto 0) := apbi_pwdata;
end if;
end if;
else
apbout(FIFO_DEPTH-1 downto 0) := amask(FIFO_DEPTH-1 downto 0);
if PROG_AM_MASK then
if apbi_pwrite = '1' then
v.am.mask_shdw(FIFO_DEPTH-1 downto 0) := apbi_pwdata(FIFO_DEPTH-1 downto 0);
end if;
end if;
end if;
elsif apbaddr = AMMSK1_ADDR then
if AM_MSK1_EN then
if FIFO_DEPTH > 64 then
apbout := amask(63 downto 32);
if PROG_AM_MASK then
if apbi_pwrite = '1' then
v.am.mask_shdw(63 downto 32) := apbi_pwdata;
end if;
end if;
else
apbout(FIFO_DEPTH-33 downto 0) := amask(FIFO_DEPTH-1 downto 32);
if PROG_AM_MASK then
if apbi_pwrite = '1' then
v.am.mask_shdw(FIFO_DEPTH-1 downto 32) := apbi_pwdata(FIFO_DEPTH-33 downto 0);
end if;
end if;
end if;
else
null;
end if;
elsif apbaddr = AMMSK2_ADDR then
if AM_MSK2_EN then
if FIFO_DEPTH > 96 then
apbout := amask(95 downto 64);
if PROG_AM_MASK then
if apbi_pwrite = '1' then
v.am.mask_shdw(95 downto 64) := apbi_pwdata;
end if;
end if;
else
apbout(FIFO_DEPTH-65 downto 0) := amask(FIFO_DEPTH-1 downto 64);
if PROG_AM_MASK then
if apbi_pwrite = '1' then
v.am.mask_shdw(FIFO_DEPTH-1 downto 64) := apbi_pwdata(FIFO_DEPTH-65 downto 0);
end if;
end if;
end if;
else
null;
end if;
elsif apbaddr = AMMSK3_ADDR then
if AM_MSK3_EN then
apbout(FIFO_DEPTH-97 downto 0) := amask(FIFO_DEPTH-1 downto 96);
if PROG_AM_MASK then
if apbi_pwrite = '1' then
v.am.mask_shdw(FIFO_DEPTH-1 downto 96) := apbi_pwdata(FIFO_DEPTH-97 downto 0);
end if;
end if;
else
null;
end if;
elsif apbaddr(10 downto 9) = AMTX_ADDR(10 downto 9) then
if conv_integer(apbaddr(8 downto 2)) < FIFO_DEPTH then
if syncram = 0 then
apbout(wlen downto 0) :=
r.am.txfifo(conv_integer(apbaddr(FIFO_BITS+1 downto 2)));
else
apbout(wlen downto 0) := tx_do(automode);
end if;
if apbi_pwrite = '1' then
v.am.txwrite := '1';
v.td := apbi_pwdata;
end if;
end if;
elsif apbaddr(10 downto 9) = AMRX_ADDR(10 downto 9) then
if conv_integer(apbaddr(8 downto 2)) < FIFO_DEPTH then
if syncram = 0 then
if r.mode.rev = '0' then
apbout := condhwordswap(reverse(select_data(r.rxfifo(conv_integer(r.am.apbaddr)), len)), len);
else
apbout := condhwordswap(select_data(r.rxfifo(conv_integer(r.am.apbaddr)), len), len);
end if;
else
if r.mode.rev = '0' then
apbout := condhwordswap(reverse(select_data(rx_do(conv_integer(not r.am.rxsel)), len)), len);
else
apbout := condhwordswap(select_data(rx_do(conv_integer(not r.am.rxsel)), len), len);
end if;
end if;
if r.am.unread(conv_integer(r.am.apbaddr)) = '1' then
v.rd_free := '1';
v.am.unread(conv_integer(r.am.apbaddr)) := '0';
v.am.lock := r.am.cfg.lock;
end if;
end if;
end if;
end if;
end if;
-- Handle transmit FIFO
if r.td_occ = '1' and r.tfreecnt /= 0 then
if syncram = 0 then
v.txfifo(conv_integer(r.tdli)) := ntxd;
else
tx_wr := '1';
end if;
v.tdli := r.tdli + 1;
v.tfreecnt := r.tfreecnt - 1;
v.td_occ := '0';
if r.tfreecnt = FIFO_DEPTH then
v.txdbyp := r.running and r.mode.ms and r.txdupd;
v.txdupd := not r.uf;
tx_rd := '1';
end if;
end if;
-- AM transmit FIFO handling when core is not implemented with SYNCRAM
if syncram = 0 and AM_EN /= 0 and r.am.txwrite = '1' then
if r.mode.rev = '0' then
v.am.txfifo(conv_integer(r.am.apbaddr)) := r.td(wlen downto 0);
else
v.am.txfifo(conv_integer(r.am.apbaddr)) := reverse(r.td)(31-wlen to 31);
end if;
end if;
-- Update receive register and FIFO
if r.rd_free = '1' and r.rfreecnt /= FIFO_DEPTH then
if syncram = 0 then
if r.mode.rev = '0' then
v.rd := reverse(select_data(r.rxfifo(conv_integer(r.rdfi)), len));
else
v.rd := select_data(r.rxfifo(conv_integer(r.rdfi)), len);
end if;
else
if r.mode.rev = '0' then
v.rd := reverse(select_data(rx_do(0), len));
else
v.rd := select_data(rx_do(0), len);
end if;
end if;
if not ((ignore > 0) and (spii_ignore = '1')) then
v.rdfi := r.rdfi + 1;
v.rfreecnt := r.rfreecnt + 1;
v.rd_free := '0';
end if;
end if;
if v.rd_free = '1' and r.rfreecnt /= FIFO_DEPTH then rx_rd := '1'; end if;
if r.mode.en = '1' then -- Core is enabled
-- Not full detection
if r.tfreecnt /= 0 or r.td_occ /= '1' then
v.event.nf := '1';
if (r.mask.nf and not r.event.nf) = '1' then
v.irq := '1';
end if;
else
v.event.nf := '0';
end if;
-- Not empty detection
if ((AM_EN = 0 or r.mode.amen = '0') and (r.rfreecnt /= FIFO_DEPTH or r.rd_free /= '1')) or
(AM_EN = 1 and r.mode.amen = '1' and r.am.unread /= zero128(FIFO_DEPTH-1 downto 0)) then
v.event.ne := '1';
if (r.mask.ne and not r.event.ne) = '1' then
v.irq := '1';
end if;
else
v.event.ne := '0';
if AM_EN = 1 then v.am.lock := '0'; end if;
end if;
end if;
---------------------------------------------------------------------------
-- Automated periodic transfer control
---------------------------------------------------------------------------
if AM_EN = 1 and r.mode.amen = '1' then
if r.am.active = '0' then
-- Activation either from register write or external event.
v.am.active := r.spio.astart or (astart and r.am.cfg.eact);
v.am.cfg.act := v.am.active;
v.am.rfreecnt := 0;
for i in 0 to aloop loop
if amask(i) = '1' then
v.am.rfreecnt := v.am.rfreecnt+1;
end if;
end loop;
v.am.skipdata := '0'; v.am.rxfull := '0';
v.am.cnt := unsigned(r.am.per);
v.event.at := v.am.active;
v.tdfi := (others => '0');
-- Check mask to see which word in the FIFO to start with.
for i in 0 to aloop loop
if amask(i) = '1' then
if tstop1 = '0' then
v.tdfi := conv_std_logic_vector(i, r.tdfi'length);
end if;
tstop1 := '1';
end if;
end loop;
if v.am.active = '1' then
v.txdupd2 := '1'; tx_rd := '1';
v.tfreecnt := FIFO_DEPTH;
for i in 0 to aloop loop
if amask(i) = '1' then
v.tfreecnt := v.tfreecnt-1;
end if;
end loop;
end if;
v.rdli := (others => '0');
for i in 0 to aloop loop
if rstop1 = '0' then
if amask(i) = '0' then
v.rdli := v.rdli + 1;
else
rstop1 := '1';
end if;
end if;
end loop;
v.cstart := v.am.active;
else
-- Receive fifo handling
if r.am.rxfull = '1' then -- AM RX fifo is filled
-- Move to receive queue if the queue is empty or if there is no
-- requirement on sequential transfers and the queue is not locked.
if (r.event.ne and (v.am.lock or r.am.cfg.seq)) = '0' then
-- Queue is empty
if syncram = 0 then
v.rxfifo := r.am.rxfifo;
else
v.am.rxsel := not r.am.rxsel;
end if;
v.rdfi := (others => '0');
v.rfreecnt := r.am.rfreecnt;
v.rd_free := '0';
v.am.rxfull := '0';
for i in 0 to aloop loop
if amask(i) = '1' then
v.am.unread(i) := '1';
end if;
end loop;
end if;
if r.event.tip = '0' and r.am.at = '1' then
v.event.at := '0';
end if;
if (r.mask.at and r.event.at) = '1' then
v.irq := '1';
end if;
end if;
if r.am.cfg.act = '0' then v.am.active := r.running; end if;
v.am.cfg.eact := '0';
if (r.am.cnt = 0 and r.am.cfg.erpt = '0') or (astart = '1' and r.am.cfg.erpt = '1') then
-- Only allowed to start new transfer if previous transfer(s) is finished
if r.event.tip = '0' then
if (not v.am.rxfull or r.am.cfg.strict) = '1' then
v.am.cnt := unsigned(r.am.per);
end if;
if (not v.am.rxfull or (r.am.cfg.strict and not r.am.cfg.ovtb)) = '1' then
-- Start transfer. Initialize indexes and fifo counter
v.txdupd2 := '1'; tx_rd := '1';
v.am.cnt := unsigned(r.am.per);
v.rdli := (others => '0');
for i in 0 to aloop loop
if rstop2 = '0' then
if amask(i) = '0' then
v.rdli := v.rdli + 1;
else
rstop2 := '1';
end if;
end if;
end loop;
v.tfreecnt := FIFO_DEPTH;
v.am.rfreecnt := 0;
for i in 0 to aloop loop
if amask(i) = '1' then
v.am.rfreecnt := v.am.rfreecnt+1;
v.tfreecnt := v.tfreecnt-1;
end if;
end loop;
v.tdfi := (others => '0');
-- Check mask to see which word in the FIFO to start with.
for i in 0 to aloop loop
if amask(i) = '1' then
if tstop2 = '0' then
v.tdfi := conv_std_logic_vector(i, r.tdfi'length);
end if;
tstop2 := '1';
end if;
end loop;
-- Skip incoming data if receive FIFO is full and OVDB is '1'.
v.am.skipdata := v.am.rxfull and r.am.cfg.ovdb;
if v.am.skipdata = '0' then
-- Clear AM receive fifo if we will overwrite it.
v.am.rfreecnt := FIFO_DEPTH;
for i in 0 to aloop loop
if amask(i) = '0' then
v.am.rfreecnt := v.am.rfreecnt-1;
end if;
end loop;
v.am.rxfull := '0';
end if;
v.event.at := '1';
v.cstart := astart and r.am.cfg.erpt;
end if;
end if;
else
v.am.cnt := r.am.cnt - 1;
end if;
end if;
end if;
---------------------------------------------------------------------------
-- SCK filtering, only used in slave mode
---------------------------------------------------------------------------
fsck := r.psck;
if (r.mode.en and not r.mode.ms) = '1' then
if (r.spii(1).sck xor r.psck) = '0' then
reload := '1';
else
-- Detected SCK change
if r.divcnt = 0 then
v.psck := r.spii(1).sck;
fsck := r.spii(1).sck;
fsck_chg := '1';
reload := '1';
else
v.divcnt := r.divcnt - 1;
end if;
end if;
elsif r.mode.en = '1' then
v.psck := r.spii(1).sck;
end if;
---------------------------------------------------------------------------
-- SPI bus control
---------------------------------------------------------------------------
if (r.mode.en and not r.running) = '1' and (r.mode.ms = '0' or r.divcnt = 0) then
if r.mode.ms = '1' then
if r.divcnt = 0 then
v.spio.sck := r.mode.cpol;
end if;
v.spio.misooen := INPUT;
if TW_EN = 0 or r.mode.tw = '0' then
if OD_EN = 0 or r.mode.od = '0' then
v.spio.mosioen := OUTPUT;
end if;
else
v.spio.mosioen := INPUT;
end if;
v.spio.sckoen := OUTPUT;
if TW_EN = 1 then v.twdir := OUTPUT xor r.mode.tto; end if;
else
if (spisel or r.mode.tw) = '0' then
v.spio.misooen := OUTPUT;
else
v.spio.misooen := INPUT;
end if;
if (not spisel and r.mode.tw and r.mode.tto) = '0' then
v.spio.mosioen := INPUT;
else
v.spio.mosioen := OUTPUT;
end if;
v.spio.sckoen := INPUT;
if TW_EN = 1 then v.twdir := INPUT xor r.mode.tto; end if;
end if;
if ((((AM_EN = 0 or r.mode.amen = '0') or
(AM_EN = 1 and r.mode.amen = '1' and r.am.active = '1')) and
r.mode.ms = '1' and r.tfreecnt /= FIFO_DEPTH and r.txdupd = '0' and (AM_EN = 0 or r.txdupd2 = '0')) or
slv_start(spisel, r.mode.cpol, fsck, fsck_chg)) then
-- Slave underrun detection
if r.tfreecnt = FIFO_DEPTH then
v.uf := '1';
if (r.mask.un and not v.event.un) = '1' then
v.irq := '1';
end if;
v.event.un := '1';
end if;
v.running := '1';
if r.mode.ms = '1' then
if TW_EN = 0 or r.mode.tw = '0' then
v.spio.mosioen := OUTPUT;
else
v.spio.mosioen := OUTPUT xor r.mode.tto;
end if;
change := not r.mode.cpha;
-- Insert cycles when cpha = '0' to ensure proper setup
-- time for first MOSI value in master mode.
reload := not r.mode.cpha;
end if;
end if;
v.cgcnt := (others => '0');
v.rbitcnt := (others => '0'); v.tbitcnt := (others => '0');
if r.mode.ms = '0' then
update := not (r.mode.cpha or (fsck xor r.mode.cpol));
if r.mode.cpha = '0' then
-- Prepare first bit
v.tbitcnt := (others => '0'); v.tbitcnt(0) := '1';
if v.running = '1' and (TW_EN = 0 or r.mode.tw = '0' or r.twdir = OUTPUT) then
txshift := '1';
end if;
end if;
end if;
-- samp and chng should not be changed on b2b
if spisel /= '0' then
v.samp := not r.mode.cpha;
v.chng := r.mode.cpha;
v.psck := r.mode.cpol;
end if;
end if;
if AM_EN = 0 or r.mode.amen = '0' or r.am.cfg.ecgc = '0' then
v.cgcntblock := '0';
else
if r.cstart = '1' then
v.cgcntblock := '0';
end if;
end if;
---------------------------------------------------------------------------
-- Clock generation, only in master mode
---------------------------------------------------------------------------
if r.mode.ms = '1' and (r.running = '1' or r.divcnt /= 0) then
-- The frequency of the SPI clock relative to the system clock is
-- determined by the fact, div16 and pm register fields.
--
-- With fact = 0 the fields have the same meaning as in the MPC83xx
-- register interface. The clock is divided by 4*([PM]+1) and if div16
-- is set the clock is divided by 16*(4*([PM]+1)).
--
-- With fact = 1 the core's register i/f is no longer compatible with
-- the MPC83xx register interface. The clock is divided by 2*([PM]+1) and
-- if div16 is set the clock is divided by 16*(2*([PM]+1)).
--
-- The generated clock's duty cycle is always 50%.
if r.divcnt = 0 then
if ASEL_EN = 0 or r.aselcnt = 0 then
-- Toggle SCK unless we are in a clock gap
if (r.cgcnt = 0 and (AM_EN = 0 or r.cgcntblock = '0')) or
r.spiolb.sck /= r.mode.cpol then
v.spio.sck := not r.spiolb.sck;
v.toggle := r.running;
end if;
if r.cgcnt /= 0 and (AM_EN = 0 or r.cgcntblock = '0') then
v.cgcnt := r.cgcnt - 1;
if ASEL_EN /= 0 and r.cgcnt = 1 then
cgasel := r.mode.tac;
end if;
end if;
elsif ASEL_EN = 1 then
v.aselcnt := r.aselcnt - 1;
end if;
reload := '1';
else
v.divcnt := r.divcnt - 1;
end if;
elsif r.mode.ms = '1' then
v.divcnt := (others => '0');
end if;
if reload = '1' then
-- Reload clock scale counter
v.divcnt(4 downto 0) := unsigned('0' & r.mode.pm) + 1;
if (not r.mode.fact and r.mode.ms) = '1' then
if r.mode.div16 = '1' then
v.divcnt := shift_left(v.divcnt, 5) - 1;
else
v.divcnt := shift_left(v.divcnt, 1) - 1;
end if;
else
if (r.mode.div16 and r.mode.ms) = '1' then
v.divcnt := shift_left(v.divcnt, 4) - 1;
else
v.divcnt(9 downto 4) := (others => '0');
v.divcnt(3 downto 0) := unsigned(r.mode.pm);
end if;
end if;
end if;
---------------------------------------------------------------------------
-- Handle master operation.
---------------------------------------------------------------------------
if r.mode.ms = '1' then
-- Sample data
if r.toggle = '1' then
v.samp := not r.samp;
sample := r.samp;
end if;
-- Change data on the clock flank...
if v.toggle = '1' then
v.chng := not r.chng;
change := r.chng;
end if;
-- Detect multiple-master errors (mode-fault)
if spisel = '0' then
v.mode.en := '0';
v.mode.ms := '0';
v.event.mme := '1';
if (r.mask.mme and not r.event.mme) = '1' then
v.irq := '1';
end if;
v.running := '0';
v.event.tip := '0';
if AM_EN = 1 then
v.event.at := '0';
end if;
end if;
-- Select input data
if r.mode.loopb = '1' then
indata := r.spiolb.mosi;
elsif TW_EN = 1 and r.mode.tw = '1' then
indata := r.spii(1).mosi;
else
indata := r.spii(1).miso;
end if;
end if;
---------------------------------------------------------------------------
-- Handle slave operation
---------------------------------------------------------------------------
if (r.mode.en and not r.mode.ms) = '1' then
if spisel = '0' then
if fsck_chg = '1' then
sample := r.samp; v.samp := not r.samp;
change := r.chng; v.chng := not r.chng;
end if;
indata := r.spii(1).mosi;
end if;
end if;
---------------------------------------------------------------------------
-- Used in both master and slave operation
---------------------------------------------------------------------------
if sample = '1' then
-- Detect receive overflow
if ((AM_EN = 0 or r.mode.amen = '0' ) and (r.rfreecnt = 0 and r.rd_free = '0')) or
(AM_EN = 1 and r.mode.amen = '1' and r.am.rfreecnt = 0) or
r.ov = '1' then
if TW_EN = 0 or r.mode.tw = '0' or r.twdir = INPUT then
-- Overflow event and IRQ
v.ov := '1';
if r.ov = '0' then
if (r.mask.ov and not r.event.ov) = '1' then
v.irq := '1';
end if;
v.event.ov := '1';
end if;
end if;
sample := '0'; -- Prevent sample below
else
sample := not r.mode.ms or r.mode.loopb;
v.syncsamp(0) := not sample;
end if;
if r.rbitcnt = len(log2(wlen+1)-1 downto 0) then
v.rbitcnt := (others => '0');
if TW_EN = 1 then
v.twdir := r.twdir xor not r.mode.loopb;
end if;
if (TW_EN = 0 or r.mode.tw = '0' or r.mode.loopb = '1' or
(r.mode.tw = '1' and r.twdir = INPUT)) then
v.incrdli := not r.ov;
end if;
if (TW_EN = 0 or r.mode.tw = '0' or r.mode.loopb = '1' or
(TW_EN = 1 and r.mode.tw = '1' and
(((r.mode.ms xor r.mode.tto) = '1' and r.twdir = INPUT) or
((r.mode.ms xor r.mode.tto) = '0' and r.twdir = OUTPUT)))) then
if r.mode.cpha = '0' then
v.cgcnt := unsigned(r.mode.cg & '0');
if ASEL_EN /= 0 then v.cgasel := r.mode.tac; end if;
if AM_EN = 1 and r.mode.amen = '1' and r.am.cfg.ecgc = '1' then
v.cgcntblock := '1';
end if;
end if;
v.ov := '0';
if r.tfreecnt = FIFO_DEPTH then
v.running := '0';
-- When running with with SCK freq. at half the system freq. we are
-- past the last edge here and SCK has transitioned from CPOL.
-- Force controller into idle state, only applies to master mode.
if (r.toggle and v.toggle) = '1' then
v.toggle := '0';
v.spio.sck := r.mode.cpol;
v.chng := r.chng;
end if;
end if;
v.uf := '0';
end if;
else
v.rbitcnt := r.rbitcnt + 1;
end if;
end if;
-- Sample data line and put into shift register.
if (r.syncsamp(1) or sample) = '1' then
v.rxd := r.rxd(wlen-1 downto 0) & indata;
if ((r.syncsamp(1) and r.incrdli) or (sample and v.incrdli)) = '1' then
v.rxdone := '1'; v.rxdone2 := '1'; v.incrdli := '0';
end if;
end if;
-- Put data into receive queue
if ((AM_EN = 0 or (r.mode.amen and r.am.skipdata) = '0') and
r.rxdone = '1') then
if AM_EN = 1 and r.am.active = '1'then
if not ((ignore > 0) and (spii_ignore = '1')) then
-- Check mask, maybe we need to skip next word in fifo
v.rdli := r.rdli + 1;
v.am.rfreecnt := v.am.rfreecnt - 1;
if DISCONT_AM_MASK then
for i in 0 to aloop loop
if i > conv_integer(r.rdli) and rstop3 = '0' then
if amask(i) = '0' then
v.rdli := v.rdli + 1;
else
rstop3 := '1';
end if;
end if;
end loop;
end if;
end if;
else
v.rdli := r.rdli + 1;
v.rfreecnt := v.rfreecnt - 1;
rx_rd := v.rd_free;
end if;
if syncram = 0 then
if AM_EN = 1 and r.am.active = '1' then
v.am.rxfifo(conv_integer(r.rdli)) := r.rxd;
else
v.rxfifo(conv_integer(r.rdli)) := r.rxd;
end if;
else
rx_wr := '1';
end if;
if r.running = '0' then
if AM_EN = 1 then v.am.rxfull := r.am.active; end if;
end if;
end if;
if AM_EN = 1 and r.mode.amen = '1' then
if TW_EN = 0 or r.mode.tw = '0' or r.mode.tto = '0' then
if r.rxdone = '1' then
v.spio.aready := '1';
end if;
else
if r.twdir = '1' and r.twdir2 = '0' then
v.spio.aready := '1';
end if;
end if;
end if;
-- Special case to put data in receive queue for automatic
-- transfer while in three wire mode with tto = 1
if AM_EN = 1 and TW_EN = 1 and r.mode.amen = '1' and
r.mode.tw = '1' and r.running = '0' and r.rxdone2 = '1' and
r.mode.tto = '1' and r.twdir = INPUT and r.mode.ms = '1' then
v.am.rxfull := r.am.active;
end if;
-- Advance transmit queue
if change = '1' then
if TW_EN = 1 and r.mode.tw = '1' then
v.spio.mosioen := r.twdir;
end if;
if r.tbitcnt = len(log2(wlen+1)-1 downto 0) then
if (TW_EN = 0 or r.mode.tw = '0' or r.mode.loopb = '1' or
(TW_EN = 1 and r.mode.tw = '1' and
(((r.mode.ms xor r.mode.tto) = '1' and r.twdir = INPUT) or
((r.mode.ms xor r.mode.tto) = '0' and r.twdir = OUTPUT)))) then
if r.mode.cpha = '1' then
v.cgcnt := unsigned(r.mode.cg & '0');
if ASEL_EN /= 0 then v.cgasel := r.mode.tac; end if;
if AM_EN = 1 and r.mode.amen = '1' and r.am.cfg.ecgc = '1' then
v.cgcntblock := '1';
end if;
end if;
end if;
if (TW_EN = 0 or r.mode.tw = '0' or r.mode.loopb = '1' or r.twdir = OUTPUT) then
if r.uf = '0' then
if not ((ignore > 0) and (spii_ignore = '1')) then
v.tfreecnt := v.tfreecnt + 1;
end if;
end if;
v.txdupd := '1'; tx_rd := '1';
end if;
v.tbitcnt := (others => '0');
else
v.tbitcnt := r.tbitcnt + 1;
end if;
if v.uf = '0' and (TW_EN = 0 or r.mode.tw = '0' or r.mode.loopb = '1' or r.twdir = OUTPUT) then
txshift := v.running;
end if;
end if;
if txshift = '1' then
v.txd := '1' & r.txd(wlen downto 1);
end if;
if AM_EN = 1 then
if r.txdupd2 = '1' then
tx_rd := '1';
v.txdupd := '1';
end if;
end if;
if r.txdupd = '1' then
tx_rd := '1';
if r.txdbyp = '0' then
if syncram = 0 then
if AM_EN = 1 and r.mode.amen = '1' then
v.txd := r.am.txfifo(conv_integer(r.tdfi));
else
v.txd := r.txfifo(conv_integer(r.tdfi));
end if;
else
-- The first FIFO is always used when using syncrams, even in AM mode
v.txd := tx_do(0);
end if;
end if;
-- Data written to TD, bypass
if v.txdbyp = '1' then
v.txd := ntxd;
end if;
if r.tfreecnt /= FIFO_DEPTH then
if AM_EN = 0 or r.mode.amen = '0' then
v.tdfi := v.tdfi + 1;
else
-- Check mask, might need to skip next word
if not (((ignore > 0) and (spii_ignore = '1'))) then
if DISCONT_AM_MASK then
for i in 0 to aloop loop
if tstop3 = '0' and i > conv_integer(v.tdfi) then
if amask(i) = '0' then
v.tdfi := v.tdfi + 1;
else
tstop3 := '1';
end if;
end if;
end loop;
end if;
v.tdfi := v.tdfi + 1;
end if;
end if;
elsif v.txdbyp = '0' then
-- Bus idle value
v.txd(0) := '1';
end if;
end if;
-- Transmit bit
if (change or update) = '1' then
if v.uf = '0' then
v.spio.miso := r.txd(0);
v.spio.mosi := r.txd(0);
if OD_EN = 1 and r.mode.od = '1' then
if (r.mode.ms or r.mode.tw) = '1' then
v.spio.mosioen := r.txd(0) xor OUTPUT;
else
v.spio.misooen := r.txd(0) xor OUTPUT;
end if;
end if;
else
v.spio.miso := '1';
v.spio.mosi := '1';
if OD_EN = 1 and r.mode.od = '1' then
v.spio.misooen := INPUT;
v.spio.mosioen := INPUT;
end if;
end if;
end if;
-- Transfer in progress interrupt generation
if (not r.running and (r.ov2 or (r.rxdone2 or (not r.mode.ms and r.mode.tw)))) = '1' then
if r.mode.ms = '0' or r.mode.cite = '0' or r.divcnt = 0 then
v.event.tip := '0'; v.rxdone2 := '0';
end if;
end if;
if v.running = '1' then v.event.tip := '1'; end if;
if (v.running and not r.event.tip and r.mask.tip and r.mode.en) = '1' then
v.irq := '1';
end if;
-- LST detection and interrupt generation
if v.running = '0' and v.tfreecnt = FIFO_DEPTH and r.lst = '1' then
v.event.lt := '1'; v.lst := '0';
if (r.mask.lt and not r.event.lt) = '1' then v.irq := '1'; end if;
end if;
---------------------------------------------------------------------------
-- Automatic slave select, only in master mode
---------------------------------------------------------------------------
if ASEL_EN /= 0 then
if (r.mode.ms and r.mode.asel) = '1' then
if ((not r.running and v.running) or -- Transfer start or
(r.event.tip and not v.event.tip) or -- transfer end or
(v.running and (cgasel or -- End or start of CG
(r.cgasel and not (r.spiolb.sck xor r.mode.cpol))))) = '1'
then
v.slvsel := r.aslvsel;
v.aslvsel := r.slvsel;
v.cgasel := '0';
end if;
-- May need to delay start of transfer
if ((not r.running and v.running) or cgasel) = '1' then -- Transfer start
v.aselcnt := unsigned(r.mode.aseldel);
end if;
else
v.cgasel := '0';
v.aselcnt := (others => '0');
end if;
end if;
-- Do not toggle outputs in loopback mode
if (r.mode.loopb = '1' or
(r.mode.tw = '1' and TW_EN = 1 and r.twdir = INPUT)) then
v.spio.mosioen := INPUT; v.spio.misooen := INPUT;
end if;
if r.mode.loopb = '1' then v.spio.sckoen := INPUT; end if;
-- When driving in OD mode, always drive low.
if OD_EN = 1 and (r.mode.od and not r.mode.loopb) = '1' then
v.spio.miso := v.spio.miso and not r.mode.od;
v.spio.mosi := v.spio.mosi and not r.mode.od;
end if;
-- Core is disabled
if ((not RESET_ALL) and rstn = '0') or (r.mode.en = '0') then
v.tfreecnt := FIFO_DEPTH;
v.rfreecnt := FIFO_DEPTH;
v.tdfi := RES.tdfi; v.rdfi := RES.rdfi;
v.tdli := RES.tdli; v.rdli := RES.rdli;
v.rd_free := RES.rd_free;
v.td_occ := RES.td_occ;
v.lst := RES.lst;
v.uf := RES.uf;
v.ov := RES.ov;
v.running := RES.running;
v.event.tip := RES.event.tip;
v.incrdli := RES.incrdli;
if TW_EN = 1 then
v.twdir := RES.twdir;
end if;
v.spio.miso := RES.spio.miso;
v.spio.mosi := RES.spio.mosi;
if syncrst = 1 or (r.mode.en = '0') then
v.spio.misooen := RES.spio.misooen;
v.spio.mosioen := RES.spio.mosioen;
v.spio.sckoen := RES.spio.sckoen;
end if;
if AM_EN = 1 then
v.event.at := RES.event.at;
end if;
-- Need to assign samp, chng and psck here if spisel is low when the
-- core is enabled
v.samp := not r.mode.cpha;
v.chng := r.mode.cpha;
v.psck := r.mode.cpol;
if AM_EN = 1 then
v.am.active := RES.am.active;
v.am.cfg.act := RES.am.cfg.act;
v.am.cfg.eact := RES.am.cfg.eact;
v.am.unread := RES.am.unread;
v.am.rxsel := RES.am.rxsel;
end if;
v.rxdone2 := '0';
v.divcnt := (others => '0');
end if;
-- Chip reset
if (not RESET_ALL) and (rstn = '0') then
v.mode := RES.mode;
v.event.tip := RES.event.tip;
v.event.lt := RES.event.lt;
v.event.ov := RES.event.ov;
v.event.un := RES.event.un;
v.event.mme := RES.event.mme;
v.event.ne := RES.event.ne;
v.event.nf := RES.event.nf;
v.mask := RES.mask;
if AM_EN = 1 then
v.event.at := RES.event.at;
if PROG_AM_MASK then
v.am.mask_shdw := RES.am.mask_shdw;
end if;
v.am.per := RES.am.per;
v.am.cfg := RES.am.cfg;
v.am.rxread := RES.am.rxread;
v.am.txwrite := RES.am.txwrite;
v.am.txread := RES.am.txread;
v.am.apbaddr := RES.am.apbaddr;
v.am.rxsel := RES.am.rxsel;
v.cgcntblock := RES.cgcntblock;
end if;
v.lst := RES.lst;
if syncrst = 1 then
v.slvsel := RES.slvsel;
end if;
v.cgcnt := RES.cgcnt;
v.rbitcnt := RES.rbitcnt; v.tbitcnt := RES.tbitcnt;
v.txd := RES.txd;
end if;
-- Drive unused bit if open drain mode is not supported
if OD_EN = 0 then v.mode.od := '0'; end if;
-- Drive unused bits if automode is not supported
if AM_EN = 0 then
v.mode.amen := '0';
--
v.am.cfg.seq := '0';
v.am.cfg.strict := '0';
v.am.cfg.ovtb := '0';
v.am.cfg.ovdb := '0';
v.am.cfg.act := '0';
v.am.cfg.eact := '0';
v.am.per := (others => '0');
v.am.active := '0';
v.am.lock := '0';
v.am.skipdata := '0';
v.am.rxfull := '0';
v.am.rfreecnt := 0;
v.event.at := '0';
v.am.unread := (others=>'0');
v.am.cfg.erpt := '0';
v.am.cfg.lock := '0';
v.am.cfg.ecgc := '0';
v.am.cnt := (others=>'0');
v.am.rxread := '0';
v.am.txwrite := '0';
v.am.txread := '0';
v.am.apbaddr := (others => '0');
v.am.rxsel := '0';
v.mask.at := '0';
v.cstart := '0';
end if;
if AM_EN = 0 or not PROG_AM_MASK then
v.am.mask := (others=>'0');
v.am.mask_shdw := (others=>'0');
end if;
-- Drive unused bits if automatic slave select is not enabled
if ASEL_EN = 0 then
v.mode.asel := '0';
v.aslvsel := (others => '0');
v.mode.aseldel := (others => '0');
v.mode.tac := '0';
v.aselcnt := (others => '0');
v.cgasel := '0';
end if;
-- Drive unused bits if three-wire mode is not enabled
if TW_EN = 0 then
v.mode.tw := '0';
v.mode.tto := '0';
v.twdir := INPUT;
end if;
if TW_EN = 0 or AM_EN = 0 then
v.twdir2 := INPUT;
end if;
if SLVSEL_EN = 0 then
v.slvsel := (others => '1');
end if;
-- Propagate core enable bit
v.spio.enable := r.mode.en;
-- Synchronize inputs coming from off-chip
v.spii(0) := (spii_miso, spii_mosi, spii_sck, spii_spisel);
v.spii(1) := r.spii(0);
-- Outputs to RAMs
if syncram = 0 then
rx_di <= (others => (others => '0'));
tx_di <= (others => (others => '0'));
rx_ra <= (others => (others => '0'));
rx_wa <= (others => (others => '0'));
tx_ra <= (others => (others => '0'));
tx_wa <= (others => (others => '0'));
rx_read <= (others => '0'); rx_write <= (others => '0');
tx_read <= (others => '0'); tx_write <= (others => '0');
else
-- TX RAM(s) write
-- TX RAM(s) are either written from TX register or AM TX area
for i in 0 to automode loop
tx_di(i) <= ntxd;
end loop;
for i in 0 to automode loop
tx_wa(i) <= r.tdli;
end loop;
tx_write(0) <= tx_wr;
if AM_EN /= 0 then
-- Auto mode present
-- Write from AM register interface writes both RAMs
-- Write from TXD register writes RAM 0
tx_write(automode) <= r.am.txwrite;
tx_write(0) <= tx_wr or r.am.txwrite;
if r.am.txwrite = '1' then
for i in 0 to automode loop
tx_wa(i) <= r.am.apbaddr;
end loop;
end if;
end if;
-- TX RAM(s) read
-- First RAM is read by bit shift logic
tx_read(0) <= tx_rd;
tx_ra(0) <= r.tdfi;
if AM_EN /= 0 then
-- Second RAM is read from register interface
tx_read(automode) <= v.am.txread or r.am.txread;
tx_ra(automode) <= v.am.apbaddr;
end if;
-- RX RAM(s) write
-- RX RAM(s) is always written from receive shift register
for i in 0 to automode loop
rx_di(i) <= r.rxd;
rx_wa(i) <= r.rdli;
end loop;
rx_write(0) <= rx_wr;
if AM_EN /= 0 then
rx_write(automode) <= '0';
end if;
if AM_EN /= 0 and r.mode.amen = '1' then
-- AM active
-- Handle writes from bit shift logic
if r.am.rxsel = '0' then
rx_write(0) <= rx_wr;
rx_write(automode) <= '0';
else
rx_write(0) <= '0';
rx_write(automode) <= rx_wr;
end if;
end if;
-- RX RAM(s) are read via register interface
for i in 0 to automode loop
rx_ra(i) <= r.rdfi;
rx_read(i) <= rx_rd;
end loop;
if AM_EN /= 0 and r.mode.amen = '1' then
if r.am.rxsel = '0' then
rx_read(0) <= '0';
rx_read(automode) <= v.am.rxread;
if v.am.rxread = '1' then
rx_ra(automode) <= v.am.apbaddr;
end if;
else
rx_read(0) <= v.am.rxread;
rx_read(automode) <= '0';
if v.am.rxread = '1' then
rx_ra(0) <= v.am.apbaddr;
end if;
end if;
end if;
if scantest = 1 and (apbi_scanen and apbi_testen) = '1' then
rx_read <= (others => '0'); rx_write <= (others => '0');
tx_read <= (others => '0'); tx_write <= (others => '0');
end if;
end if;
v.spiolb.mosi := v.spio.mosi;
v.spiolb.sck := v.spio.sck;
-- Update registers
rin <= v;
-- Update outputs
apbo_prdata <= apbout;
apbo_pirq <= r.irq;
slvsel <= r.slvsel;
spio_miso <= r.spio.miso;
spio_misooen <= r.spio.misooen;
spio_mosi <= r.spio.mosi;
spio_mosioen <= r.spio.mosioen;
spio_sck <= r.spio.sck;
spio_sckoen <= r.spio.sckoen;
spio_enable <= r.spio.enable;
spio_astart <= r.spio.astart;
spio_aready <= r.spio.aready;
if scantest = 1 and apbi_testen = '1' then
spio_misooen <= apbi_testoen;
spio_mosioen <= apbi_testoen;
spio_sckoen <= apbi_testoen;
end if;
end process comb;
-- FIFOs
fiforams : if syncram /= 0 generate
fifoloop : for i in 0 to automode generate
noft : if ft = 0 generate
rxfifo : syncram_2p
generic map (
tech => memtech,
abits => fdepth,
dbits => wlen+1,
sepclk => 0,
wrfst => 1)
port map (
rclk => clk,
renable => rx_read(i),
raddress => rx_ra(i),
dataout => rx_do(i),
wclk => clk,
write => rx_write(i),
waddress => rx_wa(i),
datain => rx_di(i));
-- testin => testin);
txfifo : syncram_2p
generic map (
tech => memtech,
abits => fdepth,
dbits => wlen+1,
sepclk => 0,
wrfst => 1)
port map (
rclk => clk,
renable => tx_read(i),
raddress => tx_ra(i),
dataout => tx_do(i),
wclk => clk,
write => tx_write(i),
waddress => tx_wa(i),
datain => tx_di(i));
-- testin => testin);
end generate noft;
ftfifos : if ft /= 0 generate
ftrxfifo : syncram_2pft
generic map (
tech => memtech,
abits => fdepth,
dbits => wlen+1,
sepclk => 0,
wrfst => 1,
ft => ft)
port map (
rclk => clk,
renable => rx_read(i),
raddress => rx_ra(i),
dataout => rx_do(i),
wclk => clk,
write => rx_write(i),
waddress => rx_wa(i),
datain => rx_di(i),
error => open);
-- testin => testin);
fttxfifo : syncram_2pft
generic map (
tech => memtech,
abits => fdepth,
dbits => wlen+1,
sepclk => 0,
wrfst => 1,
ft => ft)
port map (
rclk => clk,
renable => tx_read(i),
raddress => tx_ra(i),
dataout => tx_do(i),
wclk => clk,
write => tx_write(i),
waddress => tx_wa(i),
datain => tx_di(i),
error => open);
-- testin => testin);
end generate ftfifos;
end generate fifoloop;
end generate fiforams;
nofiforams : if syncram = 0 generate
rx_do <= (others => (others => '0'));
tx_do <= (others => (others => '0'));
end generate;
-- Registers
reg: process (clk, arstn)
begin -- process reg
if rising_edge(clk) then
r <= rin;
if rstn = '0' then
r.spio.sck <= RES.spio.sck;
r.rbitcnt <= RES.rbitcnt; r.tbitcnt <= RES.tbitcnt;
if RESET_ALL then
r <= RES;
-- Do not use synchronous reset for sync. registers
r.spii <= rin.spii;
end if;
end if;
end if;
if syncrst = 0 and arstn = '0' then
r.spio.misooen <= RES.spio.misooen;
r.spio.mosioen <= RES.spio.mosioen;
r.spio.sckoen <= RES.spio.sckoen;
if SLVSEL_EN /= 0 then
r.slvsel <= RES.slvsel;
end if;
end if;
end process reg;
end architecture rtl;
| gpl-3.0 | 697323ef841c2fc8eda3f7cec81f1699 | 0.50191 | 3.416276 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/jtag/ahbjtag_bsd.vhd | 1 | 3,384 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ahbjtag
-- File: ahbjtag.vhd
-- Author: Edvin Catovic, Jiri Gaisler - Gaisler Research
-- Description: JTAG communication link with AHB master interface
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.misc.all;
use gaisler.libjtagcom.all;
use gaisler.jtag.all;
entity ahbjtag_bsd is
generic (
tech : integer range 0 to NTECH := 0;
hindex : integer := 0;
nsync : integer range 1 to 2 := 1;
ainst : integer range 0 to 255 := 2;
dinst : integer range 0 to 255 := 3);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
asel : in std_ulogic;
dsel : in std_ulogic;
tck : in std_ulogic;
regi : in std_ulogic;
shift : in std_ulogic;
rego : out std_ulogic
);
end;
architecture struct of ahbjtag_bsd is
-- Set REREAD to 1 to include support for re-read operation when host reads
-- out data register before jtagcom has completed the current AMBA access and
-- returned to state 'shft'.
constant REREAD : integer := 1;
constant REVISION : integer := REREAD;
signal dmai : ahb_dma_in_type;
signal dmao : ahb_dma_out_type;
signal ltapi : tap_in_type;
signal ltapo : tap_out_type;
signal trst: std_ulogic;
begin
ahbmst0 : ahbmst
generic map (hindex => hindex, venid => VENDOR_GAISLER, devid => GAISLER_AHBJTAG, version => REVISION)
port map (rst, clk, dmai, dmao, ahbi, ahbo);
jtagcom0 : jtagcom generic map (isel => 1, nsync => nsync, ainst => ainst, dinst => dinst, reread => REREAD)
port map (rst, clk, ltapo, ltapi, dmao, dmai, tck, trst);
ltapo.asel <= asel;
ltapo.dsel <= dsel;
ltapo.tck <= tck;
ltapo.tdi <= regi;
ltapo.shift <= shift;
ltapo.reset <= '0';
ltapo.inst <= (others => '0');
rego <= ltapi.tdo;
trst <= '1';
-- pragma translate_off
bootmsg : report_version
generic map ("ahbjtag AHB Debug JTAG rev " & tost(REVISION));
-- pragma translate_on
end;
| gpl-3.0 | e938b2b1e0378a4b32b9a683077dadaa | 0.61052 | 3.876289 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/techmap/altera_mf/clkgen_altera_mf.vhd | 1 | 7,155 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library altera_mf;
use altera_mf.altpll;
-- pragma translate_on
entity altera_pll is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
clk_freq : integer := 25000;
clk2xen : integer := 0;
sdramen : integer := 0
);
port (
inclk0 : in std_ulogic;
c0 : out std_ulogic;
c0_2x : out std_ulogic;
e0 : out std_ulogic;
locked : out std_ulogic
);
end;
architecture rtl of altera_pll is
component altpll
generic (
operation_mode : string := "NORMAL" ;
inclk0_input_frequency : positive;
width_clock : positive := 6;
clk0_multiply_by : positive := 1;
clk0_divide_by : positive := 1;
clk1_multiply_by : positive := 1;
clk1_divide_by : positive := 1;
extclk0_multiply_by : positive := 1;
extclk0_divide_by : positive := 1
);
port (
inclk : in std_logic_vector(1 downto 0);
clkena : in std_logic_vector(5 downto 0);
extclkena : in std_logic_vector(3 downto 0);
clk : out std_logic_vector(width_clock-1 downto 0);
extclk : out std_logic_vector(3 downto 0);
locked : out std_logic
);
end component;
signal clkena : std_logic_vector (5 downto 0);
signal clkout : std_logic_vector (5 downto 0);
signal inclk : std_logic_vector (1 downto 0);
signal extclk : std_logic_vector (3 downto 0);
constant clk_period : integer := 1000000000/clk_freq;
constant CLK_MUL2X : integer := clk_mul * 2;
begin
clkena(5 downto 2) <= (others => '0');
noclk2xgen: if (clk2xen = 0) generate clkena(1 downto 0) <= "01"; end generate;
clk2xgen: if (clk2xen /= 0) generate clkena(1 downto 0) <= "11"; end generate;
inclk <= '0' & inclk0;
c0 <= clkout(0); c0_2x <= clkout(1); e0 <= extclk(0);
sden : if sdramen = 1 generate
altpll0 : altpll
generic map (
operation_mode => "ZERO_DELAY_BUFFER", inclk0_input_frequency => clk_period,
extclk0_multiply_by => clk_mul, extclk0_divide_by => clk_div,
clk0_multiply_by => clk_mul, clk0_divide_by => clk_div,
clk1_multiply_by => CLK_MUL2X, clk1_divide_by => clk_div)
port map ( clkena => clkena, inclk => inclk, extclkena => clkena(3 downto 0),
clk => clkout, locked => locked, extclk => extclk);
end generate;
nosd : if sdramen = 0 generate
altpll0 : altpll
generic map (
operation_mode => "NORMAL", inclk0_input_frequency => clk_period,
extclk0_multiply_by => clk_mul, extclk0_divide_by => clk_div,
clk0_multiply_by => clk_mul, clk0_divide_by => clk_div,
clk1_multiply_by => CLK_MUL2X, clk1_divide_by => clk_div)
port map ( clkena => clkena, inclk => inclk, extclkena => clkena(3 downto 0),
clk => clkout, locked => locked, extclk => extclk);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library altera_mf;
library grlib;
use grlib.stdlib.all;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity clkgen_altera_mf is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
sdinvclk : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000;
clk2xen : integer := 0);
port (
clkin : in std_logic;
pciclkin: in std_logic;
clk : out std_logic; -- main clock
clkn : out std_logic; -- inverted main clock
clk2x : out std_logic; -- double clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type);
end;
architecture rtl of clkgen_altera_mf is
constant VERSION : integer := 1;
constant CLKIN_PERIOD : integer := 20;
signal clk_i : std_logic;
signal clkint, pciclkint : std_logic;
signal pllclk, pllclkn : std_logic; -- generated clocks
signal s_clk : std_logic;
-- altera pll
component altera_pll
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
clk_freq : integer := 25000;
clk2xen : integer := 0;
sdramen : integer := 0
);
port (
inclk0 : in std_ulogic;
e0 : out std_ulogic;
c0 : out std_ulogic;
c0_2x : out std_ulogic;
locked : out std_ulogic);
end component;
begin
cgo.pcilock <= '1';
-- c0 : if (PCISYSCLK = 0) generate
-- Clkint <= Clkin;
-- end generate;
-- c1 : if (PCISYSCLK = 1) generate
-- Clkint <= pciclkin;
-- end generate;
-- c2 : if (PCIEN = 1) generate
-- p0 : if (PCIDLL = 1) generate
-- pciclkint <= pciclkin;
-- pciclk <= pciclkint;
-- end generate;
-- p1 : if (PCIDLL = 0) generate
-- u0 : if (PCISYSCLK = 0) generate
-- pciclkint <= pciclkin;
-- end generate;
-- pciclk <= clk_i when (PCISYSCLK = 1) else pciclkint;
-- end generate;
-- end generate;
-- c3 : if (PCIEN = 0) generate
-- pciclk <= Clkint;
-- end generate;
c0: if (PCISYSCLK = 0) or (PCIEN = 0) generate
clkint <= clkin;
end generate c0;
c1: if PCIEN /= 0 generate
d0: if PCISYSCLK = 1 generate
clkint <= pciclkin;
end generate d0;
pciclk <= pciclkin;
end generate c1;
c2: if PCIEN = 0 generate
pciclk <= '0';
end generate c2;
sdclk_pll : altera_pll
generic map (clk_mul, clk_div, freq, clk2xen, sdramen)
port map ( inclk0 => clkint, e0 => sdclk, c0 => s_clk, c0_2x => clk2x,
locked => cgo.clklock);
clk <= s_clk;
clkn <= not s_clk;
-- pragma translate_off
bootmsg : report_version
generic map (
"clkgen_altera" & ": altpll sdram/pci clock generator, version " & tost(VERSION),
"clkgen_altera" & ": Frequency " & tost(freq) & " KHz, PLL scaler " & tost(clk_mul) & "/" & tost(clk_div));
-- pragma translate_on
end;
| gpl-3.0 | f896d420932b6abcd398f8ff03a50425 | 0.592453 | 3.476676 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/gr1553b/gr1553b_nlw.vhd | 1 | 6,481 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: gr1553b_nlw
-- File: gr1553b_nlw.vhd
-- Author: Magnus Hjorth - Aeroflex Gaisler
-- Description: Netlist wrapper for GR1553B
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.all;
library techmap;
use techmap.netcomp.all;
library gaisler;
use gaisler.gr1553b_pkg.all;
entity gr1553b_nlw is
generic(
tech: integer := 0;
hindex: integer := 0;
pindex : integer := 0;
paddr: integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
bc_enable: integer range 0 to 1 := 1;
rt_enable: integer range 0 to 1 := 1;
bm_enable: integer range 0 to 1 := 1;
bc_timer: integer range 0 to 2 := 1;
bc_rtbusmask: integer range 0 to 1 := 1;
extra_regkeys: integer range 0 to 1 := 0;
syncrst: integer range 0 to 2 := 0;
ahbendian: integer := 0;
bm_filters: integer range 0 to 1 := 1;
codecfreq: integer := 20;
sameclk: integer range 0 to 1 := 0;
codecver: integer range 0 to 2 := 0
);
port(
clk: in std_logic;
rst: in std_logic;
ahbmi: in ahb_mst_in_type;
ahbmo: out ahb_mst_out_type;
apbsi: in apb_slv_in_type;
apbso: out apb_slv_out_type;
auxin: in gr1553b_auxin_type;
auxout: out gr1553b_auxout_type;
codec_clk: in std_logic;
codec_rst: in std_logic;
txout: out gr1553b_txout_type;
txout_fb: in gr1553b_txout_type;
rxin: in gr1553b_rxin_type
);
end;
architecture rtl of gr1553b_nlw is
signal mi_hgrant,mi_hready,mo_hbusreq,mo_hwrite,si_psel,si_penable,si_pwrite,so_pirq: std_logic;
signal mi_hresp,mo_htrans: std_logic_vector(1 downto 0);
signal mo_hsize,mo_hburst: std_logic_vector(2 downto 0);
signal mi_hrdata,mo_haddr,mo_hwdata,si_pwdata,so_prdata: std_logic_vector(31 downto 0);
signal si_paddr: std_logic_vector(7 downto 0);
signal bcsync,rtsync,busreset,rtaddrp: std_logic;
signal rtaddr: std_logic_vector(4 downto 0);
signal busainen,busainp,busainn,busaouten,busaoutp,busaoutn: std_logic;
signal busbinen,busbinp,busbinn,busbouten,busboutp,busboutn: std_logic;
begin
geninf: if tech=0 generate
x: gr1553b_stdlogic
generic map (bc_enable,rt_enable,bm_enable,bc_timer,bc_rtbusmask,extra_regkeys,syncrst,
ahbendian,bm_filters,codecfreq,sameclk,codecver)
port map (clk,rst,codec_clk,codec_rst,
mi_hgrant,mi_hready,mi_hresp,mi_hrdata,
mo_hbusreq,mo_htrans,mo_haddr,mo_hwrite,mo_hsize,mo_hburst,mo_hwdata,
si_psel,si_penable,si_paddr,si_pwrite,si_pwdata,
so_prdata,so_pirq,
bcsync,rtsync,busreset,rtaddr,rtaddrp,
busainen,busainp,busainn,busaouten,busaoutp,busaoutn,
busbinen,busbinp,busbinn,busbouten,busboutp,busboutn);
end generate;
gennetl : if tech /= 0 generate
x: gr1553b_net
generic map (tech,
bc_enable,rt_enable,bm_enable,bc_timer,bc_rtbusmask,extra_regkeys,syncrst,
ahbendian,bm_filters,codecfreq,sameclk,codecver)
port map (clk,rst,codec_clk,codec_rst,
mi_hgrant,mi_hready,mi_hresp,mi_hrdata,
mo_hbusreq,mo_htrans,mo_haddr,mo_hwrite,mo_hsize,mo_hburst,mo_hwdata,
si_psel,si_penable,si_paddr,si_pwrite,si_pwdata,
so_prdata,so_pirq,
bcsync,rtsync,busreset,rtaddr,rtaddrp,
busainen,busainp,busainn,busaouten,busaoutp,busaoutn,
busbinen,busbinp,busbinn,busbouten,busboutp,busboutn);
end generate;
mi_hgrant <= ahbmi.hgrant(hindex);
mi_hready <= ahbmi.hready;
mi_hresp <= ahbmi.hresp;
mi_hrdata <= ahbreadword(ahbmi.hrdata);
ahbmo.hbusreq <= mo_hbusreq;
ahbmo.hlock <= '0';
ahbmo.htrans <= mo_htrans;
ahbmo.haddr <= mo_haddr;
ahbmo.hwrite <= mo_hwrite;
ahbmo.hsize <= mo_hsize;
ahbmo.hburst <= mo_hburst;
ahbmo.hwdata <= ahbdrivedata(mo_hwdata);
ahbmo.hprot <= "0011";
ahbmo.hirq <= (others => '0');
si_psel <= apbsi.psel(pindex);
si_penable <= apbsi.penable;
si_paddr <= apbsi.paddr(7 downto 0);
si_pwrite <= apbsi.pwrite;
si_pwdata <= apbsi.pwdata;
apbso.prdata <= so_prdata;
p : process(so_pirq)
variable irqv : std_logic_vector(NAHBIRQ-1 downto 0);
begin
irqv := (others => '0');
irqv(pirq) := so_pirq;
apbso.pirq <= irqv;
end process p;
bcsync <= auxin.extsync;
auxout.rtsync <= rtsync;
auxout.busreset <= busreset;
rtaddr <= auxin.rtaddr;
rtaddrp <= auxin.rtpar;
txout.busA_txP <= busaoutp;
txout.busA_txN <= busaoutn;
txout.busA_txen <= busaouten;
txout.busA_txin <= not busaouten;
txout.busA_rxen <= busainen;
txout.busB_txP <= busboutp;
txout.busB_txN <= busboutn;
txout.busB_txen <= busbouten;
txout.busB_txin <= not busbouten;
txout.busB_rxen <= busbinen;
busainp <= rxin.busA_rxP;
busainn <= rxin.busA_rxN;
busbinp <= rxin.busB_rxP;
busbinn <= rxin.busB_rxN;
ahbmo.hindex <= hindex;
ahbmo.hconfig <= (0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_GR1553B, gr1553b_version, gr1553b_cfgver, 0 ),
others => zero32);
apbso.pindex <= pindex;
apbso.pconfig <= (0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_GR1553B, gr1553b_version, gr1553b_cfgver, pirq),
1 => apb_iobar(paddr,pmask));
end;
| gpl-3.0 | 4b5900c97143de65c8f07131d4cb757f | 0.637247 | 3.320184 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-minimal/testbench.vhd | 1 | 3,929 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
use work.debug.all;
use work.config.all;
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
clkperiod : integer := 10 -- system clock period
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sdramfile : string := "ram.srec"; -- sdram contents
constant ct : integer := clkperiod/2;
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal rstn : std_logic;
signal error : std_logic;
-- PROM flash
signal address : std_logic_vector(26 downto 0):=(others =>'0');
signal data : std_logic_vector(31 downto 0);
signal RamCE : std_logic;
signal oen : std_ulogic;
signal writen : std_ulogic;
-- Debug support unit
signal dsubre : std_ulogic;
-- AHB Uart
signal dsurx : std_ulogic;
signal dsutx : std_ulogic;
-- APB Uart
signal urxd : std_ulogic;
signal utxd : std_ulogic;
-- Output signals for LEDs
signal led : std_logic_vector(15 downto 0);
begin
-- clock and reset
clk <= not clk after ct * 1 ns;
rst <= '1', '0' after 100 ns;
rstn <= not rst;
dsubre <= '0';
urxd <= 'H';
d3 : entity work.leon3mp
generic map (fabtech, memtech, padtech, clktech)
port map (
clk => clk,
btnCpuResetn => rstn,
-- PROM
address => address(22 downto 0),
data => data(31 downto 16),
RamOE => oen,
RamWE => writen,
RamCE => RamCE,
-- AHB Uart
RsRx => dsurx,
RsTx => dsutx,
-- Output signals for LEDs
led => led
);
sram0 : sram
generic map (index => 4, abits => 24, fname => sdramfile)
port map (address(23 downto 0), data(31 downto 24), RamCE, writen, oen);
sram1 : sram
generic map (index => 5, abits => 24, fname => sdramfile)
port map (address(23 downto 0), data(23 downto 16), RamCE, writen, oen);
led(3) <= 'L'; -- ERROR pull-down
error <= not led(3);
iuerr : process
begin
wait for 5 us;
assert (to_X01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure;
end process;
data <= buskeep(data) after 5 ns;
end;
| gpl-3.0 | 9e2eb7d17bf3708ecaa0de98e752ce59 | 0.576228 | 4.054696 | false | false | false | false |
EliasLuiz/TCC | Teste/MemoTableTLRUCounter.vhd | 1 | 3,682 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
use work.Constants.all;
use work.DefTypes.all;
--ENTITY MemoTableTLRUCounter IS
ENTITY TraceMemory IS
PORT
(
Clock : IN STD_LOGIC := '1';
WAddress : IN STD_LOGIC_VECTOR (MemoTableTWayAddressLenght-1 DOWNTO 0);
--WData : IN MemoTableTLRUCounterBus;
WEnable : IN STD_LOGIC := '0';
RAddress : IN STD_LOGIC_VECTOR (MemoTableTWayAddressLenght-1 DOWNTO 0);
ValidRead: IN STD_LOGIC_VECTOR (MemoTableTAssociativity-1 DOWNTO 0);
RData : BUFFER MemoTableTLRUCounterBus;
LRUEnable: BUFFER STD_LOGIC_VECTOR(MemoTableTAssociativity-1 DOWNTO 0);
ArrayVectorDebug: BUFFER MemoTableTRegisterArray(0 TO MemoTableTAssociativity-1);
MinimumRegisterDebug: BUFFER MemoTableTRegister
);
--END MemoTableTLRUCounter;
END TraceMemory;
--ARCHITECTURE SYN OF MemoTableTLRUCounter IS
ARCHITECTURE SYN OF TraceMemory IS
COMPONENT MemoTableTLRUCounterWay
PORT (
Clock : IN STD_LOGIC := '1';
WAddress : IN STD_LOGIC_VECTOR (MemoTableTWayAddressLenght-1 DOWNTO 0);
WData : IN MemoTableTLRUCounterEntry;
WEnable : IN STD_LOGIC := '0';
RAddress : IN STD_LOGIC_VECTOR (MemoTableTWayAddressLenght-1 DOWNTO 0);
RData : OUT MemoTableTLRUCounterEntry
);
END COMPONENT;
COMPONENT Minimum IS
GENERIC(
InputArrayLenght: integer --MemoTableTRegisterArray'LEFT+1
);
PORT(
ArrayVector : IN MemoTableTRegisterArray;
MinimumRegister: OUT MemoTableTRegister
);
END COMPONENT;
SIGNAL LRURegisterAux: MemoTableTRegisterArray(0 TO MemoTableTAssociativity-1);
SIGNAL MinimumRegisterAux: MemoTableTRegister;
SIGNAL WriteEnable: STD_LOGIC;
SIGNAL WriteEnableAux: STD_LOGIC_VECTOR(MemoTableTAssociativity-1 DOWNTO 0);
--SIGNAL RData: MemoTableTLRUCounterBus;
TYPE LRUCounterLogicBus IS ARRAY(0 TO MemoTableTAssociativity-1) OF
STD_LOGIC_VECTOR(MemoTableTLRUCounterEntryWidth+MemoTableTAssociativityAddress-1 DOWNTO 0);
SIGNAL RDataAux: MemoTableTLRUCounterBus;
SIGNAL RDataLogicAux: LRUCounterLogicBus;
SIGNAL WData: MemoTableTLRUCounterBus;
BEGIN
mem: FOR i IN 0 TO MemoTableTAssociativity-1 GENERATE
--Mapping the memory way
MemoTableTLRUCounterWay_cmp : MemoTableTLRUCounterWay
PORT MAP (
WAddress => WAddress,
Clock => Clock,
WData => WData(i),
WEnable => WriteEnable,
RAddress => RAddress,
RData => RData(i)
);
--Transforming the read data into the format used by the minimum unit
RDataLogicAux(i) <= RData(i).LRUCounter(MemoTableTLRUCounterEntryWidth-1 DOWNTO 0)
& IntegerToStdLogic(i, MemoTableTAssociativityAddress);
LRURegisterAux(i) <= LRUCounterStdLogicToRegister(RDataLogicAux(i));
--Setting the output with the decoded identifier for the minimum value
LRUEnable(i) <= WEnable WHEN i = StdLogicToInteger(MinimumRegisterAux.Identifier) ELSE '0';
--Setting the data to be written (new counter value)
WData(i).LRUCounter <=
(OTHERS => '1') WHEN WriteEnableAux(i) = '1' ELSE
(OTHERS => '0') WHEN StdLogicToInteger(RData(i).LRUCounter) = 0 ELSE
IntegerToStdLogic(StdLogicToInteger(RData(i).LRUCounter)
- 1, MemoTableTLRUCounterEntryWidth);
END GENERATE mem;
Minimum_cmp : Minimum
GENERIC MAP(
InputArrayLenght => MemoTableTAssociativity
)
PORT MAP(
ArrayVector => LRURegisterAux,
MinimumRegister => MinimumRegisterAux
);
ArrayVectorDebug <= LRURegisterAux;
MinimumRegisterDebug <= MinimumRegisterAux;
WriteEnableAux(MemoTableTAssociativity-1 DOWNTO 0)
<= LRUEnable(MemoTableTAssociativity-1 DOWNTO 0)
OR ValidRead(MemoTableTAssociativity-1 DOWNTO 0);
WriteEnable <= '0' WHEN StdLogicToInteger(WriteEnableAux) = 0 ELSE '1';
END SYN;
| gpl-3.0 | bb01bc872a0e4aa5dd769365b6e8a9aa | 0.758827 | 3.048013 | false | false | false | false |
GLADICOS/SPACEWIRESYSTEMC | rtl/RTL_SL/spwpkg.vhd | 1 | 16,278 | --
-- SpaceWire VHDL package
--
library ieee;
use ieee.std_logic_1164.all;
package spwpkg is
-- Indicates a platform-specific implementation.
type spw_implementation_type is ( impl_generic, impl_fast );
-- Input signals to spwlink.
type spw_link_in_type is record
-- Enables automatic link start on receipt of a NULL character.
autostart: std_logic;
-- Enables link start once the Ready state is reached.
-- Without either "autostart" or "linkstart", the link remains in
-- state Ready.
linkstart: std_logic;
-- Do not start link (overrides "linkstart" and "autostart") and/or
-- disconnect the currently running link.
linkdis: std_logic;
-- Number of bytes available in the receive buffer. Used to for
-- flow-control operation. At least 8 bytes must be available
-- initially, otherwise the link can not start. Values larger than 63
-- are irrelevant and may be presented as 63. The available room may
-- decrease by one byte due to the reception of an N-Char; in that case
-- the "rxroom" signal must be updated on the clock following the clock
-- on which "rxchar" is high. Under no other circumstances may "rxroom"
-- be decreased.
rxroom: std_logic_vector(5 downto 0);
-- High for one clock cycle to request transmission of a TimeCode.
-- The request is registered inside spwxmit until it can be processed.
tick_in: std_logic;
-- Control bits of the TimeCode to be sent.
-- Must be valid while tick_in is high.
ctrl_in: std_logic_vector(1 downto 0);
-- Counter value of the TimeCode to be sent.
-- Must be valid while tick_in is high.
time_in: std_logic_vector(5 downto 0);
-- Requests transmission of an N-Char.
-- Keep this signal high until confirmed by "txack".
txwrite: std_logic;
-- Control flag to be sent with the next N-Char.
-- Must be valid while "txwrite" is high.
txflag: std_logic;
-- Byte to be sent, or "00000000" for EOP or "00000001" for EEP.
-- Must be valid while "txwrite" is high.
txdata: std_logic_vector(7 downto 0);
end record;
-- Output signals from spwlink.
type spw_link_out_type is record
-- High if the link state machine is currently in state Started.
started: std_logic;
-- High if the link state machine is currently in state Connecting.
connecting: std_logic;
-- High if the link state machine is currently in state Run.
running: std_logic;
-- Disconnect detected in state Run. Triggers a reset and reconnect.
-- This indication is auto-clearing.
errdisc: std_logic;
-- Parity error detected in state Run. Triggers a reset and reconnect.
-- This indication is auto-clearing.
errpar: std_logic;
-- Invalid escape sequence detected in state Run.
-- Triggers a reset and reconnect; auto-clearing.
erresc: std_logic;
-- Credit error detected. Triggers a reset and reconnect.
-- This indication is auto-clearing.
errcred: std_logic;
-- High to confirm the transmission of an N-Char.
-- This is a Wishbone-style handshake signal. It has a combinatorial
-- dependency on "txwrite".
txack: std_logic;
-- High for one clock cycle if a TimeCode was just received.
-- Verification of the TimeCode as described in 8.12.2 of ECSS-E-50
-- is not implemented; all received timecodes are reported.
tick_out: std_logic;
-- Control bits of last received TimeCode.
ctrl_out: std_logic_vector(1 downto 0);
-- Counter value of last received TimeCode.
time_out: std_logic_vector(5 downto 0);
-- High for one clock cycle if an N-Char (data byte or EOP or EEP) was
-- just received. The data bits must be accepted immediately from
-- "rxflag" and "rxdata".
rxchar: std_logic;
-- High if the received character is EOP or EEP, low if it is a data
-- byte. Valid when "rxchar" is high.
rxflag: std_logic;
-- Received byte, or "00000000" for EOP or "00000001" for EEP.
-- Valid when "rxchar" is high.
rxdata: std_logic_vector(7 downto 0);
end record;
-- Output signals from spwrecv to spwlink.
type spw_recv_out_type is record
-- High if at least one signal change was seen since enable.
-- Resets to low when rxen is low.
gotbit: std_logic;
-- High if at least one valid NULL pattern was detected since enable.
-- Resets to low when rxen is low.
gotnull: std_logic;
-- High for one clock cycle if an FCT token was just received.
gotfct: std_logic;
-- High for one clock cycle if a TimeCode was just received.
tick_out: std_logic;
-- Control bits of last received TimeCode.
ctrl_out: std_logic_vector(1 downto 0);
-- Counter value of last received TimeCode.
time_out: std_logic_vector(5 downto 0);
-- High for one clock cycle if an N-Char (data byte or EOP/EEP) was just received.
rxchar: std_logic;
-- High if rxchar is high and the received character is EOP or EEP.
-- Low if rxchar is high and the received character is a data byte.
rxflag: std_logic;
-- Received byte, or "00000000" for EOP or "00000001" for EEP.
-- Valid when "rxchar" is high.
rxdata: std_logic_vector(7 downto 0);
-- Disconnect detected (after a signal change was seen).
-- Resets to low when rxen is low or when a signal change is seen.
errdisc: std_logic;
-- Parity error detected (after a valid NULL pattern was seen).
-- Sticky; resets to low when rxen is low.
errpar: std_logic;
-- Escape sequence error detected (after a valid NULL pattern was seen).
-- Sticky; resets to low when rxen is low.
erresc: std_logic;
end record;
-- Input signals to spwxmit from spwlink.
type spw_xmit_in_type is record
-- High to enable transmitter; low to disable and reset transmitter.
txen: std_logic;
-- Indicates that only NULL characters may be transmitted.
stnull: std_logic;
-- Indicates that only NULL and/or FCT characters may be transmitted.
stfct: std_logic;
-- Requests transmission of an FCT character.
-- Keep this signal high until confirmed by "fctack".
fct_in: std_logic;
-- High for one clock cycle to request transmission of a TimeCode.
-- The request is registered inside spwxmit until it can be processed.
tick_in: std_logic;
-- Control bits of the TimeCode to be sent.
-- Must be valid while "tick_in" is high.
ctrl_in: std_logic_vector(1 downto 0);
-- Counter value of the TimeCode to be sent.
-- Must be valid while "tick_in" is high.
time_in: std_logic_vector(5 downto 0);
-- Request transmission of an N-Char.
-- Keep this signal high until confirmed by "txack".
txwrite: std_logic;
-- Control flag to be sent with the next N-Char.
-- Must be valid while "txwrite" is high.
txflag: std_logic;
-- Byte to send, or "00000000" for EOP or "00000001" for EEP.
-- Must be valid while "txwrite" is high.
txdata: std_logic_vector(7 downto 0);
end record;
-- Output signals from spwxmit to spwlink.
type spw_xmit_out_type is record
-- High to confirm transmission on an FCT character.
-- This is a Wishbone-style handshaking signal; it is combinatorially
-- dependent on "fct_in".
fctack: std_logic;
-- High to confirm transmission of an N-Char.
-- This is a Wishbone-style handshaking signal; it is combinatorially
-- dependent on both "fct_in" and "txwrite".
txack: std_logic;
end record;
-- Character-stream interface
component spwstream is
generic (
sysfreq: real; -- clk freq in Hz
txclkfreq: real := 0.0; -- txclk freq in Hz
rximpl: spw_implementation_type := impl_generic;
rxchunk: integer range 1 to 4 := 1; -- max bits per clk
tximpl: spw_implementation_type := impl_generic;
rxfifosize_bits: integer range 6 to 14 := 11; -- rx fifo size
txfifosize_bits: integer range 2 to 14 := 11 -- tx fifo size
);
port (
clk: in std_logic; -- system clock
rxclk: in std_logic; -- receiver sample clock
txclk: in std_logic; -- transmit clock
rst: in std_logic; -- synchronous reset
autostart: in std_logic; -- automatic link start
linkstart: in std_logic; -- forced link start
linkdis: in std_logic; -- stop link
txdivcnt: in std_logic_vector(7 downto 0); -- tx scale factor
tick_in: in std_logic; -- request timecode xmit
ctrl_in: in std_logic_vector(1 downto 0);
time_in: in std_logic_vector(5 downto 0);
txwrite: in std_logic; -- request character xmit
txflag: in std_logic; -- control flag of tx char
txdata: in std_logic_vector(7 downto 0);
txrdy: out std_logic; -- room in tx fifo
txhalff: out std_logic; -- tx fifo half full
tick_out: out std_logic; -- timecode received
ctrl_out: out std_logic_vector(1 downto 0);
time_out: out std_logic_vector(5 downto 0);
rxvalid: out std_logic; -- rx fifo not empty
rxhalff: out std_logic; -- rx fifo half full
rxflag: out std_logic; -- control flag of rx char
rxdata: out std_logic_vector(7 downto 0);
rxread: in std_logic; -- accept rx character
started: out std_logic; -- link in Started state
connecting: out std_logic; -- link in Connecting state
running: out std_logic; -- link in Run state
errdisc: out std_logic; -- disconnect error
errpar: out std_logic; -- parity error
erresc: out std_logic; -- escape error
errcred: out std_logic; -- credit error
spw_di: in std_logic;
spw_si: in std_logic;
spw_do: out std_logic;
spw_so: out std_logic
);
end component spwstream;
-- Link Level Interface
component spwlink is
generic (
reset_time: integer -- reset time in clocks (6.4 us)
);
port (
clk: in std_logic; -- system clock
rst: in std_logic; -- synchronous reset (active-high)
linki: in spw_link_in_type;
linko: out spw_link_out_type;
rxen: out std_logic;
recvo: in spw_recv_out_type;
xmiti: out spw_xmit_in_type;
xmito: in spw_xmit_out_type
);
end component spwlink;
-- Receiver
component spwrecv is
generic (
disconnect_time: integer range 1 to 255; -- disconnect period in system clock cycles
rxchunk: integer range 1 to 4 -- nr of bits per system clock
);
port (
clk: in std_logic; -- system clock
rxen: in std_logic; -- receiver enabled
recvo: out spw_recv_out_type;
inact: in std_logic;
inbvalid: in std_logic;
inbits: in std_logic_vector(rxchunk-1 downto 0)
);
end component spwrecv;
-- Transmitter (generic implementation)
component spwxmit is
port (
clk: in std_logic; -- system clock
rst: in std_logic; -- synchronous reset (active-high)
divcnt: in std_logic_vector(7 downto 0);
xmiti: in spw_xmit_in_type;
xmito: out spw_xmit_out_type;
spw_do: out std_logic; -- tx data to SPW bus
spw_so: out std_logic -- tx strobe to SPW bus
);
end component spwxmit;
-- Transmitter (separate tx clock domain)
component spwxmit_fast is
port (
clk: in std_logic; -- system clock
txclk: in std_logic; -- transmit clock
rst: in std_logic; -- synchronous reset (active-high)
divcnt: in std_logic_vector(7 downto 0);
xmiti: in spw_xmit_in_type;
xmito: out spw_xmit_out_type;
spw_do: out std_logic; -- tx data to SPW bus
spw_so: out std_logic -- tx strobe to SPW bus
);
end component spwxmit_fast;
-- Front-end for SpaceWire Receiver (generic implementation)
component spwrecvfront_generic is
port (
clk: in std_logic; -- system clock
rxen: in std_logic; -- high to enable receiver
inact: out std_logic; -- high if activity on input
inbvalid: out std_logic; -- high if inbits contains a valid received bit
inbits: out std_logic_vector(0 downto 0); -- received bit
spw_di: in std_logic; -- Data In signal from SpaceWire bus
spw_si: in std_logic -- Strobe In signal from SpaceWire bus
);
end component spwrecvfront_generic;
-- Front-end for SpaceWire Receiver (separate rx clock domain)
component spwrecvfront_fast is
generic (
rxchunk: integer range 1 to 4 -- max number of bits per system clock
);
port (
clk: in std_logic; -- system clock
rxclk: in std_logic; -- sample clock (DDR)
rxen: in std_logic; -- high to enable receiver
inact: out std_logic; -- high if activity on input
inbvalid: out std_logic; -- high if inbits contains a valid group of received bits
inbits: out std_logic_vector(rxchunk-1 downto 0); -- received bits
spw_di: in std_logic; -- Data In signal from SpaceWire bus
spw_si: in std_logic -- Strobe In signal from SpaceWire bus
);
end component spwrecvfront_fast;
-- Synchronous two-port memory.
component spwram is
generic (
abits: integer;
dbits: integer );
port (
rclk: in std_logic;
wclk: in std_logic;
ren: in std_logic;
raddr: in std_logic_vector(abits-1 downto 0);
rdata: out std_logic_vector(dbits-1 downto 0);
wen: in std_logic;
waddr: in std_logic_vector(abits-1 downto 0);
wdata: in std_logic_vector(dbits-1 downto 0) );
end component spwram;
-- Double flip-flop synchronizer.
component syncdff is
port (
clk: in std_logic; -- clock (destination domain)
rst: in std_logic; -- asynchronous reset, active-high
di: in std_logic; -- input data
do: out std_logic ); -- output data
end component syncdff;
end package;
| gpl-3.0 | 41dc977c7b13c43fb85a23ccd9b4347d | 0.555904 | 4.193199 | false | false | false | false |
pwsoft/fpga_examples | rtl/ttl/ttl_74163.vhd | 1 | 3,684 | -- -----------------------------------------------------------------------
--
-- Syntiac VHDL support files.
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2018 by Peter Wendrich ([email protected])
-- http://www.syntiac.com
--
-- This source file is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- -----------------------------------------------------------------------
-- Presettable synchronous 4-bit binary counter with synchronous reset
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use work.ttl_pkg.all;
-- -----------------------------------------------------------------------
entity ttl_74163 is
generic (
latency : integer := 3
);
port (
emuclk : in std_logic;
p1 : in ttl_t; -- MRn
p2 : in ttl_t; -- CP
p3 : in ttl_t; -- D0
p4 : in ttl_t; -- D1
p5 : in ttl_t; -- D2
p6 : in ttl_t; -- D3
p7 : in ttl_t; -- CEP
p9 : in ttl_t; -- PEn
p10 : in ttl_t; -- CET
p11 : out ttl_t; -- Q3
p12 : out ttl_t; -- Q2
p13 : out ttl_t; -- Q1
p14 : out ttl_t; -- Q0
p15 : out ttl_t -- TC
);
end entity;
architecture rtl of ttl_74163 is
signal q0_reg : ttl_t := ZERO;
signal q1_reg : ttl_t := ZERO;
signal q2_reg : ttl_t := ZERO;
signal q3_reg : ttl_t := ZERO;
signal tc_reg : ttl_t := ZERO;
signal cp : std_logic;
signal cp_dly : std_logic := '0';
begin
p11_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => q3_reg, q => p11);
p12_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => q2_reg, q => p12);
p13_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => q1_reg, q => p13);
p14_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => q0_reg, q => p14);
p15_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => tc_reg, q => p15);
cp <= ttl2std(p2);
process(emuclk)
begin
if rising_edge(emuclk) then
cp_dly <= cp;
if (cp = '1') and (cp_dly = '0') then
if is_low(p1) then
-- Master reset
q0_reg <= ZERO;
q1_reg <= ZERO;
q2_reg <= ZERO;
q3_reg <= ZERO;
elsif is_low(p9) then
-- Load constant
q0_reg <= buffered(p3);
q1_reg <= buffered(p4);
q2_reg <= buffered(p5);
q3_reg <= buffered(p6);
elsif is_high(p7) and is_high(p10) then
-- Count
q0_reg <= not q0_reg;
if is_high(q0_reg) then
q1_reg <= not q1_reg;
end if;
if is_high(q0_reg) and is_high(q1_reg) then
q2_reg <= not q2_reg;
end if;
if is_high(q0_reg) and is_high(q1_reg) and is_high(q2_reg) then
q3_reg <= not q3_reg;
end if;
tc_reg <= ZERO;
if is_low(q0_reg) and is_high(q1_reg) and is_high(q2_reg) and is_high(q3_reg) then
tc_reg <= ONE;
end if;
end if;
end if;
end if;
end process;
end architecture;
| lgpl-2.1 | 76a94492f40f462fbacea994f5477411 | 0.55836 | 2.956661 | false | false | false | false |
hoglet67/CoPro6502 | src/T80/T80_RegX.vhd | 8 | 5,101 | -- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- T80 Registers for Xilinx Select RAM
--
-- Version : 0244
--
-- Copyright (c) 2002 Daniel Wallner ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t51/
--
-- Limitations :
--
-- File history :
--
-- 0242 : Initial release
--
-- 0244 : Removed UNISIM library and added componet declaration
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity T80_Reg is
port(
Clk : in std_logic;
CEN : in std_logic;
WEH : in std_logic;
WEL : in std_logic;
AddrA : in std_logic_vector(2 downto 0);
AddrB : in std_logic_vector(2 downto 0);
AddrC : in std_logic_vector(2 downto 0);
DIH : in std_logic_vector(7 downto 0);
DIL : in std_logic_vector(7 downto 0);
DOAH : out std_logic_vector(7 downto 0);
DOAL : out std_logic_vector(7 downto 0);
DOBH : out std_logic_vector(7 downto 0);
DOBL : out std_logic_vector(7 downto 0);
DOCH : out std_logic_vector(7 downto 0);
DOCL : out std_logic_vector(7 downto 0)
);
end T80_Reg;
architecture rtl of T80_Reg is
component RAM16X1D
port(
DPO : out std_ulogic;
SPO : out std_ulogic;
A0 : in std_ulogic;
A1 : in std_ulogic;
A2 : in std_ulogic;
A3 : in std_ulogic;
D : in std_ulogic;
DPRA0 : in std_ulogic;
DPRA1 : in std_ulogic;
DPRA2 : in std_ulogic;
DPRA3 : in std_ulogic;
WCLK : in std_ulogic;
WE : in std_ulogic);
end component;
signal ENH : std_logic;
signal ENL : std_logic;
begin
ENH <= CEN and WEH;
ENL <= CEN and WEL;
bG1: for I in 0 to 7 generate
begin
Reg1H : RAM16X1D
port map(
DPO => DOBH(i),
SPO => DOAH(i),
A0 => AddrA(0),
A1 => AddrA(1),
A2 => AddrA(2),
A3 => '0',
D => DIH(i),
DPRA0 => AddrB(0),
DPRA1 => AddrB(1),
DPRA2 => AddrB(2),
DPRA3 => '0',
WCLK => Clk,
WE => ENH);
Reg1L : RAM16X1D
port map(
DPO => DOBL(i),
SPO => DOAL(i),
A0 => AddrA(0),
A1 => AddrA(1),
A2 => AddrA(2),
A3 => '0',
D => DIL(i),
DPRA0 => AddrB(0),
DPRA1 => AddrB(1),
DPRA2 => AddrB(2),
DPRA3 => '0',
WCLK => Clk,
WE => ENL);
Reg2H : RAM16X1D
port map(
DPO => DOCH(i),
SPO => open,
A0 => AddrA(0),
A1 => AddrA(1),
A2 => AddrA(2),
A3 => '0',
D => DIH(i),
DPRA0 => AddrC(0),
DPRA1 => AddrC(1),
DPRA2 => AddrC(2),
DPRA3 => '0',
WCLK => Clk,
WE => ENH);
Reg2L : RAM16X1D
port map(
DPO => DOCL(i),
SPO => open,
A0 => AddrA(0),
A1 => AddrA(1),
A2 => AddrA(2),
A3 => '0',
D => DIL(i),
DPRA0 => AddrC(0),
DPRA1 => AddrC(1),
DPRA2 => AddrC(2),
DPRA3 => '0',
WCLK => Clk,
WE => ENL);
end generate;
end;
| gpl-3.0 | 731b8c5835ec4102b6b66d3211c3bd07 | 0.578514 | 3.246976 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/tech/umc18/components/umc_simprims.vhd | 1 | 17,478 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: umc_simprims
-- File: umc_simprims.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Simple UMC 0.18 simulation models
------------------------------------------------------------------------------
-- pragma translate_off
-- input pad
library ieee;
use ieee.std_logic_1164.all;
entity ICMT3V is port( A : in std_logic; Z : out std_logic); end ;
architecture behav of ICMT3V is begin Z <= to_X01(A) after 1 ns; end;
-- input pad with pull-up
library ieee;
use ieee.std_logic_1164.all;
entity ICMT3VPU is port( A : in std_logic; Z : out std_logic); end ;
architecture behav of ICMT3VPU is begin
Z <= to_X01(A) after 1 ns; --A <= 'H';
end;
-- input pad with pull-down
library ieee;
use ieee.std_logic_1164.all;
entity ICMT3VPD is port( A : in std_logic; Z : out std_logic); end ;
architecture behav of ICMT3VPD is begin
Z <= to_X01(A) after 1 ns; --A <= 'L';
end;
-- schmitt input pad
library ieee;
use ieee.std_logic_1164.all;
entity ISTRT3V is port( A : in std_logic; Z : out std_logic); end ;
architecture behav of ISTRT3V is begin Z <= to_X01(A) after 1 ns; end;
-- output pads
library ieee;
use ieee.std_logic_1164.all;
entity OCM3V4 is port( Z : out std_logic; A : in std_logic); end;
architecture behav of OCM3V4 is begin Z <= to_X01(A) after 3 ns; end;
library ieee;
use ieee.std_logic_1164.all;
entity OCM3V12 is port( Z : out std_logic; A : in std_logic); end;
architecture behav of OCM3V12 is begin Z <= to_X01(A) after 2 ns; end;
library ieee;
use ieee.std_logic_1164.all;
entity OCM3V24 is port( Z : out std_logic; A : in std_logic); end;
architecture behav of OCM3V24 is begin Z <= to_X01(A) after 1 ns; end;
-- tri-state output pads
library ieee;
use ieee.std_logic_1164.all;
entity OCMTR4 is port( EN : in std_logic; A : in std_logic; Z : out std_logic); end;
architecture behav of OCMTR4 is begin
Z <= to_X01(A) after 3 ns when to_X01(en) = '1' else
'Z' after 3 ns when to_X01(en) = '0' else 'X' after 3 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity OCMTR12 is port( EN : in std_logic; A : in std_logic; Z : out std_logic); end;
architecture behav of OCMTR12 is begin
Z <= to_X01(A) after 2 ns when to_X01(en) = '1' else
'Z' after 2 ns when to_X01(en) = '0' else 'X' after 2 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity OCMTR24 is port( EN : in std_logic; A : in std_logic; Z : out std_logic); end;
architecture behav of OCMTR24 is begin
Z <= to_X01(A) after 1 ns when to_X01(en) = '1' else
'Z' after 1 ns when to_X01(en) = '0' else 'X' after 1 ns;
end;
-- bidirectional pads
library ieee;
use ieee.std_logic_1164.all;
entity BICM3V4 is port( IO : inout std_logic; EN : in std_logic; A : in std_logic; Z : out std_logic); end;
architecture behav of BICM3V4 is begin
IO <= to_X01(A) after 3 ns when to_X01(en) = '1' else
'Z' after 3 ns when to_X01(en) = '0' else 'X' after 3 ns;
Z <= to_X01(IO) after 1 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity BICM3V12 is port( IO : inout std_logic; EN : in std_logic; A : in std_logic; Z : out std_logic); end;
architecture behav of BICM3V12 is begin
IO <= to_X01(A) after 2 ns when to_X01(en) = '1' else
'Z' after 2 ns when to_X01(en) = '0' else 'X' after 2 ns;
Z <= to_X01(IO) after 1 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity BICM3V24 is port( IO : inout std_logic; EN : in std_logic; A : in std_logic; Z : out std_logic); end;
architecture behav of BICM3V24 is begin
IO <= to_X01(A) after 1 ns when to_X01(en) = '1' else
'Z' after 1 ns when to_X01(en) = '0' else 'X' after 1 ns;
Z <= to_X01(IO) after 1 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity LVDS_Receiver is port( A, AN : in std_logic; Z : out std_logic); end;
architecture struct of LVDS_Receiver is
signal yn : std_ulogic := '0';
begin
yn <= to_X01(A) after 1 ns when to_x01(A xor AN) = '1' else yn after 1 ns;
Z <= yn;
end;
library ieee;
use ieee.std_logic_1164.all;
entity LVDS_Driver is port (A, Vref, HI : in std_logic; Z, ZN : out std_logic ); end;
architecture struct of LVDS_Driver is begin
Z <= A after 1 ns;
ZN <= not A after 1 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
entity LVDS_Biasmodule is port ( RefR : in std_logic; Vref, HI : out std_logic); end;
architecture struct of LVDS_Biasmodule is begin end;
-- single-port memory
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
entity UMC_SIM_SRAM is
generic (abits, dbits : integer := 8);
port (
a : in std_logic_vector(abits-1 downto 0);
data : in std_logic_vector(dbits-1 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(dbits-1 downto 0);
clk : in std_logic
);
end;
architecture behav of UMC_SIM_SRAM is
subtype memword is std_logic_vector(dbits-1 downto 0);
type mem_type is array (0 to 2**abits-1) of memword;
signal qint : memword;
begin
m : process(clk)
variable mem : mem_type;
begin
if rising_edge(clk) then
qint <= (others => 'X');
if to_X01(wen) = '0' then mem(conv_integer(a)) := data;
elsif to_X01(wen) = '1' then qint <= mem(conv_integer(a)); end if;
end if;
end process;
q <= qint when to_X01(oen) = '0' else
(others => 'Z') when to_X01(oen) = '1' else (others => 'X');
end;
library ieee;
use ieee.std_logic_1164.all;
entity SRAM_2048wx32b is
port (
a : in std_logic_vector(10 downto 0);
data : in std_logic_vector(31 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(31 downto 0);
clk : in std_logic
);
end;
architecture behav of SRAM_2048wx32b is
component UMC_SIM_SRAM is
generic (abits, dbits : integer := 8);
port (
a : in std_logic_vector(abits-1 downto 0);
data : in std_logic_vector(dbits-1 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(dbits-1 downto 0);
clk : in std_logic
);
end component;
begin
m : UMC_SIM_SRAM generic map (11, 32) port map (a, data, csn, wen, oen, q, clk);
end;
library ieee;
use ieee.std_logic_1164.all;
entity SRAM_1024wx32b is
port (
a : in std_logic_vector(9 downto 0);
data : in std_logic_vector(31 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(31 downto 0);
clk : in std_logic
);
end;
architecture behav of SRAM_1024wx32b is
component UMC_SIM_SRAM is
generic (abits, dbits : integer := 8);
port (
a : in std_logic_vector(abits-1 downto 0);
data : in std_logic_vector(dbits-1 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(dbits-1 downto 0);
clk : in std_logic
);
end component;
begin
m : UMC_SIM_SRAM generic map (10, 32) port map (a, data, csn, wen, oen, q, clk);
end;
library ieee;
use ieee.std_logic_1164.all;
entity SRAM_512wx32b is
port (
a : in std_logic_vector(8 downto 0);
data : in std_logic_vector(31 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(31 downto 0);
clk : in std_logic
);
end;
architecture behav of SRAM_512wx32b is
component UMC_SIM_SRAM is
generic (abits, dbits : integer := 8);
port (
a : in std_logic_vector(abits-1 downto 0);
data : in std_logic_vector(dbits-1 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(dbits-1 downto 0);
clk : in std_logic
);
end component;
begin
m : UMC_SIM_SRAM generic map (9, 32) port map (a, data, csn, wen, oen, q, clk);
end;
library ieee;
use ieee.std_logic_1164.all;
entity SRAM_256wx32b is
port (
a : in std_logic_vector(7 downto 0);
data : in std_logic_vector(31 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(31 downto 0);
clk : in std_logic
);
end;
architecture behav of SRAM_256wx32b is
component UMC_SIM_SRAM is
generic (abits, dbits : integer := 8);
port (
a : in std_logic_vector(abits-1 downto 0);
data : in std_logic_vector(dbits-1 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(dbits-1 downto 0);
clk : in std_logic
);
end component;
begin
m : UMC_SIM_SRAM generic map (8, 32) port map (a, data, csn, wen, oen, q, clk);
end;
library ieee;
use ieee.std_logic_1164.all;
entity SRAM_128wx32b is
port (
a : in std_logic_vector(6 downto 0);
data : in std_logic_vector(31 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(31 downto 0);
clk : in std_logic
);
end;
architecture behav of SRAM_128wx32b is
component UMC_SIM_SRAM is
generic (abits, dbits : integer := 8);
port (
a : in std_logic_vector(abits-1 downto 0);
data : in std_logic_vector(dbits-1 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(dbits-1 downto 0);
clk : in std_logic
);
end component;
begin
m : UMC_SIM_SRAM generic map (7, 32) port map (a, data, csn, wen, oen, q, clk);
end;
library ieee;
use ieee.std_logic_1164.all;
entity SRAM_64wx32b is
port (
a : in std_logic_vector(5 downto 0);
data : in std_logic_vector(31 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(31 downto 0);
clk : in std_logic
);
end;
architecture behav of SRAM_64wx32b is
component UMC_SIM_SRAM is
generic (abits, dbits : integer := 8);
port (
a : in std_logic_vector(abits-1 downto 0);
data : in std_logic_vector(dbits-1 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(dbits-1 downto 0);
clk : in std_logic
);
end component;
begin
m : UMC_SIM_SRAM generic map (6, 32) port map (a, data, csn, wen, oen, q, clk);
end;
library ieee;
use ieee.std_logic_1164.all;
entity SRAM_32wx32b is
port (
a : in std_logic_vector(4 downto 0);
data : in std_logic_vector(31 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(31 downto 0);
clk : in std_logic
);
end;
architecture behav of SRAM_32wx32b is
component UMC_SIM_SRAM is
generic (abits, dbits : integer := 8);
port (
a : in std_logic_vector(abits-1 downto 0);
data : in std_logic_vector(dbits-1 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(dbits-1 downto 0);
clk : in std_logic
);
end component;
begin
m : UMC_SIM_SRAM generic map (5, 32) port map (a, data, csn, wen, oen, q, clk);
end;
library ieee;
use ieee.std_logic_1164.all;
entity SRAM_2048wx40b is
port (
a : in std_logic_vector(10 downto 0);
data : in std_logic_vector(39 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(39 downto 0);
clk : in std_logic
);
end;
architecture behav of SRAM_2048wx40b is
component UMC_SIM_SRAM is
generic (abits, dbits : integer := 8);
port (
a : in std_logic_vector(abits-1 downto 0);
data : in std_logic_vector(dbits-1 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(dbits-1 downto 0);
clk : in std_logic
);
end component;
begin
m : UMC_SIM_SRAM generic map (11, 40) port map (a, data, csn, wen, oen, q, clk);
end;
library ieee;
use ieee.std_logic_1164.all;
entity SRAM_1024wx40b is
port (
a : in std_logic_vector(9 downto 0);
data : in std_logic_vector(39 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(39 downto 0);
clk : in std_logic
);
end;
architecture behav of SRAM_1024wx40b is
component UMC_SIM_SRAM is
generic (abits, dbits : integer := 8);
port (
a : in std_logic_vector(abits-1 downto 0);
data : in std_logic_vector(dbits-1 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(dbits-1 downto 0);
clk : in std_logic
);
end component;
begin
m : UMC_SIM_SRAM generic map (10, 40) port map (a, data, csn, wen, oen, q, clk);
end;
library ieee;
use ieee.std_logic_1164.all;
entity SRAM_512wx40b is
port (
a : in std_logic_vector(8 downto 0);
data : in std_logic_vector(39 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(39 downto 0);
clk : in std_logic
);
end;
architecture behav of SRAM_512wx40b is
component UMC_SIM_SRAM is
generic (abits, dbits : integer := 8);
port (
a : in std_logic_vector(abits-1 downto 0);
data : in std_logic_vector(dbits-1 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(dbits-1 downto 0);
clk : in std_logic
);
end component;
begin
m : UMC_SIM_SRAM generic map (9, 40) port map (a, data, csn, wen, oen, q, clk);
end;
library ieee;
use ieee.std_logic_1164.all;
entity SRAM_256wx40b is
port (
a : in std_logic_vector(7 downto 0);
data : in std_logic_vector(39 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(39 downto 0);
clk : in std_logic
);
end;
architecture behav of SRAM_256wx40b is
component UMC_SIM_SRAM is
generic (abits, dbits : integer := 8);
port (
a : in std_logic_vector(abits-1 downto 0);
data : in std_logic_vector(dbits-1 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(dbits-1 downto 0);
clk : in std_logic
);
end component;
begin
m : UMC_SIM_SRAM generic map (8, 40) port map (a, data, csn, wen, oen, q, clk);
end;
library ieee;
use ieee.std_logic_1164.all;
entity SRAM_128wx40b is
port (
a : in std_logic_vector(6 downto 0);
data : in std_logic_vector(39 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(39 downto 0);
clk : in std_logic
);
end;
architecture behav of SRAM_128wx40b is
component UMC_SIM_SRAM is
generic (abits, dbits : integer := 8);
port (
a : in std_logic_vector(abits-1 downto 0);
data : in std_logic_vector(dbits-1 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(dbits-1 downto 0);
clk : in std_logic
);
end component;
begin
m : UMC_SIM_SRAM generic map (7, 40) port map (a, data, csn, wen, oen, q, clk);
end;
library ieee;
use ieee.std_logic_1164.all;
entity SRAM_64wx40b is
port (
a : in std_logic_vector(5 downto 0);
data : in std_logic_vector(39 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(39 downto 0);
clk : in std_logic
);
end;
architecture behav of SRAM_64wx40b is
component UMC_SIM_SRAM is
generic (abits, dbits : integer := 8);
port (
a : in std_logic_vector(abits-1 downto 0);
data : in std_logic_vector(dbits-1 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(dbits-1 downto 0);
clk : in std_logic
);
end component;
begin
m : UMC_SIM_SRAM generic map (6, 40) port map (a, data, csn, wen, oen, q, clk);
end;
library ieee;
use ieee.std_logic_1164.all;
entity SRAM_32wx40b is
port (
a : in std_logic_vector(4 downto 0);
data : in std_logic_vector(39 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(39 downto 0);
clk : in std_logic
);
end;
architecture behav of SRAM_32wx40b is
component UMC_SIM_SRAM is
generic (abits, dbits : integer := 8);
port (
a : in std_logic_vector(abits-1 downto 0);
data : in std_logic_vector(dbits-1 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(dbits-1 downto 0);
clk : in std_logic
);
end component;
begin
m : UMC_SIM_SRAM generic map (5, 40) port map (a, data, csn, wen, oen, q, clk);
end;
-- pragma translate_on
| gpl-3.0 | 924650204e4ac42196d19b51c941f403 | 0.632452 | 2.732645 | false | false | false | false |
ARC-Lab-UF/UAA | src/fifo.vhd | 1 | 5,358 | -- Copyright (c) 2015 University of Florida
--
-- This file is part of uaa.
--
-- uaa is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- uaa is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with uaa. If not, see <http://www.gnu.org/licenses/>.
-- Greg Stitt
-- University of Florida
-- Description:
-- This file implements a fifo entity. The fifo has a configurable depth
-- and width, and can use bram, distributed ram, or LUTs/FFs to implement
-- the buffer. The fifo also has a configurable output delay of either 0 or 1
-- cycles.
--
-- This entity does not implement the behavior of the fifo and instead
-- instantiates fifo_core architectures depending on the configuration of
-- generics. The fifo and fifo_core could potentially be combined, but having
-- recursive instantiations causes problems with some simulators, which this
-- implementation tries to avoid.
-- Notes:
-- The fifo protects against invalid writes (i.e. when full) and invalid reads
-- (i.e. when empty)
--
-- (use_bram = true and same_cycle_output = true) is not supported by
-- all FPGAs.
--
-- When using BRAM, the FIFO depth is rounded up to the nearest power of two.
--
-- The actual choice of RAM depends on the specific synthesis tool and FPGA.
-- This entity does not guarantee the correct type.
-- Used entities:
-- fifo_core
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- Generics Description
-- width : the width of the FIFO in bits (required)
-- depth : the depth of the FIFO in words (required)
-- use_bram : uses bram when true, uses LUTs/FFs when false
-- (default = true)
-- use_distribted_ram : uses distributed ram when true. If use_bram is also
-- true, use_distributed_ram is ignore. If both are false,
-- use LUTS/FFs. (default = false)
-- same_cycle_output : when true, output appears in same cycle as read. when
-- false, output appears one cycle after read.
-- (default = false)
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Port Description: (all control inputs are active high)
-- clk : clock
-- rst : reset (asynchronous)
-- rd : read enable
-- wr : write enable
-- empty : asserted when the FIFO is empty
-- full : asserted when the FIFO is full
-- input : Input to write into the FIFO
-- output : Output read from the FIFO
-------------------------------------------------------------------------------
entity fifo is
generic(width : positive;
depth : positive;
use_bram : boolean := true;
use_distributed_ram : boolean := false;
same_cycle_output : boolean := false);
port(clk : in std_logic;
rst : in std_logic;
rd : in std_logic;
wr : in std_logic;
empty : out std_logic;
full : out std_logic;
input : in std_logic_vector(width-1 downto 0);
output : out std_logic_vector(width-1 downto 0));
end fifo;
architecture DEFAULT of fifo is
begin
-- if the user doesn't want any type of ram, use the flip-flop architecture
FF : if use_bram = false and use_distributed_ram = false generate
U_FIFO_FF : entity work.fifo_core(FF)
generic map (width => width,
depth => depth,
use_bram => false,
same_cycle_output => same_cycle_output)
port map (clk => clk,
rst => rst,
rd => rd,
wr => wr,
empty => empty,
full => full,
input => input,
output => output);
end generate FF;
-- for any type of memory, use the MEMORY architecture where the use_bram
-- option will specify the type of memory
MEMORY : if use_bram = true or use_distributed_ram = true generate
U_FIFO_RAM : entity work.fifo_core(MEMORY)
generic map (width => width,
depth => depth,
use_bram => use_bram,
same_cycle_output => same_cycle_output)
port map (clk => clk,
rst => rst,
rd => rd,
wr => wr,
empty => empty,
full => full,
input => input,
output => output);
end generate MEMORY;
end DEFAULT;
| gpl-3.0 | 8168a7dae11c31df417a2db55627cc3e | 0.538261 | 4.540678 | false | false | false | false |
pwsoft/fpga_examples | rtl/general/gen_bin2gray_tb.vhd | 1 | 2,184 | -- -----------------------------------------------------------------------
--
-- Syntiac's generic VHDL support files.
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2012 by Peter Wendrich ([email protected])
-- http://www.syntiac.com/fpga64.html
--
-- This source file is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- -----------------------------------------------------------------------
--
-- gen_bin2gray_tb.vhd
--
-- -----------------------------------------------------------------------
--
-- Testbench for binary to gray-code converter
--
-- -----------------------------------------------------------------------
library IEEE;
use STD.textio.ALL;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
-- -----------------------------------------------------------------------
entity gen_bin2gray_tb is
end entity;
-- -----------------------------------------------------------------------
architecture rtl of gen_bin2gray_tb is
signal d : unsigned(3 downto 0);
signal q : unsigned(3 downto 0);
begin
myBin2Gray : entity work.gen_bin2gray
port map (
d => d,
q => q
);
process
begin
d <= "0000";
wait for 1 ns;
assert(q = "0000");
d <= "0001";
wait for 1 ns;
assert(q = "0001");
d <= "0010";
wait for 1 ns;
assert(q = "0011");
d <= "0011";
wait for 1 ns;
assert(q = "0010");
d <= "0110";
wait for 1 ns;
assert(q = "0101");
d <= "1100";
wait for 1 ns;
-- write(output, integer'image(to_integer(q)));
assert(q = "1010");
wait;
end process;
end architecture;
| lgpl-2.1 | b821d278f9a2ea165f58445ab0e00e7a | 0.508242 | 3.913978 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/techmap/maps/system_monitor.vhd | 1 | 13,187 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: system_monitor
-- File: system_monitor.vhd
-- Author: Jan Andersson, Jiri Gaisler - Gaisler Research
-- Description: System monitor wrapper
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity system_monitor is
generic (
-- GRLIB generics
tech : integer := DEFFABTECH;
-- Virtex 5 SYSMON generics
INIT_40 : bit_vector := X"0000";
INIT_41 : bit_vector := X"0000";
INIT_42 : bit_vector := X"0800";
INIT_43 : bit_vector := X"0000";
INIT_44 : bit_vector := X"0000";
INIT_45 : bit_vector := X"0000";
INIT_46 : bit_vector := X"0000";
INIT_47 : bit_vector := X"0000";
INIT_48 : bit_vector := X"0000";
INIT_49 : bit_vector := X"0000";
INIT_4A : bit_vector := X"0000";
INIT_4B : bit_vector := X"0000";
INIT_4C : bit_vector := X"0000";
INIT_4D : bit_vector := X"0000";
INIT_4E : bit_vector := X"0000";
INIT_4F : bit_vector := X"0000";
INIT_50 : bit_vector := X"0000";
INIT_51 : bit_vector := X"0000";
INIT_52 : bit_vector := X"0000";
INIT_53 : bit_vector := X"0000";
INIT_54 : bit_vector := X"0000";
INIT_55 : bit_vector := X"0000";
INIT_56 : bit_vector := X"0000";
INIT_57 : bit_vector := X"0000";
SIM_MONITOR_FILE : string := "design.txt");
port (
alm : out std_logic_vector(2 downto 0);
busy : out std_ulogic;
channel : out std_logic_vector(4 downto 0);
do : out std_logic_vector(15 downto 0);
drdy : out std_ulogic;
eoc : out std_ulogic;
eos : out std_ulogic;
jtagbusy : out std_ulogic;
jtaglocked : out std_ulogic;
jtagmodified : out std_ulogic;
ot : out std_ulogic;
convst : in std_ulogic;
convstclk : in std_ulogic;
daddr : in std_logic_vector(6 downto 0);
dclk : in std_ulogic;
den : in std_ulogic;
di : in std_logic_vector(15 downto 0);
dwe : in std_ulogic;
reset : in std_ulogic;
vauxn : in std_logic_vector(15 downto 0);
vauxp : in std_logic_vector(15 downto 0);
vn : in std_ulogic;
vp : in std_ulogic);
end system_monitor;
architecture struct of system_monitor is
component sysmon_virtex5
generic (
INIT_40 : bit_vector := X"0000";
INIT_41 : bit_vector := X"0000";
INIT_42 : bit_vector := X"0800";
INIT_43 : bit_vector := X"0000";
INIT_44 : bit_vector := X"0000";
INIT_45 : bit_vector := X"0000";
INIT_46 : bit_vector := X"0000";
INIT_47 : bit_vector := X"0000";
INIT_48 : bit_vector := X"0000";
INIT_49 : bit_vector := X"0000";
INIT_4A : bit_vector := X"0000";
INIT_4B : bit_vector := X"0000";
INIT_4C : bit_vector := X"0000";
INIT_4D : bit_vector := X"0000";
INIT_4E : bit_vector := X"0000";
INIT_4F : bit_vector := X"0000";
INIT_50 : bit_vector := X"0000";
INIT_51 : bit_vector := X"0000";
INIT_52 : bit_vector := X"0000";
INIT_53 : bit_vector := X"0000";
INIT_54 : bit_vector := X"0000";
INIT_55 : bit_vector := X"0000";
INIT_56 : bit_vector := X"0000";
INIT_57 : bit_vector := X"0000";
SIM_MONITOR_FILE : string := "design.txt");
port (
alm : out std_logic_vector(2 downto 0);
busy : out std_ulogic;
channel : out std_logic_vector(4 downto 0);
do : out std_logic_vector(15 downto 0);
drdy : out std_ulogic;
eoc : out std_ulogic;
eos : out std_ulogic;
jtagbusy : out std_ulogic;
jtaglocked : out std_ulogic;
jtagmodified : out std_ulogic;
ot : out std_ulogic;
convst : in std_ulogic;
convstclk : in std_ulogic;
daddr : in std_logic_vector(6 downto 0);
dclk : in std_ulogic;
den : in std_ulogic;
di : in std_logic_vector(15 downto 0);
dwe : in std_ulogic;
reset : in std_ulogic;
vauxn : in std_logic_vector(15 downto 0);
vauxp : in std_logic_vector(15 downto 0);
vn : in std_ulogic;
vp : in std_ulogic);
end component;
component sysmon
generic (
INIT_40 : bit_vector := X"0000";
INIT_41 : bit_vector := X"0000";
INIT_42 : bit_vector := X"0800";
INIT_43 : bit_vector := X"0000";
INIT_44 : bit_vector := X"0000";
INIT_45 : bit_vector := X"0000";
INIT_46 : bit_vector := X"0000";
INIT_47 : bit_vector := X"0000";
INIT_48 : bit_vector := X"0000";
INIT_49 : bit_vector := X"0000";
INIT_4A : bit_vector := X"0000";
INIT_4B : bit_vector := X"0000";
INIT_4C : bit_vector := X"0000";
INIT_4D : bit_vector := X"0000";
INIT_4E : bit_vector := X"0000";
INIT_4F : bit_vector := X"0000";
INIT_50 : bit_vector := X"0000";
INIT_51 : bit_vector := X"0000";
INIT_52 : bit_vector := X"0000";
INIT_53 : bit_vector := X"0000";
INIT_54 : bit_vector := X"0000";
INIT_55 : bit_vector := X"0000";
INIT_56 : bit_vector := X"0000";
INIT_57 : bit_vector := X"0000";
SIM_DEVICE : string := "VIRTEX5";
SIM_MONITOR_FILE : string := "design.txt");
port (
alm : out std_logic_vector(2 downto 0);
busy : out std_ulogic;
channel : out std_logic_vector(4 downto 0);
do : out std_logic_vector(15 downto 0);
drdy : out std_ulogic;
eoc : out std_ulogic;
eos : out std_ulogic;
jtagbusy : out std_ulogic;
jtaglocked : out std_ulogic;
jtagmodified : out std_ulogic;
ot : out std_ulogic;
convst : in std_ulogic;
convstclk : in std_ulogic;
daddr : in std_logic_vector(6 downto 0);
dclk : in std_ulogic;
den : in std_ulogic;
di : in std_logic_vector(15 downto 0);
dwe : in std_ulogic;
reset : in std_ulogic;
vauxn : in std_logic_vector(15 downto 0);
vauxp : in std_logic_vector(15 downto 0);
vn : in std_ulogic;
vp : in std_ulogic);
end component;
begin -- struct
gen: if not ((tech = virtex5) or (tech = virtex6) or (tech = virtex7) or (tech = kintex7)) generate
alm <= (others => '0');
busy <= '0';
channel <= (others => '0');
do <= (others => '0');
drdy <= '0';
eoc <= '0';
eos <= '0';
jtagbusy <= '0';
jtaglocked <= '0';
jtagmodified <= '0';
ot <= '0';
end generate gen;
v5: if tech = virtex5 generate
v50 : sysmon_virtex5
generic map (
INIT_40 => INIT_40,
INIT_41 => INIT_41,
INIT_42 => INIT_42,
INIT_43 => INIT_43,
INIT_44 => INIT_44,
INIT_45 => INIT_45,
INIT_46 => INIT_46,
INIT_47 => INIT_47,
INIT_48 => INIT_48,
INIT_49 => INIT_49,
INIT_4A => INIT_4A,
INIT_4B => INIT_4B,
INIT_4C => INIT_4C,
INIT_4D => INIT_4D,
INIT_4E => INIT_4E,
INIT_4F => INIT_4F,
INIT_50 => INIT_50,
INIT_51 => INIT_51,
INIT_52 => INIT_52,
INIT_53 => INIT_53,
INIT_54 => INIT_54,
INIT_55 => INIT_55,
INIT_56 => INIT_56,
INIT_57 => INIT_57,
SIM_MONITOR_FILE => SIM_MONITOR_FILE)
port map (alm => alm, busy => busy, channel => channel, do => do,
drdy => drdy, eoc => eoc, eos => eos, jtagbusy => jtagbusy,
jtaglocked => jtaglocked, jtagmodified => jtagmodified,
ot => ot, convst => convst, convstclk => convstclk,
daddr => daddr, dclk => dclk, den => den, di => di,
dwe => dwe, reset => reset, vauxn => vauxn, vauxp => vauxp,
vn => vn, vp => vp);
end generate v5;
v6: if tech = virtex6 generate
v60 : sysmon
generic map (
INIT_40 => INIT_40,
INIT_41 => INIT_41,
INIT_42 => INIT_42,
INIT_43 => INIT_43,
INIT_44 => INIT_44,
INIT_45 => INIT_45,
INIT_46 => INIT_46,
INIT_47 => INIT_47,
INIT_48 => INIT_48,
INIT_49 => INIT_49,
INIT_4A => INIT_4A,
INIT_4B => INIT_4B,
INIT_4C => INIT_4C,
INIT_4D => INIT_4D,
INIT_4E => INIT_4E,
INIT_4F => INIT_4F,
INIT_50 => INIT_50,
INIT_51 => INIT_51,
INIT_52 => INIT_52,
INIT_53 => INIT_53,
INIT_54 => INIT_54,
INIT_55 => INIT_55,
INIT_56 => INIT_56,
INIT_57 => INIT_57,
SIM_DEVICE => "VIRTEX6",
SIM_MONITOR_FILE => SIM_MONITOR_FILE)
port map (alm => alm, busy => busy, channel => channel, do => do,
drdy => drdy, eoc => eoc, eos => eos, jtagbusy => jtagbusy,
jtaglocked => jtaglocked, jtagmodified => jtagmodified,
ot => ot, convst => convst, convstclk => convstclk,
daddr => daddr, dclk => dclk, den => den, di => di,
dwe => dwe, reset => reset, vauxn => vauxn, vauxp => vauxp,
vn => vn, vp => vp);
end generate v6;
v7: if tech = virtex7 generate
v70 : sysmon
generic map (
INIT_40 => INIT_40,
INIT_41 => INIT_41,
INIT_42 => INIT_42,
INIT_43 => INIT_43,
INIT_44 => INIT_44,
INIT_45 => INIT_45,
INIT_46 => INIT_46,
INIT_47 => INIT_47,
INIT_48 => INIT_48,
INIT_49 => INIT_49,
INIT_4A => INIT_4A,
INIT_4B => INIT_4B,
INIT_4C => INIT_4C,
INIT_4D => INIT_4D,
INIT_4E => INIT_4E,
INIT_4F => INIT_4F,
INIT_50 => INIT_50,
INIT_51 => INIT_51,
INIT_52 => INIT_52,
INIT_53 => INIT_53,
INIT_54 => INIT_54,
INIT_55 => INIT_55,
INIT_56 => INIT_56,
INIT_57 => INIT_57,
SIM_DEVICE => "VIRTEX7",
SIM_MONITOR_FILE => SIM_MONITOR_FILE)
port map (alm => alm, busy => busy, channel => channel, do => do,
drdy => drdy, eoc => eoc, eos => eos, jtagbusy => jtagbusy,
jtaglocked => jtaglocked, jtagmodified => jtagmodified,
ot => ot, convst => convst, convstclk => convstclk,
daddr => daddr, dclk => dclk, den => den, di => di,
dwe => dwe, reset => reset, vauxn => vauxn, vauxp => vauxp,
vn => vn, vp => vp);
end generate v7;
k7: if tech = kintex7 generate
k70 : sysmon
generic map (
INIT_40 => INIT_40,
INIT_41 => INIT_41,
INIT_42 => INIT_42,
INIT_43 => INIT_43,
INIT_44 => INIT_44,
INIT_45 => INIT_45,
INIT_46 => INIT_46,
INIT_47 => INIT_47,
INIT_48 => INIT_48,
INIT_49 => INIT_49,
INIT_4A => INIT_4A,
INIT_4B => INIT_4B,
INIT_4C => INIT_4C,
INIT_4D => INIT_4D,
INIT_4E => INIT_4E,
INIT_4F => INIT_4F,
INIT_50 => INIT_50,
INIT_51 => INIT_51,
INIT_52 => INIT_52,
INIT_53 => INIT_53,
INIT_54 => INIT_54,
INIT_55 => INIT_55,
INIT_56 => INIT_56,
INIT_57 => INIT_57,
SIM_DEVICE => "KINTEX7",
SIM_MONITOR_FILE => SIM_MONITOR_FILE)
port map (alm => alm, busy => busy, channel => channel, do => do,
drdy => drdy, eoc => eoc, eos => eos, jtagbusy => jtagbusy,
jtaglocked => jtaglocked, jtagmodified => jtagmodified,
ot => ot, convst => convst, convstclk => convstclk,
daddr => daddr, dclk => dclk, den => den, di => di,
dwe => dwe, reset => reset, vauxn => vauxn, vauxp => vauxp,
vn => vn, vp => vp);
end generate k7;
end struct;
| gpl-3.0 | 4e500979d28ebe4f80759a65c2101d43 | 0.504588 | 3.499735 | false | false | false | false |
makestuff/mem-ctrl | vhdl/tb_unit/sdram_model_accurate.vhdl | 1 | 1,503 | --
-- Copyright (C) 2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library verilog;
use verilog.vl_types.all;
architecture behavioural of sdram_model is
begin
-- Instantiate the SDRAM model for testing
--sdram: entity work.sdram
-- port map(
-- clk => ramClk_in,
-- csb => '0',
-- cke => '1',
-- rasb => ramCmd_in(2),
-- casb => ramCmd_in(1),
-- web => ramCmd_in(0),
-- ba => ramBank_in,
-- ad => ramAddr_in,
-- dqm => "00",
-- dqi => ramData_io
-- );
sdram: entity work.mt48lc8m16a2
port map(
Clk => ramClk_in,
Cs_n => Su0,
Cke => Su1,
Ras_n => ramCmd_in(2),
Cas_n => ramCmd_in(1),
We_n => ramCmd_in(0),
Ba => ramBank_in,
Addr => ramAddr_in,
Dqm => (others => Su0),
Dq => ramData_io
);
end architecture;
| gpl-3.0 | b7f0b01dae532c6935cb4a258f56c2bd | 0.649368 | 3.012024 | false | false | false | false |
hoglet67/CoPro6502 | src/DCM/dcm_32_56.vhd | 1 | 2,183 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity dcm_32_56 is
port (CLKIN_IN : in std_logic;
CLK0_OUT : out std_logic;
CLK0_OUT1 : out std_logic;
CLK2X_OUT : out std_logic);
end dcm_32_56;
architecture BEHAVIORAL of dcm_32_56 is
signal CLKFX_BUF : std_logic;
signal CLK2X_BUF : std_logic;
signal CLKIN_IBUFG : std_logic;
signal GND_BIT : std_logic;
begin
GND_BIT <= '0';
CLKFX_BUFG_INST : BUFG
port map (I => CLKFX_BUF, O => CLK0_OUT);
CLK2X_BUFG_INST : BUFG
port map (I => CLK2X_BUF, O => CLK2X_OUT);
DCM_INST : DCM
generic map(CLK_FEEDBACK => "NONE",
CLKDV_DIVIDE => 4.0, -- 56.00 = 32.000 * 7/4
CLKFX_MULTIPLY => 7,
CLKFX_DIVIDE => 4,
CLKIN_DIVIDE_BY_2 => false,
CLKIN_PERIOD => 31.25,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => true,
FACTORY_JF => x"C080",
PHASE_SHIFT => 0,
STARTUP_WAIT => false)
port map (CLKFB => GND_BIT,
CLKIN => CLKIN_IN,
DSSEN => GND_BIT,
PSCLK => GND_BIT,
PSEN => GND_BIT,
PSINCDEC => GND_BIT,
RST => GND_BIT,
CLKDV => open,
CLKFX => CLKFX_BUF,
CLKFX180 => open,
CLK0 => open,
CLK2X => CLK2X_BUF,
CLK2X180 => open,
CLK90 => open,
CLK180 => open,
CLK270 => open,
LOCKED => open,
PSDONE => open,
STATUS => open);
end BEHAVIORAL;
| gpl-3.0 | 53609234d797a03472f43f5487c54671 | 0.412735 | 4.080374 | false | false | false | false |
hoglet67/CoPro6502 | client/6809/100c/tuberom_6809.vhd | 1 | 86,726 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tuberom_6809 is
port (
CLK : in std_logic;
ADDR : in std_logic_vector(10 downto 0);
DATA : out std_logic_vector(7 downto 0)
);
end;
architecture RTL of tuberom_6809 is
signal rom_addr : std_logic_vector(11 downto 0);
begin
p_addr : process(ADDR)
begin
rom_addr <= (others => '0');
rom_addr(10 downto 0) <= ADDR;
end process;
p_rom : process
begin
wait until rising_edge(CLK);
DATA <= (others => '0');
case rom_addr is
when x"000" => DATA <= x"F8";
when x"001" => DATA <= x"2C";
when x"002" => DATA <= x"F8";
when x"003" => DATA <= x"71";
when x"004" => DATA <= x"FF";
when x"005" => DATA <= x"E0";
when x"006" => DATA <= x"F8";
when x"007" => DATA <= x"E0";
when x"008" => DATA <= x"F8";
when x"009" => DATA <= x"F4";
when x"00A" => DATA <= x"FF";
when x"00B" => DATA <= x"EE";
when x"00C" => DATA <= x"F8";
when x"00D" => DATA <= x"E9";
when x"00E" => DATA <= x"FF";
when x"00F" => DATA <= x"E7";
when x"010" => DATA <= x"F8";
when x"011" => DATA <= x"E6";
when x"012" => DATA <= x"F8";
when x"013" => DATA <= x"DF";
when x"014" => DATA <= x"20";
when x"015" => DATA <= x"5B";
when x"016" => DATA <= x"0D";
when x"017" => DATA <= x"36";
when x"018" => DATA <= x"38";
when x"019" => DATA <= x"30";
when x"01A" => DATA <= x"39";
when x"01B" => DATA <= x"20";
when x"01C" => DATA <= x"54";
when x"01D" => DATA <= x"55";
when x"01E" => DATA <= x"42";
when x"01F" => DATA <= x"45";
when x"020" => DATA <= x"20";
when x"021" => DATA <= x"36";
when x"022" => DATA <= x"34";
when x"023" => DATA <= x"4B";
when x"024" => DATA <= x"20";
when x"025" => DATA <= x"31";
when x"026" => DATA <= x"2E";
when x"027" => DATA <= x"30";
when x"028" => DATA <= x"30";
when x"029" => DATA <= x"20";
when x"02A" => DATA <= x"0D";
when x"02B" => DATA <= x"00";
when x"02C" => DATA <= x"1A";
when x"02D" => DATA <= x"50";
when x"02E" => DATA <= x"10";
when x"02F" => DATA <= x"CE";
when x"030" => DATA <= x"F8";
when x"031" => DATA <= x"00";
when x"032" => DATA <= x"1F";
when x"033" => DATA <= x"41";
when x"034" => DATA <= x"EC";
when x"035" => DATA <= x"84";
when x"036" => DATA <= x"ED";
when x"037" => DATA <= x"81";
when x"038" => DATA <= x"8C";
when x"039" => DATA <= x"FE";
when x"03A" => DATA <= x"C0";
when x"03B" => DATA <= x"26";
when x"03C" => DATA <= x"03";
when x"03D" => DATA <= x"8E";
when x"03E" => DATA <= x"FE";
when x"03F" => DATA <= x"F0";
when x"040" => DATA <= x"8C";
when x"041" => DATA <= x"FF";
when x"042" => DATA <= x"8C";
when x"043" => DATA <= x"26";
when x"044" => DATA <= x"03";
when x"045" => DATA <= x"8E";
when x"046" => DATA <= x"FF";
when x"047" => DATA <= x"94";
when x"048" => DATA <= x"8C";
when x"049" => DATA <= x"00";
when x"04A" => DATA <= x"00";
when x"04B" => DATA <= x"26";
when x"04C" => DATA <= x"E7";
when x"04D" => DATA <= x"B6";
when x"04E" => DATA <= x"FE";
when x"04F" => DATA <= x"E0";
when x"050" => DATA <= x"1A";
when x"051" => DATA <= x"50";
when x"052" => DATA <= x"10";
when x"053" => DATA <= x"CE";
when x"054" => DATA <= x"FF";
when x"055" => DATA <= x"28";
when x"056" => DATA <= x"8D";
when x"057" => DATA <= x"68";
when x"058" => DATA <= x"BE";
when x"059" => DATA <= x"FF";
when x"05A" => DATA <= x"90";
when x"05B" => DATA <= x"BF";
when x"05C" => DATA <= x"FF";
when x"05D" => DATA <= x"8E";
when x"05E" => DATA <= x"1C";
when x"05F" => DATA <= x"00";
when x"060" => DATA <= x"8E";
when x"061" => DATA <= x"F8";
when x"062" => DATA <= x"16";
when x"063" => DATA <= x"BD";
when x"064" => DATA <= x"F9";
when x"065" => DATA <= x"33";
when x"066" => DATA <= x"BD";
when x"067" => DATA <= x"FF";
when x"068" => DATA <= x"E7";
when x"069" => DATA <= x"4F";
when x"06A" => DATA <= x"BD";
when x"06B" => DATA <= x"FF";
when x"06C" => DATA <= x"EE";
when x"06D" => DATA <= x"4F";
when x"06E" => DATA <= x"BD";
when x"06F" => DATA <= x"FA";
when x"070" => DATA <= x"30";
when x"071" => DATA <= x"10";
when x"072" => DATA <= x"CE";
when x"073" => DATA <= x"FF";
when x"074" => DATA <= x"28";
when x"075" => DATA <= x"8D";
when x"076" => DATA <= x"49";
when x"077" => DATA <= x"10";
when x"078" => DATA <= x"FE";
when x"079" => DATA <= x"FF";
when x"07A" => DATA <= x"8A";
when x"07B" => DATA <= x"8E";
when x"07C" => DATA <= x"FF";
when x"07D" => DATA <= x"B9";
when x"07E" => DATA <= x"BF";
when x"07F" => DATA <= x"FF";
when x"080" => DATA <= x"90";
when x"081" => DATA <= x"1C";
when x"082" => DATA <= x"00";
when x"083" => DATA <= x"8E";
when x"084" => DATA <= x"F8";
when x"085" => DATA <= x"96";
when x"086" => DATA <= x"BD";
when x"087" => DATA <= x"F9";
when x"088" => DATA <= x"33";
when x"089" => DATA <= x"BD";
when x"08A" => DATA <= x"FF";
when x"08B" => DATA <= x"F1";
when x"08C" => DATA <= x"25";
when x"08D" => DATA <= x"14";
when x"08E" => DATA <= x"8E";
when x"08F" => DATA <= x"FF";
when x"090" => DATA <= x"28";
when x"091" => DATA <= x"BD";
when x"092" => DATA <= x"FF";
when x"093" => DATA <= x"F7";
when x"094" => DATA <= x"20";
when x"095" => DATA <= x"ED";
when x"096" => DATA <= x"36";
when x"097" => DATA <= x"38";
when x"098" => DATA <= x"30";
when x"099" => DATA <= x"39";
when x"09A" => DATA <= x"3E";
when x"09B" => DATA <= x"2A";
when x"09C" => DATA <= x"00";
when x"09D" => DATA <= x"FF";
when x"09E" => DATA <= x"28";
when x"09F" => DATA <= x"57";
when x"0A0" => DATA <= x"20";
when x"0A1" => DATA <= x"FF";
when x"0A2" => DATA <= x"86";
when x"0A3" => DATA <= x"7E";
when x"0A4" => DATA <= x"BD";
when x"0A5" => DATA <= x"FF";
when x"0A6" => DATA <= x"F4";
when x"0A7" => DATA <= x"3F";
when x"0A8" => DATA <= x"11";
when x"0A9" => DATA <= x"45";
when x"0AA" => DATA <= x"73";
when x"0AB" => DATA <= x"63";
when x"0AC" => DATA <= x"61";
when x"0AD" => DATA <= x"70";
when x"0AE" => DATA <= x"65";
when x"0AF" => DATA <= x"00";
when x"0B0" => DATA <= x"10";
when x"0B1" => DATA <= x"FE";
when x"0B2" => DATA <= x"FF";
when x"0B3" => DATA <= x"8A";
when x"0B4" => DATA <= x"BD";
when x"0B5" => DATA <= x"FF";
when x"0B6" => DATA <= x"E7";
when x"0B7" => DATA <= x"A6";
when x"0B8" => DATA <= x"80";
when x"0B9" => DATA <= x"8D";
when x"0BA" => DATA <= x"78";
when x"0BB" => DATA <= x"BD";
when x"0BC" => DATA <= x"FF";
when x"0BD" => DATA <= x"E7";
when x"0BE" => DATA <= x"20";
when x"0BF" => DATA <= x"C3";
when x"0C0" => DATA <= x"CC";
when x"0C1" => DATA <= x"00";
when x"0C2" => DATA <= x"00";
when x"0C3" => DATA <= x"FD";
when x"0C4" => DATA <= x"FF";
when x"0C5" => DATA <= x"88";
when x"0C6" => DATA <= x"CC";
when x"0C7" => DATA <= x"F8";
when x"0C8" => DATA <= x"00";
when x"0C9" => DATA <= x"FD";
when x"0CA" => DATA <= x"FF";
when x"0CB" => DATA <= x"8A";
when x"0CC" => DATA <= x"CC";
when x"0CD" => DATA <= x"F8";
when x"0CE" => DATA <= x"B0";
when x"0CF" => DATA <= x"FD";
when x"0D0" => DATA <= x"FF";
when x"0D1" => DATA <= x"FA";
when x"0D2" => DATA <= x"CC";
when x"0D3" => DATA <= x"FE";
when x"0D4" => DATA <= x"22";
when x"0D5" => DATA <= x"FD";
when x"0D6" => DATA <= x"FE";
when x"0D7" => DATA <= x"FA";
when x"0D8" => DATA <= x"8E";
when x"0D9" => DATA <= x"FF";
when x"0DA" => DATA <= x"FA";
when x"0DB" => DATA <= x"10";
when x"0DC" => DATA <= x"8E";
when x"0DD" => DATA <= x"FF";
when x"0DE" => DATA <= x"80";
when x"0DF" => DATA <= x"39";
when x"0E0" => DATA <= x"BD";
when x"0E1" => DATA <= x"FF";
when x"0E2" => DATA <= x"E0";
when x"0E3" => DATA <= x"7E";
when x"0E4" => DATA <= x"FF";
when x"0E5" => DATA <= x"EE";
when x"0E6" => DATA <= x"BD";
when x"0E7" => DATA <= x"FF";
when x"0E8" => DATA <= x"E7";
when x"0E9" => DATA <= x"A6";
when x"0EA" => DATA <= x"80";
when x"0EB" => DATA <= x"81";
when x"0EC" => DATA <= x"04";
when x"0ED" => DATA <= x"27";
when x"0EE" => DATA <= x"F0";
when x"0EF" => DATA <= x"BD";
when x"0F0" => DATA <= x"FF";
when x"0F1" => DATA <= x"EE";
when x"0F2" => DATA <= x"20";
when x"0F3" => DATA <= x"F5";
when x"0F4" => DATA <= x"34";
when x"0F5" => DATA <= x"32";
when x"0F6" => DATA <= x"86";
when x"0F7" => DATA <= x"80";
when x"0F8" => DATA <= x"8E";
when x"0F9" => DATA <= x"FF";
when x"0FA" => DATA <= x"FF";
when x"0FB" => DATA <= x"1F";
when x"0FC" => DATA <= x"12";
when x"0FD" => DATA <= x"BD";
when x"0FE" => DATA <= x"FF";
when x"0FF" => DATA <= x"F4";
when x"100" => DATA <= x"8C";
when x"101" => DATA <= x"00";
when x"102" => DATA <= x"00";
when x"103" => DATA <= x"35";
when x"104" => DATA <= x"B2";
when x"105" => DATA <= x"34";
when x"106" => DATA <= x"06";
when x"107" => DATA <= x"1F";
when x"108" => DATA <= x"10";
when x"109" => DATA <= x"8D";
when x"10A" => DATA <= x"06";
when x"10B" => DATA <= x"1F";
when x"10C" => DATA <= x"98";
when x"10D" => DATA <= x"8D";
when x"10E" => DATA <= x"02";
when x"10F" => DATA <= x"35";
when x"110" => DATA <= x"86";
when x"111" => DATA <= x"34";
when x"112" => DATA <= x"02";
when x"113" => DATA <= x"44";
when x"114" => DATA <= x"44";
when x"115" => DATA <= x"44";
when x"116" => DATA <= x"44";
when x"117" => DATA <= x"8D";
when x"118" => DATA <= x"06";
when x"119" => DATA <= x"A6";
when x"11A" => DATA <= x"E4";
when x"11B" => DATA <= x"8D";
when x"11C" => DATA <= x"02";
when x"11D" => DATA <= x"35";
when x"11E" => DATA <= x"82";
when x"11F" => DATA <= x"84";
when x"120" => DATA <= x"0F";
when x"121" => DATA <= x"81";
when x"122" => DATA <= x"0A";
when x"123" => DATA <= x"25";
when x"124" => DATA <= x"02";
when x"125" => DATA <= x"8B";
when x"126" => DATA <= x"07";
when x"127" => DATA <= x"8B";
when x"128" => DATA <= x"30";
when x"129" => DATA <= x"7E";
when x"12A" => DATA <= x"FF";
when x"12B" => DATA <= x"EE";
when x"12C" => DATA <= x"35";
when x"12D" => DATA <= x"10";
when x"12E" => DATA <= x"8D";
when x"12F" => DATA <= x"03";
when x"130" => DATA <= x"34";
when x"131" => DATA <= x"10";
when x"132" => DATA <= x"39";
when x"133" => DATA <= x"A6";
when x"134" => DATA <= x"80";
when x"135" => DATA <= x"27";
when x"136" => DATA <= x"FB";
when x"137" => DATA <= x"BD";
when x"138" => DATA <= x"FF";
when x"139" => DATA <= x"E3";
when x"13A" => DATA <= x"20";
when x"13B" => DATA <= x"F7";
when x"13C" => DATA <= x"10";
when x"13D" => DATA <= x"8E";
when x"13E" => DATA <= x"00";
when x"13F" => DATA <= x"00";
when x"140" => DATA <= x"A6";
when x"141" => DATA <= x"80";
when x"142" => DATA <= x"81";
when x"143" => DATA <= x"30";
when x"144" => DATA <= x"25";
when x"145" => DATA <= x"2B";
when x"146" => DATA <= x"81";
when x"147" => DATA <= x"3A";
when x"148" => DATA <= x"25";
when x"149" => DATA <= x"0A";
when x"14A" => DATA <= x"84";
when x"14B" => DATA <= x"DF";
when x"14C" => DATA <= x"80";
when x"14D" => DATA <= x"07";
when x"14E" => DATA <= x"25";
when x"14F" => DATA <= x"21";
when x"150" => DATA <= x"81";
when x"151" => DATA <= x"40";
when x"152" => DATA <= x"24";
when x"153" => DATA <= x"1D";
when x"154" => DATA <= x"84";
when x"155" => DATA <= x"0F";
when x"156" => DATA <= x"1E";
when x"157" => DATA <= x"02";
when x"158" => DATA <= x"58";
when x"159" => DATA <= x"49";
when x"15A" => DATA <= x"58";
when x"15B" => DATA <= x"49";
when x"15C" => DATA <= x"58";
when x"15D" => DATA <= x"49";
when x"15E" => DATA <= x"58";
when x"15F" => DATA <= x"49";
when x"160" => DATA <= x"1E";
when x"161" => DATA <= x"12";
when x"162" => DATA <= x"1E";
when x"163" => DATA <= x"01";
when x"164" => DATA <= x"1E";
when x"165" => DATA <= x"89";
when x"166" => DATA <= x"3A";
when x"167" => DATA <= x"1E";
when x"168" => DATA <= x"12";
when x"169" => DATA <= x"20";
when x"16A" => DATA <= x"D5";
when x"16B" => DATA <= x"A6";
when x"16C" => DATA <= x"80";
when x"16D" => DATA <= x"81";
when x"16E" => DATA <= x"20";
when x"16F" => DATA <= x"27";
when x"170" => DATA <= x"FA";
when x"171" => DATA <= x"30";
when x"172" => DATA <= x"1F";
when x"173" => DATA <= x"81";
when x"174" => DATA <= x"21";
when x"175" => DATA <= x"39";
when x"176" => DATA <= x"34";
when x"177" => DATA <= x"7C";
when x"178" => DATA <= x"11";
when x"179" => DATA <= x"8C";
when x"17A" => DATA <= x"F8";
when x"17B" => DATA <= x"00";
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when x"182" => DATA <= x"10";
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when x"186" => DATA <= x"8D";
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when x"189" => DATA <= x"CE";
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when x"18D" => DATA <= x"FC";
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when x"18F" => DATA <= x"45";
when x"190" => DATA <= x"4C";
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when x"192" => DATA <= x"80";
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when x"194" => DATA <= x"4F";
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when x"19A" => DATA <= x"80";
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when x"1A0" => DATA <= x"1F";
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when x"1A2" => DATA <= x"10";
when x"1A3" => DATA <= x"A6";
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when x"1A5" => DATA <= x"81";
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when x"1AA" => DATA <= x"1F";
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when x"1B3" => DATA <= x"8E";
when x"1B4" => DATA <= x"AE";
when x"1B5" => DATA <= x"E4";
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when x"1B7" => DATA <= x"84";
when x"1B8" => DATA <= x"81";
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when x"1BA" => DATA <= x"25";
when x"1BB" => DATA <= x"68";
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when x"1BF" => DATA <= x"DF";
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when x"1C3" => DATA <= x"F8";
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when x"1C5" => DATA <= x"A2";
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when x"1C8" => DATA <= x"A6";
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when x"1CB" => DATA <= x"2E";
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when x"1CF" => DATA <= x"A0";
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when x"1D2" => DATA <= x"A6";
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when x"1D4" => DATA <= x"26";
when x"1D5" => DATA <= x"DE";
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when x"1D7" => DATA <= x"4C";
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when x"1E3" => DATA <= x"40";
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when x"1E5" => DATA <= x"80";
when x"1E6" => DATA <= x"27";
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when x"1EA" => DATA <= x"10";
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when x"1ED" => DATA <= x"90";
when x"1EE" => DATA <= x"81";
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when x"1F1" => DATA <= x"18";
when x"1F2" => DATA <= x"81";
when x"1F3" => DATA <= x"3B";
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when x"1F5" => DATA <= x"12";
when x"1F6" => DATA <= x"BD";
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when x"220" => DATA <= x"16";
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when x"234" => DATA <= x"51";
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when x"240" => DATA <= x"FA";
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when x"35E" => DATA <= x"1E";
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when x"360" => DATA <= x"4F";
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when x"364" => DATA <= x"2B";
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when x"36A" => DATA <= x"10";
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when x"37B" => DATA <= x"3A";
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when x"37E" => DATA <= x"35";
when x"37F" => DATA <= x"10";
when x"380" => DATA <= x"BD";
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when x"382" => DATA <= x"DE";
when x"383" => DATA <= x"1F";
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when x"386" => DATA <= x"89";
when x"387" => DATA <= x"4F";
when x"388" => DATA <= x"1E";
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when x"38A" => DATA <= x"4A";
when x"38B" => DATA <= x"2B";
when x"38C" => DATA <= x"03";
when x"38D" => DATA <= x"BD";
when x"38E" => DATA <= x"FC";
when x"38F" => DATA <= x"BB";
when x"390" => DATA <= x"35";
when x"391" => DATA <= x"A6";
when x"392" => DATA <= x"86";
when x"393" => DATA <= x"0A";
when x"394" => DATA <= x"BD";
when x"395" => DATA <= x"FC";
when x"396" => DATA <= x"DE";
when x"397" => DATA <= x"30";
when x"398" => DATA <= x"02";
when x"399" => DATA <= x"10";
when x"39A" => DATA <= x"8E";
when x"39B" => DATA <= x"00";
when x"39C" => DATA <= x"03";
when x"39D" => DATA <= x"BD";
when x"39E" => DATA <= x"FC";
when x"39F" => DATA <= x"AB";
when x"3A0" => DATA <= x"30";
when x"3A1" => DATA <= x"1E";
when x"3A2" => DATA <= x"86";
when x"3A3" => DATA <= x"07";
when x"3A4" => DATA <= x"BD";
when x"3A5" => DATA <= x"FC";
when x"3A6" => DATA <= x"DE";
when x"3A7" => DATA <= x"4F";
when x"3A8" => DATA <= x"BD";
when x"3A9" => DATA <= x"FC";
when x"3AA" => DATA <= x"DE";
when x"3AB" => DATA <= x"BD";
when x"3AC" => DATA <= x"FA";
when x"3AD" => DATA <= x"B4";
when x"3AE" => DATA <= x"8B";
when x"3AF" => DATA <= x"80";
when x"3B0" => DATA <= x"25";
when x"3B1" => DATA <= x"0F";
when x"3B2" => DATA <= x"AE";
when x"3B3" => DATA <= x"84";
when x"3B4" => DATA <= x"BD";
when x"3B5" => DATA <= x"FA";
when x"3B6" => DATA <= x"B4";
when x"3B7" => DATA <= x"A7";
when x"3B8" => DATA <= x"80";
when x"3B9" => DATA <= x"31";
when x"3BA" => DATA <= x"21";
when x"3BB" => DATA <= x"81";
when x"3BC" => DATA <= x"0D";
when x"3BD" => DATA <= x"26";
when x"3BE" => DATA <= x"F5";
when x"3BF" => DATA <= x"31";
when x"3C0" => DATA <= x"3F";
when x"3C1" => DATA <= x"39";
when x"3C2" => DATA <= x"00";
when x"3C3" => DATA <= x"05";
when x"3C4" => DATA <= x"00";
when x"3C5" => DATA <= x"05";
when x"3C6" => DATA <= x"04";
when x"3C7" => DATA <= x"05";
when x"3C8" => DATA <= x"08";
when x"3C9" => DATA <= x"0E";
when x"3CA" => DATA <= x"04";
when x"3CB" => DATA <= x"01";
when x"3CC" => DATA <= x"01";
when x"3CD" => DATA <= x"05";
when x"3CE" => DATA <= x"00";
when x"3CF" => DATA <= x"10";
when x"3D0" => DATA <= x"20";
when x"3D1" => DATA <= x"10";
when x"3D2" => DATA <= x"0D";
when x"3D3" => DATA <= x"00";
when x"3D4" => DATA <= x"04";
when x"3D5" => DATA <= x"80";
when x"3D6" => DATA <= x"05";
when x"3D7" => DATA <= x"00";
when x"3D8" => DATA <= x"05";
when x"3D9" => DATA <= x"00";
when x"3DA" => DATA <= x"05";
when x"3DB" => DATA <= x"00";
when x"3DC" => DATA <= x"00";
when x"3DD" => DATA <= x"00";
when x"3DE" => DATA <= x"05";
when x"3DF" => DATA <= x"09";
when x"3E0" => DATA <= x"05";
when x"3E1" => DATA <= x"00";
when x"3E2" => DATA <= x"08";
when x"3E3" => DATA <= x"19";
when x"3E4" => DATA <= x"00";
when x"3E5" => DATA <= x"01";
when x"3E6" => DATA <= x"0D";
when x"3E7" => DATA <= x"80";
when x"3E8" => DATA <= x"04";
when x"3E9" => DATA <= x"80";
when x"3EA" => DATA <= x"34";
when x"3EB" => DATA <= x"26";
when x"3EC" => DATA <= x"86";
when x"3ED" => DATA <= x"0C";
when x"3EE" => DATA <= x"BD";
when x"3EF" => DATA <= x"FC";
when x"3F0" => DATA <= x"DE";
when x"3F1" => DATA <= x"BD";
when x"3F2" => DATA <= x"FC";
when x"3F3" => DATA <= x"DA";
when x"3F4" => DATA <= x"10";
when x"3F5" => DATA <= x"8E";
when x"3F6" => DATA <= x"00";
when x"3F7" => DATA <= x"04";
when x"3F8" => DATA <= x"BD";
when x"3F9" => DATA <= x"FC";
when x"3FA" => DATA <= x"AB";
when x"3FB" => DATA <= x"35";
when x"3FC" => DATA <= x"06";
when x"3FD" => DATA <= x"BD";
when x"3FE" => DATA <= x"FC";
when x"3FF" => DATA <= x"DE";
when x"400" => DATA <= x"BD";
when x"401" => DATA <= x"FA";
when x"402" => DATA <= x"B4";
when x"403" => DATA <= x"34";
when x"404" => DATA <= x"02";
when x"405" => DATA <= x"10";
when x"406" => DATA <= x"8E";
when x"407" => DATA <= x"00";
when x"408" => DATA <= x"04";
when x"409" => DATA <= x"BD";
when x"40A" => DATA <= x"FC";
when x"40B" => DATA <= x"BB";
when x"40C" => DATA <= x"35";
when x"40D" => DATA <= x"A2";
when x"40E" => DATA <= x"34";
when x"40F" => DATA <= x"04";
when x"410" => DATA <= x"86";
when x"411" => DATA <= x"0E";
when x"412" => DATA <= x"BD";
when x"413" => DATA <= x"FC";
when x"414" => DATA <= x"DE";
when x"415" => DATA <= x"BD";
when x"416" => DATA <= x"FC";
when x"417" => DATA <= x"DA";
when x"418" => DATA <= x"35";
when x"419" => DATA <= x"04";
when x"41A" => DATA <= x"7E";
when x"41B" => DATA <= x"FA";
when x"41C" => DATA <= x"B0";
when x"41D" => DATA <= x"34";
when x"41E" => DATA <= x"06";
when x"41F" => DATA <= x"86";
when x"420" => DATA <= x"10";
when x"421" => DATA <= x"BD";
when x"422" => DATA <= x"FC";
when x"423" => DATA <= x"DE";
when x"424" => DATA <= x"BD";
when x"425" => DATA <= x"FC";
when x"426" => DATA <= x"DA";
when x"427" => DATA <= x"35";
when x"428" => DATA <= x"06";
when x"429" => DATA <= x"34";
when x"42A" => DATA <= x"06";
when x"42B" => DATA <= x"BD";
when x"42C" => DATA <= x"FC";
when x"42D" => DATA <= x"DE";
when x"42E" => DATA <= x"BD";
when x"42F" => DATA <= x"FA";
when x"430" => DATA <= x"B4";
when x"431" => DATA <= x"35";
when x"432" => DATA <= x"86";
when x"433" => DATA <= x"34";
when x"434" => DATA <= x"06";
when x"435" => DATA <= x"86";
when x"436" => DATA <= x"12";
when x"437" => DATA <= x"BD";
when x"438" => DATA <= x"FC";
when x"439" => DATA <= x"DE";
when x"43A" => DATA <= x"35";
when x"43B" => DATA <= x"06";
when x"43C" => DATA <= x"BD";
when x"43D" => DATA <= x"FC";
when x"43E" => DATA <= x"DE";
when x"43F" => DATA <= x"4D";
when x"440" => DATA <= x"27";
when x"441" => DATA <= x"06";
when x"442" => DATA <= x"BD";
when x"443" => DATA <= x"FC";
when x"444" => DATA <= x"A2";
when x"445" => DATA <= x"7E";
when x"446" => DATA <= x"FA";
when x"447" => DATA <= x"B4";
when x"448" => DATA <= x"34";
when x"449" => DATA <= x"04";
when x"44A" => DATA <= x"BD";
when x"44B" => DATA <= x"FC";
when x"44C" => DATA <= x"DA";
when x"44D" => DATA <= x"BD";
when x"44E" => DATA <= x"FA";
when x"44F" => DATA <= x"B4";
when x"450" => DATA <= x"4F";
when x"451" => DATA <= x"35";
when x"452" => DATA <= x"84";
when x"453" => DATA <= x"34";
when x"454" => DATA <= x"32";
when x"455" => DATA <= x"86";
when x"456" => DATA <= x"14";
when x"457" => DATA <= x"BD";
when x"458" => DATA <= x"FC";
when x"459" => DATA <= x"DE";
when x"45A" => DATA <= x"30";
when x"45B" => DATA <= x"02";
when x"45C" => DATA <= x"10";
when x"45D" => DATA <= x"8E";
when x"45E" => DATA <= x"00";
when x"45F" => DATA <= x"10";
when x"460" => DATA <= x"BD";
when x"461" => DATA <= x"FC";
when x"462" => DATA <= x"AB";
when x"463" => DATA <= x"30";
when x"464" => DATA <= x"1E";
when x"465" => DATA <= x"AE";
when x"466" => DATA <= x"84";
when x"467" => DATA <= x"BD";
when x"468" => DATA <= x"FC";
when x"469" => DATA <= x"A2";
when x"46A" => DATA <= x"35";
when x"46B" => DATA <= x"02";
when x"46C" => DATA <= x"BD";
when x"46D" => DATA <= x"FC";
when x"46E" => DATA <= x"DE";
when x"46F" => DATA <= x"BD";
when x"470" => DATA <= x"FA";
when x"471" => DATA <= x"B4";
when x"472" => DATA <= x"35";
when x"473" => DATA <= x"10";
when x"474" => DATA <= x"34";
when x"475" => DATA <= x"02";
when x"476" => DATA <= x"30";
when x"477" => DATA <= x"02";
when x"478" => DATA <= x"10";
when x"479" => DATA <= x"8E";
when x"47A" => DATA <= x"00";
when x"47B" => DATA <= x"10";
when x"47C" => DATA <= x"BD";
when x"47D" => DATA <= x"FC";
when x"47E" => DATA <= x"BB";
when x"47F" => DATA <= x"30";
when x"480" => DATA <= x"1E";
when x"481" => DATA <= x"35";
when x"482" => DATA <= x"A2";
when x"483" => DATA <= x"34";
when x"484" => DATA <= x"22";
when x"485" => DATA <= x"86";
when x"486" => DATA <= x"16";
when x"487" => DATA <= x"BD";
when x"488" => DATA <= x"FC";
when x"489" => DATA <= x"DE";
when x"48A" => DATA <= x"10";
when x"48B" => DATA <= x"8E";
when x"48C" => DATA <= x"00";
when x"48D" => DATA <= x"0D";
when x"48E" => DATA <= x"BD";
when x"48F" => DATA <= x"FC";
when x"490" => DATA <= x"AB";
when x"491" => DATA <= x"35";
when x"492" => DATA <= x"02";
when x"493" => DATA <= x"BD";
when x"494" => DATA <= x"FC";
when x"495" => DATA <= x"DE";
when x"496" => DATA <= x"10";
when x"497" => DATA <= x"8E";
when x"498" => DATA <= x"00";
when x"499" => DATA <= x"0D";
when x"49A" => DATA <= x"BD";
when x"49B" => DATA <= x"FC";
when x"49C" => DATA <= x"BB";
when x"49D" => DATA <= x"35";
when x"49E" => DATA <= x"20";
when x"49F" => DATA <= x"7E";
when x"4A0" => DATA <= x"FA";
when x"4A1" => DATA <= x"B0";
when x"4A2" => DATA <= x"A6";
when x"4A3" => DATA <= x"80";
when x"4A4" => DATA <= x"8D";
when x"4A5" => DATA <= x"38";
when x"4A6" => DATA <= x"81";
when x"4A7" => DATA <= x"0D";
when x"4A8" => DATA <= x"26";
when x"4A9" => DATA <= x"F8";
when x"4AA" => DATA <= x"39";
when x"4AB" => DATA <= x"34";
when x"4AC" => DATA <= x"04";
when x"4AD" => DATA <= x"1F";
when x"4AE" => DATA <= x"20";
when x"4AF" => DATA <= x"3A";
when x"4B0" => DATA <= x"35";
when x"4B1" => DATA <= x"04";
when x"4B2" => DATA <= x"A6";
when x"4B3" => DATA <= x"82";
when x"4B4" => DATA <= x"8D";
when x"4B5" => DATA <= x"28";
when x"4B6" => DATA <= x"31";
when x"4B7" => DATA <= x"3F";
when x"4B8" => DATA <= x"26";
when x"4B9" => DATA <= x"F8";
when x"4BA" => DATA <= x"39";
when x"4BB" => DATA <= x"34";
when x"4BC" => DATA <= x"04";
when x"4BD" => DATA <= x"1F";
when x"4BE" => DATA <= x"20";
when x"4BF" => DATA <= x"3A";
when x"4C0" => DATA <= x"35";
when x"4C1" => DATA <= x"04";
when x"4C2" => DATA <= x"BD";
when x"4C3" => DATA <= x"FA";
when x"4C4" => DATA <= x"B4";
when x"4C5" => DATA <= x"A7";
when x"4C6" => DATA <= x"82";
when x"4C7" => DATA <= x"31";
when x"4C8" => DATA <= x"3F";
when x"4C9" => DATA <= x"26";
when x"4CA" => DATA <= x"F7";
when x"4CB" => DATA <= x"39";
when x"4CC" => DATA <= x"34";
when x"4CD" => DATA <= x"02";
when x"4CE" => DATA <= x"B6";
when x"4CF" => DATA <= x"FE";
when x"4D0" => DATA <= x"E0";
when x"4D1" => DATA <= x"48";
when x"4D2" => DATA <= x"2A";
when x"4D3" => DATA <= x"FA";
when x"4D4" => DATA <= x"35";
when x"4D5" => DATA <= x"02";
when x"4D6" => DATA <= x"B7";
when x"4D7" => DATA <= x"FE";
when x"4D8" => DATA <= x"E1";
when x"4D9" => DATA <= x"39";
when x"4DA" => DATA <= x"1F";
when x"4DB" => DATA <= x"20";
when x"4DC" => DATA <= x"1F";
when x"4DD" => DATA <= x"98";
when x"4DE" => DATA <= x"34";
when x"4DF" => DATA <= x"02";
when x"4E0" => DATA <= x"B6";
when x"4E1" => DATA <= x"FE";
when x"4E2" => DATA <= x"E2";
when x"4E3" => DATA <= x"48";
when x"4E4" => DATA <= x"2A";
when x"4E5" => DATA <= x"FA";
when x"4E6" => DATA <= x"35";
when x"4E7" => DATA <= x"02";
when x"4E8" => DATA <= x"B7";
when x"4E9" => DATA <= x"FE";
when x"4EA" => DATA <= x"E3";
when x"4EB" => DATA <= x"39";
when x"4EC" => DATA <= x"34";
when x"4ED" => DATA <= x"02";
when x"4EE" => DATA <= x"B6";
when x"4EF" => DATA <= x"FE";
when x"4F0" => DATA <= x"E6";
when x"4F1" => DATA <= x"2B";
when x"4F2" => DATA <= x"51";
when x"4F3" => DATA <= x"B6";
when x"4F4" => DATA <= x"FE";
when x"4F5" => DATA <= x"E0";
when x"4F6" => DATA <= x"2B";
when x"4F7" => DATA <= x"06";
when x"4F8" => DATA <= x"35";
when x"4F9" => DATA <= x"02";
when x"4FA" => DATA <= x"6E";
when x"4FB" => DATA <= x"9F";
when x"4FC" => DATA <= x"FF";
when x"4FD" => DATA <= x"B1";
when x"4FE" => DATA <= x"B6";
when x"4FF" => DATA <= x"FE";
when x"500" => DATA <= x"E1";
when x"501" => DATA <= x"2B";
when x"502" => DATA <= x"1B";
when x"503" => DATA <= x"35";
when x"504" => DATA <= x"02";
when x"505" => DATA <= x"34";
when x"506" => DATA <= x"76";
when x"507" => DATA <= x"8D";
when x"508" => DATA <= x"1C";
when x"509" => DATA <= x"1F";
when x"50A" => DATA <= x"89";
when x"50B" => DATA <= x"4F";
when x"50C" => DATA <= x"1F";
when x"50D" => DATA <= x"02";
when x"50E" => DATA <= x"8D";
when x"50F" => DATA <= x"15";
when x"510" => DATA <= x"1F";
when x"511" => DATA <= x"89";
when x"512" => DATA <= x"4F";
when x"513" => DATA <= x"1F";
when x"514" => DATA <= x"01";
when x"515" => DATA <= x"8D";
when x"516" => DATA <= x"0E";
when x"517" => DATA <= x"AD";
when x"518" => DATA <= x"9F";
when x"519" => DATA <= x"FF";
when x"51A" => DATA <= x"FC";
when x"51B" => DATA <= x"35";
when x"51C" => DATA <= x"76";
when x"51D" => DATA <= x"3B";
when x"51E" => DATA <= x"48";
when x"51F" => DATA <= x"B7";
when x"520" => DATA <= x"FF";
when x"521" => DATA <= x"80";
when x"522" => DATA <= x"35";
when x"523" => DATA <= x"02";
when x"524" => DATA <= x"3B";
when x"525" => DATA <= x"B6";
when x"526" => DATA <= x"FE";
when x"527" => DATA <= x"E6";
when x"528" => DATA <= x"2B";
when x"529" => DATA <= x"02";
when x"52A" => DATA <= x"8D";
when x"52B" => DATA <= x"12";
when x"52C" => DATA <= x"B6";
when x"52D" => DATA <= x"FE";
when x"52E" => DATA <= x"E0";
when x"52F" => DATA <= x"2A";
when x"530" => DATA <= x"F4";
when x"531" => DATA <= x"B6";
when x"532" => DATA <= x"FE";
when x"533" => DATA <= x"E1";
when x"534" => DATA <= x"39";
when x"535" => DATA <= x"B6";
when x"536" => DATA <= x"FE";
when x"537" => DATA <= x"E6";
when x"538" => DATA <= x"2A";
when x"539" => DATA <= x"FB";
when x"53A" => DATA <= x"B6";
when x"53B" => DATA <= x"FE";
when x"53C" => DATA <= x"E7";
when x"53D" => DATA <= x"39";
when x"53E" => DATA <= x"1C";
when x"53F" => DATA <= x"7F";
when x"540" => DATA <= x"34";
when x"541" => DATA <= x"01";
when x"542" => DATA <= x"34";
when x"543" => DATA <= x"02";
when x"544" => DATA <= x"35";
when x"545" => DATA <= x"02";
when x"546" => DATA <= x"34";
when x"547" => DATA <= x"16";
when x"548" => DATA <= x"B6";
when x"549" => DATA <= x"FE";
when x"54A" => DATA <= x"E7";
when x"54B" => DATA <= x"2A";
when x"54C" => DATA <= x"22";
when x"54D" => DATA <= x"10";
when x"54E" => DATA <= x"CE";
when x"54F" => DATA <= x"FF";
when x"550" => DATA <= x"80";
when x"551" => DATA <= x"8E";
when x"552" => DATA <= x"FF";
when x"553" => DATA <= x"00";
when x"554" => DATA <= x"BD";
when x"555" => DATA <= x"FA";
when x"556" => DATA <= x"B4";
when x"557" => DATA <= x"86";
when x"558" => DATA <= x"3F";
when x"559" => DATA <= x"A7";
when x"55A" => DATA <= x"80";
when x"55B" => DATA <= x"BD";
when x"55C" => DATA <= x"FA";
when x"55D" => DATA <= x"B4";
when x"55E" => DATA <= x"A7";
when x"55F" => DATA <= x"80";
when x"560" => DATA <= x"BD";
when x"561" => DATA <= x"FA";
when x"562" => DATA <= x"B4";
when x"563" => DATA <= x"A7";
when x"564" => DATA <= x"80";
when x"565" => DATA <= x"26";
when x"566" => DATA <= x"F9";
when x"567" => DATA <= x"8E";
when x"568" => DATA <= x"FF";
when x"569" => DATA <= x"01";
when x"56A" => DATA <= x"34";
when x"56B" => DATA <= x"10";
when x"56C" => DATA <= x"7E";
when x"56D" => DATA <= x"FF";
when x"56E" => DATA <= x"BC";
when x"56F" => DATA <= x"34";
when x"570" => DATA <= x"02";
when x"571" => DATA <= x"8D";
when x"572" => DATA <= x"C2";
when x"573" => DATA <= x"35";
when x"574" => DATA <= x"02";
when x"575" => DATA <= x"81";
when x"576" => DATA <= x"05";
when x"577" => DATA <= x"26";
when x"578" => DATA <= x"06";
when x"579" => DATA <= x"7F";
when x"57A" => DATA <= x"FF";
when x"57B" => DATA <= x"94";
when x"57C" => DATA <= x"35";
when x"57D" => DATA <= x"16";
when x"57E" => DATA <= x"3B";
when x"57F" => DATA <= x"34";
when x"580" => DATA <= x"02";
when x"581" => DATA <= x"8D";
when x"582" => DATA <= x"B2";
when x"583" => DATA <= x"B7";
when x"584" => DATA <= x"FF";
when x"585" => DATA <= x"8C";
when x"586" => DATA <= x"8D";
when x"587" => DATA <= x"AD";
when x"588" => DATA <= x"B7";
when x"589" => DATA <= x"FF";
when x"58A" => DATA <= x"8D";
when x"58B" => DATA <= x"8D";
when x"58C" => DATA <= x"A8";
when x"58D" => DATA <= x"B7";
when x"58E" => DATA <= x"FF";
when x"58F" => DATA <= x"8E";
when x"590" => DATA <= x"8D";
when x"591" => DATA <= x"A3";
when x"592" => DATA <= x"B7";
when x"593" => DATA <= x"FF";
when x"594" => DATA <= x"8F";
when x"595" => DATA <= x"8D";
when x"596" => DATA <= x"9E";
when x"597" => DATA <= x"86";
when x"598" => DATA <= x"FF";
when x"599" => DATA <= x"B7";
when x"59A" => DATA <= x"FF";
when x"59B" => DATA <= x"94";
when x"59C" => DATA <= x"1C";
when x"59D" => DATA <= x"BF";
when x"59E" => DATA <= x"BE";
when x"59F" => DATA <= x"FF";
when x"5A0" => DATA <= x"8E";
when x"5A1" => DATA <= x"A6";
when x"5A2" => DATA <= x"E0";
when x"5A3" => DATA <= x"27";
when x"5A4" => DATA <= x"6C";
when x"5A5" => DATA <= x"81";
when x"5A6" => DATA <= x"02";
when x"5A7" => DATA <= x"25";
when x"5A8" => DATA <= x"5B";
when x"5A9" => DATA <= x"27";
when x"5AA" => DATA <= x"49";
when x"5AB" => DATA <= x"81";
when x"5AC" => DATA <= x"04";
when x"5AD" => DATA <= x"25";
when x"5AE" => DATA <= x"35";
when x"5AF" => DATA <= x"27";
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when x"7C9" => DATA <= x"FA";
when x"7CA" => DATA <= x"86";
when x"7CB" => DATA <= x"7E";
when x"7CC" => DATA <= x"FA";
when x"7CD" => DATA <= x"86";
when x"7CE" => DATA <= x"7E";
when x"7CF" => DATA <= x"FC";
when x"7D0" => DATA <= x"33";
when x"7D1" => DATA <= x"7E";
when x"7D2" => DATA <= x"FC";
when x"7D3" => DATA <= x"83";
when x"7D4" => DATA <= x"7E";
when x"7D5" => DATA <= x"FC";
when x"7D6" => DATA <= x"1D";
when x"7D7" => DATA <= x"7E";
when x"7D8" => DATA <= x"FC";
when x"7D9" => DATA <= x"0E";
when x"7DA" => DATA <= x"7E";
when x"7DB" => DATA <= x"FB";
when x"7DC" => DATA <= x"EA";
when x"7DD" => DATA <= x"7E";
when x"7DE" => DATA <= x"FC";
when x"7DF" => DATA <= x"53";
when x"7E0" => DATA <= x"7E";
when x"7E1" => DATA <= x"FA";
when x"7E2" => DATA <= x"AC";
when x"7E3" => DATA <= x"81";
when x"7E4" => DATA <= x"0D";
when x"7E5" => DATA <= x"26";
when x"7E6" => DATA <= x"07";
when x"7E7" => DATA <= x"86";
when x"7E8" => DATA <= x"0A";
when x"7E9" => DATA <= x"BD";
when x"7EA" => DATA <= x"FF";
when x"7EB" => DATA <= x"EE";
when x"7EC" => DATA <= x"86";
when x"7ED" => DATA <= x"0D";
when x"7EE" => DATA <= x"7E";
when x"7EF" => DATA <= x"FC";
when x"7F0" => DATA <= x"CC";
when x"7F1" => DATA <= x"7E";
when x"7F2" => DATA <= x"FB";
when x"7F3" => DATA <= x"33";
when x"7F4" => DATA <= x"7E";
when x"7F5" => DATA <= x"FA";
when x"7F6" => DATA <= x"BD";
when x"7F7" => DATA <= x"7E";
when x"7F8" => DATA <= x"F9";
when x"7F9" => DATA <= x"76";
when x"7FA" => DATA <= x"F8";
when x"7FB" => DATA <= x"B0";
when x"7FC" => DATA <= x"FA";
when x"7FD" => DATA <= x"86";
when x"7FE" => DATA <= x"F8";
when x"7FF" => DATA <= x"2C";
when others => DATA <= (others => '0');
end case;
end process;
end RTL;
| gpl-3.0 | e8634c914e738c5504ea41d968968952 | 0.358739 | 2.978535 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-xilinx-sp605/leon3mp.vhd | 1 | 35,682 | -----------------------------------------------------------------------------
-- LEON3 Xilinx SP605 Demonstration design
-- Copyright (C) 2011 Jiri Gaisler, Aeroflex Gaisler
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.amba.all;
use grlib.stdlib.all;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.spi.all;
use gaisler.i2c.all;
use gaisler.can.all;
use gaisler.net.all;
use gaisler.jtag.all;
use gaisler.spacewire.all;
-- pragma translate_off
use gaisler.sim.all;
library unisim;
use unisim.ODDR2;
-- pragma translate_on
library esa;
use esa.memoryctrl.all;
use work.config.all;
use work.pcie.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
reset : in std_ulogic;
clk27 : in std_ulogic; -- 27 MHz clock
clk200p : in std_ulogic; -- 200 MHz clock
clk200n : in std_ulogic; -- 200 MHz clock
clk33 : in std_ulogic; -- 32 MHz clock from sysace
address : out std_logic_vector(23 downto 0);
data : inout std_logic_vector(15 downto 0);
oen : out std_ulogic;
writen : out std_ulogic;
romsn : out std_logic;
ddr_clk : out std_logic;
ddr_clkb : out std_logic;
ddr_cke : out std_logic;
ddr_odt : out std_logic;
ddr_reset_n : out std_logic;
ddr_we : out std_ulogic; -- ddr write enable
ddr_ras : out std_ulogic; -- ddr ras
ddr_cas : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (1 downto 0); -- ddr dqs
ddr_dqs_n : inout std_logic_vector (1 downto 0); -- ddr dqs_n
ddr_ad : out std_logic_vector (12 downto 0); -- ddr address
ddr_ba : out std_logic_vector (2 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (15 downto 0); -- ddr data
ddr_rzq : inout std_ulogic;
ddr_zio : inout std_ulogic;
txd1 : out std_ulogic; -- UART1 tx data
rxd1 : in std_ulogic; -- UART1 rx data
ctsn1 : in std_ulogic; -- UART1 ctsn
rtsn1 : out std_ulogic; -- UART1 trsn
button : inout std_logic_vector(3 downto 0); -- I/O port
switch : inout std_logic_vector(3 downto 0); -- I/O port
led : out std_logic_vector(3 downto 0); -- I/O port
phy_gtx_clk : out std_logic;
phy_mii_data : inout std_logic; -- ethernet PHY interface
phy_tx_clk : in std_ulogic;
phy_rx_clk : in std_ulogic;
phy_rx_data : in std_logic_vector(7 downto 0);
phy_dv : in std_ulogic;
phy_rx_er : in std_ulogic;
phy_col : in std_ulogic;
phy_crs : in std_ulogic;
phy_tx_data : out std_logic_vector(7 downto 0);
phy_tx_en : out std_ulogic;
phy_tx_er : out std_ulogic;
phy_mii_clk : out std_ulogic;
phy_rst_n : out std_ulogic;
phy_mii_int_n : in std_ulogic;
iic_scl : inout std_ulogic;
iic_sda : inout std_ulogic;
ddc_scl : inout std_ulogic;
ddc_sda : inout std_ulogic;
dvi_iic_scl : inout std_logic;
dvi_iic_sda : inout std_logic;
tft_lcd_data : out std_logic_vector(11 downto 0);
tft_lcd_clk_p : out std_ulogic;
tft_lcd_clk_n : out std_ulogic;
tft_lcd_hsync : out std_ulogic;
tft_lcd_vsync : out std_ulogic;
tft_lcd_de : out std_ulogic;
tft_lcd_reset_b : out std_ulogic;
-- SPI flash
spi_sel_n : inout std_ulogic;
spi_clk : out std_ulogic;
spi_mosi : out std_ulogic;
--pcie
pci_exp_txp : out std_logic;
pci_exp_txn : out std_logic;
pci_exp_rxp : in std_logic;
pci_exp_rxn : in std_logic;
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
sys_reset_n : in std_logic;
sysace_mpa : out std_logic_vector(6 downto 0);
sysace_mpce : out std_ulogic;
sysace_mpirq : in std_ulogic;
sysace_mpoe : out std_ulogic;
sysace_mpwe : out std_ulogic;
sysace_d : inout std_logic_vector(7 downto 0)
);
end;
architecture rtl of leon3mp is
--attribute syn_netlist_hierarchy : boolean;
--attribute syn_netlist_hierarchy of rtl : architecture is false;
component ODDR2
generic (
DDR_ALIGNMENT : string := "NONE";
INIT : bit := '0';
SRTYPE : string := "SYNC"
);
port (
Q : out std_ulogic;
C0 : in std_ulogic;
C1 : in std_ulogic;
CE : in std_ulogic := 'H';
D0 : in std_ulogic;
D1 : in std_ulogic;
R : in std_ulogic := 'L';
S : in std_ulogic := 'L'
);
end component;
constant blength : integer := 12;
constant fifodepth : integer := 8;
constant maxahbm : integer := CFG_NCPU+CFG_GRETH+CFG_AHB_JTAG+CFG_PCIEXP;
signal vcc, gnd : std_logic;
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal vahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal vahbmo : ahb_mst_out_type;
signal clkm, rstn, rstraw, sdclkl : std_ulogic;
signal clk_200 : std_ulogic;
signal clk25, clk40, clk65 : std_ulogic;
signal cgi, cgi2 : clkgen_in_type;
signal cgo, cgo2 : clkgen_out_type;
signal u1i, u2i, dui : uart_in_type;
signal u1o, u2o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal ethi : eth_in_type;
signal etho : eth_out_type;
signal egtx_clk :std_ulogic;
signal negtx_clk :std_ulogic;
signal gpti : gptimer_in_type;
signal gpto : gptimer_out_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal clklock, elock, ulock : std_ulogic;
signal lock, calib_done, clkml, lclk, rst, ndsuact : std_ulogic;
signal tck, tckn, tms, tdi, tdo : std_ulogic;
signal ethclk : std_ulogic;
signal vgao : apbvga_out_type;
signal lcd_datal : std_logic_vector(11 downto 0);
signal lcd_hsyncl, lcd_vsyncl, lcd_del, lcd_reset_bl : std_ulogic;
signal i2ci, dvi_i2ci : i2c_in_type;
signal i2co, dvi_i2co : i2c_out_type;
signal spmi : spimctrl_in_type;
signal spmo : spimctrl_out_type;
signal spmi2 : spimctrl_in_type;
signal spmo2 : spimctrl_out_type;
constant BOARD_FREQ : integer := 33000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
constant IOAEN : integer := CFG_GRACECTRL;
constant DDR2_FREQ : integer := 200000; -- DDR2 input frequency in KHz
signal stati : ahbstat_in_type;
signal fpi : grfpu_in_vector_type;
signal fpo : grfpu_out_vector_type;
-- Used for connecting input/output signals to the DDR2 controller
signal core_ddr_clk : std_logic_vector(2 downto 0);
signal core_ddr_clkb : std_logic_vector(2 downto 0);
signal core_ddr_cke : std_logic_vector(1 downto 0);
signal core_ddr_csb : std_logic_vector(1 downto 0);
signal core_ddr_ad : std_logic_vector(13 downto 0);
signal core_ddr_odt : std_logic_vector(1 downto 0);
signal video_clk : std_ulogic; -- signals to vga_clkgen.
signal clk_sel : std_logic_vector(1 downto 0);
signal clkvga, clkvga_p, clkvga_n : std_ulogic;
signal acei : gracectrl_in_type;
signal aceo : gracectrl_out_type;
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of video_clk : signal is true;
attribute syn_preserve of video_clk : signal is true;
attribute keep of video_clk : signal is true;
attribute syn_preserve of clkm : signal is true;
attribute keep of clkm : signal is true;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= '1'; gnd <= '0';
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
ethclk <= lclk;
clk_pad : clkpad generic map (tech => padtech) port map (clk33, lclk);
clkgen0 : clkgen -- clock generator
generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
CFG_CLK_NOFB, 0, 0, 0, BOARD_FREQ)
port map (lclk, lclk, clkm, open, open, sdclkl, open, cgi, cgo, open, open, open);
reset_pad : inpad generic map (tech => padtech) port map (reset, rst);
rst0 : rstgen -- reset generator
generic map (acthigh => 1)
port map (rst, clkm, lock, rstn, rstraw);
lock <= cgo.clklock and calib_done when CFG_MIG_DDR2 = 1 else cgo.clklock;
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, fpnpen => CFG_FPNPEN,
ioen => IOAEN, nahbm => maxahbm, nahbs => 16)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
nosh : if CFG_GRFPUSH = 0 generate
cpu : for i in 0 to CFG_NCPU-1 generate
l3ft : if CFG_LEON3FT_EN /= 0 generate
leon3ft0 : leon3ft -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU*(1-CFG_GRFPUSH), CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_IUFT_EN, CFG_FPUFT_EN, CFG_CACHE_FT_EN, CFG_RF_ERRINJ,
CFG_CACHE_ERRINJ, CFG_DFIXED, CFG_LEON3_NETLIST, CFG_SCAN, CFG_MMU_PAGE,
CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), clkm);
end generate;
l3s : if CFG_LEON3FT_EN = 0 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU*(1-CFG_GRFPUSH), CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
end generate;
end generate;
sh : if CFG_GRFPUSH = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
l3ft : if CFG_LEON3FT_EN /= 0 generate
leon3ft0 : leon3ftsh -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_IUFT_EN, CFG_FPUFT_EN, CFG_CACHE_FT_EN, CFG_RF_ERRINJ,
CFG_CACHE_ERRINJ, CFG_DFIXED, CFG_LEON3_NETLIST, CFG_SCAN, CFG_MMU_PAGE,
CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), clkm, fpi(i), fpo(i));
end generate;
l3s : if CFG_LEON3FT_EN = 0 generate
u0 : leon3sh -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), fpi(i), fpo(i));
end generate;
end generate;
grfpush0 : grfpushwx generic map ((CFG_FPU-1), CFG_NCPU, fabtech)
port map (clkm, rstn, fpi, fpo);
end generate;
led1_pad : odpad generic map (tech => padtech) port map (led(1), dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
dsui.break <= button(3);
dsuact_pad : outpad generic map (tech => padtech) port map (led(0), ndsuact);
ndsuact <= not dsuo.active;
end generate;
nodsu : if CFG_DSU = 0 generate
dsuo.tstop <= '0'; dsuo.active <= '0'; ahbso(2) <= ahbs_none;
end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU),
open, open, open, open, open, open, open, gnd);
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "01";
memi.brdyn <= '0'; memi.bexcn <= '1';
mctrl_gen : if CFG_MCTRL_LEON2 /= 0 generate
mctrl0 : mctrl generic map (hindex => 0, pindex => 0,
paddr => 0, srbanks => 2, ram8 => CFG_MCTRL_RAM8BIT,
ram16 => CFG_MCTRL_RAM16BIT, sden => CFG_MCTRL_SDEN,
invclk => CFG_CLK_NOFB, sepbus => CFG_MCTRL_SEPBUS,
pageburst => CFG_MCTRL_PAGE, rammask => 0, iomask => 0)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
addr_pad : outpadv generic map (width => 24, tech => padtech)
port map (address, memo.address(24 downto 1));
roms_pad : outpad generic map (tech => padtech)
port map (romsn, memo.romsn(0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.oen);
wri_pad : outpad generic map (tech => padtech)
port map (writen, memo.writen);
data_pad : iopadvv generic map (tech => padtech, width => 16)
port map (data(15 downto 0), memo.data(31 downto 16),
memo.vbdrive(31 downto 16), memi.data(31 downto 16));
end generate;
nomctrl : if CFG_MCTRL_LEON2 = 0 generate
roms_pad : outpad generic map (tech => padtech)
port map (romsn, vcc); --ahbso(0) <= ahbso_none;
end generate;
-----------------------------------------------------------------------
--- Test report module ----------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
test0 : ahbrep generic map (hindex => 6, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(6));
-- pragma translate_on
----------------------------------------------------------------------
--- DDR2 memory controller ------------------------------------------
----------------------------------------------------------------------
mig_gen : if (CFG_MIG_DDR2 = 1) generate
ddrc : entity work.ahb2mig_sp605 generic map(
hindex => 4, haddr => 16#400#, hmask => 16#F80#,
pindex => 4, paddr => 4,
vgamst => CFG_SVGA_ENABLE, vgaburst => 64)
port map(
mcb3_dram_dq => ddr_dq,
mcb3_dram_a => ddr_ad,
mcb3_dram_ba => ddr_ba,
mcb3_dram_ras_n => ddr_ras,
mcb3_dram_cas_n => ddr_cas,
mcb3_dram_we_n => ddr_we,
mcb3_dram_odt => ddr_odt,
mcb3_dram_reset_n=> ddr_reset_n,
mcb3_dram_cke => ddr_cke,
mcb3_dram_dm => ddr_dm(0),
mcb3_dram_udqs => ddr_dqs(1),
mcb3_dram_udqs_n=> ddr_dqs_n(1),
mcb3_rzq => ddr_rzq,
mcb3_zio => ddr_zio,
mcb3_dram_udm => ddr_dm(1),
mcb3_dram_dqs => ddr_dqs(0),
mcb3_dram_dqs_n => ddr_dqs_n(0),
mcb3_dram_ck => ddr_clk,
mcb3_dram_ck_n => ddr_clkb,
ahbsi => ahbsi,
ahbso => ahbso(4),
ahbmi => vahbmi,
ahbmo => vahbmo,
apbi => apbi,
apbo => apbo(4),
calib_done => calib_done,
rst_n_syn => rstn,
rst_n_async => rstraw,
clk_amba => clkm,
clk_mem_p => clk200p,
clk_mem_n => clk200n,
clk_125 => egtx_clk,
clk_50 => video_clk
);
end generate;
led(2) <= calib_done;
led(3) <= lock;
noddr : if CFG_MIG_DDR2 = 0 generate lock <= '1'; end generate;
-----------------PCI-EXPRESS-Master-Target------------------------------------------
pcie_mt : if CFG_PCIE_TYPE = 1 generate -- master/target without fifo
EP:pcie_master_target_sp605
generic map (
master => CFG_PCIE_SIM_MAS,
hmstndx => CFG_NCPU+CFG_GRETH+CFG_AHB_JTAG,
hslvndx => 7,
abits => 21,
device_id => CFG_PCIEXPDID, -- PCIE device ID
vendor_id => CFG_PCIEXPVID, -- PCIE vendor ID
nsync => 2, -- 1 or 2 sync regs between clocks
pcie_bar_mask => 16#FFE#,
haddr => 16#a00#,
hmask => 16#fff#,
pindex => 5,
paddr => 5,
pmask => 16#fff#
)
port map(
rst => rstn,
clk => clkm,
-- System Interface
sys_clk_p => sys_clk_p,
sys_clk_n => sys_clk_n,
sys_reset_n => sys_reset_n,
-- PCI Express Fabric Interface
pci_exp_txp => pci_exp_txp,
pci_exp_txn => pci_exp_txn,
pci_exp_rxp => pci_exp_rxp,
pci_exp_rxn => pci_exp_rxn,
ahbso => ahbso(7),
ahbsi => ahbsi,
apbi => apbi,
apbo => apbo(5),
ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_GRETH+CFG_AHB_JTAG)
);
end generate;
----------------------------------------------------------------------
-----------------PCI-EXPRESS-Master-FIFO------------------------------------------
pcie_mf_dma : if CFG_PCIE_TYPE = 3 generate -- master with fifo and DMA
dma:pciedma
generic map (memtech => memtech, dmstndx => CFG_NCPU+CFG_GRETH+CFG_AHB_JTAG,
dapbndx => 7, dapbaddr => 7,dapbmask => 16#FFF#, dapbirq => 4, blength => 12,
device_id => CFG_PCIEXPDID, vendor_id => CFG_PCIEXPVID,
slvndx => 7, apbndx => 5, apbaddr => 5, apbmask =>16#FFF#, haddr => 16#A00#, hmask => 16#FFF#,
nsync => 2, pcie_bar_mask => 16#FFE#
)
port map(
rst => rstn,
clk => clkm,
-- System Interface
sys_clk_p => sys_clk_p,
sys_clk_n => sys_clk_n,
sys_reset_n => sys_reset_n,
-- PCI Express Fabric Interface
pci_exp_txp => pci_exp_txp,
pci_exp_txn => pci_exp_txn,
pci_exp_rxp => pci_exp_rxp,
pci_exp_rxn => pci_exp_rxn,
dapbo => apbo(7),
dahbmo =>ahbmo(CFG_NCPU+CFG_GRETH+CFG_AHB_JTAG),
apbi =>apbi,
apbo =>apbo(5),
ahbmi =>ahbmi,
ahbsi =>ahbsi,
ahbso =>ahbso(7)
);
end generate;
pcie_mf: if CFG_PCIE_TYPE = 2 generate -- master with fifo
EP:pcie_master_fifo_sp605
generic map (
memtech => memtech,
hslvndx => 7,
device_id => CFG_PCIEXPDID, -- PCIE device ID
vendor_id => CFG_PCIEXPVID, -- PCIE vendor ID
nsync => 2, -- 1 or 2 sync regs between clocks
pcie_bar_mask => 16#FFE#,
haddr => 16#A00#,
hmask => 16#fff#,
pindex => 5,
paddr => 5,
pmask => 16#fff#)
port map(
rst => rstn,
clk => clkm,
-- System In
sys_clk_p => sys_clk_p,
sys_clk_n => sys_clk_n,
sys_reset_n => sys_reset_n,
-- PCI Expre
pci_exp_txp => pci_exp_txp,
pci_exp_txn => pci_exp_txn,
pci_exp_rxp => pci_exp_rxp,
pci_exp_rxn => pci_exp_rxn,
ahbso => ahbso(7),
ahbsi => ahbsi,
apbi => apbi,
apbo => apbo(5)
);
end generate;
----------------------------------------------------------------------
----------------------------------------------------------------------
----------------------------------------------------------------------
--- SPI Memory Controller--------------------------------------------
----------------------------------------------------------------------
spimc: if CFG_SPICTRL_ENABLE = 0 and CFG_SPIMCTRL = 1 generate
spimctrl0 : spimctrl -- SPI Memory Controller
generic map (hindex => 3, hirq => 5, faddr => 16#e00#, fmask => 16#ff8#,
ioaddr => 16#002#, iomask => 16#fff#,
spliten => CFG_SPLIT, oepol => 0,
sdcard => CFG_SPIMCTRL_SDCARD,
readcmd => CFG_SPIMCTRL_READCMD,
dummybyte => CFG_SPIMCTRL_DUMMYBYTE,
dualoutput => CFG_SPIMCTRL_DUALOUTPUT,
scaler => CFG_SPIMCTRL_SCALER,
altscaler => CFG_SPIMCTRL_ASCALER,
pwrupcnt => CFG_SPIMCTRL_PWRUPCNT)
port map (rstn, clkm, ahbsi, ahbso(3), spmi, spmo);
-- MISO is shared with Flash data 0
spmi.miso <= memi.data(16);
mosi_pad : outpad generic map (tech => padtech)
port map (spi_mosi, spmo.mosi);
sck_pad : outpad generic map (tech => padtech)
port map (spi_clk, spmo.sck);
slvsel0_pad : odpad generic map (tech => padtech)
port map (spi_sel_n, spmo.csn);
end generate;
nospimc: if ((CFG_SPICTRL_ENABLE = 0 and CFG_SPIMCTRL = 0) or
(CFG_SPICTRL_ENABLE = 1 and CFG_SPIMCTRL = 1) or
(CFG_SPICTRL_ENABLE = 1 and CFG_SPIMCTRL = 0))generate
mosi_pad : outpad generic map (tech => padtech)
port map (spi_mosi, '0');
sck_pad : outpad generic map (tech => padtech)
port map (spi_clk, '0');
end generate;
----------------------------------------------------------------------
--- System ACE I/F Controller ---------------------------------------
----------------------------------------------------------------------
grace: if CFG_GRACECTRL = 1 generate
grace0 : gracectrl generic map (hindex => 8, hirq => 10,
haddr => 16#002#, hmask => 16#fff#, split => CFG_SPLIT, mode => 2)
port map (rstn, clkm, lclk, ahbsi, ahbso(8), acei, aceo);
end generate;
nograce: if CFG_GRACECTRL /= 1 generate
aceo <= gracectrl_none;
end generate;
sysace_mpa_pads : outpadv generic map (width => 7, tech => padtech)
port map (sysace_mpa, aceo.addr);
sysace_mpce_pad : outpad generic map (tech => padtech)
port map (sysace_mpce, aceo.cen);
sysace_d_pads : iopadv generic map (tech => padtech, width => 8)
port map (sysace_d, aceo.do(7 downto 0), aceo.doen, acei.di(7 downto 0));
acei.di(15 downto 8) <= (others => '0');
sysace_mpoe_pad : outpad generic map (tech => padtech)
port map (sysace_mpoe, aceo.oen);
sysace_mpwe_pad : outpad generic map (tech => padtech)
port map (sysace_mpwe, aceo.wen);
sysace_mpirq_pad : inpad generic map (tech => padtech)
port map (sysace_mpirq, acei.irq);
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR, nslaves => 16)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.extclk <= '0';
rxd1_pad : inpad generic map (tech => padtech) port map (rxd1, u1i.rxd);
txd1_pad : outpad generic map (tech => padtech) port map (txd1, u1o.txd);
cts1_pad : inpad generic map (tech => padtech) port map (ctsn1, u1i.ctsn);
rts1_pad : outpad generic map (tech => padtech) port map (rtsn1, u1o.rtsn);
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW, wdog => 0)
port map (rstn, clkm, apbi, apbo(3), gpti, gpto);
gpti <= gpti_dhalt_drive(dsuo.tstop);
end generate;
nogpt : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
vga : if CFG_VGA_ENABLE /= 0 generate
vga0 : apbvga generic map(memtech => memtech, pindex => 6, paddr => 6)
port map(rstn, clkm, ethclk, apbi, apbo(6), vgao);
-- video_clk <= not ethclk;
end generate;
svga : if CFG_SVGA_ENABLE /= 0 generate
svga0 : svgactrl generic map(memtech => memtech, pindex => 6, paddr => 6,
hindex => CFG_NCPU+CFG_AHB_JTAG,
clk0 => 20000, clk1 => 0, --1000000000/((BOARD_FREQ * CFG_CLKMUL)/CFG_CLKDIV),
clk2 => 0, clk3 => 0, burstlen => 6)
port map(rstn, clkm, video_clk, apbi, apbo(6), vgao, vahbmi,
vahbmo, clk_sel);
end generate;
vgadvi : if (CFG_VGA_ENABLE + CFG_SVGA_ENABLE) /= 0 generate
-- b0 : techbuf generic map (2, fabtech) port map (clk50, video_clk);
dvi0 : entity work.svga2ch7301c generic map (tech => fabtech, dynamic => 1)
port map (clkm, vgao, video_clk, clkvga_p, clkvga_n,
lcd_datal, lcd_hsyncl, lcd_vsyncl, lcd_del);
i2cdvi : i2cmst
generic map (pindex => 9, paddr => 9, pmask => 16#FFF#, pirq => 11)
port map (rstn, clkm, apbi, apbo(9), dvi_i2ci, dvi_i2co);
end generate;
novga : if (CFG_VGA_ENABLE = 0 and CFG_SVGA_ENABLE = 0) generate
apbo(6) <= apb_none; vgao <= vgao_none;
end generate;
tft_lcd_data_pad : outpadv generic map (width => 12, tech => padtech)
port map (tft_lcd_data, lcd_datal);
tft_lcd_clkp_pad : outpad generic map (tech => padtech)
port map (tft_lcd_clk_p, clkvga_p);
tft_lcd_clkn_pad : outpad generic map (tech => padtech)
port map (tft_lcd_clk_n, clkvga_n);
tft_lcd_hsync_pad : outpad generic map (tech => padtech)
port map (tft_lcd_hsync, lcd_hsyncl);
tft_lcd_vsync_pad : outpad generic map (tech => padtech)
port map (tft_lcd_vsync, lcd_vsyncl);
tft_lcd_de_pad : outpad generic map (tech => padtech)
port map (tft_lcd_de, lcd_del);
tft_lcd_reset_pad : outpad generic map (tech => padtech)
port map (tft_lcd_reset_b, rstn);
dvi_i2c_scl_pad : iopad generic map (tech => padtech)
port map (dvi_iic_scl, dvi_i2co.scl, dvi_i2co.scloen, dvi_i2ci.scl);
dvi_i2c_sda_pad : iopad generic map (tech => padtech)
port map (dvi_iic_sda, dvi_i2co.sda, dvi_i2co.sdaoen, dvi_i2ci.sda);
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map(pindex => 10, paddr => 10, imask => CFG_GRGPIO_IMASK, nbits => 7)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(10),
gpioi => gpioi, gpioo => gpioo);
pio_pads : for i in 0 to 3 generate
pio_pad : iopad generic map (tech => padtech)
port map (switch(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
pio_pads2 : for i in 4 to 6 generate
pio_pad : iopad generic map (tech => padtech)
port map (button(i-4), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
stati <= ahbstat_in_none;
ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 7,
nftslv => CFG_AHBSTATN)
port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15));
end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
negtx_clk <= not egtx_clk;
x0 : ODDR2 port map ( Q => phy_gtx_clk, C0 => egtx_clk,
C1 => negtx_clk, CE => vcc,
D0 => vcc, D1 => gnd, R => gnd, S => gnd);
e1 : grethm generic map( hindex => CFG_NCPU+CFG_AHB_JTAG,
pindex => 14, paddr => 14, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, rmii => 0, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF, phyrstadr => 7,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, enable_mdint => 1,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL,
giga => CFG_GRETH1G)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_JTAG), apbi => apbi, apbo => apbo(14),
ethi => ethi, etho => etho);
emdio_pad : iopad generic map (tech => padtech)
port map (phy_mii_data, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (phy_tx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (phy_rx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 8)
port map (phy_rx_data, ethi.rxd(7 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (phy_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (phy_rx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (phy_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (phy_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 8)
port map (phy_tx_data, etho.txd(7 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map ( phy_tx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (phy_tx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (phy_mii_clk, etho.mdc);
erst_pad : outpad generic map (tech => padtech)
port map (phy_rst_n, rstn);
emdintn_pad : inpad generic map (tech => padtech)
port map (phy_mii_int_n, ethi.mdint);
ethi.gtx_clk <= egtx_clk;
end generate;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 5, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(5));
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map ( rstn, clkm, ahbsi, ahbso(7));
end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
-- nam1 : for i in (CFG_NCPU+CFG_GRETH+CFG_AHB_JTAG+CFG_PCIEXP) to NAHBMST-1 generate
-- ahbmo(i) <= ahbm_none;
-- end generate;
-- nap0 : for i in 11 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
-- nah0 : for i in 8 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Xilinx SP605 Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
| gpl-3.0 | 0fe602d198c90c55ed4f1b6c30affa35 | 0.548876 | 3.49344 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-altera-c5ekit/ddr3if.vhd | 1 | 9,578 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
library gaisler;
use gaisler.ddrpkg.all;
entity ddr3if is
generic (
hindex: integer;
haddr: integer := 16#400#;
hmask: integer := 16#000#;
burstlen: integer := 8
);
port (
pll_ref_clk: in std_ulogic;
global_reset_n: in std_ulogic;
mem_a: out std_logic_vector(13 downto 0);
mem_ba: out std_logic_vector(2 downto 0);
mem_ck: out std_ulogic;
mem_ck_n: out std_ulogic;
mem_cke: out std_ulogic;
mem_reset_n: out std_ulogic;
mem_cs_n: out std_ulogic;
mem_dm: out std_logic_vector(3 downto 0);
mem_ras_n: out std_ulogic;
mem_cas_n: out std_ulogic;
mem_we_n: out std_ulogic;
mem_dq: inout std_logic_vector(31 downto 0);
mem_dqs: inout std_logic_vector(3 downto 0);
mem_dqs_n: inout std_logic_vector(3 downto 0);
mem_odt: out std_ulogic;
oct_rzqin: in std_logic;
ahb_clk: in std_ulogic;
ahb_rst: in std_ulogic;
ahbsi: in ahb_slv_in_type;
ahbso: out ahb_slv_out_type
);
end;
architecture rtl of ddr3if is
component ddr3ctrl1 is
port (
pll_ref_clk : in std_logic := 'X'; -- clk
global_reset_n : in std_logic := 'X'; -- reset_n
soft_reset_n : in std_logic := 'X'; -- reset_n
afi_clk : out std_logic; -- clk
afi_half_clk : out std_logic; -- clk
afi_reset_n : out std_logic; -- reset_n
afi_reset_export_n : out std_logic; -- reset_n
mem_a : out std_logic_vector(13 downto 0); -- mem_a
mem_ba : out std_logic_vector(2 downto 0); -- mem_ba
mem_ck : out std_logic_vector(0 downto 0); -- mem_ck
mem_ck_n : out std_logic_vector(0 downto 0); -- mem_ck_n
mem_cke : out std_logic_vector(0 downto 0); -- mem_cke
mem_cs_n : out std_logic_vector(0 downto 0); -- mem_cs_n
mem_dm : out std_logic_vector(3 downto 0); -- mem_dm
mem_ras_n : out std_logic_vector(0 downto 0); -- mem_ras_n
mem_cas_n : out std_logic_vector(0 downto 0); -- mem_cas_n
mem_we_n : out std_logic_vector(0 downto 0); -- mem_we_n
mem_reset_n : out std_logic; -- mem_reset_n
mem_dq : inout std_logic_vector(31 downto 0) := (others => 'X'); -- mem_dq
mem_dqs : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs
mem_dqs_n : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs_n
mem_odt : out std_logic_vector(0 downto 0); -- mem_odt
avl_ready : out std_logic; -- waitrequest_n
avl_burstbegin : in std_logic := 'X'; -- beginbursttransfer
avl_addr : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
avl_rdata_valid : out std_logic; -- readdatavalid
avl_rdata : out std_logic_vector(127 downto 0); -- readdata
avl_wdata : in std_logic_vector(127 downto 0) := (others => 'X'); -- writedata
avl_be : in std_logic_vector(15 downto 0) := (others => 'X'); -- byteenable
avl_read_req : in std_logic := 'X'; -- read
avl_write_req : in std_logic := 'X'; -- write
avl_size : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
local_init_done : out std_logic; -- local_init_done
local_cal_success : out std_logic; -- local_cal_success
local_cal_fail : out std_logic; -- local_cal_fail
oct_rzqin : in std_logic := 'X'; -- rzqin
pll_mem_clk : out std_logic; -- pll_mem_clk
pll_write_clk : out std_logic; -- pll_write_clk
pll_write_clk_pre_phy_clk : out std_logic; -- pll_write_clk_pre_phy_clk
pll_addr_cmd_clk : out std_logic; -- pll_addr_cmd_clk
pll_locked : out std_logic; -- pll_locked
pll_avl_clk : out std_logic; -- pll_avl_clk
pll_config_clk : out std_logic; -- pll_config_clk
pll_mem_phy_clk : out std_logic; -- pll_mem_phy_clk
afi_phy_clk : out std_logic; -- afi_phy_clk
pll_avl_phy_clk : out std_logic -- pll_avl_phy_clk
);
end component ddr3ctrl1;
signal vcc: std_ulogic;
signal afi_clk, afi_half_clk, afi_reset_n: std_ulogic;
signal local_init_done, local_cal_success, local_cal_fail: std_ulogic;
signal ck_p_arr, ck_n_arr, cke_arr, cs_arr: std_logic_vector(0 downto 0);
signal rasn_arr, casn_arr, wen_arr, odt_arr: std_logic_vector(0 downto 0);
signal avlsi: ddravl_slv_in_type;
signal avlso: ddravl_slv_out_type;
begin
vcc <= '1';
mem_ck <= ck_p_arr(0);
mem_ck_n <= ck_n_arr(0);
mem_cke <= cke_arr(0);
mem_cs_n <= cs_arr(0);
mem_ras_n <= rasn_arr(0);
mem_cas_n <= casn_arr(0);
mem_we_n <= wen_arr(0);
mem_odt <= odt_arr(0);
ctrl0: ddr3ctrl1
port map (
pll_ref_clk => pll_ref_clk,
global_reset_n => global_reset_n,
soft_reset_n => vcc,
afi_clk => afi_clk,
afi_half_clk => afi_half_clk,
afi_reset_n => afi_reset_n,
afi_reset_export_n => open,
mem_a => mem_a,
mem_ba => mem_ba,
mem_ck => ck_p_arr,
mem_ck_n => ck_n_arr,
mem_cke => cke_arr,
mem_cs_n => cs_arr,
mem_dm => mem_dm,
mem_ras_n => rasn_arr,
mem_cas_n => casn_arr,
mem_we_n => wen_arr,
mem_reset_n => mem_reset_n,
mem_dq => mem_dq,
mem_dqs => mem_dqs,
mem_dqs_n => mem_dqs_n,
mem_odt => odt_arr,
avl_ready => avlso.ready,
avl_burstbegin => avlsi.burstbegin,
avl_addr => avlsi.addr(24 downto 0),
avl_rdata_valid => avlso.rdata_valid,
avl_rdata => avlso.rdata(127 downto 0),
avl_wdata => avlsi.wdata(127 downto 0),
avl_be => avlsi.be(15 downto 0),
avl_read_req => avlsi.read_req,
avl_write_req => avlsi.write_req,
avl_size => avlsi.size(2 downto 0),
local_init_done => local_init_done,
local_cal_success => local_cal_success,
local_cal_fail => local_cal_fail,
oct_rzqin => oct_rzqin,
pll_mem_clk => open,
pll_write_clk => open,
pll_write_clk_pre_phy_clk => open,
pll_addr_cmd_clk => open,
pll_locked => open,
pll_avl_clk => open,
pll_config_clk => open,
pll_mem_phy_clk => open,
afi_phy_clk => open,
pll_avl_phy_clk => open
);
avlso.rdata(avlso.rdata'high downto 128) <= (others => '0');
ahb2avl0: ahb2avl_async
generic map (
hindex => hindex,
haddr => haddr,
hmask => hmask,
burstlen => burstlen,
nosync => 0,
avldbits => 128,
avlabits => 25
)
port map (
rst_ahb => ahb_rst,
clk_ahb => ahb_clk,
ahbsi => ahbsi,
ahbso => ahbso,
rst_avl => afi_reset_n,
clk_avl => afi_clk,
avlsi => avlsi,
avlso => avlso
);
end;
| gpl-3.0 | 01e9d38143b14c78c2ce955018634788 | 0.471706 | 3.595345 | false | false | false | false |
yishinli/emc2 | src/hal/drivers/mesa-hostmot2/firmware/src/simplespix.vhd | 1 | 6,387 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
-- http://www.mesanet.com
--
-- This program is is licensed under a disjunctive dual license giving you
-- the choice of one of the two following sets of free software/open source
-- licensing terms:
--
-- * GNU General Public License (GPL), version 2.0 or later
-- * 3-clause BSD License
--
--
-- The GNU GPL License:
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
--
--
-- The 3-clause BSD License:
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- * Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- * Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- * Neither the name of Mesa Electronics nor the names of its
-- contributors may be used to endorse or promote products
-- derived from this software without specific prior written
-- permission.
--
--
-- Disclaimer:
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
entity simplespi is
generic (
buswidth : integer
);
port (
clk : in std_logic;
ibus : in std_logic_vector(buswidth-1 downto 0);
obus : out std_logic_vector(buswidth-1 downto 0);
loadbitcount : in std_logic;
loadbitrate : in std_logic;
loaddata : in std_logic;
readdata : in std_logic;
readbitcount : in std_logic;
readbitrate : in std_logic;
spiclk : out std_logic;
spiin : in std_logic;
spiout: out std_logic;
spiframe: out std_logic;
davout: out std_logic
);
end simplespi;
architecture behavioral of simplespi is
constant DivWidth: integer := 8;
-- ssi interface related signals
signal RateDivReg : std_logic_vector(DivWidth -1 downto 0);
signal RateDiv : std_logic_vector(DivWidth -1 downto 0);
signal ModeReg : std_logic_vector(8 downto 0);
alias BitcountReg : std_logic_vector(5 downto 0) is ModeReg(5 downto 0);
alias CPOL : std_logic is ModeReg(6);
alias CPHA : std_logic is ModeReg(7);
alias DontClearFrame : std_logic is ModeReg(8);
signal BitCount : std_logic_vector(5 downto 0);
signal ClockFF: std_logic;
signal SPISreg: std_logic_vector(buswidth-1 downto 0);
signal Frame: std_logic;
signal EFrame: std_logic;
signal Dav: std_logic;
signal SPIInLatch: std_logic;
signal FirstLeadingEdge: std_logic;
begin
aspiinterface: process (clk, readdata, ModeReg, ClockFF, Frame,
SPISreg, readbitcount, BitcountReg,
Dav, readbitrate, RateDivReg)
begin
if rising_edge(clk) then
if loaddata = '1' then
SPISreg <= ibus;
BitCount <= BitCountReg;
Frame <= '1';
EFrame <= '1';
Dav <= '0';
ClockFF <= '0';
FirstLeadingEdge <= '1';
RateDiv <= RateDivReg;
end if;
if Frame = '1' then
if RateDiv = 0 then
RateDiv <= RateDivReg;
SPIInLatch <= spiin;
if ClockFF = '0' then
if BitCount(5) = '1' then
Frame <= '0'; -- frame cleared 1/2 SPI clock after GO
if DontClearFrame = '0' then
EFrame <= '0';
end if;
Dav <= '1';
else
ClockFF <= '1';
end if;
if CPHA = '1' and FirstLeadingEdge = '0' then -- shift out on leading edge for CPHA = 1 case
SPISreg <= SPISreg(30 downto 0) & (SPIInLatch);
end if;
FirstLeadingEdge <= '0';
else
ClockFF <= '0';
BitCount <= BitCount -1;
if CPHA = '0' then -- shift out on trailing edge for CPHA = 0 case
SPISreg <= SPISreg(30 downto 0) & (SPIInLatch);
end if;
end if;
else
RateDiv <= RateDiv -1;
end if;
end if;
if loadbitcount = '1' then
ModeReg <= ibus(8 downto 0);
end if;
if loadbitrate = '1' then
RateDivReg <= ibus(DivWidth -1 downto 0);
end if;
end if; -- clk
obus <= (others => 'Z');
if readdata = '1' then
obus <= SPISReg;
end if;
if readbitcount = '1' then
obus(8 downto 0) <= ModeReg;
obus(buswidth -1) <= Dav;
end if;
if readbitrate = '1' then
obus(DivWidth-1 downto 0) <= RateDivReg;
end if;
spiclk <= ClockFF xor CPOL;
spiframe <= not EFrame;
davout <= Dav;
-- for i in 0 to buswidth -1 loop
-- if i = BitCountReg then
-- spiout <= SPISReg(i);
-- end if;
-- end loop;
spiout <= SPISReg(conv_integer(BitCountReg(4 downto 0))); -- select the MSB of the current size
end process aspiinterface;
end Behavioral;
| lgpl-2.1 | aab5b99a63e449462ac3949a722a4df2 | 0.65054 | 3.509341 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/srmmu/mmutw.vhd | 1 | 10,772 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: mmutw
-- File: mmutw.vhd
-- Author: Konrad Eisele, Jiri Gaisler, Gaisler Research
-- Description: MMU table-walk logic
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.mmuconfig.all;
use gaisler.mmuiface.all;
use gaisler.libmmu.all;
entity mmutw is
generic (
mmupgsz : integer range 0 to 5 := 0
);
port (
rst : in std_logic;
clk : in std_logic;
mmctrl1 : in mmctrl_type1;
twi : in mmutw_in_type;
two : out mmutw_out_type;
mcmmo : in memory_mm_out_type;
mcmmi : out memory_mm_in_type
);
end mmutw;
architecture rtl of mmutw is
type write_buffer_type is record -- write buffer
addr, data : std_logic_vector(31 downto 0);
read : std_logic;
end record;
constant write_buffer_none : write_buffer_type := (
addr => (others => '0'), data => (others => '0'), read => '0');
type states is (idle, waitm, pte, lv1, lv2, lv3, lv4);
type tw_rtype is record
state : states;
wb : write_buffer_type;
req : std_logic;
walk_op : std_logic;
end record;
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant ASYNC_RESET : boolean := GRLIB_CONFIG_ARRAY(grlib_async_reset_enable) = 1;
constant RRES : tw_rtype := (
state => idle,
wb => write_buffer_none,
req => '0',
walk_op => '0');
signal c,r : tw_rtype;
begin
p0: process (rst, r, twi, mcmmo, mmctrl1)
variable v : tw_rtype;
variable finish : std_logic;
variable index : std_logic_vector(31-2 downto 0);
variable lvl : std_logic_vector(1 downto 0);
variable fault_mexc : std_logic;
variable fault_trans : std_logic;
variable fault_inv : std_logic;
variable fault_lvl : std_logic_vector(1 downto 0);
variable pte,ptd,inv,rvd : std_logic;
variable goon, found : std_logic;
variable base : std_logic_vector(31 downto 0);
variable pagesize : integer range 0 to 3;
begin
v := r;
--#init
finish := '0';
index := (others => '0');
lvl := (others => '0');
fault_mexc := '0';
fault_trans := '0';
fault_inv := '0';
fault_lvl := (others => '0');
pte := '0';ptd := '0';inv := '0';rvd := '0';
goon := '0'; found := '0';
base := (others => '0');
base(PADDR_PTD_U downto PADDR_PTD_D) := mcmmo.data(PTD_PTP32_U downto PTD_PTP32_D);
if mcmmo.grant = '1' then
v.req := '0';
end if;
if mcmmo.retry = '1' then v.req := '1'; end if;
-- # pte/ptd
if ((mcmmo.ready and not r.req)= '1') then -- context
case mcmmo.data(PT_ET_U downto PT_ET_D) is
when ET_INV => inv := '1';
when ET_PTD => ptd := '1'; goon := '1';
when ET_PTE => pte := '1'; found := '1';
when ET_RVD => rvd := '1'; null;
when others => null;
end case;
end if;
fault_trans := (rvd);
fault_inv := inv;
pagesize := MMU_getpagesize(mmupgsz,mmctrl1);
case pagesize is
when 1 =>
-- 8k tag comparision [ 7 6 6 ]
when 2 =>
-- 16k tag comparision [ 6 6 6 ]
when 3 =>
-- 32k tag comparision [ 4 7 6 ]
when others => -- standard 4k tag comparision [ 8 6 6 ]
end case;
-- # state machine
case r.state is
when idle =>
if (twi.walk_op_ur) = '1' then
v.walk_op := '1';
index(M_CTX_SZ-1 downto 0) := mmctrl1.ctx;
base := (others => '0');
base(PADDR_PTD_U downto PADDR_PTD_D) := mmctrl1.ctxp(MMCTRL_PTP32_U downto MMCTRL_PTP32_D);
v.wb.addr := base or (index&"00");
v.wb.read := '1';
v.req := '1';
v.state := lv1;
elsif (twi.areq_ur) = '1' then
index := (others => '0');
v.wb.addr := twi.aaddr;
v.wb.data := twi.adata;
v.wb.read := '0';
v.req := '1';
v.state := waitm;
end if;
when waitm =>
if ((mcmmo.ready and not r.req)= '1') then -- amba: result ready current cycle
fault_mexc := mcmmo.mexc;
v.state := idle;
finish := '1';
end if;
when lv1 =>
if ((mcmmo.ready and not r.req)= '1') then
lvl := LVL_CTX; fault_lvl := FS_L_CTX;
case pagesize is
when 1 =>
-- 8k tag comparision [ 7 6 6 ]
index(P8K_VA_I1_SZ-1 downto 0) := twi.data(P8K_VA_I1_U downto P8K_VA_I1_D);
when 2 =>
-- 16k tag comparision [ 6 6 6 ]
index(P16K_VA_I1_SZ-1 downto 0) := twi.data(P16K_VA_I1_U downto P16K_VA_I1_D);
when 3 =>
-- 32k tag comparision [ 4 7 6 ]
index(P32K_VA_I1_SZ-1 downto 0) := twi.data(P32K_VA_I1_U downto P32K_VA_I1_D);
when others =>
-- standard 4k tag comparision [ 8 6 6 ]
index(VA_I1_SZ-1 downto 0) := twi.data(VA_I1_U downto VA_I1_D);
end case;
v.state := lv2;
end if;
when lv2 =>
if ((mcmmo.ready and not r.req)= '1') then
lvl := LVL_REGION; fault_lvl := FS_L_L1;
case pagesize is
when 1 =>
-- 8k tag comparision [ 7 6 6 ]
index(P8K_VA_I2_SZ-1 downto 0) := twi.data(P8K_VA_I2_U downto P8K_VA_I2_D);
when 2 =>
-- 16k tag comparision [ 6 6 6 ]
index(P16K_VA_I2_SZ-1 downto 0) := twi.data(P16K_VA_I2_U downto P16K_VA_I2_D);
when 3 =>
-- 32k tag comparision [ 4 7 6 ]
index(P32K_VA_I2_SZ-1 downto 0) := twi.data(P32K_VA_I2_U downto P32K_VA_I2_D);
when others =>
-- standard 4k tag comparision [ 8 6 6 ]
index(VA_I2_SZ-1 downto 0) := twi.data(VA_I2_U downto VA_I2_D);
end case;
v.state := lv3;
end if;
when lv3 =>
if ((mcmmo.ready and not r.req)= '1') then
lvl := LVL_SEGMENT; fault_lvl := FS_L_L2;
case pagesize is
when 1 =>
-- 8k tag comparision [ 7 6 6 ]
index(P8K_VA_I3_SZ-1 downto 0) := twi.data(P8K_VA_I3_U downto P8K_VA_I3_D);
when 2 =>
-- 16k tag comparision [ 6 6 6 ]
index(P16K_VA_I3_SZ-1 downto 0) := twi.data(P16K_VA_I3_U downto P16K_VA_I3_D);
when 3 =>
-- 32k tag comparision [ 4 7 6 ]
index(P32K_VA_I3_SZ-1 downto 0) := twi.data(P32K_VA_I3_U downto P32K_VA_I3_D);
when others =>
-- standard 4k tag comparision [ 8 6 6 ]
index(VA_I3_SZ-1 downto 0) := twi.data(VA_I3_U downto VA_I3_D);
end case;
v.state := lv4;
end if;
when lv4 =>
if ((mcmmo.ready and not r.req)= '1') then
lvl := LVL_PAGE; fault_lvl := FS_L_L3;
fault_trans := fault_trans or ptd;
v.state := idle;
finish := '1';
end if;
when others =>
v.state := idle;
finish := '0';
end case;
base := base or (index&"00");
if r.walk_op = '1' then
if (mcmmo.ready and (not r.req)) = '1' then
fault_mexc := mcmmo.mexc;
if (( ptd and
(not fault_mexc ) and
(not fault_trans) and
(not fault_inv )) = '1') then -- tw : break table walk?
v.wb.addr := base;
v.req := '1';
else
v.walk_op := '0';
finish := '1';
v.state := idle;
end if;
end if;
end if;
-- # reset
if (not ASYNC_RESET) and (not RESET_ALL) and ( rst = '0' ) then
v.state := RRES.state;
v.req := RRES.req;
v.walk_op := RRES.walk_op;
v.wb.read := RRES.wb.read;
end if;
--# drive signals
two.finish <= finish;
two.data <= mcmmo.data;
two.addr <= r.wb.addr(31 downto 0);
two.lvl <= lvl;
two.fault_mexc <= fault_mexc;
two.fault_trans <= fault_trans;
two.fault_inv <= fault_inv;
two.fault_lvl <= fault_lvl;
mcmmi.address <= r.wb.addr;
mcmmi.data <= r.wb.data;
mcmmi.burst <= '0';
mcmmi.size <= "10";
mcmmi.read <= r.wb.read;
mcmmi.lock <= '0';
mcmmi.req <= r.req;
c <= v;
end process p0;
syncrregs : if not ASYNC_RESET generate
p1: process (clk)
begin
if rising_edge(clk) then
r <= c;
if RESET_ALL and (rst = '0') then
r <= RRES;
end if;
end if;
end process p1;
end generate;
asyncrregs : if ASYNC_RESET generate
p1: process (clk, rst)
begin
if rst = '0' then
r <= RRES;
elsif rising_edge(clk) then
r <= c;
end if;
end process p1;
end generate;
end rtl;
| gpl-3.0 | dd1d92e787aaaf5a786416d098030694 | 0.482083 | 3.500812 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-xilinx-ml403/config.vhd | 1 | 6,702 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := virtex4;
constant CFG_MEMTECH : integer := virtex4;
constant CFG_PADTECH : integer := virtex4;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := virtex4;
constant CFG_CLKMUL : integer := (13);
constant CFG_CLKDIV : integer := (20);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 0 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 0;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (1);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 1;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 1;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0 + 1*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 0;
constant CFG_ITLBNUM : integer := 2;
constant CFG_DTLBNUM : integer := 2;
constant CFG_TLB_TYPE : integer := 1 + 0*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2 + 64*0;
constant CFG_ATBSZ : integer := 2;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_STAT_ENABLE : integer := 0;
constant CFG_STAT_CNT : integer := 1;
constant CFG_STAT_NMAX : integer := 0;
constant CFG_STAT_DSUEN : integer := 0;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
constant CFG_ALTWIN : integer := 0;
constant CFG_REX : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 0;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 0 + 0 + 0;
constant CFG_ETH_BUF : integer := 1;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000009#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- DDR controller
constant CFG_DDRSP : integer := 1;
constant CFG_DDRSP_INIT : integer := 1;
constant CFG_DDRSP_FREQ : integer := (100);
constant CFG_DDRSP_COL : integer := (9);
constant CFG_DDRSP_SIZE : integer := (64);
constant CFG_DDRSP_RSKEW : integer := (0);
-- SSRAM controller
constant CFG_SSCTRL : integer := 0;
constant CFG_SSCTRLP16 : integer := 0;
-- AHB status register
constant CFG_AHBSTAT : integer := 1;
constant CFG_AHBSTATN : integer := (1);
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 0;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 8;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0FFFE#;
constant CFG_GRGPIO_WIDTH : integer := (14);
-- I2C master
constant CFG_I2C_ENABLE : integer := 1;
-- VGA and PS2/ interface
constant CFG_KBD_ENABLE : integer := 0;
constant CFG_VGA_ENABLE : integer := 0;
constant CFG_SVGA_ENABLE : integer := 0;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-3.0 | 7abf5271d20420801a785ad5323d551a | 0.644733 | 3.603226 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/techmap/maps/outpad_ddr.vhd | 1 | 3,810 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: outpad_ddr, outpad_ddrv
-- File: outpad_ddr.vhd
-- Author: Jan Andersson - Aeroflex Gaisler
-- Description: Wrapper that instantiates a DDR register connected to an
-- output pad. The generic tech wrappers are not used for nextreme
-- since this technology requires that the output enable signal is
-- connected between the DDR register and the pad.
------------------------------------------------------------------------------
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allddr.all;
use techmap.allpads.all;
entity outpad_ddr is
generic (
tech : integer := 0;
level : integer := 0;
slew : integer := 0;
voltage : integer := x33v;
strength : integer := 12
);
port (
pad : out std_ulogic;
i1, i2 : in std_ulogic;
c1, c2 : in std_ulogic;
ce : in std_ulogic;
r : in std_ulogic;
s : in std_ulogic
);
end;
architecture rtl of outpad_ddr is
signal q, oe, vcc : std_ulogic;
begin
vcc <= '1';
def: if (tech /= easic90) and (tech /= easic45) generate
ddrreg : ddr_oreg generic map (tech)
port map (q, c1, c2, ce, i1, i2, r, s);
p : outpad generic map (tech, level, slew, voltage, strength)
port map (pad, q);
oe <= '0';
end generate def;
nex : if (tech = easic90) generate
ddrreg : nextreme_oddr_reg
port map (ck => c1, dh => i1, dl => i2, doe => vcc, q => q, oe => oe, rstb => r);
p : nextreme_toutpad generic map (level, slew, voltage, strength)
port map(pad, q, oe);
end generate;
n2x : if (tech = easic45) generate
-- ddrpad : n2x_outpad_ddr generic map (level, slew, voltage, strength)
-- port map ();
--pragma translate_off
assert false report "outpad_ddr: Not yet supported on Nextreme2"
severity failure;
--pragma translate_on
q <= '0'; oe <= '0';
end generate;
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity outpad_ddrv is
generic (
tech : integer := 0;
level : integer := 0;
slew : integer := 0;
voltage : integer := 0;
strength : integer := 12;
width : integer := 1
);
port (
pad : out std_logic_vector(width-1 downto 0);
i1, i2 : in std_logic_vector(width-1 downto 0);
c1, c2 : in std_ulogic;
ce : in std_ulogic;
r : in std_ulogic;
s : in std_ulogic
);
end;
architecture rtl of outpad_ddrv is
begin
v : for j in width-1 downto 0 generate
x0 : outpad_ddr generic map (tech, level, slew, voltage, strength)
port map (pad(j), i1(j), i2(j), c1, c2, ce, r, s);
end generate;
end;
| gpl-3.0 | a7fbf868b2086335bf9c4a0544a0ebee | 0.594751 | 3.632031 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/spi/spi2ahbx.vhd | 1 | 17,429 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: spi2ahbx
-- File: spi2ahbx.vhd
-- Author: Jan Andersson - Aeroflex Gaisler AB
-- Contact: [email protected]
-- Description: Simple SPI slave providing a bridge to AMBA AHB
-- This entity is typically wrapped with spi2ahb or spi2ahb_apb.
-------------------------------------------------------------------------------
--
-- Short core documentation, for additional information see the GRLIB IP
-- Library User's Manual (GRIP):
--
-- The core functions as a SPI memory device. To write to the core, issue the
-- following SPI bus sequence:
--
-- 0. Assert chip select
-- 1. Write instruction
-- 2. Send 32-bit address
-- 3. Send data to be written
-- 4. Deassert chip select
--
-- The core will expect 32-bits of data and write these as a word. This can be
-- changed by writing to the core's control register. See documentation further
-- down. If less than HSIZE bytes are transferred the core will drop the data.
-- After HSIZE bytes has been transferred the core will perform the write to
-- memory. If another byte is received before the core has written its data
-- then the core will discard the current and any following bytes. This
-- condition can be detected by checking the MALFUNCTION bit in the core's
-- status register.
--
-- To read to the core, issue the following SPI bus sequence:
--
-- 0. Assert chip select
-- 1. Send read instruction
-- 2. Send 32-bit address to be used
-- 3. Send dummy byte (depending on read instruction used)
-- 4. Read bytes
-- 5. Deassert chip select
--
-- The core will perform 32-bit data accesses to fill its internal buffer. This
-- can be changed by writing to the core's control register (see documentation
-- further down). If the buffer is empty when the core should return the first
-- byte then the core will return invalid data. This condition can be later
-- detected by checking the MALFUNCTION bit in the core's status register.
-- When the core initiates additional data fetches can be configured via the
-- RAHEAD bit in the control/status register.
--
-- The cores control/status register is read via the RDSR instruction and
-- written via the WRSR instruction.
--
-- +--------+-----------------------------------------------------------------+
-- | Bit(s) | Description |
-- +--------+-----------------------------------------------------------------+
-- | 7 | Reserved, always zero (RO) |
-- | 6 | RAHEAD: Read ahead. When this bit is set the core will make a |
-- | | new access to fetch data as soon as the last current data bit |
-- | | has been moved. Otherwise the core will not attempt the new |
-- | | access until the 'change' transition on SCK. See GRIP doc. for |
-- | | details. Default value is '1'. (RW) |
-- | 5 | PROT: Memory protection triggered. Last access was outside |
-- | | range. Updated after each AMBA access (RO) |
-- | 4 | MEXC: Memory exception. Gets set if core receives AMBA ERROR |
-- | | response. Updated after each AMBA access. (RO) |
-- | 3 | DMAACT: Core is currently performing DMA (RO) |
-- | 2 | MALFUNCTION: Set to 1 if DMA is not finished when new byte |
-- | | starts getting shifted |
-- | 1:0 | HSIZE: Controls the access size core will use for AMBA accesses |
-- | | Default is HSIZE = WORD. HSIZE 11 is illegal (RW) |
-- +--------+-----------------------------------------------------------------+
--
-- Documentation of generics:
--
-- [hindex] AHB master index
--
-- [oepol] Output enable polarity
--
-- [filter] Length of filter used on SCK
--
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.spi.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.all;
entity spi2ahbx is
generic (
-- AHB configuration
hindex : integer := 0;
oepol : integer range 0 to 1 := 0;
filter : integer range 2 to 512 := 2;
cpol : integer range 0 to 1 := 0;
cpha : integer range 0 to 1 := 0
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- AHB master interface
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
-- SPI signals
spii : in spi_in_type;
spio : out spi_out_type;
--
spi2ahbi : in spi2ahb_in_type;
spi2ahbo : out spi2ahb_out_type
);
end entity spi2ahbx;
architecture rtl of spi2ahbx is
-----------------------------------------------------------------------------
-- Constants
-----------------------------------------------------------------------------
constant OE : std_ulogic := conv_std_logic(oepol = 1);
constant HIZ : std_ulogic := not OE;
-----------------------------------------------------------------------------
-- Instructions
-----------------------------------------------------------------------------
constant RDSR_INST : std_logic_vector(7 downto 0) := X"05";
constant WRSR_INST : std_logic_vector(7 downto 0) := X"01";
constant READ_INST : std_logic_vector(7 downto 0) := X"03";
constant READD_INST : std_logic_vector(7 downto 0) := X"0B"; -- with dummy
constant WRITE_INST : std_logic_vector(7 downto 0) := X"02";
-----------------------------------------------------------------------------
-- Types
-----------------------------------------------------------------------------
type state_type is (decode, rdsr, wrsr, addr, dummy, rd, wr, idle, malfunction);
type spi2ahb_reg_type is record
state : state_type;
--
haddr : std_logic_vector(31 downto 0);
hdata : std_logic_vector(31 downto 0);
hsize : std_logic_vector(1 downto 0);
hwrite : std_ulogic;
--
rahead : std_ulogic;
mexc : std_ulogic;
dodma : std_ulogic;
prot : std_ulogic;
malf : std_ulogic;
--
brec : std_ulogic;
rec : std_ulogic;
dummy : std_ulogic;
cnt : std_logic_vector(2 downto 0);
bcnt : std_logic_vector(1 downto 0);
sreg : std_logic_vector(7 downto 0);
miso : std_ulogic;
rdop : std_logic_vector(1 downto 0);
--
misooen : std_ulogic;
sel : std_logic_vector(1 downto 0);
psck : std_ulogic;
sck : std_logic_vector(filter downto 0);
mosi : std_logic_vector(1 downto 0);
end record;
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
signal ami : ahb_dma_in_type;
signal amo : ahb_dma_out_type;
signal r, rin : spi2ahb_reg_type;
begin
-- Generic AHB master interface
ahbmst0 : ahbmst
generic map (hindex => hindex, hirq => 0, venid => VENDOR_GAISLER,
devid => GAISLER_SPI2AHB, version => 0,
chprot => 3, incaddr => 0)
port map (rstn, clk, ami, amo, ahbi, ahbo);
comb: process (r, rstn, spii, amo, spi2ahbi)
variable v : spi2ahb_reg_type;
variable hrdata : std_logic_vector(31 downto 0);
variable ahbreq : std_ulogic;
variable lb : std_ulogic;
variable sample : std_ulogic;
variable change : std_ulogic;
begin
v := r; ahbreq := '0'; lb := '0'; hrdata := (others => '0');
sample := '0'; change := '0'; v.brec := '0';
---------------------------------------------------------------------------
-- Sync input signals
---------------------------------------------------------------------------
v.sel := r.sel(0) & spii.spisel;
v.sck := r.sck(filter-1 downto 0) & spii.sck;
v.mosi := r.mosi(0) & spii.mosi;
---------------------------------------------------------------------------
-- DMA control
---------------------------------------------------------------------------
if r.dodma = '1' then
if amo.active = '1' then
if amo.ready = '1' then
hrdata := ahbreadword(amo.rdata);
case r.hsize is
when "00" =>
v.haddr := r.haddr + 1;
for i in 1 to 3 loop
if i = conv_integer(r.haddr(1 downto 0)) then
hrdata(31 downto 24) := hrdata(31-8*i downto 24-8*i);
end if;
end loop;
when "01" =>
v.haddr := r.haddr + 2;
if r.haddr(1) = '1' then
hrdata(31 downto 16) := hrdata(15 downto 0);
end if;
when others =>
v.haddr := r.haddr + 4;
end case;
v.sreg := hrdata(31 downto 24);
v.hdata(31 downto 8) := hrdata(23 downto 0);
v.mexc := '0';
v.dodma := '0';
end if;
if amo.mexc = '1' then
v.mexc := '1';
v.dodma := '0';
end if;
else
ahbreq := '1';
end if;
end if;
---------------------------------------------------------------------------
-- SPI communication
---------------------------------------------------------------------------
if andv(r.sck(filter downto 1)) = '1' then v.psck := '1'; end if;
if orv(r.sck(filter downto 1)) = '0' then v.psck := '0'; end if;
if (r.psck xor v.psck) = '1' then
if r.psck = conv_std_logic(cpol = 1) then
sample := not conv_std_logic(cpha = 1);
change := conv_std_logic(cpha = 1);
else
sample := conv_std_logic(cpha = 1);
change := not conv_std_logic(cpha = 1);
end if;
end if;
if sample = '1' then
v.cnt := r.cnt + 1;
if r.cnt = "111" then
v.cnt := (others => '0');
v.brec := '1';
end if;
if r.state /= dummy then
v.sreg := r.sreg(6 downto 0) & r.mosi(1);
end if;
end if;
if change = '1' then
v.miso := r.sreg(7);
end if;
---------------------------------------------------------------------------
-- SPI slave control FSM
---------------------------------------------------------------------------
if ((r.hsize = "00") or ((r.hsize(0) and r.bcnt(0)) = '1') or
(r.bcnt = "11")) then
lb := '1';
end if;
case r.state is
when decode =>
if r.brec = '1' then
case r.sreg is
when RDSR_INST =>
v.state := rdsr;
v.sreg := '0' & r.rahead & r.prot & r.mexc &
r.dodma & r.malf & r.hsize;
when WRSR_INST => v.state := wrsr;
when READ_INST | READD_INST=>
v.state := addr; v.rec := '0';
v.dummy := r.sreg(3);
when WRITE_INST => v.state := addr; v.rec := '1';
when others => null;
end case;
end if;
when rdsr =>
if r.brec = '1' then
v.sreg := '0' & r.rahead & r.prot & r.mexc &
r.dodma & r.malf & r.hsize;
end if;
when wrsr =>
if r.brec = '1' then
v.rahead := r.sreg(6);
v.hsize := r.sreg(1 downto 0);
end if;
when addr =>
-- First we need a 4 byte address, then we handle data.
if r.brec = '1' then
if r.dodma = '1' then
v.state := malfunction;
else
v.haddr := r.haddr(23 downto 0) & r.sreg;
end if;
v.bcnt := r.bcnt + 1;
if r.bcnt = "11" then
if r.rec = '1' then
v.state := wr;
else
if r.dummy = '1' then
v.state := dummy;
else
v.state := rd;
end if;
v.malf := '0';
v.dodma := '1';
v.hwrite := '0';
end if;
end if;
end if;
when dummy =>
if r.brec = '1' then
v.state := rd;
end if;
when rd =>
if r.brec = '1' then
v.bcnt := r.bcnt + 1;
v.hdata(31 downto 8) := r.hdata(23 downto 0);
v.sreg := r.hdata(31 downto 24);
if (lb and r.rahead) = '1' then
v.dodma := '1';
v.bcnt := "00";
end if;
v.rdop(0) := lb and not r.rahead;
end if;
if (change and v.dodma) = '1' then
v.state := malfunction;
end if;
-- Without readahead
if orv(r.rdop) = '1' then
if (sample and v.dodma) = '1' then
-- Case is a little tricky. Master may have sampled bad
-- data but we detect the DMA operation as completed.
v.state := malfunction;
end if;
if (r.rdop(0) and change) = '1' then
v.dodma := '1';
v.rdop := "10";
end if;
if (r.dodma and not v.dodma) = '1' then
v.miso := hrdata(31);
v.rdop := (others => '0');
end if;
end if;
when wr =>
if r.brec = '1' then
v.bcnt := r.bcnt + 1;
if v.dodma = '0' then
if r.bcnt = "00" then v.hdata(31 downto 24) := r.sreg; end if;
if r.bcnt(1) = '0' then v.hdata(23 downto 16) := r.sreg; end if;
if r.bcnt(0) = '0' then v.hdata(15 downto 8) := r.sreg; end if;
v.hdata(7 downto 0) := r.sreg;
if lb = '1' then v.dodma := '1'; v.hwrite := '1'; v.malf := '0'; end if;
else
v.state := malfunction;
end if;
end if;
when idle =>
if r.sel(1) = '0' then
v.state := decode;
v.misooen := OE;
v.cnt := (others => '0');
v.bcnt := (others => '0');
end if;
when malfunction =>
v.malf := '1';
end case;
if r.state /= rd then v.rdop := (others => '0'); end if;
if spi2ahbi.hmask /= zero32 then
if v.dodma = '1' then
if ((spi2ahbi.haddr xor r.haddr) and spi2ahbi.hmask) /= zero32 then
v.dodma := '0';
v.prot := '1';
v.state := idle;
else
v.prot := '0';
end if;
end if;
else
v.prot := '0';
end if;
if spi2ahbi.en = '1' then
if r.sel(1) = '1' then
v.state := idle;
v.misooen := HIZ;
end if;
else
v.state := idle;
v.misooen := HIZ;
end if;
----------------------------------------------------------------------------
-- Reset
----------------------------------------------------------------------------
if rstn = '0' then
v.state := idle;
v.haddr := (others => '0');
v.hdata := (others => '0');
v.hsize := HSIZE_WORD(1 downto 0);
v.rahead := '1';
v.mexc := '0';
v.dodma := '0';
v.prot := '0';
v.malf := '0';
v.psck := conv_std_logic(cpol = 1);
v.miso := '1';
v.misooen := HIZ;
end if;
if spi2ahbi.hmask = zero32 then v.prot := '0'; end if;
----------------------------------------------------------------------------
-- Signal assignments
----------------------------------------------------------------------------
-- Core registers
rin <= v;
-- AHB master control
ami.address <= r.haddr;
ami.wdata <= ahbdrivedata(r.hdata);
ami.start <= ahbreq;
ami.burst <= '0';
ami.write <= r.hwrite;
ami.busy <= '0';
ami.irq <= '0';
ami.size <= '0' & r.hsize;
-- Update outputs
spi2ahbo.dma <= r.dodma;
spi2ahbo.wr <= r.hwrite;
spi2ahbo.prot <= r.prot;
-- Several unused here..
spio.miso <= r.miso;
spio.misooen <= r.misooen;
spio.mosi <= '0';
spio.mosioen <= HIZ;
spio.sck <= '0';
spio.sckoen <= HIZ;
spio.ssn <= (others => '0');
spio.enable <= spi2ahbi.en;
spio.astart <= '0';
end process comb;
reg: process (clk)
begin
if rising_edge(clk) then r <= rin; end if;
end process reg;
-- Boot message
-- pragma translate_off
bootmsg : report_version
generic map ("spi2ahb" & tost(hindex) & ": SPI to AHB bridge");
-- pragma translate_on
end architecture rtl;
| gpl-3.0 | 1741272e3013e8a3ae379ff3b4b26bba | 0.465661 | 3.952154 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/gr1553b/simtrans1553.vhd | 1 | 3,737 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: simtrans1553
-- File: simtrans1553.vhd
-- Author: Magnus Hjorth - Aeroflex Gaisler
-- Description: 1553 Transceiver simulation model
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.gr1553b_pkg.all;
entity simtrans1553_single is
generic (
txdelay: time := 200 ns;
rxdelay: time := 450 ns
);
port (
buswire: inout wire1553;
rxen: in std_logic;
txin: in std_logic;
txP: in std_logic;
txN: in std_logic;
rxP: out std_logic;
rxN: out std_logic
);
end;
architecture b of simtrans1553_single is
signal bw_rxd, bw_txd: wire1553;
begin
bw_rxd <= transport buswire after rxdelay;
buswire <= bw_txd after txdelay;
rxpr: process(bw_rxd,rxen)
variable p,n: std_ulogic;
begin
p:='U'; n:='U';
case rxen is
when '0' => p:='0'; n:='0';
when '1' =>
case bw_rxd is
when 'U' => null;
when 'X' => p := 'X'; n := 'X';
when '0' => p := '0'; n := '0';
when '+' => p := '1'; n := '0';
when '-' => p := '0'; n := '1';
end case;
when 'X' => p:='X'; n:='X';
when others => null;
end case;
rxP <= p;
rxN <= n;
end process;
txpr: process(txin, txP, txN)
variable w: wire1553;
begin
w := 'U';
if txin='1' or (txP='0' and txN='0') or (txP='1' and txN='1') then
w := '0';
elsif txin='0' and txP='1' and txN='0' then
w := '+';
elsif txin='0' and txP='0' and txN='1' then
w := '-';
elsif txin='X' or txP='X' or txN='X' then
w := 'X';
elsif txin='U' or (txP='U' and txN='U') then
w := 'U';
else
w := 'X';
end if;
bw_txd <= w;
end process;
end;
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.gr1553b_pkg.all;
entity simtrans1553 is
generic (
txdelay: time := 200 ns;
rxdelay: time := 450 ns
);
port (
busA: inout wire1553;
busB: inout wire1553;
rxenA: in std_logic;
txinA: in std_logic;
txAP: in std_logic;
txAN: in std_logic;
rxAP: out std_logic;
rxAN: out std_logic;
rxenB: in std_logic;
txinB: in std_logic;
txBP: in std_logic;
txBN: in std_logic;
rxBP: out std_logic;
rxBN: out std_logic
);
end;
architecture s of simtrans1553 is
begin
at: simtrans1553_single
generic map (txdelay,rxdelay)
port map (busA,rxenA,txinA,txAP,txAN,rxAP,rxAN);
bt: simtrans1553_single
generic map (txdelay,rxdelay)
port map (busB,rxenB,txinB,txBP,txBN,rxBP,rxBN);
end;
| gpl-3.0 | 6ac6c4ef1788c79b67f83cf8d41b2220 | 0.563018 | 3.422161 | false | false | false | false |
pwsoft/fpga_examples | rtl/general/gen_dualram.vhd | 1 | 2,549 | -- -----------------------------------------------------------------------
--
-- Syntiac's generic VHDL support files.
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2009 by Peter Wendrich ([email protected])
-- http://www.syntiac.com/fpga64.html
--
-- This source file is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- -----------------------------------------------------------------------
--
-- gen_dualram.vhd
--
-- -----------------------------------------------------------------------
--
-- Full dual port ram: Two read/write ports
--
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
-- -----------------------------------------------------------------------
entity gen_dualram is
generic (
dWidth : integer := 8;
aWidth : integer := 10
);
port (
clk : in std_logic;
wePortA : in std_logic;
aPortA : in unsigned((aWidth-1) downto 0);
dPortA : in unsigned((dWidth-1) downto 0);
qPortA : out unsigned((dWidth-1) downto 0);
wePortB : in std_logic;
aPortB : in unsigned((aWidth-1) downto 0);
dPortB : in unsigned((dWidth-1) downto 0);
qPortB : out unsigned((dWidth-1) downto 0)
);
end entity;
-- -----------------------------------------------------------------------
architecture rtl of gen_dualram is
subtype addressRange is integer range 0 to ((2**aWidth)-1);
type ramDef is array(addressRange) of unsigned((dWidth-1) downto 0);
signal ram: ramDef;
begin
-- PORT A
process(clk)
begin
if rising_edge(clk) then
if wePortA = '1' then
ram(to_integer(aPortA)) <= dPortA;
end if;
qPortA <= ram(to_integer(aPortA));
end if;
end process;
-- PORT B
process(clk)
begin
if rising_edge(clk) then
if wePortB = '1' then
ram(to_integer(aPortB)) <= dPortB;
end if;
qPortB <= ram(to_integer(aPortB));
end if;
end process;
end architecture;
| lgpl-2.1 | f3838a3a2c999c6cf9df5de1320f9b47 | 0.549627 | 3.821589 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/srmmu/mmuconfig.vhd | 1 | 22,453 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: mmuconfig
-- File: mmuconfig.vhd
-- Author: Konrad Eisele, Jiri Gaisler, Gaisler Research
-- Description: MMU types and constants
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library gaisler;
package mmuconfig is
constant M_CTX_SZ : integer := 8;
constant M_ENT_MAX : integer := 64;
constant XM_ENT_MAX_LOG : integer := log2(M_ENT_MAX);
constant M_ENT_MAX_LOG : integer := XM_ENT_MAX_LOG;
type mmu_idcache is (id_icache, id_dcache);
-- ##############################################################
-- 1.0 virtual address [sparc V8: p.243,Appx.H,Figure H-4]
-- +--------+--------+--------+---------------+
-- a) | INDEX1 | INDEX2 | INDEX3 | OFFSET |
-- +--------+--------+--------+---------------+
-- 31 24 23 18 17 12 11 0
constant VA_I1_SZ : integer := 8;
constant VA_I2_SZ : integer := 6;
constant VA_I3_SZ : integer := 6;
constant VA_I_SZ : integer := VA_I1_SZ+VA_I2_SZ+VA_I3_SZ;
constant VA_I_MAX : integer := 8;
constant VA_I1_U : integer := 31;
constant VA_I1_D : integer := 32-VA_I1_SZ;
constant VA_I2_U : integer := 31-VA_I1_SZ;
constant VA_I2_D : integer := 32-VA_I1_SZ-VA_I2_SZ;
constant VA_I3_U : integer := 31-VA_I1_SZ-VA_I2_SZ;
constant VA_I3_D : integer := 32-VA_I_SZ;
constant VA_I_U : integer := 31;
constant VA_I_D : integer := 32-VA_I_SZ;
constant VA_OFF_U : integer := 31-VA_I_SZ;
constant VA_OFF_D : integer := 0;
constant VA_OFFCTX_U : integer := 31;
constant VA_OFFCTX_D : integer := 0;
constant VA_OFFREG_U : integer := 31-VA_I1_SZ;
constant VA_OFFREG_D : integer := 0;
constant VA_OFFSEG_U : integer := 31-VA_I1_SZ-VA_I2_SZ;
constant VA_OFFSEG_D : integer := 0;
constant VA_OFFPAG_U : integer := 31-VA_I_SZ;
constant VA_OFFPAG_D : integer := 0;
-- 8k pages
-- 7 6 6 13
-- +--------+--------+--------+---------------+
-- a) | INDEX1 | INDEX2 | INDEX3 | OFFSET |
-- +--------+--------+--------+---------------+
-- 31 25 24 19 18 13 12 0
constant P8K_VA_I1_SZ : integer := 7;
constant P8K_VA_I2_SZ : integer := 6;
constant P8K_VA_I3_SZ : integer := 6;
constant P8K_VA_I_SZ : integer := P8K_VA_I1_SZ+P8K_VA_I2_SZ+P8K_VA_I3_SZ;
constant P8K_VA_I_MAX : integer := 7;
constant P8K_VA_I1_U : integer := 31;
constant P8K_VA_I1_D : integer := 32-P8K_VA_I1_SZ;
constant P8K_VA_I2_U : integer := 31-P8K_VA_I1_SZ;
constant P8K_VA_I2_D : integer := 32-P8K_VA_I1_SZ-P8K_VA_I2_SZ;
constant P8K_VA_I3_U : integer := 31-P8K_VA_I1_SZ-P8K_VA_I2_SZ;
constant P8K_VA_I3_D : integer := 32-P8K_VA_I_SZ;
constant P8K_VA_I_U : integer := 31;
constant P8K_VA_I_D : integer := 32-P8K_VA_I_SZ;
constant P8K_VA_OFF_U : integer := 31-P8K_VA_I_SZ;
constant P8K_VA_OFF_D : integer := 0;
constant P8K_VA_OFFCTX_U : integer := 31;
constant P8K_VA_OFFCTX_D : integer := 0;
constant P8K_VA_OFFREG_U : integer := 31-P8K_VA_I1_SZ;
constant P8K_VA_OFFREG_D : integer := 0;
constant P8K_VA_OFFSEG_U : integer := 31-P8K_VA_I1_SZ-P8K_VA_I2_SZ;
constant P8K_VA_OFFSEG_D : integer := 0;
constant P8K_VA_OFFPAG_U : integer := 31-P8K_VA_I_SZ;
constant P8K_VA_OFFPAG_D : integer := 0;
-- 16k pages
-- 6 6 6 14
-- +--------+--------+--------+---------------+
-- a) | INDEX1 | INDEX2 | INDEX3 | OFFSET |
-- +--------+--------+--------+---------------+
-- 31 26 25 20 19 14 13 0
constant P16K_VA_I1_SZ : integer := 6;
constant P16K_VA_I2_SZ : integer := 6;
constant P16K_VA_I3_SZ : integer := 6;
constant P16K_VA_I_SZ : integer := P16K_VA_I1_SZ+P16K_VA_I2_SZ+P16K_VA_I3_SZ;
constant P16K_VA_I_MAX : integer := 6;
constant P16K_VA_I1_U : integer := 31;
constant P16K_VA_I1_D : integer := 32-P16K_VA_I1_SZ;
constant P16K_VA_I2_U : integer := 31-P16K_VA_I1_SZ;
constant P16K_VA_I2_D : integer := 32-P16K_VA_I1_SZ-P16K_VA_I2_SZ;
constant P16K_VA_I3_U : integer := 31-P16K_VA_I1_SZ-P16K_VA_I2_SZ;
constant P16K_VA_I3_D : integer := 32-P16K_VA_I_SZ;
constant P16K_VA_I_U : integer := 31;
constant P16K_VA_I_D : integer := 32-P16K_VA_I_SZ;
constant P16K_VA_OFF_U : integer := 31-P16K_VA_I_SZ;
constant P16K_VA_OFF_D : integer := 0;
constant P16K_VA_OFFCTX_U : integer := 31;
constant P16K_VA_OFFCTX_D : integer := 0;
constant P16K_VA_OFFREG_U : integer := 31-P16K_VA_I1_SZ;
constant P16K_VA_OFFREG_D : integer := 0;
constant P16K_VA_OFFSEG_U : integer := 31-P16K_VA_I1_SZ-P16K_VA_I2_SZ;
constant P16K_VA_OFFSEG_D : integer := 0;
constant P16K_VA_OFFPAG_U : integer := 31-P16K_VA_I_SZ;
constant P16K_VA_OFFPAG_D : integer := 0;
-- 32k pages
-- 4 7 6 15
-- +--------+--------+--------+---------------+
-- a) | INDEX1 | INDEX2 | INDEX3 | OFFSET |
-- +--------+--------+--------+---------------+
-- 31 28 27 21 20 15 14 0
constant P32K_VA_I1_SZ : integer := 4;
constant P32K_VA_I2_SZ : integer := 7;
constant P32K_VA_I3_SZ : integer := 6;
constant P32K_VA_I_SZ : integer := P32K_VA_I1_SZ+P32K_VA_I2_SZ+P32K_VA_I3_SZ;
constant P32K_VA_I_MAX : integer := 7;
constant P32K_VA_I1_U : integer := 31;
constant P32K_VA_I1_D : integer := 32-P32K_VA_I1_SZ;
constant P32K_VA_I2_U : integer := 31-P32K_VA_I1_SZ;
constant P32K_VA_I2_D : integer := 32-P32K_VA_I1_SZ-P32K_VA_I2_SZ;
constant P32K_VA_I3_U : integer := 31-P32K_VA_I1_SZ-P32K_VA_I2_SZ;
constant P32K_VA_I3_D : integer := 32-P32K_VA_I_SZ;
constant P32K_VA_I_U : integer := 31;
constant P32K_VA_I_D : integer := 32-P32K_VA_I_SZ;
constant P32K_VA_OFF_U : integer := 31-P32K_VA_I_SZ;
constant P32K_VA_OFF_D : integer := 0;
constant P32K_VA_OFFCTX_U : integer := 31;
constant P32K_VA_OFFCTX_D : integer := 0;
constant P32K_VA_OFFREG_U : integer := 31-P32K_VA_I1_SZ;
constant P32K_VA_OFFREG_D : integer := 0;
constant P32K_VA_OFFSEG_U : integer := 31-P32K_VA_I1_SZ-P32K_VA_I2_SZ;
constant P32K_VA_OFFSEG_D : integer := 0;
constant P32K_VA_OFFPAG_U : integer := 31-P32K_VA_I_SZ;
constant P32K_VA_OFFPAG_D : integer := 0;
-- ##############################################################
-- 2.0 PAGE TABE DESCRIPTOR (PTD) [sparc V8: p.247,Appx.H,Figure H-7]
--
-- +-------------------------------------------------+---+---+
-- | Page Table Pointer (PTP) | 0 | 0 |
-- +-------------------------------------------------+---+---+
-- 31 2 1 0
--
-- 2.1 PAGE TABE ENTRY (PTE) [sparc V8: p.247,Appx.H,Figure H-8]
--
-- +-----------------------------+---+---+---+-----------+---+
-- |Physical Page Number (PPN) | C | M | R | ACC | ET|
-- +-----------------------------+---+---+---+-----------+---+
-- 31 8 7 6 5 4 2 1 0
--
constant PTD_PTP_U : integer := 31; -- PTD: page table pointer
constant PTD_PTP_D : integer := 2;
constant PTD_PTP32_U : integer := 27; -- PTD: page table pointer 32 bit
constant PTD_PTP32_D : integer := 2;
constant PTE_PPN_U : integer := 31; -- PTE: physical page number
constant PTE_PPN_D : integer := 8;
constant PTE_PPN_S : integer := (PTE_PPN_U+1)-PTE_PPN_D; -- PTE: pysical page number size
constant PTE_PPN32_U : integer := 27; -- PTE: physical page number 32 bit addr
constant PTE_PPN32_D : integer := 8;
constant PTE_PPN32_S : integer := (PTE_PPN32_U+1)-PTE_PPN32_D; -- PTE: pysical page number 32 bit size
constant PTE_PPN32REG_U : integer := PTE_PPN32_U; -- PTE: pte part of merged result address
constant PTE_PPN32REG_D : integer := PTE_PPN32_U+1-VA_I1_SZ;
constant PTE_PPN32SEG_U : integer := PTE_PPN32_U;
constant PTE_PPN32SEG_D : integer := PTE_PPN32_U+1-VA_I1_SZ-VA_I2_SZ;
constant PTE_PPN32PAG_U : integer := PTE_PPN32_U;
constant PTE_PPN32PAG_D : integer := PTE_PPN32_U+1-VA_I_SZ;
-- 8k pages
constant P8K_PTE_PPN32REG_U : integer := PTE_PPN32_U; -- PTE: pte part of merged result address
constant P8K_PTE_PPN32REG_D : integer := PTE_PPN32_U+1-P8K_VA_I1_SZ;
constant P8K_PTE_PPN32SEG_U : integer := PTE_PPN32_U;
constant P8K_PTE_PPN32SEG_D : integer := PTE_PPN32_U+1-P8K_VA_I1_SZ-P8K_VA_I2_SZ;
constant P8K_PTE_PPN32PAG_U : integer := PTE_PPN32_U;
constant P8K_PTE_PPN32PAG_D : integer := PTE_PPN32_U+1-P8K_VA_I_SZ;
-- 16k pages
constant P16K_PTE_PPN32REG_U : integer := PTE_PPN32_U; -- PTE: pte part of merged result address
constant P16K_PTE_PPN32REG_D : integer := PTE_PPN32_U+1-P16K_VA_I1_SZ;
constant P16K_PTE_PPN32SEG_U : integer := PTE_PPN32_U;
constant P16K_PTE_PPN32SEG_D : integer := PTE_PPN32_U+1-P16K_VA_I1_SZ-P16K_VA_I2_SZ;
constant P16K_PTE_PPN32PAG_U : integer := PTE_PPN32_U;
constant P16K_PTE_PPN32PAG_D : integer := PTE_PPN32_U+1-P16K_VA_I_SZ;
-- 32k pages
constant P32K_PTE_PPN32REG_U : integer := PTE_PPN32_U; -- PTE: pte part of merged result address
constant P32K_PTE_PPN32REG_D : integer := PTE_PPN32_U+1-P32K_VA_I1_SZ;
constant P32K_PTE_PPN32SEG_U : integer := PTE_PPN32_U;
constant P32K_PTE_PPN32SEG_D : integer := PTE_PPN32_U+1-P32K_VA_I1_SZ-P32K_VA_I2_SZ;
constant P32K_PTE_PPN32PAG_U : integer := PTE_PPN32_U;
constant P32K_PTE_PPN32PAG_D : integer := PTE_PPN32_U+1-P32K_VA_I_SZ;
constant PTE_C : integer := 7; -- PTE: Cacheable bit
constant PTE_M : integer := 6; -- PTE: Modified bit
constant PTE_R : integer := 5; -- PTE: Reference Bit - a "1" indicates an PTE
constant PTE_ACC_U : integer := 4; -- PTE: Access field
constant PTE_ACC_D : integer := 2;
constant ACC_W : integer := 2; -- PTE::ACC : write permission
constant ACC_E : integer := 3; -- PTE::ACC : exec permission
constant ACC_SU : integer := 4; -- PTE::ACC : privileged
constant PT_ET_U : integer := 1; -- PTD/PTE: PTE Type
constant PT_ET_D : integer := 0;
constant ET_INV : std_logic_vector(1 downto 0) := "00";
constant ET_PTD : std_logic_vector(1 downto 0) := "01";
constant ET_PTE : std_logic_vector(1 downto 0) := "10";
constant ET_RVD : std_logic_vector(1 downto 0) := "11";
constant PADDR_PTD_U : integer := 31;
constant PADDR_PTD_D : integer := 6;
-- ##############################################################
-- 3.0 TLBCAM TAG hardware representation (TTG)
--
type tlbcam_reg is record
ET : std_logic_vector(1 downto 0); -- et field
ACC : std_logic_vector(2 downto 0); -- on flush/probe this will become FPTY
M : std_logic; -- modified
R : std_logic; -- referenced
SU : std_logic; -- equal ACC >= 6
VALID : std_logic;
LVL : std_logic_vector(1 downto 0); -- level in pth
I1 : std_logic_vector(7 downto 0); -- vaddr
I2 : std_logic_vector(5 downto 0);
I3 : std_logic_vector(5 downto 0);
CTX : std_logic_vector(M_CTX_SZ-1 downto 0); -- ctx number
PPN : std_logic_vector(PTE_PPN_S-1 downto 0); -- physical page number
C : std_logic; -- cachable
end record;
constant tlbcam_reg_none : tlbcam_reg := ("00", "000", '0', '0', '0', '0',
"00", "00000000", "000000", "000000", "00000000", (others => '0'), '0');
-- tlbcam_reg::LVL
constant LVL_PAGE : std_logic_vector(1 downto 0) := "00"; -- equal tlbcam_tfp::TYP FPTY_PAGE
constant LVL_SEGMENT : std_logic_vector(1 downto 0) := "01"; -- equal tlbcam_tfp::TYP FPTY_SEGMENT
constant LVL_REGION : std_logic_vector(1 downto 0) := "10"; -- equal tlbcam_tfp::TYP FPTY_REGION
constant LVL_CTX : std_logic_vector(1 downto 0) := "11"; -- equal tlbcam_tfp::TYP FPTY_CTX
-- ##############################################################
-- 4.0 TLBCAM tag i/o for translation/flush/(probe)
--
type tlbcam_tfp is record
TYP : std_logic_vector(2 downto 0); -- f/(p) type
I1 : std_logic_vector(7 downto 0); -- vaddr
I2 : std_logic_vector(5 downto 0);
I3 : std_logic_vector(5 downto 0);
CTX : std_logic_vector(M_CTX_SZ-1 downto 0); -- ctx number
M : std_logic;
end record;
constant tlbcam_tfp_none : tlbcam_tfp := ("000", "00000000", "000000", "000000", "00000000", '0');
--tlbcam_tfp::TYP
constant FPTY_PAGE : std_logic_vector(2 downto 0) := "000"; -- level 3 PTE match I1+I2+I3
constant FPTY_SEGMENT : std_logic_vector(2 downto 0) := "001"; -- level 2/3 PTE/PTD match I1+I2
constant FPTY_REGION : std_logic_vector(2 downto 0) := "010"; -- level 1/2/3 PTE/PTD match I1
constant FPTY_CTX : std_logic_vector(2 downto 0) := "011"; -- level 0/1/2/3 PTE/PTD ctx
constant FPTY_N : std_logic_vector(2 downto 0) := "100"; -- entire tlb
-- ##############################################################
-- 5.0 MMU Control Register [sparc V8: p.253,Appx.H,Figure H-10]
--
-- +-------+-----+------------------+-----+-------+--+--+
-- | IMPL | VER | SC | PSO | resvd |NF|E |
-- +-------+-----+------------------+-----+-------+--+--+
-- 31 28 27 24 23 8 7 6 2 1 0
--
-- MMU Context Pointer [sparc V8: p.254,Appx.H,Figure H-11]
-- +-------------------------------------------+--------+
-- | Context Table Pointer | resvd |
-- +-------------------------------------------+--------+
-- 31 2 1 0
--
-- MMU Context Number [sparc V8: p.255,Appx.H,Figure H-12]
-- +----------------------------------------------------+
-- | Context Table Pointer |
-- +----------------------------------------------------+
-- 31 0
--
-- fault status/address register [sparc V8: p.256,Appx.H,Table H-13/14]
-- +------------+-----+---+----+----+-----+----+
-- | reserved | EBE | L | AT | FT | FAV | OW |
-- +------------+-----+---+----+----+-----+----+
-- 31 18 17 10 9 8 7 5 4 2 1 0
--
-- +----------------------------------------------------+
-- | fault address register |
-- +----------------------------------------------------+
-- 31 0
constant MMCTRL_CTXP_SZ : integer := 30;
constant MMCTRL_PTP32_U : integer := 25;
constant MMCTRL_PTP32_D : integer := 0;
constant MMCTRL_E : integer := 0;
constant MMCTRL_NF : integer := 1;
constant MMCTRL_PSO : integer := 7;
constant MMCTRL_SC_U : integer := 23;
constant MMCTRL_SC_D : integer := 8;
constant MMCTRL_PGSZ_U : integer := 17;
constant MMCTRL_PGSZ_D : integer := 16;
constant MMCTRL_VER_U : integer := 27;
constant MMCTRL_VER_D : integer := 24;
constant MMCTRL_IMPL_U : integer := 31;
constant MMCTRL_IMPL_D : integer := 28;
constant MMCTRL_TLBDIS : integer := 15;
constant MMCTRL_TLBSEP : integer := 14;
constant MMCTXP_U : integer := 31;
constant MMCTXP_D : integer := 2;
constant MMCTXNR_U : integer := M_CTX_SZ-1;
constant MMCTXNR_D : integer := 0;
constant FS_SZ : integer := 18; -- fault status size
constant FS_EBE_U : integer := 17;
constant FS_EBE_D : integer := 10;
constant FS_L_U : integer := 9;
constant FS_L_D : integer := 8;
constant FS_L_CTX : std_logic_vector(1 downto 0) := "00";
constant FS_L_L1 : std_logic_vector(1 downto 0) := "01";
constant FS_L_L2 : std_logic_vector(1 downto 0) := "10";
constant FS_L_L3 : std_logic_vector(1 downto 0) := "11";
constant FS_AT_U : integer := 7;
constant FS_AT_D : integer := 5;
constant FS_AT_LS : natural := 7; --L=0 S=1
constant FS_AT_ID : natural := 6; --D=0 I=1
constant FS_AT_SU : natural := 5; --U=0 SU=1
constant FS_AT_LUDS : std_logic_vector(2 downto 0) := "000";
constant FS_AT_LSDS : std_logic_vector(2 downto 0) := "001";
constant FS_AT_LUIS : std_logic_vector(2 downto 0) := "010";
constant FS_AT_LSIS : std_logic_vector(2 downto 0) := "011";
constant FS_AT_SUDS : std_logic_vector(2 downto 0) := "100";
constant FS_AT_SSDS : std_logic_vector(2 downto 0) := "101";
constant FS_AT_SUIS : std_logic_vector(2 downto 0) := "110";
constant FS_AT_SSIS : std_logic_vector(2 downto 0) := "111";
constant FS_FT_U : integer := 4;
constant FS_FT_D : integer := 2;
constant FS_FT_NONE : std_logic_vector(2 downto 0) := "000";
constant FS_FT_INV : std_logic_vector(2 downto 0) := "001";
constant FS_FT_PRO : std_logic_vector(2 downto 0) := "010";
constant FS_FT_PRI : std_logic_vector(2 downto 0) := "011";
constant FS_FT_TRANS : std_logic_vector(2 downto 0):= "100";
constant FS_FT_BUS : std_logic_vector(2 downto 0) := "101";
constant FS_FT_INT : std_logic_vector(2 downto 0) := "110";
constant FS_FT_RVD : std_logic_vector(2 downto 0) := "111";
constant FS_FAV : natural := 1;
constant FS_OW : natural := 0;
--# mmu ctrl reg
type mmctrl_type1 is record
e : std_logic; -- enable
nf : std_logic; -- no fault
pso : std_logic; -- partial store order
-- pre : std_logic; -- pretranslation source
-- pri : std_logic; -- i/d priority
pagesize : std_logic_vector(1 downto 0);-- page size
ctx : std_logic_vector(M_CTX_SZ-1 downto 0);-- context nr
ctxp : std_logic_vector(MMCTRL_CTXP_SZ-1 downto 0); -- context table pointer
tlbdis : std_logic; -- tlb disabled
bar : std_logic_vector(1 downto 0); -- preplace barrier
end record;
constant mmctrl_type1_none : mmctrl_type1 := ('0', '0', '0', (others => '0'), (others => '0'), (others => '0'), '0', (others => '0'));
--# fault status reg
type mmctrl_fs_type is record
ow : std_logic;
fav : std_logic;
ft : std_logic_vector(2 downto 0); -- fault type
at_ls : std_logic; -- access type, load/store
at_id : std_logic; -- access type, i/dcache
at_su : std_logic; -- access type, su/user
l : std_logic_vector(1 downto 0); -- level
ebe : std_logic_vector(7 downto 0);
end record;
constant mmctrl_fs_zero : mmctrl_fs_type :=
('0', '0', "000", '0', '0', '0', "00", "00000000");
type mmctrl_type2 is record
fs : mmctrl_fs_type;
valid : std_logic;
fa : std_logic_vector(VA_I_SZ-1 downto 0); -- fault address register
end record;
constant mmctrl2_zero : mmctrl_type2 :=
(mmctrl_fs_zero, '0', zero32(VA_I_SZ-1 downto 0));
-- ##############################################################
-- 6. Virtual Flush/Probe address [sparc V8: p.249,Appx.H,Figure H-9]
-- +---------------------------------------+--------+-------+
-- | VIRTUAL FLUSH&Probe Address (VFPA) | type | rvd |
-- +---------------------------------------+--------+-------+
-- 31 12 11 8 7 0
--
--
subtype FPA is natural range 31 downto 12;
constant FPA_I1_U : integer := 31;
constant FPA_I1_D : integer := 24;
constant FPA_I2_U : integer := 23;
constant FPA_I2_D : integer := 18;
constant FPA_I3_U : integer := 17;
constant FPA_I3_D : integer := 12;
constant FPTY_U : integer := 10; -- only 3 bits
constant FPTY_D : integer := 8;
-- ##############################################################
-- 7. control register virtual address [sparc V8: p.253,Appx.H,Table H-5]
-- +---------------------------------+-----+--------+
-- | | CNR | rsvd |
-- +---------------------------------+-----+--------+
-- 31 10 8 7 0
constant CNR_U : integer := 10;
constant CNR_D : integer := 8;
constant CNR_CTRL : std_logic_vector(2 downto 0) := "000";
constant CNR_CTXP : std_logic_vector(2 downto 0) := "001";
constant CNR_CTX : std_logic_vector(2 downto 0) := "010";
constant CNR_F : std_logic_vector(2 downto 0) := "011";
constant CNR_FADDR : std_logic_vector(2 downto 0) := "100";
-- ##############################################################
-- 8. Precise flush (ASI 0x10-14) [sparc V8: p.266,Appx.I]
-- supported: ASI_FLUSH_PAGE
-- ASI_FLUSH_CTX
constant PFLUSH_PAGE : std_logic := '0';
constant PFLUSH_CTX : std_logic := '1';
-- ##############################################################
-- 9. Diagnostic access
--
constant DIAGF_LVL_U : integer := 1;
constant DIAGF_LVL_D : integer := 0;
constant DIAGF_WR : integer := 3;
constant DIAGF_HIT : integer := 4;
constant DIAGF_CTX_U : integer := 12;
constant DIAGF_CTX_D : integer := 5;
constant DIAGF_VALID : integer := 13;
end mmuconfig;
| gpl-3.0 | 95584b8da72b045ebc8ca0b5ff47741d | 0.522959 | 3.059826 | false | false | false | false |
pwsoft/fpga_examples | rtl/ttl/ttl_latency.vhd | 1 | 2,299 | -- -----------------------------------------------------------------------
--
-- Syntiac VHDL support files.
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2018 by Peter Wendrich ([email protected])
-- http://www.syntiac.com
--
-- This source file is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- -----------------------------------------------------------------------
--
-- Implements a propagation delay emulation based on a (fast) emulation clock.
-- Recommended value for the clk cycle time is in the order of 5 to 7 ns.
-- About the propagation delay of one 7400 NAND gate.
--
-- This allows certain clock glitches to be emulated.
-- It prevents building impossible fast circuits.
--
-- Also as a bonus it turns everything into registered logic with at least
-- one flipflop on each emulated output allowing easier mapping to FPGAs.
--
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use work.ttl_pkg.ttl_t;
-- -----------------------------------------------------------------------
entity ttl_latency is
generic (
latency : integer := 1
);
port (
clk : in std_logic;
d : in ttl_t;
q : out ttl_t
);
end entity;
architecture rtl of ttl_latency is
type pipeline_t is array(0 to latency) of ttl_t;
signal pipeline : pipeline_t := (others => FLOAT);
begin
q <= pipeline(latency);
pipeline_gen : if latency > 0 generate
process(clk, d)
begin
pipeline(0) <= d;
if rising_edge(clk) then
for i in 1 to latency loop
pipeline(i) <= pipeline(i-1);
end loop;
end if;
end process;
end generate;
end architecture;
| lgpl-2.1 | ad805debb751d22e898690e8c37bd1d8 | 0.598086 | 4.098039 | false | false | false | false |
yishinli/emc2 | src/hal/drivers/mesa-hostmot2/firmware/src/kubstepgeny.vhd | 1 | 12,581 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
-- http://www.mesanet.com
--
-- This program is is licensed under a disjunctive dual license giving you
-- the choice of one of the two following sets of free software/open source
-- licensing terms:
--
-- * GNU General Public License (GPL), version 2.0 or later
-- * 3-clause BSD License
--
--
-- The GNU GPL License:
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
--
--
-- The 3-clause BSD License:
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- * Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- * Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- * Neither the name of Mesa Electronics nor the names of its
-- contributors may be used to endorse or promote products
-- derived from this software without specific prior written
-- permission.
--
--
-- Disclaimer:
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
entity stepgen is
generic (
buswidth : integer;
timersize : integer;
tablewidth : integer;
asize : integer;
rsize : integer
);
Port ( clk : in std_logic;
ibus : in std_logic_vector(buswidth-1 downto 0);
obus : out std_logic_vector(buswidth-1 downto 0);
loadsteprate : in std_logic;
loadaccum : in std_logic;
loadstepmode : in std_logic;
loaddirsetuptime : in std_logic;
loaddirholdtime : in std_logic;
loadpulseactivetime : in std_logic;
loadpulseidletime : in std_logic;
loadtable : in std_logic;
loadtablemax : in std_logic;
readsteprate : in std_logic;
readaccum : in std_logic;
readstepmode : in std_logic;
readdirsetuptime : in std_logic;
readdirholdtime : in std_logic;
readpulseactivetime : in std_logic;
readpulseidletime : in std_logic;
readtable : in std_logic;
readtablemax : in std_logic;
basicrate : in std_logic;
hold : in std_logic;
stout : out std_logic_vector(tablewidth-1 downto 0)
);
end stepgen;
architecture Behavioral of stepgen is
-- Step Generator related signals
signal stepaccum: std_logic_vector(asize-1 downto 0);
signal nextaccum: std_logic_vector(asize-1 downto 0);
alias stepmsbs: std_logic_vector(1 downto 0) is stepaccum(rsize-1 downto rsize -2);
alias stepmsb: std_logic is stepaccum(rsize -1);
alias nextmsb: std_logic is nextaccum(rsize -1);
signal dstepmsb : std_logic;
signal ddshold : std_logic;
signal steprate: std_logic_vector(rsize -1 downto 0);
alias stepdir: std_logic is steprate(rsize -1);
signal dstepdir : std_logic;
signal stepdirout : std_logic;
signal pulsewait : std_logic;
signal steppulse : std_logic := '0';
signal dpulsewait : std_logic := '0';
signal dirsetupwait : std_logic;
signal dirholdwait : std_logic;
signal ddirholdwait : std_logic;
signal dirshwait : std_logic;
signal dirhold : std_logic;
signal dirshcount: std_logic_vector(timersize-1 downto 0);
signal pulsewidthcount: std_logic_vector(timersize-1 downto 0);
signal dirsetuptime: std_logic_vector(timersize -1 downto 0);
signal dirholdtime: std_logic_vector(timersize -1 downto 0);
signal pulseactivetime: std_logic_vector(timersize -1 downto 0);
signal pulseidletime: std_logic_vector(timersize -1 downto 0);
signal stepmode: std_logic_vector(1 downto 0);
signal localout: std_logic_vector(tablewidth-1 downto 0);
signal wewouldcount : std_logic;
signal dirchange : std_logic;
signal waitforhold : std_logic;
signal waitforpulse : std_logic;
signal tableptr: std_logic_vector(3 downto 0);
signal tablemax: std_logic_vector(3 downto 0);
signal tabledata: std_logic_vector(tablewidth-1 downto 0);
component SRL16E
--
generic (INIT : bit_vector);
--
port (D : in std_logic;
CE : in std_logic;
CLK : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
Q : out std_logic);
end component;
begin
steptable: for i in 0 to tablewidth -1 generate
asr16e: SRL16E generic map (x"0000") port map(
D => ibus(i),
CE => loadtable,
CLK => clk,
A0 => tableptr(0),
A1 => tableptr(1),
A2 => tableptr(2),
A3 => tableptr(3),
Q => tabledata(i)
);
end generate;
astepgen: process (clk,stepdirout, steprate, nextaccum, stepaccum,
dirholdwait, ddirholdwait, pulsewait, dpulsewait,
dirsetupwait, pulsewidthcount, dirshcount, dirhold,
readaccum, tabledata, stepmode, steppulse, stepmsbs)
begin
if rising_edge(clk) then
if basicrate = '1' and hold = '0' and ddshold = '0' then -- our basic step rate DDS
stepaccum <= nextaccum;
dstepdir <= stepdir; -- only updated when we add
end if;
if pulsewait = '1' then -- our two timers
pulsewidthcount <= pulsewidthcount -1; -- we share dirshcount between setup and hold functions
end if;
if (pulsewait = '0') and (dpulsewait = '1') and (steppulse = '1') then
pulsewidthcount <= pulseidletime; -- output pulse idle time
steppulse <= '0'; -- clear our output pulse
end if;
if dirshwait = '1' then
dirshcount <= dirshcount -1;
end if;
if (stepmsb = '0' and dstepmsb = '1' and dstepdir = '0') -- we counted up
or (stepmsb = '1' and dstepmsb = '0' and dstepdir = '1') then -- we counted down -- the output of the DDS
pulsewidthcount <= pulseactivetime; -- output pulse active time
steppulse <= '1';
dirshcount <= dirholdtime; -- set pulse to dir change hold timer
dirhold <= '1'; -- set our flag to indicate
else
if dirholdwait = '0' then -- no change during hold time
if stepdirout /= stepdir then -- we changed the external direction signal
dirshcount <= dirsetuptime; -- set dir change to next pulse setup time
dirhold <= '0'; -- set our flag to indicate
stepdirout <= stepdir;
end if; -- our timer is for setup time
end if;
end if; -- our timer is for hold time
if (stepmsb = '0' and dstepmsb = '1' and dstepdir = '0') then -- we counted up
if (tableptr = tablemax) then
tableptr <= x"0";
else
tableptr <= tableptr +1;
end if;
end if;
if (stepmsb = '1' and dstepmsb = '0' and dstepdir = '1') then -- we counted down
if (tableptr = x"0") then
tableptr <= tablemax;
else
tableptr <= tableptr -1;
end if;
end if;
if loadstepmode = '1' then -- our register writes
stepmode <= ibus(1 downto 0);
end if;
if loadsteprate = '1' then
steprate <= ibus(rsize -1 downto 0);
end if;
if loadaccum = '1' then
stepaccum(asize -1 downto asize-buswidth) <= ibus;
steppulse <= '0';
end if;
if loaddirsetuptime = '1' then
dirsetuptime <= ibus(timersize -1 downto 0);
end if;
if loaddirholdtime = '1' then
dirholdtime <= ibus(timersize -1 downto 0);
end if;
if loadpulseactivetime = '1' then
pulseactivetime <= ibus(timersize -1 downto 0);
end if;
if loadpulseidletime = '1' then
pulseidletime <= ibus(timersize -1 downto 0);
end if;
if loadtablemax = '1' then
tablemax <= ibus(3 downto 0);
tableptr <= x"0";
end if;
dpulsewait <= pulsewait;
dstepmsb <= stepmsb;
ddirholdwait <= dirholdwait; -- ddirholdwait needed to cover case where dirhold wait has become 0
end if; -- clk -- but setup timer has not started yet (Probably more elegant to use state machine)
dirchange <= stepdirout xor stepdir;
if (stepmsb = '1' and nextmsb = '0' and stepdir = '0') -- we would count up
or (stepmsb = '0' and nextmsb = '1' and stepdir = '1') then -- we would count down
wewouldcount <= '1';
else
wewouldcount <= '0';
end if;
-- wewouldcount <= nextmsb xor stepmsb;
waitforhold <= (dirholdwait or ddirholdwait) and dirchange;
waitforpulse <= pulsewait or dpulsewait;
nextaccum <= signed(stepaccum)+ signed(steprate); -- to lookahead
if (wewouldcount = '1') and
(((waitforhold = '1') or (dirsetupwait = '1') or (waitforpulse = '1')))
then -- need to pause
ddshold <= '1';
else
ddshold <= '0';
end if;
if pulsewidthcount = 0 then
pulsewait <= '0';
else
pulsewait <= '1';
end if;
if dirshcount = 0 then
dirshwait <= '0';
else
dirshwait <= '1';
end if;
dirholdwait <= (dirhold and dirshwait);
dirsetupwait <= (not dirhold) and dirshwait;
obus <= (others => 'Z');
-- if readsteprate = '1' then
-- obus(rsize -1 downto 0) <= steprate;
-- end if;
if readaccum = '1' then
obus <= stepaccum(asize -1 downto asize-buswidth);
end if;
-- if readstepmode = '1' then -- register readbacks commented out for size
-- obus(3 downto 0) <= stepmode;
-- obus(31 downto 4) <= (others => '0');
-- end if;
-- if readdirsetuptime = '1' then
-- obus(timersize -1 downto 0) <= dirsetuptime;
-- obus(31 downto timersize) <= (others => '0');
-- end if;
-- if readdirholdtime = '1' then
-- obus(timersize -1 downto 0) <= dirholdtime;
-- obus(31 downto timersize) <= (others => '0');
-- end if;
-- if readpulseactivetime = '1' then
-- obus(timersize -1 downto 0) <= pulsewidth;
-- obus(31 downto timersize) <= (others => '0');
-- end if;
-- if readpulseidletime = '1' then
-- obus(timersize -1 downto 0) <= pulseidle;
-- obus(31 downto timersize) <= (others => '0');
-- end if;
localout <= tabledata; -- this is the default unless:
case stepmode is
when "00" =>
localout(0) <= steppulse; -- step
localOut(1) <= stepdirout; -- dir
when "01" =>
localout(0) <= steppulse and (not stepdirout); -- count up
localOut(1) <= steppulse and stepdirout; -- count down
when "10" =>
case stepmsbs is
when "00" => localout(1 downto 0) <= "00"; -- quadrature
when "01" => localout(1 downto 0) <= "01";
when "10" => localout (1 downto 0)<= "11";
when "11" => localout(1 downto 0) <= "10";
when others => null;
end case;
when others => null;
end case;
stout <= localout;
end process astepgen;
end Behavioral;
| lgpl-2.1 | 85e3198848d667c5e3c1429365e7abe5 | 0.626023 | 3.275449 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/greth/greths.vhd | 1 | 9,284 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: greths
-- File: greths.vhd
-- Authors: Andrea Gianarro
-- Description: Gigabit Ethernet Media Access Controller with Ethernet Debug
-- Communication Link and Serial GMII interface
------------------------------------------------------------------------------
library ieee;
library grlib;
library gaisler;
use ieee.std_logic_1164.all;
use grlib.stdlib.all;
use grlib.amba.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use gaisler.net.all;
use gaisler.ethernet_mac.all;
library eth;
use eth.ethcomp.all;
entity greths is
generic(
hindex : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#FFF#;
pirq : integer := 0;
fabtech : integer := 0;
memtech : integer := 0;
transtech : integer := 0;
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
slot_time : integer := 128;
mdcscaler : integer range 0 to 255 := 25;
enable_mdio : integer range 0 to 1 := 0;
fifosize : integer range 4 to 64 := 8;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 3 := 0;
edclbufsz : integer range 1 to 64 := 1;
burstlength : integer range 4 to 128 := 32;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0035#;
phyrstadr : integer range 0 to 32 := 0;
rmii : integer range 0 to 1 := 0;
sim : integer range 0 to 1 := 0;
giga : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0;
scanen : integer range 0 to 1 := 0;
ft : integer range 0 to 2 := 0;
edclft : integer range 0 to 2 := 0;
mdint_pol : integer range 0 to 1 := 0;
enable_mdint : integer range 0 to 1 := 0;
multicast : integer range 0 to 1 := 0;
ramdebug : integer range 0 to 2 := 0;
mdiohold : integer := 1;
maxsize : integer := 1500;
pcs_phyaddr : integer range 0 to 32 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
-- High-speed Serial Interface
clk_125 : in std_logic;
rst_125 : in std_logic;
eth_rx_p : in std_logic;
eth_rx_n : in std_logic := '0';
eth_tx_p : out std_logic;
eth_tx_n : out std_logic;
-- MDIO interface
reset : out std_logic;
mdio_o : out std_logic;
mdio_oe : out std_logic;
mdio_i : in std_logic;
mdc : out std_logic;
mdint : in std_logic;
-- Control signals
phyrstaddr : in std_logic_vector(4 downto 0);
edcladdr : in std_logic_vector(3 downto 0);
edclsepahb : in std_logic;
edcldisable : in std_logic;
debug_pcs_mdio : in std_logic := '0';
-- added for igloo2_serdes
apbin : in apb_in_serdes := apb_in_serdes_none;
apbout : out apb_out_serdes;
m2gl_padin : in pad_in_serdes := pad_in_serdes_none;
m2gl_padout : out pad_out_serdes;
serdes_clk125 : out std_logic;
rx_aligned : out std_logic
);
end entity;
architecture rtl of greths is
-- GMII and MII signals between MAC and PCS
signal mac_ethi : eth_in_type;
signal pcs_ethi : eth_in_type;
signal mac_etho : eth_out_type;
signal pcs_etho : eth_out_type;
signal int_tx_rstn : std_logic;
signal int_rx_rstn : std_logic;
-- MDIO signals
signal mdio_o_pcs : std_logic;
signal mdio_oe_pcs : std_logic;
signal mdio_i_pcs : std_logic;
begin
-------------------------------------------------------------------------------
-- Ethernet MAC
-------------------------------------------------------------------------------
u0 : grethm
generic map (
hindex => hindex,
pindex => pindex,
paddr => paddr,
pmask => pmask,
pirq => pirq,
memtech => memtech,
ifg_gap => ifg_gap,
attempt_limit => attempt_limit,
backoff_limit => backoff_limit,
slot_time => slot_time,
mdcscaler => mdcscaler,
enable_mdio => enable_mdio,
fifosize => fifosize,
nsync => nsync,
edcl => edcl,
edclbufsz => edclbufsz,
burstlength => burstlength,
macaddrh => macaddrh,
macaddrl => macaddrl,
ipaddrh => ipaddrh,
ipaddrl => ipaddrl,
phyrstadr => phyrstadr,
rmii => rmii,
sim => sim,
giga => giga,
oepol => oepol,
scanen => scanen,
ft => ft,
edclft => edclft,
mdint_pol => mdint_pol,
enable_mdint => enable_mdint,
multicast => multicast,
ramdebug => ramdebug,
mdiohold => mdiohold,
maxsize => maxsize,
gmiimode => 1
)
port map (
rst => rst,
clk => clk,
ahbmi => ahbmi,
ahbmo => ahbmo,
apbi => apbi,
apbo => apbo,
ethi => mac_ethi,
etho => mac_etho
);
-------------------------------------------------------------------------------
-- 1000baseX-compliant SGMII bridge
-------------------------------------------------------------------------------
sgmii0: sgmii
generic map (
fabtech => fabtech,
memtech => memtech,
transtech => transtech,
phy_addr => pcs_phyaddr
)
port map(
clk_125 => clk_125,
rst_125 => rst_125,
ser_rx_p => eth_rx_p,
ser_rx_n => eth_rx_n,
ser_tx_p => eth_tx_p,
ser_tx_n => eth_tx_n,
txd => pcs_etho.txd,
tx_en => pcs_etho.tx_en,
tx_er => pcs_etho.tx_er,
tx_clk => pcs_ethi.gtx_clk,
tx_rstn => int_tx_rstn,
rxd => pcs_ethi.rxd,
rx_dv => pcs_ethi.rx_dv,
rx_er => pcs_ethi.rx_er,
rx_col => pcs_ethi.rx_col,
rx_crs => pcs_ethi.rx_crs,
rx_clk => pcs_ethi.rx_clk,
rx_rstn => int_rx_rstn,
-- optional MDIO interface to PCS
mdc => pcs_etho.mdc,
mdio_o => mdio_o_pcs,
mdio_oe => mdio_oe_pcs,
mdio_i => mdio_i_pcs,
-- added for igloo2_serdes
apbin => apbin,
apbout => apbout,
m2gl_padin => m2gl_padin,
m2gl_padout => m2gl_padout,
serdes_clk125 => serdes_clk125,
rx_aligned => rx_aligned
);
-- 10/100 Mbit GMII to MII adapter
adapt_10_100_0 : gmii_to_mii
port map (
tx_rstn => int_tx_rstn,
rx_rstn => int_rx_rstn,
gmiii => mac_ethi, -- OUT
gmiio => mac_etho, -- IN
miii => pcs_ethi, -- IN
miio => pcs_etho -- OUT
);
-- Drive MDIO signals (including PCS bypass to MAC)
reset <= pcs_etho.reset;
mdc <= pcs_etho.mdc;
mdio_oe <= '1' when debug_pcs_mdio = '1' else pcs_etho.mdio_oe;
mdio_o <= '0' when debug_pcs_mdio = '1' else pcs_etho.mdio_o;
mdio_oe_pcs <= pcs_etho.mdio_oe when debug_pcs_mdio = '1' else '1';
mdio_o_pcs <= pcs_etho.mdio_o when debug_pcs_mdio = '1' else '0';
pcs_ethi.mdint <= mdint;
pcs_ethi.mdio_i <= mdio_i_pcs when debug_pcs_mdio = '1' else mdio_i;
-- MAC input signals integration
pcs_ethi.tx_clk <= pcs_ethi.gtx_clk;
pcs_ethi.phyrstaddr <= phyrstaddr;
pcs_ethi.edcladdr <= edcladdr;
pcs_ethi.edclsepahb <= edclsepahb;
pcs_ethi.edcldisable <= edcldisable;
end architecture;
| gpl-3.0 | 05469243f2be9d99714b0eaf3a6da610 | 0.495368 | 3.836364 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/greth/adapters/comma_detect.vhd | 1 | 5,183 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: comma_detect
-- File: comma_detect.vhd
-- Author: Andrea Gianarro - Aeroflex Gaisler AB
-- Description: SGMII' comma detector with bitslip output signal
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.stdlib.all;
use grlib.devices.all;
use grlib.amba.all;
library techmap;
use techmap.gencomp.all;
entity comma_detect is
generic (
bsbreak : integer range 0 to 31 := 0; -- number of extra deassertion cycles between bitslip assertions in a sequence
bswait : integer range 0 to 127 := 7 -- number of cycles to pause recognition after a sequence is issued
);
port (
clk : in std_logic;
rstn : in std_logic;
indata : in std_logic_vector(9 downto 0);
bitslip : out std_logic
);
end entity;
architecture arch of comma_detect is
type fsm_state_type is (idle, bitslip1, bitslip2, bitslip3);
type reg_type is record
data : std_logic_vector(19 downto 0);
state : fsm_state_type;
slipcnt : integer range 0 to 15;
slipbreak : integer range 0 to 31;
slipwait : integer range 0 to 127;
end record;
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant RES : reg_type := (
data => (others => '0'),
state => idle,
slipcnt => 0,
slipbreak => 0,
slipwait => 0
);
signal r, rin : reg_type;
begin
comb : process( rstn, r, indata )
variable v : reg_type;
--variable vbitslip : std_logic_vector(15 downto 0);
begin
v := r;
v.data(19 downto 10) := r.data(9 downto 0);
v.data(9 downto 0) := indata;
-- -- we match pattern comma+, present in +K.28.x
-- for i in 19 downto 10 loop
-- if r.data(i downto i-6) = "0011111" then
-- vbitslip(9-(i-10)) := '1'; -- unary representation of number of bitslips
-- exit;
-- end if;
-- end loop ;
-- v.slipcnt := unary_to_slv(vbitslip);
case r.state is
when idle =>
-- we match pattern comma+, present in +K.28.x
if r.data(18 downto 12) = "0011111" then
v.slipcnt := 9;
elsif r.data(17 downto 11) = "0011111" then
v.slipcnt := 8;
elsif r.data(16 downto 10) = "0011111" then
v.slipcnt := 7;
elsif r.data(15 downto 9) = "0011111" then
v.slipcnt := 6;
elsif r.data(14 downto 8) = "0011111" then
v.slipcnt := 5;
elsif r.data(13 downto 7) = "0011111" then
v.slipcnt := 4;
elsif r.data(12 downto 6) = "0011111" then
v.slipcnt := 3;
elsif r.data(11 downto 5) = "0011111" then
v.slipcnt := 2;
elsif r.data(10 downto 4) = "0011111" then
v.slipcnt := 1;
else
v.slipcnt := 0;
end if;
if v.slipcnt /= 0 then
v.state := bitslip1;
end if;
when bitslip1 =>
v.slipcnt := r.slipcnt - 1;
v.state := bitslip2;
v.slipbreak := 0;
when bitslip2 =>
if r.slipcnt /= 0 then
if r.slipbreak = bsbreak then
v.state := bitslip1;
else
v.slipbreak := r.slipbreak + 1;
end if;
else
v.slipwait := 0;
v.state := bitslip3;
end if;
when bitslip3 =>
if r.slipwait = bswait then
v.state := idle;
v.data := (others => '0');
else
v.slipwait := r.slipwait + 1;
end if;
when others =>
end case ;
if (not RESET_ALL) and (rstn = '0') then
v.data := (others => '0');
v.state := idle;
end if;
rin <= v;
if r.state = bitslip1 then
bitslip <= '1';
else
bitslip <= '0';
end if;
end process ;
reg : process(clk)
begin
if rising_edge(clk) then
r <= rin;
if RESET_ALL and rstn = '0' then
r <= RES;
end if;
end if;
end process;
end architecture ;
| gpl-3.0 | 4fe0640046b641cd030eb092b5e3c0e4 | 0.558364 | 3.72342 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-digilent-nexys4ddr/testbench.vhd | 1 | 8,835 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
use work.debug.all;
use work.config.all;
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
USE_MIG_INTERFACE_MODEL : boolean := false;
clkperiod : integer := 10 -- system clock period
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sdramfile : string := "ram.srec"; -- sdram contents
constant lresp : boolean := false;
constant ct : integer := clkperiod/2;
constant CFG_DDR2SP_DATAWIDTH : integer := 16;
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal rstn : std_logic;
signal error : std_logic;
-- PROM flash
signal address : std_logic_vector(26 downto 0):=(others =>'0');
signal data : std_logic_vector(31 downto 0);
signal RamCE : std_logic;
signal oen : std_ulogic;
signal writen : std_ulogic;
-- Debug support unit
signal dsubre : std_ulogic;
-- AHB Uart
signal dsurx : std_ulogic;
signal dsutx : std_ulogic;
-- APB Uart
signal urxd : std_ulogic;
signal utxd : std_ulogic;
-- Ethernet signals
signal erx_er : std_ulogic;
signal erx_crs : std_ulogic;
signal etxdt : std_logic_vector(1 downto 0);
-- SVGA signals
signal vid_hsync : std_ulogic;
signal vid_vsync : std_ulogic;
signal vid_r : std_logic_vector(3 downto 0);
signal vid_g : std_logic_vector(3 downto 0);
signal vid_b : std_logic_vector(3 downto 0);
-- SPI flash signals
signal spi_sel_n : std_logic;
signal spi_clk : std_logic;
signal spi_data : std_logic_vector(3 downto 0);
-- Output signals for LEDs
signal led : std_logic_vector(15 downto 0);
signal brdyn : std_ulogic;
signal sw : std_logic_vector(15 downto 0):= (others =>'0');
signal btn : std_logic_vector(4 downto 0):= (others =>'0');
signal ddr2_dq : std_logic_vector(15 downto 0);
signal ddr2_addr : std_logic_vector(12 downto 0);
signal ddr2_ba : std_logic_vector(2 downto 0);
signal ddr2_ras_n : std_ulogic;
signal ddr2_cas_n : std_ulogic;
signal ddr2_we_n : std_ulogic;
signal ddr2_cke : std_logic_vector(0 downto 0);
signal ddr2_odt : std_logic_vector(0 downto 0);
signal ddr2_cs_n : std_logic_vector(0 downto 0);
signal ddr2_dm : std_logic_vector(1 downto 0);
signal ddr2_dqs_p : std_logic_vector(1 downto 0);
signal ddr2_dqs_n : std_logic_vector(1 downto 0);
signal ddr2_ck_p : std_logic_vector(0 downto 0);
signal ddr2_ck_n : std_logic_vector(0 downto 0);
-- MIG DDR2 Simulation parameters
constant SIM_BYPASS_INIT_CAL : string := "FAST";
-- # = "OFF" - Complete memory init &
-- calibration sequence
-- # = "SKIP" - Not supported
-- # = "FAST" - Complete memory init & use
-- abbreviated calib sequence
constant SIMULATION : string := "TRUE";
-- Should be TRUE during design simulations and
-- FALSE during implementations
begin
-- clock and reset
clk <= not clk after ct * 1 ns;
rst <= '1', '0' after 100 ns;
rstn <= not rst;
dsubre <= '0';
urxd <= 'H';
--spi_sel_n <= 'H';
--spi_clk <= 'L';
d3 : entity work.leon3mp
generic map (fabtech, memtech, padtech, clktech, disas, dbguart, pclow, SIM_BYPASS_INIT_CAL, SIMULATION, USE_MIG_INTERFACE_MODEL)
port map (
sys_clk_i => clk, btnCpuResetn => rstn,
-- DDR2
ddr2_dq => ddr2_dq, ddr2_addr => ddr2_addr, ddr2_ba => ddr2_ba,
ddr2_ras_n => ddr2_ras_n, ddr2_cas_n => ddr2_cas_n, ddr2_we_n => ddr2_we_n,
ddr2_cke => ddr2_cke, ddr2_odt => ddr2_odt, ddr2_cs_n => ddr2_cs_n,
ddr2_dm => ddr2_dm, ddr2_dqs_p => ddr2_dqs_p, ddr2_dqs_n => ddr2_dqs_n,
ddr2_ck_p => ddr2_ck_p, ddr2_ck_n => ddr2_ck_n,
-- AHB Uart
uart_txd_in => dsurx,
uart_rxd_out => dsutx,
-- PHY
eth_crsdv => erx_crs,
eth_rxd => etxdt,
eth_rxerr => erx_er,
-- SPI
QspiCSn => spi_sel_n,
QspiDB => spi_data,
QspiClk => spi_clk,
-- Output signals for LEDs
led => led,
sw => sw,
btn => btn);
ddr2mem0 : ddr2ram
generic map(width => CFG_DDR2SP_DATAWIDTH, abits => 13, babits => 3, colbits => 10, rowbits => 13,
implbanks => 8, fname => sdramfile, speedbin=>1, density => 3, lddelay => (0 ns), swap => CFG_MIG_7SERIES, ldguard => 1)
port map (ck => ddr2_ck_p(0), ckn => ddr2_ck_n(0), cke => ddr2_cke(0), csn => ddr2_cs_n(0),
odt => ddr2_odt(0), rasn => ddr2_ras_n, casn => ddr2_cas_n, wen => ddr2_we_n,
dm => ddr2_dm, ba => ddr2_ba, a => ddr2_addr, dq => ddr2_dq(15 downto 0),
dqs => ddr2_dqs_p, dqsn =>ddr2_dqs_n, doload => led(4));
spimem0: if CFG_SPIMCTRL = 1 generate
s0 : spi_flash generic map (ftype => 4, debug => 0, fname => promfile,
readcmd => CFG_SPIMCTRL_READCMD,
dummybyte => CFG_SPIMCTRL_DUMMYBYTE,
dualoutput => CFG_SPIMCTRL_DUALOUTPUT)
port map (spi_clk, spi_data(0), spi_data(1), spi_sel_n);
end generate spimem0;
-- Ethernet model diasbled
erx_crs <= '0'; etxdt<= (others =>'0'); erx_er<= '0';
led(3) <= 'L'; -- ERROR pull-down
error <= not led(3);
iuerr : process
variable datav : std_logic_vector(31 downto 0);
begin
wait for 10 us;
assert (to_X01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure;
end process;
data <= buskeep(data) after 5 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#00#, 16#ef#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
--
-- txc(dsutx, 16#80#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end;
| gpl-3.0 | 7c55fa31192b45e3330ba37dbadf9acc | 0.561743 | 3.377294 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-ztex-ufm-111/leon3mp.vhd | 1 | 16,651 | ------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2011 Aeroflex Gaisler AB
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
-- Patched for ZTEX: Oleg Belousov <[email protected]>
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.spi.all;
use gaisler.jtag.all;
--pragma translate_off
use gaisler.sim.all;
--pragma translate_on
use work.config.all;
library unisim;
use unisim.vcomponents.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
reset : in std_ulogic;
clk48 : in std_ulogic;
errorn : out std_logic;
-- DDR SDRAM
mcb3_dram_dq : inout std_logic_vector(15 downto 0);
mcb3_rzq : inout std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_a : out std_logic_vector(12 downto 0);
mcb3_dram_ba : out std_logic_vector(1 downto 0);
mcb3_dram_cke : out std_logic;
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udm : out std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
-- Debug support unit
dsubre : in std_ulogic; -- Debug Unit break (connect to button)
dsuact : out std_ulogic; -- Debug Unit break (connect to button)
-- AHB UART (debug link)
dsurx : in std_ulogic;
dsutx : out std_ulogic;
-- UART
rxd1 : in std_ulogic;
txd1 : out std_ulogic;
-- SD card
sd_dat : inout std_logic;
sd_cmd : inout std_logic;
sd_sck : inout std_logic;
sd_dat3 : out std_logic
);
end;
architecture rtl of leon3mp is
signal vcc : std_logic;
signal gnd : std_logic;
signal clk200 : std_logic;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal cgo_ddr : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal gpti : gptimer_in_type;
signal spii : spi_in_type;
signal spio : spi_out_type;
signal slvsel : std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0);
signal lclk, lclk200 : std_ulogic;
signal clkm, rstn, clkml : std_ulogic;
signal tck, tms, tdi, tdo : std_ulogic;
signal rstraw : std_logic;
signal lock : std_logic;
-- Used for connecting input/output signals to the DDR2 controller
signal core_ddr_clk : std_logic_vector(2 downto 0);
signal core_ddr_clkb : std_logic_vector(2 downto 0);
signal core_ddr_cke : std_logic_vector(1 downto 0);
signal core_ddr_csb : std_logic_vector(1 downto 0);
signal core_ddr_ad : std_logic_vector(13 downto 0);
signal core_ddr_odt : std_logic_vector(1 downto 0);
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of lock : signal is true;
attribute syn_keep of clkml : signal is true;
attribute syn_keep of clkm : signal is true;
attribute syn_preserve of clkml : signal is true;
attribute syn_preserve of clkm : signal is true;
attribute keep of lock : signal is true;
attribute keep of clkml : signal is true;
attribute keep of clkm : signal is true;
constant BOARD_FREQ : integer := 48000; -- CLK input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= '1';
gnd <= '0';
cgi.pllctrl <= "00";
cgi.pllrst <= rstraw;
rst0 : rstgen generic map (acthigh => 1)
port map (reset, clkm, lock, rstn, rstraw);
clk48_pad : clkpad generic map (tech => padtech) port map (clk48, lclk);
-- clock generator
clkgen0 : clkgen
generic map (fabtech, CFG_CLKMUL, CFG_CLKDIV, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (lclk, gnd, clkm, open, open, open, open, cgi, cgo, open, open, open);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => 1,
nahbm => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
-- LEON3 processor
leon3gen : if CFG_LEON3 = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3s
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR,
CFG_NCPU-1, CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
errorn_pad : outpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
-- LEON3 Debug Support Unit
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
dsui.enable <= '1';
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
-- Debug UART
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart
generic map (hindex => CFG_NCPU, pindex => 4, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(CFG_NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (dsurx, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (dsutx, duo.txd);
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(4) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd);
end generate;
----------------------------------------------------------------------
--- DDR2 memory controller ------------------------------------------
----------------------------------------------------------------------
mig_gen : if (CFG_MIG_DDR2 = 1) generate
clkgen_ddr : clkgen
generic map (fabtech, 25, 6, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (lclk, gnd, clk200, open, open, open, open, cgi, cgo_ddr, open, open, open);
ddrc : entity work.ahb2mig_ztex generic map(
hindex => 4, haddr => 16#400#, hmask => CFG_MIG_HMASK,
pindex => 5, paddr => 5)
port map(
mcb3_dram_dq => mcb3_dram_dq,
mcb3_rzq => mcb3_rzq,
mcb3_dram_udqs => mcb3_dram_udqs,
mcb3_dram_dqs => mcb3_dram_dqs,
mcb3_dram_a => mcb3_dram_a,
mcb3_dram_ba => mcb3_dram_ba,
mcb3_dram_cke => mcb3_dram_cke,
mcb3_dram_ras_n => mcb3_dram_ras_n,
mcb3_dram_cas_n => mcb3_dram_cas_n,
mcb3_dram_we_n => mcb3_dram_we_n,
mcb3_dram_dm => mcb3_dram_dm,
mcb3_dram_udm => mcb3_dram_udm,
mcb3_dram_ck => mcb3_dram_ck,
mcb3_dram_ck_n => mcb3_dram_ck_n,
ahbsi => ahbsi,
ahbso => ahbso(4),
apbi => apbi,
apbo => apbo(5),
calib_done => lock,
rst_n_syn => rstn,
rst_n_async => rstraw,
clk_amba => clkm,
clk_mem => clk200,
test_error => open
);
end generate;
noddr : if CFG_MIG_DDR2 = 0 generate lock <= '1'; end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
-- APB Bridge
apb0 : apbctrl
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
-- Interrupt controller
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
-- General purpose timer unit
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW,
ntimers => CFG_GPT_NTIM, nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti <= gpti_dhalt_drive(dsuo.tstop);
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
-- GPIO Unit
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate
grgpio0: grgpio
generic map(pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK, nbits => 12)
port map(rstn, clkm, apbi, apbo(11), gpioi, gpioo);
end generate;
-- NOTE:
-- GPIO pads are not instantiated here. If you want to use
-- GPIO then add a top-level port, update the UCF and
-- instantiate pads for the GPIO lines as is done in other
-- template designs.
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart, fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd1;
u1i.ctsn <= '0';
u1i.extclk <= '0';
txd1 <= u1o.txd;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
spic: if CFG_SPICTRL_ENABLE = 1 generate -- SPI controller
spi1 : spictrl
generic map (pindex => 9, paddr => 9, pmask => 16#fff#, pirq => 10,
fdepth => CFG_SPICTRL_FIFO, slvselen => CFG_SPICTRL_SLVREG,
slvselsz => CFG_SPICTRL_SLVS, odmode => CFG_SPICTRL_ODMODE,
syncram => CFG_SPICTRL_SYNCRAM, ft => CFG_SPICTRL_FT)
port map (rstn, clkm, apbi, apbo(9), spii, spio, slvsel);
miso_pad : iopad generic map (tech => padtech)
port map (sd_dat, spio.miso, spio.misooen, spii.miso);
mosi_pad : iopad generic map (tech => padtech)
port map (sd_cmd, spio.mosi, spio.mosioen, spii.mosi);
sck_pad : iopad generic map (tech => padtech)
port map (sd_sck, spio.sck, spio.sckoen, spii.sck);
slvsel_pad : outpad generic map (tech => padtech)
port map (sd_dat3, slvsel(0));
spii.spisel <= '1'; -- Master only
end generate spic;
nospic: if CFG_SPICTRL_ENABLE = 0 generate apbo(9) <= apb_none; end generate;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(6) <= ahbs_none;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ahbramgen : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram
generic map (hindex => 3, haddr => CFG_AHBRADDR, tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ)
port map (rstn, clkm, ahbsi, ahbso(3));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(3) <= ahbs_none; end generate;
-----------------------------------------------------------------------
-- Test report module, only used for simulation ----------------------
-----------------------------------------------------------------------
--pragma translate_off
test0 : ahbrep generic map (hindex => 5, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(5));
--pragma translate_on
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Demonstration design for ZTEX USB-FPGA Module 1.11",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end rtl;
| gpl-3.0 | a3e3bbc5546d5d3d6b295bb3c6eb21af | 0.534562 | 3.775737 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-avnet-eval-xc4vlx60/config.vhd | 1 | 6,562 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := virtex4;
constant CFG_MEMTECH : integer := virtex4;
constant CFG_PADTECH : integer := virtex4;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := virtex4;
constant CFG_CLKMUL : integer := (7);
constant CFG_CLKDIV : integer := (5);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0 + 0*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2 + 64*0;
constant CFG_ATBSZ : integer := 2;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_STAT_ENABLE : integer := 0;
constant CFG_STAT_CNT : integer := 1;
constant CFG_STAT_NMAX : integer := 0;
constant CFG_STAT_DSUEN : integer := 0;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
constant CFG_ALTWIN : integer := 0;
constant CFG_REX : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 0;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 4;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#010a#;
constant CFG_ETH_ENM : integer := 16#020060#;
constant CFG_ETH_ENL : integer := 16#000015#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 1;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- DDR controller
constant CFG_DDRSP : integer := 0;
constant CFG_DDRSP_INIT : integer := 0;
constant CFG_DDRSP_FREQ : integer := 100;
constant CFG_DDRSP_COL : integer := 9;
constant CFG_DDRSP_SIZE : integer := 8;
constant CFG_DDRSP_RSKEW : integer := 0;
-- Xilinx MIG
constant CFG_MIG_DDR2 : integer := 1;
constant CFG_MIG_RANKS : integer := (1);
constant CFG_MIG_COLBITS : integer := (10);
constant CFG_MIG_ROWBITS : integer := (13);
constant CFG_MIG_BANKBITS: integer := (2);
constant CFG_MIG_HMASK : integer := 16#FE0#;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 32;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 8;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := (8);
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-3.0 | 50ce97cfaaa07ec6f742933b0f1d0104 | 0.643859 | 3.593647 | false | false | false | false |
techee/geany | tests/ctags/vhdl-process.vhd | 7 | 1,444 | --
-- Taken from rtl/riverlib/core/stacktrbuf.vhd of https://github.com/sergeykhbr/riscv_vhdl
--
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2017 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief Stack trace buffer on hardware level.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
entity StackTraceBuffer is
generic (
abits : integer := 5;
dbits : integer := 64
);
port (
i_clk : in std_logic;
i_raddr : in std_logic_vector(abits-1 downto 0);
o_rdata : out std_logic_vector(dbits-1 downto 0);
i_we : in std_logic;
i_waddr : in std_logic_vector(abits-1 downto 0);
i_wdata : in std_logic_vector(dbits-1 downto 0)
);
end;
architecture arch_StackTraceBuffer of StackTraceBuffer is
type ram_type is array ((2**abits)-1 downto 0) of std_logic_vector (dbits-1 downto 0);
signal stackbuf : ram_type;
signal raddr : std_logic_vector(abits-1 downto 0);
begin
-- registers:
regs : process(i_clk) begin
if rising_edge(i_clk) then
if i_we = '1' then
stackbuf(conv_integer(i_waddr)) <= i_wdata;
end if;
raddr <= i_raddr;
end if;
end process;
o_rdata <= stackbuf(conv_integer(raddr));
end;
| gpl-2.0 | 9dccceebdfd85eab63c88cb0119e3de0 | 0.581717 | 3.61 | false | false | false | false |
hoglet67/CoPro6502 | src/DCM/dcm_32_100.vhd | 1 | 2,189 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity dcm_32_100 is
port (CLKIN_IN : in std_logic;
CLK0_OUT : out std_logic;
CLK0_OUT1 : out std_logic;
CLK2X_OUT : out std_logic);
end dcm_32_100;
architecture BEHAVIORAL of dcm_32_100 is
signal CLKFX_BUF : std_logic;
signal CLK2X_BUF : std_logic;
signal CLKIN_IBUFG : std_logic;
signal GND_BIT : std_logic;
begin
GND_BIT <= '0';
CLKFX_BUFG_INST : BUFG
port map (I => CLKFX_BUF, O => CLK0_OUT);
CLK2X_BUFG_INST : BUFG
port map (I => CLK2X_BUF, O => CLK2X_OUT);
DCM_INST : DCM
generic map(CLK_FEEDBACK => "NONE",
CLKDV_DIVIDE => 4.0, -- 100.00 = 32.000 * 25/8
CLKFX_MULTIPLY => 25,
CLKFX_DIVIDE => 8,
CLKIN_DIVIDE_BY_2 => false,
CLKIN_PERIOD => 31.25,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => true,
FACTORY_JF => x"C080",
PHASE_SHIFT => 0,
STARTUP_WAIT => false)
port map (CLKFB => GND_BIT,
CLKIN => CLKIN_IN,
DSSEN => GND_BIT,
PSCLK => GND_BIT,
PSEN => GND_BIT,
PSINCDEC => GND_BIT,
RST => GND_BIT,
CLKDV => open,
CLKFX => CLKFX_BUF,
CLKFX180 => open,
CLK0 => open,
CLK2X => CLK2X_BUF,
CLK2X180 => open,
CLK90 => open,
CLK180 => open,
CLK270 => open,
LOCKED => open,
PSDONE => open,
STATUS => open);
end BEHAVIORAL;
| gpl-3.0 | 04a51451e2259e4af8960e0e2f1af499 | 0.414344 | 4.091589 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-xilinx-ml510/svga2ch7301c.vhd | 3 | 10,239 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: svga2ch7301c
-- File: svga2ch7301c.vhd
-- Author: Jan Andersson - Aeroflex Gaisler AB
-- [email protected]
--
-- Description: Converter inteneded to connect a SVGACTRL core to a Chrontel
-- CH7301C DVI transmitter. Multiplexes data and generates clocks.
-- Tailored for use on the Xilinx ML50x boards with Leon3/GRLIB
-- template designs.
--
-- This multiplexer has been developed for use with the Chrontel CH7301C DVI
-- transmitter. Supported multiplexed formats are, as in the CH7301 datasheet:
--
-- IDF Description
-- 0 12-bit multiplexed RGB input (24-bit color), (scheme 1)
-- 1 12-bit multiplexed RGB2 input (24-bit color), (scheme 2)
-- 2 8-bit multiplexed RGB input (16-bit color, 565)
-- 3 8-bit multiplexed RGB input (15-bit color, 555)
--
-- This core assumes a 100 MHz input clock on the 'clk' input.
--
-- If the generic 'dynamic' is non-zero the core uses the value vgao.bitdepth
-- to decide if multiplexing should be done according to IDF 0 or IDF 2.
-- vago.bitdepth = "11" gives IDF 0, others give IDF2.
-- The 'idf' generic is not used when the 'dynamic' generic is non-zero.
-- Note that if dynamic selection is enabled you will need to reconfigure
-- the DVI transmitter when the VGA core changes bit depth.
--
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.misc.all;
library grlib;
use grlib.stdlib.all;
-- pragma translate_off
library unisim;
use unisim.BUFG;
use unisim.DCM;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity svga2ch7301c is
generic (
tech : integer := 0;
idf : integer := 0;
dynamic : integer := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
clksel : in std_logic_vector(1 downto 0);
vgao : in apbvga_out_type;
vgaclk_fb : in std_ulogic;
clk25_fb : in std_ulogic;
clk40_fb : in std_ulogic;
clk65_fb : in std_ulogic;
vgaclk : out std_ulogic;
clk25 : out std_ulogic;
clk40 : out std_ulogic;
clk65 : out std_ulogic;
dclk_p : out std_ulogic;
dclk_n : out std_ulogic;
locked : out std_ulogic;
data : out std_logic_vector(11 downto 0);
hsync : out std_ulogic;
vsync : out std_ulogic;
de : out std_ulogic
);
end svga2ch7301c;
architecture rtl of svga2ch7301c is
component BUFG port (O : out std_logic; I : in std_logic); end component;
component BUFGMUX port ( O : out std_ulogic; I0 : in std_ulogic;
I1 : in std_ulogic; S : in std_ulogic);
end component;
component DCM
generic (
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false
);
port (
CLKFB : in std_logic;
CLKIN : in std_logic;
DSSEN : in std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector (7 downto 0));
end component;
constant VERSION : integer := 1;
constant CLKIN_PERIOD_ST : string := "10.0";
attribute CLKIN_PERIOD : string;
attribute CLKIN_PERIOD of dll1: label is CLKIN_PERIOD_ST;
attribute CLKIN_PERIOD of dll2: label is CLKIN_PERIOD_ST;
signal clk_l, clk_m, clk_n, clk_o : std_logic;
signal dll0lock, dll1lock, dll2lock : std_logic;
signal dllrst : std_ulogic;
signal vcc, gnd : std_logic;
signal d0, d1 : std_logic_vector(11 downto 0);
signal red, green, blue : std_logic_vector(7 downto 0);
signal lvgaclk, lclk40, lclk65, lclk40_65 : std_ulogic;
signal clkval : std_logic_vector(1 downto 0);
begin -- rtl
vcc <= '1'; gnd <= '0';
-----------------------------------------------------------------------------
-- RGB data multiplexer
-----------------------------------------------------------------------------
red <= vgao.video_out_r;
green <= vgao.video_out_g;
blue <= vgao.video_out_b;
static: if dynamic = 0 generate
idf0: if (idf = 0) generate
d0 <= green(3 downto 0) & blue(7 downto 0);
d1 <= red(7 downto 0) & green(7 downto 4);
end generate;
idf1: if (idf = 1) generate
d0 <= green(4 downto 2) & blue(7 downto 3) & green(0) & blue(2 downto 0);
d1 <= red(7 downto 3) & green(7 downto 5) & red(2 downto 0) & green(1);
end generate;
idf2: if (idf = 2) generate
d0(11 downto 4) <= green(4 downto 2) & blue(7 downto 3);
d0(3 downto 0) <= (others => '0');
d1(11 downto 4) <= red(7 downto 3) & green(7 downto 5);
d1(3 downto 0) <= (others => '0');
data(3 downto 0) <= (others => '0');
end generate;
idf3: if (idf = 3) generate
d0(11 downto 4) <= green(5 downto 3) & blue(7 downto 3);
d0(3 downto 0) <= (others => '0');
d1(11 downto 4) <= '0' & red(7 downto 3) & green(7 downto 6);
d1(3 downto 0) <= (others => '0');
data(3 downto 0) <= (others => '0');
end generate idf3;
-- DDR regs
dataregs: for i in 11 downto (4*(idf/2)) generate
ddr_oreg0 : ddr_oreg generic map (tech)
port map (q => data(i), c1 => vgaclk_fb, c2 => gnd, ce => vcc,
d1 => d0(i), d2 => d1(i), r => gnd, s => gnd);
end generate;
end generate;
nostatic: if dynamic /= 0 generate
d0 <= green(3 downto 0) & blue(7 downto 0) when vgao.bitdepth = "11" else
green(4 downto 2) & blue(7 downto 3) & "0000";
d1 <= red(7 downto 0) & green(7 downto 4) when vgao.bitdepth = "11" else
red(7 downto 3) & green(7 downto 5) & "0000";
dataregs: for i in 11 downto 0 generate
ddr_oreg0 : ddr_oreg generic map (tech)
port map (q => data(i), c1 => vgaclk_fb, c2 => gnd, ce => vcc,
d1 => d0(i), d2 => d1(i), r => gnd, s => gnd);
end generate;
end generate;
-----------------------------------------------------------------------------
-- Sync signals
-----------------------------------------------------------------------------
process (vgaclk_fb)
begin -- process
if rising_edge(vgaclk_fb) then
hsync <= vgao.hsync;
vsync <= vgao.vsync;
de <= vgao.blank;
end if;
end process;
-----------------------------------------------------------------------------
-- Clock generation
-----------------------------------------------------------------------------
ddroreg_p : ddr_oreg generic map (tech)
port map (q => dclk_p, c1 => vgaclk_fb, c2 => gnd, ce => vcc,
d1 => vcc, d2 => gnd, r => gnd, s => gnd);
ddroreg_n : ddr_oreg generic map (tech)
port map (q => dclk_n, c1 => vgaclk_fb, c2 => gnd, ce => vcc,
d1 => gnd, d2 => vcc, r => gnd, s => gnd);
-- Clock selection
bufg00 : BUFG port map (I => lvgaclk, O => vgaclk);
lvgaclk <= clk25_fb when clksel(1) = '0' else lclk40_65;
lclk40_65 <= lclk40 when clksel(0) = '0' else lclk65;
bufg01 : BUFG port map (I => clk40_fb, O => lclk40);
bufg02 : BUFG port map (I => clk65_fb, O => lclk65);
dllrst <= not rstn;
-- Generate clocks
clkdiv : process(clk_m, rstn)
begin
if (rstn and dll1lock) = '0' then clkval <= "00";
elsif rising_edge(clk_m) then
clkval <= clkval + 1;
end if;
end process;
clk25 <= clkval(1);
dll0lock <= '1';
bufg03 : BUFG port map (I => clk_l, O => clk_m);
dll1 : DCM
generic map (CLKFX_MULTIPLY => 4, CLKFX_DIVIDE => 10,
DFS_FREQUENCY_MODE => "LOW", DLL_FREQUENCY_MODE => "LOW")
port map ( CLKIN => clk, CLKFB => clk_m, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dllrst, CLK0 => clk_l,
CLKFX => clk40, LOCKED => dll1lock);
bufg04 : BUFG port map (I => clk_n, O => clk_o);
dll2 : DCM
generic map (CLKFX_MULTIPLY => 13, CLKFX_DIVIDE => 20,
DFS_FREQUENCY_MODE => "LOW", DLL_FREQUENCY_MODE => "LOW")
port map ( CLKIN => clk, CLKFB => clk_o, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dllrst, CLK0 => clk_n,
CLKFX => clk65, LOCKED => dll2lock);
locked <= dll0lock and dll1lock and dll2lock;
end rtl;
| gpl-3.0 | 99fa5524a8ee5ed9bb1e7d9d45e3de6d | 0.554937 | 3.566353 | false | false | false | false |
yishinli/emc2 | src/hal/drivers/m5i20/hostmot5_src/hostmot5-4eh.vhd | 1 | 26,131 | library IEEE;
use IEEE.std_logic_1164.all; -- defines std_logic types
library UNISIM;
use UNISIM.VComponents.all;
-- 4 axis version with 48 I/O bits
entity HostMot5_4EH is
port
(
LRD: in STD_LOGIC;
LWR: in STD_LOGIC;
LW_R: in STD_LOGIC;
ALE: in STD_LOGIC;
ADS: in STD_LOGIC;
BLAST: in STD_LOGIC;
WAITO: in STD_LOGIC;
LOCKO: in STD_LOGIC;
CS0: in STD_LOGIC;
CS1: in STD_LOGIC;
READY: out STD_LOGIC;
INT: out STD_LOGIC;
LAD: inout STD_LOGIC_VECTOR (31 downto 0); -- data/address bus
LA: in STD_LOGIC_VECTOR (8 downto 2); -- non-muxed address bus
lBE: in STD_LOGIC_VECTOR (3 downto 0); -- byte enables
SYNCLK: in STD_LOGIC;
LCLK: in STD_LOGIC;
-- I/O signals
A: in STD_LOGIC_VECTOR (3 downto 0);
B: in STD_LOGIC_VECTOR (3 downto 0);
IDX: in STD_LOGIC_VECTOR (3 downto 0);
PWM: inout STD_LOGIC_VECTOR (3 downto 0);
ENA: out STD_LOGIC_VECTOR (3 downto 0);
DIR: inout STD_LOGIC_VECTOR (3 downto 0);
IOBITSA: inout STD_LOGIC_VECTOR (23 downto 0);
IOBITSB: inout STD_LOGIC_VECTOR (23 downto 0);
-- led bits
LEDS: out STD_LOGIC_VECTOR(7 downto 0)
);
end HostMot5_4EH; -- for 5I20 or 4I65 100 MHz PWM clk
architecture dataflow of Hostmot5_4EH is
alias BLE: STD_LOGIC is LBE(0); -- 16 bit mode
alias BHE: STD_LOGIC is LBE(3); -- 16 bit mode
alias LA1: STD_LOGIC is LBE(1); -- 8/16 bit mode
alias LA0: STD_LOGIC is LBE(0); -- 8 bit mode
-- misc global signals --
signal D: STD_LOGIC_VECTOR (31 downto 0); -- internal data bus
signal LatchedA: STD_LOGIC_VECTOR (15 downto 0);
signal LatchedLBE: STD_LOGIC_VECTOR (3 downto 0);
signal PreFastRead: STD_LOGIC;
signal FastRead: STD_LOGIC;
-- Version specific constants --
constant counters :integer := 4;
constant HMID : STD_LOGIC_VECTOR (31 downto 0) := x"AA020004"; -- MSW = rev 2, LSW = 4 axis
constant MasterClock : STD_LOGIC_VECTOR (31 downto 0) := x"05F5E100"; -- = 100 MHz
-- misc global signals --
signal CardSelect: STD_LOGIC; -- card select decode
signal LEDView: STD_LOGIC_VECTOR (7 downto 0); -- index register
signal FClk: STD_LOGIC; -- high speed clock = 100 MHz
signal CLKFB: STD_LOGIC;
signal CLK0: STD_LOGIC;
signal CLK2X: STD_LOGIC;
-- irq related signals
signal IRQSource: STD_LOGIC;
signal IRQLatch: STD_LOGIC;
signal IRQMask: STD_LOGIC;
signal MissedIRQ: STD_LOGIC;
signal StopOnMissedIRQ: STD_LOGIC;
signal ClearMissedIRQ: STD_LOGIC;
signal LatchOnInterrupt: STD_LOGIC;
-- timeout related signals
signal ReloadWDCmd: STD_LOGIC;
signal StopOnTimeout: STD_LOGIC;
signal WDTimeOut: STD_LOGIC;
-- LEDView and id reg signals
signal LoadLEDViewCmd: STD_LOGIC;
signal ReadLEDViewCmd: STD_LOGIC;
signal Enasigs :STD_LOGIC_VECTOR (counters-1 downto 0);
signal IDSel: STD_LOGIC;
signal ReadIDCmd: STD_LOGIC;
signal MCSel: STD_LOGIC;
signal ReadMCCmd: STD_LOGIC;
-- irqdiv reg signals
signal ReadIRQDivCmd: STD_LOGIC;
signal LoadIRQDivCmd: STD_LOGIC;
signal ClearIRQCmd: STD_LOGIC;
-- irq sel reg signals
signal loadGCRCmd: STD_LOGIC;
signal LoadGMRCmd: STD_LOGIC;
signal ReadGMRCmd: STD_LOGIC;
-- timeout reg signals
signal loadTimeoutCmd: STD_LOGIC;
signal ReadTimeoutCmd: STD_LOGIC;
signal ReadTimerCmd: STD_LOGIC;
-- phase accumulator signals
signal ReadPhaseCmd: STD_LOGIC;
signal LoadPhaseCmd: STD_LOGIC;
-- counter signals --
signal CounterRead: STD_LOGIC_VECTOR (counters-1 downto 0); -- read counter
signal GlobalCounterEnable: STD_LOGIC; -- enable counting
signal GlobalCountLatchcmd: STD_LOGIC; -- command to latch counter value
signal GlobalCountLatch: STD_LOGIC; -- command + irq generated latch count
signal CountLatchEdge1: STD_LOGIC;
signal CountLatchEdge2: STD_LOGIC;
signal CCRLoadCmds: STD_LOGIC_VECTOR (counters-1 downto 0); -- counter control reg loads
signal CCRReadCmds: STD_LOGIC_VECTOR (counters-1 downto 0); -- counter control reg reads
signal GlobalCounterClear: STD_LOGIC; -- clear counter
-- secondary counter signals --
signal SCounterRead: STD_LOGIC_VECTOR (counters-1 downto 0); -- read counter
signal SCCRLoadCmds: STD_LOGIC_VECTOR (counters-1 downto 0); -- counter control reg loads
signal SCCRReadCmds: STD_LOGIC_VECTOR (counters-1 downto 0); -- counter control reg reads
-- pwm generator signals --
signal RefCountBus: STD_LOGIC_VECTOR (9 downto 0);
signal LoadPWM: STD_LOGIC_VECTOR (counters-1 downto 0);
signal ReadPWM: STD_LOGIC_VECTOR (counters-1 downto 0);
signal PCRLoadCmds: STD_LOGIC_VECTOR (counters-1 downto 0);
signal PCRReadCmds: STD_LOGIC_VECTOR (counters-1 downto 0);
signal GlobalPWMEnable: STD_LOGIC;
signal GlobalClearPWM: STD_LOGIC;
signal GlobalClearPWMCmd: STD_LOGIC;
signal StopPWM: STD_LOGIC;
-- misc i/o signals
signal PortASel: STD_LOGIC;
signal DDRASel: STD_LOGIC;
signal LoadPortA: STD_LOGIC;
signal LoadDDRA: STD_LOGIC;
signal ReadDDRA: STD_LOGIC;
signal ReadPortA: STD_LOGIC;
signal PortBSel: STD_LOGIC;
signal DDRBSel: STD_LOGIC;
signal LoadPortB: STD_LOGIC;
signal LoadDDRB: STD_LOGIC;
signal ReadDDRB: STD_LOGIC;
signal ReadPortB: STD_LOGIC;
-- decodes --
signal LEDViewSel: STD_LOGIC;
signal IndexSel: STD_LOGIC;
signal GCRSel: STD_LOGIC;
signal GMRSel: STD_LOGIC;
signal CCRSel: STD_LOGIC;
signal SCCRSel: STD_LOGIC;
signal PCRSel: STD_LOGIC;
signal TimeOutSel: STD_LOGIC;
signal TimerSel: STD_LOGIC;
signal IRQDIVSel: STD_LOGIC;
signal PWMValSel: STD_LOGIC;
signal PhaseSel: STD_LOGIC;
signal CounterSel: STD_LOGIC;
signal SCounterSel: STD_LOGIC;
function OneOfFourDecode(ena : std_logic; dec : std_logic_vector(1 downto 0)) return std_logic_vector is
variable result : std_logic_vector(counters-1 downto 0);
begin
if ena = '1' then
case dec is
when "00" => result := "0001";
when "01" => result := "0010";
when "10" => result := "0100";
when "11" => result := "1000";
when others => result := "0000";
end case;
else
result := "0000";
end if;
return result;
end OneOfFourDecode;
function OneOfFourMux(sel: std_logic_vector (1 downto 0); input: std_logic_vector(counters-1 downto 0)) return std_logic is
variable result : std_logic;
begin
case sel is
when "00" => result := input(0);
when "01" => result := input(1);
when "10" => result := input(2);
when "11" => result := input(3);
when others => result := '0';
end case;
return result;
end OneOfFourMux;
component indexreg
port (
clk: in STD_LOGIC;
ibus: in STD_LOGIC_VECTOR (15 downto 0);
obus: out STD_LOGIC_VECTOR (15 downto 0);
loadindex: in STD_LOGIC;
readindex: in STD_LOGIC;
index: out STD_LOGIC_VECTOR (7 downto 0)
);
end component;
component counter
port (
obus: out STD_LOGIC_VECTOR (31 downto 0);
ibus: in STD_LOGIC_VECTOR (31 downto 0);
quada: in STD_LOGIC;
quadb: in STD_LOGIC;
index: in STD_LOGIC;
ccrloadcmd: in STD_LOGIC;
ccrreadcmd: in STD_LOGIC;
countoutreadcmd: in STD_LOGIC;
countlatchcmd: in STD_LOGIC;
countclearcmd: in STD_LOGIC;
countenable: in STD_LOGIC;
indexmask: in STD_LOGIC;
nads: in STD_LOGIC;
clk: in STD_LOGIC
);
end component;
component pwmgenh
port (
clk: in STD_LOGIC;
hclk: in STD_LOGIC;
refcount: in STD_LOGIC_VECTOR (9 downto 0);
ibus: in STD_LOGIC_VECTOR (15 downto 0);
obus: out STD_LOGIC_VECTOR (15 downto 0);
loadpwmval: in STD_LOGIC;
readpwmval: in STD_LOGIC;
clearpwmval: in STD_LOGIC;
pcrloadcmd: STD_LOGIC;
pcrreadcmd: STD_LOGIC;
pwmout: out STD_LOGIC;
dirio: inout STD_LOGIC;
enablein: in STD_LOGIC;
enableout: out STD_LOGIC
);
end component pwmgenh;
component pwmrefh is
port (
clk: in STD_LOGIC;
hclk: in STD_LOGIC;
refcount: out STD_LOGIC_VECTOR (9 downto 0);
irqgen: out STD_LOGIC;
ibus: in STD_LOGIC_VECTOR (15 downto 0);
obus: out STD_LOGIC_VECTOR (15 downto 0);
irqdivload: in STD_LOGIC;
irqdivread: in STD_LOGIC;
phaseload: in STD_LOGIC;
phaseread: in STD_LOGIC
);
end component pwmrefh;
component globalcontrolreg is
port (
clk: in STD_LOGIC;
ibus: in STD_LOGIC_VECTOR (15 downto 0);
reset: in STD_LOGIC;
loadgcr: in STD_LOGIC;
ctrclear: out STD_LOGIC;
ctrlatch: out STD_LOGIC;
pwmclear: out STD_LOGIC;
irqclear: out STD_LOGIC;
reloadwd: out STD_LOGIC
);
end component globalcontrolreg;
component globalmodereg is
port (
clk: in STD_LOGIC;
ibus: in STD_LOGIC_VECTOR (15 downto 0);
obus: out STD_LOGIC_VECTOR (15 downto 0);
reset: in STD_LOGIC;
loadglobalmode: in STD_LOGIC;
readglobalmode: in STD_LOGIC;
ctrena: out STD_LOGIC;
pwmena: out STD_LOGIC;
clearpwmena: in STD_LOGIC;
loi: out STD_LOGIC;
som: out STD_LOGIC;
sot: out STD_LOGIC;
miout: out STD_LOGIC;
miin: in STD_LOGIC;
irqmask: out STD_LOGIC;
irqstatus: in STD_LOGIC
);
end component globalmodereg;
component WordPR24 is
port (
clear: in STD_LOGIC;
clk: in STD_LOGIC;
ibus: in STD_LOGIC_VECTOR (23 downto 0);
obus: out STD_LOGIC_VECTOR (23 downto 0);
loadport: in STD_LOGIC;
loadddr: in STD_LOGIC;
readddr: in STD_LOGIC;
portdata: out STD_LOGIC_VECTOR (23 downto 0)
);
end component WordPR24;
component Word24RB is
Port (
obus: out STD_LOGIC_VECTOR (23 downto 0);
readport: in STD_LOGIC;
portdata: in STD_LOGIC_VECTOR (23 downto 0) );
end component Word24RB;
component Timeout is
Port ( clk : in std_logic;
ibus : in std_logic_vector(15 downto 0);
obus : out std_logic_vector(15 downto 0);
timeoutload : in std_logic;
timeoutread : in std_logic;
timerread : in std_logic;
reload : in std_logic;
timerz : out std_logic);
end component Timeout;
component idreadback is
Generic ( id : std_logic_vector(31 downto 0);
mc : std_logic_vector(31 downto 0));
Port ( readid : in std_logic;
readmc : in std_logic;
obus : out std_logic_vector(31 downto 0));
end component idreadback;
begin
makecounters: for i in 0 to (counters -1) generate
counterx: counter port map (
obus => D,
ibus => LAD,
quada => A(i),
quadb => B(i),
index => Idx(i),
ccrloadcmd => CCRLoadCmds(i),
ccrreadcmd => CCRReadCmds(i),
countoutreadcmd => CounterRead(i),
countlatchcmd => GlobalCountLatch,
countclearcmd => GlobalCounterClear,
countenable => GlobalCounterEnable,
indexmask => IOBITSA(16 + i),
nads => ADS,
clk => LClk
);
end generate;
makescounters: for i in 0 to (counters -1) generate
counterx: counter port map (
obus => D,
ibus => LAD,
quada => IOBITSA((i*4)),
quadb => IOBITSA((i*4)+1),
index => IOBITSA((i*4)+2),
ccrloadcmd => SCCRLoadCmds(i),
ccrreadcmd => SCCRReadCmds(i),
countoutreadcmd => SCounterRead(i),
countlatchcmd => GlobalCountLatch,
countclearcmd => GlobalCounterClear,
countenable => GlobalCounterEnable,
indexmask => IOBITSA((i*4) +3),
nads => ADS,
clk => LClk
);
end generate;
makepwmgen: for i in 0 to (counters -1) generate
pwmgenx: pwmgenh port map (
clk => LClk,
hclk => FClk,
refcount => RefCountBus,
ibus => LAD(15 downto 0),
obus => D(15 downto 0),
loadpwmval => LoadPWM(i),
readpwmval => ReadPWM(i),
clearpwmval => GlobalClearPWM,
pcrloadcmd => PCRLoadCmds(i),
pcrreadcmd => PCRReadCmds(i),
pwmout => PWM(i),
dirio => Dir(i),
enablein => GlobalPWMEnable,
enableout =>EnaSigs(i)
);
end generate;
oporta: WordPR24 port map (
clear => '0',
clk => LClk,
ibus => LAD(23 downto 0),
obus => D(23 downto 0),
loadport => LoadPortA,
loadddr => LoadDDRA,
readddr => ReadDDRA,
portdata => IOBITSA
);
iporta: Word24RB port map (
obus => D(23 downto 0),
readport => ReadPortA,
portdata => IOBITSA
);
oportb: WordPR24 port map (
clear => '0',
clk => LClk,
ibus => LAD(23 downto 0),
obus => D(23 downto 0),
loadport => LoadPortB,
loadddr => LoadDDRB,
readddr => ReadDDRB,
portdata => IOBITSB
);
iportb: Word24RB port map (
obus => D(23 downto 0),
readport => ReadPortB,
portdata => IOBitsB
);
pwmrefcount: pwmrefh port map (
clk => LClk,
hclk => FClk,
refcount => RefCountBus,
irqgen => IRQSource,
ibus => LAD(15 downto 0),
obus => D(15 downto 0),
irqdivload => LoadIRQDivCmd,
irqdivread => ReadIRQDivCmd,
phaseload => LoadPhaseCmd,
phaseread => ReadPhaseCmd
);
gLedreg: indexreg port map (
clk => LClk,
ibus => LAD(15 downto 0),
obus => D(15 downto 0),
loadindex => LoadLEDViewCmd,
readindex => ReadLEDViewCmd,
index => LEDView
);
ggcontrolreg: globalcontrolreg port map (
clk => LClk,
ibus => LAD(15 downto 0),
reset => '0',
loadgcr => LoadGCRCmd,
ctrclear => GlobalCounterClear,
ctrlatch => GlobalCountLatchCmd,
pwmclear => GlobalClearPWMCmd,
irqclear => ClearIRQCmd,
reloadwd => ReloadWDCmd
);
gglobalmodereg: globalmodereg port map (
clk => LClk,
ibus => LAD(15 downto 0),
obus => D(15 downto 0),
reset => '0',
loadglobalmode => loadGMRCmd,
readglobalmode => ReadGMRCmd,
ctrena => GlobalCounterEnable,
pwmena => GlobalPWMEnable,
clearpwmena => StopPWM,
loi => LatchOnInterrupt,
som => StopOnMissedIRQ,
sot => StopOnTimeout,
miout => ClearMissedIRQ,
miin => MissedIRQ,
irqmask => IRQMask,
irqstatus => IRQLatch
);
atimeout: timeout port map (
clk => LClk,
ibus => LAD(15 downto 0),
obus => D(15 downto 0),
timeoutload => loadTimeOutCmd,
timeoutread => ReadTimeOutCmd,
timerread => ReadTimerCmd,
reload => ReLoadWDCmd,
timerz => WDTimeout
);
aidreadback: idreadback
generic map (
id => HMID,
mc => MasterClock
)
port map(
readid => ReadIDCmd,
readmc => ReadMCCmd,
obus => D
);
CLKDLL_inst : CLKDLL
generic map (
CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,4.0,5.0,8.0 or 16.0
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
FACTORY_JF => X"C080", -- FACTORY JF Values
STARTUP_WAIT => FALSE) -- Delay config DONE until DLL LOCK, TRUE/FALSE
port map (
CLK0 => CLK0, -- 0 degree DLL CLK output
CLKFB =>FClk, -- DLL feedback
CLK2X => CLK2X, -- 2X DLL CLK output
CLKIN => SYNCLK, -- Clock input (from IBUFG, BUFG or DLL)
RST => '0' -- DLL asynchronous reset input
);
BUFG_inst : BUFG
port map (
O => FClk, -- Clock buffer output
I => CLK2X -- Clock buffer input
);
LADDrivers: process (D,FastRead)
begin
if FastRead ='1' then
LAD <= D;
else
LAD <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
end if;
end process LADDrivers;
AddressLatch: process (lclk)
begin
if lclk'event and LClk = '1' then
if ADS = '0' then
LatchedA <= LAD(15 downto 0);
LatchedLBE <= LBE;
end if;
end if;
end process AddressLatch;
-- we generate an early read from ADS and LR_W
-- since the 10 nS LRD delay and 5 nS setup time
-- only give us 15 nS to provide data to the PLX chip
MakeFastRead: process (lclk,PreFastread,LRD)
begin
if lclk'event and LClk = '1' then
if ADS = '0' and LW_R = '0'then
PreFastRead <= '1';
else
PreFastRead <= '0';
end if;
end if;
FastRead <= PreFastRead or (not LRD);
end process MakeFastRead;
Decode: process (LatchedA)
begin
if LatchedA(7 downto 5) = "000" then -- 32 bit access
CounterSel <= '1';
else
CounterSel <= '0';
end if;
if LatchedA(7 downto 5) = "001" then -- 32 bit access
SCounterSel <= '1';
else
SCounterSel <= '0';
end if;
if LatchedA(7 downto 4) = "0100" then -- 16 bit access
CCRSel <= '1';
else
CCRSel <= '0';
end if;
if LatchedA(7 downto 4) = "0101" then -- 16 bit access
SCCRSel <= '1';
else
SCCRSel <= '0';
end if;
if LatchedA(7 downto 5) = "011" then -- 16 bit access
PWMValSel <= '1';
else
PWMValSel <= '0';
end if;
if LatchedA(7 downto 5) = "100" then -- 16 bit access
PCRSel <= '1';
else
PCRSel <= '0';
end if;
if LatchedA(7 downto 2) = "101000" then -- 32 bit access
PortASel <= '1';
else
PortASel <= '0';
end if;
if LatchedA(7 downto 2) = "101001" then -- 32 bit access
DDRASel <= '1';
else
DDRASel <= '0';
end if;
if LatchedA(7 downto 2) = "101010" then -- 32 bit access
PortBSel <= '1';
else
PortBSel <= '0';
end if;
if LatchedA(7 downto 2) = "101011" then -- 32 bit access
DDRBSel <= '1';
else
DDRBSel <= '0';
end if;
if LatchedA(7 downto 2) = "110100" then -- 32 bit access D0
IDSel <= '1';
else
IDSel <= '0';
end if;
if LatchedA(7 downto 2) = "110101" then -- 32 bit access D4
MCSel <= '1';
else
MCSel <= '0';
end if;
if LatchedA(7 downto 1) = "1100000" then -- 16 bit access
GCRSel <= '1';
else
GCRSel <= '0';
end if;
if LatchedA(7 downto 1) = "1100001" then -- 16 bit access
GMRSel <= '1';
else
GMRSel <= '0';
end if;
if LatchedA(7 downto 1) = "1100010"then -- 16 bit access
IRQDivSel <= '1';
else
IRQDivSel <= '0';
end if;
if LatchedA(7 downto 1) = "1100011"then -- 16 bit access
PhaseSel <= '1';
else
PhaseSel <= '0';
end if;
if LatchedA(7 downto 1) = "1100100" then -- 16 bit access
TimeOutSel <= '1';
else
TimeOutSel <= '0';
end if;
if LatchedA(7 downto 1) = "1100101" then -- 16 bit access
TimerSel <= '1';
else
TimerSel <= '0';
end if;
if LatchedA(7 downto 1) = "1100110" then -- 16 bit access
LEDViewSel <= '1';
else
LEDViewSel <= '0';
end if;
end process;
SigsOut: process (EnaSigs)
begin
Ena <= EnaSigs;
end process;
CounterDecode: process (CounterSel, Fastread, LatchedA)
begin
if FastRead = '1' then
CounterRead <= OneOfFourDecode(CounterSel,LatchedA(3 downto 2));
else
CounterRead <= (others => '0');
end if;
end process;
SCounterDecode: process (SCounterSel, Fastread, LatchedA)
begin
if FastRead = '1' then
SCounterRead <= OneOfFourDecode(SCounterSel,LatchedA(3 downto 2));
else
SCounterRead <= (others => '0');
end if;
end process;
CCRegs: process (CCRSel, FastRead, LWR, LatchedA)
begin
if FastRead = '1' then
CCRReadCmds <= OneOfFourDecode(CCRSel,LatchedA(2 downto 1));
else
CCRReadCmds <= (others => '0');
end if;
if LWR = '0' then
CCRLoadCmds <= OneOfFourDecode(CCRSel,LatchedA(2 downto 1));
else
CCRLoadCmds <= (others => '0');
end if;
end process;
SCCRegs: process (SCCRSel, FastRead, LWR, LatchedA)
begin
if FastRead = '1' then
SCCRReadCmds <= OneOfFourDecode(SCCRSel,LatchedA(2 downto 1));
else
SCCRReadCmds <= (others => '0');
end if;
if LWR = '0' then
SCCRLoadCmds <= OneOfFourDecode(SCCRSel,LatchedA(2 downto 1));
else
SCCRLoadCmds <= (others => '0');
end if;
end process;
PWMdecode: process (PWMValSel,Fastread, LWR, LatchedA)
begin
if FastRead = '1' then
ReadPWM <= OneOfFourDecode(PWMValSel,LatchedA(2 downto 1));
else
ReadPWM <= (others => '0');
end if;
if LWR = '0' then
LoadPWM <= OneOfFourDecode(PWMValSel,LatchedA(2 downto 1));
else
LoadPWM <= (others => '0');
end if;
end process;
PCRegs: process (PCRSel,Fastread, LWR, LatchedA)
begin
if FastRead = '1' then
PCRReadCmds <= OneOfFourDecode(PCRSel,LatchedA(2 downto 1));
else
PCRReadCmds <= (others => '0');
end if;
if LWR = '0' then
PCRLoadCmds <= OneOfFourDecode(PCRSel,LatchedA(2 downto 1));
else
PCRLoadCmds <= (others => '0');
end if;
end process;
PortADecode: process (PortASel,FastRead,LWR)
begin
if PortASel = '1' and LWR = '0' then
LoadPortA <= '1';
else
LoadPortA <= '0';
end if;
if PortASel = '1' and FastRead = '1' then
ReadPortA <= '1';
else
ReadPortA <= '0';
end if;
end process PortADecode;
DDRADecode: process (DDRASel,FastRead,LWR)
begin
if DDRASel = '1' and LWR = '0' then
LoadDDRA <= '1';
else
LoadDDRA <= '0';
end if;
if DDRASel = '1' and FastRead = '1' then
ReadDDRA <= '1';
else
ReadDDRA <= '0';
end if;
end process DDRADecode;
PortBDecode: process (PortBSel,FastRead,LWR)
begin
if PortBSel = '1' and LWR = '0' then
LoadPortB <= '1';
else
LoadPortB <= '0';
end if;
if PortBSel = '1' and FastRead = '1' then
ReadPortB <= '1';
else
ReadPortB <= '0';
end if;
end process PortBDecode;
DDRBDecode: process (DDRBSel,FastRead,LWR)
begin
if DDRBSel = '1' and LWR = '0' then
LoadDDRB <= '1';
else
LoadDDRB <= '0';
end if;
if DDRBSel = '1' and FastRead = '1' then
ReadDDRB <= '1';
else
ReadDDRB <= '0';
end if;
end process DDRBDecode;
GCRDecode: process (GCRSel,LWR)
begin
if GCRSel = '1' and LWR = '0' then
LoadGCRCmd <= '1';
else
LoadGCRCmd <= '0';
end if;
end process GCRDecode;
GMRDecode: process (GMRSel,FastRead,LWR)
begin
if GMRSel = '1' and LWR = '0' then
LoadGMRCmd <= '1';
else
LoadGMRCmd <= '0';
end if;
if GMRSel = '1' and FastRead = '1' then
ReadGMRCmd <= '1';
else
ReadGMRCmd <= '0';
end if;
end process GMRDecode;
TimeOutDecode: process (TimeOutSel,FastRead,LWR)
begin
if TimeoutSel = '1' and LWR = '0' then
LoadTimeOutCmd <= '1';
else
LoadTimeOutCmd <= '0';
end if;
if TimeOutSel = '1' and FastRead = '1' then
ReadTimeOutCmd <= '1';
else
ReadTimeOutCmd <= '0';
end if;
end process TimeOutDecode;
TimerDecode: process (TimerSel,FastRead,LWR)
begin
if TimerSel = '1' and FastRead = '1' then
ReadTimerCmd <= '1';
else
ReadTimerCmd <= '0';
end if;
end process TimerDecode;
LEDViewDecode: process (LedViewSel,FastRead,LWR)
begin
if LEDViewSel = '1' and LWR = '0' then
LoadLEDViewCmd <= '1';
else
LoadLEDViewCmd <= '0';
end if;
if LEDViewSel = '1' and FastRead= '1' then
ReadLEDViewCmd <= '1';
else
ReadLEDViewCmd <= '0';
end if;
end process LEDViewDecode;
IRQDivDecode: process (IRQDivSel,FastRead,LWR)
begin
if IRQDivSel = '1' and LWR = '0' then
LoadIRQDivCmd <= '1';
else
LoadIRQDivCmd <= '0';
end if;
if IRQDivSel = '1' and FastRead = '1' then
ReadIRQDivCmd <= '1';
else
ReadIRQDivCmd <= '0';
end if;
end process IrqDivDecode;
PhaseDecode: process (PhaseSel,FastRead,LWR)
begin
if PhaseSel = '1' and LWR = '0' then
LoadPhaseCmd <= '1';
else
LoadPhaseCmd <= '0';
end if;
if PhaseSel = '1' and FastRead = '1' then
ReadPhaseCmd <= '1';
else
ReadPhaseCmd <= '0';
end if;
end process PhaseDecode;
IDDecode: process (IDSel,FastRead)
begin
if IDSel = '1' and FastRead = '1' then
ReadIDCmd <= '1';
else
ReadIDCmd <= '0';
end if;
end process IDDecode;
MCDecode: process (MCSel,FastRead)
begin
if MCSel = '1' and FastRead = '1' then
ReadMCCmd <= '1';
else
ReadMCCmd <= '0';
end if;
end process MCDecode;
irqlogic: process (CardSelect,
IRQSource,
IrqLatch,
ClearMissedIRQ,
MissedIRQ,
StopOnMissedIRQ,
LatchOnInterrupt,
GlobalCountLatchCmd,
GlobalClearPWMCmd,
ClearIRQCmd)
begin
if IrqSource'event and IRQsource = '1' then
IRQLatch <= '1';
if IRQLatch = '1' then -- if IRQLatch is set and we get the next interrupt
MissedIRQ <= '1'; -- set Missed IRQ latch
end if;
end if;
if LClk'event and LClk = '1' then
if ((IRQLatch = '1') and (LatchOnInterrupt = '1')) or (GlobalCountLatchCmd = '1') then
CountLatchEdge1 <= '1';
else
CountLatchEdge1 <= '0';
end if;
CountLatchEdge2 <= CountLatchEdge1;
if CountLatchEdge2 = '0' and CountLatchEdge1 = '1' then
GlobalCountLatch <= '1';
else
GlobalCountLatch <= '0';
end if;
end if;
if ClearMissedIRQ = '1' then
MissedIRQ <= '0';
end if;
if ((MissedIRQ = '1') and (StopOnMissedIRQ = '1')) or
((WDTimeOut = '1') and (StopOnTimeout = '1')) then
StopPWM <= '1';
else
StopPWM <= '0';
end if;
if (StopPWM = '1') or (GlobalClearPWMCmd = '1') then -- either stop on pwm or global clear reset pwm gens
GlobalClearPWM <= '1';
else
GlobalClearPWM <= '0';
end if;
if ClearIRQCmd = '1' then -- clear IRQ
IRQLatch <= '0';
end if;
Int <= not (IRQLatch and IRQMask); -- drive our (active low) interrupt pin
Ready <= '0'; -- We're always ready
end process;
LEDDrive: process (A,B,Idx,Dir,PWM,IRQLatch,LedView)
begin
LEDS(7) <= not IRQLatch;
LEDS(6) <= not OneOfFourMux(LEDView(1 downto 0),A);
LEDS(5) <= not OneOfFourMux(LEDView(1 downto 0),B);
LEDS(4) <= not OneOfFourMux(LEDView(1 downto 0),Idx);
LEDS(3) <= not OneOfFourMux(LEDView(1 downto 0),Dir);
LEDS(2) <= not OneOfFourMux(LEDView(1 downto 0),PWM);
LEDS(1) <= OneOfFourMux(LEDView(1 downto 0),EnaSigs);
LEDS(0) <= not WDTimeout;
end process leddrive;
end dataflow;
| lgpl-2.1 | 6ac02f681bf9df2bec3d668963571325 | 0.611687 | 2.973487 | false | false | false | false |
pwsoft/fpga_examples | quartus/chameleon2/chameleon2_life/pll50.vhd | 2 | 19,634 | -- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: pll50.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 17.0.2 Build 602 07/19/2017 SJ Lite Edition
-- ************************************************************
--Copyright (C) 2017 Intel Corporation. All rights reserved.
--Your use of Intel Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Intel Program License
--Subscription Agreement, the Intel Quartus Prime License Agreement,
--the Intel MegaCore Function License Agreement, or other
--applicable license agreement, including, without limitation,
--that your use is for the sole purpose of programming logic
--devices manufactured by Intel and sold by Intel or its
--authorized distributors. Please refer to the applicable
--agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY pll50 IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
c2 : OUT STD_LOGIC ;
c3 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END pll50;
ARCHITECTURE SYN OF pll50 IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire2_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire2 : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC ;
SIGNAL sub_wire6 : STD_LOGIC ;
SIGNAL sub_wire7 : STD_LOGIC ;
SIGNAL sub_wire8 : STD_LOGIC ;
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
clk2_divide_by : NATURAL;
clk2_duty_cycle : NATURAL;
clk2_multiply_by : NATURAL;
clk2_phase_shift : STRING;
clk3_divide_by : NATURAL;
clk3_duty_cycle : NATURAL;
clk3_multiply_by : NATURAL;
clk3_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
self_reset_on_loss_lock : STRING;
width_clock : NATURAL
);
PORT (
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
locked : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire2_bv(0 DOWNTO 0) <= "0";
sub_wire2 <= To_stdlogicvector(sub_wire2_bv);
sub_wire0 <= inclk0;
sub_wire1 <= sub_wire2(0 DOWNTO 0) & sub_wire0;
sub_wire7 <= sub_wire3(3);
sub_wire6 <= sub_wire3(2);
sub_wire5 <= sub_wire3(1);
sub_wire4 <= sub_wire3(0);
c0 <= sub_wire4;
c1 <= sub_wire5;
c2 <= sub_wire6;
c3 <= sub_wire7;
locked <= sub_wire8;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 1,
clk0_duty_cycle => 50,
clk0_multiply_by => 2,
clk0_phase_shift => "0",
clk1_divide_by => 1,
clk1_duty_cycle => 50,
clk1_multiply_by => 2,
clk1_phase_shift => "0",
clk2_divide_by => 1,
clk2_duty_cycle => 50,
clk2_multiply_by => 3,
clk2_phase_shift => "0",
clk3_divide_by => 1,
clk3_duty_cycle => 50,
clk3_multiply_by => 3,
clk3_phase_shift => "4167",
compensate_clock => "CLK0",
inclk0_input_frequency => 20000,
intended_device_family => "Cyclone 10 LP",
lpm_hint => "CBX_MODULE_PREFIX=pll50",
lpm_type => "altpll",
operation_mode => "SOURCE_SYNCHRONOUS",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_USED",
port_clk3 => "PORT_USED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
self_reset_on_loss_lock => "OFF",
width_clock => 5
)
PORT MAP (
inclk => sub_wire1,
clk => sub_wire3,
locked => sub_wire8
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "100.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "100.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "150.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "150.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "2"
-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "3"
-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "3"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "200.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "150.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "150.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "225.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll50.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK3 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "3"
-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "3"
-- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "4167"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SOURCE_SYNCHRONOUS"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
-- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
-- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll50.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll50.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll50.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll05.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll50.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll50_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
| lgpl-2.1 | 8b7b368e1bc1366b843ae6ffe23b45e8 | 0.700825 | 3.269064 | false | false | false | false |
pwsoft/fpga_examples | rtl/designs/gigatron/gigatron_ram.vhd | 1 | 2,168 | -- -----------------------------------------------------------------------
--
-- Turbo Chameleon
--
-- Multi purpose FPGA expansion for the Commodore 64 computer
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2021 by Peter Wendrich ([email protected])
-- http://www.syntiac.com/chameleon.html
--
-- This source file is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- -----------------------------------------------------------------------
--
-- Part of the Gigatron emulator.
-- SRAM emulation mapped to FPGA blockram.
--
-- -----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- -----------------------------------------------------------------------
entity gigatron_ram is
generic (
abits : integer := 15;
dbits : integer := 8
);
port (
clk : in std_logic;
we : in std_logic;
a : in unsigned(abits-1 downto 0);
d : in unsigned(dbits-1 downto 0);
q : out unsigned(dbits-1 downto 0)
);
end entity;
-- -----------------------------------------------------------------------
architecture rtl of gigatron_ram is
constant ramsize : integer := 2**abits;
type ram_t is array(0 to ramsize-1) of unsigned(d'range);
signal ram_reg : ram_t := (others => (others => '0'));
signal q_reg : unsigned(q'range);
begin
q <= q_reg;
process(clk)
begin
if rising_edge(clk) then
if we = '1' then
ram_reg(to_integer(a)) <= d;
end if;
q_reg <= ram_reg(to_integer(a));
end if;
end process;
end architecture;
| lgpl-2.1 | 052fb266e664c13679d75fc0aa9c8893 | 0.550277 | 3.941818 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/esa/memoryctrl/memoryctrl.vhd | 1 | 2,716 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
-- Entity: memctrl
-- File: memctrl.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Memory controller package
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library gaisler;
use gaisler.memctrl.all;
package memoryctrl is
component mctrl
generic (
hindex : integer := 0;
pindex : integer := 0;
romaddr : integer := 16#000#;
rommask : integer := 16#E00#;
ioaddr : integer := 16#200#;
iomask : integer := 16#E00#;
ramaddr : integer := 16#400#;
rammask : integer := 16#C00#;
paddr : integer := 0;
pmask : integer := 16#fff#;
wprot : integer := 0;
invclk : integer := 0;
fast : integer := 0;
romasel : integer := 28;
sdrasel : integer := 29;
srbanks : integer := 4;
ram8 : integer := 0;
ram16 : integer := 0;
sden : integer := 0;
sepbus : integer := 0;
sdbits : integer := 32;
sdlsb : integer := 2;
oepol : integer := 0;
syncrst : integer := 0;
pageburst : integer := 0;
scantest : integer := 0;
mobile : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
memi : in memory_in_type;
memo : out memory_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
wpo : in wprot_out_type;
sdo : out sdram_out_type
);
end component;
end;
| gpl-3.0 | 6ec0de41605ee6ba34004f63ecd6a2c6 | 0.555228 | 3.930535 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/techmap/virtex/clkgen_virtex.vhd | 1 | 21,692 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: various
-- File: clkgen_xilinx.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Author: Richard Pender, Pender Electronic Design
-- Description: Clock generators for Virtex and Virtex-2 fpgas
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library grlib;
use grlib.stdlib.all;
library unisim;
use unisim.BUFG;
use unisim.CLKDLL;
use unisim.BUFGDLL;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity clkgen_virtex is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
noclkfb : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0);
port (
clkin : in std_logic;
pciclkin: in std_logic;
clk : out std_logic; -- main clock
clkn : out std_logic; -- inverted main clock
clk2x : out std_logic; -- double clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type
);
end;
architecture rtl of clkgen_virtex is
component BUFG port (O : out std_logic; I : in std_logic); end component;
component CLKDLL
port (
CLK0 : out std_ulogic;
CLK180 : out std_ulogic;
CLK270 : out std_ulogic;
CLK2X : out std_ulogic;
CLK90 : out std_ulogic;
CLKDV : out std_ulogic;
LOCKED : out std_ulogic;
CLKFB : in std_ulogic;
CLKIN : in std_ulogic;
RST : in std_ulogic);
end component;
component BUFGDLL port (O : out std_logic; I : in std_logic); end component;
signal gnd, clk_i, clk_j, clk_k, dll0rst, dll0lock, dll1lock : std_logic;
signal dll1rst : std_logic_vector(0 to 3);
signal clk0B, clkint, CLK2XL, CLKDV, CLK180, pciclkint : std_logic;
begin
gnd <= '0'; clk <= clk_i; clkn <= not clk_i;
c0 : if (PCISYSCLK = 0) or (PCIEN = 0) generate
clkint <= clkin;
end generate;
c2 : if PCIEN /= 0 generate
pciclkint <= pciclkin;
p3 : if PCISYSCLK = 1 generate clkint <= pciclkint; end generate;
p0 : if PCIDLL = 1 generate
x1 : BUFGDLL port map (I => pciclkint, O => pciclk);
end generate;
p1 : if PCIDLL = 0 generate
x1 : BUFG port map (I => pciclkint, O => pciclk);
end generate;
end generate;
c3 : if PCIEN = 0 generate
pciclk <= '0';
end generate;
bufg0 : BUFG port map (I => clk0B, O => clk_i);
bufg1 : BUFG port map (I => clk_j, O => clk_k);
dll0rst <= not cgi.pllrst;
dll0 : CLKDLL
port map (CLKIN => clkint, CLKFB => clk_k, CLK0 => clk_j, CLK180 => CLK180,
CLK2X => CLK2XL, CLKDV => CLKDV, LOCKED => dll0lock, RST => dll0rst);
clk0B <= CLK2XL when clk_mul/clk_div = 2
else CLKDV when clk_div/clk_mul = 2 else clk_j;
sd0 : if (SDRAMEN /= 0) and (NOCLKFB = 0) generate
cgo.clklock <= dll1lock;
dll1 : CLKDLL
port map (CLKIN => clk_i, CLKFB => cgi.pllref, RST => dll1rst(0), CLK0 => sdclk,
CLK2X => clk2x, LOCKED => dll1lock);
rstdel : process (clk_i)
begin
if dll0lock = '0' then dll1rst <= (others => '1');
elsif rising_edge(clk_i) then
dll1rst <= dll1rst(1 to 3) & '0';
end if;
end process;
end generate;
sd1 : if not ((SDRAMEN /= 0) and (NOCLKFB = 0)) generate
sdclk <= clk_i; cgo.clklock <= dll0lock;
end generate;
cgo.pcilock <= '1';
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library grlib;
use grlib.stdlib.all;
library unisim;
use unisim.IBUFG;
use unisim.BUFG;
use unisim.DCM;
use unisim.BUFGDLL;
use unisim.BUFGMUX;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
------------------------------------------------------------------
-- Virtex2 clock generator ---------------------------------------
------------------------------------------------------------------
entity clkgen_virtex2 is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
noclkfb : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000; -- clock frequency in KHz
clk2xen : integer := 0;
clksel : integer := 0); -- enable clock select
port (
clkin : in std_ulogic;
pciclkin: in std_ulogic;
clk : out std_ulogic; -- main clock
clkn : out std_ulogic; -- inverted main clock
clk2x : out std_ulogic; -- double clock
sdclk : out std_ulogic; -- SDRAM clock
pciclk : out std_ulogic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clk1xu : out std_ulogic; -- unscaled clock
clk2xu : out std_ulogic -- unscaled 2X clock
);
end;
architecture struct of clkgen_virtex2 is
component BUFG port (O : out std_logic; I : in std_logic); end component;
component IBUFG port (O : out std_logic; I : in std_logic); end component;
component BUFGMUX port ( O : out std_ulogic; I0 : in std_ulogic;
I1 : in std_ulogic; S : in std_ulogic);
end component;
component DCM
generic (
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false
);
port (
CLKFB : in std_logic;
CLKIN : in std_logic;
DSSEN : in std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector (7 downto 0));
end component;
component BUFGDLL port (O : out std_logic; I : in std_logic); end component;
constant VERSION : integer := 1;
--constant CLKIN_PERIOD_ST : string := "20.0";
--attribute CLKIN_PERIOD : string;
--attribute CLKIN_PERIOD of dll0: label is CLKIN_PERIOD_ST;
signal gnd, clk_i, clk_j, clk_k, clk_l, clk_m, clk_x, clk_n, clk_o, clk_p, clk_i2, clk_sd, clk_r, dll0rst, dll0lock, dll1lock, dll2xlock : std_logic;
signal dll1rst, dll2xrst : std_logic_vector(0 to 3);
signal clk0B, clkint, pciclkint, pciclkl, pciclkfb, pciclk0 : std_logic;
begin
gnd <= '0';
clk <= clk_i when (CLK2XEN = 0) else clk_p;
clkn <= clk_m; clk2x <= clk_i2;
c0 : if (PCISYSCLK = 0) or (PCIEN = 0) generate
clkint <= clkin;
end generate;
c2 : if PCIEN /= 0 generate
pciclkint <= pciclkin;
p3 : if PCISYSCLK = 1 generate clkint <= pciclkint; end generate;
p0 : if PCIDLL = 1 generate
x1 : BUFGDLL port map (I => pciclkint, O => pciclk);
end generate;
p1 : if PCIDLL = 0 generate
x1 : BUFG port map (I => pciclkint, O => pciclk);
end generate;
p2 : if (PCIDLL /= 0) and ( PCIDLL /= 1) generate
x1 : IBUFG port map (I => pciclkint, O => pciclkl);
dll0 : DCM
generic map (CLKOUT_PHASE_SHIFT => "FIXED", PHASE_SHIFT => PCIDLL)
port map ( CLKIN => pciclkint, CLKFB => pciclkfb,
DSSEN => gnd, PSCLK => gnd,
RST => gnd, PSEN => gnd, PSINCDEC => gnd, CLK0 => pciclk0);
x2 : BUFG port map (I => pciclk0, O => pciclkfb);
pciclk <= pciclkfb;
end generate;
end generate;
c3 : if PCIEN = 0 generate
pciclk <= '0';
end generate;
clk1xu <= clk_k;
clk2xu <= clk_x;
bufg0 : BUFG port map (I => clk0B, O => clk_i);
bufg1 : BUFG port map (I => clk_j, O => clk_k);
bufg2 : BUFG port map (I => clk_l, O => clk_m);
buf34gen : if (CLK2XEN /= 0) generate
cs0 : if (clksel = 0) generate
bufg3 : BUFG port map (I => clk_n, O => clk_i2);
end generate;
cs1 : if (clksel /= 0) generate
bufg3 : BUFGMUX port map (S => cgi.clksel(0), I0 => clk_o, I1 => clk_n, O => clk_i2);
end generate;
bufg4 : BUFG port map (I => clk_o, O => clk_p);
end generate;
dll0rst <= not cgi.pllrst;
dll0 : DCM
generic map (CLKFX_MULTIPLY => clk_mul, CLKFX_DIVIDE => clk_div)
port map ( CLKIN => clkint, CLKFB => clk_k, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst, CLK0 => clk_j,
CLKFX => clk0B, CLK2X => clk_x, CLKFX180 => clk_l, LOCKED => dll0lock);
clk2xgen : if (CLK2XEN /= 0) generate
dll2x : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2)
port map ( CLKIN => clk_i, CLKFB => clk_p, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll2xrst(0), CLK0 => clk_o,
CLK2X => clk_n, LOCKED => dll2xlock);
rstdel2x : process (clk_i, dll0lock)
begin
if dll0lock = '0' then dll2xrst <= (others => '1');
elsif rising_edge(clk_i) then
dll2xrst <= dll2xrst(1 to 3) & '0';
end if;
end process;
end generate;
clk_sd1 : if (CLK2XEN = 0) generate
bufg3 : BUFG port map (I => clk_x, O => clk_i2);
dll2xlock <= dll0lock;
clk_sd <= clk_i;
end generate;
clk_sd2 : if (CLK2XEN = 1) generate clk_sd <= clk_p; end generate;
clk_sd3 : if (CLK2XEN = 2) generate clk_sd <= clk_i2; end generate;
sd0 : if (SDRAMEN /= 0) and (NOCLKFB=0) generate
cgo.clklock <= dll1lock;
dll1 : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2)
port map ( CLKIN => clk_sd, CLKFB => cgi.pllref, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll1rst(0), CLK0 => sdclk, --CLK2X => clk2x,
LOCKED => dll1lock);
rstdel : process (clk_sd, dll2xlock)
begin
if dll2xlock = '0' then dll1rst <= (others => '1');
elsif rising_edge(clk_sd) then
dll1rst <= dll1rst(1 to 3) & '0';
end if;
end process;
end generate;
sd1 : if ((SDRAMEN = 0) or (NOCLKFB = 1)) and (CLK2XEN /= 2) generate
sdclk <= clk_i;
cgo.clklock <= dll0lock when (CLK2XEN = 0) else dll2xlock;
end generate;
sd1_2x : if ((SDRAMEN = 0) or (NOCLKFB = 1)) and (CLK2XEN = 2) generate
sdclk <= clk_i2;
cgo.clklock <= dll2xlock;
end generate;
cgo.pcilock <= '1';
-- pragma translate_off
bootmsg : report_version
generic map (
"clkgen_virtex2" & ": virtex-2 sdram/pci clock generator, version " & tost(VERSION),
"clkgen_virtex2" & ": Frequency " & tost(freq) & " KHz, DCM divisor " & tost(clk_mul) & "/" & tost(clk_div));
-- pragma translate_on
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library grlib;
use grlib.stdlib.all;
library unisim;
use unisim.BUFG;
use unisim.DCM;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity clkmul_virtex2 is
generic ( clk_mul : integer := 2 ; clk_div : integer := 2);
port (
resetin : in std_logic;
clkin : in std_logic;
clk : out std_logic;
resetout: out std_logic
);
end;
architecture struct of clkmul_virtex2 is
-- attribute CLKFX_MULTIPLY : string;
-- attribute CLKFX_DIVIDE : string;
-- attribute CLKIN_PERIOD : string;
--
-- attribute CLKFX_MULTIPLY of dll0: label is "5";
-- attribute CLKFX_DIVIDE of dll0: label is "4";
-- attribute CLKIN_PERIOD of dll0: label is "20";
--
-- attribute CLKFX_MULTIPLY of dll1: label is "4";
-- attribute CLKFX_DIVIDE of dll1: label is "4";
-- attribute CLKIN_PERIOD of dll1: label is "25";
--
component DCM
generic (
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false
);
port (
CLKFB : in std_logic;
CLKIN : in std_logic;
DSSEN : in std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector (7 downto 0));
end component;
component BUFG port ( O : out std_logic; I : in std_logic); end component;
signal gnd, clk_i, clk_j, clk_k, clk_l : std_logic;
signal clk0B, clk_FB, dll0rst, lock : std_logic;
begin
gnd <= '0'; clk <= clk_i;
dll0rst <= not resetin;
bufg0 : BUFG port map (I => clk0B, O => clk_i);
bufg1 : BUFG port map (I => clk_j, O => clk_k);
dll0 : DCM
generic map (CLKFX_MULTIPLY => clk_mul, CLKFX_DIVIDE => clk_div)
port map ( CLKIN => clkin, CLKFB => clk_k, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst, CLK0 => clk_j,
LOCKED => resetout, CLKFX => clk0B );
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library grlib;
use grlib.stdlib.all;
library unisim;
use unisim.BUFG;
use unisim.DCM;
use unisim.BUFGDLL;
use unisim.BUFGMUX;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity clkgen_spartan3 is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
noclkfb : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 50000; -- clock frequency in KHz
clk2xen : integer := 0;
clksel : integer := 0); -- enable clock select
port (
clkin : in std_ulogic;
pciclkin: in std_ulogic;
clk : out std_ulogic; -- main clock
clkn : out std_ulogic; -- inverted main clock
clk2x : out std_ulogic; -- double clock
sdclk : out std_ulogic; -- SDRAM clock
pciclk : out std_ulogic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clk1xu : out std_ulogic; -- unscaled clock
clk2xu : out std_ulogic -- unscaled 2X clock
);
end;
architecture struct of clkgen_spartan3 is
component BUFG port (O : out std_logic; I : in std_logic); end component;
component BUFGMUX port ( O : out std_ulogic; I0 : in std_ulogic;
I1 : in std_ulogic; S : in std_ulogic);
end component;
component DCM
generic (
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false
);
port (
CLKFB : in std_logic;
CLKIN : in std_logic;
DSSEN : in std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector (7 downto 0));
end component;
component BUFGDLL port (O : out std_logic; I : in std_logic); end component;
constant VERSION : integer := 1;
--constant CLKIN_PERIOD_ST : string := "20.0";
--attribute CLKIN_PERIOD : string;
--attribute CLKIN_PERIOD of dll0: label is CLKIN_PERIOD_ST;
signal gnd, clk_i, clk_j, clk_k, clk_l, clk_m, clk_x, clk_n, clk_o, clk_p, clk_i2, clk_sd, clk_r, dll0rst, dll0lock, dll1lock, dll2xlock : std_logic;
signal dll1rst, dll2xrst : std_logic_vector(0 to 3);
signal clk0B, clkint, pciclkint : std_logic;
begin
gnd <= '0';
clk <= clk_i when (CLK2XEN = 0) else clk_p;
clkn <= not clk_i when (CLK2XEN = 0) else not clk_p;
clk2x <= clk_i2;
c0 : if (PCISYSCLK = 0) or (PCIEN = 0) generate
clkint <= clkin;
end generate;
c2 : if PCIEN /= 0 generate
pciclkint <= pciclkin;
p3 : if PCISYSCLK = 1 generate clkint <= pciclkint; end generate;
p0 : if PCIDLL = 1 generate
x1 : BUFGDLL port map (I => pciclkint, O => pciclk);
end generate;
p1 : if PCIDLL = 0 generate
x1 : BUFG port map (I => pciclkint, O => pciclk);
end generate;
end generate;
c3 : if PCIEN = 0 generate
pciclk <= '0';
end generate;
clk1xu <= clk_j;
clk2xu <= clk_k;
bufg0 : BUFG port map (I => clk0B, O => clk_i);
bufg1 : BUFG port map (I => clk_x, O => clk_k);
buf34gen : if (CLK2XEN /= 0) generate
cs0 : if (clksel = 0) generate
bufg3 : BUFG port map (I => clk_n, O => clk_i2);
end generate;
cs1 : if (clksel /= 0) generate
bufg3 : BUFGMUX port map (S => cgi.clksel(0), I0 => clk_o, I1 => clk_n, O => clk_i2);
end generate;
bufg4 : BUFG port map (I => clk_o, O => clk_p);
end generate;
dll0rst <= not cgi.pllrst;
dll0 : DCM
generic map (CLKFX_MULTIPLY => clk_mul, CLKFX_DIVIDE => clk_div,
CLK_FEEDBACK => "2X")
port map ( CLKIN => clkint, CLKFB => clk_k, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst, CLK0 => clk_j,
CLKFX => clk0B, CLK2X => clk_x, CLKFX180 => clk_l, LOCKED => dll0lock);
clk2xgen : if (CLK2XEN /= 0) generate
dll2x : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2)
port map ( CLKIN => clk_i, CLKFB => clk_p, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll2xrst(0), CLK0 => clk_o,
CLK2X => clk_n, LOCKED => dll2xlock);
rstdel2x : process (clk_i, dll0lock)
begin
if dll0lock = '0' then dll2xrst <= (others => '1');
elsif rising_edge(clk_i) then
dll2xrst <= dll2xrst(1 to 3) & '0';
end if;
end process;
end generate;
clk_sd1 : if (CLK2XEN = 0) generate
clk_i2 <= clk_k;
dll2xlock <= dll0lock;
clk_sd <= clk_i;
end generate;
clk_sd2 : if (CLK2XEN = 1) generate clk_sd <= clk_p; end generate;
clk_sd3 : if (CLK2XEN = 2) generate clk_sd <= clk_i2; end generate;
sd0 : if (SDRAMEN /= 0) and (NOCLKFB=0) generate
cgo.clklock <= dll1lock;
dll1 : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2)
port map ( CLKIN => clk_sd, CLKFB => cgi.pllref, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll1rst(0), CLK0 => sdclk, --CLK2X => clk2x,
LOCKED => dll1lock);
rstdel : process (clk_sd, dll2xlock)
begin
if dll2xlock = '0' then dll1rst <= (others => '1');
elsif rising_edge(clk_sd) then
dll1rst <= dll1rst(1 to 3) & '0';
end if;
end process;
end generate;
sd1 : if ((SDRAMEN = 0) or (NOCLKFB = 1)) and (CLK2XEN /= 2) generate
sdclk <= clk_i;
cgo.clklock <= dll0lock when (CLK2XEN = 0) else dll2xlock;
end generate;
sd1_2x : if ((SDRAMEN = 0) or (NOCLKFB = 1)) and (CLK2XEN = 2) generate
sdclk <= clk_i2;
cgo.clklock <= dll2xlock;
end generate;
cgo.pcilock <= '1';
-- pragma translate_off
bootmsg : report_version
generic map (
"clkgen_spartan3e" & ": spartan3/e sdram/pci clock generator, version " & tost(VERSION),
"clkgen_spartan3e" & ": Frequency " & tost(freq) & " KHz, DCM divisor " & tost(clk_mul) & "/" & tost(clk_div));
-- pragma translate_on
end;
| gpl-3.0 | c565a8a141903524e55760fb762d59e4 | 0.58676 | 3.281694 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/techmap/maps/serdes.vhd | 1 | 9,506 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: serdes
-- File: serdes.vhd
-- Author: Andrea Gianarro - Aeroflex Gaisler AB
-- Description: SGMII Gigabit Ethernet PMA Physical Media Attachment
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
library grlib;
use grlib.config.all;
use grlib.config_types.all;
entity serdes is
generic (
fabtech : integer;
transtech : integer
);
port (
clk_125 : in std_logic;
rst_125 : in std_logic;
rx_in_p : in std_logic; -- SER IN
rx_in_n : in std_logic; -- SER IN
rx_out : out std_logic_vector(9 downto 0); -- PAR OUT
rx_clk : out std_logic;
rx_rstn : out std_logic;
rx_pll_clk : out std_logic;
rx_pll_rstn : out std_logic;
tx_pll_clk : out std_logic;
tx_pll_rstn : out std_logic;
tx_in : in std_logic_vector(9 downto 0) ; -- PAR IN
tx_out_p : out std_logic; -- SER OUT
tx_out_n : out std_logic; -- SER OUT
bitslip : in std_logic;
-- added for igloo2_serdes
apbin : in apb_in_serdes;
apbout : out apb_out_serdes;
m2gl_padin : in pad_in_serdes;
m2gl_padout : out pad_out_serdes;
serdes_clk125 : out std_logic;
serdes_ready: out std_logic);
end;
architecture rtl of serdes is
component serdes_stratixiii is
port (
clk_125 : in std_logic;
rst_125 : in std_logic;
rx_in : in std_logic; -- SER IN
rx_out : out std_logic_vector(9 downto 0); -- PAR OUT
rx_clk : out std_logic;
rx_rstn : out std_logic;
rx_pll_clk : out std_logic;
rx_pll_rstn : out std_logic;
tx_pll_clk : out std_logic;
tx_pll_rstn : out std_logic;
tx_in : in std_logic_vector(9 downto 0) ; -- PAR IN
tx_out : out std_logic; -- SER OUT
bitslip : in std_logic
);
end component;
component igloo2_serdes is
generic(
transtech : integer := m010);
port(
apb_in : in apb_in_serdes;
apb_out : out apb_out_serdes;
insig : in sigin_serdes_type;
outsig : out sigout_serdes_type;
padin : in pad_in_serdes;
padout : out pad_out_serdes);
end component;
component rtg4_serdes is
generic(
transtech : integer := m010);
port(
apb_in : in apb_in_serdes;
apb_out : out apb_out_serdes;
insig : in sigin_serdes_type;
outsig : out sigout_serdes_type;
padin : in pad_in_serdes;
padout : out pad_out_serdes);
end component;
component serdes_unisim is
generic (
transtech : integer
);
port (
clk_125 : in std_logic;
rst_125 : in std_logic;
rx_in_p : in std_logic; -- SER IN
rx_in_n : in std_logic; -- SER IN
rx_out : out std_logic_vector(9 downto 0); -- PAR OUT
rx_clk : out std_logic;
rx_rstn : out std_logic;
rx_pll_clk : out std_logic;
rx_pll_rstn : out std_logic;
tx_pll_clk : out std_logic;
tx_pll_rstn : out std_logic;
tx_in : in std_logic_vector(9 downto 0) ; -- PAR IN
tx_out_p : out std_logic; -- SER OUT
tx_out_n : out std_logic; -- SER OUT
bitslip : in std_logic
);
end component;
signal rst_125n, rx_clk_serdes, rx_rstn_serdes, rx_val_serdes, tx_rstn_serdes, tx_clk_lock_serdes, tx_pll_clk_sig, rx_idle, ready_sig : std_logic;
signal tx_out_p_int : std_logic;
signal r0, r1 : std_logic_vector(4 downto 0);
begin
str : if (fabtech = stratix3) or (fabtech = stratix4) generate
str0 : serdes_stratixiii
port map (clk_125, rst_125, rx_in_p, rx_out, rx_clk, rx_rstn, rx_pll_clk, rx_pll_rstn, tx_pll_clk, tx_pll_rstn, tx_in, tx_out_p_int, bitslip);
apbout <= apb_out_serdes_none; m2gl_padout <= pad_out_serdes_none; serdes_clk125 <= '0'; serdes_ready <= '1'; -- not used
tx_out_n <= not tx_out_p_int; -- not used
tx_out_p <= tx_out_p_int;
end generate;
xilinx : if (fabtech = virtex5) or (fabtech = virtex6) generate
xil0 : serdes_unisim
generic map (transtech)
port map (clk_125, rst_125, rx_in_p, rx_in_n, rx_out, rx_clk, rx_rstn, rx_pll_clk, rx_pll_rstn, tx_pll_clk, tx_pll_rstn, tx_in, tx_out_p, tx_out_n, bitslip);
apbout <= apb_out_serdes_none; m2gl_padout <= pad_out_serdes_none; serdes_clk125 <= '0'; serdes_ready <= '1'; -- not used
end generate;
igl2 : if (fabtech = igloo2) generate
rst_125n <= not(rst_125); -- used as SERDES macro reset
rx_clk <= rx_clk_serdes;
rx_pll_clk <= rx_clk_serdes;
-- reset synchronizers
rxrst0 : process (rx_clk_serdes, rx_rstn_serdes) begin
if rising_edge(rx_clk_serdes) then
r0 <= r0(3 downto 0) & rx_val_serdes;
rx_rstn <= r0(4) and r0(3) and r0(2);
rx_pll_rstn <= r0(4) and r0(3) and r0(2);
end if;
if (rx_rstn_serdes = '0') then r0 <= "00000"; rx_rstn <= '0'; rx_pll_rstn <= '0'; end if;
end process;
txrst : process (tx_pll_clk_sig, tx_rstn_serdes) begin
if rising_edge(tx_pll_clk_sig) then
r1 <= r1(3 downto 0) & tx_clk_lock_serdes;
tx_pll_rstn <= r1(4) and r1(3) and r1(2);
end if;
if (tx_rstn_serdes = '0') then r1 <= "00000"; tx_pll_rstn <= '0'; end if;
end process;
tx_out_p <= '0'; -- not used
tx_out_n <= '0'; -- not used
tx_pll_clk <= tx_pll_clk_sig;
igl20 : igloo2_serdes
generic map (transtech)
port map (
apb_in => apbin,
apb_out => apbout,
padin => m2gl_padin,
padout => m2gl_padout,
insig.rstn => rst_125n,
insig.tx_data => tx_in,
outsig.ready => ready_sig, -- not used
outsig.rx_clk => rx_clk_serdes,
outsig.rx_data => rx_out,
outsig.rx_idle => rx_idle, -- not used
outsig.rx_rstn => rx_rstn_serdes,
outsig.rx_val => rx_val_serdes,
outsig.tx_clk => tx_pll_clk_sig,
outsig.tx_clk_lock => tx_clk_lock_serdes,
outsig.tx_rstn => tx_rstn_serdes,
outsig.refclk => serdes_clk125);
serdes_ready <= rx_val_serdes;
end generate;
rt4 : if (fabtech = rtg4) generate
rst_125n <= not(rst_125); -- used as SERDES macro reset
rx_clk <= rx_clk_serdes;
rx_pll_clk <= rx_clk_serdes;
-- reset synchronizers
rxrst0 : process (rx_clk_serdes) begin
if rising_edge(rx_clk_serdes) then
r0 <= r0(3 downto 0) & not(rx_idle);
rx_rstn <= r0(4) and r0(3) and r0(2);
rx_pll_rstn <= r0(4) and r0(3) and r0(2);
if (rx_rstn_serdes = '0') then r0 <= "00000"; rx_rstn <= '0'; rx_pll_rstn <= '0'; end if;
end if;
end process;
txrst : process (tx_pll_clk_sig) begin
if rising_edge(tx_pll_clk_sig) then
r1 <= r1(3 downto 0) & tx_clk_lock_serdes;
tx_pll_rstn <= r1(4) and r1(3) and r1(2);
if (tx_rstn_serdes = '0') then r1 <= "00000"; tx_pll_rstn <= '0'; end if;
end if;
end process;
tx_out_p <= '0'; -- not used
tx_out_n <= '0'; -- not used
tx_pll_clk <= tx_pll_clk_sig;
rt40 : rtg4_serdes
generic map (transtech)
port map (
apb_in => apbin,
apb_out => apbout,
padin => m2gl_padin,
padout => m2gl_padout,
insig.rstn => rst_125n,
insig.tx_data => tx_in,
outsig.ready => ready_sig, -- not used
outsig.rx_clk => rx_clk_serdes,
outsig.rx_data => rx_out,
outsig.rx_idle => rx_idle,
outsig.rx_rstn => rx_rstn_serdes,
outsig.rx_val => rx_val_serdes,
outsig.tx_clk => tx_pll_clk_sig,
outsig.tx_clk_lock => tx_clk_lock_serdes,
outsig.tx_rstn => tx_rstn_serdes,
outsig.refclk => serdes_clk125);
serdes_ready <= rx_val_serdes;
end generate;
-- pragma translate_off
nofifo : if (has_transceivers(fabtech) = 0) generate
x : process
begin
assert false report "serdes: technology " & tech_table(fabtech) &
" not supported"
severity failure;
wait;
end process;
end generate;
dmsg : if GRLIB_CONFIG_ARRAY(grlib_debug_level) >= 2 generate
x : process
begin
assert false report "serdes: (" & tech_table(fabtech) & ")"
severity note;
wait;
end process;
end generate;
-- pragma translate_on
end;
| gpl-3.0 | 60c65911bfd01f6c418fb527259b75a3 | 0.56943 | 3.223466 | false | false | false | false |
ARC-Lab-UF/UAA | src/uaa.vhd | 1 | 10,041 | -- Copyright (c) 2015 University of Florida
--
-- This file is part of uaa.
--
-- uaa is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- uaa is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with uaa. If not, see <http://www.gnu.org/licenses/>.
-- Greg Stitt
-- University of Florida
-- Description:
-- This entity implements a pipelined, floating-point accumulator with generics
-- that select between different accumulator architectures, different adder
-- architectures, any number of inputs per cycle, and whether or not to
-- use block. Valid architectures are listed in uaa_pkg.vhd and are
-- described in the corresponding paper.
-- Notes:
-- See README before instantiating this entity. uaa requires
-- an existing adder core, a mapping onto an adder wrapper (add_flt), and
-- adder latencies (add_flt_pkg.vhd).
-- Used entities:
-- add_tree_flt
-- delay
-- dsa, fcbt, sga
library ieee;
use ieee.std_logic_1164.all;
use work.uaa_pkg.all;
use work.add_tree_flt_pkg.all;
-------------------------------------------------------------------------------
-- Generics Description
-- arch : Specifies the type of architecture to use. All possible
-- options are included in uaa_pkg.vhd
-- width : The width of the input and output in bits (e.g., 32 bits
-- for single precision, 64 for double)
-- parallel_inputs : The number of inputs provided in parallel as input. For
-- example, if a design can provide 4 inputs every cycle,
-- this should be 4 to maximize throughput.
-- add_core_name : A string representing different optimizations for the
-- actual adder core. See add_flt.vhd and flt_pkg.vhd for
-- more information.
-- use_bram : attempts to use bram when true, uses LUTs or FFs when
-- false
-- FCBT_max_inputs : Specifies the maximum number of inputs for the
-- FCBT architecture. This generic is ignored for other
-- architectures, which support any number of inputs.
-- FCBT_obuf_size : Specifies the size of the output buffer for the
-- FCBT architecture. This generic is ignored for other
-- architectures, which support any number of inputs.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Port Description:
-- clk : clock input
-- rst : reset input (asynchronous, active high)
-- hold_output : The user can assert this signal to prevent the entity from
-- continuing past a valid output. When hold_output is not
-- asserted, the output is valid for only a single cycle.
-- This signal makes it possible to stall the entity if
-- downstream components can't receive data (active high)
-- ready : The entity asserts this signal when it is ready to accept
-- new inputs. If not, asserted, external components must hold
-- the current input or it will be lost (active high)
-- end_of_group : User should be assert on the same cycle as the last input in a
-- group (active high)
-- input : Provides parallel_inputs number of width-bit inputs
-- output : Accumulated output
-- valid_in : User should assert when input is valid and ready is
-- asserted (active high)
-- valid_out : Entity asserts when the output from the dsa is valid. Unless
-- the user asserts hold_output, the entity only asserts
-- valid_out is only asserted for one cycle. (active high)
-------------------------------------------------------------------------------
entity uaa is
generic (
arch : arch_type := UAA_SGA;
width : positive := 32;
parallel_inputs : positive := 1;
add_core_name : string := "stratix5_speed";
use_bram : boolean := true;
FCBT_max_inputs : positive := 1;
FCBT_obuf_size : positive := 1
);
port (
clk : in std_logic;
rst : in std_logic;
hold_output : in std_logic;
ready : out std_logic;
end_of_group : in std_logic;
input : in std_logic_vector(width*parallel_inputs-1 downto 0);
output : out std_logic_vector(width-1 downto 0);
valid_in : in std_logic;
valid_out : out std_logic
);
end uaa;
architecture DEFAULT of uaa is
signal accum_input : std_logic_vector(width-1 downto 0);
signal accum_valid_in : std_logic;
signal accum_end_of_group : std_logic;
signal ready_s : std_logic;
begin
-- use an adder tree to reduce parallel_inputs per cycle to 1 value
ADD_TREE : if (parallel_inputs > 1) generate
-- the add tree only stalls when ready isn't asserted. This differs
-- from the accumulator. As a result, invalid outputs from the add tree
-- will likely be interleaved with valid outputs. The accumulator
-- simply ignores the invalid inputs, so there is no reason to stall
-- the add tree (unless ready is not asserted).
U_ADD_TREE : entity work.add_tree_flt
generic map (
num_inputs => parallel_inputs,
add_core_name => add_core_name,
width => width)
port map (
clk => clk,
rst => rst,
en => ready_s,
input => input,
output => accum_input);
-- delay valid_in until output leaves add tree
U_DELAY_VALID_IN : entity work.delay
generic map (
width => 1,
cycles => add_tree_flt_latency(parallel_inputs, add_core_name),
init => "0")
port map (
clk => clk,
rst => rst,
en => ready_s,
input(0) => valid_in,
output(0) => accum_valid_in);
-- delay end_of_group until output leaves add tree
U_DELAY_END_OF_GROUP : entity work.delay
generic map (
width => 1,
cycles => add_tree_flt_latency(parallel_inputs, add_core_name),
init => "0")
port map (
clk => clk,
rst => rst,
en => ready_s,
input(0) => end_of_group,
output(0) => accum_end_of_group);
end generate ADD_TREE;
-- if there is only one input per cycle, forward it to the accumulator
NO_ADD_TREE : if (parallel_inputs = 1) generate
accum_input <= input;
accum_valid_in <= valid_in;
accum_end_of_group <= end_of_group;
end generate NO_ADD_TREE;
ready <= ready_s;
-- instantiate a DSA architecture when requested
DSA : if (arch = UAA_DSA) generate
U_DSA : entity work.dsa
generic map (
width => width,
add_core_name => add_core_name,
use_bram => use_bram)
port map (
clk => clk,
rst => rst,
hold_output => hold_output,
ready => ready_s,
end_of_group => accum_end_of_group,
input => accum_input,
output => output,
valid_in => accum_valid_in,
valid_out => valid_out
);
end generate DSA;
-- instantiate a FCBT architecture when requested
FCBT : if (arch = UAA_FCBT) generate
U_FCBT : entity work.fcbt
generic map (
width => width,
add_core_name => add_core_name,
use_bram => use_bram,
FCBT_max_inputs => FCBT_max_inputs,
FCBT_obuf_size => FCBT_obuf_size)
port map(
clk => clk,
rst => rst,
hold_output => hold_output,
ready => ready_s,
end_of_group => accum_end_of_group,
input => accum_input,
output => output,
valid_in => accum_valid_in,
valid_out => valid_out
);
end generate FCBT;
-- instantiate a SGA architecture when requested
SGA : if (arch = UAA_SGA) generate
U_SGA : entity work.sga
generic map (
width => width,
add_core_name => add_core_name,
use_bram => use_bram)
port map(
clk => clk,
rst => rst,
hold_output => hold_output,
ready => ready_s,
end_of_group => accum_end_of_group,
input => accum_input,
output => output,
valid_in => accum_valid_in,
valid_out => valid_out
);
end generate SGA;
OTHER : if (arch /= UAA_DSA and arch /= UAA_FCBT and arch /= UAA_SGA) generate
assert(false) report "Error: invalid architecture specified in uaa." severity error;
end generate OTHER;
end DEFAULT;
| gpl-3.0 | 9c724a325e62aa7d45ce75e565048a8b | 0.524649 | 4.386632 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-altera-c5ekit/leon3mp.vhd | 1 | 27,795 | ------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.jtag.all;
use gaisler.i2c.all;
use gaisler.net.all;
--pragma translate_off
use gaisler.sim.all;
--pragma translate_on
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
-- Clock and reset
diff_clkin_top_125_p: in std_ulogic;
diff_clkin_bot_125_p: in std_ulogic;
clkin_50_fpga_right: in std_ulogic;
clkin_50_fpga_top: in std_ulogic;
clkout_sma: out std_ulogic;
cpu_resetn: in std_ulogic;
-- DDR3
ddr3_ck_p: out std_ulogic;
ddr3_ck_n: out std_ulogic;
ddr3_cke: out std_ulogic;
ddr3_rstn: out std_ulogic;
ddr3_csn: out std_ulogic;
ddr3_rasn: out std_ulogic;
ddr3_casn: out std_ulogic;
ddr3_wen: out std_ulogic;
ddr3_ba: out std_logic_vector(2 downto 0);
ddr3_a : out std_logic_vector(13 downto 0);
ddr3_dqs_p: inout std_logic_vector(3 downto 0);
ddr3_dqs_n: inout std_logic_vector(3 downto 0);
ddr3_dq: inout std_logic_vector(31 downto 0);
ddr3_dm: out std_logic_vector(3 downto 0);
ddr3_odt: out std_ulogic;
ddr3_oct_rzq: in std_ulogic;
-- LPDDR2
lpddr2_ck_p: out std_ulogic;
lpddr2_ck_n: out std_ulogic;
lpddr2_cke: out std_ulogic;
lpddr2_a: out std_logic_vector(9 downto 0);
lpddr2_dqs_p: inout std_logic_vector(1 downto 0);
lpddr2_dqs_n: inout std_logic_vector(1 downto 0);
lpddr2_dq: inout std_logic_vector(15 downto 0);
lpddr2_dm: out std_logic_vector(1 downto 0);
lpddr2_csn: out std_ulogic;
lpddr2_oct_rzq: in std_ulogic;
-- Flash and SSRAM interface
fm_a: out std_logic_vector(26 downto 1);
fm_d: in std_logic_vector(15 downto 0);
flash_clk: out std_ulogic;
flash_resetn: out std_ulogic;
flash_cen: out std_ulogic; -- Driven const low by MAXV CPLD?
flash_advn: out std_ulogic;
flash_wen: out std_ulogic;
flash_oen: out std_ulogic;
flash_rdybsyn: in std_ulogic;
ssram_clk: out std_ulogic;
ssram_oen: out std_ulogic;
sram_cen: out std_ulogic;
ssram_bwen: out std_ulogic;
ssram_bwan: out std_ulogic;
ssram_bwbn: out std_ulogic;
ssram_adscn: out std_ulogic;
ssram_adspn: out std_ulogic;
ssram_zzn: out std_ulogic; -- Name incorrect, this is active high
ssram_advn: out std_ulogic;
-- EEPROM
eeprom_scl : inout std_ulogic;
eeprom_sda : inout std_ulogic;
-- UART
uart_rxd : in std_ulogic;
uart_rts : in std_ulogic; -- Note CTS and RTS mixed up on PCB
uart_txd : out std_ulogic;
uart_cts : out std_ulogic;
-- USB UART Interface
usb_uart_rstn : in std_ulogic; -- inout
usb_uart_ri : in std_ulogic;
usb_uart_dcd : in std_ulogic;
usb_uart_dtr : out std_ulogic;
usb_uart_dsr : in std_ulogic;
usb_uart_txd : out std_ulogic;
usb_uart_rxd : in std_ulogic;
usb_uart_rts : in std_ulogic;
usb_uart_cts : out std_ulogic;
usb_uart_gpio2 : in std_ulogic;
usb_uart_suspend : in std_ulogic;
usb_uart_suspendn : in std_ulogic;
-- Ethernet port A
eneta_rx_clk: in std_ulogic;
eneta_tx_clk: in std_ulogic;
eneta_intn: in std_ulogic;
eneta_resetn: out std_ulogic;
eneta_mdio: inout std_ulogic;
eneta_mdc: out std_ulogic;
eneta_rx_er: in std_ulogic;
eneta_tx_er: out std_ulogic;
eneta_rx_col: in std_ulogic;
eneta_rx_crs: in std_ulogic;
eneta_tx_d: out std_logic_vector(3 downto 0);
eneta_rx_d: in std_logic_vector(3 downto 0);
eneta_gtx_clk: out std_ulogic;
eneta_tx_en: out std_ulogic;
eneta_rx_dv: in std_ulogic;
-- Ethernet port B
enetb_rx_clk: in std_ulogic;
enetb_tx_clk: in std_ulogic;
enetb_intn: in std_ulogic;
enetb_resetn: out std_ulogic;
enetb_mdio: inout std_ulogic;
enetb_mdc: out std_ulogic;
enetb_rx_er: in std_ulogic;
enetb_tx_er: out std_ulogic;
enetb_rx_col: in std_ulogic;
enetb_rx_crs: in std_ulogic;
enetb_tx_d: out std_logic_vector(3 downto 0);
enetb_rx_d: in std_logic_vector(3 downto 0);
enetb_gtx_clk: out std_ulogic;
enetb_tx_en: out std_ulogic;
enetb_rx_dv: in std_ulogic;
-- LEDs, switches, GPIO
user_led : out std_logic_vector(3 downto 0);
user_dipsw : in std_logic_vector(3 downto 0);
dip_3p3V : in std_ulogic;
user_pb : in std_logic_vector(3 downto 0);
overtemp_fpga : out std_ulogic;
header_p : in std_logic_vector(5 downto 0); -- inout
header_n : in std_logic_vector(5 downto 0); -- inout
header_d : in std_logic_vector(7 downto 0); -- inout
-- LCD
lcd_data : in std_logic_vector(7 downto 0); -- inout
lcd_wen : out std_ulogic;
lcd_csn : out std_ulogic;
lcd_d_cn : out std_ulogic;
-- HIGH-SPEED-MEZZANINE-CARD Interface
-- This has been commented out as some pins have been placed in
-- violation with the Altera diff pad keep-out rules.
-- hsmc_clk_in0: in std_ulogic;
-- hsmc_clk_out0: out std_ulogic; -- changed due to placement rule
-- hsmc_clk_in_p: in std_logic_vector(2 downto 1);
-- hsmc_clk_out_p: out std_logic_vector(2 downto 1);
-- hsmc_d: in std_logic_vector(3 downto 0); -- inout
-- hsmc_tx_d_p: out std_logic_vector(16 downto 0);
-- hsmc_rx_d_p: in std_logic_vector(16 downto 0);
-- hsmc_rx_led: out std_ulogic;
-- hsmc_tx_led: out std_ulogic;
-- hsmc_scl: out std_ulogic; -- in due to placement rule
-- hsmc_sda: in std_ulogic; -- inout
-- hsmc_prsntn: in std_ulogic;
-- MAX V CPLD interface
max5_csn: out std_ulogic;
max5_wen: out std_ulogic;
max5_oen: out std_ulogic;
max5_ben: out std_logic_vector(3 downto 0);
max5_clk: out std_ulogic;
-- USB Blaster II
usb_clk : in std_ulogic;
usb_data : in std_logic_vector(7 downto 0); -- inout
usb_addr : in std_logic_vector(1 downto 0); -- inout
usb_scl : in std_ulogic; -- inout
usb_sda : in std_ulogic; -- inout
usb_resetn : in std_ulogic;
usb_oen : in std_ulogic;
usb_rdn : in std_ulogic;
usb_wrn : in std_ulogic;
usb_full : out std_ulogic;
usb_empty : out std_ulogic;
fx2_resetn : in std_ulogic
);
end;
architecture rtl of leon3mp is
constant USE_AHBREP: integer := 0
--pragma translate_off
+1
--pragma translate_on
;
-- Bus indexes
constant hmi_cpu : integer := 0;
constant hmi_greth1 : integer := hmi_cpu + CFG_NCPU;
constant hmi_greth2 : integer := hmi_greth1 + CFG_GRETH;
constant hmi_ahbuart : integer := hmi_greth2 + CFG_GRETH2;
constant hmi_ahbjtag : integer := hmi_ahbuart + CFG_AHB_UART;
constant nahbm : integer := hmi_ahbjtag + CFG_AHB_JTAG;
constant hsi_ssrctrl : integer := 0;
constant hsi_apbctrl : integer := hsi_ssrctrl + (CFG_SSCTRL + CFG_AHBROMEN + 1)/2;
constant hsi_dsu : integer := hsi_apbctrl + 1;
constant hsi_ddr3 : integer := hsi_dsu + CFG_DSU;
constant hsi_lpddr2 : integer := hsi_ddr3 + 1;
constant hsi_ahbrep : integer := hsi_lpddr2 + 1;
constant nahbs : integer := hsi_ahbrep + USE_AHBREP;
constant pi_irqmp : integer := 0;
constant pi_apbuart : integer := pi_irqmp + CFG_IRQ3_ENABLE;
constant pi_gpt : integer := pi_apbuart + CFG_UART1_ENABLE;
constant pi_ahbuart : integer := pi_gpt + CFG_GPT_ENABLE;
constant pi_ssrctrl : integer := pi_ahbuart + CFG_AHB_UART;
constant pi_greth1 : integer := pi_ssrctrl + CFG_SSCTRL;
constant pi_greth2 : integer := pi_greth1 + CFG_GRETH;
constant pi_i2cmst : integer := pi_greth2 + CFG_GRETH2;
constant napbs : integer := pi_i2cmst + CFG_I2C_ENABLE;
constant CPU_FREQ : integer := 75000;
signal clklock: std_ulogic;
signal clkm: std_ulogic;
signal ssclk: std_ulogic;
signal rstn: std_ulogic;
signal ahbmi: ahb_mst_in_type;
signal ahbmo: ahb_mst_out_vector;
signal ahbsi: ahb_slv_in_type;
signal ahbso: ahb_slv_out_vector;
signal apbi: apb_slv_in_type;
signal apbo: apb_slv_out_vector;
signal irqi: irq_in_vector(CFG_NCPU-1 downto 0);
signal irqo: irq_out_vector(CFG_NCPU-1 downto 0);
signal dbgi: l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo: l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui: dsu_in_type;
signal dsuo: dsu_out_type;
signal gpti: gptimer_in_type;
signal sri: memory_in_type;
signal sro: memory_out_type;
signal del_addr: std_logic_vector(26 downto 1);
signal del_ce: std_logic;
signal del_bwe, del_bwa, del_bwb: std_logic_vector(1 downto 0);
signal ui_serial, ui_usb, ui, dui: uart_in_type;
signal uo_serial, uo_usb, uo, duo: uart_out_type;
signal ethi1,ethi2: eth_in_type;
signal etho1,etho2: eth_out_type;
signal i2ci: i2c_in_type;
signal i2co: i2c_out_type;
signal vcc, gnd: std_ulogic;
-- signal logsig: std_logic_vector(31 downto 0);
begin
vcc <= '1';
gnd <= '0';
-----------------------------------------------------------------------------
-- Clocking and reset
-----------------------------------------------------------------------------
user_led(0) <= not clklock;
clkgen0: entity work.clkgen_c5ekit
port map (clkin_50_fpga_right, clkm, open, clklock);
rstgen0: rstgen
generic map (syncrst => CFG_NOASYNC)
port map (cpu_resetn, clkm, clklock, rstn);
-----------------------------------------------------------------------------
-- AMBA bus fabric
-----------------------------------------------------------------------------
ahbctrl0: ahbctrl
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN,ioaddr => CFG_AHBIO, fpnpen => CFG_FPNPEN,
enbusmon => CFG_AHB_MON, assertwarn => CFG_AHB_MONWAR,
asserterr => CFG_AHB_MONERR, ahbtrace => CFG_AHB_DTRACE,
nahbm => nahbm, nahbs => nahbs)
port map (rstn,clkm,ahbmi,ahbmo,ahbsi,ahbso);
apbctrl0: apbctrl
generic map (hindex => hsi_apbctrl, haddr => CFG_APBADDR, nslaves => napbs)
port map (rstn,clkm,ahbsi,ahbso(hsi_apbctrl),apbi,apbo);
ahbmo(ahbmo'high downto nahbm) <= (others => ahbm_none);
ahbso(ahbso'high downto nahbs) <= (others => ahbs_none);
apbo(napbs to apbo'high) <= (others => apb_none);
-----------------------------------------------------------------------------
-- LEON3 Processor(s), DSU, timer and IRQ controller
-----------------------------------------------------------------------------
errorn_pad : outpad generic map (tech => padtech) port map (user_led(3), dbgo(0).error);
dsubre_pad : inpad generic map (tech => padtech) port map (user_pb(3), dsui.break);
user_led(2) <= not dsuo.active;
dsui.enable <= '1';
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => hsi_dsu, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(hsi_dsu), dbgo, dbgi, dsui, dsuo);
end generate;
end generate;
noleon: if CFG_LEON3 = 0 generate
irqo <= (others => ('0',"0000",'0','0','0'));
dbgo <= (others => dbgo_none);
end generate;
nodsu : if CFG_DSU = 0 or CFG_LEON3 = 0 generate
dsuo.tstop <= '0'; dsuo.active <= '0'; dsuo.pwd <= (others => '0');
end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => pi_irqmp, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(pi_irqmp), irqo, irqi);
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => pi_gpt, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(pi_gpt), gpti, open);
gpti <= gpti_dhalt_drive(dsuo.tstop);
end generate;
-----------------------------------------------------------------------------
-- Debug links
-----------------------------------------------------------------------------
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart -- Debug UART
generic map (hindex => hmi_ahbuart, pindex => pi_ahbuart, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(pi_ahbuart), ahbmi, ahbmo(hmi_ahbuart));
end generate;
nouah : if CFG_AHB_UART = 0 generate
duo.rtsn <= '0'; duo.txd <= '0';
duo.scaler <= (others => '0'); duo.txen <= '0';
duo.flow <= '0'; duo.rxen <= '0';
end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => hmi_ahbjtag, nsync => 2)
port map(rstn, clkm, gnd, gnd, gnd, open, ahbmi, ahbmo(hmi_ahbjtag),
open, open, open, open, open, open, open, gnd);
end generate;
-- EDCL included in Ethernet below
-----------------------------------------------------------------------------
-- Memory controllers
-----------------------------------------------------------------------------
fm_a <= del_addr; -- sro.address(26 downto 1);
-- fm_d_pad: iopadvv
-- generic map (tech => padtech, width => 16)
-- port map (pad => fm_d, i => sro.data(31 downto 16),
-- en => sro.vbdrive(31 downto 16), o => sri.data(31 downto 16));
sri.data(31 downto 16) <= fm_d;
flash_clk <= '0';
flash_resetn <= '1';
flash_cen <= '0'; -- sro.romsn(0);
flash_advn <= '0';
flash_wen <= sro.writen or sro.romsn(0);
flash_oen <= sro.oen or sro.romsn(0);
ssram_clk <= clkm;
ssram_oen <= sro.oen;
sram_cen <= del_ce; -- sro.ramsn(0);
ssram_bwen <= del_bwe(1); -- sro.writen;
ssram_bwan <= del_bwa(1); -- sro.wrn(0);
ssram_bwbn <= del_bwb(1); -- sro.wrn(1);
ssram_adscn <= '1';
ssram_adspn <= '0';
ssram_zzn <= '0';
ssram_advn <= '1';
sri.data(15 downto 0) <= sri.data(31 downto 16);
sri.brdyn <= '1';
sri.bexcn <= '1';
sri.writen <= '1';
sri.wrn <= (others => '1');
sri.bwidth <= "01";
sri.sd <= (others => '0');
sri.cb <= (others => '0');
sri.scb <= (others => '0');
sri.edac <= '0';
delproc: process(clkm)
begin
if rising_edge(clkm) then
del_addr <= sro.address(26 downto 1);
del_ce <= sro.ramsn(0);
del_bwe <= del_bwe(0) & sro.writen;
del_bwa <= del_bwa(0) & sro.wrn(0);
del_bwb <= del_bwb(0) & sro.wrn(1);
end if;
end process;
ssrctrl: if CFG_SSCTRL = 1 generate
ssrctrl0: gaisler.memctrl.ssrctrl
generic map (hindex => hsi_ssrctrl, pindex => pi_ssrctrl,
romaddr => 16#000#, rommask => 16#fc0#,
ioaddr => 0, iomask => 0,
ramaddr => 0, rammask => 0,
bus16 => CFG_SSCTRLP16
)
port map (rstn, clkm, ahbsi, ahbso(hsi_ssrctrl), apbi, apbo(pi_ssrctrl), sri, sro);
end generate;
nossrctrl: if CFG_SSCTRL = 0 generate
sro <= memory_out_none;
end generate;
bpromgen : if CFG_AHBROMEN /= 0 and CFG_SSCTRL = 0 generate
brom : entity work.ahbrom
generic map (hindex => hsi_ssrctrl, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(hsi_ssrctrl));
end generate;
ddr3if0: entity work.ddr3if
generic map (
hindex => hsi_ddr3,
haddr => 16#400#, hmask => 16#E00#
) port map (
pll_ref_clk => diff_clkin_top_125_p,
global_reset_n => cpu_resetn,
mem_a => ddr3_a,
mem_ba => ddr3_ba,
mem_ck => ddr3_ck_p,
mem_ck_n => ddr3_ck_n,
mem_cke => ddr3_cke,
mem_reset_n => ddr3_rstn,
mem_cs_n => ddr3_csn,
mem_dm => ddr3_dm,
mem_ras_n => ddr3_rasn,
mem_cas_n => ddr3_casn,
mem_we_n => ddr3_wen,
mem_dq => ddr3_dq,
mem_dqs => ddr3_dqs_p,
mem_dqs_n => ddr3_dqs_n,
mem_odt => ddr3_odt,
oct_rzqin => ddr3_oct_rzq,
ahb_clk => clkm,
ahb_rst => rstn,
ahbsi => ahbsi,
ahbso => ahbso(hsi_ddr3)
);
lpddr2if0: entity work.lpddr2if
generic map (
hindex => hsi_lpddr2,
haddr => 16#600#, hmask => 16#F00#
) port map (
pll_ref_clk => diff_clkin_bot_125_p,
global_reset_n => cpu_resetn,
mem_ca => lpddr2_a,
mem_ck => lpddr2_ck_p,
mem_ck_n => lpddr2_ck_n,
mem_cke => lpddr2_cke,
mem_cs_n => lpddr2_csn,
mem_dm => lpddr2_dm,
mem_dq => lpddr2_dq,
mem_dqs => lpddr2_dqs_p,
mem_dqs_n => lpddr2_dqs_n,
oct_rzqin => lpddr2_oct_rzq,
ahb_clk => clkm,
ahb_rst => rstn,
ahbsi => ahbsi,
ahbso => ahbso(hsi_lpddr2)
);
-----------------------------------------------------------------------------
-- UART
-----------------------------------------------------------------------------
srx_pad : inpad generic map (tech => padtech) port map (uart_rxd, ui_serial.rxd);
srts_pad : inpad generic map (tech => padtech) port map (uart_rts, ui_serial.ctsn);
stx_pad : outpad generic map (tech => padtech) port map (uart_txd, uo_serial.txd);
scts_pad : outpad generic map (tech => padtech) port map (uart_cts, uo_serial.rtsn);
urx_pad : inpad generic map (tech => padtech) port map (usb_uart_rxd, ui_usb.rxd);
urts_pad : inpad generic map (tech => padtech) port map (usb_uart_rts, ui_usb.ctsn);
utx_pad : outpad generic map (tech => padtech) port map (usb_uart_txd, uo_usb.txd);
ucts_pad : outpad generic map (tech => padtech) port map (usb_uart_cts, uo_usb.rtsn);
usb_uart_dtr <= '0';
ui_serial.extclk <= '0'; ui_usb.extclk <= '0';
-- UART switch
ui <= ui_serial when user_dipsw(0)='0' else ui_usb;
dui <= ui_usb when user_dipsw(0)='0' else ui_serial;
uo_serial <= uo when user_dipsw(0)='0' else duo;
uo_usb <= duo when user_dipsw(0)='0' else uo;
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => pi_apbuart, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(pi_apbuart), ui, uo);
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate
uo.rtsn <= '0'; uo.txd <= '0'; uo.scaler <= (others => '0');
uo.txen <= '0'; uo.flow <= '0'; uo.rxen <= '0';
end generate;
-- AHBUART, see under Debug links above
-----------------------------------------------------------------------------
-- Ethernet
-----------------------------------------------------------------------------
emdio_pad : iopad generic map (tech => padtech)
port map (eneta_mdio, etho1.mdio_o, etho1.mdio_oe, ethi1.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (eneta_tx_clk, ethi1.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (eneta_rx_clk, ethi1.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 4)
port map (eneta_rx_d, ethi1.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (eneta_rx_dv, ethi1.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (eneta_rx_er, ethi1.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (eneta_rx_col, ethi1.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (eneta_rx_crs, ethi1.rx_crs);
emdint_pad : inpad generic map (tech => padtech)
port map (eneta_intn, ethi1.mdint);
etxd_pad : outpadv generic map (tech => padtech, width => 4)
port map (eneta_tx_d, etho1.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map (eneta_tx_en, etho1.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (eneta_tx_er, etho1.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (eneta_mdc, etho1.mdc);
erst_pad : outpad generic map (tech => padtech)
port map (eneta_resetn, rstn);
ethi1.rxd(ethi1.rxd'high downto 4) <= (others => '0');
ethi1.gtx_clk <= '0'; ethi1.rmii_clk <= '0';
emdio_pad2 : iopad generic map (tech => padtech)
port map (enetb_mdio, etho2.mdio_o, etho2.mdio_oe, ethi2.mdio_i);
etxc_pad2 : clkpad generic map (tech => padtech, arch => 2)
port map (enetb_tx_clk, ethi2.tx_clk);
erxc_pad2 : clkpad generic map (tech => padtech, arch => 2)
port map (enetb_rx_clk, ethi2.rx_clk);
erxd_pad2 : inpadv generic map (tech => padtech, width => 4)
port map (enetb_rx_d, ethi2.rxd(3 downto 0));
erxdv_pad2 : inpad generic map (tech => padtech)
port map (enetb_rx_dv, ethi2.rx_dv);
erxer_pad2 : inpad generic map (tech => padtech)
port map (enetb_rx_er, ethi2.rx_er);
erxco_pad2 : inpad generic map (tech => padtech)
port map (enetb_rx_col, ethi2.rx_col);
erxcr_pad2 : inpad generic map (tech => padtech)
port map (enetb_rx_crs, ethi2.rx_crs);
emdint_pad2 : inpad generic map (tech => padtech)
port map (enetb_intn, ethi2.mdint);
etxd_pad2 : outpadv generic map (tech => padtech, width => 4)
port map (enetb_tx_d, etho2.txd(3 downto 0));
etxen_pad2 : outpad generic map (tech => padtech)
port map (enetb_tx_en, etho2.tx_en);
etxer_pad2 : outpad generic map (tech => padtech)
port map (enetb_tx_er, etho2.tx_er);
emdc_pad2 : outpad generic map (tech => padtech)
port map (enetb_mdc, etho2.mdc);
erst_pad2 : outpad generic map (tech => padtech)
port map (enetb_resetn, rstn);
ethi2.rxd(ethi1.rxd'high downto 4) <= (others => '0');
ethi2.gtx_clk <= '0'; ethi2.rmii_clk <= '0';
eth1 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm generic map(hindex => hmi_greth1,
pindex => pi_greth1, paddr => 11, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 2, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, phyrstadr => 0,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(hmi_greth1),
apbi => apbi, apbo => apbo(pi_greth1), ethi => ethi1, etho => etho1);
end generate;
noeth1 : if CFG_GRETH = 0 generate
etho1 <= eth_out_none;
end generate;
eth2 : if CFG_GRETH2 = 1 generate -- Secondary ethernet MAC
e2 : grethm generic map(hindex => hmi_greth2,
pindex => pi_greth2, paddr => 12, pirq => 13, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH2_FIFO,
nsync => 2, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, phyrstadr => 1,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH21G)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(hmi_greth2),
apbi => apbi, apbo => apbo(pi_greth2), ethi => ethi2, etho => etho2);
end generate;
noeth2 : if CFG_GRETH2 = 0 generate
etho2 <= eth_out_none;
end generate;
-----------------------------------------------------------------------------
-- GPIO
-----------------------------------------------------------------------------
-- TO DO
-----------------------------------------------------------------------------
-- Other
-----------------------------------------------------------------------------
max5_csn <= '1';
sclpad: iopad generic map (tech => padtech) port map (eeprom_scl, i2co.scl, i2co.scloen, i2ci.scl);
sdapad: iopad generic map (tech => padtech) port map (eeprom_sda, i2co.sda, i2co.sdaoen, i2ci.sda);
i2c: if CFG_I2C_ENABLE=1 generate
i2cmst0: i2cmst
generic map (pindex => pi_i2cmst, paddr => 4, pmask => 16#FFF#, pirq => 4)
port map (rstn,clkm,apbi,apbo(pi_i2cmst),i2ci,i2co);
end generate;
noi2c: if CFG_I2C_ENABLE=0 generate
i2co <= (others => '1');
end generate;
-- logan0: logan
-- generic map (pindex => napbs-1, paddr => 16#100#, memtech => memtech)
-- port map (rstn, clkm, clkm, apbi, apbo(napbs-1), logsig);
--
-- logsig(31 downto 6) <= (others => '0');
-- logsig(5 downto 0) <= i2co.scl & i2co.scloen & i2ci.scl & i2co.sda & i2co.sdaoen & i2ci.sda;
-- pragma translate_off
rep: if USE_AHBREP/=0 generate
ahbrep0: ahbrep
generic map (hindex => hsi_ahbrep, haddr => 16#200#)
port map (rstn,clkm,ahbsi,ahbso(hsi_ahbrep));
end generate;
x : report_version
generic map (
msg1 => "LEON3 Altera CycloneV E Demonstration design",
msg2 => "GRLIB Version " & tost(LIBVHDL_VERSION/1000) & "." & tost((LIBVHDL_VERSION mod 1000)/100)
& "." & tost(LIBVHDL_VERSION mod 100) & ", build " & tost(LIBVHDL_BUILD),
msg3 => "Target technology: " & tech_table(fabtech) & ", memory library: " & tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
| gpl-3.0 | be174dcf5f824daca8331811c6b93ce5 | 0.573089 | 3.333933 | false | false | false | false |
yishinli/emc2 | src/hal/drivers/mesa-hostmot2/firmware/src/atrans.vhd | 1 | 4,248 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
-- http://www.mesanet.com
--
-- This program is is licensed under a disjunctive dual license giving you
-- the choice of one of the two following sets of free software/open source
-- licensing terms:
--
-- * GNU General Public License (GPL), version 2.0 or later
-- * 3-clause BSD License
--
--
-- The GNU GPL License:
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
--
--
-- The 3-clause BSD License:
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- * Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- * Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- * Neither the name of Mesa Electronics nor the names of its
-- contributors may be used to endorse or promote products
-- derived from this software without specific prior written
-- permission.
--
--
-- Disclaimer:
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
entity atrans is
generic (
width : integer;
depth: integer );
port (
clk : in std_logic;
wea : in std_logic;
rea : in std_logic;
reb : in std_logic;
adda : in std_logic_vector(depth-1 downto 0);
addb : in std_logic_vector(depth-1 downto 0);
din : in std_logic_vector(width-1 downto 0);
douta : out std_logic_vector(width-1 downto 0);
doutb: out std_logic_vector(width-1 downto 0)
);
end atrans;
architecture syn of atrans is
type ram_type is array (0 to 2**depth-1) of std_logic_vector(width-1 downto 0);
signal RAM : ram_type;
signal dadda : std_logic_vector(depth-1 downto 0);
signal daddb : std_logic_vector(depth-1 downto 0);
signal outa : std_logic_vector(width-1 downto 0);
signal outb : std_logic_vector(width-1 downto 0);
begin
process (clk)
begin
if (clk'event and clk = '1') then
if (wea = '1') then
RAM(conv_integer(adda)) <= din;
end if;
dadda <= adda;
daddb <= addb;
end if;
outa <= RAM(conv_integer(dadda));
outb <= RAM(conv_integer(daddb));
douta <= (others => 'Z');
if rea = '1' then
douta <= outa;
end if;
doutb <= (others => 'Z');
if reb = '1' then
doutb <= outb;
end if;
end process;
end;
| lgpl-2.1 | 559b60970b5b7590c7a6c8414faee42d | 0.668079 | 3.716535 | false | false | false | false |
pwsoft/fpga_examples | rtl/chameleon/chameleon_docking_station.vhd | 1 | 8,384 | -- -----------------------------------------------------------------------
--
-- Turbo Chameleon
--
-- Multi purpose FPGA expansion for the Commodore 64 computer
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2019 by Peter Wendrich ([email protected])
-- http://www.syntiac.com/chameleon.html
--
-- This source file is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- -----------------------------------------------------------------------
--
-- Chameleon docking station
--
-- -----------------------------------------------------------------------
-- clk - system clock
-- docking_station - must be high when docking-station is available.
-- This can be determined by the state of the phi2 pin.
-- docking_version - '0' first version, supports 2 fire buttons on each port
-- '1' second version, 3 fire buttons on each port and midi in/out
-- dotclock_n - Connect to the dotclock_n pin.
-- io_ef_n - Connect to the io_ef_n pin.
-- rom_hl_n - Connect to the rom_hl_n pin.
-- irq_q - IRQ pin output (open drain output, 0 is drive low, 1 is input)
-- joystick* - Joystick outputs (fire2, fire1, right, left, down, up) low active
-- keys - State of the keyboard (low is pressed)
-- restore_key_n - State of the restore key (low is pressed)
--
-- amiga_power_led - Control input for the POWER LED on the Amiga keyboard.
-- amiga_drive_led - Control input for the DRIVE LED on the Amiga keyboard.
-- amiga_reset_n - Low when the Amiga keyboard does a reset.
-- amiga_trigger - One clock high when the Amiga keyboard has send a new scancode.
-- amiga_scancode - Value of the last received scancode from the Amiga keyboard.
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
-- -----------------------------------------------------------------------
entity chameleon_docking_station is
port (
clk : in std_logic;
docking_station : in std_logic;
docking_version : out std_logic;
dotclock_n : in std_logic;
io_ef_n : in std_logic;
rom_lh_n : in std_logic;
irq_q : out std_logic;
joystick1 : out unsigned(6 downto 0);
joystick2 : out unsigned(6 downto 0);
joystick3 : out unsigned(6 downto 0);
joystick4 : out unsigned(6 downto 0);
-- 0 = col0, row0
-- 1 = col1, row0
-- 8 = col0, row1
-- 63 = col7, row7
keys : out unsigned(63 downto 0);
restore_key_n : out std_logic;
-- Amiga keyboard
amiga_power_led : in std_logic;
amiga_drive_led : in std_logic;
amiga_reset_n : out std_logic;
amiga_trigger : out std_logic;
amiga_scancode : out unsigned(7 downto 0)
);
end entity;
-- -----------------------------------------------------------------------
architecture rtl of chameleon_docking_station is
constant shift_reg_bits : integer := 13*8;
-- We put the out-of-sync detection just before the actual sync-pulse.
-- Gives it the biggest chance of catching a sync-problem.
constant out_of_sync_pos : integer := 102;
signal shift_reg : unsigned(shift_reg_bits-1 downto 0);
signal bit_cnt : unsigned(7 downto 0) := (others => '0');
signal once : std_logic := '0';
signal docking_version_reg : std_logic := '0';
signal key_reg : unsigned(63 downto 0) := (others => '1');
signal restore_n_reg : std_logic := '1';
signal joystick1_reg : unsigned(6 downto 0) := (others => '0');
signal joystick2_reg : unsigned(6 downto 0) := (others => '0');
signal joystick3_reg : unsigned(6 downto 0) := (others => '0');
signal joystick4_reg : unsigned(6 downto 0) := (others => '0');
signal dotclock_n_reg : std_logic := '0';
signal dotclock_n_dly : std_logic := '0';
signal io_ef_n_reg : std_logic := '0';
signal rom_lh_n_reg : std_logic := '1';
signal irq_q_reg : std_logic := '1';
signal amiga_reset_n_reg : std_logic := '0';
signal amiga_trigger_reg : std_logic := '0';
signal amiga_scancode_reg : unsigned(7 downto 0) := (others => '0');
begin
docking_version <= docking_version_reg;
joystick1 <= joystick1_reg;
joystick2 <= joystick2_reg;
joystick3 <= joystick3_reg;
joystick4 <= joystick4_reg;
keys <= key_reg;
restore_key_n <= restore_n_reg;
amiga_reset_n <= amiga_reset_n_reg;
amiga_trigger <= amiga_trigger_reg;
amiga_scancode <= amiga_scancode_reg;
irq_q <= irq_q_reg;
--
-- Sample DotClock, IO_EF and ROM_LH input.
process(clk) is
begin
if rising_edge(clk) then
dotclock_n_reg <= dotclock_n;
dotclock_n_dly <= dotclock_n_reg;
io_ef_n_reg <= io_ef_n;
rom_lh_n_reg <= rom_lh_n;
end if;
end process;
--
-- Receive serial stream
process(clk) is
begin
if rising_edge(clk) then
if (dotclock_n_reg = '0') and (dotclock_n_dly = '1') then
shift_reg <= (not rom_lh_n_reg) & shift_reg(shift_reg'high downto 1);
bit_cnt <= bit_cnt + 1;
end if;
if (io_ef_n_reg = '1') and (bit_cnt = out_of_sync_pos) then
-- Out of sync detection.
-- Wait for the MCU on the docking-station to release io_ef
-- Then we can continue and syncronise on the next io_ef pulse that comes.
bit_cnt <= to_unsigned(out_of_sync_pos, bit_cnt'length);
end if;
if (io_ef_n_reg = '1') and (bit_cnt >= shift_reg_bits) then
-- Word trigger. Signals start of serial bit-stream.
bit_cnt <= (others => '0');
end if;
end if;
end process;
--
-- Amiga keyboard LED control
process(clk) is
begin
if rising_edge(clk) then
irq_q_reg <= '1';
if (bit_cnt >= 40) and (bit_cnt < 56) then
irq_q_reg <= amiga_power_led;
end if;
if (bit_cnt >= 72) and (bit_cnt < 88) then
irq_q_reg <= amiga_drive_led;
end if;
end if;
end process;
--
-- Decode bytes
process(clk) is
begin
if rising_edge(clk) then
if bit_cnt = shift_reg_bits then
-- Docking-station and protocol version information
docking_version_reg <= shift_reg(3);
-- Map shifted bits to joysticks
joystick1_reg <=
(shift_reg(4) or (not shift_reg(3))) &
shift_reg(101 downto 96);
joystick2_reg <=
(shift_reg(5) or (not shift_reg(3))) &
shift_reg(85 downto 80);
joystick3_reg <=
(shift_reg(6) or (not shift_reg(3))) &
shift_reg(102) & shift_reg(103) &
shift_reg(92) & shift_reg(93) & shift_reg(94) & shift_reg(95);
joystick4_reg <=
(shift_reg(7) or (not shift_reg(3))) &
shift_reg(86) & shift_reg(87) &
shift_reg(88) & shift_reg(89) & shift_reg(90) & shift_reg(91);
restore_n_reg <= shift_reg(1);
-- Map shifted bits to C64 keyboard
if (shift_reg(87 downto 80) = X"FF") and (shift_reg(103 downto 96) = X"FF") then
for row in 0 to 7 loop
for col in 0 to 7 loop
-- uC scans column wise.
key_reg(row*8 + col) <= shift_reg(16 + col*8 + row);
end loop;
end loop;
else
-- Prevent conflict between keyboard and joystick.
-- Relase all keyboard keys while joystick button(s) are pressed.
key_reg <= (others => '1');
end if;
-- Amiga keyboard
amiga_reset_n_reg <= shift_reg(2);
if shift_reg(0) = '1' then
amiga_scancode_reg <= shift_reg(15 downto 8);
amiga_trigger_reg <= once;
end if;
once <= '0';
end if;
if (io_ef_n_reg = '1') then
once <= '1';
end if;
-- No docking station connected.
-- Disable all outputs to prevent conflicts.
if docking_station = '0' then
docking_version_reg <= '0';
joystick1_reg <= (others => '1');
joystick2_reg <= (others => '1');
joystick3_reg <= (others => '1');
joystick4_reg <= (others => '1');
key_reg <= (others => '1');
restore_n_reg <= '1';
amiga_reset_n_reg <= '1';
amiga_scancode_reg <= (others => '1');
amiga_trigger_reg <= '0';
end if;
end if;
end process;
end architecture;
| lgpl-2.1 | 281732394e25a949b6b7a2bef1bc1883 | 0.598163 | 3.027808 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-altera-c5ekit/lpddr2if.vhd | 1 | 8,382 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
library gaisler;
use gaisler.ddrpkg.all;
entity lpddr2if is
generic (
hindex: integer;
haddr: integer := 16#400#;
hmask: integer := 16#000#;
burstlen: integer := 8
);
port (
pll_ref_clk: in std_ulogic;
global_reset_n: in std_ulogic;
mem_ca: out std_logic_vector(9 downto 0);
mem_ck: out std_ulogic;
mem_ck_n: out std_ulogic;
mem_cke: out std_ulogic;
mem_cs_n: out std_ulogic;
mem_dm: out std_logic_vector(1 downto 0);
mem_dq: inout std_logic_vector(15 downto 0);
mem_dqs: inout std_logic_vector(1 downto 0);
mem_dqs_n: inout std_logic_vector(1 downto 0);
oct_rzqin: in std_logic;
ahb_clk: in std_ulogic;
ahb_rst: in std_ulogic;
ahbsi: in ahb_slv_in_type;
ahbso: out ahb_slv_out_type
);
end;
architecture rtl of lpddr2if is
component lpddr2ctrl1 is
port (
pll_ref_clk : in std_logic := 'X'; -- clk
global_reset_n : in std_logic := 'X'; -- reset_n
soft_reset_n : in std_logic := 'X'; -- reset_n
afi_clk : out std_logic; -- clk
afi_half_clk : out std_logic; -- clk
afi_reset_n : out std_logic; -- reset_n
afi_reset_export_n : out std_logic; -- reset_n
mem_ca : out std_logic_vector(9 downto 0); -- mem_ca
mem_ck : out std_logic_vector(0 downto 0); -- mem_ck
mem_ck_n : out std_logic_vector(0 downto 0); -- mem_ck_n
mem_cke : out std_logic_vector(0 downto 0); -- mem_cke
mem_cs_n : out std_logic_vector(0 downto 0); -- mem_cs_n
mem_dm : out std_logic_vector(1 downto 0); -- mem_dm
mem_dq : inout std_logic_vector(15 downto 0) := (others => 'X'); -- mem_dq
mem_dqs : inout std_logic_vector(1 downto 0) := (others => 'X'); -- mem_dqs
mem_dqs_n : inout std_logic_vector(1 downto 0) := (others => 'X'); -- mem_dqs_n
avl_ready : out std_logic; -- waitrequest_n
avl_burstbegin : in std_logic := 'X'; -- beginbursttransfer
avl_addr : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
avl_rdata_valid : out std_logic; -- readdatavalid
avl_rdata : out std_logic_vector(63 downto 0); -- readdata
avl_wdata : in std_logic_vector(63 downto 0) := (others => 'X'); -- writedata
avl_be : in std_logic_vector(7 downto 0) := (others => 'X'); -- byteenable
avl_read_req : in std_logic := 'X'; -- read
avl_write_req : in std_logic := 'X'; -- write
avl_size : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
local_init_done : out std_logic; -- local_init_done
local_cal_success : out std_logic; -- local_cal_success
local_cal_fail : out std_logic; -- local_cal_fail
oct_rzqin : in std_logic := 'X'; -- rzqin
pll_mem_clk : out std_logic; -- pll_mem_clk
pll_write_clk : out std_logic; -- pll_write_clk
pll_write_clk_pre_phy_clk : out std_logic; -- pll_write_clk_pre_phy_clk
pll_addr_cmd_clk : out std_logic; -- pll_addr_cmd_clk
pll_locked : out std_logic; -- pll_locked
pll_avl_clk : out std_logic; -- pll_avl_clk
pll_config_clk : out std_logic; -- pll_config_clk
pll_mem_phy_clk : out std_logic; -- pll_mem_phy_clk
afi_phy_clk : out std_logic; -- afi_phy_clk
pll_avl_phy_clk : out std_logic -- pll_avl_phy_clk
);
end component lpddr2ctrl1;
signal vcc: std_ulogic;
signal afi_clk, afi_half_clk, afi_reset_n: std_ulogic;
signal local_init_done, local_cal_success, local_cal_fail: std_ulogic;
signal ck_p_arr, ck_n_arr, cke_arr, cs_arr: std_logic_vector(0 downto 0);
signal avlsi: ddravl_slv_in_type;
signal avlso: ddravl_slv_out_type;
begin
vcc <= '1';
mem_ck <= ck_p_arr(0);
mem_ck_n <= ck_n_arr(0);
mem_cke <= cke_arr(0);
mem_cs_n <= cs_arr(0);
ctrl0: lpddr2ctrl1
port map (
pll_ref_clk => pll_ref_clk,
global_reset_n => global_reset_n,
soft_reset_n => vcc,
afi_clk => afi_clk,
afi_half_clk => afi_half_clk,
afi_reset_n => afi_reset_n,
afi_reset_export_n => open,
mem_ca => mem_ca,
mem_ck => ck_p_arr,
mem_ck_n => ck_n_arr,
mem_cke => cke_arr,
mem_cs_n => cs_arr,
mem_dm => mem_dm,
mem_dq => mem_dq,
mem_dqs => mem_dqs,
mem_dqs_n => mem_dqs_n,
avl_ready => avlso.ready,
avl_burstbegin => avlsi.burstbegin,
avl_addr => avlsi.addr(24 downto 0),
avl_rdata_valid => avlso.rdata_valid,
avl_rdata => avlso.rdata(63 downto 0),
avl_wdata => avlsi.wdata(63 downto 0),
avl_be => avlsi.be(7 downto 0),
avl_read_req => avlsi.read_req,
avl_write_req => avlsi.write_req,
avl_size => avlsi.size(2 downto 0),
local_init_done => local_init_done,
local_cal_success => local_cal_success,
local_cal_fail => local_cal_fail,
oct_rzqin => oct_rzqin,
pll_mem_clk => open,
pll_write_clk => open,
pll_write_clk_pre_phy_clk => open,
pll_addr_cmd_clk => open,
pll_locked => open,
pll_avl_clk => open,
pll_config_clk => open,
pll_mem_phy_clk => open,
afi_phy_clk => open,
pll_avl_phy_clk => open
);
avlso.rdata(avlso.rdata'high downto 64) <= (others => '0');
ahb2avl0: ahb2avl_async
generic map (
hindex => hindex,
haddr => haddr,
hmask => hmask,
burstlen => burstlen,
nosync => 0,
avldbits => 64,
avlabits => 25
)
port map (
rst_ahb => ahb_rst,
clk_ahb => ahb_clk,
ahbsi => ahbsi,
ahbso => ahbso,
rst_avl => afi_reset_n,
clk_avl => afi_clk,
avlsi => avlsi,
avlso => avlso
);
end;
| gpl-3.0 | 06e506e903c217d8cfa851cd7baed3c3 | 0.476259 | 3.658664 | false | false | false | false |
pwsoft/fpga_examples | rtl/ps2/io_ps2_com.vhd | 1 | 7,030 | -- -----------------------------------------------------------------------
--
-- Syntiac VHDL support files.
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2009 by Peter Wendrich ([email protected])
-- http://www.syntiac.com
--
-- This source file is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- -----------------------------------------------------------------------
--
-- PS/2 lowlevel driver
--
-- -----------------------------------------------------------------------
--
-- clockFilter - Number of clock cycles used in filtering the PS/2 clock.
-- This suppresses transient and echo effects on the cable.
-- Recommended value is 15.
-- ticksPerUsec - Fill in the system clock speed in Mhz.
-- clk - system clock input
-- ps2_clk_in - Clock input from the ps/2 port
-- ps2_dat_in - Data input from the ps/2 port
-- ps2_clk_out - Generated ps/2 clock route to open-collector logic.
-- ps2_dat_out - Generated ps/2 data line route to open-collector logic.
-- inIdle - Output is high when driver is waiting/idle.
-- sendTrigger - Make this signal 1 clock cycle high to send byte
-- sendByte - Actual byte send when sendTrigger is given
-- recvTrigger - Is 1 clock cycle high when byte is received.
-- recvByte - Last byte received from the ps/2 interface
--
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
-- -----------------------------------------------------------------------
entity io_ps2_com is
generic (
clockFilter : integer;
ticksPerUsec : integer
);
port (
clk: in std_logic;
reset : in std_logic;
ps2_clk_in: in std_logic;
ps2_dat_in: in std_logic;
ps2_clk_out: out std_logic;
ps2_dat_out: out std_logic;
inIdle : out std_logic;
sendTrigger : in std_logic;
sendByte : in unsigned(7 downto 0);
sendBusy : out std_logic;
recvTrigger : out std_logic;
recvByte : out unsigned(10 downto 0)
);
end entity;
-- -----------------------------------------------------------------------
architecture rtl of io_ps2_com is
constant ticksPer100Usec : integer := ticksPerUsec * 100;
type comStateDef is (
stateIdle, stateWait100, stateWaitClockLow, stateWaitClockHigh, stateClockAndDataLow, stateWaitAck,
stateRecvBit, stateWaitHighRecv);
signal comState : comStateDef := stateIdle;
signal sendTriggerLoc : std_logic := '0';
signal clkReg: std_logic := '1';
signal clkFilterCnt: integer range 0 to clockFilter;
signal waitCount : integer range 0 to ticksPer100Usec := 0;
signal currentBit : std_logic;
signal bitCount : unsigned(3 downto 0);
signal parity : std_logic;
signal recvByteLoc : unsigned(10 downto 0);
begin
inIdle <= '1' when comState = stateIdle else '0';
sendBusy <= sendTrigger or sendTriggerLoc;
--
-- Noise and glitch filter on the clock-line
process(clk)
begin
if rising_edge(clk) then
clkReg <= ps2_clk_in;
if clkReg /= ps2_clk_in then
clkFilterCnt <= clockFilter;
elsif clkFilterCnt /= 0 then
clkFilterCnt <= clkFilterCnt - 1;
end if;
end if;
end process;
--
-- Lowlevel send and receive state machines
process(clk)
begin
if rising_edge(clk) then
ps2_clk_out <= '1';
ps2_dat_out <= '1';
recvTrigger <= '0';
if waitCount /= 0 then
waitCount <= waitCount - 1;
end if;
if sendTrigger = '1' then
sendTriggerLoc <= '1';
end if;
case comState is
when stateIdle =>
bitCount <= (others => '0');
parity <= '1';
if sendTriggerLoc = '1' then
waitCount <= ticksPer100Usec;
comState <= stateWait100;
end if;
if (clkReg = '0') and (clkFilterCnt = 0) then
comState <= stateRecvBit;
end if;
--
-- Host announces its wish to send by pulling clock low for 100us
when stateWait100 =>
ps2_clk_out <= '0';
if waitCount = 0 then
comState <= stateClockAndDataLow;
waitCount <= ticksPerUsec * 10;
end if;
--
-- Pull data low while keeping clock low. This is host->device start bit.
-- Now the device will take over and provide the clock so host must release.
-- Next state is waitClockHigh to check that clock indeed is released
when stateClockAndDataLow =>
ps2_clk_out <= '0';
ps2_dat_out <= '0';
if waitCount = 0 then
currentBit <= '0';
comState <= stateWaitClockHigh;
end if;
--
-- Wait for 0->1 transition on clock for send.
-- The device reads current bit while clock is low.
when stateWaitClockHigh =>
ps2_dat_out <= currentBit;
if (clkReg = '1') and (clkFilterCnt = 0) then
comState <= stateWaitClockLow;
end if;
--
-- Wait for 1->0 transition on clock for send
-- Host can now change the data line for next bit.
when stateWaitClockLow =>
ps2_dat_out <= currentBit;
if (clkReg = '0') and (clkFilterCnt = 0) then
if bitCount = 10 then
comState <= stateWaitAck;
elsif bitCount = 9 then
-- Send stop bit
currentBit <= '1';
comState <= stateWaitClockHigh;
bitCount <= bitCount + 1;
elsif bitCount = 8 then
-- Send parity bit
currentBit <= parity;
comState <= stateWaitClockHigh;
bitCount <= bitCount + 1;
else
currentBit <= sendByte(to_integer(bitCount));
parity <= parity xor sendByte(to_integer(bitCount));
comState <= stateWaitClockHigh;
bitCount <= bitCount + 1;
end if;
end if;
--
-- Transmission of byte done, wait for ack from device then return to idle.
when stateWaitAck =>
if (clkReg = '1') and (clkFilterCnt = 0) then
sendTriggerLoc <= '0';
comState <= stateIdle;
end if;
--
-- Receive a single bit.
when stateRecvBit =>
if (clkReg = '0') and (clkFilterCnt = 0) then
recvByteLoc <= ps2_dat_in & recvByteLoc(recvByteLoc'high downto 1);
bitCount <= bitCount + 1;
comState <= stateWaitHighRecv;
end if;
--
-- Wait for 0->1 transition on clock for receive.
when stateWaitHighRecv =>
if (clkReg = '1') and (clkFilterCnt = 0) then
comState <= stateRecvBit;
if bitCount = 11 then
recvTrigger <= '1';
recvByte <= recvByteLoc;
comState <= stateIdle;
end if;
end if;
end case;
if reset = '1' then
comState <= stateIdle;
sendTriggerLoc <= '0';
end if;
end if;
end process;
end architecture;
| lgpl-2.1 | 2b8f58b31b37ea3c94b9abbac49864f5 | 0.609815 | 3.50274 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/misc/gracectrl.vhd | 1 | 14,070 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: gracectrl
-- File: gracectrl.vhd
-- Author: Jan Andersson - Gaisler Research AB
-- Contact: [email protected]
-- Description: Provides a GRLIB AMBA AHB slave interface to Xilinx System ACE
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, gaisler;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.all;
use gaisler.misc.all;
entity gracectrl is
generic (
hindex : integer := 0; -- AHB slave index
hirq : integer := 0; -- Interrupt line
haddr : integer := 16#000#; -- Base address
hmask : integer := 16#fff#; -- Area mask
split : integer range 0 to 1 := 0; -- Enable AMBA SPLIT support
swap : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0; -- Output enable polarity
mode : integer range 0 to 2 := 0 -- 0: 16-bit mode only
-- 1: 8-bit mode only
-- 2: 8-bit, emulate 16-bit
);
port (
rstn : in std_ulogic;
clk : in std_ulogic; -- System (AMBA) clock
clkace : in std_ulogic; -- System ACE clock
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
acei : in gracectrl_in_type;
aceo : out gracectrl_out_type
);
end gracectrl;
architecture rtl of gracectrl is
-----------------------------------------------------------------------------
-- Constants
-----------------------------------------------------------------------------
constant REVISION : amba_version_type := 0;
constant HCONFIG : ahb_config_type := (
0 => ahb_device_reg(VENDOR_GAISLER, GAISLER_GRACECTRL, 0, REVISION, hirq),
-- 1 => conv_std_logic_vector(swap*4 + mode, 32),
4 => ahb_iobar(haddr, hmask), others => zero32);
constant OUTPUT : std_ulogic := conv_std_logic(oepol = 1);
constant INPUT : std_ulogic := not conv_std_logic(oepol = 1);
constant ACEDW : integer := 16-8*(mode mod 2);
-----------------------------------------------------------------------------
-- Functions
-----------------------------------------------------------------------------
-- purpose: swaps a hword if 'swap' is non-zero and mode is zero,
-- otherwise just propagate data
function condhswap (d : std_logic_vector)
return std_logic_vector is
variable dx : std_logic_vector(15 downto 0);
begin -- hswap
dx(ACEDW-1 downto 0) := d;
if swap /= 0 and mode = 0 then
return dx(7 downto 0) & dx(15 downto 8);
end if;
return dx;
end condhswap;
-----------------------------------------------------------------------------
-- Types
-----------------------------------------------------------------------------
type sys_sync_type is record
accdone : std_logic_vector(1 downto 0);
irq : std_logic_vector(2 downto 0);
end record;
type sys_reg_type is record
acc : std_ulogic; -- Perform access
active : std_ulogic; -- Access active
sync : sys_sync_type;
-- AHB
insplit : std_ulogic; -- SPLIT response issued
unsplit : std_ulogic; -- SPLIT complete not issued
irq : std_ulogic; -- Interrupt request
hwrite : std_ulogic;
hsel : std_ulogic;
hmbsel : std_logic_vector(0 to 1);
haddr : std_logic_vector(6 downto 0);
hready : std_ulogic;
wdata : std_logic_vector(ACEDW-1 downto 0);
hresp : std_logic_vector(1 downto 0);
splmst : std_logic_vector(log2(NAHBMST)-1 downto 0); -- SPLIT:ed master
hsplit : std_logic_vector(NAHBMST-1 downto 0); -- Other SPLIT:ed masters
ahbcancel : std_ulogic; -- Locked access cancels ongoing SPLIT
-- response
end record;
type ace_state_type is (idle, en, rd, done);
type ace_sync_type is record
acc : std_logic_vector(1 downto 0);
rstn : std_logic_vector(1 downto 0);
hwrite : std_logic_vector(1 downto 0);
dummy : std_logic_vector(1 downto 0);
end record;
type ace_reg_type is record
state : ace_state_type;
sync : ace_sync_type;
accdone : std_ulogic;
rdata : std_logic_vector(ACEDW-1 downto 0);
edone : std_ulogic;
aceo : gracectrl_out_type;
end record;
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
signal r, rin : sys_reg_type;
signal s, sin : ace_reg_type;
begin -- rtl
-----------------------------------------------------------------------------
-- System clock domain
-----------------------------------------------------------------------------
combsys: process (r, s, rstn, ahbsi, acei.irq)
variable v : sys_reg_type;
variable irq : std_logic_vector((NAHBIRQ-1) downto 0);
variable hsplit : std_logic_vector(NAHBMST-1 downto 0);
variable hwdata : std_logic_vector(31 downto 0);
begin -- process comb
v := r; v.irq := '0'; irq := (others => '0'); irq(hirq) := r.irq;
v.hresp := HRESP_OKAY; v.hready := '1'; hsplit := (others => '0');
hwdata := ahbreadword(ahbsi.hwdata, r.haddr(4 downto 2));
-- Sync
v.sync.accdone := r.sync.accdone(0) & s.accdone;
v.sync.irq := r.sync.irq(1 downto 0) & acei.irq;
-- AHB communication
if ahbsi.hready = '1' then
if (ahbsi.hsel(hindex) and ahbsi.htrans(1)) = '1' then
v.hmbsel := ahbsi.hmbsel(r.hmbsel'range);
if split = 0 or (not (r.active or r.acc) or ahbsi.hmastlock) = '1' then
v.hready := '0';
v.hwrite := ahbsi.hwrite;
v.haddr := ahbsi.haddr(6 downto 0);
v.hsel := '1';
if r.insplit = '0' then
v.acc := '1';
end if;
if split /= 0 then
if ahbsi.hmastlock = '0' then
v.hresp := HRESP_SPLIT;
v.splmst := ahbsi.hmaster;
v.unsplit := '1';
else
v.ahbcancel := r.insplit;
end if;
v.insplit := not ahbsi.hmastlock;
end if;
else
-- Core is busy, transfer is not locked respond with SPLIT
v.hready := '0';
if split /= 0 then
v.hresp := HRESP_SPLIT;
v.hsplit(conv_integer(ahbsi.hmaster)) := '1';
end if;
end if;
else
v.hsel := '0';
end if;
end if;
if (r.hready = '0') then
if (r.hresp = HRESP_OKAY) then v.hready := '0';
else v.hresp := r.hresp; end if;
end if;
if r.acc = '1' then
-- Propagate data
if r.active = '0' then
if mode /= 1 then
if r.haddr(1) = '0' then v.wdata := hwdata(ACEDW+15 downto 16);
else v.wdata := hwdata(ACEDW-1 downto 0); end if;
else
case r.haddr(1 downto 0) is
when "00" => v.wdata(7 downto 0) := hwdata(31 downto 24);
when "01" => v.wdata(7 downto 0) := hwdata(23 downto 16);
when "10" => v.wdata(7 downto 0) := hwdata(15 downto 8);
when others => v.wdata(7 downto 0) := hwdata(7 downto 0);
end case;
end if;
if mode = 2 then
-- Override writes to busmode register
if r.haddr(6 downto 1) = zero32(6 downto 1) then
v.wdata := (others => '0'); -- Byte
end if;
end if;
end if;
-- Remove access signal when access is done
if r.sync.accdone(1) = '1' then
v.acc := '0';
end if;
v.active := '1';
end if;
-- AMBA response when access is complete
if r.acc = '0' and r.sync.accdone(1) = '0' and r.active = '1' then
if split /= 0 and r.unsplit = '1' then
hsplit(conv_integer(r.splmst)) := '1';
v.unsplit := '0';
end if;
if ((split = 0 or v.ahbcancel = '0') and
(split = 0 or ahbsi.hmaster = r.splmst or r.insplit = '0') and
(((ahbsi.hsel(hindex) and ahbsi.hready and ahbsi.htrans(1)) = '1') or
((split = 0 or r.insplit = '0') and r.hready = '0' and r.hresp = HRESP_OKAY))) then
v.hresp := HRESP_OKAY;
if split /= 0 then
v.insplit := '0';
v.hsplit := r.hsplit;
end if;
v.hready := '1';
v.hsel := '0';
v.active := '0';
elsif split /= 0 and v.ahbcancel = '1' then
v.acc := '1';
v.ahbcancel := '0';
end if;
end if;
-- Interrupt request, not filtered, pulsed
if (not r.sync.irq(2) and r.sync.irq(1)) = '1' then
v.irq := '1';
end if;
-- Reset
if rstn = '0' then
v.acc := '0';
v.active := '0';
--
v.insplit := '0';
v.unsplit := '0';
v.hready := '1';
v.hwrite := '0';
v.hsel := '0';
v.hmbsel := (others => '0');
v.ahbcancel := '0';
end if;
if split = 0 then
v.insplit := '0';
v.unsplit := '0';
v.splmst := (others => '0');
v.hsplit := (others => '0');
v.ahbcancel := '0';
end if;
-- Update registers
rin <= v;
-- AHB slave output
ahbso.hready <= r.hready;
ahbso.hresp <= r.hresp;
ahbso.hrdata <= ahbdrivedata(s.rdata); -- Bad, but does not toggle much
ahbso.hconfig <= HCONFIG;
ahbso.hirq <= irq;
ahbso.hindex <= hindex;
ahbso.hsplit <= hsplit;
end process combsys;
regsys: process (clk)
begin -- process reg
if rising_edge(clk) then
r <= rin;
end if;
end process regsys;
-----------------------------------------------------------------------------
-- System ACE clock domain
-----------------------------------------------------------------------------
combace: process (r, s, rstn, acei)
variable v : ace_reg_type;
begin -- process comb
v := s;
-- Synchronize inputs
v.sync.acc := s.sync.acc(0) & r.acc;
v.sync.rstn := s.sync.rstn(0) & rstn;
v.sync.hwrite := s.sync.hwrite(0) & r.hwrite;
if mode = 2 then
-- Fake reads from BUSMODE register?
v.sync.dummy := s.sync.dummy(0) & not orv(r.haddr(6 downto 1));
else
v.sync.dummy := (others => '0');
end if;
case s.state is
when idle =>
v.aceo.addr := r.haddr(6 downto 0);
if mode = 2 then v.aceo.do(7 downto 0) := r.wdata(7 downto 0);
else v.aceo.do(r.wdata'range) := condhswap(r.wdata); end if;
if s.sync.acc(1) = '1' then
v.aceo.cen := '0';
v.aceo.doen := INPUT xor r.hwrite;
v.state := en;
end if;
if mode = 2 then v.edone := '0'; end if;
when en =>
v.aceo.wen := not r.hwrite;
if s.sync.hwrite(1) = '1' then
v.state := done;
else
v.state := rd;
end if;
when rd =>
v.aceo.oen := '0';
v.state := done;
when done =>
v.aceo.oen := '1';
v.aceo.wen := '1';
if mode = 2 and s.edone = '0' then
-- Keep 16-bit address map
v.aceo.addr(0) := '1';
v.aceo.do(7 downto 0) := r.wdata(ACEDW-1 downto ACEDW-8);
v.rdata(7 downto 0) := acei.di(7 downto 0);
v.edone := '1';
v.state := en;
else
v.aceo.cen := '1';
if s.accdone = '0' then
if mode = 2 then
v.rdata(ACEDW-1 downto ACEDW-8) := acei.di(7 downto 0);
if s.sync.dummy(1) = '1' then -- Fake read
v.rdata := (others => '0'); v.rdata(0) := '1';
end if;
else
v.rdata := condhswap(acei.di)(s.rdata'range);
end if;
v.accdone := '1';
else
v.aceo.doen := INPUT;
end if;
if s.sync.acc(1) = '0' then
v.state := idle;
v.accdone := '0';
end if;
end if;
end case;
-- Reset
if s.sync.rstn(1) = '0' then
v.state := idle;
v.accdone := '0';
v.aceo.cen := '1';
v.aceo.wen := '1';
v.aceo.oen := '1';
v.aceo.doen := INPUT;
end if;
if mode = 1 then v.aceo.do(15 downto 8) := (others => '0'); end if;
if mode /= 2 then v.edone := '0'; end if;
-- Update registers
sin <= v;
-- Assign outputs to System ACE
aceo <= s.aceo;
end process combace;
regace: process (clkace)
begin -- process reg
if rising_edge(clkace) then
s <= sin;
end if;
end process regace;
-- Boot message
-- pragma translate_off
bootmsg : report_version
generic map (
"gracectrl" & tost(hindex) & ": System ACE I/F Controller, rev " &
tost(REVISION) & ", irq " & tost(hirq));
-- pragma translate_on
end rtl;
| gpl-3.0 | a30f31b0644b9cd8c071670baa5d46cc | 0.485501 | 3.760021 | false | false | false | false |
hterkelsen/mal | vhdl/types.vhdl | 17 | 13,485 | library STD;
use STD.textio.all;
package types is
procedure debugline(l: inout line);
procedure debug(str: in string);
procedure debug(ch: in character);
procedure debug(i: in integer);
type mal_type_tag is (mal_nil, mal_true, mal_false, mal_number,
mal_symbol, mal_string, mal_keyword,
mal_list, mal_vector, mal_hashmap,
mal_atom, mal_nativefn, mal_fn);
-- Forward declarations
type mal_val;
type mal_seq;
type mal_func;
type env_record;
type mal_val_ptr is access mal_val;
type mal_seq_ptr is access mal_seq;
type mal_func_ptr is access mal_func;
type env_ptr is access env_record;
type mal_val is record
val_type: mal_type_tag;
number_val: integer; -- For types: number
string_val: line; -- For types: symbol, string, keyword, nativefn
seq_val: mal_seq_ptr; -- For types: list, vector, hashmap, atom
func_val: mal_func_ptr; -- For fn
meta_val: mal_val_ptr;
end record mal_val;
type mal_seq is array (natural range <>) of mal_val_ptr;
type mal_func is record
f_body: mal_val_ptr;
f_args: mal_val_ptr;
f_env: env_ptr;
f_is_macro: boolean;
end record mal_func;
type env_record is record
outer: env_ptr;
data: mal_val_ptr;
end record env_record;
procedure new_nil(obj: out mal_val_ptr);
procedure new_true(obj: out mal_val_ptr);
procedure new_false(obj: out mal_val_ptr);
procedure new_boolean(b: in boolean; obj: out mal_val_ptr);
procedure new_number(v: in integer; obj: out mal_val_ptr);
procedure new_symbol(name: in string; obj: out mal_val_ptr);
procedure new_symbol(name: inout line; obj: out mal_val_ptr);
procedure new_string(name: in string; obj: out mal_val_ptr);
procedure new_string(name: inout line; obj: out mal_val_ptr);
procedure new_keyword(name: in string; obj: out mal_val_ptr);
procedure new_keyword(name: inout line; obj: out mal_val_ptr);
procedure new_nativefn(name: in string; obj: out mal_val_ptr);
procedure new_fn(body_ast: inout mal_val_ptr; args: inout mal_val_ptr; env: inout env_ptr; obj: out mal_val_ptr);
procedure new_seq_obj(seq_type: in mal_type_tag; seq: inout mal_seq_ptr; obj: out mal_val_ptr);
procedure new_one_element_list(val: inout mal_val_ptr; obj: out mal_val_ptr);
procedure new_empty_hashmap(obj: out mal_val_ptr);
procedure new_atom(val: inout mal_val_ptr; obj: out mal_val_ptr);
procedure hashmap_copy(hashmap: inout mal_val_ptr; obj: out mal_val_ptr);
procedure hashmap_get(hashmap: inout mal_val_ptr; key: inout mal_val_ptr; val: out mal_val_ptr);
procedure hashmap_contains(hashmap: inout mal_val_ptr; key: inout mal_val_ptr; ok: out boolean);
procedure hashmap_put(hashmap: inout mal_val_ptr; key: inout mal_val_ptr; val: inout mal_val_ptr);
procedure hashmap_delete(hashmap: inout mal_val_ptr; key: inout mal_val_ptr);
procedure seq_drop_prefix(src: inout mal_val_ptr; prefix_length: in integer; result: out mal_val_ptr);
function is_sequential_type(t: in mal_type_tag) return boolean;
procedure equal_q(a: inout mal_val_ptr; b: inout mal_val_ptr; result: out boolean);
end package types;
package body types is
procedure debugline(l: inout line) is
variable l2: line;
begin
l2 := new string(1 to 7 + l'length);
l2(1 to l2'length) := "DEBUG: " & l.all;
writeline(output, l2);
end procedure debugline;
procedure debug(str: in string) is
variable d: line;
begin
write(d, str);
debugline(d);
end procedure debug;
procedure debug(ch: in character) is
variable d: line;
begin
write(d, ch);
debugline(d);
end procedure debug;
procedure debug(i: in integer) is
variable d: line;
begin
write(d, i);
debugline(d);
end procedure debug;
procedure new_nil(obj: out mal_val_ptr) is
begin
obj := new mal_val'(val_type => mal_nil, number_val => 0, string_val => null, seq_val => null, func_val => null, meta_val => null);
end procedure new_nil;
procedure new_true(obj: out mal_val_ptr) is
begin
obj := new mal_val'(val_type => mal_true, number_val => 0, string_val => null, seq_val => null, func_val => null, meta_val => null);
end procedure new_true;
procedure new_false(obj: out mal_val_ptr) is
begin
obj := new mal_val'(val_type => mal_false, number_val => 0, string_val => null, seq_val => null, func_val => null, meta_val => null);
end procedure new_false;
procedure new_boolean(b: in boolean; obj: out mal_val_ptr) is
begin
if b then
new_true(obj);
else
new_false(obj);
end if;
end procedure new_boolean;
procedure new_number(v: in integer; obj: out mal_val_ptr) is
begin
obj := new mal_val'(val_type => mal_number, number_val => v, string_val => null, seq_val => null, func_val => null, meta_val => null);
end procedure new_number;
procedure new_symbol(name: in string; obj: out mal_val_ptr) is
begin
obj := new mal_val'(val_type => mal_symbol, number_val => 0, string_val => new string'(name), seq_val => null, func_val => null, meta_val => null);
end procedure new_symbol;
procedure new_symbol(name: inout line; obj: out mal_val_ptr) is
begin
obj := new mal_val'(val_type => mal_symbol, number_val => 0, string_val => name, seq_val => null, func_val => null, meta_val => null);
end procedure new_symbol;
procedure new_string(name: in string; obj: out mal_val_ptr) is
begin
obj := new mal_val'(val_type => mal_string, number_val => 0, string_val => new string'(name), seq_val => null, func_val => null, meta_val => null);
end procedure new_string;
procedure new_string(name: inout line; obj: out mal_val_ptr) is
begin
obj := new mal_val'(val_type => mal_string, number_val => 0, string_val => name, seq_val => null, func_val => null, meta_val => null);
end procedure new_string;
procedure new_keyword(name: in string; obj: out mal_val_ptr) is
begin
obj := new mal_val'(val_type => mal_keyword, number_val => 0, string_val => new string'(name), seq_val => null, func_val => null, meta_val => null);
end procedure new_keyword;
procedure new_keyword(name: inout line; obj: out mal_val_ptr) is
begin
obj := new mal_val'(val_type => mal_keyword, number_val => 0, string_val => name, seq_val => null, func_val => null, meta_val => null);
end procedure new_keyword;
procedure new_nativefn(name: in string; obj: out mal_val_ptr) is
begin
obj := new mal_val'(val_type => mal_nativefn, number_val => 0, string_val => new string'(name), seq_val => null, func_val => null, meta_val => null);
end procedure new_nativefn;
procedure new_fn(body_ast: inout mal_val_ptr; args: inout mal_val_ptr; env: inout env_ptr; obj: out mal_val_ptr) is
variable f: mal_func_ptr;
begin
f := new mal_func'(f_body => body_ast, f_args => args, f_env => env, f_is_macro => false);
obj := new mal_val'(val_type => mal_fn, number_val => 0, string_val => null, seq_val => null, func_val => f, meta_val => null);
end procedure new_fn;
procedure new_seq_obj(seq_type: in mal_type_tag; seq: inout mal_seq_ptr; obj: out mal_val_ptr) is
begin
obj := new mal_val'(val_type => seq_type, number_val => 0, string_val => null, seq_val => seq, func_val => null, meta_val => null);
end procedure new_seq_obj;
procedure new_one_element_list(val: inout mal_val_ptr; obj: out mal_val_ptr) is
variable seq: mal_seq_ptr;
begin
seq := new mal_seq(0 to 0);
seq(0) := val;
new_seq_obj(mal_list, seq, obj);
end procedure new_one_element_list;
procedure new_empty_hashmap(obj: out mal_val_ptr) is
variable seq: mal_seq_ptr;
begin
seq := new mal_seq(0 to -1);
new_seq_obj(mal_hashmap, seq, obj);
end procedure new_empty_hashmap;
procedure new_atom(val: inout mal_val_ptr; obj: out mal_val_ptr) is
variable atom_seq: mal_seq_ptr;
begin
atom_seq := new mal_seq(0 to 0);
atom_seq(0) := val;
new_seq_obj(mal_atom, atom_seq, obj);
end procedure new_atom;
procedure hashmap_copy(hashmap: inout mal_val_ptr; obj: out mal_val_ptr) is
variable new_seq: mal_seq_ptr;
begin
new_seq := new mal_seq(hashmap.seq_val'range);
new_seq(new_seq'range) := hashmap.seq_val(hashmap.seq_val'range);
new_seq_obj(mal_hashmap, new_seq, obj);
end procedure hashmap_copy;
procedure hashmap_get(hashmap: inout mal_val_ptr; key: inout mal_val_ptr; val: out mal_val_ptr) is
variable i: natural;
variable curr_key: mal_val_ptr;
begin
i := 0;
while i < hashmap.seq_val'length loop
curr_key := hashmap.seq_val(i);
if key.val_type = curr_key.val_type and key.string_val.all = curr_key.string_val.all then
val := hashmap.seq_val(i + 1);
return;
end if;
i := i + 2;
end loop;
val := null;
end procedure hashmap_get;
procedure hashmap_contains(hashmap: inout mal_val_ptr; key: inout mal_val_ptr; ok: out boolean) is
variable val: mal_val_ptr;
begin
hashmap_get(hashmap, key, val);
if val = null then
ok := false;
else
ok := true;
end if;
end procedure hashmap_contains;
procedure hashmap_put(hashmap: inout mal_val_ptr; key: inout mal_val_ptr; val: inout mal_val_ptr) is
variable i: natural;
variable curr_key: mal_val_ptr;
variable new_seq: mal_seq_ptr;
begin
i := 0;
while i < hashmap.seq_val'length loop
curr_key := hashmap.seq_val(i);
if key.val_type = curr_key.val_type and key.string_val.all = curr_key.string_val.all then
hashmap.seq_val(i + 1) := val;
return;
end if;
i := i + 2;
end loop;
-- Not found so far, need to extend the seq
new_seq := new mal_seq(0 to hashmap.seq_val'length + 1);
for i in hashmap.seq_val'range loop
new_seq(i) := hashmap.seq_val(i);
end loop;
new_seq(new_seq'length - 2) := key;
new_seq(new_seq'length - 1) := val;
deallocate(hashmap.seq_val);
hashmap.seq_val := new_seq;
end procedure hashmap_put;
procedure hashmap_delete(hashmap: inout mal_val_ptr; key: inout mal_val_ptr) is
variable i, dst_i: natural;
variable curr_key: mal_val_ptr;
variable new_seq: mal_seq_ptr;
variable found: boolean;
begin
hashmap_contains(hashmap, key, found);
if not found then
return;
end if;
i := 0;
dst_i := 0;
new_seq := new mal_seq(0 to hashmap.seq_val'high - 2);
while i < hashmap.seq_val'length loop
curr_key := hashmap.seq_val(i);
if key.val_type = curr_key.val_type and key.string_val.all = curr_key.string_val.all then
i := i + 2;
else
new_seq(dst_i to dst_i + 1) := hashmap.seq_val(i to i + 1);
dst_i := dst_i + 2;
i := i + 2;
end if;
end loop;
deallocate(hashmap.seq_val);
hashmap.seq_val := new_seq;
end procedure hashmap_delete;
procedure seq_drop_prefix(src: inout mal_val_ptr; prefix_length: in integer; result: out mal_val_ptr) is
variable seq: mal_seq_ptr;
begin
seq := new mal_seq(0 to src.seq_val'length - 1 - prefix_length);
for i in seq'range loop
seq(i) := src.seq_val(i + prefix_length);
end loop;
new_seq_obj(src.val_type, seq, result);
end procedure seq_drop_prefix;
function is_sequential_type(t: in mal_type_tag) return boolean is
begin
return t = mal_list or t = mal_vector;
end function is_sequential_type;
procedure equal_seq_q(a: inout mal_val_ptr; b: inout mal_val_ptr; result: out boolean) is
variable i: integer;
variable is_element_equal: boolean;
begin
if a.seq_val'length = b.seq_val'length then
for i in a.seq_val'range loop
equal_q(a.seq_val(i), b.seq_val(i), is_element_equal);
if not is_element_equal then
result := false;
return;
end if;
end loop;
result := true;
else
result := false;
end if;
end procedure equal_seq_q;
procedure equal_hashmap_q(a: inout mal_val_ptr; b: inout mal_val_ptr; result: out boolean) is
variable i: integer;
variable is_value_equal: boolean;
variable b_val: mal_val_ptr;
begin
if a.seq_val'length = b.seq_val'length then
i := 0;
while i < a.seq_val'length loop
hashmap_get(b, a.seq_val(i), b_val);
if b_val = null then
result := false;
return;
else
equal_q(a.seq_val(i + 1), b_val, is_value_equal);
if not is_value_equal then
result := false;
return;
end if;
end if;
i := i + 2;
end loop;
result := true;
else
result := false;
end if;
end procedure equal_hashmap_q;
procedure equal_q(a: inout mal_val_ptr; b: inout mal_val_ptr; result: out boolean) is
begin
if is_sequential_type(a.val_type) and is_sequential_type(b.val_type) then
equal_seq_q(a, b, result);
elsif a.val_type = b.val_type then
case a.val_type is
when mal_nil | mal_true | mal_false =>
result := true;
when mal_number =>
result := a.number_val = b.number_val;
when mal_symbol | mal_string | mal_keyword =>
result := a.string_val.all = b.string_val.all;
when mal_hashmap =>
equal_hashmap_q(a, b, result);
when mal_atom =>
equal_q(a.seq_val(0), b.seq_val(0), result);
when others =>
result := false;
end case;
else
result := false;
end if;
end procedure equal_q;
end package body types;
| mpl-2.0 | 7a6fb01942f194eec45c397d267d6b8c | 0.634854 | 3.133132 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-xilinx-ml40x/testbench.vhd | 1 | 10,427 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
library cypress;
use cypress.components.all;
use work.debug.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 10; -- system clock period
romwidth : integer := 32; -- rom data width (8/32)
romdepth : integer := 16; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 18; -- ram address depth
srambanks : integer := 2 -- number of ram banks
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal sys_clk : std_logic := '0';
signal sys_rst_in : std_logic := '0'; -- Reset
signal sysace_clk_in : std_ulogic := '0';
constant ct : integer := clkperiod/2;
signal plb_error : std_logic;
signal opb_error : std_logic;
signal flash_a23 : std_ulogic;
signal sram_flash_addr : std_logic_vector(22 downto 0);
signal sram_flash_data : std_logic_vector(31 downto 0);
signal sram_cen : std_logic;
signal sram_bw : std_logic_vector (3 downto 0);
signal sram_flash_oe_n : std_ulogic;
signal sram_flash_we_n : std_ulogic;
signal flash_ce : std_logic;
signal sram_clk : std_ulogic;
signal sram_clk_fb : std_ulogic;
signal sram_mode : std_ulogic;
signal sram_adv_ld_n : std_ulogic;
signal sram_zz : std_ulogic;
signal iosn : std_ulogic;
signal ddr_clk : std_logic;
signal ddr_clkb : std_logic;
signal ddr_clk_fb : std_logic;
signal ddr_cke : std_logic;
signal ddr_csb : std_logic;
signal ddr_web : std_ulogic; -- ddr write enable
signal ddr_rasb : std_ulogic; -- ddr ras
signal ddr_casb : std_ulogic; -- ddr cas
signal ddr_dm : std_logic_vector (3 downto 0); -- ddr dm
signal ddr_dqs : std_logic_vector (3 downto 0); -- ddr dqs
signal ddr_ad : std_logic_vector (12 downto 0); -- ddr address
signal ddr_ba : std_logic_vector (1 downto 0); -- ddr bank address
signal ddr_dq : std_logic_vector (31 downto 0); -- ddr data
signal txd1 : std_ulogic; -- UART1 tx data
signal rxd1 : std_ulogic; -- UART1 rx data
signal gpio : std_logic_vector(26 downto 0); -- I/O port
signal phy_mii_data: std_logic; -- ethernet PHY interface
signal phy_tx_clk : std_ulogic;
signal phy_rx_clk : std_ulogic;
signal phy_rx_data : std_logic_vector(7 downto 0);
signal phy_dv : std_ulogic;
signal phy_rx_er : std_ulogic;
signal phy_col : std_ulogic;
signal phy_crs : std_ulogic;
signal phy_tx_data : std_logic_vector(7 downto 0);
signal phy_tx_en : std_ulogic;
signal phy_tx_er : std_ulogic;
signal phy_mii_clk : std_ulogic;
signal phy_rst_n : std_ulogic;
signal phy_gtx_clk : std_ulogic;
signal phy_int_n : std_ulogic;
signal ps2_keyb_clk: std_logic;
signal ps2_keyb_data: std_logic;
signal ps2_mouse_clk: std_logic;
signal ps2_mouse_data: std_logic;
signal tft_lcd_clk : std_ulogic;
signal vid_blankn : std_ulogic;
signal vid_syncn : std_ulogic;
signal vid_hsync : std_ulogic;
signal vid_vsync : std_ulogic;
signal vid_r : std_logic_vector(7 downto 0);
signal vid_g : std_logic_vector(7 downto 0);
signal vid_b : std_logic_vector(7 downto 0);
signal usb_csn : std_logic;
signal flash_cex : std_logic;
signal iic_scl : std_logic;
signal iic_sda : std_logic;
signal sace_usb_a : std_logic_vector(6 downto 0);
signal sace_mpce : std_ulogic;
signal sace_usb_d : std_logic_vector(15 downto 0);
signal sace_usb_oen : std_ulogic;
signal sace_usb_wen : std_ulogic;
signal sysace_mpirq : std_ulogic;
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal spw_clk : std_ulogic := '0';
signal spw_rxdp : std_logic_vector(0 to 2) := "000";
signal spw_rxdn : std_logic_vector(0 to 2) := "000";
signal spw_rxsp : std_logic_vector(0 to 2) := "000";
signal spw_rxsn : std_logic_vector(0 to 2) := "000";
signal spw_txdp : std_logic_vector(0 to 2);
signal spw_txdn : std_logic_vector(0 to 2);
signal spw_txsp : std_logic_vector(0 to 2);
signal spw_txsn : std_logic_vector(0 to 2);
signal datazz : std_logic_vector(0 to 3);
constant lresp : boolean := false;
begin
-- clock and reset
sys_clk <= not sys_clk after ct * 1 ns;
sys_rst_in <= '0', '1' after 200 ns;
sysace_clk_in <= not sysace_clk_in after 15 ns;
rxd1 <= 'H';
sram_clk_fb <= sram_clk; ddr_clk_fb <= ddr_clk;
ps2_keyb_data <= 'H'; ps2_keyb_clk <= 'H';
ps2_mouse_clk <= 'H'; ps2_mouse_data <= 'H';
iic_scl <= 'H'; iic_sda <= 'H';
flash_cex <= not flash_ce;
sace_usb_d <= (others => 'H'); sysace_mpirq <= 'L';
cpu : entity work.leon3mp
generic map ( fabtech, memtech, padtech, ncpu, disas, dbguart, pclow )
port map ( sys_rst_in, sys_clk, sysace_clk_in, plb_error, opb_error, flash_a23,
sram_flash_addr, sram_flash_data, sram_cen, sram_bw, sram_flash_oe_n,
sram_flash_we_n, flash_ce, sram_clk, sram_clk_fb, sram_mode, sram_adv_ld_n, iosn,
ddr_clk, ddr_clkb, ddr_clk_fb, ddr_cke, ddr_csb, ddr_web, ddr_rasb,
ddr_casb, ddr_dm, ddr_dqs, ddr_ad, ddr_ba, ddr_dq,
txd1, rxd1, gpio, phy_gtx_clk, phy_mii_data, phy_tx_clk, phy_rx_clk,
phy_rx_data, phy_dv, phy_rx_er, phy_col, phy_crs, phy_int_n,
phy_tx_data, phy_tx_en, phy_tx_er, phy_mii_clk, phy_rst_n, ps2_keyb_clk,
ps2_keyb_data, ps2_mouse_clk, ps2_mouse_data, tft_lcd_clk, vid_blankn, vid_syncn,
vid_hsync, vid_vsync, vid_r, vid_g, vid_b,
usb_csn,
iic_scl, iic_sda,
sace_usb_a, sace_mpce, sace_usb_d, sace_usb_oen, sace_usb_wen,
sysace_mpirq
);
datazz <= "HHHH";
u0 : cy7c1354 generic map (fname => sramfile, tWEH => 0.0 ns, tAH => 0.0 ns)
port map(
Dq(35 downto 32) => datazz, Dq(31 downto 0) => sram_flash_data,
Addr => sram_flash_addr(17 downto 0), Mode => sram_mode,
Clk => sram_clk, CEN_n => gnd, AdvLd_n => sram_adv_ld_n,
Bwa_n => sram_bw(3), Bwb_n => sram_bw(2),
Bwc_n => sram_bw(1), Bwd_n => sram_bw(0),
Rw_n => sram_flash_we_n, Oe_n => sram_flash_oe_n,
Ce1_n => sram_cen,
Ce2 => vcc,
Ce3_n => gnd,
Zz => sram_zz);
sram_zz <= '0';
-- u1 : mt46v16m16
-- generic map (index => 1, fname => sdramfile, bbits => 32)
-- PORT MAP(
-- Dq => ddr_dq(15 downto 0), Dqs => ddr_dqs(1 downto 0), Addr => ddr_ad(12 downto 0),
-- Ba => ddr_ba, Clk => ddr_clk, Clk_n => ddr_clkb, Cke => ddr_cke,
-- Cs_n => ddr_csb, Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web,
-- Dm => ddr_dm(1 downto 0));
-- u2 : mt46v16m16
-- generic map (index => 0, fname => sdramfile, bbits => 32)
-- PORT MAP(
-- Dq => ddr_dq(31 downto 16), Dqs => ddr_dqs(3 downto 2), Addr => ddr_ad(12 downto 0),
-- Ba => ddr_ba, Clk => ddr_clk, Clk_n => ddr_clkb, Cke => ddr_cke,
-- Cs_n => ddr_csb, Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web,
-- Dm => ddr_dm(3 downto 2));
ddr0 : ddrram
generic map(width => 32, abits => 13, colbits => 9, rowbits => 13,
implbanks => 1, fname => sdramfile, density => 2)
port map (ck => ddr_clk, cke => ddr_cke, csn => ddr_csb,
rasn => ddr_rasb, casn => ddr_casb, wen => ddr_web,
dm => ddr_dm, ba => ddr_ba, a => ddr_ad, dq => ddr_dq,
dqs => ddr_dqs);
prom0 : for i in 0 to (romwidth/8)-1 generate
sr0 : sram generic map (index => i, abits => romdepth, fname => promfile)
port map (sram_flash_addr(romdepth-1 downto 0), sram_flash_data(31-i*8 downto 24-i*8),
flash_cex, sram_bw(i), sram_flash_oe_n);
end generate;
phy_mii_data <= 'H';
p0: phy
port map(sys_rst_in, phy_mii_data, phy_tx_clk, phy_rx_clk, phy_rx_data, phy_dv,
phy_rx_er, phy_col, phy_crs, phy_tx_data, phy_tx_en, phy_tx_er, phy_mii_clk, phy_gtx_clk);
i0: i2c_slave_model
port map (iic_scl, iic_sda);
plb_error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 5000 ns;
if to_x01(plb_error) = '1' then wait on plb_error; end if;
assert (to_x01(plb_error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
test0 : grtestmod
port map ( sys_rst_in, sys_clk, plb_error, sram_flash_addr(19 downto 0), sram_flash_data,
iosn, sram_flash_oe_n, sram_bw(0), open);
sram_flash_data <= buskeep(sram_flash_data), (others => 'H') after 250 ns;
ddr_dq <= buskeep(ddr_dq), (others => 'H') after 250 ns;
end ;
| gpl-3.0 | 355fa166f155141e930ef46f30e4627f | 0.611393 | 2.997126 | false | false | false | false |
yishinli/emc2 | src/hal/drivers/m5i20/hostmot5_src/hostmot5-8eh.vhd | 1 | 26,659 | library IEEE;
use IEEE.std_logic_1164.all; -- defines std_logic types
library UNISIM;
use UNISIM.VComponents.all;
-- 8 axis version with 24 I/O bits - 100 MHz PWM and basic timing
entity HostMot5_8EH is
port
(
LRD: in STD_LOGIC;
LWR: in STD_LOGIC;
LW_R: in STD_LOGIC;
ALE: in STD_LOGIC;
ADS: in STD_LOGIC;
BLAST: in STD_LOGIC;
WAITO: in STD_LOGIC;
LOCKO: in STD_LOGIC;
CS0: in STD_LOGIC;
CS1: in STD_LOGIC;
READY: out STD_LOGIC;
INT: out STD_LOGIC;
LAD: inout STD_LOGIC_VECTOR (31 downto 0); -- data/address bus
LA: in STD_LOGIC_VECTOR (8 downto 2); -- non-muxed address bus
lBE: in STD_LOGIC_VECTOR (3 downto 0); -- byte enables
SYNCLK: in STD_LOGIC;
LCLK: in STD_LOGIC;
-- I/O signals
A: in STD_LOGIC_VECTOR (7 downto 0);
B: in STD_LOGIC_VECTOR (7 downto 0);
IDX: in STD_LOGIC_VECTOR (7 downto 0);
PWM: inout STD_LOGIC_VECTOR (7 downto 0);
ENA: out STD_LOGIC_VECTOR (7 downto 0);
DIR: inout STD_LOGIC_VECTOR (7 downto 0);
IOBITSA: inout STD_LOGIC_VECTOR (23 downto 0);
-- IOBITSB: inout STD_LOGIC_VECTOR (23 downto 0);
-- led bits
LEDS: out STD_LOGIC_VECTOR(7 downto 0)
);
end HostMot5_8EH; -- for 5I20 or 4I65
architecture dataflow of Hostmot5_8EH is
alias BLE: STD_LOGIC is LBE(0); -- 16 bit mode
alias BHE: STD_LOGIC is LBE(3); -- 16 bit mode
alias LA1: STD_LOGIC is LBE(1); -- 8/16 bit mode
alias LA0: STD_LOGIC is LBE(0); -- 8 bit mode
-- misc global signals --
signal D: STD_LOGIC_VECTOR (31 downto 0); -- internal data bus
signal LatchedA: STD_LOGIC_VECTOR (15 downto 0);
signal LatchedLBE: STD_LOGIC_VECTOR (3 downto 0);
signal PreFastRead: STD_LOGIC;
signal FastRead: STD_LOGIC;
-- Version specific constants --
constant counters :integer := 8;
constant HMID : STD_LOGIC_VECTOR (31 downto 0) := x"AA020008"; -- MSW = rev 1, LSW = 8 axis
constant MasterClock : STD_LOGIC_VECTOR (31 downto 0) := x"05F5E100"; -- = 100 MHz
-- misc global signals --
signal CardSelect: STD_LOGIC; -- card select decode
signal LEDView: STD_LOGIC_VECTOR (7 downto 0); -- index register
signal FClk: STD_LOGIC; -- high speed clock = 100 MHz
signal CLKFB: STD_LOGIC;
signal CLK0: STD_LOGIC;
signal CLK2X: STD_LOGIC;
-- irq related signals
signal IRQSource: STD_LOGIC;
signal IRQLatch: STD_LOGIC;
signal IRQMask: STD_LOGIC;
signal MissedIRQ: STD_LOGIC;
signal StopOnMissedIRQ: STD_LOGIC;
signal ClearMissedIRQ: STD_LOGIC;
signal LatchOnInterrupt: STD_LOGIC;
-- timeout related signals
signal ReloadWDCmd: STD_LOGIC;
signal StopOnTimeout: STD_LOGIC;
signal WDTimeOut: STD_LOGIC;
-- LEDView and id reg signals
signal LoadLEDViewCmd: STD_LOGIC;
signal ReadLEDViewCmd: STD_LOGIC;
signal Enasigs :STD_LOGIC_VECTOR (counters-1 downto 0);
signal IDSel: STD_LOGIC;
signal ReadIDCmd: STD_LOGIC;
signal MCSel: STD_LOGIC;
signal ReadMCCmd: STD_LOGIC;
-- irqdiv reg signals
signal ReadIRQDivCmd: STD_LOGIC;
signal LoadIRQDivCmd: STD_LOGIC;
signal ClearIRQCmd: STD_LOGIC;
-- irq sel reg signals
signal loadGCRCmd: STD_LOGIC;
signal LoadGMRCmd: STD_LOGIC;
signal ReadGMRCmd: STD_LOGIC;
-- timeout reg signals
signal loadTimeoutCmd: STD_LOGIC;
signal ReadTimeoutCmd: STD_LOGIC;
signal ReadTimerCmd: STD_LOGIC;
-- phase accumulator signals
signal ReadPhaseCmd: STD_LOGIC;
signal LoadPhaseCmd: STD_LOGIC;
-- counter signals --
signal CounterRead: STD_LOGIC_VECTOR (counters-1 downto 0); -- read counter
signal GlobalCounterEnable: STD_LOGIC; -- enable counting
signal GlobalCountLatchcmd: STD_LOGIC; -- command to latch counter value
signal GlobalCountLatch: STD_LOGIC; -- command + irq generated latch count
signal CountLatchEdge1: STD_LOGIC;
signal CountLatchEdge2: STD_LOGIC;
signal CCRLoadCmds: STD_LOGIC_VECTOR (counters-1 downto 0); -- counter control reg loads
signal CCRReadCmds: STD_LOGIC_VECTOR (counters-1 downto 0); -- counter control reg reads
signal GlobalCounterClear: STD_LOGIC; -- clear counter
-- secondary counter signals --
signal SCounterRead: STD_LOGIC_VECTOR (counters-1 downto 0); -- read counter
signal SCCRLoadCmds: STD_LOGIC_VECTOR (counters-1 downto 0); -- counter control reg loads
signal SCCRReadCmds: STD_LOGIC_VECTOR (counters-1 downto 0); -- counter control reg reads
-- pwm generator signals --
signal RefCountBus: STD_LOGIC_VECTOR (9 downto 0);
signal LoadPWM: STD_LOGIC_VECTOR (counters-1 downto 0);
signal ReadPWM: STD_LOGIC_VECTOR (counters-1 downto 0);
signal PCRLoadCmds: STD_LOGIC_VECTOR (counters-1 downto 0);
signal PCRReadCmds: STD_LOGIC_VECTOR (counters-1 downto 0);
signal GlobalPWMEnable: STD_LOGIC;
signal GlobalClearPWM: STD_LOGIC;
signal GlobalClearPWMCmd: STD_LOGIC;
signal StopPWM: STD_LOGIC;
-- misc i/o signals
signal PortASel: STD_LOGIC;
signal DDRASel: STD_LOGIC;
signal LoadPortA: STD_LOGIC;
signal LoadDDRA: STD_LOGIC;
signal ReadDDRA: STD_LOGIC;
signal ReadPortA: STD_LOGIC;
signal PortBSel: STD_LOGIC;
signal DDRBSel: STD_LOGIC;
signal LoadPortB: STD_LOGIC;
signal LoadDDRB: STD_LOGIC;
signal ReadDDRB: STD_LOGIC;
signal ReadPortB: STD_LOGIC;
-- decodes --
signal LEDViewSel: STD_LOGIC;
signal IndexSel: STD_LOGIC;
signal GCRSel: STD_LOGIC;
signal GMRSel: STD_LOGIC;
signal CCRSel: STD_LOGIC;
signal SCCRSel: STD_LOGIC;
signal PCRSel: STD_LOGIC;
signal TimeOutSel: STD_LOGIC;
signal TimerSel: STD_LOGIC;
signal IRQDIVSel: STD_LOGIC;
signal PWMValSel: STD_LOGIC;
signal PhaseSel: STD_LOGIC;
signal CounterSel: STD_LOGIC;
signal SCounterSel: STD_LOGIC;
function OneOfEightDecode(ena : std_logic; dec : std_logic_vector(2 downto 0)) return std_logic_vector is
variable result : std_logic_vector(counters-1 downto 0);
begin
if ena = '1' then
case dec is
when "000" => result := "00000001";
when "001" => result := "00000010";
when "010" => result := "00000100";
when "011" => result := "00001000";
when "100" => result := "00010000";
when "101" => result := "00100000";
when "110" => result := "01000000";
when "111" => result := "10000000";
when others => result := "00000000";
end case;
else
result := "00000000";
end if;
return result;
end OneOfEightDecode;
function OneOfEightMux(sel: std_logic_vector (2 downto 0); input: std_logic_vector(counters-1 downto 0)) return std_logic is
variable result : std_logic;
begin
case sel is
when "000" => result := input(0);
when "001" => result := input(1);
when "010" => result := input(2);
when "011" => result := input(3);
when "100" => result := input(4);
when "101" => result := input(5);
when "110" => result := input(6);
when "111" => result := input(7);
when others => result := '0';
end case;
return result;
end OneOfEightMux;
component indexreg
port (
clk: in STD_LOGIC;
ibus: in STD_LOGIC_VECTOR (15 downto 0);
obus: out STD_LOGIC_VECTOR (15 downto 0);
loadindex: in STD_LOGIC;
readindex: in STD_LOGIC;
index: out STD_LOGIC_VECTOR (7 downto 0)
);
end component;
component counter
port (
obus: out STD_LOGIC_VECTOR (31 downto 0);
ibus: in STD_LOGIC_VECTOR (31 downto 0);
quada: in STD_LOGIC;
quadb: in STD_LOGIC;
index: in STD_LOGIC;
ccrloadcmd: in STD_LOGIC;
ccrreadcmd: in STD_LOGIC;
countoutreadcmd: in STD_LOGIC;
countlatchcmd: in STD_LOGIC;
countclearcmd: in STD_LOGIC;
countenable: in STD_LOGIC;
indexmask: in STD_LOGIC;
nads: in STD_LOGIC;
clk: in STD_LOGIC
);
end component;
component pwmgenh
port (
clk: in STD_LOGIC;
hclk: in STD_LOGIC;
refcount: in STD_LOGIC_VECTOR (9 downto 0);
ibus: in STD_LOGIC_VECTOR (15 downto 0);
obus: out STD_LOGIC_VECTOR (15 downto 0);
loadpwmval: in STD_LOGIC;
readpwmval: in STD_LOGIC;
clearpwmval: in STD_LOGIC;
pcrloadcmd: STD_LOGIC;
pcrreadcmd: STD_LOGIC;
pwmout: out STD_LOGIC;
dirio: inout STD_LOGIC;
enablein: in STD_LOGIC;
enableout: out STD_LOGIC
);
end component pwmgenh;
component pwmrefh is
port (
clk: in STD_LOGIC;
hclk: in STD_LOGIC;
refcount: out STD_LOGIC_VECTOR (9 downto 0);
irqgen: out STD_LOGIC;
ibus: in STD_LOGIC_VECTOR (15 downto 0);
obus: out STD_LOGIC_VECTOR (15 downto 0);
irqdivload: in STD_LOGIC;
irqdivread: in STD_LOGIC;
phaseload: in STD_LOGIC;
phaseread: in STD_LOGIC
);
end component pwmrefh;
component globalcontrolreg is
port (
clk: in STD_LOGIC;
ibus: in STD_LOGIC_VECTOR (15 downto 0);
reset: in STD_LOGIC;
loadgcr: in STD_LOGIC;
ctrclear: out STD_LOGIC;
ctrlatch: out STD_LOGIC;
pwmclear: out STD_LOGIC;
irqclear: out STD_LOGIC;
reloadwd: out STD_LOGIC
);
end component globalcontrolreg;
component globalmodereg is
port (
clk: in STD_LOGIC;
ibus: in STD_LOGIC_VECTOR (15 downto 0);
obus: out STD_LOGIC_VECTOR (15 downto 0);
reset: in STD_LOGIC;
loadglobalmode: in STD_LOGIC;
readglobalmode: in STD_LOGIC;
ctrena: out STD_LOGIC;
pwmena: out STD_LOGIC;
clearpwmena: in STD_LOGIC;
loi: out STD_LOGIC;
som: out STD_LOGIC;
sot: out STD_LOGIC;
miout: out STD_LOGIC;
miin: in STD_LOGIC;
irqmask: out STD_LOGIC;
irqstatus: in STD_LOGIC
);
end component globalmodereg;
component WordPR24 is
port (
clear: in STD_LOGIC;
clk: in STD_LOGIC;
ibus: in STD_LOGIC_VECTOR (23 downto 0);
obus: out STD_LOGIC_VECTOR (23 downto 0);
loadport: in STD_LOGIC;
loadddr: in STD_LOGIC;
readddr: in STD_LOGIC;
portdata: out STD_LOGIC_VECTOR (23 downto 0)
);
end component WordPR24;
component Word24RB is
Port (
obus: out STD_LOGIC_VECTOR (23 downto 0);
readport: in STD_LOGIC;
portdata: in STD_LOGIC_VECTOR (23 downto 0) );
end component Word24RB;
component Timeout is
Port ( clk : in std_logic;
ibus : in std_logic_vector(15 downto 0);
obus : out std_logic_vector(15 downto 0);
timeoutload : in std_logic;
timeoutread : in std_logic;
timerread : in std_logic;
reload : in std_logic;
timerz : out std_logic);
end component Timeout;
component idreadback is
Generic ( id : std_logic_vector(31 downto 0);
mc : std_logic_vector(31 downto 0));
Port ( readid : in std_logic;
readmc : in std_logic;
obus : out std_logic_vector(31 downto 0));
end component idreadback;
begin
makecounters: for i in 0 to (counters -1) generate
counterx: counter port map (
obus => D,
ibus => LAD,
quada => A(i),
quadb => B(i),
index => Idx(i),
ccrloadcmd => CCRLoadCmds(i),
ccrreadcmd => CCRReadCmds(i),
countoutreadcmd => CounterRead(i),
countlatchcmd => GlobalCountLatch,
countclearcmd => GlobalCounterClear,
countenable => GlobalCounterEnable,
indexmask => IOBITSA(16+i),
nads => ADS,
clk => LClk
);
end generate;
makescounters: for i in 0 to 3 generate
counterx: counter port map (
obus => D,
ibus => LAD,
quada => IOBITSA((i*4)),
quadb => IOBITSA((i*4)+1),
index => IOBITSA((i*4)+2),
ccrloadcmd => SCCRLoadCmds(i),
ccrreadcmd => SCCRReadCmds(i),
countoutreadcmd => SCounterRead(i),
countlatchcmd => GlobalCountLatch,
countclearcmd => GlobalCounterClear,
countenable => GlobalCounterEnable,
indexmask => IOBITSA((i*4)+3),
nads => ADS,
clk => LClk
);
end generate;
makepwmgen: for i in 0 to (counters -1) generate
pwmgenx: pwmgenh port map (
clk => LClk,
hclk => FClk,
refcount => RefCountBus,
ibus => LAD(15 downto 0),
obus => D(15 downto 0),
loadpwmval => LoadPWM(i),
readpwmval => ReadPWM(i),
clearpwmval => GlobalClearPWM,
pcrloadcmd => PCRLoadCmds(i),
pcrreadcmd => PCRReadCmds(i),
pwmout => PWM(i),
dirio => Dir(i),
enablein => GlobalPWMEnable,
enableout =>EnaSigs(i)
);
end generate;
oporta: WordPR24 port map (
clear => '0',
clk => LClk,
ibus => LAD(23 downto 0),
obus => D(23 downto 0),
loadport => LoadPortA,
loadddr => LoadDDRA,
readddr => ReadDDRA,
portdata => IOBITSA
);
iporta: Word24RB port map (
obus => D(23 downto 0),
readport => ReadPortA,
portdata => IOBITSA
);
-- oportb: WordPR24 port map (
-- clear => '0',
-- clk => LClk,
-- ibus => LAD(23 downto 0),
-- obus => D(23 downto 0),
-- loadport => LoadPortB,
-- loadddr => LoadDDRB,
-- readddr => ReadDDRB,
-- portdata => IOBITSB
-- );
-- iportb: Word24RB port map (
-- obus => D(23 downto 0),
-- readport => ReadPortB,
-- portdata => IOBitsB
-- );
pwmrefcount: pwmrefh port map (
clk => LClk,
hclk => FClk,
refcount => RefCountBus,
irqgen => IRQSource,
ibus => LAD(15 downto 0),
obus => D(15 downto 0),
irqdivload => LoadIRQDivCmd,
irqdivread => ReadIRQDivCmd,
phaseload => LoadPhaseCmd,
phaseread => ReadPhaseCmd
);
gLedreg: indexreg port map (
clk => LClk,
ibus => LAD(15 downto 0),
obus => D(15 downto 0),
loadindex => LoadLEDViewCmd,
readindex => ReadLEDViewCmd,
index => LEDView
);
ggcontrolreg: globalcontrolreg port map (
clk => LClk,
ibus => LAD(15 downto 0),
reset => '0',
loadgcr => LoadGCRCmd,
ctrclear => GlobalCounterClear,
ctrlatch => GlobalCountLatchCmd,
pwmclear => GlobalClearPWMCmd,
irqclear => ClearIRQCmd,
reloadwd => ReloadWDCmd
);
gglobalmodereg: globalmodereg port map (
clk => LClk,
ibus => LAD(15 downto 0),
obus => D(15 downto 0),
reset => '0',
loadglobalmode => loadGMRCmd,
readglobalmode => ReadGMRCmd,
ctrena => GlobalCounterEnable,
pwmena => GlobalPWMEnable,
clearpwmena => StopPWM,
loi => LatchOnInterrupt,
som => StopOnMissedIRQ,
sot => StopOnTimeout,
miout => ClearMissedIRQ,
miin => MissedIRQ,
irqmask => IRQMask,
irqstatus => IRQLatch
);
atimeout: timeout port map (
clk => LClk,
ibus => LAD(15 downto 0),
obus => D(15 downto 0),
timeoutload => loadTimeOutCmd,
timeoutread => ReadTimeOutCmd,
timerread => ReadTimerCmd,
reload => ReLoadWDCmd,
timerz => WDTimeout
);
aidreadback: idreadback
generic map (
id => HMID,
mc => MasterClock
)
port map(
readid => ReadIDCmd,
readmc => ReadMCCmd,
obus => D
);
CLKDLL_inst : CLKDLL
generic map (
CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,4.0,5.0,8.0 or 16.0
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
FACTORY_JF => X"C080", -- FACTORY JF Values
STARTUP_WAIT => FALSE) -- Delay config DONE until DLL LOCK, TRUE/FALSE
port map (
CLK0 => CLK0, -- 0 degree DLL CLK output
CLKFB =>FClk, -- DLL feedback
CLK2X => CLK2X, -- 2X DLL CLK output
CLKIN => SYNCLK, -- Clock input (from IBUFG, BUFG or DLL)
RST => '0' -- DLL asynchronous reset input
);
BUFG_inst : BUFG
port map (
O => FClk, -- Clock buffer output
I => CLK2X -- Clock buffer input
);
LADDrivers: process (D,FastRead)
begin
if FastRead ='1' then
LAD <= D;
else
LAD <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
end if;
end process LADDrivers;
AddressLatch: process (lclk)
begin
if lclk'event and LClk = '1' then
if ADS = '0' then
LatchedA <= LAD(15 downto 0);
LatchedLBE <= LBE;
end if;
end if;
end process AddressLatch;
-- we generate an early read from ADS and LR_W
-- since the 10 nS LRD delay and 5 nS setup time
-- only give us 15 nS to provide data to the PLX chip
MakeFastRead: process (lclk,PreFastread,LRD)
begin
if lclk'event and LClk = '1' then
if ADS = '0' and LW_R = '0'then
PreFastRead <= '1';
else
PreFastRead <= '0';
end if;
end if;
FastRead <= PreFastRead or (not LRD);
end process MakeFastRead;
Decode: process (LatchedA)
begin
if LatchedA(7 downto 5) = "000" then -- 32 bit access
CounterSel <= '1';
else
CounterSel <= '0';
end if;
if LatchedA(7 downto 5) = "001" then -- 32 bit access
SCounterSel <= '1';
else
SCounterSel <= '0';
end if;
if LatchedA(7 downto 4) = "0100" then -- 16 bit access
CCRSel <= '1';
else
CCRSel <= '0';
end if;
if LatchedA(7 downto 4) = "0101" then -- 16 bit access
SCCRSel <= '1';
else
SCCRSel <= '0';
end if;
if LatchedA(7 downto 5) = "011" then -- 16 bit access
PWMValSel <= '1';
else
PWMValSel <= '0';
end if;
if LatchedA(7 downto 5) = "100" then -- 16 bit access
PCRSel <= '1';
else
PCRSel <= '0';
end if;
if LatchedA(7 downto 2) = "101000" then -- 32 bit access
PortASel <= '1';
else
PortASel <= '0';
end if;
if LatchedA(7 downto 2) = "101001" then -- 32 bit access
DDRASel <= '1';
else
DDRASel <= '0';
end if;
-- if LatchedA(7 downto 2) = "101010" then -- 32 bit access
-- PortBSel <= '1';
-- else
-- PortBSel <= '0';
-- end if;
-- if LatchedA(7 downto 2) = "101011" then -- 32 bit access
-- DDRBSel <= '1';
-- else
-- DDRBSel <= '0';
-- end if;
if LatchedA(7 downto 2) = "110100" then -- 32 bit access D0
IDSel <= '1';
else
IDSel <= '0';
end if;
if LatchedA(7 downto 2) = "110101" then -- 32 bit access D4
MCSel <= '1';
else
MCSel <= '0';
end if;
if LatchedA(7 downto 1) = "1100000" then -- 16 bit access
GCRSel <= '1';
else
GCRSel <= '0';
end if;
if LatchedA(7 downto 1) = "1100001" then -- 16 bit access
GMRSel <= '1';
else
GMRSel <= '0';
end if;
if LatchedA(7 downto 1) = "1100010"then -- 16 bit access
IRQDivSel <= '1';
else
IRQDivSel <= '0';
end if;
if LatchedA(7 downto 1) = "1100011"then -- 16 bit access
PhaseSel <= '1';
else
PhaseSel <= '0';
end if;
if LatchedA(7 downto 1) = "1100100" then -- 16 bit access
TimeOutSel <= '1';
else
TimeOutSel <= '0';
end if;
if LatchedA(7 downto 1) = "1100101" then -- 16 bit access
TimerSel <= '1';
else
TimerSel <= '0';
end if;
if LatchedA(7 downto 1) = "1100110" then -- 16 bit access
LEDViewSel <= '1';
else
LEDViewSel <= '0';
end if;
end process;
SigsOut: process (EnaSigs)
begin
Ena <= EnaSigs;
end process;
CounterDecode: process (CounterSel, Fastread, LatchedA)
begin
if FastRead = '1' then
CounterRead <= OneOfEightDecode(CounterSel,LatchedA(4 downto 2));
else
CounterRead <= (others => '0');
end if;
end process;
SCounterDecode: process (SCounterSel, Fastread, LatchedA)
begin
if FastRead = '1' then
SCounterRead <= OneOfEightDecode(SCounterSel,LatchedA(4 downto 2));
else
SCounterRead <= (others => '0');
end if;
end process;
CCRegs: process (CCRSel, FastRead, LWR, LatchedA)
begin
if FastRead = '1' then
CCRReadCmds <= OneOfEightDecode(CCRSel,LatchedA(3 downto 1));
else
CCRReadCmds <= (others => '0');
end if;
if LWR = '0' then
CCRLoadCmds <= OneOfEightDecode(CCRSel,LatchedA(3 downto 1));
else
CCRLoadCmds <= (others => '0');
end if;
end process;
SCCRegs: process (SCCRSel, FastRead, LWR, LatchedA)
begin
if FastRead = '1' then
SCCRReadCmds <= OneOfEightDecode(SCCRSel,LatchedA(3 downto 1));
else
SCCRReadCmds <= (others => '0');
end if;
if LWR = '0' then
SCCRLoadCmds <= OneOfEightDecode(SCCRSel,LatchedA(3 downto 1));
else
SCCRLoadCmds <= (others => '0');
end if;
end process;
PWMdecode: process (PWMValSel,Fastread, LWR, LatchedA)
begin
if FastRead = '1' then
ReadPWM <= OneOfEightDecode(PWMValSel,LatchedA(3 downto 1));
else
ReadPWM <= (others => '0');
end if;
if LWR = '0' then
LoadPWM <= OneOfEightDecode(PWMValSel,LatchedA(3 downto 1));
else
LoadPWM <= (others => '0');
end if;
end process;
PCRegs: process (PCRSel,Fastread, LWR, LatchedA)
begin
if FastRead = '1' then
PCRReadCmds <= OneOfEightDecode(PCRSel,LatchedA(3 downto 1));
else
PCRReadCmds <= (others => '0');
end if;
if LWR = '0' then
PCRLoadCmds <= OneOfEightDecode(PCRSel,LatchedA(3 downto 1));
else
PCRLoadCmds <= (others => '0');
end if;
end process;
PortADecode: process (PortASel,FastRead,LWR)
begin
if PortASel = '1' and LWR = '0' then
LoadPortA <= '1';
else
LoadPortA <= '0';
end if;
if PortASel = '1' and FastRead = '1' then
ReadPortA <= '1';
else
ReadPortA <= '0';
end if;
end process PortADecode;
DDRADecode: process (DDRASel,FastRead,LWR)
begin
if DDRASel = '1' and LWR = '0' then
LoadDDRA <= '1';
else
LoadDDRA <= '0';
end if;
if DDRASel = '1' and FastRead = '1' then
ReadDDRA <= '1';
else
ReadDDRA <= '0';
end if;
end process DDRADecode;
-- PortBDecode: process (PortBSel,FastRead,LWR)
-- begin
-- if PortBSel = '1' and LWR = '0' then
-- LoadPortB <= '1';
-- else
-- LoadPortB <= '0';
-- end if;
-- if PortBSel = '1' and FastRead = '1' then
-- ReadPortB <= '1';
-- else
-- ReadPortB <= '0';
-- end if;
-- end process PortBDecode;
-- DDRBDecode: process (DDRBSel,FastRead,LWR)
-- begin
-- if DDRBSel = '1' and LWR = '0' then
-- LoadDDRB <= '1';
-- else
-- LoadDDRB <= '0';
-- end if;
-- if DDRBSel = '1' and FastRead = '1' then
-- ReadDDRB <= '1';
-- else
-- ReadDDRB <= '0';
-- end if;
-- end process DDRBDecode;
GCRDecode: process (GCRSel,LWR)
begin
if GCRSel = '1' and LWR = '0' then
LoadGCRCmd <= '1';
else
LoadGCRCmd <= '0';
end if;
end process GCRDecode;
GMRDecode: process (GMRSel,FastRead,LWR)
begin
if GMRSel = '1' and LWR = '0' then
LoadGMRCmd <= '1';
else
LoadGMRCmd <= '0';
end if;
if GMRSel = '1' and FastRead = '1' then
ReadGMRCmd <= '1';
else
ReadGMRCmd <= '0';
end if;
end process GMRDecode;
TimeOutDecode: process (TimeOutSel,FastRead,LWR)
begin
if TimeoutSel = '1' and LWR = '0' then
LoadTimeOutCmd <= '1';
else
LoadTimeOutCmd <= '0';
end if;
if TimeOutSel = '1' and FastRead = '1' then
ReadTimeOutCmd <= '1';
else
ReadTimeOutCmd <= '0';
end if;
end process TimeOutDecode;
TimerDecode: process (TimerSel,FastRead,LWR)
begin
if TimerSel = '1' and FastRead = '1' then
ReadTimerCmd <= '1';
else
ReadTimerCmd <= '0';
end if;
end process TimerDecode;
LEDViewDecode: process (LedViewSel,FastRead,LWR)
begin
if LEDViewSel = '1' and LWR = '0' then
LoadLEDViewCmd <= '1';
else
LoadLEDViewCmd <= '0';
end if;
if LEDViewSel = '1' and FastRead= '1' then
ReadLEDViewCmd <= '1';
else
ReadLEDViewCmd <= '0';
end if;
end process LEDViewDecode;
IRQDivDecode: process (IRQDivSel,FastRead,LWR)
begin
if IRQDivSel = '1' and LWR = '0' then
LoadIRQDivCmd <= '1';
else
LoadIRQDivCmd <= '0';
end if;
if IRQDivSel = '1' and FastRead = '1' then
ReadIRQDivCmd <= '1';
else
ReadIRQDivCmd <= '0';
end if;
end process IrqDivDecode;
PhaseDecode: process (PhaseSel,FastRead,LWR)
begin
if PhaseSel = '1' and LWR = '0' then
LoadPhaseCmd <= '1';
else
LoadPhaseCmd <= '0';
end if;
if PhaseSel = '1' and FastRead = '1' then
ReadPhaseCmd <= '1';
else
ReadPhaseCmd <= '0';
end if;
end process PhaseDecode;
IDDecode: process (IDSel,FastRead)
begin
if IDSel = '1' and FastRead = '1' then
ReadIDCmd <= '1';
else
ReadIDCmd <= '0';
end if;
end process IDDecode;
MCDecode: process (MCSel,FastRead)
begin
if MCSel = '1' and FastRead = '1' then
ReadMCCmd <= '1';
else
ReadMCCmd <= '0';
end if;
end process MCDecode;
irqlogic: process (CardSelect,
IRQSource,
IrqLatch,
ClearMissedIRQ,
MissedIRQ,
StopOnMissedIRQ,
LatchOnInterrupt,
GlobalCountLatchCmd,
GlobalClearPWMCmd,
ClearIRQCmd)
begin
if IrqSource'event and IRQsource = '1' then
IRQLatch <= '1';
if IRQLatch = '1' then -- if IRQLatch is set and we get the next interrupt
MissedIRQ <= '1'; -- set Missed IRQ latch
end if;
end if;
if LClk'event and LClk = '1' then
if ((IRQLatch = '1') and (LatchOnInterrupt = '1')) or (GlobalCountLatchCmd = '1') then
CountLatchEdge1 <= '1';
else
CountLatchEdge1 <= '0';
end if;
CountLatchEdge2 <= CountLatchEdge1;
if CountLatchEdge2 = '0' and CountLatchEdge1 = '1' then
GlobalCountLatch <= '1';
else
GlobalCountLatch <= '0';
end if;
end if;
if ClearMissedIRQ = '1' then
MissedIRQ <= '0';
end if;
if ((MissedIRQ = '1') and (StopOnMissedIRQ = '1')) or
((WDTimeOut = '1') and (StopOnTimeout = '1')) then
StopPWM <= '1';
else
StopPWM <= '0';
end if;
if (StopPWM = '1') or (GlobalClearPWMCmd = '1') then -- either stop on pwm or global clear reset pwm gens
GlobalClearPWM <= '1';
else
GlobalClearPWM <= '0';
end if;
if ClearIRQCmd = '1' then -- clear IRQ
IRQLatch <= '0';
end if;
Int <= not (IRQLatch and IRQMask); -- drive our (active low) interrupt pin
Ready <= '0'; -- We're always ready
end process;
LEDDrive: process (A,B,Idx,Dir,PWM,IRQLatch,LedView)
begin
LEDS(7) <= not IRQLatch;
LEDS(6) <= not OneOfEightMux(LEDView(2 downto 0),A);
LEDS(5) <= not OneOfEightMux(LEDView(2 downto 0),B);
LEDS(4) <= not OneOfEightMux(LEDView(2 downto 0),Idx);
LEDS(3) <= not OneOfEightMux(LEDView(2 downto 0),Dir);
LEDS(2) <= not OneOfEightMux(LEDView(2 downto 0),PWM);
LEDS(1) <= OneOfEightMux(LEDView(2 downto 0),EnaSigs);
LEDS(0) <= not WDTimeout;
end process leddrive;
end dataflow;
| lgpl-2.1 | 00950c18e6e6d100f7d9d2ba1416edc5 | 0.607637 | 2.940547 | false | false | false | false |
pwsoft/fpga_examples | rtl/chameleon/chameleon_io.vhd | 1 | 36,207 | -- -----------------------------------------------------------------------
--
-- Turbo Chameleon
--
-- Multi purpose FPGA expansion for the Commodore 64 computer
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2019 by Peter Wendrich ([email protected])
-- http://www.syntiac.com
--
-- This source file is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- -----------------------------------------------------------------------
--
-- For better understanding what this entity does in detail, please refer
-- to the Chameleon core-developers manual. It has documentation about
-- the CPLD MUX, signal timing, docking-station protocol and the cartridge port access.
--
-- Chameleon timing and I/O driver. Handles all the timing and multiplexing
-- details of the cartridge port and the CPLD mux.
-- - Detects the type of mode the chameleon is running in.
-- - Multiplexes the PS/2 keyboard and mouse signals.
-- - Gives access to joysticks and keyboard on a C64 in cartridge mode.
-- - Gives access to joysticks and keyboard on a docking-station
-- - Gives access to MMC card and serial-flash through the CPLD MUX.
-- - Drives the two LEDs on the Chameleon (or an optional Amiga keyboard).
-- - Can optionally give access to the IEC bus
-- - Can optionally give access to other C64 resources like the SID.
--
-- -----------------------------------------------------------------------
-- enable_docking_station - Enable support for the docking-station.
-- enable_docking_irq - Drive IRQ line for docking-station communication to control LED on Amiga keyboard.
-- enable_vga_id_read - Enable reading of the VGA id lines (scl,id2,sca,id1) for debugging purposes.
-- Best to keep this disabled unless VGA id status is needed as it uses CPLD multiplexer time.
-- enable_cdtv_remove - Enable support for the cdtv remote. CDTV will be mapped to first
-- two joysticks and the "keys" array when set to true. Otherwise
-- the raw ir signal is also available for external decoding.
-- enable_c64_joykeyb - Automatically read joystick and keyboard on the C64 bus.
-- Take note this disables the C64 bus access feature on this entity.
-- enable_c64_4player - Enable 4player support on the user-port of the C64.
-- The flag enable_c64_joykeyb must be true for this to work.
-- enable_raw_spi - SPI controller inside this entity is switched off.
-- And the actual SPI lines are exposed. The maximum speed is limited
-- as the signals are time multiplexed. The maximum spi speed usable
-- is around 1/12 of clk. (One line transition each 6 clk cycles)
-- enable_iec_access - Enables support for the IEC bus on the break-out cable.
-- Set this to 'false' when the IEC bus is not used to save some logic.
-- -----------------------------------------------------------------------
-- clk - system clock
-- ena_1mhz - Enable must be '1' one clk cycle each 1 Mhz.
-- reset - Perform a reset of the subsystems
-- reset_ext - Hardware reset from the cartridge-port (eg. a C64 reset button)
--
-- no_clock - '0' when connected to C64 cartridge port.
-- '1' when in standalone mode or docking-station connected.
-- docking_station - '0' standalone/cartrdige mode
-- '1' when docking-station is connected.
-- docking_version - '0' first version, supports 2 fire buttons on each port
-- '1' second version, 3 fire buttons on each port and midi in/out
-- vga_id - State of the VGA identifier pins. bit3=scl, bit2=id2, bit1=sca, bit0=id1
-- Only gets updated if enable_vga_id_read flag is true.
-- Only enable this feature if the state of these lines is really needed in the design.
--
-- to_usb_rx
--
-- The following timing signals are only useful when writing C64 related designs.
-- They can be left unconnected in all other FPGA designs.
-- phi_mode - Selects timing in standalone mode ('0' is PAL, '1' is NTSC).
-- phi_out - Regenerated or synthesized phi2 clock.
-- phi_cnt - Counting the system-clock cycles within one phi2 cycle.
-- phi_end_0 - The half of the cycle where phi_out is low ends.
-- phi_end_1 - The half of the cycle where phi_out is high ends.
-- phi_post_1 - Triggers when phi changes
-- phi_post_2 - Triggers one cycle after phi changed
-- phi_post_3 - Triggers two cycles phi changed
-- phi_post_4 - Triggers three cycles phi changed
--
-- c64_reset - When set the reset is pending (line is pulled low) on the cartridge port.
-- As "reset_ext" is masked to prevent endless reset.
-- This signal can be used for RRNET pull-up detection instead.
-- c64_irq_n - Status of the C64 IRQ line (cartridge mode only)
-- c64_nmi_n - Status of the C64 NMI line
-- c64_ba - status of the C64 BA line
--
-- The following signals should be synchronised to the phi_out signal
-- c64_vic - When set data on c64_d is send to the VIC-II chip.
-- c64_cs - When set it accesses the C64 databus (uses Ultimax mode, no memory is mapped)
-- c64_cs_roms - Enables access to the C64 Kernal and Basic ROMs (disables Ultimax mode)
-- c64_clockport - When set it accesses the clockport.
-- c64_we - Access is a write when set (note polarity is the inverse of R/W on cartridge port)
-- c64_a - C64 address bus
-- c64_d - Data to the C64
-- c64_q - Data from the C64 (only valid when phi_end_1 is set)
--
-- spi_speed - 0 SPI bus runs at slow speed (250 Kbit), SPI bus runs at fast speed (8 Mbit)
-- spi_req - Toggle to request SPI transfer.
-- spi_ack - Is made equal to spi_req after transfer is complete.
-- spi_d - Data input into SPI controller.
-- spi_q - Data output from SPI controller.
--
-- led_green - Control the green LED (0 off, 1 on). Also power LED on Amiga keyboard.
-- led_red - Control the red LED (0 off, 1 on). Also drive LED on Amiga keyboard.
-- ir - ir signal. Input for the chameleon_cdtv_remote entity.
--
-- ps2_* - PS2 signals for both keyboard and mouse.
-- button_reset_n - Status of blue reset button (right button) on the Chameleon. Low active.
-- joystick* - Joystick ports of both docking-station and C64.
-- Bits: fire3, fire2, fire1, right, left, down, up
--
-- keys - C64 keyboard. One bit for each key on the keyboard. Low active.
-- 63..56 - RUN/S / , N V X LSHFT UPDN
-- 55..48 - Q ^ @ O U T E F5
-- 47..40 - C= F3
-- 39..32 - SPACE RSHFT F1
-- 31..24 - 2 HOME - F7
-- 23..16 - CTRL ; LEFT/RIGHT
-- 15.. 8 - Return
-- 7.. 0 - 1 + Inst/Del
-- restore_key_n - Trigger for restore key on docking-station.
-- On a C64 the restore key is wired to the NMI line instead.
--
-- iec_* - IEC signals. Only valid when enable_iec_access is set to true.
--
-- midi_txd - Midi transmit data ('1' at rest, '0' drives output)
-- midi_rxd - Midi receive data ('1' at rest, '0' when current flows through opto)
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
-- -----------------------------------------------------------------------
entity chameleon_io is
generic (
enable_docking_station : boolean := true;
enable_docking_irq : boolean := false;
enable_vga_id_read : boolean := false;
enable_cdtv_remote : boolean := false;
enable_c64_joykeyb : boolean := false;
enable_c64_4player : boolean := false;
enable_raw_spi : boolean := false;
enable_iec_access : boolean := false
);
port (
-- Clocks
clk : in std_logic;
clk_mux : in std_logic;
ena_1mhz : in std_logic;
reset : in std_logic;
reset_ext : out std_logic;
-- Config
no_clock : out std_logic;
docking_station : out std_logic;
docking_version : out std_logic;
vga_id : out unsigned(3 downto 0);
-- Chameleon FPGA pins
-- C64 Clocks
phi2_n : in std_logic;
dotclock_n : in std_logic;
-- C64 cartridge control lines
io_ef_n : in std_logic;
rom_lh_n : in std_logic;
-- SPI bus
spi_miso : in std_logic;
-- CPLD multiplexer
mux_clk : out std_logic;
mux : out unsigned(3 downto 0);
mux_d : out unsigned(3 downto 0);
mux_q : in unsigned(3 downto 0);
-- USB microcontroller (To RX of micro)
to_usb_rx : in std_logic := '1';
-- C64 timing (only for C64 related cores)
phi_mode : in std_logic := '0';
phi_out : out std_logic;
phi_cnt : out unsigned(7 downto 0);
phi_end_0 : out std_logic;
phi_end_1 : out std_logic;
phi_post_1 : out std_logic;
phi_post_2 : out std_logic;
phi_post_3 : out std_logic;
phi_post_4 : out std_logic;
-- C64 bus
c64_reset : out std_logic;
c64_irq_n : out std_logic;
c64_nmi_n : out std_logic;
c64_ba : out std_logic;
c64_vic : in std_logic := '0';
c64_cs : in std_logic := '0';
c64_cs_roms : in std_logic := '0';
c64_clockport : in std_logic := '0';
c64_we : in std_logic := '0';
c64_a : in unsigned(15 downto 0) := (others => '0');
c64_d : in unsigned(7 downto 0) := (others => '1');
c64_q : out unsigned(7 downto 0);
-- SPI chip-selects
mmc_cs_n : in std_logic := '1';
flash_cs_n : in std_logic := '1';
rtc_cs : in std_logic := '0';
-- SPI controller (enable_raw_spi must be set to false)
spi_speed : in std_logic := '1';
spi_req : in std_logic := '0';
spi_ack : out std_logic;
spi_d : in unsigned(7 downto 0) := (others => '-');
spi_q : out unsigned(7 downto 0);
-- SPI raw signals (enable_raw_spi must be set to true)
spi_raw_clk : in std_logic := '1';
spi_raw_mosi : in std_logic := '1';
-- LEDs
led_green : in std_logic := '0';
led_red : in std_logic := '0';
ir : out std_logic;
-- PS/2 Keyboard
ps2_keyboard_clk_out: in std_logic := '1';
ps2_keyboard_dat_out: in std_logic := '1';
ps2_keyboard_clk_in: out std_logic;
ps2_keyboard_dat_in: out std_logic;
-- PS/2 Mouse
ps2_mouse_clk_out: in std_logic := '1';
ps2_mouse_dat_out: in std_logic := '1';
ps2_mouse_clk_in: out std_logic;
ps2_mouse_dat_in: out std_logic;
-- Buttons
button_reset_n : out std_logic;
-- Joysticks
joystick1 : out unsigned(6 downto 0);
joystick2 : out unsigned(6 downto 0);
joystick3 : out unsigned(6 downto 0);
joystick4 : out unsigned(6 downto 0);
-- Keyboards
-- 0 = col0, row0
-- 1 = col1, row0
-- 8 = col0, row1
-- 63 = col7, row7
keys : out unsigned(63 downto 0);
restore_key_n : out std_logic;
amiga_reset_n : out std_logic;
amiga_trigger : out std_logic;
amiga_scancode : out unsigned(7 downto 0);
-- IEC bus
iec_clk_out : in std_logic := '1';
iec_dat_out : in std_logic := '1';
iec_atn_out : in std_logic := '1';
iec_srq_out : in std_logic := '1';
iec_clk_in : out std_logic;
iec_dat_in : out std_logic;
iec_atn_in : out std_logic;
iec_srq_in : out std_logic;
-- MIDI (only available on Docking-station V2)
midi_txd : in std_logic := '1';
midi_rxd : out std_logic
);
end entity;
-- -----------------------------------------------------------------------
architecture rtl of chameleon_io is
-- Clocks
signal no_clock_loc : std_logic;
signal phi : std_logic;
signal end_of_phi_0 : std_logic;
signal end_of_phi_1 : std_logic;
-- State
signal vga_id_reg : unsigned(3 downto 0) := (others => '0');
signal reset_pending : std_logic := '0';
signal reset_in : std_logic := '0';
-- Button
signal button_reset_n_reg : std_logic := '1';
-- MUX
type muxstate_t is (
-- Reset phase
MUX_RESET,
-- MMC
MUX_MMC0L, MUX_MMC0H, MUX_MMC1L, MUX_MMC1H, MUX_MMC2L, MUX_MMC2H, MUX_MMC3L, MUX_MMC3H,
MUX_MMC4L, MUX_MMC4H, MUX_MMC5L, MUX_MMC5H, MUX_MMC6L, MUX_MMC6H, MUX_MMC7L, MUX_MMC7H,
-- IEC
MUX_IEC1, MUX_IEC2, MUX_IEC3, MUX_IEC4,
-- PS2
MUX_PS2,
-- LED
MUX_LED,
-- PHI=0
MUX_WAIT0,
MUX_A3_C, MUX_BUSVIC,
MUX_D0VIC, MUX_D1VIC,
MUX_NMIIRQ1, MUX_NMIIRQ2,
MUX_ULTIMAX,
MUX_END0,
-- PHI=1
MUX_WAIT1,
MUX_BUS, MUX_CLKPORT,
MUX_A0, MUX_A1, MUX_A2, MUX_A3,
MUX_D0WR, MUX_D1WR, MUX_D0WR_1, MUX_D1WR_1, MUX_D0WR_2, MUX_D1WR_2,
MUX_D0RD_1, MUX_D1RD_1, MUX_D0RD_2, MUX_D1RD_2
);
signal mux_state : muxstate_t;
signal mux_toggle : std_logic := '0';
signal mux_c128_timeout : unsigned(7 downto 0) := (others => '1');
signal mux_clk_reg : std_logic := '0';
signal mux_d_reg : unsigned(mux_d'range) := X"F";
signal mux_reg : unsigned(mux'range) := X"F";
signal mux_d_mmc : unsigned(1 downto 0) := "11";
-- C64 bus
signal c64_reset_reg : std_logic := '0';
signal c64_ba_reg : std_logic := '1';
signal c64_data_reg : unsigned(7 downto 0) := (others => '1');
signal c64_addr : unsigned(15 downto 0) := (others => '0');
signal c64_to_io : unsigned(7 downto 0) := (others => '0');
signal c64_we_loc : std_logic := '0';
signal c64_vic_loc : std_logic := '0';
signal c64_cs_loc : std_logic := '0';
signal c64_roms_loc : std_logic := '0';
signal c64_clockport_loc : std_logic := '0';
-- C64 joystick/keyboard
signal c64_kb_req : std_logic := '0';
signal c64_kb_ack : std_logic := '0';
signal c64_kb_we : std_logic := '1';
signal c64_kb_a : unsigned(15 downto 0) := (others => '0');
signal c64_kb_q : unsigned(7 downto 0) := (others => '1');
signal c64_joystick1 : unsigned(6 downto 0);
signal c64_joystick2 : unsigned(6 downto 0);
signal c64_joystick3 : unsigned(6 downto 0);
signal c64_joystick4 : unsigned(6 downto 0);
signal c64_keys : unsigned(63 downto 0);
-- CDTV remote
signal ir_reg : std_logic := '0';
signal ir_up : std_logic := '0';
signal ir_down : std_logic := '0';
signal ir_left : std_logic := '0';
signal ir_right : std_logic := '0';
signal ir_f1 : std_logic := '0';
signal ir_f2 : std_logic := '0';
signal ir_f3 : std_logic := '0';
signal ir_f4 : std_logic := '0';
signal ir_f5 : std_logic := '0';
signal ir_f6 : std_logic := '0';
signal ir_f7 : std_logic := '0';
signal ir_f8 : std_logic := '0';
signal ir_space : std_logic := '0';
signal ir_enter : std_logic := '0';
signal ir_left_button : std_logic := '0';
signal ir_middle_button : std_logic := '0';
signal ir_right_button : std_logic := '0';
signal ir_arrowleft : std_logic := '0';
signal ir_y : std_logic := '0';
signal ir_n : std_logic := '0';
signal ir_runstop : std_logic := '0';
signal ir_keys : unsigned(63 downto 0);
signal ir_joystick1 : unsigned(6 downto 0) := (others => '1');
signal ir_joystick2 : unsigned(6 downto 0) := (others => '1');
-- Docking-station
signal docking_station_loc : std_logic;
signal docking_version_loc : std_logic;
signal docking_irq : std_logic;
signal docking_joystick1 : unsigned(6 downto 0);
signal docking_joystick2 : unsigned(6 downto 0);
signal docking_joystick3 : unsigned(6 downto 0);
signal docking_joystick4 : unsigned(6 downto 0);
signal docking_keys : unsigned(63 downto 0);
signal docking_amiga_reset_n : std_logic;
signal docking_amiga_scancode : unsigned(7 downto 0);
-- MMC
signal mmc_state : unsigned(5 downto 0) := (others => '0');
signal spi_q_reg : unsigned(7 downto 0) := (others => '1');
signal spi_ack_reg : std_logic := '0';
signal spi_run : std_logic := '0';
signal spi_sample : std_logic := '0';
signal mmc_shift_req : std_logic;
signal mmc_shift_ack : std_logic := '0';
-- IEC
signal iec_clk_reg : std_logic := '1';
signal iec_dat_reg : std_logic := '1';
signal iec_atn_reg : std_logic := '1';
signal iec_srq_reg : std_logic := '1';
-- MIDI
signal midi_txd_reg : std_logic := '1';
signal midi_rxd_reg : std_logic := '1';
begin
reset_ext <= reset_in;
no_clock <= no_clock_loc;
docking_station <= docking_station_loc;
docking_version <= docking_version_loc;
vga_id <= vga_id_reg;
--
button_reset_n <= button_reset_n_reg;
--
phi_out <= phi;
phi_end_0 <= end_of_phi_0;
phi_end_1 <= end_of_phi_1;
--
c64_reset <= c64_reset_reg;
c64_ba <= c64_ba_reg;
c64_q <= c64_data_reg;
--
spi_ack <= spi_ack_reg;
spi_q <= spi_q_reg;
--
ir <= ir_reg;
--
joystick1 <= docking_joystick1 and ir_joystick1 and (c64_joystick1);
joystick2 <= docking_joystick2 and ir_joystick2 and (c64_joystick2);
joystick3 <= docking_joystick3 and (c64_joystick3);
joystick4 <= docking_joystick4 and (c64_joystick4);
keys <= docking_keys and c64_keys and ir_keys;
--
midi_rxd <= midi_rxd_reg;
-- -----------------------------------------------------------------------
-- PHI2 clock sync
-- -----------------------------------------------------------------------
phiInstance : entity work.chameleon_phi_clock
port map (
clk => clk,
phi2_n => phi2_n,
mode => phi_mode,
no_clock => no_clock_loc,
docking_station => docking_station_loc,
phiLocal => phi,
phiCnt => phi_cnt,
phiPreHalf => end_of_phi_0,
phiPreEnd => end_of_phi_1,
phiPost1 => phi_post_1,
phiPost2 => phi_post_2,
phiPost3 => phi_post_3,
phiPost4 => phi_post_4
);
-- -----------------------------------------------------------------------
-- Docking-station
-- To enable set enable_docking_station to true.
-- -----------------------------------------------------------------------
genDockingStation : if enable_docking_station generate
myDockingStation : entity work.chameleon_docking_station
port map (
clk => clk,
docking_station => docking_station_loc,
docking_version => docking_version_loc,
dotclock_n => dotclock_n,
io_ef_n => io_ef_n,
rom_lh_n => rom_lh_n,
irq_q => docking_irq,
joystick1 => docking_joystick1,
joystick2 => docking_joystick2,
joystick3 => docking_joystick3,
joystick4 => docking_joystick4,
keys => docking_keys,
restore_key_n => restore_key_n,
amiga_power_led => led_green,
amiga_drive_led => led_red,
amiga_reset_n => amiga_reset_n,
amiga_trigger => amiga_trigger,
amiga_scancode => amiga_scancode
);
end generate;
noDockingStation : if not enable_docking_station generate
docking_version <= '0';
docking_joystick1 <= (others => '1');
docking_joystick2 <= (others => '1');
docking_joystick3 <= (others => '1');
docking_joystick4 <= (others => '1');
docking_keys <= (others => '1');
end generate;
-- -----------------------------------------------------------------------
-- CDTV remote support
-- To enable set enable_cdtv_remote to true.
-- -----------------------------------------------------------------------
genCdtvRemote : if enable_cdtv_remote generate
myCdtvRemote : entity work.chameleon_cdtv_remote
port map (
clk => clk,
ena_1mhz => ena_1mhz,
ir => ir_reg,
key_1 => ir_f1,
key_2 => ir_f2,
key_3 => ir_f3,
key_4 => ir_f4,
key_5 => ir_f5,
key_6 => ir_f6,
key_7 => ir_f7,
key_8 => ir_f8,
key_9 => ir_runstop,
key_0 => ir_space,
key_escape => ir_arrowleft,
key_enter => ir_enter,
key_genlock => ir_left_button,
key_cdtv => ir_middle_button,
key_power => ir_right_button,
key_rew => ir_left,
key_play => ir_up,
key_ff => ir_right,
key_stop => ir_down,
key_vol_up => ir_y,
key_vol_dn => ir_n,
joystick_a => ir_joystick1(5 downto 0),
joystick_b => ir_joystick2(5 downto 0)
);
-- IR remote doesn't have thrid fire button
ir_joystick1(6) <= '1';
ir_joystick2(6) <= '1';
ir_keys <= (not ir_runstop) & "11" & (not ir_n) & "111" & (not (ir_up or ir_down)) &
"1111111" & (not (ir_f5 or ir_f6)) &
"1111111" & (not (ir_f3 or ir_f4)) &
(not ir_space) & (not (ir_left or ir_up or ir_f2 or ir_f4 or ir_f6 or ir_f8)) & "11111" & (not (ir_f1 or ir_f2)) &
"1111111" & (not (ir_f7 or ir_f8)) &
"1111111" & (not (ir_left or ir_right)) &
(not ir_arrowleft) & "111" & (not ir_y) & "11" & (not ir_enter) &
"11111111";
end generate;
noCdtvRemote : if not enable_cdtv_remote generate
ir_keys <= (others => '1');
ir_joystick1 <= (others => '1');
ir_joystick2 <= (others => '1');
end generate;
-- -----------------------------------------------------------------------
-- C64 keyboard and joystick support
-- To enable set enable_c64_joykeyb to true.
-- -----------------------------------------------------------------------
genC64JoyKeyb : if enable_c64_joykeyb generate
myC64JoyKeyb : entity work.chameleon_c64_joykeyb
generic map (
enable_4player => enable_c64_4player
)
port map (
clk => clk,
ena_1mhz => ena_1mhz,
no_clock => no_clock_loc,
reset => reset,
ba => c64_ba_reg,
req => c64_kb_req,
ack => c64_kb_ack,
we => c64_kb_we,
a => c64_kb_a,
d => c64_data_reg,
q => c64_kb_q,
joystick1 => c64_joystick1,
joystick2 => c64_joystick2,
joystick3 => c64_joystick3,
joystick4 => c64_joystick4,
keys => c64_keys
);
c64_addr <= c64_kb_a;
c64_to_io <= c64_kb_q;
c64_vic_loc <= '0';
c64_roms_loc <= '0';
c64_clockport_loc <= '0';
c64_we_loc <= c64_kb_we;
process(clk)
begin
if rising_edge(clk) then
if end_of_phi_1 = '1' then
c64_cs_loc <= '0';
if c64_kb_req /= c64_kb_ack then
if c64_cs_loc = '1' then
c64_kb_ack <= c64_kb_req;
else
c64_cs_loc <= '1';
end if;
end if;
end if;
end if;
end process;
end generate;
noC64JoyKeyb : if not enable_c64_joykeyb generate
c64_joystick1 <= (others => '1');
c64_joystick2 <= (others => '1');
c64_joystick3 <= (others => '1');
c64_joystick4 <= (others => '1');
c64_keys <= (others => '1');
c64_addr <= c64_a;
c64_to_io <= c64_d;
c64_vic_loc <= c64_vic;
c64_cs_loc <= c64_cs;
c64_roms_loc <= c64_cs_roms;
c64_clockport_loc <= c64_clockport;
c64_we_loc <= c64_we;
end generate;
-- -----------------------------------------------------------------------
-- MUX CPLD
-- -----------------------------------------------------------------------
-- MUX clock
process(clk_mux)
begin
if rising_edge(clk_mux) then
mux_clk_reg <= not mux_clk_reg;
end if;
end process;
-- MUX sequence
process(clk_mux)
begin
if rising_edge(clk_mux) then
if mux_clk_reg = '1' then
mux_toggle <= not mux_toggle;
case mux_state is
when MUX_RESET =>
if phi = '1' then
mux_state <= MUX_WAIT0;
end if;
-- PHI2 0
when MUX_WAIT0 =>
if phi = '0' then
mux_state <= MUX_MMC0L;
if mux_c128_timeout /= 0 then
mux_c128_timeout <= mux_c128_timeout - 1;
end if;
end if;
when MUX_MMC0L => mux_state <= MUX_A3_C;
when MUX_A3_C => mux_state <= MUX_ULTIMAX;
when MUX_ULTIMAX => mux_state <= MUX_MMC0H;
when MUX_MMC0H => mux_state <= MUX_BUSVIC;
when MUX_BUSVIC => mux_state <= MUX_IEC1;
when MUX_IEC1 => mux_state <= MUX_MMC1L;
when MUX_MMC1L => mux_state <= MUX_PS2;
when MUX_PS2 => mux_state <= MUX_A2;
when MUX_A2 => mux_state <= MUX_MMC1H;
when MUX_MMC1H => mux_state <= MUX_NMIIRQ1;
when MUX_NMIIRQ1 => mux_state <= MUX_LED;
when MUX_LED => mux_state <= MUX_MMC2L;
when MUX_MMC2L => mux_state <= MUX_A0;
when MUX_A0 => mux_state <= MUX_IEC4;
when MUX_IEC4 => mux_state <= MUX_MMC2H;
when MUX_MMC2H => mux_state <= MUX_A1;
when MUX_A1 => mux_state <= MUX_D0VIC;
when MUX_D0VIC => mux_state <= MUX_D1VIC;
when MUX_D1VIC => mux_state <= MUX_MMC3L;
when MUX_MMC3L => mux_state <= MUX_IEC3;
when MUX_IEC3 => mux_state <= MUX_MMC3H;
when MUX_MMC3H => mux_state <= MUX_END0;
when MUX_END0 => mux_state <= MUX_WAIT1;
-- PHI2 1
when MUX_WAIT1 =>
if phi = '1' then
mux_state <= MUX_MMC4L;
end if;
when MUX_MMC4L => mux_state <= MUX_BUS;
when MUX_BUS => mux_state <= MUX_D0WR;
when MUX_D0WR => mux_state <= MUX_D1WR;
when MUX_D1WR => mux_state <= MUX_MMC4H;
when MUX_MMC4H => mux_state <= MUX_A3;
when MUX_A3 => mux_state <= MUX_CLKPORT;
when MUX_CLKPORT => mux_state <= MUX_MMC5L;
when MUX_MMC5L => mux_state <= MUX_NMIIRQ2;
when MUX_NMIIRQ2 => mux_state <= MUX_MMC5H;
when MUX_MMC5H => mux_state <= MUX_D0WR_1;
when MUX_D0WR_1 => mux_state <= MUX_D1WR_1;
when MUX_D1WR_1 => mux_state <= MUX_MMC6L;
when MUX_MMC6L => mux_state <= MUX_IEC2;
when MUX_IEC2 => mux_state <= MUX_MMC6H;
--when MUX_LED => mux_state <= MUX_MMC6H;
when MUX_MMC6H => mux_state <= MUX_D0WR_2;
when MUX_D0WR_2 => mux_state <= MUX_D1WR_2;
when MUX_D1WR_2 => mux_state <= MUX_MMC7L;
when MUX_MMC7L => mux_state <= MUX_D0RD_1;
when MUX_D0RD_1 => mux_state <= MUX_D1RD_1;
when MUX_D1RD_1 => mux_state <= MUX_MMC7H;
when MUX_MMC7H => mux_state <= MUX_D0RD_2;
when MUX_D0RD_2 => mux_state <= MUX_D1RD_2;
when MUX_D1RD_2 => mux_state <= MUX_WAIT0;
end case;
end if;
if reset = '1' then
mux_c128_timeout <= (others => '1');
-- system_wait <= '1';
end if;
end if;
end process;
-- MUX read
process(clk_mux)
begin
if rising_edge(clk_mux) then
if mux_clk_reg = '1' then
case mux_reg is
when X"0" =>
c64_data_reg(3 downto 0) <= mux_q;
when X"1" =>
c64_data_reg(7 downto 4) <= mux_q;
when X"6" =>
c64_reset_reg <= not mux_q(0);
c64_irq_n <= mux_q(2);
c64_nmi_n <= mux_q(3);
reset_pending <= reset or c64_reset_reg;
if reset_pending = '0' then
reset_in <= c64_reset_reg;
else
reset_in <= '0';
end if;
if no_clock_loc = '1' then
c64_irq_n <= '1';
end if;
when X"7" =>
c64_ba_reg <= mux_q(1);
midi_rxd_reg <= '1';
if no_clock_loc = '1' then
c64_ba_reg <= '1';
if (docking_station_loc = '1') and (docking_version_loc = '1') then
midi_rxd_reg <= mux_q(1);
end if;
end if;
when X"A" =>
vga_id_reg <= mux_q;
when X"B" =>
button_reset_n_reg <= mux_q(1);
ir_reg <= mux_q(3);
when X"D" =>
iec_dat_reg <= mux_q(0);
iec_clk_reg <= mux_q(1);
iec_srq_reg <= mux_q(2);
iec_atn_reg <= mux_q(3);
when X"E" =>
ps2_keyboard_dat_in <= mux_q(0);
ps2_keyboard_clk_in <= mux_q(1);
ps2_mouse_dat_in <= mux_q(2);
ps2_mouse_clk_in <= mux_q(3);
when others =>
null;
end case;
if spi_sample = '1' then
spi_q_reg <= spi_q_reg(6 downto 0) & spi_miso;
if mmc_state(5) = '0' then
spi_ack_reg <= spi_run;
end if;
end if;
end if;
iec_dat_in <= iec_dat_reg;
iec_clk_in <= iec_clk_reg;
iec_srq_in <= iec_srq_reg;
iec_atn_in <= iec_atn_reg;
end if;
end process;
-- MUX write
process(clk_mux)
begin
if rising_edge(clk_mux) then
midi_txd_reg <= midi_txd;
if mux_clk_reg = '1' then
spi_sample <= '0';
case mux_state is
--
-- RESET
when MUX_RESET =>
mux_d_reg <= (others => '-');
mux_reg <= X"F";
--
-- MMC
when MUX_MMC0L =>
-- Remember current state for lowspeed transfer.
-- Register is accessed another 15 times in
-- system cycle, but should not be updated when running on 250khz speed.
mux_d_mmc(0) <= mmc_state(1) or (not mmc_state(5));
mux_d_mmc(1) <= spi_d(7 - to_integer(mmc_state(4 downto 2)));
-- Update register
mux_d_reg(0) <= mmc_state(1) or (not mmc_state(5));
mux_d_reg(1) <= spi_d(7 - to_integer(mmc_state(4 downto 2)));
mux_d_reg(2) <= mmc_cs_n;
mux_d_reg(3) <= to_usb_rx;
mux_reg <= X"C";
if mmc_state(5) = '1' then
if spi_speed = '0' then
-- Slow speed. Only toggle once in two cycles
mmc_state <= mmc_state + "000001";
if mmc_state(1 downto 0) = "11" then
spi_sample <= '1';
end if;
else
-- Fast speed. Toggle 16 times in a cycle
mmc_state <= mmc_state + "000010";
if mmc_state(1) = '1' then
spi_sample <= '1';
end if;
end if;
end if;
if enable_raw_spi then
mux_d_reg(0) <= spi_raw_clk;
mux_d_reg(1) <= spi_raw_mosi;
mux_d_reg(2) <= mmc_cs_n;
mux_d_reg(3) <= to_usb_rx;
mux_reg <= X"C";
end if;
when MUX_MMC1L | MUX_MMC2L | MUX_MMC3L
| MUX_MMC4L | MUX_MMC5L | MUX_MMC6L | MUX_MMC7L =>
mux_d_reg(0) <= mux_d_mmc(0);
mux_d_reg(1) <= mux_d_mmc(1);
mux_d_reg(2) <= mmc_cs_n;
mux_d_reg(3) <= to_usb_rx;
mux_reg <= X"C";
-- Only update register on when running at fast speed (8Mhz).
if (mmc_state(5) = '1') and (spi_speed = '1') then
mux_d_reg(0) <= mmc_state(1);
mux_d_reg(1) <= spi_d(7 - to_integer(mmc_state(4 downto 2)));
-- Fast speed. Toggle 16 times in a cycle
mmc_state <= mmc_state + "000010";
if mmc_state(1) = '1' then
spi_sample <= '1';
end if;
end if;
if enable_raw_spi then
mux_d_reg(0) <= spi_raw_clk;
mux_d_reg(1) <= spi_raw_mosi;
mux_d_reg(2) <= mmc_cs_n;
mux_d_reg(3) <= to_usb_rx;
mux_reg <= X"C";
end if;
when MUX_MMC0H | MUX_MMC1H | MUX_MMC2H | MUX_MMC3H
| MUX_MMC4H | MUX_MMC5H | MUX_MMC6H | MUX_MMC7H =>
mux_d_reg(0) <= mux_d_mmc(0);
mux_d_reg(1) <= mux_d_mmc(1);
mux_d_reg(2) <= mmc_cs_n;
mux_d_reg(3) <= to_usb_rx;
mux_reg <= X"C";
if (mmc_state(5) = '1') and (spi_speed = '1') then
-- Only update register on when running at fast speed (8Mhz).
mux_d_reg(0) <= mmc_state(1);
mux_d_reg(1) <= spi_d(7 - to_integer(mmc_state(4 downto 2)));
-- Fast speed. Toggle 16 times in a cycle
mmc_state <= mmc_state + "000010";
if mmc_state(1) = '1' then
spi_sample <= '1';
end if;
elsif enable_iec_access then
-- When MMC transfer is not pending use some of the MMC cycles for IEC transfers.
mux_d_reg(0) <= iec_dat_out;
mux_d_reg(1) <= iec_clk_out;
mux_d_reg(2) <= iec_srq_out;
mux_d_reg(3) <= iec_atn_out;
mux_reg <= X"D";
end if;
if enable_raw_spi then
mux_d_reg(0) <= spi_raw_clk;
mux_d_reg(1) <= spi_raw_mosi;
mux_d_reg(2) <= mmc_cs_n;
mux_d_reg(3) <= to_usb_rx;
mux_reg <= X"C";
end if;
when MUX_NMIIRQ1 | MUX_NMIIRQ2=>
mux_d_reg <= "110" & (not reset);
mux_reg <= X"6";
if enable_docking_irq and (docking_station_loc = '1') then
mux_d_reg(2) <= docking_irq;
end if;
--
-- IEC
when MUX_IEC1 | MUX_IEC2 | MUX_IEC3 | MUX_IEC4 =>
mux_d_reg(0) <= iec_dat_out;
mux_d_reg(1) <= iec_clk_out;
mux_d_reg(2) <= iec_srq_out;
mux_d_reg(3) <= iec_atn_out;
mux_reg <= X"D";
if enable_vga_id_read and (mux_state = MUX_IEC4) then
mux_reg <= X"A";
end if;
--
-- USART, LEDs and IR
when MUX_LED =>
mux_d_reg <= flash_cs_n & rtc_cs & led_green & led_red;
mux_reg <= X"B";
--
-- PS2
when MUX_PS2 =>
mux_d_reg(0) <= ps2_keyboard_dat_out;
mux_d_reg(1) <= ps2_keyboard_clk_out;
mux_d_reg(2) <= ps2_mouse_dat_out;
mux_d_reg(3) <= ps2_mouse_clk_out;
mux_reg <= X"E";
--
-- WAITS
when MUX_WAIT0 =>
if spi_req /= spi_run then
spi_run <= spi_req;
mmc_state <= "100000";
end if;
-- Use dead time to do IEC reads/writes
mux_d_reg(0) <= iec_dat_out;
mux_d_reg(1) <= iec_clk_out;
mux_d_reg(2) <= iec_srq_out;
mux_d_reg(3) <= iec_atn_out;
mux_reg <= X"D";
if enable_raw_spi then
mux_d_reg(0) <= spi_raw_clk;
mux_d_reg(1) <= spi_raw_mosi;
mux_d_reg(2) <= mmc_cs_n;
mux_d_reg(3) <= to_usb_rx;
mux_reg <= X"C";
end if;
when MUX_WAIT1 =>
-- Continue BUSVIC output at end of phi2=0, so we sample BA a few times.
-- A15..12 driven, A11..0 not driven, Data driven, no write.
mux_d_reg <= "0101";
if docking_station_loc = '1' then
mux_d_reg <= "1111";
end if;
mux_reg <= X"7";
-- Toggle between SPI/IEC and updating BUSVIC.
if mux_toggle = '1' then
if enable_iec_access then
mux_d_reg(0) <= iec_dat_out;
mux_d_reg(1) <= iec_clk_out;
mux_d_reg(2) <= iec_srq_out;
mux_d_reg(3) <= iec_atn_out;
mux_reg <= X"D";
end if;
if enable_raw_spi then
mux_d_reg(0) <= spi_raw_clk;
mux_d_reg(1) <= spi_raw_mosi;
mux_d_reg(2) <= mmc_cs_n;
mux_d_reg(3) <= to_usb_rx;
mux_reg <= X"C";
end if;
end if;
--
-- PHI2 0
when MUX_A3_C =>
mux_d_reg <= X"C";
mux_reg <= X"5";
when MUX_BUSVIC =>
-- A15..12 driven, A11..0 not driven, Data driven, no write.
mux_d_reg <= "0101";
if docking_station_loc = '1' then
mux_d_reg <= "1111";
end if;
mux_reg <= X"7";
when MUX_ULTIMAX =>
mux_d_reg <= "1011";
if (no_clock_loc = '1') and (docking_station_loc = '1') and (docking_version_loc = '1') then
-- MIDI output on Docking-station V2
mux_d_reg(2) <= midi_txd_reg;
end if;
mux_reg <= X"8";
when MUX_D0VIC =>
mux_d_reg <= c64_to_io(3 downto 0);
mux_reg <= X"0";
when MUX_D1VIC =>
mux_d_reg <= c64_to_io(7 downto 4);
mux_reg <= X"1";
when MUX_END0 =>
-- A15..12 driven, A11..0 not driven, Data driven, no write.
mux_d_reg <= "0101";
if docking_station_loc = '1' then
mux_d_reg <= "1111";
end if;
mux_reg <= X"7";
--
-- PHI2 1
when MUX_A0 =>
mux_d_reg <= c64_addr(3 downto 0);
mux_reg <= X"2";
when MUX_A1 =>
mux_d_reg <= c64_addr(7 downto 4);
mux_reg <= X"3";
when MUX_A2 =>
mux_d_reg <= c64_addr(11 downto 8);
mux_reg <= X"4";
when MUX_BUS =>
if c64_vic_loc = '0' then
if c64_cs_loc = '1' then
mux_d_reg <= "00" & (not c64_we_loc) & (not c64_we_loc);
mux_reg <= X"7";
end if;
else
-- A15..12 driven, A11..0 not driven, Data driven, no write.
mux_d_reg <= "0101";
mux_reg <= X"7";
end if;
when MUX_CLKPORT =>
-- GAME = low unless accessing roms
mux_d_reg <= "1" & c64_roms_loc & "11";
if c64_clockport_loc = '1' then
if c64_we_loc = '0' then
-- Clockport read
mux_d_reg <= "1010";
else
-- Clockport write
mux_d_reg <= "1001";
end if;
end if;
if (no_clock_loc = '1') and (docking_station_loc = '1') and (docking_version_loc = '1') then
-- MIDI output on Docking-station V2
mux_d_reg(2) <= midi_txd_reg;
end if;
mux_reg <= X"8";
when MUX_A3 =>
if c64_vic_loc = '0' then
if c64_cs_loc = '1' then
mux_d_reg <= c64_addr(15 downto 12);
mux_reg <= X"5";
end if;
end if;
-- when MUX_D0WR | MUX_D0WR_1 | MUX_D0WR_2 =>
when MUX_D0WR | MUX_D0WR_1 | MUX_D0WR_2 | MUX_D0RD_1 | MUX_D0RD_2 =>
mux_d_reg <= c64_to_io(3 downto 0);
mux_reg <= X"0";
-- when MUX_D1WR | MUX_D1WR_1 | MUX_D1WR_2 =>
when MUX_D1WR | MUX_D1WR_1 | MUX_D1WR_2 | MUX_D1RD_1 | MUX_D1RD_2 =>
mux_d_reg <= c64_to_io(7 downto 4);
mux_reg <= X"1";
when others =>
null;
end case;
end if;
end if;
end process;
mux_clk <= mux_clk_reg;
mux_d <= mux_d_reg;
mux <= mux_reg;
end architecture;
| lgpl-2.1 | e30d6f900bec8d0c29ac0df49820fbeb | 0.561328 | 2.741708 | false | false | false | false |
18545/FPGA | src/ov7670_capture.vhd | 1 | 2,501 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Description: Captures the pixels coming from the OV7670 camera and
-- Stores them in block RAM
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ov7670_capture is
Port ( pclk : in STD_LOGIC;
vsync : in STD_LOGIC;
href : in STD_LOGIC;
d : in STD_LOGIC_VECTOR (7 downto 0);
addr : out STD_LOGIC_VECTOR (18 downto 0);
dout : out STD_LOGIC_VECTOR (11 downto 0);
we : out STD_LOGIC);
end ov7670_capture;
architecture Behavioral of ov7670_capture is
signal d_latch : std_logic_vector(15 downto 0) := (others => '0');
signal address : STD_LOGIC_VECTOR(18 downto 0) := (others => '0');
signal address_next : STD_LOGIC_VECTOR(18 downto 0) := (others => '0');
signal wr_hold : std_logic_vector(1 downto 0) := (others => '0');
begin
addr <= address;
process(pclk)
begin
if rising_edge(pclk) then
-- This is a bit tricky href starts a pixel transfer that takes 3 cycles
-- Input | state after clock tick
-- href | wr_hold d_latch d we address address_next
-- cycle -1 x | xx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx x xxxx xxxx
-- cycle 0 1 | x1 xxxxxxxxRRRRRGGG xxxxxxxxxxxxxxxx x xxxx addr
-- cycle 1 0 | 10 RRRRRGGGGGGBBBBB xxxxxxxxRRRRRGGG x addr addr
-- cycle 2 x | 0x GGGBBBBBxxxxxxxx RRRRRGGGGGGBBBBB 1 addr addr+1
if vsync = '1' then
address <= (others => '0');
address_next <= (others => '0');
wr_hold <= (others => '0');
else
dout <= d_latch(10 downto 7) & d_latch(15 downto 12) & d_latch(4 downto 1);
address <= address_next;
we <= wr_hold(1);
wr_hold <= wr_hold(0) & (href and not wr_hold(0));
d_latch <= d_latch( 7 downto 0) & d;
if wr_hold(1) = '1' then
address_next <= std_logic_vector(unsigned(address_next)+1);
end if;
end if;
end if;
end process;
end Behavioral; | mit | ec39eb0678d08648e8a4e8d2719c0b84 | 0.484206 | 3.871517 | false | false | false | false |
EliasLuiz/TCC | Teste/MemoTableTNPCTag.vhd | 1 | 1,256 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
use work.Constants.all;
use work.DefTypes.all;
ENTITY MemoTableTNPCTag IS
--ENTITY TraceMemory IS
PORT
(
Clock : IN STD_LOGIC := '1';
WAddress : IN STD_LOGIC_VECTOR (MemoTableTWayAddressLenght-1 DOWNTO 0);
WData : IN MemoTableTNPCTagBus;
WEnable : IN STD_LOGIC := '0';
RAddress : IN STD_LOGIC_VECTOR (MemoTableTWayAddressLenght-1 DOWNTO 0);
RData : OUT MemoTableTNPCTagBus
);
END MemoTableTNPCTag;
--END TraceMemory;
ARCHITECTURE SYN OF MemoTableTNPCTag IS
--ARCHITECTURE SYN OF TraceMemory IS
COMPONENT MemoTableTNPCTagWay
PORT (
Clock : IN STD_LOGIC := '1';
WAddress : IN STD_LOGIC_VECTOR (MemoTableTWayAddressLenght-1 DOWNTO 0);
WData : IN MemoTableTNPCTagEntry;
WEnable : IN STD_LOGIC := '0';
RAddress : IN STD_LOGIC_VECTOR (MemoTableTWayAddressLenght-1 DOWNTO 0);
RData : OUT MemoTableTNPCTagEntry
);
END COMPONENT;
BEGIN
mem: FOR i IN 0 TO MemoTableTAssociativity-1 GENERATE
MemoTableTNPCTagWay_cmp : MemoTableTNPCTagWay
PORT MAP (
WAddress => WAddress,
Clock => Clock,
WData => WData(i),
WEnable => WEnable,
RAddress => RAddress,
RData => RData(i)
);
END GENERATE mem;
END SYN;
| gpl-3.0 | 833aca7b47d5b799b6a29c680c0f1642 | 0.710987 | 2.579055 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/techmap/maps/iodpad.vhd | 1 | 5,278 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: iodpad
-- File: iodpad.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Open-drain I/O pad with technology wrapper
------------------------------------------------------------------------------
library ieee;
library techmap;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allpads.all;
entity iodpad is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12;
oepol : integer := 0);
port (pad : inout std_ulogic; i : in std_ulogic; o : out std_ulogic);
end;
architecture rtl of iodpad is
signal gnd, oen : std_ulogic;
begin
oen <= not i when oepol /= padoen_polarity(tech) else i;
gnd <= '0';
gen0 : if has_pads(tech) = 0 generate
pad <= '0'
-- pragma translate_off
after 2 ns
-- pragma translate_on
when oen = '0'
-- pragma translate_off
else 'X' after 2 ns when is_x(i)
-- pragma translate_on
else 'Z'
-- pragma translate_off
after 2 ns
-- pragma translate_on
;
o <= to_X01(pad)
-- pragma translate_off
after 1 ns
-- pragma translate_on
;
end generate;
xcv : if (is_unisim(tech) = 1) generate
x0 : unisim_iopad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen, o);
end generate;
axc : if (tech = axcel) or (tech = axdsp) generate
x0 : axcel_iopad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen, o);
end generate;
pa : if (tech = proasic) or (tech = apa3) generate
x0 : apa3_iopad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen, o);
end generate;
pa3e : if (tech = apa3e) generate
x0 : apa3e_iopad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen, o);
end generate;
igl2 : if (tech = igloo2) or (tech = rtg4) generate
x0 : igloo2_iopad port map (pad, gnd, oen, o);
end generate;
pa3l : if (tech = apa3l) generate
x0 : apa3l_iopad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen, o);
end generate;
fus : if (tech = actfus) generate
x0 : fusion_iopad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen, o);
end generate;
atc : if (tech = atc18s) generate
x0 : atc18_iopad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen, o);
end generate;
atcrh : if (tech = atc18rha) generate
x0 : atc18rha_iopad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen, o);
end generate;
um : if (tech = umc) generate
x0 : umc_iopad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen, o);
end generate;
rhu : if (tech = rhumc) generate
x0 : rhumc_iopad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen, o);
end generate;
ihp : if (tech = ihp25) generate
x0 : ihp25_iopad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen, o);
end generate;
rh18t : if (tech = rhlib18t) generate
x0 : rh_lib18t_iopad generic map (strength)
port map (pad, gnd, oen, o);
end generate;
ut025 : if (tech = ut25) generate
x0 : ut025crh_iopad generic map (strength)
port map (pad, gnd, oen, o);
end generate;
ut13 : if (tech = ut130) generate
x0 : ut130hbd_iopad generic map (strength) port map (pad, gnd, oen, o);
end generate;
pere : if (tech = peregrine) generate
x0 : peregrine_iopad generic map (level, slew, voltage, strength)
port map(pad, gnd, oen, o);
end generate;
end;
library ieee;
library techmap;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity iodpadv is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0; width : integer := 1;
oepol : integer := 0);
port (
pad : inout std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
o : out std_logic_vector(width-1 downto 0));
end;
architecture rtl of iodpadv is
begin
v : for j in width-1 downto 0 generate
x0 : iodpad generic map (tech, level, slew, voltage, strength, oepol)
port map (pad(j), i(j), o(j));
end generate;
end;
| gpl-3.0 | 1da412a84a8e972c11b80fbb3ef3f30b | 0.627889 | 3.486129 | false | false | false | false |
kdgwill/VHDL_Framer_Example | VHDL_Framer_Example/Example1/blockDiagram/tb_ramIntro.vhd | 1 | 4,653 | ---------------------------------------------------------------------------------
--Project Test Bench------------------------------------------------------------
--By Kyle Williams, 04/07/2011--------------------------------------------------
--PROJECT DESCRIPTION------------------------------------------------------------
--1--Input Serial data stream----------------------------------------------------
--2--Detect a start of Frame whose pattern is 10101011----------------------------
--3--After frame detect take every 8 bits and store them in a ram----------------
--4--After 8 bytes have been written in the ram start reading the data from the ram
--5--check that data read from ram matches what was written in the ram-----------
----------------Define Libraries to be used--------------------------------------
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE ieee.std_logic_unsigned.all ;
-----------------ENTITY FOR TEST BENCH------------------------------------------
ENTITY tb_ramIntro IS
GENERIC ( bits : INTEGER := 8); -- # of bits per word
END tb_ramIntro;
-----------------BEHAVIOR OF TEST BENCH-----------------------------------------
ARCHITECTURE tb_ramIntro of tb_ramIntro IS
-----------------COMPONENT INITIALIZATIONS--------------------------------------
COMPONENT generator
Generic(N : Integer := 8);
PORT(
clock, reset, load: OUT std_logic;
D : OUT std_logic_vector(n-1 downto 0);
vec : OUT std_logic_vector(N-1 downto 0);
sin : OUT STD_Logic
);
END COMPONENT;
COMPONENT receiver
PORT ( reset : IN STD_Logic;
clock : IN STD_LOGIC;
rec_in : IN STD_LOGIC;
enable : OUT STD_LOGIC;
rec_out : OUT STD_LOGIC_VECTOR (bits -1 DOWNTO 0)
);
End COMPONENT;
COMPONENT ramController
PORT ( reset : IN STD_Logic;
clock : IN STD_LOGIC;
enable : IN STD_LOGIC;
ctrl_in : IN STD_LOGIC_VECTOR (bits - 1 DOWNTO 0);
addr : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
wr_ena : OUT STD_LOGIC; -- write enable
ctrl_out : OUT STD_LOGIC_VECTOR (bits -1 DOWNTO 0)
);
End COMPONENT;
COMPONENT ram
PORT ( wr_ena : IN STD_LOGIC; -- write enable
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
addr : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
ram_in : IN STD_LOGIC_VECTOR (bits - 1 DOWNTO 0);
ram_out : OUT STD_LOGIC_VECTOR (bits -1 DOWNTO 0)
);
End COMPONENT;
COMPONENT dataValidation
PORT ( reset : IN STD_Logic;
clock : IN STD_LOGIC;
wr_ena : IN STD_LOGIC; -- write enable
enable : IN STD_LOGIC;
ctrl_out : IN STD_LOGIC_VECTOR (bits -1 DOWNTO 0);
ram_out : IN STD_LOGIC_VECTOR (bits -1 DOWNTO 0);
data_Valid : OUT STD_LOGIC;
validOffset : OUT Integer
);
End COMPONENT;
-------------------VARIABLE DECLARATION----------------------------------------
Signal clock : STD_LOGIC;
Signal reset : STD_LOGIC;
Signal load : STD_LOGIC;
Signal sin : STD_LOGIC;
Signal wr_enable : STD_LOGIC;
Signal enable : STD_LOGIC;
Signal data_Valid : STD_LOGIC;
Signal address : STD_LOGIC_VECTOR(5 DOWNTO 0);--2^6 bit address 64 possible locations
Signal D : STD_LOGIC_VECTOR(bits-1 Downto 0);
Signal rec_out : STD_LOGIC_VECTOR(bits-1 DOWNTO 0);
Signal ctrl_out : STD_LOGIC_VECTOR(bits-1 DOWNTO 0);
Signal ram_out : STD_LOGIC_VECTOR(bits-1 DOWNTO 0);
Signal validOffset : Integer;
-------------------BEGINING OF INSTRUCTIONS-----------------------------------
BEGIN
-------------------VARIABLE DECLARATIONS--------------------------------------
Gen: generator
PORT Map (sin=>sin, clock => clock, reset => reset, load => load);
recMod:receiver
PORT MAP( reset => reset, clock => clock, enable=>enable,rec_in => sin, rec_out => rec_out);
ctrlMod:ramController
PORT MAP( reset=> reset,clock => clock,enable=>enable,ctrl_in => rec_out,addr=> address,wr_ena=>wr_enable,ctrl_out => ctrl_out);
SRAM:ram
PORT MAP( wr_ena=>wr_enable,clock=>clock,reset=>reset,addr=>address,ram_in=>ctrl_out,ram_out=>ram_out);
valid:dataValidation
PORT MAP(reset=>reset,clock=>clock,wr_ena=>wr_enable,enable=>enable,ctrl_out=>ctrl_out,
ram_out=>ram_out,data_Valid=>data_Valid,validOffset=>validOffset);
-------------------ADDITIONAL INSTRUCTIONS--------------------------------------
--look into tb_ram_demo so you can add a check
END tb_ramIntro;
| gpl-3.0 | e3bd6a2314da47616c68196bd1ae27c9 | 0.511498 | 4.049608 | false | false | false | false |
ARC-Lab-UF/UAA | src/add_flt.vhd | 1 | 5,726 | -- Copyright (c) 2015 University of Florida
--
-- This file is part of uaa.
--
-- uaa is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- uaa is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with uaa. If not, see <http://www.gnu.org/licenses/>.
-- Greg Stitt
-- University of Florida
-- Description:
-- The add_flt entity is a wrapper that provides a common interface to
-- different floating-point adder cores.
--
-- IMPORTANT INSTRUCTIONS:
-- 1) Instantiate a floating-point adder core and connect it to the I/O of
-- add_flt. The adder core must have the capability to stall the add pipeline.
-- 2) If you have multiple options for cores, use the add_core string to select a
-- corresponding implementation. For example, add_core="speed" could select a core
-- optimized for speed, whereas add_core="area" could select a core optimized for
-- area. add_core is completely option, so this step can be skipped if you only have
-- a single core
-- 3) Open flt_pkg.vhd and modify the function add_flt_latency.
-- In the simplest case of a single core option, simply return the latency of
-- the adder core in terms of clock cycles. When using the add_core string to choose
-- from different cores, modify the function to return the corresponding
-- latency of each option.
-- Used entities:
-- user dependent (whatever add cores they decide to use)
-- This file contains an example of how to map add_flt to Stratix 5 and Virtex 7
-- floating-point adder cores for different optimizations.
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
-- Generics Description
-- width : The width of the adder input/output. This should match
-- the precision of the adder (e.g. single precision=32,
-- double precision=64) (required)
-- name : A string specifying the optimization strategy, or just
-- a name for the adder core. This string is optional,
-- but is useful when trying to instantiate
-- implementations with different optimizations
-- (e.g. area vs. speed).
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Port Description:
-- clk : clock input
-- en : enable input (active high), stalls the pipeline when '0'
-- input1 : the first input to the add
-- input2 : the second input to the add
-- output : the sum
-------------------------------------------------------------------------------
entity add_flt is
generic (
width : positive := 32;
core_name : string := "");
port (
clk : in std_logic;
en : in std_logic;
input1 : in std_logic_vector(width-1 downto 0);
input2 : in std_logic_vector(width-1 downto 0);
output : out std_logic_vector(width-1 downto 0));
end add_flt;
architecture default of add_flt is
begin
U_S5_LATENCY : if core_name = "stratix5_latency" generate
U_STRATIX5_LATENCY : entity work.add_flt_stratix5_latency
port map (
clk_en => en,
clock => clk,
dataa => input1,
datab => input2,
result => output);
end generate U_S5_LATENCY;
U_S5_AREA : if core_name = "stratix5_area" generate
U_STRATIX5_AREA : entity work.add_flt_stratix5_area
port map (
clk_en => en,
clock => clk,
dataa => input1,
datab => input2,
result => output);
end generate U_S5_AREA;
U_S5_SPEED : if core_name = "stratix5_speed" generate
U_STRATIX5_SPEED : entity work.add_flt_stratix5_speed
port map (
clk_en => en,
clock => clk,
dataa => input1,
datab => input2,
result => output);
end generate U_S5_SPEED;
U_V7_SPEED : if core_name = "virtex7_speed" generate
U_VIRTEX7_SPEED : entity work.add_flt_virtex7_speed
port map (
clk => clk,
ce => en,
a => input1,
b => input2,
result => output);
end generate U_V7_SPEED;
U_V7_LATENCY : if core_name = "virtex7_latency" generate
U_VIRTEX7_LATENCY : entity work.add_flt_virtex7_latency
port map (
clk => clk,
ce => en,
a => input1,
b => input2,
result => output);
end generate U_V7_LATENCY;
-- print error if invalid add core specified
U_UNDEFINED : if (core_name /= "stratix5_latency" and
core_name /= "stratix5_area" and
core_name /= "stratix5_speed" and
core_name /= "virtex7_speed" and
core_name /= "virtex7_latency"
) generate
assert(false) report "Error: Undefined add core " & core_name & " in add_flt.vhd" severity error;
end generate U_UNDEFINED;
end default;
| gpl-3.0 | 1db0dff48adf37c788c4061ea30489d7 | 0.560775 | 4.269948 | false | false | false | false |
18545/FPGA | src/ov7670_registers.vhd | 2 | 4,862 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: Mike Field <[email protected]>
--
-- Description: Register settings for the OV7670 Caamera (partially from OV7670.c
-- in the Linux Kernel
------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ov7670_registers is
Port ( clk : in STD_LOGIC;
resend : in STD_LOGIC;
advance : in STD_LOGIC;
command : out std_logic_vector(15 downto 0);
finished : out STD_LOGIC);
end ov7670_registers;
architecture Behavioral of ov7670_registers is
signal sreg : std_logic_vector(15 downto 0);
signal address : std_logic_vector(7 downto 0) := (others => '0');
begin
command <= sreg;
with sreg select finished <= '1' when x"FFFF", '0' when others;
process(clk)
begin
if rising_edge(clk) then
if resend = '1' then
address <= (others => '0');
elsif advance = '1' then
address <= std_logic_vector(unsigned(address)+1);
end if;
case address is
when x"00" => sreg <= x"1280"; -- COM7 Reset
when x"01" => sreg <= x"1280"; -- COM7 Reset
when x"02" => sreg <= x"1204"; -- COM7 Size & RGB output
when x"03" => sreg <= x"1100"; -- CLKRC Prescaler - Fin/(1+1)
when x"04" => sreg <= x"0C00"; -- COM3 Lots of stuff, enable scaling, all others off
when x"05" => sreg <= x"3E00"; -- COM14 PCLK scaling off
when x"06" => sreg <= x"8C00"; -- RGB444 Set RGB format
when x"07" => sreg <= x"0400"; -- COM1 no CCIR601
when x"08" => sreg <= x"4010"; -- COM15 Full 0-255 output, RGB 565
when x"09" => sreg <= x"3a04"; -- TSLB Set UV ordering, do not auto-reset window
when x"0A" => sreg <= x"1438"; -- COM9 - AGC Celling
when x"0B" => sreg <= x"4fb3"; -- MTX1 - colour conversion matrix
when x"0C" => sreg <= x"50b3"; -- MTX2 - colour conversion matrix
when x"0D" => sreg <= x"5100"; -- MTX3 - colour conversion matrix
when x"0E" => sreg <= x"523d"; -- MTX4 - colour conversion matrix
when x"0F" => sreg <= x"53a7"; -- MTX5 - colour conversion matrix
when x"10" => sreg <= x"54e4"; -- MTX6 - colour conversion matrix
when x"11" => sreg <= x"589e"; -- MTXS - Matrix sign and auto contrast
when x"12" => sreg <= x"3dc0"; -- COM13 - Turn on GAMMA and UV Auto adjust
when x"13" => sreg <= x"1100"; -- CLKRC Prescaler - Fin/(1+1)
when x"14" => sreg <= x"1711"; -- HSTART HREF start (high 8 bits)
when x"15" => sreg <= x"1861"; -- HSTOP HREF stop (high 8 bits)
when x"16" => sreg <= x"32A4"; -- HREF Edge offset and low 3 bits of HSTART and HSTOP
when x"17" => sreg <= x"1903"; -- VSTART VSYNC start (high 8 bits)
when x"18" => sreg <= x"1A7b"; -- VSTOP VSYNC stop (high 8 bits)
when x"19" => sreg <= x"030a"; -- VREF VSYNC low two bits
-- when x"10" => sreg <= x"703a"; -- SCALING_XSC
-- when x"11" => sreg <= x"7135"; -- SCALING_YSC
-- when x"12" => sreg <= x"7200"; -- SCALING_DCWCTR -- zzz was 11
-- when x"13" => sreg <= x"7300"; -- SCALING_PCLK_DIV
-- when x"14" => sreg <= x"a200"; -- SCALING_PCLK_DELAY must match COM14
-- when x"15" => sreg <= x"1500"; -- COM10 Use HREF not hSYNC
--
-- when x"1D" => sreg <= x"B104"; -- ABLC1 - Turn on auto black level
-- when x"1F" => sreg <= x"138F"; -- COM8 - AGC, White balance
-- when x"21" => sreg <= x"FFFF"; -- spare
-- when x"22" => sreg <= x"FFFF"; -- spare
-- when x"23" => sreg <= x"0000"; -- spare
-- when x"24" => sreg <= x"0000"; -- spare
-- when x"25" => sreg <= x"138F"; -- COM8 - AGC, White balance
-- when x"26" => sreg <= x"0000"; -- spare
-- when x"27" => sreg <= x"1000"; -- AECH Exposure
-- when x"28" => sreg <= x"0D40"; -- COMM4 - Window Size
-- when x"29" => sreg <= x"0000"; -- spare
-- when x"2a" => sreg <= x"a505"; -- AECGMAX banding filter step
-- when x"2b" => sreg <= x"2495"; -- AEW AGC Stable upper limite
-- when x"2c" => sreg <= x"2533"; -- AEB AGC Stable lower limi
-- when x"2d" => sreg <= x"26e3"; -- VPT AGC fast mode limits
-- when x"2e" => sreg <= x"9f78"; -- HRL High reference level
-- when x"2f" => sreg <= x"A068"; -- LRL low reference level
-- when x"30" => sreg <= x"a103"; -- DSPC3 DSP control
-- when x"31" => sreg <= x"A6d8"; -- LPH Lower Prob High
-- when x"32" => sreg <= x"A7d8"; -- UPL Upper Prob Low
-- when x"33" => sreg <= x"A8f0"; -- TPL Total Prob Low
-- when x"34" => sreg <= x"A990"; -- TPH Total Prob High
-- when x"35" => sreg <= x"AA94"; -- NALG AEC Algo select
-- when x"36" => sreg <= x"13E5"; -- COM8 AGC Settings
when others => sreg <= x"ffff";
end case;
end if;
end process;
end Behavioral;
| mit | a1955d281067a89f075771d33bb9fe3a | 0.544632 | 2.887173 | false | false | false | false |
hoglet67/CoPro6502 | src/DCM/dcm_32_10.vhd | 1 | 2,065 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity dcm_32_10 is
port (CLKIN_IN : in std_logic;
CLK0_OUT : out std_logic;
CLK0_OUT1 : out std_logic;
CLK2X_OUT : out std_logic);
end dcm_32_10;
architecture BEHAVIORAL of dcm_32_10 is
signal CLKFX_BUF : std_logic;
signal CLKIN_IBUFG : std_logic;
signal GND_BIT : std_logic;
begin
GND_BIT <= '0';
CLKFX_BUFG_INST : BUFG
port map (I => CLKFX_BUF, O => CLK0_OUT);
DCM_INST : DCM
generic map(CLK_FEEDBACK => "NONE",
CLKDV_DIVIDE => 4.0, -- 10.000 = 32.000 * 5/16
CLKFX_DIVIDE => 16,
CLKFX_MULTIPLY => 5,
CLKIN_DIVIDE_BY_2 => false,
CLKIN_PERIOD => 31.25,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => true,
FACTORY_JF => x"C080",
PHASE_SHIFT => 0,
STARTUP_WAIT => false)
port map (CLKFB => GND_BIT,
CLKIN => CLKIN_IN,
DSSEN => GND_BIT,
PSCLK => GND_BIT,
PSEN => GND_BIT,
PSINCDEC => GND_BIT,
RST => GND_BIT,
CLKDV => open,
CLKFX => CLKFX_BUF,
CLKFX180 => open,
CLK0 => open,
CLK2X => open,
CLK2X180 => open,
CLK90 => open,
CLK180 => open,
CLK270 => open,
LOCKED => open,
PSDONE => open,
STATUS => open);
end BEHAVIORAL;
| gpl-3.0 | f1ade51c445fc621900aead002c04c40 | 0.404843 | 4.231557 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/techmap/inferred/sim_pll.vhd | 1 | 6,498 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: sim_pll
-- File: sim_pll.vhd
-- Author: Magnus Hjorth, Aeroflex Gaisler
-- Description: Generic simulated PLL with input frequency checking
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
entity sim_pll is
generic (
clkmul: integer := 1;
clkdiv1: integer := 1;
clkphase1: integer := 0;
clkdiv2: integer := 1;
clkphase2: integer := 0;
clkdiv3: integer := 1;
clkphase3: integer := 0;
clkdiv4: integer := 1;
clkphase4: integer := 0;
-- Frequency limits in kHz, for checking only
minfreq: integer := 0;
maxfreq: integer := 10000000;
-- Lock tolerance in ps
locktol: integer := 2
);
port (
i: in std_logic;
o1: out std_logic;
o2: out std_logic;
o3: out std_logic;
o4: out std_logic;
lock: out std_logic;
rst: in std_logic
);
end;
architecture sim of sim_pll is
signal clkout1,clkout2,clkout3,clkout4: std_logic;
signal tp: time := 1 ns;
signal timeset: boolean := false;
signal fb: std_ulogic;
signal comp: time := 0 ns;
signal llock: std_logic;
begin
o1 <= transport clkout1 after tp + (tp*clkdiv1*(clkphase1 mod 360)) / (clkmul*360);
o2 <= transport clkout2 after tp + (tp*clkdiv2*(clkphase2 mod 360)) / (clkmul*360);
o3 <= transport clkout3 after tp + (tp*clkdiv3*(clkphase3 mod 360)) / (clkmul*360);
o4 <= transport clkout4 after tp + (tp*clkdiv4*(clkphase4 mod 360)) / (clkmul*360);
lock <= llock after tp*20; -- 20 cycle inertia on lock signal
freqmeas: process(i)
variable ts,te: time;
variable mf: integer;
variable warned: boolean := false;
variable first: boolean := true;
begin
if rising_edge(i) and (now /= (0 ps)) then
ts := te;
te := now;
if first then
first := false;
else
mf := (1 ms) / (te-ts);
assert (mf >= minfreq and mf <= maxfreq) or warned or rst='0' or llock/='1'
report "Input frequency out of range, " &
"measured: " & tost(mf) & ", min:" & tost(minfreq) & ", max:" & tost(maxfreq)
severity warning;
if (mf < minfreq or mf > maxfreq) and rst/='0' and llock='1' then warned := true; end if;
if llock='0' or te-ts-tp > locktol*(1 ps) or te-ts-tp < -locktol*(1 ps) then
tp <= te-ts;
timeset <= true;
end if;
end if;
end if;
end process;
genclk: process
variable divcount1,divcount2,divcount3,divcount4: integer;
variable compen: boolean;
variable t: time;
variable compps: integer;
begin
compen := false;
clkout1 <= '0';
clkout2 <= '0';
clkout3 <= '0';
clkout4 <= '0';
if not timeset or rst='0' then
wait until timeset and rst/='0';
end if;
divcount1 := 0;
divcount2 := 0;
divcount3 := 0;
divcount4 := 0;
fb <= '1';
clkout1 <= '1';
clkout2 <= '1';
clkout3 <= '1';
clkout4 <= '1';
oloop: loop
for x in 0 to 2*clkmul-1 loop
if x=0 then fb <= '1'; end if;
if x=clkmul then fb <= '0'; end if;
t := tp/(2*clkmul);
if compen and comp /= (0 ns) then
-- Handle compensation below resolution limit (1 ps assumed)
if comp < 2*clkmul*(1 ps) and comp > -2*clkmul*(1 ps) then
compps := abs(comp / (1 ps));
if x > 0 and x <= compps then
if comp > 0 ps then
t := t + 1 ps;
else
t := t - 1 ps;
end if;
end if;
else
t:=t+comp/(2*clkmul);
end if;
end if;
if t > (0 ns) then
wait on rst for t;
else
wait for 1 ns;
end if;
exit oloop when rst='0';
divcount1 := divcount1+1;
if divcount1 >= clkdiv1 then
clkout1 <= not clkout1;
divcount1 := 0;
end if;
divcount2 := divcount2+1;
if divcount2 >= clkdiv2 then
clkout2 <= not clkout2;
divcount2 := 0;
end if;
divcount3 := divcount3+1;
if divcount3 >= clkdiv3 then
clkout3 <= not clkout3;
divcount3 := 0;
end if;
divcount4 := divcount4+1;
if divcount4 >= clkdiv4 then
clkout4 <= not clkout4;
divcount4 := 0;
end if;
end loop;
compen := true;
end loop oloop;
end process;
fbchk: process(fb,i)
variable last_i,prev_i: time;
variable last_fb,prev_fb: time;
variable vlock: std_logic := '0';
begin
if falling_edge(i) then
prev_i := last_i;
last_i := now;
end if;
if falling_edge(fb) then
-- Update phase compensation
if last_i < last_fb+tp/2 then
comp <= (last_i - last_fb);
else
comp <= last_i - now;
end if;
prev_fb := last_fb;
last_fb := now;
end if;
if (last_i<=(last_fb+locktol*(1 ps)) and last_i>=(last_fb-locktol*(1 ps)) and
prev_i<=(prev_fb+locktol*(1 ps)) and prev_i>=(prev_fb-locktol*(1 ps))) then
vlock := '1';
end if;
if prev_fb > last_i+locktol*(1 ps) or prev_i>last_fb+locktol*(1 ps) then
vlock := '0';
end if;
llock <= vlock;
end process;
end;
| gpl-3.0 | 57f41f948cb41e0ff1154ce584dbe5f9 | 0.542013 | 3.689949 | false | false | false | false |
yishinli/emc2 | src/hal/drivers/mesa-hostmot2/firmware/src/uartx.vhd | 1 | 9,764 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
-- http://www.mesanet.com
--
-- This program is is licensed under a disjunctive dual license giving you
-- the choice of one of the two following sets of free software/open source
-- licensing terms:
--
-- * GNU General Public License (GPL), version 2.0 or later
-- * 3-clause BSD License
--
--
-- The GNU GPL License:
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
--
--
-- The 3-clause BSD License:
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- * Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- * Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- * Neither the name of Mesa Electronics nor the names of its
-- contributors may be used to endorse or promote products
-- derived from this software without specific prior written
-- permission.
--
--
-- Disclaimer:
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
entity uartx is
Port ( clk : in std_logic;
ibus : in std_logic_vector(31 downto 0);
obus : out std_logic_vector(31 downto 0);
addr : in std_logic_vector(1 downto 0);
pushfifo : in std_logic;
loadbitrate : in std_logic;
readbitrate : in std_logic;
clrfifo : in std_logic;
readfifocount : in std_logic;
loadmode : in std_logic;
readmode : in std_logic;
fifoempty : out std_logic;
txen : in std_logic;
drven : out std_logic;
txdata : out std_logic
);
end uartx;
architecture Behavioral of uartx is
-- FIFO related signals
signal pushdata: std_logic_vector(33 downto 0);
signal popadd: std_logic_vector(3 downto 0) := x"f";
signal popdata: std_logic_vector(33 downto 0);
alias byteshere: std_logic_vector(1 downto 0) is popdata(33 downto 32);
signal datacounter: std_logic_vector(4 downto 0);
signal push: std_logic;
signal pop: std_logic;
signal clear: std_logic;
signal lfifoempty: std_logic;
signal fifohasdata: std_logic;
-- uart interface related signals
constant DDSWidth : integer := 16;
signal BitrateDDSReg : std_logic_vector(DDSWidth-1 downto 0);
signal BitrateDDSAccum : std_logic_vector(DDSWidth-1 downto 0);
alias DDSMSB : std_logic is BitrateDDSAccum(15);
signal OldDDSMSB: std_logic;
signal SampleTime: std_logic;
signal BitCount : std_logic_vector(3 downto 0);
signal BytePointer : std_logic_vector(2 downto 0) := "000";
signal SReg: std_logic_vector(10 downto 0);
signal SendData: std_logic_vector(7 downto 0);
alias SregData: std_logic_vector(7 downto 0)is SReg(9 downto 2);
alias StartBit: std_logic is Sreg(1);
alias StopBit: std_logic is Sreg(10);
alias IdleBit: std_logic is Sreg(0);
signal Go: std_logic := '0';
signal ModeReg: std_logic_vector(6 downto 0);
alias DriveEnDelay: std_logic_vector(3 downto 0) is ModeReg (3 downto 0);
alias FIFOError: std_logic is ModeReg(4);
alias DriveEnAuto: std_logic is ModeReg(5);
alias DriveEnBit: std_logic is ModeReg(6);
signal DriveEnable: std_logic;
signal DriveEnHold: std_logic;
signal WaitingForDrive: std_logic;
signal DriveDelayCount: std_logic_vector(3 downto 0);
component SRL16E
--
generic (INIT : bit_vector);
--
port (D : in std_logic;
CE : in std_logic;
CLK : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
Q : out std_logic);
end component;
begin
fifosrl: for i in 0 to 33 generate
asr16e: SRL16E generic map (x"0000") port map(
D => pushdata(i),
CE => push,
CLK => clk,
A0 => popadd(0),
A1 => popadd(1),
A2 => popadd(2),
A3 => popadd(3),
Q => popdata(i)
);
end generate;
afifo: process (clk,popdata,datacounter)
begin
if rising_edge(clk) then
if push = '1' and pop = '0' then
if datacounter /= 16 then -- a push
-- always increment the data counter if not full
datacounter <= datacounter +1;
popadd <= popadd +1; -- popadd must follow data down shiftreg
else
FIFOError <= '1';
end if;
end if;
if (pop = '1') and (push = '0') and (lfifoempty = '0') then -- a pop
-- always decrement the data counter if not empty
datacounter <= datacounter -1;
popadd <= popadd -1;
end if;
-- if both push and pop are asserted we dont change either counter
if clear = '1' then -- a clear fifo
popadd <= (others => '1');
datacounter <= (others => '0');
FIFOError <= '0';
end if;
end if; -- clk rise
if datacounter = 0 then
lfifoempty <= '1';
else
lfifoempty <= '0';
end if;
fifohasdata <= not lfifoempty;
end process afifo;
asimpleuarttx: process (clk)
begin
if rising_edge(clk) then
if Go = '1' then
BitRateDDSAccum <= BitRateDDSAccum - BitRateDDSReg;
if SampleTime = '1' then
SReg <= '1' & SReg(10 downto 1); -- right shift = LSb first
BitCount <= BitCount -1;
if BitCount = 0 then
Go <= '0';
end if;
end if;
else
BitRateDDSAccum <= (others => '0');
end if;
if pop = '1' then -- just one clock
pop <= '0';
end if;
if Go = '0' then
StartBit <= '0';
StopBit <= '1';
IdleBit <= '1';
BitCount <= "1010";
if fifohasdata = '1' and pop = '0' and txen = '1' and DriveEnHold = '0' then -- UART SReg not busy and we have data
if bytepointer <= ('0'& byteshere) then -- still bytes to send in this double word
SRegData <= SendData;
Go <= '1';
bytepointer <= bytepointer +1;
else
pop <= '1';
bytepointer <= "000";
end if;
end if;
end if;
if DriveEnable = '0' then
DriveDelayCount <= DriveEnDelay;
else
if WaitingForDrive = '1' then
DriveDelayCount <= DriveDelayCount -1;
end if;
end if;
OldDDSMSB <= DDSMSB;
if loadbitrate = '1' then
BitRateDDSReg <= ibus(DDSWidth-1 downto 0);
end if;
if loadmode = '1' then
ModeReg(3 downto 0) <= ibus(3 downto 0);
ModeReg(6 downto 5) <= ibus(6 downto 5);
end if;
end if; -- clk
SampleTime <= (not OldDDSMSB) and DDSMSB;
pushdata <= addr & ibus; -- msbs of FIFO data are address bits to specify data size
push <= pushfifo;
clear <= clrfifo;
if DriveDelayCount /= 0 then
WaitingForDrive <= '1';
else
WaitingForDrive <= '0';
end if;
DriveEnHold <= (not DriveEnable) or WaitingForDrive;
if DriveEnAuto = '1' then
DriveEnable <= (Go or Pop or FIFOHasData) and txen; -- note that this means txen should never be removed -- when there is data to xmit
else -- in the middle of a block transmission
DriveEnable <= DriveEnBit;
end if;
case bytepointer(1 downto 0) is
when "00" => SendData <= PopData(7 downto 0);
when "01" => SendData <= PopData(15 downto 8);
when "10" => SendData <= PopData(23 downto 16);
when "11" => SendData <= PopData(31 downto 24);
when others => null;
end case;
obus <= (others => 'Z');
if readfifocount = '1' then
obus(4 downto 0) <= datacounter;
obus(31 downto 5) <= (others => '0');
end if;
if readbitrate = '1' then
obus(DDSWidth-1 downto 0) <= BitRateDDSReg;
end if;
if readmode = '1' then
obus(6 downto 0) <= ModeReg;
obus(7) <= Go or Pop or FIFOHasData;
end if;
txdata<= SReg(0);
fifoempty <= lfifoempty;
drven <= DriveEnable;
end process asimpleuarttx;
end Behavioral;
| lgpl-2.1 | 69521fae62a4735abb2cafa3ee026462 | 0.624334 | 3.431986 | false | false | false | false |
Gizeta/bjuedc | uart-fpga/narr_sig.vhd | 1 | 1,613 | --------------------------------------------
-- 信号窄化器
-- 在sig_in的上升沿作为启动窄化的信号
-- 窄化的后的信号持续narr_prd个clk周期的高电平
-- 当narr_prd=0时, narr_sig_out就是0了
--------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity narr_sig is
port(
sig_in : in std_logic;
clk : in std_logic;
reset : in std_logic;
narr_prd : in std_logic_vector(7 downto 0); -- narr信号持续的周期数(以clk为周期)
narr_sig_out : out std_logic
);
end narr_sig;
architecture arch of narr_sig is
-- narr信号持续的周期计数器(1 -> narr_prd)
signal narr_prd_cnt : std_logic_vector(7 downto 0);
-- 停止窄化标志 0-窄化, 1-不窄化
signal stop_narr_flag : std_logic;
begin
process(sig_in, reset, clk, stop_narr_flag)
begin
if reset = '1' then
narr_prd_cnt <= X"00";
stop_narr_flag <= '1';
narr_sig_out <= '0';
else
if sig_in = '0' then
narr_prd_cnt <= X"00";
stop_narr_flag <= '0';
narr_sig_out <= '0';
else
if stop_narr_flag = '0' then
if rising_edge(clk) then
narr_prd_cnt <= narr_prd_cnt + '1';
narr_sig_out <= '1';
if narr_prd_cnt = narr_prd then
stop_narr_flag <= '1';
narr_prd_cnt <= X"00";
narr_sig_out <= '0';
end if;
end if;
end if;
end if;
end if;
end process;
end arch;
| mit | 30dbaa145b88137add625f6e32b8b15d | 0.507839 | 2.538062 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/ddr/ahb2mig_7series_ddr3_dq16_ad15_ba3.vhd | 1 | 25,506 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: ahb2mig_7series_ddr3_dq16_ad15_ba3
-- File: ahb2mig_7series_ddr3_dq16_ad15_ba3.vhd
-- Based on: ahb2mig_7series_ddr2_dq16_ad13_ba3.vhd
-- Author: Pascal Trotta
--
-- This is a AHB-2.0 interface for the Xilinx Virtex-7 MIG.
-- Notes: - works only with 32-bit bus
-- - does not replicate output data
-- - does not support MIG interface model
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library gaisler;
use gaisler.all;
use gaisler.ahb2mig_7series_pkg.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
use grlib.config_types.all;
use grlib.config.all;
library std;
use std.textio.all;
entity ahb2mig_7series_ddr3_dq16_ad15_ba3 is
generic(
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
maxwriteburst : integer := 8;
maxreadburst : integer := 8;
SIM_BYPASS_INIT_CAL : string := "OFF";
SIMULATION : string := "FALSE";
USE_MIG_INTERFACE_MODEL : boolean := false
);
port(
ddr3_dq : inout std_logic_vector(15 downto 0);
ddr3_dqs_p : inout std_logic_vector(1 downto 0);
ddr3_dqs_n : inout std_logic_vector(1 downto 0);
ddr3_addr : out std_logic_vector(14 downto 0);
ddr3_ba : out std_logic_vector(2 downto 0);
ddr3_ras_n : out std_logic;
ddr3_cas_n : out std_logic;
ddr3_we_n : out std_logic;
ddr3_reset_n : out std_logic;
ddr3_ck_p : out std_logic_vector(0 downto 0);
ddr3_ck_n : out std_logic_vector(0 downto 0);
ddr3_cke : out std_logic_vector(0 downto 0);
ddr3_dm : out std_logic_vector(1 downto 0);
ddr3_odt : out std_logic_vector(0 downto 0);
ahbso : out ahb_slv_out_type;
ahbsi : in ahb_slv_in_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
calib_done : out std_logic;
rst_n_syn : in std_logic;
rst_n_async : in std_logic;
clk_amba : in std_logic;
sys_clk_i : in std_logic;
-- clk_ref_i : in std_logic;
ui_clk : out std_logic;
ui_clk_sync_rst : out std_logic
);
end ;
architecture rtl of ahb2mig_7series_ddr3_dq16_ad15_ba3 is
type bstate_type is (idle, start, read_cmd, read_data, read_wait, read_output, write_cmd, write_burst);
constant maxburst : integer := 8;
constant maxmigcmds : integer := 3;
constant wrsteps : integer := log2(32);
constant wrmask : integer := log2(32/8);
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_MIG_7SERIES, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask),
others => zero32);
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_MIG_7SERIES, 0, 0, 0),
1 => apb_iobar(paddr, pmask));
type reg_type is record
bstate : bstate_type;
cmd : std_logic_vector(2 downto 0);
cmd_en : std_logic;
wr_en : std_logic;
wr_end : std_logic;
cmd_count : unsigned(31 downto 0);
wr_count : unsigned(31 downto 0);
rd_count : unsigned(31 downto 0);
hready : std_logic;
hwrite : std_logic;
hwdata_burst : std_logic_vector(128*maxmigcmds-1 downto 0);
mask_burst : std_logic_vector(16*maxmigcmds-1 downto 0);
htrans : std_logic_vector(1 downto 0);
hburst : std_logic_vector(2 downto 0);
hsize : std_logic_vector(2 downto 0);
hrdata : std_logic_vector(AHBDW-1 downto 0);
haddr : std_logic_vector(31 downto 0);
haddr_start : std_logic_vector(31 downto 0);
haddr_offset : std_logic_vector(31 downto 0);
hmaster : std_logic_vector(3 downto 0);
int_buffer : unsigned(128*maxmigcmds-1 downto 0);
rd_buffer : unsigned(128*maxmigcmds-1 downto 0);
wdf_data_buffer : std_logic_vector(127 downto 0);
wdf_mask_buffer : std_logic_vector(15 downto 0);
migcommands : integer;
nxt : std_logic;
maxrburst : integer;
end record;
type mig_in_type is record
app_addr : std_logic_vector(28 downto 0);
app_cmd : std_logic_vector(2 downto 0);
app_en : std_logic;
app_wdf_data : std_logic_vector(127 downto 0);
app_wdf_end : std_logic;
app_wdf_mask : std_logic_vector(15 downto 0);
app_wdf_wren : std_logic;
end record;
type mig_out_type is record
app_rd_data : std_logic_vector(127 downto 0);
app_rd_data_end : std_logic;
app_rd_data_valid : std_logic;
app_rdy : std_logic;
app_wdf_rdy : std_logic;
end record;
signal rin, r, rnxt, rnxtin : reg_type;
signal migin : mig_in_type;
signal migout,migoutraw : mig_out_type;
component mig is
port (
ddr3_dq : inout std_logic_vector(15 downto 0);
ddr3_addr : out std_logic_vector(14 downto 0);
ddr3_ba : out std_logic_vector(2 downto 0);
ddr3_ras_n : out std_logic;
ddr3_cas_n : out std_logic;
ddr3_we_n : out std_logic;
ddr3_reset_n : out std_logic;
ddr3_dqs_n : inout std_logic_vector(1 downto 0);
ddr3_dqs_p : inout std_logic_vector(1 downto 0);
ddr3_ck_p : out std_logic_vector(0 downto 0);
ddr3_ck_n : out std_logic_vector(0 downto 0);
ddr3_cke : out std_logic_vector(0 downto 0);
ddr3_dm : out std_logic_vector(1 downto 0);
ddr3_odt : out std_logic_vector(0 downto 0);
sys_clk_i : in std_logic;
-- clk_ref_i : in std_logic;
app_addr : in std_logic_vector(28 downto 0);
app_cmd : in std_logic_vector(2 downto 0);
app_en : in std_logic;
app_wdf_data : in std_logic_vector(127 downto 0);
app_wdf_end : in std_logic;
app_wdf_mask : in std_logic_vector(15 downto 0);
app_wdf_wren : in std_logic;
app_rd_data : out std_logic_vector(127 downto 0);
app_rd_data_end : out std_logic;
app_rd_data_valid : out std_logic;
app_rdy : out std_logic;
app_wdf_rdy : out std_logic;
app_sr_req : in std_logic;
app_ref_req : in std_logic;
app_zq_req : in std_logic;
app_sr_active : out std_logic;
app_ref_ack : out std_logic;
app_zq_ack : out std_logic;
ui_clk : out std_logic;
ui_clk_sync_rst : out std_logic;
init_calib_complete : out std_logic;
sys_rst : in std_logic
);
end component mig;
begin
comb: process( rst_n_syn, r, rin, ahbsi, migout )
-- Design temp variables
variable v,vnxt : reg_type;
variable writedata : std_logic_vector(255 downto 0);
variable wmask : std_logic_vector(AHBDW/4-1 downto 0);
variable shift_steps : natural;
variable hrdata_shift_steps : natural;
variable steps_write : unsigned(31 downto 0);
variable shift_steps_write : natural;
variable shift_steps_write_mask : natural;
variable startaddress : unsigned(v.haddr'length-1 downto 0);
variable start_address : std_logic_vector(v.haddr'length-1 downto 0);
variable step_offset : unsigned(steps_write'length-1 downto 0);
variable haddr_offset : unsigned(steps_write'length-1 downto 0);
begin
-- Make all register visible for the statemachine
v := r; vnxt := rnxt;
-- workout the start address in AHB2MIG buffer based upon
startaddress := resize(unsigned(unsigned(ahbsi.haddr(ahbsi.haddr'left-5 downto 4)) & "000"),startaddress'length);
-- Adjust offset in memory buffer
start_address := std_logic_vector(startaddress);
-- Workout local offset to be able to adust for warp-around
haddr_offset := unsigned(r.haddr_start) - unsigned(unsigned(r.haddr_offset(r.haddr_offset'length-1 downto 4))&"0000");
step_offset := resize(unsigned(haddr_offset(5 downto 4)&"00"),step_offset'length);
-- Fetch AMBA Commands
if (( ahbsi.hsel(hindex) and ahbsi.htrans(1) and ahbsi.hready and not ahbsi.htrans(0)) = '1'
and (ahbsi.hwrite = '0' or ahbsi.hwrite = '1' )) then
vnxt.cmd_count:= (others => '0');
vnxt.wr_count := (others => '0');
vnxt.rd_count := (others => '0');
vnxt.hrdata := (others => '0');
-- Clear old pointers and MIG command signals
vnxt.cmd := (others => '0');
vnxt.cmd_en := '0';
vnxt.wr_en := '0';
vnxt.wr_end := '0';
vnxt.hwrite := '0';
vnxt.hwdata_burst := (others => '0');
vnxt.mask_burst := (others => '0');
-- Hold info regarding transaction and execute
vnxt.hburst := ahbsi.hburst;
vnxt.hwrite := ahbsi.hwrite;
vnxt.hsize := ahbsi.hsize;
vnxt.hmaster := ahbsi.hmaster;
vnxt.hready := '0';
vnxt.htrans := ahbsi.htrans;
vnxt.bstate := start;
vnxt.haddr := start_address;
vnxt.haddr_start := ahbsi.haddr;
vnxt.haddr_offset := ahbsi.haddr;
vnxt.cmd(2 downto 0) := (others => '0');
vnxt.cmd(0) := not ahbsi.hwrite;
if (r.bstate = idle) then vnxt.nxt := '0'; else vnxt.nxt := '1'; end if;
-- Clear some old stuff
vnxt.int_buffer := (others => '0');
vnxt.rd_buffer := (others => '0');
vnxt.wdf_data_buffer := (others => '0');
vnxt.wdf_mask_buffer := (others => '0');
end if;
case r.bstate is
when idle =>
-- Clear old pointers and MIG command signals
v.cmd := (others => '0');
v.cmd_en := '0';
v.wr_en := '0';
v.wr_end := '0';
v.hready := '1';
v.hwrite := '0';
v.hwdata_burst := (others => '0');
v.mask_burst := (others => '0');
v.rd_count := (others => '0');
vnxt.cmd := (others => '0');
vnxt.cmd_en := '0';
vnxt.wr_en := '0';
vnxt.wr_end := '0';
vnxt.hready := '1';
vnxt.hwrite := '0';
vnxt.hwdata_burst := (others => '0');
vnxt.mask_burst := (others => '0');
vnxt.rd_count := (others => '0');
vnxt.wr_count := (others => '0');
vnxt.cmd_count := (others => '0');
-- Check if this is a single or burst transfer (and not a BUSY transfer)
if (( ahbsi.hsel(hindex) and ahbsi.htrans(1) and ahbsi.hready) = '1'
and (ahbsi.hwrite = '0' or ahbsi.hwrite = '1' )) then
-- Hold info regarding transaction and execute
v.hburst := ahbsi.hburst;
v.hwrite := ahbsi.hwrite;
v.hsize := ahbsi.hsize;
v.hmaster := ahbsi.hmaster;
v.hready := '0';
v.htrans := ahbsi.htrans;
v.bstate := start;
v.haddr := start_address;
v.haddr_start := ahbsi.haddr;
v.haddr_offset := ahbsi.haddr;
v.cmd := (others => '0');
v.cmd(0) := not ahbsi.hwrite;
end if;
when start =>
v.migcommands := nbrmigcmds16(r.hwrite,r.hsize,ahbsi.htrans,step_offset,AHBDW);
-- Check if a write command shall be issued to the DDR3 memory
if r.hwrite = '1' then
wmask := (others => '0');
writedata := (others => '0');
if ((ahbsi.htrans /= HTRANS_SEQ) or ((ahbsi.htrans = HTRANS_SEQ) and (r.rd_count > 0) and (r.rd_count <= maxburst))) then
-- work out how many steps we need to shift the input
steps_write := ahbselectdatanoreplicastep16(r.haddr_start(7 downto 2),r.hsize(2 downto 0)) + step_offset;
shift_steps_write := to_integer(shift_left(steps_write,wrsteps));
shift_steps_write_mask := to_integer(shift_left(steps_write,wrmask));
-- generate mask for complete burst (only need to use addr[3:0])
wmask := ahbselectdatanoreplicamask(r.haddr_start(6 downto 0),r.hsize(2 downto 0));
v.mask_burst := r.mask_burst or std_logic_vector(shift_left(resize(unsigned(wmask), r.mask_burst'length),shift_steps_write_mask));
-- fetch all wdata before write to memory can begin (only supports upto 128bits i.e. addr[4:0]
writedata(AHBDW-1 downto 0) := ahbselectdatanoreplica(ahbsi.hwdata(AHBDW-1 downto 0),r.haddr_start(4 downto 0),r.hsize(2 downto 0));
v.hwdata_burst := r.hwdata_burst or std_logic_vector(shift_left(resize(unsigned(writedata),v.hwdata_burst'length),shift_steps_write));
v.haddr_start := ahbsi.haddr;
end if;
-- Check if this is a cont burst longer than internal buffer
if (ahbsi.htrans = HTRANS_SEQ) then
if (r.rd_count < maxburst-1) then
v.hready := '1';
else
v.hready := '0';
end if;
if (r.rd_count >= maxburst) then
if (r.htrans = HTRANS_SEQ) then
v.bstate := write_cmd;
end if;
v.htrans := ahbsi.htrans;
end if;
else
v.bstate := write_cmd;
v.htrans := ahbsi.htrans;
end if;
-- Else issue a read command when ready
else
if migout.app_rdy = '1' and migout.app_wdf_rdy = '1' then
v.cmd := "001";
v.bstate := read_cmd;
v.htrans := ahbsi.htrans;
v.cmd_count := to_unsigned(0,v.cmd_count'length);
end if;
end if;
when write_cmd =>
-- Check if burst has ended due to max size burst
if (ahbsi.htrans /= HTRANS_SEQ) then
v.htrans := (others => '0');
end if;
-- Stop when addr and write command is accepted by mig
if (r.wr_count >= r.migcommands) and (r.cmd_count >= r.migcommands) then
if (r.htrans /= HTRANS_SEQ) then
-- Check if we have a pending transaction
if (vnxt.nxt = '1') then
v := vnxt;
vnxt.nxt := '0';
else
v.bstate := idle;
end if;
else -- Cont burst and work out new offset for next write command
v.bstate := write_burst;
v.hready := '1';
end if;
end if;
when write_burst =>
v.bstate := start;
v.hready := '0';
v.hwdata_burst := (others => '0');
v.mask_burst := (others => '0');
v.haddr := start_address;
v.haddr_offset := ahbsi.haddr;
-- Check if we have a pending transaction
if (vnxt.nxt = '1') then
v := vnxt;
vnxt.nxt := '0';
end if;
when read_cmd =>
v.hready := '0';
v.rd_count := (others => '0');
-- stop when read command is accepted ny mig.
if (r.cmd_count >= r.migcommands) then
v.bstate := read_data;
--v.int_buffer := (others => '0');
end if;
when read_data =>
-- We are not ready yet so issue a read command to the memory controller
v.hready := '0';
-- If read data is valid store data in buffers
if (migout.app_rd_data_valid = '1') then
v.rd_count := r.rd_count + 1;
-- Viviado seems to misinterpet the following shift construct and
-- therefore changed to a if-else statement
--v.int_buffer := r.int_buffer or shift_left( resize(unsigned(migout.app_rd_data),r.int_buffer'length),
-- to_integer(shift_left(r.rd_count,9)));
if (r.rd_count = 0) then
v.int_buffer(127 downto 0) := unsigned(migout.app_rd_data);
elsif (r.rd_count = 1) then
v.int_buffer(255 downto 128) := unsigned(migout.app_rd_data);
end if;
end if;
if (r.rd_count >= r.migcommands) then
v.rd_buffer := r.int_buffer;
v.bstate := read_output;
v.rd_count := to_unsigned(0,v.rd_count'length);
end if;
when read_output =>
-- Data is fetched from memory and ready to be transfered
v.hready := '1';
-- uses the "wr_count" signal to keep track of number of bytes output'd to AHB
-- Select correct 32bit output
v.hrdata := ahbselectdatanoreplicaoutput16(r.haddr_start(7 downto 0),r.wr_count,r.hsize,r.rd_buffer,r.wr_count,false);
-- Count number of bytes send
v.wr_count := r.wr_count + 1;
-- Set maximum read burst depending on the starting address offset
case r.haddr_start(3 downto 2) is
when "01" => v.maxrburst := 7;
when "10" => v.maxrburst := 6;
when "11" => v.maxrburst := 5;
when others => v.maxrburst := 8;
end case;
-- Check if this was the last transaction
if (r.wr_count >= v.maxrburst-1) then
v.bstate := read_wait;
end if;
-- Check if transfer was interrupted or no burst
if (ahbsi.htrans = HTRANS_IDLE) or ((ahbsi.htrans = HTRANS_NONSEQ) and (r.wr_count < maxburst)) then
v.bstate := read_wait;
v.wr_count := (others => '0');
v.rd_count := (others => '0');
v.cmd_count := (others => '0');
-- Check if we have a pending transaction
if (vnxt.nxt = '1') then
v := vnxt;
vnxt.nxt := '0';
v.bstate := start;
end if;
end if;
when read_wait =>
if ((r.wr_count >= v.maxrburst) and (ahbsi.htrans = HTRANS_SEQ)) then
v.hready := '0';
v.bstate := start;
v.haddr_start := ahbsi.haddr;
v.haddr := start_address;
v.haddr_offset := ahbsi.haddr;
else
-- Check if we have a pending transaction
if (vnxt.nxt = '1') then
v := vnxt;
vnxt.nxt := '0';
v.bstate := start;
else
v.bstate := idle;
v.hready := '1';
end if;
end if;
when others =>
v.bstate := idle;
end case;
if ((ahbsi.htrans /= HTRANS_SEQ) and (r.bstate = start)) then
v.hready := '0';
end if;
if rst_n_syn = '0' then
v.bstate := idle; v.hready := '1'; v.cmd_en := '0'; v.wr_en := '0'; v.wr_end := '0'; v.maxrburst := maxburst;
end if;
rin <= v;
rnxtin <= vnxt;
end process;
ahbso.hready <= r.hready;
ahbso.hresp <= "00";
ahbso.hrdata <= ahbdrivedata(r.hrdata);
migin.app_addr <= r.haddr(28 downto 2) & "00";
migin.app_cmd <= r.cmd;
migin.app_en <= r.cmd_en;
migin.app_wdf_data <= r.wdf_data_buffer;
migin.app_wdf_end <= r.wr_end;
migin.app_wdf_mask <= r.wdf_mask_buffer;
migin.app_wdf_wren <= r.wr_en;
ahbso.hconfig <= hconfig;
ahbso.hirq <= (others => '0');
ahbso.hindex <= hindex;
ahbso.hsplit <= (others => '0');
apbo.pindex <= pindex;
apbo.pconfig <= pconfig;
apbo.pirq <= (others => '0');
apbo.prdata <= (others => '0');
regs : process(clk_amba)
begin
if rising_edge(clk_amba) then
-- Copy variables into registers (Default values)
r <= rin;
rnxt <= rnxtin;
-- add extra pipe-stage for read data
migout <= migoutraw;
-- IDLE Clear
if ((r.bstate = idle) or (r.bstate = read_wait)) then
r.cmd_count <= (others => '0');
r.wr_count <= (others => '0');
r.rd_count <= (others => '0');
end if;
if (r.bstate = write_burst) then
r.cmd_count <= (others => '0');
r.wr_count <= (others => '0');
r.rd_count <= to_unsigned(1,r.rd_count'length);
end if;
-- Read AHB write data
if (r.bstate = start) and (r.hwrite = '1') then
r.rd_count <= r.rd_count + 1;
end if;
-- Write command repsonse
if r.bstate = write_cmd then
if (r.cmd_count < 1) then
r.cmd_en <= '1';
end if;
if (migoutraw.app_rdy = '1') and (r.cmd_en = '1' ) then
r.cmd_count <= r.cmd_count + 1;
if (r.cmd_count < r.migcommands-1 ) then
r.haddr <= r.haddr + 8;
end if;
if (r.cmd_count >= r.migcommands-1) then
r.cmd_en <= '0';
end if;
end if;
if (r.wr_count < 1 ) then
r.wr_en <= '1';
r.wr_end <= '1';
r.wdf_mask_buffer <= not r.mask_burst(15 downto 0);
r.wdf_data_buffer <= r.hwdata_burst(127 downto 0);
end if;
if (migoutraw.app_wdf_rdy = '1') and (r.wr_en = '1' ) then
if (r.wr_count = 0) then
r.wdf_mask_buffer <= not r.mask_burst(31 downto 16);
r.wdf_data_buffer <= r.hwdata_burst(255 downto 128);
elsif (r.wr_count = 1) then --to support 3 migcmds
r.wdf_mask_buffer <= not r.mask_burst(47 downto 32);
r.wdf_data_buffer <= r.hwdata_burst(383 downto 256);
else
r.wdf_mask_buffer <= not r.mask_burst(31 downto 16);
r.wdf_data_buffer <= r.hwdata_burst(255 downto 128);
end if;
r.wr_count <= r.wr_count + 1;
if (r.wr_count >= r.migcommands - 1) then
r.wr_en <= '0';
r.wr_end <= '0';
end if;
end if;
end if;
-- Burst Write Wait
if r.bstate = write_burst then
r.cmd_count <= (others => '0');
r.wr_count <= (others => '0');
r.rd_count <= (others => '0');
end if;
-- Read command repsonse
if r.bstate = read_cmd then
if (r.cmd_count < 1) then
r.cmd_en <= '1';
end if;
if (migoutraw.app_rdy = '1') and (r.cmd_en = '1' ) then
r.cmd_count <= r.cmd_count + 1;
if (r.cmd_count < r.migcommands-1 ) then
r.haddr <= r.haddr + 8;
end if;
if (r.cmd_count >= r.migcommands-1) then
r.cmd_en <= '0';
end if;
end if;
end if;
end if;
end process;
MCB_inst : mig
port map (
ddr3_dq => ddr3_dq,
ddr3_dqs_p => ddr3_dqs_p,
ddr3_dqs_n => ddr3_dqs_n,
ddr3_addr => ddr3_addr,
ddr3_ba => ddr3_ba,
ddr3_ras_n => ddr3_ras_n,
ddr3_cas_n => ddr3_cas_n,
ddr3_we_n => ddr3_we_n,
ddr3_reset_n => ddr3_reset_n,
ddr3_ck_p => ddr3_ck_p,
ddr3_ck_n => ddr3_ck_n,
ddr3_cke => ddr3_cke,
ddr3_dm => ddr3_dm,
ddr3_odt => ddr3_odt,
sys_clk_i => sys_clk_i,
-- clk_ref_i => clk_ref_i,
app_addr => migin.app_addr,
app_cmd => migin.app_cmd,
app_en => migin.app_en,
app_rdy => migoutraw.app_rdy,
app_wdf_data => migin.app_wdf_data,
app_wdf_end => migin.app_wdf_end,
app_wdf_mask => migin.app_wdf_mask,
app_wdf_wren => migin.app_wdf_wren,
app_wdf_rdy => migoutraw.app_wdf_rdy,
app_rd_data => migoutraw.app_rd_data,
app_rd_data_end => migoutraw.app_rd_data_end,
app_rd_data_valid => migoutraw.app_rd_data_valid,
app_sr_req => '0',
app_ref_req => '0',
app_zq_req => '0',
app_sr_active => open,
app_ref_ack => open,
app_zq_ack => open,
ui_clk => ui_clk,
ui_clk_sync_rst => ui_clk_sync_rst,
init_calib_complete => calib_done,
sys_rst => rst_n_async
);
end;
| gpl-3.0 | 5a3f4e2c2e219549e54364678a5b9869 | 0.522191 | 3.44257 | false | false | false | false |
pwsoft/fpga_examples | rtl/ttl/ttl_7410.vhd | 1 | 2,239 | -- -----------------------------------------------------------------------
--
-- Syntiac VHDL support files.
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2018 by Peter Wendrich ([email protected])
-- http://www.syntiac.com
--
-- This source file is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- -----------------------------------------------------------------------
-- Tripple 3-input NAND gate
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use work.ttl_pkg.all;
-- -----------------------------------------------------------------------
entity ttl_7410 is
generic (
latency : integer := 1
);
port (
emuclk : in std_logic;
p1 : in ttl_t;
p2 : in ttl_t;
p13 : in ttl_t;
p12 : out ttl_t;
p3 : in ttl_t;
p4 : in ttl_t;
p5 : in ttl_t;
p6 : out ttl_t;
p9 : in ttl_t;
p10 : in ttl_t;
p11 : in ttl_t;
p8 : out ttl_t
);
end entity;
architecture rtl of ttl_7410 is
signal p6_loc : ttl_t;
signal p8_loc : ttl_t;
signal p12_loc : ttl_t;
begin
p6_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p6_loc, q => p6);
p8_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p8_loc, q => p8);
p12_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p12_loc, q => p12);
p6_loc <= not(p3 and p4 and p5);
p8_loc <= not(p9 and p10 and p11);
p12_loc <= not(p1 and p2 and p13);
end architecture;
| lgpl-2.1 | 04e837cf27cf0ca0549226ad391d78d4 | 0.558285 | 3.336811 | false | false | false | false |
EliasLuiz/TCC | Teste/MemoTableT.vhd | 1 | 3,243 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
use work.Constants.all;
use work.DefTypes.all;
ENTITY MemoTableT IS
--ENTITY TraceMemory IS
PORT
(
Clock : IN STD_LOGIC := '1';
WAddress : IN STD_LOGIC_VECTOR (MemoTableTWayAddressLenght-1 DOWNTO 0);
WData : IN MemoTableTTrace;
WEnable : IN STD_LOGIC := '0';
RAddress : IN STD_LOGIC_VECTOR (MemoTableTWayAddressLenght-1 DOWNTO 0);
RData : OUT MemoTableTNPCTagBus
);
END MemoTableT;
--END TraceMemory;
ARCHITECTURE SYN OF MemoTableT IS
--ARCHITECTURE SYN OF TraceMemory IS
COMPONENT MemoTableTNPCTag
PORT (
Clock : IN STD_LOGIC := '1';
WAddress : IN STD_LOGIC_VECTOR (MemoTableTWayAddressLenght-1 DOWNTO 0);
WData : IN MemoTableTNPCTagBus;
WEnable : IN STD_LOGIC := '0';
RAddress : IN STD_LOGIC_VECTOR (MemoTableTWayAddressLenght-1 DOWNTO 0);
RData : OUT MemoTableTNPCTagBus
);
END COMPONENT;
COMPONENT MemoTableTLRUCounter
PORT (
Clock : IN STD_LOGIC := '1';
WAddress : IN STD_LOGIC_VECTOR (MemoTableTWayAddressLenght-1 DOWNTO 0);
WData : IN MemoTableTLRUCounterBus;
WEnable : IN STD_LOGIC := '0';
RAddress : IN STD_LOGIC_VECTOR (MemoTableTWayAddressLenght-1 DOWNTO 0);
LRUEnable: BUFFER STD_LOGIC_VECTOR(MemoTableTAssociativity-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT MemoTableTInput
PORT (
Clock : IN STD_LOGIC := '1';
WAddress : IN STD_LOGIC_VECTOR (MemoTableTWayAddressLenght-1 DOWNTO 0);
WData : IN MemoTableTInputBus;
WEnable : IN STD_LOGIC := '0';
RAddress : IN STD_LOGIC_VECTOR (MemoTableTWayAddressLenght-1 DOWNTO 0);
RData : OUT MemoTableTInputBus
);
END COMPONENT;
COMPONENT MemoTableTOutput
PORT (
Clock : IN STD_LOGIC := '1';
WAddress : IN STD_LOGIC_VECTOR (MemoTableTWayAddressLenght-1 DOWNTO 0);
WData : IN MemoTableTOutputBus;
WEnable : IN STD_LOGIC := '0';
RAddress : IN STD_LOGIC_VECTOR (MemoTableTWayAddressLenght-1 DOWNTO 0);
RData : OUT MemoTableTOutputBus
);
END COMPONENT;
SIGNAL InputIn: MemoTableTInputBus;
SIGNAL InputOut: MemoTableTInputBus;
SIGNAL OutputIn: MemoTableTOutputBus;
SIGNAL OutputOut: MemoTableTOutputBus;
SIGNAL LRUCounterIn: MemoTableTLRUCounterBus;
SIGNAL LRUCounterOut: STD_LOGIC_VECTOR(MemoTableTAssociativity-1 DOWNTO 0);
SIGNAL NPCTagIn: MemoTableTNPCTagBus;
SIGNAL NPCTagOut: MemoTableTNPCTagBus;
BEGIN
MemoTableTInput_cmp : MemoTableTInput
PORT MAP (
WAddress => WAddress,
Clock => Clock,
WData => InputIn,
WEnable => WEnable,
RAddress => RAddress,
RData => InputOut
);
MemoTableTOutput_cmp : MemoTableTOutput
PORT MAP (
WAddress => WAddress,
Clock => Clock,
WData => OutputIn,
WEnable => WEnable,
RAddress => RAddress,
RData => OutputOut
);
MemoTableTLRUCounter_cmp : MemoTableTLRUCounter
PORT MAP (
WAddress => WAddress,
Clock => Clock,
WData => LRUCounterIn,
WEnable => WEnable,
RAddress => RAddress,
LRUEnable=> LRUCounterOut
);
MemoTableTNPCTag_cmp : MemoTableTNPCTag
PORT MAP (
WAddress => WAddress,
Clock => Clock,
WData => NPCTagIn,
WEnable => WEnable,
RAddress => RAddress,
RData => NPCTagOut
);
mem: FOR i IN 0 TO MemoTableTAssociativity-1 GENERATE
END GENERATE mem;
END SYN;
| gpl-3.0 | b99501e4bf522e9c649f21ce616c677b | 0.717237 | 2.588188 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/ambatest/ahbtbs.vhd | 1 | 5,480 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ahbtbs
-- File: ahbtbs.vhd
-- Author: Nils-Johan Wessman - Gaisler Research
-- Description: AMBA testbench slave
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.misc.all;
use work.ahbtbp.all;
entity ahbtbs is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
tech : integer := DEFMEMTECH;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbtbs is
constant abits : integer := log2(kbytes) + 8;
constant ws : std_logic_vector(7 downto 0) :="00000000";
constant retry : integer := 0;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, 0, 0, abits+2, 0),
4 => ahb_membar(haddr, '1', '1', hmask),
others => zero32);
type reg_type is record
hwrite : std_ulogic;
hready : std_ulogic;
hsel : std_ulogic;
addr : std_logic_vector(abits+1 downto 0);
size : std_logic_vector(1 downto 0);
hresp : std_logic_vector(1 downto 0);
ws : std_logic_vector(7 downto 0);
rty : std_logic_vector(3 downto 0);
retry : std_logic;
end record;
signal r, c : reg_type;
signal ramsel : std_ulogic;
signal write : std_logic_vector(3 downto 0);
signal ramaddr : std_logic_vector(abits-1 downto 0);
signal ramdata : std_logic_vector(31 downto 0);
begin
comb : process (ahbsi, r, rst, ramdata)
variable bs : std_logic_vector(3 downto 0);
variable v : reg_type;
variable haddr : std_logic_vector(abits-1 downto 0);
begin
v := r; v.hready := '1'; bs := (others => '0');
v.hresp := HRESP_OKAY;
if ahbsi.hready = '1' then
v.hsel := ahbsi.hsel(hindex) and ahbsi.htrans(1);
v.hwrite := ahbsi.hwrite and v.hsel;
v.addr := ahbsi.haddr(abits+1 downto 0);
v.size := ahbsi.hsize(1 downto 0);
v.ws := ws;
--v.retry := retry;
if retry = 1 then
if v.hsel = '1' then
v.rty := r.rty - 1;
if r.rty = "0000" then
v.retry := '0';
v.rty := "0010";
else
v.retry := '1';
end if;
end if;
else
v.retry := '0';
end if;
end if;
if r.ws /= "00000000" and r.hsel = '1' then
v.ws := r.ws - 1;
end if;
if v.ws /= "00000000" and v.hsel = '1' then
v.hready := '0';
elsif v.hsel = '1' and v.retry = '1' then
if r.hresp = HRESP_OKAY then
v.hready := '0';
v.hresp := HRESP_RETRY;
else
v.hready := '1';
v.hresp := HRESP_RETRY;
v.retry := '0';
end if;
end if;
if (r.hwrite or not r.hready) = '1' then
haddr := r.addr(abits+1 downto 2);
else
haddr := ahbsi.haddr(abits+1 downto 2); bs := (others => '0');
end if;
if r.hwrite = '1' and r.hready = '1' then
case r.size(1 downto 0) is
when "00" => bs (conv_integer(r.addr(1 downto 0))) := '1';
when "01" => bs := r.addr(1) & r.addr(1) & not (r.addr(1) & r.addr(1));
when others => bs := (others => '1');
end case;
--v.hready := not (v.hsel and not ahbsi.hwrite);
--v.hwrite := v.hwrite and v.hready;
end if;
if rst = '0' then
v.hwrite := '0'; v.hready := '1'; v.ws := ws;
v.rty := "0010";
end if;
write <= bs; ramsel <= v.hsel or r.hwrite; ahbso.hready <= r.hready;
ramaddr <= haddr; c <= v; ahbso.hrdata <= ramdata;
end process;
ahbso.hresp <= r.hresp; --"00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
ra : for i in 0 to 3 generate
aram : syncram generic map (tech, abits, 8) port map (
clk, ramaddr, ahbsi.hwdata(i*8+7 downto i*8),
ramdata(i*8+7 downto i*8), ramsel, write(3-i));
end generate;
reg : process (clk)
begin
if rising_edge(clk ) then r <= c; end if;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbram" & tost(hindex) &
": AHB SRAM Module rev 1, " & tost(kbytes) & " kbytes");
-- pragma translate_on
end;
| gpl-3.0 | 12d4b7fd4a98a286e6ec7866f747f709 | 0.566241 | 3.370234 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-digilent-atlys/leon3mp.vhd | 1 | 32,143 | ------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2011 Jiri Gaisler, Gaisler Research
--
-- Modified by Joris van Rantwijk to support Digilent Atlys board.
--
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
-- led(6) = dsuact (LED 6 ON when processor in debug mode)
-- led(7) = not errorn (LED 7 ON when processor in error mode)
-- switch(6) = dsubre (SWITCH 6 ON to force DSU break)
-- switch(7) = dsuen (SWITCH 7 ON to enable debug mode)
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.amba.all;
use grlib.stdlib.all;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.ddrpkg.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.spi.all;
use gaisler.net.all;
use gaisler.jtag.all;
-- pragma translate_off
use gaisler.sim.all;
-- pragma translate_on
library esa;
use esa.memoryctrl.all;
library unisim;
use unisim.vcomponents.OBUFDS;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
resetn : in std_ulogic;
clk : in std_ulogic; -- 100 MHz board clock
-- DDR2 memory
ddr_clk : out std_logic;
ddr_clkb : out std_logic;
ddr_cke : out std_logic;
ddr_odt : out std_logic;
ddr_we : out std_ulogic;
ddr_ras : out std_ulogic;
ddr_cas : out std_ulogic;
ddr_dm : out std_logic_vector (1 downto 0);
ddr_dqs : inout std_logic_vector (1 downto 0);
ddr_dqsn : inout std_logic_vector (1 downto 0);
ddr_ad : out std_logic_vector (12 downto 0);
ddr_ba : out std_logic_vector (2 downto 0);
ddr_dq : inout std_logic_vector (15 downto 0);
ddr_rzq : inout std_ulogic;
ddr_zio : inout std_ulogic;
-- dsuen : in std_ulogic; -- switch(7)
-- dsubre : in std_ulogic; -- switch(6)
-- dsuact : out std_ulogic; -- led(6)
-- errorn : out std_ulogic; -- led(7)
txd1 : out std_ulogic; -- UART1 tx data
rxd1 : in std_ulogic; -- UART1 rx data
-- GPIO
pmoda : inout std_logic_vector(7 downto 0);
switch : in std_logic_vector(7 downto 0);
led : out std_logic_vector(7 downto 0);
button : in std_logic_vector(4 downto 0);
-- MII Ethernet
erx_clk : in std_ulogic;
erxd : in std_logic_vector(7 downto 0);
erx_dv : in std_ulogic;
erx_er : in std_ulogic;
erx_col : in std_ulogic;
erx_crs : in std_ulogic;
etx_clk : in std_ulogic;
etxd : out std_logic_vector(7 downto 0);
etx_en : out std_ulogic;
etx_er : out std_ulogic;
erst : out std_ulogic;
egtxclk : out std_ulogic;
emdc : out std_ulogic;
emdio : inout std_logic;
emdint : in std_ulogic;
-- PS/2
kbd_clk : inout std_logic;
kbd_data : inout std_logic;
mou_clk : inout std_logic;
mou_data : inout std_logic;
-- SPI flash
spi_sel_n : inout std_ulogic;
spi_clk : out std_ulogic;
spi_miso : in std_ulogic;
spi_mosi : inout std_ulogic;
-- HDMI port
tmdstx_clk_p : out std_logic;
tmdstx_clk_n : out std_logic;
tmdstx_dat_p : out std_logic_vector(2 downto 0);
tmdstx_dat_n : out std_logic_vector(2 downto 0)
);
end entity;
architecture rtl of leon3mp is
attribute syn_netlist_hierarchy : boolean;
attribute syn_netlist_hierarchy of rtl : architecture is false;
constant maxahbm : integer := CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG;
signal vcc, gnd : std_logic;
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdo : sdram_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, rstraw : std_ulogic;
signal clk200 : std_ulogic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal ethi : eth_in_type;
signal etho : eth_out_type;
signal gpti : gptimer_in_type;
signal gpto : gptimer_out_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal lock, calib_done, lclk : std_ulogic;
signal rstext : std_ulogic;
signal rstint : std_ulogic;
signal errorp : std_ulogic;
signal tck, tckn, tms, tdi, tdo : std_ulogic;
signal ddr2clk : std_ulogic;
signal ddr0_clk_fb : std_ulogic;
signal ddr0_clk : std_logic_vector(2 downto 0);
signal ddr0_clkb : std_logic_vector(2 downto 0);
signal ddr0_cke : std_logic_vector(1 downto 0);
signal ddr0_odt : std_logic_vector(1 downto 0);
signal ddr0_ad : std_logic_vector(13 downto 0);
signal ddr0_lock: std_ulogic;
signal spmi : spimctrl_in_type;
signal spmo : spimctrl_out_type;
signal kbdi : ps2_in_type;
signal kbdo : ps2_out_type;
signal moui : ps2_in_type;
signal mouo : ps2_out_type;
signal vgao : apbvga_out_type;
signal video_clk : std_logic;
signal video_fastclk : std_logic;
signal video_clksel : std_logic_vector(1 downto 0);
signal tmds_clk : std_logic;
signal tmds_dat : std_logic_vector(2 downto 0);
constant BOARD_FREQ : integer := 100000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
constant IOAEN : integer := 1;
-- constant DDR2_FREQ : integer := 150000; -- DDR2 input frequency in KHz
signal stati : ahbstat_in_type;
signal leon_rstn : std_ulogic;
signal fpi : grfpu_in_vector_type;
signal fpo : grfpu_out_vector_type;
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_preserve of ddr2clk : signal is true;
attribute keep of ddr2clk : signal is true;
attribute syn_preserve of clkm : signal is true;
attribute keep of clkm : signal is true;
attribute syn_preserve of video_clk : signal is true;
attribute keep of video_clk : signal is true;
attribute syn_preserve of video_fastclk : signal is true;
attribute keep of video_fastclk : signal is true;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= '1'; gnd <= '0';
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
clk_pad : clkpad generic map (tech => padtech) port map (clk, lclk);
clkgen0 : clkgen -- clock generator
generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
CFG_CLK_NOFB, 0, 0, 0, BOARD_FREQ)
port map (clkin => lclk, pciclkin => lclk,
clk => clkm, clkn => open, clk2x => open,
sdclk => open, pciclk => open,
cgi => cgi, cgo => cgo,
clk4x => open, clk1xu => open, clk2xu => clk200);
resetn_pad : inpad generic map (tech => padtech) port map (resetn, rstext);
rst0 : rstgen -- reset generator
port map (rstint, clkm, lock, rstn, rstraw);
lock <= cgo.clklock and ddr0_lock;
-- Generate clean internal reset from external reset and watchdog.
rst1 : process (lclk, rstext) is
variable v_shift: std_logic_vector(3 downto 0);
variable v_wdog: std_logic_vector(2 downto 0);
begin
if rstext = '0' then
rstint <= '0';
v_shift := (others => '0');
v_wdog := (others => '0');
elsif rising_edge(lclk) then
rstint <= v_shift(0);
if CFG_GPT_WDOGEN /= 0 and v_wdog(0) = '1' then
v_shift := (others => '0');
else
v_shift := '1' & v_shift(3 downto 1);
end if;
if CFG_GPT_WDOGEN /= 0 then
v_wdog(0) := v_wdog(2) and not v_wdog(1);
v_wdog(1) := v_wdog(2);
v_wdog(2) := gpto.wdog;
end if;
end if;
end process;
leon_rstn <= rstn and spmo.initialized;
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
ioen => IOAEN, nahbm => maxahbm, nahbs => 16)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
nosh : if CFG_GRFPUSH = 0 generate
cpu : for i in 0 to CFG_NCPU-1 generate
l3ft : if CFG_LEON3FT_EN /= 0 generate
leon3ft0 : leon3ft -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_IUFT_EN, CFG_FPUFT_EN, CFG_CACHE_FT_EN, CFG_RF_ERRINJ,
CFG_CACHE_ERRINJ, CFG_DFIXED, CFG_LEON3_NETLIST, CFG_SCAN, CFG_MMU_PAGE,
CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, leon_rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), clkm);
end generate;
l3s : if CFG_LEON3FT_EN = 0 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, leon_rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
end generate;
end generate;
sh : if CFG_GRFPUSH = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
l3ft : if CFG_LEON3FT_EN /= 0 generate
leon3ft0 : leon3ftsh -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_IUFT_EN, CFG_FPUFT_EN, CFG_CACHE_FT_EN, CFG_RF_ERRINJ,
CFG_CACHE_ERRINJ, CFG_DFIXED, CFG_LEON3_NETLIST, CFG_SCAN, CFG_MMU_PAGE,
CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, leon_rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), clkm, fpi(i), fpo(i));
end generate;
l3s : if CFG_LEON3FT_EN = 0 generate
u0 : leon3sh -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, leon_rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), fpi(i), fpo(i));
end generate;
end generate;
grfpush0 : grfpushwx generic map ((CFG_FPU-1), CFG_NCPU, fabtech)
port map (clkm, rstn, fpi, fpo);
end generate;
-- LED(7) = error
errorp <= not dbgo(0).error;
led1_pad : outpad generic map (tech => padtech) port map (led(7), errorp);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
end generate;
nodsu : if CFG_DSU = 0 generate
dsuo.tstop <= '0'; dsuo.active <= '0'; ahbso(2) <= ahbs_none;
end generate;
-- SWITCH(7) = dsuen
dsuen_pad : inpad generic map (tech => padtech) port map (switch(7), dsui.enable);
-- SWITCH(6) = dsubre
dsubre_pad : inpad generic map (tech => padtech) port map (switch(6), dsui.break);
-- LED(6) = dsuact
dsuact_pad : outpad generic map (tech => padtech) port map (led(6), dsuo.active);
dcomgen : if CFG_AHB_UART = 1 generate
dcom0: ahbuart -- Debug UART
generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (rxd1, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (txd1, duo.txd);
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd);
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
mctrl_gen : if (CFG_MCTRL_LEON2 /= 0) generate
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "00";
memi.brdyn <= '0'; memi.bexcn <= '1';
mctrl0 : mctrl generic map (hindex => 0, pindex => 0,
paddr => 0, srbanks => 2, ram8 => CFG_MCTRL_RAM8BIT,
ram16 => CFG_MCTRL_RAM16BIT, sden => CFG_MCTRL_SDEN,
invclk => CFG_CLK_NOFB, sepbus => CFG_MCTRL_SEPBUS,
pageburst => CFG_MCTRL_PAGE, rammask => 0, iomask => 0)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
memi.data <= (others => '0'); -- Atlys board has no asynchronous memory bus
memi.sd <= (others => '0'); -- Atlys board has no classic SDRAM
end generate;
-----------------------------------------------------------------------
--- Test report module ----------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
test0 : ahbrep generic map (hindex => 5, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(5));
-- pragma translate_on
----------------------------------------------------------------------
--- DDR2 memory controller ------------------------------------------
----------------------------------------------------------------------
ddr_gen : if (CFG_DDR2SP = 1) generate
ddr0: ddr2spa
generic map (
fabtech => fabtech,
memtech => memtech,
rskew => 0,
hindex => 4,
haddr => 16#400#,
hmask => 16#f80#,
ioaddr => 16#001#,
iomask => 16#fff#,
MHz => CPU_FREQ/1000,
TRFC => CFG_DDR2SP_TRFC,
clkmul => 6,
clkdiv => 2,
col => CFG_DDR2SP_COL,
Mbyte => CFG_DDR2SP_SIZE,
rstdel => 200,
pwron => CFG_DDR2SP_INIT,
ddrbits => CFG_DDR2SP_DATAWIDTH,
ahbfreq => CPU_FREQ/1000,
readdly => 1,
norefclk => 0,
odten => 3,
dqsgating => 0,
nosync => CFG_DDR2SP_NOSYNC,
eightbanks => 1,
dqsse => 0,
burstlen => 8,
ft => CFG_DDR2SP_FTEN,
ftbits => CFG_DDR2SP_FTWIDTH,
bigmem => 0,
raspipe => 0 )
port map (
rst_ddr => rstraw,
rst_ahb => rstn,
clk_ddr => clkm,
clk_ahb => clkm,
clkref200 => clk200,
lock => ddr0_lock,
clkddro => ddr2clk,
clkddri => ddr2clk,
ahbsi => ahbsi,
ahbso => ahbso(4),
ddr_clk => ddr0_clk,
ddr_clkb => ddr0_clkb,
ddr_clk_fb_out => ddr0_clk_fb,
ddr_clk_fb => ddr0_clk_fb,
ddr_cke => ddr0_cke,
ddr_csb => open,
ddr_web => ddr_we,
ddr_rasb => ddr_ras,
ddr_casb => ddr_cas,
ddr_dm => ddr_dm,
ddr_dqs => ddr_dqs,
ddr_dqsn => ddr_dqsn,
ddr_ad => ddr0_ad,
ddr_ba => ddr_ba,
ddr_dq => ddr_dq,
ddr_odt => ddr0_odt,
ce => open );
ddr_clk <= ddr0_clk(0);
ddr_clkb <= ddr0_clkb(0);
ddr_cke <= ddr0_cke(0);
ddr_odt <= ddr0_odt(0);
ddr_ad <= ddr0_ad(12 downto 0);
ddr_rzq <= 'Z';
ddr_zio <= 'Z';
end generate;
ddr_nogen : if (CFG_DDR2SP /= 1) generate
ddr0_lock <= '1';
ddrcke_nopad : outpad generic map (tech => padtech) port map (ddr_cke, gnd);
end generate;
----------------------------------------------------------------------
--- SPI Memory Controller--------------------------------------------
----------------------------------------------------------------------
-- Numonyx N25Q12 16 MByte SPI flash memory
-- SPI memory controller is mapped at address 0 if AHBROM is disabled.
-- If AHBROM is enabled then the SPI Flash area is mapped at 0xe0000000
spimc: if CFG_SPIMCTRL = 1 generate
spimctrl0 : spimctrl -- SPI Memory Controller
generic map (hindex => 3, hirq => 11, faddr => 16#e00#*CFG_AHBROMEN,
fmask => 16#ff0#,
ioaddr => 16#002#, iomask => 16#fff#,
spliten => CFG_SPLIT, oepol => 0,
sdcard => CFG_SPIMCTRL_SDCARD,
readcmd => CFG_SPIMCTRL_READCMD,
dummybyte => CFG_SPIMCTRL_DUMMYBYTE,
dualoutput => CFG_SPIMCTRL_DUALOUTPUT,
scaler => CFG_SPIMCTRL_SCALER,
altscaler => CFG_SPIMCTRL_ASCALER,
pwrupcnt => CFG_SPIMCTRL_PWRUPCNT,
offset => CFG_SPIMCTRL_OFFSET)
port map (rstn, clkm, ahbsi, ahbso(3), spmi, spmo);
miso_pad : inpad generic map (tech => padtech)
port map (spi_miso, spmi.miso);
mosi_pad : iopad generic map (tech => padtech)
port map (spi_mosi, spmo.mosi, spmo.mosioen , spmi.mosi);
sck_pad : outpad generic map (tech => padtech)
port map (spi_clk, spmo.sck);
spisel_pad : odpad generic map (tech => padtech)
port map (spi_sel_n, spmo.csn);
end generate;
nospimc : if CFG_SPIMCTRL = 0 generate
spmo.initialized <= '1';
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR, nslaves => 16)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.extclk <= '0';
u1i.ctsn <= '0';
rxd1_pad : inpad generic map (tech => padtech) port map (rxd1, u1i.rxd);
txd1_pad : outpad generic map (tech => padtech) port map (txd1, u1o.txd);
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
notxd : if CFG_UART1_ENABLE = 0 and CFG_AHB_UART = 0 generate
notxd_pad : outpad generic map (tech => padtech) port map (txd1, vcc);
end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW, wdog => CFG_GPT_WDOGEN*CFG_GPT_WDOG)
port map (rstn, clkm, apbi, apbo(3), gpti, gpto);
gpti <= gpti_dhalt_drive(dsuo.tstop);
end generate;
nogpt : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
kbd : if CFG_KBD_ENABLE /= 0 generate
ps21 : apbps2 generic map(pindex => 4, paddr => 4, pirq => 4)
port map(rstn, clkm, apbi, apbo(4), moui, mouo);
ps20 : apbps2 generic map(pindex => 5, paddr => 5, pirq => 5)
port map(rstn, clkm, apbi, apbo(5), kbdi, kbdo);
end generate;
nokbd : if CFG_KBD_ENABLE = 0 generate
apbo(4) <= apb_none; mouo <= ps2o_none;
apbo(5) <= apb_none; kbdo <= ps2o_none;
end generate;
kbdclk_pad : iopad generic map (tech => padtech)
port map (kbd_clk, kbdo.ps2_clk_o, kbdo.ps2_clk_oe, kbdi.ps2_clk_i);
kbdata_pad : iopad generic map (tech => padtech)
port map (kbd_data, kbdo.ps2_data_o, kbdo.ps2_data_oe, kbdi.ps2_data_i);
mouclk_pad : iopad generic map (tech => padtech)
port map (mou_clk, mouo.ps2_clk_o, mouo.ps2_clk_oe, moui.ps2_clk_i);
mouata_pad : iopad generic map (tech => padtech)
port map (mou_data, mouo.ps2_data_o, mouo.ps2_data_oe, moui.ps2_data_i);
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map (pindex => 10, paddr => 10, imask => CFG_GRGPIO_IMASK, nbits => 32)
port map (rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(10),
gpioi => gpioi, gpioo => gpioo);
-- Map GPIO bits 0 to 5 to LEDS 0 to 5.
gpio_led_pads : outpadv
generic map (tech => padtech, width => 6)
port map (led(5 downto 0), gpioo.dout(5 downto 0));
-- Map GPIO bits 8 to 13 to SWITCHES 0 to 5.
gpio_sw_pads : inpadv
generic map (tech => padtech, width => 6)
port map (switch(5 downto 0), gpioi.din(13 downto 8));
-- Map GPIO bits 16 to 20 to BUTTONS 0 to 4.
gpio_button_pads : inpadv
generic map (tech => padtech, width => 5)
port map (button(4 downto 0), gpioi.din(20 downto 16));
-- Map GPIO bits 24 to 31 to PMODA port.
gpio_pmod_pads : for i in 0 to 7 generate
gpio_pmod_padi : iopad
generic map (tech => padtech)
port map (pmoda(i), gpioo.dout(24+i), gpioo.oen(24+i), gpioi.din(24+i));
end generate;
gpioi.din(7 downto 0) <= (others => '0');
gpioi.din(15 downto 14) <= (others => '0');
gpioi.din(23 downto 21) <= (others => '0');
end generate;
ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
stati <= ahbstat_in_none;
ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 7,
nftslv => CFG_AHBSTATN)
port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15));
end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm
generic map (
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
pindex => 14, paddr => 14, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, rmii => 0, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF, phyrstadr => 7,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, enable_mdint => 1,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL,
giga => 0)
port map (
rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG),
apbi => apbi, apbo => apbo(14), ethi => ethi, etho => etho);
etxc_pad : clkpad generic map (tech => padtech)
port map (etx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech)
port map (erx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 8)
port map (erxd, ethi.rxd(7 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (erx_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (erx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (erx_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (erx_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 8)
port map (etxd, etho.txd(7 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map (etx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (etx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (emdc, etho.mdc);
emdio_pad : iopad generic map (tech => padtech)
port map (emdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
emdint_pad : inpad generic map (tech => padtech)
port map (emdint, ethi.mdint);
end generate;
eth_nopads : if (CFG_GRETH /= 1) generate -- eth pads
etxd_nopad : outpadv generic map (tech => padtech, width => 8)
port map (etxd, "00000000");
etxen_nopad : outpad generic map (tech => padtech)
port map (etx_en, '0');
etxer_nopad : outpad generic map (tech => padtech)
port map (etx_er, '0');
emdc_nopad : outpad generic map (tech => padtech)
port map (emdc, '0');
emdio_nopad : iopad generic map (tech => padtech)
port map (emdio, '0', '1', open);
end generate;
erst_pad : outpad generic map (tech => padtech)
port map (erst, rstraw);
egtxclk_pad : outpad generic map (tech => padtech)
port map (egtxclk, '0');
ethi.gtx_clk <= '0';
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP )
port map (rstn, clkm, ahbsi, ahbso(6));
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ)
port map ( rstn, clkm, ahbsi, ahbso(7));
end generate;
-----------------------------------------------------------------------
--- VGA / HDMI ------------------------------------------------------
-----------------------------------------------------------------------
vga : if CFG_VGA_ENABLE /= 0 generate
vga0 : apbvga
generic map(memtech => memtech, pindex => 6, paddr => 6)
port map(rstn, clkm, video_clk, apbi, apbo(6), vgao);
video_clksel <= "00"; -- fixed 25 MHz
end generate;
svga : if CFG_SVGA_ENABLE /= 0 generate
svga0 : svgactrl
generic map(memtech => memtech, pindex => 6, paddr => 6,
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH,
clk0 => 40000, clk1 => 25000, clk2 => 40000, clk3 => 25000,
burstlen => 6)
port map(rstn, clkm, video_clk, apbi, apbo(6), vgao,
ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH),
video_clksel);
end generate;
tmds : if CFG_VGA_ENABLE /= 0 or CFG_SVGA_ENABLE /= 0 generate
vgaclk0 : entity work.vga_clkgen
port map (resetn => rstraw, clk100 => lclk, sel => video_clksel,
vgaclk => video_clk, fastclk => video_fastclk);
tmds0 : entity work.vga2tmds
generic map (tech => fabtech)
port map (vgaclk => video_clk, fastclk => video_fastclk, vgao => vgao,
tmdsclk => tmds_clk, tmdsdat => tmds_dat );
tmdsc_pad : OBUFDS
port map (O => tmdstx_clk_p, OB => tmdstx_clk_n, I => tmds_clk);
tmdsd_pad : for i in 0 to 2 generate
tmdsdi_pad : OBUFDS
port map (O => tmdstx_dat_p(i), OB => tmdstx_dat_n(i), I => tmds_dat(i));
end generate;
end generate;
novga : if (CFG_VGA_ENABLE = 0 and CFG_SVGA_ENABLE = 0) generate
apbo(6) <= apb_none; vgao <= vgao_none;
tmdsc_pad : OBUFDS
port map (O => tmdstx_clk_p, OB => tmdstx_clk_n, I => gnd);
tmdsd_pad : for i in 0 to 2 generate
tmdsdi_pad : OBUFDS
port map (O => tmdstx_dat_p(i), OB => tmdstx_dat_n(i), I => gnd);
end generate;
end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Digilent-Atlys-XC6SLX45 Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end architecture;
| gpl-3.0 | 44ad738605a8f1e6592382fdc1cc26ee | 0.552406 | 3.593806 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-xilinx-sp605/config.vhd | 1 | 7,955 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := spartan6;
constant CFG_MEMTECH : integer := spartan6;
constant CFG_PADTECH : integer := spartan6;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := spartan6;
constant CFG_CLKMUL : integer := (5);
constant CFG_CLKDIV : integer := (3);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 1;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 2;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 2;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0 + 1*2 + 4*1;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 4 + 64*0;
constant CFG_ATBSZ : integer := 4;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_STAT_ENABLE : integer := 0;
constant CFG_STAT_CNT : integer := 1;
constant CFG_STAT_NMAX : integer := 0;
constant CFG_STAT_DSUEN : integer := 0;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
constant CFG_ALTWIN : integer := 0;
constant CFG_REX : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020605#;
constant CFG_ETH_ENL : integer := 16#000987#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 1;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- Xilinx MIG
constant CFG_MIG_DDR2 : integer := 1;
constant CFG_MIG_RANKS : integer := (1);
constant CFG_MIG_COLBITS : integer := (10);
constant CFG_MIG_ROWBITS : integer := (13);
constant CFG_MIG_BANKBITS: integer := (2);
constant CFG_MIG_HMASK : integer := 16#F00#;
-- AHB status register
constant CFG_AHBSTAT : integer := 1;
constant CFG_AHBSTATN : integer := (1);
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 32;
constant CFG_GRETH_FT : integer := 0;
constant CFG_GRETH_EDCLFT : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := (8);
-- VGA and PS2/ interface
constant CFG_KBD_ENABLE : integer := 0;
constant CFG_VGA_ENABLE : integer := 0;
constant CFG_SVGA_ENABLE : integer := 1;
-- SPI memory controller
constant CFG_SPIMCTRL : integer := 0;
constant CFG_SPIMCTRL_SDCARD : integer := 0;
constant CFG_SPIMCTRL_READCMD : integer := 16#0#;
constant CFG_SPIMCTRL_DUMMYBYTE : integer := 0;
constant CFG_SPIMCTRL_DUALOUTPUT : integer := 0;
constant CFG_SPIMCTRL_SCALER : integer := 1;
constant CFG_SPIMCTRL_ASCALER : integer := 1;
constant CFG_SPIMCTRL_PWRUPCNT : integer := 0;
constant CFG_SPIMCTRL_OFFSET : integer := 16#0#;
-- SPI controller
constant CFG_SPICTRL_ENABLE : integer := 0;
constant CFG_SPICTRL_NUM : integer := 1;
constant CFG_SPICTRL_SLVS : integer := 1;
constant CFG_SPICTRL_FIFO : integer := 1;
constant CFG_SPICTRL_SLVREG : integer := 0;
constant CFG_SPICTRL_ODMODE : integer := 0;
constant CFG_SPICTRL_AM : integer := 0;
constant CFG_SPICTRL_ASEL : integer := 0;
constant CFG_SPICTRL_TWEN : integer := 0;
constant CFG_SPICTRL_MAXWLEN : integer := 0;
constant CFG_SPICTRL_SYNCRAM : integer := 0;
constant CFG_SPICTRL_FT : integer := 0;
-- AMBA System ACE Interface Controller
constant CFG_GRACECTRL : integer := 1;
-- PCIEXP interface
constant CFG_PCIEXP : integer := 0;
constant CFG_PCIE_TYPE : integer := 0;
constant CFG_PCIE_SIM_MAS : integer := 0;
constant CFG_PCIEXPVID : integer := 16#0#;
constant CFG_PCIEXPDID : integer := 16#0#;
constant CFG_NO_OF_LANES : integer := 1;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-3.0 | 96d295c82a544d01714271ee36142705 | 0.653048 | 3.624146 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/techmap/maps/grfpw_net.vhd | 1 | 36,532 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: grfpw_net
-- File: grfpw_net.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: GRFPU / GRLFPC netlist wrapper
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.gencomp.all;
entity grfpw_net is
generic (tech : integer := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer range 0 to 2 := 1;
disas : integer range 0 to 2 := 0;
pipe : integer range 0 to 2 := 0
);
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi_flush : in std_ulogic; -- pipeline flush
cpi_exack : in std_ulogic; -- FP exception acknowledge
cpi_a_rs1 : in std_logic_vector(4 downto 0);
cpi_d_pc : in std_logic_vector(31 downto 0);
cpi_d_inst : in std_logic_vector(31 downto 0);
cpi_d_cnt : in std_logic_vector(1 downto 0);
cpi_d_trap : in std_ulogic;
cpi_d_annul : in std_ulogic;
cpi_d_pv : in std_ulogic;
cpi_a_pc : in std_logic_vector(31 downto 0);
cpi_a_inst : in std_logic_vector(31 downto 0);
cpi_a_cnt : in std_logic_vector(1 downto 0);
cpi_a_trap : in std_ulogic;
cpi_a_annul : in std_ulogic;
cpi_a_pv : in std_ulogic;
cpi_e_pc : in std_logic_vector(31 downto 0);
cpi_e_inst : in std_logic_vector(31 downto 0);
cpi_e_cnt : in std_logic_vector(1 downto 0);
cpi_e_trap : in std_ulogic;
cpi_e_annul : in std_ulogic;
cpi_e_pv : in std_ulogic;
cpi_m_pc : in std_logic_vector(31 downto 0);
cpi_m_inst : in std_logic_vector(31 downto 0);
cpi_m_cnt : in std_logic_vector(1 downto 0);
cpi_m_trap : in std_ulogic;
cpi_m_annul : in std_ulogic;
cpi_m_pv : in std_ulogic;
cpi_x_pc : in std_logic_vector(31 downto 0);
cpi_x_inst : in std_logic_vector(31 downto 0);
cpi_x_cnt : in std_logic_vector(1 downto 0);
cpi_x_trap : in std_ulogic;
cpi_x_annul : in std_ulogic;
cpi_x_pv : in std_ulogic;
cpi_lddata : in std_logic_vector(31 downto 0); -- load data
cpi_dbg_enable : in std_ulogic;
cpi_dbg_write : in std_ulogic;
cpi_dbg_fsr : in std_ulogic; -- FSR access
cpi_dbg_addr : in std_logic_vector(4 downto 0);
cpi_dbg_data : in std_logic_vector(31 downto 0);
cpo_data : out std_logic_vector(31 downto 0); -- store data
cpo_exc : out std_logic; -- FP exception
cpo_cc : out std_logic_vector(1 downto 0); -- FP condition codes
cpo_ccv : out std_ulogic; -- FP condition codes valid
cpo_ldlock : out std_logic; -- FP pipeline hold
cpo_holdn : out std_ulogic;
cpo_dbg_data : out std_logic_vector(31 downto 0);
rfi1_rd1addr : out std_logic_vector(3 downto 0);
rfi1_rd2addr : out std_logic_vector(3 downto 0);
rfi1_wraddr : out std_logic_vector(3 downto 0);
rfi1_wrdata : out std_logic_vector(31 downto 0);
rfi1_ren1 : out std_ulogic;
rfi1_ren2 : out std_ulogic;
rfi1_wren : out std_ulogic;
rfi2_rd1addr : out std_logic_vector(3 downto 0);
rfi2_rd2addr : out std_logic_vector(3 downto 0);
rfi2_wraddr : out std_logic_vector(3 downto 0);
rfi2_wrdata : out std_logic_vector(31 downto 0);
rfi2_ren1 : out std_ulogic;
rfi2_ren2 : out std_ulogic;
rfi2_wren : out std_ulogic;
rfo1_data1 : in std_logic_vector(31 downto 0);
rfo1_data2 : in std_logic_vector(31 downto 0);
rfo2_data1 : in std_logic_vector(31 downto 0);
rfo2_data2 : in std_logic_vector(31 downto 0)
);
end;
architecture rtl of grfpw_net is
component grfpw_0_unisim
port(
rst : in std_logic;
clk : in std_logic;
holdn : in std_logic;
cpi_flush : in std_logic;
cpi_exack : in std_logic;
cpi_a_rs1 : in std_logic_vector (4 downto 0);
cpi_d_pc : in std_logic_vector (31 downto 0);
cpi_d_inst : in std_logic_vector (31 downto 0);
cpi_d_cnt : in std_logic_vector (1 downto 0);
cpi_d_trap : in std_logic;
cpi_d_annul : in std_logic;
cpi_d_pv : in std_logic;
cpi_a_pc : in std_logic_vector (31 downto 0);
cpi_a_inst : in std_logic_vector (31 downto 0);
cpi_a_cnt : in std_logic_vector (1 downto 0);
cpi_a_trap : in std_logic;
cpi_a_annul : in std_logic;
cpi_a_pv : in std_logic;
cpi_e_pc : in std_logic_vector (31 downto 0);
cpi_e_inst : in std_logic_vector (31 downto 0);
cpi_e_cnt : in std_logic_vector (1 downto 0);
cpi_e_trap : in std_logic;
cpi_e_annul : in std_logic;
cpi_e_pv : in std_logic;
cpi_m_pc : in std_logic_vector (31 downto 0);
cpi_m_inst : in std_logic_vector (31 downto 0);
cpi_m_cnt : in std_logic_vector (1 downto 0);
cpi_m_trap : in std_logic;
cpi_m_annul : in std_logic;
cpi_m_pv : in std_logic;
cpi_x_pc : in std_logic_vector (31 downto 0);
cpi_x_inst : in std_logic_vector (31 downto 0);
cpi_x_cnt : in std_logic_vector (1 downto 0);
cpi_x_trap : in std_logic;
cpi_x_annul : in std_logic;
cpi_x_pv : in std_logic;
cpi_lddata : in std_logic_vector (31 downto 0);
cpi_dbg_enable : in std_logic;
cpi_dbg_write : in std_logic;
cpi_dbg_fsr : in std_logic;
cpi_dbg_addr : in std_logic_vector (4 downto 0);
cpi_dbg_data : in std_logic_vector (31 downto 0);
cpo_data : out std_logic_vector (31 downto 0);
cpo_exc : out std_logic;
cpo_cc : out std_logic_vector (1 downto 0);
cpo_ccv : out std_logic;
cpo_ldlock : out std_logic;
cpo_holdn : out std_logic;
cpo_dbg_data : out std_logic_vector (31 downto 0);
rfi1_rd1addr : out std_logic_vector (3 downto 0);
rfi1_rd2addr : out std_logic_vector (3 downto 0);
rfi1_wraddr : out std_logic_vector (3 downto 0);
rfi1_wrdata : out std_logic_vector (31 downto 0);
rfi1_ren1 : out std_logic;
rfi1_ren2 : out std_logic;
rfi1_wren : out std_logic;
rfi2_rd1addr : out std_logic_vector (3 downto 0);
rfi2_rd2addr : out std_logic_vector (3 downto 0);
rfi2_wraddr : out std_logic_vector (3 downto 0);
rfi2_wrdata : out std_logic_vector (31 downto 0);
rfi2_ren1 : out std_logic;
rfi2_ren2 : out std_logic;
rfi2_wren : out std_logic;
rfo1_data1 : in std_logic_vector (31 downto 0);
rfo1_data2 : in std_logic_vector (31 downto 0);
rfo2_data1 : in std_logic_vector (31 downto 0);
rfo2_data2 : in std_logic_vector (31 downto 0));
-- disasen : in std_logic);
end component;
component grfpw_0_altera
port(
rst : in std_logic;
clk : in std_logic;
holdn : in std_logic;
cpi_flush : in std_logic;
cpi_exack : in std_logic;
cpi_a_rs1 : in std_logic_vector (4 downto 0);
cpi_d_pc : in std_logic_vector (31 downto 0);
cpi_d_inst : in std_logic_vector (31 downto 0);
cpi_d_cnt : in std_logic_vector (1 downto 0);
cpi_d_trap : in std_logic;
cpi_d_annul : in std_logic;
cpi_d_pv : in std_logic;
cpi_a_pc : in std_logic_vector (31 downto 0);
cpi_a_inst : in std_logic_vector (31 downto 0);
cpi_a_cnt : in std_logic_vector (1 downto 0);
cpi_a_trap : in std_logic;
cpi_a_annul : in std_logic;
cpi_a_pv : in std_logic;
cpi_e_pc : in std_logic_vector (31 downto 0);
cpi_e_inst : in std_logic_vector (31 downto 0);
cpi_e_cnt : in std_logic_vector (1 downto 0);
cpi_e_trap : in std_logic;
cpi_e_annul : in std_logic;
cpi_e_pv : in std_logic;
cpi_m_pc : in std_logic_vector (31 downto 0);
cpi_m_inst : in std_logic_vector (31 downto 0);
cpi_m_cnt : in std_logic_vector (1 downto 0);
cpi_m_trap : in std_logic;
cpi_m_annul : in std_logic;
cpi_m_pv : in std_logic;
cpi_x_pc : in std_logic_vector (31 downto 0);
cpi_x_inst : in std_logic_vector (31 downto 0);
cpi_x_cnt : in std_logic_vector (1 downto 0);
cpi_x_trap : in std_logic;
cpi_x_annul : in std_logic;
cpi_x_pv : in std_logic;
cpi_lddata : in std_logic_vector (31 downto 0);
cpi_dbg_enable : in std_logic;
cpi_dbg_write : in std_logic;
cpi_dbg_fsr : in std_logic;
cpi_dbg_addr : in std_logic_vector (4 downto 0);
cpi_dbg_data : in std_logic_vector (31 downto 0);
cpo_data : out std_logic_vector (31 downto 0);
cpo_exc : out std_logic;
cpo_cc : out std_logic_vector (1 downto 0);
cpo_ccv : out std_logic;
cpo_ldlock : out std_logic;
cpo_holdn : out std_logic;
cpo_dbg_data : out std_logic_vector (31 downto 0);
rfi1_rd1addr : out std_logic_vector (3 downto 0);
rfi1_rd2addr : out std_logic_vector (3 downto 0);
rfi1_wraddr : out std_logic_vector (3 downto 0);
rfi1_wrdata : out std_logic_vector (31 downto 0);
rfi1_ren1 : out std_logic;
rfi1_ren2 : out std_logic;
rfi1_wren : out std_logic;
rfi2_rd1addr : out std_logic_vector (3 downto 0);
rfi2_rd2addr : out std_logic_vector (3 downto 0);
rfi2_wraddr : out std_logic_vector (3 downto 0);
rfi2_wrdata : out std_logic_vector (31 downto 0);
rfi2_ren1 : out std_logic;
rfi2_ren2 : out std_logic;
rfi2_wren : out std_logic;
rfo1_data1 : in std_logic_vector (31 downto 0);
rfo1_data2 : in std_logic_vector (31 downto 0);
rfo2_data1 : in std_logic_vector (31 downto 0);
rfo2_data2 : in std_logic_vector (31 downto 0));
end component;
component grfpw_0_stratixii
port(
rst : in std_logic;
clk : in std_logic;
holdn : in std_logic;
cpi_flush : in std_logic;
cpi_exack : in std_logic;
cpi_a_rs1 : in std_logic_vector (4 downto 0);
cpi_d_pc : in std_logic_vector (31 downto 0);
cpi_d_inst : in std_logic_vector (31 downto 0);
cpi_d_cnt : in std_logic_vector (1 downto 0);
cpi_d_trap : in std_logic;
cpi_d_annul : in std_logic;
cpi_d_pv : in std_logic;
cpi_a_pc : in std_logic_vector (31 downto 0);
cpi_a_inst : in std_logic_vector (31 downto 0);
cpi_a_cnt : in std_logic_vector (1 downto 0);
cpi_a_trap : in std_logic;
cpi_a_annul : in std_logic;
cpi_a_pv : in std_logic;
cpi_e_pc : in std_logic_vector (31 downto 0);
cpi_e_inst : in std_logic_vector (31 downto 0);
cpi_e_cnt : in std_logic_vector (1 downto 0);
cpi_e_trap : in std_logic;
cpi_e_annul : in std_logic;
cpi_e_pv : in std_logic;
cpi_m_pc : in std_logic_vector (31 downto 0);
cpi_m_inst : in std_logic_vector (31 downto 0);
cpi_m_cnt : in std_logic_vector (1 downto 0);
cpi_m_trap : in std_logic;
cpi_m_annul : in std_logic;
cpi_m_pv : in std_logic;
cpi_x_pc : in std_logic_vector (31 downto 0);
cpi_x_inst : in std_logic_vector (31 downto 0);
cpi_x_cnt : in std_logic_vector (1 downto 0);
cpi_x_trap : in std_logic;
cpi_x_annul : in std_logic;
cpi_x_pv : in std_logic;
cpi_lddata : in std_logic_vector (31 downto 0);
cpi_dbg_enable : in std_logic;
cpi_dbg_write : in std_logic;
cpi_dbg_fsr : in std_logic;
cpi_dbg_addr : in std_logic_vector (4 downto 0);
cpi_dbg_data : in std_logic_vector (31 downto 0);
cpo_data : out std_logic_vector (31 downto 0);
cpo_exc : out std_logic;
cpo_cc : out std_logic_vector (1 downto 0);
cpo_ccv : out std_logic;
cpo_ldlock : out std_logic;
cpo_holdn : out std_logic;
cpo_dbg_data : out std_logic_vector (31 downto 0);
rfi1_rd1addr : out std_logic_vector (3 downto 0);
rfi1_rd2addr : out std_logic_vector (3 downto 0);
rfi1_wraddr : out std_logic_vector (3 downto 0);
rfi1_wrdata : out std_logic_vector (31 downto 0);
rfi1_ren1 : out std_logic;
rfi1_ren2 : out std_logic;
rfi1_wren : out std_logic;
rfi2_rd1addr : out std_logic_vector (3 downto 0);
rfi2_rd2addr : out std_logic_vector (3 downto 0);
rfi2_wraddr : out std_logic_vector (3 downto 0);
rfi2_wrdata : out std_logic_vector (31 downto 0);
rfi2_ren1 : out std_logic;
rfi2_ren2 : out std_logic;
rfi2_wren : out std_logic;
rfo1_data1 : in std_logic_vector (31 downto 0);
rfo1_data2 : in std_logic_vector (31 downto 0);
rfo2_data1 : in std_logic_vector (31 downto 0);
rfo2_data2 : in std_logic_vector (31 downto 0));
end component;
component grfpw_0_cycloneiii
port(
rst : in std_logic;
clk : in std_logic;
holdn : in std_logic;
cpi_flush : in std_logic;
cpi_exack : in std_logic;
cpi_a_rs1 : in std_logic_vector (4 downto 0);
cpi_d_pc : in std_logic_vector (31 downto 0);
cpi_d_inst : in std_logic_vector (31 downto 0);
cpi_d_cnt : in std_logic_vector (1 downto 0);
cpi_d_trap : in std_logic;
cpi_d_annul : in std_logic;
cpi_d_pv : in std_logic;
cpi_a_pc : in std_logic_vector (31 downto 0);
cpi_a_inst : in std_logic_vector (31 downto 0);
cpi_a_cnt : in std_logic_vector (1 downto 0);
cpi_a_trap : in std_logic;
cpi_a_annul : in std_logic;
cpi_a_pv : in std_logic;
cpi_e_pc : in std_logic_vector (31 downto 0);
cpi_e_inst : in std_logic_vector (31 downto 0);
cpi_e_cnt : in std_logic_vector (1 downto 0);
cpi_e_trap : in std_logic;
cpi_e_annul : in std_logic;
cpi_e_pv : in std_logic;
cpi_m_pc : in std_logic_vector (31 downto 0);
cpi_m_inst : in std_logic_vector (31 downto 0);
cpi_m_cnt : in std_logic_vector (1 downto 0);
cpi_m_trap : in std_logic;
cpi_m_annul : in std_logic;
cpi_m_pv : in std_logic;
cpi_x_pc : in std_logic_vector (31 downto 0);
cpi_x_inst : in std_logic_vector (31 downto 0);
cpi_x_cnt : in std_logic_vector (1 downto 0);
cpi_x_trap : in std_logic;
cpi_x_annul : in std_logic;
cpi_x_pv : in std_logic;
cpi_lddata : in std_logic_vector (31 downto 0);
cpi_dbg_enable : in std_logic;
cpi_dbg_write : in std_logic;
cpi_dbg_fsr : in std_logic;
cpi_dbg_addr : in std_logic_vector (4 downto 0);
cpi_dbg_data : in std_logic_vector (31 downto 0);
cpo_data : out std_logic_vector (31 downto 0);
cpo_exc : out std_logic;
cpo_cc : out std_logic_vector (1 downto 0);
cpo_ccv : out std_logic;
cpo_ldlock : out std_logic;
cpo_holdn : out std_logic;
cpo_dbg_data : out std_logic_vector (31 downto 0);
rfi1_rd1addr : out std_logic_vector (3 downto 0);
rfi1_rd2addr : out std_logic_vector (3 downto 0);
rfi1_wraddr : out std_logic_vector (3 downto 0);
rfi1_wrdata : out std_logic_vector (31 downto 0);
rfi1_ren1 : out std_logic;
rfi1_ren2 : out std_logic;
rfi1_wren : out std_logic;
rfi2_rd1addr : out std_logic_vector (3 downto 0);
rfi2_rd2addr : out std_logic_vector (3 downto 0);
rfi2_wraddr : out std_logic_vector (3 downto 0);
rfi2_wrdata : out std_logic_vector (31 downto 0);
rfi2_ren1 : out std_logic;
rfi2_ren2 : out std_logic;
rfi2_wren : out std_logic;
rfo1_data1 : in std_logic_vector (31 downto 0);
rfo1_data2 : in std_logic_vector (31 downto 0);
rfo2_data1 : in std_logic_vector (31 downto 0);
rfo2_data2 : in std_logic_vector (31 downto 0));
end component;
component grfpw_0_stratixiii
port(
rst : in std_logic;
clk : in std_logic;
holdn : in std_logic;
cpi_flush : in std_logic;
cpi_exack : in std_logic;
cpi_a_rs1 : in std_logic_vector (4 downto 0);
cpi_d_pc : in std_logic_vector (31 downto 0);
cpi_d_inst : in std_logic_vector (31 downto 0);
cpi_d_cnt : in std_logic_vector (1 downto 0);
cpi_d_trap : in std_logic;
cpi_d_annul : in std_logic;
cpi_d_pv : in std_logic;
cpi_a_pc : in std_logic_vector (31 downto 0);
cpi_a_inst : in std_logic_vector (31 downto 0);
cpi_a_cnt : in std_logic_vector (1 downto 0);
cpi_a_trap : in std_logic;
cpi_a_annul : in std_logic;
cpi_a_pv : in std_logic;
cpi_e_pc : in std_logic_vector (31 downto 0);
cpi_e_inst : in std_logic_vector (31 downto 0);
cpi_e_cnt : in std_logic_vector (1 downto 0);
cpi_e_trap : in std_logic;
cpi_e_annul : in std_logic;
cpi_e_pv : in std_logic;
cpi_m_pc : in std_logic_vector (31 downto 0);
cpi_m_inst : in std_logic_vector (31 downto 0);
cpi_m_cnt : in std_logic_vector (1 downto 0);
cpi_m_trap : in std_logic;
cpi_m_annul : in std_logic;
cpi_m_pv : in std_logic;
cpi_x_pc : in std_logic_vector (31 downto 0);
cpi_x_inst : in std_logic_vector (31 downto 0);
cpi_x_cnt : in std_logic_vector (1 downto 0);
cpi_x_trap : in std_logic;
cpi_x_annul : in std_logic;
cpi_x_pv : in std_logic;
cpi_lddata : in std_logic_vector (31 downto 0);
cpi_dbg_enable : in std_logic;
cpi_dbg_write : in std_logic;
cpi_dbg_fsr : in std_logic;
cpi_dbg_addr : in std_logic_vector (4 downto 0);
cpi_dbg_data : in std_logic_vector (31 downto 0);
cpo_data : out std_logic_vector (31 downto 0);
cpo_exc : out std_logic;
cpo_cc : out std_logic_vector (1 downto 0);
cpo_ccv : out std_logic;
cpo_ldlock : out std_logic;
cpo_holdn : out std_logic;
cpo_dbg_data : out std_logic_vector (31 downto 0);
rfi1_rd1addr : out std_logic_vector (3 downto 0);
rfi1_rd2addr : out std_logic_vector (3 downto 0);
rfi1_wraddr : out std_logic_vector (3 downto 0);
rfi1_wrdata : out std_logic_vector (31 downto 0);
rfi1_ren1 : out std_logic;
rfi1_ren2 : out std_logic;
rfi1_wren : out std_logic;
rfi2_rd1addr : out std_logic_vector (3 downto 0);
rfi2_rd2addr : out std_logic_vector (3 downto 0);
rfi2_wraddr : out std_logic_vector (3 downto 0);
rfi2_wrdata : out std_logic_vector (31 downto 0);
rfi2_ren1 : out std_logic;
rfi2_ren2 : out std_logic;
rfi2_wren : out std_logic;
rfo1_data1 : in std_logic_vector (31 downto 0);
rfo1_data2 : in std_logic_vector (31 downto 0);
rfo2_data1 : in std_logic_vector (31 downto 0);
rfo2_data2 : in std_logic_vector (31 downto 0));
end component;
component grfpw_tsmc90
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi_flush : in std_ulogic; -- pipeline flush
cpi_exack : in std_ulogic; -- FP exception acknowledge
cpi_a_rs1 : in std_logic_vector(4 downto 0);
cpi_d_pc : in std_logic_vector(31 downto 0);
cpi_d_inst : in std_logic_vector(31 downto 0);
cpi_d_cnt : in std_logic_vector(1 downto 0);
cpi_d_trap : in std_ulogic;
cpi_d_annul : in std_ulogic;
cpi_d_pv : in std_ulogic;
cpi_a_pc : in std_logic_vector(31 downto 0);
cpi_a_inst : in std_logic_vector(31 downto 0);
cpi_a_cnt : in std_logic_vector(1 downto 0);
cpi_a_trap : in std_ulogic;
cpi_a_annul : in std_ulogic;
cpi_a_pv : in std_ulogic;
cpi_e_pc : in std_logic_vector(31 downto 0);
cpi_e_inst : in std_logic_vector(31 downto 0);
cpi_e_cnt : in std_logic_vector(1 downto 0);
cpi_e_trap : in std_ulogic;
cpi_e_annul : in std_ulogic;
cpi_e_pv : in std_ulogic;
cpi_m_pc : in std_logic_vector(31 downto 0);
cpi_m_inst : in std_logic_vector(31 downto 0);
cpi_m_cnt : in std_logic_vector(1 downto 0);
cpi_m_trap : in std_ulogic;
cpi_m_annul : in std_ulogic;
cpi_m_pv : in std_ulogic;
cpi_x_pc : in std_logic_vector(31 downto 0);
cpi_x_inst : in std_logic_vector(31 downto 0);
cpi_x_cnt : in std_logic_vector(1 downto 0);
cpi_x_trap : in std_ulogic;
cpi_x_annul : in std_ulogic;
cpi_x_pv : in std_ulogic;
cpi_lddata : in std_logic_vector(31 downto 0); -- load data
cpi_dbg_enable : in std_ulogic;
cpi_dbg_write : in std_ulogic;
cpi_dbg_fsr : in std_ulogic; -- FSR access
cpi_dbg_addr : in std_logic_vector(4 downto 0);
cpi_dbg_data : in std_logic_vector(31 downto 0);
cpo_data : out std_logic_vector(31 downto 0); -- store data
cpo_exc : out std_logic; -- FP exception
cpo_cc : out std_logic_vector(1 downto 0); -- FP condition codes
cpo_ccv : out std_ulogic; -- FP condition codes valid
cpo_ldlock : out std_logic; -- FP pipeline hold
cpo_holdn : out std_ulogic;
--cpo_restart : out std_ulogic;
cpo_dbg_data : out std_logic_vector(31 downto 0);
rfi1_rd1addr : out std_logic_vector(3 downto 0);
rfi1_rd2addr : out std_logic_vector(3 downto 0);
rfi1_wraddr : out std_logic_vector(3 downto 0);
rfi1_wrdata : out std_logic_vector(31 downto 0);
rfi1_ren1 : out std_ulogic;
rfi1_ren2 : out std_ulogic;
rfi1_wren : out std_ulogic;
rfi2_rd1addr : out std_logic_vector(3 downto 0);
rfi2_rd2addr : out std_logic_vector(3 downto 0);
rfi2_wraddr : out std_logic_vector(3 downto 0);
rfi2_wrdata : out std_logic_vector(31 downto 0);
rfi2_ren1 : out std_ulogic;
rfi2_ren2 : out std_ulogic;
rfi2_wren : out std_ulogic;
rfo1_data1 : in std_logic_vector(31 downto 0);
rfo1_data2 : in std_logic_vector(31 downto 0);
rfo2_data1 : in std_logic_vector(31 downto 0);
rfo2_data2 : in std_logic_vector(31 downto 0)
);
end component;
component grfpw_tm65gplus
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi_flush : in std_ulogic; -- pipeline flush
cpi_exack : in std_ulogic; -- FP exception acknowledge
cpi_a_rs1 : in std_logic_vector(4 downto 0);
cpi_d_pc : in std_logic_vector(31 downto 0);
cpi_d_inst : in std_logic_vector(31 downto 0);
cpi_d_cnt : in std_logic_vector(1 downto 0);
cpi_d_trap : in std_ulogic;
cpi_d_annul : in std_ulogic;
cpi_d_pv : in std_ulogic;
cpi_a_pc : in std_logic_vector(31 downto 0);
cpi_a_inst : in std_logic_vector(31 downto 0);
cpi_a_cnt : in std_logic_vector(1 downto 0);
cpi_a_trap : in std_ulogic;
cpi_a_annul : in std_ulogic;
cpi_a_pv : in std_ulogic;
cpi_e_pc : in std_logic_vector(31 downto 0);
cpi_e_inst : in std_logic_vector(31 downto 0);
cpi_e_cnt : in std_logic_vector(1 downto 0);
cpi_e_trap : in std_ulogic;
cpi_e_annul : in std_ulogic;
cpi_e_pv : in std_ulogic;
cpi_m_pc : in std_logic_vector(31 downto 0);
cpi_m_inst : in std_logic_vector(31 downto 0);
cpi_m_cnt : in std_logic_vector(1 downto 0);
cpi_m_trap : in std_ulogic;
cpi_m_annul : in std_ulogic;
cpi_m_pv : in std_ulogic;
cpi_x_pc : in std_logic_vector(31 downto 0);
cpi_x_inst : in std_logic_vector(31 downto 0);
cpi_x_cnt : in std_logic_vector(1 downto 0);
cpi_x_trap : in std_ulogic;
cpi_x_annul : in std_ulogic;
cpi_x_pv : in std_ulogic;
cpi_lddata : in std_logic_vector(31 downto 0); -- load data
cpi_dbg_enable : in std_ulogic;
cpi_dbg_write : in std_ulogic;
cpi_dbg_fsr : in std_ulogic; -- FSR access
cpi_dbg_addr : in std_logic_vector(4 downto 0);
cpi_dbg_data : in std_logic_vector(31 downto 0);
cpo_data : out std_logic_vector(31 downto 0); -- store data
cpo_exc : out std_logic; -- FP exception
cpo_cc : out std_logic_vector(1 downto 0); -- FP condition codes
cpo_ccv : out std_ulogic; -- FP condition codes valid
cpo_ldlock : out std_logic; -- FP pipeline hold
cpo_holdn : out std_ulogic;
--cpo_restart : out std_ulogic;
cpo_dbg_data : out std_logic_vector(31 downto 0);
rfi1_rd1addr : out std_logic_vector(3 downto 0);
rfi1_rd2addr : out std_logic_vector(3 downto 0);
rfi1_wraddr : out std_logic_vector(3 downto 0);
rfi1_wrdata : out std_logic_vector(31 downto 0);
rfi1_ren1 : out std_ulogic;
rfi1_ren2 : out std_ulogic;
rfi1_wren : out std_ulogic;
rfi2_rd1addr : out std_logic_vector(3 downto 0);
rfi2_rd2addr : out std_logic_vector(3 downto 0);
rfi2_wraddr : out std_logic_vector(3 downto 0);
rfi2_wrdata : out std_logic_vector(31 downto 0);
rfi2_ren1 : out std_ulogic;
rfi2_ren2 : out std_ulogic;
rfi2_wren : out std_ulogic;
rfo1_data1 : in std_logic_vector(31 downto 0);
rfo1_data2 : in std_logic_vector(31 downto 0);
rfo2_data1 : in std_logic_vector(31 downto 0);
rfo2_data2 : in std_logic_vector(31 downto 0)
);
end component;
component grfpw_cust1
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi_flush : in std_ulogic; -- pipeline flush
cpi_exack : in std_ulogic; -- FP exception acknowledge
cpi_a_rs1 : in std_logic_vector(4 downto 0);
cpi_d_pc : in std_logic_vector(31 downto 0);
cpi_d_inst : in std_logic_vector(31 downto 0);
cpi_d_cnt : in std_logic_vector(1 downto 0);
cpi_d_trap : in std_ulogic;
cpi_d_annul : in std_ulogic;
cpi_d_pv : in std_ulogic;
cpi_a_pc : in std_logic_vector(31 downto 0);
cpi_a_inst : in std_logic_vector(31 downto 0);
cpi_a_cnt : in std_logic_vector(1 downto 0);
cpi_a_trap : in std_ulogic;
cpi_a_annul : in std_ulogic;
cpi_a_pv : in std_ulogic;
cpi_e_pc : in std_logic_vector(31 downto 0);
cpi_e_inst : in std_logic_vector(31 downto 0);
cpi_e_cnt : in std_logic_vector(1 downto 0);
cpi_e_trap : in std_ulogic;
cpi_e_annul : in std_ulogic;
cpi_e_pv : in std_ulogic;
cpi_m_pc : in std_logic_vector(31 downto 0);
cpi_m_inst : in std_logic_vector(31 downto 0);
cpi_m_cnt : in std_logic_vector(1 downto 0);
cpi_m_trap : in std_ulogic;
cpi_m_annul : in std_ulogic;
cpi_m_pv : in std_ulogic;
cpi_x_pc : in std_logic_vector(31 downto 0);
cpi_x_inst : in std_logic_vector(31 downto 0);
cpi_x_cnt : in std_logic_vector(1 downto 0);
cpi_x_trap : in std_ulogic;
cpi_x_annul : in std_ulogic;
cpi_x_pv : in std_ulogic;
cpi_lddata : in std_logic_vector(31 downto 0); -- load data
cpi_dbg_enable : in std_ulogic;
cpi_dbg_write : in std_ulogic;
cpi_dbg_fsr : in std_ulogic; -- FSR access
cpi_dbg_addr : in std_logic_vector(4 downto 0);
cpi_dbg_data : in std_logic_vector(31 downto 0);
cpo_data : out std_logic_vector(31 downto 0); -- store data
cpo_exc : out std_logic; -- FP exception
cpo_cc : out std_logic_vector(1 downto 0); -- FP condition codes
cpo_ccv : out std_ulogic; -- FP condition codes valid
cpo_ldlock : out std_logic; -- FP pipeline hold
cpo_holdn : out std_ulogic;
--cpo_restart : out std_ulogic;
cpo_dbg_data : out std_logic_vector(31 downto 0);
rfi1_rd1addr : out std_logic_vector(3 downto 0);
rfi1_rd2addr : out std_logic_vector(3 downto 0);
rfi1_wraddr : out std_logic_vector(3 downto 0);
rfi1_wrdata : out std_logic_vector(31 downto 0);
rfi1_ren1 : out std_ulogic;
rfi1_ren2 : out std_ulogic;
rfi1_wren : out std_ulogic;
rfi2_rd1addr : out std_logic_vector(3 downto 0);
rfi2_rd2addr : out std_logic_vector(3 downto 0);
rfi2_wraddr : out std_logic_vector(3 downto 0);
rfi2_wrdata : out std_logic_vector(31 downto 0);
rfi2_ren1 : out std_ulogic;
rfi2_ren2 : out std_ulogic;
rfi2_wren : out std_ulogic;
rfo1_data1 : in std_logic_vector(31 downto 0);
rfo1_data2 : in std_logic_vector(31 downto 0);
rfo2_data1 : in std_logic_vector(31 downto 0);
rfo2_data2 : in std_logic_vector(31 downto 0)
);
end component;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of u0_tsmc90 : label is TRUE;
attribute DONT_TOUCH of u0_tm65gplus : label is TRUE;
-- signal disasen : std_logic;
begin
-- disasen <= '1' when disas /= 0 else '0';
uni : if (is_unisim(tech) = 1) generate
grfpw0 : grfpw_0_unisim
port map (rst, clk, holdn, cpi_flush, cpi_exack, cpi_a_rs1, cpi_d_pc,
cpi_d_inst, cpi_d_cnt, cpi_d_trap, cpi_d_annul, cpi_d_pv, cpi_a_pc,
cpi_a_inst, cpi_a_cnt, cpi_a_trap, cpi_a_annul, cpi_a_pv, cpi_e_pc,
cpi_e_inst, cpi_e_cnt, cpi_e_trap, cpi_e_annul, cpi_e_pv, cpi_m_pc,
cpi_m_inst, cpi_m_cnt, cpi_m_trap, cpi_m_annul, cpi_m_pv, cpi_x_pc,
cpi_x_inst, cpi_x_cnt, cpi_x_trap, cpi_x_annul, cpi_x_pv, cpi_lddata,
cpi_dbg_enable, cpi_dbg_write, cpi_dbg_fsr, cpi_dbg_addr, cpi_dbg_data,
cpo_data, cpo_exc, cpo_cc, cpo_ccv, cpo_ldlock, cpo_holdn, cpo_dbg_data,
rfi1_rd1addr, rfi1_rd2addr, rfi1_wraddr, rfi1_wrdata, rfi1_ren1,
rfi1_ren2, rfi1_wren, rfi2_rd1addr, rfi2_rd2addr, rfi2_wraddr,
rfi2_wrdata, rfi2_ren1, rfi2_ren2, rfi2_wren, rfo1_data1,
rfo1_data2, rfo2_data1, rfo2_data2);--, disasen);
end generate;
alt : if (tech = altera) generate -- Cyclone, Stratix V, Cyclone V
grfpw0 : grfpw_0_altera
port map (rst, clk, holdn, cpi_flush, cpi_exack, cpi_a_rs1, cpi_d_pc,
cpi_d_inst, cpi_d_cnt, cpi_d_trap, cpi_d_annul, cpi_d_pv, cpi_a_pc,
cpi_a_inst, cpi_a_cnt, cpi_a_trap, cpi_a_annul, cpi_a_pv, cpi_e_pc,
cpi_e_inst, cpi_e_cnt, cpi_e_trap, cpi_e_annul, cpi_e_pv, cpi_m_pc,
cpi_m_inst, cpi_m_cnt, cpi_m_trap, cpi_m_annul, cpi_m_pv, cpi_x_pc,
cpi_x_inst, cpi_x_cnt, cpi_x_trap, cpi_x_annul, cpi_x_pv, cpi_lddata,
cpi_dbg_enable, cpi_dbg_write, cpi_dbg_fsr, cpi_dbg_addr, cpi_dbg_data,
cpo_data, cpo_exc, cpo_cc, cpo_ccv, cpo_ldlock, cpo_holdn, cpo_dbg_data,
rfi1_rd1addr, rfi1_rd2addr, rfi1_wraddr, rfi1_wrdata, rfi1_ren1,
rfi1_ren2, rfi1_wren, rfi2_rd1addr, rfi2_rd2addr, rfi2_wraddr,
rfi2_wrdata, rfi2_ren1, rfi2_ren2, rfi2_wren, rfo1_data1,
rfo1_data2, rfo2_data1, rfo2_data2 );
end generate;
strtx : if (tech = stratix1) or (tech = stratix2) generate
grfpw0 : grfpw_0_stratixii
port map (rst, clk, holdn, cpi_flush, cpi_exack, cpi_a_rs1, cpi_d_pc,
cpi_d_inst, cpi_d_cnt, cpi_d_trap, cpi_d_annul, cpi_d_pv, cpi_a_pc,
cpi_a_inst, cpi_a_cnt, cpi_a_trap, cpi_a_annul, cpi_a_pv, cpi_e_pc,
cpi_e_inst, cpi_e_cnt, cpi_e_trap, cpi_e_annul, cpi_e_pv, cpi_m_pc,
cpi_m_inst, cpi_m_cnt, cpi_m_trap, cpi_m_annul, cpi_m_pv, cpi_x_pc,
cpi_x_inst, cpi_x_cnt, cpi_x_trap, cpi_x_annul, cpi_x_pv, cpi_lddata,
cpi_dbg_enable, cpi_dbg_write, cpi_dbg_fsr, cpi_dbg_addr, cpi_dbg_data,
cpo_data, cpo_exc, cpo_cc, cpo_ccv, cpo_ldlock, cpo_holdn, cpo_dbg_data,
rfi1_rd1addr, rfi1_rd2addr, rfi1_wraddr, rfi1_wrdata, rfi1_ren1,
rfi1_ren2, rfi1_wren, rfi2_rd1addr, rfi2_rd2addr, rfi2_wraddr,
rfi2_wrdata, rfi2_ren1, rfi2_ren2, rfi2_wren, rfo1_data1,
rfo1_data2, rfo2_data1, rfo2_data2 );
end generate;
strtxiii : if (tech = stratix3) or (tech = stratix4) generate
grfpw0 : grfpw_0_stratixiii
port map (rst, clk, holdn, cpi_flush, cpi_exack, cpi_a_rs1, cpi_d_pc,
cpi_d_inst, cpi_d_cnt, cpi_d_trap, cpi_d_annul, cpi_d_pv, cpi_a_pc,
cpi_a_inst, cpi_a_cnt, cpi_a_trap, cpi_a_annul, cpi_a_pv, cpi_e_pc,
cpi_e_inst, cpi_e_cnt, cpi_e_trap, cpi_e_annul, cpi_e_pv, cpi_m_pc,
cpi_m_inst, cpi_m_cnt, cpi_m_trap, cpi_m_annul, cpi_m_pv, cpi_x_pc,
cpi_x_inst, cpi_x_cnt, cpi_x_trap, cpi_x_annul, cpi_x_pv, cpi_lddata,
cpi_dbg_enable, cpi_dbg_write, cpi_dbg_fsr, cpi_dbg_addr, cpi_dbg_data,
cpo_data, cpo_exc, cpo_cc, cpo_ccv, cpo_ldlock, cpo_holdn, cpo_dbg_data,
rfi1_rd1addr, rfi1_rd2addr, rfi1_wraddr, rfi1_wrdata, rfi1_ren1,
rfi1_ren2, rfi1_wren, rfi2_rd1addr, rfi2_rd2addr, rfi2_wraddr,
rfi2_wrdata, rfi2_ren1, rfi2_ren2, rfi2_wren, rfo1_data1,
rfo1_data2, rfo2_data1, rfo2_data2 );
end generate;
cyc3 : if (tech = cyclone3) generate
grfpw0 : grfpw_0_cycloneiii
port map (rst, clk, holdn, cpi_flush, cpi_exack, cpi_a_rs1, cpi_d_pc,
cpi_d_inst, cpi_d_cnt, cpi_d_trap, cpi_d_annul, cpi_d_pv, cpi_a_pc,
cpi_a_inst, cpi_a_cnt, cpi_a_trap, cpi_a_annul, cpi_a_pv, cpi_e_pc,
cpi_e_inst, cpi_e_cnt, cpi_e_trap, cpi_e_annul, cpi_e_pv, cpi_m_pc,
cpi_m_inst, cpi_m_cnt, cpi_m_trap, cpi_m_annul, cpi_m_pv, cpi_x_pc,
cpi_x_inst, cpi_x_cnt, cpi_x_trap, cpi_x_annul, cpi_x_pv, cpi_lddata,
cpi_dbg_enable, cpi_dbg_write, cpi_dbg_fsr, cpi_dbg_addr, cpi_dbg_data,
cpo_data, cpo_exc, cpo_cc, cpo_ccv, cpo_ldlock, cpo_holdn, cpo_dbg_data,
rfi1_rd1addr, rfi1_rd2addr, rfi1_wraddr, rfi1_wrdata, rfi1_ren1,
rfi1_ren2, rfi1_wren, rfi2_rd1addr, rfi2_rd2addr, rfi2_wraddr,
rfi2_wrdata, rfi2_ren1, rfi2_ren2, rfi2_wren, rfo1_data1,
rfo1_data2, rfo2_data1, rfo2_data2 );
end generate;
u0_tsmc90 : if tech = tsmc90 generate
grfpw0 : grfpw_tsmc90
port map (rst, clk, holdn, cpi_flush, cpi_exack, cpi_a_rs1, cpi_d_pc,
cpi_d_inst, cpi_d_cnt, cpi_d_trap, cpi_d_annul, cpi_d_pv, cpi_a_pc,
cpi_a_inst, cpi_a_cnt, cpi_a_trap, cpi_a_annul, cpi_a_pv, cpi_e_pc,
cpi_e_inst, cpi_e_cnt, cpi_e_trap, cpi_e_annul, cpi_e_pv, cpi_m_pc,
cpi_m_inst, cpi_m_cnt, cpi_m_trap, cpi_m_annul, cpi_m_pv, cpi_x_pc,
cpi_x_inst, cpi_x_cnt, cpi_x_trap, cpi_x_annul, cpi_x_pv, cpi_lddata,
cpi_dbg_enable, cpi_dbg_write, cpi_dbg_fsr, cpi_dbg_addr, cpi_dbg_data,
cpo_data, cpo_exc, cpo_cc, cpo_ccv, cpo_ldlock, cpo_holdn, cpo_dbg_data,
rfi1_rd1addr, rfi1_rd2addr, rfi1_wraddr, rfi1_wrdata, rfi1_ren1,
rfi1_ren2, rfi1_wren, rfi2_rd1addr, rfi2_rd2addr, rfi2_wraddr,
rfi2_wrdata, rfi2_ren1, rfi2_ren2, rfi2_wren, rfo1_data1,
rfo1_data2, rfo2_data1, rfo2_data2 );
end generate;
u0_tm65gplus : if tech = tm65gplus generate
grfpw0 : grfpw_tm65gplus
port map (rst, clk, holdn, cpi_flush, cpi_exack, cpi_a_rs1, cpi_d_pc,
cpi_d_inst, cpi_d_cnt, cpi_d_trap, cpi_d_annul, cpi_d_pv, cpi_a_pc,
cpi_a_inst, cpi_a_cnt, cpi_a_trap, cpi_a_annul, cpi_a_pv, cpi_e_pc,
cpi_e_inst, cpi_e_cnt, cpi_e_trap, cpi_e_annul, cpi_e_pv, cpi_m_pc,
cpi_m_inst, cpi_m_cnt, cpi_m_trap, cpi_m_annul, cpi_m_pv, cpi_x_pc,
cpi_x_inst, cpi_x_cnt, cpi_x_trap, cpi_x_annul, cpi_x_pv, cpi_lddata,
cpi_dbg_enable, cpi_dbg_write, cpi_dbg_fsr, cpi_dbg_addr, cpi_dbg_data,
cpo_data, cpo_exc, cpo_cc, cpo_ccv, cpo_ldlock, cpo_holdn, cpo_dbg_data,
rfi1_rd1addr, rfi1_rd2addr, rfi1_wraddr, rfi1_wrdata, rfi1_ren1,
rfi1_ren2, rfi1_wren, rfi2_rd1addr, rfi2_rd2addr, rfi2_wraddr,
rfi2_wrdata, rfi2_ren1, rfi2_ren2, rfi2_wren, rfo1_data1,
rfo1_data2, rfo2_data1, rfo2_data2 );
end generate;
u0_cust1 : if tech = custom1 generate
grfpw0 : grfpw_cust1
port map (rst, clk, holdn, cpi_flush, cpi_exack, cpi_a_rs1, cpi_d_pc,
cpi_d_inst, cpi_d_cnt, cpi_d_trap, cpi_d_annul, cpi_d_pv, cpi_a_pc,
cpi_a_inst, cpi_a_cnt, cpi_a_trap, cpi_a_annul, cpi_a_pv, cpi_e_pc,
cpi_e_inst, cpi_e_cnt, cpi_e_trap, cpi_e_annul, cpi_e_pv, cpi_m_pc,
cpi_m_inst, cpi_m_cnt, cpi_m_trap, cpi_m_annul, cpi_m_pv, cpi_x_pc,
cpi_x_inst, cpi_x_cnt, cpi_x_trap, cpi_x_annul, cpi_x_pv, cpi_lddata,
cpi_dbg_enable, cpi_dbg_write, cpi_dbg_fsr, cpi_dbg_addr, cpi_dbg_data,
cpo_data, cpo_exc, cpo_cc, cpo_ccv, cpo_ldlock, cpo_holdn, cpo_dbg_data,
rfi1_rd1addr, rfi1_rd2addr, rfi1_wraddr, rfi1_wrdata, rfi1_ren1,
rfi1_ren2, rfi1_wren, rfi2_rd1addr, rfi2_rd2addr, rfi2_wraddr,
rfi2_wrdata, rfi2_ren1, rfi2_ren2, rfi2_wren, rfo1_data1,
rfo1_data2, rfo2_data1, rfo2_data2 );
end generate;
end;
| gpl-3.0 | 846b19c2e6c6354551d40685b4f3ef51 | 0.617103 | 2.700273 | false | false | false | false |
hoglet67/CoPro6502 | src/CPU65C02/fsm_intnmi.vhd | 1 | 4,873 | -- VHDL Entity r65c02_tc.fsm_intnmi.symbol
--
-- Created:
-- by - eda.UNKNOWN (ENTW-7HPZ200)
-- at - 11:59:05 06.09.2018
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
entity fsm_intnmi is
port(
clk_clk_i : in std_logic;
nmi_n_i : in std_logic;
rst_nmi_i : in std_logic;
rst_rst_n_i : in std_logic;
nmi_o : out std_logic
);
-- Declarations
end fsm_intnmi ;
-- (C) 2008 - 2013 Jens Gutschmidt
-- (email: [email protected])
--
-- Versions:
-- Revision 1.8 2018/09/01 18:07:00 jens
-- - NMI = '0' need at least 1 cycles for correct
-- operation now (2 cycles in the past)
--
-- Revision 1.7 2013/07/21 11:11:00 jens
-- - Changing the title block and internal revision history
--
-- Revision 1.6 2009/01/04 10:20:47 eda
-- Changes for cosmetic issues only
--
-- Revision 1.5 2009/01/04 09:23:10 eda
-- - Delete unused nets and blocks (same as R6502_TC)
-- - Rename blocks
--
-- Revision 1.4 2009/01/03 16:53:02 eda
-- - Unused nets and blocks deleted
-- - Renamed blocks
--
-- Revision 1.3 2009/01/03 16:42:02 eda
-- - Unused nets and blocks deleted
-- - Renamed blocks
--
-- Revision 1.2 2008/12/31 19:31:24 eda
-- Production Release
--
--
--
-- VHDL Architecture r65c02_tc.fsm_intnmi.fsm
--
-- Created:
-- by - eda.UNKNOWN (ENTW-7HPZ200)
-- at - 11:59:05 06.09.2018
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5)
--
-- COPYRIGHT (C) 2008 - 2013 by Jens Gutschmidt
--
-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
architecture fsm of fsm_intnmi is
type state_type is (
idle,
idle1,
IMP
);
-- State vector declaration
attribute state_vector : string;
attribute state_vector of fsm : architecture is "current_state";
-- Declare current and next state signals
signal current_state : state_type;
signal next_state : state_type;
-- Declare any pre-registered internal signals
signal nmi_o_cld : std_logic ;
begin
-----------------------------------------------------------------
clocked_proc : process (
clk_clk_i,
rst_rst_n_i
)
-----------------------------------------------------------------
begin
if (rst_rst_n_i = '0') then
current_state <= idle;
-- Default Reset Values
nmi_o_cld <= '0';
elsif (clk_clk_i'event and clk_clk_i = '1') then
current_state <= next_state;
-- Default Assignment To Internals
nmi_o_cld <= '0';
-- Combined Actions
case current_state is
when idle1 =>
if (nmi_n_i = '0') then
nmi_o_cld <= '1';
end if;
when IMP =>
nmi_o_cld <= '1';
if (rst_nmi_i = '1') then
nmi_o_cld <= '0';
end if;
when others =>
null;
end case;
end if;
end process clocked_proc;
-----------------------------------------------------------------
nextstate_proc : process (
current_state,
nmi_n_i,
rst_nmi_i
)
-----------------------------------------------------------------
begin
case current_state is
when idle =>
if (nmi_n_i = '1') then
next_state <= idle1;
else
next_state <= idle;
end if;
when idle1 =>
if (nmi_n_i = '0') then
next_state <= IMP;
else
next_state <= idle1;
end if;
when IMP =>
if (rst_nmi_i = '1') then
next_state <= idle;
else
next_state <= IMP;
end if;
when others =>
next_state <= idle;
end case;
end process nextstate_proc;
-- Concurrent Statements
-- Clocked output assignments
nmi_o <= nmi_o_cld;
end fsm;
| gpl-3.0 | db3da417f062e16375c32868fd7d313d | 0.518982 | 3.694466 | false | false | false | false |
kdgwill/VHDL_Framer_Example | VHDL_Framer_Example/Example1/blockDiagram/generator.vhd | 1 | 2,229 | ---------------------------------------------------------------------------------
--Generator------------------------------------------------------------
--By Kyle Williams, 04/07/2011--------------------------------------------------
--PROJECT DESCRIPTION------------------------------------------------------------
--1--Input Serial data stream----------------------------------------------------
----------------Define Libraries to be used--------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
-----------------ENTITY FOR GENERATOR------------------------------------------
ENTITY generator IS
Generic(N : Integer := 8);
PORT(
clock, reset, load: OUT std_logic;
D : OUT std_logic_vector(n-1 downto 0);
vec : OUT std_logic_vector(N-1 downto 0);
sin : OUT STD_Logic
);
END generator;
-----------------BEHAVIOR OF GENERATOR-----------------------------------------
ARCHITECTURE behavior OF generator IS
-------------------VARIABLE DECLARATION----------------------------------------
signal S_clock: std_logic := '0';
signal S_D: std_logic_vector(n-1 downto 0) := (others =>'0');
signal S_reset: std_logic := '0';
signal S_load: std_logic :='0';
signal tap: std_logic;
signal ssr: std_logic_vector(n-1 downto 0);
-------------------PROCEDUREE------------------------------
BEGIN
S_clock <= not S_clock after 5 ns;
S_D <= "10101011" after 250 ns;
S_reset <= '1' after 10 ns;
-- process
-- begin
-- S_load <= '1';
-- wait for 10 ns;
-- S_load <= '0';
-- wait for 10 ns;
-- end process;
clock <= S_clock;
reset <= S_reset;
load <= S_load;
D <= S_D;
Process(S_Clock,S_Reset,S_Load)
Begin
If(S_reset='0') then
SSR <= (others => '0');
elsif rising_edge(S_Clock) Then
IF S_Load = '1' AND (SSR="00000000" OR SSR="11111111") Then
SSR <= S_D;
ELSE
SSR<= SSR(6 downTo 0)&tap;
END If;
End If;
tap<=SSR(1) XOR SSR(2) XOR SSR(3) XOR SSR(7);
sin<= SSR(7);
vec<= SSR;
End Process;
END behavior;
| gpl-3.0 | b2d3766ead335965eb42f97c97d85ebd | 0.419919 | 4.082418 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/subsys/leon_dsu_stat_base.vhd | 1 | 17,765 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: leon_dsu_stat_base
-- File: leon_dsu_stat_base.vhd
-- Author: Cobham Gaisler AB
-- Description: Entity that instantiates LEON3 and LEON4 together with the
-- corresponding debug support unit and performance counters.
--
-- Limitations:
--
-- Primarly targeted for FPGA designs and for designs without clock gating
-- since the same clock feeds all instantiated blocks.
--
-- Memory BIST signals are not propagated to the top-level
--
-- Scan test is disabled
--
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.stdlib.all;
use techmap.gencomp.all;
library gaisler;
use gaisler.leon3.all;
use gaisler.leon4.all;
use gaisler.subsys.all;
entity leon_dsu_stat_base is
generic (
-- LEON selection
leon : integer range 0 to 4 := 0;
ncpu : integer range 1 to 16 := 1;
-- LEON configuration
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 63 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 2 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 2 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 7 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 128 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 31 := 0; -- support SMP systems
cached : integer := 0; -- cacheability table
clk2x : integer := 0;
wbmask : integer := 0; -- Wide-bus mask
busw : integer := 64; -- AHB/Cache data width (64/128)
netlist : integer := 0; -- Use netlist
ft : integer := 0; -- FT option
npasi : integer range 0 to 1 := 0;
pwrpsr : integer range 0 to 1 := 0;
rex : integer range 0 to 1 := 0;
altwin : integer range 0 to 1 := 0;
ahbpipe : integer := 0;
--
grfpush : integer range 0 to 1 := 0;
-- DSU
dsu_hindex : integer := 2;
dsu_haddr : integer := 16#900#;
dsu_hmask : integer := 16#F00#;
atbsz : integer := 4;
--
stat : integer range 0 to 1 := 0;
stat_pindex : integer := 0;
stat_paddr : integer := 0;
stat_pmask : integer := 16#ffc#;
stat_ncnt : integer := 1;
stat_nmax : integer := 0
--
);
port (
rstn : in std_ulogic;
--
ahbclk : in std_ulogic; -- bus clock
cpuclk : in std_ulogic; -- cpu clock
hclken : in std_ulogic; -- bus clock enable qualifier
--
leon_ahbmi : in ahb_mst_in_type;
leon_ahbmo : out ahb_mst_out_vector_type(ncpu-1 downto 0);
leon_ahbsi : in ahb_slv_in_type;
leon_ahbso : in ahb_slv_out_vector;
--
irqi : in irq_in_vector(0 to ncpu-1);
irqo : out irq_out_vector(0 to ncpu-1);
--
stat_apbi : in apb_slv_in_type;
stat_apbo : out apb_slv_out_type;
stat_ahbsi : in ahb_slv_in_type;
stati : in l3stat_in_type;
--
dsu_ahbsi : in ahb_slv_in_type;
dsu_ahbso : out ahb_slv_out_type;
dsu_tahbmi : in ahb_mst_in_type;
dsu_tahbsi : in ahb_slv_in_type;
--
sysi : in leon_dsu_stat_base_in_type;
syso : out leon_dsu_stat_base_out_type
);
end;
architecture rtl of leon_dsu_stat_base is
signal fpi : grfpu_in_vector_type;
signal fpo : grfpu_out_vector_type;
signal vcc : std_ulogic;
begin
vcc <= '1';
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if leon = 3 generate
leon3blk : block
signal l3dbgi : l3_debug_in_vector(0 to ncpu-1);
signal l3dbgo : l3_debug_out_vector(0 to ncpu-1);
signal l3dsui : dsu_in_type;
signal l3dsuo : dsu_out_type;
begin
cpu : for i in 0 to ncpu-1 generate
leon3 : leon3x -- LEON3 processor
generic map (
hindex => i,
fabtech => fabtech,
memtech => memtech,
nwindows => nwindows,
dsu => dsu,
fpu => fpu + 32*grfpush,
v8 => v8,
cp => 0,
mac => mac,
pclow => pclow,
notag => notag,
nwp => nwp,
icen => icen,
irepl => irepl,
isets => isets,
ilinesize => ilinesize,
isetsize => isetsize,
isetlock => isetlock,
dcen => dcen,
drepl => drepl,
dsets => dsets,
dlinesize => dlinesize,
dsetsize => dsetsize,
dsetlock => dsetlock,
dsnoop => dsnoop,
ilram => ilram,
ilramsize => ilramsize,
ilramstart => ilramstart,
dlram => dlram,
dlramsize => dlramsize,
dlramstart => dlramstart,
mmuen => mmuen,
itlbnum => itlbnum,
dtlbnum => dtlbnum,
tlb_type => tlb_type,
tlb_rep => tlb_rep,
lddel => lddel,
disas => disas,
tbuf => tbuf,
pwd => pwd,
svt => svt,
rstaddr => rstaddr,
smp => ncpu-1,
iuft => ft mod 4,
fpft => ft mod 4,
cmft => ft/8,
iuinj => 0, --iuinj,
ceinj => 0, --ceinj,
cached => cached,
clk2x => clk2x,
netlist => netlist,
scantest => 0,
mmupgsz => 0, -- 4 KiB
bp => 2, -- programmable
npasi => npasi,
pwrpsr => pwrpsr,
rex => rex,
altwin => altwin
)
port map (
clk => ahbclk,
gclk2 => cpuclk,
gfclk2 => cpuclk,
clk2 => cpuclk,
rstn => rstn,
ahbi => leon_ahbmi,
ahbo => leon_ahbmo(i),
ahbsi => leon_ahbsi,
ahbso => leon_ahbso,
irqi => irqi(i),
irqo => irqo(i),
dbgi => l3dbgi(i),
dbgo => l3dbgo(i),
fpui => fpi(i),
fpuo => fpo(i),
clken => hclken);
end generate cpu;
syso.proc_error <= l3dbgo(0).error;
syso.proc_errorn <= not l3dbgo(0).error;
-- LEON3 Debug Support Unit
dsugen : if dsu = 1 generate
dsu0 : dsu3x
generic map (
hindex => dsu_hindex,
haddr => dsu_haddr,
hmask => dsu_hmask,
ncpu => ncpu,
tbits => 30,
tech => memtech,
irq => 0,
kbytes => atbsz,
clk2x => 0,
testen => 0,
bwidth => AHBDW,
ahbpf => 0)
port map (
rst => rstn,
hclk => ahbclk,
cpuclk => cpuclk,
ahbmi => dsu_tahbmi,
ahbsi => dsu_ahbsi,
ahbso => dsu_ahbso,
tahbsi => dsu_tahbsi,
dbgi => l3dbgo,
dbgo => l3dbgi,
dsui => l3dsui,
dsuo => l3dsuo,
hclken => hclken
);
l3dsui.enable <= sysi.dsu_enable;
l3dsui.break <= sysi.dsu_break;
syso.dsu_active <= l3dsuo.active;
syso.dsu_tstop <= l3dsuo.tstop;
end generate;
nodsugen : if dsu = 0 generate
l3dbgi <= (others => dbgi_none);
end generate;
l3sgen : if stat /= 0 generate
l3s : l3stat
generic map (
pindex => stat_pindex,
paddr => stat_paddr,
pmask => stat_pmask,
ncnt => stat_ncnt,
ncpu => ncpu,
nmax => stat_nmax,
lahben => 1,
dsuen => dsu,
forcer0 => 0)
port map (
rstn => rstn,
clk => ahbclk,
apbi => stat_apbi,
apbo => stat_apbo,
ahbsi => stat_ahbsi,
dbgo => l3dbgo,
dsuo => l3dsuo,
stati => stati,
apb2i => apb_slv_in_none,
apb2o => open,
astat => amba_stat_none);
end generate;
nol3s : if stat = 0 generate
stat_apbo <= apb_none;
end generate;
end block leon3blk;
end generate;
----------------------------------------------------------------------
--- LEON4 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l4 : if leon = 4 generate
leon4blk : block
signal l4dbgi : l4_debug_in_vector(0 to ncpu-1);
signal l4dbgo : l4_debug_out_vector(0 to ncpu-1);
signal l4dsui : dsu4_in_type;
signal l4dsuo : dsu4_out_type;
begin
cpu : for i in 0 to ncpu-1 generate
leon4 : leon4x -- LEON4 processor
generic map (
hindex => i,
fabtech => fabtech,
memtech => memtech,
nwindows => nwindows,
dsu => dsu,
fpu => fpu + 32*grfpush,
v8 => v8,
cp => 0,
mac => mac,
pclow => pclow,
notag => notag,
nwp => nwp,
icen => icen,
irepl => irepl,
isets => isets,
ilinesize => ilinesize,
isetsize => isetsize,
isetlock => isetlock,
dcen => dcen,
drepl => drepl,
dsets => dsets,
dlinesize => dlinesize,
dsetsize => dsetsize,
dsetlock => dsetlock,
dsnoop => dsnoop,
ilram => ilram,
ilramsize => ilramsize,
ilramstart => ilramstart,
dlram => dlram,
dlramsize => dlramsize,
dlramstart => dlramstart,
mmuen => mmuen,
itlbnum => itlbnum,
dtlbnum => dtlbnum,
tlb_type => tlb_type,
tlb_rep => tlb_rep,
lddel => lddel,
disas => disas,
tbuf => tbuf,
pwd => pwd,
svt => svt,
rstaddr => rstaddr,
smp => smp,
cached => cached,
clk2x => 0,
scantest => 0,
wbmask => wbmask,
busw => busw,
netlist => netlist,
ft => ft,
npasi => npasi,
pwrpsr => pwrpsr)
port map (
ahbclk => ahbclk,
cpuclk => cpuclk,
gcpuclk => cpuclk,
fpuclk => cpuclk,
hclken => hclken,
rstn => rstn,
ahbi => leon_ahbmi,
ahbo => leon_ahbmo(i),
ahbsi => leon_ahbsi,
ahbso => leon_ahbso,
irqi => irqi(i),
irqo => irqo(i),
dbgi => l4dbgi(i),
dbgo => l4dbgo(i),
fpui => fpi(i),
fpuo => fpo(i)
);
end generate cpu;
syso.proc_error <= l4dbgo(0).error;
syso.proc_errorn <= not l4dbgo(0).error;
-- LEON4 Debug Support Unit
dsugen : if dsu = 1 generate
dsu0 : dsu4x
generic map (
hindex => dsu_hindex,
haddr => dsu_haddr,
hmask => dsu_hmask,
ncpu => ncpu,
tbits => 30,
tech => memtech,
irq => 0,
kbytes => atbsz,
clk2x => 0, -- fixme
bwidth => AHBDW,
ahbpf => 0, -- fixme
ahbwp => 0, -- fixme
scantest => 0,
pipedbg => 0,
pipeahbt => 0)
port map (
rst => rstn,
hclk => ahbclk,
cpuclk => cpuclk,
fcpuclk => cpuclk,
ahbmi => dsu_tahbmi,
ahbsi => dsu_ahbsi,
ahbso => dsu_ahbso,
tahbsi => dsu_tahbsi,
dbgi => l4dbgo,
dbgo => l4dbgi,
dsui => l4dsui,
dsuo => l4dsuo,
hclken => hclken
);
l4dsui.enable <= sysi.dsu_enable;
l4dsui.break <= sysi.dsu_break;
syso.dsu_active <= l4dsuo.active;
syso.dsu_tstop <= l4dsuo.tstop;
end generate;
nodsugen : if dsu = 0 generate
l4dbgi <= (others => l4_dbgi_none);
end generate;
l4sgen : if stat /= 0 generate
l4s : l4stat
generic map (
pindex => stat_pindex,
paddr => stat_paddr,
pmask => stat_pmask,
ncnt => stat_ncnt,
ncpu => ncpu,
nmax => stat_nmax,
lahben => 0,
dsuen => dsu,
nextev => 7)
port map (
rstn => rstn,
clk => ahbclk,
apbi => stat_apbi,
apbo => stat_apbo,
ahbsi => stat_ahbsi,
dbgo => l4dbgo,
dsuo => l4dsuo,
stati => stati,
apb2i => apb_slv_in_none,
apb2o => open,
astat => amba_stat_none);
end generate;
nol4s : if stat = 0 generate
stat_apbo <= apb_none;
end generate;
end block leon4blk;
end generate;
nodsu : if dsu = 0 generate
syso.dsu_tstop <= '0'; syso.dsu_active <= '0';
dsu_ahbso <= ahbs_none;
end generate;
----------------------------------------------------------------------
--- Optional shared FPU -----------------------------------------
----------------------------------------------------------------------
shfpu : if grfpush = 1 generate
grfpush0 : grfpushwx generic map ((fpu-1), ncpu, fabtech)
port map (cpuclk, rstn, fpi, fpo);
end generate;
noshfpu : if grfpush = 0 generate
fpo <= (others => grfpu_out_none);
end generate;
end;
| gpl-3.0 | 5a276a0e9c6fb51a9daa365c4ac71c88 | 0.428539 | 4.224732 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-altera-ep3c25-eek/serializer.vhd | 1 | 2,713 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
-- Entity: serializer
-- File: serializer.vhd
-- Author: Jan Andersson - Gaisler Research AB
-- [email protected]
--
-- Description: Takes in three vectors and serializes them into one
-- output vector. Intended to be used to serialize
-- RGB VGA data.
--
library ieee;
use ieee.std_logic_1164.all;
entity serializer is
generic (
length : integer := 8 -- vector length
);
port (
clk : in std_ulogic;
sync : in std_ulogic;
ivec0 : in std_logic_vector((length-1) downto 0);
ivec1 : in std_logic_vector((length-1) downto 0);
ivec2 : in std_logic_vector((length-1) downto 0);
ovec : out std_logic_vector((length-1) downto 0)
);
end entity serializer;
architecture rtl of serializer is
type state_type is (vec0, vec1, vec2);
type sreg_type is record
state : state_type;
sync : std_logic_vector(1 downto 0);
end record;
signal r, rin : sreg_type;
begin -- rtl
comb: process (r, clk, sync, ivec0, ivec1, ivec2)
variable v : sreg_type;
begin -- process comb
v := r;
v.sync := r.sync(0) & sync;
case r.state is
when vec0 =>
ovec <= ivec0;
v.state := vec1;
when vec1 =>
ovec <= ivec1;
v.state := vec2;
when vec2 =>
ovec <= ivec2;
v.state := vec0;
end case;
if (r.sync(0) xor sync) = '1' then
v.state := vec1;
end if;
rin <= v;
end process comb;
reg: process (clk)
begin -- process reg
if rising_edge(clk) then
r <= rin;
end if;
end process reg;
end rtl;
| gpl-3.0 | eff780558e5cd2be51a5867be079e9d2 | 0.588279 | 3.757618 | false | false | false | false |
18545/FPGA | FPGA.srcs/sources_1/ip/blk_mem_gen_1/synth/blk_mem_gen_1.vhd | 1 | 14,454 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_2;
USE blk_mem_gen_v8_2.blk_mem_gen_v8_2;
ENTITY blk_mem_gen_1 IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(18 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(18 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
);
END blk_mem_gen_1;
ARCHITECTURE blk_mem_gen_1_arch OF blk_mem_gen_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF blk_mem_gen_1_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_2 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(18 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(18 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(18 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(18 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_2;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF blk_mem_gen_1_arch: ARCHITECTURE IS "blk_mem_gen_v8_2,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF blk_mem_gen_1_arch : ARCHITECTURE IS "blk_mem_gen_1,blk_mem_gen_v8_2,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF blk_mem_gen_1_arch: ARCHITECTURE IS "blk_mem_gen_1,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=1,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAME=no_coe_file_loaded,C_INIT_FILE=blk_mem_gen_1.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=NO_CHANGE,C_WRITE_WIDTH_A=12,C_READ_WIDTH_A=12,C_WRITE_DEPTH_A=307200,C_READ_DEPTH_A=307200,C_ADDRA_WIDTH=19,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=12,C_READ_WIDTH_B=12,C_WRITE_DEPTH_B=307200,C_READ_DEPTH_B=307200,C_ADDRB_WIDTH=19,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=1,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=103,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 16.887376 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF clkb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
ATTRIBUTE X_INTERFACE_INFO OF addrb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
ATTRIBUTE X_INTERFACE_INFO OF doutb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
BEGIN
U0 : blk_mem_gen_v8_2
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 1,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 0,
C_INIT_FILE_NAME => "no_coe_file_loaded",
C_INIT_FILE => "blk_mem_gen_1.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 0,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "NO_CHANGE",
C_WRITE_WIDTH_A => 12,
C_READ_WIDTH_A => 12,
C_WRITE_DEPTH_A => 307200,
C_READ_DEPTH_A => 307200,
C_ADDRA_WIDTH => 19,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 12,
C_READ_WIDTH_B => 12,
C_WRITE_DEPTH_B => 307200,
C_READ_DEPTH_B => 307200,
C_ADDRB_WIDTH => 19,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 1,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "103",
C_COUNT_18K_BRAM => "1",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 16.887376 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => '0',
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
clkb => clkb,
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => addrb,
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
doutb => doutb,
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END blk_mem_gen_1_arch;
| mit | 304c31295802be255f202964d3b99f48 | 0.628407 | 3.015019 | false | false | false | false |
yishinli/emc2 | src/hal/drivers/m5i20/hostmot5_src/pwmgen.vhd | 1 | 3,331 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity pwmgen is
port (
clk: in STD_LOGIC;
refcount: in STD_LOGIC_VECTOR (9 downto 0);
ibus: in STD_LOGIC_VECTOR (15 downto 0);
obus: out STD_LOGIC_VECTOR (15 downto 0);
loadpwmval: in STD_LOGIC;
readpwmval: in STD_LOGIC;
clearpwmval: in STD_LOGIC;
pcrloadcmd: STD_LOGIC;
pcrreadcmd: STD_LOGIC;
pwmout: out STD_LOGIC;
dirio: inout STD_LOGIC;
enablein: in STD_LOGIC;
enableout: out STD_LOGIC
);
end pwmgen;
architecture behavioral of pwmgen is
signal pwmval: STD_LOGIC_VECTOR (9 downto 0);
signal fixedpwmval: STD_LOGIC_VECTOR (9 downto 0);
signal fixedrefcount: STD_LOGIC_VECTOR (9 downto 0);
signal dir: STD_LOGIC;
signal pwm: STD_LOGIC;
signal unsignedmode: STD_LOGIC;
signal localenable: STD_LOGIC;
signal lacedpwm: STD_LOGIC;
begin
apwmgen: process (clk,
refcount,
ibus,
loadpwmval,
readpwmval,
clearpwmval,
enablein,
localenable,
lacedpwm,
pwmval,
dir,
pcrreadcmd,
pwm
)
begin
if clk'event and clk = '1' then
if unsignedmode = '0' then
if dir = '1' then
-- fixedpwmval <= (not pwmval) +1; -- convert from 2s comp to magnitude
-- suffers from overflow problem
fixedpwmval <= (not pwmval); -- convert from 2s comp to magnitude
-- suffers from discontinuity at 0 but thats more palatable than overflow
else
fixedpwmval <= pwmval;
end if;
dirio <= dir;
else -- unsigned mode
fixedpwmval <= pwmval;
dirio <= 'Z';
end if;
if lacedpwm = '1' then -- interlaced (600 kc) output for analog
fixedrefcount(9) <= refcount(4);
fixedrefcount(8) <= refcount(5);
fixedrefcount(7) <= refcount(6);
fixedrefcount(6) <= refcount(7);
fixedrefcount(5) <= refcount(8);
fixedrefcount(4) <= refcount(9);
fixedrefcount(3 downto 0) <= refcount(3 downto 0);
else
fixedrefcount <= refcount;
end if;
if (UNSIGNED(fixedrefcount) < UNSIGNED(fixedpwmval)) and (enablein = '1') and (localenable = '1') then
pwm <= '1';
else
pwm <= '0';
end if;
pwmout <= pwm;
if loadpwmval = '1' then
if unsignedmode = '0' then
pwmval <= ibus(14 downto 5);
dir <= ibus(15);
else
pwmval <= ibus(15 downto 6);
end if;
end if;
if pcrloadcmd = '1' then
unsignedmode <= ibus(2);
lacedpwm <= ibus(1);
localenable <= ibus(0);
end if;
end if;
if clearpwmval = '1' then
pwmval <= "0000000000";
localenable <= '0';
end if;
if readpwmval = '1' and pcrreadcmd = '0' then
if unsignedmode = '0' then
obus(14 downto 5) <= pwmval;
obus(15) <= dir;
obus(4 downto 0) <= "00000";
else
obus(15 downto 6) <= pwmval;
obus(5 downto 0) <= "000000";
end if;
elsif readpwmval = '0' and pcrreadcmd = '1' then
obus(4) <= dirio;
obus(3) <= pwm;
obus(2) <= unsignedmode;
obus(1) <= lacedpwm;
obus(0) <= localenable;
obus(15 downto 5) <="00000000000";
else
obus <= "ZZZZZZZZZZZZZZZZ";
end if;
enableout <= not localenable;
end process;
end behavioral;
| lgpl-2.1 | 49cc9de3f0dc735c7a79320cf7ac8309 | 0.592615 | 2.934802 | false | false | false | false |
Gizeta/bjuedc | uart-fpga/uart_recv.vhd | 1 | 2,905 | --------------------------------------------
-- 串口接收模块
--------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity uart_recv is
generic(framelen : integer := 8); -- 数据为framelen - 1
port(
bclk_r, reset_r, rxd : in std_logic; -- rxd - 数据输入脚
r_ready : out std_logic;
rbuf : out std_logic_vector(7 downto 0)
);
end uart_recv;
architecture arch of uart_recv is
type states is (r_idle, r_sample_start_bit, r_sample_data_bit, r_sample, r_stop);
signal state : states := r_idle;
signal rxd_syn : std_logic;
begin
process(rxd) -- 用DFF把数据输入脚整形下,防止干扰
begin
if rxd = '0' then
rxd_syn <= '0';
else
rxd_syn <= '1';
end if;
end process;
process(bclk_r, reset_r, rxd_syn)
variable count : std_logic_vector(3 downto 0) := "0000";
variable rcnt : integer range 0 to framelen := 0;
variable rbuf_tmp : std_logic_vector(7 downto 0);
begin
if reset_r = '1' then
state <= r_idle;
count := "0000";
rcnt := 0;
r_ready <= '0';
elsif rising_edge(bclk_r) then
case state is -- 检测是否是起始位
when r_idle =>
if rxd_syn = '0' then
state <= r_sample_start_bit;
r_ready <= '0'; -- 检测到起始位后才复位r_ready
rcnt := 0;
count := "0000"; -- 在这儿起始位为0已经有一个时钟时间了
else
state <= r_idle;
end if;
when r_sample_start_bit => -- 检测起始位是否够时间
if rxd_syn = '0' then
if count < "0111" then -- 8个时钟后, 再采样
count := count + 1;
state <= r_sample_start_bit;
else -- 起始位正确,开始采样数据位
state <= r_sample_data_bit;
count := "0000";
rcnt := 0; -- 开始接收数据位
end if;
else
state <= r_idle;
count := "0000";
end if;
when r_sample_data_bit =>
if count <= "1110" then -- 16个时钟后再采样
count := count + 1;
state <= r_sample_data_bit;
else
if rcnt = framelen then
state <= r_stop;
count := "0000";
rcnt := 0;
else
state <= r_sample_data_bit;
count := "0000";
rbuf_tmp(rcnt) := rxd_syn; -- 移入数据位
rcnt := rcnt + 1;
end if;
end if;
when r_stop => -- 省略了对停止位的检测
r_ready <= '1'; -- 接受数据可读了
rbuf <= rbuf_tmp; -- 更新输出数据
state <= r_idle;
when others=>
state <= r_idle;
end case;
end if;
end process;
end arch;
| mit | 5af92a3e491ebfea7916face77f80ac8 | 0.481229 | 2.853896 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/tech/virage/simprims/virage_simprims.vhd | 1 | 18,579 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: virage_simprims
-- File: virage_simprims.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: Simple simulation models for VIRAGE RAMs
-----------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
package virage_simprims is
component virage_syncram_sim
generic ( abits : integer := 10; dbits : integer := 8 );
port (
addr : in std_logic_vector((abits -1) downto 0);
clk : in std_logic;
di : in std_logic_vector((dbits -1) downto 0);
do : out std_logic_vector((dbits -1) downto 0);
me : in std_logic;
oe : in std_logic;
we : in std_logic
);
end component;
-- synchronous 2-port ram
component virage_2pram_sim
generic (
abits : integer := 8;
dbits : integer := 32;
words : integer := 256
);
port (
addra, addrb : in std_logic_vector((abits -1) downto 0);
clka, clkb : in std_logic;
dia : in std_logic_vector((dbits -1) downto 0);
dob : out std_logic_vector((dbits -1) downto 0);
mea, wea, meb, oeb : in std_logic
);
end component;
component virage_dpram_sim
generic (
abits : integer := 8;
dbits : integer := 32
);
port (
addra : in std_logic_vector((abits -1) downto 0);
clka : in std_logic;
dia : in std_logic_vector((dbits -1) downto 0);
doa : out std_logic_vector((dbits -1) downto 0);
mea, oea, wea : in std_logic;
addrb : in std_logic_vector((abits -1) downto 0);
clkb : in std_logic;
dib : in std_logic_vector((dbits -1) downto 0);
dob : out std_logic_vector((dbits -1) downto 0);
meb, oeb, web : in std_logic
);
end component;
end;
-- 1-port syncronous ram
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity virage_syncram_sim is
generic (
abits : integer := 10;
dbits : integer := 8
);
port (
addr : in std_logic_vector((abits -1) downto 0);
clk : in std_logic;
di : in std_logic_vector((dbits -1) downto 0);
do : out std_logic_vector((dbits -1) downto 0);
me : in std_logic;
oe : in std_logic;
we : in std_logic
);
end;
architecture behavioral of virage_syncram_sim is
subtype word is std_logic_vector((dbits -1) downto 0);
type mem is array(0 to (2**abits -1)) of word;
begin
main : process(clk, oe, me)
variable memarr : mem;-- := (others => (others => '0'));
variable doint : std_logic_vector((dbits -1) downto 0);
begin
if rising_edge(clk) and (me = '1') and not is_x(addr) then
if (we = '1') then memarr(to_integer(unsigned(addr))) := di; end if;
doint := memarr(to_integer(unsigned(addr)));
end if;
-- if (me and oe) = '1' then do <= doint;
if oe = '1' then do <= doint;
else do <= (others => 'Z'); end if;
end process;
end behavioral;
-- synchronous 2-port ram
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity virage_2pram_sim is
generic (
abits : integer := 10;
dbits : integer := 8;
words : integer := 1024
);
port (
addra, addrb : in std_logic_vector((abits -1) downto 0);
clka, clkb : in std_logic;
dia : in std_logic_vector((dbits -1) downto 0);
dob : out std_logic_vector((dbits -1) downto 0);
mea, wea, meb, oeb : in std_logic
);
end;
architecture behavioral of virage_2pram_sim is
subtype word is std_logic_vector((dbits -1) downto 0);
type mem is array(0 to (words-1)) of word;
begin
main : process(clka, clkb, oeb, mea, meb, wea)
variable memarr : mem;
variable doint : std_logic_vector((dbits -1) downto 0);
begin
if rising_edge(clka) and (mea = '1') and not is_x(addra) then
if (wea = '1') then memarr(to_integer(unsigned(addra)) mod words) := dia; end if;
end if;
if rising_edge(clkb) and (meb = '1') and not is_x(addrb) then
doint := memarr(to_integer(unsigned(addrb)) mod words);
end if;
if oeb = '1' then dob <= doint;
else dob <= (others => 'Z'); end if;
end process;
end behavioral;
-- synchronous dual-port ram
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity virage_dpram_sim is
generic (
abits : integer := 10;
dbits : integer := 8
);
port (
addra : in std_logic_vector((abits -1) downto 0);
clka : in std_logic;
dia : in std_logic_vector((dbits -1) downto 0);
doa : out std_logic_vector((dbits -1) downto 0);
mea, oea, wea : in std_logic;
addrb : in std_logic_vector((abits -1) downto 0);
clkb : in std_logic;
dib : in std_logic_vector((dbits -1) downto 0);
dob : out std_logic_vector((dbits -1) downto 0);
meb, oeb, web : in std_logic
);
end;
architecture behavioral of virage_dpram_sim is
subtype word is std_logic_vector((dbits -1) downto 0);
type mem is array(0 to (2**abits -1)) of word;
begin
main : process(clka, oea, mea, clkb, oeb, meb)
variable memarr : mem;
variable dointa, dointb : std_logic_vector((dbits -1) downto 0);
begin
if rising_edge(clka) and (mea = '1') and not is_x(addra) then
if (wea = '1') then memarr(to_integer(unsigned(addra))) := dia; end if;
dointa := memarr(to_integer(unsigned(addra)));
end if;
if oea = '1' then doa <= dointa;
else doa <= (others => 'Z'); end if;
if rising_edge(clkb) and (meb = '1') and not is_x(addrb) then
if (web = '1') then memarr(to_integer(unsigned(addrb))) := dib; end if;
dointb := memarr(to_integer(unsigned(addrb)));
end if;
if oeb = '1' then dob <= dointb;
else dob <= (others => 'Z'); end if;
end process;
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss1_128x32cm4sw0ab is
port (
addr, taddr : in std_logic_vector(6 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(31 downto 0);
do : out std_logic_vector(31 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end;
architecture behavioral of hdss1_128x32cm4sw0ab is
begin
syncram0 : virage_syncram_sim
generic map ( abits => 7, dbits => 32)
port map ( addr, clk, di, do, me, oe, we);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss1_256x32cm4sw0ab is
port (
addr, taddr : in std_logic_vector(7 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(31 downto 0);
do : out std_logic_vector(31 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end;
architecture behavioral of hdss1_256x32cm4sw0ab is
begin
syncram0 : virage_syncram_sim
generic map ( abits => 8, dbits => 32)
port map ( addr, clk, di, do, me, oe, we);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss1_512x32cm4sw0ab is
port (
addr, taddr : in std_logic_vector(8 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(31 downto 0);
do : out std_logic_vector(31 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end;
architecture behavioral of hdss1_512x32cm4sw0ab is
begin
syncram0 : virage_syncram_sim
generic map ( abits => 9, dbits => 32)
port map ( addr, clk, di, do, me, oe, we);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss1_512x38cm4sw0ab is
port (
addr, taddr : in std_logic_vector(8 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(37 downto 0);
do : out std_logic_vector(37 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end;
architecture behavioral of hdss1_512x38cm4sw0ab is
begin
syncram0 : virage_syncram_sim
generic map ( abits => 9, dbits => 38)
port map ( addr, clk, di, do, me, oe, we);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss1_1024x32cm4sw0ab is
port (
addr, taddr : in std_logic_vector(9 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(31 downto 0);
do : out std_logic_vector(31 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end;
architecture behavioral of hdss1_1024x32cm4sw0ab is
begin
syncram0 : virage_syncram_sim
generic map ( abits => 10, dbits => 32)
port map ( addr, clk, di, do, me, oe, we);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss1_2048x32cm8sw0ab is
port (
addr, taddr : in std_logic_vector(10 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(31 downto 0);
do : out std_logic_vector(31 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end;
architecture behavioral of hdss1_2048x32cm8sw0ab is
begin
syncram0 : virage_syncram_sim
generic map ( abits => 11, dbits => 32)
port map ( addr, clk, di, do, me, oe, we);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss1_4096x36cm8sw0ab is
port (
addr, taddr : in std_logic_vector(11 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(35 downto 0);
do : out std_logic_vector(35 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end;
architecture behavioral of hdss1_4096x36cm8sw0ab is
begin
syncram0 : virage_syncram_sim
generic map ( abits => 12, dbits => 36)
port map ( addr, clk, di, do, me, oe, we);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss1_16384x8cm16sw0 is
port (
addr : in std_logic_vector(13 downto 0);
clk : in std_logic;
di : in std_logic_vector(7 downto 0);
do : out std_logic_vector(7 downto 0);
me, oe, we : in std_logic
);
end;
architecture behavioral of hdss1_16384x8cm16sw0 is
begin
syncram0 : virage_syncram_sim
generic map ( abits => 14, dbits => 8)
port map ( addr, clk, di, do, me, oe, we);
end behavioral;
-- 2-port syncronous ram
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity rfss2_136x32cm2sw0ab is
port (
addra, taddra : in std_logic_vector(7 downto 0);
addrb, taddrb : in std_logic_vector(7 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(31 downto 0);
dob : out std_logic_vector(31 downto 0);
mea, wea, tmea, twea, bistea : in std_logic;
meb, oeb, tmeb, awtb, bisteb, toeb : in std_logic
);
end;
architecture behavioral of rfss2_136x32cm2sw0ab is
begin
syncram0 : virage_2pram_sim
generic map ( abits => 8, dbits => 32, words => 136)
port map ( addra, addrb, clka, clkb, dia, dob, mea, wea, meb, oeb);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity rfss2_136x40cm2sw0ab is
port (
addra, taddra : in std_logic_vector(7 downto 0);
addrb, taddrb : in std_logic_vector(7 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(39 downto 0);
dob : out std_logic_vector(39 downto 0);
mea, wea, tmea, twea, bistea : in std_logic;
meb, oeb, tmeb, awtb, bisteb, toeb : in std_logic
);
end;
architecture behavioral of rfss2_136x40cm2sw0ab is
begin
syncram0 : virage_2pram_sim
generic map ( abits => 8, dbits => 40, words => 136)
port map ( addra, addrb, clka, clkb, dia, dob, mea, wea, meb, oeb);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity rfss2_168x32cm2sw0ab is
port (
addra, taddra : in std_logic_vector(7 downto 0);
addrb, taddrb : in std_logic_vector(7 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(31 downto 0);
dob : out std_logic_vector(31 downto 0);
mea, wea, tmea, twea, bistea : in std_logic;
meb, oeb, tmeb, awtb, bisteb, toeb : in std_logic
);
end;
architecture behavioral of rfss2_168x32cm2sw0ab is
begin
syncram0 : virage_2pram_sim
generic map ( abits => 8, dbits => 32, words => 168)
port map ( addra, addrb, clka, clkb, dia, dob, mea, wea, meb, oeb);
end behavioral;
-- dual-port syncronous ram
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss2_64x32cm4sw0ab is
port (
addra, taddra : in std_logic_vector(5 downto 0);
addrb, taddrb : in std_logic_vector(5 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(31 downto 0);
dib, tdib : in std_logic_vector(31 downto 0);
doa, dob : out std_logic_vector(31 downto 0);
mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
);
end;
architecture behavioral of hdss2_64x32cm4sw0ab is
begin
syncram0 : virage_dpram_sim
generic map ( abits => 6, dbits => 32)
port map ( addra, clka, dia, doa, mea, oea, wea,
addrb, clkb, dib, dob, meb, oeb, web);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss2_128x32cm4sw0ab is
port (
addra, taddra : in std_logic_vector(6 downto 0);
addrb, taddrb : in std_logic_vector(6 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(31 downto 0);
dib, tdib : in std_logic_vector(31 downto 0);
doa, dob : out std_logic_vector(31 downto 0);
mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
);
end;
architecture behavioral of hdss2_128x32cm4sw0ab is
begin
syncram0 : virage_dpram_sim
generic map ( abits => 7, dbits => 32)
port map ( addra, clka, dia, doa, mea, oea, wea,
addrb, clkb, dib, dob, meb, oeb, web);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss2_256x32cm4sw0ab is
port (
addra, taddra : in std_logic_vector(7 downto 0);
addrb, taddrb : in std_logic_vector(7 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(31 downto 0);
dib, tdib : in std_logic_vector(31 downto 0);
doa, dob : out std_logic_vector(31 downto 0);
mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
);
end;
architecture behavioral of hdss2_256x32cm4sw0ab is
begin
syncram0 : virage_dpram_sim
generic map ( abits => 8, dbits => 32)
port map ( addra, clka, dia, doa, mea, oea, wea,
addrb, clkb, dib, dob, meb, oeb, web);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss2_512x32cm4sw0ab is
port (
addra, taddra : in std_logic_vector(8 downto 0);
addrb, taddrb : in std_logic_vector(8 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(31 downto 0);
dib, tdib : in std_logic_vector(31 downto 0);
doa, dob : out std_logic_vector(31 downto 0);
mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
);
end;
architecture behavioral of hdss2_512x32cm4sw0ab is
begin
syncram0 : virage_dpram_sim
generic map ( abits => 9, dbits => 32)
port map ( addra, clka, dia, doa, mea, oea, wea,
addrb, clkb, dib, dob, meb, oeb, web);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss2_512x38cm4sw0ab is
port (
addra, taddra : in std_logic_vector(8 downto 0);
addrb, taddrb : in std_logic_vector(8 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(37 downto 0);
dib, tdib : in std_logic_vector(37 downto 0);
doa, dob : out std_logic_vector(37 downto 0);
mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
);
end;
architecture behavioral of hdss2_512x38cm4sw0ab is
begin
syncram0 : virage_dpram_sim
generic map ( abits => 9, dbits => 38)
port map ( addra, clka, dia, doa, mea, oea, wea,
addrb, clkb, dib, dob, meb, oeb, web);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss2_8192x8cm16sw0ab is
port (
addra, taddra : in std_logic_vector(12 downto 0);
addrb, taddrb : in std_logic_vector(12 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(7 downto 0);
dib, tdib : in std_logic_vector(7 downto 0);
doa, dob : out std_logic_vector(7 downto 0);
mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
);
end;
architecture behavioral of hdss2_8192x8cm16sw0ab is
begin
syncram0 : virage_dpram_sim
generic map ( abits => 13, dbits => 8)
port map ( addra, clka, dia, doa, mea, oea, wea,
addrb, clkb, dib, dob, meb, oeb, web);
end behavioral;
-- pragma translate_on
| gpl-3.0 | 418abe5bb06a4b45e56d8bfc03b05ac8 | 0.634157 | 3.168315 | false | false | false | false |
EliasLuiz/TCC | Leon3/lib/gaisler/i2c/i2cmst.vhd | 1 | 11,746 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: i2cmst
-- File: i2cmst.vhd
-- Author: Jan Andersson - Gaisler Research
-- Contact: [email protected]
-- Description:
--
-- APB interface to OpenCores I2C-master. This is an GRLIB AMBA wrapper
-- that instantiates the byte- and bit-controller of the OpenCores I2C
-- master (OC core developed by Richard Herveille, [email protected]).
-- The OC byte- and bit-controller are located under lib/opencores/i2c
--
-- The original master had a WISHBONE interface with registers
-- aligned at byte boundaries. This wrapper has a slighly different
-- alignment of the registers, and also (optionally) adds a filter
-- filter register (FR):
--
-- +------------+--------------------------------------+
-- | Offset | Bits in word |
-- | |---------+---------+---------+--------+
-- | | 31 - 24 | 23 - 16 | 15 - 8 | 7 - 0 |
-- +------------+---------+---------+---------+--------+
-- | 0x00 | 0x00 | 0x00 | PRERhi | PRERlo |
-- | 0x04 | 0x00 | 0x00 | 0x00 | CTR |
-- | 0x08 | 0x00 | 0x00 | 0x00 | TXR |
-- | 0x08 | 0x00 | 0x00 | 0x00 | RXR |
-- | 0x0C | 0x00 | 0x00 | 0x00 | CR |
-- | 0x0C | 0x00 | 0x00 | 0x00 | SR |
-- | 0x10 | FR |
-- +------------+---------+---------+---------+--------+
--
-- Revision 1 of this core also sets the TIP bit when STO is set.
--
-- Revision 2 of this core adds a filter generic to adjust the low pass filter
--
-- Revision 3 of this core adds yet another filter generic that can be set to
-- make the filter soft configurable.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.i2c.all;
library opencores;
use opencores.i2coc.all;
entity i2cmst is
generic (
-- APB generics
pindex : integer := 0; -- slave bus index
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0; -- interrupt index
oepol : integer range 0 to 1 := 0; -- output enable polarity
filter : integer range 2 to 512 := 2; -- filter bit size
dynfilt : integer range 0 to 1 := 0);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- APB signals
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
-- I2C signals
i2ci : in i2c_in_type;
i2co : out i2c_out_type
);
end entity i2cmst;
architecture rtl of i2cmst is
-----------------------------------------------------------------------------
-- Constants
-----------------------------------------------------------------------------
constant I2CMST_REV : integer := 3;
constant PCONFIG : apb_config_type := (
0 => ahb_device_reg(VENDOR_GAISLER, GAISLER_I2CMST, 0, I2CMST_REV, pirq),
1 => apb_iobar(paddr, pmask));
constant PRER_addr : std_logic_vector(7 downto 2) := "000000";
constant CTR_addr : std_logic_vector(7 downto 2) := "000001";
constant TXR_addr : std_logic_vector(7 downto 2) := "000010";
constant RXR_addr : std_logic_vector(7 downto 2) := "000010";
constant CR_addr : std_logic_vector(7 downto 2) := "000011";
constant SR_addr : std_logic_vector(7 downto 2) := "000011";
constant FR_addr : std_logic_vector(7 downto 2) := "000100";
-----------------------------------------------------------------------------
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Types
-----------------------------------------------------------------------------
-- Register interface
type ctrl_reg_type is record -- Control register
en : std_ulogic;
ien : std_ulogic;
end record;
type cmd_reg_type is record -- Command register
sta : std_ulogic;
sto : std_ulogic;
rd : std_ulogic;
wr : std_ulogic;
ack : std_ulogic;
end record;
type sts_reg_type is record -- Status register
rxack : std_ulogic;
busy : std_ulogic;
al : std_ulogic;
tip : std_ulogic;
ifl : std_ulogic;
end record;
-- Core registers
type i2c_reg_type is record
-- i2c registers
prer : std_logic_vector(15 downto 0); -- clock prescale register
ctrl : ctrl_reg_type; -- control register
txr : std_logic_vector(7 downto 0); -- transmit register
cmd : cmd_reg_type; -- command register
sts : sts_reg_type; -- status register
filt : std_logic_vector((filter-1)*dynfilt downto 0); -- filter register
--
irq : std_ulogic;
end record;
-- Signals to and from byte controller block
signal rxr : std_logic_vector(7 downto 0); -- Receive register
signal done : std_logic; -- Signals completion of command
signal rxack : std_logic; -- Received acknowledge
signal busy : std_logic; -- I2C core busy
signal al : std_logic; -- Aribitration lost
signal irst : std_ulogic; -- Internal, negated reset signal
signal iscloen : std_ulogic; -- Internal SCL output enable
signal isdaoen : std_ulogic; -- Internal SDA output enable
-- Register interface
signal r, rin : i2c_reg_type;
signal vcc : std_logic;
begin
-- Byte Controller from OpenCores I2C master,
-- by Richard Herveille ([email protected]). The asynchronous
-- reset is tied to '1'. Only the synchronous reset is used.
vcc <= '1';
byte_ctrl: i2c_master_byte_ctrl
generic map (
filter => filter,
dynfilt => dynfilt)
port map (
clk => clk,
rst => irst,
nReset => vcc,
ena => r.ctrl.en,
clk_cnt => r.prer,
start => r.cmd.sta,
stop => r.cmd.sto,
read => r.cmd.rd,
write => r.cmd.wr,
ack_in => r.cmd.ack,
din => r.txr,
filt => r.filt,
cmd_ack => done,
ack_out => rxack,
i2c_busy => busy,
i2c_al => al,
dout => rxr,
scl_i => i2ci.scl,
scl_o => i2co.scl,
scl_oen => iscloen,
sda_i => i2ci.sda,
sda_o => i2co.sda,
sda_oen => isdaoen);
-- OC I2C logic has active high reset.
irst <= not rstn;
i2co.enable <= r.ctrl.en;
-- Fix output enable polarity
soepol0: if oepol = 0 generate
i2co.scloen <= iscloen;
i2co.sdaoen <= isdaoen;
end generate soepol0;
soepol1: if oepol /= 0 generate
i2co.scloen <= not iscloen;
i2co.sdaoen <= not isdaoen;
end generate soepol1;
comb: process (r, rstn, rxr, rxack, busy, al, done, apbi)
variable v : i2c_reg_type;
variable irq : std_logic_vector((NAHBIRQ-1) downto 0);
variable apbaddr : std_logic_vector(7 downto 2);
variable apbout : std_logic_vector(31 downto 0);
begin -- process comb
v := r; v.irq := '0'; irq := (others=>'0'); irq(pirq) := r.irq;
apbaddr := apbi.paddr(7 downto 2); apbout := (others => '0');
-- Command done or arbitration lost, clear command register
if (done or al) = '1' then
v.cmd := ('0', '0', '0', '0', '0');
end if;
-- Update status register
v.sts := (rxack => rxack,
busy => busy,
al => al or (r.sts.al and not r.cmd.sta),
tip => r.cmd.rd or r.cmd.wr or r.cmd.sto,
ifl => done or al or r.sts.ifl);
v.irq := (done or al) and r.ctrl.ien;
-- read registers
if (apbi.psel(pindex) and apbi.penable and (not apbi.pwrite)) = '1' then
case apbaddr is
when PRER_addr =>
apbout(15 downto 0) := r.prer;
when CTR_addr =>
apbout(7 downto 6) := r.ctrl.en & r.ctrl.ien;
when RXR_addr =>
apbout(7 downto 0) := rxr;
when SR_addr =>
apbout(7 downto 5) := r.sts.rxack & r.sts.busy & r.sts.al;
apbout(1 downto 0) := r.sts.tip & r.sts.ifl;
when FR_addr =>
if dynfilt /= 0 then apbout(r.filt'range) := r.filt; end if;
when others => null;
end case;
end if;
-- write registers
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbaddr is
when PRER_addr => v.prer := apbi.pwdata(15 downto 0);
when CTR_addr => v.ctrl.en := apbi.pwdata(7);
v.ctrl.ien := apbi.pwdata(6);
when TXR_addr => v.txr := apbi.pwdata(7 downto 0);
when CR_addr =>
-- Check that core is enabled and that WR and RD has been cleared
-- before accepting new command.
if (r.ctrl.en and not (r.cmd.wr or r.cmd.rd)) = '1' then
v.cmd.sta := apbi.pwdata(7);
v.cmd.sto := apbi.pwdata(6);
v.cmd.rd := apbi.pwdata(5);
v.cmd.wr := apbi.pwdata(4);
v.cmd.ack := apbi.pwdata(3);
end if;
-- Bit 0 of CR is interrupt acknowledge. The core will only pulse one
-- interrupt per irq event. Software does not have to clear the
-- interrupt flag...
if apbi.pwdata(0) = '1' then
v.sts.ifl := '0';
end if;
when FR_addr =>
if dynfilt /= 0 then v.filt := apbi.pwdata(r.filt'range); end if;
when others => null;
end case;
end if;
if rstn = '0' then
v.prer := (others => '1');
v.ctrl := ('0', '0');
v.txr := (others => '0');
v.cmd := ('0','0','0','0', '0');
v.sts := ('0','0','0','0', '0');
if dynfilt /= 0 then v.filt := (others => '1'); end if;
end if;
if dynfilt = 0 then v.filt := (others => '0'); end if;
-- Update registers
rin <= v;
-- Update outputs
apbo.prdata <= apbout;
apbo.pirq <= irq;
apbo.pconfig <= PCONFIG;
apbo.pindex <= pindex;
end process comb;
reg: process (clk)
begin -- process reg
if rising_edge(clk) then
r <= rin;
end if;
end process reg;
-- Boot message
-- pragma translate_off
bootmsg : report_version
generic map (
"i2cmst" & tost(pindex) & ": AMBA Wrapper for OC I2C-master rev " &
tost(I2CMST_REV) & ", irq " & tost(pirq));
-- pragma translate_on
end architecture rtl;
| gpl-3.0 | 1bdff0744ef70ac90a19bf4e64f8a423 | 0.516857 | 3.654636 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-xilinx-zc702/testbench.vhd | 2 | 7,478 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2012 Fredrik Ringhage, Gaisler Research
-- Modified by Jiri Gaisler, 2014-04-05
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.config.all;
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
end;
architecture behav of testbench is
signal button : std_logic_vector(3 downto 0) := (others => '0');
signal switch : std_logic_vector(7 downto 0); -- I/O port
signal led : std_logic_vector(7 downto 0); -- I/O port
signal processing_system7_0_MIO : std_logic_vector(53 downto 0);
signal processing_system7_0_PS_SRSTB : std_logic;
signal processing_system7_0_PS_CLK : std_logic;
signal processing_system7_0_PS_PORB : std_logic;
signal processing_system7_0_DDR_Clk : std_logic;
signal processing_system7_0_DDR_Clk_n : std_logic;
signal processing_system7_0_DDR_CKE : std_logic;
signal processing_system7_0_DDR_CS_n : std_logic;
signal processing_system7_0_DDR_RAS_n : std_logic;
signal processing_system7_0_DDR_CAS_n : std_logic;
signal processing_system7_0_DDR_WEB_pin : std_logic;
signal processing_system7_0_DDR_BankAddr : std_logic_vector(2 downto 0);
signal processing_system7_0_DDR_Addr : std_logic_vector(14 downto 0);
signal processing_system7_0_DDR_ODT : std_logic;
signal processing_system7_0_DDR_DRSTB : std_logic;
signal processing_system7_0_DDR_DQ : std_logic_vector(31 downto 0);
signal processing_system7_0_DDR_DM : std_logic_vector(3 downto 0);
signal processing_system7_0_DDR_DQS : std_logic_vector(3 downto 0);
signal processing_system7_0_DDR_DQS_n : std_logic_vector(3 downto 0);
signal processing_system7_0_DDR_VRN : std_logic;
signal processing_system7_0_DDR_VRP : std_logic;
component leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
processing_system7_0_MIO : inout std_logic_vector(53 downto 0);
processing_system7_0_PS_SRSTB : inout std_logic;
processing_system7_0_PS_CLK : inout std_logic;
processing_system7_0_PS_PORB : inout std_logic;
processing_system7_0_DDR_Clk : inout std_logic;
processing_system7_0_DDR_Clk_n : inout std_logic;
processing_system7_0_DDR_CKE : inout std_logic;
processing_system7_0_DDR_CS_n : inout std_logic;
processing_system7_0_DDR_RAS_n : inout std_logic;
processing_system7_0_DDR_CAS_n : inout std_logic;
processing_system7_0_DDR_WEB_pin : inout std_logic;
processing_system7_0_DDR_BankAddr : inout std_logic_vector(2 downto 0);
processing_system7_0_DDR_Addr : inout std_logic_vector(14 downto 0);
processing_system7_0_DDR_ODT : inout std_logic;
processing_system7_0_DDR_DRSTB : inout std_logic;
processing_system7_0_DDR_DQ : inout std_logic_vector(31 downto 0);
processing_system7_0_DDR_DM : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_DQS : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_DQS_n : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_VRN : inout std_logic;
processing_system7_0_DDR_VRP : inout std_logic;
button : in std_logic_vector(3 downto 0);
switch : inout std_logic_vector(7 downto 0);
led : out std_logic_vector(7 downto 0)
);
end component;
begin
-- clock, reset and misc
button <= (others => '0');
switch <= (others => '0');
cpu : leon3mp
generic map (
fabtech => fabtech,
memtech => memtech,
padtech => padtech,
clktech => clktech,
disas => disas,
dbguart => dbguart,
pclow => pclow
)
port map (
processing_system7_0_MIO => processing_system7_0_MIO,
processing_system7_0_PS_SRSTB => processing_system7_0_PS_SRSTB,
processing_system7_0_PS_CLK => processing_system7_0_PS_CLK,
processing_system7_0_PS_PORB => processing_system7_0_PS_PORB,
processing_system7_0_DDR_Clk => processing_system7_0_DDR_Clk,
processing_system7_0_DDR_Clk_n => processing_system7_0_DDR_Clk_n,
processing_system7_0_DDR_CKE => processing_system7_0_DDR_CKE,
processing_system7_0_DDR_CS_n => processing_system7_0_DDR_CS_n,
processing_system7_0_DDR_RAS_n => processing_system7_0_DDR_RAS_n,
processing_system7_0_DDR_CAS_n => processing_system7_0_DDR_CAS_n,
processing_system7_0_DDR_WEB_pin => processing_system7_0_DDR_WEB_pin,
processing_system7_0_DDR_BankAddr => processing_system7_0_DDR_BankAddr,
processing_system7_0_DDR_Addr => processing_system7_0_DDR_Addr,
processing_system7_0_DDR_ODT => processing_system7_0_DDR_ODT,
processing_system7_0_DDR_DRSTB => processing_system7_0_DDR_DRSTB,
processing_system7_0_DDR_DQ => processing_system7_0_DDR_DQ,
processing_system7_0_DDR_DM => processing_system7_0_DDR_DM,
processing_system7_0_DDR_DQS => processing_system7_0_DDR_DQS,
processing_system7_0_DDR_DQS_n => processing_system7_0_DDR_DQS_n,
processing_system7_0_DDR_VRN => processing_system7_0_DDR_VRN,
processing_system7_0_DDR_VRP => processing_system7_0_DDR_VRP,
button => button,
switch => switch,
led => led
);
iuerr : process
begin
wait for 5000 ns;
wait on led(1);
assert (led(1) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
end ;
| gpl-3.0 | 487737f5fad900d39f6f0a044f5804af | 0.620754 | 3.547438 | false | false | false | false |
tec499-20142/t02-warmup | rtl/uart.vhd | 1 | 7,098 | ----------------------------------------------------------------------------------
-- Creation Date: 21:12:48 05/06/2010
-- Module Name: RS232/UART Interface - Behavioral
-- Used TAB of 4 Spaces
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity uart is
generic (
CLK_FREQ : integer := 50; -- Main frequency (MHz)
SER_FREQ : integer := 9600 -- Baud rate (bps)
);
port (
-- Control
clk : in std_logic; -- Main clock
rst : in std_logic; -- Main reset
-- External Interface
rx : in std_logic; -- RS232 received serial data
tx : out std_logic; -- RS232 transmitted serial data
-- RS232/UART Configuration
par_en : in std_logic; -- Parity bit enable
-- uPC Interface
tx_req : in std_logic; -- Request SEND of data
tx_end : out std_logic; -- Data SENDED
tx_data : in std_logic_vector(7 downto 0); -- Data to transmit
rx_ready : out std_logic; -- Received data ready to uPC read
rx_data : out std_logic_vector(7 downto 0) -- Received data
);
end uart;
architecture Behavioral of uart is
-- Constants
constant UART_IDLE : std_logic := '1';
constant UART_START : std_logic := '0';
constant PARITY_EN : std_logic := '1';
constant RST_LVL : std_logic := '1';
-- Types
type state is (idle,data,parity,stop1,stop2); -- Stop1 and Stop2 are inter frame gap signals
-- RX Signals
signal rx_fsm : state; -- Control of reception
signal rx_clk_en : std_logic; -- Received clock enable
signal rx_rcv_init : std_logic; -- Start of reception
signal rx_par_bit : std_logic; -- Calculated Parity bit
signal rx_data_deb : std_logic; -- Debounce RX data
signal rx_data_tmp : std_logic_vector(7 downto 0); -- Serial to parallel converter
signal rx_data_cnt : std_logic_vector(2 downto 0); -- Count received bits
-- TX Signals
signal tx_fsm : state; -- Control of transmission
signal tx_clk_en : std_logic; -- Transmited clock enable
signal tx_par_bit : std_logic; -- Calculated Parity bit
signal tx_data_tmp : std_logic_vector(7 downto 0); -- Parallel to serial converter
signal tx_data_cnt : std_logic_vector(2 downto 0); -- Count transmited bits
begin
tx_clk_gen:process(clk)
variable counter : integer range 0 to conv_integer((CLK_FREQ*1_000_000)/SER_FREQ-1);
begin
if clk'event and clk = '1' then
-- Normal Operation
if counter = (CLK_FREQ*1_000_000)/SER_FREQ-1 then
tx_clk_en <= '1';
counter := 0;
else
tx_clk_en <= '0';
counter := counter + 1;
end if;
-- Reset condition
if rst = RST_LVL then
tx_clk_en <= '0';
counter := 0;
end if;
end if;
end process;
tx_proc:process(clk)
variable data_cnt : std_logic_vector(2 downto 0);
begin
if clk'event and clk = '1' then
if tx_clk_en = '1' then
-- Default values
tx_end <= '0';
tx <= UART_IDLE;
-- FSM description
case tx_fsm is
-- Wait to transfer data
when idle =>
-- Send Init Bit
if tx_req = '1' then
tx <= UART_START;
tx_data_tmp <= tx_data;
tx_fsm <= data;
tx_data_cnt <= (others=>'1');
tx_par_bit <= '0';
end if;
-- Data receive
when data =>
tx <= tx_data_tmp(0);
tx_par_bit <= tx_par_bit xor tx_data_tmp(0);
if tx_data_cnt = 0 then
if par_en = PARITY_EN then
tx_fsm <= parity;
else
tx_fsm <= stop1;
end if;
tx_data_cnt <= (others=>'1');
else
tx_data_tmp <= '0' & tx_data_tmp(7 downto 1);
tx_data_cnt <= tx_data_cnt - 1;
end if;
when parity =>
tx <= tx_par_bit;
tx_fsm <= stop1;
-- End of communication
when stop1 =>
-- Send Stop Bit
tx <= UART_IDLE;
tx_fsm <= stop2;
when stop2 =>
-- Send Stop Bit
tx_end <= '1';
tx <= UART_IDLE;
tx_fsm <= idle;
-- Invalid States
when others => null;
end case;
-- Reset condition
if rst = RST_LVL then
tx_fsm <= idle;
tx_par_bit <= '0';
tx_data_tmp <= (others=>'0');
tx_data_cnt <= (others=>'0');
end if;
end if;
end if;
end process;
rx_debounceer:process(clk)
variable deb_buf : std_logic_vector(3 downto 0);
begin
if clk'event and clk = '1' then
-- Debounce logic
if deb_buf = "0000" then
rx_data_deb <= '0';
elsif deb_buf = "1111" then
rx_data_deb <= '1';
end if;
-- Data storage to debounce
deb_buf := deb_buf(2 downto 0) & rx;
end if;
end process;
rx_start_detect:process(clk)
variable rx_data_old : std_logic;
begin
if clk'event and clk = '1' then
-- Falling edge detection
if rx_data_old = '1' and rx_data_deb = '0' and rx_fsm = idle then
rx_rcv_init <= '1';
else
rx_rcv_init <= '0';
end if;
-- Default assignments
rx_data_old := rx_data_deb;
-- Reset condition
if rst = RST_LVL then
rx_data_old := '0';
rx_rcv_init <= '0';
end if;
end if;
end process;
rx_clk_gen:process(clk)
variable counter : integer range 0 to conv_integer((CLK_FREQ*1_000_000)/SER_FREQ-1);
begin
if clk'event and clk = '1' then
-- Normal Operation
if counter = (CLK_FREQ*1_000_000)/SER_FREQ-1 or rx_rcv_init = '1' then
rx_clk_en <= '1';
counter := 0;
else
rx_clk_en <= '0';
counter := counter + 1;
end if;
-- Reset condition
if rst = RST_LVL then
rx_clk_en <= '0';
counter := 0;
end if;
end if;
end process;
rx_proc:process(clk)
begin
if clk'event and clk = '1' then
-- Default values
rx_ready <= '0';
-- Enable on UART rate
if rx_clk_en = '1' then
-- FSM description
case rx_fsm is
-- Wait to transfer data
when idle =>
if rx_data_deb = UART_START then
rx_fsm <= data;
end if;
rx_par_bit <= '0';
rx_data_cnt <= (others=>'0');
-- Data receive
when data =>
-- Check data to generate parity
if par_en = PARITY_EN then
rx_par_bit <= rx_par_bit xor rx;
end if;
if rx_data_cnt = 7 then
-- Data path
rx_data(7) <= rx;
for i in 0 to 6 loop
rx_data(i) <= rx_data_tmp(6-i);
end loop;
-- With parity verification
if par_en = PARITY_EN then
rx_fsm <= parity;
-- Without parity verification
else
rx_ready <= '1';
rx_fsm <= idle;
end if;
else
rx_data_tmp <= rx_data_tmp(6 downto 0) & rx;
rx_data_cnt <= rx_data_cnt + 1;
end if;
when parity =>
-- Check received parity
rx_fsm <= idle;
if rx_par_bit = rx then
rx_ready <= '1';
end if;
when others => null;
end case;
-- Reset condition
if rst = RST_LVL then
rx_fsm <= idle;
rx_ready <= '0';
rx_data <= (others=>'0');
rx_data_tmp <= (others=>'0');
rx_data_cnt <= (others=>'0');
end if;
end if;
end if;
end process;
end Behavioral;
| gpl-2.0 | 4e4a49eb4382b64bd3df8e415f001e20 | 0.554804 | 2.70916 | false | false | false | false |
pwsoft/fpga_examples | rtl/video/iq_mixer_tb.vhd | 1 | 2,163 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
-- -----------------------------------------------------------------------
entity iq_mixer_tb is
end entity;
-- -----------------------------------------------------------------------
architecture tb of iq_mixer_tb is
signal clk : std_logic := '0';
signal stop : std_logic := '0';
type test_t is record
name : string(1 to 16);
phase_i : unsigned(3 downto 0);
phase_q : unsigned(3 downto 0);
in_y : unsigned(7 downto 0);
in_i : signed(7 downto 0);
in_q : signed(7 downto 0);
black : std_logic;
sync : std_logic;
end record;
signal video : unsigned(7 downto 0);
signal test_reg : test_t := (
" ",
"0000", "0000",
"00000000", "00000000", "00000000",
'0', '0');
procedure wait_clk is
begin
if clk = '1' then
wait until clk = '0';
end if;
wait until clk = '1';
end procedure;
procedure phase_cycle(signal t : inout test_t) is
begin
phase_loop : for i in 0 to 15 loop
wait_clk;
t.phase_i <= t.phase_i + 1;
t.phase_q <= t.phase_q + 1;
end loop;
end procedure;
begin
clk <= (not stop) and (not clk) after 5 ns;
iq_mixer_inst : entity work.iq_mixer
generic map (
black_level => "00010000"
)
port map (
clk => clk,
phase_i => test_reg.phase_i,
phase_q => test_reg.phase_q,
in_y => test_reg.in_y,
in_i => test_reg.in_i,
in_q => test_reg.in_q,
black => test_reg.black,
sync => test_reg.sync,
video => video
);
process
begin
phase_cycle(test_reg);
test_reg.in_y <= "10000000";
phase_cycle(test_reg);
i_ampl_loop : for i in -128 to 127 loop
test_reg.in_i <= to_signed(i, 8);
phase_cycle(test_reg);
end loop;
test_reg.phase_i <= X"0";
test_reg.phase_q <= X"4";
test_reg.in_i <= to_signed(16, 8);
q_ampl_loop : for i in -128 to 127 loop
test_reg.in_q <= to_signed(i, 8);
phase_cycle(test_reg);
end loop;
test_reg.name <= "BLACK LEVEL ";
test_reg.black <= '1';
phase_cycle(test_reg);
test_reg.name <= "SYNC ";
test_reg.sync <= '1';
phase_cycle(test_reg);
stop <= '1';
wait;
end process;
end architecture; | lgpl-2.1 | 1bc3c45d6972622f959fc73387523c8f | 0.550162 | 2.731061 | false | true | false | false |
EliasLuiz/TCC | Leon3/lib/techmap/saed32/pads_saed32.vhd | 1 | 12,080 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: saed32pads
-- File: pads_saed32.vhd
-- Author: Fredrik Ringhage - Aeroflex Gaisler AB
-- Description: SAED32 pad wrappers
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package saed32pads is
-- input pad
component I1025_NS port(PADIO : inout std_logic; VSS : inout std_logic; VDDIO : inout std_logic; VDD : inout std_logic; R_EN : in std_logic; VSSIO : inout std_logic;DOUT : out std_logic); end component;
-- input pad with pull-up and pull-down
component B4I1025_NS port(PADIO : inout std_logic; VSS : inout std_logic; PULL_UP : in std_logic; VDDIO : inout std_logic; EN : in std_logic; VDD : inout std_logic; VSSIO : inout std_logic; DOUT: out std_logic; DIN : in std_logic; PULL_DOWN : in std_logic; R_EN : in std_logic); end component;
-- schmitt input pad
component ISH1025_EW port(PADIO : inout std_logic; VSS : inout std_logic; VDDIO : inout std_logic; VDD : inout std_logic; R_EN : in std_logic; VSSIO : inout std_logic; DOUT : out std_logic); end component;
-- output pads
component D4I1025_NS port(PADIO : inout std_logic; VSS : inout std_logic; EN : in std_logic; VDDIO : inout std_logic; VDD : inout std_logic; VSSIO : inout std_logic; DIN : in std_logic); end component;
component D12I1025_NS port(PADIO : inout std_logic; VSS : inout std_logic; EN : in std_logic; VDDIO : inout std_logic; VDD : inout std_logic; VSSIO : inout std_logic; DIN : in std_logic); end component;
component D16I1025_NS port(PADIO : inout std_logic; VSS : inout std_logic; EN : in std_logic; VDDIO : inout std_logic; VDD : inout std_logic; VSSIO : inout std_logic; DIN : in std_logic); end component;
-- bidirectional pads (and tri-state output pads)
component B4ISH1025_NS port(PADIO : inout std_logic; VSS : inout std_logic; PULL_UP : in std_logic; VDDIO : inout std_logic; EN : in std_logic; VDD : inout std_logic; VSSIO : inout std_logic; DOUT : out std_logic; DIN : in std_logic; PULL_DOWN : in std_logic; R_EN : in std_logic); end component;
component B12ISH1025_NS port(PADIO : inout std_logic; VSS : inout std_logic; PULL_UP : in std_logic; VDDIO : inout std_logic; EN : in std_logic; VDD : inout std_logic; VSSIO : inout std_logic; DOUT : out std_logic; DIN : in std_logic; PULL_DOWN : in std_logic; R_EN : in std_logic); end component;
component B16ISH1025_NS port(PADIO : inout std_logic; VSS : inout std_logic; PULL_UP : in std_logic; VDDIO : inout std_logic; EN : in std_logic; VDD : inout std_logic; VSSIO : inout std_logic; DOUT : out std_logic; DIN : in std_logic; PULL_DOWN : in std_logic; R_EN : in std_logic); end component;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
library work;
use work.all;
-- pragma translate_off
library saed32;
use saed32.I1025_NS;
use saed32.B4I1025_NS;
use saed32.ISH1025_EW;
-- pragma translate_on
entity saed32_inpad is
generic (level : integer := 0; voltage : integer := 0; filter : integer := 0);
port (pad : in std_logic; o : out std_logic);
end;
architecture rtl of saed32_inpad is
component I1025_NS port(PADIO : inout std_logic; VSS : inout std_logic; VDDIO : inout std_logic; VDD : inout std_logic; R_EN : in std_logic; VSSIO : inout std_logic; DOUT : out std_logic); end component;
component B4I1025_NS port(PADIO : inout std_logic; VSS : inout std_logic; PULL_UP : in std_logic; VDDIO : inout std_logic; EN : in std_logic; VDD : inout std_logic; VSSIO : inout std_logic; DOUT: out std_logic; DIN : in std_logic; PULL_DOWN : in std_logic; R_EN : in std_logic); end component;
component ISH1025_EW port(PADIO : inout std_logic; VSS : inout std_logic; VDDIO : inout std_logic; VDD : inout std_logic; R_EN : in std_logic; VSSIO : inout std_logic; DOUT : out std_logic); end component;
signal localout,localpad : std_logic;
begin
norm : if filter = 0 generate
ip : I1025_NS port map (PADIO => localpad, DOUT => localout, VSS => OPEN, R_EN => '1', VDDIO => OPEN, VDD => OPEN, VSSIO => OPEN);
end generate;
pu : if filter = pullup generate
ip : B4I1025_NS port map (PADIO => localpad, PULL_UP => '1', PULL_DOWN => '0', DOUT => localout, DIN => '0', VSS => OPEN, R_EN => '1', EN => '0', VDDIO => OPEN, VDD => OPEN, VSSIO => OPEN);
end generate;
pd : if filter = pulldown generate
ip : B4I1025_NS port map (PADIO => localpad, PULL_UP => '0', PULL_DOWN => '1', DOUT => localout, DIN => '0', VSS => OPEN, R_EN => '1', EN => '0', VDDIO => OPEN, VDD => OPEN, VSSIO => OPEN);
end generate;
sch : if filter = schmitt generate
ip : ISH1025_EW port map (PADIO => localpad, DOUT => localout, VSS => OPEN, R_EN => '1', VDDIO => OPEN, VDD => OPEN, VSSIO => OPEN);
end generate;
o <= localout;
localpad <= pad;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
library work;
use work.all;
-- pragma translate_off
library saed32;
use saed32.B4ISH1025_NS;
use saed32.B12ISH1025_NS;
use saed32.B16ISH1025_NS;
-- pragma translate_on
entity saed32_iopad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : inout std_logic; i, en : in std_logic; o : out std_logic);
end ;
architecture rtl of saed32_iopad is
component B4ISH1025_NS port(PADIO : inout std_logic; VSS : inout std_logic; PULL_UP : in std_logic; VDDIO : inout std_logic; EN : in std_logic; VDD : inout std_logic; VSSIO : inout std_logic; DOUT : out std_logic; DIN : in std_logic; PULL_DOWN : in std_logic; R_EN : in std_logic); end component;
component B12ISH1025_NS port(PADIO : inout std_logic; VSS : inout std_logic; PULL_UP : in std_logic; VDDIO : inout std_logic; EN : in std_logic; VDD : inout std_logic; VSSIO : inout std_logic; DOUT : out std_logic; DIN : in std_logic; PULL_DOWN : in std_logic; R_EN : in std_logic); end component;
component B16ISH1025_NS port(PADIO : inout std_logic; VSS : inout std_logic; PULL_UP : in std_logic; VDDIO : inout std_logic; EN : in std_logic; VDD : inout std_logic; VSSIO : inout std_logic; DOUT : out std_logic; DIN : in std_logic; PULL_DOWN : in std_logic; R_EN : in std_logic); end component;
signal localen : std_logic;
signal localout,localpad : std_logic;
begin
localen <= not en;
f4 : if (strength <= 4) generate
op : B4ISH1025_NS port map (DIN => i,PADIO => pad, DOUT => o, VSS => OPEN, R_EN => localen, EN => en, VDDIO => OPEN, VDD => OPEN, VSSIO => OPEN, PULL_UP => '0', PULL_DOWN => '0');
end generate;
f12 : if (strength > 4) and (strength <= 12) generate
op : B12ISH1025_NS port map (DIN => i, PADIO => pad, DOUT => o, VSS => OPEN, R_EN => localen, EN => en, VDDIO => OPEN, VDD => OPEN, VSSIO => OPEN, PULL_UP => '0', PULL_DOWN => '0');
end generate;
f16 : if (strength > 12) generate
op : B16ISH1025_NS port map (DIN => i, PADIO => pad, DOUT => o, VSS => OPEN, R_EN => localen, EN => en, VDDIO => OPEN, VDD => OPEN, VSSIO => OPEN, PULL_UP => '0', PULL_DOWN => '0');
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
library work;
use work.all;
-- pragma translate_off
library saed32;
use saed32.D4I1025_NS;
use saed32.D12I1025_NS;
use saed32.D16I1025_NS;
-- pragma translate_on
entity saed32_outpad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_logic; i : in std_logic);
end ;
architecture rtl of saed32_outpad is
component D4I1025_NS port(PADIO : inout std_logic; VSS : inout std_logic; EN : in std_logic; VDDIO : inout std_logic; VDD : inout std_logic; VSSIO : inout std_logic; DIN : in std_logic); end component;
component D12I1025_NS port(PADIO : inout std_logic; VSS : inout std_logic; EN : in std_logic; VDDIO : inout std_logic; VDD : inout std_logic; VSSIO : inout std_logic; DIN : in std_logic); end component;
component D16I1025_NS port(PADIO : inout std_logic; VSS : inout std_logic; EN : in std_logic; VDDIO : inout std_logic; VDD : inout std_logic; VSSIO : inout std_logic; DIN : in std_logic); end component;
signal localout,localpad : std_logic;
begin
f4 : if (strength <= 4) generate
op : D4I1025_NS port map (DIN => i, PADIO => localpad, VSS => OPEN, EN => '1', VDDIO => OPEN, VDD => OPEN, VSSIO => OPEN);
end generate;
f12 : if (strength > 4) and (strength <= 12) generate
op : D12I1025_NS port map (DIN => i, PADIO => localpad, VSS => OPEN, EN => '1', VDDIO => OPEN, VDD => OPEN, VSSIO => OPEN);
end generate;
f16 : if (strength > 12) generate
op : D16I1025_NS port map (DIN => i, PADIO => localpad, VSS => OPEN, EN => '1', VDDIO => OPEN, VDD => OPEN, VSSIO => OPEN);
end generate;
pad <= localpad;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
library work;
use work.all;
-- pragma translate_off
library saed32;
use saed32.B4ISH1025_NS;
use saed32.B12ISH1025_NS;
use saed32.B16ISH1025_NS;
-- pragma translate_on
entity saed32_toutpad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_logic; i, en : in std_logic);
end ;
architecture rtl of saed32_toutpad is
component B4ISH1025_NS port(PADIO : inout std_logic; VSS : inout std_logic; PULL_UP : in std_logic; VDDIO : inout std_logic; EN : in std_logic; VDD : inout std_logic; VSSIO : inout std_logic; DOUT : out std_logic; DIN : in std_logic; PULL_DOWN : in std_logic; R_EN : in std_logic); end component;
component B12ISH1025_NS port(PADIO : inout std_logic; VSS : inout std_logic; PULL_UP : in std_logic; VDDIO : inout std_logic; EN : in std_logic; VDD : inout std_logic; VSSIO : inout std_logic; DOUT : out std_logic; DIN : in std_logic; PULL_DOWN : in std_logic; R_EN : in std_logic); end component;
component B16ISH1025_NS port(PADIO : inout std_logic; VSS : inout std_logic; PULL_UP : in std_logic; VDDIO : inout std_logic; EN : in std_logic; VDD : inout std_logic; VSSIO : inout std_logic; DOUT : out std_logic; DIN : in std_logic; PULL_DOWN : in std_logic; R_EN : in std_logic); end component;
signal localpad : std_logic;
begin
f4 : if (strength <= 4) generate
op : B4ISH1025_NS port map (DIN => i,PADIO => localpad, DOUT => OPEN, VSS => OPEN, R_EN => '0', EN => en, VDDIO => OPEN, VDD => OPEN, VSSIO => OPEN, PULL_UP => '0', PULL_DOWN => '0');
end generate;
f12 : if (strength > 4) and (strength <= 12) generate
op : B12ISH1025_NS port map (DIN => i, PADIO => localpad, DOUT => OPEN, VSS => OPEN, R_EN => '0', EN => en, VDDIO => OPEN, VDD => OPEN, VSSIO => OPEN, PULL_UP => '0', PULL_DOWN => '0');
end generate;
f16 : if (strength > 12) generate
op : B16ISH1025_NS port map (DIN => i, PADIO => localpad, DOUT => OPEN, VSS => OPEN, R_EN => '0', EN => en, VDDIO => OPEN, VDD => OPEN, VSSIO => OPEN, PULL_UP => '0', PULL_DOWN => '0');
end generate;
pad <= localpad;
end;
| gpl-3.0 | 86e4618446fac3df8976d3a398b53eb5 | 0.656043 | 3.23687 | false | false | false | false |
pwsoft/fpga_examples | rtl/ttl/ttl_7411.vhd | 1 | 2,223 | -- -----------------------------------------------------------------------
--
-- Syntiac VHDL support files.
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2018 by Peter Wendrich ([email protected])
-- http://www.syntiac.com
--
-- This source file is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- -----------------------------------------------------------------------
-- Tripple 3-input AND gate
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use work.ttl_pkg.all;
-- -----------------------------------------------------------------------
entity ttl_7411 is
generic (
latency : integer := 1
);
port (
emuclk : in std_logic;
p1 : in ttl_t;
p2 : in ttl_t;
p13 : in ttl_t;
p12 : out ttl_t;
p3 : in ttl_t;
p4 : in ttl_t;
p5 : in ttl_t;
p6 : out ttl_t;
p9 : in ttl_t;
p10 : in ttl_t;
p11 : in ttl_t;
p8 : out ttl_t
);
end entity;
architecture rtl of ttl_7411 is
signal p6_loc : ttl_t;
signal p8_loc : ttl_t;
signal p12_loc : ttl_t;
begin
p6_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p6_loc, q => p6);
p8_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p8_loc, q => p8);
p12_latency_inst : entity work.ttl_latency
generic map (latency => latency)
port map (clk => emuclk, d => p12_loc, q => p12);
p6_loc <= p3 and p4 and p5;
p8_loc <= p9 and p10 and p11;
p12_loc <= p1 and p2 and p13;
end architecture;
| lgpl-2.1 | 882d488517438667c7a7789d59701d0a | 0.557805 | 3.342857 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-avnet-eval-xc4vlx25/config.vhd | 1 | 6,291 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := virtex4;
constant CFG_MEMTECH : integer := virtex4;
constant CFG_PADTECH : integer := virtex4;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := virtex4;
constant CFG_CLKMUL : integer := (7);
constant CFG_CLKDIV : integer := (10);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 0;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 16;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 1;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 16;
constant CFG_DLINE : integer := 8;
constant CFG_DREPL : integer := 1;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0 + 1*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2 + 64*0;
constant CFG_ATBSZ : integer := 2;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_STAT_ENABLE : integer := 0;
constant CFG_STAT_CNT : integer := 1;
constant CFG_STAT_NMAX : integer := 0;
constant CFG_STAT_DSUEN : integer := 0;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
constant CFG_ALTWIN : integer := 0;
constant CFG_REX : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0045#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000014#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 1;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- DDR controller
constant CFG_DDRSP : integer := 1;
constant CFG_DDRSP_INIT : integer := 1;
constant CFG_DDRSP_FREQ : integer := (100);
constant CFG_DDRSP_COL : integer := (9);
constant CFG_DDRSP_SIZE : integer := (32);
constant CFG_DDRSP_RSKEW : integer := (0);
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 32;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 8;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := (8);
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-3.0 | 0e07525d1d44c830d1c8818a7ad7b9fc | 0.643141 | 3.607225 | false | false | false | false |
techee/geany | tests/ctags/vhdl-component.vhd | 7 | 788 | -- Taken from a comment https://github.com/universal-ctags/ctags/issues/2678
-- submitted by @pidgeon777
library ieee;
use ieee.std_logic_1164.all;
entity ENTITY_TOP is
generic (
GEN : integer := 0
);
port (
INP : in std_logic
);
end entity;
architecture arch of ENTITY_TOP is
signal sig : std_logic := '0';
component ENTITY_1
generic (
GEN : integer := 0
);
port (
INP : in std_logic
);
end component;
component ENTITY_2
generic (
GEN : integer := 0
);
port (
INP : in std_logic
);
end component;
begin
ENTITY_1_i : ENTITY_1
generic map(
GEN => 0
)
port map(
INP => '0'
);
ENTITY_2_i : ENTITY_2
generic map(
GEN => 0
)
port map(
INP => '0'
);
end architecture;
| gpl-2.0 | fd31833a2f6d4ed28f52033f3bbff812 | 0.568528 | 3.324895 | false | false | false | false |
ARC-Lab-UF/UAA | src/dsa_ctrl.vhd | 1 | 10,344 | -- Copyright (c) 2015 University of Florida
--
-- This file is part of uaa.
--
-- uaa is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- uaa is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with uaa. If not, see <http://www.gnu.org/licenses/>.
-- Greg Stitt
-- University of Florida
-- Description:
-- The dsa_ctrl entity implements a controller for its associated adder in the
-- dsa entity and is responsible for handling the control signals from/to the ibuf,
-- and obuf.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.dsa_pkg.all;
use work.math_custom.all;
entity dsa_ctrl is
generic(add_latency : positive);
port(clk : in std_logic;
rst : in std_logic;
-- ibuf control signals
ibuf_empty : in std_logic_vector(1 downto 0);
ibuf_rd : out std_logic;
ibuf_end_of_group : in std_logic;
ibuf_give_up : out std_logic;
-- obuf control signals
obuf_empty : in std_logic;
obuf_rd : out std_logic;
obuf_wr : out std_logic;
-- adder control signals
add_en : out std_logic;
add_in1_sel : out std_logic;
add_in2_sel : out std_logic_vector(1 downto 0);
add_valid_in : out std_logic;
add_valid_out : in std_logic;
add_count : in std_logic_vector(bitsNeeded(add_latency)-1 downto 0);
-- status signals
hold_output : in std_logic;
is_earliest : in std_logic;
has_ibuf_access : in std_logic;
is_steady : out std_logic;
is_coalescing : out std_logic;
done : out std_logic);
end dsa_ctrl;
architecture FSM of dsa_ctrl is
type state_type is (S_WAIT_FOR_IBUF_ACCESS, S_WAIT_FOR_DATA, S_FILL,
S_STEADY, S_COALESCE, S_DONE);
signal state, next_state : state_type;
begin
process(clk, rst)
begin
if (rst = '1') then
state <= S_WAIT_FOR_IBUF_ACCESS;
elsif (rising_edge(clk)) then
state <= next_state;
-- unsynthesizeble assertions for testing
-- synthesis should ignore, but comment out if a problem
case state is
when S_WAIT_FOR_DATA =>
assert(not(ibuf_empty = "01" and ibuf_end_of_group = '1')) report "DSA_CTRL ERROR: ibuf(1) should be empty when reaching the end of the group.";
when S_STEADY =>
-- This assertion is no longer relevant because DSA now
-- forces a write into ibuf1 when a group ends in ibuf0.
-- This isn't always needed, but prevents groups from
-- getting misaligned when both controllers are coalescing.
-- There is probably a better way to implement the buffers
-- that makes this assertion valid.
-- assert(ibuf_empty(1) = '0') report "DSA_CTRL ERROR: ibuf(1) should not have valid element in state S_STEADY.";
if (ibuf_empty(0) = '0') then
assert(add_valid_out = '1') report "DSA_CTRL ERROR: adder output isn't valid.";
end if;
when others => null;
end case;
assert(ibuf_empty /= "01") report "DSA_CTRL ERROR: ibuf(1) should be empty when ibuf(0) is empty.";
end if;
end process;
process(state, ibuf_empty, ibuf_end_of_group, obuf_empty, add_valid_out, add_count, hold_output, is_earliest, has_ibuf_access)
procedure startAdd(in1 : std_logic;
in2 : std_logic_vector(1 downto 0)) is
begin
add_en <= '1';
add_valid_in <= '1';
add_in1_sel <= in1;
add_in2_sel <= in2;
if (in1 = SEL_IBUF_L or in2 = SEL_IBUF_R) then
ibuf_rd <= '1';
end if;
if (in1 = SEL_OBUF) then
obuf_rd <= '1';
end if;
end startAdd;
begin
-- default control values
ibuf_rd <= '0';
obuf_rd <= '0';
obuf_wr <= '0';
add_en <= '0';
add_in1_sel <= SEL_IBUF_L;
add_in2_sel <= SEL_IBUF_R;
add_valid_in <= '0';
is_steady <= '0';
is_coalescing <= '0';
done <= '0';
next_state <= state;
case state is
when S_WAIT_FOR_IBUF_ACCESS =>
-- clear out the obuf from previous executions
obuf_rd <= '1';
-- wait until given access to the ibuf. This prevents
-- multiple adders from reading from the buffer simultaneously
if (has_ibuf_access = '1') then
next_state <= S_WAIT_FOR_DATA;
end if;
when S_WAIT_FOR_DATA =>
-- waits until first pair of data from ibuf, pushes that data into
-- the adder, and then moves to the fill state (or the coalesce
-- state if the end of the group is reached.
if (ibuf_empty = "00") then
startAdd(SEL_IBUF_L, SEL_IBUF_R);
if (ibuf_end_of_group = '1') then
next_state <= S_COALESCE;
else
next_state <= S_FILL;
end if;
elsif (ibuf_empty = "10" and ibuf_end_of_group = '1') then
-- the input group only has one element.
-- This code forces a zero into the adder.
-- NOTE: This can be optimized by directly moving the input
-- to the output.
startAdd(SEL_IBUF_L, SEL_ZERO);
next_state <= S_COALESCE;
end if;
when S_FILL =>
if (ibuf_end_of_group = '1') then
-- push the final values into the adder, forcing a zero
-- if necessary
if (ibuf_empty = "00") then
startAdd(SEL_IBUF_L, SEL_IBUF_R);
else
startAdd(SEL_IBUF_L, SEL_ZERO);
end if;
next_state <= S_COALESCE;
elsif (ibuf_empty = "00") then
startAdd(SEL_IBUF_L, SEL_IBUF_R);
-- if adder pipeline is full, move to steady state
if (unsigned(add_count) = (add_latency-1)) then
-- TODO: verify is steady should bea asserted here
is_steady <= '1';
next_state <= S_STEADY;
end if;
end if;
when S_STEADY =>
is_steady <= '1';
-- whenever there is a single input in ibuf, add it with the
-- output of the adder
if (ibuf_empty(0) = '0') then
startAdd(SEL_IBUF_L, SEL_ADD_OUT);
if (ibuf_end_of_group = '1') then
-- stop is_steady one cycle early to prevent writing
-- into ibuf0 twice in a row at the beginning of the
-- next group, which can happen if there is no delay
-- between groups
is_steady <= '0';
next_state <= S_COALESCE;
end if;
end if;
when S_COALESCE =>
is_coalescing <= '1';
-- force a junk value into adder when obuf or adder output is invalid
if (obuf_empty = '1' or add_valid_out = '0') then
add_en <= '1';
add_valid_in <= '0';
end if;
if (add_valid_out = '1') then
if (obuf_empty = '1') then
-- write the adder output to the obuf when empty
obuf_wr <= '1';
else
-- start an add if both adder output and obuf are valid
startAdd(SEL_OBUF, SEL_ADD_OUT);
end if;
end if;
-- the controller is done when the adder has no pending adds
-- (count = 0) and when the controller is not starting another
-- add
if (unsigned(add_count) = 0 and
not (add_valid_out = '1' and obuf_empty = '0')) then
next_state <= S_DONE;
end if;
when S_DONE =>
-- if this adder isn't handling the earliest group, delay until
-- the earliest group finishes to prevent out-of-order outputs.
-- This also stalls if hold_output isn't asserted, which
-- prevents the output from being lost.
if (is_earliest = '1' and hold_output = '0') then
done <= '1';
next_state <= S_WAIT_FOR_IBUF_ACCESS;
end if;
when others => null;
end case;
end process;
-- this process guarantees that any transition to the coalesce state
-- gives up access to the ibuf. This separate process is safer than having
-- to remember to manually specify every transition in the earlier process.
process(state, next_state)
begin
ibuf_give_up <= '0';
if (next_state = S_COALESCE and state /= S_COALESCE) then
ibuf_give_up <= '1';
end if;
end process;
end FSM;
| gpl-3.0 | d616b44601d308984e326457cd5ffcc6 | 0.491976 | 4.270851 | false | false | false | false |
EliasLuiz/TCC | Leon3/designs/leon3-digilent-nexys4ddr/leon3mp.vhd | 1 | 33,779 | ------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2013 Aeroflex Gaisler
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.spi.all;
use gaisler.net.all;
use gaisler.jtag.all;
use gaisler.ddrpkg.all;
--pragma translate_off
use gaisler.sim.all;
library unisim;
use unisim.BUFG;
use unisim.PLLE2_ADV;
use unisim.STARTUPE2;
--pragma translate_on
library esa;
use esa.memoryctrl.all;
use work.config.all;
library testgrouppolito;
use testgrouppolito.dprc_pkg.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
SIM_BYPASS_INIT_CAL : string := "OFF";
SIMULATION : string := "FALSE";
USE_MIG_INTERFACE_MODEL : boolean := false
);
port (
sys_clk_i : in std_ulogic;
-- onBoard DDR2
ddr2_dq : inout std_logic_vector(15 downto 0);
ddr2_addr : out std_logic_vector(12 downto 0);
ddr2_ba : out std_logic_vector(2 downto 0);
ddr2_ras_n : out std_ulogic;
ddr2_cas_n : out std_ulogic;
ddr2_we_n : out std_ulogic;
ddr2_cke : out std_logic_vector(0 downto 0);
ddr2_odt : out std_logic_vector(0 downto 0);
ddr2_cs_n : out std_logic_vector(0 downto 0);
ddr2_dm : out std_logic_vector(1 downto 0);
ddr2_dqs_p : inout std_logic_vector(1 downto 0);
ddr2_dqs_n : inout std_logic_vector(1 downto 0);
ddr2_ck_p : out std_logic_vector(0 downto 0);
ddr2_ck_n : out std_logic_vector(0 downto 0);
-- SPI
QspiCSn : out std_ulogic;
QspiDB : inout std_logic_vector(3 downto 0);
--pragma translate_off
QspiClk : out std_ulogic;
--pragma translate_on
-- 7 segment display
--seg : out std_logic_vector(6 downto 0);
--an : out std_logic_vector(7 downto 0);
-- LEDs
Led : out std_logic_vector(15 downto 0);
-- Switches
sw : in std_logic_vector(15 downto 0);
-- Buttons
btnCpuResetn : in std_ulogic;
btn : in std_logic_vector(4 downto 0);
-- VGA Connector
--vgaRed : out std_logic_vector(2 downto 0);
--vgaGreen : out std_logic_vector(2 downto 0);
--vgaBlue : out std_logic_vector(2 downto 1);
--Hsync : out std_ulogic;
--Vsync : out std_ulogic;
-- 12 pin connectors
--ja : inout std_logic_vector(7 downto 0);
--jb : inout std_logic_vector(7 downto 0);
--jc : inout std_logic_vector(7 downto 0);
--jd : inout std_logic_vector(7 downto 0);
-- SMSC ethernet PHY
eth_rstn : out std_ulogic;
eth_crsdv : in std_ulogic;
eth_refclk : out std_ulogic;
eth_txd : out std_logic_vector(1 downto 0);
eth_txen : out std_ulogic;
eth_rxd : in std_logic_vector(1 downto 0);
eth_rxerr : in std_ulogic;
eth_mdc : out std_ulogic;
eth_mdio : inout std_logic;
-- Pic USB-HID interface
--~ PS2KeyboardData : inout std_logic;
--~ PS2KeyboardClk : inout std_logic;
--~ PS2MouseData : inout std_logic;
--~ PS2MouseClk : inout std_logic;
--~ PicGpio : out std_logic_vector(1 downto 0);
-- USB-RS232 interface
uart_txd_in : in std_logic;
uart_rxd_out : out std_logic);
end;
architecture rtl of leon3mp is
component PLLE2_ADV
generic (
BANDWIDTH : string := "OPTIMIZED";
CLKFBOUT_MULT : integer := 5;
CLKFBOUT_PHASE : real := 0.0;
CLKIN1_PERIOD : real := 0.0;
CLKIN2_PERIOD : real := 0.0;
CLKOUT0_DIVIDE : integer := 1;
CLKOUT0_DUTY_CYCLE : real := 0.5;
CLKOUT0_PHASE : real := 0.0;
CLKOUT1_DIVIDE : integer := 1;
CLKOUT1_DUTY_CYCLE : real := 0.5;
CLKOUT1_PHASE : real := 0.0;
CLKOUT2_DIVIDE : integer := 1;
CLKOUT2_DUTY_CYCLE : real := 0.5;
CLKOUT2_PHASE : real := 0.0;
CLKOUT3_DIVIDE : integer := 1;
CLKOUT3_DUTY_CYCLE : real := 0.5;
CLKOUT3_PHASE : real := 0.0;
CLKOUT4_DIVIDE : integer := 1;
CLKOUT4_DUTY_CYCLE : real := 0.5;
CLKOUT4_PHASE : real := 0.0;
CLKOUT5_DIVIDE : integer := 1;
CLKOUT5_DUTY_CYCLE : real := 0.5;
CLKOUT5_PHASE : real := 0.0;
COMPENSATION : string := "ZHOLD";
DIVCLK_DIVIDE : integer := 1;
REF_JITTER1 : real := 0.0;
REF_JITTER2 : real := 0.0;
STARTUP_WAIT : string := "FALSE"
);
port (
CLKFBOUT : out std_ulogic := '0';
CLKOUT0 : out std_ulogic := '0';
CLKOUT1 : out std_ulogic := '0';
CLKOUT2 : out std_ulogic := '0';
CLKOUT3 : out std_ulogic := '0';
CLKOUT4 : out std_ulogic := '0';
CLKOUT5 : out std_ulogic := '0';
DO : out std_logic_vector (15 downto 0);
DRDY : out std_ulogic := '0';
LOCKED : out std_ulogic := '0';
CLKFBIN : in std_ulogic;
CLKIN1 : in std_ulogic;
CLKIN2 : in std_ulogic;
CLKINSEL : in std_ulogic;
DADDR : in std_logic_vector(6 downto 0);
DCLK : in std_ulogic;
DEN : in std_ulogic;
DI : in std_logic_vector(15 downto 0);
DWE : in std_ulogic;
PWRDWN : in std_ulogic;
RST : in std_ulogic
);
end component;
component STARTUPE2
generic (
PROG_USR : string := "FALSE";
SIM_CCLK_FREQ : real := 0.0
);
port (
CFGCLK : out std_ulogic;
CFGMCLK : out std_ulogic;
EOS : out std_ulogic;
PREQ : out std_ulogic;
CLK : in std_ulogic;
GSR : in std_ulogic;
GTS : in std_ulogic;
KEYCLEARB : in std_ulogic;
PACK : in std_ulogic;
USRCCLKO : in std_ulogic;
USRCCLKTS : in std_ulogic;
USRDONEO : in std_ulogic;
USRDONETS : in std_ulogic
);
end component;
component BUFG port (O : out std_logic; I : in std_logic); end component;
signal CLKFBOUT : std_logic;
signal CLKFBIN : std_logic;
signal eth_pll_rst : std_logic;
signal eth_clk_nobuf : std_logic;
signal eth_clk90_nobuf : std_logic;
signal eth_clk : std_logic;
signal eth_clk90 : std_logic;
signal vcc : std_logic;
signal gnd : std_logic;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal cgi : clkgen_in_type;
signal cgo, cgo1 : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal ndsuact : std_ulogic;
signal ethi : eth_in_type;
signal etho : eth_out_type;
signal gpti : gptimer_in_type;
signal spii : spi_in_type;
signal spio : spi_out_type;
signal spmi : spimctrl_in_type;
signal spmo : spimctrl_out_type;
signal clkm : std_ulogic
-- pragma translate_off
:= '0'
-- pragma translate_on
;
signal clkm2x, clk200, clkfb, pllrst, rstn, clkml : std_ulogic;
signal tck, tms, tdi, tdo : std_ulogic;
signal rstraw : std_logic;
signal btnCpuReset : std_logic;
signal lock, lock0 : std_logic;
signal clkinmig : std_logic;
signal ddr0_clkv : std_logic_vector(2 downto 0);
signal ddr0_clkbv : std_logic_vector(2 downto 0);
signal ddr0_cke : std_logic_vector(1 downto 0);
signal ddr0_csb : std_logic_vector(1 downto 0);
signal ddr0_odt : std_logic_vector(1 downto 0);
signal ddr0_addr : std_logic_vector(13 downto 0);
signal ddr0_clk_fb : std_logic;
signal clkref, calib_done, migrstn : std_logic;
-- RS232 APB Uart
signal rxd1 : std_logic;
signal txd1 : std_logic;
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of lock : signal is true;
attribute syn_keep of clkml : signal is true;
attribute syn_keep of clkm : signal is true;
attribute syn_preserve of clkml : signal is true;
attribute syn_preserve of clkm : signal is true;
attribute keep of lock : signal is true;
attribute keep of clkml : signal is true;
attribute keep of clkm : signal is true;
constant BOARD_FREQ : integer := 100000; -- CLK input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
----------------------------------------------------------------------
--- FIR component declaration --------------------------------------
----------------------------------------------------------------------
component fir_ahb_dma_apb is
generic (
hindex : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
technology : integer := virtex4);
port (
clk : in std_logic;
rstn : in std_logic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbin : in ahb_mst_in_type;
ahbout : out ahb_mst_out_type;
rm_reset: in std_logic
);
end component;
signal rm_reset : std_logic_vector(31 downto 0);
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= '1';
gnd <= '0';
led(15 downto 6) <= (others =>'0'); -- unused leds off
btnCpuReset<= not btnCpuResetn;
cgi.pllctrl <= "00";
cgi.pllrst <= rstraw;
pllrst <= not cgi.pllrst;
rst0 : rstgen generic map (acthigh => 1)
port map (btnCpuReset, clkm, lock, rstn, rstraw);
lock <= calib_done when CFG_MIG_7SERIES = 1 else cgo.clklock and lock0;
led(4) <= lock;
led(5) <= lock0;
rst1 : rstgen -- reset generator
generic map (acthigh => 1)
port map (btnCpuReset, clkm, lock, migrstn, open);
-- clock generator
clkgen_gen: if (CFG_MIG_7SERIES = 0) generate
clkgen0 : clkgen
generic map (fabtech, CFG_CLKMUL, CFG_CLKDIV, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (sys_clk_i, gnd, clkm, open, clkm2x, open, open, cgi, cgo, open, open, open);
end generate;
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => 1,
nahbm => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+CFG_PRC*2,
nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
-- LEON3 processor
leon3gen : if CFG_LEON3 = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3s
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR,
CFG_NCPU-1, CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
led(3) <= not dbgo(0).error;
led(2) <= not dsuo.active;
-- LEON3 Debug Support Unit
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#, ahbpf => CFG_AHBPF,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
--dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsui.enable <= '1';
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
-- Debug UART
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart
generic map (hindex => CFG_NCPU, pindex => 4, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(CFG_NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (uart_txd_in, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (uart_rxd_out, duo.txd);
led(0) <= not dui.rxd;
led(1) <= not duo.txd;
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(4) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd);
end generate;
----------------------------------------------------------------------
--- DDR2 Memory controller ------------------------------------------
----------------------------------------------------------------------
ddr2gen: if (CFG_DDR2SP = 1) and (CFG_MIG_7SERIES = 0) generate
ddrc : ddr2spa generic map (fabtech => fabtech, memtech => memtech,
hindex => 5, haddr => 16#400#, hmask => 16#F80#, ioaddr => 1, rstdel => 200, -- iomask generic default value
MHz => CPU_FREQ/1000, TRFC => CFG_DDR2SP_TRFC, clkmul => 12,
clkdiv => 6, col => CFG_DDR2SP_COL, Mbyte => CFG_DDR2SP_SIZE,
pwron => CFG_DDR2SP_INIT, ddrbits => CFG_DDR2SP_DATAWIDTH, raspipe => 0,
ahbfreq => CPU_FREQ/1000, readdly => 0, rskew => 0, oepol => 0,
ddelayb0 => CFG_DDR2SP_DELAY0, ddelayb1 => CFG_DDR2SP_DELAY1,
ddelayb2 => CFG_DDR2SP_DELAY2, ddelayb3 => CFG_DDR2SP_DELAY3,
ddelayb4 => CFG_DDR2SP_DELAY4, ddelayb5 => CFG_DDR2SP_DELAY5,
ddelayb6 => CFG_DDR2SP_DELAY6, ddelayb7 => CFG_DDR2SP_DELAY7, -- cbdelayb0-3 generics not used in non-ft mode
numidelctrl => 1, norefclk => 1, -- dqsse, ahbbits, bigmem, nclk, scantest and octen default
nosync => CFG_DDR2SP_NOSYNC, eightbanks => 1, odten => 3, dqsgating => 0,
burstlen => 8, ft => CFG_DDR2SP_FTEN, ftbits => CFG_DDR2SP_FTWIDTH)
port map (
btnCpuResetn, rstn, clkm, clkm, clkm, lock0, clkml, clkml, ahbsi, ahbso(5),
ddr0_clkv, ddr0_clkbv, ddr0_clk_fb, ddr0_clk_fb,
ddr0_cke, ddr0_csb, ddr2_we_n, ddr2_ras_n, ddr2_cas_n,
ddr2_dm, ddr2_dqs_p, ddr2_dqs_n, ddr0_addr, ddr2_ba, ddr2_dq, ddr0_odt,open);
ddr2_addr <= ddr0_addr(12 downto 0);
ddr2_cke <= ddr0_cke(0 downto 0);
ddr2_cs_n <= ddr0_csb(0 downto 0);
ddr2_ck_p(0) <= ddr0_clkv(0);
ddr2_ck_n(0) <= ddr0_clkbv(0);
ddr2_odt <= ddr0_odt(0 downto 0);
end generate;
noddr2 : if (CFG_DDR2SP = 0) and (CFG_MIG_7SERIES = 0) generate lock0 <= '1'; end generate;
mig_gen : if (CFG_DDR2SP = 0) and (CFG_MIG_7SERIES = 1) generate
gen_mig : if (USE_MIG_INTERFACE_MODEL /= true) generate
ddrc : ahb2mig_7series_ddr2_dq16_ad13_ba3 generic map(
hindex => 5, haddr => 16#400#, hmask => 16#F80#, pindex => 5, paddr => 5,
SIM_BYPASS_INIT_CAL => SIM_BYPASS_INIT_CAL, SIMULATION => SIMULATION, USE_MIG_INTERFACE_MODEL => USE_MIG_INTERFACE_MODEL)
port map(
ddr2_dq => ddr2_dq,
ddr2_dqs_p => ddr2_dqs_p,
ddr2_dqs_n => ddr2_dqs_n,
ddr2_addr => ddr2_addr,
ddr2_ba => ddr2_ba,
ddr2_ras_n => ddr2_ras_n,
ddr2_cas_n => ddr2_cas_n,
ddr2_we_n => ddr2_we_n,
ddr2_reset_n => open,
ddr2_ck_p => ddr2_ck_p,
ddr2_ck_n => ddr2_ck_n,
ddr2_cke => ddr2_cke,
ddr2_cs_n => ddr2_cs_n,
ddr2_dm => ddr2_dm,
ddr2_odt => ddr2_odt,
ahbsi => ahbsi,
ahbso => ahbso(5),
apbi => apbi,
apbo => apbo(5),
calib_done => calib_done,
rst_n_syn => migrstn,
rst_n_async => cgo1.clklock,--rstraw,
clk_amba => clkm,
sys_clk_i => clkinmig,
clk_ref_i => clkref,
ui_clk => clkm, -- 70 MHz clk , DDR at 280 MHz (560 Mbps)
ui_clk_sync_rst => open);
clkgenmigref0 : clkgen
generic map (clktech, 16, 8, 0,CFG_CLK_NOFB, 0, 0, 0, 100000)
port map (sys_clk_i, sys_clk_i, clkref, open, open, open, open, cgi, cgo, open, open, open);
clkgenmigin : clkgen
generic map (clktech, 14, 20, 0,CFG_CLK_NOFB, 0, 0, 0, 100000)
port map (sys_clk_i, sys_clk_i, clkinmig, open, open, open, open, cgi, cgo1, open, open, open);
end generate gen_mig;
gen_mig_model : if (USE_MIG_INTERFACE_MODEL = true) generate
-- pragma translate_off
mig_ahbram : ahbram_sim
generic map (
hindex => 5,
haddr => 16#400#,
hmask => 16#F80#,
tech => 0,
kbytes => 1000,
pipe => 0,
maccsz => AHBDW,
fname => "ram.srec"
)
port map(
rst => rstn,
clk => clkm,
ahbsi => ahbsi,
ahbso => ahbso(5)
);
ddr2_dq <= (others => 'Z');
ddr2_dqs_p <= (others => 'Z');
ddr2_dqs_n <= (others => 'Z');
ddr2_addr <= (others => '0');
ddr2_ba <= (others => '0');
ddr2_ras_n <= '0';
ddr2_cas_n <= '0';
ddr2_we_n <= '0';
ddr2_ck_p <= (others => '0');
ddr2_ck_n <= (others => '0');
ddr2_cke <= (others => '0');
ddr2_cs_n <= (others => '0');
ddr2_dm <= (others => '0');
ddr2_odt <= (others => '0');
--calib_done : out std_logic;
calib_done <= '1';
--ui_clk : out std_logic;
clkm <= not clkm after 13.333 ns;
--ui_clk_sync_rst : out std_logic
-- n/a
-- pragma translate_on
end generate gen_mig_model; end generate;
----------------------------------------------------------------------
--- SPI Memory controller -------------------------------------------
----------------------------------------------------------------------
spi_gen: if CFG_SPIMCTRL = 1 generate
-- OPTIONALY set the offset generic (only affect reads).
-- The first 4MB are used for loading the FPGA.
-- For dual ouptut: readcmd => 16#3B#, dualoutput => 1
spimctrl1 : spimctrl
generic map (hindex => 7, hirq => 7, faddr => 16#000#, fmask => 16#ff0#,
ioaddr => 16#700#, iomask => 16#fff#, spliten => CFG_SPLIT,
sdcard => CFG_SPIMCTRL_SDCARD, readcmd => CFG_SPIMCTRL_READCMD, dummybyte => CFG_SPIMCTRL_DUMMYBYTE,
dualoutput => CFG_SPIMCTRL_DUALOUTPUT, scaler => CFG_SPIMCTRL_SCALER, altscaler => CFG_SPIMCTRL_ASCALER)
port map (rstn, clkm, ahbsi, ahbso(7), spmi, spmo);
QspiDB(3) <= '1'; QspiDB(2) <= '1';
-- spi_bdr : iopad generic map (tech => padtech)
-- port map (QspiDB(0), spmo.mosi, spmo.mosioen, spmi.mosi);
spi_mosi_pad : outpad generic map (tech => padtech)
port map (QspiDB(0), spmo.mosi);
spi_miso_pad : inpad generic map (tech => padtech)
port map (QspiDB(1), spmi.miso);
spi_slvsel0_pad : outpad generic map (tech => padtech)
port map (QspiCSn, spmo.csn);
-- MACRO for assigning the SPI output clock
spicclk: STARTUPE2
port map (--CFGCLK => open, CFGMCLK => open, EOS => open, PREQ => open,
CLK => '0', GSR => '0', GTS => '0', KEYCLEARB => '0', PACK => '0',
USRCCLKO => spmo.sck, USRCCLKTS => '0', USRDONEO => '1', USRDONETS => '0' );
--pragma translate_off
QspiClk <= spmo.sck;
--pragma translate_on
end generate;
nospi: if CFG_SPIMCTRL = 0 generate
ahbso(7) <= ahbs_none;
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
-- APB Bridge
apb0 : apbctrl
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
-- Interrupt controller
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
-- Time Unit
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW,
ntimers => CFG_GPT_NTIM, nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti <= gpti_dhalt_drive(dsuo.tstop);
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart, fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd1;
u1i.ctsn <= '0';
u1i.extclk <= '0';
txd1 <= u1o.txd;
-- serrx_pad : inpad generic map (tech => padtech) port map (dsurx, rxd1);
-- sertx_pad : outpad generic map (tech => padtech) port map (dsutx, txd1);
-- led(0) <= not rxd1;
-- led(1) <= not txd1;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm
generic map(hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
pindex => 15, paddr => 15, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, phyrstadr => 1,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G, rmii => 1)
port map(rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG),
apbi => apbi, apbo => apbo(15), ethi => ethi, etho => etho);
eth_rstn<=rstn;
end generate;
etxc_pad : outpad generic map (tech => padtech)
port map (eth_refclk, eth_clk);
ethpads : if (CFG_GRETH = 1) generate
emdio_pad : iopad generic map (tech => padtech)
port map (eth_mdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
ethi.rmii_clk<=eth_clk90;
erxd_pad : inpadv generic map (tech => padtech, width => 2) --8
port map (eth_rxd, ethi.rxd(1 downto 0));
erxer_pad : inpad generic map (tech => padtech)
port map (eth_rxerr, ethi.rx_er);
erxcr_pad : inpad generic map (tech => padtech)
port map (eth_crsdv, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 2)
port map (eth_txd, etho.txd(1 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map (eth_txen, etho.tx_en);
emdc_pad : outpad generic map (tech => padtech)
port map (eth_mdc, etho.mdc);
end generate;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(6) <= ahbs_none;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ahbramgen : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram
generic map (hindex => 3, haddr => CFG_AHBRADDR, tech => CFG_MEMTECH,
kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map (rstn, clkm, ahbsi, ahbso(3));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(3) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- DYNAMIC PARTIAL RECONFIGURATION ---------------------------------
-----------------------------------------------------------------------
prc : if CFG_PRC = 1 generate
p1 : dprc generic map(hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH, pindex => 14, paddr => 14, clk_sel => 1, edac_en => CFG_EDAC_EN, pirq => 14,
technology => CFG_FABTECH, crc_en => CFG_CRC_EN, words_block => CFG_WORDS_BLOCK, fifo_dcm_inst => CFG_DCM_FIFO, fifo_depth => CFG_DPR_FIFO)
port map(rstn => rstn, clkm => clkm, clkraw => '0', clk100 => sys_clk_i, ahbmi => ahbmi, ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH),
apbi => apbi, apbo => apbo(14), rm_reset => rm_reset);
--------------------------------------------------------------------
-- FIR component instantiation (for dprc demo) -------------------
--------------------------------------------------------------------
fir_ex : FIR_AHB_DMA_APB
generic map (hindex=>CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+CFG_PRC, pindex=>13, paddr=>13,
pmask=>16#fff#, technology =>CFG_FABTECH)
port map (rstn=>rstn, clk=>clkm, apbi=>apbi, apbo=>apbo(13), ahbin=>ahbmi,
ahbout=>ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+CFG_PRC), rm_reset => rm_reset(0));
end generate;
-----------------------------------------------------------------------
-- Test report module, only used for simulation ----------------------
-----------------------------------------------------------------------
--pragma translate_off
test0 : ahbrep generic map (hindex => 4, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(4));
--pragma translate_on
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+CFG_PRC*2+1) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Demonstration design for Digilent NEXYS 4 DDR board",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
-----------------------------------------------------------------------
--- Ethernet Clock Generation ---------------------------------------
-----------------------------------------------------------------------
ethclk : if CFG_GRETH = 1 generate
-- 50 MHz clock for output
bufgclk0 : BUFG port map (I => eth_clk_nobuf, O => eth_clk);
-- 50 MHz with +90 deg phase for Rx GRETH
bufgclk45 : BUFG port map (I => eth_clk90_nobuf, O => eth_clk90);
CLKFBIN <= CLKFBOUT;
eth_pll_rst <= not cgi.pllrst;
PLLE2_ADV_inst : PLLE2_ADV generic map (
BANDWIDTH => "OPTIMIZED", -- OPTIMIZED, HIGH, LOW
CLKFBOUT_MULT => 8, -- Multiply value for all CLKOUT, (2-64)
CLKFBOUT_PHASE => 0.0, -- Phase offset in degrees of CLKFB, (-360.000-360.000).
-- CLKIN_PERIOD: Input clock period in nS to ps resolution (i.e. 33.333 is 30 MHz).
CLKIN1_PERIOD => 1000000.0/real(100000.0),
CLKIN2_PERIOD => 0.0,
-- CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for CLKOUT (1-128)
CLKOUT0_DIVIDE => 16,
CLKOUT1_DIVIDE => 16,
CLKOUT2_DIVIDE => 1,
CLKOUT3_DIVIDE => 1,
CLKOUT4_DIVIDE => 1,
CLKOUT5_DIVIDE => 1,
-- CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE: Duty cycle for CLKOUT outputs (0.001-0.999).
CLKOUT0_DUTY_CYCLE => 0.5,
CLKOUT1_DUTY_CYCLE => 0.5,
CLKOUT2_DUTY_CYCLE => 0.5,
CLKOUT3_DUTY_CYCLE => 0.5,
CLKOUT4_DUTY_CYCLE => 0.5,
CLKOUT5_DUTY_CYCLE => 0.5,
-- CLKOUT0_PHASE - CLKOUT5_PHASE: Phase offset for CLKOUT outputs (-360.000-360.000).
CLKOUT0_PHASE => 0.0,
CLKOUT1_PHASE => 90.0,
CLKOUT2_PHASE => 0.0,
CLKOUT3_PHASE => 0.0,
CLKOUT4_PHASE => 0.0,
CLKOUT5_PHASE => 0.0,
COMPENSATION => "ZHOLD", -- ZHOLD, BUF_IN, EXTERNAL, INTERNAL
DIVCLK_DIVIDE => 1, -- Master division value (1-56)
-- REF_JITTER: Reference input jitter in UI (0.000-0.999).
REF_JITTER1 => 0.0,
REF_JITTER2 => 0.0,
STARTUP_WAIT => "TRUE" -- Delay DONE until PLL Locks, ("TRUE"/"FALSE")
)
port map (
-- Clock Outputs: 1-bit (each) output: User configurable clock outputs
CLKOUT0 => eth_clk_nobuf,
CLKOUT1 => eth_clk90_nobuf,
CLKOUT2 => open,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
-- DRP Ports: 16-bit (each) output: Dynamic reconfigration ports
DO => open,
DRDY => open,
-- Feedback Clocks: 1-bit (each) output: Clock feedback ports
CLKFBOUT => CLKFBOUT,
-- Status Ports: 1-bit (each) output: PLL status ports
LOCKED => open,
-- Clock Inputs: 1-bit (each) input: Clock inputs
CLKIN1 => sys_clk_i,
CLKIN2 => '0',
-- Con trol Ports: 1-bit (each) input: PLL control ports
CLKINSEL => '1',
PWRDWN => '0',
RST => eth_pll_rst,
-- DRP Ports: 7-bit (each) input: Dynamic reconfigration ports
DADDR => "0000000",
DCLK => '0',
DEN => '0',
DI => "0000000000000000",
DWE => '0',
-- Feedback Clocks: 1-bit (each) input: Clock feedback ports
CLKFBIN => CLKFBIN
);
end generate;
end rtl;
| gpl-3.0 | 890a95a70250a9e4698b45096c9c3b2b | 0.517659 | 3.696946 | false | false | false | false |
GLADICOS/SPACEWIRESYSTEMC | altera_work/spw_jaxa/jaxa/synthesis/jaxa.vhd | 1 | 59,161 | -- jaxa.vhd
-- Generated using ACDS version 17.1 593
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity jaxa is
port (
autostart_external_connection_export : out std_logic; -- autostart_external_connection.export
clk_clk : in std_logic := '0'; -- clk.clk
controlflagsin_external_connection_export : out std_logic_vector(1 downto 0); -- controlflagsin_external_connection.export
controlflagsout_external_connection_export : in std_logic_vector(1 downto 0) := (others => '0'); -- controlflagsout_external_connection.export
creditcount_external_connection_export : in std_logic_vector(5 downto 0) := (others => '0'); -- creditcount_external_connection.export
errorstatus_external_connection_export : in std_logic_vector(7 downto 0) := (others => '0'); -- errorstatus_external_connection.export
linkdisable_external_connection_export : out std_logic; -- linkdisable_external_connection.export
linkstart_external_connection_export : out std_logic; -- linkstart_external_connection.export
linkstatus_external_connection_export : in std_logic_vector(15 downto 0) := (others => '0'); -- linkstatus_external_connection.export
memory_mem_a : out std_logic_vector(12 downto 0); -- memory.mem_a
memory_mem_ba : out std_logic_vector(2 downto 0); -- .mem_ba
memory_mem_ck : out std_logic; -- .mem_ck
memory_mem_ck_n : out std_logic; -- .mem_ck_n
memory_mem_cke : out std_logic; -- .mem_cke
memory_mem_cs_n : out std_logic; -- .mem_cs_n
memory_mem_ras_n : out std_logic; -- .mem_ras_n
memory_mem_cas_n : out std_logic; -- .mem_cas_n
memory_mem_we_n : out std_logic; -- .mem_we_n
memory_mem_reset_n : out std_logic; -- .mem_reset_n
memory_mem_dq : inout std_logic_vector(7 downto 0) := (others => '0'); -- .mem_dq
memory_mem_dqs : inout std_logic := '0'; -- .mem_dqs
memory_mem_dqs_n : inout std_logic := '0'; -- .mem_dqs_n
memory_mem_odt : out std_logic; -- .mem_odt
memory_mem_dm : out std_logic; -- .mem_dm
memory_oct_rzqin : in std_logic := '0'; -- .oct_rzqin
outstandingcount_external_connection_export : in std_logic_vector(5 downto 0) := (others => '0'); -- outstandingcount_external_connection.export
pll_0_outclk0_clk : out std_logic; -- pll_0_outclk0.clk
receiveactivity_external_connection_export : in std_logic := '0'; -- receiveactivity_external_connection.export
receiveclock_external_connection_export : out std_logic; -- receiveclock_external_connection.export
receivefifodatacount_external_connection_export : in std_logic := '0'; -- receivefifodatacount_external_connection.export
receivefifodataout_external_connection_export : in std_logic_vector(8 downto 0) := (others => '0'); -- receivefifodataout_external_connection.export
receivefifoempty_external_connection_export : in std_logic := '0'; -- receivefifoempty_external_connection.export
receivefifofull_external_connection_export : in std_logic := '0'; -- receivefifofull_external_connection.export
receivefiforeadenable_external_connection_export : out std_logic; -- receivefiforeadenable_external_connection.export
spacewiredatain_external_connection_export : out std_logic; -- spacewiredatain_external_connection.export
spacewiredataout_external_connection_export : in std_logic := '0'; -- spacewiredataout_external_connection.export
spacewirestrobein_external_connection_export : out std_logic; -- spacewirestrobein_external_connection.export
spacewirestrobeout_external_connection_export : in std_logic := '0'; -- spacewirestrobeout_external_connection.export
statisticalinformation_0_external_connection_export : in std_logic_vector(31 downto 0) := (others => '0'); -- statisticalinformation_0_external_connection.export
statisticalinformation_1_external_connection_export : in std_logic_vector(31 downto 0) := (others => '0'); -- statisticalinformation_1_external_connection.export
statisticalinformation_2_external_connection_export : in std_logic_vector(31 downto 0) := (others => '0'); -- statisticalinformation_2_external_connection.export
statisticalinformation_3_external_connection_export : in std_logic_vector(31 downto 0) := (others => '0'); -- statisticalinformation_3_external_connection.export
statisticalinformation_4_external_connection_export : in std_logic_vector(31 downto 0) := (others => '0'); -- statisticalinformation_4_external_connection.export
statisticalinformation_5_external_connection_export : in std_logic_vector(31 downto 0) := (others => '0'); -- statisticalinformation_5_external_connection.export
statisticalinformation_6_external_connection_export : in std_logic_vector(31 downto 0) := (others => '0'); -- statisticalinformation_6_external_connection.export
statisticalinformation_7_external_connection_export : in std_logic_vector(31 downto 0) := (others => '0'); -- statisticalinformation_7_external_connection.export
statisticalinformationclear_external_connection_export : out std_logic; -- statisticalinformationclear_external_connection.export
tickin_external_connection_export : out std_logic; -- tickin_external_connection.export
tickout_external_connection_export : in std_logic := '0'; -- tickout_external_connection.export
timein_external_connection_export : out std_logic_vector(5 downto 0); -- timein_external_connection.export
timeout_external_connection_export : in std_logic_vector(5 downto 0) := (others => '0'); -- timeout_external_connection.export
transmitactivity_external_connection_export : in std_logic := '0'; -- transmitactivity_external_connection.export
transmitclock_external_connection_export : out std_logic; -- transmitclock_external_connection.export
transmitclockdividevalue_external_connection_export : out std_logic_vector(5 downto 0); -- transmitclockdividevalue_external_connection.export
transmitfifodatacount_external_connection_export : in std_logic_vector(5 downto 0) := (others => '0'); -- transmitfifodatacount_external_connection.export
transmitfifodatain_external_connection_export : out std_logic_vector(8 downto 0); -- transmitfifodatain_external_connection.export
transmitfifofull_external_connection_export : in std_logic := '0'; -- transmitfifofull_external_connection.export
transmitfifowriteenable_external_connection_export : out std_logic -- transmitfifowriteenable_external_connection.export
);
end entity jaxa;
architecture rtl of jaxa is
component jaxa_autoStart is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
write_n : in std_logic := 'X'; -- write_n
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
chipselect : in std_logic := 'X'; -- chipselect
readdata : out std_logic_vector(31 downto 0); -- readdata
out_port : out std_logic -- export
);
end component jaxa_autoStart;
component jaxa_controlFlagsIn is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
write_n : in std_logic := 'X'; -- write_n
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
chipselect : in std_logic := 'X'; -- chipselect
readdata : out std_logic_vector(31 downto 0); -- readdata
out_port : out std_logic_vector(1 downto 0) -- export
);
end component jaxa_controlFlagsIn;
component jaxa_controlFlagsOut is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
readdata : out std_logic_vector(31 downto 0); -- readdata
in_port : in std_logic_vector(1 downto 0) := (others => 'X') -- export
);
end component jaxa_controlFlagsOut;
component jaxa_creditCount is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
readdata : out std_logic_vector(31 downto 0); -- readdata
in_port : in std_logic_vector(5 downto 0) := (others => 'X') -- export
);
end component jaxa_creditCount;
component jaxa_errorStatus is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
readdata : out std_logic_vector(31 downto 0); -- readdata
in_port : in std_logic_vector(7 downto 0) := (others => 'X') -- export
);
end component jaxa_errorStatus;
component jaxa_hps_0 is
generic (
F2S_Width : integer := 2;
S2F_Width : integer := 2
);
port (
mem_a : out std_logic_vector(12 downto 0); -- mem_a
mem_ba : out std_logic_vector(2 downto 0); -- mem_ba
mem_ck : out std_logic; -- mem_ck
mem_ck_n : out std_logic; -- mem_ck_n
mem_cke : out std_logic; -- mem_cke
mem_cs_n : out std_logic; -- mem_cs_n
mem_ras_n : out std_logic; -- mem_ras_n
mem_cas_n : out std_logic; -- mem_cas_n
mem_we_n : out std_logic; -- mem_we_n
mem_reset_n : out std_logic; -- mem_reset_n
mem_dq : inout std_logic_vector(7 downto 0) := (others => 'X'); -- mem_dq
mem_dqs : inout std_logic := 'X'; -- mem_dqs
mem_dqs_n : inout std_logic := 'X'; -- mem_dqs_n
mem_odt : out std_logic; -- mem_odt
mem_dm : out std_logic; -- mem_dm
oct_rzqin : in std_logic := 'X'; -- oct_rzqin
h2f_rst_n : out std_logic; -- reset_n
h2f_axi_clk : in std_logic := 'X'; -- clk
h2f_AWID : out std_logic_vector(11 downto 0); -- awid
h2f_AWADDR : out std_logic_vector(29 downto 0); -- awaddr
h2f_AWLEN : out std_logic_vector(3 downto 0); -- awlen
h2f_AWSIZE : out std_logic_vector(2 downto 0); -- awsize
h2f_AWBURST : out std_logic_vector(1 downto 0); -- awburst
h2f_AWLOCK : out std_logic_vector(1 downto 0); -- awlock
h2f_AWCACHE : out std_logic_vector(3 downto 0); -- awcache
h2f_AWPROT : out std_logic_vector(2 downto 0); -- awprot
h2f_AWVALID : out std_logic; -- awvalid
h2f_AWREADY : in std_logic := 'X'; -- awready
h2f_WID : out std_logic_vector(11 downto 0); -- wid
h2f_WDATA : out std_logic_vector(31 downto 0); -- wdata
h2f_WSTRB : out std_logic_vector(3 downto 0); -- wstrb
h2f_WLAST : out std_logic; -- wlast
h2f_WVALID : out std_logic; -- wvalid
h2f_WREADY : in std_logic := 'X'; -- wready
h2f_BID : in std_logic_vector(11 downto 0) := (others => 'X'); -- bid
h2f_BRESP : in std_logic_vector(1 downto 0) := (others => 'X'); -- bresp
h2f_BVALID : in std_logic := 'X'; -- bvalid
h2f_BREADY : out std_logic; -- bready
h2f_ARID : out std_logic_vector(11 downto 0); -- arid
h2f_ARADDR : out std_logic_vector(29 downto 0); -- araddr
h2f_ARLEN : out std_logic_vector(3 downto 0); -- arlen
h2f_ARSIZE : out std_logic_vector(2 downto 0); -- arsize
h2f_ARBURST : out std_logic_vector(1 downto 0); -- arburst
h2f_ARLOCK : out std_logic_vector(1 downto 0); -- arlock
h2f_ARCACHE : out std_logic_vector(3 downto 0); -- arcache
h2f_ARPROT : out std_logic_vector(2 downto 0); -- arprot
h2f_ARVALID : out std_logic; -- arvalid
h2f_ARREADY : in std_logic := 'X'; -- arready
h2f_RID : in std_logic_vector(11 downto 0) := (others => 'X'); -- rid
h2f_RDATA : in std_logic_vector(31 downto 0) := (others => 'X'); -- rdata
h2f_RRESP : in std_logic_vector(1 downto 0) := (others => 'X'); -- rresp
h2f_RLAST : in std_logic := 'X'; -- rlast
h2f_RVALID : in std_logic := 'X'; -- rvalid
h2f_RREADY : out std_logic -- rready
);
end component jaxa_hps_0;
component jaxa_linkStatus is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
readdata : out std_logic_vector(31 downto 0); -- readdata
in_port : in std_logic_vector(15 downto 0) := (others => 'X') -- export
);
end component jaxa_linkStatus;
component jaxa_pll_0 is
port (
refclk : in std_logic := 'X'; -- clk
rst : in std_logic := 'X'; -- reset
outclk_0 : out std_logic; -- clk
locked : out std_logic -- export
);
end component jaxa_pll_0;
component jaxa_receiveActivity is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
readdata : out std_logic_vector(31 downto 0); -- readdata
in_port : in std_logic := 'X' -- export
);
end component jaxa_receiveActivity;
component jaxa_receiveFIFODataOut is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
readdata : out std_logic_vector(31 downto 0); -- readdata
in_port : in std_logic_vector(8 downto 0) := (others => 'X') -- export
);
end component jaxa_receiveFIFODataOut;
component jaxa_statisticalInformation_0 is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
readdata : out std_logic_vector(31 downto 0); -- readdata
in_port : in std_logic_vector(31 downto 0) := (others => 'X') -- export
);
end component jaxa_statisticalInformation_0;
component jaxa_timeIn is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
write_n : in std_logic := 'X'; -- write_n
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
chipselect : in std_logic := 'X'; -- chipselect
readdata : out std_logic_vector(31 downto 0); -- readdata
out_port : out std_logic_vector(5 downto 0) -- export
);
end component jaxa_timeIn;
component jaxa_transmitFIFODataIn is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
write_n : in std_logic := 'X'; -- write_n
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
chipselect : in std_logic := 'X'; -- chipselect
readdata : out std_logic_vector(31 downto 0); -- readdata
out_port : out std_logic_vector(8 downto 0) -- export
);
end component jaxa_transmitFIFODataIn;
component altera_reset_controller is
generic (
NUM_RESET_INPUTS : integer := 6;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 0;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := 'X'; -- reset
clk : in std_logic := 'X'; -- clk
reset_out : out std_logic; -- reset
reset_req : out std_logic; -- reset_req
reset_req_in0 : in std_logic := 'X'; -- reset_req
reset_in1 : in std_logic := 'X'; -- reset
reset_req_in1 : in std_logic := 'X'; -- reset_req
reset_in2 : in std_logic := 'X'; -- reset
reset_req_in2 : in std_logic := 'X'; -- reset_req
reset_in3 : in std_logic := 'X'; -- reset
reset_req_in3 : in std_logic := 'X'; -- reset_req
reset_in4 : in std_logic := 'X'; -- reset
reset_req_in4 : in std_logic := 'X'; -- reset_req
reset_in5 : in std_logic := 'X'; -- reset
reset_req_in5 : in std_logic := 'X'; -- reset_req
reset_in6 : in std_logic := 'X'; -- reset
reset_req_in6 : in std_logic := 'X'; -- reset_req
reset_in7 : in std_logic := 'X'; -- reset
reset_req_in7 : in std_logic := 'X'; -- reset_req
reset_in8 : in std_logic := 'X'; -- reset
reset_req_in8 : in std_logic := 'X'; -- reset_req
reset_in9 : in std_logic := 'X'; -- reset
reset_req_in9 : in std_logic := 'X'; -- reset_req
reset_in10 : in std_logic := 'X'; -- reset
reset_req_in10 : in std_logic := 'X'; -- reset_req
reset_in11 : in std_logic := 'X'; -- reset
reset_req_in11 : in std_logic := 'X'; -- reset_req
reset_in12 : in std_logic := 'X'; -- reset
reset_req_in12 : in std_logic := 'X'; -- reset_req
reset_in13 : in std_logic := 'X'; -- reset
reset_req_in13 : in std_logic := 'X'; -- reset_req
reset_in14 : in std_logic := 'X'; -- reset
reset_req_in14 : in std_logic := 'X'; -- reset_req
reset_in15 : in std_logic := 'X'; -- reset
reset_req_in15 : in std_logic := 'X' -- reset_req
);
end component altera_reset_controller;
signal hps_0_h2f_reset_reset : std_logic; -- hps_0:h2f_rst_n -> hps_0_h2f_reset_reset:in
signal rst_controller_reset_out_reset : std_logic; -- rst_controller:reset_out -> rst_controller_reset_out_reset:in
signal hps_0_h2f_reset_reset_ports_inv : std_logic; -- hps_0_h2f_reset_reset:inv -> [pll_0:rst, rst_controller:reset_in0]
signal rst_controller_reset_out_reset_ports_inv : std_logic; -- rst_controller_reset_out_reset:inv -> [autoStart:reset_n, controlFlagsIn:reset_n, controlFlagsOut:reset_n, creditCount:reset_n, errorStatus:reset_n, linkDisable:reset_n, linkStart:reset_n, linkStatus:reset_n, outstandingCount:reset_n, receiveActivity:reset_n, receiveClock:reset_n, receiveFIFODataCount:reset_n, receiveFIFODataOut:reset_n, receiveFIFOEmpty:reset_n, receiveFIFOFull:reset_n, receiveFIFOReadEnable:reset_n, spaceWireDataIn:reset_n, spaceWireDataOut:reset_n, spaceWireStrobeIn:reset_n, spaceWireStrobeOut:reset_n, statisticalInformationClear:reset_n, statisticalInformation_0:reset_n, statisticalInformation_1:reset_n, statisticalInformation_2:reset_n, statisticalInformation_3:reset_n, statisticalInformation_4:reset_n, statisticalInformation_5:reset_n, statisticalInformation_6:reset_n, statisticalInformation_7:reset_n, tickIn:reset_n, tickOut:reset_n, timeIn:reset_n, timeOut:reset_n, transmitActivity:reset_n, transmitClock:reset_n, transmitClockDivideValue:reset_n, transmitFIFODataCount:reset_n, transmitFIFODataIn:reset_n, transmitFIFOFull:reset_n, transmitFIFOWriteEnable:reset_n]
begin
autostart : component jaxa_autoStart
port map (
clk => clk_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
address => open, -- s1.address
write_n => open, -- .write_n
writedata => open, -- .writedata
chipselect => open, -- .chipselect
readdata => open, -- .readdata
out_port => autostart_external_connection_export -- external_connection.export
);
controlflagsin : component jaxa_controlFlagsIn
port map (
clk => clk_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
address => open, -- s1.address
write_n => open, -- .write_n
writedata => open, -- .writedata
chipselect => open, -- .chipselect
readdata => open, -- .readdata
out_port => controlflagsin_external_connection_export -- external_connection.export
);
controlflagsout : component jaxa_controlFlagsOut
port map (
clk => clk_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
address => open, -- s1.address
readdata => open, -- .readdata
in_port => controlflagsout_external_connection_export -- external_connection.export
);
creditcount : component jaxa_creditCount
port map (
clk => clk_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
address => open, -- s1.address
readdata => open, -- .readdata
in_port => creditcount_external_connection_export -- external_connection.export
);
errorstatus : component jaxa_errorStatus
port map (
clk => clk_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
address => open, -- s1.address
readdata => open, -- .readdata
in_port => errorstatus_external_connection_export -- external_connection.export
);
hps_0 : component jaxa_hps_0
generic map (
F2S_Width => 0,
S2F_Width => 1
)
port map (
mem_a => memory_mem_a, -- memory.mem_a
mem_ba => memory_mem_ba, -- .mem_ba
mem_ck => memory_mem_ck, -- .mem_ck
mem_ck_n => memory_mem_ck_n, -- .mem_ck_n
mem_cke => memory_mem_cke, -- .mem_cke
mem_cs_n => memory_mem_cs_n, -- .mem_cs_n
mem_ras_n => memory_mem_ras_n, -- .mem_ras_n
mem_cas_n => memory_mem_cas_n, -- .mem_cas_n
mem_we_n => memory_mem_we_n, -- .mem_we_n
mem_reset_n => memory_mem_reset_n, -- .mem_reset_n
mem_dq => memory_mem_dq, -- .mem_dq
mem_dqs => memory_mem_dqs, -- .mem_dqs
mem_dqs_n => memory_mem_dqs_n, -- .mem_dqs_n
mem_odt => memory_mem_odt, -- .mem_odt
mem_dm => memory_mem_dm, -- .mem_dm
oct_rzqin => memory_oct_rzqin, -- .oct_rzqin
h2f_rst_n => hps_0_h2f_reset_reset, -- h2f_reset.reset_n
h2f_axi_clk => clk_clk, -- h2f_axi_clock.clk
h2f_AWID => open, -- h2f_axi_master.awid
h2f_AWADDR => open, -- .awaddr
h2f_AWLEN => open, -- .awlen
h2f_AWSIZE => open, -- .awsize
h2f_AWBURST => open, -- .awburst
h2f_AWLOCK => open, -- .awlock
h2f_AWCACHE => open, -- .awcache
h2f_AWPROT => open, -- .awprot
h2f_AWVALID => open, -- .awvalid
h2f_AWREADY => open, -- .awready
h2f_WID => open, -- .wid
h2f_WDATA => open, -- .wdata
h2f_WSTRB => open, -- .wstrb
h2f_WLAST => open, -- .wlast
h2f_WVALID => open, -- .wvalid
h2f_WREADY => open, -- .wready
h2f_BID => open, -- .bid
h2f_BRESP => open, -- .bresp
h2f_BVALID => open, -- .bvalid
h2f_BREADY => open, -- .bready
h2f_ARID => open, -- .arid
h2f_ARADDR => open, -- .araddr
h2f_ARLEN => open, -- .arlen
h2f_ARSIZE => open, -- .arsize
h2f_ARBURST => open, -- .arburst
h2f_ARLOCK => open, -- .arlock
h2f_ARCACHE => open, -- .arcache
h2f_ARPROT => open, -- .arprot
h2f_ARVALID => open, -- .arvalid
h2f_ARREADY => open, -- .arready
h2f_RID => open, -- .rid
h2f_RDATA => open, -- .rdata
h2f_RRESP => open, -- .rresp
h2f_RLAST => open, -- .rlast
h2f_RVALID => open, -- .rvalid
h2f_RREADY => open -- .rready
);
linkdisable : component jaxa_autoStart
port map (
clk => clk_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
address => open, -- s1.address
write_n => open, -- .write_n
writedata => open, -- .writedata
chipselect => open, -- .chipselect
readdata => open, -- .readdata
out_port => linkdisable_external_connection_export -- external_connection.export
);
linkstart : component jaxa_autoStart
port map (
clk => clk_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
address => open, -- s1.address
write_n => open, -- .write_n
writedata => open, -- .writedata
chipselect => open, -- .chipselect
readdata => open, -- .readdata
out_port => linkstart_external_connection_export -- external_connection.export
);
linkstatus : component jaxa_linkStatus
port map (
clk => clk_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
address => open, -- s1.address
readdata => open, -- .readdata
in_port => linkstatus_external_connection_export -- external_connection.export
);
outstandingcount : component jaxa_creditCount
port map (
clk => clk_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
address => open, -- s1.address
readdata => open, -- .readdata
in_port => outstandingcount_external_connection_export -- external_connection.export
);
pll_0 : component jaxa_pll_0
port map (
refclk => clk_clk, -- refclk.clk
rst => hps_0_h2f_reset_reset_ports_inv, -- reset.reset
outclk_0 => pll_0_outclk0_clk, -- outclk0.clk
locked => open -- locked.export
);
receiveactivity : component jaxa_receiveActivity
port map (
clk => clk_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
address => open, -- s1.address
readdata => open, -- .readdata
in_port => receiveactivity_external_connection_export -- external_connection.export
);
receiveclock : component jaxa_autoStart
port map (
clk => clk_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
address => open, -- s1.address
write_n => open, -- .write_n
writedata => open, -- .writedata
chipselect => open, -- .chipselect
readdata => open, -- .readdata
out_port => receiveclock_external_connection_export -- external_connection.export
);
receivefifodatacount : component jaxa_receiveActivity
port map (
clk => clk_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
address => open, -- s1.address
readdata => open, -- .readdata
in_port => receivefifodatacount_external_connection_export -- external_connection.export
);
receivefifodataout : component jaxa_receiveFIFODataOut
port map (
clk => clk_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
address => open, -- s1.address
readdata => open, -- .readdata
in_port => receivefifodataout_external_connection_export -- external_connection.export
);
receivefifoempty : component jaxa_receiveActivity
port map (
clk => clk_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
address => open, -- s1.address
readdata => open, -- .readdata
in_port => receivefifoempty_external_connection_export -- external_connection.export
);
receivefifofull : component jaxa_receiveActivity
port map (
clk => clk_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
address => open, -- s1.address
readdata => open, -- .readdata
in_port => receivefifofull_external_connection_export -- external_connection.export
);
receivefiforeadenable : component jaxa_autoStart
port map (
clk => clk_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
address => open, -- s1.address
write_n => open, -- .write_n
writedata => open, -- .writedata
chipselect => open, -- .chipselect
readdata => open, -- .readdata
out_port => receivefiforeadenable_external_connection_export -- external_connection.export
);
spacewiredatain : component jaxa_autoStart
port map (
clk => clk_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
address => open, -- s1.address
write_n => open, -- .write_n
writedata => open, -- .writedata
chipselect => open, -- .chipselect
readdata => open, -- .readdata
out_port => spacewiredatain_external_connection_export -- external_connection.export
);
spacewiredataout : component jaxa_receiveActivity
port map (
clk => clk_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
address => open, -- s1.address
readdata => open, -- .readdata
in_port => spacewiredataout_external_connection_export -- external_connection.export
);
spacewirestrobein : component jaxa_autoStart
port map (
clk => clk_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
address => open, -- s1.address
write_n => open, -- .write_n
writedata => open, -- .writedata
chipselect => open, -- .chipselect
readdata => open, -- .readdata
out_port => spacewirestrobein_external_connection_export -- external_connection.export
);
spacewirestrobeout : component jaxa_receiveActivity
port map (
clk => clk_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
address => open, -- s1.address
readdata => open, -- .readdata
in_port => spacewirestrobeout_external_connection_export -- external_connection.export
);
statisticalinformationclear : component jaxa_autoStart
port map (
clk => clk_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
address => open, -- s1.address
write_n => open, -- .write_n
writedata => open, -- .writedata
chipselect => open, -- .chipselect
readdata => open, -- .readdata
out_port => statisticalinformationclear_external_connection_export -- external_connection.export
);
statisticalinformation_0 : component jaxa_statisticalInformation_0
port map (
clk => clk_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
address => open, -- s1.address
readdata => open, -- .readdata
in_port => statisticalinformation_0_external_connection_export -- external_connection.export
);
statisticalinformation_1 : component jaxa_statisticalInformation_0
port map (
clk => clk_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
address => open, -- s1.address
readdata => open, -- .readdata
in_port => statisticalinformation_1_external_connection_export -- external_connection.export
);
statisticalinformation_2 : component jaxa_statisticalInformation_0
port map (
clk => clk_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
address => open, -- s1.address
readdata => open, -- .readdata
in_port => statisticalinformation_2_external_connection_export -- external_connection.export
);
statisticalinformation_3 : component jaxa_statisticalInformation_0
port map (
clk => clk_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
address => open, -- s1.address
readdata => open, -- .readdata
in_port => statisticalinformation_3_external_connection_export -- external_connection.export
);
statisticalinformation_4 : component jaxa_statisticalInformation_0
port map (
clk => clk_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
address => open, -- s1.address
readdata => open, -- .readdata
in_port => statisticalinformation_4_external_connection_export -- external_connection.export
);
statisticalinformation_5 : component jaxa_statisticalInformation_0
port map (
clk => clk_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
address => open, -- s1.address
readdata => open, -- .readdata
in_port => statisticalinformation_5_external_connection_export -- external_connection.export
);
statisticalinformation_6 : component jaxa_statisticalInformation_0
port map (
clk => clk_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
address => open, -- s1.address
readdata => open, -- .readdata
in_port => statisticalinformation_6_external_connection_export -- external_connection.export
);
statisticalinformation_7 : component jaxa_statisticalInformation_0
port map (
clk => clk_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
address => open, -- s1.address
readdata => open, -- .readdata
in_port => statisticalinformation_7_external_connection_export -- external_connection.export
);
tickin : component jaxa_autoStart
port map (
clk => clk_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
address => open, -- s1.address
write_n => open, -- .write_n
writedata => open, -- .writedata
chipselect => open, -- .chipselect
readdata => open, -- .readdata
out_port => tickin_external_connection_export -- external_connection.export
);
tickout : component jaxa_receiveActivity
port map (
clk => clk_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
address => open, -- s1.address
readdata => open, -- .readdata
in_port => tickout_external_connection_export -- external_connection.export
);
timein : component jaxa_timeIn
port map (
clk => clk_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
address => open, -- s1.address
write_n => open, -- .write_n
writedata => open, -- .writedata
chipselect => open, -- .chipselect
readdata => open, -- .readdata
out_port => timein_external_connection_export -- external_connection.export
);
timeout : component jaxa_creditCount
port map (
clk => clk_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
address => open, -- s1.address
readdata => open, -- .readdata
in_port => timeout_external_connection_export -- external_connection.export
);
transmitactivity : component jaxa_receiveActivity
port map (
clk => clk_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
address => open, -- s1.address
readdata => open, -- .readdata
in_port => transmitactivity_external_connection_export -- external_connection.export
);
transmitclock : component jaxa_autoStart
port map (
clk => clk_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
address => open, -- s1.address
write_n => open, -- .write_n
writedata => open, -- .writedata
chipselect => open, -- .chipselect
readdata => open, -- .readdata
out_port => transmitclock_external_connection_export -- external_connection.export
);
transmitclockdividevalue : component jaxa_timeIn
port map (
clk => clk_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
address => open, -- s1.address
write_n => open, -- .write_n
writedata => open, -- .writedata
chipselect => open, -- .chipselect
readdata => open, -- .readdata
out_port => transmitclockdividevalue_external_connection_export -- external_connection.export
);
transmitfifodatacount : component jaxa_creditCount
port map (
clk => clk_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
address => open, -- s1.address
readdata => open, -- .readdata
in_port => transmitfifodatacount_external_connection_export -- external_connection.export
);
transmitfifodatain : component jaxa_transmitFIFODataIn
port map (
clk => clk_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
address => open, -- s1.address
write_n => open, -- .write_n
writedata => open, -- .writedata
chipselect => open, -- .chipselect
readdata => open, -- .readdata
out_port => transmitfifodatain_external_connection_export -- external_connection.export
);
transmitfifofull : component jaxa_receiveActivity
port map (
clk => clk_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
address => open, -- s1.address
readdata => open, -- .readdata
in_port => transmitfifofull_external_connection_export -- external_connection.export
);
transmitfifowriteenable : component jaxa_autoStart
port map (
clk => clk_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
address => open, -- s1.address
write_n => open, -- .write_n
writedata => open, -- .writedata
chipselect => open, -- .chipselect
readdata => open, -- .readdata
out_port => transmitfifowriteenable_external_connection_export -- external_connection.export
);
rst_controller : component altera_reset_controller
generic map (
NUM_RESET_INPUTS => 1,
OUTPUT_RESET_SYNC_EDGES => "deassert",
SYNC_DEPTH => 2,
RESET_REQUEST_PRESENT => 0,
RESET_REQ_WAIT_TIME => 1,
MIN_RST_ASSERTION_TIME => 3,
RESET_REQ_EARLY_DSRT_TIME => 1,
USE_RESET_REQUEST_IN0 => 0,
USE_RESET_REQUEST_IN1 => 0,
USE_RESET_REQUEST_IN2 => 0,
USE_RESET_REQUEST_IN3 => 0,
USE_RESET_REQUEST_IN4 => 0,
USE_RESET_REQUEST_IN5 => 0,
USE_RESET_REQUEST_IN6 => 0,
USE_RESET_REQUEST_IN7 => 0,
USE_RESET_REQUEST_IN8 => 0,
USE_RESET_REQUEST_IN9 => 0,
USE_RESET_REQUEST_IN10 => 0,
USE_RESET_REQUEST_IN11 => 0,
USE_RESET_REQUEST_IN12 => 0,
USE_RESET_REQUEST_IN13 => 0,
USE_RESET_REQUEST_IN14 => 0,
USE_RESET_REQUEST_IN15 => 0,
ADAPT_RESET_REQUEST => 0
)
port map (
reset_in0 => hps_0_h2f_reset_reset_ports_inv, -- reset_in0.reset
clk => clk_clk, -- clk.clk
reset_out => rst_controller_reset_out_reset, -- reset_out.reset
reset_req => open, -- (terminated)
reset_req_in0 => '0', -- (terminated)
reset_in1 => '0', -- (terminated)
reset_req_in1 => '0', -- (terminated)
reset_in2 => '0', -- (terminated)
reset_req_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_req_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_req_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_req_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_req_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_req_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_req_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_req_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_req_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_req_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_req_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_req_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_req_in14 => '0', -- (terminated)
reset_in15 => '0', -- (terminated)
reset_req_in15 => '0' -- (terminated)
);
hps_0_h2f_reset_reset_ports_inv <= not hps_0_h2f_reset_reset;
rst_controller_reset_out_reset_ports_inv <= not rst_controller_reset_out_reset;
end architecture rtl; -- of jaxa
| gpl-3.0 | 70a7ed3dd1f5b3386f5e58e3b5b21c12 | 0.428035 | 4.181876 | false | false | false | false |
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